verilator-5.042/0000755000542200017500000000000015101701376014112 5ustar mahmoudyfreeshellverilator-5.042/CITATION.cff0000644000542200017500000000144015101701376016003 0ustar mahmoudyfreeshell# See https://citation-file-format.github.io/ cff-version: 1.2.0 title: Verilator message: >- If you use this software, please cite it using the metadata from this file. type: software authors: - given-names: Wilson family-names: Snyder email: wsnyder@wsnyder.org affiliation: Veripool - given-names: Paul family-names: Wasson - given-names: Duane family-names: Galbi - name: 'et al' repository-code: 'https://github.com/verilator/verilator' url: 'https://verilator.org' abstract: >- The Verilator package converts Verilog and SystemVerilog hardware description language (HDL) designs into a fast C++ or SystemC model that, after compiling, can be executed. Verilator is not a traditional simulator but a compiler. license: - LGPL-3.0-only - Artistic-2.0 verilator-5.042/ci/0000755000542200017500000000000015101701376014505 5ustar mahmoudyfreeshellverilator-5.042/ci/docker/0000755000542200017500000000000015101701376015754 5ustar mahmoudyfreeshellverilator-5.042/ci/docker/buildenv/0000755000542200017500000000000015101701376017564 5ustar mahmoudyfreeshellverilator-5.042/ci/docker/buildenv/build.sh0000755000542200017500000000117215101701376021223 0ustar mahmoudyfreeshell#!/bin/bash -e # DESCRIPTION: Build Verilator (inside container) # # Copyright 2020 by Stefan Wallentowitz. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 : "${REPO:=https://github.com/verilator/verilator}" : "${REV:=master}" : "${CXX:=g++}" SRCS=$PWD/verilator git clone "$REPO" "$SRCS" cd "$SRCS" git checkout "$REV" autoconf ./configure --enable-longtests make -j $(nproc) if [ "${1:-''}" == "test" ]; then make test fi verilator-5.042/ci/docker/buildenv/README.rst0000644000542200017500000000354215101701376021257 0ustar mahmoudyfreeshell.. Copyright 2003-2025 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 .. _Verilator Build Docker Container: Verilator Build Docker Container ================================ This Verilator Build Docker Container is set up to compile and test a Verilator build. It uses the following parameters: - Source repository (default: https://github.com/verilator/verilator) - Source revision (default: master) - Compiler (GCC 13.3.0, clang 18.1.3, default: 13.3.0) The container is published as ``verilator/verilator-buildenv`` on `docker hub `__. To run the basic build using the current Verilator master: :: docker run -ti verilator/verilator-buildenv To also run tests: :: docker run -ti verilator/verilator-buildenv test To change the compiler use the `-e` switch to pass environment variables: :: docker run -ti -e CXX=clang++-18 verilator/verilator-buildenv test The tests, that involve numactl are not working due to security restrictions. To run those too, add the CAP_SYS_NICE capability during the start of the container: :: docker run -ti --cap-add=CAP_SYS_NICE verilator/verilator-buildenv test Rather then building using a remote git repository you may prefer to use a working copy on the local filesystem. Mount the local working copy path as a volume and use that in place of git. When doing this be careful to have all changes committed to the local git area. To build the current HEAD from top of a repository: :: docker run -ti -v ${PWD}:/tmp/repo -e REPO=/tmp/repo -e REV=`git rev-parse --short HEAD` verilator/verilator-buildenv test Rebuilding ---------- To rebuild the Verilator-buildenv docker image, run: :: docker build . This will also build SystemC under all supported compiler variants to reduce the SystemC testing time. verilator-5.042/ci/docker/buildenv/Dockerfile0000644000542200017500000000415415101701376021562 0ustar mahmoudyfreeshell# DESCRIPTION: Dockerfile for env to build and fully test Verilator # # Copyright 2020 by Stefan Wallentowitz. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 FROM ubuntu:24.04 # Create the user RUN groupadd verilator \ && useradd -g verilator -m verilator -s /bin/bash \ && apt-get update \ && apt-get install --no-install-recommends -y sudo \ && apt-get clean \ && rm -rf /var/lib/apt/lists/* \ && echo verilator ALL=\(root\) NOPASSWD:ALL > /etc/sudoers.d/verilator \ && chmod 0440 /etc/sudoers.d/verilator RUN apt-get update \ && DEBIAN_FRONTEND=noninteractive \ apt-get install --no-install-recommends -y \ autoconf \ bc \ bison \ build-essential \ ca-certificates \ ccache \ clang \ cmake \ flex \ gdb \ git \ gtkwave \ help2man \ libfl2 \ libfl-dev \ libclang-rt-18-dev \ libgoogle-perftools-dev \ libsystemc \ libsystemc-dev \ numactl \ perl \ python3 \ python3-distro \ wget \ z3 \ zlib1g \ zlib1g-dev \ && apt-get clean \ && rm -rf /var/lib/apt/lists/* WORKDIR /tmp RUN git clone https://github.com/veripool/vcddiff.git && \ make -C vcddiff && \ cp -p vcddiff/vcddiff /usr/local/bin/vcddiff && \ rm -rf vcddiff COPY build.sh /tmp/build.sh ENV VERILATOR_AUTHOR_SITE=1 USER verilator WORKDIR /work ENTRYPOINT [ "/tmp/build.sh" ] verilator-5.042/ci/docker/run/0000755000542200017500000000000015101701376016560 5ustar mahmoudyfreeshellverilator-5.042/ci/docker/run/verilator-wrap.sh0000755000542200017500000000206615101701376022101 0ustar mahmoudyfreeshell#!/bin/bash # DESCRIPTION: Wrap a Verilator call and copy vlt includes # (inside docker container) # # Copyright 2020 by Stefan Wallentowitz. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 perl /usr/local/bin/verilator "$@" status=$? if [ $status -ne 0 ]; then exit $status fi # Check if user set an obj_dir obj_dir=$(echo " $@" | grep -oP '\s--Mdir\s*\K\S+') if [ "$obj_dir" == "" ]; then obj_dir="obj_dir" fi # If the run was successful: Copy required files to allow build without this container if [ -e ${obj_dir} ]; then # Copy files required for the build mkdir -p ${obj_dir}/vlt cp -r /usr/local/share/verilator/bin ${obj_dir}/vlt cp -r /usr/local/share/verilator/include ${obj_dir}/vlt # Point Makefile to that folder sed -i 's/VERILATOR_ROOT = \/usr\/local\/share\/verilator/VERILATOR_ROOT = vlt/g' ${obj_dir}/*.mk fi verilator-5.042/ci/docker/run/hooks/0000755000542200017500000000000015101701376017703 5ustar mahmoudyfreeshellverilator-5.042/ci/docker/run/hooks/post_push0000755000542200017500000000076215101701376021662 0ustar mahmoudyfreeshell#!/bin/bash # DESCRIPTION: Docker hub hook to tag the latest release (stable) # # Copyright 2020 by Stefan Wallentowitz. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 if [ "$SOURCE_BRANCH"="stable" ]; then docker tag $IMAGE_NAME $DOCKER_REPO:latest docker push $DOCKER_REPO:latest fi verilator-5.042/ci/docker/run/hooks/build0000644000542200017500000000070515101701376020727 0ustar mahmoudyfreeshell#!/bin/bash # DESCRIPTION: Docker hub hook to pass SOURCE_COMMIT # # Copyright 2020 by Stefan Wallentowitz. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 docker build --build-arg SOURCE_COMMIT=${SOURCE_COMMIT} -f $DOCKERFILE_PATH -t $IMAGE_NAME . verilator-5.042/ci/docker/run/verilator-docker0000755000542200017500000000077015101701376021766 0ustar mahmoudyfreeshell#!/bin/bash # DESCRIPTION: Wrap a verilator call to run a docker container # # Copyright 2020 by Stefan Wallentowitz. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 docker pull verilator/verilator:$1 >/dev/null docker run -ti -v ${PWD}:/work --user $(id -u):$(id -g) verilator/verilator:$1 "${@:2}" verilator-5.042/ci/docker/run/README.rst0000644000542200017500000000436315101701376020255 0ustar mahmoudyfreeshell.. Copyright 2003-2025 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 Verilator Executable Docker Container ===================================== The Verilator Executable Docker Container allows you to run Verilator easily as a docker image, e.g.: :: docker run -ti verilator/verilator:latest --version This will pull the container from `docker hub `_, run the latest Verilator and print Verilator's version. Containers are automatically built and pushed to docker hub for all released versions, so you may easily compare results across versions, e.g.: :: docker run -ti verilator/verilator:4.030 --version Verilator needs to read and write files on the local system. To simplify this process, use the ``verilator-docker`` convenience script. This script takes the version number, and all remaining arguments are passed through to Verilator. e.g.: :: ./verilator-docker 4.030 --version or :: ./verilator-docker 4.030 --cc test.v If you prefer not to use ``verilator-docker`` you must give the container access to your files as a volume with appropriate user rights. For example to Verilate test.v: :: docker run -ti -v ${PWD}:/work --user $(id -u):$(id -g) verilator/verilator:latest --cc test.v This method can only access files below the current directory. An alternative is setup the volume ``-workdir``. You can also work in the container by setting the entrypoint (don't forget to mount a volume if you want your work persistent): :: docker run -ti --entrypoint /bin/bash verilator/verilator:latest You can also use the container to build Verilator at a specific commit: :: docker build --build-arg SOURCE_COMMIT= . Internals --------- The Dockerfile builds Verilator and removes the tree when completed to reduce the image size. The entrypoint is a wrapper script (``verilator-wrap.sh``). That script 1. calls Verilator, and 2. copies the Verilated runtime files to the ``obj_dir`` or the ``-Mdir`` respectively. This allows the user to have the files to they may later build the C++ output with the matching runtime files. The wrapper also patches the Verilated Makefile accordingly. A hook is also defined and run by Docker Hub via automated builds. verilator-5.042/ci/docker/run/Dockerfile0000644000542200017500000000334515101701376020557 0ustar mahmoudyfreeshell# DESCRIPTION: Dockerfile for image to run Verilator inside # # Copyright 2020 by Stefan Wallentowitz. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 FROM ubuntu:24.04 RUN apt-get update \ && DEBIAN_FRONTEND=noninteractive \ && apt-get install --no-install-recommends -y \ autoconf \ bc \ bison \ build-essential \ ca-certificates \ ccache \ flex \ git \ help2man \ libfl2 \ libfl-dev \ libgoogle-perftools-dev \ numactl \ perl \ perl-doc \ python3 \ zlib1g \ zlib1g-dev \ && apt-get clean \ && rm -rf /var/lib/apt/lists/* ARG REPO=https://github.com/verilator/verilator ARG SOURCE_COMMIT=master WORKDIR /tmp # Add an exception for the linter, we want to cd here in one layer # to reduce the number of layers (and thereby size). # hadolint ignore=DL3003 RUN git clone "${REPO}" verilator && \ cd verilator && \ git checkout "${SOURCE_COMMIT}" && \ autoconf && \ ./configure && \ make && \ make install && \ cd .. && \ rm -r verilator && \ ccache -C COPY verilator-wrap.sh /usr/local/bin/verilator-wrap.sh WORKDIR /work ENTRYPOINT [ "/usr/local/bin/verilator-wrap.sh" ] verilator-5.042/ci/ci-pages.bash0000755000542200017500000001315515101701376017044 0ustar mahmoudyfreeshell#!/usr/bin/env bash # DESCRIPTION: Verilator: CI script for 'pages.yml', builds the GitHub Pages # # Copyright 2025 by Geza Lore. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # This scipt build the content of the GitHub Pages for the repository. # Currently this only hosts code coverage reports, but it would be possible to # add any other contents to the page in parallel here. # Developer note: You should be able to run this script in your local checkout # if you have GitHub CLI (command 'gh') setup, authenticated ('gh auth login'), # and have set a default repository ('gh repo set-default'). # Create pages root directory. The contents of this directory will be deployed # and served via GitHubPages readonly PAGES_ROOT=pages mkdir -p ${PAGES_ROOT} # Get the current repo URL - might differ on a fork readonly REPO_URL=$(gh repo view --json url --jq .url) # Set GITHUB_OUTPUT when run locally for testing if [[ -z "$GITHUB_OUTPUT" ]]; then GITHUB_OUTPUT=github-output.txt fi # Populates ${PAGES_ROOT}/coverage-reports compile_coverage_reports() { # We will process all runs up to and including this date. This is chosen to be # slightly less than the artifact retention period for simplicity. local OLDEST=$(date --date="28 days ago" --iso-8601=date) # Gather all coverage workflow runs within the time window gh run list -w coverage.yml --limit 1000 --created ">=${OLDEST}" --json "databaseId,event,status,conclusion,createdAt,number" > recentRuns.json echo @@@ Recent runs: jq "." recentRuns.json # Select completd runs that were not cancelled or skipped, sort by descending run number jq 'sort_by(-.number) | map(select(.status == "completed" and (.conclusion == "success" or .conclusion == "failure")))' recentRuns.json > completedRuns.json echo @@@ Completed with success or failure: jq "." completedRuns.json # Create artifacts root directory local ARTIFACTS_ROOT=artifacts mkdir -p ${ARTIFACTS_ROOT} # Create coverage reports root directory local COVERAGE_ROOT=${PAGES_ROOT}/coverage-reports mkdir -p ${COVERAGE_ROOT} # Create index page contents fragment local CONTENTS=contents.tmp echo > ${CONTENTS} # Run IDs of PR jobs processed local PR_RUN_IDS="" # Iterate over all unique event types that triggered the workflows for EVENT in $(jq -r 'map(.event) | sort | unique | .[]' completedRuns.json); do echo "@@@ Processing '${EVENT}' runs" # Emit section header if a report exists with this event type EMIT_SECTION_HEADER=1 # For each worfklow run that was triggered by this event type for RUN_ID in $(jq ".[] | select(.event == \"${EVENT}\") |.databaseId" completedRuns.json); do echo "@@@ Processing run ${RUN_ID}" # Extract the info of this run jq ".[] | select(.databaseId == $RUN_ID)" completedRuns.json > workflow.json jq "." workflow.json # Record run ID of PR job if [[ $EVENT == "pull_request" ]]; then if [[ -z "$PR_RUN_IDS" ]]; then PR_RUN_IDS="$RUN_ID" else PR_RUN_IDS="$PR_RUN_IDS,$RUN_ID" fi fi # Create workflow artifacts directory local ARTIFACTS_DIR=${ARTIFACTS_ROOT}/${RUN_ID} mkdir -p ${ARTIFACTS_DIR} # Download artifacts of this run, if exists gh run download ${RUN_ID} --name coverage-report --dir ${ARTIFACTS_DIR} || true ls -lsha ${ARTIFACTS_DIR} # Move on if no coverage report is available if [ ! -d ${ARTIFACTS_DIR}/report ]; then echo "No coverage report found" continue fi echo "Coverage report found" # Emit section header if [[ -n $EMIT_SECTION_HEADER ]]; then unset EMIT_SECTION_HEADER if [[ $EVENT == "pull_request" ]]; then echo "

Patch coverage reports for '${EVENT}' runs:

" >> ${CONTENTS} else echo "

Code coverage reports for '${EVENT}' runs:

" >> ${CONTENTS} fi fi # Create pages subdirectory mv ${ARTIFACTS_DIR}/report ${COVERAGE_ROOT}/${RUN_ID} # Add index page content local WORKFLOW_CREATED=$(jq -r '.createdAt' workflow.json) local WOFKRLOW_NUMBER=$(jq -r '.number' workflow.json) cat >> ${CONTENTS} <#${WOFKRLOW_NUMBER} | GitHub: ${RUN_ID} | started at: ${WORKFLOW_CREATED} CONTENTS_TEMPLATE if [ -e ${ARTIFACTS_DIR}/pr-number.txt ]; then local PRNUMBER=$(cat ${ARTIFACTS_DIR}/pr-number.txt) echo " | Pull request: #${PRNUMBER}" >> ${CONTENTS} fi echo "
" >> ${CONTENTS} done # Section break if [[ -z "$EMIT_SECTION_HEADER" ]]; then echo "
" >> ${CONTENTS} fi done # Write coverage report index.html cat > ${COVERAGE_ROOT}/index.html < Verilator CI coverage reports $(cat ${CONTENTS})

Assembled $(date --iso-8601=minutes --utc)

INDEX_TEMPLATE # Report size du -shc ${COVERAGE_ROOT}/* # Set output echo "coverage-pr-run-ids=${PR_RUN_IDS}" >> $GITHUB_OUTPUT } # Compilie coverage reports compile_coverage_reports; # You can build any other content here to be put under ${PAGES_ROOT} verilator-5.042/ci/ci-pages-notify.bash0000755000542200017500000000310715101701376020346 0ustar mahmoudyfreeshell#!/usr/bin/env bash # DESCRIPTION: Verilator: CI script for 'pages.yml', notifies PRs # # Copyright 2025 by Geza Lore. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Notify PRs via comment that their coverage reports are available # Get the current repo URL - might differ on a fork readonly REPO_URL=$(gh repo view --json url --jq .url) # Create artifacts root directory ARTIFACTS_ROOT=artifacts mkdir -p ${ARTIFACTS_ROOT} for RUN_ID in ${COVERAGE_PR_RUN_IDS//,/ }; do echo "@@@ Processing run ${RUN_ID}" # Create workflow artifacts directory ARTIFACTS_DIR=${ARTIFACTS_ROOT}/${RUN_ID} mkdir -p ${ARTIFACTS_DIR} # Download artifact of this run, if exists gh run download ${RUN_ID} --name coverage-pr-notification --dir ${ARTIFACTS_DIR} || true ls -lsha ${ARTIFACTS_DIR} # Move on if no notification is required if [ ! -f ${ARTIFACTS_DIR}/pr-number.txt ]; then echo "No notification found" continue fi echo "Posting notification found" cat ${ARTIFACTS_DIR}/body.txt gh pr comment $(cat ${ARTIFACTS_DIR}/pr-number.txt) --body-file ${ARTIFACTS_DIR}/body.txt # Get the artifact ID ARTIFACT_ID=$(gh api "repos/{owner}/{repo}/actions/runs/${RUN_ID}/artifacts" --jq '.artifacts[] | select(.name == "coverage-pr-notification") | .id') # Delete it, so we only notify once gh api --method DELETE "repos/{owner}/{repo}/actions/artifacts/${ARTIFACT_ID}" done verilator-5.042/ci/ci-win-test.ps10000644000542200017500000000127215101701376017277 0ustar mahmoudyfreeshell# DESCRIPTION: Verilator: CI Windows Power Shell - Verilate a test # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ################################################################################ Set-PSDebug -Trace 1 cd install $Env:VERILATOR_ROOT=$PWD cd examples/cmake_tracing_c mkdir build cd build cmake .. cmake --build . --config Release -j 3 # TODO put this back in, see issue# 5163 # Release/example.exe cd .. Remove-Item -path build -recurse verilator-5.042/ci/ci-script.bash0000755000542200017500000001624015101701376017247 0ustar mahmoudyfreeshell#!/usr/bin/env bash # DESCRIPTION: Verilator: CI main job script # # Copyright 2020 by Geza Lore. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ################################################################################ # This is the main script executed in the 'script' phase by all jobs. We use a # single script to keep the CI setting simple. We pass job parameters via # environment variables using 'env' keys. ################################################################################ set -e set -x fatal() { echo "ERROR: $(basename "$0"): $1" >&2; exit 1; } if [ "$CI_OS_NAME" = "linux" ]; then export MAKE=make NPROC=$(nproc) elif [ "$CI_OS_NAME" = "osx" ]; then export MAKE=make NPROC=$(sysctl -n hw.logicalcpu) # Disable ccache, doesn't always work in GitHub Actions export OBJCACHE= elif [ "$CI_OS_NAME" = "freebsd" ]; then export MAKE=gmake NPROC=$(sysctl -n hw.ncpu) else fatal "Unknown os: '$CI_OS_NAME'" fi NPROC=$(expr $NPROC '+' 1) if [ "$CI_BUILD_STAGE_NAME" = "build" ]; then ############################################################################## # Build verilator autoconf CONFIGURE_ARGS="--enable-longtests --enable-ccwarn" if [ "$CI_DEV_ASAN" = 1 ]; then CONFIGURE_ARGS="$CONFIGURE_ARGS --enable-dev-asan" CXX="$CXX -DVL_LEAK_CHECKS" fi if [ "$CI_DEV_GCOV" = 1 ]; then CONFIGURE_ARGS="$CONFIGURE_ARGS --enable-dev-gcov" fi ./configure $CONFIGURE_ARGS --prefix="$INSTALL_DIR" ccache -z "$MAKE" -j "$NPROC" -k # 22.04: ccache -s -v ccache -s if [ "$CI_OS_NAME" = "osx" ]; then file bin/verilator_bin file bin/verilator_bin_dbg md5 bin/verilator_bin md5 bin/verilator_bin_dbg stat bin/verilator_bin stat bin/verilator_bin_dbg fi elif [ "$CI_BUILD_STAGE_NAME" = "test" ]; then ############################################################################## # Run tests export VERILATOR_TEST_NO_CONTRIBUTORS=1 # Separate workflow check export VERILATOR_TEST_NO_LINT_PY=1 # Separate workflow check if [ "$CI_OS_NAME" = "osx" ]; then export VERILATOR_TEST_NO_GDB=1 # Pain to get GDB to work on OS X # TODO below may no longer be required as configure checks for -pg export VERILATOR_TEST_NO_GPROF=1 # Apple Clang has no -pg # export PATH="/Applications/gtkwave.app/Contents/Resources/bin:$PATH" # fst2vcd file bin/verilator_bin file bin/verilator_bin_dbg md5 bin/verilator_bin md5 bin/verilator_bin_dbg stat bin/verilator_bin stat bin/verilator_bin_dbg # For some reason, the dbg exe is corrupted by this point ('file' reports # it as data rather than a Mach-O). Unclear if this is an OS X issue or # CI's. Remove the file and re-link... rm bin/verilator_bin_dbg "$MAKE" -j "$NPROC" -k elif [ "$CI_OS_NAME" = "freebsd" ]; then export VERILATOR_TEST_NO_GDB=1 # Disable for now, ideally should run # TODO below may no longer be required as configure checks for -pg export VERILATOR_TEST_NO_GPROF=1 # gprof is a bit different on FreeBSD, disable fi TEST_REGRESS=test_regress if [ "$CI_RELOC" == 1 ]; then # Testing that the installation is relocatable. "$MAKE" install mkdir -p "$RELOC_DIR" mv "$INSTALL_DIR" "$RELOC_DIR/relocated-install" export VERILATOR_ROOT="$RELOC_DIR/relocated-install/share/verilator" TEST_REGRESS="$RELOC_DIR/test_regress" mv test_regress "$TEST_REGRESS" NODIST="$RELOC_DIR/nodist" mv nodist "$NODIST" # Feeling brave? find . -delete ls -la . fi # Run the specified test ccache -z case $TESTS in dist-vlt-0) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--dist --vlt --driver-clean" DRIVER_HASHSET=--hashset=0/4 ;; dist-vlt-1) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--dist --vlt --driver-clean" DRIVER_HASHSET=--hashset=1/4 ;; dist-vlt-2) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--dist --vlt --driver-clean" DRIVER_HASHSET=--hashset=2/4 ;; dist-vlt-3) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--dist --vlt --driver-clean" DRIVER_HASHSET=--hashset=3/4 ;; vltmt-0) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt --driver-clean" DRIVER_HASHSET=--hashset=0/3 ;; vltmt-1) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt --driver-clean" DRIVER_HASHSET=--hashset=1/3 ;; vltmt-2) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt --driver-clean" DRIVER_HASHSET=--hashset=2/3 ;; coverage-dist) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--dist" ;; coverage-vlt-0) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vlt" DRIVER_HASHSET=--hashset=0/10 ;; coverage-vlt-1) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vlt" DRIVER_HASHSET=--hashset=1/10 ;; coverage-vlt-2) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vlt" DRIVER_HASHSET=--hashset=2/10 ;; coverage-vlt-3) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vlt" DRIVER_HASHSET=--hashset=3/10 ;; coverage-vlt-4) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vlt" DRIVER_HASHSET=--hashset=4/10 ;; coverage-vlt-5) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vlt" DRIVER_HASHSET=--hashset=5/10 ;; coverage-vlt-6) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vlt" DRIVER_HASHSET=--hashset=6/10 ;; coverage-vlt-7) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vlt" DRIVER_HASHSET=--hashset=7/10 ;; coverage-vlt-8) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vlt" DRIVER_HASHSET=--hashset=8/10 ;; coverage-vlt-9) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vlt" DRIVER_HASHSET=--hashset=9/10 ;; coverage-vltmt-0) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt" DRIVER_HASHSET=--hashset=0/10 ;; coverage-vltmt-1) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt" DRIVER_HASHSET=--hashset=1/10 ;; coverage-vltmt-2) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt" DRIVER_HASHSET=--hashset=2/10 ;; coverage-vltmt-3) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt" DRIVER_HASHSET=--hashset=3/10 ;; coverage-vltmt-4) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt" DRIVER_HASHSET=--hashset=4/10 ;; coverage-vltmt-5) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt" DRIVER_HASHSET=--hashset=5/10 ;; coverage-vltmt-6) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt" DRIVER_HASHSET=--hashset=6/10 ;; coverage-vltmt-7) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt" DRIVER_HASHSET=--hashset=7/10 ;; coverage-vltmt-8) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt" DRIVER_HASHSET=--hashset=8/10 ;; coverage-vltmt-9) "$MAKE" -C "$TEST_REGRESS" SCENARIOS="--vltmt" DRIVER_HASHSET=--hashset=9/10 ;; *) fatal "Unknown test: $TESTS" ;; esac # To see load average (1 minute, 5 minute, 15 minute) uptime # 22.04: ccache -s -v ccache -s else ############################################################################## # Unknown build stage fatal "Unknown build stage: '$CI_BUILD_STAGE_NAME'" fi verilator-5.042/ci/ci-win-compile.ps10000644000542200017500000000165215101701376017752 0ustar mahmoudyfreeshell# DESCRIPTION: Verilator: CI Windows Power Shell - Compile Verilator # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ################################################################################ Set-PSDebug -Trace 1 if (-Not (Test-Path $PWD/../.ccache/win_bison.exe)) { git clone --depth 1 https://github.com/lexxmark/winflexbison cd winflexbison mkdir build cd build cmake .. --install-prefix $PWD/../../../.ccache cmake --build . --config Release -j 3 cmake --install . --prefix $PWD/../../../.ccache cd ../.. } mkdir build cd build cmake .. --install-prefix $PWD/../install cmake --build . --config Release -j 3 cmake --install . --prefix $PWD/../install verilator-5.042/ci/ci-install.bash0000755000542200017500000001134315101701376017410 0ustar mahmoudyfreeshell#!/usr/bin/env bash # DESCRIPTION: Verilator: CI dependency install script # # Copyright 2020 by Geza Lore. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ################################################################################ # This script runs in the 'install' phase of all jobs, in all stages. We try to # minimize the time spent in this by selectively installing only the components # required by the particular build stage. ################################################################################ set -e set -x cd $(dirname "$0")/.. # Avoid occasional cpan failures "Issued certificate has expired." export PERL_LWP_SSL_VERIFY_HOSTNAME=0 echo "check_certificate = off" >> ~/.wgetrc fatal() { echo "ERROR: $(basename "$0"): $1" >&2; exit 1; } if [ "$CI_OS_NAME" = "linux" ]; then MAKE=make elif [ "$CI_OS_NAME" = "osx" ]; then MAKE=make elif [ "$CI_OS_NAME" = "freebsd" ]; then MAKE=gmake else fatal "Unknown os: '$CI_OS_NAME'" fi if [ "$CI_OS_NAME" = "linux" ]; then # Avoid slow "processing triggers for man db" echo "path-exclude /usr/share/doc/*" | sudo tee -a /etc/dpkg/dpkg.cfg.d/01_nodoc echo "path-exclude /usr/share/man/*" | sudo tee -a /etc/dpkg/dpkg.cfg.d/01_nodoc echo "path-exclude /usr/share/info/*" | sudo tee -a /etc/dpkg/dpkg.cfg.d/01_nodoc fi install-vcddiff() { TMP_DIR="$(mktemp -d)" git clone https://github.com/veripool/vcddiff "$TMP_DIR" git -C "${TMP_DIR}" checkout dca845020668887fd13498c772939814d9264fd5 "$MAKE" -C "${TMP_DIR}" sudo cp "${TMP_DIR}/vcddiff" /usr/local/bin } if [ "$CI_BUILD_STAGE_NAME" = "build" ]; then ############################################################################## # Dependencies of jobs in the 'build' stage, i.e.: packages required to # build Verilator if [ "$CI_OS_NAME" = "linux" ]; then sudo apt-get update || sudo apt-get update sudo apt-get install ccache help2man libfl-dev || sudo apt-get install ccache help2man libfl-dev if [[ ! "$CI_RUNS_ON" =~ "ubuntu-22.04" ]]; then # Some conflict of libunwind verison on 22.04, can live without it for now sudo apt-get install libgoogle-perftools-dev || sudo apt-get install libgoogle-perftools-dev fi if [[ "$CI_RUNS_ON" =~ "ubuntu-20.04" ]] || [[ "$CI_RUNS_ON" =~ "ubuntu-22.04" ]] || [[ "$CI_RUNS_ON" =~ "ubuntu-24.04" ]]; then sudo apt-get install libsystemc libsystemc-dev || sudo apt-get install libsystemc libsystemc-dev fi if [[ "$CI_RUNS_ON" =~ "ubuntu-22.04" ]] || [[ "$CI_RUNS_ON" =~ "ubuntu-24.04" ]]; then sudo apt-get install bear mold || sudo apt-get install bear mold fi elif [ "$CI_OS_NAME" = "osx" ]; then brew update brew install ccache perl gperftools autoconf bison flex help2man elif [ "$CI_OS_NAME" = "freebsd" ]; then sudo pkg install -y autoconf bison ccache gmake perl5 else fatal "Unknown os: '$CI_OS_NAME'" fi if [ -n "$CCACHE_DIR" ]; then mkdir -p "$CCACHE_DIR" fi elif [ "$CI_BUILD_STAGE_NAME" = "test" ]; then ############################################################################## # Dependencies of jobs in the 'test' stage, i.e.: packages required to # run the tests if [ "$CI_OS_NAME" = "linux" ]; then sudo apt-get update || sudo apt-get update # libfl-dev needed for internal coverage's test runs sudo apt-get install gdb gtkwave lcov libfl-dev ccache jq z3 || sudo apt-get install gdb gtkwave lcov libfl-dev ccache jq z3 # Required for test_regress/t/t_dist_attributes.py if [[ "$CI_RUNS_ON" =~ "ubuntu-22.04" ]] || [[ "$CI_RUNS_ON" =~ "ubuntu-24.04" ]]; then sudo apt-get install python3-clang mold || sudo apt-get install python3-clang mold fi if [[ "$CI_RUNS_ON" =~ "ubuntu-20.04" ]] || [[ "$CI_RUNS_ON" =~ "ubuntu-22.04" ]] || [[ "$CI_RUNS_ON" =~ "ubuntu-24.04" ]]; then sudo apt-get install libsystemc-dev || sudo apt-get install libsystemc-dev fi elif [ "$CI_OS_NAME" = "osx" ]; then brew update # brew cask install gtkwave # fst2vcd hangs at launch, so don't bother brew install ccache perl jq z3 elif [ "$CI_OS_NAME" = "freebsd" ]; then # fst2vcd fails with "Could not open '', exiting." sudo pkg install -y ccache gmake perl5 python3 jq z3 else fatal "Unknown os: '$CI_OS_NAME'" fi # Common installs install-vcddiff # Workaround -fsanitize=address crash sudo sysctl -w vm.mmap_rnd_bits=28 else ############################################################################## # Unknown build stage fatal "Unknown build stage: '$CI_BUILD_STAGE_NAME'" fi verilator-5.042/verilator-config-version.cmake.in0000644000542200017500000000166015101701376022461 0ustar mahmoudyfreeshell###################################################################### # # DESCRIPTION: CMake version configuration file for Verilator # # This allows specifying a minimum Verilator version. # Include it in your CMakeLists.txt using: # # find_package(verilator 4.0) # # Copyright 2003-2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ###################################################################### set(PACKAGE_VERSION "@PACKAGE_VERSION_NUMBER@") if(PACKAGE_VERSION VERSION_LESS PACKAGE_FIND_VERSION) set(PACKAGE_VERSION_COMPATIBLE FALSE) else() set(PACKAGE_VERSION_COMPATIBLE TRUE) if(PACKAGE_FIND_VERSION STREQUAL PACKAGE_VERSION) set(PACKAGE_VERSION_EXACT TRUE) endif() endif() verilator-5.042/configure.ac0000644000542200017500000006443415101701376016413 0ustar mahmoudyfreeshell# DESCRIPTION: Process this file with autoconf to produce a configure script. # # Copyright 2003-2025 by Wilson Snyder. Verilator is free software; you # can redistribute it and/or modify it under the terms of either the GNU Lesser # General Public License Version 3 or the Perl Artistic License Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # When releasing, also update header of Changes file, and CMakeLists.txt, # and commit using "devel release" or "Version bump" message # Then 'make distclean' 'autoconf' './configure' 'make' 'make test' # Then 'make maintainer-dist' #AC_INIT([Verilator],[#.### YYYY-MM-DD]) #AC_INIT([Verilator],[#.### devel]) AC_INIT([Verilator],[5.042 2025-11-02], [https://verilator.org], [verilator],[https://verilator.org]) AC_CONFIG_HEADERS(src/config_package.h) AC_CONFIG_FILES(Makefile src/Makefile src/Makefile_obj include/verilated.mk include/verilated_config.h verilator.pc verilator-config.cmake verilator-config-version.cmake) # Version AC_MSG_RESULT([configuring for $PACKAGE_STRING]) PACKAGE_VERSION_NUMBER=`AS_ECHO("$PACKAGE_VERSION") | sed 's/ .*//g'` AC_SUBST(PACKAGE_VERSION_NUMBER) AC_DEFINE_UNQUOTED([PACKAGE_VERSION_NUMBER_STRING],["$PACKAGE_VERSION_NUMBER"],[Package version as a number]) VERILATOR_VERSION_INTEGER=`AS_ECHO("$PACKAGE_VERSION") | [sed 's/\([0-9]\)\.\([0-9][0-9][0-9]\) .*/\1\2000/g']` AC_SUBST(VERILATOR_VERSION_INTEGER) AC_DEFINE_UNQUOTED([PACKAGE_VERSION_STRING_CHAR], [static const char* const PACKAGE_STRING_UNUSED = "$PACKAGE_STRING";], [Package version as a number]) AC_SUBST(PACKAGE_VERSION_STRING_CHAR) ###################################################################### ## Arguments/flag checking # Ignore automake flags passed by Ubuntu builds AC_ARG_ENABLE([dependency-tracking], [AS_HELP_STRING([--disable-dependency-tracking], [ignored])]) AC_ARG_ENABLE([maintainer-mode], [AS_HELP_STRING([--enable-maintainer-mode], [ignored])]) AC_ARG_ENABLE([silent-rules], [AS_HELP_STRING([--disable-silent-rules], [ignored])]) # Flag to enable linking specific libraries statically AC_MSG_CHECKING(whether to perform partial static linking of Verilator binary) AC_ARG_ENABLE([partial-static], [AS_HELP_STRING([--disable-partial-static], [By default, for Verilation performance, Verilator is linked against some of its dependencies statically. Use this to link the Verilator binary fully dynamically.])], [case "${enableval}" in yes) CFG_ENABLE_PARTIAL_STATIC=yes ;; no) CFG_ENABLE_PARTIAL_STATIC=no ;; *) AC_MSG_ERROR([bad value '${enableval}' for --disable-partial-static]) ;; esac], CFG_ENABLE_PARTIAL_STATIC=yes) AC_MSG_RESULT($CFG_ENABLE_PARTIAL_STATIC) # Flag to enable compiling with AddressSanitizer AC_MSG_CHECKING(whether to use AddressSanitizer) AC_ARG_ENABLE([dev-asan], [AS_HELP_STRING([--enable-dev-asan], [Enable compiling Verilator with ASAN AddressSanitizer for memory error detection. This disables tcmalloc. Does not affect Verilated models using ASAN.])], [case "${enableval}" in yes) CFG_WITH_DEV_ASAN=yes ;; no) CFG_WITH_DEV_ASAN=no ;; *) AC_MSG_ERROR([bad value '${enableval}' for --enable-dev-asan]) ;; esac], CFG_WITH_DEV_ASAN=no) AC_MSG_RESULT($CFG_WITH_DEV_ASAN) # Flag to enable linking Verilator with tcmalloc if available AC_MSG_CHECKING(whether to use tcmalloc) AC_ARG_ENABLE([tcmalloc], [AS_HELP_STRING([--enable-tcmalloc], [Use libtcmalloc_minimal for faster dynamic memory management in Verilator binary @<:@default=check@:>@])], [case "${enableval}" in yes) CFG_WITH_TCMALLOC=yes ;; no) CFG_WITH_TCMALLOC=no ;; *) AC_MSG_ERROR([bad value '${enableval}' for --enable-tcmalloc]) ;; esac], [CFG_WITH_TCMALLOC=check;]) if test "$CFG_WITH_DEV_ASAN" = "yes"; then CFG_WITH_TCMALLOC=no AC_MSG_RESULT("disabled by --enable-dev-asan") else AC_MSG_RESULT($CFG_WITH_TCMALLOC) fi # Flag to enable code coverage build with gcov AC_MSG_CHECKING(whether to build for gcov code coverage collection) AC_ARG_ENABLE([dev-gcov], [AS_HELP_STRING([--enable-dev-gcov], [Build Verilator for code coverage collection with gcov. For developers only.])], [case "${enableval}" in yes) CFG_WITH_DEV_GCOV=yes ;; no) CFG_WITH_DEV_GCOV=no ;; *) AC_MSG_ERROR([bad value '${enableval}' for --enable-dev-gcov]) ;; esac], CFG_WITH_DEV_GCOV=no) AC_SUBST(CFG_WITH_DEV_GCOV) AC_MSG_RESULT($CFG_WITH_DEV_GCOV) # Special Substitutions - CFG_WITH_DEFENV AC_MSG_CHECKING(whether to use hardcoded paths) AC_ARG_ENABLE([defenv], [AS_HELP_STRING([--disable-defenv], [disable using some hardcoded data paths extracted from some default environment variables (the default is to use hardcoded paths) in Verilator binary])], [case "${enableval}" in yes) CFG_WITH_DEFENV=yes ;; no) CFG_WITH_DEFENV=no ;; *) AC_MSG_ERROR([bad value ${enableval} for --disable-defenv]) ;; esac], CFG_WITH_DEFENV=yes) AC_SUBST(CFG_WITH_DEFENV) AC_MSG_RESULT($CFG_WITH_DEFENV) # Special Substitutions - CFG_WITH_CCWARN AC_MSG_CHECKING(whether to show and stop on compilation warnings) AC_ARG_ENABLE([ccwarn], [AS_HELP_STRING([--enable-ccwarn], [enable showing and stopping on compilation warnings in Verilator binary and Verilated makefiles])], [case "${enableval}" in yes) CFG_WITH_CCWARN=yes ;; no) CFG_WITH_CCWARN=no ;; *) AC_MSG_ERROR([bad value ${enableval} for --enable-ccwarn]) ;; esac], [case "x${VERILATOR_AUTHOR_SITE}" in x) CFG_WITH_CCWARN=no ;; *) CFG_WITH_CCWARN=yes ;; esac] ) AC_SUBST(CFG_WITH_CCWARN) AC_MSG_RESULT($CFG_WITH_CCWARN) # Special Substitutions - CFG_WITH_LONGTESTS AC_MSG_CHECKING(whether to run long tests) AC_ARG_ENABLE([longtests], [AS_HELP_STRING([--enable-longtests], [enable running long developer tests])], [case "${enableval}" in yes) CFG_WITH_LONGTESTS=yes ;; no) CFG_WITH_LONGTESTS=no ;; *) AC_MSG_ERROR([bad value ${enableval} for --enable-longtests]) ;; esac], [case "x${VERILATOR_AUTHOR_SITE}" in x) CFG_WITH_LONGTESTS=no ;; *) CFG_WITH_LONGTESTS=yes ;; esac] ) AC_SUBST(CFG_WITH_LONGTESTS) AC_MSG_RESULT($CFG_WITH_LONGTESTS) AC_CHECK_PROG(HAVE_Z3,z3,yes) AC_CHECK_PROG(HAVE_CVC5,cvc5,yes) AC_CHECK_PROG(HAVE_CVC4,cvc4,yes) # Special Substitutions - CFG_WITH_SOLVER AC_MSG_CHECKING(for SMT solver) AC_ARG_WITH([solver], [AS_HELP_STRING([--with-solver='z3 --in'], [set default SMT solver for constrained randomization])], [CFG_WITH_SOLVER="${withval}"], [CFG_WITH_SOLVER=no if test "x$HAVE_Z3" = "xyes"; then CFG_WITH_SOLVER="z3 --in" elif test "x$HAVE_CVC5" = "xyes"; then CFG_WITH_SOLVER="cvc5 --incremental" elif test "x$HAVE_CVC4" = "xyes"; then CFG_WITH_SOLVER="cvc4 --lang=smt2 --incremental" fi] ) AC_SUBST(CFG_WITH_SOLVER) AC_MSG_RESULT($CFG_WITH_SOLVER) ###################################################################### ## Compiler checks AC_MSG_RESULT([compiler CXX inbound is set to... $CXX]) # Compiler flags (ensure they are not empty to avoid configure defaults) CFLAGS="$CFLAGS " CPPFLAGS="$CPPFLAGS " CXXFLAGS="$CXXFLAGS " LDFLAGS="$LDFLAGS " # Checks for programs. AC_PROG_CC AC_PROG_CXX AC_PROG_INSTALL AC_LANG_PUSH(C++) CFG_CXX_VERSION=`$CXX --version | head -1` AC_MSG_RESULT([compiler version... $CXX --version = $CFG_CXX_VERSION]) AC_SUBST(CFG_CXX_VERSION) AC_MSG_CHECKING([that C++ compiler can compile simple program]) AC_RUN_IFELSE( [AC_LANG_SOURCE([int main() { return 0; }])], AC_MSG_RESULT(yes), AC_MSG_RESULT(no);AC_MSG_ERROR([a working C++ compiler is required]), AC_MSG_RESULT(yes)) AC_CHECK_PROG(AR,ar,ar) if test "x$AR" = "x" ; then AC_MSG_ERROR([Cannot find "ar" in your PATH, please install it]) fi AC_CHECK_PROG(PERL,perl,perl) if test "x$PERL" = "x" ; then AC_MSG_ERROR([Cannot find "perl" in your PATH, please install it]) fi AC_CHECK_PROG(PYTHON3,python3,python3) if test "x$PYTHON3" = "x" ; then AC_MSG_ERROR([Cannot find "python3" in your PATH, please install it]) fi python3_version=$($PYTHON3 --version | head -1) AC_MSG_RESULT([$PYTHON3 --version = $python3_version]) AC_CHECK_PROG(LEX,flex,flex) if test "x$LEX" = "x" ; then AC_MSG_ERROR([Cannot find "flex" in your PATH, please install it]) fi flex_version=$($LEX --version | head -1) AC_MSG_RESULT([$LEX --version = $flex_version]) AC_CHECK_PROG(YACC,bison,bison) if test "x$YACC" = "x" ; then AC_MSG_ERROR([Cannot find "bison" in your PATH, please install it]) fi bison_version=$($YACC --version | head -1) AC_MSG_RESULT([$YACC --version = $bison_version]) AC_CHECK_PROG(OBJCACHE,ccache,ccache) if test "x$OBJCACHE" != "x" ; then objcache_version=$($OBJCACHE --version | head -1) AC_MSG_RESULT([objcache is $OBJCACHE --version = $objcache_version]) fi # Checks for libraries. # Checks for typedefs, structures AC_CHECK_TYPE(size_t,unsigned int) AC_TYPE_SIZE_T # Checks for compiler characteristics. AC_C_INLINE AC_LINK_IFELSE( [AC_LANG_PROGRAM([#include ], [[int* a=new int; delete a; ]])], [], [AC_MSG_ERROR([$CXX does not seem to successfully compile a simple C++ program])]) AC_DEFUN([_MY_CXX_CHECK_FLAG], [# _MY_CXX_CHECK_FLAG(flag) -- Check if compiler supports specific options # Set $_my_result appropriately ACO_SAVE_CXXFLAGS="$CXXFLAGS" # -Werror needed otherwise unknown -Wno-div-by-zero won't report problems # new/delete is needed to find -faligned-new link problem on Darwin CXXFLAGS="$CXXFLAGS $1 -Werror" AC_MSG_CHECKING([whether $CXX accepts $1]) AC_LINK_IFELSE( [AC_LANG_PROGRAM([#include ], [[int* a=new int; delete a; ]])], [_my_result=yes if test -s conftest.err; then if grep -e "$1" conftest.err >/dev/null; then _my_result=no fi fi], [_my_result=no]) # GCC is annoying, trying to be helpful, it postpones unknown -Wno- # options if there's no error We want to see them regardless, so try # forcing an error and see if we get a gcc warning AC_COMPILE_IFELSE( [AC_LANG_PROGRAM([[an_error "intentional-error-for-test.h" ]],[])], [], # Ignore ok exit [if test -s conftest.err; then if grep -e "$1" conftest.err >/dev/null; then _my_result=no fi fi]) AC_MSG_RESULT($_my_result) CXXFLAGS="$ACO_SAVE_CXXFLAGS" ]) AC_DEFUN([_MY_CXX_CHECK_IFELSE], [# _MY_CXX_CHECK_IFELSE(option,action-if-supported,action-if-not-supported) # Check if compiler supports specific option. If it does, # do action-if-supported, otherwise do action-if-not-supported _MY_CXX_CHECK_FLAG($1) if test "$_my_result" = "yes" ; then true $2 else true $3 fi ]) AC_DEFUN([_MY_CXX_CHECK_SET], [# _MY_CXX_CHECK_SET(variable,option) # Check if compiler supports specific option. If it does, # set variable to option, only if not previously set. if test "$$1" = ""; then _MY_CXX_CHECK_IFELSE($2, $1="$2") fi ]) AC_DEFUN([_MY_CXX_CHECK_OPT], [# _MY_CXX_CHECK_OPT(variable,option) # Check if compiler supports specific option. If it does, # append option to variable _MY_CXX_CHECK_IFELSE($2, $1="$$1 $2") ]) AC_DEFUN([_MY_CXX_CHECK_CORO_SET], [# _MY_CXX_CHECK_CORO_SET(variable,option) # Check if compiler supports coroutines with specific option. If it does, # set variable to option, only if not previously set. # Define HAVE_COROUTINES if supported. if test "$$1" = ""; then if test "$2" != ""; then _my_msg_opt=" with $2" else _my_msg_opt="" fi AC_MSG_CHECKING([whether coroutines are supported by $CXX$_my_msg_opt]) ACO_SAVE_CXXFLAGS="$CXXFLAGS" CXXFLAGS="$CXXFLAGS $2" AC_LINK_IFELSE( [AC_LANG_PROGRAM([ #if defined(__clang__) && !defined(__cpp_impl_coroutine) #define __cpp_impl_coroutine 1 #endif #include ],[[std::coroutine_handle<> h;]])], [_my_result=yes], [AC_LINK_IFELSE( [AC_LANG_PROGRAM( [#include ], [[std::experimental::coroutine_handle<> h;]])], [_my_result=yes], [_my_result=no])]) AC_MSG_RESULT($_my_result) CXXFLAGS="$ACO_SAVE_CXXFLAGS" if test "$_my_result" = "yes" ; then $1="$2" AC_DEFINE([HAVE_COROUTINES],[1],[Defined if coroutines are supported by $CXX]) fi fi ]) AC_DEFUN([_MY_LDLIBS_CHECK_FLAG], [# _MY_LDLIBS_CHECK_FLAG(flag) -- Check if linker supports specific options # Set $_my_result appropriately ACO_SAVE_LIBS="$LIBS" LIBS="$LIBS $1" AC_MSG_CHECKING([whether $CXX linker accepts $1]) AC_LINK_IFELSE( [AC_LANG_PROGRAM([[]])], [_my_result=yes if test -s conftest.err; then if grep -e "$1" conftest.err >/dev/null; then _my_result=no fi fi], [_my_result=no]) AC_MSG_RESULT($_my_result) LIBS="$ACO_SAVE_LIBS" ]) AC_DEFUN([_MY_LDLIBS_CHECK_IFELSE], [# _MY_LDLIBS_CHECK_IFELSE(flag,action-if-supported,action-if-not-supported) # Check if linker supports specific flag, if it does do action-if-supported # otherwise do action-if-not-supported _MY_LDLIBS_CHECK_FLAG($1) if test "$_my_result" = "yes" ; then true $2 else true $3 fi ]) AC_DEFUN([_MY_LDLIBS_CHECK_OPT], [# _MY_LDLIBS_CHECK_OPT(variable, flag) -- Check if linker supports specific # options. If it does, append flag to variable. _MY_LDLIBS_CHECK_IFELSE($2, $1="$$1 $2") ]) # Add the coverage flags early as they influence later checks. if test "$CFG_WITH_DEV_GCOV" = "yes"; then _MY_CXX_CHECK_OPT(CXX,--coverage) # Otherwise inline may not show as uncovered # If we use this then e.g. verilated.h functions properly show up # if unused. # However, VerilatedSerialize::write then changes from covered # to uncovered (in G++ 9.3.0) even with all inlining turned off. # Having false negative coverage is more effort then missing negatives. # Also this seems to explode the runtime (since a lot more data). # _MY_CXX_CHECK_OPT(CXX,-fkeep-inline-functions) # Otherwise static may not show as uncovered _MY_CXX_CHECK_OPT(CXX,-fkeep-static-functions) # Similarly for inline functions. - This is too slow. See Makefile_obj instead. #_MY_CXX_CHECK_OPT(CXX,-fkeep-inline-functions) # Make sure profiling is thread-safe _MY_CXX_CHECK_OPT(CXX,-fprofile-update=atomic) # Ensure data files can be written from parallel runs _MY_CXX_CHECK_OPT(CXX,-fprofile-reproducible=parallel-runs) # Save source files as absolute paths in gcno files _MY_CXX_CHECK_OPT(CXX,-fprofile-abs-path) # Define so compiled code can know _MY_CXX_CHECK_OPT(CXX,-DVL_GCOV) AC_DEFINE([HAVE_DEV_GCOV],[1],[Defined if compiled with code coverage collection for gcov])] fi AC_SUBST(HAVE_DEV_GCOV) # Compiler flags to enable profiling _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_PROFILE,-pg) AC_SUBST(CFG_CXXFLAGS_PROFILE) # Flag to select newest language standard supported # Macros work such that first option that passes is the one we take # Currently enable c++17/c++14 due to packaged SystemC dependency # c++17 is the newest that Verilator is regularly tested to support # c++14 is the oldest that Verilator supports # gnu is required for Cygwin to compile verilated.h successfully #_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++20) #_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=c++20) _MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++17) _MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=c++17) _MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++14) _MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=c++14) AC_SUBST(CFG_CXXFLAGS_STD_NEWEST) # Flags for compiling Verilator internals including parser, and Verilated files # These turn on extra warnings and are only used with 'configure --enable-ccwarn' _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_WEXTRA,-Wextra) _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_WEXTRA,-Wfloat-conversion) _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_WEXTRA,-Wlogical-op) _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_WEXTRA,-Wthread-safety) AC_SUBST(CFG_CXXFLAGS_WEXTRA) # Flags for coroutine support for dynamic scheduling _MY_CXX_CHECK_CORO_SET(CFG_CXXFLAGS_COROUTINES, "") _MY_CXX_CHECK_CORO_SET(CFG_CXXFLAGS_COROUTINES,-fcoroutines-ts) _MY_CXX_CHECK_CORO_SET(CFG_CXXFLAGS_COROUTINES,-fcoroutines) _MY_CXX_CHECK_CORO_SET(CFG_CXXFLAGS_COROUTINES,-fcoroutines-ts -Wno-deprecated-experimental-coroutine) _MY_CXX_CHECK_CORO_SET(CFG_CXXFLAGS_COROUTINES,-std=gnu++20) AC_SUBST(CFG_CXXFLAGS_COROUTINES) AC_SUBST(HAVE_COROUTINES) # Flags for compiling Verilator internals including parser always if test "$CFG_WITH_DEV_ASAN" = "yes"; then _MY_CXX_CHECK_IFELSE(-fsanitize=address -DVL_ASAN, [CFG_CXXFLAGS_SRC="$CFG_CXXFLAGS_SRC -fsanitize=address -DVL_ASAN" CFG_LDFLAGS_SRC="$CFG_LDFLAGS_SRC -fsanitize=address" AC_DEFINE([HAVE_DEV_ASAN],[1],[Defined if built with AddresSanitizer])] ) fi AC_SUBST(HAVE_DEV_ASAN) _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-Qunused-arguments) _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-Wno-shadow) _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-Wno-unused-parameter) _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-Xclang -fno-pch-timestamp) _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-faligned-new) AC_SUBST(CFG_CXXFLAGS_SRC) # Flags for compiling Verilator parser always (in addition to above CFG_CXXFLAGS_SRC) _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_PARSER,-Wno-char-subscripts) _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_PARSER,-Wno-null-conversion) _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_PARSER,-Wno-parentheses-equality) _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_PARSER,-Wno-unused) AC_SUBST(CFG_CXXFLAGS_PARSER) # Flags for compiling the debug version of Verilator (in addition to above CFG_CXXFLAGS_SRC) if test "$CFG_WITH_DEV_GCOV" = "no"; then # Do not optimize for the coverage build _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_DBG,-Og) fi _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_DBG,-ggdb) _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_DBG,-gz) AC_SUBST(CFG_CXXFLAGS_DBG) # Flags for linking the debug version of Verilator (in addition to above CFG_LDFLAGS_SRC) _MY_LDLIBS_CHECK_OPT(CFG_LDFLAGS_DBG,-gz) AC_SUBST(CFG_LDFLAGS_DBG) # Flags for compiling the optimized version of Verilator (in addition to above CFG_CXXFLAGS_SRC) if test "$CFG_WITH_DEV_GCOV" = "no"; then # Do not optimize for the coverage build _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_OPT,-O3) fi AC_SUBST(CFG_CXXFLAGS_OPT) # Flags for Verilated makefile # For example, -Wno-div-by-zero isn't in 4.1.2 # Random code often does / 0. Unfortunately VL_DIV_I(0,0) will warn # without this flag, even though there's a conditional to prevent the divide. # We still don't add no-div-by-zero as it throws message to stdout, though doesn't die. #_MY_CXX_CHECK_OPT(-Wno-div-by-zero) # For some reason -faligned-new does not work under Travis w/ clang but the # configure test doesn't catch this either AS_IF([test "x$TRAVIS_COMPILER" != xclang], [_MY_CXX_CHECK_OPT(CFG_CXXFLAGS_NO_UNUSED,-faligned-new)]) CFG_CXX_FLAGS_CMAKE="-faligned-new" m4_foreach([cflag],[ [-fbracket-depth=4096], [-fcf-protection=none], [-Xclang -fno-pch-timestamp], [-mno-cet], [-Qunused-arguments], [-Wno-bool-operation], [-Wno-c++11-narrowing], [-Wno-constant-logical-operand], [-Wno-int-in-bool-context], [-Wno-non-pod-varargs], [-Wno-parentheses-equality], [-Wno-shadow], [-Wno-sign-compare], [-Wno-subobject-linkage], [-Wno-tautological-bitwise-compare], [-Wno-tautological-compare], [-Wno-uninitialized], [-Wno-unused-but-set-parameter], [-Wno-unused-but-set-variable], [-Wno-unused-parameter], [-Wno-unused-variable]],[ _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_NO_UNUSED,cflag) # CMake will test what flags work itself, so pass all flags through to it CFG_CXX_FLAGS_CMAKE="$CFG_CXX_FLAGS_CMAKE cflag" ]) AC_SUBST(CFG_CXXFLAGS_NO_UNUSED) AC_SUBST(CFG_CXX_FLAGS_CMAKE) # Find multithread linker flags m4_foreach([ldflag], [ [-mt], [-pthread], [-lpthread], [-latomic]],[ _MY_LDLIBS_CHECK_OPT(CFG_LDLIBS_THREADS,ldflag) # CMake will test what flags work itself, so pass all flags through to it CFG_LDFLAGS_THREADS_CMAKE="$CFG_LDFLAGS_THREADS_CMAKE ldflag" ]) AC_SUBST(CFG_LDLIBS_THREADS) AC_SUBST(CFG_LDFLAGS_THREADS_CMAKE) # If 'mold' is installed, use it to link for faster buildtimes _MY_LDLIBS_CHECK_OPT(CFG_LDFLAGS_SRC, -fuse-ld=mold) _MY_LDLIBS_CHECK_OPT(CFG_LDFLAGS_VERILATED, -fuse-ld=mold) # When linking partially statically if test "$CFG_ENABLE_PARTIAL_STATIC" = "yes"; then _MY_LDLIBS_CHECK_OPT(CFG_LDFLAGS_SRC, -static-libgcc) _MY_LDLIBS_CHECK_OPT(CFG_LDFLAGS_SRC, -static-libstdc++) _MY_LDLIBS_CHECK_OPT(CFG_LDFLAGS_SRC, -Xlinker -gc-sections) LTCMALLOC="-Wl,--whole-archive -l:libtcmalloc_minimal.a -Wl,--no-whole-archive" else LTCMALLOC=-ltcmalloc_minimal fi AC_SUBST(CFG_LDFLAGS_SRC) AC_SUBST(CFG_LDFLAGS_VERILATED) # The pthread library is required by tcmalloc, so add it if it exists. If it # does not, the tcmalloc check below will fail anyway, and linking against # pthreads is harmless otherwise. CFG_LIBS="$LIBS $CFG_LIBS" _MY_LDLIBS_CHECK_OPT(CFG_LIBS, -lpthread) _MY_LDLIBS_CHECK_OPT(CFG_LIBS, -latomic) # Check libraries for MingW _MY_LDLIBS_CHECK_OPT(CFG_LIBS, -lbcrypt) _MY_LDLIBS_CHECK_OPT(CFG_LIBS, -lpsapi) # Check if tcmalloc is available based on --enable-tcmalloc _MY_LDLIBS_CHECK_IFELSE( $LTCMALLOC, [if test "$CFG_WITH_TCMALLOC" != "no"; then CFG_LIBS="$LTCMALLOC $CFG_LIBS"; # If using tcmalloc, add some extra options to make the compiler not assume # it is using its own versions of the standard library functions _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-fno-builtin-malloc) _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-fno-builtin-calloc) _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-fno-builtin-realloc) _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-fno-builtin-free) AC_DEFINE([HAVE_TCMALLOC],[1],[Defined if have tcmalloc]) fi], [if test "$CFG_WITH_TCMALLOC" = "yes"; then AC_MSG_ERROR([--enable-tcmalloc was given but test for ${LTCMALLOC} failed]) fi]) AC_SUBST(HAVE_TCMALLOC) AC_SUBST(CFG_LIBS) # Need C++14 at least #Alternative: AX_CXX_COMPILE_STDCXX([14]) AC_DEFUN([_MY_CXX_CHECK_CXX_VER], [# _MY_CXX_CHECK_CXX_VER(flag) -- Check if compiler runs C++14 # Set $_my_result AC_RUN_IFELSE( [AC_LANG_PROGRAM([#include #if (__cplusplus < 201402L) # error "Too old" #endif ], [[ ]])], [_my_result=yes], [_my_result=no], [_my_result=no]) ]) # Add $CFG_CXXFLAGS_STD only if can't compile correctly otherwise, # as adding std= when not needed can cause errors with the C++ std library. CFG_CXXFLAGS_STD=$CFG_CXXFLAGS_STD_NEWEST AC_MSG_CHECKING(whether $CXX supports C++14) _MY_CXX_CHECK_CXX_VER() AC_MSG_RESULT($_my_result) if test "$_my_result" = "no" ; then CXXFLAGS="$CXXFLAGS $CFG_CXXFLAGS_STD" CFG_CXX_FLAGS_CMAKE="$CFG_CXX_FLAGS_CMAKE $CFG_CXXFLAGS_STD" AC_MSG_CHECKING(whether $CXX supports C++14 with $CFG_CXXFLAGS_STD) _MY_CXX_CHECK_CXX_VER() AC_MSG_RESULT($_my_result) else # CFG_CXXFLAGS_STD is also propagated to include/verilated.mk.in # make sure we use the same std flag while compiling verilator and verilated design CFG_CXXFLAGS_STD="" fi if test "$_my_result" = "no" ; then AC_MSG_NOTICE([[]]) AC_MSG_ERROR([[the $CXX compiler appears to not support C++14. Verilator requires a C++14 or newer compiler.]]) fi AC_SUBST(CFG_CXXFLAGS_STD) # Compiler precompiled header options (assumes either gcc or clang++) AC_MSG_CHECKING([for $CXX precompile header include option]) if $CXX --help | grep include-pch >/dev/null 2>/dev/null ; then # clang CFG_CXXFLAGS_PCH_I=-include-pch CFG_GCH_IF_CLANG=.gch else # GCC CFG_CXXFLAGS_PCH_I=-include CFG_GCH_IF_CLANG= fi AC_MSG_RESULT($CFG_CXXFLAGS_PCH_I) AC_SUBST(CFG_CXXFLAGS_PCH_I) AC_SUBST(CFG_GCH_IF_CLANG) # Checks for library functions. AC_CHECK_MEMBER([struct stat.st_mtim.tv_nsec], [AC_DEFINE([HAVE_STAT_NSEC],[1],[Defined if struct stat has st_mtim.tv_nsec])], [], [#include ]) # HAVE_SYSTEMC # - If found the default search path has it, so support is always enabled. # - If not found or not system-wide, user can set SYSTEMC_INCLUDE. # AC_CHECK_HEADERS seems to not locate on Travis-CI but include does work. AC_MSG_CHECKING([whether SystemC is found (in system path)]) ACO_SAVE_LIBS="$LIBS" LIBS="$LIBS -lsystemc" AC_LINK_IFELSE( [AC_LANG_PROGRAM([[#include extern "C" int sc_main(int argc, char* argv[]) { return 0; } ]],[[sc_version()]])], [_my_result=yes AC_DEFINE([HAVE_SYSTEMC],[1],[Defined if have SystemC library])], [_my_result=no]) AC_MSG_RESULT($_my_result) LIBS="$ACO_SAVE_LIBS" AC_SUBST(HAVE_SYSTEMC) # Checks for system services ###################################################################### ## Output # Other install directories pkgdatadir=${datadir}/verilator AC_SUBST(pkgdatadir) pkgconfigdir=${datadir}/pkgconfig AC_SUBST(pkgconfigdir) AC_OUTPUT AC_MSG_RESULT([]) AC_MSG_RESULT([Now type 'make' (or sometimes 'gmake') to build Verilator.]) AC_MSG_RESULT([]) verilator-5.042/.github/0000755000542200017500000000000015101701376015452 5ustar mahmoudyfreeshellverilator-5.042/.github/labels.toml0000644000542200017500000001173015101701376017613 0ustar mahmoudyfreeshell["area: assertions"] color = "ffffe8" name = "area: assertions" description = "Issue involves assertions" ["area: configure/compiling"] color = "ffffe8" name = "area: configure/compiling" description = "Issue involves configuring or compilating Verilator itself" ["area: coverage"] color = "ffffe8" name = "area: coverage" description = "Issue involves coverage generation" ["area: data-types"] color = "ffffe8" name = "area: data-types" description = "Issue involves data-types" ["area: documentation"] color = "ffffe8" name = "area: documentation" description = "Issue involves documentation" ["area: elaboration"] color = "ffffe8" name = "area: elaboration" description = "Issue involves elaboration phase" ["area: invoking/options"] color = "ffffe8" name = "area: invoking/options" description = "Issue involves options passed to Verilator" ["area: lint"] color = "ffffe8" name = "area: lint" description = "Issue involves SystemVerilog lint checking" ["area: parser"] color = "ffffe8" name = "area: parser" description = "Issue involves SystemVerilog parsing" ["area: performance"] color = "ffffe8" name = "area: performance" description = "Issue involves performance issues" ["area: portability"] color = "ffffe8" name = "area: portability" description = "Issue involves operating system/compiler portability" ["area: runtime result"] color = "ffffe8" name = "area: runtime result" description = "Issue involves an incorrect runtine result from Verilated model" ["area: scheduling"] color = "ffffe8" name = "area: scheduling" description = "Issue involves scheduling/ordering of events" ["area: tests"] color = "ffffe8" name = "area: tests" description = "Issue involves the testing system" ["area: usability"] color = "ffffe8" name = "area: usability" description = "Issue involves general usability" ["effort: days"] color = "d0c0b0" name = "effort: days" description = "Expect this issue to require roughly days of invested effort to resolve" ["effort: hours"] color = "f5e6d6" name = "effort: hours" description = "Expect this issue to require roughly hours of invested effort to resolve" ["effort: minutes"] color = "f5e6d6" name = "effort: minutes" description = "Expect this issue to require less than an hour of invested effort to resolve" ["effort: weeks"] color = "d0c0b0" name = "effort: weeks" description = "Expect this issue to require weeks or more of invested effort to resolve" ["good first issue"] color = "7057ff" name = "good first issue" description = "Good for newcomers" ["help wanted"] color = "008672" name = "help wanted" description = "Extra attention is needed" ["new"] color = "ff4400" name = "new" description = "New issue, not yet seen by maintainers" ["resolution: abandoned"] color = "cfd3d7" name = "resolution: abandoned" description = "Closed; not enough information or otherwise never finished" ["resolution: answered"] color = "cfd3d7" name = "resolution: answered" description = "Closed; only applies to questions which were answered" ["resolution: duplicate"] color = "cfd3d7" name = "resolution: duplicate" description = "Closed; issue or pull request already exists" ["resolution: external"] color = "cfd3d7" name = "resolution: external" description = "Closed; passed to another tool's bug tracker" ["resolution: fixed"] color = "cfd3d7" name = "resolution: fixed" description = "Closed; fixed" ["resolution: invalid"] color = "cfd3d7" name = "resolution: invalid" description = "Closed; issue or pull request is no longer relevant" ["resolution: no fix needed"] color = "cfd3d7" name = "resolution: no fix needed" description = "Closed; no fix required (not a bug)" ["resolution: wontfix"] color = "cfd3d7" name = "resolution: wontfix" description = "Closed; work won't continue on an issue or pull request" ["status: asked reporter"] color = "ffffff" name = "status: asked reporter" description = "Bug is waiting for reporter to answer a question" ["status: assigned"] color = "a0f0ff" name = "status: assigned" description = "Issue is assigned to someone to work on" ["status: blocked"] color = "00007f" name = "status: blocked" description = "Issue is waiting for another bug, when other bug is fixed, then goes to 'status: assigned'" ["status: discussion"] color = "d876e3" name = "status: discussion" description = "Issue is waiting for discussions to resolve" ["status: ready"] color = "b6c92a" name = "status: ready" description = "Issue is ready for someone to fix; then goes to 'status: assigned'" ["type: bug"] color = "d73a4a" name = "type: bug" description = "Defect" ["type: feature-IEEE"] color = "cfccff" name = "type: feature-IEEE" description = "Request to add new feature, described in IEEE 1800" ["type: feature-non-IEEE"] color = "cfccff" name = "type: feature-non-IEEE" description = "Request to add new feature, outside IEEE 1800" ["type: maintenance"] color = "cfccff" name = "type: maintenance" description = "Internal maintenance task" ["type: q and a"] color = "84ba34" name = "type: q and a" description = "Question and answer about some feature or user question" verilator-5.042/.github/ISSUE_TEMPLATE/0000755000542200017500000000000015101701376017635 5ustar mahmoudyfreeshellverilator-5.042/.github/ISSUE_TEMPLATE/questions.md0000644000542200017500000000064515101701376022216 0ustar mahmoudyfreeshell--- name: Q and A, or Other about: Use this to ask a question, not related to a specific bug nor feature request. (Note our contributor agreement at https://github.com/verilator/verilator/blob/master/docs/CONTRIBUTING.rst) title: '' labels: new assignees: '' --- How may we help - what is your question? (If reporting a bug or requesting a feature please hit BACK on your browser and use a different issue templates.) verilator-5.042/.github/ISSUE_TEMPLATE/issue.md0000644000542200017500000000221115101701376021303 0ustar mahmoudyfreeshell--- name: Bug or feature about: Use this to report that something isn't working as expected, or is a desired feature. (Note our contributor agreement at https://github.com/verilator/verilator/blob/master/docs/CONTRIBUTING.rst) title: '' labels: new assignees: '' --- Thanks for taking the time to report this. Can you please attach an example that shows the issue or missing feature? (Must be openly licensed, completely self-contained so can directly run what you provide. Ideally use test_regress format, see https://veripool.org/guide/latest/contributing.html?highlight=test_regress#reporting-bugs) What output from that test indicates it is wrong, and what is the correct or expected output? (Or, please make test self-checking if possible.) What 'verilator' command line do we use to run your example? What 'verilator --version' are you using? Did you try it with the git master version? Did you try it with other simulators? What OS and distribution are you using? May we assist you in trying to fix this in Verilator yourself? (Please avoid attaching screenshots that show text - you can convert images to text using e.g. https://ocr.space) verilator-5.042/.github/PULL_REQUEST_TEMPLATE.md0000644000542200017500000000026715101701376021260 0ustar mahmoudyfreeshellWe appreciate your contributing to Verilator. If this is your first commit, please add your name to docs/CONTRIBUTORS, and read our contributing guidelines in docs/CONTRIBUTING.rst. verilator-5.042/.github/dependabot.yml0000644000542200017500000000037615101701376020310 0ustar mahmoudyfreeshell--- # See https://docs.github.com/code-security/dependabot/dependabot-version-updates/configuration-options-for-the-dependabot.yml-file version: 2 updates: - package-ecosystem: "github-actions" directory: "/" schedule: interval: "weekly" verilator-5.042/.github/workflows/0000755000542200017500000000000015101701376017507 5ustar mahmoudyfreeshellverilator-5.042/.github/workflows/rtlmeter.yml0000644000542200017500000003667315101701376022107 0ustar mahmoudyfreeshell--- # DESCRIPTION: Github actions config # This name is key to badges in README.rst, so we use the name build # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 name: RTLMeter on: workflow_dispatch: schedule: - cron: '0 2 * * *' # Daily, starting at 02:00 UTC pull_request: types: [opened, synchronize, reopened, labeled, unlabeled] permissions: contents: read defaults: run: shell: bash concurrency: # At most 1 job per branch. Auto cancel all but scheduled jobs group: ${{ github.workflow }}-${{ github.ref }} cancel-in-progress: ${{ github.event_name != 'schedule' }} jobs: start: name: Start # Only run scheduled jobs if explicitly enabled for that repo (e.g.: not on forks) # Only run pull request jobs if labelled as needing an RTLMeter run # Always run workflow dispatch jobs if: | (github.event_name == 'schedule' && vars.ENABLE_SCHEDULED_JOBS == 'true') || (github.event_name == 'pull_request' && contains(github.event.pull_request.labels.*.name, 'pr: rtlmeter')) || (github.event_name == 'workflow_dispatch') runs-on: ubuntu-24.04 steps: - name: Startup run: echo build-gcc: name: Build GCC needs: start uses: ./.github/workflows/reusable-rtlmeter-build.yml with: runs-on: ubuntu-24.04 cc: gcc build-clang: name: Build Clang needs: start uses: ./.github/workflows/reusable-rtlmeter-build.yml with: runs-on: ubuntu-24.04 cc: clang run-gcc: name: Run GCC | ${{ matrix.cases }} needs: build-gcc uses: ./.github/workflows/reusable-rtlmeter-run.yml with: tag: gcc runs-on: ubuntu-24.04 cc: gcc cases: ${{ matrix.cases }} run-name: "gcc" compileArgs: "" executeArgs: "" strategy: fail-fast: false max-parallel: ${{ github.event == 'schedule' && 2 || 7 }} matrix: cases: - "BlackParrot:1x1:*" - "BlackParrot:2x2:*" - "BlackParrot:4x4:*" - "NVDLA:*" - "OpenPiton:1x1:*" - "OpenPiton:2x2:*" - "OpenPiton:4x4:*" - "OpenTitan:*" - "VeeR-EH1:asic*" - "VeeR-EH1:default*" - "VeeR-EH1:hiperf*" - "VeeR-EH2:asic*" - "VeeR-EH2:default*" - "VeeR-EH2:hiperf*" - "VeeR-EL2:asic*" - "VeeR-EL2:default*" - "VeeR-EL2:hiperf*" - "Vortex:mini:*" - "Vortex:sane:*" - "XiangShan:default-chisel3:* !*:linux" - "XiangShan:default-chisel6:* !*:linux" - "XiangShan:mini-chisel3:* !*:linux" - "XiangShan:mini-chisel6:* !*:linux" - "XuanTie-E902:*" - "XuanTie-E906:*" - "XuanTie-C906:*" - "XuanTie-C910:*" run-clang: name: Run Clang | ${{ matrix.cases }} needs: build-clang uses: ./.github/workflows/reusable-rtlmeter-run.yml with: tag: clang runs-on: ubuntu-24.04 cc: clang cases: ${{ matrix.cases }} run-name: "clang --threads 4" compileArgs: "--threads 4" executeArgs: "" strategy: fail-fast: false max-parallel: ${{ github.event == 'schedule' && 2 || 7 }} matrix: cases: - "BlackParrot:1x1:*" - "BlackParrot:2x2:*" - "BlackParrot:4x4:*" - "NVDLA:*" - "OpenPiton:1x1:*" - "OpenPiton:2x2:*" - "OpenPiton:4x4:*" - "OpenTitan:*" - "VeeR-EH1:asic*" - "VeeR-EH1:default*" - "VeeR-EH1:hiperf*" - "VeeR-EH2:asic*" - "VeeR-EH2:default*" - "VeeR-EH2:hiperf*" - "VeeR-EL2:asic*" - "VeeR-EL2:default*" - "VeeR-EL2:hiperf*" - "Vortex:mini:*" - "Vortex:sane:*" - "XiangShan:default-chisel3:* !*:linux" - "XiangShan:default-chisel6:* !*:linux" - "XiangShan:mini-chisel3:* !*:linux" - "XiangShan:mini-chisel6:* !*:linux" - "XuanTie-E902:*" - "XuanTie-E906:*" - "XuanTie-C906:*" - "XuanTie-C910:*" run-gcc-hier: name: Run GCC hier | ${{ matrix.cases }} needs: build-gcc uses: ./.github/workflows/reusable-rtlmeter-run.yml with: tag: gcc-hier runs-on: ubuntu-24.04 cc: gcc cases: ${{ matrix.cases }} run-name: "gcc --hierarchical" compileArgs: "--hierarchical" executeArgs: "" strategy: fail-fast: false max-parallel: ${{ github.event == 'schedule' && 2 || 7 }} matrix: cases: - "BlackParrot:1x1:* !-hier" - "BlackParrot:2x2:* !-hier" - "BlackParrot:4x4:* !-hier" - "NVDLA:* !-hier" - "OpenPiton:1x1:* !-hier" - "OpenPiton:2x2:* !-hier" - "OpenPiton:4x4:* !-hier" - "OpenPiton:8x8:* !-hier" - "OpenPiton:16x16:dhry !-hier" - "XuanTie-C910:* !-hier" combine-results: name: Combine results needs: [run-gcc, run-clang, run-gcc-hier] # Run if any of the dependencies have run, even if failed. # That is: do not run if all skipped, or the workflow was cancelled. if: ${{ (contains(needs.*.result, 'success') || contains(needs.*.result, 'failure')) && !cancelled() }} runs-on: ubuntu-24.04 strategy: fail-fast: false matrix: tag: [gcc, clang, gcc-hier] steps: - name: Checkout RTLMeter uses: actions/checkout@v5 with: repository: "verilator/rtlmeter" path: rtlmeter - name: Setup RTLMeter venv working-directory: rtlmeter run: make venv - name: Download all results uses: actions/download-artifact@v6 with: pattern: rtlmeter-${{ matrix.tag }}-results-* path: all-results-${{ matrix.tag }} merge-multiple: true - name: Combine results working-directory: rtlmeter run: | ./rtlmeter collate ../all-results-${{ matrix.tag }}/*.json > ../all-results-${{ matrix.tag }}.json - name: Upload combined results uses: actions/upload-artifact@v5 with: path: all-results-${{ matrix.tag }}.json name: all-results-${{ matrix.tag }} overwrite: true retention-days: 30 publish-scheduled-results: name: Publish results to verilator/verilator-rtlmeter-results needs: combine-results # Only run on scheduled builds on the main repository. We also restrict # the publishing to run only on the first run_attempt. This is required # to prevent multiple uploads the same day (if rerunning), as the # dashboard UI currently assumes there is only one data point per # calendar day. Results from reruns can be imported manually if needed. if: ${{ github.event_name == 'schedule' && github.repository == 'verilator/verilator' && github.run_attempt == 1 && contains(needs.*.result, 'success') && !cancelled() }} runs-on: ubuntu-24.04 steps: - name: Download combined results uses: actions/download-artifact@v6 with: pattern: all-results-* path: results merge-multiple: true - name: Upload published results uses: actions/upload-artifact@v5 with: path: results/*.json name: published-results # Pushing to verilator/verilator-rtlmeter-results requires elevated permissions - name: Generate access token id: generate-token uses: actions/create-github-app-token@v2.1.4 with: app-id: ${{ vars.VERILATOR_CI_ID }} private-key: ${{ secrets.VERILATOR_CI_KEY }} owner: verilator repositories: verilator-rtlmeter-results permission-contents: write - name: Checkout verilator-rtlmeter-results uses: actions/checkout@v5 with: repository: "verilator/verilator-rtlmeter-results" token: ${{ steps.generate-token.outputs.token }} path: verilator-rtlmeter-results - name: Import results id: import-results working-directory: verilator-rtlmeter-results run: | for f in $(find ../results -name "*.json"); do \ echo "Importing $f"; \ ./bin/add-rtlmeter-result $f; \ done test -z "$(git status --porcelain)" || echo "valid=1" >> "$GITHUB_OUTPUT" - name: Push to verilator-rtlmeter-results if: ${{ steps.import-results.outputs.valid }} working-directory: verilator-rtlmeter-results run: | git config --global user.email "action@example.com" git config --global user.name "github action" git add . git commit -m "Verilator CI: Results of 'RTLMeter' workflow run #${{ github.run_number }}" git push origin prepare-pr-results: name: Prepare Pull Request results needs: combine-results if: ${{ github.event_name == 'pull_request' && github.repository == 'verilator/verilator' && contains(needs.*.result, 'success') && !cancelled() }} runs-on: ubuntu-24.04 permissions: actions: read steps: - name: Checkout RTLMeter uses: actions/checkout@v5 with: repository: "verilator/rtlmeter" path: rtlmeter - name: Setup RTLMeter venv working-directory: rtlmeter run: make venv - name: Download combined results uses: actions/download-artifact@v6 with: pattern: all-results-* path: all-results merge-multiple: true - name: Get scheduled run info id: scheduled-info env: GH_TOKEN: ${{ secrets.GITHUB_TOKEN }} run: | ID=$(gh run --repo ${{ github.repository }} list --workflow RTLMeter --event schedule --status success --limit 1 --json databaseId --jq ".[0].databaseId") echo "id=$ID" >> $GITHUB_OUTPUT URL=$(gh run --repo ${{ github.repository }} view $ID --json url --jq ".url") echo "url=$URL" >> $GITHUB_OUTPUT NUM=$(gh run --repo ${{ github.repository }} view $ID --json number --jq ".number") echo "num=$NUM" >> $GITHUB_OUTPUT DATE=$(gh run --repo ${{ github.repository }} view $ID --json createdAt --jq ".createdAt") echo "date=$DATE" >> $GITHUB_OUTPUT - name: Download scheduled run results uses: actions/download-artifact@v6 with: name: published-results path: nightly-results run-id: ${{ steps.scheduled-info.outputs.id }} github-token: ${{ secrets.GITHUB_TOKEN }} - name: Compare results working-directory: rtlmeter run: | for tag in gcc clang gcc-hier; do ADATA=../nightly-results/all-results-${tag}.json BDATA=../all-results/all-results-${tag}.json touch ../verilate-${tag}.txt touch ../execute-${tag}.txt touch ../cppbuild-${tag}.txt if [[ ! -e $ADATA ]]; then continue fi ./rtlmeter compare --cases '* !Example:* !*:hello' --steps "verilate" --metrics "elapsed memory" $ADATA $BDATA > ../verilate-${tag}.txt cat ../verilate-${tag}.txt ./rtlmeter compare --cases '* !Example:* !*:hello' --steps "execute" --metrics "speed memory elapsed" $ADATA $BDATA > ../execute-${tag}.txt cat ../execute-${tag}.txt ./rtlmeter compare --cases '* !Example:* !*:hello' --steps "cppbuild" --metrics "elapsed memory cpu codeSize" $ADATA $BDATA > ../cppbuild-${tag}.txt cat ../cppbuild-${tag}.txt done - name: Create report env: GH_TOKEN: ${{ secrets.GITHUB_TOKEN }} run: | set -x NUM=$(gh run --repo ${{ github.repository }} view ${{ github.run_id }} --json number --jq ".number") URL=$(gh run --repo ${{ github.repository }} view ${{ github.run_id }} --json url --jq ".url") echo -n "Performance metrics for PR workflow [#$NUM]($URL) (B) compared to scheduled run" > report.txt echo -n " [#${{ steps.scheduled-info.outputs.num }}](${{ steps.scheduled-info.outputs.url }}) (A)" >> report.txt echo " from ${{ steps.scheduled-info.outputs.date }}" >> report.txt for tag in gcc clang gcc-hier; do echo "" >> report.txt if [[ $tag == "gcc" ]]; then echo "
" >> report.txt else echo "
" >> report.txt fi echo -n "" >> report.txt jq -rj ".[0].runName" all-results/all-results-${tag}.json >> report.txt echo "" >> report.txt awk -v RS= -v tag=${tag} '{print > sprintf("frag-%02d-verilate-%s.txt",NR,tag)}' verilate-${tag}.txt awk -v RS= -v tag=${tag} '{print > sprintf("frag-%02d-execute-%s.txt" ,NR,tag)}' execute-${tag}.txt awk -v RS= -v tag=${tag} '{print > sprintf("frag-$02d-cppbuild-%s.txt",NR,tag)}' cppbuild-${tag}.txt for f in $(ls -1 frag-*-verilate-${tag}.txt | sort) $(ls -1 frag-*-execute-${tag}.txt | sort) $(ls -1 frag-*-cppbuild-${tag}.txt | sort); do if [[ $f == frag-01-verilate-${tag}.txt || $f == frag-01-execute-${tag}.txt ]]; then echo "
" >> report.txt else echo "
" >> report.txt fi echo -n "" >> report.txt head -n 1 $f | tr -d '\n' >> report.txt echo "" >> report.txt echo '
' >> report.txt
              tail -n +2 $f >> report.txt
              echo '
' >> report.txt echo "
" >> report.txt done echo "
" >> report.txt done cat report.txt - name: Upload report uses: actions/upload-artifact@v5 with: path: report.txt name: rtlmeter-pr-results - name: Save PR number run: echo ${{ github.event.number }} > pr-number.txt - name: Upload PR number uses: actions/upload-artifact@v5 with: path: pr-number.txt name: pr-number # Create GitHub issue for failed scheduled jobs # This should always be the last job (we want an issue if anything breaks) create-issue: name: Create issue on failure needs: publish-scheduled-results if: ${{ github.event_name == 'schedule' && github.repository == 'verilator/verilator' && github.run_attempt == 1 && failure() && !cancelled() }} runs-on: ubuntu-24.04 steps: # Creating issues requires elevated privilege - name: Generate access token id: generate-token uses: actions/create-github-app-token@v2.1.4 with: app-id: ${{ vars.VERILATOR_CI_ID }} private-key: ${{ secrets.VERILATOR_CI_KEY }} owner: verilator repositories: verilator permission-issues: write - name: Create issue env: GH_TOKEN: ${{ steps.generate-token.outputs.token }} run: |- echo "This issue was created automatically by the GitHub Actions CI due to the failure of a scheduled RTLMeter run." >> body.txt echo "" >> body.txt echo "Workflow status: ${{ github.server_url }}/${{ github.repository }}/actions/runs/${{ github.run_id }}" >> body.txt gh issue --repo ${{ github.repository }} create \ --title "RTLMeter run #${{ github.run_number }} Failed" \ --body-file body.txt \ --label new \ --assignee gezalore,wsnyder verilator-5.042/.github/workflows/build-test.yml0000644000542200017500000002154715101701376022317 0ustar mahmoudyfreeshell--- # DESCRIPTION: Github actions config # This name is key to badges in README.rst, so we use the name build # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 name: build-test on: push: branches-ignore: - 'dependabot/**' # Avoid duplicates: only run the PR, not the push pull_request: workflow_dispatch: schedule: - cron: '0 0 * * 0' # weekly permissions: contents: read defaults: run: working-directory: repo concurrency: # At most 1 job per branch. Auto cancel on pull requests and on all forks group: ${{ github.workflow }}-${{ github.ref }} cancel-in-progress: ${{ github.event_name == 'pull_request' || github.repository != 'verilator/verilator' }} jobs: build-2404-gcc: name: Build | ${{ matrix.os }} | ${{ matrix.cc }}${{ matrix.asan && ' | asan' || '' }} uses: ./.github/workflows/reusable-build.yml with: sha: ${{ github.sha }} os: ${{ matrix.os }} os-name: linux cc: ${{ matrix.cc }} dev-asan: ${{ matrix.asan }} dev-gcov: 0 strategy: fail-fast: false matrix: include: - {os: ubuntu-24.04, cc: gcc, asan: 0} build-2404-clang: name: Build | ${{ matrix.os }} | ${{ matrix.cc }}${{ matrix.asan && ' | asan' || '' }} uses: ./.github/workflows/reusable-build.yml with: sha: ${{ github.sha }} os: ${{ matrix.os }} os-name: linux cc: ${{ matrix.cc }} dev-asan: ${{ matrix.asan }} dev-gcov: 0 strategy: fail-fast: false matrix: include: - {os: ubuntu-24.04, cc: clang, asan: 1} build-2204-gcc: name: Build | ${{ matrix.os }} | ${{ matrix.cc }}${{ matrix.asan && ' | asan' || '' }} uses: ./.github/workflows/reusable-build.yml with: sha: ${{ github.sha }} os: ${{ matrix.os }} os-name: linux cc: ${{ matrix.cc }} dev-asan: ${{ matrix.asan }} dev-gcov: 0 strategy: fail-fast: false matrix: include: - {os: ubuntu-22.04, cc: gcc, asan: 0} build-2204-clang: name: Build | ${{ matrix.os }} | ${{ matrix.cc }}${{ matrix.asan && ' | asan' || '' }} uses: ./.github/workflows/reusable-build.yml with: sha: ${{ github.sha }} os: ${{ matrix.os }} os-name: linux cc: ${{ matrix.cc }} dev-asan: ${{ matrix.asan }} dev-gcov: 0 strategy: fail-fast: false matrix: include: - {os: ubuntu-22.04, cc: clang, asan: 0} build-osx-gcc: name: Build | ${{ matrix.os }} | ${{ matrix.cc }}${{ matrix.asan && ' | asan' || '' }} uses: ./.github/workflows/reusable-build.yml with: sha: ${{ github.sha }} os: ${{ matrix.os }} os-name: osx cc: ${{ matrix.cc }} dev-asan: ${{ matrix.asan }} dev-gcov: 0 strategy: fail-fast: false matrix: include: - {os: macos-15, cc: gcc, asan: 0} build-osx-clang: name: Build | ${{ matrix.os }} | ${{ matrix.cc }}${{ matrix.asan && ' | asan' || '' }} uses: ./.github/workflows/reusable-build.yml with: sha: ${{ github.sha }} os: ${{ matrix.os }} os-name: osx cc: ${{ matrix.cc }} dev-asan: ${{ matrix.asan }} dev-gcov: 0 strategy: fail-fast: false matrix: include: - {os: macos-15, cc: clang, asan: 0} build-windows: name: Build | ${{ matrix.os }} | ${{ matrix.cc }} runs-on: ${{ matrix.os }} strategy: fail-fast: false matrix: include: - {os: windows-2025, cc: msvc} env: CI_OS_NAME: win CCACHE_COMPRESS: 1 CCACHE_DIR: ${{ github.workspace }}/.ccache CCACHE_LIMIT_MULTIPLE: 0.95 steps: - uses: actions/checkout@v5 with: path: repo - name: Cache $CCACHE_DIR uses: actions/cache@v4 with: path: ${{ env.CCACHE_DIR }} key: msbuild-msvc-cmake - name: compile env: WIN_FLEX_BISON: ${{ github.workspace }}/.ccache run: ./ci/ci-win-compile.ps1 - name: test build run: ./ci/ci-win-test.ps1 - name: Zip up repository run: Compress-Archive -LiteralPath install -DestinationPath verilator.zip - name: Upload zip archive uses: actions/upload-artifact@v5 with: path: ${{ github.workspace }}/repo/verilator.zip name: verilator-win.zip test-2404-gcc: name: Test | ${{ matrix.os }} | ${{ matrix.cc }} | ${{ matrix.reloc && 'reloc | ' || '' }} ${{ matrix.suite }} needs: build-2404-gcc uses: ./.github/workflows/reusable-test.yml with: archive: ${{ needs.build-2404-gcc.outputs.archive }} os: ${{ matrix.os }} cc: ${{ matrix.cc }} reloc: ${{ matrix.reloc }} suite: ${{ matrix.suite }} dev-gcov: 0 strategy: fail-fast: false matrix: include: # Ubuntu 24.04 gcc - {os: ubuntu-24.04, cc: gcc, reloc: 0, suite: dist-vlt-0} - {os: ubuntu-24.04, cc: gcc, reloc: 0, suite: dist-vlt-1} - {os: ubuntu-24.04, cc: gcc, reloc: 0, suite: dist-vlt-2} - {os: ubuntu-24.04, cc: gcc, reloc: 0, suite: dist-vlt-3} - {os: ubuntu-24.04, cc: gcc, reloc: 0, suite: vltmt-0} - {os: ubuntu-24.04, cc: gcc, reloc: 0, suite: vltmt-1} - {os: ubuntu-24.04, cc: gcc, reloc: 0, suite: vltmt-2} test-2404-clang: name: Test | ${{ matrix.os }} | ${{ matrix.cc }} | ${{ matrix.reloc && 'reloc | ' || '' }} ${{ matrix.suite }} needs: build-2404-clang uses: ./.github/workflows/reusable-test.yml with: archive: ${{ needs.build-2404-clang.outputs.archive }} os: ${{ matrix.os }} cc: ${{ matrix.cc }} reloc: ${{ matrix.reloc }} suite: ${{ matrix.suite }} dev-gcov: 0 strategy: fail-fast: false matrix: include: # Ubuntu 24.04 clang - {os: ubuntu-24.04, cc: clang, reloc: 0, suite: dist-vlt-0} - {os: ubuntu-24.04, cc: clang, reloc: 0, suite: dist-vlt-1} - {os: ubuntu-24.04, cc: clang, reloc: 0, suite: dist-vlt-2} - {os: ubuntu-24.04, cc: clang, reloc: 0, suite: dist-vlt-3} - {os: ubuntu-24.04, cc: clang, reloc: 0, suite: vltmt-0} - {os: ubuntu-24.04, cc: clang, reloc: 0, suite: vltmt-1} - {os: ubuntu-24.04, cc: clang, reloc: 0, suite: vltmt-2} test-2204-gcc: name: Test | ${{ matrix.os }} | ${{ matrix.cc }} | ${{ matrix.reloc && 'reloc | ' || '' }} ${{ matrix.suite }} needs: build-2204-gcc uses: ./.github/workflows/reusable-test.yml with: archive: ${{ needs.build-2204-gcc.outputs.archive }} os: ${{ matrix.os }} cc: ${{ matrix.cc }} reloc: ${{ matrix.reloc }} suite: ${{ matrix.suite }} dev-gcov: 0 strategy: fail-fast: false matrix: include: # Ubuntu 22.04 gcc - {os: ubuntu-22.04, cc: gcc, reloc: 0, suite: dist-vlt-0} - {os: ubuntu-22.04, cc: gcc, reloc: 0, suite: dist-vlt-1} - {os: ubuntu-22.04, cc: gcc, reloc: 0, suite: dist-vlt-2} - {os: ubuntu-22.04, cc: gcc, reloc: 0, suite: dist-vlt-3} - {os: ubuntu-22.04, cc: gcc, reloc: 0, suite: vltmt-0} - {os: ubuntu-22.04, cc: gcc, reloc: 0, suite: vltmt-1} - {os: ubuntu-22.04, cc: gcc, reloc: 0, suite: vltmt-2} test-2204-clang: name: Test | ${{ matrix.os }} | ${{ matrix.cc }} | ${{ matrix.reloc && 'reloc | ' || '' }} ${{ matrix.suite }} needs: build-2204-clang uses: ./.github/workflows/reusable-test.yml with: archive: ${{ needs.build-2204-clang.outputs.archive }} os: ${{ matrix.os }} cc: ${{ matrix.cc }} reloc: ${{ matrix.reloc }} suite: ${{ matrix.suite }} dev-gcov: 0 strategy: fail-fast: false matrix: include: # Ubuntu 22.04 clang, also test relocation - {os: ubuntu-22.04, cc: clang, reloc: 1, suite: dist-vlt-0} - {os: ubuntu-22.04, cc: clang, reloc: 1, suite: dist-vlt-1} - {os: ubuntu-22.04, cc: clang, reloc: 1, suite: dist-vlt-2} - {os: ubuntu-22.04, cc: clang, reloc: 1, suite: dist-vlt-3} - {os: ubuntu-22.04, cc: clang, reloc: 1, suite: vltmt-0} - {os: ubuntu-22.04, cc: clang, reloc: 1, suite: vltmt-1} - {os: ubuntu-22.04, cc: clang, reloc: 1, suite: vltmt-2} lint-py: name: Lint Python uses: ./.github/workflows/reusable-lint-py.yml passed: name: Test suite passed if: always() needs: - build-2404-gcc - build-2404-clang - build-2204-gcc - build-2204-clang - build-osx-gcc - build-osx-clang - build-windows - test-2404-gcc - test-2404-clang - test-2204-gcc - test-2204-clang - lint-py runs-on: ubuntu-24.04 steps: - name: Decide whether the needed jobs succeeded or failed uses: re-actors/alls-green@release/v1 with: jobs: ${{ toJSON(needs) }} verilator-5.042/.github/workflows/reusable-test.yml0000644000542200017500000000546515101701376023023 0ustar mahmoudyfreeshell--- # DESCRIPTION: Github actions config # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 name: reusable-test on: workflow_call: inputs: archive: description: "Name of the repository archive artifact from reusable-build" required: true type: string os: # e.g. ubuntu-24.04 required: true type: string cc: # gcc or clang required: true type: string reloc: # 0 or 1 required: true type: number suite: # e.g. dist-vlt-0 required: true type: string dev-gcov: required: true type: number env: CI_OS_NAME: linux CCACHE_COMPRESS: 1 CCACHE_DIR: ${{ github.workspace }}/.ccache CCACHE_LIMIT_MULTIPLE: 0.95 INSTALL_DIR: ${{ github.workspace }}/install RELOC_DIR: ${{ github.workspace }}/relloc defaults: run: shell: bash working-directory: repo jobs: test: runs-on: ${{ inputs.os }} name: Test env: CI_BUILD_STAGE_NAME: test CI_RUNS_ON: ${{ inputs.os }} CI_RELOC: ${{inputs.reloc }} CXX: ${{ inputs.cc == 'clang' && 'clang++' || 'g++' }} CACHE_BASE_KEY: test-${{ inputs.os }}-${{ inputs.cc }}-${{inputs.reloc }}-${{ inputs.suite }} CCACHE_MAXSIZE: 100M # Per build per suite (* 5 * 5 = 2500M in total) steps: - name: Download repository archive uses: actions/download-artifact@v6 with: name: ${{ inputs.archive }} path: ${{ github.workspace }} - name: Unpack repository archive working-directory: ${{ github.workspace }} run: | tar -x -z -f ${{ inputs.archive }} ls -lsha - name: Cache $CCACHE_DIR uses: actions/cache@v4 env: CACHE_KEY: ${{ env.CACHE_BASE_KEY }}-ccache2 with: path: ${{ env.CCACHE_DIR }} key: ${{ env.CACHE_KEY }}-${{ github.sha }} restore-keys: | ${{ env.CACHE_KEY }}- - name: Install test dependencies run: ./ci/ci-install.bash - name: Test id: run-test continue-on-error: true env: TESTS: ${{ inputs.suite }} run: ./ci/ci-script.bash - name: Combine code coverage data if: ${{ inputs.dev-gcov }} run: | make coverage-combine mv obj_coverage/verilator.info obj_coverage/verilator-${{ inputs.suite }}.info ls -lsha obj_coverage - name: Upload code coverage data if: ${{ inputs.dev-gcov }} uses: actions/upload-artifact@v5 with: path: ${{ github.workspace }}/repo/obj_coverage/verilator-${{ inputs.suite }}.info name: code-coverage-${{ inputs.suite }} - name: Fail job if a test failed if: ${{ steps.run-test.outcome == 'failure' && !cancelled() }} run: exit 1 verilator-5.042/.github/workflows/reusable-lint-py.yml0000644000542200017500000000206515101701376023431 0ustar mahmoudyfreeshell--- # DESCRIPTION: Github actions config # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 name: reusable-lint-py on: workflow_call: env: CI_OS_NAME: linux CI_BUILD_STAGE_NAME: build CI_RUNS_ON: ubuntu-22.04 CCACHE_COMPRESS: 1 CCACHE_DIR: ${{ github.workspace }}/.ccache CCACHE_LIMIT_MULTIPLE: 0.95 defaults: run: shell: bash working-directory: repo jobs: lint-py: runs-on: ubuntu-22.04 name: Sub-lint | Python steps: - name: Checkout uses: actions/checkout@v5 with: path: repo - name: Install packages for build run: ./ci/ci-install.bash # We use specific version numbers, otherwise a Python package # update may add a warning and break our build - name: Install packages for lint run: sudo pip3 install mypy==1.18.2 pylint==3.0.2 ruff==0.1.3 clang sphinx sphinx_rtd_theme sphinxcontrib-spelling breathe ruff - name: Configure run: autoconf && ./configure --enable-longtests --enable-ccwarn - name: Lint run: make -k lint-py verilator-5.042/.github/workflows/contributor.yml0000644000542200017500000000074215101701376022607 0ustar mahmoudyfreeshell--- # DESCRIPTION: Github actions config # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # name: Contributor Agreement on: push: branches-ignore: - 'dependabot/**' # Avoid duplicates: only run the PR, not the push pull_request: workflow_dispatch: permissions: contents: read jobs: Test: name: "'docs/CONTRIBUTORS' was signed" runs-on: ubuntu-24.04 steps: - uses: actions/checkout@v5 - run: test_regress/t/t_dist_contributors.py verilator-5.042/.github/workflows/reusable-rtlmeter-build.yml0000644000542200017500000000427415101701376024774 0ustar mahmoudyfreeshell--- # DESCRIPTION: Github actions config # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 name: reusable-rtlmeter-build on: workflow_call: inputs: runs-on: description: "Runner to use, e.g.: ubuntu-24.04" type: string required: true cc: description: "Compiler to use: 'gcc' or 'clang'" type: string required: true defaults: run: shell: bash env: CCACHE_DIR: ${{ github.workspace }}/ccache CCACHE_MAXSIZE: 512M jobs: build: runs-on: ${{ inputs.runs-on }} name: Build steps: - name: Install dependencies run: | echo "path-exclude /usr/share/doc/*" | sudo tee -a /etc/dpkg/dpkg.cfg.d/01_nodoc echo "path-exclude /usr/share/man/*" | sudo tee -a /etc/dpkg/dpkg.cfg.d/01_nodoc echo "path-exclude /usr/share/info/*" | sudo tee -a /etc/dpkg/dpkg.cfg.d/01_nodoc sudo apt update sudo apt install ccache mold help2man libfl-dev libgoogle-perftools-dev libsystemc-dev - name: Use saved ccache uses: actions/cache@v4 with: path: ccache key: rtlmeter-build-ccache-${{ inputs.runs-on }}-${{ inputs.cc }}-${{ github.run_id }}-${{ github.run_attempt }} restore-keys: rtlmeter-build-ccache-${{ inputs.runs-on }}-${{ inputs.cc }} - name: Checkout uses: actions/checkout@v5 with: path: repo fetch-depth: 0 # Required for 'git describe' used for 'verilator --version' - name: Configure working-directory: repo run: | autoconf ./configure --prefix=${{ github.workspace }}/install CXX=${{ inputs.cc == 'clang' && 'clang++' || 'g++' }} - name: Make working-directory: repo run: make -j $(nproc) - name: Install working-directory: repo run: make install - name: Tar up installation run: tar --posix -c -z -f verilator-rtlmeter.tar.gz install - name: Upload Verilator installation archive uses: actions/upload-artifact@v5 with: path: verilator-rtlmeter.tar.gz name: verilator-rtlmeter-${{ inputs.runs-on }}-${{ inputs.cc }} overwrite: true verilator-5.042/.github/workflows/reusable-build.yml0000644000542200017500000000547215101701376023141 0ustar mahmoudyfreeshell--- # DESCRIPTION: Github actions config # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 name: reusable-build on: workflow_call: inputs: sha: description: "Commit SHA to build" required: true type: string os: # e.g. ubuntu-24.04 required: true type: string cc: # 'clang' or 'gcc' required: true type: string os-name: # 'linux' or 'osx' required: true type: string dev-asan: required: true type: number dev-gcov: required: true type: number outputs: archive: description: "Name of the built repository archive artifact" value: ${{ jobs.build.outputs.archive }} env: CI_OS_NAME: ${{ inputs.os-name }} CCACHE_COMPRESS: 1 CCACHE_DIR: ${{ github.workspace }}/.ccache CCACHE_LIMIT_MULTIPLE: 0.95 INSTALL_DIR: ${{ github.workspace }}/install RELOC_DIR: ${{ github.workspace }}/relloc defaults: run: shell: bash working-directory: repo jobs: build: name: Build runs-on: ${{ inputs.os }} outputs: archive: ${{ steps.create-archive.outputs.archive }} env: CI_BUILD_STAGE_NAME: build CI_DEV_ASAN: ${{ inputs.dev-asan }} CI_DEV_GCOV: ${{ inputs.dev-gcov }} CI_RUNS_ON: ${{ inputs.os }} CXX: ${{ inputs.cc == 'clang' && 'clang++' || 'g++' }} CACHE_BASE_KEY: build-${{ inputs.os }}-${{ inputs.cc }} CCACHE_MAXSIZE: 1000M # Per build matrix entry (* 5 = 5000M in total) steps: - name: Checkout uses: actions/checkout@v5 with: path: repo ref: ${{ inputs.sha }} fetch-depth: ${{ inputs.dev-gcov && '0' || '1' }} # Coverage flow needs full history - name: Cache $CCACHE_DIR uses: actions/cache@v4 env: CACHE_KEY: ${{ env.CACHE_BASE_KEY }}-ccache with: path: ${{ env.CCACHE_DIR }} key: ${{ env.CACHE_KEY }}-${{ inputs.sha }} restore-keys: | ${{ env.CACHE_KEY }}- - name: Install packages for build run: ./ci/ci-install.bash - name: Build run: ./ci/ci-script.bash - name: Create repository archive id: create-archive working-directory: ${{ github.workspace }} run: | # Name of the archive must be unique based on the build parameters ARCHIVE=verilator-${{ inputs.sha }}-${{ inputs.os }}-${{ inputs.cc }}-${{ inputs.dev-asan }}-${{ inputs.dev-gcov }}.tar.gz tar --posix -c -z -f $ARCHIVE repo echo "archive=$ARCHIVE" >> "$GITHUB_OUTPUT" - name: Upload repository archive uses: actions/upload-artifact@v5 with: path: ${{ github.workspace }}/${{ steps.create-archive.outputs.archive }} name: ${{ steps.create-archive.outputs.archive }} verilator-5.042/.github/workflows/format.yml0000644000542200017500000000236515101701376021530 0ustar mahmoudyfreeshell--- # DESCRIPTION: Github actions config # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # name: format on: push: branches-ignore: - 'dependabot/**' # Avoid duplicates: only run the PR, not the push permissions: contents: write jobs: format: runs-on: ubuntu-24.04 name: Ubuntu 24.04 | format env: CI_OS_NAME: linux CI_RUNS_ON: ubuntu-24.04 CI_COMMIT: ${{ github.sha }} steps: - name: Checkout uses: actions/checkout@v5 with: token: ${{ secrets.GITHUB_TOKEN }} - name: Install packages for build env: CI_BUILD_STAGE_NAME: build run: | bash ci/ci-install.bash && sudo apt-get install clang-format-18 yapf3 && sudo pip3 install gersemi mbake && git config --global user.email "action@example.com" && git config --global user.name "github action" - name: Format code run: | autoconf && ./configure && make -j 2 format CLANGFORMAT=clang-format-18 && git status - name: Push run: |- if [ -n "$(git status --porcelain)" ]; then git commit . -m "Apply 'make format'" && git push origin fi verilator-5.042/.github/workflows/reusable-rtlmeter-run.yml0000644000542200017500000001111515101701376024471 0ustar mahmoudyfreeshell--- # DESCRIPTION: Github actions config # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 name: reusable-rtlmeter-run on: workflow_call: inputs: tag: description: "Unique identifier for storing results" type: string required: true runs-on: description: "Runner to use, e.g.: ubuntu-24.04" type: string required: true cc: description: "Compiler to use: 'gcc' or 'clang'" type: string required: true # Note: The combination of 'cases' and 'run-name' must be unique for all # invocations of this workflow within a run of the parent workflow. # These two are used together to generate a unique results file name. cases: description: "RTLMeter cases to run" type: string required: true run-name: description: "Run name (identifier) to add to collated results" type: string required: true compileArgs: description: "Additional Verilator command line arguments" type: string default: "" executeArgs: description: "Additional simulator command line arguments" type: string default: "" defaults: run: shell: bash env: CCACHE_DIR: ${{ github.workspace }}/ccache CCACHE_MAXSIZE: 512M CCACHE_DISABLE: 1 jobs: run: runs-on: ${{ inputs.runs-on }} name: Run steps: - name: Install dependencies run: | echo "path-exclude /usr/share/doc/*" | sudo tee -a /etc/dpkg/dpkg.cfg.d/01_nodoc echo "path-exclude /usr/share/man/*" | sudo tee -a /etc/dpkg/dpkg.cfg.d/01_nodoc echo "path-exclude /usr/share/info/*" | sudo tee -a /etc/dpkg/dpkg.cfg.d/01_nodoc sudo apt update sudo apt install ccache mold libfl-dev libgoogle-perftools-dev libsystemc-dev - name: Download Verilator installation archive uses: actions/download-artifact@v6 with: name: verilator-rtlmeter-${{ inputs.runs-on }}-${{ inputs.cc }} - name: Unpack Verilator installation archive run: | tar -x -z -f verilator-rtlmeter.tar.gz echo "${{ github.workspace }}/install/bin" >> $GITHUB_PATH - name: Use saved ccache if: ${{ env.CCACHE_DISABLE == 0 }} uses: actions/cache@v4 with: path: ${{ env.CCACHE_DIR }} key: rtlmeter-run-ccache-${{ inputs.runs-on }}-${{ inputs.cc }}-${{ inputs.cases }}-${{ inputs.compileArgs }}-${{ github.run_id }}-${{ github.run_attempt }} restore-keys: rtlmeter-run-ccache-${{ inputs.runs-on }}-${{ inputs.cc }}-${{ inputs.cases }}-${{ inputs.compileArgs }} - name: Checkout RTLMeter uses: actions/checkout@v5 with: repository: "verilator/rtlmeter" path: rtlmeter - name: Setup RTLMeter venv working-directory: rtlmeter run: make venv - name: Compile cases working-directory: rtlmeter run: | ./rtlmeter run --timeout 60 --verbose --cases='${{inputs.cases}}' --compileArgs='${{inputs.compileArgs}}' --executeArgs='${{inputs.executeArgs}}' --nExecute=0 - name: Execute cases working-directory: rtlmeter continue-on-error: true # Do not fail on error, so we can at least save the successful results run: | ./rtlmeter run --timeout 60 --verbose --cases='${{inputs.cases}}' --compileArgs='${{inputs.compileArgs}}' --executeArgs='${{inputs.executeArgs}}' - name: Collate results id: results working-directory: rtlmeter run: | # Use 'inputs.cases' and 'inputs.run-name' to generate a unique file name hash=$(md5sum <<< '${{ inputs.cases }} ${{ inputs.run-name }}' | awk '{print $1}') echo "hash=${hash}" >> $GITHUB_OUTPUT ./rtlmeter collate --runName "${{ inputs.run-name }}" > ../results-${hash}.json - name: Report results working-directory: rtlmeter run: | ./rtlmeter report --steps '*' --metrics '*' ../results-${{ steps.results.outputs.hash }}.json - name: Upload results uses: actions/upload-artifact@v5 with: path: results-${{ steps.results.outputs.hash }}.json name: rtlmeter-${{ inputs.tag }}-results-${{ steps.results.outputs.hash }} overwrite: true retention-days: 2 - name: Report status working-directory: rtlmeter run: | # This will fail the job if any of the runs failed ./rtlmeter run --verbose --cases='${{inputs.cases}}' --compileArgs='${{inputs.compileArgs}}' --executeArgs='${{inputs.executeArgs}}' verilator-5.042/.github/workflows/rtlmeter-pr-results.yml0000644000542200017500000000302615101701376024207 0ustar mahmoudyfreeshell--- # DESCRIPTION: Github actions config # This name is key to badges in README.rst, so we use the name build # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 name: RTLMeter PR results on: workflow_run: workflows: [RTLMeter] types: [completed] jobs: publish: name: Publish runs-on: ubuntu-latest if: ${{ github.event.workflow_run.event == 'pull_request' && github.event.workflow_run.conclusion == 'success' }} permissions: actions: read pull-requests: write steps: - name: Download report uses: actions/download-artifact@v6 with: name: rtlmeter-pr-results run-id: ${{ github.event.workflow_run.id }} github-token: ${{ secrets.GITHUB_TOKEN }} - name: Download PR number uses: actions/download-artifact@v6 with: name: pr-number run-id: ${{ github.event.workflow_run.id }} github-token: ${{ secrets.GITHUB_TOKEN }} # Use the Verilator CI app to post the comment - name: Generate access token id: generate-token uses: actions/create-github-app-token@v2.1.4 with: app-id: ${{ vars.VERILATOR_CI_ID }} private-key: ${{ secrets.VERILATOR_CI_KEY }} permission-pull-requests: write - name: Comment on PR env: GH_TOKEN: ${{ steps.generate-token.outputs.token }} run: |- ls -la cat report.txt gh pr --repo ${{ github.repository }} comment $(cat pr-number.txt) --body-file report.txt verilator-5.042/.github/workflows/docker.yml0000644000542200017500000000556015101701376021507 0ustar mahmoudyfreeshell--- # Build and push verilator docker image when tags are pushed to the repository. # The following variable(s) must be configured in the github repository: # DOCKER_HUB_NAMESPACE: docker hub namespace. # The following secrets must be configured in the github repository: # DOCKER_HUB_USER: user name for logging into docker hub # DOCKER_HUB_ACCESS_TOKEN: docker hub access token. name: Build Verilator Container on: push: tags: ['v*'] workflow_dispatch: inputs: manual_tag: description: 'Git tag to use for image build' required: true type: string add_latest_tag: description: 'Tag workflow_dispatch docker image as "latest"' required: true type: boolean default: false permissions: contents: write jobs: build: runs-on: ubuntu-24.04 strategy: matrix: contexts: - "ci/docker/run:verilator" # - "ci/docker/buildenv:verilator-buildenv" steps: - name: Checkout uses: actions/checkout@v5 - name: Extract context variables run: | echo "${{ matrix.contexts }}" | sed -r 's/(.*):.*/build_context=\1/' >> "$GITHUB_ENV" echo "${{ matrix.contexts }}" | sed -r 's/.*:(.*)/image_name=\1/' >> "$GITHUB_ENV" echo "git_tag=${GITHUB_REF#refs/*/}" >> "$GITHUB_ENV" - name: Use manual tag if: ${{ inputs.manual_tag }} run: | echo "git_tag=${{ inputs.manual_tag }}" >> "$GITHUB_ENV" - name: Docker meta id: docker_meta uses: docker/metadata-action@v5 with: images: | ${{ vars.DOCKER_HUB_NAMESPACE }}/${{ env.image_name }} tags: | type=match,pattern=(v.*),group=1,enable=${{ startsWith(github.ref, 'refs/tags/v') }} type=raw,value=${{ inputs.manual_tag }},enable=${{ inputs.manual_tag != '' }} type=raw,value=latest,enable=${{ inputs.add_latest_tag == true }} - name: Set up QEMU uses: docker/setup-qemu-action@v3 - name: Set up Docker Buildx uses: docker/setup-buildx-action@v3 with: buildkitd-flags: --debug - name: Login to Docker Hub uses: docker/login-action@v3 with: username: ${{ secrets.DOCKER_HUB_USER }} password: ${{ secrets.DOCKER_HUB_ACCESS_TOKEN }} - name: Build and Push to Docker uses: docker/build-push-action@v6 if: startsWith(github.ref, 'refs/tags/v') || github.event_name == 'workflow_dispatch' with: context: ${{ env.build_context }} build-args: SOURCE_COMMIT=${{ env.git_tag }} platforms: linux/arm64,linux/amd64 push: ${{ !env.ACT && (startsWith(github.ref, 'refs/tags/v') || github.event_name == 'workflow_dispatch') }} tags: ${{ steps.docker_meta.outputs.tags }} labels: ${{ steps.docker_meta.outputs.labels }} verilator-5.042/.github/workflows/coverage.yml0000644000542200017500000001740615101701376022035 0ustar mahmoudyfreeshell--- # DESCRIPTION: Github actions config # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 name: Code coverage on: workflow_dispatch: schedule: - cron: '0 0 * * 0' # weekly pull_request: types: [opened, synchronize, reopened, labeled, unlabeled] permissions: contents: read defaults: run: shell: bash concurrency: # At most 1 job per branch. Auto cancel all but scheduled jobs group: ${{ github.workflow }}-${{ github.ref }} cancel-in-progress: ${{ github.event_name != 'schedule' }} jobs: build: name: Build # Only run scheduled jobs if explicitly enabled for that repo (e.g.: not on forks) # Only run pull request jobs if labelled as needing an coverage run # Always run workflow dispatch jobs if: | (github.event_name == 'schedule' && vars.ENABLE_SCHEDULED_JOBS == 'true') || (github.event_name == 'pull_request' && contains(github.event.pull_request.labels.*.name, 'pr: dev-coverage')) || (github.event_name == 'workflow_dispatch') uses: ./.github/workflows/reusable-build.yml with: # For pull requests, build the head of the pull request branch, not the # merge commit, otherwise patch coverage would include the changes # between the root of the pull request and the target branch sha: ${{ github.event_name == 'pull_request' && github.event.pull_request.head.sha || github.sha }} os: ubuntu-24.04 os-name: linux cc: gcc dev-asan: 0 dev-gcov: 1 test: name: Test | ${{ matrix.test }}${{ matrix.num }} needs: build uses: ./.github/workflows/reusable-test.yml with: archive: ${{ needs.build.outputs.archive }} os: ubuntu-24.04 cc: gcc reloc: 0 suite: ${{ matrix.test }}${{ matrix.num }} dev-gcov: 1 strategy: fail-fast: false matrix: test: [coverage-vlt-, coverage-vltmt-] num: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9] include: - {test: coverage-dist, num: ''} publish-codecov: name: Publish results to codecov.io needs: test if: ${{ contains(needs.*.result, 'success') && !cancelled() }} runs-on: ubuntu-24.04 steps: - name: Checkout uses: actions/checkout@v5 - name: Download code coverage data uses: actions/download-artifact@v6 with: pattern: code-coverage-* path: obj_coverage merge-multiple: true - name: List files id: list-files run: | ls -lsha obj_coverage find obj_coverage -type f | paste -sd, | sed "s/^/files=/" >> "$GITHUB_OUTPUT" - name: Upload to codecov.io uses: codecov/codecov-action@v5 with: disable_file_fixes: true disable_search: true fail_ci_if_error: true files: ${{ steps.list-files.outputs.files }} plugins: noop token: ${{ secrets.CODECOV_TOKEN }} verbose: true prepare-report: name: Prepare HTML report needs: [build, test] if: ${{ contains(needs.*.result, 'success') && !cancelled() }} runs-on: ubuntu-24.04 steps: - name: Install dependencies run: | echo 'set man-db/auto-update false' | sudo debconf-communicate >/dev/null sudo dpkg-reconfigure man-db sudo apt install lcov - name: Download repository archive uses: actions/download-artifact@v6 with: name: ${{ needs.build.outputs.archive }} path: ${{ github.workspace }} - name: Unpack repository archive run: | tar -x -z -f ${{ needs.build.outputs.archive }} ls -lsha - name: Download code coverage data uses: actions/download-artifact@v6 with: pattern: code-coverage-* path: repo/obj_coverage merge-multiple: true - name: Create report working-directory: repo env: GH_TOKEN: ${{ github.token }} run: | ls -lsha obj_coverage # Combine reports from test jobs nodist/fastcov.py -C obj_coverage/verilator-*.info --lcov -o obj_coverage/verilator.info # For a PR, report patch coverage against the merge-base between the head of the PR and the target branch if [[ "${{ github.event_name }}" == "pull_request" ]]; then COVERAGE_BASE=$(git rev-parse --short $(git merge-base ${{ github.event.pull_request.base.sha }} ${{ github.event.pull_request.head.sha }})) make coverage-report COVERAGE_BASE=${COVERAGE_BASE} |& tee ${{ github.workspace }}/make-coverage-report.log else make coverage-report fi # Remove data files rm -f obj_coverage/verilator*.info # Some extra work for PRs only if [[ "${{ github.event_name }}" == "pull_request" ]]; then # Save PR number in report echo ${{ github.event.number }} > obj_coverage/pr-number.txt # Generate notification comment content mkdir -p notification echo ${{ github.event.number }} > notification/pr-number.txt NUM=$(gh run view ${{ github.run_id }} --json number --jq ".number") URL=$(gh run view ${{ github.run_id }} --json url --jq ".url") echo "Patch coverage from PR workflow [#$NUM]($URL) (code coverage of lines changed relative to ${COVERAGE_BASE}):" > notification/body.txt if [[ ! -f obj_coverage/empty-patch ]]; then echo "
" >> notification/body.txt
              grep -E "(lines|branches)\.*:" ${{ github.workspace }}/make-coverage-report.log | sed "s/\.*:/:/" >> notification/body.txt || true
              echo "
" >> notification/body.txt echo "Report: [${{ github.run_id }}](https://${{ github.repository_owner }}.github.io/verilator/coverage-reports/${{ github.run_id }}/index.html)" >> notification/body.txt else echo "Patch contains no code changes" >> notification/body.txt fi cat notification/body.txt fi - name: Upload report uses: actions/upload-artifact@v5 with: path: repo/obj_coverage name: coverage-report - name: Upload notification if: ${{ github.event_name == 'pull_request' }} uses: actions/upload-artifact@v5 with: path: repo/notification name: coverage-pr-notification # Create GitHub issue for failed scheduled jobs # This should always be the last job (we want an issue if anything breaks) create-issue: name: Create issue on failure needs: [publish-codecov, prepare-report] if: ${{ github.event_name == 'schedule' && github.repository == 'verilator/verilator' && github.run_attempt == 1 && failure() && !cancelled() }} runs-on: ubuntu-24.04 steps: # Creating issues requires elevated privilege - name: Generate access token id: generate-token uses: actions/create-github-app-token@v2.1.4 with: app-id: ${{ vars.VERILATOR_CI_ID }} private-key: ${{ secrets.VERILATOR_CI_KEY }} owner: verilator repositories: verilator permission-issues: write - name: Create issue env: GH_TOKEN: ${{ steps.generate-token.outputs.token }} run: |- echo "This issue was created automatically by the GitHub Actions CI due to the failure of a scheduled Code coverage run." >> body.txt echo "" >> body.txt echo "Workflow status: ${{ github.server_url }}/${{ github.repository }}/actions/runs/${{ github.run_id }}" >> body.txt gh issue --repo ${{ github.repository }} create \ --title "Code coverage run #${{ github.run_number }} Failed" \ --body-file body.txt \ --label new \ --assignee gezalore,wsnyder verilator-5.042/.github/workflows/pages.yml0000644000542200017500000000441615101701376021336 0ustar mahmoudyfreeshell--- # DESCRIPTION: Github actions config # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 name: Pages on: push: branches: - master paths: - "ci/**" - ".github/workflows" workflow_dispatch: workflow_run: workflows: ["Code coverage"] types: [completed] # Sets permissions of the GITHUB_TOKEN to allow deployment to GitHub Pages permissions: contents: read pages: write id-token: write # Allow only one concurrent deployment, skipping runs queued between the run # in-progress and latest queued. However, do NOT cancel in-progress runs as we # want to allow these deployments to complete. concurrency: group: "pages" cancel-in-progress: false defaults: run: shell: bash jobs: build: name: Build content runs-on: ubuntu-24.04 outputs: coverage-pr-run-ids: ${{ steps.build.outputs.coverage-pr-run-ids }} steps: - name: Checkout uses: actions/checkout@v5 - name: Build pages id: build env: GH_TOKEN: ${{ github.token }} run: | bash -x ./ci/ci-pages.bash ls -lsha tree -L 3 pages - name: Upload pages artifact uses: actions/upload-pages-artifact@v4 with: path: pages deploy: name: Deploy needs: build runs-on: ubuntu-24.04 environment: name: github-pages url: ${{ steps.deployment.outputs.page_url }} steps: - name: Deploy to GitHub Pages uses: actions/deploy-pages@v4 notify: name: Notify needs: [build, deploy] runs-on: ubuntu-24.04 if: ${{ github.repository == 'verilator/verilator' }} steps: - name: Checkout uses: actions/checkout@v5 # Use the Verilator CI app to post the comment - name: Generate access token id: generate-token uses: actions/create-github-app-token@v2.1.4 with: app-id: ${{ vars.VERILATOR_CI_ID }} private-key: ${{ secrets.VERILATOR_CI_KEY }} permission-actions: write permission-pull-requests: write - name: Comment on PR env: GH_TOKEN: ${{ steps.generate-token.outputs.token }} COVERAGE_PR_RUN_IDS: ${{ needs.build.outputs.coverage-pr-run-ids }} run: bash -x ./ci/ci-pages-notify.bash verilator-5.042/.codecov.yml0000644000542200017500000000104315101701376016333 0ustar mahmoudyfreeshell--- # DESCRIPTION: codecov.io config # # Copyright 2020-2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 #################### # Validate: # curl --data-binary @.codecov.yml https://codecov.io/validate # coverage: precision: 2 range: 75...100 round: down status: project: false patch: false comment: false verilator-5.042/.gitattributes0000644000542200017500000000027215101701376017006 0ustar mahmoudyfreeshell*.v linguist-language=SystemVerilog *.vh linguist-language=SystemVerilog *.sv linguist-language=SystemVerilog Changes linguist-language=reStructuredText nodist linguist-detectable=false verilator-5.042/README.rst0000644000542200017500000001551015101701376015603 0ustar mahmoudyfreeshell.. Github doesn't render images unless absolute URL .. Do not know of a conditional tag, "only: github" nor "github display" works |badge1| |badge2| |badge3| |badge4| |badge5| |badge7| |badge8| .. |badge1| image:: https://img.shields.io/badge/Website-Verilator.org-181717.svg :target: https://verilator.org .. |badge2| image:: https://img.shields.io/badge/License-LGPL%20v3-blue.svg :target: https://www.gnu.org/licenses/lgpl-3.0 .. |badge3| image:: https://img.shields.io/badge/License-Artistic%202.0-0298c3.svg :target: https://opensource.org/licenses/Artistic-2.0 .. |badge4| image:: https://repology.org/badge/tiny-repos/verilator.svg?header=distro%20packages :target: https://repology.org/project/verilator/versions .. |badge5| image:: https://img.shields.io/docker/pulls/verilator/verilator :target: https://hub.docker.com/r/verilator/verilator .. |badge7| image:: https://github.com/verilator/verilator/workflows/build/badge.svg :target: https://github.com/verilator/verilator/actions?query=workflow%3Abuild .. |badge8| image:: https://img.shields.io/github/actions/workflow/status/verilator/verilator/rtlmeter.yml?branch=master&event=schedule&label=benchmarks :target: https://verilator.github.io/verilator-rtlmeter-results Welcome to Verilator ==================== .. list-table:: * - **Welcome to Verilator, the fastest Verilog/SystemVerilog simulator.** * Accepts Verilog or SystemVerilog * Performs lint code-quality checks * Compiles into multithreaded C++, or SystemC * Creates XML to front-end your own tools - |Logo| * - |verilator multithreaded performance| - **Fast** * Outperforms many closed-source commercial simulators * Single- and multithreaded output models * - **Widely Used** * Wide industry and academic deployment * Out-of-the-box support from Arm and RISC-V vendor IP * Over 700 contributors - |verilator usage| * - |verilator community| - **Community Driven & Openly Licensed** * Guided by the `CHIPS Alliance`_ and `Linux Foundation`_ * Open, and free as in both speech and beer * More simulation for your verification budget * - **Commercial Support Available** * Commercial support contracts * Design support contracts * Enhancement contracts - |verilator support| What Verilator Does =================== Verilator is invoked with parameters similar to GCC or Synopsys's VCS. It "Verilates" the specified Verilog or SystemVerilog code by reading it, performing lint checks, and optionally inserting assertion checks and coverage-analysis points. It outputs single- or multithreaded .cpp and .h files, the "Verilated" code. These Verilated C++/SystemC files are then compiled by a C++ compiler (gcc/clang/MSVC++), optionally along with a user's own C++/SystemC wrapper file, to instantiate the Verilated model. Executing the resulting executable performs the design simulation. Verilator also supports linking Verilated generated libraries, optionally encrypted, into other simulators. Verilator may not be the best choice if you are expecting a full-featured replacement for a closed-source Verilog simulator, need SDF annotation, mixed-signal simulation, or are doing a quick class project (we recommend `Icarus Verilog`_ for classwork). However, if you are looking for a path to migrate SystemVerilog to C++/SystemC, or want high-speed simulation of designs, Verilator is the tool for you. Performance =========== Verilator does not directly translate Verilog HDL to C++ or SystemC. Rather, Verilator compiles your code into a much faster optimized and optionally thread-partitioned model, which is in turn wrapped inside a C++/SystemC module. The results are a compiled Verilog model that executes even on a single thread over 10x faster than standalone SystemC, and on a single thread is about 100 times faster than interpreted Verilog simulators such as `Icarus Verilog`_. Another 2-10x speedup might be gained from multithreading (yielding 200-1000x total over interpreted simulators). Verilator has typically similar or better performance versus closed-source Verilog simulators (e.g., Aldec Riviera-Pro, Cadence Incisive/NC-Verilog, Mentor ModelSim/Questa, Synopsys VCS, VTOC, and Pragmatic CVer/CVC). But, Verilator is open-sourced, so you can spend on computes rather than licenses. Thus, Verilator gives you the best simulation cycles/dollar. Installation & Documentation ============================ For more information: - `Verilator installation and package directory structure `_ - `Verilator manual (HTML) `_, or `Verilator manual (PDF) `_ - `Subscribe to Verilator announcements `_ - `Verilator forum `_ - `Verilator issues `_ Support ======= Verilator is a community project, guided by the `CHIPS Alliance`_ under the `Linux Foundation`_. We appreciate and welcome your contributions in whatever form; please see `Contributing to Verilator `_. Thanks to our `Contributors and Sponsors `_. Verilator also supports and encourages commercial support models and organizations; please see `Verilator Commercial Support `_. Related Projects ================ - `GTKwave `_ - Waveform viewer for Verilator traces. - `Icarus Verilog`_ - Icarus is a highly-featured interpreted Verilog simulator. If Verilator does not support your needs, perhaps Icarus may. - `Surfer `_ - Web or offline waveform viewer for Verilator traces. Open License ============ Verilator is Copyright 2003-2025 by Wilson Snyder. (Report bugs to `Verilator Issues `_.) Verilator is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. See the documentation for more details. .. _CHIPS Alliance: https://chipsalliance.org .. _Icarus Verilog: https://steveicarus.github.io/iverilog .. _Linux Foundation: https://www.linuxfoundation.org .. |Logo| image:: https://www.veripool.org/img/verilator_256_200_min.png .. |verilator multithreaded performance| image:: https://www.veripool.org/img/verilator_multithreaded_performance_bg-min.png .. |verilator usage| image:: https://www.veripool.org/img/verilator_usage_400x200-min.png .. |verilator community| image:: https://www.veripool.org/img/verilator_community_400x125-min.png .. |verilator support| image:: https://www.veripool.org/img/verilator_support_400x125-min.png verilator-5.042/verilator-config.cmake.in0000644000542200017500000007402015101701376020776 0ustar mahmoudyfreeshell###################################################################### # # DESCRIPTION: CMake configuration file for Verilator # # Include it in your CMakeLists.txt using: # # find_package(verilator) # # This script adds a verilate function. # # add_executable(simulator ) # verilate(simulator SOURCES ) # # Copyright 2003-2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ###################################################################### cmake_minimum_required(VERSION 3.19) # Prefer VERILATOR_ROOT from environment if(DEFINED ENV{VERILATOR_ROOT}) set(VERILATOR_ROOT "$ENV{VERILATOR_ROOT}" CACHE PATH "VERILATOR_ROOT") endif() set(VERILATOR_ROOT "${CMAKE_CURRENT_LIST_DIR}" CACHE PATH "VERILATOR_ROOT") find_program( VERILATOR_BIN NAMES verilator_bin verilator_bin.exe HINTS ${VERILATOR_ROOT}/bin ENV VERILATOR_ROOT NO_CMAKE_PATH NO_CMAKE_ENVIRONMENT_PATH NO_CMAKE_SYSTEM_PATH ) if(NOT VERILATOR_ROOT) message( FATAL_ERROR "VERILATOR_ROOT cannot be detected. Set it to the appropriate directory (e.g. /usr/share/verilator) as an environment variable or CMake define." ) endif() if(NOT VERILATOR_BIN) message(FATAL_ERROR "Cannot find verilator_bin excecutable.") endif() set(verilator_FOUND 1) include(CheckCXXSourceCompiles) function(_verilator_check_cxx_libraries LIBRARIES RESVAR) # Check whether a particular link option creates a valid executable set(_VERILATOR_CHECK_CXX_LINK_OPTIONS_SRC "int main() {return 0;}\n") set(CMAKE_REQUIRED_FLAGS) set(CMAKE_REQUIRED_DEFINITIONS) set(CMAKE_REQUIRED_INCLUDES) set(CMAKE_REQUIRED_LINK_OPTIONS) set(CMAKE_REQUIRED_LIBRARIES ${LIBRARIES}) set(CMAKE_REQUIRED_QUIET) check_cxx_source_compiles( "${_VERILATOR_CHECK_CXX_LINK_OPTIONS_SRC}" "${RESVAR}" ) set("${RESVAR}" "${${RESVAR}}" PARENT_SCOPE) endfunction() function(_verilator_check_cxx_compiler_flag FLAG RESVAR) # Check whether the compiler understands the flag FLAG set(_VERILATOR_CHECK_CXX_COMPILER_FLAG_SRC " #warning warning int main() { return 0; } " ) set(CMAKE_REQUIRED_FLAGS ${FLAG}) # Make sure the compiler warning is not turned into an error string(APPEND CMAKE_REQUIRED_FLAGS " -Wno-error=cpp") set(CMAKE_REQUIRED_DEFINITIONS) set(CMAKE_REQUIRED_INCLUDES) set(CMAKE_REQUIRED_LINK_OPTIONS) set(CMAKE_REQUIRED_LIBRARIES) set(CMAKE_REQUIRED_QUIET) check_compiler_flag_common_patterns(_common_patterns) check_cxx_source_compiles( "${_VERILATOR_CHECK_CXX_COMPILER_FLAG_SRC}" "${RESVAR}" FAIL_REGEX "command[ -]line option .* is valid for .* but not for C[+][+]" FAIL_REGEX "-Werror=.* argument .* is not valid for C[+][+]" ${_common_patterns} ) set("${RESVAR}" "${${RESVAR}}" PARENT_SCOPE) endfunction() # Check compiler flag support. Skip on MSVC, these are all GCC flags. if(NOT CMAKE_CXX_COMPILER_ID MATCHES MSVC) if(NOT DEFINED VERILATOR_CFLAGS OR NOT DEFINED VERILATOR_MT_CFLAGS) include(CheckCXXCompilerFlag) foreach(FLAG @CFG_CXX_FLAGS_CMAKE@) string(MAKE_C_IDENTIFIER ${FLAG} FLAGNAME) _verilator_check_cxx_compiler_flag(${FLAG} ${FLAGNAME}) if(${FLAGNAME}) list(APPEND VERILATOR_CFLAGS $<$:${FLAG}>) endif() endforeach() foreach(FLAG @CFG_LDFLAGS_THREADS_CMAKE@) string(MAKE_C_IDENTIFIER ${FLAG} FLAGNAME) _verilator_check_cxx_libraries("${FLAG}" ${FLAGNAME}) if(${FLAGNAME}) list(APPEND VERILATOR_MT_CFLAGS ${FLAG}) endif() endforeach() endif() endif() if(APPLE) add_link_options(-Wl,-U,__Z15vl_time_stamp64v,-U,__Z13sc_time_stampv) endif() define_property( TARGET PROPERTY VERILATOR_THREADED BRIEF_DOCS "Deprecated and has no effect (ignored)" FULL_DOCS "Deprecated and has no effect (ignored)" ) define_property( TARGET PROPERTY VERILATOR_TRACE_THREADED BRIEF_DOCS "Verilator multithread tracing enabled" FULL_DOCS "Verilator multithread tracing enabled" ) define_property( TARGET PROPERTY VERILATOR_TIMING BRIEF_DOCS "Verilator timing enabled" FULL_DOCS "Verilator timing enabled" ) define_property( TARGET PROPERTY VERILATOR_COVERAGE BRIEF_DOCS "Verilator coverage enabled" FULL_DOCS "Verilator coverage enabled" ) define_property( TARGET PROPERTY VERILATOR_TRACE BRIEF_DOCS "Verilator trace enabled" FULL_DOCS "Verilator trace enabled" ) define_property( TARGET PROPERTY VERILATOR_TRACE_FST BRIEF_DOCS "Verilator FST trace enabled" FULL_DOCS "Verilator FST trace enabled" ) define_property( TARGET PROPERTY VERILATOR_TRACE_SAIF BRIEF_DOCS "Verilator SAIF trace enabled" FULL_DOCS "Verilator SAIF trace enabled" ) define_property( TARGET PROPERTY VERILATOR_TRACE_VCD BRIEF_DOCS "Verilator VCD trace enabled" FULL_DOCS "Verilator VCD trace enabled" ) define_property( TARGET PROPERTY VERILATOR_SYSTEMC BRIEF_DOCS "Verilator SystemC enabled" FULL_DOCS "Verilator SystemC enabled" ) define_property( TARGET PROPERTY VERILATOR_TRACE_STRUCTS BRIEF_DOCS "Verilator trace structs enabled" FULL_DOCS "Verilator trace structs enabled" ) function(json_get_string RET JSON SECTION VARIABLE) string(JSON JV ERROR_VARIABLE STATUS GET "${JSON}" ${SECTION} ${VARIABLE}) if(NOT ${STATUS} STREQUAL "NOTFOUND") set(JV "") endif() set(${RET} ${JV} PARENT_SCOPE) endfunction() function(json_get_bool RET JSON SECTION VARIABLE) string(JSON JV GET "${JSON}" ${SECTION} ${VARIABLE}) if(JV) set(${RET} 1 PARENT_SCOPE) else() set(${RET} 0 PARENT_SCOPE) endif() endfunction() function(json_get_int RET JSON SECTION VARIABLE) string(JSON JV GET "${JSON}" ${SECTION} ${VARIABLE}) set(${RET} ${JV} PARENT_SCOPE) endfunction() function(json_get_submodules SUBMODULES NSUBMODULES JSON) string(JSON JV ERROR_VARIABLE STATUS GET "${JSON}" submodules) if(NOT ${STATUS} STREQUAL "NOTFOUND") set(${SUBMODULES} "" PARENT_SCOPE) set(${NSUBMODULES} 0 PARENT_SCOPE) return() endif() string(JSON L ERROR_VARIABLE STATUS LENGTH "${JSON}" submodules) math(EXPR L "${L}-1") set(${SUBMODULES} ${JV} PARENT_SCOPE) set(${NSUBMODULES} ${L} PARENT_SCOPE) endfunction() function(json_get_list RET JSON SECTION VARIABLE) string(JSON L ERROR_VARIABLE STATUS LENGTH "${JSON}" ${SECTION} ${VARIABLE}) if(NOT ${STATUS} STREQUAL "NOTFOUND" OR NOT ${L}) set(${RET} "" PARENT_SCOPE) return() endif() math(EXPR L "${L}-1") foreach(I RANGE ${L}) string(JSON JV GET "${JSON}" ${SECTION} ${VARIABLE} ${I}) if(NOT JL) string(APPEND JL "${JV}") else() string(APPEND JL " ${JV}") endif() endforeach() set(${RET} ${JL} PARENT_SCOPE) endfunction() function(verilate TARGET) cmake_parse_arguments( VERILATE "COVERAGE;SYSTEMC;TRACE_FST;TRACE_SAIF;TRACE_VCD;TRACE;TRACE_STRUCTS" "PREFIX;TOP_MODULE;THREADS;TRACE_THREADS;DIRECTORY" "SOURCES;VERILATOR_ARGS;INCLUDE_DIRS;OPT_SLOW;OPT_FAST;OPT_GLOBAL" ${ARGN} ) if(VERILATE_TRACE) if(NOT VERILATE_TRACE_VCD) set(VERILATE_TRACE_VCD TRUE) endif() message( DEPRECATION "The `TRACE` argument is deprecated. Please use `TRACE_VCD` instead." ) endif() if(NOT VERILATE_SOURCES) message(FATAL_ERROR "Need at least one source") endif() if(NOT VERILATE_PREFIX) list(LENGTH VERILATE_SOURCES NUM_SOURCES) if(${NUM_SOURCES} GREATER 1) message(WARNING "Specify PREFIX if there are multiple SOURCES") endif() list(GET VERILATE_SOURCES 0 TOPSRC) get_filename_component(_SRC_NAME ${TOPSRC} NAME_WE) string(MAKE_C_IDENTIFIER V${_SRC_NAME} VERILATE_PREFIX) endif() if(VERILATE_TOP_MODULE) list(APPEND VERILATOR_ARGS --top ${VERILATE_TOP_MODULE}) endif() if(VERILATE_THREADS) list(APPEND VERILATOR_ARGS --threads ${VERILATE_THREADS}) endif() if(VERILATE_TRACE_THREADS) list(APPEND VERILATOR_ARGS --trace-threads ${VERILATE_TRACE_THREADS}) endif() if(VERILATE_COVERAGE) list(APPEND VERILATOR_ARGS --coverage) endif() if(VERILATE_SYSTEMC) list(APPEND VERILATOR_ARGS --sc) else() list(APPEND VERILATOR_ARGS --cc) endif() if(VERILATE_TRACE AND VERILATE_TRACE_FST) message(FATAL_ERROR "Cannot have both TRACE and TRACE_FST") endif() if(VERILATE_TRACE_FST AND VERILATE_TRACE_VCD) message(FATAL_ERROR "Cannot have both TRACE_FST and TRACE_VCD") endif() if(VERILATE_TRACE_SAIF AND VERILATE_TRACE_VCD) message(FATAL_ERROR "Cannot have both TRACE_SAIF and TRACE_VCD") endif() if(VERILATE_TRACE) list(APPEND VERILATOR_ARGS --trace-vcd) endif() if(VERILATE_TRACE_FST) list(APPEND VERILATOR_ARGS --trace-fst) endif() if(VERILATE_TRACE_SAIF) list(APPEND VERILATOR_ARGS --trace-saif) endif() if(VERILATE_TRACE_VCD) list(APPEND VERILATOR_ARGS --trace-vcd) endif() if(VERILATE_TRACE_STRUCTS) list(APPEND VERILATOR_ARGS --trace-structs) endif() foreach(INC ${VERILATE_INCLUDE_DIRS}) list(APPEND VERILATOR_ARGS -y "${INC}") endforeach() string(TOLOWER ${CMAKE_CXX_COMPILER_ID} COMPILER) if(COMPILER STREQUAL "appleclang") set(COMPILER clang) elseif(NOT COMPILER MATCHES "^msvc$|^clang$") set(COMPILER gcc) endif() set(OBJCACHE "" CACHE STRING "Path for ccache, auto-detected if empty") option(OBJCACHE_ENABLED "Compile Verilator with ccache" ON) if(OBJCACHE_ENABLED) if(OBJCACHE STREQUAL "") find_program(OBJCACHE_PATH ccache) if(OBJCACHE_PATH STREQUAL "OBJCACHE_PATH-NOTFOUND") set(OBJCACHE_PATH "") endif() else() set(OBJCACHE_PATH "${OBJCACHE}") endif() if(NOT OBJCACHE_PATH STREQUAL "") execute_process( COMMAND "${OBJCACHE_PATH}" --version OUTPUT_VARIABLE objcache_version ) string( REGEX MATCH "[^\n\r]+" objcache_version "${objcache_version}" ) message( STATUS "Found ccache: ${OBJCACHE_PATH} (\"${objcache_version}\")" ) set_property(GLOBAL PROPERTY RULE_LAUNCH_COMPILE "${OBJCACHE_PATH}") endif() endif() get_target_property(BINARY_DIR "${TARGET}" BINARY_DIR) get_target_property(TARGET_NAME "${TARGET}" NAME) set(VDIR "${BINARY_DIR}/CMakeFiles/${TARGET_NAME}.dir/${VERILATE_PREFIX}.dir" ) if(VERILATE_DIRECTORY) set(VDIR "${VERILATE_DIRECTORY}") endif() file(MAKE_DIRECTORY ${VDIR}) set(VERILATOR_COMMAND "${CMAKE_COMMAND}" -E env "VERILATOR_ROOT=${VERILATOR_ROOT}" "${VERILATOR_BIN}" --compiler ${COMPILER} --prefix ${VERILATE_PREFIX} --Mdir ${VDIR} --make json ${VERILATOR_ARGS} ${VERILATE_VERILATOR_ARGS} ${VERILATE_SOURCES} ) set(VARGS_FILE "${VDIR}/verilator_args.txt") set(VCMAKE "${VDIR}/${VERILATE_PREFIX}.cmake") set(VCMAKE_COPY "${VDIR}/${VERILATE_PREFIX}_copy.cmake") if(NOT EXISTS "${VARGS_FILE}" OR NOT EXISTS "${VCMAKE_COPY}") set(VERILATOR_OUTDATED ON) else() file(READ "${VARGS_FILE}" PREVIOUS_VERILATOR_COMMAND) if(NOT VERILATOR_COMMAND STREQUAL PREVIOUS_VERILATOR_COMMAND) set(VERILATOR_OUTDATED ON) endif() endif() if(VERILATOR_OUTDATED) message(STATUS "Executing Verilator...") execute_process( COMMAND ${VERILATOR_COMMAND} WORKING_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}" RESULT_VARIABLE _VERILATOR_RC OUTPUT_VARIABLE _VERILATOR_OUTPUT ERROR_VARIABLE _VERILATOR_OUTPUT ) if(_VERILATOR_RC) string( REPLACE ";" " " VERILATOR_COMMAND_READABLE "${VERILATOR_COMMAND}" ) message("Verilator command: \"${VERILATOR_COMMAND_READABLE}\"") message("Output:\n${_VERILATOR_OUTPUT}") message( FATAL_ERROR "Verilator command failed (return code=${_VERILATOR_RC})" ) endif() file(READ ${VDIR}/${VERILATE_PREFIX}.json MANIFEST) json_get_string(JSYSTEM_PERL "${MANIFEST}" system perl) json_get_string(JSYSTEM_PYTHON3 "${MANIFEST}" system python3) json_get_string(JSYSTEM_VERILATOR_ROOT "${MANIFEST}" system verilator_root) json_get_string(JSYSTEM_VERILATOR_SOLVER "${MANIFEST}" system verilator_solver) json_get_list(JOPTIONS_CFLAGS "${MANIFEST}" options cflags) json_get_list(JOPTIONS_LDFLAGS "${MANIFEST}" options ldflags) json_get_bool(JOPTIONS_SYSTEM_C "${MANIFEST}" options system_c) json_get_bool(JOPTIONS_COVERAGE "${MANIFEST}" options coverage) json_get_bool(JOPTIONS_USE_TIMING "${MANIFEST}" options use_timing) json_get_int(JOPTIONS_THREADS "${MANIFEST}" options threads) json_get_bool(JOPTIONS_TRACE_FST "${MANIFEST}" options trace_fst) json_get_bool(JOPTIONS_TRACE_SAIF "${MANIFEST}" options trace_saif) json_get_bool(JOPTIONS_TRACE_VCD "${MANIFEST}" options trace_vcd) json_get_list(JSOURCES_GLOBAL "${MANIFEST}" sources global) json_get_list(JSOURCES_CLASSES_SLOW "${MANIFEST}" sources classes_slow) json_get_list(JSOURCES_CLASSES_FAST "${MANIFEST}" sources classes_fast) json_get_list(JSOURCES_SUPPORT_SLOW "${MANIFEST}" sources support_slow) json_get_list(JSOURCES_SUPPORT_FAST "${MANIFEST}" sources support_fast) json_get_list(JSOURCES_USER_CLASSES "${MANIFEST}" sources user_classes) json_get_list(JSOURCES_DEPS "${MANIFEST}" sources deps) file( WRITE ${VDIR}/${VERILATE_PREFIX}.cmake "# Verilated -*- CMake -*-\n" "# DESCRIPTION: Verilator output: CMake include script with class lists\n" "#\n" "# This CMake script lists generated Verilated files, for including in higher level CMake scripts.\n" "# This file is meant to be consumed by the verilate() function,\n" "# which becomes available after executing `find_package(verilator).\n\n" "### Constants...\n" "set(PERL \"${JSYSTEM_PERL}\" CACHE FILEPATH \"Perl executable (from \$PERL, defaults to 'perl' if not set)\")\n" "set(PYTHON3 \"${JSYSTEM_PYTHON3}\" CACHE FILEPATH \"Python3 executable (from \$PYTHON3, defaults to 'python3' if not set)\")\n" "set(VERILATOR_ROOT \"${JSYSTEM_VERILATOR_ROOT}\" CACHE PATH \"Path to Verilator kit (from $VERILATOR_ROOT)\")\n" "set(VERILATOR_SOLVER \"${JSYSTEM_VERILATOR_SOLVER}\" CACHE STRING \"Default SMT solver for constrained randomization (from \$VERILATOR_SOLVER)\")\n\n" "### Compiler flags...\n" "# User CFLAGS (from -CFLAGS on Verilator command line)\n" "set(${VERILATE_PREFIX}_USER_CFLAGS ${JOPTIONS_CFLAGS})\n" "# User LDLIBS (from -LDFLAGS on Verilator command line)\n" "set(${VERILATE_PREFIX}_USER_LDLIBS ${JOPTIONS_LDFLAGS})\n\n" "### Switches...\n" "# SystemC output mode? 0/1 (from --sc)\n" "set(${VERILATE_PREFIX}_SC ${JOPTIONS_SYSTEM_C})\n" "# Coverage output mode? 0/1 (from --coverage)\n" "set(${VERILATE_PREFIX}_COVERAGE ${JOPTIONS_COVERAGE})\n" "# Timing mode? 0/1\n" "set(${VERILATE_PREFIX}_TIMING ${JOPTIONS_USE_TIMING})\n" "# Threaded output mode? 1/N threads (from --threads)\n" "set(${VERILATE_PREFIX}_THREADS ${JOPTIONS_THREADS})\n" "# FST Tracing output mode? 0/1 (from --trace-fst)\n" "set(${VERILATE_PREFIX}_TRACE_FST ${JOPTIONS_TRACE_FST})\n\n" "# SAIF Tracing output mode? 0/1 (from --trace-saif)\n" "set(${VERILATE_PREFIX}_TRACE_SAIF ${JOPTIONS_TRACE_SAIF})\n\n" "# VCD Tracing output mode? 0/1 (from --trace-vcd)\n" "set(${VERILATE_PREFIX}_TRACE_VCD ${JOPTIONS_TRACE_VCD})\n" "### Sources...\n" "# Global classes, need linked once per executable\n" "set(${VERILATE_PREFIX}_GLOBAL ${JSOURCES_GLOBAL})\n" "# Generated module classes, non-fast-path, compile with low/medium optimization\n" "set(${VERILATE_PREFIX}_CLASSES_SLOW ${JSOURCES_CLASSES_SLOW})\n" "# Generated module classes, fast-path, compile with highest optimization\n" "set(${VERILATE_PREFIX}_CLASSES_FAST ${JSOURCES_CLASSES_FAST})\n" "# Generated support classes, non-fast-path, compile with low/medium optimization\n" "set(${VERILATE_PREFIX}_SUPPORT_SLOW ${JSOURCES_SUPPORT_SLOW})\n" "# Generated support classes, fast-path, compile with highest optimization\n" "set(${VERILATE_PREFIX}_SUPPORT_FAST ${JSOURCES_SUPPORT_FAST})\n" "# All dependencies\n" "set(${VERILATE_PREFIX}_DEPS ${JSOURCES_DEPS})\n" "# User .cpp files (from .cpp's on Verilator command line)\n" "set(${VERILATE_PREFIX}_USER_CLASSES ${JSOURCES_USER_CLASSES})\n" ) json_get_submodules(JSUBMODULES JNSUBMODULES "${MANIFEST}") if(JNSUBMODULES) file( APPEND ${VDIR}/${VERILATE_PREFIX}.cmake "# Verilate hierarchical blocks\n" "get_target_property(TOP_TARGET_NAME \"\${TARGET}\" NAME)\n" ) foreach(I RANGE ${JNSUBMODULES}) json_get_string(JSUBMODULE_PREFIX "${JSUBMODULES}" ${I} prefix) json_get_string(JSUBMODULE_TOP "${JSUBMODULES}" ${I} top) json_get_list(JSUBMODULE_DEPS "${JSUBMODULES}" ${I} deps) json_get_string(JSUBMODULE_DIRECTORY "${JSUBMODULES}" ${I} directory) json_get_list(JSUBMODULE_SOURCES "${JSUBMODULES}" ${I} sources) json_get_list(JSUBMODULE_CFLAGS "${JSUBMODULES}" ${I} cflags) json_get_string(JSUBMODILE_VERILATOR_ARGS "${JSUBMODULES}" ${I} verilator_args) set(SUBMODULE_CMAKE "") set(SUBMODULE_VERILATE_ARGS "") if(NOT ${I} STREQUAL ${JNSUBMODULES}) string( APPEND SUBMODULE_CMAKE "add_library(${JSUBMODULE_PREFIX} STATIC)\n" "target_link_libraries(\${TOP_TARGET_NAME} PRIVATE ${JSUBMODULE_PREFIX})\n" ) if(JSUBMODULE_DEPS) string( APPEND SUBMODULE_CMAKE "target_link_libraries(${JSUBMODULE_PREFIX} INTERFACE ${JSUBMODULE_DEPS})\n" ) endif() string( APPEND SUBMODULE_VERILATE_ARGS "${JSUBMODULE_PREFIX} PREFIX ${JSUBMODULE_PREFIX} TOP_MODULE ${JSUBMODULE_TOP} DIRECTORY ${JSUBMODULE_DIRECTORY} SOURCES ${JSUBMODULE_SOURCES}" ) else() string( APPEND SUBMODULE_CMAKE "# Verilate the top module that refers to lib-create wrappers of above\n" ) string( APPEND SUBMODULE_VERILATE_ARGS "\${TOP_TARGET_NAME} PREFIX ${JSUBMODULE_PREFIX} TOP_MODULE ${JSUBMODULE_TOP} DIRECTORY ${JSUBMODULE_DIRECTORY} SOURCES ${JSUBMODULE_SOURCES}" ) endif() if(JSUBMODILE_VERILATOR_ARGS) string( APPEND SUBMODULE_VERILATE_ARGS " VERILATOR_ARGS -f ${JSUBMODILE_VERILATOR_ARGS}" ) endif() if(JSUBMODULE_CFLAGS) string( APPEND SUBMODULE_VERILATE_ARGS " -CFLAGS ${JSUBMODULE_CFLAGS}" ) endif() file( APPEND ${VDIR}/${VERILATE_PREFIX}.cmake "${SUBMODULE_CMAKE}" "verilate(${SUBMODULE_VERILATE_ARGS})\n" ) endforeach() endif() execute_process( COMMAND "${CMAKE_COMMAND}" -E copy "${VCMAKE}" "${VCMAKE_COPY}" ) endif() file(WRITE "${VARGS_FILE}" "${VERILATOR_COMMAND}") include("${VCMAKE_COPY}") set(GENERATED_C_SOURCES ${${VERILATE_PREFIX}_CLASSES_FAST} ${${VERILATE_PREFIX}_CLASSES_SLOW} ${${VERILATE_PREFIX}_SUPPORT_FAST} ${${VERILATE_PREFIX}_SUPPORT_SLOW} ) # No need for .h's as the .cpp will get written same time set(GENERATED_SOURCES ${GENERATED_C_SOURCES}) add_custom_command( OUTPUT ${GENERATED_SOURCES} "${VCMAKE}" COMMAND ${VERILATOR_COMMAND} WORKING_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}" DEPENDS "${VERILATOR_BIN}" ${${VERILATE_PREFIX}_DEPS} VERBATIM ) # Reconfigure if file list has changed # (check contents rather than modified time to avoid unnecessary reconfiguration) add_custom_command( OUTPUT "${VCMAKE_COPY}" COMMAND "${CMAKE_COMMAND}" -E copy_if_different "${VCMAKE}" "${VCMAKE_COPY}" DEPENDS "${VCMAKE}" VERBATIM ) if(${VERILATE_PREFIX}_COVERAGE) # If any verilate() call specifies COVERAGE, define VM_COVERAGE in the final build set_property(TARGET ${TARGET} PROPERTY VERILATOR_COVERAGE ON) endif() if(${VERILATE_PREFIX}_SC) # If any verilate() call specifies SYSTEMC, define VM_SC in the final build set_property(TARGET ${TARGET} PROPERTY VERILATOR_SYSTEMC ON) endif() if(${VERILATE_PREFIX}_TRACE_FST) # If any verilate() call specifies TRACE_FST, define VM_TRACE_FST in the final build set_property(TARGET ${TARGET} PROPERTY VERILATOR_TRACE ON) set_property(TARGET ${TARGET} PROPERTY VERILATOR_TRACE_FST ON) endif() if(${VERILATE_PREFIX}_TRACE_SAIF) # If any verilate() call specifies TRACE_SAIF, define VM_TRACE_SAIF in the final build set_property(TARGET ${TARGET} PROPERTY VERILATOR_TRACE ON) set_property(TARGET ${TARGET} PROPERTY VERILATOR_TRACE_SAIF ON) endif() if(${VERILATE_PREFIX}_TRACE_VCD) # If any verilate() call specifies TRACE, define VM_TRACE_VCD in the final build set_property(TARGET ${TARGET} PROPERTY VERILATOR_TRACE ON) set_property(TARGET ${TARGET} PROPERTY VERILATOR_TRACE_VCD ON) endif() if(${VERILATE_PREFIX}_TRACE_STRUCTS) set_property(TARGET ${TARGET} PROPERTY VERILATOR_TRACE_STRUCTS ON) endif() # Add the compile flags only on Verilated sources target_include_directories(${TARGET} PUBLIC ${VDIR}) target_sources( ${TARGET} PRIVATE ${GENERATED_SOURCES} "${VCMAKE_COPY}" ${${VERILATE_PREFIX}_GLOBAL} ${${VERILATE_PREFIX}_USER_CLASSES} ) foreach(_VSOURCE ${VERILATE_SOURCES} ${${VERILATE_PREFIX}_DEPS}) get_filename_component(_VSOURCE "${_VSOURCE}" ABSOLUTE BASE_DIR) list(APPEND VHD_SOURCES "${_VSOURCE}") endforeach() target_sources(${TARGET} PRIVATE ${VHD_SOURCES}) # Add the compile flags only on Verilated sources foreach( VSLOW ${${VERILATE_PREFIX}_CLASSES_SLOW} ${${VERILATE_PREFIX}_SUPPORT_SLOW} ) foreach(OPT_SLOW ${VERILATE_OPT_SLOW} ${${VERILATE_PREFIX}_USER_CFLAGS}) set_property( SOURCE "${VSLOW}" APPEND_STRING PROPERTY COMPILE_FLAGS " ${OPT_SLOW}" ) endforeach() endforeach() foreach( VFAST ${${VERILATE_PREFIX}_CLASSES_FAST} ${${VERILATE_PREFIX}_SUPPORT_FAST} ) foreach(OPT_FAST ${VERILATE_OPT_FAST} ${${VERILATE_PREFIX}_USER_CFLAGS}) set_property( SOURCE "${VFAST}" APPEND_STRING PROPERTY COMPILE_FLAGS " ${OPT_FAST}" ) endforeach() endforeach() foreach(VGLOBAL ${${VERILATE_PREFIX}_GLOBAL}) foreach( OPT_GLOBAL ${VERILATE_OPT_GLOBAL} ${${VERILATE_PREFIX}_USER_CFLAGS} ) set_property( SOURCE "${VGLOBAL}" APPEND_STRING PROPERTY COMPILE_FLAGS " ${OPT_GLOBAL}" ) endforeach() endforeach() target_include_directories( ${TARGET} PUBLIC "${VERILATOR_ROOT}/include" "${VERILATOR_ROOT}/include/vltstd" ) target_compile_definitions( ${TARGET} PRIVATE VM_COVERAGE=$> VM_SC=$> VM_TRACE=$> VM_TRACE_VCD=$> VM_TRACE_FST=$> VM_TRACE_SAIF=$> ) target_link_libraries(${TARGET} PUBLIC ${${VERILATE_PREFIX}_USER_LDLIBS}) target_link_libraries(${TARGET} PUBLIC ${VERILATOR_MT_CFLAGS}) target_compile_features(${TARGET} PRIVATE cxx_std_11) if(${VERILATE_PREFIX}_TIMING) check_cxx_compiler_flag(-fcoroutines-ts COROUTINES_TS_FLAG) target_compile_options( ${TARGET} PRIVATE $,-fcoroutines-ts,-fcoroutines> ) endif() endfunction() function(_verilator_find_systemc) if(NOT TARGET Verilator::systemc) # Find SystemC include file "systemc.h" in the following order: # 1. SYSTEMC_INCLUDE (environment) variable # 2. SYSTEMC_ROOT (environment) variable # 3. SYSTEMC (environment) variable # 4. Use CMake module provided by SystemC installation # (eventually requires CMAKE_PREFIX_PATH set) find_path( SYSTEMC_INCLUDEDIR NAMES systemc.h HINTS "${SYSTEMC_INCLUDE} " ENV SYSTEMC_INCLUDE ) find_path( SYSTEMC_INCLUDEDIR NAMES systemc.h HINTS "${SYSTEMC_ROOT}" ENV SYSTEMC_ROOT PATH_SUFFIXES include ) find_path( SYSTEMC_INCLUDEDIR NAMES systemc.h HINTS "${SYSTEMC}" ENV SYSTEMC PATH_SUFFIXES include ) # Find SystemC library in the following order: # 1. SYSTEMC_LIBDIR (environment) variable # 2. SYSTEMC_ROOT (environment) variable # 3. SYSTEMC (environment) variable # 4. Use CMake module provided by SystemC installation # (eventually requires CMAKE_PREFIX_PATH set) # Find SystemC using include and library paths find_library( SYSTEMC_LIBRARY NAMES systemc HINTS "${SYSTEMC_LIBDIR}" ENV SYSTEMC_LIBDIR ) find_library( SYSTEMC_LIBRARY NAMES systemc HINTS "${SYSTEMC_ROOT}" ENV SYSTEMC_ROOT PATH_SUFFIXES lib ) find_library( SYSTEMC_LIBRARY NAMES systemc HINTS "${SYSTEMC}" ENV SYSTEMC PATH_SUFFIXES lib ) if(SYSTEMC_INCLUDEDIR AND SYSTEMC_LIBRARY) add_library(Verilator::systemc INTERFACE IMPORTED) set_target_properties( Verilator::systemc PROPERTIES INTERFACE_INCLUDE_DIRECTORIES "${SYSTEMC_INCLUDEDIR}" INTERFACE_LINK_LIBRARIES "${SYSTEMC_LIBRARY}" ) return() endif() find_package(SystemCLanguage QUIET) if(SystemCLanguage_FOUND) add_library(Verilator::systemc INTERFACE IMPORTED) set_target_properties( Verilator::systemc PROPERTIES INTERFACE_LINK_LIBRARIES "SystemC::systemc" ) return() endif() message( "SystemC not found. This can be fixed by doing either of the following steps:" ) message( "- set the SYSTEMC_INCLUDE and SYSTEMC_LIBDIR (environment) variables; or" ) message("- set SYSTEMC_ROOT (environment) variable; or") message("- set SYSTEMC (environment) variable; or") message( "- use the CMake module of your SystemC installation (may require CMAKE_PREFIX_PATH)" ) message(FATAL_ERROR "SystemC not found") endif() endfunction() function(verilator_link_systemc TARGET) _verilator_find_systemc() target_link_libraries("${TARGET}" PUBLIC Verilator::systemc) target_compile_options( ${TARGET} PRIVATE $ENV{SYSTEMC_CXX_FLAGS} ${SYSTEMC_CXX_FLAGS} ) endfunction() function(verilator_generate_key OUTPUT_VARIABLE) execute_process( COMMAND ${VERILATOR_BIN} --generate-key OUTPUT_VARIABLE KEY_VAL RESULT_VARIABLE KEY_RET ) if(KEY_RET) message(FATAL_ERROR "verilator --generate-key failed") endif() string(STRIP ${KEY_VAL} KEY_VAL) set(${OUTPUT_VARIABLE} ${KEY_VAL} PARENT_SCOPE) endfunction() verilator-5.042/.clang-tidy0000644000542200017500000000304115101701376016144 0ustar mahmoudyfreeshellChecks: '*,-hicpp*,-android-cloexec-fopen,-cert-dcl50-cpp,-cert-env33-c,-cert-err34-c,-cert-err58-cpp,-clang-analyzer-core.UndefinedBinaryOperatorResult,-clang-analyzer-security*,-cppcoreguidelines-avoid-magic-numbers,-cppcoreguidelines-no-malloc,-cppcoreguidelines-owning-memory,-cppcoreguidelines-pro-bounds-array-to-pointer-decay,-cppcoreguidelines-pro-bounds-array-to-pointer-decay,-cppcoreguidelines-pro-bounds-constant-array-index,-cppcoreguidelines-pro-bounds-pointer-arithmetic,-cppcoreguidelines-pro-type-const-cast,-cppcoreguidelines-pro-type-reinterpret-cast,-cppcoreguidelines-pro-type-static-cast-downcast,-cppcoreguidelines-pro-type-union-access,-cppcoreguidelines-pro-type-vararg,-cppcoreguidelines-special-member-functions,-fuchsia-*,-google-default-arguments,-google-readability-todo,-google-runtime-references,-llvm-header-guard,-llvm-include-order,-misc-string-integer-assignment,-misc-string-literal-with-embedded-nul,-modernize-use-auto,-modernize-use-trailing-return-type,-readability-braces-around-statements,-readability-container-size-empty,-readability-delete-null-pointer,-readability-else-after-return,-readability-implicit-bool-conversion,-readability-named-parameter,-readability-static-accessed-through-instance,-llvmlibc-*,-altera-*' WarningsAsErrors: '' HeaderFilterRegex: '' FormatStyle: none CheckOptions: - key: google-readability-braces-around-statements.ShortStatementLines value: '2' - key: google-readability-namespace-comments.SpacesBeforeComments value: '2' verilator-5.042/Changes0000644000542200017500000072434515101701376015424 0ustar mahmoudyfreeshell.. for github, vim: syntax=reStructuredText =============================== Revision History and Change Log =============================== The changes in each Verilator version are described below. The contributors that suggested or implemented a given issue are shown in []. Thanks! Verilator 5.042 2025-11-02 ========================== **Other:** * Add HIERPARAM error on hierarchical parameter values (#1626) (#6456) (#6484) (#6587) (#6609) (#6621) (#6623). [Todd Strader] [Luca Rufer] [Paul Swirhun] * Add error on zero/negative unpacked dimensions (#1642). [Stefan Wallentowitz] * Add verilator_gantt profiling of DPI imports (#3084). [Geza Lore] * Add ASSIGNEQEXPR when use `=` inside expressions (#5567). [Ethan Sifferman] * Add error on non-packed struct randc (#5999). [Seth Pellegrino] * Add configure `--enable-dev-asan` to compile verilator_bin with the address sanitizer (#6404). [Geza Lore] * Add $(LDFLAGS) and $(LIBS) to when building shared libraries (#6425) (#6426). [Ahmed El-Mahmoudy] * Add IMPLICITSTATIC also on procedure variables. * Add FUNCTIMCTL error on function invoking task or time-controlling statements (#6385). * Add error on `virtual new` (#6486). [Alex Solomatnikov] * Add error on ranges with tristate values (#6534). [Alex Solomatnikov] * Add NORETURN warning on functions without return values (#6534). [Alex Solomatnikov] * Add `--aslr` and `--no-aslr` options. * Add `$cpure` (#6580). [Igor Zaworski, Antmicro Ltd.] * Add `--preproc-defines`. * Deprecate sensitivity list on public_flat_rw attributes (#6443). [Geza Lore] * Deprecate clocker attribute and --clk option (#6463). [Geza Lore] * Deprecate '--make cmake' option (#6540). [Geza Lore] * Change default `--expand-limit` to 256 (#3419). * Change developer coverage flow and add configure `--enable-dev-gcov` (#6526). [Geza Lore] * Change `verilator_difftree` to return exit code 1 on mismatch, 2 on error. * Change default thread pool sizes to respect processor affinity (#6604). [Geza Lore] * Change `--preproc-comments` to be new name of `--pp-comments` option. * Support modports referencing clocking blocks (#4555) (#6436). [Ryszard Rozak, Antmicro Ltd.] * Support class package reference on pattern keys (#5653). [Todd Strader] * Support digits in `$sscanf` field width formats (#6083). [Iztok Jeras] * Support pure functions in sensitivity lists (#6393). [Krzysztof Bieganski, Antmicro Ltd.] * Support simple alias statements (#6339) (#6501). [Ryszard Rozak, Antmicro Ltd.] * Support simple cycle delay sequence expressions inside properties (#6508). [Bartłomiej Chmiel, Antmicro Ltd.] * Support impure expressions in `inside` (#6562). [Igor Zaworski, Antmicro Ltd.] * Support `case` impure expressions (#6563). [Igor Zaworski, Antmicro Ltd.] * Support dotted access to ports of a direct hier_block instance. (#6595). [Geza Lore] * Improve `lint_off` to allow multiple messages and comments (#2755). * Improve automatic selection of logic for DFG synthesis (#6370). [Geza Lore] * Improve `covergroup with function sample` handling (#6387). [Jakub Wasilewski] * Improve DFG type system (#6390). [Geza Lore] * Improve DFG variable removal and temporary insertion (#6401). [Geza Lore] * Improve memory usage of statistics (#6513). [Geza Lore] * Improve conditional merging to preserve branch prediction. [Geza Lore] * Optimize duplicate 'if' and '?:' conditions (#3807) (#6495) * Optimize dead functions in more cases (#6380) (#6430). [Artur Bieniek, Antmicro Ltd.] * Optimize constant folding in wide expression expansion (#6381). [Geza Lore] * Fix `--trace-max-width` and increase to 4096. (#2385). * Fix missing BLKSEQ when connecting module port to array (#2973). * Fix LATCH warning with CASEINCOMPLETE (#3301). * Fix unused parameterized class causing internal error (#4013). [Alberto Del Rio] * Fix false CONSTVAR error on initializers (#4992). * Fix hierarchical references with parameterized modules and interfaces (#5649) (#6566). [Ryszard Rozak, Antmicro Ltd.] * Fix interface exposure with `--public-depth` or `--trace-depth` (#5758). * Fix cell scoping performance (#6059). [Jerry Tianchen] * Fix hierarchical `--prof-pgo` (#6213). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix while loop hang on timing-delayed assignment (#6343) (#6354). [Krzysztof Bieganski, Antmicro Ltd.] * Fix driver analysis of partially assigned variables (#6364) (#6378). [Geza Lore] * Fix V3Hash MacOS ambiguity (#6350). [Lan Zongwei] * Fix cmake APPLE variable (#6351). [Lan Zongwei] * Fix randomize local after parameters applied (#6371). [Alex Solomatnikov] * Fix package imports not found after parameters applied (#6373). [Alex Solomatnikov] * Fix deep shift pattern performance (#6379) (#6420). [Geza Lore] * Fix COVERAGEIGN-ignored `get_inst_coverage` and other covergroup methods (#6383). [Alex Solomatnikov] * Fix error when modport variable is unresolved (#6386). [Ryszard Rozak, Antmicro Ltd.] * Fix resolving parameters (#6388) (#6418) (#6421) (#6438) (#6429). [Artur Bieniek, Antmicro Ltd.] * Fix wire array with initial assignment (#6391). [Alex Solomatnikov] * Fix import of class with default params (#6396) (#6410) (#6413). [Krzysztof Bieganski, Antmicro Ltd.] * Fix use after free in elaboration (#6403). [Geza Lore] * Fix address sanitizer issues (#6406). [Geza Lore] * Fix timing control under fork under function (#6407). [Krzysztof Bieganski, Antmicro Ltd.] * Fix memory leaks and reduce requirements (#6411) (#6417) (#6419) (#6437) (#6439) (#6517). [Geza Lore] * Fix parameter implicit type from string (#6414). [Alex Solomatnikov] * Fix parsing for sequence expressions (#6427). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix parameterized class super functions (#6431) (#6438). [Artur Bieniek, Antmicro Ltd.] * Fix external function declarations with class typedef references (#6433). * Fix internal error on out-of-bounds real array access. * Fix pre/post increments in assertions (#6434). * Fix elaboration displays with `%m` and some `%p` (#6445) (#6451). [Alex Solomatnikov] * Fix cast in gdbinit.py (#6447). [Artur Bieniek, Antmicro Ltd.] * Fix false unique assertions on `else ;` (#6450). [Don Owen] * Fix loss of clock attribute in DFG variable removal (#6453). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix data types of method calls without parenthesis (#6457). [Artur Bieniek, Antmicro Ltd.] * Fix segfault on unsupported PLI calls (#6458). [Krzysztof Bieganski, Antmicro Ltd.] * Fix false assertion failure on failed DFG driver tracing (#6459). [Geza Lore] * Fix side effects when using select (#6460). [Igor Zaworski, Antmicro Ltd.] * Fix timeprecision backward assignment (#6469). [Artur Bieniek, Antmicro Ltd.] * Fix splitting hierarchically referenced variables (#6475). [Ryszard Rozak, Antmicro Ltd.] * Fix Windows compilation of Verilator with spaces in the path (#6477). [Fabian Keßler-Schulz] * Fix PROTOTYPEMIS error on implicit logic (#6482). [Alex Solomatnikov] * Fix configure misdetecting C++14 (#6488) (#6515). [Thomas O'Keeffe] * Fix false BLKSEQ on non-edged sensitivity list (#6492). [Oron Port] * Fix .vlt public_flat* and others to support long identifier names (#6516). [Szymon Gizler, Antmicro Ltd.] * Fix always_ff on constants (#6519). [Todd Strader] * Fix fault on operations on uninitialized strings (#6520). [Artur Bieniek, Antmicro Ltd.] * Fix find_index methods of associative arrays (#6525). [Ryszard Rozak, Antmicro Ltd.] * Fix parsing of `eventually[]` and property expression memory leaks (#6530). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix memory leak for unsupported `$past` (#6535). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix inconsistent force assignment (#6541). [Artur Bieniek, Antmicro Ltd.] * Fix DFG circular driver tracing with partial assignments. [Geza Lore] * Fix passing typedef value as parameter (#6543) (#6547). [Igor Zaworski, Antmicro Ltd.] * Fix indent error on quoted strings (#6544). * Fix incorrect nested interface-class error (#6549). [Matthew Ballance] * Fix std::process::get_randstate to not affect random stability (#6550) (#6565). [Aleksander Kiryk] * Fix exit code signal number reporting (#6554). [Artur Bieniek, Antmicro Ltd.] * Fix `$finish` inside fork blocks (#6555). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix single element unpacked array DPI parameters. [Geza Lore] * Fix DFG synthesis non-determinism (#6557) (#6568). [Todd Strader] * Fix side effects for improved function/task/process purity (#6559). [Igor Zaworski, Antmicro Ltd.] * Fix excessive logic replication in DFG circular driver tracing (#6561) (#6594). [Geza Lore] * Fix hierarchical with parameterized instances under hier block (#6572). [Geza Lore] * Fix segfault on type casts (#6574). [David Moberg] * Fix references to interfaces containing generate blocks (#6579). [Ryszard Rozak, Antmicro Ltd.] * Fix missing net type mappings in FST traces (#6582) (#6583). [Matt Stroud] * Fix function call expression coverage (#6589). [Todd Strader] * Fix V3Life eliminating assignments across timing controls (#6593) (#6596). [Geza Lore] * Fix incorrectly resuming process waiting on multiple events (#6597). [Geza Lore] * Fix `--hierarchical` with `--binary` (#6602). [Geza Lore] * Fix mis-ignoring virtual interface member triggers (#5116 reopened) (#6613). [Geza Lore] * Fix ENUMVALUE warning when overriding parameter using `-G/-pvalue` options. [Geza Lore] * Fix `-G` and `-pvalue` with `--hierarchical`. [Geza Lore] * Fix waiving messages with empty contents (#6610). [Yoshitomo KANEDA] * Fix constant-arrayed instance parameters (#6614). [Alex Solomatnikov] Verilator 5.040 2025-08-30 ========================== **Other:** * Add ENUMITEMWIDTH error, and apply to X-extended and ranged values. * Add NOEFFECT warning, replacing previous `foreach` error. * Add SPECIFYIGN warning for specify constructs that were previously silently ignored. * Add PARAMNODEFAULT error, for parameters without defaults. * Add enum base data type, wire data type, and I/O versus data declaration checking per IEEE. * Add PROTOTYPEMIS error on missing and mismatching prototypes (#6206) (#6207). [Alex Solomatnikov] * Add error when trying to assign class object to variable of non-class types (#6237). [Igor Zaworski, Antmicro Ltd.] * Add ALWNEVER warning, for `always @*` that never execute (#6291). * Add separate coverage counters for toggles 0->1 and 1->0 (#6086). [Ryszard Rozak, Antmicro Ltd.] * Add error on class 'function static'. * Add error on force/release non-constant selects. * Add `-DVERILATOR=1` definition to compiler flags when using verilated.mk. * Support member-level triggers for virtual interfaces (#5166) (#6148). [Yilou Wang] * Support unassigned virtual interfaces (#5265) (#6245). [Szymon Gizler, Antmicro Ltd.] * Support randomization of scope variables with 'std::randomize()' (#5438) (#6185). [Yilou Wang] * Support disabling a fork in additional contexts (#5432 partial) (#6174) (#6183). [Ryszard Rozak, Antmicro Ltd.] * Support bit queue streaming (#5830) (#6103). [Paul Swirhun] * Support `$fread` with missing start (#6125). [Iztok Jeras] * Support unpacked array `with` methods (#6134). * Support Verilog real ports as SystemC double ports (#6136) (#6158). [George Polack] * Support `$countones` in constraints (#6144 partial) (#6235). [Ryszard Rozak, Antmicro Ltd.] * Support disable dotted references (#6154). [Ryszard Rozak, Antmicro Ltd.] * Support randomize() on class member selects (#6161) (#6195). [Igor Zaworski, Ryszard Rozak, Antmicro Ltd.] * Support multiple variables on RHS of a `force` assignment (#6163). [Artur Bieniek, Antmicro Ltd.] * Support covergroup extends, etc., as unsupported (#6160). [Artur Bieniek, Antmicro Ltd.] * Support parameter resolution of 1D unpacked array slices (#6257) (#6268). [Michael Bedford Taylor] * Support generic interfaces (#6272). [Igor Zaworski, Antmicro Ltd.] * Support disabling a fork from within that fork (#6314). [Ryszard Rozak, Antmicro Ltd.] * Support future sampled value functions. * Support simple disable within task (#6334). [Ryszard Rozak, Antmicro Ltd.] * Support recursive constant functions. * Change control file `public_flat_*` and other signal attributes to support __ in names (#6140). * Change runtime to exit() instead of abort(), unless under +verilated+debug. * Change `$display("%p")` to remove space after `}`. * Improve `--skip-identical` to skip on identical input file contents (#6109). * Improve testing on FreeBSD (#6328). [Aleksander Kiryk] * Optimize to return memory when using -build (#6192) (#6226). [Michael B. Taylor] * Optimize 2 ** X to 1 << X if base is signed (#6203). [Max Wipfli] * Optimize more complex combinational logic in DFG (#6205) (#6209) (#6298). [Geza Lore] * Optimize combinational cycles through arrays in DFG (#6210). [Geza Lore] * Optimize variable removal in scoped DFG (#6260). [Geza Lore] * Optimize acyclic DFG components into the original acyclic sub-graph. (#6261). [Geza Lore] * Optimize multiplexers in DFG synthesis (#6331). [Geza Lore] * Optimize interfaces in DFG (#6332). [Geza Lore] * Optimize logic in non-virtual interfaces with DFG (#6347). [Geza Lore] * Fix loop initialization visibility outside loop (#4237). * Fix constructor parameters in inheritance hierarchies (#6036) (#6070). [Petr Nohavica] * Fix replicate of negative giving 'REPLICATE has no expected width' internal error (#6048) (#6229). * Fix cmake `-Wno` compiler flag testing (#6145). [Martin Stadler] * Fix class extends dotted error (#6162). [Igor Zaworski, Antmicro Ltd.] * Fix genvar error with `-O0` (#6165). [Max Wipfli] * Fix uninitialized thread PGO counters (#6167). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix additional UNOPTFLAT combinational cycles automatically in DFG (#6168) (#6173) (#6176). [Geza Lore] * Fix omitting error when assigning to an input (#6169). [Artur Bieniek, Antmicro Ltd.] * Fix parameter-dependent type linking (#6170). [Igor Zaworski, Antmicro Ltd.] * Fix param-dependent class typedef linking (#6171). [Igor Zaworski, Antmicro Ltd.] * Fix virtual interface member propagation (#6175) (#6184). [Yilou Wang] * Fix `--coverage-expr` null pointer dereference (#6181). [Igor Zaworski, Antmicro Ltd.] * Fix conflicting function/class name linking error (#6182). [Igor Zaworski, Antmicro Ltd.] * Fix negate of wide structure selections (#6186). * Fix VPI signal range order (#6189) (#6200). [Ibrahim Burak Yorulmaz] * Fix structure select causing 'Wide Op' error (#6191). [Danny Oler] * Fix automatic task variables in unrolled loops with forks (#6194) (#6201). [Danny Oler] * Fix 'driver same component' assertion (#6211) (#6215). [Geza Lore] * Fix `--stats` overridden by skipping identical build (#6220). [Geza Lore] * Fix MODDUP with duplicate packages to take first package (#6222). * Fix replicate with unsigned count but MSB set (#6231) (#6233). [Geza Lore] * Fix randomize on function-local variable (#6234). * Fix queue typedef with unbounded slice (#6236). * Fix error when force assignment is used with ref function args (#6244). [Ryszard Rozak, Antmicro Ltd.] * Fix write of 0 in '%c' (#6248) (#6249). [Rodrigo Batista de Moraes] * Fix coverage of variables of complex types (#6250). [Ryszard Rozak, Antmicro Ltd.] * Fix broken support of unassigned virtual interfaces (#6253) (#6338). [Szymon Gizler, Antmicro Ltd.] * Fix partial DFG conversion of concat assignments (#6255). [Geza Lore] * Fix dynamic cast purity (#6267). [Igor Zaworski, Antmicro Ltd.] * Fix same variable on the RHS forced to two different LHSs. (#6269). [Artur Bieniek, Antmicro Ltd.] * Fix spurious VPI value change callbacks (#6274). [Todd Strader] * Fix stray ']' in Verilog code output for non-constant select (#6277). [Geza Lore] * Fix hierarchical NBAs (#6286) (#6300). [Geza Lore] * Fix variables hiding package imports (#6289). [Johan Wouters] * Fix DFG circular driver tracing. [Geza Lore] * Fix no matching function calls for randomized `VlWide` in unpacked and dynamic arrays (#6290). [Mateusz Gancarz, Antmicro Ltd.] * Fix PowerPC support (#6292). [Sergey Fedorov] * Fix referencing module variables above classes (#6304). [Artur Bieniek, Antmicro Ltd.] * Fix direct NBA to dynamically-sized variable (#6310). [Artur Bieniek, Antmicro Ltd.] * Fix static vars under member select (#6313). [Igor Zaworski, Antmicro Ltd.] * Fix expression type comparison (#6316). [Igor Zaworski, Antmicro Ltd.] * Fix of inline constraints with member selects (#6321). [Igor Zaworski, Antmicro Ltd.] * Fix corner case bugs in module and variable inlining (#6322). [Geza Lore] * Fix queue extend to check bounds (#6324). [Aleksander Kiryk] * Fix gathering sensitivities from virtual interface members (#6325). [Aleksander Kiryk] * Fix FreeBSD missing headers (#6326). [Aleksander Kiryk] * Fix to select UDPs when they are the only candidate for a top module. * Fix splitting of assignments to SC variables (#6329) (#6336). [Geza Lore] * Fix to localize for super constructors with function calls as arguments (#6330). [Igor Zaworski, Antmicro Ltd.] * Fix wide select expansion and substitution (#6341) (#6345). [Geza Lore] * Fix upcasting class type parameters (#6344). [Krzysztof Bieganski, Antmicro Ltd.] * Fix undefined weak link for Apple GCC etc (#6348). [Congcong Cai] Verilator 5.038 2025-07-08 ========================== **Important:** * Change `--assert` to be the default; use `--no-assert` for legacy behavior and faster runtimes. **Other:** * Support redeclaring type as non-type; major parsing change (#2412) (#6020) (#6042) (#6044). * Support scoped `new` (#4199). * Support elaboration-time printing of unpacked array with `%p` (#4732). * Support constrained random for associative arrays (#5985) (#5986). [Yilou Wang] * Support assignments to concatenations with impure RHS (#6002). [Ryszard Rozak, Antmicro Ltd.] * Support SARIF JSON diagnostic output with `--diagnostics-sarif`. (#6017) * Support 1-bit params with -G and -pvalue (#6051) (#6082). [Paul Swirhun] * Support `specparam` (#5767) (#6142). * Support `$timeformat` with missing arguments (#6113). [Alex Solomatnikov] * Support non-overlapping blocking/non-blocking assignments (#6137). [Geza Lore] * Support parameter forward types. * Support constant functions with left-hand-side concatenates. * Add PROCINITASSIGN on initial assignments to process variables (#2481). [Niraj Menon] * Add BADVLTPRAGMA on unknown Verilator pragmas (#5945). [Shou-Li Hsu] * Add ternary operator into branch coverage (#5880). [Ryszard Rozak, Antmicro Ltd.] * Add aggregate type error checks (#5570) (#5950). [Shou-Li Hsu] * Add `--work` library-selection option (#5891 partial). * Add `--filter-type` to verilator_coverage (#6030). [Ryszard Rozak, Antmicro Ltd.] * Add `--hierarchical-threads` (#6037). [Bartłomiej Chmiel] * Add `MODMISSING` error, in place of unnamed error (#6054). [Paul Swirhun] * Add DFG binToOneHot pass to generate one-hot decoders (#6096). [Geza Lore] * Add hint of the signed right-hand-side in oversized replication error (#6098). [Peter Birch] * Improve hierarchical scheduling visualization in V3ExecGraph (#6009). [Bartłomiej Chmiel, Antmicro Ltd.] * Improve DPI temporary 'for' loop performance (#6079). [Bartłomiej Chmiel, Antmicro Ltd.] * Improve memory usage for SenTrees in V3OrderProcessDomains (#6112). [Geza Lore] * Improve docker image size (#6139). [Tobias Rosenkranz, bitaggregat GmbH] * Update docker base image to Ubuntu 24.04 (#6147). [Tobias Rosenkranz, bitaggregat GmbH] * Optimize DFG De Morgan patterns (#6090). [Geza Lore] * Optimize DFG variable elimination (#6091). [Geza Lore] * Optimize DFG PUSH_SEL_THROUGH_CONCAT pattern (#6092). [Geza Lore] * Optimize DFG before V3Gate (#6141). [Geza Lore] * Optimize DFG peephole patterns (#6149). [Geza Lore] * Optimize constification within Expand and Subst stages (#6111). [Geza Lore] * Fix --x-initial and --x-assign random stability (#2662) (#5958) (#6018) (#6025) (#6075). [Todd Strader] * Fix trace hierarchical-name runtime errors (#5668) (#6076). [Paul Swirhun] * Fix streaming operator packing order (#5903) (#6077). [Paul Swirhun] * Fix filename backslash escapes in C code (#5947). * Fix C++ widths in V3Expand (#5953) (#5975). [Geza Lore] * Fix dependencies from different hierarchical schedules (#5954). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix constant propagation of post-expand stages (#5955) (#5963) (#5969) (#5972) (#5983). * Fix sign extension of signed compared with unsigned case items (#5968). * Fix always processes ignoring $finish (#5971). [Hennadii Chernyshchyk] * Fix method calls and new to access interface arrays (#5973). [Nick Brereton] * Fix streaming to/from packed arrays (#5976). [Geza Lore] * Fix segfault writing timestamp to VCD after buffer flush (#5978) (#5980). [Dominick Grochowina] * Fix inconsistent assignment error with split-var (#5984) (#5988). [Yutetsu TAKATSUKASA] * Fix AstAssignW conversion (#5991) (#5992). [Ryszard Rozak, Antmicro Ltd.] * Fix const-bit-op-tree with single-bit masks (#5993) (#5998). [Yutetsu TAKATSUKASA] * Fix arithmetic right-shift by constants over 32 bits (#5994). [Zhen Yan] * Fix array bounds checking with class member selects (#5996) (#5997). [Krzysztof Starecki] * Fix checking for too-wide divide and modulus (#6003) (#6006). [Zhen Yan] * Fix folding of LteS in DfgPeephole (#6000) (#6004). [Geza Lore] * Fix slicing of AstExprStmt nodes (#6005). [Ryszard Rozak, Antmicro Ltd.] * Fix skipped generate blocks in toggle coverage (#6010). [Ryszard Rozak, Antmicro Ltd.] * Fix arithmetic left-shift by constants over 32 bits (#6007) (#6015). [Zhen Yan] * Fix concatenation and type casting (#6012) (#6013). [Todd Strader] * Fix wrong optimization result of shifted out variable (#6016) (#6019). [Yutetsu TAKATSUKASA] * Fix missing FreeBSD include (#6027) (#6028). [Joel Bodenmann] * Fix associative arrays with enum keys (#6034) (#6035). [Petr Nohavica] * Fix GCC 10 read-only linker error (#6040). [Todd Strader] * Fix WIDTHCONCAT on packed pattern assignment (#6045). [Dan Petrisko] * Fix type operator for interface signals (#6049) (#6050). [Todd Strader] * Fix V3OrderParallel scoring contraction hang (#6052). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix virtual interface array typedef expressions (#6057). * Fix DFG peephole select conditionals (#6064) (#6071). [Geza Lore] * Fix `--skip-identical` skipping on some errors (#6066). [Todd Strader] * Fix class typedef elaboration (#6080). [Kamil Rakoczy, Antmicro Ltd.] * Fix unpacked to packed parameter assignment (#6081) (#6088). [Todd Strader] * Fix casting reals to large integrals (#6085). [Todd Strader] * Fix nested hier blocks workers error (#6087). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix `--lib-create` with double-underscore (#6099). * Fix DFG binToOneHot table index missing driver (#6100). [Geza Lore] * Fix decoding octal string escapes with 1-2 digits (#6108). * Fix colon-divide operator without space (#6121). [Alex Solomatnikov] * Fix variables declared in fork after taskify (#6126). [Kamil Rakoczy, Antmicro Ltd.] * Fix method calls without parenthesis (#6127). [Alex Solomatnikov] * Fix `pre_randomize`/`post_randomize` when no randomize (#6128). [Alex Solomatnikov] * Fix wide non-blocking assignment mis-optimization (#6150) (#6152) (#6155). [Todd Strader] * Fix interface array connections with non-zero low declaration index. * Fix developer build error on MacOS/Flex2.6.4 (#6153). [Paul Swirhun] * Fix crash with --dumpi-V3LinkDot without --debug (#6159). [Igor Zaworski, Antmicro Ltd.] * Fix dereferencing stale iterator in DfgVertex::scopep() (#6225) (#6227). [Geza Lore] * Fix component numbers of new Vertices in V3DfgBreakCycles (#6225) (#6228). [Geza Lore] Verilator 5.036 2025-04-27 ========================== **Important:** * Change `--output-groups` to default to value of `--build-jobs` (#5751). Those using build farms may need to now use `--output-groups 0` or otherwise. * Support user-defined primitives (UDPs) (#468) (#5807) (#5936). [Zhou Shen, Krzysztof Sychla, et al] * Add `--trace-saif` for SAIF power traces (#5812) (#5914). [Mateusz Gancarz, Antmicro Ltd.] **Other:** * Change `--trace` to `--trace-vcd`. * Support simple `checker` blocks (#4066). [Srinivasan Venkataramanan] * Support force/release with a variable reference (#5721) (#5810). [Bartłomiej Chmiel, Antmicro Ltd.] * Support constraint random for StructArray (#5805) (#5937). [Yilou Wang] * Support command-line overriding `define (#5900) (#5908). [Brian Li] * Support soft unions (#5912) (#5932). [Robin Heinemann] * Support `$setuphold` (#5884). [Krzysztof Sychla] * Support assigning unpacked arrays to queues (#5924) (#5928). [Brian Li] * Support `systemc_interface and related inside `class`. * Support class extends with arguments. * Add multi-thread hierarchical simulation (#2583) (#5871). [Bartłomiej Chmiel, Antmicro Ltd.] * Add check for `let` misused in statement context (#5733). * Add used language to `--preproc-resolve` output (#5795). [Kamil Rakoczy, Antmicro Ltd.] * Add `--make json` to enable integration with non-make/cmake build systems (#5799). [Andrew Voznytsa] * Add numactl-like automatic assignment of processor affinity (#5911). * Add ccache support for generated cmake files (#5926) (#5930). [Andrew Voznytsa] * Add visualization of multi-threaded waiting time with verilator_gantt (#5929). [Bartłomiej Chmiel, Antmicro Ltd.] * Add suggesting isolate_assignments to UNOPTFLAT (#5942). [John Khoo] * Add profiling of hierarchical mtasks with verilator_gantt (#5956). [Bartłomiej Chmiel, Antmicro Ltd.] * Add empty veriuser.h for legacy compatibility. * Add DEPRECATED warning on `--xml-only` and `--xml-output`. * Remove unused gtkwave/wavealloca.h. [Geza Lore] * Optimize automatic splitting of some packed variables (#5843). [Geza Lore] * Optimize trigger vector in whole words (#5857). [Geza Lore] * Fix parameters referencing interface fields (#1593) (#5910). [Ryszard Rozak, Antmicro Ltd.] * Fix interface array assignments (#5270) (#5633) (#5869). [Nick Brereton] * Fix change detection at time 0 (#5499) (#5864). [Geza Lore] * Fix foreach of associative array inside a constraint block (#5727) (#5841). [Yilou Wang] * Fix reset of automatic function variables (#5747). [Augustin Fabre] * Fix invalid code motion over branches (#5811) (#5814). [Geza Lore] * Fix sorting of wide SenItems (#5816). [Geza Lore] * Fix tcmalloc static link and non-22.04 builds (#5817) (#5818). [Geza Lore] * Fix error on out-of-range lvalue part select (#5820). * Fix UNOPTFLAT warnings with `--coverage-trace` and always_comb (#5821). * Fix function locals in SenExprBuilder (#5822). [Geza Lore] * Fix type_id package scope resolution (#5826). [Krzysztof Bieganski, Antmicro Ltd.] * Fix `rand_mode` method with cast (#5831). * Fix invalidating variable caches in SenExprBulider (#5834) (#5835). [Geza Lore] * Fix assignment pattern as function argument (#5839). * Fix checking built-in method arguments (#5839). * Fix splitting of packed ports with non-zero based ranges (#5842). [Geza Lore] * Fix delays inside interface functions, and classes inside interfaces (#5846). * Fix NBA shared flag reuse (#5848). [Geza Lore] * Fix multiple expression coverage issues (#5849 partial) (#5867) (#5870). [Todd Strader] * Fix unresolved typedefs as parameters (#5850). [Eugene Feinberg, Brian Li] * Fix removal of callbacks no longer in current list (#5851) (#5852). [Gilberto Abram] * Fix segmentation fault on member compare (#5853). * Fix recursive error on virtual interfaces (#5854). [Yilou Wang] * Fix streaming of unpacked arrays concatenations (#5856). [Ryszard Rozak, Antmicro Ltd.] * Fix Windows paths in Perl (#5858) (#5860). [Tobias Jensen] * Fix algorithm header portability in V3Os.cpp (for std::replace) (#5861). [William D. Jones] * Fix `$fscanf` not returning -1 on EOF (#5881). * Fix PGO profiling for multi-threaded hierarchical scenarios (#5888). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix V3Gate assertion on eliminated circular logic (#5889) (#5898). [Geza Lore] * Fix process comparisons (#5896). * Fix ccache with clang (#5899). [Geza Lore] * Fix delayed assignment malformed LHS assertion (#5904). * Fix segfault in fork synchronization (#5906). [Krzysztof Bieganski, Antmicro Ltd.] * Fix `new this` (#5909). * Fix assignments with stream expressions and unpacked arrays (#5915). [Ryszard Rozak, Antmicro Ltd.] * Fix LATCH warning for automatic variables (#5918). [Yutetsu TAKATSUKASA] * Fix %% on elaboration severity tasks (#5922). [Ethan Sifferman] * Fix port default values with `--coverage-line` creating `0=0` (#5920). [Drew Ranck] * Fix vlSelf error on fork repeats (#5927). [Drew Ranck] * Fix missing C++ regeneration when Verilog files are updated (#5934). [Zhouyi Shen] * Fix stream expressions (#5938). [Ryszard Rozak, Antmicro Ltd.] * Fix packed selection using over 32-bit index (#5957). Verilator 5.034 2025-02-24 ========================== **Important:** * This is likely the last version to support Ubuntu 20.04, which is at end-of-life. * Add expression coverage (#4677) (#5719). [Todd Strader] **Other:** * Add `COVERIGN` warning, as a more specific UNSUPPORTED error. * Add `--public-ignore` to ignore public metacomments (#5716). [Andrew Nolte] * Add `--preproc-token-limit` (#5768). [Krzysztof Bieganski, Antmicro Ltd.] * Add lint error on importing package within a class (#5634) (#5679). [Nick Brereton] * Add `--preproc-resolve` for modules in preprocessor output (#5789). [Kamil Rakoczy, Antmicro Ltd.] * Support multidimensional array access via VPI (#2812) (#5573). [Krzysztof Starecki] * Support nested classes (#4178) (#5778). [Kamil Rakoczy, Antmicro Ltd.] * Support VPI array accessors (#5612). [Moubarak Jeje] * Support unpacked structure constrained randomization (#5657) (#5759). [Yilou Wang] * Support generated classes (#5665). [Shou-Li Hsu] * Support constraints on associative array user-defined keys (#5671) (#5729). [Yilou Wang] * Support `+incdir` with multiple directories. * Support integer atom type ports in `--hierarchical` (#5748). [Bartłomiej Chmiel, Antmicro Ltd.] * Support constrained random for arrays in structs (#5765) (#5802). [Yilou Wang] * Support selects on arbitrary string expressions (#5773). [Krzysztof Bieganski, Antmicro Ltd.] * Support side effects of form 'variable[index_function()]++'. * Improve hierarchical DPI wrapper scheduling performance (#2583) (#5734). [Bartłomiej Chmiel, Antmicro Ltd.] * Improve VPI write errors (#5712). [Andrew Nolte] * Improve `resetall support (#5728) (#5730). [Ethan Sifferman] * Optimize labels as final `if` block statements (#5744). * Optimize empty function definition bodies (#5750). * Optimize splitting trigger computation and dump (#5798). [Geza Lore] * Fix error message when call task as a function (#3089). [Matthew Ballance] * Fix force VPI public signal visibility (#5225). [Frédéric Requin] * Fix VPI iteration over hierarchy (#5314) (#5731). [Natan Kreimer] * Fix constrained random for > 64-bit associative arrays (#5670) (#5682). [Yilou Wang] * Fix mis-optimizing away `$urandom` (#5703). [Parker Schless] * Fix packages with `--public-depth 1` (#5708). [Andrew Nolte] * Fix V3Simulate constant reuse (#5709). [Geza Lore] * Fix man pages what-is section (#5710). [Ahmed El-Mahmoudy] * Fix pattern assignment to real inside struct (#5713). * Fix %p format output for real inside struct (#5713). * Fix segfault when only enum value referenced in package (#5714). [Dan Katz] * Fix `BLKSEQ` on suspendable processes (#5722). [Krzysztof Bieganski, Antmicro Ltd.] * Fix vpiDefName issues with non-inlined scopes and dpi conflicts (#5732). [Andrew Nolte] * Fix inlined expression with assignment under LHS of NBA (#5736) (#5740). [Geza Lore] * Fix duplicate-named class variable equivalence (#5737). * Fix `-j` ignored after `-f` (#5749). [Luca Colagrande] * Fix handling forced assigns in V3Life (#5757). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix VFileContent reference count (#5769) (#5771). [Dave Sargeant] * Fix ignoring joins in stringify in preprocessor (#5777). [Krzysztof Bieganski, Antmicro Ltd.] * Fix unpacked split_var (#5782) (#5785). [Yutetsu TAKATSUKASA] * Fix time import error on time parameters (#5786). [Luca Colagrande] * Fix dpi context functions (#5788). [Ryszard Rozak, Antmicro Ltd.] * Fix `$monitor` with dotted references (#5794). [Ahmed Elzeftawi] * Fix parsing input wire with default and range (#5800). [RJ Cunningham] * Fix matching language extension options including dots. Verilator 5.032 2025-01-01 ========================== **Minor:** * Support queue's assignment `push_back/push_front('{})` (#5585) (#5586). [Yilou Wang] * Support basic constrained random for multi-dimensional dynamic array and queue (#5591). [Yilou Wang] * Support vpiDefName (#3906) (#5572). [Krzysztof Starecki] * Support parameter names in pattern initialization (#5593) (#5596). [Greg Davill] * Support randomize size constraints with restrictions (#5582 partial) (#5611). [Ryszard Rozak, Antmicro Ltd.] * Support associative array basic constrained randomization (#5658) (#5670). [Yilou Wang] * Support `default disable iff` and `$inferred_disable` (#4016). [Srinivasan Venkataramanan] * Support `extern constraint` and `pure constraint`. * Add `--no-std-waiver` and default reading of standard lint waivers file (#5607). * Add `--no-std-package` as subset-alias of `--no-std` (#5607). * Add `lint_off --contents` in configuration files (#5606). * Add `--waiver-multiline` for context-sensitive `--waiver-output` (#5608). * Add `--fno-inline-funcs` to disable function inlining. * Add `--fno-slice` to disable array assignment slicing (#5644). * Add error on illegal enum base type (#3010). [Iztok Jeras] * Add error on `wait` with missing `.triggered` (#4457). * Add error when improperly storing to parameter (#5147). [Gökçe Aydos] * Add error on illegal `--prefix` etc. values (#5507). [Fabian Keßler] * Add error on `--savable --timing` (#5690). [Narcis Rodas] * Add coverage point hierarchy to coverage reports (#5575) (#5576). [Andrew Nolte] * Add warning on global constraints (#5625). [Ryszard Rozak, Antmicro Ltd.] * Add default CMAKE_BUILD_TYPE (#5691) (#5692). [Anthony Moore] * Add error on `solve before` or soft constraints of `randc` variable. * Improve concatenation performance (#5598) (#5599) (#5602). [Geza Lore] * Improve optimization of duplicate wide expressions (#5637). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix dotted reference in delay value (#2410). * Fix `function fork...join_none` regression with unknown type (#4449). * Fix public_module requiring a wire to become public (#4916). [Andrew Nolte] * Fix --hierarchical on projects with dot-f dependency lists (#5199) (#5669). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix can't locate scope error in interface task delayed assignment (#5462) (#5568). [Zhou Shen] * Fix BLKANDNBLK for for VARXREFs (#5569). [Todd Strader] * Fix VPI error instead of fatal for vpi_get_value() on large signals (#5571). [Todd Strader] * Fix --output-groups leftover files issue (#5574). [Todd Strader] * Fix slow unsized number parsing (#5577). [Geza Lore] * Fix negative assignment pattern keys (#5580). [Iztok Jeras] * Fix duplicate scope identifiers decoding (#5584). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix `rand` dynamic arrays with null handles (#5594). [Ryszard Rozak, Antmicro Ltd.] * Fix NBAs to unpacked arrays of unpacked structs (#5603). [Geza Lore] * Fix array of struct member overwrites on member update (#5605) (#5618) (#5628). [sumpster] * Fix interface and struct pattern collision (#5639) (#5640). [Todd Strader] * Fix mis-aliasing of instances with mailbox parameter types (#5632 partial). * Fix error on duplicated declaration of gen block (#5663). [Ryszard Rozak, Antmicro Ltd.] * Fix wildcard equality and inside operators for non-fourstate expressions (#5673). [Ryszard Rozak, Antmicro Ltd.] * Fix `randomize..with` of parameterized classes (#5676). [Ryszard Rozak, Antmicro Ltd.] * Fix interface bracketed array parameter access (#5677) (#5678). [Todd Strader] * Fix width extension of operands of `inside` operator (#5685). [Ryszard Rozak, Antmicro Ltd.] * Fix VPI + SYMRSVDWORD intersection (#5686). [Todd Strader] * Fix verilator_gantt for hierarchically Verilated models (#5700). [Bartłomiej Chmiel, Antmicro Ltd.] Verilator 5.030 2024-10-27 ========================== **Major:** * Add `-output-groups` to build with concatenated .cpp files (#5257). [Mariusz Glebocki] * Self-tests have been converted to Python, run `{test_name}.py` instead of `{test_name}.pl`. **Minor:** * Change .vlt config files to be read before .v files (#5185). [David Moberg] * Change to use maximum for cover point aggregation (#5402). [Andrew Nolte] * Change `--main` and `--binary` to use a TOP hierarchy name of "" (#5482). * Change install of public executables into bindir instead of pkgdatadir (#5140) (#5544). [Geza Lore] * Support IEEE-compliant intra-assign delays (#3711) (#5441). [Krzysztof Bieganski, Antmicro Ltd.] * Support `wor`, `trior`, `wand`, `triand` (#5386) (#5496). [Zhou Shen] * Support unconstrained randomization for unions (#5395) (#5396). [Yilou Wang] * Support basic constrained queue randomization (#5413). [Arkadiusz Kozdra, Antmicro Ltd.] * Support packed/unpacked and dynamic array unconstrained randomization (#5414) (#5415). [Yilou Wang] * Support appending to queue via `[]` (#5421). [Krzysztof Bieganski, Antmicro Ltd.] * Support named event locals (#5422). [Krzysztof Bieganski, Antmicro Ltd.] * Support basic `dist` constraints (#5431). [Arkadiusz Kozdra, Antmicro Ltd.] * Support unpacked array constrained randomization (#5437) (#5489). [Yilou Wang] * Support inside array constraints (#5448). [Arkadiusz Kozdra, Antmicro Ltd.] * Support DPI imports and exports with double underscores (#5481). * Support ccache when compiling Verilated files with cmake. * Support `local` and `protected` on `typedef` (#5460). * Support unconstrained randomization for associative array and queue (#5515). [Yilou Wang] * Support `rand` dynamic arrays of objects (#5557) (#5564). [Ryszard Rozak, Antmicro Ltd.] * Add error on misused genvar (#408). [Alex Solomatnikov] * Add error on instances without parenthesis. * Add Docker pre-commit hook (#5238) (#5452). [Chris Bachhuber] * Add partial coverage symbol and branch data in lcov info files (#5388). [Andrew Nolte] * Add method to check if there are VPI callbacks of the given type (#5399). [Kaleb Barrett] * Remove warning on unsized numbers exceeding 32-bits. * Improve Verilation thread pool (#5161). [Bartłomiej Chmiel, Antmicro Ltd.] * Improve performance of V3VariableOrder with parallelism (#5406). [Bartłomiej Chmiel, Antmicro Ltd.] * Improve parser error handling (#5493). [Arkadiusz Kozdra, Antmicro Ltd.] * Improve process trigger performance (#5483). [Geza Lore] * Fix suppression of WIDTH* warnings when immediately under a size cast (#3417). * Fix `$fatal` to not be affected by `+verilator+error+limit` (#5135). [Gökçe Aydos] * Fix equivalence checking when replacing type parameters (#5213) (#5255). [Han Qi] * Fix display with multiple string formats (#5311). [Luiza de Melo] * Fix performance of V3Trace when many activity blocks (#5372). [Deniz Güzel] * Fix REALCVT warning on integral timescale conversions (#5378). [Liam Braun] * Fix multidimensional function return value selects (#5382). [Gökçe Aydos] * Fix internal error in out-of-range select (#5393) (#5443). [Geza Lore] * Fix dot fallback finding wrong symbols (#5394). [Arkadiusz Kozdra, Antmicro Ltd.] * Fix infinite recursion due to recursive functions/tasks (#5398). [Krzysztof Bieganski, Antmicro Ltd.] * Fix V3Randomize compile error on old GCC (#5403) (#5417). [Krzysztof Bieganski, Antmicro Ltd.] * Fix extra events in traces (#5405). * Fix empty `foreach` in `if` in constraints (#5408). [Krzysztof Bieganski, Antmicro Ltd.] * Fix queue `[$-i]` select as reference argument (#5411). [Krzysztof Bieganski, Antmicro Ltd.] * Fix `pre`/`post_randomize` on `randomize() with` (#5412). [Krzysztof Bieganski, Antmicro Ltd.] * Fix capturing params in `randomize() with` (#5416) (#5418). [Krzysztof Bieganski, Antmicro Ltd.] * Fix `sformatf` internal error on initial automatics (#5423). [Todd Strader] * Fix clearing trigger of events with no sensitivity trees (#5426). [Arkadiusz Kozdra, Antmicro Ltd.] * Fix driving clocking block in reactive region (#5430). [Krzysztof Bieganski, Antmicro Ltd.] * Fix associative array next/prev/first/last mis-propagating constants (#5435). [Ethan Sifferman] * Fix randomize treated as std::randomize in classes (#5436). [Arkadiusz Kozdra, Antmicro Ltd.] * Fix `foreach` colliding index names (#5444). [Arkadiusz Kozdra, Antmicro Ltd.] * Fix fault on defparam with UNSUPPORTED ignored (#5450). [Luiza de Melo] * Fix class reference with pin that is a class reference (#5454). * Fix not reporting class reference with extra parameters (#5467). * Fix user-type parameter overlap (#5469). [Todd Strader] * Fix tracing when name() is empty (#5470). [Sam Shahrestani] * Fix timing mode not exiting on empty events (#5472). * Fix coverage counts missing due to table optimization (#5473) (#5474). [Vito Gamberini] * Fix `--binary` with .cpp PLI filenames under relative directory paths. * Fix extra dot in coverage point hierarchy when using name()=''. * Fix short-circuiting with associative array access (#5484). [Ethan Sifferman] * Fix short-circuiting on method calls (#5486). [Ethan Sifferman] * Fix exponential concatenate performance (#5488). [Arkadiusz Kozdra, Antmicro Ltd.] * Fix V3Table trying to generate 'x' bits in the lookup table (#5491). [Geza Lore] * Fix randomize with foreach constraints (#5492). [Arkadiusz Kozdra, Antmicro Ltd.] * Fix explicit CMAKE_INSTALL_PREFIX usages (#5500). [Fabian Keßler] * Fix configure inserting absolute paths for Python and Perl (#5504) (#5505). [Nathan Graybeal] * Fix pattern initialization with typedef key (#5512). [Eugene Feinberg] * Fix `-j` option without argument in hierarchical Verilation (#5514). [Ryszard Rozak, Antmicro Ltd.] * Fix `foreach` with 2-D queues and dynamic arrays (#5525) (#5529). [Yilou Wang] * Fix struct array assignment (#5455) (#5537). [Yilou Wang] * Fix copy constructor of classes that use std::process (#5528). [Ryszard Rozak, Antmicro Ltd.] * Fix foreach on associative array (#5530). [Yilou Wang] * Fix multi-range indices assignment (#5534) (#5547). [Yilou Wang] * Fix static function wrappers (#5536). [Ryszard Rozak, Antmicro Ltd.] * Fix assignments of concatenation to queues and dynamic arrays (#5540). [Ryszard Rozak, Antmicro Ltd.] * Fix container reduction methods (#5542). [Krzysztof Boroński] * Fix complex user type problem with `--x-assign` (#5543). [Todd Strader] * Fix long module names crashing string handling (#5546). [Filip Badáň] * Fix array trace splitting (#5549). [Todd Strader] * Fix queue element access (#5551). [Ryszard Rozak, Antmicro Ltd.] * Fix struct literal on pattern assignment (#5552) (#5559). [Todd Strader] * Fix build on gcc when using the Spack wrapper (#5555). [Eric Müller] * Fix enum name method (#5563). [Todd Strader] * Fix `$countbits` in assert with non-tristates (#5566). [Shou-Li Hsu] * Fix missing VlProcess handle in coroutines with splits (#5623) (#5650). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix imported array assignment literals (#5642) (#5648). [Todd Strader] * Fix foreach mixed array (#5655) (#5656). [Yilou Wang] Verilator 5.028 2024-08-21 ========================== **Minor:** * Support state-dependent constraints (#5217). [Arkadiusz Kozdra, Antmicro Ltd.] * Support cross-module clocking variable access (#5184). [Arkadiusz Kozdra, Antmicro Ltd.] * Support inline constraints for class randomization methods (#5234). [Krzysztof Boroński] * Support clocking blocks in virtual interfaces (#5235). [Arkadiusz Kozdra, Antmicro Ltd.] * Support `$assertcontrol` assertion_type (#5236). [Bartłomiej Chmiel, Antmicro Ltd.] * Support conditional constraints (#5245). [Arkadiusz Kozdra, Antmicro Ltd.] * Support`--compiler-include` headers in user-supplied cpp files (#5271). [Bartłomiej Chmiel, Antmicro Ltd.] * Support `rand_mode` (#5273). [Krzysztof Bieganski, Antmicro Ltd.] * Support `this.randomize with` (#5282). [Arkadiusz Kozdra, Antmicro Ltd.] * Support foreach constraints (#5302). [Arkadiusz Kozdra, Antmicro Ltd.] * Support `parameter type` in hierarchical blocks (#5309) (#5333). [Bartłomiej Chmiel, Antmicro Ltd.] * Support assertcontrol directive type (#5310). [Bartłomiej Chmiel, Antmicro Ltd.] * Support inline random variable control (#5317). [Krzysztof Bieganski, Antmicro Ltd.] * Support streaming operator on arrays and wide data (#5326). [Arkadiusz Kozdra, Antmicro Ltd.] * Support streams to/from arrays of wide data (#5334). [Arkadiusz Kozdra, Antmicro Ltd.] * Support `constraint_mode` (#5338). [Krzysztof Bieganski, Antmicro Ltd.] * Support constraining AstSel (#5344). [Arkadiusz Kozdra, Antmicro Ltd.] * Support default value on module input (#5358) (#5373). [Drew Ranck] * Add `--compiler-include` for additional C++ includes (#5139) (#5202). [Bartłomiej Chmiel, Antmicro Ltd.] * Add `--emit-accessors` (#5182) (#5227). [Ryan Ziegler] * Add suggestions on misspelled PLI functions. * Add warning on dist in constraints (#5264). [Arkadiusz Kozdra, Antmicro Ltd.] * Add more `rand_mode` unsupported errors (#5329). [Krzysztof Bieganski, Antmicro Ltd.] * Add parsing but otherwise ignore std::randomize (#5354). [Arkadiusz Kozdra, Antmicro Ltd.] * Add Verilated cc define when `--timing` used (#5383). [Kaleb Barrett] * Improve emitted code to use a reference for VlSelf (#5254). [Yangyu Chen] * Fix monitor block sensitivity items (#4040) (#4400) (#5294). [Udaya Raj Subedi] * Fix fusing macro arguments to not ignore whitespace (#5061). [Tudor Timi] * Fix optimized-out sensitivity trees with `--timing` (#5080) (#5349). [Krzysztof Bieganski, Antmicro Ltd.] * Fix classes/modules of case-similar names (#5109). [Arkadiusz Kozdra] * Fix mis-removing $value$plusargs calls (#5127) (#5137). [Seth Pellegrino] * Fix incorrect result of width mismatch (#5186) (#5189). [Yutetsu TAKATSUKASA] * Fix compiler coroutine check (#5190) (#5300). [Ricardo Barbedo] * Fix shortened module names when searching for files (#5196) (#5246). [Tim Hutt] * Fix `--x-assign` to be independent from `+verilator+rand+reset` (#5214). [Andrew Nolte] * Fix splitting if statements with impure conditions (#5219). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix unknown conversion on queues (#5220). [Alex Solomatnikov] * Fix top-level unpacked structure resets (#5221). * Fix concurrency for mailbox and semaphores (#5222). [Liam Braun] * Fix forks capturing non-input ports in tasks (#5237) (#5343). [Krzysztof Bieganski, Antmicro Ltd.] * Fix toggle coverage aggregation on same line (#5248). [Krzysztof Obłonczek] * Fix error on empty generate with -O0 (#5250). * Fix unconstrained randomization of unpacked structs (#5252). [Krzysztof Bieganski, Antmicro Ltd.] * Fix inlining of variables driven from forced vars (#5259). [Geza Lore] * Fix tracing with `--main-top-name -` (#5261). [Ethan Sifferman] * Fix randomization when used with inheritance (#5268). [Krzysztof Bieganski, Antmicro Ltd.] * Fix inline constraints creating class random generator (#5280). [Krzysztof Bieganski, Antmicro Ltd.] * Fix WIDTHEXPAND on left shift of intuitive amount (#5284). [Greg Taylor] * Fix elaborating foreach loops (#5285). [Arkadiusz Kozdra, Antmicro Ltd.] * Fix initializing static array in dynamic arrays and queues (#5287). [Baruch Sterin] * Fix static variable initializers in procedures (#5296). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix randomizing current object with `rand` class instance member (#5292). [Krzysztof Bieganski, Antmicro Ltd.] * Fix handling of rand fields not referenced in constraints (#5305). [Ryszard Rozak, Antmicro Ltd.] * Fix Python3 path discovery in make flows to avoid mixing system and user python interpreters (#5307). [Markus Krause] * Fix make flows to pass PYTHON3 (like PERL) (#5307) (#5308). [Markus Krause] * Fix assert on wide expression (#5319) (#5324). [Varun Koyyalagunta] * Fix output clock variable overwriting signal (#5320) (#5347). [Krzysztof Bieganski, Antmicro Ltd.] * Fix stringify in nested preprocessor macros (#5323). [Krzysztof Bieganski, Antmicro Ltd.] * Fix $sformat with array arguments (#5330). [Abe Jordan] * Fix -Wunused-but-set-variable clang warning (#5331). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix purity of functions with AstJumpBlock or AstStmtExpr (#5332). [Ryszard Rozak, Antmicro Ltd.] * Fix compilation error on unreachable disable fork / wait fork (#5339). [Arkadiusz Kozdra, Antmicro Ltd.] * Fix missing type coercion in 'inside {array}' (#5340). [Arkadiusz Kozdra, Antmicro Ltd.] * Fix +: and -: unpacked array slicing when array has nonzero low index (#5345) (#5387). [James Bailey] * Fix tracing_{on,off} in the presence of non-inlined modules (#5346). [Geza Lore] * Fix NBAs in suspendables (#5348). [Krzysztof Bieganski, Antmicro Ltd.] * Fix lint_off on Errors (#5351) (#5363). [Ethan Sifferman] * Fix cache config file resolution performance (#5369). [Geza Lore] * Fix capturing fields from superclass in `randomize() with` (#5389). [Krzysztof Bieganski, Antmicro Ltd.] * Fix virtual interface null checks (#5391). [Krzysztof Bieganski, Antmicro Ltd.] * Fix ==? and !=? with X values. * Fix CPU time being zero. * Fix inline function ref port persistence. Verilator 5.026 2024-06-15 ========================== **Major:** * Support constrained randomization with external solvers (#4947). [Arkadiusz Kozdra, Antmicro Ltd.] **Minor:** * Support `$psprintf` system function (#4314) (#5169). [Arkadiusz Kozdra, Antmicro Ltd.] * Support 2D dynamic array initialization (#4700) (#5122). [Valentin Atepalikhin] * Support __en/__out signals on top level inout ports (#4812) (#4856). [Paul Wright] * Support empty queue as dynarray default value (#5055). [Arkadiusz Kozdra, Antmicro Ltd.] * Support vpiInertialDelay (#5087). [Todd Strader] * Support NBAs to arrays inside loops (#5092). [Geza Lore] * Support parsing and otherwise ignoring inline constraints (#5126). [Arkadiusz Kozdra, Antmicro Ltd.] * Support `inout` clocking items (#5160). [Arkadiusz Kozdra, Antmicro Ltd.] * Support StructSel in unpacked array assignments (#5176). [Geza Lore] * Add error on zero width select (#5028). * Add CITATION.cff (#5057) (#5058). [Gijs Burghoorn] * Add VPI eval needed tracking (#5065). [Todd Strader] * Add `--localize-max-size` option and optimization (#5072). * Add parameterless assert control system tasks (#5010). [Bartłomiej Chmiel] * Add traceCapable indication to model header (#5053). [Vito Gamberini] * Add increasing of stack size when possible (#5071) (#5104). [Yinan Xu] * Add assertion on reusing VerilatedContext (#5167). * Add `--pins-sc-uint-bool` to force SystemC uint type (#5192). [Bartłomiej Chmiel, Antmicro Ltd.] * Improve DFG regularization in cyclic graphs (#5142). [Geza Lore] * Improve VerilatedVpiPutHolder storage requirements (#5144). [Kaleb Barrett] * Fix coroutines without awaits to have a co_return (#4208) (#5175). [Arkadiusz Kozdra, Antmicro Ltd.] * Fix missing flex include path variable (#4970) (#4971). [Christopher Taylor] * Fix missing parameters with comma to be errors (#4979) (#5012). [Paul Swirhun] * Fix 'experimental/coroutine' file not found on MacOS (#5030) (#5031) (#5151). [Paul Bowen-Huggett] * Fix bound queue printing (#5032). [Aleksander Kiryk, Antmicro Ltd.] * Fix consecutive zero-delays (#5038). [Krzysztof Bieganski, Antmicro Ltd.] * Fix attempted to destroy locked thread pool error (#5040). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix `$system` with string argument (#5042). * Fix width extension on delays (#5043). * Fix `$typename` on array.min and others (#5049). [Gökçe Aydos] * Fix `make $(info)` which cannot be silenced (#5059). [Gökçe Aydos] * Fix CMake builds to export VERILATOR_ROOT (#5063). [Michael Bikovitsky] * Fix false ASSIGNIN on functions with explicit port map (#5069). * Fix 4-state value support for $readmem (#5070) (#5078). [Ethan Sifferman] * Fix DFG assertion with SystemC (#5076). [Geza Lore] * Fix `$typename` string to be more standard (#5082) (#5083). [Andrew Nolte] * Fix missed optimization in V3Delayed (#5089). [Geza Lore] * Fix macro expansion in strings per 1800-2023 (#5094). [Geza Lore] * Fix width extension of unpacked array select (#5095). [Varun Koyyalagunta] * Fix MacOS missing header (#5096) (#5097). [Vito Gamberini] * Fix assertion failure in V3Gate (#5101). [Yutetsu TAKATSUKASA] * Fix aliases for forced port signals (#5105). [Geza Lore] * Fix tracing interface functions (#5108). [Alex Solomatnikov] * Fix method calls parsing in constraints (#5110). [Arkadiusz Kozdra, Antmicro Ltd.] * Fix vpiInertialDelay for memories (#5113). [Todd Strader] * Fix hierarchical compilation with nested -F (#5114) (#5124). [Alex Solomatnikov] * Fix references to ports in forks (#5123). [Krzysztof Bieganski, Antmicro Ltd.] * Fix output C++ type error on change detect of I/O arrays (#5125) (#5131). [Pawel Jewstafjew] * Fix x-valued parameters with `--x-assign unique` (#5129). [Ethan Sifferman] * Fix overflow of string on VPI reads (#5145) (#5146). [Kaleb Barrett] * Fix VerilatedVpiPutHolder class (#5156). [Kaleb Barrett] * Fix extending out-of-range select (#5159) (#5164). [Geza Lore] * Fix radix in width warnings (#5166). [Geza Lore] * Fix SystemC BITS_PER_DIGIT in VL_ASSIGN_SBW (#5170). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix non-constant replication in concats (#5171). [Arkadiusz Kozdra, Antmicro Ltd.] * Fix table optimization when applied on real data type (#5172) (#5173). [Arthur Rosa] * Fix signed types emitted in hierarchical Verilation (#5178). [Bartłomiej Chmiel, Antmicro Ltd.] * Fix DPI import of null C-string (#5179). * Fix CMake installation missing verilated.mk (#5187) (#5188). [Philip Axer] * Fix linking with pthreads on CMake (#5194). [Tim Hutt] * Fix clang-17 coroutines configuration with -std=gnu++20 (#5200). [Gus Smith] Verilator 5.024 2024-04-05 ========================== **Major:** * Add printing summary reports, use `--quiet` or `+verilator+quiet` to suppress (#4909). * Support 1800-2023 keywords, and parsing with UNDEFINED warnings. * Support 1800-2023 preprocessor ifdef expressions. **Minor:** * Change 1800-2023 to be default language version. * Add DFG 'regularize' pass, and improve variable removal (#4937). [Geza Lore] * Add error when pass net to function argument (#4132) (#4966). [Fuad Ismail] * Add `UNUSEDLOOP` when unused loop is removed (#4926). [Bartłomiej Chmiel, Antmicro Ltd.] * Add custom version for verilator --version packaging (#4954). [Nolan Poe] * Add error on missing pure virtual functions (#4961). * Add error on calling static function without object (#4962). * Add JSON AST dumps (#5020). [Szymon Gizler] * Support 1800-2023 DPI headers, svGetTime/svgGetTimeUnit/svGetTimePrecision methods. * Support 1800-2023 class and function :initial, :extends, :final virtual overrides (#5025). * Support public packed struct / union (#860) (#4878). [Kefa Chen] * Support stream operation on unpacked array (#4714) (#5006). [Fuad Ismail] * Support implicitly-typed variable definitions in for-loop initializers (#4945) (#4986). [Kevin Nygaard] * Support inside range with implicit type conversion (#5026). [Arkadiusz Kozdra, Antmicro Ltd.] * Improve installation to be relocatable (#4927). [Geza Lore] * Improve internal ordering code (#4957) (#4990) (#4994) et al. [Geza Lore] * Fix generate blocks in vpi_iterate (#3609) (#4913). [Andrew Nolte] * Fix __Vlip undefined error in --freloop (#4824). [Justin Yao Du] * Fix missing VPI scopes (#4918). [Andrew Nolte] * Fix invalid cast on string structure creation (#4921). * Fix try-lock spuriously fails (#4931) (#4938). [Kamil Rakoczy] * Fix V3Unknown unpacked struct x-assign (#4934). [Yan Xu] * Fix DFG removing forceable signals (#4942). [Geza Lore] * Fix null characters in shortened identifiers (#4946). [Abdul Hameed] * Fix assignment of null into struct member (#4952). * Fix VPI missing scopes 2 (#4965). [Andrew Nolte] * Fix object assignment from conditionals (#4968). * Fix GCC14 warnings on template specialization syntax (#4974) (#4975). [Nolan Poe] * Fix unpacked structure upper bit cleaning (#4978). * Fix tests on MacOS (#4984) (#4985). [Kevin Nygaard] * Fix `--prof-exec` predicted time values (#4988). [Geza Lore] * Fix class type as an associative array parameter (#4997). * Fix inout ports of unpacked struct type (#5000). [Ryszard Rozak, Antmicro Ltd.] * Fix `unique {}` constraints missing semicolon (#5001). * Fix preprocessor to respect strings in joins (#5007). * Fix tracing class parameters (#5014). * Fix memory leaks (#5016). [Geza Lore] * Fix `$readmem` with missing newline (#5019). [Josse Van Delm] * Fix internal error on missing pattern key (#5023). * Fix tracing replicated hierarchical models (#5027). * Fix false LIFETIME warning on `repeat` in `fork-join` (#5456). Verilator 5.022 2024-02-24 ========================== **Minor:** * Add predicted stack overflow warning (#4799). * Add `+verilator+coverage+file` runtime option. * Add `--assert-case` option (#4919). [Yutetsu TAKATSUKASA] * Add `--decorations node` for inserting debug comments into emitted code. * Add `--json-only` and related JSON dumping (#4715) (#4831). [Szymon Gizler, Antmicro Ltd.] * Add `--[no]-stop-fail` option for continuing after assertions (#4904). [Yutetsu TAKATSUKASA] * Add `--runtime-debug` for Verilated executable runtime debugging. * Add `--valgrind` switch (#4828). [Szymon Gizler] * Add `unroll_disable` and `unroll_full` loop control metacomments (#3260). [Jiaxun Yang] * Remove deprecated 32-bit pointer mode (`gcc -m32`). * Deprecate --xml-only and XML dumping (#4715) (#4831). * Change zero replication width error to ZEROREPL warning (#4753) (#4762). [Pengcheng Xu] * Improve message for priority case assertion failure (#4905). [Yutetsu TAKATSUKASA] * Support dumping coverage with `--main`. * Support dumping DFG patterns with `--stats` (#4889). [Geza Lore] * Support `vpiConstType` in `vpi_get_str()` (#4797). [Marlon James] * Support SystemC 3.0.0 public review version (#4805) (#4807). [Anthony Donlon] * Support parsing anonymous primitive instantiations (#4809). [Anthony Donlon] * Fix to not emit already waived warnings in waiver output (#4574) (#4818). [Jonathan Schröter] * Fix `this` in member initialization (#4710). [eliasphanna] * Fix localparam elaboration (#3858) (#4794). [Andrew Nolte] * Fix lint_off disables on preprocessor warnings (#4703). [Srinivasan Venkataramanan] * Fix $time not rounding up (#4790) (#4792). [Paul Wright] * Fix `vpi_get()` and `vpi_get64()` to return vpiUndefined on errors (#4795). [Marlon James] * Fix VPI parameter iteration (#4798). [Marlon James] * Fix delays using wrong timeunit when modules inlined (#4806). [Paul Wright] * Fix warnings in verilated_sc_trace.h for Clang (#4807) (#4827). [Anthony Donlon] * Fix null pointer dereference (#4810) (#4825). [Adrian Sampson] * Fix compilation error on multi-inherited interface class usage (#4819). * Fix maybe-uninitialized compiler warning (#4820) (#4822). [Larry Doolittle] * Fix mis-splitting of dump control functions (#4821). [Fan Shupei] * Fix wrong utimes() parameter (#4829). [Szymon Gizler] * Fix incorrect bit-op-tree NOT optimization (#4832) (#4847). [Yutetsu TAKATSUKASA] * Fix width calculation in replaceShiftOp (#4837) (#4841) (#4849). [Yutetsu TAKATSUKASA] * Fix unsafe write in wide array insertion (#4850) (#4855). [Paul Swirhun] * Fix NOT when checking EQ/NEQ under AND/OR tree (#4857) (#4863). [Yutetsu TAKATSUKASA] * Fix tracing chandles (#4860). [Nathan Graybeal] * Fix $fwrite of null (#4862). [Jose Tejada] * Fix -fno-const-bit-op-tree wrong runtime result (#4864) (#4867). [Yutetsu TAKATSUKASA] * Fix SystemC biguint sign desynchronization (#4870). [Bartłomiej Chmiel] * Fix incorrect temporary insertion in loop conditions with statements (#4873). [Geza Lore] * Fix timing with expr on assign LHS (#4880). [Krzysztof Bieganski, Antmicro Ltd.] * Fix assertion for unique case (#4892). [Yutetsu TAKATSUKASA] * Fix GCC tautological-compare warnings. * Fix compile error on structs with queues (and ignore toggle coverage on queues). * Fix toggle coverage error on multi-edge driven signals. * Fix whitespace in `pragma protect version` (#4902) (#4914). [Paul Swirhun] * Fix incorrect code generation for change expression on typedefed unpacked array (#4915). [Geza Lore] * Fix inconsistent driver resolution with typedefs (#4917). [Geza Lore] Verilator 5.020 2024-01-01 ========================== **Major:** * Support compilation with precompiled headers with Make, and GCC or CLang. * Change include to systemc instead of systemc.h (#4622) (#4623). [Chih-Mao Chen] This may require that SystemC programs add 'using namespace sc_core', 'using namespace sc_dt'. **Minor:** * Add devcontainer support (#4748). [Stefan Wallentowitz] * Support `iff` in sensitivity list (#1482) (#4626). [Krzysztof Bieganski, Antmicro Ltd.] * Support parameterized virtual interfaces (#4047) (#4743). [Ryszard Rozak, Antmicro Ltd.] * Support --timing triggers for virtual interfaces (#4673). [Krzysztof Bieganski, Antmicro Ltd.] * Support ccache when compiling Verilator with CMake (#4678). [Anthony Donlon] * Support passing constraints to --xml-only output (still otherwise unsupported) (#4683). [Shahid Ikram] * Support node memory usage information in --stats (#4684). [Geza Lore] * Support vpiConstType in vpi_get() (#4761). [Todd Strader] * Support vpi_iterate on packages with vpiInstance (#4726). [Todd Strader] * Support multiple parameters in virtual interfaces (#4745). [Ryszard Rozak, Antmicro Ltd.] * Support user C/C++ code in final archive, and make a lib{model}.a (#4749) (#4754). [Fan Shupei] * Support inside operator on unpacked arrays and queues (#4751). [Ryszard Rozak, Antmicro Ltd.] * Support VPI parameter iteration (#4765). [Todd Strader] * Support packages in vpi_handle_by_name() (#4768). [Todd Strader] * Support invoking interface methods on virtual interface variables (#4774) (#4775). [Jordan McConnon] * Remove deprecated options (#4663). [Geza Lore] * Remove older compiler support; require C++14 or newer (#4784) (#4786). * Optimize timing-delayed queue (#4584). [qrqiuren] * Optimize substitute optimization memory usage (#4687). [Geza Lore] * Optimize wide primitive operations with -Oz (#4733). [Geza Lore] * Optimize V3Premit performance etc. (#4736). [Geza Lore] * Fix VPI TOP level variable iteration (#3919) (#4618). [Marlon James] * Fix display with no % printing assoc array (#4376). [Alex Solomatnikov] * Fix scheduling of external force signals (#4577) (#4668). [Geza Lore] * Fix a memory leak in V3Fork (#4628). [Krzysztof Boroński] * Fix linking parameterized hierarchical blocks and recursive hierarchical blocks (#4654). [Anthony Donlon] * Fix identifiers that end with '_' on Windows (#4655). [Anthony Donlon] * Fix 'for' loop with outside variable reference (#4660). [David Harris] * Fix tracing FST enums (#4661) (#4756). [Todd Strader] * Fix interface parameters used in loop generate constructs (#4664) (#4665). [Anthony Donlon] * Fix C++20 compilation errors (#4670). * Fix deadlocks in error handler (#4672). [Mariusz Glebocki, Antmicro Ltd.] * Fix MingW compilation (#4675). [David Ledger] * Fix trace when using SystemC with certain configurations (#4676). [Anthony Donlon] * Fix range access to classes depending on parameter resolution (#4681). [Krzysztof Boroński] * Fix select into constant And/Or/Xor pattern (#4689). [Geza Lore] * Fix access type of function arguments (#4692) (#4694). [Ryszard Rozak, Antmicro Ltd.] * Fix dynamic NBAs with automatic vars (#4696). [Krzysztof Bieganski, Antmicro Ltd.] * Fix # 0 delays for process resumption, etc. (#4697). [Krzysztof Boroński] * Fix conflicted namespace for coroutines (#4701) (#4707). [Jinyan Xu] * Fix compilers seeing empty input due to file system races (#4708). [Flavien Solt] * Fix shift of > 32-bit number (#4719). [Flavien Solt] * Fix Windows include gates in filesystem Flush implementation (#4720). [William D. Jones] * Fix power operator with wide numbers and constants (#4721) (#4763). [Flavien Solt] * Fix parameter passing to ports (#4723). [Ryszard Rozak, Antmicro Ltd.] * Fix block names of nested do..while loops (#4728). [Ryszard Rozak, Antmicro Ltd.] * Fix class name in error on 'new' on virtual class (#4739). [Ryszard Rozak, Antmicro Ltd.] * Fix typedefs pointing to parameterized classes (#4747). [Ryszard Rozak, Antmicro Ltd.] * Fix $finish twice to no longer exit (#4757). [Tim Hutt] * Fix dynamic NBA conditions (#4773). [Krzysztof Bieganski, Antmicro Ltd.] * Fix `V3Fork` stage to run only if `--timing` is set (#4778). [Krzysztof Bieganski, Antmicro Ltd.] * Fix max multiply width and add runtime assertions if too small (#4781). * Fix select value too wide (#5148) (#5153). [Dercury] Verilator 5.018 2023-10-30 ========================== **Major:** * Support compilation with precompiled headers with Make and GCC or CLang. * Change include of systemc instead of systemc.h (#4622) (#4623). [Chih-Mao Chen] This may require that SystemC programs add 'using namespace sc_core', 'using namespace sc_dt'. **Minor:** * Add SIDEEFFECT warning on mishandled side effect cases. * Add trace() API even when Verilated without --trace (#4462). [phelter] * Add warning on interface instantiation without parens (#4094). [Gökçe Aydos] * Add sv_vpi_user.h from IEEE 1800-2017 Annex M (#4606). [Marlon James] * Support 'disable fork' (#4125) (#4569). [Aleksander Kiryk, Antmicro Ltd.] * Support 'wait fork' (#4586). [Aleksander Kiryk, Antmicro Ltd.] * Support 'randc' (#4349). * Support assigning events (#4403). [Krzysztof Boroński] * Support resizing function call inout arguments (#4467). * Support NBAs in non-inlined functions/tasks (#4496) (#4572). [Krzysztof Bieganski, Antmicro Ltd.] * Support converting parameters inside modules to localparams (#4511). [Anthony Donlon] * Support concatenation of unpacked arrays (#4558). [Yutetsu TAKATSUKASA] * Support Clang 16 (#4592). [Mariusz Glebocki] * Support VPI variables of real and string data types (#4594). [Marlon James] * Support making VL_LOCK_SPINS configurable (#4599). [Geza Lore] * Change code --stats output (#4597). [Geza Lore] * Change --prof-exec infrastructure and report (#4602). [Geza Lore] * Change lint_off to not propagate upwards to files including where the lint_off is. * Optimize empty expression statements (#4544). * Optimize trace internals (#4610) (#4612). [Geza Lore] * Optimize internal performance issues (#4638). [Geza Lore] * Fix conversion of impure logical expressions to bit expressions (#487 partial) (#4437). [Ryszard Rozak, Antmicro Ltd.] * Fix enum functions in localparams (#3999). [Andrew Nolte] * Fix passing arguments by reference (#3385 partial) (#4489). [Ryszard Rozak, Antmicro Ltd.] * Fix multithreading handling to separate by code units that use/never use it (#4228). [Mariusz Glebocki, Antmicro Ltd.] * Fix usage of annotation options (#4486) (#4504). [Michal Czyz] * Fix detecting local vars in nested forks (#4493) (#4506). [Kamil Rakoczy] * Fix handling input file path separator (#4515) (#4516). [Anthony Donlon] * Fix mis-support for parameterized UDPs (#4518). [Anthony Donlon] * Fix constant conversion of $realtobits, $bitstoreal (#4522). [Andrew Nolte] * Fix conversion of integers in $display '%e' (#4528). [muzafferkal] * Fix non-inlined interface tracing (#3984) (#4530). [Todd Strader] * Fix stream operations with operands of struct type (#4531) (#4532). [Ryszard Rozak, Antmicro Ltd.] * Fix 'this' in a constructor (#4533). [Ryszard Rozak, Antmicro Ltd.] * Fix stream shift operator of 32 bits (#4536). [Julien Faucher] * Fix object destruction after a copy constructor (#4540) (#4541). [Ryszard Rozak, Antmicro Ltd.] * Fix inlining of real functions miscasting (#4543). [Andrew Nolte] * Fix broken link error for enum references (#4551). [Anthony Donlon] * Fix logical expressions with class objects - caching in v3Const (#4552). [Ryszard Rozak, Antmicro Ltd.] * Fix using functions/tasks following class definition inside module (#4553). [Anthony Donlon] * Fix large constant buffer overflow (#4556). [Varun Koyyalagunta] * Fix instance arrays connecting to array of structs (#4557). [raphmaster] * Fix error message for invalid parameter overrides (#4559). [Anthony Donlon] * Fix shift to remove operation side effects (#4563). * Fix compile warning on unused member function variable (#4567). * Fix method narrowing conversion compiler error (#4568). * Fix interface comparison (#4570). [Krzysztof Bieganski, Antmicro Ltd.] * Fix dynamic triggers for named events (#4571). [Krzysztof Bieganski, Antmicro Ltd.] * Fix dictionaries with keys of class types (#4576). [Ryszard Rozak, Antmicro Ltd.] * Fix to not remap local assign intervals in forks (#4583). [Krzysztof Bieganski, Antmicro Ltd.] * Fix display optimization ignoring side effects (#4585). * Fix PLI/DPI user defined system task/function grammar (#4587) (#4588). [Quentin Corradi] * Fix fault on empty clocking block (#4593). [Alex Mykyta] * Fix creating implicit nets for inputs of gate primitives (#4603). [Geza Lore] * Fix try_put method of unbounded mailbox (#4608). [Ryszard Rozak, Antmicro Ltd.] * Fix stable name generation in V3Fork (#4615) (#4624). [Krzysztof Boroński] * Fix virtual methods (#4616). [Ryszard Rozak, Antmicro Ltd.] * Fix insertion at queue end (#4619). [Krzysztof Boroński] * Fix rand fields of reference types (#4627). [Ryszard Rozak, Antmicro Ltd.] * Fix dynamic casts of null values (#4631). [Ryszard Rozak, Antmicro Ltd.] * Fix signals read via virtual interfaces being misoptimized (#4645). [Krzysztof Bieganski, Antmicro Ltd.] * Fix handling of static keyword in methods (#4649). [Ryszard Rozak, Antmicro Ltd.] * Fix preprocessor to show `line 2 on resumed file. Verilator 5.016 2023-09-16 ========================== **Minor:** * Add prepareClone and atClone APIs for Verilated models (#3503) (#4444). [Yinan Xu] * Add check for conflicting options e.g. binary and lint-only (#4409). [Ethan Sifferman] * Add --no-trace-top to not trace top signals (#4412) (#4422). [Frans Skarman] * Support recursive function calls (#3267). * Support assignments of packed values to stream expressions on queues (#4401). [Ryszard Rozak, Antmicro Ltd] * Support no-parentheses calls to static methods (#4432). [Krzysztof Boroński] * Support block_item_declaration in forks (#4455). [Krzysztof Boroński] * Support assignments of stream expressions on queues to packed values (#4458). [Ryszard Rozak, Antmicro Ltd] * Support function non-constant default arguments (#4470). * Support 'let'. * Optimize Verilator executable size by refactoring error reporting routines (#4446). [Anthony Donlon] * Optimize Verilation runtime pointers and graphs (#4396) (#4397) (#4398). [Krzysztof Bieganski, Antmicro Ltd] * Optimize preparations towards multithreaded Verilation (#4291) (#4463) (#4476) (#4477) (#4479). [Kamil Rakoczy, Antmicro Ltd] * Fix Windows filename format, etc (#3873) (#4421). [Anthony Donlon]. * Fix t_dist_cppstyle Perl performance issue (#4085). [Srinivasan Venkataramanan] * Fix using type in parameterized classes without #() (#4281) (#4440). [Anthony Donlon] * Fix false INFINITELOOP on forever..mailbox.get() (#4323). [Srinivasan Venkataramanan] * Fix data type of condition operation on class objects (#4345) (#4352). [Ryszard Rozak, Antmicro Ltd] * Fix variables mutated under fork..join_none/join_any blocks into anonymous objects (#4356). [Krzysztof Boroński] * Fix V3CUse, do not consider implementations (.cpp) at all (#4386). [Krzysztof Boroński] * Fix ++/-- under statements (#4399). [Aleksander Kiryk, Antmicro Ltd] * Fix detection of mixed blocking and nonblocking assignment in nested assignments (#4404). [Ryszard Rozak, Antmicro Ltd] * Fix jumping over object initialization (#4411). [Krzysztof Boroński] * Fix multiple issues towards short circuit support (#4413) (#4460). [Ryszard Rozak, Antmicro Ltd] * Fix variable lifetimes in extern methods (#4414). [Krzysztof Boroński] * Fix multiple function definitions in V3Sched (#4416). [Hennadii Chernyshchyk] * Fix false UNUSEDPARAM on generate localparam (#4427). [Bill Pringlemeir] * Fix checking for parameter and port connections in the wrong place (#4428). [Anthony Donlon] * Fix coroutine handle movement during queue manipulation (#4431). [Aleksander Kiryk, Antmicro Ltd] * Fix nested assignments on the LHS (#4435). [Ryszard Rozak, Antmicro Ltd] * Fix false MULTITOP on bound interfaces (#4438). [Alex Solomatnikov] * Fix internal error on real conversion (#4447). [vdhotre-ventana] * Fix lifetime unknown error on enum.name (#4448). [Johan Wouters] * Fix unstable output of VHashSha256 (#4453). [Anthony Donlon] * Fix static cast from a stream type (#4469) (#4485). [Ryszard Rozak, Antmicro Ltd] * Fix error on enum with VARHIDDEN of cell (#4482). [Michail Rontionov] * Fix lint of case statements with enum and wildcard bits (#4464) (#4487). [Anthony Donlon] * Fix reference to extended class in parameterized class (#4466). * Fix recursive display causing segfault (#4480). [Kuoping Hsu] * Fix the error message when the type of ref argument is wrong (#4490). [Ryszard Rozak, Antmicro Ltd] * Fix display %x formatting of real. * Fix mis-warning on #() in classes' own functions. * Fix IGNOREDRETURN to not warn on void-cast static function calls. * Fix ZERODLY to not warn on 'wait(0)'. Verilator 5.014 2023-08-06 ========================== **Minor:** * Deprecation planned for 32-bit pointer -m32 mode (#4268). * Deprecate CMake config below version 3.13 (#4389) (#4390). [Vito Gamberini] * Support some stream operations on queues (#4292). [Ryszard Rozak, Antmicro Ltd] * Support property declaration with empty parentheses (#4313) (#4317). [Anthony Donlon] * Support locator methods with "with" on assoc arrays (#4335). [Ryszard Rozak, Antmicro Ltd] * Support string replication with variable (#4341). [Aleksander Kiryk, Antmicro Ltd] * Support more types in wait (#4374). [Aleksander Kiryk, Antmicro Ltd] * Support static method calls as default values of function arguments (#4378). [Ryszard Rozak, Antmicro Ltd] * Add GENUNNAMED lint warning. [Srinivasan Venkataramanan, Deepa Palaniappan] * Add MISINDENT lint warning for misleading indentation. * Fix 'VlForkSync' redeclaration (#4277). [Krzysztof Bieganski, Antmicro Ltd] * Fix processes that can outlive their parents (#4253). [Krzysztof Boronski, Antmicro Ltd] * Fix duplicate fork names (#4295). [Ryszard Rozak, Antmicro Ltd] * Fix splitting coroutines (#4297) (#4307). [Jiamin Zhu] * Fix error when multiple duplicate DPI exports (#4301). * Fix class reference assignment checking (#4296). [Ryszard Rozak, Antmicro Ltd] * Fix handling of ref types in initial values of type parameters (#4304). [Ryszard Rozak, Antmicro Ltd] * Fix comparison of string parameters (#4308). [Ryszard Rozak, Antmicro Ltd] * Fix state update for always processes (#4311). [Aleksander Kiryk, Antmicro Ltd] * Fix multiple edge timing controls in class methods (#4318) (#4320) (#4344). [Krzysztof Bieganski, Antmicro Ltd] * Fix implicit calls of base class constructors with optional arguments (#4319). [Ryszard Rozak, Antmicro Ltd] * Fix propagation of process requirement (#4321). [Krzysztof Boroński] * Fix unhandled overloads in V3InstrCount (#4324). [Krzysztof Boroński] * Fix selects of static members (#4326). [Ryszard Rozak, Antmicro Ltd] * Fix references to members of results of static methods (#4327). [Ryszard Rozak, Antmicro Ltd] * Fix unique..with method on queues of class objects (#4328). [Ryszard Rozak, Antmicro Ltd] * Fix queue slicing (#4329). [Aleksander Kiryk, Antmicro Ltd] * Fix wildcard referring types (#4336) (#4342). [Aleksander Kiryk, Antmicro Ltd] * Fix comparison of class objects (#4346). [Ryszard Rozak, Antmicro Ltd] * Fix unexpected RefDType on assoc arrays (#4337). [Aleksander Kiryk, Antmicro Ltd] * Fix cmake astgen for Rocky Linux 8.7 (#4343). [Julian Daube] * Fix class timescale in class packages (#4348). [Krzysztof Bieganski, Antmicro Ltd] * Fix string concatenations (#4354). [Ryszard Rozak, Antmicro Ltd] * Fix unlinked task error from broken context (#4355) (#4402). [Aleksander Kiryk, Antmicro Ltd] * Fix selects on unpacked structs (#4359). [Ryszard Rozak, Antmicro Ltd] * Fix select operation on assoc array with wide keys (#4360). [Ryszard Rozak, Antmicro Ltd] * Fix non-public methods with wide output (#4364). [Ryszard Rozak, Antmicro Ltd] * Fix handling of super.new calls (#4366). [Ryszard Rozak, Antmicro Ltd] * Fix assign to input var in methods (#4367). [Aleksander Kiryk, Antmicro Ltd] * Fix VlProcess not found (#4368). [Aleksander Kiryk, Antmicro Ltd] * Fix order of evaluation of function calls in statements (#4375). [Ryszard Rozak, Antmicro Ltd] * Fix config_build.h issues (#4380) (#4381). [Andrew Miloradovsky] Verilator 5.012 2023-06-13 ========================== **Major:** * With -j or --build-jobs, multithread Verilator's emit phase of Verilation. [Kamil Rakoczy, Antmicro Ltd] Additional Verilator-internal stages will become multithreaded over time. **Minor:** * Add --main-top-name option for C main TOP name (#4235) (#4249). [Don Williamson] * Add creating __inputs.vpp file with --debug (#4177). [Tudor Timi] * Add NEWERSTD warning when using feature in newer language standard (#4168) (#4172). [Ethan Sifferman] * Add warning that timing controls in DPI exports are unsupported (#4238). [Krzysztof Bieganski, Antmicro Ltd] * Support std::process class (#4212). [Aleksander Kiryk, Antmicro Ltd] * Support inside expressions with strings and doubles (#4138) (#4139). [Krzysztof Boroński] * Support get_randstate/set_randstate class method functions. * Support for condition operator on class objects (#4214). [Ryszard Rozak, Antmicro Ltd] * Support array max (#4275). [Aleksander Kiryk, Antmicro Ltd] * Optimize VPI callValueCbs (#4155). [Hennadii Chernyshchyk] * Configure for faster C++ linking using 'mold', if it is installed. * Fix crash on duplicate imported modules (#3231). [Robert Balas] * Fix false WIDTHEXPAND on array declarations (#3959). [Jose Tejada] * Fix marking overridden methods as coroutines (#4120) (#4169). [Krzysztof Bieganski, Antmicro Ltd] * Fix SystemC signal copy macro use (#4135). [Josep Sans] * Fix duplicate static names in blocks in functions (#4144) (#4160). [Stefan Wallentowitz] * Fix initialization order of initial static after function/task (#4159). [Kamil Rakoczy, Antmicro Ltd] * Fix linking AstRefDType if it has parameterized class ref (#4164) (#4170). [Ryszard Rozak, Antmicro Ltd] * Fix crash caused by $display() optimization (#4165) (#4166). [Tudor Timi] * Fix arrays of unpacked structs (#4173). [Risto Pejašinović] * Fix $fscanf of decimals overflowing variables (#4174). [Ahmed El-Mahmoudy] * Fix super.new missing data type (#4147). [Tudor Timi] * Fix missing class forward declarations (#4151). [Krzysztof Boroński] * Fix hashes of instances of parameterized classes (#4182). [Ryszard Rozak, Antmicro Ltd] * Fix forced assignments that override non-continuous assignments (#4183) (#4192). [Krzysztof Bieganski, Antmicro Ltd] * Fix wide structure VL_TOSTRING_W generation (#4188) (#4189). [Aylon Chaim Porat] * Fix references to members of parameterized base classes (#4196). [Ryszard Rozak, Antmicro Ltd] * Fix tracing undefined alignment (#4201) (#4288) [John Wehle] * Fix class-specific same methods for AstVarScope, AstVar, and AstScope (#4203) (#4250). [John Wehle] * Fix dotted references in parameterized classes (#4206). [Ryszard Rozak, Antmicro Ltd] * Fix bit selections under parameterized classes (#4210). [Ryszard Rozak, Antmicro Ltd] * Fix duplicate std:: declaration with -I (#4215). [Harald Pretl] * Fix deep traversal of class inheritance timing (#4216). [Krzysztof Boroński] * Fix class parameters of enum types (#4219). [Ryszard Rozak, Antmicro Ltd] * Fix static methods with prototypes (#4220). [Ryszard Rozak, Antmicro Ltd] * Fix LATCH warning on function local variables (#4221) (#4284) [Julien Margetts] * Fix VCD scope types (#4227) (#4282). [Àlex Torregrosa] * Fix incorrect multi-driven lint warning (#4231) (#4248). [Adrien Le Masle] * Fix missing assignment for wide unpacked structs (#4233). [Jiamin Zhu] * Fix unpacked struct == and != operators (#4234) (#4240). [Risto Pejašinović] * Fix AstStructSel clean when data type is structure (#4241) (#4244). [Risto Pejašinović] * Fix function calls in with statements (#4245). [Ryszard Rozak, Antmicro Ltd] * Fix operator == for unpacked struct, if elements are VlUnpacked arrays (#4247). [Risto Pejašinović] * Fix STATIC lifetime for variables created from clocking items (#4262). [Krzysztof Boroński] * Fix names of foreach blocks (#4264). [Ryszard Rozak, Antmicro Ltd] * Fix iterated variables in foreach loops to have VAUTOM lifetimes (#4265). [Krzysztof Boroński] * Fix missing assignment for wide class members (#4267). [Jiamin Zhu] * Fix the global uses timing flag when forks exist (#4274). [Krzysztof Bieganski, Antmicro Ltd] * Fix struct redefinition (#4276). [Aleksander Kiryk, Antmicro Ltd] * Fix detection of wire/reg duplicates. * Fix false IMPLICITSTATIC on package functions. * Fix method calls on function return values. Verilator 5.010 2023-04-30 ========================== **Minor:** * Add --public-depth to force public to a certain instance depth (#3952). [Andrew Nolte] * Add --public-params flag (#3990). [Andrew Nolte] * Add CONSTRAINTIGN warning when constraint ignored. * Add STATICVAR warning and convert to automatic (#4018) (#4027) (#4030). [Ryszard Rozak, Antmicro Ltd] * Add error if class types don't match (#4064). [Ryszard Rozak, Antmicro Ltd] * Support class extends of package::class. * Support class srandom and class random stability. * Support class method calls without parenthesis (#3902) (#4082). [Srinivasan Venkataramanan] * Support method calls without parenthesis (#4034). [Ryszard Rozak, Antmicro Ltd] * Support parameterized return types of methods (#4122). [Ryszard Rozak, Antmicro Ltd] * Support parameterized class references in extends statement (#4146). [Ryszard Rozak, Antmicro Ltd] * Support complicated IEEE 'for' assignments. * Support $fopen as an expression. * Support ++/-- on dotted member variables. * Optimize static trigger evaluation (#4142). [Geza Lore, X-EPIC] * Optimize more xor trees (#4071). [Yutetsu TAKATSUKASA] * Change range order warning from LITENDIAN to ASCRANGE (#4010). [Iztok Jeras] * Change ZERODLY to a warning. * Fix random internal crashes (#666). [Dag Lem] * Fix install, standardization in cmake CMakeLists.txt (#3974). [Yu-Sheng Lin] * Fix UNDRIVEN warning seg fault (#3989). [Felix Neumärker] * Fix symbol entries when inheriting classes (#3995) (#3996). [Krzysztof Boroński] * Fix event controls reusing same variable (#4014). Kamil Rakoczy * Fix push to dynamic queue in struct (#4015). [ezchi] * Fix names for blocks in do..while loop (#4019). [Ryszard Rozak, Antmicro Ltd] * Fix randomize on null field (#4023). [Ryszard Rozak, Antmicro Ltd] * Fix rand fields in base classes (#4025). [Ryszard Rozak, Antmicro Ltd] * Fix large return blocks with --comp-limit-blocks (#4028). [tenghtt] * Fix clocking block scope internal error (#4032). [Srinivasan Venkataramanan] * Fix false LATCH warning on --assert 'unique else if' (#4033) ($4054). [Jesse Taube] * Fix characters from DEFENV literals for Conda (#4035) (#4044). [Tim Snyder] * Fix info message prints under --assert (#4036) (#4053). [Srinivasan Venkataramanan] * Fix C++ compile errors when passing class refs as task argument (#4063). [Krzysztof Bieganski, Antmicro Ltd] * Fix NBAs inside fork-joins (#4050). [Aleksander Kiryk, Antmicro Ltd] * Fix task calls as fork statements (#4055). [Krzysztof Bieganski, Antmicro Ltd] * Fix _Vilp used before declaration (#4057) (#4062). [Josep Sans] * Fix incorrect optimization of bit op tree (#4059) (#4070). [Yutetsu TAKATSUKASA] * Fix parameters in a class body to be localparam (#4061). [Ryszard Rozak, Antmicro Ltd] * Fix interface generate begin (#4065). [Srinivasan Venkataramanan] * Fix tracing with awaits at end of block (#4075) (#4076). [Krzysztof Bieganski, Antmicro Ltd] * Fix sense expression variable naming (#4081). [Kamil Rakoczy] * Fix importing symbols from base class (#4084). [Ryszard Rozak, Antmicro Ltd] * Fix false error on new const assignment (#4098). [Tudor Timi] * Fix unpacked structs under classes (#4102). [Tudor Timi] * Fix variables in class methods to be automatic (#4111) (#4137). [Peter Monsson] * Fix to use parallel build for projects with a lot of files (#4116). [Krzysztof Boroński] * Fix including __Syms header in generated C++ files (#4123). [Krzysztof Boroński] * Fix systemc namespace issues (#4126) (#4127). [Eyck Jentzsch] * Fix class param extends A=B (#4128). [Ryszard Rozak, Antmicro Ltd] * Fix missing begin block hierarchy in --xml-only cells section (#4129) (#4133). [Risto Pejašinović] * Fix resolution of class lvalues after parameterization (#4131). [Krzysztof Boroński] * Fix DFG error on $countbits (#4101) (#4143). [Paul Donahue] * Fix duplicating parameter class types (#4115). [Ryszard Rozak, Antmicro Ltd] * Fix class extend param references (#4136). [Ryszard Rozak, Antmicro Ltd] * Fix -CFLAGS to allow overriding optimization levels (#4140). [Peter Monsson] * Fix DPI function type alias (#4148) (#4149). [Toru Niina] * Fix deleting unused parameterized classes (#4150). [Ryszard Rozak, Antmicro Ltd] * Fix false ENUMVALUE on expressions and arrays. * Fix unnecessary verilated_std.sv waivers in --waiver-output. Verilator 5.008 2023-03-04 ========================== **Minor:** * Add --annotate-points option, change multipoint on line reporting (#3876). [Nassim Corteggiani] * Add --verilate-jobs option (#3889). [Kamil Rakoczy, Antmicro Ltd] * Add WIDTHEXPAND and WIDTHTRUNC warnings to replace WIDTH (#3900). [Andrew Nolte] * Add SOURCE_DATE_EPOCH for docs/guide/conf.py (#3918). [Larry Doolittle] * Add /*verilator public[flat|flat_rd|flat_rw| ]*/ metacomments (#3894). [Joseph Nwabueze] * Add lint warning on always_comb multidriven (#3888) (#3939). [Adam Bagley] * Add warning on ++/-- over expressions with potential side effects (#3976). [Krzysztof Boroński] * Add error on mixing .name and by-port instantiations. * Removed deprecated --cdc option. * Support unpacked unions. * Support interface classes and class implements. * Support global clocking and $global_clock. * Support class parameters without initial values. * Support cast to numbers from strings. * Support struct I/O in --lib-create (#3378) (#3892). [Varun Koyyalagunta] * Support function calls without parenthesis (#3903) (#3902). [Ryszard Rozak, Antmicro Ltd] * Support class extending its parameter (#3904). [Ryszard Rozak, Antmicro Ltd] * Support static function variables (#3830). [Ryszard Rozak, Antmicro Ltd] * Support recursive methods (#3987). [Ryszard Rozak, Antmicro Ltd] * Fix real parameters of infinity and NaN. * Fix pattern assignment to unpacked structs (#3510). [Mostafa Garnal] * Fix single-element replication to dynarray/unpacked/queue (#3548). [Gustav Svensk] * Fix constant enum methods (#3621). [Todd Strader] * Fix inconsistent naming of generate scope arrays (#3840). [Andrew Nolte] * Fix namespace fallback resolution (#3863) (#3942). [Aleksander Kiryk, Antmicro Ltd] * Fix std:: to be parsed first (#3864) (#3928). [Aleksander Kiryk, Antmicro Ltd] * Fix cmake warning if multiple SOURCES w/o PREFIX (#3916) (#3927). [Yoda Lee] * Fix parameterized class function linkage (#3917). [Ryszard Rozak] * Fix static members of type aliases of a parameterized class (#3922). [Ryszard Rozak, Antmicro Ltd] * Fix class extend parameter dot case (#3926). [Ryszard Rozak, Antmicro Ltd] * Fix MsWin missing directory exception, and ::std (#3928) (#3933) (#3935). [Kritik Bhimani] * Fix very long VPI signal names (#3929). [Marlon James] * Fix VPI upper interface scopes not found (#3937). [David Stanford] * Fix virus detection false positive (#3944). [Stuart Morris] * Fix constant string function assignment (#3945). [Todd Strader] * Fix constant format field widths (#3946). [Todd Strader] * Fix class field linking when a super classes is a param (#3949). [Ryszard Rozak, Antmicro Ltd] * Fix CMake bad C identifiers (#3948) (#3951). [Zixi Li] * Fix build on HP PA architecture (#3954). [John David Anglin] * Fix date on the front page of verilator.pdf (#3956) (#3957). [Larry Doolittle] * Fix associative arrays declared with ref type (#3960). [Ryszard Rozak, Antmicro Ltd] * Fix missing error on negative replicate (#3963). [Benjamin Menküc] * Fix self references to parameterized classes (#3962). [Ryszard Rozak, Antmicro Ltd] * Fix LITENDIAN warning is backwards (#3966) (#3967). [Cameron Kirk] * Fix subsequent parameter declarations (#3969). [Ryszard Rozak, Antmicro Ltd] * Fix timing delays to not truncate below 64 bits (#3973) (#3982). [Felix Neumärker] * Fix cmake on MacOS to mark weak symbols with -U linker flag (#3978) (#3979). [Peter Debacker] * Fix UNDRIVEN warning seg fault (#3989). [Felix Neumärker] * Fix coverage of class methods (#3998). [Tim Paine] * Fix packed array structure replication. * Fix enum.next(0) and enum.prev(0). Verilator 5.006 2023-01-22 ========================== **Minor:** * Support clocking blocks (#3674). [Krzysztof Bieganski, Antmicro Ltd] * Support unpacked structs (#3802). [Aleksander Kiryk, Antmicro Ltd] * Support Windows-native builds using cmake (#3814). [Kritik Bhimani] * Support p format for UnpackArray (#3877). [Aleksander Kiryk, Antmicro Ltd] * Support property calls without parenthesis (#3879) (#3893). [Ryszard Rozak, Antmicro Ltd] * Support import/export lists in modport (#3886). [Gökçe Aydos] * Support class queue equality (#3895). [Ilya Barkov] * Support type case and type equality comparisons. * Add IMPLICITSTATIC warning when a task/function is implicitly static (#3839). [Ryszard Rozak, Antmicro Ltd] * Add VL_VALUE_STRING_MAX_WORDS override (#3869). [Andrew Nolte] * Optimize expansion of extend operators. * Internal multithreading tests. [Mariusz Glebocki, et al, Antmicro Ltd] * Fix VPI one-time timed callbacks (#2778). [Marlon James, et al] * Fix initiation of function variables (#3815). [Dan Gisselquist] * Fix to zero possibly uninitialized bits in replications (#3815). * Fix crash in DFT due to width use after free (#3817) (#3820). [Jevin Sweval] * Fix signed/unsigned comparison compile warning (#3822). [Kamil Rakoczy] * Fix OS-X weak symbols with -U linker flag (#3823). [Jevin Sweval] * Fix wrong bit op tree optimization (#3824) (#3825). [Yutetsu TAKATSUKASA] * Fix self references when param class instantiated (#3833). [Ryszard Rozak, Antmicro Ltd] * Fix memory leak in V3Sched, etc. (#3834). [Geza Lore] * Fix compatibility with musl libc / Alpine Linux (#3845). [Sören Tempel] * Fix empty case items crash (#3851). [Rich Porter] * Fix VL_CPU_RELAX on MIPS/Armel/s390/sparc (#3843) (#3891). [Kamil Rakoczy] * Fix module parameter name collision (#3854) (#3855). [James Shi] * Fix unpacked array expansion (#3861). [Joey Liu] * Fix signed/unsigned parameter types (#3866). [James Shi] * Fix chain call of abstract class constructor (#3868) (#3883). [Ilya Barkov] * Fix to use same std in Verilator and Verilated compile (#3881). [Kamil Rakoczy, Antmicro Ltd] * Fix foreach unnamedblk duplicate error (#3885). [Ilya Barkov] * Fix elaboration of member selected classes (#3890). [Ilya Barkov] * Fix mismatched widths in DFG (#3872). [Geza Lore, Yike Zhou] * Fix lint for non-integral types in packed structs. * Fix generate case with empty body statements. Verilator 5.004 2022-12-14 ========================== **Major:** * Support named properties (#3667). [Ryszard Rozak, Antmicro Ltd] * Add ENUMVALUE warning when value misused for enum (#726) (#3777) (#3783). * Deprecate --no-threads; use --threads 1 for single threaded (#3703). [Kamil Rakoczy, Antmicro Ltd] **Minor:** * Support std::semaphore and typed std::mailbox (#3708). [Krzysztof Bieganski, Antmicro Ltd] * Support 'with' in unique, unique_index, min, max in queues (#3772). [Ryszard Rozak, Antmicro Ltd] * Support events in VCD/FST traces (#3759). [Yves Mathieu] * Support foreach loops on strings (#3760). [Ryszard Rozak, Antmicro Ltd] * Support member selects in with clauses (#3775). [Ryszard Rozak, Antmicro Ltd] * Support super.new calls (#3789). [Ryszard Rozak, Antmicro Ltd] * Support randcase. * Support pre_randomize and post_randomize. * Support $timeunit and $timeprecision. * Support assignment expressions. * Change ENDLABEL from warning into an error. * Internal AST improvements, also affect XML format (#3721). [Geza Lore] * Deprecate verilated_fst_sc.cpp and verilated_vcd_sc.cpp. * Disable stack size limit (#3706) (#3751). [Mariusz Glebocki] * Add error when use --exe with --lib-create (#3785). [Yinan Xu] * Fix jump handling in do while loops (#3731). [Ryszard Rozak, Antmicro Ltd] * Fix 'with' clause handling in functions (#3739). [Ryszard Rozak, Antmicro Ltd] * Fix CONTEXT compile error on MingW (#3741). [William D. Jones] * Fix MSVC compiler errors (#3742) (#3746). [Kritik Bhimani] * Fix CASEINCOMPLETE when covers all enum values (#3745) (#3782). [Guy-Armand Kamendje] * Fix return type of $countbits functions to int (#3725). [Ryszard Rozak, Antmicro Ltd] * Fix timing control in while-break loops (#3733) (#3769). [Ryszard Rozak, Antmicro Ltd] * Fix return in constructors (#3734). [Ryszard Rozak, Antmicro Ltd] * Fix missing UNUSED warnings with --coverage (#3736). [alejandro-castro-ortegon] * Fix tracing parameters overridden with -G (#3723). [Iztok Jeras] * Fix folding of LogAnd with non-bool operands (#3726). [Geza Lore] * Fix DFG optimization issues (#3740) (#3771). [Geza Lore] * Fix pre/postincrement operations (#3744) (#3756). [Ryszard Rozak, Antmicro Ltd] * Fix cross-compile for MingW, Arm and RISC-V (#3752). [Miodrag Milanović] * Fix $unit as base package for other packages (#3755). [Ryszard Rozak, Antmicro Ltd] * Fix make jobserver with submakes (#3758). [Gus Smith] * Fix to escape VERILATOR_ROOT file paths (#3764) (#3765). [Jiacheng Qian] * Fix empty string literals converting to string types (#3774). [miree] * Fix to remove $date from .vcd files (#3779). [Larry Doolittle] * Fix missing user objects in --lib-create mode (#3780) (#3784). [Yinan Xu] * Fix non-blocking assignments in forks (#3781) (#3800). [Krzysztof Bieganski, Antmicro Ltd] * Fix forks without any delayed statements (#3792) (#3801). [Krzysztof Bieganski, Antmicro Ltd] * Fix internal error in bit op tree optimization (#3793). [Yutetsu TAKATSUKASA] * Fix lint_off EOFNEWLINE in .vlt files (#3796). [Andrew Nolte] * Fix wait 0. * Fix comparing ranged slices of unpacked arrays. Verilator 5.002 2022-10-29 ========================== **Major:** * This is a major new release. * Require C++20 for the new --timing features. Upgrading to a C++20 or newer compiler is strongly recommended. * Support the Active and NBA scheduling regions as defined by the SystemVerilog standard (IEEE 1800-2017 chapter 4). This means all generated clocks are now simulated correctly (#3278, #3384). [Geza Lore, Shunyao CAD] * Support timing controls (delays, event controls in any location, wait statements) and forks. [Krzysztof Bieganski, Antmicro Ltd] This may require adding --timing or --no-timing. See docs for details. * Introduce a new combinational logic optimizer (DFG), that can yield significant performance improvements on some designs. [Geza Lore, Shunyao CAD] * Add --binary option as alias of --main --exe --build --timing (#3625). For designs where C++ was only used to make a simple no-I/O testbench, we recommend abandoning that C++, and instead letting Verilator build it with --binary (or --main). **Minor:** * Split UNUSED warning into genvar, param, and signal warnings (#3607). [Topa Topino] * Support standalone 'this' in classes (#2594) (#3248) (#3675). [Arkadiusz Kozdra, Antmicro Ltd] * Support tristate select/extend (#3604). [Ryszard Rozak, Antmicro Ltd> * Support linting for top module interfaces (#3635). [Kanad Kanhere] * Support virtual interfaces (#3654). [Arkadiusz Kozdra, Antmicro Ltd] * Support class type params without defaults (#3693). [Krzysztof Bieganski, Antmicro Ltd] * Support empty generate_regions (#3695). [mpb27] * Support access to constructs inside type parameters (#3702). [Arkadiusz Kozdra, Antmicro Ltd] * Add --dump-tree-dot to enable dumping Ast Tree .dot files (#3636). [Marcel Chang] * Add --get-supported to determine what features are in Verilator. * Add error on real edge event control. * Fix false LATCH warning on 'unique if' (#3088). [Rachit Nigam] * Fix cell assigning integer array parameters (#3299). [Michael Platzer] * Fix LSB error on --hierarchical submodules (#3539). [danbone] * Fix $display of fixed-width numbers (#3565). [Iztok Jeras] * Fix foreach and pre/post increment in functions (#3613). [Nandu Raj] * Fix linker errors in user-facing timing functions (#3657). [Krzysztof Bieganski, Antmicro Ltd] * Fix null access on optimized-out fork statements (#3658). [Krzysztof Bieganski, Antmicro Ltd] * Fix VPI inline module naming mismatch (#3690) (#3694). [Jiuyang Liu] * Fix deadlock in timeprecision when using SystemC (#3707). [Kamil Rakoczy, Antmicro Ltd] * Fix width mismatch on inside operator (#3714). [Àlex Torregrosa] Verilator 4.228 2022-10-01 ========================== **Announcement:** * The next release is anticipated to premiere Verilator Version 5. Please consider beta-testing the github 'develop-v5' branch, which will soon merge into the github 'master' branch (#3383). **Minor:** * Support some IEEE signal strengths (#3601) (#3629). [Ryszard Rozak, Antmicro Ltd] * Add --main to generate main() C++ (previously was experimental only). * Add --build-jobs, and rework arguments for -j (#3623). [Kamil Rakoczy] * Rename --bin to --build-dep-bin. * Rename debug flags --dumpi-tree, --dumpi-graph, etc. [Geza Lore] * Fix thread safety in SystemC VL_ASSIGN_SBW/WSB (#3494) (#3513). [Mladen Slijepcevic] * Fix crash in gate optimization of circular logic (#3543). [Bill Flynn] * Fix arguments in non-static method call (#3547) (#3582). [Gustav Svensk] * Fix default --mod-prefix when --prefix is repeated (#3603). [Geza Lore] * Fix calling trace() after open() segfault (#3610) (#3627). [Yu-Sheng Lin] * Fix typedef'ed class conversion to Boolean (#3616). [Aleksander Kiryk] * Fix Verilation speed when disabled warnings (#3632). [Kamil Rakoczy, Antmicro Ltd] Verilator 4.226 2022-08-31 ========================== **Minor:** * Add --future0 and --future1 options. * Support class parameters (#2231) (#3541). [Arkadiusz Kozdra, Antmicro Ltd] * Support wildcard index associative arrays (#3501). [Arkadiusz Kozdra, Antmicro Ltd] * Support negated properties (#3572). [Aleksander Kiryk] * Support $test$plusargs(expr) (#3489). * Rename trace rolloverSize() (#3570). * Improve Verilation speed with --threads on large designs. [Geza Lore] * Improve Verilation memory by reducing V3Number (#3521). [Mariusz Glebocki, Antmicro Ltd] * Fix struct pattern assignment (#2328) (#3517). [Mostafa Gamal] * Fix public combo propagation issues (#2905). [Todd Strader] * Fix incorrect tristate logic (#3399) [shareefj, Vighnesh Iyer] * Fix incorrect bit op tree optimization (#3470). [algrobman] * Fix bisonpre for MSYS2 (#3471). * Fix max memory usage (#3483). [Kamil Rakoczy, Antmicro Ltd] * Fix empty string arguments to display (#3484). [Grulfen] * Fix table optimizing away display (#3488). [Stefan Post] * Fix unique_ptr memory header for MinGW64 (#3493). * Fix $dump system task with --output-split-cfuncs (#3495) (#3497). [Varun Koyyalagunta] * Fix wrong bit op tree optimization (#3509). [Nathan Graybeal] * Fix nested default assignment for struct pattern (#3511) (#3524). [Mostafa Gamal] * Fix sformat string incorrectly cleared (#3515) (#3519). [Gustav Svensk] * Fix segfault exporting non-existent package (#3535). * Fix void-cast queue pop_front or pop_back (#3542) (#3364). [Drew Ranck] * Fix case statement comparing string literal (#3544). [Gustav Svensk] * Fix === with some tristate constants (#3551). [Ryszard Rozak, Antmicro Ltd] * Fix converting classes to string (#3552). [Arkadiusz Kozdra, Antmicro Ltd] * Fix --hierarchical with order-based pin connections (#3583) (#3585). [Kelin9298] Verilator 4.224 2022-06-19 ========================== **Major:** * VCD tracing is now parallelized with --threads (#3449). [Geza Lore, Shunyao CAD] **Minor:** * Add -f options to replace -O options (#3436). * Changed --no-merge-const-pool to -fno-merge-const-pool (#3436). * Changed --no-decoration to remove output whitespace (#3460). [Kamil Rakoczy] * Support compile time trace signal selection with tracing_on/off (#3323). [Shunyao CAD] * Support non-ANSI interface port declarations (#3439). [Geza Lore, Shunyao CAD] * Support concat assignment to packed array (#3446). * Improve conditional merging optimization (#3125). [Geza Lore, Shunyao CAD] * Define VM_TRACE_VCD when tracing in VCD format. [Geza Lore, Shunyao CAD] * Add assert when VerilatedContext is mis-deleted (#3121). [Rupert Swarbrick] * Internal prep work towards timing control. [Krzysztof Bieganski, Antmicro Ltd] * Fix hang with large case statement optimization (#3405). [Mike Urbach] * Fix UNOPTFLAT warning from initial static var (#3406). [Kamil Rakoczy] * Fix compile error when enable VL_LEAK_CHECKS (#3411). [HungMingWu] * Fix cmake rules to support higher-level targets (#3377) (#3386). [Martin Stadler] * Fix BLKANDNBLK on $readmem/$writemem (#3379). [Alex Solomatnikov] * Fix 'with' operator with type casting (#3387). [xiak95] * Fix incorrect conditional merging (#3409). [Raynard Qiao] * Fix passing VL_TRACE_FST_WRITER_THREAD in CMake build. [Geza Lore, Shunyao CAD] * Fix compile error under strict C++11 mode (#3463). [Kevin Kiningham] * Fix public unpacked input ports (#3465). [Todd Strader] Verilator 4.222 2022-05-02 ========================== **Minor:** * Split --prof-threads into --prof-exec and --prof-pgo (#3365). [Geza Lore, Shunyao CAD] * Deprecate 'vluint64_t' and similar types (#3255). * Raise error on assignment to const in initial blocks. [Geza Lore, Shunyao CAD] * Issue INITIALDLY/COMBDLY/BLKSEQ warnings consistent with Verilator execution. [Geza Lore, Shunyao CAD] * Support LoongArch ISA multithreading (#3353) (#3354). [Xi Zhang] * Fix MSVC localtime_s (#3124). * Fix Bison 3.8.2 error (#3366). [elike-ypq] * Fix rare bug in -Oz (V3Localize) (#3286). [Geza Lore, Shunyao CAD] * Fix tracing interfaces inside interfaces (#3309). [Kevin Millis] * Fix filenames with dots overwriting debug .vpp files (#3373). * Fix including VK_USER_OBJS in make library (#3370) (#3382). [Julien Margetts] * Fix hang in generate symbol references (#3391) (#3398). [Yoda Lee] * Fix missing #include (#3392). [Aliaksei Chapyzhenka] * Fix crash in recursive module inlining (#3393). [david-sawatzke] * Fix --protect-ids mangling names of library methods. [Geza Lore, Shunyao CAD] * Fix foreach segmentation fault (#3400). [Kamil Rakoczy] Verilator 4.220 2022-03-12 ========================== **Minor:** * Removed the deprecated lint_off flag -msg; use -rule instead. * Removed the deprecated "fl" attribute in XML output; use "loc" attribute instead. * Suppress WIDTH warning on negate using carry bit (#3295). [Peter Monsson] * Add trace dumpvars() call for selective runtime tracing (#3322). [Shunyao CAD] * Add VERILATOR_VERSION_INTEGER for determining API (#3343). [Larry Doolittle] * Improve various V3Combine algorithm details (#3328). [Yutetsu TAKATSUKASA] * Improve various V3Order algorithm details. [Geza Lore] * Fix MacOS arm64 build (#3285) (#3291). [Guokai Chen] * Fix signed number operation (#3294) (#3308). [Raynard Qiao] * Fix FST traces to include vector range (#3296) (#3297). [Jamie Iles] * Fix skipping public enum values with four-state values (#3303). * Fix $readmem file not found to be warning not error (#3310). [Alexander Grobman] * Fix class stringification on wide arrays (#3312). [Iru Cai] * Fix $fscanf etc to return -1 on EOF (#3313). [Jose Tejada] * Fix public function arguments that are arrayed (#3316). [pawel256] * Fix unnamedblk error on foreach (#3321). [Aliaksei Chapyzhenka] * Fix crash in recursive module inlining (#3324). [Larry Doolittle] * Fix VL_RESTORER behavior on passing a lvalue reference (#3326). [HungMingWu] * Fix compile error with --trace-fst --sc (#3332). [leavinel] * Fix cast to array types (#3333). [Todd Strader] * Fix Vdeeptemp error with --threads and --compiler clang (#3338). [Per Karlsson] Verilator 4.218 2022-01-17 ========================== **Major:** * Primary inputs and outputs (VL_INW/VL_OUTW) now use VlWide type. In general this should be backward compatible, but may lead to some wrapper code needing changes. * Option --cdc is deprecated and is planned for removal, file a bug if this is still being used. **Minor:** * Support class static members (#2233). * Support force/release (#2431) (#2593). [Shunyao CAD] * Add 'forceable' attribute to allow forcing from C++ (#3272). [Geza Lore, Shunyao CAD] * Support lower dimension looping in foreach loops (#3172). [Ehab Ibrahim] * Support up to 64 bit enums for .next/.prev/.name (#3244). [Alexander Grobman] * Reduce .rodata footprint of trace initialization (#3250). [Geza Lore, Shunyao CAD] * Support FST tracing in hierarchical Verilation (#3251). [Yutetsu TAKATSUKASA] * Use C++11 standard types for MacOS portability (#3254) (#3257). [Adrien Le Masle] * Fix make support for BSD ar (#2999) (#3256). [Julie Schwartz] * Fix bad ending address on $readmem (#3205). [Julie Schwartz] * Fix MSWIN compile error (#2681). [Unai Martinez-Corral] * Fix break under foreach loop (#3230). * Fix VL_STREAML_FAST_QQI with 64 bit left-hand-side (#3232) (#3235). [Adrien Le Masle] * Fix $sformat of inputs/outputs (#3236). [Adrien Le Masle] * Fix associative array first method as statement (#3228). [Adrien Le Masle] * Fix associative array foreach loop (#3229). * Fix $fclose not accepting expressions (#3237). [Julie Schwartz] * Fix $random not updating seed (#3238). [Julie Schwartz] * Fix top level param overwrite when package has same param (#3241) (#3247). [Adrien Le Masle] * Fix spurious UNUSED by ignoring inout pin connections (#3242). [Julie Schwartz] * Fix splitting of _eval and other top level functions. [Geza Lore, Shunyao CAD] * Fix internal error by inout port (#3258). [Yutetsu TAKATSUKASA] * Fix GCC 11 compile error (#3273). [HungMingWu] Verilator 4.216 2021-12-05 ========================== **Major:** * Add --lib-create, similar to --protect-lib but without protections. * Support tracing through --hierarchical/--lib-create libraries (#3200). **Minor:** * Internal code cleanups and improvements. [Geza Lore] * Improve --thread Verilation-time performance. * Support task name in $display %m (#3211). [Julie Schwartz] * Make 'bit', 'logic' and 'time' types unsigned by default. [Geza Lore] * Optimize $random concatenates/selects (#3114). * Fix array method names with parenthesis (#3181) (#3183). [Teng Huang] * Fix split_var assign merging (#3177) (#3179). [Yutetsu TAKATSUKASA] * Fix wrong bit op tree optimization (#3185). [Yutetsu TAKATSUKASA] * Fix some SliceSels not being constants (#3186) (#3218). [Michaël Lefebvre] * Fix nested generate if genblk naming (#3189). [yanx21] * Fix hang on recursive definition error (#3199). [Jonathan Kimmitt] * Fix display of signed without format (#3204). [Julie Schwartz] * Fix display of empty string constant (#3207) (#3215). [Julie Schwartz] * Fix incorrect width after and-or optimization (#3208). [Julie Schwartz] * Fix $fopen etc on integer arrays (#3214). [adrienlemasle] * Fix $size on dynamic strings (#3216). * Fix %0 format on $value$plusargs (#3217). * Fix timescale portability on Arm64 (#3222). Verilator 4.214 2021-10-17 ========================== **Major:** * Add profile-guided optimization of mtasks (#3150). **Minor:** * Verilator_gantt has removed the ASCII graphics, use the VCD output instead. * Verilator_gantt now shows the predicted mtask times, eval times, and additional statistics. * Verilator_gantt data files now include processor information, to allow later processing. * Support displaying x and z in $display task (#3107) (#3109). [Iru Cai] * Fix verilator_profcfunc profile accounting (#3115). * Fix display has no time units on class function (#3116). [Damien Pretet] * Fix removing if statement with side effect in condition (#3131). [Alexander Grobman] * Fix --waiver-output for multiline warnings (#2429) (#3141). [Keith Colbert] * Fix internal error on bad widths (#3140) (#3145). [Zhanglei Wang] * Fix crash on clang 12/13 (#3148). [Kuoping Hsu] * Fix cygwin compile error due to missing -std=gnu++14 (#3149). [Sun Kim] * Fix $urandom_range when the range is 0 ... UINT_MAX (#3161). [Iru Cai] * Fix constructor-parameter argument comma-separation in C++ (#3162). [Matthew Ballance] * Fix missing install of vl_file_copy/vl_hier_graph (#3165). [Popolon] * Fix calling new with arguments in same class (#3166). [Matthew Ballance] * Fix false EOFNEWLINE warning when DOS carriage returns present (#3171). Verilator 4.212 2021-09-01 ========================== **Minor:** * Fix re-evaluation of logic dependent on state set in DPI exports (#3091). [Geza Lore] * Support unpacked array localparams in tasks/functions (#3078). [Geza Lore] * Support timeunit/timeprecision in $unit. * Support assignment patterns as children of pins (#3041). [Krzysztof Bieganski, Antmicro Ltd] * Add --instr-count-dpi to tune assumed DPI import cost for multithreaded model scheduling. Default value changed to 200 (#3068). [Yinan Xu] * Output files are split based on the set of headers required in order to aid incremental compilation via ccache (#3071). [Geza Lore] * Parameter values are now emitted as 'static constexpr' instead of enum. C++ direct references to parameters might require updating (#3077). [Geza Lore] * Refactored Verilated include files; include verilated.h not verilated_heavy.h. * Add header guards on Dpi.h generated files (#2979). [Tood Strader] * Add XML ccall, constpool, initarray, and if/while begins (#3080). [Steven Hugg] * Add error when constant function under a generate (#3103). [Don Owen] * Fix -G to treat simple integer literals as signed (#3060). [Anikin1610] * Fix emitted string array initializers (#2895). [Iztok Jeras] * Fix bitop tree optimization dropping necessary & operator (#3096). [Flavien Solt] * Fix internal error on wide -x-initial unique (#3106). [Alexandre Joannou] * Fix traces to show array instances with brackets (#3092) (#3095). [Pieter Kapsenberg] Verilator 4.210 2021-07-07 ========================== **Major:** * Generated code is now emitted as global functions rather than methods. '$c' contents might need to be updated, see the docs (#3006). [Geza Lore] * The generated model class instantiated by the user is now an interface object and no longer the TOP module instance. User code with direct C++ member access to model internals, including verilator public_flat items will likely need to be updated. See the manual for instructions: https://verilator.org/guide/latest/connecting.html#porting-from-pre-4-210 (#3036). [Geza Lore] **Minor:** * Add --prof-c to pass profiling to compiler (#3059). [Alexander Grobman] * Optimize a lot more model variables into function locals (#3027). [Geza Lore] * Support middle-of-design nested top modules (#3026). [Dan Petrisko] * Remove deprecated --no-relative-cfuncs option (#3024). [Geza Lore] * Remove deprecated --inhibit-sim option (#3035). [Geza Lore] * Merge const static data globally into a new constant pool (#3013). [Geza Lore] * Allow configure override of AR program (#2999). [ahouska] * In XML, show pinIndex information (#2877). [errae233] * Fix error on unsupported recursive functions (#2957). [Trefor Southwell] * Fix type parameter specialization when struct names are same (#3055). [7FM] * Improve speed of table optimization (-OA) pass. [Geza Lore] Verilator 4.204 2021-06-12 ========================== **Minor:** * Add 'make ccache-report' (#3011). [Geza Lore] * Add --reloop-limit argument (#2943) (#2960). [Geza Lore] * Add --expand-limit argument (#3005). [Julien Margetts] * Add TRACE_THREADS to CMake (#2934). [Jonathan Drolet] * Optimize large lookup tables to static data (#2925). [Geza Lore] * Optimize reloop to accept constant index offsets (#2939). [Geza Lore] * Split always blocks to better respect --output-split-cfuncs. [Geza Lore] * Support ignoring "`pragma protect ..." (#2886). [Udi Finkelstein] * Support --trace-fst for SystemC with CMake (#2927). [Jonathan Drolet] * Update cmake latest C++ Standard Compilation flag (#2951). [Ameya Vikram Singh] * Prep work towards better ccache hashing/performance. [Geza Lore] * Fix assertion failure in bitOpTree optimization (#2891) (#2899). [Raynard Qiao] * Fix DPI functions not seen as vpiModule (#2893). [Todd Strader] * Fix bounds check in VL_SEL_IWII (#2910). [Krzysztof Bieganski, Antmicro Ltd] * Fix slowdown in elaboration (#2911). [Nathan Graybeal] * Fix initialization of assoc in assoc array (#2914). [myftptoyman] * Fix make support for gmake 3.x (#2920) (#2921). [Philipp Wagner] * Fix VPI memory access for packed arrays (#2922). [Todd Strader] * Fix MCD close also closing stdout (#2931). [Alexander Grobman] * Fix split procedures to better respect --output-split-cfuncs (#2942). [Geza Lore] * Fix to emit 'else if' without nesting (#2944). [Geza Lore] * Fix part select issues in LATCH warning (#2948) (#2938). [Julien Margetts] * Fix to not emit empty files with low split limits (#2961). [Geza Lore] * Fix merging of assignments in C++ code (#2970). [Rupert Swarbrick] * Fix unused variable warnings (#2991). [Pieter Kapsenberg] * Fix --protect-ids when using SV classes (#2994). [Geza Lore] * Fix constant function calls with uninitialized value (#2995). [yanx21] * Fix Makefiles to support Windows EXEEXT usage (#3008). [Miodrag Milanovic] Verilator 4.202 2021-04-24 ========================== **Major:** * Documentation has been rewritten into a book format. * Verilated signals now use VlWide and VlPacked in place of C arrays. **Minor:** * Add an URL on warnings to point to the manual's description. * Add EOFNEWLINE warning when missing a newline at EOF. * Changed TIMESCALEMOD from error into a warning. * Mark --no-relative-cfuncs as scheduled for deprecation. * Add --coverage-max-width (#2853). [xuejiazidi] * Add VerilatedCovContext::forcePerInstance (#2793). [Kevin Laeufer] * Add FST SystemC tracing (#2806). [Àlex Torregrosa] * Add PINNOTFOUND warning in place of error (#2868). [Udi Finkelstein] * Support overlaps in priority case statements (#2864). [Rupert Swarbrick] * Support for null ports (#2875). [Udi Finkelstein] * Fix class unpacked-array compile error (#2774). [Iru Cai] * Fix scope types in FST and VCD traces (#2805). [Àlex Torregrosa] * Fix exceeding command-line ar limit (#2834). [Yinan Xu] * Fix false $dumpfile warning on model save (#2834). [Yinan Xu] * Fix --timescale-override not suppressing TIMESCALEMOD (#2838). [Kaleb Barrett] * Fix false TIMESCALEMOD on generate-ignored instances (#2838). [Kaleb Barrett] * Fix --output-split with class extends (#2839). [Iru Cai] * Fix false WIDTHCONCAT on casted constant (#2849). [Rupert Swarbrick] * Fix tracing of long hashed names (#2854). [Graham Rushton] * Fix --public-flat-rw / DPI issue (#2858). [Todd Strader] * Fix interface localparam access (#2859). [Todd Strader] * Fix Cygwin example compile issues (#2856). [Mark Shaw] * Fix select of with index variable (#2880). [Alexander Grobman] * Fix cmake version number to be numeric (#2881). [Yuri Victorovich] * Fix MinGW not supporting 'localtime_r' (#2882). [HyungKi Jeong] * Fix cast from packed, typedef'ed interface signal (#2884). [Todd Strader] * Fix VPI package reported as vpiModule (#2885). [Todd Strader] * Fix dumping waveforms to multiple FST files (#2889). [David Metz] * Fix assertion failure in bitOpTree (#2892). [Yutetsu TAKATSUKASA] * Fix V3Premit infinite loop on always read-and-write (#2898). [Raynard Qiao] * Fix VPI packed vectors (#2900). [Todd Strader] * Fix VPI public interface parameters (#2901). [Todd Strader] Verilator 4.200 2021-03-12 ========================== **Announcement:** * --inhibit-sim is planned for deprecation, file a bug if this is still being used. **Major:** * Add simulation context (VerilatedContext) to allow multiple fully independent models to be in the same process. Please see the updated examples (#2660). * Add context->time() and context->timeInc() API calls, to set simulation time. These now are recommended in place of the legacy sc_time_stamp(). **Minor:** * Converted Asciidoc documentation into reStructuredText (RST) format. * Fix range inheritance on port without data type (#2753). [Embedded Go] * Fix slice-assign overflow (#2803) (#2811). [David Turner] * Fix interface array connection ordering broken in v4.110 (#2827). [Don Owen] * Fix or-reduction on different scopes broken in 4.110 (#2828). [Yinan Xu] * Fix MSVC++ compile error (#2831) (#2833). [Drew Taussig] Verilator 4.110 2021-02-25 ========================== **Major:** * Optimize bit operations and others (#2186) (#2632) (#2633) (#2751) (#2800) [Yutetsu TAKATSUKASA] **Minor:** * Support concat selection (#2721). * Support struct scopes when dumping structs to VCD (#2776) [Àlex Torregrosa] * Generate SELRANGE for potentially unreachable code (#2625) (#2754) [Pierre-Henri Horrein] * For --flatten, override inlining of public and no_inline modules (#2761) [James Hanlon] * Fix little endian interface pin swizzling (#2475). [Don Owen] * Fix range inheritance on port without data type (#2753). [Embedded Go] * Fix TIMESCALE warnings on primitives (#2763). [Xuanqi] * Fix to exclude strings from toggle coverage (#2766) (#2767) [Paul Wright] * Fix $fread extra semicolon inside statements. [Leendert van Doorn] * Fix class extends with VM_PARALLEL_BUILDS (#2775). [Iru Cai] * Fix shifts by > 32 bit values (#2785). [qrq992] * Fix examples not flushing vcd (#2787). [Richard E George] * Fix little endian packed array pattern assignment (#2795). [Àlex Torregrosa] Verilator 4.108 2021-01-10 ========================== **Major:** * Many VPI changes for IEEE compatibility, which may alter behavior from previous releases. * Support randomize() class method and rand (#2607). [Krzysztof Bieganski, Antmicro Ltd] **Minor:** * Support $cast and new CASTCONST warning. * Add --top option as alias of --top-module. * Add LATCH and NOLATCH warnings (#1609) (#2740). [Julien Margetts] * Remove Unix::Processors internal test dependency. * Report UNUSED on parameters, localparam and genvars (#2627). [Charles Eric LaForest] * Add error on real to non-real output pins (#2690). [Peter Monsson] * Support package imports before parameters in interfaces (#2714). [James Hanlon] * Support --sanitize in internal tests (#2705). [Yutetsu TAKATSUKASA] * Fix passing parameter type instantiations by position number. * Fix DPI open array handling issues. * Fix error when dotted refers to missing module (#2095). [Alexander Grobman] * Fix little endian packed array counting (#2499). [phantom-killua] * Fix showing reference locations for BLKANDNBLK (#2170). [Yuri Victorovich] * Fix genblk naming to match IEEE (#2686). [tinshark] * Fix VPI memory word indexing (#2695). [Marlon James] * Fix vpiLeftRange on little-endian memories (#2696). [Marlon James] * Fix VPI module tree (#2704). [Todd Strader] * Fix vpi_release_handle to be called implicitly per IEEE (#2706). * Fix to allow inheriting 'VerilatedVcdFile' class (#2720). [HyungKi Jeong] * Fix $urandom_range maximum value (#2723). [Nandu Raj] * Fix tracing empty sc module (#2729). * Fix generate for unrolling to be signed (#2730). [yanx21] * Fix to emit timescale in hierarchical blocks (#2735). [Yutetsu TAKATSUKASA] * Fix to ignore coverage on real ports (#2741) (#2745). [Paul Wright] Verilator 4.106 2020-12-02 ========================== **Major:** * Change -sv option to select 1800-2017 instead of 1800-2005. **Minor:** * Check for proper 'local' and 'protected' (#2228). * Support $random and $urandom seeds. * Support $monitor and $strobe. * Support complex function arguments. * Support 'super'. * Support 'with item.index'. * Fix the default GNU Make executable name on FreeBSD (#2553). [Yuri Victorovich] * Fix trace signal names getting hashed (#2643). [Barbara Gigerl] * Fix unpacked array parameters near functions (#2639). [Anderson Ignacio da Silva] * Fix access to non-overridden base class variable (#2654). [Tobias Rosenkranz] Verilator 4.104 2020-11-14 ========================== **Minor:** * Support queue and associative array 'with' statements (#2616). * Support queue slicing (#2326). * Support associative array pattern assignments and defaults. * Support static methods and typedefs in classes (#2615). [Krzysztof Bieganski, Antmicro Ltd] * Add error on typedef referencing self (#2539). [Cody Piersall] * With --debug, turn off address space layout randomization. * Fix iteration over mutating list bug in VPI (#2588). [Kaleb Barrett] * Fix cast width propagation (#2597). [flex-liu] * Fix return from callValueCbs (#2589) (#2605). [Marlon James] * Fix WIDTH warnings on comparisons with nullptr (#2602). [Rupert Swarbrick] * Fix fault when $fgets, $sscanf, etc used with string (#2604). [Yutetsu TAKATSUKASA] * Fix WIFEXITED missing from MinGW/MSYS2 (#2609). [Jean Berniolles] * Fix queue poping wrong value when otherwise unused (#2512). [nanduraj1] * Fix arrays of modport interfaces (#2614). [Thierry Tambe] * Fix split_var internal error (#2640) (#2641). [Yutetsu TAKATSUKASA] Verilator 4.102 2020-10-15 ========================== **Minor:** * Support const object new() assignments. * Support # as a comment in -f files (#2497). [phantom-killua] * Support 'this' (#2585). [Rafal Kapuscik] * Support defines for FST tracing (#2592). [Markus Krause] * Support non-overlapping implication inside properties (#1292). [Peter Monsson] * Fix timescale with --hierarchical (#2554). [Yutetsu TAKATSUKASA] * Fix cmake build with --hierarchical (#2560). [Yutetsu TAKATSUKASA] * Fix -G dropping public indication (#2561). [Andrew Goessling] * Fix $urandom_range passed variable (#2563). [nanduraj1] * Fix method calls to package class functions (#2565). [Peter Monsson] * Fix class wide member display (#2567). [Nandu Raj P] * Fix hierarchical references inside function (#2267) (#2572). [James Pallister] * Fix flushCall for backward compatibility (#2580). [chenguokai] * Fix preprocessor stringify of undefined macro. [Martin Whitaker] Verilator 4.100 2020-09-07 ========================== **Major:** * C++11 or newer compilers are now required. * SystemC 2.3.0 or newer (SYSTEMC_VERSION >= 20111121) is now required. * Support hierarchical Verilation (#2206). [Yutetsu TAKATSUKASA] **Minor:** * Support (with limitations) class extern, class extends, virtual class. * Support $urandom, $urandom_range without stability. * Support assume property. [Peter Monsson] * Support non-overlapping implication inside properties (#1292). [Peter Monsson] * Fix false DECLFILENAME on black-boxed modules (#2430). [Philipp Wagner] * Fix naming of "id : begin" blocks. * Fix class constructor error on assignments to const. * Fix splitting eval functions with --output-split-cfuncs (#2368). [Geza Lore] * Fix queues as class members (#2525). [nanduraj1] Verilator 4.040 2020-08-15 ========================== **Announcement:** * Version 4.040 is planned to be the final version that will support pre-C++11 compilers. Please move to C++11 or newer compilers. **Minor:** * Fix arrayed interfaces, broke in 4.038 (#2468). [Josh Redford] * Support $stable, $rose and $fell (#2148) (#2501). [Peter Monsson] * Support simple function localparams (#2461). [James Hanlon] * Miscellaneous parsing error changes towards UVM support. * Fix arrayed interfaces (#2469). [Josh Redford] * Fix protect lib VCS warning (#2479). [Julien Margetts] * Fix combining different-width parameters (#2484). [abirkmanis] * Fix protect-lib without sequential logic (#2492). [Yutetsu TAKATSUKASA] * Fix V3Unknown from running with flat XML output (#2494). [James Hanlon] * Fix non-32 bit conversion to float (#2495). [dsvf] * Fix casting non-self-determined subexpressions (#2493). [phantom-killua] * Fix SystemC net names (#2500). [Edgar E. Iglesias] * Fix build with Bison 3.7 and newer (#2505). [Rupert Swarbrick] * Fix slice of unpacked array (#2506) (#2507). [Yutetsu TAKATSUKASA] Verilator 4.038 2020-07-11 ========================== **Announcement:** * Versions 4.038 and 4.040 are planned to be the final versions that will support pre-C++11 compilers. Please move to C++11 or newer compilers. **Minor:** * Support VPI access to parameters and localparam. [Ludwig Rogiers] * Support parsing (not elaboration, yet) of UVM. * Add new UNSUPPORTED error code to replace most previous Unsupported: messages. * With --bbox-unsup continue parsing on many (not all) UVM constructs. * Support for-loop increments with commas. * Support $swrite with arbitrary arguments. * Support $writememb (#2450). [Fan Shupei] * Fix OS X, Free BSD, and -m32 portability issues. [Geza Lore] * Fix to flush FST trace on termination due to $stop or assertion failure. * Fix part select error when multipling by power-of-two (#2413). [Conor McCullough] * Fix division exception (#2460) [Kuoping Hsu] Verilator 4.036 2020-06-06 ========================== **Major:** * OPT_FAST is now -Os by default. See the BENCHMARKING & OPTIMIZATION part of the manual if you experience issues with compilation speed. * --output-split is now on by default. VM_PARALLEL_BUILDS is set by default iff the --output-split caused an actual file split to occur. --output-split-cfuncs and --output-split-ctrace now default to the value of --output-split. These changes should improve build times of medium and large designs with default options. User makefiles may require changes. **Minor:** * Configure now enables SystemC if it is installed as a system headers, e.g. with 'apt-get install systemc-dev'. * Add --waiver-output flag that writes a verilator config file (.vlt) with waivers to the warnings emitted during a Verilator run. * Support verilator_coverage --write-info for lcov HTML reports. * Line Coverage now tracks all statement lines, not just branch lines. * The run-time library is now compiled with -Os by default (#2369, #2373). * Support multi channel descriptor I/O (#2190) [Stephen Henry] * Support $countbits (#2287). [Yossi Nivin] * Support $isunbounded and parameter $ (#2104). * Support unpacked array .sum and .product. * Support prefix/postfix increment/decrement (#2223). [Maciej Sobkowski] * Fix FST tracing of little bit endian signals. [Geza Lore] * Fix +: and -: on unpacked arrays (#2304). [engr248] * Fix $isunknown with constant Z's. * Fix queues and dynamic array wide ops (#2352). [Vassilis Papaefstathiou] Verilator 4.034 2020-05-03 ========================== **Major:** * Support simplistic classes with many restrictions, see manual. (#377) * Support IEEE time units and time precisions. (#234) Includes `timescale, $printtimescale, $timeformat. VL_TIME_MULTIPLIER, VL_TIME_PRECISION, VL_TIME_UNIT have been removed and the time precision must now match the SystemC time precision. To get closer behavior to older versions, use e.g. --timescale-override "1ps/1ps". * Add --build to call make automatically. (#2249) [Yutetsu TAKATSUKASA] * Configuring with ccache present now defaults to using it; see OBJCACHE. * Fix DPI import/export to be standard compliant. (#2236) [Geza Lore] * Add --trace-threads for general multithreaded tracing. (#2269) [Geza Lore] **Minor:** * Add --flatten for use with --xml-only. (#2270) [James Hanlon] * Greatly improve FST/VCD dump performance (#2244) (#2246) (#2250) (#2257) [Geza Lore] * Support $ferror, and $fflush without arguments. (#1638) * Support event data type (with some restrictions). * Support $root. (#2150) [Keyi Zhang] * Add error if use SystemC 2.2 and earlier (pre-2011) as is deprecated. * Add support of --trace-structs for CMake (#2986). [Martin Schmidt] * Fix arrayed instances connecting to slices. (#2263) [Don/engr248] * Fix error on unpacked connecting to packed. (#2288) [Joseph Shaker] * Fix logical not optimization with empty begin. (#2291) [Baltazar Ortiz] * Fix reduction OR on wide data, broke in v4.026. (#2300) [Jack Koenig] * Fix clock enables with bit-extends. (#2299) [Marco Widmer] * Fix MacOs Homebrew by removing default LIBS. (#2298) [Ryan Clarke] Verilator 4.032 2020-04-04 ========================== **Minor:** * Add column numbers to errors and warnings. * Add GCC 9-style line number prefix when showing source text for errors. * Add setting VM_PARALLEL_BUILDS=1 when using --output-split. (#2185) * Change --quiet-exit to also suppress 'Exiting due to N errors'. * Suppress REALCVT for whole real numbers. * Support split_var in vlt files. (#2219) [Marco Widmer] * Fix parameter type redeclaring a type. (#2195) [hdzhangdoc] * Fix VCD open with empty filename. (#2198) [Julius Baxter] * Fix packages as enum base types. (#2202) [Driss Hafdi] * Fix duplicate typedefs in generate for. (#2205) [hdzhangdoc] * Fix MinW portability. (#2114) [Sean Cross] * Fix assertions with unique case inside. (#2199) [hdzhangdoc] * Fix implicit conversion of floats to wide integers. Verilator 4.030 2020-03-08 ========================== **Major:** * Add split_var metacomment to assist UNOPTFLAT fixes. (#2066) [Yutetsu TAKATSUKASA] * Support $dumpfile and $dumpvars. (#2126) [Alexander Grobman] * Support dynamic arrays. (#379) **Minor:** * Add +verilator+noassert flag to disable assertion checking. [Tobias Wölfel] * Add check for assertOn for asserts. (#2162) [Tobias Wölfel] * Add --structs-packed for forward compatibility. * Support $displayb/o/h, $writeb/o/h, etc. (#1637) * Use gcc -Os in examples instead of -O2 for better average performance. * Fix genblk naming with directly nested generate blocks. (#2176) [Alexander Grobman] * Fix undeclared VL_SHIFTR_WWQ. (#2114) [Alex Solomatnikov] Verilator 4.028 2020-02-08 ========================== **Major:** * Support attributes (public, isolate_assignments, etc.) in configuration files. * Add -match to lint_off to waive warnings. [Philipp Wagner] **Minor:** * Link Verilator binary partially statically. (#2146) [Geza Lore] * Verilation speed improvements (#2133) (#2138) [Geza Lore] * Support libgoogle-perftools-dev's libtcmalloc if available. (#2137) [Geza Lore] * Support $readmem/$writemem with assoc arrarys. (#2100) [agrobman] * Support type(expression) operator and $typename. (#1650) * Support left justified $display. (#2101) [Pieter Kapsenberg] * Support string character access via indexing. * Support enum.next(k) with constant k > 1. (#2125) [Tobias Rosenkranz] * Support parameter access from arrays of interfaces. (#2155) [Todd Strader] * Add parameter values in XML. #2110. [Pieter Kapsenberg] * Add loc column location in XML (replaces fl). (#2122) [Pieter Kapsenberg] * Add error on misused define. [Topa Tota] * Add parameter to set maximum signal width. (#2082) [Øyvind Harboe] * Add warning on genvar in normal for loop. (#2143) [Yuri Victorovich] * Fix VPI scope naming for public modules. [Nandu Raj] * Fix FST tracing of enums inside structs. [fsiegle] * Fix WIDTH warning on . * Support VerilatedFstC set_time_unit. (#1433) [Pieter Kapsenberg] * Support deferred assertions. (#1449) [Charles Eddleston] * Mark infrequently called functions with GCC cold attribute. * Fix sign-compare warning in verilated.cpp. (#1437) [Sergey Kvachonok] * Fix fault on $realtime with %t. (#1443) [Julien Margetts] * Fix $display with string without %s. (#1441) [Denis Rystsov] * Fix parameter function string returns. (#1441) [Denis Rystsov] * Fix invalid XML output due to special chars. (#1444) [Kanad Kanhere] * Fix performance when mulithreaded on 1 CPU. (#1455) [Stefan Wallentowitz] * Fix type and real parameter issues (#1427) (#1456) (#1458) [Todd Strader] * Fix build error on MinGW. (#1460) [Richard Myers] * Fix not reporting some duplicate signals. (#1462) [Peter Gerst] * Fix --savable invalid C++ on packed arrays. (#1465) [Alex Chadwick] * Fix constant function return of function var. (#1467) [Roman Popov] Verilator 4.014 2019-05-08 ========================== **Minor:** * Add --trace-fst-thread. * Support '#' comments in $readmem. (#1411) [Frédéric Requin] * Support "'dx" constants. (#1423) [Udi Finkelstein] * For FST tracing use LZ4 compression. [Tony Bybell] * Add error when use parameters without value. (#1424) [Peter Gerst] * Auto-extend and WIDTH warn on unsized X/Zs. (#1423) [Udi Finkelstein] * Fix missing VL_SHIFTL errors. (#1412) (#1415) [Larry Lee] * Fix MinGW GCC 6 printf formats. (#1413) [Sergey Kvachonok] * Fix test problems when missing fst2vcd. (#1417) [Todd Strader] * Fix GTKWave register warning. (#1421) [Pieter Kapsenberg] * Fix FST enums not displaying. (#1426) [Danilo Ramos] * Fix table compile error with multiinterfaces. (#1431) [Bogdan Vukobratovic] Verilator 4.012 2019-03-23 ========================== **Minor:** * Add +verilator+seed. (#1396) [Stan Sokorac] * Support $fread. [Leendert van Doorn] * Support void' cast on functions called as tasks. (#1383) [Al Grant] * Add IGNOREDRETURN warning. (#1383) * Report PORTSHORT errors on concat constants. (#1400) [Will Korteland] * Fix VERILATOR_GDB being ignored. (#2017) [Yu Sheng Lin] * Fix $value$plus$args missing verilated_heavy.h. [Yi-Chung Chen] * Fix MSVC compile error. (#1406) [Benjamin Gartner] * Fix maintainer test when no Parallel::Forker. (#1977) [Enzo Chi] * Fix +1364-1995ext flags applying too late. (#1384) [Al Grant] Verilator 4.010 2019-01-27 ========================== **Minor:** * Removed --trace-lxt2, use --trace-fst instead. * For --xml, add additional information. (#1372) [Jonathan Kimmitt] * Add circular typedef error. (#1388) [Al Grant] * Add unsupported for loops error. (#1986) [Yu Sheng Lin] * Fix FST tracing of wide arrays. (#1376) [Aleksander Osman] * Fix error when pattern assignment has too few elements. (#1378) [Viktor Tomov] * Fix error when no modules in $unit. (#1381) [Al Grant] * Fix missing too many digits warning. (#1380) [Jonathan Kimmitt] * Fix uninitialized data in verFiles and unroller. (#1385) (#1386) [Al Grant] * Fix internal error on xrefs into unrolled functions. (#1387) [Al Grant] * Fix DPI export void compiler error. (#1391) [Stan Sokorac] Verilator 4.008 2018-12-01 ========================== **Minor:** * Support "ref" and "const ref" pins and functions. (#1360) [Jake Longo] * In --xml-only show the original unmodified names, and add module_files and cells similar to Verilog-Perl, msg2719. [Kanad Kanhere] * Add CONTASSREG error on continuous assignments to regs. (#1369) [Peter Gerst] * Add PROCASSWIRE error on behavioral assignments to wires, msg2737. [Neil Turton] * Add IMPORTSTAR warning on import::* inside $unit scope. * Fix --trace-lxt2 compile error on MinGW. (#1990) [HyungKi Jeong] * Fix hang on bad pattern keys. (#1364) [Matt Myers] * Fix crash due to cygwin bug in getline. (#1349) [Affe Mao] * Fix __Slow files getting compiled with OPT_FAST. (#1370) [Thomas Watts] Verilator 4.006 2018-10-27 ========================== **Minor:** * Add --pp-comments. (#1988) [Robert Henry] * Add --dump-defines. * For --trace-fst, save enum decoding information. (#1358) [Sergi Granell] (To visualize enumeration data you must use GTKwave 3.3.95 or newer.) * For --trace-fst, combine hier information into FST. [Tony Bybell] * Fix --trace-lxt2 compile error on MinGW, msg2667. [HyungKi Jeong] * Fix Windows .exe not found. (#1361) [Patrick Stewart] Verilator 4.004 2018-10-06 ========================== **Major:** * Add GTKWave FST native tracing. (#1356) [Sergi Granell] (Verilator developers need to pull the latest vcddiff.) **Minor:** * Support $past. [Dan Gisselquist] * Support restrict. (#1350) [Clifford Wolf] * Rename include/lxt2 to include/gtkwave. * Fix replication of 64-bit signal change detects. * Fix Mac OSX 10.13.6 / LLVM 9.1 compile issues. (#1348) [Kevin Kiningham] * Fix MinGW compile issues. (#1979) [HyungKi Jeong] Verilator 4.002 2018-09-16 ========================== **Major:** * This is a major release. Any patches may require major rework to apply. [Thanks everyone] * Add multithreaded model generation. * Add runtime arguments. * Add GTKWave LXT2 native tracing. (#1333) [Yu Sheng Lin] * Note $random has new algorithm; results may vary vs. previous versions. **Minor:** * Better optimize large always block splitting. (#1244) [John Coiner] * Add new reloop optimization for repetitive assignment compression. * Support string.atoi and similar methods. (#1289) [Joel Holdsworth] * Fix internals to be C++ null-pointer-check clean. * Fix internals to avoid 'using namespace std'. * Fix Verilation performance issues. (#1316) [John Coiner] * Fix clocker attributes to not propagate on concats. [John Coiner] * Fix first clock edge and --x-initial-edge. (#1327) [Rupert Swarbrick] * Fix compile error on tracing of string arrays. (#1338) [Iztok Jeras] * Fix number parsing with newline after radix. (#1340) [George Cuan] * Fix string ?: conditional type resolution. (#1345) [Iztok Jeras] * Fix duplicate symbol error on generate tri. (#1347) [Tomas Dzetkulic] Verilator 3.926 2018-08-22 ========================== **Minor:** * Add OBJCACHE envvar support to examples and generated Makefiles. * Change MODDUP errors to warnings. (#1969) [Marshal Qiao] * Fix define argument stringification (`"), broke since 3.914. [Joe DErrico] * Fix to ignore Unicode UTF-8 BOM sequences. (#1967) [HyungKi Jeong] * Fix std:: build error. (#1322) * Fix function inlining inside certain while loops. (#1330) [Julien Margetts] Verilator 3.924 2018-06-12 ========================== **Minor:** * Renamed --profile-cfuncs to --prof-cfuncs. * Report interface ports connected to wrong interface. (#1294) [Todd Strader] * When tracing, use scalars on single bit arrays to appease vcddiff. * Fix parsing "output signed" in V2K port list, msg2540. [James Jung] * Fix parsing error on bad missing #. (#1308) [Dan Kirkham] * Fix $clog2 to be in verilog 2005. (#1319) [James Hutchinson] Verilator 3.922 2018-03-17 ========================== **Major:** * Support IEEE 1800-2017 as default language. **Minor:** * Support trig functions ($sin() etc). (#1281) [Patrick Stewart] * Support calling system functions as tasks. (#1285) [Joel Holdsworth] * Support assert properties. (#785) (#1290) [John Coiner, et al] * Support $writememh. [John Coiner] * Add --no-debug-leak to reduce memory use under debug. [John Coiner] * Fix severe runtime performance bug in certain foreach loops. [John Coiner] * On convergence errors, show activity. [John Coiner] * Fix GCC 8.0 issues. (#1273) * Fix pullup/pulldowns on bit selects. (#1274) [Rob Stoddard] * Fix verilator_coverage --annotate-min. (#1284) [Tymoteusz Blazejczyk] * Fix quoting of quoted arguments. [John Coiner] Verilator 3.920 2018-02-01 ========================== **Announcement:** * Moving forward, use the git "stable" branch to track the latest release, and git "v#.###" tags for specific releases. **Minor:** * Support 'assume' similar to 'assert'. (#1269) [Dan Gisselquist] * Remove c++filt. (#1265) [Stefan Wallentowitz] * Fix tracing example file output. (#1268) [Enzo Chi] * Fix gate optimization out of memory, add --gate-stmts. (#1260) [Alex Solomatnikov] * Fix compile error on public real parameters by suppressing. (#1261) [Alex Solomatnikov] * Fix input-only tristate comparisons. (#1267) [Alexis G] * Fix missing edge type in xml output. (#1955) [Alexis G] * Fix compile error with --public and interface bind. (#1264) [Alexis G] Verilator 3.918 2018-01-02 ========================== **Minor:** * Workaround GCC/clang bug with huge compile times. (#1248) * Support DPI open arrays. (#909) (#1245) [David Pierce, Victor Besyakov] * Add INFINITELOOP warning. (#1254) [Alex Solomatnikov] * Support > 64 bit decimal $display. * Support DPI time and svLogicVal. [Victor Besyakov] Note older version incorrectly assumed svBitVal even for logicals. * Support string len() method. [Victor Besyakov] * Add error if always_comb has sensitivity list. [Arjen Roodselaar] * Fix SystemC 2.3.2 compile error. (#1251) [Tymoteusz Blazejczyk] * Fix modport outputs being treated as inputs. (#1246) [Jeff Bush] * Fix false ALWCOMBORDER on interface references. (#1247) [Josh Redford] * Fix constant propagation across DPI imports of inout strings. [Victor Besyakov] * Fix resolving inline nested interface names. (#1250) [Arjen Roodselaar] * Fix GCC false warning on array bounds. (#2386) Verilator 3.916 2017-11-25 ========================== **Minor:** * Support self-recursive modules. (#659) [Sean Moore, et al] * Support $error/$warning in elaboration time blocks. * Support $size/$bits/etc on type references. * Add error when driving input-only modport. (#1110) [Trevor Elbourne] * Add BSSPACE and COLONPLUS lint warnings. * Detect MSB overflow when under VL_DEBUG. (#1238) [Junyi Xi] * Add data types to --xml. [Rui Terra] * Fix partial slicing with pattern assignments. (#991) [Johan Bjork] * Fix false unused warning on interfaces. (#1241) [Laurens van Dam] * Fix error on "unique case" with no cases. * Fix MacOS portability. (#1232) [Jeff Bush] Verilator 3.914 2017-10-14 ========================== **Major:** * Add new examples/ directory with appropriate examples. This replaces the old test_c and test_sc directories. **Minor:** * Add --getenv option for simplifying Makefiles. * Add --x-initial option for specifying initial value assignment behavior. * Add --no-relative-cfuncs and related default optimization. (#1224) [John Coiner] * Add /*verilator tag*/ for XML extraction applications. [Chris Randall] * The internal test_verilated test directory is moved to be part of test_regress. * The experimental VL_THREADED setting (only, not normal mode) now requires C++11. * Fix over-aggressive inlining. (#1223) [John Coiner] * Fix Ubuntu 17.10 issues. (#1223 partial). [John Coiner] * Fix compiler warning when WIDTH warning ignored on large compare. * Fix memory leak in VerilatedVcd dumps. (#1222 partial) [Shareef Jalloq] * Fix unnecessary Vdly variables. (#1224 partial) [John Coiner] * Fix conditional slices and add related optimizations. * Fix \`\` expansion of `defines. (#1225) (#1227) (#1228) [Odd Magne Reitan] * Fix -E duplicating output. (#1226) [Odd Magne Reitan] * Fix float-conversion warning. (#1229) [Robert Henry] * Fix MacOS portability. (#1230) (#1231) [Jeff Bush] Verilator 3.912 2017-09-23 ========================== **Major:** * Verilated headers no longer "use namespace std;" User's code without "std::" prefixes may need "use namespace std;" to compile. **Minor:** * Support or/and/xor array intrinsic methods. (#1210) [Michael Popoloski] * Support package export. (#1217) [Usuario Eda] * Support module port parameters without defaults. (#1213) [Michael Popoloski] * Add performance information to --stats file. * Simplify VL_CONST_W macro generation for faster compiles. * Optimize improvements for Shift-And, and replication constructs. * Fix ordering of arrayed cell wide connections. (#1202 partial) [Michael Popoloski] * Fix LITENDIAN warning on arrayed cells. (#1202) [Michael Popoloski] * Fix enum ranges without colons. (#1204) [Michael Popoloski] * Fix GCC noreturn compile error. (#1209) [Michael Popoloski] * Fix constant function default parameters. (#1211) [Michael Popoloski] * Fix non-colon array of interface modports. (#1212) [Michael Popoloski] * Fix .name connections on interfaces. (#1214) [Michael Popoloski] * Fix wide array indices causing compile error. Verilator 3.910 2017-09-07 ========================== **Major:** * SystemPerl mode (-sp-deprecated) has been removed. **Minor:** * Update keyword warnings to include C++11 and others. Verilator 3.908 2017-08-28 ========================== **Minor:** * Support x in $readmem. (#1180) [Arthur Kahlich] * Support packed struct DPI imports. (#1190) [Rob Stoddard] * Fix GCC 6 warnings. * Fix compile error on unused VL_VALUEPLUSARGS_IW. (#1181) [Thomas J Whatson] * Fix undefined VL_POW_WWI. [Clifford Wolf] * Fix internal error on unconnected inouts. (#1187) [Rob Stoddard] Verilator 3.906 2017-06-22 ========================== **Minor:** * Support set_time_unit/set_time_precision in C traces. (#1937) * Fix extract of packed array with non-zero LSB. (#1172) [James Pallister] * Fix shifts by more than 32-bit numbers. (#1174) [Clifford Wolf] * Fix power operator on wide constants. (#761) [Clifford Wolf] * Fix .* on interface pins. (#1176) [Maciej Piechotka] Verilator 3.904 2017-05-30 ========================== **Minor:** * Fix non-cutable ordering loops on clock arrays. (#1009) [Todd Strader] * Support ports of array of reals. (#1154) [J Briquet] * Support arrayed parameter overrides. (#1153) [John Stevenson] * Support $value$plusargs with variables. (#1165) [Wesley Terpstra] * Support modport access to un-modport objects. (#1161) [Todd Strader] * Add stack trace when can't optimize function. (#1158) [Todd Strader] * Add warning on mis-sized literal. (#1156) [Todd Strader] * Fix interface functions returning wrong parameters. (#996) [Todd Strader] * Fix non-arrayed cells with interface arrays. (#1153) [John Stevenson] * Fix --assert with complex case statements. (#1164) [Enzo Chi] Verilator 3.902 2017-04-02 ========================== **Major:** * Add -FI option to force includes. (#1916) [Amir Gonnen] * Add --relative-includes. [Rob Stoddard] **Minor:** * Add error on duplicate pattern assignments. (#1145) [Johan Bjork] * Fix error on improperly widthed default function. (#984) [Todd Strader] * Fix 2009 localparam syntax, msg2139. [Galen Seitz] * Fix ugly interface-to-non-interface errors. (#1112) [Johan Bjork] * Fix LDFLAGS and CFLAGS not preserving order. (#1130) [Olof Kindgren] * Fix internal error on initializing parameter array. (#1131) [Jie Xu] * Fix internal error on interface arrays. (#1135) [John Stevenson] * Fix calling sformatf to display, and elab $displays. (#1139) [Johan Bjork] * Fix realpath compile issue on MSVC++. (#1141) [Miodrag Milanovic] * Fix missing error on interface size mismatch. (#1143) [Johan Bjork] * Fix error on parameters with dotted references. (#1146) [Johan Bjork] * Fix wreal not handling continuous assign. (#1150) [J Briquet] * Fix nested structure parameter selects. (#1150) [J Briquet] Verilator 3.900 2017-01-15 ========================== **Major:** * Internal code changes for improved compatibility and performance. **Minor:** * Support old-style $display($time). (#467) [John Demme] * With --bbox-unsup, suppress desassign and mixed edges. (#1120) [Galen Seitz] * Fix parsing sensitivity with &&. (#934) [Luke Yang] * Fix internal error on double-for loop unrolling. (#1044) [Jan Egil Ruud] * Fix internal error on unique casez with --assert. (#1117) [Enzo Chi] * Fix bad code when tracing array of structs. (#1122) [Andrew Bardsley] Verilator 3.890 2016-11-25 ========================== **Minor:** * Honor --output-split on coverage constructors. (#1098) [Johan Bjork] * Fix various issues when making outside of the kit. * Fix flex 2.6.2 bug. (#1103) [Sergey Kvachonok] * Fix error on bad interface name. (#1097) [Todd Strader] * Fix error on referencing variable in parent. (#1099) [Ian Thompson] * Fix type parameters with low optimization. (#1101) [Stefan Wallentowitz] Verilator 3.888 2016-10-14 ========================== **Major:** * Support foreach. (#1078) [Xuan Guo] **Minor:** * Add --no-decoration to remove output comments, msg2015. [Frédéric Requin] * If VM_PARALLEL_BUILDS=1, use OPT_FAST and OPT_SLOW. [Frédéric Requin] Set VM_DEFAULT_RULES=0 for old behavior. * Add error on DPI functions > 32 bits. (#1898) [Elliot Mednick] * Improve Verilation performance on internal strings. (#1896) [Johan Bjork] * Improve Verilation performance on trace duplicates. (#1090) [Johan Bjork] * Fix SystemC compiles with VPI. (#1081) [Arthur Kahlich] * Fix error on wide numbers that represent shifts, msg1991. (#1088) [Mandy Xu] Verilator 3.886 2016-07-30 ========================== **Minor:** * Fix enum values of 11-16 bits wide using .next/.prev. (#1062) [Brian Flachs] * Fix false warnings on non-power-2 enums using .next/.prev. * Fix comparison of unpacked arrays. (#1071) [Andrew Bardsley] * Fix compiler warning in GCC 6. [David Horton] Verilator 3.884 2016-05-18 ========================== **Major:** * Support parameter type. (#376) [Alan Hunter, et al] * Support command-line -G/+pvalue param overrides. (#1045) [Stefan Wallentowitz] * Add --l2-name option for controlling "v" naming. * The default l2 scope name is now the same as the top-level module. (#1050) Use "--l2-name v" for the historical behavior. **Minor:** * Fix --output-split of constructors. (#1035) [Johan Bjork] * Fix removal of empty packages, modules and cells. (#1034) [Johan Bjork] * Fix core dump on Arch Linux/GCC 6.1.1. (#1058) [Jannis Harder] * Fix $value$plusargs to string. (#1880) [Frédéric Requin] Verilator 3.882 2016-03-01 ========================== **Minor:** * Internal Verilation-time performance enhancements. (#1021) [Johan Bjork] * Support inlining interfaces. (#1018) [Johan Bjork] * Support SV strings to readmemh. (#1040) [Stefan Wallentowitz] * Fix unrolling complicated for-loop bounds. (#677) [Johan Bjork] * Fix stats file containing multiple unroll entries. (#1020) [Johan Bjork] * Fix using short parameter names on negative params. (#1022) [Duraid Madina] * Fix read-after-free error. (#1031) [Johan Bjork] * Fix elaboration-time display warnings. (#1032) [Johan Bjork] * Fix crash on very deep function trees. (#1028) [Jonathan Kimmitt] * Fix slicing mix of big and little-endian. (#1033) [Geoff Barrett] * Fix pattern assignment width propagation. (#1037) [Johan Bjork] Verilator 3.880 2015-12-19 ========================== **Minor:** * Support display %u, %v, %p, %z. (#989) [Johan Bjork] * Fix real parameters causing bad module names. (#992) [Johan Bjork] * Fix size-changing cast on packed struct. (#993) [Johan Bjork] * Fix function calls on arrayed interface. (#994) [Johan Bjork] * Fix arrayed interfaces. (#879) (#1001) [Todd Strader] * Fix constant function assigned to packed structs. (#997) [Johan Bjork] * Fix interface inside generate. (#998) [Johan Bjork] * Fix $signed casts under generates. (#999) [Clifford Wolf] * Fix genvar constant propagation. (#1003) [Johan Bjork] * Fix parameter constant propagation from package. (#1004) [Johan Bjork] * Fix array slicing of non-const indexes. (#1006) [Johan Bjork] * Fix dotted generated array error. (#1005) [Jeff Bush, Johan Bjork] * Fix error instead of warning on large concat. (#1865) [Paul Rolfe] * Fix $bitstoreal constant propagation. (#1012) [Jonathan Kimmitt] * Fix model restore crash. (#1013) [Jason McMullan] * Fix arrayed instances to unpacked of same size. (#1015) [Varun Koyyalagunta] * Fix slices of unpacked arrays with non-zero LSBs. * Fix ternary operation with unpacked array. (#1017) [Varun Koyyalagunta]. Verilator 3.878 2015-11-01 ========================== **Major:** * Add --vpi flag, and fix VPI linkage. (#969) [Arthur Kahlich] * Support genvar indexes into arrayed cells. (#517) [Todd Strader] * Support $sformatf. (#977) [Johan Bjork] * Support elaboration assertions. (#973) [Johan Bjork] * Support $display with non-format arguments. (#467) [Jamey Hicks] **Minor:** * Add VerilatedScopeNameMap for introspection. (#966) [Todd Strader] * Ignore %l in $display. (#983) [Todd Strader] * Fix very long module names. (#937) [Todd Strader] * Fix internal error on dotted refs into generates. (#958) [Jie Xu] * Fix structure parameter constant propagation. (#968) [Todd Strader] * Fix enum constant propagation. (#970) [Todd Strader] * Fix mis-optimizing public DPI functions. (#963) [Wei Song] * Fix package:scope.scope variable references. * Fix $fwrite to constant stderr/stdout. (#961) [Wei Song] * Fix struct.enum.name method calls. (#855) [Jonathon Donaldson] * Fix dot indexing into arrayed inferfaces. (#978) [Johan Bjork] * Fix crash in commandArgsPlusMatch. (#987) [Jamie Iles] * Fix error message on missing interface. (#985) [Todd Strader] Verilator 3.876 2015-08-12 ========================== **Minor:** * Add tracing_on, etc to vlt files. (#932) [Frédéric Requin] * Support extraction of enum bits. (#951) [Jonathon Donaldson] * Fix MinGW compiler error. (#927) (#929) [Hans Tichelaar] * Fix .c files to be treated as .cpp. (#930) [Jonathon Donaldson] * Fix string-to-int space conversion. (#931) [Fabrizio Ferrandi] * Fix dpi imports inside generates. [Michael Tresidder] * Fix rounding in trace $timescale. (#946) [Frédéric Requin] * Fix $fopen with SV string. (#947) [Sven Stucki] * Fix hashed error with typedef inside block. (#948) [Sven Stucki] * Fix makefile with --coverage. (#953) [Eivind Liland] * Fix coverage documentation. (#954) [Thomas J Whatson] * Fix parameters with function parameter arguments. (#952) [Jie Xu] * Fix size casts as second argument of cast item. (#950) [Jonathon Donaldson] Verilator 3.874 2015-06-06 ========================== **Minor:** * Add pkg-config .pc file. (#919) [Stefan Wallentowitz] * Fix installing missing manpages. (#908) [Ahmed El-Mahmoudy] * Fix sign extension in large localparams. (#910) [Mike Thyer] * Fix core dump in sync-async warnings. (#911) [Sebastian Dressler] * Fix truncation warning with -pins-bv. (#912) [Alfonso Martinez] * Fix Cygwin uint32 compile. (#914) [Matthew Barr] * Fix preprocessing stringified newline escapes. (#915) [Anton Rapp] * Fix part-select in constant function. (#916) [Andrew Bardsley] * Fix width extension on mis-width ports. (#918) [Patrick Maupin] * Fix width propagation on sized casts. (#925) [Jonathon Donaldson] * Fix MSVC++ compiler error. (#927) [Hans Tichelaar] Verilator 3.872 2015-04-05 ========================== **Minor:** * Add VerilatedVcdFile to allow real-time waveforms. (#890) [HyungKi Jeong] * Add --clk and related optimizations. (#1840) [Jie Xu] * Fix order of C style arrays. [Duraid Madina] * Add --dump-treei-. (#894) [Jie Xu] * Fix comma-instantiations with parameters. (#884) [Franck Jullien] * Fix SystemC arrayed bit vectors. (#886) [David Poole] * Fix compile error on MinGW. (#887) [HyungKi Jeong] Verilator 3.870 2015-02-12 ========================== **Minor:** * Suppress COMBDLY when inside always_latch. (#864) [Iztok Jeras] * Support cast operator with expression size. (#865) [Iztok Jeras] * Add warning on slice selection out of bounds. (#875) [Cong Van Nguyen]. * Fix member select error broke in 3.868. (#867) [Iztok Jeras] * Fix $sccanf from string. (#866) [David Pierce] * Fix VM_PARALLEL_BUILDS broke in 3.868. (#870) [Hiroki Honda] * Fix non-ANSI modport instantiations. (#868) [Kevin Thompson] * Fix UNOPTFLAT change detect on multidim arrays. (#872) [Andrew Bardsley] * Fix slice connections of arrays to ports. (#880) [Varun Koyyalagunta] * Fix mis-optimizing gate assignments in unopt blocks. (#881) [Mike Thyer] * Fix sign extension of pattern members. (#882) [Iztok Jeras] * Fix clang compile warnings. Verilator 3.868 2014-12-20 ========================== **Major:** * New verilator_coverage program added to replace SystemPerl's vcoverage. * PSL support was removed, please use System Verilog assertions. * SystemPerl mode is deprecated and now untested. **Minor:** * Support enum.first/name and similar methods. (#460) (#848) * Add 'string' printing and comparisons. (#746) (#747) etc. * Inline C functions that are used only once. (#1838) [Jie Xu] * Fix tracing SystemC signals with structures. (#858) [Eivind Liland] Note that SystemC traces will no longer show the signals in the wrapper, they can be seen one level further down. * Add --stats-vars. (#851) [Jeremy Bennett] * Fix bare generates in interfaces. (#789) [Bob Newgard] * Fix underscores in real literals. (#863) [Jonathon Donaldson] Verilator 3.866 2014-11-15 ========================== **Minor:** * Fix +define+A+B to define A and B to match other simulators. (#847) [Adam Krolnik] * Add optimization of wires from arrayed cells. (#1831) [Jie Xu] * Add optimization of operators between concats. (#1831) [Jie Xu] * Add public enums. (#833) [Jonathon Donaldson] * Trace_off now operates on cells. (#826) [Lane Brooks] * Fix public parameters in unused packages. (#804) [Jonathon Donaldson] * Fix select when partially out-of-bound. (#823) [Clifford Wolf] * Fix generate unrolling with function call. (#830) [Steven Slatter] * Fix cast-to-size context-determined sizing. (#828) [Geoff Barrett] * Fix not tracing modules following primitives. (#837) [Jie Xu] * Fix trace overflow on huge arrays. (#834) [Geoff Barrett] * Fix quoted comment slashes in defines. (#845) [Adam Krolnik] Verilator 3.864 2014-09-21 ========================== **Minor:** * Support power operator with real. (#809) [Jonathon Donaldson] * Improve verilator_profcfunc time attributions. [Jonathon Donaldson] * Fix duplicate anonymous structures in $root. (#788) [Bob Newgard] * Fix mis-optimization of bit-swap in wide signal. (#800) [Jie Xu] * Fix error when tracing public parameters. (#722) [Jonathon Donaldson] * Fix dpiGetContext in dotted scopes. (#740) [Geoff Barrett] * Fix over-shift structure optimization error. (#803) [Jeff Bush] * Fix optional parameter keyword in module #(). (#810) [Iztok Jeras] * Fix $warning/$error multi-argument ordering. (#816) [Jonathon Donaldson] * Fix clang warnings. (#818) [Iztok Jeras] * Fix string formats under deep expressions. (#820) [Iztok Jeras] Verilator 3.862 2014-06-10 ========================== **Minor:** * Using command line -Wno-{WARNING} now overrides file-local lint_on. * Add -P to suppress `line and blanks with preprocessing. (#781) [Derek Lockhart] * Support SV 2012 package import before port list. * Change SYMRSVDWORD to print as warning rather than error. * Fix seg-fault with variable of parameterized interface. (#692) [Jie Xu] * Fix false name conflict on cells in generate blocks. (#749) [Igor Lesik] * Fix pattern assignment to basic types. (#767) [Jie Xu] * Fix pattern assignment to conditionals. (#769) [Jie Xu] * Fix shift corner-cases. (#765) (#766) (#768) (#772) (#774) (#776) [Clifford Wolf] * Fix C compiler interpreting signing. (#773) [Clifford Wolf] * Fix late constant division by zero giving X error. (#775) [Clifford Wolf] * Fix gate primitives with arrays and non-arrayed pins. * Fix DETECTARRAY error on packed arrays. (#770) [Jie Xu] * Fix ENDLABEL warnings on escaped identifiers. * Fix string corruption. (#780) [Derek Lockhart] Verilator 3.860 2014-05-11 ========================== **Major:** * PSL is no longer supported, please use System Verilog assertions. * Support '{} assignment pattern on arrays. (#355) * Support streaming operators. (#649) [Glen Gibb] * Fix expression problems with -Wno-WIDTH. (#729) (#736) (#737) (#759) Where WIDTH warnings were ignored this might result in different warning messages and results, though it should better match the spec. [Clifford Wolf] **Minor:** * Add --no-trace-params. * Add assertions on 'unique if'. (#725) [Jeff Bush] * Add PINCONNECTEMPTY warning. [Holger Waechtler] * Support parameter arrays. (#683) [Jeremy Bennett] * Documentation fixes. (#723) [Glen Gibb] * Support {} in always sensitivity lists. (#745) [Igor Lesik] * Fix begin_keywords "1800+VAMS". (#1806) * Fix tracing of package variables and real arrays. * Fix tracing of packed arrays without --trace-structs. (#742) [Jie Xu] * Fix missing coverage line on else-if. (#727) [Sharad Bagri] * Fix modport function import not-found error. * Fix power operator calculation. (#730) (#735) [Clifford Wolf] * Fix reporting struct members as reserved words. (#741) [Chris Randall] * Fix change detection error on unions. (#758) [Jie Xu] * Fix -Wno-UNOPTFLAT change detection with 64-bits. (#762) [Clifford Wolf] * Fix shift-right optimization. (#763) [Clifford Wolf] * Fix Mac OS-X test issues. [Holger Waechtler] * Fix C++-2011 warnings. Verilator 3.856 2014-03-11 ========================== **Minor:** * Support case inside. (#708) [Jan Egil Ruud] * Add parameters into trace files. (#706) [Alex Solomatnikov] * Fix parsing "#0 'b0". (#256) * Fix array bound checks on real variables. * Fix --skip-identical mis-detecting on OS-X. (#707) * Fix missing VL_SHIFTRS_IQI with WIDTH warning. (#714) [Fabrizio Ferrandi] * Fix signed shift right optimization. (#715) [Fabrizio Ferrandi] * Fix internal error on "input x =" syntax error. (#716) [Lane Brooks] * Fix slice extraction from packed array. (#717) [Jan Egil Ruud] * Fix inside statement EQWILD error. (#718) [Jan Egil Ruud] Verilator 3.855 2014-01-18 ========================== **Minor:** * Support modport import. (#696) [Jeremy Bennett] * Add --trace-structs to show struct names. (#673) [Chris Randall] * Fix tracing of packed structs. (#705) [Jie Xu] * Fix --lint-only with MinGW. (#1813) [HyungKi Jeong] * Fix some delayed assignments of typedefed unpacked arrays. * Fix wire declarations with size and not range. (#466) [Alex Solomatnikov] * Fix parameter pin vs. normal pin error. (#704) [Alex Solomatnikov] Verilator 3.854 2013-11-26 ========================== **Minor:** * Add UNPACKED warning to convert unpacked structs. [Jeremy Bennett] * Add --compiler clang to work around compiler bug. (#694) [Stefan Ludwig] * Support vpi_get of vpiSuppressVal. (#687) [Varun Koyyalagunta] * Support vpi_get_time. (#688) [Varun Koyyalagunta] * Fix evaluation of chained parameter functions. (#684) [Ted Campbell] * Fix enum value extension of '1. * Fix multiple VPI variable callbacks. (#679) [Rich Porter] * Fix vpi_get of vpiSize. (#680) [Rich Porter] * Fix vpi_remove_cb inside callback. (#689) [Varun Koyyalagunta] * Fix crash with coverage of structures. (#691) [Eivind Liland] * Fix array assignment from const var. (#693) [Jie Xu] Verilator 3.853 2013-09-30 ========================== **Minor:** * Add --no-order-clock-delay to work around #613. [Charlie Brej] Verilator 3.852 2013-09-29 ========================== **Minor:** * Support named function and task arguments. [Chris Randall] * Report SELRANGE warning for non-generate if. (#675) [Roland Kruse] * Fix ordering of $fgetc. (#1808) [Frédéric Requin] * Fix --output-split-cfunc to count internal functions. [Chris Randall] * Fix crash on 32-bit Ubuntu. (#670) [Mark Jackson Pulver] Verilator 3.851 2013-08-15 ========================== **Minor:** * Fix ordering of clock enables with delayed assigns. (#613) [Jeremy Bennett] * Fix vpi_iterate on memory words. (#655) [Rich Porter] * Fix final duplicate declarations when non-inlined. (#661) [Charlie Brej] * Fix interface ports with comma lists. (#1779) [Ed Lander] * Fix parameter real conversion from integer. * Fix clang warnings. (#668) [Yutetsu Takatsukasa] Verilator 3.850 2013-06-02 ========================== **Major:** * Support interfaces and modports. (#102) [Byron Bradley, Jeremy Bennett] **Minor:** * Duplicate clock gate optimization on by default. (#621) * Fix arrayed input compile error. (#645) [Krzysztof Jankowski] * Fix GCC version runtime changes. (#651) [Jeremy Bennett] * Fix packed array select internal error. (#652) [Krzysztof Jankowski] Verilator 3.847 2013-05-11 ========================== **Minor:** * Add ALWCOMBORDER warning. [KC Buckenmaier] * Add --pins-sc-uint and --pins-sc-biguint. (#638) [Alex Hornung] * Support "signal[vec]++". * Fix simulation error when inputs and MULTIDRIVEN. (#634) [Ted Campbell] * Fix module resolution with __. (#631) [Jason McMullan] * Fix packed array non-zero right index select crash. (#642) [Krzysztof Jankowski] * Fix nested union crash. (#643) [Krzysztof Jankowski] Verilator 3.846 2013-03-09 ========================== **Major:** * IEEE 1800-2012 is now the default language. This adds 4 new keywords and updates the svdpi.h and vpi_user.h header files. * Add --report-unoptflat. (#611) [Jeremy Bennett] **Minor:** * Add duplicate clock gate optimization. (#1772) [Varun Koyyalagunta] Disabled unless -OD or -O3 used, please try it as may get some significant speedups. * Support pattern assignment features. (#616) (#617) (#618) [Ed Lander] * Support bind in $unit. (#602) [Ed Lander] * Support '() sized casts. (#628) [Ed Lander] * Fix wrong dot resolution under inlining. [Art Stamness] * Fix DETECTARRAY on packed structures. (#610) [Jeremy Bennett] * Fix LITENDIAN on unpacked structures. (#614) [Wai Sum Mong] * Fix 32-bit OS VPI scan issue. (#615) [Jeremy Bennett, Rich Porter] * Fix opening a VerilatedVcdC file multiple times. (#1774) [Frédéric Requin] * Fix UNOPTFLAT circular array bounds crossing. (#630) [Jie Xu] Verilator 3.845 2013-02-04 ========================== **Minor:** * Fix nested packed arrays and struct. (#600) [Jeremy Bennett] Packed arrays are now represented as a single linear vector in Verilated models. This may affect packed arrays that are public or accessed via the VPI. * Support wires with data types. (#608) [Ed Lander] * Support bind, to module names only. (#602) [Ed Lander] * Support VPI product info, warning calls, etc. (#588) [Rick Porter] * Support $left, $right and related functions. (#448) [Iztok Jeras] * Support inside expressions. * Define SYSTEMVERILOG, SV_COV_START and other IEEE mandated predefines. * Fix pin width mismatch error. (#595) [Alex Solomatnikov] * Fix implicit one bit parameter selection. (#603) [Jeremy Bennett] * Fix signed/unsigned parameter misconversion. (#606) [Jeremy Bennett] * Fix segfault on multidimensional dotted arrays. (#607) [Jie Xu] * Fix per-bit array output connection error. (#414) [Jan Egil Ruud] * Fix package logic var compile error. * Fix enums with X values. Verilator 3.844 2013-01-09 ========================== **Minor:** * Support "unsigned int" DPI import functions. (#1770) [Alex Lee] * Fix package resolution of parameters. (#586) [Jeremy Bennett] * Fix non-integer vpi_get_value. (#587) [Rich Porter] * Fix task inlining under $display and case. (#589) (#598) [Holger Waechtler] * Fix package import of non-localparam parameter. (#474) (#591) [Jeremy Bennett] * Fix package import of package imports, partial #592. [Jeremy Bennett] * Fix package import preventing local var. (#599) [Jeremy Bennett] * Fix array extraction of implicit vars. (#601) [Joe Eiler] Verilator 3.843 2012-12-01 ========================== **Minor:** * Add +1364-1995ext and similar language options. (#532) [Jeremy Bennett] * Fix mis-optimized identical submodule subtract. (#581) [Charlie Brej] * Fix crash on dotted references into dead modules. (#583) [Jeremy Bennett] * Fix compile issues on MSVCC. (#571) (#577) [Amir Gonnen] * Fix --debug overriding preceding --dump-treei. (#580) [Jeremy Bennett] Verilator 3.842 2012-11-03 ========================== **Minor:** * Add -x-initial-edge. (#570) [Jeremy Bennett] * Fix parameter pins interspersed with cells broke in 3.840. [Bernard Deadman] * Fix large shift error on large shift constants. [David Welch] * Fix $display mangling on GCC 4.7 and speed up. (#1765) (#373) (#574) [R Diez] * Fix array of struct references giving false error. (#566) [Julius Baxter] * Fix missing var access functions when no DPI. (#572) [Amir Gonnen] * Fix name collision on unnamed blocks. (#567) [Chandan Egbert] * Fix name collision on task inputs. (#569) [Chandan Egbert] Verilator 3.841 2012-09-03 ========================== **Major:** * Add --savable to support model save/restore. [Jeremy Bennett] **Minor:** * Support '{} assignment pattern on structures, part of #355. * Fix double-deep parameter cell WIDTHs. (#541) [Hiroki Honda] * Fix imports under multiple instantiated cells. (#542) [Alex Solomatnikov] * Fix defparam in generate broke in 3.840. (#543) [Alex Solomatnikov] * Fix duplicate begin error broke in 3.840. (#548) [Alex Solomatnikov] * Fix triangle symbol resolution error broke in 3.840. (#550) [Ted Campbell] Verilator 3.840 2012-07-31 Beta =============================== **Major:** * Rewrote tristate handling; supports tri0, tri1, tristate bit selects, concatenates and pullup/pulldowns. (#395) (#56) (#54) (#51) [Alex Solomatnikov, Lane Brooks, et al] * Support packed structures and unions. (#181) Note this was a major internal change that may lead to some instability. **Minor:** * Support tri0 and tri1. (#462) [Alex Solomatnikov] * Support nmos and pmos. (#488) [Alex Solomatnikov] * Add INITIALDLY warning on initial assignments. (#478) [Alex Solomatnikov] * Add PINMISSING and PINNOCONNECT lint checks. * Add --converge-limit option. * Fix generate operators not short circuiting. (#413) [by Jeremy Bennett] * Fix parameters not supported in constant functions. (#474) [Alex Solomatnikov] * Fix duplicate warnings/errors. (#516) [Alex Solomatnikov] * Fix signed extending biops with WIDTH warning off. (#511) [Junji Hashimoto] * Fix ITOD internal error on real conversions. (#491) [Alex Solomatnikov] * Fix input and real loosing real data type. (#501) [Alex Solomatnikov] * Fix imports causing symbol table error. (#490) [Alex Solomatnikov] * Fix newlines in radix values. (#507) [Walter Lavino] * Fix loop error message to report line. (#513) [Jeremy Bennett] * Fix false UNUSED warning on file system calls. * Fix GCC 4.7.0 compile warnings. (#530) [Jeremy Bennett] * Fix svdpi.h compile error on Apple OS. * Fix compile error under git submodules. (#534) [Aurelien Francillon] Verilator 3.833 2012-04-15 ========================== **Minor:** * Support += and -= in standard for loops. (#463) [Alex Solomatnikov] * Fix processing unused parameterized modules. (#469) (#470) [Alex Solomatnikov] * Add SELRANGE as warning instead of error. (#477) [Alex Solomatnikov] * Add readme.pdf and internal.pdf and doxygen. (#483) [by Jeremy Bennett] * Fix change detections on arrays. (#364) [John Stevenson, Alex Solomatnikov] * Fix signed array warning. (#456) [Alex Solomatnikov] * Fix genvar and begin under generate. (#461) [Alex Solomatnikov] * Fix real constant parameter functions. (#475) [Alex Solomatnikov] * Fix and document --gdb option. (#454) [Jeremy Bennett] * Fix OpenSolaris compile error. [Sanjay Singh] Verilator 3.832 2012-03-07 ========================== **Minor:** * Fix memory delayed assignments from multiple clock domains. [Andrew Ling] * Support arrayed SystemC I/O pins. [Christophe Joly] * Report MULTIDRIVEN on memories set in multiple clock domains. * Report ENDLABEL on mismatching end labels. (#450) [Iztok Jeras] * Fix expansion of back-slashed escaped macros. (#441) [Alberto Del Rio] * Fix inheriting real and signed type across untyped parameters. * Fix core dump with over 100 deep UNOPTFLAT. (#432) [Joe Eiler] * Fix false command not found warning in makefiles. [Ruben Diez] * Fix hang when functions inside begin block. [David Welch] * Fix hang on recursive substitution `defines. (#443) [Alex Solomatnikov] Verilator 3.831 2012-01-20 ========================== **Major:** * Support SystemC 2.3.0 prerelease. This requires setting the new SYSTEMC_INCLUDE and SYSTEMC_LIBDIR variables in place of now deprecated SYSTEMC and SYSTEMC_ARCH. [Iztok Jeras] **Minor:** * Suppress VARHIDDEN on dpi import arguments. [Ruben Diez] * Support "generate for (genvar i=0; ...". [David Kravitz] * Fix dpi exports with > 32 bit but < 64 bit args. (#423) [Chandan Egbert] * Fix array of instantiations with sub-range output. (#414) [Jeremy Bennett] * Fix BLKSEQ warnings on variables declared inside always. [Ruben Diez] Verilator 3.830 2011-11-27 ========================== **Major:** * With "--language VAMS" support a touch of Verilog AMS. [Holger Waechtler] **Minor:** * Add sc_bv attribute to force bit vectors. (#402) [by Stefan Wallentowitz] * Search for user -y paths before default current directory. [Ruben Diez] * Support constants in sensitivity lists. (#412) [Jeremy Bennett] * Support $system. [Ruben Diez] * Support $sscanf with %g. [Holger Waechtler] * Indicate 'exiting due to errors' if errors, not warnings. [Ruben Diez] * Fix bad result with if-else-return optimization. (#420) [Alex Solomatnikov] * Fix reporting not found modules if generate-off. (#403) [Jeremy Bennett] * Fix $display with %d following %g. [Holger Waechtler] Verilator 3.824 2011-10-25 ========================== **Minor:** * Fix "always @ (* )". (#403) (#404) [Walter Lavino] * Add ASSIGNIN as suppressible error. [Jeremy Bennett] * Fix 3.823 constructor core dump on Debian. (#401) [Ahmed El-Mahmoudy] Verilator 3.823 2011-10-20 ========================== **Minor:** * Support $ceil, $floor, etc. [Alex Solomatnikov] * Add configure options for cc warnings and extended tests. [Ruben Diez] * Add -Wall reporting ASSIGNDLY on assignment delays. [Ruben Diez] * Fix UNDRIVEN warnings inside DPI import functions. [Ruben Diez] * Fix --help output to go to stderr, not stdout. (#397) [Ruben Diez] * Fix DPI import output of 64 bits. (#398) [Mike Denio] * Fix DPI import false BLKSEQ warnings. [Alex Solomatnikov] * Fix MSVC compile warning with trunc/round. (#394) [Amir Gonnen] * Fix autoconf and Makefile warnings. (#396) [Ruben Diez] Verilator 3.821 2011-09-14 ========================== **Minor:** * Fix PowerPC runtime error. (#288) [Ahmed El-Mahmoudy] * Fix internal error on integer casts. (#374) [Chandan Egbert] Verilator 3.820 2011-07-28 ========================== **Minor:** * Support 'real' numbers and related functions. * Support 'const' variables in limited cases; similar to enums. [Alex Solomatnikov] * Support disable for loop escapes. * Support $fopen and I/O with integer instead of `verilator_file_descriptor. * Support coverage in -cc and -sc output modes. [John Li] Note this requires SystemPerl 1.338 or newer. * Use 'vluint64_t' for SystemC instead of (same sized) 'uint64' for MSVC++. * Fix vpi_register_cb using bad s_cb_data. (#370) [by Thomas Watts] * Fix $display missing leading zeros in %0d. (#367) [Alex Solomatnikov] Verilator 3.813 2011-06-28 ========================== **Minor:** * Support bit vectors > 64 bits wide in DPI import and exports. * Fix out of memory on slice syntax error. (#354) [Alex Solomatnikov] * Fix error on enum references to other packages. (#339) [Alex Solomatnikov] * Fix DPI undeclared svBitVecVal compile error. (#346) [Chandan Egbert] * Fix DPI bit vector compile errors. (#347) (#359) [Chandan Egbert] * Fix CDCRSTLOGIC report showing endpoint flops without resets. * Fix compiler warnings on SPARC. (#288) [Ahmed El-Mahmoudy] Verilator 3.812 2011-04-06 ========================== **Minor:** * Add --trace-max-width and --trace-max-array. (#319) [Alex Solomatnikov] * Add --Wno-fatal to turn off abort on warnings. [by Stefan Wallentowitz] * Support ${...} and $(...) env vars in .vc files. [by Stefan Wallentowitz] * Support $bits(data_type). (#327) [Alex Solomatnikov] * Support loop unrolling on width mismatches. (#333) [Joe Eiler] * Support simple cast operators. (#335) [Alex Solomatnikov] * Accelerate bit-selected inversions. * Add error on circular parameter definitions. (#329) [Alex Solomatnikov] * Fix concatenates and vectored bufif1. (#326) [Iztok Jeras] Verilator 3.811 2011-02-14 ========================== **Minor:** * Report error on duplicated or empty pins. (#321) [Christian Leber] * Report error on function call output tied to constant. [Bernard Deadman] * Throw UNUSED/UNDRIVEN only once per net in a parameterized module. * Fix internal error on functions called as SV tasks. [Bernard Deadman] * Fix internal error on non-inlined inout pins. [Jeff Winston] * Fix false BLKSEQ on non-unrolled for loop indexes. [Jeff Winston] * Fix block comment not separating identifiers. (#311) [Gene Sullivan] * Fix warnings to point to lowest net usage, not upper level ports. * Fix error on constants connected to outputs. (#323) [Christian Leber] Verilator 3.810 2011-01-03 ========================== **Major:** * Add limited support for VPI access to public signals, see docs. * Add -F option to read relative option files. (#297) [Neil Hamilton] * Support ++,--,+= etc as standalone statements. [Alex Solomatnikov] * Add -Wall, -Wwarn-style, -Wno-style to enable code style warnings that have been added to this release, and disabled by default: * With --Wall, add BLKSEQ warning on blocking assignments in seq blocks. * With --Wall, add DECLFILENAME warning on modules not matching filename. * With --Wall, add DEFPARAM warning on deprecated defparam statements. * With --Wall, add IFDEPTH warning on deep if statements. * With --Wall, add INCABSPATH warning on `include with absolute paths. * With --Wall, add SYNCASYNCNET warning on mixed sync/async reset nets. * With --Wall, add UNDRIVEN warning on undriven nets. * With --Wall, add UNUSED warning on unused nets. **Minor:** * When running with VERILATOR_ROOT, optionally find binaries under bin. * Suppress WIDTH warnings when adding/subtracting 1'b1. * The VARHIDDEN warning is now disabled by default, use -Wall to enable. Verilator 3.805 2010-11-02 ========================== **Minor:** * Add warning when directory contains spaces. (#1705) [Salman Sheikh] * Fix wrong filename on include file errors. (#289) [Brad Parker] * Fix segfault on SystemVerilog "output wire foo=0". (#291) [Joshua Wise] * Fix DPI export name not found. (#1703) [Terry Chen] Verilator 3.804 2010-09-20 ========================== **Minor:** * Support tracing/coverage of underscore signals. (#280) [by Jason McMullan] * Increase define recursions before error. [Paul Liu] * On core dump, print debug suggestions. * Fix preprocessor \`\` of existing base define. (#283) [Usha Priyadharshini] Verilator 3.803 2010-07-10 ========================== **Minor:** * Fix preprocessor preservation of newlines across macro substitutions. * Fix preprocessor stringification of nested macros. * Fix some constant parameter functions causing crash. (#253) [Nick Bowler] * Fix do {...} while() not requiring final semicolon. Verilator 3.802 2010-05-01 ========================== **Minor:** * Support runtime access to public signal names. * Add /*verilator public_flat_rw*/ for timing-specific public access. * Fix word size to match uint64_t on -m64 systems. (#238) [Joe Eiler] * Improve error handling on slices of arrays. (#226) [by Byron Bradley] * Report errors when extra underscores used in meta-comments. * Fix bit reductions on multi-packed dimensions. (#227) [by Byron Bradley] * Fix removing $fscanf if assigned to unused var. (#248) [Ashutosh Das] * Fix "make install" with configure outside srcdir. [Stefan Wallentowitz] * Fix loop unroller out of memory; change --unroll-stmts. [Ashutosh Das] * Fix trace files with empty modules crashing some viewers. * Fix parsing single files > 2GB. [Jeffrey Short] * Fix installing data files as non-executable. (#168) [by Ahmed El-Mahmoudy] Verilator 3.801 2010-03-17 ========================== **Minor:** * Support "break", "continue", "return". * Support "`default_nettype none|wire". [Dominic Plunkett] * Skip SystemC tests if not installed. [Iztok Jeras] * Fix clock-gates with non-AND complex logic. (#220) [Ashutosh Das] * Fix flushing VCD buffers on $stop. [Ashutosh Das] * Fix Mac OS-X compile issues. (#217) [Joshua Wise, Trevor Williams] * Fix make uninstall. (#216) [Iztok Jeras] * Fix parameterized defines with empty arguments. Verilator 3.800 2010-02-07 ========================== **Major application visible changes:** * SystemPerl is no longer required for tracing. Applications must use VerilatedVcdC class in place of SpTraceVcdC. * SystemVerilog 1800-2009 is now the default language. Thus "global" etc are now keywords. See the --language option. **Major new features:** * Support SystemVerilog types "byte", "chandle", "int", "longint", "shortint", "time", "var" and "void" in variables and functions. * Support "program", "package", "import" and $unit. * Support typedef and enum. [by Donal Casey] * Support direct programming interface (DPI) "import" and "export". Includes an extension to map user $system PLI calls to the DPI. * Support assignments of multidimensional slices. (#170) [by Byron Bradley] * Support multidimensional inputs/outputs. (#171) [by Byron Bradley] * Support "reg [1:0][1:0][1:0]" and "reg x [3][2]". (#176) [Byron Bradley] * Support declarations in loop initializers. (#172) [by Byron Bradley] * Support $test$plusargs and $value$plusargs, but see the docs! * Support $sformat and $swrite. * Support 1800-2009 define defaults and `undefineall. * Add -CFLAGS, -LDFLAGS, .a, .o, and .so options. * Speed compiles by avoiding including the STL iostream header. Application programs may need to include it themselves to avoid errors. * Add experimental clock domain crossing checks. * Add experimental --pipe-filter to filter all Verilog input. * Add experimental config files to filter warnings outside of the source. * Add VARHIDDEN warning when signal name hides module name. * Support optional cell parenthesis. (#179) [by Byron Bradley] * Support for-loop i++, ++i, i--, --i. (#175) [by Byron Bradley] * Support 1800-2009 /*comments*/ in define values. * Add Makefile VM_GLOBAL_FAST, listing objects needed to link executables. * Add --bbox-unsup option to black-box unsupported UDP tables. * Add -Wno-MODDUP option to allow duplicate modules. **Bug fixes:** * Fix implicit variable issues. (#196) (#201) [Byron Bradley] * Fix 'for' variable typing. (#205) [by Byron Bradley] * Fix tracing with --pins-bv 1. (#195) [Michael S] * Fix MSVC++ 2008 compile issues. (#209) [Amir Gonnen] * Fix MinGW compilation. (#184) (#214) [by Shankar Giri, Amir Gonnen] * Fix Cygwin 1.7.x compiler error with uint32_t. (#204) [Ivan Djordjevic] * Fix `define argument mis-replacing system task of same name. (#191) * Fix Verilator core dump on wide integer divides. (#178) [Byron Bradley] * Fix lint_off/lint_on meta comments on same line as warning. Verilator 3.720 2009-10-26 ========================== **Major:** * Support little endian bit vectors ("reg [0:2] x;"). * Support division and modulus of > 64 bit vectors. [Gary Thomas] **Minor:** * Fix writing to out-of-bounds arrays writing element 0. * Fix core dump with SystemVerilog var declarations under unnamed begins. * Fix VCD files showing internal flattened hierarchy, broke in 3.714. * Fix cell port connection to unsized integer causing false width warning. * Fix erroring on strings with backslashed newlines. (#168) [Pete Nixon] Verilator 3.714 2009-09-18 ========================== **Major:** * Add --bbox-sys option to blackbox $system calls. **Minor:** * Support generate for var++, var--, ++var, --var. * Improved warning when "do" used as identifier. * Don't require SYSTEMPERL_INCLUDE if SYSTEMPERL/src exists. [Gary Thomas] * Fix deep defines causing flex scanner overflows. [Brad Dobbie] * Fix preprocessing commas in deep parameterized macros. [Brad Dobbie] * Fix tracing escaped dotted identifiers. (#107) * Fix $display with uppercase %M. * Fix --error-limit option being ignored. Verilator 3.713 2009-08-04 ========================== **Minor:** * Support constant function calls for parameters. [many!] * Support SystemVerilog "logic". (#101) [by Alex Duller] * Name SYMRSVDWORD error, and allow disabling it. (#103) [Gary Thomas] * Fix escaped preprocessor identifiers. (#106) [Nimrod Gileadi] Verilator 3.712 2009-07-14 ========================== **Major:** * Patching SystemC is no longer required to trace sc_bvs. **Minor:** * Add verilator --pins-uint8 option to use sc_in. * Add verilator -V option, to show verbose version. * Add BLKLOOPINIT error code, and describe --unroll-count. [Jeff Winston] * Support zero-width constants in concatenations. [Jeff Winston] * On WIDTH warnings, show variable name causing error. [Jeff Winston] Verilator 3.711 2009-06-23 ========================== **Minor:** * Support decimal constants of arbitrary widths. [Mark Marshall] * Fix error on case statement with all duplicate items. (#99) [Gary Thomas] * Fix segfault on unrolling for's with bad inits. (#90) [Andreas Olofsson] * Fix tristates causing "Assigned pin is neither...". [by Lane Brooks] * Fix compiler errors under Fedora release candidate 11. [Chitlesh Goorah] Verilator 3.710 2009-05-19 ========================== **Major:** * Verilator is now licensed under LGPL v3 and/or Artistic v2.0. **Minor:** * `__FILE__ now expands to a string, per draft SystemVerilog 2010(ish). * The front end parser has been re-factored to enable more SV parsing. Code should parse the same, but minor parsing bugs may pop up. * Verilator_includer is no longer installed twice. (#48) [Lane Brooks] * Fix escaped identifiers with '.' causing conflicts. (#83) [J Baxter] * Fix define formal arguments that contain newlines. (#84) [David A] Verilator 3.703 2009-05-02 ========================== **Minor:** * Fix $clog2 calculation error with powers-of-2. (#81) [Patricio Kaplan] * Fix error with tasks that have output first. (#78) [Andrea Foletto] * Fix "cloning" error with -y/--top-module. (#76) [Dimitris Nalbantis] * Fix segfault with error on bad --top-module. (#79) [Dimitris Nalbantis] * Fix "redefining I" error with complex includes. [Duraid Madina] * Fix GCC 4.3.2 compile warnings. Verilator 3.702 2009-03-28 ========================== **Minor:** * Add --pins-bv option to use sc_bv for all ports. [Brian Small] * Add SYSTEMPERL_INCLUDE envvar to assist RPM builds. [Chitlesh Goorah] * Report errors when duplicate labels are used. (#72) [Vasu Kandadi] * Fix the SC_MODULE name() to not include __PVT__. [Bob Fredieu] Verilator 3.701 2009-02-26 ========================== **Minor:** * Support repeat and forever statements. [Jeremy Bennett] * Add --debugi- option, for internal debugging. [Dennis Muhlestein] * Fix compile issues with GCC 4.3. (#47) [Lane Brooks] * Fix VL_RANDom to better randomize bits. [Art Stamness] * Fix error messages to consistently go to stderr. [Jeremy Bennett] * Fix left associativity for ?: operators. Verilator 3.700 2009-01-08 ========================== **Major:** * Support limited tristate inouts. Written by Lane Brooks, under support by Ubixum Inc. This allows common pad ring and tristate-mux structures to be Verilated. See the documentation for more information on supported constructs. * Add --coverage_toggle for toggle coverage analysis. Running coverage now requires SystemPerl 1.301 or newer. * Add coverage_on/_off metacomments to bracket coverage regions. **Minor:** * Support posedge of bit-selected signals. (#45) [Rodney Sinclair] * Optimize two-level shift and and/or trees, +23% on one test. * Line coverage now aggregates by hierarchy automatically. Previously this would be done inside SystemPerl, which was slower. * Minor performance improvements of Verilator compiler runtime. * Coverage of each parameterized module is counted separately. [Bob Fredieu] * Fix creating parameterized modules when no parameter values are changed. * Fix certain generate-if cells causing "clone" error. [Stephane Laurent] * Fix line coverage of public functions. [Soon Koh] * Fix SystemC 2.2 deprecated warnings about sensitive() and sc_start(). * Fix arrayed variables under function not compiling. (#44) [Ralf Karge] * Fix --output-split-cfuncs to also split trace code. [Niranjan Prabhu] * Fix 'bad select range' warning missing some cases. (#43) [Lane Brooks] * Fix internal signal names containing control characters (broke in 3.680). * Fix compile error on Ubuntu 8.10. [Christopher Boumenot] * Fix internal error on "output x; reg x = y;". * Fix wrong result for read of delayed FSM signal. (#46) [Rodney Sinclair] Verilator 3.681 2008-11-12 ========================== **Minor:** * Support SystemVerilog unique and priority case. * Include Verilog file's directory name in coverage reports. * Fix 'for' under 'generate-for' causing error. (#38) [Rafael Shirakawa] * Fix coverage hierarchy being backwards with inlining. [Vasu Arasanipalai] * Fix GCC 4.3 compile error. (#35) [Lane Brooks] * Fix MSVC compile error. (#42) [John Stroebel] Verilator 3.680 2008-10-08 ========================== **Major:** * Support negative bit indexes. [Stephane Laurent] Tracing negative indexes requires latest Verilog-Perl and SystemPerl. **Minor:** * Suppress width warnings between constant strings and wider vectors. [Rodney Sinclair] * Ignore SystemVerilog timeunit and timeprecision. * Expand environment variables in -f input files. [Lawrence Butcher] * Report error if port declaration is missing. (#32) [Guy-Armand Kamendje] * Fix genvars causing link error when using --public. [Chris Candler] Verilator 3.671 2008-09-19 ========================== **Major:** * SystemC uint64_t pins are now the default instead of sc_bv<64>. Use --no-pins64 for backward compatibility. * Support SystemVerilog "cover property" statements. **Minor:** * When warnings are disabled on signals that are flattened out, disable the warnings on the signal(s) that replace it. * Add by-design and by-module subtotals to verilator_profcfunc. * Add IMPERFECTSCH warning, disabled by default. * Support coverage under SystemPerl 1.285 and newer. * Support arbitrary characters in identifiers. [Stephane Laurent] * Fix extra evaluation of pure combo blocks in SystemC output. * Fix stack overflow on large ? : trees. [John Sanguinetti] Verilator 3.670 2008-07-23 ========================== **Major:** * Add --x-assign=fast option, and make it the default. This chooses performance over reset debugging. See the manual. * Add --autoflush, for flushing streams after $display. [Steve Tong] * Add CASEWITHX lint warning and if disabled fix handling of casez with Xs. **Minor:** * Add $feof, $fgetc, $fgets, $fflush, $fscanf, $sscanf. [Holger Waechtler] * Add $stime. [Holger Waechtler] * Add $random. * Add --Wfuture-, for improving forward compatibility. * Add WIDTH warning to $fopen etc file descriptors. * Fix verilator_includer not being installed properly. [Holger Waechtler] * Fix IMPURE errors due to X-assignment temporary variables. [Steve Tong] * Fix "lvalue" errors with public functions. (#25) [CY Wang] Verilator 3.665 2008-06-25 ========================== **Minor:** * Ignore "// verilator" comments alone on endif lines. [Rodney Sinclair] * "Make install" now installs verilator_includer and verilator_profcfunc. * Fix tracing missing changes on undriven public wires. [Rodney Sinclair] * Fix syntax error when "`include `defname" is ifdefed. [John Dickol] * Fix error when macro call has commas in concatenate. [John Dickol] * Fix compile errors under Fedora 9, GCC 4.3.0. [by Jeremy Bennett] * Fix Makefile to find headers/libraries under prefix. [by Holger Waechtler] Verilator 3.664 2008-05-08 ========================== **Minor:** * Fix missing file in kit. Verilator 3.663 2008-05-07 ========================== **Minor:** * Add DESTDIR to Makefiles to assist RPM construction. [Gunter Dannoritzer] * Fix compiler warnings under GCC 4.2.1. * Fix preprocessor `else after series of `elsif. [Mark Nodine] * Fix parameterized defines calling define with comma. [Joshua Wise] * Fix comma separated list of primitives. [by Bryan Brady] Verilator 3.662 2008-04-25 ========================== **Minor:** * Add Verilog 2005 $clog2() function. This is useful in calculating bus-widths from parameters. * Support C-style comments in -f option files. [Stefan Thiede] * Add error message when modules have duplicate names. [Stefan Thiede] * Support defines terminated in EOF, though against spec. [Stefan Thiede] * Support optional argument to $finish and $stop. [by Stefan Thiede] * Support ranges on gate primitive instantiations. [Stefan Thiede] * Ignore old standard(ish) Verilog-XL defines. [by Stefan Thiede] * Fix "always @ ((a) or (b))" syntax error. [by Niranjan Prabhu] * Fix "output reg name=expr;" syntax error. [Martin Scharrer] * Fix multiple .v files being read in random order. [Stefan Thiede] * Fix internal error when params get non-constants. [Johan Wouters] * Fix bug introduced in 3.661 with parameterized defines. Verilator 3.661 2008-04-04 ========================== **Major:** * The --enable-defenv configure option added in 3.660 is now the default. This hard-codes a default for VERILATOR_ROOT etc in the executables. * Add --language option for supporting older code. [Stefan Thiede] * Add --top-module option to select between multiple tops. [Stefan Thiede] **Minor:** * Unsized concatenates now give WIDTHCONCAT warnings. [Jonathan Kimmitt] Previously they threw fatal errors, which in most cases is correct according to spec, but can be incorrect in presence of parameter values. * Support functions with "input integer". [Johan Wouters] * Ignore delays attached to gate UDPs. [Stefan Thiede] * Fix SystemVerilog parameterized defines with \`\` expansion, and fix extra whitespace inserted on substitution. [Vladimir Matveyenko] * Fix no-module include files on command line. [Stefan Thiede] * Fix dropping of backslash quoted-quote at end of $display. * Fix task output pin connected to non-variables. [Jonathan Kimmitt] * Fix missing test_v in install datadir. [Holger Waechtler] * Fix internal error after MSB < LSB error reported to user. [Stefan Thiede] Verilator 3.660 2008-03-23 ========================== **Minor:** * Support hard-coding VERILATOR_ROOT etc in the executables, to enable easier use of Verilator RPMs. [Gunter Dannoritzer] * Allow multiple .v files on command line. [Stefan Thiede] * Convert re-defining macro error to warning. [Stefan Thiede] * Add --error-limit option. [Stefan Thiede] * Allow __ in cell names by quoting them in C. [Stefan Thiede] * Fix genvar to be signed, so "< 0" works properly. [Niranjan Prabhu] * Fix assignments to inputs inside functions/tasks. [Patricio Kaplan] * Fix definitions in main file.v, referenced in library. [Stefan Thiede] * Fix undefined assigns to be implicit warnings. [Stefan Thiede] Verilator 3.658 2008-02-25 ========================== **Minor:** * Fix unistd compile error in 3.657. [Patricio Kaplan, Jonathan Kimmitt] Verilator 3.657 2008-02-20 ========================== **Minor:** * Fix assignments of {a,b,c} = {c,b,a}. [Jonathan Kimmitt] * Fix Perl warning with --lint-only. [by Ding Xiaoliang] * Fix to avoid creating obj_dir with --lint-only. [Ding Xiaoliang] * Fix parsing of always @(*). [Patricio Kaplan] Verilator 3.656 2008-01-18 ========================== **Minor:** * Wide VL_CONST_W_#X functions are now made automatically. [Bernard Deadman] In such cases, a new {prefix}__Inlines.h file will be built and included. * Fix sign error when extracting from signed memory. [Peter Debacker] * Fix tracing of SystemC w/o SystemPerl. [Bernard Deadman, Johan Wouters] Verilator 3.655 2007-11-27 ========================== **Minor:** * Support "#delay ;" with associated STMTDLY warning. * Fix generate for loops with constant zero conditions. [Rodney Sinclair] * Fix divide-by-zero errors in constant propagator. [Rodney Sinclair] * Fix wrong result with obscure signed-shift underneath a "? :". * Fix many internal memory leaks, and added leak detector. Verilator 3.654 2007-10-18 ========================== **Minor:** * Don't exit early if many warnings but no errors are found. [Stan Mayer] * Fix parsing module #(parameter x,y) declarations. [Oleg Rodionov] * Fix parsing system functions with empty parens. [Oleg Rodionov] Verilator 3.653 2007-08-01 ========================== **Minor:** * Support SystemVerilog ==? and !=? operators. * Fix SC_LIBS missing from generated makefiles. [Ding Xiaoliang] Verilator 3.652 2007-06-21 ========================== **Minor:** * Report as many warning types as possible before exiting. * Support V2K portlists with "input a,b,...". [Mark Nodine] * Support V2K function/task argument lists. * Optimize constant $display arguments. * Fix preprocessor dropping some `line directives. [Mark Nodine] Verilator 3.651 2007-05-22 ========================== **Major:** * Add verilator_profcfunc utility. [Gene Weber] **Minor:** * Treat modules within `celldefine and `endcelldefine as if in library. * Support functions which return integers. [Mark Nodine] * Warn if flex is not installed. [Ralf Karge] * Ignore `protect and `endprotect. * Fix empty case/endcase blocks. Verilator 3.650 2007-04-20 ========================== **Major:** * Add --compiler msvc option. This is now required when Verilated code is to be run through MSVC++. This also enables fixing MSVC++ error C1061, blocks nested too deeply. [Ralf Karge] * Add --lint-only option, to lint without creating other output. **Minor:** * Add /*verilator lint_save*/ and /*verilator lint_restore*/ to allow friendly control over re-enabling lint messages. [Gerald Williams] * Support SystemVerilog .name and .* interconnect. * Support while and do-while loops. * Use $(LINK) instead of $(CXX) for Makefile link rules. [Gerald Williams] * Add USER_CPPFLAGS and USER_LDFLAGS to Makefiles. [Gerald Williams] * Fix compile errors under Windows MINGW compiler. [Gerald Williams] * Fix dotted bit reference to local memory. [Eugene Weber] * Fix 3.640 `verilog forcing IEEE 1364-1995 only. [David Hewson] Verilator 3.640 2007-03-12 ========================== **Minor:** * Support Verilog 2005 `begin_keywords and `end_keywords. * Updated list of SystemVerilog keywords to correspond to IEEE 1800-2005. * Add /*verilator public_flat*/. [Eugene Weber] * Try all +libext's in the exact order given. [Michael Shinkarovsky] * Fix elimination of public signals assigned to constants. [Eugene Weber] * Fix internal error when public for loop has empty body. [David Addison] * Fix "Loops detected" assertion when model exceeds 4GB. [David Hewson] * Fix display %m names inside named blocks. Verilator 3.633 2007-02-07 ========================== **Minor:** * Add --trace-depth option for minimizing VCD file size. [Emerson Suguimoto] * With VL_DEBUG, show wires causing convergence errors. [Mike Shinkarovsky] * Fix isolate_assignments when many signals per always. [Mike Shinkarovsky] * Fix isolate_assignments across task/func temporaries. [Mike Shinkarovsky] * Fix $display's with array select followed by wide AND. [David Hewson] Verilator 3.632 2007-01-17 ========================== **Minor:** * Add /*verilator isolate_assignments*/ attribute. [Mike Shinkarovsky] Verilator 3.631 2007-01-02 ========================== **Major:** * Support standard NAME[#] for cells created by arraying or generate for. This replaces the non-standard name__# syntax used in earlier versions. **Minor:** * Fix again dotted references into generate cells. [David Hewson] Verilator no longer accepts duplicated variables inside unique generate blocks as this is illegal according to the specification. * Fix $readmem* with filenames < 8 characters. [Emerson Suguimoto] Verilator 3.630 2006-12-19 ========================== **Major:** * Support $readmemb and $readmemh. [Eugene Weber, Arthur Kahlich] **Minor:** * When dotted signal lookup fails, help the user by showing known scopes. * Fix to reduce depth of priority encoded case statements. [Eugene Weber] * Fix configure and compiling under Solaris. [Bob Farrell] * Fix dotted references inside generated cells. [David Hewson] * Fix missed split optimization points underneath other re-split blocks. Verilator 3.623 2006-12-05 ========================== **Major:** * Add --output-split-cfuncs for accelerating GCC compile. [Eugene Weber] **Minor:** * Add M32 make variable to support -m32 compiles. [Eugene Weber] * Fix $signed mis-extending when input has a WIDTH violation. [Eugene Weber] Verilator 3.622 2006-10-17 Stable ================================= **Minor:** * Fix --skip-identical without --debug, broken in 3.621. [Andy Meier] Verilator 3.621 2006-10-11 Beta =============================== **Major:** * Add /*verilator no_inline_task*/ to prevent over-expansion. [Eugene Weber] **Minor:** * Public functions now allow > 64 bit arguments. * Remove .vpp intermediate files when not under --debug. * Fix link error when using --exe with --trace. [Eugene Weber] * Fix mis-optimization of wide concats with constants. * Fix core dump on printing error when not under --debug. [Allan Cochrane] Verilator 3.620 2006-10-04 Stable ================================= **Minor:** * Support simple inout task ports. [Eugene Weber] * Allow overriding Perl, Flex and Bison versions. [by Robert Farrell] * Optimize variables set to constants within basic blocks for ~3%. * Default make no longer makes the docs; if you edit the documentation. sources, run "make info" to get them. * Optimize additional Boolean identities (a|a = a, etc.) * Fix coredump when dotted cross-ref inside task call. [Eugene Weber] * Fix dotted variables in always sensitivity lists. [Allan Cochrane] Verilator 3.610 2006-09-20 Stable ================================= **Minor:** * Verilator now works under DJGPP (Pentium GCC). [John Stroebel] * Add default define for VL_PRINTF. [John Stroebel] * Removed coverage request variable; see Coverage limitations in docs. * Fix DOS carriage returns in multiline defines. [Ralf Karge] * Fix printf format warnings on 64-bit linux. Verilator 3.602 2006-09-11 Stable ================================= **Minor:** * Fix function references under top inlined module. [David Hewson] Verilator 3.601 2006-09-06 Beta =============================== **Major:** * Add --inhibit-sim flag for environments using old __Vm_inhibitSim. * Add `systemc_dtor for destructor extensions. [Allan Cochrane] * Add -MP to make phony dependencies, ala GCC's. **Minor:** * Changed how internal functions are invoked to reduce aliasing. Useful when using GCC's -O2 or -fstrict-aliasing, to gain another ~4%. * Declare optimized lookup tables as 'static', to reduce D-Cache miss rate. * Fix memory leak when destroying modules. [John Stroebel] * Fix coredump when unused modules have unused cells. [David Hewson] * Fix 3.600 internal error with arrayed instances. [David Hewson] * Fix 3.600 internal error with non-unrolled function loops. [David Hewson] * Fix $display %m name not matching Verilog name inside SystemC modules. Verilator 3.600 2006-08-28 Beta =============================== **Major:** * Support dotted cross-hierarchy variable and task references. **Minor:** * Lint for x's in generate case statements. * Fix line numbers being off by one when first file starts with newline. * Fix naming of generate for blocks to prevent non-inline name conflict. * Fix redundant statements remaining after table optimization. Verilator 3.542 2006-08-11 Stable ================================= **Minor:** * vl_finish and vl_fatal now print via VL_PRINTF rather then cerr/cout. * Fix extraneous UNSIGNED warning when comparing genvars. [David Hewson] * Fix extra white space in $display %c. [by David Addison] * Fix missing VL_CONST_W_24X macro. [Bernard Deadman] Verilator 3.541 2006-07-05 Beta =============================== **Minor:** * Add warning on changeDetect to arrayed structures. [David Hewson] * Fix "// verilator lint_on" not re-enabling warnings. [David Hewson] * Fix 3.540's multiple memory assignments to same block. [David Hewson] * Fix non-zero start number for arrayed instantiations. [Jae Hossell] * Fix GCC 4.0 header file warnings. Verilator 3.540 2006-06-27 Beta =============================== **Minor:** * Optimize combo assignments that are used only once, ~5-25% faster. * Optimize delayed assignments to memories inside loops, ~0-5% faster. * Fix mis-width warning on bit selects of memories. [David Hewson] * Fix mis-width warning on dead generate-if branches. [Jae Hossell] Verilator 3.533 2006-06-05 Stable ================================= **Minor:** * Add PDF user manual, verilator.pdf. * Fix delayed bit-selected arrayed assignments. [David Hewson] * Fix execution path to Perl. [Shanshan Xu] * Fix Bison compile errors in verilog.y. [by Ben Jackson] Verilator 3.531 2006-05-10 Stable ================================= **Minor:** * Support $c routines which return 64 bit values. * Fix `include `DEFINE. * Fix Verilator core dump when have empty public function. [David.Hewson] Verilator 3.530 2006-04-24 Stable ================================= **Major:** * $time is now 64 bits. The macro VL_TIME_I is now VL_TIME_Q, but calls the same sc_time_stamp() function to get the current time. Verilator 3.523 2006-03-06 Stable ================================= **Minor:** * Fix error line numbers being off due to multi-line defines. [Mat Zeno] * Fix GCC sign extending (uint64_t)(a>>, $signed, $unsigned. [MANY!] * Support multi-dimensional arrays. [Eugen Fekete] * Support very limited Property Specification Language (aka PSL or Sugar). The format and keywords are now very limited, but will grow with future releases. The --assert switch enables this feature. * With --assert, generate assertions for synthesis parallel_case and full_case. **Minor:** * Fix generate if's with empty if/else blocks. [Mat Zeno] * Fix generate for cell instantiations with same name. [Mat Zeno] Verilator 3.481 2005-10-12 Stable ================================= **Minor:** * Add /*verilator tracing_on/off*/ for waveform control. * Fix split optimization reordering $display statements. Verilator 3.480 2005-09-27 Beta =============================== **Major:** * Allow coverage of flattened modules, and multiple points per line. Coverage analysis requires SystemPerl 1.230 or newer. **Minor:** * Add preprocessor changes to support meta-comments. * Optimize sequential assignments of different bits of same bus; ~5% faster. * Optimize away duplicate lookup tables. * Optimize wide concatenates into individual words. [Ralf Karge] * Optimize local variables from delayed array assignments. Verilator 3.470 2005-09-06 Stable ================================= **Minor:** * Optimize staging flops under reset blocks. * Add '-Werror-...' to upgrade specific warnings to errors. * Add GCC branch prediction hints on generated if statements. * Fix bad simulation when same function called twice in same expression. * Fix preprocessor substitution of quoted parameterized defines. Verilator 3.464 2005-08-24 Stable ================================= **Major:** * Add `systemc_imp_header, for use when using --output-split. * Add --stats option to dump design statistics. **Minor:** * Fix core dump with clock inversion optimizations. Verilator 3.463 2005-08-05 Stable ================================= **Minor:** * Fix case defaults when not last statement in case list. [Wim Michiels] Verilator 3.462 2005-08-03 Stable ================================= **Minor:** * Fix reordering of delayed assignments to same memory index. [Wim Michiels] * Fix compile error with Flex 2.5.1. [Jens Arm] * Fix multiply-instantiated public tasks generating non-compilable code. Verilator 3.461 2005-07-28 Beta =============================== **Minor:** * Fix compile error with older versions of bison. [Jeff Dutton] Verilator 3.460 2005-07-27 Beta =============================== **Major:** * Add -output-split option to enable faster parallel GCC compiles. To support --output-split, the makefiles now split VM_CLASSES into VM_CLASSES_FAST and VM_CLASSES_SLOW. This may require a change to local makefiles. * Support -v argument to read library files. **Minor:** * When issuing unoptimizable warning, show an example path. * Internal tree dumps now indicate edit number that changed the node. * Fix false warning when a clock is constant. * Fix X/Z in decimal numbers. [Wim Michiels] * Fix genvar statements in non-named generate blocks. * Fix core dump when missing newline in `define. [David van der Bokke] Verilator 3.450 2005-07-12 ========================== **Major:** * $finish will no longer exit, but set Verilated::gotFinish(). This enables support for final statements, and for other cleanup code. If this is undesired, redefine the vl_user_finish routine. Top level loops should use Verilated::gotFinish() as an exit condition for their loop, and then call top->final(). To prevent an infinite loop, a double $finish will still exit; this may be removed in future releases. * Support SystemVerilog keywords $bits, $countones, $isunknown, $onehot, $onehot0, always_comb, always_ff, always_latch, finish. **Minor:** * Fix "=== 1'bx" to always be false, instead of random. Verilator 3.440 2005-06-28 Stable ================================= **Major:** * Add Verilog 2001 generate for/if/case statements. Verilator 3.431 2005-06-24 Stable ================================= **Minor:** * Fix selection bugs introduced in 3.430 beta. Verilator 3.430 2005-06-22 Beta =============================== **Minor:** * Add Verilog 2001 variable part selects [n+:m] and [n-:m]. [Wim Michiels] Verilator 3.422 2005-06-10 Stable ================================= **Minor:** * Add Verilog 2001 power (**) operator. [Danny Ding] * Fix crash and added error message when assigning to inputs. [Ralf Karge] * Fix tracing of modules with public functions. Verilator 3.421 2005-06-02 Beta =============================== **Minor:** * Fix error about reserved word on non-public signals. * Fix missing initialization compile errors in 3.420 beta. [Ralf Karge] Verilator 3.420 2005-06-02 Beta =============================== **Minor:** * Performance improvements worth ~20% * Add -x-assign options; ~5% faster if use -x-assign=0. * Add error message when multiple defaults in case statement. * Optimize shifts out of conditionals and if statements. * Optimize local 'short' wires. * Fix case defaults when not last statement in case list. [Ralf Karge] * Fix crash when wire self-assigns x=x. * Fix gate optimization with top-flattened modules. [Mahesh Kumashikar] Verilator 3.411 2005-05-30 Stable ================================= **Minor:** * Fix compile error in GCC 2.96. [Jeff Dutton] Verilator 3.410 2005-05-25 Beta =============================== **Major:** * Allow functions and tasks to be declared public. They will become public C++ functions, with appropriate C++ types. This allows users to make public accessor functions/tasks, instead of having to use public variables and `systemc_header hacks. **Minor:** * Skip producing output files if all inputs are identical This uses timestamps, similar to make. Disable with --no-skip-identical. * Improved compile performance with large case statements. * Fix internal error in V3Table. [Jeff Dutton] * Fix compile error in GCC 2.96, and with SystemC 1.2. [Jeff Dutton] Verilator 3.400 2005-04-29 Beta =============================== **Major:** * Internal changes to support future clocking features. * Verilog-Perl and SystemPerl are no longer required for C++ or SystemC output. If you want tracing or coverage analysis, they are still needed. * Add --sc to create pure SystemC output not requiring SystemPerl. * Add --pins64 to create 64 bit SystemC outputs instead of sc_bv<64>. * The --exe flag is now required to produce executables inside the makefile. This was previously the case any time .cpp files were passed on the command line. * Add -O3 and --inline-mult for performance tuning. [Ralf Karge] One experiment regained 5% performance, at a cost of 300% in compile time. **Minor:** * Improved performance of large case/always statements with low fanin by converting to internal lookup tables (ROMs). * Initialize SystemC port names. [S Shuba] * Add Doxygen comments to Verilated includes. * Fix -cc pins 8 bits wide and less to be uint8_t instead of uint16_t. * Fix crash when Mdir has same name as .v file. [Gernot Koch] * Fix crash with size mismatches on case items. [Gernot Koch] Verilator 3.340 2005-02-18 Stable ================================= **Minor:** * Report misconnected pins across all modules, instead of just first error. * Improved large netlist compile times. * Fix over-active inlining, resulting in compile slowness. Verilator 3.332 2005-01-27 ========================== **Major:** * Add -E preprocess only flag, similar to GCC. * Add CMPCONSTLR when comparison is constant due to > or < with all ones. **Minor:** * Fix loss of first -f file argument, introduced in 3.331. Verilator 3.331 2005-01-18 ========================== **Major:** * The Verilog::Perl preprocessor is now C++ code inside of Verilator. This improves performance, makes compilation easier, and enables some future features. **Minor:** * Support arrays of instantiations (non-primitives only). [Wim Michiels] * Fix unlinked error with defparam. [Shawn Wang] Verilator 3.320 2004-12-10 ========================== **Major:** * NEWS is now renamed Changes, to support CPAN indexing. * If Verilator is passed a C file, create a makefile link rule. This saves several user steps when compiling small projects. **Minor:** * Add new COMBDLY warning in place of fatal error. [Shawn Wang] * Fix mis-simulation with wide-arrays under bit selects. [Ralf Karge] * Add NC Verilog as alternative to VCS for reference tests. * Support implicit wire declarations on input-only signals. (Dangerous, as leads to wires without drivers, but allowed by spec.) * Fix compile warnings on Suse 9.1 Verilator 3.311 2004-11-29 ========================== **Major:** * Support implicit wire declarations (as a warning). [Shawn Wang] **Minor:** * Fix over-shift difference in Verilog vs C++. [Ralf Karge] Verilator 3.310 2004-11-15 ========================== **Major:** * Support defparam. * Support gate primitives: buf, not, and, nand, or, nor, xor, xnor. **Minor:** * Ignore all specify blocks. Verilator 3.302 2004-11-12 ========================== **Minor:** * Support NAND and NOR operators. * Better warnings when port widths don't match. * Fix internal error due to some port width mismatches. [Ralf Karge] * Fix WIDTH warnings on modules that are only used parameterized, not in 'default' state. * Fix selection of SystemC library on cygwin systems. [Shawn Wang] * Fix runtime bit-selection of parameter constants. Verilator 3.301 2004-11-04 ========================== **Minor:** * Fix 64 bit [31:0] = {#{}} mis-simulation. [Ralf Karge] * Fix shifts greater then word width mis-simulation. [Ralf Karge] * Fix to work around GCC 2.96 negation bug. Verilator 3.300 2004-10-21 ========================== **Major:** * New backend that eliminates most VL macros. Improves performance 20%-50%, depending on frequency of use of signals over 64 bits. GCC compile times with -O2 shrink by a factor of 10. **Minor:** * Fix "setting unsigned int from signed value" warning. Verilator 3.271 2004-10-21 ========================== **Minor:** * Fix "loops detected" error with some negedge clocks. * Fix some output code spacing issues. Verilator 3.270 2004-10-15 ========================== **Minor:** * Support Verilog 2001 parameters in module headers. [Ralf Karge] * Faster code to support compilers not inlining all Verilated functions. * Fix numeric fault when dividing by zero. Verilator 3.260 2004-10-07 ========================== **Major:** * Support Verilog 2001 named parameter instantiation. [Ralf Karge] **Minor:** * Return 1's when one bit wide extract indexes outside array bounds. * Fix compile warnings on 64-bit operating systems. * Fix incorrect dependency in .d file when setting VERILATOR_BIN. Verilator 3.251 2004-09-09 ========================== **Minor:** * Fix parenthesis overflow in Microsoft Visual C++ [Renga Sundararajan] Verilator 3.250 2004-08-30 ========================== **Major:** * Support Microsoft Visual C++ [Renga Sundararajan] **Minor:** * SystemPerl 1.161+ is required. Verilator 3.241 2004-08-17 ========================== **Minor:** * Support ,'s to separate multiple assignments. [Paul Nitza] * Fix shift sign extension problem using non-GCC compilers. Verilator 3.240 2004-08-13 ========================== **Major:** * Verilator now uses 64 bit math where appropriate. Inputs and outputs of 33-64 bits wide to the C++ Verilated model must now be uint64_t's; SystemC has not changed, they will remain sc_bv's. This increases performance by ~ 9% on x86 machines, varying with how frequently 33-64 bit signals occur. Signals 9-16 bits wide are now stored as 16 bit shorts instead of longs, this aids cache packing. **Minor:** * Fix SystemC compile error with feedthrus. [Paul Nitza] * Fix concat value error introduced in 3.230. Verilator 3.230 2004-08-10 ========================== **Minor:** * Add coverage output to test_sp example, SystemPerl 1.160+ is required. * Fix time 0 value of signals. [Hans Van Antwerpen] Earlier versions would not evaluate some combinatorial signals until posedge/negedge blocks had been activated. * Fix wide constant inputs to public submodules [Hans Van Antwerpen] * Fix wide signal width extension bug. Only applies when width mismatch warnings were overridden. Verilator 3.220 2004-06-22 ========================== **Major:** * Many waveform tracing changes: * Tracing is now supported on C++ standalone simulations. [John Brownlee] **Minor:** * When tracing, SystemPerl 1.150 or newer is required. * When tracing, Verilator must be called with the --trace switch. * Add SystemPerl example to documentation. [John Brownlee] * Various Cygwin compilation fixes. [John Brownlee] Verilator 3.210 2004-04-01 ========================== **Major:** * Compiler optimization switches have changed See the BENCHMARKING section of the documentation. * With Verilog-Perl 2.3 or newer, Verilator supports SystemVerilog preprocessor extensions. **Minor:** * Add localparam. [Thomas Hawkins] * Add warnings for SystemVerilog reserved words. Verilator 3.203 2004-03-10 ========================== **Minor:** * Notes and repairs for Solaris. [Fred Ma] Verilator 3.202 2004-01-27 ========================== **Major:** * The beta version is now the primary release. See below for many changes. If you have many problems, you may wish to try release 3.125. * Verilated::traceEverOn(true) must be called at time 0 if you will ever turn on tracing (waveform dumping) of signals. Future versions will need this switch to disable trace incompatible optimizations. **Minor:** * Optimize common replication operations. * Fix several tracing bugs Verilator 3.201-beta 2003-12-10 =============================== **Major:** * BETA VERSION, USE 3.124 for stable release! * Version 3.2XX includes an all new back-end. This includes automatic inlining, flattening of signals between hierarchy, and complete ordering of statements. This results in 60-300% execution speedups, though less pretty C++ output. Even better results are possible using GCC 3.2.2 (part of Redhat 9.1), as GCC has fixed some optimization problems which Verilator exposes. If you are using `systemc_ctor, beware pointers to submodules are now initialized after the constructor is called for a module, to avoid segfaults, move statements that reference subcells into initial statements. * C++ Constructor that creates a verilog module may take a char* name. This name will be used to prefix any $display %m arguments, so users may distinguish between multiple Verilated modules in a single executable. Verilator 3.125 2004-01-27 ========================== **Minor:** * Optimize bit replications Verilator 3.124 2003-12-05 ========================== **Major:** * An optimized executable will be made by default, in addition to a debug executable. Invoking Verilator with --debug will pick the debug version. **Minor:** * Many minor invisible changes to support the next version. Verilator 3.123 2003-11-10 ========================== **Minor:** * Wide bus performance enhancements. * Fix function call bug when width warning suppressed. [Leon Wildman] * Fix __DOT__ compile problem with funcs in last revision. [Leon Wildman] Verilator 3.122 2003-10-29 ========================== **Major:** * Modules which are accessed from external code now must be marked with /*verilator public_module*/ unless they already contain public signals. To enforce this, private cell names now have a string prepended. **Minor:** * Fix replicated function calls in one statement. [Robert A. Clark] * Fix function call bug when width warning suppressed. [Leon Wildman] Verilator 3.121 2003-09-29 ========================== **Minor:** * Support multiplication over 32 bits. [Chris Boumenot] Also improved speed of addition and subtraction over 32 bits. * Detect bit selection out of range errors. * Detect integer width errors. * Fix width problems on function arguments. [Robert A. Clark] Verilator 3.120 2003-09-24 ========================== **Minor:** * $finish now exits the model (via vl_finish function). * Support inputs/outputs in tasks. * Support V2K "integer int = {INITIAL_VALUE};" * Ignore floating point delay values. [Robert A. Clark] * Ignore `celldefine, `endcelldefine, etc. [Robert A. Clark] * Optimize reduction operators. * Fix converting "\ooo" into octal values. * Fix $display("%x"); Verilator 3.112 2003-09-16 ========================== **Minor:** * Fix functions in continuous assignments. [Robert A. Clark] * Fix inlining of modules with 2-level deep outputs. Verilator 3.111 2003-09-15 ========================== **Minor:** * Fix declaration of functions before using that module. [Robert A. Clark] * Fix module inlining bug with outputs. Verilator 3.110 2003-09-12 ========================== **Major:** * Support Verilog 2001 style input/output declarations. [Robert A. Clark] * Support local vars in headers of function/tasks. [Leon Wildman] Verilator 3.109 2003-08-28 ========================== **Major:** * Support local variables in named begin blocks. [Leon Wildman] Verilator 3.108 2003-08-11 ========================== **Major:** * Support functions. **Minor:** * Signals 8 bits and shorter are now stored as chars instead of uint32_t's. This improves Dcache packing and improves performance by ~7%. * $display now usually results in a single VL_PRINT rather then many. * Optimize conditionals (?:) Verilator 3.107 2003-07-15 ========================== **Major:** * --private and --l2name are now the default, as this enables additional optimizations. Use --noprivate or --nol2name to get the older behavior. **Minor:** * Now support $display of binary and wide format data. * Add detection of incomplete case statements, and added related optimizations worth ~4%. * Work around flex bug in Redhat 8.0. [Eugene Weber] * Add some additional C++ reserved words. * Additional constant optimizations, ~5% speed improvement. Verilator 3.106 2003-06-17 ========================== **Major:** * $c can now take multiple expressions as arguments. For example $c("foo","bar(",32+1,");") will insert "foobar(33);" This makes it easier to pass the values of signals. * Several changes to support future versions that may have signal-eliminating optimizations. Users should try to use these switch on designs, they will become the default in later versions. * Add --private switch and /*verilator public*/ metacomment. This renames all signals so that compile errors will result if any signals referenced by C++ code are missing a /*verilator public*/ metacomment. * With --l2name, the second level cell C++ cell is now named "v". Previously it was named based on the name of the verilog code. This means to get to signals, scope to "{topcell} ->v ->{mysignal}" instead of "{topcell} ->{verilogmod}. {mysignal}". This allows different modules to be substituted for the cell without requiring source changes. **Minor:** * Several cleanups for Redhat 8.0. Verilator 3.105 2003-05-08 ========================== **Minor:** * Fix more GCC 3.2 errors. [David Black] Verilator 3.104 2003-04-30 ========================== **Major:** * Indicate direction of ports with VL_IN and VL_OUT. * Allow $c32, etc, to specify width of the $c statement for VCS. * Numerous performance improvements, worth about 25% **Minor:** * Fix false "indent underflow" error inside `systemc_ctor sections. * Fix missing ordering optimizations when outputs also used internally. * Assign constant cell pins in initial blocks rather then every cycle. * Promote subcell's combo logic to sequential evaluation when possible. * Fix GCC 3.2 compile errors. [Narayan Bhagavatula] Verilator 3.103 2003-01-28 ========================== **Minor:** * Fix missing model evaluation when clock generated several levels of hierarchy across from where it is used as a clock. [Richard Myers] * Fix sign-extension bug introduced in 3.102. Verilator 3.102 2003-01-24 ========================== **Minor:** * Fix sign-extension of X/Z's ("32'hx") Verilator 3.101 2003-01-13 ========================== **Minor:** * Fix 'parameter FOO=#'bXXXX' [Richard Myers] * Allow spaces inside numbers ("32'h 1234") [Sam Gladstone] Verilator 3.100 2002-12-23 ========================== **Major:** * Support for simple tasks w/o vars or I/O. [Richard Myers] **Minor:** * Ignore DOS carriage returns in Linux files. [Richard Myers] Verilator 3.012 2002-12-18 ========================== **Minor:** * Fix parsing bug with casex statements containing case items with bit extracts of parameters. [Richard Myers] * Fix bug which could cause writes of non-power-of-2 sized arrays to corrupt memory beyond the size of the array. [Dan Lussier] * Fix bug which did not detect UNOPT problems caused by submodules. See the description in the verilator man page. [John Deroo] * Fix compile with threaded Perl. [Ami Keren] Verilator 3.010 2002-11-03 ========================== **Major:** * Support SystemC 2.0.1. SystemPerl version 1.130 or newer is required. **Minor:** * Fix bug with inlined modules under other inlined modules. [Scott Bleiweiss] Verilator 3.005 2002-10-21 ========================== **Minor:** * Fix X's in case (not casex/z) to constant propagate correctly. * Fix missing include. [Kurachi] Verilator 3.004 2002-10-10 ========================== **Minor:** * Add module_inline metacomment and associated optimizations. * Allow coverage_block_off metacomment in place of `coverage_block_off. This prevents problems with Emacs AUTORESET. [Ray Strouble] * Fix `coverage_block_off also disabling subsequent blocks. * Fix unrolling of loops with multiple simple statements. * Fix compile warnings on newer GCC. [Kurachi] * Additional concatenation optimizations. Verilator 3.003 2002-09-13 ========================== **Minor:** * Now compiles on Windows 2000 with Cygwin. * Fix bug with pin assignments to wide memories. * Optimize wire assignments to constants. Verilator 3.002 2002-08-19 ========================== **Major:** * First public release of version 3. Verilator 3.000 2002-08-03 ========================== **Major:** * All new code base. Many changes too numerous to mention. **Minor:** * Approximately 4 times faster then Verilator 2. * Support initial statements * Support correct blocking/nonblocking assignments * Support `defines across multiple modules * Optimize call ordering, constant propagation, and dead code elimination. Verilator 2.1.8 2002-04-03 ========================== **Major:** * All applications must now link against include/verilated.cpp **Minor:** * Paths specified to verilator_make should be absolute, or be formed to allow for execution in the object directory (prepend ../ to each path.) This allows relative filenames for makes which hash and cache dependencies. * Add warning when parameter constants are too large. [John Deroo] * Add warning when x/?'s used in non-casez statements. * Add warning when blocking assignments used in posedge blocks. [Dan Lussier] * Split evaluation function into clocked and non-clocked, 20% perf gain. Verilator 2.1.5 2001-12-01 ========================== **Major:** * Add coverage analysis. In conjunction with SystemC provide line coverage reports, without SystemC, provide a hook to user written accumulation function. See --coverage option of verilator_make. **Minor:** * Relaxed multiply range checking * Support for constants up to 128 bits * Randomize values used when assigning to X's. * Add -guard option of internal testing. * Changed indentation in emitted code to be automatically generated. * Fix corruption of assignments of signal over 32 bits with non-0 lsb. Verilator 2.1.4 2001-11-16 ========================== **Major:** * Add $c("c_commands();"); for embedding arbitrary C code in Verilog. Verilator 2.1.3 2001-11-03 ========================== **Major:** * Support for parameters. Verilator 2.1.2 2001-10-25 ========================== **Major:** * Verilog Errors now reference the .v file rather then the .vpp file. **Minor:** * Support strings in assignments: reg [31:0] foo = "STRG"; * Support %m in format strings. Ripped out old $info support, use Verilog-Perl's vpm program instead. * Convert $stop to call of v_stop() which user can define. * Fix bug where a==b==c would have wrong precedence rule. * Fix bug where XNOR on odd-bit-widths (~^ or ^~) had bad value. Verilator 2.1.1 2001-05-17 ========================== **Major:** * New test_sp directory for System-Perl (SystemC) top level instantiation of the Verilated code, lower modules are still C++ code. (Experimental). * New test_spp directory for Pure System-Perl (SystemC) where every module is true SystemC code. (Experimental) **Minor:** * Input ports are now loaded by pointer reference into the sub-cell. This is faster on I-386 machines, as the stack must be used when there are a large number of parameters. Also, this simplifies debugging as the value of input ports exists for tracing. * Many code cleanups towards standard C++ style conventions. Verilator 2.1.0 2001-05-08 ========================== **Minor:** * Many code cleanups towards standard C++ style conventions. Version history lost ==================== Verilator 1.8 1996-07-08 ======================== [Versions 0 to 1.8 were by Paul Wasson] * Fix single bit in concat from instance output incorrect offset bug. Verilator 1.7 1996-05-20 ======================== * Mask unused bits of DONTCAREs. Verilator 1.6 1996-05-13 ======================== * Add fasttrace script Verilator 1.5 1996-01-09 ======================== * Pass structure pointer into translated code, so multiple instances can use same functions. * Fix static value concat on casex items. Verilator 1.1 1995-03-30 ======================== * Bug fixes, added verimake_partial script, performance improvements. Verilator 1.0c 1994-09-30 ========================= * Initial release of Verilator Verilator 0.0 1994-07-08 ======================== * First code written. .. ---------------------------------------------------------------------- Copyright ========= Copyright 2001-2025 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 verilator-5.042/.bake.toml0000644000542200017500000000111315101701376015763 0ustar mahmoudyfreeshell# mbake configuration file [formatter] # Indentation settings use_tabs = true tab_width = 2 # Spacing settings space_around_assignment = true space_before_colon = false space_after_colon = true # Line continuation settings normalize_line_continuations = true max_line_length = 100 # PHONY settings group_phony_declarations = false phony_at_top = false auto_insert_phony_declarations = false # General settings remove_trailing_whitespace = true ensure_final_newline = true normalize_empty_lines = true max_consecutive_empty_lines = 2 # Global settings debug = false verbose = false verilator-5.042/nodist/0000755000542200017500000000000015101701376015412 5ustar mahmoudyfreeshellverilator-5.042/nodist/fuzzer/0000755000542200017500000000000015101701376016737 5ustar mahmoudyfreeshellverilator-5.042/nodist/fuzzer/run0000755000542200017500000000125115101701376017470 0ustar mahmoudyfreeshell#!/bin/bash ###################################################################### # DESCRIPTION: Fuzzer run script # # Copyright 2019-2019 by Eric Rippey. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ###################################################################### # Actually do the fuzzing. Note that this will not terminate in any reasonable # amount of time. However, it will give updates on its progress. afl-fuzz -i in1 -o out1 -x dictionary ./wrapper --cc @@ verilator-5.042/nodist/fuzzer/setup_user0000755000542200017500000000204515101701376021064 0ustar mahmoudyfreeshell#!/bin/bash ###################################################################### # DESCRIPTION: Fuzzer setup to be run as a normal user # # Copyright 2019-2019 by Eric Rippey. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ###################################################################### # This is the portion of the setup for fuzzing that does not require root access. set -e # Build instrumented version of verilator pushd ../.. autoconf AFL_HARDEN=1 CXX=afl-g++ ./configure $(cd ..; pwd) make clean make -j $(ncpus) popd # Create a listing of likely snippets for the fuzzer to use. # Not essential, but makes things likely to be found faster. ./generate_dictionary # Set up input directory mkdir in1 echo "module m; initial \$display(\"Hello world!\n\"); endmodule" > in1/1.v # Compile wrapper program AFL_HARDEN=1 CXX=afl-g++ make wrapper verilator-5.042/nodist/fuzzer/generate_dictionary0000755000542200017500000000431515101701376022707 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # pylint: disable=C0103,C0114,C0115,C0116,C0321 ###################################################################### # DESCRIPTION: Fuzzer dictionary generator # # Copyright 2019-2019 by Eric Rippey. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU Lesser # General Public License Version 3 or the Perl Artistic License Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ###################################################################### # Attempts to pull a list of keywords out of the Flex input # These are then put in a dictionary of "interesting" sequences # This will be used to help the fuzzer pick interesting inputs more quickly. from subprocess import getstatusoutput from os import system def take_while(f, a): # any(a) => (a->bool)->[a]->[a] # Does the same think as Haskell's takewhile. out = [] for elem in a: if f(elem): out.append(elem) else: return out return out def skip_while(f, a): # any(a) => (a->bool)->[a]->[a] # Basically, the opposite thing from skipwhile while len(a) and f(a[0]): a = a[1:] return a def print_lines(a): # printable(a) => [a]->void for elem in a: print(elem) def write_file(filename, contents): # str->str->void with open(filename, "w", encoding="utf8") as fh: fh.write(contents) def parse_line(s): # str->maybe str if len(s) == 0: return None part = skip_while(lambda x: x != '"', s) if len(part) == 0 or part[0] != '"': return None literal_part = take_while(lambda x: x != '"', part[1:]) return ''.join(filter(lambda x: x != '\\', literal_part)) def main(): status, output = getstatusoutput('flex -T ../../src/verilog.l') assert status == 0 lines = output.splitlines() lines = take_while(lambda x: 'beginning dump of nfa' not in x, lines) tokens = set(filter(lambda x: x, map(parse_line, lines))) dirname = 'dictionary' r = system('mkdir -p ' + dirname) assert r == 0 for i, token in enumerate(tokens): write_file(dirname + '/' + str(i), token) if __name__ == '__main__': main() verilator-5.042/nodist/fuzzer/.gitignore0000644000542200017500000000004215101701376020723 0ustar mahmoudyfreeshellwrapper dictionary/ in* lex.yy.cc verilator-5.042/nodist/fuzzer/all0000755000542200017500000000122415101701376017434 0ustar mahmoudyfreeshell#!/bin/bash ###################################################################### # DESCRIPTION: Fuzzer one-line setup & run # # Copyright 2019-2019 by Eric Rippey. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ###################################################################### # Run all steps needed to configure and start fuzzer # Note that this assumes the system is a Debian-like Linux distribution set -e sudo ./setup_root ./setup_user ./run verilator-5.042/nodist/fuzzer/wrapper.cpp0000644000542200017500000000201115101701376021115 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // DESCRIPTION: Verilator fuzzing wrapper for verilator_bin // // Copyright 2019 by Eric Rippey. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 //************************************************************************* #include #include #include // The purpose of this script is to make sure that the results folder that // is generated by running verilator does not change the results of // subsequent runs. // This does slow down the execution to some degree but makes the results // more reliable. int main(int argc, char** argv, char** envp) { auto r = system("rm -rf obj_dir"); assert(r == 0); return execve("../../bin/verilator_bin", argv, envp); } verilator-5.042/nodist/fuzzer/actual_fail0000755000542200017500000000326615101701376021140 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # mypy: disallow-untyped-defs # pylint: disable=C0103,C0114,C0115,C0116,C0321,R0911 ###################################################################### # DESCRIPTION: Fuzzer result checker # # Copyright 2019-2019 by Eric Rippey. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU Lesser # General Public License Version 3 or the Perl Artistic License Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ###################################################################### # This script is designed to rerun examples to see whether they have # unexpected types of output besides the ones that afl-fuzz detects as # such. from glob import glob from subprocess import getstatusoutput from argparse import ArgumentParser def interesting(s: str) -> bool: if 'assert' in s: return True if 'Assert' in s: return True if 'Aborted' in s: return True if 'terminate' in s: if 'unterminated' in s: return False return True if 'Segmentation' in s: return True if 'internal error' in s: return True return False def main() -> None: p = ArgumentParser() p.add_argument('--dir', default='out1/queue') args = p.parse_args() for infile in glob(args.dir + '/*'): # Input filenames are known not to contain spaces or other unusual # characters, therefore this works. status, output = getstatusoutput('../../bin/verilator_bin --cc ' + infile) if interesting(output): print(infile) print(status) print(output) if __name__ == '__main__': main() verilator-5.042/nodist/fuzzer/setup_root0000755000542200017500000000156015101701376021072 0ustar mahmoudyfreeshell#!/bin/bash ###################################################################### # DESCRIPTION: Fuzzer setup to be run as root # # Copyright 2019-2019 by Eric Rippey. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ###################################################################### # This is the portion of the fuzzer setup that must be run as root. # Note that this assumes a Debian-like distribution. set -e # Get dependencies apt-get install afl mdm apt-get build-dep verilator # Run a couple pieces of setup which should speed up the fuzzer echo core >/proc/sys/kernel/core_pattern cd /sys/devices/system/cpu echo performance | tee cpu*/cpufreq/scaling_governor verilator-5.042/nodist/fastcov.py0000755000542200017500000013773715101701376017456 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # SPDX-License-Identifier: MIT # Copyright 2018-present, Bryan Gillespie """ Author: Bryan Gillespie https://github.com/RPGillespie6/fastcov A massively parallel gcov wrapper for generating intermediate coverage formats fast The goal of fastcov is to generate code coverage intermediate formats as fast as possible, even for large projects with hundreds of gcda objects. The intermediate formats may then be consumed by a report generator such as lcov's genhtml, or a dedicated frontend such as coveralls. Sample Usage: $ cd build_dir $ ./fastcov.py --zerocounters $ $ ./fastcov.py --exclude /usr/include test/ --lcov -o report.info $ genhtml -o code_coverage report.info """ import re import os import sys import glob import json import time import fnmatch import logging import argparse import threading import subprocess import multiprocessing from pathlib import Path FASTCOV_VERSION = (1,17) MINIMUM_PYTHON = (3,5) MINIMUM_GCOV = (9,0,0) # Interesting metrics START_TIME = time.monotonic() GCOVS_TOTAL = 0 GCOVS_SKIPPED = 0 # Gcov Coverage File Extensions GCOV_GCNO_EXT = ".gcno" # gcno = "[gc]ov [no]te" GCOV_GCDA_EXT = ".gcda" # gcda = "[gc]ov [da]ta" # For when things go wrong... # Start error codes at 3 because 1-2 are special # See https://stackoverflow.com/a/1535733/2516916 EXIT_CODE = 0 EXIT_CODES = { "gcov_version": 3, "python_version": 4, "unsupported_coverage_format": 5, "excl_not_found": 6, "bad_chunk_file": 7, "missing_json_key": 8, "no_coverage_files": 9, } # Disable all logging in case developers are using this as a module logging.disable(level=logging.CRITICAL) class FastcovFormatter(logging.Formatter): def format(self, record): record.levelname = record.levelname.lower() log_message = super(FastcovFormatter, self).format(record) return "[{:.3f}s] {}".format(stopwatch(), log_message) class DiffParseError(Exception): pass class DiffParser(object): def _refinePaths(self, diff_metadata, diff_base_dir): diff_metadata.pop('/dev/null', None) diff_metadata.pop('', None) for key, value in diff_metadata.copy().items(): diff_metadata.pop(key) #sources without added lines will be excluded if value: newpath = os.path.join(diff_base_dir, key) if diff_base_dir else os.path.abspath(key) diff_metadata[newpath] = value def _parseTargetFile(self, line_with_target_file): #f.e. '+++ b/README.md1' or '+++ b/README.md1 timestamp' target_source = line_with_target_file[4:].partition('\t')[0].strip() target_source = target_source[2:] if target_source.startswith('b/') else target_source return target_source def _parseHunkBoundaries(self, line_with_hunk_boundaries, line_index): #f.e. '@@ -121,4 +122,4 @@ Time to process all gcda and parse all gcov:' # Here ['-121,4', '+122,4'] lines_info = line_with_hunk_boundaries[3:].partition("@@")[0].strip().split(' ') if len(lines_info) != 2: raise DiffParseError("Found invalid hunk. Line #{}. {}".format(line_index, line_with_hunk_boundaries)) # Here ['122','4'] target_lines_info = lines_info[1].strip('+').partition(',') target_line_current = int(target_lines_info[0]) target_lines_count = int(target_lines_info[2]) if target_lines_info[2] else 1 # Here ['121','4'] source_lines_info = lines_info[0].strip('-').partition(',') source_line_current = int(source_lines_info[0]) source_lines_count = int(source_lines_info[2]) if source_lines_info[2] else 1 return target_line_current, target_lines_count, source_line_current, source_lines_count def parseDiffFile(self, diff_file, diff_base_dir, fallback_encodings=[]): diff_metadata = {} target_source = None target_hunk = set() target_line_current = 0 target_line_end = 0 source_line_current = 0 source_line_end = 0 found_hunk = False for i, line in enumerate(getSourceLines(diff_file, fallback_encodings), 1): line = line.rstrip() if not found_hunk: if line.startswith('+++ '): # refresh file target_source = self._parseTargetFile(line) elif line.startswith('@@ '): # refresh hunk target_line_current, target_lines_count, source_line_current, source_lines_count = self._parseHunkBoundaries(line, i) target_line_end = target_line_current + target_lines_count source_line_end = source_line_current + source_lines_count target_hunk = set() found_hunk = True continue if target_line_current > target_line_end or source_line_current > source_line_end: raise DiffParseError("Hunk longer than expected. Line #{}. {}".format(i, line)) if line.startswith('+'): #line related to target target_hunk.add(target_line_current) target_line_current = target_line_current + 1 elif line.startswith(' ') or line == '': # line related to both target_line_current = target_line_current + 1 source_line_current = source_line_current + 1 elif line.startswith('-'): # line related to source source_line_current = source_line_current + 1 elif not line.startswith('\\'): # No newline at end of file # line with newline marker is not included into any boundaries raise DiffParseError("Found unrecognized hunk line type. Line #{}. {}".format(i, line)) if target_line_current == target_line_end and source_line_current == source_line_end: # Checked all lines, save data if target_source in diff_metadata: diff_metadata[target_source] = target_hunk.union(diff_metadata[target_source]) else: diff_metadata[target_source] = target_hunk target_hunk = set() found_hunk = False if target_line_current != target_line_end or source_line_current != source_line_end: raise DiffParseError("Unexpected end of file. Expected hunk with {} target lines, {} source lines".format( target_line_end - target_line_current, source_line_end - source_line_current)) self._refinePaths(diff_metadata, diff_base_dir) return diff_metadata def filterByDiff(self, diff_file, dir_base_dir, fastcov_json, fallback_encodings=[]): diff_metadata = self.parseDiffFile(diff_file, dir_base_dir, fallback_encodings) logging.debug("Include only next files: {}".format(diff_metadata.keys())) excluded_files_count = 0 excluded_lines_count = 0 for source in list(fastcov_json["sources"].keys()): diff_lines = diff_metadata.get(source, None) if not diff_lines: excluded_files_count = excluded_files_count + 1 logging.debug("Exclude {} according to diff file".format(source)) fastcov_json["sources"].pop(source) continue for test_name, report_data in fastcov_json["sources"][source].copy().items(): #No info about functions boundaries, removing all for function in list(report_data["functions"].keys()): report_data["functions"].pop(function, None) for line in list(report_data["lines"].keys()): if line not in diff_lines: excluded_lines_count = excluded_lines_count + 1 report_data["lines"].pop(line) for branch_line in list(report_data["branches"].keys()): if branch_line not in diff_lines: report_data["branches"].pop(branch_line) if len(report_data["lines"]) == 0: fastcov_json["sources"][source].pop(test_name) if len(fastcov_json["sources"][source]) == 0: excluded_files_count = excluded_files_count + 1 logging.debug('Exclude {} file as it has no lines due to diff filter'.format(source)) fastcov_json["sources"].pop(source) logging.info("Excluded {} files and {} lines according to diff file".format(excluded_files_count, excluded_lines_count)) return fastcov_json def chunks(l, n): """Yield successive n-sized chunks from l.""" for i in range(0, len(l), n): yield l[i:i + n] def setExitCode(key): global EXIT_CODE EXIT_CODE = EXIT_CODES[key] def setExitCodeRaw(code): global EXIT_CODE EXIT_CODE = code def incrementCounters(total, skipped): global GCOVS_TOTAL global GCOVS_SKIPPED GCOVS_TOTAL += total GCOVS_SKIPPED += skipped def stopwatch(): """Return number of seconds since last time this was called.""" global START_TIME end_time = time.monotonic() delta = end_time - START_TIME START_TIME = end_time return delta def parseVersionFromLine(version_str): """Given a string containing a dotted integer version, parse out integers and return as tuple.""" version = re.search(r'(\d+\.\d+\.\d+)', version_str) if not version: return (0,0,0) return tuple(map(int, version.group(1).split("."))) def getGcovVersion(gcov): p = subprocess.Popen([gcov, "-v"], stdout=subprocess.PIPE) output = p.communicate()[0].decode('UTF-8') p.wait() return parseVersionFromLine(output.split("\n")[0]) def tryParseNumber(s): try: return int(s) except ValueError: # Log a warning if not hyphen if s != "-": logging.warning("Unsupported numerical value '%s', using 0", s) # Default to 0 if we can't parse the number (e.g. "-", "NaN", etc.) return 0 def removeFiles(files): for file in files: os.remove(file) def processPrefix(path, prefix, prefix_strip): p = Path(path) if p.exists() or not p.is_absolute(): return path if prefix_strip > 0: segments = p.parts if len(segments) < prefix_strip + 1: logging.warning("Couldn't strip %i path levels from %s.", prefix_strip, path) return path segments = segments[prefix_strip+1:] p = Path(segments[0]) segments = segments[1:] for s in segments: p = p.joinpath(s) if len(prefix) > 0: if p.is_absolute(): p = Path(prefix).joinpath(p.relative_to('/')) else: p = Path(prefix).joinpath(p) return str(p) def getFilteredCoverageFiles(coverage_files, exclude): def excludeGcda(gcda): for ex in exclude: if ex in gcda: logging.debug("Omitting %s due to '--exclude-gcda %s'", gcda, ex) return False return True return list(filter(excludeGcda, coverage_files)) def globCoverageFiles(cwd, coverage_type): return glob.glob(os.path.join(os.path.abspath(cwd), "**/*" + coverage_type), recursive=True) def findCoverageFiles(cwd, coverage_files, use_gcno): coverage_type = "user provided" if not coverage_files: # gcov strips off extension of whatever you pass it and searches [extensionless name] + .gcno/.gcda # We should pass either gcno or gcda, but not both - if you pass both it will be processed twice coverage_type = GCOV_GCNO_EXT if use_gcno else GCOV_GCDA_EXT coverage_files = globCoverageFiles(cwd, coverage_type) logging.info("Found {} coverage files ({})".format(len(coverage_files), coverage_type)) logging.debug("Coverage files found:\n %s", "\n ".join(coverage_files)) return coverage_files def gcovWorker(data_q, metrics_q, args, chunk, gcov_filter_options): base_report = {"sources": {}} gcovs_total = 0 gcovs_skipped = 0 error_exit = False gcov_bin = args.gcov gcov_args = ["--json-format", "--stdout"] if args.branchcoverage or args.xbranchcoverage: gcov_args.append("--branch-probabilities") encoding = sys.stdout.encoding if sys.stdout.encoding else 'UTF-8' workdir = args.cdirectory if args.cdirectory else "." p = subprocess.Popen([gcov_bin] + gcov_args + chunk, cwd=workdir, stdout=subprocess.PIPE, stderr=subprocess.DEVNULL) for i, line in enumerate(iter(p.stdout.readline, b'')): try: intermediate_json = json.loads(line.decode(encoding)) except json.decoder.JSONDecodeError as e: logging.error("Could not process chunk file '{}' ({}/{})".format(chunk[i], i+1, len(chunk))) logging.error(str(e)) setExitCode("bad_chunk_file") continue if "current_working_directory" not in intermediate_json: logging.error("Missing 'current_working_directory' for data file: {}".format(intermediate_json)) setExitCode("missing_json_key") continue intermediate_json_files = processGcovs(args.cdirectory, intermediate_json["files"], intermediate_json["current_working_directory"], gcov_filter_options) for f in intermediate_json_files: distillSource(f, base_report["sources"], args.test_name, args.xbranchcoverage) gcovs_total += len(intermediate_json["files"]) gcovs_skipped += len(intermediate_json["files"]) - len(intermediate_json_files) p.wait() data_q.put(base_report) metrics_q.put((gcovs_total, gcovs_skipped)) sys.exit(EXIT_CODE) def processGcdas(args, coverage_files, gcov_filter_options): chunk_size = max(args.minimum_chunk, int(len(coverage_files) / args.jobs) + 1) processes = [] data_q = multiprocessing.Queue() metrics_q = multiprocessing.Queue() for chunk in chunks(coverage_files, chunk_size): p = multiprocessing.Process(target=gcovWorker, args=(data_q, metrics_q, args, chunk, gcov_filter_options)) processes.append(p) p.start() logging.info("Spawned {} gcov processes, each processing at most {} coverage files".format(len(processes), chunk_size)) fastcov_jsons = [] for p in processes: fastcov_jsons.append(data_q.get()) incrementCounters(*metrics_q.get()) for p in processes: p.join() if p.exitcode != 0: setExitCodeRaw(p.exitcode) base_fastcov = fastcov_jsons.pop() for fj in fastcov_jsons: combineReports(base_fastcov, fj) return base_fastcov def shouldFilterSource(source, gcov_filter_options): """Returns true if the provided source file should be filtered due to CLI options, otherwise returns false.""" # If explicit sources were passed, check for match if gcov_filter_options["sources"]: if source not in gcov_filter_options["sources"]: logging.debug("Filtering coverage for '%s' due to option '--source-files'", source) return True # Check exclude filter for ex in gcov_filter_options["exclude"]: if ex in source: logging.debug("Filtering coverage for '%s' due to option '--exclude %s'", source, ex) return True # Check exclude filter for ex_glob in gcov_filter_options["exclude_glob"]: if fnmatch.fnmatch(source, ex_glob): logging.debug("Filtering coverage for '%s' due to option '--exclude-glob %s'", source, ex_glob) return True # Check include filter if gcov_filter_options["include"]: included = False for inc in gcov_filter_options["include"]: if inc in source: included = True break if not included: logging.debug("Filtering coverage for '%s' due to option '--include %s'", source, " ".join(gcov_filter_options["include"])) return True return False def filterFastcov(fastcov_json, args): logging.info("Performing filtering operations (if applicable)") gcov_filter_options = getGcovFilterOptions(args) for source in list(fastcov_json["sources"].keys()): if shouldFilterSource(source, gcov_filter_options): del fastcov_json["sources"][source] def processGcov(cwd, gcov, source_base_dir, files, gcov_filter_options): # Uses cwd if set, else source_base_dir from gcov json. If both are empty, uses "." base_dir = cwd if cwd else source_base_dir base_dir = base_dir if base_dir else "." # Add absolute path gcov["file_abs"] = os.path.abspath(os.path.join(base_dir, gcov["file"])) if shouldFilterSource(gcov["file_abs"], gcov_filter_options): return files.append(gcov) logging.debug("Accepted coverage for '%s'", gcov["file_abs"]) def processGcovs(cwd, gcov_files, source_base_dir, gcov_filter_options): files = [] for gcov in gcov_files: processGcov(cwd, gcov, source_base_dir, files, gcov_filter_options) return files def dumpBranchCoverageToLcovInfo(f, branches): branch_miss = 0 branch_found = 0 brda = [] for line_num, branch_counts in branches.items(): for i, count in enumerate(branch_counts): # Branch (, , , ) brda.append((line_num, int(i/2), i, count)) branch_miss += int(count == 0) branch_found += 1 for v in sorted(brda): f.write("BRDA:{},{},{},{}\n".format(*v)) f.write("BRF:{}\n".format(branch_found)) # Branches Found f.write("BRH:{}\n".format(branch_found - branch_miss)) # Branches Hit def dumpToLcovInfo(fastcov_json, output): with open(output, "w") as f: sources = fastcov_json["sources"] for sf in sorted(sources.keys()): for tn in sorted(sources[sf].keys()): data = sources[sf][tn] f.write("TN:{}\n".format(tn)) #Test Name - used mainly in conjuction with genhtml --show-details f.write("SF:{}\n".format(sf)) #Source File fn_miss = 0 fn = [] fnda = [] for function, fdata in data["functions"].items(): fn.append((fdata["start_line"], function)) # Function Start Line fnda.append((fdata["execution_count"], function)) # Function Hits fn_miss += int(fdata["execution_count"] == 0) # NOTE: lcov sorts FN, but not FNDA. for v in sorted(fn): f.write("FN:{},{}\n".format(*v)) for v in sorted(fnda): f.write("FNDA:{},{}\n".format(*v)) f.write("FNF:{}\n".format(len(data["functions"]))) #Functions Found f.write("FNH:{}\n".format((len(data["functions"]) - fn_miss))) #Functions Hit if data["branches"]: dumpBranchCoverageToLcovInfo(f, data["branches"]) line_miss = 0 da = [] for line_num, count in data["lines"].items(): da.append((line_num, count)) line_miss += int(count == 0) for v in sorted(da): f.write("DA:{},{}\n".format(*v)) # Line f.write("LF:{}\n".format(len(data["lines"]))) #Lines Found f.write("LH:{}\n".format((len(data["lines"]) - line_miss))) #Lines Hit f.write("end_of_record\n") def getSourceLines(source, fallback_encodings=[]): """Return a list of lines from the provided source, trying to decode with fallback encodings if the default fails.""" default_encoding = sys.getdefaultencoding() for encoding in [default_encoding] + fallback_encodings: try: with open(source, encoding=encoding) as f: return f.readlines() except UnicodeDecodeError: pass logging.warning("Could not decode '{}' with {} or fallback encodings ({}); ignoring errors".format(source, default_encoding, ",".join(fallback_encodings))) with open(source, errors="ignore") as f: return f.readlines() def containsMarker(markers, strBody): for marker in markers: if marker in strBody: return True return False # Returns whether source coverage changed or not def exclProcessSource(fastcov_sources, source, exclude_branches_sw, include_branches_sw, exclude_line_marker, fallback_encodings, gcov_prefix, gcov_prefix_strip): source_to_open = processPrefix(source, gcov_prefix, gcov_prefix_strip) # Before doing any work, check if this file even needs to be processed if not exclude_branches_sw and not include_branches_sw: # Ignore unencodable characters with open(source_to_open, errors="ignore") as f: if not containsMarker(exclude_line_marker + ["LCOV_EXCL"], f.read()): return False # If we've made it this far we have to check every line start_line = 0 end_line = 0 # Start enumeration at line 1 because the first line of the file is line 1 not 0 for i, line in enumerate(getSourceLines(source_to_open, fallback_encodings), 1): # Cycle through test names (likely only 1) for test_name in fastcov_sources[source]: fastcov_data = fastcov_sources[source][test_name] # Check if branch coverage should be deleted based on CLI options if (exclude_branches_sw or include_branches_sw) and (i in fastcov_data["branches"]): del_exclude_br = exclude_branches_sw and any(line.lstrip().startswith(e) for e in exclude_branches_sw) del_include_br = include_branches_sw and all(not line.lstrip().startswith(e) for e in include_branches_sw) if del_exclude_br or del_include_br: del fastcov_data["branches"][i] # Skip to next line as soon as possible if not containsMarker(exclude_line_marker + ["LCOV_EXCL"], line): continue # Build line to function dict so can quickly delete by line number line_to_func = {} for f in fastcov_data["functions"].keys(): l = fastcov_data["functions"][f]["start_line"] if l not in line_to_func: line_to_func[l] = set() line_to_func[l].add(f) if any(marker in line for marker in exclude_line_marker): for key in ["lines", "branches"]: if i in fastcov_data[key]: del fastcov_data[key][i] if i in line_to_func: for key in line_to_func[i]: if key in fastcov_data["functions"]: del fastcov_data["functions"][key] elif "LCOV_EXCL_START" in line: start_line = i elif "LCOV_EXCL_STOP" in line: end_line = i if not start_line: end_line = 0 continue for key in ["lines", "branches"]: for line_num in list(fastcov_data[key].keys()): if start_line <= line_num <= end_line: del fastcov_data[key][line_num] for line_num in range(start_line, end_line): if line_num in line_to_func: for key in line_to_func[line_num]: if key in fastcov_data["functions"]: del fastcov_data["functions"][key] start_line = end_line = 0 elif "LCOV_EXCL_BR_LINE" in line: if i in fastcov_data["branches"]: del fastcov_data["branches"][i] # Source coverage changed return True def exclMarkerWorker(data_q, fastcov_sources, chunk, exclude_branches_sw, include_branches_sw, exclude_line_marker, fallback_encodings, gcov_prefix, gcov_prefix_strip): changed_sources = [] for source in chunk: try: if exclProcessSource(fastcov_sources, source, exclude_branches_sw, include_branches_sw, exclude_line_marker, fallback_encodings, gcov_prefix, gcov_prefix_strip): changed_sources.append((source, fastcov_sources[source])) except FileNotFoundError: logging.error("Could not find '%s' to scan for exclusion markers...", source) setExitCode("excl_not_found") # Set exit code because of error # Write out changed sources back to main fastcov file data_q.put(changed_sources) # Exit current process with appropriate code sys.exit(EXIT_CODE) def processExclusionMarkers(fastcov_json, jobs, exclude_branches_sw, include_branches_sw, exclude_line_marker, min_chunk_size, fallback_encodings, gcov_prefix, gcov_prefix_strip): chunk_size = max(min_chunk_size, int(len(fastcov_json["sources"]) / jobs) + 1) processes = [] data_q = multiprocessing.Queue() for chunk in chunks(list(fastcov_json["sources"].keys()), chunk_size): p = multiprocessing.Process(target=exclMarkerWorker, args=(data_q, fastcov_json["sources"], chunk, exclude_branches_sw, include_branches_sw, exclude_line_marker, fallback_encodings, gcov_prefix, gcov_prefix_strip)) processes.append(p) p.start() logging.info("Spawned {} exclusion marker scanning processes, each processing at most {} source files".format(len(processes), chunk_size)) changed_sources = [] for p in processes: changed_sources += data_q.get() for p in processes: p.join() if p.exitcode != 0: setExitCodeRaw(p.exitcode) for changed_source in changed_sources: fastcov_json["sources"][changed_source[0]] = changed_source[1] def validateSources(fastcov_json, gcov_prefix, gcov_prefix_strip): logging.info("Checking if all sources exist") for source in fastcov_json["sources"].keys(): source = processPrefix(source, gcov_prefix, gcov_prefix_strip) if not os.path.exists(source): logging.error("Cannot find '{}'".format(source)) def distillFunction(function_raw, functions): function_name = function_raw["name"] # NOTE: need to explicitly cast all counts coming from gcov to int - this is because gcov's json library # will pass as scientific notation (i.e. 12+e45) start_line = int(function_raw["start_line"]) execution_count = int(function_raw["execution_count"]) if function_name not in functions: functions[function_name] = { "start_line": start_line, "execution_count": execution_count } else: functions[function_name]["execution_count"] += execution_count def emptyBranchSet(branch1, branch2): return (branch1["count"] == 0 and branch2["count"] == 0) def matchingBranchSet(branch1, branch2): return (branch1["count"] == branch2["count"]) def filterExceptionalBranches(branches): filtered_branches = [] exception_branch = False for i in range(0, len(branches), 2): if i+1 >= len(branches): filtered_branches.append(branches[i]) break # Filter exceptional branch noise if branches[i+1]["throw"]: exception_branch = True continue # Filter initializer list noise if exception_branch and emptyBranchSet(branches[i], branches[i+1]) and len(filtered_branches) >= 2 and matchingBranchSet(filtered_branches[-1], filtered_branches[-2]): return [] filtered_branches.append(branches[i]) filtered_branches.append(branches[i+1]) return filtered_branches def distillLine(line_raw, lines, branches, include_exceptional_branches): line_number = int(line_raw["line_number"]) count = int(line_raw["count"]) if count < 0: if "function_name" in line_raw: logging.warning("Ignoring negative count found in '%s'.", line_raw["function_name"]) else: logging.warning("Ignoring negative count.") count = 0 if line_number not in lines: lines[line_number] = count else: lines[line_number] += count # Filter out exceptional branches by default unless requested otherwise if not include_exceptional_branches: line_raw["branches"] = filterExceptionalBranches(line_raw["branches"]) # Increment all branch counts for i, branch in enumerate(line_raw["branches"]): if line_number not in branches: branches[line_number] = [] blen = len(branches[line_number]) glen = len(line_raw["branches"]) if blen < glen: branches[line_number] += [0] * (glen - blen) branches[line_number][i] += int(branch["count"]) def distillSource(source_raw, sources, test_name, include_exceptional_branches): source_name = source_raw["file_abs"] if source_name not in sources: sources[source_name] = { test_name: { "functions": {}, "branches": {}, "lines": {} } } for function in source_raw["functions"]: distillFunction(function, sources[source_name][test_name]["functions"]) for line in source_raw["lines"]: distillLine(line, sources[source_name][test_name]["lines"], sources[source_name][test_name]["branches"], include_exceptional_branches) def dumpToJson(intermediate, output): with open(output, "w") as f: json.dump(intermediate, f) def getGcovFilterOptions(args): return { "sources": set([os.path.abspath(s) for s in args.sources]), #Make paths absolute, use set for fast lookups "include": args.includepost, "exclude": args.excludepost, "exclude_glob":args.excludepost_glob } def addDicts(dict1, dict2): """Add dicts together by value. i.e. addDicts({"a":1,"b":0}, {"a":2}) == {"a":3,"b":0}.""" result = {k:v for k,v in dict1.items()} for k,v in dict2.items(): if k in result: result[k] += v else: result[k] = v return result def addLists(list1, list2): """Add lists together by value. i.e. addLists([1,1], [2,2]) == [3,3].""" # Find big list and small list blist, slist = list(list2), list(list1) if len(list1) > len(list2): blist, slist = slist, blist # Overlay small list onto big list for i, b in enumerate(slist): blist[i] += b return blist def combineReports(base, overlay): for source, scov in overlay["sources"].items(): # Combine Source Coverage if source not in base["sources"]: base["sources"][source] = scov continue for test_name, tcov in scov.items(): # Combine Source Test Name Coverage if test_name not in base["sources"][source]: base["sources"][source][test_name] = tcov continue # Drill down and create convenience variable base_data = base["sources"][source][test_name] # Combine Line Coverage base_data["lines"] = addDicts(base_data["lines"], tcov["lines"]) # Combine Branch Coverage for branch, cov in tcov["branches"].items(): if branch not in base_data["branches"]: base_data["branches"][branch] = cov else: base_data["branches"][branch] = addLists(base_data["branches"][branch], cov) # Combine Function Coverage for function, cov in tcov["functions"].items(): if function not in base_data["functions"]: base_data["functions"][function] = cov else: base_data["functions"][function]["execution_count"] += cov["execution_count"] def parseInfo(path): """Parse an lcov .info file into fastcov json.""" fastcov_json = { "sources": {} } with open(path) as f: current_test_name = "" for line in f: if line.startswith("TN:"): current_test_name = line[3:].strip() elif line.startswith("SF:"): current_sf = line[3:].strip() fastcov_json["sources"].setdefault(current_sf, { current_test_name: { "functions": {}, "branches": {}, "lines": {}, } }) current_data = fastcov_json["sources"][current_sf][current_test_name] elif line.startswith("FN:"): line_nums, function_name = line[3:].strip().rsplit(",", maxsplit=1) line_num_start = line_nums.split(",")[0] current_data["functions"][function_name] = {} current_data["functions"][function_name]["start_line"] = tryParseNumber(line_num_start) elif line.startswith("FNDA:"): count, function_name = line[5:].strip().split(",") current_data["functions"][function_name]["execution_count"] = tryParseNumber(count) elif line.startswith("DA:"): line_num, count = line[3:].strip().split(",") current_data["lines"][line_num] = tryParseNumber(count) elif line.startswith("BRDA:"): branch_tokens = line[5:].strip().split(",") line_num, count = branch_tokens[0], branch_tokens[-1] if line_num not in current_data["branches"]: current_data["branches"][line_num] = [] current_data["branches"][line_num].append(tryParseNumber(count)) return fastcov_json def convertKeysToInt(report): for source in report["sources"].keys(): for test_name in report["sources"][source].keys(): report_data = report["sources"][source][test_name] report_data["lines"] = {int(k):v for k,v in report_data["lines"].items()} report_data["branches"] = {int(k):v for k,v in report_data["branches"].items()} def parseAndCombine(paths): base_report = {} for path in paths: if path.endswith(".json"): with open(path) as f: report = json.load(f) elif path.endswith(".info"): report = parseInfo(path) else: logging.error("Currently only fastcov .json and lcov .info supported for combine operations, aborting due to %s...\n", path) sys.exit(EXIT_CODES["unsupported_coverage_format"]) # In order for sorting to work later when we serialize, # make sure integer keys are int convertKeysToInt(report) if not base_report: base_report = report logging.info("Setting {} as base report".format(path)) else: combineReports(base_report, report) logging.info("Adding {} to base report".format(path)) return base_report def getCombineCoverage(args): logging.info("Performing combine operation") fastcov_json = parseAndCombine(args.combine) filterFastcov(fastcov_json, args) return fastcov_json def getGcovCoverage(args): # Need at least python 3.5 because of use of recursive glob checkPythonVersion(sys.version_info[0:2]) # Need at least gcov 9.0.0 because that's when gcov JSON and stdout streaming was introduced checkGcovVersion(getGcovVersion(args.gcov)) # Get list of gcda files to process coverage_files = findCoverageFiles(args.directory, args.coverage_files, args.use_gcno) # If gcda/gcno filtering is enabled, filter them out now if args.excludepre: coverage_files = getFilteredCoverageFiles(coverage_files, args.excludepre) logging.info("Found {} coverage files after filtering".format(len(coverage_files))) # We "zero" the "counters" by simply deleting all gcda files if args.zerocounters: removeFiles(globCoverageFiles(args.directory, GCOV_GCDA_EXT)) logging.info("Removed {} .gcda files".format(len(coverage_files))) sys.exit() if not coverage_files: logging.error("No coverage files found in directory '%s'", args.directory) setExitCode("no_coverage_files") sys.exit(EXIT_CODE) # Fire up one gcov per cpu and start processing gcdas gcov_filter_options = getGcovFilterOptions(args) fastcov_json = processGcdas(args, coverage_files, gcov_filter_options) # Summarize processing results logging.info("Processed {} .gcov files ({} total, {} skipped)".format(GCOVS_TOTAL - GCOVS_SKIPPED, GCOVS_TOTAL, GCOVS_SKIPPED)) logging.debug("Final report will contain coverage for the following %d source files:\n %s", len(fastcov_json["sources"]), "\n ".join(fastcov_json["sources"])) return fastcov_json def formatCoveredItems(covered, total): coverage = (covered * 100.0) / total if total > 0 else 100.0 coverage = round(coverage, 2) return "{:.2f}%, {}/{}".format(coverage, covered, total) def dumpStatistic(fastcov_json): total_lines = 0 covered_lines = 0 total_functions = 0 covered_functions = 0 total_files = len(fastcov_json["sources"]) covered_files = 0 for source_name, source in fastcov_json["sources"].items(): is_file_covered = False for test_name, test in source.items(): total_lines += len(test["lines"]) for execution_count in test["lines"].values(): covered_lines += 1 if execution_count > 0 else 0 is_file_covered = is_file_covered or execution_count > 0 total_functions += len(test["functions"]) for function in test["functions"].values(): covered_functions += 1 if function['execution_count'] > 0 else 0 is_file_covered = is_file_covered or function['execution_count'] > 0 if is_file_covered: covered_files = covered_files + 1 logging.info("Files Coverage: {}".format(formatCoveredItems(covered_files, total_files))) logging.info("Functions Coverage: {}".format(formatCoveredItems(covered_functions, total_functions))) logging.info("Lines Coverage: {}".format(formatCoveredItems(covered_lines, total_lines))) def dumpFile(fastcov_json, args): if args.lcov: dumpToLcovInfo(fastcov_json, args.output) logging.info("Created lcov info file '{}'".format(args.output)) else: dumpToJson(fastcov_json, args.output) logging.info("Created fastcov json file '{}'".format(args.output)) if args.dump_statistic: dumpStatistic(fastcov_json) def tupleToDotted(tup): return ".".join(map(str, tup)) def parseArgs(): parser = argparse.ArgumentParser(description='A parallel gcov wrapper for fast coverage report generation') parser.add_argument('-z', '--zerocounters', dest='zerocounters', action="store_true", help='Recursively delete all gcda files') # Enable Branch Coverage parser.add_argument('-b', '--branch-coverage', dest='branchcoverage', action="store_true", help='Include only the most useful branches in the coverage report.') parser.add_argument('-B', '--exceptional-branch-coverage', dest='xbranchcoverage', action="store_true", help='Include ALL branches in the coverage report (including potentially noisy exceptional branches).') parser.add_argument('-A', '--exclude-br-lines-starting-with', dest='exclude_branches_sw', nargs="+", metavar='', default=[], help='Exclude branches from lines starting with one of the provided strings (i.e. assert, return, etc.)') parser.add_argument('-a', '--include-br-lines-starting-with', dest='include_branches_sw', nargs="+", metavar='', default=[], help='Include only branches from lines starting with one of the provided strings (i.e. if, else, while, etc.)') parser.add_argument('-X', '--skip-exclusion-markers', dest='skip_exclusion_markers', action="store_true", help='Skip reading source files to search for lcov exclusion markers (such as "LCOV_EXCL_LINE")') parser.add_argument('-x', '--scan-exclusion-markers', dest='scan_exclusion_markers', action="store_true", help='(Combine operations) Force reading source files to search for lcov exclusion markers (such as "LCOV_EXCL_LINE")') # Capture untested file coverage as well via gcno parser.add_argument('-n', '--process-gcno', dest='use_gcno', action="store_true", help='Process both gcno and gcda coverage files. This option is useful for capturing untested files in the coverage report.') # Filtering Options parser.add_argument('-s', '--source-files', dest='sources', nargs="+", metavar='', default=[], help='Filter: Specify exactly which source files should be included in the final report. Paths must be either absolute or relative to current directory.') parser.add_argument('-e', '--exclude', dest='excludepost', nargs="+", metavar='', default=[], help='Filter: Exclude source files from final report if they contain one of the provided substrings (i.e. /usr/include test/, etc.)') parser.add_argument('-eg', '--exclude-glob', dest='excludepost_glob', nargs="+", metavar='', default=[], help='Filter: Exclude source files by glob pattern from final report if they contain one of the provided substrings (i.e. /usr/include test/, etc.)') parser.add_argument('-i', '--include', dest='includepost', nargs="+", metavar='', default=[], help='Filter: Only include source files in final report that contain one of the provided substrings (i.e. src/ etc.)') parser.add_argument('-f', '--gcda-files', dest='coverage_files', nargs="+", metavar='', default=[], help='Filter: Specify exactly which gcda or gcno files should be processed. Note that specifying gcno causes both gcno and gcda to be processed.') parser.add_argument('-E', '--exclude-gcda', dest='excludepre', nargs="+", metavar='', default=[], help='Filter: Exclude gcda or gcno files from being processed via simple find matching (not regex)') parser.add_argument('-u', '--diff-filter', dest='diff_file', default='', help='Unified diff file with changes which will be included into final report') parser.add_argument('-ub', '--diff-base-dir', dest='diff_base_dir', default='', help='Base directory for sources in unified diff file, usually repository dir') parser.add_argument('-ce', '--custom-exclusion-marker', dest='exclude_line_marker', nargs="+", metavar='', default=["LCOV_EXCL_LINE"], help='Filter: Add filter for lines that will be excluded from coverage (same behavior as "LCOV_EXCL_LINE")') parser.add_argument('-g', '--gcov', dest='gcov', default='gcov', help='Which gcov binary to use') parser.add_argument('-d', '--search-directory', dest='directory', default=".", help='Base directory to recursively search for gcda files (default: .)') parser.add_argument('-c', '--compiler-directory', dest='cdirectory', default="", help='Base directory compiler was invoked from (default: . or read from gcov) \ This needs to be set if invoking fastcov from somewhere other than the base compiler directory. No need to set it if gcc version > 9.1') parser.add_argument('-j', '--jobs', dest='jobs', type=int, default=multiprocessing.cpu_count(), help='Number of parallel gcov to spawn (default: {}).'.format(multiprocessing.cpu_count())) parser.add_argument('-m', '--minimum-chunk-size', dest='minimum_chunk', type=int, default=5, help='Minimum number of files a thread should process (default: 5). \ If you have only 4 gcda files but they are monstrously huge, you could change this value to a 1 so that each thread will only process 1 gcda. Otherwise fastcov will spawn only 1 thread to process all of them.') parser.add_argument('-F', '--fallback-encodings', dest='fallback_encodings', nargs="+", metavar='', default=[], help='List of encodings to try if opening a source file with the default fails (i.e. latin1, etc.). This option is not usually needed.') parser.add_argument('-l', '--lcov', dest='lcov', action="store_true", help='Output in lcov info format instead of fastcov json') parser.add_argument('-o', '--output', dest='output', default="", help='Name of output file (default: coverage.json or coverage.info, depends on --lcov option)') parser.add_argument('-q', '--quiet', dest='quiet', action="store_true", help='Suppress output to stdout') parser.add_argument('-t', '--test-name', dest='test_name', default="", help='Specify a test name for the coverage. Equivalent to lcov\'s `-t`.') parser.add_argument('-C', '--add-tracefile', dest='combine', nargs="+", help='Combine multiple coverage files into one. If this flag is specified, fastcov will do a combine operation instead invoking gcov. Equivalent to lcov\'s `-a`.') parser.add_argument('-V', '--verbose', dest="verbose", action="store_true", help="Print more detailed information about what fastcov is doing") parser.add_argument('-w', '--validate-sources', dest="validate_sources", action="store_true", help="Check if every source file exists") parser.add_argument('-p', '--dump-statistic', dest="dump_statistic", action="store_true", help="Dump total statistic at the end") parser.add_argument('-v', '--version', action="version", version='%(prog)s {version}'.format(version=__version__), help="Show program's version number and exit") parser.add_argument('-gps', '--gcov_prefix_strip', dest="gcov_prefix_strip", action="store", default=0, type=int, help="The number of initial directory names to strip off the absolute paths in the object file.") parser.add_argument('-gp', '--gcov_prefix', dest="gcov_prefix", action="store", default="", help="The prefix to add to the paths in the object file.") args = parser.parse_args() if not args.output: args.output = 'coverage.info' if args.lcov else 'coverage.json' return args def checkPythonVersion(version): """Exit if the provided python version is less than the supported version.""" if version < MINIMUM_PYTHON: sys.stderr.write("Minimum python version {} required, found {}\n".format(tupleToDotted(MINIMUM_PYTHON), tupleToDotted(version))) sys.exit(EXIT_CODES["python_version"]) def checkGcovVersion(version): """Exit if the provided gcov version is less than the supported version.""" if version < MINIMUM_GCOV: sys.stderr.write("Minimum gcov version {} required, found {}\n".format(tupleToDotted(MINIMUM_GCOV), tupleToDotted(version))) sys.exit(EXIT_CODES["gcov_version"]) def setupLogging(quiet, verbose): handler = logging.StreamHandler() handler.setFormatter(FastcovFormatter("[%(levelname)s]: %(message)s")) root = logging.getLogger() root.setLevel(logging.INFO) root.addHandler(handler) if not quiet: logging.disable(level=logging.NOTSET) # Re-enable logging if verbose: root.setLevel(logging.DEBUG) def main(): args = parseArgs() # Setup logging setupLogging(args.quiet, args.verbose) if args.gcov_prefix_strip > 0: os.environ["GCOV_PREFIX_STRIP"] = str(args.gcov_prefix_strip) if len(args.gcov_prefix) > 0: os.environ["GCOV_PREFIX"] = args.gcov_prefix # Get report from appropriate source if args.combine: fastcov_json = getCombineCoverage(args) skip_exclusion_markers = not args.scan_exclusion_markers else: fastcov_json = getGcovCoverage(args) skip_exclusion_markers = args.skip_exclusion_markers # Scan for exclusion markers if not skip_exclusion_markers: processExclusionMarkers(fastcov_json, args.jobs, args.exclude_branches_sw, args.include_branches_sw, args.exclude_line_marker, args.minimum_chunk, args.fallback_encodings, args.gcov_prefix, args.gcov_prefix_strip) logging.info("Scanned {} source files for exclusion markers".format(len(fastcov_json["sources"]))) if args.diff_file: logging.info("Filtering according to {} file".format(args.diff_file)) DiffParser().filterByDiff(args.diff_file, args.diff_base_dir, fastcov_json, args.fallback_encodings) if args.validate_sources: validateSources(fastcov_json, args.gcov_prefix, args.gcov_prefix_strip) # Dump to desired file format dumpFile(fastcov_json, args) # If there was an error along the way, but we still completed the pipeline... if EXIT_CODE: sys.exit(EXIT_CODE) # Set package version... it's way down here so that we can call tupleToDotted __version__ = tupleToDotted(FASTCOV_VERSION) if __name__ == '__main__': main() verilator-5.042/nodist/verilator_saif_diff0000755000542200017500000002367615101701376021357 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # pylint: disable=C0114,C0115,C0116,R0902,R0903,R0912,R0915,W0719,W0718 ###################################################################### # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import argparse import re SUCCESS_CODE = 0 FAILURE_CODE = 1 INSTANCE_TYPE = "INSTANCE" NET_LIST_TYPE = "NET" SIGNAL_TYPE = "SIGNAL" EOF_ERROR = "Unexpected EOF" def saif_assert(expression : bool, message : str) -> None: if not expression: raise Exception(message) def saif_error(message : str) -> None: raise Exception(message) class SAIFSignalBit: name: str high_time: int low_time: int transitions: int def __init__(self, name : str): self.name = name self.high_time = 0 self.low_time = 0 self.transitions = 0 class SAIFInstance: def __init__(self, scope_name : str): self.scope_name = scope_name self.parent_instance = None self.nets = {} self.child_instances = {} class SAIFToken: def __init__(self, token : str): self.token = token self.type = '' self.value = '' class SAIFParser: def __init__(self): self.token_stack = [] # For parsing simplicity self.token_stack.append(SAIFToken('saif_root')) self.current_instance = None self.has_saifile_header = False self.direction = '' self.saif_version = '' self.top_instances = {} self.duration = '' self.divider = '' self.timescale = '' def parse(self, saif_filename : str) -> None: file_contents = '' with open(saif_filename, 'r', encoding="utf8") as saif_file: content = saif_file.readlines() filtered_lines = [line for line in content if not line.strip().startswith('//')] file_contents = ''.join(filtered_lines) tokens = file_contents.replace('(', ' ( ').replace(')', ' ) ').split() num_of_tokens = len(tokens) index = 0 while index < num_of_tokens: token = tokens[index] index += 1 if token == '(': self.token_stack.append(SAIFToken(token)) self.token_stack[-1].type = self.token_stack[-2].type self.token_stack[-1].value = self.token_stack[-2].value continue if token == ')': if self.token_stack[-1].type == INSTANCE_TYPE: self.current_instance = self.current_instance.parent_instance self.token_stack.pop() continue if re.match(r'SAIFILE', token): self.has_saifile_header = True continue if re.match(r'DIRECTION', token): saif_assert(index < num_of_tokens, EOF_ERROR) self.direction = tokens[index].replace('\"', '') index += 1 continue if re.match(r'SAIFVERSION', token): saif_assert(index < num_of_tokens, EOF_ERROR) self.saif_version = tokens[index].replace('\"', '') index += 1 continue if re.match(r'DESIGN|DATE|VENDOR|PROGRAM_NAME|VERSION', token): # NOP, only skip value saif_assert(index < num_of_tokens, EOF_ERROR) index += 1 continue if re.match(r'DIVIDER', token): saif_assert(index < num_of_tokens, EOF_ERROR) self.divider = tokens[index] index += 1 continue if re.match(r'TIMESCALE', token): saif_assert(index < num_of_tokens, EOF_ERROR) self.timescale = tokens[index] index += 1 continue if re.match(r'DURATION', token): saif_assert(index < num_of_tokens, EOF_ERROR) self.duration = tokens[index] index += 1 continue if re.match(r'INSTANCE', token): saif_assert(index < num_of_tokens, EOF_ERROR) instance_name = tokens[index] index += 1 self.token_stack[-1].type = INSTANCE_TYPE self.token_stack[-1].value = instance_name instance = SAIFInstance(instance_name) if self.current_instance is None: self.top_instances[instance_name] = instance else: self.current_instance.child_instances[instance_name] = instance instance.parent_instance = self.current_instance self.current_instance = instance continue if re.match(r'NET', token): self.token_stack[-1].type = NET_LIST_TYPE continue if re.match(r'T1', token): net_name = self.token_stack[-1].value saif_assert(index < num_of_tokens, EOF_ERROR) self.current_instance.nets[net_name].high_time = tokens[index] index += 1 continue if re.match(r'T0', token): net_name = self.token_stack[-1].value saif_assert(index < num_of_tokens, EOF_ERROR) self.current_instance.nets[net_name].low_time = tokens[index] index += 1 continue if re.match(r'TC', token): net_name = self.token_stack[-1].value saif_assert(index < num_of_tokens, EOF_ERROR) self.current_instance.nets[net_name].transitions = tokens[index] index += 1 continue if re.match(r'TZ|TX|TB|TG|IG|IK', token): # NOP, only skip value index += 1 continue if self.token_stack[-2].type == NET_LIST_TYPE: self.token_stack[-1].type = SIGNAL_TYPE self.token_stack[-1].value = token self.current_instance.nets[token] = SAIFSignalBit(token) saif_assert(self.has_saifile_header, "SAIF file doesn't contain a SAIFILE keyword") saif_assert(self.direction == "backward", f"SAIF file doesn't have a valid/compatible direction: {self.direction}") saif_assert(self.saif_version == "2.0", f"SAIF file doesn't have a valid/compatible version: {self.saif_version}") # Only 'saif_root' token should be left saif_assert(len(self.token_stack) == 1, "Incorrect nesting of scopes") def compare_saif_instances(first: SAIFInstance, second: SAIFInstance) -> None: if len(first.nets) != len(second.nets): saif_error(f"Number of nets doesn't match in {first.scope_name}: " f"{len(first.nets)} != {len(second.nets)}") for signal_name, saif_signal in first.nets.items(): if signal_name not in second.nets: saif_error(f"Signal {signal_name} doesn't exist in the second object\n") other_signal = second.nets[signal_name] if (saif_signal.high_time != other_signal.high_time or saif_signal.low_time != other_signal.low_time or saif_signal.transitions != other_signal.transitions): saif_error("Incompatible signal bit parameters in " f"{signal_name}\n") if len(first.child_instances) != len(second.child_instances): saif_error(f"Number of child instances doesn't match in {first.scope_name}: " f"{len(first.child_instances)} != {len(second.child_instances)}") for instance_name, instance in first.child_instances.items(): if instance_name not in second.child_instances: saif_error(f"Instance {instance_name} doesn't exist in the second object\n") compare_saif_instances(instance, second.child_instances[instance_name]) def compare_saif_contents(first_file: str, second_file: str) -> int: """Test if second SAIF file has the same values as the first""" first_saif = SAIFParser() first_saif.parse(first_file) second_saif = SAIFParser() second_saif.parse(second_file) if first_saif.duration != second_saif.duration: saif_error("Duration of trace doesn't match: " f"{first_saif.duration} != {second_saif.duration}") if first_saif.divider != second_saif.divider: saif_error(f"Dividers don't match: {first_saif.divider} != {second_saif.divider}") if first_saif.timescale != second_saif.timescale: saif_error(f"Timescale doesn't match: {first_saif.timescale} != {second_saif.timescale}") if len(first_saif.top_instances) != len(second_saif.top_instances): saif_error("Number of top instances doesn't match: " f"{len(first_saif.top_instances)} != {len(second_saif.top_instances)}") for top_instance_name, top_instance in first_saif.top_instances.items(): if top_instance_name not in second_saif.top_instances: saif_error(f"Top instance {top_instance_name} missing in other SAIF") compare_saif_instances(top_instance, second_saif.top_instances[top_instance_name]) return SUCCESS_CODE parser = argparse.ArgumentParser(allow_abbrev=False, formatter_class=argparse.RawDescriptionHelpFormatter, description="""verilator_saif_diff checks if two SAIF files are logically-identical. It returns first encountered difference as output. Run as: cd $VERILATOR_ROOT nodist/code_coverage --first example.saif --second other.saif""") parser.add_argument('--first', action='store', help='First SAIF file') parser.add_argument('--second', action='store', help='Second SAIF file') parser.set_defaults(stop=True) args = parser.parse_args() try: compare_saif_contents(args.first, args.second) except Exception as error: print(error) verilator-5.042/nodist/lint_py_test_filter0000755000542200017500000000357515101701376021434 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # mypy: disallow-untyped-defs # pylint: disable= ###################################################################### import argparse import re import sys SUPPRESSES = [ "**********", "E0602: Undefined variable 'test' (undefined-variable)", "E0602: Undefined variable 're' (undefined-variable)", "E0602: Undefined variable 'os' (undefined-variable)", "E0602: Undefined variable 'glob' (undefined-variable)", "W0611: Unused import vltest_bootstrap (unused-import)", ] ###################################################################### def process() -> None: anymsg = False for line in sys.stdin: line = line.rstrip(); show = True for msg in SUPPRESSES: if msg in line: show = False continue if show: print(line) anymsg = True if anymsg: sys.exit("%Error: See messages above") ####################################################################### ####################################################################### parser = argparse.ArgumentParser( allow_abbrev=False, formatter_class=argparse.RawDescriptionHelpFormatter, description="""lint_py_test_filter is used to filter pylint output for expected errors in Verilator test_regress/*.py tests.""", epilog="""Copyright 2024-2025 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") parser.add_argument('--debug', action='store_true', help='enable debug') Args = parser.parse_args() process() ###################################################################### # Local Variables: # compile-command: "cd .. ; make lint-py-pylint-tests" # End: verilator-5.042/nodist/uvm_pkg_packer0000755000542200017500000000570615101701376020345 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # mypy: disallow-untyped-defs # pylint: disable= ###################################################################### import argparse import re import sys ###################################################################### def process() -> None: in_header = True for line in sys.stdin: line = line.rstrip() line = line.expandtabs(tabsize=8) line = re.sub(r', +', ', ', line) line = re.sub(r'"/[^"]+/src/', '"t/uvm/src/', line) # Replace header if in_header: if re.match(r'^//', line): continue else: in_header = False print_header() in_header = False # Drop some unneeded items if re.match(r'^`begin_keywords ', line): continue if re.match(r'^`line ', line): continue if re.match(r'^\s*$', line): continue if re.match(r'^ *endpackage', line): print(line) break print(line) def print_header() -> None: print("// DESCR" "IPTION: Verilator: Concatenated UVM header for internal testing") print("// SPDX-" "License-Identifier: Apache-2.0") print("//----------------------------------------------------------------------") print("// To recreate:") print("// Using verilator_ext_tests:") print("// " + Args.test_name + " --gold") # Copy the copyright header from original sources with open(Args.uvm_header_filename, 'r', encoding="utf8") as fh: for line in fh: line = line.strip() line = line.expandtabs(tabsize=8) if not re.match(r'^//', line): break print(line) ####################################################################### ####################################################################### parser = argparse.ArgumentParser( allow_abbrev=False, formatter_class=argparse.RawDescriptionHelpFormatter, description="""uvm_pkg_packer is used to create the test_regress uvm_pkg libraries from sources in verilator_ext_test repository's tests.""", epilog="""Copyright 2025-2025 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") parser.add_argument('--debug', action='store_true', help='enable debug') parser.add_argument('--test-name', type=str, required=True, help='name of test to run to recreate') parser.add_argument('--uvm-header-filename', type=str, required=True, help='filename of uvm_pkg.sv') Args = parser.parse_args() process() ###################################################################### # Local Variables: # compile-command: "cd $VE && t/t_uvm_hello_v2017_1_0_nodpi.py" # End: verilator-5.042/nodist/dot_importer0000755000542200017500000000707115101701376020054 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # mypy: disallow-untyped-defs # pylint: disable=C0103,C0114,C0115,C0116,C0209,C0301 ###################################################################### import argparse import re ###################################################################### Header = [] Vertexes = [] Edges = [] ####################################################################### def dotread(filename: str) -> None: with open(filename, "r", encoding="utf8") as fh: header = True vnum = 0 vertex_re = re.compile(r'^\t([a-zA-Z0-9_]+)\t(.*)$') edge_re = re.compile(r'^\t([a-zA-Z0-9_]+)\s+->\s+([a-zA-Z0-9_]+)\s*(.*)$') for line in fh: vertex_match = re.search(vertex_re, line) edge_match = re.search(edge_re, line) if vertex_match: if vertex_match.group(1) != 'nTITLE': header = False Vertexes.append({'num': vnum, 'line': line, 'name': vertex_match.group(1)}) vnum += 1 elif edge_match: fromv = edge_match.group(1) tov = edge_match.group(2) w = re.match(r'weight=(\d+)', line) weight = w.group(1) if w else 1 w = re.match(r'style=(\S+)', line) cutable = w.group(1) if w else None edge = { 'num': vnum, 'line': line, 'weight': weight, 'cutable': cutable, 'from': fromv, 'to': tov } vnum += 1 Edges.append(edge) elif header: Header.append(line) print("IGNORE: " + line) ####################################################################### def cwrite(filename: str) -> None: with open(filename, "w", encoding="utf8") as fh: fh.write("void V3GraphTestImport::dotImport() {\n") fh.write(" auto* gp = &m_graph;\n") for ver in sorted(Vertexes, key=lambda ver: ver['num']): fh.write(" auto* %s = new V3GraphTestVertex{gp, \"%s\"}; if (%s) {}\n" % (ver['name'], ver['name'], ver['name'])) fh.write("\n") for edge in Edges: fh.write( " new V3GraphEdge{gp, %s, %s, %s, %s};\n" % (edge['from'], edge['to'], edge['weight'], "true" if edge['cutable'] else "false")) fh.write("}\n") ###################################################################### # main parser = argparse.ArgumentParser( allow_abbrev=False, formatter_class=argparse.RawDescriptionHelpFormatter, description="""dot_importer takes a graphvis .dot file and converts into .cpp file. This x.cpp file is then manually included in V3GraphTest.cpp to verify various xsub-algorithms.""", epilog="""Copyright 2005-2025 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") parser.add_argument('--debug', action='store_const', const=9, help='enable debug') parser.add_argument('filename', help='input .dot filename to process') Args = parser.parse_args() dotread(Args.filename) cwrite("graph_export.cpp") ###################################################################### # Local Variables: # compile-command: "./dot_importer ../test_regress/obj_vlt/t_EXAMPLE/*orderg_o*.dot && cat graph_export.cpp" # End: verilator-5.042/nodist/log_changes0000755000542200017500000000705715101701376017622 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # mypy: disallow-untyped-defs # pylint: disable=C0114,C0116,C0209,R0911,R0912,R0915 ###################################################################### import argparse import os import re #from pprint import pprint,pformat ####################################################################### def message_section(msg: str) -> int: """Return sorting-section number for given commit message""" if re.match(r'^Support', msg): return 10 if re.match(r'^Add', msg): return 20 if re.match(r'^Improve', msg): return 30 if re.match(r'^Fix', msg): return 40 if re.match(r'^(Internals|CI|Tests)', msg): return -1 if re.match(r'^Bump.* from .* to .*', msg): # dependabot return -1 return 0 def process() -> None: cmd = "git log" msgs = {} with os.popen(cmd) as fh: author = "" lineno = 0 for line in fh: lineno += 1 line = line.rstrip() if re.match(r'^Date', line): continue if re.match(r'^commit', line): continue if re.search(r'Commentary: Changes update', line): break am = re.match(r'^Author: (.*) <(.*)>', line) dm = re.match(r'^ +(.*)', line) if am: email = am.group(2) author = am.group(1) if re.search(r'antmicro', email): author += ", Antmicro Ltd." if re.search(r'github action', author): author = "" continue elif author != "" and dm: msg = dm.group(1) if not re.search(r'\.$', msg): msg += '.' msg += ' [' + author + ']' mid = re.search(r'\(#([0-9][0-9][0-9][0-9]+)', line) if mid: bug_id = mid.group(1) else: bug_id = " %d" % lineno section = message_section(msg) if section >= 0: key = "%06s_%06s_%06d" % (section, bug_id, lineno) msgs[key] = '* ' + msg # print("i [%s] %s" % (key, msg)) author = "" if not msgs: print("No Changes need to be inserted.") return print() print("Insertion-sort the following lines into 'Changes' file:") print() dedup = {} for key in sorted(msgs.keys()): if msgs[key] not in dedup: dedup[msgs[key]] = True print(msgs[key]) print() print("You may now want to clean up spelling, and commit:") print(" (make spelling | grep -vi 'writing output')") print(" git ci -am 'Commentary: Changes update'") print() ####################################################################### parser = argparse.ArgumentParser( allow_abbrev=False, prog="log_changes", description="Create example entries for 'Changes' from parsing 'git log'", epilog="""Copyright 2019-2025 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") parser.add_argument('--debug', action='store_true', help='enable debug') Args = parser.parse_args() process() ###################################################################### # Local Variables: # compile-command: "cd .. ; nodist/log_changes" # End: verilator-5.042/nodist/clang_check_attributes0000755000542200017500000013704315101701376022037 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # pylint: disable=C0114,C0115,C0116,C0209,C0302,R0902,R0911,R0912,R0914,R0915,E1101 # # Copyright 2022-2025 by Wilson Snyder. Verilator is free software; you # can redistribute it and/or modify it under the terms of either the GNU Lesser # General Public License Version 3 or the Apache License 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Apache-2.0 import argparse import os import sys import shlex from typing import Callable, Iterable, Optional, Union, TYPE_CHECKING import dataclasses from dataclasses import dataclass import enum from enum import Enum import multiprocessing import re import tempfile import clang.cindex from clang.cindex import ( Index, TranslationUnitSaveError, TranslationUnitLoadError, CompilationDatabase, ) if not TYPE_CHECKING: from clang.cindex import CursorKind else: # Workaround for missing support for members defined out-of-class in Pylance: # https://github.com/microsoft/pylance-release/issues/2365#issuecomment-1035803067 class CursorKindMeta(type): def __getattr__(cls, name: str) -> clang.cindex.CursorKind: return getattr(clang.cindex.CursorKind, name) # pylint: disable-next=invalid-enum-extension class CursorKind(clang.cindex.CursorKind, metaclass=CursorKindMeta): pass def fully_qualified_name(node): if node is None: return [] if node.kind == CursorKind.TRANSLATION_UNIT: return [] res = fully_qualified_name(node.semantic_parent) displayname = node.displayname displayname = [displayname] if displayname else [] if res: return res + displayname return displayname # Returns True, if `class_node` contains node # that matches `member` spelling def check_class_member_exists(class_node, member): for child in class_node.get_children(): if member.spelling == child.spelling: return True return False # Returns Base class (if found) of `class_node` # that is of type `base_type` def get_base_class(class_node, base_type): for child in class_node.get_children(): if child.kind is CursorKind.CXX_BASE_SPECIFIER: base_class = child.type if base_type.spelling == base_class.spelling: return base_class return None @dataclass class VlAnnotations: mt_start: bool = False mt_safe: bool = False stable_tree: bool = False mt_safe_postinit: bool = False mt_unsafe: bool = False mt_disabled: bool = False mt_unsafe_one: bool = False pure: bool = False guarded: bool = False requires: bool = False excludes: bool = False acquire: bool = False release: bool = False def is_mt_safe_context(self): return self.mt_safe and not (self.mt_unsafe or self.mt_unsafe_one) def is_pure_context(self): return self.pure def is_stabe_tree_context(self): # stable tree context requires calls to be marked # as MT_SAFE or MT_STABLE # Functions in MT_START needs to be MT_SAFE or MT_STABLE return self.stable_tree or self.mt_start def is_mt_unsafe_call(self): return self.mt_unsafe or self.mt_unsafe_one or self.mt_disabled def is_mt_safe_call(self): return (not self.is_mt_unsafe_call() and (self.mt_safe or self.mt_safe_postinit or self.pure or self.requires or self.excludes or self.acquire or self.release)) def is_pure_call(self): return self.pure def is_stabe_tree_call(self): return self.stable_tree def __or__(self, other: "VlAnnotations"): result = VlAnnotations() for key, value in dataclasses.asdict(self).items(): setattr(result, key, value | getattr(other, key)) return result def is_empty(self): for value in dataclasses.asdict(self).values(): if value: return False return True def __str__(self): result = [] for field, value in dataclasses.asdict(self).items(): if value: result.append(field) return ", ".join(result) @staticmethod def from_nodes_list(nodes: Iterable): result = VlAnnotations() for node in nodes: if node.kind == CursorKind.ANNOTATE_ATTR: displayname = node.displayname if displayname == "MT_START": result.mt_start = True elif displayname == "MT_SAFE": result.mt_safe = True elif displayname == "MT_STABLE": result.stable_tree = True elif displayname == "MT_SAFE_POSTINIT": result.mt_safe_postinit = True elif displayname == "MT_UNSAFE": result.mt_unsafe = True elif displayname == "MT_UNSAFE_ONE": result.mt_unsafe_one = True elif displayname == "MT_DISABLED": result.mt_disabled = True elif displayname == "PURE": result.pure = True elif displayname in ["ACQUIRE", "ACQUIRE_SHARED"]: result.acquire = True elif displayname in ["RELEASE", "RELEASE_SHARED"]: result.release = True elif displayname == "REQUIRES": result.requires = True elif displayname in ["EXCLUDES", "MT_SAFE_EXCLUDES"]: result.excludes = True elif displayname == "GUARDED_BY": result.guarded = True # Attributes are always at the beginning elif not node.kind.is_attribute(): break return result class FunctionType(Enum): UNKNOWN = enum.auto() FUNCTION = enum.auto() METHOD = enum.auto() STATIC_METHOD = enum.auto() CONSTRUCTOR = enum.auto() @staticmethod def from_node(node: clang.cindex.Cursor): if node is None: return FunctionType.UNKNOWN if node.kind == CursorKind.FUNCTION_DECL: return FunctionType.FUNCTION if node.kind == CursorKind.CXX_METHOD and node.is_static_method(): return FunctionType.STATIC_METHOD if node.kind == CursorKind.CXX_METHOD: return FunctionType.METHOD if node.kind == CursorKind.CONSTRUCTOR: return FunctionType.CONSTRUCTOR return FunctionType.UNKNOWN @dataclass(eq=False) class FunctionInfo: name_parts: list[str] usr: str file: str line: int annotations: VlAnnotations ftype: FunctionType _hash: Optional[int] = dataclasses.field(default=None, init=False, repr=False) @property def name(self): return "::".join(self.name_parts) def __str__(self): return f"[{self.name}@{self.file}:{self.line}]" def __hash__(self): if not self._hash: self._hash = hash(f"{self.usr}:{self.file}:{self.line}") return self._hash def __eq__(self, other): return (self.usr == other.usr and self.file == other.file and self.line == other.line) def copy(self, /, **changes): return dataclasses.replace(self, **changes) @staticmethod def from_decl_file_line_and_refd_node(file: str, line: int, refd: clang.cindex.Cursor, annotations: VlAnnotations): file = os.path.abspath(file) refd = refd.canonical assert refd is not None name_parts = fully_qualified_name(refd) usr = refd.get_usr() ftype = FunctionType.from_node(refd) return FunctionInfo(name_parts, usr, file, line, annotations, ftype) @staticmethod def from_node(node: clang.cindex.Cursor, refd: Optional[clang.cindex.Cursor] = None, annotations: Optional[VlAnnotations] = None): file = os.path.abspath(node.location.file.name) line = node.location.line if annotations is None: annotations = VlAnnotations.from_nodes_list(node.get_children()) if refd is None: refd = node.referenced if refd is not None: refd = refd.canonical assert refd is not None name_parts = fully_qualified_name(refd) usr = refd.get_usr() ftype = FunctionType.from_node(refd) return FunctionInfo(name_parts, usr, file, line, annotations, ftype) class DiagnosticKind(Enum): ANNOTATIONS_DEF_DECL_MISMATCH = enum.auto() NON_PURE_CALL_IN_PURE_CTX = enum.auto() NON_MT_SAFE_CALL_IN_MT_SAFE_CTX = enum.auto() NON_STABLE_TREE_CALL_IN_STABLE_TREE_CTX = enum.auto() MISSING_MT_DISABLED_ANNOTATION = enum.auto() def __lt__(self, other): return self.value < other.value @dataclass class Diagnostic: target: FunctionInfo source: FunctionInfo source_ctx: FunctionInfo kind: DiagnosticKind _hash: Optional[int] = dataclasses.field(default=None, init=False, repr=False) def __hash__(self): if not self._hash: self._hash = hash(hash(self.target) ^ hash(self.source_ctx) ^ hash(self.kind)) return self._hash class CallAnnotationsValidator: def __init__(self, diagnostic_cb: Callable[[Diagnostic], None], is_ignored_top_level: Callable[[clang.cindex.Cursor], bool], is_ignored_def: Callable[[clang.cindex.Cursor, clang.cindex.Cursor], bool], is_ignored_call: Callable[[clang.cindex.Cursor], bool]): self._diagnostic_cb = diagnostic_cb self._is_ignored_top_level = is_ignored_top_level self._is_ignored_call = is_ignored_call self._is_ignored_def = is_ignored_def self._index = Index.create() # Map key represents translation unit initial defines # (from command line and source's lines before any include) self._processed_headers: dict[str, set[str]] = {} self._external_decls: dict[str, set[tuple[str, int]]] = {} # Current context self._main_source_file: str = "" self._defines: dict[str, str] = {} self._call_location: Optional[FunctionInfo] = None self._caller: Optional[FunctionInfo] = None self._base_func_declarations: dict[str, clang.cindex.Cursor] = {} self._constructor_context: list[clang.cindex.Cursor] = [] self._level: int = 0 def is_mt_disabled_code_unit(self): return "VL_MT_DISABLED_CODE_UNIT" in self._defines def is_constructor_context(self): return len(self._constructor_context) > 0 # Parses all lines in a form: `#define KEY VALUE` located before any `#include` line. # The parsing is very simple, there is no support for line breaks, etc. @staticmethod def parse_initial_defines(source_file: str) -> dict[str, str]: defs: dict[str, str] = {} with open(source_file, "r", encoding="utf-8") as file: for line in file: line = line.strip() match = re.fullmatch(r"^#\s*(define\s+(\w+)(?:\s+(.*))?|include\s+.*)$", line) if match: if match.group(1).startswith("define"): key = match.group(2) value = match.groups("1")[2] defs[key] = value elif match.group(1).startswith("include"): break return defs @staticmethod def filter_out_unsupported_compiler_args(args: list[str]) -> tuple[list[str], dict[str, str]]: filtered_args = [] defines = {} args_iter = iter(args) try: while arg := next(args_iter): # Skip positional arguments (input file name). if not arg.startswith("-") and (arg.endswith(".cpp") or arg.endswith(".c") or arg.endswith(".h")): continue # Skipped options with separate value argument. if arg in ["-o", "-T", "-MT", "-MQ", "-MF" "-L"]: next(args_iter) continue # Skipped options without separate value argument. if arg == "-c" or arg.startswith("-W") or arg.startswith("-L"): continue # Preserved options with separate value argument. if arg in [ "-x" "-Xclang", "-I", "-isystem", "-iquote", "-include", "-include-pch" ]: filtered_args += [arg, next(args_iter)] continue kv_str = None d_or_u = None # Preserve define/undefine with separate value argument. if arg in ["-D", "-U"]: filtered_args.append(arg) d_or_u = arg[1] kv_str = next(args_iter) filtered_args.append(kv_str) # Preserve define/undefine without separate value argument. elif arg[0:2] in ["-D", "-U"]: filtered_args.append(arg) kv_str = arg[2:] d_or_u = arg[1] # Preserve everything else. else: filtered_args.append(arg) continue # Keep track of defines for class' internal purposes. key_value = kv_str.split("=", 1) key = key_value[0] val = "1" if len(key_value) == 1 else key_value[1] if d_or_u == "D": defines[key] = val elif d_or_u == "U" and key in defines: del defines[key] except StopIteration: pass return (filtered_args, defines) def compile_and_analyze_file(self, source_file: str, compiler_args: list[str], build_dir: Optional[str]): filename = os.path.abspath(source_file) initial_cwd = "." filtered_args, defines = self.filter_out_unsupported_compiler_args(compiler_args) defines.update(self.parse_initial_defines(source_file)) if build_dir: initial_cwd = os.getcwd() os.chdir(build_dir) try: translation_unit = self._index.parse(filename, filtered_args) except TranslationUnitLoadError: translation_unit = None errors = [] if translation_unit: for diag in translation_unit.diagnostics: if diag.severity >= clang.cindex.Diagnostic.Error: errors.append(str(diag)) if translation_unit and len(errors) == 0: self._defines = defines self._main_source_file = filename self.process_translation_unit(translation_unit) self._main_source_file = "" self._defines = {} elif len(errors) != 0: print(f"%Error: parsing failed: {filename}", file=sys.stderr) for error in errors: print(f" {error}", file=sys.stderr) if build_dir: os.chdir(initial_cwd) def emit_diagnostic(self, target: Union[FunctionInfo, clang.cindex.Cursor], kind: DiagnosticKind): assert self._caller is not None assert self._call_location is not None source = self._caller source_ctx = self._call_location if isinstance(target, FunctionInfo): self._diagnostic_cb(Diagnostic(target, source, source_ctx, kind)) else: self._diagnostic_cb( Diagnostic(FunctionInfo.from_node(target), source, source_ctx, kind)) def iterate_children(self, children: Iterable[clang.cindex.Cursor], handler: Callable[[clang.cindex.Cursor], None]): if children: self._level += 1 for child in children: handler(child) self._level -= 1 @staticmethod def get_referenced_node_info( node: clang.cindex.Cursor ) -> tuple[bool, Optional[clang.cindex.Cursor], VlAnnotations, Iterable[clang.cindex.Cursor]]: if not node.spelling and not node.displayname: return (False, None, VlAnnotations(), []) refd = node.referenced if refd is None: raise ValueError("The node does not specify referenced node.") refd = refd.canonical children = list(refd.get_children()) annotations = VlAnnotations.from_nodes_list(children) return (True, refd, annotations, children) def check_mt_safe_call(self, node: clang.cindex.Cursor, refd: clang.cindex.Cursor, annotations: VlAnnotations): is_mt_safe = False if annotations.is_mt_safe_call(): is_mt_safe = True elif not annotations.is_mt_unsafe_call(): # Check whether the object the method is called on is mt-safe def find_object_ref(node): try: node = next(node.get_children()) if node.kind == CursorKind.DECL_REF_EXPR: # Operator on an argument or local object return node if node.kind != CursorKind.MEMBER_REF_EXPR: return None if node.referenced and node.referenced.kind == CursorKind.FIELD_DECL: # Operator on a member object return node node = next(node.get_children()) if node.kind == CursorKind.UNEXPOSED_EXPR: node = next(node.get_children()) return node except StopIteration: return None refn = find_object_ref(node) if self.is_constructor_context() and not refn: # we are in constructor and no object reference means # we are calling local method. It is MT safe # only if this method is also only calling local methods or # MT-safe methods self.iterate_children(refd.get_children(), self.dispatch_node_inside_definition) is_mt_safe = True # class/struct member elif refn and refn.kind == CursorKind.MEMBER_REF_EXPR and refn.referenced: refn = refn.referenced refna = VlAnnotations.from_nodes_list(refn.get_children()) if refna.guarded: is_mt_safe = True if self.is_constructor_context() and refn.semantic_parent: # we are in constructor, so calling local members is MT_SAFE, # make sure object that we are calling is local to the constructor constructor_class = self._constructor_context[-1].semantic_parent if refn.semantic_parent.spelling == constructor_class.spelling: if check_class_member_exists(constructor_class, refn): is_mt_safe = True else: # check if this class inherits from some base class base_class = get_base_class(constructor_class, refn.semantic_parent) if base_class: if check_class_member_exists(base_class.get_declaration(), refn): is_mt_safe = True # variable elif refn and refn.kind == CursorKind.DECL_REF_EXPR and refn.referenced: if refn.get_definition(): if refn.referenced.semantic_parent: if refn.referenced.semantic_parent.kind in [ CursorKind.FUNCTION_DECL, CursorKind.CXX_METHOD ]: # This is a local or an argument. # Calling methods on local pointers or references is MT-safe, # but on argument pointers or references is not. if "*" not in refn.type.spelling and "&" not in refn.type.spelling: is_mt_safe = True # local variable if refn.referenced.kind == CursorKind.VAR_DECL: is_mt_safe = True else: # Global variable in different translation unit, unsafe pass elif refn and refn.kind == CursorKind.CALL_EXPR: if self.is_constructor_context(): # call to local function from constructor context # safe if this function also calling local methods or # MT-safe methods self.dispatch_call_node(refn) is_mt_safe = True return is_mt_safe # Call handling def process_method_call(self, node: clang.cindex.Cursor, refd: clang.cindex.Cursor, annotations: VlAnnotations): assert self._call_location ctx = self._call_location.annotations # MT-safe context if ctx.is_mt_safe_context(): if not self.check_mt_safe_call(node, refd, annotations): self.emit_diagnostic(FunctionInfo.from_node(refd, refd, annotations), DiagnosticKind.NON_MT_SAFE_CALL_IN_MT_SAFE_CTX) # stable tree context if ctx.is_stabe_tree_context(): if annotations.is_mt_unsafe_call() or not ( annotations.is_stabe_tree_call() or annotations.is_pure_call() or self.check_mt_safe_call(node, refd, annotations)): self.emit_diagnostic(FunctionInfo.from_node(refd, refd, annotations), DiagnosticKind.NON_STABLE_TREE_CALL_IN_STABLE_TREE_CTX) # pure context if ctx.is_pure_context(): if not annotations.is_pure_call(): self.emit_diagnostic(FunctionInfo.from_node(refd, refd, annotations), DiagnosticKind.NON_PURE_CALL_IN_PURE_CTX) def process_function_call(self, refd: clang.cindex.Cursor, annotations: VlAnnotations): assert self._call_location ctx = self._call_location.annotations # MT-safe context if ctx.is_mt_safe_context(): if not annotations.is_mt_safe_call(): self.emit_diagnostic(FunctionInfo.from_node(refd, refd, annotations), DiagnosticKind.NON_MT_SAFE_CALL_IN_MT_SAFE_CTX) # stable tree context if ctx.is_stabe_tree_context(): if annotations.is_mt_unsafe_call() or not (annotations.is_pure_call() or annotations.is_mt_safe_call() or annotations.is_stabe_tree_call()): self.emit_diagnostic(FunctionInfo.from_node(refd, refd, annotations), DiagnosticKind.NON_STABLE_TREE_CALL_IN_STABLE_TREE_CTX) # pure context if ctx.is_pure_context(): if not annotations.is_pure_call(): self.emit_diagnostic(FunctionInfo.from_node(refd, refd, annotations), DiagnosticKind.NON_PURE_CALL_IN_PURE_CTX) def process_constructor_call(self, refd: clang.cindex.Cursor, annotations: VlAnnotations): assert self._call_location ctx = self._call_location.annotations # Constructors are OK in MT-safe context # only if they call local methods or MT-safe functions. if ctx.is_mt_safe_context() or self.is_constructor_context(): self._constructor_context.append(refd) self.iterate_children(refd.get_children(), self.dispatch_node_inside_definition) self._constructor_context.pop() # stable tree context if ctx.is_stabe_tree_context(): self._constructor_context.append(refd) self.iterate_children(refd.get_children(), self.dispatch_node_inside_definition) self._constructor_context.pop() # pure context if ctx.is_pure_context(): if not annotations.is_pure_call() and not refd.is_default_constructor(): self.emit_diagnostic(FunctionInfo.from_node(refd, refd, annotations), DiagnosticKind.NON_PURE_CALL_IN_PURE_CTX) def dispatch_call_node(self, node: clang.cindex.Cursor): [supported, refd, annotations, _] = self.get_referenced_node_info(node) if not supported: self.iterate_children(node.get_children(), self.dispatch_node_inside_definition) return True assert refd is not None if self._is_ignored_call(refd): return True if "std::function" in refd.displayname: # Workaroud for missing support for lambda annotations # in c++11. # If function takes std::function as argument, # assume, that this std::function will be called inside it. self.process_function_definition(node) return False assert self._call_location is not None node_file = os.path.abspath(node.location.file.name) self._call_location = self._call_location.copy(file=node_file, line=node.location.line) # Standalone functions and static class methods if (refd.kind == CursorKind.FUNCTION_DECL or refd.kind == CursorKind.CXX_METHOD and refd.is_static_method()): self.process_function_call(refd, annotations) # Function pointer elif refd.kind in [CursorKind.VAR_DECL, CursorKind.FIELD_DECL, CursorKind.PARM_DECL]: self.process_function_call(refd, annotations) # Non-static class methods elif refd.kind == CursorKind.CXX_METHOD: self.process_method_call(node, refd, annotations) # Conversion method (e.g. `operator int()`) elif refd.kind == CursorKind.CONVERSION_FUNCTION: self.process_method_call(node, refd, annotations) # Constructors elif refd.kind == CursorKind.CONSTRUCTOR: self.process_constructor_call(refd, annotations) else: # Ignore other callables, but report them print("Unknown callable: " f"{refd.location.file.name}:{refd.location.line}: " f"{refd.displayname} {refd.kind}\n" f" from: {node.location.file.name}:{node.location.line}") return True def process_function_declaration(self, node: clang.cindex.Cursor): # Ignore declarations in main .cpp file if node.location.file.name != self._main_source_file: children = list(node.get_children()) annotations = VlAnnotations.from_nodes_list(children) if not annotations.mt_disabled: self._external_decls.setdefault(node.get_usr(), set()).add( (str(node.location.file.name), int(node.location.line))) return self.iterate_children(children, self.dispatch_node) return self.iterate_children(node.get_children(), self.dispatch_node) # Definition handling def dispatch_node_inside_definition(self, node: clang.cindex.Cursor): if node.kind == CursorKind.CALL_EXPR: if self.dispatch_call_node(node) is False: return None elif node.is_definition() and node.kind in [ CursorKind.CXX_METHOD, CursorKind.FUNCTION_DECL, CursorKind.CONSTRUCTOR, CursorKind.CONVERSION_FUNCTION ]: self.process_function_definition(node) return None return self.iterate_children(node.get_children(), self.dispatch_node_inside_definition) def process_function_definition(self, node: clang.cindex.Cursor): [supported, refd, annotations, _] = self.get_referenced_node_info(node) # Fetch virtual annotations from base class. # Set refd to virtual definition if present. signature = node.displayname if signature in self._base_func_declarations: refd = self._base_func_declarations[signature] virtual_annotations = VlAnnotations.from_nodes_list(refd.get_children()) annotations = annotations | virtual_annotations if refd and self._is_ignored_def(node, refd): return None node_children = list(node.get_children()) if not supported: return self.iterate_children(node_children, self.dispatch_node) assert refd is not None def_annotations = VlAnnotations.from_nodes_list(node_children) # Implicitly mark definitions in VL_MT_DISABLED_CODE_UNIT .cpp files as # VL_MT_DISABLED. Existence of the annotation on declarations in .h # files is verified below. # Also sets VL_EXCLUDES, as this annotation is added together with # explicit VL_MT_DISABLED. if self.is_mt_disabled_code_unit(): if node.location.file.name == self._main_source_file: annotations.mt_disabled = True annotations.excludes = True if refd.location.file.name == self._main_source_file: def_annotations.mt_disabled = True def_annotations.excludes = True if def_annotations != annotations: # Use definition's annotations for the diagnostic # source (i.e. the definition) self._caller = FunctionInfo.from_node(node, refd, def_annotations) self._call_location = self._caller self.emit_diagnostic(FunctionInfo.from_node(refd, refd, annotations), DiagnosticKind.ANNOTATIONS_DEF_DECL_MISMATCH) else: # Use concatenation of definition and declaration annotations # for calls validation. self._caller = FunctionInfo.from_node(node, refd, def_annotations | annotations) prev_call_location = self._call_location self._call_location = self._caller if self.is_mt_disabled_code_unit(): # Report declarations of this functions that don't have MT_DISABLED annotation # and are located in headers. if node.location.file.name == self._main_source_file: usr = node.get_usr() declarations = self._external_decls.get(usr, set()) for file, line in declarations: self.emit_diagnostic( FunctionInfo.from_decl_file_line_and_refd_node( file, line, refd, def_annotations), DiagnosticKind.MISSING_MT_DISABLED_ANNOTATION) if declarations: del self._external_decls[usr] self.iterate_children(node_children, self.dispatch_node_inside_definition) self._call_location = prev_call_location self._caller = prev_call_location return None # Nodes not located inside definition def dispatch_node(self, node: clang.cindex.Cursor): kind = node.kind if kind is CursorKind.CXX_BASE_SPECIFIER: # Get referenced virtual declarations from base class. for base in node.get_children(): if base.referenced: for declaration in base.referenced.get_children(): self._base_func_declarations[declaration.displayname] = declaration elif kind in [ CursorKind.CXX_METHOD, CursorKind.FUNCTION_DECL, CursorKind.CONSTRUCTOR, CursorKind.CONVERSION_FUNCTION ]: if node.is_definition(): return self.process_function_definition(node) return self.process_function_declaration(node) result = self.iterate_children(node.get_children(), self.dispatch_node) # Clean declarations if class declaration processing is finished. if kind in [ CursorKind.CLASS_DECL, CursorKind.STRUCT_DECL, CursorKind.UNION_DECL, CursorKind.ENUM_DECL, CursorKind.UNEXPOSED_DECL ]: self._base_func_declarations = {} return result def process_translation_unit(self, translation_unit: clang.cindex.TranslationUnit): self._level += 1 kv_defines = sorted([f"{k}={v}" for k, v in self._defines.items()]) concat_defines = '\n'.join(kv_defines) # List of headers already processed in a TU with specified set of defines. tu_processed_headers = self._processed_headers.setdefault(concat_defines, set()) for child in translation_unit.cursor.get_children(): if self._is_ignored_top_level(child): continue if tu_processed_headers: filename = os.path.abspath(child.location.file.name) if filename in tu_processed_headers: continue self.dispatch_node(child) self._level -= 1 tu_processed_headers.update( [os.path.abspath(str(hdr.source)) for hdr in translation_unit.get_includes()]) @dataclass class CompileCommand: refid: int filename: str args: list[str] directory: str = dataclasses.field(default_factory=os.getcwd) def get_filter_funcs(verilator_root: str): verilator_root = os.path.abspath(verilator_root) + "/" def is_ignored_top_level(node: clang.cindex.Cursor) -> bool: # Anything defined in a header outside Verilator root if not node.location.file: return True filename = os.path.abspath(node.location.file.name) return not filename.startswith(verilator_root) def is_ignored_def(node: clang.cindex.Cursor, refd: clang.cindex.Cursor) -> bool: # __* if str(refd.spelling).startswith("__"): return True # Anything defined in a header outside Verilator root if not node.location.file: return True filename = os.path.abspath(node.location.file.name) if not filename.startswith(verilator_root): return True return False def is_ignored_call(refd: clang.cindex.Cursor) -> bool: # __* if str(refd.spelling).startswith("__"): return True # std::* fqn = fully_qualified_name(refd) if fqn and fqn[0] == "std": return True # Anything declared in a header outside Verilator root if not refd.location.file: return True filename = os.path.abspath(refd.location.file.name) if not filename.startswith(verilator_root): return True return False return (is_ignored_top_level, is_ignored_def, is_ignored_call) def precompile_header(compile_command: CompileCommand, tmp_dir: str) -> str: initial_cwd = os.getcwd() errors = [] try: os.chdir(compile_command.directory) index = Index.create() translation_unit = index.parse(compile_command.filename, compile_command.args) for diag in translation_unit.diagnostics: if diag.severity >= clang.cindex.Diagnostic.Error: errors.append(str(diag)) if len(errors) == 0: pch_file = os.path.join( tmp_dir, f"{compile_command.refid:02}_{os.path.basename(compile_command.filename)}.pch") translation_unit.save(pch_file) if pch_file: return pch_file except (TranslationUnitSaveError, TranslationUnitLoadError, OSError) as exception: print(f"%Warning: {exception}", file=sys.stderr) finally: os.chdir(initial_cwd) print(f"%Warning: Precompilation failed, skipping: {compile_command.filename}", file=sys.stderr) for error in errors: print(f" {error}", file=sys.stderr) return "" # Compile and analyze inputs in a single process. def run_analysis(ccl: Iterable[CompileCommand], pccl: Iterable[CompileCommand], diagnostic_cb: Callable[[Diagnostic], None], verilator_root: str): (is_ignored_top_level, is_ignored_def, is_ignored_call) = get_filter_funcs(verilator_root) prefix = "verilator_clang_check_attributes_" with tempfile.TemporaryDirectory(prefix=prefix) as tmp_dir: extra_args = [] for pcc in pccl: pch_file = precompile_header(pcc, tmp_dir) if pch_file: extra_args += ["-include-pch", pch_file] cav = CallAnnotationsValidator(diagnostic_cb, is_ignored_top_level, is_ignored_def, is_ignored_call) for compile_command in ccl: cav.compile_and_analyze_file(compile_command.filename, extra_args + compile_command.args, compile_command.directory) @dataclass class ParallelAnalysisProcess: cav: Optional[CallAnnotationsValidator] = None diags: set[Diagnostic] = dataclasses.field(default_factory=set) tmp_dir: str = "" @staticmethod def init_data(verilator_root: str, tmp_dir: str): (is_ignored_top_level, is_ignored_def, is_ignored_call) = get_filter_funcs(verilator_root) ParallelAnalysisProcess.cav = CallAnnotationsValidator( ParallelAnalysisProcess._diagnostic_handler, is_ignored_top_level, is_ignored_def, is_ignored_call) ParallelAnalysisProcess.tmp_dir = tmp_dir @staticmethod def _diagnostic_handler(diag: Diagnostic): ParallelAnalysisProcess.diags.add(diag) @staticmethod def analyze_cpp_file(compile_command: CompileCommand) -> set[Diagnostic]: ParallelAnalysisProcess.diags = set() assert ParallelAnalysisProcess.cav is not None ParallelAnalysisProcess.cav.compile_and_analyze_file(compile_command.filename, compile_command.args, compile_command.directory) return ParallelAnalysisProcess.diags @staticmethod def precompile_header(compile_command: CompileCommand) -> str: return precompile_header(compile_command, ParallelAnalysisProcess.tmp_dir) # Compile and analyze inputs in multiple processes. def run_parallel_analysis(ccl: Iterable[CompileCommand], pccl: Iterable[CompileCommand], diagnostic_cb: Callable[[Diagnostic], None], jobs_count: int, verilator_root: str): prefix = "verilator_clang_check_attributes_" with tempfile.TemporaryDirectory(prefix=prefix) as tmp_dir: with multiprocessing.Pool(processes=jobs_count, initializer=ParallelAnalysisProcess.init_data, initargs=[verilator_root, tmp_dir]) as pool: extra_args = [] for pch_file in pool.imap_unordered(ParallelAnalysisProcess.precompile_header, pccl): if pch_file: extra_args += ["-include-pch", pch_file] if extra_args: for compile_command in ccl: compile_command.args = compile_command.args + extra_args for diags in pool.imap_unordered(ParallelAnalysisProcess.analyze_cpp_file, ccl, 1): for diag in diags: diagnostic_cb(diag) class TopDownSummaryPrinter(): @dataclass class FunctionCallees: info: FunctionInfo calees: set[FunctionInfo] mismatch: Optional[FunctionInfo] = None reason: Optional[DiagnosticKind] = None def __init__(self): self._is_first_group = True self._funcs: dict[str, TopDownSummaryPrinter.FunctionCallees] = {} self._unsafe_in_safe: set[str] = set() def begin_group(self, label): if not self._is_first_group: print() print(f"%Error: {label}") self._is_first_group = False def handle_diagnostic(self, diag: Diagnostic): usr = diag.source.usr func = self._funcs.get(usr, None) if func is None: func = TopDownSummaryPrinter.FunctionCallees(diag.source, set()) self._funcs[usr] = func func.reason = diag.kind if diag.kind == DiagnosticKind.ANNOTATIONS_DEF_DECL_MISMATCH: func.mismatch = diag.target else: func.calees.add(diag.target) self._unsafe_in_safe.add(diag.target.usr) def print_summary(self, root_dir: str): row_groups: dict[str, list[list[str]]] = {} column_widths = [0, 0] for func in sorted(self._funcs.values(), key=lambda func: (func.info.file, func.info.line, func.info.usr)): func_info = func.info relfile = os.path.relpath(func_info.file, root_dir) row_group = [] name = f"\"{func_info.name}\" " if func.reason == DiagnosticKind.ANNOTATIONS_DEF_DECL_MISMATCH: name += "declaration does not match definition" elif func.reason == DiagnosticKind.NON_MT_SAFE_CALL_IN_MT_SAFE_CTX: name += "is mtsafe but calls non-mtsafe function(s)" elif func.reason == DiagnosticKind.NON_PURE_CALL_IN_PURE_CTX: name += "is pure but calls non-pure function(s)" elif func.reason == DiagnosticKind.NON_STABLE_TREE_CALL_IN_STABLE_TREE_CTX: name += "is stable_tree but calls non-stable_tree or non-mtsafe" elif func.reason == DiagnosticKind.MISSING_MT_DISABLED_ANNOTATION: name += ("defined in a file marked as " + "VL_MT_DISABLED_CODE_UNIT has declaration(s) " + "without VL_MT_DISABLED annotation") else: name += "for unknown reason (please add description)" if func.mismatch: mrelfile = os.path.relpath(func.mismatch.file, root_dir) row_group.append([ f"{mrelfile}:{func.mismatch.line}:", f"[{func.mismatch.annotations}]", func.mismatch.name + " [declaration]" ]) row_group.append( [f"{relfile}:{func_info.line}:", f"[{func_info.annotations}]", func_info.name]) for callee in sorted(func.calees, key=lambda func: (func.file, func.line, func.usr)): crelfile = os.path.relpath(callee.file, root_dir) row_group.append( [f"{crelfile}:{callee.line}:", f"[{callee.annotations}]", " " + callee.name]) row_groups[name] = row_group for row in row_group: for row_id, value in enumerate(row[0:-1]): column_widths[row_id] = max(column_widths[row_id], len(value)) for label, rows in sorted(row_groups.items(), key=lambda kv: kv[0]): self.begin_group(label) for row in rows: print(f"{row[0]:<{column_widths[0]}} " f"{row[1]:<{column_widths[1]}} " f"{row[2]}") print(f"Number of functions reported unsafe: {len(self._unsafe_in_safe)}") def get_cpu_count(): try: return len(os.sched_getaffinity(0)) except AttributeError: return multiprocessing.cpu_count() def main(): default_verilator_root = os.path.abspath(os.path.join(os.path.dirname(__file__), "..")) parser = argparse.ArgumentParser( allow_abbrev=False, formatter_class=argparse.RawDescriptionHelpFormatter, description="""Check function annotations for correctness""", epilog="""Copyright 2022-2025 by Wilson Snyder. Verilator is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Apache License 2.0. SPDX-License-Identifier: LGPL-3.0-only OR Apache-2.0""") parser.add_argument("--verilator-root", type=str, default=default_verilator_root, help="Path to Verilator sources root directory.") parser.add_argument("--jobs", "-j", type=int, default=0, help="Number of parallel jobs to use.") parser.add_argument("--compile-commands-dir", type=str, default=None, help="Path to directory containing compile_commands.json.") parser.add_argument("--cxxflags", type=str, default=None, help="Extra flags passed to clang++.") parser.add_argument("--compilation-root", type=str, default=os.getcwd(), help="Directory used as CWD when compiling source files.") parser.add_argument("-c", "--precompile", action="append", help="Header file to be precompiled and cached at the start.") parser.add_argument("file", type=str, nargs="+", help="Source file to analyze.") cmdline = parser.parse_args() if cmdline.jobs == 0: cmdline.jobs = max(1, get_cpu_count()) if not cmdline.compilation_root: cmdline.compilation_root = cmdline.verilator_root verilator_root = os.path.abspath(cmdline.verilator_root) default_compilation_root = os.path.abspath(cmdline.compilation_root) compdb: Optional[CompilationDatabase] = None if cmdline.compile_commands_dir: compdb = CompilationDatabase.fromDirectory(cmdline.compile_commands_dir) if cmdline.cxxflags is not None: common_cxxflags = shlex.split(cmdline.cxxflags) else: common_cxxflags = [] precompile_commands_list = [] if cmdline.precompile: hdr_cxxflags = ['-xc++-header'] + common_cxxflags for refid, file in enumerate(cmdline.precompile): filename = os.path.abspath(file) compile_command = CompileCommand(refid, filename, hdr_cxxflags, default_compilation_root) precompile_commands_list.append(compile_command) compile_commands_list = [] for refid, file in enumerate(cmdline.file): filename = os.path.abspath(file) root = default_compilation_root cxxflags = common_cxxflags[:] if compdb: entry = compdb.getCompileCommands(filename) if entry is None: print(f"%Error: reading compile commands failed: {filename}", file=sys.stderr) entry_list = [] else: entry_list = list(entry) # Compilation database can contain multiple entries for single file, # e.g. when it has been updated by appending new entries. # Use last entry for the file, if it exists, as it is the newest one. if len(entry_list) > 0: last_entry = entry_list[-1] root = last_entry.directory entry_args = list(last_entry.arguments) # First argument in compile_commands.json arguments list is # compiler executable name/path. CIndex (libclang) always # implicitly prepends executable name, so it shouldn't be passed # here. cxxflags.extend(entry_args[1:]) compile_command = CompileCommand(refid, filename, cxxflags, root) compile_commands_list.append(compile_command) summary_printer = TopDownSummaryPrinter() if cmdline.jobs == 1: run_analysis(compile_commands_list, precompile_commands_list, summary_printer.handle_diagnostic, verilator_root) else: run_parallel_analysis(compile_commands_list, precompile_commands_list, summary_printer.handle_diagnostic, cmdline.jobs, verilator_root) summary_printer.print_summary(verilator_root) if __name__ == '__main__': main() verilator-5.042/nodist/install_test0000755000542200017500000001216015101701376020045 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # mypy: disallow-untyped-defs # pylint: disable=C0103,C0114,C0115,C0116,C0209,R0801,R0915 ###################################################################### import argparse import multiprocessing import os import shutil import subprocess import sys ###################################################################### def test() -> None: if not os.path.exists("nodist/install_test"): sys.exit("%Error: Run from the top of the verilator kit") cleanenv() if os.path.exists("Makefile"): run("make distclean") # Try building from a scratch area srcdir = os.getcwd() blddir = srcdir + "/test_regress/obj_dir/install_test_bld" prefix = srcdir + "/test_regress/obj_dir/install_test_prefix" testdirp = srcdir + "/test_regress/obj_dir/install_test_testp" testdirn = srcdir + "/test_regress/obj_dir/install_test_testn" if Args.stage <= 0: print("== stage 0") run("/bin/rm -rf " + blddir) run("/bin/mkdir -p " + blddir) # Matches Ubuntu's e.g. /usr/share/pkgconfig/verilator.pc run("cd " + blddir + " && " + srcdir + "/configure --prefix " + prefix + " --exec-prefix " + prefix + " --datarootdir " + prefix + "/share" + " --includedir " + prefix + "/share/verilator/include") run("cd " + blddir + " && make -j " + str(calc_jobs())) # Install it under the prefix if Args.stage <= 1: print("== stage 1") run("/bin/rm -rf " + prefix) run("/bin/mkdir -p " + prefix) run("cd " + blddir + " && make install") run("test -e " + prefix + "/share/man/man1/verilator.1") run("test -e " + prefix + "/share/verilator/examples/make_tracing_c/Makefile") run("test -e " + prefix + "/share/verilator/include/verilated.h") run("test -e " + prefix + "/bin/verilator") run("test -e " + prefix + "/bin/verilator_bin") run("test -e " + prefix + "/bin/verilator_bin_dbg") run("test -e " + prefix + "/bin/verilator_gantt") run("test -e " + prefix + "/bin/verilator_profcfunc") # run a test using just the path if Args.stage <= 2: print("== stage 2") odir = testdirp run("/bin/rm -rf " + odir) run("/bin/mkdir -p " + odir) path = prefix + "/bin" + ":" + prefix + "/share/bin" write_verilog(odir) run("cd " + odir + " && PATH=" + path + ":$PATH verilator --cc top.v --exe sim_main.cpp") run("cd " + odir + "/obj_dir && PATH=" + path + ":$PATH make -f Vtop.mk") run("cd " + odir + " && PATH=" + path + ":$PATH obj_dir/Vtop") # run a test using exact path to binary if Args.stage <= 3: print("== stage 3") odir = testdirn run("/bin/rm -rf " + odir) run("/bin/mkdir -p " + odir) write_verilog(odir) bin1 = prefix + "/bin" run("cd " + odir + " && " + bin1 + "/verilator --cc top.v --exe sim_main.cpp") run("cd " + odir + "/obj_dir && make -f Vtop.mk") run("cd " + odir + "/obj_dir && ./Vtop") if Args.stage <= 9: print("*-* All Finished *-*") def write_verilog(odir: str) -> None: shutil.copy2("examples/make_hello_c/top.v", odir + "/top.v") shutil.copy2("examples/make_hello_c/sim_main.cpp", odir + "/sim_main.cpp") def cleanenv() -> None: for var in os.environ: if var in ('VERILATOR_ROOT', 'VERILATOR_INCLUDE', 'VERILATOR_NO_OPT_BUILD'): print("unset %s # Was '%s'" % (var, os.environ[var])) del os.environ[var] def get_cpu_count() -> int: try: return len(os.sched_getaffinity(0)) except AttributeError: return multiprocessing.cpu_count() def calc_jobs() -> int: return get_cpu_count() + 1 def run(command: str) -> None: # run a system command, check errors print("\t%s" % command) os.system(command) status = subprocess.call(command, shell=True) if status < 0: raise RuntimeError("%Error: Command failed " + command + ", stopped") ####################################################################### ####################################################################### parser = argparse.ArgumentParser( allow_abbrev=False, formatter_class=argparse.RawDescriptionHelpFormatter, description="""install_test performs several make-and-install iterations to verify the Verilator kit. It isn't part of the normal "make test" due to the number of builds required.""", epilog="""Copyright 2009-2025 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") parser.add_argument('--debug', action='store_const', const=9, help='enable debug') parser.add_argument('--stage', type=int, default=0, help='run a specific test stage (see the script)') Args = parser.parse_args() test() ###################################################################### # Local Variables: # compile-command: "cd .. ; nodist/install_test" # End: verilator-5.042/.clang-format0000644000542200017500000000722515101701376016473 0ustar mahmoudyfreeshell--- Language: Cpp # BasedOnStyle: LLVM AccessModifierOffset: -4 AlignAfterOpenBracket: Align AlignConsecutiveAssignments: false AlignConsecutiveDeclarations: false AlignEscapedNewlines: DontAlign AlignOperands: true AlignTrailingComments: false AllowAllParametersOfDeclarationOnNextLine: true AllowShortBlocksOnASingleLine: true AllowShortCaseLabelsOnASingleLine: true AllowShortFunctionsOnASingleLine: All AllowShortIfStatementsOnASingleLine: true AllowShortLoopsOnASingleLine: true AlwaysBreakAfterDefinitionReturnType: None AlwaysBreakAfterReturnType: None AlwaysBreakBeforeMultilineStrings: false AlwaysBreakTemplateDeclarations: true BinPackArguments: true BinPackParameters: true BraceWrapping: AfterClass: false AfterControlStatement: false AfterEnum: false AfterFunction: false AfterNamespace: false AfterObjCDeclaration: false AfterStruct: false AfterUnion: false AfterExternBlock: false BeforeCatch: false BeforeElse: false IndentBraces: false SplitEmptyFunction: true SplitEmptyRecord: true SplitEmptyNamespace: true BreakBeforeBinaryOperators: All BreakBeforeBraces: Attach BreakBeforeInheritanceComma: false BreakBeforeTernaryOperators: true BreakConstructorInitializersBeforeComma: false BreakConstructorInitializers: BeforeComma BreakAfterJavaFieldAnnotations: false BreakStringLiterals: true ColumnLimit: 99 CommentPragmas: '^ IWYU pragma:' CompactNamespaces: false ConstructorInitializerAllOnOneLineOrOnePerLine: false ConstructorInitializerIndentWidth: 4 ContinuationIndentWidth: 4 Cpp11BracedListStyle: true DerivePointerAlignment: false DisableFormat: false ExperimentalAutoDetectBinPacking: false FixNamespaceComments: true ForEachMacros: - Q_FOREACH - BOOST_FOREACH # Include grouping/sorting SortIncludes: true IncludeBlocks: Regroup IncludeCategories: - Regex: '"V3Pch.*\.h"' Priority: -2 # Precompiled headers - Regex: '"(config_build|verilated_config|verilatedos)\.h"' Priority: -1 # Sepecials before main header - Regex: '(<|")verilated.*' Priority: 1 # Runtime headers - Regex: '"V3.*__gen.*\.h"' Priority: 3 # Generated internal headers separately - Regex: '"V3.*"' Priority: 2 # Internal header - Regex: '".*"' Priority: 4 # Other non-system headers - Regex: '<[[:alnum:]_.]+>' Priority: 5 # Simple system headers next - Regex: '<.*>' Priority: 6 # Other system headers next IncludeIsMainRegex: '$' IndentCaseLabels: false IndentPPDirectives: None IndentWidth: 4 IndentWrappedFunctionNames: false JavaScriptQuotes: Leave JavaScriptWrapImports: true KeepEmptyLinesAtTheStartOfBlocks: true MacroBlockBegin: '' MacroBlockEnd: '' MaxEmptyLinesToKeep: 1 NamespaceIndentation: None ObjCBlockIndentWidth: 2 ObjCSpaceAfterProperty: false ObjCSpaceBeforeProtocolList: true PenaltyBreakAssignment: 2 PenaltyBreakBeforeFirstCallParameter: 19 PenaltyBreakComment: 300 PenaltyBreakFirstLessLess: 120 PenaltyBreakString: 1000 PenaltyExcessCharacter: 1000000 PenaltyReturnTypeOnItsOwnLine: 60 PointerAlignment: Left ReflowComments: true SortUsingDeclarations: true SpaceAfterCStyleCast: false SpaceAfterTemplateKeyword: true SpaceBeforeAssignmentOperators: true SpaceBeforeParens: ControlStatements SpaceInEmptyParentheses: false SpacesBeforeTrailingComments: 2 SpacesInAngles: false SpacesInContainerLiterals: true SpacesInCStyleCastParentheses: false SpacesInLineCommentPrefix: Minimum: 0 Maximum: -1 SpacesInParentheses: false SpacesInSquareBrackets: false Standard: Cpp11 TabWidth: 8 UseTab: Never ... verilator-5.042/.gitignore0000644000542200017500000000112715101701376016103 0ustar mahmoudyfreeshell\#* .#* .gdb_history .nfs* *~ *.tidy *.old *.gz *.gz.uu *.html *.info *.log *.1 .*.swp *.tmp *.tex *.pdf /Makefile /.ccache /artifact/ README TAGS autom4te.cache compile_commands.json config.cache config.status configure dddrun* doxygen-doc gdbrun* gmon.out internals.txt ncverilog.history nohup.out verilator-config-version.cmake verilator-config.cmake verilator.pc verilator.txt verilator_bin* verilator_coverage_bin* **/__pycache__/* **/_build/* **/obj_dir/* /.vscode/ /.idea/ /cmake-build-*/ /obj_coverage/ /test_regress/snapshot/ xmverilog.* xrun.history # Normal CMake build directory /build verilator-5.042/test_regress/0000755000542200017500000000000015101701376016623 5ustar mahmoudyfreeshellverilator-5.042/test_regress/Makefile_obj0000644000542200017500000000276115101701376021123 0ustar mahmoudyfreeshell# -*- Makefile -*- #***************************************************************************** # # DESCRIPTION: Verilator Example: Makefile for inside object directory # # This is executed in the object directory, and called by ../Makefile # # Copyright 2003-2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # #***************************************************************************** default: $(VM_PREFIX) include $(VM_PREFIX).mk # So t/t_foobar.cpp is found (due to test_regress using -Mdir) VPATH += ../.. ####################################################################### # Debugging CPPFLAGS += -DVL_DEBUG=1 # Assertions disabled as SystemC libraries are not clean #CPPFLAGS += -D_GLIBCXX_DEBUG # Needed by tracing routines CPPFLAGS += -DTEST_OBJ_DIR=$(TEST_OBJ_DIR) CPPFLAGS += -DVM_PREFIX=$(VM_PREFIX) CPPFLAGS += -DVM_PREFIX_INCLUDE="<$(VM_PREFIX).h>" CPPFLAGS += -DVM_PREFIX_ROOT_INCLUDE="<$(VM_PREFIX)___024root.h>" CPPFLAGS += $(CPPFLAGS_DRIVER) CPPFLAGS += $(CPPFLAGS_DRIVER2) CPPFLAGS += $(CPPFLAGS_ADD) # Reduce spin count for faster testing CPPFLAGS += -DVL_LOCK_SPINS=10000 ifeq ($(CFG_WITH_LONGTESTS),yes) ifeq ($(DRIVER_STD),newest) CPPFLAGS += $(CFG_CXXFLAGS_STD) endif endif ####################################################################### verilator-5.042/test_regress/.gdbinit0000644000542200017500000000002715101701376020243 0ustar mahmoudyfreeshellsource ../src/.gdbinit verilator-5.042/test_regress/t/0000755000542200017500000000000015101701376017066 5ustar mahmoudyfreeshellverilator-5.042/test_regress/t/t_class_imp2.v0000644000542200017500000000211315101701376021631 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; interface class Courier; pure virtual function void deliver(); endclass class Person implements Courier; virtual function void deliver(); $display("slow delivery"); endfunction endclass interface class Seats; pure virtual function int seats(); endclass class Vehicle; endclass class Car extends Vehicle implements Courier, Seats; virtual function void deliver(); $display("fast delivery"); endfunction virtual function int seats(); return 4; endfunction endclass class MetaCar extends Car; endclass function void do_delivery(Courier courier); courier.deliver(); endfunction initial begin MetaCar car; car = new(); do_delivery(car); if (car.seats() != 4) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_force_bad_rw.out0000644000542200017500000000046515101701376022563 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_force_bad_rw.v:14:20: Unsupported: Signals used via read-write reference cannot be forced 14 | foreach (ass[index]) begin | ^~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_param_array8.py0000755000542200017500000000073415101701376022360 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_opt_const_cond_redundant.v0000644000542200017500000000206115101701376024656 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // bug3806 module t ( input clk ); reg [65:0] idx /*verilator public*/; initial idx = 1; wire unlikely = idx > 200; typedef enum logic { UP, DOWN } dir_t; dir_t direction; always_comb direction = idx % 2 == 0 ? UP : DOWN; int ups; // Make computable always @(posedge clk) begin if (idx > 100) begin `ifdef TEST_VERBOSE $write("ups = %0d\n", ups); `endif if (ups != 50049) $stop; $write("*-* All Finished *-*\n"); $finish; end if (direction == UP) ++ups; else if (direction == UP) ++ups; else ups += 1000; case (direction) DOWN: idx = idx + 3; UP: idx = idx - 1; default: begin // This if just gets rid of branch pred on default^ if (unlikely == '1) begin $write("never\n"); end end endcase end endmodule verilator-5.042/test_regress/t/t_clocking_bad2.v0000644000542200017500000000072415101701376022264 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; logic in, out; clocking cb @(posedge clk); default input #1 output #1step; default input #2 output #2; output #1step out; output out; endclocking endmodule verilator-5.042/test_regress/t/t_order.v0000644000542200017500000000677515101701376020732 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); // surefire lint_off ASWEBB // surefire lint_off ASWEMB // surefire lint_off STMINI // surefire lint_off CSEBEQ input clk; reg [7:0] a_to_clk_levm3; reg [7:0] b_to_clk_levm1; reg [7:0] c_com_levs10; reg [7:0] d_to_clk_levm2; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [7:0] m_from_clk_lev1_r; // From a of t_order_a.v wire [7:0] n_from_clk_lev2; // From a of t_order_a.v wire [7:0] o_from_com_levs11; // From a of t_order_a.v wire [7:0] o_from_comandclk_levs12;// From a of t_order_a.v wire [7:0] o_subfrom_clk_lev2; // From b of t_order_b.v // End of automatics reg [7:0] cyc; initial cyc = 0; t_order_a a ( .one (8'h1), /*AUTOINST*/ // Outputs .m_from_clk_lev1_r (m_from_clk_lev1_r[7:0]), .n_from_clk_lev2 (n_from_clk_lev2[7:0]), .o_from_com_levs11 (o_from_com_levs11[7:0]), .o_from_comandclk_levs12(o_from_comandclk_levs12[7:0]), // Inputs .clk (clk), .a_to_clk_levm3 (a_to_clk_levm3[7:0]), .b_to_clk_levm1 (b_to_clk_levm1[7:0]), .c_com_levs10 (c_com_levs10[7:0]), .d_to_clk_levm2 (d_to_clk_levm2[7:0])); t_order_b b ( /*AUTOINST*/ // Outputs .o_subfrom_clk_lev2 (o_subfrom_clk_lev2[7:0]), // Inputs .m_from_clk_lev1_r (m_from_clk_lev1_r[7:0])); reg [7:0] o_from_com_levs12; reg [7:0] o_from_com_levs13; always @ (/*AS*/o_from_com_levs11) begin o_from_com_levs12 = o_from_com_levs11 + 8'h1; o_from_com_levs12 = o_from_com_levs12 + 8'h1; // Test we can add to self and optimize o_from_com_levs13 = o_from_com_levs12; end reg sepassign_in; wire [3:0] sepassign; // verilator lint_off UNOPT assign #0.1 sepassign[0] = 0, sepassign[1] = sepassign[2], sepassign[2] = sepassign[3], sepassign[3] = sepassign_in; wire [7:0] o_subfrom_clk_lev3 = o_subfrom_clk_lev2; // verilator lint_on UNOPT always @ (posedge clk) begin cyc <= cyc+8'd1; sepassign_in <= 0; if (cyc == 8'd1) begin a_to_clk_levm3 <= 0; d_to_clk_levm2 <= 1; b_to_clk_levm1 <= 1; c_com_levs10 <= 2; sepassign_in <= 1; end if (cyc == 8'd2) begin if (sepassign !== 4'b1110) $stop; end if (cyc == 8'd3) begin $display("%d %d %d %d", m_from_clk_lev1_r, n_from_clk_lev2, o_from_com_levs11, o_from_comandclk_levs12); if (m_from_clk_lev1_r !== 8'h2) $stop; if (o_subfrom_clk_lev3 !== 8'h2) $stop; if (n_from_clk_lev2 !== 8'h2) $stop; if (o_from_com_levs11 !== 8'h3) $stop; if (o_from_com_levs13 !== 8'h5) $stop; if (o_from_comandclk_levs12 !== 8'h5) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_display_time.py0000755000542200017500000000100015101701376022440 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_func_dotted.v0000644000542200017500000001047015101701376022100 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); // verilator lint_off MULTIDRIVEN ma ma0 (); initial t.ma0.u_b[0].f(1); initial t.ma0.u_b[0].f(clk); global_mod #(32'hf00d) global_cell (); global_mod #(32'hf22d) global_cell2 (); input clk; integer cyc=1; function [31:0] getName; input fake; getName = "t "; endfunction always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==2) begin if (global_cell. getGlob(1'b0) !== 32'hf00d) $stop; if (global_cell2.getGlob(1'b0) !== 32'hf22d) $stop; end if (cyc==3) begin if (ma0. getName(1'b0) !== "ma ") $stop; if (ma0.mb0. getName(1'b0) !== "mb ") $stop; if (ma0.mb0.mc0.getName(1'b0) !== "mc ") $stop; end if (cyc==4) begin if (ma0.mb0. getP2(1'b0) !== 32'h0) $stop; if (ma0.mb0.mc0.getP3(1'b0) !== 32'h0) $stop; if (ma0.mb0.mc1.getP3(1'b0) !== 32'h1) $stop; end if (cyc==5) begin ma0. checkName(ma0. getName(1'b0)); ma0.mb0. checkName(ma0.mb0. getName(1'b0)); ma0.mb0.mc0.checkName(ma0.mb0.mc0.getName(1'b0)); end if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule `ifdef ATTRIBUTES `ifdef USE_INLINE_MID `define INLINE_MODULE /*verilator inline_module*/ `define INLINE_MID_MODULE /*verilator no_inline_module*/ `else `ifdef USE_INLINE `define INLINE_MODULE /*verilator inline_module*/ `define INLINE_MID_MODULE /*verilator inline_module*/ `else `define INLINE_MODULE /*verilator public_module*/ `define INLINE_MID_MODULE /*verilator public_module*/ `endif `endif `else `define INLINE_MODULE `define INLINE_MID_MODULE `endif module global_mod; `INLINE_MODULE parameter INITVAL = 0; integer globali; initial globali = INITVAL; function [31:0] getName; input fake; getName = "gmod"; endfunction function [31:0] getGlob; input fake; getGlob = globali; endfunction endmodule module ma (); `INLINE_MODULE mb #(0) mb0 (); reg [31:0] gName; initial gName = "ma "; function [31:0] getName; input fake; getName = "ma "; endfunction task checkName; input [31:0] name; if (name !== "ma ") $stop; endtask initial begin if (ma.getName(1'b0) !== "ma ") $stop; if (mb0.getName(1'b0) !== "mb ") $stop; if (mb0.mc0.getName(1'b0) !== "mc ") $stop; end endmodule module mb (); `INLINE_MID_MODULE parameter P2 = 0; mc #(P2,0) mc0 (); mc #(P2,1) mc1 (); global_mod #(32'hf33d) global_cell2 (); reg [31:0] gName; initial gName = "mb "; function [31:0] getName; input fake; getName = "mb "; endfunction function [31:0] getP2 ; input fake; getP2 = P2; endfunction task checkName; input [31:0] name; if (name !== "mb ") $stop; endtask initial begin `ifndef verilator #1; `endif if (ma. getName(1'b0) !== "ma ") $stop; if ( getName(1'b0) !== "mb ") $stop; if (mc1.getName(1'b0) !== "mc ") $stop; ma. checkName (ma. gName); /**/checkName ( gName); mc1.checkName (mc1.gName); ma. checkName (ma. getName(1'b0)); /**/checkName ( getName(1'b0)); mc1.checkName (mc1.getName(1'b0)); end endmodule module mc (); `INLINE_MODULE parameter P2 = 0; parameter P3 = 0; reg [31:0] gName; initial gName = "mc "; function [31:0] getName; input fake; getName = "mc "; endfunction function [31:0] getP3 ; input fake; getP3 = P3; endfunction task checkName; input [31:0] name; if (name !== "mc ") $stop; endtask initial begin `ifndef verilator #1; `endif if (ma.getName(1'b0) !== "ma ") $stop; if (mb.getName(1'b0) !== "mb ") $stop; if (mc.getName(1'b0) !== "mc ") $stop; ma.checkName (ma.gName); mb.checkName (mb.gName); mc.checkName (mc.gName); ma.checkName (ma.getName(1'b0)); mb.checkName (mb.getName(1'b0)); mc.checkName (mc.getName(1'b0)); end endmodule module b; function void f(bit v); $display("%m"); endfunction : f; endmodule : b bind ma b u_b[0:1](); verilator-5.042/test_regress/t/t_func_inout_bit_sel.py0000755000542200017500000000073415101701376023644 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_tri_struct.v0000644000542200017500000000105515101701376022003 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 typedef struct { bit x; } u_struct_t; module u_mh (inout u_struct_t u_i, inout u_struct_t u_o); assign u_o.x = u_i.x; endmodule module t; u_struct_t u_i, u_o; u_mh u_mh(u_i, u_o); initial begin u_i.x = 1; #1; if (u_o.x != 1'b1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_flag_topmodule_bad.out0000644000542200017500000000133615101701376023754 0ustar mahmoudyfreeshell%Warning-MULTITOP: t/t_flag_topmodule.v:15:8: Multiple top level modules : ... Suggest see manual; fix the duplicates, or use --top-module to select top. ... For warning description see https://verilator.org/warn/MULTITOP?v=latest ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message. : ... Top module 'a' 7 | module a; | ^ : ... Top module 'a2' 15 | module a2; | ^~ : ... Top module 'b' 22 | module b; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_assoc_method_bad.py0000755000542200017500000000076315101701376023252 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_x_assign_0.py0000755000542200017500000000124115101701376022016 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_x_assign.cpp" test.top_filename = "t/t_x_assign.v" test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--x-assign 0 --exe", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_randomize_rand_mode_bad.py0000755000542200017500000000076315101701376024602 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dpi_if_cond_c.cpp0000644000542200017500000000231315101701376022653 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2024 by Antmicro. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "svdpi.h" #include #include // These require the above. Comment prevents clang-format moving them #include "TestCheck.h" //====================================================================== // clang-format off #if defined(VERILATOR) # include "Vt_dpi_if_cond__Dpi.h" #elif defined(VCS) # include "../vc_hdrs.h" #elif defined(NC) # define NEED_EXTERNS #else # error "Unknown simulator for DPI test" #endif // clang-format on #ifdef NEED_EXTERNS extern "C" { // If get ncsim: *F,NOFDPI: Function {foo} not found in default libdpi. // Then probably forgot to list a function here. extern int dpii_increment(int* counter); } #endif int dpii_increment(int* counter) { ++(*counter); return 0; } verilator-5.042/test_regress/t/t_specparam.py0000755000542200017500000000076315101701376021747 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=['--binary']) test.execute() test.passes() verilator-5.042/test_regress/t/t_case_auto1.v0000644000542200017500000000543015101701376021626 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; localparam // synopsys enum En_State EP_State_IDLE = {3'b000,5'd00}, EP_State_CMDSHIFT0 = {3'b001,5'd00}, EP_State_CMDSHIFT13 = {3'b001,5'd13}, EP_State_CMDSHIFT14 = {3'b001,5'd14}, EP_State_CMDSHIFT15 = {3'b001,5'd15}, EP_State_CMDSHIFT16 = {3'b001,5'd16}, EP_State_DWAIT = {3'b010,5'd00}, EP_State_DSHIFT0 = {3'b100,5'd00}, EP_State_DSHIFT1 = {3'b100,5'd01}, EP_State_DSHIFT15 = {3'b100,5'd15}; reg [7:0] /* synopsys enum En_State */ m_state_xr; // Last command, for debugging /*AUTOASCIIENUM("m_state_xr", "m_stateAscii_xr", "EP_State_")*/ // Beginning of automatic ASCII enum decoding reg [79:0] m_stateAscii_xr; // Decode of m_state_xr always @(m_state_xr) begin case ({m_state_xr}) EP_State_IDLE: m_stateAscii_xr = "idle "; EP_State_CMDSHIFT0: m_stateAscii_xr = "cmdshift0 "; EP_State_CMDSHIFT13: m_stateAscii_xr = "cmdshift13"; EP_State_CMDSHIFT14: m_stateAscii_xr = "cmdshift14"; EP_State_CMDSHIFT15: m_stateAscii_xr = "cmdshift15"; EP_State_CMDSHIFT16: m_stateAscii_xr = "cmdshift16"; EP_State_DWAIT: m_stateAscii_xr = "dwait "; EP_State_DSHIFT0: m_stateAscii_xr = "dshift0 "; EP_State_DSHIFT1: m_stateAscii_xr = "dshift1 "; EP_State_DSHIFT15: m_stateAscii_xr = "dshift15 "; default: m_stateAscii_xr = "%Error "; endcase end // End of automatics integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; //$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b); if (cyc==1) begin m_state_xr <= EP_State_IDLE; end if (cyc==2) begin if (m_stateAscii_xr != "idle ") $stop; m_state_xr <= EP_State_CMDSHIFT13; end if (cyc==3) begin if (m_stateAscii_xr != "cmdshift13") $stop; m_state_xr <= EP_State_CMDSHIFT16; end if (cyc==4) begin if (m_stateAscii_xr != "cmdshift16") $stop; m_state_xr <= EP_State_DWAIT; end if (cyc==9) begin if (m_stateAscii_xr != "dwait ") $stop; $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.042/test_regress/t/t_gen_defparam_multi.out0000644000542200017500000000205115101701376023762 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_gen_defparam_multi.v:14:17: Unsupported: defparam with no dot 14 | defparam PAR = 5; | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_gen_defparam_multi.v:39:24: Unsupported: defparam with more than one dot 39 | defparam m2.m3.PAR3 = 80; | ^ %Error: t/t_gen_defparam_multi.v:39:25: syntax error, unexpected IDENTIFIER, expecting ',' or ';' 39 | defparam m2.m3.PAR3 = 80; | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error-UNSUPPORTED: t/t_gen_defparam_multi.v:44:24: Unsupported: defparam with more than one dot 44 | defparam m2.m3.PAR3 = 40; | ^ %Error: t/t_gen_defparam_multi.v:44:25: syntax error, unexpected IDENTIFIER, expecting ',' or ';' 44 | defparam m2.m3.PAR3 = 40; | ^~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_clocking_sched.out0000644000542200017500000000113315101701376023077 0ustar mahmoudyfreeshell0 | posedge 0 | cb.y=0 0 | b=0 0 | x<=0 0 | y=0 0 | c<=0 0 | c<=1 0 | cb.a=1 0 | cb.b=1 0 | posedge 0 | x<=1 0 | y=1 0 | c<=0 0 | cb.a=0 0 | cb.b=1 0 | cb.y=1 0 | b=1 0 | x<=0 0 | y=0 0 | 0 1 0 0 0 0 20 | posedge 20 | c<=1 20 | cb.a=1 20 | cb.b=1 20 | cb.y=0 20 | b=0 20 | posedge 20 | x<=1 20 | y=1 20 | c<=0 20 | cb.a=0 20 | cb.b=1 20 | cb.y=1 20 | b=1 20 | x<=0 20 | y=0 20 | 0 1 0 0 0 0 30 | posedge 30 | c<=1 30 | cb.a=1 30 | cb.b=1 30 | cb.y=0 30 | b=0 30 | posedge 30 | x<=1 30 | y=1 30 | c<=0 30 | cb.a=0 30 | cb.b=1 30 | cb.y=1 30 | b=1 30 | x<=0 30 | y=0 30 | 0 1 0 0 0 0 *-* All Finished *-* verilator-5.042/test_regress/t/t_interface_param_genblk.v0000644000542200017500000000246315101701376024247 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Anthony Donlon. // SPDX-License-Identifier: CC0-1.0 // See #4664 interface intf #( parameter A = 10 ); localparam B = A / A + 1; // 2 logic [A/10-1:0] sig; endinterface module t; intf #( .A(100) ) intf(); sub i_sub ( .intf ); endmodule module sub ( intf intf // Having this named same "intf intf" important for V3LinkDot coverage ); if (intf.A == 10) begin $error("incorrect"); end else if (intf.A / intf.B == 50) begin // end else if (intf.A / $bits(intf.sig) == 10) begin // TODO: support this $info("correct"); end else begin $error("incorrect"); end for (genvar i = intf.A - 2; i < intf.A + 1; i += intf.B) begin for (genvar j = intf.B; j > intf.A - 100; j--) begin if (i < intf.A - 2) $error("error"); if (i > intf.A) $error("error"); $info("i = %0d, j = %0d", i, j); end end case (intf.A) 10, intf.A - 10: $error("incorrect"); intf.B * 50: $info("correct"); 30: $error("incorrect"); default: $error("incorrect"); endcase endmodule verilator-5.042/test_regress/t/t_dist_cppstyle.py0000755000542200017500000000663715101701376022670 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Primitive C++ style checker # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') def get_source_files(): git_files = test.run_capture("cd " + test.root + " && git ls-files") if test.verbose: print("MF " + git_files) files = {} for filename in git_files.split(): if filename == '': continue files[filename] = True return files def check_pattern(filename, contents, pattern, not_pattern, message): # Pattern uses match, so must include skipping leading whitespace if necessary lineno = 0 buffer_lineno = 0 buffer = "\n" for line in contents.splitlines(): lineno += 1 if buffer == "\n": buffer_lineno = lineno if line != "": # Don't do whole file at once - see issue #4085 # Build a buffer until a newline so we check a block at a time. buffer += line + "\n" continue m = re.search(r"\n" + pattern, buffer) if m: if not not_pattern or not re.search(not_pattern, buffer): test.error_keep_going(filename + ":" + str(buffer_lineno) + ": " + message + m.group(0)) buffer = "\n" if not os.path.exists(test.root + "/.git"): test.skip("Not in a git repository") files = get_source_files() for filename in sorted(files.keys()): filename = os.path.join(test.root, filename) if not os.path.exists(filename): # git file might be deleted but not yet staged continue if not re.search(r'\.(h|c|cpp)(\.in)?$', filename): continue if '/gtkwave/' in filename: continue contents = test.file_contents(filename) + "\n\n" check_pattern(filename, contents, r"[^\']*virtual[^{};\n]+override[^\n]*", None, "'virtual' keyword is redundant on 'override' method") check_pattern(filename, contents, r' \s*(\w+ )*\s*(inline) [^;]+?\([^;]*?\)[^;]+?(?:{|:|=\s*default[^\n]*)', None, "'inline' keyword is redundant on method definitions inside classes") check_pattern( filename, contents, r'\s*inline \S+ [^;:(]+::[^;:(]+\([^;]*\)[^;]+{[^\n]*', r'template', "Use 'inline' only on declaration inside classes" " (except for template specializations)") check_pattern( filename, contents, r'.*[( ]new [a-zA-Z0-9]+\([^\n]*', # Ignore common ok narrowing conversions, on int vs uint32_t arguments r'(Need \(\)|new AstArraySel|new AstConst|new AstRange)', "Use brace instead of parenthesis-style new constructors e.g. 'new ...{...}'") check_pattern( filename, contents, r'.*(\n *[:,]|,\n) +m_[a-zA-Z0-9]+\(', # Ignore common m_e enum constructors r'.*(Need \(\)|: m_e\()|V3OPTION_PARSER_DEF', "Use brace instead of parenthesis-style constructors e.g. ': m_...{...}'") if re.search(r'\.(c|cpp)', filename): check_pattern(filename, contents, r'(\w+\s+)*(\binline\b)[^\n]*', None, "'inline' keyword is on functions defined in .cpp files") test.passes() verilator-5.042/test_regress/t/t_let_stmt_bad.v0000644000542200017500000000062015101701376022237 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; wire clk; let letf(x) = (x << 1); always @(posedge clk) begin case (0) 0: letf(0); // Bad, need a statement endcase end endmodule verilator-5.042/test_regress/t/t_class_imp2.py0000755000542200017500000000073415101701376022026 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_array_saif.py0000755000542200017500000000136115101701376023265 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_trace_array.v" test.golden_filename = "t/t_trace_array_saif.out" test.compile(verilator_flags2=['--cc --trace-saif --trace-structs --trace-max-width 0']) test.execute() # saif_identical is very slow, so require exact match test.files_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_constraint_dist_randc_bad.v0000644000542200017500000000053715101701376024771 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls1; randc int rc; constraint c_bad { rc dist {3 := 0, 10 := 5}; } // Bad, no dist on randc endclass module t; endmodule verilator-5.042/test_regress/t/t_inst_dtree_inlad.py0000755000542200017500000000111615101701376023274 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_inst_dtree.v" test.compile(v_flags2=['+define+INLINE_A +define+INLINE_D'], verilator_flags2=['-trace']) test.execute() test.passes() verilator-5.042/test_regress/t/t_timing_pong.v0000644000542200017500000000130215101701376022106 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; event ping; event pong; int cnt = 0; initial forever @ping begin `ifdef TEST_VERBOSE $write("ping\n"); `endif cnt++; ->pong; end initial forever @pong begin `ifdef TEST_VERBOSE $write("pong\n"); `endif if (cnt < 10) ->ping; end initial #1 ->ping; initial #2 if (cnt == 10) begin $write("*-* All Finished *-*\n"); $finish; end else $stop; initial #3 $stop; // timeout endmodule verilator-5.042/test_regress/t/t_hier_block_type_param_typedef.v0000644000542200017500000000157615101701376025653 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t( clk ); input clk; logic [21:0] in1; logic [21:0] out1; assign in1 = 0; typedef logic[21:0] PARAM_T; Test #(.TYPE_t(PARAM_T)) test(.out (out1), .in (in1)); logic [63:0] in2; logic [63:0] out2; assign in2 = 0; typedef logic[63:0] PARAM2_T; Test #(.TYPE_t(PARAM2_T)) test2(.out (out2), .in (in2)); always @ (posedge clk) begin if (out1 !== ~in1) $stop; if (out2 !== ~in2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module Test #(parameter type TYPE_t = logic [4:0]) ( output TYPE_t out, input TYPE_t in ); /*verilator hier_block*/ assign out = ~ in; endmodule verilator-5.042/test_regress/t/t_sys_file_basic_uz.v0000644000542200017500000000743015101701376023300 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2030 by Stephen Henry. // SPDX-License-Identifier: CC0-1.0 module t; int fdin_bin, fdout_txt, fdout_bin; `define STRINGIFY(x) `"x`" `define checkh(gotv,expv) \ do if ((gotv) !== (expv)) begin\ $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv));\ end while(0) // // task automatic test1; begin for (int i = 0; i < 256; i++) begin byte actual, expected; expected = i[7:0]; $fscanf(fdin_bin, "%u", actual); `checkh(actual, expected); $fdisplay(fdout_txt, "%h", actual); $fwrite(fdout_bin, "%u", actual); end for (int i = 0; i < 256; i++) begin shortint actual, expected; for (int j = 0; j < 2; j++) expected[(8 * j)+:8] = i[7:0] + j[7:0]; $fscanf(fdin_bin, "%u", actual); `checkh(actual, expected); $fdisplay(fdout_txt, "%h", actual); $fwrite(fdout_bin, "%u", actual); end for (int i = 0; i < 256; i++) begin int actual, expected; for (int j = 0; j < 4; j++) expected[(8 * j)+:8] = i[7:0] + j[7:0]; $fscanf(fdin_bin, "%u", actual); `checkh(actual, expected); $fdisplay(fdout_txt, "%h", actual); $fwrite(fdout_bin, "%u", actual); end for (int i = 0; i < 256; i++) begin longint actual, expected; for (int j = 0; j < 8; j++) expected[(8 * j)+:8] = i[7:0] + j[7:0]; $fscanf(fdin_bin, "%u", actual); `checkh(actual, expected); $fdisplay(fdout_txt, "%h", actual); $fwrite(fdout_bin, "%u", actual); end end endtask // // task automatic test2; begin for (int i = 0; i < 256; i++) begin byte actual, expected; expected = i[7:0]; $fscanf(fdin_bin, "%z", actual); `checkh(actual, expected); $fdisplay(fdout_txt, "%h", actual); $fwrite(fdout_bin, "%z", actual); end for (int i = 0; i < 256; i++) begin shortint actual, expected; for (int j = 0; j < 2; j++) expected[(8 * j)+:8] = i[7:0] + j[7:0]; $fscanf(fdin_bin, "%z", actual); `checkh(actual, expected); $fdisplay(fdout_txt, "%h", actual); $fwrite(fdout_bin, "%z", actual); end for (int i = 0; i < 256; i++) begin int actual, expected; for (int j = 0; j < 4; j++) expected[(8 * j)+:8] = i[7:0] + j[7:0]; $fscanf(fdin_bin, "%z", actual); `checkh(actual, expected); $fdisplay(fdout_txt, "%h", actual); $fwrite(fdout_bin, "%z", actual); end for (int i = 0; i < 256; i++) begin longint actual, expected; for (int j = 0; j < 8; j++) expected[(8 * j)+:8] = i[7:0] + j[7:0]; $fscanf(fdin_bin, "%z", actual); `checkh(actual, expected); $fdisplay(fdout_txt, "%h", actual); $fwrite(fdout_bin, "%z", actual); end end endtask initial begin : main_PROC string filename; filename = "t/t_sys_file_basic_uz.dat"; fdin_bin = $fopen(filename, "rb"); `ifdef IVERILOG filename = $sformatf("%s/t_sys_file_basic_uz_test.log","obj_iv/t_sys_file_basic_uz"); `else filename = $sformatf("%s/t_sys_file_basic_uz_test.log",`STRINGIFY(`TEST_OBJ_DIR)); `endif fdout_txt = $fopen(filename, "w"); `ifdef IVERILOG filename = $sformatf("%s/t_sys_file_basic_uz_test.bin","obj_iv/t_sys_file_basic_uz"); `else filename = $sformatf("%s/t_sys_file_basic_uz_test.bin",`STRINGIFY(`TEST_OBJ_DIR)); `endif $display(filename); fdout_bin = $fopen(filename, "wb"); test1; test2; $fclose(fdin_bin); $fclose(fdout_txt); $write("*-* All Finished *-*\n"); $finish(0); // Test arguments to finish end // block: main_PROC `undef STRINGIFY endmodule // t verilator-5.042/test_regress/t/t_flag_prefix_bad.out0000644000542200017500000000030115101701376023230 0ustar mahmoudyfreeshell%Error: --prefix argument must be a legal C++ identifier: 'bad/name' ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_vpi_multidim.py0000755000542200017500000000131315101701376022466 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(make_top_shell=False, make_main=False, make_pli=True, v_flags2=["+define+USE_VPI_NOT_DPI"], verilator_flags2=["--exe --vpi --no-l2name --public-flat-rw", test.pli_filename]) test.execute(use_libvpi=True) test.passes() verilator-5.042/test_regress/t/t_assoc_wildcard.v0000644000542200017500000000327215101701376022565 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; integer i; always @ (posedge clk) begin cyc <= cyc + 1; begin // Wildcard typedef string dict_t [*]; static string a [*] = '{default: "nope", "BBBBB": "fooing", 23'h434343: "baring"}; static dict_t b = '{default: "nope", "BBBBB": "fooing", 23'h434343: "baring"}; int k; string v; v = b["CCC"]; `checks(v, "baring"); v = b["BBBBB"]; `checks(v, "fooing"); v = a["CCC"]; `checks(v, "baring"); v = a["BBBBB"]; `checks(v, "fooing"); a[32'd1234] = "fooed"; a[4'd3] = "bared"; a[79'h4141] = "bazed"; i = a.num(); `checkh(i, 5); i = a.size(); `checkh(i, 5); v = a[39'd1234]; `checks(v, "fooed"); v = a["AA"]; `checks(v, "bazed"); v = a[4'd3]; `checks(v, "bared"); i = a.exists("baz"); `checkh(i, 0); i = a.exists(4'd3); `checkh(i, 1); a.delete(4'd3); i = a.size(); `checkh(i, 4); end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_func_types.v0000644000542200017500000000407715101701376021767 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; function int int123(); int123 = 32'h123; endfunction function bit f_bit ; input bit i; f_bit = ~i; endfunction function int f_int ; input int i; f_int = ~i; endfunction function byte f_byte ; input byte i; f_byte = ~i; endfunction function shortint f_shortint; input shortint i; f_shortint = ~i; endfunction function longint f_longint ; input longint i; f_longint = ~i; endfunction function chandle f_chandle ; input chandle i; f_chandle = i; endfunction // Note there's no "input" here vvvv, it's the default function bit g_bit (bit i); g_bit = ~i; endfunction function int g_int (int i); g_int = ~i; endfunction function byte g_byte (byte i); g_byte = ~i; endfunction function shortint g_shortint(shortint i); g_shortint = ~i; endfunction function longint g_longint (longint i); g_longint = ~i; endfunction function chandle g_chandle (chandle i); g_chandle = i; endfunction chandle c; initial begin if (int123() !== 32'h123) $stop; if (f_bit(1'h1) !== 1'h0) $stop; if (f_bit(1'h0) !== 1'h1) $stop; if (f_int(32'h1) !== 32'hfffffffe) $stop; if (f_byte(8'h1) !== 8'hfe) $stop; if (f_shortint(16'h1) !== 16'hfffe) $stop; if (f_longint(64'h1) !== 64'hfffffffffffffffe) $stop; if (f_chandle(c) !== c) $stop; if (g_bit(1'h1) !== 1'h0) $stop; if (g_bit(1'h0) !== 1'h1) $stop; if (g_int(32'h1) !== 32'hfffffffe) $stop; if (g_byte(8'h1) !== 8'hfe) $stop; if (g_shortint(16'h1) !== 16'hfffe) $stop; if (g_longint(64'h1) !== 64'hfffffffffffffffe) $stop; if (g_chandle(c) !== c) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_interface1_noinl.py0000755000542200017500000000103315101701376023203 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface1.v" test.compile(v_flags2=["-fno-inline"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_dpi_string.v0000644000542200017500000000126315101701376021744 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (); import "DPI-C" function int dpii_string(input string DSM_NAME); generate begin : DSM string SOME_STRING; end endgenerate initial begin $sformat(DSM.SOME_STRING, "%m"); if (dpii_string(DSM.SOME_STRING) != 5) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_flag_relinc_dir/0000755000542200017500000000000015101701376022514 5ustar mahmoudyfreeshellverilator-5.042/test_regress/t/t_flag_relinc_dir/chip/0000755000542200017500000000000015101701376023437 5ustar mahmoudyfreeshellverilator-5.042/test_regress/t/t_flag_relinc_dir/chip/t_flag_relinc_sub.v0000644000542200017500000000074115101701376027271 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2017 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `include "../include/t_flag_relinc.vh" module t_flag_relinc_sub (); initial begin `all_finished; $finish; end endmodule verilator-5.042/test_regress/t/t_flag_relinc_dir/include/0000755000542200017500000000000015101701376024137 5ustar mahmoudyfreeshellverilator-5.042/test_regress/t/t_flag_relinc_dir/include/t_flag_relinc.vh0000644000542200017500000000061415101701376027267 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2017 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `define all_finished $write("*-* All Finished *-*\n") verilator-5.042/test_regress/t/t_alias_var_bad.py0000755000542200017500000000076315101701376022543 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dfg_regularize_circular.v0000644000542200017500000000056215101701376024460 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module A ( output [2:0] Y ); endmodule module B; wire [2:0] w1; wire w2; A A ( .Y({ w1[2], w1[0], w2 }) ); assign w1[1] = w1[2]; endmodule verilator-5.042/test_regress/t/t_covergroup_with_sample_args_too_many_bad.v0000644000542200017500000000075115101701376030121 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off COVERIGN */ module t; covergroup cg_with_sample(int init) with function sample (int addr, bit is_read = 1'b0); endgroup cg_with_sample cov1 = new(7); function void run(); cov1.sample(5, 1'b0, 42); // Too many arguments endfunction endmodule verilator-5.042/test_regress/t/t_interface_nest.py0000755000542200017500000000073415101701376022763 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_new_scoped_bad.py0000755000542200017500000000076615101701376024120 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_vlcov_data_a.dat0000644000542200017500000000026715101701376022532 0ustar mahmoudyfreeshell# SystemC::Coverage-3 C 'CoverPoint0ffile1.sphl159' 0 C 'CoverPoint1ffile1.sphl159' 1 C 'CoverPoint2ffile1.sphl159' 10 C 'CoverPoint3ffile1.sphl159' 0 verilator-5.042/test_regress/t/t_alw_combdly.py0000755000542200017500000000073415101701376022266 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_case_reducer.v0000644000542200017500000002610415101701376022227 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [7:0] operand_a = crc[7:0]; wire [7:0] operand_b = crc[15:8]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [6:0] out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out (out[6:0]), // Inputs .clk (clk), .operand_a (operand_a[7:0]), .operand_b (operand_b[7:0])); // Aggregate outputs into a single result vector wire [63:0] result = {57'h0, out}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h8a78c2ec4946ac38 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test ( // Inputs input wire clk, input wire [7:0] operand_a, // operand a input wire [7:0] operand_b, // operand b // Outputs output wire [6:0] out ); wire [6:0] clz_a; wire [6:0] clz_b; clz u_clz_a ( // Inputs .data_i (operand_a), .out (clz_a)); clz u_clz_b ( // Inputs .data_i (operand_b), .out (clz_b)); assign out = clz_a - clz_b; `ifdef TEST_VERBOSE always @(posedge clk) $display("Out(%x) = clz_a(%x) - clz_b(%x)", out, clz_a, clz_b); `endif endmodule `define def_0000_001x 8'b0000_0010, 8'b0000_0011 `define def_0000_01xx 8'b0000_0100, 8'b0000_0101, 8'b0000_0110, 8'b0000_0111 `define def_0000_10xx 8'b0000_1000, 8'b0000_1001, 8'b0000_1010, 8'b0000_1011 `define def_0000_11xx 8'b0000_1100, 8'b0000_1101, 8'b0000_1110, 8'b0000_1111 `define def_0000_1xxx `def_0000_10xx, `def_0000_11xx `define def_0001_00xx 8'b0001_0000, 8'b0001_0001, 8'b0001_0010, 8'b0001_0011 `define def_0001_01xx 8'b0001_0100, 8'b0001_0101, 8'b0001_0110, 8'b0001_0111 `define def_0001_10xx 8'b0001_1000, 8'b0001_1001, 8'b0001_1010, 8'b0001_1011 `define def_0001_11xx 8'b0001_1100, 8'b0001_1101, 8'b0001_1110, 8'b0001_1111 `define def_0010_00xx 8'b0010_0000, 8'b0010_0001, 8'b0010_0010, 8'b0010_0011 `define def_0010_01xx 8'b0010_0100, 8'b0010_0101, 8'b0010_0110, 8'b0010_0111 `define def_0010_10xx 8'b0010_1000, 8'b0010_1001, 8'b0010_1010, 8'b0010_1011 `define def_0010_11xx 8'b0010_1100, 8'b0010_1101, 8'b0010_1110, 8'b0010_1111 `define def_0011_00xx 8'b0011_0000, 8'b0011_0001, 8'b0011_0010, 8'b0011_0011 `define def_0011_01xx 8'b0011_0100, 8'b0011_0101, 8'b0011_0110, 8'b0011_0111 `define def_0011_10xx 8'b0011_1000, 8'b0011_1001, 8'b0011_1010, 8'b0011_1011 `define def_0011_11xx 8'b0011_1100, 8'b0011_1101, 8'b0011_1110, 8'b0011_1111 `define def_0100_00xx 8'b0100_0000, 8'b0100_0001, 8'b0100_0010, 8'b0100_0011 `define def_0100_01xx 8'b0100_0100, 8'b0100_0101, 8'b0100_0110, 8'b0100_0111 `define def_0100_10xx 8'b0100_1000, 8'b0100_1001, 8'b0100_1010, 8'b0100_1011 `define def_0100_11xx 8'b0100_1100, 8'b0100_1101, 8'b0100_1110, 8'b0100_1111 `define def_0101_00xx 8'b0101_0000, 8'b0101_0001, 8'b0101_0010, 8'b0101_0011 `define def_0101_01xx 8'b0101_0100, 8'b0101_0101, 8'b0101_0110, 8'b0101_0111 `define def_0101_10xx 8'b0101_1000, 8'b0101_1001, 8'b0101_1010, 8'b0101_1011 `define def_0101_11xx 8'b0101_1100, 8'b0101_1101, 8'b0101_1110, 8'b0101_1111 `define def_0110_00xx 8'b0110_0000, 8'b0110_0001, 8'b0110_0010, 8'b0110_0011 `define def_0110_01xx 8'b0110_0100, 8'b0110_0101, 8'b0110_0110, 8'b0110_0111 `define def_0110_10xx 8'b0110_1000, 8'b0110_1001, 8'b0110_1010, 8'b0110_1011 `define def_0110_11xx 8'b0110_1100, 8'b0110_1101, 8'b0110_1110, 8'b0110_1111 `define def_0111_00xx 8'b0111_0000, 8'b0111_0001, 8'b0111_0010, 8'b0111_0011 `define def_0111_01xx 8'b0111_0100, 8'b0111_0101, 8'b0111_0110, 8'b0111_0111 `define def_0111_10xx 8'b0111_1000, 8'b0111_1001, 8'b0111_1010, 8'b0111_1011 `define def_0111_11xx 8'b0111_1100, 8'b0111_1101, 8'b0111_1110, 8'b0111_1111 `define def_1000_00xx 8'b1000_0000, 8'b1000_0001, 8'b1000_0010, 8'b1000_0011 `define def_1000_01xx 8'b1000_0100, 8'b1000_0101, 8'b1000_0110, 8'b1000_0111 `define def_1000_10xx 8'b1000_1000, 8'b1000_1001, 8'b1000_1010, 8'b1000_1011 `define def_1000_11xx 8'b1000_1100, 8'b1000_1101, 8'b1000_1110, 8'b1000_1111 `define def_1001_00xx 8'b1001_0000, 8'b1001_0001, 8'b1001_0010, 8'b1001_0011 `define def_1001_01xx 8'b1001_0100, 8'b1001_0101, 8'b1001_0110, 8'b1001_0111 `define def_1001_10xx 8'b1001_1000, 8'b1001_1001, 8'b1001_1010, 8'b1001_1011 `define def_1001_11xx 8'b1001_1100, 8'b1001_1101, 8'b1001_1110, 8'b1001_1111 `define def_1010_00xx 8'b1010_0000, 8'b1010_0001, 8'b1010_0010, 8'b1010_0011 `define def_1010_01xx 8'b1010_0100, 8'b1010_0101, 8'b1010_0110, 8'b1010_0111 `define def_1010_10xx 8'b1010_1000, 8'b1010_1001, 8'b1010_1010, 8'b1010_1011 `define def_1010_11xx 8'b1010_1100, 8'b1010_1101, 8'b1010_1110, 8'b1010_1111 `define def_1011_00xx 8'b1011_0000, 8'b1011_0001, 8'b1011_0010, 8'b1011_0011 `define def_1011_01xx 8'b1011_0100, 8'b1011_0101, 8'b1011_0110, 8'b1011_0111 `define def_1011_10xx 8'b1011_1000, 8'b1011_1001, 8'b1011_1010, 8'b1011_1011 `define def_1011_11xx 8'b1011_1100, 8'b1011_1101, 8'b1011_1110, 8'b1011_1111 `define def_1100_00xx 8'b1100_0000, 8'b1100_0001, 8'b1100_0010, 8'b1100_0011 `define def_1100_01xx 8'b1100_0100, 8'b1100_0101, 8'b1100_0110, 8'b1100_0111 `define def_1100_10xx 8'b1100_1000, 8'b1100_1001, 8'b1100_1010, 8'b1100_1011 `define def_1100_11xx 8'b1100_1100, 8'b1100_1101, 8'b1100_1110, 8'b1100_1111 `define def_1101_00xx 8'b1101_0000, 8'b1101_0001, 8'b1101_0010, 8'b1101_0011 `define def_1101_01xx 8'b1101_0100, 8'b1101_0101, 8'b1101_0110, 8'b1101_0111 `define def_1101_10xx 8'b1101_1000, 8'b1101_1001, 8'b1101_1010, 8'b1101_1011 `define def_1101_11xx 8'b1101_1100, 8'b1101_1101, 8'b1101_1110, 8'b1101_1111 `define def_1110_00xx 8'b1110_0000, 8'b1110_0001, 8'b1110_0010, 8'b1110_0011 `define def_1110_01xx 8'b1110_0100, 8'b1110_0101, 8'b1110_0110, 8'b1110_0111 `define def_1110_10xx 8'b1110_1000, 8'b1110_1001, 8'b1110_1010, 8'b1110_1011 `define def_1110_11xx 8'b1110_1100, 8'b1110_1101, 8'b1110_1110, 8'b1110_1111 `define def_1111_00xx 8'b1111_0000, 8'b1111_0001, 8'b1111_0010, 8'b1111_0011 `define def_1111_01xx 8'b1111_0100, 8'b1111_0101, 8'b1111_0110, 8'b1111_0111 `define def_1111_10xx 8'b1111_1000, 8'b1111_1001, 8'b1111_1010, 8'b1111_1011 `define def_1111_11xx 8'b1111_1100, 8'b1111_1101, 8'b1111_1110, 8'b1111_1111 `define def_0001_xxxx `def_0001_00xx, `def_0001_01xx, `def_0001_10xx, `def_0001_11xx `define def_0010_xxxx `def_0010_00xx, `def_0010_01xx, `def_0010_10xx, `def_0010_11xx `define def_0011_xxxx `def_0011_00xx, `def_0011_01xx, `def_0011_10xx, `def_0011_11xx `define def_0100_xxxx `def_0100_00xx, `def_0100_01xx, `def_0100_10xx, `def_0100_11xx `define def_0101_xxxx `def_0101_00xx, `def_0101_01xx, `def_0101_10xx, `def_0101_11xx `define def_0110_xxxx `def_0110_00xx, `def_0110_01xx, `def_0110_10xx, `def_0110_11xx `define def_0111_xxxx `def_0111_00xx, `def_0111_01xx, `def_0111_10xx, `def_0111_11xx `define def_1000_xxxx `def_1000_00xx, `def_1000_01xx, `def_1000_10xx, `def_1000_11xx `define def_1001_xxxx `def_1001_00xx, `def_1001_01xx, `def_1001_10xx, `def_1001_11xx `define def_1010_xxxx `def_1010_00xx, `def_1010_01xx, `def_1010_10xx, `def_1010_11xx `define def_1011_xxxx `def_1011_00xx, `def_1011_01xx, `def_1011_10xx, `def_1011_11xx `define def_1100_xxxx `def_1100_00xx, `def_1100_01xx, `def_1100_10xx, `def_1100_11xx `define def_1101_xxxx `def_1101_00xx, `def_1101_01xx, `def_1101_10xx, `def_1101_11xx `define def_1110_xxxx `def_1110_00xx, `def_1110_01xx, `def_1110_10xx, `def_1110_11xx `define def_1111_xxxx `def_1111_00xx, `def_1111_01xx, `def_1111_10xx, `def_1111_11xx `define def_1xxx_xxxx `def_1000_xxxx, `def_1001_xxxx, `def_1010_xxxx, `def_1011_xxxx, \ `def_1100_xxxx, `def_1101_xxxx, `def_1110_xxxx, `def_1111_xxxx `define def_01xx_xxxx `def_0100_xxxx, `def_0101_xxxx, `def_0110_xxxx, `def_0111_xxxx `define def_001x_xxxx `def_0010_xxxx, `def_0011_xxxx module clz( input wire [7:0] data_i, output wire [6:0] out ); // ----------------------------- // Reg declarations // ----------------------------- reg [2:0] clz_byte0; reg [2:0] clz_byte1; reg [2:0] clz_byte2; reg [2:0] clz_byte3; always @* case (data_i) `def_1xxx_xxxx : clz_byte0 = 3'b000; `def_01xx_xxxx : clz_byte0 = 3'b001; `def_001x_xxxx : clz_byte0 = 3'b010; `def_0001_xxxx : clz_byte0 = 3'b011; `def_0000_1xxx : clz_byte0 = 3'b100; `def_0000_01xx : clz_byte0 = 3'b101; `def_0000_001x : clz_byte0 = 3'b110; 8'b0000_0001 : clz_byte0 = 3'b111; 8'b0000_0000 : clz_byte0 = 3'b111; default : clz_byte0 = 3'bxxx; endcase always @* case (data_i) `def_1xxx_xxxx : clz_byte1 = 3'b000; `def_01xx_xxxx : clz_byte1 = 3'b001; `def_001x_xxxx : clz_byte1 = 3'b010; `def_0001_xxxx : clz_byte1 = 3'b011; `def_0000_1xxx : clz_byte1 = 3'b100; `def_0000_01xx : clz_byte1 = 3'b101; `def_0000_001x : clz_byte1 = 3'b110; 8'b0000_0001 : clz_byte1 = 3'b111; 8'b0000_0000 : clz_byte1 = 3'b111; default : clz_byte1 = 3'bxxx; endcase always @* case (data_i) `def_1xxx_xxxx : clz_byte2 = 3'b000; `def_01xx_xxxx : clz_byte2 = 3'b001; `def_001x_xxxx : clz_byte2 = 3'b010; `def_0001_xxxx : clz_byte2 = 3'b011; `def_0000_1xxx : clz_byte2 = 3'b100; `def_0000_01xx : clz_byte2 = 3'b101; `def_0000_001x : clz_byte2 = 3'b110; 8'b0000_0001 : clz_byte2 = 3'b111; 8'b0000_0000 : clz_byte2 = 3'b111; default : clz_byte2 = 3'bxxx; endcase always @* case (data_i) `def_1xxx_xxxx : clz_byte3 = 3'b000; `def_01xx_xxxx : clz_byte3 = 3'b001; `def_001x_xxxx : clz_byte3 = 3'b010; `def_0001_xxxx : clz_byte3 = 3'b011; `def_0000_1xxx : clz_byte3 = 3'b100; `def_0000_01xx : clz_byte3 = 3'b101; `def_0000_001x : clz_byte3 = 3'b110; 8'b0000_0001 : clz_byte3 = 3'b111; 8'b0000_0000 : clz_byte3 = 3'b111; default : clz_byte3 = 3'bxxx; endcase assign out = {4'b0000, clz_byte1}; endmodule // clz verilator-5.042/test_regress/t/t_math_wide_bad.out0000644000542200017500000000312315101701376022710 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_math_wide_bad.v:34:19: Unsupported: operator ISTORD operator of 64 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h 34 | assign r = real'(a); | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_math_wide_bad.v:28:18: Unsupported: operator POWSS operator of 5472 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h 28 | assign z2 = a ** 3; | ^~ %Error-UNSUPPORTED: t/t_math_wide_bad.v:27:17: Unsupported: operator MULS operator of 5472 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h 27 | assign z = a * b; | ^ %Error-UNSUPPORTED: t/t_math_wide_bad.v:29:18: Unsupported: operator DIVS operator of 5472 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h 29 | assign z3 = a / b; | ^ %Error-UNSUPPORTED: t/t_math_wide_bad.v:30:18: Unsupported: operator MODDIVS operator of 5472 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h 30 | assign z4 = a % b; | ^ %Error-UNSUPPORTED: t/t_math_wide_bad.v:31:19: Unsupported: operator DIV operator of 5472 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h 31 | assign z5 = ua / ub; | ^ %Error-UNSUPPORTED: t/t_math_wide_bad.v:32:19: Unsupported: operator MODDIV operator of 5472 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h 32 | assign z6 = ua % ub; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_fork_jumpblock.v0000644000542200017500000000072215101701376022610 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class bar; task foo(logic r); int a, b; if (r) return; fork a = #1 b; join_none endtask endclass module t; bar b = new; initial begin b.foo(0); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_cover_lib_c.cpp0000644000542200017500000000710115101701376022362 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2017 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "verilated_cov.h" #include "svdpi.h" #include #include #include // These require the above. Comment prevents clang-format moving them #include "TestCheck.h" #include VM_PREFIX_INCLUDE //====================================================================== double sc_time_stamp() { return 0; } int errors = 0; //====================================================================== const char* name() { return "main"; } void hier_insert(VerilatedCovContext* covContextp, uint64_t* countp, const char* hierp, const char* peri) { // This needs to be a function at one line number so all of the // line numbers for coverage are constant, otherwise instances won't combine. VL_COVER_INSERT(covContextp, name(), countp, "hier", hierp, "per_instance", peri); } int main() { uint32_t covers[1]; uint64_t coverw[6]; VerilatedCovContext* covContextp = Verilated::defaultContextp()->coveragep(); VL_COVER_INSERT(covContextp, name(), &covers[0], "comment", "kept_one"); VL_COVER_INSERT(covContextp, name(), &coverw[0], "comment", "kept_two"); VL_COVER_INSERT(covContextp, name(), &coverw[1], "comment", "lost_three"); hier_insert(covContextp, &coverw[2], "top.a0.pi", "0"); hier_insert(covContextp, &coverw[3], "top.a1.pi", "0"); hier_insert(covContextp, &coverw[4], "top.a0.npi", "1"); hier_insert(covContextp, &coverw[5], "top.a1.npi", "1"); covers[0] = 100; coverw[0] = 210; coverw[1] = 220; coverw[2] = 200; coverw[3] = 300; coverw[4] = 200; coverw[5] = 300; #ifdef T_COVER_LIB TEST_CHECK_EQ(covContextp->defaultFilename(), "coverage.dat"); covContextp->write(VL_STRINGIFY(TEST_OBJ_DIR) "/coverage1.dat"); covContextp->forcePerInstance(true); covContextp->write(VL_STRINGIFY(TEST_OBJ_DIR) "/coverage1_per_instance.dat"); covContextp->forcePerInstance(false); covContextp->clearNonMatch("kept_"); covContextp->write(VL_STRINGIFY(TEST_OBJ_DIR) "/coverage2.dat"); covContextp->zero(); covContextp->write(VL_STRINGIFY(TEST_OBJ_DIR) "/coverage3.dat"); covContextp->clear(); Verilated::defaultContextp()->coverageFilename(VL_STRINGIFY(TEST_OBJ_DIR) "/coverage4.dat"); TEST_CHECK_EQ(covContextp->defaultFilename(), VL_STRINGIFY(TEST_OBJ_DIR) "/coverage4.dat"); covContextp->write(); // Uses defaultFilename() #elif defined(T_COVER_LIB_LEGACY) TEST_CHECK_EQ(VerilatedCov::defaultFilename(), "coverage.dat"); VerilatedCov::write(VL_STRINGIFY(TEST_OBJ_DIR) "/coverage1.dat"); VerilatedCov::clearNonMatch("kept_"); VerilatedCov::write(VL_STRINGIFY(TEST_OBJ_DIR) "/coverage2.dat"); VerilatedCov::zero(); VerilatedCov::write(VL_STRINGIFY(TEST_OBJ_DIR) "/coverage3.dat"); VerilatedCov::clear(); Verilated::defaultContextp()->coverageFilename(VL_STRINGIFY(TEST_OBJ_DIR) "/coverage4.dat"); TEST_CHECK_EQ(VerilatedCov::defaultFilename(), VL_STRINGIFY(TEST_OBJ_DIR) "/coverage4.dat"); VerilatedCov::write(); // Uses defaultFilename() #else #error #endif printf("*-* All Finished *-*\n"); return (errors ? 10 : 0); } verilator-5.042/test_regress/t/t_pp_underline_bad.py0000755000542200017500000000076315101701376023266 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_order_blkloopinit_bad.py0000755000542200017500000000101015101701376024305 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=[], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_var_static.py0000755000542200017500000000104415101701376022124 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['-Wno-IMPLICITSTATIC']) test.execute(all_run_flags=['+plusarg=value']) test.passes() verilator-5.042/test_regress/t/t_order_wireloop.py0000755000542200017500000000156215101701376023025 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(fails=test.vlt_all, verilator_flags2=["-fno-dfg"]) # Used to be %Error: t/t_order_wireloop.v:\d+: Wire inputs its own output, creating circular logic .wire x=x. # However we no longer gate optimize this # Can't use expect_filename here as unstable output test.file_grep( test.compile_log_filename, r"%Warning-UNOPTFLAT: t/t_order_wireloop.v:\d+:\d+: Signal unoptimizable: Circular combinational logic: \'t.foo\'" ) test.passes() verilator-5.042/test_regress/t/t_sys_file_basic_mcd_test2_1.dat0000644000542200017500000000020215101701376025237 0ustar mahmoudyfreeshellScotland is the greatest country. All other countries are inferior. Woe betide those to stand against the mighty Scottish nation. verilator-5.042/test_regress/t/t_implements_not_nested.v0000644000542200017500000000143315101701376024200 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package ipkg; typedef interface class iclass; interface class iclass; pure virtual function void doit(); endclass endpackage package epkg; interface class cclass2 extends ipkg::iclass; pure virtual function void doit2(); endclass class cclass implements cclass2; virtual function void doit(); $display("doit"); endfunction virtual function void doit2(); $display("doit2"); endfunction endclass endpackage module top; import epkg::*; initial begin automatic cclass c = new(); c.doit(); $finish; end endmodule verilator-5.042/test_regress/t/t_sequence_first_match_unsup.py0000755000542200017500000000107715101701376025420 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert --error-limit 1000'], fails=True) test.passes() verilator-5.042/test_regress/t/t_array_rev.py0000755000542200017500000000073415101701376021764 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_enum_overlap_bad.v0000644000542200017500000000053615101701376023106 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; enum { e0, e1, e2, e1b=1 } BAD1; initial begin $stop; end endmodule verilator-5.042/test_regress/t/t_trace_param_fst.py0000755000542200017500000000103215101701376023114 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_trace_param.v" test.compile(v_flags2=["--trace-fst"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_literal_bad.v0000644000542200017500000000040515101701376023067 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 module t ( ); localparam the_localparam = 8'd256; endmodule verilator-5.042/test_regress/t/t_array_in_struct.py0000755000542200017500000000073415101701376023202 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_generic_bad2.v0000644000542200017500000000106015101701376024121 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class inf; int v; endclass module GenericModule (interface a); initial begin #1; if (a.v != 7) $stop; if (b.k != 9) $stop; end endmodule module t; inf inf_inst(); GenericModule genericModule (inf_inst); initial begin inf_inst.v = 7; inf_inst2.k = 9; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_mod_dot.py0000755000542200017500000000140215101701376021410 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') # This doesn't use the general compile rule as we want to make sure we form # prefix properly using post-escaped identifiers test.run(cmd=[ os.environ["VERILATOR_ROOT"] + "/bin/verilator", "--cc", "--Mdir " + test.obj_dir + "/t_mod_dot", "--exe --build --main", 't/t_mod_dot.v', ], verilator_run=True) test.passes() verilator-5.042/test_regress/t/t_randomize_prepost.py0000755000542200017500000000104615101701376023533 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_checker_unsup.py0000755000542200017500000000111015101701376022615 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=['--assert'], expect_filename=test.golden_filename, fails=test.vlt_all) #test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_depth.v0000644000542200017500000000134415101701376022064 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( input clk ); int cyc; wire integer value_at_top = cyc; // Magic name checked in .py file sub1 sub1a (.*); sub1 sub1b (.*); always @(posedge clk) begin cyc <= cyc + 1; if (cyc == 10) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module sub1 ( input int cyc ); sub2 sub2a (.*); sub2 sub2b (.*); sub2 sub2c (.*); endmodule module sub2 ( input int cyc ); wire integer value_in_sub = cyc; // Magic name checked in .py file endmodule verilator-5.042/test_regress/t/t_array_packed_sysfunct.py0000755000542200017500000000073415101701376024355 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_json_only_begin_hier.py0000755000542200017500000000135415101701376024156 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') out_filename = test.obj_dir + "/V" + test.name + ".tree.json" test.compile(verilator_flags2=['--no-std', '--json-only', '--no-json-edit-nums'], verilator_make_gmake=False, make_top_shell=False, make_main=False) test.files_identical(out_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_timing_trace_saif.out0000644000542200017500000001145715101701376023621 0ustar mahmoudyfreeshell// Generated by verilated_saif (SAIFILE (SAIFVERSION "2.0") (DIRECTION "backward") (PROGRAM_NAME "Verilator") (DIVIDER / ) (TIMESCALE 1ps) (DURATION 100) (INSTANCE t (NET (CLK_PERIOD\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[1\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1)) (CLK_PERIOD\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[3\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1)) (CLK_PERIOD\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_PERIOD\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[0\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1)) (CLK_HALF_PERIOD\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[2\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1)) (CLK_HALF_PERIOD\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (CLK_HALF_PERIOD\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (rst (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1)) (clk (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 20)) (a (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 2)) (c (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10)) (d (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ev (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) verilator-5.042/test_regress/t/t_dpi_open_oob_bad_c.cpp0000644000542200017500000001165615101701376023672 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "svdpi.h" #include #include #include // These require the above. Comment prevents clang-format moving them #include "TestCheck.h" //====================================================================== // clang-format off #if defined(VERILATOR) # include "Vt_dpi_open_oob_bad__Dpi.h" #else # error "Unknown simulator for DPI test" #endif // clang-format on //====================================================================== int errors = 0; void dpii_nullptr() { printf("%s:\n", __func__); // These cause fatal errors, so each would need a separate run // svOpenArrayHandle h = nullptr; // svBitVecVal bit_vec_val[2]; // svLogicVecVal logic_vec_val[2]; // svDimensions(h); // svGetArrayPtr(h); // svHigh(h, 0); // svIncrement(h, 0); // svLeft(h, 0); // svLow(h, 0); // svRight(h, 0); // svSize(h, 0); // svSizeOfArray(h); // // svGetArrElemPtr(h, 0); // svGetArrElemPtr1(h, 0); // svGetArrElemPtr2(h, 0, 0); // svGetArrElemPtr3(h, 0, 0, 0); // svGetBitArrElem(h, 0); // svGetBitArrElem1(h, 0); // svGetBitArrElem1VecVal(bit_vec_val, h, 0); // svGetBitArrElem2(h, 0, 0); // svGetBitArrElem2VecVal(bit_vec_val, h, 0, 0); // svGetBitArrElem3(h, 0, 0, 0); // svGetBitArrElem3VecVal(bit_vec_val, h, 0, 0, 0); // svGetBitArrElemVecVal(bit_vec_val, h, 0); // svGetLogicArrElem(h, 0); // svGetLogicArrElem1(h, 0); // svGetLogicArrElem1VecVal(logic_vec_val, h, 0); // svGetLogicArrElem2(h, 0, 0); // svGetLogicArrElem2VecVal(logic_vec_val, h, 0, 0); // svGetLogicArrElem3(h, 0, 0, 0); // svGetLogicArrElem3VecVal(logic_vec_val, h, 0, 0, 0); // svGetLogicArrElemVecVal(logic_vec_val, h, 0); // svPutBitArrElem(h, 0, 0); // svPutBitArrElem1(h, 0, 0); // svPutBitArrElem1VecVal(h, bit_vec_val, 0); // svPutBitArrElem2(h, 0, 0, 0); // svPutBitArrElem2VecVal(h, bit_vec_val, 0, 0); // svPutBitArrElem3(h, 0, 0, 0, 0); // svPutBitArrElem3VecVal(h, bit_vec_val, 0, 0, 0); // svPutBitArrElemVecVal(h, bit_vec_val, 0); // svPutLogicArrElem(h, 0, 0); // svPutLogicArrElem1(h, 0, 0); // svPutLogicArrElem1VecVal(h, logic_vec_val, 0); // svPutLogicArrElem2(h, 0, 0, 0); // svPutLogicArrElem2VecVal(h, logic_vec_val, 0, 0); // svPutLogicArrElem3(h, 0, 0, 0, 0); // svPutLogicArrElem3VecVal(h, logic_vec_val, 0, 0, 0); // svPutLogicArrElemVecVal(h, logic_vec_val, 0); } void dpii_int_u3(const svOpenArrayHandle i) { printf("%s:\n", __func__); // Correct usage intptr_t ip = (intptr_t)svGetArrElemPtr3(i, 1, 2, 3); TEST_CHECK_HEX_NE(ip, 0); // Out of bounds ip = (intptr_t)svGetArrElemPtr3(i, 1, 2, 30); TEST_CHECK_HEX_EQ(ip, 0); ip = (intptr_t)svGetArrElemPtr3(i, 1, 20, 3); TEST_CHECK_HEX_EQ(ip, 0); ip = (intptr_t)svGetArrElemPtr3(i, 10, 2, 3); TEST_CHECK_HEX_EQ(ip, 0); ip = (intptr_t)svGetArrElemPtr1(i, 30); TEST_CHECK_HEX_EQ(ip, 0); } void dpii_real_u1(const svOpenArrayHandle i) { printf("%s:\n", __func__); svBitVecVal bit_vec_val[4]; svLogicVecVal logic_vec_val[4]; svGetBitArrElem(i, 0); svGetBitArrElem1(i, 0); svGetBitArrElem1VecVal(bit_vec_val, i, 0); svGetBitArrElemVecVal(bit_vec_val, i, 0); svGetLogicArrElem(i, 0); svGetLogicArrElem1(i, 0); svGetLogicArrElem1VecVal(logic_vec_val, i, 0); svGetLogicArrElemVecVal(logic_vec_val, i, 0); svPutBitArrElem(i, 0, 0); svPutBitArrElem1(i, 0, 0); svPutBitArrElem1VecVal(i, bit_vec_val, 0); svPutBitArrElemVecVal(i, bit_vec_val, 0); svPutLogicArrElem(i, 0, 0); svPutLogicArrElem1(i, 0, 0); svPutLogicArrElem1VecVal(i, logic_vec_val, 0); svPutLogicArrElemVecVal(i, logic_vec_val, 0); } void dpii_bit_u6(const svOpenArrayHandle i) { printf("%s:\n", __func__); svBitVecVal bit_vec_val[4]; svLogicVecVal logic_vec_val[4]; svGetBitArrElem(i, 0, 0, 0, 0, 0, 0); svGetBitArrElemVecVal(bit_vec_val, i, 0, 0, 0, 0, 0, 0); svGetLogicArrElem(i, 0, 0, 0, 0, 0, 0); svGetLogicArrElemVecVal(logic_vec_val, i, 0, 0, 0, 0, 0, 0); svPutBitArrElem(i, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); svPutBitArrElemVecVal(i, bit_vec_val, 0, 0, 0, 0, 0, 0); svPutLogicArrElem(i, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); svPutLogicArrElemVecVal(i, logic_vec_val, 0, 0, 0, 0, 0, 0); } void dpii_real_u6(const svOpenArrayHandle i) { printf("%s:\n", __func__); svGetArrElemPtr(i, 0, 0, 0, 0, 0, 0); } verilator-5.042/test_regress/t/t_c_width_bad.py0000755000542200017500000000076615101701376022226 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_var_pins_sc_uint_bool_nomain.py0000755000542200017500000000107415101701376025711 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_a1_first_cc.v" test.compile(verilator_flags2=["-sc --trace-vcd --pins-sc-uint-bool"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_order_dpi_export_8.cpp0000644000542200017500000000112315101701376023711 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2022 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include #include void call_set_x(svBit val) { set_x(val); } verilator-5.042/test_regress/t/t_opt_table_string.py0000755000542200017500000000130215101701376023321 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--stats"]) if test.vlt_all: test.file_grep(test.stats, r'Optimizations, Tables created\s+(\d+)', 1) test.file_grep(test.stats, r'ConstPool, Tables emitted\s+(\d+)', 1) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_multitop_sig.cpp0000644000542200017500000000232215101701376022633 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include VM_PREFIX_INCLUDE #include // These require the above. Comment prevents clang-format moving them #include "TestCheck.h" double sc_time_stamp() { return 0; } int errors = 0; int main(int argc, char* argv[]) { Verilated::debug(0); Verilated::commandArgs(argc, argv); VM_PREFIX* topp = new VM_PREFIX{""}; { topp->a__02Ein = 0; topp->b__02Ein = 0; topp->uniq_in = 0; topp->eval(); TEST_CHECK_EQ(topp->a__02Eout, 1); TEST_CHECK_EQ(topp->b__02Eout, 0); TEST_CHECK_EQ(topp->uniq_out, 1); topp->a__02Ein = 1; topp->b__02Ein = 1; topp->uniq_in = 1; topp->eval(); TEST_CHECK_EQ(topp->a__02Eout, 0); TEST_CHECK_EQ(topp->b__02Eout, 1); TEST_CHECK_EQ(topp->uniq_out, 0); } topp->final(); VL_DO_DANGLING(delete topp, topp); printf("*-* All Finished *-*\n"); return errors ? 10 : 0; } verilator-5.042/test_regress/t/t_timing_strobe.py0000755000542200017500000000103515101701376022632 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_method.v0000644000542200017500000000163215101701376022247 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef class Cls; class Cls; int imembera; function int get_methoda; return imembera; endfunction task set_methoda(input int val); imembera = val; endtask function void setv_methoda(input int val); imembera = val; endfunction endclass : Cls module t; initial begin int tmp_i; Cls c; if (c != null) $stop; c = new; c.imembera = 10; if (c.get_methoda() != 10) $stop; c.set_methoda(20); if (c.get_methoda() != 20) $stop; c.setv_methoda(30); if (c.get_methoda() != 30) $stop; c.setv_methoda(300); tmp_i = c.get_methoda; if (tmp_i != 300) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_time_print.py0000755000542200017500000000100015101701376022127 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dpi_display_c.cpp0000644000542200017500000000225215101701376022721 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "svdpi.h" #include //====================================================================== // clang-format off #if defined(VERILATOR) # include "Vt_dpi_display__Dpi.h" #elif defined(VCS) # include "../vc_hdrs.h" #elif defined(CADENCE) # define NEED_EXTERNS #else # error "Unknown simulator for DPI test" #endif // clang-format on #ifdef NEED_EXTERNS extern "C" { extern void dpii_display_call(const char* c); } #endif // clang-format off #ifndef VL_PRINTF # define VL_PRINTF printf #endif // clang-format on //====================================================================== void dpii_display_call(const char* c) { VL_PRINTF("dpii_display_call: '%s'\n", c); } verilator-5.042/test_regress/t/t_dfg_regularize_clk.py0000755000542200017500000000100415101701376023603 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["--hierarchical", "--trace"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_select_bad_range6.py0000755000542200017500000000077615101701376023327 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_select_width.py0000755000542200017500000000070615101701376022447 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.042/test_regress/t/t_convert2string.py0000755000542200017500000000073415101701376022763 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_constraint_inheritance_with.v0000644000542200017500000000307215101701376025372 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 `define check_rand(cl, field, constr, cond) \ begin \ longint prev_result; \ int ok = 0; \ if (!bit'(cl.randomize() with { constr; })) $stop; \ prev_result = longint'(field); \ if (!(cond)) $stop; \ repeat(9) begin \ longint result; \ if (!bit'(cl.randomize() with { constr; })) $stop; \ result = longint'(field); \ if (!(cond)) $stop; \ if (result != prev_result) ok = 1; \ prev_result = result; \ end \ if (ok != 1) $stop; \ end typedef class C; class D extends C; rand int z; constraint x_lt_y { x < y; } endclass class A; rand int x; endclass class B extends A; constraint x_gt_0 { x > 0; } endclass class C extends B; rand int y; endclass class E extends C; constraint x_gt_y { x > y; } endclass module t; initial begin B b = new; C c = new; D d = new; E e = new; A a = b; `check_rand(a, a.x, x < 10, a.x > 0 && a.x < 10); `check_rand(c, c.x, x < 100, c.x > 0 && c.x < 100); `check_rand(c, c.y, x == 5, c.x == 5); `check_rand(d, d.x, z > x && z < y, d.x > 0 && d.x < d.y); `check_rand(d, d.y, z > x && z < y, d.x > 0 && d.x < d.y); `check_rand(e, e.x, x inside {[10:20]}, e.x inside {[10:20]} && e.x > e.y); `check_rand(e, e.y, x inside {[10:20]}, e.x inside {[10:20]} && e.x > e.y); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_inst_recurse2_bad.v0000644000542200017500000000046015101701376023175 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; looped looped (); endmodule module looped; looped looped (); endmodule verilator-5.042/test_regress/t/t_class_param_circ_bad.py0000755000542200017500000000076615101701376024072 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_mailbox_notiming.v0000644000542200017500000000154215101701376023141 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Methods defined by IEEE: // class mailbox #(type T = dynamic_singular_type) ; // function new(int bound = 0); // function int num(); // task put( T message); // function int try_put( T message); // task get( ref T message ); // function int try_get( ref T message ); // task peek( ref T message ); // function int try_peek( ref T message ); // endclass `ifndef MAILBOX_T `define MAILBOX_T mailbox `endif // verilator lint_off DECLFILENAME module t; `MAILBOX_T #(int) m; initial begin m = new(4); if (m.num() != 0) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_param_array4.v0000644000542200017500000000236015101701376022163 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; parameter int SIZES [3:1] = '{10,20,30}; parameter int SUMS3 = SIZES[3]; parameter int SUMS2 = SIZES[2]; parameter int SUMS1 = SIZES[1]; parameter int LE_SIZES [1:3] = '{10,20,30}; parameter int LE_SUMS3 = LE_SIZES[3]; parameter int LE_SUMS2 = LE_SIZES[2]; parameter int LE_SUMS1 = LE_SIZES[1]; function int from_array(int index); if (index != 0); return SIZES[index]; endfunction function int from_array_le(int index); if (index != 0); return LE_SIZES[index]; endfunction initial begin if (SUMS1 != 30) $stop; if (SUMS2 != 20) $stop; if (SUMS3 != 10) $stop; if (LE_SUMS1 != 10) $stop; if (LE_SUMS2 != 20) $stop; if (LE_SUMS3 != 30) $stop; if (from_array(1) != 30) $stop; if (from_array(2) != 20) $stop; if (from_array(3) != 10) $stop; if (from_array_le(1) != 10) $stop; if (from_array_le(2) != 20) $stop; if (from_array_le(3) != 30) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_std_identifier.v0000644000542200017500000000056215101701376022577 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 package foo; `ifdef TEST_DECLARE_STD class std; static int bar; endclass `endif endpackage module t; int baz = foo::std::bar; endmodule verilator-5.042/test_regress/t/t_assert_disable_bad.out0000644000542200017500000000064015101701376023734 0ustar mahmoudyfreeshell%Error: t/t_assert_disable_bad.v:27:38: disable iff expression before property call and in its body is not legal : ... note: In instance 't' 27 | assert property (disable iff (val == 0) check(1, 1)); | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_generate_fatal_bad.out0000644000542200017500000000171315101701376023713 0ustar mahmoudyfreeshell%Warning-USERFATAL: "boom" ... For warning description see https://verilator.org/warn/USERFATAL?v=latest ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. %Error: t/t_generate_fatal_bad.v:13:29: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz' : ... note: In instance 't.nested_loop[10].foo2_inst.foo2_loop[1].foo_in_foo2_inst' t/t_generate_fatal_bad.v:9:4: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing t/t_generate_fatal_bad.v:13:29: ... Called from 'get_baz()' with parameters: bar = ?32?h0 13 | localparam integer BAZ = get_baz(BAR); | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_class_param_bad1.py0000755000542200017500000000076615101701376023153 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dynarray_method.py0000755000542200017500000000073415101701376023163 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_const_number_bad.v0000644000542200017500000000115615101701376023107 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Test of select from constant // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; parameter integer FOO2 = 32'd-6; // Minus doesn't go here parameter integer FOO3 = 32'd; parameter integer FOO4 = 32'h; parameter integer FOO5 = 32'b2; parameter integer FOO6 = 32'o8; // See bug2432, this is questionable, some simulators take this, others do not parameter logic [3:0] FOO7 = 1'b1?4'hF:4'h1; // bug2432 - intentionally no spaces near ? endmodule verilator-5.042/test_regress/t/t_lint_syncasyncnet_bad.v0000644000542200017500000000255315101701376024162 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk, rst_both_l, rst_sync_l, rst_async_l, d ); /*AUTOINPUT*/ input clk; input rst_both_l; input rst_sync_l; input rst_async_l; input d; reg q1; reg q2; always @(posedge clk) begin if (~rst_sync_l) begin /*AUTORESET*/ // Beginning of autoreset for uninitialized flops q1 <= 1'h0; // End of automatics end else begin q1 <= d; end end always @(posedge clk) begin q2 <= (rst_both_l) ? d : 1'b0; if (0 && q1 && q2) ; end reg q3; always @(posedge clk or negedge rst_async_l) begin if (~rst_async_l) begin /*AUTORESET*/ // Beginning of autoreset for uninitialized flops q3 <= 1'h0; // End of automatics end else begin q3 <= d; end end reg q4; always @(posedge clk or negedge rst_both_l) begin q4 <= (~rst_both_l) ? 1'b0 : d; end // Make there be more async uses than sync uses reg q5; always @(posedge clk or negedge rst_both_l) begin q5 <= (~rst_both_l) ? 1'b0 : d; if (0 && q3 && q4 && q5) ; end endmodule verilator-5.042/test_regress/t/t_math_pow6.py0000755000542200017500000000073415101701376021676 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_package.py0000755000542200017500000000073415101701376022552 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_open_wrong_order_bad.v0000644000542200017500000000037215101701376025136 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog dummy test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Yu-Sheng Lin. // SPDX-License-Identifier: CC0-1.0 module t(input clk); endmodule verilator-5.042/test_regress/t/t_flag_parameter.v0000644000542200017500000000777315101701376022567 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2016 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // // Special cases of "string parameters" : // This table compares obtain results from big-3 simulators to Verilator // expected behavior. Base specified integer literals are also included as // string detection may impact results for such cases. // // | Option/Param file | simulator 1 | simulator 2 | simulator 3 | verilator | // |---------------------|-------------|-------------|-------------|-------------| // | -gC0='"AB CD"' | AB CD | UNSUPPORTED | AB CD | AB CD | // | -gC1=\"AB\ CD\" | AB CD | UNSUPPORTED | UNSUPPORTED | AB CD | // | -gC2="\"AB CD\"" | AB CD | AB CD | AB CD | AB CD | // | -gC3="\"AB\ CD\"" | AB CD | AB\\ CD | AB CD | AB CD | // | -gC4=32'h600D600D | UNSUPPORTED | 32'h600D600D| 32'h600D600D| 32'h600D600D| // | -gC5=32\'h600D600D | 32'h600D600D| UNSUPPORTED | UNSUPPORTED | 32'h600D600D| // | -gC6="32'h600D600D" | 32'h600D600D| 32'h600D600D| UNSUPPORTED | 32'h600D600D| // | -gC7='AB CD' | AB CD | UNSUPPORTED | UNSUPPORTED | UNSUPPORTED | `define stop $stop `define check(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: Wrong parameter value", `__FILE__,`__LINE__); `stop; end while(0); typedef enum logic [1:0] { enum_val_0 = 2'd0, enum_val_1 = 2'd1, enum_val_2 = 2'd2, enum_val_3 = 2'd3 } enum_t; module t; parameter string1 = "Original String"; parameter string2 = "Original String"; parameter string11 = "Original String"; parameter string12 = "Original String"; parameter string21 = "Original String"; parameter string22 = "Original String"; parameter real11 = 0.1; parameter real12 = 0.1; parameter real21 = 0.1; parameter real22 = 0.1; parameter real31 = 0.1; parameter real32 = 0.1; parameter real41 = 0.1; parameter real42 = 0.1; parameter real51 = 0.1; parameter real52 = 0.1; parameter int11 = 1; parameter int12 = 1; parameter int21 = 1; parameter int22 = 1; parameter int31 = 1; parameter int32 = 1; parameter int41 = 1; parameter int42 = 1; parameter int51 = 1; parameter int52 = 1; parameter int61 = 1; parameter int62 = 1; parameter int71 = 1; parameter int72 = 1; parameter bit bit0to0 = 0; parameter bit bit1to1 = 1; parameter bit bit0to1 = 0; parameter bit bit1to0 = 1; parameter enum_t enum11 = enum_val_1; parameter enum_t enum12 = enum_val_1; parameter enum_t enum21 = enum_val_1; parameter enum_t enum22 = enum_val_1; initial begin `check(string1,"New String"); `check(string2,"New String"); `check(string11,"New String"); `check(string12,"New String"); `check(string21,"New String"); `check(string22,"New String"); `check(real11,0.2); `check(real12,0.2); `check(real21,400); `check(real22,400); `check(real31,20); `check(real32,20); `check(real41,582.5); `check(real42,582.5); `check(real51,145.5); `check(real52,145.5); `check(int11,16); `check(int12,16); `check(int21,16); `check(int22,16); `check(int31,123); `check(int32,123); `check(int41,32'hdeadbeef); `check(int42,32'hdeadbeef); `check(int51,32'hdeadbeef); `check(int52,32'hdeadbeef); `check(int61,32'hdeadbeef); `check(int62,32'hdeadbeef); `check(int71,-1000); `check(int72,-1000); `check(bit0to0, 1'b0); `check(bit1to1, 1'b1); `check(bit0to1, 1'b1); `check(bit1to0, 1'b0); `check(enum11, enum_val_2); `check(enum12, enum_val_2); `check(enum21, enum_val_3); `check(enum22, enum_val_3); // Check parameter assigned simple integer literal is signed if ((int11 << 27) >>> 31 != -1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_config_include_bad.v0000644000542200017500000000041515101701376023356 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 include "meant_to_tick_include.v" module t; endmodule verilator-5.042/test_regress/t/t_preproc_strify_join.py0000755000542200017500000000137515101701376024065 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') stdout_filename = os.path.join(test.obj_dir, test.name + "__test.vpp") test.compile(verilator_flags2=['-E -P'], verilator_make_gmake=False, make_top_shell=False, make_main=False, stdout_filename=stdout_filename) test.files_identical(stdout_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_display_type_bad.v0000644000542200017500000000057615101701376023124 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; string s = "a string"; initial begin $display("%d %x %f %t", s, s, s, s); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_time_sc_bad.py0000755000542200017500000000130515101701376022216 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_time_sc.v" test.sc_time_resolution = 'SC_NS' test.compile(verilator_flags2=[ '-sc', '-timescale 1ps/1ps', # Mismatch w/sc_time_resolution '+define+TEST_EXPECT=2us' ]) test.execute(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_extends_default.py0000755000542200017500000000077615101701376024343 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_enum_type_nomethod_bad.v0000644000542200017500000000062115101701376024307 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; typedef enum [3:0] { E01 = 1 } my_t; my_t e; initial begin e.bad_no_such_method(); $stop; end endmodule verilator-5.042/test_regress/t/t_bitsel_struct.py0000755000542200017500000000073415101701376022660 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_assoc.py0000755000542200017500000000073415101701376021102 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_dpi_name_bad.py0000755000542200017500000000077615101701376022362 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_enum_base.v0000644000542200017500000000060715101701376021541 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; typedef int int_t; typedef enum int_t {INTT_VAL = 1} intt_e; intt_e intte; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_array_backw_index_bad.v0000644000542200017500000000164615101701376024071 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; logic [31:0] array_assign [3:0]; logic [31:0] larray_assign [0:3]; logic [31:0] array_assign2 [6:3]; logic [31:0] larray_assign2 [3:6]; initial begin array_assign[1:3] = '{32'd4, 32'd3, 32'd2}; larray_assign[3:1] = '{32'd4, 32'd3, 32'd2}; array_assign2[4:6] = '{32'd4, 32'd3, 32'd2}; larray_assign2[6:4] = '{32'd4, 32'd3, 32'd2}; array_assign[4:3] = '{32'd4, 32'd3}; array_assign[1:-1] = '{32'd4, 32'd3}; array_assign[1:1] = '{32'd4}; // Ok larray_assign[1:1] = '{32'd4}; // Ok array_assign2[4:4] = '{32'd4}; // Ok larray_assign2[4:4] = '{32'd4}; // Ok $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_sys_delta_monitor.v0000644000542200017500000000115515101701376023340 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; logic [31:0] tmp; logic [31:0] tmp2; logic [31:0] tmp3; initial begin tmp = 0; $monitor("[%0t] monitor0 %h", $time, tmp); while (tmp < 32) begin tmp = tmp + 1; if ((tmp % 5) == 1) begin tmp = tmp + 2; tmp = tmp + 1; end #1; end $write("*-* All Finished *-*\n"); $finish(); end endmodule verilator-5.042/test_regress/t/t_alw_split.v0000644000542200017500000000513415101701376021601 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg [15:0] m_din; // We expect all these blocks should split; // blocks that don't split should go in t_alw_nosplit.v reg [15:0] a_split_1, a_split_2; always @ (/*AS*/m_din) begin a_split_1 = m_din; a_split_2 = m_din; end reg [15:0] d_split_1, d_split_2; always @ (posedge clk) begin d_split_1 <= m_din; d_split_2 <= d_split_1; d_split_1 <= ~m_din; end reg [15:0] h_split_1; reg [15:0] h_split_2; always @ (posedge clk) begin // $write(" cyc = %x m_din = %x\n", cyc, m_din); if (cyc > 2) begin if (m_din == 16'h0) begin h_split_1 <= 16'h0; h_split_2 <= 16'h0; end else begin h_split_1 <= m_din; h_split_2 <= ~m_din; end end else begin h_split_1 <= 16'h0; h_split_2 <= 16'h0; end end reg [15:0] l_split_1, l_split_2; always @ (posedge clk) begin l_split_2 <= l_split_1; l_split_1 <= l_split_2 | m_din; end // (The checker block is an exception, it won't split.) always @ (posedge clk) begin if (cyc!=0) begin cyc<=cyc+1; if (cyc==1) begin m_din <= 16'hfeed; end if (cyc==3) begin end if (cyc==4) begin m_din <= 16'he11e; //$write(" A %x %x\n", a_split_1, a_split_2); if (!(a_split_1==16'hfeed && a_split_2==16'hfeed)) $stop; if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop; if (!(h_split_1==16'hfeed && h_split_2==16'h0112)) $stop; end if (cyc==5) begin m_din <= 16'he22e; if (!(a_split_1==16'he11e && a_split_2==16'he11e)) $stop; if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop; if (!(h_split_1==16'hfeed && h_split_2==16'h0112)) $stop; end if (cyc==6) begin m_din <= 16'he33e; if (!(a_split_1==16'he22e && a_split_2==16'he22e)) $stop; if (!(d_split_1==16'h1ee1 && d_split_2==16'h0112)) $stop; if (!(h_split_1==16'he11e && h_split_2==16'h1ee1)) $stop; end if (cyc==7) begin $write("*-* All Finished *-*\n"); $finish; end end end // always @ (posedge clk) endmodule verilator-5.042/test_regress/t/t_param_named_2.py0000755000542200017500000000073415101701376022457 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_process_redecl.v0000644000542200017500000000067615101701376022605 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( ); // Overrides standard class class process; endclass class mailbox; endclass class semaphore; endclass initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_udp_param_bad.out0000644000542200017500000000054615101701376022725 0ustar mahmoudyfreeshell%Error: t/t_udp_param_bad.v:12:15: syntax error, unexpected '#', expecting ';' 12 | primitive udp #( | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_udp_param_bad.v:14:1: syntax error, unexpected ')', expecting ';' 14 | ) (o, a); | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_x_rand_stability_trace.out0000644000542200017500000000105615101701376024661 0ustar mahmoudyfreeshelluninitialized = 0xf5bbcbc0 x_assigned (initial) = 0x00000000 uninitialized2 = 0xa979eb54 big = 0xa20c93ac50d8c57d4c80949aa68e82775da6af98ce08f75dc6ccfad97b059a33 random_init = 0x952aaa76 top.t.the_sub_yes_inline_1 no_init 0x4a544f7798b83fc8 top.t.the_sub_yes_inline_2 no_init 0x19b7000ee0472c9 top.t.the_sub_no_inline_1 no_init 0x38121a34978975dd top.t.the_sub_no_inline_2 no_init 0x9022c84ae0fa3cf6 rand = 0xe3e54aaa rand = 0xe85acf2d rand = 0x15e12c6a rand = 0x0f7f28c0 rand = 0xe189c52a x_assigned = 0x486aeb2d Last rand = 0xf0700dbf *-* All Finished *-* verilator-5.042/test_regress/t/t_unpacked_slice.py0000755000542200017500000000073415101701376022743 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_var_tieout.py0000755000542200017500000000073415101701376022153 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_udp_bad_comb_trigger.out0000644000542200017500000000054415101701376024266 0ustar mahmoudyfreeshell%Error: t/t_udp_bad_comb_trigger.v:14:10: There should not be a edge trigger for combinational UDP table line : ... note: In instance 'top' 14 | (01) 1 0 : 0; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_tri_gate_pmos_pins_inout.py0000755000542200017500000000140615101701376025072 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_tri_gate.cpp" test.top_filename = "t/t_tri_gate.v" test.compile(make_top_shell=False, make_main=False, v_flags2=['+define+T_PMOS'], make_flags=['CPPFLAGS_ADD=-DT_PMOS'], verilator_flags2=["--exe --pins-inout-enables", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_var_outoforder.py0000755000542200017500000000073415101701376023032 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_lib_prot_exe_bad.out0000644000542200017500000000031015101701376023415 0ustar mahmoudyfreeshell%Error: --exe cannot be used together with --lib-create. Suggest see manual ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_initial_assign_sformatf_debug.py0000755000542200017500000000105415101701376026032 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_initial_assign_sformatf.v" test.compile(verilator_flags2=['--debug']) test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_gen12_noinl.py0000755000542200017500000000104015101701376024114 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_gen12.v" test.compile(v_flags2=["-fno-inline"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_width_genfor_bad.py0000755000542200017500000000076615101701376024312 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_var_dotted1_inl2.py0000755000542200017500000000104715101701376023130 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_var_dotted1.v" test.compile(v_flags2=['+define+USE_INLINE_MID']) test.execute() test.passes() verilator-5.042/test_regress/t/t_class_extends1.py0000755000542200017500000000073415101701376022712 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_randomize_inline_var_ctl_unsup_1.v0000644000542200017500000000103115101701376026305 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Foo; int x; static function Foo get; Foo foo = new; return foo; endfunction endclass module t; initial begin Foo foo = Foo::get(); Foo foos[] = new[1]; void'(foo.randomize(Foo::get().x)); void'(foo.randomize(foos[0].x)); void'(foo.randomize(null)); end endmodule verilator-5.042/test_regress/t/t_gate_inline_wide_noexclude_small_wide.v0000644000542200017500000000106615101701376027337 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 localparam N = 65; // Wide but narrower than expand limit module t( input wire [N-1:0] i, output wire [N-1:0] o ); // Do not exclude from inlining wides small enough to be handled by // V3Expand. wire [65:0] wide_small = N << i * i / N; for (genvar n = 0; n < N; ++n) begin assign o[n] = i[n] ^ wide_small[n]; end endmodule verilator-5.042/test_regress/t/t_var_overwidth_bad.out0000644000542200017500000000016315101701376023633 0ustar mahmoudyfreeshell%Error: unknown:0: Testbench C set input 'clk' to value that overflows what the signal's width can fit Aborting... verilator-5.042/test_regress/t/t_hier_block_import_cmake.py0000755000542200017500000000231715101701376024624 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') # CMake build executes from a different directory than the Make one. test.top_filename = os.path.abspath("t/t_hier_block_import.v") # stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. test.clean_objs() test.setenv('TEST_ROOT', test.t_dir + "/t_hier_block_import") test.compile(verilator_make_cmake=True, verilator_make_gmake=False, verilator_flags2=[ '$TEST_ROOT/t_hier_block_import_def.vh', '-f $TEST_ROOT/t_hier_block_import_args.f', '-I$TEST_ROOT' ], threads=(6 if test.vltmt else 1)) test.execute() test.file_grep(test.obj_dir + "/VsubA/subA.sv", r'^module\s+(\S+)\s+', "subA") test.file_grep(test.stats, r'HierBlock,\s+Hierarchical blocks\s+(\d+)', 2) test.passes() verilator-5.042/test_regress/t/t_lint_latch_1.v0000644000542200017500000000057515101701376022150 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module for issue #1609 // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by Julien Margetts. // SPDX-License-Identifier: Unlicense module t (/*AUTOARG*/ a, b, o); input a; input b; output reg o; // verilator lint_off LATCH always @(a or b) if (a) o <= b; endmodule verilator-5.042/test_regress/t/t_var_bad_hide2.py0000755000542200017500000000110515101701376022434 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["--lint-only -Wwarn-VARHIDDEN"], fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_debug_fatalsrc_bt_bad.py0000755000542200017500000000160215101701376024225 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') if 'VERILATOR_TEST_NO_GDB' in os.environ: test.skip("Skipping due to VERILATOR_TEST_NO_GDB") if not test.have_gdb: test.skip("No gdb installed") test.lint(verilator_flags2=["--lint-only --debug --gdbbt --debug-fatalsrc"], fails='any') test.file_grep(test.compile_log_filename, r'%Error: Internal Error: .*: --debug-fatal-src') test.file_grep(test.compile_log_filename, r'See the manual') test.file_grep(test.compile_log_filename, r'in V3Options::') test.passes() verilator-5.042/test_regress/t/t_clocking_bad1.v0000644000542200017500000000060415101701376022260 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; default clocking @(posedge clk); endclocking default clocking @(posedge clk); endclocking endmodule verilator-5.042/test_regress/t/t_sys_readmem_h.mem0000644000542200017500000000104715101701376022732 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test data file // // Copyright 2006 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 @4 4004_37654321_27654321_17654321_07654321_abcdef10 @a 400a_37654321_27654321_17654321_07654321_abcdef11 400b_37654321_27654321_17654321_07654321_abcdef12 400c_37654321_27654321_17654321_07654321_abcdef13 verilator-5.042/test_regress/t/t_package_using_dollar_unit.py0000755000542200017500000000073415101701376025166 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_constraint_struct.py0000755000542200017500000000104615101701376023557 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_extend_c_class_c.h0000644000542200017500000000103315101701376023037 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006-2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class t_extend_c_class_c { public: // CONSTRUCTORS t_extend_c_class_c() = default; ~t_extend_c_class_c() = default; // METHODS // This function will be called from an instance created in Verilog uint32_t my_math(uint32_t in) { return in + 1; } }; verilator-5.042/test_regress/t/t_trace_no_top_name2.cpp0000644000542200017500000000272615101701376023662 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #if VM_TRACE_FST #include #define TRACE_FILE_NAME "simx.fst" #define TRACE_CLASS VerilatedFstC #elif VM_TRACE_VCD #include #define TRACE_FILE_NAME "simx.vcd" #define TRACE_CLASS VerilatedVcdC #elif VM_TRACE_SAIF #include #define TRACE_FILE_NAME "simx.saif" #define TRACE_CLASS VerilatedSaifC #endif #include #include VM_PREFIX_INCLUDE unsigned long long main_time = 0; double sc_time_stamp() { return (double)main_time; } int main(int argc, char** argv) { Verilated::debug(0); Verilated::traceEverOn(true); Verilated::commandArgs(argc, argv); // This test is to specifically check "" as the below upper model name std::unique_ptr top{new VM_PREFIX{""}}; std::unique_ptr tfp{new TRACE_CLASS}; top->trace(tfp.get(), 99); tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/" TRACE_FILE_NAME); top->clk = 0; while (main_time <= 20) { top->eval(); tfp->dump((unsigned int)(main_time)); ++main_time; top->clk = !top->clk; } tfp->close(); top->final(); tfp.reset(); top.reset(); printf("*-* All Finished *-*\n"); return 0; } verilator-5.042/test_regress/t/t_mod_dup_bad_lib.py0000755000542200017500000000102415101701376023046 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flag2=["--work liba"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_udp_bad_multi_output.out0000644000542200017500000000053715101701376024377 0ustar mahmoudyfreeshell%Error: t/t_udp_bad_multi_output.v:8:15: 2 output ports for UDP table, there must be one output port : ... note: In instance 'top' 8 | output dout1, dout2; | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_disable_fork2.py0000755000542200017500000000077115101701376022501 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_vlcov_debugi.py0000755000542200017500000000137115101701376022440 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') for basename in [ "t_vlcov_data_a.dat", "t_vlcov_data_b.dat", "t_vlcov_data_c.dat", "t_vlcov_data_d.dat" ]: test.run(cmd=[ os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "t/" + basename, "--debug", "--debugi 9" ], tee=test.verbose, verilator_run=True) test.passes() verilator-5.042/test_regress/t/t_nba_commit_queue_suspenable.v0000644000542200017500000000337415101701376025344 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Test of select from constant // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module t; reg clk = 0; always #50 clk = ~clk; initial begin #1000; $write("*-* All Finished *-*\n"); $finish; end int cyc = 0; always @(posedge clk) cyc <= cyc + 1; localparam SIZE = 65536; // Case 1: Array NBA inside suspendable int array1 [SIZE]; always @ (posedge clk) begin #1; for (int i=0; i 1) begin for (int i=0; i // Avoid C++11 in this file as not all simulators allow it //====================================================================== class TestVpiHandle { /// For testing, etc, wrap vpiHandle in an auto-releasing class vpiHandle m_handle; // No = as no C++11 bool m_freeit; // No = as no C++11 public: TestVpiHandle() : m_handle(NULL) // Need (), not C++11 , m_freeit(true) {} // Need (), not C++11 TestVpiHandle(vpiHandle h) : m_handle(h) // Need (), not C++11 , m_freeit(true) {} // Need (), not C++11 ~TestVpiHandle() { release(); } operator vpiHandle() const { return m_handle; } TestVpiHandle& operator=(vpiHandle h) { release(); m_handle = h; m_freeit = true; return *this; } void release() { if (m_handle && m_freeit) { // Below not VL_DO_DANGLING so is portable #ifdef IVERILOG vpi_free_object(m_handle); #else vpi_release_handle(m_handle); #endif m_handle = NULL; } } // Freed by another action e.g. vpi_scan; so empty and don't free again void freed() { m_handle = NULL; m_freeit = false; } }; //====================================================================== // VerilatedVpiError Methods const char* strFromVpiVal(PLI_INT32 vpiVal) { // clang-format off static const char* const names[] = { "*undefined*", "vpiBinStrVal", "vpiOctStrVal", "vpiDecStrVal", "vpiHexStrVal", "vpiScalarVal", "vpiIntVal", "vpiRealVal", "vpiStringVal", "vpiVectorVal", "vpiStrengthVal", "vpiTimeVal", "vpiObjTypeVal", "vpiSuppressVal", "vpiShortIntVal", "vpiLongIntVal", "vpiShortRealVal", "vpiRawTwoStateVal", "vpiRawFourStateVal", }; // clang-format on if ((vpiVal < 0)) return names[0]; return names[(vpiVal <= vpiRawFourStateVal) ? vpiVal : 0]; } const char* strFromVpiObjType(PLI_INT32 vpiVal) { // clang-format off static const char* const names[] = { "*undefined*", "vpiAlways", "vpiAssignStmt", "vpiAssignment", "vpiBegin", "vpiCase", "vpiCaseItem", "vpiConstant", "vpiContAssign", "vpiDeassign", "vpiDefParam", "vpiDelayControl", "vpiDisable", "vpiEventControl", "vpiEventStmt", "vpiFor", "vpiForce", "vpiForever", "vpiFork", "vpiFuncCall", "vpiFunction", "vpiGate", "vpiIf", "vpiIfElse", "vpiInitial", "vpiIntegerVar", "vpiInterModPath", "vpiIterator", "vpiIODecl", "vpiMemory", "vpiMemoryWord", "vpiModPath", "vpiModule", "vpiNamedBegin", "vpiNamedEvent", "vpiNamedFork", "vpiNet", "vpiNetBit", "vpiNullStmt", "vpiOperation", "vpiParamAssign", "vpiParameter", "vpiPartSelect", "vpiPathTerm", "vpiPort", "vpiPortBit", "vpiPrimTerm", "vpiRealVar", "vpiReg", "vpiRegBit", "vpiRelease", "vpiRepeat", "vpiRepeatControl", "vpiSchedEvent", "vpiSpecParam", "vpiSwitch", "vpiSysFuncCall", "vpiSysTaskCall", "vpiTableEntry", "vpiTask", "vpiTaskCall", "vpiTchk", "vpiTchkTerm", "vpiTimeVar", "vpiTimeQueue", "vpiUdp", "vpiUdpDefn", "vpiUserSystf", "vpiVarSelect", "vpiWait", "vpiWhile", "vpiCondition", "vpiDelay", "vpiElseStmt", "vpiForIncStmt", "vpiForInitStmt", "vpiHighConn", "vpiLhs", "vpiIndex", "vpiLeftRange", "vpiLowConn", "vpiParent", "vpiRhs", "vpiRightRange", "vpiScope", "vpiSysTfCall", "vpiTchkDataTerm", "vpiTchkNotifier", "vpiTchkRefTerm", "vpiArgument", "vpiBit", "vpiDriver", "vpiInternalScope", "vpiLoad", "vpiModDataPathIn", "vpiModPathIn", "vpiModPathOut", "vpiOperand", "vpiPortInst", "vpiProcess", "vpiVariables", "vpiUse", "vpiExpr", "vpiPrimitive", "vpiStmt", "vpiAttribute", "vpiBitSelect", "vpiCallback", "vpiDelayTerm", "vpiDelayDevice", "vpiFrame", "vpiGateArray", "vpiModuleArray", "vpiPrimitiveArray", "vpiNetArray", "vpiRange", "vpiRegArray", "vpiSwitchArray", "vpiUdpArray", "vpiActiveTimeFormat", "vpiInTerm", "vpiInstanceArray", "vpiLocalDriver", "vpiLocalLoad", "vpiOutTerm", "vpiPorts", "vpiSimNet", "vpiTaskFunc", "vpiContAssignBit", "vpiNamedEventArray", "vpiIndexedPartSelect", "vpiBaseExpr", "vpiWidthExpr", "vpiGenScopeArray", "vpiGenScope", "vpiGenVar", "vpiAutomatics" }; static const char* const sv_names1[] = { "vpiPackage", "vpiInterface", "vpiProgram", "vpiInterfaceArray", "vpiProgramArray", "vpiTypespec", "vpiModport", "vpiInterfaceTfDecl", "vpiRefObj", "vpiTypeParameter", "vpiLongIntVar", "vpiShortIntVar", "vpiIntVar", "vpiShortRealVar", "vpiByteVar", "vpiClassVar", "vpiStringVar", "vpiEnumVar", "vpiStructVar", "vpiUnionVar", "vpiBitVar", "vpiClassObj", "vpiChandleVar", "vpiPackedArrayVar", "*undefined*", // 624 is not defined for object types "vpiLongIntTypespec", "vpiShortRealTypespec", "vpiByteTypespec", "vpiShortIntTypespec", "vpiIntTypespec", "vpiClassTypespec", "vpiStringTypespec", "vpiChandleTypespec", "vpiEnumTypespec", "vpiEnumConst", "vpiIntegerTypespec", "vpiTimeTypespec", "vpiRealTypespec", "vpiStructTypespec", "vpiUnionTypespec", "vpiBitTypespec", "vpiLogicTypespec", "vpiArrayTypespec", "vpiVoidTypespec", "vpiTypespecMember", "vpiDistItem", "vpiAliasStmt", "vpiThread", "vpiMethodFuncCall", "vpiMethodTaskCall", "vpiClockingBlock", "vpiClockingIODecl", "vpiClassDefn", "vpiConstraint", "vpiConstraintOrdering", "vpiPropertyDecl", "vpiPropertySpec", "vpiPropertyExpr", "vpiMulticlockSequenceExpr", "vpiClockedSeq", "vpiPropertyInst", "vpiSequenceDecl", "vpiCaseProperty", "*undefined*", // 663 is not defined for object types "vpiSequenceInst", "vpiImmediateAssert", "vpiReturn", "vpiAnyPattern", "vpiTaggedPattern", "vpiStructPattern", "vpiDoWhile", "vpiOrderedWait", "vpiWaitFork", "vpiDisableFork", "vpiExpectStmt", "vpiForeachStmt", "vpiFinal", "vpiExtends", "vpiDistribution", "vpiSeqFormalDecl", "vpiEnumNet", "vpiIntegerNet", "vpiTimeNet", "vpiStructNet", "vpiBreak", "vpiContinue", "vpiAssert", "vpiAssume", "vpiCover", "vpiDisableCondition", "vpiClockingEvent", "vpiReturnStmt", "vpiPackedArrayTypespec", "vpiPackedArrayNet", "vpiImmediateAssume", "vpiImmediateCover", "vpiSequenceTypespec", "vpiPropertyTypespec", "vpiEventTypespec", "vpiPropFormalDecl", }; // clang-format on if (vpiVal < 0) return names[0]; else if (vpiVal <= vpiAutomatics) return names[vpiVal]; else if (vpiVal >= vpiPackage && vpiVal <= vpiPropFormalDecl) return sv_names1[(vpiVal - vpiPackage)]; else return names[0]; } const char* strFromVpiMethod(PLI_INT32 vpiVal) { // clang-format off static const char* const names[] = { "vpiCondition", "vpiDelay", "vpiElseStmt", "vpiForIncStmt", "vpiForInitStmt", "vpiHighConn", "vpiLhs", "vpiIndex", "vpiLeftRange", "vpiLowConn", "vpiParent", "vpiRhs", "vpiRightRange", "vpiScope", "vpiSysTfCall", "vpiTchkDataTerm", "vpiTchkNotifier", "vpiTchkRefTerm", "vpiArgument", "vpiBit", "vpiDriver", "vpiInternalScope", "vpiLoad", "vpiModDataPathIn", "vpiModPathIn", "vpiModPathOut", "vpiOperand", "vpiPortInst", "vpiProcess", "vpiVariables", "vpiUse", "vpiExpr", "vpiPrimitive", "vpiStmt" }; // clang-format on if (vpiVal > vpiStmt || vpiVal < vpiCondition) return "*undefined*"; return names[vpiVal - vpiCondition]; } const char* strFromVpiCallbackReason(PLI_INT32 vpiVal) { // clang-format off static const char* const names[] = { "*undefined*", "cbValueChange", "cbStmt", "cbForce", "cbRelease", "cbAtStartOfSimTime", "cbReadWriteSynch", "cbReadOnlySynch", "cbNextSimTime", "cbAfterDelay", "cbEndOfCompile", "cbStartOfSimulation", "cbEndOfSimulation", "cbError", "cbTchkViolation", "cbStartOfSave", "cbEndOfSave", "cbStartOfRestart", "cbEndOfRestart", "cbStartOfReset", "cbEndOfReset", "cbEnterInteractive", "cbExitInteractive", "cbInteractiveScopeChange", "cbUnresolvedSystf", "cbAssign", "cbDeassign", "cbDisable", "cbPLIError", "cbSignal", "cbNBASynch", "cbAtEndOfSimTime" }; // clang-format on if (vpiVal < 0) return names[0]; return names[(vpiVal <= cbAtEndOfSimTime) ? vpiVal : 0]; } const char* strFromVpiProp(PLI_INT32 vpiVal) { // clang-format off static const char* const names[] = { "*undefined or other*", "vpiType", "vpiName", "vpiFullName", "vpiSize", "vpiFile", "vpiLineNo", "vpiTopModule", "vpiCellInstance", "vpiDefName", "vpiProtected", "vpiTimeUnit", "vpiTimePrecision", "vpiDefNetType", "vpiUnconnDrive", "vpiDefFile", "vpiDefLineNo", "vpiScalar", "vpiVector", "vpiExplicitName", "vpiDirection", "vpiConnByName", "vpiNetType", "vpiExplicitScalared", "vpiExplicitVectored", "vpiExpanded", "vpiImplicitDecl", "vpiChargeStrength", "vpiArray", "vpiPortIndex", "vpiTermIndex", "vpiStrength0", "vpiStrength1", "vpiPrimType", "vpiPolarity", "vpiDataPolarity", "vpiEdge", "vpiPathType", "vpiTchkType", "vpiOpType", "vpiConstType", "vpiBlocking", "vpiCaseType", "vpiFuncType", "vpiNetDeclAssign", "vpiUserDefn", "vpiScheduled", "*undefined*", "*undefined*", "vpiActive", "vpiAutomatic", "vpiCell", "vpiConfig", "vpiConstantSelect", "vpiDecompile", "vpiDefAttribute", "vpiDelayType", "vpiIteratorType", "vpiLibrary", "*undefined*", "vpiOffset", "vpiResolvedNetType", "vpiSaveRestartID", "vpiSaveRestartLocation", "vpiValid", "vpiSigned", "vpiStop", "vpiFinish", "vpiReset", "vpiSetInteractiveScope", "vpiLocalParam", "vpiModPathHasIfNone", "vpiIndexedPartSelectType", "vpiIsMemory", "vpiIsProtected" }; // clang-format on if (vpiVal == vpiUndefined) return "vpiUndefined"; return names[(vpiVal <= vpiIsProtected) ? vpiVal : 0]; } const char* strFromVpiConstType(PLI_INT32 constType) { // clang-format off static const char* const names[] = { "*undefined*", "vpiDecConst", "vpiRealConst", "vpiBinaryConst", "vpiOctConst", "vpiHexConst", "vpiStringConst", "vpiIntConst", "vpiTimeConst", }; // clang-format on if (constType < 0) return names[0]; return names[(constType <= vpiTimeConst) ? constType : 0]; } #define FILENM basename(strdup(__FILE__)) #define CHECK_RESULT_VH(got, exp) \ if ((got) != (exp)) { \ printf("%%Error: %s:%d: GOT = %p EXP = %p\n", FILENM, __LINE__, (got), (exp)); \ return __LINE__; \ } #define CHECK_RESULT_NZ(got) \ if (!(got)) { \ printf("%%Error: %s:%d: GOT = NULL EXP = !NULL\n", FILENM, __LINE__); \ return __LINE__; \ } #define CHECK_RESULT_Z(got) \ if (got) { \ printf("%%Error: %s:%d: GOT = !NULL EXP = NULL\n", FILENM, __LINE__); \ return __LINE__; \ } // Use cout to avoid issues with %d/%lx etc #define CHECK_RESULT(got, exp) \ if ((got) != (exp)) { \ std::cout << std::dec << "%Error: " << FILENM << ":" << __LINE__ << ": GOT = " << (got) \ << " EXP = " << (exp) << std::endl; \ return __LINE__; \ } #define CHECK_RESULT_HEX(got, exp) \ if ((got) != (exp)) { \ std::cout << std::dec << "%Error: " << FILENM << ":" << __LINE__ << std::hex \ << ": GOT = " << (got) << " EXP = " << (exp) << std::endl; \ return __LINE__; \ } #define CHECK_RESULT_CSTR(got, exp) \ if (std::strcmp((got), (exp))) { \ printf("%%Error: %s:%d: GOT = '%s' EXP = '%s'\n", FILENM, __LINE__, \ (got) ? (got) : "", (exp) ? (exp) : ""); \ return __LINE__; \ } #define CHECK_RESULT_CSTR_STRIP(got, exp) CHECK_RESULT_CSTR(got + strspn(got, " "), exp) verilator-5.042/test_regress/t/t_expect.v0000644000542200017500000000113515101701376021070 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg a; reg b; initial begin #10; expect (@(posedge clk) a ##1 b) a = 110; #10; expect (@(posedge clk) a ##1 b) else a = 299; #10; expect (@(posedge clk) a ##1 b) a = 300; else a = 399; end // TODO set a/b appropriately - this is just a parsing test currently endmodule verilator-5.042/test_regress/t/t_lint_input_eq_good.py0000755000542200017500000000070315101701376023650 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint() test.passes() verilator-5.042/test_regress/t/t_unroll_delay.py0000755000542200017500000000105115101701376022454 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--binary --trace-vcd']) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_func_wide_out.v0000644000542200017500000000730115101701376022433 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); typedef bit signed [11:0] s12_t; typedef bit unsigned [11:0] u12_t; typedef bit signed [69:0] s70_t; typedef bit unsigned [69:0] u70_t; import "DPI-C" context function void dpii_inv_s12(input s12_t in, output s12_t out); import "DPI-C" context function void dpii_inv_u12(input u12_t in, output u12_t out); import "DPI-C" context function void dpii_inv_s70(input s70_t in, output s70_t out); import "DPI-C" context function void dpii_inv_u70(input s70_t in, output u70_t out); class Cls #(type T = bit); static function void get(inout T value); `ifdef TEST_NOINLINE // verilator no_inline_task `endif value = ~value; endfunction endclass module t; parameter MSG_PORT_WIDTH = 4350; localparam PAYLOAD_MAX_BITS = 4352; reg [MSG_PORT_WIDTH-1:0] msg; function void func (output bit [PAYLOAD_MAX_BITS-1:0] data); `ifdef TEST_NOINLINE // verilator no_inline_task `endif data = {PAYLOAD_MAX_BITS{1'b1}}; endfunction s12_t ds12; u12_t du12; s70_t ds70; u70_t du70; s12_t qs12; u12_t qu12; s70_t qs70; u70_t qu70; initial begin // Operator TASKREF 'func' expects 4352 bits on the Function Argument, but Function Argument's VARREF 'msg' generates 4350 bits. // verilator lint_off WIDTHEXPAND func(msg); if (msg !== {MSG_PORT_WIDTH{1'b1}}) $stop; begin // narrow connect to wide ds12 = 12'h234; Cls#(s70_t)::get(ds12); `checkh(ds12, 12'hdcb); ds12 = 12'he34; // negative if signed Cls#(s70_t)::get(ds12); `checkh(ds12, 12'h1cb); du12 = 12'h244; Cls#(u70_t)::get(du12); `checkh(du12, 12'hdbb); du12 = 12'he34; // negative if signed Cls#(u70_t)::get(du12); `checkh(du12, 12'h1cb); // wie connect to narrow ds70 = 12'h254; Cls#(s12_t)::get(ds70); `checkh(ds70, 70'h3ffffffffffffffdab); ds70 = 12'he34; // negative if signed Cls#(s12_t)::get(ds70); `checkh(ds70, 70'h0000000000000001cb); du70 = 12'h264; Cls#(u12_t)::get(du70); `checkh(du70, 70'h000000000000000d9b); du70 = 12'he34; // negative if signed Cls#(u12_t)::get(du70); `checkh(du70, 70'h0000000000000001cb); end begin // narrow connect to wide ds12 = 12'h234; dpii_inv_s70(ds12, qs12); `checkh(qs12, 12'hdcb); ds12 = 12'he34; // negative if signed dpii_inv_s70(ds12, qs12); `checkh(qs12, 12'h1cb); du12 = 12'h244; dpii_inv_u70(du12, qu12); `checkh(qu12, 12'hdbb); du12 = 12'he34; // negative if signed dpii_inv_u70(ds12, qs12); `checkh(qs12, 12'h1cb); // wie connect to narrow ds70 = 12'h254; dpii_inv_s12(ds70, qs70); `checkh(qs70, 70'h3ffffffffffffffdab); ds70 = 12'he34; // negative if signed dpii_inv_s12(ds70, qs70); `checkh(qs70, 70'h0000000000000001cb); du70 = 12'h264; dpii_inv_u12(du70, qu70); `checkh(qu70, 70'h000000000000000d9b); du70 = 12'he34; // negative if signed dpii_inv_u12(du70, qu70); `checkh(qu70, 70'h0000000000000001cb); end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_interface_localparam.v0000644000542200017500000000254115101701376023735 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2023 by Justin Thiel. // SPDX-License-Identifier: CC0-1.0 interface SimpleIntf #( parameter int VAL = 28 ) (); // This value is calculated incorrectly for other instances of // this interface when it is accessed via the HDL for any other // instance of this interface localparam int valDiv2 = VAL/2; localparam int valDiv4 = valDiv2/2; localparam bit mismatch2 = (VAL != (2*valDiv2) ); localparam bit mismatch4 = (VAL != (4*valDiv4) ); initial begin $write("%m: VAL %0d, valDiv2 %0d, mismatch2 %0d\n", VAL, valDiv2, mismatch2); $write("%m: VAL %0d, valDiv4 %0d, mismatch4 %0d\n", VAL, valDiv4, mismatch2); if (mismatch2) $stop; if (mismatch4) $stop; end endinterface module Core( SimpleIntf intf ); // this will constify and valDiv2 will have the default value localparam valDiv4Upper = intf.valDiv2; SimpleIntf #(.VAL(68)) core_intf (); initial begin if (intf.valDiv2 != valDiv4Upper) begin $display("%%Error: param = %0d", intf.valDiv2); end end endmodule module t(); SimpleIntf intf(); Core theCore (.intf); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_sys_file_basic_mcd.py0000755000542200017500000000217115101701376023570 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.unlink_ok(test.obj_dir + "/t_sys_file_basic_mcd.log") test.compile() test.execute(expect_filename=test.golden_filename) test.files_identical(test.obj_dir + "/t_sys_file_basic_mcd_test2_0.dat", test.t_dir + "/t_sys_file_basic_mcd_test2_0.dat") test.files_identical(test.obj_dir + "/t_sys_file_basic_mcd_test2_1.dat", test.t_dir + "/t_sys_file_basic_mcd_test2_1.dat") test.files_identical(test.obj_dir + "/t_sys_file_basic_mcd_test2_2.dat", test.t_dir + "/t_sys_file_basic_mcd_test2_2.dat") test.files_identical(test.obj_dir + "/t_sys_file_basic_mcd_test5.dat", test.t_dir + "/t_sys_file_basic_mcd_test5.dat") test.passes() verilator-5.042/test_regress/t/t_cover_line_cc_vlt.py0000755000542200017500000000176615101701376023457 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_cover_line.v" test.golden_filename = "t/t_cover_line.out" test.compile(verilator_flags2=['--cc', '--coverage-line', "t/t_cover_line.vlt"]) test.execute() # Read the input .v file and do any CHECK_COVER requests test.inline_checks() test.run(cmd=[ os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--annotate-points", "--annotate", test.obj_dir + "/annotated", test.obj_dir + "/coverage.dat", ], verilator_run=True) test.files_identical(test.obj_dir + "/annotated/t_cover_line.v", test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_opt_balance_cats.py0000755000542200017500000000131415101701376023246 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile( verilator_flags2=["--stats", "--build", "--gate-stmts", "10000", "--expand-limit", "128"]) test.file_grep(test.stats, r'Optimizations, FuncOpt concat trees balanced\s+(\d+)', 1) test.file_grep(test.stats, r'Optimizations, FuncOpt concat splits\s+(\d+)', 62) test.passes() verilator-5.042/test_regress/t/t_package_alone_bad.v0000644000542200017500000000033315101701376023156 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 export pkg::something; verilator-5.042/test_regress/t/t_preproc_persist_inc.v0000644000542200017500000000043415101701376023655 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `ifndef COMMON_GUARD `define COMMON_GUARD 1 Inside `__FILE__. `endif verilator-5.042/test_regress/t/t_assert_inside_cond_bad.py0000755000542200017500000000117715101701376024441 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_assert_inside_cond.v" test.compile(verilator_flags2=["-x-assign 0 --assert +define+T_ASSERT_INSIDE_COND_BAD"]) test.execute(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_to_basic_assignment_bad.py0000755000542200017500000000076615101701376026005 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_assert_future.py0000755000542200017500000000077115101701376022666 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--assert']) test.execute() test.passes() verilator-5.042/test_regress/t/t_with_suggest_bad.out0000644000542200017500000000120415101701376023461 0ustar mahmoudyfreeshell%Error: t/t_with_suggest_bad.v:16:25: Can't find definition of variable: 'itemm' : ... Suggested alternative: 'item' 16 | qv = q.find with (itemm == 2); | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_with_suggest_bad.v:18:37: Can't find definition of variable: 'misspelledd' : ... Suggested alternative: 'misspelled' 18 | qv = q.find(misspelled) with (misspelledd == 2); | ^~~~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_array_pattern_bad.v0000644000542200017500000000075015101701376023263 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // bug1364 module t (/*AUTOARG*/ // Inputs clk, res ); input clk; input res; typedef struct packed { logic [3:0] port_num; } info_t; info_t myinfo; always_comb myinfo = '{default: '0, valids: '1}; endmodule verilator-5.042/test_regress/t/t_func_purification.v0000644000542200017500000000076115101701376023313 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t; initial begin if (0 & func(1)) $stop; $write("*-* All Finished *-*\n"); $finish; end function bit func(bit x); if (x) begin if (x) begin return 1; end else begin $c(""); end return 0; end endfunction endmodule verilator-5.042/test_regress/t/t_split_var_3_wreal.py0000755000542200017500000000130015101701376023377 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--stats', "-fno-dfg"]) test.execute() test.file_grep(test.stats, r'SplitVar,\s+packed variables split due to attribute\s+(\d+)', 0) test.file_grep(test.stats, r'SplitVar,\s+unpacked arrays split due to attribute\s+(\d+)', 3) test.passes() verilator-5.042/test_regress/t/t_cast_size_bad.v0000644000542200017500000000051015101701376022366 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; int a; reg [3:0] b; initial begin a = 1; b = (-1)'(a); // Bad end endmodule verilator-5.042/test_regress/t/t_sys_readmem_bad_addr2.mem0000644000542200017500000000054215101701376024304 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test data file // // Copyright 2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 @10x 10x verilator-5.042/test_regress/t/t_func_nansi_dup_bad.out0000644000542200017500000000122715101701376023745 0ustar mahmoudyfreeshell%Error: t/t_func_nansi_dup_bad.v:14:9: Duplicate declaration of signal: 'bad4' 14 | reg bad4; | ^~~~ t/t_func_nansi_dup_bad.v:12:17: ... Location of original declaration 12 | input [7:0] bad4; | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_func_nansi_dup_bad.v:19:17: Duplicate declaration of signal: 'bad5' 19 | input [7:0] bad5; | ^~~~ t/t_func_nansi_dup_bad.v:18:17: ... Location of original declaration 18 | input [7:0] bad5; | ^~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_nonsequential_udp.v0000755000542200017500000000250315101701376023340 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Mike Thyer. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg a, b, sel, z; udp_mux2(z, a, b, sel); int cycle=0; always @(posedge clk) begin cycle <= cycle+1; if (cycle==0) begin a = 0; b = 1; sel = 0; end else if (cycle==1) begin a = 1; b = 1; sel = 0; if (z != 0) $stop; end else if (cycle==2) begin a = 0; b = 1; sel = 0; if (z != 1) $stop; end else if (cycle==3) begin a = 1; b = 0; sel = 0; if (z != 0) $stop; end else if (cycle==4) begin if (z != 1) $stop; end else if (cycle >= 5) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule primitive udp_mux2 (z, a, b, sel); output z; input a, b, sel; table //a b s o ? 1 1 : 1 ; ? 0 1 : 0 ; 1 ? 0 : 1 ; 0 ? 0 : 0 ; 1 1 x : 1 ; // Next blank line is intentional for parser // Next \ at EOL is intentional for parser 0 0 x \ : 0 ; endtable endprimitive verilator-5.042/test_regress/t/t_parse_delay_timing.py0000755000542200017500000000102115101701376023617 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_parse_delay.v" test.compile(verilator_flags2=['--binary']) test.passes() verilator-5.042/test_regress/t/t_func_tie_bad.v0000644000542200017500000000066215101701376022206 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin // verilator lint_off IGNOREDRETURN func(0, 1'b1); end function automatic int func ( input int a, output bit b ); return 0; endfunction endmodule verilator-5.042/test_regress/t/t_trace_dumpvars_dyn.v0000644000542200017500000000150015101701376023465 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; int cyc; sub1 #(10) sub1a (.*); sub1 #(20) sub1b (.*); always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 10) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module sub1 #(parameter int ADD) (input int cyc); int value; always_comb value = cyc + ADD; sub2 #(ADD + 1) sub2a(.*); sub2 #(ADD + 2) sub2b(.*); sub2 #(ADD + 3) sub2c(.*); endmodule module sub2 #(parameter int ADD) (input int cyc); int value; always_comb value = cyc + ADD; endmodule verilator-5.042/test_regress/t/t_assert_ctl_arg.dat.out0000644000542200017500000005176415101701376023722 0ustar mahmoudyfreeshell# SystemC::Coverage-3 C 'ft/t_assert_ctl_arg.vl100n32tuserpagev_user/tocover_simple_immediate_100htop.t.cover_simple_immediate_100' 1 C 'ft/t_assert_ctl_arg.vl100n37tuserpagev_user/tocover_simple_immediate_stmt_100htop.t.cover_simple_immediate_stmt_100' 1 C 'ft/t_assert_ctl_arg.vl100n40tuserpagev_user/tocover_final_deferred_immediate_100htop.t.cover_final_deferred_immediate_100' 1 C 'ft/t_assert_ctl_arg.vl100n43tuserpagev_user/tocover_observed_deferred_immediate_100htop.t.cover_observed_deferred_immediate_100' 1 C 'ft/t_assert_ctl_arg.vl100n45tuserpagev_user/tocover_final_deferred_immediate_stmt_100htop.t.cover_final_deferred_immediate_stmt_100' 1 C 'ft/t_assert_ctl_arg.vl100n48tuserpagev_user/tocover_observed_deferred_immediate_stmt_100htop.t.cover_observed_deferred_immediate_stmt_100' 1 C 'ft/t_assert_ctl_arg.vl103n32tuserpagev_user/tocover_simple_immediate_103htop.t.cover_simple_immediate_103' 0 C 'ft/t_assert_ctl_arg.vl103n37tuserpagev_user/tocover_simple_immediate_stmt_103htop.t.cover_simple_immediate_stmt_103' 0 C 'ft/t_assert_ctl_arg.vl103n40tuserpagev_user/tocover_final_deferred_immediate_103htop.t.cover_final_deferred_immediate_103' 0 C 'ft/t_assert_ctl_arg.vl103n43tuserpagev_user/tocover_observed_deferred_immediate_103htop.t.cover_observed_deferred_immediate_103' 0 C 'ft/t_assert_ctl_arg.vl103n45tuserpagev_user/tocover_final_deferred_immediate_stmt_103htop.t.cover_final_deferred_immediate_stmt_103' 0 C 'ft/t_assert_ctl_arg.vl103n48tuserpagev_user/tocover_observed_deferred_immediate_stmt_103htop.t.cover_observed_deferred_immediate_stmt_103' 0 C 'ft/t_assert_ctl_arg.vl106n32tuserpagev_user/tocover_simple_immediate_106htop.t.cover_simple_immediate_106' 1 C 'ft/t_assert_ctl_arg.vl106n37tuserpagev_user/tocover_simple_immediate_stmt_106htop.t.cover_simple_immediate_stmt_106' 1 C 'ft/t_assert_ctl_arg.vl106n40tuserpagev_user/tocover_final_deferred_immediate_106htop.t.cover_final_deferred_immediate_106' 1 C 'ft/t_assert_ctl_arg.vl106n43tuserpagev_user/tocover_observed_deferred_immediate_106htop.t.cover_observed_deferred_immediate_106' 1 C 'ft/t_assert_ctl_arg.vl106n45tuserpagev_user/tocover_final_deferred_immediate_stmt_106htop.t.cover_final_deferred_immediate_stmt_106' 1 C 'ft/t_assert_ctl_arg.vl106n48tuserpagev_user/tocover_observed_deferred_immediate_stmt_106htop.t.cover_observed_deferred_immediate_stmt_106' 1 C 'ft/t_assert_ctl_arg.vl108n32tuserpagev_user/tocover_simple_immediate_108htop.t.cover_simple_immediate_108' 1 C 'ft/t_assert_ctl_arg.vl108n37tuserpagev_user/tocover_simple_immediate_stmt_108htop.t.cover_simple_immediate_stmt_108' 1 C 'ft/t_assert_ctl_arg.vl108n40tuserpagev_user/tocover_final_deferred_immediate_108htop.t.cover_final_deferred_immediate_108' 1 C 'ft/t_assert_ctl_arg.vl108n43tuserpagev_user/tocover_observed_deferred_immediate_108htop.t.cover_observed_deferred_immediate_108' 1 C 'ft/t_assert_ctl_arg.vl108n45tuserpagev_user/tocover_final_deferred_immediate_stmt_108htop.t.cover_final_deferred_immediate_stmt_108' 1 C 'ft/t_assert_ctl_arg.vl108n48tuserpagev_user/tocover_observed_deferred_immediate_stmt_108htop.t.cover_observed_deferred_immediate_stmt_108' 1 C 'ft/t_assert_ctl_arg.vl110n32tuserpagev_user/tocover_simple_immediate_110htop.t.cover_simple_immediate_110' 0 C 'ft/t_assert_ctl_arg.vl110n37tuserpagev_user/tocover_simple_immediate_stmt_110htop.t.cover_simple_immediate_stmt_110' 0 C 'ft/t_assert_ctl_arg.vl110n40tuserpagev_user/tocover_final_deferred_immediate_110htop.t.cover_final_deferred_immediate_110' 0 C 'ft/t_assert_ctl_arg.vl110n43tuserpagev_user/tocover_observed_deferred_immediate_110htop.t.cover_observed_deferred_immediate_110' 0 C 'ft/t_assert_ctl_arg.vl110n45tuserpagev_user/tocover_final_deferred_immediate_stmt_110htop.t.cover_final_deferred_immediate_stmt_110' 0 C 'ft/t_assert_ctl_arg.vl110n48tuserpagev_user/tocover_observed_deferred_immediate_stmt_110htop.t.cover_observed_deferred_immediate_stmt_110' 0 C 'ft/t_assert_ctl_arg.vl112n32tuserpagev_user/tocover_simple_immediate_112htop.t.cover_simple_immediate_112' 1 C 'ft/t_assert_ctl_arg.vl112n37tuserpagev_user/tocover_simple_immediate_stmt_112htop.t.cover_simple_immediate_stmt_112' 1 C 'ft/t_assert_ctl_arg.vl112n40tuserpagev_user/tocover_final_deferred_immediate_112htop.t.cover_final_deferred_immediate_112' 1 C 'ft/t_assert_ctl_arg.vl112n43tuserpagev_user/tocover_observed_deferred_immediate_112htop.t.cover_observed_deferred_immediate_112' 0 C 'ft/t_assert_ctl_arg.vl112n45tuserpagev_user/tocover_final_deferred_immediate_stmt_112htop.t.cover_final_deferred_immediate_stmt_112' 1 C 'ft/t_assert_ctl_arg.vl112n48tuserpagev_user/tocover_observed_deferred_immediate_stmt_112htop.t.cover_observed_deferred_immediate_stmt_112' 0 C 'ft/t_assert_ctl_arg.vl192n22tuserpagev_user/concurrentocover_concurrenthtop.t.concurrent.cover_concurrent' 0 C 'ft/t_assert_ctl_arg.vl193n27tuserpagev_user/concurrentocover_concurrent_stmthtop.t.concurrent.cover_concurrent_stmt' 0 C 'ft/t_assert_ctl_arg.vl49n31tuserpagev_user/tocover_simple_immediate_49htop.t.cover_simple_immediate_49' 1 C 'ft/t_assert_ctl_arg.vl49n36tuserpagev_user/tocover_simple_immediate_stmt_49htop.t.cover_simple_immediate_stmt_49' 1 C 'ft/t_assert_ctl_arg.vl49n39tuserpagev_user/tocover_final_deferred_immediate_49htop.t.cover_final_deferred_immediate_49' 0 C 'ft/t_assert_ctl_arg.vl49n42tuserpagev_user/tocover_observed_deferred_immediate_49htop.t.cover_observed_deferred_immediate_49' 0 C 'ft/t_assert_ctl_arg.vl49n44tuserpagev_user/tocover_final_deferred_immediate_stmt_49htop.t.cover_final_deferred_immediate_stmt_49' 0 C 'ft/t_assert_ctl_arg.vl49n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_49htop.t.cover_observed_deferred_immediate_stmt_49' 0 C 'ft/t_assert_ctl_arg.vl51n31tuserpagev_user/tocover_simple_immediate_51htop.t.cover_simple_immediate_51' 0 C 'ft/t_assert_ctl_arg.vl51n36tuserpagev_user/tocover_simple_immediate_stmt_51htop.t.cover_simple_immediate_stmt_51' 0 C 'ft/t_assert_ctl_arg.vl51n39tuserpagev_user/tocover_final_deferred_immediate_51htop.t.cover_final_deferred_immediate_51' 0 C 'ft/t_assert_ctl_arg.vl51n42tuserpagev_user/tocover_observed_deferred_immediate_51htop.t.cover_observed_deferred_immediate_51' 0 C 'ft/t_assert_ctl_arg.vl51n44tuserpagev_user/tocover_final_deferred_immediate_stmt_51htop.t.cover_final_deferred_immediate_stmt_51' 0 C 'ft/t_assert_ctl_arg.vl51n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_51htop.t.cover_observed_deferred_immediate_stmt_51' 0 C 'ft/t_assert_ctl_arg.vl56n31tuserpagev_user/tocover_simple_immediate_56htop.t.cover_simple_immediate_56' 0 C 'ft/t_assert_ctl_arg.vl56n36tuserpagev_user/tocover_simple_immediate_stmt_56htop.t.cover_simple_immediate_stmt_56' 0 C 'ft/t_assert_ctl_arg.vl56n39tuserpagev_user/tocover_final_deferred_immediate_56htop.t.cover_final_deferred_immediate_56' 0 C 'ft/t_assert_ctl_arg.vl56n42tuserpagev_user/tocover_observed_deferred_immediate_56htop.t.cover_observed_deferred_immediate_56' 1 C 'ft/t_assert_ctl_arg.vl56n44tuserpagev_user/tocover_final_deferred_immediate_stmt_56htop.t.cover_final_deferred_immediate_stmt_56' 0 C 'ft/t_assert_ctl_arg.vl56n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_56htop.t.cover_observed_deferred_immediate_stmt_56' 1 C 'ft/t_assert_ctl_arg.vl58n31tuserpagev_user/tocover_simple_immediate_58htop.t.cover_simple_immediate_58' 0 C 'ft/t_assert_ctl_arg.vl58n36tuserpagev_user/tocover_simple_immediate_stmt_58htop.t.cover_simple_immediate_stmt_58' 0 C 'ft/t_assert_ctl_arg.vl58n39tuserpagev_user/tocover_final_deferred_immediate_58htop.t.cover_final_deferred_immediate_58' 0 C 'ft/t_assert_ctl_arg.vl58n42tuserpagev_user/tocover_observed_deferred_immediate_58htop.t.cover_observed_deferred_immediate_58' 0 C 'ft/t_assert_ctl_arg.vl58n44tuserpagev_user/tocover_final_deferred_immediate_stmt_58htop.t.cover_final_deferred_immediate_stmt_58' 0 C 'ft/t_assert_ctl_arg.vl58n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_58htop.t.cover_observed_deferred_immediate_stmt_58' 0 C 'ft/t_assert_ctl_arg.vl63n31tuserpagev_user/tocover_simple_immediate_63htop.t.cover_simple_immediate_63' 0 C 'ft/t_assert_ctl_arg.vl63n36tuserpagev_user/tocover_simple_immediate_stmt_63htop.t.cover_simple_immediate_stmt_63' 0 C 'ft/t_assert_ctl_arg.vl63n39tuserpagev_user/tocover_final_deferred_immediate_63htop.t.cover_final_deferred_immediate_63' 1 C 'ft/t_assert_ctl_arg.vl63n42tuserpagev_user/tocover_observed_deferred_immediate_63htop.t.cover_observed_deferred_immediate_63' 0 C 'ft/t_assert_ctl_arg.vl63n44tuserpagev_user/tocover_final_deferred_immediate_stmt_63htop.t.cover_final_deferred_immediate_stmt_63' 1 C 'ft/t_assert_ctl_arg.vl63n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_63htop.t.cover_observed_deferred_immediate_stmt_63' 0 C 'ft/t_assert_ctl_arg.vl65n31tuserpagev_user/tocover_simple_immediate_65htop.t.cover_simple_immediate_65' 0 C 'ft/t_assert_ctl_arg.vl65n36tuserpagev_user/tocover_simple_immediate_stmt_65htop.t.cover_simple_immediate_stmt_65' 0 C 'ft/t_assert_ctl_arg.vl65n39tuserpagev_user/tocover_final_deferred_immediate_65htop.t.cover_final_deferred_immediate_65' 0 C 'ft/t_assert_ctl_arg.vl65n42tuserpagev_user/tocover_observed_deferred_immediate_65htop.t.cover_observed_deferred_immediate_65' 0 C 'ft/t_assert_ctl_arg.vl65n44tuserpagev_user/tocover_final_deferred_immediate_stmt_65htop.t.cover_final_deferred_immediate_stmt_65' 0 C 'ft/t_assert_ctl_arg.vl65n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_65htop.t.cover_observed_deferred_immediate_stmt_65' 0 C 'ft/t_assert_ctl_arg.vl69n31tuserpagev_user/tocover_simple_immediate_69htop.t.cover_simple_immediate_69' 0 C 'ft/t_assert_ctl_arg.vl69n36tuserpagev_user/tocover_simple_immediate_stmt_69htop.t.cover_simple_immediate_stmt_69' 0 C 'ft/t_assert_ctl_arg.vl69n39tuserpagev_user/tocover_final_deferred_immediate_69htop.t.cover_final_deferred_immediate_69' 0 C 'ft/t_assert_ctl_arg.vl69n42tuserpagev_user/tocover_observed_deferred_immediate_69htop.t.cover_observed_deferred_immediate_69' 0 C 'ft/t_assert_ctl_arg.vl69n44tuserpagev_user/tocover_final_deferred_immediate_stmt_69htop.t.cover_final_deferred_immediate_stmt_69' 0 C 'ft/t_assert_ctl_arg.vl69n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_69htop.t.cover_observed_deferred_immediate_stmt_69' 0 C 'ft/t_assert_ctl_arg.vl71n31tuserpagev_user/tocover_simple_immediate_71htop.t.cover_simple_immediate_71' 1 C 'ft/t_assert_ctl_arg.vl71n36tuserpagev_user/tocover_simple_immediate_stmt_71htop.t.cover_simple_immediate_stmt_71' 1 C 'ft/t_assert_ctl_arg.vl71n39tuserpagev_user/tocover_final_deferred_immediate_71htop.t.cover_final_deferred_immediate_71' 1 C 'ft/t_assert_ctl_arg.vl71n42tuserpagev_user/tocover_observed_deferred_immediate_71htop.t.cover_observed_deferred_immediate_71' 1 C 'ft/t_assert_ctl_arg.vl71n44tuserpagev_user/tocover_final_deferred_immediate_stmt_71htop.t.cover_final_deferred_immediate_stmt_71' 1 C 'ft/t_assert_ctl_arg.vl71n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_71htop.t.cover_observed_deferred_immediate_stmt_71' 1 C 'ft/t_assert_ctl_arg.vl73n31tuserpagev_user/tocover_simple_immediate_73htop.t.cover_simple_immediate_73' 0 C 'ft/t_assert_ctl_arg.vl73n36tuserpagev_user/tocover_simple_immediate_stmt_73htop.t.cover_simple_immediate_stmt_73' 0 C 'ft/t_assert_ctl_arg.vl73n39tuserpagev_user/tocover_final_deferred_immediate_73htop.t.cover_final_deferred_immediate_73' 0 C 'ft/t_assert_ctl_arg.vl73n42tuserpagev_user/tocover_observed_deferred_immediate_73htop.t.cover_observed_deferred_immediate_73' 0 C 'ft/t_assert_ctl_arg.vl73n44tuserpagev_user/tocover_final_deferred_immediate_stmt_73htop.t.cover_final_deferred_immediate_stmt_73' 0 C 'ft/t_assert_ctl_arg.vl73n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_73htop.t.cover_observed_deferred_immediate_stmt_73' 0 C 'ft/t_assert_ctl_arg.vl76n31tuserpagev_user/tocover_simple_immediate_76htop.t.cover_simple_immediate_76' 1 C 'ft/t_assert_ctl_arg.vl76n36tuserpagev_user/tocover_simple_immediate_stmt_76htop.t.cover_simple_immediate_stmt_76' 1 C 'ft/t_assert_ctl_arg.vl76n39tuserpagev_user/tocover_final_deferred_immediate_76htop.t.cover_final_deferred_immediate_76' 0 C 'ft/t_assert_ctl_arg.vl76n42tuserpagev_user/tocover_observed_deferred_immediate_76htop.t.cover_observed_deferred_immediate_76' 1 C 'ft/t_assert_ctl_arg.vl76n44tuserpagev_user/tocover_final_deferred_immediate_stmt_76htop.t.cover_final_deferred_immediate_stmt_76' 0 C 'ft/t_assert_ctl_arg.vl76n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_76htop.t.cover_observed_deferred_immediate_stmt_76' 1 C 'ft/t_assert_ctl_arg.vl78n31tuserpagev_user/tocover_simple_immediate_78htop.t.cover_simple_immediate_78' 1 C 'ft/t_assert_ctl_arg.vl78n36tuserpagev_user/tocover_simple_immediate_stmt_78htop.t.cover_simple_immediate_stmt_78' 1 C 'ft/t_assert_ctl_arg.vl78n39tuserpagev_user/tocover_final_deferred_immediate_78htop.t.cover_final_deferred_immediate_78' 1 C 'ft/t_assert_ctl_arg.vl78n42tuserpagev_user/tocover_observed_deferred_immediate_78htop.t.cover_observed_deferred_immediate_78' 1 C 'ft/t_assert_ctl_arg.vl78n44tuserpagev_user/tocover_final_deferred_immediate_stmt_78htop.t.cover_final_deferred_immediate_stmt_78' 1 C 'ft/t_assert_ctl_arg.vl78n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_78htop.t.cover_observed_deferred_immediate_stmt_78' 1 C 'ft/t_assert_ctl_arg.vl80n31tuserpagev_user/tocover_simple_immediate_80htop.t.cover_simple_immediate_80' 1 C 'ft/t_assert_ctl_arg.vl80n36tuserpagev_user/tocover_simple_immediate_stmt_80htop.t.cover_simple_immediate_stmt_80' 1 C 'ft/t_assert_ctl_arg.vl80n39tuserpagev_user/tocover_final_deferred_immediate_80htop.t.cover_final_deferred_immediate_80' 0 C 'ft/t_assert_ctl_arg.vl80n42tuserpagev_user/tocover_observed_deferred_immediate_80htop.t.cover_observed_deferred_immediate_80' 0 C 'ft/t_assert_ctl_arg.vl80n44tuserpagev_user/tocover_final_deferred_immediate_stmt_80htop.t.cover_final_deferred_immediate_stmt_80' 0 C 'ft/t_assert_ctl_arg.vl80n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_80htop.t.cover_observed_deferred_immediate_stmt_80' 0 C 'ft/t_assert_ctl_arg.vl82n31tuserpagev_user/tocover_simple_immediate_82htop.t.cover_simple_immediate_82' 1 C 'ft/t_assert_ctl_arg.vl82n36tuserpagev_user/tocover_simple_immediate_stmt_82htop.t.cover_simple_immediate_stmt_82' 1 C 'ft/t_assert_ctl_arg.vl82n39tuserpagev_user/tocover_final_deferred_immediate_82htop.t.cover_final_deferred_immediate_82' 0 C 'ft/t_assert_ctl_arg.vl82n42tuserpagev_user/tocover_observed_deferred_immediate_82htop.t.cover_observed_deferred_immediate_82' 0 C 'ft/t_assert_ctl_arg.vl82n44tuserpagev_user/tocover_final_deferred_immediate_stmt_82htop.t.cover_final_deferred_immediate_stmt_82' 0 C 'ft/t_assert_ctl_arg.vl82n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_82htop.t.cover_observed_deferred_immediate_stmt_82' 0 C 'ft/t_assert_ctl_arg.vl84n31tuserpagev_user/tocover_simple_immediate_84htop.t.cover_simple_immediate_84' 0 C 'ft/t_assert_ctl_arg.vl84n36tuserpagev_user/tocover_simple_immediate_stmt_84htop.t.cover_simple_immediate_stmt_84' 0 C 'ft/t_assert_ctl_arg.vl84n39tuserpagev_user/tocover_final_deferred_immediate_84htop.t.cover_final_deferred_immediate_84' 0 C 'ft/t_assert_ctl_arg.vl84n42tuserpagev_user/tocover_observed_deferred_immediate_84htop.t.cover_observed_deferred_immediate_84' 0 C 'ft/t_assert_ctl_arg.vl84n44tuserpagev_user/tocover_final_deferred_immediate_stmt_84htop.t.cover_final_deferred_immediate_stmt_84' 0 C 'ft/t_assert_ctl_arg.vl84n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_84htop.t.cover_observed_deferred_immediate_stmt_84' 0 C 'ft/t_assert_ctl_arg.vl86n31tuserpagev_user/tocover_simple_immediate_86htop.t.cover_simple_immediate_86' 1 C 'ft/t_assert_ctl_arg.vl86n36tuserpagev_user/tocover_simple_immediate_stmt_86htop.t.cover_simple_immediate_stmt_86' 1 C 'ft/t_assert_ctl_arg.vl86n39tuserpagev_user/tocover_final_deferred_immediate_86htop.t.cover_final_deferred_immediate_86' 0 C 'ft/t_assert_ctl_arg.vl86n42tuserpagev_user/tocover_observed_deferred_immediate_86htop.t.cover_observed_deferred_immediate_86' 0 C 'ft/t_assert_ctl_arg.vl86n44tuserpagev_user/tocover_final_deferred_immediate_stmt_86htop.t.cover_final_deferred_immediate_stmt_86' 0 C 'ft/t_assert_ctl_arg.vl86n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_86htop.t.cover_observed_deferred_immediate_stmt_86' 0 C 'ft/t_assert_ctl_arg.vl88n31tuserpagev_user/tocover_simple_immediate_88htop.t.cover_simple_immediate_88' 0 C 'ft/t_assert_ctl_arg.vl88n36tuserpagev_user/tocover_simple_immediate_stmt_88htop.t.cover_simple_immediate_stmt_88' 0 C 'ft/t_assert_ctl_arg.vl88n39tuserpagev_user/tocover_final_deferred_immediate_88htop.t.cover_final_deferred_immediate_88' 0 C 'ft/t_assert_ctl_arg.vl88n42tuserpagev_user/tocover_observed_deferred_immediate_88htop.t.cover_observed_deferred_immediate_88' 0 C 'ft/t_assert_ctl_arg.vl88n44tuserpagev_user/tocover_final_deferred_immediate_stmt_88htop.t.cover_final_deferred_immediate_stmt_88' 0 C 'ft/t_assert_ctl_arg.vl88n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_88htop.t.cover_observed_deferred_immediate_stmt_88' 0 C 'ft/t_assert_ctl_arg.vl90n31tuserpagev_user/tocover_simple_immediate_90htop.t.cover_simple_immediate_90' 1 C 'ft/t_assert_ctl_arg.vl90n36tuserpagev_user/tocover_simple_immediate_stmt_90htop.t.cover_simple_immediate_stmt_90' 1 C 'ft/t_assert_ctl_arg.vl90n39tuserpagev_user/tocover_final_deferred_immediate_90htop.t.cover_final_deferred_immediate_90' 1 C 'ft/t_assert_ctl_arg.vl90n42tuserpagev_user/tocover_observed_deferred_immediate_90htop.t.cover_observed_deferred_immediate_90' 1 C 'ft/t_assert_ctl_arg.vl90n44tuserpagev_user/tocover_final_deferred_immediate_stmt_90htop.t.cover_final_deferred_immediate_stmt_90' 1 C 'ft/t_assert_ctl_arg.vl90n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_90htop.t.cover_observed_deferred_immediate_stmt_90' 1 C 'ft/t_assert_ctl_arg.vl92n31tuserpagev_user/tocover_simple_immediate_92htop.t.cover_simple_immediate_92' 0 C 'ft/t_assert_ctl_arg.vl92n36tuserpagev_user/tocover_simple_immediate_stmt_92htop.t.cover_simple_immediate_stmt_92' 0 C 'ft/t_assert_ctl_arg.vl92n39tuserpagev_user/tocover_final_deferred_immediate_92htop.t.cover_final_deferred_immediate_92' 0 C 'ft/t_assert_ctl_arg.vl92n42tuserpagev_user/tocover_observed_deferred_immediate_92htop.t.cover_observed_deferred_immediate_92' 0 C 'ft/t_assert_ctl_arg.vl92n44tuserpagev_user/tocover_final_deferred_immediate_stmt_92htop.t.cover_final_deferred_immediate_stmt_92' 0 C 'ft/t_assert_ctl_arg.vl92n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_92htop.t.cover_observed_deferred_immediate_stmt_92' 0 C 'ft/t_assert_ctl_arg.vl97n31tuserpagev_user/tocover_simple_immediate_97htop.t.cover_simple_immediate_97' 0 C 'ft/t_assert_ctl_arg.vl97n36tuserpagev_user/tocover_simple_immediate_stmt_97htop.t.cover_simple_immediate_stmt_97' 0 C 'ft/t_assert_ctl_arg.vl97n39tuserpagev_user/tocover_final_deferred_immediate_97htop.t.cover_final_deferred_immediate_97' 0 C 'ft/t_assert_ctl_arg.vl97n42tuserpagev_user/tocover_observed_deferred_immediate_97htop.t.cover_observed_deferred_immediate_97' 0 C 'ft/t_assert_ctl_arg.vl97n44tuserpagev_user/tocover_final_deferred_immediate_stmt_97htop.t.cover_final_deferred_immediate_stmt_97' 0 C 'ft/t_assert_ctl_arg.vl97n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_97htop.t.cover_observed_deferred_immediate_stmt_97' 0 verilator-5.042/test_regress/t/t_assert_disable_iff.v0000644000542200017500000000224215101701376023410 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Peter Monsson. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; int cyc; Test test (/*AUTOINST*/ // Inputs .clk (clk)); always @(posedge clk) begin cyc <= cyc + 1; if (cyc == 10) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test ( input clk ); `ifdef FAIL_ASSERT_1 assert property (@(posedge clk) disable iff (0) 0) else $display("wrong disable"); `endif assert property (@(posedge clk) disable iff (1) 0); assert property (@(posedge clk) disable iff (1) 1); assert property (@(posedge clk) disable iff (0) 1); // // Cover properties behave differently // cover property (@(posedge clk) disable iff (1) 1) $stop; cover property (@(posedge clk) disable iff (1) 0) $stop; cover property (@(posedge clk) disable iff (0) 1) $display("*COVER: ok"); cover property (@(posedge clk) disable iff (0) 0) $stop; endmodule verilator-5.042/test_regress/t/t_flag_f__3.v0000644000542200017500000000002315101701376021372 0ustar mahmoudyfreeshell`define GOT_DEF3 1 verilator-5.042/test_regress/t/t_fork_repeat.v0000644000542200017500000000122015101701376022074 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; bit clk; // Gen Clock always #10 clk = ~clk; initial begin fork begin forever @(posedge clk); end begin repeat(10) @(posedge clk); end begin for(int i=0; i < 6; ++i) @(posedge clk); end join_any $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_sys_file_basic_mcd.v0000644000542200017500000000767715101701376023422 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t; `define STR(__s) `"__s`" task automatic fail(string s); $display({"FAIL! Reason: ", s}); $stop; endtask task automatic test1; int fd[30], fd_fail, fd_success, fd_close, tmp; for (int i = 0; i < 30; i++) begin // Attempt to allocate 30 MCD descriptors; returned descriptors // should fall within correct range: [1, 30]. tmp = $fopen($sformatf("%s/some_file%0d.dat", `STR(`TEST_OBJ_DIR), i)); fd[i] = tmp; if ((fd[i] == 0) || !$onehot(fd[i])) fail($sformatf("MCD descriptor out of range %d", fd[i])); end // Attempt to allocate another MCD descriptor when all should // be used. We expect this operation to fail and return the // invalid descriptor (0). fd_fail = $fopen($sformatf("%s/another_file.dat", `STR(`TEST_OBJ_DIR))); if (fd_fail != 0) fail("Able to allocate MCD descriptor when fully utilized."); // Return descriptor back to pool fd_close = fd[0]; $fclose(fd_close); // Re-attempt MCD allocation; should pass at this point. fd_success = $fopen($sformatf("%s/yet_another_file.dat", `STR(`TEST_OBJ_DIR))); if (fd_success == 0) fail("Expect to have free descriptors at this point."); // Returned descriptor should have a value matching that which // had previously just been returned back to the pool. if (fd_success != fd[0]) fail("Descriptor has incorrect value."); // Return all descriptors back to the pool. for (int i = 1; i < 30; i++) begin fd_close = fd[i]; $fclose(fd_close); end endtask task automatic test2; // Validate basic MCD functionality. integer fd[3], fd_all, tmp; for (int i = 0; i < 3; i++) begin tmp = $fopen($sformatf("%s/t_sys_file_basic_mcd_test2_%0d.dat", `STR(`TEST_OBJ_DIR), i)); fd[i] = tmp; end fd_all = 0; for (int i = 0; i < 3; i++) fd_all |= fd[i]; $fwrite(fd_all, "Scotland is the greatest country.\n"); $fwrite(fd_all, "All other countries are inferior.\n"); $fwrite(fd_all, "Woe betide those to stand against the mighty Scottish nation.\n"); $fclose(fd_all); endtask task automatic test3; int result; // Write some things to standard output. $fwrite(32'h8000_0001, "Sean Connery was the best Bond.\n"); $fwrite(32'h8000_0001); $fstrobe(32'h8000_0001); result = $fseek(32'hffffffff, 0, 0); `checkd(result, -1); result = $ftell(32'hffffffff); `checkd(result, -1); result = $rewind(32'hffffffff); `checkd(result, -1); result = $feof(0); `checkd(result, 1); endtask task automatic test4; int fd; // Wide filename fd = $fopen({`STR(`TEST_OBJ_DIR), "/some_very_large_filename_that_no_one_would_ever_use_", "except_to_purposefully_break_my_beautiful_code.dat"}); if (fd == 0) fail("Long filename could not be opened."); $fclose(fd); endtask task automatic test5; int fd_all; fd_all = $fopen({`STR(`TEST_OBJ_DIR), "/t_sys_file_basic_mcd_test5.dat"}); if (fd_all == 0) fail("could not be opened."); fd_all |= 1; $fdisplay(fd_all, "To file and to stdout"); $fclose(fd_all); endtask initial begin // Test1: Validate file descriptor region. test1; // Test2: Validate basic MCD functionality. test2; // Test3: Validate explicit descriptor ID test3; // Test4: Validate filename lengths test4; // Test5: OR with stdout test5; $write("*-* All Finished *-*\n"); $finish(0); // Test arguments to finish end // initial begin `undef STR endmodule // t verilator-5.042/test_regress/t/t_preproc_kwd.v0000644000542200017500000000306615101701376022124 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; v95 v95 (); v01nc v01nc (); v01c v01c (); v05 v05 (); s05 s05 (); s09 s09 (); s12 s12 (); s17 s17 (); s23 s23 (); a23 a23 (); initial begin $finish; end endmodule `begin_keywords "1364-1995" module v95; integer signed; initial signed = 1; endmodule `end_keywords `begin_keywords "1364-2001-noconfig" module v01nc; localparam g = 0; integer instance; initial instance = 1; endmodule `end_keywords `begin_keywords "1364-2001" module v01c; localparam g = 0; integer bit; initial bit = 1; endmodule `end_keywords `begin_keywords "1364-2005" module v05; uwire w; integer final; initial final = 1; endmodule `end_keywords `begin_keywords "1800-2005" module s05; bit b; integer global; initial global = 1; endmodule `end_keywords `begin_keywords "1800-2009" module s09; bit b; integer soft; initial soft = 1; endmodule `end_keywords `begin_keywords "1800-2012" module s12; final begin $write("*-* All Finished *-*\n"); end endmodule `end_keywords `begin_keywords "1800-2017" module s17; final begin $write("*-* All Finished *-*\n"); end endmodule `end_keywords `begin_keywords "1800-2023" module s23; final begin $write("*-* All Finished *-*\n"); end endmodule `end_keywords `begin_keywords "VAMS-2.3" module a23; real foo; initial foo = sqrt(2.0); endmodule `end_keywords verilator-5.042/test_regress/t/t_interface_virtual_controlflow.v0000644000542200017500000000345415101701376025744 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 interface Bus1; logic [15:0] data; endinterface interface Bus2; logic [15:0] data; endinterface interface Bus3; logic [15:0] data; endinterface module t_controlflow; logic clk = 0; integer cyc = 0; Bus1 intf1(); Bus2 intf2(); Bus3 intf3(), intf4(); virtual Bus1 vif1 = intf1; virtual Bus2 vif2 = intf2; virtual Bus3 vif3 = intf3, vif4 = intf4; // Finish on negedge so that $finish is last always @(negedge clk) begin if (cyc >= 10) begin $write("*-* All Finished *-*\n"); $finish; end end function void assign_to_intf3(); intf3.data = 'hcafe; endfunction always @(posedge clk) begin cyc <= cyc + 1; if (cyc == 1 || cyc == 3 || cyc == 5) intf1.data = 'hdead; else vif2.data = 'hbeef; if (cyc == 1 || cyc == 3 || cyc == 5) begin if (cyc < 3) intf3.data = 'hfafa; intf4.data = 'hface; end if (cyc == 7) begin intf4.data = 'hcafe; end if (cyc == 9) begin assign_to_intf3; intf4.data = 'hdeaf; end end always @(vif1.data) begin $write("[%0t] vif1.data==%h\n", $time, vif1.data); end always @(intf2.data) begin $write("[%0t] intf2.data==%h\n", $time, intf2.data); end always @(vif3.data) begin $write("[%0t] vif3.data==%h\n", $time, vif3.data); end always @(intf4.data) begin $write("[%0t] intf4.data==%h\n", $time, intf4.data); end initial begin repeat (20) #5ns clk = ~clk; end endmodule verilator-5.042/test_regress/t/t_tri_array.py0000755000542200017500000000106015101701376021757 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) if not test.vlt_all: test.execute() test.passes() verilator-5.042/test_regress/t/t_implements_noninterface_bad.out0000644000542200017500000000103315101701376025655 0ustar mahmoudyfreeshell%Error: t/t_implements_noninterface_bad.v:10:26: Attempting to implement from non-interface class 'NotIcls' ... Suggest use 'extends' 10 | class ClsBad1 implements NotIcls; | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_implements_noninterface_bad.v:16:23: Attempting to extend from interface class 'Icls' ... Suggest use 'implements' 16 | class ClsBad2 extends Icls; | ^~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_assigndly_dynamic_notiming_bad.out0000644000542200017500000000060215101701376026353 0ustar mahmoudyfreeshell%Error-NOTIMING: t/t_assigndly_dynamic_notiming_bad.v:10:11: Delayed assignment in a non-inlined function/task requires --timing : ... note: In instance '$unit::Cls' 10 | qux <= '1; | ^~ ... For error description see https://verilator.org/warn/NOTIMING?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_lint_pragma_protected_bad.py0000755000542200017500000000106715101701376025146 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, verilator_flags2=['--lint-only -Wpedantic'], expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_randomize_this.v0000644000542200017500000000163715101701376022626 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Member; rand int m_val; endclass class Cls; rand int m_val; rand Member m_member; function void test; automatic int rand_result; logic ok1 = 0, ok2 = 0; m_val = 256; m_member.m_val = 65535; for (int i = 0; i < 20; i++) begin rand_result = randomize(); if (rand_result != 1) $stop; if (m_val != 256) ok1 = 1; if (m_member.m_val != 65535) ok2 = 1; end if (!ok1) $stop; if (!ok2) $stop; endfunction function new; m_member = new; endfunction endclass module t; initial begin Cls c; c = new; c.test; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_sys_writemem_b.gold5.mem0000644000542200017500000000162015101701376024151 0ustar mahmoudyfreeshell00000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000 11011100101110101001100001110110010101000000000000000100 00000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000 11011100101110101001100001110110010101000000000000001010 11011100101110101001100001110110010101000000000000001011 11011100101110101001100001110110010101000000000000001100 00000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000 verilator-5.042/test_regress/t/t_assign_slice_overflow.py0000755000542200017500000000073415101701376024360 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_disable_bad.v0000644000542200017500000000042415101701376022011 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t; initial begin disable abcd; end endmodule: t verilator-5.042/test_regress/t/t_threads_crazy.v0000644000542200017500000000077015101701376022446 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; int cyc; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc!=0) begin if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.042/test_regress/t/t_uniqueif_else.py0000755000542200017500000000077415101701376022633 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.compile(verilator_flags2=['--binary']) test.execute() test.passes() verilator-5.042/test_regress/t/t_covergroup_in_class_duplicate_bad.py0000755000542200017500000000077415101701376026704 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_mod_mod.out0000644000542200017500000000142115101701376021556 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_mod_mod.v:10:3: Unsupported: module decls within module decls 10 | program p_in_m(); | ^~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_mod_mod.v:12:3: Unsupported: program decls within module decls 12 | interface i_in_m(); | ^~~~~~~~~ %Error-UNSUPPORTED: t/t_mod_mod.v:14:1: Unsupported: interface decls within module decls 14 | endmodule | ^~~~~~~~~ %Error-UNSUPPORTED: t/t_mod_mod.v:19:3: Unsupported: interface decls within interface decls 19 | program p_in_i(); | ^~~~~~~ %Error-UNSUPPORTED: t/t_mod_mod.v:21:1: Unsupported: program decls within interface decls 21 | endinterface | ^~~~~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_lint_latch_casei_bad.v0000644000542200017500000000061415101701376023674 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module for Issue#1609 // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( input a, output reg o ); always_comb begin // verilator lint_off CASEINCOMPLETE case (a) 1'b0: o = 1; endcase end endmodule verilator-5.042/test_regress/t/t_assert_ctl_type_bad.py0000755000542200017500000000102515101701376023776 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=['--assert'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_func_impure_bad.out0000644000542200017500000000063015101701376023263 0ustar mahmoudyfreeshell%Error-IMPURE: t/t_func_impure_bad.v:11:9: Unsupported: External variable referenced by non-inlined function/task: 't.foo' 11 | task foo; | ^~~ t/t_func_impure_bad.v:13:7: ... Location of the external reference: 't.sig' 13 | sig = '1; | ^~~ ... For error description see https://verilator.org/warn/IMPURE?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_lint_width_bad.py0000755000542200017500000000076315101701376022747 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_module_input_default_value_1_bad.v0000644000542200017500000000221115101701376026226 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Andrew Ranck // SPDX-License-Identifier: CC0-1.0 // Test for Issue#5358: Support default value on module input. // This test *is* expected to not compile, and must match .out file. module dut_should_fail_compile1 ( input logic i = 1'b1, output logic o ); assign i = 1'b0; // bad, should fail post link in V3Width assign o = i; endmodule module t (/*AUTOARG*/ // Inputs clk ); input clk; int cyc = 0; // 1800-2009, a few flavors to test: // We should have some DUT instances that fail to compile, // if you tried having a default value on port output. logic dut_should_fail_o; dut_should_fail_compile1 u_dut_should_fail_compile1 (.i(1'b0), .o(dut_should_fail_o) ); always @(posedge clk) begin : main cyc <= cyc + 1; if (cyc == 10) begin // done checking various DUTs and finish $display("%t %m: cyc=%0d", $time, cyc); $write("*-* All Finished *-*\n"); $finish(); end end endmodule : t verilator-5.042/test_regress/t/t_clocking_concat.v0000644000542200017500000000163215101701376022722 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; logic[3:0] D1, D2, Q1, Q2; always @(posedge clk) begin {Q1, Q2} <= {D1, D2}; end always @(posedge clk) $display("[%0t] posedge clk", $time); clocking cb @(posedge clk); input #0 Q = {Q1, Q2}; output #0 D = {D1, D2}; endclocking initial $monitor("[%0t] --> D=%x\t\tQ=%x\t\tcb.Q=%x", $time, {D1,D2}, {Q1,Q2}, cb.Q); int cyc = 0; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc > 1 && cb.Q != {D1 - 4'd1, D2 - 4'd1}) $stop; cb.D <= {D1 + 4'd1, D2 + 4'd1}; if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_leak.cpp0000644000542200017500000000513415101701376021034 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test driver/expect definition // // Copyright 2003-2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 #include #include #include #include VM_PREFIX_INCLUDE unsigned int main_time = 0; double sc_time_stamp() { return main_time; } long long get_memory_usage() { // Return memory usage. Return 0 if the system doesn't look quite right. #if 0 // BSD only. struct rusage usage; getrusage(RUSAGE_SELF, &usage); return usage.ru_ixrss + usage.ru_idrss + usage.ru_isrss; #endif FILE* fp = fopen("/proc/self/stat", "r"); if (!fp) return 0; int ps_ign; uint64_t ps_vsize, ps_rss; int items = fscanf(fp, ("%d (%*[^) ]) %*1s %d %*d %*d %*d %*d %u" " %u %u %u %u %d %d %d %d" " %*d %*d %*u %*u %d %" PRIu64 " %" PRIu64 " "), &ps_ign, &ps_ign, &ps_ign, &ps_ign, &ps_ign, &ps_ign, &ps_ign, &ps_ign, &ps_ign, &ps_ign, &ps_ign, &ps_ign, &ps_vsize, &ps_rss); fclose(fp); if (items >= 14) { return ps_vsize; } else { return 0; } } void make_and_destroy() { VerilatedContext* contextp = new VerilatedContext; contextp->debug(0); VM_PREFIX* topp = new VM_PREFIX{contextp}; topp->eval(); topp->clk = true; while (!contextp->gotFinish()) { contextp->timeInc(5); topp->clk = !topp->clk; topp->eval(); } VL_DO_DANGLING(delete topp, topp); VL_DO_DANGLING(delete contextp, contextp); } int main(int argc, char* argv[]) { uint64_t firstUsage = get_memory_usage(); // Warmup phase for (int i = 0; i < 10; i++) { // make_and_destroy(); } firstUsage = get_memory_usage(); printf("Memory size %" PRId64 " bytes\n", firstUsage); int loops = 10; for (int left = loops; left > 0;) { for (int j = 0; j < 1; ++j, --left) { // make_and_destroy(); } } uint64_t leaked = get_memory_usage() - firstUsage; if (leaked > 64 * 1024) { // Have to allow some slop for this code. printf("Leaked %" PRId64 " bytes, or ~ %" PRId64 " bytes/construt\n", // leaked, leaked / loops); vl_fatal(__FILE__, __LINE__, "top", "Leaked memory\n"); } printf("*-* All Finished *-*\n"); } verilator-5.042/test_regress/t/t_time_passed.v0000644000542200017500000000244515101701376022102 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under The Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `timescale 1ns/1ps module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; time in; // verilator lint_off REALCVT initial in = 5432109876.543210ns; // Will round to time units // verilator lint_on REALCVT // This shows time changes when passed between modules with different units // See also discussion in uvm_tlm2_time.svh ps ps (.*); ns ns (.*); always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 60) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule `timescale 1ps/1ps module ps (input clk, input integer cyc, input time in); always @ (posedge clk) begin if (cyc == 10) begin $timeformat(-9, 6, "ns", 16); $write("%m: Input time %t %d\n", in, in); end end endmodule `timescale 1ns/1ps module ns (input clk, input integer cyc, input time in); always @ (posedge clk) begin if (cyc == 20) begin $timeformat(-9, 6, "ns", 16); $write("%m: Input time %t %d\n", in, in); end end endmodule verilator-5.042/test_regress/t/t_math_shiftrs.py0000755000542200017500000000073415101701376022465 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_struct_nest_uarray.py0000755000542200017500000000073415101701376023732 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_select_bad_range3.out0000644000542200017500000000076115101701376023472 0ustar mahmoudyfreeshell%Warning-SELRANGE: t/t_select_bad_range3.v:19:33: Selection index out of range: 13 outside 12:10 : ... note: In instance 't' 19 | assign outwires[12] = inwires[13]; | ^ ... For warning description see https://verilator.org/warn/SELRANGE?v=latest ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_randomize_inline_var_ctl_bad.py0000755000542200017500000000077615101701376025646 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_unroll_genf.v0000644000542200017500000000110215101701376022104 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 //bug830 module sub(); endmodule function integer cdiv(input integer x); begin cdiv = 10; end endfunction module t; genvar j; generate for (j = 0; j < cdiv(10); j=j+1) sub #() sub (); // #() for code coverage in verilog.y endgenerate initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_flag_language.v0000644000542200017500000000057415101701376022362 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; // See also t_preproc_kwd.v integer bit; initial bit = 1; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_dynarray_param.v0000644000542200017500000000303215101701376022607 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Noam Gallmann. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module t; localparam int SIZES [3:0] = '{1,2,3,4}; typedef int calc_sums_t [3:0]; localparam int SUMS_ARRAY [3:0] = calc_sums_array(SIZES, 4); function automatic calc_sums_t calc_sums_array(int s[3:0], int n); int sum = 0; for (int ii = 0; ii < n; ++ii) begin sum = sum + s[ii]; calc_sums_array[ii] = sum; end endfunction `ifndef VERILATOR localparam int SUMS_DYN [3:0] = calc_sums_dyn(SIZES, 4); `endif function automatic calc_sums_t calc_sums_dyn(int s[], int n); int sum = 0; for (int ii = 0; ii < n; ++ii) begin sum = sum + s[ii]; calc_sums_dyn[ii] = sum; end endfunction initial begin `checkh(SIZES[0], 4); `checkh(SIZES[1], 3); `checkh(SIZES[2], 2); `checkh(SIZES[3], 1); `checkh(SUMS_ARRAY[0], 4); `checkh(SUMS_ARRAY[1], 7); `checkh(SUMS_ARRAY[2], 9); `checkh(SUMS_ARRAY[3], 10); `ifndef VERILATOR `checkh(SUMS_DYN[0], 1); `checkh(SUMS_DYN[1], 3); `checkh(SUMS_DYN[2], 6); `checkh(SUMS_DYN[3], 10); `endif $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_vams_kwd_bad.v0000644000542200017500000000254515101701376022227 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Driss Hafdi. // SPDX-License-Identifier: CC0-1.0 `begin_keywords "VAMS-2.3" module t; // Just get errors on bad keywords (for code coverage) int above; int abs; int absdelay; int abstol; int ac_stim; int access; int acos; int acosh; int aliasparam; int analog; int analysis; int assert; int branch; int connect; int connectmodule; int connectrules; int continuous; int cross; int ddt; int ddt_nature; int ddx; int discipline; int discrete; int domain; int driver_update; int endconnectrules; int enddiscipline; int endnature; int endparamset; int exclude; int final_step; int flicker_noise; int flow; int from; int ground; int idt; int idt_nature; int idtmod; int inf; int initial_step; int laplace_nd; int laplace_np; int laplace_zd; int laplace_zp; int last_crossing; int limexp; int max; int merged; int min; int nature; int net_resolution; int noise_table; int paramset; int potential; int resolveto; int slew; int split; int timer; int transition; int units; int white_noise; int zi_nd; int zi_np; int zi_zd; int zi_zp; endmodule verilator-5.042/test_regress/t/t_flag_main_top_name.v0000644000542200017500000000126315101701376023401 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2023 by Don Williamson and Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module top; string scope; initial begin scope = $sformatf("%m"); $write("[%0t] In %s\n", $time, scope); `ifdef MAIN_TOP_NAME_EMPTY if (scope != "top") $stop; `else if (scope != "ALTOP.top") $stop; `endif $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_const_op_red_scope.py0000755000542200017500000000073415101701376023641 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_defaultparam_import.py0000755000542200017500000000070615101701376025215 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.passes() verilator-5.042/test_regress/t/t_lint_always_comb_bad.out0000644000542200017500000000260315101701376024277 0ustar mahmoudyfreeshell%Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:29:9: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'temp1' : ... note: In instance 't' 29 | temp1 = 'h0; | ^~~~~ ... For error description see https://verilator.org/warn/PROCASSWIRE?v=latest %Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:31:9: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'temp1' : ... note: In instance 't' 31 | temp1 = (temp1_d1r - 'h1); | ^~~~~ %Warning-ALWCOMBORDER: t/t_lint_always_comb_bad.v:32:7: Always_comb variable driven after use: 'mid' : ... note: In instance 't' 32 | mid = (temp1_d1r == 'h0); | ^~~ ... For warning description see https://verilator.org/warn/ALWCOMBORDER?v=latest ... Use "/* verilator lint_off ALWCOMBORDER */" and lint_on around source to disable this message. %Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:46:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'temp1_d1r' : ... note: In instance 't' 46 | temp1_d1r <= temp1; | ^~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_timing_zerodly_unsup.py0000755000542200017500000000106615101701376024262 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--exe --main --timing"]) test.execute(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_opt_merge_cond_no_motion.py0000755000542200017500000000164515101701376025041 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_opt_merge_cond.v" test.compile(verilator_flags2=["-unroll-count 64", "--stats", "-fno-merge-cond-motion"]) test.execute() if test.vlt: # Note, with vltmt this might be split differently, so only checking vlt test.file_grep(test.stats, r'Optimizations, MergeCond merges\s+(\d+)', 10) test.file_grep(test.stats, r'Optimizations, MergeCond merged items\s+(\d+)', 580) test.file_grep(test.stats, r'Optimizations, MergeCond longest merge\s+(\d+)', 64) test.passes() verilator-5.042/test_regress/t/t_covergroup_in_class_colliding.v0000644000542200017500000000116415101701376025674 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off COVERIGN */ class myClass; covergroup embeddedCg; endgroup function new(); real r; embeddedCg = new(); embeddedCg.sample(); r = embeddedCg.get_coverage(); endfunction endclass class secondClass; covergroup embeddedCg; endgroup function new(); real r; embeddedCg = new(); embeddedCg.sample(); r = embeddedCg.get_coverage(); endfunction endclass verilator-5.042/test_regress/t/t_gen_class.v0000644000542200017500000000364015101701376021541 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module Child; int ch_value; endmodule module Parent; for (genvar i = 0; i < 10; i++) begin : gen_child Child child(); end endmodule module t; Parent parent(); virtual class ChildAgentBase; pure virtual task preload(int value); pure virtual function string name(); endclass ChildAgentBase child_agents[10]; for (genvar i = 0; i < 10; i++) begin : gfor class ChildAgent extends ChildAgentBase; task automatic preload(int value); parent.gen_child[i].child.ch_value = value; endtask function string name(); return $sformatf("%m"); endfunction endclass ChildAgent agent = new(); initial child_agents[i] = agent; end task automatic preload_children; for (int i = 0; i < 10; i++) begin child_agents[i].preload(i); end endtask string s; initial begin #1; // Ensure all class instances are initialized preload_children(); `checkh(parent.gen_child[3].child.ch_value, 3); `checkh(parent.gen_child[8].child.ch_value, 8); `ifdef VERILATOR // Some legal examples "t.gfor[4].\ChildAgent::name", "t.gfor[4].ChildAgent.name" `checks(child_agents[4].name(), "t.gfor[4].ChildAgent.name"); `endif $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_lib_prot_clk_gated.py0000755000542200017500000000367515101701376023610 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt', 'xsim') test.top_filename = "t/t_lib_prot.v" if test.benchmark: test.sim_time = test.benchmark * 100 trace_opt = "" secret_prefix = "secret" secret_dir = test.obj_dir + "/" + secret_prefix test.mkdir_ok(secret_dir) # Always compile the secret file with Verilator no matter what simulator # we are testing with test.run( logfile=secret_dir + "/vlt_compile.log", cmd=["perl", os.environ["VERILATOR_ROOT"] + "/bin/verilator", '--no-timing', trace_opt, "--prefix", "Vt_lib_prot_secret", "-cc", "-Mdir", secret_dir, "-GGATED_CLK=1", "--protect-lib", secret_prefix, "--protect-key", "secret-key", "t/t_lib_prot_secret.v"], verilator_run=True) # yapf:disable test.run(logfile=secret_dir + "/secret_gcc.log", cmd=[os.environ["MAKE"], "-C", secret_dir, "-f", "Vt_lib_prot_secret.mk"]) test.compile(verilator_flags2=['--no-timing', trace_opt, "-GGATED_CLK=1", "-LDFLAGS", secret_prefix + "/libsecret.a", secret_dir + "/secret.sv"], xsim_flags2=[secret_dir + "/secret.sv"]) # yapf:disable test.execute(xsim_run_flags2=["--sv_lib", secret_dir + "/libsecret", "--dpi_absolute"]) if test.vlt and test.trace: # We can see the ports of the secret module test.file_grep(test.trace_filename, r'accum_in') # but we can't see what's inside test.file_grep_not(test.trace_filename, r'secret_') test.passes() verilator-5.042/test_regress/t/t_timing_finish2.py0000755000542200017500000000077115101701376022704 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--binary']) test.execute() test.passes() verilator-5.042/test_regress/t/t_concat_string.v0000644000542200017500000000167115101701376022442 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 typedef enum {efgh} en; module t; initial begin en e; string s; s = {"a", "b"}; if (s != "ab") $stop; e = efgh; s = {"abcd", e.name(), "ijkl"}; if (s != "abcdefghijkl") $stop; // hang V3Width if complexity grows exponential (2**52 should suffice) s = {"a", "b", "c", "d", "e", "f", "g", "h", "i", "j", "k", "l", "m", "n", "o", "p", "q", "r", "s", "t", "u", "v", "w", "x", "y", "z", "a", "b", "c", "d", "e", "f", "g", "h", "i", "j", "k", "l", "m", "n", "o", "p", "q", "r", "s", "t", "u", "v", "w", "x", "y", "z"}; if (s != "abcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyz") $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_clocked_release_combo.py0000755000542200017500000000073415101701376024255 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_json_only_flat_no_inline_mod.out0000644000542200017500000001354615101701376026064 0ustar mahmoudyfreeshell{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"(E)", "modulesp": [ {"type":"MODULE","name":"$root","addr":"(F)","loc":"d,11:8,11:11","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"$root","level":1,"modPublic":true,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"i_clk","addr":"(G)","loc":"d,11:24,11:29","dtypep":"(H)","origName":"i_clk","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"top.i_clk","addr":"(I)","loc":"d,11:24,11:29","dtypep":"(H)","origName":"i_clk","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"top.f.i_clk","addr":"(J)","loc":"d,7:24,7:29","dtypep":"(H)","origName":"i_clk","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"TOPSCOPE","name":"","addr":"(E)","loc":"d,11:8,11:11","senTreesp": [], "scopep": [ {"type":"SCOPE","name":"TOP","addr":"(K)","loc":"d,11:8,11:11","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(F)", "varsp": [ {"type":"VARSCOPE","name":"i_clk","addr":"(L)","loc":"d,11:24,11:29","dtypep":"(H)","isTrace":true,"scopep":"(K)","varp":"(G)"}, {"type":"VARSCOPE","name":"top.i_clk","addr":"(M)","loc":"d,11:24,11:29","dtypep":"(H)","isTrace":true,"scopep":"(K)","varp":"(I)"}, {"type":"ALWAYS","name":"","addr":"(N)","loc":"d,11:24,11:29","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(O)","loc":"d,11:24,11:29","dtypep":"(H)", "rhsp": [ {"type":"VARREF","name":"i_clk","addr":"(P)","loc":"d,11:24,11:29","dtypep":"(H)","access":"RD","varp":"(G)","varScopep":"(L)","classOrPackagep":"UNLINKED"} ], "lhsp": [ {"type":"VARREF","name":"top.i_clk","addr":"(Q)","loc":"d,11:24,11:29","dtypep":"(H)","access":"WR","varp":"(I)","varScopep":"(M)","classOrPackagep":"UNLINKED"} ],"timingControlp": [],"strengthSpecp": []} ]}, {"type":"VARSCOPE","name":"top.f.i_clk","addr":"(R)","loc":"d,7:24,7:29","dtypep":"(H)","isTrace":true,"scopep":"(K)","varp":"(J)"}, {"type":"ALWAYS","name":"","addr":"(S)","loc":"d,7:24,7:29","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(T)","loc":"d,7:24,7:29","dtypep":"(H)", "rhsp": [ {"type":"VARREF","name":"i_clk","addr":"(U)","loc":"d,7:24,7:29","dtypep":"(H)","access":"RD","varp":"(G)","varScopep":"(L)","classOrPackagep":"UNLINKED"} ], "lhsp": [ {"type":"VARREF","name":"top.f.i_clk","addr":"(V)","loc":"d,7:24,7:29","dtypep":"(H)","access":"WR","varp":"(J)","varScopep":"(R)","classOrPackagep":"UNLINKED"} ],"timingControlp": [],"strengthSpecp": []} ]} ],"blocksp": [],"inlinesp": []} ]} ]} ],"filesp": [], "miscsp": [ {"type":"TYPETABLE","name":"","addr":"(C)","loc":"a,0:0,0:0","constraintRefp":"UNLINKED","emptyQueuep":"UNLINKED","queueIndexp":"UNLINKED","streamp":"UNLINKED","voidp":"UNLINKED", "typesp": [ {"type":"BASICDTYPE","name":"logic","addr":"(H)","loc":"d,11:18,11:23","dtypep":"(H)","keyword":"logic","generic":true,"rangep": []} ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ {"type":"MODULE","name":"@CONST-POOL@","addr":"(W)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], "stmtsp": [ {"type":"SCOPE","name":"@CONST-POOL@","addr":"(X)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(W)","varsp": [],"blocksp": [],"inlinesp": []} ]} ]} ]} verilator-5.042/test_regress/t/t_interface_and_struct_pattern.py0000755000542200017500000000073415101701376025715 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_ascendingrange.py0000755000542200017500000000161415101701376024116 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') # CI environment offers 2 VCPUs, 2 thread setting causes the following warning. # %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. # Strangely, asking for more threads makes it go away. test.compile(verilator_flags2=['--cc --trace-vcd --trace-params -Wno-ASCRANGE'], threads=(6 if test.vltmt else 1)) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_pindup_bad.v0000644000542200017500000000115715101701376022737 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( output wire o, input wire i, input wire i2 ); sub #(.NEXIST(1), // Not found .P(2), .P(3)) // Dup sub (.o(o), .i(i), .i(i2), // Dup .nexist(i2) // Not found ); endmodule module sub #(parameter P=1, parameter EXIST=9) ( output wire o, input wire i, input wire exists ); assign o = ~i; endmodule verilator-5.042/test_regress/t/t_inst_tree_inl1_pub0.py0000755000542200017500000000235515101701376023640 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_inst_tree.v" out_filename = test.obj_dir + "/V" + test.name + ".tree.json" test.compile(v_flags2=[ "--no-json-edit-nums", "-fno-dfg-post-inline", "-fno-dfg-scoped", test.t_dir + "/t_inst_tree_inl1_pub0.vlt" ]) if test.vlt_all: test.file_grep( out_filename, r'{"type":"VAR","name":"t.u.u0.u0.z1",.*"loc":"\w,70:[^"]*",.*"origName":"z1",.*"dtypeName":"logic"' ) test.file_grep( out_filename, r'{"type":"VAR","name":"t.u.u0.u1.z1",.*"loc":"\w,70:[^"]*",.*"origName":"z1",.*"dtypeName":"logic"' ) test.file_grep( out_filename, r'{"type":"VAR","name":"t.u.u1.u0.z0",.*"loc":"\w,70:[^"]*",.*"origName":"z0",.*"dtypeName":"logic"' ) test.execute() test.file_grep(test.run_log_filename, r"\] (%m|.*t\.ps): Clocked") test.passes() verilator-5.042/test_regress/t/t_randomize_member_select.py0000755000542200017500000000104615101701376024645 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_implements_missing_bad.out0000644000542200017500000000074215101701376024661 0ustar mahmoudyfreeshell%Error: t/t_implements_missing_bad.v:12:1: Class 'Cls' implements 'Icls1' but is missing implementation for 'icf2' (IEEE 1800-2023 8.26) 12 | class Cls implements Icls1; | ^~~~~ t/t_implements_missing_bad.v:9:30: ... Location of interface class's function 9 | pure virtual function int icf2; | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_struct_packed_sysfunct.v0000644000542200017500000000312215101701376024367 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2009 by Iztok Jeras. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; // packed structures struct packed { logic e0; logic [1:0] e1; logic [3:0] e2; logic [7:0] e3; } struct_dsc; // descendng range structure /* verilator lint_off ASCRANGE */ struct packed { logic e0; logic [0:1] e1; logic [0:3] e2; logic [0:7] e3; } struct_asc; // ascending range structure /* verilator lint_on ASCRANGE */ integer cnt = 0; // event counter always @ (posedge clk) begin cnt <= cnt + 1; end // finish report always @ (posedge clk) if (cnt==2) begin $write("*-* All Finished *-*\n"); $finish; end always @ (posedge clk) if (cnt==1) begin // descending range if ($bits (struct_dsc ) != 15) $stop; if ($bits (struct_dsc.e0) != 1) $stop; if ($bits (struct_dsc.e1) != 2) $stop; if ($bits (struct_dsc.e2) != 4) $stop; if ($bits (struct_dsc.e3) != 8) $stop; if ($increment (struct_dsc, 1) != 1) $stop; // ascending range if ($bits (struct_asc ) != 15) $stop; if ($bits (struct_asc.e0) != 1) $stop; if ($bits (struct_asc.e1) != 2) $stop; if ($bits (struct_asc.e2) != 4) $stop; if ($bits (struct_asc.e3) != 8) $stop; if ($increment (struct_asc, 1) != 1) $stop; // Structure itself always big numbered end endmodule verilator-5.042/test_regress/t/t_interface_generic_modport2.py0000755000542200017500000000101315101701376025243 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(timing_loop=True, verilator_flags2=['--timing']) test.execute() test.passes() verilator-5.042/test_regress/t/t_wait_order.py0000755000542200017500000000107515101701376022130 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(expect_filename=test.golden_filename, verilator_flags2=['--binary'], fails=test.vlt_all) test.passes() verilator-5.042/test_regress/t/t_class_field_name.v0000644000542200017500000000066615101701376023060 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class Cls; int queue; endclass module t; initial begin Cls cls = new; cls.queue = 1; if (cls.queue == 1) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_timescale_lint2.py0000755000542200017500000000104515101701376023044 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.top_filename = "t/t_timescale_lint.v" test.lint(verilator_flags2=["--lint-only --timescale 1ns/1ns"]) test.passes() verilator-5.042/test_regress/t/t_mailbox_concurrent.v0000644000542200017500000000201515101701376023473 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Liam Braun. // SPDX-License-Identifier: CC0-1.0 module t(); mailbox #(int) m; task automatic test_get; int v; m.get(v); // Only one thread should be here at a time (mailbox empty) $display("mailbox read %0t", $time); #1; m.put(v); endtask task automatic test_put; int v; m.put(42); // Only one thread should be here at a time (mailbox full) $display("mailbox write %0t", $time); #1; m.get(v); endtask initial begin m = new(1); m.put(42); fork test_get(); test_get(); test_get(); join m = new(1); fork test_put(); test_put(); test_put(); join $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_langext_3_bad.out0000644000542200017500000000035015101701376022632 0ustar mahmoudyfreeshell%Error: t/t_langext_3.v:20:4: Can't find typedef/interface: 'uwire' 20 | uwire w; | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_func_outp.v0000644000542200017500000000352415101701376021606 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; reg [7:0] a,b; wire [7:0] z; mytop u0 ( a, b, clk, z ); integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; //$write("%d %x\n", cyc, z); if (cyc==1) begin a <= 8'h07; b <= 8'h20; end if (cyc==2) begin a <= 8'h8a; b <= 8'h12; end if (cyc==3) begin if (z !== 8'hdf) $stop; a <= 8'h71; b <= 8'hb2; end if (cyc==4) begin if (z !== 8'hed) $stop; end if (cyc==5) begin if (z !== 8'h4d) $stop; end if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule // mytop module inv( input [ 7:0 ] a, output wire [ 7:0 ] z ); assign z = ~a; endmodule module ftest( input [ 7:0 ] a, b, // Test legal syntax input clk, output reg [ 7:0 ] z ); wire [7:0] zi; inv u1 (.a(myadd(a,b)), .z(zi)); always @ ( posedge clk ) begin z <= myadd( a, zi ); end function [ 7:0 ] myadd; input [7:0] ina; input [7:0] inb; begin myadd = ina + inb; end endfunction // myadd endmodule // ftest module mytop ( input [ 7:0 ] a, b, input clk, output [ 7:0 ] z ); ftest u0( a, b, clk, z ); endmodule // mytop verilator-5.042/test_regress/t/t_opt_merge_cond.py0000755000542200017500000000154015101701376022752 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(verilator_flags2=["-unroll-count 64", "--stats"]) test.execute() if test.vlt: # Note, with vltmt this might be split differently, so only checking vlt test.file_grep(test.stats, r'Optimizations, MergeCond merges\s+(\d+)', 9) test.file_grep(test.stats, r'Optimizations, MergeCond merged items\s+(\d+)', 580) test.file_grep(test.stats, r'Optimizations, MergeCond longest merge\s+(\d+)', 128) test.passes() verilator-5.042/test_regress/t/t_randomize_unpacked_wide.v0000644000542200017500000000144415101701376024455 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Foo; rand bit [65:0] m_wideUnpacked[3]; constraint int_queue_c { m_wideUnpacked[0] == 0; m_wideUnpacked[1] == 1; m_wideUnpacked[2] == 2; } function void self_check(); if (m_wideUnpacked[0] != 0) $stop; if (m_wideUnpacked[1] != 1) $stop; if (m_wideUnpacked[2] != 2) $stop; endfunction endclass module t; int success; initial begin Foo foo = new; success = foo.randomize(); if (success != 1) $stop; foo.self_check(); $display("Unpacked: %p", foo.m_wideUnpacked); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_select_bad_range5.out0000644000542200017500000000375615101701376023503 0ustar mahmoudyfreeshell%Error: t/t_select_bad_range5.v:16:19: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' : ... note: In instance 't' 16 | assign mi = unk[3:2]; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Warning-SELRANGE: t/t_select_bad_range5.v:16:19: Extracting 2 bits from only 1 bit number : ... note: In instance 't' 16 | assign mi = unk[3:2]; | ^ ... For warning description see https://verilator.org/warn/SELRANGE?v=latest ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Warning-SELRANGE: t/t_select_bad_range5.v:16:19: Selection index out of range: 3:2 outside 1:0 : ... note: In instance 't' 16 | assign mi = unk[3:2]; | ^ %Warning-WIDTHEXPAND: t/t_select_bad_range5.v:16:19: Bit extraction of var[3:0] requires 2 bit index, not 1 bits. : ... note: In instance 't' 16 | assign mi = unk[3:2]; | ^ ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. %Warning-WIDTHTRUNC: t/t_select_bad_range5.v:16:14: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS's SEL generates 2 bits. : ... note: In instance 't' 16 | assign mi = unk[3:2]; | ^ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_debug_graph_test.py0000755000542200017500000000125415101701376023276 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') if 'VERILATOR_TEST_NO_GDB' in os.environ: test.skip("Skipping due to VERILATOR_TEST_NO_GDB") test.lint( # Check we can call dump() on graph, and other things v_flags=["--lint-only --debug --debugi-V3GraphTest 9 --debug-self-test"]) test.passes() verilator-5.042/test_regress/t/t_math_repl_bad.v0000644000542200017500000000062415101701376022363 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; logic [31:0] o; initial begin o = {0 {1'b1}}; // Bad 0 rep o = {$test$plusargs("NON-CONSTANT") {1'b1}}; // Bad non-constant rep $stop; end endmodule verilator-5.042/test_regress/t/t_timing_fork_nba.py0000755000542200017500000000075715101701376023127 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--exe --timing"]) test.passes() verilator-5.042/test_regress/t/t_struct_unpacked.py0000755000542200017500000000073415101701376023170 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_display_cwide_bad.py0000755000542200017500000000076315101701376023422 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_debug_width.py0000755000542200017500000000114015101701376022247 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_opt_const.v" test.lint(verilator_flags2=["--lint-only", "--debug-width"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_implements_nested_bad.v0000644000542200017500000000054415101701376024130 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls; interface class inte; interface class bad_cannot_nest; endclass endclass endclass module t; Cls c; endmodule verilator-5.042/test_regress/t/t_alias_tristate_unsup.out0000644000542200017500000000053615101701376024410 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_alias_tristate_unsup.v:17:9: Unsupported: Tristate variable referenced in alias: 'a' : ... note: In instance 't' 17 | alias a = b; | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_tri_struct_packed.py0000755000542200017500000000106115101701376023475 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--binary']) test.execute(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_initial_dlyass_bad.out0000644000542200017500000000133515101701376023762 0ustar mahmoudyfreeshell%Warning-INITIALDLY: t/t_initial_dlyass.v:18:9: Non-blocking assignment '<=' in initial/final block : ... This will be executed as a blocking assignment '='! 18 | a <= 22; | ^~ ... For warning description see https://verilator.org/warn/INITIALDLY?v=latest ... Use "/* verilator lint_off INITIALDLY */" and lint_on around source to disable this message. %Warning-INITIALDLY: t/t_initial_dlyass.v:19:9: Non-blocking assignment '<=' in initial/final block : ... This will be executed as a blocking assignment '='! 19 | b <= 33; | ^~ %Error: Exiting due to verilator-5.042/test_regress/t/t_constraint_pure_nonabs_bad.v0000644000542200017500000000050515101701376025165 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class NonAsbstract; pure constraint raintBad; // Bad: Not in abstract class endclass module t; endmodule verilator-5.042/test_regress/t/t_dpi_type_bad.py0000755000542200017500000000077615101701376022423 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_udp_bad_comb_trigger.v0000755000542200017500000000103515101701376023723 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 primitive t_gate(dout, a, b, c); output dout; input a, b, c; table x 0 1 : 1; 0 ? 1 : 1; (01) 1 0 : 0; 1 1 ? : 1; 1 0 0 : 0; 0 0 0 : 1; endtable endprimitive module top (o, a, b, c); output o; input a, b, c; t_gate(o, a, b, c); endmodule verilator-5.042/test_regress/t/t_udp_bad_first_input.v0000755000542200017500000000103215101701376023623 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 primitive t_gate(a, b, c, dout); input a, b, c; output dout; table x 0 1 : 1; 0 ? 1 : 1; 0 1 0 : 0; 1 1 ? : 1; 1 0 0 : 0; 0 0 0 : 1; endtable endprimitive module top (a, b, c, o); input a, b, c; output o; t_gate(a, b, c, o); endmodule verilator-5.042/test_regress/t/t_opt_dead_noassigns.v0000644000542200017500000000102315101701376023437 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs in ); input int in; int ass_keptdead; initial begin if (in != 0) begin ass_keptdead = 1 | in; $display("Avoid gate removing"); ass_keptdead = 2 | in; end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_gen_for0.py0000755000542200017500000000073415101701376021471 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_sys_fread.v0000644000542200017500000000671115101701376021564 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilog_format: off `define STRINGIFY(x) `"x`" `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); // verilog_format: on //====================================================================== module t; integer file; integer r_i; byte r_upb[20:10]; byte r_dnb[10:20]; reg [13:0] r_ups[20:10]; reg [13:0] r_dns[10:20]; reg [30:0] r_upi[20:10]; reg [30:0] r_dni[10:20]; reg [61:0] r_upq[20:10]; reg [61:0] r_dnq[10:20]; reg [71:0] r_upw[20:10]; reg [71:0] r_dnw[10:20]; task clear; // Initialize memories to zero, // avoid differences between 2-state and 4-state. r_i = ~0; foreach (r_upb[i]) r_upb[i] = ~0; foreach (r_dnb[i]) r_dnb[i] = ~0; foreach (r_ups[i]) r_ups[i] = ~0; foreach (r_dns[i]) r_dns[i] = ~0; foreach (r_upi[i]) r_upi[i] = ~0; foreach (r_dni[i]) r_dni[i] = ~0; foreach (r_upq[i]) r_upq[i] = ~0; foreach (r_dnq[i]) r_dnq[i] = ~0; foreach (r_upw[i]) r_upw[i] = ~0; foreach (r_dnw[i]) r_dnw[i] = ~0; // Open file $fclose(file); file = $fopen({`STRINGIFY(`TEST_OBJ_DIR), "/t_sys_fread.mem"}, "r"); if ($feof(file)) $stop; endtask task dump; // verilog_format: off $write("Dump:"); $write("\n r_i:"); $write(" %x",r_i); $write("\n r_upb:"); foreach (r_upb[i]) $write(" %x", r_upb[i]); $write("\n r_dnb:"); foreach (r_dnb[i]) $write(" %x", r_dnb[i]); $write("\n r_ups:"); foreach (r_ups[i]) $write(" %x", r_ups[i]); $write("\n r_dns:"); foreach (r_dns[i]) $write(" %x", r_dns[i]); $write("\n r_upi:"); foreach (r_upi[i]) $write(" %x", r_upi[i]); $write("\n r_dni:"); foreach (r_dni[i]) $write(" %x", r_dni[i]); $write("\n r_upq:"); foreach (r_upq[i]) $write(" %x", r_upq[i]); $write("\n r_dnq:"); foreach (r_dnq[i]) $write(" %x", r_dnq[i]); $write("\n r_upw:"); foreach (r_upw[i]) $write(" %x", r_upw[i]); $write("\n r_dnw:"); foreach (r_dnw[i]) $write(" %x", r_dnw[i]); $write("\n\n"); // verilog_format: on endtask integer code; initial begin // verilog_format: off clear; code = $fread(r_i, file); `checkd(code, 4); code = $fread(r_upb, file); `checkd(code, 11); code = $fread(r_dnb, file); `checkd(code, 11); code = $fread(r_ups, file); `checkd(code, 22); code = $fread(r_dns, file); `checkd(code, 22); code = $fread(r_upi, file); `checkd(code, 44); code = $fread(r_dni, file); `checkd(code, 44); code = $fread(r_upq, file); `checkd(code, 88); code = $fread(r_dnq, file); `checkd(code, 88); code = $fread(r_upw, file); `checkd(code, 99); code = $fread(r_dnw, file); `checkd(code, 99); dump; clear; code = $fread(r_upb, file, 15); `checkd(code, 6); code = $fread(r_dnb, file, 15); `checkd(code, 6); code = $fread(r_upb, file, , 1); `checkd(code, 1); code = $fread(r_dnb, file, , 1); `checkd(code, 1); code = $fread(r_upb, file, 13, 1); `checkd(code, 1); code = $fread(r_dnb, file, 13, 1); `checkd(code, 1); // verilog_format: on // Bug where fread in if() broke. if ($fread(r_ups, file, 15, 2) != 4) $stop; dump; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_flag_prefix.v0000644000542200017500000000210715101701376022066 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 module t; sub sub(); endmodule module sub; // no_inline_module, so it goes into separate file /* verilator no_inline_module */ // Goes into const pool which is separate file wire logic [255:0] C = {32'h1111_1111, 32'h2222_2222, 32'h3333_3333, 32'h4444_4444, 32'h5555_5555, 32'h6666_6666, 32'h7777_7777, 32'h8888_8888}; int i; initial begin // Note: Base index via $c to prevent optimization i = $c(0*32); $display("0x%32x", C[i+:32]); i = $c(1*32); $display("0x%32x", C[i+:32]); i = $c(2*32); $display("0x%32x", C[i+:32]); i = $c(3*32); $display("0x%32x", C[i+:32]); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_array_packed_write_read.py0000755000542200017500000000073415101701376024624 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_exprstmt_on_lhs_of_nba.v0000644000542200017500000000550115101701376024335 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Outputs data_o, // Inputs clk, rst_i, write_valid_i, write_front_i, read_valid_i, data_i ); localparam NR_ELEMENTS = 16; localparam DATAW = 32; input clk; input rst_i; input write_valid_i; input write_front_i; input read_valid_i; input [31:0] data_i; output [31:0] data_o; reg [31:0] FIFOContent [NR_ELEMENTS-1:0]; typedef logic [$clog2(NR_ELEMENTS)-1:0] FIFOPointer_t; // verilator lint_off WIDTH localparam FIFOPointer_t MAX_PTR_VAL = NR_ELEMENTS-1; // verilator lint_on WIDTH localparam FIFOPointer_t MIN_PTR_VAL = 0; localparam FIFOPointer_t PTR_INC = 1; FIFOPointer_t write_pointer; FIFOPointer_t read_pointer; function FIFOPointer_t nextPointer(input FIFOPointer_t val); if ($clog2(NR_ELEMENTS) == $clog2(NR_ELEMENTS+1) && val == MAX_PTR_VAL) nextPointer = MIN_PTR_VAL; // explicit wrap if NR_ELEMENTS is not a power of 2 else nextPointer = val + PTR_INC; endfunction function FIFOPointer_t prevPointer(input FIFOPointer_t val); if ($clog2(NR_ELEMENTS) == $clog2(NR_ELEMENTS+1) && val == MIN_PTR_VAL) prevPointer = MAX_PTR_VAL; // explicit wrap if NR_ELEMENTS is not a power of 2 else prevPointer = val - PTR_INC; endfunction reg [$clog2(NR_ELEMENTS)-1:0] level; reg is_empty; always @(posedge clk) begin if (write_valid_i) FIFOContent[write_front_i ? (read_valid_i ? read_pointer : prevPointer(read_pointer)) : write_pointer] <= data_i; end assign data_o = FIFOContent[read_pointer]; always @(posedge clk) begin if (rst_i) begin is_empty <= 1; end else if (write_valid_i) begin is_empty <= 0; end else if (read_valid_i && write_pointer == nextPointer(read_pointer)) begin is_empty <= 1; end end always @(posedge clk) begin if (rst_i) begin level <= 0; end else begin level <= level + (write_valid_i ? 1 : 0) - (read_valid_i ? 1 : 0); end end always @(posedge clk) begin if (rst_i) begin write_pointer <= 0; end else if (write_valid_i && !write_front_i) begin write_pointer <= nextPointer(write_pointer); end end always @(posedge clk) begin if (rst_i) begin read_pointer <= 0; end else if (read_valid_i) begin if (!(write_valid_i && write_front_i))read_pointer <= nextPointer(read_pointer); end else if (write_valid_i && write_front_i) begin read_pointer <= prevPointer(read_pointer); end end endmodule verilator-5.042/test_regress/t/t_vlprocess_missing.py0000755000542200017500000000437615101701376023551 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = test.obj_dir + "/t_vlprocess_missing.v" # Number of tests to generate NUM_TESTS = 200 # Testbench header template HEADER = """\ module Testbench; logic clk; logic reset; // Clock driver initial begin clk = 0; forever begin #5 clk = ~clk; end end task automatic advance_clock(int n = 1); repeat (n) @(posedge clk); endtask """ # Test task template TEST_TASK_TEMPLATE = """ task automatic test_{num}(); int counter = 0; int expected_value = {num}; // Timeout wait fork begin advance_clock(10000); $error("Timeout"); end join_none wait (counter == expected_value); disable fork; while (counter < expected_value) begin advance_clock(); counter++; end endtask """ # Testbench footer template FOOTER = " initial begin" # Call template for invoking each test task CALL_TEMPLATE = " test_{num}();\n" # Footer end FOOTER_END = """ $finish; end endmodule """ def gen(filename, num_tests): """ Generates a SystemVerilog testbench with the specified number of tests. Args: filename (str): The output file name for the generated testbench. num_tests (int): The number of test tasks to generate. """ with open(filename, 'w', encoding="utf-8") as fh: fh.write("// Generated by t_vlprocess_missing.py\n") # Write the header fh.write(HEADER) # Generate the test tasks for i in range(1, num_tests + 1): fh.write(TEST_TASK_TEMPLATE.format(num=i)) # Write the initial block with test calls fh.write(FOOTER) for i in range(1, num_tests + 1): fh.write(CALL_TEMPLATE.format(num=i)) fh.write(FOOTER_END) gen(test.top_filename, NUM_TESTS) test.compile(verilator_flags2=["--binary"]) test.passes() verilator-5.042/test_regress/t/t_inside_queue_elem.v0000644000542200017500000000064315101701376023264 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t; initial begin int q[$] = {1, 2}; if (!(1 inside {q[0], q[1]})) $stop; if (3 inside {q[0], q[1]}) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_order_dpi_export_3.cpp0000644000542200017500000000223015101701376023704 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2021 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include #include #include void toggle_other_clk(svBit val) { set_other_clk(val); } void toggle_third_clk(svBit val) { set_third_clk(val); } int main(int argc, char* argv[]) { VM_PREFIX* const tb = new VM_PREFIX; tb->contextp()->commandArgs(argc, argv); bool clk = true; while (!tb->contextp()->gotFinish()) { // Timeout if (tb->contextp()->time() > 100000) break; // Toggle and set main clock clk = !clk; tb->clk = clk; // Eval tb->eval(); // Advance time tb->contextp()->timeInc(500); } delete tb; return 0; } verilator-5.042/test_regress/t/t_mod_nomod.py0000755000542200017500000000071215101701376021741 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile() test.passes() verilator-5.042/test_regress/t/t_fork.out0000644000542200017500000000043715101701376021107 0ustar mahmoudyfreeshell%Error-NOTIMING: t/t_fork.v:10:7: Fork statements require --timing : ... note: In instance 't' 10 | fork : fblk | ^~~~ ... For error description see https://verilator.org/warn/NOTIMING?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_expr_incr_unsup.v0000644000542200017500000000066515101701376023032 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 Krzysztof Boronski. // SPDX-License-Identifier: CC0-1.0 int i = 0; function int postincrement_i; return i++; endfunction module t; initial begin int arr [1:0] = {0, 0}; i = 0; $display("Value: %d", arr[postincrement_i()]++); end endmodule verilator-5.042/test_regress/t/t_constraint_dist_randc_bad.out0000644000542200017500000000101515101701376025323 0ustar mahmoudyfreeshell%Error: t/t_constraint_dist_randc_bad.v:10:23: Randc variables not allowed in 'constraint dist' (IEEE 1800-2023 18.5.3) 10 | constraint c_bad { rc dist {3 := 0, 10 := 5}; } | ^~ t/t_constraint_dist_randc_bad.v:10:26: ... Location of restricting expression 10 | constraint c_bad { rc dist {3 := 0, 10 := 5}; } | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_struct_packed_init_bad.out0000644000542200017500000000057115101701376024631 0ustar mahmoudyfreeshell%Error: t/t_struct_packed_init_bad.v:12:17: Initial values not allowed in packed struct/union (IEEE 1800-2023 7.2.2) : ... note: In instance 't' 12 | bit [3:0] m_lo = P; | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_func_const_packed_struct_bad2.out0000644000542200017500000000233115101701376026105 0ustar mahmoudyfreeshell%Warning-USERFATAL: "f_add = 15" ... For warning description see https://verilator.org/warn/USERFATAL?v=latest ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. %Error: t/t_func_const_packed_struct_bad2.v:20:21: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2' : ... note: In instance 't' t/t_func_const_packed_struct_bad2.v:31:9: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing t/t_func_const_packed_struct_bad2.v:43:16: ... Called from 'f_add()' with parameters: params = [0 = '{a: 32'h7, foo: 6'hb, sub_params: '{b: 32'h37, bar: 8'h6f}}, 1 = '{a: 32'h3039, foo: 6'hc, sub_params: '{b: 32'h8, bar: 8'h70}}] t/t_func_const_packed_struct_bad2.v:20:21: ... Called from 'f_add2()' with parameters: a = ?32?h7 b = ?32?h8 c = ?32?h9 20 | localparam P24 = f_add2(7, 8, 9); | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_class_override_bad.v0000644000542200017500000001106115101701376023411 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Function names correspond to how the function is declared in the base class, // then the extend class, with letters: // Does-not-exist(x), Nothing(n), :initial(i), :extends(e), :final(f) class Base; // _X = non-existant // _n = None function int get_n; return 1; endfunction function int get_n_n; return 1; endfunction function int get_n_e; return 1; endfunction function int get_n_ef; return 1; endfunction function int get_n_i; return 1; endfunction function int get_n_if; return 1; endfunction function int get_n_f; return 1; endfunction // _e = :extends function :extends int get_e; return 1; endfunction // Bad // _ef = :extends :final function :extends :final int get_ef; return 1; endfunction // Bad // _i = :initial function :initial int get_i; return 1; endfunction function :initial int get_i_n; return 1; endfunction function :initial int get_i_e; return 1; endfunction function :initial int get_i_ef; return 1; endfunction function :initial int get_i_i; return 1; endfunction function :initial int get_i_if; return 1; endfunction function :initial int get_i_f; return 1; endfunction // _if = :initial :final function :initial :final int get_if; return 1; endfunction function :initial :final int get_if_n; return 1; endfunction function :initial :final int get_if_e; return 1; endfunction function :initial :final int get_if_ef; return 1; endfunction function :initial :final int get_if_i; return 1; endfunction function :initial :final int get_if_if; return 1; endfunction function :initial :final int get_if_f; return 1; endfunction // _f = :final function :final int get_f; return 1; endfunction function :final int get_f_n; return 1; endfunction function :final int get_f_e; return 1; endfunction function :final int get_f_ef; return 1; endfunction function :final int get_f_i; return 1; endfunction function :final int get_f_if; return 1; endfunction function :final int get_f_f; return 1; endfunction endclass class Cls extends Base; // _X = non-existant function int get_x_n; return 1; endfunction function :extends int get_x_e; return 1; endfunction // Bad function :extends :final int get_x_ef; return 1; endfunction // Bad function :initial int get_x_i; return 1; endfunction function :initial :final int get_x_if; return 1; endfunction function :final int get_x_f; return 1; endfunction // _n = None function int get_n_n; return 1; endfunction function :extends int get_n_e; return 1; endfunction function :extends :final int get_n_ef; return 1; endfunction function :initial int get_n_i; return 1; endfunction // Bad function :initial :final int get_n_if; return 1; endfunction // Bad function :final int get_n_f; return 1; endfunction // _e = :extends // _ef = :extends :final // _i = :initial function int get_i_n; return 1; endfunction function :extends int get_i_e; return 1; endfunction function :extends :final int get_i_ef; return 1; endfunction function :initial int get_i_i; return 1; endfunction // Bad function :initial :final int get_i_if; return 1; endfunction // Bad function :final int get_i_f; return 1; endfunction // _if = :initial :final function int get_if_n; return 1; endfunction // Bad function :extends int get_if_e; return 1; endfunction // Bad function :extends :final int get_if_ef; return 1; endfunction // Bad function :initial int get_if_i; return 1; endfunction // Bad function :initial :final int get_if_if; return 1; endfunction // Bad function :final int get_if_f; return 1; endfunction // Bad // _f = :final function int get_f_n; return 1; endfunction // Bad function :extends int get_f_e; return 1; endfunction // Bad function :extends :final int get_f_ef; return 1; endfunction // Bad function :initial int get_f_i; return 1; endfunction // Bad function :initial :final int get_f_if; return 1; endfunction // Bad function :final int get_f_f; return 1; endfunction // Bad endclass class CBase; endclass class CClsN extends CBase; endclass class :final CClsF extends CBase; endclass class :final CClsBadExtendsFinal extends CClsF; endclass module t; initial begin Cls c; CClsF cc; if (c != null) $stop; c = new; cc = new; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_select_loop.v0000644000542200017500000000275715101701376022123 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg [255:0] a; reg [255:0] q; reg [63:0] qq; integer i; always @* begin for (i=0; i<256; i=i+1) begin q[255-i] = a[i]; end q[27:16] = 12'hfed; for (i=0; i<64; i=i+1) begin qq[63-i] = a[i]; end qq[27:16] = 12'hfed; end always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; `ifdef TEST_VERBOSE $write("%x/%x %x\n", q, qq, a); `endif if (cyc==1) begin a = 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26; end if (cyc==2) begin a = 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8; if (q != 256'h64fe7e285bcf892eca128d426ed707a20eebc824d5d9127bacbc21362fed1cb7) $stop; if (qq != 64'h64fe7e285fed892e) $stop; end if (cyc==3) begin if (q != 256'h1da9cf939c0712504b5bdbbbbfbb6c47c316bd471362641958a7fabcffede870) $stop; if (qq != 64'h1da9cf939fed1250) $stop; end if (cyc==4) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.042/test_regress/t/t_interface_modportlist.py0000755000542200017500000000101515101701376024363 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_make_gmake=False, make_top_shell=False, make_main=False) test.passes() verilator-5.042/test_regress/t/t_class_new.v0000644000542200017500000000367715101701376021573 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class ClsNoArg; const int imembera; // Ok for new() to assign to a const function new(); int other = other_func(); imembera = 5; if (other != 6) $stop; endfunction : new class InnerNoArg; const int imembera; function new(); int other = other_func(); imembera = 5; if (other != 6) $stop; endfunction function int other_func(); return 6; endfunction endclass function int other_func(); return 6; endfunction endclass class ClsArg; int imembera; function new(int i); imembera = i + 1; endfunction function int geta; return imembera; endfunction static function ClsArg create6; ClsArg obj; obj = new(6 - 1); return obj; endfunction endclass class Cls2Arg; int imembera; int imemberb; function new(int i, int j); imembera = i + 1; imemberb = j + 2; endfunction function Cls2Arg clone(); Cls2Arg ret; ret = new(imembera, imemberb); return ret; endfunction endclass module t; initial begin ClsNoArg c1; ClsArg c2; Cls2Arg c3; Cls2Arg c4; ClsNoArg::InnerNoArg c5 = new; c1 = new; if (c1.imembera != 5) $stop; c2 = new(3 - 1); if (c2.imembera != 3) $stop; if (c2.geta() != 3) $stop; c2 = ClsArg::create6(); if (c2.imembera != 6) $stop; if (c2.geta() != 6) $stop; c3 = new(4, 5); if (c3.imembera != 5) $stop; if (c3.imemberb != 7) $stop; c4 = c3.clone(); if (c4.imembera != 6) $stop; if (c4.imemberb != 9) $stop; c5 = new; if (c5.imembera != 5) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_covergroup_unsup.py0000755000542200017500000000107115101701376023412 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert --error-limit 1000'], fails=True) test.passes() verilator-5.042/test_regress/t/t_display_real_noopt.py0000755000542200017500000000115715101701376023661 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_display_real.v" test.golden_filename = "t/t_display_real.out" test.compile(verilator_flags2=["-O0"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_clk_scope_bad.v0000644000542200017500000000133315101701376022350 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs out, // Inputs clk, in ); input clk; input [2:0] in; output [2:0] out; logic [2:0] r_in; always_ff @ (posedge clk) r_in <= in; flop p0 (.clk(clk), .d(r_in[0]), .q(out[0])); flop p2 (.clk(r_in[1]), .d(clk), .q(out[1])); flop p1 (.clk(clk), .d(r_in[2]), .q(out[2])); endmodule module flop ( input d, input clk, output logic q); // verilator no_inline_module always_ff @ (posedge clk) begin q <= d; end endmodule verilator-5.042/test_regress/t/t_timing_wait1.v0000644000542200017500000000374615101701376022206 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `ifdef TEST_VERBOSE `define WRITE_VERBOSE(msg) $write(msg) `else `define WRITE_VERBOSE(msg) `endif module t; int a = 0; int b = 0; int c = 0; int q[$]; initial begin `WRITE_VERBOSE("start with a==0, b==0, c==0\n"); #2 a = 1; `WRITE_VERBOSE("assign 1 to a\n"); #1 a = 2; `WRITE_VERBOSE("assign 2 to a\n"); // a==2 #1 a = 0; `WRITE_VERBOSE("assign 0 to a\n"); #1 a = 2; `WRITE_VERBOSE("assign 2 to a\n"); // 1a #1 c = 3; `WRITE_VERBOSE("assign 3 to c\n"); #1 c = 4; `WRITE_VERBOSE("assign 4 to c\n"); // a+bc b = 5; `WRITE_VERBOSE("push_back b to q\n"); q.push_back(b); end initial begin #1 `WRITE_VERBOSE("waiting for a==2\n"); wait(a == 2) if (a != 2) $stop; `WRITE_VERBOSE("waiting for a<2\n"); wait(a < 2) if (a >= 2) $stop; `WRITE_VERBOSE("waiting for a==0\n"); wait(a == 0) if (a != 0) $stop; `WRITE_VERBOSE("waiting for 1 1 && a < 3) if (a <= 1 || a >= 3) $stop; `WRITE_VERBOSE("waiting for b>a\n"); wait(b > a) if (b <= a) $stop; `WRITE_VERBOSE("waiting for a+b= c) $stop; `WRITE_VERBOSE("waiting for ac\n"); wait(a < b && b > c) if (a >= b || b <= c) $stop; `WRITE_VERBOSE("waiting for q.size() > 0\n"); wait(q.size() > 0) if (q.size() <= 0) $stop; wait(1); wait(0 < 1) $write("*-* All Finished *-*\n"); $finish; end initial wait(0) $stop; // Note this doesn't give WAITCONST initial wait(1 == 0) $stop; initial #12 $stop; // timeout endmodule verilator-5.042/test_regress/t/t_mailbox_array.v0000644000542200017500000000104715101701376022433 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls; localparam DWIDTH = 6; typedef int my_type_t [2**DWIDTH]; mailbox #(my_type_t) m_mbx; function new(); this.m_mbx = new(1); endfunction endclass module tb_top(); Cls c; initial begin c = new(); $display("%p", c); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_var_port2_bad.py0000755000542200017500000000076615101701376022523 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_typedef_param_class.v0000644000542200017500000000100415101701376023600 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Class1 #(type T); typedef T::Some_type2 Some_type1; endclass class Class2; typedef int Some_type2; endclass module t; initial begin int value0 = 7; Class1#(Class2)::Some_type1 value1 = value0; int value2 = value1; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_vpi_unimpl.cpp0000644000542200017500000001165215101701376022304 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "verilated.h" #include "verilated_vcd_c.h" #include "Vt_vpi_unimpl.h" #include "Vt_vpi_unimpl__Dpi.h" #include "svdpi.h" // No verilated_vpi.h, make sure can link without it #include extern "C" { #include } // These require the above. Comment prevents clang-format moving them #include "TestVpi.h" unsigned int callback_count = 0; //====================================================================== int _mon_check_unimpl(p_cb_data cb_data) { static TestVpiHandle cb, clk_h; vpiHandle handle; const char* cp = nullptr; if (cb_data) { // this is the callback s_vpi_error_info info; vpi_chk_error(&info); callback_count++; printf("%%Info: got pli message %s\n", info.message); } else { // setup and install static t_cb_data cb_data; clk_h = vpi_handle_by_name((PLI_BYTE8*)"t.clk", NULL); cb_data.reason = cbPLIError; cb_data.cb_rtn = _mon_check_unimpl; // this function cb = vpi_register_cb(&cb_data); CHECK_RESULT_NZ(cb); // now exercise unimplemented fns vpi_get_cb_info(cb, NULL); CHECK_RESULT(callback_count, 1); vpi_register_systf(NULL); vpi_get_systf_info(NULL, NULL); vpi_handle_multi(0, NULL, NULL); vpi_get64(0, NULL); vpi_get_delays(NULL, NULL); vpi_put_delays(NULL, NULL); vpi_get_time(NULL, NULL); vpi_mcd_name(0); vpi_compare_objects(NULL, NULL); vpi_get_data(0, NULL, 0); vpi_put_data(0, NULL, 0); vpi_get_userdata(NULL); vpi_put_userdata(NULL, NULL); vpi_handle_by_multi_index(NULL, 0, NULL); vpi_control(0); s_vpi_time time_s; time_s.type = 0; vpi_get_time(NULL, &time_s); handle = vpi_put_value(NULL, NULL, NULL, 0); CHECK_RESULT(handle, 0); handle = vpi_handle(0, NULL); CHECK_RESULT(handle, 0); vpi_iterate(0, NULL); handle = vpi_register_cb(NULL); CHECK_RESULT(handle, 0); s_cb_data cb_data_s; cb_data_s.reason = 0; // Bad handle = vpi_register_cb(&cb_data_s); CHECK_RESULT(handle, 0); (void)vpi_get_str(vpiRange, clk_h); // Bad type // Supported but illegal tests: // Various checks that guarded passing NULL handles handle = vpi_scan(NULL); CHECK_RESULT(handle, 0); (void)vpi_get(vpiType, NULL); (void)vpi_get(vpiDirection, NULL); (void)vpi_get(vpiVector, NULL); cp = vpi_get_str(vpiType, NULL); CHECK_RESULT_Z(cp); vpi_release_handle(NULL); printf("End of main test\n"); } return 0; // Ok } extern "C" int mon_check() { // Callback from initial block in monitor if (int status = _mon_check_unimpl(NULL)) return status; return 0; // Ok } //====================================================================== int main(int argc, char** argv) { const std::unique_ptr contextp{new VerilatedContext}; uint64_t sim_time = 1100; contextp->commandArgs(argc, argv); // contextp->debug(9); // We're going to be checking for these errors so don't crash out contextp->fatalOnVpiError(0); const std::unique_ptr topp{new VM_PREFIX{contextp.get(), // Note null name - we're flattening it out ""}}; #ifdef VERILATOR #ifdef TEST_VERBOSE contextp->scopesDump(); #endif #endif #if VM_TRACE contextp->traceEverOn(true); VL_PRINTF("Enabling waves...\n"); VerilatedVcdC* tfp = new VerilatedVcdC; topp->trace(tfp, 99); tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); #endif topp->eval(); topp->clk = 0; contextp->timeInc(10); while (contextp->time() < sim_time && !contextp->gotFinish()) { contextp->timeInc(1); topp->eval(); // VerilatedVpi::callValueCbs(); // Make sure can link without verilated_vpi.h included topp->clk = !topp->clk; // mon_do(); #if VM_TRACE if (tfp) tfp->dump(contextp->time()); #endif } if (!callback_count) vl_fatal(FILENM, __LINE__, "main", "%Error: never got callbacks"); if (!contextp->gotFinish()) { vl_fatal(FILENM, __LINE__, "main", "%Error: Timeout; never got a $finish"); } topp->final(); #if VM_TRACE if (tfp) tfp->close(); #endif return 0; } verilator-5.042/test_regress/t/t_force_input_assign_bad.out0000644000542200017500000000140315101701376024627 0ustar mahmoudyfreeshell%Error-ASSIGNIN: t/t_force_input_assign_bad.v:18:10: Assigning to input/const variable: 'i' : ... note: In instance 't' 18 | s1.i = 2; | ^ ... For error description see https://verilator.org/warn/ASSIGNIN?v=latest %Error-ASSIGNIN: t/t_force_input_assign_bad.v:21:10: Assigning to input/const variable: 'i' : ... note: In instance 't' 21 | s2.i = 2; | ^ %Error-ASSIGNIN: t/t_force_input_assign_bad.v:25:17: Assigning to input/const variable: 'i' : ... note: In instance 't' 25 | assign s3.i = 2; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_strength_strongest_non_tristate.v0000644000542200017500000000171315101701376026341 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t (clk1, clk2); input wire clk1; input wire clk2; wire (weak0, weak1) a = 0; assign (strong0, supply1) a = clk1; assign (pull0, pull1) a = 1; wire b; xor (strong0, strong1) (b, clk1, clk2); and (weak0, pull1) (b, clk1, clk2); wire [7:0] c; assign (supply0, strong1) c = clk1 ? '1 : '0; assign (weak0, supply1) c = '0; assign (weak0, pull1) c = 'z; always begin if (a === clk1 && b === clk1 ^ clk2 && c[0] === clk1) begin $write("*-* All Finished *-*\n"); $finish; end else begin $write("Error: a = %b, b = %b, c[0] = %b, ", a, b, c[0]); $write("expected: a = %b, b = %b, c[0] = %b\n", clk1, clk1 ^ clk2, clk1); $stop; end end endmodule verilator-5.042/test_regress/t/t_trace_depth.py0000755000542200017500000000116215101701376022250 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(v_flags2=["--trace-vcd --trace-depth 1"]) test.execute() test.file_grep(test.trace_filename, r'value_at_top') test.file_grep_not(test.trace_filename, r' value_in_sub') test.passes() verilator-5.042/test_regress/t/t_dpi_arg_input_unpack.py0000755000542200017500000000237515101701376024162 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if test.nc: # For NC, compile twice, first just to generate DPI headers test.compile(nc_flags2=[ "+ncdpiheader+" + test.obj_dir + "/dpi-exp.h", "+ncdpiimpheader+" + test.obj_dir + "/dpi-imp.h" ]) test.compile( v_flags2=["t/" + test.name + ".cpp"], # --no-decoration so .out file doesn't comment on source lines verilator_flags2=["-Wall -Wno-DECLFILENAME --no-decoration"], # NC: Gdd the obj_dir to the C include path nc_flags2=["+ncscargs+-I" + test.obj_dir], # ModelSim: Generate DPI header, add obj_dir to the C include path ms_flags2=["-dpiheader " + test.obj_dir + "/dpi.h", "-ccflags -I" + test.obj_dir]) if test.vlt_all: test.files_identical(test.obj_dir + "/" + test.vm_prefix + "__Dpi.h", "t/" + test.name + "__Dpi.out") test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_width_arraydecl.py0000755000542200017500000000070315101701376024161 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint() test.passes() verilator-5.042/test_regress/t/t_unroll_nested.v0000644000542200017500000000243115101701376022455 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `ifndef VERILATOR `define PRAGMA `elsif TEST_DISABLE `define PRAGMA /*verilator unroll_disable*/ `elsif TEST_FULL `define PRAGMA /*verilator unroll_full*/ `endif module t; int a, b; int pos; initial begin for (int exit_a = 0; exit_a < 2; ++exit_a) begin `PRAGMA for (int exit_b = 0; exit_b < 3; ++exit_b) begin `PRAGMA b = 0; $write("exit_a %0d %0d", exit_a, exit_b); for (a = 0; a < 3; ++a) begin : a_loop `PRAGMA $write(" A%0d", a * 10 + b); for (b = 0; b < 3; ++b) begin : b_loop `PRAGMA $write(" B%0d", a * 10 + b); if (exit_b == 1 && b == 1) disable b_loop; $write(" C%0d", a * 10 + b); if (exit_b == 2 && a == 1) disable a_loop; $write(" D%0d", a * 10 + b); end $write(" Y%0d", a * 10 + b); if (exit_a == 1 && a == 1) disable a_loop; $write(" Z%0d", a * 10 + b); end $display; end end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_var_dotted_dup_bad.py0000755000542200017500000000076315101701376023605 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_program.py0000755000542200017500000000073415101701376021441 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_xml_flat_vlvbound.v0000644000542200017500000000117015101701376023324 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module vlvbound_test ( input logic [15:0] i_a, input logic [15:0] i_b, output logic [6:0] o_a, output logic [6:0] o_b ); function automatic logic [6:0] foo(input logic [15:0] val); logic [6:0] ret; integer i; for (i=0 ; i < 7; i++) begin ret[i] = (val[i*2 +: 2] == 2'b00); end return ret; endfunction assign o_a = foo(i_a); assign o_b = foo(i_b); endmodule verilator-5.042/test_regress/t/t_func_purification.py0000755000542200017500000000073415101701376023501 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_pgo_threads_hier.py0000755000542200017500000000333115101701376023274 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vltmt') test.top_filename = "t/t_hier_block_perf.v" cycles = 100 test.sim_time = cycles * 10 + 1000 threads = 2 config_file = test.t_dir + "/" + test.name + ".vlt" flags = [config_file, "--hierarchical", "-Wno-UNOPTFLAT", "-DSIM_CYCLES=" + str(cycles)] test.compile(benchmarksim=1, v_flags2=["--prof-pgo"] + flags, threads=threads) test.execute(all_run_flags=[ "+verilator+prof+exec+start+0", " +verilator+prof+exec+file+/dev/null", " +verilator+prof+vlt+file+" + test.obj_dir + "/profile.vlt"]) # yapf:disable test.file_grep(test.obj_dir + "/profile.vlt", r'profile_data -model "VTest"') test.file_grep(test.obj_dir + "/profile.vlt", r'profile_data -model "VCheck"') test.file_grep(test.obj_dir + "/profile.vlt", r'profile_data -model "VCoreHier"') test.file_grep(test.obj_dir + "/profile.vlt", r'profile_data -model "V' + test.name + '"') # Check for cost rollovers test.file_grep_not(test.obj_dir + "/profile.vlt", r'.*cost 64\'d\d{18}.*') # Differentiate benchmarksim results test.name = test.name + "_optimized" test.compile( benchmarksim=1, # Intentionally no --prof-pgo here to make sure profile data can be read in # without it (that is: --prof-pgo has no effect on profile_data hash names) v_flags2=[test.obj_dir + "/profile.vlt"] + flags, threads=threads) test.execute() test.passes() verilator-5.042/test_regress/t/t_var_in_assign.v0000644000542200017500000000302715101701376022424 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; integer v; reg i; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire oa; // From a of a.v wire oz; // From z of z.v // End of automatics a a (.*); z z (.*); always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d i=%x oa=%x oz=%x\n", $time, cyc, i, oa, oz); `endif cyc <= cyc + 1; i <= cyc[0]; if (cyc==0) begin v = 3; if (v !== 3) $stop; if (assignin(v) !== 2) $stop; if (v !== 3) $stop; // Make sure V didn't get changed end else if (cyc<10) begin if (cyc==11 && oz!==1'b0) $stop; if (cyc==12 && oz!==1'b1) $stop; if (cyc==12 && oa!==1'b1) $stop; end else if (cyc<90) begin end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end function integer assignin(input integer i); i = 2; assignin = i; endfunction endmodule module a (input i, output oa); // verilator lint_off ASSIGNIN assign i = 1'b1; assign oa = i; endmodule module z (input i, output oz); assign oz = i; endmodule verilator-5.042/test_regress/t/t_param_store_bad.out0000644000542200017500000000051015101701376023260 0ustar mahmoudyfreeshell%Error: t/t_param_store_bad.v:12:31: Storing to parameter variable 'S' in a context that is determined only at runtime 12 | $value$plusargs("S=%s", S); | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_func_complex.v0000644000542200017500000000223715101701376022266 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(); typedef integer q_t[$]; function void queue_set(ref q_t q); `ifdef TEST_NOINLINE // verilator no_inline_task `endif q.push_back(42); if (q.size() != 1) $stop; endfunction function void queue_check_nref(q_t q); `ifdef TEST_NOINLINE // verilator no_inline_task `endif q[0] = 11; if (q[0] != 11) $stop; endfunction function void queue_check_ref(const ref q_t q); `ifdef TEST_NOINLINE // verilator no_inline_task `endif if (q[0] != 42) $stop; endfunction function q_t queue_ret(); `ifdef TEST_NOINLINE // verilator no_inline_task `endif queue_ret = '{101}; endfunction initial begin q_t iq; queue_set(iq); if (iq.size() != 1) $stop; queue_check_ref(iq); iq[0] = 44; queue_check_nref(iq); if (iq[0] != 44) $stop; iq = queue_ret(); if (iq[0] != 101) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_vpi_public_depth.v0000644000542200017500000000446615101701376023132 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2010 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifndef IVERILOG import "DPI-C" context function int mon_check(); `endif package somepackage; int someint; endpackage module t (/*AUTOARG*/ // Inputs clk ); `ifdef USE_DOLLAR_C32 `systemc_header extern "C" int mon_check(); `verilog `endif input clk; integer status; wire a, b, x; A \mod.a (/*AUTOINST*/ // Outputs .x (x), // Inputs .clk (clk), .a (a), .b (b)); // Test loop initial begin `ifdef IVERILOG status = $mon_check(); `elsif USE_DOLLAR_C32 status = $c32("mon_check()"); `else status = mon_check(); `endif if (status!=0) begin $write("%%Error: t_vpi_module.cpp:%0d: C Test failed\n", status); $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule : t module A(/*AUTOARG*/ // Outputs x, // Inputs clk, a, b ); // this comment should get ignored for public-ignore input clk /* verilator public_flat_rw */; input a, b; output x; wire y, c; B \mod_b$ (/*AUTOINST*/ // Outputs .y (y), // Inputs .b (b), .c (c)); C \mod\c$ (/*AUTOINST*/ // Outputs .x (x), // Inputs .clk (clk), .a (a), .y (y)); endmodule : A module B(/*AUTOARG*/ // Outputs y, // Inputs b, c ); input b, c; output reg y; always @(*) begin : myproc y = b ^ c; end endmodule module C(/*AUTOARG*/ // Outputs x, // Inputs clk, a, y ); input clk; input a, y; output reg x; always @(posedge clk) begin x <= a & y; end endmodule verilator-5.042/test_regress/t/t_flag_modprefix_bad.out0000644000542200017500000000030515101701376023734 0ustar mahmoudyfreeshell%Error: --mod-prefix argument must be a legal C++ identifier: 'bad/name' ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_inst_array.v0000644000542200017500000000270015101701376021752 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; parameter ONE = 1; wire [17:10] bitout; reg [7:0] allbits; reg [15:0] onebit; sub sub [7:0] (allbits, onebit, bitout); integer x; always @ (posedge clk) begin //$write("%x\n", bitout); if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin allbits <= 8'hac; onebit <= 16'hc01a; end if (cyc==2) begin if (bitout !== 8'h07) $stop; allbits <= 8'hca; onebit <= 16'h1f01; end if (cyc==3) begin if (bitout !== 8'h41) $stop; if (sub[0].bitout !== 1'b1) $stop; if (sub[1].bitout !== 1'b0) $stop; `ifndef verilator // Hacky array subscripting if (sub[ONE].bitout !== 1'b0) $stop; `endif $write("*-* All Finished *-*\n"); $finish; end end end endmodule `ifdef USE_INLINE `define INLINE_MODULE /*verilator inline_module*/ `else `define INLINE_MODULE /*verilator public_module*/ `endif module sub (input [7:0] allbits, input [1:0] onebit, output bitout); `INLINE_MODULE assign bitout = (^ onebit) ^ (^ allbits); endmodule verilator-5.042/test_regress/t/t_unpacked_to_queue.py0000755000542200017500000000073415101701376023472 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_altera_lpm_mult.py0000755000542200017500000000111115101701376023141 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) test.compile(verilator_flags2=["--top-module", module]) test.passes() verilator-5.042/test_regress/t/t_timing_sched.py0000755000542200017500000000077115101701376022430 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_hier_block_vlt.py0000755000542200017500000000321615101701376022756 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_hier_block.v" # stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. test.clean_objs() # CI environment offers 2 VCPUs, 2 thread setting causes the following warning. # %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. # So use 6 threads here though it's not optimal in performance, but ok. test.compile(v_flags2=['t/t_hier_block.cpp'], verilator_flags2=[ '--stats', '--hierarchical', '+define+SHOW_TIMESCALE', '+define+USE_VLT', 't/t_hier_block_vlt.vlt', '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"' ], threads=(6 if test.vltmt else 1)) test.execute() test.file_grep(test.obj_dir + "/Vsub0/sub0.sv", r'^\s+timeprecision\s+(\d+)ps;', 1) test.file_grep(test.obj_dir + "/Vsub0/sub0.sv", r'^module\s+(\S+)\s+', "sub0") test.file_grep(test.obj_dir + "/Vsub1/sub1.sv", r'^module\s+(\S+)\s+', "sub1") test.file_grep(test.obj_dir + "/Vsub2/sub2.sv", r'^module\s+(\S+)\s+', "sub2") test.file_grep(test.stats, r'HierBlock,\s+Hierarchical blocks\s+(\d+)', 14) test.file_grep(test.run_log_filename, r'MACRO:(\S+) is defined', "cplusplus") test.passes() verilator-5.042/test_regress/t/t_dpi_lib_c.cpp0000644000542200017500000001375115101701376022030 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2017 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "svdpi.h" #include #include #include // These require the above. Comment prevents clang-format moving them #include "TestCheck.h" //====================================================================== // clang-format off #if defined(VERILATOR) # include "Vt_dpi_lib__Dpi.h" #elif defined(VCS) # include "../vc_hdrs.h" #elif defined(NC) # define NEED_EXTERNS #else # error "Unknown simulator for DPI test" #endif // clang-format on #ifdef NEED_EXTERNS extern "C" { // If get ncsim: *F,NOFDPI: Function {foo} not found in default libdpi. // Then probably forgot to list a function here. extern int dpii_failure(); extern void dpii_check(); } #endif //====================================================================== int errors = 0; int dpii_failure() { return errors; } //====================================================================== void dpii_lib_bit_check() { svBitVecVal bv[3]; bv[0] = 0xa3a2a1a0; // 31..0 bv[1] = 0xa7a6a5a4; // 63..32 bv[2] = 0xabaaa9a8; // 95..64 TEST_CHECK_HEX_EQ((int)svGetBitselBit(bv, 32), 0); TEST_CHECK_HEX_EQ((int)svGetBitselBit(bv, 33), 0); TEST_CHECK_HEX_EQ((int)svGetBitselBit(bv, 34), 1); TEST_CHECK_HEX_EQ((int)svGetBitselBit(bv, 35), 0); TEST_CHECK_HEX_EQ((int)svGetBitselBit(bv, 36), 0); TEST_CHECK_HEX_EQ((int)svGetBitselBit(bv, 37), 1); TEST_CHECK_HEX_EQ((int)svGetBitselBit(bv, 38), 0); TEST_CHECK_HEX_EQ((int)svGetBitselBit(bv, 39), 1); svPutBitselBit(bv, 32, 1); svPutBitselBit(bv, 33, 0); svPutBitselBit(bv, 34, 1); svPutBitselBit(bv, 35, 1); TEST_CHECK_HEX_EQ(bv[0], 0xa3a2a1a0); TEST_CHECK_HEX_EQ(bv[1], 0xa7a6a5ad); TEST_CHECK_HEX_EQ(bv[2], 0xabaaa9a8); svBitVecVal btmp[2]; svGetPartselBit(btmp, bv, 40, 8); TEST_CHECK_HEX_EQ(btmp[0], 0xa5); svGetPartselBit(btmp, bv, 32, 32); TEST_CHECK_HEX_EQ(btmp[0], 0xa7a6a5ad); svGetPartselBit(btmp, bv, 48, 40); TEST_CHECK_HEX_EQ(btmp[0], 0xa9a8a7a6); TEST_CHECK_HEX_EQ(btmp[1], 0xaa); btmp[0] = 0xa5; svPutPartselBit(bv, btmp[0], 48, 8); TEST_CHECK_HEX_EQ(bv[0], 0xa3a2a1a0); TEST_CHECK_HEX_EQ(bv[1], 0xa7a5a5ad); TEST_CHECK_HEX_EQ(bv[2], 0xabaaa9a8); btmp[0] = 0x11223344; svPutPartselBit(bv, btmp[0], 32, 32); TEST_CHECK_HEX_EQ(bv[0], 0xa3a2a1a0); TEST_CHECK_HEX_EQ(bv[1], 0x11223344); TEST_CHECK_HEX_EQ(bv[2], 0xabaaa9a8); btmp[0] = 0x99887766; svPutPartselBit(bv, btmp[0], 24, 24); TEST_CHECK_HEX_EQ(bv[0], 0x66a2a1a0); TEST_CHECK_HEX_EQ(bv[1], 0x11228877); TEST_CHECK_HEX_EQ(bv[2], 0xabaaa9a8); } void dpii_lib_logic_check() { svLogicVecVal lv[3]; lv[0].aval = 0xb3b2b1b0; // 31..0 lv[1].aval = 0xb7b6b5b4; // 63..32 lv[2].aval = 0xbbbab9b8; // 95..64 lv[0].bval = 0xc3c2c1c0; // 31..0 lv[1].bval = 0xc7c6c5c4; // 63..32 lv[2].bval = 0xcbcac9c8; // 95..64 TEST_CHECK_HEX_EQ((int)svGetBitselLogic(lv, 32), 0); TEST_CHECK_HEX_EQ((int)svGetBitselLogic(lv, 33), 0); TEST_CHECK_HEX_EQ((int)svGetBitselLogic(lv, 34), 3); TEST_CHECK_HEX_EQ((int)svGetBitselLogic(lv, 35), 0); TEST_CHECK_HEX_EQ((int)svGetBitselLogic(lv, 36), 1); TEST_CHECK_HEX_EQ((int)svGetBitselLogic(lv, 37), 1); TEST_CHECK_HEX_EQ((int)svGetBitselLogic(lv, 38), 2); TEST_CHECK_HEX_EQ((int)svGetBitselLogic(lv, 39), 3); svPutBitselLogic(lv, 32, 1); svPutBitselLogic(lv, 33, 0); svPutBitselLogic(lv, 34, 1); svPutBitselLogic(lv, 35, 3); TEST_CHECK_HEX_EQ(lv[0].aval, 0xb3b2b1b0); TEST_CHECK_HEX_EQ(lv[1].aval, 0xb7b6b5bd); TEST_CHECK_HEX_EQ(lv[2].aval, 0xbbbab9b8); TEST_CHECK_HEX_EQ(lv[0].bval, 0xc3c2c1c0); TEST_CHECK_HEX_EQ(lv[1].bval, 0xc7c6c5c8); TEST_CHECK_HEX_EQ(lv[2].bval, 0xcbcac9c8); svLogicVecVal ltmp[2]; svGetPartselLogic(ltmp, lv, 40, 8); TEST_CHECK_HEX_EQ(ltmp[0].aval, 0xb5); TEST_CHECK_HEX_EQ(ltmp[0].bval, 0xc5); svGetPartselLogic(ltmp, lv, 32, 32); TEST_CHECK_HEX_EQ(ltmp[0].aval, 0xb7b6b5bd); TEST_CHECK_HEX_EQ(ltmp[0].bval, 0xc7c6c5c8); svGetPartselLogic(ltmp, lv, 48, 40); TEST_CHECK_HEX_EQ(ltmp[0].aval, 0xb9b8b7b6); TEST_CHECK_HEX_EQ(ltmp[0].bval, 0xc9c8c7c6); TEST_CHECK_HEX_EQ(ltmp[1].aval, 0xba); TEST_CHECK_HEX_EQ(ltmp[1].bval, 0xca); ltmp[0].aval = 0xb5; ltmp[0].bval = 0xc5; svPutPartselLogic(lv, ltmp[0], 48, 8); TEST_CHECK_HEX_EQ(lv[0].aval, 0xb3b2b1b0); TEST_CHECK_HEX_EQ(lv[1].aval, 0xb7b5b5bd); TEST_CHECK_HEX_EQ(lv[2].aval, 0xbbbab9b8); TEST_CHECK_HEX_EQ(lv[0].bval, 0xc3c2c1c0); TEST_CHECK_HEX_EQ(lv[1].bval, 0xc7c5c5c8); TEST_CHECK_HEX_EQ(lv[2].bval, 0xcbcac9c8); ltmp[0].aval = 0x11223344; ltmp[0].bval = 0x81828384; svPutPartselLogic(lv, ltmp[0], 32, 32); TEST_CHECK_HEX_EQ(lv[0].aval, 0xb3b2b1b0); TEST_CHECK_HEX_EQ(lv[1].aval, 0x11223344); TEST_CHECK_HEX_EQ(lv[2].aval, 0xbbbab9b8); TEST_CHECK_HEX_EQ(lv[0].bval, 0xc3c2c1c0); TEST_CHECK_HEX_EQ(lv[1].bval, 0x81828384); TEST_CHECK_HEX_EQ(lv[2].bval, 0xcbcac9c8); ltmp[0].aval = 0x99887766; ltmp[0].bval = 0x89888786; svPutPartselLogic(lv, ltmp[0], 24, 24); TEST_CHECK_HEX_EQ(lv[0].aval, 0x66b2b1b0); TEST_CHECK_HEX_EQ(lv[1].aval, 0x11228877); TEST_CHECK_HEX_EQ(lv[2].aval, 0xbbbab9b8); TEST_CHECK_HEX_EQ(lv[0].bval, 0x86c2c1c0); TEST_CHECK_HEX_EQ(lv[1].bval, 0x81828887); TEST_CHECK_HEX_EQ(lv[2].bval, 0xcbcac9c8); } //====================================================================== void dpii_check() { dpii_lib_bit_check(); dpii_lib_logic_check(); } verilator-5.042/test_regress/t/t_flag_f_bad_cmt.v0000644000542200017500000000150115101701376022464 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `include "t_flag_f_tsub_inc.v" module t; initial begin `ifndef GOT_DEF1 $write("%%Error: NO GOT_DEF1\n"); $stop; `endif `ifndef GOT_DEF2 $write("%%Error: NO GOT_DEF2\n"); $stop; `endif `ifndef GOT_DEF3 $write("%%Error: NO GOT_DEF3\n"); $stop; `endif `ifndef GOT_DEF4 $write("%%Error: NO GOT_DEF4\n"); $stop; `endif `ifndef GOT_DEF5 $write("%%Error: NO GOT_DEF5\n"); $stop; `endif `ifndef GOT_DEF6 $write("%%Error: NO GOT_DEF6\n"); $stop; `endif `ifdef NON_DEF $write("%%Error: NON_DEF\n"); $stop; `endif $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_dynarray_concat.py0000755000542200017500000000073415101701376023152 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_assert_question.v0000644000542200017500000000146515101701376023036 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2016 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs dout, // Inputs clk, sel, a, c ); input clk; input bit [3:0] sel; input bit [3:0] a; input bit c; output bit dout; localparam logic DC = 1'b?; always_ff @(posedge clk) begin unique casez(sel) 4'b0000: dout <= a[0]; 4'b001?: dout <= a[1]; {1'b0, 1'b1, 1'b?, 1'b?}: dout <= a[2]; {1'b1, 1'b?, 1'b?, DC}: dout <= a[3]; default: dout <= '0; endcase $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_class_copy2.v0000644000542200017500000000142415101701376022022 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); class Cls; bit x = 1; endclass module t; Cls obj1; Cls obj2; initial begin obj1 = new; `checkh(obj1.x, 1); obj1.x = 0; obj2 = new obj1; `checkh(obj2.x, 0); obj2.x = 1; `checkh(obj1.x, 0); `checkh(obj2.x, 1); obj2.x = 0; `checkh(obj2.x, 0); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_enum_public.v0000644000542200017500000000166715101701376022114 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package p3; typedef enum logic [2:0] { ZERO = 3'b0, ONE = 3'b1 } e3_t /*verilator public*/; typedef enum logic [2:0] { TWO = 3'd2, XES = 3'b?1? } has_x_t /*verilator public*/; endpackage package p62; typedef enum logic [62:0] { ZERO = '0, ALLONE = '1 } e62_t /*verilator public*/; endpackage package pw; typedef enum logic [99:0] { // Too wide for public WIDE = 100'h123} ewide_t /*verilator public*/; endpackage module t; enum integer { EI_A, EI_B, EI_C } m_state; initial begin m_state = EI_A; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_timing_fork_nba.v0000644000542200017500000000062115101701376022727 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg b = 0, c = 1; always @(posedge clk) begin fork b <= c; c <= b; join end endmodule verilator-5.042/test_regress/t/t_detectarray_1.py0000755000542200017500000000101315101701376022510 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["-Wno-UNOPTFLAT", "-fno-dfg"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_eofnewline.out0000644000542200017500000000017515101701376023326 0ustar mahmoudyfreeshell`line 1 "obj_vlt/t_lint_eofnewline/t_lint_eofnewline_bad.v" 1 `line 2 "obj_vlt/t_lint_eofnewline/t_lint_eofnewline_bad.v" 0 verilator-5.042/test_regress/t/t_timing_delay_callstack.v0000644000542200017500000000304315101701376024266 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; int counter = 0; // As Verilator doesn't support recursive calls, let's use macros to // generate tasks for a deep call stack `ifdef TEST_VERBOSE `define DEEP_STACK_DELAY_END(i) \ task delay``i; \ counter++; \ $write("[%0t] at depth %0d\n", $time, i); \ counter++; \ endtask `define DEEP_STACK_DELAY(i, j) \ task delay``i; \ $write("[%0t] entering depth %0d\n", $time, i); \ #1 delay``j; \ counter++; \ #1 $write("[%0t] leaving depth %0d\n", $time, i); \ counter++; \ endtask `else `define DEEP_STACK_DELAY_END(i) \ task delay``i; \ counter += 2; \ endtask `define DEEP_STACK_DELAY(i, j) \ task delay``i; \ #1 delay``j; \ counter++; \ #1; \ counter++; \ endtask `endif `DEEP_STACK_DELAY_END(10); `DEEP_STACK_DELAY(9, 10); `DEEP_STACK_DELAY(8, 9); `DEEP_STACK_DELAY(7, 8); `DEEP_STACK_DELAY(6, 7); `DEEP_STACK_DELAY(5, 6); `DEEP_STACK_DELAY(4, 5); `DEEP_STACK_DELAY(3, 4); `DEEP_STACK_DELAY(2, 3); `DEEP_STACK_DELAY(1, 2); initial begin delay1; if ($time != 9*2) $stop; if (counter != 10*2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_case_reducer.py0000755000542200017500000000073415101701376022416 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_wrapper_context__top1.dat.out0000644000542200017500000003470615101701376025251 0ustar mahmoudyfreeshell# SystemC::Coverage-3 C 'ft/t_wrapper_context.vl14n22ttogglepagev_toggle/topoclk:0->1htop1.top' 6 C 'ft/t_wrapper_context.vl14n22ttogglepagev_toggle/topoclk:1->0htop1.top' 5 C 'ft/t_wrapper_context.vl15n22ttogglepagev_toggle/toporst:0->1htop1.top' 1 C 'ft/t_wrapper_context.vl15n22ttogglepagev_toggle/toporst:1->0htop1.top' 1 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[0]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[0]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[10]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[10]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[11]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[11]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[12]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[12]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[13]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[13]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[14]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[14]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[15]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[15]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[16]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[16]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[17]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[17]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[18]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[18]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[19]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[19]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[1]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[1]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[20]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[20]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[21]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[21]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[22]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[22]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[23]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[23]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[24]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[24]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[25]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[25]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[26]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[26]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[27]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[27]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[28]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[28]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[29]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[29]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[2]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[2]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[30]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[30]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[31]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[31]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[3]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[3]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[4]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[4]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[5]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[5]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[6]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[6]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[7]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[7]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[8]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[8]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[9]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[9]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl17n22ttogglepagev_toggle/topostop:0->1htop1.top' 1 C 'ft/t_wrapper_context.vl17n22ttogglepagev_toggle/topostop:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[0]:0->1htop1.top' 3 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[0]:1->0htop1.top' 2 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[10]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[10]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[11]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[11]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[12]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[12]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[13]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[13]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[14]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[14]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[15]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[15]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[16]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[16]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[17]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[17]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[18]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[18]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[19]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[19]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[1]:0->1htop1.top' 1 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[1]:1->0htop1.top' 1 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[20]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[20]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[21]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[21]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[22]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[22]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[23]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[23]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[24]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[24]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[25]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[25]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[26]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[26]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[27]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[27]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[28]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[28]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[29]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[29]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[2]:0->1htop1.top' 1 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[2]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[30]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[30]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[31]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[31]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[3]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[3]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[4]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[4]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[5]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[5]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[6]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[6]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[7]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[7]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[8]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[8]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[9]:0->1htop1.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[9]:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl19n22ttogglepagev_toggle/topodone_o:0->1htop1.top' 1 C 'ft/t_wrapper_context.vl19n22ttogglepagev_toggle/topodone_o:1->0htop1.top' 0 C 'ft/t_wrapper_context.vl22n4tlinepagev_line/topoblockS22,25,29,31-33htop1.top' 1 C 'ft/t_wrapper_context.vl36n4tlinepagev_line/topoblockS36htop1.top' 6 C 'ft/t_wrapper_context.vl37n7tbranchpagev_branch/topoifS37-38htop1.top' 1 C 'ft/t_wrapper_context.vl37n8tbranchpagev_branch/topoelseS40htop1.top' 5 C 'ft/t_wrapper_context.vl42n4tlinepagev_line/topoblockS42-43htop1.top' 19 C 'ft/t_wrapper_context.vl44n7tbranchpagev_branch/topoifS44htop1.top' 19 C 'ft/t_wrapper_context.vl44n8tbranchpagev_branch/topoelseS50htop1.top' 0 C 'ft/t_wrapper_context.vl45n11tlinepagev_line/topoelsehtop1.top' 18 C 'ft/t_wrapper_context.vl45n27texprpagev_expr/topo((counter >= 32'sh5)==0) => 0htop1.top' 18 C 'ft/t_wrapper_context.vl45n27texprpagev_expr/topo((counter >= 32'sh5)==1 && stop==1) => 1htop1.top' 1 C 'ft/t_wrapper_context.vl45n27texprpagev_expr/topo(stop==0) => 0htop1.top' 0 C 'ft/t_wrapper_context.vl51n10tbranchpagev_branch/topoifS51-53htop1.top' 0 C 'ft/t_wrapper_context.vl51n11tbranchpagev_branch/topoelsehtop1.top' 0 verilator-5.042/test_regress/t/t_class_class.v0000644000542200017500000000170015101701376022070 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Note UVM internals do not require classes-in-classes package P; class Cls #(type STORE_T=string); STORE_T imembera; STORE_T imemberb; class SubCls; STORE_T smembera; STORE_T smemberb; // TODO put extern function here or in t_class_extern.v to check link endclass : SubCls SubCls sc; endclass : Cls endpackage : P module t; P::Cls#(int) c; initial begin c = new; c.imembera = 10; c.imemberb = 20; c.sc = new; c.sc.smembera = 30; c.sc.smemberb = 40; if (c.imembera != 10) $stop; if (c.imemberb != 20) $stop; if (c.sc.smembera != 30) $stop; if (c.sc.smemberb != 40) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_threads_crazy_context.py0000755000542200017500000000145515101701376024401 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_threads_crazy.v" test.compile(verilator_flags2=['--cc'], threads=(2 if test.vltmt else 1), context_threads=1024) test.execute() if test.vltmt: test.file_grep( test.run_log_filename, r'Process has \d+ hardware threads available, but simulation thread count set to 1024\. This will likely cause significant slowdown\.' ) test.passes() verilator-5.042/test_regress/t/t_class_static_method.py0000755000542200017500000000073415101701376024006 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_sys_sformat.py0000755000542200017500000000073415101701376022343 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_display_qqq.py0000755000542200017500000000077215101701376022323 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_force_readwrite_unsup.v0000644000542200017500000000124615101701376024201 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Cls; task take_ref(ref logic s); endtask endclass module t; logic a; logic b = 1; Cls cls = new; initial begin force a = b; cls.take_ref(a); cls.take_ref(b); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_wrapper_context__top0.dat.out0000644000542200017500000003471115101701376025244 0ustar mahmoudyfreeshell# SystemC::Coverage-3 C 'ft/t_wrapper_context.vl14n22ttogglepagev_toggle/topoclk:0->1htop0.top' 11 C 'ft/t_wrapper_context.vl14n22ttogglepagev_toggle/topoclk:1->0htop0.top' 10 C 'ft/t_wrapper_context.vl15n22ttogglepagev_toggle/toporst:0->1htop0.top' 1 C 'ft/t_wrapper_context.vl15n22ttogglepagev_toggle/toporst:1->0htop0.top' 1 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[0]:0->1htop0.top' 1 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[0]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[10]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[10]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[11]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[11]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[12]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[12]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[13]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[13]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[14]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[14]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[15]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[15]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[16]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[16]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[17]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[17]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[18]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[18]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[19]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[19]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[1]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[1]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[20]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[20]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[21]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[21]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[22]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[22]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[23]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[23]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[24]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[24]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[25]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[25]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[26]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[26]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[27]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[27]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[28]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[28]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[29]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[29]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[2]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[2]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[30]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[30]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[31]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[31]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[3]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[3]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[4]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[4]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[5]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[5]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[6]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[6]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[7]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[7]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[8]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[8]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[9]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[9]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl17n22ttogglepagev_toggle/topostop:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl17n22ttogglepagev_toggle/topostop:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[0]:0->1htop0.top' 5 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[0]:1->0htop0.top' 5 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[10]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[10]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[11]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[11]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[12]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[12]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[13]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[13]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[14]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[14]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[15]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[15]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[16]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[16]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[17]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[17]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[18]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[18]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[19]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[19]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[1]:0->1htop0.top' 3 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[1]:1->0htop0.top' 2 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[20]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[20]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[21]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[21]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[22]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[22]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[23]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[23]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[24]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[24]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[25]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[25]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[26]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[26]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[27]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[27]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[28]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[28]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[29]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[29]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[2]:0->1htop0.top' 1 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[2]:1->0htop0.top' 1 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[30]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[30]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[31]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[31]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[3]:0->1htop0.top' 1 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[3]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[4]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[4]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[5]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[5]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[6]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[6]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[7]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[7]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[8]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[8]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[9]:0->1htop0.top' 0 C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[9]:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl19n22ttogglepagev_toggle/topodone_o:0->1htop0.top' 1 C 'ft/t_wrapper_context.vl19n22ttogglepagev_toggle/topodone_o:1->0htop0.top' 0 C 'ft/t_wrapper_context.vl22n4tlinepagev_line/topoblockS22,25,29,31-33htop0.top' 1 C 'ft/t_wrapper_context.vl36n4tlinepagev_line/topoblockS36htop0.top' 11 C 'ft/t_wrapper_context.vl37n7tbranchpagev_branch/topoifS37-38htop0.top' 1 C 'ft/t_wrapper_context.vl37n8tbranchpagev_branch/topoelseS40htop0.top' 10 C 'ft/t_wrapper_context.vl42n4tlinepagev_line/topoblockS42-43htop0.top' 34 C 'ft/t_wrapper_context.vl44n7tbranchpagev_branch/topoifS44htop0.top' 0 C 'ft/t_wrapper_context.vl44n8tbranchpagev_branch/topoelseS50htop0.top' 34 C 'ft/t_wrapper_context.vl45n11tlinepagev_line/topoelsehtop0.top' 0 C 'ft/t_wrapper_context.vl45n27texprpagev_expr/topo((counter >= 32'sh5)==0) => 0htop0.top' 0 C 'ft/t_wrapper_context.vl45n27texprpagev_expr/topo((counter >= 32'sh5)==1 && stop==1) => 1htop0.top' 0 C 'ft/t_wrapper_context.vl45n27texprpagev_expr/topo(stop==0) => 0htop0.top' 0 C 'ft/t_wrapper_context.vl51n10tbranchpagev_branch/topoifS51-53htop0.top' 1 C 'ft/t_wrapper_context.vl51n11tbranchpagev_branch/topoelsehtop0.top' 33 verilator-5.042/test_regress/t/t_lint_iface_array_topmodule3.py0000755000542200017500000000070615101701376025437 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.042/test_regress/t/t_case_inside.v0000644000542200017500000000340715101701376022052 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc = 0; reg [63:0] crc; reg [63:0] sum; reg out1; reg [4:0] out2; sub sub (.in(crc[23:0]), .out1(out1), .out2(out2)); always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x sum=%x in[3:0]=%x out=%x,%x\n", $time, cyc, crc, sum, crc[3:0], out1,out2); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {58'h0,out1,out2}; if (cyc==0) begin // Setup crc <= 64'h00000000_00000097; sum <= 64'h0; end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); `define EXPECTED_SUM 64'h10204fa5567c8a4b if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module sub (/*AUTOARG*/ // Outputs out1, out2, // Inputs in ); input [23:0] in; output reg out1; output reg [4:0] out2; always @* begin case (in[3:0]) inside default {out1,out2} = {1'b0,5'h0F}; // Note not last item, no : to cover parser 4'h1, 4'h2, 4'h3: {out1,out2} = {1'b1,5'h01}; 4'h4: {out1,out2} = {1'b1,5'h04}; [4'h6:4'h5]: {out1,out2} = {1'b1,5'h05}; // order backwards, will not match 4'b100?:/*8,9*/ {out1,out2} = {1'b1,5'h08}; [4'hc:4'hf]: {out1,out2} = {1'b1,5'h0C}; endcase end endmodule verilator-5.042/test_regress/t/t_lint_modport_dir_bad.v0000644000542200017500000000154515101701376023763 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface dummy_if (); logic signal; modport slave (output signal); modport master (input signal); endinterface: dummy_if module sub ( input wire signal_i, output wire signal_o, dummy_if.master dummy_in, dummy_if.slave dummy_out ); assign dummy_in.signal = signal_i; assign signal_o = dummy_out.signal; endmodule module t (/*AUTOARG*/ // Outputs signal_o, // Inputs signal_i ); input signal_i; output signal_o; dummy_if dummy_if (); sub sub ( .signal_i(signal_i), .signal_o(signal_o), .dummy_in(dummy_if), .dummy_out(dummy_if) ); endmodule verilator-5.042/test_regress/t/t_lint_defparam_bad.py0000755000542200017500000000116215101701376023401 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_lint_defparam.v" test.lint(verilator_flags2=["--lint-only -Wwarn-style -Wno-DECLFILENAME"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface_ar2a.v0000644000542200017500000000077515101701376022456 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: SystemVerilog interface test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by Thierry Tambe. // SPDX-License-Identifier: CC0-1.0 module t (); ahb_slave_intf AHB_S[1](); AHB_MEM uMEM(.S(AHB_S[0].source)); // AHB_MEM V_MEM(.S(AHB_S[0])); endmodule module AHB_MEM ( ahb_slave_intf.source S ); endmodule interface ahb_slave_intf (); logic [31:0] HADDR; modport source (input HADDR); endinterface verilator-5.042/test_regress/t/t_timing_wait3.py0000755000542200017500000000077115101701376022371 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_class_extends_arg.py0000755000542200017500000000073415101701376023462 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_udp_param_bad.py0000755000542200017500000000076615101701376022555 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_sequence_first_match_unsup.out0000644000542200017500000000273515101701376025576 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_sequence_first_match_unsup.v:47:40: Unsupported: or (in sequence expression) 47 | initial p0: assert property ((##1 1) or (##2 1) |-> x==1); | ^~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_sequence_first_match_unsup.v:50:52: Unsupported: or (in sequence expression) 50 | initial p1: assert property (first_match((##1 1) or (##2 1)) |-> x==1); | ^~ %Error-UNSUPPORTED: t/t_sequence_first_match_unsup.v:50:32: Unsupported: first_match (in sequence expression) 50 | initial p1: assert property (first_match((##1 1) or (##2 1)) |-> x==1); | ^~~~~~~~~~~ %Error-UNSUPPORTED: t/t_sequence_first_match_unsup.v:53:34: Unsupported: or (in sequence expression) 53 | initial p2: assert property (1 or ##1 1 |-> x==0); | ^~ %Error-UNSUPPORTED: t/t_sequence_first_match_unsup.v:56:46: Unsupported: or (in sequence expression) 56 | initial p3: assert property (first_match(1 or ##1 1) |-> x==0); | ^~ %Error-UNSUPPORTED: t/t_sequence_first_match_unsup.v:56:32: Unsupported: first_match (in sequence expression) 56 | initial p3: assert property (first_match(1 or ##1 1) |-> x==0); | ^~~~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_gantt_io_arm.out0000644000542200017500000000266315101701376022614 0ustar mahmoudyfreeshellVerilator Gantt report Argument settings: +verilator+prof+exec+start+1 +verilator+prof+exec+window+2 Summary: Total elapsed time = 300000 rdtsc ticks Parallelized code = 80.49% of elapsed time Waiting time = 0.67% of elapsed time Total threads = 2 Total CPUs used = 2 Total mtasks = 5 Total yields = 51 NUMA assignment: NUMA status = 0,2;1,3 Parallelized code, measured: Thread utilization = 42.50% Speedup = 0.85x Parallelized code, predicted during static scheduling: Thread utilization = 82.44% Speedup = 1.65x All code, measured: Thread utilization = 43.96% Speedup = 0.879x All code, measured, scaled by predicted speedup: Thread utilization = 72.06% Speedup = 1.44x MTask statistics: Longest mtask id = 79 Longest mtask time = 57.05% of time elapsed in parallelized code min log(p2e) = -1.054 from mtask 79 (predict 48001, elapsed 137754) max log(p2e) = 3.641 from mtask 87 (predict 33809, elapsed 887) mean = 1.656 stddev = 2.104 e ^ stddev = 8.200 CPU info: Id | Time spent executing MTask | Socket | Core | Model | % of elapsed ticks / ticks | | | ====|============================|========|======|====== 2 | 67.44% / 202323 | | | Phytium,FT-2500/128 3 | 0.97% / 2914 | | | Phytium,FT-2500/128 Writing profile_exec.vcd verilator-5.042/test_regress/t/t_tri_gate_nmos_pins_inout.py0000755000542200017500000000140615101701376025070 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_tri_gate.cpp" test.top_filename = "t/t_tri_gate.v" test.compile(make_top_shell=False, make_main=False, v_flags2=['+define+T_NMOS'], make_flags=['CPPFLAGS_ADD=-DT_NMOS'], verilator_flags2=["--exe --pins-inout-enables", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_class_new_ref_bad.out0000644000542200017500000000150615101701376023564 0ustar mahmoudyfreeshell%Error: t/t_class_new_ref_bad.v:16:24: new() assignment not legal to non-class data type 'int' : ... note: In instance 't' 16 | txn_type_t txn = new; | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_class_new_ref_bad.v:17:25: new() cannot copy from non-class data type 'int' : ... note: In instance 't' 17 | txn_type_t copy = new txn; | ^~~ %Error: t/t_class_new_ref_bad.v:26:21: Assign RHS expects a CLASSREFDTYPE 'Base', got BASICDTYPE 'int' : ... note: In instance 't' 26 | Base b = Cls::generate_txn(); | ^~~~~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_display_wide_bad.out0000644000542200017500000000054515101701376023431 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_display_wide_bad.v:25:10: Unsupported: Exceeded limit of 8192 bits for any $display-like arguments 25 | $write("[%0t] cyc==%0d crc=%d\n", $time, cyc, {crc, crc, crc, crc}); | ^~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_pgo_profoutofdate_bad.out0000644000542200017500000000074715101701376024506 0ustar mahmoudyfreeshell%Warning-PROFOUTOFDATE: t/t_pgo_profoutofdate_bad.v:27:1: Profile data for mtasks may be out of date. 3 of 3 mtasks had no data 27 | profile_data -model "x" -mtask "h7baded98__0" -cost 64'd12345678901234567890 | ^~~~~~~~~~~~ ... For warning description see https://verilator.org/warn/PROFOUTOFDATE?v=latest ... Use "/* verilator lint_off PROFOUTOFDATE */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_tagged.out0000644000542200017500000000427015101701376021400 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_tagged.v:9:18: Unsupported: tagged union 9 | typedef union tagged { | ^~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_tagged.v:10:6: Unsupported: void (for tagged unions) 10 | void m_invalid; | ^~~~ %Error: t/t_tagged.v:19:14: syntax error, unexpected tagged, expecting IDENTIFIER-for-type 19 | u = tagged m_invalid; | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error-UNSUPPORTED: t/t_tagged.v:24:16: Unsupported: matches (for tagged union) 24 | case (u) matches | ^~~~~~~ %Error: t/t_tagged.v:29:9: syntax error, unexpected tagged, expecting IDENTIFIER-for-type 29 | tagged m_invalid: ; | ^~~~~~ %Error-UNSUPPORTED: t/t_tagged.v:34:34: Unsupported: '{} tagged patterns 34 | if (u matches tagged m_int .n) $stop; | ^ %Error-UNSUPPORTED: t/t_tagged.v:34:21: Unsupported: '{} tagged patterns 34 | if (u matches tagged m_int .n) $stop; | ^~~~~~ %Error-UNSUPPORTED: t/t_tagged.v:34:13: Unsupported: matches operator 34 | if (u matches tagged m_int .n) $stop; | ^~~~~~~ %Error: t/t_tagged.v:36:11: syntax error, unexpected tagged, expecting IDENTIFIER-for-type 36 | u = tagged m_int (123); | ^~~~~~ %Error: t/t_tagged.v:40:9: syntax error, unexpected tagged, expecting IDENTIFIER-for-type 40 | tagged m_invalid: $stop; | ^~~~~~ %Error-UNSUPPORTED: t/t_tagged.v:45:34: Unsupported: '{} tagged patterns 45 | if (u matches tagged m_int .n) if (n != 123) $stop; | ^ %Error-UNSUPPORTED: t/t_tagged.v:45:21: Unsupported: '{} tagged patterns 45 | if (u matches tagged m_int .n) if (n != 123) $stop; | ^~~~~~ %Error-UNSUPPORTED: t/t_tagged.v:45:13: Unsupported: matches operator 45 | if (u matches tagged m_int .n) if (n != 123) $stop; | ^~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_alias_cyclic_bad.out0000644000542200017500000000166415101701376023376 0ustar mahmoudyfreeshell%Error: t/t_alias_cyclic_bad.v:18:13: Alias is specified more than once (IEEE 1800-2023 10.11): 'a' : ... note: In instance 't' 18 | alias a = a; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_alias_cyclic_bad.v:19:9: Alias is specified more than once (IEEE 1800-2023 10.11): 'a' : ... note: In instance 't' 19 | alias a = b; | ^ %Error: t/t_alias_cyclic_bad.v:20:9: Alias is specified more than once (IEEE 1800-2023 10.11): 'b' : ... note: In instance 't' 20 | alias b = a; | ^ %Error: t/t_alias_cyclic_bad.v:20:13: Alias is specified more than once (IEEE 1800-2023 10.11): 'a' : ... note: In instance 't' 20 | alias b = a; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_disable_fork1.v0000644000542200017500000000200215101701376022277 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `define N 3 class Cls; task runforks(integer n); for (integer i = 0; i < n; i++) fork #1 $stop; join_none endtask endclass module t; Cls cls = new; initial begin // run forks for (integer i = 0; i < `N; i++) fork #1 $stop; join_none // run forks inside a method cls.runforks(`N); // run forks in forks for (integer i = 0; i < `N; i++) fork for (integer j = 0; j < `N; j++) fork #1 $stop; join_none join_none for (integer i = 0; i < `N; i++) fork cls.runforks(`N); join_none // kill them all disable fork; // check if we can still fork fork #2 $write("*-* All Finished *-*\n"); #3 $finish; join_none end endmodule verilator-5.042/test_regress/t/t_class2.py0000755000542200017500000000073415101701376021161 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_extends_colon.py0000755000542200017500000000101315101701376024012 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(make_flags=['VM_PARALLEL_BUILDS=1']) # bug2775) test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_dearray_bad.out0000644000542200017500000000346115101701376024423 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_interface_dearray_bad.v:23:9: Unexpected target of interface assignment ['IFACEREFDTYPE$[0:5]'] : ... note: In instance 'tb_top' 23 | a = f; | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_interface_dearray_bad.v:26:13: Array size mismatch in interface assignment : ... note: In instance 'tb_top' 26 | c.vif = b; | ^ %Error: t/t_interface_dearray_bad.v:31:23: Expecting expression to be constant, but variable isn't const: 'i' : ... note: In instance 'tb_top' 31 | d.vif[i] = a[i]; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error-UNSUPPORTED: t/t_interface_dearray_bad.v:31:23: Non-constant index in RHS interface array selection : ... note: In instance 'tb_top' 31 | d.vif[i] = a[i]; | ^ %Error-UNSUPPORTED: t/t_interface_dearray_bad.v:35:16: Interface slices unsupported : ... note: In instance 'tb_top' 35 | e.vif = b[0:5]; | ^ %Error: Internal Error: t/t_interface_dearray_bad.v:23:11: ../V3Broken.cpp:#: Broken link in node (or something without maybePointedTo): 'm_varp && !m_varp->brokeExists()' @ ./V3Ast__gen_impl.h:# : ... note: In instance 'tb_top' 23 | a = f; | ^ ... This fatal error may be caused by the earlier error(s); resolve those first. verilator-5.042/test_regress/t/t_disable_bad.out0000644000542200017500000000074215101701376022356 0ustar mahmoudyfreeshell%Error: t/t_disable_bad.v:9:15: Can't find definition of block/task: 'abcd' 9 | disable abcd; | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Internal Error: t/t_disable_bad.v:9:7: ../V3LinkJump.cpp:#: Unlinked disable statement 9 | disable abcd; | ^~~~~~~ ... This fatal error may be caused by the earlier error(s); resolve those first. verilator-5.042/test_regress/t/t_package_enum.py0000755000542200017500000000073415101701376022411 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_time_passed.py0000755000542200017500000000100015101701376022252 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_mailbox_bad.v0000644000542200017500000000061015101701376022036 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; mailbox #(int) m; initial begin m = new(4); if (m.bad_method() != 0) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_func_paramed.v0000644000542200017500000000363115101701376022227 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [11:0] in_a; reg [31:0] sel; wire [2:0] out_x; extractor #(4,3) extractor ( // Outputs .out (out_x), // Inputs .in (in_a), .sel (sel)); integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; //$write("%d %x %x %x\n", cyc, in_a, sel, out_x); if (cyc==1) begin in_a <= 12'b001_101_111_010; sel <= 32'd0; end if (cyc==2) begin sel <= 32'd1; if (out_x != 3'b010) $stop; end if (cyc==3) begin sel <= 32'd2; if (out_x != 3'b111) $stop; end if (cyc==4) begin sel <= 32'd3; if (out_x != 3'b101) $stop; end if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module extractor (/*AUTOARG*/ // Outputs out, // Inputs in, sel ); parameter IN_WIDTH=8; parameter OUT_WIDTH=2; input [IN_WIDTH*OUT_WIDTH-1:0] in; output [OUT_WIDTH-1:0] out; input [31:0] sel; wire [OUT_WIDTH-1:0] out = selector(in,sel); function [OUT_WIDTH-1:0] selector; input [IN_WIDTH*OUT_WIDTH-1:0] inv; input [31:0] selv; integer i; begin selector = 0; for (i=0; i>{4'hd}}); `checkh(bit_q[0], 1'b1); `checkh(bit_q[1], 1'b1); `checkh(bit_q[2], 1'b0); `checkh(bit_q[3], 1'b1); bit_q = bit_q_t'({<<{4'hc}}); `checkh(bit_q[0], 1'b0); `checkh(bit_q[1], 1'b0); `checkh(bit_q[2], 1'b1); `checkh(bit_q[3], 1'b1); bit_q = {>>{bit_q_t'(4'he)}}; `checkh(bit_q[0], 1'b1); `checkh(bit_q[1], 1'b1); `checkh(bit_q[2], 1'b1); `checkh(bit_q[3], 1'b0); bit_q = {<<{bit_q_t'(4'hd)}}; `checkh(bit_q[0], 1'b1); `checkh(bit_q[1], 1'b0); `checkh(bit_q[2], 1'b1); `checkh(bit_q[3], 1'b1); bit_qq = {>>{bit_q}}; `checkh(bit_qq[0], 1'b1); `checkh(bit_qq[1], 1'b0); `checkh(bit_qq[2], 1'b1); `checkh(bit_qq[3], 1'b1); bit_qq = {<<{bit_q}}; `checkh(bit_qq[0], 1'b1); `checkh(bit_qq[1], 1'b1); `checkh(bit_qq[2], 1'b0); `checkh(bit_qq[3], 1'b1); bit_q = bit_q_t'({>>{4'hd}}); `checkh(bit_q[0], 1'b1); `checkh(bit_q[1], 1'b1); `checkh(bit_q[2], 1'b0); `checkh(bit_q[3], 1'b1); bit_q = bit_q_t'({>>2{4'hd}}); `checkh(bit_q[0], 1'b1); `checkh(bit_q[1], 1'b1); `checkh(bit_q[2], 1'b0); `checkh(bit_q[3], 1'b1); bit_qq = bit_q_t'({>>{bit_q}}); `checkh(bit_qq[0], 1'b1); `checkh(bit_qq[1], 1'b1); `checkh(bit_qq[2], 1'b0); `checkh(bit_qq[3], 1'b1); bit_qq = bit_q_t'({>>2{bit_q}}); `checkh(bit_qq[0], 1'b1); `checkh(bit_qq[1], 1'b1); `checkh(bit_qq[2], 1'b0); `checkh(bit_qq[3], 1'b1); bit_qq = bit_q_t'({<<{bit_q}}); `checkh(bit_qq[0], 1'b1); `checkh(bit_qq[1], 1'b0); `checkh(bit_qq[2], 1'b1); `checkh(bit_qq[3], 1'b1); bit_qq = {<<2{bit_qq}}; `checkh(bit_qq[0], 1'b1); `checkh(bit_qq[1], 1'b1); `checkh(bit_qq[2], 1'b1); `checkh(bit_qq[3], 1'b0); bit_qq = {<<2{bit_q_t'({<<{bit_q}})}}; `checkh(bit_qq[0], 1'b1); `checkh(bit_qq[1], 1'b1); `checkh(bit_qq[2], 1'b1); `checkh(bit_qq[3], 1'b0); end begin cdata_q_t cdata_q, cdata_qq; cdata_q = cdata_q_t'(32'hdeadbeef); `checkh(cdata_q[0], 8'hde); `checkh(cdata_q[1], 8'had); `checkh(cdata_q[2], 8'hbe); `checkh(cdata_q[3], 8'hef); cdata_qq = cdata_q_t'({<<{cdata_q}}); `checkh(cdata_qq[0], 8'hf7); `checkh(cdata_qq[1], 8'h7d); `checkh(cdata_qq[2], 8'hb5); `checkh(cdata_qq[3], 8'h7b); cdata_qq = {<<2{cdata_q}}; `checkh(cdata_qq[0], 8'hfb); `checkh(cdata_qq[1], 8'hbe); `checkh(cdata_qq[2], 8'h7a); `checkh(cdata_qq[3], 8'hb7); end begin sdata_logic_q_t sdata_q, sdata_qq; sdata_q = sdata_logic_q_t'(64'hfeedface_deadbeef); `checkh(sdata_q[0], 16'hfeed); `checkh(sdata_q[1], 16'hface); `checkh(sdata_q[2], 16'hdead); `checkh(sdata_q[3], 16'hbeef); sdata_qq = sdata_logic_q_t'({<<{sdata_q}}); `checkh(sdata_qq[0], 16'hf77d); `checkh(sdata_qq[1], 16'hb57b); `checkh(sdata_qq[2], 16'h735f); `checkh(sdata_qq[3], 16'hb77f); sdata_qq = {<<2{sdata_q}}; `checkh(sdata_qq[0], 16'hfbbe); `checkh(sdata_qq[1], 16'h7ab7); `checkh(sdata_qq[2], 16'hb3af); `checkh(sdata_qq[3], 16'h7bbf); end begin idata_logic_q_t idata_q, idata_qq; idata_q = idata_logic_q_t'(64'h12345678_9abcdef0); `checkh(idata_q[0], 32'h12345678); `checkh(idata_q[1], 32'h9abcdef0); idata_qq = idata_logic_q_t'({<<{idata_q}}); `checkh(idata_qq[0], 32'h0f7b3d59); `checkh(idata_qq[1], 32'h1e6a2c48); idata_q = idata_logic_q_t'(128'hfeedface_deadbeef_cafebabe_12345678); `checkh(idata_q[0], 32'hfeedface); `checkh(idata_q[1], 32'hdeadbeef); `checkh(idata_q[2], 32'hcafebabe); `checkh(idata_q[3], 32'h12345678); idata_qq = {<<2{idata_logic_q_t'({<<{idata_q}})}}; `checkh(idata_qq[0], 32'hfddef5cd); `checkh(idata_qq[1], 32'hed5e7ddf); `checkh(idata_qq[2], 32'hc5fd757d); `checkh(idata_qq[3], 32'h2138a9b4); end begin qdata_logic_q_t qdata_q, qdata_qq; qdata_q.push_back(64'hdeadbeef_cafebabe); qdata_q.push_back(64'hfeedface_12345678); `checkh(qdata_q[0], 64'hdeadbeef_cafebabe); `checkh(qdata_q[1], 64'hfeedface_12345678); qdata_qq = qdata_logic_q_t'({<<{qdata_q}}); `checkh(qdata_qq[0], 64'h1e6a2c48735fb77f); `checkh(qdata_qq[1], 64'h7d5d7f53f77db57b); qdata_q.push_back(64'h1111222233334444); qdata_q.push_back(64'h5555666677778888); qdata_qq = {<<2{qdata_q}}; `checkh(qdata_qq[0], 64'h2222dddd99995555); `checkh(qdata_qq[1], 64'h1111cccc88884444); `checkh(qdata_qq[2], 64'h2d951c84b3af7bbf); `checkh(qdata_qq[3], 64'hbeaebfa3fbbe7ab7); end begin wide_q_t wide_q, wide_qq; wide_q.push_back(128'hdeadbeef_cafebabe_feedface_12345678); wide_q.push_back(128'h11112222_33334444_55556666_77778888); `checkh(wide_q[0], 128'hdeadbeef_cafebabe_feedface_12345678); `checkh(wide_q[1], 128'h11112222_33334444_55556666_77778888); wide_qq = wide_q_t'({<<{wide_q}}); `checkh(wide_qq[0], 128'h1111eeee6666aaaa2222cccc44448888); `checkh(wide_qq[1], 128'h1e6a2c48735fb77f7d5d7f53f77db57b); wide_q.push_back(128'haaaabbbb_ccccdddd_eeeeffff_00001111); wide_q.push_back(128'h22223333_44445555_66667777_88889999); wide_qq = wide_q_t'({<<{wide_q}}); wide_qq = {<<2{wide_q}}; `checkh(wide_qq[0], 128'h66662222dddd999955551111cccc8888); `checkh(wide_qq[1], 128'h44440000ffffbbbb77773333eeeeaaaa); `checkh(wide_qq[2], 128'h2222dddd999955551111cccc88884444); `checkh(wide_qq[3], 128'h2d951c84b3af7bbfbeaebfa3fbbe7ab7); end begin byte_q_t bytq_init; byte_q_t bytq; bit_q_t bitq; bytq_init.push_back(8'h84); bytq_init.push_back(8'haa); `checkh(bytq_init[0], 8'h84); `checkh(bytq_init[1], 8'haa); s = $sformatf("bytq_init=%p", bytq_init); `checks(s, "bytq_init='{'h84, 'haa}"); bytq = bytq_init; bitq = {<<8{bit_q_t'({<<{bytq}})}}; bytq = {<<8{bit_q_t'({<<{bitq}})}}; s = $sformatf("bitq=%p", bitq); `checks(s, "bitq='{'h0, 'h0, 'h1, 'h0, 'h0, 'h0, 'h0, 'h1, 'h0, 'h1, 'h0, 'h1, 'h0, 'h1, 'h0, 'h1}"); s = $sformatf("bytq=%p", bytq); `checks(s, "bytq='{'h84, 'haa}"); /* Generalized block-reversal semantics for the outer left-stream when blockSize > 1. This seemingly complicated approach is what is required to match commercial simulators, otherwise the straggler bit [1] in the padded byte might end up as 0x01 instead of 0x80. Starting with result of inner {<<{bitq}}: [1,1,0,1,0,1,0,1,0,1,0,0,0,0,1,0,0] (17 bits), apply outer {<<8{...}} using generalized block-reversal like this: - Reverse all bits: [0,0,1,0,0,0,0,1,0,1,0,1,0,1,0,1,1] - Split into 8-bit blocks from left and pad incomplete blocks on the left: - Block 0: [0,0,1,0,0,0,0,1] (complete) - Block 1: [0,1,0,1,0,1,0,1] (complete) - Block 2: [1] -> pad on left -> [0,0,0,0,0,0,0,1] - Reverse bits within each 8-bit block: - Block 0: [0,0,1,0,0,0,0,1] -> [1,0,0,0,0,1,0,0] = 0x84 - Block 1: [0,1,0,1,0,1,0,1] -> [1,0,1,0,1,0,1,0] = 0xaa - Block 2: [0,0,0,0,0,0,0,1] -> [1,0,0,0,0,0,0,0] = 0x80 */ bytq = bytq_init; bitq = {<<8{bit_q_t'({<<{bytq}})}}; bitq.push_back(1'b1); bytq = {<<8{bit_q_t'({<<{bitq}})}}; s = $sformatf("bitq=%p", bitq); `checks(s, "bitq='{'h0, 'h0, 'h1, 'h0, 'h0, 'h0, 'h0, 'h1, 'h0, 'h1, 'h0, 'h1, 'h0, 'h1, 'h0, 'h1, 'h1}"); `checkh(bytq[0], 8'h84); `checkh(bytq[1], 8'haa); `checkh(bytq[2], 8'h80); s = $sformatf("bytq=%p", bytq); `checks(s, "bytq='{'h84, 'haa, 'h80}"); bytq = bytq_init; bitq = {<<8{bit_q_t'({<<{bytq}})}}; bitq.push_back(1'b1); bitq.push_back(1'b1); bytq = {<<8{bit_q_t'({<<{bitq}})}}; s = $sformatf("bitq=%p", bitq); `checks(s, "bitq='{'h0, 'h0, 'h1, 'h0, 'h0, 'h0, 'h0, 'h1, 'h0, 'h1, 'h0, 'h1, 'h0, 'h1, 'h0, 'h1, 'h1, 'h1}"); s = $sformatf("bytq=%p", bytq); `checks(s, "bytq='{'h84, 'haa, 'hc0}"); bytq = bytq_init; bitq = {<<8{bit_q_t'({<<{bytq}})}}; bitq.push_back(1'b1); bitq.push_back(1'b1); bitq.push_back(1'b1); bytq = {<<8{bit_q_t'({<<{bitq}})}}; s = $sformatf("bytq=%p", bytq); `checks(s, "bytq='{'h84, 'haa, 'he0}"); bytq = bytq_init; bitq = {<<8{bit_q_t'({<<{bytq}})}}; bitq.push_back(1'b1); bitq.push_back(1'b1); bitq.push_back(1'b1); bitq.push_back(1'b0); bytq = {<<8{bit_q_t'({<<{bitq}})}}; s = $sformatf("bytq=%p", bytq); `checks(s, "bytq='{'h84, 'haa, 'h70}"); bytq = bytq_init; bitq = {<<8{bit_q_t'({<<{bytq}})}}; bitq.push_back(1'b1); bitq.push_back(1'b1); bitq.push_back(1'b1); bitq.push_back(1'b0); bitq.push_back(1'b1); bytq = {<<8{bit_q_t'({<<{bitq}})}}; s = $sformatf("bytq=%p", bytq); `checks(s, "bytq='{'h84, 'haa, 'hb8}"); bytq = bytq_init; bitq = {<<8{bit_q_t'({<<{bytq}})}}; bitq.push_back(1'b1); bitq.push_back(1'b1); bitq.push_back(1'b1); bitq.push_back(1'b0); bitq.push_back(1'b1); bitq.push_back(1'b0); bytq = {<<8{bit_q_t'({<<{bitq}})}}; s = $sformatf("bytq=%p", bytq); `checks(s, "bytq='{'h84, 'haa, 'h5c}"); bytq = bytq_init; bitq = {<<8{bit_q_t'({<<{bytq}})}}; bitq.push_back(1'b1); bitq.push_back(1'b1); bitq.push_back(1'b1); bitq.push_back(1'b0); bitq.push_back(1'b1); bitq.push_back(1'b0); bitq.push_back(1'b0); bytq = {<<8{bit_q_t'({<<{bitq}})}}; s = $sformatf("bytq=%p", bytq); `checks(s, "bytq='{'h84, 'haa, 'h2e}"); bytq = bytq_init; bitq = {<<8{bit_q_t'({<<{bytq}})}}; bitq.push_back(1'b1); bitq.push_back(1'b1); bitq.push_back(1'b1); bitq.push_back(1'b0); bitq.push_back(1'b1); bitq.push_back(1'b0); bitq.push_back(1'b0); bitq.push_back(1'b1); bytq = {<<8{bit_q_t'({<<{bitq}})}}; s = $sformatf("bytq=%p", bytq); `checks(s, "bytq='{'h84, 'haa, 'h97}"); bytq = bytq_init; bitq = {<<8{bit_q_t'({<<{bytq}})}}; bitq.push_back(1'b1); bitq.push_back(1'b1); bitq.push_back(1'b1); bitq.push_back(1'b0); bitq.push_back(1'b1); bitq.push_back(1'b0); bitq.push_back(1'b0); bitq.push_back(1'b1); bitq.push_back(1'b1); bytq = {<<8{bit_q_t'({<<{bitq}})}}; s = $sformatf("bytq=%p", bytq); `checks(s, "bytq='{'h84, 'haa, 'h97, 'h80}"); end // Test StreamR (>>) operations - fairly simple since this should maintain left-to-right order. begin bit_q_t bitq; byte_q_t bytq; bitq = {1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0}; bitq = {>>4{bit_q_t'({<<{bitq}})}}; s = $sformatf("bitq=%p", bitq); `checks(s, "bitq='{'h0, 'h1, 'h0, 'h1, 'h0, 'h1, 'h0, 'h1}"); bytq = {8'h84, 8'haa}; bitq = {>>{bit_q_t'({<<{bytq}})}}; s = $sformatf("bitq=%p", bitq); `checks(s, "bitq='{'h0, 'h1, 'h0, 'h1, 'h0, 'h1, 'h0, 'h1, 'h0, 'h0, 'h1, 'h0, 'h0, 'h0, 'h0, 'h1}"); bitq = { 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0 }; bytq = {>>2{byte_q_t'({<<{bitq}})}}; s = $sformatf("bytq=%p", bytq); `checks(s, "bytq='{'h43, 'h55}"); bytq = {8'h12, 8'h34, 8'h56}; bytq = {>>{byte_q_t'({<<{bytq}})}}; s = $sformatf("bytq=%p", bytq); `checks(s, "bytq='{'h6a, 'h2c, 'h48}"); bitq = {1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0}; bitq = {>>6{bit_q_t'({>>{bitq}})}}; s = $sformatf("bitq=%p", bitq); `checks(s, "bitq='{'h1, 'h0, 'h1, 'h0, 'h1, 'h0, 'h1, 'h0}"); bytq = {8'h84, 8'haa}; bitq = {>>{bit_q_t'({>>{bytq}})}}; s = $sformatf("bitq=%p", bitq); `checks(s, "bitq='{'h1, 'h0, 'h0, 'h0, 'h0, 'h1, 'h0, 'h0, 'h1, 'h0, 'h1, 'h0, 'h1, 'h0, 'h1, 'h0}"); bitq = { 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0 }; bytq = {>>8{byte_q_t'({>>{bitq}})}}; s = $sformatf("bytq=%p", bytq); `checks(s, "bytq='{'haa, 'hc2}"); bytq = {8'h12, 8'h34, 8'h56}; bytq = {>>{byte_q_t'({>>{bytq}})}}; s = $sformatf("bytq=%p", bytq); `checks(s, "bytq='{'h12, 'h34, 'h56}"); end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_param_type_bad.out0000644000542200017500000000042315101701376023110 0ustar mahmoudyfreeshell%Error: t/t_param_type_bad.v:9:27: syntax error, unexpected INTEGER NUMBER 9 | localparam type bad2 = 2; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_gen_for_overlap.py0000755000542200017500000000073415101701376023141 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_fst_cmake.out0000644000542200017500000002554515101701376023267 0ustar mahmoudyfreeshell$date Sat Apr 5 13:56:26 2025 $end $version fstWriter $end $timescale 1ps $end $scope module top $end $var wire 1 ! clk $end $var wire 5 " state [4:0] $end $scope module t $end $var wire 1 ! clk $end $var int 32 # cyc [31:0] $end $var logic 1 $ rstn $end $var wire 5 " state [4:0] $end $var real_parameter 64 % fst_gparam_real $end $var real_parameter 64 & fst_lparam_real $end $var real 64 % fst_real $end $var integer 32 ' fst_integer [31:0] $end $var bit 1 ( fst_bit $end $var logic 1 ) fst_logic $end $var int 32 * fst_int [31:0] $end $var shortint 16 + fst_shortint [15:0] $end $var longint 64 , fst_longint [63:0] $end $var byte 8 - fst_byte [7:0] $end $var parameter 32 . fst_parameter [31:0] $end $var parameter 32 / fst_lparam [31:0] $end $var supply0 1 0 fst_supply0 $end $var supply1 1 1 fst_supply1 $end $var tri0 1 0 fst_tri0 $end $var tri1 1 1 fst_tri1 $end $var tri 1 2 fst_tri $end $var wire 1 3 fst_wire $end $scope module test $end $var wire 1 ! clk $end $var wire 1 $ rstn $end $var wire 5 " state [4:0] $end $var logic 5 4 state_w [4:0] $end $var logic 5 5 state_array[0] [4:0] $end $var logic 5 6 state_array[1] [4:0] $end $var logic 5 7 state_array[2] [4:0] $end $scope module unnamedblk1 $end $var int 32 8 i [31:0] $end $upscope $end $scope module unnamedblk2 $end $var int 32 9 i [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b00000000000000000000000000000000 9 b00000000000000000000000000000000 8 b00000 7 b00000 6 b00000 5 b00000 4 03 02 11 00 b00000000000000000000000111001000 / b00000000000000000000000001111011 . b00000000 - b0000000000000000000000000000000000000000000000000000000000000000 , b0000000000000000 + b00000000000000000000000000000000 * 0) 0( b00000000000000000000000000000000 ' r4.56 & r1.23 % 0$ b00000000000000000000000000000000 # b00000 " 0! $end #10 1! b00001 " b00000000000000000000000000000001 # b10100 4 b00001 5 b00001 6 b00001 7 b00000000000000000000000000000011 8 #15 0! #20 1! b00000000000000000000000000000010 # #25 0! #30 1! b00000000000000000000000000000011 # #35 0! #40 1! b00000000000000000000000000000100 # #45 0! #50 1! b00000000000000000000000000000101 # #55 0! #60 1! b00000000000000000000000000000110 # #65 0! #70 1! b00000000000000000000000000000111 # #75 0! #80 1! b00000000000000000000000000001000 # #85 0! #90 1! b00000000000000000000000000001001 # #95 0! #100 1! b00000000000000000000000000001010 # #105 0! #110 1! b00000000000000000000000000001011 # 1$ #115 0! #120 1! b00000000000000000000000000001100 # b10100 7 b01010 4 b00000000000000000000000000000010 9 #125 0! #130 1! b00101 4 b01010 7 b00000000000000000000000000001101 # b10100 6 #135 0! #140 1! b01010 6 b00000000000000000000000000001110 # b00101 7 b10110 4 b10100 5 b10100 " #145 0! #150 1! b01010 " b01010 5 b01011 4 b10110 7 b00000000000000000000000000001111 # b00101 6 #155 0! #160 1! b10110 6 b00000000000000000000000000010000 # b01011 7 b10001 4 b00101 5 b00101 " #165 0! #170 1! b10110 " b10110 5 b11100 4 b10001 7 b00000000000000000000000000010001 # b01011 6 #175 0! #180 1! b10001 6 b00000000000000000000000000010010 # b11100 7 b01110 4 b01011 5 b01011 " #185 0! #190 1! b10001 " b10001 5 b00111 4 b01110 7 b00000000000000000000000000010011 # b11100 6 #195 0! #200 1! b01110 6 b00000000000000000000000000010100 # b00111 7 b10111 4 b11100 5 b11100 " #205 0! #210 1! b01110 " b01110 5 b11111 4 b10111 7 b00000000000000000000000000010101 # b00111 6 #215 0! #220 1! b10111 6 b00000000000000000000000000010110 # b11111 7 b11011 4 b00111 5 b00111 " #225 0! #230 1! b10111 " b10111 5 b11001 4 b11011 7 b00000000000000000000000000010111 # b11111 6 #235 0! #240 1! b11011 6 b00000000000000000000000000011000 # b11001 7 b11000 4 b11111 5 b11111 " #245 0! #250 1! b11011 " b11011 5 b01100 4 b11000 7 b00000000000000000000000000011001 # b11001 6 #255 0! #260 1! b11000 6 b00000000000000000000000000011010 # b01100 7 b00110 4 b11001 5 b11001 " #265 0! #270 1! b11000 " b11000 5 b00011 4 b00110 7 b00000000000000000000000000011011 # b01100 6 #275 0! #280 1! b00110 6 b00000000000000000000000000011100 # b00011 7 b10101 4 b01100 5 b01100 " #285 0! #290 1! b00110 " b00110 5 b11110 4 b10101 7 b00000000000000000000000000011101 # b00011 6 #295 0! #300 1! b10101 6 b00000000000000000000000000011110 # b11110 7 b01111 4 b00011 5 b00011 " #305 0! #310 1! b10101 " b10101 5 b10011 4 b01111 7 b00000000000000000000000000011111 # b11110 6 #315 0! #320 1! b01111 6 b00000000000000000000000000100000 # b10011 7 b11101 4 b11110 5 b11110 " #325 0! #330 1! b01111 " b01111 5 b11010 4 b11101 7 b00000000000000000000000000100001 # b10011 6 #335 0! #340 1! b11101 6 b00000000000000000000000000100010 # b11010 7 b01101 4 b10011 5 b10011 " #345 0! #350 1! b11101 " b11101 5 b10010 4 b01101 7 b00000000000000000000000000100011 # b11010 6 #355 0! #360 1! b01101 6 b00000000000000000000000000100100 # b10010 7 b01001 4 b11010 5 b11010 " #365 0! #370 1! b01101 " b01101 5 b10000 4 b01001 7 b00000000000000000000000000100101 # b10010 6 #375 0! #380 1! b01001 6 b00000000000000000000000000100110 # b10000 7 b01000 4 b10010 5 b10010 " #385 0! #390 1! b01001 " b01001 5 b00100 4 b01000 7 b00000000000000000000000000100111 # b10000 6 #395 0! #400 1! b01000 6 b00000000000000000000000000101000 # b00100 7 b00010 4 b10000 5 b10000 " #405 0! #410 1! b01000 " b01000 5 b00001 4 b00010 7 b00000000000000000000000000101001 # b00100 6 #415 0! #420 1! b00010 6 b00000000000000000000000000101010 # b00001 7 b10100 4 b00100 5 b00100 " #425 0! #430 1! b00010 " b00010 5 b01010 4 b10100 7 b00000000000000000000000000101011 # b00001 6 #435 0! #440 1! b10100 6 b00000000000000000000000000101100 # b01010 7 b00101 4 b00001 5 b00001 " #445 0! #450 1! b10100 " b10100 5 b10110 4 b00101 7 b00000000000000000000000000101101 # b01010 6 #455 0! #460 1! b00101 6 b00000000000000000000000000101110 # b10110 7 b01011 4 b01010 5 b01010 " #465 0! #470 1! b00101 " b00101 5 b10001 4 b01011 7 b00000000000000000000000000101111 # b10110 6 #475 0! #480 1! b01011 6 b00000000000000000000000000110000 # b10001 7 b11100 4 b10110 5 b10110 " #485 0! #490 1! b01011 " b01011 5 b01110 4 b11100 7 b00000000000000000000000000110001 # b10001 6 #495 0! #500 1! b11100 6 b00000000000000000000000000110010 # b01110 7 b00111 4 b10001 5 b10001 " #505 0! #510 1! b11100 " b11100 5 b10111 4 b00111 7 b00000000000000000000000000110011 # b01110 6 #515 0! #520 1! b00111 6 b00000000000000000000000000110100 # b10111 7 b11111 4 b01110 5 b01110 " #525 0! #530 1! b00111 " b00111 5 b11011 4 b11111 7 b00000000000000000000000000110101 # b10111 6 #535 0! #540 1! b11111 6 b00000000000000000000000000110110 # b11011 7 b11001 4 b10111 5 b10111 " #545 0! #550 1! b11111 " b11111 5 b11000 4 b11001 7 b00000000000000000000000000110111 # b11011 6 #555 0! #560 1! b11001 6 b00000000000000000000000000111000 # b11000 7 b01100 4 b11011 5 b11011 " #565 0! #570 1! b11001 " b11001 5 b00110 4 b01100 7 b00000000000000000000000000111001 # b11000 6 #575 0! #580 1! b01100 6 b00000000000000000000000000111010 # b00110 7 b00011 4 b11000 5 b11000 " #585 0! #590 1! b01100 " b01100 5 b10101 4 b00011 7 b00000000000000000000000000111011 # b00110 6 #595 0! #600 1! b00011 6 b00000000000000000000000000111100 # b10101 7 b11110 4 b00110 5 b00110 " #605 0! #610 1! b00011 " b00011 5 b01111 4 b11110 7 b00000000000000000000000000111101 # b10101 6 #615 0! #620 1! b11110 6 b00000000000000000000000000111110 # b01111 7 b10011 4 b10101 5 b10101 " #625 0! #630 1! b11110 " b11110 5 b11101 4 b10011 7 b00000000000000000000000000111111 # b01111 6 #635 0! #640 1! b10011 6 b00000000000000000000000001000000 # b11101 7 b11010 4 b01111 5 b01111 " #645 0! #650 1! b10011 " b10011 5 b01101 4 b11010 7 b00000000000000000000000001000001 # b11101 6 #655 0! #660 1! b11010 6 b00000000000000000000000001000010 # b01101 7 b10010 4 b11101 5 b11101 " #665 0! #670 1! b11010 " b11010 5 b01001 4 b10010 7 b00000000000000000000000001000011 # b01101 6 #675 0! #680 1! b10010 6 b00000000000000000000000001000100 # b01001 7 b10000 4 b01101 5 b01101 " #685 0! #690 1! b10010 " b10010 5 b01000 4 b10000 7 b00000000000000000000000001000101 # b01001 6 #695 0! #700 1! b10000 6 b00000000000000000000000001000110 # b01000 7 b00100 4 b01001 5 b01001 " #705 0! #710 1! b10000 " b10000 5 b00010 4 b00100 7 b00000000000000000000000001000111 # b01000 6 #715 0! #720 1! b00100 6 b00000000000000000000000001001000 # b00010 7 b00001 4 b01000 5 b01000 " #725 0! #730 1! b00100 " b00100 5 b10100 4 b00001 7 b00000000000000000000000001001001 # b00010 6 #735 0! #740 1! b00001 6 b00000000000000000000000001001010 # b10100 7 b01010 4 b00010 5 b00010 " #745 0! #750 1! b00001 " b00001 5 b00101 4 b01010 7 b00000000000000000000000001001011 # b10100 6 #755 0! #760 1! b01010 6 b00000000000000000000000001001100 # b00101 7 b10110 4 b10100 5 b10100 " #765 0! #770 1! b01010 " b01010 5 b01011 4 b10110 7 b00000000000000000000000001001101 # b00101 6 #775 0! #780 1! b10110 6 b00000000000000000000000001001110 # b01011 7 b10001 4 b00101 5 b00101 " #785 0! #790 1! b10110 " b10110 5 b11100 4 b10001 7 b00000000000000000000000001001111 # b01011 6 #795 0! #800 1! b10001 6 b00000000000000000000000001010000 # b11100 7 b01110 4 b01011 5 b01011 " #805 0! #810 1! b10001 " b10001 5 b00111 4 b01110 7 b00000000000000000000000001010001 # b11100 6 #815 0! #820 1! b01110 6 b00000000000000000000000001010010 # b00111 7 b10111 4 b11100 5 b11100 " #825 0! #830 1! b01110 " b01110 5 b11111 4 b10111 7 b00000000000000000000000001010011 # b00111 6 #835 0! #840 1! b10111 6 b00000000000000000000000001010100 # b11111 7 b11011 4 b00111 5 b00111 " #845 0! #850 1! b10111 " b10111 5 b11001 4 b11011 7 b00000000000000000000000001010101 # b11111 6 #855 0! #860 1! b11011 6 b00000000000000000000000001010110 # b11001 7 b11000 4 b11111 5 b11111 " #865 0! #870 1! b11011 " b11011 5 b01100 4 b11000 7 b00000000000000000000000001010111 # b11001 6 #875 0! #880 1! b11000 6 b00000000000000000000000001011000 # b01100 7 b00110 4 b11001 5 b11001 " #885 0! #890 1! b11000 " b11000 5 b00011 4 b00110 7 b00000000000000000000000001011001 # b01100 6 #895 0! #900 1! b00110 6 b00000000000000000000000001011010 # b00011 7 b10101 4 b01100 5 b01100 " #905 0! #910 1! b00110 " b00110 5 b11110 4 b10101 7 b00000000000000000000000001011011 # b00011 6 #915 0! #920 1! b10101 6 b00000000000000000000000001011100 # b11110 7 b01111 4 b00011 5 b00011 " #925 0! #930 1! b10101 " b10101 5 b10011 4 b01111 7 b00000000000000000000000001011101 # b11110 6 #935 0! #940 1! b01111 6 b00000000000000000000000001011110 # b10011 7 b11101 4 b11110 5 b11110 " #945 0! #950 1! b01111 " b01111 5 b11010 4 b11101 7 b00000000000000000000000001011111 # b10011 6 #955 0! #960 1! b11101 6 b00000000000000000000000001100000 # b11010 7 b01101 4 b10011 5 b10011 " #965 0! #970 1! b11101 " b11101 5 b10010 4 b01101 7 b00000000000000000000000001100001 # b11010 6 #975 0! #980 1! b01101 6 b00000000000000000000000001100010 # b10010 7 b01001 4 b11010 5 b11010 " #985 0! #990 1! b01101 " b01101 5 b10000 4 b01001 7 b00000000000000000000000001100011 # b10010 6 #995 0! #1000 1! b01001 6 b00000000000000000000000001100100 # b10000 7 b01000 4 b10010 5 b10010 " verilator-5.042/test_regress/t/t_select_sideeffect.py0000755000542200017500000000073415101701376023432 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_assert_ctl_immediate.out0000644000542200017500000000105615101701376024325 0ustar mahmoudyfreeshell[0] %Error: t_assert_ctl_immediate.v:47: Assertion failed in top.t.module_with_assertctl: 'assert' failed. -Info: t/t_assert_ctl_immediate.v:47: Verilog $stop, ignored due to +verilator+error+limit [0] %Error: t_assert_ctl_immediate.v:53: Assertion failed in top.t.module_with_assertctl: 'assert' failed. [0] %Error: t_assert_ctl_immediate.v:41: Assertion failed in top.t.module_with_assertctl.f_assert: 'assert' failed. [0] %Error: t_assert_ctl_immediate.v:41: Assertion failed in top.t.module_with_assertctl.f_assert: 'assert' failed. *-* All Finished *-* verilator-5.042/test_regress/t/t_fuzz_eqne_bad.v0000644000542200017500000000045715101701376022422 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 //bug1587 module t; reg a[0]; reg b; reg c; initial c = (a != &b); endmodule verilator-5.042/test_regress/t/t_tagged.py0000755000542200017500000000100415101701376021214 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_fuzz_always_bad.out0000644000542200017500000000063615101701376023333 0ustar mahmoudyfreeshell%Error: t/t_fuzz_always_bad.v:10:15: Can't find definition of 'a' in dotted variable/method: 'c.a' 10 | always @ c.a c:h; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_fuzz_always_bad.v:10:19: Can't find definition of task/function: 'h' 10 | always @ c.a c:h; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_math_repl.v0000644000542200017500000000702515101701376021557 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg [63:0] rf; reg [63:0] rf2; reg [63:0] biu; reg b; always @* begin rf[63:32] = biu[63:32] & {32{b}}; rf[31:0] = {32{b}}; rf2 = rf; rf2[31:0] = ~{32{b}}; end reg [31:0] src1, src0, sr, mask; wire [31:0] dualasr = ((| src1[31:4]) ? {{16{src0[31]}}, {16{src0[15]}}} : ( ( sr & {2{mask[31:16]}}) | ( {{16{src0[31]}}, {16{src0[15]}}} & {2{~mask[31:16]}}))); wire [31:0] sl_mask = (32'hffffffff << src1[4:0]); wire [31:0] sr_mask = {sl_mask[0], sl_mask[1], sl_mask[2], sl_mask[3], sl_mask[4], sl_mask[5], sl_mask[6], sl_mask[7], sl_mask[8], sl_mask[9], sl_mask[10], sl_mask[11], sl_mask[12], sl_mask[13], sl_mask[14], sl_mask[15], sl_mask[16], sl_mask[17], sl_mask[18], sl_mask[19], sl_mask[20], sl_mask[21], sl_mask[22], sl_mask[23], sl_mask[24], sl_mask[25], sl_mask[26], sl_mask[27], sl_mask[28], sl_mask[29], sl_mask[30], sl_mask[31]}; wire [95:0] widerep = {2{({2{({2{ {b,b}, {b,{2{b}}}, {{2{b}},b}, {2{({2{b}})}} }})}})}}; wire [1:0] w = {2{b}}; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; `ifdef TEST_VERBOSE $write("cyc=%0d d=%x %x %x %x %x %x %x\n", cyc, b, rf, rf2, dualasr, sl_mask, sr_mask, widerep); `endif if (cyc==1) begin biu <= 64'h12451282_abadee00; b <= 1'b0; src1 <= 32'h00000001; src0 <= 32'h9a4f1235; sr <= 32'h0f19f567; mask <= 32'h7af07ab4; end if (cyc==2) begin biu <= 64'h12453382_abad8801; b <= 1'b1; if (rf != 64'h0) $stop; if (rf2 != 64'h00000000ffffffff) $stop; src1 <= 32'h0010000f; src0 <= 32'h028aa336; sr <= 32'h42ad0377; mask <= 32'h1ab3b906; if (dualasr != 32'h8f1f7060) $stop; if (sl_mask != 32'hfffffffe) $stop; if (sr_mask != 32'h7fffffff) $stop; if (widerep != '0) $stop; end if (cyc==3) begin biu <= 64'h12422382_77ad8802; b <= 1'b1; if (rf != 64'h12453382ffffffff) $stop; if (rf2 != 64'h1245338200000000) $stop; src1 <= 32'h0000000f; src0 <= 32'h5c158f71; sr <= 32'h7076c40a; mask <= 32'h33eb3d44; if (dualasr != 32'h0000ffff) $stop; if (sl_mask != 32'hffff8000) $stop; if (sr_mask != 32'h0001ffff) $stop; if (widerep != '1) $stop; end if (cyc==4) begin if (rf != 64'h12422382ffffffff) $stop; if (rf2 != 64'h1242238200000000) $stop; if (dualasr != 32'h3062cc1e) $stop; if (sl_mask != 32'hffff8000) $stop; if (sr_mask != 32'h0001ffff) $stop; $write("*-* All Finished *-*\n"); if (widerep != '1) $stop; $finish; end end end endmodule verilator-5.042/test_regress/t/t_lint_assigneqexpr.v0000644000542200017500000000137615101701376023346 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( input logic a2_i, a1_i, a0_i, input logic b_i, output logic d_o ); // verilator lint_off PINMISSING Sub sub (.a_i({a2_i, a1_i, a0_i}), .b_i, .d_o); // verilator lint_on PINMISSING endmodule module Sub ( input logic [2:0] a_i, input logic b_i, output logic c_o, output logic d_o ); assign c_o = (a_i != 0) ? 1 : 0; assign d_o = // Note = not == below ( c_o = 1 // <--- Warning: ASSIGNEQEXPR ) ? 1 : ( c_o = 0 // <--- Warning: ASSIGNEQEXPR ) ? b_i : 0; endmodule verilator-5.042/test_regress/t/t_foreach_type_bad.v0000644000542200017500000000077215101701376023064 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls; endclass module t; real r; bit b[2]; Cls c; initial begin foreach (c[i]); // bad type foreach (r[i]); // no loop var foreach (b[i, j, k]); // extra loop var foreach (r[, i]); // no loop var and extra $stop; end endmodule verilator-5.042/test_regress/t/t_assert_ctl_type_bad.v0000755000542200017500000000046015101701376023615 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin $assertcontrol(0); $assertcontrol(100); end endmodule verilator-5.042/test_regress/t/t_flag_f_bad_cmt.vc0000644000542200017500000000004215101701376022626 0ustar mahmoudyfreeshell/* Multiline unterminated comment verilator-5.042/test_regress/t/t_preproc_elsif_bad.py0000755000542200017500000000105615101701376023432 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint( fails=True, # The .vh file has the error, not the .v file expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_inst_missing_dot_bad.v0000644000542200017500000000053115101701376023761 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Stefan Wallentowitz. // SPDX-License-Identifier: CC0-1.0 module t; initial begin $display("a=", missing.a); end missing missing(); // Intentionally missing endmodule verilator-5.042/test_regress/t/t_c_width_bad.v0000644000542200017500000000044615101701376022033 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Test of select from constant // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; bit [99:0] wide = $c100("0"); initial $display("%d", wide); endmodule verilator-5.042/test_regress/t/t_alias_transitive.py0000755000542200017500000000073415101701376023333 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_func_ref_arg.py0000755000542200017500000000073415101701376022412 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_randomize_rand_mode_unsup.py0000755000542200017500000000076315101701376025226 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_foreach_array.v0000755000542200017500000001163415101701376022415 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by PlanV GmbH. // SPDX-License-Identifier: CC0-1.0 module t_foreach_array; // Define various structures to test foreach behavior int dyn_arr[][]; int queue[$][$]; int unpacked_arr [3:1][9:8]; int associative_array_3d[string][string][string]; int queue_unp[$][3]; // Outer dynamic queue with fixed-size inner arrays int unp_queue[3][$]; // Fixed-size outer array with dynamic inner queues int dyn_queue[][]; // Fully dynamic 2D array int queue_dyn[$][]; // Outer dynamic queue with dynamic inner queues int dyn_unp[][3]; // Dynamic outer array with fixed-size inner arrays int unp_dyn[3][]; // Fixed-size outer array with dynamic inner arrays // Define counter for various structures of array int count_que, exp_count_que; int count_dyn, exp_count_dyn; int count_unp, exp_count_unp; int count_assoc; int count_queue_unp, exp_count_queue_unp; int count_unp_queue, exp_count_unp_queue; int count_dyn_queue, exp_count_dyn_queue; int count_queue_dyn, exp_count_queue_dyn; int count_dyn_unp, exp_count_dyn_unp; int count_unp_dyn, exp_count_unp_dyn; string k1, k2, k3; initial begin // Initialize queue = '{'{1, 2, 3}, '{4, 5}, '{6}}; dyn_arr = '{'{1, 2, 3}, '{4, 5, 6, 0, 10}, '{6, 7, 8, 9}}; associative_array_3d["key1"]["subkey1"]["subsubkey1"] = 1; associative_array_3d["key1"]["subkey1"]["subsubkey2"] = 2; associative_array_3d["key1"]["subkey2"]["subsubkey1"] = 3; associative_array_3d["key1"]["subkey3"]["subsubkey1"] = 4; associative_array_3d["key1"]["subkey3"]["subsubkey2"] = 5; associative_array_3d["key1"]["subkey3"]["subsubkey3"] = 6; associative_array_3d["key2"]["subkey1"]["subsubkey1"] = 7; associative_array_3d["key2"]["subkey1"]["subsubkey2"] = 8; associative_array_3d["key2"]["subkey3"]["subsubkey1"] = 9; queue_unp = '{'{1, 2, 3}, '{4, 5, 6}, '{7, 8, 9}}; unp_queue[0] = '{10, 11}; unp_queue[1] = '{12, 13, 14}; unp_queue[2] = '{15}; dyn_queue = '{'{16, 17}, '{18, 19, 20}}; queue_dyn = '{'{21, 22}, '{23, 24, 25}}; dyn_unp = '{'{26, 27, 28}, '{29, 30, 31}}; unp_dyn[0] = '{32, 33}; unp_dyn[1] = '{34, 35, 36}; unp_dyn[2] = '{37}; // Perform foreach loop counting and expected value calculation count_que = 0; foreach(queue[i, j]) count_que++; exp_count_que = 0; foreach(queue[i]) foreach(queue[i][j]) exp_count_que++; count_dyn = 0; foreach(dyn_arr[i, j]) count_dyn++; exp_count_dyn = 0; foreach(dyn_arr[i]) foreach(dyn_arr[i][j]) exp_count_dyn++; count_unp = 0; foreach(unpacked_arr[i, j]) count_unp++; exp_count_unp = 0; foreach(unpacked_arr[i]) foreach(unpacked_arr[i][j]) exp_count_unp++; count_assoc = 0; foreach(associative_array_3d[k1, k2, k3]) count_assoc++; count_queue_unp = 0; foreach (queue_unp[i, j]) count_queue_unp++; exp_count_queue_unp = 0; foreach (queue_unp[i]) foreach (queue_unp[i][j]) exp_count_queue_unp++; count_unp_queue = 0; foreach (unp_queue[i, j]) count_unp_queue++; exp_count_unp_queue = 0; foreach (unp_queue[i]) foreach (unp_queue[i][j]) exp_count_unp_queue++; count_dyn_queue = 0; foreach (dyn_queue[i, j]) count_dyn_queue++; exp_count_dyn_queue = 0; foreach (dyn_queue[i]) foreach (dyn_queue[i][j]) exp_count_dyn_queue++; count_queue_dyn = 0; foreach (queue_dyn[i, j]) count_queue_dyn++; exp_count_queue_dyn = 0; foreach (queue_dyn[i]) foreach (queue_dyn[i][j]) exp_count_queue_dyn++; count_dyn_unp = 0; foreach (dyn_unp[i, j]) count_dyn_unp++; exp_count_dyn_unp = 0; foreach (dyn_unp[i]) foreach (dyn_unp[i][j]) exp_count_dyn_unp++; count_unp_dyn = 0; foreach (unp_dyn[i, j]) count_unp_dyn++; exp_count_unp_dyn = 0; foreach (unp_dyn[i]) foreach (unp_dyn[i][j]) exp_count_unp_dyn++; // Verification checks if (count_que != 6 || count_que != exp_count_que) $stop; if (count_dyn != 12 || count_dyn != exp_count_dyn) $stop; if (count_unp != 6 || count_unp != exp_count_unp) $stop; if (count_assoc != 9) $stop; if (count_queue_unp != exp_count_queue_unp) $stop; if (count_unp_queue != exp_count_unp_queue) $stop; if (count_dyn_queue != exp_count_dyn_queue) $stop; if (count_queue_dyn != exp_count_queue_dyn) $stop; if (count_dyn_unp != exp_count_dyn_unp) $stop; if (count_unp_dyn != exp_count_unp_dyn) $stop; $write("*-* All Finished *-*\\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_alias_ports_unsup.py0000755000542200017500000000077615101701376023552 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_range_negative_bad.py0000755000542200017500000000076615101701376024611 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dpi_arg_input_type.py0000755000542200017500000000244115101701376023654 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if test.nc: # For NC, compile twice, first just to generate DPI headers test.compile(nc_flags2=[ "+ncdpiheader+" + test.obj_dir + "/dpi-exp.h", "+ncdpiimpheader+" + test.obj_dir + "/dpi-imp.h" ]) test.compile( v_flags2=["t/" + test.name + ".cpp"], # --no-decoration so .out file doesn't comment on source lines verilator_flags2=["-Wall -Wno-DECLFILENAME --no-decoration"], # NC: Gdd the obj_dir to the C include path nc_flags2=["+ncscargs+-I" + test.obj_dir], # ModelSim: Generate DPI header, add obj_dir to the C include path ms_flags2=["-dpiheader " + test.obj_dir + "/dpi.h", "-ccflags -I" + test.obj_dir]) if test.vlt_all: test.files_identical(test.obj_dir + "/" + test.vm_prefix + "__Dpi.h", "t/" + test.name + "__Dpi.out") test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_randomize_method_with_bad.v0000644000542200017500000000075315101701376024776 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class Foo; rand int unsigned v; endclass module t_randomize_method_with_bad(); function automatic int unsigned in_mod_function(); return 5; endfunction initial begin Foo foo = new; int res = foo.randomize() with { v < in_mod_function(); }; end endmodule verilator-5.042/test_regress/t/t_var_ref_bad3.out0000644000542200017500000000050115101701376022453 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_var_ref_bad3.v:10:18: Unsupported: ref/const ref as primary input/output: 'bad_primary_ref' 10 | module t(ref int bad_primary_ref); | ^~~~~~~~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_a5_attributes_include.py0000755000542200017500000000335415101701376024251 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') test.rerunnable = False def have_clang_check(): cmd = 'python3 -c "from clang.cindex import Index; index = Index.create(); print(\\"Clang imported\\")";' if test.verbose: print("\t" + cmd) nout = test.run_capture(cmd, check=False) if not nout or not re.search(r'Clang imported', nout): return False return True if 'VERILATOR_TEST_NO_ATTRIBUTES' in os.environ: test.skip("Skipping due to VERILATOR_TEST_NO_ATTRIBUTES") if not os.path.exists(test.root + "/src/obj_dbg/compile_commands.json"): test.skip("compile_commands.json not found. Please install 'bear > 3.0' and rebuild Verilator") if not have_clang_check(): test.skip("No libclang installed") # some of the files are only used in Verilation # and are only in "include" folder srcfiles = test.glob_some(test.root + "/include/*.cpp") srcfiles_str = " ".join(srcfiles) clang_args = "-I" + test.root + "/include/ -I" + test.root + "/include/vltstd/ -fcoroutines-ts" test.run(logfile=test.run_log_filename, tee=True, cmd=["python3", test.root + "/nodist/clang_check_attributes", "--verilator-root=" + test.root, "--cxxflags='" + clang_args + "'", srcfiles_str]) # yapf:disable test.file_grep(test.run_log_filename, r'Number of functions reported unsafe: +(\d+)', 0) test.passes() verilator-5.042/test_regress/t/t_mod_interface_array0.v0000644000542200017500000000260315101701376023656 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Johan Bjork. // SPDX-License-Identifier: CC0-1.0 parameter N = 4; interface a_if #(parameter PARAM = 0) (); logic long_name; modport source (output long_name); modport sink (input long_name); endinterface module intf_source ( input logic [N-1:0] intf_input, a_if.source i_intf_source[N-1:0] ); generate for (genvar i=0; i < N;i++) begin assign i_intf_source[i].long_name = intf_input[i]; end endgenerate endmodule module intf_sink ( output [N-1:0] a_out, a_if.sink i_intf_sink[N-1:0] ); generate for (genvar i=0; i < N;i++) begin assign a_out[i] = i_intf_sink[i].long_name; end endgenerate endmodule module t ( clk ); input clk; logic [N-1:0] a_in; logic [N-1:0] a_out; logic [N-1:0] ack_out; a_if #(.PARAM(1)) tl_intf [N-1:0] (); intf_source source(a_in, tl_intf); intf_sink sink(a_out, tl_intf); initial a_in = '0; initial ack_out = '0; always @(posedge clk) begin a_in <= a_in + { {N-1 {1'b0}}, 1'b1 }; ack_out <= ack_out + { {N-1 {1'b0}}, 1'b1 }; if (ack_out != a_out) begin $stop; end if (& a_in) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_nba_struct_array.py0000755000542200017500000000075715101701376023341 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(check_finished=True) test.passes() verilator-5.042/test_regress/t/t_dedupe_clk_gate.v0000644000542200017500000000255715101701376022710 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Dedupe optimization test. // // This file ONLY is placed into the Public Domain, for any use, // without warranty. // SPDX-License-Identifier: CC0-1.0 // Contributed 2012 by Varun Koyyalagunta, Centaur Technology. module t(res,d,clk,en); output res; input d,en,clk; wire q0,q1,q2,q3; flop_gated_latch f0(q0,d,clk,en); flop_gated_latch f1(q1,d,clk,en); flop_gated_flop f2(q2,d,clk,en); flop_gated_flop f3(q3,d,clk,en); assign res = (q0 + q1) * (q2 - q3); endmodule module flop_gated_latch(q,d,clk,en); input d, clk, en; output reg q; wire gated_clock; clock_gate_latch clock_gate(gated_clock, clk, en); always @(posedge gated_clock) begin q <= d; end endmodule module flop_gated_flop(q,d,clk,en); input d, clk, en; output reg q; wire gated_clock; clock_gate_flop clock_gate(gated_clock, clk, en); always @(posedge gated_clock) begin q <= d; end endmodule module clock_gate_latch (gated_clk, clk, clken); output gated_clk; input clk, clken; reg clken_latched; assign gated_clk = clk & clken_latched ; wire clkb = ~clk; always_latch @(clkb or clken) if(clkb) clken_latched = clken; endmodule module clock_gate_flop (gated_clk, clk, clken); output gated_clk; input clk, clken; reg clken_r; assign gated_clk = clk & clken_r ; always @(negedge clk) clken_r <= clken; endmodule verilator-5.042/test_regress/t/t_covergroup_args.py0000755000542200017500000000070615101701376023200 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.passes() verilator-5.042/test_regress/t/t_param_default_override.v0000644000542200017500000000301315101701376024300 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Josse Van Delm. // SPDX-License-Identifier: CC0-1.0 // verilator lint_off WIDTH module m2 #(parameter int N = 4) (input [N-1:0] i0, i1, input s, output [N-1:0] y); assign y = s ? i1 : i0; endmodule module m4 #(parameter int N = 4) (input [N-1:0] i0, i1, i2, i3, input [1:0] S, output [N-1:0] y); wire [N-1:0] o_low, o_high; // See issue #4920 - use of m4 without parameter overrides // caused the other use of m4(#(6)) to irop the #(N) below m2 #(N) lowm( .i0(i0), .i1(i1), .s(S[0]), .y(o_low)); m2 #(N) highm( .i0(i2), .i1(i3), .s(S[0]), .y(o_high)); m2 #(N) finalm( .i0(o_low), .i1(o_high), .s(S[1]), .y(y)); endmodule module m8 #(parameter int N = 4) (input [N-1:0] i0, i1, i2, i3, i4, i5, i6, i7, input [2:0] S, output [N-1:0] y); wire [N-1:0] o_low, o_high; m4 #(N) lowm(.i0(i0), .i1(i1), .i2(i2), .i3(i3), .S(S[1:0]), .y(o_low)); m4 #(N) highm(.i0(i4), .i1(i5), .i2(i6), .i3(i7), .S(S[1:0]), .y(o_high)); m2 #(N) finalm(.i0(o_low), .i1(o_high), .s(S[2]), .y(y)); endmodule module t (); reg [5:0] i0, i1, i2, i3; reg [1:0] S; wire [5:0] Y; m4 #(6) iut(.i0(i0), .i1(i1), .i2(i2), .i3(i3), .S(S), .y(Y)); initial begin i0 = 6'b000000; i1 = 6'b000001; i2 = 6'b000010; i3 = 6'b000100; S = 2'b00; #10; S = 2'b01; #10; $write("*-* All Finished *-*\n"); end endmodule verilator-5.042/test_regress/t/t_queue.v0000644000542200017500000001743315101701376020734 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; integer i; typedef int q_t[$]; function void set_val(ref int lhs, input int rhs); lhs = rhs; endfunction initial begin q_t iq; iq.push_back(42); // Resize via [] set_val(iq[0], 9000); `checkh(iq.size(), 1); `checks(iq[0], 9000); iq[1]++; `checkh(iq.size(), 2); `checks(iq[1], 1); iq[1000] = 1000; `checkh(iq.size(), 2); `checks(iq[1000], 0); end always @ (posedge clk) begin cyc <= cyc + 1; begin // Very simple test using bit bit q[$]; bit x; `checkh($left(q), 0); `checkh($right(q), -1); `checkh($increment(q), -1); `checkh($low(q), 0); `checkh($high(q), -1); `checkh($size(q), 0); `checkh($dimensions(q), 1); // $bits is unsupported in several other simulators, see bug1646 // Unsup: `checkh($bits(q), 0); q.push_back(1'b1); `checkh($left(q), 0); `checkh($right(q), 0); `checkh($increment(q), -1); `checkh($low(q), 0); `checkh($high(q), 0); `checkh($size(q), 1); `checkh($dimensions(q), 1); // Unsup: `checkh($bits(q), 2); `checkh(q.size(), 1); q.push_back(1'b1); q.push_back(1'b0); q.push_back(1'b1); `checkh($left(q), 0); `checkh($right(q), 3); `checkh($low(q), 0); `checkh($high(q), 3); `checkh($size(q), 4); // Unsup: `checkh($bits(q), 4); `checkh(q.size(), 4); x = q.pop_back(); `checkh(x, 1'b1); `checkh($left(q), 0); `checkh($right(q), 2); `checkh($low(q), 0); `checkh($high(q), 2); `checkh($size(q), 3); // sure those are working now.. x = q.pop_front(); `checkh(x, 1'b1); x = q.pop_front(); `checkh(x, 1'b1); x = q.pop_front(); `checkh(x, 1'b0); `checkh(q.size(), 0); end begin // Simple test using integer typedef bit [3:0] nibble_t; nibble_t q[$]; nibble_t v; `checkh($left(q), 0); `checkh($right(q), -1); `checkh($increment(q), -1); `checkh($low(q), 0); `checkh($high(q), -1); `checkh($size(q), 0); `checkh($dimensions(q), 2); i = q.size(); `checkh(i, 0); q.push_back(4'd1); // 1 q.push_front(4'd2); // 2 1 q.push_back(4'd3); // 2 1 3 i = q.size; `checkh(i, 3); // Also checks no parens end begin // Strings string q[$]; string p[$:3]; string v; int j; // Empty queue checks `checkh($left(q), 0); `checkh($right(q), -1); `checkh($increment(q), -1); `checkh($low(q), 0); `checkh($high(q), -1); `checkh($size(q), 0); `checkh($dimensions(q), 2); //Unsup: `checkh($bits(q), 0); q.push_front("f1"); //Unsup: `checkh($bits(q), 16); q.push_back("b1"); q.push_front("f2"); q.push_back("b2"); i = q.size(); `checkh(i, 4); v = q[0]; `checks(v, "f2"); v = q[1]; `checks(v, "f1"); v = q[2]; `checks(v, "b1"); v = q[3]; `checks(v, "b2"); v = q[4]; `checks(v, ""); //Unsup: `checkh(q[$], "b2"); `checkp(q, "'{\"f2\", \"f1\", \"b1\", \"b2\"}"); `checkp(p, "'{}"); //Unsup: q.delete(1); //Unsup: v = q[1]; `checks(v, "b1"); //Unsup: q.insert(0, "ins0"); //Unsup: q.insert(3, "ins3"); //v = q[0]; `checks(v, "ins0"); //v = q[3]; `checks(v, "ins3"); j = 0; foreach (q[i]) begin j++; v = q[i]; if (i == 0) `checks(v, "f2"); if (i == 1) `checks(v, "f1"); if (i == 2) `checks(v, "b1"); if (i == 3) `checks(v, "b2"); end `checkh(j,4); q.pop_front(); v = q.pop_front(); `checks(v, "f1"); v = q.pop_back(); `checks(v, "b2"); v = q.pop_back(); `checks(v, "b1"); i = q.size(); `checkh(i, 0); // Empty queue, this should be 0 foreach (q[i]) begin j++; end `checkh(j,4); q.push_front("non-empty"); i = q.size(); `checkh(i, 1); q.delete(); i = q.size(); `checkh(i, 0); v = q.pop_front(); `checks(v, ""); // Was empty, optional warning v = q.pop_back(); `checks(v, ""); // Was empty, optional warning // Conversion of insert/delete with zero to operator q.push_front("front"); q.insert(0, "newfront"); i = q.size(); `checkh(i, 2); q.delete(0); i = q.size(); `checkh(i, 1); `checks(q[0], "front"); //Unsup: `checks(q[$], "front"); // Resize via [] q[0] = "long"; `checkh(q.size(), 1); `checks(q[0], "long"); end // Append to queue of queues using [] begin int q[$][$]; q[0][0] = 1; `checkh(q.size(), 1); `checkh(q[0].size(), 1); `checks(q[0][0], 1); end // Do not append with [] if used as index begin int p[$]; int q[$]; q[p[0]] = 1; `checkh(p.size(), 0); `checkh(q.size(), 1); `checks(q[0], 1); end begin typedef struct packed { bit [7:0] opcode; bit [23:0] addr; } instruction; // named structure type instruction q[$]; `checkh($dimensions(q), 2); //Unsup: `checkh($bits(q), 0); end // testing a wide queue begin typedef struct packed { bit [7:0] opcode; bit [23:0] addr; bit [127:0] data; } instructionW; // named structure type instructionW inst_push; instructionW inst_pop; instructionW q[$]; `checkh($dimensions(q), 2); `checkh(q[0].opcode, 0); `checkh(q[0].addr, 0); `checkh(q[0].data, 0); inst_push.opcode = 1; inst_push.addr = 42; inst_push.data = {4{32'hdeadbeef}}; q.push_back(inst_push); `checkh(q[0].opcode, 1); `checkh(q[0].addr, 42); `checkh(q[0].data, {4{32'hdeadbeef}}); inst_pop = q.pop_front(); `checkh(inst_pop.opcode, 1); `checkh(inst_pop.addr, 42); `checkh(inst_pop.data, {4{32'hdeadbeef}}); `checkh(q.size(), 0); `checkh(q[0].opcode, 0); `checkh(q[0].addr, 0); `checkh(q[0].data, 0); end /* Unsup: begin int q[4][$]; q[0].push_back(0); q[0].push_back(1); q[1].push_back(2); q[2].push_back(3); end */ // See t_queue_unsup_bad for more unsupported stuff $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_assert_ctl_immediate_noinl.py0000755000542200017500000000130015101701376025340 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t_assert_ctl_immediate.v" test.golden_filename = "t/t_assert_ctl_immediate.out" test.compile(verilator_flags2=['--assert --timing --fno-inline']) test.execute(all_run_flags=["+verilator+error+limit+100"], expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_gate_inline_wide_exclude_multiple.v0000644000542200017500000000137515101701376026520 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 localparam N = 256; // Wider than expand limit. module t( input wire [N-1:0] i, output logic [N-1:0] o_multiple1, output logic [N-1:0] o_multiple2, output wire [N-1:0] o ); // Exclude from inline wide expressions referenced multiple times. wire [N-1:0] wide_multiple_assigns = N >> i; wire [N-1:0] wide = N << i; for (genvar n = 0; n < N - 1; ++n) begin assign o[n] = i[N-1-n] | wide[N-1-n]; end assign o_multiple1 = wide_multiple_assigns | i + 1; assign o_multiple2 = wide_multiple_assigns | i + 2; endmodule verilator-5.042/test_regress/t/t_dpi_context.py0000755000542200017500000000103215101701376022302 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=["t/t_dpi_context_c.cpp", "--debug", "-no-dump-tree"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_class_param_extends3.py0000755000542200017500000000073415101701376024074 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_pp_recursedef_bad.py0000755000542200017500000000076315101701376023430 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_enum_bad_value.v0000644000542200017500000000100715101701376022544 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(); enum bit signed [3:0] {OK1 = -1} ok1_t; // As is signed, loss of 1 bits is ok per IEEE enum bit signed [3:0] {OK2 = 3} ok2_t; typedef enum [2:0] { VALUE_BAD1 = 8 } enum_t; enum bit [4:0] {BAD2[4] = 100} bad2; enum logic [3:0] {BAD3 = 5'bxxxxx} bad3; initial $stop; endmodule verilator-5.042/test_regress/t/t_interface_gen7.v0000644000542200017500000000330115101701376022455 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty. // SPDX-License-Identifier: CC0-1.0 // bug998 interface intf #(parameter PARAM = 0) (); /* verilator lint_off MULTIDRIVEN */ logic val; /* verilator lint_on MULTIDRIVEN */ function integer func (); return 5; endfunction endinterface module t1(intf mod_intf); initial begin $display("%m %d", mod_intf.val); end endmodule module t(); intf #(.PARAM(1)) my_intf [1:0] (); generate genvar the_genvar; begin : ia for (the_genvar = 0; the_genvar < 2; the_genvar++) begin : TestIf begin assign my_intf[the_genvar].val = '1; t1 t (.mod_intf(my_intf[the_genvar])); end end end endgenerate generate genvar the_second_genvar; begin : ib intf #(.PARAM(1)) my_intf [1:0] (); for (the_second_genvar = 0; the_second_genvar < 2; the_second_genvar++) begin : TestIf begin assign my_intf[the_second_genvar].val = '1; t1 t (.mod_intf(my_intf[the_second_genvar])); end end end endgenerate generate genvar the_third_genvar; begin : ic for (the_third_genvar = 0; the_third_genvar < 2; the_third_genvar++) begin : TestIf begin intf #(.PARAM(1)) my_intf [1:0] (); assign my_intf[the_third_genvar].val = '1; t1 t (.mod_intf(my_intf[the_third_genvar])); end end end endgenerate initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_struct_unpacked_array.v0000644000542200017500000000153415101701376024177 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef struct { logic a; } Data_t; module t (/*AUTOARG*/ clk ); input clk; int cyc = 0; localparam int SIZE = 20; reg[$clog2(SIZE)-1 : 0] ptr; Data_t buffer[SIZE]; Data_t out; reg out1; always_ff @( posedge clk ) begin int i; cyc <= cyc + 1; if (cyc == 0) begin for (i=0;i= 0); | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_randomize_rand_mode.py0000755000542200017500000000073415101701376023772 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_param_type_cmp.v0000644000542200017500000000214415101701376022601 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (); logic [2:0] a; logic [2:0] b; logic signed_out; logic unsigned_out; cmp #(.element_type(logic signed [2:0])) signed_cmp (.a(a), .b(b), .c(signed_out)); cmp #(.element_type(logic [2:0])) unsigned_cmp (.a(a), .b(b), .c(unsigned_out)); initial a = 3'b001; initial b = 3'b111; initial begin #1; if (signed_out !== 1'b0) begin $display("%%Error: bad signed comparison %b < %b: got=%d exp=%d", a, b, signed_out, 1'b0); $stop; end if (unsigned_out !== 1'b1) begin $display("%%Error: bad unsigned comparison %b < %b: got=%d exp=%d", a, b, unsigned_out, 1'b1); $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule module cmp #( parameter type element_type = logic ) ( input element_type a, input element_type b, output logic c ); assign c = a < b; endmodule verilator-5.042/test_regress/t/t_lint_blkseq_bad.py0000755000542200017500000000111115101701376023075 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["--lint-only -Wwarn-BLKSEQ -Wwarn-COMBDLY"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_real_out_of_bounds.v0000644000542200017500000000160715101701376023454 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilog_format: off `define stop $stop `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); // verilog_format: on module t; class Cls; function void m_uvm_execute_field_op(); real sa_real[3]; string s; // 5 doesn't match array size of 3 for (int i = 0; i < 5; ++i) begin s = $sformatf("%g", sa_real[i]); `checks(s, "0"); s = $sformatf("%p", sa_real[i]); `checks(s, "0"); end endfunction endclass initial begin Cls c; c = new; c.m_uvm_execute_field_op(); $finish; end endmodule verilator-5.042/test_regress/t/t_sdf_annotate_unsup.py0000755000542200017500000000077615101701376023677 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_math_vgen.py0000755000542200017500000000073415101701376021742 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_tri_pull2_bad.v0000644000542200017500000000064515101701376022327 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2010 by Lane Brooks. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; wire A; pullup p1(A); child child(/*AUTOINST*/ // Inouts .A (A)); endmodule module child(inout A); pulldown p2(A); endmodule verilator-5.042/test_regress/t/t_const_bad.v0000644000542200017500000000110615101701376021532 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin if (32'hxxxxxxxx !== 'hx) $stop; if (32'hzzzzzzzz !== 'hz) $stop; if (32'h???????? !== 'h?) $stop; if (68'hx_xxxxxxxx_xxxxxxxx !== 'dX) $stop; if (68'hz_zzzzzzzz_zzzzzzzz !== 'dZ) $stop; if (68'h?_????????_???????? !== 'd?) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_langext_2_bad.py0000755000542200017500000000116115101701376022456 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.top_filename = "t/t_langext_2.v" test.leak_check_disable() # This is a lint only test. test.lint(v_flags2=["+1364-1995ext+v"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_mem_slot.py0000755000542200017500000000112715101701376021606 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename, "--no-timing"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_exprstmt_on_lhs_of_nba.py0000755000542200017500000000070615101701376024525 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.passes() verilator-5.042/test_regress/t/t_tri_gate_pmos.py0000755000542200017500000000136115101701376022623 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_tri_gate.cpp" test.top_filename = "t/t_tri_gate.v" test.compile(make_top_shell=False, make_main=False, v_flags2=['+define+T_PMOS'], make_flags=['CPPFLAGS_ADD=-DT_PMOS'], verilator_flags2=["--exe", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_inst_recurse2_bad.py0000755000542200017500000000076615101701376023374 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface_generic_modport_bad2.out0000755000542200017500000000053115101701376026234 0ustar mahmoudyfreeshell%Error: t/t_interface_generic_modport_bad2.v:17:7: Attempt to drive input-only modport: 'v' : ... note: In instance 't.genericModule' 17 | a.v = 10; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_semaphore_class.v0000644000542200017500000000152115101701376022747 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class semaphore_cls; // Test an implementation similar to what Verilator will do internally int m_keys; function new(int keyCount = 0); m_keys = keyCount; endfunction function void put(int keyCount = 1); m_keys += keyCount; endfunction task get(int keyCount = 1); wait (m_keys >= keyCount); m_keys -= keyCount; endtask function int try_get(int keyCount = 1); if (m_keys >= keyCount) begin m_keys -= keyCount; return 1; end else begin return 0; end endfunction endclass `define SEMAPHORE_T semaphore_cls `include "t_semaphore.v" verilator-5.042/test_regress/t/t_unpacked_concat_bad2.out0000644000542200017500000000147315101701376024160 0ustar mahmoudyfreeshell%Error: t/t_unpacked_concat_bad2.v:20:15: Array initialization has too many elements. 2 elements are expected, but at least 5 elements exist. 20 | s1 = {s0, s2}; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_unpacked_concat_bad2.v:21:23: Array initialization has too many elements. 4 elements are expected, but at least 5 elements exist. 21 | s2 = {s1, s0, s0, s0}; | ^ %Error: t/t_unpacked_concat_bad2.v:23:17: Item is incompatible with the array type. 23 | s2 = {s0, s3}; | ^~ %Error: t/t_unpacked_concat_bad2.v:25:19: Item is incompatible with the array type. 25 | A9_logic = {A3, 4, 5, A3, 6}; | ^~ %Error: Exiting due to verilator-5.042/test_regress/t/t_savable_open_bad.out0000644000542200017500000000037315101701376023411 0ustar mahmoudyfreeshellModel width = 10 Restoring model from 'obj_vlt/t_savable_open_bad/saved.vltsv' %Error: obj_vlt/t_savable_open_bad/saved.vltsv:0: Can't deserialize; file has wrong header signature, or file not found: obj_vlt/t_savable_open_bad/saved.vltsv Aborting... verilator-5.042/test_regress/t/t_config_libmap.v0000644000542200017500000000047115101701376022373 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_net_dtype_bad.v0000644000542200017500000000143415101701376022403 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls; endclass module t; typedef real real_t; typedef struct packed { bit m_bit; } bad_t; typedef struct { logic m_bit; } ok_unpk_t; typedef struct packed { logic m_bit; } ok_t; wire real_t bad_real; // <--- Error - bad net type wire Cls bad_class; // <--- Error - bad net type wire string bad_string; // <--- Error - bad net type wire bit bad_bit; // <--- Error - bad net type wire bad_t bad_struct; // <--- Error - bad net type wire ok_unpk_t ok_unpk_struct; wire ok_t ok_struct; // Ok initial $stop; endmodule verilator-5.042/test_regress/t/t_timing_sched_nba.v0000644000542200017500000000243015101701376023054 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; bit clk1 = 0; assign #3 clk1 = ~clk1; bit clk2 = 0; assign #11 clk2 = ~clk2; int a1 = 0; int b1 = 0; always @(posedge clk1) #4 a1 <= a1 + 1; always @(posedge clk1) @(posedge clk2) b1 <= b1 + 1; int a2 = 0; always_comb begin // verilator lint_off MULTIDRIVEN a2 = a1 << 1; // verilator lint_on MULTIDRIVEN `ifdef TEST_VERBOSE $display("[%0t] a2 = %0d", $time, a2); `endif end int b2 = 0; always_comb begin // verilator lint_off MULTIDRIVEN b2 = b1 << 2; // verilator lint_on MULTIDRIVEN `ifdef TEST_VERBOSE $display("[%0t] b2 = %0d", $time, b2); `endif end always @(posedge clk1) #5 if (a2 != a1 << 1) $stop; always @(posedge clk2) #1 if (b2 != b1 << 2) $stop; initial #78 begin `ifdef TEST_VERBOSE $display("a1=%0d, b1=%0d, a2=%0d, b2=%0d", a1, b1, a2, b2); `endif if (a1 != 12) $stop; if (b1 != 4) $stop; if (a2 != a1 << 1) $stop; if (b2 != b1 << 2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_runflag_errorlimit_bad.out0000644000542200017500000000057615101701376024666 0ustar mahmoudyfreeshell[0] %Error: t_runflag_errorlimit_bad.v:9: Assertion failed in top.t: One -Info: t/t_runflag_errorlimit_bad.v:9: Verilog $stop, ignored due to +verilator+error+limit [0] %Error: t_runflag_errorlimit_bad.v:10: Assertion failed in top.t: Two [0] %Error: t_runflag_errorlimit_bad.v:11: Assertion failed in top.t: Three %Error: t/t_runflag_errorlimit_bad.v:11: Verilog $stop Aborting... verilator-5.042/test_regress/t/t_vlcov_opt_user.py0000755000542200017500000000133615101701376023042 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') test.run(cmd=[ os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--write-info", test.obj_dir + "/coverage.info", "--filter-type user", "t/t_vlcov_data_f.dat" ], verilator_run=True) test.files_identical(test.obj_dir + "/coverage.info", "t/" + test.name + ".info.out") test.passes() verilator-5.042/test_regress/t/t_timing_func_fork.py0000755000542200017500000000077015101701376023315 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary -Wno-UNOPTFLAT"]) test.passes() verilator-5.042/test_regress/t/t_flag_names.py0000755000542200017500000000104115101701376022056 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["--mod-prefix modPrefix --top-module t --l2-name l2Name"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_wrapper_context__trace1.vcd.out0000644000542200017500000000215015101701376025535 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top0 $end $var wire 1 # clk $end $var wire 1 $ rst $end $var wire 32 % trace_number [31:0] $end $var wire 1 & stop $end $var wire 32 ' counter [31:0] $end $var wire 1 ( done_o $end $scope module top $end $var wire 1 # clk $end $var wire 1 $ rst $end $var wire 32 % trace_number [31:0] $end $var wire 1 & stop $end $var wire 32 ' counter [31:0] $end $var wire 1 ( done_o $end $upscope $end $upscope $end $enddefinitions $end #0 0# 1$ b00000000000000000000000000000001 % 0& b00000000000000000000000000000000 ' 0( #1 1# #2 0# 0$ #3 1# b00000000000000000000000000000001 ' #4 0# #5 1# b00000000000000000000000000000010 ' #6 0# #7 1# b00000000000000000000000000000011 ' #8 0# #9 1# b00000000000000000000000000000100 ' #10 0# #11 1# b00000000000000000000000000000101 ' #12 0# #13 1# b00000000000000000000000000000110 ' #14 0# #15 1# b00000000000000000000000000000111 ' #16 0# #17 1# b00000000000000000000000000001000 ' #18 0# #19 1# b00000000000000000000000000001001 ' #20 0# #21 1# b00000000000000000000000000001010 ' 1( verilator-5.042/test_regress/t/t_xml_tag.py0000755000542200017500000000133615101701376021424 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') out_filename = test.obj_dir + "/V" + test.name + ".xml" test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only'], verilator_make_gmake=False, make_top_shell=False, make_main=False) test.files_identical(out_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_vpi_module_empty.py0000755000542200017500000000124515101701376023351 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile( make_top_shell=False, make_main=False, make_pli=True, iv_flags2=["-g2005-sv"], verilator_flags2=["+define+USE_DOLLAR_C32 --exe --vpi --no-l2name", test.pli_filename]) test.execute(use_libvpi=True) test.passes() verilator-5.042/test_regress/t/t_runflag_errorlimit_fatal_bad.v0000644000542200017500000000066415101701376025471 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin $error("One"); $fatal; $error("Two"); $error("Three"); $error("Four"); $error("Five"); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_lint_latch_bad.py0000755000542200017500000000111015101701376022706 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--lint-only -Wwarn-style -Wno-DECLFILENAME"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_inside_assoc_unsup.py0000755000542200017500000000076615101701376023674 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_emit_constw.py0000755000542200017500000000077515101701376022332 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--fno-expand']) test.execute() test.passes() verilator-5.042/test_regress/t/t_case_unique_many.py0000755000542200017500000000077115101701376023320 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--assert"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_randomize_method_with_bad.out0000644000542200017500000000055515101701376025340 0ustar mahmoudyfreeshell%Error: t/t_randomize_method_with_bad.v:18:42: Can't find definition of task/function: 'in_mod_function' 18 | int res = foo.randomize() with { v < in_mod_function(); }; | ^~~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_order_blkloopinit_bad.v0000644000542200017500000000122215101701376024124 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Test of select from constant // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilator lint_off MULTIDRIVEN module t (/*AUTOARG*/ // Outputs o, // Inputs clk ); input clk; output int o; localparam SIZE = 65536; // Unsupported case 1: Array NBA to compund type class C; endclass C array2[SIZE]; always @ (negedge clk) begin o <= int'(array2[1] == null); for (int i=0; i b) ? a : b; endfunction function automatic integer log2; input integer value; value = value >> 1; for (log2 = 0; value > 0; log2 = log2 + 1) value = value >> 1; endfunction function automatic integer ceil_log2; input integer value; value = value - 1; for (ceil_log2 = 0; value > 0; ceil_log2 = ceil_log2 + 1) value = value >> 1; endfunction endpackage module sub(); import defs::*; parameter RAND_NUM_MAX = ""; localparam DATA_RANGE = RAND_NUM_MAX + 1; localparam DATA_WIDTH = ceil_log2(DATA_RANGE); localparam WIDTH = max(4, ceil_log2(DATA_RANGE + 1)); endmodule module t; import defs::*; parameter WHICH = 0; parameter MAX_COUNT = 10; localparam MAX_EXPONENT = log2(MAX_COUNT); localparam EXPONENT_WIDTH = ceil_log2(MAX_EXPONENT + 1); generate if (WHICH == 1) begin : which_true sub sub_true(); defparam sub_true.RAND_NUM_MAX = MAX_EXPONENT; end else begin : which_false sub sub_false(); defparam sub_false.RAND_NUM_MAX = MAX_COUNT; end endgenerate endmodule verilator-5.042/test_regress/t/t_case_nest.v0000644000542200017500000001056415101701376021552 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc = 0; reg [63:0] crc; reg [63:0] sum; reg out1; sub sub (.in(crc[23:0]), .out1(out1)); always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x sum=%x out=%x\n", $time, cyc, crc, sum, out1); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {63'h0,out1}; if (cyc==1) begin // Setup crc <= 64'h00000000_00000097; sum <= 64'h0; end else if (cyc==90) begin if (sum !== 64'h2e5cb972eb02b8a0) $stop; end else if (cyc==91) begin end else if (cyc==92) begin end else if (cyc==93) begin end else if (cyc==94) begin end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module sub (/*AUTOARG*/ // Outputs out1, // Inputs in ); input [23:0] in; output reg [0:0] out1; // Note this tests a vector of 1 bit, which is different from a non-arrayed signal parameter [1023:0] RANDOM = 1024'b101011010100011011100111101001000000101000001111111111100110000110011011010110011101000100110000110101111101000111100100010111001001110001010101000111000100010000010011100001100011110110110000101100011111000110111110010110011000011111111010101110001101010010001111110111100000110111101100110101110001110110000010000110101110111001111001100001101110001011100111001001110101001010000110101010100101111000010000010110100101110100110000110110101000100011101111100011000110011001100010010011001101100100101110010100110101001110011111110010000111001111000010001101100101101110111110001000010110010011100101001011111110011010110111110000110010011110001110110011010011010110011011111001110100010110100011100001011000101111000010011111010111001110110011101110101011111001100011000101000001000100111110010100111011101010101011001101000100000101111110010011010011010001111010001110000110010100011110110011001010000011001010010110111101010010011111111010001000101100010100100010011001100110000111111000001000000001001111101110000100101; always @* begin casez (in[17:16]) 2'b00: casez (in[2:0]) 3'h0: out1[0] = in[0]^RANDOM[0]; 3'h1: out1[0] = in[0]^RANDOM[1]; 3'h2: out1[0] = in[0]^RANDOM[2]; 3'h3: out1[0] = in[0]^RANDOM[3]; 3'h4: out1[0] = in[0]^RANDOM[4]; 3'h5: out1[0] = in[0]^RANDOM[5]; 3'h6: out1[0] = in[0]^RANDOM[6]; 3'h7: out1[0] = in[0]^RANDOM[7]; endcase 2'b01: casez (in[2:0]) 3'h0: out1[0] = RANDOM[10]; 3'h1: out1[0] = RANDOM[11]; 3'h2: out1[0] = RANDOM[12]; 3'h3: out1[0] = RANDOM[13]; 3'h4: out1[0] = RANDOM[14]; 3'h5: out1[0] = RANDOM[15]; 3'h6: out1[0] = RANDOM[16]; 3'h7: out1[0] = RANDOM[17]; endcase 2'b1?: casez (in[4]) 1'b1: casez (in[2:0]) 3'h0: out1[0] = RANDOM[20]; 3'h1: out1[0] = RANDOM[21]; 3'h2: out1[0] = RANDOM[22]; 3'h3: out1[0] = RANDOM[23]; 3'h4: out1[0] = RANDOM[24]; 3'h5: out1[0] = RANDOM[25]; 3'h6: out1[0] = RANDOM[26]; 3'h7: out1[0] = RANDOM[27]; endcase 1'b0: casez (in[2:0]) 3'h0: out1[0] = RANDOM[30]; 3'h1: out1[0] = RANDOM[31]; 3'h2: out1[0] = RANDOM[32]; 3'h3: out1[0] = RANDOM[33]; 3'h4: out1[0] = RANDOM[34]; 3'h5: out1[0] = RANDOM[35]; 3'h6: out1[0] = RANDOM[36]; 3'h7: out1[0] = RANDOM[37]; endcase endcase endcase end endmodule verilator-5.042/test_regress/t/t_math_shortcircuit_assocsel.py0000755000542200017500000000073415101701376025421 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_inst_tree_inl0_pub0.py0000755000542200017500000000272315101701376023636 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_inst_tree.v" out_filename = test.obj_dir + "/V" + test.name + ".tree.json" test.compile(v_flags2=["--no-json-edit-nums", test.t_dir + "/" + test.name + ".vlt"]) if test.vlt_all: test.file_grep(out_filename, r'{"type":"MODULE","name":"l1",.*"loc":"\w,56:[^"]*",.*"origName":"l1"') test.file_grep(out_filename, r'{"type":"MODULE","name":"l2",.*"loc":"\w,62:[^"]*",.*"origName":"l2"') test.file_grep(out_filename, r'{"type":"MODULE","name":"l3",.*"loc":"\w,69:[^"]*",.*"origName":"l3"') test.file_grep(out_filename, r'{"type":"MODULE","name":"l4",.*"loc":"\w,76:[^"]*",.*"origName":"l4"') test.file_grep(out_filename, r'{"type":"MODULE","name":"l5__P1",.*"loc":"\w,83:[^"]*",.*"origName":"l5"') test.file_grep(out_filename, r'{"type":"MODULE","name":"l5__P2",.*"loc":"\w,83:[^"]*",.*"origName":"l5"') test.execute() test.file_grep(test.run_log_filename, r"\] (%m|.*t\.ps): Clocked") test.passes() verilator-5.042/test_regress/t/t_randomize_neasted_unsup.v0000644000542200017500000000071015101701376024523 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class A; rand logic[31:0] rdata; endclass module t; A a; A aa; initial begin a = new; aa = new; if (a.randomize() with {rdata == aa.randomize();} == 0) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_stream_dynamic.v0000644000542200017500000001410515101701376022600 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); typedef enum bit [5:0] { A = 6'b111000, B = 6,b111111 } enum_t; module t; task test1; bit arr[]; bit [1:0] arr2[$]; bit [5:0] arr6[$]; bit [5:0] bit6; bit [5:0] ans; bit [3:0] arr4[]; bit [7:0] arr8[]; bit [63:0] arr64[]; bit [159:0] arr160[]; bit [63:0] bit64; bit [99:0] bit100; bit [319:0] bit320; enum_t ans_enum; bit6 = 6'b111000; arr4 = '{25{4'b1000}}; arr8 = '{8{8'b00110011}}; arr64 = '{5{64'h0123456789abcdef}}; arr160 = '{2{160'h0123456789abcdef0123456789abcdef01234567}}; { >> bit {arr}} = bit6; `checkp(arr, "'{'h1, 'h1, 'h1, 'h0, 'h0, 'h0}"); ans = { >> bit {arr} }; `checkh(ans, bit6); ans_enum = enum_t'({ >> bit {arr} }); `checkh(ans_enum, bit6); { << bit {arr}} = bit6; `checkp(arr, "'{'h0, 'h0, 'h0, 'h1, 'h1, 'h1}"); ans = { << bit {arr} }; `checkh(ans, bit6); ans_enum = enum_t'({ << bit {arr} }); `checkh(ans_enum, bit6); `ifdef VERILATOR // This set flags errors on other simulators { >> bit[1:0] {arr2}} = bit6; `checkp(arr2, "'{'h3, 'h2, 'h0}"); ans = { >> bit[1:0] {arr2} }; `checkh(ans, bit6); ans_enum = enum_t'({ >> bit[1:0] {arr2} }); `checkh(ans_enum, bit6); { << bit[1:0] {arr2}} = bit6; `checkp(arr2, "'{'h0, 'h2, 'h3}"); ans = { << bit[1:0] {arr2} }; `checkh(ans, bit6); ans_enum = enum_t'({ << bit[1:0] {arr2} }); `checkh(ans_enum, bit6); { >> bit [5:0] {arr6} } = bit6; `checkp(arr6, "'{'h38}"); ans = { >> bit[5:0] {arr6} }; `checkh(ans, bit6); ans_enum = enum_t'({ >> bit[5:0] {arr6} }); `checkh(ans_enum, bit6); { << bit [5:0] {arr6} } = bit6; `checkp(arr6, "'{'h38}"); ans = { << bit[5:0] {arr6} }; `checkh(ans, bit6); ans_enum = enum_t'({ << bit[5:0] {arr6} }); `checkh(ans_enum, bit6); `endif bit64 = { >> bit {arr8} }; `checkh(bit64[7:0], 8'b00110011); bit64 = { << bit {arr8} }; `checkh(bit64[7:0], 8'b11001100); { >> bit {arr8} } = bit64; `checkh(arr8[0], 8'b11001100); { << bit {arr8} } = bit64; `checkh(arr8[0], 8'b00110011); bit100 = { >> bit {arr4} }; `checkh(bit100[3:0], 4'b1000); bit100 = { << bit {arr4} }; `checkh(bit100[3:0], 4'b0001); { >> bit {arr4} } = bit100; `checkh(arr4[0], 4'b0001); { << bit {arr4} } = bit100; `checkh(arr4[0], 4'b1000); bit320 = { >> byte {arr64} }; `checkh(bit320[63:0], 64'h0123456789abcdef); bit320 = { << byte {arr64} }; `checkh(bit320[63:0], 64'hefcdab8967452301); { >> byte {arr64} } = bit320; `checkh(arr64[0], 64'hefcdab8967452301); { << byte {arr64} } = bit320; `checkh(arr64[0], 64'h0123456789abcdef); { >> bit {arr64} } = bit64; `checkh(arr64[0], 64'hcccccccccccccccc); { << bit {arr64} } = bit64; `checkh(arr64[0], 64'h3333333333333333); bit64 = { >> bit {arr64} }; `checkh(bit64, 64'h3333333333333333); bit64 = { << bit {arr64} }; `checkh(bit64, 64'hcccccccccccccccc); bit320 = { >> byte {arr160} }; `checkh(bit320[159:0], 160'h0123456789abcdef0123456789abcdef01234567); bit320 = { << byte {arr160} }; `checkh(bit320[159:0], 160'h67452301efcdab8967452301efcdab8967452301); { >> byte {arr160} } = bit320; `checkh(arr160[0], 160'h67452301efcdab8967452301efcdab8967452301); { << byte {arr160} } = bit320; `checkh(arr160[0], 160'h0123456789abcdef0123456789abcdef01234567); endtask task test2; byte unpack [8]; // [0] is left-most for purposes of streaming bit [63:0] bits; // [63] is left-most for purposes of streaming longint word; // [63] is left-most for purposes of streaming // Using packed bits $display("Test2"); bits = {8'hfa, 8'hde, 8'hca, 8'hfe, 8'hde, 8'had, 8'hbe, 8'hef}; word = {>>{bits}}; `checkh(word, 64'hfadecafedeadbeef); word = {<<8{bits}}; `checkh(word, 64'hefbeaddefecadefa); // Using byte unpacked array unpack = '{8'hfa, 8'hde, 8'hca, 8'hfe, 8'hde, 8'had, 8'hbe, 8'hef}; `checkh(unpack[0], 8'hfa); `checkh(unpack[7], 8'hef); word = {>>{unpack}}; `checkh(word, 64'hfadecafedeadbeef); word = {<<8{unpack}}; `checkh(word, 64'hefbeaddefecadefa); endtask task test3; byte dyn8 []; // [0] is left-most for purposes of streaming longint word; // [63] is left-most for purposes of streaming // verilator lint_off ASCRANGE bit [0:63] rbits; // [63] is still left-most for purposes of streaming // verilator lint_on ASCRANGE // Using byte dynamic array dyn8 = new[8]('{8'hfa, 8'hde, 8'hca, 8'hfe, 8'hde, 8'had, 8'hbe, 8'hef}); `checkh(dyn8[0], 8'hfa); `checkh(dyn8[7], 8'hef); word = {>>{dyn8}}; `checkh(word, 64'hfadecafedeadbeef); word = {<<1{dyn8}}; `checkh(word, 64'hf77db57b7f537b5f); word = {<<8{dyn8}}; `checkh(word, 64'hefbeaddefecadefa); rbits = {>>{dyn8}}; `checkh(rbits, 64'hfadecafedeadbeef); rbits = {<<1{dyn8}}; `checkh(rbits, 64'hf77db57b7f537b5f); rbits = {<<8{dyn8}}; `checkh(rbits, 64'hefbeaddefecadefa); endtask initial begin; test1(); test2(); test3(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_preproc_ifexpr.v0000644000542200017500000000363515101701376022636 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `begin_keywords "1800-2023" `define ONE `undef ZERO `ifdef ( ONE ) "ok ( ONE )" `endif // Test no spaces around () `ifdef (ZERO) `error "( ZERO )" `endif `ifndef ( ! ONE ) "ok ( ! ONE )" `endif // Test no spaces around () `ifndef (!ZERO) `error "( ! ZERO )" `endif `ifdef ( ! ZERO ) "ok ( ! ZERO )" `endif `ifdef ( ! ONE ) `error "( ! ONE )" `endif `ifdef ( ZERO || ZERO || ONE ) "ok ( ZERO || ZERO || ONE )" `endif `ifdef ( ZERO || ZERO || ZERO ) `error "( ZERO || ZERO || ZERO )" `endif `ifdef ( ONE && ONE && ONE ) "ok ( ONE && ONE && ONE )" `endif `ifdef ( ONE && ONE && ZERO ) `error "( ONE && ONE && ZERO )" `endif // Precedence of && is under || `ifdef ( ZERO && ZERO || ONE ) "ok ( ZERO && ZERO || ONE )" `endif `ifdef ( ONE || ZERO && ZERO ) "ok ( ONE || ZERO && ZERO )" `endif `ifdef ZERO `elsif ( ONE && !( ZERO && ONE ) ) "ok ( ONE && !( ZERO && ONE ) )" `endif `ifdef ( ZERO -> ZERO) "ok ( ZERO -> ZERO)" `endif // Text extra newlines `ifdef ( ZERO -> ONE) "ok ( ZERO -> ONE)" `endif // Text comments `ifdef ( ZERO // Zero -> // Operator ONE) // One "ok ( ZERO -> ONE)" `endif `ifdef ( /*val*/ ZERO /*op*/ -> /*val*/ ONE) "ok ( ZERO -> ONE)" `endif `ifndef ( ONE -> ZERO) "ok ( ONE -> ZERO)" `endif `ifdef ( ONE -> ONE) "ok ( ONE -> ONE)" `endif `ifdef ( ZERO <-> ZERO) "ok ( ZERO <-> ZERO)" `endif `ifndef ( ZERO <-> ONE) "ok ( ZERO <-> ONE)" `endif `ifndef ( ONE <-> ZERO) "ok ( ONE <-> ZERO)" `endif `ifdef ( ONE <-> ONE) "ok ( ONE <-> ONE)" `endif `ifdef (ZERO) "bad" `elsif (ZERO) "bad" `elsif (ONE) "ok " `elsif (ONE) "bad" `endif // Did we end up right? Line: `__LINE__ verilator-5.042/test_regress/t/t_lib_prot_secret.v0000644000542200017500000000661215101701376022764 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 module secret #(parameter GATED_CLK = 0) ( input [31:0] accum_in, output wire [31:0] accum_out, input accum_bypass, output [31:0] accum_bypass_out, input s1_in, output logic s1_out, input s1up_in[2], output logic s1up_out[2], input [1:0] s2_in, output logic [1:0] s2_out, input [7:0] s8_in, output logic [7:0] s8_out, input [32:0] s33_in, output logic [32:0] s33_out, input [63:0] s64_in, output logic [63:0] s64_out, input [64:0] s65_in, output logic [64:0] s65_out, input [128:0] s129_in, output logic [128:0] s129_out, input [3:0] [31:0] s4x32_in, output logic [3:0] [31:0] s4x32_out, /*verilator lint_off ASCRANGE*/ input [0:15] s6x16up_in[0:1][2:0], output logic [0:15] s6x16up_out[0:1][2:0], /*verilator lint_on ASCRANGE*/ input [15:0] s8x16up_in[1:0][0:3], output logic [15:0] s8x16up_out[1:0][0:3], input [15:0] s8x16up_3d_in[1:0][0:1][0:1], output logic [15:0] s8x16up_3d_out[1:0][0:1][0:1], input clk_en, input clk); logic [31:0] secret_accum_q = 0; logic [31:0] secret_value = 7; initial $display("created %m"); logic the_clk; generate if (GATED_CLK != 0) begin: yes_gated_clock logic clk_en_latch; /* verilator lint_off COMBDLY */ /* verilator lint_off LATCH */ always_comb if (clk == '0) clk_en_latch <= clk_en; /* verilator lint_on LATCH */ /* verilator lint_on COMBDLY */ assign the_clk = clk & clk_en_latch; end else begin: no_gated_clock assign the_clk = clk; end endgenerate always @(posedge the_clk) begin secret_accum_q <= secret_accum_q + accum_in + secret_value; end // Test combinatorial paths of different sizes always @(*) begin s1_out = s1_in; s1up_out = s1up_in; s2_out = s2_in; s8_out = s8_in; s64_out = s64_in; s65_out = s65_in; s129_out = s129_in; s4x32_out = s4x32_in; end for (genvar i = 0; i < 3; ++i) begin assign s6x16up_out[0][i] = s6x16up_in[0][i]; assign s6x16up_out[1][i] = s6x16up_in[1][i]; end for (genvar i = 0; i < 4; ++i) begin assign s8x16up_out[0][i] = s8x16up_in[0][i]; assign s8x16up_out[1][i] = s8x16up_in[1][i]; end for (genvar i = 0; i < 8; ++i) begin assign s8x16up_3d_out[i[2]][i[1]][i[0]] = s8x16up_3d_in[i[2]][i[1]][i[0]]; end sub sub (.sub_in(s33_in), .sub_out(s33_out)); // Test sequential path assign accum_out = secret_accum_q; // Test mixed combinatorial/sequential path assign accum_bypass_out = accum_bypass ? accum_in : secret_accum_q; final $display("destroying %m"); endmodule module sub ( input [32:0] sub_in, output [32:0] sub_out); /*verilator no_inline_module*/ assign sub_out = sub_in; endmodule verilator-5.042/test_regress/t/t_time_literals.v0000644000542200017500000000173715101701376022445 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under The Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `timescale 1ns/1ps module t; time t; // realtime value scaled to timeunit, rounded to timeprecision initial begin // verilator lint_off REALCVT t = 1s; `checkd(t, 64'd1000000000); t = 2ms; `checkd(t, 2000000); t = 1ms; `checkd(t, 1000000); t = 1us; `checkd(t, 1000); t = 1ns; `checkd(t, 1); t = 1ps; `checkd(t, 0); // Below precision t = 1fs; `checkd(t, 0); t = 2.3ps; `checkd(t, 0); t = 2.4us; `checkd(t, 2400); // verilator lint_on REALCVT $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_profcfunc.py0000755000542200017500000000131515101701376021753 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') test.run(cmd=[ "cd " + test.obj_dir + " && " + os.environ["VERILATOR_ROOT"] + "/bin/verilator_profcfunc", test.t_dir + "/t_profcfunc.gprof > profcfuncs.log" ], check_finished=False) test.files_identical(test.obj_dir + "/profcfuncs.log", test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_unopt_combo_isolate.vlt0000644000542200017500000000070715101701376024210 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. // SPDX-License-Identifier: CC0-1.0 `verilator_config isolate_assignments -module "file" -var "b" isolate_assignments -module "file" -task "set_b_d" -var "t_c*" isolate_assignments -module "file" -function "get_31_16" -var "t_crc" isolate_assignments -module "file" -function "get_31_16" verilator-5.042/test_regress/t/t_inst_missing.v0000644000542200017500000000117115101701376022306 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; wire ok = 1'b0; // verilator lint_off UNDRIVEN wire nc; // verilator lint_on UNDRIVEN // verilator lint_off PINNOCONNECT // verilator lint_off PINCONNECTEMPTY sub sub (ok, , nc); // verilator lint_on PINCONNECTEMPTY // verilator lint_on PINNOCONNECT endmodule module sub (input ok, input none, input nc); initial if (ok && none && nc) begin end // No unused warning endmodule verilator-5.042/test_regress/t/t_assert_procedural_clk_bad.py0000755000542200017500000000076315101701376025154 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(expect_filename=test.golden_filename, fails=True) test.passes() verilator-5.042/test_regress/t/t_covergroup_with_sample_zeroargs.v0000644000542200017500000000060615101701376026305 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off COVERIGN */ module t; covergroup cg0 with function sample (); endgroup cg0 cov = new(); function void run(); cov.sample(); endfunction endmodule verilator-5.042/test_regress/t/t_param_noval_bad.out0000644000542200017500000000402715101701376023252 0ustar mahmoudyfreeshell%Error: t/t_param_noval_bad.v:7:22: Parameter without default value is never given value (IEEE 1800-2023 6.20.1): 'P' : ... note: In instance 't' 7 | module t #(parameter P, parameter type T); | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_param_noval_bad.v:7:40: Parameter type without default value is never given value (IEEE 1800-2023 6.20.1): 'T' : ... note: In instance 't' 7 | module t #(parameter P, parameter type T); | ^ %Warning-WIDTHTRUNC: t/t_param_noval_bad.v:10:7: Logical operator GENFOR expects 1 bit on the For Test Condition, but For Test Condition's VARREF 'P' generates 32 bits. : ... note: In instance 't' 10 | for (j=0; P; j++) | ^~~ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: t/t_param_noval_bad.v:10:7: Non-genvar used in generate for: 'j' : ... note: In instance 't' 10 | for (j=0; P; j++) | ^~~ %Error: t/t_param_noval_bad.v:10:7: Loop unrolling failed. : ... note: In instance 't' 10 | for (j=0; P; j++) | ^~~ %Error-UNSUPPORTED: t/t_param_noval_bad.v:10:7: Unsupported: Can't unroll generate for; Unable to unroll loop : ... note: In instance 't' 10 | for (j=0; P; j++) | ^~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: t/t_param_noval_bad.v:10:7: For loop doesn't have genvar index, or is malformed : ... note: In instance 't' 10 | for (j=0; P; j++) | ^~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_class_const.v0000644000542200017500000000074515101701376022121 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls; const int aconst = 10; static const int astatic = 20; endclass module t; initial begin Cls c = new; if (c.aconst !== 10) $stop; if (Cls::astatic !== 20) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_case_call_count.v0000644000542200017500000000212615101701376022717 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Cls; int callCount = 0; int callCount2 = 0; int value = 6; bit[5:0] value2 = 6; function int get(); callCount += 1; return value; endfunction function bit[5:0] get2(); callCount2 += 1; return value2; endfunction function int getPure(); return callCount2; endfunction endclass module t; Cls c; initial begin bit called = 0; c = new; case (c.get()) 4: $stop; 5: $stop; 6: called = 1; 7: $stop; default: $stop; endcase if (!called) $stop; if (c.callCount != 1) $stop; called = 0; case (c.get2()) 4: $stop; 5: $stop; 6: called = 1; 7: $stop; default: $stop; endcase case (c.getPure()) 1:; default: $stop; endcase if (!called) $stop; if (c.callCount2 != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_interface_generic_bad2.out0000755000542200017500000000251515101701376024474 0ustar mahmoudyfreeshell%Error: t/t_interface_generic_bad2.v:15:9: Can't find definition of scope/variable: 'b' 15 | if (b.k != 9) $stop; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_interface_generic_bad2.v:20:3: Cannot find file containing interface: 'inf' 20 | inf inf_inst(); | ^~~ %Error: t/t_interface_generic_bad2.v:21:32: Found definition of 'inf_inst' as a CELL but expected a variable 21 | GenericModule genericModule (inf_inst); | ^~~~~~~~ %Error: t/t_interface_generic_bad2.v:21:32: Expected an interface but 'inf_inst' is not an interface 21 | GenericModule genericModule (inf_inst); | ^~~~~~~~ %Error: t/t_interface_generic_bad2.v:23:5: Dotted reference to instance that refers to missing module/interface: 'inf' 23 | inf_inst.v = 7; | ^~~~~~~~ %Error: t/t_interface_generic_bad2.v:23:14: Can't find definition of 'v' in dotted variable/method: 'inf_inst.v' 23 | inf_inst.v = 7; | ^ %Error: t/t_interface_generic_bad2.v:24:5: Can't find definition of scope/variable: 'inf_inst2' : ... Suggested alternative: 'inf_inst' 24 | inf_inst2.k = 9; | ^~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_dpi_imp_gen_c.cpp0000644000542200017500000000221715101701376022673 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // Copyright 2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 //************************************************************************* #include "svdpi.h" #include #include //====================================================================== // clang-format off #if defined(VERILATOR) # include "Vt_dpi_imp_gen__Dpi.h" #elif defined(VCS) # include "../vc_hdrs.h" #elif defined(CADENCE) # define NEED_EXTERNS #else # error "Unknown simulator for DPI test" #endif // clang-format on #ifdef NEED_EXTERNS extern "C" { extern void dpi_genvarTest(); } #endif //====================================================================== // Called from our Verilog code to run the tests void dpi_genvarTest() { const char* scopeName = svGetNameFromScope(svGetScope()); printf("scope name : %s\n", scopeName); } verilator-5.042/test_regress/t/t_bitsel_over32.v0000644000542200017500000000207515101701376022266 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(aw_addr, orig_aw_size); typedef logic [63:0] addr_t; typedef logic [7:0][7:0] mst_data_t; logic [127:0] slv_req_i_w_data; input addr_t aw_addr; mst_data_t w_data; input logic [2:0] orig_aw_size; always_comb begin // verilator lint_off WIDTHEXPAND automatic addr_t mst_port_offset = aw_addr[2:0]; automatic addr_t slv_port_offset = aw_addr[3:0]; w_data = '0; for (int b=0; b<16; b++) begin if ((b >= slv_port_offset) && (b - slv_port_offset < (1 << orig_aw_size)) && (b + mst_port_offset - slv_port_offset < 8)) begin automatic addr_t index = b + mst_port_offset - slv_port_offset; // verilator lint_on WIDTHEXPAND // [#][7:0] = [ +: 8] w_data[index] = slv_req_i_w_data[8*b +: 8]; end end end endmodule verilator-5.042/test_regress/t/t_probdist.v0000644000542200017500000000550015101701376021426 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t; integer seed; integer r; integer sum; initial begin //======= seed = 1234; r = $dist_chi_square(seed, 5); `checkd(seed, 923940542); `checkd(r, 8); sum = 1; repeat(20) sum += $dist_chi_square(seed, 5); `checkd(sum, 130); sum = 1; repeat(20) sum += $dist_chi_square(seed, -5); `checkd(sum, 1); sum = 1; repeat(20) sum += $dist_chi_square(seed, 2); `checkd(sum, 30); //======= seed = 1234; r = $dist_erlang(seed, 5, 10); `checkd(seed, 1025211431); `checkd(r, 19); sum = 1; repeat(20) sum += $dist_erlang(seed, 5, 10); `checkd(sum, 173); sum = 1; repeat(20) sum += $dist_erlang(seed, 5, -10); `checkd(sum, -241); //======= seed = 1234; r = $dist_exponential(seed, 5); `checkd(seed, 85231147); `checkd(r, 20); sum = 1; repeat(20) sum += $dist_exponential(seed, 5); `checkd(sum, 104); //======= seed = 1234; r = $dist_normal(seed, 5, 10); `checkd(seed, -1570070672); `checkd(r, 4); sum = 1; repeat(20) sum += $dist_normal(seed, 5, 10); `checkd(sum, 114); //======= seed = 1234; r = $dist_poisson(seed, 5); `checkd(seed, 418012337); `checkd(r, 2); sum = 1; repeat(20) sum += $dist_poisson(seed, 5); `checkd(sum, 111); //======= seed = 1234; r = $dist_t(seed, 5); `checkd(seed, -797481412); `checkd(r, 0); sum = 1; repeat(20) sum += $dist_t(seed, 5); `checkd(sum, -2); //======= seed = 1234; r = $dist_uniform(seed, 5, 10); `checkd(seed, 85231147); `checkd(r, 5); sum = 1; repeat(20) sum += $dist_uniform(seed, 5, 10); `checkd(sum, 147); seed = 1234; r = $dist_uniform(seed, 10, 5); `checkd(r, 10); sum = 1; repeat(20) sum += $dist_uniform(seed, -2147483648, -20); `checkd(sum, 1768955681); sum = 1; repeat(20) sum += $dist_uniform(seed, 20, 2147483647); `checkd(sum, 1534326415); sum = 1; repeat(20) sum += $dist_uniform(seed, -2147483648, 2147483647); `checkd(sum, 1394525852); seed = 0; sum = 1; repeat(20) sum += $dist_uniform(seed, -10, 100); `checkd(seed, 1003647461); `checkd(sum, 896); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_lint_sideeffect_bad.v0000644000542200017500000000075715101701376023546 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 Krzysztof Boronski. // SPDX-License-Identifier: CC0-1.0 int i = 0; function int postincrement_i; return i++; endfunction module t; initial begin int arr [3][3] = {{1, 2, 3}, {4, 5, 6}, {7, 8, 9}}; i = 0; arr[postincrement_i()][postincrement_i()]++; $display("Value: %d", i); end endmodule verilator-5.042/test_regress/t/t_func_regfirst.py0000755000542200017500000000073415101701376022632 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_dpi_result_type.py0000755000542200017500000000244115101701376023202 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if test.nc: # For NC, compile twice, first just to generate DPI headers test.compile(nc_flags2=[ "+ncdpiheader+" + test.obj_dir + "/dpi-exp.h", "+ncdpiimpheader+" + test.obj_dir + "/dpi-imp.h" ]) test.compile( v_flags2=["t/" + test.name + ".cpp"], # --no-decoration so .out file doesn't comment on source lines verilator_flags2=["-Wall -Wno-DECLFILENAME --no-decoration"], # NC: Gdd the obj_dir to the C include path nc_flags2=["+ncscargs+-I" + test.obj_dir], # ModelSim: Generate DPI header, add obj_dir to the C include path ms_flags2=["-dpiheader " + test.obj_dir + "/dpi.h", "-ccflags -I" + test.obj_dir]) if test.vlt_all: test.files_identical(test.obj_dir + "/" + test.vm_prefix + "__Dpi.h", "t/" + test.name + "__Dpi.out") test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_initial_edge.py0000755000542200017500000000100115101701376022373 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--x-initial-edge"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_assert_disable_bad.v0000644000542200017500000000130115101701376023365 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; int cyc = 0; logic val = 0; always @(posedge clk) begin cyc <= cyc + 1; val = ~val; end property check(int cyc_mod_2, logic expected); @(posedge clk) disable iff (cyc == 0) cyc % 2 == cyc_mod_2 |=> val == expected; endproperty // Test should fail due to duplicated disable iff statements // (IEEE 1800-2012 16.12.1). assert property (disable iff (val == 0) check(1, 1)); endmodule verilator-5.042/test_regress/t/t_parse_sync_bad2.out0000644000542200017500000000234015101701376023177 0ustar mahmoudyfreeshell%Error: t/t_parse_sync_bad2.v:9:15: Can't find typedef/interface: 'unknown' 9 | typedef unknown defu; | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_parse_sync_bad2.v:17:7: Can't find typedef/interface: 'Invalid1' 17 | Invalid1 invalid1; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_parse_sync_bad2.v:18:12: Unsupported: Multiple '::' package/class reference 18 | pkg::cls::defi valid1; | ^~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: t/t_parse_sync_bad2.v:18:17: Can't find typedef/interface: 'defi' 18 | pkg::cls::defi valid1; | ^~~~ %Error-UNSUPPORTED: t/t_parse_sync_bad2.v:19:12: Unsupported: Multiple '::' package/class reference 19 | pkg::cls::defu valid2; | ^~~ %Error: t/t_parse_sync_bad2.v:19:17: Can't find typedef/interface: 'defu' 19 | pkg::cls::defu valid2; | ^~~~ %Error: t/t_parse_sync_bad2.v:20:7: Can't find typedef/interface: 'Invalid2' 20 | Invalid2 invalid2; | ^~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_func_under.py0000755000542200017500000000073415101701376022122 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_queue_slice.v0000644000542200017500000000740515101701376022111 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); module t; initial begin typedef string q_t[$]; q_t q; string v; int i; int qi[$:5]; int ri[$]; q.push_front("non-empty"); i = q.size(); `checkh(i, 1); `checkp(q, "'{\"non-empty\"}"); q = '{}; i = q.size(); `checkh(i, 0); q = '{"q"}; `checkp(q, "'{\"q\"}"); q = {}; i = q.size(); `checkh(i, 0); q = '{"q", "b", "c", "d", "e", "f"}; if (q[0] !== "q") $stop; `checkp(q, "'{\"q\", \"b\", \"c\", \"d\", \"e\", \"f\"}"); q = {"q", "b", "c", "d", "e", "f"}; `checkp(q, "'{\"q\", \"b\", \"c\", \"d\", \"e\", \"f\"}"); q.delete(1); v = q[1]; `checks(v, "c"); `checkp(q, "'{\"q\", \"c\", \"d\", \"e\", \"f\"}"); q.insert(0, "ins0"); q.insert(2, "ins2"); v = q[0]; `checks(v, "ins0"); v = q[2]; `checks(v, "ins2"); `checkp(q, "'{\"ins0\", \"q\", \"ins2\", \"c\", \"d\", \"e\", \"f\"}"); // Slicing q = '{"q", "b", "c", "d", "e", "f"}; q = q[-1:0]; `checkp(q, "'{\"q\"}"); q = '{"q", "b", "c", "d", "e", "f"}; q = q[2:3]; `checkp(q, "'{\"c\", \"d\"}"); q = '{"q", "b", "c", "d", "e", "f"}; q = q[3:$]; `checkp(q, "'{\"d\", \"e\", \"f\"}"); q = q[$:$]; `checkp(q, "'{\"f\"}"); // Similar using implied notation q = '{"f"}; q = {q, "f1"}; // push_front q = {q, "f2"}; // push_front q = {"b1", q}; // push_back q = {"b2", q}; // push_back `checkp(q, "'{\"b2\", \"b1\", \"f\", \"f1\", \"f2\"}"); q = {q[0], q[2:$]}; // delete element 1 `checkp(q, "'{\"b2\", \"f\", \"f1\", \"f2\"}"); q = {"a", "b"}; q = {q, q}; `checkp(q, "'{\"a\", \"b\", \"a\", \"b\"}"); begin string ai[$] = '{ "Foo", "Bar" }; q = ai; // Copy i = q.size(); `checkh(i, 2); v = q.pop_front(); `checks(v, "Foo"); v = q.pop_front(); `checks(v, "Bar"); q = '{ "BB", "CC" }; // Note '{} not {} v = q.pop_front(); `checks(v, "BB"); v = q.pop_front(); `checks(v, "CC"); q = { "BB", "CC" }; // Note {} not '{} v = q.pop_front(); `checks(v, "BB"); v = q.pop_front(); `checks(v, "CC"); end begin qi.push_back(0); qi.push_back(1); qi.push_back(2); qi.push_back(3); qi.push_back(4); qi.push_back(5); // Assignment to unsized queue from sized queue ri = qi[ 2 : 4 ]; `checkh(ri.size, 3); ri = qi[ 4 : 2 ]; `checkh(ri.size, 0); ri = qi[ 2 : 2 ]; `checkh(ri.size, 1); ri = qi[ -2 : 2 ]; // 2 - 0 + 1 = 3 `checkh(ri.size, 3); ri = qi[ 2 : 10 ]; // 5 - 2 + 1 = 4 `checkh(ri.size, 4); // Assignment from unsized to sized ri = '{1,2,3,4,5,6,7,8,9}; qi = ri; `checkh(qi.size, 5); end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_func_sel.v0000644000542200017500000000306215101701376021377 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // The code as shown applies a random vector to the Test // module, then calculates a CRC on the Test module's outputs. // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; parameter W = 104; integer cyc = 0; reg [63:0] crc; reg [127:0] sum; wire [127:0] result; wire [103:0] in; reg [103:0] out; assign in = {crc[39:0], crc[63:0]}; always @(posedge clk) begin out <= reverse(in); end assign result = {24'h0, out }; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x in=%x out=%x\n", $time, cyc, crc, result, in, out); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= {sum[127:1], 1'b0} + result; if (cyc < 10) begin crc <= 1; sum <= '0; end else if (cyc >= 90) begin $display("SUM = %x_%x_%x_%x", sum[127:96], sum[95:64], sum[63:32], sum[31:0]); `define EXPECTED_SUM 128'h00002d36_42d1a346_8d1a5936_42d1a319 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end function [W-1:0] reverse(input [W-1:0] val); integer i; // Bug workaround: reverse = '0; for (i = 0; i < W; i = i + 1) reverse[W-1-i] = val[i]; endfunction endmodule verilator-5.042/test_regress/t/t_table_fsm.v0000644000542200017500000001062615101701376021541 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; reg reset; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire myevent; // From test of Test.v wire myevent_pending; // From test of Test.v wire [1:0] state; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .state (state[1:0]), .myevent (myevent), .myevent_pending (myevent_pending), // Inputs .clk (clk), .reset (reset)); // Aggregate outputs into a single result vector wire [63:0] result = {60'h0, myevent_pending,myevent,state}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x me=%0x mep=%x\n", $time, cyc, crc, result, myevent, myevent_pending); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; reset <= (cyc<2); if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h4e93a74bd97b25ef if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs state, myevent, myevent_pending, // Inputs clk, reset ); input clk; input reset; output [1:0] state; output myevent; output myevent_pending; reg [5:0] count = 0; always @ (posedge clk) if (reset) count <= 0; else count <= count + 1; reg myevent = 1'b0; always @ (posedge clk) myevent <= (count == 6'd27); reg myevent_done; reg hickup_ready; reg hickup_done; localparam STATE_ZERO = 0; localparam STATE_ONE = 1; localparam STATE_TWO = 2; reg [1:0] state = STATE_ZERO; reg state_start_myevent = 1'b0; reg state_start_hickup = 1'b0; reg myevent_pending = 1'b0; always @ (posedge clk) begin state <= state; myevent_pending <= myevent_pending || myevent; state_start_myevent <= 1'b0; state_start_hickup <= 1'b0; case (state) STATE_ZERO: if (myevent_pending) begin state <= STATE_ONE; myevent_pending <= 1'b0; state_start_myevent <= 1'b1; end else if (hickup_ready) begin state <= STATE_TWO; state_start_hickup <= 1'b1; end STATE_ONE: if (myevent_done) state <= STATE_ZERO; STATE_TWO: if (hickup_done) state <= STATE_ZERO; default: ; /* do nothing */ endcase end reg [3:0] myevent_count = 0; always @ (posedge clk) if (state_start_myevent) myevent_count <= 9; else if (myevent_count > 0) myevent_count <= myevent_count - 1; initial myevent_done = 1'b0; always @ (posedge clk) myevent_done <= (myevent_count == 0); reg [4:0] hickup_backlog = 2; always @ (posedge clk) if (state_start_myevent) hickup_backlog <= hickup_backlog - 1; else if (state_start_hickup) hickup_backlog <= hickup_backlog + 1; initial hickup_ready = 1'b1; always @ (posedge clk) hickup_ready <= (hickup_backlog < 3); reg [3:0] hickup_count = 0; always @ (posedge clk) if (state_start_hickup) hickup_count <= 10; else if (hickup_count > 0) hickup_count <= hickup_count - 1; initial hickup_done = 1'b0; always @ (posedge clk) hickup_done <= (hickup_count == 1); endmodule verilator-5.042/test_regress/t/t_lint_restore_prag_bad.py0000755000542200017500000000076315101701376024324 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_alias_tristate_unsup.py0000755000542200017500000000077615101701376024242 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_func_noinl.v0000644000542200017500000000566415101701376021745 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; wire [31:0] inp = crc[31:0]; wire reset = (cyc < 5); /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [31:0] outp; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .outp (outp[31:0]), // Inputs .reset (reset), .clk (clk), .inp (inp[31:0])); // Aggregate outputs into a single result vector wire [63:0] result = {32'h0, outp}; // What checksum will we end up with `define EXPECTED_SUM 64'ha7f0a34f9cf56ccb // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs outp, // Inputs reset, clk, inp ); input reset; input clk; input [31:0] inp; output [31:0] outp; function automatic [31:0] no_inline_function; input [31:0] var1; input [31:0] var2; /*verilator no_inline_task*/ reg [31*2:0] product1 ; reg [31*2:0] product2 ; integer i; reg [31:0] tmp; begin product2 = {(31*2+1){1'b0}}; for (i = 0; i < 32; i = i + 1) if (var2[i]) begin product1 = { {31*2+1-32{1'b0}}, var1} << i; product2 = product2 ^ product1; end no_inline_function = 0; for (i= 0; i < 31; i = i + 1 ) no_inline_function[i+1] = no_inline_function[i] ^ product2[i] ^ var1[i]; end endfunction reg [31:0] outp; reg [31:0] inp_d; always @( posedge clk ) begin if( reset ) begin outp <= 0; end else begin inp_d <= inp; outp <= no_inline_function(inp, inp_d); end end endmodule verilator-5.042/test_regress/t/t_preproc_persist.out0000644000542200017500000000014515101701376023365 0ustar mahmoudyfreeshellInside "t/t_preproc_persist.v". Inside "t/t_preproc_persist_inc.v". Inside "t/t_preproc_persist2.v". verilator-5.042/test_regress/t/t_uniqueif.py0000755000542200017500000000102015101701376021604 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--assert'], nc_flags2=['+assert']) test.execute() test.passes() verilator-5.042/test_regress/t/t_flag_bboxsys.v0000644000542200017500000000074515101701376022270 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg a; initial begin $unknown_sys_task_call_to_be_bbox("blah"); $unkown_sys_task_call_noarg; a = $unknown_sys_func_call(23); a = $unknown_sys_func_call_noarg; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_class_extends_aliased_real_bad.out0000644000542200017500000000054015101701376026273 0ustar mahmoudyfreeshell%Error: t/t_class_extends_aliased_real_bad.v:14:10: Attempting to extend using non-class : ... note: In instance 't' 14 | bar #(real_t) bar_real_t; | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_param_up_bad.out0000644000542200017500000000041615101701376022555 0ustar mahmoudyfreeshell%Error: t/t_param_up_bad.v:16:19: Can't find definition of scope/variable: 'bar' 16 | assign a_bad = bar.foo; | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_trace_cat_renew.out0000644000542200017500000001745015101701376023276 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $date Sat Feb 23 20:18:07 2013 $end $timescale 1ps $end $scope module top $end $var wire 1 $ clk $end $scope module t $end $var wire 1 $ clk $end $var wire 32 # cyc [31:0] $end $upscope $end $upscope $end $enddefinitions $end #0 b00000000000000000000000000000001 # 1$ #1 0$ #2 b00000000000000000000000000000010 # 1$ #3 0$ #4 b00000000000000000000000000000011 # 1$ #5 0$ #6 b00000000000000000000000000000100 # 1$ #7 0$ #8 b00000000000000000000000000000101 # 1$ #9 0$ #10 b00000000000000000000000000000110 # 1$ #11 0$ #12 b00000000000000000000000000000111 # 1$ #13 0$ #14 b00000000000000000000000000001000 # 1$ #15 0$ #16 b00000000000000000000000000001001 # 1$ #17 0$ #18 b00000000000000000000000000001010 # 1$ #19 0$ #20 b00000000000000000000000000001011 # 1$ #21 0$ #22 b00000000000000000000000000001100 # 1$ #23 0$ #24 b00000000000000000000000000001101 # 1$ #25 0$ #26 b00000000000000000000000000001110 # 1$ #27 0$ #28 b00000000000000000000000000001111 # 1$ #29 0$ #30 b00000000000000000000000000010000 # 1$ #31 0$ #32 b00000000000000000000000000010001 # 1$ #33 0$ #34 b00000000000000000000000000010010 # 1$ #35 0$ #36 b00000000000000000000000000010011 # 1$ #37 0$ #38 b00000000000000000000000000010100 # 1$ #39 0$ #40 b00000000000000000000000000010101 # 1$ #41 0$ #42 b00000000000000000000000000010110 # 1$ #43 0$ #44 b00000000000000000000000000010111 # 1$ #45 0$ #46 b00000000000000000000000000011000 # 1$ #47 0$ #48 b00000000000000000000000000011001 # 1$ #49 0$ #50 b00000000000000000000000000011010 # 1$ #51 0$ #52 b00000000000000000000000000011011 # 1$ #53 0$ #54 b00000000000000000000000000011100 # 1$ #55 0$ #56 b00000000000000000000000000011101 # 1$ #57 0$ #58 b00000000000000000000000000011110 # 1$ #59 0$ #60 b00000000000000000000000000011111 # 1$ #61 0$ #62 b00000000000000000000000000100000 # 1$ #63 0$ #64 b00000000000000000000000000100001 # 1$ #65 0$ #66 b00000000000000000000000000100010 # 1$ #67 0$ #68 b00000000000000000000000000100011 # 1$ #69 0$ #70 b00000000000000000000000000100100 # 1$ #71 0$ #72 b00000000000000000000000000100101 # 1$ #73 0$ #74 b00000000000000000000000000100110 # 1$ #75 0$ #76 b00000000000000000000000000100111 # 1$ #77 0$ #78 b00000000000000000000000000101000 # 1$ #79 0$ #80 b00000000000000000000000000101001 # 1$ #81 0$ #82 b00000000000000000000000000101010 # 1$ #83 0$ #84 b00000000000000000000000000101011 # 1$ #85 0$ #86 b00000000000000000000000000101100 # 1$ #87 0$ #88 b00000000000000000000000000101101 # 1$ #89 0$ #90 b00000000000000000000000000101110 # 1$ #91 0$ #92 b00000000000000000000000000101111 # 1$ #93 0$ #94 b00000000000000000000000000110000 # 1$ #95 0$ #96 b00000000000000000000000000110001 # 1$ #97 0$ #98 b00000000000000000000000000110010 # 1$ #99 0$ #100 b00000000000000000000000000110011 # 1$ #101 0$ #102 b00000000000000000000000000110100 # 1$ #103 0$ #104 b00000000000000000000000000110101 # 1$ #105 0$ #106 b00000000000000000000000000110110 # 1$ #107 0$ #108 b00000000000000000000000000110111 # 1$ #109 0$ #110 b00000000000000000000000000111000 # 1$ #111 0$ #112 b00000000000000000000000000111001 # 1$ #113 0$ #114 b00000000000000000000000000111010 # 1$ #115 0$ #116 b00000000000000000000000000111011 # 1$ #117 0$ #118 b00000000000000000000000000111100 # 1$ #119 0$ #120 b00000000000000000000000000111101 # 1$ #121 0$ #122 b00000000000000000000000000111110 # 1$ #123 0$ #124 b00000000000000000000000000111111 # 1$ #125 0$ #126 b00000000000000000000000001000000 # 1$ #127 0$ #128 b00000000000000000000000001000001 # 1$ #129 0$ #130 b00000000000000000000000001000010 # 1$ #131 0$ #132 b00000000000000000000000001000011 # 1$ #133 0$ #134 b00000000000000000000000001000100 # 1$ #135 0$ #136 b00000000000000000000000001000101 # 1$ #137 0$ #138 b00000000000000000000000001000110 # 1$ #139 0$ #140 b00000000000000000000000001000111 # 1$ #141 0$ #142 b00000000000000000000000001001000 # 1$ #143 0$ #144 b00000000000000000000000001001001 # 1$ #145 0$ #146 b00000000000000000000000001001010 # 1$ #147 0$ #148 b00000000000000000000000001001011 # 1$ #149 0$ #150 b00000000000000000000000001001100 # 1$ #151 0$ #152 b00000000000000000000000001001101 # 1$ #153 0$ #154 b00000000000000000000000001001110 # 1$ #155 0$ #156 b00000000000000000000000001001111 # 1$ #157 0$ #158 b00000000000000000000000001010000 # 1$ #159 0$ #160 b00000000000000000000000001010001 # 1$ #161 0$ #162 b00000000000000000000000001010010 # 1$ #163 0$ #164 b00000000000000000000000001010011 # 1$ #165 0$ #166 b00000000000000000000000001010100 # 1$ #167 0$ #168 b00000000000000000000000001010101 # 1$ #169 0$ #170 b00000000000000000000000001010110 # 1$ #171 0$ #172 b00000000000000000000000001010111 # 1$ #173 0$ #174 b00000000000000000000000001011000 # 1$ #175 0$ #176 b00000000000000000000000001011001 # 1$ #177 0$ #178 b00000000000000000000000001011010 # 1$ #179 0$ #180 b00000000000000000000000001011011 # 1$ #181 0$ #182 b00000000000000000000000001011100 # 1$ #183 0$ #184 b00000000000000000000000001011101 # 1$ #185 0$ #186 b00000000000000000000000001011110 # 1$ #187 0$ #188 b00000000000000000000000001011111 # 1$ #189 0$ #190 b00000000000000000000000001100000 # 1$ #191 0$ #192 b00000000000000000000000001100001 # 1$ #193 0$ #194 b00000000000000000000000001100010 # 1$ #195 0$ #196 b00000000000000000000000001100011 # 1$ #197 0$ #198 b00000000000000000000000001100100 # 1$ #199 0$ #200 b00000000000000000000000001100101 # 1$ #201 0$ #202 b00000000000000000000000001100110 # 1$ #203 0$ #204 b00000000000000000000000001100111 # 1$ #205 0$ #206 b00000000000000000000000001101000 # 1$ #207 0$ #208 b00000000000000000000000001101001 # 1$ #209 0$ #210 b00000000000000000000000001101010 # 1$ #211 0$ #212 b00000000000000000000000001101011 # 1$ #213 0$ #214 b00000000000000000000000001101100 # 1$ #215 0$ #216 b00000000000000000000000001101101 # 1$ #217 0$ #218 b00000000000000000000000001101110 # 1$ #219 0$ #220 b00000000000000000000000001101111 # 1$ #221 0$ #222 b00000000000000000000000001110000 # 1$ #223 0$ #224 b00000000000000000000000001110001 # 1$ #225 0$ #226 b00000000000000000000000001110010 # 1$ #227 0$ #228 b00000000000000000000000001110011 # 1$ #229 0$ #230 b00000000000000000000000001110100 # 1$ #231 0$ #232 b00000000000000000000000001110101 # 1$ #233 0$ #234 b00000000000000000000000001110110 # 1$ #235 0$ #236 b00000000000000000000000001110111 # 1$ #237 0$ #238 b00000000000000000000000001111000 # 1$ #239 0$ #240 b00000000000000000000000001111001 # 1$ #241 0$ #242 b00000000000000000000000001111010 # 1$ #243 0$ #244 b00000000000000000000000001111011 # 1$ #245 0$ #246 b00000000000000000000000001111100 # 1$ #247 0$ #248 b00000000000000000000000001111101 # 1$ #249 0$ #250 b00000000000000000000000001111110 # 1$ #251 0$ #252 b00000000000000000000000001111111 # 1$ #253 0$ #254 b00000000000000000000000010000000 # 1$ #255 0$ #256 b00000000000000000000000010000001 # 1$ #257 0$ #258 b00000000000000000000000010000010 # 1$ #259 0$ #260 b00000000000000000000000010000011 # 1$ #261 0$ #262 b00000000000000000000000010000100 # 1$ #263 0$ #264 b00000000000000000000000010000101 # 1$ #265 0$ #266 b00000000000000000000000010000110 # 1$ #267 0$ #268 b00000000000000000000000010000111 # 1$ #269 0$ #270 b00000000000000000000000010001000 # 1$ #271 0$ #272 b00000000000000000000000010001001 # 1$ #273 0$ #274 b00000000000000000000000010001010 # 1$ #275 0$ #276 b00000000000000000000000010001011 # 1$ #277 0$ #278 b00000000000000000000000010001100 # 1$ #279 0$ #280 b00000000000000000000000010001101 # 1$ #281 0$ #282 b00000000000000000000000010001110 # 1$ #283 0$ #284 b00000000000000000000000010001111 # 1$ #285 0$ #286 b00000000000000000000000010010000 # 1$ #287 0$ #288 b00000000000000000000000010010001 # 1$ #289 0$ #290 b00000000000000000000000010010010 # 1$ #291 0$ #292 b00000000000000000000000010010011 # 1$ #293 0$ #294 b00000000000000000000000010010100 # 1$ #295 0$ #296 b00000000000000000000000010010101 # 1$ #297 0$ #298 b00000000000000000000000010010110 # 1$ #299 0$ verilator-5.042/test_regress/t/t_clocking_xref.v0000644000542200017500000000202515101701376022414 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module mod; bit clk = 1'b0; bit inp = 1'b0; clocking cb @(posedge clk); input #3 inp; endclocking always @(posedge clk) inp <= 1'b1; always #1 clk = ~clk; endmodule module main; bit clk = 1'b0; bit inp = 1'b0; always begin #2 if (t.mod1.cb.inp != 1'b0) $stop; if (t.main1.cbb.inp != 1'b0) $stop; if (t.main2.cbb.inp != 1'b0) $stop; #4; if (t.mod1.cb.inp != 1'b1) $stop; if (t.main1.cbb.inp != 1'b1) $stop; if (t.main2.cbb.inp != 1'b1) $stop; end clocking cbb @(posedge clk); input #3 inp; endclocking always @(posedge clk) inp <= 1'b1; always #1 clk = ~clk; endmodule module t; main main1(); mod mod1(); main main2(); initial begin #7; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_pp_lib.v0000644000542200017500000000046615101701376021053 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `include "t_pp_lib_inc.vh" module t(); wire [`WIDTH-1:0] a; library_cell n1(a); endmodule verilator-5.042/test_regress/t/t_order_dpi_export_6.cpp0000644000542200017500000000213615101701376023714 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2022 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include #include #include void toggle_other_clk(svBit val) { set_other_clk(val); } int main(int argc, char* argv[]) { VM_PREFIX* const tb = new VM_PREFIX; tb->contextp()->commandArgs(argc, argv); bool clk = true; while (!tb->contextp()->gotFinish()) { // Timeout if (tb->contextp()->time() > 100000) break; // Toggle and set main clock clk = !clk; tb->clk = clk; // Eval tb->eval(); // Advance time tb->contextp()->timeInc(500); } delete tb; return 0; } verilator-5.042/test_regress/t/t_class_extends_rec_bad.v0000644000542200017500000000051315101701376024075 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class RecursiveExtCls extends RecursiveExtCls; int i; endclass module t; RecursiveExtCls cls = new; endmodule verilator-5.042/test_regress/t/t_opt_table_enum.out0000644000542200017500000000027515101701376023143 0ustar mahmoudyfreeshellcyle 0 = 0 cyle 1 = 1 cyle 2 = 2 cyle 3 = 99 cyle 4 = 4 cyle 5 = 5 cyle 6 = 99 cyle 7 = 99 *-* All Finished *-* verilator-5.042/test_regress/t/t_property_untyped.py0000755000542200017500000000077115101701376023427 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--assert']) test.execute() test.passes() verilator-5.042/test_regress/t/t_slice_cond.py0000755000542200017500000000071415101701376022072 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.passes() verilator-5.042/test_regress/t/t_sys_file_zero.py0000755000542200017500000000073415101701376022646 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_param_pattern.v0000644000542200017500000000250215101701376022434 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2021 by Krzysztof Bieganski. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); package config_pkg; typedef struct packed { int UPPER0; int UPPER2; int USE_QUAD0; int USE_QUAD1; int USE_QUAD2; } config_struct_t; endpackage module t; import config_pkg::*; struct_submodule #(.MY_CONFIG('{ UPPER0: 10, UPPER2: 20, USE_QUAD0: 4, USE_QUAD1: 5, USE_QUAD2: 6 })) a_submodule_I (); endmodule module struct_submodule import config_pkg::*; #(parameter config_struct_t MY_CONFIG = '0); initial begin `checkd(MY_CONFIG.UPPER0, 10); `checkd(MY_CONFIG.USE_QUAD0, 4); `checkd(MY_CONFIG.USE_QUAD1, 5); `checkd(MY_CONFIG.USE_QUAD2, 6); `checkd(MY_CONFIG.UPPER2, 20); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_std_process_self.v0000644000542200017500000000075115101701376023144 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class Foo; static task do_something(); `ifdef USE_STD_PREFIX std::process p; `else process p; `endif p = process::self(); endtask endclass module t(); initial begin Foo::do_something(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_struct_port.v0000644000542200017500000000413215101701376022170 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef struct packed { bit b9; byte b1; bit b0; } pack_t; module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs pack_t in; always @* in = crc[9:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) pack_t out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out (out), // Inputs .in (in)); // Aggregate outputs into a single result vector wire [63:0] result = {54'h0, out}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x in=%x result=%x\n", $time, cyc, crc, in, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h99c434d9b08c2a8a if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test ( input pack_t in, output pack_t out); always @* begin out = in; out.b1 = in.b1 + 1; out.b0 = 1'b1; end endmodule // Local Variables: // verilog-typedef-regexp: "_t$" // End: verilator-5.042/test_regress/t/t_lint_didnotconverge_bad.out0000644000542200017500000000025315101701376025010 0ustar mahmoudyfreeshell-V{t#,#} 'stl' region trigger index 0 is active: @([hybrid] a) %Error: t/t_lint_didnotconverge_bad.v:7: Settle region did not converge after 100 tries Aborting... verilator-5.042/test_regress/t/t_pp_pragmas.py0000755000542200017500000000072615101701376022124 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_wire_self_bad.v0000644000542200017500000000050715101701376022367 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias' // // Simple bi-directional alias test. // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; wire myself = myself; endmodule verilator-5.042/test_regress/t/t_mem_twoedge.py0000755000542200017500000000073415101701376022266 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_clocking_react.v0000644000542200017500000000256015101701376022552 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 interface axi_if; logic clk; wire rlast; wire rvalid; clocking cb @(posedge clk); inout rlast, rvalid; endclocking endinterface module t; axi_if axi_vi(); initial begin axi_vi.clk = 1'b0; #1 axi_vi.clk = 1'b1; // triggers line 26 #1 axi_vi.clk = 1'b0; // triggers line 29 (shouldn't happen) #1 axi_vi.clk = 1'b1; // triggers line 18 (shouldn't happen) end initial begin @(negedge axi_vi.rvalid); $display("[%0t] rvalid==%b", $time, axi_vi.rvalid); $display("[%0t] rlast is 1: ", $time, axi_vi.rlast === 1); if (axi_vi.rlast === 1) $stop; $write("*-* All Finished *-*\n"); $finish; end initial begin $display("[%0t] rvalid <= 1", $time); axi_vi.cb.rvalid <= 1'b1; // assigned on first clk posedge (line 13) @(posedge axi_vi.rvalid); $display("[%0t] rvalid <= 0", $time); axi_vi.cb.rvalid <= 1'b0; // assigned on second clk posedge (line 15), but should be on first @(negedge axi_vi.clk); $display("[%0t] rlast <= 1", $time); axi_vi.cb.rlast <= 1'b1; // assigned on second clk posedge (line 15), shouldn't happen end endmodule verilator-5.042/test_regress/t/t_format_wide_decimal.py0000755000542200017500000000103215101701376023740 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["-Wall"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_flag_build_jobs_bad.out0000644000542200017500000000043615101701376024060 0ustar mahmoudyfreeshell%Error: --build-jobs requires a non-negative integer, but '-1' was passed ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: The following cannot be used together: --build, --lint-only. Suggest see manual %Error: Exiting due to verilator-5.042/test_regress/t/t_queue_output_func.v0000644000542200017500000000075515101701376023366 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Cls; int x = 1; endclass task init_set_2 (output Cls c); c = new; c.x = 2; endtask module t; initial begin Cls cls_q[$]; init_set_2(cls_q[0]); if (cls_q[0].x != 2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_stream_unpack.v0000644000542200017500000001743515101701376022446 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); typedef enum bit [5:0] { A = 6'b111000, B = 6,b111111 } enum_t; module t; initial begin typedef bit [5:0] bit6_t; typedef bit bit6_unpacked_t[6]; bit6_unpacked_t arr; bit [1:0] arr2[3]; bit6_t arr6[1]; bit6_t [0:0] parr6; bit6_t bit6 = 6'b111000; bit [5:0] ans; bit [2:0][1:0] ans_packed; enum_t ans_enum; logic [1:0] a [3] = {1, 0, 3}; logic [1:0] b [3] = {1, 2, 0}; logic c [4] = {1, 1, 0, 0}; logic [15:0] d; logic [3:0] e [2]; logic f [8]; logic [1:0][7:0] g; logic [1:0][1:0][3:0] h; byte i []; longint j; int k; int l []; logic [127:0] m; longint n []; logic [255:0] o; logic [127:0] p[]; { >> bit {arr}} = bit6; `checkp(arr, "'{'h1, 'h1, 'h1, 'h0, 'h0, 'h0}"); arr = { >> bit {bit6}}; `checkp(arr, "'{'h1, 'h1, 'h1, 'h0, 'h0, 'h0}"); ans = { >> bit {arr} }; `checkh(ans, bit6); { >> bit {ans}} = arr; `checkh(ans, bit6); ans_packed = { >> bit {arr} }; `checkh(ans_packed, bit6); { >> bit {ans_packed}} = arr; `checkh(ans_packed, bit6); ans_enum = enum_t'({ >> bit {arr} }); `checkh(ans_enum, bit6); { << bit {arr}} = bit6; `checkp(arr, "'{'h0, 'h0, 'h0, 'h1, 'h1, 'h1}"); arr = { << bit {bit6}}; `checkp(arr, "'{'h0, 'h0, 'h0, 'h1, 'h1, 'h1}"); ans = { << bit {arr} }; `checkh(ans, bit6); { << bit {ans} } = arr; `checkh(ans, bit6); ans_packed = { << bit {arr} }; `checkh(ans_packed, bit6); { << bit {ans_packed} } = arr; `checkh(ans_packed, bit6); ans_enum = enum_t'({ << bit {arr} }); `checkh(ans_enum, bit6); { >> bit[1:0] {arr2}} = bit6; `checkp(arr2, "'{'h3, 'h2, 'h0}"); arr2 = { >> bit[1:0] {bit6}}; `checkp(arr2, "'{'h3, 'h2, 'h0}"); ans = { >> bit[1:0] {arr2} }; `checkh(ans, bit6); { >> bit[1:0] {ans} } = arr2; `checkh(ans, bit6); ans_packed = { >> bit[1:0] {arr2} }; `checkh(ans_packed, bit6); { >> bit[1:0] {ans_packed} } = arr2; `checkh(ans_packed, bit6); ans_enum = enum_t'({ >> bit[1:0] {arr2} }); `checkh(ans_enum, bit6); { << bit[1:0] {arr2}} = bit6; `checkp(arr2, "'{'h0, 'h2, 'h3}"); ans = { << bit[1:0] {arr2} }; `checkh(ans, bit6); { << bit[1:0] {ans} } = arr2; `checkh(ans, bit6); ans_packed = { << bit[1:0] {arr2} }; `checkh(ans_packed, bit6); { << bit[1:0] {ans_packed} } = arr2; `checkh(ans_packed, bit6); ans_enum = enum_t'({ << bit[1:0] {arr2} }); `checkh(ans_enum, bit6); { >> bit [5:0] {arr6} } = bit6; `checkp(arr6, "'{'h38}"); arr6 = { >> bit [5:0] {bit6}}; `checkp(arr6, "'{'h38}"); ans = { >> bit[5:0] {arr6} }; `checkh(ans, bit6); { >> bit[5:0] {ans} } = arr6; `checkh(ans, bit6); ans_packed = { >> bit[5:0] {arr6} }; `checkh(ans_packed, bit6); { >> bit[5:0] {ans_packed} } = arr6; `checkh(ans_packed, bit6); ans_enum = enum_t'({ >> bit[5:0] {arr6} }); `checkh(ans_enum, bit6); { << bit [5:0] {arr6} } = bit6; `checkp(arr6, "'{'h38}"); arr6 = { << bit [5:0] {bit6}}; `checkp(arr6, "'{'h38}"); ans = { << bit[5:0] {arr6} }; `checkh(ans, bit6); { << bit[5:0] {ans} } = arr6; `checkh(ans, bit6); ans_packed = { << bit[5:0] {arr6} }; `checkh(ans_packed, bit6); { << bit[5:0] {ans_packed} } = arr6; `checkh(ans_packed, bit6); ans_enum = enum_t'({ << bit[5:0] {arr6} }); `checkh(ans_enum, bit6); { >> bit [5:0] {parr6} } = bit6; `checkh(parr6, bit6); parr6 = { >> bit [5:0] {bit6}}; `checkh(parr6, bit6); ans = { >> bit[5:0] {parr6} }; `checkh(ans, bit6); { >> bit[5:0] {ans} } = parr6; `checkh(ans, bit6); ans_packed = { >> bit[5:0] {parr6} }; `checkh(ans_packed, bit6); { >> bit[5:0] {ans_packed} } = parr6; `checkh(ans_packed, bit6); ans_enum = enum_t'({ >> bit[5:0] {parr6} }); `checkh(ans_enum, bit6); { << bit [5:0] {parr6} } = bit6; `checkh(parr6, bit6); parr6 = { << bit [5:0] {bit6}}; `checkh(parr6, bit6); ans = { << bit[5:0] {parr6} }; `checkh(ans, bit6); { << bit[5:0] {ans} } = parr6; `checkh(ans, bit6); ans_packed = { << bit[5:0] {parr6} }; `checkh(ans_packed, bit6); { << bit[5:0] {ans_packed} } = parr6; `checkh(ans_packed, bit6); ans_enum = enum_t'({ << bit[5:0] {parr6} }); `checkh(ans_enum, bit6); d = { >> {a, b, c}}; `checkh(d, 16'b0100110110001100); { >> {e, f}} = d; `checkp(e, "'{'h4, 'hd}"); `checkp(f, "'{'h1, 'h0, 'h0, 'h0, 'h1, 'h1, 'h0, 'h0}"); d = { << 4 {a, b, c}}; `checkh(d, 16'b1100100011010100); { << 2 {e, f}} = d; `checkp(e, "'{'h1, 'h7}"); `checkp(f, "'{'h0, 'h0, 'h1, 'h0, 'h0, 'h0, 'h1, 'h1}"); g = { << 8 {16'hABCD}}; `checkh(g, 16'hCDAB); h = { << 8 {16'hABCD}}; `checkh(h, 16'hCDAB); i = new[8]('{8'hfa, 8'hde, 8'hca, 8'hfe, 8'hde, 8'had, 8'hbe, 8'hef}); `checkh(i[0], 8'hfa); `checkh(i[7], 8'hef); j = {>>{i}}; `checkh(j, 64'hfadecafedeadbeef); j = {<<8{i}}; `checkh(j, 64'hefbeaddefecadefa); i = new[4]('{8'hba, 8'hbe, 8'hfa, 8'hce}); k = {>>{i}}; `checkh(k, 32'hbabeface); k = {<<8{i}}; `checkh(k, 32'hcefabeba); i = new[8]('{8'hba, 8'hbe, 8'hfa, 8'hce, 8'hde, 8'had, 8'hbe, 8'hef}); j = {>>{i}}; `checkh(j, 64'hbabefacedeadbeef); j = {<<8{i}}; `checkh(j, 64'hefbeaddecefabeba); i = new[16]('{8'hba, 8'hbe, 8'hfa, 8'hce, 8'hde, 8'had, 8'hbe, 8'hef, 8'hde, 8'had, 8'hbe, 8'hef, 8'hde, 8'had, 8'hbe, 8'hef}); m = {>>{i}}; `checkh(m, 128'hbabefacedeadbeefdeadbeefdeadbeef); m = {<<8{i}}; `checkh(m, 128'hefbeaddeefbeaddeefbeaddecefabeba); l = new[2]('{32'hbabeface, 32'hdeadbeef}); j = {>>{l}}; `checkh(j, 64'hbabefacedeadbeef); j = {<<8{l}}; `checkh(j, 64'hefbeaddecefabeba); l = new[4]('{32'hbabeface, 32'hdeadbeef, 32'hdeadbeef, 32'hdeadbeef}); m = {>>{l}}; `checkh(m, 128'hbabefacedeadbeefdeadbeefdeadbeef); m = {<<8{l}}; `checkh(m, 128'hefbeaddeefbeaddeefbeaddecefabeba); n = new[2]('{64'hfadecafedeadbeef, 64'habcd0123456789ab}); m = {>>{n}}; `checkh(m, 128'hfadecafedeadbeefabcd0123456789ab); m = {<<64{n}}; `checkh(m, 128'habcd0123456789abfadecafedeadbeef); p = new[2]('{128'hfadecafedeadbeefabcd0123456789ab, 128'habcd0123456789abfadecafedeadbeef}); o = {>>{p}}; `checkh(o, 256'hfadecafedeadbeefabcd0123456789ababcd0123456789abfadecafedeadbeef); o = {<<128{p}}; `checkh(o, 256'habcd0123456789abfadecafedeadbeeffadecafedeadbeefabcd0123456789ab); {>>{p}} = o; `checkh(p[0], 128'habcd0123456789abfadecafedeadbeef); `checkh(p[1], 128'hfadecafedeadbeefabcd0123456789ab); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_timescale_default.out0000644000542200017500000000006215101701376023612 0ustar mahmoudyfreeshellTime scale of t is 1ps / 1ps *-* All Finished *-* verilator-5.042/test_regress/t/t_display_concat2.out0000644000542200017500000000013515101701376023217 0ustar mahmoudyfreeshell00005678 00001234 00005679 00001234 0000567a 00001234 0000567b 00001234 *-* All Finished *-* verilator-5.042/test_regress/t/t_split_var_5.py0000755000542200017500000000135015101701376022214 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_split_var_4.v" test.compile(verilator_flags2=['--stats', "-fno-dfg"]) test.execute() test.file_grep(test.stats, r'SplitVar,\s+packed variables split due to attribute\s+(\d+)', 0) test.file_grep(test.stats, r'SplitVar,\s+unpacked arrays split due to attribute\s+(\d+)', 0) test.passes() verilator-5.042/test_regress/t/t_math_wide_inc.py0000755000542200017500000000073415101701376022564 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_typedef_consistency_0.py0000755000542200017500000000073415101701376024272 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_unpacked_slice_range.v0000644000542200017500000000401315101701376023723 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by Yutetsu TAKATSUKASA // SPDX-License-Identifier: Unlicense module t ( clk ); input clk; int c = 0; t2 #(0) i_0(.*); t2 #(-1) i_1(.*); // lo is -1, hi is 5 t2 #(-4) i_2(.*); // lo is -4, hi is 1 t2 #(-10) i_3(.*); // lo is -10, hi is -4 t2 #(+1) i_4(.*); // lo is 1, hi is 7 t2 #(+4) i_5(.*); // lo is 4, hi is 10 t2 #(+10) i_6(.*); // lo is 10, hi is 16 always @(posedge clk) begin c <= c + 1; if (c == 5) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module t2 #(parameter ORIGIN = 0) (input wire clk, input int c); localparam WIDTH = 7; localparam OFFSET = 3; localparam FULL_LO = ORIGIN; localparam FULL_HI = ORIGIN + WIDTH - 1; localparam PART_LO = FULL_LO + OFFSET; localparam PART_HI = FULL_HI; bit unpack_sig0 [FULL_LO:FULL_HI]; bit unpack_sig1 [PART_LO:PART_HI]; bit unpack_sig2 [FULL_HI:FULL_LO]; bit unpack_sig3 [PART_HI:PART_LO]; initial $display("%m ORIGIN:%d [%d:%d] [%d:%d]", ORIGIN, FULL_LO, FULL_HI, PART_LO, PART_HI); always @(posedge clk) begin unpack_sig0[PART_LO] <= 1'b1; unpack_sig1[PART_LO] <= 1'b1; unpack_sig0 [PART_LO+1:FULL_HI] <= unpack_sig0[PART_LO:FULL_HI-1]; unpack_sig1 [PART_LO+1:PART_HI] <= unpack_sig1[PART_LO:PART_HI-1]; unpack_sig2[PART_LO] <= 1'b1; unpack_sig3[PART_LO] <= 1'b1; unpack_sig2 [FULL_HI:PART_LO+1] <= unpack_sig2[FULL_HI-1:PART_LO]; unpack_sig3 [PART_HI:PART_LO+1] <= unpack_sig3[PART_HI-1:PART_LO]; end always @(posedge clk) begin if (c >= 4) begin if (!unpack_sig0[FULL_HI] || !unpack_sig1[PART_HI]) $stop; if (!unpack_sig2[FULL_HI] || !unpack_sig3[PART_HI]) $stop; end else begin if (unpack_sig0[FULL_HI] || unpack_sig1[PART_HI]) $stop; if (unpack_sig2[FULL_HI] || unpack_sig3[PART_HI]) $stop; end end endmodule verilator-5.042/test_regress/t/t_interface_inl.py0000755000542200017500000000115715101701376022574 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface.v" test.compile( # Avoid inlining so we find bugs in the non-inliner connection code verilator_flags2=["-fno-inline"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_two_dumpfst_cc.py0000755000542200017500000000243115101701376024164 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Test tracing with two models instanced import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t_trace_two_a.v" test.pli_filename = "t/t_trace_two_cc.cpp" test.compile(make_main=False, verilator_make_gmake=False, top_filename='t_trace_two_b.v', vm_prefix='Vt_trace_two_b', verilator_flags2=['--trace-fst --trace-threads 1 -DTEST_FST']) test.run(logfile=test.obj_dir + "/make_first_ALL.log", cmd=[ os.environ["MAKE"], "-C", test.obj_dir, "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp" ]) test.compile( make_main=False, top_filename='t_trace_two_a.v', verilator_flags2=['-exe', '--trace-fst --trace-threads 1', '-DTEST_FST', test.pli_filename], v_flags2=['+define+TEST_DUMP']) test.execute() if test.vlt_all: test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_style_bad.v0000644000542200017500000000060115101701376022571 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; integer top; task x; output top; begin end endtask initial begin begin: lower integer top; end end endmodule verilator-5.042/test_regress/t/t_clk_dsp.py0000755000542200017500000000073415101701376021411 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_package_export.py0000755000542200017500000000100115101701376022752 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=['+define+T_PACKAGE_EXPORT']) test.execute() test.passes() verilator-5.042/test_regress/t/t_program_anonymous.v0000644000542200017500000000110615101701376023355 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 program; task atask; endtask function int afunc(input int i); return i+1; endfunction class acls; static int i = 10; endclass endprogram program t; int i; initial begin atask(); i = afunc(2); if (i != 3) $stop; if (acls::i != 10) $stop; $write("*-* All Finished *-*\n"); $finish; end endprogram verilator-5.042/test_regress/t/t_gen_defparam_nfound_bad.v0000644000542200017500000000047315101701376024373 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; a a (); defparam z.W = 3; // Bad endmodule module a; parameter W = 0; endmodule verilator-5.042/test_regress/t/t_lint_implicit_type_bad.py0000755000542200017500000000123715101701376024500 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') # --debug-check adds extra internal message, otherwise golden log would vary test.lint(verilator_flags2=["--lint-only --no-debug-check -Wall -Wno-DECLFILENAME"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_force_multi.v0000644000542200017500000000175415101701376022117 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module t(/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; logic [3:0] busa; logic [3:0] busb; // Test loop always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 0) begin busa <= 4'b0101; busb <= 4'b0111; end else if (cyc == 1) begin force {busa, busb} = 8'b1111_1101; end else if (cyc == 2) begin `checkh(busa, 4'b1111); `checkh(busb, 4'b1101); end // else if (cyc == 99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_flag_xinitial_unique.py0000755000542200017500000000121015101701376024160 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios("vlt_all") test.compile(verilator_flags2=["--x-initial unique"]) test.execute() files = glob.glob(test.obj_dir + "/" + test.vm_prefix + "___024root__*__Slow.cpp") test.file_grep_any(files, r"VL_SCOPED_RAND_RESET") test.passes() verilator-5.042/test_regress/t/t_opt_table_signed.py0000755000542200017500000000130215101701376023264 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--stats"]) if test.vlt_all: test.file_grep(test.stats, r'Optimizations, Tables created\s+(\d+)', 1) test.file_grep(test.stats, r'ConstPool, Tables emitted\s+(\d+)', 1) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_sys_readmem_bad_end.mem0000644000542200017500000000057515101701376024064 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test data file // // Copyright 2006 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 00 01 10 // Missing additional data verilator-5.042/test_regress/t/t_display.py0000755000542200017500000000100015101701376021422 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_genvar_misuse_bad.out0000644000542200017500000000112115101701376023612 0ustar mahmoudyfreeshell%Error: t/t_genvar_misuse_bad.v:15:19: Genvar 'i' used outside generate for loop (IEEE 1800-2023 27.4) 15 | assign q[i] = d[i]; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_genvar_misuse_bad.v:15:12: Genvar 'i' used outside generate for loop (IEEE 1800-2023 27.4) 15 | assign q[i] = d[i]; | ^ %Error: t/t_genvar_misuse_bad.v:22:11: Genvar 'c' used outside generate for loop (IEEE 1800-2023 27.4) 22 | if (c); | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_flag_trace_threads_bad.out0000644000542200017500000000021615101701376024550 0ustar mahmoudyfreeshell%Error: --trace-threads must be >= 1: -1 ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. verilator-5.042/test_regress/t/t_compiler_include_dpi.h0000644000542200017500000000122115101701376023727 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2024 by Antmicro. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // no header guards to check if included once in pch file extern "C" int dpii_add_check(int actual, int expected); extern "C" void dpii_add(int a, int b, int* out); verilator-5.042/test_regress/t/t_sys_readmem_bad_addr2.py0000755000542200017500000000102415101701376024155 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_var_extern_method_lifetime.py0000755000542200017500000000077115101701376025366 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_udp_delay.v0000644000542200017500000000066415101701376021554 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 primitive not_u(out, in); output out; input in; table 0 : 1; 1 : 0; endtable endprimitive module t (out, in); input in; output wire out; real v = 0.34; not_u #(1.145, v) dut_u (out, in); endmodule verilator-5.042/test_regress/t/t_implements_missing_bad.py0000755000542200017500000000076615101701376024513 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_alw_sen_compare.v0000644000542200017500000000065515101701376022744 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module top; sub inst( .a({128{1'b1}}), .b({128{1'b1}}) ); endmodule module sub(a, b); input [127:0] a; input [127:0] b; always @(a or b) begin $display("doesn't matter"); end endmodule verilator-5.042/test_regress/t/t_sc_names.py0000755000542200017500000000113215101701376021553 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_sc: test.skip("No SystemC installed") test.compile(make_main=False, verilator_flags2=["-sc --exe", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_dist_docs_style.py0000755000542200017500000000764515101701376023175 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Primitive C++ style checker # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') def get_source_files(): git_files = test.run_capture("cd " + test.root + " && git ls-files") if test.verbose: print("MF " + git_files) files = {} for filename in git_files.split(): if filename == '': continue files[filename] = True return files def check_pattern(filename, contents, pattern, message): lineno = 1 buf = contents while True: m = re.match(r'^(.*?^(' + pattern + '))(.*)', buf) if not m: break lineno += m.group(1).count("\n") buf = m.group(3) test.error_keep_going(filename + ":" + str(lineno) + ": " + message) def check_sorted(filename, contents): re_option = re.compile(r'^\.\. option:: (.*)') re_other = re.compile(r'^[^ ]') # .. t_dist_docs_style ignore string # Ignore the given string, as a prefix match re_ignore = re.compile(r' *\.\. t_dist_docs_style ignore (.*)') # .. t_dist_docs_style restart_sort # Restart the sort as if it's a new list, for forcing specific ordering re_restart = re.compile(r' *\.\. t_dist_docs_style restart_sort') contents += "__EOF__\n" lineno = 0 options = [] ignores = [] for line in contents.split("\n"): lineno += 1 if re.match(r'^($|\.\. _)', line): continue match_option = re_option.match(line) match_ignore = re_ignore.match(line) if match_option: arg = match_option.group(1) # print("-option %s" % line) hit = False for ignore in ignores: if arg[:len(ignore)] == ignore: hit = True if not hit: options.append([lineno, arg]) elif match_ignore: arg = match_ignore.group(1) ignores.append(arg) elif (options and re_other.match(line)) or re_restart.match(line): # print("-end-list %d %s" % (len(options), line)) check_sorted_options(filename, options) ignores = [] options = [] def check_sorted_options(filename, options): last_opt = None for opt_data in options: (lineno, opt) = opt_data if last_opt and _option_sort_key(last_opt) > _option_sort_key(opt): test.error_keep_going(filename + ":" + str(lineno) + ": Option '%s' should be in sorted order before '%s'" % (opt, last_opt)) last_opt = opt def _option_sort_key(opt): opt = re.sub(r'^<', ' <', opt) # before -option opt = re.sub(r'^\+', '-', opt) # +options sort with -options opt = re.sub(r'^--', '-', opt) # -- sorts with - opt = re.sub(r'^-no-', '-', opt) # -no- sorts with non-no opt = opt.lower() return opt ##### if not os.path.exists(test.root + "/.git"): test.skip("Not in a git repository") ### Must trim output before and after our file list files = get_source_files() for filename in sorted(files.keys()): filename = os.path.join(test.root, filename) if not os.path.exists(filename): # git file might be deleted but not yet staged continue if not re.search(r'\.rst$', filename): continue contents = test.file_contents(filename) check_pattern(filename, contents, r'.*[a-z](?= 0: -2 ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. verilator-5.042/test_regress/t/t_cover_toggle_underscore.py0000755000542200017500000000120715101701376024676 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = 't/t_cover_toggle.v' test.compile(verilator_flags2=['--cc --coverage-toggle --coverage-underscore']) test.execute() test.file_grep(test.obj_dir + "/coverage.dat", "_under_toggle") test.passes() verilator-5.042/test_regress/t/t_opt_merge_cond_blowup.py0000755000542200017500000000200715101701376024341 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') # TODO: This takes excessively long on vltmt, this should be fixed test.compile(verilator_flags2=["--unroll-count 1000000000", "--output-split 0", "--stats"]) test.execute() if test.vlt: # Note, with vltmt this might be split differently, so only checking vlt test.file_grep(test.stats, r'Optimizations, MergeCond merges\s+(\d+)', 500) # V3MergeCond.cpp MAX_DISTANCE test.file_grep(test.stats, r'Optimizations, MergeCond merged items\s+(\d+)', 1000) # V3MergeCond.cpp MAX_DISTANCE *2 test.file_grep(test.stats, r'Optimizations, MergeCond longest merge\s+(\d+)', 2) test.passes() verilator-5.042/test_regress/t/t_gen_missing.v0000644000542200017500000000255015101701376022104 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; // verilator lint_off PINMISSING `ifdef T_GEN_MISSING_BAD foobar #(.FOO_TYPE(1)) foobar(); // This means we should instatiate missing module `elsif T_GEN_MISSING foobar #(.FOO_TYPE(0)) foobar(); // This means we should instatiate foo0 `else `error "Bad Test" `endif endmodule module foobar #( parameter FOO_START = 0, FOO_NUM = 2, FOO_TYPE = 1 ) ( input wire[FOO_NUM-1:0] foo, output wire[FOO_NUM-1:0] bar); generate begin: g genvar j; for (j = FOO_START; j < FOO_NUM+FOO_START; j = j + 1) begin: foo_inst; if (FOO_TYPE == 0) begin: foo_0 // instatiate foo0 foo0 i_foo(.x(foo[j]), .y(bar[j])); end if (FOO_TYPE == 1) begin: foo_1 // instatiate foo1 foo_not_needed i_foo(.x(foo[j]), .y(bar[j])); end end end endgenerate endmodule module foo0(input wire x, output wire y); assign y = ~x; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_vpi_dump_missing_scopes.out0000644000542200017500000000210515101701376025070 0ustar mahmoudyfreeshellt (vpiModule) t vpiDefName=t vpiReg: vpiParameter: vpiInternalScope: top_wrap_1 (vpiModule) t.top_wrap_1 vpiDefName=gen_wrapper vpiReg: vpiParameter: vpiInternalScope: gen_loop[0] (vpiGenScope) t.top_wrap_1.gen_loop[0] vpiReg: vpiParameter: vpiInternalScope: after_gen_loop (vpiModule) t.top_wrap_1.gen_loop[0].after_gen_loop vpiDefName=sub vpiReg: subsig1 (vpiReg) t.top_wrap_1.gen_loop[0].after_gen_loop.subsig1 vpiParameter: top_wrap_2 (vpiModule) t.top_wrap_2 vpiDefName=gen_wrapper vpiReg: vpiParameter: vpiInternalScope: gen_loop[0] (vpiGenScope) t.top_wrap_2.gen_loop[0] vpiReg: vpiParameter: vpiInternalScope: after_gen_loop (vpiModule) t.top_wrap_2.gen_loop[0].after_gen_loop vpiDefName=sub vpiReg: subsig1 (vpiReg) t.top_wrap_2.gen_loop[0].after_gen_loop.subsig1 vpiParameter: *-* All Finished *-* verilator-5.042/test_regress/t/t_lib_nolib.py0000755000542200017500000000213715101701376021722 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all', 'xsim') test.top_filename = "t/t_lib_prot.v" if test.benchmark: test.sim_time = test.benchmark * 100 trace_opt = ("" if re.search(r'--no-trace', ' '.join(test.driver_verilator_flags)) else "-trace") # Tests the same code as t_lib_prot.py but without --protect-lib test.compile(verilator_flags2=['--no-timing', trace_opt, "t/t_lib_prot_secret.v"], xsim_flags2=["t/t_lib_prot_secret.v"]) test.execute() if test.vlt and test.trace: # We can see the ports of the secret module test.file_grep(test.trace_filename, r'accum_in') # and we can see what's inside (because we didn't use --protect-lib) test.file_grep(test.trace_filename, r'secret_') test.passes() verilator-5.042/test_regress/t/t_eq_wild_unsup.v0000644000542200017500000000066015101701376022460 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 function logic get_x_or_0(logic get_x); return get_x ? 1'bx : 1'b0; endfunction module t; initial begin if (1 ==? get_x_or_0(0)) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_lint_width_genfor_bad.out0000644000542200017500000000323015101701376024453 0ustar mahmoudyfreeshell%Warning-WIDTHTRUNC: t/t_lint_width_genfor_bad.v:25:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '?32?sh10' generates 32 or 5 bits. : ... note: In instance 't' 25 | rg = g; | ^ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Warning-WIDTHTRUNC: t/t_lint_width_genfor_bad.v:26:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'P' generates 32 or 5 bits. : ... note: In instance 't' 26 | rp = P; | ^ %Warning-WIDTHTRUNC: t/t_lint_width_genfor_bad.v:27:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'w' generates 5 bits. : ... note: In instance 't' 27 | rw = w; | ^ %Warning-WIDTHTRUNC: t/t_lint_width_genfor_bad.v:28:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '64'h1' generates 64 bits. : ... note: In instance 't' 28 | rc = 64'h1; | ^ %Warning-WIDTHTRUNC: t/t_lint_width_genfor_bad.v:33:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'i' generates 32 bits. : ... note: In instance 't' 33 | ri = i; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_trace_enum_fst.out0000644000542200017500000000121715101701376023141 0ustar mahmoudyfreeshell$date Sat Apr 5 13:56:28 2025 $end $version fstWriter $end $timescale 1ps $end $scope module top $end $attrbegin misc 07 $unit::state_t 4 VAL_A VAL_B VAL_C VAL_D 00 01 10 11 1 $end $attrbegin misc 07 t.other_state_t 3 VAL_X VAL_Y VAL_Z 00 01 10 2 $end $var wire 1 ! clk $end $scope module t $end $var wire 1 ! clk $end $scope interface sink $end $attrbegin misc 07 "" 1 $end $var logic 2 " state [1:0] $end $upscope $end $attrbegin misc 07 "" 1 $end $var logic 2 # v_enumed [1:0] $end $attrbegin misc 07 "" 2 $end $var logic 2 $ v_other_enumed [1:0] $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b00 $ b00 # b00 " 0! $end #10 1! verilator-5.042/test_regress/t/t_pipe_filter.v0000644000542200017500000000073615101701376022110 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 //=========================================================================== // Includes example line 10; example line 11; `include "t_pipe_filter_inc.vh" // Twice to check caching of includes `include "t_pipe_filter_inc.vh" example line 15; example line 16; verilator-5.042/test_regress/t/t_lint_iface_array_topmodule_bad.out0000644000542200017500000000062315101701376026334 0ustar mahmoudyfreeshell%Error: t/t_lint_iface_array_topmodule_bad.v:8:24: Parameter without default value is never given value (IEEE 1800-2023 6.20.1): 'DW' : ... note: In instance 't' 8 | parameter integer DW | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_display_esc_bad.out0000644000542200017500000000040115101701376023242 0ustar mahmoudyfreeshell%Error: t/t_display_esc_bad.v:9:16: Unknown escape sequence: \x 9 | $display("\x\y\z"); | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_if_same_bad.v0000644000542200017500000000212215101701376022006 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // bug3806 module t(/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [3:0] in; tri [3:0] bus = in; int never_driven; int never_forced; task force_bus; force bus[1:0] = 2'b10; endtask task release_bus; release bus; endtask // Test loop always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 0) begin in <= 4'b0101; end else if (cyc == 10) begin $display("10"); end else if (cyc == 11) begin $display("11"); end // // bus else if (cyc == 10) begin // Should warn $display("10b"); end else if (cyc == 11) begin // Should warn $display("11b"); end // else if (cyc == 99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_mod_interface_array2.py0000755000542200017500000000073415101701376024051 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_force_select_bad.py0000755000542200017500000000076615101701376023242 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_waiveroutput_roundtrip.v0000644000542200017500000000147315101701376024471 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs out, out2, // Inputs clk, a0, d0, d1 ); input clk; input [1:0] a0; input [7:0] d0; input [7:0] d1; output reg [31:0] out; output reg [15:0] out2; reg [7:0] mem [4]; always @(posedge clk) begin mem[a0] <= d0; // <--- Warning end always @(negedge clk) begin mem[a0] <= d1; // <--- Warning end assign out = {mem[3],mem[2],mem[1],mem[0]}; always @(posedge clk) begin out2[7:0] <= d0; // <--- Warning end always @(negedge clk) begin out2[15:8] <= d0; // <--- Warning end endmodule verilator-5.042/test_regress/t/t_uniqueif_fail1.py0000755000542200017500000000131415101701376022666 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_uniqueif.v" test.compile(v_flags2=['+define+FAILING_ASSERTION1'], verilator_flags2=['--assert'], nc_flags2=['+assert'], fails=test.nc) test.execute(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_param_noinit.py0000755000542200017500000000073415101701376023637 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_extends_param_unused.py0000755000542200017500000000073415101701376025374 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_method_struct.v0000644000542200017500000000126715101701376023657 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 typedef struct packed { int x; int y; int z; } my_struct; class Cls; function my_struct get_struct; my_struct s; s.x = 1; s.y = 2; s.z = 3; return s; endfunction endclass : Cls module t; initial begin Cls c = new; my_struct s = c.get_struct; if (s.x != 1) $stop; if (s.y != 2) $stop; if (s.z != 3) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_xml_debugcheck.out0000644000542200017500000031037415101701376023116 0ustar mahmoudyfreeshell verilator-5.042/test_regress/t/t_stream_unpack_narrower.v0000644000542200017500000000076315101701376024361 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 module t; logic [30:0] packed_data; logic [60:0] packed_data2; logic [7:0] stream[4]; initial begin packed_data = 31'h12345678; {>>{stream}} = packed_data; packed_data = {>>{stream}}; stream = {>>{packed_data2}}; {>>{packed_data2}} = stream; end endmodule verilator-5.042/test_regress/t/t_opt_table_real.v0000644000542200017500000000127015101701376022554 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024. // SPDX-License-Identifier: CC0-1.0 module t ( // Inputs clk ); input clk; reg [2:0] cyc; real x; initial cyc = 0; always @(posedge clk) cyc <= cyc + 1; always @(cyc) begin case (cyc) 3'd0: x = 1.0; 3'd1: x = 2.0; 3'd2: x = 3.0; 3'd4: x = 5.0; 3'd5: x = 6.0; default: x = 0.0; endcase end always @(posedge clk) begin $display("cyle %d = %.1f", cyc, x); if (cyc == 7) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule ; verilator-5.042/test_regress/t/t_langext_4_bad.py0000755000542200017500000000116115101701376022460 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.top_filename = "t/t_langext_2.v" test.leak_check_disable() # This is a lint only test. test.lint(v_flags2=["+1800-2005ext+v"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_flag_compiler_clang.py0000755000542200017500000000105315101701376023734 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_flag_compiler.v" test.compile(verilator_flags2=["--compiler clang"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_jumps_do_while_saif.out0000644000542200017500000000214315101701376025332 0ustar mahmoudyfreeshell// Generated by verilated_saif (SAIFILE (SAIFVERSION "2.0") (DIRECTION "backward") (PROGRAM_NAME "Verilator") (DIVIDER / ) (TIMESCALE 1ps) (DURATION 10) (INSTANCE top (NET (clk (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) ) (INSTANCE t (NET (clk (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) ) (INSTANCE unnamedblk1 (NET (results\[0\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) (results\[1\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) (results\[2\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) (results\[3\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) (results\[4\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) (results\[5\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) (results\[6\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) (results\[7\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) (results\[8\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) (results\[9\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) (results\[10\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) (results\[11\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) ) ) ) ) ) verilator-5.042/test_regress/t/t_vpi_finish.py0000755000542200017500000000103115101701376022117 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=["t/t_vpi_finish_c.cpp"], verilator_flags2=["--vpi"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_stream.py0000755000542200017500000000073415101701376021265 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_array_nocolon.v0000644000542200017500000000324015101701376024464 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Functionally demonstrate an array of interfaces // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Mike Popoloski. // SPDX-License-Identifier: CC0-1.0 interface foo_intf ( input x ); endinterface module foo_subm ( input x ); endmodule module t (); localparam N = 3; wire [2:0] X = 3'b110; // Should not cause ASCRANGE warning, as no harm in array selections. // verilator lint_on ASCRANGE foo_intf foo1 [N] (.x(1'b1)); foo_subm sub1 [N] (.x(1'b1)); // Will cause ASCRANGE warning? // verilator lint_off ASCRANGE foo_intf foos [N] (.x(X)); foo_intf fool [1:3] (.x(X)); foo_intf foom [3:1] (.x(X)); foo_subm subs [N] (.x(X)); foo_subm subl [1:3] (.x(X)); foo_subm subm [3:1] (.x(X)); initial begin // Check numbering with 0 first // NC has a bug here if (foos[0].x !== 1'b1) $stop; if (foos[1].x !== 1'b1) $stop; if (foos[2].x !== 1'b0) $stop; // if (fool[1].x !== 1'b1) $stop; if (fool[2].x !== 1'b1) $stop; if (fool[3].x !== 1'b0) $stop; // if (foom[1].x !== 1'b0) $stop; if (foom[2].x !== 1'b1) $stop; if (foom[3].x !== 1'b1) $stop; // if (subs[0].x !== 1'b1) $stop; if (subs[1].x !== 1'b1) $stop; if (subs[2].x !== 1'b0) $stop; // if (subl[1].x !== 1'b1) $stop; if (subl[2].x !== 1'b1) $stop; if (subl[3].x !== 1'b0) $stop; // if (subm[1].x !== 1'b0) $stop; if (subm[2].x !== 1'b1) $stop; if (subm[3].x !== 1'b1) $stop; // $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_trace_dumpvars_dyn_vcd_0.py0000755000542200017500000000130315101701376024727 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_trace_dumpvars_dyn.cpp" test.top_filename = "t/t_trace_dumpvars_dyn.v" test.compile(make_main=False, verilator_flags2=["--trace-vcd --exe", test.pli_filename]) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_clk_condflop.v0000644000542200017500000000540215101701376022236 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; reg [0:0] d1; reg [2:0] d3; reg [7:0] d8; wire [0:0] q1; wire [2:0] q3; wire [7:0] q8; reg ena; condff #(12) condff (.clk(clk), .sen(1'b0), .ena(ena), .d({d8,d3,d1}), .q({q8,q3,q1})); integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin //$write("%x %x %x %x\n", cyc, q8, q3, q1); cyc <= cyc + 1; if (cyc==1) begin d1 <= 1'b1; d3<=3'h1; d8<=8'h11; ena <= 1'b1; end if (cyc==2) begin d1 <= 1'b0; d3<=3'h2; d8<=8'h33; ena <= 1'b0; end if (cyc==3) begin d1 <= 1'b1; d3<=3'h3; d8<=8'h44; ena <= 1'b1; if (q8 != 8'h11) $stop; end if (cyc==4) begin d1 <= 1'b1; d3<=3'h4; d8<=8'h77; ena <= 1'b1; if (q8 != 8'h11) $stop; end if (cyc==5) begin d1 <= 1'b1; d3<=3'h0; d8<=8'h88; ena <= 1'b1; if (q8 != 8'h44) $stop; end if (cyc==6) begin if (q8 != 8'h77) $stop; end if (cyc==7) begin if (q8 != 8'h88) $stop; end // if (cyc==20) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module condff (clk, sen, ena, d, q); parameter WIDTH = 1; input clk; input sen; input ena; input [WIDTH-1:0] d; output [WIDTH-1:0] q; condffimp #(.WIDTH(WIDTH)) imp (.clk(clk), .sen(sen), .ena(ena), .d(d), .q(q)); endmodule module condffimp (clk, sen, ena, d, q); parameter WIDTH = 1; input clk; input sen; input ena; input [WIDTH-1:0] d; output reg [WIDTH-1:0] q; wire gatedclk; clockgate clockgate (.clk(clk), .sen(sen), .ena(ena), .gatedclk(gatedclk)); always @(posedge gatedclk) begin if (gatedclk === 1'bX) begin q <= {WIDTH{1'bX}}; end else begin q <= d; end end endmodule module clockgate (clk, sen, ena, gatedclk); input clk; input sen; input ena; output gatedclk; reg ena_b; wire gatedclk = clk & ena_b; // verilator lint_off COMBDLY // verilator lint_off LATCH always @(clk or ena or sen) begin if (~clk) begin ena_b <= ena | sen; end else begin if ((clk^sen)===1'bX) ena_b <= 1'bX; end end // verilator lint_on LATCH // verilator lint_on COMBDLY endmodule verilator-5.042/test_regress/t/t_trace_multi_bad.v0000644000542200017500000000037515101701376022723 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial $finish; endmodule verilator-5.042/test_regress/t/t_class_compare.py0000755000542200017500000000073415101701376022605 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_split.v0000644000542200017500000000115415101701376022121 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Iru Cai. // SPDX-License-Identifier: CC0-1.0 class Cls1; int ctr; task run(); $display("%d", ctr); ctr = ctr + 1; endtask: run endclass; class Cls2 extends Cls1; task runtask(); run(); run(); run(); run(); run(); run(); endtask: runtask endclass module top; Cls2 o; initial begin o = new; o.runtask(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_randomize_inline_var_ctl_bad.out0000644000542200017500000000373715101701376026022 0ustar mahmoudyfreeshell%Error: t/t_randomize_inline_var_ctl_bad.v:12:23: 'randomize()' argument must be a variable contained in 'Foo' : ... note: In instance 't' 12 | void'(randomize(y)); | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_randomize_inline_var_ctl_bad.v:26:46: 'randomize()' argument must be a variable contained in 'foo' : ... note: In instance 't' 26 | void'(foo.randomize(x, foo.x, null, qux.x, bar.y, 0 + 1, x ** 2)); | ^ %Error: t/t_randomize_inline_var_ctl_bad.v:26:53: 'randomize()' argument must be a variable contained in 'foo' : ... note: In instance 't' 26 | void'(foo.randomize(x, foo.x, null, qux.x, bar.y, 0 + 1, x ** 2)); | ^ %Error: t/t_randomize_inline_var_ctl_bad.v:26:59: 'randomize()' argument must be a variable contained in 'foo' : ... note: In instance 't' 26 | void'(foo.randomize(x, foo.x, null, qux.x, bar.y, 0 + 1, x ** 2)); | ^ %Error: t/t_randomize_inline_var_ctl_bad.v:26:66: 'randomize()' argument must be a variable contained in 'foo' : ... note: In instance 't' 26 | void'(foo.randomize(x, foo.x, null, qux.x, bar.y, 0 + 1, x ** 2)); | ^~ %Error: t/t_randomize_inline_var_ctl_bad.v:26:37: Cannot pass more arguments to 'randomize(null)' : ... note: In instance 't' 26 | void'(foo.randomize(x, foo.x, null, qux.x, bar.y, 0 + 1, x ** 2)); | ^~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_class_local_nested_bad.v0000644000542200017500000000077715101701376024242 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class NodeList; class Node; static local string name; endclass string name; function new(); name = Node::name; endfunction endclass module t; initial begin NodeList n = new; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_gate_width_bad.v0000644000542200017500000000111615101701376022524 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg [1:0] in; wire [2:0] out; // verilator lint_off WIDTH buf buf1 (out[0], 1); // <--- BAD wrong connection width buf buf2[0:0] (out[1], 2'b01); // <--- BAD wrong connection width buf buf3[0:0] (out[2], in[1:0]); // <--- BAD wrong connection width buf buf4[3:0] (out[2], in[1:0]); // <--- BAD wrong connection width initial $stop; endmodule verilator-5.042/test_regress/t/t_force_release.py0000755000542200017500000000102715101701376022564 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["--binary"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_preproc_eof_qqq_bad.py0000755000542200017500000000076615101701376023772 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_property_named.py0000755000542200017500000000077115101701376023023 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--assert']) test.execute() test.passes() verilator-5.042/test_regress/t/t_queue_class.v0000644000542200017500000000160015101701376022106 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; class Cls; int que[$]; task push_data(int val); que.push_back(val); endtask function logic ok; return '1; endfunction endclass initial begin Cls c2 [1:0]; Cls cq[$]; c2[0] = new(); c2[0].push_data(20); // Works if (c2[0].que.size() != 1) $stop; c2[0].que.push_back(10); // Unsupported if (c2[0].que.size() != 2) $stop; // Test there's no side effect warning on iteration foreach (cq[i]) case (cq[i].ok()) '0: $stop; '1: $stop; endcase $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_hier_block1_bad.v0000644000542200017500000000204515101701376022571 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by Yutetsu TAKATSUKASA // SPDX-License-Identifier: Unlicense `define HIER_BLOCK /*verilator hier_block*/ interface byte_ifs(input clk); logic [7:0] data; modport sender(input clk, output data); modport receiver(input clk, input data); endinterface; module t (/*AUTOARG*/ // Inputs clk ); `HIER_BLOCK // Top module can not be a hierarchy block input wire clk; wire [7:0] out0; int count = 0; byte_ifs in_ifs(.clk(clk)); byte_ifs out_ifs(.clk(clk)); assign in_ifs.data = out0; sub0 i_sub0(.clk(clk), .in(count), .out(out0)); sub1 i_sub1(.in(in_ifs), .out(out_ifs)); endmodule module sub0 ( input wire clk, input wire [7:0] in, output wire [7:0] out); `HIER_BLOCK logic [7:0] ff; always_ff @(posedge clk) ff <= in; assign out = ff; endmodule module sub1 (byte_ifs.receiver in, byte_ifs.sender out); `HIER_BLOCK assign out.data = in.data; endmodule verilator-5.042/test_regress/t/t_unopt_converge_initial.v0000644000542200017500000000074215101701376024351 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs x, // Inputs clk ); `ifdef ALLOW_UNOPT /*verilator lint_off UNOPTFLAT*/ `endif input clk; output [31:0] x; // Avoid eliminating x reg [31:0] x; always @* begin x = x ^ $random; end endmodule verilator-5.042/test_regress/t/t_xml_flat_no_inline_mod.v0000644000542200017500000000062615101701376024303 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module foo(input logic i_clk); /* verilator no_inline_module */ endmodule // --flatten forces inlining of 'no_inline_module' module foo. module top(input logic i_clk); foo f(.*); endmodule verilator-5.042/test_regress/t/t_trace_dumpvars_dyn_fst_1.py0000755000542200017500000000130315101701376024750 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_trace_dumpvars_dyn.cpp" test.top_filename = "t/t_trace_dumpvars_dyn.v" test.compile(make_main=False, verilator_flags2=["--trace-fst --exe", test.pli_filename]) test.execute() test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_semaphore_bad.out0000644000542200017500000000054215101701376022734 0ustar mahmoudyfreeshell%Error: t/t_semaphore_bad.v:12:13: Class method 'bad_method' not found in class 'semaphore' : ... note: In instance 't' 12 | if (s.bad_method() != 0) $stop; | ^~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_cover_expr_dyn_array_class.v0000644000542200017500000000114415101701376025211 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Class1; int value0 = 7; endclass module t; initial begin int i = 0; Class1 q[] = new [15]; for (int j = 0; j < 15; j = j + 1) begin Class1 x = new; q[j] = x; end while (i < 15) begin if ((q[i].value0 > 8) || (q[i].value0 < 5)) $stop; i += 1; end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_std_randomize_bad1.out0000644000542200017500000000122415101701376023672 0ustar mahmoudyfreeshell%Error: t/t_std_randomize_bad1.v:12:36: Non-variable arguments for 'std::randomize()'. : ... note: In instance 't_std_randomize_bad1' 12 | success = std::randomize(a + 1); | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_std_randomize_bad1.v:19:30: 'std::randomize()' does not accept 'null' as arguments. : ... note: In instance 't_std_randomize_bad1' 19 | void'(std::randomize(null)); | ^~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_xml_first.out0000644000542200017500000001104715101701376022154 0ustar mahmoudyfreeshell verilator-5.042/test_regress/t/t_flag_noop_bad.out0000644000542200017500000000032615101701376022715 0ustar mahmoudyfreeshell%Error: verilator: Need --binary, --cc, --sc, --dpi-hdr-only, --lint-only, --xml-only, --json-only or --E option ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. verilator-5.042/test_regress/t/t_case_inside_call_count.py0000755000542200017500000000107315101701376024440 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--stats']) test.execute() test.file_grep(test.stats, r'Impure case expressions\s+(\d+)', 2) test.passes() verilator-5.042/test_regress/t/t_json_only_tag.out0000644000542200017500000003460415101701376023016 0ustar mahmoudyfreeshell{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"UNLINKED", "modulesp": [ {"type":"MODULE","name":"m","addr":"(E)","loc":"d,12:8,12:9","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"m","level":2,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"clk_ip","addr":"(F)","loc":"d,14:11,14:17","dtypep":"(G)","origName":"clk_ip","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"rst_ip","addr":"(H)","loc":"d,15:11,15:17","dtypep":"(G)","origName":"rst_ip","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"foo_op","addr":"(I)","loc":"d,16:11,16:17","dtypep":"(G)","origName":"foo_op","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"TYPEDEF","name":"my_struct","addr":"(J)","loc":"d,25:6,25:15","dtypep":"(K)","attrPublic":false,"isUnderClass":false,"childDTypep": [],"attrsp": []}, {"type":"CELL","name":"itop","addr":"(L)","loc":"d,29:8,29:12","origName":"itop","recursive":false,"modp":"(M)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []}, {"type":"VAR","name":"itop","addr":"(N)","loc":"d,29:8,29:12","dtypep":"(O)","origName":"itop__Viftop","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"IFACEREF","dtypeName":"","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"this_struct","addr":"(P)","loc":"d,31:14,31:25","dtypep":"(Q)","origName":"this_struct","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"dotted","addr":"(R)","loc":"d,33:16,33:22","dtypep":"(S)","origName":"dotted","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"ALWAYS","name":"","addr":"(T)","loc":"d,33:23,33:24","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(U)","loc":"d,33:23,33:24","dtypep":"(S)", "rhsp": [ {"type":"VARXREF","name":"value","addr":"(V)","loc":"d,33:30,33:35","dtypep":"(W)","containsGenBlock":false,"dotted":"itop","inlinedDots":"","access":"RD","varp":"(X)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "lhsp": [ {"type":"VARREF","name":"dotted","addr":"(Y)","loc":"d,33:16,33:22","dtypep":"(S)","access":"WR","varp":"(R)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": [],"strengthSpecp": []} ]}, {"type":"TASK","name":"f","addr":"(Z)","loc":"d,35:18,35:19","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"f","fvarp": [],"classOrPackagep": [], "stmtsp": [ {"type":"VAR","name":"m","addr":"(AB)","loc":"d,35:33,35:34","dtypep":"(BB)","origName":"m","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":true,"lifetime":"VAUTOMI","varType":"PORT","dtypeName":"string","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"DISPLAY","name":"","addr":"(CB)","loc":"d,36:7,36:15", "fmtp": [ {"type":"SFORMATF","name":"%@","addr":"(DB)","loc":"d,36:7,36:15","dtypep":"(BB)", "exprsp": [ {"type":"VARREF","name":"m","addr":"(EB)","loc":"d,36:22,36:23","dtypep":"(BB)","access":"RD","varp":"(AB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"scopeNamep": []} ],"filep": []} ],"scopeNamep": []}, {"type":"INITIAL","name":"","addr":"(FB)","loc":"d,39:4,39:11","isSuspendable":false,"needProcess":false, "stmtsp": [ {"type":"BEGIN","name":"","addr":"(GB)","loc":"d,39:12,39:17","implied":false,"needProcess":false,"unnamed":true,"declsp": [], "stmtsp": [ {"type":"STMTEXPR","name":"","addr":"(HB)","loc":"d,41:7,41:8", "exprp": [ {"type":"TASKREF","name":"f","addr":"(IB)","loc":"d,41:7,41:8","dtypep":"(JB)","dotted":"","taskp":"(Z)","classOrPackagep":"UNLINKED","namep": [], "pinsp": [ {"type":"ARG","name":"","addr":"(KB)","loc":"d,41:9,41:736", "exprp": [ {"type":"CONST","name":"\\\"\\001\\002\\003\\004\\005\\006\\007\\010\\t\\n\\013\\014\\r\\016\\017\\020\\021\\022\\023\\024\\025\\026\\027\\030\\031\\032\\033\\034\\035\\036\\037 !\\\"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\\\\]^_`abcdefghijklmnopqrstuvwxyz{|}~\\177\\200\\201\\202\\203\\204\\205\\206\\207\\210\\211\\212\\213\\214\\215\\216\\217\\220\\221\\222\\223\\224\\225\\226\\227\\230\\231\\232\\233\\234\\235\\236\\237\\240\\241\\242\\243\\244\\245\\246\\247\\250\\251\\252\\253\\254\\255\\256\\257\\260\\261\\262\\263\\264\\265\\266\\267\\270\\271\\272\\273\\274\\275\\276\\277\\300\\301\\302\\303\\304\\305\\306\\307\\310\\311\\312\\313\\314\\315\\316\\317\\320\\321\\322\\323\\324\\325\\326\\327\\330\\331\\332\\333\\334\\335\\336\\337\\340\\341\\342\\343\\344\\345\\346\\347\\350\\351\\352\\353\\354\\355\\356\\357\\360\\361\\362\\363\\364\\365\\366\\367\\370\\371\\372\\373\\374\\375\\376\\377\\\"","addr":"(LB)","loc":"d,41:9,41:736","dtypep":"(BB)"} ]} ],"scopeNamep": []} ]} ]} ]} ]}, {"type":"IFACE","name":"ifc","addr":"(M)","loc":"d,7:11,7:14","origName":"ifc","level":3,"modPublic":false,"inLibrary":true,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"value","addr":"(X)","loc":"d,8:12,8:17","dtypep":"(W)","origName":"value","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"integer","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"MODPORT","name":"out_modport","addr":"(MB)","loc":"d,9:12,9:23", "varsp": [ {"type":"MODPORTVARREF","name":"value","addr":"(NB)","loc":"d,9:32,9:37","direction":"OUTPUT","varp":"(X)"} ]} ]} ],"filesp": [], "miscsp": [ {"type":"TYPETABLE","name":"","addr":"(C)","loc":"a,0:0,0:0","constraintRefp":"UNLINKED","emptyQueuep":"UNLINKED","queueIndexp":"UNLINKED","streamp":"UNLINKED","voidp":"(JB)", "typesp": [ {"type":"VOIDDTYPE","name":"","addr":"(JB)","loc":"d,41:7,41:8","dtypep":"(JB)","generic":false}, {"type":"BASICDTYPE","name":"integer","addr":"(W)","loc":"d,8:4,8:11","dtypep":"(W)","keyword":"integer","range":"31:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(G)","loc":"d,14:11,14:17","dtypep":"(G)","keyword":"logic","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(OB)","loc":"d,21:7,21:12","dtypep":"(OB)","keyword":"logic","generic":false,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(PB)","loc":"d,22:7,22:12","dtypep":"(PB)","keyword":"logic","generic":false,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(QB)","loc":"d,23:7,23:12","dtypep":"(QB)","keyword":"logic","generic":false,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(RB)","loc":"d,24:7,24:12","dtypep":"(RB)","keyword":"logic","generic":false,"rangep": []}, {"type":"STRUCTDTYPE","name":"m.my_struct","addr":"(K)","loc":"d,20:12,20:18","dtypep":"(K)","packed":true,"isFourstate":true,"generic":false,"classOrPackagep":"UNLINKED", "membersp": [ {"type":"MEMBERDTYPE","name":"clk","addr":"(SB)","loc":"d,21:19,21:22","dtypep":"(OB)","isConstrainedRand":false,"name":"clk","tag":"this is clk","generic":false,"refDTypep":"(OB)","childDTypep": [],"valuep": []}, {"type":"MEMBERDTYPE","name":"k","addr":"(TB)","loc":"d,22:19,22:20","dtypep":"(PB)","isConstrainedRand":false,"name":"k","tag":"","generic":false,"refDTypep":"(PB)","childDTypep": [],"valuep": []}, {"type":"MEMBERDTYPE","name":"enable","addr":"(UB)","loc":"d,23:19,23:25","dtypep":"(QB)","isConstrainedRand":false,"name":"enable","tag":"enable","generic":false,"refDTypep":"(QB)","childDTypep": [],"valuep": []}, {"type":"MEMBERDTYPE","name":"data","addr":"(VB)","loc":"d,24:19,24:23","dtypep":"(RB)","isConstrainedRand":false,"name":"data","tag":"data","generic":false,"refDTypep":"(RB)","childDTypep": [],"valuep": []} ]}, {"type":"IFACEREFDTYPE","name":"","addr":"(O)","loc":"d,29:8,29:12","dtypep":"(O)","isPortDecl":false,"isVirtual":false,"cellName":"itop","ifaceName":"ifc","modportName":"","generic":false,"ifacep":"UNLINKED","cellp":"(L)","modportp":"UNLINKED","paramsp": []}, {"type":"BASICDTYPE","name":"logic","addr":"(S)","loc":"d,31:27,31:28","dtypep":"(S)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, {"type":"REFDTYPE","name":"my_struct","addr":"(WB)","loc":"d,31:4,31:13","dtypep":"(K)","generic":false,"typedefp":"UNLINKED","refDTypep":"(K)","classOrPackagep":"UNLINKED","typeofp": [],"classOrPackageOpp": [],"paramsp": []}, {"type":"UNPACKARRAYDTYPE","name":"","addr":"(Q)","loc":"d,31:26,31:27","dtypep":"(Q)","isCompound":false,"declRange":"[0:1]","generic":false,"refDTypep":"(WB)","childDTypep": [], "rangep": [ {"type":"RANGE","name":"","addr":"(XB)","loc":"d,31:26,31:27","ascending":true,"fromBracket":true, "leftp": [ {"type":"CONST","name":"32'h0","addr":"(YB)","loc":"d,31:27,31:28","dtypep":"(S)"} ], "rightp": [ {"type":"CONST","name":"32'h1","addr":"(ZB)","loc":"d,31:27,31:28","dtypep":"(S)"} ]} ]}, {"type":"BASICDTYPE","name":"string","addr":"(BB)","loc":"d,35:26,35:32","dtypep":"(BB)","keyword":"string","generic":true,"rangep": []} ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ {"type":"MODULE","name":"@CONST-POOL@","addr":"(AC)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], "stmtsp": [ {"type":"SCOPE","name":"@CONST-POOL@","addr":"(BC)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(AC)","varsp": [],"blocksp": [],"inlinesp": []} ]} ]} ]} verilator-5.042/test_regress/t/t_tri_pull_bad.py0000755000542200017500000000077615101701376022440 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_blkseq_bad.out0000644000542200017500000000416115101701376023261 0ustar mahmoudyfreeshell%Warning-BLKSEQ: t/t_lint_blkseq_bad.v:22:14: Blocking assignment '=' in sequential logic process : ... note: In instance 't' : ... Suggest using delayed assignment '<=' 22 | sync_blk = 1'b1; | ^ ... For warning description see https://verilator.org/warn/BLKSEQ?v=latest ... Use "/* verilator lint_off BLKSEQ */" and lint_on around source to disable this message. %Warning-BLKSEQ: t/t_lint_blkseq_bad.v:23:15: Blocking assignment '=' in sequential logic process : ... note: In instance 't' : ... Suggest using delayed assignment '<=' 23 | sync_blk2 = 1'b1; | ^ %Warning-BLKSEQ: t/t_lint_blkseq_bad.v:66:29: Blocking assignment '=' in sequential logic process : ... note: In instance 't.a' : ... Suggest using delayed assignment '<=' 66 | always @(posedge clk) out = 1; | ^ %Warning-BLKSEQ: t/t_lint_blkseq_bad.v:75:29: Blocking assignment '=' in sequential logic process : ... note: In instance 't.b' : ... Suggest using delayed assignment '<=' 75 | always @(posedge clk) out = 1; | ^ %Warning-COMBDLY: t/t_lint_blkseq_bad.v:29:16: Non-blocking assignment '<=' in combinational logic process : ... This will be executed as a blocking assignment '='! 29 | combo_nblk <= 1'b1; | ^~ ... For warning description see https://verilator.org/warn/COMBDLY?v=latest ... Use "/* verilator lint_off COMBDLY */" and lint_on around source to disable this message. *** See https://verilator.org/warn/COMBDLY?v=latest before disabling this, else you may end up with different sim results. %Error: Exiting due to verilator-5.042/test_regress/t/t_func_check.v0000644000542200017500000000323515101701376021673 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilator lint_off WIDTH // verilator lint_off VARHIDDEN module t ( clk ); input clk; integer cyc = 0; reg [63:0] crc; initial crc = 64'h1; chk chk (.clk (clk), .rst_l (1'b1), .expr (|crc) ); always @ (posedge clk) begin cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; if (cyc==0) begin crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<90) begin end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module chk (input clk, input rst_l, input expr); int errors; task printerr; input [8*64:1] msg; begin errors = errors + 1; $write("%%Error: %0s\n", msg); $stop; end endtask always @(posedge clk) begin if (rst_l) begin if (expr == 1'b0) begin printerr("expr not asserted"); end end end wire noxs = ((expr ^ expr) == 1'b0); // TODO: this test is dodgy, noxs can be proven constant, so this block // should never relly trigger... reg hasx; always @ (noxs) begin if (noxs) begin hasx = 1'b0; end else begin hasx = 1'b1; end end always @(posedge clk) begin if (rst_l) begin if (hasx) begin printerr("expr has unknowns"); end end end endmodule verilator-5.042/test_regress/t/t_bitsel_slice.v0000644000542200017500000000404415101701376022243 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; logic [2:0] [1:0] in; always @* in = crc[5:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) logic [1:0] [1:0] out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out (out/*[1:0][1:0]*/), // Inputs .clk (clk), .in (in/*[2:0][1:0]*/)); // Aggregate outputs into a single result vector wire [63:0] result = {60'h0, out[1],out[0]}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'hdc21e42d85441511 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs out, // Inputs clk, in ); //bug717 input clk; input logic [2:0][1:0] in; output logic [1:0][1:0] out; always @(posedge clk) begin out <= in[2 -: 2]; end endmodule verilator-5.042/test_regress/t/t_foreach_bad.py0000755000542200017500000000076615101701376022214 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_setuphold.v0000644000542200017500000000466015101701376021615 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk, d, t_in ); input clk; input d; input t_in; wire delayed_CLK; wire delayed_D; reg notifier; wire [1:0] BL_X = 2'b11; wire [5:0] BL_X2; wire BL_0; wire [3:0] BL_1 = 4'b1100; wire fake_CLK; wire fake_D; logic[3:0] sh1 = 1; logic[3:0] sh2 = 2; logic[3:0] sh3 = 3; logic[3:0] sh4 = 4; logic[3:0] sh5 = 5; logic[3:0] sh6 = 6; int cyc = 0; specify $setuphold (posedge clk, negedge d, 0, 0, notifier, (0:0:0), 0, delayed_CLK, delayed_D); $setuphold (posedge sh1, negedge sh3, 0, 0, notifier,,, sh2, sh4); $setuphold (posedge sh5, negedge d, 0, 0, notifier,,, sh6); $setuphold (posedge clk, negedge d, 0, 0, notifier, (1:2:3), (0:0:0)); $setuphold (posedge clk, negedge d, 0, 0, notifier, (1:2:3)); $setuphold (posedge clk, negedge d, 0, 0, notifier); $setuphold (posedge clk, negedge d, 0, 0); $setuphold (posedge clk, negedge d, 0, 0); $setuphold (posedge clk, negedge d, (0:0:0), (0:0:0)); $setuphold (posedge clk, negedge d, 0:0:0, 0:0:0); $setuphold (posedge clk, negedge d, 0, 0,,,,,); $setuphold (posedge clk &&& sh1, BL_X[0], 0, 0, ,,,delayed_CLK, BL_0); $setuphold (posedge clk &&& sh1, BL_1, 0, 0, ,,,delayed_CLK, BL_X2[4:1]); $setuphold (fake_CLK, fake_D &&& sh1, 0, 0); $setuphold (posedge fake_CLK, posedge fake_D &&& sh1, 0, 0); $setuphold (negedge fake_CLK, negedge fake_D &&& sh1, 0, 0); $setuphold (edge fake_CLK, edge fake_D &&& sh1, 0, 0); $setuphold (edge [0Z, z1, 10] fake_CLK, edge [01, x0, 0X] fake_CLK &&& sh1, 0, 0); $setuphold (posedge clk, negedge d, 0, 0, notifier, (0:0:0), 0, t_in); endspecify initial begin if (sh1 != sh2 || sh3 != sh4) begin $stop; end if (sh5 != sh6) begin $stop; end if (BL_0 != BL_X[0] || BL_1 != BL_X2[4:1]) begin $stop; end end always @(posedge clk) begin cyc <= cyc + 1; $display("%d %d", clk, delayed_CLK); if (delayed_CLK != clk || delayed_D != d) begin $stop; end if (cyc == 10) begin $display("*-* All Finished *-*"); $finish; end end endmodule verilator-5.042/test_regress/t/t_trace_public_sig.py0000755000542200017500000000155515101701376023272 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_trace_public.v" test.golden_filename = "t/t_trace_public.out" test.compile(make_top_shell=False, make_main=False, v_flags2=["-DATTRIBUTES --trace-vcd --exe", test.pli_filename]) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) # vcd_identical doesn't detect "$var a.b;" vs "$scope module a; $var b;" test.file_grep(test.trace_filename, r'module glbl') test.passes() verilator-5.042/test_regress/t/t_bitsel_enum.py0000755000542200017500000000073415101701376022300 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_event_control_timing.py0000755000542200017500000000110715101701376024215 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_event_control.v" test.compile(verilator_flags2=["--timing"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_embed1_c.cpp0000644000542200017500000001071015101701376021553 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2011-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "../t_embed1_child/Vt_embed1_child.h" #include "svdpi.h" #include //====================================================================== // clang-format off #if defined(VERILATOR) # include "Vt_embed1__Dpi.h" #elif defined(VCS) # include "../vc_hdrs.h" #elif defined(CADENCE) # define NEED_EXTERNS #else # error "Unknown simulator for DPI test" #endif // clang-format on #include "verilated.h" #ifdef NEED_EXTERNS extern "C" { extern void t_embed_child_initial(); extern void t_embed_child_final(); extern void t_embed_child_eval(); extern void t_embed_child_io_eval(); // TODO real function params here } #endif //====================================================================== extern int T_Embed_Child_Unique; int T_Embed_Child_Unique = 0; // Address used for uniqueness Vt_embed1_child* __get_modelp() { svScope scope = svGetScope(); if (!scope) { vl_fatal(__FILE__, __LINE__, __FILE__, "svGetScope failed"); return nullptr; } void* __modelp = svGetUserData(scope, &T_Embed_Child_Unique); if (!__modelp) { // Create the model const char* scopenamep = svGetNameFromScope(scope); if (!scopenamep) vl_fatal(__FILE__, __LINE__, __FILE__, "svGetNameFromScope failed"); __modelp = new Vt_embed1_child{scopenamep}; if (svPutUserData(scope, &T_Embed_Child_Unique, __modelp)) { vl_fatal(__FILE__, __LINE__, __FILE__, "svPutUserData failed"); } } return reinterpret_cast(__modelp); } void __delete_modelp() { svScope scope = svGetScope(); if (!scope) { vl_fatal(__FILE__, __LINE__, __FILE__, "svGetScope failed"); return; } void* __modelp = svGetUserData(scope, &T_Embed_Child_Unique); if (__modelp) { delete reinterpret_cast(__modelp); __modelp = nullptr; if (svPutUserData(scope, &T_Embed_Child_Unique, __modelp)) { vl_fatal(__FILE__, __LINE__, __FILE__, "svPutUserData failed"); } } } void t_embed_child_initial() { VL_DEBUG_IF(VL_PRINTF(" t_embed1_child_initial\n");); Vt_embed1_child* __modelp = __get_modelp(); __modelp->eval(); } void t_embed_child_final() { VL_DEBUG_IF(VL_PRINTF(" t_embed1_child_final\n");); Vt_embed1_child* __modelp = __get_modelp(); __modelp->final(); __delete_modelp(); } void t_embed_child_eval() { VL_DEBUG_IF(VL_PRINTF(" t_embed1_child_eval\n");); Vt_embed1_child* __modelp = __get_modelp(); __modelp->eval(); } void t_embed_child_io_eval(unsigned char clk, unsigned char bit_in, const svBitVecVal* vec_in, const svBitVecVal* wide_in, unsigned char is_ref, unsigned char* bit_out, svBitVecVal* vec_out, svBitVecVal* wide_out, unsigned char* did_init_out) { VL_DEBUG_IF(VL_PRINTF(" t_embed1_child_io_eval\n");); Vt_embed1_child* __modelp = __get_modelp(); VL_DEBUG_IF(VL_PRINTF("[%0ld] in clk=%x b=%x V=%x R=%x\n", // (long int)(VL_TIME_Q()), clk, bit_in, vec_in[0], is_ref);); __modelp->clk = clk; __modelp->bit_in = bit_in; __modelp->vec_in = vec_in[0]; __modelp->wide_in[0] = wide_in[0]; __modelp->wide_in[1] = wide_in[1]; __modelp->wide_in[2] = wide_in[2]; __modelp->wide_in[3] = wide_in[3]; __modelp->is_ref = is_ref; // __modelp->eval(); // TODO maybe we should look at a "change detect" to know if we need to copy // out the variables; can return this value to the caller verilog code too // *bit_out = __modelp->bit_out; vec_out[0] = __modelp->vec_out; wide_out[0] = __modelp->wide_out[0]; wide_out[1] = __modelp->wide_out[1]; wide_out[2] = __modelp->wide_out[2]; wide_out[3] = __modelp->wide_out[3]; *did_init_out = __modelp->did_init_out; VL_DEBUG_IF(VL_PRINTF("[%0ld] out b=%x V=%x DI=%x\n", // (long int)(VL_TIME_Q()), *bit_out, *vec_out, *did_init_out);); } verilator-5.042/test_regress/t/t_case_string.py0000755000542200017500000000073415101701376022273 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_strength_bufif1.py0000755000542200017500000000077315101701376023067 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_randomize_this.py0000755000542200017500000000073415101701376023011 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_param_type_id_bad.py0000755000542200017500000000077615101701376023423 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_runflag_bad.py0000755000542200017500000000226415101701376022236 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile() test.execute(all_run_flags=["+verilator+bad+flag+testing"], fails=True, expect_filename="t/" + test.name + "__a.out") test.execute(all_run_flags=["+verilator+rand+reset+-1"], fails=True, expect_filename="t/" + test.name + "__b.out") test.execute(all_run_flags=["+verilator+rand+reset+3"], fails=True, expect_filename="t/" + test.name + "__c.out") test.execute(all_run_flags=["+verilator+prof+exec+window+0"], fails=True, expect_filename="t/" + test.name + "__d.out") test.execute(all_run_flags=["+verilator+prof+exec+window+1000000000000000000000000"], fails=True, expect_filename="t/" + test.name + "__e.out") test.passes() verilator-5.042/test_regress/t/t_opt_merge_cond_no_merge.py0000755000542200017500000000163515101701376024632 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_opt_merge_cond.v" test.compile(verilator_flags2=["-unroll-count 64", "--stats", "-fno-merge-cond"]) test.execute() if test.vlt: # Note, with vltmt this might be split differently, so only checking vlt test.file_grep_not(test.stats, r'Optimizations, MergeCond merges\s+(\d+)') test.file_grep_not(test.stats, r'Optimizations, MergeCond merged items\s+(\d+)') test.file_grep_not(test.stats, r'Optimizations, MergeCond longest merge\s+(\d+)') test.passes() verilator-5.042/test_regress/t/t_attr_parenstar.v0000644000542200017500000000143615101701376022635 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; always @(*) begin if (clk) begin end end always @(* ) begin if (clk) begin end end // Not legal in some simulators, legal in others // always @(* /*cmt*/ ) begin // if (clk) begin end // end // Not legal in some simulators, legal in others // always @(* // cmt // ) begin // if (clk) begin end // end always @ (* ) begin if (clk) begin end end initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_interface_virtual_unused.v0000644000542200017500000000062515101701376024674 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Arkadiusz Kozdra. // SPDX-License-Identifier: CC0-1.0 // See also t_interface_virtual.v interface QBus(); endinterface module t; virtual QBus q8; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_param_passed_to_port.v0000644000542200017500000000115415101701376024006 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 parameter int HwDataAttr[1] = '{1}; module flash_mp_data_region_sel ( input int region_attrs_i[1] ); initial begin int o = 0; for (int i = 0; i < 1; i++) begin o = region_attrs_i[i]; end if (o != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module t; flash_mp_data_region_sel u_hw_sel (.region_attrs_i(HwDataAttr)); endmodule verilator-5.042/test_regress/t/t_preproc_cmtend_bad.out0000644000542200017500000000030415101701376023751 0ustar mahmoudyfreeshell%Error: t/t_preproc_cmtend_bad.v:10:1: EOF in '/* ... */' block comment ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_gen_index.py0000755000542200017500000000071415101701376021730 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.passes() verilator-5.042/test_regress/t/t_preproc_inc3.vh0000644000542200017500000000120615101701376022335 0ustar mahmoudyfreeshell// DESCRIPTION: Verilog::Preproc: Example source code // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2000-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `ifndef _EXAMPLE_INC2_V_ `define _EXAMPLE_INC2_V_ 1 `define _EMPTY // FOO At file `__FILE__ line `__LINE__ `line `__LINE__ "inc3_a_filename_from_line_directive_with_LINE" 0 At file `__FILE__ line `__LINE__ `line 100 "inc3_a_filename_from_line_directive" 0 At file `__FILE__ line `__LINE__ `else `error "INC2 File already included once" `endif // guard `ifdef not_defined `include "NotToBeInced.vh" `endif verilator-5.042/test_regress/t/t_flag_wfatal.py0000755000542200017500000000107415101701376022237 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_flag_wfatal.v" test.lint(verilator_flags2=["--lint-only -Wno-fatal"], expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_opt_table_sparse_output_split.py0000755000542200017500000000234015101701376026146 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_opt_table_sparse.v" test.golden_filename = "t/t_opt_table_sparse.out" def check_splits(expected): n = 0 for filename in test.glob_some(test.obj_dir + "/*.cpp"): if re.search(r'__ConstPool_', filename): n += 1 if n != expected: test.error("__ConstPool*.cpp not split: " + str(n)) test.compile(verilator_flags2=["--stats", "--output-split 1"]) if test.vlt_all: test.file_grep(test.stats, r'Optimizations, Tables created\s+(\d+)', 1) test.file_grep(test.stats, r'ConstPool, Tables emitted\s+(\d+)', 2) # Splitting should set VM_PARALLEL_BUILDS to 1 by default test.file_grep(test.obj_dir + "/" + test.vm_prefix + "_classes.mk", r'VM_PARALLEL_BUILDS\s*=\s*1') check_splits(2) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_pp_misdef_bad.v0000644000542200017500000000061615101701376022357 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; `define DEFINED // NDEFINED isn't defined here: `NDEFINED // Botched directive (`timescale) `imescale initial $stop; // Should have failed endmodule verilator-5.042/test_regress/t/t_interface_dearray.py0000755000542200017500000000073415101701376023441 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_mod_mod.v0000644000542200017500000000066215101701376021222 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module m(); module m_in_m; endmodule program p_in_m(); endprogram interface i_in_m(); endinterface endmodule interface i(); interface i_in_i(); endinterface program p_in_i(); endprogram endinterface verilator-5.042/test_regress/t/t_lint_blkseq_loop.py0000755000542200017500000000100015101701376023315 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--lint-only -Wwarn-BLKSEQ -Wwarn-COMBDLY"]) test.passes() verilator-5.042/test_regress/t/t_virtual_interface_member_trigger.v0000755000542200017500000000353115101701376026365 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by PlanV GmbH. // SPDX-License-Identifier: CC0-1.0 `timescale 1ns/1ps interface INTF; logic x; logic y; logic z; logic [7:0] data; endinterface class Dummy; virtual INTF vif; function new(virtual INTF vif); this.vif = vif; endfunction task write_data(logic [7:0] d); vif.data = d; endtask endclass module t_virtual_interface_member_trigger(); // === Part 1: logic trigger false loop test === logic s1, s2, src_val; INTF intf_loop(); virtual INTF vif_loop; assign intf_loop.x = s1; assign intf_loop.y = src_val; assign intf_loop.z = !intf_loop.y; assign s2 = intf_loop.z; assign s1 = s2; // === Part 2: data transfer chain test === logic [7:0] data; INTF intf_read(); INTF intf_write(); assign intf_read.data = data; assign data = intf_write.data; virtual INTF vif_read, vif_write; Dummy cl_1, cl_2; initial begin // Test 1: no false loop with member-level trigger #1ns; vif_loop = intf_loop; cl_1 = new(vif_loop); #1ns; src_val = 0; #1ns; if (!(cl_1.vif.x == 1 && cl_1.vif.y == 0 && cl_1.vif.z == 1 && s1 == 1 && s2 == 1)) $stop; // Test 2: write from module #1ns; vif_read = intf_read; vif_write = intf_write; #1ns; vif_write.data = 8'hA5; #1ns; if (vif_read.data !== 8'hA5) $stop; // Test 3: write from class #1ns; cl_2 = new(vif_write); #1ns; cl_2.write_data(8'hB7); #1ns; if (vif_read.data !== 8'hB7) $stop; #5ns; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_covergroup_extends_newfirst.py0000755000542200017500000000070615101701376025637 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.passes() verilator-5.042/test_regress/t/t_lib_prot.v0000644000542200017500000001504115101701376021413 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 `define DRIVE(sig) \ /* Just throw a bunch of bits at the input */ \ /* verilator lint_off WIDTH */ \ sig``_in <= {8{crc}}; \ /* verilator lint_on WIDTH */ `define CHECK(sig) \ if (cyc > 0 && sig``_in != sig``_out) begin \ $display(`"%%Error (%m) sig``_in (0x%0x) != sig``_out (0x%0x)`", \ sig``_in, sig``_out); \ $stop; \ end module t #(parameter GATED_CLK = 0) (/*AUTOARG*/ // Inputs clk ); input clk; localparam last_cyc = `ifdef TEST_BENCHMARK `TEST_BENCHMARK; `else 10; `endif genvar x; generate for (x = 0; x < 2; x = x + 1) begin: gen_loop integer cyc = 0; reg [63:0] crc = 64'h5aef0c8d_d70a4497; logic [31:0] accum_in; logic [31:0] accum_out; logic accum_bypass; logic [31:0] accum_bypass_out; logic [31:0] accum_out_expect; logic [31:0] accum_bypass_out_expect; logic s1_in; logic s1_out; logic s1up_in[2]; logic s1up_out[2]; logic [1:0] s2_in; logic [1:0] s2_out; logic [7:0] s8_in; logic [7:0] s8_out; logic [32:0] s33_in; logic [32:0] s33_out; logic [63:0] s64_in; logic [63:0] s64_out; logic [64:0] s65_in; logic [64:0] s65_out; logic [128:0] s129_in; logic [128:0] s129_out; logic [3:0] [31:0] s4x32_in; logic [3:0] [31:0] s4x32_out; /*verilator lint_off ASCRANGE*/ logic [0:15] s6x16up_in[0:1][2:0]; logic [0:15] s6x16up_out[0:1][2:0]; /*verilator lint_on ASCRANGE*/ logic [15:0] s8x16up_in[1:0][0:3]; logic [15:0] s8x16up_out[1:0][0:3]; logic [15:0] s8x16up_3d_in[1:0][0:1][0:1]; logic [15:0] s8x16up_3d_out[1:0][0:1][0:1]; wire clk_en = crc[0]; secret secret ( .accum_in, .accum_out, .accum_bypass, .accum_bypass_out, .s1_in, .s1_out, .s1up_in, .s1up_out, .s2_in, .s2_out, .s8_in, .s8_out, .s33_in, .s33_out, .s64_in, .s64_out, .s65_in, .s65_out, .s129_in, .s129_out, .s4x32_in, .s4x32_out, .s6x16up_in, .s6x16up_out, .s8x16up_in, .s8x16up_out, .s8x16up_3d_in, .s8x16up_3d_out, .clk_en, .clk); always @(posedge clk) begin `ifdef TEST_VERBOSE $display("[%0t] x=%0d, cyc=%0d accum_in=%0d accum_out=%0d accum_bypass_out=%0d", $time, x, cyc, accum_in, accum_out, accum_bypass_out); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; accum_in <= accum_in + 5; `DRIVE(s1) `DRIVE(s2) `DRIVE(s8) `DRIVE(s33) `DRIVE(s64) `DRIVE(s65) `DRIVE(s129) `DRIVE(s4x32) {s1up_in[1], s1up_in[0]} <= {^crc, ~(^crc)}; {s6x16up_in[0][0], s6x16up_in[0][1], s6x16up_in[0][2]} <= crc[47:0]; {s6x16up_in[1][0], s6x16up_in[1][1], s6x16up_in[1][2]} <= ~crc[63:16]; {s8x16up_in[0][0], s8x16up_in[0][1], s8x16up_in[0][2], s8x16up_in[0][3]} <= crc; {s8x16up_in[1][0], s8x16up_in[1][1], s8x16up_in[1][2], s8x16up_in[1][3]} <= ~crc; {s8x16up_3d_in[0][0][0], s8x16up_3d_in[0][0][1]} <= ~crc[31:0]; {s8x16up_3d_in[0][1][0], s8x16up_3d_in[0][1][1]} <= ~crc[63:32]; {s8x16up_3d_in[1][0][0], s8x16up_3d_in[1][0][1]} <= crc[31:0]; {s8x16up_3d_in[1][1][0], s8x16up_3d_in[1][1][1]} <= crc[63:32]; if (cyc == 0) begin accum_in <= x*100; accum_bypass <= '0; end else if (cyc > 0) begin if (accum_out_expect != accum_out) begin $display("%%Error: (%m) accum_out expected %0d got %0d", accum_out_expect, accum_out); $stop; end if (accum_bypass_out_expect != accum_bypass_out) begin $display("%%Error: (%m) accum_bypass_out expected %0d got %0d", accum_bypass_out_expect, accum_bypass_out); $stop; end end if (cyc == 5) accum_bypass <= '1; if (x == 0 && cyc == last_cyc) begin $display("final cycle = %0d", cyc); $write("*-* All Finished *-*\n"); $finish; end end logic possibly_gated_clk; if (GATED_CLK != 0) begin: yes_gated_clock logic clk_en_latch; // verilator lint_off COMBDLY,LATCH always_comb if (clk == '0) clk_en_latch <= clk_en; // verilator lint_on COMBDLY,LATCH assign possibly_gated_clk = clk & clk_en_latch; end else begin: no_gated_clock assign possibly_gated_clk = clk; end always @(posedge possibly_gated_clk) begin // 7 is the secret_value inside the secret module accum_out_expect <= accum_in + accum_out_expect + 7; end always @(*) begin // XSim (and maybe all event simulators?) sees the moment where // s1_in has not yet propagated to s1_out, however, they do always // both change at the same time /* verilator lint_off STMTDLY */ #1; /* verilator lint_on STMTDLY */ `CHECK(s1) `CHECK(s1up) `CHECK(s2) `CHECK(s8) `CHECK(s33) `CHECK(s64) `CHECK(s65) `CHECK(s129) `CHECK(s4x32) `CHECK(s6x16up) `CHECK(s8x16up) `CHECK(s8x16up_3d) end assign accum_bypass_out_expect = accum_bypass ? accum_in : accum_out_expect; end endgenerate endmodule verilator-5.042/test_regress/t/t_disable_outside.py0000755000542200017500000000101315101701376023120 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(timing_loop=True, verilator_flags2=["--timing"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_duplicated_gen_blocks_bad.py0000755000542200017500000000076615101701376025111 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_pgo_profoutofdate_bad.py0000755000542200017500000000100315101701376024314 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vltmt') test.compile(threads=2, fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_force_chained.v0000644000542200017500000000173415101701376022356 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); end while(0) module t; reg [1:0] a; wire [1:0] b = 1; bit [1:0] c; initial begin #1 a = 0; force b = a; force c = b; `checkh(a, 0); `checkh(b, 0); `checkh(c, 0); a = 1; #1; `checkh(a, 1); `checkh(b, 1); // TODO implement inter-dependency resolution between force statements `checkh(c, 1); a = 2; #1; `checkh(a, 2); `checkh(b, 2); `checkh(c, 2); a = 3; c = 3; #1; `checkh(a, 3); `checkh(b, 3); `checkh(c, 3); release b; release c; `checkh(a, 3); `checkh(b, 1); `checkh(c, 3); #1 $finish; end endmodule verilator-5.042/test_regress/t/t_vpi_unimpl.v0000644000542200017500000000206115101701376021761 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2010 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VERILATOR //We call it via $c so we can verify DPI isn't required - see bug572 `else import "DPI-C" context function int mon_check(); `endif module t (/*AUTOARG*/ // Inputs clk ); `ifdef VERILATOR `systemc_header extern "C" int mon_check(); `verilog `endif input clk; reg onebit /*verilator public_flat_rw @(posedge clk) */; integer status; // Test loop initial begin `ifdef VERILATOR status = $c32("mon_check()"); `else status = mon_check(); `endif if (status != 0) begin $write("%%Error: t_vpi_unimpl.cpp:%0d: C Test failed\n", status); $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule : t verilator-5.042/test_regress/t/t_math_signed_noexpand.py0000755000542200017500000000103615101701376024144 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_math_signed.v" test.compile(verilator_flags2=['-fno-expand']) test.execute() test.passes() verilator-5.042/test_regress/t/t_constraint_dyn_queue_basic.v0000755000542200017500000000630715101701376025214 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by PlanV GmbH. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); class ConstrainedDynamicQueueArray; rand int queue_1d[$]; rand int queue[$][$]; rand int dyn[][]; rand int queue_dyn[$][]; rand int dyn_queue[][$]; rand int queue_unp[$][3]; rand int unp_queue[3][$]; rand int \array_w[ith_es]cape [3][2]; // Constraints for the queues and dynamic arrays constraint queue_constraints { foreach (queue_1d[i]) queue_1d[i] == i + 2; foreach (queue[i, j]) queue[i][j] == (2 * i) + j; } constraint dyn_constraints { dyn[0][0] == 10; dyn[1][0] inside {20, 30, 40}; dyn[1][1] > 50; dyn[0][1] < 100; dyn[0][2] inside {5, 15, 25}; } constraint queue_dyn_constraints { foreach (queue_dyn[i, j]) queue_dyn[i][j] == i + j + 3; } constraint dyn_queue_constraints { foreach (dyn_queue[i, j]) dyn_queue[i][j] == (3 * i) + j + 2; } constraint unp_queue_constraints { foreach (unp_queue[i, j]) unp_queue[i][j] == (i * 5) + j + 1; } constraint array_with_escape_constraints { \array_w[ith_es]cape [0][0] == 6; } // Constructor function new(); queue_1d = {1, 2, 3, 4}; queue = '{ '{1, 2}, '{3, 4, 5}, '{6}}; dyn = new[2]; dyn[0] = new[3]; dyn[1] = new[4]; queue_dyn = {}; queue_dyn[0] = new[3]; queue_dyn[1] = new[4]; dyn_queue = new[2]; dyn_queue[0] = {7, 8, 9}; dyn_queue[1] = {10}; queue_unp = {}; unp_queue[0] = {17, 18}; unp_queue[1] = {19}; unp_queue[2] = {20}; endfunction // Self-check function function void check(); foreach (queue_1d[i]) `checkh(queue_1d[i], i + 2) foreach (queue[i, j]) `checkh(queue[i][j], (2 * i) + j) `checkh(dyn[0][0], 10) `checkh(dyn[1][0] inside {20, 30, 40}, 1'b1) `checkh(dyn[1][1] > 50, 1'b1) `checkh(dyn[0][1] < 100, 1'b1) `checkh(dyn[0][2] inside {5, 15, 25}, 1'b1) foreach (queue_dyn[i, j]) `checkh(queue_dyn[i][j], i + j + 3) foreach (dyn_queue[i, j]) `checkh(dyn_queue[i][j], (3 * i) + j + 2) `checkh(unp_queue[0][0], (0 * 5) + 0 + 1) `checkh(unp_queue[0][1], (0 * 5) + 1 + 1) `checkh(unp_queue[1][0], (1 * 5) + 0 + 1) `checkh(unp_queue[2][0], (2 * 5) + 0 + 1) `checkh(\array_w[ith_es]cape [0][0], 6) endfunction endclass module t_constraint_dyn_queue_basic; ConstrainedDynamicQueueArray array_test; int success; initial begin $display("Test: Randomization for dynamic and mixed queues and arrays:"); array_test = new(); repeat(2) begin success = array_test.randomize(); `checkh(success, 1) array_test.check(); end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_difftree.py0000755000542200017500000000161015101701376021554 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') if not os.path.exists(os.environ["VERILATOR_ROOT"] + "/bin/verilator_difftree"): test.skip("No verilator_difftree available") test.run(cmd=[ "cd " + test.obj_dir + " && " + os.environ["VERILATOR_ROOT"] + "/bin/verilator_difftree", test.t_dir + "/t_difftree.a.tree", test.t_dir + "/t_difftree.b.tree > diff.log" ], fails=1) # Testing mismatch, so exit code 1 test.files_identical(test.obj_dir + "/diff.log", test.golden_filename, 'logfile') test.passes() verilator-5.042/test_regress/t/t_mod_interface_array4.v0000644000542200017500000000331015101701376023656 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) interface intf (); integer index; endinterface module t ( clk ); input clk; intf ifa1_intf[2:1](); intf ifa2_intf[2:1](); intf ifb1_intf[1:2](); intf ifb2_intf[1:2](); int cyc; sub sub ( .clk, .cyc, .alh(ifa1_intf), .ahl(ifa2_intf), .blh(ifb1_intf), .bhl(ifb2_intf) ); always @(posedge clk) begin cyc <= cyc + 1; if (cyc == 1) begin ifa1_intf[1].index = 'h101; ifa1_intf[2].index = 'h102; ifa2_intf[1].index = 'h201; ifa2_intf[2].index = 'h202; ifb1_intf[1].index = 'h301; ifb1_intf[2].index = 'h302; ifb2_intf[1].index = 'h401; ifb2_intf[2].index = 'h402; end end endmodule module sub ( input logic clk, input int cyc, intf alh[1:2], intf ahl[2:1], intf blh[1:2], intf bhl[2:1] ); always @(posedge clk) begin if (cyc == 5) begin `checkh(alh[1].index, 'h102); `checkh(alh[2].index, 'h101); `checkh(ahl[1].index, 'h201); `checkh(ahl[2].index, 'h202); `checkh(blh[1].index, 'h301); `checkh(blh[2].index, 'h302); `checkh(bhl[1].index, 'h402); `checkh(bhl[2].index, 'h401); $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_udp_param_bad.v0000644000542200017500000000064215101701376022360 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Anthony Donlon. // SPDX-License-Identifier: CC0-1.0 module t; wire a, b; udp i_udp (a, b); endmodule primitive udp #( parameter A = 1 ) (o, a); output o; input a; table //o a 0 : 1; 1 : 0; endtable endprimitive verilator-5.042/test_regress/t/t_class_diamond.py0000755000542200017500000000073415101701376022572 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_incorrect_multi_driven.v0000644000542200017500000000222315101701376024350 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2023 by Adrien Le Masle. // SPDX-License-Identifier: CC0-1.0 interface test_if #(parameter int AA = 2, BB=5); logic [AA-1 : 0] a; logic [BB-1 : 0] b; logic c; logic d; modport slave (input a, input b, input c, input d); modport master (output a, output b, output c, output d); endinterface : test_if module test (input logic [28:0] a, output logic [28:0] b); always_comb begin b = a; end endmodule module multi_driven ( input logic [20-1 : 0] data_in, output logic [20-1 : 0] data_out, test_if.slave test_if_in, test_if.master test_if_out ); test test_inst ( .a({data_in, test_if_in.a, test_if_in.b, test_if_in.c, test_if_in.d}), .b({data_out, test_if_out.a, test_if_out.b, test_if_out.c, test_if_out.d})); endmodule; verilator-5.042/test_regress/t/t_protect_ids_debug.py0000755000542200017500000000126115101701376023453 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_protect_ids.v" test.compile(verilator_flags2=[ "--protect-ids", "--protect-key SECRET_KEY", "--trace-vcd", "--debug-protect", "--coverage", "-Wno-INSECURE", ], verilator_make_gmake=False) test.passes() verilator-5.042/test_regress/t/t_class_virtual_bad.py0000755000542200017500000000076315101701376023455 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_case_itemwidth.v0000644000542200017500000000561315101701376022576 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; // Some inputs we'll set to random values reg [6:0] addr; reg [6:0] e0; reg [5:0] e1; reg [5:0] e2; wire [7:0] data; reg [2:0] wrapcheck_a; reg [2:0] wrapcheck_b; test test (/*AUTOINST*/ // Outputs .data (data[7:0]), // Inputs .addr (addr[6:0]), .e0 (e0[6:0]), .e1 (e1[5:0]), .e2 (e2[5:0])); always @(/*AS*/addr) begin case(addr[2:0]) 3'd0+3'd0: wrapcheck_a = 3'h0; 3'd0+3'd1: wrapcheck_a = 3'h1; 3'd0+3'd2: wrapcheck_a = 3'h2; 3'd0+3'd3: wrapcheck_a = 3'h3; default: wrapcheck_a = 3'h4; endcase case(addr[2:0]) 3'd0+0: wrapcheck_b = 3'h0; 3'd1+1: wrapcheck_b = 3'h1; 3'd2+2: wrapcheck_b = 3'h2; 3'd3+3: wrapcheck_b = 3'h3; default: wrapcheck_b = 3'h4; endcase end integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; //$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b); if (cyc==1) begin addr <= 7'h28; e0 <= 7'h11; e1 <= 6'h02; e2 <= 6'h03; end if (cyc==2) begin addr <= 7'h2b; if (data != 8'h11) $stop; end if (cyc==3) begin addr <= 7'h2c; if (data != 8'h03) $stop; if (wrapcheck_a != 3'h3) $stop; if (wrapcheck_b != 3'h4) $stop; end if (cyc==4) begin addr <= 7'h0; if (data != 8'h00) $stop; if (wrapcheck_a != 3'h4) $stop; if (wrapcheck_b != 3'h2) $stop; end if (cyc==5) begin if (data != 8'h00) $stop; end if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule /* verilator lint_off WIDTH */ `define AI 7'h28 module test (/*AUTOARG*/ // Outputs data, // Inputs addr, e0, e1, e2 ); output [7:0] data; input [6:0] addr; input [6:0] e0; input [5:0] e1, e2; reg [7:0] data; always @(/*AS*/addr or e0 or e1 or e2) begin case (addr) `AI: data = {e0[6], 1'b0, e0[5:0]}; `AI+1: data = e1; `AI+2, `AI+3: data = e2; default: data = 0; endcase end endmodule // Local Variables: // eval:(verilog-read-defines) // verilog-auto-sense-defines-constant: t // End: verilator-5.042/test_regress/t/t_time_vpi.v0000644000542200017500000000361015101701376021414 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under The Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `timescale `time_scale_units / `time_scale_prec import "DPI-C" function void dpii_check(); module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; // verilator lint_off REALCVT time digits = 5432109876.543210ns; // Will round to time units realtime rdigits = 5432109876.543210ns; // Will round to time precision time high_acc = 64'd12345678901234567890; // Would lose accuracy if calculated in double // verilator lint_on REALCVT always @ (posedge clk) begin cyc <= cyc + 1; `ifdef TEST_VERBOSE $write("- [%0t] tick\n", $time); `endif if ($time >= 60) begin $write(":: In %m\n"); $printtimescale; $write("[%0t] time%%0d=%0d 123%%0t=%0t\n", $time, $time, 123); $write(" dig%%0t=%0t dig%%0d=%0d\n", digits, digits); $write(" rdig%%0t=%0t rdig%%0f=%0f\n", rdigits, rdigits); $write(" acc%%0t=%0t acc%%0d=%0d\n", high_acc, high_acc); $timeformat(-9, 6, "ns", 16); $write("[%0t] time%%0d=%0d 123%%0t=%0t\n", $time, $time, 123); $write(" dig%%0t=%0t dig%%0d=%0d\n", digits, digits); $write(" rdig%%0t=%0t rdig%%0f=%0f\n", rdigits, rdigits); $write(" acc%%0t=%0t acc%%0d=%0d\n", high_acc, high_acc); $write("[%0t] stime%%0t=%0t stime%%0d=%0d stime%%0f=%0f\n", $time, $stime, $stime, $stime); // verilator lint_off REALCVT $write("[%0t] rtime%%0t=%0t rtime%%0d=%0d rtime%%0f=%0f\n", $time, $realtime, $realtime, $realtime); // verilator lint_on REALCVT dpii_check(); $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_concat_link_bad.py0000755000542200017500000000076615101701376023071 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_param_up_bad.py0000755000542200017500000000076615101701376022411 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_debug_sigsegv_bt_bad.py0000755000542200017500000000146615101701376024105 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') if 'VERILATOR_TEST_NO_GDB' in os.environ: test.skip("Skipping due to VERILATOR_TEST_NO_GDB") if not test.have_gdb: test.skip("No gdb installed") test.lint(verilator_flags2=["--lint-only --debug --gdbbt --debug-sigsegv"], fails='any') test.file_grep(test.compile_log_filename, r'Program received signal SIGSEGV') test.file_grep(test.compile_log_filename, r'in V3Options::') test.passes() verilator-5.042/test_regress/t/t_config_work__libb.v0000644000542200017500000000062515101701376023241 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module m2; m3 u_23(); initial $display("libb:m2 %%m=%m %%l=%l"); endmodule module m3; // Module name duplicated between libraries initial $display("libb:m3 %%m=%m %%l=%l"); endmodule verilator-5.042/test_regress/t/t_randomize_method_with.py0000755000542200017500000000151115101701376024347 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile( # Ensure we test captures of static variables verilator_flags2=["--fno-inline"]) test.execute() for filename in test.glob_some(test.obj_dir + "/" + test.vm_prefix + "*Baz*.cpp"): # Check that "Baz" has no constrained random generator test.file_grep_not(filename, "this->__PVT__constraint") test.passes() verilator-5.042/test_regress/t/t_trace_ub_misaligned_address.v0000644000542200017500000000325315101701376025270 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // When compiled using -fsanitize=address,undefined this triggered: // // verilated_trace_imp.h:875:5: runtime error: store to misaligned address ... // verilated_trace.h:450:31: runtime error: load of misaligned address ... // // due to 32 bit aligned addresses being used for types which require // stricter alignment. // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by John Wehle. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" module t; wire [2:0] out; reg in; reg [39:0] p; reg rst; reg clk; initial begin $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); $dumpvars(0, test); clk = 0; rst = 0; for (int i = 0; i < 2; i++) begin #10 rst = 1; #10 rst = 0; p = 40'b0000000000111111111111111111110000000000; in = i[0]; for (int k = 0; k < 31; k++) begin in = p[39 - k] ^ i[0]; #1; end end #30 $write("*-* All Finished *-*\n"); $finish; end always begin #10 clk <= !clk; end Test test(.out(out), .in(in), .clk(clk), .rst(rst)); endmodule module Test(/*AUTOARG*/ // Outputs out, // Inputs clk, in, rst ); input clk; input in; input rst; output wire [2:0] out; reg [2:0] s; reg sin; assign out = s; always @(posedge clk, posedge rst) begin s[0] <= s[2]; s[2] <= in; s[1] <= sin; end always @(negedge clk, posedge rst) if (rst) sin <= 1'b0; else sin <= in; endmodule verilator-5.042/test_regress/t/t_trace_two_hdr_cc.py0000755000542200017500000000246515101701376023266 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Test tracing with two models instanced import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t_trace_two_a.v" test.pli_filename = "t/t_trace_two_cc.cpp" test.compile(make_main=False, verilator_make_gmake=False, top_filename='t_trace_two_b.v', vm_prefix='Vt_trace_two_b', verilator_flags2=['-trace']) test.run(logfile=test.obj_dir + "/make_first_ALL.log", cmd=[ os.environ["MAKE"], "-C", test.obj_dir, "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp" ]) test.compile(make_main=False, top_filename='t_trace_two_a.v', make_flags=['CPPFLAGS_ADD=-DTEST_HDR_TRACE=1'], verilator_flags2=['-exe', '-trace', test.pli_filename]) test.execute() if test.vlt_all: test.file_grep(test.trace_filename, r'\$enddefinitions') test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_typedef_param.py0000755000542200017500000000073415101701376022612 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_member_bad2.py0000755000542200017500000000076615101701376023323 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_randomize_complex_dynamic_arrays.v0000644000542200017500000000250515101701376026406 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class SubClass; rand bit [2:0] field; function new (); field = 0; endfunction endclass class MyClass; SubClass sc_inst2[]; function new (); sc_inst2 = new [7]; sc_inst2[1] = new; endfunction endclass; class Deep; MyClass sc_inst1; function new (); sc_inst1 = new; endfunction endclass; class WeNeedToGoDeeper; Deep sc_inst; function new (); sc_inst = new; endfunction endclass; module t; initial begin WeNeedToGoDeeper cl_inst[]; MyClass cl_inst2[]; cl_inst = new [3]; cl_inst2 = new [5]; cl_inst[1] = new; cl_inst2[0] = new; if (cl_inst[1].sc_inst.sc_inst1.sc_inst2[1].randomize() with {field inside {1, 2, 3};} == 0) begin $stop; end if (cl_inst[1].sc_inst.sc_inst1.sc_inst2[1].field < 1 || cl_inst[1].sc_inst.sc_inst1.sc_inst2[1].field > 3) begin $stop; end if (cl_inst2[0].sc_inst2[1].randomize() with {field inside {1, 2, 3};} == 0) begin $stop; end if (cl_inst2[0].sc_inst2[1].field < 1 || cl_inst2[0].sc_inst2[1].field > 3) begin $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_param_array6.v0000644000542200017500000000322115101701376022162 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Anderson Ignacio da Silva. // SPDX-License-Identifier: CC0-1.0 package test_pkg; localparam [31:0] test_arr [4][4:0] = '{ '{'h0000, 'h1000, 'h2000, 'h3000, 'h4000}, '{'h0FFF, 'h1FFF, 'h2FFF, 'h3FFF, 'h4FFF}, '{ 'd0, 'd0, 'd0, 'd0, 'd0}, '{ 'd0, 'd1, 'd2, 'd3, 'd4} }; typedef struct packed{ logic [7:0] val_1; logic [7:0] val_2; } test_ret_t; endpackage module t import test_pkg::*; (clk); input clk; function automatic test_ret_t test_f(logic [31:0] val); test_ret_t temp; temp = test_ret_t'(0); for (int i=0; i<5; i++) begin if (val >= test_arr[0][i] && val <= test_arr[1][i]) begin temp.val_1 = test_arr[2][i][7:0]; temp.val_2 = test_arr[3][i][7:0]; end end return temp; endfunction test_ret_t temp; logic [31:0] random; int cyc; bit [63:0] sum; always @ (posedge clk) begin cyc <= cyc + 1; random <= {17'b0, cyc[3:0], 11'b0}; temp <= test_f(random); `ifdef TEST_VERBOSE $display("rand: %h / Values -> val_1: %d / val_2: %d", random, temp.val_1, temp.val_2); `endif if (cyc > 10 && cyc < 90) begin sum <= {48'h0, temp} ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; end else if (cyc == 99) begin $displayh(sum); if (sum != 64'h74d34ea7a775f994) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_order_dpi_export_1.cpp0000644000542200017500000000212715101701376023707 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2021 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include #include #include int main(int argc, char* argv[]) { VM_PREFIX* const tb = new VM_PREFIX; tb->contextp()->commandArgs(argc, argv); bool clk = true; while (!tb->contextp()->gotFinish()) { // Timeout if (tb->contextp()->time() > 100000) break; // Toggle and set clock svSetScope(svGetScopeFromName("TOP.testbench")); clk = !clk; set_clk(clk); // Eval tb->eval(); // Advance time tb->contextp()->timeInc(500); } delete tb; return 0; } verilator-5.042/test_regress/t/t_fork_block_item_declaration.v0000644000542200017500000000137215101701376025301 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 static int counts[10]; class Foo; static task do_something(); for (int i = 0; i < 10; i++) frk : fork int ii = i; #(10 + i) begin $display("i: %d, ii: %d", i, ii); if (counts[ii]++ != 0) $stop; end join_none : frk endtask endclass module t(); initial begin int desired_counts[10] = '{10{1}}; counts = '{10{0}}; Foo::do_something(); #20; if (counts != desired_counts) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_trace_ena_sc.py0000755000542200017500000000142015101701376022371 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_ena.v" if not test.have_sc: test.skip("No SystemC installed") test.compile(verilator_flags2=['-trace -sc']) test.execute() if test.vlt_all: # Note more checks in _cc.py test.file_grep(test.trace_filename, r'\$enddefinitions') test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_altera_lpm_ff.py0000755000542200017500000000111115101701376022553 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) test.compile(verilator_flags2=["--top-module", module]) test.passes() verilator-5.042/test_regress/t/t_genvar_misuse_bad.py0000755000542200017500000000076615101701376023454 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_implicit_port.py0000755000542200017500000000075015101701376023674 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["-Wno-IMPLICIT"]) test.passes() verilator-5.042/test_regress/t/t_event_control_scope_var.v0000644000542200017500000000230015101701376024515 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module test_mod(input reg clk, input reg reset, output integer result); always @(reset) begin result <= 1; end endmodule module Dut(input clk); int num; integer result1; integer result2; reg reset1; reg reset2; initial begin reset1 = $random; reset2 = $random; end always @(posedge clk) begin num <= num + 1; if (num == 5) begin reset1 <= 1'b1; end if (num == 10) begin // display to prevent optimalization $display("result1: %d", result1); $display("result2: %d", result2); $write("*-* All Finished *-*\n"); $finish; end end always @(reset1) begin reset2 <= t.reset; end test_mod t ( .clk(clk), .reset(reset1), .result(result1) ); test_mod t2 ( .clk(clk), .reset(reset2), .result(result2)); endmodule module Dut_wrapper(input clk); Dut d(.clk(clk)); Dut d2(.clk(clk)); endmodule module t (/*AUTOARG*/ clk); input clk; Dut_wrapper d_w(.clk(clk)); endmodule verilator-5.042/test_regress/t/t_tri_top_en_out.py0000755000542200017500000000114115101701376023014 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe --timing --pins-inout-enables", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_var_overwidth_bad.py0000755000542200017500000000111215101701376023452 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(make_main=False, verilator_flags2=["--exe", test.pli_filename]) test.execute(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_param_bad1.v0000644000542200017500000000056015101701376022755 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls #(parameter PARAMB = 12); endclass module t; Cls #(.PARAMBAD(1)) c; // Bad param name Cls #(13, 1) cd; // Bad param number endmodule verilator-5.042/test_regress/t/t_vlt_legacy.py0000755000542200017500000000077315101701376022126 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=[test.t_dir + "/" + test.name + ".vlt"]) test.passes() verilator-5.042/test_regress/t/t_force_readwrite_unsup.py0000755000542200017500000000103015101701376024356 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.lint(verilator_flags2=['--timing'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface_wire_bad_param.v0000644000542200017500000000056415101701376024561 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface Ifc; endinterface module Sub #(parameter P); Ifc a(); endmodule module t; Sub #(0) sub(); // Issue #5649 wire wbad = sub.a; endmodule verilator-5.042/test_regress/t/t_class_param_subtype2.v0000644000542200017500000000110715101701376023721 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Class1 #(type T); static function int get(); return T::Helper::getter(); endfunction endclass class Class2; typedef Class2 Helper; static function int getter(); return 13; endfunction endclass module t; initial begin if (Class1#(Class2)::get() != 13) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_class_short_circuit.v0000644000542200017500000000135015101701376023645 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class Cls; int x; function new; x = 10; endfunction function bit set_x(int a); x = a; return 1; endfunction function int get_x; return x; endfunction endclass module t; initial begin Cls cls; if (cls != null && cls.x == 10) $stop; if (cls != null && cls.get_x() == 10) $stop; cls = new; if (!cls.set_x(1) || cls.x != 1) $stop; if (!cls.set_x(2) || cls.get_x() != 2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_vpi_get_value_array.v0000644000542200017500000000610515101701376023631 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2024 by Diego Roux. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VERILATOR_COMMENTS `define PUBLIC_FLAT_RD /*verilator public_flat_rd*/ `define PUBLIC_FLAT_RW /*verilator public_flat_rw*/ `else `define PUBLIC_FLAT_RD `define PUBLIC_FLAT_RW `endif module test (); `ifdef VERILATOR `systemc_header extern "C" int mon_check(); `verilog `endif reg [7:0] read_bytes [0:3] `PUBLIC_FLAT_RD; reg [7:0] read_bytes_nonzero_index [1:4] `PUBLIC_FLAT_RD; reg [7:0] read_bytes_rl [3:0] `PUBLIC_FLAT_RD; reg [15:0] read_shorts [0:3] `PUBLIC_FLAT_RD; reg [31:0] read_words [0:3] `PUBLIC_FLAT_RD; reg [31:0] read_words_rl [3:0] `PUBLIC_FLAT_RD; reg [63:0] read_longs [0:3] `PUBLIC_FLAT_RD; integer read_integers [0:3] `PUBLIC_FLAT_RD; reg [68:0] read_customs [0:3] `PUBLIC_FLAT_RD; reg [68:0] read_customs_nonzero_index_rl [4:1] `PUBLIC_FLAT_RD; reg [7:0] read_scalar `PUBLIC_FLAT_RD; reg [7:0] read_bounds [1:3] `PUBLIC_FLAT_RD; integer status; initial begin read_bytes[0] = 8'had; read_bytes[1] = 8'hde; read_bytes[2] = 8'hef; read_bytes[3] = 8'hbe; read_bytes_rl[3] = 8'had; read_bytes_rl[2] = 8'hde; read_bytes_rl[1] = 8'hef; read_bytes_rl[0] = 8'hbe; read_bytes_nonzero_index[1] = 8'had; read_bytes_nonzero_index[2] = 8'hde; read_bytes_nonzero_index[3] = 8'hef; read_bytes_nonzero_index[4] = 8'hbe; read_shorts[0] = 16'hdead; read_shorts[1] = 16'hbeef; read_shorts[2] = 16'hcafe; read_shorts[3] = 16'hf00d; read_words[0] = 32'hdeadbeef; read_words[1] = 32'hcafef00d; read_words[2] = 32'h00010203; read_words[3] = 32'h04050607; read_integers[0] = 32'hdeadbeef; read_integers[1] = 32'hcafef00d; read_integers[2] = 32'h00010203; read_integers[3] = 32'h04050607; read_longs[0] = 64'hdeadbeefcafef00d; read_longs[1] = 64'h0001020304050607; read_longs[2] = 64'h08090a0b0c0d0e0f; read_longs[3] = 64'h1011121314151617; read_customs[0] = 69'hFAdeadbeefcafef00d; //0x001F'FFFF'FFFF'FFFF'FFFF read_customs[1] = 69'hF50001020304050607; read_customs[2] = 69'h0A08090a0b0c0d0e0f; read_customs[3] = 69'h051011121314151617; read_customs_nonzero_index_rl[4] = 69'hFAdeadbeefcafef00d; //0x001F'FFFF'FFFF'FFFF'FFFF read_customs_nonzero_index_rl[3] = 69'hF50001020304050607; read_customs_nonzero_index_rl[2] = 69'h0A08090a0b0c0d0e0f; read_customs_nonzero_index_rl[1] = 69'h051011121314151617; `ifdef IVERILOG status = $mon_check; `endif `ifdef VERILATOR status = $c32("mon_check()"); `endif if (status != 0) begin $write("%%Error: t_vpi_get_value_array.cpp:%0d: C Test failed\n", status); $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_sys_readmem_bad_notfound.out0000644000542200017500000000013315101701376025171 0ustar mahmoudyfreeshell%Warning: t/t_sys_readmem_bad_NOTFOUND.mem:0: $readmem file not found *-* All Finished *-* verilator-5.042/test_regress/t/t_package_twodeep.v0000644000542200017500000000102115101701376022714 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Jeremy Bennett // SPDX-License-Identifier: CC0-1.0 // See issue #591 package pkg2; parameter PARAM2 = 16; endpackage // pkg2 package pkg1; import pkg2::*; parameter PARAM1 = 8; endpackage // pkg1 module t import pkg1::*; // Test SV 2012 import format ; reg [PARAM1:0] bus1; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_savable_open_bad.py0000755000542200017500000000116215101701376023232 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_savable.v" test.compile(v_flags2=["--savable"], save_time=500) test.execute(all_run_flags=['+save_restore=1'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_foreach_nindex_bad.py0000755000542200017500000000076615101701376023561 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_clocking_unsup1.out0000644000542200017500000000111215101701376023241 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_clocking_unsup1.v:14:15: Unsupported: clocking event edge override 14 | output posedge #1 a; | ^~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_clocking_unsup1.v:15:15: Unsupported: clocking event edge override 15 | output negedge #1 b; | ^~~~~~~ %Error-UNSUPPORTED: t/t_clocking_unsup1.v:16:15: Unsupported: clocking event edge override 16 | output edge #1 b; | ^~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_interface_noinl.py0000755000542200017500000000103215101701376023121 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface.v" test.compile(v_flags2=["-fno-inline"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_wrapper_reuse_context_bad.v0000644000542200017500000000040015101701376025027 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module top; initial $finish; endmodule verilator-5.042/test_regress/t/t_func_while.v0000644000542200017500000000144115101701376021723 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2018 by Julien Margetts. // SPDX-License-Identifier: CC0-1.0 module t #(parameter SZ = 4096) ( input wire clk, output reg [tdw(SZ)-1:0] data ); // bug1330 function integer clog2(input integer value); integer tmp; tmp = value-1; clog2 = 0; for (clog2=0; (tmp>0) && (clog2<32); clog2=clog2+1) tmp = tmp>>1; endfunction function integer tdw(input integer SZ); tdw = clog2(SZ); endfunction integer b; always @(posedge clk) for (b=0; b #include #include #include #include void rngUpdate(uint64_t& x) { x ^= x << 13; x ^= x >> 7; x ^= x << 17; } int main(int, char**) { // Create contexts VerilatedContext ctx; // Create models Vref ref{&ctx}; Vopt opt{&ctx}; uint64_t rand_a = 0x5aef0c8dd70a4497; uint64_t rand_b = 0xf0c0a8dd75ae4497; uint64_t srand_a = 0x000fa8dcc7ae4957; uint64_t srand_b = 0x00fa8dc7ae3c9574; uint64_t arand_a = 0x758c168d16c93a0f; uint64_t arand_b = 0xbe01de017d87355d; for (size_t n = 0; n < 200000; ++n) { // Update rngs rngUpdate(rand_a); rngUpdate(rand_b); rngUpdate(srand_a); rngUpdate(srand_b); rngUpdate(arand_a); rngUpdate(arand_b); // Assign inputs ref.rand_a = opt.rand_a = rand_a; ref.rand_b = opt.rand_b = rand_b; ref.srand_a = opt.srand_a = srand_a; ref.srand_b = opt.srand_b = srand_b; ref.arand_a = opt.arand_a = arand_a; ref.arand_b = opt.arand_b = arand_b; // Evaluate both models ref.eval(); opt.eval(); // Check equivalence #include "checks.h" // increment time ctx.timeInc(1); } std::cout << "*-* All Finished *-*\n"; } verilator-5.042/test_regress/t/t_langext_4.py0000755000542200017500000000105515101701376021654 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_langext_2.v" # This is a compile only test. test.compile(v_flags2=["+1800-2009ext+v"]) test.passes() verilator-5.042/test_regress/t/t_struct_circ_bad.out0000644000542200017500000000047515101701376023302 0ustar mahmoudyfreeshell%Error: t/t_struct_circ_bad.v:11:11: Struct's type is circular: t.t2_t : ... note: In instance 't' 11 | typedef struct packed { | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_param_array4.py0000755000542200017500000000073415101701376022354 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_assoc_compare.v0000644000542200017500000000402515101701376022417 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Check == and != operations performed on associative arrays // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Ilya Barkov. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define check_comp(lhs, rhs, op, exp) if ((exp) != ((lhs) op (rhs))) begin $write("%%Error: %s:%0d: op comparison shall return 'b%x\n", `__FILE__, `__LINE__, (exp)); `stop; end // Two checks because == and != may not be derived from each other `define check_eq(lhs, rhs) `check_comp(lhs, rhs, ==, 1'b1) `check_comp(lhs, rhs, !=, 1'b0) `define check_ne(lhs, rhs) `check_comp(lhs, rhs, ==, 1'b0) `check_comp(lhs, rhs, !=, 1'b1) class Cls; int i; endclass module t; initial begin begin // simple case int assoc1[int]; int assoc2[int]; // Empty are equal `check_eq(assoc1, assoc2) // Make different assoc1[10] = 15; assoc2[-1] = 365; `check_ne(assoc1, assoc2) // Make same assoc1[-1] = 365; assoc2[10] = 15; `check_eq(assoc1, assoc2) // Don't actually change assoc1[-1] = 365; `check_eq(assoc1, assoc2) // Compare different sizes assoc1[3] = 0; `check_ne(assoc1, assoc2) end begin // check that a class as key is fine int assoc1[Cls]; int assoc2[Cls]; Cls a = new; Cls b = new; int t; assoc1[a] = 0; `check_ne(assoc1, assoc2) assoc2[a] = 0; `check_eq(assoc1, assoc2) assoc2.delete(a); assoc2[b] = 0; `check_ne(assoc1, assoc2) end begin // check that a class as value is fine Cls assoc1[int]; Cls assoc2[int]; Cls a = new; Cls b = new; assoc1[1] = a; assoc2[1] = b; `check_ne(assoc1, assoc2) assoc2[1] = a; `check_eq(assoc1, assoc2) end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_dpi_arg_output_type.py0000755000542200017500000000244115101701376024055 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if test.nc: # For NC, compile twice, first just to generate DPI headers test.compile(nc_flags2=[ "+ncdpiheader+" + test.obj_dir + "/dpi-exp.h", "+ncdpiimpheader+" + test.obj_dir + "/dpi-imp.h" ]) test.compile( v_flags2=["t/" + test.name + ".cpp"], # --no-decoration so .out file doesn't comment on source lines verilator_flags2=["-Wall -Wno-DECLFILENAME --no-decoration"], # NC: Gdd the obj_dir to the C include path nc_flags2=["+ncscargs+-I" + test.obj_dir], # ModelSim: Generate DPI header, add obj_dir to the C include path ms_flags2=["-dpiheader " + test.obj_dir + "/dpi.h", "-ccflags -I" + test.obj_dir]) if test.vlt_all: test.files_identical(test.obj_dir + "/" + test.vm_prefix + "__Dpi.h", "t/" + test.name + "__Dpi.out") test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_tri_pullvec_bad.out0000644000542200017500000000147315101701376023305 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_tri_pullvec_bad.v:13:13: Unsupported: Conflicting pull directions. : ... note: In instance 't' 13 | pulldown p1 (w[1]); | ^~ t/t_tri_pullvec_bad.v:12:11: ... Location of conflicting pull. 12 | pullup p0 (w[0]); | ^~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_tri_pullvec_bad.v:14:13: Unsupported: Conflicting pull directions. : ... note: In instance 't' 14 | pulldown p2 (w[2]); | ^~ t/t_tri_pullvec_bad.v:12:11: ... Location of conflicting pull. 12 | pullup p0 (w[0]); | ^~ %Error: Exiting due to verilator-5.042/test_regress/t/t_trace_complex_saif_threads_2.py0000755000542200017500000000126215101701376025551 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_complex.v" test.golden_filename = "t/t_trace_complex_saif.out" test.compile(verilator_flags2=['--cc --trace-saif --trace-threads 2']) test.execute() test.saif_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_pp_misdef_bad.py0000755000542200017500000000076315101701376022550 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_struct_init_bad.py0000755000542200017500000000110615101701376023141 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.top_filename = "t/t_struct_init.v" test.lint(v_flags2=['+define+T_STRUCT_INIT_BAD'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_trace_packed_struct_fst_sc.out0000644000542200017500000000153315101701376025516 0ustar mahmoudyfreeshell$date Sat Apr 5 13:56:26 2025 $end $version fstWriter $end $timescale 1ps $end $scope module top $end $scope module t $end $var wire 1 ! clk $end $var int 32 " cnt [31:0] $end $var parameter 96 # v[0] [95:0] $end $var parameter 96 $ v[1] [95:0] $end $var parameter 96 % v[2] [95:0] $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b000100000000000000000000000000100001000000000000000000000000000100010000000000000000000000000000 % b001000000000000000000000000000100010000000000000000000000000000100100000000000000000000000000000 $ b001100000000000000000000000000100011000000000000000000000000000100110000000000000000000000000000 # b00000000000000000000000000000000 " 0! $end #10 1! b00000000000000000000000000000001 " #15 0! #20 1! b00000000000000000000000000000010 " #25 0! #30 1! b00000000000000000000000000000011 " #35 0! #40 1! #44 verilator-5.042/test_regress/t/t_dos.v0000644000542200017500000000075415101701376020373 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // This file has DOS carrage returns in it! module t (/*AUTOARG*/ // Inputs clk ); input clk; always @ (posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule // This file has DOS carrage returns in it! verilator-5.042/test_regress/t/t_inst_pin_realnreal.out0000644000542200017500000000065015101701376024013 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_inst_pin_realnreal.v:51:32: Unsupported: Output port connection 'out' connects real to non-real : ... note: In instance 't.netlist' 51 | pga_model pga0(.in, .gain, .out(pga_out)); | ^~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_var_ref_noinline.py0000755000542200017500000000104015101701376023300 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 test.top_filename = "t/t_var_ref.v" import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=['+define+T_NOINLINE']) test.execute() test.passes() verilator-5.042/test_regress/t/t_vlt_warn.py0000755000542200017500000000077215101701376021630 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--lint-only -Wall t/t_vlt_warn.vlt"]) test.passes() verilator-5.042/test_regress/t/t_param_unreachable.py0000755000542200017500000000073415101701376023423 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_split.py0000755000542200017500000000100215101701376022277 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--output-split 10']) test.execute() test.passes() verilator-5.042/test_regress/t/t_std_randomize_unsup_bad.out0000644000542200017500000000105315101701376025043 0ustar mahmoudyfreeshell%Warning-CONSTRAINTIGN: t/t_std_randomize_unsup_bad.v:11:16: Unsupported: std::randomize()'s 'with' : ... note: In instance 't' 11 | if (std::randomize(a, b) with { 2 < a; a < 7; b < a; } != 1) $stop; | ^~~~~~~~~ ... For warning description see https://verilator.org/warn/CONSTRAINTIGN?v=latest ... Use "/* verilator lint_off CONSTRAINTIGN */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_forceable_var_cmt_trace.py0000755000542200017500000000146215101701376024604 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.pli_filename = "t/t_forceable_var.cpp" test.top_filename = "t/t_forceable_var.v" test.golden_filename = "t/t_forceable_var_trace.vcd.out" test.compile(make_top_shell=False, make_main=False, verilator_flags2=['-DCMT=1', '--exe', '--trace-vcd', test.pli_filename]) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_struct_packed_init_bad.v0000644000542200017500000000064715101701376024273 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; parameter P = 4'h5; struct packed { bit [3:0] m_lo = P; // Bad bit [3:0] m_hi; } s; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_scheduling_2.v0000644000542200017500000000217415101701376022152 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2022 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VERILATOR // The '$c1(1)' is there to prevent inlining of the signal by V3Gate `define IMPURE_ONE $c(1); `else // Use standard $random (chaces of getting 2 consecutive zeroes is zero). `define IMPURE_ONE |($random | $random); `endif module top( clk ); input clk; reg clk_half = 0; reg [31:0] cyc = 0; reg [31:0] a, b, c; always @(posedge clk) begin $display("tick %d: a: %d, b: %d, c: %d", cyc, a, b, c); // Check invariant if (a !== cyc + 1) $stop; if (b !== cyc + 2) $stop; if (c !== cyc + 2) $stop; // End of test if (cyc == 100) begin $write("*-* All Finished *-*\n"); $finish; end cyc <= cyc + 1; end always @(clk) a = cyc + `IMPURE_ONE; always @(a) b = a + `IMPURE_ONE; assign c = a + `IMPURE_ONE; endmodule verilator-5.042/test_regress/t/t_inside_dyn.py0000755000542200017500000000073415101701376022117 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_array_nocolon_bad.v0000644000542200017500000000123015101701376025267 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Functionally demonstrate an array of interfaces // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Mike Popoloski. // SPDX-License-Identifier: CC0-1.0 interface foo_intf ( input x ); endinterface module foo_subm ( input x ); endmodule module t (); localparam N = 3; wire [2:0] X = 3'b110; // Will cause ASCRANGE warning? foo_intf foos [N] (.x(X)); // bad foo_intf fool [1:3] (.x(X)); // bad foo_intf foom [3:1] (.x(X)); // ok foo_subm subs [N] (.x(X)); // bad foo_subm subl [1:3] (.x(X)); // bad foo_subm subm [3:1] (.x(X)); // ok endmodule verilator-5.042/test_regress/t/t_clk_first.py0000755000542200017500000000100515101701376021742 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["+define+ATTRIBUTES=1"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_generic_bad3.v0000644000542200017500000000105515101701376024126 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 interface inf; int v; endinterface module GenericModule (interface a); initial begin #1; if (a.v != 7) $stop; if (b.k != 9) $stop; end endmodule module t; inf inf_inst(); GenericModule genericModule (inf_inst, inf_inst); initial begin inf_inst.v = 7; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_inst_nansi_param.py0000755000542200017500000000071115101701376023312 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.compile() test.passes() verilator-5.042/test_regress/t/t_gate_inline_wide_exclude_multiple.py0000755000542200017500000000122715101701376026702 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=['--stats', '--expand-limit 5']) test.file_grep(test.stats, r'Optimizations, Gate excluded wide expressions\s+(\d+)', 2) test.file_grep(test.stats, r'Optimizations, Gate sigs deleted\s+(\d+)', 0) test.passes() verilator-5.042/test_regress/t/t_strength_2_uneq_assign.py0000755000542200017500000000076615101701376024452 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_func_default_warn.py0000755000542200017500000000077315101701376023463 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["-Wno-WIDTH"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_preproc_nodef_bad.v0000644000542200017500000000037015101701376023233 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `not_defined module t; endmodule verilator-5.042/test_regress/t/t_mem_bound_bad.v0000644000542200017500000000104315101701376022351 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014 by Jie Xu // SPDX-License-Identifier: CC0-1.0 module t; logic [1:0][31:0] tt; logic [31:0] a; logic [31:0] b; logic [31:0] c; initial begin a = 1; b = 2; c = 3; tt[0] = a; tt[1] = b; tt[2] = c; // Out of bounds if (tt[0]!=a) $stop; if (tt[1]!=b) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_trace_packed_struct_saif.py0000755000542200017500000000114515101701376025002 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_packed_struct.v" test.compile(v_flags2=["--trace-saif"]) test.execute() test.saif_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_opt_0.py0000755000542200017500000000074415101701376021014 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['-O0']) test.passes() verilator-5.042/test_regress/t/t_inst_array_inl1.py0000755000542200017500000000104215101701376023061 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_inst_array.v" test.compile(v_flags2=['+define+USE_INLINE']) test.execute() test.passes() verilator-5.042/test_regress/t/t_selextract_in_paramextends.py0000755000542200017500000000077115101701376025412 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_dfg_multidriver_dfg_bad.out0000644000542200017500000002014215101701376024755 0ustar mahmoudyfreeshell%Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:45:18: Bit [1] of signal 'y' have multiple combinational drivers. This can cause performance degradation. : ... note: In instance 't' t/t_dfg_multidriver_dfg_bad.v:48:24: ... Location of offending driver 48 | {y[1:0], y[2:1]} = i[3:0] + 4'd5; | ^ t/t_dfg_multidriver_dfg_bad.v:48:24: ... Location of offending driver 48 | {y[1:0], y[2:1]} = i[3:0] + 4'd5; | ^ ... For warning description see https://verilator.org/warn/MULTIDRIVEN?v=latest ... Use "/* verilator lint_off MULTIDRIVEN */" and lint_on around source to disable this message. %Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:16:18: Bits [3:1] of signal 'a' have multiple combinational drivers. This can cause performance degradation. : ... note: In instance 't' t/t_dfg_multidriver_dfg_bad.v:17:19: ... Location of offending driver 17 | assign a[3:0] = i[3:0]; | ^ t/t_dfg_multidriver_dfg_bad.v:18:19: ... Location of offending driver 18 | assign a[4:1] = ~i[4:1]; | ^ %Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:16:18: Bit [3] of signal 'a' have multiple combinational drivers. This can cause performance degradation. : ... note: In instance 't' t/t_dfg_multidriver_dfg_bad.v:17:19: ... Location of offending driver 17 | assign a[3:0] = i[3:0]; | ^ t/t_dfg_multidriver_dfg_bad.v:19:17: ... Location of offending driver 19 | assign a[3] = ~i[3]; | ^ %Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:16:18: Bits [7:6] of signal 'a' have multiple combinational drivers. This can cause performance degradation. : ... note: In instance 't' t/t_dfg_multidriver_dfg_bad.v:20:19: ... Location of offending driver 20 | assign a[8:5] = i[8:5]; | ^ t/t_dfg_multidriver_dfg_bad.v:21:19: ... Location of offending driver 21 | assign a[7:6] = ~i[7:6]; | ^ %Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:16:18: Bit [9] of signal 'a' have multiple combinational drivers. This can cause performance degradation. : ... note: In instance 't' t/t_dfg_multidriver_dfg_bad.v:22:17: ... Location of offending driver 22 | assign a[9] = i[9]; | ^ t/t_dfg_multidriver_dfg_bad.v:23:17: ... Location of offending driver 23 | assign a[9] = ~i[9]; | ^ %Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:26:18: Elements [3:0] of signal 'u' have multiple combinational drivers. This can cause performance degradation. : ... note: In instance 't' t/t_dfg_multidriver_dfg_bad.v:27:14: ... Location of offending driver 27 | assign u = j; | ^ t/t_dfg_multidriver_dfg_bad.v:28:14: ... Location of offending driver 28 | assign u = k; | ^ %Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:30:18: Element [1] of signal 'v' have multiple combinational drivers. This can cause performance degradation. : ... note: In instance 't' t/t_dfg_multidriver_dfg_bad.v:31:14: ... Location of offending driver 31 | assign v = j; | ^ t/t_dfg_multidriver_dfg_bad.v:32:13: ... Location of offending driver 32 | assign v[1] = i; | ^ %Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:34:18: Element [0] of signal 'w' have multiple combinational drivers. This can cause performance degradation. : ... note: In instance 't' t/t_dfg_multidriver_dfg_bad.v:35:13: ... Location of offending driver 35 | assign w[0] = i; | ^ t/t_dfg_multidriver_dfg_bad.v:36:14: ... Location of offending driver 36 | assign w = j; | ^ %Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:38:18: Bits [3:2] of signal 'x[3]' have multiple combinational drivers. This can cause performance degradation. : ... note: In instance 't' t/t_dfg_multidriver_dfg_bad.v:39:17: ... Location of offending driver 39 | assign x[3] = i; | ^ t/t_dfg_multidriver_dfg_bad.v:40:22: ... Location of offending driver 40 | assign x[3][3:2] = ~i[1:0]; | ^ %Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:51:18: Bits [2:1] of signal 'z' have multiple combinational drivers. This can cause performance degradation. : ... note: In instance 't' t/t_dfg_multidriver_dfg_bad.v:53:14: ... Location of offending driver 53 | z[2:0] = i[2:0]; | ^ t/t_dfg_multidriver_dfg_bad.v:58:17: ... Location of offending driver 58 | z[3:1] = i[3:1]; | ^ %Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:51:18: Bits [6:5] of signal 'z' have multiple combinational drivers. This can cause performance degradation. : ... note: In instance 't' t/t_dfg_multidriver_dfg_bad.v:57:14: ... Location of offending driver 57 | z[6:4] = i[6:4]; | ^ t/t_dfg_multidriver_dfg_bad.v:54:14: ... Location of offending driver 54 | z[7:5] = i[7:5]; | ^ %Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:51:18: Bit [7] of signal 'z' have multiple combinational drivers. This can cause performance degradation. : ... note: In instance 't' t/t_dfg_multidriver_dfg_bad.v:54:14: ... Location of offending driver 54 | z[7:5] = i[7:5]; | ^ t/t_dfg_multidriver_dfg_bad.v:60:20: ... Location of offending driver 60 | assign z[10:7] = i[10:7]; | ^ %Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:74:18: Bits [5:2] of signal 't.sub_1.a' have multiple combinational drivers. This can cause performance degradation. t/t_dfg_multidriver_dfg_bad.v:63:20: ... Location of offending driver 63 | assign sub_1.a = i; | ^ t/t_dfg_multidriver_dfg_bad.v:75:19: ... Location of offending driver 75 | assign a[5:2] = i[5:2]; | ^ %Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:74:18: Bits [3:2] of signal 't.sub_2.a' have multiple combinational drivers. This can cause performance degradation. t/t_dfg_multidriver_dfg_bad.v:67:25: ... Location of offending driver 67 | assign sub_2.a[3:0] = i[3:0]; | ^ t/t_dfg_multidriver_dfg_bad.v:75:19: ... Location of offending driver 75 | assign a[5:2] = i[5:2]; | ^ %Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:74:18: Bit [5] of signal 't.sub_2.a' have multiple combinational drivers. This can cause performance degradation. t/t_dfg_multidriver_dfg_bad.v:75:19: ... Location of offending driver 75 | assign a[5:2] = i[5:2]; | ^ t/t_dfg_multidriver_dfg_bad.v:66:26: ... Location of offending driver 66 | assign sub_2.a[10:5] = i[10:5]; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_array_pattern_scalar_bad.py0000755000542200017500000000076615101701376025005 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dpi_argtype_bad.v0000644000542200017500000000076015101701376022720 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2021 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; typedef struct { string a; string b; } foo_t; import "DPI-C" task dpix_twice(foo_t arg); initial begin $stop; end endmodule verilator-5.042/test_regress/t/t_randomize_method_constraints.py0000755000542200017500000000104615101701376025746 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_lib_prot_inout_bad.v0000644000542200017500000000061115101701376023434 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 module secret_impl ( input a, input oe, inout z, output y); assign z = oe ? a : 1'bz; assign y = z; endmodule verilator-5.042/test_regress/t/t_func_ref_bad.out0000644000542200017500000000042215101701376022535 0ustar mahmoudyfreeshell%Error: t/t_func_ref_bad.v:19:22: Function/task ref argument is not of allowed type 19 | b = cls.get_x(a[1]); | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_dpi_context_c.cpp0000644000542200017500000001024515101701376022741 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "svdpi.h" #include //====================================================================== // clang-format off #if defined(VERILATOR) # ifdef T_DPI_CONTEXT_NOOPT # include "Vt_dpi_context_noopt__Dpi.h" # else # include "Vt_dpi_context__Dpi.h" # endif #elif defined(VCS) # include "../vc_hdrs.h" #elif defined(CADENCE) # define NEED_EXTERNS #else # error "Unknown simulator for DPI test" #endif #ifdef VERILATOR # include "verilated.h" #endif // clang-format on #ifdef NEED_EXTERNS extern "C" { extern int dpic_line(); extern int dpic_save(int value); extern int dpic_restore(); extern unsigned dpic_getcontext(); extern unsigned dpic_get1(); } #endif //====================================================================== int dpic_line() { svScope scope = svGetScope(); if (!scope) { printf("%%Warning: svGetScope failed\n"); return 0; } #ifdef VERILATOR static int didDump = 0; if (didDump++ == 0) Verilated::scopesDump(); #endif const char* scopenamep = svGetNameFromScope(scope); if (!scopenamep) { printf("%%Warning: svGetNameFromScope failed\n"); return 0; } if (scope != svGetScopeFromName(scopenamep)) { printf("%%Warning: svGetScopeFromName repeat failed\n"); return 0; } const char* filenamep = ""; int lineno = 0; if (svGetCallerInfo(&filenamep, &lineno)) { printf("Call from %s:%d:%s\n", filenamep, lineno, scopenamep); } else { printf("%%Warning: svGetCallerInfo failed\n"); return 0; } (void)svGetCallerInfo(nullptr, nullptr); // Check doesn't segflt return lineno; } extern int Dpic_Unique; int Dpic_Unique = 0; // Address used for uniqueness extern int Dpic_Value; int Dpic_Value = 0; // Address used for testing int dpic_save(int value) { svScope scope = svGetScope(); if (!scope) { printf("%%Warning: svGetScope failed\n"); return 0; } // Use union to avoid cast to different size pointer warnings union valpack { void* ptr; int i; } vp; // Load the value here, and below, to test we can reinsert correctly if (svPutUserData(scope, &Dpic_Unique, &Dpic_Value)) { printf("%%Warning: svPutUserData failed (initial)\n"); return 0; } if (void* userp = svGetUserData(scope, &Dpic_Unique)) { if (userp != &Dpic_Value) { printf("%%Warning: svGetUserData failed (initial wrong data)\n"); return 0; } } else { printf("%%Warning: svGetUserData failed (initial)\n"); return 0; } vp.i = value; (void)vp.i; if (svPutUserData(scope, &Dpic_Unique, vp.ptr)) { printf("%%Warning: svPutUserData failed\n"); return 0; } return 1; } int dpic_restore() { svScope scope = svGetScope(); if (!scope) { printf("%%Warning: svGetScope failed\n"); return 0; } if (void* userp = svGetUserData(scope, (void*)&Dpic_Unique)) { // Use union to avoid cast to different size pointer warnings union valpack { void* ptr; int i; } vp; vp.ptr = userp; return vp.i; } else { printf("%%Warning: svGetUserData failed\n"); return 0; } } unsigned dpic_getcontext() { svScope scope = svGetScope(); printf("%%Info: svGetScope returned scope (%p) with name %s\n", // scope, svGetNameFromScope(scope)); return (unsigned)(uintptr_t)scope; } unsigned dpic_get1() { return 1; } void dpic_final() { static int s_once = 0; if (s_once++) return; printf("%s:\n", __func__); #ifdef VERILATOR // Cover VerilatedImp::userDump Verilated::internalsDump(); #endif } verilator-5.042/test_regress/t/t_dpi_accessors_inc.vh0000644000542200017500000000332615101701376023426 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Accessor definitions for test of DPI accessors // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // Contributed by Jeremy Bennett and Jie Xu // See t_dpi_accessors.v for details of the test. This file should be included // by the top level module to define all the accessors needed. // Use the macros to provide the desire access to our data. First simple // access to the registers, array elements and wires. For consistency with // simulators, we do not attempt to write wires. `RW_ACCESS([0:0], a, {t.i_test_sub.a}); `RW_ACCESS([7:0], b, {t.i_test_sub.b}); `RW_ACCESS([7:0], mem32, {t.i_test_sub.mem[32]}); `R_ACCESS ([0:0], c, {t.i_test_sub.c}); `R_ACCESS ([7:0], d, {t.i_test_sub.d}); `RW_ACCESS([7:0], e, {t.i_test_sub.e}); `RW_ACCESS([7:0], f, {t.i_test_sub.f}); // Slices of vectors and array elements. For consistency with simulators, // we do not attempt to write wire slices. `RW_ACCESS([3:0], b_slice, {t.i_test_sub.b[3:0]}); `RW_ACCESS([4:0], mem32_slice, {t.i_test_sub.mem[32][7:6], t.i_test_sub.mem[32][2:0]}); `R_ACCESS([5:0], d_slice, {t.i_test_sub.d[6:1]}); // Complex registers, one with distinct read and write. We avoid use of // wires for consistency with simulators. `RW_ACCESS([14:0], l1, {t.i_test_sub.b[3:0], t.i_test_sub.mem[32][7:6], t.i_test_sub.e[6:1], t.i_test_sub.mem[32][2:0]}); `R_ACCESS([7:0], l2, {t.i_test_sub.e[7:4], t.i_test_sub.f[3:0]}); `W_ACCESS([7:0], l2, {t.i_test_sub.e[5:2], t.i_test_sub.f[5:2]}); verilator-5.042/test_regress/t/t_func_const3_bad.py0000755000542200017500000000076315101701376023026 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_unroll_forfor.v0000644000542200017500000000164115101701376022472 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This files is used to generated the following error: // %Error: Internal Error: t/t_unroll_forfor.v:27: ../V3Simulate.h:177: No value found for node. // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2016 by Jan Egil Ruud. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk, in ); input clk; input [71:0] in; reg [71:0] in_tmp; localparam [71:0] TEST_PARAM = {72{1'b0}}; // Test loop always @* begin: testmap byte i, j; // bug1044 for ( i = 0; i < 9; i = i + 1 ) // verilator lint_off WIDTH for ( j=0; j<(TEST_PARAM[i*8+:8]); j=j+1) begin in_tmp[TEST_PARAM[i*8+:8]+j] = in[TEST_PARAM[i*8+:8]+j]; end // verilator lint_on WIDTH $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_interface_down_inlc.py0000755000542200017500000000110115101701376023753 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_down.v" test.compile(v_flags2=['+define+INLINE_C'], verilator_flags2=['-trace']) test.execute() test.passes() verilator-5.042/test_regress/t/t_order_dpi_export_3.v0000644000542200017500000000267215101701376023401 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2021 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module testbench( /*AUTOARG*/ // Inputs clk ); input clk; // Top level input clock bit other_clk; // Dependent clock set via DPI bit third_clk; // Additional dependent clock set via DPI export "DPI-C" function set_other_clk; function void set_other_clk(bit val); other_clk = val; endfunction; export "DPI-C" function set_third_clk; function void set_third_clk(bit val); third_clk = val; endfunction; bit even_other = 1; import "DPI-C" context function void toggle_other_clk(bit val); always @(posedge clk) begin even_other <= ~even_other; toggle_other_clk(even_other); end bit even_third = 1; import "DPI-C" context function void toggle_third_clk(bit val); always @(posedge other_clk) begin even_third <= ~even_third; toggle_third_clk(even_third); end int n = 0; always @(posedge third_clk) begin $display("[%0t] n=%0d", $time, n); if ($time != (8*n+1) * 500) $stop; if (n == 20) begin $write("*-* All Finished *-*\n"); $finish; end n += 1; end endmodule verilator-5.042/test_regress/t/t_config_unsup.out0000644000542200017500000000644515101701376022652 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_config_unsup.v:24:1: Unsupported: config 24 | config cfg; | ^~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_config_unsup.v:25:11: Unsupported: config cell 25 | design t; | ^ %Error-UNSUPPORTED: t/t_config_unsup.v:28:4: Unsupported: config rule 28 | default liblist; | ^~~~~~~ %Error-UNSUPPORTED: t/t_config_unsup.v:29:4: Unsupported: config rule 29 | default liblist liba libb; | ^~~~~~~ %Error-UNSUPPORTED: t/t_config_unsup.v:32:4: Unsupported: config rule 32 | instance t.m20 liblist; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_config_unsup.v:33:4: Unsupported: config rule 33 | instance t.m21 liblist libc; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_config_unsup.v:34:4: Unsupported: config rule 34 | instance t.m22 liblist libc libd; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_config_unsup.v:35:4: Unsupported: config rule 35 | instance t.m23 liblist libc libd; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_config_unsup.v:36:4: Unsupported: config rule 36 | instance t.m24 liblist libc libd; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_config_unsup.v:39:4: Unsupported: config rule 39 | instance t.m30 use cell_identifier; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_config_unsup.v:39:19: Unsupported: config use 39 | instance t.m30 use cell_identifier; | ^~~ %Error-UNSUPPORTED: t/t_config_unsup.v:40:4: Unsupported: config rule 40 | instance t.m31 use lib_id.cell_id; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_config_unsup.v:40:19: Unsupported: config use 40 | instance t.m31 use lib_id.cell_id; | ^~~ %Error-UNSUPPORTED: t/t_config_unsup.v:41:4: Unsupported: config rule 41 | instance t.m32 use #(); | ^~~~~~~~ %Error-UNSUPPORTED: t/t_config_unsup.v:41:19: Unsupported: config use 41 | instance t.m32 use #(); | ^~~ %Error-UNSUPPORTED: t/t_config_unsup.v:44:4: Unsupported: config rule 44 | cell m40 liblist libc libd; | ^~~~ %Error-UNSUPPORTED: t/t_config_unsup.v:44:9: Unsupported: config cell 44 | cell m40 liblist libc libd; | ^~~ %Error-UNSUPPORTED: t/t_config_unsup.v:45:4: Unsupported: config rule 45 | cell work.m41 liblist libc libd; | ^~~~ %Error-UNSUPPORTED: t/t_config_unsup.v:45:9: Unsupported: config cell 45 | cell work.m41 liblist libc libd; | ^~~~ %Error-UNSUPPORTED: t/t_config_unsup.v:46:4: Unsupported: config rule 46 | cell m42 use m42alt; | ^~~~ %Error-UNSUPPORTED: t/t_config_unsup.v:46:9: Unsupported: config cell 46 | cell m42 use m42alt; | ^~~ %Error-UNSUPPORTED: t/t_config_unsup.v:46:13: Unsupported: config use 46 | cell m42 use m42alt; | ^~~ %Error-UNSUPPORTED: t/t_config_unsup.v:47:4: Unsupported: config rule 47 | cell work.m43 use work.m43alt; | ^~~~ %Error-UNSUPPORTED: t/t_config_unsup.v:47:9: Unsupported: config cell 47 | cell work.m43 use work.m43alt; | ^~~~ %Error-UNSUPPORTED: t/t_config_unsup.v:47:18: Unsupported: config use 47 | cell work.m43 use work.m43alt; | ^~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_mailbox_array.py0000755000542200017500000000105115101701376022614 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--fno-slice']) # TODO remove -fno-slice, issue #5632/#5644 test.execute() test.passes() verilator-5.042/test_regress/t/t_inst_2star_bad.v0000644000542200017500000000057215101701376022502 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; wire foo; wire bar; sub sub (.*, .*); sub sub (foo, .*); sub sub (foo, .bar); endmodule module sub (input foo, input bar); endmodule verilator-5.042/test_regress/t/t_func_lib_sub.py0000755000542200017500000000077315101701376022427 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(verilator_flags2=['--no-timing']) #test.execute() test.passes() verilator-5.042/test_regress/t/t_sys_sscanf.py0000755000542200017500000000073415101701376022145 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_complex_params_saif.out0000644000542200017500000012230715101701376025341 0ustar mahmoudyfreeshell// Generated by verilated_saif (SAIFILE (SAIFVERSION "2.0") (DIRECTION "backward") (PROGRAM_NAME "Verilator") (DIVIDER / ) (TIMESCALE 1ps) (DURATION 60) (INSTANCE top (NET (clk (T0 35) (T1 25) (TZ 0) (TX 0) (TB 0) (TC 11)) ) (INSTANCE $unit (NET (global_bit (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) ) ) (INSTANCE t (NET (clk (T0 35) (T1 25) (TZ 0) (TX 0) (TB 0) (TC 11)) (cyc\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (cyc\[1\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3)) (cyc\[2\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_strp\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_strp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_strp_strp\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_strp_strp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_strp_strp\[2\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_strp_strp\[3\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_unip_strp\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_unip_strp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arrp\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arrp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arrp_arrp\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arrp_arrp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arrp_arrp\[2\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arrp_arrp\[3\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arrp_strp\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arrp_strp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arrp_strp\[2\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arrp_strp\[3\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arru[1] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arru[2] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arru_arru[3][1] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arru_arru[3][2] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arru_arru[4][1] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arru_arru[4][2] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arru_arrp[3]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arru_arrp[3]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arru_arrp[4]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arru_arrp[4]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arru_strp[3]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arru_strp[3]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arru_strp[4]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arru_strp[4]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_real\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[32\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[33\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[34\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[35\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[36\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[37\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[38\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[39\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[40\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[41\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[42\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[43\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[44\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[45\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[46\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[47\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[48\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[49\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[50\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[51\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[52\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[53\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[54\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[55\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[56\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[57\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[58\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[59\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[60\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[61\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[62\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[63\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[32\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[33\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[34\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[35\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[36\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[37\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[38\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[39\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[40\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[41\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[42\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[43\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[44\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[45\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[46\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[47\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[48\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[49\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[50\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[51\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[52\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[53\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[54\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[55\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[56\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[57\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[58\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[59\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[60\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[61\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[62\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[63\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[32\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[33\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[34\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[35\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[36\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[37\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[38\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[39\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[40\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[41\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[42\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[43\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[44\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[45\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[46\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[47\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[48\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[49\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[50\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[51\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[52\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[53\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[54\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[55\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[56\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[57\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[58\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[59\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[60\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[61\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[62\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[63\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[32\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[33\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[34\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[35\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[36\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[37\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[38\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[39\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[40\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[41\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[42\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[43\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[44\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[45\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[46\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[47\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[48\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[49\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[50\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[51\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[52\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[53\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[54\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[55\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[56\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[57\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[58\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[59\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[60\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[61\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[62\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[63\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 7)) (v_str32x2\[1\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4)) (v_str32x2\[2\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_str32x2\[3\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_str32x2\[4\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_str32x2\[5\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_str32x2\[6\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_str32x2\[7\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_str32x2\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[32\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_str32x2\[33\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3)) (v_str32x2\[34\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_str32x2\[35\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[36\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[37\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[38\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[39\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[40\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[41\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[42\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[43\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[44\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[45\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[46\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[47\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[48\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[49\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[50\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[51\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[52\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[53\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[54\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[55\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[56\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[57\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[58\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[59\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[60\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[61\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[62\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[63\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_enumed\[1\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3)) (v_enumed\[2\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_enumed\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_enumed2\[2\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3)) (v_enumed2\[3\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_enumed2\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumb\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_enumb\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 3)) (v_enumb\[2\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_enumb2_str\[0\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 5)) (v_enumb2_str\[1\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3)) (v_enumb2_str\[2\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_enumb2_str\[3\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 5)) (v_enumb2_str\[4\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3)) (v_enumb2_str\[5\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2)) (unpacked_array[-2]\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-2]\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-2]\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-2]\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-2]\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-2]\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-2]\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-2]\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-1]\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-1]\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-1]\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-1]\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-1]\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-1]\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-1]\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-1]\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[0]\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[0]\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[0]\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[0]\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[0]\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[0]\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[0]\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[0]\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed (NET (PARAM\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[2\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (PARAM\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE p2 (NET (PARAM\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[1\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (PARAM\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE p3 (NET (PARAM\[0\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (PARAM\[1\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (PARAM\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE unnamedblk1 (NET (b\[0\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (b\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[2\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (b\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE unnamedblk2 (NET (a\[0\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (a\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[2\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (a\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) ) ) verilator-5.042/test_regress/t/t_concat_large.py0000755000542200017500000000073415101701376022413 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_savable_format1_bad.out0000644000542200017500000000040315101701376024013 0ustar mahmoudyfreeshellModel width = 40 Restoring model from 'obj_vlt/t_savable_format1_bad/saved.vltsv' %Error: obj_vlt/t_savable_format1_bad/saved.vltsv:0: Can't deserialize save-restore file as was made from different model: obj_vlt/t_savable_format1_bad/saved.vltsv Aborting... verilator-5.042/test_regress/t/t_func_no_lifetime_bad.out0000644000542200017500000000406415101701376024261 0ustar mahmoudyfreeshell%Warning-IMPLICITSTATIC: t/t_func_no_lifetime_bad.v:26:17: Function/task's lifetime implicitly set to static : ... Suggest use 'function automatic' or 'function static' 26 | function int f_implicit_static(); | ^~~~~~~~~~~~~~~~~ t/t_func_no_lifetime_bad.v:27:11: ... Location of implicit static variable : ... The initializer value will only be set once 27 | int cnt = 0; | ^~~ ... For warning description see https://verilator.org/warn/IMPLICITSTATIC?v=latest ... Use "/* verilator lint_off IMPLICITSTATIC */" and lint_on around source to disable this message. %Warning-IMPLICITSTATIC: t/t_func_no_lifetime_bad.v:31:9: Function/task's lifetime implicitly set to static : ... Suggest use 'task automatic' or 'task static' 31 | task t_implicit_static(); | ^~~~~~~~~~~~~~~~~ t/t_func_no_lifetime_bad.v:32:11: ... Location of implicit static variable : ... The initializer value will only be set once 32 | int cnt = 0; | ^~~ %Warning-IMPLICITSTATIC: t/t_func_no_lifetime_bad.v:9:8: Variable's lifetime implicitly set to static : ... The initializer value will only be set once : ... Suggest use 'static' before variable declaration' 9 | int cnt = 0; | ^~~ %Warning-IMPLICITSTATIC: t/t_func_no_lifetime_bad.v:15:8: Variable's lifetime implicitly set to static : ... The initializer value will only be set once : ... Suggest use 'static' before variable declaration' 15 | int cnt = 0; | ^~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_hier_bynum.py0000755000542200017500000000110415101701376022123 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(v_flags2=['t/t_hier_block.cpp'], verilator_flags2=['--hierarchical'], verilator_make_gmake=False) test.passes() verilator-5.042/test_regress/t/t_struct_init_trace.py0000755000542200017500000000105115101701376023510 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_struct_init.v" test.compile(verilator_flags2=['--cc --trace-vcd']) test.execute() test.passes() verilator-5.042/test_regress/t/t_class_virtual_pure_bad.py0000755000542200017500000000076315101701376024510 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_config_unsup.v0000644000542200017500000000217715101701376022306 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; m10 u_10(); m20 u_20(); m21 u_21(); m22 u_22(); m23 u_23(); m24 u_24(); m30 u_30(); m31 u_31(); m32 u_32(); m40 u_40(); m41 u_41(); m42 u_42(); m43 u_43(); final $write("*-* All Finished *-*\n"); endmodule config cfg; design t; // Test uses m10 default liblist; // Ignored default liblist liba libb; // Test uses m20-29 instance t.m20 liblist; // Use parent's cell library instance t.m21 liblist libc; instance t.m22 liblist libc libd; // m22 in libc instance t.m23 liblist libc libd; // m23 in libd instance t.m24 liblist libc libd; // m24 in default (libb) // Test uses m30-39 instance t.m30 use cell_identifier; instance t.m31 use lib_id.cell_id; instance t.m32 use #(); // Test uses m40-49 cell m40 liblist libc libd; cell work.m41 liblist libc libd; cell m42 use m42alt; cell work.m43 use work.m43alt; endconfig verilator-5.042/test_regress/t/t_unpacked_slice_range.py0000755000542200017500000000073415101701376024117 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_vpi_escape.vlt0000644000542200017500000000077115101701376022263 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `verilator_config public_flat_rd -module "*" -var "double__underscore__vlt" public_flat_rd -module "sub_with_very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very_long_name" -var "subsig2" verilator-5.042/test_regress/t/t_timing_class.v0000644000542200017500000001512315101701376022256 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `ifdef TEST_VERBOSE `define WRITE_VERBOSE(args) $write args `else `define WRITE_VERBOSE(args) `endif class BaseClass; virtual task sleep; endtask virtual task await; endtask endclass module t; // ============================================= // EVENTS class EventClass extends BaseClass; event e; int trig_count; function new; trig_count = 0; endfunction task inc_trig_count; trig_count++; endtask; task sleep; @e inc_trig_count; `WRITE_VERBOSE(("Event in class triggered at time %0t!\n", $time)); endtask task wake; ->e; endtask endclass class WaitClass extends BaseClass; int a; int b; logic ok; function new; a = 0; b = 0; ok = 0; endfunction task await; wait(a == 4 && b > 16) if (a != 4 || b <= 16) $stop; ok = 1; `WRITE_VERBOSE(("Condition in object met at time %0t!\n", $time)); endtask endclass class LocalWaitClass extends BaseClass; logic ok; function new; ok = 0; endfunction task await; int a = 0; int b = 100; fork wait(a == 42 || b != 100) if (a != 42 && b == 100) $stop; #10 a = 42; join ok = 1; `WRITE_VERBOSE(("Condition with local variables met at time %0t!\n", $time)); endtask endclass class ClkClass; logic clk; int count; function new; clk = 0; count = 0; endfunction task flip; clk = ~clk; endtask; task count_5; @(posedge clk) count++; @(posedge clk) count++; @(posedge clk) count++; @(posedge clk) count++; @(posedge clk) count++; endtask endclass EventClass ec = new; WaitClass wc = new; LocalWaitClass lc = new; ClkClass cc = new; initial begin @ec.e; ec.sleep; if (wc.ok) $stop; wc.await; if (lc.ok) $stop; lc.await; end initial #20 ec.wake; initial #40 ->ec.e; initial begin wc.a = #50 4; wc.b = #10 32; end always @ec.e begin ec.inc_trig_count; `WRITE_VERBOSE(("Event in class triggered at time %0t!\n", $time)); end always #5 cc.flip; initial cc.count_5; initial begin #80 if (cc.count != 5) $stop; if (ec.trig_count != 3) $stop; if (!wc.ok) $stop; if (!lc.ok) $stop; end // ============================================= // DELAYS virtual class DelayClass; pure virtual task do_delay; pure virtual task do_sth_else; endclass `ifdef TEST_VERBOSE `define DELAY_CLASS(dt) \ class Delay``dt extends DelayClass; \ virtual task do_delay; \ $write("Starting a #%0d delay\n", dt); \ #dt \ $write("Ended a #%0d delay\n", dt); \ endtask \ virtual task do_sth_else; \ $write("Task with no delay (in Delay%0d)\n", dt); \ endtask \ endclass `else `define DELAY_CLASS(dt) \ class Delay``dt extends DelayClass; \ virtual task do_delay; \ #dt; \ endtask \ virtual task do_sth_else; \ endtask \ endclass `endif `DELAY_CLASS(10); `DELAY_CLASS(20); `DELAY_CLASS(40); class NoDelay extends DelayClass; virtual task do_delay; `WRITE_VERBOSE(("Task with no delay\n")); endtask virtual task do_sth_else; `WRITE_VERBOSE(("Task with no delay (in NoDelay)\n")); endtask endclass class AssignDelayClass; logic x; logic y; task do_assign; y = #10 x; `WRITE_VERBOSE(("Did assignment with delay\n")); endtask endclass initial begin DelayClass dc; Delay10 d10 = new; Delay20 d20 = new; Delay40 d40 = new; NoDelay dNo = new; AssignDelayClass dAsgn = new; `WRITE_VERBOSE(("I'm at time %0t\n", $time)); dc = d10; dc.do_delay; dc.do_sth_else; `WRITE_VERBOSE(("I'm at time %0t\n", $time)); if ($time != 10) $stop; dc = d20; dc.do_delay; dc.do_sth_else; `WRITE_VERBOSE(("I'm at time %0t\n", $time)); if ($time != 30) $stop; dc = d40; dc.do_delay; dc.do_sth_else; `WRITE_VERBOSE(("I'm at time %0t\n", $time)); if ($time != 70) $stop; dc = dNo; dc.do_delay; dc.do_sth_else; `WRITE_VERBOSE(("I'm at time %0t\n", $time)); dAsgn.x = 1; dAsgn.y = 0; fork #5 dAsgn.x = 0; join_none dAsgn.do_assign; if ($time != 80) $stop; if (dAsgn.y != 1) $stop; // Test if the object is deleted before do_assign finishes: fork dAsgn.do_assign; join_none #5 dAsgn = null; #15 $write("*-* All Finished *-*\n"); $finish; end // ============================================= // FORKS class ForkDelayClass; task do_delay; #40; endtask endclass class ForkClass; int done = 0; task do_fork(); ForkDelayClass d; fork begin #10 done++; `WRITE_VERBOSE(("Forked process %0d ending at time %0t\n", done, $time)); end fork begin #20 done++; `WRITE_VERBOSE(("Forked process %0d ending at time %0t\n", done, $time)); d = new; end begin #30 d.do_delay; done++; `WRITE_VERBOSE(("Forked process %0d ending at time %0t\n", done, $time)); end join join done++; `WRITE_VERBOSE(("All forked processes ended at time %0t\n", $time)); endtask endclass initial begin ForkClass fc = new; fc.do_fork; if (fc.done != 4 || $time != 70) $stop; end initial #101 $stop; // timeout endmodule verilator-5.042/test_regress/t/t_assert_ctl_concurrent.py0000755000542200017500000000077415101701376024403 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["--binary --assert"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_array_packed_write_read.v0000644000542200017500000002373415101701376024443 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Iztok Jeras. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; // parameters for array sizes localparam WA = 8; // address dimension size localparam WB = 8; // bit dimension size localparam NO = 10; // number of access events // 2D packed arrays logic [WA-1:0] [WB-1:0] array_dsc; // descending range array /* verilator lint_off ASCRANGE */ logic [0:WA-1] [0:WB-1] array_asc; // ascending range array /* verilator lint_on ASCRANGE */ integer cnt = 0; // msg926 logic [3:0][31:0] packedArray; initial packedArray = '0; // event counter always @ (posedge clk) begin cnt <= cnt + 1; end // finish report always @ (posedge clk) if ((cnt[30:2]==NO) && (cnt[1:0]==2'd0)) begin $write("*-* All Finished *-*\n"); $finish; end // descending range always @ (posedge clk) if (cnt[1:0]==2'd0) begin // initialize to defaaults (all bits to 0) if (cnt[30:2]==0) array_dsc <= '0; else if (cnt[30:2]==1) array_dsc <= '0; else if (cnt[30:2]==2) array_dsc <= '0; else if (cnt[30:2]==3) array_dsc <= '0; else if (cnt[30:2]==4) array_dsc <= '0; else if (cnt[30:2]==5) array_dsc <= '0; else if (cnt[30:2]==6) array_dsc <= '0; else if (cnt[30:2]==7) array_dsc <= '0; else if (cnt[30:2]==8) array_dsc <= '0; else if (cnt[30:2]==9) array_dsc <= '0; end else if (cnt[1:0]==2'd1) begin // write value to array if (cnt[30:2]==0) begin end else if (cnt[30:2]==1) array_dsc <= {WA *WB +0{1'b1}}; else if (cnt[30:2]==2) array_dsc [WA/2-1:0 ] <= {WA/2*WB +0{1'b1}}; else if (cnt[30:2]==3) array_dsc [WA -1:WA/2] <= {WA/2*WB +0{1'b1}}; else if (cnt[30:2]==4) array_dsc [ 0 ] <= {1 *WB +0{1'b1}}; else if (cnt[30:2]==5) array_dsc [WA -1 ] <= {1 *WB +0{1'b1}}; else if (cnt[30:2]==6) array_dsc [ 0 ][WB/2-1:0 ] <= {1 *WB/2+0{1'b1}}; else if (cnt[30:2]==7) array_dsc [WA -1 ][WB -1:WB/2] <= {1 *WB/2+0{1'b1}}; else if (cnt[30:2]==8) array_dsc [ 0 ][ 0 ] <= {1 *1 +0{1'b1}}; else if (cnt[30:2]==9) array_dsc [WA -1 ][WB -1 ] <= {1 *1 +0{1'b1}}; end else if (cnt[1:0]==2'd2) begin // check array value if (cnt[30:2]==0) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end else if (cnt[30:2]==1) begin if (array_dsc !== 64'b1111111111111111111111111111111111111111111111111111111111111111) begin $display("%b", array_dsc); $stop(); end end else if (cnt[30:2]==2) begin if (array_dsc !== 64'b0000000000000000000000000000000011111111111111111111111111111111) begin $display("%b", array_dsc); $stop(); end end else if (cnt[30:2]==3) begin if (array_dsc !== 64'b1111111111111111111111111111111100000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end else if (cnt[30:2]==4) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000011111111) begin $display("%b", array_dsc); $stop(); end end else if (cnt[30:2]==5) begin if (array_dsc !== 64'b1111111100000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end else if (cnt[30:2]==6) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000000001111) begin $display("%b", array_dsc); $stop(); end end else if (cnt[30:2]==7) begin if (array_dsc !== 64'b1111000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end else if (cnt[30:2]==8) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000000000001) begin $display("%b", array_dsc); $stop(); end end else if (cnt[30:2]==9) begin if (array_dsc !== 64'b1000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end end else if (cnt[1:0]==2'd3) begin // read value from array (not a very good test for now) if (cnt[30:2]==0) begin if (array_dsc !== {WA *WB {1'b0}}) $stop(); end else if (cnt[30:2]==1) begin if (array_dsc !== {WA *WB +0{1'b1}}) $stop(); end else if (cnt[30:2]==2) begin if (array_dsc [WA/2-1:0 ] !== {WA/2*WB +0{1'b1}}) $stop(); end else if (cnt[30:2]==3) begin if (array_dsc [WA -1:WA/2] !== {WA/2*WB +0{1'b1}}) $stop(); end else if (cnt[30:2]==4) begin if (array_dsc [ 0 ] !== {1 *WB +0{1'b1}}) $stop(); end else if (cnt[30:2]==5) begin if (array_dsc [WA -1 ] !== {1 *WB +0{1'b1}}) $stop(); end else if (cnt[30:2]==6) begin if (array_dsc [ 0 ][WB/2-1:0 ] !== {1 *WB/2+0{1'b1}}) $stop(); end else if (cnt[30:2]==7) begin if (array_dsc [WA -1 ][WB -1:WB/2] !== {1 *WB/2+0{1'b1}}) $stop(); end else if (cnt[30:2]==8) begin if (array_dsc [ 0 ][ 0 ] !== {1 *1 +0{1'b1}}) $stop(); end else if (cnt[30:2]==9) begin if (array_dsc [WA -1 ][WB -1 ] !== {1 *1 +0{1'b1}}) $stop(); end end // ascending range always @ (posedge clk) if (cnt[1:0]==2'd0) begin // initialize to defaaults (all bits to 0) if (cnt[30:2]==0) array_asc <= '0; else if (cnt[30:2]==1) array_asc <= '0; else if (cnt[30:2]==2) array_asc <= '0; else if (cnt[30:2]==3) array_asc <= '0; else if (cnt[30:2]==4) array_asc <= '0; else if (cnt[30:2]==5) array_asc <= '0; else if (cnt[30:2]==6) array_asc <= '0; else if (cnt[30:2]==7) array_asc <= '0; else if (cnt[30:2]==8) array_asc <= '0; else if (cnt[30:2]==9) array_asc <= '0; end else if (cnt[1:0]==2'd1) begin // write value to array if (cnt[30:2]==0) begin end else if (cnt[30:2]==1) array_asc <= {WA *WB +0{1'b1}}; else if (cnt[30:2]==2) array_asc [0 :WA/2-1] <= {WA/2*WB +0{1'b1}}; else if (cnt[30:2]==3) array_asc [WA/2:WA -1] <= {WA/2*WB +0{1'b1}}; else if (cnt[30:2]==4) array_asc [0 ] <= {1 *WB +0{1'b1}}; else if (cnt[30:2]==5) array_asc [ WA -1] <= {1 *WB +0{1'b1}}; else if (cnt[30:2]==6) array_asc [0 ][0 :WB/2-1] <= {1 *WB/2+0{1'b1}}; else if (cnt[30:2]==7) array_asc [ WA -1][WB/2:WB -1] <= {1 *WB/2+0{1'b1}}; else if (cnt[30:2]==8) array_asc [0 ][0 ] <= {1 *1 +0{1'b1}}; else if (cnt[30:2]==9) array_asc [ WA -1][ WB -1] <= {1 *1 +0{1'b1}}; end else if (cnt[1:0]==2'd2) begin // check array value if (cnt[30:2]==0) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end else if (cnt[30:2]==1) begin if (array_asc !== 64'b1111111111111111111111111111111111111111111111111111111111111111) begin $display("%b", array_asc); $stop(); end end else if (cnt[30:2]==2) begin if (array_asc !== 64'b1111111111111111111111111111111100000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end else if (cnt[30:2]==3) begin if (array_asc !== 64'b0000000000000000000000000000000011111111111111111111111111111111) begin $display("%b", array_asc); $stop(); end end else if (cnt[30:2]==4) begin if (array_asc !== 64'b1111111100000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end else if (cnt[30:2]==5) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000011111111) begin $display("%b", array_asc); $stop(); end end else if (cnt[30:2]==6) begin if (array_asc !== 64'b1111000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end else if (cnt[30:2]==7) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000000001111) begin $display("%b", array_asc); $stop(); end end else if (cnt[30:2]==8) begin if (array_asc !== 64'b1000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end else if (cnt[30:2]==9) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000000000001) begin $display("%b", array_asc); $stop(); end end end else if (cnt[1:0]==2'd3) begin // read value from array (not a very good test for now) if (cnt[30:2]==0) begin if (array_asc !== {WA *WB {1'b0}}) $stop(); end else if (cnt[30:2]==1) begin if (array_asc !== {WA *WB +0{1'b1}}) $stop(); end else if (cnt[30:2]==2) begin if (array_asc [0 :WA/2-1] !== {WA/2*WB +0{1'b1}}) $stop(); end else if (cnt[30:2]==3) begin if (array_asc [WA/2:WA -1] !== {WA/2*WB +0{1'b1}}) $stop(); end else if (cnt[30:2]==4) begin if (array_asc [0 ] !== {1 *WB +0{1'b1}}) $stop(); end else if (cnt[30:2]==5) begin if (array_asc [ WA -1] !== {1 *WB +0{1'b1}}) $stop(); end else if (cnt[30:2]==6) begin if (array_asc [0 ][0 :WB/2-1] !== {1 *WB/2+0{1'b1}}) $stop(); end else if (cnt[30:2]==7) begin if (array_asc [ WA -1][WB/2:WB -1] !== {1 *WB/2+0{1'b1}}) $stop(); end else if (cnt[30:2]==8) begin if (array_asc [0 ][0 ] !== {1 *1 +0{1'b1}}) $stop(); end else if (cnt[30:2]==9) begin if (array_asc [ WA -1][ WB -1] !== {1 *1 +0{1'b1}}) $stop(); end end endmodule verilator-5.042/test_regress/t/t_case_x.v0000644000542200017500000000270415101701376021045 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg [3:0] value; reg [3:0] valuex; // verilator lint_off CASEOVERLAP // verilator lint_off CASEWITHX // verilator lint_off CASEX // Note for Verilator Xs must become zeros, or the Xs may match. initial begin value = 4'b1001; valuex = 4'b1xxx; case (value) 4'b1xxx: $stop; 4'b1???: $stop; 4'b1001: ; default: $stop; endcase case (valuex) 4'b1???: $stop; 4'b1xxx: ; 4'b1001: ; 4'b1000: ; // 1xxx is mapped to this by Verilator -x-assign 0 default: $stop; endcase // casex (value) 4'b100x: ; default: $stop; endcase casex (value) 4'b100?: ; default: $stop; endcase casex (valuex) 4'b100x: ; default: $stop; endcase casex (valuex) 4'b100?: ; default: $stop; endcase // casez (value) 4'bxxxx: $stop; 4'b100?: ; default: $stop; endcase casez (valuex) 4'b1xx?: ; 4'b100?: ; // 1xxx is mapped to this by Verilator -x-assign 0 default: $stop; endcase $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_constraint_struct_complex.py0000755000542200017500000000104615101701376025306 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_scheduling_many_clocks.py0000755000542200017500000000143115101701376024474 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.sim_time = 100000 test.scenarios('simulator') test.compile(verilator_flags2=["--stats"]) if test.vlt or test.vltmt: test.file_grep(test.stats, r"Scheduling, 'act' extra triggers\s+(\d+)", 1) test.file_grep(test.stats, r"Scheduling, 'act' pre triggers\s+(\d+)", 1) test.file_grep(test.stats, r"Scheduling, 'act' sense triggers\s+(\d+)", 228) test.execute() test.passes() verilator-5.042/test_regress/t/t_type_param.py0000755000542200017500000000073415101701376022133 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_math_repl2_bad.py0000755000542200017500000000076615101701376022642 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_select_bad_msb.py0000755000542200017500000000076315101701376022722 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_math_shift_extend.py0000755000542200017500000000073415101701376023467 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_wire_trireg_unsup.v0000644000542200017500000000062115101701376023353 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias' // // Simple bi-directional alias test. // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; trireg unsup; trireg (small) unsup_s; trireg (medium) unsup_m; trireg (large) unsup_l; endmodule verilator-5.042/test_regress/t/t_param_while.py0000755000542200017500000000073415101701376022262 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_hier_block_type_param_notfound_bad.py0000755000542200017500000000120615101701376027031 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_hier_block_type_param.v" test.compile(verilator_flags2=["--hierarchical-params-file", "/does-not-exist"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_packed_concat_bad.v0000644000542200017500000000122315101701376023162 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Driss Hafdi // SPDX-License-Identifier: CC0-1.0 module t; typedef logic [15:0] count_t; typedef bit [31:0] bit_int_t; localparam bit_int_t [1:0] count_bits = {2{$bits(count_t)}}; localparam bit_int_t [1:0] count_bitsc = {$bits(count_t), $bits(count_t)}; initial begin if (count_bits[0] != 16) $stop; if (count_bits[1] != 16) $stop; if (count_bitsc[0] != 16) $stop; if (count_bitsc[1] != 16) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_cxx_equal_to.v0000644000542200017500000000252715101701376022301 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // On some platforms (i.e. FreeBSD 12) this triggered: // // Active region did not converge. // // due to the mistaken belief that the AstVarScope node for TOP->t__DOT__clk // is equal to the AstVarScope node for TOP->t__DOT__rst. This occured because // AstVarScope was missing an appropriate same method and is tickled by the LLVM // libcxx library. // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by John Wehle. // SPDX-License-Identifier: CC0-1.0 module t; wire [1:0] out; reg in; reg rst; reg clk; initial begin clk = 0; rst = 0; #10 rst = 1; #10 rst = 0; in = 1'b0; #30 $write("*-* All Finished *-*\n"); $finish; end always begin #10 clk <= !clk; end Test test(.out(out), .in(in), .clk(clk), .rst(rst)); endmodule module Test(/*AUTOARG*/ // Outputs out, // Inputs clk, in, rst ); input clk; input in; input rst; output wire [1:0] out; reg [1:0] s; reg sin; assign out = s; always @(posedge clk) begin s[1] <= in; s[0] <= sin; end always @(negedge clk, posedge rst) if (rst) sin <= 1'b0; else sin <= in; endmodule verilator-5.042/test_regress/t/t_cover_line_trace.out0000644000542200017500000011027115101701376023447 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $var wire 1 8! clk $end $scope module t $end $var wire 1 8! clk $end $var wire 1 = toggle $end $var wire 32 # vlCoverageLineTrace_t_cover_line__15_block [31:0] $end $var wire 32 > cyc [31:0] $end $var wire 32 $ vlCoverageLineTrace_t_cover_line__18_block [31:0] $end $var wire 8 ? cyc_copy [7:0] $end $scope module b1 $end $var wire 1 8! clk $end $var wire 1 = toggle $end $var wire 32 ,! vlCoverageLineTrace_t_cover_line__164_block [31:0] $end $var wire 32 -! vlCoverageLineTrace_t_cover_line__166_else [31:0] $end $var wire 32 N! vlCoverageLineTrace_t_cover_line__166_if [31:0] $end $var wire 32 .! vlCoverageLineTrace_t_cover_line__170_else [31:0] $end $var wire 32 /! vlCoverageLineTrace_t_cover_line__170_if [31:0] $end $var wire 32 0! vlCoverageLineTrace_t_cover_line__174_else [31:0] $end $upscope $end $scope module b2 $end $var wire 1 8! clk $end $var wire 1 = toggle $end $var wire 32 1! vlCoverageLineTrace_t_cover_line__164_block [31:0] $end $var wire 32 2! vlCoverageLineTrace_t_cover_line__166_else [31:0] $end $var wire 32 O! vlCoverageLineTrace_t_cover_line__166_if [31:0] $end $var wire 32 3! vlCoverageLineTrace_t_cover_line__170_else [31:0] $end $var wire 32 4! vlCoverageLineTrace_t_cover_line__170_if [31:0] $end $var wire 32 5! vlCoverageLineTrace_t_cover_line__174_else [31:0] $end $upscope $end $scope module t1 $end $var wire 1 8! clk $end $var wire 1 = toggle $end $var wire 32 6! vlCoverageLineTrace_t_cover_line__215_block [31:0] $end $var wire 32 ;! vlCoverageLineTrace_t_cover_line__219_block [31:0] $end $var wire 32 ! vlCoverageLineTrace_t_cover_line__225_if [31:0] $end $upscope $end $var wire 32 @ vlCoverageLineTrace_t_cover_line__55_block [31:0] $end $var wire 32 A vlCoverageLineTrace_t_cover_line__56_else [31:0] $end $var wire 32 B vlCoverageLineTrace_t_cover_line__56_if [31:0] $end $var wire 32 C vlCoverageLineTrace_t_cover_line__60_else [31:0] $end $var wire 32 D vlCoverageLineTrace_t_cover_line__60_if [31:0] $end $var wire 32 E vlCoverageLineTrace_t_cover_line__61_else [31:0] $end $var wire 32 F vlCoverageLineTrace_t_cover_line__61_if [31:0] $end $var wire 32 G vlCoverageLineTrace_t_cover_line__66_else [31:0] $end $var wire 32 H vlCoverageLineTrace_t_cover_line__66_if [31:0] $end $var wire 32 I vlCoverageLineTrace_t_cover_line__67_else [31:0] $end $var wire 32 J vlCoverageLineTrace_t_cover_line__67_if [31:0] $end $var wire 32 K vlCoverageLineTrace_t_cover_line__73_else [31:0] $end $var wire 32 L vlCoverageLineTrace_t_cover_line__73_if [31:0] $end $var wire 32 M vlCoverageLineTrace_t_cover_line__74_else [31:0] $end $var wire 32 N vlCoverageLineTrace_t_cover_line__74_if [31:0] $end $var wire 32 O vlCoverageLineTrace_t_cover_line__83_elsif [31:0] $end $var wire 32 P vlCoverageLineTrace_t_cover_line__87_elsif [31:0] $end $var wire 32 Q vlCoverageLineTrace_t_cover_line__91_else [31:0] $end $var wire 32 R vlCoverageLineTrace_t_cover_line__91_if [31:0] $end $var wire 32 ?! vlCoverageLineTrace_t_cover_line__100_block [31:0] $end $var wire 32 @! vlCoverageLineTrace_t_cover_line__101_block [31:0] $end $var wire 32 A! vlCoverageLineTrace_t_cover_line__104_block [31:0] $end $var wire 32 B! vlCoverageLineTrace_t_cover_line__105_block [31:0] $end $var wire 32 S vlCoverageLineTrace_t_cover_line__107_block [31:0] $end $var wire 32 T vlCoverageLineTrace_t_cover_line__110_elsif [31:0] $end $var wire 32 U vlCoverageLineTrace_t_cover_line__113_elsif [31:0] $end $var wire 32 V vlCoverageLineTrace_t_cover_line__120_else [31:0] $end $var wire 32 W vlCoverageLineTrace_t_cover_line__120_if [31:0] $end $var wire 32 9! vlCoverageLineTrace_t_cover_line__127_block [31:0] $end $scope module a1 $end $var wire 1 8! clk $end $var wire 1 = toggle $end $var wire 32 X vlCoverageLineTrace_t_cover_line__140_block [31:0] $end $var wire 32 Y vlCoverageLineTrace_t_cover_line__141_else [31:0] $end $var wire 32 Z vlCoverageLineTrace_t_cover_line__141_if [31:0] $end $var wire 32 [ vlCoverageLineTrace_t_cover_line__145_else [31:0] $end $upscope $end $scope module a2 $end $var wire 1 8! clk $end $var wire 1 = toggle $end $var wire 32 \ vlCoverageLineTrace_t_cover_line__140_block [31:0] $end $var wire 32 ] vlCoverageLineTrace_t_cover_line__141_else [31:0] $end $var wire 32 ^ vlCoverageLineTrace_t_cover_line__141_if [31:0] $end $var wire 32 _ vlCoverageLineTrace_t_cover_line__145_else [31:0] $end $upscope $end $scope module cond1 $end $var wire 1 8! clk $end $var wire 32 > cyc [31:0] $end $var wire 1 2 a $end $var wire 1 3 b $end $var wire 1 * c $end $var wire 1 ` d $end $var wire 1 4 e $end $var wire 1 a f $end $var wire 1 + g $end $var wire 1 b h $end $var wire 1 c k $end $var wire 1 C! l $end $var wire 1 :! m $end $var wire 6 , tab [5:0] $end $var wire 8 d data[0][0] [7:0] $end $var wire 8 e data[0][1] [7:0] $end $var wire 8 f data[1][0] [7:0] $end $var wire 8 g data[1][1] [7:0] $end $var wire 32 % vlCoverageLineTrace_t_cover_line__315_block [31:0] $end $var wire 32 - vlCoverageLineTrace_t_cover_line__318_block [31:0] $end $var wire 32 h vlCoverageLineTrace_t_cover_line__323_block [31:0] $end $var wire 8 D! get_arr__Vstatic__arr[0] [7:0] $end $var wire 8 E! get_arr__Vstatic__arr[1] [7:0] $end $var wire 32 5 vlCoverageLineTrace_t_cover_line__328_cond_else [31:0] $end $var wire 32 6 vlCoverageLineTrace_t_cover_line__328_cond_then [31:0] $end $var wire 32 7 vlCoverageLineTrace_t_cover_line__329_cond_else [31:0] $end $var wire 32 8 vlCoverageLineTrace_t_cover_line__329_cond_then [31:0] $end $var wire 32 . vlCoverageLineTrace_t_cover_line__330_cond_else [31:0] $end $var wire 32 / vlCoverageLineTrace_t_cover_line__330_cond_then [31:0] $end $var wire 32 i vlCoverageLineTrace_t_cover_line__331_block [31:0] $end $var wire 32 j vlCoverageLineTrace_t_cover_line__332_cond_else [31:0] $end $var wire 32 k vlCoverageLineTrace_t_cover_line__332_cond_then [31:0] $end $var wire 32 l vlCoverageLineTrace_t_cover_line__333_cond_else [31:0] $end $var wire 32 m vlCoverageLineTrace_t_cover_line__333_cond_then [31:0] $end $var wire 32 9 vlCoverageLineTrace_t_cover_line__335_cond_else_1 [31:0] $end $var wire 32 : vlCoverageLineTrace_t_cover_line__335_cond_then_1 [31:0] $end $var wire 32 ; vlCoverageLineTrace_t_cover_line__335_cond_else [31:0] $end $var wire 32 < vlCoverageLineTrace_t_cover_line__335_cond_then [31:0] $end $var wire 32 n vlCoverageLineTrace_t_cover_line__338_cond_else [31:0] $end $var wire 32 o vlCoverageLineTrace_t_cover_line__338_cond_then [31:0] $end $var wire 32 F! vlCoverageLineTrace_t_cover_line__344_cond_else [31:0] $end $var wire 32 0 vlCoverageLineTrace_t_cover_line__344_cond_else_1 [31:0] $end $var wire 32 G! vlCoverageLineTrace_t_cover_line__344_cond_then [31:0] $end $var wire 32 1 vlCoverageLineTrace_t_cover_line__344_cond_then_1 [31:0] $end $var wire 32 & vlCoverageLineTrace_t_cover_line__347_block [31:0] $end $var wire 32 p vlCoverageLineTrace_t_cover_line__348_else [31:0] $end $var wire 32 q vlCoverageLineTrace_t_cover_line__348_if [31:0] $end $var wire 32 r vlCoverageLineTrace_t_cover_line__348_cond_else [31:0] $end $var wire 32 s vlCoverageLineTrace_t_cover_line__348_cond_then [31:0] $end $var wire 32 t vlCoverageLineTrace_t_cover_line__351_cond_else [31:0] $end $var wire 32 u vlCoverageLineTrace_t_cover_line__351_cond_then [31:0] $end $var wire 32 ' vlCoverageLineTrace_t_cover_line__354_block [31:0] $end $var wire 32 v vlCoverageLineTrace_t_cover_line__357_block [31:0] $end $var wire 32 w vlCoverageLineTrace_t_cover_line__357_cond_else [31:0] $end $var wire 32 x vlCoverageLineTrace_t_cover_line__357_cond_then [31:0] $end $var wire 32 y vlCoverageLineTrace_t_cover_line__361_else [31:0] $end $var wire 32 z vlCoverageLineTrace_t_cover_line__361_if [31:0] $end $scope module unnamedblk1 $end $var wire 32 H! i [31:0] $end $upscope $end $scope module unnamedblk2 $end $var wire 32 { i [31:0] $end $upscope $end $upscope $end $scope module o1 $end $var wire 1 8! clk $end $var wire 1 = toggle $end $var wire 32 | vlCoverageLineTrace_t_cover_line__253_block [31:0] $end $var wire 32 } vlCoverageLineTrace_t_cover_line__254_else [31:0] $end $var wire 32 ~ vlCoverageLineTrace_t_cover_line__254_if [31:0] $end $var wire 32 !! vlCoverageLineTrace_t_cover_line__257_else [31:0] $end $var wire 32 I! vlCoverageLineTrace_t_cover_line__257_if [31:0] $end $upscope $end $scope module par1 $end $var wire 32 J! CALLS_FUNC [31:0] $end $var wire 32 K! vlCoverageLineTrace_t_cover_line__288_block [31:0] $end $var wire 32 L! vlCoverageLineTrace_t_cover_line__289_else [31:0] $end $var wire 32 M! vlCoverageLineTrace_t_cover_line__289_if [31:0] $end $upscope $end $scope module tab1 $end $var wire 1 8! clk $end $var wire 4 "! cyc4 [3:0] $end $var wire 32 #! decoded [31:0] $end $var wire 32 $! vlCoverageLineTrace_t_cover_line__266_block [31:0] $end $var wire 32 %! vlCoverageLineTrace_t_cover_line__268_case [31:0] $end $var wire 32 &! vlCoverageLineTrace_t_cover_line__269_case [31:0] $end $var wire 32 '! vlCoverageLineTrace_t_cover_line__270_case [31:0] $end $var wire 32 (! vlCoverageLineTrace_t_cover_line__271_case [31:0] $end $var wire 32 )! vlCoverageLineTrace_t_cover_line__272_case [31:0] $end $var wire 32 *! vlCoverageLineTrace_t_cover_line__273_case [31:0] $end $var wire 32 +! vlCoverageLineTrace_t_cover_line__277_block [31:0] $end $upscope $end $upscope $end $scope module my_pkg $end $var wire 32 ( x [31:0] $end $var wire 32 ) vlCoverageLineTrace_t_cover_line__301_block [31:0] $end $upscope $end $upscope $end $enddefinitions $end #0 b00000000000000000000000000000001 # b00000000000000000000000000000001 $ b00000000000000000000000000000001 % b00000000000000000000000000000001 & b00000000000000000000000000000101 ' b00000000000000000000000000000001 ( b00000000000000000000000000000001 ) 0* 0+ b000001 , b00000000000000000000000000000010 - b00000000000000000000000000000000 . b00000000000000000000000000000010 / b00000000000000000000000000000010 0 b00000000000000000000000000000000 1 02 03 04 b00000000000000000000000000000010 5 b00000000000000000000000000000000 6 b00000000000000000000000000000000 7 b00000000000000000000000000000010 8 b00000000000000000000000000000000 9 b00000000000000000000000000000010 : b00000000000000000000000000000010 ; b00000000000000000000000000000000 < 0= b00000000000000000000000000000001 > b00000001 ? b00000000000000000000000000000000 @ b00000000000000000000000000000000 A b00000000000000000000000000000000 B b00000000000000000000000000000000 C b00000000000000000000000000000000 D b00000000000000000000000000000000 E b00000000000000000000000000000000 F b00000000000000000000000000000000 G b00000000000000000000000000000000 H b00000000000000000000000000000000 I b00000000000000000000000000000000 J b00000000000000000000000000000000 K b00000000000000000000000000000000 L b00000000000000000000000000000000 M b00000000000000000000000000000000 N b00000000000000000000000000000000 O b00000000000000000000000000000000 P b00000000000000000000000000000000 Q b00000000000000000000000000000000 R b00000000000000000000000000000000 S b00000000000000000000000000000000 T b00000000000000000000000000000000 U b00000000000000000000000000000000 V b00000000000000000000000000000000 W b00000000000000000000000000000000 X b00000000000000000000000000000000 Y b00000000000000000000000000000000 Z b00000000000000000000000000000000 [ b00000000000000000000000000000000 \ b00000000000000000000000000000000 ] b00000000000000000000000000000000 ^ b00000000000000000000000000000000 _ 0` 1a 1b 0c b00000000 d b00000000 e b00000000 f b00000000 g b00000000000000000000000000000001 h b00000000000000000000000000000000 i b00000000000000000000000000000000 j b00000000000000000000000000000000 k b00000000000000000000000000000000 l b00000000000000000000000000000000 m b00000000000000000000000000000000 n b00000000000000000000000000000001 o b00000000000000000000000000000001 p b00000000000000000000000000000000 q b00000000000000000000000000000000 r b00000000000000000000000000000000 s b00000000000000000000000000000001 t b00000000000000000000000000000000 u b00000000000000000000000000000100 v b00000000000000000000000000000011 w b00000000000000000000000000000001 x b00000000000000000000000000000001 y b00000000000000000000000000000000 z b00000000000000000000000000000111 { b00000000000000000000000000000000 | b00000000000000000000000000000000 } b00000000000000000000000000000000 ~ b00000000000000000000000000000000 !! b0000 "! b00000000000000000000000000000000 #! b00000000000000000000000000000000 $! b00000000000000000000000000000000 %! b00000000000000000000000000000000 &! b00000000000000000000000000000000 '! b00000000000000000000000000000000 (! b00000000000000000000000000000000 )! b00000000000000000000000000000000 *! b00000000000000000000000000000000 +! b00000000000000000000000000000000 ,! b00000000000000000000000000000000 -! b00000000000000000000000000000000 .! b00000000000000000000000000000000 /! b00000000000000000000000000000000 0! b00000000000000000000000000000000 1! b00000000000000000000000000000000 2! b00000000000000000000000000000000 3! b00000000000000000000000000000000 4! b00000000000000000000000000000000 5! b00000000000000000000000000000000 6! b00000000000000000000000000000000 7! 08! b00000000000000000000000000000000 9! 0:! b00000000000000000000000000000000 ;! b00000000000000000000000000000000 ! b00000000000000000000000000000000 ?! b00000000000000000000000000000000 @! b00000000000000000000000000000000 A! b00000000000000000000000000000000 B! 0C! b00000000 D! b00000000 E! b00000000000000000000000000000000 F! b00000000000000000000000000000000 G! b00000000000000000000000000000101 H! b00000000000000000000000000000000 I! b00000000000000000000000000000010 J! b00000000000000000000000000000000 K! b00000000000000000000000000000000 L! b00000000000000000000000000000000 M! b00000000000000000000000000000000 N! b00000000000000000000000000000000 O! #10 1* 1+ b000011 , b00000000000000000000000000000011 - b00000000000000000000000000000011 / b00000000000000000000000000000001 1 14 b00000000000000000000000000000100 5 b00000000000000000000000000000001 7 b00000000000000000000000000000011 8 b00000000000000000000000000000001 9 b00000000000000000000000000000011 : b00000000000000000000000000000001 < b00000000000000000000000000000010 > b00000010 ? b00000000000000000000000000000001 @ b00000000000000000000000000000001 B b00000000000000000000000000000001 C b00000000000000000000000000000001 E b00000000000000000000000000000001 G b00000000000000000000000000000001 I b00000000000000000000000000000001 K b00000000000000000000000000000001 M b00000000000000000000000000000001 Q b00000000000000000000000000000001 S b00000000000000000000000000000001 V b00000000000000000000000000000001 X b00000000000000000000000000000001 Y b00000000000000000000000000000001 [ b00000000000000000000000000000001 \ b00000000000000000000000000000001 ] b00000000000000000000000000000001 _ b00000010 d b00000001 e b00000000000000000000000000000001 i b00000000000000000000000000000001 j b00000000000000000000000000000001 l b00000000000000000000000000000010 o b00000000000000000000000000000010 p b00000000000000000000000000000001 u b00000000000000000000000000001000 v b00000000000000000000000000000110 w b00000000000000000000000000000010 x b00000000000000000000000000000010 y b00000000000000000000000000000001 | b00000000000000000000000000000001 } b0001 "! b00000000000000000000000000000001 $! b00000000000000000000000000000001 *! b00000000000000000000000000000001 +! b00000000000000000000000000000001 ,! b00000000000000000000000000000001 -! b00000000000000000000000000000001 .! b00000000000000000000000000000001 0! b00000000000000000000000000000001 1! b00000000000000000000000000000001 2! b00000000000000000000000000000001 3! b00000000000000000000000000000001 5! b00000000000000000000000000000001 6! b00000000000000000000000000000001 7! 18! b00000000000000000000000000000001 ;! b00000000000000000000000000000001 b00000011 ? b00000000000000000000000000000010 @ b00000000000000000000000000000010 B b00000000000000000000000000000010 C b00000000000000000000000000000010 E b00000000000000000000000000000010 G b00000000000000000000000000000010 I b00000000000000000000000000000010 K b00000000000000000000000000000010 M b00000000000000000000000000000010 Q b00000000000000000000000000000010 S b00000000000000000000000000000010 V b00000000000000000000000000000010 X b00000000000000000000000000000010 Y b00000000000000000000000000000010 [ b00000000000000000000000000000010 \ b00000000000000000000000000000010 ] b00000000000000000000000000000010 _ b00000000 d b00000000 e b00000000000000000000000000000010 h b00000000000000000000000000000010 i b00000000000000000000000000000010 j b00000000000000000000000000000010 l b00000000000000000000000000000011 o b00000000000000000000000000000011 p b00000000000000000000000000000010 t b00000000000000000000000000001100 v b00000000000000000000000000001001 w b00000000000000000000000000000011 x b00000000000000000000000000000011 y b00000000000000000000000000000010 | b00000000000000000000000000000010 } b0010 "! b00000000000000000000000000001010 #! b00000000000000000000000000000010 $! b00000000000000000000000000000001 %! b00000000000000000000000000000010 +! b00000000000000000000000000000010 ,! b00000000000000000000000000000010 -! b00000000000000000000000000000010 .! b00000000000000000000000000000010 0! b00000000000000000000000000000010 1! b00000000000000000000000000000010 2! b00000000000000000000000000000010 3! b00000000000000000000000000000010 5! b00000000000000000000000000000010 6! b00000000000000000000000000000010 7! 18! b00000000000000000000000000000010 ;! b00000000000000000000000000000010 b00000100 ? b00000000000000000000000000000011 @ b00000000000000000000000000000011 B b00000000000000000000000000000001 D b00000000000000000000000000000001 F b00000000000000000000000000000001 H b00000000000000000000000000000001 J b00000000000000000000000000000001 L b00000000000000000000000000000001 N b00000000000000000000000000000001 O b00000000000000000000000000000011 S b00000000000000000000000000000001 T b00000000000000000000000000000011 X b00000000000000000000000000000011 Y b00000000000000000000000000000011 [ b00000000000000000000000000000011 \ b00000000000000000000000000000011 ] b00000000000000000000000000000011 _ 1` b00000000000000000000000000000011 h b00000000000000000000000000000011 i b00000000000000000000000000000001 k b00000000000000000000000000000011 l b00000000000000000000000000000100 o b00000000000000000000000000000100 p b00000000000000000000000000000011 t b00000000000000000000000000010000 v b00000000000000000000000000001100 w b00000000000000000000000000000100 x b00000000000000000000000000000100 y b00000000000000000000000000000011 | b00000000000000000000000000000011 } b0011 "! b00000000000000000000000000010100 #! b00000000000000000000000000000011 $! b00000000000000000000000000000001 &! b00000000000000000000000000000011 +! b00000000000000000000000000000011 ,! b00000000000000000000000000000011 -! b00000000000000000000000000000011 .! b00000000000000000000000000000011 0! b00000000000000000000000000000011 1! b00000000000000000000000000000011 2! b00000000000000000000000000000011 3! b00000000000000000000000000000011 5! b00000000000000000000000000000011 6! b00000000000000000000000000000011 7! 18! b00000000000000000000000000000011 ;! b00000000000000000000000000000011 b00000101 ? b00000000000000000000000000000100 @ b00000000000000000000000000000100 B b00000000000000000000000000000011 C b00000000000000000000000000000011 E b00000000000000000000000000000011 G b00000000000000000000000000000011 I b00000000000000000000000000000011 K b00000000000000000000000000000011 M b00000000000000000000000000000001 P b00000000000000000000000000000100 S b00000000000000000000000000000011 V b00000000000000000000000000000100 X b00000000000000000000000000000001 Z b00000000000000000000000000000100 \ b00000000000000000000000000000001 ^ 0` 0b b00000000000000000000000000000100 h b00000000000000000000000000000100 i b00000000000000000000000000000011 j b00000000000000000000000000000100 l b00000000000000000000000000000101 o b00000000000000000000000000000001 q b00000000000000000000000000000001 r b00000000000000000000000000000100 t b00000000000000000000000000010100 v b00000000000000000000000000001111 w b00000000000000000000000000000101 x b00000000000000000000000000000101 y b00000000000000000000000000000100 | b00000000000000000000000000000001 ~ b00000000000000000000000000000001 !! b0100 "! b00000000000000000000000000011110 #! b00000000000000000000000000000100 $! b00000000000000000000000000000001 '! b00000000000000000000000000000100 +! b00000000000000000000000000000100 ,! b00000000000000000000000000000100 -! b00000000000000000000000000000001 /! b00000000000000000000000000000100 1! b00000000000000000000000000000100 2! b00000000000000000000000000000001 4! b00000000000000000000000000000100 6! b00000000000000000000000000000100 7! 18! b00000000000000000000000000000100 ;! b00000000000000000000000000000001 =! #45 0* 0+ b00000000000000000000000000001010 - b00000000000000000000000000001010 / b00000000000000000000000000000110 0 b00000000000000000000000000001110 5 b00000000000000000000000000001011 7 b00000000000000000000000000001000 9 08! #50 1* 1+ b00000000000000000000000000001011 - b00000000000000000000000000001011 / b00000000000000000000000000000101 1 b00000000000000000000000000010000 5 b00000000000000000000000000001101 7 b00000000000000000000000000001010 9 b00000000000000000000000000000110 > b00000110 ? b00000000000000000000000000000101 @ b00000000000000000000000000000101 B b00000000000000000000000000000100 C b00000000000000000000000000000100 E b00000000000000000000000000000100 G b00000000000000000000000000000100 I b00000000000000000000000000000100 K b00000000000000000000000000000100 M b00000000000000000000000000000001 R b00000000000000000000000000000101 S b00000000000000000000000000000001 U b00000000000000000000000000000101 X b00000000000000000000000000000100 Y b00000000000000000000000000000100 [ b00000000000000000000000000000101 \ b00000000000000000000000000000100 ] b00000000000000000000000000000100 _ 1b b00000000000000000000000000000101 h b00000000000000000000000000000101 i b00000000000000000000000000000100 j b00000000000000000000000000000101 l b00000000000000000000000000000110 o b00000000000000000000000000000101 p b00000000000000000000000000000101 t b00000000000000000000000000011000 v b00000000000000000000000000010010 w b00000000000000000000000000000110 x b00000000000000000000000000000110 y b00000000000000000000000000000101 | b00000000000000000000000000000100 } b0101 "! b00000000000000000000000000101000 #! b00000000000000000000000000000101 $! b00000000000000000000000000000001 (! b00000000000000000000000000000101 +! b00000000000000000000000000000101 ,! b00000000000000000000000000000101 -! b00000000000000000000000000000100 .! b00000000000000000000000000000100 0! b00000000000000000000000000000101 1! b00000000000000000000000000000101 2! b00000000000000000000000000000100 3! b00000000000000000000000000000100 5! b00000000000000000000000000000101 6! b00000000000000000000000000000101 7! 18! b00000000000000000000000000000001 9! b00000000000000000000000000000110 ;! b00000000000000000000000000000101 ! #55 0* 0+ b00000000000000000000000000001100 - b00000000000000000000000000001100 / b00000000000000000000000000000111 0 b00000000000000000000000000010001 5 b00000000000000000000000000001110 7 b00000000000000000000000000001011 9 08! #60 1* 1+ b00000000000000000000000000001101 - b00000000000000000000000000001101 / b00000000000000000000000000000110 1 b00000000000000000000000000010011 5 b00000000000000000000000000010000 7 b00000000000000000000000000001100 9 b00000000000000000000000000000111 : b00000000000000000000000000000100 < b00000000000000000000000000000111 > b00000111 ? b00000000000000000000000000000110 @ b00000000000000000000000000000110 B b00000000000000000000000000000101 C b00000000000000000000000000000101 E b00000000000000000000000000000101 G b00000000000000000000000000000101 I b00000000000000000000000000000101 K b00000000000000000000000000000101 M b00000000000000000000000000000011 Q b00000000000000000000000000000110 S b00000000000000000000000000000100 V b00000000000000000000000000000110 X b00000000000000000000000000000101 Y b00000000000000000000000000000101 [ b00000000000000000000000000000110 \ b00000000000000000000000000000101 ] b00000000000000000000000000000101 _ 1` b00000000000000000000000000000110 h b00000000000000000000000000000110 i b00000000000000000000000000000010 k b00000000000000000000000000000110 l b00000000000000000000000000000111 o b00000000000000000000000000000110 p b00000000000000000000000000000110 t b00000000000000000000000000011100 v b00000000000000000000000000010101 w b00000000000000000000000000000111 x b00000000000000000000000000000111 y b00000000000000000000000000000110 | b00000000000000000000000000000101 } b0110 "! b00000000000000000000000000110010 #! b00000000000000000000000000000110 $! b00000000000000000000000000000001 )! b00000000000000000000000000000110 +! b00000000000000000000000000000110 ,! b00000000000000000000000000000110 -! b00000000000000000000000000000101 .! b00000000000000000000000000000101 0! b00000000000000000000000000000110 1! b00000000000000000000000000000110 2! b00000000000000000000000000000101 3! b00000000000000000000000000000101 5! b00000000000000000000000000000110 6! b00000000000000000000000000000110 7! 18! b00000000000000000000000000000111 ;! b00000000000000000000000000000110 b00001000 ? b00000000000000000000000000000111 @ b00000000000000000000000000000111 B b00000000000000000000000000000110 C b00000000000000000000000000000110 E b00000000000000000000000000000110 G b00000000000000000000000000000110 I b00000000000000000000000000000110 K b00000000000000000000000000000110 M b00000000000000000000000000000100 Q b00000000000000000000000000000111 S b00000000000000000000000000000101 V b00000000000000000000000000000111 X b00000000000000000000000000000110 Y b00000000000000000000000000000110 [ b00000000000000000000000000000111 \ b00000000000000000000000000000110 ] b00000000000000000000000000000110 _ 0` b00000000000000000000000000000111 h b00000000000000000000000000000111 i b00000000000000000000000000000101 j b00000000000000000000000000000111 l b00000000000000000000000000001000 o b00000000000000000000000000000111 p b00000000000000000000000000000111 t b00000000000000000000000000100000 v b00000000000000000000000000011000 w b00000000000000000000000000001000 x b00000000000000000000000000001000 y b00000000000000000000000000000111 | b00000000000000000000000000000110 } b0111 "! b00000000000000000000000000000000 #! b00000000000000000000000000000111 $! b00000000000000000000000000000010 *! b00000000000000000000000000000111 +! b00000000000000000000000000000111 ,! b00000000000000000000000000000111 -! b00000000000000000000000000000110 .! b00000000000000000000000000000110 0! b00000000000000000000000000000111 1! b00000000000000000000000000000111 2! b00000000000000000000000000000110 3! b00000000000000000000000000000110 5! b00000000000000000000000000000111 6! b00000000000000000000000000000111 7! 18! b00000000000000000000000000001000 ;! b00000000000000000000000000000111 b00001001 ? b00000000000000000000000000001000 @ b00000000000000000000000000001000 B b00000000000000000000000000000111 C b00000000000000000000000000000111 E b00000000000000000000000000000111 G b00000000000000000000000000000111 I b00000000000000000000000000000111 K b00000000000000000000000000000111 M b00000000000000000000000000000101 Q b00000000000000000000000000001000 S b00000000000000000000000000000110 V b00000000000000000000000000001000 X b00000000000000000000000000000111 Y b00000000000000000000000000000111 [ b00000000000000000000000000001000 \ b00000000000000000000000000000111 ] b00000000000000000000000000000111 _ b00000000000000000000000000001000 h b00000000000000000000000000001000 i b00000000000000000000000000000110 j b00000000000000000000000000001000 l b00000000000000000000000000001001 o b00000000000000000000000000001000 p b00000000000000000000000000001000 t b00000000000000000000000000100100 v b00000000000000000000000000011011 w b00000000000000000000000000001001 x b00000000000000000000000000001001 y b00000000000000000000000000001000 | b00000000000000000000000000000111 } b1000 "! b00000000000000000000000000001000 $! b00000000000000000000000000000011 *! b00000000000000000000000000001000 +! b00000000000000000000000000001000 ,! b00000000000000000000000000001000 -! b00000000000000000000000000000111 .! b00000000000000000000000000000111 0! b00000000000000000000000000001000 1! b00000000000000000000000000001000 2! b00000000000000000000000000000111 3! b00000000000000000000000000000111 5! b00000000000000000000000000001000 6! b00000000000000000000000000001000 7! 18! b00000000000000000000000000001001 ;! b00000000000000000000000000001000 b00001010 ? b00000000000000000000000000001001 @ b00000000000000000000000000001001 B b00000000000000000000000000001000 C b00000000000000000000000000001000 E b00000000000000000000000000001000 G b00000000000000000000000000001000 I b00000000000000000000000000001000 K b00000000000000000000000000001000 M b00000000000000000000000000000110 Q b00000000000000000000000000001001 S b00000000000000000000000000000111 V b00000000000000000000000000001001 X b00000000000000000000000000001000 Y b00000000000000000000000000001000 [ b00000000000000000000000000001001 \ b00000000000000000000000000001000 ] b00000000000000000000000000001000 _ 1` b00000000000000000000000000001001 h b00000000000000000000000000001001 i b00000000000000000000000000000011 k b00000000000000000000000000001001 l b00000000000000000000000000001010 o b00000000000000000000000000001001 p b00000000000000000000000000001001 t b00000000000000000000000000101000 v b00000000000000000000000000011110 w b00000000000000000000000000001010 x b00000000000000000000000000001010 y b00000000000000000000000000001001 | b00000000000000000000000000001000 } b1001 "! b00000000000000000000000000001001 $! b00000000000000000000000000000100 *! b00000000000000000000000000001001 +! b00000000000000000000000000001001 ,! b00000000000000000000000000001001 -! b00000000000000000000000000001000 .! b00000000000000000000000000001000 0! b00000000000000000000000000001001 1! b00000000000000000000000000001001 2! b00000000000000000000000000001000 3! b00000000000000000000000000001000 5! b00000000000000000000000000001001 6! b00000000000000000000000000001001 7! 18! b00000000000000000000000000001010 ;! b00000000000000000000000000001001 b00001011 ? b00000000000000000000000000001010 @ b00000000000000000000000000001010 B b00000000000000000000000000001001 C b00000000000000000000000000001001 E b00000000000000000000000000001001 G b00000000000000000000000000001001 I b00000000000000000000000000001001 K b00000000000000000000000000001001 M b00000000000000000000000000000111 Q b00000000000000000000000000001010 S b00000000000000000000000000000001 W b00000000000000000000000000001010 X b00000000000000000000000000001001 Y b00000000000000000000000000001001 [ b00000000000000000000000000001010 \ b00000000000000000000000000001001 ] b00000000000000000000000000001001 _ 0` b00000000000000000000000000001010 h b00000000000000000000000000001010 i b00000000000000000000000000000111 j b00000000000000000000000000001010 l b00000000000000000000000000001011 o b00000000000000000000000000001010 p b00000000000000000000000000001010 t b00000000000000000000000000101100 v b00000000000000000000000000100001 w b00000000000000000000000000001011 x b00000000000000000000000000001011 y b00000000000000000000000000001010 | b00000000000000000000000000001001 } b1010 "! b00000000000000000000000000001010 $! b00000000000000000000000000000101 *! b00000000000000000000000000001010 +! b00000000000000000000000000001010 ,! b00000000000000000000000000001010 -! b00000000000000000000000000001001 .! b00000000000000000000000000001001 0! b00000000000000000000000000001010 1! b00000000000000000000000000001010 2! b00000000000000000000000000001001 3! b00000000000000000000000000001001 5! b00000000000000000000000000001010 6! b00000000000000000000000000001010 7! 18! b00000000000000000000000000001011 ;! b00000000000000000000000000001010 ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_process_rand.v0000644000542200017500000000236715101701376022272 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; process p; integer seed; string state; int a; int b; initial begin p = process::self(); // Test setting RNG state with state string state = p.get_randstate(); p.set_randstate(state); a = $random; p.set_randstate(state); b = $random; $display("a=%d, b=%d", a, b); if (a != b) $stop; // Test the same with $urandom state = p.get_randstate(); p.set_randstate(state); a = $urandom; p.set_randstate(state); b = $urandom; $display("a=%d, b=%d", a, b); if (a != b) $stop; // Test if the results repeat after the state is reset state = p.get_randstate(); for (int i = 0; i < 10; i++) $random; a = $random; // Now reset the state and take 11th result again p.set_randstate(state); for (int i = 0; i < 10; i++) $random; b = $random; $display("a=%d, b=%d", a, b); if (a != b) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_extend_c_class.py0000755000542200017500000000100115101701376022734 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(make_flags=["CPPFLAGS_ADD=-I" + test.t_dir]) test.execute() test.passes() verilator-5.042/test_regress/t/t_while_cond_is_stmt.py0000755000542200017500000000073415101701376023647 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_func_unit.py0000755000542200017500000000073415101701376021764 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_debug_trace.v0000644000542200017500000000056715101701376022054 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Dotted reference that uses another dotted reference // as the select expression // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs a ); input a; sub sub (); endmodule module sub; reg svar; endmodule verilator-5.042/test_regress/t/t_for_local.py0000755000542200017500000000073415101701376021732 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_dpi_open_oob_bad.py0000755000542200017500000000124115101701376023226 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(v_flags2=["t/t_dpi_open_oob_bad_c.cpp"], verilator_flags2=["-Wall -Wno-DECLFILENAME -unroll-count 1"]) test.execute( fails=False, # DPI warnings are not errors expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_disable_within_task_unsup.py0000755000542200017500000000103015101701376025221 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.lint(verilator_flags2=['--timing'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_nba_commit_queue.py0000755000542200017500000000127015101701376023302 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(verilator_flags2=["-unroll-count 1", "--stats"]) test.execute() test.file_grep(test.stats, r'NBA, variables using ValueQueueWhole scheme\s+(\d+)', 6) test.file_grep(test.stats, r'NBA, variables using ValueQueuePartial scheme\s+(\d+)', 3) test.passes() verilator-5.042/test_regress/t/t_pp_circdef_bad.py0000755000542200017500000000112715101701376022673 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True) # EOF result varies with Bison version, so can't use .out test.file_grep(test.compile_log_filename, r'define or other nested inclusion') test.passes() verilator-5.042/test_regress/t/t_nba_shared_flag_reuse.py0000755000542200017500000000077115101701376024255 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--binary']) test.execute() test.passes() verilator-5.042/test_regress/t/t_unpacked_slice.v0000644000542200017500000000361015101701376022551 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module t; parameter int sliceddn[4:-3] = '{'h100, 'h101, 'h102, 'h103, 'h104, 'h105, 'h106, 'h107}; parameter int slicedup[-3:4] = '{'h100, 'h101, 'h102, 'h103, 'h104, 'h105, 'h106, 'h107}; int alldn[7:0]; int allup[0:7]; int twodn[1:0]; int twoup[0:1]; initial begin `checkh(sliceddn[4], 'h100); alldn[7:0] = sliceddn[4:-3]; `checkh(alldn[7], 'h100); alldn[7:0] = sliceddn[-3 +: 8]; // down: lsb/lo +: width `checkh(alldn[7], 'h100); alldn[7:0] = sliceddn[4 -: 8]; // down: msb/hi -: width `checkh(alldn[7], 'h100); twodn[1:0] = sliceddn[3:2]; `checkh(twodn[1], 'h101); `checkh(twodn[0], 'h102); twodn[1:0] = sliceddn[1 +: 2]; `checkh(twodn[1], 'h102); `checkh(twodn[0], 'h103); twodn[1:0] = sliceddn[1 -: 2]; `checkh(twodn[1], 'h103); `checkh(twodn[0], 'h104); `checkh(slicedup[4], 'h107); allup[0:7] = slicedup[-3:4]; `checkh(alldn[7], 'h100); allup[0:7] = slicedup[-3 +: 8]; // up: msb/lo +: width `checkh(alldn[7], 'h100); allup[0:7] = slicedup[4 -: 8]; // up: lsb/hi -: width `checkh(alldn[7], 'h100); twoup[0:1] = slicedup[2:3]; `checkh(twoup[1], 'h106); `checkh(twoup[0], 'h105); twoup[0:1] = slicedup[1 +: 2]; `checkh(twoup[1], 'h105); `checkh(twoup[0], 'h104); twoup[0:1] = slicedup[1 -: 2]; `checkh(twoup[1], 'h104); `checkh(twoup[0], 'h103); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_timing_always.py0000755000542200017500000000077115101701376022642 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_randomize_with_constraint.out0000644000542200017500000000073715101701376025440 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_randomize_with_constraint.v:13:26: Unsupported: 'randomize with (...) {...}' 13 | return obj.randomize() with ( | ^~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_randomize_with_constraint.v:21:26: Unsupported: 'randomize with (...) {...}' 21 | return obj.randomize() with ( | ^~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_vpi_stop_bad.v0000644000542200017500000000105215101701376022247 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; import "DPI-C" function void dpii_test(); initial begin dpii_test(); $display("Should have stopped above"); //$write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_param_store_bad.py0000755000542200017500000000076615101701376023121 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_property_fail_1.py0000755000542200017500000000126015101701376023064 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_property.v" test.compile(v_flags2=['+define+FAIL_ASSERT_1'], verilator_flags2=['--assert --cc']) test.execute() # We expect to get a message when this assert fires: test.file_grep(test.run_log_filename, r'cyc != 3') test.passes() verilator-5.042/test_regress/t/t_lint_multiple_msgs.v0000644000542200017500000000065615101701376023521 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( input [3:1] i3, input [4:1] i4, output [3:1] o3, output [4:1] o4 ); // verilator lint_off WIDTHTRUNC,WIDTHEXPAND // after slashes ignored assign o3 = i4; assign o4 = i3; endmodule verilator-5.042/test_regress/t/t_json_only_flat.py0000755000542200017500000000144515101701376023012 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_json_only_first.v" out_filename = test.obj_dir + "/V" + test.name + ".tree.json" test.compile(verilator_flags2=['--no-std', '--json-only', '--no-json-edit-nums', '--flatten'], verilator_make_gmake=False, make_top_shell=False, make_main=False) test.files_identical(out_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_inst_paren_bad.out0000644000542200017500000000152415101701376023114 0ustar mahmoudyfreeshell%Warning-MULTITOP: t/t_inst_paren_bad.v:10:8: Multiple top level modules : ... Suggest see manual; fix the duplicates, or use --top-module to select top. ... For warning description see https://verilator.org/warn/MULTITOP?v=latest ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message. : ... Top module 'sub' 7 | module sub; | ^~~ : ... Top module 't' 10 | module t; | ^ %Error: t/t_inst_paren_bad.v:11:4: Can't find typedef/interface: 'sub' 11 | sub sub_inst; | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_class_extends_arg.v0000644000542200017500000000177415101701376023301 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); class Base; int m_s = 2; function new(int def = 3); m_s = def; endfunction endclass class Cls5Exp extends Base(5); int m_a = 11; function new(int def = 42); // Explicit new m_a = def; endfunction endclass class Cls5Imp extends Base(5); int m_a = 12; // Implicit new endclass module t (); Cls5Exp ce; Cls5Imp ci; initial begin ce = new(37); `checkh(ce.m_s, 5); `checkh(ce.m_a, 37); ci = new; `checkh(ci.m_s, 5); `checkh(ci.m_a, 12); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_inst_misarray2_bad.out0000644000542200017500000000067515101701376023726 0ustar mahmoudyfreeshell%Error: t/t_inst_misarray2_bad.v:10:17: Illegal input port connection 'i_data', mismatch between port which is not an array, and expression which is an array. (IEEE 1800-2023 7.6) : ... note: In instance 't' 10 | .i_data(fft_oQ[6:0]) | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_assert_synth_full_vlt.py0000755000542200017500000000134115101701376024422 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_assert_synth.v" test.compile(v_flags2=['+define+FAILING_FULL', "t/t_assert_synth_full.vlt"], verilator_flags2=['--assert'], nc_flags2=['+assert']) test.execute(check_finished=False, fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_func_plog.v0000644000542200017500000000525415101701376021562 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; reg rst_n; // Take CRC data and apply to testblock inputs /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [2:0] pos1; // From test of Test.v wire [2:0] pos2; // From test of Test.v // End of automatics Test test ( // Outputs .pos1 (pos1[2:0]), .pos2 (pos2[2:0]), /*AUTOINST*/ // Inputs .clk (clk), .rst_n (rst_n)); // Aggregate outputs into a single result vector wire [63:0] result = {61'h0, pos1}; // What checksum will we end up with `define EXPECTED_SUM 64'h039ea4d039c2e70b // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; rst_n <= ~1'b0; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; rst_n <= ~1'b1; end else if (cyc<10) begin sum <= 64'h0; rst_n <= ~1'b1; end else if (cyc<90) begin if (pos1 !== pos2) $stop; end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test #(parameter SAMPLE_WIDTH = 5 ) ( `ifdef verilator // Some simulators don't support clog2 output reg [$clog2(SAMPLE_WIDTH)-1:0] pos1, `else output reg [log2(SAMPLE_WIDTH-1)-1:0] pos1, `endif output reg [log2(SAMPLE_WIDTH-1)-1:0] pos2, // System input clk, input rst_n ); function integer log2(input integer arg); begin for(log2=0; arg>0; log2=log2+1) arg = (arg >> 1); end endfunction always @ (posedge clk or negedge rst_n) if (!rst_n) begin pos1 <= 0; pos2 <= 0; end else begin pos1 <= pos1 + 1; pos2 <= pos2 + 1; end endmodule verilator-5.042/test_regress/t/t_lint_edge_real_bad.py0000755000542200017500000000076315101701376023537 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_timescale_parse_bad.out0000644000542200017500000000232215101701376024107 0ustar mahmoudyfreeshell%Error: t/t_timescale_parse_bad.v:8:1: `timescale timeunit '1ps' must be greater than or equal to timeprecision '1ns' 8 | `timescale 1ps/1ns | ^~~~~~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_timescale_parse_bad.v:11:1: `timescale timeunit syntax error: 'frump' 11 | `timescale frump | ^~~~~~~~~~~~~~~~ %Error: t/t_timescale_parse_bad.v:12:1: `timescale timeunit syntax error: '1xs' 12 | `timescale 1xs | ^~~~~~~~~~~~~~ %Error: t/t_timescale_parse_bad.v:13:1: `timescale timeunit syntax error: '2ps' 13 | `timescale 2ps | ^~~~~~~~~~~~~~ %Error: t/t_timescale_parse_bad.v:14:1: `timescale timeprecision syntax error: 'frump' 14 | `timescale 1ns / frump | ^~~~~~~~~~~~~~~~~~~~~~ %Error: t/t_timescale_parse_bad.v:15:1: `timescale syntax error: ' 1ns / 1ps /extra' 15 | `timescale 1ns / 1ps /extra | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ %Error: t/t_timescale_parse_bad.v:18:13: timeunit illegal value 18 | timeunit 2ps; | ^~~ %Error: t/t_timescale_parse_bad.v:19:18: timeprecision illegal value 19 | timeprecision 2ps; | ^~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_force_initial.v0000644000542200017500000000141715101701376022412 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); end while(0) module t; reg [1:0] a = 0; reg [1:0] b = 2; initial begin force b = a; `checkh(a, 0); `checkh(b, 0); end initial begin #1; `checkh(b, 0); a = 1; #1; `checkh(a, 1); `checkh(b, 1); a = 3; #1; `checkh(a, 3); `checkh(b, 3); release b; `checkh(a, 3); `checkh(b, 3); b = 0; #1; `checkh(b, 0); #1 $finish; end endmodule verilator-5.042/test_regress/t/t_class_member_sens.v0000644000542200017500000000114315101701376023263 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; class EventClass; event e; endclass EventClass ec = new; int cyc = 0; always @ec.e ec = new; always @(posedge clk) begin cyc <= cyc + 1; if (cyc == 1) ->ec.e; else if (cyc == 2) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_flag_wpedantic_bad.py0000755000542200017500000000102415101701376023540 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["-Wpedantic"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_iface_array_topmodule1.v0000644000542200017500000000177715101701376025260 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Josh Redford. // SPDX-License-Identifier: CC0-1.0 interface my_if; logic valid; logic [7:0] data ; modport slave_mp ( input valid, input data ); modport master_mp ( output valid, output data ); endinterface module t ( input wire clk, my_if.slave_mp in_if [2], my_if.master_mp out_if [2] ); my_if my_i [2] (); always @(posedge clk) begin my_i[0].valid <= in_if[0].valid; my_i[0].data <= in_if[0].data; my_i[1].valid <= in_if[1].valid; my_i[1].data <= in_if[1].data; end assign out_if[0].valid = my_i[0].valid; assign out_if[0].data = my_i[0].data; assign out_if[1].valid = my_i[1].valid; assign out_if[1].data = my_i[1].data; endmodule verilator-5.042/test_regress/t/t_wire_behp1800_bad.out0000644000542200017500000000153315101701376023227 0ustar mahmoudyfreeshell%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:23:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'w' : ... note: In instance 't' 23 | w = '0; | ^ ... For error description see https://verilator.org/warn/PROCASSWIRE?v=latest %Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:24:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'o' : ... note: In instance 't' 24 | o = '0; | ^ %Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:25:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'oa' : ... note: In instance 't' 25 | oa = '0; | ^~ %Error: Exiting due to verilator-5.042/test_regress/t/t_mod_topmodule.v0000644000542200017500000000124415101701376022450 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This test verifies that a top-module can be specified which // is instantiated beneath another module in the compiled source // code. // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Dan Petrisko // SPDX-License-Identifier: CC0-1.0 module top(/*AUTOARG*/ // Inputs clk ); input clk; always_ff @(posedge clk) begin $write("*-* All Finished *-*\n"); $finish(); end endmodule module faketop(/*AUTOARG*/ ); top top(); // Stop immediately if this module is instantiated initial begin $stop(); end endmodule verilator-5.042/test_regress/t/t_param_circ_bad.py0000755000542200017500000000076615101701376022705 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dfg_true_cycle_bad.v0000644000542200017500000000061415101701376023365 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 `default_nettype none module t( output wire [9:0] o ); assign o[1:0] = o[9:8]; assign o[3:2] = o[1:0]; assign o[7:4] = 4'(o[3:2]); assign o[9:8] = o[5:4]; endmodule verilator-5.042/test_regress/t/t_inst_tree.v0000644000542200017500000000403215101701376021573 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg printclk; ps ps (printclk); reg [7:0] a; wire [7:0] z; l1 u (~a,z); always @ (posedge clk) begin printclk <= 0; if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin printclk <= 1'b1; end if (cyc==2) begin a <= 8'b1; end if (cyc==3) begin if (z !== 8'hf8) $stop; //if (u.u1.u1.u1.u0.PARAM !== 1) $stop; //if (u.u1.u1.u1.u1.PARAM !== 2) $stop; //if (u.u0.u0.u0.u0.z !== 8'hfe) $stop; //if (u.u0.u0.u0.u1.z !== 8'hff) $stop; //if (u.u1.u1.u1.u0.z !== 8'h00) $stop; //if (u.u1.u1.u1.u1.z !== 8'h01) $stop; $write("*-* All Finished *-*\n"); $finish; end end end endmodule module ps (input printclk); // Check that %m stays correct across inlines always @ (posedge printclk) $write("[%0t] %m: Clocked\n", $time); endmodule module l1 (input [7:0] a, output [7:0] z); wire [7:0] z0; wire [7:0] z1; assign z = z0+z1; l2 u0 (a, z0); l2 u1 (a, z1); endmodule module l2 (input [7:0] a, output [7:0] z); wire [7:0] z0; wire [7:0] z1; assign z = z0+z1; wire [7:0] a1 = a+8'd1; l3 u0 (a, z0); l3 u1 (a1, z1); endmodule module l3 (input [7:0] a, output [7:0] z); wire [7:0] z0; wire [7:0] z1; assign z = z0+z1; wire [7:0] a1 = a+8'd1; l4 u0 (a, z0); l4 u1 (a1, z1); endmodule module l4 (input [7:0] a, output [7:0] z); wire [7:0] z0; wire [7:0] z1; assign z = z0+z1; wire [7:0] a1 = a+8'd1; l5 #(1) u0 (a, z0); l5 #(2) u1 (a1, z1); endmodule module l5 (input [7:0] a, output [7:0] z); parameter PARAM = 5; wire [7:0] z0; wire [7:0] z1; assign z = a; endmodule verilator-5.042/test_regress/t/t_past_unsup.out0000644000542200017500000000115315101701376022343 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_past_unsup.v:16:11: Unsupported: $past expr2 and/or clock arguments 16 | if ($past(d, 1, 1)) $stop; | ^~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_past_unsup.v:17:11: Unsupported: $past expr2 and/or clock arguments 17 | if ($past(d, 1, 1, )) $stop; | ^~~~~ %Error-UNSUPPORTED: t/t_past_unsup.v:18:11: Unsupported: $past expr2 and/or clock arguments 18 | if ($past(d, 1, 1, @(posedge clk))) $stop; | ^~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_randomize_member_select.v0000644000542200017500000000212715101701376024460 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class B; rand int insideB; constraint i { insideB inside {[0:10]}; }; endclass class A; rand logic[31:0] rdata; rand int delay; int i = 97; rand B b; function new(); b = new; endfunction constraint delay_bounds { delay inside {[0:2]}; } endclass module t; A a; int i; int delay; logic[31:0] rdata; int b; initial begin a = new; i = 7; repeat (120) begin a.b.insideB = 3; a.delay = 1; a.rdata = 3; if (a.randomize() with {if (a.delay == 1) a.rdata == i;} == 0) $stop; if (a.b.randomize() with {a.b.insideB < 3;} == 0) $stop; if (a.delay == 1 && a.rdata != 97) $stop; if (a.b.insideB >= 3) $stop; if (a.randomize() with {if (a.delay == 1) a.rdata == local::i;} == 0) $stop; if (a.delay == 1 && a.rdata != 7) $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_trace_off_sc.py0000755000542200017500000000121515101701376022402 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_ena.v" test.compile(verilator_flags2=['-notrace -sc']) test.execute() if test.vlt_all: if os.path.exists(test.trace_filename): test.error("Tracing should be off") test.passes() verilator-5.042/test_regress/t/t_math_shift_huge.py0000755000542200017500000000071415101701376023126 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.passes() verilator-5.042/test_regress/t/t_slice_struct_array_modport.v0000644000542200017500000000065115101701376025247 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Varun Koyyalagunta. // SPDX-License-Identifier: CC0-1.0 typedef struct packed { logic p; } s_data; module m1 (output s_data data[1:0]); assign data[0].p = 0; assign data[1].p = 0; endmodule module top (output s_data data[2:0]); m1 m1_inst (.data(data[1:0])); endmodule verilator-5.042/test_regress/t/t_mem_multidim.py0000755000542200017500000000073415101701376022454 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_past_unsup.py0000755000542200017500000000076315101701376022175 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_constraint_unsup.out0000644000542200017500000000045415101701376023563 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_constraint_unsup.v:9:22: Unsupported expression inside constraint 9 | constraint cons { $onehot(m_one) == 1; } | ^~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_cover_expr_max.py0000755000542200017500000000200615101701376023005 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap from pathlib import Path test.scenarios('simulator') test.top_filename = "t/t_cover_expr.v" test.compile(verilator_flags2=['--cc', '--coverage-expr', '--coverage-expr-max', '128']) test.execute() # Read the input .v file and do any CHECK_COVER requests test.inline_checks() test.run(cmd=[ os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--annotate-points", "--annotate", test.obj_dir + "/annotated", test.obj_dir + "/coverage.dat", ], verilator_run=True) top = Path(test.top_filename) test.files_identical(test.obj_dir + f"/annotated/{top.name}", test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_var_local.v0000644000542200017500000000307215101701376021544 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class cls; static task automatic tsk1; integer task_assign = 1; if (task_assign != 1) $stop; task_assign = 2; if (task_assign != 2) $stop; endtask static task tsk2; integer task_assign = 1; if (task_assign != 1) $stop; task_assign = 2; if (task_assign != 2) $stop; endtask endclass module t; integer top; integer top_assign=1; task automatic tsk; integer task_assign = 1; if (task_assign != 1) $stop; task_assign = 2; if (task_assign != 2) $stop; endtask initial begin begin : a integer lower; integer lower_assign=1; lower = 1; top = 1; if (lower != 1) $stop; if (lower_assign != 1) $stop; begin : aa integer lev2; lev2 = 1; lower = 2; lower_assign = 2; top = 2; end if (lower != 2) $stop; if (lower_assign != 2) $stop; end begin : b integer lower; lower = 1; top = 2; begin : empty begin : empty end end end // Repeat task calls to ensure we reinit the initial value tsk; tsk; cls::tsk1(); cls::tsk1(); cls::tsk2(); cls::tsk2(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_math_shift_extend.v0000644000542200017500000000261215101701376023276 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; logic in1 = 1; logic [1:0] in2 = 2'b11; logic [31:0] out; logic [7:0] ones = 8'b11111111; logic [9:0] ones10 = 10'b1111111111; typedef logic [7:0] data_t; typedef logic [9:0] ten_t; ten_t out10; // verilator lint_off WIDTH initial begin in1 = 1; in2 = 0; out = data_t'(in1 << in2); if (out != 8'b1) $stop; in2 = 1; out = data_t'(in1 << in2); if (out != 8'b10) $stop; in2 = 2; out = data_t'(in1 << in2); if (out != 8'b100) $stop; in2 = 3; out = data_t'(in1 << in2); if (out != 8'b1000) $stop; // Check upper bits get cleared when cast in2 = 3; out = data_t'(ones << in2); if (out != 8'b11111000) $stop; in2 = 3; out = data_t'(ones10 << in2); if (out != 8'b11111000) $stop; // bug2597 out = data_t'(10'h208 >> 2); if (out != 8'h82) $stop; out = data_t'(10'h208 >> 2); if (out != 8'h82) $stop; out = data_t'('h208 >> 2); if (out != 8'h82) $stop; out10 = ten_t'('h404 >> 2); if (out10 != 10'h101) $stop; $write("*-* All Finished *-*\n"); $finish(); end endmodule verilator-5.042/test_regress/t/t_select_bad_msb.v0000644000542200017500000000067215101701376022533 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; reg [43:0] mi; reg [3:0] sel2; reg [0:22] backwd; always @ (posedge clk) begin mi = 44'h123; sel2 = mi[1:4]; $write ("Bad select %x\n", sel2); end endmodule verilator-5.042/test_regress/t/t_param_module.v0000644000542200017500000000241315101701376022245 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This test case is used for testing a modeule parameterized with a typed // localparam. // // We find Verilator appears to mis-evaluate the parameter WIDTH as -16 when // used in the test module to set the value of MSB. A number of warnings and // errors follow, starting with: // // %Warning-ASCRANGE: t/t_param_module.v:42: Ascending bit range vector: MSB // < LSB of bit range: -17:0 // // This file ONLY is placed into the Public Domain, for any use, without // warranty, 2013 by Jie Xu. // SPDX-License-Identifier: CC0-1.0 // bug606 module t (/*AUTOARG*/ // Inputs clk ); input clk; localparam logic[4:0] WID = 16; //localparam WID = 16; // No problem if defined like this wire [15:0] b33; test #(WID) i_test_33(.clk (clk), .b (b33)); endmodule module test (/*AUTOARG*/ //Inputs clk, // Outputs b ); parameter WIDTH = 10; localparam MSB = WIDTH - 1; input clk; output wire [MSB:0] b; wire [MSB:0] a; assign b = {~a[MSB-1:0], clk}; initial begin if ($bits(WIDTH)!=5) $stop; // Comes from the parent! if ($bits(MSB)!=32) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_unconnected_bad.out0000644000542200017500000000077215101701376023263 0ustar mahmoudyfreeshell%Error: t/t_unconnected_bad.v:7:1: Bad `unconnected_drive syntax 7 | `unconnected_drive | ^~~~~~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_unconnected_bad.v:9:1: Bad `unconnected_drive syntax 9 | `unconnected_drive pull2 | ^~~~~~~~~~~~~~~~~~ %Error: t/t_unconnected_bad.v:9:20: syntax error, unexpected IDENTIFIER 9 | `unconnected_drive pull2 | ^~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_assign_automatic_bad.py0000755000542200017500000000076615101701376024137 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_debug_width.out0000644000542200017500000000053015101701376022425 0ustar mahmoudyfreeshell%Error: Internal Error: t/t_opt_const.v:12:8: ../V3Ast.cpp:#: widthMismatch detected 'lhsp()->widthMin() != rhsp()->widthMin()' @ ../V3AstNodes.cpp:#OUT:(G/wu32/1) LHS:(G/w32) RHS:(G/wu32/1) 12 | module t( | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. verilator-5.042/test_regress/t/t_flag_fi.py0000755000542200017500000000114215101701376021353 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(make_top_shell=False, make_main=False, v_flags2=["-FI", test.t_dir + "/t_flag_fi_h.h", "--exe", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_unopt_array.v0000644000542200017500000000453515101701376022152 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [31:0] out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out (out[31:0]), // Inputs .clk (clk), .in (in[31:0])); // Aggregate outputs into a single result vector wire [63:0] result = {32'h0, out}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h458c2de282e30f8b if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs out, // Inputs clk, in ); input clk; input [31:0] in; output wire [31:0] out; `ifdef USE_TYPEDEF typedef reg [3:0][31:0] stage_t [3:0]; stage_t stage; `else reg [3:0][31:0] stage [3:0]; `endif genvar g; generate for (g=0; g<4; g++) begin always_comb begin if (g==0) stage[g] = {4{in}}; else stage[g] = {4{stage[g-1][0][30:0],1'b1}}; end end endgenerate assign out = stage[3][0]; endmodule verilator-5.042/test_regress/t/t_disable.v0000644000542200017500000000101315101701376021176 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin fork : foo disable foo; #1 $stop; join_none #2; begin : forked fork disable forked; #1 $stop; join_none end #2; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_lint_const_func_dpi_bad.v0000644000542200017500000000046615101701376024437 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Donald Owen. // SPDX-License-Identifier: CC0-1.0 module t (); import "DPI-C" function int dpiFunc(); localparam PARAM = dpiFunc(); endmodule verilator-5.042/test_regress/t/t_randomize_inline_var_ctl_bad.v0000644000542200017500000000104015101701376025441 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Foo; int x; function void test; int y; void'(randomize(y)); endfunction endclass class Bar; int y; endclass module t; initial begin Foo foo = new; Foo qux = new; Bar bar = new; int x; void'(foo.randomize(x, foo.x, null, qux.x, bar.y, 0 + 1, x ** 2)); end endmodule verilator-5.042/test_regress/t/t_std_randomize_no_args.py0000755000542200017500000000074615101701376024347 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.lint(verilator_flags2=["--binary"]) test.passes() verilator-5.042/test_regress/t/t_gen_local.py0000755000542200017500000000073415101701376021715 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_didnotconverge_nodbg_bad.py0000755000542200017500000000152115101701376026004 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_lint_didnotconverge_bad.v" if not os.path.exists(test.root + "/.git"): test.skip("Not in a git repository") test.compile(make_flags=['CPPFLAGS_ADD=-UVL_DEBUG']) test.execute(fails=True, expect_filename=test.golden_filename) test.extract(in_filename=test.golden_filename, out_filename=test.root + "/docs/gen/ex_DIDNOTCONVERGE_nodbg_msg.rst", lines="1") test.passes() verilator-5.042/test_regress/t/t_program.v0000644000542200017500000000047315101701376021253 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 program t; initial begin $write("*-* All Finished *-*\n"); $finish; end endprogram verilator-5.042/test_regress/t/t_lint_procassinit_bad.py0000755000542200017500000000176415101701376024170 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=['-Wall -Wno-DECLFILENAME'], fails=True, expect_filename=test.golden_filename) test.extract(in_filename=test.top_filename, out_filename=test.root + "/docs/gen/ex_PROCASSINIT_faulty.rst", lines="26-32") test.extract(in_filename=test.top_filename, out_filename=test.root + "/docs/gen/ex_PROCASSINIT_fixed.rst", lines="36-45") test.extract(in_filename=test.golden_filename, out_filename=test.root + "/docs/gen/ex_PROCASSINIT_msg.rst", lines="1-9") test.passes() verilator-5.042/test_regress/t/t_math_clog2.py0000755000542200017500000000073415101701376022011 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_select_bound3.v0000644000542200017500000000137715101701376022341 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2025 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 class cls; int m_field; endclass module t(); cls inst[2]; initial begin // Loop (even just 1 iteration) is needed to reproduce the error for (int i = 0; i < 2; ++i) begin inst[i] = new(); inst[i].m_field = i; end for (int i = 0; i < 2; ++i) begin if (inst[i].m_field != i) $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_inst_mism.py0000755000542200017500000000073415101701376021774 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_flag_compiler_bad.py0000755000542200017500000000106015101701376023374 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--compiler bad_one"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_opt_assemble_cellarray.py0000755000542200017500000000125015101701376024477 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=["--stats -fno-dfg"]) test.execute() if test.vlt_all: test.file_grep(test.stats, r'Optimizations, Gate assign merged\s+(\d+)', 28) test.file_grep(test.stats, r'Optimizations, Concat merges\s+(\d+)', 42) test.passes() verilator-5.042/test_regress/t/t_for_assign.py0000755000542200017500000000073415101701376022124 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_clocker.py0000755000542200017500000000107315101701376021411 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--trace-vcd"]) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface_wrong_bad.py0000755000542200017500000000076615101701376023761 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_opt_localize_max_size.py0000755000542200017500000000116715101701376024356 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["--stats"]) test.execute() # Value must differ from that in t_opt_localize_max_size.py test.file_grep(test.stats, r'Optimizations, Vars localized\s+(\d+)', 1) test.passes() verilator-5.042/test_regress/t/t_dpi_if_cond.py0000755000542200017500000000077615101701376022235 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=["t/t_dpi_if_cond_c.cpp"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_fork_func2_bad.py0000755000542200017500000000103015101701376022624 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=['--lint-only'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_trace_scope_vlt.py0000755000542200017500000000116515101701376023145 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_trace_scope_vlt.v" test.compile(v_flags2=["--trace-vcd t/t_trace_scope_vlt.vlt"]) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_pipe_exit_bad_pf.pf0000755000542200017500000000101215101701376023216 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # mypy: disallow-untyped-defs # pylint: disable=C0114 # # DESCRIPTION: Verilator: Verilog Test example --pipe-filter script # # Copyright 2010 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import sys sys.exit("%Error: t_pipe_exit_bad_pf.pf: Intentional bad exit status...") verilator-5.042/test_regress/t/t_tri_select_eqcase.py0000755000542200017500000000073415101701376023450 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_flag_future_bad.py0000755000542200017500000000103315101701376023074 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_flag_future.v" test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dfg_3679.py0000755000542200017500000000073415101701376021222 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_struct_genfor.py0000755000542200017500000000070615101701376022655 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.042/test_regress/t/t_dfg_3679.v0000644000542200017500000000176215101701376021036 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=1; reg [31:0] dly0; // DFG can fold this into 'dly3 = dly1 = dly0 + 1' and 'dly2 = dly0 + 2', // but the 'dly0 + 1' term having multiple sinks needs to considered. wire [31:0] dly1 = dly0 + 32'h1; wire [31:0] dly2 = dly1 + 32'h1; wire [31:0] dly3 = dly0 + 32'h1; always @ (posedge clk) begin $display("[%0t] dly0=%h dly1=%h dly2=%h dly3=%h", $time, dly0, dly1, dly2, dly3); cyc <= cyc + 1; if (cyc == 1) begin dly0 <= 32'h55; end else if (cyc == 3) begin if (dly1 !== 32'h56) $stop; if (dly2 !== 32'h57) $stop; if (dly3 !== 32'h56) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_sv_bus_mux_demux/0000755000542200017500000000000015101701376023005 5ustar mahmoudyfreeshellverilator-5.042/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_demux.sv0000644000542200017500000000447515101701376030167 0ustar mahmoudyfreeshell//////////////////////////////////////////////////////////////////////////////// // // // This file is placed into the Public Domain, for any use, without warranty. // // 2012 by Iztok Jeras // // SPDX-License-Identifier: CC0-1.0 // // // //////////////////////////////////////////////////////////////////////////////// import package_bus::*; import package_str::*; module sv_bus_mux_demux_demux ( // system signals input logic clk, // clock input logic rst, // reset // output stream input logic str_vld, // valid (chip select) input logic [7:0] str_bus, // byte data bus output logic str_rdy, // ready (acknowledge) // input bus output logic bus_vld, // valid (chip select) output logic [31:0] bus_adr, // address output logic [31:0] bus_dat, // data input logic bus_rdy // ready (acknowledge) ); logic bus_trn; // bus data transfer logic str_trn; // stream data transfer logic [2:0] pkt_cnt; // packet byte counter logic pkt_end; // packet byte counter end t_str pkt_str; // transfer packet as a structure t_bus pkt_bus; // transfer packet as an array // stream data transfer assign str_trn = str_vld & str_rdy; // ready if pipe is empty or output is ready assign str_rdy = ~bus_vld | bus_rdy; // packet byte counter always @ (posedge clk, posedge rst) if (rst) pkt_cnt <= 3'd0; else if (str_trn) pkt_cnt <= pkt_cnt + 3'd1; // packet byte counter end assign pkt_end = (&pkt_cnt); always @ (posedge clk) if (str_trn) pkt_str [pkt_cnt] <= str_bus; // the input packed array is mapped onto the output structure assign pkt_bus = pkt_str; // the output structure is mapped onto address/data outputs assign bus_adr = pkt_bus.adr; assign bus_dat = pkt_bus.dat; // output valid is set on the last input packed byte // or cleared by each output transfer always @ (posedge clk, posedge rst) if (rst) bus_vld <= 1'b0; else bus_vld <= str_trn & pkt_end | bus_vld & ~bus_rdy; // bus data transfer assign bus_trn = bus_vld & bus_rdy; endmodule : sv_bus_mux_demux_demux verilator-5.042/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_wrap.sv0000644000542200017500000000660315101701376030011 0ustar mahmoudyfreeshell//////////////////////////////////////////////////////////////////////////////// // // // This file is placed into the Public Domain, for any use, without warranty. // // 2012 by Iztok Jeras // // SPDX-License-Identifier: CC0-1.0 // // // //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// // // // This wrapper contains a bus multiplexer and a bus demultiplexer. Both // // modules have all ports exposed an there are no signals connecting them. // // // // --------------------- // // | wrap | // // | | // // | ----------- | // // bsi -> | -> | mux | -> | -> sto // // | ----------- | // // | | // // | ----------- | // // bso <- | <- | demux | <- | <- sto // // | ----------- | // // | | // // --------------------- // // // //////////////////////////////////////////////////////////////////////////////// module sv_bus_mux_demux_wrap ( // system signals input logic clk, input logic rst, // input bus input logic bsi_vld, // valid (chip select) input logic [31:0] bsi_adr, // address input logic [31:0] bsi_dat, // data output logic bsi_rdy, // ready (acknowledge) // output stream output logic sto_vld, output logic [7:0] sto_bus, input logic sto_rdy, // input stream input logic sti_vld, input logic [7:0] sti_bus, output logic sti_rdy, // output bus output logic bso_vld, // valid (chip select) output logic [31:0] bso_adr, // address output logic [31:0] bso_dat, // data input logic bso_rdy // ready (acknowledge) ); sv_bus_mux_demux_mux mux ( // system signals .clk (clk), .rst (rst), // input bus .bus_vld (bsi_vld), .bus_adr (bsi_adr), .bus_dat (bsi_dat), .bus_rdy (bsi_rdy), // output stream .str_vld (sto_vld), .str_bus (sto_bus), .str_rdy (sto_rdy) ); sv_bus_mux_demux_demux demux ( // system signals .clk (clk), .rst (rst), // input stream .str_vld (sti_vld), .str_bus (sti_bus), .str_rdy (sti_rdy), // output bus .bus_vld (bso_vld), .bus_adr (bso_adr), .bus_dat (bso_dat), .bus_rdy (bso_rdy) ); endmodule : sv_bus_mux_demux_wrap verilator-5.042/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv0000644000542200017500000000212115101701376027565 0ustar mahmoudyfreeshell//////////////////////////////////////////////////////////////////////////////// // // // This file is placed into the Public Domain, for any use, without warranty. // // 2012 by Iztok Jeras // // SPDX-License-Identifier: CC0-1.0 // // // //////////////////////////////////////////////////////////////////////////////// // definition of data bus structure package package_bus; typedef struct packed { logic [3:0] [7:0] adr; // address logic [3:0] [7:0] dat; // data } t_bus; endpackage : package_bus // definition of streaming bus packet as an array package package_str; typedef logic [7:0][7:0] t_str; endpackage : package_str // union of the structure and array representation package package_uni; import package_bus::*; import package_str::*; typedef union packed { t_bus bus; t_str str; } t_uni; endpackage : package_uni verilator-5.042/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_mux.sv0000644000542200017500000000455715101701376027657 0ustar mahmoudyfreeshell//////////////////////////////////////////////////////////////////////////////// // // // This file is placed into the Public Domain, for any use, without warranty. // // 2012 by Iztok Jeras // // SPDX-License-Identifier: CC0-1.0 // // // //////////////////////////////////////////////////////////////////////////////// import package_bus::*; import package_str::*; import package_uni::*; module sv_bus_mux_demux_mux ( // system signals input logic clk, // clock input logic rst, // reset // input bus input logic bus_vld, // valid (chip select) input logic [31:0] bus_adr, // address input logic [31:0] bus_dat, // data output logic bus_rdy, // ready (acknowledge) // output stream output logic str_vld, // valid (chip select) output logic [7:0] str_bus, // byte data bus input logic str_rdy // ready (acknowledge) ); logic bus_trn; // bus data transfer logic str_trn; // stream data transfer logic [2:0] pkt_cnt; // packet byte counter logic pkt_end; // packet byte counter end //t_bus pkt_bus; // transfer packet as a structure //t_str pkt_str; // transfer packet as an array t_uni pkt_uni; // transfer packet as an union // bus data transfer assign bus_trn = bus_vld & bus_rdy; // ready if pipe is empty or output is ready assign bus_rdy = ~str_vld | pkt_end; // writing input address/data into a structure always @ (posedge clk) if (bus_trn) begin pkt_uni.bus.adr <= bus_adr; pkt_uni.bus.dat <= bus_dat; end // output valid is set by an input transfer // or cleared by the last output transfer always @ (posedge clk, posedge rst) if (rst) str_vld <= 1'b0; else str_vld <= bus_trn | (str_vld & ~pkt_end); // packet byte counter always @ (posedge clk, posedge rst) if (rst) pkt_cnt <= '0; else if (str_trn) pkt_cnt <= pkt_cnt + 3'd1; // packet byte counter end assign pkt_end = str_rdy & (&pkt_cnt); // TODO, this should be a registered signal assign str_bus = pkt_uni.str [pkt_cnt]; // stream data transfer assign str_trn = str_vld & str_rdy; endmodule : sv_bus_mux_demux_mux verilator-5.042/test_regress/t/t_cover_unused_bad.v0000644000542200017500000000057015101701376023111 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; logic unu3 = 0; logic isusd = 0; cover property (@(posedge clk) isusd == 0); endmodule verilator-5.042/test_regress/t/t_interface_virtual_unused.py0000755000542200017500000000073415101701376025063 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_enum_bad_cell.out0000644000542200017500000000101415101701376022707 0ustar mahmoudyfreeshell%Warning-VARHIDDEN: t/t_enum_bad_cell.v:12:14: Declaration of enum value hides declaration in upper scope: s1 12 | enum {s0, s1} state; | ^~ t/t_enum_bad_cell.v:8:8: ... Location of original declaration 8 | sub s1(); | ^~ ... For warning description see https://verilator.org/warn/VARHIDDEN?v=latest ... Use "/* verilator lint_off VARHIDDEN */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_fuzz_triand_bad.v0000644000542200017500000000037715101701376022754 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (); tri g=g.and.g; endmodule verilator-5.042/test_regress/t/t_class_mod_bad.py0000755000542200017500000000076615101701376022551 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_func_outfirst.py0000755000542200017500000000073415101701376022664 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_extract_static_const.v0000644000542200017500000000277115101701376024036 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 module t; bit [255:0] C; initial C = {32'h1111_1111, 32'h2222_2222, 32'h3333_3333, 32'h4444_4444, 32'h5555_5555, 32'h6666_6666, 32'h7777_7777, 32'h8888_8888}; // Same values as above, but with different type logic [255:0] D; initial D = {32'h1111_1111, 32'h2222_2222, 32'h3333_3333, 32'h4444_4444, 32'h5555_5555, 32'h6666_6666, 32'h7777_7777, 32'h8888_8888}; int i; initial begin // Note: Base index via $c to prevent optimization by Verilator i = $c(0*32); $display("0x%8x", C[i+:32]); i = $c(1*32); $display("0x%8x", D[i+:32]); i = $c(2*32); $display("0x%8x", C[i+:32]); i = $c(3*32); $display("0x%8x", D[i+:32]); i = $c(4*32); $display("0x%8x", C[i+:32]); i = $c(5*32); $display("0x%8x", D[i+:32]); i = $c(6*32); $display("0x%8x", C[i+:32]); i = $c(7*32); $display("0x%8x", D[i+:32]); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_hier_block_sc_trace_fst.py0000755000542200017500000000314515101701376024611 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_hier_block.v" # stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. test.clean_objs() # CI environment offers 2 VCPUs, 2 thread setting causes the following warning. # %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. # So use 6 threads here though it's not optimal in performance, but ok. test.compile(v_flags2=['t/t_hier_block.cpp'], verilator_flags2=[ '--sc', '--stats', '--hierarchical', '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"', "--CFLAGS", '"-O0 -ggdb"', "--trace-fst" ], threads=(6 if test.vltmt else 1)) test.execute() test.file_grep(test.obj_dir + "/Vsub0/sub0.sv", r'^module\s+(\S+)\s+', "sub0") test.file_grep(test.obj_dir + "/Vsub1/sub1.sv", r'^module\s+(\S+)\s+', "sub1") test.file_grep(test.obj_dir + "/Vsub2/sub2.sv", r'^module\s+(\S+)\s+', "sub2") test.file_grep(test.stats, r'HierBlock,\s+Hierarchical blocks\s+(\d+)', 14) test.file_grep(test.run_log_filename, r'MACRO:(\S+) is defined', "cplusplus") test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface_virtual_unused2.py0000755000542200017500000000073415101701376025145 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_timescale_unit.v0000644000542200017500000000107415101701376022607 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under The Creative Commons Public Domain, for // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 timeunit 10ps; timeprecision 10ps; task show; $printtimescale; endtask module from_unit; task show; $printtimescale; endtask endmodule module t; from_unit from_unit(); timeunit 100ps; initial begin show(); from_unit.show(); $printtimescale; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_vpi_time_cb.cpp0000644000542200017500000000462015101701376022377 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "verilated.h" #include "verilated_vcd_c.h" #include "verilated_vpi.h" #include "Vt_vpi_time_cb.h" #include "Vt_vpi_time_cb__Dpi.h" #include "svdpi.h" #include // These require the above. Comment prevents clang-format moving them #include "TestCheck.h" //====================================================================== int main(int argc, char** argv) { const std::unique_ptr contextp{new VerilatedContext}; uint64_t sim_time = 1100; contextp->debug(0); contextp->commandArgs(argc, argv); const std::unique_ptr topp{new VM_PREFIX{contextp.get(), // Note null name - we're flattening it out ""}}; #ifdef TEST_VERBOSE contextp->scopesDump(); #endif #if VM_TRACE contextp->traceEverOn(true); VL_PRINTF("Enabling waves...\n"); VerilatedVcdC* tfp = new VerilatedVcdC; topp->trace(tfp, 99); tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); #endif VerilatedVpi::callCbs(cbStartOfSimulation); topp->eval(); topp->clk = 0; while (vl_time_stamp64() < sim_time && !contextp->gotFinish()) { contextp->timeInc(1); topp->eval(); VerilatedVpi::callValueCbs(); VerilatedVpi::callTimedCbs(); if (contextp->time() > 20) { // Else haven't registered callbacks TEST_CHECK_EQ(VerilatedVpi::cbNextDeadline(), contextp->time() + 1); } if ((contextp->time() % 5) == 0) topp->clk = !topp->clk; // mon_do(); #if VM_TRACE if (tfp) tfp->dump(contextp->time()); #endif } VerilatedVpi::callCbs(cbEndOfSimulation); if (!contextp->gotFinish()) { vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); } topp->final(); #if VM_TRACE if (tfp) tfp->close(); #endif return errors ? 10 : 0; } verilator-5.042/test_regress/t/t_const_slicesel.v0000644000542200017500000000107615101701376022615 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Michael Lefebvre. // SPDX-License-Identifier: CC0-1.0 module t; localparam int unsigned A2 [1:0] = '{5,6}; localparam int unsigned A3 [2:0] = '{4,5,6}; // Matching sizes with slicesel are okay. localparam int unsigned B22 [1:0] = A2[1:0]; localparam int unsigned B33 [2:0] = A3[2:0]; // See issue #3186 localparam int unsigned B32_B [1:0] = A3[1:0]; localparam int unsigned B32_T [1:0] = A3[2:1]; endmodule verilator-5.042/test_regress/t/t_enum_enumvalue_struct_bad.py0000755000542200017500000000076615101701376025236 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(expect_filename=test.golden_filename, fails=True) test.passes() verilator-5.042/test_regress/t/t_trace_dumpvars_dyn.cpp0000644000542200017500000000366315101701376024016 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #if VM_TRACE_FST #include #define TRACE_FILE_NAME "simx.fst" #define TRACE_CLASS VerilatedFstC #elif VM_TRACE_VCD #include #define TRACE_FILE_NAME "simx.vcd" #define TRACE_CLASS VerilatedVcdC #elif VM_TRACE_SAIF #include #define TRACE_FILE_NAME "simx.saif" #define TRACE_CLASS VerilatedSaifC #endif #include #include VM_PREFIX_INCLUDE unsigned long long main_time = 0; double sc_time_stamp() { return (double)main_time; } const unsigned long long dt_2 = 3; int main(int argc, char** argv) { Verilated::debug(0); Verilated::traceEverOn(true); Verilated::commandArgs(argc, argv); std::unique_ptr top{new VM_PREFIX{"top"}}; std::unique_ptr tfp{new TRACE_CLASS}; #if defined(T_TRACE_DUMPVARS_DYN_VCD_0) || defined(T_TRACE_DUMPVARS_DYN_FST_0) \ || defined(T_TRACE_DUMPVARS_DYN_SAIF_0) tfp->dumpvars(0, ""); #elif defined(T_TRACE_DUMPVARS_DYN_VCD_1) || defined(T_TRACE_DUMPVARS_DYN_FST_1) \ || defined(T_TRACE_DUMPVARS_DYN_SAIF_1) tfp->dumpvars(99, "t"); // This should not match "top." tfp->dumpvars(1, "top.t.cyc"); // A signal tfp->dumpvars(1, "top.t.sub1a"); // Scope tfp->dumpvars(2, "top.t.sub1b"); // Scope #else #error "Bad test" #endif top->trace(tfp.get(), 99); tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/" TRACE_FILE_NAME); top->clk = 0; while (main_time <= 20) { top->eval(); tfp->dump((unsigned int)(main_time)); ++main_time; top->clk = !top->clk; } tfp->close(); top->final(); tfp.reset(); top.reset(); printf("*-* All Finished *-*\n"); return 0; } verilator-5.042/test_regress/t/t_class_this_super.v0000644000542200017500000000200515101701376023147 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilog_format: off `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); // verilog_format: on // Based on icarus/ivtest/ivltests/sv_class_super6.v class B; int m_x, m_y; task set_y; m_y = 2000; endtask function void check_x; `checkd(m_x, 1000); endfunction endclass class C extends B; byte m_x, m_y; task set_x; m_x = 6; this.m_y = 7; this.super.m_x = 1000; endtask function void check_y; `checkd(m_x, 6); `checkd(this.m_y, 7); `checkd(this.super.m_y, 2000); endfunction endclass module test; C c; initial begin c = new; c.set_x(); c.set_y(); c.check_x(); c.check_y(); $finish; end endmodule verilator-5.042/test_regress/t/t_structu_dataType_assignment.v0000644000542200017500000000766715101701376025414 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module for specialized type default values // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Mostafa Gamal. // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off UNPACKED */ module top(); typedef struct { // IEEE 1800-2023 5.10 int a; shortint b; } ab_struct; typedef struct { // IEEE 1800-2023 10.9.2 int x; int y; } st_struct; typedef struct { // IEEE 1800-2023 10.9.2 logic [7:0] a; bit b; bit signed [31:0] c; int s; } sa_struct; typedef struct { // IEEE 1800-2023 10.9.2 int A; struct { int B, C; } BC1, BC2; } DEF_struct; typedef struct { // IEEE 1800-2023 10.9.2 int A; struct { int B, C; struct { int D, E; struct { int F; shortint G; } FG1; } DE1; } BC1; } HIJ_struct; // struct ab ab_struct ab; ab_struct abkey[1:0]; // struct st st_struct st; int k = 1; // struct sa sa_struct sa; // struct DEF DEF_struct DEF; // struct HIJ HIJ_struct HIJ; initial begin; // struct ab ab = '{0, 0}; //constant member by position if (ab.a != 0) $stop; if (ab.b != 0) $stop; ab = '{default: 0}; //default value if (ab.a != 0) $stop; if (ab.b != 0) $stop; ab = '{int: 1, shortint: 0}; //data type and default value if (ab.a != 1) $stop; if (ab.b != 0) $stop; abkey[1:0] = '{'{a:1, b:2}, '{int:2, shortint:3}}; // member: value & data_type: value if (abkey[1].a != 1) $stop; if (abkey[1].b != 2) $stop; if (abkey[0].a != 2) $stop; if (abkey[0].b != 3) $stop; // struct st st = '{1, 2+k}; //constant member by position if (st.x != 1) $stop; if (st.y != 2+k) $stop; st = '{x:2, y:3+k}; //member: value if (st.x != 2) $stop; if (st.y != 3+k) $stop; st = '{int:2, int:3+k}; //data_type: value override if (st.x != 3+k) $stop; if (st.y != 3+k) $stop; // struct sa sa = '{default:'1}; if (sa.a != '1) $stop; if (sa.b != '1) $stop; if (sa.c != '1) $stop; if (sa.s != '1) $stop; sa = '{default:'1, int: 5}; if (sa.a != '1) $stop; if (sa.b != '1) $stop; if (sa.c != '1) $stop; if (sa.s != 5) $stop; sa = '{default:'1, int: 5, b: 0}; if (sa.a != '1) $stop; if (sa.b != 0) $stop; if (sa.c != '1) $stop; if (sa.s != 5) $stop; // struct DEF DEF = '{A:1, BC1:'{B:2, C:3}, BC2:'{B:4,C:5}}; if (DEF.A != 1) $stop; if (DEF.BC1.B != 2) $stop; if (DEF.BC1.C != 3) $stop; if (DEF.BC2.B != 4) $stop; if (DEF.BC2.C != 5) $stop; DEF = '{int:0, BC1:'{int:10}, BC2:'{default:5}}; if (DEF.A != 0) $stop; if (DEF.BC1.B != 10) $stop; if (DEF.BC1.C != 10) $stop; if (DEF.BC2.B != 5) $stop; if (DEF.BC2.C != 5) $stop; DEF = '{default:1, BC1:'{int:10}, BC2:'{default:5}}; if (DEF.A != 1) $stop; if (DEF.BC1.B != 10) $stop; if (DEF.BC1.C != 10) $stop; if (DEF.BC2.B != 5) $stop; if (DEF.BC2.C != 5) $stop; DEF = '{default:10}; if (DEF.A != 10) $stop; if (DEF.BC1.B != 10) $stop; if (DEF.BC1.C != 10) $stop; if (DEF.BC2.B != 10) $stop; if (DEF.BC2.C != 10) $stop; DEF = '{int:10}; if (DEF.A != 10) $stop; if (DEF.BC1.B != 10) $stop; if (DEF.BC1.C != 10) $stop; if (DEF.BC2.B != 10) $stop; if (DEF.BC2.C != 10) $stop; // struct HIJ HIJ = '{int:10, default: 5}; if (HIJ.A != 10) $stop; if (HIJ.BC1.B != 10) $stop; if (HIJ.BC1.C != 10) $stop; if (HIJ.BC1.DE1.D != 10) $stop; if (HIJ.BC1.DE1.E != 10) $stop; if (HIJ.BC1.DE1.FG1.F != 10) $stop; if (HIJ.BC1.DE1.FG1.G != 5) $stop; HIJ = '{shortint:10, default: 5}; if (HIJ.A != 5) $stop; if (HIJ.BC1.B != 5) $stop; if (HIJ.BC1.C != 5) $stop; if (HIJ.BC1.DE1.D != 5) $stop; if (HIJ.BC1.DE1.E != 5) $stop; if (HIJ.BC1.DE1.FG1.F != 5) $stop; if (HIJ.BC1.DE1.FG1.G != 10) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_udp_binary_top.v0000644000542200017500000000066615101701376022626 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Test that a standalone primitive can be a top level module primitive p(output id_2, input id_1); table 1 : 0; 0 : 1; endtable endprimitive module t; // Overridden by --top-module initial $stop; endmodule verilator-5.042/test_regress/t/t_string_add_bad.v0000644000542200017500000000073315101701376022527 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; string s; initial begin for (int a = 0; a < 3; ++a) begin : a_loop s += $sformatf(" a%0d", a); // <--- Error: += is not legal on strings s = s + s; // <--- Error: += is not legal on strings end $stop; end endmodule verilator-5.042/test_regress/t/t_let_stmt_bad.py0000755000542200017500000000076615101701376022440 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_typedef_param.v0000644000542200017500000000477115101701376022431 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef reg [2:0] threeansi_t; module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [2:0] in = crc[2:0]; localparam type three_t = reg [2:0]; three_t outna; three_t outa; TestNonAnsi #( .p_t (reg [2:0]) ) test (// Outputs .out (outna), /*AUTOINST*/ // Inputs .clk (clk), .in (in[2:0])); TestAnsi #( .p_t (reg [2:0])) testa (// Outputs .out (outa), /*AUTOINST*/ // Inputs .clk (clk), .in (in[2:0])); // Aggregate outputs into a single result vector wire [63:0] result = {57'h0, outna, 1'b0, outa}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h018decfea0a8828a if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module TestNonAnsi (/*AUTOARG*/ // Outputs out, // Inputs clk, in ); /*verilator hier_block*/ parameter type p_t = shortint; input clk; input p_t in; output p_t out; always @(posedge clk) begin out <= ~in; end endmodule module TestAnsi #( parameter type p_t = shortint ) ( input clk, input p_t in, output p_t out ); /*verilator hier_block*/ always @(posedge clk) begin out <= ~in; end endmodule // Local Variables: // verilog-typedef-regexp: "_t$" // End: verilator-5.042/test_regress/t/t_sys_file_null.py0000755000542200017500000000112715101701376022636 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() filename = test.obj_dir + "/zeros.log" if os.path.getsize(filename) != 20: test.error(filename + ": Wrong file size") test.passes() verilator-5.042/test_regress/t/t_tri_graph.v0000644000542200017500000000101415101701376021553 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Unsupported tristate construct error // // This is a compile only regression test of tristate handling for bug514 // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; wire [11:0] ck; assign ck[1:0] = {1'bz,{1{1'b0}}}; test i_test (.clk (ck[1:0])); endmodule module test (clk); output wire [1:0] clk; endmodule // test verilator-5.042/test_regress/t/t_stream_crc_example.py0000755000542200017500000000073415101701376023627 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_twod_noinl.py0000755000542200017500000000103715101701376024163 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_twod.v" test.compile(v_flags2=["-fno-inline"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_iface_array_topmodule_bad.v0000644000542200017500000000204515101701376025772 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Josh Redford. // SPDX-License-Identifier: CC0-1.0 interface my_if #( parameter integer DW ) (); logic valid; logic [7:0] data ; modport slave_mp ( input valid, input data ); modport master_mp ( output valid, output data ); endinterface module t ( input wire clk, my_if.slave_mp in_if [2], my_if.master_mp out_if [2] ); my_if my_i [2] (); always @(posedge clk) begin my_i[0].valid <= in_if[0].valid; my_i[0].data <= in_if[0].data; my_i[1].valid <= in_if[1].valid; my_i[1].data <= in_if[1].data; end assign out_if[0].valid = my_i[0].valid; assign out_if[0].data = my_i[0].data; assign out_if[1].valid = my_i[1].valid; assign out_if[1].data = my_i[1].data; endmodule verilator-5.042/test_regress/t/t_math_div_noexpand.py0000755000542200017500000000103315101701376023452 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_math_div.v" test.compile(verilator_flags2=['-fno-expand']) test.execute() test.passes() verilator-5.042/test_regress/t/t_mem_banks.py0000755000542200017500000000073415101701376021726 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_opt_table_display.py0000755000542200017500000000103415101701376023462 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--stats"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_var_ref_bad1.py0000755000542200017500000000076315101701376022307 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_trace_noflag_bad.v0000644000542200017500000000052115101701376023030 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; int i; initial begin i = 10; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_std_identifier_bad.py0000755000542200017500000000104115101701376023564 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.top_filename = "t/t_std_identifier.v" test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_export_packed_struct2.py0000755000542200017500000000105215101701376024302 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_hier_block_typedef_param.py0000755000542200017500000000105115101701376024764 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_typedef_param.v" test.compile(verilator_flags2=["--hierarchical"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_clk_concat2.py0000755000542200017500000000073415101701376022154 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_covergroup_with_sample_args_default.py0000755000542200017500000000070615101701376027300 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.passes() verilator-5.042/test_regress/t/t_class_extends1.v0000644000542200017500000000464315101701376022527 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Base0; class BaseInnerOnly; int inneronly; function new(); inneronly = 10; if (inneronly != 10) $stop; endfunction endclass class BaseInnerOver; int innerover; function new(); innerover = 10; if (innerover != 10) $stop; endfunction endclass int baseonly; int baseover; BaseInnerOnly inneronly = new; BaseInnerOver innerover = new; function void b_set_bo(int v); baseover = v; endfunction function int b_get_bo(); return baseover; endfunction function int get_bo(); return baseover; endfunction function void b_set_io(int v); innerover.innerover = v; endfunction function int b_get_io(); return innerover.innerover; endfunction function int get_io(); return innerover.innerover; endfunction endclass class Ext extends Base0; class BaseInnerOver; int innerover; function new(); innerover = 20; if (innerover != 20) $stop; endfunction endclass int baseover; int extonly; BaseInnerOnly inneronly = new; BaseInnerOver innerover = new; function void e_set_bo(int v); baseover = v; endfunction function int e_get_bo(); return baseover; endfunction function int get_bo(); return baseover; endfunction function void e_set_io(int v); innerover.innerover = v; endfunction function int e_get_io(); return innerover.innerover; endfunction function int get_io(); return innerover.innerover; endfunction endclass module t; initial begin Ext c; c = new; c.baseonly = 10; c.baseover = 20; c.extonly = 30; c.inneronly.inneronly = 40; c.innerover.innerover = 50; if (c.baseonly != 10) $stop; if (c.baseover != 20) $stop; if (c.extonly != 30) $stop; if (c.inneronly.inneronly != 40) $stop; if (c.innerover.innerover != 50) $stop; c.b_set_bo(100); c.e_set_bo(200); c.b_set_io(300); c.e_set_io(400); if (c.b_get_bo() != 100) $stop; if (c.e_get_bo() != 200) $stop; if (c.get_bo() != 200) $stop; if (c.b_get_io() != 300) $stop; if (c.e_get_io() != 400) $stop; if (c.get_io() != 400) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_trace_fst.v0000644000542200017500000000515615101701376021561 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // Author: Yu-Sheng Lin johnjohnlys@media.ee.ntu.edu.tw // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs state, // Inouts fst_inout, // Inputs clk ); input clk; int cyc; reg rstn; output [4:0] state; parameter real fst_gparam_real = 1.23; localparam real fst_lparam_real = 4.56; real fst_real = 1.23; integer fst_integer; bit fst_bit; logic fst_logic; int fst_int; shortint fst_shortint; longint fst_longint; byte fst_byte; time fst_time; parameter fst_parameter = 123; localparam fst_lparam = 456; supply0 fst_supply0; supply1 fst_supply1; tri0 fst_tri0; tri1 fst_tri1; tri fst_tri; triand fst_triand; trior fst_trior; //trireg fst_trireg; // Error-UNSUPPORTED wand fst_wand; wor fst_wor; wire fst_wire; uwire fst_uwire; inout fst_inout; Test test (/*AUTOINST*/ // Outputs .state (state[4:0]), // Inputs .clk (clk), .rstn (rstn)); // Test loop always @ (posedge clk) begin cyc <= cyc + 1; fst_time <= $time; if (cyc==0) begin // Setup rstn <= ~'1; end else if (cyc<10) begin rstn <= ~'1; end else if (cyc<90) begin rstn <= ~'0; end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test ( input clk, input rstn, output logic [4:0] state ); logic [4:0] state_w; logic [4:0] state_array [3]; assign state = state_array[0]; always_comb begin state_w[4] = state_array[2][0]; state_w[3] = state_array[2][4]; state_w[2] = state_array[2][3] ^ state_array[2][0]; state_w[1] = state_array[2][2]; state_w[0] = state_array[2][1]; end always_ff @(posedge clk or negedge rstn) begin if (!rstn) begin for (int i = 0; i < 3; i++) state_array[i] <= 'b1; end else begin for (int i = 0; i < 2; i++) state_array[i] <= state_array[i+1]; state_array[2] <= state_w; end end endmodule verilator-5.042/test_regress/t/t_case_write1_noexpand.py0000755000542200017500000000103615101701376024070 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_case_write1.v" test.compile(verilator_flags2=['-fno-expand']) test.execute() test.passes() verilator-5.042/test_regress/t/t_gen_defparam.py0000755000542200017500000000073415101701376022402 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_opt_dead_noassigns.py0000755000542200017500000000116215101701376023631 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--fno-dead-assigns']) test.execute() files = test.glob_some(test.obj_dir + "/" + test.vm_prefix + "_*.cpp") test.file_grep_any(files, r'keptdead') test.passes() verilator-5.042/test_regress/t/t_randsequence_recurse.out0000644000542200017500000000040415101701376024345 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_randsequence_recurse.v:21:7: Unsupported: randsequence 21 | randsequence(main) | ^~~~~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_func_wide_out_bad.py0000755000542200017500000000103515101701376023425 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_func_wide_out.v" test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_timing_dpi_unsup.py0000755000542200017500000000110215101701376023335 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.top_filename = "t/t_timing_dpi_unsup.v" test.lint(verilator_flags2=["--timing"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_randomize_srandom.py0000755000542200017500000000073415101701376023505 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_capitalization.v0000644000542200017500000000234715101701376024006 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Test different uppercase/lowercase capitalization cases class ClsMixed; int m; int M; endclass class Clsmixed; int m; int M; endclass module ModMixed; // verilator no_inline_module int m; int M; endmodule module Modmixed; // verilator no_inline_module int m; int M; endmodule module t; // verilator no_inline_module ModMixed modMixed(); Modmixed modmixed(); initial begin ClsMixed clsMixed; Clsmixed clsmixed; clsMixed = new; clsMixed.m = 1; clsMixed.M = 2; clsmixed = new; clsmixed.m = 3; clsmixed.M = 4; if (clsMixed.m != 1) $stop; if (clsMixed.M != 2) $stop; if (clsmixed.m != 3) $stop; if (clsmixed.M != 4) $stop; modMixed.m = 1; modMixed.M = 2; modmixed.m = 3; modmixed.M = 4; if (modMixed.m != 1) $stop; if (modMixed.M != 2) $stop; if (modmixed.m != 3) $stop; if (modmixed.M != 4) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_dpi_context.v0000644000542200017500000000443515101701376022126 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (); sub a (.inst(1)); sub b (.inst(2)); initial begin a.test1; b.test1; a.test2; b.test2; $write("*-* All Finished *-*\n"); $finish; end import "DPI-C" context function void dpic_final(); final dpic_final(); endmodule module sub (input integer inst); import "DPI-C" context function int dpic_line(); import "DPI-C" context function int dpic_save(int value); import "DPI-C" context function int dpic_restore(); import "DPI-C" context function int unsigned dpic_getcontext(); import "DPI-C" context function int unsigned dpic_get1(); int result; // Exports here are only to cover the export dumper of Verilated::internalsDump export "DPI-C" function dpix_void; function void dpix_void; endfunction export "DPI-C" function dpix_result; function int dpix_result; return result; endfunction task test1; // Check line numbering `ifndef verilator // Not all sims support SV2009 `__LINE__, and some that do fail the specific-line test result = dpic_line(); if (!result) $stop; `else result = dpic_line(); if (result !== `__LINE__) $stop; // result = dpic_line(); if (result !== `__LINE__) $stop; `endif // Check save-restore result = dpic_save(23+inst); if (result==0) $stop; endtask task test2; if (dpic_restore() != 23+inst) $stop; endtask function automatic int call_dpic_get1; int res = dpic_get1(); return res; endfunction int unsigned cntxt1; int unsigned cntxt2; initial begin cntxt1 = dpic_getcontext(); begin : caller_context // call from a different scope - should still get the context of the function declaration cntxt2 = dpic_getcontext(); end // svContext should be the context of the function declaration, not the context of the function call if (cntxt1 != cntxt2) $stop; if (call_dpic_get1() != 1) $stop; end endmodule verilator-5.042/test_regress/t/t_gen_intdot.v0000644000542200017500000000424215101701376021734 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; wire out; reg in; Genit g (.clk(clk), .value(in), .result(out)); always @ (posedge clk) begin //$write("[%0t] cyc==%0d %x %x\n", $time, cyc, in, out); cyc <= cyc + 1; if (cyc==0) begin // Setup in <= 1'b1; end else if (cyc==1) begin in <= 1'b0; end else if (cyc==2) begin if (out != 1'b1) $stop; end else if (cyc==3) begin if (out != 1'b0) $stop; end else if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module Generate (clk, value, result); input clk; input value; output result; reg Internal; assign result = Internal; always @(posedge clk) Internal <= value; endmodule module Checker (clk, value); input clk, value; always @(posedge clk) begin $write ("[%0t] value=%h\n", $time, value); end endmodule module Test (clk, value, result); input clk; input value; output result; Generate gen (clk, value, result); Checker chk (clk, gen.Internal); endmodule module Genit (clk, value, result); input clk; input value; output result; `ifndef ATSIM // else unsupported `ifndef NC // else unsupported `ifndef IVERILOG // else unsupported `define WITH_FOR_GENVAR `endif `endif `endif `define WITH_GENERATE `ifdef WITH_GENERATE `ifndef WITH_FOR_GENVAR genvar i; `endif generate for ( `ifdef WITH_FOR_GENVAR genvar `endif i = 0; i < 1; i = i + 1) begin : foo Test tt (clk, value, result); end endgenerate `else Test tt (clk, value, result); `endif wire Result2 = t.g.foo[0].tt.gen.Internal; // Works - Do not change! always @ (posedge clk) begin $write("[%0t] Result2 = %x\n", $time, Result2); end endmodule verilator-5.042/test_regress/t/t_sampled_expr.v0000644000542200017500000000220415101701376022261 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [3:0] a, b; Test1 t1(clk, a, b); Test2 t2(clk, a, b); Test3 t3(clk); initial begin a = 0; b = 0; end always @(posedge clk) begin a <= a + 1; b = b + 1; $display("a = %0d, b = %0d, %0d == %0d", a, b, $sampled(a), $sampled(b)); if (b >= 10) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test1( clk, a, b ); input clk; input [3:0] a, b; assert property (@(posedge clk) $sampled(a == b) == ($sampled(a) == $sampled(b))); endmodule module Test2( clk, a, b ); input clk; input [3:0] a, b; assert property (@(posedge clk) eq(a, b)); function [0:0] eq([3:0] x, y); return x == y; endfunction endmodule module Test3( clk ); input clk; assert property (@(posedge clk) $sampled($time) == $time); endmodule verilator-5.042/test_regress/t/t_increment_bad.py0000755000542200017500000000076315101701376022566 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_math_tri.v0000644000542200017500000000110415101701376021403 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg [3:0] a; reg [99:0] x; initial begin a = 4'b010x; if (a[3:2] !== 2'b01) $stop; if (|a !== 1'b1) $stop; if (&a !== 1'b0) $stop; x = 100'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_opt_const_red.py0000755000542200017500000000116115101701376022627 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["-Wno-UNOPTTHREADS", "--stats"]) test.execute() if test.vlt: test.file_grep(test.stats, r'Optimizations, Const bit op reduction\s+(\d+)', 158) test.passes() verilator-5.042/test_regress/t/t_preproc_inc_recurse_bad.out0000644000542200017500000000050115101701376024777 0ustar mahmoudyfreeshell%Error: t/t_preproc_inc_recurse_bad.v:7:10: Recursive inclusion of file: t/t_preproc_inc_recurse_bad.v 7 | `include "t_preproc_inc_recurse_bad.v" | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_param_type_bit.py0000755000542200017500000000071415101701376022767 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.passes() verilator-5.042/test_regress/t/t_func_named.py0000755000542200017500000000073415101701376022071 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_time_vpi_1ns1ns.py0000755000542200017500000000147215101701376023011 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.pli_filename = "t/t_time_vpi_c.cpp" test.top_filename = "t/t_time_vpi.v" test.main_time_multiplier = 1e-9 / 1e-9 test.compile( v_flags2=['+define+time_scale_units=1ns +define+time_scale_prec=1ns', test.pli_filename], verilator_flags2=['--vpi --trace-vcd']) test.execute(expect_filename=test.golden_filename) test.file_grep(test.trace_filename, r'timescale +1ns') test.passes() verilator-5.042/test_regress/t/t_timing_fork_comb.v0000644000542200017500000000241715101701376023114 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; bit clk; assign #5 clk = ~clk; int a = 0; always @(posedge clk) begin a <= a + 1; `ifdef TEST_VERBOSE $display("a=%0d, b=%0d, c=%0d, d=%0d, e=%0d, f=%0d, v=%b", a, b, c, d, e, f, v); `endif end int b = 0, c = 0, d = 0, e = 0, f = 0; always @a begin b = a << 1; fork #10 d = b + c; e = c + d; #5 f = d + e; join_none c = a + b; end bit [5:0] v; always @a begin v[0] = a[0]; fork begin v[1] = a[1]; #5 v[2] = a[2]; end #10 v[3] = a[3]; join_none v[4] = a[4]; end initial #100 begin `ifdef TEST_VERBOSE $display("a=%0d, b=%0d, c=%0d, d=%0d, e=%0d, f=%0d, v=%b", a, b, c, d, e, f, v); `endif if (a != 10) $stop; if (b != 20) $stop; if (c != 30) $stop; if (d != 45) $stop; if (e != 75) $stop; if (f != 107) $stop; if (v != 'b001010) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_mod_interface_array0_noinl.py0000755000542200017500000000104515101701376025242 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_mod_interface_array0.v" test.compile(v_flags2=["-fno-inline"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_dpi_binary.py0000755000542200017500000000110215101701376022100 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.pli_filename = "t/t_dpi_binary_c.cpp" test.compile(v_flags2=[test.pli_filename], verilator_flags2=['--binary']) test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_scstruct.v0000644000542200017500000000100115101701376022620 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilator lint_off UNUSED // verilator lint_off UNDRIVEN //bug858 typedef struct packed { logic m_1; logic m_2; } struct_t; typedef struct packed { logic [94:0] m_1; logic m_2; } struct96_t; module t ( input struct_t test_input, input struct96_t t96 ); endmodule verilator-5.042/test_regress/t/t_trace_scope_no_inline.out0000644000542200017500000000336615101701376024473 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $scope module t $end $scope module mid_a $end $upscope $end $scope module mid_b $end $var wire 1 ' clk $end $var wire 32 # cnt [31:0] $end $scope module sub_a $end $var wire 1 ' clk $end $var wire 32 $ cnt [31:0] $end $upscope $end $scope module sub_b $end $var wire 1 ' clk $end $var wire 32 % cnt [31:0] $end $upscope $end $scope module sub_c $end $var wire 1 ' clk $end $var wire 32 & cnt [31:0] $end $upscope $end $upscope $end $scope module mid_c $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 b00000000000000000000000000000000 # b00000000000000000000000000000000 $ b00000000000000000000000000000000 % b00000000000000000000000000000000 & 0' #10 b00000000000000000000000000000001 # b00000000000000000000000000000010 $ b00000000000000000000000000000010 % b00000000000000000000000000000010 & 1' #15 0' #20 b00000000000000000000000000000010 # b00000000000000000000000000000100 $ b00000000000000000000000000000100 % b00000000000000000000000000000100 & 1' #25 0' #30 b00000000000000000000000000000011 # b00000000000000000000000000000110 $ b00000000000000000000000000000110 % b00000000000000000000000000000110 & 1' #35 0' #40 b00000000000000000000000000000100 # b00000000000000000000000000001000 $ b00000000000000000000000000001000 % b00000000000000000000000000001000 & 1' #45 0' #50 b00000000000000000000000000000101 # b00000000000000000000000000001010 $ b00000000000000000000000000001010 % b00000000000000000000000000001010 & 1' #55 0' #60 b00000000000000000000000000000110 # b00000000000000000000000000001100 $ b00000000000000000000000000001100 % b00000000000000000000000000001100 & 1' verilator-5.042/test_regress/t/t_interface_array_nocolon.py0000755000542200017500000000073415101701376024657 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_vpi_module.cpp0000644000542200017500000001317715101701376022271 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #ifdef IS_VPI #include "vpi_user.h" #include #else #include "verilated.h" #include "verilated_vcd_c.h" #include "verilated_vpi.h" #include "Vt_vpi_module.h" #include "Vt_vpi_module__Dpi.h" #include "svdpi.h" #endif #include #include #include extern "C" { #include } // These require the above. Comment prevents clang-format moving them #include "TestSimulator.h" #include "TestVpi.h" #define DEBUG \ if (0) printf void modDump(const TestVpiHandle& it, int n) { while (TestVpiHandle hndl = vpi_scan(it)) { const char* nm = vpi_get_str(vpiName, hndl); for (int i = 0; i < n; i++) printf(" "); printf("%s\n", nm); TestVpiHandle subIt = vpi_iterate(vpiModule, hndl); if (subIt) modDump(subIt, n + 1); } } extern "C" { int mon_check() { #ifdef TEST_VERBOSE printf("-mon_check()\n"); #endif TestVpiHandle it = vpi_iterate(vpiModule, NULL); CHECK_RESULT_NZ(it); // Uncomment to see what other simulators return // modDump(it, 0); // return 1; TestVpiHandle topmod; // both somepackage and t exist at the top level while ((topmod = vpi_scan(it))) { if (vpi_get(vpiType, topmod) == vpiModule) break; } CHECK_RESULT_NZ(topmod); const char* t_name = vpi_get_str(vpiName, topmod); CHECK_RESULT_NZ(t_name); // Icarus reports the top most module as "top" if (std::strcmp(t_name, "top") == 0) { it = vpi_iterate(vpiModule, topmod); CHECK_RESULT_NZ(it); CHECK_RESULT(vpi_get(vpiType, it), vpiModule); topmod = vpi_scan(it); t_name = vpi_get_str(vpiName, topmod); CHECK_RESULT_NZ(t_name); } CHECK_RESULT_CSTR(t_name, "t"); TestVpiHandle topmod_done_should_be_0 = (vpi_scan(it)); it.freed(); // IEEE 37.2.2 vpi_scan at end does a vpi_release_handle CHECK_RESULT_Z(topmod_done_should_be_0); TestVpiHandle it2 = vpi_iterate(vpiModule, topmod); CHECK_RESULT_NZ(it2); TestVpiHandle mod2 = vpi_scan(it2); CHECK_RESULT_NZ(mod2); const char* mod_a_name = vpi_get_str(vpiName, mod2); CHECK_RESULT_CSTR(mod_a_name, "\\mod.a "); TestVpiHandle it3 = vpi_iterate(vpiModule, mod2); CHECK_RESULT_NZ(it3); TestVpiHandle mod3 = vpi_scan(it3); CHECK_RESULT_NZ(mod3); const char* mod_c_name = vpi_get_str(vpiName, mod3); if (std::strcmp(mod_c_name, "\\mod_b$ ") == 0) { // Full visibility in other simulators, skip mod_b TestVpiHandle mod4 = vpi_scan(it3); CHECK_RESULT_NZ(mod4); mod_c_name = vpi_get_str(vpiName, mod4); } CHECK_RESULT_CSTR(mod_c_name, "\\mod\\c$ "); return 0; // Ok } } //====================================================================== #ifdef IS_VPI static int mon_check_vpi() { TestVpiHandle href = vpi_handle(vpiSysTfCall, 0); s_vpi_value vpi_value; vpi_value.format = vpiIntVal; vpi_value.value.integer = mon_check(); vpi_put_value(href, &vpi_value, NULL, vpiNoDelay); return 0; } static s_vpi_systf_data vpi_systf_data[] = {{vpiSysFunc, vpiIntFunc, (PLI_BYTE8*)"$mon_check", (PLI_INT32(*)(PLI_BYTE8*))mon_check_vpi, 0, 0, 0}, 0}; // cver entry void vpi_compat_bootstrap(void) { p_vpi_systf_data systf_data_p; systf_data_p = &(vpi_systf_data[0]); while (systf_data_p->type != 0) vpi_register_systf(systf_data_p++); } // icarus entry void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0}; #else int main(int argc, char** argv) { const std::unique_ptr contextp{new VerilatedContext}; uint64_t sim_time = 1100; contextp->debug(0); contextp->commandArgs(argc, argv); // We're going to be checking for these errors so don't crash out contextp->fatalOnVpiError(0); { // Construct and destroy const std::unique_ptr topp{ new VM_PREFIX{contextp.get(), // Note null name - we're flattening it out ""}}; } // Test second construction const std::unique_ptr topp{new VM_PREFIX{contextp.get(), // Note null name - we're flattening it out ""}}; #ifdef VERILATOR #ifdef TEST_VERBOSE contextp->scopesDump(); #endif #endif #if VM_TRACE contextp->traceEverOn(true); VL_PRINTF("Enabling waves...\n"); VerilatedVcdC* tfp = new VerilatedVcdC; topp->trace(tfp, 99); tfp->open(STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); #endif topp->eval(); topp->clk = 0; contextp->timeInc(10); while (contextp->time() < sim_time && !contextp->gotFinish()) { contextp->timeInc(1); topp->eval(); VerilatedVpi::callValueCbs(); topp->clk = !topp->clk; // mon_do(); #if VM_TRACE if (tfp) tfp->dump(contextp->time()); #endif } if (!contextp->gotFinish()) { vl_fatal(FILENM, __LINE__, "main", "%Error: Timeout; never got a $finish"); } topp->final(); #if VM_TRACE if (tfp) tfp->close(); #endif return 0; } #endif verilator-5.042/test_regress/t/t_fork_bbox.py0000755000542200017500000000077415101701376021751 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=['--lint-only --no-timing --bbox-unsup']) test.passes() verilator-5.042/test_regress/t/t_alias_force.v0000644000542200017500000000131615101701376022050 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ // Inputs clk ); input clk; wire [15:0] a, b; integer cyc = 0; alias a = b; always @(posedge clk) begin cyc <= cyc + 1; if (cyc == 1) begin force a = 16'h1234; if (a != 16'h1234 || a != b) $stop; release a; end else if (cyc == 2) begin force b = 16'h5678; if (a != 16'h5678 || a != b) $stop; release b; end else if (cyc == 3) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_gantt_io_noproc.py0000755000542200017500000000132115101701376023147 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') test.run(cmd=[ "cd " + test.obj_dir + " && " + os.environ["VERILATOR_ROOT"] + "/bin/verilator_gantt" + " --no-vcd", test.t_dir + "/" + test.name + ".dat > gantt.log" ], check_finished=False) test.files_identical(test.obj_dir + "/gantt.log", test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_var_overcmp.py0000755000542200017500000000073415101701376022315 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_preproc_ifdef.py0000755000542200017500000000073415101701376022601 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_iface.out0000644000542200017500000000326515101701376022375 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $var wire 1 ( clk $end $scope module t $end $var wire 1 ( clk $end $var wire 32 # cyc [31:0] $end $scope module c5_data $end $var wire 1 $ valid $end $var wire 4 % value [3:0] $end $var wire 1 ) reset $end $upscope $end $scope module c6_data $end $var wire 1 & valid $end $var wire 4 ' value [3:0] $end $var wire 1 * reset $end $upscope $end $scope module cif2 $end $upscope $end $scope module cif3 $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 b00000000000000000000000000000001 # 0$ b0000 % 0& b0000 ' 0( 0) 0* #10 b00000000000000000000000000000010 # 1( #15 0( #20 b00000000000000000000000000000011 # b1111 % 1& b1010 ' 1( #25 0( #30 b00000000000000000000000000000100 # 1( #35 0( #40 b00000000000000000000000000000101 # 1( #45 0( #50 b00000000000000000000000000000110 # 1( #55 0( #60 b00000000000000000000000000000111 # 1( #65 0( #70 b00000000000000000000000000001000 # 1( #75 0( #80 b00000000000000000000000000001001 # 1( #85 0( #90 b00000000000000000000000000001010 # 1( #95 0( #100 b00000000000000000000000000001011 # 1( #105 0( #110 b00000000000000000000000000001100 # 1( #115 0( #120 b00000000000000000000000000001101 # 1( #125 0( #130 b00000000000000000000000000001110 # 1( #135 0( #140 b00000000000000000000000000001111 # 1( #145 0( #150 b00000000000000000000000000010000 # 1( #155 0( #160 b00000000000000000000000000010001 # 1( #165 0( #170 b00000000000000000000000000010010 # 1( #175 0( #180 b00000000000000000000000000010011 # 1( #185 0( #190 b00000000000000000000000000010100 # 1( #195 0( #200 b00000000000000000000000000010101 # 1( verilator-5.042/test_regress/t/t_cover_toggle_min.info.out0000644000542200017500000000041315101701376024414 0ustar mahmoudyfreeshellTN:verilator_coverage SF:t/t_cover_toggle_min.v DA:10,1 BRDA:10,0,0,1 BRDA:10,0,1,0 BRDA:10,0,2,0 BRDA:10,0,3,0 DA:11,1 BRDA:11,0,0,0 BRDA:11,0,1,0 BRDA:11,0,2,1 BRDA:11,0,3,0 DA:12,1 BRDA:12,0,0,1 BRDA:12,0,1,1 BRDA:12,0,2,1 BRDA:12,0,3,0 BRF:12 BRH:0 end_of_record verilator-5.042/test_regress/t/t_dpi_unpack_bad.py0000755000542200017500000000076615101701376022722 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_string_size.py0000755000542200017500000000100015101701376022315 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface_array3.v0000644000542200017500000000212015101701376023014 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface my_ifc (); logic sig; modport master ( output sig ); modport slave ( input sig ); endinterface package my_pkg; typedef virtual my_ifc my_vif; function void my_func; input my_vif in_vif; begin in_vif.sig = 1'b1; end endfunction endpackage module dut (input logic clk, my_ifc.slave sif[2]); generate genvar i; for (i=0; i<2; i++) begin always_ff @( posedge clk ) begin if (sif[i].sig == 1'b1) $display("Hello World %0d", i); end end endgenerate endmodule module t; import my_pkg::*; logic clk; my_ifc sif[2] (); dut DUT (.*); initial begin clk = 0; forever #(5) clk = ~clk; end initial begin repeat (4) @(posedge clk); my_func(sif[0]); my_func(sif[1]); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_xml_flat_pub_mod.v0000644000542200017500000000060715101701376023116 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module foo(input logic i_clk); /* verilator public_module */ endmodule // --flatten forces inlining of public module foo. module top(input logic i_clk); foo f(.*); endmodule verilator-5.042/test_regress/t/t_enum_func.py0000755000542200017500000000073415101701376021751 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_preproc_ifexpr.out0000644000542200017500000000065415101701376023176 0ustar mahmoudyfreeshell`begin_keywords "1800-2023" "ok ( ONE )" "ok ( ! ONE )" "ok ( ! ZERO )" "ok ( ZERO || ZERO || ONE )" "ok ( ONE && ONE && ONE )" "ok ( ZERO && ZERO || ONE )" "ok ( ZERO -> ZERO)" "ok ( ZERO -> ONE)" "ok ( ZERO -> ONE)" "ok ( ZERO -> ONE)" "ok ( ONE -> ZERO)" "ok ( ONE -> ONE)" "ok ( ZERO <-> ZERO)" "ok ( ZERO <-> ONE)" "ok ( ONE <-> ZERO)" "ok ( ONE <-> ONE)" "ok " Line: 117 verilator-5.042/test_regress/t/t_gate_loop.v0000644000542200017500000000046415101701376021555 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 module t; wire a; wire b; wire c; assign a = b; assign b = c; assign c = a; endmodule verilator-5.042/test_regress/t/t_bigmem_bad.out0000644000542200017500000000155415101701376022215 0ustar mahmoudyfreeshell%Error: t/t_bigmem_bad.v:14:19: Width of bit extract must be positive (IEEE 1800-2023 11.5.1) : ... note: In instance 't_bigmem' 14 | if (wen) mem[addr] <= data; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Warning-WIDTHTRUNC: t/t_bigmem_bad.v:14:26: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS's VARREF 'data' generates 256 bits. : ... note: In instance 't_bigmem' 14 | if (wen) mem[addr] <= data; | ^~ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_randomize_inline_var_ctl_unsup_2.out0000644000542200017500000000123615101701376026657 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_randomize_inline_var_ctl_unsup_2.v:17:29: Unsupported: Inline random variable control with 'randomize()' called on complex expressions 17 | initial void'(Foo::get().randomize(x)); | ^~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: t/t_randomize_inline_var_ctl_unsup_2.v:17:39: Can't find definition of variable: 'x' 17 | initial void'(Foo::get().randomize(x)); | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_enum_name_sformatf.v0000644000542200017500000000143415101701376023447 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Demonstrate struct literal param assignment problem // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module sub #(parameter int param_a, parameter bit [1:0] enum_param = '0) (); typedef enum logic [1:0] { FOO = enum_param, BAR, BAZ } enum_t; enum_t the_enum = enum_t'(1); initial $display("%s", the_enum.name()); endmodule module t (/*AUTOARG*/ // Inputs clk ); input clk; // finish report always @ (posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end sub #(.param_a(1)) the_sub1(); sub #(.param_a(2)) the_sub2(); sub #(.param_a(2), .enum_param(2'd1)) the_sub3(); endmodule verilator-5.042/test_regress/t/t_mem_first.py0000755000542200017500000000073415101701376021757 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_super_new3.py0000755000542200017500000000073415101701376023251 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_param_override_local_bad.v0000644000542200017500000000120115101701376025736 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class Cls1; parameter type T = int; endclass class Cls2; localparam int P = 0; endclass interface class Icls1; localparam LP1 = 1; endclass interface class Icls2; parameter LP1 = 1; endclass class Cls3 implements Icls1#(2), Icls2#(0); endclass module t; initial begin automatic Cls1#(bit) cls1 = new; automatic Cls2#(1) cls2 = new; automatic Cls3 cls3 = new; $stop; end endmodule verilator-5.042/test_regress/t/t_stream3.py0000755000542200017500000000073415101701376021350 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_stream2.v0000644000542200017500000000445315101701376021163 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [67:0] left; // From test of Test.v wire [67:0] right; // From test of Test.v // End of automatics wire [6:0] amt = crc[6:0]; wire [67:0] in = {crc[3:0], crc[63:0]}; Test test (/*AUTOINST*/ // Outputs .left (left[67:0]), .right (right[67:0]), // Inputs .amt (amt[6:0]), .in (in[67:0])); wire [63:0] result = (left[63:0] ^ {60'h0, left[67:64]} ^ right[63:0] ^ {60'h0, right[67:64]}); // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x amt=%x left=%x right=%x\n", $time, cyc, crc, result, amt, left, right); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h0da01049b480c38a if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs left, right, // Inputs amt, in ); input [6:0] amt; input [67:0] in; // amt must be constant output wire [67:0] left; output wire [67:0] right; assign right = { << 33 {in}}; assign left = { >> 33 {in}}; endmodule verilator-5.042/test_regress/t/t_inst_pin_realnreal.v0000644000542200017500000000276515101701376023462 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by Peter Monsson. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; wire gain = 1'b0; real in; always_comb in = (cyc-4) * 1.0; wire cmp; adc_netlist netlist(.clk, .in, .gain, .cmp); always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; $display("cyc=%0d cmp=%d", cyc, cmp); if (cyc == 3) begin if (cmp != 0) $stop; end else if (cyc == 4) begin if (cmp != 1) $stop; end else if (cyc == 5) begin if (cmp != 0) $stop; end else if (cyc == 10) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module adc_netlist(clk, in, gain, cmp); input clk; input real in; input gain; output cmp; wire pga_out; //TODO: convert to real or support real pga_model pga0(.in, .gain, .out(pga_out)); comparator_model cmp0(.clk, .in(pga_out), .cmp); endmodule module pga_model(in, gain, out); input real in; input gain; output real out; always_comb begin out = in * 3.0; end endmodule module comparator_model(clk, in, cmp); input clk; input real in; output logic cmp; always_ff @(posedge clk) begin cmp <= in > 0.0; end endmodule verilator-5.042/test_regress/t/t_order.py0000755000542200017500000000107115101701376021100 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.main_time_multiplier = 1e-8 / 1e-9 test.compile(verilator_flags2=["--timescale 10ns/1ns --no-timing"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_stream_string_array.v0000644000542200017500000000116315101701376023660 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; string qs[$]; string as[]; string s; initial begin s = {>>{qs}}; if (s != "") $stop; s = {>>{as}}; if (s != "") $stop; qs = '{"ab", "c", ""}; s = {>>{qs}}; if (s != "abc") $stop; as = new[3]; as[0] = "abcd"; as[2] = "ef"; s = {>>{as}}; if (s != "abcdef") $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_final.v0000644000542200017500000000121515101701376020670 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Charlie Brej. // SPDX-License-Identifier: CC0-1.0 module submodule (); // This bug only appears when not inlining // verilator no_inline_module initial begin $write("d"); end final begin $write("d"); end final ; // Empty test endmodule module t (); generate for (genvar i = 0; i < 100; i = i + 1) begin : module_set submodule u_submodule(); end endgenerate initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_var_in_assign_pedantic.py0000755000542200017500000000130315101701376024454 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_var_in_assign_bad.v" # Although this is mostly a lint test, do 'compile' to make sure we do not # generate thrash code in the presence of a warning that is not fatal test.compile(verilator_flags2=['-Wpedantic -Wno-fatal --flatten -fno-gate']) test.passes() verilator-5.042/test_regress/t/t_struct_negate.v0000644000542200017500000000072315101701376022451 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( input logic signed [64:0] i_x, output logic signed [64:0] o_y ); struct {logic signed [64:0] m_x;} s; assign s.m_x = i_x; assign o_y = -s.m_x; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_cover_line.vlt0000644000542200017500000000057415101701376022273 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. // SPDX-License-Identifier: CC0-1.0 `verilator_config coverage_block_off -file "t/t_cover_line.v" -lines 145 coverage_block_off -file "t/t_cover_line.v" -lines 179 coverage_block_off -module "beta" -block "block" verilator-5.042/test_regress/t/t_constraint_struct_complex.v0000755000542200017500000004154515101701376025133 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by PlanV GmbH. // SPDX-License-Identifier: CC0-1.0 class ArrayStruct; /* verilator lint_off SIDEEFFECT */ // Struct with an unpacked array typedef int arr_3_t[3]; typedef int arr_4_t[4]; typedef struct { rand arr_3_t arr_3; arr_4_t arr_4; rand int arr[3]; } unpacked_struct_t; // Struct with a dynamic array typedef struct { rand int arr[]; } dynamic_struct_t; // Struct with a queue typedef struct { rand int arr[$]; } queue_struct_t; // Struct with an associative array (string as index) typedef struct { rand int arr[string]; } associative_struct_t; // Struct with a multi-dimensional array typedef struct { rand int arr[2][3]; } multi_dim_struct_t; // Struct with a mix of dynamic and unpacked arrays typedef struct { rand int mix_arr[3][]; } mixed_struct_t; rand unpacked_struct_t s1; rand dynamic_struct_t s2; rand queue_struct_t s3; rand associative_struct_t s4; rand multi_dim_struct_t s5; rand mixed_struct_t s6; constraint c_unpacked { foreach (s1.arr[i]) s1.arr[i] inside {1, 2, 3, 4}; foreach (s1.arr_3[i]) s1.arr_3[i] inside {11, 22, 33, 44, 55}; } constraint c_dynamic { foreach (s2.arr[i]) s2.arr[i] inside {[10:20]}; } constraint c_queue { foreach (s3.arr[i]) s3.arr[i] inside {[100:200]}; } constraint c_assoc { s4.arr["one"] inside {[10:50]}; s4.arr["two"] inside {[51:100]}; s4.arr["three"] inside {[101:150]}; } constraint c_multi_dim { foreach (s5.arr[i, j]) s5.arr[i][j] inside {[0:9]}; } constraint c_mix { foreach (s6.mix_arr[i, j]) s6.mix_arr[i][j] inside {[50:100]}; } function new(); s1.arr = '{1, 2, 3}; s1.arr_3 = '{1, 2, 3}; s1.arr_4 = '{0, 2, 3, 4}; s2.arr = new[3]; foreach(s2.arr[i]) begin s2.arr[i] = 'h0 + i; end s3.arr.push_back(100); s3.arr.push_back(200); s3.arr.push_back(300); s4.arr["one"] = 1000; s4.arr["two"] = 2000; s4.arr["three"] = 3000; s5.arr = '{ '{default:0}, '{default:0} }; foreach (s6.mix_arr[i]) begin s6.mix_arr[i] = new[i + 1]; end endfunction function void print(); foreach (s1.arr[i]) $display("s1.arr[%0d] = %0d", i, s1.arr[i]); foreach (s1.arr_3[i]) $display("s1.arr_3[%0d] = %0d", i, s1.arr_3[i]); foreach (s1.arr_4[i]) $display("s1.arr_4[%0d] = %0d", i, s1.arr_4[i]); foreach (s2.arr[i]) $display("s2.arr[%0d] = %0d", i, s2.arr[i]); foreach (s3.arr[i]) $display("s3.arr[%0d] = %0d", i, s3.arr[i]); foreach (s4.arr[i]) $display("s4.arr[\"%s\"] = %0d", i, s4.arr[i]); foreach (s5.arr[i, j]) $display("s5.arr[%0d][%0d] = %0d", i, j, s5.arr[i][j]); foreach (s6.mix_arr[i, j]) $display("s6.mix_arr[%0d][%0d] = %0d", i, j, s6.mix_arr[i][j]); endfunction // Self-test function to verify constraints function void self_test(); foreach (s1.arr[i]) if (!(s1.arr[i] inside {1, 2, 3, 4})) $stop; foreach (s1.arr_3[i]) if (!(s1.arr_3[i] inside {11, 22, 33, 44, 55})) $stop; // Note: s1.arr_4[0] is not rand if ((s1.arr_4[0] != 0) || (s1.arr_4[1] != 2) || (s1.arr_4[2] != 3) || (s1.arr_4[3] != 4)) $stop; foreach (s2.arr[i]) if (!(s2.arr[i] inside {[10:20]})) $stop; foreach (s3.arr[i]) if (!(s3.arr[i] inside {[100:200]})) $stop; if (!(s4.arr["one"] inside {[10:50]})) $stop; if (!(s4.arr["two"] inside {[51:100]})) $stop; if (!(s4.arr["three"] inside {[101:150]})) $stop; foreach (s5.arr[i, j]) if (!(s5.arr[i][j] inside {[0:9]})) $stop; foreach (s6.mix_arr[i]) if (s6.mix_arr[i].size() == 0) $stop; foreach (s6.mix_arr[i, j]) if (!(s6.mix_arr[i][j] inside {[50:100]})) $stop; endfunction /* verilator lint_off SIDEEFFECT */ endclass class StructArray; /* verilator lint_off WIDTHTRUNC */ typedef struct { rand int arr[3]; // static unpacked array rand int a; rand bit [3:0] b; bit c; } struct_t; rand struct_t s_arr[2]; rand struct_t s_2d_arr[2][3]; rand struct_t s_dyn_arr[]; rand struct_t s_que_arr[$]; rand struct_t s_assoc_arr[string]; rand struct_t s_assoc_arr_2[bit[5:0]]; constraint c_arr { foreach (s_arr[i]) foreach (s_arr[i].arr[j]) s_arr[i].arr[j] inside {[0:9]}; foreach (s_2d_arr[i, j]) foreach (s_2d_arr[i][j].arr[k]) s_2d_arr[i][j].arr[k] inside {[9:19]}; foreach (s_dyn_arr[i]) foreach (s_dyn_arr[i].arr[j]) s_dyn_arr[i].arr[j] inside {[19:29]}; foreach (s_que_arr[i]) foreach (s_que_arr[i].arr[j]) s_que_arr[i].arr[j] inside {[29:39]}; foreach (s_assoc_arr[i]) foreach (s_assoc_arr[i].arr[j]) s_assoc_arr[i].arr[j] inside {[39:49]}; foreach (s_assoc_arr_2[i]) foreach (s_assoc_arr_2[i].arr[j]) s_assoc_arr_2[i].arr[j] inside {[49:59]}; } constraint c_others { foreach (s_arr[i]) s_arr[i].a inside {[40:50]}; foreach (s_arr[i]) s_arr[i].b inside {[0:7]}; foreach (s_2d_arr[i, j]) s_2d_arr[i][j].a inside {[50:60]}; foreach (s_dyn_arr[i]) s_dyn_arr[i].a inside {[60:70]}; foreach (s_que_arr[i]) s_que_arr[i].a inside {[70:80]}; foreach (s_assoc_arr[i]) s_assoc_arr[i].a inside {[80:90]}; foreach (s_assoc_arr_2[i]) s_assoc_arr_2[i].a inside {[90:100]}; } function new(); foreach (s_arr[i]) begin foreach (s_arr[i].arr[j]) s_arr[i].arr[j] = j; s_arr[i].a = 40 + i; s_arr[i].b = i; s_arr[i].c = 0; end foreach (s_2d_arr[i, j]) begin foreach (s_2d_arr[i][j].arr[k]) s_2d_arr[i][j].arr[k] = k + 10; s_2d_arr[i][j].a = 50 + i + j; s_2d_arr[i][j].b = i + j; s_2d_arr[i][j].c = 0; end foreach (s_dyn_arr[i]) begin s_dyn_arr = new[3]; foreach (s_dyn_arr[i].arr[j]) s_dyn_arr[i].arr[j] = j + 20; s_dyn_arr[i].a = 60 + i; s_dyn_arr[i].b = i; s_dyn_arr[i].c = 0; end for (int i = 0; i < 3; i++) begin s_que_arr.push_back('{arr: '{30, 31, 32}, a: 70 + i, b: i, c: 0}); end // Associative array with string index foreach (s_assoc_arr["x"].arr[j]) s_assoc_arr["x"].arr[j] = j + 40; foreach (s_assoc_arr["y"].arr[j]) s_assoc_arr["y"].arr[j] = j + 50; foreach (s_assoc_arr["long_string_index"].arr[j]) s_assoc_arr["long_string_index"].arr[j] = j + 60; s_assoc_arr["x"].a = 80; s_assoc_arr["x"].b = 0; s_assoc_arr["x"].c = 0; s_assoc_arr["y"].a = 90; s_assoc_arr["y"].b = 1; s_assoc_arr["y"].c = 0; s_assoc_arr["long_string_index"].a = 100; s_assoc_arr["long_string_index"].b = 2; s_assoc_arr["long_string_index"].c = 0; foreach (s_assoc_arr_2[6'd30].arr[j]) s_assoc_arr_2[6'd30].arr[j] = j + 70; foreach (s_assoc_arr_2[6'd7].arr[j]) s_assoc_arr_2[6'd7].arr[j] = j + 80; s_assoc_arr_2[6'd30].a = 90; s_assoc_arr_2[6'd30].b = 0; s_assoc_arr_2[6'd30].c = 0; s_assoc_arr_2[6'd7].a = 100; s_assoc_arr_2[6'd7].b = 1; s_assoc_arr_2[6'd7].c = 0; endfunction function void print(); foreach (s_arr[i]) begin foreach (s_arr[i].arr[j]) $display("s_arr[%0d].arr[%0d] = %0d", i, j, s_arr[i].arr[j]); $display("s_arr[%0d].a = %0d", i, s_arr[i].a); $display("s_arr[%0d].b = %0d", i, s_arr[i].b); $display("s_arr[%0d].c = %0d", i, s_arr[i].c); end foreach (s_2d_arr[i, j]) begin foreach (s_2d_arr[i][j].arr[k]) $display("s_2d_arr[%0d][%0d].arr[%0d] = %0d", i, j, k, s_2d_arr[i][j].arr[k]); $display("s_2d_arr[%0d][%0d].a = %0d", i, j, s_2d_arr[i][j].a); $display("s_2d_arr[%0d][%0d].b = %0d", i, j, s_2d_arr[i][j].b); $display("s_2d_arr[%0d][%0d].c = %0d", i, j, s_2d_arr[i][j].c); end foreach (s_dyn_arr[i]) begin foreach (s_dyn_arr[i].arr[j]) $display("s_dyn_arr[%0d].arr[%0d] = %0d", i, j, s_dyn_arr[i].arr[j]); $display("s_dyn_arr[%0d].a = %0d", i, s_dyn_arr[i].a); $display("s_dyn_arr[%0d].b = %0d", i, s_dyn_arr[i].b); $display("s_dyn_arr[%0d].c = %0d", i, s_dyn_arr[i].c); end foreach (s_que_arr[i]) begin foreach (s_que_arr[i].arr[j]) $display("s_que_arr[%0d].arr[%0d] = %0d", i, j, s_que_arr[i].arr[j]); $display("s_que_arr[%0d].a = %0d", i, s_que_arr[i].a); $display("s_que_arr[%0d].b = %0d", i, s_que_arr[i].b); $display("s_que_arr[%0d].c = %0d", i, s_que_arr[i].c); end foreach (s_assoc_arr["x"].arr[j]) $display("s_assoc_arr[x].arr[%0d] = %0d", j, s_assoc_arr["x"].arr[j]); $display("s_assoc_arr[x].a = %0d", s_assoc_arr["x"].a); $display("s_assoc_arr[x].b = %0d", s_assoc_arr["x"].b); $display("s_assoc_arr[x].c = %0d", s_assoc_arr["x"].c); foreach (s_assoc_arr["y"].arr[j]) $display("s_assoc_arr[y].arr[%0d] = %0d", j, s_assoc_arr["y"].arr[j]); $display("s_assoc_arr[y].a = %0d", s_assoc_arr["y"].a); $display("s_assoc_arr[y].b = %0d", s_assoc_arr["y"].b); $display("s_assoc_arr[y].c = %0d", s_assoc_arr["y"].c); foreach (s_assoc_arr["long_string_index"].arr[j]) $display("s_assoc_arr[long_string_index].arr[%0d] = %0d", j, s_assoc_arr["long_string_index"].arr[j]); $display("s_assoc_arr[long_string_index].a = %0d", s_assoc_arr["long_string_index"].a); $display("s_assoc_arr[long_string_index].b = %0d", s_assoc_arr["long_string_index"].b); $display("s_assoc_arr[long_string_index].c = %0d", s_assoc_arr["long_string_index"].c); foreach (s_assoc_arr_2[6'd30].arr[j]) $display("s_assoc_arr_2[30].arr[%0d] = %0d", j, s_assoc_arr_2[6'd30].arr[j]); $display("s_assoc_arr_2[30].a = %0d", s_assoc_arr_2[6'd30].a); $display("s_assoc_arr_2[30].b = %0d", s_assoc_arr_2[6'd30].b); $display("s_assoc_arr_2[30].c = %0d", s_assoc_arr_2[6'd30].c); foreach (s_assoc_arr_2[6'd7].arr[j]) $display("s_assoc_arr_2[7].arr[%0d] = %0d", j, s_assoc_arr_2[6'd7].arr[j]); $display("s_assoc_arr_2[7].a = %0d", s_assoc_arr_2[6'd7].a); $display("s_assoc_arr_2[7].b = %0d", s_assoc_arr_2[6'd7].b); $display("s_assoc_arr_2[7].c = %0d", s_assoc_arr_2[6'd7].c); endfunction function void self_test(); foreach (s_arr[i]) begin foreach (s_arr[i].arr[j]) if (!(s_arr[i].arr[j] inside {[0:9]})) $stop; if (!(s_arr[i].a inside {[40:50]})) $stop; end foreach (s_2d_arr[i, j]) begin foreach (s_2d_arr[i][j].arr[k]) if (!(s_2d_arr[i][j].arr[k] inside {[9:19]})) $stop; if (!(s_2d_arr[i][j].a inside {[50:60]})) $stop; end foreach (s_dyn_arr[i]) begin foreach (s_dyn_arr[i].arr[j]) if (!(s_dyn_arr[i].arr[j] inside {[19:29]})) $stop; if (!(s_dyn_arr[i].a inside {[60:70]})) $stop; end foreach (s_que_arr[i]) begin foreach (s_que_arr[i].arr[j]) if (!(s_que_arr[i].arr[j] inside {[29:39]})) $stop; if (!(s_que_arr[i].a inside {[70:80]})) $stop; end foreach (s_assoc_arr["x"].arr[j]) if (!(s_assoc_arr["x"].arr[j] inside {[39:49]})) $stop; if (!(s_assoc_arr["x"].a inside {[80:90]})) $stop; foreach (s_assoc_arr["y"].arr[j]) if (!(s_assoc_arr["y"].arr[j] inside {[39:49]})) $stop; if (!(s_assoc_arr["y"].a inside {[80:90]})) $stop; foreach (s_assoc_arr["long_string_index"].arr[j]) if (!(s_assoc_arr["long_string_index"].arr[j] inside {[39:49]})) $stop; if (!(s_assoc_arr["long_string_index"].a inside {[80:90]})) $stop; foreach (s_assoc_arr_2[6'd30].arr[j]) if (!(s_assoc_arr_2[6'd30].arr[j] inside {[49:59]})) $stop; if (!(s_assoc_arr_2[6'd30].a inside {[90:100]})) $stop; foreach (s_assoc_arr_2[6'd7].arr[j]) if (!(s_assoc_arr_2[6'd7].arr[j] inside {[49:59]})) $stop; if (!(s_assoc_arr_2[6'd7].a inside {[90:100]})) $stop; endfunction /* verilator lint_off WIDTHTRUNC */ endclass class MixedStructure; /* verilator lint_off WIDTHTRUNC */ typedef struct { rand int arr[3]; // static unpacked array rand int dyn[]; // dynamic array rand int que[$]; // queue rand int assoc[string]; // associative array with string key rand int a; rand bit [3:0] b; bit c; } struct_t; rand struct_t s_arr[2]; constraint c_static { foreach (s_arr[i]) foreach (s_arr[i].arr[j]) s_arr[i].arr[j] inside {[0:9]}; } constraint c_dyn { foreach (s_arr[i]) foreach (s_arr[i].dyn[j]) s_arr[i].dyn[j] inside {[10:19]}; } constraint c_queue { foreach (s_arr[i]) foreach (s_arr[i].que[j]) s_arr[i].que[j] inside {[20:29]}; } constraint c_assoc { foreach (s_arr[i]) { s_arr[i].assoc["x"] inside {[30:39]}; s_arr[i].assoc["y"] inside {[30:39]}; } } constraint c_other { foreach (s_arr[i]) s_arr[i].a inside {[40:50]}; } function new(); foreach (s_arr[i]) begin s_arr[i].dyn = new[2]; s_arr[i].que = {0, 0}; s_arr[i].assoc = '{"x": 0, "y": 0}; foreach (s_arr[i].arr[j]) s_arr[i].arr[j] = j; foreach (s_arr[i].dyn[j]) s_arr[i].dyn[j] = 10 + j; foreach (s_arr[i].que[j]) s_arr[i].que[j] = 20 + j; s_arr[i].assoc["x"] = i + 30; s_arr[i].assoc["y"] = i + 31; s_arr[i].a = 40 + i; s_arr[i].b = i; s_arr[i].c = i; end endfunction function void print(); foreach (s_arr[i]) begin foreach (s_arr[i].arr[j]) $display("s_arr[%0d].arr[%0d] = %0d", i, j, s_arr[i].arr[j]); foreach (s_arr[i].dyn[j]) $display("s_arr[%0d].dyn[%0d] = %0d", i, j, s_arr[i].dyn[j]); foreach (s_arr[i].que[j]) $display("s_arr[%0d].que[%0d] = %0d", i, j, s_arr[i].que[j]); $display("s_arr[%0d].assoc[\"x\"] = %0d", i, s_arr[i].assoc["x"]); $display("s_arr[%0d].assoc[\"y\"] = %0d", i, s_arr[i].assoc["y"]); $display("s_arr[%0d].a = %0d", i, s_arr[i].a); $display("s_arr[%0d].b = %0d", i, s_arr[i].b); $display("s_arr[%0d].c = %0d", i, s_arr[i].c); end endfunction function void self_test(); foreach (s_arr[i]) begin foreach (s_arr[i].arr[j]) if (!(s_arr[i].arr[j] inside {[0:9]})) $stop; foreach (s_arr[i].dyn[j]) if (!(s_arr[i].dyn[j] inside {[10:19]})) $stop; foreach (s_arr[i].que[j]) if (!(s_arr[i].que[j] inside {[20:29]})) $stop; if (!(s_arr[i].assoc.exists("x") && s_arr[i].assoc["x"] inside {[30:39]})) $stop; if (!(s_arr[i].assoc.exists("y") && s_arr[i].assoc["y"] inside {[30:39]})) $stop; if (!(s_arr[i].a inside {[40:50]})) $stop; if (i == 0 && s_arr[i].c != 0) $stop; if (i == 1 && s_arr[i].c != 1) $stop; end endfunction /* verilator lint_off WIDTHTRUNC */ endclass module t_constraint_struct_complex; int success; ArrayStruct as_c; StructArray sa_c; MixedStructure mixed_c; initial begin as_c = new(); sa_c = new(); mixed_c = new(); success = as_c.randomize(); if (success != 1) $stop; as_c.self_test(); // as_c.print(); // $display(" ArrayStruct passed! \n"); success = sa_c.randomize(); if (success != 1) $stop; sa_c.self_test(); // sa_c.print(); // $display(" StructArray passed! \n"); success = mixed_c.randomize(); if (success != 1) $stop; mixed_c.self_test(); // mixed_c.print(); // $display(" MixedStructure passed! \n"); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_force_bad_rw.py0000755000542200017500000000076315101701376022410 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_initial_edge_bad.py0000755000542200017500000000122315101701376023207 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # This works with other vlt_alls, we we don't run it for them. It should # fail with Verilator if --x-initial-edge is not specified. import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_initial_edge.v" test.compile() test.execute(fails=True) test.passes() verilator-5.042/test_regress/t/t_vlcov_merge.out0000644000542200017500000000046015101701376022452 0ustar mahmoudyfreeshell# SystemC::Coverage-3 C 'CoverPoint0ffile1.sphl159' 0 C 'CoverPoint1ffile1.sphl159' 1 C 'CoverPoint2ffile1.sphl159' 20 C 'CoverPoint3ffile1.sphl159' 0 C 'CoverPoint4ffile1.sphl159' 1 C 'CoverPoint5ffile1.sphl159' 9 C 'CoverPoint6ffile1.sphl159' 22 verilator-5.042/test_regress/t/t_class_param.py0000755000542200017500000000073415101701376022257 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_timescale_parse_bad.v0000644000542200017500000000067315101701376023554 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under The Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // units < precision `timescale 1ps/1ns // Bad scale `timescale frump `timescale 1xs `timescale 2ps `timescale 1ns / frump `timescale 1ns / 1ps /extra module t; timeunit 2ps; // Bad timeprecision 2ps; // Bad endmodule verilator-5.042/test_regress/t/t_tri_public.py0000755000542200017500000000074115101701376022124 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() # Compile only test test.passes() verilator-5.042/test_regress/t/t_lint_ftask_output_assign_bad.py0000755000542200017500000000076315101701376025724 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_randomize_local_param.v0000644000542200017500000000131315101701376024120 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package Pkg; virtual class uvm_sequence #( type REQ = int ); REQ m_req; endclass endpackage package SubPkg; import Pkg::*; class s_trgt_txn; int m_txn_val; endclass class p_mem_seq extends uvm_sequence #(s_trgt_txn); rand bit m_wr_flag; virtual task body(); if (0 !== (m_req.randomize() with {local::m_wr_flag;})) begin end endtask endclass endpackage module t; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_hier_block_sc_trace_vcd.out0000644000542200017500000141775315101701376024764 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $scope module t $end $var wire 32 w" PARAM_A [31:0] $end $var wire 32 x" PARAM_B [31:0] $end $var wire 1 v" clk $end $var wire 8 C" out0 [7:0] $end $var wire 8 D" out1 [7:0] $end $var wire 8 E" out2 [7:0] $end $var wire 8 ?! out3 [7:0] $end $var wire 8 # out3_2 [7:0] $end $var wire 8 $ out5 [7:0] $end $var wire 8 % out6 [7:0] $end $var wire 32 & count [31:0] $end $scope module i_delay0 $end $var wire 32 y" N [31:0] $end $var wire 32 z" WIDTH [31:0] $end $var wire 1 v" clk $end $var wire 8 ?! in [7:0] $end $var wire 8 $ out [7:0] $end $var wire 8 ' tmp [7:0] $end $scope module genblk1 $end $scope module i_delay $end $var wire 32 {" N [31:0] $end $var wire 32 z" WIDTH [31:0] $end $var wire 1 v" clk $end $var wire 8 ' in [7:0] $end $var wire 8 $ out [7:0] $end $var wire 8 $ tmp [7:0] $end $upscope $end $upscope $end $upscope $end $scope module i_delay1 $end $var wire 32 |" N [31:0] $end $var wire 32 z" WIDTH [31:0] $end $var wire 1 v" clk $end $var wire 8 $ in [7:0] $end $var wire 8 % out [7:0] $end $var wire 8 ( tmp [7:0] $end $scope module genblk1 $end $scope module i_delay $end $var wire 32 y" N [31:0] $end $var wire 32 z" WIDTH [31:0] $end $var wire 1 v" clk $end $var wire 8 ( in [7:0] $end $var wire 8 % out [7:0] $end $var wire 8 ) tmp [7:0] $end $scope module genblk1 $end $scope module i_delay $end $var wire 32 {" N [31:0] $end $var wire 32 z" WIDTH [31:0] $end $var wire 1 v" clk $end $var wire 8 ) in [7:0] $end $var wire 8 % out [7:0] $end $var wire 8 % tmp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module i_sub0 $end $var wire 1 v" clk $end $var wire 8 ?! in [7:0] $end $var wire 8 C" out [7:0] $end $scope module i_sub0 $end $var wire 1 v" clk $end $var wire 8 ?! in [7:0] $end $var wire 8 C" out [7:0] $end $upscope $end $upscope $end $scope module i_sub1 $end $var wire 1 v" clk $end $var wire 8 C" in [11:4] $end $var wire 8 D" out [7:0] $end $upscope $end $scope module i_sub2 $end $var wire 1 v" clk $end $var wire 8 D" in [7:0] $end $var wire 8 E" out [7:0] $end $upscope $end $scope module i_sub3 $end $var wire 8 }" P0 [7:0] $end $var wire 32 ~" UNPACKED_ARRAY[0] [31:0] $end $var wire 32 !# UNPACKED_ARRAY[1] [31:0] $end $var wire 16 "# UNUSED [15:0] $end $var wire 2 ## ENUM [1:0] $end $var wire 1 v" clk $end $var wire 8 E" in [7:0] $end $var wire 8 ?! out [7:0] $end $var wire 8 @! ff [7:0] $end $var wire 8 ?! out4 [7:0] $end $var wire 8 * out4_2 [7:0] $end $scope module i_sub4_0 $end $var wire 32 $# P0 [31:0] $end $var real 64 %# P1 $end $var real 64 '# P3 $end $var wire 1 v" clk $end $var wire 8 @! in [7:0] $end $var wire 8 ?! out [7:0] $end $var wire 8 ?! ff [7:0] $end $var wire 128 + sub5_in[0][0] [127:0] $end $var wire 128 / sub5_in[0][1] [127:0] $end $var wire 128 3 sub5_in[0][2] [127:0] $end $var wire 128 7 sub5_in[1][0] [127:0] $end $var wire 128 ; sub5_in[1][1] [127:0] $end $var wire 128 ? sub5_in[1][2] [127:0] $end $var wire 8 F" sub5_out[0][0] [7:0] $end $var wire 8 G" sub5_out[0][1] [7:0] $end $var wire 8 H" sub5_out[0][2] [7:0] $end $var wire 8 I" sub5_out[1][0] [7:0] $end $var wire 8 J" sub5_out[1][1] [7:0] $end $var wire 8 K" sub5_out[1][2] [7:0] $end $var wire 32 C count [31:0] $end $scope module i_sub5 $end $var wire 1 v" clk $end $var wire 128 A! in[0][0] [127:0] $end $var wire 128 E! in[0][1] [127:0] $end $var wire 128 I! in[0][2] [127:0] $end $var wire 128 M! in[1][0] [127:0] $end $var wire 128 Q! in[1][1] [127:0] $end $var wire 128 U! in[1][2] [127:0] $end $var wire 8 L" out[0][0] [7:0] $end $var wire 8 M" out[0][1] [7:0] $end $var wire 8 N" out[0][2] [7:0] $end $var wire 8 O" out[1][0] [7:0] $end $var wire 8 P" out[1][1] [7:0] $end $var wire 8 Q" out[1][2] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var wire 32 D i [31:0] $end $scope module unnamedblk2 $end $var wire 32 E j [31:0] $end $scope module unnamedblk3 $end $var wire 8 F exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module i_sub4_1 $end $var wire 32 $# P0 [31:0] $end $var real 64 %# P1 $end $var real 64 )# P3 $end $var wire 1 v" clk $end $var wire 8 @! in [7:0] $end $var wire 8 * out [7:0] $end $var wire 8 * ff [7:0] $end $var wire 128 G sub5_in[0][0] [127:0] $end $var wire 128 K sub5_in[0][1] [127:0] $end $var wire 128 O sub5_in[0][2] [127:0] $end $var wire 128 S sub5_in[1][0] [127:0] $end $var wire 128 W sub5_in[1][1] [127:0] $end $var wire 128 [ sub5_in[1][2] [127:0] $end $var wire 8 R" sub5_out[0][0] [7:0] $end $var wire 8 S" sub5_out[0][1] [7:0] $end $var wire 8 T" sub5_out[0][2] [7:0] $end $var wire 8 U" sub5_out[1][0] [7:0] $end $var wire 8 V" sub5_out[1][1] [7:0] $end $var wire 8 W" sub5_out[1][2] [7:0] $end $var wire 32 _ count [31:0] $end $scope module i_sub5 $end $var wire 1 v" clk $end $var wire 128 Y! in[0][0] [127:0] $end $var wire 128 ]! in[0][1] [127:0] $end $var wire 128 a! in[0][2] [127:0] $end $var wire 128 e! in[1][0] [127:0] $end $var wire 128 i! in[1][1] [127:0] $end $var wire 128 m! in[1][2] [127:0] $end $var wire 8 X" out[0][0] [7:0] $end $var wire 8 Y" out[0][1] [7:0] $end $var wire 8 Z" out[0][2] [7:0] $end $var wire 8 [" out[1][0] [7:0] $end $var wire 8 \" out[1][1] [7:0] $end $var wire 8 ]" out[1][2] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var wire 32 ` i [31:0] $end $scope module unnamedblk2 $end $var wire 32 a j [31:0] $end $scope module unnamedblk3 $end $var wire 8 b exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module i_sub3_2 $end $var wire 8 }" P0 [7:0] $end $var wire 32 +# UNPACKED_ARRAY[0] [31:0] $end $var wire 32 ,# UNPACKED_ARRAY[1] [31:0] $end $var wire 16 "# UNUSED [15:0] $end $var wire 2 ## ENUM [1:0] $end $var wire 1 v" clk $end $var wire 8 E" in [7:0] $end $var wire 8 # out [7:0] $end $var wire 8 c ff [7:0] $end $var wire 8 # out4 [7:0] $end $var wire 8 d out4_2 [7:0] $end $scope module i_sub4_0 $end $var wire 32 $# P0 [31:0] $end $var real 64 %# P1 $end $var real 64 '# P3 $end $var wire 1 v" clk $end $var wire 8 c in [7:0] $end $var wire 8 # out [7:0] $end $var wire 8 # ff [7:0] $end $var wire 128 e sub5_in[0][0] [127:0] $end $var wire 128 i sub5_in[0][1] [127:0] $end $var wire 128 m sub5_in[0][2] [127:0] $end $var wire 128 q sub5_in[1][0] [127:0] $end $var wire 128 u sub5_in[1][1] [127:0] $end $var wire 128 y sub5_in[1][2] [127:0] $end $var wire 8 ^" sub5_out[0][0] [7:0] $end $var wire 8 _" sub5_out[0][1] [7:0] $end $var wire 8 `" sub5_out[0][2] [7:0] $end $var wire 8 a" sub5_out[1][0] [7:0] $end $var wire 8 b" sub5_out[1][1] [7:0] $end $var wire 8 c" sub5_out[1][2] [7:0] $end $var wire 32 } count [31:0] $end $scope module i_sub5 $end $var wire 1 v" clk $end $var wire 128 q! in[0][0] [127:0] $end $var wire 128 u! in[0][1] [127:0] $end $var wire 128 y! in[0][2] [127:0] $end $var wire 128 }! in[1][0] [127:0] $end $var wire 128 #" in[1][1] [127:0] $end $var wire 128 '" in[1][2] [127:0] $end $var wire 8 d" out[0][0] [7:0] $end $var wire 8 e" out[0][1] [7:0] $end $var wire 8 f" out[0][2] [7:0] $end $var wire 8 g" out[1][0] [7:0] $end $var wire 8 h" out[1][1] [7:0] $end $var wire 8 i" out[1][2] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var wire 32 ~ i [31:0] $end $scope module unnamedblk2 $end $var wire 32 !! j [31:0] $end $scope module unnamedblk3 $end $var wire 8 "! exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module i_sub4_1 $end $var wire 32 $# P0 [31:0] $end $var real 64 %# P1 $end $var real 64 )# P3 $end $var wire 1 v" clk $end $var wire 8 c in [7:0] $end $var wire 8 d out [7:0] $end $var wire 8 d ff [7:0] $end $var wire 128 #! sub5_in[0][0] [127:0] $end $var wire 128 '! sub5_in[0][1] [127:0] $end $var wire 128 +! sub5_in[0][2] [127:0] $end $var wire 128 /! sub5_in[1][0] [127:0] $end $var wire 128 3! sub5_in[1][1] [127:0] $end $var wire 128 7! sub5_in[1][2] [127:0] $end $var wire 8 j" sub5_out[0][0] [7:0] $end $var wire 8 k" sub5_out[0][1] [7:0] $end $var wire 8 l" sub5_out[0][2] [7:0] $end $var wire 8 m" sub5_out[1][0] [7:0] $end $var wire 8 n" sub5_out[1][1] [7:0] $end $var wire 8 o" sub5_out[1][2] [7:0] $end $var wire 32 ;! count [31:0] $end $scope module i_sub5 $end $var wire 1 v" clk $end $var wire 128 +" in[0][0] [127:0] $end $var wire 128 /" in[0][1] [127:0] $end $var wire 128 3" in[0][2] [127:0] $end $var wire 128 7" in[1][0] [127:0] $end $var wire 128 ;" in[1][1] [127:0] $end $var wire 128 ?" in[1][2] [127:0] $end $var wire 8 p" out[0][0] [7:0] $end $var wire 8 q" out[0][1] [7:0] $end $var wire 8 r" out[0][2] [7:0] $end $var wire 8 s" out[1][0] [7:0] $end $var wire 8 t" out[1][1] [7:0] $end $var wire 8 u" out[1][2] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var wire 32 ! exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub0.i_sub0 $end $var wire 1 .# clk $end $var wire 8 /# in [7:0] $end $var wire 8 0# out [7:0] $end $scope module sub0 $end $var wire 1 .# clk $end $var wire 8 /# in [7:0] $end $var wire 8 0# out [7:0] $end $var wire 8 1# ff [7:0] $end $upscope $end $upscope $end $scope module top.t.i_sub1 $end $var wire 1 3# clk $end $var wire 8 4# in [11:4] $end $var wire 8 5# out [7:0] $end $scope module sub1 $end $var wire 1 3# clk $end $var wire 8 4# in [11:4] $end $var wire 8 5# out [7:0] $end $var wire 8 6# ff [7:0] $end $upscope $end $upscope $end $scope module top.t.i_sub2 $end $var wire 1 #' clk $end $var wire 8 $' in [7:0] $end $var wire 8 %' out [7:0] $end $scope module sub2 $end $var wire 1 #' clk $end $var wire 8 $' in [7:0] $end $var wire 8 %' out [7:0] $end $var wire 8 x# ff [7:0] $end $scope module in_ifs $end $var wire 1 #' clk $end $var wire 8 x# data [7:0] $end $upscope $end $scope module out_ifs $end $var wire 1 #' clk $end $var wire 8 y# data [7:0] $end $upscope $end $scope module i_sub3 $end $scope module in $end $var wire 1 #' clk $end $var wire 8 x# data [7:0] $end $upscope $end $scope module out $end $var wire 1 #' clk $end $var wire 8 y# data [7:0] $end $upscope $end $var wire 8 x# in_wire [7:0] $end $var wire 8 y# out_1 [7:0] $end $var wire 8 z# out_2 [7:0] $end $scope module i_sub3 $end $var wire 8 &' P0 [7:0] $end $var wire 32 '' UNPACKED_ARRAY[0] [31:0] $end $var wire 32 (' UNPACKED_ARRAY[1] [31:0] $end $var wire 16 )' UNUSED [15:0] $end $var wire 2 *' ENUM [1:0] $end $var wire 1 #' clk $end $var wire 8 x# in [7:0] $end $var wire 8 y# out [7:0] $end $var wire 8 {# ff [7:0] $end $var wire 8 y# out4 [7:0] $end $var wire 8 |# out4_2 [7:0] $end $scope module i_sub4_0 $end $var wire 32 +' P0 [31:0] $end $var real 64 ,' P1 $end $var real 64 .' P3 $end $var wire 1 #' clk $end $var wire 8 {# in [7:0] $end $var wire 8 y# out [7:0] $end $var wire 8 y# ff [7:0] $end $var wire 128 }# sub5_in[0][0] [127:0] $end $var wire 128 #$ sub5_in[0][1] [127:0] $end $var wire 128 '$ sub5_in[0][2] [127:0] $end $var wire 128 +$ sub5_in[1][0] [127:0] $end $var wire 128 /$ sub5_in[1][1] [127:0] $end $var wire 128 3$ sub5_in[1][2] [127:0] $end $var wire 8 7$ sub5_out[0][0] [7:0] $end $var wire 8 8$ sub5_out[0][1] [7:0] $end $var wire 8 9$ sub5_out[0][2] [7:0] $end $var wire 8 :$ sub5_out[1][0] [7:0] $end $var wire 8 ;$ sub5_out[1][1] [7:0] $end $var wire 8 <$ sub5_out[1][2] [7:0] $end $var wire 32 =$ count [31:0] $end $scope module i_sub5 $end $var wire 1 #' clk $end $var wire 128 >$ in[0][0] [127:0] $end $var wire 128 B$ in[0][1] [127:0] $end $var wire 128 F$ in[0][2] [127:0] $end $var wire 128 J$ in[1][0] [127:0] $end $var wire 128 N$ in[1][1] [127:0] $end $var wire 128 R$ in[1][2] [127:0] $end $var wire 8 V$ out[0][0] [7:0] $end $var wire 8 W$ out[0][1] [7:0] $end $var wire 8 X$ out[0][2] [7:0] $end $var wire 8 Y$ out[1][0] [7:0] $end $var wire 8 Z$ out[1][1] [7:0] $end $var wire 8 [$ out[1][2] [7:0] $end $var wire 32 \$ count [31:0] $end $var wire 8 8# val0[0] [7:0] $end $var wire 8 9# val0[1] [7:0] $end $var wire 8 :# val1[0] [7:0] $end $var wire 8 ;# val1[1] [7:0] $end $var wire 8 <# val2[0] [7:0] $end $var wire 8 =# val2[1] [7:0] $end $var wire 8 ># val3[0] [7:0] $end $var wire 8 ?# val3[1] [7:0] $end $scope module i_sub0 $end $var wire 32 0' P0 [31:0] $end $var wire 32 1' P1 [31:0] $end $var wire 8 @# out[0] [7:0] $end $var wire 8 A# out[1] [7:0] $end $upscope $end $scope module i_sub1 $end $var wire 32 0' P0 [31:0] $end $var wire 32 1' P1 [31:0] $end $var wire 8 B# out[0] [7:0] $end $var wire 8 C# out[1] [7:0] $end $upscope $end $scope module i_sub2 $end $var wire 32 0' P0 [31:0] $end $var wire 32 1' P1 [31:0] $end $var wire 8 D# out[0] [7:0] $end $var wire 8 E# out[1] [7:0] $end $upscope $end $scope module i_sub3 $end $var wire 32 0' P0 [31:0] $end $var wire 32 2' P1 [31:0] $end $var wire 8 F# out[0] [7:0] $end $var wire 8 G# out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var wire 32 ]$ i [31:0] $end $scope module unnamedblk2 $end $var wire 32 ^$ j [31:0] $end $scope module unnamedblk3 $end $var wire 128 _$ exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module unnamedblk1 $end $var wire 32 c$ i [31:0] $end $scope module unnamedblk2 $end $var wire 32 d$ j [31:0] $end $scope module unnamedblk3 $end $var wire 8 e$ exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module i_sub4_1 $end $var wire 32 +' P0 [31:0] $end $var real 64 ,' P1 $end $var real 64 3' P3 $end $var wire 1 #' clk $end $var wire 8 {# in [7:0] $end $var wire 8 |# out [7:0] $end $var wire 8 |# ff [7:0] $end $var wire 128 f$ sub5_in[0][0] [127:0] $end $var wire 128 j$ sub5_in[0][1] [127:0] $end $var wire 128 n$ sub5_in[0][2] [127:0] $end $var wire 128 r$ sub5_in[1][0] [127:0] $end $var wire 128 v$ sub5_in[1][1] [127:0] $end $var wire 128 z$ sub5_in[1][2] [127:0] $end $var wire 8 ~$ sub5_out[0][0] [7:0] $end $var wire 8 !% sub5_out[0][1] [7:0] $end $var wire 8 "% sub5_out[0][2] [7:0] $end $var wire 8 #% sub5_out[1][0] [7:0] $end $var wire 8 $% sub5_out[1][1] [7:0] $end $var wire 8 %% sub5_out[1][2] [7:0] $end $var wire 32 &% count [31:0] $end $scope module i_sub5 $end $var wire 1 #' clk $end $var wire 128 '% in[0][0] [127:0] $end $var wire 128 +% in[0][1] [127:0] $end $var wire 128 /% in[0][2] [127:0] $end $var wire 128 3% in[1][0] [127:0] $end $var wire 128 7% in[1][1] [127:0] $end $var wire 128 ;% in[1][2] [127:0] $end $var wire 8 ?% out[0][0] [7:0] $end $var wire 8 @% out[0][1] [7:0] $end $var wire 8 A% out[0][2] [7:0] $end $var wire 8 B% out[1][0] [7:0] $end $var wire 8 C% out[1][1] [7:0] $end $var wire 8 D% out[1][2] [7:0] $end $var wire 32 E% count [31:0] $end $var wire 8 H# val0[0] [7:0] $end $var wire 8 I# val0[1] [7:0] $end $var wire 8 J# val1[0] [7:0] $end $var wire 8 K# val1[1] [7:0] $end $var wire 8 L# val2[0] [7:0] $end $var wire 8 M# val2[1] [7:0] $end $var wire 8 N# val3[0] [7:0] $end $var wire 8 O# val3[1] [7:0] $end $scope module i_sub0 $end $var wire 32 0' P0 [31:0] $end $var wire 32 1' P1 [31:0] $end $var wire 8 P# out[0] [7:0] $end $var wire 8 Q# out[1] [7:0] $end $upscope $end $scope module i_sub1 $end $var wire 32 0' P0 [31:0] $end $var wire 32 1' P1 [31:0] $end $var wire 8 R# out[0] [7:0] $end $var wire 8 S# out[1] [7:0] $end $upscope $end $scope module i_sub2 $end $var wire 32 0' P0 [31:0] $end $var wire 32 1' P1 [31:0] $end $var wire 8 T# out[0] [7:0] $end $var wire 8 U# out[1] [7:0] $end $upscope $end $scope module i_sub3 $end $var wire 32 0' P0 [31:0] $end $var wire 32 2' P1 [31:0] $end $var wire 8 V# out[0] [7:0] $end $var wire 8 W# out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var wire 32 F% i [31:0] $end $scope module unnamedblk2 $end $var wire 32 G% j [31:0] $end $scope module unnamedblk3 $end $var wire 128 H% exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module unnamedblk1 $end $var wire 32 L% i [31:0] $end $scope module unnamedblk2 $end $var wire 32 M% j [31:0] $end $scope module unnamedblk3 $end $var wire 8 N% exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module i_sub3_2 $end $var wire 8 &' P0 [7:0] $end $var wire 32 5' UNPACKED_ARRAY[0] [31:0] $end $var wire 32 6' UNPACKED_ARRAY[1] [31:0] $end $var wire 16 )' UNUSED [15:0] $end $var wire 2 *' ENUM [1:0] $end $var wire 1 #' clk $end $var wire 8 x# in [7:0] $end $var wire 8 z# out [7:0] $end $var wire 8 O% ff [7:0] $end $var wire 8 z# out4 [7:0] $end $var wire 8 P% out4_2 [7:0] $end $scope module i_sub4_0 $end $var wire 32 +' P0 [31:0] $end $var real 64 ,' P1 $end $var real 64 .' P3 $end $var wire 1 #' clk $end $var wire 8 O% in [7:0] $end $var wire 8 z# out [7:0] $end $var wire 8 z# ff [7:0] $end $var wire 128 Q% sub5_in[0][0] [127:0] $end $var wire 128 U% sub5_in[0][1] [127:0] $end $var wire 128 Y% sub5_in[0][2] [127:0] $end $var wire 128 ]% sub5_in[1][0] [127:0] $end $var wire 128 a% sub5_in[1][1] [127:0] $end $var wire 128 e% sub5_in[1][2] [127:0] $end $var wire 8 i% sub5_out[0][0] [7:0] $end $var wire 8 j% sub5_out[0][1] [7:0] $end $var wire 8 k% sub5_out[0][2] [7:0] $end $var wire 8 l% sub5_out[1][0] [7:0] $end $var wire 8 m% sub5_out[1][1] [7:0] $end $var wire 8 n% sub5_out[1][2] [7:0] $end $var wire 32 o% count [31:0] $end $scope module i_sub5 $end $var wire 1 #' clk $end $var wire 128 p% in[0][0] [127:0] $end $var wire 128 t% in[0][1] [127:0] $end $var wire 128 x% in[0][2] [127:0] $end $var wire 128 |% in[1][0] [127:0] $end $var wire 128 "& in[1][1] [127:0] $end $var wire 128 && in[1][2] [127:0] $end $var wire 8 *& out[0][0] [7:0] $end $var wire 8 +& out[0][1] [7:0] $end $var wire 8 ,& out[0][2] [7:0] $end $var wire 8 -& out[1][0] [7:0] $end $var wire 8 .& out[1][1] [7:0] $end $var wire 8 /& out[1][2] [7:0] $end $var wire 32 0& count [31:0] $end $var wire 8 X# val0[0] [7:0] $end $var wire 8 Y# val0[1] [7:0] $end $var wire 8 Z# val1[0] [7:0] $end $var wire 8 [# val1[1] [7:0] $end $var wire 8 \# val2[0] [7:0] $end $var wire 8 ]# val2[1] [7:0] $end $var wire 8 ^# val3[0] [7:0] $end $var wire 8 _# val3[1] [7:0] $end $scope module i_sub0 $end $var wire 32 0' P0 [31:0] $end $var wire 32 1' P1 [31:0] $end $var wire 8 `# out[0] [7:0] $end $var wire 8 a# out[1] [7:0] $end $upscope $end $scope module i_sub1 $end $var wire 32 0' P0 [31:0] $end $var wire 32 1' P1 [31:0] $end $var wire 8 b# out[0] [7:0] $end $var wire 8 c# out[1] [7:0] $end $upscope $end $scope module i_sub2 $end $var wire 32 0' P0 [31:0] $end $var wire 32 1' P1 [31:0] $end $var wire 8 d# out[0] [7:0] $end $var wire 8 e# out[1] [7:0] $end $upscope $end $scope module i_sub3 $end $var wire 32 0' P0 [31:0] $end $var wire 32 2' P1 [31:0] $end $var wire 8 f# out[0] [7:0] $end $var wire 8 g# out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var wire 32 1& i [31:0] $end $scope module unnamedblk2 $end $var wire 32 2& j [31:0] $end $scope module unnamedblk3 $end $var wire 128 3& exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module unnamedblk1 $end $var wire 32 7& i [31:0] $end $scope module unnamedblk2 $end $var wire 32 8& j [31:0] $end $scope module unnamedblk3 $end $var wire 8 9& exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module i_sub4_1 $end $var wire 32 +' P0 [31:0] $end $var real 64 ,' P1 $end $var real 64 3' P3 $end $var wire 1 #' clk $end $var wire 8 O% in [7:0] $end $var wire 8 P% out [7:0] $end $var wire 8 P% ff [7:0] $end $var wire 128 :& sub5_in[0][0] [127:0] $end $var wire 128 >& sub5_in[0][1] [127:0] $end $var wire 128 B& sub5_in[0][2] [127:0] $end $var wire 128 F& sub5_in[1][0] [127:0] $end $var wire 128 J& sub5_in[1][1] [127:0] $end $var wire 128 N& sub5_in[1][2] [127:0] $end $var wire 8 R& sub5_out[0][0] [7:0] $end $var wire 8 S& sub5_out[0][1] [7:0] $end $var wire 8 T& sub5_out[0][2] [7:0] $end $var wire 8 U& sub5_out[1][0] [7:0] $end $var wire 8 V& sub5_out[1][1] [7:0] $end $var wire 8 W& sub5_out[1][2] [7:0] $end $var wire 32 X& count [31:0] $end $scope module i_sub5 $end $var wire 1 #' clk $end $var wire 128 Y& in[0][0] [127:0] $end $var wire 128 ]& in[0][1] [127:0] $end $var wire 128 a& in[0][2] [127:0] $end $var wire 128 e& in[1][0] [127:0] $end $var wire 128 i& in[1][1] [127:0] $end $var wire 128 m& in[1][2] [127:0] $end $var wire 8 q& out[0][0] [7:0] $end $var wire 8 r& out[0][1] [7:0] $end $var wire 8 s& out[0][2] [7:0] $end $var wire 8 t& out[1][0] [7:0] $end $var wire 8 u& out[1][1] [7:0] $end $var wire 8 v& out[1][2] [7:0] $end $var wire 32 w& count [31:0] $end $var wire 8 h# val0[0] [7:0] $end $var wire 8 i# val0[1] [7:0] $end $var wire 8 j# val1[0] [7:0] $end $var wire 8 k# val1[1] [7:0] $end $var wire 8 l# val2[0] [7:0] $end $var wire 8 m# val2[1] [7:0] $end $var wire 8 n# val3[0] [7:0] $end $var wire 8 o# val3[1] [7:0] $end $scope module i_sub0 $end $var wire 32 0' P0 [31:0] $end $var wire 32 1' P1 [31:0] $end $var wire 8 p# out[0] [7:0] $end $var wire 8 q# out[1] [7:0] $end $upscope $end $scope module i_sub1 $end $var wire 32 0' P0 [31:0] $end $var wire 32 1' P1 [31:0] $end $var wire 8 r# out[0] [7:0] $end $var wire 8 s# out[1] [7:0] $end $upscope $end $scope module i_sub2 $end $var wire 32 0' P0 [31:0] $end $var wire 32 1' P1 [31:0] $end $var wire 8 t# out[0] [7:0] $end $var wire 8 u# out[1] [7:0] $end $upscope $end $scope module i_sub3 $end $var wire 32 0' P0 [31:0] $end $var wire 32 2' P1 [31:0] $end $var wire 8 v# out[0] [7:0] $end $var wire 8 w# out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var wire 32 x& i [31:0] $end $scope module unnamedblk2 $end $var wire 32 y& j [31:0] $end $scope module unnamedblk3 $end $var wire 128 z& exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module unnamedblk1 $end $var wire 32 ~& i [31:0] $end $scope module unnamedblk2 $end $var wire 32 !' j [31:0] $end $scope module unnamedblk3 $end $var wire 8 "' exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3.i_sub4_0.i_sub5 $end $var wire 1 m' clk $end $var wire 128 n' in[0][0] [127:0] $end $var wire 128 r' in[0][1] [127:0] $end $var wire 128 v' in[0][2] [127:0] $end $var wire 128 z' in[1][0] [127:0] $end $var wire 128 ~' in[1][1] [127:0] $end $var wire 128 $( in[1][2] [127:0] $end $var wire 8 (( out[0][0] [7:0] $end $var wire 8 )( out[0][1] [7:0] $end $var wire 8 *( out[0][2] [7:0] $end $var wire 8 +( out[1][0] [7:0] $end $var wire 8 ,( out[1][1] [7:0] $end $var wire 8 -( out[1][2] [7:0] $end $scope module sub5 $end $var wire 1 m' clk $end $var wire 128 H' in[0][0] [127:0] $end $var wire 128 L' in[0][1] [127:0] $end $var wire 128 P' in[0][2] [127:0] $end $var wire 128 T' in[1][0] [127:0] $end $var wire 128 X' in[1][1] [127:0] $end $var wire 128 \' in[1][2] [127:0] $end $var wire 8 `' out[0][0] [7:0] $end $var wire 8 a' out[0][1] [7:0] $end $var wire 8 b' out[0][2] [7:0] $end $var wire 8 c' out[1][0] [7:0] $end $var wire 8 d' out[1][1] [7:0] $end $var wire 8 e' out[1][2] [7:0] $end $var wire 32 f' count [31:0] $end $var wire 8 8' val0[0] [7:0] $end $var wire 8 9' val0[1] [7:0] $end $var wire 8 :' val1[0] [7:0] $end $var wire 8 ;' val1[1] [7:0] $end $var wire 8 <' val2[0] [7:0] $end $var wire 8 =' val2[1] [7:0] $end $var wire 8 >' val3[0] [7:0] $end $var wire 8 ?' val3[1] [7:0] $end $scope module i_sub0 $end $var wire 32 .( P0 [31:0] $end $var wire 32 /( P1 [31:0] $end $var wire 8 @' out[0] [7:0] $end $var wire 8 A' out[1] [7:0] $end $upscope $end $scope module i_sub1 $end $var wire 32 .( P0 [31:0] $end $var wire 32 /( P1 [31:0] $end $var wire 8 B' out[0] [7:0] $end $var wire 8 C' out[1] [7:0] $end $upscope $end $scope module i_sub2 $end $var wire 32 .( P0 [31:0] $end $var wire 32 /( P1 [31:0] $end $var wire 8 D' out[0] [7:0] $end $var wire 8 E' out[1] [7:0] $end $upscope $end $scope module i_sub3 $end $var wire 32 .( P0 [31:0] $end $var wire 32 0( P1 [31:0] $end $var wire 8 F' out[0] [7:0] $end $var wire 8 G' out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var wire 32 g' i [31:0] $end $scope module unnamedblk2 $end $var wire 32 h' j [31:0] $end $scope module unnamedblk3 $end $var wire 128 i' exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3.i_sub4_1.i_sub5 $end $var wire 1 g( clk $end $var wire 128 h( in[0][0] [127:0] $end $var wire 128 l( in[0][1] [127:0] $end $var wire 128 p( in[0][2] [127:0] $end $var wire 128 t( in[1][0] [127:0] $end $var wire 128 x( in[1][1] [127:0] $end $var wire 128 |( in[1][2] [127:0] $end $var wire 8 ") out[0][0] [7:0] $end $var wire 8 #) out[0][1] [7:0] $end $var wire 8 $) out[0][2] [7:0] $end $var wire 8 %) out[1][0] [7:0] $end $var wire 8 &) out[1][1] [7:0] $end $var wire 8 ') out[1][2] [7:0] $end $scope module sub5 $end $var wire 1 g( clk $end $var wire 128 B( in[0][0] [127:0] $end $var wire 128 F( in[0][1] [127:0] $end $var wire 128 J( in[0][2] [127:0] $end $var wire 128 N( in[1][0] [127:0] $end $var wire 128 R( in[1][1] [127:0] $end $var wire 128 V( in[1][2] [127:0] $end $var wire 8 Z( out[0][0] [7:0] $end $var wire 8 [( out[0][1] [7:0] $end $var wire 8 \( out[0][2] [7:0] $end $var wire 8 ]( out[1][0] [7:0] $end $var wire 8 ^( out[1][1] [7:0] $end $var wire 8 _( out[1][2] [7:0] $end $var wire 32 `( count [31:0] $end $var wire 8 2( val0[0] [7:0] $end $var wire 8 3( val0[1] [7:0] $end $var wire 8 4( val1[0] [7:0] $end $var wire 8 5( val1[1] [7:0] $end $var wire 8 6( val2[0] [7:0] $end $var wire 8 7( val2[1] [7:0] $end $var wire 8 8( val3[0] [7:0] $end $var wire 8 9( val3[1] [7:0] $end $scope module i_sub0 $end $var wire 32 () P0 [31:0] $end $var wire 32 )) P1 [31:0] $end $var wire 8 :( out[0] [7:0] $end $var wire 8 ;( out[1] [7:0] $end $upscope $end $scope module i_sub1 $end $var wire 32 () P0 [31:0] $end $var wire 32 )) P1 [31:0] $end $var wire 8 <( out[0] [7:0] $end $var wire 8 =( out[1] [7:0] $end $upscope $end $scope module i_sub2 $end $var wire 32 () P0 [31:0] $end $var wire 32 )) P1 [31:0] $end $var wire 8 >( out[0] [7:0] $end $var wire 8 ?( out[1] [7:0] $end $upscope $end $scope module i_sub3 $end $var wire 32 () P0 [31:0] $end $var wire 32 *) P1 [31:0] $end $var wire 8 @( out[0] [7:0] $end $var wire 8 A( out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var wire 32 a( i [31:0] $end $scope module unnamedblk2 $end $var wire 32 b( j [31:0] $end $scope module unnamedblk3 $end $var wire 128 c( exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3_2.i_sub4_0.i_sub5 $end $var wire 1 a) clk $end $var wire 128 b) in[0][0] [127:0] $end $var wire 128 f) in[0][1] [127:0] $end $var wire 128 j) in[0][2] [127:0] $end $var wire 128 n) in[1][0] [127:0] $end $var wire 128 r) in[1][1] [127:0] $end $var wire 128 v) in[1][2] [127:0] $end $var wire 8 z) out[0][0] [7:0] $end $var wire 8 {) out[0][1] [7:0] $end $var wire 8 |) out[0][2] [7:0] $end $var wire 8 }) out[1][0] [7:0] $end $var wire 8 ~) out[1][1] [7:0] $end $var wire 8 !* out[1][2] [7:0] $end $scope module sub5 $end $var wire 1 a) clk $end $var wire 128 <) in[0][0] [127:0] $end $var wire 128 @) in[0][1] [127:0] $end $var wire 128 D) in[0][2] [127:0] $end $var wire 128 H) in[1][0] [127:0] $end $var wire 128 L) in[1][1] [127:0] $end $var wire 128 P) in[1][2] [127:0] $end $var wire 8 T) out[0][0] [7:0] $end $var wire 8 U) out[0][1] [7:0] $end $var wire 8 V) out[0][2] [7:0] $end $var wire 8 W) out[1][0] [7:0] $end $var wire 8 X) out[1][1] [7:0] $end $var wire 8 Y) out[1][2] [7:0] $end $var wire 32 Z) count [31:0] $end $var wire 8 ,) val0[0] [7:0] $end $var wire 8 -) val0[1] [7:0] $end $var wire 8 .) val1[0] [7:0] $end $var wire 8 /) val1[1] [7:0] $end $var wire 8 0) val2[0] [7:0] $end $var wire 8 1) val2[1] [7:0] $end $var wire 8 2) val3[0] [7:0] $end $var wire 8 3) val3[1] [7:0] $end $scope module i_sub0 $end $var wire 32 "* P0 [31:0] $end $var wire 32 #* P1 [31:0] $end $var wire 8 4) out[0] [7:0] $end $var wire 8 5) out[1] [7:0] $end $upscope $end $scope module i_sub1 $end $var wire 32 "* P0 [31:0] $end $var wire 32 #* P1 [31:0] $end $var wire 8 6) out[0] [7:0] $end $var wire 8 7) out[1] [7:0] $end $upscope $end $scope module i_sub2 $end $var wire 32 "* P0 [31:0] $end $var wire 32 #* P1 [31:0] $end $var wire 8 8) out[0] [7:0] $end $var wire 8 9) out[1] [7:0] $end $upscope $end $scope module i_sub3 $end $var wire 32 "* P0 [31:0] $end $var wire 32 $* P1 [31:0] $end $var wire 8 :) out[0] [7:0] $end $var wire 8 ;) out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var wire 32 [) i [31:0] $end $scope module unnamedblk2 $end $var wire 32 \) j [31:0] $end $scope module unnamedblk3 $end $var wire 128 ]) exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3_2.i_sub4_1.i_sub5 $end $var wire 1 [* clk $end $var wire 128 \* in[0][0] [127:0] $end $var wire 128 `* in[0][1] [127:0] $end $var wire 128 d* in[0][2] [127:0] $end $var wire 128 h* in[1][0] [127:0] $end $var wire 128 l* in[1][1] [127:0] $end $var wire 128 p* in[1][2] [127:0] $end $var wire 8 t* out[0][0] [7:0] $end $var wire 8 u* out[0][1] [7:0] $end $var wire 8 v* out[0][2] [7:0] $end $var wire 8 w* out[1][0] [7:0] $end $var wire 8 x* out[1][1] [7:0] $end $var wire 8 y* out[1][2] [7:0] $end $scope module sub5 $end $var wire 1 [* clk $end $var wire 128 6* in[0][0] [127:0] $end $var wire 128 :* in[0][1] [127:0] $end $var wire 128 >* in[0][2] [127:0] $end $var wire 128 B* in[1][0] [127:0] $end $var wire 128 F* in[1][1] [127:0] $end $var wire 128 J* in[1][2] [127:0] $end $var wire 8 N* out[0][0] [7:0] $end $var wire 8 O* out[0][1] [7:0] $end $var wire 8 P* out[0][2] [7:0] $end $var wire 8 Q* out[1][0] [7:0] $end $var wire 8 R* out[1][1] [7:0] $end $var wire 8 S* out[1][2] [7:0] $end $var wire 32 T* count [31:0] $end $var wire 8 &* val0[0] [7:0] $end $var wire 8 '* val0[1] [7:0] $end $var wire 8 (* val1[0] [7:0] $end $var wire 8 )* val1[1] [7:0] $end $var wire 8 ** val2[0] [7:0] $end $var wire 8 +* val2[1] [7:0] $end $var wire 8 ,* val3[0] [7:0] $end $var wire 8 -* val3[1] [7:0] $end $scope module i_sub0 $end $var wire 32 z* P0 [31:0] $end $var wire 32 {* P1 [31:0] $end $var wire 8 .* out[0] [7:0] $end $var wire 8 /* out[1] [7:0] $end $upscope $end $scope module i_sub1 $end $var wire 32 z* P0 [31:0] $end $var wire 32 {* P1 [31:0] $end $var wire 8 0* out[0] [7:0] $end $var wire 8 1* out[1] [7:0] $end $upscope $end $scope module i_sub2 $end $var wire 32 z* P0 [31:0] $end $var wire 32 {* P1 [31:0] $end $var wire 8 2* out[0] [7:0] $end $var wire 8 3* out[1] [7:0] $end $upscope $end $scope module i_sub3 $end $var wire 32 z* P0 [31:0] $end $var wire 32 |* P1 [31:0] $end $var wire 8 4* out[0] [7:0] $end $var wire 8 5* out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var wire 32 U* i [31:0] $end $scope module unnamedblk2 $end $var wire 32 V* j [31:0] $end $scope module unnamedblk3 $end $var wire 128 W* exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 b00000000 # b00000000 $ b00000000 % b00000000000000000000000000000000 & b00000000 ' b00000000 ( b00000000 ) b00000000 * b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 / b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ? b00000000000000000000000000000000 C b00000000000000000000000000000000 D b00000000000000000000000000000000 E b00000000 F b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 G b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 [ b00000000000000000000000000000000 _ b00000000000000000000000000000000 ` b00000000000000000000000000000000 a b00000000 b b00000000 c b00000000 d b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y b00000000000000000000000000000000 } b00000000000000000000000000000000 ~ b00000000000000000000000000000000 !! b00000000 "! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 #! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7! b00000000000000000000000000000000 ;! b00000000000000000000000000000000 ! b00000000 ?! b00000000 @! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 A! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 E! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ?" b00000000 C" b00000000 D" b00000000 E" b00000000 F" b00000000 G" b00000000 H" b00000000 I" b00000000 J" b00000000 K" b00000000 L" b00000000 M" b00000000 N" b00000000 O" b00000000 P" b00000000 Q" b00000000 R" b00000000 S" b00000000 T" b00000000 U" b00000000 V" b00000000 W" b00000000 X" b00000000 Y" b00000000 Z" b00000000 [" b00000000 \" b00000000 ]" b00000000 ^" b00000000 _" b00000000 `" b00000000 a" b00000000 b" b00000000 c" b00000000 d" b00000000 e" b00000000 f" b00000000 g" b00000000 h" b00000000 i" b00000000 j" b00000000 k" b00000000 l" b00000000 m" b00000000 n" b00000000 o" b00000000 p" b00000000 q" b00000000 r" b00000000 s" b00000000 t" b00000000 u" 0v" 0.# b00000000 /# b00000000 0# b00000000 1# 03# b00000000 4# b00000000 5# b00000000 6# b00000001 8# b00000010 9# b00000001 :# b00000010 ;# b00000001 <# b00000010 =# b00000001 ># b00000011 ?# b00000001 @# b00000010 A# b00000001 B# b00000010 C# b00000001 D# b00000010 E# b00000001 F# b00000011 G# b00000001 H# b00000010 I# b00000001 J# b00000010 K# b00000001 L# b00000010 M# b00000001 N# b00000011 O# b00000001 P# b00000010 Q# b00000001 R# b00000010 S# b00000001 T# b00000010 U# b00000001 V# b00000011 W# b00000001 X# b00000010 Y# b00000001 Z# b00000010 [# b00000001 \# b00000010 ]# b00000001 ^# b00000011 _# b00000001 `# b00000010 a# b00000001 b# b00000010 c# b00000001 d# b00000010 e# b00000001 f# b00000011 g# b00000001 h# b00000010 i# b00000001 j# b00000010 k# b00000001 l# b00000010 m# b00000001 n# b00000011 o# b00000001 p# b00000010 q# b00000001 r# b00000010 s# b00000001 t# b00000010 u# b00000001 v# b00000011 w# b00000000 x# b00000000 y# b00000000 z# b00000000 {# b00000000 |# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 }# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 #$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3$ b00000000 7$ b00000000 8$ b00000000 9$ b00000000 :$ b00000000 ;$ b00000000 <$ b00000000000000000000000000000000 =$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 >$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R$ b00000000 V$ b00000000 W$ b00000000 X$ b00000000 Y$ b00000000 Z$ b00000000 [$ b00000000000000000000000000000000 \$ b00000000000000000000000000000000 ]$ b00000000000000000000000000000000 ^$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 _$ b00000000000000000000000000000000 c$ b00000000000000000000000000000000 d$ b00000000 e$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 f$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 j$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z$ b00000000 ~$ b00000000 !% b00000000 "% b00000000 #% b00000000 $% b00000000 %% b00000000000000000000000000000000 &% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;% b00000000 ?% b00000000 @% b00000000 A% b00000000 B% b00000000 C% b00000000 D% b00000000000000000000000000000000 E% b00000000000000000000000000000000 F% b00000000000000000000000000000000 G% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H% b00000000000000000000000000000000 L% b00000000000000000000000000000000 M% b00000000 N% b00000000 O% b00000000 P% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Q% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 U% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Y% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e% b00000000 i% b00000000 j% b00000000 k% b00000000 l% b00000000 m% b00000000 n% b00000000000000000000000000000000 o% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 && b00000000 *& b00000000 +& b00000000 ,& b00000000 -& b00000000 .& b00000000 /& b00000000000000000000000000000000 0& b00000000000000000000000000000000 1& b00000000000000000000000000000000 2& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3& b00000000000000000000000000000000 7& b00000000000000000000000000000000 8& b00000000 9& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 :& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 >& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N& b00000000 R& b00000000 S& b00000000 T& b00000000 U& b00000000 V& b00000000 W& b00000000000000000000000000000000 X& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Y& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m& b00000000 q& b00000000 r& b00000000 s& b00000000 t& b00000000 u& b00000000 v& b00000000000000000000000000000000 w& b00000000000000000000000000000000 x& b00000000000000000000000000000000 y& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z& b00000000000000000000000000000000 ~& b00000000000000000000000000000000 !' b00000000 "' 0#' b00000000 $' b00000000 %' b00000001 8' b00000010 9' b00000001 :' b00000010 ;' b00000001 <' b00000010 =' b00000001 >' b00000011 ?' b00000001 @' b00000010 A' b00000001 B' b00000010 C' b00000001 D' b00000010 E' b00000001 F' b00000011 G' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \' b00000000 `' b00000000 a' b00000000 b' b00000000 c' b00000000 d' b00000000 e' b00000000000000000000000000000000 f' b00000000000000000000000000000000 g' b00000000000000000000000000000000 h' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i' 0m' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $( b00000000 (( b00000000 )( b00000000 *( b00000000 +( b00000000 ,( b00000000 -( b00000001 2( b00000010 3( b00000001 4( b00000010 5( b00000001 6( b00000010 7( b00000001 8( b00000011 9( b00000001 :( b00000010 ;( b00000001 <( b00000010 =( b00000001 >( b00000010 ?( b00000001 @( b00000011 A( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V( b00000000 Z( b00000000 [( b00000000 \( b00000000 ]( b00000000 ^( b00000000 _( b00000000000000000000000000000000 `( b00000000000000000000000000000000 a( b00000000000000000000000000000000 b( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 c( 0g( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 h( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |( b00000000 ") b00000000 #) b00000000 $) b00000000 %) b00000000 &) b00000000 ') b00000001 ,) b00000010 -) b00000001 .) b00000010 /) b00000001 0) b00000010 1) b00000001 2) b00000011 3) b00000001 4) b00000010 5) b00000001 6) b00000010 7) b00000001 8) b00000010 9) b00000001 :) b00000011 ;) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 <) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 @) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 D) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P) b00000000 T) b00000000 U) b00000000 V) b00000000 W) b00000000 X) b00000000 Y) b00000000000000000000000000000000 Z) b00000000000000000000000000000000 [) b00000000000000000000000000000000 \) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]) 0a) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 b) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 f) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 j) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v) b00000000 z) b00000000 {) b00000000 |) b00000000 }) b00000000 ~) b00000000 !* b00000001 &* b00000010 '* b00000001 (* b00000010 )* b00000001 ** b00000010 +* b00000001 ,* b00000011 -* b00000001 .* b00000010 /* b00000001 0* b00000010 1* b00000001 2* b00000010 3* b00000001 4* b00000011 5* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 6* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 :* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 >* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J* b00000000 N* b00000000 O* b00000000 P* b00000000 Q* b00000000 R* b00000000 S* b00000000000000000000000000000000 T* b00000000000000000000000000000000 U* b00000000000000000000000000000000 V* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W* 0[* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 `* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 d* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p* b00000000 t* b00000000 u* b00000000 v* b00000000 w* b00000000 x* b00000000 y* b00000000000000000000000000100001 w" b00000000000000000000000000101100 x" b00000000000000000000000000000010 y" b00000000000000000000000000001000 z" b00000000000000000000000000000001 {" b00000000000000000000000000000011 |" b00000001 }" b00000000000000000000000000000000 ~" b00000000000000000000000000000001 !# b1111111111111101 "# b00 ## b00000000000000000000000000000010 $# r3.1 %# r4.1 '# r5 )# b00000000000000000000000000000000 +# b00000000000000000000000000000001 ,# b00000011 &' b00000000000000000000000000000000 '' b00000000000000000000000000000001 (' b1111111111111101 )' b11 *' b00000000000000000000000000000010 +' r3.1 ,' r4.1 .' b00000000000000000000000000000001 0' b00000000000000000000000000000010 1' b00000000000000000000000000000011 2' r5 3' b00000000000000000000000000000000 5' b00000000000000000000000000000001 6' b00000000000000000000000000000001 .( b00000000000000000000000000000010 /( b00000000000000000000000000000011 0( b00000000000000000000000000000001 () b00000000000000000000000000000010 )) b00000000000000000000000000000011 *) b00000000000000000000000000000001 "* b00000000000000000000000000000010 #* b00000000000000000000000000000011 $* b00000000000000000000000000000001 z* b00000000000000000000000000000010 {* b00000000000000000000000000000011 |* #10 b00000010 # b00000000000000000000000000000001 & b00000010 * b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 / b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ? b00000000000000000000000000000001 C b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 [ b00000000000000000000000000000001 _ b00000001 c b00000010 d b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 y b00000000000000000000000000000001 } b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 '! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 7! b00000000000000000000000000000001 ;! b00000010 ?! b00000001 @! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 E! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 u! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 /" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ?" b00000001 D" b00000010 E" 1v" 1.# b00000010 /# 13# b00000001 5# b00000001 6# b00000010 x# b00000010 y# b00000010 z# b00000011 {# b00000010 |# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 #$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 '$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 3$ b00000000000000000000000000000001 =$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 B$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 F$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 R$ b00000000000000000000000000000001 \$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 j$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 n$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 z$ b00000000000000000000000000000001 &% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 +% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 /% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;% b00000000000000000000000000000001 E% b00000011 O% b00000010 P% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 U% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 Y% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 e% b00000000000000000000000000000001 o% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 t% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 x% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 && b00000000000000000000000000000001 0& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 >& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 B& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 N& b00000000000000000000000000000001 X& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m& b00000000000000000000000000000001 w& 1#' b00000001 $' b00000010 %' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 L' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 P' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 \' b00000000000000000000000000000001 f' 1m' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 r' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 v' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 $( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 F( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 J( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 V( b00000000000000000000000000000001 `( 1g( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 l( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 p( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 |( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 @) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 D) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 P) b00000000000000000000000000000001 Z) 1a) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 f) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 j) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 v) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 :* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 >* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 J* b00000000000000000000000000000001 T* 1[* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 `* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 d* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 p* #15 0v" 0.# 03# 0#' 0m' 0g( 0a) 0[* #20 b00000011 # b00000000000000000000000000000010 & b00000010 ' b00000011 * b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 / b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ? b00000000000000000000000000000010 C b00000000000000000000000000000010 D b00000000000000000000000000000011 E b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 [ b00000000000000000000000000000010 _ b00000000000000000000000000000010 ` b00000000000000000000000000000011 a b00000011 c b00000011 d b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y b00000000000000000000000000000010 } b00000000000000000000000000000010 ~ b00000000000000000000000000000011 !! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7! b00000000000000000000000000000010 ;! b00000000000000000000000000000010 & b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N& b00000110 R& b00000101 S& b00000100 T& b00000011 U& b00000010 V& b00000001 W& b00000000000000000000000000000010 X& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m& b00000110 q& b00000101 r& b00000100 s& b00000011 t& b00000010 u& b00000001 v& b00000000000000000000000000000010 w& b00000000000000000000000000000010 x& b00000000000000000000000000000011 y& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 z& b00000000000000000000000000000010 ~& b00000000000000000000000000000011 !' 1#' b00000101 %' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \' b00000110 `' b00000101 a' b00000100 b' b00000011 c' b00000010 d' b00000001 e' b00000000000000000000000000000010 f' b00000000000000000000000000000010 g' b00000000000000000000000000000011 h' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 i' 1m' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $( b00000110 (( b00000101 )( b00000100 *( b00000011 +( b00000010 ,( b00000001 -( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V( b00000110 Z( b00000101 [( b00000100 \( b00000011 ]( b00000010 ^( b00000001 _( b00000000000000000000000000000010 `( b00000000000000000000000000000010 a( b00000000000000000000000000000011 b( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 c( 1g( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |( b00000110 ") b00000101 #) b00000100 $) b00000011 %) b00000010 &) b00000001 ') b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 @) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 D) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P) b00000110 T) b00000101 U) b00000100 V) b00000011 W) b00000010 X) b00000001 Y) b00000000000000000000000000000010 Z) b00000000000000000000000000000010 [) b00000000000000000000000000000011 \) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ]) 1a) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 f) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 j) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v) b00000110 z) b00000101 {) b00000100 |) b00000011 }) b00000010 ~) b00000001 !* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 :* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 >* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J* b00000110 N* b00000101 O* b00000100 P* b00000011 Q* b00000010 R* b00000001 S* b00000000000000000000000000000010 T* b00000000000000000000000000000010 U* b00000000000000000000000000000011 V* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 W* 1[* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 `* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 d* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p* b00000110 t* b00000101 u* b00000100 v* b00000011 w* b00000010 x* b00000001 y* #25 0v" 0.# 03# 0#' 0m' 0g( 0a) 0[* #30 b00000101 # b00000010 $ b00000000000000000000000000000011 & b00000011 ' b00000101 * b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 / b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ? b00000000000000000000000000000011 C b00000001 F b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 [ b00000000000000000000000000000011 _ b00000001 b b00000110 c b00000101 d b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 y b00000000000000000000000000000011 } b00000001 "! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 '! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 7! b00000000000000000000000000000011 ;! b00000001 >! b00000101 ?! b00000110 @! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 E! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 u! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 /" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ?" b00000011 C" b00000011 D" b00000111 E" b00000000 F" b00000000 G" b00000000 H" b00000000 I" b00000000 J" b00000000 K" b00000000 L" b00000000 M" b00000000 N" b00000000 O" b00000000 P" b00000000 Q" b00000000 R" b00000000 S" b00000000 T" b00000000 U" b00000000 V" b00000000 W" b00000000 X" b00000000 Y" b00000000 Z" b00000000 [" b00000000 \" b00000000 ]" b00000000 ^" b00000000 _" b00000000 `" b00000000 a" b00000000 b" b00000000 c" b00000000 d" b00000000 e" b00000000 f" b00000000 g" b00000000 h" b00000000 i" b00000000 j" b00000000 k" b00000000 l" b00000000 m" b00000000 n" b00000000 o" b00000000 p" b00000000 q" b00000000 r" b00000000 s" b00000000 t" b00000000 u" 1v" 1.# b00000101 /# b00000011 0# b00000011 1# 13# b00000011 4# b00000011 5# b00000011 6# b00000111 y# b00000111 z# b00000110 {# b00000111 |# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 #$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 '$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 3$ b00000000 7$ b00000000 8$ b00000000 9$ b00000000 :$ b00000000 ;$ b00000000 <$ b00000000000000000000000000000011 =$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 B$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 F$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 R$ b00000000 V$ b00000000 W$ b00000000 X$ b00000000 Y$ b00000000 Z$ b00000000 [$ b00000000000000000000000000000011 \$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 _$ b00000001 e$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 j$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 n$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 z$ b00000000 ~$ b00000000 !% b00000000 "% b00000000 #% b00000000 $% b00000000 %% b00000000000000000000000000000011 &% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 +% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 /% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;% b00000000 ?% b00000000 @% b00000000 A% b00000000 B% b00000000 C% b00000000 D% b00000000000000000000000000000011 E% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H% b00000001 N% b00000110 O% b00000111 P% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 U% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 Y% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 e% b00000000 i% b00000000 j% b00000000 k% b00000000 l% b00000000 m% b00000000 n% b00000000000000000000000000000011 o% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 t% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 x% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 && b00000000 *& b00000000 +& b00000000 ,& b00000000 -& b00000000 .& b00000000 /& b00000000000000000000000000000011 0& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3& b00000001 9& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 >& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 B& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 N& b00000000 R& b00000000 S& b00000000 T& b00000000 U& b00000000 V& b00000000 W& b00000000000000000000000000000011 X& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m& b00000000 q& b00000000 r& b00000000 s& b00000000 t& b00000000 u& b00000000 v& b00000000000000000000000000000011 w& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z& b00000001 "' 1#' b00000011 $' b00000111 %' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 L' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 P' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 \' b00000000 `' b00000000 a' b00000000 b' b00000000 c' b00000000 d' b00000000 e' b00000000000000000000000000000011 f' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i' 1m' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 r' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 v' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 $( b00000000 (( b00000000 )( b00000000 *( b00000000 +( b00000000 ,( b00000000 -( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 F( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 J( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 V( b00000000 Z( b00000000 [( b00000000 \( b00000000 ]( b00000000 ^( b00000000 _( b00000000000000000000000000000011 `( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 c( 1g( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 l( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 p( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 |( b00000000 ") b00000000 #) b00000000 $) b00000000 %) b00000000 &) b00000000 ') b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 @) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 D) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 P) b00000000 T) b00000000 U) b00000000 V) b00000000 W) b00000000 X) b00000000 Y) b00000000000000000000000000000011 Z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]) 1a) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 f) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 j) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 v) b00000000 z) b00000000 {) b00000000 |) b00000000 }) b00000000 ~) b00000000 !* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 :* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 >* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 J* b00000000 N* b00000000 O* b00000000 P* b00000000 Q* b00000000 R* b00000000 S* b00000000000000000000000000000011 T* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W* 1[* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 `* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 d* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 p* b00000000 t* b00000000 u* b00000000 v* b00000000 w* b00000000 x* b00000000 y* #35 0v" 0.# 03# 0#' 0m' 0g( 0a) 0[* #40 b00001000 # b00000011 $ b00000000000000000000000000000100 & b00000101 ' b00000010 ( b00001000 * b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 / b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ? b00000000000000000000000000000100 C b00000000 F b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 [ b00000000000000000000000000000100 _ b00000000 b b00001000 c b00001000 d b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y b00000000000000000000000000000100 } b00000000 "! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7! b00000000000000000000000000000100 ;! b00000000 >! b00001000 ?! b00001000 @! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 E! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ?" b00000101 C" b00000100 D" b00001000 E" b00000110 F" b00000101 G" b00000100 H" b00000011 I" b00000010 J" b00000001 K" b00000110 L" b00000101 M" b00000100 N" b00000011 O" b00000010 P" b00000001 Q" b00000110 R" b00000101 S" b00000100 T" b00000011 U" b00000010 V" b00000001 W" b00000110 X" b00000101 Y" b00000100 Z" b00000011 [" b00000010 \" b00000001 ]" b00000110 ^" b00000101 _" b00000100 `" b00000011 a" b00000010 b" b00000001 c" b00000110 d" b00000101 e" b00000100 f" b00000011 g" b00000010 h" b00000001 i" b00000110 j" b00000101 k" b00000100 l" b00000011 m" b00000010 n" b00000001 o" b00000110 p" b00000101 q" b00000100 r" b00000011 s" b00000010 t" b00000001 u" 1v" 1.# b00001000 /# b00000101 0# b00000101 1# 13# b00000101 4# b00000100 5# b00000100 6# b00000101 x# b00001000 y# b00001000 z# b00001000 |# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 #$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3$ b00000110 7$ b00000101 8$ b00000100 9$ b00000011 :$ b00000010 ;$ b00000001 <$ b00000000000000000000000000000100 =$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R$ b00000110 V$ b00000101 W$ b00000100 X$ b00000011 Y$ b00000010 Z$ b00000001 [$ b00000000000000000000000000000100 \$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _$ b00000000 e$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 j$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z$ b00000110 ~$ b00000101 !% b00000100 "% b00000011 #% b00000010 $% b00000001 %% b00000000000000000000000000000100 &% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;% b00000110 ?% b00000101 @% b00000100 A% b00000011 B% b00000010 C% b00000001 D% b00000000000000000000000000000100 E% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 H% b00000000 N% b00001000 P% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 U% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Y% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e% b00000110 i% b00000101 j% b00000100 k% b00000011 l% b00000010 m% b00000001 n% b00000000000000000000000000000100 o% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 && b00000110 *& b00000101 +& b00000100 ,& b00000011 -& b00000010 .& b00000001 /& b00000000000000000000000000000100 0& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 3& b00000000 9& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 >& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N& b00000110 R& b00000101 S& b00000100 T& b00000011 U& b00000010 V& b00000001 W& b00000000000000000000000000000100 X& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m& b00000110 q& b00000101 r& b00000100 s& b00000011 t& b00000010 u& b00000001 v& b00000000000000000000000000000100 w& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 z& b00000000 "' 1#' b00000100 $' b00001000 %' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \' b00000110 `' b00000101 a' b00000100 b' b00000011 c' b00000010 d' b00000001 e' b00000000000000000000000000000100 f' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 i' 1m' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $( b00000110 (( b00000101 )( b00000100 *( b00000011 +( b00000010 ,( b00000001 -( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V( b00000110 Z( b00000101 [( b00000100 \( b00000011 ]( b00000010 ^( b00000001 _( b00000000000000000000000000000100 `( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 c( 1g( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |( b00000110 ") b00000101 #) b00000100 $) b00000011 %) b00000010 &) b00000001 ') b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 @) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 D) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P) b00000110 T) b00000101 U) b00000100 V) b00000011 W) b00000010 X) b00000001 Y) b00000000000000000000000000000100 Z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ]) 1a) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 f) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 j) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v) b00000110 z) b00000101 {) b00000100 |) b00000011 }) b00000010 ~) b00000001 !* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 :* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 >* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J* b00000110 N* b00000101 O* b00000100 P* b00000011 Q* b00000010 R* b00000001 S* b00000000000000000000000000000100 T* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 W* 1[* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 `* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 d* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p* b00000110 t* b00000101 u* b00000100 v* b00000011 w* b00000010 x* b00000001 y* #45 0v" 0.# 03# 0#' 0m' 0g( 0a) 0[* #50 b00001010 # b00000101 $ b00000000000000000000000000000101 & b00001000 ' b00000011 ( b00000010 ) b00001010 * b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 / b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ? b00000000000000000000000000000101 C b00000001 F b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 [ b00000000000000000000000000000101 _ b00000001 b b00001001 c b00001010 d b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 y b00000000000000000000000000000101 } b00000001 "! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 '! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 7! b00000000000000000000000000000101 ;! b00000001 >! b00001010 ?! b00001001 @! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 E! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 u! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 /" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ?" b00001000 C" b00000110 D" b00000000 F" b00000000 G" b00000000 H" b00000000 I" b00000000 J" b00000000 K" b00000000 L" b00000000 M" b00000000 N" b00000000 O" b00000000 P" b00000000 Q" b00000000 R" b00000000 S" b00000000 T" b00000000 U" b00000000 V" b00000000 W" b00000000 X" b00000000 Y" b00000000 Z" b00000000 [" b00000000 \" b00000000 ]" b00000000 ^" b00000000 _" b00000000 `" b00000000 a" b00000000 b" b00000000 c" b00000000 d" b00000000 e" b00000000 f" b00000000 g" b00000000 h" b00000000 i" b00000000 j" b00000000 k" b00000000 l" b00000000 m" b00000000 n" b00000000 o" b00000000 p" b00000000 q" b00000000 r" b00000000 s" b00000000 t" b00000000 u" 1v" 1.# b00001010 /# b00001000 0# b00001000 1# 13# b00001000 4# b00000110 5# b00000110 6# b00000110 x# b00001000 {# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 #$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 '$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 3$ b00000000 7$ b00000000 8$ b00000000 9$ b00000000 :$ b00000000 ;$ b00000000 <$ b00000000000000000000000000000101 =$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 B$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 F$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 R$ b00000000 V$ b00000000 W$ b00000000 X$ b00000000 Y$ b00000000 Z$ b00000000 [$ b00000000000000000000000000000101 \$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 _$ b00000001 e$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 j$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 n$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 z$ b00000000 ~$ b00000000 !% b00000000 "% b00000000 #% b00000000 $% b00000000 %% b00000000000000000000000000000101 &% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 +% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 /% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;% b00000000 ?% b00000000 @% b00000000 A% b00000000 B% b00000000 C% b00000000 D% b00000000000000000000000000000101 E% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H% b00000001 N% b00001000 O% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 U% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 Y% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 e% b00000000 i% b00000000 j% b00000000 k% b00000000 l% b00000000 m% b00000000 n% b00000000000000000000000000000101 o% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 t% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 x% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 && b00000000 *& b00000000 +& b00000000 ,& b00000000 -& b00000000 .& b00000000 /& b00000000000000000000000000000101 0& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3& b00000001 9& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 >& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 B& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 N& b00000000 R& b00000000 S& b00000000 T& b00000000 U& b00000000 V& b00000000 W& b00000000000000000000000000000101 X& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m& b00000000 q& b00000000 r& b00000000 s& b00000000 t& b00000000 u& b00000000 v& b00000000000000000000000000000101 w& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z& b00000001 "' 1#' b00000110 $' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 L' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 P' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 \' b00000000 `' b00000000 a' b00000000 b' b00000000 c' b00000000 d' b00000000 e' b00000000000000000000000000000101 f' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i' 1m' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 r' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 v' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 $( b00000000 (( b00000000 )( b00000000 *( b00000000 +( b00000000 ,( b00000000 -( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 F( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 J( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 V( b00000000 Z( b00000000 [( b00000000 \( b00000000 ]( b00000000 ^( b00000000 _( b00000000000000000000000000000101 `( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 c( 1g( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 l( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 p( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 |( b00000000 ") b00000000 #) b00000000 $) b00000000 %) b00000000 &) b00000000 ') b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 @) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 D) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 P) b00000000 T) b00000000 U) b00000000 V) b00000000 W) b00000000 X) b00000000 Y) b00000000000000000000000000000101 Z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]) 1a) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 f) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 j) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 v) b00000000 z) b00000000 {) b00000000 |) b00000000 }) b00000000 ~) b00000000 !* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 :* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 >* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 J* b00000000 N* b00000000 O* b00000000 P* b00000000 Q* b00000000 R* b00000000 S* b00000000000000000000000000000101 T* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W* 1[* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 `* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 d* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 p* b00000000 t* b00000000 u* b00000000 v* b00000000 w* b00000000 x* b00000000 y* #55 0v" 0.# 03# 0#' 0m' 0g( 0a) 0[* #60 b00001011 # b00001000 $ b00000010 % b00000000000000000000000000000110 & b00001010 ' b00000101 ( b00000011 ) b00001011 * b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 / b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ? b00000000000000000000000000000110 C b00000000 F b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 [ b00000000000000000000000000000110 _ b00000000 b b00001011 d b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y b00000000000000000000000000000110 } b00000000 "! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7! b00000000000000000000000000000110 ;! b00000000 >! b00001011 ?! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 E! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ?" b00001010 C" b00001001 D" b00001010 E" b00000110 F" b00000101 G" b00000100 H" b00000011 I" b00000010 J" b00000001 K" b00000110 L" b00000101 M" b00000100 N" b00000011 O" b00000010 P" b00000001 Q" b00000110 R" b00000101 S" b00000100 T" b00000011 U" b00000010 V" b00000001 W" b00000110 X" b00000101 Y" b00000100 Z" b00000011 [" b00000010 \" b00000001 ]" b00000110 ^" b00000101 _" b00000100 `" b00000011 a" b00000010 b" b00000001 c" b00000110 d" b00000101 e" b00000100 f" b00000011 g" b00000010 h" b00000001 i" b00000110 j" b00000101 k" b00000100 l" b00000011 m" b00000010 n" b00000001 o" b00000110 p" b00000101 q" b00000100 r" b00000011 s" b00000010 t" b00000001 u" 1v" 1.# b00001011 /# b00001010 0# b00001010 1# 13# b00001010 4# b00001001 5# b00001001 6# b00001000 x# b00001010 y# b00001010 z# b00001001 {# b00001010 |# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 #$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3$ b00000110 7$ b00000101 8$ b00000100 9$ b00000011 :$ b00000010 ;$ b00000001 <$ b00000000000000000000000000000110 =$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R$ b00000110 V$ b00000101 W$ b00000100 X$ b00000011 Y$ b00000010 Z$ b00000001 [$ b00000000000000000000000000000110 \$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _$ b00000000 e$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 j$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z$ b00000110 ~$ b00000101 !% b00000100 "% b00000011 #% b00000010 $% b00000001 %% b00000000000000000000000000000110 &% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;% b00000110 ?% b00000101 @% b00000100 A% b00000011 B% b00000010 C% b00000001 D% b00000000000000000000000000000110 E% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 H% b00000000 N% b00001001 O% b00001010 P% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 U% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Y% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e% b00000110 i% b00000101 j% b00000100 k% b00000011 l% b00000010 m% b00000001 n% b00000000000000000000000000000110 o% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 && b00000110 *& b00000101 +& b00000100 ,& b00000011 -& b00000010 .& b00000001 /& b00000000000000000000000000000110 0& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 3& b00000000 9& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 >& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N& b00000110 R& b00000101 S& b00000100 T& b00000011 U& b00000010 V& b00000001 W& b00000000000000000000000000000110 X& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m& b00000110 q& b00000101 r& b00000100 s& b00000011 t& b00000010 u& b00000001 v& b00000000000000000000000000000110 w& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 z& b00000000 "' 1#' b00001001 $' b00001010 %' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \' b00000110 `' b00000101 a' b00000100 b' b00000011 c' b00000010 d' b00000001 e' b00000000000000000000000000000110 f' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 i' 1m' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $( b00000110 (( b00000101 )( b00000100 *( b00000011 +( b00000010 ,( b00000001 -( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V( b00000110 Z( b00000101 [( b00000100 \( b00000011 ]( b00000010 ^( b00000001 _( b00000000000000000000000000000110 `( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 c( 1g( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |( b00000110 ") b00000101 #) b00000100 $) b00000011 %) b00000010 &) b00000001 ') b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 @) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 D) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P) b00000110 T) b00000101 U) b00000100 V) b00000011 W) b00000010 X) b00000001 Y) b00000000000000000000000000000110 Z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ]) 1a) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 f) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 j) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v) b00000110 z) b00000101 {) b00000100 |) b00000011 }) b00000010 ~) b00000001 !* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 :* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 >* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J* b00000110 N* b00000101 O* b00000100 P* b00000011 Q* b00000010 R* b00000001 S* b00000000000000000000000000000110 T* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 W* 1[* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 `* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 d* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p* b00000110 t* b00000101 u* b00000100 v* b00000011 w* b00000010 x* b00000001 y* #65 0v" 0.# 03# 0#' 0m' 0g( 0a) 0[* #70 b00001010 $ b00000011 % b00000000000000000000000000000111 & b00001011 ' b00001000 ( b00000101 ) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 / b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ? b00000000000000000000000000000111 C b00000001 F b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 [ b00000000000000000000000000000111 _ b00000001 b b00001011 c b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 y b00000000000000000000000000000111 } b00000001 "! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 '! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 7! b00000000000000000000000000000111 ;! b00000001 >! b00001011 @! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 E! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 u! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 /" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ?" b00001011 C" b00001011 D" b00001011 E" b00000000 F" b00000000 G" b00000000 H" b00000000 I" b00000000 J" b00000000 K" b00000000 L" b00000000 M" b00000000 N" b00000000 O" b00000000 P" b00000000 Q" b00000000 R" b00000000 S" b00000000 T" b00000000 U" b00000000 V" b00000000 W" b00000000 X" b00000000 Y" b00000000 Z" b00000000 [" b00000000 \" b00000000 ]" b00000000 ^" b00000000 _" b00000000 `" b00000000 a" b00000000 b" b00000000 c" b00000000 d" b00000000 e" b00000000 f" b00000000 g" b00000000 h" b00000000 i" b00000000 j" b00000000 k" b00000000 l" b00000000 m" b00000000 n" b00000000 o" b00000000 p" b00000000 q" b00000000 r" b00000000 s" b00000000 t" b00000000 u" 1v" 1.# b00001011 0# b00001011 1# 13# b00001011 4# b00001011 5# b00001011 6# b00001011 x# b00001011 y# b00001011 z# b00001011 {# b00001011 |# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 #$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 '$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 3$ b00000000 7$ b00000000 8$ b00000000 9$ b00000000 :$ b00000000 ;$ b00000000 <$ b00000000000000000000000000000111 =$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 B$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 F$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 R$ b00000000 V$ b00000000 W$ b00000000 X$ b00000000 Y$ b00000000 Z$ b00000000 [$ b00000000000000000000000000000111 \$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 _$ b00000001 e$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 j$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 n$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 z$ b00000000 ~$ b00000000 !% b00000000 "% b00000000 #% b00000000 $% b00000000 %% b00000000000000000000000000000111 &% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 +% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 /% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;% b00000000 ?% b00000000 @% b00000000 A% b00000000 B% b00000000 C% b00000000 D% b00000000000000000000000000000111 E% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H% b00000001 N% b00001011 O% b00001011 P% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 U% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 Y% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 e% b00000000 i% b00000000 j% b00000000 k% b00000000 l% b00000000 m% b00000000 n% b00000000000000000000000000000111 o% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 t% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 x% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 && b00000000 *& b00000000 +& b00000000 ,& b00000000 -& b00000000 .& b00000000 /& b00000000000000000000000000000111 0& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3& b00000001 9& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 >& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 B& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 N& b00000000 R& b00000000 S& b00000000 T& b00000000 U& b00000000 V& b00000000 W& b00000000000000000000000000000111 X& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m& b00000000 q& b00000000 r& b00000000 s& b00000000 t& b00000000 u& b00000000 v& b00000000000000000000000000000111 w& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z& b00000001 "' 1#' b00001011 $' b00001011 %' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 L' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 P' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 \' b00000000 `' b00000000 a' b00000000 b' b00000000 c' b00000000 d' b00000000 e' b00000000000000000000000000000111 f' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i' 1m' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 r' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 v' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 $( b00000000 (( b00000000 )( b00000000 *( b00000000 +( b00000000 ,( b00000000 -( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 F( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 J( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 V( b00000000 Z( b00000000 [( b00000000 \( b00000000 ]( b00000000 ^( b00000000 _( b00000000000000000000000000000111 `( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 c( 1g( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 l( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 p( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 |( b00000000 ") b00000000 #) b00000000 $) b00000000 %) b00000000 &) b00000000 ') b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 @) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 D) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 P) b00000000 T) b00000000 U) b00000000 V) b00000000 W) b00000000 X) b00000000 Y) b00000000000000000000000000000111 Z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]) 1a) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 f) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 j) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 v) b00000000 z) b00000000 {) b00000000 |) b00000000 }) b00000000 ~) b00000000 !* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 :* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 >* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 J* b00000000 N* b00000000 O* b00000000 P* b00000000 Q* b00000000 R* b00000000 S* b00000000000000000000000000000111 T* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W* 1[* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 `* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 d* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 p* b00000000 t* b00000000 u* b00000000 v* b00000000 w* b00000000 x* b00000000 y* #75 0v" 0.# 03# 0#' 0m' 0g( 0a) 0[* #80 b00001101 # b00001011 $ b00000101 % b00000000000000000000000000001000 & b00001010 ( b00001000 ) b00001101 * b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 / b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ? b00000000000000000000000000001000 C b00000000 F b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 [ b00000000000000000000000000001000 _ b00000000 b b00001100 c b00001101 d b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y b00000000000000000000000000001000 } b00000000 "! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7! b00000000000000000000000000001000 ;! b00000000 >! b00001101 ?! b00001100 @! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 E! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ?" b00001100 D" b00001101 E" b00000110 F" b00000101 G" b00000100 H" b00000011 I" b00000010 J" b00000001 K" b00000110 L" b00000101 M" b00000100 N" b00000011 O" b00000010 P" b00000001 Q" b00000110 R" b00000101 S" b00000100 T" b00000011 U" b00000010 V" b00000001 W" b00000110 X" b00000101 Y" b00000100 Z" b00000011 [" b00000010 \" b00000001 ]" b00000110 ^" b00000101 _" b00000100 `" b00000011 a" b00000010 b" b00000001 c" b00000110 d" b00000101 e" b00000100 f" b00000011 g" b00000010 h" b00000001 i" b00000110 j" b00000101 k" b00000100 l" b00000011 m" b00000010 n" b00000001 o" b00000110 p" b00000101 q" b00000100 r" b00000011 s" b00000010 t" b00000001 u" 1v" 1.# b00001101 /# 13# b00001100 5# b00001100 6# b00001101 x# b00001101 y# b00001101 z# b00001110 {# b00001101 |# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 #$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3$ b00000110 7$ b00000101 8$ b00000100 9$ b00000011 :$ b00000010 ;$ b00000001 <$ b00000000000000000000000000001000 =$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R$ b00000110 V$ b00000101 W$ b00000100 X$ b00000011 Y$ b00000010 Z$ b00000001 [$ b00000000000000000000000000001000 \$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _$ b00000000 e$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 j$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z$ b00000110 ~$ b00000101 !% b00000100 "% b00000011 #% b00000010 $% b00000001 %% b00000000000000000000000000001000 &% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;% b00000110 ?% b00000101 @% b00000100 A% b00000011 B% b00000010 C% b00000001 D% b00000000000000000000000000001000 E% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 H% b00000000 N% b00001110 O% b00001101 P% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 U% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Y% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e% b00000110 i% b00000101 j% b00000100 k% b00000011 l% b00000010 m% b00000001 n% b00000000000000000000000000001000 o% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 && b00000110 *& b00000101 +& b00000100 ,& b00000011 -& b00000010 .& b00000001 /& b00000000000000000000000000001000 0& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 3& b00000000 9& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 >& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N& b00000110 R& b00000101 S& b00000100 T& b00000011 U& b00000010 V& b00000001 W& b00000000000000000000000000001000 X& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m& b00000110 q& b00000101 r& b00000100 s& b00000011 t& b00000010 u& b00000001 v& b00000000000000000000000000001000 w& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 z& b00000000 "' 1#' b00001100 $' b00001101 %' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \' b00000110 `' b00000101 a' b00000100 b' b00000011 c' b00000010 d' b00000001 e' b00000000000000000000000000001000 f' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 i' 1m' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $( b00000110 (( b00000101 )( b00000100 *( b00000011 +( b00000010 ,( b00000001 -( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V( b00000110 Z( b00000101 [( b00000100 \( b00000011 ]( b00000010 ^( b00000001 _( b00000000000000000000000000001000 `( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 c( 1g( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |( b00000110 ") b00000101 #) b00000100 $) b00000011 %) b00000010 &) b00000001 ') b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 @) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 D) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P) b00000110 T) b00000101 U) b00000100 V) b00000011 W) b00000010 X) b00000001 Y) b00000000000000000000000000001000 Z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ]) 1a) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 f) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 j) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v) b00000110 z) b00000101 {) b00000100 |) b00000011 }) b00000010 ~) b00000001 !* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 :* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 >* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J* b00000110 N* b00000101 O* b00000100 P* b00000011 Q* b00000010 R* b00000001 S* b00000000000000000000000000001000 T* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 W* 1[* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 `* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 d* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p* b00000110 t* b00000101 u* b00000100 v* b00000011 w* b00000010 x* b00000001 y* #85 0v" 0.# 03# 0#' 0m' 0g( 0a) 0[* #90 b00001110 # b00001000 % b00000000000000000000000000001001 & b00001101 ' b00001011 ( b00001010 ) b00001110 * b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 / b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ? b00000000000000000000000000001001 C b00000001 F b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 [ b00000000000000000000000000001001 _ b00000001 b b00001110 c b00001110 d b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 y b00000000000000000000000000001001 } b00000001 "! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 '! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 7! b00000000000000000000000000001001 ;! b00000001 >! b00001110 ?! b00001110 @! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 E! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 u! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 /" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ?" b00001101 C" b00010000 E" b00000000 F" b00000000 G" b00000000 H" b00000000 I" b00000000 J" b00000000 K" b00000000 L" b00000000 M" b00000000 N" b00000000 O" b00000000 P" b00000000 Q" b00000000 R" b00000000 S" b00000000 T" b00000000 U" b00000000 V" b00000000 W" b00000000 X" b00000000 Y" b00000000 Z" b00000000 [" b00000000 \" b00000000 ]" b00000000 ^" b00000000 _" b00000000 `" b00000000 a" b00000000 b" b00000000 c" b00000000 d" b00000000 e" b00000000 f" b00000000 g" b00000000 h" b00000000 i" b00000000 j" b00000000 k" b00000000 l" b00000000 m" b00000000 n" b00000000 o" b00000000 p" b00000000 q" b00000000 r" b00000000 s" b00000000 t" b00000000 u" 1v" 1.# b00001110 /# b00001101 0# b00001101 1# 13# b00001101 4# b00001110 x# b00010000 y# b00010000 z# b00010000 {# b00010000 |# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 #$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 '$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 3$ b00000000 7$ b00000000 8$ b00000000 9$ b00000000 :$ b00000000 ;$ b00000000 <$ b00000000000000000000000000001001 =$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 B$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 F$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 R$ b00000000 V$ b00000000 W$ b00000000 X$ b00000000 Y$ b00000000 Z$ b00000000 [$ b00000000000000000000000000001001 \$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 _$ b00000001 e$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 j$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 n$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 z$ b00000000 ~$ b00000000 !% b00000000 "% b00000000 #% b00000000 $% b00000000 %% b00000000000000000000000000001001 &% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 +% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 /% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;% b00000000 ?% b00000000 @% b00000000 A% b00000000 B% b00000000 C% b00000000 D% b00000000000000000000000000001001 E% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H% b00000001 N% b00010000 O% b00010000 P% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 U% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 Y% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 e% b00000000 i% b00000000 j% b00000000 k% b00000000 l% b00000000 m% b00000000 n% b00000000000000000000000000001001 o% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 t% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 x% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 && b00000000 *& b00000000 +& b00000000 ,& b00000000 -& b00000000 .& b00000000 /& b00000000000000000000000000001001 0& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3& b00000001 9& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 >& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 B& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 N& b00000000 R& b00000000 S& b00000000 T& b00000000 U& b00000000 V& b00000000 W& b00000000000000000000000000001001 X& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m& b00000000 q& b00000000 r& b00000000 s& b00000000 t& b00000000 u& b00000000 v& b00000000000000000000000000001001 w& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z& b00000001 "' 1#' b00010000 %' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 L' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 P' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 \' b00000000 `' b00000000 a' b00000000 b' b00000000 c' b00000000 d' b00000000 e' b00000000000000000000000000001001 f' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i' 1m' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 r' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 v' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 $( b00000000 (( b00000000 )( b00000000 *( b00000000 +( b00000000 ,( b00000000 -( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 F( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 J( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 V( b00000000 Z( b00000000 [( b00000000 \( b00000000 ]( b00000000 ^( b00000000 _( b00000000000000000000000000001001 `( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 c( 1g( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 l( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 p( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 |( b00000000 ") b00000000 #) b00000000 $) b00000000 %) b00000000 &) b00000000 ') b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 @) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 D) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 P) b00000000 T) b00000000 U) b00000000 V) b00000000 W) b00000000 X) b00000000 Y) b00000000000000000000000000001001 Z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]) 1a) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 f) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 j) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 v) b00000000 z) b00000000 {) b00000000 |) b00000000 }) b00000000 ~) b00000000 !* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 :* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 >* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 J* b00000000 N* b00000000 O* b00000000 P* b00000000 Q* b00000000 R* b00000000 S* b00000000000000000000000000001001 T* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W* 1[* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 `* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 d* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 p* b00000000 t* b00000000 u* b00000000 v* b00000000 w* b00000000 x* b00000000 y* #95 0v" 0.# 03# 0#' 0m' 0g( 0a) 0[* #100 b00010000 # b00001101 $ b00001010 % b00000000000000000000000000001010 & b00001110 ' b00001011 ) b00010000 * b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 / b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ? b00000000000000000000000000001010 C b00000000 F b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 [ b00000000000000000000000000001010 _ b00000000 b b00010001 c b00010000 d b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y b00000000000000000000000000001010 } b00000000 "! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7! b00000000000000000000000000001010 ;! b00000000 >! b00010000 ?! b00010001 @! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 E! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ?" b00001110 C" b00001110 D" b00010010 E" b00000110 F" b00000101 G" b00000100 H" b00000011 I" b00000010 J" b00000001 K" b00000110 L" b00000101 M" b00000100 N" b00000011 O" b00000010 P" b00000001 Q" b00000110 R" b00000101 S" b00000100 T" b00000011 U" b00000010 V" b00000001 W" b00000110 X" b00000101 Y" b00000100 Z" b00000011 [" b00000010 \" b00000001 ]" b00000110 ^" b00000101 _" b00000100 `" b00000011 a" b00000010 b" b00000001 c" b00000110 d" b00000101 e" b00000100 f" b00000011 g" b00000010 h" b00000001 i" b00000110 j" b00000101 k" b00000100 l" b00000011 m" b00000010 n" b00000001 o" b00000110 p" b00000101 q" b00000100 r" b00000011 s" b00000010 t" b00000001 u" 1v" 1.# b00010000 /# b00001110 0# b00001110 1# 13# b00001110 4# b00001110 5# b00001110 6# b00010010 y# b00010010 z# b00010001 {# b00010010 |# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 #$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3$ b00000110 7$ b00000101 8$ b00000100 9$ b00000011 :$ b00000010 ;$ b00000001 <$ b00000000000000000000000000001010 =$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R$ b00000110 V$ b00000101 W$ b00000100 X$ b00000011 Y$ b00000010 Z$ b00000001 [$ b00000000000000000000000000001010 \$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _$ b00000000 e$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 j$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z$ b00000110 ~$ b00000101 !% b00000100 "% b00000011 #% b00000010 $% b00000001 %% b00000000000000000000000000001010 &% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;% b00000110 ?% b00000101 @% b00000100 A% b00000011 B% b00000010 C% b00000001 D% b00000000000000000000000000001010 E% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 H% b00000000 N% b00010001 O% b00010010 P% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 U% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Y% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e% b00000110 i% b00000101 j% b00000100 k% b00000011 l% b00000010 m% b00000001 n% b00000000000000000000000000001010 o% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 && b00000110 *& b00000101 +& b00000100 ,& b00000011 -& b00000010 .& b00000001 /& b00000000000000000000000000001010 0& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 3& b00000000 9& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 >& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N& b00000110 R& b00000101 S& b00000100 T& b00000011 U& b00000010 V& b00000001 W& b00000000000000000000000000001010 X& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m& b00000110 q& b00000101 r& b00000100 s& b00000011 t& b00000010 u& b00000001 v& b00000000000000000000000000001010 w& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 z& b00000000 "' 1#' b00001110 $' b00010010 %' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \' b00000110 `' b00000101 a' b00000100 b' b00000011 c' b00000010 d' b00000001 e' b00000000000000000000000000001010 f' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 i' 1m' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $( b00000110 (( b00000101 )( b00000100 *( b00000011 +( b00000010 ,( b00000001 -( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V( b00000110 Z( b00000101 [( b00000100 \( b00000011 ]( b00000010 ^( b00000001 _( b00000000000000000000000000001010 `( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 c( 1g( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |( b00000110 ") b00000101 #) b00000100 $) b00000011 %) b00000010 &) b00000001 ') b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 @) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 D) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P) b00000110 T) b00000101 U) b00000100 V) b00000011 W) b00000010 X) b00000001 Y) b00000000000000000000000000001010 Z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ]) 1a) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 f) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 j) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v) b00000110 z) b00000101 {) b00000100 |) b00000011 }) b00000010 ~) b00000001 !* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 :* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 >* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J* b00000110 N* b00000101 O* b00000100 P* b00000011 Q* b00000010 R* b00000001 S* b00000000000000000000000000001010 T* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 W* 1[* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 `* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 d* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p* b00000110 t* b00000101 u* b00000100 v* b00000011 w* b00000010 x* b00000001 y* #105 0v" 0.# 03# 0#' 0m' 0g( 0a) 0[* #110 b00010011 # b00001110 $ b00001011 % b00000000000000000000000000001011 & b00010000 ' b00001101 ( b00010011 * b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 / b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ? b00000000000000000000000000001011 C b00000001 F b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 [ b00000000000000000000000000001011 _ b00000001 b b00010011 c b00010011 d b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 y b00000000000000000000000000001011 } b00000001 "! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 '! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 7! b00000000000000000000000000001011 ;! b00000001 >! b00010011 ?! b00010011 @! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 E! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 u! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 /" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ?" b00010000 C" b00001111 D" b00010011 E" b00000000 F" b00000000 G" b00000000 H" b00000000 I" b00000000 J" b00000000 K" b00000000 L" b00000000 M" b00000000 N" b00000000 O" b00000000 P" b00000000 Q" b00000000 R" b00000000 S" b00000000 T" b00000000 U" b00000000 V" b00000000 W" b00000000 X" b00000000 Y" b00000000 Z" b00000000 [" b00000000 \" b00000000 ]" b00000000 ^" b00000000 _" b00000000 `" b00000000 a" b00000000 b" b00000000 c" b00000000 d" b00000000 e" b00000000 f" b00000000 g" b00000000 h" b00000000 i" b00000000 j" b00000000 k" b00000000 l" b00000000 m" b00000000 n" b00000000 o" b00000000 p" b00000000 q" b00000000 r" b00000000 s" b00000000 t" b00000000 u" 1v" 1.# b00010011 /# b00010000 0# b00010000 1# 13# b00010000 4# b00001111 5# b00001111 6# b00010000 x# b00010011 y# b00010011 z# b00010011 |# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 #$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 '$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 3$ b00000000 7$ b00000000 8$ b00000000 9$ b00000000 :$ b00000000 ;$ b00000000 <$ b00000000000000000000000000001011 =$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 B$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 F$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 R$ b00000000 V$ b00000000 W$ b00000000 X$ b00000000 Y$ b00000000 Z$ b00000000 [$ b00000000000000000000000000001011 \$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 _$ b00000001 e$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 j$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 n$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 z$ b00000000 ~$ b00000000 !% b00000000 "% b00000000 #% b00000000 $% b00000000 %% b00000000000000000000000000001011 &% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 +% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 /% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;% b00000000 ?% b00000000 @% b00000000 A% b00000000 B% b00000000 C% b00000000 D% b00000000000000000000000000001011 E% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H% b00000001 N% b00010011 P% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 U% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 Y% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 e% b00000000 i% b00000000 j% b00000000 k% b00000000 l% b00000000 m% b00000000 n% b00000000000000000000000000001011 o% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 t% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 x% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 && b00000000 *& b00000000 +& b00000000 ,& b00000000 -& b00000000 .& b00000000 /& b00000000000000000000000000001011 0& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3& b00000001 9& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 >& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 B& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 N& b00000000 R& b00000000 S& b00000000 T& b00000000 U& b00000000 V& b00000000 W& b00000000000000000000000000001011 X& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m& b00000000 q& b00000000 r& b00000000 s& b00000000 t& b00000000 u& b00000000 v& b00000000000000000000000000001011 w& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z& b00000001 "' 1#' b00001111 $' b00010011 %' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 L' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 P' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 \' b00000000 `' b00000000 a' b00000000 b' b00000000 c' b00000000 d' b00000000 e' b00000000000000000000000000001011 f' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i' 1m' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 r' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 v' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 $( b00000000 (( b00000000 )( b00000000 *( b00000000 +( b00000000 ,( b00000000 -( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 F( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 J( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 V( b00000000 Z( b00000000 [( b00000000 \( b00000000 ]( b00000000 ^( b00000000 _( b00000000000000000000000000001011 `( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 c( 1g( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 l( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 p( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 |( b00000000 ") b00000000 #) b00000000 $) b00000000 %) b00000000 &) b00000000 ') b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 @) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 D) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 P) b00000000 T) b00000000 U) b00000000 V) b00000000 W) b00000000 X) b00000000 Y) b00000000000000000000000000001011 Z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]) 1a) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 f) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 j) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 v) b00000000 z) b00000000 {) b00000000 |) b00000000 }) b00000000 ~) b00000000 !* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 :* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 >* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 J* b00000000 N* b00000000 O* b00000000 P* b00000000 Q* b00000000 R* b00000000 S* b00000000000000000000000000001011 T* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W* 1[* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 `* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 d* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 p* b00000000 t* b00000000 u* b00000000 v* b00000000 w* b00000000 x* b00000000 y* #115 0v" 0.# 03# 0#' 0m' 0g( 0a) 0[* #120 b00010101 # b00010000 $ b00000000000000000000000000001100 & b00010011 ' b00001110 ( b00001101 ) b00010101 * b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 / b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ? b00000000000000000000000000001100 C b00000000 F b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 [ b00000000000000000000000000001100 _ b00000000 b b00010100 c b00010101 d b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y b00000000000000000000000000001100 } b00000000 "! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7! b00000000000000000000000000001100 ;! b00000000 >! b00010101 ?! b00010100 @! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 E! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ?" b00010011 C" b00010001 D" b00000110 F" b00000101 G" b00000100 H" b00000011 I" b00000010 J" b00000001 K" b00000110 L" b00000101 M" b00000100 N" b00000011 O" b00000010 P" b00000001 Q" b00000110 R" b00000101 S" b00000100 T" b00000011 U" b00000010 V" b00000001 W" b00000110 X" b00000101 Y" b00000100 Z" b00000011 [" b00000010 \" b00000001 ]" b00000110 ^" b00000101 _" b00000100 `" b00000011 a" b00000010 b" b00000001 c" b00000110 d" b00000101 e" b00000100 f" b00000011 g" b00000010 h" b00000001 i" b00000110 j" b00000101 k" b00000100 l" b00000011 m" b00000010 n" b00000001 o" b00000110 p" b00000101 q" b00000100 r" b00000011 s" b00000010 t" b00000001 u" 1v" 1.# b00010101 /# b00010011 0# b00010011 1# 13# b00010011 4# b00010001 5# b00010001 6# b00010001 x# b00010011 {# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 #$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3$ b00000110 7$ b00000101 8$ b00000100 9$ b00000011 :$ b00000010 ;$ b00000001 <$ b00000000000000000000000000001100 =$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R$ b00000110 V$ b00000101 W$ b00000100 X$ b00000011 Y$ b00000010 Z$ b00000001 [$ b00000000000000000000000000001100 \$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _$ b00000000 e$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 j$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z$ b00000110 ~$ b00000101 !% b00000100 "% b00000011 #% b00000010 $% b00000001 %% b00000000000000000000000000001100 &% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;% b00000110 ?% b00000101 @% b00000100 A% b00000011 B% b00000010 C% b00000001 D% b00000000000000000000000000001100 E% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 H% b00000000 N% b00010011 O% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 U% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Y% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e% b00000110 i% b00000101 j% b00000100 k% b00000011 l% b00000010 m% b00000001 n% b00000000000000000000000000001100 o% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 && b00000110 *& b00000101 +& b00000100 ,& b00000011 -& b00000010 .& b00000001 /& b00000000000000000000000000001100 0& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 3& b00000000 9& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 >& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N& b00000110 R& b00000101 S& b00000100 T& b00000011 U& b00000010 V& b00000001 W& b00000000000000000000000000001100 X& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m& b00000110 q& b00000101 r& b00000100 s& b00000011 t& b00000010 u& b00000001 v& b00000000000000000000000000001100 w& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 z& b00000000 "' 1#' b00010001 $' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \' b00000110 `' b00000101 a' b00000100 b' b00000011 c' b00000010 d' b00000001 e' b00000000000000000000000000001100 f' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 i' 1m' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $( b00000110 (( b00000101 )( b00000100 *( b00000011 +( b00000010 ,( b00000001 -( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V( b00000110 Z( b00000101 [( b00000100 \( b00000011 ]( b00000010 ^( b00000001 _( b00000000000000000000000000001100 `( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 c( 1g( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |( b00000110 ") b00000101 #) b00000100 $) b00000011 %) b00000010 &) b00000001 ') b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 @) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 D) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P) b00000110 T) b00000101 U) b00000100 V) b00000011 W) b00000010 X) b00000001 Y) b00000000000000000000000000001100 Z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ]) 1a) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 f) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 j) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v) b00000110 z) b00000101 {) b00000100 |) b00000011 }) b00000010 ~) b00000001 !* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 :* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 >* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J* b00000110 N* b00000101 O* b00000100 P* b00000011 Q* b00000010 R* b00000001 S* b00000000000000000000000000001100 T* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 W* 1[* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 `* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 d* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p* b00000110 t* b00000101 u* b00000100 v* b00000011 w* b00000010 x* b00000001 y* #125 0v" 0.# 03# 0#' 0m' 0g( 0a) 0[* #130 b00010110 # b00010011 $ b00001101 % b00000000000000000000000000001101 & b00010101 ' b00010000 ( b00001110 ) b00010110 * b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 / b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ? b00000000000000000000000000001101 C b00000001 F b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 [ b00000000000000000000000000001101 _ b00000001 b b00010110 d b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 y b00000000000000000000000000001101 } b00000001 "! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 '! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 7! b00000000000000000000000000001101 ;! b00000001 >! b00010110 ?! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 E! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 u! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 /" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ?" b00010101 C" b00010100 D" b00010101 E" b00000000 F" b00000000 G" b00000000 H" b00000000 I" b00000000 J" b00000000 K" b00000000 L" b00000000 M" b00000000 N" b00000000 O" b00000000 P" b00000000 Q" b00000000 R" b00000000 S" b00000000 T" b00000000 U" b00000000 V" b00000000 W" b00000000 X" b00000000 Y" b00000000 Z" b00000000 [" b00000000 \" b00000000 ]" b00000000 ^" b00000000 _" b00000000 `" b00000000 a" b00000000 b" b00000000 c" b00000000 d" b00000000 e" b00000000 f" b00000000 g" b00000000 h" b00000000 i" b00000000 j" b00000000 k" b00000000 l" b00000000 m" b00000000 n" b00000000 o" b00000000 p" b00000000 q" b00000000 r" b00000000 s" b00000000 t" b00000000 u" 1v" 1.# b00010110 /# b00010101 0# b00010101 1# 13# b00010101 4# b00010100 5# b00010100 6# b00010011 x# b00010101 y# b00010101 z# b00010100 {# b00010101 |# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 #$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 '$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 3$ b00000000 7$ b00000000 8$ b00000000 9$ b00000000 :$ b00000000 ;$ b00000000 <$ b00000000000000000000000000001101 =$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 B$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 F$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 R$ b00000000 V$ b00000000 W$ b00000000 X$ b00000000 Y$ b00000000 Z$ b00000000 [$ b00000000000000000000000000001101 \$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 _$ b00000001 e$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 j$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 n$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 z$ b00000000 ~$ b00000000 !% b00000000 "% b00000000 #% b00000000 $% b00000000 %% b00000000000000000000000000001101 &% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 +% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 /% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;% b00000000 ?% b00000000 @% b00000000 A% b00000000 B% b00000000 C% b00000000 D% b00000000000000000000000000001101 E% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H% b00000001 N% b00010100 O% b00010101 P% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 U% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 Y% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 e% b00000000 i% b00000000 j% b00000000 k% b00000000 l% b00000000 m% b00000000 n% b00000000000000000000000000001101 o% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 t% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 x% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 && b00000000 *& b00000000 +& b00000000 ,& b00000000 -& b00000000 .& b00000000 /& b00000000000000000000000000001101 0& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3& b00000001 9& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 >& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 B& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 N& b00000000 R& b00000000 S& b00000000 T& b00000000 U& b00000000 V& b00000000 W& b00000000000000000000000000001101 X& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m& b00000000 q& b00000000 r& b00000000 s& b00000000 t& b00000000 u& b00000000 v& b00000000000000000000000000001101 w& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z& b00000001 "' 1#' b00010100 $' b00010101 %' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 L' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 P' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 \' b00000000 `' b00000000 a' b00000000 b' b00000000 c' b00000000 d' b00000000 e' b00000000000000000000000000001101 f' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i' 1m' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 r' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 v' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 $( b00000000 (( b00000000 )( b00000000 *( b00000000 +( b00000000 ,( b00000000 -( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 F( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 J( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 V( b00000000 Z( b00000000 [( b00000000 \( b00000000 ]( b00000000 ^( b00000000 _( b00000000000000000000000000001101 `( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 c( 1g( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 l( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 p( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 |( b00000000 ") b00000000 #) b00000000 $) b00000000 %) b00000000 &) b00000000 ') b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 @) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 D) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 P) b00000000 T) b00000000 U) b00000000 V) b00000000 W) b00000000 X) b00000000 Y) b00000000000000000000000000001101 Z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]) 1a) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 f) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 j) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 v) b00000000 z) b00000000 {) b00000000 |) b00000000 }) b00000000 ~) b00000000 !* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 :* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 >* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 J* b00000000 N* b00000000 O* b00000000 P* b00000000 Q* b00000000 R* b00000000 S* b00000000000000000000000000001101 T* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W* 1[* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 `* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 d* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 p* b00000000 t* b00000000 u* b00000000 v* b00000000 w* b00000000 x* b00000000 y* #135 0v" 0.# 03# 0#' 0m' 0g( 0a) 0[* #140 b00010101 $ b00001110 % b00000000000000000000000000001110 & b00010110 ' b00010011 ( b00010000 ) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 / b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ? b00000000000000000000000000001110 C b00000000 F b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 [ b00000000000000000000000000001110 _ b00000000 b b00010110 c b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y b00000000000000000000000000001110 } b00000000 "! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7! b00000000000000000000000000001110 ;! b00000000 >! b00010110 @! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 E! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ?" b00010110 C" b00010110 D" b00010110 E" b00000110 F" b00000101 G" b00000100 H" b00000011 I" b00000010 J" b00000001 K" b00000110 L" b00000101 M" b00000100 N" b00000011 O" b00000010 P" b00000001 Q" b00000110 R" b00000101 S" b00000100 T" b00000011 U" b00000010 V" b00000001 W" b00000110 X" b00000101 Y" b00000100 Z" b00000011 [" b00000010 \" b00000001 ]" b00000110 ^" b00000101 _" b00000100 `" b00000011 a" b00000010 b" b00000001 c" b00000110 d" b00000101 e" b00000100 f" b00000011 g" b00000010 h" b00000001 i" b00000110 j" b00000101 k" b00000100 l" b00000011 m" b00000010 n" b00000001 o" b00000110 p" b00000101 q" b00000100 r" b00000011 s" b00000010 t" b00000001 u" 1v" 1.# b00010110 0# b00010110 1# 13# b00010110 4# b00010110 5# b00010110 6# b00010110 x# b00010110 y# b00010110 z# b00010110 {# b00010110 |# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 #$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3$ b00000110 7$ b00000101 8$ b00000100 9$ b00000011 :$ b00000010 ;$ b00000001 <$ b00000000000000000000000000001110 =$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R$ b00000110 V$ b00000101 W$ b00000100 X$ b00000011 Y$ b00000010 Z$ b00000001 [$ b00000000000000000000000000001110 \$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _$ b00000000 e$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 j$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z$ b00000110 ~$ b00000101 !% b00000100 "% b00000011 #% b00000010 $% b00000001 %% b00000000000000000000000000001110 &% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;% b00000110 ?% b00000101 @% b00000100 A% b00000011 B% b00000010 C% b00000001 D% b00000000000000000000000000001110 E% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 H% b00000000 N% b00010110 O% b00010110 P% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 U% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Y% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e% b00000110 i% b00000101 j% b00000100 k% b00000011 l% b00000010 m% b00000001 n% b00000000000000000000000000001110 o% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 && b00000110 *& b00000101 +& b00000100 ,& b00000011 -& b00000010 .& b00000001 /& b00000000000000000000000000001110 0& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 3& b00000000 9& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 >& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N& b00000110 R& b00000101 S& b00000100 T& b00000011 U& b00000010 V& b00000001 W& b00000000000000000000000000001110 X& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m& b00000110 q& b00000101 r& b00000100 s& b00000011 t& b00000010 u& b00000001 v& b00000000000000000000000000001110 w& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 z& b00000000 "' 1#' b00010110 $' b00010110 %' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \' b00000110 `' b00000101 a' b00000100 b' b00000011 c' b00000010 d' b00000001 e' b00000000000000000000000000001110 f' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 i' 1m' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $( b00000110 (( b00000101 )( b00000100 *( b00000011 +( b00000010 ,( b00000001 -( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V( b00000110 Z( b00000101 [( b00000100 \( b00000011 ]( b00000010 ^( b00000001 _( b00000000000000000000000000001110 `( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 c( 1g( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |( b00000110 ") b00000101 #) b00000100 $) b00000011 %) b00000010 &) b00000001 ') b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 @) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 D) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P) b00000110 T) b00000101 U) b00000100 V) b00000011 W) b00000010 X) b00000001 Y) b00000000000000000000000000001110 Z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ]) 1a) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 f) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 j) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v) b00000110 z) b00000101 {) b00000100 |) b00000011 }) b00000010 ~) b00000001 !* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 :* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 >* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J* b00000110 N* b00000101 O* b00000100 P* b00000011 Q* b00000010 R* b00000001 S* b00000000000000000000000000001110 T* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 W* 1[* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 `* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 d* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p* b00000110 t* b00000101 u* b00000100 v* b00000011 w* b00000010 x* b00000001 y* #145 0v" 0.# 03# 0#' 0m' 0g( 0a) 0[* #150 b00011000 # b00010110 $ b00010000 % b00000000000000000000000000001111 & b00010101 ( b00010011 ) b00011000 * b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 / b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ? b00000000000000000000000000001111 C b00000001 F b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 [ b00000000000000000000000000001111 _ b00000001 b b00010111 c b00011000 d b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 y b00000000000000000000000000001111 } b00000001 "! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 '! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 7! b00000000000000000000000000001111 ;! b00000001 >! b00011000 ?! b00010111 @! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 E! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 u! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 /" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ?" b00010111 D" b00011000 E" b00000000 F" b00000000 G" b00000000 H" b00000000 I" b00000000 J" b00000000 K" b00000000 L" b00000000 M" b00000000 N" b00000000 O" b00000000 P" b00000000 Q" b00000000 R" b00000000 S" b00000000 T" b00000000 U" b00000000 V" b00000000 W" b00000000 X" b00000000 Y" b00000000 Z" b00000000 [" b00000000 \" b00000000 ]" b00000000 ^" b00000000 _" b00000000 `" b00000000 a" b00000000 b" b00000000 c" b00000000 d" b00000000 e" b00000000 f" b00000000 g" b00000000 h" b00000000 i" b00000000 j" b00000000 k" b00000000 l" b00000000 m" b00000000 n" b00000000 o" b00000000 p" b00000000 q" b00000000 r" b00000000 s" b00000000 t" b00000000 u" 1v" 1.# b00011000 /# 13# b00010111 5# b00010111 6# b00011000 x# b00011000 y# b00011000 z# b00011001 {# b00011000 |# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 #$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 '$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 3$ b00000000 7$ b00000000 8$ b00000000 9$ b00000000 :$ b00000000 ;$ b00000000 <$ b00000000000000000000000000001111 =$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 B$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 F$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 R$ b00000000 V$ b00000000 W$ b00000000 X$ b00000000 Y$ b00000000 Z$ b00000000 [$ b00000000000000000000000000001111 \$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 _$ b00000001 e$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 j$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 n$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 z$ b00000000 ~$ b00000000 !% b00000000 "% b00000000 #% b00000000 $% b00000000 %% b00000000000000000000000000001111 &% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 +% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 /% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;% b00000000 ?% b00000000 @% b00000000 A% b00000000 B% b00000000 C% b00000000 D% b00000000000000000000000000001111 E% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H% b00000001 N% b00011001 O% b00011000 P% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 U% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 Y% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 e% b00000000 i% b00000000 j% b00000000 k% b00000000 l% b00000000 m% b00000000 n% b00000000000000000000000000001111 o% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 t% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 x% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 && b00000000 *& b00000000 +& b00000000 ,& b00000000 -& b00000000 .& b00000000 /& b00000000000000000000000000001111 0& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3& b00000001 9& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 >& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 B& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 N& b00000000 R& b00000000 S& b00000000 T& b00000000 U& b00000000 V& b00000000 W& b00000000000000000000000000001111 X& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m& b00000000 q& b00000000 r& b00000000 s& b00000000 t& b00000000 u& b00000000 v& b00000000000000000000000000001111 w& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z& b00000001 "' 1#' b00010111 $' b00011000 %' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 L' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 P' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 \' b00000000 `' b00000000 a' b00000000 b' b00000000 c' b00000000 d' b00000000 e' b00000000000000000000000000001111 f' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i' 1m' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 r' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 v' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 $( b00000000 (( b00000000 )( b00000000 *( b00000000 +( b00000000 ,( b00000000 -( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 F( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 J( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 V( b00000000 Z( b00000000 [( b00000000 \( b00000000 ]( b00000000 ^( b00000000 _( b00000000000000000000000000001111 `( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 c( 1g( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 l( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 p( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 |( b00000000 ") b00000000 #) b00000000 $) b00000000 %) b00000000 &) b00000000 ') b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 @) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 D) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 P) b00000000 T) b00000000 U) b00000000 V) b00000000 W) b00000000 X) b00000000 Y) b00000000000000000000000000001111 Z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]) 1a) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 f) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 j) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 v) b00000000 z) b00000000 {) b00000000 |) b00000000 }) b00000000 ~) b00000000 !* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 :* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 >* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 J* b00000000 N* b00000000 O* b00000000 P* b00000000 Q* b00000000 R* b00000000 S* b00000000000000000000000000001111 T* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W* 1[* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 `* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 d* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 p* b00000000 t* b00000000 u* b00000000 v* b00000000 w* b00000000 x* b00000000 y* #155 0v" 0.# 03# 0#' 0m' 0g( 0a) 0[* #160 b00011001 # b00010011 % b00000000000000000000000000010000 & b00011000 ' b00010110 ( b00010101 ) b00011001 * b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 / b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ? b00000000000000000000000000010000 C b00000000 F b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 [ b00000000000000000000000000010000 _ b00000000 b b00011001 c b00011001 d b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y b00000000000000000000000000010000 } b00000000 "! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7! b00000000000000000000000000010000 ;! b00000000 >! b00011001 ?! b00011001 @! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 E! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ?" b00011000 C" b00011011 E" b00000110 F" b00000101 G" b00000100 H" b00000011 I" b00000010 J" b00000001 K" b00000110 L" b00000101 M" b00000100 N" b00000011 O" b00000010 P" b00000001 Q" b00000110 R" b00000101 S" b00000100 T" b00000011 U" b00000010 V" b00000001 W" b00000110 X" b00000101 Y" b00000100 Z" b00000011 [" b00000010 \" b00000001 ]" b00000110 ^" b00000101 _" b00000100 `" b00000011 a" b00000010 b" b00000001 c" b00000110 d" b00000101 e" b00000100 f" b00000011 g" b00000010 h" b00000001 i" b00000110 j" b00000101 k" b00000100 l" b00000011 m" b00000010 n" b00000001 o" b00000110 p" b00000101 q" b00000100 r" b00000011 s" b00000010 t" b00000001 u" 1v" 1.# b00011001 /# b00011000 0# b00011000 1# 13# b00011000 4# b00011001 x# b00011011 y# b00011011 z# b00011011 {# b00011011 |# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 #$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3$ b00000110 7$ b00000101 8$ b00000100 9$ b00000011 :$ b00000010 ;$ b00000001 <$ b00000000000000000000000000010000 =$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R$ b00000110 V$ b00000101 W$ b00000100 X$ b00000011 Y$ b00000010 Z$ b00000001 [$ b00000000000000000000000000010000 \$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _$ b00000000 e$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 j$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z$ b00000110 ~$ b00000101 !% b00000100 "% b00000011 #% b00000010 $% b00000001 %% b00000000000000000000000000010000 &% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;% b00000110 ?% b00000101 @% b00000100 A% b00000011 B% b00000010 C% b00000001 D% b00000000000000000000000000010000 E% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 H% b00000000 N% b00011011 O% b00011011 P% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 U% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Y% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e% b00000110 i% b00000101 j% b00000100 k% b00000011 l% b00000010 m% b00000001 n% b00000000000000000000000000010000 o% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 && b00000110 *& b00000101 +& b00000100 ,& b00000011 -& b00000010 .& b00000001 /& b00000000000000000000000000010000 0& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 3& b00000000 9& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 >& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N& b00000110 R& b00000101 S& b00000100 T& b00000011 U& b00000010 V& b00000001 W& b00000000000000000000000000010000 X& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m& b00000110 q& b00000101 r& b00000100 s& b00000011 t& b00000010 u& b00000001 v& b00000000000000000000000000010000 w& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 z& b00000000 "' 1#' b00011011 %' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \' b00000110 `' b00000101 a' b00000100 b' b00000011 c' b00000010 d' b00000001 e' b00000000000000000000000000010000 f' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 i' 1m' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $( b00000110 (( b00000101 )( b00000100 *( b00000011 +( b00000010 ,( b00000001 -( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V( b00000110 Z( b00000101 [( b00000100 \( b00000011 ]( b00000010 ^( b00000001 _( b00000000000000000000000000010000 `( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 c( 1g( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |( b00000110 ") b00000101 #) b00000100 $) b00000011 %) b00000010 &) b00000001 ') b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 @) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 D) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P) b00000110 T) b00000101 U) b00000100 V) b00000011 W) b00000010 X) b00000001 Y) b00000000000000000000000000010000 Z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ]) 1a) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 f) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 j) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v) b00000110 z) b00000101 {) b00000100 |) b00000011 }) b00000010 ~) b00000001 !* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 :* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 >* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J* b00000110 N* b00000101 O* b00000100 P* b00000011 Q* b00000010 R* b00000001 S* b00000000000000000000000000010000 T* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 W* 1[* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 `* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 d* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p* b00000110 t* b00000101 u* b00000100 v* b00000011 w* b00000010 x* b00000001 y* #165 0v" 0.# 03# 0#' 0m' 0g( 0a) 0[* #170 b00011011 # b00011000 $ b00010101 % b00000000000000000000000000010001 & b00011001 ' b00010110 ) b00011011 * b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 / b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ? b00000000000000000000000000010001 C b00000001 F b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 [ b00000000000000000000000000010001 _ b00000001 b b00011100 c b00011011 d b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 y b00000000000000000000000000010001 } b00000001 "! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 '! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 7! b00000000000000000000000000010001 ;! b00000001 >! b00011011 ?! b00011100 @! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 E! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 u! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 /" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ?" b00011001 C" b00011001 D" b00011101 E" b00000000 F" b00000000 G" b00000000 H" b00000000 I" b00000000 J" b00000000 K" b00000000 L" b00000000 M" b00000000 N" b00000000 O" b00000000 P" b00000000 Q" b00000000 R" b00000000 S" b00000000 T" b00000000 U" b00000000 V" b00000000 W" b00000000 X" b00000000 Y" b00000000 Z" b00000000 [" b00000000 \" b00000000 ]" b00000000 ^" b00000000 _" b00000000 `" b00000000 a" b00000000 b" b00000000 c" b00000000 d" b00000000 e" b00000000 f" b00000000 g" b00000000 h" b00000000 i" b00000000 j" b00000000 k" b00000000 l" b00000000 m" b00000000 n" b00000000 o" b00000000 p" b00000000 q" b00000000 r" b00000000 s" b00000000 t" b00000000 u" 1v" 1.# b00011011 /# b00011001 0# b00011001 1# 13# b00011001 4# b00011001 5# b00011001 6# b00011101 y# b00011101 z# b00011100 {# b00011101 |# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 #$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 '$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 3$ b00000000 7$ b00000000 8$ b00000000 9$ b00000000 :$ b00000000 ;$ b00000000 <$ b00000000000000000000000000010001 =$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 B$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 F$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 R$ b00000000 V$ b00000000 W$ b00000000 X$ b00000000 Y$ b00000000 Z$ b00000000 [$ b00000000000000000000000000010001 \$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 _$ b00000001 e$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 j$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 n$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 z$ b00000000 ~$ b00000000 !% b00000000 "% b00000000 #% b00000000 $% b00000000 %% b00000000000000000000000000010001 &% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 +% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 /% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;% b00000000 ?% b00000000 @% b00000000 A% b00000000 B% b00000000 C% b00000000 D% b00000000000000000000000000010001 E% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H% b00000001 N% b00011100 O% b00011101 P% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 U% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 Y% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 e% b00000000 i% b00000000 j% b00000000 k% b00000000 l% b00000000 m% b00000000 n% b00000000000000000000000000010001 o% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 t% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 x% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 && b00000000 *& b00000000 +& b00000000 ,& b00000000 -& b00000000 .& b00000000 /& b00000000000000000000000000010001 0& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3& b00000001 9& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 >& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 B& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 N& b00000000 R& b00000000 S& b00000000 T& b00000000 U& b00000000 V& b00000000 W& b00000000000000000000000000010001 X& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m& b00000000 q& b00000000 r& b00000000 s& b00000000 t& b00000000 u& b00000000 v& b00000000000000000000000000010001 w& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z& b00000001 "' 1#' b00011001 $' b00011101 %' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 L' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 P' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 \' b00000000 `' b00000000 a' b00000000 b' b00000000 c' b00000000 d' b00000000 e' b00000000000000000000000000010001 f' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i' 1m' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 r' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 v' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 $( b00000000 (( b00000000 )( b00000000 *( b00000000 +( b00000000 ,( b00000000 -( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 F( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 J( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 V( b00000000 Z( b00000000 [( b00000000 \( b00000000 ]( b00000000 ^( b00000000 _( b00000000000000000000000000010001 `( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 c( 1g( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 l( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 p( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 |( b00000000 ") b00000000 #) b00000000 $) b00000000 %) b00000000 &) b00000000 ') b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 @) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 D) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 P) b00000000 T) b00000000 U) b00000000 V) b00000000 W) b00000000 X) b00000000 Y) b00000000000000000000000000010001 Z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]) 1a) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 f) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 j) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 v) b00000000 z) b00000000 {) b00000000 |) b00000000 }) b00000000 ~) b00000000 !* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 :* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 >* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 J* b00000000 N* b00000000 O* b00000000 P* b00000000 Q* b00000000 R* b00000000 S* b00000000000000000000000000010001 T* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W* 1[* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 `* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 d* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 p* b00000000 t* b00000000 u* b00000000 v* b00000000 w* b00000000 x* b00000000 y* #174 verilator-5.042/test_regress/t/t_randomize_unpacked_wide.py0000755000542200017500000000104615101701376024641 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_wire_behp1800_bad.py0000755000542200017500000000107615101701376023055 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--lint-only --language 1800-2017"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_latch_4.py0000755000542200017500000000070315101701376022332 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint() test.passes() verilator-5.042/test_regress/t/t_assert_past.v0000644000542200017500000000144715101701376022136 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ clk ); input clk; int cyc = 0; logic val = 0; // Example: always @(posedge clk) begin cyc <= cyc + 1; val = ~val; $display("t=%0t cyc=%0d val=%b", $time, cyc, val); if (cyc == 10) begin $write("*-* All Finished *-*\n"); $finish; end end assert property(@(posedge clk) cyc % 2 == 0 |=> $past(val) == 0) else $display("$past assert 1 failed"); assert property(@(posedge clk) cyc % 2 == 1 |=> $past(val) == 1) else $display("$past assert 2 failed"); // Example end endmodule verilator-5.042/test_regress/t/t_let_arg_bad.py0000755000542200017500000000076615101701376022222 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_func_nansi_mism_bad.py0000755000542200017500000000076615101701376023755 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_wrapper_context__trace0.vcd.out0000644000542200017500000000155615101701376025545 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top1 $end $var wire 1 # clk $end $var wire 1 $ rst $end $var wire 32 % trace_number [31:0] $end $var wire 1 & stop $end $var wire 32 ' counter [31:0] $end $var wire 1 ( done_o $end $scope module top $end $var wire 1 # clk $end $var wire 1 $ rst $end $var wire 32 % trace_number [31:0] $end $var wire 1 & stop $end $var wire 32 ' counter [31:0] $end $var wire 1 ( done_o $end $upscope $end $upscope $end $enddefinitions $end #0 0# 1$ b00000000000000000000000000000000 % 1& b00000000000000000000000000000000 ' 0( #1 1# #2 0# 0$ #3 1# b00000000000000000000000000000001 ' #4 0# #5 1# b00000000000000000000000000000010 ' #6 0# #7 1# b00000000000000000000000000000011 ' #8 0# #9 1# b00000000000000000000000000000100 ' #10 0# #11 1# b00000000000000000000000000000101 ' 1( verilator-5.042/test_regress/t/t_inst_recurse2_bad.out0000644000542200017500000000064715101701376023546 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_inst_recurse2_bad.v:13:8: Unsupported: Identically recursive module (module instantiates itself, without changing parameters): 'looped' : ... note: In instance 't.looped.looped.looped' 13 | module looped; | ^~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_display_qqq.v0000644000542200017500000000056715101701376022137 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin $display("""First "quoted"\nsecond\ third fourth"""); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_param_repl.py0000755000542200017500000000073415101701376022114 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_unopt_bound.v0000644000542200017500000000126015101701376022133 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Jue Xu. // SPDX-License-Identifier: CC0-1.0 // bug630 module t ( clk, out ); input clk; output out; reg a; reg b; typedef struct packed { logic config_a; logic config_b; } param_t; // verilator lint_off UNOPTFLAT param_t conf [1:2] ; // verilator lint_on UNOPTFLAT always @ (posedge clk) begin conf[2].config_b <= a; $write("*-* All Finished *-*\n"); $finish; end always @ (posedge conf[2].config_b) begin a = conf[2].config_a; end endmodule verilator-5.042/test_regress/t/t_trace_sc_empty.py0000755000542200017500000000076315101701376022775 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['-sc', '--trace-vcd']) test.passes() verilator-5.042/test_regress/t/t_wire_beh1364_bad.v0000644000542200017500000000130315101701376022505 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs o, oa, ro, roa, wo, woa ); wire w; reg r; output o; output [1:0] oa; output reg ro; output reg [1:0] roa; output wire wo; output wire [1:0] woa; //1800 only: //output var vo; //output var [1:0] voa; initial begin // Error w = 0; o = 0; oa = 0; wo = 0; woa = 0; // Not an error r = 0; ro = 0; roa = 0; //vo = 0; //voa = 0; end endmodule verilator-5.042/test_regress/t/t_dpi_import_c.cpp0000644000542200017500000001646215101701376022576 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "svdpi.h" #include #include //====================================================================== // clang-format off #if defined(VERILATOR) # include "Vt_dpi_import__Dpi.h" #elif defined(VCS) # include "../vc_hdrs.h" #elif defined(CADENCE) # define NEED_EXTERNS #else # error "Unknown simulator for DPI test" #endif // clang-format on typedef struct { int a; int b; } substruct_t; #ifdef NEED_EXTERNS extern "C" { // If get ncsim: *F,NOFDPI: Function {foo} not found in default libdpi. // Then probably forgot to list a function here. extern unsigned char dpii_f_bit(unsigned char i); extern svBitVecVal dpii_f_bit8(const svBitVecVal* i); extern svBitVecVal dpii_f_bit9(const svBitVecVal* i); extern svBitVecVal dpii_f_bit16(const svBitVecVal* i); extern svBitVecVal dpii_f_bit17(const svBitVecVal* i); extern svBitVecVal dpii_f_bit32(const svBitVecVal* i); extern long long dpii_f_bit33(const svBitVecVal* i); extern long long dpii_f_bit64(const svBitVecVal* i); extern long long dpii_f_bit95(const svBitVecVal* i, svBitVecVal* o); extern int dpii_f_int(int i); extern char dpii_f_byte(char i); extern short int dpii_f_shortint(short int i); extern long long dpii_f_longint(long long i); extern void* dpii_f_chandle(void* i); extern const char* dpii_f_string(const char* i); extern const char* dpii_f_null(); extern double dpii_f_real(double i); extern float dpii_f_shortreal(float i); extern void dpii_v_bit(unsigned char i, unsigned char* o); extern void dpii_v_int(int i, int* o); extern void dpii_v_uint(unsigned int i, unsigned int* o); extern void dpii_v_byte(char i, char* o); extern void dpii_v_shortint(short int i, short int* o); extern void dpii_v_ushort(unsigned short i, unsigned short* o); extern void dpii_v_longint(long long i, long long* o); extern void dpii_v_ulong(unsigned long long i, unsigned long long* o); extern void dpii_v_struct(const svBitVecVal* i, svBitVecVal* o); extern void dpii_v_substruct(const svBitVecVal* i, int* o); extern void dpii_v_chandle(void* i, void** o); extern void dpii_v_string(const char* i, const char** o); extern void dpii_v_real(double i, double* o); extern void dpii_v_shortreal(float i, float* o); extern void dpii_v_struct(const svBitVecVal* i, svBitVecVal* o); extern void dpii_v_substruct(const svBitVecVal* i, int* o); extern void dpii_v_bit64(const svBitVecVal* i, svBitVecVal* o); extern void dpii_v_bit95(const svBitVecVal* i, svBitVecVal* o); extern void dpii_v_bit96(const svBitVecVal* i, svBitVecVal* o); extern void dpii_v_reg(unsigned char i, unsigned char* o); extern void dpii_v_reg15(const svLogicVecVal* i, svLogicVecVal* o); extern void dpii_v_reg95(const svLogicVecVal* i, svLogicVecVal* o); extern void dpii_v_integer(const svLogicVecVal* i, svLogicVecVal* o); extern void dpii_v_time(const svLogicVecVal* i, svLogicVecVal* o); extern int dpii_f_strlen(const char* i); extern void dpii_f_void(); extern int dpii_t_void(); extern int dpii_t_void_context(); extern int dpii_t_int(int i, int* o); extern int dpii_fa_bit(int i); } #endif //====================================================================== unsigned char dpii_f_bit(unsigned char i) { return 0x1 & ~i; } svBitVecVal dpii_f_bit8(const svBitVecVal* i) { return 0xffUL & ~*i; } svBitVecVal dpii_f_bit9(const svBitVecVal* i) { return 0x1ffUL & ~*i; } svBitVecVal dpii_f_bit16(const svBitVecVal* i) { return 0xffffUL & ~*i; } svBitVecVal dpii_f_bit17(const svBitVecVal* i) { return 0x1ffffUL & ~*i; } svBitVecVal dpii_f_bit32(const svBitVecVal* i) { return ~*i; } long long dpii_f_bit33(const svBitVecVal* i) { return ((1ULL << 33) - 1) & ~((long long)(i[1]) << 32ULL | i[0]); } long long dpii_f_bit64(const svBitVecVal* i) { return ~((long long)(i[1]) << 32ULL | i[0]); } int dpii_f_int(int i) { return ~i; } char dpii_f_byte(char i) { return ~i; } short int dpii_f_shortint(short int i) { return ~i; } long long dpii_f_longint(long long i) { return ~i; } void* dpii_f_chandle(void* i) { return i; } const char* dpii_f_string(const char* i) { return i; } const char* dpii_f_null() { return nullptr; } double dpii_f_real(double i) { return i + 1.5; } float dpii_f_shortreal(float i) { return i + 1.5f; } void dpii_v_bit(unsigned char i, unsigned char* o) { *o = 1 & ~i; } void dpii_v_int(int i, int* o) { *o = ~i; } void dpii_v_uint(unsigned int i, unsigned int* o) { *o = ~i; } void dpii_v_byte(char i, char* o) { *o = ~i; } void dpii_v_shortint(short int i, short int* o) { *o = ~i; } void dpii_v_ushort(unsigned short i, unsigned short* o) { *o = ~i; } void dpii_v_longint(long long i, long long* o) { *o = ~i; } void dpii_v_ulong(unsigned long long i, unsigned long long* o) { *o = ~i; } void dpii_v_chandle(void* i, void** o) { *o = i; } void dpii_v_string(const char* i, const char** o) { *o = i; } void dpii_v_real(double i, double* o) { *o = i + 1.5; } void dpii_v_shortreal(float i, float* o) { *o = i + 1.5f; } void dpii_v_reg(unsigned char i, unsigned char* o) { *o = (~i) & 1; } void dpii_v_reg15(const svLogicVecVal* i, svLogicVecVal* o) { o[0].aval = (~i[0].aval) & 0x7fffUL; o[0].bval = 0; } void dpii_v_reg95(const svLogicVecVal* i, svLogicVecVal* o) { o[0].aval = (~i[0].aval); o[1].aval = (~i[1].aval); o[2].aval = (~i[2].aval) & 0x7fffffffUL; o[0].bval = 0; o[1].bval = 0; o[2].bval = 0; } void dpii_v_integer(const svLogicVecVal* i, svLogicVecVal* o) { o[0].aval = (~i[0].aval); o[0].bval = 0; } void dpii_v_time(const svLogicVecVal* i, svLogicVecVal* o) { o[0].aval = (~i[0].aval); o[1].aval = (~i[1].aval); o[0].bval = 0; o[1].bval = 0; } void dpii_v_struct(const svBitVecVal* i, svBitVecVal* o) { o[0] = ~i[0]; o[1] = ~i[1]; o[2] = ~i[2]; } void dpii_v_substruct(const svBitVecVal* i, int* o) { // To be most like other tools, this should automagically take the substruct_t // as an argument, and not require this cast... substruct_t* issp = (substruct_t*)i; o[0] = issp->b - issp->a; } void dpii_v_bit64(const svBitVecVal* i, svBitVecVal* o) { o[0] = ~i[0]; o[1] = ~i[1]; } void dpii_v_bit95(const svBitVecVal* i, svBitVecVal* o) { o[0] = (~i[0]); o[1] = (~i[1]); o[2] = (~i[2]) & 0x7fffffffUL; } void dpii_v_bit96(const svBitVecVal* i, svBitVecVal* o) { o[0] = ~i[0]; o[1] = ~i[1]; o[2] = ~i[2]; } int dpii_f_strlen(const char* i) { return strlen(i); } int dpii__under___score(int i) { return i + 1; } //====================================================================== void dpii_f_void() {} #ifdef VCS void dpii_t_void() {} void dpii_t_void_context() {} void dpii_t_int(int i, int* o) { *o = i; } #else int dpii_t_void() { return svIsDisabledState(); } int dpii_t_void_context() { return svIsDisabledState(); } int dpii_t_int(int i, int* o) { *o = i; bool disabled = svIsDisabledState(); // Tasks generally need this svAckDisabledState(); return disabled; } #endif int dpii_fa_bit(int i) { return ~i; } verilator-5.042/test_regress/t/t_altera_lpm_divide.py0000755000542200017500000000111115101701376023424 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) test.compile(verilator_flags2=["--top-module", module]) test.passes() verilator-5.042/test_regress/t/t_class_super_new2.py0000755000542200017500000000073415101701376023250 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_static_member_pkg.py0000755000542200017500000000073415101701376024636 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_debug_gate.v0000644000542200017500000000076315101701376021674 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Dotted reference that uses another dotted reference // as the select expression // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs o, // Inputs i ); input i; output o; sub sub (.i, .o); endmodule module sub(/*AUTOARG*/ // Outputs o, // Inputs i ); input i; output o; assign o = !i; endmodule verilator-5.042/test_regress/t/t_class_format.v0000644000542200017500000000214015101701376022252 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `ifdef verilator `define stop $stop `else `define stop `endif `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); class Cls; bit b; int i; bit [15:0] carray4 [4]; bit [64:0] cwide[2]; string name; real r; task debug(); $display("DEBUG: %s (@%0t) %s", this.name, $realtime, "message"); endtask endclass module t; initial begin Cls c; c = new; c.b = '1; c.i = 42; c.r = 2.2; c.name = "object_name"; c.carray4[0] = 16'h11; c.carray4[1] = 16'h22; c.carray4[2] = 16'h33; c.carray4[3] = 16'h44; $display("'%p'", c); c.carray4 = '{16'h911, 16'h922, 16'h933, 16'h944}; $display("'%p'", c); c.debug(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_func_no_parentheses_bad.v0000644000542200017500000000056615101701376024445 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 function static int func(); int cnt = 0; return ++cnt; endfunction module t; int a; initial begin a = func; $stop; end endmodule verilator-5.042/test_regress/t/t_no_std_pkg_bad.py0000755000542200017500000000122615101701376022724 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.top_filename = "t/t_no_std_bad.v" test.golden_filename = "t/t_no_std_bad.out" test.lint(fails=True, verilator_flags2=["--no-std-package", "--binary -Wall"], expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_trace_complex_fst_sc.out0000644000542200017500000001134415101701376024333 0ustar mahmoudyfreeshell$date Sat Apr 5 13:56:23 2025 $end $version fstWriter $end $timescale 1ps $end $scope module top $end $attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end $attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end $scope module $unit $end $var bit 1 ! global_bit $end $upscope $end $scope module t $end $var wire 1 " clk $end $var integer 32 # cyc [31:0] $end $var bit 2 $ v_strp [1:0] $end $var bit 4 % v_strp_strp [3:0] $end $var bit 2 & v_unip_strp [1:0] $end $var bit 2 ' v_arrp [2:1] $end $var bit 4 ( v_arrp_arrp [3:0] $end $var bit 4 ) v_arrp_strp [3:0] $end $var bit 1 * v_arru[1] $end $var bit 1 + v_arru[2] $end $var bit 1 , v_arru_arru[3][1] $end $var bit 1 - v_arru_arru[3][2] $end $var bit 1 . v_arru_arru[4][1] $end $var bit 1 / v_arru_arru[4][2] $end $var bit 2 0 v_arru_arrp[3] [2:1] $end $var bit 2 1 v_arru_arrp[4] [2:1] $end $var bit 2 2 v_arru_strp[3] [1:0] $end $var bit 2 3 v_arru_strp[4] [1:0] $end $var real 64 4 v_real $end $var real 64 5 v_arr_real[0] $end $var real 64 6 v_arr_real[1] $end $var longint 64 7 v_chandle [63:0] $end $var logic 64 8 v_str32x2 [63:0] $end $attrbegin misc 07 "" 1 $end $var int 32 9 v_enumed [31:0] $end $attrbegin misc 07 "" 1 $end $var int 32 : v_enumed2 [31:0] $end $attrbegin misc 07 "" 2 $end $var logic 3 ; v_enumb [2:0] $end $var logic 6 < v_enumb2_str [5:0] $end $var logic 8 = unpacked_array[-2] [7:0] $end $var logic 8 > unpacked_array[-1] [7:0] $end $var logic 8 ? unpacked_array[0] [7:0] $end $var bit 1 @ LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end $scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end $var parameter 32 A PARAM [31:0] $end $upscope $end $scope module p2 $end $var parameter 32 B PARAM [31:0] $end $upscope $end $scope module p3 $end $var parameter 32 C PARAM [31:0] $end $upscope $end $scope module unnamedblk1 $end $var integer 32 D b [31:0] $end $scope module unnamedblk2 $end $var integer 32 E a [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b00000000000000000000000000000000 E b00000000000000000000000000000000 D b00000000000000000000000000000011 C b00000000000000000000000000000010 B b00000000000000000000000000000100 A 0@ b00000000 ? b00000000 > b00000000 = b000000 < b000 ; b00000000000000000000000000000000 : b00000000000000000000000000000000 9 b0000000000000000000000000000000000000000000000000000000011111111 8 b0000000000000000000000000000000000000000000000000000000000000000 7 r0 6 r0 5 r0 4 b00 3 b00 2 b00 1 b00 0 0/ 0. 0- 0, 0+ 0* b0000 ) b0000 ( b00 ' b00 & b0000 % b00 $ b00000000000000000000000000000000 # 0" 1! $end #10 1" b00000000000000000000000000000001 # b11 $ b1111 % b11 & b11 ' b1111 ( b1111 ) b11 0 b11 1 b11 2 b11 3 r0.1 4 r0.2 5 r0.3 6 b0000000000000000000000000000000100000000000000000000000011111110 8 b00000000000000000000000000000001 9 b00000000000000000000000000000010 : b111 ; b00000000000000000000000000000101 D b00000000000000000000000000000101 E #15 0" #20 1" b110 ; b00000000000000000000000000000100 : b00000000000000000000000000000010 9 b0000000000000000000000000000001000000000000000000000000011111101 8 r0.6 6 r0.4 5 r0.2 4 b00 3 b00 2 b00 1 b00 0 b0000 ) b0000 ( b00 ' b00 & b0000 % b00 $ b00000000000000000000000000000010 # b111111 < #25 0" #30 1" b110110 < b00000000000000000000000000000011 # b11 $ b1111 % b11 & b11 ' b1111 ( b1111 ) b11 0 b11 1 b11 2 b11 3 r0.3 4 r0.6000000000000001 5 r0.8999999999999999 6 b0000000000000000000000000000001100000000000000000000000011111100 8 b00000000000000000000000000000011 9 b00000000000000000000000000000110 : b101 ; #35 0" #40 1" b100 ; b00000000000000000000000000001000 : b00000000000000000000000000000100 9 b0000000000000000000000000000010000000000000000000000000011111011 8 r1.2 6 r0.8 5 r0.4 4 b00 3 b00 2 b00 1 b00 0 b0000 ) b0000 ( b00 ' b00 & b0000 % b00 $ b00000000000000000000000000000100 # b101101 < #45 0" #50 1" b100100 < b00000000000000000000000000000101 # b11 $ b1111 % b11 & b11 ' b1111 ( b1111 ) b11 0 b11 1 b11 2 b11 3 r0.5 4 r1 5 r1.5 6 b0000000000000000000000000000010100000000000000000000000011111010 8 b00000000000000000000000000000101 9 b00000000000000000000000000001010 : b011 ; #55 0" #60 1" b010 ; b00000000000000000000000000001100 : b00000000000000000000000000000110 9 b0000000000000000000000000000011000000000000000000000000011111001 8 r1.8 6 r1.2 5 r0.6 4 b00 3 b00 2 b00 1 b00 0 b0000 ) b0000 ( b00 ' b00 & b0000 % b00 $ b00000000000000000000000000000110 # b011011 < #64 verilator-5.042/test_regress/t/t_sys_readmem_eof.py0000755000542200017500000000146115101701376023131 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') def gen(filename): # Generate using file to avoid missing newline in repository with open(filename, 'w', encoding="utf8") as fh: fh.write("// Generated by t_vthread.py\n") fh.write("1\n") fh.write("10\n") fh.write("20\n") fh.write("30") # No newline gen(test.obj_dir + "/dat.mem") test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_vlcov_nfound_bad.py0000755000542200017500000000123315101701376023275 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') test.run(fails=True, cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "t/t_NOT_FOUND"], logfile=test.run_log_filename, expect_filename=test.golden_filename, verilator_run=True) test.passes() verilator-5.042/test_regress/t/t_math_pow2.py0000755000542200017500000000073415101701376021672 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_extends_this3.v0000644000542200017500000000156415101701376023557 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef class Cls; class Base; class Inner; int value = 10; function void testBaseInner; if (value != 10) $stop; endfunction endclass int value = 1; Inner inner = new; function void testBase; if (value != 1) $stop; if (inner.value != 10) $stop; endfunction endclass class Cls extends Base; function void testDerived; if (value != 1) $stop; if (inner.value != 10) $stop; endfunction endclass module t; initial begin Cls c; c = new; c.testBase(); c.testDerived(); c.inner.testBaseInner(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_union_hard_bad.out0000644000542200017500000000054715101701376023104 0ustar mahmoudyfreeshell%Error: t/t_union_hard_bad.v:11:21: Hard packed union members must have equal size (IEEE 1800-2023 7.3.1) : ... note: In instance 't' 11 | bit [7 : 0] val1; | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_gated_clk_1.v0000644000542200017500000000305615101701376021741 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Test of gated clock detection // // The code as shown generates a result by a delayed assignment from PC. The // creation of the result is from a clock gated from the clock that sets // PC. Howevever since they are essentially the same clock, the result should // be delayed by one cycle. // // Standard Verilator treats them as different clocks, so the result stays in // step with the PC. An event drive simulator always allows the clock to win. // // The problem is caused by the extra loop added by Verilator to the // evaluation of all internally generated clocks (effectively removed by // marking the clock enable). // // This test is added to facilitate experiments with solutions. // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Jeremy Bennett . // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg gated_clk_en = 1'b0 ; reg [1:0] pc = 2'b0; reg [1:0] res = 2'b0; wire gated_clk = gated_clk_en & clk; always @(posedge clk) begin pc <= pc + 1; gated_clk_en <= 1'b1; end always @(posedge gated_clk) begin res <= pc; end always @(posedge clk) begin if (pc == 2'b11) begin // Correct behaviour is that res should be lagging pc in the count // by one cycle if (res == 2'b10) begin $write("*-* All Finished *-*\n"); $finish; end else begin $stop; end end end endmodule verilator-5.042/test_regress/t/t_interface_missing_bad.out0000644000542200017500000000106315101701376024441 0ustar mahmoudyfreeshell%Error: t/t_interface_missing_bad.v:14:4: Can't find typedef/interface: 'foo_intf' 14 | foo_intf foo | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_interface_missing_bad.v:20:4: Cannot find file containing interface: 'foo_intf' 20 | foo_intf the_foo (); | ^~~~~~~~ %Error: t/t_interface_missing_bad.v:25:15: Found definition of 'the_foo' as a CELL but expected a variable 25 | .foo (the_foo) | ^~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_process_propagation.v0000644000542200017500000000220015101701376023653 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 event evt1, evt2; class Foo; process p; bit event_received; function new(); p = process::self(); endfunction virtual task ewait(); @evt1 $display("Foo received event `evt1`"); event_received = 1; ->evt2; endtask endclass class Bar extends Foo; function new(); super.new(); $display("Constructing Bar"); endfunction virtual task ewait(); @evt1 $display("Bar received event `evt1`"); event_received = 1; endtask endclass module t(); initial begin process p; Foo foo; Bar bar; fork begin foo = new; foo.ewait(); end begin bar = new; p = process::self(); bar.ewait(); end join_none p.kill(); ->evt1; @evt2 begin if (!foo.event_received) $stop; if (bar.event_received) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_math_repl_bad.py0000755000542200017500000000076615101701376022560 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface_ref_trace_inlb.py0000755000542200017500000000132215101701376024742 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_ref_trace.v" test.golden_filename = "t/t_interface_ref_trace.out" test.compile(v_flags2=['+define+NO_INLINE_B'], verilator_flags2=['--trace-structs --trace-vcd']) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_order_a.v0000644000542200017500000000321415101701376021213 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t_order_a (/*AUTOARG*/ // Outputs m_from_clk_lev1_r, n_from_clk_lev2, o_from_com_levs11, o_from_comandclk_levs12, // Inputs clk, a_to_clk_levm3, b_to_clk_levm1, c_com_levs10, d_to_clk_levm2, one ); input clk; input [7:0] a_to_clk_levm3; input [7:0] b_to_clk_levm1; input [7:0] c_com_levs10; input [7:0] d_to_clk_levm2; input [7:0] one; output [7:0] m_from_clk_lev1_r; output [7:0] n_from_clk_lev2; output [7:0] o_from_com_levs11; output [7:0] o_from_comandclk_levs12; /*AUTOREG*/ // Beginning of automatic regs (for this module's undeclared outputs) reg [7:0] m_from_clk_lev1_r; // End of automatics // surefire lint_off ASWEBB // surefire lint_off ASWEMB wire [7:0] a_to_clk_levm1; wire [7:0] a_to_clk_levm2; wire [7:0] c_com_levs11; reg [7:0] o_from_comandclk_levs12; wire [7:0] n_from_clk_lev2; wire [7:0] n_from_clk_lev3; assign a_to_clk_levm1 = a_to_clk_levm2 + d_to_clk_levm2; assign a_to_clk_levm2 = a_to_clk_levm3 + 0; always @ (posedge clk) begin m_from_clk_lev1_r <= a_to_clk_levm1 + b_to_clk_levm1; end assign c_com_levs11 = c_com_levs10 + one; always @ (/*AS*/c_com_levs11 or n_from_clk_lev3) o_from_comandclk_levs12 = c_com_levs11 + n_from_clk_lev3; assign n_from_clk_lev2 = m_from_clk_lev1_r; assign n_from_clk_lev3 = n_from_clk_lev2; wire [7:0] o_from_com_levs11 = c_com_levs10 + 1; endmodule verilator-5.042/test_regress/t/t_enum_name3.v0000644000542200017500000000073015101701376021627 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014 by Jonathon Donaldson. // SPDX-License-Identifier: CC0-1.0 // bug855 module our; typedef enum logic {n,N} T_Flg_N; typedef struct packed { T_Flg_N N; } T_PS_Reg; T_PS_Reg PS = 1'b1; initial begin $write ("P:%s\n", PS.N.name); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_cover_toggle.v0000644000542200017500000001460115101701376022261 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef struct packed {logic a;} str_logic; module t (/*AUTOARG*/ // Inputs clk, check_real, check_array_real, check_string ); input clk; input real check_real; // Check issue #2741 input real check_array_real [1:0]; input string check_string; // Check issue #2766 typedef struct packed { union packed { logic ua; logic ub; } u; logic b; } str_t; reg toggle; initial toggle='0; logic _under_toggle = toggle; // For --coverage-underscore str_t stoggle; initial stoggle='0; str_logic strl; initial strl='0; union { real val1; // TODO use bit [7:0] here real val2; // TODO use bit [3:0] here } utoggle; const reg aconst = '0; reg [1:0][1:0] ptoggle; initial ptoggle=0; integer cyc; initial cyc=1; wire [7:0] cyc_copy = cyc[7:0]; wire toggle_up; typedef struct { int q[$]; } str_queue_t; str_queue_t str_queue; typedef struct packed { // verilator lint_off ASCRANGE bit [3:5] x; // verilator lint_on ASCRANGE bit [0:0] y; } str_bit_t; str_bit_t str_bit; str_bit_t [5:2] str_bit_arr; assign strl.a = clk; alpha a1 (/*AUTOINST*/ // Outputs .toggle_up (toggle_up), // Inputs .clk (clk), .toggle (toggle), .cyc_copy (cyc_copy[7:0])); alpha a2 (/*AUTOINST*/ // Outputs .toggle_up (toggle_up), // Inputs .clk (clk), .toggle (toggle), .cyc_copy (cyc_copy[7:0])); beta b1 (/*AUTOINST*/ // Inputs .clk (clk), .toggle_up (toggle_up)); off o1 (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle)); param#(1) p1 (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle)); param#() p2 (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle)); mod_struct i_mod_struct (/*AUTOINST*/ // Inputs .input_struct (strl)); reg [1:0] memory[121:110]; wire [1023:0] largeish = {992'h0, cyc}; // CHECK_COVER_MISSING(-1) always @ (posedge clk) begin if (cyc != 0) begin cyc <= cyc + 1; memory[cyc + 'd100] <= memory[cyc + 'd100] + 2'b1; toggle <= '0; stoggle.u <= toggle; stoggle.b <= toggle; utoggle.val1 <= real'(cyc[7:0]); ptoggle[0][0] <= toggle; if (cyc == 3) begin str_queue.q.push_back(1); toggle <= '1; str_bit.x <= '1; str_bit.y <= '1; str_bit_arr[4].x <= '1; end if (cyc == 4) begin if (str_queue.q.size() != 1) $stop; toggle <= '0; str_bit.x[3] <= 0; str_bit.y[0] <= 0; str_bit_arr[4].x[3] <= 0; end else if (cyc == 10) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module alpha (/*AUTOARG*/ // Outputs toggle_up, // Inputs clk, toggle, cyc_copy ); // t.a1 and t.a2 collapse to a count of 2 input clk; input toggle; // CHECK_COVER(-1,"top.t.a*","toggle:0->1",2) // CHECK_COVER(-2,"top.t.a*","toggle:1->0",2) // (t.a1 and t.a2) input [7:0] cyc_copy; // CHECK_COVER(-1,"top.t.a*","cyc_copy[0]:0->1",12) // CHECK_COVER(-2,"top.t.a*","cyc_copy[0]:1->0",10) // CHECK_COVER(-3,"top.t.a*","cyc_copy[1]:0->1",6) // CHECK_COVER(-4,"top.t.a*","cyc_copy[1]:1->0",4) // CHECK_COVER(-5,"top.t.a*","cyc_copy[2]:0->1",2) // CHECK_COVER(-6,"top.t.a*","cyc_copy[2]:1->0",2) // CHECK_COVER(-7,"top.t.a*","cyc_copy[3]:0->1",2) // CHECK_COVER(-8,"top.t.a*","cyc_copy[3]:1->0",0) // CHECK_COVER(-9,"top.t.a*","cyc_copy[4]:0->1",0) // CHECK_COVER(-10,"top.t.a*","cyc_copy[4]:1->0",0) // CHECK_COVER(-11,"top.t.a*","cyc_copy[5]:0->1",0) // CHECK_COVER(-12,"top.t.a*","cyc_copy[5]:1->0",0) // CHECK_COVER(-13,"top.t.a*","cyc_copy[6]:0->1",0) // CHECK_COVER(-14,"top.t.a*","cyc_copy[6]:1->0",0) // CHECK_COVER(-15,"top.t.a*","cyc_copy[7]:0->1",0) // CHECK_COVER(-16,"top.t.a*","cyc_copy[7]:1->0",0) reg toggle_internal; // CHECK_COVER(-1,"top.t.a*","toggle_internal:0->1",2) // CHECK_COVER(-2,"top.t.a*","toggle_internal:1->0",2) // (t.a1 and t.a2) output reg toggle_up; // CHECK_COVER(-1,"top.t.a*","toggle_up:0->1",2) // CHECK_COVER(-2,"top.t.a*","toggle_up:1->0",2) // (t.a1 and t.a2) always @ (posedge clk) begin toggle_internal <= toggle; toggle_up <= toggle; end endmodule module beta (/*AUTOARG*/ // Inputs clk, toggle_up ); input clk; input toggle_up; // CHECK_COVER(-1,"top.t.b1","toggle_up:0->1",1) // CHECK_COVER(-2,"top.t.b1","toggle_up:1->0",1) /* verilator public_module */ always @ (posedge clk) begin if (0 && toggle_up) begin end end endmodule module off (/*AUTOARG*/ // Inputs clk, toggle ); // verilator coverage_off input clk; // CHECK_COVER_MISSING(-1) // verilator coverage_on input toggle; // CHECK_COVER(-1,"top.t.o1","toggle:0->1",1) // CHECK_COVER(-2,"top.t.o1","toggle:1->0",1) endmodule module param #(parameter P = 2) (/*AUTOARG*/ // Inputs clk, toggle ); input clk; input toggle; logic z; for (genvar i = 0; i < P; i++) begin logic x; always @ (posedge clk) begin x <= toggle; end for (genvar j = 0; j < 3; j++) begin logic [2:0] y; always @ (negedge clk) begin y <= {toggle, ~toggle, 1'b1}; end end end if (P > 1) begin : gen_1 assign z = 1; end endmodule module mod_struct(/*AUTOARG*/ // Inputs input_struct ); input str_logic input_struct; endmodule verilator-5.042/test_regress/t/t_alias_transitive.v0000644000542200017500000000131015101701376023134 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias' // // Simple bi-directional transitive alias test. // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ // Inputs clk ); input clk; wire [31:0] a = 32'hdeadbeef; wire [31:0] b; wire [31:0] c; alias a = b = c; always @(posedge clk) begin `ifdef TEST_VERBOSE $write("a = %x, b = %x, c = %x\n", a, b, c); `endif if (a != 32'hdeadbeef) $stop; if (b != 32'hdeadbeef) $stop; if (c != 32'hdeadbeef) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_interface_derived_type.v0000644000542200017500000000302615101701376024304 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: SystemVerilog interface test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Iztok Jeras. // SPDX-License-Identifier: CC0-1.0 interface intf #( parameter type data_t = bit, parameter int arr[2][4] ) (); data_t data; // TODO -- some kind of issue with multi-dimensional array constness: // %Error: t/t_interface_derived_type.v:12:12: Expecting expression to be constant, but variable isn't const: 'arr' // : ... note: In instance 't.sub16' // 19 | logic [arr[0][0]-1:0] other_data; // | ^~~ // `define SHOW_2D_BUG `ifdef SHOW_2D_BUG logic [arr[0][0]-1:0] other_data; `else logic [$bits(data)-1:0] other_data; `endif endinterface module t (/*AUTOARG*/ // Inputs clk ); input clk; // finish report always @ (posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end sub #(.width(8), .arr('{'{8, 2, 3, 4}, '{1, 2, 3, 4}})) sub8 (); sub #(.width(16), .arr('{'{16, 2, 3, 4}, '{1, 2, 3, 4}})) sub16 (); endmodule module sub #( parameter int width, parameter int arr[2][4] ) (); typedef struct packed { logic [3:3] [0:0] [width-1:0] field; } user_type_t; intf #( .data_t(user_type_t), .arr(arr) ) the_intf (); logic [width-1:0] signal; always_comb begin the_intf.data.field = signal; the_intf.other_data = signal; end endmodule verilator-5.042/test_regress/t/t_vpi_release_dup_bad.py0000755000542200017500000000117515101701376023746 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(v_flags2=["t/" + test.name + "_c.cpp"], verilator_flags2=['--vpi']) test.execute(fails=True) test.file_grep(test.run_log_filename, r'vpi_release_handle.*called on same object twice') test.passes() verilator-5.042/test_regress/t/t_var_xref_bad.v0000644000542200017500000000044715101701376022227 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; task tsk; endtask initial tsk.bad_missing_ref = 0; endmodule verilator-5.042/test_regress/t/t_class_hier_construction.py0000755000542200017500000000073415101701376024720 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_display_concat2.v0000644000542200017500000000121515101701376022655 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module test( /*AUTOARG*/ // Inputs clk ); input clk; int cnt = 32'h12345678; int cyc = 0; always @(posedge clk) begin if (cyc > 3) begin $write("*-* All Finished *-*\n"); $finish; end else begin cyc <= cyc + 1; cnt <= cnt + 1; $write("%08x\n", {16'h0, cnt[15: 0]}); $write("%08x\n", {16'h0, cnt[31:16]}); end end endmodule verilator-5.042/test_regress/t/t_assert_synth_full.out0000644000542200017500000000057315101701376023717 0ustar mahmoudyfreeshell[0] -Info: t_assert_synth.v:115: top.t.test_info: Start of $info test [0] -Info: t_assert_synth.v:116: top.t.test_info: Middle of $info test [0] -Info: t_assert_synth.v:117: top.t.test_info: End of $info test [40] %Error: t_assert_synth.v:31: Assertion failed in top.t: synthesis full_case, but non-match found for '2'h3' %Error: t/t_assert_synth.v:31: Verilog $stop Aborting... verilator-5.042/test_regress/t/t_savable_open_bad2.cpp0000644000542200017500000000204215101701376023441 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include #include #include VM_PREFIX_INCLUDE // These require the above. Comment prevents clang-format moving them #include "TestCheck.h" //====================================================================== unsigned int main_time = 0; int errors = 0; double sc_time_stamp() { return main_time; } int main(int argc, char* argv[]) { Verilated::debug(0); Verilated::commandArgs(argc, argv); // No need to make a model: topp = new VM_PREFIX; { VerilatedSave os; os.open("/No/such_file_as_this"); TEST_CHECK_EQ(os.isOpen(), false); } { VerilatedRestore os; os.open("/No/such_file_as_this"); TEST_CHECK_EQ(os.isOpen(), false); } return errors ? 10 : 0; } verilator-5.042/test_regress/t/t_unopt_array.py0000755000542200017500000000101315101701376022324 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["-Wno-UNOPTFLAT", "-fno-dfg"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_order_dpi_export_6.v0000644000542200017500000000254115101701376023377 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2022 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module testbench( /*AUTOARG*/ // Inputs clk ); input clk; // Top level input clock bit other_clk; // Dependent clock set via DPI export "DPI-C" function set_other_clk; function void set_other_clk(bit val); other_clk = val; endfunction; bit even_other = 1; bit current_even_other = 1; import "DPI-C" context function void toggle_other_clk(bit val); always @(posedge clk) begin even_other <= ~even_other; current_even_other = even_other; toggle_other_clk(even_other); end int n = 0; always @(edge other_clk) begin // This always block needs to evaluate before the NBA to even_other // above is committed, as setting clocks via the set_other_clk uses // blocking assignment. if (even_other !== current_even_other) $stop; $display("[%0t] n=%0d", $time, n); if ($time != (2*n+1) * 500) $stop; if (n == 20) begin $write("*-* All Finished *-*\n"); $finish; end n += 1; end endmodule verilator-5.042/test_regress/t/t_premit_rw.py0000755000542200017500000000073515101701376022003 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() #test.execute() test.passes() verilator-5.042/test_regress/t/t_sys_readmem_bad_digit.mem0000644000542200017500000000053415101701376024411 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test data file // // Copyright 2006 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 a0 verilator-5.042/test_regress/t/t_wire_behp1800_bad.v0000644000542200017500000000136215101701376022665 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( output o, output [1:0] oa, output reg ro, output reg [1:0] roa, output wire wo, output wire [1:0] woa, // 1800 only output var vo, output var [1:0] voa ); wire w; reg r; initial begin w = '0; // Error o = '0; // Error oa = '0; // Error wo = '0; // Error woa = '0; // Error r = '0; // Not an error ro = '0; // Not an error roa = '0; // Not an error vo = '0; // Not an error voa = '0; // Not an error end endmodule verilator-5.042/test_regress/t/t_lint_paramnodefault.py0000755000542200017500000000077615101701376024030 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=['-Wno-PARAMNODEFAULT']) test.execute() test.passes() verilator-5.042/test_regress/t/t_config_include_bad.out0000644000542200017500000000124615101701376023723 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_config_include_bad.v:7:1: Unsupported: IEEE 1800-2001-config lib.map reserved word not implemented: 'include' : ... Suggest unless in a lib.map file, want `include instead 7 | include "meant_to_tick_include.v" | ^~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: t/t_config_include_bad.v:7:9: syntax error, unexpected STRING 7 | include "meant_to_tick_include.v" | ^~~~~~~~~~~~~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_trace_fst_sc.py0000755000542200017500000000117215101701376022426 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') if not test.have_sc: test.skip("No SystemC installed") test.compile(verilator_flags2=["--trace-fst --sc"]) test.execute() test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_mod_interface_array4_noinl.py0000755000542200017500000000104515101701376025246 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_mod_interface_array4.v" test.compile(v_flags2=["-fno-inline"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_force_bad_rw.v0000644000542200017500000000071415101701376022216 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; int ass[int]; initial begin ass[2] = 20; foreach (ass[index]) begin force index = 0; $display("ii %d\n", index); end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_static_elab.v0000644000542200017500000000213515101701376022053 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Simple static elaboration case // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 module t; typedef struct packed { logic [ 31 : 0 ] _five; } five_t; typedef enum { LOW_FIVE = 32'hdeadbeef, HIGH_FIVE } five_style_t; function five_t gimme_five (); automatic five_t result; result._five = 5; return result; endfunction function five_style_t gimme_high_five (); automatic five_style_t result; result = HIGH_FIVE; return result; endfunction localparam five_t FIVE = gimme_five(); localparam five_style_t THE_HIGH_FIVE = gimme_high_five(); initial begin if (FIVE._five != 5) begin $display("%%Error: Got 0b%b instead of 5", FIVE._five); $stop; end if (THE_HIGH_FIVE != HIGH_FIVE) begin $display("%%Error: Got 0b%b instead of HIGH_FIVE", THE_HIGH_FIVE); $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_flag_lib_dpi.v0000644000542200017500000000053615101701376022177 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Shupei Fan. // SPDX-License-Identifier: CC0-1.0 import "DPI-C" function void write_all_finished(); module t; initial begin write_all_finished; $finish; end endmodule verilator-5.042/test_regress/t/t_func_automatic_clear.v0000644000542200017500000000716215101701376023755 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Test automatic function variables lifetime // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Augustin Fabre. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); // Bug5747: Make sure that a variable with automatic storage is freshly // allocated when entering the function. module t(); function automatic int ts_queue(); static int qs[$]; qs.push_back(0); // $display(" qs: %p", qs); return qs.size(); endfunction function automatic int t_queue(); int q[$]; q.push_back(0); // $display(" q: %p", q); return q.size(); endfunction function automatic int t_scalar(); int x; ++x; return x; endfunction typedef struct { int y; } y_t; function automatic int t_struct(); y_t y; ++y.y; return y.y; endfunction function automatic string t_string(); string x; x = {x, "s"}; return x; endfunction class ClsZ; int z; endclass function automatic int t_class(); ClsZ z = new(); ++z.z; return z.z; endfunction typedef string dyn_t[]; function automatic dyn_t t_dyn(); dyn_t x; x = {x, "s"}; return x; endfunction typedef string assoc_t[int]; function automatic assoc_t t_assoc(); static int ins = 0; assoc_t x; ins = ins + 1; x[ins] = "s"; return x; endfunction typedef string wild_t[*]; function automatic wild_t t_wild(); static int ins = 0; wild_t x; ins = ins + 1; x[ins] = "s"; return x; endfunction typedef int unpack_t[8]; function automatic unpack_t t_unpack(); static int ins = 0; unpack_t x; ins = ins + 1; x[ins] = ins; return x; endfunction // ======================= function automatic void main(); for (int i = 0; i < 3; ++i) begin int qn = ts_queue(); int qo = ts_queue(); `checkh(qn, i * 2 + 1); `checkh(qo, i * 2 + 2); end for (int i = 0; i < 3; ++i) begin int qn = t_queue(); `checkh(qn, 1); end for (int i = 0; i < 3; ++i) begin int x = t_scalar(); `checkh(x, 1); end for (int i = 0; i < 3; ++i) begin int y = t_struct(); `checkh(y, 1); end for (int i = 0; i < 3; ++i) begin int z = t_class(); `checkh(z, 1); end for (int i = 0; i < 3; ++i) begin string z = t_string(); `checks(z, "s"); end for (int i = 0; i < 3; ++i) begin dyn_t z = t_dyn(); `checkh(z.size(), 1); end for (int i = 0; i < 3; ++i) begin assoc_t z = t_assoc(); `checkh(z.size(), 1); end for (int i = 0; i < 3; ++i) begin wild_t z = t_wild(); `checkh(z.size(), 1); end for (int i = 0; i < 3; ++i) begin int cnt; unpack_t z = t_unpack(); cnt = 0; for (int j = 0; j < $high(z); ++j) begin if (z[j] != 0) cnt = cnt + 1; end `checkh(cnt, 1); end endfunction initial begin main(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_flag_f__2.vc0000644000542200017500000000012415101701376021536 0ustar mahmoudyfreeshell +define+GOT_DEF1 // -DNON_DEF /* +define+NON_DEF */ +define+GOT_DEF2=1 verilator-5.042/test_regress/t/t_typedef_fwd_class.v0000644000542200017500000000114415101701376023265 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef logic [3:0] T; class Cls; extern static function int f(T x); // This is after the usage above, but to match other simulators, // no error about use after declaration typedef logic [7:0] T; endclass function int Cls::f(T x); return $bits(x); endfunction module t; initial begin if (Cls::f('1) != 8) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_func_wide_out.py0000755000542200017500000000111315101701376022614 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["-Wno-WIDTHTRUNC"], v_flags2=["+define+T_FUNC_WIDE_OUT t/t_func_wide_out_c.cpp"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_func_ref_bad.py0000755000542200017500000000103015101701376022355 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["-fno-var-split"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface_modport_noinl.py0000755000542200017500000000104215101701376024666 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_modport.v" test.compile(v_flags2=["-fno-inline"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_vpi_release_dup_bad_c.cpp0000644000542200017500000000224515101701376024376 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2011 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "svdpi.h" #include "vpi_user.h" #include //#include "verilated.h" #include "Vt_vpi_release_dup_bad__Dpi.h" //====================================================================== void dpii_check() { vpiHandle mod; // Not TestVpiHandle as testing double free // Verilated::scopesDump(); mod = vpi_handle_by_name((PLI_BYTE8*)"top.t", NULL); if (!mod) vpi_printf(const_cast("-- Cannot vpi_find module\n")); #ifdef VL_NO_LEGACY vpi_release_handle(mod); vpi_release_handle(mod); #else vpi_free_object(mod); // using vpi_free_object instead of vpi_release_handle for coverage vpi_free_object(mod); // error: double free #endif } verilator-5.042/test_regress/t/t_wrapper_del_context_bad.v0000644000542200017500000000040015101701376024450 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module top; initial $finish; endmodule verilator-5.042/test_regress/t/t_select_ascending.v0000644000542200017500000000444215101701376023076 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // verilator lint_off ASCRANGE wire [10:41] sel2 = crc[31:0]; wire [10:100] sel3 = {crc[26:0],crc}; wire out20 = sel2[{1'b0,crc[3:0]} + 11]; wire [3:0] out21 = sel2[13 : 16]; wire [3:0] out22 = sel2[{1'b0,crc[3:0]} + 20 +: 4]; wire [3:0] out23 = sel2[{1'b0,crc[3:0]} + 20 -: 4]; wire out30 = sel3[{2'b0,crc[3:0]} + 11]; wire [3:0] out31 = sel3[13 : 16]; wire [3:0] out32 = sel3[crc[5:0] + 20 +: 4]; wire [3:0] out33 = sel3[crc[5:0] + 20 -: 4]; // Aggregate outputs into a single result vector wire [63:0] result = {38'h0, out20, out21, out22, out23, out30, out31, out32, out33}; reg [19:50] sel1; initial begin // Path clearing // 122333445 // 826048260 sel1 = 32'h12345678; if (sel1 != 32'h12345678) $stop; if (sel1[47 : 50] != 4'h8) $stop; if (sel1[31 : 34] != 4'h4) $stop; if (sel1[27 +: 4] != 4'h3) $stop; //==[27:30], in memory as [23:20] if (sel1[26 -: 4] != 4'h2) $stop; //==[23:26], in memory as [27:24] end // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] sels=%x,%x,%x,%x %x,%x,%x,%x\n", $time, out20,out21,out22,out23, out30,out31,out32,out33); $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; `define EXPECTED_SUM 64'h28bf65439eb12c00 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_flag_main_top_name_empty.py0000755000542200017500000000132215101701376025001 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_flag_main_top_name.v" test.compile(verilator_flags=["-Mdir " + test.obj_dir, "--exe", "--build", "--main"], verilator_flags2=["--top-module top", "--main-top-name -", "-DMAIN_TOP_NAME_EMPTY"], make_main=False) test.execute() test.passes() verilator-5.042/test_regress/t/t_randsequence_bad.out0000644000542200017500000000103315101701376023422 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_randsequence_bad.v:12:7: Unsupported: randsequence 12 | randsequence(no_such_production) | ^~~~~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_randsequence_bad.v:16:7: Unsupported: randsequence 16 | randsequence(main) | ^~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_randsequence_bad.v:21:7: Unsupported: randsequence 21 | randsequence() | ^~~~~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_constraint_xml.py0000755000542200017500000000136415101701376023036 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') out_filename = test.obj_dir + "/V" + test.name + ".xml" test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only', '-Wno-CONSTRAINTIGN'], verilator_make_gmake=False, make_top_shell=False, make_main=False) test.files_identical(out_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_covergroup_with_sample_args_too_many_bad.py0000755000542200017500000000077415101701376030314 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_structu_dataType_assignment_bad.py0000755000542200017500000000103515101701376026367 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=['--structs-packed'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_inst_param_comma_bad.py0000755000542200017500000000076615101701376024116 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_force_release_net_trace.out0000644000542200017500000000431415101701376024766 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $var wire 1 # clk $end $scope module t $end $var wire 1 # clk $end $var wire 32 $ cyc [31:0] $end $var wire 1 % net_1 $end $var wire 8 & net_8 [7:0] $end $var wire 8 & alias_net_8 [7:0] $end $upscope $end $upscope $end $enddefinitions $end #0 0# b00000000000000000000000000000000 $ 1% b11111111 & #10 1# b00000000000000000000000000000001 $ 0% #15 0# #20 1# b00000000000000000000000000000010 $ 1% b11111110 & #25 0# #30 1# b00000000000000000000000000000011 $ 0% #35 0# #40 1# b00000000000000000000000000000100 $ b11111101 & #45 0# #50 1# b00000000000000000000000000000101 $ b01011111 & #55 0# #60 1# b00000000000000000000000000000110 $ 1% #65 0# #70 1# b00000000000000000000000000000111 $ b11110101 & #75 0# #80 1# b00000000000000000000000000001000 $ #85 0# #90 1# b00000000000000000000000000001001 $ 0% #95 0# #100 1# b00000000000000000000000000001010 $ 1% b11111010 & #105 0# #110 1# b00000000000000000000000000001011 $ b01011010 & #115 0# #120 1# b00000000000000000000000000001100 $ #125 0# #130 1# b00000000000000000000000000001101 $ 0% b10100101 & #135 0# #140 1# b00000000000000000000000000001110 $ #145 0# #150 1# b00000000000000000000000000001111 $ b11111000 & #155 0# #160 1# b00000000000000000000000000010000 $ 1% b11110111 & #165 0# #170 1# b00000000000000000000000000010001 $ 0% #175 0# #180 1# b00000000000000000000000000010010 $ 1% b11110110 & #185 0# #190 1# b00000000000000000000000000010011 $ 0% #195 0# #200 1# b00000000000000000000000000010100 $ 1% b11110101 & #205 0# #210 1# b00000000000000000000000000010101 $ 0% #215 0# #220 1# b00000000000000000000000000010110 $ 1% b11110100 & #225 0# #230 1# b00000000000000000000000000010111 $ 0% #235 0# #240 1# b00000000000000000000000000011000 $ 1% b11110011 & #245 0# #250 1# b00000000000000000000000000011001 $ 0% #255 0# #260 1# b00000000000000000000000000011010 $ 1% b11110010 & #265 0# #270 1# b00000000000000000000000000011011 $ 0% #275 0# #280 1# b00000000000000000000000000011100 $ 1% b11110001 & #285 0# #290 1# b00000000000000000000000000011101 $ 0% #295 0# #300 1# b00000000000000000000000000011110 $ 1% b11110000 & #305 0# #310 1# b00000000000000000000000000011111 $ 0% verilator-5.042/test_regress/t/t_probdist_bad.v0000644000542200017500000000207515101701376022240 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t; integer seed; integer r; initial begin // Illegal values r = $dist_chi_square(seed, 0); if (r != 0 && !$isunknown(r)) $stop; r = $dist_erlang(seed, 0, 0); if (r != 0 && !$isunknown(r)) $stop; r = $dist_exponential(seed, 0); if (r != 0 && !$isunknown(r)) $stop; // r =$dist_exponential(seed, mean); // Always valid r = $dist_poisson(seed, 0); if (r != 0 && !$isunknown(r)) $stop; r = $dist_t(seed, 0); if (r != 0 && !$isunknown(r)) $stop; r = $dist_uniform(seed, 10, 0); if (r != 10 && !$isunknown(r)) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_disable_genfor_unsup.out0000644000542200017500000000101215101701376024331 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_disable_genfor_unsup.v:13:23: Unsupported: Generate block referenced by disable 13 | if (i == 5) disable t.genblk[0].init.named; | ^~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_disable_genfor_unsup.v:13:23: Node of type CELLREF referenced by disable 13 | if (i == 5) disable t.genblk[0].init.named; | ^~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_strength_assignments_constants.v0000644000542200017500000000173715101701376026155 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; wire a; assign (weak0, weak1) a = 1; assign (weak0, supply1) a = 1; assign (strong0, strong1) a = 0; wire (weak0, weak1) b = 1; assign (strong0, strong1) b = 0; wire [1:0] c; assign (weak0, supply1) c = 2'b11; assign (supply0, pull1) c = 2'b11; assign (strong0, strong1) c = 0; wire [1:0] cr; assign (supply1, weak0) cr = 2'b11; assign (pull1, supply0) cr = 2'b11; assign (strong1, strong0) cr = 0; supply0 d; assign (strong0, strong1) d = 1; wire (supply0, supply1) e = 1'bz; assign (weak0, weak1) e = 1; always begin if (a !== 1'b1) $stop; if (b !== 1'b0) $stop; if (c !== 2'b11) $stop; if (cr !== 2'b11) $stop; if (e !== 1'b1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_func_const3_bad.out0000644000542200017500000000100415101701376023167 0ustar mahmoudyfreeshell%Warning-WIDTHCONCAT: t/t_func_const3_bad.v:12:28: More than a 8k bit replication is probably wrong: 9000 : ... note: In instance 't.b9k.c9' 12 | localparam SOMEP = {BITS{1'b0}}; | ^ ... For warning description see https://verilator.org/warn/WIDTHCONCAT?v=latest ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_mod_interface_array6_noinl.py0000755000542200017500000000104515101701376025250 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_mod_interface_array6.v" test.compile(v_flags2=["-fno-inline"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_notiming_off.py0000755000542200017500000000110215101701376022436 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_timing_off.v" test.lint(verilator_flags2=["--no-timing"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dpi_context_noopt.py0000755000542200017500000000114715101701376023530 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_dpi_context.v" test.compile(v_flags2=["t/t_dpi_context_c.cpp"], verilator_flags2=[("-O0" if test.vlt_all else "")]) test.execute() test.passes() verilator-5.042/test_regress/t/t_func_outfirst.v0000644000542200017500000000604315101701376022475 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define DDIFF_BITS 9 `define AOA_BITS 8 `define HALF_DDIFF `DDIFF_BITS'd256 `define MAX_AOA `AOA_BITS'd255 `define BURP_DIVIDER 9'd16 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [`DDIFF_BITS-1:0] DDIFF_B = crc[`DDIFF_BITS-1:0]; wire reset = (cyc<7); /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [`AOA_BITS-1:0] AOA_B; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .AOA_B (AOA_B[`AOA_BITS-1:0]), // Inputs .DDIFF_B (DDIFF_B[`DDIFF_BITS-1:0]), .reset (reset), .clk (clk)); // Aggregate outputs into a single result vector wire [63:0] result = {56'h0, AOA_B}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h3a74e9d34771ad93 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs AOA_B, // Inputs DDIFF_B, reset, clk ); input [`DDIFF_BITS-1:0] DDIFF_B; input reset; input clk; output reg [`AOA_BITS-1:0] AOA_B; reg [`AOA_BITS-1:0] AOA_NEXT_B; reg [`AOA_BITS-1:0] tmp; always @(posedge clk) begin if (reset) begin AOA_B <= 8'h80; end else begin AOA_B <= AOA_NEXT_B; end end always @* begin // verilator lint_off WIDTH tmp = ((`HALF_DDIFF-DDIFF_B)/`BURP_DIVIDER); t_aoa_update(AOA_NEXT_B, AOA_B, ((`HALF_DDIFF-DDIFF_B)/`BURP_DIVIDER)); // verilator lint_on WIDTH end task t_aoa_update; output [`AOA_BITS-1:0] aoa_reg_next; input [`AOA_BITS-1:0] aoa_reg; input [`AOA_BITS-1:0] aoa_delta_update; begin if ((`MAX_AOA-aoa_reg)= 0); endmodule verilator-5.042/test_regress/t/t_uniqueif_fail2.out0000644000542200017500000000021515101701376023042 0ustar mahmoudyfreeshell[10] %Error: t_uniqueif.v:82: Assertion failed in top.t: 'unique if' statement violated %Error: t/t_uniqueif.v:82: Verilog $stop Aborting... verilator-5.042/test_regress/t/t_std_randomize_mod.py0000755000542200017500000000074615101701376023476 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.lint(verilator_flags2=["--binary"]) test.passes() verilator-5.042/test_regress/t/t_order_blkandnblk_bad.v0000644000542200017500000000125515101701376023706 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Test of select from constant // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs o, // Inputs clk, i, idx ); input clk; input [3:0] i; input idx; output [3:0] o; logic [1:0][3:0] array; always_comb array[0] = i; always @ (posedge clk) array[0] <= array[0]; struct { logic [3:0] a; logic [3:0] b; } unpacked; always_comb unpacked.a = i; always @ (posedge clk) unpacked.b <= unpacked.a; assign o = array[idx] + unpacked.a; endmodule verilator-5.042/test_regress/t/t_math_cond_clean.v0000644000542200017500000000454615101701376022707 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [3:0] cnt = crc[3:0]; wire [6:0] decr = crc[14:8]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [3:0] next; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .next (next[3:0]), // Inputs .cnt (cnt[3:0]), .decr (decr[6:0])); // Aggregate outputs into a single result vector wire [63:0] result = {60'h0, next}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc<10) begin sum <= '0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h7cd85c944415d2ef if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs next, // Inputs cnt, decr ); input [3:0] cnt; input signed [6:0] decr; output reg [3:0] next; always_comb begin reg signed [6:0] tmp; tmp = 0; // verilator lint_off WIDTH tmp = ($signed({1'b0, cnt}) - decr); // verilator lint_on WIDTH if ((tmp > 15)) begin next = 15; end else if ((tmp < 0)) begin next = 0; end else begin next = tmp[3:0]; end end endmodule verilator-5.042/test_regress/t/t_dfg_peephole.py0000755000542200017500000000772315101701376022420 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.sim_time = 2000000 test.top_filename = "t/t_dfg_peephole.v" if not os.path.exists(test.root + "/.git"): test.skip("Not in a git repository") # Read optimizations optimizations = [] hdrFile = "../src/V3DfgPeepholePatterns.h" with open(hdrFile, 'r', encoding="utf8") as hdrFh: prevOpt = "" lineno = 0 for line in hdrFh: lineno += 1 m = re.search(r'^\s*_FOR_EACH_DFG_PEEPHOLE_OPTIMIZATION_APPLY\(macro, (\w+)\)', line) if not m: continue opt = m.group(1) if prevOpt > opt: test.error(hdrFile + ":" + str(lineno) + ": '" + opt + "; is not in sorted order") prevOpt = opt optimizations.append(opt) if len(optimizations) < 1: test.error("no optimizations defined in " + hdrFile) # Generate the equivalence checks and declaration boilerplate rdFile = test.top_filename plistFile = test.obj_dir + "/portlist.vh" pdeclFile = test.obj_dir + "/portdecl.vh" checkFile = test.obj_dir + "/checks.h" with open(rdFile, 'r', encoding="utf8") as rdFh, \ open(plistFile, 'w', encoding="utf8") as plistFh, \ open(pdeclFile, 'w', encoding="utf8") as pdeclFh, \ open(checkFile, 'w', encoding="utf8") as checkFh: for line in rdFh: m = re.search(r'^\s*.*`signal\((\w+),', line) if not m: continue sig = m.group(1) plistFh.write(sig + ",\n") pdeclFh.write("output " + sig + ";\n") checkFh.write("if (ref." + sig + " != opt." + sig + ") {\n") checkFh.write(" std::cout << \"Mismatched " + sig + "\" << std::endl;\n") checkFh.write(" std::cout << \"Ref: 0x\" << std::hex << (ref." + sig + " + 0) << std::endl;\n") checkFh.write(" std::cout << \"Opt: 0x\" << std::hex << (opt." + sig + " + 0) << std::endl;\n") checkFh.write(" std::exit(1);\n") checkFh.write("}\n") # Compile un-optimized test.compile(verilator_flags2=[ "--stats", "--build", "-fno-dfg", "+incdir+" + test.obj_dir, "-Mdir", test.obj_dir + "/obj_ref", "--prefix", "Vref" ]) # yapf:disable # Compile optimized - also builds executable extraArgs = [] if test.name == "t_dfg_peephole_off_all": extraArgs.append("-fno-dfg-peephole") if test.name == "t_dfg_peephole_off_each": for opt in optimizations: opt = opt.lower() opt = re.sub(r"_", "-", opt) extraArgs.append("-fno-dfg-peephole-" + opt) test.compile(verilator_flags2=[ "--stats", "--build", "--exe", "+incdir+" + test.obj_dir, "-Mdir", test.obj_dir + "/obj_opt", "--prefix", "Vopt", "-fno-const-before-dfg", # Otherwise V3Const makes testing painful "-fdfg-synthesize-all", "--dump-dfg", # To fill code coverage "-CFLAGS \"-I .. -I ../obj_ref\"", "../obj_ref/Vref__ALL.a", "../../t/t_dfg_peephole.cpp" ] + extraArgs) # yapf:disable def check(name, enabled): name = name.lower() name = re.sub(r'_', ' ', name) pattern = r'DFG\s+(pre inline|post inline|scoped) Peephole, ' + name + r'\s+([1-9]\d*)\s*$' if enabled: test.file_grep(test.obj_dir + "/obj_opt/Vopt__stats.txt", pattern) else: test.file_grep_not(test.obj_dir + "/obj_opt/Vopt__stats.txt", pattern) # Check all optimizations defined in for opt in optimizations: check(opt, test.name == "t_dfg_peephole") test.file_grep_not(test.obj_dir + "/obj_opt/Vopt__stats.txt", r'DFG.*non-representable.*\s[1-9]\d*$') # Execute test to check equivalence test.execute(executable=test.obj_dir + "/obj_opt/Vopt") test.passes() verilator-5.042/test_regress/t/t_genfor_init_o0.py0000755000542200017500000000101315101701376022662 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=['-O0'], make_main=False, verilator_make_gmake=False) test.passes() verilator-5.042/test_regress/t/t_assert_unique_case.out0000644000542200017500000000172215101701376024026 0ustar mahmoudyfreeshell[0] %Error: t_assert_unique_case_bad.v:56: Assertion failed in top.t: priority case, but non-match found match_item0 [20] %Error: t_assert_unique_case_bad.v:47: Assertion failed in top.t: unique case, but none matched match_item0 match_item0 [40] %Error: t_assert_unique_case_bad.v:47: Assertion failed in top.t: unique case, but none matched match_item0 match_item0 [60] %Error: t_assert_unique_case_bad.v:47: Assertion failed in top.t: unique case, but none matched match_item0 match_item0 [80] %Error: t_assert_unique_case_bad.v:47: Assertion failed in top.t: unique case, but none matched match_item0 [90] %Error: t_assert_unique_case_bad.v:47: Assertion failed in top.t: unique case, but none matched match_item0 [90] %Error: t_assert_unique_case_bad.v:38: Assertion failed in top.t: unique case, but multiple matches found for '12'h388' *-* All Finished *-* [100] %Error: t_assert_unique_case_bad.v:47: Assertion failed in top.t: unique case, but none matched match_item0 verilator-5.042/test_regress/t/t_var_overwidth_bad.v0000644000542200017500000000077615101701376023303 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2010 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; always @ (posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_debug_emitv.py0000755000542200017500000000241015101701376022255 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios("vlt") test.lint( # We also have dump-tree turned on, so hit a lot of AstNode*::dump() functions # Likewise XML v_flags=[ "--lint-only --timing", "--dumpi-tree 9 --dumpi-V3EmitV 9 --debug-emitv", # Dev coverage of the V3EmitV code "--dump-graph --dumpi-tree-json 9 --no-json-ids" ]) output_vs = test.glob_some(test.obj_dir + "/" + test.vm_prefix + "_*_width.tree.v") for output_v in output_vs: test.files_identical(output_v, test.golden_filename) if test.verbose: # Print if that the output Verilog is clean # TODO not yet round-trip clean test.run( cmd=[ os.environ["VERILATOR_ROOT"] + "/bin/verilator", "--lint-only", output_vs[0], ], logfile=test.obj_dir + "/sim_roundtrip.log", fails=True, verilator_run=True, ) test.passes() verilator-5.042/test_regress/t/t_mem_first.v0000644000542200017500000000675415101701376021601 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer _mode; initial _mode = 0; // verilator lint_off ASCRANGE reg [7:0] mem_narrow [0:31]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM reg [77:0] mem_wide [1024:0]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM reg [7:0] mem_dly_narrow [0:1]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM reg [77:0] mem_dly_wide [1:0]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM reg [34:0] vec_wide; // verilator lint_on ASCRANGE reg [31:0] wrd0 [15:0]; wire [3:0] sel = 4'h3; wire [31:0] selout = wrd0[sel]; // Must take LSBs into account in bit extract widths. wire [15:14] sixt = 2'b10; // surefire lint_off_line ASWCBB wire [16:14] sixt2 = 3'b110; // surefire lint_off_line ASWCBB wire [3:0] sixfrom = 13; wire [4:0] sixfrom2 = 16; wire sixtext = sixt[sixfrom]; wire sixtext2 = sixt2[sixfrom2]; // Non-power of 2 memory overwriting checks reg [2:0] np2_mem [5:0] /*verilator public*/; reg [2:0] np2_guard [7:6] /*verilator public*/; integer i; always @ (posedge clk) begin if (_mode!=0) begin wrd0[0] = 32'h1; // for (i=0; i<32; i=i+1) begin //surefire lint_off_line STMFOR mem_narrow[i] = i[7:0]; mem_wide[i] = {i[7:0],70'hfeed}; end // for (i=0; i<32; i=i+1) begin //surefire lint_off_line STMFOR if (mem_narrow[i] !== i[7:0]) $stop; if (mem_wide[i] !== {i[7:0],70'hfeed}) $stop; end // vec_wide <= 0; // np2_guard[6] = 0; np2_guard[7] = 0; // $write("selout %b %b %b\n", selout, sixtext, sixtext2); end if (_mode == 1) begin _mode <= 2; // i=0; mem_dly_narrow[0] <= ~i[7:0]; mem_dly_wide[0] <= {~i[7:0],70'hface}; i=1; mem_dly_narrow[i] <= ~i[7:0]; mem_dly_wide[i] <= {~i[7:0],70'hface}; // for (i=0; i<16; i=i+1) begin //surefire lint_off_line STMFOR // verilator lint_off width np2_mem[i] = i[2:0]; // surefire lint_off_line ASWSBB // verilator lint_on width if (np2_guard[6]!=0 || np2_guard[7]!=0) $stop; end // verilator lint_off SELRANGE if (np2_mem[6] !== np2_mem[7]) begin $write("Mem[6]!=Mem[7] during randomize...\n"); //$stop; // Random value, so this can happen end // verilator lint_on SELRANGE //if (np2_mem[8] !== np2_mem[9]) $stop; // Enhancement: Illegal indexes, make sure map to X's // vec_wide[32:31] <= 2'b11; vec_wide[34] <= 1'b1; $display("%x",vec_wide); end if (_mode == 2) begin _mode <= 3; // for (i=0; i<2; i=i+1) begin //surefire lint_off_line STMFOR if (mem_dly_narrow[i] !== ~i[7:0]) $stop; if (mem_dly_wide[i] !== {~i[7:0],70'hface}) $stop; end // //$write ("VW %x %x\n", vec_wide[34:32], vec_wide[31:0]); if (vec_wide != {4'b101_1,31'd0}) $stop; // $write("*-* All Finished *-*\n"); $finish; end _mode <= _mode + 1; end endmodule verilator-5.042/test_regress/t/t_inst_wideconst.v0000644000542200017500000000270715101701376022642 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg [41:0] aaa; wire [41:0] bbb; // verilator public_module wire [41:0] z_0; wire [41:0] z_1; wide w_0( .xxx( { {40{1'b0}},2'b11 } ), .yyy( aaa[1:0] ), .zzz( z_0 ) ); wide w_1( .xxx( aaa ), .yyy( 2'b10 ), .zzz( z_1 ) ); assign bbb= z_0 + z_1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin aaa <= 42'b01; end if (cyc==2) begin aaa <= 42'b10; if (z_0 != 42'h4) $stop; if (z_1 != 42'h3) $stop; end if (cyc==3) begin if (z_0 != 42'h5) $stop; if (z_1 != 42'h4) $stop; end if (cyc==4) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module wide ( input [41:0] xxx, input [1:0] yyy, output [41:0] zzz ); // verilator public_module assign zzz = xxx+ { {40{1'b0}},yyy }; endmodule verilator-5.042/test_regress/t/t_dfg_3676.py0000755000542200017500000000070615101701376021216 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.passes() verilator-5.042/test_regress/t/t_timing_fork_no_timing_ctrl.py0000755000542200017500000000077115101701376025372 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_inst_tree_inl0_pub1.vlt0000644000542200017500000000042215101701376024003 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. // SPDX-License-Identifier: CC0-1.0 `verilator_config no_inline -module "l*" public -module "l*" -var "z*" verilator-5.042/test_regress/t/t_fork_label_timing.py0000755000542200017500000000106115101701376023433 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_fork_label.v" test.compile(verilator_flags2=["--binary"], make_main=False) test.execute() test.passes() verilator-5.042/test_regress/t/t_tri_compass_bad.py0000755000542200017500000000076315101701376023125 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_trace_packed_struct.v0000644000542200017500000000160715101701376023615 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Andrew Bardsley. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; int cnt; // This won't compile with tracing as an incorrect declaration is made for // the temp variables used to represent the elements of localparam v typedef struct packed { logic [2:0][31:0] a; } t; localparam t v[2:0] = '{ '{'{32'h10000002, 32'h10000001, 32'h10000000}}, '{'{32'h20000002, 32'h20000001, 32'h20000000}}, '{'{32'h30000002, 32'h30000001, 32'h30000000}} }; initial cnt = 0; always@(posedge clk) begin if (cnt < 3) begin cnt = cnt + 1; end else begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_flag_parameter_hier.v0000644000542200017500000000307015101701376023560 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2016 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define check(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: %m: Wrong parameter value\n", `__FILE__,`__LINE__); `stop; end while(0); module t (/*AUTOARG*/ // Inputs clk ); input clk; u u (); tx x (); parameter PARAM = 0; parameter HIER = 0; initial begin $display("%m PARAM=%0d HIER=%0d", PARAM, HIER); `ifdef IVERILOG `check(PARAM, 0); `elsif NC `check(PARAM, 0); `elsif VCS `check(PARAM, 10); `else `check(PARAM, 10); `endif `check(HIER, 0); end always @ (posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule module u; ux x(); endmodule module ux; parameter PARAM = 0; parameter HIER = 0; initial begin $display("%m PARAM=%0d HIER=%0d", PARAM, HIER); `ifdef IVERILOG `check(PARAM, 0); `elsif NC `check(PARAM, 0); `elsif VCS `check(PARAM, 10); `else `check(PARAM, 0); `endif `check(HIER, 0); end endmodule module tx; parameter PARAM = 0; parameter HIER = 0; initial begin $display("%m PARAM=%0d HIER=%0d", PARAM, HIER); `ifdef IVERILOG `check(PARAM, 0); `elsif NC `check(PARAM, 10); `elsif VCS `check(PARAM, 10); `else `check(PARAM, 0); `endif `ifdef NC `check(HIER, 20); `else `check(HIER, 0); `endif end endmodule verilator-5.042/test_regress/t/t_math_pow6.v0000644000542200017500000000266015101701376021510 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs i65, j65, i33, j33, i30, j30, q65, r65, q33, r33, q30, r30, w65, x65, w33, x33, w30, x30, // Inputs a, a40, a70 ); input [3:0] a; input [39:0] a40; input [69:0] a70; // -- Verilator 621c515 creates code that uses the undeclared function VL_POW_WWI() // verilator lint_off WIDTH output [3:0] i65 = 65'd3 ** a; // IWI output [3:0] j65 = a ** 65'd3; // IIW output [3:0] i33 = 33'd3 ** a; // QQI output [3:0] j33 = a ** 33'd3; // IIQ output [3:0] i30 = 30'd3 ** a; // III output [3:0] j30 = a ** 30'd3; // III output [39:0] q65 = 65'd3 ** a40; // WWQ output [39:0] r65 = a40 ** 65'd3; // WWQ output [39:0] q33 = 33'd3 ** a40; // QQQ output [39:0] r33 = a40 ** 33'd3; // QQQ output [39:0] q30 = 30'd3 ** a40; // QQI output [39:0] r30 = a40 ** 30'd3; // QQI output [69:0] w65 = 65'd3 ** a70; // WWW output [69:0] x65 = a70 ** 65'd3; // WWW output [69:0] w33 = 33'd3 ** a70; // WWW output [69:0] x33 = a70 ** 33'd3; // WWW output [69:0] w30 = 30'd3 ** a70; // WWW output [69:0] x30 = a70 ** 30'd3; // WWW // verilator lint_on WIDTH initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_stream_unpack_lhs.v0000644000542200017500000001345415101701376023311 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // Ref. to IEEE Std 1800-2017 11.4.14 & A.8.1 // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Victor Besyakov. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; // 1D packed array into concatenation logic [32-1:0] concat_din; logic [8-1:0] concat4_dout3, concat4_dout2, concat4_dout1, concat4_dout0; // same size logic [8-1:0] concat3_dout3, concat3_dout2, concat3_dout1 ; // smaller logic [8-1:0] concat5_dout4, concat5_dout3, concat5_dout2, concat5_dout1, concat5_dout0; // larger // 2D packed array into unpacked array /* verilator lint_off ASCRANGE */ logic [0:4-1][8-1:0] packed_siz_din; logic [0:4-1][8-1:0] packed_asc_din; /* verilator lint_on ASCRANGE */ logic [4-1:0][8-1:0] packed_des_din; logic [8-1:0] unpacked_siz_dout [4]; logic [8-1:0] unpacked_asc_dout [0:4-1]; logic [8-1:0] unpacked_des_dout [4-1:0]; // 2D unpacked array into packed array logic [8-1:0] unpacked_siz_din [4]; logic [8-1:0] unpacked_asc_din [0:4-1]; logic [8-1:0] unpacked_des_din [4-1:0]; /* verilator lint_off ASCRANGE */ logic [0:4-1][8-1:0] packed_siz_dout; logic [0:4-1][8-1:0] packed_asc_dout; /* verilator lint_on ASCRANGE */ logic [4-1:0][8-1:0] packed_des_dout; // 2D packed array into queue logic [8-1:0] packed_siz_queue_dout [$]; logic [8-1:0] packed_asc_queue_dout [$]; logic [8-1:0] packed_des_queue_dout [$]; // 2D unpacked array into queue logic [8-1:0] unpacked_siz_queue_dout [$]; logic [8-1:0] unpacked_asc_queue_dout [$]; logic [8-1:0] unpacked_des_queue_dout [$]; integer cyc = 1; always_comb begin // 1D packed array into concatenation {>>{ concat4_dout3, concat4_dout2, concat4_dout1, concat4_dout0}} = concat_din; /* verilator lint_off WIDTHTRUNC */ {>>{ concat3_dout3, concat3_dout2, concat3_dout1 }} = concat_din; /* verilator lint_on WIDTHTRUNC */ /* verilator lint_off WIDTHEXPAND */ {>>{concat5_dout4, concat5_dout3, concat5_dout2, concat5_dout1, concat5_dout0}} = concat_din; /* verilator lint_on WIDTHEXPAND */ // 2D packed array into unpacked array {>>{unpacked_siz_dout}} = packed_asc_din; {>>{unpacked_asc_dout}} = packed_asc_din; {>>{unpacked_des_dout}} = packed_des_din; // 2D unpacked array into packed array {>>{packed_siz_dout}} = unpacked_siz_din; {>>{packed_asc_dout}} = unpacked_asc_din; {>>{packed_des_dout}} = unpacked_des_din; // 2D packed array into queue {>>{packed_siz_queue_dout}} = packed_siz_din; {>>{packed_asc_queue_dout}} = packed_asc_din; {>>{packed_des_queue_dout}} = packed_des_din; // 2D unpacked array into queue {>>{unpacked_siz_queue_dout}} = unpacked_siz_din; {>>{unpacked_asc_queue_dout}} = unpacked_asc_din; {>>{unpacked_des_queue_dout}} = unpacked_des_din; end always @(posedge clk) begin if (cyc != 0) begin cyc <= cyc + 1; if (cyc == 1) begin // 1D packed array into concatenation concat_din <= 32'h76543210; // 2D packed array into unpacked array packed_siz_din <= '{8'h01, 8'h23, 8'h45, 8'h67}; packed_asc_din <= '{8'h01, 8'h23, 8'h45, 8'h67}; packed_des_din <= '{8'h76, 8'h54, 8'h32, 8'h10}; // 2D unpacked array into packed array unpacked_siz_din <= '{8'h01, 8'h23, 8'h45, 8'h67}; unpacked_asc_din <= '{8'h01, 8'h23, 8'h45, 8'h67}; unpacked_des_din <= '{8'h76, 8'h54, 8'h32, 8'h10}; end if (cyc == 2) begin // 1D packed array into concatenation (same size) if (concat4_dout0 != 8'h10) $stop; if (concat4_dout1 != 8'h32) $stop; if (concat4_dout2 != 8'h54) $stop; if (concat4_dout3 != 8'h76) $stop; // 1D packed array into concatenation (smaller) if (concat3_dout1 != 8'h32) $stop; if (concat3_dout2 != 8'h54) $stop; if (concat3_dout3 != 8'h76) $stop; // 1D packed array into concatenation (larger) if (concat5_dout0 != 8'h00) $stop; if (concat5_dout1 != 8'h10) $stop; if (concat5_dout2 != 8'h32) $stop; if (concat5_dout3 != 8'h54) $stop; if (concat5_dout4 != 8'h76) $stop; // 2D packed array into unpacked array if (unpacked_siz_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; if (unpacked_asc_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; if (unpacked_des_dout != '{8'h76, 8'h54, 8'h32, 8'h10}) $stop; // 2D unpacked array into packed array if (packed_siz_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; if (packed_asc_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; if (packed_des_dout != '{8'h76, 8'h54, 8'h32, 8'h10}) $stop; // 2D packed array into queue if (packed_siz_queue_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; if (packed_asc_queue_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; if (packed_des_queue_dout != '{8'h76, 8'h54, 8'h32, 8'h10}) $stop; // 2D unpacked array into queue if (unpacked_siz_queue_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; if (unpacked_asc_queue_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; if (unpacked_des_queue_dout != '{8'h76, 8'h54, 8'h32, 8'h10}) $stop; end if (cyc == 3) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.042/test_regress/t/t_preproc_eof2_bad.py0000755000542200017500000000076615101701376023172 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dpi_open_c.cpp0000644000542200017500000002721315101701376022221 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2017 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "svdpi.h" #include #include #include // These require the above. Comment prevents clang-format moving them #include "TestCheck.h" //====================================================================== // clang-format off #if defined(VERILATOR) # include "Vt_dpi_open__Dpi.h" #elif defined(VCS) # include "../vc_hdrs.h" #elif defined(NC) # define NEED_EXTERNS // #elif defined(MS) // # define NEED_EXTERNS #else # error "Unknown simulator for DPI test" #endif // clang-format on #ifdef NEED_EXTERNS extern "C" { // If get ncsim: *F,NOFDPI: Function {foo} not found in default libdpi. // Then probably forgot to list a function here. extern void dpii_unused(const svOpenArrayHandle u); extern void dpii_open_p0_u1(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_p1_u0(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_p1_u1(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_p1_u2(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_p1_u3(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_pw_u0(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_pw_u1(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_pw_u2(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_pw_u3(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_bit(const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_byte(const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_int(const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_integer(const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_logic(const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_int_u1(int u, const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_int_u2(int u, const svOpenArrayHandle i, const svOpenArrayHandle o); extern void dpii_open_int_u3(int u, const svOpenArrayHandle i, const svOpenArrayHandle o); extern int dpii_failure(); } #endif int errors = 0; int dpii_failure() { return errors; } void dpii_unused(const svOpenArrayHandle u) {} void _dpii_all(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o) { #ifdef TEST_VERBOSE fprintf(stderr, "-:%s:%d: For case c=%d p=%d u=%d data=%p\n", // __FILE__, __LINE__, c, p, u, svGetArrayPtr(i)); #endif (void)svGetArrayPtr(i); #ifndef NC // NC always returns zero and warns (void)svSizeOfArray(i); #endif #ifndef VCS // VCS does not support dimension 0 query if (p) { int d = 0; if (c == 0 || c == 1) { TEST_CHECK_HEX_EQ(svLeft(i, d), 1); TEST_CHECK_HEX_EQ(svRight(i, d), -1); TEST_CHECK_HEX_EQ(svLow(i, d), -1); TEST_CHECK_HEX_EQ(svHigh(i, d), 1); // TEST_CHECK_HEX_EQ(svIncrement(i, d), 0); TEST_CHECK_HEX_EQ(svSize(i, d), 3); } else if (c == 2) { TEST_CHECK_HEX_EQ(svLeft(i, d), 95); TEST_CHECK_HEX_EQ(svRight(i, d), 1); TEST_CHECK_HEX_EQ(svLow(i, d), 1); TEST_CHECK_HEX_EQ(svHigh(i, d), 95); // TEST_CHECK_HEX_EQ(svIncrement(i, d), 0); TEST_CHECK_HEX_EQ(svSize(i, d), 95); } else { TEST_CHECK_HEX_EQ(0, 1); } } #endif if (u >= 1) { int d = 1; if (c == 0) { TEST_CHECK_HEX_EQ(svLeft(i, d), -2); TEST_CHECK_HEX_EQ(svRight(i, d), 2); TEST_CHECK_HEX_EQ(svLow(i, d), -2); TEST_CHECK_HEX_EQ(svHigh(i, d), 2); // TEST_CHECK_HEX_EQ(svIncrement(i, d), 0); TEST_CHECK_HEX_EQ(svSize(i, d), 5); } else if (c == 1) { TEST_CHECK_HEX_EQ(svLeft(i, d), 2); TEST_CHECK_HEX_EQ(svRight(i, d), -2); TEST_CHECK_HEX_EQ(svLow(i, d), -2); TEST_CHECK_HEX_EQ(svHigh(i, d), 2); // TEST_CHECK_HEX_EQ(svIncrement(i, d), 0); TEST_CHECK_HEX_EQ(svSize(i, d), 5); } } if (u >= 2) { int d = 2; if (c == 0) { TEST_CHECK_HEX_EQ(svLeft(i, d), -3); TEST_CHECK_HEX_EQ(svRight(i, d), 3); TEST_CHECK_HEX_EQ(svLow(i, d), -3); TEST_CHECK_HEX_EQ(svHigh(i, d), 3); // TEST_CHECK_HEX_EQ(svIncrement(i, d), 0); TEST_CHECK_HEX_EQ(svSize(i, d), 7); } else if (c == 1) { TEST_CHECK_HEX_EQ(svLeft(i, d), 3); TEST_CHECK_HEX_EQ(svRight(i, d), -3); TEST_CHECK_HEX_EQ(svLow(i, d), -3); TEST_CHECK_HEX_EQ(svHigh(i, d), 3); // TEST_CHECK_HEX_EQ(svIncrement(i, d), 0); TEST_CHECK_HEX_EQ(svSize(i, d), 7); } } #ifdef VERILATOR // Check out-of-bounds read doesn't access bad memory (when sanitizer used) (void)svLeft(i, -1); (void)svRight(i, -1); (void)svLow(i, -1); (void)svHigh(i, -1); (void)svIncrement(i, -1); (void)svSize(i, -1); // (void)svLeft(i, 99); (void)svRight(i, 99); (void)svLow(i, 99); (void)svHigh(i, 99); (void)svIncrement(i, 99); (void)svSize(i, 99); #endif if (c == 2 && p == 1 && u == 3) { for (int a = svLow(i, 1); a <= svHigh(i, 1); ++a) { for (int b = svLow(i, 2); b <= svHigh(i, 2); ++b) { for (int c = svLow(i, 3); c <= svHigh(i, 3); ++c) { // printf("Copy abc %d,%d,%d\n", a,b,c); svLogicVecVal vec[3]; svGetLogicArrElemVecVal(vec, i, a, b, c); #ifdef NC // printf(" %08lx_%08lx_%08lx\n", vec[2].a, vec[1].a, vec[0].a); vec[0].a = (~vec[0].a); vec[1].a = (~vec[1].a); vec[2].a = (~vec[2].a) & 0x7fffffff; // vec[0].b = vec[0].b; // vec[1].b = vec[1].b; // vec[2].b = vec[2].b; #else vec[0].aval = (~vec[0].aval); vec[1].aval = (~vec[1].aval); vec[2].aval = (~vec[2].aval) & 0x7fffffff; // vec[0].bval = vec[0].bval; // vec[1].bval = vec[1].bval; // vec[2].bval = vec[2].bval; #endif svPutLogicArrElemVecVal(o, vec, a, b, c); } } } } } void dpii_open_p0_u1(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o) { _dpii_all(c, p, u, i, o); } void dpii_open_p1_u0(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o) { _dpii_all(c, p, u, i, o); } void dpii_open_p1_u1(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o) { _dpii_all(c, p, u, i, o); } void dpii_open_p1_u2(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o) { _dpii_all(c, p, u, i, o); } void dpii_open_p1_u3(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o) { _dpii_all(c, p, u, i, o); } void dpii_open_pw_u0(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o) { _dpii_all(c, p, u, i, o); } void dpii_open_pw_u1(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o) { _dpii_all(c, p, u, i, o); } void dpii_open_pw_u2(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o) { _dpii_all(c, p, u, i, o); } void dpii_open_pw_u3(int c, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o) { _dpii_all(c, p, u, i, o); } void dpii_open_bit(const svOpenArrayHandle i, const svOpenArrayHandle o) {} void dpii_open_byte(const svOpenArrayHandle i, const svOpenArrayHandle o) { intptr_t arrPtr = (intptr_t)svGetArrayPtr(i); TEST_CHECK_HEX_NE(arrPtr, 0); // All the arrays should actually exist #ifndef NC // NC always returns zero and warns int sizeInputOfArray = svSizeOfArray(i); TEST_CHECK_HEX_NE(sizeInputOfArray, 0); // None of the test cases have zero size TEST_CHECK_HEX_NE(svDimensions(i), 0); // All the test cases are unpacked arrays #endif } void dpii_open_integer(const svOpenArrayHandle i, const svOpenArrayHandle o) {} void dpii_open_logic(const svOpenArrayHandle i, const svOpenArrayHandle o) {} static void _dpii_open_int_ux(int u, const svOpenArrayHandle i, const svOpenArrayHandle o) { intptr_t arrPtr = (intptr_t)svGetArrayPtr(i); TEST_CHECK_HEX_NE(arrPtr, 0); // All the arrays should actually exist #ifndef NC // NC always returns zero and warns int sizeInputOfArray = svSizeOfArray(i); TEST_CHECK_HEX_NE(sizeInputOfArray, 0); // None of the test cases have zero size TEST_CHECK_HEX_EQ(svDimensions(i), u); #endif int dim = svDimensions(i); for (int a = svLow(i, 1); a <= svHigh(i, 1); ++a) { if (dim == 1) { intptr_t ip = (intptr_t)svGetArrElemPtr(i, a); intptr_t i2p = (intptr_t)svGetArrElemPtr1(i, a); TEST_CHECK_HEX_EQ(ip, i2p); TEST_CHECK_HEX_NE(ip, 0); intptr_t op = (intptr_t)svGetArrElemPtr(o, a); TEST_CHECK_HEX_NE(op, 0); *reinterpret_cast(op) = ~*reinterpret_cast(ip); } else { for (int b = svLow(i, 2); b <= svHigh(i, 2); ++b) { if (dim == 2) { intptr_t ip = (intptr_t)svGetArrElemPtr(i, a, b); intptr_t i2p = (intptr_t)svGetArrElemPtr2(i, a, b); TEST_CHECK_HEX_EQ(ip, i2p); TEST_CHECK_HEX_NE(ip, 0); intptr_t op = (intptr_t)svGetArrElemPtr(o, a, b); TEST_CHECK_HEX_NE(op, 0); *reinterpret_cast(op) = ~*reinterpret_cast(ip); } else { for (int c = svLow(i, 3); c <= svHigh(i, 3); ++c) { if (dim == 3) { intptr_t ip = (intptr_t)svGetArrElemPtr(i, a, b, c); intptr_t i2p = (intptr_t)svGetArrElemPtr3(i, a, b, c); TEST_CHECK_HEX_EQ(ip, i2p); TEST_CHECK_HEX_NE(ip, 0); intptr_t op = (intptr_t)svGetArrElemPtr(o, a, b, c); TEST_CHECK_HEX_NE(op, 0); *reinterpret_cast(op) = ~*reinterpret_cast(ip); } } } } } } } void dpii_open_int_u1(int u, const svOpenArrayHandle i, const svOpenArrayHandle o) { _dpii_open_int_ux(u, i, o); } void dpii_open_int_u2(int u, const svOpenArrayHandle i, const svOpenArrayHandle o) { _dpii_open_int_ux(u, i, o); } void dpii_open_int_u3(int u, const svOpenArrayHandle i, const svOpenArrayHandle o) { _dpii_open_int_ux(u, i, o); } verilator-5.042/test_regress/t/t_compiler_include_dpi.cpp0000644000542200017500000000126715101701376024274 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2024 by Antmicro. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // t_compiler_include.h is implicitly included by `--compiler-include` int dpii_add_check(int actual, int expected) { return actual == expected; } void dpii_add(int a, int b, int* out) { *out = a + b; } verilator-5.042/test_regress/t/t_trace_enum_saif.py0000755000542200017500000000120115101701376023104 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_enum.v" test.compile(verilator_flags2=['--cc --trace-saif --output-split-ctrace 1']) test.execute() test.saif_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_event_method_bad.py0000755000542200017500000000076615101701376023266 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_cover_line.out0000644000542200017500000004552315101701376022300 0ustar mahmoudyfreeshell// // verilator_coverage annotation // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg toggle; %000001 initial toggle=0; -000001 point: comment=block hier=top.t integer cyc; %000001 initial cyc=1; -000001 point: comment=block hier=top.t wire [7:0] cyc_copy = cyc[7:0]; alpha a1 (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle)); alpha a2 (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle)); beta b1 (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle)); beta b2 (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle)); tsk t1 (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle)); off o1 (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle)); tab tab1 (/*AUTOINST*/ // Inputs .clk (clk)); par par1 (/*AUTOINST*/); cond cond1 (/*AUTOINST*/ // Inputs .clk (clk), .cyc (cyc)); 000010 always @ (posedge clk) begin +000010 point: comment=block hier=top.t ~000010 if (cyc!=0) begin +000010 point: comment=if hier=top.t -000000 point: comment=else hier=top.t 000010 cyc <= cyc + 1; +000010 point: comment=if hier=top.t 000010 toggle <= '0; +000010 point: comment=if hier=top.t // Single and multiline if %000009 if (cyc==3) $write(""); -000001 point: comment=if hier=top.t -000009 point: comment=else hier=top.t %000009 if (cyc==3) -000001 point: comment=if hier=top.t -000009 point: comment=else hier=top.t %000001 begin -000001 point: comment=if hier=top.t %000001 $write(""); -000001 point: comment=if hier=top.t end // Single and multiline else %000009 if (cyc==3) ; else $write(""); -000001 point: comment=if hier=top.t -000009 point: comment=else hier=top.t %000009 if (cyc==3) ; -000001 point: comment=if hier=top.t -000009 point: comment=else hier=top.t else %000009 begin -000009 point: comment=else hier=top.t %000009 $write(""); -000009 point: comment=else hier=top.t end // Single and multiline if else %000009 if (cyc==3) $write(""); else $write(""); -000001 point: comment=if hier=top.t -000009 point: comment=else hier=top.t %000009 if (cyc==3) -000001 point: comment=if hier=top.t -000009 point: comment=else hier=top.t %000001 begin -000001 point: comment=if hier=top.t %000001 $write(""); -000001 point: comment=if hier=top.t end else %000009 begin -000009 point: comment=else hier=top.t %000009 $write(""); -000009 point: comment=else hier=top.t end // multiline elseif %000001 if (cyc==3) -000001 point: comment=elsif hier=top.t %000001 begin -000001 point: comment=elsif hier=top.t %000001 $write(""); -000001 point: comment=elsif hier=top.t end %000001 else if (cyc==4) -000001 point: comment=elsif hier=top.t %000001 begin -000001 point: comment=elsif hier=top.t %000001 $write(""); -000001 point: comment=elsif hier=top.t end %000007 else if (cyc==5) -000001 point: comment=if hier=top.t -000007 point: comment=else hier=top.t %000001 begin -000001 point: comment=if hier=top.t %000001 $write(""); -000001 point: comment=if hier=top.t end else %000007 begin -000007 point: comment=else hier=top.t %000007 $write(""); -000007 point: comment=else hier=top.t end // Single and multiline while %000000 while (0); -000000 point: comment=block hier=top.t %000000 while (0) begin -000000 point: comment=block hier=top.t %000000 $write(""); -000000 point: comment=block hier=top.t end %000000 do ; while (0); -000000 point: comment=block hier=top.t ~000010 do begin -000000 point: comment=block hier=top.t +000010 point: comment=block hier=top.t 000010 $write(""); +000010 point: comment=block hier=top.t ~000010 end while (0); -000000 point: comment=block hier=top.t +000010 point: comment=block hier=top.t //=== // Task and complicated %000001 if (cyc==3) begin -000001 point: comment=elsif hier=top.t %000001 toggle <= '1; -000001 point: comment=elsif hier=top.t end %000001 else if (cyc==5) begin -000001 point: comment=elsif hier=top.t `ifdef VERILATOR %000001 $c("this->call_task();"); -000001 point: comment=elsif hier=top.t `else call_task(); `endif end %000007 else if (cyc==10) begin -000001 point: comment=if hier=top.t -000007 point: comment=else hier=top.t %000001 $write("*-* All Finished *-*\n"); -000001 point: comment=if hier=top.t %000001 $finish; -000001 point: comment=if hier=top.t end end end %000001 task call_task; -000001 point: comment=block hier=top.t /* verilator public */ %000001 t1.center_task(1'b1); -000001 point: comment=block hier=top.t endtask endmodule module alpha (/*AUTOARG*/ // Inputs clk, toggle ); input clk; input toggle; 000020 always @ (posedge clk) begin +000020 point: comment=block hier=top.t.a* ~000018 if (toggle) begin // CHECK_COVER(0,"top.t.a*",18) -000002 point: comment=if hier=top.t.a* +000018 point: comment=else hier=top.t.a* %000002 $write(""); -000002 point: comment=if hier=top.t.a* // t.a1 and t.a2 collapse to a count of 2 end 000018 if (toggle) begin // *** t_cover_line.vlt turns this off +000018 point: comment=else hier=top.t.a* $write(""); // CHECK_COVER_MISSING(0) // This doesn't even get added `ifdef ATTRIBUTE // verilator coverage_block_off `endif end end endmodule module beta (/*AUTOARG*/ // Inputs clk, toggle ); input clk; input toggle; /* verilator public_module */ 000020 always @ (posedge clk) begin +000020 point: comment=block hier=top.t.b* 000020 $write(""); // Always covered +000020 point: comment=block hier=top.t.b* ~000020 if (0) begin // CHECK_COVER(0,"top.t.b*",0) -000000 point: comment=if hier=top.t.b* +000020 point: comment=else hier=top.t.b* // Make sure that we don't optimize away zero buckets %000000 $write(""); -000000 point: comment=if hier=top.t.b* end ~000018 if (toggle) begin // CHECK_COVER(0,"top.t.b*",2) -000002 point: comment=if hier=top.t.b* +000018 point: comment=else hier=top.t.b* // t.b1 and t.b2 collapse to a count of 2 %000002 $write(""); -000002 point: comment=if hier=top.t.b* end 000018 if (toggle) begin : block +000018 point: comment=else hier=top.t.b* // This doesn't `ifdef ATTRIBUTE // verilator coverage_block_off `endif begin end // *** t_cover_line.vlt turns this off (so need begin/end) if (1) begin end // CHECK_COVER_MISSING(0) $write(""); // CHECK_COVER_MISSING(0) end end endmodule class Cls; bit m_toggle; 000011 function new(bit toggle); +000011 point: comment=block hier=top.$unit::Cls__Vclpkg 000011 m_toggle = toggle; +000011 point: comment=block hier=top.$unit::Cls__Vclpkg ~000011 if (m_toggle) begin // CHECK_COVER(0,"top.$unit::Cls",1) +000011 point: comment=if hier=top.$unit::Cls__Vclpkg -000000 point: comment=else hier=top.$unit::Cls__Vclpkg 000011 $write(""); +000011 point: comment=if hier=top.$unit::Cls__Vclpkg end endfunction 000011 static function void fstatic(bit toggle); +000011 point: comment=block hier=top.$unit::Cls__Vclpkg ~000011 if (1) begin // CHECK_COVER(0,"top.$unit::Cls",1) +000011 point: comment=if hier=top.$unit::Cls__Vclpkg -000000 point: comment=else hier=top.$unit::Cls__Vclpkg 000011 $write(""); +000011 point: comment=if hier=top.$unit::Cls__Vclpkg end endfunction 000011 function void fauto(); +000011 point: comment=block hier=top.$unit::Cls__Vclpkg ~000011 if (m_toggle) begin // CHECK_COVER(0,"top.$unit::Cls",11) +000011 point: comment=if hier=top.$unit::Cls__Vclpkg -000000 point: comment=else hier=top.$unit::Cls__Vclpkg 000011 $write(""); +000011 point: comment=if hier=top.$unit::Cls__Vclpkg end endfunction endclass module tsk (/*AUTOARG*/ // Inputs clk, toggle ); input clk; input toggle; /* verilator public_module */ 000010 always @ (posedge clk) begin +000010 point: comment=block hier=top.t.t1 000010 center_task(1'b0); +000010 point: comment=block hier=top.t.t1 end 000011 task automatic center_task; +000011 point: comment=block hier=top.t.t1 input external; 000011 begin +000011 point: comment=block hier=top.t.t1 ~000010 if (toggle) begin // CHECK_COVER(0,"top.t.t1",1) -000001 point: comment=if hier=top.t.t1 +000010 point: comment=else hier=top.t.t1 %000001 $write(""); -000001 point: comment=if hier=top.t.t1 end ~000010 if (external) begin // CHECK_COVER(0,"top.t.t1",1) -000001 point: comment=if hier=top.t.t1 +000010 point: comment=else hier=top.t.t1 %000001 $write("[%0t] Got external pulse\n", $time); -000001 point: comment=if hier=top.t.t1 end end 000011 begin +000011 point: comment=block hier=top.t.t1 Cls c; 000011 c = new(1'b1); +000011 point: comment=block hier=top.t.t1 000011 c.fauto(); +000011 point: comment=block hier=top.t.t1 000011 Cls::fstatic(1'b1); +000011 point: comment=block hier=top.t.t1 end endtask endmodule module off (/*AUTOARG*/ // Inputs clk, toggle ); input clk; input toggle; // verilator coverage_off always @ (posedge clk) begin if (toggle) begin $write(""); // CHECK_COVER_MISSING(0) // because under coverage_module_off end end // verilator coverage_on 000010 always @ (posedge clk) begin +000010 point: comment=block hier=top.t.o1 %000009 if (toggle) begin -000001 point: comment=if hier=top.t.o1 -000009 point: comment=else hier=top.t.o1 // because under coverage_module_off %000001 $write(""); -000001 point: comment=if hier=top.t.o1 %000001 if (0) ; // CHECK_COVER(0,"top.t.o1",1) -000000 point: comment=if hier=top.t.o1 -000001 point: comment=else hier=top.t.o1 end end endmodule module tab (input clk); bit [3:0] cyc4; int decoded; 000010 always @ (posedge clk) begin +000010 point: comment=block hier=top.t.tab1 000010 case (cyc4) +000010 point: comment=block hier=top.t.tab1 %000001 1: decoded = 10; -000001 point: comment=case hier=top.t.tab1 %000001 2: decoded = 20; -000001 point: comment=case hier=top.t.tab1 %000001 3: decoded = 30; -000001 point: comment=case hier=top.t.tab1 %000001 4: decoded = 40; -000001 point: comment=case hier=top.t.tab1 %000001 5: decoded = 50; -000001 point: comment=case hier=top.t.tab1 %000005 default: decoded = 0; -000005 point: comment=case hier=top.t.tab1 endcase end 000010 always @ (posedge clk) begin +000010 point: comment=block hier=top.t.tab1 000010 cyc4 <= cyc4 + 1; +000010 point: comment=block hier=top.t.tab1 end endmodule module par(); localparam int CALLS_FUNC = param_func(1); // We don't currently count elaboration time use towards coverage. This // seems safer for functions used both at elaboration time and not - but may // revisit this. %000000 function automatic int param_func(int i); -000000 point: comment=block hier=top.t.par1 %000000 if (i == 0) begin -000000 point: comment=if hier=top.t.par1 -000000 point: comment=else hier=top.t.par1 %000000 i = 99; // Uncovered -000000 point: comment=if hier=top.t.par1 end %000000 else begin -000000 point: comment=else hier=top.t.par1 %000000 i = i + 1; -000000 point: comment=else hier=top.t.par1 end %000000 return i; -000000 point: comment=block hier=top.t.par1 endfunction endmodule package my_pkg; %000001 int x = 1 ? 1 : 0; -000001 point: comment=block hier=top.my_pkg endpackage %000001 class Getter1; -000001 point: comment=block hier=top.$unit::Getter1__Vclpkg 000020 function int get_1; +000020 point: comment=block hier=top.$unit::Getter1__Vclpkg 000020 return 1; +000020 point: comment=block hier=top.$unit::Getter1__Vclpkg endfunction endclass module cond(input logic clk, input int cyc); logic a, b, c, d, e, f, g, h, k, l, m; logic [5:0] tab; typedef logic [7:0] arr_t[1:0]; arr_t data[1:0]; %000001 Getter1 getter1 = new; -000001 point: comment=block hier=top.t.cond1 string s; 000021 function logic func_side_effect; +000021 point: comment=block hier=top.t.cond1 000021 $display("SIDE EFFECT"); +000021 point: comment=block hier=top.t.cond1 000021 return 1; +000021 point: comment=block hier=top.t.cond1 endfunction 000010 function arr_t get_arr; +000010 point: comment=block hier=top.t.cond1 arr_t arr; 000010 return arr; +000010 point: comment=block hier=top.t.cond1 endfunction ~000031 assign a = (cyc == 0) ? clk : 1'bz; -000000 point: comment=cond_then hier=top.t.cond1 +000031 point: comment=cond_else hier=top.t.cond1 ~000028 assign b = (cyc == 1) ? clk : 0; -000003 point: comment=cond_then hier=top.t.cond1 +000028 point: comment=cond_else hier=top.t.cond1 ~000021 assign c = func_side_effect() ? clk : 0; +000021 point: comment=cond_then hier=top.t.cond1 -000000 point: comment=cond_else hier=top.t.cond1 000010 always @(posedge clk) begin +000010 point: comment=block hier=top.t.cond1 ~000010 d = (cyc % 3 == 0) ? 1 : 0; +000010 point: comment=block hier=top.t.cond1 -000003 point: comment=cond_then hier=top.t.cond1 -000007 point: comment=cond_else hier=top.t.cond1 ~000010 s = (getter1.get_1() == 0) ? "abcd" : $sformatf("%d", getter1.get_1()[4:0]); +000010 point: comment=block hier=top.t.cond1 -000000 point: comment=cond_then hier=top.t.cond1 +000010 point: comment=cond_else hier=top.t.cond1 end ~000019 assign e = (cyc % 3 == 1) ? (clk ? 1 : 0) : 1; +000012 point: comment=cond_then hier=top.t.cond1 +000019 point: comment=cond_else hier=top.t.cond1 -000007 point: comment=cond_then hier=top.t.cond1 -000005 point: comment=cond_else hier=top.t.cond1 // ternary operator in condition shouldn't be included to the coverae ~000011 assign f = (cyc != 0 ? 1 : 0) ? 1 : 0; +000011 point: comment=cond_then hier=top.t.cond1 -000000 point: comment=cond_else hier=top.t.cond1 // the same as in index assign tab[clk ? 1 : 0] = 1; assign m = tab[clk ? 3 : 4]; for (genvar i = 0; i < 2; i++) begin 000011 assign g = clk ? 1 : 0; +000010 point: comment=cond_then hier=top.t.cond1 +000011 point: comment=cond_else hier=top.t.cond1 end 000011 always begin +000011 point: comment=block hier=top.t.cond1 ~000010 if (cyc == 5) h = cyc > 5 ? 1 : 0; -000000 point: comment=cond_then hier=top.t.cond1 -000001 point: comment=cond_else hier=top.t.cond1 -000001 point: comment=if hier=top.t.cond1 +000010 point: comment=else hier=top.t.cond1 000010 else h = 1; +000010 point: comment=else hier=top.t.cond1 ~000011 data[0] = (cyc == 2) ? '{8'h01, 8'h02} : get_arr(); +000011 point: comment=block hier=top.t.cond1 -000001 point: comment=cond_then hier=top.t.cond1 +000010 point: comment=cond_else hier=top.t.cond1 // ternary operator in conditions should be skipped 000055 for (int i = 0; (i < 5) ? 1 : 0; i++) begin +000011 point: comment=block hier=top.t.cond1 +000055 point: comment=block hier=top.t.cond1 000055 k = 1'(i); +000055 point: comment=block hier=top.t.cond1 end 000044 for (int i = 0; i < 7; i = (i > 4) ? i + 1 : i + 2) begin +000011 point: comment=block hier=top.t.cond1 +000011 point: comment=cond_then hier=top.t.cond1 +000033 point: comment=cond_else hier=top.t.cond1 +000044 point: comment=block hier=top.t.cond1 000044 k = 1'(i); +000044 point: comment=block hier=top.t.cond1 end ~000011 if (k ? 1 : 0) k = 1; -000000 point: comment=if hier=top.t.cond1 +000011 point: comment=else hier=top.t.cond1 000011 else k = 0; +000011 point: comment=else hier=top.t.cond1 end endmodule verilator-5.042/test_regress/t/t_trace_decoration.py0000755000542200017500000000113515101701376023273 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--cc --trace-vcd --no-decoration']) test.execute() test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + ".h", r'// Body') test.passes() verilator-5.042/test_regress/t/t_net_delay.out0000644000542200017500000000433115101701376022107 0ustar mahmoudyfreeshell%Warning-STMTDLY: t/t_net_delay.v:16:11: Ignoring delay on this statement due to --no-timing : ... note: In instance 't' 16 | always #2 clk = ~clk; | ^ ... For warning description see https://verilator.org/warn/STMTDLY?v=latest ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message. %Warning-STMTDLY: t/t_net_delay.v:22:14: Ignoring delay on this statement due to --no-timing : ... note: In instance 't' 22 | wire[3:0] #3 val1; | ^ %Warning-STMTDLY: t/t_net_delay.v:23:14: Ignoring delay on this statement due to --no-timing : ... note: In instance 't' 23 | wire[3:0] #3 val2; | ^ %Warning-ASSIGNDLY: t/t_net_delay.v:24:14: Ignoring timing control on this assignment/primitive due to --no-timing : ... note: In instance 't' 24 | wire[3:0] #5 val3 = cyc; | ^ ... For warning description see https://verilator.org/warn/ASSIGNDLY?v=latest ... Use "/* verilator lint_off ASSIGNDLY */" and lint_on around source to disable this message. %Warning-STMTDLY: t/t_net_delay.v:25:14: Ignoring delay on this statement due to --no-timing : ... note: In instance 't' 25 | wire[3:0] #5 val4; | ^ %Warning-ASSIGNDLY: t/t_net_delay.v:26:14: Ignoring timing control on this assignment/primitive due to --no-timing : ... note: In instance 't' 26 | wire[3:0] #3 val5 = x, val6 = cyc; | ^ %Warning-ASSIGNDLY: t/t_net_delay.v:29:11: Ignoring timing control on this assignment/primitive due to --no-timing : ... note: In instance 't' 29 | assign #3 val2 = cyc; | ^ %Warning-STMTDLY: t/t_net_delay.v:41:26: Ignoring delay on this statement due to --no-timing : ... note: In instance 't' 41 | always @(posedge clk) #1 begin | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_config_libmap.map0000644000542200017500000000100315101701376022673 0ustar mahmoudyfreeshell// -*- Verilog -*- // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // lib.map file: include ./t_config_libmap_inc.map library rtllib *.v; library rtllib2 *.v, *.sv; library rtllib3 *.v -incdir *.vh; library rtllib4 *.v -incdir *.vh, *.svh; // Note this does not start a comment library gatelib ./*.vg; // */ config cfg; design t; endconfig verilator-5.042/test_regress/t/t_case_genx_bad.v0000644000542200017500000000071415101701376022344 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; parameter P = 32'b1000; generate case (P) 32'b0: initial begin end 32'b1xxx: initial begin end default initial begin end // No ':' to cover parser endcase endgenerate endmodule verilator-5.042/test_regress/t/t_bitsel_slice.py0000755000542200017500000000073415101701376022433 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_gen12.v0000644000542200017500000000113715101701376022536 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty. // SPDX-License-Identifier: CC0-1.0 // bug1005 module foo_module; generate for (genvar i = 0; i < 2; i = i + 1) begin : my_gen_block logic baz; end endgenerate endmodule module bar_module; foo_module foo(); endmodule module t; bar_module bar(); initial begin bar.foo.my_gen_block[0].baz = 1; if (bar.foo.my_gen_block[0].baz) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_clk_latch_edgestyle.py0000755000542200017500000000105015101701376023753 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_clk_latch.v" test.compile(v_flags2=['+define+EDGE_DETECT_STYLE']) test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_saif.out0000644000542200017500000012246715101701376022256 0ustar mahmoudyfreeshell// Generated by verilated_saif (SAIFILE (SAIFVERSION "2.0") (DIRECTION "backward") (PROGRAM_NAME "Verilator") (DIVIDER / ) (TIMESCALE 1ps) (DURATION 1000) (INSTANCE top (NET (clk (T0 505) (T1 495) (TZ 0) (TX 0) (TB 0) (TC 199)) (state\[0\] (T0 410) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46)) (state\[1\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) (state\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44)) (state\[4\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) (fst_inout (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE t (NET (clk (T0 505) (T1 495) (TZ 0) (TX 0) (TB 0) (TC 199)) (cyc\[0\] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 100)) (cyc\[1\] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 50)) (cyc\[2\] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 25)) (cyc\[3\] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 12)) (cyc\[4\] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 6)) (cyc\[5\] (T0 640) (T1 360) (TZ 0) (TX 0) (TB 0) (TC 3)) (cyc\[6\] (T0 640) (T1 360) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (rstn (T0 110) (T1 890) (TZ 0) (TX 0) (TB 0) (TC 1)) (state\[0\] (T0 410) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46)) (state\[1\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) (state\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44)) (state\[4\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) (fst_gparam_real\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[32\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[33\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[34\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[35\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[36\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[37\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[38\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[39\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[40\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[41\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[42\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[43\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[44\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[45\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[46\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[47\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[48\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[49\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[50\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[51\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[52\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[53\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[54\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[55\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[56\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[57\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[58\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[59\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[60\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[61\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[62\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[63\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[32\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[33\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[34\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[35\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[36\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[37\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[38\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[39\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[40\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[41\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[42\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[43\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[44\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[45\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[46\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[47\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[48\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[49\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[50\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[51\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[52\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[53\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[54\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[55\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[56\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[57\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[58\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[59\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[60\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[61\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[62\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[63\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[32\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[33\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[34\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[35\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[36\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[37\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[38\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[39\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[40\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[41\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[42\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[43\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[44\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[45\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[46\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[47\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[48\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[49\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[50\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[51\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[52\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[53\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[54\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[55\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[56\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[57\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[58\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[59\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[60\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[61\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[62\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[63\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_bit (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_logic (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[32\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[33\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[34\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[35\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[36\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[37\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[38\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[39\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[40\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[41\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[42\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[43\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[44\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[45\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[46\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[47\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[48\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[49\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[50\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[51\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[52\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[53\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[54\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[55\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[56\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[57\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[58\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[59\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[60\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[61\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[62\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[63\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_byte\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_byte\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_byte\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_byte\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_byte\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_byte\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_byte\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_byte\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[1\] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 100)) (fst_time\[2\] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 50)) (fst_time\[3\] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 75)) (fst_time\[4\] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 62)) (fst_time\[5\] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 31)) (fst_time\[6\] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 15)) (fst_time\[7\] (T0 510) (T1 490) (TZ 0) (TX 0) (TB 0) (TC 7)) (fst_time\[8\] (T0 510) (T1 490) (TZ 0) (TX 0) (TB 0) (TC 3)) (fst_time\[9\] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_time\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[32\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[33\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[34\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[35\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[36\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[37\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[38\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[39\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[40\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[41\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[42\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[43\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[44\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[45\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[46\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[47\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[48\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[49\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[50\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[51\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[52\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[53\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[54\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[55\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[56\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[57\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[58\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[59\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[60\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[61\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[62\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_time\[63\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[0\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_parameter\[1\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_parameter\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[3\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_parameter\[4\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_parameter\[5\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_parameter\[6\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_parameter\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[3\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_lparam\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[6\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_lparam\[7\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_lparam\[8\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_lparam\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_supply0 (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_supply1 (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_tri0 (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_tri1 (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_tri (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_triand (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_trior (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_wand (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_wor (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_wire (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_uwire (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_inout (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE test (NET (clk (T0 505) (T1 495) (TZ 0) (TX 0) (TB 0) (TC 199)) (rstn (T0 110) (T1 890) (TZ 0) (TX 0) (TB 0) (TC 1)) (state\[0\] (T0 410) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46)) (state\[1\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) (state\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44)) (state\[4\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) (state_w\[0\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_w\[1\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_w\[2\] (T0 430) (T1 570) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_w\[3\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 47)) (state_w\[4\] (T0 420) (T1 580) (TZ 0) (TX 0) (TB 0) (TC 48)) (state_array[0]\[0\] (T0 410) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_array[0]\[1\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) (state_array[0]\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_array[0]\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44)) (state_array[0]\[4\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) (state_array[1]\[0\] (T0 420) (T1 580) (TZ 0) (TX 0) (TB 0) (TC 47)) (state_array[1]\[1\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_array[1]\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_array[1]\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) (state_array[1]\[4\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_array[2]\[0\] (T0 420) (T1 580) (TZ 0) (TX 0) (TB 0) (TC 48)) (state_array[2]\[1\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_array[2]\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_array[2]\[3\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_array[2]\[4\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 47)) ) (INSTANCE unnamedblk1 (NET (i\[0\] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1)) (i\[1\] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1)) (i\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE unnamedblk2 (NET (i\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[1\] (T0 120) (T1 880) (TZ 0) (TX 0) (TB 0) (TC 1)) (i\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) ) ) verilator-5.042/test_regress/t/t_class_member_sens.py0000755000542200017500000000072615101701376023457 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_param_avec.v0000644000542200017500000000217215101701376021700 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2016 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t (/*AUTOARG*/ // Inputs clk ); input clk; sub #(.IDX(0), .CHK(10)) i0(); sub #(.IDX(2), .CHK(12)) i2(); sub #(.IDX(7), .CHK(17)) i7(); always @ (posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule module sub (); function integer get_element; input integer index; input integer array_arg[7:0]; get_element = array_arg[index]; endfunction parameter integer IDX = 5; parameter integer CHK = 5; localparam integer array[0:7] = '{10, 11, 12, 13, 14, 15, 16, 17}; localparam element1 = array[IDX]; localparam elementf = get_element(IDX, array); initial begin `checkh (element1, CHK); `checkh (elementf, CHK); end endmodule verilator-5.042/test_regress/t/t_net_dtype_bad.py0000755000542200017500000000076615101701376022600 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface_gen2_noinl.py0000755000542200017500000000103715101701376024041 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_gen2.v" test.compile(v_flags2=["-fno-inline"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_typedef_package.py0000755000542200017500000000073415101701376023105 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_unopt_converge_print_bad.out0000644000542200017500000000024215101701376025217 0ustar mahmoudyfreeshell-V{t#,#} 'stl' region trigger index 0 is active: @([hybrid] x) %Error: t/t_unopt_converge.v:7: Settle region did not converge after 100 tries Aborting... verilator-5.042/test_regress/t/t_param_default_bad.py0000755000542200017500000000076615101701376023411 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_trace_fst_sc.v0000644000542200017500000000444415101701376022245 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // Author: Yu-Sheng Lin johnjohnlys@media.ee.ntu.edu.tw // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; int cyc; reg rstn; parameter real fst_gparam_real = 1.23; localparam real fst_lparam_real = 4.56; real fst_real = 1.23; integer fst_integer; bit fst_bit; logic fst_logic; int fst_int; shortint fst_shortint; longint fst_longint; byte fst_byte; parameter fst_parameter = 123; localparam fst_lparam = 456; supply0 fst_supply0; supply1 fst_supply1; tri0 fst_tri0; tri1 fst_tri1; tri fst_tri; wire fst_wire; logic [4:0] state; Test test (/*AUTOINST*/ // Outputs .state (state[4:0]), // Inputs .clk (clk), .rstn (rstn)); // Test loop always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==0) begin // Setup rstn <= ~'1; end else if (cyc<10) begin rstn <= ~'1; end else if (cyc<90) begin rstn <= ~'0; end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test ( input clk, input rstn, output logic [4:0] state ); logic [4:0] state_w; logic [4:0] state_array [3]; assign state = state_array[0]; always_comb begin state_w[4] = state_array[2][0]; state_w[3] = state_array[2][4]; state_w[2] = state_array[2][3] ^ state_array[2][0]; state_w[1] = state_array[2][2]; state_w[0] = state_array[2][1]; end always_ff @(posedge clk or negedge rstn) begin if (!rstn) begin for (int i = 0; i < 3; i++) state_array[i] <= 'b1; end else begin for (int i = 0; i < 2; i++) state_array[i] <= state_array[i+1]; state_array[2] <= state_w; end end endmodule verilator-5.042/test_regress/t/t_inst_dtree_inlbd.py0000755000542200017500000000111615101701376023275 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_inst_dtree.v" test.compile(v_flags2=['+define+INLINE_B +define+INLINE_D'], verilator_flags2=['-trace']) test.execute() test.passes() verilator-5.042/test_regress/t/t_sys_readmem_bad_end.py0000755000542200017500000000100015101701376023721 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_tri_gate_notif1_pins_inout.py0000755000542200017500000000141215101701376025311 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_tri_gate.cpp" test.top_filename = "t/t_tri_gate.v" test.compile(make_top_shell=False, make_main=False, v_flags2=['+define+T_NOTIF1'], make_flags=['CPPFLAGS_ADD=-DT_NOTIF1'], verilator_flags2=["--exe --pins-inout-enables", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_udp_bad_first_input.out0000644000542200017500000000046415101701376024172 0ustar mahmoudyfreeshell%Error: t/t_udp_bad_first_input.v:8:7: First UDP port must be the output port : ... note: In instance 'top' 8 | input a, b, c; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_altera_lpm_add_sub.py0000755000542200017500000000111115101701376023561 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) test.compile(verilator_flags2=["--top-module", module]) test.passes() verilator-5.042/test_regress/t/t_tri_top_en_out.cpp0000644000542200017500000001657615101701376023165 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module, C driver code // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Paul Wright. // SPDX-License-Identifier: CC0-1.0 #include "verilated.h" #include "TestCheck.h" #include VM_PREFIX_INCLUDE #include int main(int argc, char** argv, char**) { int errors; // Setup context, defaults, and parse command line Verilated::debug(0); const std::unique_ptr contextp{new VerilatedContext}; contextp->commandArgs(argc, argv); // Construct the Verilated model, from Vtop.h generated from Verilating const std::unique_ptr topp{new VM_PREFIX{contextp.get()}}; // Initial input topp->drv_en = 0; topp->single_bit_io = rand() & 1; topp->bidir_single_bit_io = rand() & 1; topp->bus_64_io = 0; topp->bidir_bus_64_io = rand() & 0xffffffffffffffff; topp->bus_128_io[0] = 0; topp->bus_128_io[1] = 0; topp->bus_128_io[2] = 0; topp->bus_128_io[3] = 0; topp->bidir_bus_128_io[0] = rand() & 0xffffffff; topp->bidir_bus_128_io[1] = rand() & 0xffffffff; topp->bidir_bus_128_io[2] = rand() & 0xffffffff; topp->bidir_bus_128_io[3] = rand() & 0xffffffff; topp->sub_io = rand() & 1; topp->test_en = 1; errors = 0; // Simulate until $finish while (!contextp->gotFinish()) { // Evaluate model topp->eval(); // Advance time (to scheduled events) if (!topp->eventsPending()) break; contextp->time(topp->nextTimeSlot()); // We want to check that the __en and __out signals can be accessed printf("Info:(cpp): drv_en = %x\n", topp->drv_en); printf("Info:(cpp): bidir_single_bit_io__en = %x\n", topp->bidir_single_bit_io__en); printf("Info:(cpp): bidir_bus_64_io__en = %x\n", (unsigned int)topp->bidir_bus_64_io__en); printf("Info:(cpp): bidir_bus_128_io__en = %x,%x,%x,%x\n", topp->bidir_bus_128_io__en[3], topp->bidir_bus_128_io__en[2], topp->bidir_bus_128_io__en[1], topp->bidir_bus_128_io__en[0]); printf("Info:(cpp): sub_io__en = %x\n", topp->sub_io__en); printf("Info:(cpp): bidir_single_bit_io = %x\n", topp->bidir_single_bit_io__out); printf("Info:(cpp): bidir_bus_64_io = %x\n", (unsigned int)topp->bidir_bus_64_io__out); printf("Info:(cpp): bidir_bus_128_io = %x,%x,%x,%x\n", topp->bidir_bus_128_io__out[3], topp->bidir_bus_128_io__out[2], topp->bidir_bus_128_io__out[1], topp->bidir_bus_128_io__out[0]); printf("Info:(cpp): sub_io = %x\n", topp->sub_io__out); // Loop back if verilog is driving // Verilator will not do this for itself // We must implement the top-level resolution if (topp->sub_io__en) topp->sub_io = topp->sub_io__out; if (topp->bidir_single_bit_io__en) { topp->bidir_single_bit_io = topp->bidir_single_bit_io__out; } // For bus signals, overwrite the bits which are driven by verilog, preserve the others if (topp->bidir_bus_64_io__en) { topp->bidir_bus_64_io = ((~topp->bidir_bus_64_io__en) & topp->bidir_bus_64_io) | (topp->bidir_bus_64_io__en & topp->bidir_bus_64_io__out); } for (int i = 0; i < 4; i++) { if (topp->bidir_bus_128_io__en[i]) { topp->bidir_bus_128_io[i] = ((~topp->bidir_bus_128_io__en[i]) & topp->bidir_bus_128_io[i]) | (topp->bidir_bus_128_io__en[i] & topp->bidir_bus_128_io__out[i]); } } // Has the verilog code finished a test loop? if (topp->loop_done == 1) { // Check the expected __en output if (topp->drv_en & 0x1) { TEST_CHECK_EQ(uint64_t(topp->sub_io__en), 1); TEST_CHECK_EQ(uint64_t(topp->bidir_single_bit_io__en), 1); } else { TEST_CHECK_EQ(uint64_t(topp->sub_io__en), 0); TEST_CHECK_EQ(uint64_t(topp->bidir_single_bit_io__en), 0); } for (int i = 0; i < 4; i++) { // __en enabled? if ((topp->drv_en & (1 << i)) != 0) { TEST_CHECK_EQ(uint64_t(topp->bidir_bus_64_io__en >> (i * 16) & 0xffff), 0xffff); TEST_CHECK_EQ(uint64_t(topp->bidir_bus_128_io__en[i]), 0xffffffff); } // __en not enabled else { TEST_CHECK_EQ(uint64_t(topp->bidir_bus_64_io__en >> (i * 16) & 0xffff), 0x0000); TEST_CHECK_EQ(uint64_t(topp->bidir_bus_128_io__en[i]), 0x00000000); } } // for if (topp->drv_en == 15) { topp->test_en = 0; } else { topp->drv_en++; // Drive the bits verilog shouldn't be driving if (topp->drv_en & 1) { topp->single_bit_io = rand() & 1; topp->bidir_single_bit_io = rand() & 1; topp->sub_io = rand() & 1; topp->bidir_bus_64_io = ((rand() & 0xffff) << 0) | (topp->bidir_bus_64_io & 0xffffffffffff0000); topp->bidir_bus_128_io[0] = rand() & 0xffffffff; } else { topp->single_bit_io = 0; topp->bidir_single_bit_io = 0; topp->sub_io = 0; topp->bidir_bus_64_io = (topp->bidir_bus_64_io & 0xffffffffffff0000); topp->bidir_bus_128_io[0] = 0; } if (topp->drv_en & 2) { topp->bidir_bus_64_io = ((rand() & 0xffff) << 16) | (topp->bidir_bus_64_io & 0xffffffff0000ffff); topp->bidir_bus_128_io[1] = rand() & 0xffffffff; } else { topp->bidir_bus_64_io = (topp->bidir_bus_64_io & 0xffffffff0000ffff); topp->bidir_bus_128_io[1] = 0; } if (topp->drv_en & 4) { topp->bidir_bus_64_io = (((uint64_t)(rand() & 0xffff)) << 32) | (topp->bidir_bus_64_io & 0xffff0000ffffffff); topp->bidir_bus_128_io[2] = rand() & 0xffffffff; } else { topp->bidir_bus_64_io = (topp->bidir_bus_64_io & 0xffff0000ffffffff); topp->bidir_bus_128_io[2] = 0; } if (topp->drv_en & 8) { topp->bidir_bus_64_io = (((uint64_t)(rand() & 0xffff)) << 48) | (topp->bidir_bus_64_io & 0x0000ffffffffffff); topp->bidir_bus_128_io[3] = rand() & 0xffffffff; } else { topp->bidir_bus_64_io = (topp->bidir_bus_64_io & 0x0000ffffffffffff); topp->bidir_bus_128_io[3] = 0; } } // Invert the input side topp->bidir_single_bit_io = (~topp->bidir_single_bit_io) & 0x1; topp->bidir_bus_64_io = ~topp->bidir_bus_64_io; for (int i = 0; i < 4; i++) topp->bidir_bus_128_io[i] = ~topp->bidir_bus_128_io[i]; } // if (loop_done) if (errors != 0) break; } // Final model cleanup topp->final(); return 0; } verilator-5.042/test_regress/t/t_clk_2in.cpp0000644000542200017500000000233015101701376021434 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include VM_PREFIX_INCLUDE unsigned int main_time = 0; double sc_time_stamp() { return main_time; } VM_PREFIX* topp = nullptr; void clockit(int clk1, int clk0) { topp->clks = clk1 << 1 | clk0; #ifndef T_CLK_2IN_VEC topp->c1 = clk1; topp->c0 = clk0; #endif #ifdef TEST_VERBOSE printf("[%u] c1=%d c0=%d\n", main_time, clk1, clk0); #endif topp->eval(); main_time++; } int main(int argc, char* argv[]) { Verilated::debug(0); Verilated::commandArgs(argc, argv); topp = new VM_PREFIX; topp->check = 0; clockit(0, 0); main_time += 10; for (int i = 0; i < 2; i++) { clockit(0, 0); clockit(0, 1); clockit(1, 1); clockit(0, 0); clockit(1, 1); clockit(1, 0); clockit(0, 0); clockit(0, 1); clockit(1, 0); clockit(0, 0); } topp->check = 1; clockit(0, 0); topp->final(); VL_DO_DANGLING(delete topp, topp); } verilator-5.042/test_regress/t/t_real_cast.py0000755000542200017500000000072615101701376021730 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios("vlt") test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_realcvt_bad.py0000755000542200017500000000107315101701376023263 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["--lint-only -Wwarn-REALCVT"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_param_concat_bad.out0000644000542200017500000000206215101701376023377 0ustar mahmoudyfreeshell%Warning-WIDTHCONCAT: t/t_param_concat.v:19:15: Unsized numbers/parameters not allowed in concatenations. : ... note: In instance 't' 19 | if ({UNSIZED,UNSIZED+1} != {32'd10, 32'd11}) $stop; | ^~~~~~~ ... For warning description see https://verilator.org/warn/WIDTHCONCAT?v=latest ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message. %Warning-WIDTHCONCAT: t/t_param_concat.v:19:22: Unsized numbers/parameters not allowed in replications. : ... note: In instance 't' 19 | if ({UNSIZED,UNSIZED+1} != {32'd10, 32'd11}) $stop; | ^ %Warning-WIDTHCONCAT: t/t_param_concat.v:20:17: Unsized numbers/parameters not allowed in replications. : ... note: In instance 't' 20 | if ({2{UNSIZED}} != {32'd10, 32'd10}) $stop; | ^~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_order_2d.v0000644000542200017500000000424415101701376021304 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2015 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire input_signal = crc[0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire output_signal; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .output_signal (output_signal), // Inputs .input_signal (input_signal)); // Aggregate outputs into a single result vector wire [63:0] result = {63'h0, output_signal}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc<10) begin sum <= '0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h765b2e12b25ec97b if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test ( input input_signal, output output_signal ); // bug872 // verilator lint_off UNOPTFLAT wire some_signal[1:0][1:0]; assign some_signal[0][0] = input_signal; assign some_signal[0][1] = some_signal[0][0]; assign some_signal[1][0] = some_signal[0][1]; assign some_signal[1][1] = some_signal[1][0]; assign output_signal = some_signal[1][1]; endmodule verilator-5.042/test_regress/t/t_param_wide_io.py0000755000542200017500000000073515101701376022572 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() #test.execute() test.passes() verilator-5.042/test_regress/t/t_nba_commit_queue.v0000644000542200017500000002756515101701376023133 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) `define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t(clk); input clk; logic [31:0] cyc = 0; always @(posedge clk) begin cyc <= cyc + 1; if (cyc == 99) begin $write("*-* All Finished *-*\n"); $finish; end end reg [63:0] crc = 64'h5aef0c8d_d70a4497; always @ (posedge clk) crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; `define at_posedge_clk_on_cycle(n) always @(posedge clk) if (cyc == n) // Case 1: narrow packed variable, whole element updates only - 1D typedef logic [31:0] elem1_t; typedef elem1_t array1_t[128]; array1_t array1; `at_posedge_clk_on_cycle(0) begin for (int i = 0 ; i < 128; ++i) array1[i] = 0; for (int i = 0 ; i < 128; ++i) `checkh(array1[i], 0); end `at_posedge_clk_on_cycle(1) begin for (int i = 0 ; i < 128; ++i) `checkh(array1[i], 0); for (int i = 0 ; i < 128; ++i) array1[i] <= i; for (int i = 0 ; i < 128; ++i) `checkh(array1[i], 0); end `at_posedge_clk_on_cycle(2) begin for (int i = 0 ; i < 128; ++i) `checkh(array1[i], i); for (int i = 0 ; i < 128; ++i) array1[i] <= ~i; for (int i = 0 ; i < 128; ++i) `checkh(array1[i], i); end `at_posedge_clk_on_cycle(3) begin for (int i = 0 ; i < 128; ++i) `checkh(array1[i], ~i); for (int i = 0 ; i < 128; ++i) array1[i] <= -1; for (int i = 0 ; i < 128; ++i) `checkh(array1[i], ~i); end `at_posedge_clk_on_cycle(4) begin for (int i = 0 ; i < 128; ++i) `checkh(array1[i], -1); end // Case 2: wide packed variable, whole element updates only - 1D typedef logic [127:0] elem2_t; typedef elem2_t array2_t[128]; array2_t array2; `at_posedge_clk_on_cycle(0) begin for (int i = 0 ; i < 128; ++i) array2[i] = 0; for (int i = 0 ; i < 128; ++i) `checkh(array2[i], 0); end `at_posedge_clk_on_cycle(1) begin for (int i = 0 ; i < 128; ++i) `checkh(array2[i], 0); for (int i = 0 ; i < 128; ++i) array2[i] <= {4{i}}; for (int i = 0 ; i < 128; ++i) `checkh(array2[i], 0); end `at_posedge_clk_on_cycle(2) begin for (int i = 0 ; i < 128; ++i) `checkh(array2[i], {4{i}}); for (int i = 0 ; i < 128; ++i) array2[i] <= {4{~i}}; for (int i = 0 ; i < 128; ++i) `checkh(array2[i], {4{i}}); end `at_posedge_clk_on_cycle(3) begin for (int i = 0 ; i < 128; ++i) `checkh(array2[i], {4{~i}}); for (int i = 0 ; i < 128; ++i) array2[i] <= '1; for (int i = 0 ; i < 128; ++i) `checkh(array2[i], {4{~i}}); end `at_posedge_clk_on_cycle(4) begin for (int i = 0 ; i < 128; ++i) `checkh(array2[i], ~128'b0); end // Case 3: wide packed variable, whole element updates only - 2D typedef logic [127:0] elem3_t; typedef elem3_t array3sub_t[512]; typedef array3sub_t array3_t[128]; array3_t array3; `at_posedge_clk_on_cycle(0) begin for (int i = 0 ; i < 128; ++i) for (int j = 0 ; j < 512; ++j) array3[i][j] = 0; for (int i = 0 ; i < 128; ++i) for (int j = 0 ; j < 512; ++j) `checkh(array3[i][j], 0); end `at_posedge_clk_on_cycle(1) begin for (int i = 0 ; i < 128; ++i) for (int j = 0 ; j < 512; ++j) `checkh(array3[i][j], 0); for (int i = 0 ; i < 128; ++i) for (int j = 0 ; j < 512; ++j) array3[i][j] <= {4{i}}; for (int i = 0 ; i < 128; ++i) for (int j = 0 ; j < 512; ++j) `checkh(array3[i][j], 0); end `at_posedge_clk_on_cycle(2) begin for (int i = 0 ; i < 128; ++i) for (int j = 0 ; j < 512; ++j) `checkh(array3[i][j], {4{i}}); for (int i = 0 ; i < 128; ++i) for (int j = 0 ; j < 512; ++j) array3[i][j] <= {4{~i}}; for (int i = 0 ; i < 128; ++i) for (int j = 0 ; j < 512; ++j) `checkh(array3[i][j], {4{i}}); end `at_posedge_clk_on_cycle(3) begin for (int i = 0 ; i < 128; ++i) for (int j = 0 ; j < 512; ++j) `checkh(array3[i][j], {4{~i}}); for (int i = 0 ; i < 128; ++i) for (int j = 0 ; j < 512; ++j) array3[i][j] <= '1; for (int i = 0 ; i < 128; ++i) for (int j = 0 ; j < 512; ++j) `checkh(array3[i][j], {4{~i}}); end `at_posedge_clk_on_cycle(4) begin for (int i = 0 ; i < 128; ++i) for (int j = 0 ; j < 512; ++j) `checkh(array3[i][j], ~128'b0); end // Case 4: real typedef real elem4_t; typedef elem4_t array4_t[128]; array4_t array4; `at_posedge_clk_on_cycle(0) begin for (int i = 0 ; i < 128; ++i) array4[i] = 1e-5; for (int i = 0 ; i < 128; ++i) `checkr(array4[i], 1e-5); end `at_posedge_clk_on_cycle(1) begin for (int i = 0 ; i < 128; ++i) `checkr(array4[i], 1e-5); for (int i = 0 ; i < 128; ++i) array4[i] <= 3.14*real'(i); for (int i = 0 ; i < 128; ++i) `checkr(array4[i], 1e-5); end `at_posedge_clk_on_cycle(2) begin for (int i = 0 ; i < 128; ++i) `checkr(array4[i], 3.14*real'(i)); for (int i = 0 ; i < 128; ++i) array4[i] <= 2.78*real'(i); for (int i = 0 ; i < 128; ++i) `checkr(array4[i], 3.14*real'(i)); end `at_posedge_clk_on_cycle(3) begin for (int i = 0 ; i < 128; ++i) `checkr(array4[i], 2.78*real'(i)); for (int i = 0 ; i < 128; ++i) array4[i] <= 1e50; for (int i = 0 ; i < 128; ++i) `checkr(array4[i], 2.78*real'(i)); end `at_posedge_clk_on_cycle(4) begin for (int i = 0 ; i < 128; ++i) `checkr(array4[i], 1e50); end // Case 5: narrow packed variable, partial element updates - 1D typedef logic [31:0] elem5_t; typedef elem5_t array5_t[128]; array5_t array5; `at_posedge_clk_on_cycle(0) begin for (int i = 0 ; i < 128; ++i) array5[i] = -1; for (int i = 0 ; i < 128; ++i) `checkh(array5[i], -1); end `at_posedge_clk_on_cycle(1) begin for (int i = 0 ; i < 128; ++i) `checkh(array5[i], -1); for (int i = 0 ; i < 128; ++i) array5[i][0] <= 1'b0; for (int i = 0 ; i < 128; ++i) array5[i][1] <= 1'b0; for (int i = 0 ; i < 128; ++i) array5[i][2] <= 1'b0; for (int i = 0 ; i < 128; ++i) array5[i][1] <= 1'b1; for (int i = 0 ; i < 128; ++i) `checkh(array5[i], -1); end `at_posedge_clk_on_cycle(2) begin for (int i = 0 ; i < 128; ++i) `checkh(array5[i], 32'hffff_fffa); for (int i = 0 ; i < 128; ++i) array5[i][18:16] <= i[3:1]; for (int i = 0 ; i < 128; ++i) array5[i][19:17] <= ~i[2:0]; for (int i = 0 ; i < 128; ++i) `checkh(array5[i], 32'hffff_fffa); end `at_posedge_clk_on_cycle(3) begin for (int i = 0 ; i < 128; ++i) `checkh(array5[i], {12'hfff, ~i[2:0], i[1], 16'hfffa}); for (int i = 0 ; i < 128; ++i) array5[i] <= -1; for (int i = 0 ; i < 128; ++i) `checkh(array5[i], {12'hfff, ~i[2:0], i[1], 16'hfffa}); end `at_posedge_clk_on_cycle(4) begin for (int i = 0 ; i < 128; ++i) `checkh(array5[i], -1); end // Case 6: wide packed variable, partial element updates - 1D typedef logic [99:0] elem6_t; typedef elem6_t array6_t[128]; array6_t array6; `at_posedge_clk_on_cycle(0) begin for (int i = 0 ; i < 128; ++i) array6[i] = -1; for (int i = 0 ; i < 128; ++i) `checkh(array6[i], -1); end `at_posedge_clk_on_cycle(1) begin for (int i = 0 ; i < 128; ++i) `checkh(array6[i], -1); for (int i = 0 ; i < 128; ++i) array6[i][80] <= 1'b0; for (int i = 0 ; i < 128; ++i) array6[i][81] <= 1'b0; for (int i = 0 ; i < 128; ++i) array6[i][82] <= 1'b0; for (int i = 0 ; i < 128; ++i) array6[i][81] <= 1'b1; for (int i = 0 ; i < 128; ++i) `checkh(array6[i], -1); end `at_posedge_clk_on_cycle(2) begin for (int i = 0 ; i < 128; ++i) `checkh(array6[i], 100'hf_fffa_ffff_ffff_ffff_ffff_ffff); for (int i = 0 ; i < 128; ++i) array6[i][86:84] <= ~i[3:1]; for (int i = 0 ; i < 128; ++i) array6[i][87:85] <= i[2:0]; for (int i = 0 ; i < 128; ++i) `checkh(array6[i], 100'hf_fffa_ffff_ffff_ffff_ffff_ffff); end `at_posedge_clk_on_cycle(3) begin for (int i = 0 ; i < 128; ++i) `checkh(array6[i], {12'hfff, i[2:0], ~i[1], 84'ha_ffff_ffff_ffff_ffff_ffff}); for (int i = 0 ; i < 128; ++i) array6[i] <= -1; for (int i = 0 ; i < 128; ++i) `checkh(array6[i], {12'hfff, i[2:0], ~i[1], 84'ha_ffff_ffff_ffff_ffff_ffff}); end `at_posedge_clk_on_cycle(4) begin for (int i = 0 ; i < 128; ++i) `checkh(array6[i], -1); end // Case 7: variable partial updates typedef logic [99:0] elem7_t; typedef elem7_t array7sub_t[256]; typedef array7sub_t array7_t[128]; array7_t array7_nba; array7_t array7_ref; always @(posedge clk) begin if (cyc == 0) begin for (int i = 0 ; i < 128; ++i) for (int j = 0 ; j < 256; ++j) array7_nba[i][j] = 100'b0; for (int i = 0 ; i < 128; ++i) for (int j = 0 ; j < 256; ++j) array7_ref[i][j] = ~100'b0; end else begin for (int i = 0 ; i < 128; ++i) for (int j = 0 ; j < 256; ++j) `checkh(array7_nba[i][j], ~array7_ref[i][j]); for (int i = 0 ; i < 128; ++i) begin for (int j = 0 ; j < 256; ++j) begin array7_nba[i[6:0] ^ crc[30+:7]][j[7:0] ^ crc[10+:8]][7'((crc % 10) * 5) +: 5] <= ~crc[4+:5]; array7_ref[i[6:0] ^ crc[30+:7]][j[7:0] ^ crc[10+:8]][7'((crc % 10) * 5) +: 5] = crc[4+:5]; end end end end // Case 8: Mixed dynamic/non-dynamic typedef longint elem8_t; typedef elem8_t array8_t[4]; array8_t array8; `at_posedge_clk_on_cycle(0) begin array8[0] <= 0; array8[1] <= 0; array8[2] <= 0; array8[3] <= 0; end `at_posedge_clk_on_cycle(1) begin `checkh(array8[0], 0); `checkh(array8[1], 0); `checkh(array8[2], 0); `checkh(array8[3], 0); array8[1] <= 42; array8[3] <= 63; for (int i = 1 ; i < 3 ; ++i) array8[i] <= 2*i + 7; array8[1] <= 74; end `at_posedge_clk_on_cycle(3) begin `checkh(array8[0], 0); `checkh(array8[1], 74); `checkh(array8[2], 11); `checkh(array8[3], 63); end // Case 9: string typedef string elem9_t; typedef elem9_t array9_t[10]; array9_t array9; `at_posedge_clk_on_cycle(0) begin for (int i = 0 ; i < 10; ++i) array9[i] = "squid"; for (int i = 0 ; i < 10; ++i) `checks(array9[i], "squid"); end `at_posedge_clk_on_cycle(1) begin for (int i = 0 ; i < 10; ++i) `checks(array9[i], "squid"); for (int i = 0 ; i < 10; ++i) array9[i] <= "octopus"; for (int i = 0 ; i < 10; ++i) `checks(array9[i], "squid"); end `at_posedge_clk_on_cycle(2) begin for (int i = 0 ; i < 10; ++i) `checks(array9[i], "octopus"); for (int i = 1 ; i < 9; ++i) begin string tmp; $sformat(tmp, "%0d-legged-cephalopod", i); array9[i] <= tmp; end for (int i = 0 ; i < 10; ++i) `checks(array9[i], "octopus"); end `at_posedge_clk_on_cycle(3) begin `checks(array9[0], "octopus"); `checks(array9[1], "1-legged-cephalopod"); `checks(array9[2], "2-legged-cephalopod"); `checks(array9[3], "3-legged-cephalopod"); `checks(array9[4], "4-legged-cephalopod"); `checks(array9[5], "5-legged-cephalopod"); `checks(array9[6], "6-legged-cephalopod"); `checks(array9[7], "7-legged-cephalopod"); `checks(array9[8], "8-legged-cephalopod"); `checks(array9[9], "octopus"); for (int i = 0 ; i < 10; ++i) array9[i] <= "cuttlefish"; `checks(array9[0], "octopus"); `checks(array9[1], "1-legged-cephalopod"); `checks(array9[2], "2-legged-cephalopod"); `checks(array9[3], "3-legged-cephalopod"); `checks(array9[4], "4-legged-cephalopod"); `checks(array9[5], "5-legged-cephalopod"); `checks(array9[6], "6-legged-cephalopod"); `checks(array9[7], "7-legged-cephalopod"); `checks(array9[8], "8-legged-cephalopod"); `checks(array9[9], "octopus"); end `at_posedge_clk_on_cycle(4) begin for (int i = 0 ; i < 10; ++i) `checks(array9[i], "cuttlefish"); end endmodule verilator-5.042/test_regress/t/t_fork_join_none_virtual.v0000644000542200017500000000226215101701376024347 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 event evt1; typedef enum {ENUM_VALUE} enum_t; class Foo; int m_member; enum_t m_en; virtual task do_something(); fork #20 begin m_member++; $display("this's m_member: %0d m_en: %s", m_member, m_en.name()); if (m_member != 3) $stop; ->evt1; end #10 begin m_member++; bar(this); end join_none endtask static task bar(Foo foo); fork begin foo.m_member++; $display("foo's m_member: %0d m_en: %s", foo.m_member, foo.m_en.name()); if (foo.m_member != 2) $stop; end join_none endtask endclass class Subfoo extends Foo; virtual task do_something();#5;endtask endclass module t(); initial begin Subfoo subfoo; Foo foo; subfoo = new; subfoo.do_something(); foo = new; foo.m_member = 0; foo.do_something(); end always @(evt1) begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_enum_param_class.v0000644000542200017500000000165015101701376023113 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Anthony Donlon. // SPDX-License-Identifier: CC0-1.0 /// (See bug4551) /// Verilator creates an AstEnumItemRef for each reference. If the enum is inside a parameterizable class/module, it /// should be handled properly. class ClsParam #( int A = 0 ); typedef enum int { EN_A = A + 0, EN_B = A + 1, EN_C = A + 2 } enums_t; int val = EN_C; function int test(); return EN_C; endfunction endclass; module t; // localparam ENUM_VAL = ClsParam#(100)::EN_C; // TODO: Unsupported: dotted expressions in parameters // $info("ENUM_VAL: %0d", ENUM_VAL); ClsParam#(100) cls = new; initial begin if (cls.test() != 102) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_interface_modport_export.v0000644000542200017500000000253115101701376024706 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // A test of the export parameter used with modport // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 interface test_if; // Pre-declare function extern function myfunc (input logic val); // Interface variable logic data; // Modport modport mp_e( export myfunc, output data ); // Modport modport mp_i( import myfunc, output data ); endinterface // test_if module t (/*AUTOARG*/ // Inputs clk ); input clk; test_if i (); testmod_callee testmod_callee_i (.ie (i.mp_e)); testmod_caller testmod_caller_i (.clk (clk), .ii (i.mp_i)); endmodule module testmod_callee ( test_if.mp_e ie ); function automatic logic ie.myfunc (input logic val); begin myfunc = (val == 1'b0); end endfunction endmodule // testmod_caller module testmod_caller ( input clk, test_if.mp_i ii ); always @(posedge clk) begin ii.data = 1'b0; if (ii.myfunc (1'b0)) begin $write("*-* All Finished *-*\n"); $finish; end else begin $stop; end end endmodule verilator-5.042/test_regress/t/t_class_static_method_protect_ids.py0000755000542200017500000000152315101701376026402 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_class_static_method.v" # This test makes randomly named .cpp/.h files, which tend to collect, so remove them first for filename in (glob.glob(test.obj_dir + "/*_PS*.cpp") + glob.glob(test.obj_dir + "/*_PS*.h") + glob.glob(test.obj_dir + "/*.d")): test.unlink_ok(filename) test.compile(verilator_flags2=["--protect-ids", "--protect-key SECRET_KEY"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_ftask_output_assign_bad.v0000644000542200017500000000114315101701376025527 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( input logic in, output wire wire_out, output logic reg_out ); function void set_f(output set_out, input set_in); set_out = 1; endfunction task set_task(output set_out, input set_in); set_out = 1; endtask always_comb begin : setCall set_f(wire_out, in); set_f(reg_out, in); set_task(wire_out, in); set_task(reg_out, in); end endmodule verilator-5.042/test_regress/t/t_force_release_net_reverse.py0000755000542200017500000000105615101701376025167 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_force_release_net.v" test.compile(verilator_flags2=['+define+REVERSE']) test.execute() test.passes() verilator-5.042/test_regress/t/t_sdf_annotate_unsup.v0000644000542200017500000000115015101701376023474 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias' // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin $sdf_annotate("file.sdf"); $sdf_annotate("file.sdf",); $sdf_annotate("file.sdf", t); // TArguments are all optional, so test more exhaustively $sdf_annotate("file.sdf", t, "config_file", "log_file", "mtm_spec", "scale_factors", "scale_type"); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_std_randomize.v0000644000542200017500000000363315101701376022447 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by PlanV GmbH. // SPDX-License-Identifier: CC0-1.0 class std_randomize_class; rand bit [7:0] addr; rand bit [31:0] data; rand bit [63:0] data_x_4; bit [7:0] old_addr; bit [31:0] old_data; bit [63:0] old_data_x_4; function bit std_randomize(); int success; bit valid; old_addr = addr; old_data = data; old_data_x_4 = data_x_4; success = std::randomize(addr, data); valid = (success == 1) && !(addr == old_addr || data == old_data) && data_x_4 == old_data_x_4; return valid; endfunction endclass module t_scope_std_randomize; bit [7:0] addr; bit [15:0] data; function bit run(); int ready; int success; bit [7:0] old_addr; bit [15:0] old_data; int old_ready; old_addr = addr; old_data = data; old_ready = ready; success = randomize(addr, ready); // std::randomize if (success == 0) return 0; if (addr == old_addr && data != old_data && ready == old_ready) begin return 0; end return 1; endfunction std_randomize_class test; initial begin bit ok = 0; int success; test = new(); test.old_addr = test.addr; test.old_data = test.data; test.old_data_x_4 = test.data_x_4; success = std::randomize(test.addr, test.data); ok = (success == 1) && !(test.addr == test.old_addr || test.data == test.old_data) && test.data_x_4 == test.old_data_x_4; if (!ok) $stop; ok = 0; ok = run(); if (!ok) $stop; ok = 0; ok = test.std_randomize(); if (!ok) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_func_range.v0000644000542200017500000000312315101701376021706 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; // verilator lint_off WIDTH `define INT_RANGE 31:0 `define INT_RANGE_MAX 31 `define VECTOR_RANGE 63:0 reg [`INT_RANGE] stashb, stasha, stashn, stashm; function [`VECTOR_RANGE] copy_range; input [`VECTOR_RANGE] y; input [`INT_RANGE] b; input [`INT_RANGE] a; input [`VECTOR_RANGE] x; input [`INT_RANGE] n; input [`INT_RANGE] m; begin copy_range = y; stashb = b; stasha = a; stashn = n; stashm = m; end endfunction parameter DATA_SIZE = 16; parameter NUM_OF_REGS = 32; reg [NUM_OF_REGS*DATA_SIZE-1 : 0] memread_rf; reg [DATA_SIZE-1:0] memread_rf_reg; always @(memread_rf) begin : memread_convert memread_rf_reg = copy_range('d0, DATA_SIZE-'d1, DATA_SIZE-'d1, memread_rf, DATA_SIZE-'d1, DATA_SIZE-'d1); end integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin memread_rf = 512'haa; end if (cyc==3) begin if (stashb != 'd15) $stop; if (stasha != 'd15) $stop; if (stashn != 'd15) $stop; if (stashm != 'd15) $stop; $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.042/test_regress/t/t_select_set.v0000644000542200017500000000256415101701376021741 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; reg [63:0] inwide; reg [39:0] addr; integer cyc; initial cyc=1; always @ (posedge clk) begin `ifdef TEST_VERBOSE $write ("%x %x\n", cyc, addr); `endif if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin addr <= 40'h12_3456_7890; end if (cyc==2) begin if (addr !== 40'h1234567890) $stop; addr[31:0] <= 32'habcd_efaa; end if (cyc==3) begin if (addr !== 40'h12abcdefaa) $stop; addr[39:32] <= 8'h44; inwide <= 64'hffeeddcc_11334466; end if (cyc==4) begin if (addr !== 40'h44abcdefaa) $stop; addr[31:0] <= inwide[31:0]; end if (cyc==5) begin if (addr !== 40'h4411334466) $stop; $display ("Flip [%x]\n", inwide[3:0]); addr[{2'b0,inwide[3:0]}] <= ! addr[{2'b0,inwide[3:0]}]; end if (cyc==6) begin if (addr !== 40'h4411334426) $stop; end if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.042/test_regress/t/t_case_write1.out0000644000542200017500000001674715101701376022367 0ustar mahmoudyfreeshell[2] crc=0000000000000097 1410 [3] crc=000000000000012e 1410 [4] crc=000000000000025d 1410 [5] crc=00000000000004ba 1410 [6] crc=0000000000000974 1410 [7] crc=00000000000012e9 1410 [8] crc=00000000000025d3 1410 [9] crc=0000000000004ba7 1410 [10] crc=000000000000974e 1410 [11] crc=0000000000012e9d 1410 [12] crc=0000000000025d3a 1410 [13] crc=000000000004ba74 1410 [14] crc=00000000000974e9 1410 [15] crc=000000000012e9d3 1410 [16] crc=000000000025d3a7 1410 [17] crc=00000000004ba74e 1410 [18] crc=0000000000974e9d 1410 [19] crc=00000000012e9d3a 1410 [20] crc=00000000025d3a74 1410 [21] crc=0000000004ba74e9 1410 [22] crc=000000000974e9d3 1304a:000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002031303039;17 1304b:000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002031303039203233 1304c:000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020313030392032332031333033;4 1304d:000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002031303039203233203133303320313338 1304e:203130303920323320313330332031333820202020202020202020202020202020202020202020202020202020202020202020202020202020202020202020202020202020202020202020202020 1304: 1009 23 1303 138 [23] crc=0000000012e9d3a7 1313: 1009 46 1309 1311 143 1312 [24] crc=0000000025d3a74e 1129: 1009 172 407 175 408 409 410 1106 [25] crc=000000004ba74e9d 1017: 1009 223 1014 880 885 1015 1016 1007 [26] crc=00000000974e9d3a 1231: 1229 967 1230 718 [27] crc=000000012e9d3a74 1410 [28] crc=000000025d3a74e9 1370: 1009 58 1369 19 [29] crc=00000004ba74e9d3 1036: 1009 194 1033 1034 1008 1035 880 [30] crc=0000000974e9d3a7 1409:i [31] crc=00000012e9d3a74e 1321: 1009 29 1320 137 144 141 138 148 [32] crc=00000025d3a74e9d 1383:§ [33] crc=0000004ba74e9d3a 1021: 1009 216 1018 882 884 1019 1020 1007 [34] crc=000000974e9d3a74 1017: 1009 197 1014 882 883 1015 1016 1008 [35] crc=0000012e9d3a74e9 1231: 1228 979 1230 713 [36] crc=0000025d3a74e9d3 1013: 1009 194 1011 1006 1008 1012 880 [37] crc=000004ba74e9d3a7 1409:i [38] crc=00000974e9d3a74e 1321: 1009 29 1320 137 144 141 138 148 [39] crc=000012e9d3a74e9d 1383:§ [40] crc=000025d3a74e9d3a 1021: 1009 216 1018 882 884 1019 1020 1007 [41] crc=00004ba74e9d3a74 1017: 1009 197 1014 882 883 1015 1016 1008 [42] crc=0000974e9d3a74e9 1231: 1228 979 1230 713 [43] crc=00012e9d3a74e9d3 1013: 1009 194 1011 1006 1008 1012 880 [44] crc=00025d3a74e9d3a7 1409:i [45] crc=0004ba74e9d3a74e 1321: 1009 29 1320 137 144 141 138 148 [46] crc=000974e9d3a74e9d 1383:§ [47] crc=0012e9d3a74e9d3a 1021: 1009 216 1018 882 884 1019 1020 1007 [48] crc=0025d3a74e9d3a74 1017: 1009 197 1014 882 883 1015 1016 1008 [49] crc=004ba74e9d3a74e9 1231: 1228 979 1230 713 [50] crc=00974e9d3a74e9d3 1013: 1009 194 1011 1006 1008 1012 880 [51] crc=012e9d3a74e9d3a7 1409:i [52] crc=025d3a74e9d3a74e 1321: 1009 29 1320 137 144 141 138 148 [53] crc=04ba74e9d3a74e9d 1383:§ [54] crc=0974e9d3a74e9d3a 1021: 1009 216 1018 882 884 1019 1020 1007 [55] crc=12e9d3a74e9d3a74 1017: 1009 197 1014 882 883 1015 1016 1008 [56] crc=25d3a74e9d3a74e9 1231: 1228 979 1230 713 [57] crc=4ba74e9d3a74e9d3 1013: 1009 194 1011 1006 1008 1012 880 [58] crc=974e9d3a74e9d3a7 1409:i [59] crc=2e9d3a74e9d3a74f 1321: 1009 29 1320 137 144 141 138 149 [60] crc=5d3a74e9d3a74e9e 1383:§ [61] crc=ba74e9d3a74e9d3d 1021: 1009 216 1018 882 884 1019 1020 1007 [62] crc=74e9d3a74e9d3a7b 1017: 1009 197 1014 882 883 1015 1016 1008 [63] crc=e9d3a74e9d3a74f7 1231: 1228 979 1230 713 [64] crc=d3a74e9d3a74e9ef 1013: 1009 194 1011 1006 1008 1012 880 [65] crc=a74e9d3a74e9d3df 1409:i [66] crc=4e9d3a74e9d3a7bf 1321: 1009 29 1320 137 144 141 145 149 [67] crc=9d3a74e9d3a74f7e 1383:§ [68] crc=3a74e9d3a74e9efc 1021: 1009 216 1018 882 884 1019 1020 1007 [69] crc=74e9d3a74e9d3df9 1017: 1009 197 1014 882 883 1015 1016 1008 [70] crc=e9d3a74e9d3a7bf3 1231: 1228 979 1230 713 [71] crc=d3a74e9d3a74f7e6 1013: 1009 194 1011 1006 1008 1012 880 [72] crc=a74e9d3a74e9efcc 1409:i [73] crc=4e9d3a74e9d3df98 1321: 1009 29 1320 137 147 149 143 142 [74] crc=9d3a74e9d3a7bf30 1383:§ [75] crc=3a74e9d3a74f7e61 1021: 1009 216 1018 882 885 1019 1020 1007 [76] crc=74e9d3a74e9efcc3 1017: 1009 197 1014 882 884 1015 1016 1008 [77] crc=e9d3a74e9d3df987 1231: 1228 982 1230 713 [78] crc=d3a74e9d3a7bf30f 1013: 1009 194 1011 1006 1008 1012 881 885 [79] crc=a74e9d3a74f7e61f 1409:w [80] crc=4e9d3a74e9efcc3f 1321: 1009 30 1320 149 146 146 137 149 [81] crc=9d3a74e9d3df987e 1383:ß [82] crc=3a74e9d3a7bf30fc 1021: 1009 225 1018 882 885 1019 1020 1008 [83] crc=74e9d3a74f7e61f9 1017: 1009 218 1014 882 884 1015 1016 1008 [84] crc=e9d3a74e9efcc3f3 1231: 1228 981 1230 708 [85] crc=d3a74e9d3df987e6 1013: 1009 232 1011 1005 1008 1012 881 883 [86] crc=a74e9d3a7bf30fcc 1409:s [87] crc=4e9d3a74f7e61f98 1262: 1009 1006 1258 846 1259 1006 1260 833 1261 [88] crc=9d3a74e9efcc3f30 1321: 1009 124 1320 146 137 149 137 134 [89] crc=3a74e9d3df987e61 1383:˜ [90] crc=74e9d3a7bf30fcc3 1036: 1009 215 1033 1034 1008 1035 879 verilator-5.042/test_regress/t/t_class_new_scoped_bad.out0000644000542200017500000000052215101701376024262 0ustar mahmoudyfreeshell%Error: t/t_class_new_scoped_bad.v:17:16: new() assignment not legal to non-class 'Pkg' : ... note: In instance 't' 17 | c = Pkg::new; | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_mem_multiwire.py0000755000542200017500000000073415101701376022651 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_unpacked_str_pair.py0000755000542200017500000000073415101701376023467 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_struct_cons_cast.v0000644000542200017500000000246515101701376023167 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class uvm_policy; typedef enum { NEVER, STARTED, FINISHED } recursion_state_e; endclass typedef enum { UVM_DEFAULT_POLICY = 0, UVM_DEEP = (1<<16), UVM_SHALLOW = (1<<17), UVM_REFERENCE = (1<<18) } uvm_recursion_policy_enum; class Cls; typedef struct { uvm_policy::recursion_state_e state; bit ret_val; } state_info_t; state_info_t m_recur_states/*[uvm_object][uvm_object]*/[uvm_recursion_policy_enum]; function uvm_recursion_policy_enum get_recursion_policy(); return UVM_DEEP; endfunction function bit get_ret_val(); return $c(1); endfunction function void test(); bit ret_val; ret_val = $c1(1); // See issue #4568 m_recur_states[get_recursion_policy()] = '{uvm_policy::FINISHED, ret_val}; endfunction endclass module t; initial begin Cls c; c = new; $display("%p", c); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_clocker.out0000644000542200017500000000372715101701376021575 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $var wire 1 # clk $end $var wire 1 $ res $end $var wire 8 % res8 [7:0] $end $var wire 16 & res16 [15:0] $end $scope module $unit $end $var wire 32 + ID_MSB [31:0] $end $upscope $end $scope module t $end $var wire 1 # clk $end $var wire 1 $ res $end $var wire 8 % res8 [7:0] $end $var wire 16 & res16 [15:0] $end $var wire 8 ' clkSet [7:0] $end $var wire 1 # clk_1 $end $var wire 3 ( clk_3 [2:0] $end $var wire 4 ) clk_4 [3:0] $end $var wire 1 # clk_final $end $var wire 8 * count [7:0] $end $upscope $end $upscope $end $enddefinitions $end #0 0# 0$ b00000000 % b0000000000000000 & b00000000 ' b000 ( b0000 ) b00000000 * b00000000000000000000000000000001 + #10 1# 1$ b11101111 % b0000000111111111 & b11111111 ' b111 ( b1111 ) b00000001 * #15 0# 0$ b00000000 % b0000001000000000 & b00000000 ' b000 ( b0000 ) b00000010 * #20 1# 1$ b11101111 % b0000001111111111 & b11111111 ' b111 ( b1111 ) b00000011 * #25 0# 0$ b00000000 % b0000010000000000 & b00000000 ' b000 ( b0000 ) b00000100 * #30 1# 1$ b11101111 % b0000010111111111 & b11111111 ' b111 ( b1111 ) b00000101 * #35 0# 0$ b00000000 % b0000011000000000 & b00000000 ' b000 ( b0000 ) b00000110 * #40 1# 1$ b11101111 % b0000011111111111 & b11111111 ' b111 ( b1111 ) b00000111 * #45 0# 0$ b00000000 % b0000100000000000 & b00000000 ' b000 ( b0000 ) b00001000 * #50 1# 1$ b11101111 % b0000100111111111 & b11111111 ' b111 ( b1111 ) b00001001 * #55 0# 0$ b00000000 % b0000101000000000 & b00000000 ' b000 ( b0000 ) b00001010 * #60 1# 1$ b11101111 % b0000101111111111 & b11111111 ' b111 ( b1111 ) b00001011 * #65 0# 0$ b00000000 % b0000110000000000 & b00000000 ' b000 ( b0000 ) b00001100 * #70 1# 1$ b11101111 % b0000110111111111 & b11111111 ' b111 ( b1111 ) b00001101 * #75 0# 0$ b00000000 % b0000111000000000 & b00000000 ' b000 ( b0000 ) b00001110 * #80 1# 1$ b11101111 % b0000111111111111 & b11111111 ' b111 ( b1111 ) b00001111 * verilator-5.042/test_regress/t/t_opt_subst.py0000755000542200017500000000113515101701376022010 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.compile(verilator_flags2=["--stats"]) if test.vlt_all: test.file_grep(test.stats, r'Optimizations, Substituted temps\s+(\d+)', 43) test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_assigneqexpr_bad.py0000755000542200017500000000161715101701376024340 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_lint_assigneqexpr.v" test.lint(verilator_flags2=['-Wall -Wno-DECLFILENAME'], fails=True, expect_filename=test.golden_filename) test.extract(in_filename=test.top_filename, out_filename=test.root + "/docs/gen/ex_ASSIGNEQEXPR_faulty.rst", lines="26-29") test.extract(in_filename=test.golden_filename, out_filename=test.root + "/docs/gen/ex_ASSIGNEQEXPR_msg.rst", lines="7-8") test.passes() verilator-5.042/test_regress/t/t_dpi_export_scope_bad.out0000644000542200017500000000020615101701376024314 0ustar mahmoudyfreeshell%Error: unknown:0: Testbench C called 'dpix_task' but this DPI export function exists only in other scopes, not scope 't' Aborting... verilator-5.042/test_regress/t/t_interface_gen3_noinl.py0000755000542200017500000000103715101701376024042 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_gen3.v" test.compile(v_flags2=["-fno-inline"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_public_func.vlt0000644000542200017500000000040615101701376023607 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. // SPDX-License-Identifier: CC0-1.0 `verilator_config public -module "glbl" -function "setGSR" verilator-5.042/test_regress/t/t_order_clkinst.v0000644000542200017500000000551015101701376022443 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; // verilator lint_off COMBDLY // verilator lint_off LATCH // verilator lint_off UNOPT // verilator lint_off UNOPTFLAT // verilator lint_off MULTIDRIVEN reg c1_start; initial c1_start = 0; wire [31:0] c1_count; comb_loop c1 (.count(c1_count), .start(c1_start)); wire s2_start = c1_start; wire [31:0] s2_count; seq_loop s2 (.count(s2_count), .start(s2_start)); wire c3_start = (s2_count[0]); wire [31:0] c3_count; comb_loop c3 (.count(c3_count), .start(c3_start)); reg [7:0] cyc; initial cyc = 0; always @ (posedge clk) begin //$write("[%0t] %x counts %x %x %x\n", $time,cyc,c1_count,s2_count,c3_count); cyc <= cyc + 8'd1; case (cyc) 8'd00: begin c1_start <= 1'b0; end 8'd01: begin c1_start <= 1'b1; end default: ; endcase case (cyc) 8'd02: begin // On Verilator, we expect these comparisons to match exactly, // confirming that our settle loop repeated the exact number of // iterations we expect. No '$stop' should be called here, and we // should reach the normal '$finish' below on the next cycle. if (c1_count!=32'h3) $stop; if (s2_count!=32'h3) $stop; if (c3_count!=32'h3) $stop; end 8'd03: begin $write("*-* All Finished *-*\n"); $finish; end default: ; endcase end endmodule module comb_loop (/*AUTOARG*/ // Outputs count, // Inputs start ); input start; output reg [31:0] count = 0; reg [31:0] runnerm1, runner; initial runner = 0; always @ (posedge start) begin count = 0; runner = 3; end always @ (/*AS*/runner) begin runnerm1 = runner - 32'd1; end always @ (/*AS*/runnerm1) begin if (runner > 0) begin count = count + 1; runner = runnerm1; $write ("%m count=%d runner =%x\n",count, runnerm1); end end endmodule module seq_loop (/*AUTOARG*/ // Outputs count, // Inputs start ); input start; output reg [31:0] count; initial count = 0; reg [31:0] runnerm1, runner; initial runner = 0; always @ (posedge start) begin count = 0; runner <= 3; end always @ (/*AS*/runner) begin runnerm1 = runner - 32'd1; end always @ (/*AS*/runnerm1) begin if (runner > 0) begin count = count + 1; runner <= runnerm1; $write ("%m count=%d runner<=%x\n",count, runnerm1); end end endmodule verilator-5.042/test_regress/t/t_vlt_syntax_bad.out0000644000542200017500000000265315101701376023171 0ustar mahmoudyfreeshell%Error: t/t_vlt_syntax_bad.vlt:9:20: sensitivity not expected for attribute 9 | public -module "t" @(posedge clk) | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_vlt_syntax_bad.vlt:11:1: isolate_assignments only applies to signals or functions/tasks 11 | isolate_assignments -module "t" | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_vlt_syntax_bad.vlt:13:1: Argument -match only supported for lint_off 13 | tracing_off --file "*" -match "nothing" | ^~~~~~~~~~~ %Error: t/t_vlt_syntax_bad.vlt:15:1: Argument -scope only supported for tracing_on/off 15 | lint_off --rule UNOPTFLAT -scope "top*" | ^~~~~~~~ %Error: t/t_vlt_syntax_bad.vlt:16:1: Argument -scope only supported for tracing_on/off_off 16 | lint_off --rule UNOPTFLAT -scope "top*" -levels 0 | ^~~~~~~~ %Error: t/t_vlt_syntax_bad.vlt:17:1: Argument -scope only supported for tracing_on/off 17 | lint_on --rule UNOPTFLAT -scope "top*" | ^~~~~~~ %Error: t/t_vlt_syntax_bad.vlt:18:1: Argument -scope only supported for tracing_on/off_off 18 | lint_on --rule UNOPTFLAT -scope "top*" -levels 0 | ^~~~~~~ %Error: t/t_vlt_syntax_bad.vlt:20:1: forceable missing -module 20 | forceable -module "" -var "net_*" | ^~~~~~~~~ %Error: t/t_vlt_syntax_bad.vlt:22:1: missing -var 22 | forceable -module "top" -var "" | ^~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_gantt_two.py0000755000542200017500000000373515101701376022004 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Test for bin/verilator_gantt, import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_gantt.v" test.pli_filename = "t/t_gantt_c.cpp" threads_num = (2 if test.vltmt else 1) test.compile( make_top_shell=False, make_main=False, verilator_flags2=["--prof-exec --exe", test.pli_filename, "t/t_gantt_two.cpp"], # Checks below care about thread count, so use 2 (minimum reasonable) threads=threads_num, make_flags=["CPPFLAGS_ADD=\"-DVL_NO_LEGACY -DTEST_USE_THREADS=" + str(threads_num) + "\""]) test.execute(all_run_flags=[ "+verilator+prof+exec+start+4", " +verilator+prof+exec+window+4", " +verilator+prof+exec+file+" + test.obj_dir + "/profile_exec.dat", " +verilator+prof+vlt+file+" + test.obj_dir + "/profile.vlt"]) # yapf:disable gantt_log = test.obj_dir + "/gantt.log" # The profiling data goes direct to the runtime's STDOUT # (maybe that should go to a separate file - gantt.dat?) test.run(cmd=[ os.environ["VERILATOR_ROOT"] + "/bin/verilator_gantt", test.obj_dir + "/profile_exec.dat", "--vcd " + test.obj_dir + "/profile_exec.vcd", "| tee " + gantt_log]) # yapf:disable if test.vltmt: test.file_grep(gantt_log, r'Total threads += +(\d+)', 2) test.file_grep(gantt_log, r'Total mtasks += +(\d+)', 6) else: test.file_grep(gantt_log, r'Total threads += +(\d+)', 1) test.file_grep(gantt_log, r'Total mtasks += +(\d+)', 0) test.file_grep(gantt_log, r'\|\s+4\s+\|\s+4\.0+\s+\|\s+eval') # Diff to itself, just to check parsing test.vcd_identical(test.obj_dir + "/profile_exec.vcd", test.obj_dir + "/profile_exec.vcd") test.passes() verilator-5.042/test_regress/t/t_trace_two_port_cc.out0000644000542200017500000000365115101701376023647 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module topa $end $var wire 1 # clk $end $scope module t $end $var wire 1 # clk $end $var wire 32 $ cyc [31:0] $end $var wire 32 % c_trace_on [31:0] $end $scope module sub $end $var wire 32 & inside_sub_a [31:0] $end $upscope $end $upscope $end $upscope $end $scope module topb $end $var wire 1 ( clk $end $scope module t $end $var wire 1 ( clk $end $var wire 32 + cyc [31:0] $end $var wire 32 , c_trace_on [31:0] $end $var real 64 ) r $end $scope module sub $end $var wire 32 - inside_sub_a [31:0] $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #10 1# b00000000000000000000000000000001 $ b00000000000000000000000000000000 % 1( r0 ) b00000000000000000000000000000001 & b00000000000000000000000000000001 + b00000000000000000000000000000000 , b00000000000000000000000000000010 - #15 0# 0( #20 1# b00000000000000000000000000000010 $ b00000000000000000000000000000011 % 1( r0.1 ) #25 0# 0( #30 1# b00000000000000000000000000000011 $ b00000000000000000000000000000100 % 1( r0.2 ) #35 0# 0( #40 1# b00000000000000000000000000000100 $ b00000000000000000000000000000101 % 1( r0.3 ) #45 0# 0( #50 1# b00000000000000000000000000000101 $ b00000000000000000000000000000110 % 1( r0.4 ) #55 0# 0( #60 1# b00000000000000000000000000000110 $ b00000000000000000000000000000111 % 1( r0.5 ) #65 0# 0( #70 1# b00000000000000000000000000000111 $ b00000000000000000000000000001000 % 1( r0.6 ) #75 0# 0( #80 1# b00000000000000000000000000001000 $ b00000000000000000000000000001001 % 1( r0.7 ) #85 0# 0( #90 1# b00000000000000000000000000001001 $ b00000000000000000000000000001010 % 1( r0.7999999999999999 ) #95 0# 0( #100 1# b00000000000000000000000000001010 $ b00000000000000000000000000001011 % 1( r0.8999999999999999 ) #105 0# 0( #110 1# b00000000000000000000000000001011 $ b00000000000000000000000000001100 % 1( r0.9999999999999999 ) verilator-5.042/test_regress/t/t_func_v.v0000644000542200017500000000124615101701376021063 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Chandan Egbert. // SPDX-License-Identifier: CC0-1.0 // See bug569 module t(); `ifdef T_FUNC_V_NOINL // verilator no_inline_module `endif level1 ul1(); initial ul1.doit(4'b0); endmodule module level1(); `ifdef T_FUNC_V_NOINL // verilator no_inline_module `endif level2 ul2(); task doit(input logic [3:0] v); ul2.mem = v; $write("*-* All Finished *-*\n"); $finish; endtask endmodule module level2(); `ifdef T_FUNC_V_NOINL // verilator no_inline_module `endif logic [3:0] mem; endmodule verilator-5.042/test_regress/t/t_timing_func_bad.py0000755000542200017500000000103015101701376023070 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename, verilator_flags2=['--no-timing']) test.passes() verilator-5.042/test_regress/t/t_inside_unpacked.v0000644000542200017500000000163515101701376022732 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; int array [10]; logic l; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 0) begin // Setup array[0] = 10; array[1] = 20; array[9] = 90; end else if (cyc < 99) begin l = (10 inside {array}); if (l != 1) $stop; l = (20 inside {array}); if (l != 1) $stop; l = (90 inside {array}); if (l != 1) $stop; l = (99 inside {array}); if (l != 0) $stop; end else if (cyc == 99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_var_dup2.v0000644000542200017500000000055015101701376021322 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Legal with ANSI Verilog 2001 style ports module t ( output wire ok_ow, output reg ok_or); wire ok_o_w; reg ok_o_r; endmodule verilator-5.042/test_regress/t/t_math_eq.py0000755000542200017500000000073415101701376021410 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_select_bad_range.out0000644000542200017500000000126015101701376023402 0ustar mahmoudyfreeshell%Warning-SELRANGE: t/t_select_bad_range.v:16:15: Selection index out of range: 44:44 outside 43:0 : ... note: In instance 't' 16 | sel = mi[44]; | ^ ... For warning description see https://verilator.org/warn/SELRANGE?v=latest ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Warning-SELRANGE: t/t_select_bad_range.v:17:16: Selection index out of range: 44:41 outside 43:0 : ... note: In instance 't' 17 | sel2 = mi[44:41]; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_assert_iff_bad2.py0000755000542200017500000000110515101701376023000 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = 't_assert_iff.v' test.compile(verilator_flags2=['--assert --cc --coverage-user -DFAIL2']) test.execute(fails=True) test.passes() verilator-5.042/test_regress/t/t_dpi_2exp_bad.py0000755000542200017500000000077615101701376022320 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_semaphore.v0000644000542200017500000000240315101701376021562 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Methods defined by IEEE: // class semaphore; // function new(int keyCount = 0); // function void put(int keyCount = 1); // task get(int keyCount = 1); // function int try_get(int keyCount = 1); // endclass `ifndef SEMAPHORE_T `define SEMAPHORE_T semaphore `endif // verilator lint_off DECLFILENAME module t; // From UVM: `SEMAPHORE_T s; `SEMAPHORE_T s2; initial begin s = new(1); if (s.try_get() == 0) $stop; if (s.try_get() != 0) $stop; s = new; if (s.try_get() != 0) $stop; s.put(); s.get(); s.put(2); s.get(2); s.put(2); if (s.try_get(2) <= 0) $stop; fork begin #10; // So later then get() starts below s.put(1); s.put(1); end begin if (s.try_get(1) != 0) $stop; s.get(); // Blocks until put s.get(); end join s2 = new; if (s2.try_get() != 0) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_math_countbits2_bad.out0000644000542200017500000000207615101701376024062 0ustar mahmoudyfreeshell%Error: t/t_math_countbits2_bad.v:15:15: Expected numeric type, but got a 'logic$[0:3]' data type : ... note: In instance 't' 15 | count = $countones(my_vec); | ^~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_math_countbits2_bad.v:16:15: Expected numeric type, but got a 'logic$[0:3]' data type : ... note: In instance 't' 16 | count = $countbits(my_vec, '0); | ^~~~~~~~~~ %Error: t/t_math_countbits2_bad.v:17:14: Expected numeric type, but got a 'logic$[0:3]' data type : ... note: In instance 't' 17 | bool = $onehot(my_vec); | ^~~~~~~ %Error: t/t_math_countbits2_bad.v:18:14: Expected numeric type, but got a 'logic$[0:3]' data type : ... note: In instance 't' 18 | bool = $onehot0(my_vec); | ^~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_foreach.v0000644000542200017500000001111615101701376021207 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2016 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t; // verilator lint_off ASCRANGE // verilator lint_off WIDTH reg [63:0] sum; // Checked not in objects reg [63:0] add; reg [2:1] [4:3] array [5:6] [7:8]; reg [1:2] [3:4] larray [6:5] [8:7]; bit [31:0] depth1_array [0:0]; int oned [3:1]; int twod [3:1][9:8]; string str1; string str2; typedef struct packed { reg [1:0] [63:0] subarray; } str_t; typedef struct packed { str_t mid; } mid_t; mid_t strarray[3]; function [63:0] crc (input [63:0] sum, input [31:0] a, input [31:0] b, input [31:0] c, input [31:0] d); crc = {sum[62:0],sum[63]} ^ {4'b0,a[7:0], 4'h0,b[7:0], 4'h0,c[7:0], 4'h0,d[7:0]}; endfunction initial begin sum = 0; // We use 'index_' as the prefix for all loop vars, // this allows t_foreach.py to confirm that all loops // have been unrolled and flattened away and no loop vars // remain in the generated .cpp foreach (depth1_array[index_a]) begin sum = crc(sum, index_a, 0, 0, 0); // Ensure the index never goes out of bounds. // We used to get this wrong for an array of depth 1. assert (index_a != -1); assert (index_a != 1); end `checkh(sum, 64'h0); sum = 0; foreach (array[index_a]) begin sum = crc(sum, index_a, 0, 0, 0); end `checkh(sum, 64'h000000c000000000); sum = 0; foreach (array[index_a,index_b]) begin sum = crc(sum, index_a, index_b, 0, 0); end `checkh(sum, 64'h000003601e000000); sum = 0; foreach (array[index_a,index_b,index_c]) begin sum = crc(sum, index_a, index_b, index_c, 0); end `checkh(sum, 64'h00003123fc101000); sum = 0; foreach (array[index_a,index_b,index_c,index_d]) begin sum = crc(sum, index_a, index_b, index_c, index_d); end `checkh(sum, 64'h0030128ab2a8e557); // comma syntax sum = 0; foreach (array[,index_b]) begin $display(index_b); sum = crc(sum, 0, index_b, 0, 0); end `checkh(sum, 64'h0000000006000000); // sum = 0; foreach (larray[index_a]) begin sum = crc(sum, index_a, 0, 0, 0); end `checkh(sum, 64'h0000009000000000); sum = 0; foreach (larray[index_a,index_b]) begin sum = crc(sum, index_a, index_b, 0, 0); sum = sum + {4'b0,index_a[7:0], 4'h0,index_b[7:0]}; end `checkh(sum, 64'h000002704b057073); sum = 0; foreach (larray[index_a,index_b,index_c]) begin sum = crc(sum, index_a, index_b, index_c, 0); end `checkh(sum, 64'h00002136f9000000); sum = 0; foreach (larray[index_a,index_b,index_c,index_d]) begin sum = crc(sum, index_a, index_b, index_c, index_d); end `checkh(sum, 64'h0020179aa7aa0aaa); add = 0; strarray[0].mid.subarray[0] = 1; strarray[0].mid.subarray[1] = 2; strarray[1].mid.subarray[0] = 4; strarray[1].mid.subarray[1] = 5; strarray[2].mid.subarray[0] = 6; strarray[2].mid.subarray[1] = 7; foreach (strarray[s]) foreach (strarray[s].mid.subarray[ss]) add += strarray[s].mid.subarray[ss]; `checkh(add, 'h19); add = 0; foreach (oned[i]) begin ++add; break; end `checkh(add, 1); // 9 add = 0; foreach (oned[i]) begin ++add; continue; add += 100; end `checkh(add, 3); // 9, 8, 7 add = 0; foreach (twod[i, j]) begin ++add; break; end // See https://www.accellera.org/images/eda/sv-bc/10303.html `checkh(add, 1); // 3,9 add = 0; foreach (twod[i, j]) begin ++add; continue; add += 100; end `checkh(add, 6); foreach (twod[i, j]); // Null body check str1 = "abcd"; str2 = "1234"; foreach (str1[i]) begin str2[i] = str1[i]; end if (str1 != str2) $stop; str1 = ""; add = 0; foreach(str1[i]) begin add++; end `checkh(add, 0); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_interface_dups.py0000755000542200017500000000073415101701376022765 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_udp_tableeof_bad.py0000755000542200017500000000121715101701376023226 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["--lint-only --bbox-unsup"], fails=test.vlt_all) # Cannot use .out, get "$end" or "end of file" depending on bison version test.file_grep(test.compile_log_filename, r"EOF in 'table'") test.passes() verilator-5.042/test_regress/t/t_covergroup_with_sample_args_too_many_bad.out0000644000542200017500000000062415101701376030462 0ustar mahmoudyfreeshell%Error: t/t_covergroup_with_sample_args_too_many_bad.v:15:26: Too many arguments in function call to FUNC 'sample' : ... note: In instance 't' 15 | cov1.sample(5, 1'b0, 42); | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_no_trace_top.py0000755000542200017500000000132015101701376022436 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t_trace_cat.v" test.compile(make_top_shell=False, make_main=False, v_flags2=["--trace-vcd --no-trace-top --exe", test.pli_filename]) test.execute() test.vcd_identical(test.obj_dir + "/simno_trace_top.vcd", test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_order_multialways.v0000644000542200017500000000254415101701376023353 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [31:0] in_a; reg [31:0] in_b; reg [31:0] e,f,g,h; always @ (/*AS*/in_a) begin e = in_a; f = {e[15:0], e[31:16]}; g = {f[15:0], f[31:16]}; h = {g[15:0], g[31:16]}; end reg [31:0] e2,f2,g2,h2; always @ (/*AS*/f2, g2) begin h2 = {g2[15:0], g2[31:16]}; g2 = {f2[15:0], f2[31:16]}; end always @ (/*AS*/in_a, e2) begin f2 = {e2[15:0], e2[31:16]}; e2 = in_a; end integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; //$write("%d %x %x\n", cyc, h, h2); if (h != h2) $stop; if (cyc==1) begin in_a <= 32'h89a14fab; in_b <= 32'h7ab512fa; end if (cyc==2) begin in_a <= 32'hf4c11a42; in_b <= 32'h359967c6; if (h != 32'h4fab89a1) $stop; end if (cyc==3) begin if (h != 32'h1a42f4c1) $stop; end if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.042/test_regress/t/t_union_soft.py0000755000542200017500000000072615101701376022156 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_sys_fscanf_bad.py0000755000542200017500000000076615101701376022743 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_json_only_flat_vlvbound.v0000644000542200017500000000117015101701376024536 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module vlvbound_test ( input logic [15:0] i_a, input logic [15:0] i_b, output logic [6:0] o_a, output logic [6:0] o_b ); function automatic logic [6:0] foo(input logic [15:0] val); logic [6:0] ret; integer i; for (i=0 ; i < 7; i++) begin ret[i] = (val[i*2 +: 2] == 2'b00); end return ret; endfunction assign o_a = foo(i_a); assign o_b = foo(i_b); endmodule verilator-5.042/test_regress/t/t_flag_errorlimit_bad.v0000644000542200017500000000047115101701376023571 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; int u1; int u1; int u1; int u1; int u1; int u1; int u1; endmodule verilator-5.042/test_regress/t/t_queue_empty_bad.out0000644000542200017500000000107415101701376023314 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_queue_empty_bad.v:11:11: Unsupported/Illegal: empty queue ('{}') in this context : ... note: In instance 't' 11 | i = {} + 1; | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_queue_empty_bad.v:13:9: Unsupported/Illegal: empty queue ('{}') in this assign context : ... note: In instance 't' 13 | i = {}; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_debug_fatalsrc_bad.py0000755000542200017500000000145115101701376023542 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') if 'VERILATOR_TEST_NO_GDB' in os.environ: test.skip("Skipping due to VERILATOR_TEST_NO_GDB") if not test.have_gdb: test.skip("No gdb installed") test.lint(verilator_flags2=["--debug-fatalsrc"], fails='any') test.file_grep(test.compile_log_filename, r'%Error: Internal Error: .*: --debug-fatal-src') test.file_grep(test.compile_log_filename, r'See the manual') test.passes() verilator-5.042/test_regress/t/t_pp_line_bad.v0000644000542200017500000000052415101701376022035 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `line `line 100 `line 200 somefile `line 300 "somefile 1 `line 400 "some file" `line 500 "somefile" 3 `line 600 "some file" 3 verilator-5.042/test_regress/t/t_hier_block.py0000755000542200017500000000321015101701376022063 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') # stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. test.clean_objs() # CI environment offers 2 VCPUs, 2 thread setting causes the following warning. # %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. # So use 6 threads here though it's not optimal in performance, but ok. test.compile( v_flags2=['t/t_hier_block.cpp'], verilator_flags2=[ '--stats', '--hierarchical', '--Wno-TIMESCALEMOD', # '-GPARAM_A=100', '-pvalue+PARAM_B=200', '-DPARAM_OVERRIDE', # '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"' ], threads=(6 if test.vltmt else 1)) test.execute() test.file_grep(test.obj_dir + "/Vsub0/sub0.sv", r'^\s+\/\/\s+timeprecision\s+(\d+)ps;', 1) test.file_grep(test.obj_dir + "/Vsub0/sub0.sv", r'^module\s+(\S+)\s+', "sub0") test.file_grep(test.obj_dir + "/Vsub1/sub1.sv", r'^module\s+(\S+)\s+', "sub1") test.file_grep(test.obj_dir + "/Vsub2/sub2.sv", r'^module\s+(\S+)\s+', "sub2") test.file_grep(test.stats, r'HierBlock,\s+Hierarchical blocks\s+(\d+)', 14) test.file_grep(test.run_log_filename, r'MACRO:(\S+) is defined', "cplusplus") test.passes() verilator-5.042/test_regress/t/t_var_pins_sc_biguint.py0000755000542200017500000000332315101701376024016 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.pli_filename = "t/t_var_pinsizes.cpp" test.top_filename = "t/t_var_pinsizes.v" test.compile(verilator_flags2=["-sc --pins-sc-biguint --trace-vcd --exe", test.pli_filename], make_main=False) def hgrep(re): test.file_grep(os.path.join(test.obj_dir, test.vm_prefix + ".h"), re) hgrep(r'sc_core::sc_in\s+&i1;') hgrep(r'sc_core::sc_in\s+&i8;') hgrep(r'sc_core::sc_in\s+&i16;') hgrep(r'sc_core::sc_in\s+&i32;') hgrep(r'sc_core::sc_in\s+&i64;') hgrep(r'sc_core::sc_in\s>\s+&i65;') hgrep(r'sc_core::sc_in\s>\s+&i128;') hgrep(r'sc_core::sc_in\s>\s+&i513;') hgrep(r'sc_core::sc_in\s>\s+&ibv1;') hgrep(r'sc_core::sc_in\s>\s+&ibv16;') hgrep(r'sc_core::sc_out\s+&o1;') hgrep(r'sc_core::sc_out\s+&o8;') hgrep(r'sc_core::sc_out\s+&o16;') hgrep(r'sc_core::sc_out\s+&o32;') hgrep(r'sc_core::sc_out\s+&o64;') hgrep(r'sc_core::sc_out\s>\s+&o65;') hgrep(r'sc_core::sc_out\s>\s+&o128;') hgrep(r'sc_core::sc_out\s>\s+&o513;') hgrep(r'sc_core::sc_out\s>\s+&obv1;') hgrep(r'sc_core::sc_out\s>\s+&obv16;') test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_virtual_sched_ico.py0000755000542200017500000000103315101701376025471 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(verilator_flags2=["--binary"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dpi_export_noopt.py0000755000542200017500000000131315101701376023360 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # irun -sv top.v t_dpi_export.v -cpost t_dpi_export_c.c -end import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_dpi_export.v" test.compile( v_flags2=["t/t_dpi_export_c.cpp"], verilator_flags2=["-Wall -Wno-DECLFILENAME -no-l2name", ("-O0" if test.vlt_all else "")]) test.execute() test.passes() verilator-5.042/test_regress/t/t_clk_gate_ext.py0000755000542200017500000000073415101701376022423 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_bitsel_struct2.py0000755000542200017500000000073415101701376022742 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_two_dump_sc.out0000644000542200017500000000364315101701376023651 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module topa $end $scope module t $end $var wire 1 # clk $end $var wire 32 $ cyc [31:0] $end $var wire 32 % c_trace_on [31:0] $end $scope module sub $end $var wire 32 & inside_sub_a [31:0] $end $upscope $end $upscope $end $upscope $end $scope module topb $end $scope module t $end $var wire 1 ( clk $end $var wire 32 + cyc [31:0] $end $var wire 32 , c_trace_on [31:0] $end $var real 64 ) r $end $scope module sub $end $var wire 32 - inside_sub_a [31:0] $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 0# b00000000000000000000000000000001 $ b00000000000000000000000000000000 % 0( r0 ) b00000000000000000000000000000001 & b00000000000000000000000000000001 + b00000000000000000000000000000000 , b00000000000000000000000000000010 - #10000 1# b00000000000000000000000000000010 $ b00000000000000000000000000000011 % 1( r0.1 ) #15000 0# 0( #20000 1# b00000000000000000000000000000011 $ b00000000000000000000000000000100 % 1( r0.2 ) #25000 0# 0( #30000 1# b00000000000000000000000000000100 $ b00000000000000000000000000000101 % 1( r0.3 ) #35000 0# 0( #40000 1# b00000000000000000000000000000101 $ b00000000000000000000000000000110 % 1( r0.4 ) #45000 0# 0( #50000 1# b00000000000000000000000000000110 $ b00000000000000000000000000000111 % 1( r0.5 ) #55000 0# 0( #60000 1# b00000000000000000000000000000111 $ b00000000000000000000000000001000 % 1( r0.6 ) #65000 0# 0( #70000 1# b00000000000000000000000000001000 $ b00000000000000000000000000001001 % 1( r0.7 ) #75000 0# 0( #80000 1# b00000000000000000000000000001001 $ b00000000000000000000000000001010 % 1( r0.7999999999999999 ) #85000 0# 0( #90000 1# b00000000000000000000000000001010 $ b00000000000000000000000000001011 % 1( r0.8999999999999999 ) #95000 0# 0( #100000 1# b00000000000000000000000000001011 $ b00000000000000000000000000001100 % 1( r0.9999999999999999 ) verilator-5.042/test_regress/t/t_sampled_expr_unsup.py0000755000542200017500000000106415101701376023704 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert -Wno-UNSIGNED'], fails=True) test.passes() verilator-5.042/test_regress/t/t_assoc_method.py0000755000542200017500000000073415101701376022442 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_tri_pull_unsup.v0000644000542200017500000000131415101701376022663 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; wire u1; wire u2; wire u3; wire u4; wire u5; wire u6; pullup (supply1) pu1(a); pullup (strong1) pu2(a); pullup (pull1) pu3(a); pullup (weak1) pu4(a); pullup (supply1, supply0) pu5(a); pullup (strong0, strong1) pu6(a); wire d1; wire d2; wire d3; wire d4; wire d5; wire d6; pulldown (supply0) pd1(a); pulldown (strong0) pd2(a); pulldown (pull0) pd3(a); pulldown (weak0) pd4(a); pulldown (supply0, supply1) pd5(a); pulldown (strong1, strong0) pd6(a); endmodule verilator-5.042/test_regress/t/t_constraint_method_bad.v0000644000542200017500000000060315101701376024131 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Packet; rand int m_one; constraint cons { m_one > 0 && m_one < 2; } task test1; cons.bad_method(1); // BAD endtask endclass module t; endmodule verilator-5.042/test_regress/t/t_assigndly_task.v0000644000542200017500000000072015101701376022616 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t ( input clk, input [7:0] d, input [2:0] a, output [7:0] q ); always_ff @(posedge clk) tick(a); logic [7:0] d_ = d; logic [7:0] q_; assign q = q_; task automatic tick(logic [2:0] a); q_[a] <= d_[a]; endtask endmodule verilator-5.042/test_regress/t/t_param_shift.v0000644000542200017500000000113015101701376022070 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2016 by Mandy Xu. // SPDX-License-Identifier: CC0-1.0 module t #(parameter[95:0] P = 1) (input clk); localparam [32:0] M = 4; function [M:0] gen_matrix; gen_matrix[0] = 1>> M; endfunction reg [95: 0] lfsr = 0; always @(posedge clk) begin lfsr <= (1 >> P); end wire [95: 0] lfsr_w = 1 >> P; localparam [95: 0] LFSR_P = 1 >> P; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_scheduling_initial_event.v0000644000542200017500000000563015101701376024643 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); module top; logic pEdge = 1'b0; logic nEdge = 1'b1; logic edgeP = 1'b0; logic edgeN = 1'b1; logic changeP = 1'b0; logic changeN = 1'b1; int pEdgeCnt = 0; int nEdgeCnt = 0; int edgePCnt = 0; int edgeNCnt = 0; int changePCnt = 0; int changeNCnt = 0; time pEdgeTime[3] = '{-1, -1, -1}; time nEdgeTime[3] = '{-1, -1, -1}; time edgePTime[3] = '{-1, -1, -1}; time edgeNTime[3] = '{-1, -1, -1}; time changePTime[3] = '{-1, -1, -1}; time changeNTime[3] = '{-1, -1, -1}; initial begin pEdge = 1'b1; nEdge = 1'b0; edgeP = 1'b1; edgeN = 1'b0; changeP = 1'b1; changeN = 1'b0; #10; pEdge = 1'b0; nEdge = 1'b1; edgeP = 1'b0; edgeN = 1'b1; changeP = 1'b0; changeN = 1'b1; #10; pEdge = 1'b1; nEdge = 1'b0; edgeP = 1'b1; edgeN = 1'b0; changeP = 1'b1; changeN = 1'b0; #10; $display("pEdgeCnt: %0d", pEdgeCnt); $display("nEdgeCnt: %0d", nEdgeCnt); $display("edgePCnt: %0d", edgePCnt); $display("edgeNCnt: %0d", edgeNCnt); $display("changePCnt: %0d", changePCnt); $display("changeNCnt: %0d", changeNCnt); $display("pEdgeTime: %p", pEdgeTime); $display("nEdgeTime: %p", nEdgeTime); $display("edgePTime: %p", edgePTime); $display("edgeNTime: %p", edgeNTime); $display("changePTime: %p", changePTime); $display("changeNTime: %p", changeNTime); `checkh(pEdgeCnt, 2); `checkh(nEdgeCnt, 2); `checkh(edgePCnt, 3); `checkh(edgeNCnt, 3); `checkh(changePCnt, 3); `checkh(changeNCnt, 3); `checkh(pEdgeTime[0], 0); `checkh(pEdgeTime[1], 20); `checkh(pEdgeTime[2], -1); `checkh(nEdgeTime[0], 0); `checkh(nEdgeTime[1], 20); `checkh(nEdgeTime[2], -1); `checkh(edgePTime[0], 0); `checkh(edgePTime[1], 10); `checkh(edgePTime[2], 20); `checkh(edgeNTime[0], 0); `checkh(edgeNTime[1], 10); `checkh(edgeNTime[2], 20); `checkh(changePTime[0], 0); `checkh(changePTime[1], 10); `checkh(changePTime[2], 20); `checkh(changeNTime[0], 0); `checkh(changeNTime[1], 10); `checkh(changeNTime[2], 20); $write("*-* All Finished *-*\n"); $finish; end always @(posedge pEdge) pEdgeTime[pEdgeCnt++] = $time; always @(negedge nEdge) nEdgeTime[nEdgeCnt++] = $time; always @(edge edgeP) edgePTime[edgePCnt++] = $time; always @(edge edgeN) edgeNTime[edgeNCnt++] = $time; always @(changeP) changePTime[changePCnt++] = $time; always @(changeN) changeNTime[changeNCnt++] = $time; endmodule // test verilator-5.042/test_regress/t/t_var_local.py0000755000542200017500000000073415101701376021734 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_case_inside.py0000755000542200017500000000073415101701376022240 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_cat_fst.py0000755000542200017500000000137515101701376022575 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(make_top_shell=False, make_main=False, v_flags2=["--trace-fst --exe", test.pli_filename]) test.execute() test.fst_identical(test.obj_dir + "/simpart_0000.fst", "t/" + test.name + "__0000.out") test.fst_identical(test.obj_dir + "/simpart_0100.fst", "t/" + test.name + "__0100.out") test.passes() verilator-5.042/test_regress/t/t_func_wide_out_noinl.py0000755000542200017500000000121315101701376024014 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t_func_wide_out.v" test.compile( verilator_flags2=["-Wno-WIDTHTRUNC"], v_flags2=["+define+T_FUNC_WIDE_OUT_NOINL +define+TEST_NOINLINE t/t_func_wide_out_c.cpp"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_timing_wait3.v0000644000542200017500000000150515101701376022177 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; typedef process pr; pr p[4]; int n = 0; initial begin wait (p[1]); p[1].await(); p[0] = process::self(); if (n == 3) n++; #2 $write("*-* All Finished *-*\n"); $finish; end initial begin wait (p[2]); p[2].await(); p[1] = process::self(); if (n == 2) n++; end initial begin wait (p[3]); p[3].await(); p[2] = process::self(); if (n == 1) n++; end initial begin p[3] = process::self(); if (n == 0) n++; end initial #1 if (n != 4) $stop; initial #3 $stop; // timeout endmodule verilator-5.042/test_regress/t/t_flag_help_valgrind.py0000755000542200017500000000104615101701376023576 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 test.run(fails=False, cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator", "--help", "--valgrind"], tee=False, verilator_run=True) test.passes() verilator-5.042/test_regress/t/t_func_paramed.py0000755000542200017500000000073415101701376022416 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_func_call_super_arg.v0000644000542200017500000000106715101701376023601 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class base; function new(string name); $display(name); if(name == "42") $finish; endfunction function string retstr(); return $sformatf("%0d", $c("42")); endfunction endclass class derived extends base; function new(); super.new(retstr()); endfunction endclass module t; initial begin derived test = new; end endmodule verilator-5.042/test_regress/t/t_dpi_export_context_bad.v0000644000542200017500000000071315101701376024330 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; export "DPI-C" task dpix_task; task dpix_task(); $write("Hello in %m\n"); endtask endmodule verilator-5.042/test_regress/t/t_flag_mmd.v0000644000542200017500000000035215101701376021346 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2016 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; endmodule verilator-5.042/test_regress/t/t_trace_array_saif_portable.py0000755000542200017500000000153115101701376025154 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_trace_array.v" test.golden_filename = "t/t_trace_array_saif.out" # Don't pass --trace-max-width 0, we shrink the file intentionally test.compile(verilator_flags2=[ '--cc --trace-saif --trace-structs --trace-max-width 0', '-CFLAGS -DVL_PORTABLE_ONLY' ]) test.execute() # saif_identical is very slow, so require exact match test.files_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_unpacked_str_init2.out0000644000542200017500000000051015101701376023725 0ustar mahmoudyfreeshellREGX: zero REGX: ra REGX: sp REGX: gp REGX: tp REGX: t0 REGX: t1 REGX: t2 REGX: s0/fp REGX: s1 REGX: a0 REGX: a1 REGX: a2 REGX: a3 REGX: a4 REGX: a5 REGX: a6 REGX: a7 REGX: s2 REGX: s3 REGX: s4 REGX: s5 REGX: s6 REGX: s7 REGX: s8 REGX: s9 REGX: s10 REGX: s11 REGX: t3 REGX: t4 REGX: t5 REGX: t6 OP: ILLEGAL *-* All Finished *-* verilator-5.042/test_regress/t/t_split_var_types.v0000644000542200017500000000262115101701376023030 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; logic [7:0] data = 0; // Test loop always @ (posedge clk) begin if (data != 15) begin data <= data + 8'd1; end else begin $write("*-* All Finished *-*\n"); $finish; end end bug5782 u_bug5782(.data_out()); bug5984 u_bug5984(.in(data)); endmodule // #5782 internal error with --trace-vcd. Bit range is not properly handled. module bug5782 ( output logic [31:0][15:0] data_out ); logic [31:0][15:0] data [8] /*verilator split_var*/; always begin data_out = data[7]; end endmodule // #5984 inconsistent assignment due to wrong bit range calculation. module bug5984 ( input logic [1:0][3:0] in ); logic [1:0][5:2] internal; for (genvar dim1 = 0; dim1 < 2; dim1++) begin for (genvar dim2 = 0; dim2 < 4; dim2++) begin assign internal[dim1][dim2+2] = in[dim1][dim2]; end end for (genvar dim1 = 0; dim1 < 2; dim1++) begin for (genvar dim2 = 0; dim2 < 4; dim2++) begin always_ff @(negedge internal[dim1][dim2+2]) begin $display("%0b", internal[dim1][dim2+2]); end end end endmodule verilator-5.042/test_regress/t/t_wrapper_context.cpp0000644000542200017500000000747115101701376023352 0ustar mahmoudyfreeshell// // DESCRIPTION: Verilator: Verilog Multiple Model Test Module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020-2021 by Andreas Kuster. // SPDX-License-Identifier: CC0-1.0 // #include #include #include #include // These require the above. Comment prevents clang-format moving them #include "TestCheck.h" #include VM_PREFIX_INCLUDE // Check we properly define the version integer #if VERILATOR_VERSION_INTEGER < 4219000 // Added in 4.219 #error "VERILATOR_VERSION_INTEGER not set" #endif double sc_time_stamp() { return 0; } int errors = 0; VerilatedMutex outputMutex; #ifdef T_WRAPPER_CONTEXT #elif defined(T_WRAPPER_CONTEXT_SEQ) VerilatedMutex sequentialMutex; #elif defined(T_WRAPPER_CONTEXT_FST) #else #error "Unexpected test name" #endif void sim(VM_PREFIX* topp) { #ifdef T_WRAPPER_CONTEXT_SEQ // Run each sim sequentially const VerilatedLockGuard seqLock(sequentialMutex); #endif VerilatedContext* contextp = topp->contextp(); // This test created a thread, so need to associate VerilatedContext with it Verilated::threadContextp(contextp); // reset topp->clk = 0; topp->rst = 1; topp->stop = (topp->trace_number == 0); topp->eval(); contextp->timeInc(1); topp->clk = 1; topp->eval(); contextp->timeInc(1); topp->rst = 0; topp->clk = 0; topp->eval(); // simulate until done while (!contextp->gotFinish()) { // increment time contextp->timeInc(1); { const VerilatedLockGuard lock(outputMutex); #ifdef TEST_VERBOSE // std::endl needed to flush output before mutex release std::cout << "{top" << topp->trace_number << ", ctx=" << reinterpret_cast(contextp) << "} [" << contextp->time() << "]" << std::endl; #endif } // toggle clk topp->clk = !topp->clk; // evaluate model topp->eval(); } std::string filename = std::string{VL_STRINGIFY(TEST_OBJ_DIR) "/coverage_"} + topp->name() + ".dat"; contextp->coveragep()->write(filename.c_str()); } int main(int argc, char** argv) { // Create contexts std::unique_ptr context0p{new VerilatedContext}; std::unique_ptr context1p{new VerilatedContext}; // configuration context0p->threads(1); context1p->threads(1); context0p->fatalOnError(false); context1p->fatalOnError(false); context0p->traceEverOn(true); context1p->traceEverOn(true); // error number checks TEST_CHECK_EQ(context0p->errorCount(), 0); TEST_CHECK_EQ(context1p->errorCount(), 0); context0p->errorCount(1); TEST_CHECK_EQ(context0p->errorCount(), 1); context0p->errorCount(0); TEST_CHECK_EQ(context0p->errorCount(), 0); // instantiate verilated design std::unique_ptr top0p{new VM_PREFIX{context0p.get(), "top0"}}; std::unique_ptr top1p{new VM_PREFIX{context1p.get(), "top1"}}; top0p->trace_number = 0; top0p->trace_number = 1; std::cout << "Below '%Error: ... Verilog $stop' is expected as part of the test\n"; // create threads std::thread t0(sim, top0p.get()); std::thread t1(sim, top1p.get()); // wait to finish t0.join(); t1.join(); // check if both finished bool pass = true; if (errors) { std::cout << "Error: comparison errors" << std::endl; pass = false; } else if (top0p->done_o && top1p->done_o) { std::cout << "*-* All Finished *-*" << std::endl; } else { std::cout << "Error: Early termination!" << std::endl; pass = false; } // final model cleanup top0p->final(); top1p->final(); // exit successful return pass ? 0 : 10; } verilator-5.042/test_regress/t/t_flag_deprecated_bad.out0000644000542200017500000000106515101701376024043 0ustar mahmoudyfreeshell%Warning-DEPRECATED: Option --trace-fst-thread is deprecated. Use --trace-fst with --trace-threads > 0. ... For warning description see https://verilator.org/warn/DEPRECATED?v=latest ... Use "/* verilator lint_off DEPRECATED */" and lint_on around source to disable this message. %Warning-DEPRECATED: Option order-clock-delay is deprecated and has no effect. %Warning-DEPRECATED: Option '--clk' is deprecated and has no effect. %Warning-DEPRECATED: Option '--no-clk' is deprecated and has no effect. %Error: Exiting due to verilator-5.042/test_regress/t/t_class_param_extra_bad.py0000755000542200017500000000076615101701376024275 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_flag_main_sc_bad.py0000755000542200017500000000106715101701376023202 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=['--exe --build --main --sc'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_randomize_inline_var_ctl.v0000644000542200017500000000772115101701376024647 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Foo; rand int zero; int two; endclass class Bar extends Foo; rand int one; static int three; function void test; logic[1:0] ok = '0; zero = 100; one = 200; two = 300; three = 400; for (int i = 0; i < 20; i++) begin void'(randomize(one)); if (zero != 100) $stop; if (one != 200) ok[0] = 1; if (two != 300) $stop; if (three != 400) $stop; end if (!ok[0]) $stop; ok = '0; if (zero.rand_mode() != 1) $stop; if (one.rand_mode() != 1) $stop; zero = 500; one = 600; two = 700; three = 800; one.rand_mode(0); for (int i = 0; i < 20; i++) begin void'(randomize(one, two)); if (zero != 500) $stop; if (one != 600) ok[0] = 1; if (two != 700) ok[1] = 1; if (three != 800) $stop; end if (one.rand_mode() != 0) $stop; one.rand_mode(1); if (ok != 'b11) $stop; endfunction endclass class Baz; int four; Bar bar; function new; bar = new; endfunction endclass class Qux; Baz baz; function new; baz = new; endfunction endclass class Boo extends Bar; rand int five; endclass module t; initial begin Boo boo = new; Bar bar = boo; Qux qux = new; logic[2:0] ok = '0; bar.test; bar.zero = 1000; bar.one = 2000; bar.two = 3000; bar.three = 4000; boo.five = 999999; for (int i = 0; i < 20; i++) begin int res = bar.randomize(two); if (boo.five != 999999) $stop; end bar.zero = 1000; bar.one = 2000; bar.two = 3000; bar.three = 4000; boo.five = 999999; for (int i = 0; i < 20; i++) begin int res = bar.randomize(two) with { two > 3000 && two < 4000; }; if (bar.zero != 1000) $stop; if (bar.one != 2000) $stop; if (!(bar.two > 3000 && bar.two < 4000)) $stop; if (bar.three != 4000) $stop; if (boo.five != 999999) $stop; end qux.baz.bar.zero = 5000; qux.baz.bar.one = 6000; qux.baz.bar.two = 7000; qux.baz.bar.three = 8000; qux.baz.four = 9000; for (int i = 0; i < 20; i++) begin void'(qux.randomize(baz)); if (qux.baz.bar.zero != 5000) $stop; if (qux.baz.bar.one != 6000) $stop; if (qux.baz.bar.two != 7000) $stop; if (qux.baz.bar.three != 8000) $stop; if (qux.baz.four != 9000) $stop; end for (int i = 0; i < 20; i++) begin void'(qux.randomize(baz.bar)); if (qux.baz.bar.zero != 5000) ok[0] = 1; if (qux.baz.bar.one != 6000) ok[1] = 1; if (qux.baz.bar.two != 7000) $stop; if (qux.baz.bar.three != 8000) $stop; if (qux.baz.four != 9000) $stop; end if (!ok[0]) $stop; if (!ok[1]) $stop; ok = '0; qux.baz.bar.zero = 10000; qux.baz.bar.one = 20000; for (int i = 0; i < 20; i++) begin void'(qux.randomize(baz.four)); if (qux.baz.bar.zero != 10000) $stop; if (qux.baz.bar.one != 20000) $stop; if (qux.baz.bar.two != 7000) $stop; if (qux.baz.bar.three != 8000) $stop; if (qux.baz.four != 9000) ok[0] = 1; end if (!ok[0]) $stop; ok = '0; qux.baz.four = 30000; for (int i = 0; i < 20; i++) begin void'(qux.randomize(baz.bar, qux.baz.bar.one, baz.four)); if (qux.baz.bar.zero != 10000) ok[0] = 1; if (qux.baz.bar.one != 20000) ok[1] = 1; if (qux.baz.bar.two != 7000) $stop; if (qux.baz.bar.three != 8000) $stop; if (qux.baz.four != 30000) ok[2] = 1; end if (ok != 'b111) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_preproc_def09.v0000644000542200017500000000355115101701376022245 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `undefineall // Definitions as speced // Note there are trailing spaces, which spec doesn't show properly `define D(x,y) initial $display("start", x , y, "end"); '`D( "msg1" , "msg2" )' 'initial $display("start", "msg1" , "msg2" , "end");' '`D( " msg1", )' 'initial $display("start", " msg1" , , "end");' '`D(, "msg2 ")' 'initial $display("start", , "msg2 ", "end");' '`D(,)' 'initial $display("start", , , "end");' '`D( , )' 'initial $display("start", , , "end");' //`D("msg1") // ILLEGAL: only one argument //`D() // ILLEGAL: only one empty argument //`D(,,) // ILLEGAL: more actual than formal arguments // Defaults: `define MACRO1(a=5,b="B",c) $display(a,,b,,c); '`MACRO1 ( , 2, 3 )' '$display(5,,2,,3);' '`MACRO1 ( 1 , , 3 )' '$display(1 ,,"B",,3 );' '`MACRO1 ( , 2, )' '$display(5,,2,,);' //`MACRO1 ( 1 ) // ILLEGAL: b and c omitted, no default for c `define MACRO2(a=5, b, c="C") $display(a,,b,,c); '`MACRO2 (1, , 3)' '$display(5,,,,"C");' '`MACRO2 (, 2, )' '$display(5,,2,,"C");' '`MACRO2 (, 2)' '$display(5,,2,,"C");' `define MACRO3(a=5, b=0, c="C") $display(a,,b,,c); '`MACRO3 ( 1 )' '$display(1 ,,0,,"C");' '`MACRO3 ( )' '$display(5,,0,,"C");' //`MACRO3 // ILLEGAL: parentheses required `define DTOP(a,b) a + b '`DTOP( `DTOP(b,1), `DTOP(42,a) )' 'b + 1 + 42 + a' // Local tests `define MACROQUOTE(a="==)",b="((((",c=() ) 'a b c' `MACROQUOTE(); '"==)" "((((" () '; // Also check our line counting doesn't go bad `define MACROPAREN(a=(6), b=(eq=al), c) 'a b c' `MACROPAREN( ,, ZOT) HERE-`__LINE__ - Line71 //====================================================================== verilator-5.042/test_regress/t/t_a7_hier_block_cmake.py0000755000542200017500000000352115101701376023617 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap import os # If a test fails, broken .cmake may disturb the next run test.clean_objs() test.scenarios('simulator') test.top_filename = "t/t_hier_block.v" threads = ('-DTEST_THREADS=6' if test.vltmt else '-DTEST_THREADS=1') if not test.have_cmake: test.skip("Test requires CMake; ignore error since not available or version too old") test.run(logfile=test.obj_dir + "/cmake.log", cmd=[ 'cd "' + test.obj_dir + '" && cmake ' + test.t_dir + '/t_hier_block_cmake', "-DCMAKE_PREFIX_PATH=" + os.environ["VERILATOR_ROOT"], threads ]) test.run(logfile=test.obj_dir + "/build.log", cmd=[ 'cd "' + test.obj_dir + '" && cmake --build', '.', ('-v' if test.verbose else ''), '-j ' + str(test.max_procs), '--', "CXX_FLAGS=" + str(threads) ]) test.run(logfile=test.obj_dir + "/run.log", cmd=['cd "' + test.obj_dir + '" && ./t_hier_block_cmake', '.']) target_dir = test.obj_dir + '/CMakeFiles/t_hier_block_cmake.dir/Vt_hier_block.dir/' test.file_grep(target_dir + 'Vsub0/sub0.sv', r'^module\s+(\S+)\s+', "sub0") test.file_grep(target_dir + 'Vsub1/sub1.sv', r'^module\s+(\S+)\s+', "sub1") test.file_grep(target_dir + 'Vsub2/sub2.sv', r'^module\s+(\S+)\s+', "sub2") test.file_grep(target_dir + 'Vt_hier_block__stats.txt', r'HierBlock,\s+Hierarchical blocks\s+(\d+)', 14) test.file_grep(test.obj_dir + '/run.log', r'MACRO:(\S+) is defined', "cplusplus") test.passes() verilator-5.042/test_regress/t/t_fuzz_eof_bad.v0000644000542200017500000000006615101701376022237 0ustar mahmoudyfreeshellmodule a; initial $lay(*Hello!=n"); endmodule verilator-5.042/test_regress/t/t_process_bad.out0000644000542200017500000000105415101701376022426 0ustar mahmoudyfreeshell%Error: t/t_process_bad.v:13:13: Class method 'bad_method' not found in class 'process' : ... note: In instance 't' 13 | if (p.bad_method() != 0) $stop; | ^~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_process_bad.v:15:9: Class method 'bad_method_2' not found in class 'process' : ... note: In instance 't' 15 | p.bad_method_2(); | ^~~~~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_math_mul.py0000755000542200017500000000073415101701376021600 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_var_dotted2.v0000644000542200017500000000633415101701376022023 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `ifdef USE_INLINE `define INLINE_MODULE /*verilator inline_module*/ `else `define INLINE_MODULE /*verilator public_module*/ `endif module t; `define DRAM1(bank) mem.mem_bank[bank].dccm.dccm_bank.ram_core `define DRAM2(bank) mem.mem_bank2[bank].dccm.dccm_bank.ram_core `define DRAM3(bank) mem.mem_bank3[bank].dccm.dccm_bank.ram_core `define DRAM4(bank) mem.sub4.mem_bank4[bank].dccm.dccm_bank.ram_core initial begin `DRAM1(0)[3] = 130; `DRAM1(1)[3] = 131; `DRAM2(0)[3] = 230; `DRAM2(1)[3] = 231; `DRAM3(0)[3] = 330; `DRAM3(1)[3] = 331; `DRAM4(0)[3] = 430; `DRAM4(1)[3] = 431; if (`DRAM1(0)[3] !== 130) $stop; if (`DRAM1(1)[3] !== 131) $stop; if (`DRAM2(0)[3] !== 230) $stop; if (`DRAM2(1)[3] !== 231) $stop; if (`DRAM3(0)[3] !== 330) $stop; if (`DRAM3(1)[3] !== 331) $stop; if (`DRAM4(0)[3] !== 430) $stop; if (`DRAM4(1)[3] !== 431) $stop; $write("*-* All Finished *-*\n"); $finish; end eh2_lsu_dccm_mem mem (/*AUTOINST*/); endmodule module eh2_lsu_dccm_mem #( DCCM_INDEX_DEPTH = 8192, DCCM_NUM_BANKS = 2 )( ); `INLINE_MODULE // 8 Banks, 16KB each (2048 x 72) for (genvar i=0; i= SIZE) begin $stop; end end end end endgenerate generate for (g = 0; g < `MAX_SIZE; g = g + 1) begin if (!((g >= SIZE) || ~MASK[g])) begin always @(posedge clk) begin `ifdef TEST_VERBOSE $write ("Logical OR generate if MASK [%1d] = %d\n", g, MASK[g]); `endif if (g >= SIZE) begin $stop; end end end end endgenerate generate for (g = 0; g < `MAX_SIZE; g = g + 1) begin if (!((g < SIZE) -> ~MASK[g])) begin always @(posedge clk) begin `ifdef TEST_VERBOSE $write ("Logical infer generate if MASK [%1d] = %d\n", g, MASK[g]); `endif if (g >= SIZE) begin $stop; end end end end endgenerate generate for (g = 0; g < `MAX_SIZE; g = g + 1) begin if ( g < SIZE ? MASK[g] : 1'b0) begin always @(posedge clk) begin `ifdef TEST_VERBOSE $write ("Conditional generate if MASK [%1d] = %d\n", g, MASK[g]); `endif if (g >= SIZE) begin $stop; end end end end endgenerate // The other way round generate for (g = 0; g < `MAX_SIZE; g = g + 1) begin if ( g >= SIZE ? 1'b0 : MASK[g]) begin always @(posedge clk) begin `ifdef TEST_VERBOSE $write ("Conditional generate if MASK [%1d] = %d\n", g, MASK[g]); `endif if (g >= SIZE) begin $stop; end end end end endgenerate endmodule verilator-5.042/test_regress/t/t_clocking_bad5.v0000644000542200017500000000122015101701376022257 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; sub sub(.*); // Bad - no global clock always @ ($global_clock) $display; endmodule module sub(/*AUTOARG*/ // Inputs clk ); input clk; global clocking ck @(posedge clk); endclocking // Bad - global duplicate global clocking ogck @(posedge clk); endclocking // Bad - name duplicate global clocking ck @(posedge clk); endclocking endmodule verilator-5.042/test_regress/t/t_func_void.py0000755000542200017500000000073415101701376021746 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_forceable_net_trace.vcd.out0000644000542200017500000000450415101701376024666 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $var wire 1 # clk $end $var wire 1 $ rst $end $var wire 32 % cyc [31:0] $end $scope module t $end $var wire 1 # clk $end $var wire 1 $ rst $end $var wire 32 % cyc [31:0] $end $var wire 1 & net_1 $end $var wire 8 ' net_8 [7:0] $end $var wire 1 & obs_1 $end $var wire 8 ' obs_8 [7:0] $end $upscope $end $upscope $end $enddefinitions $end #0 0# 1$ b00000000000000000000000000000000 % 1& b11111111 ' #5 1# 0$ #10 0# #15 1# b00000000000000000000000000000001 % 0& #20 0# #25 1# b00000000000000000000000000000010 % 1& b11111110 ' #30 0# #35 1# b00000000000000000000000000000011 % 0& #40 0# #45 1# b00000000000000000000000000000100 % b01011111 ' #50 0# #55 1# b00000000000000000000000000000101 % 1& #60 0# #65 1# b00000000000000000000000000000110 % b11110101 ' #70 0# #75 1# b00000000000000000000000000000111 % #80 0# #85 1# b00000000000000000000000000001000 % #90 0# #95 1# b00000000000000000000000000001001 % 0& b11111011 ' #100 0# #105 1# b00000000000000000000000000001010 % 1& b01011010 ' #110 0# #115 1# b00000000000000000000000000001011 % #120 0# #125 1# b00000000000000000000000000001100 % 0& b10100101 ' #130 0# #135 1# b00000000000000000000000000001101 % #140 0# #145 1# b00000000000000000000000000001110 % 1& b11111000 ' #150 0# #155 1# b00000000000000000000000000001111 % 0& #160 0# #165 1# b00000000000000000000000000010000 % 1& b11110111 ' #170 0# #175 1# b00000000000000000000000000010001 % 0& #180 0# #185 1# b00000000000000000000000000010010 % 1& b11110110 ' #190 0# #195 1# b00000000000000000000000000010011 % 0& #200 0# #205 1# b00000000000000000000000000010100 % 1& b11110101 ' #210 0# #215 1# b00000000000000000000000000010101 % 0& #220 0# #225 1# b00000000000000000000000000010110 % 1& b11110100 ' #230 0# #235 1# b00000000000000000000000000010111 % 0& #240 0# #245 1# b00000000000000000000000000011000 % 1& b11110011 ' #250 0# #255 1# b00000000000000000000000000011001 % 0& #260 0# #265 1# b00000000000000000000000000011010 % 1& b11110010 ' #270 0# #275 1# b00000000000000000000000000011011 % 0& #280 0# #285 1# b00000000000000000000000000011100 % 1& b11110001 ' #290 0# #295 1# b00000000000000000000000000011101 % 0& #300 0# #305 1# b00000000000000000000000000011110 % 1& b11110000 ' #310 0# #315 1# b00000000000000000000000000011111 % 0& verilator-5.042/test_regress/t/t_fork_dynscope_interface.py0000755000542200017500000000100515101701376024647 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--binary --trace-fst']) test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_primitive_fst_sc.py0000755000542200017500000000114115101701376024512 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_primitive.v" if not test.have_sc: test.skip("No SystemC installed") test.compile(v_flags2=["--sc --trace-fst"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_down_inlab.py0000755000542200017500000000112215101701376024116 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_down.v" test.compile(v_flags2=['+define+INLINE_A +define+INLINE_B'], verilator_flags2=['-trace']) test.execute() test.passes() verilator-5.042/test_regress/t/t_package_export_bad2.v0000644000542200017500000000054315101701376023466 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package Pkg1; endpackage package Pkg10; // verilator lint_off PKGNODECL export Pkg1b::*; // BAD - typo in package name endpackage module t; endmodule verilator-5.042/test_regress/t/t_delay_incr_timing.py0000755000542200017500000000105515101701376023447 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_delay_incr.v" test.compile(verilator_flags2=['--binary -Wno-ZERODLY']) test.execute() test.passes() verilator-5.042/test_regress/t/t_dfg_bin_to_one_hot.py0000755000542200017500000000115015101701376023570 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["--stats"]) test.execute() test.file_grep(test.stats, r'Optimizations, DFG pre inline BinToOneHot, decoders created\s+(\d+)', 3) test.passes() verilator-5.042/test_regress/t/t_timing_split.py0000755000542200017500000000176515101701376022501 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') def check_splits(): got1 = False gotSyms1 = False for filename in test.glob_some(test.obj_dir + "/*.cpp"): if re.search(r'Syms__1', filename): gotSyms1 = True elif re.search(r'__1', filename): got1 = True if not got1: test.error("No __1 split file found") if not gotSyms1: test.error("No Syms__1 split file found") test.compile(timing_loop=True, verilator_flags2=["--timing --output-split-cfuncs 1 -CFLAGS -Werror"]) test.execute() if test.have_coroutines: check_splits() test.passes() verilator-5.042/test_regress/t/t_var_pins_sc_uint_bool.py0000755000542200017500000000300515101701376024344 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.pli_filename = "t/t_var_pinsizes.cpp" test.top_filename = "t/t_var_pinsizes.v" test.compile(verilator_flags2=["-sc --pins-sc-uint-bool --trace-vcd --exe", test.pli_filename], make_main=False) def hgrep(re): test.file_grep(os.path.join(test.obj_dir, test.vm_prefix + ".h"), re) hgrep(r'sc_core::sc_in\s>\s+&i1;') hgrep(r'sc_core::sc_in\s+&i8;') hgrep(r'sc_core::sc_in\s+&i16;') hgrep(r'sc_core::sc_in\s+&i32;') hgrep(r'sc_core::sc_in\s+&i64;') hgrep(r'sc_core::sc_in\s>\s+&i65;') hgrep(r'sc_core::sc_in\s>\s+&i128;') hgrep(r'sc_core::sc_in\s>\s+&i513;') hgrep(r'sc_core::sc_out\s>\s+&o1;') hgrep(r'sc_core::sc_out\s+&o8;') hgrep(r'sc_core::sc_out\s+&o16;') hgrep(r'sc_core::sc_out\s+&o32;') hgrep(r'sc_core::sc_out\s+&o64;') hgrep(r'sc_core::sc_out\s>\s+&o65;') hgrep(r'sc_core::sc_out\s>\s+&o128;') hgrep(r'sc_core::sc_out\s>\s+&o513;') test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_dumpvars_dyn_fst_0.out0000644000542200017500000001236115101701376025131 0ustar mahmoudyfreeshell$date Sat Jul 19 22:57:16 2025 $end $version fstWriter $end $timescale 1ps $end $scope module top $end $var wire 1 ! clk $end $scope module t $end $var wire 1 ! clk $end $var int 32 " cyc [31:0] $end $scope module sub1a $end $var parameter 32 # ADD [31:0] $end $var wire 32 " cyc [31:0] $end $var int 32 $ value [31:0] $end $scope module sub2a $end $var parameter 32 % ADD [31:0] $end $var wire 32 " cyc [31:0] $end $var int 32 & value [31:0] $end $upscope $end $scope module sub2b $end $var parameter 32 ' ADD [31:0] $end $var wire 32 " cyc [31:0] $end $var int 32 ( value [31:0] $end $upscope $end $scope module sub2c $end $var parameter 32 ) ADD [31:0] $end $var wire 32 " cyc [31:0] $end $var int 32 * value [31:0] $end $upscope $end $upscope $end $scope module sub1b $end $var parameter 32 + ADD [31:0] $end $var wire 32 " cyc [31:0] $end $var int 32 , value [31:0] $end $scope module sub2a $end $var parameter 32 - ADD [31:0] $end $var wire 32 " cyc [31:0] $end $var int 32 . value [31:0] $end $upscope $end $scope module sub2b $end $var parameter 32 / ADD [31:0] $end $var wire 32 " cyc [31:0] $end $var int 32 0 value [31:0] $end $upscope $end $scope module sub2c $end $var parameter 32 1 ADD [31:0] $end $var wire 32 " cyc [31:0] $end $var int 32 2 value [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b00000000000000000000000000010111 2 b00000000000000000000000000010111 1 b00000000000000000000000000010110 0 b00000000000000000000000000010110 / b00000000000000000000000000010101 . b00000000000000000000000000010101 - b00000000000000000000000000010100 , b00000000000000000000000000010100 + b00000000000000000000000000001101 * b00000000000000000000000000001101 ) b00000000000000000000000000001100 ( b00000000000000000000000000001100 ' b00000000000000000000000000001011 & b00000000000000000000000000001011 % b00000000000000000000000000001010 $ b00000000000000000000000000001010 # b00000000000000000000000000000000 " 0! $end #1 1! b00000000000000000000000000000001 " b00000000000000000000000000001011 $ b00000000000000000000000000001100 & b00000000000000000000000000001101 ( b00000000000000000000000000001110 * b00000000000000000000000000010101 , b00000000000000000000000000010110 . b00000000000000000000000000010111 0 b00000000000000000000000000011000 2 #2 0! #3 1! b00000000000000000000000000011001 2 b00000000000000000000000000011000 0 b00000000000000000000000000010111 . b00000000000000000000000000010110 , b00000000000000000000000000001111 * b00000000000000000000000000001110 ( b00000000000000000000000000001101 & b00000000000000000000000000001100 $ b00000000000000000000000000000010 " #4 0! #5 1! b00000000000000000000000000000011 " b00000000000000000000000000001101 $ b00000000000000000000000000001110 & b00000000000000000000000000001111 ( b00000000000000000000000000010000 * b00000000000000000000000000010111 , b00000000000000000000000000011000 . b00000000000000000000000000011001 0 b00000000000000000000000000011010 2 #6 0! #7 1! b00000000000000000000000000011011 2 b00000000000000000000000000011010 0 b00000000000000000000000000011001 . b00000000000000000000000000011000 , b00000000000000000000000000010001 * b00000000000000000000000000010000 ( b00000000000000000000000000001111 & b00000000000000000000000000001110 $ b00000000000000000000000000000100 " #8 0! #9 1! b00000000000000000000000000000101 " b00000000000000000000000000001111 $ b00000000000000000000000000010000 & b00000000000000000000000000010001 ( b00000000000000000000000000010010 * b00000000000000000000000000011001 , b00000000000000000000000000011010 . b00000000000000000000000000011011 0 b00000000000000000000000000011100 2 #10 0! #11 1! b00000000000000000000000000011101 2 b00000000000000000000000000011100 0 b00000000000000000000000000011011 . b00000000000000000000000000011010 , b00000000000000000000000000010011 * b00000000000000000000000000010010 ( b00000000000000000000000000010001 & b00000000000000000000000000010000 $ b00000000000000000000000000000110 " #12 0! #13 1! b00000000000000000000000000000111 " b00000000000000000000000000010001 $ b00000000000000000000000000010010 & b00000000000000000000000000010011 ( b00000000000000000000000000010100 * b00000000000000000000000000011011 , b00000000000000000000000000011100 . b00000000000000000000000000011101 0 b00000000000000000000000000011110 2 #14 0! #15 1! b00000000000000000000000000011111 2 b00000000000000000000000000011110 0 b00000000000000000000000000011101 . b00000000000000000000000000011100 , b00000000000000000000000000010101 * b00000000000000000000000000010100 ( b00000000000000000000000000010011 & b00000000000000000000000000010010 $ b00000000000000000000000000001000 " #16 0! #17 1! b00000000000000000000000000001001 " b00000000000000000000000000010011 $ b00000000000000000000000000010100 & b00000000000000000000000000010101 ( b00000000000000000000000000010110 * b00000000000000000000000000011101 , b00000000000000000000000000011110 . b00000000000000000000000000011111 0 b00000000000000000000000000100000 2 #18 0! #19 1! b00000000000000000000000000100001 2 b00000000000000000000000000100000 0 b00000000000000000000000000011111 . b00000000000000000000000000011110 , b00000000000000000000000000010111 * b00000000000000000000000000010110 ( b00000000000000000000000000010101 & b00000000000000000000000000010100 $ b00000000000000000000000000001010 " #20 0! verilator-5.042/test_regress/t/t_gantt_two.cpp0000644000542200017500000000227715101701376022133 0ustar mahmoudyfreeshell// // DESCRIPTION: Verilator: Verilog Multiple Model Test Module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 // #include "verilated.h" #include VM_PREFIX_INCLUDE #include int main(int argc, char** argv) { srand48(5); const std::unique_ptr contextp{new VerilatedContext}; // VL_USE_THREADS define is set in t_gantt_two.py contextp->threads(TEST_USE_THREADS); contextp->debug(0); contextp->commandArgs(argc, argv); std::unique_ptr topap{new VM_PREFIX{contextp.get(), "topa"}}; std::unique_ptr topbp{new VM_PREFIX{contextp.get(), "topb"}}; topap->clk = false; topap->eval(); topbp->clk = false; topbp->eval(); contextp->timeInc(10); while ((contextp->time() < 1100) && !contextp->gotFinish()) { topap->clk = !topap->clk; topap->eval(); topbp->clk = !topbp->clk; topbp->eval(); contextp->timeInc(5); } if (!contextp->gotFinish()) { vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); } return 0; } verilator-5.042/test_regress/t/t_case_deep.v0000644000542200017500000004777115101701376021530 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [33:0] in = crc[33:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [31:0] code; // From test of Test.v wire [4:0] len; // From test of Test.v wire next; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .next (next), .code (code[31:0]), .len (len[4:0]), // Inputs .clk (clk), .in (in[33:0])); // Aggregate outputs into a single result vector wire [63:0] result = {26'h0, next, len, code}; // What checksum will we end up with `define EXPECTED_SUM 64'h5537fa30d49bf865 // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs next, code, len, // Inputs clk, in ); input clk; input [33:0] in; output next; output [31:0] code; output [4:0] len; /*AUTOREG*/ // Beginning of automatic regs (for this module's undeclared outputs) reg [31:0] code; reg [4:0] len; reg next; // End of automatics /* #!/usr/bin/env perl use warnings; srand(5); my @used; pat: for (my $pat=0; 1; ) { last if $pat > 196; my $len = int($pat / (6 + $pat/50)) + 4; $len=20 if $len>20; my ($try, $val, $mask); try: for ($try=0; ; $try++) { next pat if $try>50; $val = 0; for (my $bit=23; $bit>(23-$len); $bit--) { my $b = int(rand()*2); $val |= (1<<$bit) if $b; } $mask = (1<<(23-$len+1))-1; for (my $testval = $val; $testval <= ($val + $mask); $testval ++) { next try if $used[$testval]; } last; } my $bits = ""; my $val2 = 0; for (my $bit=23; $bit>(23-$len); $bit--) { my $b = ($val & (1<<$bit)); $bits .= $b?'1':'0'; } for (my $testval = $val; $testval <= ($val + $mask); $testval++) { $used[$testval]= 1; #printf "U%08x\n", $testval; } if ($try<90) { printf +(" 24'b%s: {next, len, code} = {in[%02d], 5'd%02d, 32'd%03d};\n" ,$bits.("?"x(24-$len)), 31-$len, $len, $pat); $pat++; } } */ always @* begin next = 1'b0; code = 32'd0; len = 5'b11111; casez (in[31:8]) 24'b1010????????????????????: {next, len, code} = {in[27], 5'd04, 32'd000}; 24'b1100????????????????????: {next, len, code} = {in[27], 5'd04, 32'd001}; 24'b0110????????????????????: {next, len, code} = {in[27], 5'd04, 32'd002}; 24'b1001????????????????????: {next, len, code} = {in[27], 5'd04, 32'd003}; 24'b1101????????????????????: {next, len, code} = {in[27], 5'd04, 32'd004}; 24'b0011????????????????????: {next, len, code} = {in[27], 5'd04, 32'd005}; 24'b0001????????????????????: {next, len, code} = {in[27], 5'd04, 32'd006}; 24'b10001???????????????????: {next, len, code} = {in[26], 5'd05, 32'd007}; 24'b01110???????????????????: {next, len, code} = {in[26], 5'd05, 32'd008}; 24'b01000???????????????????: {next, len, code} = {in[26], 5'd05, 32'd009}; 24'b00001???????????????????: {next, len, code} = {in[26], 5'd05, 32'd010}; 24'b11100???????????????????: {next, len, code} = {in[26], 5'd05, 32'd011}; 24'b01011???????????????????: {next, len, code} = {in[26], 5'd05, 32'd012}; 24'b100001??????????????????: {next, len, code} = {in[25], 5'd06, 32'd013}; 24'b111110??????????????????: {next, len, code} = {in[25], 5'd06, 32'd014}; 24'b010010??????????????????: {next, len, code} = {in[25], 5'd06, 32'd015}; 24'b001011??????????????????: {next, len, code} = {in[25], 5'd06, 32'd016}; 24'b101110??????????????????: {next, len, code} = {in[25], 5'd06, 32'd017}; 24'b111011??????????????????: {next, len, code} = {in[25], 5'd06, 32'd018}; 24'b0111101?????????????????: {next, len, code} = {in[24], 5'd07, 32'd020}; 24'b0010100?????????????????: {next, len, code} = {in[24], 5'd07, 32'd021}; 24'b0111111?????????????????: {next, len, code} = {in[24], 5'd07, 32'd022}; 24'b1011010?????????????????: {next, len, code} = {in[24], 5'd07, 32'd023}; 24'b1000000?????????????????: {next, len, code} = {in[24], 5'd07, 32'd024}; 24'b1011111?????????????????: {next, len, code} = {in[24], 5'd07, 32'd025}; 24'b1110100?????????????????: {next, len, code} = {in[24], 5'd07, 32'd026}; 24'b01111100????????????????: {next, len, code} = {in[23], 5'd08, 32'd027}; 24'b00000110????????????????: {next, len, code} = {in[23], 5'd08, 32'd028}; 24'b00000101????????????????: {next, len, code} = {in[23], 5'd08, 32'd029}; 24'b01001100????????????????: {next, len, code} = {in[23], 5'd08, 32'd030}; 24'b10110110????????????????: {next, len, code} = {in[23], 5'd08, 32'd031}; 24'b00100110????????????????: {next, len, code} = {in[23], 5'd08, 32'd032}; 24'b11110010????????????????: {next, len, code} = {in[23], 5'd08, 32'd033}; 24'b010011101???????????????: {next, len, code} = {in[22], 5'd09, 32'd034}; 24'b001000000???????????????: {next, len, code} = {in[22], 5'd09, 32'd035}; 24'b010101111???????????????: {next, len, code} = {in[22], 5'd09, 32'd036}; 24'b010101010???????????????: {next, len, code} = {in[22], 5'd09, 32'd037}; 24'b010011011???????????????: {next, len, code} = {in[22], 5'd09, 32'd038}; 24'b010100011???????????????: {next, len, code} = {in[22], 5'd09, 32'd039}; 24'b010101000???????????????: {next, len, code} = {in[22], 5'd09, 32'd040}; 24'b1111010101??????????????: {next, len, code} = {in[21], 5'd10, 32'd041}; 24'b0010001000??????????????: {next, len, code} = {in[21], 5'd10, 32'd042}; 24'b0101001101??????????????: {next, len, code} = {in[21], 5'd10, 32'd043}; 24'b0010010100??????????????: {next, len, code} = {in[21], 5'd10, 32'd044}; 24'b1011001110??????????????: {next, len, code} = {in[21], 5'd10, 32'd045}; 24'b1111000011??????????????: {next, len, code} = {in[21], 5'd10, 32'd046}; 24'b0101000000??????????????: {next, len, code} = {in[21], 5'd10, 32'd047}; 24'b1111110000??????????????: {next, len, code} = {in[21], 5'd10, 32'd048}; 24'b10110111010?????????????: {next, len, code} = {in[20], 5'd11, 32'd049}; 24'b11110000011?????????????: {next, len, code} = {in[20], 5'd11, 32'd050}; 24'b01001111011?????????????: {next, len, code} = {in[20], 5'd11, 32'd051}; 24'b00101011011?????????????: {next, len, code} = {in[20], 5'd11, 32'd052}; 24'b01010010100?????????????: {next, len, code} = {in[20], 5'd11, 32'd053}; 24'b11110111100?????????????: {next, len, code} = {in[20], 5'd11, 32'd054}; 24'b00100111001?????????????: {next, len, code} = {in[20], 5'd11, 32'd055}; 24'b10110001010?????????????: {next, len, code} = {in[20], 5'd11, 32'd056}; 24'b10000010000?????????????: {next, len, code} = {in[20], 5'd11, 32'd057}; 24'b111111101100????????????: {next, len, code} = {in[19], 5'd12, 32'd058}; 24'b100000111110????????????: {next, len, code} = {in[19], 5'd12, 32'd059}; 24'b100000110010????????????: {next, len, code} = {in[19], 5'd12, 32'd060}; 24'b100000111001????????????: {next, len, code} = {in[19], 5'd12, 32'd061}; 24'b010100101111????????????: {next, len, code} = {in[19], 5'd12, 32'd062}; 24'b001000001100????????????: {next, len, code} = {in[19], 5'd12, 32'd063}; 24'b000001111111????????????: {next, len, code} = {in[19], 5'd12, 32'd064}; 24'b011111010100????????????: {next, len, code} = {in[19], 5'd12, 32'd065}; 24'b1110101111101???????????: {next, len, code} = {in[18], 5'd13, 32'd066}; 24'b0100110101110???????????: {next, len, code} = {in[18], 5'd13, 32'd067}; 24'b1111111011011???????????: {next, len, code} = {in[18], 5'd13, 32'd068}; 24'b0101011011001???????????: {next, len, code} = {in[18], 5'd13, 32'd069}; 24'b0010000101100???????????: {next, len, code} = {in[18], 5'd13, 32'd070}; 24'b1111111101101???????????: {next, len, code} = {in[18], 5'd13, 32'd071}; 24'b1011110010110???????????: {next, len, code} = {in[18], 5'd13, 32'd072}; 24'b0101010111010???????????: {next, len, code} = {in[18], 5'd13, 32'd073}; 24'b1111011010010???????????: {next, len, code} = {in[18], 5'd13, 32'd074}; 24'b01010100100011??????????: {next, len, code} = {in[17], 5'd14, 32'd075}; 24'b10110000110010??????????: {next, len, code} = {in[17], 5'd14, 32'd076}; 24'b10111101001111??????????: {next, len, code} = {in[17], 5'd14, 32'd077}; 24'b10110000010101??????????: {next, len, code} = {in[17], 5'd14, 32'd078}; 24'b00101011001111??????????: {next, len, code} = {in[17], 5'd14, 32'd079}; 24'b00100000101100??????????: {next, len, code} = {in[17], 5'd14, 32'd080}; 24'b11111110010111??????????: {next, len, code} = {in[17], 5'd14, 32'd081}; 24'b10110010100000??????????: {next, len, code} = {in[17], 5'd14, 32'd082}; 24'b11101011101000??????????: {next, len, code} = {in[17], 5'd14, 32'd083}; 24'b01010000011111??????????: {next, len, code} = {in[17], 5'd14, 32'd084}; 24'b101111011001011?????????: {next, len, code} = {in[16], 5'd15, 32'd085}; 24'b101111010001100?????????: {next, len, code} = {in[16], 5'd15, 32'd086}; 24'b100000111100111?????????: {next, len, code} = {in[16], 5'd15, 32'd087}; 24'b001010101011000?????????: {next, len, code} = {in[16], 5'd15, 32'd088}; 24'b111111100100001?????????: {next, len, code} = {in[16], 5'd15, 32'd089}; 24'b001001011000010?????????: {next, len, code} = {in[16], 5'd15, 32'd090}; 24'b011110011001011?????????: {next, len, code} = {in[16], 5'd15, 32'd091}; 24'b111111111111010?????????: {next, len, code} = {in[16], 5'd15, 32'd092}; 24'b101111001010011?????????: {next, len, code} = {in[16], 5'd15, 32'd093}; 24'b100000110000111?????????: {next, len, code} = {in[16], 5'd15, 32'd094}; 24'b0010010000000101????????: {next, len, code} = {in[15], 5'd16, 32'd095}; 24'b0010010010101001????????: {next, len, code} = {in[15], 5'd16, 32'd096}; 24'b1111011010110010????????: {next, len, code} = {in[15], 5'd16, 32'd097}; 24'b0010010001100100????????: {next, len, code} = {in[15], 5'd16, 32'd098}; 24'b0101011101110100????????: {next, len, code} = {in[15], 5'd16, 32'd099}; 24'b0101011010001111????????: {next, len, code} = {in[15], 5'd16, 32'd100}; 24'b0010000110011111????????: {next, len, code} = {in[15], 5'd16, 32'd101}; 24'b0101010010000101????????: {next, len, code} = {in[15], 5'd16, 32'd102}; 24'b1110101011000000????????: {next, len, code} = {in[15], 5'd16, 32'd103}; 24'b1111000000110010????????: {next, len, code} = {in[15], 5'd16, 32'd104}; 24'b0111100010001101????????: {next, len, code} = {in[15], 5'd16, 32'd105}; 24'b00100010110001100???????: {next, len, code} = {in[14], 5'd17, 32'd106}; 24'b00100010101101010???????: {next, len, code} = {in[14], 5'd17, 32'd107}; 24'b11111110111100000???????: {next, len, code} = {in[14], 5'd17, 32'd108}; 24'b00100000111010000???????: {next, len, code} = {in[14], 5'd17, 32'd109}; 24'b00100111011101001???????: {next, len, code} = {in[14], 5'd17, 32'd110}; 24'b11111110111000011???????: {next, len, code} = {in[14], 5'd17, 32'd111}; 24'b11110001101000100???????: {next, len, code} = {in[14], 5'd17, 32'd112}; 24'b11101011101011101???????: {next, len, code} = {in[14], 5'd17, 32'd113}; 24'b01010000100101011???????: {next, len, code} = {in[14], 5'd17, 32'd114}; 24'b00100100110011001???????: {next, len, code} = {in[14], 5'd17, 32'd115}; 24'b01001110010101000???????: {next, len, code} = {in[14], 5'd17, 32'd116}; 24'b010011110101001000??????: {next, len, code} = {in[13], 5'd18, 32'd117}; 24'b111010101110010010??????: {next, len, code} = {in[13], 5'd18, 32'd118}; 24'b001001001001111000??????: {next, len, code} = {in[13], 5'd18, 32'd119}; 24'b101111000110111101??????: {next, len, code} = {in[13], 5'd18, 32'd120}; 24'b101101111010101001??????: {next, len, code} = {in[13], 5'd18, 32'd121}; 24'b111101110010111110??????: {next, len, code} = {in[13], 5'd18, 32'd122}; 24'b010100100011010000??????: {next, len, code} = {in[13], 5'd18, 32'd123}; 24'b001001001111011001??????: {next, len, code} = {in[13], 5'd18, 32'd124}; 24'b010100110010001001??????: {next, len, code} = {in[13], 5'd18, 32'd125}; 24'b111010110000111000??????: {next, len, code} = {in[13], 5'd18, 32'd126}; 24'b111010110011000101??????: {next, len, code} = {in[13], 5'd18, 32'd127}; 24'b010100001000111001??????: {next, len, code} = {in[13], 5'd18, 32'd128}; 24'b1000001011000110100?????: {next, len, code} = {in[12], 5'd19, 32'd129}; 24'b0010010111001110110?????: {next, len, code} = {in[12], 5'd19, 32'd130}; 24'b0101011001000001101?????: {next, len, code} = {in[12], 5'd19, 32'd131}; 24'b0101000010010101011?????: {next, len, code} = {in[12], 5'd19, 32'd132}; 24'b1111011111101001101?????: {next, len, code} = {in[12], 5'd19, 32'd133}; 24'b1011001000101010110?????: {next, len, code} = {in[12], 5'd19, 32'd134}; 24'b1011000001000100001?????: {next, len, code} = {in[12], 5'd19, 32'd135}; 24'b1110101100010011001?????: {next, len, code} = {in[12], 5'd19, 32'd136}; 24'b0010010111010111110?????: {next, len, code} = {in[12], 5'd19, 32'd137}; 24'b0010010001100111100?????: {next, len, code} = {in[12], 5'd19, 32'd138}; 24'b1011001011100000101?????: {next, len, code} = {in[12], 5'd19, 32'd139}; 24'b1011000100010100101?????: {next, len, code} = {in[12], 5'd19, 32'd140}; 24'b1111111001000111011?????: {next, len, code} = {in[12], 5'd19, 32'd141}; 24'b00100010111101101101????: {next, len, code} = {in[11], 5'd20, 32'd142}; 24'b10000010101010101101????: {next, len, code} = {in[11], 5'd20, 32'd143}; 24'b10110010100101001101????: {next, len, code} = {in[11], 5'd20, 32'd144}; 24'b01010110111100010000????: {next, len, code} = {in[11], 5'd20, 32'd145}; 24'b10110111110011001001????: {next, len, code} = {in[11], 5'd20, 32'd146}; 24'b11111101101100100101????: {next, len, code} = {in[11], 5'd20, 32'd147}; 24'b10110000010100100001????: {next, len, code} = {in[11], 5'd20, 32'd148}; 24'b10110010011010110110????: {next, len, code} = {in[11], 5'd20, 32'd149}; 24'b01111001010000011000????: {next, len, code} = {in[11], 5'd20, 32'd150}; 24'b11110110001011011011????: {next, len, code} = {in[11], 5'd20, 32'd151}; 24'b01010000100100001011????: {next, len, code} = {in[11], 5'd20, 32'd152}; 24'b10110001100101110111????: {next, len, code} = {in[11], 5'd20, 32'd153}; 24'b10111100110111101000????: {next, len, code} = {in[11], 5'd20, 32'd154}; 24'b01010001010111010000????: {next, len, code} = {in[11], 5'd20, 32'd155}; 24'b01010100111110001110????: {next, len, code} = {in[11], 5'd20, 32'd156}; 24'b11111110011001100111????: {next, len, code} = {in[11], 5'd20, 32'd157}; 24'b11110111111101010001????: {next, len, code} = {in[11], 5'd20, 32'd158}; 24'b10110000010111100000????: {next, len, code} = {in[11], 5'd20, 32'd159}; 24'b01001111100001000101????: {next, len, code} = {in[11], 5'd20, 32'd160}; 24'b01010010000111010110????: {next, len, code} = {in[11], 5'd20, 32'd161}; 24'b11101010101011101111????: {next, len, code} = {in[11], 5'd20, 32'd162}; 24'b11111110010011100011????: {next, len, code} = {in[11], 5'd20, 32'd163}; 24'b01010111001111101111????: {next, len, code} = {in[11], 5'd20, 32'd164}; 24'b10110001111111111101????: {next, len, code} = {in[11], 5'd20, 32'd165}; 24'b10110001001100110000????: {next, len, code} = {in[11], 5'd20, 32'd166}; 24'b11110100011000111101????: {next, len, code} = {in[11], 5'd20, 32'd167}; 24'b00101011101110100011????: {next, len, code} = {in[11], 5'd20, 32'd168}; 24'b01010000011011111110????: {next, len, code} = {in[11], 5'd20, 32'd169}; 24'b00000111000010000010????: {next, len, code} = {in[11], 5'd20, 32'd170}; 24'b00101010000011001000????: {next, len, code} = {in[11], 5'd20, 32'd171}; 24'b01001110010100101110????: {next, len, code} = {in[11], 5'd20, 32'd172}; 24'b11110000000010000000????: {next, len, code} = {in[11], 5'd20, 32'd173}; 24'b01001101011001111001????: {next, len, code} = {in[11], 5'd20, 32'd174}; 24'b11110111000111010101????: {next, len, code} = {in[11], 5'd20, 32'd175}; 24'b01111001101001110110????: {next, len, code} = {in[11], 5'd20, 32'd176}; 24'b11110000101011101111????: {next, len, code} = {in[11], 5'd20, 32'd177}; 24'b00100100100110101010????: {next, len, code} = {in[11], 5'd20, 32'd178}; 24'b11110001011011000011????: {next, len, code} = {in[11], 5'd20, 32'd179}; 24'b01010111001000110011????: {next, len, code} = {in[11], 5'd20, 32'd180}; 24'b01111000000100010101????: {next, len, code} = {in[11], 5'd20, 32'd181}; 24'b00100101101011001101????: {next, len, code} = {in[11], 5'd20, 32'd182}; 24'b10110010110000111001????: {next, len, code} = {in[11], 5'd20, 32'd183}; 24'b10110000101010000011????: {next, len, code} = {in[11], 5'd20, 32'd184}; 24'b00100100111110001101????: {next, len, code} = {in[11], 5'd20, 32'd185}; 24'b01111001101001101011????: {next, len, code} = {in[11], 5'd20, 32'd186}; 24'b01010001000000010001????: {next, len, code} = {in[11], 5'd20, 32'd187}; 24'b11110101111111101110????: {next, len, code} = {in[11], 5'd20, 32'd188}; 24'b10000010111110110011????: {next, len, code} = {in[11], 5'd20, 32'd189}; 24'b00000100011110100111????: {next, len, code} = {in[11], 5'd20, 32'd190}; 24'b11111101001111101100????: {next, len, code} = {in[11], 5'd20, 32'd191}; 24'b00101011100011110000????: {next, len, code} = {in[11], 5'd20, 32'd192}; 24'b00100100111001011001????: {next, len, code} = {in[11], 5'd20, 32'd193}; 24'b10000010101000000100????: {next, len, code} = {in[11], 5'd20, 32'd194}; 24'b11110001001000111100????: {next, len, code} = {in[11], 5'd20, 32'd195}; 24'b10111100011010011001????: {next, len, code} = {in[11], 5'd20, 32'd196}; 24'b000000??????????????????: begin casez (in[33:32]) 2'b1?: {next, len, code} = {1'b0, 5'd18, 32'd197}; 2'b01: {next, len, code} = {1'b0, 5'd19, 32'd198}; 2'b00: {next, len, code} = {1'b0, 5'd19, 32'd199}; default: ; endcase end default: ; endcase end endmodule verilator-5.042/test_regress/t/t_wait.py0000755000542200017500000000107015101701376020730 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=['--lint-only --no-timing'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_func_bad.v0000644000542200017500000000167215101701376021347 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin if (add(3'd1) != 0) $stop; // Too few args if (add(3'd1, 3'd2, 3'd3) != 0) $stop; // Too many args x; // Too few args if (hasout(3'd1) != 0) $stop; // outputs // f(.j(1), .no_such(2)); // Name mismatch f(.dup(1), .dup(3)); // Duplicate f(1,2,3); // Too many end function [2:0] add; input [2:0] from1; input [2:0] from2; begin add = from1 + from2; end endfunction task x; output y; begin end endtask function hasout; output [2:0] illegal_output; hasout = 0; endfunction function automatic int f( int j = 1, int dup = 0 ); return (j<<16) | dup; endfunction endmodule verilator-5.042/test_regress/t/t_display_impure.out0000644000542200017500000000005515101701376023170 0ustar mahmoudyfreeshell 1 2 *-* All Finished *-* verilator-5.042/test_regress/t/t_std_waiver.v0000644000542200017500000000060615101701376021751 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Rather than look at waivers, just check we included it `ifndef _VERILATED_STD_WAIVER_VLT_ `error "Didn't include, no _VERILATED_STD_WAIVER_VLT_" `endif module t; endmodule verilator-5.042/test_regress/t/t_compiler_include_split.py0000755000542200017500000000144115101701376024516 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.pli_filename = "t/t_compiler_include.cpp" test.top_filename = "t/t_compiler_include.v" test.compile(make_top_shell=False, make_main=False, verilator_flags2=[ "--exe", test.pli_filename, "--compiler-include", test.t_dir + "/t_compiler_include.h", "--output-split 1" ]) test.execute() test.passes() verilator-5.042/test_regress/t/t_select_little_pack.v0000644000542200017500000000114715101701376023435 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; // No ascending range warning here reg [7:0] pack [3:0]; initial begin pack[0] = 8'h78; pack[1] = 8'h88; pack[2] = 8'h98; pack[3] = 8'hA8; if (pack[0] !== 8'h78) $stop; if (pack[1] !== 8'h88) $stop; if (pack[2] !== 8'h98) $stop; if (pack[3] !== 8'hA8) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_timeout.py0000755000542200017500000000141615101701376021456 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') test.passes() test.timeout(1) # Check whether the soft limit is set to 1s test.run(cmd=["bash", "-c", "\"[ '$(ulimit -St)' -eq 1 ] || exit 1\""]) # Set the hard limit to 2s (in case soft limit fails) and run a command which spins until signalled test.run(cmd=["bash", "-c", "\"trap 'exit 0' SIGXCPU; ulimit -Ht 2; while :; do :; done\""]) test.passes() verilator-5.042/test_regress/t/t_lint_const_func_dpi_bad.py0000755000542200017500000000076315101701376024625 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_param_typedef2.v0000644000542200017500000000120315101701376023663 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 virtual class Virt; endclass class MyInt; int x; endclass class uvm_object_registry #( type T = Virt ); static function T create_object(); T obj = new(); obj.x = 1; return obj; endfunction endclass typedef uvm_object_registry#(MyInt) type_id; module t; initial begin MyInt mi = type_id::create_object(); if (mi.x != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_trace_timescale.v0000644000542200017500000000103015101701376022716 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `timescale 1ms/1ms // See also t_time_sc_*.v/pl module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc = 0; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 10) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_case_x_bad.py0000755000542200017500000000076615101701376022047 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_notiming_off.out0000644000542200017500000000362715101701376022630 0ustar mahmoudyfreeshell%Error-NOTIMING: t/t_timing_off.v:25:8: Event control statement in this location requires --timing : ... note: In instance 't' : ... With --no-timing, suggest have one event control statement per procedure, at the top of the procedure 25 | @e1; | ^ ... For error description see https://verilator.org/warn/NOTIMING?v=latest %Warning-STMTDLY: t/t_timing_off.v:33:12: Ignoring delay on this statement due to --no-timing : ... note: In instance 't' 33 | initial #2 ->e1; | ^ ... For warning description see https://verilator.org/warn/STMTDLY?v=latest ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message. %Warning-STMTDLY: t/t_timing_off.v:37:12: Ignoring delay on this statement due to --no-timing : ... note: In instance 't' 37 | initial #3 $stop; | ^ %Warning-STMTDLY: t/t_timing_off.v:38:12: Ignoring delay on this statement due to --no-timing : ... note: In instance 't' 38 | initial #1 @(e1, e2) #1 $stop; | ^ %Error-NOTIMING: t/t_timing_off.v:38:15: Event control statement in this location requires --timing : ... note: In instance 't' : ... With --no-timing, suggest have one event control statement per procedure, at the top of the procedure 38 | initial #1 @(e1, e2) #1 $stop; | ^ %Warning-STMTDLY: t/t_timing_off.v:38:25: Ignoring delay on this statement due to --no-timing : ... note: In instance 't' 38 | initial #1 @(e1, e2) #1 $stop; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_math_width.v0000644000542200017500000000250515101701376021732 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (); // See also t_lint_width parameter A_ONE = '1; // verilator lint_off WIDTH parameter [3:0] A_W4 = A_ONE; // verilator lint_on WIDTH initial begin if ($bits(A_ONE) != 1 || A_ONE !== 1'b1) $stop; if ($bits(A_W4) != 4) $stop; if (A_W4 != 4'b0001) $stop; end b #(.B_WIDTH(48)) b (); reg [4:0] c; integer c_i; initial begin c_i = 3; c = 1'b1 << c_i; // No width warning when not embedded in expression, as is common syntax if (c != 5'b1000) $stop; end localparam D_TT = 32'd23; localparam D_SIX = 6; // verilator lint_off WIDTH localparam [5:0] D_SUB = D_TT - D_SIX; // verilator lint_on WIDTH initial begin if (D_SUB != 17) $stop; end initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule module b; parameter B_WIDTH = 1; localparam B_VALUE0 = {B_WIDTH{1'b0}}; localparam B_VALUE1 = {B_WIDTH{1'b1}}; reg [47:0] b_val; initial begin b_val = B_VALUE0; if (b_val != 48'b0) $stop; b_val = B_VALUE1; if (b_val != ~48'b0) $stop; end endmodule verilator-5.042/test_regress/t/t_inst_port_array.py0000755000542200017500000000073415101701376023211 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_inst_overwide.v0000644000542200017500000000235415101701376022465 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs outc_w30, outd_w73, // Inputs clk, ina_w1, inb_w61 ); input clk; input ina_w1; input [60:0] inb_w61; output [29:0] outc_w30; output [72:0] outd_w73; sub sub ( // Outputs .outy_w92 (outc_w30), // .large => (small) .outz_w22 (outd_w73), // .small => (large) // Inputs .clk (clk), .inw_w31 (ina_w1), // .large <= (small) .inx_w11 (inb_w61) // .small <= (large) ); endmodule module sub (/*AUTOARG*/ // Outputs outy_w92, outz_w22, // Inputs clk, inw_w31, inx_w11 ); input clk; input [30:0] inw_w31; input [10:0] inx_w11; output reg [91:0] outy_w92 /*verilator public*/; output reg [21:0] outz_w22 /*verilator public*/; always @(posedge clk) begin outy_w92 <= {inw_w31[29:0],inw_w31[29:0],inw_w31[29:0],2'b00}; outz_w22 <= {inx_w11[10:0],inx_w11[10:0]}; end endmodule // regfile verilator-5.042/test_regress/t/t_alias_sub_select.v0000644000542200017500000000100715101701376023077 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ // Inputs clk ); input clk; sub s (); assign s.a[0] = 0; assign s.b[1] = 1; initial begin if (s.a != 2) $stop; if (s.b != 2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module sub; wire [1:0] a, b; alias a = b; endmodule verilator-5.042/test_regress/t/t_let_unsup.out0000644000542200017500000000057515101701376022167 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_let_unsup.v:10:10: Unsupported: let typed ports 10 | let G(int a) = 30 + a; | ^~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_let_unsup.v:11:10: Unsupported: let typed ports 11 | let H(signed a) = 30 + a; | ^~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_inst_signed.py0000755000542200017500000000073415101701376022300 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_class.py0000755000542200017500000000116615101701376022255 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile( # verilator_flags2 = ['--binary --trace-vcd'], verilator_flags2=['--binary --trace-vcd']) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_udp_bad.v0000644000542200017500000000065615101701376021205 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; wire a, b; udp_x x (a, b); endmodule primitive udp_x (a_bad, b, c_bad); tri a_bad; output b; output c_bad; table //a b 0 : 1; 1 : 0; endtable endprimitive verilator-5.042/test_regress/t/t_preproc.out0000644000542200017500000003655115101701376021626 0ustar mahmoudyfreeshell`line 1 "t/t_preproc.v" 1 `line 6 "t/t_preproc.v" 0 `line 8 "t/t_preproc.v" 0 `line 10 "t/t_preproc.v" 0 `line 1 "t/t_preproc_inc2.vh" 1 `line 2 "t/t_preproc_inc2.vh" 0 At file "t/t_preproc_inc2.vh" line 5 `line 7 "t/t_preproc_inc2.vh" 0 `line 1 "t/t_preproc_inc3.vh" 1 `line 2 "t/t_preproc_inc3.vh" 0 `line 6 "t/t_preproc_inc3.vh" 0 At file "t/t_preproc_inc3.vh" line 10 `line 12 "inc3_a_filename_from_line_directive_with_LINE" 0 At file "inc3_a_filename_from_line_directive_with_LINE" line 12 `line 100 "inc3_a_filename_from_line_directive" 0 At file "inc3_a_filename_from_line_directive" line 100 `line 103 "inc3_a_filename_from_line_directive" 0 `line 106 "inc3_a_filename_from_line_directive" 0 `line 110 "inc3_a_filename_from_line_directive" 0 `line 7 "t/t_preproc_inc2.vh" 2 `line 9 "t/t_preproc_inc2.vh" 0 `line 10 "t/t_preproc.v" 2 `line 12 "t/t_preproc.v" 0 `line 15 "t/t_preproc.v" 0 /*verilator pass_thru comment*/ `line 17 "t/t_preproc.v" 0 /*verilator pass_thru_comment2*/ `line 19 "t/t_preproc.v" 0 `line 22 "t/t_preproc.v" 0 wire [3:0] q = { 1'b1 , 1'b0 , 1'b1 , 1'b1 }; `line 32 "t/t_preproc.v" 0 text. `line 34 "t/t_preproc.v" 0 foo bar foobar2 `line 39 "t/t_preproc.v" 0 `line 43 "t/t_preproc.v" 0 `line 48 "t/t_preproc.v" 0 first part `line 49 "t/t_preproc.v" 0 second part `line 49 "t/t_preproc.v" 0 third part { `line 50 "t/t_preproc.v" 0 a, `line 50 "t/t_preproc.v" 0 b, `line 50 "t/t_preproc.v" 0 c} Line_Preproc_Check 51 `line 53 "t/t_preproc.v" 0 `line 55 "t/t_preproc.v" 0 `line 57 "t/t_preproc.v" 0 deep deep `line 61 "t/t_preproc.v" 0 "Inside: `nosubst" "`nosubst" `line 66 "t/t_preproc.v" 0 x y LLZZ x y p q LLZZ p q r s LLZZ r s LLZZ p q LLZZ p q r s LLZZ r s `line 72 "t/t_preproc.v" 0 firstline comma","line LLZZ firstline comma","line `line 74 "t/t_preproc.v" 0 x y LLZZ "a" y `line 77 "t/t_preproc.v" 0 (a,b)(a,b) `line 80 "t/t_preproc.v" 0 $display("left side: \"right side\"") `line 83 "t/t_preproc.v" 0 bar_suffix more `line 86 "t/t_preproc.v" 0 arg suffix_after_space `line 89 "t/t_preproc.v" 0 `line 91 "t/t_preproc.v" 0 $c("Zap(\"",bug1,"\");");; `line 92 "t/t_preproc.v" 0 $c("Zap(\"","bug2","\");");; `line 94 "t/t_preproc.v" 0 `line 97 "t/t_preproc.v" 0 `line 100 "t/t_preproc.v" 0 initial begin $display("pre thrupre thrumid thrupost post: \"right side\""); $display("left side: \"right side\""); $display("left side: \"right side\""); $display("left_side: \"right_side\""); $display("na: \"right_side\""); $display("prep ( midp1 left_side midp2 ( outp ) ): \"right_side\""); $display("na: \"nana\""); $display("left_side right_side: \"left_side right_side\""); $display(": \"\""); $display("left side: \"right side\""); $display("left side: \"right side\""); $display("standalone"); `line 121 "t/t_preproc.v" 0 $display("twoline: \"first second\""); $write("*-* All Finished *-*\n"); $finish; end endmodule `line 131 "t/t_preproc.v" 0 `line 134 "t/t_preproc.v" 0 `line 139 "t/t_preproc.v" 0 module add1 ( input wire d1, output wire o1); `line 140 "t/t_preproc.v" 0 wire tmp_d1 = d1; `line 140 "t/t_preproc.v" 0 wire tmp_o1 = tmp_d1 + 1; `line 140 "t/t_preproc.v" 0 assign o1 = tmp_o1 ; endmodule module add2 ( input wire d2, output wire o2); `line 143 "t/t_preproc.v" 0 wire tmp_d2 = d2; `line 143 "t/t_preproc.v" 0 wire tmp_o2 = tmp_d2 + 1; `line 143 "t/t_preproc.v" 0 assign o2 = tmp_o2 ; endmodule `line 146 "t/t_preproc.v" 0 `line 152 "t/t_preproc.v" 0 `line 157 "t/t_preproc.v" 0 `line 157 "t/t_preproc.v" 0 generate for (i=0; i<(3); i=i+1) begin `line 157 "t/t_preproc.v" 0 psl cover { m5k.f .ctl._ctl_mvldx_m1.d[i] & ~m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoRise: m5kc_fcl._ctl_mvldx_m1"; `line 157 "t/t_preproc.v" 0 psl cover { ~m5k.f .ctl._ctl_mvldx_m1.d[i] & m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoFall: m5kc_fcl._ctl_mvldx_m1"; `line 157 "t/t_preproc.v" 0 end endgenerate `line 159 "t/t_preproc.v" 0 module prot(); `protected I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl) #nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk] `line 165 "t/t_preproc.v" 0 `endprotected endmodule `line 169 "t/t_preproc.v" 0 module t_lint_pragma_protected; `line 173 "t/t_preproc.v" 0 `pragma protect begin_protected `pragma protect version=1 `pragma protect encrypt_agent="XXXXX" `pragma protect encrypt_agent_info="YYYYY" `pragma protect data_method="AES128-CBC" `pragma protect key_keyowner="BIG3#1" `pragma protect key_keyname="AAAAAA" `pragma protect key_method="RSA" `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `pragma protect key_block ICAgICAgICAgICAgICAgICAgIEdOVSBMRVNTRVIgR0VORVJBTCBQVUJMSUMgTElDRU5TRQogICAg KSAyMDA3IE== `line 186 "t/t_preproc.v" 0 `pragma protect key_keyowner="BIG3#2" `pragma protect key_keyname="BBBBBB" `pragma protect key_method="RSA" `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `pragma protect key_block IEV2ZXJ5b25lIGlzIHBlcm1pdHRlZCB0byBjb3B5IGFuZCBkaXN0cmlidXRlIHZlcmJhdGltIGNv cGllcwogb2YgdGhpcyBsaWNlbnNlIGRvY3VtZW50LCBidXQgY2hhbmdpbmcgaXQgaXMgbm90IGFs bG93ZWQuCgoKICBUaGl= `line 195 "t/t_preproc.v" 0 `pragma protect key_keyowner="BIG3#3" `pragma protect key_keyname="CCCCCCCC" `pragma protect key_method="RSA" `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `pragma protect key_block TGljZW5zZSBpbmNvcnBvcmF0ZXMKdGhlIHRlcm1zIGFuZCBjb25kaXRpb25zIG9mIHZlcnNpb24g MyBvZiB0aGUgR05VIEdlbmVyYWwgUHVibGljCkxpY2Vuc2UsIHN1cHBsZW1lbnRlZCBieSB0aGUg YWRkaXRpb25hbCBwZXJ= `line 204 "t/t_preproc.v" 0 `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 295) `pragma protect data_block aW5pdGlvbnMuCgogIEFzIHVzZWQgaGVyZWluLCAidGhpcyBMaWNlbnNlIiByZWZlcnMgdG8gdmVy c2lvbiAzIG9mIHRoZSBHTlUgTGVzc2VyCkdlbmVyYWwgUHVibGljIExpY2Vuc2UsIGFuZCB0aGUg IkdOVSBHUEwiIHJlZmVycyB0byB2ZXJzaW9uIDMgb2YgdGhlIEdOVQpHZW5lcmFsIFB1YmxpYyBM aWNlbnNlLgoKICAiVGhlIExpYnJhcnkiIHJlZmVycyB0byBhIGNvdmVyZWQgd29yayBnb3Zlcm5l ZCBieSB0aGlzIExpY2Vuc2UsCm90aGVyIHRoYW4gYW4gQXBwbGljYXRpb24gb3IgYSBDb21iaW5l ZCBXb3JrIGFzIG== `line 214 "t/t_preproc.v" 0 `pragma protect end_protected `line 216 "t/t_preproc.v" 0 `pragma protect `pragma protect end `line 220 "t/t_preproc.v" 0 endmodule `line 222 "t/t_preproc.v" 0 `line 232 "t/t_preproc.v" 0 begin addr <= (({regs[6], regs[7]} + 1)); rd <= 1; end and begin addr <= (({regs[6], regs[7]})); wdata <= (rdata); wr <= 1; end begin addr <= ({regs[6], regs[7]} + 1); rd <= 1; end begin addr <= ({regs[6], regs[7]}); wdata <= (rdata); wr <= 1; end more `line 236 "t/t_preproc.v" 0 `line 239 "t/t_preproc.v" 0 `line 1 "t/t_preproc_inc4.vh" 1 `line 2 "t/t_preproc_inc4.vh" 0 `line 6 "t/t_preproc_inc4.vh" 0 `line 8 "t/t_preproc_inc4.vh" 0 `line 239 "t/t_preproc.v" 2 `line 240 "t/t_preproc.v" 0 `line 243 "t/t_preproc.v" 0 `line 245 "t/t_preproc.v" 0 `line 249 "t/t_preproc.v" 0 `line 252 "t/t_preproc.v" 0 $blah("ab,cd","e,f"); $blah(this.logfile,vec); $blah(this.logfile,vec[1,2,3]); $blah(this.logfile,{blah.name(), " is not foo"}); `line 258 "t/t_preproc.v" 0 `line 261 "t/t_preproc.v" 0 `pragma foo = 1 `default_nettype none `default_nettype uwire `line 265 "t/t_preproc.v" 0 `line 268 "t/t_preproc.v" 0 `line 272 "t/t_preproc.v" 0 Line_Preproc_Check 272 `line 274 "t/t_preproc.v" 0 `line 277 "t/t_preproc.v" 0 (p,q) `line 284 "t/t_preproc.v" 0 (x,y) Line_Preproc_Check 285 `line 287 "t/t_preproc.v" 0 `line 290 "t/t_preproc.v" 0 beginend beginend "beginend" `line 298 "t/t_preproc.v" 0 `\esc`def `line 304 "t/t_preproc.v" 0 Not a \`define `line 306 "t/t_preproc.v" 0 x,y)--bee submacro has comma paren `line 314 "t/t_preproc.v" 0 $display("bits %d %d", $bits(foo), 10); `line 319 "t/t_preproc.v" 0 `line 324 "t/t_preproc.v" 0 `line 327 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 assign a3 = ~b3 ; `line 341 "t/t_preproc.v" 0 `line 343 "t/t_preproc.v" 0 \ `line 352 "t/t_preproc.v" 0 `line 352 "t/t_preproc.v" 0 `line 352 "t/t_preproc.v" 0 def i `line 354 "t/t_preproc.v" 0 `line 356 "t/t_preproc.v" 0 `line 360 "t/t_preproc.v" 0 `line 366 "t/t_preproc.v" 0 1 /*verilator NOT IN DEFINE*/ (nodef) 2 /*verilator PART OF DEFINE*/ (hasdef) 3 `line 368 "t/t_preproc.v" 0 /*verilator NOT PART OF DEFINE*/ (nodef) `line 369 "t/t_preproc.v" 0 4 `line 369 "t/t_preproc.v" 0 /*verilator PART OF DEFINE*/ (nodef) `line 370 "t/t_preproc.v" 0 5 also in `line 370 "t/t_preproc.v" 0 also3 (nodef) HAS a NEW `line 373 "t/t_preproc.v" 0 LINE `line 375 "t/t_preproc.v" 0 `line 377 "t/t_preproc.v" 0 `line 390 "t/t_preproc.v" 0 `line 393 "t/t_preproc.v" 0 EXP: clxx_scen clxx_scen EXP: clxx_scen "clxx_scen" EXP: do if (start("verilog/inc1.v", 25)) begin message({"Blah-", "clx_scen", " end"}); end while(0); `line 399 "t/t_preproc.v" 0 do `line 399 "t/t_preproc.v" 0 `line 399 "t/t_preproc.v" 0 `line 399 "t/t_preproc.v" 0 `line 399 "t/t_preproc.v" 0 `line 399 "t/t_preproc.v" 0 if (start("t/t_preproc.v", 399)) begin `line 399 "t/t_preproc.v" 0 `line 399 "t/t_preproc.v" 0 message({"Blah-", "clx_scen", " end"}); `line 399 "t/t_preproc.v" 0 end `line 399 "t/t_preproc.v" 0 `line 399 "t/t_preproc.v" 0 while(0); `line 401 "t/t_preproc.v" 0 `line 403 "t/t_preproc.v" 0 `line 407 "t/t_preproc.v" 0 `line 407 "t/t_preproc.v" 0 `line 408 "t/t_preproc.v" 0 EXP: This is fooed This is fooed EXP: This is fooed_2 This is fooed_2 `line 415 "t/t_preproc.v" 0 np np `line 426 "t/t_preproc.v" 0 `line 429 "t/t_preproc.v" 0 `line 437 "t/t_preproc.v" 0 `line 441 "t/t_preproc.v" 0 hello3hello3hello3 hello4hello4hello4hello4 `line 447 "t/t_preproc.v" 0 `line 1 "t/t_preproc_inc4.vh" 1 `line 2 "t/t_preproc_inc4.vh" 0 `line 6 "t/t_preproc_inc4.vh" 0 `line 8 "t/t_preproc_inc4.vh" 0 `line 447 "t/t_preproc.v" 2 `line 448 "t/t_preproc.v" 0 `line 456 "t/t_preproc.v" 0 Line_Preproc_Check 460 Line_Preproc_Check 466 "FOO \ BAR " "arg_line1 \ arg_line2" "FOO \ BAR " `line 469 "t/t_preproc.v" 0 Line_Preproc_Check 469 `line 473 "t/t_preproc.v" 0 abc `line 483 "t/t_preproc.v" 0 EXP: sonet_frame sonet_frame `line 489 "t/t_preproc.v" 0 EXP: sonet_frame sonet_frame EXP: sonet_frame sonet_frame `line 499 "t/t_preproc.v" 0 EXP: module zzz ; endmodule module zzz ; endmodule module zzz ; endmodule `line 506 "t/t_preproc.v" 0 EXP: module a_b ; endmodule module a_b ; endmodule module a_b ; endmodule `line 511 "t/t_preproc.v" 0 integer foo; module t; initial begin : \`LEX_CAT(a[0],_assignment) `line 523 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\`LEX_CAT(a[0],_assignment) "); end initial begin : \a[0]_assignment_a[1] `line 530 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\a[0]_assignment_a[1] "); end initial begin : \`CAT(pp,suffix) $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(pp,suffix) "); end initial begin : \`CAT(ff,bb) `line 544 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(ff,bb) "); end initial begin : \`zzz `line 550 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\`zzz "); end initial begin : \`FOO `line 557 "t/t_preproc.v" 0 $write("GOT%%m='%m' OTHER_EXP='%s'\n OUR_EXP='%s'", "t.bar ","t.\\`FOO "); end initial begin : \xx`FOO `line 559 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\xx`FOO "); end initial begin : \`UNKNOWN $write("GOT%%m='%m' EXP='%s'\n", "t.\\`UNKNOWN "); end initial begin : \`DEF_NO_EXPAND $write("GOT%%m='%m' EXP='%s'\n", "t.\\`DEF_NO_EXPAND "); end initial $write("GOT='%s' EXP='%s'\n", "foo name baz", "foo bar baz"); initial $write("GOT='%s' EXP='%s'\n", "foo name baz", "foo `A(bar) baz"); initial $write("Slashed=`%s'\n", "1//2.3"); initial `line 590 "t/t_preproc.v" 0 $display("%s%s","a1","b2c3\n"); endmodule `line 593 "t/t_preproc.v" 0 `line 596 "t/t_preproc.v" 0 $display("RAM0"); $display("CPU"); `line 601 "t/t_preproc.v" 0 `line 606 "t/t_preproc.v" 0 XXE_FAMILY = XXE_ $display("XXE_ is defined"); `line 613 "t/t_preproc.v" 0 XYE_FAMILY = XYE_ $display("XYE_ is defined"); `line 620 "t/t_preproc.v" 0 XXS_FAMILY = XXS_some $display("XXS_some is defined"); `line 627 "t/t_preproc.v" 0 XYS_FAMILY = XYS_foo $display("XYS_foo is defined"); `line 634 "t/t_preproc.v" 0 `line 636 "t/t_preproc.v" 0 `line 644 "t/t_preproc.v" 0 `line 651 "t/t_preproc.v" 0 `line 658 "t/t_preproc.v" 0 `line 665 "t/t_preproc.v" 0 `line 667 "t/t_preproc.v" 0 `line 669 "t/t_preproc.v" 0 (.mySig (myInterface.pa5), `line 673 "t/t_preproc.v" 0 `line 676 "t/t_preproc.v" 0 `dbg_hdl(UVM_LOW, ("Functional coverage enabled: paramgrp")); `line 679 "t/t_preproc.v" 0 `line 687 "t/t_preproc.v" 0 module pcc2_cfg; generate `line 689 "t/t_preproc.v" 0 covergroup a @(posedge b); `line 689 "t/t_preproc.v" 0 c: coverpoint d iff ((c) === 1'b1); endgroup `line 689 "t/t_preproc.v" 0 a u_a; `line 689 "t/t_preproc.v" 0 initial do begin $display ("DEBUG : %s [%m]", $sformatf ("Functional coverage enabled: u_a")); end while(0); endgenerate endmodule `line 693 "t/t_preproc.v" 0 "`NOT_DEFINED_STR" `line 698 "t/t_preproc.v" 0 """First line with "quoted"\nSecond line\ Third line""" """First line Second line""" `line 705 "t/t_preproc.v" 0 """QQQ defform""" """QQQ defval""" `line 710 "t/t_preproc.v" 0 "string argument" `line 714 "t/t_preproc.v" 0 `line 717 "t/t_preproc.v" 0 bar "foo foo foo" bar bar """foo foo foo""" bar `line 722 "t/t_preproc.v" 0 predef 0 0 predef 1 1 predef 2 2 predef 3 3 predef 10 10 predef 11 11 predef 20 20 predef 21 21 predef 22 22 predef 23 23 predef -2 -2 predef -1 -1 predef 0 0 predef 1 1 predef 2 2 `line 744 "t/t_preproc.v" 0 string boo = "test"; string boo = "test x,y x,y"; string boo = "testx,ytest x x,y"; string boo = "testtest x,y xquux(test)"; `line 757 "t/t_preproc.v" 0 `line 760 "t/t_preproc.v" 0 `line 769 "t/t_preproc.v" 0 verilator-5.042/test_regress/t/t_altera_lpm_ram_dq.py0000755000542200017500000000111115101701376023423 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) test.compile(verilator_flags2=["--top-module", module]) test.passes() verilator-5.042/test_regress/t/t_class_static_member_pkg.v0000644000542200017500000000240615101701376024446 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); package Pkg; class Cls; int c_no = 2; //automatic int c_au = 2; // automatic not a legal keyword here static int c_st = 22; function int f_c_no (); ++c_no; return c_no; endfunction function int f_c_st (); ++c_st; return c_st; endfunction static function int f_cs_st (); ++c_st; return c_st; endfunction endclass endpackage module t; Pkg::Cls a = new; Pkg::Cls b = new; int v; initial begin v = a.f_c_no(); `checkh(v, 3); v = a.f_c_no(); `checkh(v, 4); v = b.f_c_no(); `checkh(v, 3); v = b.f_c_no(); `checkh(v, 4); v = a.f_c_st(); `checkh(v, 23); v = a.f_c_st(); `checkh(v, 24); v = b.f_c_st(); `checkh(v, 25); v = b.f_c_st(); `checkh(v, 26); // v = Pkg::Cls::f_cs_st(); `checkh(v, 27); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_func_no_parentheses_bad.out0000644000542200017500000000042515101701376025001 0ustar mahmoudyfreeshell%Error: t/t_func_no_parentheses_bad.v:16:11: Found definition of 'func' as a FUNC but expected a variable 16 | a = func; | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_typedef_unused_bad.py0000755000542200017500000000103015101701376023611 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["--Wpedantic"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_json_only_tag.py0000755000542200017500000000135415101701376022636 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') out_filename = test.obj_dir + "/V" + test.name + ".tree.json" test.compile(verilator_flags2=['--no-std', '--json-only', '--no-json-edit-nums'], verilator_make_gmake=False, make_top_shell=False, make_main=False) test.files_identical(out_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_struct_literal_param.py0000755000542200017500000000077015101701376024212 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--debug"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_property_untyped_unsup.out0000644000542200017500000000056415101701376025035 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_property_untyped_unsup.v:20:52: Untyped property port following a typed port 20 | property check(cyc_mod_2, logic [4:0] expected, arg3, untyped arg4, arg5); | ^~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_hier_block_perf.vlt0000644000542200017500000000050415101701376023254 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 `verilator_config `ifdef WORKERS hier_workers -module "Test" -workers `WORKERS hier_workers -module "Check" -workers `WORKERS `endif verilator-5.042/test_regress/t/t_semaphore_std.py0000755000542200017500000000110215101701376022615 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_semaphore.v" test.compile(verilator_flags2=["--binary -Wall -DSEMAPHORE_T=std::semaphore"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_package_struct.v0000644000542200017500000000106115101701376022575 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 package pkg; typedef struct { string a, b; struct { bit a, b; } has; } strings; endpackage module t; initial begin pkg::strings stct; stct.a = "hello"; stct.b = "world"; $display("%s, %s (%1b, %1b)", stct.a, stct.b, stct.has.a, stct.has.b); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_lint_literal_bad.out0000644000542200017500000000065115101701376023434 0ustar mahmoudyfreeshell%Warning-WIDTHTRUNC: t/t_lint_literal_bad.v:10:33: Value too large for 8 bit number: 256 10 | localparam the_localparam = 8'd256; | ^~~~~~ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_unopt_combo_isolate_vlt.py0000755000542200017500000000365215101701376024725 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_unopt_combo.v" out_filename = test.obj_dir + "/V" + test.name + ".tree.json" test.compile(verilator_flags2=[ "--no-json-edit-nums", "--stats", test.t_dir + "/t_unopt_combo_isolate.vlt", "-fno-dfg" ]) if test.vlt_all: test.file_grep(test.stats, r'Optimizations, isolate_assignments blocks\s+4') test.file_grep( out_filename, r'{"type":"VAR","name":"t.b",.*"loc":"\w,23:[^"]*",.*"origName":"b",.*"attrIsolateAssign":true,.*"dtypeName":"logic"' ) test.file_grep( out_filename, r'{"type":"VAR","name":"__Vfunc_t.file.get_31_16__0__Vfuncout",.*"loc":"\w,104:[^"]*",.*"origName":"__Vfunc_t__DOT__file__DOT__get_31_16__0__Vfuncout",.*"attrIsolateAssign":true,.*"dtypeName":"logic"' ) test.file_grep( out_filename, r'{"type":"VAR","name":"__Vfunc_t.file.get_31_16__0__t_crc",.*"loc":"\w,105:[^"]*",.*"origName":"__Vfunc_t__DOT__file__DOT__get_31_16__0__t_crc",.*"attrIsolateAssign":true,.*"dtypeName":"logic"' ) test.file_grep( out_filename, r'{"type":"VAR","name":"__Vtask_t.file.set_b_d__1__t_crc",.*"loc":"\w,115:[^"]*",.*"origName":"__Vtask_t__DOT__file__DOT__set_b_d__1__t_crc",.*"attrIsolateAssign":true,.*"dtypeName":"logic"' ) test.file_grep( out_filename, r'{"type":"VAR","name":"__Vtask_t.file.set_b_d__1__t_c",.*"loc":"\w,116:[^"]*",.*"origName":"__Vtask_t__DOT__file__DOT__set_b_d__1__t_c",.*"attrIsolateAssign":true,.*"dtypeName":"logic"' ) test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_class.v0000644000542200017500000000134115101701376022062 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" class Cls #(parameter int PARAM); static int s_cls_static = 123; endclass module top(); typedef Cls#(.PARAM(0)) Cls_t; Cls_t obj; initial begin obj = new; `ifdef verilator obj.s_cls_static = $c("100"); // no-opt `else obj.s_cls_static = 100; `endif if (obj.s_cls_static != 100) $stop; if (obj.PARAM != 0) $stop; $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); $dumpvars(0); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_math_countbits_tri.v0000644000542200017500000000170415101701376023503 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Outputs num_zeros, num_ones, // Inputs clk, reset_l, vec ); input logic clk; input logic reset_l; input logic [7:0] vec; output logic [7:0] num_zeros; output logic [7:0] num_ones; always_comb begin num_zeros = '0; num_ones = '0; for (int i = 0; i < 8; i++) begin if (vec[i] == 0) begin num_zeros++; end else begin num_ones++; end end end assert property (@(negedge clk) disable iff (~reset_l) (num_ones == $countones(vec))); assert property (@(negedge clk) disable iff (~reset_l) (num_zeros == $countbits(vec, '0))); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_let_stmt_bad.out0000644000542200017500000000041015101701376022576 0ustar mahmoudyfreeshell%Error: t/t_let_stmt_bad.v:15:14: Expected statement, not let substitution 'letf' 15 | 0: letf(0); | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_sarif.py0000755000542200017500000000254615101701376021101 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=['-Wno-fatal --diagnostics-sarif --no-skip-identical'], expect_filename=test.golden_filename) sarif_filename = test.obj_dir + "/" + test.vm_prefix + ".sarif" # Make sure V3Error meta comments aren't in any outputs test.file_grep_not(test.compile_log_filename, r'__WARN') test.file_grep_not(sarif_filename, r'__WARN') test.files_identical(sarif_filename, "t/" + test.name + ".sarif.out", "logfile") # Check that sarif parses nout = test.run_capture("sarif --version", check=False) version_match = re.search(r'SARIF tools', nout, re.IGNORECASE) if not version_match: test.skip("sarif is not installed") html_filename = test.obj_dir + "/validation.html" test.run(cmd=['sarif', 'html', sarif_filename, '--output', html_filename]) # Validator: # https://sarifweb.azurewebsites.net/Validation # Rewrite # test.run(cmd=['sarif copy t/t_sarif.out --output ' + test.obj_dir + '/t_sarif.out.rewrite']) test.passes() verilator-5.042/test_regress/t/t_inst_notunsized.v0000644000542200017500000000552615101701376023047 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [71:0] muxed; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .muxed (muxed[71:0]), // Inputs .clk (clk), .in (in[31:0])); // Aggregate outputs into a single result vector wire [63:0] result = {muxed[63:0]}; wire [5:0] width_check = cyc[5:0] + 1; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h20050a66e7b253d1 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs muxed, // Inputs clk, in ); input clk; input [31:0] in; output [71:0] muxed; wire [71:0] a = {in[7:0],~in[31:0],in[31:0]}; wire [71:0] b = {~in[7:0],in[31:0],~in[31:0]}; /*AUTOWIRE*/ Muxer muxer ( .sa (0), .sb (in[0]), /*AUTOINST*/ // Outputs .muxed (muxed[71:0]), // Inputs .a (a[71:0]), .b (b[71:0])); endmodule module Muxer (/*AUTOARG*/ // Outputs muxed, // Inputs sa, sb, a, b ); input sa; input sb; output wire [71:0] muxed; input [71:0] a; input [71:0] b; // Constification wasn't sizing with inlining and gave // unsized error on below // v assign muxed = (({72{sa}} & a) | ({72{sb}} & b)); endmodule verilator-5.042/test_regress/t/t_wait_fork.v0000644000542200017500000000102015101701376021556 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; logic never; integer n = 0; initial begin disable fork; fork #10 if (n != 0) $stop; else n = 1; #15 if (n != 1) $stop; else n = 2; join_none wait fork; if (n != 2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_tri_unconn.v0000644000542200017500000001063015101701376021756 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; wire one = '1; wire z0 = 'z; wire z1 = 'z; wire z2 = 'z; wire z3 = 'z; wire tog = cyc[0]; // verilator lint_off PINMISSING t_tri0 tri0a (.line(`__LINE__), .expval(1'b0)); // Pin missing t_tri0 tri0b (.line(`__LINE__), .expval(1'b0), .tn()); t_tri0 tri0z (.line(`__LINE__), .expval(1'b0), .tn(z0)); t_tri0 tri0Z (.line(`__LINE__), .expval(1'b0), .tn(1'bz)); t_tri0 tri0c (.line(`__LINE__), .expval(1'b0), .tn(1'b0)); t_tri0 tri0d (.line(`__LINE__), .expval(1'b1), .tn(1'b1)); // Warning would be reasonable given tri0 connect t_tri0 tri0e (.line(`__LINE__), .expval(1'b0), .tn(~one)); t_tri0 tri0f (.line(`__LINE__), .expval(1'b1), .tn(one)); t_tri0 tri0g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog)); t_tri0 tri0h (.line(`__LINE__), .expval(cyc[0]), .tn(tog)); t_tri1 tri1a (.line(`__LINE__), .expval(1'b1)); // Pin missing t_tri1 tri1b (.line(`__LINE__), .expval(1'b1), .tn()); t_tri1 tri1z (.line(`__LINE__), .expval(1'b1), .tn(z1)); t_tri1 tri1Z (.line(`__LINE__), .expval(1'b1), .tn(1'bz)); t_tri1 tri1c (.line(`__LINE__), .expval(1'b0), .tn(1'b0)); // Warning would be reasonable given tri1 connect t_tri1 tri1d (.line(`__LINE__), .expval(1'b1), .tn(1'b1)); t_tri1 tri1e (.line(`__LINE__), .expval(1'b0), .tn(~one)); t_tri1 tri1f (.line(`__LINE__), .expval(1'b1), .tn(one)); t_tri1 tri1g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog)); t_tri1 tri1h (.line(`__LINE__), .expval(cyc[0]), .tn(tog)); t_tri2 tri2a (.line(`__LINE__), .expval(1'b0)); // Pin missing t_tri2 tri2b (.line(`__LINE__), .expval(1'b0), .tn()); t_tri2 tri2z (.line(`__LINE__), .expval(1'b0), .tn(z2)); t_tri2 tri2Z (.line(`__LINE__), .expval(1'b0), .tn(1'bz)); t_tri2 tri2c (.line(`__LINE__), .expval(1'b0), .tn(1'b0)); t_tri2 tri2d (.line(`__LINE__), .expval(1'b1), .tn(1'b1)); t_tri2 tri2e (.line(`__LINE__), .expval(1'b0), .tn(~one)); t_tri2 tri2f (.line(`__LINE__), .expval(1'b1), .tn(one)); t_tri2 tri2g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog)); t_tri2 tri2h (.line(`__LINE__), .expval(cyc[0]), .tn(tog)); t_tri3 tri3a (.line(`__LINE__), .expval(1'b1)); // Pin missing t_tri3 tri3b (.line(`__LINE__), .expval(1'b1), .tn()); t_tri3 tri3z (.line(`__LINE__), .expval(1'b1), .tn(z3)); t_tri3 tri3Z (.line(`__LINE__), .expval(1'b1), .tn(1'bz)); t_tri3 tri3c (.line(`__LINE__), .expval(1'b0), .tn(1'b0)); t_tri3 tri3d (.line(`__LINE__), .expval(1'b1), .tn(1'b1)); t_tri3 tri3e (.line(`__LINE__), .expval(1'b0), .tn(~one)); t_tri3 tri3f (.line(`__LINE__), .expval(1'b1), .tn(one)); t_tri3 tri3g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog)); t_tri3 tri3h (.line(`__LINE__), .expval(cyc[0]), .tn(tog)); // verilator lint_on PINMISSING // Test loop always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module t_tri0 (line, expval, tn); input integer line; input expval; input tn; // Illegal to be inout; spec requires net connection to any inout tri0 tn; wire clk = t.clk; always @(posedge clk) if (tn !== expval) begin $display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop; end endmodule module t_tri1 (line, expval, tn); input integer line; input expval; input tn; tri1 tn; wire clk = t.clk; always @(posedge clk) if (tn !== expval) begin $display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop; end endmodule module t_tri2 (line, expval, tn); input integer line; input expval; input tn; pulldown(tn); wire clk = t.clk; always @(posedge clk) if (tn !== expval) begin $display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop; end endmodule module t_tri3 (line, expval, tn); input integer line; input expval; input tn; pullup(tn); wire clk = t.clk; always @(negedge clk) if (tn !== expval) begin $display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop; end endmodule verilator-5.042/test_regress/t/t_time_vpi_c.cpp0000644000542200017500000000632515101701376022241 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2011 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "svdpi.h" #include "vpi_user.h" #include #include extern "C" { #include } // These require the above. Comment prevents clang-format moving them #include "TestCheck.h" #include "TestVpi.h" int errors = 0; //====================================================================== #define NEED_EXTERNS #ifdef NEED_EXTERNS extern "C" { extern void dpii_check(); } #endif //====================================================================== void dpi_bad() { { int res = svGetTime(0, nullptr); TEST_CHECK_EQ(res, -1); } { int res = svGetTimeUnit(0, nullptr); TEST_CHECK_EQ(res, -1); } { int res = svGetTimePrecision(0, nullptr); TEST_CHECK_EQ(res, -1); } } void dpi_show(svScope obj) { const char* namep; if (obj) { namep = svGetNameFromScope(obj); } else { namep = "global"; } svTimeVal t; // aka s_vpi_time t.type = vpiSimTime; int gres = svGetTime(obj, &t); vpi_printf(const_cast("%s svGetTime = %d %d,%d\n"), namep, gres, (int)t.high, (int)t.low); // These will both print the precision, because the 0 asks for global scope int32_t u = 99; int ures = svGetTimeUnit(obj, &u); int32_t p = 99; int pres = svGetTimePrecision(obj, &p); vpi_printf(const_cast("%s svGetTimeUnit = %d %d"), namep, ures, u); vpi_printf(const_cast(" svGetTmePrecision = %d %d\n"), pres, p); } void vpi_show(vpiHandle obj) { const char* namep; if (obj) { namep = vpi_get_str(vpiFullName, obj); } else { namep = "global"; } s_vpi_time t; t.type = vpiSimTime; vpi_get_time(obj, &t); vpi_printf(const_cast("%s vpiSimTime = %d,%d"), namep, (int)t.high, (int)t.low); // Should be same value as vpiSimTime, just converted to real t.type = vpiScaledRealTime; vpi_get_time(obj, &t); vpi_printf(const_cast(" vpiScaledRealTime = %g\n"), t.real); // These will both print the precision, because the 0 asks for global scope int u = vpi_get(vpiTimeUnit, obj); int p = vpi_get(vpiTimePrecision, obj); vpi_printf(const_cast("%s vpiTimeUnit = %d"), namep, u); vpi_printf(const_cast(" vpiTimePrecision = %d\n"), p); } void dpii_check() { dpi_bad(); dpi_show(0); vpi_show(0); svScope smod = svGetScopeFromName("top.t"); if (!smod) { vpi_printf(const_cast("-- Cannot svGetScopeFromName\n")); } else { dpi_show(smod); } TestVpiHandle mod = vpi_handle_by_name((PLI_BYTE8*)"top.t", NULL); if (!mod) { vpi_printf(const_cast("-- Cannot vpi_find module\n")); } else { vpi_show(mod); } } verilator-5.042/test_regress/t/t_class_extern_args_bad.py0000755000542200017500000000076615101701376024313 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_event_control_prev_name_collision.v0000644000542200017500000000277115101701376026577 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module S( input reset, io_i, output io_o ); reg s; always @(posedge reset) begin if (reset) begin s <= 1'h0; end else begin s <= io_i; end end assign io_o = s; endmodule module Q( input reset_e, input reset_d, output ready_e ); wire reset_n; wire io_v; wire io_e; S e ( .io_i (), .reset (reset_e | ~reset_n), .io_o (io_e) ); S v ( .io_i (io_e), .reset (reset_e), .io_o (io_v) ); assign reset_n = ~reset_d; assign ready_e = io_v; endmodule module Test( input reset, output valid ); wire ready_e; Q q ( .reset_e (reset), .reset_d (reset), .ready_e (ready_e) ); assign valid = ready_e; endmodule module Test2( input reset, input valid ); always begin if (~reset & valid) begin $fatal; end end endmodule module Dut( input reset ); wire valid_g; Test t ( .reset (reset), .valid (valid_g) ); Test2 t2 ( .reset (reset), .valid (valid_g) ); endmodule module t (/*AUTOARG*/ ); reg [$bits(dut.reset)-1:0] reset; Dut dut ( .reset(reset) ); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_concat_or.py0000755000542200017500000000074615101701376021744 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["--lint-only"]) test.passes() verilator-5.042/test_regress/t/t_for_init_bug.v0000644000542200017500000000151515101701376022250 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs priority_mask, // Inputs muxed_requests ); parameter ARW = 7; // verilator lint_off UNOPTFLAT integer i,j; output reg [ARW-1:0] priority_mask; input [ARW-1:0] muxed_requests; always @* begin for (i=ARW-1;i>0;i=i-1) begin priority_mask[i]=1'b0; // vvvv=== note j=j not j=i; was bug for( j=j;j>=0;j=j-1) priority_mask[i]=priority_mask[j] | muxed_requests[j]; end //Bit zero is always enabled priority_mask[0]=1'b0; end endmodule // Local Variables: // verilog-auto-inst-param-value: t // End: verilator-5.042/test_regress/t/t_string_type_methods_bad.py0000755000542200017500000000076615101701376024677 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_queue_var_slice.v0000644000542200017500000000102315101701376022747 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer i = 0; integer q[$] = {0, 1}; always @(posedge clk) begin $display("%p", q[i:i+1]); q.push_back(i+2); i++; if (i >= 3) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_tri_gate_bufif1.py0000755000542200017500000000136515101701376023025 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_tri_gate.cpp" test.top_filename = "t/t_tri_gate.v" test.compile(make_top_shell=False, make_main=False, v_flags2=['+define+T_BUFIF1'], make_flags=['CPPFLAGS_ADD=-DT_BUFIF1'], verilator_flags2=["--exe", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_math_div0.py0000755000542200017500000000077515101701376021652 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--x-assign 0']) test.execute() test.passes() verilator-5.042/test_regress/t/t_gate_strength.py0000755000542200017500000000075415101701376022632 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['-bbox-unsup']) test.passes() verilator-5.042/test_regress/t/t_bitsel_wire_array_bad.out0000644000542200017500000000052515101701376024460 0ustar mahmoudyfreeshell%Error: t/t_bitsel_wire_array_bad.v:16:16: Illegal assignment of constant to unpacked array : ... note: In instance 't' 16 | assign b = a[0]; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_var_pins_bad.out0000644000542200017500000000024015101701376022565 0ustar mahmoudyfreeshell%Error: --pins-bv maximum is 65: 99 ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_var_ref_static.v0000644000542200017500000000070215101701376022572 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Make sure type errors aren't suppressable // verilator lint_off WIDTH module t; // TODO make this a proper test function void crs(const ref static i); endfunction function void rs(ref static i); endfunction endmodule verilator-5.042/test_regress/t/t_property_var_unsup.out0000644000542200017500000000115515101701376024132 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_property_var_unsup.v:18:13: Unsupported: sequence match items 18 | (valid, prevcyc = cyc) |=> (cyc == prevcyc + 1); | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_property_var_unsup.v:17:11: Unsupported: property variable declaration 17 | int prevcyc; | ^~~~~~~ %Error-UNSUPPORTED: t/t_property_var_unsup.v:24:31: Unsupported: property variable default value 24 | property with_def(int nine = 9); | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_cast_stream.py0000755000542200017500000000071415101701376022275 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.passes() verilator-5.042/test_regress/t/t_convert2string.v0000644000542200017500000000276415101701376022602 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by Peter Monsson. // SPDX-License-Identifier: Unlicense module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; wire [31:0] in = cyc; Test test (/*AUTOINST*/ // Inputs .clk (clk), .in (in[31:0])); always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule package lpcm_pkg; class lpcm_tr; int latency; int sample; function new(); latency = 0; sample = 0; endfunction function string convert2string(); return $sformatf("sample=0x%0h latency=%0d", sample, latency); endfunction endclass endpackage //internal error happens when lpcm_pkg is not imported //import lpcm_pkg::*; module Test (/*AUTOARG*/ // Inputs clk, in ); input clk; input [31:0] in; initial begin string s; lpcm_pkg::lpcm_tr tr; // internal error happens when lpcm_pkg is not imported tr = new(); tr.sample = 1; tr.latency = 2; s = tr.convert2string(); $display("hello %s", tr.convert2string()); if (s != "sample=0x1 latency=2") $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_do_while.py0000755000542200017500000000073415101701376021564 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_func_const_packed_array_bad.v0000644000542200017500000000162315101701376025256 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 module t; localparam [ 1 : 0 ] [ 31 : 0 ] P = {32'd5, 32'd1}; localparam P6 = f_add(P); localparam P14 = f_add2(2, 3, f_add(P)); localparam P24 = f_add2(7, 8, 9); initial begin // Should never get here $write("*-* All Finished *-*\n"); $finish; end function integer f_add(input [ 1 : 0 ] [ 31 : 0 ] params); f_add = params[0]+params[1]; if (f_add == 15) $fatal(2, "f_add = 15"); endfunction // Speced ok: function called from function function integer f_add2(input [31:0] a, input [31:0] b, input [31:0] c); logic [ 1 : 0 ] [ 31 : 0 ] params; params[0] = a; params[1] = b; f_add2 = f_add(params)+c; endfunction endmodule verilator-5.042/test_regress/t/t_comb_input_2.cpp0000644000542200017500000000233715101701376022502 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2022 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "verilated.h" #include "Vt_comb_input_2.h" #include "Vt_comb_input_2__Syms.h" #include int main(int argc, char** argv) { const std::unique_ptr contextp{new VerilatedContext}; contextp->debug(0); contextp->commandArgs(argc, argv); srand48(5); const std::unique_ptr topp{new VM_PREFIX}; topp->inc = 1; topp->clk = false; topp->eval(); while (!contextp->gotFinish() && contextp->time() < 100000) { contextp->timeInc(5); if (topp->clk) topp->inc += 1; topp->clk = !topp->clk; topp->eval(); } if (!contextp->gotFinish()) { vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); } return 0; } verilator-5.042/test_regress/t/t_cover_expr.py0000755000542200017500000000170115101701376022141 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap from pathlib import Path test.scenarios('simulator') test.compile(verilator_flags2=['--cc', '--coverage-expr']) test.execute() # Read the input .v file and do any CHECK_COVER requests test.inline_checks() test.run(cmd=[ os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--annotate-points", "--annotate", test.obj_dir + "/annotated", test.obj_dir + "/coverage.dat", ], verilator_run=True) top = Path(test.top_filename) test.files_identical(test.obj_dir + f"/annotated/{top.name}", test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_package_alone_bad.py0000755000542200017500000000076615101701376023356 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_local_nested_bad.py0000755000542200017500000000100415101701376024410 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_timing_func_join.v0000644000542200017500000000124515101701376023123 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; function int fun(int val); fork $display("abc"); $display("def"); join_none // Although join is illegal, join_none legal (IEEE 1800-2023 13.4) return val + 2; endfunction task tsk(); fork $display("ghi"); $display("jkl"); join_none endtask initial begin $display("$d", fun(2)); tsk(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_interface_ar2a.py0000755000542200017500000000071415101701376022635 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.passes() verilator-5.042/test_regress/t/t_param_array6.py0000755000542200017500000000073415101701376022356 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_mem_packed_assign.py0000755000542200017500000000073415101701376023423 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_force_select_bad.out0000644000542200017500000000327615101701376023415 0ustar mahmoudyfreeshell%Error: t/t_force_select_bad.v:24:5: Force left-hand-side must not have variable bit/part select (IEEE 1800-2023 10.6.2) : ... note: In instance 't' 24 | force array1[bad_index] = 1'b1; | ^~~~~ t/t_force_select_bad.v:24:18: ... Location of non-constant index 24 | force array1[bad_index] = 1'b1; | ^~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_force_select_bad.v:25:5: Release left-hand-side must not have variable bit/part select (IEEE 1800-2023 10.6.2) : ... note: In instance 't' 25 | release array1[bad_index]; | ^~~~~~~ t/t_force_select_bad.v:25:20: ... Location of non-constant index 25 | release array1[bad_index]; | ^~~~~~~~~ %Error: t/t_force_select_bad.v:26:5: Force left-hand-side must not have variable bit/part select (IEEE 1800-2023 10.6.2) : ... note: In instance 't' 26 | force vec[bad_index+:1] = 1'b1; | ^~~~~ t/t_force_select_bad.v:26:15: ... Location of non-constant index 26 | force vec[bad_index+:1] = 1'b1; | ^~~~~~~~~ %Error: t/t_force_select_bad.v:27:5: Release left-hand-side must not have variable bit/part select (IEEE 1800-2023 10.6.2) : ... note: In instance 't' 27 | release vec[bad_index+:1]; | ^~~~~~~ t/t_force_select_bad.v:27:17: ... Location of non-constant index 27 | release vec[bad_index+:1]; | ^~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_interface_virtual_bad.py0000755000542200017500000000076615101701376024313 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_trace_timing1.out0000644000542200017500000000043615101701376022673 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module t $end $var wire 32 % CLOCK_CYCLE [31:0] $end $var wire 1 # rst $end $var wire 1 $ clk $end $upscope $end $enddefinitions $end #0 1# 0$ b00000000000000000000000000001010 % #5 1$ #10 0# 0$ #15 1$ #20 0$ verilator-5.042/test_regress/t/t_interface_typedef.py0000755000542200017500000000105515101701376023447 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) if not test.vlt_all: test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_generic_modport_task_bad.v0000644000542200017500000000117215101701376026631 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 interface inf; int v; task setup(); v = 3; endtask modport mp( input v ); endinterface interface inf2; int k; endinterface module GenericModule (interface.mp a); initial begin a.setup(); end endmodule module t; inf inf_inst(); GenericModule genericModule (inf_inst); initial begin #1; if (inf_inst.v != 3) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_altera_lpm_counter.py0000755000542200017500000000114115101701376023642 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) test.compile(verilator_flags2=["--top-module", module, "--binary --no-timing"]) test.passes() verilator-5.042/test_regress/t/t_case_string2.v0000644000542200017500000000102115101701376022155 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; function automatic string broken_case(input string some_string); case(some_string) "alpha": return "alpha"; default: return "beta"; endcase endfunction initial begin $display(broken_case("gamma")); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_interface_param1.v0000644000542200017500000000172315101701376023004 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014 by Jie Xu. // SPDX-License-Identifier: CC0-1.0 //bug692 module t (/*AUTOARG*/ // Inputs clk ); input wire clk; wire [31:0] result; test_if #(.ID(3)) s(); sub_test U_SUB_TEST(s.a.b, result); // the line causing error endmodule : t // --------------------------------------------------------------------------- module sub_test ( input [31:0] b, output [31:0] c ); assign c = b; endmodule // --------------------------------------------------------------------------- interface test_if #(parameter ID = 0) (); typedef struct packed { logic a; logic [31:0] b; } aType; aType a; typedef struct packed { logic c; logic [31:0] d; } bType; bType b; modport master (input a, output b); endinterface verilator-5.042/test_regress/t/t_typedef_fwd_class.py0000755000542200017500000000073415101701376023457 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_generic_mod_param.v0000644000542200017500000000105315101701376025252 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 interface inf; int v; endinterface module GenericModule#(type T, type Y = int) (interface a); initial begin #1; if (a.v != 7) $stop; end endmodule module t; inf inf_inst(); GenericModule #(string) genericModule (inf_inst); initial begin inf_inst.v = 7; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_class_param_func_return.py0000755000542200017500000000073415101701376024671 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_foreach_noivar_bad.out0000644000542200017500000000124515101701376023737 0ustar mahmoudyfreeshell%Warning-NOEFFECT: t/t_foreach_noivar.v:17:5: foreach with no loop variable has no effect : ... note: In instance 't' 17 | foreach (array[]) begin | ^~~~~~~ ... For warning description see https://verilator.org/warn/NOEFFECT?v=latest ... Use "/* verilator lint_off NOEFFECT */" and lint_on around source to disable this message. %Warning-NOEFFECT: t/t_foreach_noivar.v:23:5: foreach with no loop variable has no effect : ... note: In instance 't' 23 | foreach (array[,,]) begin | ^~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_clk_gater.v0000644000542200017500000000732615101701376021543 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; reg reset; reg enable; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [31:0] out; // From test of Test.v // End of automatics // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; Test test (/*AUTOINST*/ // Outputs .out (out[31:0]), // Inputs .clk (clk), .reset (reset), .enable (enable), .in (in[31:0])); wire [63:0] result = {32'h0, out}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; reset <= (cyc < 5); enable <= cyc[4] || (cyc < 2); if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; `define EXPECTED_SUM 64'h01e1553da1dcf3af if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs out, // Inputs clk, reset, enable, in ); input clk; input reset; input enable; input [31:0] in; output [31:0] out; // No gating reg [31:0] d10; always @(posedge clk) begin d10 <= in; end reg displayit; `ifdef VERILATOR // Harder test initial displayit = $c1("0"); // Something that won't optimize away `else initial displayit = '0; `endif // Obvious gating + PLI reg [31:0] d20; always @(posedge clk) begin if (enable) begin d20 <= d10; // Obvious gating if (displayit) begin $display("hello!"); // Must glob with other PLI statements end end end // Reset means second-level gating reg [31:0] d30, d31a, d31b, d32; always @(posedge clk) begin d32 <= d31b; if (reset) begin d30 <= 32'h0; d31a <= 32'h0; d31b <= 32'h0; d32 <= 32'h0; // Overlaps above, just to make things interesting end else begin // Mix two outputs d30 <= d20; if (enable) begin d31a <= d30; d31b <= d31a; end end end // Multiple ORs for gater reg [31:0] d40a,d40b; always @(posedge clk) begin if (reset) begin d40a <= 32'h0; d40b <= 32'h0; end if (enable) begin d40a <= d32; d40b <= d40a; end end // Non-optimizable reg [31:0] d91, d92; reg [31:0] inverted; always @(posedge clk) begin inverted = ~d40b; if (reset) begin d91 <= 32'h0; end else begin if (enable) begin d91 <= inverted; end else begin d92 <= inverted ^ 32'h12341234; // Inverted gating condition end end end wire [31:0] out = d91 ^ d92; endmodule verilator-5.042/test_regress/t/t_waiveroutput_allgood.out0000644000542200017500000000056315101701376024425 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator output: Waivers generated with --waiver-output `verilator_config // Below are suggested waivers. You have three options: // 1. Fix the reason for the linter warning in the Verilog sources // 2. Keep the waiver permanently if you are sure it is okay // 3. Keep the waiver temporarily to suppress the output // No waivers needed - great! verilator-5.042/test_regress/t/t_lint_noreturn.v0000644000542200017500000000065115101701376022504 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; // verilator lint_off UNDRIVEN function int no_rtn(); // <--- Warning: No return endfunction int i; initial begin i = no_rtn(); if (i !== 0) $stop; $finish; end endmodule verilator-5.042/test_regress/t/t_var_pins_sc32.py0000755000542200017500000000340215101701376022440 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.pli_filename = "t/t_var_pinsizes.cpp" test.top_filename = "t/t_var_pinsizes.v" test.compile(verilator_flags2=[ "-sc -no-pins64 --trace-vcd --exe", test.pli_filename, test.t_dir + "/t_var_pinsizes.vlt" ], make_main=False) def hgrep(re): test.file_grep(os.path.join(test.obj_dir, test.vm_prefix + ".h"), re) hgrep(r'sc_core::sc_in\s+&i1;') hgrep(r'sc_core::sc_in\s+&i8;') hgrep(r'sc_core::sc_in\s+&i16;') hgrep(r'sc_core::sc_in\s+&i32;') hgrep(r'sc_core::sc_in\s>\s+&i64;') hgrep(r'sc_core::sc_in\s>\s+&i65;') hgrep(r'sc_core::sc_in\s>\s+&ibv1;') hgrep(r'sc_core::sc_in\s>\s+&ibv16;') hgrep(r'sc_core::sc_in\s>\s+&ibv1_vlt;') hgrep(r'sc_core::sc_in\s>\s+&ibv16_vlt;') hgrep(r'sc_core::sc_out\s+&o1;') hgrep(r'sc_core::sc_out\s+&o8;') hgrep(r'sc_core::sc_out\s+&o16;') hgrep(r'sc_core::sc_out\s+&o32;') hgrep(r'sc_core::sc_out\s>\s+&o64;') hgrep(r'sc_core::sc_out\s>\s+&o65;') hgrep(r'sc_core::sc_out\s>\s+&obv1;') hgrep(r'sc_core::sc_out\s>\s+&obv16;') hgrep(r'sc_core::sc_out\s>\s+&obv1_vlt;') hgrep(r'sc_core::sc_out\s>\s+&obv16_vlt;') test.execute() test.passes() verilator-5.042/test_regress/t/t_dpi_accessors.v0000644000542200017500000000453115101701376022424 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Test for using DPI as general accessors // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // // Contributed by Jeremy Bennett and Jie Xul // // This test exercises the use of DPI to access signals and registers in a // module hierarchy in a uniform fashion. See the discussion at // // https://github.com/verilator/verilator/issues/1750 // // We need to test read and write access to: // - scalars // - vectors // - array elements // - slices of vectors or array elements // // We need to test that writing to non-writable elements generates an error. // // This Verilog would run forever. It will be stopped externally by the C++ // instantiating program. // Define the width of registers and size of memory we use `define REG_WIDTH 8 `define MEM_SIZE 256 // Top module defines the accessors and instantiates a sub-module with // substantive content. module t (/*AUTOARG*/ // Inputs clk ); input clk; `include "t_dpi_accessors_macros_inc.vh" `include "t_dpi_accessors_inc.vh" // Put the serious stuff in a sub-module, so we can check hierarchical // access works OK. test_sub i_test_sub (.clk (clk)); endmodule // t // A sub-module with all sorts of goodies we would like to access module test_sub (/*AUTOARG*/ // Inputs clk ); input clk; integer i; // General counter // Elements we would like to access from outside reg a; reg [`REG_WIDTH - 1:0] b; reg [`REG_WIDTH - 1:0] mem [`MEM_SIZE - 1:0]; wire c; wire [`REG_WIDTH - 1:0] d; reg [`REG_WIDTH - 1:0] e; reg [`REG_WIDTH - 1:0] f; // Drive our wires from our registers assign c = ~a; assign d = ~b; // Initial values for registers and array initial begin a = 0; b = `REG_WIDTH'h0; for (i = 0; i < `MEM_SIZE; i++) begin mem[i] = i [`REG_WIDTH - 1:0]; end e = 0; f = 0; end // Wipe out one memory cell in turn on the positive clock edge, restoring // the previous element. We toggle the wipeout value. always @(posedge clk) begin mem[b] <= {`REG_WIDTH {a}}; mem[b - 1] <= b - 1; a <= ~a; b <= b + 1; end endmodule // test_sub verilator-5.042/test_regress/t/t_case_write1.py0000755000542200017500000000114715101701376022177 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--stats -O3 -x-assign fast"]) test.execute() test.files_identical(test.obj_dir + "/" + test.name + "_logger.log", test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_var_static_assign_decl_bad.v0000644000542200017500000000562115101701376025104 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 function static func_stat; input logic in; logic tmp = in; endfunction task static task_stat; input logic in; logic tmp = in; endtask package pkg; function static func_stat; input logic in; logic tmp = in; endfunction task static task_stat; input logic in; logic tmp = in; endtask endpackage interface iface; function static func_stat; input logic in; logic tmp = in; endfunction task static task_stat; input logic in; logic tmp = in; endtask endinterface program prog; function static func_stat; input logic in; logic tmp = in; endfunction task static task_stat; input logic in; logic tmp = in; endtask endprogram module no_warn#(PARAM = 1)(input in, input clk); typedef enum {A, B} enum_t; // Do not warn on variables under modules. logic tmp = in; // Do not warn on assignment with module var. function static func; static logic func_var = tmp; endfunction // Do not warn on constant assignments. function static func_param; static logic func_var = PARAM; static logic func_enum = A; endfunction // Do not warn on assignment referencing module I/O. function static func_module_input; logic tmp = in; endfunction // Do not warn on automatic assignment. function automatic func_auto; input logic in; logic tmp = in; endfunction // Do not warn on assignment separate from declaration. function static func_decl_and_assign; input logic in; logic tmp; tmp = in; endfunction // Do not warn on variables under blocks. initial begin logic init_tmp = in; end always @(posedge clk) begin static logic always_tmp = in; end endmodule module t(input clk); function static func_stat; input logic in; logic tmp = in; endfunction task static task_stat; input logic in; logic tmp = in; endtask function automatic func_auto_with_static; input logic in; static logic tmp = in; endfunction function static func_assign_out; output logic out; logic tmp = out; endfunction function static func_assign_expr; input logic in; logic tmp = in + 1; endfunction function static int func_assign_static_in_to_auto(input int i); automatic int tmp = i; static int foo = tmp + 1; return foo; endfunction function static int func_assign_auto_to_static(); automatic int tmp = 0; static int foo = tmp + 1; return foo; endfunction function static func_local; automatic logic loc; static logic func_var = loc; endfunction iface iface(); prog prog(); logic in; no_warn no_warn(.in(in), .clk(clk)); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_sys_plusargs.v0000644000542200017500000000747115101701376022347 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; integer p_i; // signal type IData reg [15:0] p_s; // signal type SData reg [7:0] p_c; // signal type CData real p_r; // signal type double reg [7*8:1] p_str; string sv_str; reg [7*8:1] p_in; string sv_in; integer unread; // never read initial begin if ($test$plusargs("PLUS")!==1) $stop; if ($test$plusargs("PLUSNOT")!==0) $stop; if ($test$plusargs("PL")!==1) $stop; //if ($test$plusargs("")!==1) $stop; // Simulators differ in this answer if ($test$plusargs("NOTTHERE")!==0) $stop; sv_in = "PLUS"; `ifdef VERILATOR if ($c1(0)) sv_in = "NEVER"; // Prevent constant propagation `endif if ($test$plusargs(sv_in)!==1) $stop; p_i = 10; if ($value$plusargs("NOTTHERE%d", p_i) !== 0) $stop; if ($value$plusargs("NOTTHERE%0d", p_i) !== 0) $stop; if (p_i !== 10) $stop; p_i = 0; if ($value$plusargs("INT=%d", p_i) !== 1) $stop; if (p_i !== 32'd1234) $stop; p_i = 0; if ($value$plusargs("INT=%0d", p_i) !== 1) $stop; if (p_i !== 32'd1234) $stop; p_i = 0; if ($value$plusargs("INT=%H", p_i)!==1) $stop; // tests uppercase % also if (p_i !== 32'h1234) $stop; p_i = 0; // Check octal and WIDTH if (!$value$plusargs("INT=%o", p_i)) $stop; if (p_i !== 32'o1234) $stop; // Check handling of 'SData' type signals (issue #1592) p_s = 0; if (!$value$plusargs("INT=%d", p_s)) $stop; if (p_s !== 16'd1234) $stop; // Check handling of 'CData' type signals (issue #1592) p_c = 0; if (!$value$plusargs("INT=%d", p_c)) $stop; if (p_c !== 8'd210) $stop; // Check handling of 'double' type signals (issue #1619) p_r = 0; if (!$value$plusargs("REAL=%e", p_r)) $stop; $display("r='%e'", p_r); if (p_r !== 1.2345) $stop; p_r = 0; if (!$value$plusargs("REAL=%f", p_r)) $stop; $display("r='%f'", p_r); if (p_r !== 1.2345) $stop; p_r = 0; if (!$value$plusargs("REAL=%g", p_r)) $stop; $display("r='%g'", p_r); if (p_r !== 1.2345) $stop; p_str = "none"; if ($value$plusargs("IN%s", p_str)!==1) $stop; $display("str='%s'",p_str); if (p_str !== "T=1234") $stop; sv_str = "none"; if ($value$plusargs("IN%s", sv_str)!==1) $stop; $display("str='%s'",sv_str); if (sv_str != "T=1234") $stop; sv_str = "none"; $value$plusargs("IN%s", sv_str); $display("str='%s'",sv_str); if (sv_str != "T=1234") $stop; p_in = "IN%s"; `ifdef VERILATOR p_in = $c(p_in); // Prevent constant propagation `endif sv_str = "none"; if ($value$plusargs(p_in, sv_str)!==1) $stop; $display("str='%s'",sv_str); if (sv_str != "T=1234") $stop; sv_str = "none"; if ($value$plusargs("IP%%P%b", p_i)!==1) $stop; $display("str='%s'",sv_str); if (p_i != 'b101) $stop; sv_in = "INT=%d"; `ifdef VERILATOR if ($c1(0)) sv_in = "NEVER"; // Prevent constant propagation `endif p_i = 0; if ($value$plusargs(sv_in, p_i)!==1) $stop; $display("i='%d'",p_i); if (p_i !== 32'd1234) $stop; // bug3131 - really "if" side effect test p_i = 0; if ($value$plusargs("INT=%d", p_i)) ; if (p_i !== 32'd1234) $stop; // bug5127 - assign side effect test p_i = 0; p_r = 0; unread = $value$plusargs("INT=%d", p_i); unread = $value$plusargs("REAL=%e", p_r); if (p_i !== 32'd1234) $stop; if (p_r !== 1.2345) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_lint_badvltpragma_bad.v0000644000542200017500000000047315101701376024104 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; // verilator lintt_off WIDTH //<--- Warning (lint_off misspelled) bit one = 2; endmodule verilator-5.042/test_regress/t/t_order_clkinst.py0000755000542200017500000000142315101701376022630 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') # On Verilator, we expect this to pass. # # TBD: Will event-based simulators match Verilator's behavior # closely enough to pass the same test? # If not -- probably we should switch this to be vlt-only. test.compile(verilator_flags2=["--trace-vcd", "-fno-dfg"]) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_trace_complex_threads_1.py0000755000542200017500000000220715101701376024546 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_complex.v" test.golden_filename = "t/t_trace_complex.out" test.compile(verilator_flags2=['--cc --trace-vcd --trace-threads 1']) test.execute() test.file_grep(test.trace_filename, r' v_strp ') test.file_grep(test.trace_filename, r' v_strp_strp ') test.file_grep(test.trace_filename, r' v_arrp ') test.file_grep(test.trace_filename, r' v_arrp_arrp ') test.file_grep(test.trace_filename, r' v_arrp_strp ') test.file_grep(test.trace_filename, r' v_arru\[') test.file_grep(test.trace_filename, r' v_arru_arru\[') test.file_grep(test.trace_filename, r' v_arru_arrp\[') test.file_grep(test.trace_filename, r' v_arru_strp\[') test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_enum_int.py0000755000542200017500000000103615101701376021604 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--debug", "--debugi", "0", "--dumpi-tree", "0"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_forceable_var.v0000644000542200017500000000466615101701376022406 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module t ( input wire clk, input wire rst, output reg [31:0] cyc ); always @(posedge clk) begin if (rst) begin cyc <= 0; end else begin cyc <= cyc +1; end end reg tmp_1; reg [7:0] tmp_8; always @(posedge clk) begin if (rst) begin tmp_1 <= 0; tmp_8 <= 0; end else begin tmp_1 <= cyc[0]; tmp_8 <= cyc[1 +: 8]; end end `ifdef CMT reg var_1 /* verilator forceable */; reg [7:0] var_8 /* verilator forceable */; `else reg var_1; reg [7:0] var_8; `endif always @* var_1 = tmp_1; always @* var_8 = tmp_8; reg obs_1; reg [7:0] obs_8; always @* obs_1 = var_1; always @* obs_8 = var_8; always @ (posedge clk) begin $display("%d: %x %x", cyc, obs_8, obs_1); if (!rst) begin case (cyc) 0: begin // Reset values `checkh (obs_1, 0); `checkh (obs_8, 0); end 13: begin `checkh (obs_1, 1); `checkh ({1'b0, obs_8}, (cyc[0 +: 9] - 1) >> 1); end 14: begin `checkh (obs_1, 1); `checkh (obs_8, 8'hf5); end 15: begin `checkh (obs_1, 0); `checkh (obs_8, 8'hf5); end 16, 17: begin `checkh (obs_1, 0); `checkh (obs_8, 8'h5f); end 18: begin `checkh (obs_1, ~cyc[0]); `checkh (obs_8, 8'h5f); end 20, 21: begin `checkh (obs_1, 1); `checkh (obs_8, 8'h5a); end 22, 23: begin `checkh (obs_1, 0); `checkh (obs_8, 8'ha5); end default: begin `checkh ({obs_8, obs_1}, cyc[0 +: 9] - 1); end endcase end if (cyc == 30) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_time_sc_bad_mt.py0000755000542200017500000000135315101701376022721 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vltmt') test.top_filename = "t/t_time_sc.v" test.sc_time_resolution = 'SC_NS' test.compile( verilator_flags2=[ '-sc', '-timescale 1ps/1ps', # Mismatch w/sc_time_resolution '+define+TEST_EXPECT=2us' ], threads=2) test.execute(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_func_dotted_inl2.vlt0000644000542200017500000000047015101701376023363 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. // SPDX-License-Identifier: CC0-1.0 `verilator_config inline -module "global_mod" inline -module "ma" no_inline -module "mb" inline -module "mc" verilator-5.042/test_regress/t/t_dump_dfg.py0000755000542200017500000000115715101701376021557 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') # For code coverage of graph dumping, so does not matter much what the input is test.top_filename = "t/t_bench_mux4k.v" test.compile(verilator_flags2=["--dump-dfg", "--dumpi-dfg 9"]) test.passes() verilator-5.042/test_regress/t/t_output_groups.py0000755000542200017500000000175315101701376022733 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(verilator_flags2=["--output-groups", "2"]) test.execute() # Check that only vm_classes_*.cpp are to be compiled test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + "_classes.mk", "Foo") test.file_grep(test.obj_dir + "/" + test.vm_prefix + "_classes.mk", "vm_classes_Slow_1") test.file_grep(test.obj_dir + "/" + test.vm_prefix + "_classes.mk", "vm_classes_1") test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + "_classes.mk", "vm_classes_Slow_2") test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + "_classes.mk", "vm_classes_2") test.passes() verilator-5.042/test_regress/t/t_flag_build_jobs_bad.py0000755000542200017500000000113415101701376023700 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_flag_werror.v" test.lint(fails=True, verilator_flags=["--build-jobs -1 --build"], expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_vlt_warn_bad.out0000644000542200017500000000104315101701376022602 0ustar mahmoudyfreeshell%Warning-WIDTHTRUNC: t/t_vlt_warn.v:21:33: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CONST '2'h3' generates 2 bits. : ... note: In instance 't' 21 | reg width_warn3_var_line20 = 2'b11; | ^~~~~ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_timing_func_fork_bad.py0000755000542200017500000000110415101701376024113 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(fails=True, verilator_flags2=["--binary -Wno-UNOPTFLAT"], expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_fork_label.v0000644000542200017500000000131315101701376021676 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin // Label checks begin : b1 end : b1 // b2 : begin end : b2 // With no statements this is a NOP fork : f1 join : f1 // f2: fork join_any : f2 // fork join_none // With one statement this is supported and optimized to a begin/end fork : fblk begin $write("*-* All Finished *-*\n"); $finish; end join : fblk end endmodule verilator-5.042/test_regress/t/t_sv_bus_mux_demux.v0000644000542200017500000001644215101701376023203 0ustar mahmoudyfreeshell//////////////////////////////////////////////////////////////////////////////// // // // This file is placed into the Public Domain, for any use, without warranty. // // 2012 by Iztok Jeras // // SPDX-License-Identifier: CC0-1.0 // // // //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// // // // This testbench contains a bus source and a bus drain. The source creates // // address and data bus values, while the drain is the final destination of // // such pairs. All source and drain transfers are logged into memories, which // // are used at the end of simulation to check for data transfer correctness. // // Inside the RLT wrapper there is a multiplexer and a demultiplexer, they // // bus transfers into a 8bit data stream and back. Both stream input and // // output are exposed, they are connected together into a loopback. // // // // ----------- --------------------- // // | bso_mem | | wrap | // // ----------- | | // // ----------- | | ----------- | // // | bsi src | ------------> | -> | mux | -> | -> - sto // // ----------- | ----------- | \ // // | | | loopback // // ----------- | ----------- | / // // | bso drn | <------------ | <- | demux | <- | <- - sti // // ----------- | | ----------- | // // ----------- | | // // | bso_mem | | | // // ----------- --------------------- // // // // PROTOCOL: // // // // The 'vld' signal is driven by the source to indicate valid data is // // available, 'rdy' is used by the drain to indicate is is ready to accept // // valid data. A data transfer only happens if both 'vld' & 'rdy' are active. // // // //////////////////////////////////////////////////////////////////////////////// `timescale 1ns/1ps // include RTL files `include "t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv" `include "t_sv_bus_mux_demux/sv_bus_mux_demux_demux.sv" `include "t_sv_bus_mux_demux/sv_bus_mux_demux_mux.sv" `include "t_sv_bus_mux_demux/sv_bus_mux_demux_wrap.sv" module t (/*AUTOARG*/ // Inputs clk ); input clk; parameter SIZ = 10; // system signals //logic clk = 1'b1; // clock logic rst = 1'b1; // reset integer rst_cnt = 0; // input bus logic bsi_vld; // valid (chip select) logic [31:0] bsi_adr; // address logic [31:0] bsi_dat; // data logic bsi_rdy; // ready (acknowledge) logic bsi_trn; // data transfer logic [31:0] bsi_mem [SIZ]; // output stream logic sto_vld; // valid (chip select) logic [7:0] sto_bus; // data bus logic sto_rdy; // ready (acknowledge) // input stream logic sti_vld; // valid (chip select) logic [7:0] sti_bus; // data bus logic sti_rdy; // ready (acknowledge) // output bus logic bso_vld; // valid (chip select) logic [31:0] bso_adr; // address logic [31:0] bso_dat; // data logic bso_rdy; // ready (acknowledge) logic bso_trn; // data transfer logic [31:0] bso_mem [SIZ]; integer bso_cnt = 0; //////////////////////////////////////////////////////////////////////////////// // clock and reset //////////////////////////////////////////////////////////////////////////////// // clock toggling //always #5 clk = ~clk; // reset is removed after a delay always @ (posedge clk) begin rst_cnt <= rst_cnt + 1; rst <= rst_cnt <= 3; end // reset is removed after a delay always @ (posedge clk) if (bso_cnt == SIZ) begin if (bsi_mem === bso_mem) begin $write("*-* All Finished *-*\n"); $finish(); end else begin $display ("FAILED"); $stop(); end end //////////////////////////////////////////////////////////////////////////////// // input data generator //////////////////////////////////////////////////////////////////////////////// // input data transfer assign bsi_trn = bsi_vld & bsi_rdy; // valid (for SIZ transfers) always @ (posedge clk, posedge rst) if (rst) bsi_vld = 1'b0; else bsi_vld = (bsi_adr < SIZ); // address (increments every transfer) always @ (posedge clk, posedge rst) if (rst) bsi_adr <= 32'h00000000; else if (bsi_trn) bsi_adr <= bsi_adr + 'd1; // data (new random value generated after every transfer) always @ (posedge clk, posedge rst) if (rst) bsi_dat <= 32'h00000000; else if (bsi_trn) bsi_dat <= $random(); // storing transferred data into memory for final check always @ (posedge clk) if (bsi_trn) bsi_mem [bsi_adr] <= bsi_dat; //////////////////////////////////////////////////////////////////////////////// // RTL instance //////////////////////////////////////////////////////////////////////////////// sv_bus_mux_demux_wrap wrap ( // system signals .clk (clk), .rst (rst), // input bus .bsi_vld (bsi_vld), .bsi_adr (bsi_adr), .bsi_dat (bsi_dat), .bsi_rdy (bsi_rdy), // output stream .sto_vld (sto_vld), .sto_bus (sto_bus), .sto_rdy (sto_rdy), // input stream .sti_vld (sti_vld), .sti_bus (sti_bus), .sti_rdy (sti_rdy), // output bus .bso_vld (bso_vld), .bso_adr (bso_adr), .bso_dat (bso_dat), .bso_rdy (bso_rdy) ); // stream output from mux is looped back into stream input for demux assign sti_vld = sto_vld; assign sti_bus = sto_bus; assign sto_rdy = sti_rdy; //////////////////////////////////////////////////////////////////////////////// // output data monitor //////////////////////////////////////////////////////////////////////////////// // input data transfer assign bso_trn = bso_vld & bso_rdy; // output transfer counter used to end the test always @ (posedge clk, posedge rst) if (rst) bso_cnt <= 0; else if (bso_trn) bso_cnt <= bso_cnt + 1; // storing transferred data into memory for final check always @ (posedge clk) if (bso_trn) bso_mem [bso_adr] <= bso_dat; // every output transfer against expected value stored in memory always @ (posedge clk) if (bso_trn && (bsi_mem [bso_adr] !== bso_dat)) $display ("@%08h i:%08h o:%08h", bso_adr, bsi_mem [bso_adr], bso_dat); // ready is active for SIZ transfers always @ (posedge clk, posedge rst) if (rst) bso_rdy = 1'b0; else bso_rdy = 1'b1; endmodule verilator-5.042/test_regress/t/t_flag_threads_dpi_bad.out0000644000542200017500000000033615101701376024231 0ustar mahmoudyfreeshell%Error: Unknown setting for --threads-dpi: 'bad_one' ... Suggest 'all', 'none', or 'pure' ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_func_task_bad2.out0000644000542200017500000000124515101701376023011 0ustar mahmoudyfreeshell%Error-FUNCTIMECTL: t/t_func_task_bad2.v:14:5: Functions cannot invoke tasks (IEEE 1800-2023 13.4) : ... note: In instance 't' 14 | a_task(1'b0); | ^~~~~~ : ... Suggest make caller 'function func_calls_task' a task 13 | function void func_calls_task; | ^~~~~~~~~~~~~~~ : ... Or, suggest make called 'task a_task' a function void 9 | task a_task; | ^~~~~~ ... For error description see https://verilator.org/warn/FUNCTIMECTL?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_vpi_package.cpp0000644000542200017500000001502415101701376022370 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #ifdef IS_VPI #include "sv_vpi_user.h" #include #else #include "verilated.h" #include "verilated_vcd_c.h" #include "verilated_vpi.h" #include "Vt_vpi_package.h" #include "Vt_vpi_package__Dpi.h" #include "svdpi.h" #endif #include #include #include extern "C" { #include } // These require the above. Comment prevents clang-format moving them #include "TestSimulator.h" #include "TestVpi.h" extern "C" { int count_params(TestVpiHandle& handle, int expectedParams) { TestVpiHandle it = vpi_iterate(vpiParameter, handle); CHECK_RESULT_NZ(it) int params = 0; while (true) { TestVpiHandle handle = vpi_scan(it); if (!handle) break; const int vpi_type = vpi_get(vpiType, handle); CHECK_RESULT(vpi_type, vpiParameter); params++; } it.freed(); CHECK_RESULT(params, expectedParams); return 0; } int check_handle(char* name, vpiHandle scopeHandle) { const TestVpiHandle handle = vpi_handle_by_name(name, scopeHandle); CHECK_RESULT_NZ(handle) return 0; } int mon_check() { #ifdef TEST_VERBOSE printf("-mon_check()\n"); #endif TestVpiHandle it = vpi_iterate(vpiModule, NULL); CHECK_RESULT_NZ(it) bool found_t = false; while (true) { TestVpiHandle handle = vpi_scan(it); if (handle == NULL) break; CHECK_RESULT_CSTR("t", vpi_get_str(vpiName, handle)) CHECK_RESULT_Z(found_t) found_t = true; } it.freed(); CHECK_RESULT_NZ(found_t); it = vpi_iterate(vpiInstance, NULL); CHECK_RESULT_NZ(it) TestVpiHandle pkgHandle = NULL; TestVpiHandle tHandle = NULL; TestVpiHandle unitHandle = NULL; while (true) { TestVpiHandle handle = vpi_scan(it); if (handle == NULL) break; const char* name = vpi_get_str(vpiName, handle); const char* fullname = vpi_get_str(vpiFullName, handle); if (!strcmp("t", name)) { CHECK_RESULT_CSTR("t", fullname) CHECK_RESULT_Z(tHandle) tHandle = handle; handle.freed(); } else if (!strcmp("somepackage", name)) { CHECK_RESULT_CSTR("somepackage::", fullname) CHECK_RESULT_Z(pkgHandle) pkgHandle = handle; handle.freed(); } else if (!strcmp("$unit", name)) { CHECK_RESULT_CSTR("$unit::", fullname) CHECK_RESULT_Z(unitHandle) unitHandle = handle; handle.freed(); } else { CHECK_RESULT_NZ(0) } } it.freed(); CHECK_RESULT_NZ(pkgHandle) CHECK_RESULT_NZ(tHandle) CHECK_RESULT_NZ(unitHandle) CHECK_RESULT_Z(count_params(unitHandle, 1)); CHECK_RESULT_Z(count_params(pkgHandle, 2)); CHECK_RESULT_Z(count_params(tHandle, 6)); CHECK_RESULT_Z(check_handle(const_cast("someOtherInt"), tHandle)) CHECK_RESULT_Z(check_handle(const_cast("t.someOtherInt"), NULL)) CHECK_RESULT_Z(check_handle(const_cast("$root.t.someOtherInt"), NULL)) CHECK_RESULT_Z(check_handle(const_cast("someString"), tHandle)) CHECK_RESULT_Z(check_handle(const_cast("t.someString"), NULL)) CHECK_RESULT_Z(check_handle(const_cast("someInt"), pkgHandle)) CHECK_RESULT_Z(check_handle(const_cast("somepackage::someInt"), NULL)) CHECK_RESULT_Z(check_handle(const_cast("dollarUnitInt"), unitHandle)) CHECK_RESULT_Z(check_handle(const_cast("$unit::dollarUnitInt"), NULL)) CHECK_RESULT_Z(check_handle(const_cast("somepackage"), NULL)) return 0; // Ok } } //====================================================================== #ifdef IS_VPI static int mon_check_vpi() { TestVpiHandle href = vpi_handle(vpiSysTfCall, 0); s_vpi_value vpi_value; vpi_value.format = vpiIntVal; vpi_value.value.integer = mon_check(); vpi_put_value(href, &vpi_value, NULL, vpiNoDelay); return 0; } static s_vpi_systf_data vpi_systf_data[] = {{vpiSysFunc, vpiIntFunc, (PLI_BYTE8*)"$mon_check", (PLI_INT32(*)(PLI_BYTE8*))mon_check_vpi, 0, 0, 0}, 0}; // cver entry void vpi_compat_bootstrap(void) { p_vpi_systf_data systf_data_p; systf_data_p = &(vpi_systf_data[0]); while (systf_data_p->type != 0) vpi_register_systf(systf_data_p++); } // icarus entry void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0}; #else int main(int argc, char** argv) { const std::unique_ptr contextp{new VerilatedContext}; uint64_t sim_time = 1100; contextp->debug(0); contextp->commandArgs(argc, argv); // We're going to be checking for these errors so don't crash out contextp->fatalOnVpiError(0); { // Construct and destroy const std::unique_ptr topp{ new VM_PREFIX{contextp.get(), // Note null name - we're flattening it out ""}}; } // Test second construction const std::unique_ptr topp{new VM_PREFIX{contextp.get(), // Note null name - we're flattening it out ""}}; #ifdef VERILATOR #ifdef TEST_VERBOSE contextp->scopesDump(); #endif #endif #if VM_TRACE contextp->traceEverOn(true); VL_PRINTF("Enabling waves...\n"); VerilatedVcdC* tfp = new VerilatedVcdC; topp->trace(tfp, 99); tfp->open(STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); #endif topp->eval(); contextp->timeInc(10); while (contextp->time() < sim_time && !contextp->gotFinish()) { contextp->timeInc(1); topp->eval(); VerilatedVpi::callValueCbs(); // mon_do(); #if VM_TRACE if (tfp) tfp->dump(contextp->time()); #endif } if (!contextp->gotFinish()) { vl_fatal(FILENM, __LINE__, "main", "%Error: Timeout; never got a $finish"); } topp->final(); #if VM_TRACE if (tfp) tfp->close(); #endif return 0; } #endif verilator-5.042/test_regress/t/t_case_group.v0000644000542200017500000000103615101701376021727 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014 by Jonathon Donaldson. // SPDX-License-Identifier: CC0-1.0 module t ( input i_clk, input [6:0] i_input, output logic o_output ); always_ff @(posedge i_clk) // verilator lint_off CASEINCOMPLETE case (i_input) 7'(92+2), 7'(92+3): o_output <= 1'b1; endcase initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_trace_off_cc.py0000755000542200017500000000121115101701376022356 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_ena.v" test.compile(verilator_flags2=['-notrace']) test.execute() if test.vlt_all: if os.path.exists(test.trace_filename): test.error("Tracing should be off") test.passes() verilator-5.042/test_regress/t/t_detectarray_3.py0000755000542200017500000000103115101701376022512 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["-Wno-UNOPTFLAT", "-Wno-WIDTH", "-fno-dfg"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_param_genblk.py0000755000542200017500000000075215101701376024434 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_do_not_convert_to_comb.v0000644000542200017500000000157115101701376024330 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 module t ( clk, input wire i, output reg o_0, output reg o_1, output reg o_2, output reg o_3, output reg o_4, output reg o_5 ); input clk; reg a = 0; reg b = 0; event e; // We must not convert these blocks into combinational blocks always @(i) begin a <= ~a; o_0 = i; end always @(i) begin force b = 1; o_1 = i; end always @(i) begin release b; o_2 = i; end always @(i) begin -> e; o_3 = i; end always @(i) begin ->> e; o_4 = i; end always @(i) begin $display("Hello"); o_5 = i; end endmodule verilator-5.042/test_regress/t/t_lint_latch_4.v0000644000542200017500000000134215101701376022144 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module for issue #2938 // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2021 by Julien Margetts (Originally provided by YanJiun) // SPDX-License-Identifier: Unlicense module test ( input [2:0] a, input [3:0] c, output reg [7:0] o1, output reg [7:0] o2 ); integer i; always @ (*) begin case(a) {3'b000}: o1 = 8'd1; {3'b001}: for(i=0;i<4;i=i+1) o1[i*2+:2] = 2'(c[i]); {3'b010}: o1 = 8'd3; {3'b011}: o1 = 8'd4; default : o1 = 0; endcase end always_comb begin unique if (a[0]) o2 = 1; else if (a[1]) o2 = 2; else o2 = 3; end endmodule verilator-5.042/test_regress/t/t_interface_param_another_bad.py0000755000542200017500000000076615101701376025445 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_trace_cat.cpp0000644000542200017500000000343415101701376022046 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include #include #include VM_PREFIX_INCLUDE #include "TestCheck.h" int errors = 0; unsigned long long main_time = 0; double sc_time_stamp() { return (double)main_time; } const char* trace_name() { static char name[1000]; VL_SNPRINTF(name, 1000, VL_STRINGIFY(TEST_OBJ_DIR) "/simpart_%04d.vcd", (int)main_time); return name; } int main(int argc, char** argv) { Verilated::debug(0); Verilated::traceEverOn(true); Verilated::commandArgs(argc, argv); std::unique_ptr top{new VM_PREFIX{"top"}}; std::unique_ptr tfp{new VerilatedVcdC}; top->trace(tfp.get(), 99); // Test for traceCapable - randomly-ish selected this test TEST_CHECK_EQ(top->traceCapable, true); tfp->open(trace_name()); top->clk = 0; while (main_time < 190) { // Creates 2 files top->clk = !top->clk; top->eval(); if ((main_time % 100) == 0) { #if defined(T_TRACE_CAT) tfp->openNext(true); #elif defined(T_TRACE_CAT_REOPEN) tfp->close(); tfp->open(trace_name()); #elif defined(T_TRACE_CAT_RENEW) tfp->close(); tfp.reset(new VerilatedVcdC); top->trace(tfp.get(), 99); tfp->open(trace_name()); #else #error "Unknown test" #endif } tfp->dump((unsigned int)(main_time)); ++main_time; } tfp->close(); top->final(); tfp.reset(); top.reset(); printf("*-* All Finished *-*\n"); return errors; } verilator-5.042/test_regress/t/t_randomize_method_bad.v0000644000542200017500000000066515101701376023745 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls1; function int randomize; return 1; endfunction endclass class Cls2; function void randomize(int x); endfunction function void srandom(int seed); endfunction endclass module t; endmodule verilator-5.042/test_regress/t/t_profc.py0000755000542200017500000000273315101701376021104 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap import platform test.scenarios('vlt') test.top_filename = "t_prof.v" if re.search(r'clang', test.cxx_version) and 'aarch64' in platform.processor(): test.skip("Known compiler profile issues on clang aarch64") if platform.libc_ver()[0] != "glibc": test.skip("The test depends on GMON_OUT_PREFIX which is glibc-specific") test.compile(verilator_flags2=["--stats --prof-c +define+T_PROF"]) # TODO below might no longer be required as configure checks for -pg if 'VERILATOR_TEST_NO_GPROF' in os.environ: test.skip("Skipping due to VERILATOR_TEST_NO_GPROF") for filename in glob.glob(test.obj_dir + "/gmon.out.*"): test.unlink_ok(filename) test.setenv('GMON_OUT_PREFIX', test.obj_dir + "/gmon.out") test.execute() gmon_path = None for filename in glob.glob(test.obj_dir + "/gmon.out.*"): gmon_path = filename if not gmon_path: test.error("Profiler did not create a gmon.out") gmon_base = re.sub(r'.*[/\\]', '', gmon_path) test.run( cmd=["cd " + test.obj_dir + " && gprof " + test.vm_prefix + " " + gmon_base + " > gprof.log"], check_finished=False) test.passes() verilator-5.042/test_regress/t/t_hierarchy_unnamed.v0000644000542200017500000000067615101701376023276 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Chandan Egbert. // SPDX-License-Identifier: CC0-1.0 module sub(); endmodule module t(input logic a, input logic b, output logic x, output logic y); always_comb begin integer i; x = a; end sub u0(); always_comb begin integer j; y = b; end endmodule verilator-5.042/test_regress/t/t_lint_unusedloop_removed_bad.py0000755000542200017500000000107015101701376025536 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename, verilator_flags2=["--top-module t", "-Wall"]) test.passes() verilator-5.042/test_regress/t/t_unpacked_concat.py0000755000542200017500000000073415101701376023113 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_hier_block_threads_bad.vlt0000644000542200017500000000046015101701376024561 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 `verilator_config hier_workers -module "Core" -workers `WORKERS hier_workers -module "SubCore" -workers `WORKERS verilator-5.042/test_regress/t/t_randomize_rand_mode_constr.v0000644000542200017500000000633415101701376025176 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Foo; rand int a; rand int b; endclass class Bar; rand int x; rand Foo foo; constraint x_gt_0 {x > 0;}; function new; foo = new; endfunction endclass class Qux extends Bar; rand int y; constraint y_gt_x {y > x;}; constraint y_lt_10 {y < 10;}; function bit get_rand_mode(); return bit'(y.rand_mode()); endfunction function void test; logic ok = 0; x.rand_mode(1); if (x.rand_mode != 1) $stop; // Note no rand_mode parens if (get_rand_mode() != 1) $stop; y.rand_mode(0); if (y.rand_mode() != 0) $stop; // Note has rand_mode parens foo.a.rand_mode(0); if (foo.a.rand_mode != 0) $stop; // Note no rand_mode parens foo.b.rand_mode(1); if (foo.b.rand_mode() != 1) $stop; // Note has rand_mode parens for (int i = 0; i < 20; ++i) begin x = 4; y = 8; foo.a = 15; foo.b = 16; void'(randomize()); if (x >= y) $stop; if (x != 4) ok = 1; if (y != 8) $stop; if (foo.a != 15) $stop; if (foo.b != 16) ok = 1; end if (!ok) $stop; foo.b = 16; foo.rand_mode(0); if (foo.rand_mode == 1) $stop; if (foo.a.rand_mode == 1) $stop; if (foo.b.rand_mode == 0) $stop; void'(randomize()); if (foo.a != 15) $stop; if (foo.b != 16) $stop; ok = 0; foo.rand_mode(1); if (foo.rand_mode == 0) $stop; for (int i = 0; i < 20; ++i) begin foo.a = 23; foo.b = 42; void'(randomize()); if (foo.a != 23) $stop; if (foo.b != 42) ok = 1; end if (!ok) $stop; endfunction endclass class Baz; Qux qux; function new(); qux = new; endfunction function void test; qux.x = 42; qux.rand_mode(0); if (qux.x.rand_mode == 1) $stop; void'(qux.randomize()); if (qux.x != 42) $stop; endfunction endclass class Quux; rand int x; endclass module t; initial begin logic ok = 0; int res; Baz baz = new; Qux qux = new; Quux quux = new; baz.test; qux.test; qux.x.rand_mode(0); if (qux.x.rand_mode == 1) $stop; qux.y.rand_mode(1); if (qux.y.rand_mode == 0) $stop; qux.foo.a.rand_mode(1); if (qux.foo.a.rand_mode == 0) $stop; qux.foo.b.rand_mode(0); if (qux.foo.b.rand_mode == 1) $stop; for (int i = 0; i < 20; ++i) begin qux.x = 5; qux.y = 8; qux.foo.a = 13; qux.foo.b = 21; res = qux.randomize() with {y > 5;}; if (qux.x >= qux.y) $stop; if (qux.y <= 5) $stop; if (qux.x != 5) $stop; if (qux.y != 8) ok = 1; if (qux.foo.a != 13) ok = 1; if (qux.foo.b != 21) $stop; end if (!ok) $stop; quux.x.rand_mode(0); quux.x = 1000; res = quux.randomize() with {x != 1000;}; if (quux.x != 1000) $stop; quux.rand_mode(1); res = quux.randomize() with {x != 1000;}; if (quux.x == 1000) $stop; qux.x = 1024; qux.y = 512; qux.rand_mode(0); if (qux.randomize() == 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_interface_parameter_access.v0000644000542200017500000001010515101701376025116 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Interface parameter getter // // A test of the import parameter used with modport // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Todd Strader // SPDX-License-Identifier: CC0-1.0 interface test_if #(parameter integer FOO = 1); // Interface variable logic data; localparam integer BAR = FOO + 1; // Modport modport mp( import getFoo, output data ); function integer getFoo (); return FOO; endfunction endinterface // test_if function integer identity (input integer x); return x; endfunction module t (/*AUTOARG*/ // Inputs clk ); input clk; test_if #( .FOO (identity(5)) ) the_interface (); test_if #( .FOO (identity(7)) ) array_interface [1:0] (); testmod testmod_i (.clk (clk), .intf (the_interface), .intf_no_mp (the_interface), .intf_array (array_interface) ); // verilator lint_off HIERPARAM localparam THE_TOP_FOO = the_interface.FOO; localparam THE_TOP_FOO_BITS = $bits({the_interface.FOO, the_interface.FOO}); localparam THE_ARRAY_FOO = array_interface[0].FOO; // verilator lint_on HIERPARAM initial begin if (THE_TOP_FOO != 5) begin $display("%%Error: THE_TOP_FOO = %0d", THE_TOP_FOO); $stop; end if (THE_TOP_FOO_BITS != 64) begin $display("%%Error: THE_TOP_FOO_BITS = %0d", THE_TOP_FOO_BITS); $stop; end if (THE_ARRAY_FOO != 7) begin $display("%%Error: THE_ARRAY_FOO = %0d", THE_ARRAY_FOO); $stop; end end endmodule module testmod #(parameter SOME_PARAM = 789) ( input clk, test_if.mp intf, test_if intf_no_mp, test_if.mp intf_array [1:0] ); test_if #(.FOO (intf.FOO)) some_other_intf (); // verilator lint_off HIERPARAM localparam THE_FOO = intf.FOO; localparam THE_OTHER_FOO = intf_no_mp.FOO; localparam THE_ARRAY_FOO = intf_array[0].FOO; localparam THE_BAR = intf.BAR; localparam THE_OTHER_BAR = intf_no_mp.BAR; localparam THE_ARRAY_BAR = intf_array[0].BAR; // verilator lint_on HIERPARAM always @(posedge clk) begin if (THE_FOO != 5) begin $display("%%Error: THE_FOO = %0d", THE_FOO); $stop; end if (some_other_intf.FOO != 5) begin $display("%%Error: some_other_intf.FOO = %0d", some_other_intf.FOO); $stop; end if (THE_OTHER_FOO != 5) begin $display("%%Error: THE_OTHER_FOO = %0d", THE_OTHER_FOO); $stop; end if (THE_ARRAY_FOO != 7) begin $display("%%Error: THE_ARRAY_FOO = %0d", THE_ARRAY_FOO); $stop; end if (intf.FOO != 5) begin $display("%%Error: intf.FOO = %0d", intf.FOO); $stop; end if (intf_no_mp.FOO != 5) begin $display("%%Error: intf_no_mp.FOO = %0d", intf_no_mp.FOO); $stop; end if (intf_array[0].FOO != 7) begin $display("%%Error: intf_array[0].FOO = %0d", intf_array[0].FOO); $stop; end // if (i.getFoo() != 5) begin // $display("%%Error: i.getFoo() = %0d", i.getFoo()); // $stop; // end if (THE_BAR != 6) begin $display("%%Error: THE_BAR = %0d", THE_BAR); $stop; end if (THE_OTHER_BAR != 6) begin $display("%%Error: THE_OTHER_BAR = %0d", THE_OTHER_BAR); $stop; end if (THE_ARRAY_BAR != 8) begin $display("%%Error: THE_ARRAY_BAR = %0d", THE_ARRAY_BAR); $stop; end if (intf.BAR != 6) begin $display("%%Error: intf.BAR = %0d", intf.BAR); $stop; end if (intf_no_mp.BAR != 6) begin $display("%%Error: intf_no_mp.BAR = %0d", intf_no_mp.BAR); $stop; end if (intf_array[0].BAR != 8) begin $display("%%Error: intf_array[0].BAR = %0d", intf_array[0].BAR); $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_pgo_threads.py0000755000542200017500000000207015101701376022264 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vltmt') test.top_filename = "t/t_gen_alw.v" # It doesn't really matter what test test.compile(v_flags2=["--prof-pgo"], threads=2) test.execute(all_run_flags=[ "+verilator+prof+exec+start+0", " +verilator+prof+exec+file+/dev/null", " +verilator+prof+vlt+file+" + test.obj_dir + "/profile.vlt"]) # yapf:disable test.file_grep(test.obj_dir + "/profile.vlt", r'profile_data ') test.compile( # Intentionally no --prof-pgo here to make sure profile data can be read in # without it (that is: --prof-pgo has no effect on profile_data hash names) v_flags2=[" " + test.obj_dir + "/profile.vlt"], threads=2) test.execute() test.passes() verilator-5.042/test_regress/t/t_wire_beh1364_bad.py0000755000542200017500000000137415101701376022703 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') waiver_filename = test.obj_dir + "/" + test.name + "_waiver.vlt" test.lint(verilator_flags2=["--lint-only --language 1364-2001 --waiver-output", waiver_filename], fails=True, expect_filename=test.golden_filename) if os.path.exists(waiver_filename): test.error("Waiver file generated, not expected") test.passes() verilator-5.042/test_regress/t/t_interface_generic2.py0000755000542200017500000000077115101701376023511 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--timing']) test.execute() test.passes() verilator-5.042/test_regress/t/t_event_control_star.out0000644000542200017500000000037115101701376024055 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_event_control_star.v:19:6: Unsupported: no sense equation (@*) 19 | @* a = c; | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_class_new_bad.v0000644000542200017500000000204215101701376022362 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class ClsNoArg; int imembera; function new(); imembera = 5; endfunction endclass class ClsNoNew; int imembera; endclass class ClsArg; int imembera; function new(int i); imembera = i + 1; endfunction endclass class ClsNew1; static function new(); // <--- Error: new can't be static endfunction endclass class ClsNew2; virtual function new(); // <--- Error: new can't be virtual endfunction endclass class ClsNew3; extern virtual function new(); // <--- Error: new can't be virtual endclass function ClsNew3::new(); endfunction module t; initial begin ClsNoArg c1; ClsNoNew c2; ClsArg c3; c1 = new(3); // Bad, called with arg c2 = new(3); // Bad, called with arg c3 = new(); // Bad, called without arg c1 = new[2]; $stop; end endmodule verilator-5.042/test_regress/t/t_lint_assigneqexpr_bad.out0000644000542200017500000000134715101701376024514 0ustar mahmoudyfreeshell%Warning-ASSIGNEQEXPR: t/t_lint_assigneqexpr.v:28:11: Assignment '=' inside expression : ... Was a '==' intended, or suggest use a separate statement 28 | c_o = 1 | ^ ... For warning description see https://verilator.org/warn/ASSIGNEQEXPR?v=latest ... Use "/* verilator lint_off ASSIGNEQEXPR */" and lint_on around source to disable this message. %Warning-ASSIGNEQEXPR: t/t_lint_assigneqexpr.v:30:11: Assignment '=' inside expression : ... Was a '==' intended, or suggest use a separate statement 30 | c_o = 0 | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_past_bad.py0000755000542200017500000000076315101701376021551 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_export_packed_struct.cpp0000644000542200017500000001436515101701376024362 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // Copyright 2024 by Kefa Chen. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 //************************************************************************* #include #include VM_PREFIX_INCLUDE #include "TestCheck.h" /* typedef logic [5:0] udata6_t; typedef union packed { udata6_t a; logic [2:0] b; } sub_t; typedef struct packed { logic [40:0] a; udata6_t [3:0] b; sub_t c; } in_t ; typedef struct packed { udata6_t [3:0] b; sub_t c; logic [40:0] a; } out_t ; // struct in1_t should cover parts of VL_ASSIGNSEL_II functions typedef struct packed { logic [3:0] a; logic [11:0] b; } in1_t; // 4 + 12 = 16 typedef struct packed { logic [11:0] b; logic [3:0] a; } out1_t; // struct in2_t should cover all VL_ASSIGNSEL_II functions typedef struct packed { logic [2:0] a; logic [8:0] b; logic [18:0] c; } in2_t; // 3 + 9 + 19 = 31 typedef struct packed { logic [8:0] b; logic [18:0] c; logic [2:0] a; } out2_t; // struct in3_t should cover all VL_ASSIGNSEL_XQ functions typedef struct packed { logic [1:0] a; logic [8:0] b; logic [16:0] c; logic [32:0] d; } in3_t; // 33 + 17 + 9 + 2 = 61 typedef struct packed { logic [8:0] b; logic [1:0] a; logic [32:0] d; logic [16:0] c; } out3_t; // struct in4_t should cover all VL_ASSIGNSEL_XW functions typedef struct packed { logic [4:0] a; logic [12:0] b; logic [24:0] c; logic [48:0] d; logic [80:0] e; } in4_t; // 5 + 13 + 25 + 49 + 81 = 173 typedef struct packed { logic [24:0] c; logic [48:0] d; logic [80:0] e; logic [4:0] a; logic [12:0] b; } out4_t; */ #define CONCAT_IMPL(a, b) a##b #define CONCAT(a, b) CONCAT_IMPL(a, b) #define CONCAT5(a, b, c, d, e) CONCAT(CONCAT(CONCAT(CONCAT(a, b), c), d), e) #define EXPORTED_STRUCT_NAME(STRUCT_NAME, NUMBER) \ CONCAT5(VM_PREFIX, _, STRUCT_NAME, __struct__, NUMBER) #define EXPORTED_UNION_NAME(UNION_NAME, NUMBER) \ CONCAT5(VM_PREFIX, _, UNION_NAME, __union__, NUMBER) #define SUB_T EXPORTED_UNION_NAME(sub_t, 0) #define IN_T EXPORTED_STRUCT_NAME(in_t, 0) #define OUT_T EXPORTED_STRUCT_NAME(out_t, 0) #define IN1_T EXPORTED_STRUCT_NAME(in1_t, 0) #define IN2_T EXPORTED_STRUCT_NAME(in2_t, 0) #define IN3_T EXPORTED_STRUCT_NAME(in3_t, 0) #define IN4_T EXPORTED_STRUCT_NAME(in4_t, 0) #define OUT1_T EXPORTED_STRUCT_NAME(out1_t, 0) #define OUT2_T EXPORTED_STRUCT_NAME(out2_t, 0) #define OUT3_T EXPORTED_STRUCT_NAME(out3_t, 0) #define OUT4_T EXPORTED_STRUCT_NAME(out4_t, 0) int errors = 0; int main(int argc, char** argv) { const std::unique_ptr contextp{new VerilatedContext}; contextp->debug(0); contextp->randReset(2); contextp->commandArgs(argc, argv); const std::unique_ptr adder{new VM_PREFIX{contextp.get()}}; { IN_T in1, in2; OUT_T out; in1.a = 0x12345678; in1.__SYM__nullptr[0] = 0x1; in1.__SYM__nullptr[1] = 0x2; in1.__SYM__nullptr[2] = 0x3; in1.__SYM__nullptr[3] = 0x4; in1.get__0.a = 0x5; in2.a = 0x11111111; in2.__SYM__nullptr[0] = 0x10; in2.__SYM__nullptr[1] = 0x20; in2.__SYM__nullptr[2] = 0x30; in2.__SYM__nullptr[3] = 0x30; in2.get__0.a = 0x20; adder->op1 = in1.get(); adder->op2 = in2.get(); adder->eval(); out.set(adder->out); TEST_CHECK_EQ(out.__SYM__nullptr[0], 0x11); TEST_CHECK_EQ(out.__SYM__nullptr[1], 0x22); TEST_CHECK_EQ(out.__SYM__nullptr[2], 0x33); TEST_CHECK_EQ(out.__SYM__nullptr[3], 0x34); TEST_CHECK_EQ(out.get__0.a, 0x25); TEST_CHECK_EQ(out.a, 0x23456789); // Additional tests IN1_T op1a, op1b; OUT1_T out1; op1a.a = 0x4; op1b.a = 0x5; op1a.b = 0x1fe; op1b.b = 0x1ef; adder->op1a = op1a.get(); adder->op1b = op1b.get(); adder->eval(); out1.set(adder->out1); TEST_CHECK_EQ(out1.a, op1a.a + op1b.a); TEST_CHECK_EQ(out1.b, op1a.b + op1b.b); IN2_T op2a, op2b; OUT2_T out2; op2a.a = 0x4; op2b.a = 0x3; op2a.b = 0xff; op2b.b = 0x1; op2a.c = 0x11212; op2b.c = 0x12121; adder->op2a = op2a.get(); adder->op2b = op2b.get(); adder->eval(); out2.set(adder->out2); TEST_CHECK_EQ(out2.a, op2a.a + op2b.a); TEST_CHECK_EQ(out2.b, op2a.b + op2b.b); TEST_CHECK_EQ(out2.c, op2a.c + op2b.c); IN3_T op3a, op3b; OUT3_T out3; op3a.a = 0x1; op3b.a = 0x2; op3a.b = 0x155; op3b.b = 0x44; op3a.c = 0xff; op3b.c = 0xff00; op3a.d = 0x123232323ULL; op3b.d = 0x32323232ULL; adder->op3a = op3a.get(); adder->op3b = op3b.get(); adder->eval(); out3.set(adder->out3); TEST_CHECK_EQ(out3.a, op3a.a + op3b.a); TEST_CHECK_EQ(out3.b, op3a.b + op3b.b); TEST_CHECK_EQ(out3.c, op3a.c + op3b.c); TEST_CHECK_EQ(out3.d, op3a.d + op3b.d); IN4_T op4a, op4b; OUT4_T out4; op4a.a = 0xf; op4b.a = 0x2; op4a.b = 0x123; op4b.b = 0x432; op4a.c = 0x123456; op4b.c = 0x654321; op4a.d = 0x123456789ULL; op4b.d = 0x987654321ULL; op4a.e[0] = 0x12345678; op4b.e[0] = 0x87654321; op4a.e[1] = 0xabcde000; op4b.e[1] = 0x000cdeba; op4a.e[2] = 0xe; op4b.e[2] = 0xf; adder->op4a = op4a.get(); adder->op4b = op4b.get(); adder->eval(); out4.set(adder->out4); TEST_CHECK_EQ(out4.a, op4a.a + op4b.a); TEST_CHECK_EQ(out4.b, op4a.b + op4b.b); TEST_CHECK_EQ(out4.c, op4a.c + op4b.c); TEST_CHECK_EQ(out4.d, op4a.d + op4b.d); TEST_CHECK_EQ(out4.e[0], op4a.e[0] + op4b.e[0]); TEST_CHECK_EQ(out4.e[1], op4a.e[1] + op4b.e[1]); TEST_CHECK_EQ(out4.e[2], op4a.e[2] + op4b.e[2]); } printf("*-* All Finished *-*\n"); return errors; } verilator-5.042/test_regress/t/t_enum_huge_methods_bad.v0000644000542200017500000000141515101701376024106 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; typedef enum logic [159:0] { E01 = 160'h1, ELARGE = 160'h1234_4567_abcd_1234_4567_abcd } my_t; my_t e; int cyc; // Check runtime always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==0) begin // Setup e <= E01; end else if (cyc==1) begin $display(e.name); e <= ELARGE; end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_class_param_comma_bad.py0000755000542200017500000000076615101701376024246 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_math_trig.py0000755000542200017500000000073415101701376021750 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_packed_struct_saif.out0000644000542200017500000004577415101701376025176 0ustar mahmoudyfreeshell// Generated by verilated_saif (SAIFILE (SAIFVERSION "2.0") (DIRECTION "backward") (PROGRAM_NAME "Verilator") (DIVIDER / ) (TIMESCALE 1ps) (DURATION 40) (INSTANCE top (NET (clk (T0 25) (T1 15) (TZ 0) (TX 0) (TB 0) (TC 7)) ) (INSTANCE t (NET (clk (T0 25) (T1 15) (TZ 0) (TX 0) (TB 0) (TC 7)) (cnt\[0\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3)) (cnt\[1\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (cnt\[2\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[3\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[4\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[5\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[6\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[8\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[9\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[10\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[11\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[12\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[13\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[14\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[15\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[16\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[17\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[18\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[19\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[20\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[21\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[22\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[23\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[24\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[25\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[26\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[27\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[28\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[29\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[30\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cnt\[31\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[0\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[1\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[2\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[3\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[4\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[5\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[6\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[8\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[9\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[10\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[11\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[12\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[13\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[14\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[15\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[16\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[17\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[18\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[19\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[20\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[21\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[22\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[23\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[24\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[25\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[26\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[27\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[28\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) (v[0]\[29\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) (v[0]\[30\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[31\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[32\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) (v[0]\[33\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[34\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[35\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[36\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[37\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[38\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[39\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[40\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[41\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[42\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[43\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[44\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[45\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[46\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[47\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[48\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[49\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[50\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[51\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[52\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[53\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[54\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[55\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[56\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[57\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[58\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[59\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[60\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) (v[0]\[61\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) (v[0]\[62\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[63\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[64\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[65\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) (v[0]\[66\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[67\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[68\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[69\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[70\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[71\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[72\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[73\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[74\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[75\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[76\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[77\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[78\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[79\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[80\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[81\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[82\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[83\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[84\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[85\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[86\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[87\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[88\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[89\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[90\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[91\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[92\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) (v[0]\[93\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) (v[0]\[94\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[0]\[95\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[0\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[1\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[2\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[3\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[4\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[5\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[6\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[8\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[9\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[10\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[11\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[12\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[13\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[14\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[15\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[16\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[17\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[18\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[19\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[20\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[21\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[22\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[23\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[24\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[25\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[26\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[27\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[28\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[29\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) (v[1]\[30\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[31\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[32\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) (v[1]\[33\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[34\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[35\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[36\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[37\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[38\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[39\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[40\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[41\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[42\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[43\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[44\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[45\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[46\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[47\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[48\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[49\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[50\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[51\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[52\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[53\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[54\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[55\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[56\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[57\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[58\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[59\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[60\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[61\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) (v[1]\[62\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[63\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[64\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[65\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) (v[1]\[66\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[67\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[68\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[69\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[70\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[71\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[72\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[73\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[74\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[75\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[76\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[77\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[78\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[79\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[80\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[81\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[82\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[83\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[84\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[85\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[86\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[87\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[88\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[89\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[90\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[91\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[92\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[93\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) (v[1]\[94\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[1]\[95\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[0\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[1\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[2\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[3\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[4\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[5\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[6\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[8\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[9\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[10\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[11\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[12\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[13\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[14\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[15\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[16\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[17\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[18\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[19\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[20\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[21\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[22\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[23\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[24\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[25\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[26\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[27\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[28\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) (v[2]\[29\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[30\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[31\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[32\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) (v[2]\[33\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[34\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[35\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[36\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[37\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[38\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[39\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[40\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[41\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[42\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[43\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[44\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[45\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[46\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[47\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[48\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[49\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[50\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[51\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[52\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[53\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[54\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[55\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[56\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[57\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[58\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[59\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[60\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) (v[2]\[61\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[62\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[63\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[64\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[65\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) (v[2]\[66\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[67\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[68\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[69\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[70\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[71\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[72\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[73\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[74\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[75\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[76\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[77\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[78\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[79\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[80\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[81\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[82\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[83\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[84\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[85\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[86\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[87\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[88\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[89\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[90\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[91\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[92\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) (v[2]\[93\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[94\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v[2]\[95\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) verilator-5.042/test_regress/t/t_display_signed.out0000644000542200017500000000201215101701376023133 0ustar mahmoudyfreeshell[0] lp %x=0bbccc %x=0bbccc %o=2736314 %b=010111011110011001100 %0d=769228 %d= 769228 %p= 769228 %0p='hbbccc [0] ln %x=1bbccc %x=1bbccc %o=6736314 %b=110111011110011001100 %0d=-279348 %d= -279348 %p=1817804 %0p='h1bbccc [0] qp %x=001bbbbcccc %x=001bbbbcccc %o=00067356746314 %b=00000000110111011101110111100110011001100 %0d=7444614348 %d= 7444614348 %p= 7444614348 %0p='h1bbbbcccc [0] qn %x=101bbbbcccc %x=101bbbbcccc %o=20067356746314 %b=10000000110111011101110111100110011001100 %0d=-1092067013428 %d=-1092067013428 %p=1106956242124 %0p='h101bbbbcccc [0] wp %x=000bc1234567812345678 %x=000bc1234567812345678 %o=000570110642547402215053170 %b=000000000101111000001001000110100010101100111100000010010001101000101011001111000 %p= 3469299654322568844920 %0p='hbc1234567812345678 [0] wn %x=000bc1234577812345678 %x=000bc1234577812345678 %o=000570110642567402215053170 %b=000000000101111000001001000110100010101110111100000010010001101000101011001111000 %p= 3469299655422080472696 %0p='hbc1234577812345678 *-* All Finished *-* verilator-5.042/test_regress/t/t_trace_dumpvars_dyn_saif_0.py0000755000542200017500000000130515101701376025077 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_trace_dumpvars_dyn.cpp" test.top_filename = "t/t_trace_dumpvars_dyn.v" test.compile(make_main=False, verilator_flags2=["--trace-saif --exe", test.pli_filename]) test.execute() test.saif_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_math_shortcircuit_dynsel.v0000644000542200017500000000201715101701376024711 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; logic [31:0] dict [int] []; // verilator lint_off WIDTHTRUNC function automatic logic f(int a); int dict_size = dict.size; logic next_exists = dict.next(a); // incorrectly inserts element at `a` logic next_nonzero = !next_exists || (dict[a].size != 0); if (dict_size != dict.size) begin $display("Assertion failed: dict_size mismatch"); $display("Initial size: %0d, New size: %0d", dict_size, dict.size); $display("Dictionary contents:"); foreach (dict[key]) begin $display(" Key: %0d, Value: %0d", key, dict[key]); end $error; end return next_nonzero; endfunction initial begin logic r = f(0); $display(r); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_tri_array_pull.py0000755000542200017500000000073415101701376023022 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_vpi_time_cb.v0000644000542200017500000000174515101701376022067 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2010 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import "DPI-C" function void dpii_init(); import "DPI-C" function void dpii_final(); module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [31:0] count /*verilator public_flat_rd */; integer status; // Test loop initial begin count = 0; dpii_init(); end always @(posedge clk) begin `ifdef TEST_VERBOSE $display("[%0t] clk @ count %0d", $time, count); `endif count <= count + 2; if (count == 200) begin $display("Final section"); // See C++ code: $write("*-* All Finished *-*\n"); dpii_final(); $finish; end end endmodule : t verilator-5.042/test_regress/t/t_param_bit_sel.v0000644000542200017500000000141415101701376022401 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // We see Verilator assumes a 1-bit parameter is a scalar rather than a 1-bit // long vector. This causes the following code to fail. // // Other event drive simulators accept this. // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; // At this point it is ambiguous whether a is scalar or vector parameter A = 1'b0; wire b = A[0]; // Note however b[0] is illegal. always @(posedge clk) begin if (b == 1'b0) begin $write("*-* All Finished *-*\n"); $finish; end else begin $stop; end end endmodule verilator-5.042/test_regress/t/t_inside3.v0000644000542200017500000000165715101701376021147 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Foo; int callCount = 0; int value = 6; function int get(); callCount += 1; return value; endfunction endclass module t; Foo foo; Foo array[100]; Foo res[$]; initial begin foo = new; for (int i = 0; i < 100; ++i) begin array[i] = new; end if (!(foo.get() inside {3,4,5,6,7,8,9})) $stop; if (foo.callCount != 1) $stop; if (!(foo.get() inside {[3:9]})) $stop; if (foo.callCount != 2) $stop; res = array.find(x) with (x.get() inside {5,7,8,9}); if (res.size() != 0) $stop; for (int i = 0; i < 100; ++i) begin if (array[i].callCount != 1) $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_stop_winos_bad.py0000755000542200017500000000105015101701376022774 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['-no-MMD']) test.execute(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_cover_sva_trace.out0000644000542200017500000000377115101701376023317 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $var wire 1 # clk $end $scope module t $end $var wire 1 # clk $end $var wire 1 $ toggle $end $var wire 32 % cyc [31:0] $end $scope module suba $end $var wire 1 # clk $end $var wire 1 $ toggle $end $var wire 32 & cyc [31:0] $end $var wire 32 ' cyc_eq_5_vlCoverageUserTrace [31:0] $end $upscope $end $scope module subb $end $var wire 1 # clk $end $var wire 1 $ toggle $end $var wire 32 & cyc [31:0] $end $var wire 32 ( cyc_eq_5_vlCoverageUserTrace [31:0] $end $upscope $end $scope module subc $end $var wire 1 # clk $end $var wire 1 $ toggle $end $var wire 32 & cyc [31:0] $end $var wire 32 ) cyc_eq_5_vlCoverageUserTrace [31:0] $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 0# 0$ b00000000000000000000000000000001 % b00000000000000000000000000000001 & b00000000000000000000000000000000 ' b00000000000000000000000000000000 ( b00000000000000000000000000000000 ) #10 1# b00000000000000000000000000000010 % b00000000000000000000000000000010 & #15 0# #20 1# 1$ b00000000000000000000000000000011 % b00000000000000000000000000000011 & #25 0# #30 1# 0$ b00000000000000000000000000000100 % b00000000000000000000000000000100 & #35 0# #40 1# 1$ b00000000000000000000000000000101 % b00000000000000000000000000000101 & #45 0# #50 1# 0$ b00000000000000000000000000000110 % b00000000000000000000000000000110 & b00000000000000000000000000000001 ' b00000000000000000000000000000001 ( b00000000000000000000000000000001 ) #55 0# #60 1# 1$ b00000000000000000000000000000111 % b00000000000000000000000000000111 & #65 0# #70 1# 0$ b00000000000000000000000000001000 % b00000000000000000000000000001000 & #75 0# #80 1# 1$ b00000000000000000000000000001001 % b00000000000000000000000000001001 & #85 0# #90 1# 0$ b00000000000000000000000000001010 % b00000000000000000000000000001010 & #95 0# #100 1# 1$ b00000000000000000000000000001011 % b00000000000000000000000000001011 & verilator-5.042/test_regress/t/t_vlt_warn_bad.vlt0000644000542200017500000000117515101701376022606 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `verilator_config lint_off -rule CASEINCOMPLETE -file "t/t_vlt_warn.v" lint_off -rule WIDTH -file "t/t_vlt_warn.v" -lines 18 // Test wildcard filenames lint_off -rule WIDTH -file "*/t_vlt_warn.v" -lines 19-19 // Test global disables lint_off -file "*/t_vlt_warn.v" -lines 20-20 coverage_off -file "t/t_vlt_warn.v" // Test --flag is also accepted tracing_off --file "t/t_vlt_warn.v" verilator-5.042/test_regress/t/t_interface_ref_trace_noinl.py0000755000542200017500000000150515101701376025140 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_ref_trace.v" # Should be the same as the inlined version, but might have declarations # in a different order. Sadly vcddiff can't check equivalence # test.golden_filename = "t/t_interface_ref_trace.out" test.compile(verilator_flags2=['-fno-inline --trace-structs --trace-vcd']) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_implements_notfound_bad.py0000755000542200017500000000076615101701376024676 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_inst_prepost.py0000755000542200017500000000071415101701376022521 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.passes() verilator-5.042/test_regress/t/t_sys_strobe.out0000644000542200017500000000020515101701376022333 0ustar mahmoudyfreeshell[110] cyc=11 [110] cyc=11 also 00000000000000000000000000010010b 00000013h 00000000024o [230] cyc=23 new-strobe *-* All Finished *-* verilator-5.042/test_regress/t/t_randomize.out0000644000542200017500000000177515101701376022144 0ustar mahmoudyfreeshell%Warning-CONSTRAINTIGN: t/t_randomize.v:22:14: Constraint expression ignored (imperfect distribution) : ... note: In instance 't' 22 | length dist { [0:1], [2:5] :/ 2, 6 := 6, 7 := 10, 1}; | ^~~~ ... For warning description see https://verilator.org/warn/CONSTRAINTIGN?v=latest ... Use "/* verilator lint_off CONSTRAINTIGN */" and lint_on around source to disable this message. %Warning-CONSTRAINTIGN: t/t_randomize.v:40:7: Constraint expression ignored (unsupported) : ... note: In instance 't' 40 | unique { array[0], array[1] }; | ^~~~~~ %Warning-CONSTRAINTIGN: t/t_randomize.v:43:23: Constraint expression ignored (imperfect distribution) : ... note: In instance 't' 43 | constraint order { solve length before header; } | ^~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_for_break.v0000644000542200017500000000775115101701376021544 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [3:0] l_stop = crc[3:0]; wire [3:0] l_break = crc[7:4]; wire [3:0] l_continue = crc[11:8]; /*AUTOWIRE*/ wire [15:0] out0 = Test0(l_stop, l_break, l_continue); wire [15:0] out1 = Test1(l_stop, l_break, l_continue); wire [15:0] out2 = Test2(l_stop, l_break, l_continue); wire [15:0] out3 = Test3(l_stop, l_break, l_continue); // Aggregate outputs into a single result vector wire [63:0] result = {out3,out2,out1,out0}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin if (out0!==out1) $stop; if (out0!==out2) $stop; if (out0!==out3) $stop; end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h293e9f9798e97da0 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end function [15:0] Test0; input [3:0] loop_stop; input [3:0] loop_break; input [3:0] loop_continue; integer i; reg broken; Test0 = 0; broken = 0; begin for (i=1; i<20; i=i+1) begin if (!broken) begin Test0 = Test0 + 1; if (i[3:0] != loop_continue) begin // continue if (i[3:0] == loop_break) begin broken = 1'b1; end if (!broken) begin Test0 = Test0 + i[15:0]; end end end end end endfunction function [15:0] Test1; input [3:0] loop_stop; input [3:0] loop_break; input [3:0] loop_continue; integer i; Test1 = 0; begin : outer_block for (i=1; i<20; i=i+1) begin : inner_block Test1 = Test1 + 1; // continue, IE jump to end-of-inner_block. Must be inside inner_block. if (i[3:0] == loop_continue) disable inner_block; // break, IE jump to end-of-outer_block. Must be inside outer_block. if (i[3:0] == loop_break) disable outer_block; Test1 = Test1 + i[15:0]; end : inner_block end : outer_block endfunction function [15:0] Test2; input [3:0] loop_stop; input [3:0] loop_break; input [3:0] loop_continue; integer i; Test2 = 0; begin for (i=1; i<20; i=i+1) begin Test2 = Test2 + 1; if (i[3:0] == loop_continue) continue; if (i[3:0] == loop_break) break; Test2 = Test2 + i[15:0]; end end endfunction function [15:0] Test3; input [3:0] loop_stop; input [3:0] loop_break; input [3:0] loop_continue; integer i; Test3 = 0; begin for (i=1; i<20; i=i+1) begin Test3 = Test3 + 1; if (i[3:0] == loop_continue) continue; // return, IE jump to end-of-function optionally setting return value if (i[3:0] == loop_break) return Test3; Test3 = Test3 + i[15:0]; end end endfunction endmodule verilator-5.042/test_regress/t/t_sys_sformat.v0000644000542200017500000000611115101701376022150 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; // Note $sscanf already tested elsewhere reg [3:0] n; reg [63:0] q; reg [16*8:1] wide; reg [8:1] ochar; reg [48*8:1] str; reg [48*8:1] str2; string str3; reg [39:0] instruction_str [1:0]; real r; initial begin n = 4'b1100; q = 64'h1234_5678_abcd_0123; wide = "hello-there12345"; $sformat(str, "n=%b q=%d w=%s", n, q, wide); `ifdef TEST_VERBOSE $display("str=%0s",str); `endif if (str !== "n=1100 q= 1311768467750060323 w=hello-there12345") $stop; q = {q[62:0],1'b1}; $swrite(str2, "n=%b q=%d w=%s", n, q, wide); `ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif if (str2 !== "n=1100 q= 2623536935500120647 w=hello-there12345") $stop; str3 = $sformatf("n=%b q=%d w=%s", n, q, wide); `ifdef TEST_VERBOSE $display("str3=%0s",str3); `endif if (str3 !== "n=1100 q= 2623536935500120647 w=hello-there12345") $stop; $swrite(str2, "e=%e", r); $swrite(str2, "e=%f", r); $swrite(str2, "e=%g", r); str3 = "hello"; $swrite(str2, {str3, str3}); `ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif if (str2 !== "hellohello") $stop; r = 0.01; $swrite(str2, "e=%e f=%f g=%g", r, r, r); `ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif if (str2 !== "e=1.000000e-02 f=0.010000 g=0.01") $stop; $swrite(str2, "mod=%m"); `ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif if (str2 !== "mod=top.t") $stop; $swrite(str2, "lib=%l"); `ifdef TEST_VERBOSE $display("chkl %0s",str2); `endif if (str2 !== "lib=work.t") $stop; str3 = $sformatf("u=%u", {"a","b","c","d"}); // Value selected so is printable `ifdef TEST_VERBOSE $display("chku %s", str3); `endif if (str3 !== "u=dcba") $stop; str3 = $sformatf("v=%v", 4'b01xz); // Value selected so is printable `ifdef TEST_VERBOSE $display("chkv %s", str3); `endif str3 = $sformatf("z=%z", {"a","b","c","d"}); // Value selected so is printable `ifdef TEST_VERBOSE $display("chkz %s", str3); `endif $sformat(ochar,"%s","c"); if (ochar != "c") $stop; $swrite(str2, 4'd12); if (str2 != "12") $stop; $swriteb(str2, 4'd12); if (str2 != "1100") $stop; $swriteh(str2, 4'd12); if (str2 != "c") $stop; $swriteo(str2, 4'd12); if (str2 != "14") $stop; str3 = "foo"; $sformat(str3, "%s", str3); // $sformat twice so verilator does not $sformat(str3, "%s", str3); // optimize the call to $sformat(str3, "%s", "foo") `ifdef TEST_VERBOSE $display("str3=%0s", str3); `endif if (str3 != "foo") $stop; $sformat(instruction_str[0], "%s", "Hello"); $sformat(instruction_str[1], "%s", "World"); if (instruction_str[0] != "Hello") $stop; if (instruction_str[1] != "World") $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_enum_value_assign.py0000755000542200017500000000073415101701376023476 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_didnotconverge_bad.py0000755000542200017500000000165615101701376024644 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') if not os.path.exists(test.root + "/.git"): test.skip("Not in a git repository") test.compile(verilator_flags2=["--prof-cfuncs"]) test.execute(fails=True, expect_filename=test.golden_filename) test.extract(in_filename=test.top_filename, out_filename=test.root + "/docs/gen/ex_DIDNOTCONVERGE_faulty.rst", lines="16-17") test.extract(in_filename=test.golden_filename, out_filename=test.root + "/docs/gen/ex_DIDNOTCONVERGE_msg.rst", lines="1-2") test.passes() verilator-5.042/test_regress/t/t_dfg_synthesis_pre_inline.v0000644000542200017500000000167315101701376024664 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 `define signal(name, expr) wire [$bits(expr)-1:0] ``name = expr module t ( `include "portlist.vh" // Boilerplate generated by t_dfg_break_cycles.py rand_a, rand_b, srand_a, srand_b ); `include "portdecl.vh" // Boilerplate generated by t_dfg_break_cycles.py input rand_a; input rand_b; input srand_a; input srand_b; wire logic [63:0] rand_a; wire logic [63:0] rand_b; wire logic signed [63:0] srand_a; wire logic signed [63:0] srand_b; ////////////////////////////////////////////////////////////////////////// logic concat_lhs_a; logic concat_lhs_b; always_comb begin {concat_lhs_a, concat_lhs_b} = rand_a[1:0] + rand_b[1:0]; end `signal(CONCAT_LHS, {concat_lhs_a, concat_lhs_b}); endmodule verilator-5.042/test_regress/t/t_fork_join_none_class_cap.py0000755000542200017500000000077115101701376025002 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_pp_display.out0000644000542200017500000000063615101701376022313 0ustar mahmoudyfreeshellpre thrupre thrumid thrupost post: "right side" left side: "right side" left side: "right side" left_side: "right_side" na: "right_side" prep ( midp1 left_side midp2 ( outp ) ): "right_side" na: "nana" left_side right_side: "left_side right_side" left side: "right side" : "" left side: "right side" left side: "right side" standalone twoline: "first second" Line 50 File "t/t_pp_display.v" *-* All Finished *-* verilator-5.042/test_regress/t/t_flag_context_bad.py0000755000542200017500000000110215101701376023243 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["-Wall -Wno-DECLFILENAME -Wno-context"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_recursive_module_bug_2.py0000755000542200017500000000071415101701376024422 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.passes() verilator-5.042/test_regress/t/t_func_recurse.py0000755000542200017500000000073415101701376022455 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_override_bad.py0000755000542200017500000000076615101701376023611 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_dyn_cast_empty_if.py0000755000542200017500000000073415101701376024657 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_unpacked_struct_redef.v0000644000542200017500000000112215101701376024137 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class Class#(parameter WIDTH); typedef logic [WIDTH-1:0] word; typedef struct { word w; } Struct; endclass module t; Class#(1)::Struct s1; Class#(1)::Struct s2; Class#(2)::Struct s3; initial begin $display("%p", s1); $display("%p", s2); $display("%p", s3); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_unroll_nested_param.v0000644000542200017500000000254215101701376023640 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; int a, b; int pos; function string value; // Debug 'initial' loops first value = ""; for (int exit_a = 0; exit_a < 2; ++exit_a) begin for (int exit_b = 0; exit_b < 3; ++exit_b) begin b = 0; value = {value, $sformatf("exit_a %0d %0d", exit_a, exit_b)}; for (a = 0; a < 3; ++a) begin : a_loop value = {value, $sformatf(" A%0d", a * 10 + b)}; for (b = 0; b < 3; ++b) begin : b_loop value = {value, $sformatf(" B%0d", a * 10 + b)}; if (exit_b == 1 && b == 1) disable b_loop; value = {value, $sformatf(" C%0d", a * 10 + b)}; if (exit_b == 2 && a == 1) disable a_loop; value = {value, $sformatf(" D%0d", a * 10 + b)}; end value = {value, $sformatf(" Y%0d", a * 10 + b)}; if (exit_a == 1 && a == 1) disable a_loop; value = {value, $sformatf(" Z%0d", a * 10 + b)}; end value = {value, "\n"}; end end endfunction localparam string VALUE = value(); initial begin $write("%s", VALUE); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_disable_fork1.py0000755000542200017500000000077115101701376022500 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_constraint_foreach.py0000755000542200017500000000104615101701376023642 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_reloop_cam.v0000644000542200017500000001227415101701376021726 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; reg rst; // Two phases, random so nothing optimizes away, and focused so get hits logic inval; wire [30:0] wdat = (cyc < 50 ? crc[30:0] : {29'h0, crc[1:0]}); wire [30:0] cdat = (cyc < 50 ? crc[30:0] : {29'h0, crc[1:0]}); wire wdat_val = 1'b1; wire camen = crc[32]; wire ren = crc[33]; wire wen = crc[34]; wire [7:0] rwidx = (cyc < 50 ? crc[63:56] : {6'h0, crc[57:56]}); /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) logic hit_d2r; // From cam of cam.v logic [7:0] hitidx_d1r; // From cam of cam.v logic [255:0] hitvec_d1r; // From cam of cam.v logic [30:0] rdat_d2r; // From cam of cam.v logic rdat_val_d2r; // From cam of cam.v // End of automatics cam cam (/*AUTOINST*/ // Outputs .hitvec_d1r (hitvec_d1r[255:0]), .hitidx_d1r (hitidx_d1r[7:0]), .hit_d2r (hit_d2r), .rdat_d2r (rdat_d2r[30:0]), .rdat_val_d2r (rdat_val_d2r), // Inputs .clk (clk), .rst (rst), .camen (camen), .inval (inval), .cdat (cdat[30:0]), .ren (ren), .wen (wen), .wdat (wdat[30:0]), .wdat_val (wdat_val), .rwidx (rwidx[7:0])); // Aggregate outputs into a single result vector wire [63:0] result = {hitvec_d1r[15:0], 15'h0, hit_d2r, rdat_val_d2r, rdat_d2r}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; rst <= 1'b1; end else if (cyc<10) begin sum <= '0; rst <= 1'b0; end else if (cyc==70) begin inval <= 1'b1; end else if (cyc==71) begin inval <= 1'b0; end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; `define EXPECTED_SUM 64'h5182640870b07199 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module cam ( input clk, input rst, input camen, input inval, input [30:0] cdat, output logic [255:0] hitvec_d1r, output logic [7:0] hitidx_d1r, output logic hit_d2r, input ren, input wen, input [30:0] wdat, input wdat_val, input [7:0] rwidx, output logic [30:0] rdat_d2r, output logic rdat_val_d2r ); logic camen_d1r; logic inval_d1r; logic ren_d1r; logic wen_d1r; logic [7:0] rwidx_d1r; logic [30:0] cdat_d1r; logic [30:0] wdat_d1r; logic wdat_val_d1r; always_ff @(posedge clk) begin camen_d1r <= camen; inval_d1r <= inval; ren_d1r <= ren; wen_d1r <= wen; cdat_d1r <= cdat; rwidx_d1r <= rwidx; wdat_d1r <= wdat; wdat_val_d1r <= wdat_val; end typedef struct packed { logic [30:0] data; logic valid; } entry_t; entry_t [255:0] entries; always_ff @(posedge clk) begin if (camen_d1r) begin for (int i = 0; i < 256; i = i + 1) begin hitvec_d1r[i] <= entries[i].valid & (entries[i].data == cdat_d1r); end end end always_ff @(posedge clk) begin hit_d2r <= | hitvec_d1r; end always_ff @(posedge clk) begin if (rst) begin for (int i = 0; i < 256; i = i + 1) begin entries[i] <= '0; end end else if (wen_d1r) begin entries[rwidx_d1r] <= '{valid:wdat_val_d1r, data:wdat_d1r}; end else if (inval_d1r) begin for (int i = 0; i < 256; i = i + 1) begin entries[i] <= '{valid:'0, data:entries[i].data}; end end end always_ff @(posedge clk) begin if (ren_d1r) begin rdat_d2r <= entries[rwidx_d1r].data; rdat_val_d2r <= entries[rwidx_d1r].valid; end end endmodule verilator-5.042/test_regress/t/t_virtual_interface_method_bad.v0000644000542200017500000000151215101701376025453 0ustar mahmoudyfreeshell// Copyright 2003 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 class ExampleClass; localparam NUM_TXNS = 10; protected virtual example_if v_if; task run(); v_if.x(); endtask: run function void bind_if(virtual example_if v_if); this.v_if = v_if; endfunction: bind_if endclass: ExampleClass interface example_if(); logic clk; logic rstn; logic[7:0] x; endinterface: example_if module t; example_if example_if_inst(); initial begin: main ExampleClass exampleClass = new(); exampleClass.bind_if(example_if_inst); exampleClass.run(); end: main endmodule: t verilator-5.042/test_regress/t/t_param_bit_sel.py0000755000542200017500000000073415101701376022573 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_case_enum_emptyish.py0000755000542200017500000000106515101701376023651 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile( # We have deep expressions we want to test) verilator_flags2=["--compiler msvc"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_class_mispure_bad.out0000644000542200017500000000073215101701376023623 0ustar mahmoudyfreeshell%Error: t/t_class_mispure_bad.v:11:1: Class 'Bar' extends 'Base' but is missing implementation for 'pvfunc' (IEEE 1800-2023 8.26) 11 | class Bar extends Base; | ^~~~~ t/t_class_mispure_bad.v:8:31: ... Location of interface class's function 8 | pure virtual function void pvfunc(); | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_lint_const_func_gen_bad.out0000644000542200017500000000164515101701376024776 0ustar mahmoudyfreeshell%Error: t/t_lint_const_func_gen_bad.v:11:30: Constant function may not be declared under generate (IEEE 1800-2023 13.4.3) : ... note: In instance 't' 11 | function automatic bit constFunc(); | ^~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_lint_const_func_gen_bad.v:15:26: Expecting expression to be constant, but can't determine constant for FUNCREF 'constFunc' : ... note: In instance 't' t/t_lint_const_func_gen_bad.v:11:30: ... Location of non-constant FUNC 'constFunc': Constant function called under generate t/t_lint_const_func_gen_bad.v:15:26: ... Called from 'constFunc()' with parameters: 15 | localparam PARAM = constFunc(); | ^~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_inst_overwide_bad.out0000644000542200017500000000337515101701376023641 0ustar mahmoudyfreeshell%Warning-WIDTHEXPAND: t/t_inst_overwide.v:23:14: Output port connection 'outy_w92' expects 92 bits on the pin connection, but pin connection's VARREF 'outc_w30' generates 30 bits. : ... note: In instance 't' 23 | .outy_w92 (outc_w30), | ^~~~~~~~ ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. %Warning-WIDTHTRUNC: t/t_inst_overwide.v:24:14: Output port connection 'outz_w22' expects 22 bits on the pin connection, but pin connection's VARREF 'outd_w73' generates 73 bits. : ... note: In instance 't' 24 | .outz_w22 (outd_w73), | ^~~~~~~~ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Warning-WIDTHEXPAND: t/t_inst_overwide.v:27:14: Input port connection 'inw_w31' expects 31 bits on the pin connection, but pin connection's VARREF 'ina_w1' generates 1 bits. : ... note: In instance 't' 27 | .inw_w31 (ina_w1), | ^~~~~~~ %Warning-WIDTHTRUNC: t/t_inst_overwide.v:28:14: Input port connection 'inx_w11' expects 11 bits on the pin connection, but pin connection's VARREF 'inb_w61' generates 61 bits. : ... note: In instance 't' 28 | .inx_w11 (inb_w61) | ^~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_disable_iff_multi_bad.out0000644000542200017500000000055615101701376024417 0ustar mahmoudyfreeshell%Error: t/t_disable_iff_multi_bad.v:14:4: Only one 'default disable iff' allowed per module (IEEE 1800-2023 16.15) : ... note: In instance 't' 14 | default disable iff (!rstn); | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_func_inout_bit_sel.v0000644000542200017500000000135515101701376023456 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); class Cls; function bit get_x_set_1(inout bit x); bit a = x; x = 1; return a; endfunction endclass module t; int a; bit b; Cls cls; initial begin cls = new; b = cls.get_x_set_1(a[1]); `checkh(b, 0); `checkh(a[1], 1); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_func_task_bad2.v0000644000542200017500000000075415101701376022453 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; task a_task; input ign; endtask function void func_calls_task; a_task(1'b0); // <--- Bad: Calling task _from_ function endfunction function void func_ok; fork a_task(1'b0); // ok, and done in UVM join_none endfunction endmodule verilator-5.042/test_regress/t/t_queue_unpacked.v0000644000542200017500000000343215101701376022600 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t; typedef string sarray_t[2]; typedef sarray_t q_sarray_t[$]; typedef bit [95:0] wide_t; typedef wide_t warray_t[2]; typedef warray_t q_warray_t[$]; initial begin begin q_sarray_t iq; sarray_t a; sarray_t b0; sarray_t b1; a[0] = "hello"; a[1] = "world"; iq.push_back(a); a[0] = "bye"; a[1] = "world"; iq.push_back(a); b0 = iq[0]; b1 = iq[1]; `checks(b0[0], "hello"); `checks(b0[1], "world"); `checks(b1[0], "bye"); `checks(b1[1], "world"); iq[2][0] = "goodbye"; iq[2][1] = "world"; `checks(iq[2][0], "goodbye"); `checks(iq[2][1], "world"); end `ifndef verilator // Need wide conversion into VlUnpacked types // If we convert all arrays to VlUnpacked it works, so we need to track // data types and insert conversions perhaps in V3Cast, but we currently // don't know the output datatypes, so work needed. begin q_warray_t iq; warray_t a; warray_t b0; a[0] = "abcdefg_ijkl"; a[1] = "012123123128"; iq.push_back(a); b0 = iq[0]; `checks(b0[0], "abcdefg_ijkl"); `checks(b0[1], "012123123128"); end `endif $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_interface_ref_trace_noinl_notrace.py0000755000542200017500000000105415101701376026652 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_ref_trace.v" test.compile(verilator_flags2=['-fno-inline']) test.execute() test.passes() verilator-5.042/test_regress/t/t_vpi_stop_bad_c.cpp0000644000542200017500000000145515101701376023075 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "svdpi.h" #include "vpi_user.h" #include #include //====================================================================== extern "C" { extern void dpii_test(); } //====================================================================== void dpii_test() { vpi_control(vpiStop); } verilator-5.042/test_regress/t/t_order_quad.cpp0000644000542200017500000000222615101701376022244 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include VM_PREFIX_INCLUDE //====================================================================== unsigned int main_time = 0; double sc_time_stamp() { return main_time; } VM_PREFIX* topp = nullptr; bool fail = false; void check(QData got, QData exp) { if (got != exp) { VL_PRINTF("%%Error: got=0x%" PRIx64 " exp=0x%" PRIx64 "\n", got, exp); fail = true; } } int main(int argc, char* argv[]) { Verilated::debug(0); Verilated::commandArgs(argc, argv); topp = new VM_PREFIX; topp->a0 = 0; topp->eval(); check(topp->y, 0x0ULL); topp->a0 = 15; topp->eval(); check(topp->y, 0x3c00000000ULL); if (!fail) { VL_PRINTF("*-* All Finished *-*\n"); topp->final(); } else { vl_fatal(__FILE__, __LINE__, "top", "Unexpected results\n"); } VL_DO_DANGLING(delete topp, topp); return 0; } verilator-5.042/test_regress/t/t_extract_static_const_multimodule.py0000755000542200017500000000133015101701376026632 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(verilator_flags2=["--stats"]) test.execute(expect_filename=test.golden_filename) if test.vlt_all: test.file_grep(test.stats, r'Optimizations, Prelim extracted value to ConstPool\s+(\d+)', 8) test.file_grep(test.stats, r'ConstPool, Constants emitted\s+(\d+)', 1) test.passes() verilator-5.042/test_regress/t/t_timing_wait1.py0000755000542200017500000000101015101701376022352 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary -Wno-WAITCONST"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_dpi_instr_count_large.cpp0000644000542200017500000000101615101701376024470 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2025 by Antmicro. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* extern "C" void dpii_call(void) {} verilator-5.042/test_regress/t/t_union_soft.out0000644000542200017500000000035415101701376022327 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_union_soft.v:9:10: Unsupported: 'union soft' 9 | union soft { | ^~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_vlcov_info.py0000755000542200017500000000142415101701376022133 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') test.run(cmd=[ os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--write-info", test.obj_dir + "/coverage.info", "t/t_vlcov_data_a.dat", "t/t_vlcov_data_b.dat", "t/t_vlcov_data_c.dat", "t/t_vlcov_data_d.dat" ], verilator_run=True) test.files_identical(test.obj_dir + "/coverage.info", "t/" + test.name + ".info.out") test.passes() verilator-5.042/test_regress/t/t_flag_deprecated_bad.v0000644000542200017500000000035215101701376023477 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; endmodule verilator-5.042/test_regress/t/t_constraint_assoc_arr_wide.py0000755000542200017500000000104615101701376025217 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_vlt_match_contents.py0000755000542200017500000000111215101701376023657 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--lint-only -Wall t/t_vlt_match_contents.vlt"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_program_anonymous.py0000755000542200017500000000105515101701376023546 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) if not test.vlt_all: test.execute() test.passes() verilator-5.042/test_regress/t/t_typedef_circ_bad.v0000644000542200017500000000040515101701376023045 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef a_t; typedef a_t b_t; typedef b_t a_t; verilator-5.042/test_regress/t/t_var_dotted1_inl0.py0000755000542200017500000000104515101701376023124 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_var_dotted1.v" test.compile(v_flags2=['+define+NOUSE_INLINE']) test.execute() test.passes() verilator-5.042/test_regress/t/t_mem_slice_dtype_bad.py0000755000542200017500000000076615101701376023747 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_param_typedef.py0000755000542200017500000000070615101701376022611 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.042/test_regress/t/t_lint_once_bad.py0000755000542200017500000000107215101701376022546 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["--lint-only -Wwarn-UNUSED"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface_down_inld.py0000755000542200017500000000110115101701376023754 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_down.v" test.compile(v_flags2=['+define+INLINE_D'], verilator_flags2=['-trace']) test.execute() test.passes() verilator-5.042/test_regress/t/t_nettype.v0000644000542200017500000000251215101701376021270 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package Pkg; typedef real real_t; real last_resolve; function automatic real resolver(input real drivers[]); resolver = 0.0; foreach (drivers[i]) resolver += drivers[i]; last_resolve = resolver; endfunction endpackage module t; function automatic real local_resolver(input real drivers[]); local_resolver = 0.0; foreach (drivers[i]) local_resolver += drivers[i]; endfunction nettype real real1_n with Pkg::resolver; real1_n real1; assign real1 = 1.23; nettype real real2_n with local_resolver; real2_n real2; assign real2 = 1.23; // Create alias using new name nettype real2_n real3_n; real3_n real3; assign real3 = 1.23; nettype Pkg::real_t real4_n with Pkg::resolver; real4_n real4; assign real4 = 1.23; // TODO when implement net types need to check multiple driver cases, across // submodules initial begin #10; if (real1 != 1.23) $stop; if (real2 != 1.23) $stop; if (real3 != 1.23) $stop; if (Pkg::last_resolve != 1.23) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_enum_bad_dup.py0000755000542200017500000000107515101701376022413 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["--lint-only -Wwarn-VARHIDDEN"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dfg_peephole.v0000644000542200017500000003503415101701376022226 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 `define signal(name, expr) wire [$bits(expr)-1:0] ``name = expr module t ( `include "portlist.vh" // Boilerplate generated by t_dfg_peephole.py rand_a, rand_b, srand_a, srand_b, arand_a, arand_b ); `include "portdecl.vh" // Boilerplate generated by t_dfg_peephole.py input rand_a; input rand_b; input srand_a; input srand_b; input arand_a; input arand_b; wire logic [63:0] rand_a; wire logic [63:0] rand_b; wire logic signed [63:0] srand_a; wire logic signed [63:0] srand_b; // verilator lint_off ASCRANGE wire logic [0:63] arand_a; wire logic [0:63] arand_b; // verilator lint_on ASCRANGE wire logic randbit_a = rand_a[0]; wire logic [127:0] rand_ba = {rand_b, rand_a}; wire logic [127:0] rand_aa = {2{rand_a}}; wire logic [63:0] const_a; wire logic [63:0] const_b; wire logic signed [63:0] sconst_a; wire logic signed [63:0] sconst_b; logic [63:0] array [3:0]; logic [63:0] unitArrayWhole [0:0]; logic [63:0] unitArrayParts [0:0]; assign array[0] = (rand_a << 32) | (rand_a >> 32); assign array[1] = (rand_a << 16) | (rand_a >> 48); assign array[2][3:0] = rand_a[3:0]; always @(rand_b) begin // Intentional non-combinational partial driver array[2][7:4] = rand_a[7:4]; end assign unitArrayWhole[0] = rand_a; assign unitArrayParts[0][1] = rand_a[1]; assign unitArrayParts[0][9] = rand_a[9]; `signal(FOLD_UNARY_LogNot, !const_a[0]); `signal(FOLD_UNARY_Negate, -const_a); `signal(FOLD_UNARY_Not, ~const_a); `signal(FOLD_UNARY_RedAnd, &const_a); `signal(FOLD_UNARY_RedOr, |const_a); `signal(FOLD_UNARY_RedXor, ^const_a); // verilator lint_off WIDTH wire logic [79:0] tmp_FOLD_UNARY_Extend = const_a; wire logic signed [79:0] tmp_FOLD_UNARY_ExtendS = sconst_a; //verilator lint_on WIDTH `signal(FOLD_UNARY_Extend, tmp_FOLD_UNARY_Extend); `signal(FOLD_UNARY_ExtendS, tmp_FOLD_UNARY_ExtendS); `signal(FOLD_BINARY_Add, const_a + const_b); `signal(FOLD_BINARY_And, const_a & const_b); `signal(FOLD_BINARY_Concat, {const_a, const_b}); `signal(FOLD_BINARY_Div, const_a / 64'd3); `signal(FOLD_BINARY_DivS, sconst_a / 64'sd3); `signal(FOLD_BINARY_Eq, const_a == const_b); `signal(FOLD_BINARY_Gt, const_a > const_b); `signal(FOLD_BINARY_GtS, sconst_a > sconst_b); `signal(FOLD_BINARY_Gte, const_a >= const_b); `signal(FOLD_BINARY_GteS, sconst_a >= sconst_b); `signal(FOLD_BINARY_LogAnd, const_a[0] && const_b[0]); `signal(FOLD_BINARY_LogEq, const_a[0] <-> const_b[0]); `signal(FOLD_BINARY_LogIf, const_a[0] -> const_b[0]); `signal(FOLD_BINARY_LogOr, const_a[0] || const_b[0]); `signal(FOLD_BINARY_Lt, const_a < const_b); `signal(FOLD_BINARY_Lt2, const_a < const_a); `signal(FOLD_BINARY_LtS, sconst_a < sconst_b); `signal(FOLD_BINARY_LtS2, sconst_a < sconst_a); `signal(FOLD_BINARY_Lte, const_a <= const_b); `signal(FOLD_BINARY_Lte2, const_a <= const_a); `signal(FOLD_BINARY_LteS, sconst_a <= sconst_b); `signal(FOLD_BINARY_LteS2, sconst_a <= sconst_a); `signal(FOLD_BINARY_ModDiv, const_a % 64'd3); `signal(FOLD_BINARY_ModDivS, sconst_a % 64'sd3); `signal(FOLD_BINARY_Mul, const_a * 64'd3); `signal(FOLD_BINARY_MulS, sconst_a * 64'sd3); `signal(FOLD_BINARY_Neq, const_a != const_b); `signal(FOLD_BINARY_Or, const_a | const_b); `signal(FOLD_BINARY_Pow, const_a ** 64'd2); `signal(FOLD_BINARY_PowSS, sconst_a ** 64'sd2); `signal(FOLD_BINARY_PowSU, sconst_a ** 64'd2); `signal(FOLD_BINARY_PowUS, const_a ** 64'sd2); `signal(FOLD_BINARY_Replicate, {2{const_a}}); `signal(FOLD_BINARY_ShiftL, const_a << 2); `signal(FOLD_BINARY_ShiftR, const_a >> 2); `signal(FOLD_BINARY_ShiftRS, sconst_a >>> 2); `signal(FOLD_BINARY_Sub, const_a - const_b); `signal(FOLD_BINARY_Xor, const_a ^ const_b); `signal(FOLD_ASSOC_BINARY_LHS_OF_RHS_And, (const_a & (const_b & rand_a))); `signal(FOLD_ASSOC_BINARY_LHS_OF_RHS_Or, (const_a | (const_b | rand_a))); `signal(FOLD_ASSOC_BINARY_LHS_OF_RHS_Xor, (const_a ^ (const_b ^ rand_a))); `signal(FOLD_ASSOC_BINARY_LHS_OF_RHS_Add, (const_a + (const_b + rand_a))); `signal(FOLD_ASSOC_BINARY_LHS_OF_RHS_Mul, (const_a * (const_b * rand_a))); `signal(FOLD_ASSOC_BINARY_LHS_OF_RHS_MulS, (sconst_a * (sconst_b * srand_a))); `signal(FOLD_ASSOC_BINARY_LHS_OF_RHS_Concat, {const_a, {const_b, rand_a}}); `signal(FOLD_ASSOC_BINARY_RHS_OF_LHS_And, ((rand_a & const_b) & const_a)); `signal(FOLD_ASSOC_BINARY_RHS_OF_LHS_Or, ((rand_a | const_b) | const_a)); `signal(FOLD_ASSOC_BINARY_RHS_OF_LHS_Xor, ((rand_a ^ const_b) ^ const_a)); `signal(FOLD_ASSOC_BINARY_RHS_OF_LHS_Add, ((rand_a + const_b) + const_a)); `signal(FOLD_ASSOC_BINARY_RHS_OF_LHS_Mul, ((rand_a * const_b) * const_a)); `signal(FOLD_ASSOC_BINARY_RHS_OF_LHS_MulS, ((srand_a * sconst_b) * sconst_a)); `signal(FOLD_ASSOC_BINARY_RHS_OF_LHS_Concat, {{rand_a, const_b}, const_a}); `signal(FOLD_SEL, const_a[3:1]); `signal(SWAP_CONST_IN_COMMUTATIVE_BINARY, rand_a + const_a); `signal(SWAP_NOT_IN_COMMUTATIVE_BINARY, rand_a + ~rand_a); `signal(SWAP_VAR_IN_COMMUTATIVE_BINARY, rand_b + rand_a); `signal(PUSH_BITWISE_OP_THROUGH_CONCAT, 32'h12345678 ^ {8'h0, rand_a[23:0]}); `signal(PUSH_BITWISE_OP_THROUGH_CONCAT_2, 32'h12345678 ^ {rand_b[7:0], rand_a[23:0]}); `signal(PUSH_COMPARE_OP_THROUGH_CONCAT, 4'b1011 == {2'b10, rand_a[1:0]}); `signal(PUSH_REDUCTION_THROUGH_COND_WITH_CONST_BRANCH, |(rand_a[32] ? rand_a[3:0] : 4'h0)); `signal(REPLACE_REDUCTION_OF_CONST_AND, &const_a); `signal(REPLACE_REDUCTION_OF_CONST_OR, |const_a); `signal(REPLACE_REDUCTION_OF_CONST_XOR, ^const_a); `signal(REPLACE_EXTEND, 4'(rand_a[0])); `signal(PUSH_NOT_THROUGH_COND, ~(rand_a[0] ? rand_a[4:0] : 5'hb)); `signal(REMOVE_NOT_NOT, ~~rand_a); `signal(REPLACE_NOT_NEQ, ~(rand_a != rand_b)); `signal(REPLACE_NOT_EQ, ~(srand_a == srand_b)); `signal(REPLACE_NOT_OF_CONST, ~4'd0); `signal(REPLACE_DISTRIBUTIVE_AND_OR_ABAC, ((rand_a >> 10) | (rand_b >> 10)) & ((rand_a >> 10) | (srand_b >> 10))); `signal(REPLACE_DISTRIBUTIVE_AND_OR_ABCA, ((rand_a >> 11) | (rand_b >> 11)) & ((srand_b >> 11) | (rand_a >> 11))); `signal(REPLACE_DISTRIBUTIVE_AND_OR_BAAC, ((rand_b >> 12) | (rand_a >> 12)) & ((rand_a >> 12) | (srand_b >> 12))); `signal(REPLACE_DISTRIBUTIVE_AND_OR_BACA, ((rand_b >> 13) | (rand_a >> 13)) & ((srand_b >> 13) | (rand_a >> 13))); `signal(REPLACE_AND_OF_NOT_AND_NOT, ~rand_a[1] & ~rand_b[1]); `signal(REPLACE_AND_OF_NOT_AND_NEQ, ~rand_a[2] & (rand_b != 64'd2)); `signal(REPLACE_AND_OF_CONST_AND_CONST, const_a & const_b); `signal(REPLACE_AND_WITH_ZERO, 64'd0 & rand_a); `signal(REMOVE_AND_WITH_ONES, -64'd1 & rand_a); `signal(REMOVE_AND_WITH_SELF, ~rand_a & ~rand_a); `signal(REPLACE_CONTRADICTORY_AND, rand_a & ~rand_a); `signal(REPLACE_CONTRADICTORY_AND_3, ~(rand_a + 1) & ((rand_a + 1) & rand_b)); `signal(REPLACE_OR_DISTRIBUTIVE, (rand_a & rand_b) | (rand_a & srand_b)); `signal(REPLACE_DISTRIBUTIVE_OR_AND_ABAC, ((rand_a >> 14) & (rand_b >> 14)) | ((rand_a >> 14) & (srand_b >> 14))); `signal(REPLACE_DISTRIBUTIVE_OR_AND_ABCA, ((rand_a >> 15) & (rand_b >> 15)) | ((srand_b >> 15) & (rand_a >> 15))); `signal(REPLACE_DISTRIBUTIVE_OR_AND_BAAC, ((rand_b >> 16) & (rand_a >> 16)) | ((rand_a >> 16) & (srand_b >> 16))); `signal(REPLACE_DISTRIBUTIVE_OR_AND_BACA, ((rand_b >> 17) & (rand_a >> 17)) | ((srand_b >> 17) & (rand_a >> 17))); `signal(REPLACE_OR_OF_NOT_AND_NOT, ~rand_a[3] | ~rand_b[3]); `signal(REPLACE_OR_OF_NOT_AND_NEQ, ~rand_a[4] | (rand_b != 64'd3)); `signal(REPLACE_OR_OF_CONCAT_ZERO_LHS_AND_CONCAT_RHS_ZERO, {2'd0, rand_a[1:0]} | {rand_b[1:0], 2'd0}); `signal(REPLACE_OR_OF_CONCAT_LHS_ZERO_AND_CONCAT_ZERO_RHS, {rand_a[1:0], 2'd0} | {2'd0, rand_b[1:0]}); `signal(REPLACE_OR_OF_CONST_AND_CONST, const_a | const_b); `signal(REPLACE_OR_WITH_ONES, -64'd1 | rand_a); `signal(REMOVE_OR_WITH_SELF, ~rand_a | ~rand_a); `signal(REMOVE_OR_WITH_ZERO, 64'd0 | rand_a); `signal(REPLACE_TAUTOLOGICAL_OR, rand_a | ~rand_a); `signal(REPLACE_TAUTOLOGICAL_OR_3, ~(rand_a + 1) | ((rand_a + 1) | rand_b)); `signal(REMOVE_SUB_ZERO, rand_a - 64'd0); `signal(REPLACE_SUB_WITH_NOT, rand_a[0] - 1'b1); `signal(REMOVE_REDUNDANT_ZEXT_ON_RHS_OF_SHIFT, rand_a << {2'b0, rand_a[2:0]}); `signal(REPLACE_EQ_OF_CONST_AND_CONST, 4'd0 == 4'd1); `signal(REMOVE_FULL_WIDTH_SEL, rand_a[63:0]); `signal(REMOVE_SEL_FROM_RHS_OF_CONCAT, rand_ba[63:0]); `signal(REMOVE_SEL_FROM_LHS_OF_CONCAT, rand_ba[127:64]); `signal(PUSH_SEL_THROUGH_CONCAT, rand_ba[120:0]); `signal(PUSH_SEL_THROUGH_REPLICATE, rand_aa[0]); `signal(REPLACE_SEL_FROM_CONST, const_a[2]); `signal(REPLACE_CONCAT_OF_CONSTS, {const_a, const_b}); `signal(REPLACE_CONCAT_ZERO_AND_SEL_TOP_WITH_SHIFTR, {62'd0, rand_a[63:62]}); `signal(REPLACE_CONCAT_SEL_BOTTOM_AND_ZERO_WITH_SHIFTL, {rand_a[1:0], 62'd0}); `signal(PUSH_CONCAT_THROUGH_NOTS, {~(rand_a+64'd101), ~(rand_b+64'd101)} ); `signal(REMOVE_CONCAT_OF_ADJOINING_SELS, {rand_a[10:3], rand_a[2:1]}); `signal(REPLACE_NESTED_CONCAT_OF_ADJOINING_SELS_ON_LHS_CAT, {rand_a[2:1], rand_b}); `signal(REPLACE_NESTED_CONCAT_OF_ADJOINING_SELS_ON_RHS_CAT, {rand_b, rand_a[10:3]}); `signal(REPLACE_NESTED_CONCAT_OF_ADJOINING_SELS_ON_LHS, {rand_a[10:3], {rand_a[2:1], rand_b}}); `signal(REPLACE_NESTED_CONCAT_OF_ADJOINING_SELS_ON_RHS, {{rand_b, rand_a[10:3]}, rand_a[2:1]}); `signal(REMOVE_COND_WITH_FALSE_CONDITION, 1'd0 ? rand_a : rand_b); `signal(REMOVE_COND_WITH_TRUE_CONDITION, 1'd1 ? rand_a : rand_b); `signal(REMOVE_COND_WITH_BRANCHES_SAME, rand_a[0] ? ~rand_b : ~rand_b); `signal(SWAP_COND_WITH_NOT_CONDITION, (~rand_a[0] & 1'd1) ? rand_a : rand_b); `signal(SWAP_COND_WITH_NEQ_CONDITION, rand_b != rand_a ? rand_a : rand_b); `signal(PULL_NOTS_THROUGH_COND, rand_a[0] ? ~rand_a[4:0] : ~rand_b[4:0]); `signal(REPLACE_COND_OR_THEN_COND_LHS, (rand_a[0] | rand_b[0] ? (rand_a[0] ? rand_a : rand_b) : srand_a)); `signal(REPLACE_COND_OR_THEN_COND_RHS, (rand_a[0] | rand_b[0] ? (rand_b[0] ? rand_a : rand_b) : srand_a)); `signal(REPLACE_COND_WITH_THEN_BRANCH_COND, rand_a[0] ? rand_a[0] : rand_a[1]); `signal(REPLACE_COND_WITH_THEN_BRANCH_ZERO, rand_a[0] ? 1'd0 : rand_a[1]); `signal(REPLACE_COND_WITH_THEN_BRANCH_ONES, rand_a[0] ? 1'd1 : rand_a[1]); `signal(REPLACE_COND_WITH_ELSE_BRANCH_ZERO, rand_a[0] ? rand_a[1] : 1'd0); `signal(REPLACE_COND_WITH_ELSE_BRANCH_ONES, rand_a[0] ? rand_a[1] : 1'd1); `signal(INLINE_ARRAYSEL_SPLICE, array[0]); `signal(NO_INLINE_ARRAYSEL_SPLICE_PARTIAL, array[2]); `signal(INLINE_ARRAYSEL_UNIT, unitArrayWhole[0]); `signal(NO_INLINE_ARRAYSEL_UNIT_PARTIAL, unitArrayParts[0]); `signal(PUSH_BITWISE_THROUGH_REDUCTION_AND, (&(rand_a + 64'd105)) & (&(rand_b + 64'd108))); `signal(PUSH_BITWISE_THROUGH_REDUCTION_OR, (|(rand_a + 64'd106)) | (|(rand_b + 64'd109))); `signal(PUSH_BITWISE_THROUGH_REDUCTION_XOR, (^(rand_a + 64'd107)) ^ (^(rand_b + 64'd110))); `signal(PUSH_REDUCTION_THROUGH_CONCAT_AND, &{1'd1, rand_b}); `signal(PUSH_REDUCTION_THROUGH_CONCAT_OR, |{1'd1, rand_b}); `signal(PUSH_REDUCTION_THROUGH_CONCAT_XOR, ^{1'd1, rand_b}); `signal(REMOVE_WIDTH_ONE_REDUCTION_AND, &rand_a[0]); `signal(REMOVE_WIDTH_ONE_REDUCTION_OR, |rand_a[0]); `signal(REMOVE_WIDTH_ONE_REDUCTION_XOR, ^rand_a[0]); `signal(REMOVE_XOR_WITH_ZERO, 64'd0 ^ rand_a); `signal(REPLACE_XOR_WITH_SELF, ~rand_a ^ ~rand_a); `signal(REPLACE_XOR_WITH_ONES, -64'd1 ^ rand_a); `signal(REPLACE_COND_DEC, randbit_a ? rand_b - 64'b1 : rand_b); `signal(REPLACE_COND_INC, randbit_a ? rand_b + 64'b1 : rand_b); `signal(NO_REPLACE_COND_DEC, randbit_a ? rand_b - 64'hf000000000000000 : rand_b); `signal(NO_REPLACE_COND_INC, randbit_a ? rand_b + 64'hf000000000000000 : rand_b); `signal(REPLACE_LOGAND_WITH_AND, rand_a[0] && rand_a[1]); `signal(REPLACE_LOGOR_WITH_OR, rand_a[0] || rand_a[1]); `signal(RIGHT_LEANING_ASSOC, (((rand_a + rand_b) + rand_a) + rand_b)); `signal(RIGHT_LEANING_CONCET, {{{rand_a, rand_b}, rand_a}, rand_b}); // Operators that should work wiht mismatched widths `signal(MISMATCHED_ShiftL,const_a << 4'd2); `signal(MISMATCHED_ShiftR,const_a >> 4'd2); `signal(MISMATCHED_ShiftRS, const_a >> 4'd2); `signal(MISMATCHED_PowUU, rand_a ** 4'd5); `signal(MISMATCHED_PowSS, srand_a ** 4'sd5); `signal(MISMATCHED_PowSU, srand_b ** 4'd5); `signal(MISMATCHED_PowUS, rand_b ** 4'sd5); // Some selects need extra temporaries wire [63:0] sel_from_cond = rand_a[0] ? rand_a : const_a; wire [63:0] sel_from_shiftl = rand_a << 10; wire [31:0] sel_from_sel = rand_a[10+:32]; `signal(PUSH_SEL_THROUGH_COND, sel_from_cond[2]); `signal(PUSH_SEL_THROUGH_SHIFTL, sel_from_shiftl[20:0]); `signal(REPLACE_SEL_FROM_SEL, sel_from_sel[4:3]); logic [2:0] sel_from_partial_tmp;; always_comb begin sel_from_partial_tmp[1:0] = 2'd0; if (rand_a[0]) begin sel_from_partial_tmp[0] = rand_b[0]; end end `signal(PUSH_SEL_THROUGH_SPLICE, sel_from_partial_tmp[1:0]); // Asscending ranges `signal(ASCENDNG_SEL, arand_a[0:4]); // verilator lint_off ASCRANGE wire [0:7] ascending_assign; // verilator lint_on ASCRANGE assign ascending_assign[0:3] = arand_a[4:7]; assign ascending_assign[4:7] = arand_b[0:3]; `signal(ASCENDING_ASSIGN, ascending_assign); // Special cases to be covered `signal(REPLICATE_WIDTH, {4'd8{rand_a[0]}}); // Replicate count unsigned, but MSB set if ($bits(REPLICATE_WIDTH) != 8) $fatal("%0d != 8", $bits(REPLICATE_WIDTH)); // Sel from not requires the operand to have a sinle sink, so can't use // the chekc due to the raw expression referencing the operand wire [63:0] sel_from_not_tmp = ~(rand_a >> rand_b[2:0] << rand_a[3:0]); wire sel_from_not = sel_from_not_tmp[2]; always @(posedge randbit_a) if ($c(0)) $display(sel_from_not); // Do not remove signal // Assigned at the end to avoid inlining by other passes assign const_a = 64'h0123456789abcdef; assign const_b = 64'h98badefc10325647; assign sconst_a = 64'hfedcba9876543210; assign sconst_b = 64'hba0123456789cdef; endmodule verilator-5.042/test_regress/t/t_randomize_complex_dynamic_arrays.py0000755000542200017500000000104615101701376026573 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_struct_param.v0000644000542200017500000000301315101701376022301 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Matt Myers. // SPDX-License-Identifier: CC0-1.0 // verilog_format: off `define stop $stop `define checkd(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); // verilog_format: on package config_pkg; typedef struct packed { int UPPER0; struct packed { int USE_QUAD0; int USE_QUAD1; int USE_QUAD2; } mac; int UPPER2; } config_struct_t; function automatic config_struct_t static_config(int selector); config_struct_t return_config; return_config = '0; return_config.UPPER0 = 10; return_config.UPPER2 = 20; return_config.mac.USE_QUAD0 = 4; return_config.mac.USE_QUAD2 = 6; case (selector) 1: return_config.mac.USE_QUAD1 = 5; endcase return return_config; endfunction endpackage module t; import config_pkg::*; localparam config_struct_t MY_CONFIG = static_config(1); struct_submodule #(.MY_CONFIG(MY_CONFIG)) a_submodule_I (); endmodule module struct_submodule import config_pkg::*; #( parameter config_struct_t MY_CONFIG = '0 ); initial begin `checkd(MY_CONFIG.UPPER0, 10); `checkd(MY_CONFIG.mac.USE_QUAD0, 4); `checkd(MY_CONFIG.mac.USE_QUAD1, 5); `checkd(MY_CONFIG.mac.USE_QUAD2, 6); `checkd(MY_CONFIG.UPPER2, 20); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_math_shift_rep.v0000644000542200017500000000402415101701376022574 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; //bug765; disappears if add this wire //wire [7:0] a = (crc[7] ? {7'b0,crc[0]} : crc[7:0]); // favor low values wire [7:0] a = crc[7:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [15:0] y; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .y (y[15:0]), // Inputs .a (a[7:0])); // Aggregate outputs into a single result vector wire [63:0] result = {48'h0, y}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h0 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs y, // Inputs a ); input signed [7:0] a; output [15:0] y; // verilator lint_off WIDTH assign y = ~66'd0 <<< {4{a}}; // verilator lint_on WIDTH endmodule verilator-5.042/test_regress/t/t_nba_assign_on_rhs.v0000644000542200017500000000133415101701376023255 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; int x; int y; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 0) begin x <= 1; end else if (cyc == 1) begin // verilator lint_off ASSIGNEQEXPR y <= (x = 2); // verilator lint_on ASSIGNEQEXPR end else begin if (x != 2) $stop; if (y != 2) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_mem_func.py0000755000542200017500000000073415101701376021563 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_constraint_mode.py0000755000542200017500000000104615101701376023157 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_preproc_kwd_bad.py0000755000542200017500000000103515101701376023112 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, verilator_flags2=['--no-std'], expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_event_control_assign.py0000755000542200017500000000114215101701376024211 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile( verilator_flags2=["--binary"], make_main=False, # Multithreading would cause a warning on event assignments threads=1) test.execute() test.passes() verilator-5.042/test_regress/t/t_flag_relinc.v0000644000542200017500000000060715101701376022050 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2017 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; t_flag_relinc_sub sub (); endmodule verilator-5.042/test_regress/t/t_clocking_out_on_change.py0000755000542200017500000000077115101701376024454 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_dpi_result_type.out0000644000542200017500000000252515101701376023361 0ustar mahmoudyfreeshelli_void 0 i_chandle 0 i_string 0 i_bit 0 i_logic 0 i_chandle_t 0 i_string_t 0 i_bit_t 0 i_logic_t 0 i_array_2_state_1 0 i_array_2_state_32 0 i_struct_2_state_1 0 i_struct_2_state_32 0 i_union_2_state_1 0 i_union_2_state_32 0 e_void 0 e_chandle 0 e_string 0 e_bit 0 e_logic 0 e_chandle_t 0 e_string_t 0 e_bit_t 0 e_logic_t 0 e_array_2_state_1 0 e_array_2_state_32 0 e_struct_2_state_1 0 e_struct_2_state_32 0 e_union_2_state_1 0 e_union_2_state_32 0 i_void 1 i_chandle 1 i_string 1 i_bit 1 i_logic 1 i_chandle_t 1 i_string_t 1 i_bit_t 1 i_logic_t 1 i_array_2_state_1 1 i_array_2_state_32 1 i_struct_2_state_1 1 i_struct_2_state_32 1 i_union_2_state_1 1 i_union_2_state_32 1 e_void 1 e_chandle 1 e_string 1 e_bit 1 e_logic 1 e_chandle_t 1 e_string_t 1 e_bit_t 1 e_logic_t 1 e_array_2_state_1 1 e_array_2_state_32 1 e_struct_2_state_1 1 e_struct_2_state_32 1 e_union_2_state_1 1 e_union_2_state_32 1 i_void 2 i_chandle 2 i_string 2 i_bit 2 i_logic 2 i_chandle_t 2 i_string_t 2 i_bit_t 2 i_logic_t 2 i_array_2_state_1 2 i_array_2_state_32 2 i_struct_2_state_1 2 i_struct_2_state_32 2 i_union_2_state_1 2 i_union_2_state_32 2 e_void 2 e_chandle 2 e_string 2 e_bit 2 e_logic 2 e_chandle_t 2 e_string_t 2 e_bit_t 2 e_logic_t 2 e_array_2_state_1 2 e_array_2_state_32 2 e_struct_2_state_1 2 e_struct_2_state_32 2 e_union_2_state_1 2 e_union_2_state_32 2 *-* All Finished *-* verilator-5.042/test_regress/t/t_flag_no_unlimited_stack.v0000644000542200017500000000035215101701376024444 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; endmodule verilator-5.042/test_regress/t/t_class_ref_ref.v0000644000542200017500000000061215101701376022374 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls#(type T = bit); endclass module t; Cls#(bit) cb; Cls#(Cls#(bit)) ccb; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_typedef_signed.py0000755000542200017500000000073415101701376022763 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_virtual_interface_delayed.v0000644000542200017500000000174015101701376024777 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); interface Ifc; bit [7:0] rdata; endinterface class drv_c; virtual Ifc vif; virtual task run(); #100; `checkh(vif.rdata, 8'haa); #100; `checkh(vif.rdata, 8'haa); #100; endtask endclass module dut (output wire [7:0] rd_val); assign rd_val = 8'haa; endmodule module m; drv_c d_0; Ifc u_Ifc (); dut u_dut (.rd_val (u_Ifc.rdata)); initial begin d_0 = new(); d_0.vif = u_Ifc; //u_Ifc.rdata = 10; d_0.run(); $write("*-* All Finished *-*\n"); $finish(2); end endmodule verilator-5.042/test_regress/t/t_math_cmp.py0000755000542200017500000000073415101701376021562 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_param_subtype_bad_paren.py0000755000542200017500000000110615101701376026017 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.top_filename = "t/t_class_param_subtype.v" test.lint(fails=True, v_flags2=['+define+BAD_PAREN'], expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_func_under2.v0000644000542200017500000000174515101701376022021 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // bug598 module t (/*AUTOARG*/ // Outputs val, // Inputs clk ); input clk; output integer val; integer dbg_addr = 0; function func1; input en; input [31:0] a; func1 = en && (a == 1); endfunction function func2; input en; input [31:0] a; func2 = en && (a == 2); endfunction always @(posedge clk) begin case( 1'b1 ) // This line is OK: func1(1'b1, dbg_addr) : val = 1; // This fails: // %Error: Internal Error: test.v:23: ../V3Task.cpp:993: Function not underneath a statement func2(1'b1, dbg_addr) : val = 2; default : val = 0; endcase // $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_order_dpi_export_2.cpp0000644000542200017500000000213615101701376023710 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2021 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include #include #include void toggle_other_clk(svBit val) { set_other_clk(val); } int main(int argc, char* argv[]) { VM_PREFIX* const tb = new VM_PREFIX; tb->contextp()->commandArgs(argc, argv); bool clk = true; while (!tb->contextp()->gotFinish()) { // Timeout if (tb->contextp()->time() > 100000) break; // Toggle and set main clock clk = !clk; tb->clk = clk; // Eval tb->eval(); // Advance time tb->contextp()->timeInc(500); } delete tb; return 0; } verilator-5.042/test_regress/t/t_inst_param_override_bad.py0000755000542200017500000000076615101701376024641 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_tri_pullup.cpp0000644000542200017500000000272615101701376022323 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2008 by Lane Brooks. // SPDX-License-Identifier: CC0-1.0 #include VM_PREFIX_INCLUDE VM_PREFIX* tb = nullptr; double sc_time_stamp() { return 0; } bool check() { bool pass; int Z, Y, X; if (tb->OE) { Z = tb->A; Y = tb->A; X = tb->A; } else { Z = 1; Y = 0; X = 1; } #ifdef TEST_VERBOSE bool verbose = true; #else bool verbose = false; #endif if (tb->Z == Z && tb->Y == Y && tb->X == X) { if (verbose) printf("PASS: "); pass = true; } else { printf("%%E-FAIL: "); verbose = true; pass = false; } if (verbose) printf("OE=%d A=%d X=%d xexp=%d Y=%d yexp=%d Z=%d zexp=%d\n", tb->OE, tb->A, tb->X, X, tb->Y, Y, tb->Z, Z); return pass; } int main() { Verilated::debug(0); tb = new VM_PREFIX{"tb"}; // loop through every possibility and check the result bool pass = true; for (tb->OE = 0; tb->OE < 2; tb->OE++) { for (tb->A = 0; tb->A < 2; tb->A++) { tb->eval(); if (!check()) pass = false; } } if (pass) { VL_PRINTF("*-* All Finished *-*\n"); tb->final(); } else { vl_fatal(__FILE__, __LINE__, "top", "Unexpected results from pullup test\n"); } VL_DO_DANGLING(delete tb, tb); return 0; } verilator-5.042/test_regress/t/t_math_red.py0000755000542200017500000000073415101701376021555 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_type_compare.v0000644000542200017500000000350515101701376022272 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module Sub #(parameter type T = type(logic[11:0])); endmodule module t; int case_ok; Sub #(.T(int)) sub(); typedef logic [12:0] logic12_t; // Generate if if (type(logic[12:0]) !== type(logic[12:0])) initial $stop; if (type(logic[12:0]) != type(logic12_t)) initial $stop; if (type(logic[12:0]) !== type(logic12_t)) initial $stop; if (type(logic[22:0]) == type(logic12_t)) initial $stop; if (type(logic[22:0]) === type(logic12_t)) initial $stop; // Generate case case (type(real)) type(int): initial $stop; type(real): ; default: initial $stop; endcase initial begin if (type(real) == type(logic[12:0])) $stop; if (type(real) === type(logic[12:0])) $stop; if (type(real) != type(real)) $stop; if (type(real) !== type(real)) $stop; if (type(logic[12:0]) !== type(logic[12:0])) $stop; if (type(logic[12:0]) != type(logic12_t)) $stop; if (type(logic[12:0]) !== type(logic12_t)) $stop; if (type(logic[22:0]) == type(logic12_t)) $stop; if (type(logic[22:0]) === type(logic12_t)) $stop; // Item selected case (type(real)) type(real): case_ok = 1; type(int): $stop; type(chandle): $stop; default: $stop; endcase if (case_ok != 1) $stop; // Default selected case (type(real)) type(int): $stop; default: case_ok = 2; endcase if (case_ok != 2) $stop; // No body selected case (type(real)) type(int): $stop; endcase if (case_ok != 2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_trace_complex_structs_fst_sc.out0000644000542200017500000001243615101701376026125 0ustar mahmoudyfreeshell$date Sat Apr 5 13:56:24 2025 $end $version fstWriter $end $timescale 1ps $end $scope module top $end $attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end $attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end $scope module $unit $end $var bit 1 ! global_bit $end $upscope $end $scope module t $end $var wire 1 " clk $end $var integer 32 # cyc [31:0] $end $scope struct v_strp $end $var bit 1 $ b1 $end $var bit 1 % b0 $end $upscope $end $scope struct v_strp_strp $end $scope struct x1 $end $var bit 1 & b1 $end $var bit 1 ' b0 $end $upscope $end $scope struct x0 $end $var bit 1 ( b1 $end $var bit 1 ) b0 $end $upscope $end $upscope $end $scope union v_unip_strp $end $scope struct x1 $end $var bit 1 * b1 $end $var bit 1 + b0 $end $upscope $end $scope struct x0 $end $var bit 1 * b1 $end $var bit 1 + b0 $end $upscope $end $upscope $end $var bit 2 , v_arrp [2:1] $end $var bit 2 - v_arrp_arrp[3] [2:1] $end $var bit 2 . v_arrp_arrp[4] [2:1] $end $scope struct v_arrp_strp[3] $end $var bit 1 / b1 $end $var bit 1 0 b0 $end $upscope $end $scope struct v_arrp_strp[4] $end $var bit 1 1 b1 $end $var bit 1 2 b0 $end $upscope $end $var bit 1 3 v_arru[1] $end $var bit 1 4 v_arru[2] $end $var bit 1 5 v_arru_arru[3][1] $end $var bit 1 6 v_arru_arru[3][2] $end $var bit 1 7 v_arru_arru[4][1] $end $var bit 1 8 v_arru_arru[4][2] $end $var bit 2 9 v_arru_arrp[3] [2:1] $end $var bit 2 : v_arru_arrp[4] [2:1] $end $scope struct v_arru_strp[3] $end $var bit 1 ; b1 $end $var bit 1 < b0 $end $upscope $end $scope struct v_arru_strp[4] $end $var bit 1 = b1 $end $var bit 1 > b0 $end $upscope $end $var real 64 ? v_real $end $var real 64 @ v_arr_real[0] $end $var real 64 A v_arr_real[1] $end $var longint 64 B v_chandle [63:0] $end $scope struct v_str32x2[0] $end $var logic 32 C data [31:0] $end $upscope $end $scope struct v_str32x2[1] $end $var logic 32 D data [31:0] $end $upscope $end $attrbegin misc 07 "" 1 $end $var int 32 E v_enumed [31:0] $end $attrbegin misc 07 "" 1 $end $var int 32 F v_enumed2 [31:0] $end $attrbegin misc 07 "" 2 $end $var logic 3 G v_enumb [2:0] $end $scope struct v_enumb2_str $end $attrbegin misc 07 "" 2 $end $var logic 3 H a [2:0] $end $attrbegin misc 07 "" 2 $end $var logic 3 I b [2:0] $end $upscope $end $var logic 8 J unpacked_array[-2] [7:0] $end $var logic 8 K unpacked_array[-1] [7:0] $end $var logic 8 L unpacked_array[0] [7:0] $end $var bit 1 M LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end $scope module unnamedblk1 $end $var integer 32 N b [31:0] $end $scope module unnamedblk2 $end $var integer 32 O a [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b00000000000000000000000000000000 O b00000000000000000000000000000000 N 0M b00000000 L b00000000 K b00000000 J b000 I b000 H b000 G b00000000000000000000000000000000 F b00000000000000000000000000000000 E b00000000000000000000000000000000 D b00000000000000000000000011111111 C b0000000000000000000000000000000000000000000000000000000000000000 B r0 A r0 @ r0 ? 0> 0= 0< 0; b00 : b00 9 08 07 06 05 04 03 02 01 00 0/ b00 . b00 - b00 , 0+ 0* 0) 0( 0' 0& 0% 0$ b00000000000000000000000000000000 # 0" 1! $end #10 1" b00000000000000000000000000000001 # 1$ 1% 1& 1' 1( 1) 1* 1+ b11 , b11 - b11 . 1/ 10 11 12 b11 9 b11 : 1; 1< 1= 1> r0.1 ? r0.2 @ r0.3 A b00000000000000000000000011111110 C b00000000000000000000000000000001 D b00000000000000000000000000000001 E b00000000000000000000000000000010 F b111 G b00000000000000000000000000000101 N b00000000000000000000000000000101 O #15 0" #20 1" b110 G b00000000000000000000000000000100 F b00000000000000000000000000000010 E b00000000000000000000000000000010 D b00000000000000000000000011111101 C r0.6 A r0.4 @ r0.2 ? 0> 0= 0< 0; b00 : b00 9 02 01 00 0/ b00 . b00 - b00 , 0+ 0* 0) 0( 0' 0& 0% 0$ b00000000000000000000000000000010 # b111 H b111 I #25 0" #30 1" b110 I b110 H b00000000000000000000000000000011 # 1$ 1% 1& 1' 1( 1) 1* 1+ b11 , b11 - b11 . 1/ 10 11 12 b11 9 b11 : 1; 1< 1= 1> r0.3 ? r0.6000000000000001 @ r0.8999999999999999 A b00000000000000000000000011111100 C b00000000000000000000000000000011 D b00000000000000000000000000000011 E b00000000000000000000000000000110 F b101 G #35 0" #40 1" b100 G b00000000000000000000000000001000 F b00000000000000000000000000000100 E b00000000000000000000000000000100 D b00000000000000000000000011111011 C r1.2 A r0.8 @ r0.4 ? 0> 0= 0< 0; b00 : b00 9 02 01 00 0/ b00 . b00 - b00 , 0+ 0* 0) 0( 0' 0& 0% 0$ b00000000000000000000000000000100 # b101 H b101 I #45 0" #50 1" b100 I b100 H b00000000000000000000000000000101 # 1$ 1% 1& 1' 1( 1) 1* 1+ b11 , b11 - b11 . 1/ 10 11 12 b11 9 b11 : 1; 1< 1= 1> r0.5 ? r1 @ r1.5 A b00000000000000000000000011111010 C b00000000000000000000000000000101 D b00000000000000000000000000000101 E b00000000000000000000000000001010 F b011 G #55 0" #60 1" b010 G b00000000000000000000000000001100 F b00000000000000000000000000000110 E b00000000000000000000000000000110 D b00000000000000000000000011111001 C r1.8 A r1.2 @ r0.6 ? 0> 0= 0< 0; b00 : b00 9 02 01 00 0/ b00 . b00 - b00 , 0+ 0* 0) 0( 0' 0& 0% 0$ b00000000000000000000000000000110 # b011 H b011 I #64 verilator-5.042/test_regress/t/t_concat_large.v0000644000542200017500000000073315101701376022224 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2015 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg [32767:0] a; initial begin // verilator lint_off WIDTHCONCAT a = {32768{1'b1}}; // verilator lint_on WIDTHCONCAT if (a[32000] != 1'b1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_sys_fstrobe.v0000644000542200017500000000242615101701376022146 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" module t(/*AUTOARG*/ // Inputs clk ); input clk; int cyc = 0; int fd; // Test loop always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 5) begin fd = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/open.log"}, "w"); end else if (cyc == 10) begin $fstrobe(fd, "[%0t] cyc=%0d", $time, cyc); $fstrobe(fd, "[%0t] cyc=%0d also", $time, cyc); end else if (cyc == 17) begin $fstrobeb(fd, cyc, "b"); end else if (cyc == 18) begin $fstrobeh(fd, cyc, "h"); end else if (cyc == 19) begin $fstrobeo(fd, cyc, "o"); end else if (cyc == 22) begin $fstrobe(fd, "[%0t] cyc=%0d new-strobe", $time, cyc); end else if (cyc == 24) begin $monitoroff; end else if (cyc == 26) begin $monitoron; end else if (cyc == 27) begin $fclose(fd); end else if (cyc == 30) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_gen_mislevel.v0000644000542200017500000000126215101701376022252 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 /// We define the modules in "backward" order. module d; endmodule module b; generate if (1) begin c c1 (); c c2 (); end endgenerate endmodule module c; generate if (1) begin d d1 (); d d2 (); end endgenerate endmodule module a; generate if (1) begin b b1 (); b b2 (); end endgenerate endmodule module t; a a1 (); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_class_param_extends2.py0000755000542200017500000000073415101701376024073 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_tri_array_bufif.py0000755000542200017500000000073415101701376023141 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_math_synmul_mul.v0000644000542200017500000120467415101701376023033 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Mahesh Kumashikar // SPDX-License-Identifier: CC0-1.0 module t_math_synmul_mul (/*AUTOARG*/ // Outputs product_d4, // Inputs clk, enable, negate, datA, datB ); input clk; input enable; input negate; input [31:0] datA; input [31:0] datB; // verilator lint_off UNOPTFLAT output reg [64:0] product_d4; reg [33:0] datA_d1r; reg [33:0] datB_d1r; always @ (posedge clk) begin if (enable) begin datA_d1r <= {2'b0,datA}; datB_d1r <= {2'b0,datB}; // The extra multiplier bits were for signed, for this // test we've ripped that out if (negate) $stop; end end reg en_d1; reg en_d2; reg en_d3; always @ (posedge clk) begin en_d1 <= enable; en_d2 <= en_d1; en_d3 <= en_d2; end wire [63:0] prod_d3; smmultiplier_34_34 mul (.OPA(datA_d1r), .OPB(datB_d1r), .RESULT(prod_d3), /*AUTOINST*/ // Inputs .clk (clk), .en_d1 (en_d1), .en_d2 (en_d2)); always @ (posedge clk) begin if (en_d3) begin product_d4 <= {1'b0,prod_d3}; end end endmodule // The below was originally generated by the "Synthesizable Arithmetic Module Generator" // at http://modgen.fysel.ntnu.no/~pihl/iwlas98/ then cleaned up by hand. // Unfortunately the generator no longer appears available. Please contact // us if you know otherwise. // verilog_format: off module smmultiplier_34_34 ( input clk, input en_d1, input en_d2, input [33:0] OPA, input [33:0] OPB, output [63:0] RESULT ); wire [628:0] PPBIT; wire [66:0] INT_CARRY; wire [66:0] INT_SUM; smboothcoder_34_34 db (.OPA(OPA[33:0]), .OPB(OPB[33:0]), .SUMMAND(PPBIT[628:0]) ); smwallace_34_34 dw (.SUMMAND(PPBIT[628:0]), .CARRY(INT_CARRY[66:1]), .SUM(INT_SUM[66:0]), /*AUTOINST*/ // Inputs .clk (clk), .en_d1 (en_d1), .en_d2 (en_d2)); assign INT_CARRY[0] = 1'b0; smdblcadder_128_128 dd (.OPA(INT_SUM[63:0]), .OPB(INT_CARRY[63:0]), .CIN (1'b0), .SUM(RESULT)); endmodule module smdblcadder_128_128 (OPA, OPB, CIN, SUM); input [63:0] OPA; input [63:0] OPB; input CIN; output [63:0] SUM; wire [63:0] INTPROP; wire [63:0] INTGEN; wire [0:0] PBIT; wire [63:0] CARRY; smprestage_128 dp (OPA[63:0], OPB[63:0], CIN, INTPROP, INTGEN); smdblctree_128 dd (INTPROP[63:0], INTGEN[63:0], CARRY[63:0], PBIT); smxorstage_128 dx (OPA[63:0], OPB[63:0], PBIT[0], CARRY[63:0], SUM); endmodule module smdblctree_128 (PIN, GIN, GOUT, POUT); input [63:0] PIN; input [63:0] GIN; output [63:0] GOUT; output [0:0] POUT; wire [63:0] INTPROP_0; wire [63:0] INTGEN_0; wire [63:0] INTPROP_1; wire [63:0] INTGEN_1; wire [63:0] INTPROP_2; wire [63:0] INTGEN_2; wire [63:0] INTPROP_3; wire [63:0] INTGEN_3; wire [63:0] INTPROP_4; wire [63:0] INTGEN_4; wire [63:0] INTPROP_5; wire [63:0] INTGEN_5; smdblc_0_128 ddb0 (.PIN(PIN), .GIN(GIN), .POUT(INTPROP_0), .GOUT(INTGEN_0) ); smdblc_1_128 ddb1 (.PIN(INTPROP_0), .GIN(INTGEN_0), .POUT(INTPROP_1), .GOUT(INTGEN_1) ); smdblc_2_128 ddb2 (.PIN(INTPROP_1), .GIN(INTGEN_1), .POUT(INTPROP_2), .GOUT(INTGEN_2) ); smdblc_3_128 ddb3 (.PIN(INTPROP_2), .GIN(INTGEN_2), .POUT(INTPROP_3), .GOUT(INTGEN_3) ); smdblc_4_128 ddb4 (.PIN(INTPROP_3), .GIN(INTGEN_3), .POUT(INTPROP_4), .GOUT(INTGEN_4) ); smdblc_5_128 ddb5 (.PIN(INTPROP_4), .GIN(INTGEN_4), .POUT(INTPROP_5), .GOUT(INTGEN_5) ); smdblc_6_128 ddb6 (.PIN(INTPROP_5), .GIN(INTGEN_5), .POUT(POUT), .GOUT(GOUT) ); endmodule module smwallace_34_34 ( input clk, input en_d1, input en_d2, input [628:0] SUMMAND, output [65:0] CARRY, output [66:0] SUM ); wire [628:0] LATCHED_PP; wire [551:0] INT_CARRY; wire [687:0] INT_SUM; smffa dla0 (.D(SUMMAND[0]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[0]) ); smffa dla1 (.D(SUMMAND[1]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[1]) ); smhalfadder dha0 (.DATA_A (LATCHED_PP[0]), .DATA_B (LATCHED_PP[1]), .SAVE (INT_SUM[0]), .CARRY (INT_CARRY[0]) ); smffb dla2 (.D(INT_SUM[0]), .clk(clk), .en_d2(en_d2), .Q(SUM[0]) ); smffb dla3 (.D(INT_CARRY[0]), .clk(clk), .en_d2(en_d2), .Q(CARRY[0]) ); smffa dla4 (.D(SUMMAND[2]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[2]) ); assign INT_SUM[1] = LATCHED_PP[2]; assign CARRY[1] = 1'b0; smffb dla5 (.D(INT_SUM[1]), .clk(clk), .en_d2(en_d2), .Q(SUM[1]) ); smffa dla6 (.D(SUMMAND[3]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[3]) ); smffa dla7 (.D(SUMMAND[4]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[4]) ); smffa dla8 (.D(SUMMAND[5]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[5]) ); smfulladder dfa0 (.DATA_A (LATCHED_PP[3]), .DATA_B (LATCHED_PP[4]), .DATA_C (LATCHED_PP[5]), .SAVE (INT_SUM[2]), .CARRY (INT_CARRY[1]) ); smffb dla9 (.D(INT_SUM[2]), .clk(clk), .en_d2(en_d2), .Q(SUM[2]) ); smffb dla10 (.D(INT_CARRY[1]), .clk(clk), .en_d2(en_d2), .Q(CARRY[2]) ); smffa dla11 (.D(SUMMAND[6]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[6]) ); smffa dla12 (.D(SUMMAND[7]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[7]) ); smhalfadder dha1 (.DATA_A (LATCHED_PP[6]), .DATA_B (LATCHED_PP[7]), .SAVE (INT_SUM[3]), .CARRY (INT_CARRY[2]) ); smffb dla13 (.D(INT_SUM[3]), .clk(clk), .en_d2(en_d2), .Q(SUM[3]) ); smffb dla14 (.D(INT_CARRY[2]), .clk(clk), .en_d2(en_d2), .Q(CARRY[3]) ); smffa dla15 (.D(SUMMAND[8]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[8]) ); smffa dla16 (.D(SUMMAND[9]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[9]) ); smffa dla17 (.D(SUMMAND[10]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[10]) ); smfulladder dfa1 (.DATA_A (LATCHED_PP[8]), .DATA_B (LATCHED_PP[9]), .DATA_C (LATCHED_PP[10]), .SAVE (INT_SUM[4]), .CARRY (INT_CARRY[4]) ); smffa dla18 (.D(SUMMAND[11]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[11]) ); assign INT_SUM[5] = LATCHED_PP[11]; smhalfadder dha2 (.DATA_A (INT_SUM[4]), .DATA_B (INT_SUM[5]), .SAVE (INT_SUM[6]), .CARRY (INT_CARRY[3]) ); smffb dla19 (.D(INT_SUM[6]), .clk(clk), .en_d2(en_d2), .Q(SUM[4]) ); smffb dla20 (.D(INT_CARRY[3]), .clk(clk), .en_d2(en_d2), .Q(CARRY[4]) ); smffa dla21 (.D(SUMMAND[12]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[12]) ); smffa dla22 (.D(SUMMAND[13]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[13]) ); smffa dla23 (.D(SUMMAND[14]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[14]) ); smfulladder dfa2 (.DATA_A (LATCHED_PP[12]), .DATA_B (LATCHED_PP[13]), .DATA_C (LATCHED_PP[14]), .SAVE (INT_SUM[7]), .CARRY (INT_CARRY[6]) ); smhalfadder dha3 (.DATA_A (INT_SUM[7]), .DATA_B (INT_CARRY[4]), .SAVE (INT_SUM[8]), .CARRY (INT_CARRY[5]) ); smffb dla24 (.D(INT_SUM[8]), .clk(clk), .en_d2(en_d2), .Q(SUM[5]) ); smffb dla25 (.D(INT_CARRY[5]), .clk(clk), .en_d2(en_d2), .Q(CARRY[5]) ); smffa dla26 (.D(SUMMAND[15]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[15]) ); smffa dla27 (.D(SUMMAND[16]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[16]) ); smffa dla28 (.D(SUMMAND[17]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[17]) ); smfulladder dfa3 (.DATA_A (LATCHED_PP[15]), .DATA_B (LATCHED_PP[16]), .DATA_C (LATCHED_PP[17]), .SAVE (INT_SUM[9]), .CARRY (INT_CARRY[8]) ); smffa dla29 (.D(SUMMAND[18]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[18]) ); smffa dla30 (.D(SUMMAND[19]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[19]) ); smhalfadder dha4 (.DATA_A (LATCHED_PP[18]), .DATA_B (LATCHED_PP[19]), .SAVE (INT_SUM[10]), .CARRY (INT_CARRY[9]) ); smfulladder dfa4 (.DATA_A (INT_SUM[9]), .DATA_B (INT_SUM[10]), .DATA_C (INT_CARRY[6]), .SAVE (INT_SUM[11]), .CARRY (INT_CARRY[7]) ); smffb dla31 (.D(INT_SUM[11]), .clk(clk), .en_d2(en_d2), .Q(SUM[6]) ); smffb dla32 (.D(INT_CARRY[7]), .clk(clk), .en_d2(en_d2), .Q(CARRY[6]) ); smffa dla33 (.D(SUMMAND[20]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[20]) ); smffa dla34 (.D(SUMMAND[21]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[21]) ); smffa dla35 (.D(SUMMAND[22]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[22]) ); smfulladder dfa5 (.DATA_A (LATCHED_PP[20]), .DATA_B (LATCHED_PP[21]), .DATA_C (LATCHED_PP[22]), .SAVE (INT_SUM[12]), .CARRY (INT_CARRY[11]) ); smffa dla36 (.D(SUMMAND[23]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[23]) ); assign INT_SUM[13] = LATCHED_PP[23]; smfulladder dfa6 (.DATA_A (INT_SUM[12]), .DATA_B (INT_SUM[13]), .DATA_C (INT_CARRY[8]), .SAVE (INT_SUM[14]), .CARRY (INT_CARRY[12]) ); assign INT_SUM[15] = INT_CARRY[9]; smhalfadder dha5 (.DATA_A (INT_SUM[14]), .DATA_B (INT_SUM[15]), .SAVE (INT_SUM[16]), .CARRY (INT_CARRY[10]) ); smffb dla37 (.D(INT_SUM[16]), .clk(clk), .en_d2(en_d2), .Q(SUM[7]) ); smffb dla38 (.D(INT_CARRY[10]), .clk(clk), .en_d2(en_d2), .Q(CARRY[7]) ); smffa dla39 (.D(SUMMAND[24]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[24]) ); smffa dla40 (.D(SUMMAND[25]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[25]) ); smffa dla41 (.D(SUMMAND[26]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[26]) ); smfulladder dfa7 (.DATA_A (LATCHED_PP[24]), .DATA_B (LATCHED_PP[25]), .DATA_C (LATCHED_PP[26]), .SAVE (INT_SUM[17]), .CARRY (INT_CARRY[14]) ); smffa dla42 (.D(SUMMAND[27]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[27]) ); smffa dla43 (.D(SUMMAND[28]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[28]) ); smffa dla44 (.D(SUMMAND[29]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[29]) ); smfulladder dfa8 (.DATA_A (LATCHED_PP[27]), .DATA_B (LATCHED_PP[28]), .DATA_C (LATCHED_PP[29]), .SAVE (INT_SUM[18]), .CARRY (INT_CARRY[15]) ); smfulladder dfa9 (.DATA_A (INT_SUM[17]), .DATA_B (INT_SUM[18]), .DATA_C (INT_CARRY[11]), .SAVE (INT_SUM[19]), .CARRY (INT_CARRY[16]) ); smhalfadder dha6 (.DATA_A (INT_SUM[19]), .DATA_B (INT_CARRY[12]), .SAVE (INT_SUM[20]), .CARRY (INT_CARRY[13]) ); smffb dla45 (.D(INT_SUM[20]), .clk(clk), .en_d2(en_d2), .Q(SUM[8]) ); smffb dla46 (.D(INT_CARRY[13]), .clk(clk), .en_d2(en_d2), .Q(CARRY[8]) ); smffa dla47 (.D(SUMMAND[30]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[30]) ); smffa dla48 (.D(SUMMAND[31]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[31]) ); smffa dla49 (.D(SUMMAND[32]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[32]) ); smfulladder dfa10 (.DATA_A (LATCHED_PP[30]), .DATA_B (LATCHED_PP[31]), .DATA_C (LATCHED_PP[32]), .SAVE (INT_SUM[21]), .CARRY (INT_CARRY[18]) ); smffa dla50 (.D(SUMMAND[33]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[33]) ); smffa dla51 (.D(SUMMAND[34]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[34]) ); smhalfadder dha7 (.DATA_A (LATCHED_PP[33]), .DATA_B (LATCHED_PP[34]), .SAVE (INT_SUM[22]), .CARRY (INT_CARRY[19]) ); smfulladder dfa11 (.DATA_A (INT_SUM[21]), .DATA_B (INT_SUM[22]), .DATA_C (INT_CARRY[14]), .SAVE (INT_SUM[23]), .CARRY (INT_CARRY[20]) ); assign INT_SUM[24] = INT_CARRY[15]; smfulladder dfa12 (.DATA_A (INT_SUM[23]), .DATA_B (INT_SUM[24]), .DATA_C (INT_CARRY[16]), .SAVE (INT_SUM[25]), .CARRY (INT_CARRY[17]) ); smffb dla52 (.D(INT_SUM[25]), .clk(clk), .en_d2(en_d2), .Q(SUM[9]) ); smffb dla53 (.D(INT_CARRY[17]), .clk(clk), .en_d2(en_d2), .Q(CARRY[9]) ); smffa dla54 (.D(SUMMAND[35]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[35]) ); smffa dla55 (.D(SUMMAND[36]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[36]) ); smffa dla56 (.D(SUMMAND[37]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[37]) ); smfulladder dfa13 (.DATA_A (LATCHED_PP[35]), .DATA_B (LATCHED_PP[36]), .DATA_C (LATCHED_PP[37]), .SAVE (INT_SUM[26]), .CARRY (INT_CARRY[22]) ); smffa dla57 (.D(SUMMAND[38]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[38]) ); smffa dla58 (.D(SUMMAND[39]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[39]) ); smffa dla59 (.D(SUMMAND[40]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[40]) ); smfulladder dfa14 (.DATA_A (LATCHED_PP[38]), .DATA_B (LATCHED_PP[39]), .DATA_C (LATCHED_PP[40]), .SAVE (INT_SUM[27]), .CARRY (INT_CARRY[23]) ); smffa dla60 (.D(SUMMAND[41]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[41]) ); assign INT_SUM[28] = LATCHED_PP[41]; smfulladder dfa15 (.DATA_A (INT_SUM[26]), .DATA_B (INT_SUM[27]), .DATA_C (INT_SUM[28]), .SAVE (INT_SUM[29]), .CARRY (INT_CARRY[24]) ); smhalfadder dha8 (.DATA_A (INT_CARRY[18]), .DATA_B (INT_CARRY[19]), .SAVE (INT_SUM[30]), .CARRY (INT_CARRY[25]) ); smfulladder dfa16 (.DATA_A (INT_SUM[29]), .DATA_B (INT_SUM[30]), .DATA_C (INT_CARRY[20]), .SAVE (INT_SUM[31]), .CARRY (INT_CARRY[21]) ); smffb dla61 (.D(INT_SUM[31]), .clk(clk), .en_d2(en_d2), .Q(SUM[10]) ); smffb dla62 (.D(INT_CARRY[21]), .clk(clk), .en_d2(en_d2), .Q(CARRY[10]) ); smffa dla63 (.D(SUMMAND[42]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[42]) ); smffa dla64 (.D(SUMMAND[43]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[43]) ); smffa dla65 (.D(SUMMAND[44]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[44]) ); smfulladder dfa17 (.DATA_A (LATCHED_PP[42]), .DATA_B (LATCHED_PP[43]), .DATA_C (LATCHED_PP[44]), .SAVE (INT_SUM[32]), .CARRY (INT_CARRY[27]) ); smffa dla66 (.D(SUMMAND[45]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[45]) ); smffa dla67 (.D(SUMMAND[46]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[46]) ); smffa dla68 (.D(SUMMAND[47]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[47]) ); smfulladder dfa18 (.DATA_A (LATCHED_PP[45]), .DATA_B (LATCHED_PP[46]), .DATA_C (LATCHED_PP[47]), .SAVE (INT_SUM[33]), .CARRY (INT_CARRY[28]) ); smfulladder dfa19 (.DATA_A (INT_SUM[32]), .DATA_B (INT_SUM[33]), .DATA_C (INT_CARRY[22]), .SAVE (INT_SUM[34]), .CARRY (INT_CARRY[29]) ); assign INT_SUM[35] = INT_CARRY[23]; smfulladder dfa20 (.DATA_A (INT_SUM[34]), .DATA_B (INT_SUM[35]), .DATA_C (INT_CARRY[24]), .SAVE (INT_SUM[36]), .CARRY (INT_CARRY[30]) ); assign INT_SUM[37] = INT_CARRY[25]; smhalfadder dha9 (.DATA_A (INT_SUM[36]), .DATA_B (INT_SUM[37]), .SAVE (INT_SUM[38]), .CARRY (INT_CARRY[26]) ); smffb dla69 (.D(INT_SUM[38]), .clk(clk), .en_d2(en_d2), .Q(SUM[11]) ); smffb dla70 (.D(INT_CARRY[26]), .clk(clk), .en_d2(en_d2), .Q(CARRY[11]) ); smffa dla71 (.D(SUMMAND[48]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[48]) ); smffa dla72 (.D(SUMMAND[49]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[49]) ); smffa dla73 (.D(SUMMAND[50]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[50]) ); smfulladder dfa21 (.DATA_A (LATCHED_PP[48]), .DATA_B (LATCHED_PP[49]), .DATA_C (LATCHED_PP[50]), .SAVE (INT_SUM[39]), .CARRY (INT_CARRY[32]) ); smffa dla74 (.D(SUMMAND[51]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[51]) ); smffa dla75 (.D(SUMMAND[52]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[52]) ); smffa dla76 (.D(SUMMAND[53]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[53]) ); smfulladder dfa22 (.DATA_A (LATCHED_PP[51]), .DATA_B (LATCHED_PP[52]), .DATA_C (LATCHED_PP[53]), .SAVE (INT_SUM[40]), .CARRY (INT_CARRY[33]) ); smffa dla77 (.D(SUMMAND[54]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[54]) ); assign INT_SUM[41] = LATCHED_PP[54]; smffa dla78 (.D(SUMMAND[55]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[55]) ); assign INT_SUM[42] = LATCHED_PP[55]; smfulladder dfa23 (.DATA_A (INT_SUM[39]), .DATA_B (INT_SUM[40]), .DATA_C (INT_SUM[41]), .SAVE (INT_SUM[43]), .CARRY (INT_CARRY[34]) ); smfulladder dfa24 (.DATA_A (INT_SUM[42]), .DATA_B (INT_CARRY[27]), .DATA_C (INT_CARRY[28]), .SAVE (INT_SUM[44]), .CARRY (INT_CARRY[35]) ); smfulladder dfa25 (.DATA_A (INT_SUM[43]), .DATA_B (INT_SUM[44]), .DATA_C (INT_CARRY[29]), .SAVE (INT_SUM[45]), .CARRY (INT_CARRY[36]) ); smhalfadder dha10 (.DATA_A (INT_SUM[45]), .DATA_B (INT_CARRY[30]), .SAVE (INT_SUM[46]), .CARRY (INT_CARRY[31]) ); smffb dla79 (.D(INT_SUM[46]), .clk(clk), .en_d2(en_d2), .Q(SUM[12]) ); smffb dla80 (.D(INT_CARRY[31]), .clk(clk), .en_d2(en_d2), .Q(CARRY[12]) ); smffa dla81 (.D(SUMMAND[56]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[56]) ); smffa dla82 (.D(SUMMAND[57]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[57]) ); smffa dla83 (.D(SUMMAND[58]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[58]) ); smfulladder dfa26 (.DATA_A (LATCHED_PP[56]), .DATA_B (LATCHED_PP[57]), .DATA_C (LATCHED_PP[58]), .SAVE (INT_SUM[47]), .CARRY (INT_CARRY[38]) ); smffa dla84 (.D(SUMMAND[59]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[59]) ); smffa dla85 (.D(SUMMAND[60]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[60]) ); smffa dla86 (.D(SUMMAND[61]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[61]) ); smfulladder dfa27 (.DATA_A (LATCHED_PP[59]), .DATA_B (LATCHED_PP[60]), .DATA_C (LATCHED_PP[61]), .SAVE (INT_SUM[48]), .CARRY (INT_CARRY[39]) ); smffa dla87 (.D(SUMMAND[62]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[62]) ); assign INT_SUM[49] = LATCHED_PP[62]; smfulladder dfa28 (.DATA_A (INT_SUM[47]), .DATA_B (INT_SUM[48]), .DATA_C (INT_SUM[49]), .SAVE (INT_SUM[50]), .CARRY (INT_CARRY[40]) ); smhalfadder dha11 (.DATA_A (INT_CARRY[32]), .DATA_B (INT_CARRY[33]), .SAVE (INT_SUM[51]), .CARRY (INT_CARRY[41]) ); smfulladder dfa29 (.DATA_A (INT_SUM[50]), .DATA_B (INT_SUM[51]), .DATA_C (INT_CARRY[34]), .SAVE (INT_SUM[52]), .CARRY (INT_CARRY[42]) ); assign INT_SUM[53] = INT_CARRY[35]; smfulladder dfa30 (.DATA_A (INT_SUM[52]), .DATA_B (INT_SUM[53]), .DATA_C (INT_CARRY[36]), .SAVE (INT_SUM[54]), .CARRY (INT_CARRY[37]) ); smffb dla88 (.D(INT_SUM[54]), .clk(clk), .en_d2(en_d2), .Q(SUM[13]) ); smffb dla89 (.D(INT_CARRY[37]), .clk(clk), .en_d2(en_d2), .Q(CARRY[13]) ); smffa dla90 (.D(SUMMAND[63]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[63]) ); smffa dla91 (.D(SUMMAND[64]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[64]) ); smffa dla92 (.D(SUMMAND[65]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[65]) ); smfulladder dfa31 (.DATA_A (LATCHED_PP[63]), .DATA_B (LATCHED_PP[64]), .DATA_C (LATCHED_PP[65]), .SAVE (INT_SUM[55]), .CARRY (INT_CARRY[44]) ); smffa dla93 (.D(SUMMAND[66]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[66]) ); smffa dla94 (.D(SUMMAND[67]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[67]) ); smffa dla95 (.D(SUMMAND[68]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[68]) ); smfulladder dfa32 (.DATA_A (LATCHED_PP[66]), .DATA_B (LATCHED_PP[67]), .DATA_C (LATCHED_PP[68]), .SAVE (INT_SUM[56]), .CARRY (INT_CARRY[45]) ); smffa dla96 (.D(SUMMAND[69]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[69]) ); smffa dla97 (.D(SUMMAND[70]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[70]) ); smffa dla98 (.D(SUMMAND[71]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[71]) ); smfulladder dfa33 (.DATA_A (LATCHED_PP[69]), .DATA_B (LATCHED_PP[70]), .DATA_C (LATCHED_PP[71]), .SAVE (INT_SUM[57]), .CARRY (INT_CARRY[46]) ); smfulladder dfa34 (.DATA_A (INT_SUM[55]), .DATA_B (INT_SUM[56]), .DATA_C (INT_SUM[57]), .SAVE (INT_SUM[58]), .CARRY (INT_CARRY[47]) ); smhalfadder dha12 (.DATA_A (INT_CARRY[38]), .DATA_B (INT_CARRY[39]), .SAVE (INT_SUM[59]), .CARRY (INT_CARRY[48]) ); smfulladder dfa35 (.DATA_A (INT_SUM[58]), .DATA_B (INT_SUM[59]), .DATA_C (INT_CARRY[40]), .SAVE (INT_SUM[60]), .CARRY (INT_CARRY[49]) ); assign INT_SUM[61] = INT_CARRY[41]; smfulladder dfa36 (.DATA_A (INT_SUM[60]), .DATA_B (INT_SUM[61]), .DATA_C (INT_CARRY[42]), .SAVE (INT_SUM[62]), .CARRY (INT_CARRY[43]) ); smffb dla99 (.D(INT_SUM[62]), .clk(clk), .en_d2(en_d2), .Q(SUM[14]) ); smffb dla100 (.D(INT_CARRY[43]), .clk(clk), .en_d2(en_d2), .Q(CARRY[14]) ); smffa dla101 (.D(SUMMAND[72]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[72]) ); smffa dla102 (.D(SUMMAND[73]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[73]) ); smffa dla103 (.D(SUMMAND[74]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[74]) ); smfulladder dfa37 (.DATA_A (LATCHED_PP[72]), .DATA_B (LATCHED_PP[73]), .DATA_C (LATCHED_PP[74]), .SAVE (INT_SUM[63]), .CARRY (INT_CARRY[51]) ); smffa dla104 (.D(SUMMAND[75]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[75]) ); smffa dla105 (.D(SUMMAND[76]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[76]) ); smffa dla106 (.D(SUMMAND[77]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[77]) ); smfulladder dfa38 (.DATA_A (LATCHED_PP[75]), .DATA_B (LATCHED_PP[76]), .DATA_C (LATCHED_PP[77]), .SAVE (INT_SUM[64]), .CARRY (INT_CARRY[52]) ); smffa dla107 (.D(SUMMAND[78]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[78]) ); smffa dla108 (.D(SUMMAND[79]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[79]) ); smhalfadder dha13 (.DATA_A (LATCHED_PP[78]), .DATA_B (LATCHED_PP[79]), .SAVE (INT_SUM[65]), .CARRY (INT_CARRY[53]) ); smfulladder dfa39 (.DATA_A (INT_SUM[63]), .DATA_B (INT_SUM[64]), .DATA_C (INT_SUM[65]), .SAVE (INT_SUM[66]), .CARRY (INT_CARRY[54]) ); smfulladder dfa40 (.DATA_A (INT_CARRY[44]), .DATA_B (INT_CARRY[45]), .DATA_C (INT_CARRY[46]), .SAVE (INT_SUM[67]), .CARRY (INT_CARRY[55]) ); smfulladder dfa41 (.DATA_A (INT_SUM[66]), .DATA_B (INT_SUM[67]), .DATA_C (INT_CARRY[47]), .SAVE (INT_SUM[68]), .CARRY (INT_CARRY[56]) ); assign INT_SUM[69] = INT_CARRY[48]; smfulladder dfa42 (.DATA_A (INT_SUM[68]), .DATA_B (INT_SUM[69]), .DATA_C (INT_CARRY[49]), .SAVE (INT_SUM[70]), .CARRY (INT_CARRY[50]) ); smffb dla109 (.D(INT_SUM[70]), .clk(clk), .en_d2(en_d2), .Q(SUM[15]) ); smffb dla110 (.D(INT_CARRY[50]), .clk(clk), .en_d2(en_d2), .Q(CARRY[15]) ); smffa dla111 (.D(SUMMAND[80]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[80]) ); smffa dla112 (.D(SUMMAND[81]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[81]) ); smffa dla113 (.D(SUMMAND[82]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[82]) ); smfulladder dfa43 (.DATA_A (LATCHED_PP[80]), .DATA_B (LATCHED_PP[81]), .DATA_C (LATCHED_PP[82]), .SAVE (INT_SUM[71]), .CARRY (INT_CARRY[58]) ); smffa dla114 (.D(SUMMAND[83]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[83]) ); smffa dla115 (.D(SUMMAND[84]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[84]) ); smffa dla116 (.D(SUMMAND[85]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[85]) ); smfulladder dfa44 (.DATA_A (LATCHED_PP[83]), .DATA_B (LATCHED_PP[84]), .DATA_C (LATCHED_PP[85]), .SAVE (INT_SUM[72]), .CARRY (INT_CARRY[59]) ); smffa dla117 (.D(SUMMAND[86]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[86]) ); smffa dla118 (.D(SUMMAND[87]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[87]) ); smffa dla119 (.D(SUMMAND[88]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[88]) ); smfulladder dfa45 (.DATA_A (LATCHED_PP[86]), .DATA_B (LATCHED_PP[87]), .DATA_C (LATCHED_PP[88]), .SAVE (INT_SUM[73]), .CARRY (INT_CARRY[60]) ); smffa dla120 (.D(SUMMAND[89]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[89]) ); assign INT_SUM[74] = LATCHED_PP[89]; smfulladder dfa46 (.DATA_A (INT_SUM[71]), .DATA_B (INT_SUM[72]), .DATA_C (INT_SUM[73]), .SAVE (INT_SUM[75]), .CARRY (INT_CARRY[61]) ); smfulladder dfa47 (.DATA_A (INT_SUM[74]), .DATA_B (INT_CARRY[51]), .DATA_C (INT_CARRY[52]), .SAVE (INT_SUM[76]), .CARRY (INT_CARRY[62]) ); assign INT_SUM[77] = INT_CARRY[53]; smfulladder dfa48 (.DATA_A (INT_SUM[75]), .DATA_B (INT_SUM[76]), .DATA_C (INT_SUM[77]), .SAVE (INT_SUM[78]), .CARRY (INT_CARRY[63]) ); smhalfadder dha14 (.DATA_A (INT_CARRY[54]), .DATA_B (INT_CARRY[55]), .SAVE (INT_SUM[79]), .CARRY (INT_CARRY[64]) ); smfulladder dfa49 (.DATA_A (INT_SUM[78]), .DATA_B (INT_SUM[79]), .DATA_C (INT_CARRY[56]), .SAVE (INT_SUM[80]), .CARRY (INT_CARRY[57]) ); smffb dla121 (.D(INT_SUM[80]), .clk(clk), .en_d2(en_d2), .Q(SUM[16]) ); smffb dla122 (.D(INT_CARRY[57]), .clk(clk), .en_d2(en_d2), .Q(CARRY[16]) ); smffa dla123 (.D(SUMMAND[90]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[90]) ); smffa dla124 (.D(SUMMAND[91]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[91]) ); smffa dla125 (.D(SUMMAND[92]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[92]) ); smfulladder dfa50 (.DATA_A (LATCHED_PP[90]), .DATA_B (LATCHED_PP[91]), .DATA_C (LATCHED_PP[92]), .SAVE (INT_SUM[81]), .CARRY (INT_CARRY[66]) ); smffa dla126 (.D(SUMMAND[93]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[93]) ); smffa dla127 (.D(SUMMAND[94]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[94]) ); smffa dla128 (.D(SUMMAND[95]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[95]) ); smfulladder dfa51 (.DATA_A (LATCHED_PP[93]), .DATA_B (LATCHED_PP[94]), .DATA_C (LATCHED_PP[95]), .SAVE (INT_SUM[82]), .CARRY (INT_CARRY[67]) ); smffa dla129 (.D(SUMMAND[96]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[96]) ); smffa dla130 (.D(SUMMAND[97]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[97]) ); smffa dla131 (.D(SUMMAND[98]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[98]) ); smfulladder dfa52 (.DATA_A (LATCHED_PP[96]), .DATA_B (LATCHED_PP[97]), .DATA_C (LATCHED_PP[98]), .SAVE (INT_SUM[83]), .CARRY (INT_CARRY[68]) ); smfulladder dfa53 (.DATA_A (INT_SUM[81]), .DATA_B (INT_SUM[82]), .DATA_C (INT_SUM[83]), .SAVE (INT_SUM[84]), .CARRY (INT_CARRY[69]) ); smfulladder dfa54 (.DATA_A (INT_CARRY[58]), .DATA_B (INT_CARRY[59]), .DATA_C (INT_CARRY[60]), .SAVE (INT_SUM[85]), .CARRY (INT_CARRY[70]) ); smfulladder dfa55 (.DATA_A (INT_SUM[84]), .DATA_B (INT_SUM[85]), .DATA_C (INT_CARRY[61]), .SAVE (INT_SUM[86]), .CARRY (INT_CARRY[71]) ); assign INT_SUM[87] = INT_CARRY[62]; smfulladder dfa56 (.DATA_A (INT_SUM[86]), .DATA_B (INT_SUM[87]), .DATA_C (INT_CARRY[63]), .SAVE (INT_SUM[88]), .CARRY (INT_CARRY[72]) ); assign INT_SUM[89] = INT_CARRY[64]; smhalfadder dha15 (.DATA_A (INT_SUM[88]), .DATA_B (INT_SUM[89]), .SAVE (INT_SUM[90]), .CARRY (INT_CARRY[65]) ); smffb dla132 (.D(INT_SUM[90]), .clk(clk), .en_d2(en_d2), .Q(SUM[17]) ); smffb dla133 (.D(INT_CARRY[65]), .clk(clk), .en_d2(en_d2), .Q(CARRY[17]) ); smffa dla134 (.D(SUMMAND[99]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[99]) ); smffa dla135 (.D(SUMMAND[100]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[100]) ); smffa dla136 (.D(SUMMAND[101]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[101]) ); smfulladder dfa57 (.DATA_A (LATCHED_PP[99]), .DATA_B (LATCHED_PP[100]), .DATA_C (LATCHED_PP[101]), .SAVE (INT_SUM[91]), .CARRY (INT_CARRY[74]) ); smffa dla137 (.D(SUMMAND[102]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[102]) ); smffa dla138 (.D(SUMMAND[103]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[103]) ); smffa dla139 (.D(SUMMAND[104]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[104]) ); smfulladder dfa58 (.DATA_A (LATCHED_PP[102]), .DATA_B (LATCHED_PP[103]), .DATA_C (LATCHED_PP[104]), .SAVE (INT_SUM[92]), .CARRY (INT_CARRY[75]) ); smffa dla140 (.D(SUMMAND[105]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[105]) ); smffa dla141 (.D(SUMMAND[106]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[106]) ); smffa dla142 (.D(SUMMAND[107]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[107]) ); smfulladder dfa59 (.DATA_A (LATCHED_PP[105]), .DATA_B (LATCHED_PP[106]), .DATA_C (LATCHED_PP[107]), .SAVE (INT_SUM[93]), .CARRY (INT_CARRY[76]) ); smffa dla143 (.D(SUMMAND[108]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[108]) ); assign INT_SUM[94] = LATCHED_PP[108]; smffa dla144 (.D(SUMMAND[109]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[109]) ); assign INT_SUM[95] = LATCHED_PP[109]; smfulladder dfa60 (.DATA_A (INT_SUM[91]), .DATA_B (INT_SUM[92]), .DATA_C (INT_SUM[93]), .SAVE (INT_SUM[96]), .CARRY (INT_CARRY[77]) ); smfulladder dfa61 (.DATA_A (INT_SUM[94]), .DATA_B (INT_SUM[95]), .DATA_C (INT_CARRY[66]), .SAVE (INT_SUM[97]), .CARRY (INT_CARRY[78]) ); assign INT_SUM[98] = INT_CARRY[67]; assign INT_SUM[99] = INT_CARRY[68]; smfulladder dfa62 (.DATA_A (INT_SUM[96]), .DATA_B (INT_SUM[97]), .DATA_C (INT_SUM[98]), .SAVE (INT_SUM[100]), .CARRY (INT_CARRY[79]) ); smfulladder dfa63 (.DATA_A (INT_SUM[99]), .DATA_B (INT_CARRY[69]), .DATA_C (INT_CARRY[70]), .SAVE (INT_SUM[101]), .CARRY (INT_CARRY[80]) ); smfulladder dfa64 (.DATA_A (INT_SUM[100]), .DATA_B (INT_SUM[101]), .DATA_C (INT_CARRY[71]), .SAVE (INT_SUM[102]), .CARRY (INT_CARRY[81]) ); smhalfadder dha16 (.DATA_A (INT_SUM[102]), .DATA_B (INT_CARRY[72]), .SAVE (INT_SUM[103]), .CARRY (INT_CARRY[73]) ); smffb dla145 (.D(INT_SUM[103]), .clk(clk), .en_d2(en_d2), .Q(SUM[18]) ); smffb dla146 (.D(INT_CARRY[73]), .clk(clk), .en_d2(en_d2), .Q(CARRY[18]) ); smffa dla147 (.D(SUMMAND[110]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[110]) ); smffa dla148 (.D(SUMMAND[111]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[111]) ); smffa dla149 (.D(SUMMAND[112]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[112]) ); smfulladder dfa65 (.DATA_A (LATCHED_PP[110]), .DATA_B (LATCHED_PP[111]), .DATA_C (LATCHED_PP[112]), .SAVE (INT_SUM[104]), .CARRY (INT_CARRY[83]) ); smffa dla150 (.D(SUMMAND[113]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[113]) ); smffa dla151 (.D(SUMMAND[114]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[114]) ); smffa dla152 (.D(SUMMAND[115]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[115]) ); smfulladder dfa66 (.DATA_A (LATCHED_PP[113]), .DATA_B (LATCHED_PP[114]), .DATA_C (LATCHED_PP[115]), .SAVE (INT_SUM[105]), .CARRY (INT_CARRY[84]) ); smffa dla153 (.D(SUMMAND[116]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[116]) ); smffa dla154 (.D(SUMMAND[117]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[117]) ); smffa dla155 (.D(SUMMAND[118]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[118]) ); smfulladder dfa67 (.DATA_A (LATCHED_PP[116]), .DATA_B (LATCHED_PP[117]), .DATA_C (LATCHED_PP[118]), .SAVE (INT_SUM[106]), .CARRY (INT_CARRY[85]) ); smffa dla156 (.D(SUMMAND[119]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[119]) ); assign INT_SUM[107] = LATCHED_PP[119]; smfulladder dfa68 (.DATA_A (INT_SUM[104]), .DATA_B (INT_SUM[105]), .DATA_C (INT_SUM[106]), .SAVE (INT_SUM[108]), .CARRY (INT_CARRY[86]) ); smfulladder dfa69 (.DATA_A (INT_SUM[107]), .DATA_B (INT_CARRY[74]), .DATA_C (INT_CARRY[75]), .SAVE (INT_SUM[109]), .CARRY (INT_CARRY[87]) ); assign INT_SUM[110] = INT_CARRY[76]; smfulladder dfa70 (.DATA_A (INT_SUM[108]), .DATA_B (INT_SUM[109]), .DATA_C (INT_SUM[110]), .SAVE (INT_SUM[111]), .CARRY (INT_CARRY[88]) ); smhalfadder dha17 (.DATA_A (INT_CARRY[77]), .DATA_B (INT_CARRY[78]), .SAVE (INT_SUM[112]), .CARRY (INT_CARRY[89]) ); smfulladder dfa71 (.DATA_A (INT_SUM[111]), .DATA_B (INT_SUM[112]), .DATA_C (INT_CARRY[79]), .SAVE (INT_SUM[113]), .CARRY (INT_CARRY[90]) ); assign INT_SUM[114] = INT_CARRY[80]; smfulladder dfa72 (.DATA_A (INT_SUM[113]), .DATA_B (INT_SUM[114]), .DATA_C (INT_CARRY[81]), .SAVE (INT_SUM[115]), .CARRY (INT_CARRY[82]) ); smffb dla157 (.D(INT_SUM[115]), .clk(clk), .en_d2(en_d2), .Q(SUM[19]) ); smffb dla158 (.D(INT_CARRY[82]), .clk(clk), .en_d2(en_d2), .Q(CARRY[19]) ); smffa dla159 (.D(SUMMAND[120]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[120]) ); smffa dla160 (.D(SUMMAND[121]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[121]) ); smffa dla161 (.D(SUMMAND[122]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[122]) ); smfulladder dfa73 (.DATA_A (LATCHED_PP[120]), .DATA_B (LATCHED_PP[121]), .DATA_C (LATCHED_PP[122]), .SAVE (INT_SUM[116]), .CARRY (INT_CARRY[92]) ); smffa dla162 (.D(SUMMAND[123]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[123]) ); smffa dla163 (.D(SUMMAND[124]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[124]) ); smffa dla164 (.D(SUMMAND[125]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[125]) ); smfulladder dfa74 (.DATA_A (LATCHED_PP[123]), .DATA_B (LATCHED_PP[124]), .DATA_C (LATCHED_PP[125]), .SAVE (INT_SUM[117]), .CARRY (INT_CARRY[93]) ); smffa dla165 (.D(SUMMAND[126]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[126]) ); smffa dla166 (.D(SUMMAND[127]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[127]) ); smffa dla167 (.D(SUMMAND[128]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[128]) ); smfulladder dfa75 (.DATA_A (LATCHED_PP[126]), .DATA_B (LATCHED_PP[127]), .DATA_C (LATCHED_PP[128]), .SAVE (INT_SUM[118]), .CARRY (INT_CARRY[94]) ); smffa dla168 (.D(SUMMAND[129]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[129]) ); smffa dla169 (.D(SUMMAND[130]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[130]) ); smffa dla170 (.D(SUMMAND[131]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[131]) ); smfulladder dfa76 (.DATA_A (LATCHED_PP[129]), .DATA_B (LATCHED_PP[130]), .DATA_C (LATCHED_PP[131]), .SAVE (INT_SUM[119]), .CARRY (INT_CARRY[95]) ); smfulladder dfa77 (.DATA_A (INT_SUM[116]), .DATA_B (INT_SUM[117]), .DATA_C (INT_SUM[118]), .SAVE (INT_SUM[120]), .CARRY (INT_CARRY[96]) ); smfulladder dfa78 (.DATA_A (INT_SUM[119]), .DATA_B (INT_CARRY[83]), .DATA_C (INT_CARRY[84]), .SAVE (INT_SUM[121]), .CARRY (INT_CARRY[97]) ); assign INT_SUM[122] = INT_CARRY[85]; smfulladder dfa79 (.DATA_A (INT_SUM[120]), .DATA_B (INT_SUM[121]), .DATA_C (INT_SUM[122]), .SAVE (INT_SUM[123]), .CARRY (INT_CARRY[98]) ); smhalfadder dha18 (.DATA_A (INT_CARRY[86]), .DATA_B (INT_CARRY[87]), .SAVE (INT_SUM[124]), .CARRY (INT_CARRY[99]) ); smfulladder dfa80 (.DATA_A (INT_SUM[123]), .DATA_B (INT_SUM[124]), .DATA_C (INT_CARRY[88]), .SAVE (INT_SUM[125]), .CARRY (INT_CARRY[100]) ); assign INT_SUM[126] = INT_CARRY[89]; smfulladder dfa81 (.DATA_A (INT_SUM[125]), .DATA_B (INT_SUM[126]), .DATA_C (INT_CARRY[90]), .SAVE (INT_SUM[127]), .CARRY (INT_CARRY[91]) ); smffb dla171 (.D(INT_SUM[127]), .clk(clk), .en_d2(en_d2), .Q(SUM[20]) ); smffb dla172 (.D(INT_CARRY[91]), .clk(clk), .en_d2(en_d2), .Q(CARRY[20]) ); smffa dla173 (.D(SUMMAND[132]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[132]) ); smffa dla174 (.D(SUMMAND[133]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[133]) ); smffa dla175 (.D(SUMMAND[134]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[134]) ); smfulladder dfa82 (.DATA_A (LATCHED_PP[132]), .DATA_B (LATCHED_PP[133]), .DATA_C (LATCHED_PP[134]), .SAVE (INT_SUM[128]), .CARRY (INT_CARRY[102]) ); smffa dla176 (.D(SUMMAND[135]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[135]) ); smffa dla177 (.D(SUMMAND[136]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[136]) ); smffa dla178 (.D(SUMMAND[137]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[137]) ); smfulladder dfa83 (.DATA_A (LATCHED_PP[135]), .DATA_B (LATCHED_PP[136]), .DATA_C (LATCHED_PP[137]), .SAVE (INT_SUM[129]), .CARRY (INT_CARRY[103]) ); smffa dla179 (.D(SUMMAND[138]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[138]) ); smffa dla180 (.D(SUMMAND[139]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[139]) ); smffa dla181 (.D(SUMMAND[140]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[140]) ); smfulladder dfa84 (.DATA_A (LATCHED_PP[138]), .DATA_B (LATCHED_PP[139]), .DATA_C (LATCHED_PP[140]), .SAVE (INT_SUM[130]), .CARRY (INT_CARRY[104]) ); smffa dla182 (.D(SUMMAND[141]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[141]) ); assign INT_SUM[131] = LATCHED_PP[141]; smffa dla183 (.D(SUMMAND[142]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[142]) ); assign INT_SUM[132] = LATCHED_PP[142]; smfulladder dfa85 (.DATA_A (INT_SUM[128]), .DATA_B (INT_SUM[129]), .DATA_C (INT_SUM[130]), .SAVE (INT_SUM[133]), .CARRY (INT_CARRY[105]) ); smfulladder dfa86 (.DATA_A (INT_SUM[131]), .DATA_B (INT_SUM[132]), .DATA_C (INT_CARRY[92]), .SAVE (INT_SUM[134]), .CARRY (INT_CARRY[106]) ); smfulladder dfa87 (.DATA_A (INT_CARRY[93]), .DATA_B (INT_CARRY[94]), .DATA_C (INT_CARRY[95]), .SAVE (INT_SUM[135]), .CARRY (INT_CARRY[107]) ); smfulladder dfa88 (.DATA_A (INT_SUM[133]), .DATA_B (INT_SUM[134]), .DATA_C (INT_SUM[135]), .SAVE (INT_SUM[136]), .CARRY (INT_CARRY[108]) ); smhalfadder dha19 (.DATA_A (INT_CARRY[96]), .DATA_B (INT_CARRY[97]), .SAVE (INT_SUM[137]), .CARRY (INT_CARRY[109]) ); smfulladder dfa89 (.DATA_A (INT_SUM[136]), .DATA_B (INT_SUM[137]), .DATA_C (INT_CARRY[98]), .SAVE (INT_SUM[138]), .CARRY (INT_CARRY[110]) ); assign INT_SUM[139] = INT_CARRY[99]; smfulladder dfa90 (.DATA_A (INT_SUM[138]), .DATA_B (INT_SUM[139]), .DATA_C (INT_CARRY[100]), .SAVE (INT_SUM[140]), .CARRY (INT_CARRY[101]) ); smffb dla184 (.D(INT_SUM[140]), .clk(clk), .en_d2(en_d2), .Q(SUM[21]) ); smffb dla185 (.D(INT_CARRY[101]), .clk(clk), .en_d2(en_d2), .Q(CARRY[21]) ); smffa dla186 (.D(SUMMAND[143]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[143]) ); smffa dla187 (.D(SUMMAND[144]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[144]) ); smffa dla188 (.D(SUMMAND[145]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[145]) ); smfulladder dfa91 (.DATA_A (LATCHED_PP[143]), .DATA_B (LATCHED_PP[144]), .DATA_C (LATCHED_PP[145]), .SAVE (INT_SUM[141]), .CARRY (INT_CARRY[112]) ); smffa dla189 (.D(SUMMAND[146]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[146]) ); smffa dla190 (.D(SUMMAND[147]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[147]) ); smffa dla191 (.D(SUMMAND[148]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[148]) ); smfulladder dfa92 (.DATA_A (LATCHED_PP[146]), .DATA_B (LATCHED_PP[147]), .DATA_C (LATCHED_PP[148]), .SAVE (INT_SUM[142]), .CARRY (INT_CARRY[113]) ); smffa dla192 (.D(SUMMAND[149]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[149]) ); smffa dla193 (.D(SUMMAND[150]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[150]) ); smffa dla194 (.D(SUMMAND[151]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[151]) ); smfulladder dfa93 (.DATA_A (LATCHED_PP[149]), .DATA_B (LATCHED_PP[150]), .DATA_C (LATCHED_PP[151]), .SAVE (INT_SUM[143]), .CARRY (INT_CARRY[114]) ); smffa dla195 (.D(SUMMAND[152]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[152]) ); smffa dla196 (.D(SUMMAND[153]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[153]) ); smffa dla197 (.D(SUMMAND[154]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[154]) ); smfulladder dfa94 (.DATA_A (LATCHED_PP[152]), .DATA_B (LATCHED_PP[153]), .DATA_C (LATCHED_PP[154]), .SAVE (INT_SUM[144]), .CARRY (INT_CARRY[115]) ); smffa dla198 (.D(SUMMAND[155]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[155]) ); assign INT_SUM[145] = LATCHED_PP[155]; smfulladder dfa95 (.DATA_A (INT_SUM[141]), .DATA_B (INT_SUM[142]), .DATA_C (INT_SUM[143]), .SAVE (INT_SUM[146]), .CARRY (INT_CARRY[116]) ); smfulladder dfa96 (.DATA_A (INT_SUM[144]), .DATA_B (INT_SUM[145]), .DATA_C (INT_CARRY[102]), .SAVE (INT_SUM[147]), .CARRY (INT_CARRY[117]) ); smhalfadder dha20 (.DATA_A (INT_CARRY[103]), .DATA_B (INT_CARRY[104]), .SAVE (INT_SUM[148]), .CARRY (INT_CARRY[118]) ); smfulladder dfa97 (.DATA_A (INT_SUM[146]), .DATA_B (INT_SUM[147]), .DATA_C (INT_SUM[148]), .SAVE (INT_SUM[149]), .CARRY (INT_CARRY[119]) ); smfulladder dfa98 (.DATA_A (INT_CARRY[105]), .DATA_B (INT_CARRY[106]), .DATA_C (INT_CARRY[107]), .SAVE (INT_SUM[150]), .CARRY (INT_CARRY[120]) ); smfulladder dfa99 (.DATA_A (INT_SUM[149]), .DATA_B (INT_SUM[150]), .DATA_C (INT_CARRY[108]), .SAVE (INT_SUM[151]), .CARRY (INT_CARRY[121]) ); assign INT_SUM[152] = INT_CARRY[109]; smfulladder dfa100 (.DATA_A (INT_SUM[151]), .DATA_B (INT_SUM[152]), .DATA_C (INT_CARRY[110]), .SAVE (INT_SUM[153]), .CARRY (INT_CARRY[111]) ); smffb dla199 (.D(INT_SUM[153]), .clk(clk), .en_d2(en_d2), .Q(SUM[22]) ); smffb dla200 (.D(INT_CARRY[111]), .clk(clk), .en_d2(en_d2), .Q(CARRY[22]) ); smffa dla201 (.D(SUMMAND[156]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[156]) ); smffa dla202 (.D(SUMMAND[157]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[157]) ); smffa dla203 (.D(SUMMAND[158]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[158]) ); smfulladder dfa101 (.DATA_A (LATCHED_PP[156]), .DATA_B (LATCHED_PP[157]), .DATA_C (LATCHED_PP[158]), .SAVE (INT_SUM[154]), .CARRY (INT_CARRY[123]) ); smffa dla204 (.D(SUMMAND[159]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[159]) ); smffa dla205 (.D(SUMMAND[160]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[160]) ); smffa dla206 (.D(SUMMAND[161]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[161]) ); smfulladder dfa102 (.DATA_A (LATCHED_PP[159]), .DATA_B (LATCHED_PP[160]), .DATA_C (LATCHED_PP[161]), .SAVE (INT_SUM[155]), .CARRY (INT_CARRY[124]) ); smffa dla207 (.D(SUMMAND[162]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[162]) ); smffa dla208 (.D(SUMMAND[163]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[163]) ); smffa dla209 (.D(SUMMAND[164]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[164]) ); smfulladder dfa103 (.DATA_A (LATCHED_PP[162]), .DATA_B (LATCHED_PP[163]), .DATA_C (LATCHED_PP[164]), .SAVE (INT_SUM[156]), .CARRY (INT_CARRY[125]) ); smffa dla210 (.D(SUMMAND[165]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[165]) ); smffa dla211 (.D(SUMMAND[166]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[166]) ); smffa dla212 (.D(SUMMAND[167]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[167]) ); smfulladder dfa104 (.DATA_A (LATCHED_PP[165]), .DATA_B (LATCHED_PP[166]), .DATA_C (LATCHED_PP[167]), .SAVE (INT_SUM[157]), .CARRY (INT_CARRY[126]) ); smfulladder dfa105 (.DATA_A (INT_SUM[154]), .DATA_B (INT_SUM[155]), .DATA_C (INT_SUM[156]), .SAVE (INT_SUM[158]), .CARRY (INT_CARRY[127]) ); smfulladder dfa106 (.DATA_A (INT_SUM[157]), .DATA_B (INT_CARRY[112]), .DATA_C (INT_CARRY[113]), .SAVE (INT_SUM[159]), .CARRY (INT_CARRY[128]) ); smhalfadder dha21 (.DATA_A (INT_CARRY[114]), .DATA_B (INT_CARRY[115]), .SAVE (INT_SUM[160]), .CARRY (INT_CARRY[129]) ); smfulladder dfa107 (.DATA_A (INT_SUM[158]), .DATA_B (INT_SUM[159]), .DATA_C (INT_SUM[160]), .SAVE (INT_SUM[161]), .CARRY (INT_CARRY[130]) ); smfulladder dfa108 (.DATA_A (INT_CARRY[116]), .DATA_B (INT_CARRY[117]), .DATA_C (INT_CARRY[118]), .SAVE (INT_SUM[162]), .CARRY (INT_CARRY[131]) ); smfulladder dfa109 (.DATA_A (INT_SUM[161]), .DATA_B (INT_SUM[162]), .DATA_C (INT_CARRY[119]), .SAVE (INT_SUM[163]), .CARRY (INT_CARRY[132]) ); assign INT_SUM[164] = INT_CARRY[120]; smfulladder dfa110 (.DATA_A (INT_SUM[163]), .DATA_B (INT_SUM[164]), .DATA_C (INT_CARRY[121]), .SAVE (INT_SUM[165]), .CARRY (INT_CARRY[122]) ); smffb dla213 (.D(INT_SUM[165]), .clk(clk), .en_d2(en_d2), .Q(SUM[23]) ); smffb dla214 (.D(INT_CARRY[122]), .clk(clk), .en_d2(en_d2), .Q(CARRY[23]) ); smffa dla215 (.D(SUMMAND[168]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[168]) ); smffa dla216 (.D(SUMMAND[169]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[169]) ); smffa dla217 (.D(SUMMAND[170]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[170]) ); smfulladder dfa111 (.DATA_A (LATCHED_PP[168]), .DATA_B (LATCHED_PP[169]), .DATA_C (LATCHED_PP[170]), .SAVE (INT_SUM[166]), .CARRY (INT_CARRY[134]) ); smffa dla218 (.D(SUMMAND[171]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[171]) ); smffa dla219 (.D(SUMMAND[172]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[172]) ); smffa dla220 (.D(SUMMAND[173]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[173]) ); smfulladder dfa112 (.DATA_A (LATCHED_PP[171]), .DATA_B (LATCHED_PP[172]), .DATA_C (LATCHED_PP[173]), .SAVE (INT_SUM[167]), .CARRY (INT_CARRY[135]) ); smffa dla221 (.D(SUMMAND[174]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[174]) ); smffa dla222 (.D(SUMMAND[175]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[175]) ); smffa dla223 (.D(SUMMAND[176]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[176]) ); smfulladder dfa113 (.DATA_A (LATCHED_PP[174]), .DATA_B (LATCHED_PP[175]), .DATA_C (LATCHED_PP[176]), .SAVE (INT_SUM[168]), .CARRY (INT_CARRY[136]) ); smffa dla224 (.D(SUMMAND[177]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[177]) ); smffa dla225 (.D(SUMMAND[178]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[178]) ); smffa dla226 (.D(SUMMAND[179]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[179]) ); smfulladder dfa114 (.DATA_A (LATCHED_PP[177]), .DATA_B (LATCHED_PP[178]), .DATA_C (LATCHED_PP[179]), .SAVE (INT_SUM[169]), .CARRY (INT_CARRY[137]) ); smffa dla227 (.D(SUMMAND[180]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[180]) ); smffa dla228 (.D(SUMMAND[181]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[181]) ); smhalfadder dha22 (.DATA_A (LATCHED_PP[180]), .DATA_B (LATCHED_PP[181]), .SAVE (INT_SUM[170]), .CARRY (INT_CARRY[138]) ); smfulladder dfa115 (.DATA_A (INT_SUM[166]), .DATA_B (INT_SUM[167]), .DATA_C (INT_SUM[168]), .SAVE (INT_SUM[171]), .CARRY (INT_CARRY[139]) ); smfulladder dfa116 (.DATA_A (INT_SUM[169]), .DATA_B (INT_SUM[170]), .DATA_C (INT_CARRY[123]), .SAVE (INT_SUM[172]), .CARRY (INT_CARRY[140]) ); smfulladder dfa117 (.DATA_A (INT_CARRY[124]), .DATA_B (INT_CARRY[125]), .DATA_C (INT_CARRY[126]), .SAVE (INT_SUM[173]), .CARRY (INT_CARRY[141]) ); smfulladder dfa118 (.DATA_A (INT_SUM[171]), .DATA_B (INT_SUM[172]), .DATA_C (INT_SUM[173]), .SAVE (INT_SUM[174]), .CARRY (INT_CARRY[142]) ); smfulladder dfa119 (.DATA_A (INT_CARRY[127]), .DATA_B (INT_CARRY[128]), .DATA_C (INT_CARRY[129]), .SAVE (INT_SUM[175]), .CARRY (INT_CARRY[143]) ); smfulladder dfa120 (.DATA_A (INT_SUM[174]), .DATA_B (INT_SUM[175]), .DATA_C (INT_CARRY[130]), .SAVE (INT_SUM[176]), .CARRY (INT_CARRY[144]) ); assign INT_SUM[177] = INT_CARRY[131]; smfulladder dfa121 (.DATA_A (INT_SUM[176]), .DATA_B (INT_SUM[177]), .DATA_C (INT_CARRY[132]), .SAVE (INT_SUM[178]), .CARRY (INT_CARRY[133]) ); smffb dla229 (.D(INT_SUM[178]), .clk(clk), .en_d2(en_d2), .Q(SUM[24]) ); smffb dla230 (.D(INT_CARRY[133]), .clk(clk), .en_d2(en_d2), .Q(CARRY[24]) ); smffa dla231 (.D(SUMMAND[182]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[182]) ); smffa dla232 (.D(SUMMAND[183]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[183]) ); smffa dla233 (.D(SUMMAND[184]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[184]) ); smfulladder dfa122 (.DATA_A (LATCHED_PP[182]), .DATA_B (LATCHED_PP[183]), .DATA_C (LATCHED_PP[184]), .SAVE (INT_SUM[179]), .CARRY (INT_CARRY[146]) ); smffa dla234 (.D(SUMMAND[185]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[185]) ); smffa dla235 (.D(SUMMAND[186]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[186]) ); smffa dla236 (.D(SUMMAND[187]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[187]) ); smfulladder dfa123 (.DATA_A (LATCHED_PP[185]), .DATA_B (LATCHED_PP[186]), .DATA_C (LATCHED_PP[187]), .SAVE (INT_SUM[180]), .CARRY (INT_CARRY[147]) ); smffa dla237 (.D(SUMMAND[188]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[188]) ); smffa dla238 (.D(SUMMAND[189]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[189]) ); smffa dla239 (.D(SUMMAND[190]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[190]) ); smfulladder dfa124 (.DATA_A (LATCHED_PP[188]), .DATA_B (LATCHED_PP[189]), .DATA_C (LATCHED_PP[190]), .SAVE (INT_SUM[181]), .CARRY (INT_CARRY[148]) ); smffa dla240 (.D(SUMMAND[191]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[191]) ); smffa dla241 (.D(SUMMAND[192]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[192]) ); smffa dla242 (.D(SUMMAND[193]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[193]) ); smfulladder dfa125 (.DATA_A (LATCHED_PP[191]), .DATA_B (LATCHED_PP[192]), .DATA_C (LATCHED_PP[193]), .SAVE (INT_SUM[182]), .CARRY (INT_CARRY[149]) ); smffa dla243 (.D(SUMMAND[194]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[194]) ); assign INT_SUM[183] = LATCHED_PP[194]; smfulladder dfa126 (.DATA_A (INT_SUM[179]), .DATA_B (INT_SUM[180]), .DATA_C (INT_SUM[181]), .SAVE (INT_SUM[184]), .CARRY (INT_CARRY[150]) ); smfulladder dfa127 (.DATA_A (INT_SUM[182]), .DATA_B (INT_SUM[183]), .DATA_C (INT_CARRY[134]), .SAVE (INT_SUM[185]), .CARRY (INT_CARRY[151]) ); smfulladder dfa128 (.DATA_A (INT_CARRY[135]), .DATA_B (INT_CARRY[136]), .DATA_C (INT_CARRY[137]), .SAVE (INT_SUM[186]), .CARRY (INT_CARRY[152]) ); assign INT_SUM[187] = INT_CARRY[138]; smfulladder dfa129 (.DATA_A (INT_SUM[184]), .DATA_B (INT_SUM[185]), .DATA_C (INT_SUM[186]), .SAVE (INT_SUM[188]), .CARRY (INT_CARRY[153]) ); smfulladder dfa130 (.DATA_A (INT_SUM[187]), .DATA_B (INT_CARRY[139]), .DATA_C (INT_CARRY[140]), .SAVE (INT_SUM[189]), .CARRY (INT_CARRY[154]) ); assign INT_SUM[190] = INT_CARRY[141]; smfulladder dfa131 (.DATA_A (INT_SUM[188]), .DATA_B (INT_SUM[189]), .DATA_C (INT_SUM[190]), .SAVE (INT_SUM[191]), .CARRY (INT_CARRY[155]) ); smhalfadder dha23 (.DATA_A (INT_CARRY[142]), .DATA_B (INT_CARRY[143]), .SAVE (INT_SUM[192]), .CARRY (INT_CARRY[156]) ); smfulladder dfa132 (.DATA_A (INT_SUM[191]), .DATA_B (INT_SUM[192]), .DATA_C (INT_CARRY[144]), .SAVE (INT_SUM[193]), .CARRY (INT_CARRY[145]) ); smffb dla244 (.D(INT_SUM[193]), .clk(clk), .en_d2(en_d2), .Q(SUM[25]) ); smffb dla245 (.D(INT_CARRY[145]), .clk(clk), .en_d2(en_d2), .Q(CARRY[25]) ); smffa dla246 (.D(SUMMAND[195]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[195]) ); smffa dla247 (.D(SUMMAND[196]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[196]) ); smffa dla248 (.D(SUMMAND[197]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[197]) ); smfulladder dfa133 (.DATA_A (LATCHED_PP[195]), .DATA_B (LATCHED_PP[196]), .DATA_C (LATCHED_PP[197]), .SAVE (INT_SUM[194]), .CARRY (INT_CARRY[158]) ); smffa dla249 (.D(SUMMAND[198]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[198]) ); smffa dla250 (.D(SUMMAND[199]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[199]) ); smffa dla251 (.D(SUMMAND[200]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[200]) ); smfulladder dfa134 (.DATA_A (LATCHED_PP[198]), .DATA_B (LATCHED_PP[199]), .DATA_C (LATCHED_PP[200]), .SAVE (INT_SUM[195]), .CARRY (INT_CARRY[159]) ); smffa dla252 (.D(SUMMAND[201]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[201]) ); smffa dla253 (.D(SUMMAND[202]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[202]) ); smffa dla254 (.D(SUMMAND[203]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[203]) ); smfulladder dfa135 (.DATA_A (LATCHED_PP[201]), .DATA_B (LATCHED_PP[202]), .DATA_C (LATCHED_PP[203]), .SAVE (INT_SUM[196]), .CARRY (INT_CARRY[160]) ); smffa dla255 (.D(SUMMAND[204]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[204]) ); smffa dla256 (.D(SUMMAND[205]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[205]) ); smffa dla257 (.D(SUMMAND[206]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[206]) ); smfulladder dfa136 (.DATA_A (LATCHED_PP[204]), .DATA_B (LATCHED_PP[205]), .DATA_C (LATCHED_PP[206]), .SAVE (INT_SUM[197]), .CARRY (INT_CARRY[161]) ); smffa dla258 (.D(SUMMAND[207]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[207]) ); smffa dla259 (.D(SUMMAND[208]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[208]) ); smffa dla260 (.D(SUMMAND[209]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[209]) ); smfulladder dfa137 (.DATA_A (LATCHED_PP[207]), .DATA_B (LATCHED_PP[208]), .DATA_C (LATCHED_PP[209]), .SAVE (INT_SUM[198]), .CARRY (INT_CARRY[162]) ); smfulladder dfa138 (.DATA_A (INT_SUM[194]), .DATA_B (INT_SUM[195]), .DATA_C (INT_SUM[196]), .SAVE (INT_SUM[199]), .CARRY (INT_CARRY[163]) ); smfulladder dfa139 (.DATA_A (INT_SUM[197]), .DATA_B (INT_SUM[198]), .DATA_C (INT_CARRY[146]), .SAVE (INT_SUM[200]), .CARRY (INT_CARRY[164]) ); smfulladder dfa140 (.DATA_A (INT_CARRY[147]), .DATA_B (INT_CARRY[148]), .DATA_C (INT_CARRY[149]), .SAVE (INT_SUM[201]), .CARRY (INT_CARRY[165]) ); smfulladder dfa141 (.DATA_A (INT_SUM[199]), .DATA_B (INT_SUM[200]), .DATA_C (INT_SUM[201]), .SAVE (INT_SUM[202]), .CARRY (INT_CARRY[166]) ); smfulladder dfa142 (.DATA_A (INT_CARRY[150]), .DATA_B (INT_CARRY[151]), .DATA_C (INT_CARRY[152]), .SAVE (INT_SUM[203]), .CARRY (INT_CARRY[167]) ); smfulladder dfa143 (.DATA_A (INT_SUM[202]), .DATA_B (INT_SUM[203]), .DATA_C (INT_CARRY[153]), .SAVE (INT_SUM[204]), .CARRY (INT_CARRY[168]) ); assign INT_SUM[205] = INT_CARRY[154]; smfulladder dfa144 (.DATA_A (INT_SUM[204]), .DATA_B (INT_SUM[205]), .DATA_C (INT_CARRY[155]), .SAVE (INT_SUM[206]), .CARRY (INT_CARRY[169]) ); assign INT_SUM[207] = INT_CARRY[156]; smhalfadder dha24 (.DATA_A (INT_SUM[206]), .DATA_B (INT_SUM[207]), .SAVE (INT_SUM[208]), .CARRY (INT_CARRY[157]) ); smffb dla261 (.D(INT_SUM[208]), .clk(clk), .en_d2(en_d2), .Q(SUM[26]) ); smffb dla262 (.D(INT_CARRY[157]), .clk(clk), .en_d2(en_d2), .Q(CARRY[26]) ); smffa dla263 (.D(SUMMAND[210]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[210]) ); smffa dla264 (.D(SUMMAND[211]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[211]) ); smffa dla265 (.D(SUMMAND[212]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[212]) ); smfulladder dfa145 (.DATA_A (LATCHED_PP[210]), .DATA_B (LATCHED_PP[211]), .DATA_C (LATCHED_PP[212]), .SAVE (INT_SUM[209]), .CARRY (INT_CARRY[171]) ); smffa dla266 (.D(SUMMAND[213]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[213]) ); smffa dla267 (.D(SUMMAND[214]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[214]) ); smffa dla268 (.D(SUMMAND[215]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[215]) ); smfulladder dfa146 (.DATA_A (LATCHED_PP[213]), .DATA_B (LATCHED_PP[214]), .DATA_C (LATCHED_PP[215]), .SAVE (INT_SUM[210]), .CARRY (INT_CARRY[172]) ); smffa dla269 (.D(SUMMAND[216]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[216]) ); smffa dla270 (.D(SUMMAND[217]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[217]) ); smffa dla271 (.D(SUMMAND[218]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[218]) ); smfulladder dfa147 (.DATA_A (LATCHED_PP[216]), .DATA_B (LATCHED_PP[217]), .DATA_C (LATCHED_PP[218]), .SAVE (INT_SUM[211]), .CARRY (INT_CARRY[173]) ); smffa dla272 (.D(SUMMAND[219]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[219]) ); smffa dla273 (.D(SUMMAND[220]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[220]) ); smffa dla274 (.D(SUMMAND[221]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[221]) ); smfulladder dfa148 (.DATA_A (LATCHED_PP[219]), .DATA_B (LATCHED_PP[220]), .DATA_C (LATCHED_PP[221]), .SAVE (INT_SUM[212]), .CARRY (INT_CARRY[174]) ); smffa dla275 (.D(SUMMAND[222]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[222]) ); smffa dla276 (.D(SUMMAND[223]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[223]) ); smhalfadder dha25 (.DATA_A (LATCHED_PP[222]), .DATA_B (LATCHED_PP[223]), .SAVE (INT_SUM[213]), .CARRY (INT_CARRY[175]) ); smfulladder dfa149 (.DATA_A (INT_SUM[209]), .DATA_B (INT_SUM[210]), .DATA_C (INT_SUM[211]), .SAVE (INT_SUM[214]), .CARRY (INT_CARRY[176]) ); smfulladder dfa150 (.DATA_A (INT_SUM[212]), .DATA_B (INT_SUM[213]), .DATA_C (INT_CARRY[158]), .SAVE (INT_SUM[215]), .CARRY (INT_CARRY[177]) ); smfulladder dfa151 (.DATA_A (INT_CARRY[159]), .DATA_B (INT_CARRY[160]), .DATA_C (INT_CARRY[161]), .SAVE (INT_SUM[216]), .CARRY (INT_CARRY[178]) ); assign INT_SUM[217] = INT_CARRY[162]; smfulladder dfa152 (.DATA_A (INT_SUM[214]), .DATA_B (INT_SUM[215]), .DATA_C (INT_SUM[216]), .SAVE (INT_SUM[218]), .CARRY (INT_CARRY[179]) ); smfulladder dfa153 (.DATA_A (INT_SUM[217]), .DATA_B (INT_CARRY[163]), .DATA_C (INT_CARRY[164]), .SAVE (INT_SUM[219]), .CARRY (INT_CARRY[180]) ); assign INT_SUM[220] = INT_CARRY[165]; smfulladder dfa154 (.DATA_A (INT_SUM[218]), .DATA_B (INT_SUM[219]), .DATA_C (INT_SUM[220]), .SAVE (INT_SUM[221]), .CARRY (INT_CARRY[181]) ); assign INT_SUM[222] = INT_CARRY[166]; assign INT_SUM[223] = INT_CARRY[167]; smfulladder dfa155 (.DATA_A (INT_SUM[221]), .DATA_B (INT_SUM[222]), .DATA_C (INT_SUM[223]), .SAVE (INT_SUM[224]), .CARRY (INT_CARRY[182]) ); assign INT_SUM[225] = INT_CARRY[168]; smfulladder dfa156 (.DATA_A (INT_SUM[224]), .DATA_B (INT_SUM[225]), .DATA_C (INT_CARRY[169]), .SAVE (INT_SUM[226]), .CARRY (INT_CARRY[170]) ); smffb dla277 (.D(INT_SUM[226]), .clk(clk), .en_d2(en_d2), .Q(SUM[27]) ); smffb dla278 (.D(INT_CARRY[170]), .clk(clk), .en_d2(en_d2), .Q(CARRY[27]) ); smffa dla279 (.D(SUMMAND[224]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[224]) ); smffa dla280 (.D(SUMMAND[225]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[225]) ); smffa dla281 (.D(SUMMAND[226]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[226]) ); smfulladder dfa157 (.DATA_A (LATCHED_PP[224]), .DATA_B (LATCHED_PP[225]), .DATA_C (LATCHED_PP[226]), .SAVE (INT_SUM[227]), .CARRY (INT_CARRY[184]) ); smffa dla282 (.D(SUMMAND[227]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[227]) ); smffa dla283 (.D(SUMMAND[228]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[228]) ); smffa dla284 (.D(SUMMAND[229]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[229]) ); smfulladder dfa158 (.DATA_A (LATCHED_PP[227]), .DATA_B (LATCHED_PP[228]), .DATA_C (LATCHED_PP[229]), .SAVE (INT_SUM[228]), .CARRY (INT_CARRY[185]) ); smffa dla285 (.D(SUMMAND[230]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[230]) ); smffa dla286 (.D(SUMMAND[231]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[231]) ); smffa dla287 (.D(SUMMAND[232]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[232]) ); smfulladder dfa159 (.DATA_A (LATCHED_PP[230]), .DATA_B (LATCHED_PP[231]), .DATA_C (LATCHED_PP[232]), .SAVE (INT_SUM[229]), .CARRY (INT_CARRY[186]) ); smffa dla288 (.D(SUMMAND[233]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[233]) ); smffa dla289 (.D(SUMMAND[234]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[234]) ); smffa dla290 (.D(SUMMAND[235]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[235]) ); smfulladder dfa160 (.DATA_A (LATCHED_PP[233]), .DATA_B (LATCHED_PP[234]), .DATA_C (LATCHED_PP[235]), .SAVE (INT_SUM[230]), .CARRY (INT_CARRY[187]) ); smffa dla291 (.D(SUMMAND[236]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[236]) ); smffa dla292 (.D(SUMMAND[237]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[237]) ); smffa dla293 (.D(SUMMAND[238]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[238]) ); smfulladder dfa161 (.DATA_A (LATCHED_PP[236]), .DATA_B (LATCHED_PP[237]), .DATA_C (LATCHED_PP[238]), .SAVE (INT_SUM[231]), .CARRY (INT_CARRY[188]) ); smffa dla294 (.D(SUMMAND[239]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[239]) ); assign INT_SUM[232] = LATCHED_PP[239]; smfulladder dfa162 (.DATA_A (INT_SUM[227]), .DATA_B (INT_SUM[228]), .DATA_C (INT_SUM[229]), .SAVE (INT_SUM[233]), .CARRY (INT_CARRY[189]) ); smfulladder dfa163 (.DATA_A (INT_SUM[230]), .DATA_B (INT_SUM[231]), .DATA_C (INT_SUM[232]), .SAVE (INT_SUM[234]), .CARRY (INT_CARRY[190]) ); smfulladder dfa164 (.DATA_A (INT_CARRY[171]), .DATA_B (INT_CARRY[172]), .DATA_C (INT_CARRY[173]), .SAVE (INT_SUM[235]), .CARRY (INT_CARRY[191]) ); assign INT_SUM[236] = INT_CARRY[174]; assign INT_SUM[237] = INT_CARRY[175]; smfulladder dfa165 (.DATA_A (INT_SUM[233]), .DATA_B (INT_SUM[234]), .DATA_C (INT_SUM[235]), .SAVE (INT_SUM[238]), .CARRY (INT_CARRY[192]) ); smfulladder dfa166 (.DATA_A (INT_SUM[236]), .DATA_B (INT_SUM[237]), .DATA_C (INT_CARRY[176]), .SAVE (INT_SUM[239]), .CARRY (INT_CARRY[193]) ); assign INT_SUM[240] = INT_CARRY[177]; assign INT_SUM[241] = INT_CARRY[178]; smfulladder dfa167 (.DATA_A (INT_SUM[238]), .DATA_B (INT_SUM[239]), .DATA_C (INT_SUM[240]), .SAVE (INT_SUM[242]), .CARRY (INT_CARRY[194]) ); smfulladder dfa168 (.DATA_A (INT_SUM[241]), .DATA_B (INT_CARRY[179]), .DATA_C (INT_CARRY[180]), .SAVE (INT_SUM[243]), .CARRY (INT_CARRY[195]) ); smfulladder dfa169 (.DATA_A (INT_SUM[242]), .DATA_B (INT_SUM[243]), .DATA_C (INT_CARRY[181]), .SAVE (INT_SUM[244]), .CARRY (INT_CARRY[196]) ); smhalfadder dha26 (.DATA_A (INT_SUM[244]), .DATA_B (INT_CARRY[182]), .SAVE (INT_SUM[245]), .CARRY (INT_CARRY[183]) ); smffb dla295 (.D(INT_SUM[245]), .clk(clk), .en_d2(en_d2), .Q(SUM[28]) ); smffb dla296 (.D(INT_CARRY[183]), .clk(clk), .en_d2(en_d2), .Q(CARRY[28]) ); smffa dla297 (.D(SUMMAND[240]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[240]) ); smffa dla298 (.D(SUMMAND[241]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[241]) ); smffa dla299 (.D(SUMMAND[242]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[242]) ); smfulladder dfa170 (.DATA_A (LATCHED_PP[240]), .DATA_B (LATCHED_PP[241]), .DATA_C (LATCHED_PP[242]), .SAVE (INT_SUM[246]), .CARRY (INT_CARRY[198]) ); smffa dla300 (.D(SUMMAND[243]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[243]) ); smffa dla301 (.D(SUMMAND[244]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[244]) ); smffa dla302 (.D(SUMMAND[245]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[245]) ); smfulladder dfa171 (.DATA_A (LATCHED_PP[243]), .DATA_B (LATCHED_PP[244]), .DATA_C (LATCHED_PP[245]), .SAVE (INT_SUM[247]), .CARRY (INT_CARRY[199]) ); smffa dla303 (.D(SUMMAND[246]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[246]) ); smffa dla304 (.D(SUMMAND[247]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[247]) ); smffa dla305 (.D(SUMMAND[248]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[248]) ); smfulladder dfa172 (.DATA_A (LATCHED_PP[246]), .DATA_B (LATCHED_PP[247]), .DATA_C (LATCHED_PP[248]), .SAVE (INT_SUM[248]), .CARRY (INT_CARRY[200]) ); smffa dla306 (.D(SUMMAND[249]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[249]) ); smffa dla307 (.D(SUMMAND[250]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[250]) ); smffa dla308 (.D(SUMMAND[251]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[251]) ); smfulladder dfa173 (.DATA_A (LATCHED_PP[249]), .DATA_B (LATCHED_PP[250]), .DATA_C (LATCHED_PP[251]), .SAVE (INT_SUM[249]), .CARRY (INT_CARRY[201]) ); smffa dla309 (.D(SUMMAND[252]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[252]) ); smffa dla310 (.D(SUMMAND[253]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[253]) ); smffa dla311 (.D(SUMMAND[254]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[254]) ); smfulladder dfa174 (.DATA_A (LATCHED_PP[252]), .DATA_B (LATCHED_PP[253]), .DATA_C (LATCHED_PP[254]), .SAVE (INT_SUM[250]), .CARRY (INT_CARRY[202]) ); smfulladder dfa175 (.DATA_A (INT_SUM[246]), .DATA_B (INT_SUM[247]), .DATA_C (INT_SUM[248]), .SAVE (INT_SUM[251]), .CARRY (INT_CARRY[203]) ); smfulladder dfa176 (.DATA_A (INT_SUM[249]), .DATA_B (INT_SUM[250]), .DATA_C (INT_CARRY[184]), .SAVE (INT_SUM[252]), .CARRY (INT_CARRY[204]) ); smfulladder dfa177 (.DATA_A (INT_CARRY[185]), .DATA_B (INT_CARRY[186]), .DATA_C (INT_CARRY[187]), .SAVE (INT_SUM[253]), .CARRY (INT_CARRY[205]) ); assign INT_SUM[254] = INT_CARRY[188]; smfulladder dfa178 (.DATA_A (INT_SUM[251]), .DATA_B (INT_SUM[252]), .DATA_C (INT_SUM[253]), .SAVE (INT_SUM[255]), .CARRY (INT_CARRY[206]) ); smfulladder dfa179 (.DATA_A (INT_SUM[254]), .DATA_B (INT_CARRY[189]), .DATA_C (INT_CARRY[190]), .SAVE (INT_SUM[256]), .CARRY (INT_CARRY[207]) ); assign INT_SUM[257] = INT_CARRY[191]; smfulladder dfa180 (.DATA_A (INT_SUM[255]), .DATA_B (INT_SUM[256]), .DATA_C (INT_SUM[257]), .SAVE (INT_SUM[258]), .CARRY (INT_CARRY[208]) ); smhalfadder dha27 (.DATA_A (INT_CARRY[192]), .DATA_B (INT_CARRY[193]), .SAVE (INT_SUM[259]), .CARRY (INT_CARRY[209]) ); smfulladder dfa181 (.DATA_A (INT_SUM[258]), .DATA_B (INT_SUM[259]), .DATA_C (INT_CARRY[194]), .SAVE (INT_SUM[260]), .CARRY (INT_CARRY[210]) ); assign INT_SUM[261] = INT_CARRY[195]; smfulladder dfa182 (.DATA_A (INT_SUM[260]), .DATA_B (INT_SUM[261]), .DATA_C (INT_CARRY[196]), .SAVE (INT_SUM[262]), .CARRY (INT_CARRY[197]) ); smffb dla312 (.D(INT_SUM[262]), .clk(clk), .en_d2(en_d2), .Q(SUM[29]) ); smffb dla313 (.D(INT_CARRY[197]), .clk(clk), .en_d2(en_d2), .Q(CARRY[29]) ); smffa dla314 (.D(SUMMAND[255]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[255]) ); smffa dla315 (.D(SUMMAND[256]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[256]) ); smffa dla316 (.D(SUMMAND[257]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[257]) ); smfulladder dfa183 (.DATA_A (LATCHED_PP[255]), .DATA_B (LATCHED_PP[256]), .DATA_C (LATCHED_PP[257]), .SAVE (INT_SUM[263]), .CARRY (INT_CARRY[212]) ); smffa dla317 (.D(SUMMAND[258]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[258]) ); smffa dla318 (.D(SUMMAND[259]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[259]) ); smffa dla319 (.D(SUMMAND[260]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[260]) ); smfulladder dfa184 (.DATA_A (LATCHED_PP[258]), .DATA_B (LATCHED_PP[259]), .DATA_C (LATCHED_PP[260]), .SAVE (INT_SUM[264]), .CARRY (INT_CARRY[213]) ); smffa dla320 (.D(SUMMAND[261]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[261]) ); smffa dla321 (.D(SUMMAND[262]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[262]) ); smffa dla322 (.D(SUMMAND[263]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[263]) ); smfulladder dfa185 (.DATA_A (LATCHED_PP[261]), .DATA_B (LATCHED_PP[262]), .DATA_C (LATCHED_PP[263]), .SAVE (INT_SUM[265]), .CARRY (INT_CARRY[214]) ); smffa dla323 (.D(SUMMAND[264]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[264]) ); smffa dla324 (.D(SUMMAND[265]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[265]) ); smffa dla325 (.D(SUMMAND[266]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[266]) ); smfulladder dfa186 (.DATA_A (LATCHED_PP[264]), .DATA_B (LATCHED_PP[265]), .DATA_C (LATCHED_PP[266]), .SAVE (INT_SUM[266]), .CARRY (INT_CARRY[215]) ); smffa dla326 (.D(SUMMAND[267]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[267]) ); smffa dla327 (.D(SUMMAND[268]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[268]) ); smffa dla328 (.D(SUMMAND[269]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[269]) ); smfulladder dfa187 (.DATA_A (LATCHED_PP[267]), .DATA_B (LATCHED_PP[268]), .DATA_C (LATCHED_PP[269]), .SAVE (INT_SUM[267]), .CARRY (INT_CARRY[216]) ); smffa dla329 (.D(SUMMAND[270]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[270]) ); assign INT_SUM[268] = LATCHED_PP[270]; smffa dla330 (.D(SUMMAND[271]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[271]) ); assign INT_SUM[269] = LATCHED_PP[271]; smfulladder dfa188 (.DATA_A (INT_SUM[263]), .DATA_B (INT_SUM[264]), .DATA_C (INT_SUM[265]), .SAVE (INT_SUM[270]), .CARRY (INT_CARRY[217]) ); smfulladder dfa189 (.DATA_A (INT_SUM[266]), .DATA_B (INT_SUM[267]), .DATA_C (INT_SUM[268]), .SAVE (INT_SUM[271]), .CARRY (INT_CARRY[218]) ); smfulladder dfa190 (.DATA_A (INT_SUM[269]), .DATA_B (INT_CARRY[198]), .DATA_C (INT_CARRY[199]), .SAVE (INT_SUM[272]), .CARRY (INT_CARRY[219]) ); smfulladder dfa191 (.DATA_A (INT_CARRY[200]), .DATA_B (INT_CARRY[201]), .DATA_C (INT_CARRY[202]), .SAVE (INT_SUM[273]), .CARRY (INT_CARRY[220]) ); smfulladder dfa192 (.DATA_A (INT_SUM[270]), .DATA_B (INT_SUM[271]), .DATA_C (INT_SUM[272]), .SAVE (INT_SUM[274]), .CARRY (INT_CARRY[221]) ); smfulladder dfa193 (.DATA_A (INT_SUM[273]), .DATA_B (INT_CARRY[203]), .DATA_C (INT_CARRY[204]), .SAVE (INT_SUM[275]), .CARRY (INT_CARRY[222]) ); assign INT_SUM[276] = INT_CARRY[205]; smfulladder dfa194 (.DATA_A (INT_SUM[274]), .DATA_B (INT_SUM[275]), .DATA_C (INT_SUM[276]), .SAVE (INT_SUM[277]), .CARRY (INT_CARRY[223]) ); smhalfadder dha28 (.DATA_A (INT_CARRY[206]), .DATA_B (INT_CARRY[207]), .SAVE (INT_SUM[278]), .CARRY (INT_CARRY[224]) ); smfulladder dfa195 (.DATA_A (INT_SUM[277]), .DATA_B (INT_SUM[278]), .DATA_C (INT_CARRY[208]), .SAVE (INT_SUM[279]), .CARRY (INT_CARRY[225]) ); assign INT_SUM[280] = INT_CARRY[209]; smfulladder dfa196 (.DATA_A (INT_SUM[279]), .DATA_B (INT_SUM[280]), .DATA_C (INT_CARRY[210]), .SAVE (INT_SUM[281]), .CARRY (INT_CARRY[211]) ); smffb dla331 (.D(INT_SUM[281]), .clk(clk), .en_d2(en_d2), .Q(SUM[30]) ); smffb dla332 (.D(INT_CARRY[211]), .clk(clk), .en_d2(en_d2), .Q(CARRY[30]) ); smffa dla333 (.D(SUMMAND[272]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[272]) ); smffa dla334 (.D(SUMMAND[273]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[273]) ); smffa dla335 (.D(SUMMAND[274]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[274]) ); smfulladder dfa197 (.DATA_A (LATCHED_PP[272]), .DATA_B (LATCHED_PP[273]), .DATA_C (LATCHED_PP[274]), .SAVE (INT_SUM[282]), .CARRY (INT_CARRY[227]) ); smffa dla336 (.D(SUMMAND[275]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[275]) ); smffa dla337 (.D(SUMMAND[276]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[276]) ); smffa dla338 (.D(SUMMAND[277]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[277]) ); smfulladder dfa198 (.DATA_A (LATCHED_PP[275]), .DATA_B (LATCHED_PP[276]), .DATA_C (LATCHED_PP[277]), .SAVE (INT_SUM[283]), .CARRY (INT_CARRY[228]) ); smffa dla339 (.D(SUMMAND[278]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[278]) ); smffa dla340 (.D(SUMMAND[279]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[279]) ); smffa dla341 (.D(SUMMAND[280]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[280]) ); smfulladder dfa199 (.DATA_A (LATCHED_PP[278]), .DATA_B (LATCHED_PP[279]), .DATA_C (LATCHED_PP[280]), .SAVE (INT_SUM[284]), .CARRY (INT_CARRY[229]) ); smffa dla342 (.D(SUMMAND[281]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[281]) ); smffa dla343 (.D(SUMMAND[282]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[282]) ); smffa dla344 (.D(SUMMAND[283]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[283]) ); smfulladder dfa200 (.DATA_A (LATCHED_PP[281]), .DATA_B (LATCHED_PP[282]), .DATA_C (LATCHED_PP[283]), .SAVE (INT_SUM[285]), .CARRY (INT_CARRY[230]) ); smffa dla345 (.D(SUMMAND[284]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[284]) ); smffa dla346 (.D(SUMMAND[285]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[285]) ); smffa dla347 (.D(SUMMAND[286]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[286]) ); smfulladder dfa201 (.DATA_A (LATCHED_PP[284]), .DATA_B (LATCHED_PP[285]), .DATA_C (LATCHED_PP[286]), .SAVE (INT_SUM[286]), .CARRY (INT_CARRY[231]) ); smffa dla348 (.D(SUMMAND[287]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[287]) ); assign INT_SUM[287] = LATCHED_PP[287]; smfulladder dfa202 (.DATA_A (INT_SUM[282]), .DATA_B (INT_SUM[283]), .DATA_C (INT_SUM[284]), .SAVE (INT_SUM[288]), .CARRY (INT_CARRY[232]) ); smfulladder dfa203 (.DATA_A (INT_SUM[285]), .DATA_B (INT_SUM[286]), .DATA_C (INT_SUM[287]), .SAVE (INT_SUM[289]), .CARRY (INT_CARRY[233]) ); smfulladder dfa204 (.DATA_A (INT_CARRY[212]), .DATA_B (INT_CARRY[213]), .DATA_C (INT_CARRY[214]), .SAVE (INT_SUM[290]), .CARRY (INT_CARRY[234]) ); assign INT_SUM[291] = INT_CARRY[215]; assign INT_SUM[292] = INT_CARRY[216]; smfulladder dfa205 (.DATA_A (INT_SUM[288]), .DATA_B (INT_SUM[289]), .DATA_C (INT_SUM[290]), .SAVE (INT_SUM[293]), .CARRY (INT_CARRY[235]) ); smfulladder dfa206 (.DATA_A (INT_SUM[291]), .DATA_B (INT_SUM[292]), .DATA_C (INT_CARRY[217]), .SAVE (INT_SUM[294]), .CARRY (INT_CARRY[236]) ); smfulladder dfa207 (.DATA_A (INT_CARRY[218]), .DATA_B (INT_CARRY[219]), .DATA_C (INT_CARRY[220]), .SAVE (INT_SUM[295]), .CARRY (INT_CARRY[237]) ); smfulladder dfa208 (.DATA_A (INT_SUM[293]), .DATA_B (INT_SUM[294]), .DATA_C (INT_SUM[295]), .SAVE (INT_SUM[296]), .CARRY (INT_CARRY[238]) ); smhalfadder dha29 (.DATA_A (INT_CARRY[221]), .DATA_B (INT_CARRY[222]), .SAVE (INT_SUM[297]), .CARRY (INT_CARRY[239]) ); smfulladder dfa209 (.DATA_A (INT_SUM[296]), .DATA_B (INT_SUM[297]), .DATA_C (INT_CARRY[223]), .SAVE (INT_SUM[298]), .CARRY (INT_CARRY[240]) ); assign INT_SUM[299] = INT_CARRY[224]; smfulladder dfa210 (.DATA_A (INT_SUM[298]), .DATA_B (INT_SUM[299]), .DATA_C (INT_CARRY[225]), .SAVE (INT_SUM[300]), .CARRY (INT_CARRY[226]) ); smffb dla349 (.D(INT_SUM[300]), .clk(clk), .en_d2(en_d2), .Q(SUM[31]) ); smffb dla350 (.D(INT_CARRY[226]), .clk(clk), .en_d2(en_d2), .Q(CARRY[31]) ); smffa dla351 (.D(SUMMAND[288]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[288]) ); smffa dla352 (.D(SUMMAND[289]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[289]) ); smffa dla353 (.D(SUMMAND[290]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[290]) ); smfulladder dfa211 (.DATA_A (LATCHED_PP[288]), .DATA_B (LATCHED_PP[289]), .DATA_C (LATCHED_PP[290]), .SAVE (INT_SUM[301]), .CARRY (INT_CARRY[242]) ); smffa dla354 (.D(SUMMAND[291]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[291]) ); smffa dla355 (.D(SUMMAND[292]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[292]) ); smffa dla356 (.D(SUMMAND[293]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[293]) ); smfulladder dfa212 (.DATA_A (LATCHED_PP[291]), .DATA_B (LATCHED_PP[292]), .DATA_C (LATCHED_PP[293]), .SAVE (INT_SUM[302]), .CARRY (INT_CARRY[243]) ); smffa dla357 (.D(SUMMAND[294]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[294]) ); smffa dla358 (.D(SUMMAND[295]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[295]) ); smffa dla359 (.D(SUMMAND[296]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[296]) ); smfulladder dfa213 (.DATA_A (LATCHED_PP[294]), .DATA_B (LATCHED_PP[295]), .DATA_C (LATCHED_PP[296]), .SAVE (INT_SUM[303]), .CARRY (INT_CARRY[244]) ); smffa dla360 (.D(SUMMAND[297]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[297]) ); smffa dla361 (.D(SUMMAND[298]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[298]) ); smffa dla362 (.D(SUMMAND[299]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[299]) ); smfulladder dfa214 (.DATA_A (LATCHED_PP[297]), .DATA_B (LATCHED_PP[298]), .DATA_C (LATCHED_PP[299]), .SAVE (INT_SUM[304]), .CARRY (INT_CARRY[245]) ); smffa dla363 (.D(SUMMAND[300]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[300]) ); smffa dla364 (.D(SUMMAND[301]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[301]) ); smffa dla365 (.D(SUMMAND[302]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[302]) ); smfulladder dfa215 (.DATA_A (LATCHED_PP[300]), .DATA_B (LATCHED_PP[301]), .DATA_C (LATCHED_PP[302]), .SAVE (INT_SUM[305]), .CARRY (INT_CARRY[246]) ); smffa dla366 (.D(SUMMAND[303]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[303]) ); smffa dla367 (.D(SUMMAND[304]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[304]) ); smffa dla368 (.D(SUMMAND[305]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[305]) ); smfulladder dfa216 (.DATA_A (LATCHED_PP[303]), .DATA_B (LATCHED_PP[304]), .DATA_C (LATCHED_PP[305]), .SAVE (INT_SUM[306]), .CARRY (INT_CARRY[247]) ); smfulladder dfa217 (.DATA_A (INT_SUM[301]), .DATA_B (INT_SUM[302]), .DATA_C (INT_SUM[303]), .SAVE (INT_SUM[307]), .CARRY (INT_CARRY[248]) ); smfulladder dfa218 (.DATA_A (INT_SUM[304]), .DATA_B (INT_SUM[305]), .DATA_C (INT_SUM[306]), .SAVE (INT_SUM[308]), .CARRY (INT_CARRY[249]) ); smfulladder dfa219 (.DATA_A (INT_CARRY[227]), .DATA_B (INT_CARRY[228]), .DATA_C (INT_CARRY[229]), .SAVE (INT_SUM[309]), .CARRY (INT_CARRY[250]) ); smhalfadder dha30 (.DATA_A (INT_CARRY[230]), .DATA_B (INT_CARRY[231]), .SAVE (INT_SUM[310]), .CARRY (INT_CARRY[251]) ); smfulladder dfa220 (.DATA_A (INT_SUM[307]), .DATA_B (INT_SUM[308]), .DATA_C (INT_SUM[309]), .SAVE (INT_SUM[311]), .CARRY (INT_CARRY[252]) ); smfulladder dfa221 (.DATA_A (INT_SUM[310]), .DATA_B (INT_CARRY[232]), .DATA_C (INT_CARRY[233]), .SAVE (INT_SUM[312]), .CARRY (INT_CARRY[253]) ); assign INT_SUM[313] = INT_CARRY[234]; smfulladder dfa222 (.DATA_A (INT_SUM[311]), .DATA_B (INT_SUM[312]), .DATA_C (INT_SUM[313]), .SAVE (INT_SUM[314]), .CARRY (INT_CARRY[254]) ); smfulladder dfa223 (.DATA_A (INT_CARRY[235]), .DATA_B (INT_CARRY[236]), .DATA_C (INT_CARRY[237]), .SAVE (INT_SUM[315]), .CARRY (INT_CARRY[255]) ); smfulladder dfa224 (.DATA_A (INT_SUM[314]), .DATA_B (INT_SUM[315]), .DATA_C (INT_CARRY[238]), .SAVE (INT_SUM[316]), .CARRY (INT_CARRY[256]) ); assign INT_SUM[317] = INT_CARRY[239]; smfulladder dfa225 (.DATA_A (INT_SUM[316]), .DATA_B (INT_SUM[317]), .DATA_C (INT_CARRY[240]), .SAVE (INT_SUM[318]), .CARRY (INT_CARRY[241]) ); smffb dla369 (.D(INT_SUM[318]), .clk(clk), .en_d2(en_d2), .Q(SUM[32]) ); smffb dla370 (.D(INT_CARRY[241]), .clk(clk), .en_d2(en_d2), .Q(CARRY[32]) ); smffa dla371 (.D(SUMMAND[306]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[306]) ); smffa dla372 (.D(SUMMAND[307]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[307]) ); smffa dla373 (.D(SUMMAND[308]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[308]) ); smfulladder dfa226 (.DATA_A (LATCHED_PP[306]), .DATA_B (LATCHED_PP[307]), .DATA_C (LATCHED_PP[308]), .SAVE (INT_SUM[319]), .CARRY (INT_CARRY[258]) ); smffa dla374 (.D(SUMMAND[309]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[309]) ); smffa dla375 (.D(SUMMAND[310]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[310]) ); smffa dla376 (.D(SUMMAND[311]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[311]) ); smfulladder dfa227 (.DATA_A (LATCHED_PP[309]), .DATA_B (LATCHED_PP[310]), .DATA_C (LATCHED_PP[311]), .SAVE (INT_SUM[320]), .CARRY (INT_CARRY[259]) ); smffa dla377 (.D(SUMMAND[312]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[312]) ); smffa dla378 (.D(SUMMAND[313]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[313]) ); smffa dla379 (.D(SUMMAND[314]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[314]) ); smfulladder dfa228 (.DATA_A (LATCHED_PP[312]), .DATA_B (LATCHED_PP[313]), .DATA_C (LATCHED_PP[314]), .SAVE (INT_SUM[321]), .CARRY (INT_CARRY[260]) ); smffa dla380 (.D(SUMMAND[315]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[315]) ); smffa dla381 (.D(SUMMAND[316]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[316]) ); smffa dla382 (.D(SUMMAND[317]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[317]) ); smfulladder dfa229 (.DATA_A (LATCHED_PP[315]), .DATA_B (LATCHED_PP[316]), .DATA_C (LATCHED_PP[317]), .SAVE (INT_SUM[322]), .CARRY (INT_CARRY[261]) ); smffa dla383 (.D(SUMMAND[318]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[318]) ); smffa dla384 (.D(SUMMAND[319]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[319]) ); smffa dla385 (.D(SUMMAND[320]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[320]) ); smfulladder dfa230 (.DATA_A (LATCHED_PP[318]), .DATA_B (LATCHED_PP[319]), .DATA_C (LATCHED_PP[320]), .SAVE (INT_SUM[323]), .CARRY (INT_CARRY[262]) ); smffa dla386 (.D(SUMMAND[321]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[321]) ); assign INT_SUM[324] = LATCHED_PP[321]; smffa dla387 (.D(SUMMAND[322]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[322]) ); assign INT_SUM[325] = LATCHED_PP[322]; smfulladder dfa231 (.DATA_A (INT_SUM[319]), .DATA_B (INT_SUM[320]), .DATA_C (INT_SUM[321]), .SAVE (INT_SUM[326]), .CARRY (INT_CARRY[263]) ); smfulladder dfa232 (.DATA_A (INT_SUM[322]), .DATA_B (INT_SUM[323]), .DATA_C (INT_SUM[324]), .SAVE (INT_SUM[327]), .CARRY (INT_CARRY[264]) ); smfulladder dfa233 (.DATA_A (INT_SUM[325]), .DATA_B (INT_CARRY[242]), .DATA_C (INT_CARRY[243]), .SAVE (INT_SUM[328]), .CARRY (INT_CARRY[265]) ); smfulladder dfa234 (.DATA_A (INT_CARRY[244]), .DATA_B (INT_CARRY[245]), .DATA_C (INT_CARRY[246]), .SAVE (INT_SUM[329]), .CARRY (INT_CARRY[266]) ); assign INT_SUM[330] = INT_CARRY[247]; smfulladder dfa235 (.DATA_A (INT_SUM[326]), .DATA_B (INT_SUM[327]), .DATA_C (INT_SUM[328]), .SAVE (INT_SUM[331]), .CARRY (INT_CARRY[267]) ); smfulladder dfa236 (.DATA_A (INT_SUM[329]), .DATA_B (INT_SUM[330]), .DATA_C (INT_CARRY[248]), .SAVE (INT_SUM[332]), .CARRY (INT_CARRY[268]) ); smfulladder dfa237 (.DATA_A (INT_CARRY[249]), .DATA_B (INT_CARRY[250]), .DATA_C (INT_CARRY[251]), .SAVE (INT_SUM[333]), .CARRY (INT_CARRY[269]) ); smfulladder dfa238 (.DATA_A (INT_SUM[331]), .DATA_B (INT_SUM[332]), .DATA_C (INT_SUM[333]), .SAVE (INT_SUM[334]), .CARRY (INT_CARRY[270]) ); smhalfadder dha31 (.DATA_A (INT_CARRY[252]), .DATA_B (INT_CARRY[253]), .SAVE (INT_SUM[335]), .CARRY (INT_CARRY[271]) ); smfulladder dfa239 (.DATA_A (INT_SUM[334]), .DATA_B (INT_SUM[335]), .DATA_C (INT_CARRY[254]), .SAVE (INT_SUM[336]), .CARRY (INT_CARRY[272]) ); assign INT_SUM[337] = INT_CARRY[255]; smfulladder dfa240 (.DATA_A (INT_SUM[336]), .DATA_B (INT_SUM[337]), .DATA_C (INT_CARRY[256]), .SAVE (INT_SUM[338]), .CARRY (INT_CARRY[257]) ); smffb dla388 (.D(INT_SUM[338]), .clk(clk), .en_d2(en_d2), .Q(SUM[33]) ); smffb dla389 (.D(INT_CARRY[257]), .clk(clk), .en_d2(en_d2), .Q(CARRY[33]) ); smffa dla390 (.D(SUMMAND[323]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[323]) ); smffa dla391 (.D(SUMMAND[324]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[324]) ); smffa dla392 (.D(SUMMAND[325]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[325]) ); smfulladder dfa241 (.DATA_A (LATCHED_PP[323]), .DATA_B (LATCHED_PP[324]), .DATA_C (LATCHED_PP[325]), .SAVE (INT_SUM[339]), .CARRY (INT_CARRY[274]) ); smffa dla393 (.D(SUMMAND[326]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[326]) ); smffa dla394 (.D(SUMMAND[327]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[327]) ); smffa dla395 (.D(SUMMAND[328]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[328]) ); smfulladder dfa242 (.DATA_A (LATCHED_PP[326]), .DATA_B (LATCHED_PP[327]), .DATA_C (LATCHED_PP[328]), .SAVE (INT_SUM[340]), .CARRY (INT_CARRY[275]) ); smffa dla396 (.D(SUMMAND[329]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[329]) ); smffa dla397 (.D(SUMMAND[330]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[330]) ); smffa dla398 (.D(SUMMAND[331]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[331]) ); smfulladder dfa243 (.DATA_A (LATCHED_PP[329]), .DATA_B (LATCHED_PP[330]), .DATA_C (LATCHED_PP[331]), .SAVE (INT_SUM[341]), .CARRY (INT_CARRY[276]) ); smffa dla399 (.D(SUMMAND[332]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[332]) ); smffa dla400 (.D(SUMMAND[333]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[333]) ); smffa dla401 (.D(SUMMAND[334]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[334]) ); smfulladder dfa244 (.DATA_A (LATCHED_PP[332]), .DATA_B (LATCHED_PP[333]), .DATA_C (LATCHED_PP[334]), .SAVE (INT_SUM[342]), .CARRY (INT_CARRY[277]) ); smffa dla402 (.D(SUMMAND[335]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[335]) ); smffa dla403 (.D(SUMMAND[336]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[336]) ); smffa dla404 (.D(SUMMAND[337]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[337]) ); smfulladder dfa245 (.DATA_A (LATCHED_PP[335]), .DATA_B (LATCHED_PP[336]), .DATA_C (LATCHED_PP[337]), .SAVE (INT_SUM[343]), .CARRY (INT_CARRY[278]) ); smffa dla405 (.D(SUMMAND[338]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[338]) ); smffa dla406 (.D(SUMMAND[339]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[339]) ); smffa dla407 (.D(SUMMAND[340]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[340]) ); smfulladder dfa246 (.DATA_A (LATCHED_PP[338]), .DATA_B (LATCHED_PP[339]), .DATA_C (LATCHED_PP[340]), .SAVE (INT_SUM[344]), .CARRY (INT_CARRY[279]) ); smfulladder dfa247 (.DATA_A (INT_SUM[339]), .DATA_B (INT_SUM[340]), .DATA_C (INT_SUM[341]), .SAVE (INT_SUM[345]), .CARRY (INT_CARRY[280]) ); smfulladder dfa248 (.DATA_A (INT_SUM[342]), .DATA_B (INT_SUM[343]), .DATA_C (INT_SUM[344]), .SAVE (INT_SUM[346]), .CARRY (INT_CARRY[281]) ); smfulladder dfa249 (.DATA_A (INT_CARRY[258]), .DATA_B (INT_CARRY[259]), .DATA_C (INT_CARRY[260]), .SAVE (INT_SUM[347]), .CARRY (INT_CARRY[282]) ); assign INT_SUM[348] = INT_CARRY[261]; assign INT_SUM[349] = INT_CARRY[262]; smfulladder dfa250 (.DATA_A (INT_SUM[345]), .DATA_B (INT_SUM[346]), .DATA_C (INT_SUM[347]), .SAVE (INT_SUM[350]), .CARRY (INT_CARRY[283]) ); smfulladder dfa251 (.DATA_A (INT_SUM[348]), .DATA_B (INT_SUM[349]), .DATA_C (INT_CARRY[263]), .SAVE (INT_SUM[351]), .CARRY (INT_CARRY[284]) ); smfulladder dfa252 (.DATA_A (INT_CARRY[264]), .DATA_B (INT_CARRY[265]), .DATA_C (INT_CARRY[266]), .SAVE (INT_SUM[352]), .CARRY (INT_CARRY[285]) ); smfulladder dfa253 (.DATA_A (INT_SUM[350]), .DATA_B (INT_SUM[351]), .DATA_C (INT_SUM[352]), .SAVE (INT_SUM[353]), .CARRY (INT_CARRY[286]) ); smfulladder dfa254 (.DATA_A (INT_CARRY[267]), .DATA_B (INT_CARRY[268]), .DATA_C (INT_CARRY[269]), .SAVE (INT_SUM[354]), .CARRY (INT_CARRY[287]) ); smfulladder dfa255 (.DATA_A (INT_SUM[353]), .DATA_B (INT_SUM[354]), .DATA_C (INT_CARRY[270]), .SAVE (INT_SUM[355]), .CARRY (INT_CARRY[288]) ); assign INT_SUM[356] = INT_CARRY[271]; smfulladder dfa256 (.DATA_A (INT_SUM[355]), .DATA_B (INT_SUM[356]), .DATA_C (INT_CARRY[272]), .SAVE (INT_SUM[357]), .CARRY (INT_CARRY[273]) ); smffb dla408 (.D(INT_SUM[357]), .clk(clk), .en_d2(en_d2), .Q(SUM[34]) ); smffb dla409 (.D(INT_CARRY[273]), .clk(clk), .en_d2(en_d2), .Q(CARRY[34]) ); smffa dla410 (.D(SUMMAND[341]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[341]) ); smffa dla411 (.D(SUMMAND[342]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[342]) ); smffa dla412 (.D(SUMMAND[343]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[343]) ); smfulladder dfa257 (.DATA_A (LATCHED_PP[341]), .DATA_B (LATCHED_PP[342]), .DATA_C (LATCHED_PP[343]), .SAVE (INT_SUM[358]), .CARRY (INT_CARRY[290]) ); smffa dla413 (.D(SUMMAND[344]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[344]) ); smffa dla414 (.D(SUMMAND[345]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[345]) ); smffa dla415 (.D(SUMMAND[346]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[346]) ); smfulladder dfa258 (.DATA_A (LATCHED_PP[344]), .DATA_B (LATCHED_PP[345]), .DATA_C (LATCHED_PP[346]), .SAVE (INT_SUM[359]), .CARRY (INT_CARRY[291]) ); smffa dla416 (.D(SUMMAND[347]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[347]) ); smffa dla417 (.D(SUMMAND[348]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[348]) ); smffa dla418 (.D(SUMMAND[349]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[349]) ); smfulladder dfa259 (.DATA_A (LATCHED_PP[347]), .DATA_B (LATCHED_PP[348]), .DATA_C (LATCHED_PP[349]), .SAVE (INT_SUM[360]), .CARRY (INT_CARRY[292]) ); smffa dla419 (.D(SUMMAND[350]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[350]) ); smffa dla420 (.D(SUMMAND[351]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[351]) ); smffa dla421 (.D(SUMMAND[352]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[352]) ); smfulladder dfa260 (.DATA_A (LATCHED_PP[350]), .DATA_B (LATCHED_PP[351]), .DATA_C (LATCHED_PP[352]), .SAVE (INT_SUM[361]), .CARRY (INT_CARRY[293]) ); smffa dla422 (.D(SUMMAND[353]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[353]) ); smffa dla423 (.D(SUMMAND[354]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[354]) ); smffa dla424 (.D(SUMMAND[355]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[355]) ); smfulladder dfa261 (.DATA_A (LATCHED_PP[353]), .DATA_B (LATCHED_PP[354]), .DATA_C (LATCHED_PP[355]), .SAVE (INT_SUM[362]), .CARRY (INT_CARRY[294]) ); smffa dla425 (.D(SUMMAND[356]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[356]) ); smffa dla426 (.D(SUMMAND[357]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[357]) ); smhalfadder dha32 (.DATA_A (LATCHED_PP[356]), .DATA_B (LATCHED_PP[357]), .SAVE (INT_SUM[363]), .CARRY (INT_CARRY[295]) ); smfulladder dfa262 (.DATA_A (INT_SUM[358]), .DATA_B (INT_SUM[359]), .DATA_C (INT_SUM[360]), .SAVE (INT_SUM[364]), .CARRY (INT_CARRY[296]) ); smfulladder dfa263 (.DATA_A (INT_SUM[361]), .DATA_B (INT_SUM[362]), .DATA_C (INT_SUM[363]), .SAVE (INT_SUM[365]), .CARRY (INT_CARRY[297]) ); smfulladder dfa264 (.DATA_A (INT_CARRY[274]), .DATA_B (INT_CARRY[275]), .DATA_C (INT_CARRY[276]), .SAVE (INT_SUM[366]), .CARRY (INT_CARRY[298]) ); smfulladder dfa265 (.DATA_A (INT_CARRY[277]), .DATA_B (INT_CARRY[278]), .DATA_C (INT_CARRY[279]), .SAVE (INT_SUM[367]), .CARRY (INT_CARRY[299]) ); smfulladder dfa266 (.DATA_A (INT_SUM[364]), .DATA_B (INT_SUM[365]), .DATA_C (INT_SUM[366]), .SAVE (INT_SUM[368]), .CARRY (INT_CARRY[300]) ); smfulladder dfa267 (.DATA_A (INT_SUM[367]), .DATA_B (INT_CARRY[280]), .DATA_C (INT_CARRY[281]), .SAVE (INT_SUM[369]), .CARRY (INT_CARRY[301]) ); assign INT_SUM[370] = INT_CARRY[282]; smfulladder dfa268 (.DATA_A (INT_SUM[368]), .DATA_B (INT_SUM[369]), .DATA_C (INT_SUM[370]), .SAVE (INT_SUM[371]), .CARRY (INT_CARRY[302]) ); smfulladder dfa269 (.DATA_A (INT_CARRY[283]), .DATA_B (INT_CARRY[284]), .DATA_C (INT_CARRY[285]), .SAVE (INT_SUM[372]), .CARRY (INT_CARRY[303]) ); smfulladder dfa270 (.DATA_A (INT_SUM[371]), .DATA_B (INT_SUM[372]), .DATA_C (INT_CARRY[286]), .SAVE (INT_SUM[373]), .CARRY (INT_CARRY[304]) ); assign INT_SUM[374] = INT_CARRY[287]; smfulladder dfa271 (.DATA_A (INT_SUM[373]), .DATA_B (INT_SUM[374]), .DATA_C (INT_CARRY[288]), .SAVE (INT_SUM[375]), .CARRY (INT_CARRY[289]) ); smffb dla427 (.D(INT_SUM[375]), .clk(clk), .en_d2(en_d2), .Q(SUM[35]) ); smffb dla428 (.D(INT_CARRY[289]), .clk(clk), .en_d2(en_d2), .Q(CARRY[35]) ); smffa dla429 (.D(SUMMAND[358]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[358]) ); smffa dla430 (.D(SUMMAND[359]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[359]) ); smffa dla431 (.D(SUMMAND[360]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[360]) ); smfulladder dfa272 (.DATA_A (LATCHED_PP[358]), .DATA_B (LATCHED_PP[359]), .DATA_C (LATCHED_PP[360]), .SAVE (INT_SUM[376]), .CARRY (INT_CARRY[306]) ); smffa dla432 (.D(SUMMAND[361]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[361]) ); smffa dla433 (.D(SUMMAND[362]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[362]) ); smffa dla434 (.D(SUMMAND[363]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[363]) ); smfulladder dfa273 (.DATA_A (LATCHED_PP[361]), .DATA_B (LATCHED_PP[362]), .DATA_C (LATCHED_PP[363]), .SAVE (INT_SUM[377]), .CARRY (INT_CARRY[307]) ); smffa dla435 (.D(SUMMAND[364]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[364]) ); smffa dla436 (.D(SUMMAND[365]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[365]) ); smffa dla437 (.D(SUMMAND[366]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[366]) ); smfulladder dfa274 (.DATA_A (LATCHED_PP[364]), .DATA_B (LATCHED_PP[365]), .DATA_C (LATCHED_PP[366]), .SAVE (INT_SUM[378]), .CARRY (INT_CARRY[308]) ); smffa dla438 (.D(SUMMAND[367]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[367]) ); smffa dla439 (.D(SUMMAND[368]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[368]) ); smffa dla440 (.D(SUMMAND[369]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[369]) ); smfulladder dfa275 (.DATA_A (LATCHED_PP[367]), .DATA_B (LATCHED_PP[368]), .DATA_C (LATCHED_PP[369]), .SAVE (INT_SUM[379]), .CARRY (INT_CARRY[309]) ); smffa dla441 (.D(SUMMAND[370]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[370]) ); smffa dla442 (.D(SUMMAND[371]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[371]) ); smffa dla443 (.D(SUMMAND[372]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[372]) ); smfulladder dfa276 (.DATA_A (LATCHED_PP[370]), .DATA_B (LATCHED_PP[371]), .DATA_C (LATCHED_PP[372]), .SAVE (INT_SUM[380]), .CARRY (INT_CARRY[310]) ); smffa dla444 (.D(SUMMAND[373]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[373]) ); assign INT_SUM[381] = LATCHED_PP[373]; smfulladder dfa277 (.DATA_A (INT_SUM[376]), .DATA_B (INT_SUM[377]), .DATA_C (INT_SUM[378]), .SAVE (INT_SUM[382]), .CARRY (INT_CARRY[311]) ); smfulladder dfa278 (.DATA_A (INT_SUM[379]), .DATA_B (INT_SUM[380]), .DATA_C (INT_SUM[381]), .SAVE (INT_SUM[383]), .CARRY (INT_CARRY[312]) ); smfulladder dfa279 (.DATA_A (INT_CARRY[290]), .DATA_B (INT_CARRY[291]), .DATA_C (INT_CARRY[292]), .SAVE (INT_SUM[384]), .CARRY (INT_CARRY[313]) ); smfulladder dfa280 (.DATA_A (INT_CARRY[293]), .DATA_B (INT_CARRY[294]), .DATA_C (INT_CARRY[295]), .SAVE (INT_SUM[385]), .CARRY (INT_CARRY[314]) ); smfulladder dfa281 (.DATA_A (INT_SUM[382]), .DATA_B (INT_SUM[383]), .DATA_C (INT_SUM[384]), .SAVE (INT_SUM[386]), .CARRY (INT_CARRY[315]) ); smfulladder dfa282 (.DATA_A (INT_SUM[385]), .DATA_B (INT_CARRY[296]), .DATA_C (INT_CARRY[297]), .SAVE (INT_SUM[387]), .CARRY (INT_CARRY[316]) ); assign INT_SUM[388] = INT_CARRY[298]; assign INT_SUM[389] = INT_CARRY[299]; smfulladder dfa283 (.DATA_A (INT_SUM[386]), .DATA_B (INT_SUM[387]), .DATA_C (INT_SUM[388]), .SAVE (INT_SUM[390]), .CARRY (INT_CARRY[317]) ); smfulladder dfa284 (.DATA_A (INT_SUM[389]), .DATA_B (INT_CARRY[300]), .DATA_C (INT_CARRY[301]), .SAVE (INT_SUM[391]), .CARRY (INT_CARRY[318]) ); smfulladder dfa285 (.DATA_A (INT_SUM[390]), .DATA_B (INT_SUM[391]), .DATA_C (INT_CARRY[302]), .SAVE (INT_SUM[392]), .CARRY (INT_CARRY[319]) ); assign INT_SUM[393] = INT_CARRY[303]; smfulladder dfa286 (.DATA_A (INT_SUM[392]), .DATA_B (INT_SUM[393]), .DATA_C (INT_CARRY[304]), .SAVE (INT_SUM[394]), .CARRY (INT_CARRY[305]) ); smffb dla445 (.D(INT_SUM[394]), .clk(clk), .en_d2(en_d2), .Q(SUM[36]) ); smffb dla446 (.D(INT_CARRY[305]), .clk(clk), .en_d2(en_d2), .Q(CARRY[36]) ); smffa dla447 (.D(SUMMAND[374]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[374]) ); smffa dla448 (.D(SUMMAND[375]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[375]) ); smffa dla449 (.D(SUMMAND[376]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[376]) ); smfulladder dfa287 (.DATA_A (LATCHED_PP[374]), .DATA_B (LATCHED_PP[375]), .DATA_C (LATCHED_PP[376]), .SAVE (INT_SUM[395]), .CARRY (INT_CARRY[321]) ); smffa dla450 (.D(SUMMAND[377]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[377]) ); smffa dla451 (.D(SUMMAND[378]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[378]) ); smffa dla452 (.D(SUMMAND[379]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[379]) ); smfulladder dfa288 (.DATA_A (LATCHED_PP[377]), .DATA_B (LATCHED_PP[378]), .DATA_C (LATCHED_PP[379]), .SAVE (INT_SUM[396]), .CARRY (INT_CARRY[322]) ); smffa dla453 (.D(SUMMAND[380]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[380]) ); smffa dla454 (.D(SUMMAND[381]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[381]) ); smffa dla455 (.D(SUMMAND[382]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[382]) ); smfulladder dfa289 (.DATA_A (LATCHED_PP[380]), .DATA_B (LATCHED_PP[381]), .DATA_C (LATCHED_PP[382]), .SAVE (INT_SUM[397]), .CARRY (INT_CARRY[323]) ); smffa dla456 (.D(SUMMAND[383]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[383]) ); smffa dla457 (.D(SUMMAND[384]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[384]) ); smffa dla458 (.D(SUMMAND[385]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[385]) ); smfulladder dfa290 (.DATA_A (LATCHED_PP[383]), .DATA_B (LATCHED_PP[384]), .DATA_C (LATCHED_PP[385]), .SAVE (INT_SUM[398]), .CARRY (INT_CARRY[324]) ); smffa dla459 (.D(SUMMAND[386]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[386]) ); smffa dla460 (.D(SUMMAND[387]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[387]) ); smffa dla461 (.D(SUMMAND[388]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[388]) ); smfulladder dfa291 (.DATA_A (LATCHED_PP[386]), .DATA_B (LATCHED_PP[387]), .DATA_C (LATCHED_PP[388]), .SAVE (INT_SUM[399]), .CARRY (INT_CARRY[325]) ); smffa dla462 (.D(SUMMAND[389]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[389]) ); assign INT_SUM[400] = LATCHED_PP[389]; smfulladder dfa292 (.DATA_A (INT_SUM[395]), .DATA_B (INT_SUM[396]), .DATA_C (INT_SUM[397]), .SAVE (INT_SUM[401]), .CARRY (INT_CARRY[326]) ); smfulladder dfa293 (.DATA_A (INT_SUM[398]), .DATA_B (INT_SUM[399]), .DATA_C (INT_SUM[400]), .SAVE (INT_SUM[402]), .CARRY (INT_CARRY[327]) ); smfulladder dfa294 (.DATA_A (INT_CARRY[306]), .DATA_B (INT_CARRY[307]), .DATA_C (INT_CARRY[308]), .SAVE (INT_SUM[403]), .CARRY (INT_CARRY[328]) ); assign INT_SUM[404] = INT_CARRY[309]; assign INT_SUM[405] = INT_CARRY[310]; smfulladder dfa295 (.DATA_A (INT_SUM[401]), .DATA_B (INT_SUM[402]), .DATA_C (INT_SUM[403]), .SAVE (INT_SUM[406]), .CARRY (INT_CARRY[329]) ); smfulladder dfa296 (.DATA_A (INT_SUM[404]), .DATA_B (INT_SUM[405]), .DATA_C (INT_CARRY[311]), .SAVE (INT_SUM[407]), .CARRY (INT_CARRY[330]) ); smfulladder dfa297 (.DATA_A (INT_CARRY[312]), .DATA_B (INT_CARRY[313]), .DATA_C (INT_CARRY[314]), .SAVE (INT_SUM[408]), .CARRY (INT_CARRY[331]) ); smfulladder dfa298 (.DATA_A (INT_SUM[406]), .DATA_B (INT_SUM[407]), .DATA_C (INT_SUM[408]), .SAVE (INT_SUM[409]), .CARRY (INT_CARRY[332]) ); smhalfadder dha33 (.DATA_A (INT_CARRY[315]), .DATA_B (INT_CARRY[316]), .SAVE (INT_SUM[410]), .CARRY (INT_CARRY[333]) ); smfulladder dfa299 (.DATA_A (INT_SUM[409]), .DATA_B (INT_SUM[410]), .DATA_C (INT_CARRY[317]), .SAVE (INT_SUM[411]), .CARRY (INT_CARRY[334]) ); assign INT_SUM[412] = INT_CARRY[318]; smfulladder dfa300 (.DATA_A (INT_SUM[411]), .DATA_B (INT_SUM[412]), .DATA_C (INT_CARRY[319]), .SAVE (INT_SUM[413]), .CARRY (INT_CARRY[320]) ); smffb dla463 (.D(INT_SUM[413]), .clk(clk), .en_d2(en_d2), .Q(SUM[37]) ); smffb dla464 (.D(INT_CARRY[320]), .clk(clk), .en_d2(en_d2), .Q(CARRY[37]) ); smffa dla465 (.D(SUMMAND[390]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[390]) ); smffa dla466 (.D(SUMMAND[391]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[391]) ); smffa dla467 (.D(SUMMAND[392]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[392]) ); smfulladder dfa301 (.DATA_A (LATCHED_PP[390]), .DATA_B (LATCHED_PP[391]), .DATA_C (LATCHED_PP[392]), .SAVE (INT_SUM[414]), .CARRY (INT_CARRY[336]) ); smffa dla468 (.D(SUMMAND[393]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[393]) ); smffa dla469 (.D(SUMMAND[394]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[394]) ); smffa dla470 (.D(SUMMAND[395]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[395]) ); smfulladder dfa302 (.DATA_A (LATCHED_PP[393]), .DATA_B (LATCHED_PP[394]), .DATA_C (LATCHED_PP[395]), .SAVE (INT_SUM[415]), .CARRY (INT_CARRY[337]) ); smffa dla471 (.D(SUMMAND[396]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[396]) ); smffa dla472 (.D(SUMMAND[397]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[397]) ); smffa dla473 (.D(SUMMAND[398]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[398]) ); smfulladder dfa303 (.DATA_A (LATCHED_PP[396]), .DATA_B (LATCHED_PP[397]), .DATA_C (LATCHED_PP[398]), .SAVE (INT_SUM[416]), .CARRY (INT_CARRY[338]) ); smffa dla474 (.D(SUMMAND[399]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[399]) ); smffa dla475 (.D(SUMMAND[400]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[400]) ); smffa dla476 (.D(SUMMAND[401]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[401]) ); smfulladder dfa304 (.DATA_A (LATCHED_PP[399]), .DATA_B (LATCHED_PP[400]), .DATA_C (LATCHED_PP[401]), .SAVE (INT_SUM[417]), .CARRY (INT_CARRY[339]) ); smffa dla477 (.D(SUMMAND[402]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[402]) ); smffa dla478 (.D(SUMMAND[403]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[403]) ); smffa dla479 (.D(SUMMAND[404]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[404]) ); smfulladder dfa305 (.DATA_A (LATCHED_PP[402]), .DATA_B (LATCHED_PP[403]), .DATA_C (LATCHED_PP[404]), .SAVE (INT_SUM[418]), .CARRY (INT_CARRY[340]) ); smfulladder dfa306 (.DATA_A (INT_SUM[414]), .DATA_B (INT_SUM[415]), .DATA_C (INT_SUM[416]), .SAVE (INT_SUM[419]), .CARRY (INT_CARRY[341]) ); smfulladder dfa307 (.DATA_A (INT_SUM[417]), .DATA_B (INT_SUM[418]), .DATA_C (INT_CARRY[321]), .SAVE (INT_SUM[420]), .CARRY (INT_CARRY[342]) ); smfulladder dfa308 (.DATA_A (INT_CARRY[322]), .DATA_B (INT_CARRY[323]), .DATA_C (INT_CARRY[324]), .SAVE (INT_SUM[421]), .CARRY (INT_CARRY[343]) ); assign INT_SUM[422] = INT_CARRY[325]; smfulladder dfa309 (.DATA_A (INT_SUM[419]), .DATA_B (INT_SUM[420]), .DATA_C (INT_SUM[421]), .SAVE (INT_SUM[423]), .CARRY (INT_CARRY[344]) ); smfulladder dfa310 (.DATA_A (INT_SUM[422]), .DATA_B (INT_CARRY[326]), .DATA_C (INT_CARRY[327]), .SAVE (INT_SUM[424]), .CARRY (INT_CARRY[345]) ); assign INT_SUM[425] = INT_CARRY[328]; smfulladder dfa311 (.DATA_A (INT_SUM[423]), .DATA_B (INT_SUM[424]), .DATA_C (INT_SUM[425]), .SAVE (INT_SUM[426]), .CARRY (INT_CARRY[346]) ); smfulladder dfa312 (.DATA_A (INT_CARRY[329]), .DATA_B (INT_CARRY[330]), .DATA_C (INT_CARRY[331]), .SAVE (INT_SUM[427]), .CARRY (INT_CARRY[347]) ); smfulladder dfa313 (.DATA_A (INT_SUM[426]), .DATA_B (INT_SUM[427]), .DATA_C (INT_CARRY[332]), .SAVE (INT_SUM[428]), .CARRY (INT_CARRY[348]) ); assign INT_SUM[429] = INT_CARRY[333]; smfulladder dfa314 (.DATA_A (INT_SUM[428]), .DATA_B (INT_SUM[429]), .DATA_C (INT_CARRY[334]), .SAVE (INT_SUM[430]), .CARRY (INT_CARRY[335]) ); smffb dla480 (.D(INT_SUM[430]), .clk(clk), .en_d2(en_d2), .Q(SUM[38]) ); smffb dla481 (.D(INT_CARRY[335]), .clk(clk), .en_d2(en_d2), .Q(CARRY[38]) ); smffa dla482 (.D(SUMMAND[405]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[405]) ); smffa dla483 (.D(SUMMAND[406]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[406]) ); smffa dla484 (.D(SUMMAND[407]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[407]) ); smfulladder dfa315 (.DATA_A (LATCHED_PP[405]), .DATA_B (LATCHED_PP[406]), .DATA_C (LATCHED_PP[407]), .SAVE (INT_SUM[431]), .CARRY (INT_CARRY[350]) ); smffa dla485 (.D(SUMMAND[408]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[408]) ); smffa dla486 (.D(SUMMAND[409]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[409]) ); smffa dla487 (.D(SUMMAND[410]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[410]) ); smfulladder dfa316 (.DATA_A (LATCHED_PP[408]), .DATA_B (LATCHED_PP[409]), .DATA_C (LATCHED_PP[410]), .SAVE (INT_SUM[432]), .CARRY (INT_CARRY[351]) ); smffa dla488 (.D(SUMMAND[411]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[411]) ); smffa dla489 (.D(SUMMAND[412]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[412]) ); smffa dla490 (.D(SUMMAND[413]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[413]) ); smfulladder dfa317 (.DATA_A (LATCHED_PP[411]), .DATA_B (LATCHED_PP[412]), .DATA_C (LATCHED_PP[413]), .SAVE (INT_SUM[433]), .CARRY (INT_CARRY[352]) ); smffa dla491 (.D(SUMMAND[414]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[414]) ); smffa dla492 (.D(SUMMAND[415]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[415]) ); smffa dla493 (.D(SUMMAND[416]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[416]) ); smfulladder dfa318 (.DATA_A (LATCHED_PP[414]), .DATA_B (LATCHED_PP[415]), .DATA_C (LATCHED_PP[416]), .SAVE (INT_SUM[434]), .CARRY (INT_CARRY[353]) ); smffa dla494 (.D(SUMMAND[417]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[417]) ); smffa dla495 (.D(SUMMAND[418]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[418]) ); smffa dla496 (.D(SUMMAND[419]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[419]) ); smfulladder dfa319 (.DATA_A (LATCHED_PP[417]), .DATA_B (LATCHED_PP[418]), .DATA_C (LATCHED_PP[419]), .SAVE (INT_SUM[435]), .CARRY (INT_CARRY[354]) ); smfulladder dfa320 (.DATA_A (INT_SUM[431]), .DATA_B (INT_SUM[432]), .DATA_C (INT_SUM[433]), .SAVE (INT_SUM[436]), .CARRY (INT_CARRY[355]) ); smfulladder dfa321 (.DATA_A (INT_SUM[434]), .DATA_B (INT_SUM[435]), .DATA_C (INT_CARRY[336]), .SAVE (INT_SUM[437]), .CARRY (INT_CARRY[356]) ); smfulladder dfa322 (.DATA_A (INT_CARRY[337]), .DATA_B (INT_CARRY[338]), .DATA_C (INT_CARRY[339]), .SAVE (INT_SUM[438]), .CARRY (INT_CARRY[357]) ); assign INT_SUM[439] = INT_CARRY[340]; smfulladder dfa323 (.DATA_A (INT_SUM[436]), .DATA_B (INT_SUM[437]), .DATA_C (INT_SUM[438]), .SAVE (INT_SUM[440]), .CARRY (INT_CARRY[358]) ); smfulladder dfa324 (.DATA_A (INT_SUM[439]), .DATA_B (INT_CARRY[341]), .DATA_C (INT_CARRY[342]), .SAVE (INT_SUM[441]), .CARRY (INT_CARRY[359]) ); assign INT_SUM[442] = INT_CARRY[343]; smfulladder dfa325 (.DATA_A (INT_SUM[440]), .DATA_B (INT_SUM[441]), .DATA_C (INT_SUM[442]), .SAVE (INT_SUM[443]), .CARRY (INT_CARRY[360]) ); smhalfadder dha34 (.DATA_A (INT_CARRY[344]), .DATA_B (INT_CARRY[345]), .SAVE (INT_SUM[444]), .CARRY (INT_CARRY[361]) ); smfulladder dfa326 (.DATA_A (INT_SUM[443]), .DATA_B (INT_SUM[444]), .DATA_C (INT_CARRY[346]), .SAVE (INT_SUM[445]), .CARRY (INT_CARRY[362]) ); assign INT_SUM[446] = INT_CARRY[347]; smfulladder dfa327 (.DATA_A (INT_SUM[445]), .DATA_B (INT_SUM[446]), .DATA_C (INT_CARRY[348]), .SAVE (INT_SUM[447]), .CARRY (INT_CARRY[349]) ); smffb dla497 (.D(INT_SUM[447]), .clk(clk), .en_d2(en_d2), .Q(SUM[39]) ); smffb dla498 (.D(INT_CARRY[349]), .clk(clk), .en_d2(en_d2), .Q(CARRY[39]) ); smffa dla499 (.D(SUMMAND[420]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[420]) ); smffa dla500 (.D(SUMMAND[421]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[421]) ); smffa dla501 (.D(SUMMAND[422]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[422]) ); smfulladder dfa328 (.DATA_A (LATCHED_PP[420]), .DATA_B (LATCHED_PP[421]), .DATA_C (LATCHED_PP[422]), .SAVE (INT_SUM[448]), .CARRY (INT_CARRY[364]) ); smffa dla502 (.D(SUMMAND[423]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[423]) ); smffa dla503 (.D(SUMMAND[424]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[424]) ); smffa dla504 (.D(SUMMAND[425]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[425]) ); smfulladder dfa329 (.DATA_A (LATCHED_PP[423]), .DATA_B (LATCHED_PP[424]), .DATA_C (LATCHED_PP[425]), .SAVE (INT_SUM[449]), .CARRY (INT_CARRY[365]) ); smffa dla505 (.D(SUMMAND[426]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[426]) ); smffa dla506 (.D(SUMMAND[427]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[427]) ); smffa dla507 (.D(SUMMAND[428]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[428]) ); smfulladder dfa330 (.DATA_A (LATCHED_PP[426]), .DATA_B (LATCHED_PP[427]), .DATA_C (LATCHED_PP[428]), .SAVE (INT_SUM[450]), .CARRY (INT_CARRY[366]) ); smffa dla508 (.D(SUMMAND[429]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[429]) ); smffa dla509 (.D(SUMMAND[430]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[430]) ); smffa dla510 (.D(SUMMAND[431]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[431]) ); smfulladder dfa331 (.DATA_A (LATCHED_PP[429]), .DATA_B (LATCHED_PP[430]), .DATA_C (LATCHED_PP[431]), .SAVE (INT_SUM[451]), .CARRY (INT_CARRY[367]) ); smffa dla511 (.D(SUMMAND[432]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[432]) ); smffa dla512 (.D(SUMMAND[433]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[433]) ); smhalfadder dha35 (.DATA_A (LATCHED_PP[432]), .DATA_B (LATCHED_PP[433]), .SAVE (INT_SUM[452]), .CARRY (INT_CARRY[368]) ); smfulladder dfa332 (.DATA_A (INT_SUM[448]), .DATA_B (INT_SUM[449]), .DATA_C (INT_SUM[450]), .SAVE (INT_SUM[453]), .CARRY (INT_CARRY[369]) ); smfulladder dfa333 (.DATA_A (INT_SUM[451]), .DATA_B (INT_SUM[452]), .DATA_C (INT_CARRY[350]), .SAVE (INT_SUM[454]), .CARRY (INT_CARRY[370]) ); smfulladder dfa334 (.DATA_A (INT_CARRY[351]), .DATA_B (INT_CARRY[352]), .DATA_C (INT_CARRY[353]), .SAVE (INT_SUM[455]), .CARRY (INT_CARRY[371]) ); assign INT_SUM[456] = INT_CARRY[354]; smfulladder dfa335 (.DATA_A (INT_SUM[453]), .DATA_B (INT_SUM[454]), .DATA_C (INT_SUM[455]), .SAVE (INT_SUM[457]), .CARRY (INT_CARRY[372]) ); smfulladder dfa336 (.DATA_A (INT_SUM[456]), .DATA_B (INT_CARRY[355]), .DATA_C (INT_CARRY[356]), .SAVE (INT_SUM[458]), .CARRY (INT_CARRY[373]) ); assign INT_SUM[459] = INT_CARRY[357]; smfulladder dfa337 (.DATA_A (INT_SUM[457]), .DATA_B (INT_SUM[458]), .DATA_C (INT_SUM[459]), .SAVE (INT_SUM[460]), .CARRY (INT_CARRY[374]) ); smhalfadder dha36 (.DATA_A (INT_CARRY[358]), .DATA_B (INT_CARRY[359]), .SAVE (INT_SUM[461]), .CARRY (INT_CARRY[375]) ); smfulladder dfa338 (.DATA_A (INT_SUM[460]), .DATA_B (INT_SUM[461]), .DATA_C (INT_CARRY[360]), .SAVE (INT_SUM[462]), .CARRY (INT_CARRY[376]) ); assign INT_SUM[463] = INT_CARRY[361]; smfulladder dfa339 (.DATA_A (INT_SUM[462]), .DATA_B (INT_SUM[463]), .DATA_C (INT_CARRY[362]), .SAVE (INT_SUM[464]), .CARRY (INT_CARRY[363]) ); smffb dla513 (.D(INT_SUM[464]), .clk(clk), .en_d2(en_d2), .Q(SUM[40]) ); smffb dla514 (.D(INT_CARRY[363]), .clk(clk), .en_d2(en_d2), .Q(CARRY[40]) ); smffa dla515 (.D(SUMMAND[434]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[434]) ); smffa dla516 (.D(SUMMAND[435]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[435]) ); smffa dla517 (.D(SUMMAND[436]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[436]) ); smfulladder dfa340 (.DATA_A (LATCHED_PP[434]), .DATA_B (LATCHED_PP[435]), .DATA_C (LATCHED_PP[436]), .SAVE (INT_SUM[465]), .CARRY (INT_CARRY[378]) ); smffa dla518 (.D(SUMMAND[437]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[437]) ); smffa dla519 (.D(SUMMAND[438]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[438]) ); smffa dla520 (.D(SUMMAND[439]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[439]) ); smfulladder dfa341 (.DATA_A (LATCHED_PP[437]), .DATA_B (LATCHED_PP[438]), .DATA_C (LATCHED_PP[439]), .SAVE (INT_SUM[466]), .CARRY (INT_CARRY[379]) ); smffa dla521 (.D(SUMMAND[440]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[440]) ); smffa dla522 (.D(SUMMAND[441]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[441]) ); smffa dla523 (.D(SUMMAND[442]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[442]) ); smfulladder dfa342 (.DATA_A (LATCHED_PP[440]), .DATA_B (LATCHED_PP[441]), .DATA_C (LATCHED_PP[442]), .SAVE (INT_SUM[467]), .CARRY (INT_CARRY[380]) ); smffa dla524 (.D(SUMMAND[443]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[443]) ); smffa dla525 (.D(SUMMAND[444]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[444]) ); smffa dla526 (.D(SUMMAND[445]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[445]) ); smfulladder dfa343 (.DATA_A (LATCHED_PP[443]), .DATA_B (LATCHED_PP[444]), .DATA_C (LATCHED_PP[445]), .SAVE (INT_SUM[468]), .CARRY (INT_CARRY[381]) ); smffa dla527 (.D(SUMMAND[446]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[446]) ); smffa dla528 (.D(SUMMAND[447]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[447]) ); smhalfadder dha37 (.DATA_A (LATCHED_PP[446]), .DATA_B (LATCHED_PP[447]), .SAVE (INT_SUM[469]), .CARRY (INT_CARRY[382]) ); smfulladder dfa344 (.DATA_A (INT_SUM[465]), .DATA_B (INT_SUM[466]), .DATA_C (INT_SUM[467]), .SAVE (INT_SUM[470]), .CARRY (INT_CARRY[383]) ); smfulladder dfa345 (.DATA_A (INT_SUM[468]), .DATA_B (INT_SUM[469]), .DATA_C (INT_CARRY[364]), .SAVE (INT_SUM[471]), .CARRY (INT_CARRY[384]) ); smfulladder dfa346 (.DATA_A (INT_CARRY[365]), .DATA_B (INT_CARRY[366]), .DATA_C (INT_CARRY[367]), .SAVE (INT_SUM[472]), .CARRY (INT_CARRY[385]) ); assign INT_SUM[473] = INT_CARRY[368]; smfulladder dfa347 (.DATA_A (INT_SUM[470]), .DATA_B (INT_SUM[471]), .DATA_C (INT_SUM[472]), .SAVE (INT_SUM[474]), .CARRY (INT_CARRY[386]) ); smfulladder dfa348 (.DATA_A (INT_SUM[473]), .DATA_B (INT_CARRY[369]), .DATA_C (INT_CARRY[370]), .SAVE (INT_SUM[475]), .CARRY (INT_CARRY[387]) ); assign INT_SUM[476] = INT_CARRY[371]; smfulladder dfa349 (.DATA_A (INT_SUM[474]), .DATA_B (INT_SUM[475]), .DATA_C (INT_SUM[476]), .SAVE (INT_SUM[477]), .CARRY (INT_CARRY[388]) ); smhalfadder dha38 (.DATA_A (INT_CARRY[372]), .DATA_B (INT_CARRY[373]), .SAVE (INT_SUM[478]), .CARRY (INT_CARRY[389]) ); smfulladder dfa350 (.DATA_A (INT_SUM[477]), .DATA_B (INT_SUM[478]), .DATA_C (INT_CARRY[374]), .SAVE (INT_SUM[479]), .CARRY (INT_CARRY[390]) ); assign INT_SUM[480] = INT_CARRY[375]; smfulladder dfa351 (.DATA_A (INT_SUM[479]), .DATA_B (INT_SUM[480]), .DATA_C (INT_CARRY[376]), .SAVE (INT_SUM[481]), .CARRY (INT_CARRY[377]) ); smffb dla529 (.D(INT_SUM[481]), .clk(clk), .en_d2(en_d2), .Q(SUM[41]) ); smffb dla530 (.D(INT_CARRY[377]), .clk(clk), .en_d2(en_d2), .Q(CARRY[41]) ); smffa dla531 (.D(SUMMAND[448]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[448]) ); smffa dla532 (.D(SUMMAND[449]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[449]) ); smffa dla533 (.D(SUMMAND[450]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[450]) ); smfulladder dfa352 (.DATA_A (LATCHED_PP[448]), .DATA_B (LATCHED_PP[449]), .DATA_C (LATCHED_PP[450]), .SAVE (INT_SUM[482]), .CARRY (INT_CARRY[392]) ); smffa dla534 (.D(SUMMAND[451]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[451]) ); smffa dla535 (.D(SUMMAND[452]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[452]) ); smffa dla536 (.D(SUMMAND[453]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[453]) ); smfulladder dfa353 (.DATA_A (LATCHED_PP[451]), .DATA_B (LATCHED_PP[452]), .DATA_C (LATCHED_PP[453]), .SAVE (INT_SUM[483]), .CARRY (INT_CARRY[393]) ); smffa dla537 (.D(SUMMAND[454]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[454]) ); smffa dla538 (.D(SUMMAND[455]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[455]) ); smffa dla539 (.D(SUMMAND[456]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[456]) ); smfulladder dfa354 (.DATA_A (LATCHED_PP[454]), .DATA_B (LATCHED_PP[455]), .DATA_C (LATCHED_PP[456]), .SAVE (INT_SUM[484]), .CARRY (INT_CARRY[394]) ); smffa dla540 (.D(SUMMAND[457]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[457]) ); smffa dla541 (.D(SUMMAND[458]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[458]) ); smffa dla542 (.D(SUMMAND[459]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[459]) ); smfulladder dfa355 (.DATA_A (LATCHED_PP[457]), .DATA_B (LATCHED_PP[458]), .DATA_C (LATCHED_PP[459]), .SAVE (INT_SUM[485]), .CARRY (INT_CARRY[395]) ); smffa dla543 (.D(SUMMAND[460]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[460]) ); assign INT_SUM[486] = LATCHED_PP[460]; smfulladder dfa356 (.DATA_A (INT_SUM[482]), .DATA_B (INT_SUM[483]), .DATA_C (INT_SUM[484]), .SAVE (INT_SUM[487]), .CARRY (INT_CARRY[396]) ); smfulladder dfa357 (.DATA_A (INT_SUM[485]), .DATA_B (INT_SUM[486]), .DATA_C (INT_CARRY[378]), .SAVE (INT_SUM[488]), .CARRY (INT_CARRY[397]) ); smfulladder dfa358 (.DATA_A (INT_CARRY[379]), .DATA_B (INT_CARRY[380]), .DATA_C (INT_CARRY[381]), .SAVE (INT_SUM[489]), .CARRY (INT_CARRY[398]) ); assign INT_SUM[490] = INT_CARRY[382]; smfulladder dfa359 (.DATA_A (INT_SUM[487]), .DATA_B (INT_SUM[488]), .DATA_C (INT_SUM[489]), .SAVE (INT_SUM[491]), .CARRY (INT_CARRY[399]) ); smfulladder dfa360 (.DATA_A (INT_SUM[490]), .DATA_B (INT_CARRY[383]), .DATA_C (INT_CARRY[384]), .SAVE (INT_SUM[492]), .CARRY (INT_CARRY[400]) ); assign INT_SUM[493] = INT_CARRY[385]; smfulladder dfa361 (.DATA_A (INT_SUM[491]), .DATA_B (INT_SUM[492]), .DATA_C (INT_SUM[493]), .SAVE (INT_SUM[494]), .CARRY (INT_CARRY[401]) ); smhalfadder dha39 (.DATA_A (INT_CARRY[386]), .DATA_B (INT_CARRY[387]), .SAVE (INT_SUM[495]), .CARRY (INT_CARRY[402]) ); smfulladder dfa362 (.DATA_A (INT_SUM[494]), .DATA_B (INT_SUM[495]), .DATA_C (INT_CARRY[388]), .SAVE (INT_SUM[496]), .CARRY (INT_CARRY[403]) ); assign INT_SUM[497] = INT_CARRY[389]; smfulladder dfa363 (.DATA_A (INT_SUM[496]), .DATA_B (INT_SUM[497]), .DATA_C (INT_CARRY[390]), .SAVE (INT_SUM[498]), .CARRY (INT_CARRY[391]) ); smffb dla544 (.D(INT_SUM[498]), .clk(clk), .en_d2(en_d2), .Q(SUM[42]) ); smffb dla545 (.D(INT_CARRY[391]), .clk(clk), .en_d2(en_d2), .Q(CARRY[42]) ); smffa dla546 (.D(SUMMAND[461]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[461]) ); smffa dla547 (.D(SUMMAND[462]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[462]) ); smffa dla548 (.D(SUMMAND[463]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[463]) ); smfulladder dfa364 (.DATA_A (LATCHED_PP[461]), .DATA_B (LATCHED_PP[462]), .DATA_C (LATCHED_PP[463]), .SAVE (INT_SUM[499]), .CARRY (INT_CARRY[405]) ); smffa dla549 (.D(SUMMAND[464]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[464]) ); smffa dla550 (.D(SUMMAND[465]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[465]) ); smffa dla551 (.D(SUMMAND[466]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[466]) ); smfulladder dfa365 (.DATA_A (LATCHED_PP[464]), .DATA_B (LATCHED_PP[465]), .DATA_C (LATCHED_PP[466]), .SAVE (INT_SUM[500]), .CARRY (INT_CARRY[406]) ); smffa dla552 (.D(SUMMAND[467]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[467]) ); smffa dla553 (.D(SUMMAND[468]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[468]) ); smffa dla554 (.D(SUMMAND[469]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[469]) ); smfulladder dfa366 (.DATA_A (LATCHED_PP[467]), .DATA_B (LATCHED_PP[468]), .DATA_C (LATCHED_PP[469]), .SAVE (INT_SUM[501]), .CARRY (INT_CARRY[407]) ); smffa dla555 (.D(SUMMAND[470]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[470]) ); smffa dla556 (.D(SUMMAND[471]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[471]) ); smffa dla557 (.D(SUMMAND[472]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[472]) ); smfulladder dfa367 (.DATA_A (LATCHED_PP[470]), .DATA_B (LATCHED_PP[471]), .DATA_C (LATCHED_PP[472]), .SAVE (INT_SUM[502]), .CARRY (INT_CARRY[408]) ); smffa dla558 (.D(SUMMAND[473]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[473]) ); smfulladder dfa368 (.DATA_A (LATCHED_PP[473]), .DATA_B (INT_CARRY[392]), .DATA_C (INT_CARRY[393]), .SAVE (INT_SUM[503]), .CARRY (INT_CARRY[409]) ); assign INT_SUM[504] = INT_CARRY[394]; assign INT_SUM[505] = INT_CARRY[395]; smfulladder dfa369 (.DATA_A (INT_SUM[499]), .DATA_B (INT_SUM[500]), .DATA_C (INT_SUM[501]), .SAVE (INT_SUM[506]), .CARRY (INT_CARRY[410]) ); smfulladder dfa370 (.DATA_A (INT_SUM[502]), .DATA_B (INT_SUM[503]), .DATA_C (INT_SUM[504]), .SAVE (INT_SUM[507]), .CARRY (INT_CARRY[411]) ); smfulladder dfa371 (.DATA_A (INT_SUM[505]), .DATA_B (INT_CARRY[396]), .DATA_C (INT_CARRY[397]), .SAVE (INT_SUM[508]), .CARRY (INT_CARRY[412]) ); assign INT_SUM[509] = INT_CARRY[398]; smfulladder dfa372 (.DATA_A (INT_SUM[506]), .DATA_B (INT_SUM[507]), .DATA_C (INT_SUM[508]), .SAVE (INT_SUM[510]), .CARRY (INT_CARRY[413]) ); smfulladder dfa373 (.DATA_A (INT_SUM[509]), .DATA_B (INT_CARRY[399]), .DATA_C (INT_CARRY[400]), .SAVE (INT_SUM[511]), .CARRY (INT_CARRY[414]) ); smfulladder dfa374 (.DATA_A (INT_SUM[510]), .DATA_B (INT_SUM[511]), .DATA_C (INT_CARRY[401]), .SAVE (INT_SUM[512]), .CARRY (INT_CARRY[415]) ); assign INT_SUM[513] = INT_CARRY[402]; smfulladder dfa375 (.DATA_A (INT_SUM[512]), .DATA_B (INT_SUM[513]), .DATA_C (INT_CARRY[403]), .SAVE (INT_SUM[514]), .CARRY (INT_CARRY[404]) ); smffb dla559 (.D(INT_SUM[514]), .clk(clk), .en_d2(en_d2), .Q(SUM[43]) ); smffb dla560 (.D(INT_CARRY[404]), .clk(clk), .en_d2(en_d2), .Q(CARRY[43]) ); smffa dla561 (.D(SUMMAND[474]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[474]) ); smffa dla562 (.D(SUMMAND[475]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[475]) ); smffa dla563 (.D(SUMMAND[476]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[476]) ); smfulladder dfa376 (.DATA_A (LATCHED_PP[474]), .DATA_B (LATCHED_PP[475]), .DATA_C (LATCHED_PP[476]), .SAVE (INT_SUM[515]), .CARRY (INT_CARRY[417]) ); smffa dla564 (.D(SUMMAND[477]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[477]) ); smffa dla565 (.D(SUMMAND[478]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[478]) ); smffa dla566 (.D(SUMMAND[479]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[479]) ); smfulladder dfa377 (.DATA_A (LATCHED_PP[477]), .DATA_B (LATCHED_PP[478]), .DATA_C (LATCHED_PP[479]), .SAVE (INT_SUM[516]), .CARRY (INT_CARRY[418]) ); smffa dla567 (.D(SUMMAND[480]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[480]) ); smffa dla568 (.D(SUMMAND[481]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[481]) ); smffa dla569 (.D(SUMMAND[482]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[482]) ); smfulladder dfa378 (.DATA_A (LATCHED_PP[480]), .DATA_B (LATCHED_PP[481]), .DATA_C (LATCHED_PP[482]), .SAVE (INT_SUM[517]), .CARRY (INT_CARRY[419]) ); smffa dla570 (.D(SUMMAND[483]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[483]) ); smffa dla571 (.D(SUMMAND[484]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[484]) ); smffa dla572 (.D(SUMMAND[485]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[485]) ); smfulladder dfa379 (.DATA_A (LATCHED_PP[483]), .DATA_B (LATCHED_PP[484]), .DATA_C (LATCHED_PP[485]), .SAVE (INT_SUM[518]), .CARRY (INT_CARRY[420]) ); smfulladder dfa380 (.DATA_A (INT_SUM[515]), .DATA_B (INT_SUM[516]), .DATA_C (INT_SUM[517]), .SAVE (INT_SUM[519]), .CARRY (INT_CARRY[421]) ); smfulladder dfa381 (.DATA_A (INT_SUM[518]), .DATA_B (INT_CARRY[405]), .DATA_C (INT_CARRY[406]), .SAVE (INT_SUM[520]), .CARRY (INT_CARRY[422]) ); smfulladder dfa382 (.DATA_A (INT_CARRY[407]), .DATA_B (INT_CARRY[408]), .DATA_C (INT_CARRY[409]), .SAVE (INT_SUM[521]), .CARRY (INT_CARRY[423]) ); smfulladder dfa383 (.DATA_A (INT_SUM[519]), .DATA_B (INT_SUM[520]), .DATA_C (INT_SUM[521]), .SAVE (INT_SUM[522]), .CARRY (INT_CARRY[424]) ); smfulladder dfa384 (.DATA_A (INT_CARRY[410]), .DATA_B (INT_CARRY[411]), .DATA_C (INT_CARRY[412]), .SAVE (INT_SUM[523]), .CARRY (INT_CARRY[425]) ); smfulladder dfa385 (.DATA_A (INT_SUM[522]), .DATA_B (INT_SUM[523]), .DATA_C (INT_CARRY[413]), .SAVE (INT_SUM[524]), .CARRY (INT_CARRY[426]) ); assign INT_SUM[525] = INT_CARRY[414]; smfulladder dfa386 (.DATA_A (INT_SUM[524]), .DATA_B (INT_SUM[525]), .DATA_C (INT_CARRY[415]), .SAVE (INT_SUM[526]), .CARRY (INT_CARRY[416]) ); smffb dla573 (.D(INT_SUM[526]), .clk(clk), .en_d2(en_d2), .Q(SUM[44]) ); smffb dla574 (.D(INT_CARRY[416]), .clk(clk), .en_d2(en_d2), .Q(CARRY[44]) ); smffa dla575 (.D(SUMMAND[486]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[486]) ); smffa dla576 (.D(SUMMAND[487]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[487]) ); smffa dla577 (.D(SUMMAND[488]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[488]) ); smfulladder dfa387 (.DATA_A (LATCHED_PP[486]), .DATA_B (LATCHED_PP[487]), .DATA_C (LATCHED_PP[488]), .SAVE (INT_SUM[527]), .CARRY (INT_CARRY[428]) ); smffa dla578 (.D(SUMMAND[489]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[489]) ); smffa dla579 (.D(SUMMAND[490]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[490]) ); smffa dla580 (.D(SUMMAND[491]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[491]) ); smfulladder dfa388 (.DATA_A (LATCHED_PP[489]), .DATA_B (LATCHED_PP[490]), .DATA_C (LATCHED_PP[491]), .SAVE (INT_SUM[528]), .CARRY (INT_CARRY[429]) ); smffa dla581 (.D(SUMMAND[492]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[492]) ); smffa dla582 (.D(SUMMAND[493]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[493]) ); smffa dla583 (.D(SUMMAND[494]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[494]) ); smfulladder dfa389 (.DATA_A (LATCHED_PP[492]), .DATA_B (LATCHED_PP[493]), .DATA_C (LATCHED_PP[494]), .SAVE (INT_SUM[529]), .CARRY (INT_CARRY[430]) ); smffa dla584 (.D(SUMMAND[495]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[495]) ); smffa dla585 (.D(SUMMAND[496]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[496]) ); smffa dla586 (.D(SUMMAND[497]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[497]) ); smfulladder dfa390 (.DATA_A (LATCHED_PP[495]), .DATA_B (LATCHED_PP[496]), .DATA_C (LATCHED_PP[497]), .SAVE (INT_SUM[530]), .CARRY (INT_CARRY[431]) ); smfulladder dfa391 (.DATA_A (INT_SUM[527]), .DATA_B (INT_SUM[528]), .DATA_C (INT_SUM[529]), .SAVE (INT_SUM[531]), .CARRY (INT_CARRY[432]) ); smfulladder dfa392 (.DATA_A (INT_SUM[530]), .DATA_B (INT_CARRY[417]), .DATA_C (INT_CARRY[418]), .SAVE (INT_SUM[532]), .CARRY (INT_CARRY[433]) ); smhalfadder dha40 (.DATA_A (INT_CARRY[419]), .DATA_B (INT_CARRY[420]), .SAVE (INT_SUM[533]), .CARRY (INT_CARRY[434]) ); smfulladder dfa393 (.DATA_A (INT_SUM[531]), .DATA_B (INT_SUM[532]), .DATA_C (INT_SUM[533]), .SAVE (INT_SUM[534]), .CARRY (INT_CARRY[435]) ); smfulladder dfa394 (.DATA_A (INT_CARRY[421]), .DATA_B (INT_CARRY[422]), .DATA_C (INT_CARRY[423]), .SAVE (INT_SUM[535]), .CARRY (INT_CARRY[436]) ); smfulladder dfa395 (.DATA_A (INT_SUM[534]), .DATA_B (INT_SUM[535]), .DATA_C (INT_CARRY[424]), .SAVE (INT_SUM[536]), .CARRY (INT_CARRY[437]) ); assign INT_SUM[537] = INT_CARRY[425]; smfulladder dfa396 (.DATA_A (INT_SUM[536]), .DATA_B (INT_SUM[537]), .DATA_C (INT_CARRY[426]), .SAVE (INT_SUM[538]), .CARRY (INT_CARRY[427]) ); smffb dla587 (.D(INT_SUM[538]), .clk(clk), .en_d2(en_d2), .Q(SUM[45]) ); smffb dla588 (.D(INT_CARRY[427]), .clk(clk), .en_d2(en_d2), .Q(CARRY[45]) ); smffa dla589 (.D(SUMMAND[498]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[498]) ); smffa dla590 (.D(SUMMAND[499]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[499]) ); smffa dla591 (.D(SUMMAND[500]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[500]) ); smfulladder dfa397 (.DATA_A (LATCHED_PP[498]), .DATA_B (LATCHED_PP[499]), .DATA_C (LATCHED_PP[500]), .SAVE (INT_SUM[539]), .CARRY (INT_CARRY[439]) ); smffa dla592 (.D(SUMMAND[501]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[501]) ); smffa dla593 (.D(SUMMAND[502]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[502]) ); smffa dla594 (.D(SUMMAND[503]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[503]) ); smfulladder dfa398 (.DATA_A (LATCHED_PP[501]), .DATA_B (LATCHED_PP[502]), .DATA_C (LATCHED_PP[503]), .SAVE (INT_SUM[540]), .CARRY (INT_CARRY[440]) ); smffa dla595 (.D(SUMMAND[504]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[504]) ); smffa dla596 (.D(SUMMAND[505]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[505]) ); smffa dla597 (.D(SUMMAND[506]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[506]) ); smfulladder dfa399 (.DATA_A (LATCHED_PP[504]), .DATA_B (LATCHED_PP[505]), .DATA_C (LATCHED_PP[506]), .SAVE (INT_SUM[541]), .CARRY (INT_CARRY[441]) ); smffa dla598 (.D(SUMMAND[507]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[507]) ); assign INT_SUM[542] = LATCHED_PP[507]; smffa dla599 (.D(SUMMAND[508]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[508]) ); assign INT_SUM[543] = LATCHED_PP[508]; smfulladder dfa400 (.DATA_A (INT_SUM[539]), .DATA_B (INT_SUM[540]), .DATA_C (INT_SUM[541]), .SAVE (INT_SUM[544]), .CARRY (INT_CARRY[442]) ); smfulladder dfa401 (.DATA_A (INT_SUM[542]), .DATA_B (INT_SUM[543]), .DATA_C (INT_CARRY[428]), .SAVE (INT_SUM[545]), .CARRY (INT_CARRY[443]) ); smfulladder dfa402 (.DATA_A (INT_CARRY[429]), .DATA_B (INT_CARRY[430]), .DATA_C (INT_CARRY[431]), .SAVE (INT_SUM[546]), .CARRY (INT_CARRY[444]) ); smfulladder dfa403 (.DATA_A (INT_SUM[544]), .DATA_B (INT_SUM[545]), .DATA_C (INT_SUM[546]), .SAVE (INT_SUM[547]), .CARRY (INT_CARRY[445]) ); smfulladder dfa404 (.DATA_A (INT_CARRY[432]), .DATA_B (INT_CARRY[433]), .DATA_C (INT_CARRY[434]), .SAVE (INT_SUM[548]), .CARRY (INT_CARRY[446]) ); smfulladder dfa405 (.DATA_A (INT_SUM[547]), .DATA_B (INT_SUM[548]), .DATA_C (INT_CARRY[435]), .SAVE (INT_SUM[549]), .CARRY (INT_CARRY[447]) ); assign INT_SUM[550] = INT_CARRY[436]; smfulladder dfa406 (.DATA_A (INT_SUM[549]), .DATA_B (INT_SUM[550]), .DATA_C (INT_CARRY[437]), .SAVE (INT_SUM[551]), .CARRY (INT_CARRY[438]) ); smffb dla600 (.D(INT_SUM[551]), .clk(clk), .en_d2(en_d2), .Q(SUM[46]) ); smffb dla601 (.D(INT_CARRY[438]), .clk(clk), .en_d2(en_d2), .Q(CARRY[46]) ); smffa dla602 (.D(SUMMAND[509]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[509]) ); smffa dla603 (.D(SUMMAND[510]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[510]) ); smffa dla604 (.D(SUMMAND[511]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[511]) ); smfulladder dfa407 (.DATA_A (LATCHED_PP[509]), .DATA_B (LATCHED_PP[510]), .DATA_C (LATCHED_PP[511]), .SAVE (INT_SUM[552]), .CARRY (INT_CARRY[449]) ); smffa dla605 (.D(SUMMAND[512]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[512]) ); smffa dla606 (.D(SUMMAND[513]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[513]) ); smffa dla607 (.D(SUMMAND[514]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[514]) ); smfulladder dfa408 (.DATA_A (LATCHED_PP[512]), .DATA_B (LATCHED_PP[513]), .DATA_C (LATCHED_PP[514]), .SAVE (INT_SUM[553]), .CARRY (INT_CARRY[450]) ); smffa dla608 (.D(SUMMAND[515]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[515]) ); smffa dla609 (.D(SUMMAND[516]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[516]) ); smffa dla610 (.D(SUMMAND[517]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[517]) ); smfulladder dfa409 (.DATA_A (LATCHED_PP[515]), .DATA_B (LATCHED_PP[516]), .DATA_C (LATCHED_PP[517]), .SAVE (INT_SUM[554]), .CARRY (INT_CARRY[451]) ); smffa dla611 (.D(SUMMAND[518]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[518]) ); smffa dla612 (.D(SUMMAND[519]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[519]) ); smhalfadder dha41 (.DATA_A (LATCHED_PP[518]), .DATA_B (LATCHED_PP[519]), .SAVE (INT_SUM[555]), .CARRY (INT_CARRY[452]) ); smfulladder dfa410 (.DATA_A (INT_SUM[552]), .DATA_B (INT_SUM[553]), .DATA_C (INT_SUM[554]), .SAVE (INT_SUM[556]), .CARRY (INT_CARRY[453]) ); smfulladder dfa411 (.DATA_A (INT_SUM[555]), .DATA_B (INT_CARRY[439]), .DATA_C (INT_CARRY[440]), .SAVE (INT_SUM[557]), .CARRY (INT_CARRY[454]) ); assign INT_SUM[558] = INT_CARRY[441]; smfulladder dfa412 (.DATA_A (INT_SUM[556]), .DATA_B (INT_SUM[557]), .DATA_C (INT_SUM[558]), .SAVE (INT_SUM[559]), .CARRY (INT_CARRY[455]) ); smfulladder dfa413 (.DATA_A (INT_CARRY[442]), .DATA_B (INT_CARRY[443]), .DATA_C (INT_CARRY[444]), .SAVE (INT_SUM[560]), .CARRY (INT_CARRY[456]) ); smfulladder dfa414 (.DATA_A (INT_SUM[559]), .DATA_B (INT_SUM[560]), .DATA_C (INT_CARRY[445]), .SAVE (INT_SUM[561]), .CARRY (INT_CARRY[457]) ); assign INT_SUM[562] = INT_CARRY[446]; smfulladder dfa415 (.DATA_A (INT_SUM[561]), .DATA_B (INT_SUM[562]), .DATA_C (INT_CARRY[447]), .SAVE (INT_SUM[563]), .CARRY (INT_CARRY[448]) ); smffb dla613 (.D(INT_SUM[563]), .clk(clk), .en_d2(en_d2), .Q(SUM[47]) ); smffb dla614 (.D(INT_CARRY[448]), .clk(clk), .en_d2(en_d2), .Q(CARRY[47]) ); smffa dla615 (.D(SUMMAND[520]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[520]) ); smffa dla616 (.D(SUMMAND[521]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[521]) ); smffa dla617 (.D(SUMMAND[522]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[522]) ); smfulladder dfa416 (.DATA_A (LATCHED_PP[520]), .DATA_B (LATCHED_PP[521]), .DATA_C (LATCHED_PP[522]), .SAVE (INT_SUM[564]), .CARRY (INT_CARRY[459]) ); smffa dla618 (.D(SUMMAND[523]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[523]) ); smffa dla619 (.D(SUMMAND[524]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[524]) ); smffa dla620 (.D(SUMMAND[525]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[525]) ); smfulladder dfa417 (.DATA_A (LATCHED_PP[523]), .DATA_B (LATCHED_PP[524]), .DATA_C (LATCHED_PP[525]), .SAVE (INT_SUM[565]), .CARRY (INT_CARRY[460]) ); smffa dla621 (.D(SUMMAND[526]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[526]) ); smffa dla622 (.D(SUMMAND[527]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[527]) ); smffa dla623 (.D(SUMMAND[528]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[528]) ); smfulladder dfa418 (.DATA_A (LATCHED_PP[526]), .DATA_B (LATCHED_PP[527]), .DATA_C (LATCHED_PP[528]), .SAVE (INT_SUM[566]), .CARRY (INT_CARRY[461]) ); smffa dla624 (.D(SUMMAND[529]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[529]) ); assign INT_SUM[567] = LATCHED_PP[529]; smfulladder dfa419 (.DATA_A (INT_SUM[564]), .DATA_B (INT_SUM[565]), .DATA_C (INT_SUM[566]), .SAVE (INT_SUM[568]), .CARRY (INT_CARRY[462]) ); smfulladder dfa420 (.DATA_A (INT_SUM[567]), .DATA_B (INT_CARRY[449]), .DATA_C (INT_CARRY[450]), .SAVE (INT_SUM[569]), .CARRY (INT_CARRY[463]) ); assign INT_SUM[570] = INT_CARRY[451]; assign INT_SUM[571] = INT_CARRY[452]; smfulladder dfa421 (.DATA_A (INT_SUM[568]), .DATA_B (INT_SUM[569]), .DATA_C (INT_SUM[570]), .SAVE (INT_SUM[572]), .CARRY (INT_CARRY[464]) ); smfulladder dfa422 (.DATA_A (INT_SUM[571]), .DATA_B (INT_CARRY[453]), .DATA_C (INT_CARRY[454]), .SAVE (INT_SUM[573]), .CARRY (INT_CARRY[465]) ); smfulladder dfa423 (.DATA_A (INT_SUM[572]), .DATA_B (INT_SUM[573]), .DATA_C (INT_CARRY[455]), .SAVE (INT_SUM[574]), .CARRY (INT_CARRY[466]) ); assign INT_SUM[575] = INT_CARRY[456]; smfulladder dfa424 (.DATA_A (INT_SUM[574]), .DATA_B (INT_SUM[575]), .DATA_C (INT_CARRY[457]), .SAVE (INT_SUM[576]), .CARRY (INT_CARRY[458]) ); smffb dla625 (.D(INT_SUM[576]), .clk(clk), .en_d2(en_d2), .Q(SUM[48]) ); smffb dla626 (.D(INT_CARRY[458]), .clk(clk), .en_d2(en_d2), .Q(CARRY[48]) ); smffa dla627 (.D(SUMMAND[530]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[530]) ); smffa dla628 (.D(SUMMAND[531]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[531]) ); smffa dla629 (.D(SUMMAND[532]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[532]) ); smfulladder dfa425 (.DATA_A (LATCHED_PP[530]), .DATA_B (LATCHED_PP[531]), .DATA_C (LATCHED_PP[532]), .SAVE (INT_SUM[577]), .CARRY (INT_CARRY[468]) ); smffa dla630 (.D(SUMMAND[533]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[533]) ); smffa dla631 (.D(SUMMAND[534]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[534]) ); smffa dla632 (.D(SUMMAND[535]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[535]) ); smfulladder dfa426 (.DATA_A (LATCHED_PP[533]), .DATA_B (LATCHED_PP[534]), .DATA_C (LATCHED_PP[535]), .SAVE (INT_SUM[578]), .CARRY (INT_CARRY[469]) ); smffa dla633 (.D(SUMMAND[536]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[536]) ); smffa dla634 (.D(SUMMAND[537]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[537]) ); smffa dla635 (.D(SUMMAND[538]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[538]) ); smfulladder dfa427 (.DATA_A (LATCHED_PP[536]), .DATA_B (LATCHED_PP[537]), .DATA_C (LATCHED_PP[538]), .SAVE (INT_SUM[579]), .CARRY (INT_CARRY[470]) ); smffa dla636 (.D(SUMMAND[539]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[539]) ); assign INT_SUM[580] = LATCHED_PP[539]; smfulladder dfa428 (.DATA_A (INT_SUM[577]), .DATA_B (INT_SUM[578]), .DATA_C (INT_SUM[579]), .SAVE (INT_SUM[581]), .CARRY (INT_CARRY[471]) ); smfulladder dfa429 (.DATA_A (INT_SUM[580]), .DATA_B (INT_CARRY[459]), .DATA_C (INT_CARRY[460]), .SAVE (INT_SUM[582]), .CARRY (INT_CARRY[472]) ); assign INT_SUM[583] = INT_CARRY[461]; smfulladder dfa430 (.DATA_A (INT_SUM[581]), .DATA_B (INT_SUM[582]), .DATA_C (INT_SUM[583]), .SAVE (INT_SUM[584]), .CARRY (INT_CARRY[473]) ); smhalfadder dha42 (.DATA_A (INT_CARRY[462]), .DATA_B (INT_CARRY[463]), .SAVE (INT_SUM[585]), .CARRY (INT_CARRY[474]) ); smfulladder dfa431 (.DATA_A (INT_SUM[584]), .DATA_B (INT_SUM[585]), .DATA_C (INT_CARRY[464]), .SAVE (INT_SUM[586]), .CARRY (INT_CARRY[475]) ); assign INT_SUM[587] = INT_CARRY[465]; smfulladder dfa432 (.DATA_A (INT_SUM[586]), .DATA_B (INT_SUM[587]), .DATA_C (INT_CARRY[466]), .SAVE (INT_SUM[588]), .CARRY (INT_CARRY[467]) ); smffb dla637 (.D(INT_SUM[588]), .clk(clk), .en_d2(en_d2), .Q(SUM[49]) ); smffb dla638 (.D(INT_CARRY[467]), .clk(clk), .en_d2(en_d2), .Q(CARRY[49]) ); smffa dla639 (.D(SUMMAND[540]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[540]) ); smffa dla640 (.D(SUMMAND[541]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[541]) ); smffa dla641 (.D(SUMMAND[542]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[542]) ); smfulladder dfa433 (.DATA_A (LATCHED_PP[540]), .DATA_B (LATCHED_PP[541]), .DATA_C (LATCHED_PP[542]), .SAVE (INT_SUM[589]), .CARRY (INT_CARRY[477]) ); smffa dla642 (.D(SUMMAND[543]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[543]) ); smffa dla643 (.D(SUMMAND[544]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[544]) ); smffa dla644 (.D(SUMMAND[545]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[545]) ); smfulladder dfa434 (.DATA_A (LATCHED_PP[543]), .DATA_B (LATCHED_PP[544]), .DATA_C (LATCHED_PP[545]), .SAVE (INT_SUM[590]), .CARRY (INT_CARRY[478]) ); smffa dla645 (.D(SUMMAND[546]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[546]) ); smffa dla646 (.D(SUMMAND[547]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[547]) ); smffa dla647 (.D(SUMMAND[548]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[548]) ); smfulladder dfa435 (.DATA_A (LATCHED_PP[546]), .DATA_B (LATCHED_PP[547]), .DATA_C (LATCHED_PP[548]), .SAVE (INT_SUM[591]), .CARRY (INT_CARRY[479]) ); smfulladder dfa436 (.DATA_A (INT_SUM[589]), .DATA_B (INT_SUM[590]), .DATA_C (INT_SUM[591]), .SAVE (INT_SUM[592]), .CARRY (INT_CARRY[480]) ); smfulladder dfa437 (.DATA_A (INT_CARRY[468]), .DATA_B (INT_CARRY[469]), .DATA_C (INT_CARRY[470]), .SAVE (INT_SUM[593]), .CARRY (INT_CARRY[481]) ); smfulladder dfa438 (.DATA_A (INT_SUM[592]), .DATA_B (INT_SUM[593]), .DATA_C (INT_CARRY[471]), .SAVE (INT_SUM[594]), .CARRY (INT_CARRY[482]) ); assign INT_SUM[595] = INT_CARRY[472]; smfulladder dfa439 (.DATA_A (INT_SUM[594]), .DATA_B (INT_SUM[595]), .DATA_C (INT_CARRY[473]), .SAVE (INT_SUM[596]), .CARRY (INT_CARRY[483]) ); assign INT_SUM[597] = INT_CARRY[474]; smfulladder dfa440 (.DATA_A (INT_SUM[596]), .DATA_B (INT_SUM[597]), .DATA_C (INT_CARRY[475]), .SAVE (INT_SUM[598]), .CARRY (INT_CARRY[476]) ); smffb dla648 (.D(INT_SUM[598]), .clk(clk), .en_d2(en_d2), .Q(SUM[50]) ); smffb dla649 (.D(INT_CARRY[476]), .clk(clk), .en_d2(en_d2), .Q(CARRY[50]) ); smffa dla650 (.D(SUMMAND[549]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[549]) ); smffa dla651 (.D(SUMMAND[550]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[550]) ); smffa dla652 (.D(SUMMAND[551]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[551]) ); smfulladder dfa441 (.DATA_A (LATCHED_PP[549]), .DATA_B (LATCHED_PP[550]), .DATA_C (LATCHED_PP[551]), .SAVE (INT_SUM[599]), .CARRY (INT_CARRY[485]) ); smffa dla653 (.D(SUMMAND[552]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[552]) ); smffa dla654 (.D(SUMMAND[553]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[553]) ); smffa dla655 (.D(SUMMAND[554]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[554]) ); smfulladder dfa442 (.DATA_A (LATCHED_PP[552]), .DATA_B (LATCHED_PP[553]), .DATA_C (LATCHED_PP[554]), .SAVE (INT_SUM[600]), .CARRY (INT_CARRY[486]) ); smffa dla656 (.D(SUMMAND[555]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[555]) ); smffa dla657 (.D(SUMMAND[556]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[556]) ); smffa dla658 (.D(SUMMAND[557]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[557]) ); smfulladder dfa443 (.DATA_A (LATCHED_PP[555]), .DATA_B (LATCHED_PP[556]), .DATA_C (LATCHED_PP[557]), .SAVE (INT_SUM[601]), .CARRY (INT_CARRY[487]) ); smfulladder dfa444 (.DATA_A (INT_SUM[599]), .DATA_B (INT_SUM[600]), .DATA_C (INT_SUM[601]), .SAVE (INT_SUM[602]), .CARRY (INT_CARRY[488]) ); smfulladder dfa445 (.DATA_A (INT_CARRY[477]), .DATA_B (INT_CARRY[478]), .DATA_C (INT_CARRY[479]), .SAVE (INT_SUM[603]), .CARRY (INT_CARRY[489]) ); smfulladder dfa446 (.DATA_A (INT_SUM[602]), .DATA_B (INT_SUM[603]), .DATA_C (INT_CARRY[480]), .SAVE (INT_SUM[604]), .CARRY (INT_CARRY[490]) ); assign INT_SUM[605] = INT_CARRY[481]; smfulladder dfa447 (.DATA_A (INT_SUM[604]), .DATA_B (INT_SUM[605]), .DATA_C (INT_CARRY[482]), .SAVE (INT_SUM[606]), .CARRY (INT_CARRY[491]) ); smhalfadder dha43 (.DATA_A (INT_SUM[606]), .DATA_B (INT_CARRY[483]), .SAVE (INT_SUM[607]), .CARRY (INT_CARRY[484]) ); smffb dla659 (.D(INT_SUM[607]), .clk(clk), .en_d2(en_d2), .Q(SUM[51]) ); smffb dla660 (.D(INT_CARRY[484]), .clk(clk), .en_d2(en_d2), .Q(CARRY[51]) ); smffa dla661 (.D(SUMMAND[558]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[558]) ); smffa dla662 (.D(SUMMAND[559]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[559]) ); smffa dla663 (.D(SUMMAND[560]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[560]) ); smfulladder dfa448 (.DATA_A (LATCHED_PP[558]), .DATA_B (LATCHED_PP[559]), .DATA_C (LATCHED_PP[560]), .SAVE (INT_SUM[608]), .CARRY (INT_CARRY[493]) ); smffa dla664 (.D(SUMMAND[561]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[561]) ); smffa dla665 (.D(SUMMAND[562]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[562]) ); smffa dla666 (.D(SUMMAND[563]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[563]) ); smfulladder dfa449 (.DATA_A (LATCHED_PP[561]), .DATA_B (LATCHED_PP[562]), .DATA_C (LATCHED_PP[563]), .SAVE (INT_SUM[609]), .CARRY (INT_CARRY[494]) ); smffa dla667 (.D(SUMMAND[564]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[564]) ); smffa dla668 (.D(SUMMAND[565]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[565]) ); smfulladder dfa450 (.DATA_A (LATCHED_PP[564]), .DATA_B (LATCHED_PP[565]), .DATA_C (INT_CARRY[485]), .SAVE (INT_SUM[610]), .CARRY (INT_CARRY[495]) ); smhalfadder dha44 (.DATA_A (INT_CARRY[486]), .DATA_B (INT_CARRY[487]), .SAVE (INT_SUM[611]), .CARRY (INT_CARRY[496]) ); smfulladder dfa451 (.DATA_A (INT_SUM[608]), .DATA_B (INT_SUM[609]), .DATA_C (INT_SUM[610]), .SAVE (INT_SUM[612]), .CARRY (INT_CARRY[497]) ); smfulladder dfa452 (.DATA_A (INT_SUM[611]), .DATA_B (INT_CARRY[488]), .DATA_C (INT_CARRY[489]), .SAVE (INT_SUM[613]), .CARRY (INT_CARRY[498]) ); smfulladder dfa453 (.DATA_A (INT_SUM[612]), .DATA_B (INT_SUM[613]), .DATA_C (INT_CARRY[490]), .SAVE (INT_SUM[614]), .CARRY (INT_CARRY[499]) ); smhalfadder dha45 (.DATA_A (INT_SUM[614]), .DATA_B (INT_CARRY[491]), .SAVE (INT_SUM[615]), .CARRY (INT_CARRY[492]) ); smffb dla669 (.D(INT_SUM[615]), .clk(clk), .en_d2(en_d2), .Q(SUM[52]) ); smffb dla670 (.D(INT_CARRY[492]), .clk(clk), .en_d2(en_d2), .Q(CARRY[52]) ); smffa dla671 (.D(SUMMAND[566]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[566]) ); smffa dla672 (.D(SUMMAND[567]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[567]) ); smffa dla673 (.D(SUMMAND[568]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[568]) ); smfulladder dfa454 (.DATA_A (LATCHED_PP[566]), .DATA_B (LATCHED_PP[567]), .DATA_C (LATCHED_PP[568]), .SAVE (INT_SUM[616]), .CARRY (INT_CARRY[501]) ); smffa dla674 (.D(SUMMAND[569]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[569]) ); smffa dla675 (.D(SUMMAND[570]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[570]) ); smffa dla676 (.D(SUMMAND[571]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[571]) ); smfulladder dfa455 (.DATA_A (LATCHED_PP[569]), .DATA_B (LATCHED_PP[570]), .DATA_C (LATCHED_PP[571]), .SAVE (INT_SUM[617]), .CARRY (INT_CARRY[502]) ); smffa dla677 (.D(SUMMAND[572]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[572]) ); assign INT_SUM[618] = LATCHED_PP[572]; smffa dla678 (.D(SUMMAND[573]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[573]) ); assign INT_SUM[619] = LATCHED_PP[573]; smfulladder dfa456 (.DATA_A (INT_SUM[616]), .DATA_B (INT_SUM[617]), .DATA_C (INT_SUM[618]), .SAVE (INT_SUM[620]), .CARRY (INT_CARRY[503]) ); assign INT_SUM[621] = INT_SUM[619]; smfulladder dfa457 (.DATA_A (INT_SUM[620]), .DATA_B (INT_SUM[621]), .DATA_C (INT_CARRY[493]), .SAVE (INT_SUM[622]), .CARRY (INT_CARRY[504]) ); smfulladder dfa458 (.DATA_A (INT_CARRY[494]), .DATA_B (INT_CARRY[495]), .DATA_C (INT_CARRY[496]), .SAVE (INT_SUM[623]), .CARRY (INT_CARRY[505]) ); smfulladder dfa459 (.DATA_A (INT_SUM[622]), .DATA_B (INT_SUM[623]), .DATA_C (INT_CARRY[497]), .SAVE (INT_SUM[624]), .CARRY (INT_CARRY[506]) ); assign INT_SUM[625] = INT_CARRY[498]; smfulladder dfa460 (.DATA_A (INT_SUM[624]), .DATA_B (INT_SUM[625]), .DATA_C (INT_CARRY[499]), .SAVE (INT_SUM[626]), .CARRY (INT_CARRY[500]) ); smffb dla679 (.D(INT_SUM[626]), .clk(clk), .en_d2(en_d2), .Q(SUM[53]) ); smffb dla680 (.D(INT_CARRY[500]), .clk(clk), .en_d2(en_d2), .Q(CARRY[53]) ); smffa dla681 (.D(SUMMAND[574]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[574]) ); smffa dla682 (.D(SUMMAND[575]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[575]) ); smffa dla683 (.D(SUMMAND[576]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[576]) ); smfulladder dfa461 (.DATA_A (LATCHED_PP[574]), .DATA_B (LATCHED_PP[575]), .DATA_C (LATCHED_PP[576]), .SAVE (INT_SUM[627]), .CARRY (INT_CARRY[508]) ); smffa dla684 (.D(SUMMAND[577]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[577]) ); smffa dla685 (.D(SUMMAND[578]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[578]) ); smffa dla686 (.D(SUMMAND[579]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[579]) ); smfulladder dfa462 (.DATA_A (LATCHED_PP[577]), .DATA_B (LATCHED_PP[578]), .DATA_C (LATCHED_PP[579]), .SAVE (INT_SUM[628]), .CARRY (INT_CARRY[509]) ); smffa dla687 (.D(SUMMAND[580]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[580]) ); smfulladder dfa463 (.DATA_A (LATCHED_PP[580]), .DATA_B (INT_CARRY[501]), .DATA_C (INT_CARRY[502]), .SAVE (INT_SUM[629]), .CARRY (INT_CARRY[510]) ); smfulladder dfa464 (.DATA_A (INT_SUM[627]), .DATA_B (INT_SUM[628]), .DATA_C (INT_SUM[629]), .SAVE (INT_SUM[630]), .CARRY (INT_CARRY[511]) ); assign INT_SUM[631] = INT_CARRY[503]; smfulladder dfa465 (.DATA_A (INT_SUM[630]), .DATA_B (INT_SUM[631]), .DATA_C (INT_CARRY[504]), .SAVE (INT_SUM[632]), .CARRY (INT_CARRY[512]) ); assign INT_SUM[633] = INT_CARRY[505]; smfulladder dfa466 (.DATA_A (INT_SUM[632]), .DATA_B (INT_SUM[633]), .DATA_C (INT_CARRY[506]), .SAVE (INT_SUM[634]), .CARRY (INT_CARRY[507]) ); smffb dla688 (.D(INT_SUM[634]), .clk(clk), .en_d2(en_d2), .Q(SUM[54]) ); smffb dla689 (.D(INT_CARRY[507]), .clk(clk), .en_d2(en_d2), .Q(CARRY[54]) ); smffa dla690 (.D(SUMMAND[581]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[581]) ); smffa dla691 (.D(SUMMAND[582]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[582]) ); smffa dla692 (.D(SUMMAND[583]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[583]) ); smfulladder dfa467 (.DATA_A (LATCHED_PP[581]), .DATA_B (LATCHED_PP[582]), .DATA_C (LATCHED_PP[583]), .SAVE (INT_SUM[635]), .CARRY (INT_CARRY[514]) ); smffa dla693 (.D(SUMMAND[584]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[584]) ); smffa dla694 (.D(SUMMAND[585]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[585]) ); smffa dla695 (.D(SUMMAND[586]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[586]) ); smfulladder dfa468 (.DATA_A (LATCHED_PP[584]), .DATA_B (LATCHED_PP[585]), .DATA_C (LATCHED_PP[586]), .SAVE (INT_SUM[636]), .CARRY (INT_CARRY[515]) ); smffa dla696 (.D(SUMMAND[587]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[587]) ); assign INT_SUM[637] = LATCHED_PP[587]; smfulladder dfa469 (.DATA_A (INT_SUM[635]), .DATA_B (INT_SUM[636]), .DATA_C (INT_SUM[637]), .SAVE (INT_SUM[638]), .CARRY (INT_CARRY[516]) ); smfulladder dfa470 (.DATA_A (INT_CARRY[508]), .DATA_B (INT_CARRY[509]), .DATA_C (INT_CARRY[510]), .SAVE (INT_SUM[639]), .CARRY (INT_CARRY[517]) ); smfulladder dfa471 (.DATA_A (INT_SUM[638]), .DATA_B (INT_SUM[639]), .DATA_C (INT_CARRY[511]), .SAVE (INT_SUM[640]), .CARRY (INT_CARRY[518]) ); smhalfadder dha46 (.DATA_A (INT_SUM[640]), .DATA_B (INT_CARRY[512]), .SAVE (INT_SUM[641]), .CARRY (INT_CARRY[513]) ); smffb dla697 (.D(INT_SUM[641]), .clk(clk), .en_d2(en_d2), .Q(SUM[55]) ); smffb dla698 (.D(INT_CARRY[513]), .clk(clk), .en_d2(en_d2), .Q(CARRY[55]) ); smffa dla699 (.D(SUMMAND[588]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[588]) ); smffa dla700 (.D(SUMMAND[589]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[589]) ); smffa dla701 (.D(SUMMAND[590]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[590]) ); smfulladder dfa472 (.DATA_A (LATCHED_PP[588]), .DATA_B (LATCHED_PP[589]), .DATA_C (LATCHED_PP[590]), .SAVE (INT_SUM[642]), .CARRY (INT_CARRY[520]) ); smffa dla702 (.D(SUMMAND[591]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[591]) ); smffa dla703 (.D(SUMMAND[592]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[592]) ); smffa dla704 (.D(SUMMAND[593]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[593]) ); smfulladder dfa473 (.DATA_A (LATCHED_PP[591]), .DATA_B (LATCHED_PP[592]), .DATA_C (LATCHED_PP[593]), .SAVE (INT_SUM[643]), .CARRY (INT_CARRY[521]) ); smfulladder dfa474 (.DATA_A (INT_SUM[642]), .DATA_B (INT_SUM[643]), .DATA_C (INT_CARRY[514]), .SAVE (INT_SUM[644]), .CARRY (INT_CARRY[522]) ); assign INT_SUM[645] = INT_CARRY[515]; smfulladder dfa475 (.DATA_A (INT_SUM[644]), .DATA_B (INT_SUM[645]), .DATA_C (INT_CARRY[516]), .SAVE (INT_SUM[646]), .CARRY (INT_CARRY[523]) ); assign INT_SUM[647] = INT_CARRY[517]; smfulladder dfa476 (.DATA_A (INT_SUM[646]), .DATA_B (INT_SUM[647]), .DATA_C (INT_CARRY[518]), .SAVE (INT_SUM[648]), .CARRY (INT_CARRY[519]) ); smffb dla705 (.D(INT_SUM[648]), .clk(clk), .en_d2(en_d2), .Q(SUM[56]) ); smffb dla706 (.D(INT_CARRY[519]), .clk(clk), .en_d2(en_d2), .Q(CARRY[56]) ); smffa dla707 (.D(SUMMAND[594]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[594]) ); smffa dla708 (.D(SUMMAND[595]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[595]) ); smffa dla709 (.D(SUMMAND[596]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[596]) ); smfulladder dfa477 (.DATA_A (LATCHED_PP[594]), .DATA_B (LATCHED_PP[595]), .DATA_C (LATCHED_PP[596]), .SAVE (INT_SUM[649]), .CARRY (INT_CARRY[525]) ); smffa dla710 (.D(SUMMAND[597]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[597]) ); smffa dla711 (.D(SUMMAND[598]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[598]) ); smffa dla712 (.D(SUMMAND[599]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[599]) ); smfulladder dfa478 (.DATA_A (LATCHED_PP[597]), .DATA_B (LATCHED_PP[598]), .DATA_C (LATCHED_PP[599]), .SAVE (INT_SUM[650]), .CARRY (INT_CARRY[526]) ); smfulladder dfa479 (.DATA_A (INT_SUM[649]), .DATA_B (INT_SUM[650]), .DATA_C (INT_CARRY[520]), .SAVE (INT_SUM[651]), .CARRY (INT_CARRY[527]) ); assign INT_SUM[652] = INT_CARRY[521]; smfulladder dfa480 (.DATA_A (INT_SUM[651]), .DATA_B (INT_SUM[652]), .DATA_C (INT_CARRY[522]), .SAVE (INT_SUM[653]), .CARRY (INT_CARRY[528]) ); smhalfadder dha47 (.DATA_A (INT_SUM[653]), .DATA_B (INT_CARRY[523]), .SAVE (INT_SUM[654]), .CARRY (INT_CARRY[524]) ); smffb dla713 (.D(INT_SUM[654]), .clk(clk), .en_d2(en_d2), .Q(SUM[57]) ); smffb dla714 (.D(INT_CARRY[524]), .clk(clk), .en_d2(en_d2), .Q(CARRY[57]) ); smffa dla715 (.D(SUMMAND[600]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[600]) ); smffa dla716 (.D(SUMMAND[601]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[601]) ); smffa dla717 (.D(SUMMAND[602]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[602]) ); smfulladder dfa481 (.DATA_A (LATCHED_PP[600]), .DATA_B (LATCHED_PP[601]), .DATA_C (LATCHED_PP[602]), .SAVE (INT_SUM[655]), .CARRY (INT_CARRY[530]) ); smffa dla718 (.D(SUMMAND[603]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[603]) ); smffa dla719 (.D(SUMMAND[604]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[604]) ); smhalfadder dha48 (.DATA_A (LATCHED_PP[603]), .DATA_B (LATCHED_PP[604]), .SAVE (INT_SUM[656]), .CARRY (INT_CARRY[531]) ); smfulladder dfa482 (.DATA_A (INT_SUM[655]), .DATA_B (INT_SUM[656]), .DATA_C (INT_CARRY[525]), .SAVE (INT_SUM[657]), .CARRY (INT_CARRY[532]) ); assign INT_SUM[658] = INT_CARRY[526]; smfulladder dfa483 (.DATA_A (INT_SUM[657]), .DATA_B (INT_SUM[658]), .DATA_C (INT_CARRY[527]), .SAVE (INT_SUM[659]), .CARRY (INT_CARRY[533]) ); smhalfadder dha49 (.DATA_A (INT_SUM[659]), .DATA_B (INT_CARRY[528]), .SAVE (INT_SUM[660]), .CARRY (INT_CARRY[529]) ); smffb dla720 (.D(INT_SUM[660]), .clk(clk), .en_d2(en_d2), .Q(SUM[58]) ); smffb dla721 (.D(INT_CARRY[529]), .clk(clk), .en_d2(en_d2), .Q(CARRY[58]) ); smffa dla722 (.D(SUMMAND[605]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[605]) ); smffa dla723 (.D(SUMMAND[606]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[606]) ); smffa dla724 (.D(SUMMAND[607]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[607]) ); smfulladder dfa484 (.DATA_A (LATCHED_PP[605]), .DATA_B (LATCHED_PP[606]), .DATA_C (LATCHED_PP[607]), .SAVE (INT_SUM[661]), .CARRY (INT_CARRY[535]) ); smffa dla725 (.D(SUMMAND[608]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[608]) ); smffa dla726 (.D(SUMMAND[609]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[609]) ); smhalfadder dha50 (.DATA_A (LATCHED_PP[608]), .DATA_B (LATCHED_PP[609]), .SAVE (INT_SUM[662]), .CARRY (INT_CARRY[536]) ); smfulladder dfa485 (.DATA_A (INT_SUM[661]), .DATA_B (INT_SUM[662]), .DATA_C (INT_CARRY[530]), .SAVE (INT_SUM[663]), .CARRY (INT_CARRY[537]) ); assign INT_SUM[664] = INT_CARRY[531]; smfulladder dfa486 (.DATA_A (INT_SUM[663]), .DATA_B (INT_SUM[664]), .DATA_C (INT_CARRY[532]), .SAVE (INT_SUM[665]), .CARRY (INT_CARRY[538]) ); smhalfadder dha51 (.DATA_A (INT_SUM[665]), .DATA_B (INT_CARRY[533]), .SAVE (INT_SUM[666]), .CARRY (INT_CARRY[534]) ); smffb dla727 (.D(INT_SUM[666]), .clk(clk), .en_d2(en_d2), .Q(SUM[59]) ); smffb dla728 (.D(INT_CARRY[534]), .clk(clk), .en_d2(en_d2), .Q(CARRY[59]) ); smffa dla729 (.D(SUMMAND[610]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[610]) ); smffa dla730 (.D(SUMMAND[611]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[611]) ); smffa dla731 (.D(SUMMAND[612]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[612]) ); smfulladder dfa487 (.DATA_A (LATCHED_PP[610]), .DATA_B (LATCHED_PP[611]), .DATA_C (LATCHED_PP[612]), .SAVE (INT_SUM[667]), .CARRY (INT_CARRY[540]) ); smffa dla732 (.D(SUMMAND[613]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[613]) ); smfulladder dfa488 (.DATA_A (LATCHED_PP[613]), .DATA_B (INT_CARRY[535]), .DATA_C (INT_CARRY[536]), .SAVE (INT_SUM[668]), .CARRY (INT_CARRY[541]) ); smfulladder dfa489 (.DATA_A (INT_SUM[667]), .DATA_B (INT_SUM[668]), .DATA_C (INT_CARRY[537]), .SAVE (INT_SUM[669]), .CARRY (INT_CARRY[542]) ); smhalfadder dha52 (.DATA_A (INT_SUM[669]), .DATA_B (INT_CARRY[538]), .SAVE (INT_SUM[670]), .CARRY (INT_CARRY[539]) ); smffb dla733 (.D(INT_SUM[670]), .clk(clk), .en_d2(en_d2), .Q(SUM[60]) ); smffb dla734 (.D(INT_CARRY[539]), .clk(clk), .en_d2(en_d2), .Q(CARRY[60]) ); smffa dla735 (.D(SUMMAND[614]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[614]) ); smffa dla736 (.D(SUMMAND[615]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[615]) ); smffa dla737 (.D(SUMMAND[616]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[616]) ); smfulladder dfa490 (.DATA_A (LATCHED_PP[614]), .DATA_B (LATCHED_PP[615]), .DATA_C (LATCHED_PP[616]), .SAVE (INT_SUM[671]), .CARRY (INT_CARRY[544]) ); smffa dla738 (.D(SUMMAND[617]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[617]) ); assign INT_SUM[672] = LATCHED_PP[617]; smfulladder dfa491 (.DATA_A (INT_SUM[671]), .DATA_B (INT_SUM[672]), .DATA_C (INT_CARRY[540]), .SAVE (INT_SUM[673]), .CARRY (INT_CARRY[545]) ); assign INT_SUM[674] = INT_CARRY[541]; smfulladder dfa492 (.DATA_A (INT_SUM[673]), .DATA_B (INT_SUM[674]), .DATA_C (INT_CARRY[542]), .SAVE (INT_SUM[675]), .CARRY (INT_CARRY[543]) ); smffb dla739 (.D(INT_SUM[675]), .clk(clk), .en_d2(en_d2), .Q(SUM[61]) ); smffb dla740 (.D(INT_CARRY[543]), .clk(clk), .en_d2(en_d2), .Q(CARRY[61]) ); smffa dla741 (.D(SUMMAND[618]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[618]) ); smffa dla742 (.D(SUMMAND[619]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[619]) ); smffa dla743 (.D(SUMMAND[620]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[620]) ); smfulladder dfa493 (.DATA_A (LATCHED_PP[618]), .DATA_B (LATCHED_PP[619]), .DATA_C (LATCHED_PP[620]), .SAVE (INT_SUM[676]), .CARRY (INT_CARRY[547]) ); assign INT_SUM[677] = INT_SUM[676]; assign INT_SUM[678] = INT_CARRY[544]; smfulladder dfa494 (.DATA_A (INT_SUM[677]), .DATA_B (INT_SUM[678]), .DATA_C (INT_CARRY[545]), .SAVE (INT_SUM[679]), .CARRY (INT_CARRY[546]) ); smffb dla744 (.D(INT_SUM[679]), .clk(clk), .en_d2(en_d2), .Q(SUM[62]) ); smffb dla745 (.D(INT_CARRY[546]), .clk(clk), .en_d2(en_d2), .Q(CARRY[62]) ); smffa dla746 (.D(SUMMAND[621]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[621]) ); smffa dla747 (.D(SUMMAND[622]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[622]) ); smffa dla748 (.D(SUMMAND[623]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[623]) ); smfulladder dfa495 (.DATA_A (LATCHED_PP[621]), .DATA_B (LATCHED_PP[622]), .DATA_C (LATCHED_PP[623]), .SAVE (INT_SUM[680]), .CARRY (INT_CARRY[549]) ); assign INT_SUM[681] = INT_CARRY[547]; smhalfadder dha53 (.DATA_A (INT_SUM[680]), .DATA_B (INT_SUM[681]), .SAVE (INT_SUM[682]), .CARRY (INT_CARRY[548]) ); smffb dla749 (.D(INT_SUM[682]), .clk(clk), .en_d2(en_d2), .Q(SUM[63]) ); smffb dla750 (.D(INT_CARRY[548]), .clk(clk), .en_d2(en_d2), .Q(CARRY[63]) ); smffa dla751 (.D(SUMMAND[624]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[624]) ); assign INT_SUM[683] = LATCHED_PP[624]; smffa dla752 (.D(SUMMAND[625]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[625]) ); assign INT_SUM[684] = LATCHED_PP[625]; smfulladder dfa496 (.DATA_A (INT_SUM[683]), .DATA_B (INT_SUM[684]), .DATA_C (INT_CARRY[549]), .SAVE (INT_SUM[685]), .CARRY (INT_CARRY[550]) ); smffb dla753 (.D(INT_SUM[685]), .clk(clk), .en_d2(en_d2), .Q(SUM[64]) ); smffb dla754 (.D(INT_CARRY[550]), .clk(clk), .en_d2(en_d2), .Q(CARRY[64]) ); smffa dla755 (.D(SUMMAND[626]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[626]) ); smffa dla756 (.D(SUMMAND[627]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[627]) ); smhalfadder dha54 (.DATA_A (LATCHED_PP[626]), .DATA_B (LATCHED_PP[627]), .SAVE (INT_SUM[686]), .CARRY (INT_CARRY[551]) ); smffb dla757 (.D(INT_SUM[686]), .clk(clk), .en_d2(en_d2), .Q(SUM[65]) ); smffb dla758 (.D(INT_CARRY[551]), .clk(clk), .en_d2(en_d2), .Q(CARRY[65]) ); smffa dla759 (.D(SUMMAND[628]), .clk(clk), .en_d1(en_d1), .Q(LATCHED_PP[628]) ); assign INT_SUM[687] = LATCHED_PP[628]; smffb dla760 (.D(INT_SUM[687]), .clk(clk), .en_d2(en_d2), .Q(SUM[66]) ); endmodule module smprestage_128 (A, B, CIN, POUT, GOUT); input [63:0] A; input [63:0] B; input CIN; output [63:0] POUT; output [63:0] GOUT; smblock0 d10 (A[0], B[0], POUT[0], GOUT[1] ); smblock0 d11 (A[1], B[1], POUT[1], GOUT[2] ); smblock0 d12 (A[2], B[2], POUT[2], GOUT[3] ); smblock0 d13 (A[3], B[3], POUT[3], GOUT[4] ); smblock0 d14 (A[4], B[4], POUT[4], GOUT[5] ); smblock0 d15 (A[5], B[5], POUT[5], GOUT[6] ); smblock0 d16 (A[6], B[6], POUT[6], GOUT[7] ); smblock0 d17 (A[7], B[7], POUT[7], GOUT[8] ); smblock0 d18 (A[8], B[8], POUT[8], GOUT[9] ); smblock0 d19 (A[9], B[9], POUT[9], GOUT[10] ); smblock0 d110 (A[10], B[10], POUT[10], GOUT[11] ); smblock0 d111 (A[11], B[11], POUT[11], GOUT[12] ); smblock0 d112 (A[12], B[12], POUT[12], GOUT[13] ); smblock0 d113 (A[13], B[13], POUT[13], GOUT[14] ); smblock0 d114 (A[14], B[14], POUT[14], GOUT[15] ); smblock0 d115 (A[15], B[15], POUT[15], GOUT[16] ); smblock0 d116 (A[16], B[16], POUT[16], GOUT[17] ); smblock0 d117 (A[17], B[17], POUT[17], GOUT[18] ); smblock0 d118 (A[18], B[18], POUT[18], GOUT[19] ); smblock0 d119 (A[19], B[19], POUT[19], GOUT[20] ); smblock0 d120 (A[20], B[20], POUT[20], GOUT[21] ); smblock0 d121 (A[21], B[21], POUT[21], GOUT[22] ); smblock0 d122 (A[22], B[22], POUT[22], GOUT[23] ); smblock0 d123 (A[23], B[23], POUT[23], GOUT[24] ); smblock0 d124 (A[24], B[24], POUT[24], GOUT[25] ); smblock0 d125 (A[25], B[25], POUT[25], GOUT[26] ); smblock0 d126 (A[26], B[26], POUT[26], GOUT[27] ); smblock0 d127 (A[27], B[27], POUT[27], GOUT[28] ); smblock0 d128 (A[28], B[28], POUT[28], GOUT[29] ); smblock0 d129 (A[29], B[29], POUT[29], GOUT[30] ); smblock0 d130 (A[30], B[30], POUT[30], GOUT[31] ); smblock0 d131 (A[31], B[31], POUT[31], GOUT[32] ); smblock0 d132 (A[32], B[32], POUT[32], GOUT[33] ); smblock0 d133 (A[33], B[33], POUT[33], GOUT[34] ); smblock0 d134 (A[34], B[34], POUT[34], GOUT[35] ); smblock0 d135 (A[35], B[35], POUT[35], GOUT[36] ); smblock0 d136 (A[36], B[36], POUT[36], GOUT[37] ); smblock0 d137 (A[37], B[37], POUT[37], GOUT[38] ); smblock0 d138 (A[38], B[38], POUT[38], GOUT[39] ); smblock0 d139 (A[39], B[39], POUT[39], GOUT[40] ); smblock0 d140 (A[40], B[40], POUT[40], GOUT[41] ); smblock0 d141 (A[41], B[41], POUT[41], GOUT[42] ); smblock0 d142 (A[42], B[42], POUT[42], GOUT[43] ); smblock0 d143 (A[43], B[43], POUT[43], GOUT[44] ); smblock0 d144 (A[44], B[44], POUT[44], GOUT[45] ); smblock0 d145 (A[45], B[45], POUT[45], GOUT[46] ); smblock0 d146 (A[46], B[46], POUT[46], GOUT[47] ); smblock0 d147 (A[47], B[47], POUT[47], GOUT[48] ); smblock0 d148 (A[48], B[48], POUT[48], GOUT[49] ); smblock0 d149 (A[49], B[49], POUT[49], GOUT[50] ); smblock0 d150 (A[50], B[50], POUT[50], GOUT[51] ); smblock0 d151 (A[51], B[51], POUT[51], GOUT[52] ); smblock0 d152 (A[52], B[52], POUT[52], GOUT[53] ); smblock0 d153 (A[53], B[53], POUT[53], GOUT[54] ); smblock0 d154 (A[54], B[54], POUT[54], GOUT[55] ); smblock0 d155 (A[55], B[55], POUT[55], GOUT[56] ); smblock0 d156 (A[56], B[56], POUT[56], GOUT[57] ); smblock0 d157 (A[57], B[57], POUT[57], GOUT[58] ); smblock0 d158 (A[58], B[58], POUT[58], GOUT[59] ); smblock0 d159 (A[59], B[59], POUT[59], GOUT[60] ); smblock0 d160 (A[60], B[60], POUT[60], GOUT[61] ); smblock0 d161 (A[61], B[61], POUT[61], GOUT[62] ); smblock0 d162 (A[62], B[62], POUT[62], GOUT[63] ); sminvblock d2 (CIN, GOUT[0] ); endmodule module smdblc_0_128 (PIN, GIN, POUT, GOUT); input [63:0] PIN; input [63:0] GIN; output [63:0] POUT; output [63:0] GOUT; sminvblock d10 (GIN[0], GOUT[0] ); smblock1a d21 (PIN[0], GIN[0], GIN[1], GOUT[1] ); smblock1 d32 (PIN[0], PIN[1], GIN[1], GIN[2], POUT[0], GOUT[2] ); smblock1 d33 (PIN[1], PIN[2], GIN[2], GIN[3], POUT[1], GOUT[3] ); smblock1 d34 (PIN[2], PIN[3], GIN[3], GIN[4], POUT[2], GOUT[4] ); smblock1 d35 (PIN[3], PIN[4], GIN[4], GIN[5], POUT[3], GOUT[5] ); smblock1 d36 (PIN[4], PIN[5], GIN[5], GIN[6], POUT[4], GOUT[6] ); smblock1 d37 (PIN[5], PIN[6], GIN[6], GIN[7], POUT[5], GOUT[7] ); smblock1 d38 (PIN[6], PIN[7], GIN[7], GIN[8], POUT[6], GOUT[8] ); smblock1 d39 (PIN[7], PIN[8], GIN[8], GIN[9], POUT[7], GOUT[9] ); smblock1 d310 (PIN[8], PIN[9], GIN[9], GIN[10], POUT[8], GOUT[10] ); smblock1 d311 (PIN[9], PIN[10], GIN[10], GIN[11], POUT[9], GOUT[11] ); smblock1 d312 (PIN[10], PIN[11], GIN[11], GIN[12], POUT[10], GOUT[12] ); smblock1 d313 (PIN[11], PIN[12], GIN[12], GIN[13], POUT[11], GOUT[13] ); smblock1 d314 (PIN[12], PIN[13], GIN[13], GIN[14], POUT[12], GOUT[14] ); smblock1 d315 (PIN[13], PIN[14], GIN[14], GIN[15], POUT[13], GOUT[15] ); smblock1 d316 (PIN[14], PIN[15], GIN[15], GIN[16], POUT[14], GOUT[16] ); smblock1 d317 (PIN[15], PIN[16], GIN[16], GIN[17], POUT[15], GOUT[17] ); smblock1 d318 (PIN[16], PIN[17], GIN[17], GIN[18], POUT[16], GOUT[18] ); smblock1 d319 (PIN[17], PIN[18], GIN[18], GIN[19], POUT[17], GOUT[19] ); smblock1 d320 (PIN[18], PIN[19], GIN[19], GIN[20], POUT[18], GOUT[20] ); smblock1 d321 (PIN[19], PIN[20], GIN[20], GIN[21], POUT[19], GOUT[21] ); smblock1 d322 (PIN[20], PIN[21], GIN[21], GIN[22], POUT[20], GOUT[22] ); smblock1 d323 (PIN[21], PIN[22], GIN[22], GIN[23], POUT[21], GOUT[23] ); smblock1 d324 (PIN[22], PIN[23], GIN[23], GIN[24], POUT[22], GOUT[24] ); smblock1 d325 (PIN[23], PIN[24], GIN[24], GIN[25], POUT[23], GOUT[25] ); smblock1 d326 (PIN[24], PIN[25], GIN[25], GIN[26], POUT[24], GOUT[26] ); smblock1 d327 (PIN[25], PIN[26], GIN[26], GIN[27], POUT[25], GOUT[27] ); smblock1 d328 (PIN[26], PIN[27], GIN[27], GIN[28], POUT[26], GOUT[28] ); smblock1 d329 (PIN[27], PIN[28], GIN[28], GIN[29], POUT[27], GOUT[29] ); smblock1 d330 (PIN[28], PIN[29], GIN[29], GIN[30], POUT[28], GOUT[30] ); smblock1 d331 (PIN[29], PIN[30], GIN[30], GIN[31], POUT[29], GOUT[31] ); smblock1 d332 (PIN[30], PIN[31], GIN[31], GIN[32], POUT[30], GOUT[32] ); smblock1 d333 (PIN[31], PIN[32], GIN[32], GIN[33], POUT[31], GOUT[33] ); smblock1 d334 (PIN[32], PIN[33], GIN[33], GIN[34], POUT[32], GOUT[34] ); smblock1 d335 (PIN[33], PIN[34], GIN[34], GIN[35], POUT[33], GOUT[35] ); smblock1 d336 (PIN[34], PIN[35], GIN[35], GIN[36], POUT[34], GOUT[36] ); smblock1 d337 (PIN[35], PIN[36], GIN[36], GIN[37], POUT[35], GOUT[37] ); smblock1 d338 (PIN[36], PIN[37], GIN[37], GIN[38], POUT[36], GOUT[38] ); smblock1 d339 (PIN[37], PIN[38], GIN[38], GIN[39], POUT[37], GOUT[39] ); smblock1 d340 (PIN[38], PIN[39], GIN[39], GIN[40], POUT[38], GOUT[40] ); smblock1 d341 (PIN[39], PIN[40], GIN[40], GIN[41], POUT[39], GOUT[41] ); smblock1 d342 (PIN[40], PIN[41], GIN[41], GIN[42], POUT[40], GOUT[42] ); smblock1 d343 (PIN[41], PIN[42], GIN[42], GIN[43], POUT[41], GOUT[43] ); smblock1 d344 (PIN[42], PIN[43], GIN[43], GIN[44], POUT[42], GOUT[44] ); smblock1 d345 (PIN[43], PIN[44], GIN[44], GIN[45], POUT[43], GOUT[45] ); smblock1 d346 (PIN[44], PIN[45], GIN[45], GIN[46], POUT[44], GOUT[46] ); smblock1 d347 (PIN[45], PIN[46], GIN[46], GIN[47], POUT[45], GOUT[47] ); smblock1 d348 (PIN[46], PIN[47], GIN[47], GIN[48], POUT[46], GOUT[48] ); smblock1 d349 (PIN[47], PIN[48], GIN[48], GIN[49], POUT[47], GOUT[49] ); smblock1 d350 (PIN[48], PIN[49], GIN[49], GIN[50], POUT[48], GOUT[50] ); smblock1 d351 (PIN[49], PIN[50], GIN[50], GIN[51], POUT[49], GOUT[51] ); smblock1 d352 (PIN[50], PIN[51], GIN[51], GIN[52], POUT[50], GOUT[52] ); smblock1 d353 (PIN[51], PIN[52], GIN[52], GIN[53], POUT[51], GOUT[53] ); smblock1 d354 (PIN[52], PIN[53], GIN[53], GIN[54], POUT[52], GOUT[54] ); smblock1 d355 (PIN[53], PIN[54], GIN[54], GIN[55], POUT[53], GOUT[55] ); smblock1 d356 (PIN[54], PIN[55], GIN[55], GIN[56], POUT[54], GOUT[56] ); smblock1 d357 (PIN[55], PIN[56], GIN[56], GIN[57], POUT[55], GOUT[57] ); smblock1 d358 (PIN[56], PIN[57], GIN[57], GIN[58], POUT[56], GOUT[58] ); smblock1 d359 (PIN[57], PIN[58], GIN[58], GIN[59], POUT[57], GOUT[59] ); smblock1 d360 (PIN[58], PIN[59], GIN[59], GIN[60], POUT[58], GOUT[60] ); smblock1 d361 (PIN[59], PIN[60], GIN[60], GIN[61], POUT[59], GOUT[61] ); smblock1 d362 (PIN[60], PIN[61], GIN[61], GIN[62], POUT[60], GOUT[62] ); smblock1 d363 (PIN[61], PIN[62], GIN[62], GIN[63], POUT[61], GOUT[63] ); endmodule module smdblc_1_128 (PIN, GIN, POUT, GOUT); input [63:0] PIN; input [63:0] GIN; output [63:0] POUT; output [63:0] GOUT; sminvblock d10 (GIN[0], GOUT[0] ); sminvblock d11 (GIN[1], GOUT[1] ); smblock2a d22 (PIN[0], GIN[0], GIN[2], GOUT[2] ); smblock2a d23 (PIN[1], GIN[1], GIN[3], GOUT[3] ); smblock2 d34 (PIN[0], PIN[2], GIN[2], GIN[4], POUT[0], GOUT[4] ); smblock2 d35 (PIN[1], PIN[3], GIN[3], GIN[5], POUT[1], GOUT[5] ); smblock2 d36 (PIN[2], PIN[4], GIN[4], GIN[6], POUT[2], GOUT[6] ); smblock2 d37 (PIN[3], PIN[5], GIN[5], GIN[7], POUT[3], GOUT[7] ); smblock2 d38 (PIN[4], PIN[6], GIN[6], GIN[8], POUT[4], GOUT[8] ); smblock2 d39 (PIN[5], PIN[7], GIN[7], GIN[9], POUT[5], GOUT[9] ); smblock2 d310 (PIN[6], PIN[8], GIN[8], GIN[10], POUT[6], GOUT[10] ); smblock2 d311 (PIN[7], PIN[9], GIN[9], GIN[11], POUT[7], GOUT[11] ); smblock2 d312 (PIN[8], PIN[10], GIN[10], GIN[12], POUT[8], GOUT[12] ); smblock2 d313 (PIN[9], PIN[11], GIN[11], GIN[13], POUT[9], GOUT[13] ); smblock2 d314 (PIN[10], PIN[12], GIN[12], GIN[14], POUT[10], GOUT[14] ); smblock2 d315 (PIN[11], PIN[13], GIN[13], GIN[15], POUT[11], GOUT[15] ); smblock2 d316 (PIN[12], PIN[14], GIN[14], GIN[16], POUT[12], GOUT[16] ); smblock2 d317 (PIN[13], PIN[15], GIN[15], GIN[17], POUT[13], GOUT[17] ); smblock2 d318 (PIN[14], PIN[16], GIN[16], GIN[18], POUT[14], GOUT[18] ); smblock2 d319 (PIN[15], PIN[17], GIN[17], GIN[19], POUT[15], GOUT[19] ); smblock2 d320 (PIN[16], PIN[18], GIN[18], GIN[20], POUT[16], GOUT[20] ); smblock2 d321 (PIN[17], PIN[19], GIN[19], GIN[21], POUT[17], GOUT[21] ); smblock2 d322 (PIN[18], PIN[20], GIN[20], GIN[22], POUT[18], GOUT[22] ); smblock2 d323 (PIN[19], PIN[21], GIN[21], GIN[23], POUT[19], GOUT[23] ); smblock2 d324 (PIN[20], PIN[22], GIN[22], GIN[24], POUT[20], GOUT[24] ); smblock2 d325 (PIN[21], PIN[23], GIN[23], GIN[25], POUT[21], GOUT[25] ); smblock2 d326 (PIN[22], PIN[24], GIN[24], GIN[26], POUT[22], GOUT[26] ); smblock2 d327 (PIN[23], PIN[25], GIN[25], GIN[27], POUT[23], GOUT[27] ); smblock2 d328 (PIN[24], PIN[26], GIN[26], GIN[28], POUT[24], GOUT[28] ); smblock2 d329 (PIN[25], PIN[27], GIN[27], GIN[29], POUT[25], GOUT[29] ); smblock2 d330 (PIN[26], PIN[28], GIN[28], GIN[30], POUT[26], GOUT[30] ); smblock2 d331 (PIN[27], PIN[29], GIN[29], GIN[31], POUT[27], GOUT[31] ); smblock2 d332 (PIN[28], PIN[30], GIN[30], GIN[32], POUT[28], GOUT[32] ); smblock2 d333 (PIN[29], PIN[31], GIN[31], GIN[33], POUT[29], GOUT[33] ); smblock2 d334 (PIN[30], PIN[32], GIN[32], GIN[34], POUT[30], GOUT[34] ); smblock2 d335 (PIN[31], PIN[33], GIN[33], GIN[35], POUT[31], GOUT[35] ); smblock2 d336 (PIN[32], PIN[34], GIN[34], GIN[36], POUT[32], GOUT[36] ); smblock2 d337 (PIN[33], PIN[35], GIN[35], GIN[37], POUT[33], GOUT[37] ); smblock2 d338 (PIN[34], PIN[36], GIN[36], GIN[38], POUT[34], GOUT[38] ); smblock2 d339 (PIN[35], PIN[37], GIN[37], GIN[39], POUT[35], GOUT[39] ); smblock2 d340 (PIN[36], PIN[38], GIN[38], GIN[40], POUT[36], GOUT[40] ); smblock2 d341 (PIN[37], PIN[39], GIN[39], GIN[41], POUT[37], GOUT[41] ); smblock2 d342 (PIN[38], PIN[40], GIN[40], GIN[42], POUT[38], GOUT[42] ); smblock2 d343 (PIN[39], PIN[41], GIN[41], GIN[43], POUT[39], GOUT[43] ); smblock2 d344 (PIN[40], PIN[42], GIN[42], GIN[44], POUT[40], GOUT[44] ); smblock2 d345 (PIN[41], PIN[43], GIN[43], GIN[45], POUT[41], GOUT[45] ); smblock2 d346 (PIN[42], PIN[44], GIN[44], GIN[46], POUT[42], GOUT[46] ); smblock2 d347 (PIN[43], PIN[45], GIN[45], GIN[47], POUT[43], GOUT[47] ); smblock2 d348 (PIN[44], PIN[46], GIN[46], GIN[48], POUT[44], GOUT[48] ); smblock2 d349 (PIN[45], PIN[47], GIN[47], GIN[49], POUT[45], GOUT[49] ); smblock2 d350 (PIN[46], PIN[48], GIN[48], GIN[50], POUT[46], GOUT[50] ); smblock2 d351 (PIN[47], PIN[49], GIN[49], GIN[51], POUT[47], GOUT[51] ); smblock2 d352 (PIN[48], PIN[50], GIN[50], GIN[52], POUT[48], GOUT[52] ); smblock2 d353 (PIN[49], PIN[51], GIN[51], GIN[53], POUT[49], GOUT[53] ); smblock2 d354 (PIN[50], PIN[52], GIN[52], GIN[54], POUT[50], GOUT[54] ); smblock2 d355 (PIN[51], PIN[53], GIN[53], GIN[55], POUT[51], GOUT[55] ); smblock2 d356 (PIN[52], PIN[54], GIN[54], GIN[56], POUT[52], GOUT[56] ); smblock2 d357 (PIN[53], PIN[55], GIN[55], GIN[57], POUT[53], GOUT[57] ); smblock2 d358 (PIN[54], PIN[56], GIN[56], GIN[58], POUT[54], GOUT[58] ); smblock2 d359 (PIN[55], PIN[57], GIN[57], GIN[59], POUT[55], GOUT[59] ); smblock2 d360 (PIN[56], PIN[58], GIN[58], GIN[60], POUT[56], GOUT[60] ); smblock2 d361 (PIN[57], PIN[59], GIN[59], GIN[61], POUT[57], GOUT[61] ); smblock2 d362 (PIN[58], PIN[60], GIN[60], GIN[62], POUT[58], GOUT[62] ); smblock2 d363 (PIN[59], PIN[61], GIN[61], GIN[63], POUT[59], GOUT[63] ); endmodule module smdblc_2_128 (PIN, GIN, POUT, GOUT); input [63:0] PIN; input [63:0] GIN; output [63:0] POUT; output [63:0] GOUT; sminvblock d10 (GIN[0], GOUT[0] ); sminvblock d11 (GIN[1], GOUT[1] ); sminvblock d12 (GIN[2], GOUT[2] ); sminvblock d13 (GIN[3], GOUT[3] ); smblock1a d24 (PIN[0], GIN[0], GIN[4], GOUT[4] ); smblock1a d25 (PIN[1], GIN[1], GIN[5], GOUT[5] ); smblock1a d26 (PIN[2], GIN[2], GIN[6], GOUT[6] ); smblock1a d27 (PIN[3], GIN[3], GIN[7], GOUT[7] ); smblock1 d38 (PIN[0], PIN[4], GIN[4], GIN[8], POUT[0], GOUT[8] ); smblock1 d39 (PIN[1], PIN[5], GIN[5], GIN[9], POUT[1], GOUT[9] ); smblock1 d310 (PIN[2], PIN[6], GIN[6], GIN[10], POUT[2], GOUT[10] ); smblock1 d311 (PIN[3], PIN[7], GIN[7], GIN[11], POUT[3], GOUT[11] ); smblock1 d312 (PIN[4], PIN[8], GIN[8], GIN[12], POUT[4], GOUT[12] ); smblock1 d313 (PIN[5], PIN[9], GIN[9], GIN[13], POUT[5], GOUT[13] ); smblock1 d314 (PIN[6], PIN[10], GIN[10], GIN[14], POUT[6], GOUT[14] ); smblock1 d315 (PIN[7], PIN[11], GIN[11], GIN[15], POUT[7], GOUT[15] ); smblock1 d316 (PIN[8], PIN[12], GIN[12], GIN[16], POUT[8], GOUT[16] ); smblock1 d317 (PIN[9], PIN[13], GIN[13], GIN[17], POUT[9], GOUT[17] ); smblock1 d318 (PIN[10], PIN[14], GIN[14], GIN[18], POUT[10], GOUT[18] ); smblock1 d319 (PIN[11], PIN[15], GIN[15], GIN[19], POUT[11], GOUT[19] ); smblock1 d320 (PIN[12], PIN[16], GIN[16], GIN[20], POUT[12], GOUT[20] ); smblock1 d321 (PIN[13], PIN[17], GIN[17], GIN[21], POUT[13], GOUT[21] ); smblock1 d322 (PIN[14], PIN[18], GIN[18], GIN[22], POUT[14], GOUT[22] ); smblock1 d323 (PIN[15], PIN[19], GIN[19], GIN[23], POUT[15], GOUT[23] ); smblock1 d324 (PIN[16], PIN[20], GIN[20], GIN[24], POUT[16], GOUT[24] ); smblock1 d325 (PIN[17], PIN[21], GIN[21], GIN[25], POUT[17], GOUT[25] ); smblock1 d326 (PIN[18], PIN[22], GIN[22], GIN[26], POUT[18], GOUT[26] ); smblock1 d327 (PIN[19], PIN[23], GIN[23], GIN[27], POUT[19], GOUT[27] ); smblock1 d328 (PIN[20], PIN[24], GIN[24], GIN[28], POUT[20], GOUT[28] ); smblock1 d329 (PIN[21], PIN[25], GIN[25], GIN[29], POUT[21], GOUT[29] ); smblock1 d330 (PIN[22], PIN[26], GIN[26], GIN[30], POUT[22], GOUT[30] ); smblock1 d331 (PIN[23], PIN[27], GIN[27], GIN[31], POUT[23], GOUT[31] ); smblock1 d332 (PIN[24], PIN[28], GIN[28], GIN[32], POUT[24], GOUT[32] ); smblock1 d333 (PIN[25], PIN[29], GIN[29], GIN[33], POUT[25], GOUT[33] ); smblock1 d334 (PIN[26], PIN[30], GIN[30], GIN[34], POUT[26], GOUT[34] ); smblock1 d335 (PIN[27], PIN[31], GIN[31], GIN[35], POUT[27], GOUT[35] ); smblock1 d336 (PIN[28], PIN[32], GIN[32], GIN[36], POUT[28], GOUT[36] ); smblock1 d337 (PIN[29], PIN[33], GIN[33], GIN[37], POUT[29], GOUT[37] ); smblock1 d338 (PIN[30], PIN[34], GIN[34], GIN[38], POUT[30], GOUT[38] ); smblock1 d339 (PIN[31], PIN[35], GIN[35], GIN[39], POUT[31], GOUT[39] ); smblock1 d340 (PIN[32], PIN[36], GIN[36], GIN[40], POUT[32], GOUT[40] ); smblock1 d341 (PIN[33], PIN[37], GIN[37], GIN[41], POUT[33], GOUT[41] ); smblock1 d342 (PIN[34], PIN[38], GIN[38], GIN[42], POUT[34], GOUT[42] ); smblock1 d343 (PIN[35], PIN[39], GIN[39], GIN[43], POUT[35], GOUT[43] ); smblock1 d344 (PIN[36], PIN[40], GIN[40], GIN[44], POUT[36], GOUT[44] ); smblock1 d345 (PIN[37], PIN[41], GIN[41], GIN[45], POUT[37], GOUT[45] ); smblock1 d346 (PIN[38], PIN[42], GIN[42], GIN[46], POUT[38], GOUT[46] ); smblock1 d347 (PIN[39], PIN[43], GIN[43], GIN[47], POUT[39], GOUT[47] ); smblock1 d348 (PIN[40], PIN[44], GIN[44], GIN[48], POUT[40], GOUT[48] ); smblock1 d349 (PIN[41], PIN[45], GIN[45], GIN[49], POUT[41], GOUT[49] ); smblock1 d350 (PIN[42], PIN[46], GIN[46], GIN[50], POUT[42], GOUT[50] ); smblock1 d351 (PIN[43], PIN[47], GIN[47], GIN[51], POUT[43], GOUT[51] ); smblock1 d352 (PIN[44], PIN[48], GIN[48], GIN[52], POUT[44], GOUT[52] ); smblock1 d353 (PIN[45], PIN[49], GIN[49], GIN[53], POUT[45], GOUT[53] ); smblock1 d354 (PIN[46], PIN[50], GIN[50], GIN[54], POUT[46], GOUT[54] ); smblock1 d355 (PIN[47], PIN[51], GIN[51], GIN[55], POUT[47], GOUT[55] ); smblock1 d356 (PIN[48], PIN[52], GIN[52], GIN[56], POUT[48], GOUT[56] ); smblock1 d357 (PIN[49], PIN[53], GIN[53], GIN[57], POUT[49], GOUT[57] ); smblock1 d358 (PIN[50], PIN[54], GIN[54], GIN[58], POUT[50], GOUT[58] ); smblock1 d359 (PIN[51], PIN[55], GIN[55], GIN[59], POUT[51], GOUT[59] ); smblock1 d360 (PIN[52], PIN[56], GIN[56], GIN[60], POUT[52], GOUT[60] ); smblock1 d361 (PIN[53], PIN[57], GIN[57], GIN[61], POUT[53], GOUT[61] ); smblock1 d362 (PIN[54], PIN[58], GIN[58], GIN[62], POUT[54], GOUT[62] ); smblock1 d363 (PIN[55], PIN[59], GIN[59], GIN[63], POUT[55], GOUT[63] ); endmodule module smdblc_3_128 (PIN, GIN, POUT, GOUT); input [63:0] PIN; input [63:0] GIN; output [63:0] POUT; output [63:0] GOUT; sminvblock d10 (GIN[0], GOUT[0] ); sminvblock d11 (GIN[1], GOUT[1] ); sminvblock d12 (GIN[2], GOUT[2] ); sminvblock d13 (GIN[3], GOUT[3] ); sminvblock d14 (GIN[4], GOUT[4] ); sminvblock d15 (GIN[5], GOUT[5] ); sminvblock d16 (GIN[6], GOUT[6] ); sminvblock d17 (GIN[7], GOUT[7] ); smblock2a d28 (PIN[0], GIN[0], GIN[8], GOUT[8] ); smblock2a d29 (PIN[1], GIN[1], GIN[9], GOUT[9] ); smblock2a d210 (PIN[2], GIN[2], GIN[10], GOUT[10] ); smblock2a d211 (PIN[3], GIN[3], GIN[11], GOUT[11] ); smblock2a d212 (PIN[4], GIN[4], GIN[12], GOUT[12] ); smblock2a d213 (PIN[5], GIN[5], GIN[13], GOUT[13] ); smblock2a d214 (PIN[6], GIN[6], GIN[14], GOUT[14] ); smblock2a d215 (PIN[7], GIN[7], GIN[15], GOUT[15] ); smblock2 d316 (PIN[0], PIN[8], GIN[8], GIN[16], POUT[0], GOUT[16] ); smblock2 d317 (PIN[1], PIN[9], GIN[9], GIN[17], POUT[1], GOUT[17] ); smblock2 d318 (PIN[2], PIN[10], GIN[10], GIN[18], POUT[2], GOUT[18] ); smblock2 d319 (PIN[3], PIN[11], GIN[11], GIN[19], POUT[3], GOUT[19] ); smblock2 d320 (PIN[4], PIN[12], GIN[12], GIN[20], POUT[4], GOUT[20] ); smblock2 d321 (PIN[5], PIN[13], GIN[13], GIN[21], POUT[5], GOUT[21] ); smblock2 d322 (PIN[6], PIN[14], GIN[14], GIN[22], POUT[6], GOUT[22] ); smblock2 d323 (PIN[7], PIN[15], GIN[15], GIN[23], POUT[7], GOUT[23] ); smblock2 d324 (PIN[8], PIN[16], GIN[16], GIN[24], POUT[8], GOUT[24] ); smblock2 d325 (PIN[9], PIN[17], GIN[17], GIN[25], POUT[9], GOUT[25] ); smblock2 d326 (PIN[10], PIN[18], GIN[18], GIN[26], POUT[10], GOUT[26] ); smblock2 d327 (PIN[11], PIN[19], GIN[19], GIN[27], POUT[11], GOUT[27] ); smblock2 d328 (PIN[12], PIN[20], GIN[20], GIN[28], POUT[12], GOUT[28] ); smblock2 d329 (PIN[13], PIN[21], GIN[21], GIN[29], POUT[13], GOUT[29] ); smblock2 d330 (PIN[14], PIN[22], GIN[22], GIN[30], POUT[14], GOUT[30] ); smblock2 d331 (PIN[15], PIN[23], GIN[23], GIN[31], POUT[15], GOUT[31] ); smblock2 d332 (PIN[16], PIN[24], GIN[24], GIN[32], POUT[16], GOUT[32] ); smblock2 d333 (PIN[17], PIN[25], GIN[25], GIN[33], POUT[17], GOUT[33] ); smblock2 d334 (PIN[18], PIN[26], GIN[26], GIN[34], POUT[18], GOUT[34] ); smblock2 d335 (PIN[19], PIN[27], GIN[27], GIN[35], POUT[19], GOUT[35] ); smblock2 d336 (PIN[20], PIN[28], GIN[28], GIN[36], POUT[20], GOUT[36] ); smblock2 d337 (PIN[21], PIN[29], GIN[29], GIN[37], POUT[21], GOUT[37] ); smblock2 d338 (PIN[22], PIN[30], GIN[30], GIN[38], POUT[22], GOUT[38] ); smblock2 d339 (PIN[23], PIN[31], GIN[31], GIN[39], POUT[23], GOUT[39] ); smblock2 d340 (PIN[24], PIN[32], GIN[32], GIN[40], POUT[24], GOUT[40] ); smblock2 d341 (PIN[25], PIN[33], GIN[33], GIN[41], POUT[25], GOUT[41] ); smblock2 d342 (PIN[26], PIN[34], GIN[34], GIN[42], POUT[26], GOUT[42] ); smblock2 d343 (PIN[27], PIN[35], GIN[35], GIN[43], POUT[27], GOUT[43] ); smblock2 d344 (PIN[28], PIN[36], GIN[36], GIN[44], POUT[28], GOUT[44] ); smblock2 d345 (PIN[29], PIN[37], GIN[37], GIN[45], POUT[29], GOUT[45] ); smblock2 d346 (PIN[30], PIN[38], GIN[38], GIN[46], POUT[30], GOUT[46] ); smblock2 d347 (PIN[31], PIN[39], GIN[39], GIN[47], POUT[31], GOUT[47] ); smblock2 d348 (PIN[32], PIN[40], GIN[40], GIN[48], POUT[32], GOUT[48] ); smblock2 d349 (PIN[33], PIN[41], GIN[41], GIN[49], POUT[33], GOUT[49] ); smblock2 d350 (PIN[34], PIN[42], GIN[42], GIN[50], POUT[34], GOUT[50] ); smblock2 d351 (PIN[35], PIN[43], GIN[43], GIN[51], POUT[35], GOUT[51] ); smblock2 d352 (PIN[36], PIN[44], GIN[44], GIN[52], POUT[36], GOUT[52] ); smblock2 d353 (PIN[37], PIN[45], GIN[45], GIN[53], POUT[37], GOUT[53] ); smblock2 d354 (PIN[38], PIN[46], GIN[46], GIN[54], POUT[38], GOUT[54] ); smblock2 d355 (PIN[39], PIN[47], GIN[47], GIN[55], POUT[39], GOUT[55] ); smblock2 d356 (PIN[40], PIN[48], GIN[48], GIN[56], POUT[40], GOUT[56] ); smblock2 d357 (PIN[41], PIN[49], GIN[49], GIN[57], POUT[41], GOUT[57] ); smblock2 d358 (PIN[42], PIN[50], GIN[50], GIN[58], POUT[42], GOUT[58] ); smblock2 d359 (PIN[43], PIN[51], GIN[51], GIN[59], POUT[43], GOUT[59] ); smblock2 d360 (PIN[44], PIN[52], GIN[52], GIN[60], POUT[44], GOUT[60] ); smblock2 d361 (PIN[45], PIN[53], GIN[53], GIN[61], POUT[45], GOUT[61] ); smblock2 d362 (PIN[46], PIN[54], GIN[54], GIN[62], POUT[46], GOUT[62] ); smblock2 d363 (PIN[47], PIN[55], GIN[55], GIN[63], POUT[47], GOUT[63] ); endmodule module smdblc_4_128 (PIN, GIN, POUT, GOUT); input [63:0] PIN; input [63:0] GIN; output [63:0] POUT; output [63:0] GOUT; sminvblock d10 (GIN[0], GOUT[0] ); sminvblock d11 (GIN[1], GOUT[1] ); sminvblock d12 (GIN[2], GOUT[2] ); sminvblock d13 (GIN[3], GOUT[3] ); sminvblock d14 (GIN[4], GOUT[4] ); sminvblock d15 (GIN[5], GOUT[5] ); sminvblock d16 (GIN[6], GOUT[6] ); sminvblock d17 (GIN[7], GOUT[7] ); sminvblock d18 (GIN[8], GOUT[8] ); sminvblock d19 (GIN[9], GOUT[9] ); sminvblock d110 (GIN[10], GOUT[10] ); sminvblock d111 (GIN[11], GOUT[11] ); sminvblock d112 (GIN[12], GOUT[12] ); sminvblock d113 (GIN[13], GOUT[13] ); sminvblock d114 (GIN[14], GOUT[14] ); sminvblock d115 (GIN[15], GOUT[15] ); smblock1a d216 (PIN[0], GIN[0], GIN[16], GOUT[16] ); smblock1a d217 (PIN[1], GIN[1], GIN[17], GOUT[17] ); smblock1a d218 (PIN[2], GIN[2], GIN[18], GOUT[18] ); smblock1a d219 (PIN[3], GIN[3], GIN[19], GOUT[19] ); smblock1a d220 (PIN[4], GIN[4], GIN[20], GOUT[20] ); smblock1a d221 (PIN[5], GIN[5], GIN[21], GOUT[21] ); smblock1a d222 (PIN[6], GIN[6], GIN[22], GOUT[22] ); smblock1a d223 (PIN[7], GIN[7], GIN[23], GOUT[23] ); smblock1a d224 (PIN[8], GIN[8], GIN[24], GOUT[24] ); smblock1a d225 (PIN[9], GIN[9], GIN[25], GOUT[25] ); smblock1a d226 (PIN[10], GIN[10], GIN[26], GOUT[26] ); smblock1a d227 (PIN[11], GIN[11], GIN[27], GOUT[27] ); smblock1a d228 (PIN[12], GIN[12], GIN[28], GOUT[28] ); smblock1a d229 (PIN[13], GIN[13], GIN[29], GOUT[29] ); smblock1a d230 (PIN[14], GIN[14], GIN[30], GOUT[30] ); smblock1a d231 (PIN[15], GIN[15], GIN[31], GOUT[31] ); smblock1 d332 (PIN[0], PIN[16], GIN[16], GIN[32], POUT[0], GOUT[32] ); smblock1 d333 (PIN[1], PIN[17], GIN[17], GIN[33], POUT[1], GOUT[33] ); smblock1 d334 (PIN[2], PIN[18], GIN[18], GIN[34], POUT[2], GOUT[34] ); smblock1 d335 (PIN[3], PIN[19], GIN[19], GIN[35], POUT[3], GOUT[35] ); smblock1 d336 (PIN[4], PIN[20], GIN[20], GIN[36], POUT[4], GOUT[36] ); smblock1 d337 (PIN[5], PIN[21], GIN[21], GIN[37], POUT[5], GOUT[37] ); smblock1 d338 (PIN[6], PIN[22], GIN[22], GIN[38], POUT[6], GOUT[38] ); smblock1 d339 (PIN[7], PIN[23], GIN[23], GIN[39], POUT[7], GOUT[39] ); smblock1 d340 (PIN[8], PIN[24], GIN[24], GIN[40], POUT[8], GOUT[40] ); smblock1 d341 (PIN[9], PIN[25], GIN[25], GIN[41], POUT[9], GOUT[41] ); smblock1 d342 (PIN[10], PIN[26], GIN[26], GIN[42], POUT[10], GOUT[42] ); smblock1 d343 (PIN[11], PIN[27], GIN[27], GIN[43], POUT[11], GOUT[43] ); smblock1 d344 (PIN[12], PIN[28], GIN[28], GIN[44], POUT[12], GOUT[44] ); smblock1 d345 (PIN[13], PIN[29], GIN[29], GIN[45], POUT[13], GOUT[45] ); smblock1 d346 (PIN[14], PIN[30], GIN[30], GIN[46], POUT[14], GOUT[46] ); smblock1 d347 (PIN[15], PIN[31], GIN[31], GIN[47], POUT[15], GOUT[47] ); smblock1 d348 (PIN[16], PIN[32], GIN[32], GIN[48], POUT[16], GOUT[48] ); smblock1 d349 (PIN[17], PIN[33], GIN[33], GIN[49], POUT[17], GOUT[49] ); smblock1 d350 (PIN[18], PIN[34], GIN[34], GIN[50], POUT[18], GOUT[50] ); smblock1 d351 (PIN[19], PIN[35], GIN[35], GIN[51], POUT[19], GOUT[51] ); smblock1 d352 (PIN[20], PIN[36], GIN[36], GIN[52], POUT[20], GOUT[52] ); smblock1 d353 (PIN[21], PIN[37], GIN[37], GIN[53], POUT[21], GOUT[53] ); smblock1 d354 (PIN[22], PIN[38], GIN[38], GIN[54], POUT[22], GOUT[54] ); smblock1 d355 (PIN[23], PIN[39], GIN[39], GIN[55], POUT[23], GOUT[55] ); smblock1 d356 (PIN[24], PIN[40], GIN[40], GIN[56], POUT[24], GOUT[56] ); smblock1 d357 (PIN[25], PIN[41], GIN[41], GIN[57], POUT[25], GOUT[57] ); smblock1 d358 (PIN[26], PIN[42], GIN[42], GIN[58], POUT[26], GOUT[58] ); smblock1 d359 (PIN[27], PIN[43], GIN[43], GIN[59], POUT[27], GOUT[59] ); smblock1 d360 (PIN[28], PIN[44], GIN[44], GIN[60], POUT[28], GOUT[60] ); smblock1 d361 (PIN[29], PIN[45], GIN[45], GIN[61], POUT[29], GOUT[61] ); smblock1 d362 (PIN[30], PIN[46], GIN[46], GIN[62], POUT[30], GOUT[62] ); smblock1 d363 (PIN[31], PIN[47], GIN[47], GIN[63], POUT[31], GOUT[63] ); endmodule module smxorstage_128 (A, B, PBIT, CARRY, SUM); input [63:0] A; input [63:0] B; input PBIT; input [63:0] CARRY; output [63:0] SUM; smxxor1 d20 (A[0], B[0], CARRY[0], SUM[0] ); smxxor1 d21 (A[1], B[1], CARRY[1], SUM[1] ); smxxor1 d22 (A[2], B[2], CARRY[2], SUM[2] ); smxxor1 d23 (A[3], B[3], CARRY[3], SUM[3] ); smxxor1 d24 (A[4], B[4], CARRY[4], SUM[4] ); smxxor1 d25 (A[5], B[5], CARRY[5], SUM[5] ); smxxor1 d26 (A[6], B[6], CARRY[6], SUM[6] ); smxxor1 d27 (A[7], B[7], CARRY[7], SUM[7] ); smxxor1 d28 (A[8], B[8], CARRY[8], SUM[8] ); smxxor1 d29 (A[9], B[9], CARRY[9], SUM[9] ); smxxor1 d210 (A[10], B[10], CARRY[10], SUM[10] ); smxxor1 d211 (A[11], B[11], CARRY[11], SUM[11] ); smxxor1 d212 (A[12], B[12], CARRY[12], SUM[12] ); smxxor1 d213 (A[13], B[13], CARRY[13], SUM[13] ); smxxor1 d214 (A[14], B[14], CARRY[14], SUM[14] ); smxxor1 d215 (A[15], B[15], CARRY[15], SUM[15] ); smxxor1 d216 (A[16], B[16], CARRY[16], SUM[16] ); smxxor1 d217 (A[17], B[17], CARRY[17], SUM[17] ); smxxor1 d218 (A[18], B[18], CARRY[18], SUM[18] ); smxxor1 d219 (A[19], B[19], CARRY[19], SUM[19] ); smxxor1 d220 (A[20], B[20], CARRY[20], SUM[20] ); smxxor1 d221 (A[21], B[21], CARRY[21], SUM[21] ); smxxor1 d222 (A[22], B[22], CARRY[22], SUM[22] ); smxxor1 d223 (A[23], B[23], CARRY[23], SUM[23] ); smxxor1 d224 (A[24], B[24], CARRY[24], SUM[24] ); smxxor1 d225 (A[25], B[25], CARRY[25], SUM[25] ); smxxor1 d226 (A[26], B[26], CARRY[26], SUM[26] ); smxxor1 d227 (A[27], B[27], CARRY[27], SUM[27] ); smxxor1 d228 (A[28], B[28], CARRY[28], SUM[28] ); smxxor1 d229 (A[29], B[29], CARRY[29], SUM[29] ); smxxor1 d230 (A[30], B[30], CARRY[30], SUM[30] ); smxxor1 d231 (A[31], B[31], CARRY[31], SUM[31] ); smxxor1 d232 (A[32], B[32], CARRY[32], SUM[32] ); smxxor1 d233 (A[33], B[33], CARRY[33], SUM[33] ); smxxor1 d234 (A[34], B[34], CARRY[34], SUM[34] ); smxxor1 d235 (A[35], B[35], CARRY[35], SUM[35] ); smxxor1 d236 (A[36], B[36], CARRY[36], SUM[36] ); smxxor1 d237 (A[37], B[37], CARRY[37], SUM[37] ); smxxor1 d238 (A[38], B[38], CARRY[38], SUM[38] ); smxxor1 d239 (A[39], B[39], CARRY[39], SUM[39] ); smxxor1 d240 (A[40], B[40], CARRY[40], SUM[40] ); smxxor1 d241 (A[41], B[41], CARRY[41], SUM[41] ); smxxor1 d242 (A[42], B[42], CARRY[42], SUM[42] ); smxxor1 d243 (A[43], B[43], CARRY[43], SUM[43] ); smxxor1 d244 (A[44], B[44], CARRY[44], SUM[44] ); smxxor1 d245 (A[45], B[45], CARRY[45], SUM[45] ); smxxor1 d246 (A[46], B[46], CARRY[46], SUM[46] ); smxxor1 d247 (A[47], B[47], CARRY[47], SUM[47] ); smxxor1 d248 (A[48], B[48], CARRY[48], SUM[48] ); smxxor1 d249 (A[49], B[49], CARRY[49], SUM[49] ); smxxor1 d250 (A[50], B[50], CARRY[50], SUM[50] ); smxxor1 d251 (A[51], B[51], CARRY[51], SUM[51] ); smxxor1 d252 (A[52], B[52], CARRY[52], SUM[52] ); smxxor1 d253 (A[53], B[53], CARRY[53], SUM[53] ); smxxor1 d254 (A[54], B[54], CARRY[54], SUM[54] ); smxxor1 d255 (A[55], B[55], CARRY[55], SUM[55] ); smxxor1 d256 (A[56], B[56], CARRY[56], SUM[56] ); smxxor1 d257 (A[57], B[57], CARRY[57], SUM[57] ); smxxor1 d258 (A[58], B[58], CARRY[58], SUM[58] ); smxxor1 d259 (A[59], B[59], CARRY[59], SUM[59] ); smxxor1 d260 (A[60], B[60], CARRY[60], SUM[60] ); smxxor1 d261 (A[61], B[61], CARRY[61], SUM[61] ); smxxor1 d262 (A[62], B[62], CARRY[62], SUM[62] ); smxxor1 d263 (A[63], B[63], CARRY[63], SUM[63] ); endmodule module smdblc_5_128 (PIN, GIN, POUT, GOUT); input [63:0] PIN; input [63:0] GIN; output [63:0] POUT; output [63:0] GOUT; sminvblock d10 (GIN[0], GOUT[0] ); sminvblock d11 (GIN[1], GOUT[1] ); sminvblock d12 (GIN[2], GOUT[2] ); sminvblock d13 (GIN[3], GOUT[3] ); sminvblock d14 (GIN[4], GOUT[4] ); sminvblock d15 (GIN[5], GOUT[5] ); sminvblock d16 (GIN[6], GOUT[6] ); sminvblock d17 (GIN[7], GOUT[7] ); sminvblock d18 (GIN[8], GOUT[8] ); sminvblock d19 (GIN[9], GOUT[9] ); sminvblock d110 (GIN[10], GOUT[10] ); sminvblock d111 (GIN[11], GOUT[11] ); sminvblock d112 (GIN[12], GOUT[12] ); sminvblock d113 (GIN[13], GOUT[13] ); sminvblock d114 (GIN[14], GOUT[14] ); sminvblock d115 (GIN[15], GOUT[15] ); sminvblock d116 (GIN[16], GOUT[16] ); sminvblock d117 (GIN[17], GOUT[17] ); sminvblock d118 (GIN[18], GOUT[18] ); sminvblock d119 (GIN[19], GOUT[19] ); sminvblock d120 (GIN[20], GOUT[20] ); sminvblock d121 (GIN[21], GOUT[21] ); sminvblock d122 (GIN[22], GOUT[22] ); sminvblock d123 (GIN[23], GOUT[23] ); sminvblock d124 (GIN[24], GOUT[24] ); sminvblock d125 (GIN[25], GOUT[25] ); sminvblock d126 (GIN[26], GOUT[26] ); sminvblock d127 (GIN[27], GOUT[27] ); sminvblock d128 (GIN[28], GOUT[28] ); sminvblock d129 (GIN[29], GOUT[29] ); sminvblock d130 (GIN[30], GOUT[30] ); sminvblock d131 (GIN[31], GOUT[31] ); smblock2a d232 (PIN[0], GIN[0], GIN[32], GOUT[32] ); smblock2a d233 (PIN[1], GIN[1], GIN[33], GOUT[33] ); smblock2a d234 (PIN[2], GIN[2], GIN[34], GOUT[34] ); smblock2a d235 (PIN[3], GIN[3], GIN[35], GOUT[35] ); smblock2a d236 (PIN[4], GIN[4], GIN[36], GOUT[36] ); smblock2a d237 (PIN[5], GIN[5], GIN[37], GOUT[37] ); smblock2a d238 (PIN[6], GIN[6], GIN[38], GOUT[38] ); smblock2a d239 (PIN[7], GIN[7], GIN[39], GOUT[39] ); smblock2a d240 (PIN[8], GIN[8], GIN[40], GOUT[40] ); smblock2a d241 (PIN[9], GIN[9], GIN[41], GOUT[41] ); smblock2a d242 (PIN[10], GIN[10], GIN[42], GOUT[42] ); smblock2a d243 (PIN[11], GIN[11], GIN[43], GOUT[43] ); smblock2a d244 (PIN[12], GIN[12], GIN[44], GOUT[44] ); smblock2a d245 (PIN[13], GIN[13], GIN[45], GOUT[45] ); smblock2a d246 (PIN[14], GIN[14], GIN[46], GOUT[46] ); smblock2a d247 (PIN[15], GIN[15], GIN[47], GOUT[47] ); smblock2a d248 (PIN[16], GIN[16], GIN[48], GOUT[48] ); smblock2a d249 (PIN[17], GIN[17], GIN[49], GOUT[49] ); smblock2a d250 (PIN[18], GIN[18], GIN[50], GOUT[50] ); smblock2a d251 (PIN[19], GIN[19], GIN[51], GOUT[51] ); smblock2a d252 (PIN[20], GIN[20], GIN[52], GOUT[52] ); smblock2a d253 (PIN[21], GIN[21], GIN[53], GOUT[53] ); smblock2a d254 (PIN[22], GIN[22], GIN[54], GOUT[54] ); smblock2a d255 (PIN[23], GIN[23], GIN[55], GOUT[55] ); smblock2a d256 (PIN[24], GIN[24], GIN[56], GOUT[56] ); smblock2a d257 (PIN[25], GIN[25], GIN[57], GOUT[57] ); smblock2a d258 (PIN[26], GIN[26], GIN[58], GOUT[58] ); smblock2a d259 (PIN[27], GIN[27], GIN[59], GOUT[59] ); smblock2a d260 (PIN[28], GIN[28], GIN[60], GOUT[60] ); smblock2a d261 (PIN[29], GIN[29], GIN[61], GOUT[61] ); smblock2a d262 (PIN[30], GIN[30], GIN[62], GOUT[62] ); smblock2a d263 (PIN[31], GIN[31], GIN[63], GOUT[63] ); endmodule module smdblc_6_128 (PIN, GIN, POUT, GOUT); input [63:0] PIN; input [63:0] GIN; output [0:0] POUT; output [63:0] GOUT; assign GOUT[63:0] = GIN[63:0]; endmodule module smboothcoder_34_34 (OPA, OPB, SUMMAND); input [33:0] OPA; input [33:0] OPB; output [628:0] SUMMAND; wire [33:0] OPA_; wire [67:0] INT_MULTIPLIER; wire LOGIC_ONE, LOGIC_ZERO; assign LOGIC_ONE = 1'b1; assign LOGIC_ZERO = 1'b0; smdecoder dDEC0 (.INA (LOGIC_ZERO), .INB (OPB[0]), .INC (OPB[1]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]) ); assign OPA_ = ~ OPA; smpp_low dPPL0 (.INA (OPA[0]), .INB (OPA_[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[0]) ); smr_gate dRGATE0 (.INA (LOGIC_ZERO), .INB (OPB[0]), .INC (OPB[1]), .PPBIT (SUMMAND[1]) ); smpp_middle dPPM0 (.INA (OPA[0]), .INB (OPA_[0]), .INC (OPA[1]), .IND (OPA_[1]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[2]) ); smpp_middle dPPM1 (.INA (OPA[1]), .INB (OPA_[1]), .INC (OPA[2]), .IND (OPA_[2]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[3]) ); smpp_middle dPPM2 (.INA (OPA[2]), .INB (OPA_[2]), .INC (OPA[3]), .IND (OPA_[3]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[6]) ); smpp_middle dPPM3 (.INA (OPA[3]), .INB (OPA_[3]), .INC (OPA[4]), .IND (OPA_[4]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[8]) ); smpp_middle dPPM4 (.INA (OPA[4]), .INB (OPA_[4]), .INC (OPA[5]), .IND (OPA_[5]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[12]) ); smpp_middle dPPM5 (.INA (OPA[5]), .INB (OPA_[5]), .INC (OPA[6]), .IND (OPA_[6]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[15]) ); smpp_middle dPPM6 (.INA (OPA[6]), .INB (OPA_[6]), .INC (OPA[7]), .IND (OPA_[7]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[20]) ); smpp_middle dPPM7 (.INA (OPA[7]), .INB (OPA_[7]), .INC (OPA[8]), .IND (OPA_[8]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[24]) ); smpp_middle dPPM8 (.INA (OPA[8]), .INB (OPA_[8]), .INC (OPA[9]), .IND (OPA_[9]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[30]) ); smpp_middle dPPM9 (.INA (OPA[9]), .INB (OPA_[9]), .INC (OPA[10]), .IND (OPA_[10]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[35]) ); smpp_middle dPPM10 (.INA (OPA[10]), .INB (OPA_[10]), .INC (OPA[11]), .IND (OPA_[11]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[42]) ); smpp_middle dPPM11 (.INA (OPA[11]), .INB (OPA_[11]), .INC (OPA[12]), .IND (OPA_[12]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[48]) ); smpp_middle dPPM12 (.INA (OPA[12]), .INB (OPA_[12]), .INC (OPA[13]), .IND (OPA_[13]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[56]) ); smpp_middle dPPM13 (.INA (OPA[13]), .INB (OPA_[13]), .INC (OPA[14]), .IND (OPA_[14]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[63]) ); smpp_middle dPPM14 (.INA (OPA[14]), .INB (OPA_[14]), .INC (OPA[15]), .IND (OPA_[15]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[72]) ); smpp_middle dPPM15 (.INA (OPA[15]), .INB (OPA_[15]), .INC (OPA[16]), .IND (OPA_[16]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[80]) ); smpp_middle dPPM16 (.INA (OPA[16]), .INB (OPA_[16]), .INC (OPA[17]), .IND (OPA_[17]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[90]) ); smpp_middle dPPM17 (.INA (OPA[17]), .INB (OPA_[17]), .INC (OPA[18]), .IND (OPA_[18]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[99]) ); smpp_middle dPPM18 (.INA (OPA[18]), .INB (OPA_[18]), .INC (OPA[19]), .IND (OPA_[19]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[110]) ); smpp_middle dPPM19 (.INA (OPA[19]), .INB (OPA_[19]), .INC (OPA[20]), .IND (OPA_[20]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[120]) ); smpp_middle dPPM20 (.INA (OPA[20]), .INB (OPA_[20]), .INC (OPA[21]), .IND (OPA_[21]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[132]) ); smpp_middle dPPM21 (.INA (OPA[21]), .INB (OPA_[21]), .INC (OPA[22]), .IND (OPA_[22]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[143]) ); smpp_middle dPPM22 (.INA (OPA[22]), .INB (OPA_[22]), .INC (OPA[23]), .IND (OPA_[23]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[156]) ); smpp_middle dPPM23 (.INA (OPA[23]), .INB (OPA_[23]), .INC (OPA[24]), .IND (OPA_[24]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[168]) ); smpp_middle dPPM24 (.INA (OPA[24]), .INB (OPA_[24]), .INC (OPA[25]), .IND (OPA_[25]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[182]) ); smpp_middle dPPM25 (.INA (OPA[25]), .INB (OPA_[25]), .INC (OPA[26]), .IND (OPA_[26]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[195]) ); smpp_middle dPPM26 (.INA (OPA[26]), .INB (OPA_[26]), .INC (OPA[27]), .IND (OPA_[27]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[210]) ); smpp_middle dPPM27 (.INA (OPA[27]), .INB (OPA_[27]), .INC (OPA[28]), .IND (OPA_[28]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[224]) ); smpp_middle dPPM28 (.INA (OPA[28]), .INB (OPA_[28]), .INC (OPA[29]), .IND (OPA_[29]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[240]) ); smpp_middle dPPM29 (.INA (OPA[29]), .INB (OPA_[29]), .INC (OPA[30]), .IND (OPA_[30]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[255]) ); smpp_middle dPPM30 (.INA (OPA[30]), .INB (OPA_[30]), .INC (OPA[31]), .IND (OPA_[31]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[272]) ); smpp_middle dPPM31 (.INA (OPA[31]), .INB (OPA_[31]), .INC (OPA[32]), .IND (OPA_[32]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[288]) ); smpp_middle dPPM32 (.INA (OPA[32]), .INB (OPA_[32]), .INC (OPA[33]), .IND (OPA_[33]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[306]) ); smpp_high dPPH0 (.INA (OPA[33]), .INB (OPA_[33]), .TWOPOS (INT_MULTIPLIER[0]), .TWONEG (INT_MULTIPLIER[1]), .ONEPOS (INT_MULTIPLIER[2]), .ONENEG (INT_MULTIPLIER[3]), .PPBIT (SUMMAND[323]) ); assign SUMMAND[324] = 1'b1; smdecoder dDEC1 (.INA (OPB[1]), .INB (OPB[2]), .INC (OPB[3]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]) ); smpp_low dPPL1 (.INA (OPA[0]), .INB (OPA_[0]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[4]) ); smr_gate dRGATE1 (.INA (OPB[1]), .INB (OPB[2]), .INC (OPB[3]), .PPBIT (SUMMAND[5]) ); smpp_middle dPPM33 (.INA (OPA[0]), .INB (OPA_[0]), .INC (OPA[1]), .IND (OPA_[1]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[7]) ); smpp_middle dPPM34 (.INA (OPA[1]), .INB (OPA_[1]), .INC (OPA[2]), .IND (OPA_[2]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[9]) ); smpp_middle dPPM35 (.INA (OPA[2]), .INB (OPA_[2]), .INC (OPA[3]), .IND (OPA_[3]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[13]) ); smpp_middle dPPM36 (.INA (OPA[3]), .INB (OPA_[3]), .INC (OPA[4]), .IND (OPA_[4]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[16]) ); smpp_middle dPPM37 (.INA (OPA[4]), .INB (OPA_[4]), .INC (OPA[5]), .IND (OPA_[5]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[21]) ); smpp_middle dPPM38 (.INA (OPA[5]), .INB (OPA_[5]), .INC (OPA[6]), .IND (OPA_[6]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[25]) ); smpp_middle dPPM39 (.INA (OPA[6]), .INB (OPA_[6]), .INC (OPA[7]), .IND (OPA_[7]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[31]) ); smpp_middle dPPM40 (.INA (OPA[7]), .INB (OPA_[7]), .INC (OPA[8]), .IND (OPA_[8]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[36]) ); smpp_middle dPPM41 (.INA (OPA[8]), .INB (OPA_[8]), .INC (OPA[9]), .IND (OPA_[9]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[43]) ); smpp_middle dPPM42 (.INA (OPA[9]), .INB (OPA_[9]), .INC (OPA[10]), .IND (OPA_[10]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[49]) ); smpp_middle dPPM43 (.INA (OPA[10]), .INB (OPA_[10]), .INC (OPA[11]), .IND (OPA_[11]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[57]) ); smpp_middle dPPM44 (.INA (OPA[11]), .INB (OPA_[11]), .INC (OPA[12]), .IND (OPA_[12]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[64]) ); smpp_middle dPPM45 (.INA (OPA[12]), .INB (OPA_[12]), .INC (OPA[13]), .IND (OPA_[13]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[73]) ); smpp_middle dPPM46 (.INA (OPA[13]), .INB (OPA_[13]), .INC (OPA[14]), .IND (OPA_[14]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[81]) ); smpp_middle dPPM47 (.INA (OPA[14]), .INB (OPA_[14]), .INC (OPA[15]), .IND (OPA_[15]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[91]) ); smpp_middle dPPM48 (.INA (OPA[15]), .INB (OPA_[15]), .INC (OPA[16]), .IND (OPA_[16]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[100]) ); smpp_middle dPPM49 (.INA (OPA[16]), .INB (OPA_[16]), .INC (OPA[17]), .IND (OPA_[17]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[111]) ); smpp_middle dPPM50 (.INA (OPA[17]), .INB (OPA_[17]), .INC (OPA[18]), .IND (OPA_[18]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[121]) ); smpp_middle dPPM51 (.INA (OPA[18]), .INB (OPA_[18]), .INC (OPA[19]), .IND (OPA_[19]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[133]) ); smpp_middle dPPM52 (.INA (OPA[19]), .INB (OPA_[19]), .INC (OPA[20]), .IND (OPA_[20]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[144]) ); smpp_middle dPPM53 (.INA (OPA[20]), .INB (OPA_[20]), .INC (OPA[21]), .IND (OPA_[21]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[157]) ); smpp_middle dPPM54 (.INA (OPA[21]), .INB (OPA_[21]), .INC (OPA[22]), .IND (OPA_[22]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[169]) ); smpp_middle dPPM55 (.INA (OPA[22]), .INB (OPA_[22]), .INC (OPA[23]), .IND (OPA_[23]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[183]) ); smpp_middle dPPM56 (.INA (OPA[23]), .INB (OPA_[23]), .INC (OPA[24]), .IND (OPA_[24]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[196]) ); smpp_middle dPPM57 (.INA (OPA[24]), .INB (OPA_[24]), .INC (OPA[25]), .IND (OPA_[25]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[211]) ); smpp_middle dPPM58 (.INA (OPA[25]), .INB (OPA_[25]), .INC (OPA[26]), .IND (OPA_[26]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[225]) ); smpp_middle dPPM59 (.INA (OPA[26]), .INB (OPA_[26]), .INC (OPA[27]), .IND (OPA_[27]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[241]) ); smpp_middle dPPM60 (.INA (OPA[27]), .INB (OPA_[27]), .INC (OPA[28]), .IND (OPA_[28]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[256]) ); smpp_middle dPPM61 (.INA (OPA[28]), .INB (OPA_[28]), .INC (OPA[29]), .IND (OPA_[29]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[273]) ); smpp_middle dPPM62 (.INA (OPA[29]), .INB (OPA_[29]), .INC (OPA[30]), .IND (OPA_[30]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[289]) ); smpp_middle dPPM63 (.INA (OPA[30]), .INB (OPA_[30]), .INC (OPA[31]), .IND (OPA_[31]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[307]) ); smpp_middle dPPM64 (.INA (OPA[31]), .INB (OPA_[31]), .INC (OPA[32]), .IND (OPA_[32]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[325]) ); smpp_middle dPPM65 (.INA (OPA[32]), .INB (OPA_[32]), .INC (OPA[33]), .IND (OPA_[33]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[341]) ); assign SUMMAND[342] = LOGIC_ONE; smpp_high dPPH1 (.INA (OPA[33]), .INB (OPA_[33]), .TWOPOS (INT_MULTIPLIER[4]), .TWONEG (INT_MULTIPLIER[5]), .ONEPOS (INT_MULTIPLIER[6]), .ONENEG (INT_MULTIPLIER[7]), .PPBIT (SUMMAND[358]) ); smdecoder dDEC2 (.INA (OPB[3]), .INB (OPB[4]), .INC (OPB[5]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]) ); smpp_low dPPL2 (.INA (OPA[0]), .INB (OPA_[0]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[10]) ); smr_gate dRGATE2 (.INA (OPB[3]), .INB (OPB[4]), .INC (OPB[5]), .PPBIT (SUMMAND[11]) ); smpp_middle dPPM66 (.INA (OPA[0]), .INB (OPA_[0]), .INC (OPA[1]), .IND (OPA_[1]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[14]) ); smpp_middle dPPM67 (.INA (OPA[1]), .INB (OPA_[1]), .INC (OPA[2]), .IND (OPA_[2]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[17]) ); smpp_middle dPPM68 (.INA (OPA[2]), .INB (OPA_[2]), .INC (OPA[3]), .IND (OPA_[3]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[22]) ); smpp_middle dPPM69 (.INA (OPA[3]), .INB (OPA_[3]), .INC (OPA[4]), .IND (OPA_[4]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[26]) ); smpp_middle dPPM70 (.INA (OPA[4]), .INB (OPA_[4]), .INC (OPA[5]), .IND (OPA_[5]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[32]) ); smpp_middle dPPM71 (.INA (OPA[5]), .INB (OPA_[5]), .INC (OPA[6]), .IND (OPA_[6]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[37]) ); smpp_middle dPPM72 (.INA (OPA[6]), .INB (OPA_[6]), .INC (OPA[7]), .IND (OPA_[7]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[44]) ); smpp_middle dPPM73 (.INA (OPA[7]), .INB (OPA_[7]), .INC (OPA[8]), .IND (OPA_[8]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[50]) ); smpp_middle dPPM74 (.INA (OPA[8]), .INB (OPA_[8]), .INC (OPA[9]), .IND (OPA_[9]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[58]) ); smpp_middle dPPM75 (.INA (OPA[9]), .INB (OPA_[9]), .INC (OPA[10]), .IND (OPA_[10]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[65]) ); smpp_middle dPPM76 (.INA (OPA[10]), .INB (OPA_[10]), .INC (OPA[11]), .IND (OPA_[11]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[74]) ); smpp_middle dPPM77 (.INA (OPA[11]), .INB (OPA_[11]), .INC (OPA[12]), .IND (OPA_[12]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[82]) ); smpp_middle dPPM78 (.INA (OPA[12]), .INB (OPA_[12]), .INC (OPA[13]), .IND (OPA_[13]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[92]) ); smpp_middle dPPM79 (.INA (OPA[13]), .INB (OPA_[13]), .INC (OPA[14]), .IND (OPA_[14]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[101]) ); smpp_middle dPPM80 (.INA (OPA[14]), .INB (OPA_[14]), .INC (OPA[15]), .IND (OPA_[15]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[112]) ); smpp_middle dPPM81 (.INA (OPA[15]), .INB (OPA_[15]), .INC (OPA[16]), .IND (OPA_[16]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[122]) ); smpp_middle dPPM82 (.INA (OPA[16]), .INB (OPA_[16]), .INC (OPA[17]), .IND (OPA_[17]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[134]) ); smpp_middle dPPM83 (.INA (OPA[17]), .INB (OPA_[17]), .INC (OPA[18]), .IND (OPA_[18]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[145]) ); smpp_middle dPPM84 (.INA (OPA[18]), .INB (OPA_[18]), .INC (OPA[19]), .IND (OPA_[19]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[158]) ); smpp_middle dPPM85 (.INA (OPA[19]), .INB (OPA_[19]), .INC (OPA[20]), .IND (OPA_[20]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[170]) ); smpp_middle dPPM86 (.INA (OPA[20]), .INB (OPA_[20]), .INC (OPA[21]), .IND (OPA_[21]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[184]) ); smpp_middle dPPM87 (.INA (OPA[21]), .INB (OPA_[21]), .INC (OPA[22]), .IND (OPA_[22]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[197]) ); smpp_middle dPPM88 (.INA (OPA[22]), .INB (OPA_[22]), .INC (OPA[23]), .IND (OPA_[23]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[212]) ); smpp_middle dPPM89 (.INA (OPA[23]), .INB (OPA_[23]), .INC (OPA[24]), .IND (OPA_[24]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[226]) ); smpp_middle dPPM90 (.INA (OPA[24]), .INB (OPA_[24]), .INC (OPA[25]), .IND (OPA_[25]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[242]) ); smpp_middle dPPM91 (.INA (OPA[25]), .INB (OPA_[25]), .INC (OPA[26]), .IND (OPA_[26]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[257]) ); smpp_middle dPPM92 (.INA (OPA[26]), .INB (OPA_[26]), .INC (OPA[27]), .IND (OPA_[27]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[274]) ); smpp_middle dPPM93 (.INA (OPA[27]), .INB (OPA_[27]), .INC (OPA[28]), .IND (OPA_[28]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[290]) ); smpp_middle dPPM94 (.INA (OPA[28]), .INB (OPA_[28]), .INC (OPA[29]), .IND (OPA_[29]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[308]) ); smpp_middle dPPM95 (.INA (OPA[29]), .INB (OPA_[29]), .INC (OPA[30]), .IND (OPA_[30]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[326]) ); smpp_middle dPPM96 (.INA (OPA[30]), .INB (OPA_[30]), .INC (OPA[31]), .IND (OPA_[31]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[343]) ); smpp_middle dPPM97 (.INA (OPA[31]), .INB (OPA_[31]), .INC (OPA[32]), .IND (OPA_[32]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[359]) ); smpp_middle dPPM98 (.INA (OPA[32]), .INB (OPA_[32]), .INC (OPA[33]), .IND (OPA_[33]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[374]) ); assign SUMMAND[375] = LOGIC_ONE; smpp_high dPPH2 (.INA (OPA[33]), .INB (OPA_[33]), .TWOPOS (INT_MULTIPLIER[8]), .TWONEG (INT_MULTIPLIER[9]), .ONEPOS (INT_MULTIPLIER[10]), .ONENEG (INT_MULTIPLIER[11]), .PPBIT (SUMMAND[390]) ); smdecoder dDEC3 (.INA (OPB[5]), .INB (OPB[6]), .INC (OPB[7]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]) ); smpp_low dPPL3 (.INA (OPA[0]), .INB (OPA_[0]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[18]) ); smr_gate dRGATE3 (.INA (OPB[5]), .INB (OPB[6]), .INC (OPB[7]), .PPBIT (SUMMAND[19]) ); smpp_middle dPPM99 (.INA (OPA[0]), .INB (OPA_[0]), .INC (OPA[1]), .IND (OPA_[1]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[23]) ); smpp_middle dPPM100 (.INA (OPA[1]), .INB (OPA_[1]), .INC (OPA[2]), .IND (OPA_[2]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[27]) ); smpp_middle dPPM101 (.INA (OPA[2]), .INB (OPA_[2]), .INC (OPA[3]), .IND (OPA_[3]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[33]) ); smpp_middle dPPM102 (.INA (OPA[3]), .INB (OPA_[3]), .INC (OPA[4]), .IND (OPA_[4]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[38]) ); smpp_middle dPPM103 (.INA (OPA[4]), .INB (OPA_[4]), .INC (OPA[5]), .IND (OPA_[5]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[45]) ); smpp_middle dPPM104 (.INA (OPA[5]), .INB (OPA_[5]), .INC (OPA[6]), .IND (OPA_[6]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[51]) ); smpp_middle dPPM105 (.INA (OPA[6]), .INB (OPA_[6]), .INC (OPA[7]), .IND (OPA_[7]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[59]) ); smpp_middle dPPM106 (.INA (OPA[7]), .INB (OPA_[7]), .INC (OPA[8]), .IND (OPA_[8]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[66]) ); smpp_middle dPPM107 (.INA (OPA[8]), .INB (OPA_[8]), .INC (OPA[9]), .IND (OPA_[9]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[75]) ); smpp_middle dPPM108 (.INA (OPA[9]), .INB (OPA_[9]), .INC (OPA[10]), .IND (OPA_[10]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[83]) ); smpp_middle dPPM109 (.INA (OPA[10]), .INB (OPA_[10]), .INC (OPA[11]), .IND (OPA_[11]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[93]) ); smpp_middle dPPM110 (.INA (OPA[11]), .INB (OPA_[11]), .INC (OPA[12]), .IND (OPA_[12]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[102]) ); smpp_middle dPPM111 (.INA (OPA[12]), .INB (OPA_[12]), .INC (OPA[13]), .IND (OPA_[13]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[113]) ); smpp_middle dPPM112 (.INA (OPA[13]), .INB (OPA_[13]), .INC (OPA[14]), .IND (OPA_[14]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[123]) ); smpp_middle dPPM113 (.INA (OPA[14]), .INB (OPA_[14]), .INC (OPA[15]), .IND (OPA_[15]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[135]) ); smpp_middle dPPM114 (.INA (OPA[15]), .INB (OPA_[15]), .INC (OPA[16]), .IND (OPA_[16]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[146]) ); smpp_middle dPPM115 (.INA (OPA[16]), .INB (OPA_[16]), .INC (OPA[17]), .IND (OPA_[17]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[159]) ); smpp_middle dPPM116 (.INA (OPA[17]), .INB (OPA_[17]), .INC (OPA[18]), .IND (OPA_[18]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[171]) ); smpp_middle dPPM117 (.INA (OPA[18]), .INB (OPA_[18]), .INC (OPA[19]), .IND (OPA_[19]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[185]) ); smpp_middle dPPM118 (.INA (OPA[19]), .INB (OPA_[19]), .INC (OPA[20]), .IND (OPA_[20]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[198]) ); smpp_middle dPPM119 (.INA (OPA[20]), .INB (OPA_[20]), .INC (OPA[21]), .IND (OPA_[21]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[213]) ); smpp_middle dPPM120 (.INA (OPA[21]), .INB (OPA_[21]), .INC (OPA[22]), .IND (OPA_[22]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[227]) ); smpp_middle dPPM121 (.INA (OPA[22]), .INB (OPA_[22]), .INC (OPA[23]), .IND (OPA_[23]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[243]) ); smpp_middle dPPM122 (.INA (OPA[23]), .INB (OPA_[23]), .INC (OPA[24]), .IND (OPA_[24]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[258]) ); smpp_middle dPPM123 (.INA (OPA[24]), .INB (OPA_[24]), .INC (OPA[25]), .IND (OPA_[25]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[275]) ); smpp_middle dPPM124 (.INA (OPA[25]), .INB (OPA_[25]), .INC (OPA[26]), .IND (OPA_[26]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[291]) ); smpp_middle dPPM125 (.INA (OPA[26]), .INB (OPA_[26]), .INC (OPA[27]), .IND (OPA_[27]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[309]) ); smpp_middle dPPM126 (.INA (OPA[27]), .INB (OPA_[27]), .INC (OPA[28]), .IND (OPA_[28]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[327]) ); smpp_middle dPPM127 (.INA (OPA[28]), .INB (OPA_[28]), .INC (OPA[29]), .IND (OPA_[29]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[344]) ); smpp_middle dPPM128 (.INA (OPA[29]), .INB (OPA_[29]), .INC (OPA[30]), .IND (OPA_[30]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[360]) ); smpp_middle dPPM129 (.INA (OPA[30]), .INB (OPA_[30]), .INC (OPA[31]), .IND (OPA_[31]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[376]) ); smpp_middle dPPM130 (.INA (OPA[31]), .INB (OPA_[31]), .INC (OPA[32]), .IND (OPA_[32]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[391]) ); smpp_middle dPPM131 (.INA (OPA[32]), .INB (OPA_[32]), .INC (OPA[33]), .IND (OPA_[33]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[405]) ); assign SUMMAND[406] = LOGIC_ONE; smpp_high dPPH3 (.INA (OPA[33]), .INB (OPA_[33]), .TWOPOS (INT_MULTIPLIER[12]), .TWONEG (INT_MULTIPLIER[13]), .ONEPOS (INT_MULTIPLIER[14]), .ONENEG (INT_MULTIPLIER[15]), .PPBIT (SUMMAND[420]) ); smdecoder dDEC4 (.INA (OPB[7]), .INB (OPB[8]), .INC (OPB[9]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]) ); smpp_low dPPL4 (.INA (OPA[0]), .INB (OPA_[0]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[28]) ); smr_gate dRGATE4 (.INA (OPB[7]), .INB (OPB[8]), .INC (OPB[9]), .PPBIT (SUMMAND[29]) ); smpp_middle dPPM132 (.INA (OPA[0]), .INB (OPA_[0]), .INC (OPA[1]), .IND (OPA_[1]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[34]) ); smpp_middle dPPM133 (.INA (OPA[1]), .INB (OPA_[1]), .INC (OPA[2]), .IND (OPA_[2]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[39]) ); smpp_middle dPPM134 (.INA (OPA[2]), .INB (OPA_[2]), .INC (OPA[3]), .IND (OPA_[3]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[46]) ); smpp_middle dPPM135 (.INA (OPA[3]), .INB (OPA_[3]), .INC (OPA[4]), .IND (OPA_[4]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[52]) ); smpp_middle dPPM136 (.INA (OPA[4]), .INB (OPA_[4]), .INC (OPA[5]), .IND (OPA_[5]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[60]) ); smpp_middle dPPM137 (.INA (OPA[5]), .INB (OPA_[5]), .INC (OPA[6]), .IND (OPA_[6]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[67]) ); smpp_middle dPPM138 (.INA (OPA[6]), .INB (OPA_[6]), .INC (OPA[7]), .IND (OPA_[7]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[76]) ); smpp_middle dPPM139 (.INA (OPA[7]), .INB (OPA_[7]), .INC (OPA[8]), .IND (OPA_[8]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[84]) ); smpp_middle dPPM140 (.INA (OPA[8]), .INB (OPA_[8]), .INC (OPA[9]), .IND (OPA_[9]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[94]) ); smpp_middle dPPM141 (.INA (OPA[9]), .INB (OPA_[9]), .INC (OPA[10]), .IND (OPA_[10]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[103]) ); smpp_middle dPPM142 (.INA (OPA[10]), .INB (OPA_[10]), .INC (OPA[11]), .IND (OPA_[11]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[114]) ); smpp_middle dPPM143 (.INA (OPA[11]), .INB (OPA_[11]), .INC (OPA[12]), .IND (OPA_[12]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[124]) ); smpp_middle dPPM144 (.INA (OPA[12]), .INB (OPA_[12]), .INC (OPA[13]), .IND (OPA_[13]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[136]) ); smpp_middle dPPM145 (.INA (OPA[13]), .INB (OPA_[13]), .INC (OPA[14]), .IND (OPA_[14]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[147]) ); smpp_middle dPPM146 (.INA (OPA[14]), .INB (OPA_[14]), .INC (OPA[15]), .IND (OPA_[15]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[160]) ); smpp_middle dPPM147 (.INA (OPA[15]), .INB (OPA_[15]), .INC (OPA[16]), .IND (OPA_[16]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[172]) ); smpp_middle dPPM148 (.INA (OPA[16]), .INB (OPA_[16]), .INC (OPA[17]), .IND (OPA_[17]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[186]) ); smpp_middle dPPM149 (.INA (OPA[17]), .INB (OPA_[17]), .INC (OPA[18]), .IND (OPA_[18]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[199]) ); smpp_middle dPPM150 (.INA (OPA[18]), .INB (OPA_[18]), .INC (OPA[19]), .IND (OPA_[19]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[214]) ); smpp_middle dPPM151 (.INA (OPA[19]), .INB (OPA_[19]), .INC (OPA[20]), .IND (OPA_[20]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[228]) ); smpp_middle dPPM152 (.INA (OPA[20]), .INB (OPA_[20]), .INC (OPA[21]), .IND (OPA_[21]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[244]) ); smpp_middle dPPM153 (.INA (OPA[21]), .INB (OPA_[21]), .INC (OPA[22]), .IND (OPA_[22]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[259]) ); smpp_middle dPPM154 (.INA (OPA[22]), .INB (OPA_[22]), .INC (OPA[23]), .IND (OPA_[23]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[276]) ); smpp_middle dPPM155 (.INA (OPA[23]), .INB (OPA_[23]), .INC (OPA[24]), .IND (OPA_[24]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[292]) ); smpp_middle dPPM156 (.INA (OPA[24]), .INB (OPA_[24]), .INC (OPA[25]), .IND (OPA_[25]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[310]) ); smpp_middle dPPM157 (.INA (OPA[25]), .INB (OPA_[25]), .INC (OPA[26]), .IND (OPA_[26]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[328]) ); smpp_middle dPPM158 (.INA (OPA[26]), .INB (OPA_[26]), .INC (OPA[27]), .IND (OPA_[27]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[345]) ); smpp_middle dPPM159 (.INA (OPA[27]), .INB (OPA_[27]), .INC (OPA[28]), .IND (OPA_[28]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[361]) ); smpp_middle dPPM160 (.INA (OPA[28]), .INB (OPA_[28]), .INC (OPA[29]), .IND (OPA_[29]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[377]) ); smpp_middle dPPM161 (.INA (OPA[29]), .INB (OPA_[29]), .INC (OPA[30]), .IND (OPA_[30]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[392]) ); smpp_middle dPPM162 (.INA (OPA[30]), .INB (OPA_[30]), .INC (OPA[31]), .IND (OPA_[31]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[407]) ); smpp_middle dPPM163 (.INA (OPA[31]), .INB (OPA_[31]), .INC (OPA[32]), .IND (OPA_[32]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[421]) ); smpp_middle dPPM164 (.INA (OPA[32]), .INB (OPA_[32]), .INC (OPA[33]), .IND (OPA_[33]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[434]) ); assign SUMMAND[435] = LOGIC_ONE; smpp_high dPPH4 (.INA (OPA[33]), .INB (OPA_[33]), .TWOPOS (INT_MULTIPLIER[16]), .TWONEG (INT_MULTIPLIER[17]), .ONEPOS (INT_MULTIPLIER[18]), .ONENEG (INT_MULTIPLIER[19]), .PPBIT (SUMMAND[448]) ); smdecoder dDEC5 (.INA (OPB[9]), .INB (OPB[10]), .INC (OPB[11]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]) ); smpp_low dPPL5 (.INA (OPA[0]), .INB (OPA_[0]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[40]) ); smr_gate dRGATE5 (.INA (OPB[9]), .INB (OPB[10]), .INC (OPB[11]), .PPBIT (SUMMAND[41]) ); smpp_middle dPPM165 (.INA (OPA[0]), .INB (OPA_[0]), .INC (OPA[1]), .IND (OPA_[1]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[47]) ); smpp_middle dPPM166 (.INA (OPA[1]), .INB (OPA_[1]), .INC (OPA[2]), .IND (OPA_[2]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[53]) ); smpp_middle dPPM167 (.INA (OPA[2]), .INB (OPA_[2]), .INC (OPA[3]), .IND (OPA_[3]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[61]) ); smpp_middle dPPM168 (.INA (OPA[3]), .INB (OPA_[3]), .INC (OPA[4]), .IND (OPA_[4]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[68]) ); smpp_middle dPPM169 (.INA (OPA[4]), .INB (OPA_[4]), .INC (OPA[5]), .IND (OPA_[5]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[77]) ); smpp_middle dPPM170 (.INA (OPA[5]), .INB (OPA_[5]), .INC (OPA[6]), .IND (OPA_[6]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[85]) ); smpp_middle dPPM171 (.INA (OPA[6]), .INB (OPA_[6]), .INC (OPA[7]), .IND (OPA_[7]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[95]) ); smpp_middle dPPM172 (.INA (OPA[7]), .INB (OPA_[7]), .INC (OPA[8]), .IND (OPA_[8]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[104]) ); smpp_middle dPPM173 (.INA (OPA[8]), .INB (OPA_[8]), .INC (OPA[9]), .IND (OPA_[9]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[115]) ); smpp_middle dPPM174 (.INA (OPA[9]), .INB (OPA_[9]), .INC (OPA[10]), .IND (OPA_[10]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[125]) ); smpp_middle dPPM175 (.INA (OPA[10]), .INB (OPA_[10]), .INC (OPA[11]), .IND (OPA_[11]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[137]) ); smpp_middle dPPM176 (.INA (OPA[11]), .INB (OPA_[11]), .INC (OPA[12]), .IND (OPA_[12]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[148]) ); smpp_middle dPPM177 (.INA (OPA[12]), .INB (OPA_[12]), .INC (OPA[13]), .IND (OPA_[13]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[161]) ); smpp_middle dPPM178 (.INA (OPA[13]), .INB (OPA_[13]), .INC (OPA[14]), .IND (OPA_[14]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[173]) ); smpp_middle dPPM179 (.INA (OPA[14]), .INB (OPA_[14]), .INC (OPA[15]), .IND (OPA_[15]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[187]) ); smpp_middle dPPM180 (.INA (OPA[15]), .INB (OPA_[15]), .INC (OPA[16]), .IND (OPA_[16]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[200]) ); smpp_middle dPPM181 (.INA (OPA[16]), .INB (OPA_[16]), .INC (OPA[17]), .IND (OPA_[17]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[215]) ); smpp_middle dPPM182 (.INA (OPA[17]), .INB (OPA_[17]), .INC (OPA[18]), .IND (OPA_[18]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[229]) ); smpp_middle dPPM183 (.INA (OPA[18]), .INB (OPA_[18]), .INC (OPA[19]), .IND (OPA_[19]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[245]) ); smpp_middle dPPM184 (.INA (OPA[19]), .INB (OPA_[19]), .INC (OPA[20]), .IND (OPA_[20]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[260]) ); smpp_middle dPPM185 (.INA (OPA[20]), .INB (OPA_[20]), .INC (OPA[21]), .IND (OPA_[21]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[277]) ); smpp_middle dPPM186 (.INA (OPA[21]), .INB (OPA_[21]), .INC (OPA[22]), .IND (OPA_[22]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[293]) ); smpp_middle dPPM187 (.INA (OPA[22]), .INB (OPA_[22]), .INC (OPA[23]), .IND (OPA_[23]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[311]) ); smpp_middle dPPM188 (.INA (OPA[23]), .INB (OPA_[23]), .INC (OPA[24]), .IND (OPA_[24]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[329]) ); smpp_middle dPPM189 (.INA (OPA[24]), .INB (OPA_[24]), .INC (OPA[25]), .IND (OPA_[25]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[346]) ); smpp_middle dPPM190 (.INA (OPA[25]), .INB (OPA_[25]), .INC (OPA[26]), .IND (OPA_[26]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[362]) ); smpp_middle dPPM191 (.INA (OPA[26]), .INB (OPA_[26]), .INC (OPA[27]), .IND (OPA_[27]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[378]) ); smpp_middle dPPM192 (.INA (OPA[27]), .INB (OPA_[27]), .INC (OPA[28]), .IND (OPA_[28]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[393]) ); smpp_middle dPPM193 (.INA (OPA[28]), .INB (OPA_[28]), .INC (OPA[29]), .IND (OPA_[29]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[408]) ); smpp_middle dPPM194 (.INA (OPA[29]), .INB (OPA_[29]), .INC (OPA[30]), .IND (OPA_[30]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[422]) ); smpp_middle dPPM195 (.INA (OPA[30]), .INB (OPA_[30]), .INC (OPA[31]), .IND (OPA_[31]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[436]) ); smpp_middle dPPM196 (.INA (OPA[31]), .INB (OPA_[31]), .INC (OPA[32]), .IND (OPA_[32]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[449]) ); smpp_middle dPPM197 (.INA (OPA[32]), .INB (OPA_[32]), .INC (OPA[33]), .IND (OPA_[33]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[461]) ); assign SUMMAND[462] = LOGIC_ONE; smpp_high dPPH5 (.INA (OPA[33]), .INB (OPA_[33]), .TWOPOS (INT_MULTIPLIER[20]), .TWONEG (INT_MULTIPLIER[21]), .ONEPOS (INT_MULTIPLIER[22]), .ONENEG (INT_MULTIPLIER[23]), .PPBIT (SUMMAND[474]) ); smdecoder dDEC6 (.INA (OPB[11]), .INB (OPB[12]), .INC (OPB[13]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]) ); smpp_low dPPL6 (.INA (OPA[0]), .INB (OPA_[0]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[54]) ); smr_gate dRGATE6 (.INA (OPB[11]), .INB (OPB[12]), .INC (OPB[13]), .PPBIT (SUMMAND[55]) ); smpp_middle dPPM198 (.INA (OPA[0]), .INB (OPA_[0]), .INC (OPA[1]), .IND (OPA_[1]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[62]) ); smpp_middle dPPM199 (.INA (OPA[1]), .INB (OPA_[1]), .INC (OPA[2]), .IND (OPA_[2]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[69]) ); smpp_middle dPPM200 (.INA (OPA[2]), .INB (OPA_[2]), .INC (OPA[3]), .IND (OPA_[3]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[78]) ); smpp_middle dPPM201 (.INA (OPA[3]), .INB (OPA_[3]), .INC (OPA[4]), .IND (OPA_[4]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[86]) ); smpp_middle dPPM202 (.INA (OPA[4]), .INB (OPA_[4]), .INC (OPA[5]), .IND (OPA_[5]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[96]) ); smpp_middle dPPM203 (.INA (OPA[5]), .INB (OPA_[5]), .INC (OPA[6]), .IND (OPA_[6]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[105]) ); smpp_middle dPPM204 (.INA (OPA[6]), .INB (OPA_[6]), .INC (OPA[7]), .IND (OPA_[7]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[116]) ); smpp_middle dPPM205 (.INA (OPA[7]), .INB (OPA_[7]), .INC (OPA[8]), .IND (OPA_[8]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[126]) ); smpp_middle dPPM206 (.INA (OPA[8]), .INB (OPA_[8]), .INC (OPA[9]), .IND (OPA_[9]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[138]) ); smpp_middle dPPM207 (.INA (OPA[9]), .INB (OPA_[9]), .INC (OPA[10]), .IND (OPA_[10]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[149]) ); smpp_middle dPPM208 (.INA (OPA[10]), .INB (OPA_[10]), .INC (OPA[11]), .IND (OPA_[11]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[162]) ); smpp_middle dPPM209 (.INA (OPA[11]), .INB (OPA_[11]), .INC (OPA[12]), .IND (OPA_[12]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[174]) ); smpp_middle dPPM210 (.INA (OPA[12]), .INB (OPA_[12]), .INC (OPA[13]), .IND (OPA_[13]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[188]) ); smpp_middle dPPM211 (.INA (OPA[13]), .INB (OPA_[13]), .INC (OPA[14]), .IND (OPA_[14]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[201]) ); smpp_middle dPPM212 (.INA (OPA[14]), .INB (OPA_[14]), .INC (OPA[15]), .IND (OPA_[15]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[216]) ); smpp_middle dPPM213 (.INA (OPA[15]), .INB (OPA_[15]), .INC (OPA[16]), .IND (OPA_[16]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[230]) ); smpp_middle dPPM214 (.INA (OPA[16]), .INB (OPA_[16]), .INC (OPA[17]), .IND (OPA_[17]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[246]) ); smpp_middle dPPM215 (.INA (OPA[17]), .INB (OPA_[17]), .INC (OPA[18]), .IND (OPA_[18]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[261]) ); smpp_middle dPPM216 (.INA (OPA[18]), .INB (OPA_[18]), .INC (OPA[19]), .IND (OPA_[19]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[278]) ); smpp_middle dPPM217 (.INA (OPA[19]), .INB (OPA_[19]), .INC (OPA[20]), .IND (OPA_[20]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[294]) ); smpp_middle dPPM218 (.INA (OPA[20]), .INB (OPA_[20]), .INC (OPA[21]), .IND (OPA_[21]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[312]) ); smpp_middle dPPM219 (.INA (OPA[21]), .INB (OPA_[21]), .INC (OPA[22]), .IND (OPA_[22]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[330]) ); smpp_middle dPPM220 (.INA (OPA[22]), .INB (OPA_[22]), .INC (OPA[23]), .IND (OPA_[23]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[347]) ); smpp_middle dPPM221 (.INA (OPA[23]), .INB (OPA_[23]), .INC (OPA[24]), .IND (OPA_[24]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[363]) ); smpp_middle dPPM222 (.INA (OPA[24]), .INB (OPA_[24]), .INC (OPA[25]), .IND (OPA_[25]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[379]) ); smpp_middle dPPM223 (.INA (OPA[25]), .INB (OPA_[25]), .INC (OPA[26]), .IND (OPA_[26]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[394]) ); smpp_middle dPPM224 (.INA (OPA[26]), .INB (OPA_[26]), .INC (OPA[27]), .IND (OPA_[27]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[409]) ); smpp_middle dPPM225 (.INA (OPA[27]), .INB (OPA_[27]), .INC (OPA[28]), .IND (OPA_[28]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[423]) ); smpp_middle dPPM226 (.INA (OPA[28]), .INB (OPA_[28]), .INC (OPA[29]), .IND (OPA_[29]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[437]) ); smpp_middle dPPM227 (.INA (OPA[29]), .INB (OPA_[29]), .INC (OPA[30]), .IND (OPA_[30]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[450]) ); smpp_middle dPPM228 (.INA (OPA[30]), .INB (OPA_[30]), .INC (OPA[31]), .IND (OPA_[31]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[463]) ); smpp_middle dPPM229 (.INA (OPA[31]), .INB (OPA_[31]), .INC (OPA[32]), .IND (OPA_[32]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[475]) ); smpp_middle dPPM230 (.INA (OPA[32]), .INB (OPA_[32]), .INC (OPA[33]), .IND (OPA_[33]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[486]) ); assign SUMMAND[487] = LOGIC_ONE; smpp_high dPPH6 (.INA (OPA[33]), .INB (OPA_[33]), .TWOPOS (INT_MULTIPLIER[24]), .TWONEG (INT_MULTIPLIER[25]), .ONEPOS (INT_MULTIPLIER[26]), .ONENEG (INT_MULTIPLIER[27]), .PPBIT (SUMMAND[498]) ); smdecoder dDEC7 (.INA (OPB[13]), .INB (OPB[14]), .INC (OPB[15]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]) ); smpp_low dPPL7 (.INA (OPA[0]), .INB (OPA_[0]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[70]) ); smr_gate dRGATE7 (.INA (OPB[13]), .INB (OPB[14]), .INC (OPB[15]), .PPBIT (SUMMAND[71]) ); smpp_middle dPPM231 (.INA (OPA[0]), .INB (OPA_[0]), .INC (OPA[1]), .IND (OPA_[1]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[79]) ); smpp_middle dPPM232 (.INA (OPA[1]), .INB (OPA_[1]), .INC (OPA[2]), .IND (OPA_[2]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[87]) ); smpp_middle dPPM233 (.INA (OPA[2]), .INB (OPA_[2]), .INC (OPA[3]), .IND (OPA_[3]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[97]) ); smpp_middle dPPM234 (.INA (OPA[3]), .INB (OPA_[3]), .INC (OPA[4]), .IND (OPA_[4]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[106]) ); smpp_middle dPPM235 (.INA (OPA[4]), .INB (OPA_[4]), .INC (OPA[5]), .IND (OPA_[5]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[117]) ); smpp_middle dPPM236 (.INA (OPA[5]), .INB (OPA_[5]), .INC (OPA[6]), .IND (OPA_[6]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[127]) ); smpp_middle dPPM237 (.INA (OPA[6]), .INB (OPA_[6]), .INC (OPA[7]), .IND (OPA_[7]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[139]) ); smpp_middle dPPM238 (.INA (OPA[7]), .INB (OPA_[7]), .INC (OPA[8]), .IND (OPA_[8]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[150]) ); smpp_middle dPPM239 (.INA (OPA[8]), .INB (OPA_[8]), .INC (OPA[9]), .IND (OPA_[9]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[163]) ); smpp_middle dPPM240 (.INA (OPA[9]), .INB (OPA_[9]), .INC (OPA[10]), .IND (OPA_[10]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[175]) ); smpp_middle dPPM241 (.INA (OPA[10]), .INB (OPA_[10]), .INC (OPA[11]), .IND (OPA_[11]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[189]) ); smpp_middle dPPM242 (.INA (OPA[11]), .INB (OPA_[11]), .INC (OPA[12]), .IND (OPA_[12]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[202]) ); smpp_middle dPPM243 (.INA (OPA[12]), .INB (OPA_[12]), .INC (OPA[13]), .IND (OPA_[13]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[217]) ); smpp_middle dPPM244 (.INA (OPA[13]), .INB (OPA_[13]), .INC (OPA[14]), .IND (OPA_[14]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[231]) ); smpp_middle dPPM245 (.INA (OPA[14]), .INB (OPA_[14]), .INC (OPA[15]), .IND (OPA_[15]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[247]) ); smpp_middle dPPM246 (.INA (OPA[15]), .INB (OPA_[15]), .INC (OPA[16]), .IND (OPA_[16]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[262]) ); smpp_middle dPPM247 (.INA (OPA[16]), .INB (OPA_[16]), .INC (OPA[17]), .IND (OPA_[17]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[279]) ); smpp_middle dPPM248 (.INA (OPA[17]), .INB (OPA_[17]), .INC (OPA[18]), .IND (OPA_[18]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[295]) ); smpp_middle dPPM249 (.INA (OPA[18]), .INB (OPA_[18]), .INC (OPA[19]), .IND (OPA_[19]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[313]) ); smpp_middle dPPM250 (.INA (OPA[19]), .INB (OPA_[19]), .INC (OPA[20]), .IND (OPA_[20]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[331]) ); smpp_middle dPPM251 (.INA (OPA[20]), .INB (OPA_[20]), .INC (OPA[21]), .IND (OPA_[21]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[348]) ); smpp_middle dPPM252 (.INA (OPA[21]), .INB (OPA_[21]), .INC (OPA[22]), .IND (OPA_[22]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[364]) ); smpp_middle dPPM253 (.INA (OPA[22]), .INB (OPA_[22]), .INC (OPA[23]), .IND (OPA_[23]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[380]) ); smpp_middle dPPM254 (.INA (OPA[23]), .INB (OPA_[23]), .INC (OPA[24]), .IND (OPA_[24]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[395]) ); smpp_middle dPPM255 (.INA (OPA[24]), .INB (OPA_[24]), .INC (OPA[25]), .IND (OPA_[25]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[410]) ); smpp_middle dPPM256 (.INA (OPA[25]), .INB (OPA_[25]), .INC (OPA[26]), .IND (OPA_[26]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[424]) ); smpp_middle dPPM257 (.INA (OPA[26]), .INB (OPA_[26]), .INC (OPA[27]), .IND (OPA_[27]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[438]) ); smpp_middle dPPM258 (.INA (OPA[27]), .INB (OPA_[27]), .INC (OPA[28]), .IND (OPA_[28]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[451]) ); smpp_middle dPPM259 (.INA (OPA[28]), .INB (OPA_[28]), .INC (OPA[29]), .IND (OPA_[29]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[464]) ); smpp_middle dPPM260 (.INA (OPA[29]), .INB (OPA_[29]), .INC (OPA[30]), .IND (OPA_[30]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[476]) ); smpp_middle dPPM261 (.INA (OPA[30]), .INB (OPA_[30]), .INC (OPA[31]), .IND (OPA_[31]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[488]) ); smpp_middle dPPM262 (.INA (OPA[31]), .INB (OPA_[31]), .INC (OPA[32]), .IND (OPA_[32]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[499]) ); smpp_middle dPPM263 (.INA (OPA[32]), .INB (OPA_[32]), .INC (OPA[33]), .IND (OPA_[33]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[509]) ); assign SUMMAND[510] = LOGIC_ONE; smpp_high dPPH7 (.INA (OPA[33]), .INB (OPA_[33]), .TWOPOS (INT_MULTIPLIER[28]), .TWONEG (INT_MULTIPLIER[29]), .ONEPOS (INT_MULTIPLIER[30]), .ONENEG (INT_MULTIPLIER[31]), .PPBIT (SUMMAND[520]) ); smdecoder dDEC8 (.INA (OPB[15]), .INB (OPB[16]), .INC (OPB[17]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]) ); smpp_low dPPL8 (.INA (OPA[0]), .INB (OPA_[0]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[88]) ); smr_gate dRGATE8 (.INA (OPB[15]), .INB (OPB[16]), .INC (OPB[17]), .PPBIT (SUMMAND[89]) ); smpp_middle dPPM264 (.INA (OPA[0]), .INB (OPA_[0]), .INC (OPA[1]), .IND (OPA_[1]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[98]) ); smpp_middle dPPM265 (.INA (OPA[1]), .INB (OPA_[1]), .INC (OPA[2]), .IND (OPA_[2]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[107]) ); smpp_middle dPPM266 (.INA (OPA[2]), .INB (OPA_[2]), .INC (OPA[3]), .IND (OPA_[3]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[118]) ); smpp_middle dPPM267 (.INA (OPA[3]), .INB (OPA_[3]), .INC (OPA[4]), .IND (OPA_[4]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[128]) ); smpp_middle dPPM268 (.INA (OPA[4]), .INB (OPA_[4]), .INC (OPA[5]), .IND (OPA_[5]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[140]) ); smpp_middle dPPM269 (.INA (OPA[5]), .INB (OPA_[5]), .INC (OPA[6]), .IND (OPA_[6]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[151]) ); smpp_middle dPPM270 (.INA (OPA[6]), .INB (OPA_[6]), .INC (OPA[7]), .IND (OPA_[7]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[164]) ); smpp_middle dPPM271 (.INA (OPA[7]), .INB (OPA_[7]), .INC (OPA[8]), .IND (OPA_[8]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[176]) ); smpp_middle dPPM272 (.INA (OPA[8]), .INB (OPA_[8]), .INC (OPA[9]), .IND (OPA_[9]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[190]) ); smpp_middle dPPM273 (.INA (OPA[9]), .INB (OPA_[9]), .INC (OPA[10]), .IND (OPA_[10]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[203]) ); smpp_middle dPPM274 (.INA (OPA[10]), .INB (OPA_[10]), .INC (OPA[11]), .IND (OPA_[11]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[218]) ); smpp_middle dPPM275 (.INA (OPA[11]), .INB (OPA_[11]), .INC (OPA[12]), .IND (OPA_[12]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[232]) ); smpp_middle dPPM276 (.INA (OPA[12]), .INB (OPA_[12]), .INC (OPA[13]), .IND (OPA_[13]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[248]) ); smpp_middle dPPM277 (.INA (OPA[13]), .INB (OPA_[13]), .INC (OPA[14]), .IND (OPA_[14]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[263]) ); smpp_middle dPPM278 (.INA (OPA[14]), .INB (OPA_[14]), .INC (OPA[15]), .IND (OPA_[15]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[280]) ); smpp_middle dPPM279 (.INA (OPA[15]), .INB (OPA_[15]), .INC (OPA[16]), .IND (OPA_[16]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[296]) ); smpp_middle dPPM280 (.INA (OPA[16]), .INB (OPA_[16]), .INC (OPA[17]), .IND (OPA_[17]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[314]) ); smpp_middle dPPM281 (.INA (OPA[17]), .INB (OPA_[17]), .INC (OPA[18]), .IND (OPA_[18]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[332]) ); smpp_middle dPPM282 (.INA (OPA[18]), .INB (OPA_[18]), .INC (OPA[19]), .IND (OPA_[19]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[349]) ); smpp_middle dPPM283 (.INA (OPA[19]), .INB (OPA_[19]), .INC (OPA[20]), .IND (OPA_[20]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[365]) ); smpp_middle dPPM284 (.INA (OPA[20]), .INB (OPA_[20]), .INC (OPA[21]), .IND (OPA_[21]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[381]) ); smpp_middle dPPM285 (.INA (OPA[21]), .INB (OPA_[21]), .INC (OPA[22]), .IND (OPA_[22]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[396]) ); smpp_middle dPPM286 (.INA (OPA[22]), .INB (OPA_[22]), .INC (OPA[23]), .IND (OPA_[23]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[411]) ); smpp_middle dPPM287 (.INA (OPA[23]), .INB (OPA_[23]), .INC (OPA[24]), .IND (OPA_[24]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[425]) ); smpp_middle dPPM288 (.INA (OPA[24]), .INB (OPA_[24]), .INC (OPA[25]), .IND (OPA_[25]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[439]) ); smpp_middle dPPM289 (.INA (OPA[25]), .INB (OPA_[25]), .INC (OPA[26]), .IND (OPA_[26]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[452]) ); smpp_middle dPPM290 (.INA (OPA[26]), .INB (OPA_[26]), .INC (OPA[27]), .IND (OPA_[27]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[465]) ); smpp_middle dPPM291 (.INA (OPA[27]), .INB (OPA_[27]), .INC (OPA[28]), .IND (OPA_[28]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[477]) ); smpp_middle dPPM292 (.INA (OPA[28]), .INB (OPA_[28]), .INC (OPA[29]), .IND (OPA_[29]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[489]) ); smpp_middle dPPM293 (.INA (OPA[29]), .INB (OPA_[29]), .INC (OPA[30]), .IND (OPA_[30]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[500]) ); smpp_middle dPPM294 (.INA (OPA[30]), .INB (OPA_[30]), .INC (OPA[31]), .IND (OPA_[31]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[511]) ); smpp_middle dPPM295 (.INA (OPA[31]), .INB (OPA_[31]), .INC (OPA[32]), .IND (OPA_[32]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[521]) ); smpp_middle dPPM296 (.INA (OPA[32]), .INB (OPA_[32]), .INC (OPA[33]), .IND (OPA_[33]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[530]) ); assign SUMMAND[531] = LOGIC_ONE; smpp_high dPPH8 (.INA (OPA[33]), .INB (OPA_[33]), .TWOPOS (INT_MULTIPLIER[32]), .TWONEG (INT_MULTIPLIER[33]), .ONEPOS (INT_MULTIPLIER[34]), .ONENEG (INT_MULTIPLIER[35]), .PPBIT (SUMMAND[540]) ); smdecoder dDEC9 (.INA (OPB[17]), .INB (OPB[18]), .INC (OPB[19]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]) ); smpp_low dPPL9 (.INA (OPA[0]), .INB (OPA_[0]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[108]) ); smr_gate dRGATE9 (.INA (OPB[17]), .INB (OPB[18]), .INC (OPB[19]), .PPBIT (SUMMAND[109]) ); smpp_middle dPPM297 (.INA (OPA[0]), .INB (OPA_[0]), .INC (OPA[1]), .IND (OPA_[1]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[119]) ); smpp_middle dPPM298 (.INA (OPA[1]), .INB (OPA_[1]), .INC (OPA[2]), .IND (OPA_[2]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[129]) ); smpp_middle dPPM299 (.INA (OPA[2]), .INB (OPA_[2]), .INC (OPA[3]), .IND (OPA_[3]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[141]) ); smpp_middle dPPM300 (.INA (OPA[3]), .INB (OPA_[3]), .INC (OPA[4]), .IND (OPA_[4]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[152]) ); smpp_middle dPPM301 (.INA (OPA[4]), .INB (OPA_[4]), .INC (OPA[5]), .IND (OPA_[5]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[165]) ); smpp_middle dPPM302 (.INA (OPA[5]), .INB (OPA_[5]), .INC (OPA[6]), .IND (OPA_[6]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[177]) ); smpp_middle dPPM303 (.INA (OPA[6]), .INB (OPA_[6]), .INC (OPA[7]), .IND (OPA_[7]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[191]) ); smpp_middle dPPM304 (.INA (OPA[7]), .INB (OPA_[7]), .INC (OPA[8]), .IND (OPA_[8]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[204]) ); smpp_middle dPPM305 (.INA (OPA[8]), .INB (OPA_[8]), .INC (OPA[9]), .IND (OPA_[9]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[219]) ); smpp_middle dPPM306 (.INA (OPA[9]), .INB (OPA_[9]), .INC (OPA[10]), .IND (OPA_[10]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[233]) ); smpp_middle dPPM307 (.INA (OPA[10]), .INB (OPA_[10]), .INC (OPA[11]), .IND (OPA_[11]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[249]) ); smpp_middle dPPM308 (.INA (OPA[11]), .INB (OPA_[11]), .INC (OPA[12]), .IND (OPA_[12]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[264]) ); smpp_middle dPPM309 (.INA (OPA[12]), .INB (OPA_[12]), .INC (OPA[13]), .IND (OPA_[13]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[281]) ); smpp_middle dPPM310 (.INA (OPA[13]), .INB (OPA_[13]), .INC (OPA[14]), .IND (OPA_[14]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[297]) ); smpp_middle dPPM311 (.INA (OPA[14]), .INB (OPA_[14]), .INC (OPA[15]), .IND (OPA_[15]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[315]) ); smpp_middle dPPM312 (.INA (OPA[15]), .INB (OPA_[15]), .INC (OPA[16]), .IND (OPA_[16]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[333]) ); smpp_middle dPPM313 (.INA (OPA[16]), .INB (OPA_[16]), .INC (OPA[17]), .IND (OPA_[17]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[350]) ); smpp_middle dPPM314 (.INA (OPA[17]), .INB (OPA_[17]), .INC (OPA[18]), .IND (OPA_[18]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[366]) ); smpp_middle dPPM315 (.INA (OPA[18]), .INB (OPA_[18]), .INC (OPA[19]), .IND (OPA_[19]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[382]) ); smpp_middle dPPM316 (.INA (OPA[19]), .INB (OPA_[19]), .INC (OPA[20]), .IND (OPA_[20]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[397]) ); smpp_middle dPPM317 (.INA (OPA[20]), .INB (OPA_[20]), .INC (OPA[21]), .IND (OPA_[21]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[412]) ); smpp_middle dPPM318 (.INA (OPA[21]), .INB (OPA_[21]), .INC (OPA[22]), .IND (OPA_[22]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[426]) ); smpp_middle dPPM319 (.INA (OPA[22]), .INB (OPA_[22]), .INC (OPA[23]), .IND (OPA_[23]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[440]) ); smpp_middle dPPM320 (.INA (OPA[23]), .INB (OPA_[23]), .INC (OPA[24]), .IND (OPA_[24]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[453]) ); smpp_middle dPPM321 (.INA (OPA[24]), .INB (OPA_[24]), .INC (OPA[25]), .IND (OPA_[25]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[466]) ); smpp_middle dPPM322 (.INA (OPA[25]), .INB (OPA_[25]), .INC (OPA[26]), .IND (OPA_[26]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[478]) ); smpp_middle dPPM323 (.INA (OPA[26]), .INB (OPA_[26]), .INC (OPA[27]), .IND (OPA_[27]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[490]) ); smpp_middle dPPM324 (.INA (OPA[27]), .INB (OPA_[27]), .INC (OPA[28]), .IND (OPA_[28]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[501]) ); smpp_middle dPPM325 (.INA (OPA[28]), .INB (OPA_[28]), .INC (OPA[29]), .IND (OPA_[29]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[512]) ); smpp_middle dPPM326 (.INA (OPA[29]), .INB (OPA_[29]), .INC (OPA[30]), .IND (OPA_[30]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[522]) ); smpp_middle dPPM327 (.INA (OPA[30]), .INB (OPA_[30]), .INC (OPA[31]), .IND (OPA_[31]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[532]) ); smpp_middle dPPM328 (.INA (OPA[31]), .INB (OPA_[31]), .INC (OPA[32]), .IND (OPA_[32]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[541]) ); smpp_middle dPPM329 (.INA (OPA[32]), .INB (OPA_[32]), .INC (OPA[33]), .IND (OPA_[33]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[549]) ); assign SUMMAND[550] = LOGIC_ONE; smpp_high dPPH9 (.INA (OPA[33]), .INB (OPA_[33]), .TWOPOS (INT_MULTIPLIER[36]), .TWONEG (INT_MULTIPLIER[37]), .ONEPOS (INT_MULTIPLIER[38]), .ONENEG (INT_MULTIPLIER[39]), .PPBIT (SUMMAND[558]) ); smdecoder dDEC10 (.INA (OPB[19]), .INB (OPB[20]), .INC (OPB[21]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]) ); smpp_low dPPL10 (.INA (OPA[0]), .INB (OPA_[0]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[130]) ); smr_gate dRGATE10 (.INA (OPB[19]), .INB (OPB[20]), .INC (OPB[21]), .PPBIT (SUMMAND[131]) ); smpp_middle dPPM330 (.INA (OPA[0]), .INB (OPA_[0]), .INC (OPA[1]), .IND (OPA_[1]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[142]) ); smpp_middle dPPM331 (.INA (OPA[1]), .INB (OPA_[1]), .INC (OPA[2]), .IND (OPA_[2]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[153]) ); smpp_middle dPPM332 (.INA (OPA[2]), .INB (OPA_[2]), .INC (OPA[3]), .IND (OPA_[3]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[166]) ); smpp_middle dPPM333 (.INA (OPA[3]), .INB (OPA_[3]), .INC (OPA[4]), .IND (OPA_[4]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[178]) ); smpp_middle dPPM334 (.INA (OPA[4]), .INB (OPA_[4]), .INC (OPA[5]), .IND (OPA_[5]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[192]) ); smpp_middle dPPM335 (.INA (OPA[5]), .INB (OPA_[5]), .INC (OPA[6]), .IND (OPA_[6]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[205]) ); smpp_middle dPPM336 (.INA (OPA[6]), .INB (OPA_[6]), .INC (OPA[7]), .IND (OPA_[7]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[220]) ); smpp_middle dPPM337 (.INA (OPA[7]), .INB (OPA_[7]), .INC (OPA[8]), .IND (OPA_[8]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[234]) ); smpp_middle dPPM338 (.INA (OPA[8]), .INB (OPA_[8]), .INC (OPA[9]), .IND (OPA_[9]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[250]) ); smpp_middle dPPM339 (.INA (OPA[9]), .INB (OPA_[9]), .INC (OPA[10]), .IND (OPA_[10]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[265]) ); smpp_middle dPPM340 (.INA (OPA[10]), .INB (OPA_[10]), .INC (OPA[11]), .IND (OPA_[11]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[282]) ); smpp_middle dPPM341 (.INA (OPA[11]), .INB (OPA_[11]), .INC (OPA[12]), .IND (OPA_[12]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[298]) ); smpp_middle dPPM342 (.INA (OPA[12]), .INB (OPA_[12]), .INC (OPA[13]), .IND (OPA_[13]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[316]) ); smpp_middle dPPM343 (.INA (OPA[13]), .INB (OPA_[13]), .INC (OPA[14]), .IND (OPA_[14]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[334]) ); smpp_middle dPPM344 (.INA (OPA[14]), .INB (OPA_[14]), .INC (OPA[15]), .IND (OPA_[15]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[351]) ); smpp_middle dPPM345 (.INA (OPA[15]), .INB (OPA_[15]), .INC (OPA[16]), .IND (OPA_[16]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[367]) ); smpp_middle dPPM346 (.INA (OPA[16]), .INB (OPA_[16]), .INC (OPA[17]), .IND (OPA_[17]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[383]) ); smpp_middle dPPM347 (.INA (OPA[17]), .INB (OPA_[17]), .INC (OPA[18]), .IND (OPA_[18]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[398]) ); smpp_middle dPPM348 (.INA (OPA[18]), .INB (OPA_[18]), .INC (OPA[19]), .IND (OPA_[19]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[413]) ); smpp_middle dPPM349 (.INA (OPA[19]), .INB (OPA_[19]), .INC (OPA[20]), .IND (OPA_[20]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[427]) ); smpp_middle dPPM350 (.INA (OPA[20]), .INB (OPA_[20]), .INC (OPA[21]), .IND (OPA_[21]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[441]) ); smpp_middle dPPM351 (.INA (OPA[21]), .INB (OPA_[21]), .INC (OPA[22]), .IND (OPA_[22]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[454]) ); smpp_middle dPPM352 (.INA (OPA[22]), .INB (OPA_[22]), .INC (OPA[23]), .IND (OPA_[23]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[467]) ); smpp_middle dPPM353 (.INA (OPA[23]), .INB (OPA_[23]), .INC (OPA[24]), .IND (OPA_[24]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[479]) ); smpp_middle dPPM354 (.INA (OPA[24]), .INB (OPA_[24]), .INC (OPA[25]), .IND (OPA_[25]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[491]) ); smpp_middle dPPM355 (.INA (OPA[25]), .INB (OPA_[25]), .INC (OPA[26]), .IND (OPA_[26]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[502]) ); smpp_middle dPPM356 (.INA (OPA[26]), .INB (OPA_[26]), .INC (OPA[27]), .IND (OPA_[27]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[513]) ); smpp_middle dPPM357 (.INA (OPA[27]), .INB (OPA_[27]), .INC (OPA[28]), .IND (OPA_[28]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[523]) ); smpp_middle dPPM358 (.INA (OPA[28]), .INB (OPA_[28]), .INC (OPA[29]), .IND (OPA_[29]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[533]) ); smpp_middle dPPM359 (.INA (OPA[29]), .INB (OPA_[29]), .INC (OPA[30]), .IND (OPA_[30]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[542]) ); smpp_middle dPPM360 (.INA (OPA[30]), .INB (OPA_[30]), .INC (OPA[31]), .IND (OPA_[31]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[551]) ); smpp_middle dPPM361 (.INA (OPA[31]), .INB (OPA_[31]), .INC (OPA[32]), .IND (OPA_[32]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[559]) ); smpp_middle dPPM362 (.INA (OPA[32]), .INB (OPA_[32]), .INC (OPA[33]), .IND (OPA_[33]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[566]) ); assign SUMMAND[567] = LOGIC_ONE; smpp_high dPPH10 (.INA (OPA[33]), .INB (OPA_[33]), .TWOPOS (INT_MULTIPLIER[40]), .TWONEG (INT_MULTIPLIER[41]), .ONEPOS (INT_MULTIPLIER[42]), .ONENEG (INT_MULTIPLIER[43]), .PPBIT (SUMMAND[574]) ); smdecoder dDEC11 (.INA (OPB[21]), .INB (OPB[22]), .INC (OPB[23]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]) ); smpp_low dPPL11 (.INA (OPA[0]), .INB (OPA_[0]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[154]) ); smr_gate dRGATE11 (.INA (OPB[21]), .INB (OPB[22]), .INC (OPB[23]), .PPBIT (SUMMAND[155]) ); smpp_middle dPPM363 (.INA (OPA[0]), .INB (OPA_[0]), .INC (OPA[1]), .IND (OPA_[1]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[167]) ); smpp_middle dPPM364 (.INA (OPA[1]), .INB (OPA_[1]), .INC (OPA[2]), .IND (OPA_[2]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[179]) ); smpp_middle dPPM365 (.INA (OPA[2]), .INB (OPA_[2]), .INC (OPA[3]), .IND (OPA_[3]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[193]) ); smpp_middle dPPM366 (.INA (OPA[3]), .INB (OPA_[3]), .INC (OPA[4]), .IND (OPA_[4]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[206]) ); smpp_middle dPPM367 (.INA (OPA[4]), .INB (OPA_[4]), .INC (OPA[5]), .IND (OPA_[5]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[221]) ); smpp_middle dPPM368 (.INA (OPA[5]), .INB (OPA_[5]), .INC (OPA[6]), .IND (OPA_[6]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[235]) ); smpp_middle dPPM369 (.INA (OPA[6]), .INB (OPA_[6]), .INC (OPA[7]), .IND (OPA_[7]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[251]) ); smpp_middle dPPM370 (.INA (OPA[7]), .INB (OPA_[7]), .INC (OPA[8]), .IND (OPA_[8]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[266]) ); smpp_middle dPPM371 (.INA (OPA[8]), .INB (OPA_[8]), .INC (OPA[9]), .IND (OPA_[9]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[283]) ); smpp_middle dPPM372 (.INA (OPA[9]), .INB (OPA_[9]), .INC (OPA[10]), .IND (OPA_[10]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[299]) ); smpp_middle dPPM373 (.INA (OPA[10]), .INB (OPA_[10]), .INC (OPA[11]), .IND (OPA_[11]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[317]) ); smpp_middle dPPM374 (.INA (OPA[11]), .INB (OPA_[11]), .INC (OPA[12]), .IND (OPA_[12]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[335]) ); smpp_middle dPPM375 (.INA (OPA[12]), .INB (OPA_[12]), .INC (OPA[13]), .IND (OPA_[13]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[352]) ); smpp_middle dPPM376 (.INA (OPA[13]), .INB (OPA_[13]), .INC (OPA[14]), .IND (OPA_[14]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[368]) ); smpp_middle dPPM377 (.INA (OPA[14]), .INB (OPA_[14]), .INC (OPA[15]), .IND (OPA_[15]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[384]) ); smpp_middle dPPM378 (.INA (OPA[15]), .INB (OPA_[15]), .INC (OPA[16]), .IND (OPA_[16]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[399]) ); smpp_middle dPPM379 (.INA (OPA[16]), .INB (OPA_[16]), .INC (OPA[17]), .IND (OPA_[17]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[414]) ); smpp_middle dPPM380 (.INA (OPA[17]), .INB (OPA_[17]), .INC (OPA[18]), .IND (OPA_[18]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[428]) ); smpp_middle dPPM381 (.INA (OPA[18]), .INB (OPA_[18]), .INC (OPA[19]), .IND (OPA_[19]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[442]) ); smpp_middle dPPM382 (.INA (OPA[19]), .INB (OPA_[19]), .INC (OPA[20]), .IND (OPA_[20]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[455]) ); smpp_middle dPPM383 (.INA (OPA[20]), .INB (OPA_[20]), .INC (OPA[21]), .IND (OPA_[21]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[468]) ); smpp_middle dPPM384 (.INA (OPA[21]), .INB (OPA_[21]), .INC (OPA[22]), .IND (OPA_[22]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[480]) ); smpp_middle dPPM385 (.INA (OPA[22]), .INB (OPA_[22]), .INC (OPA[23]), .IND (OPA_[23]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[492]) ); smpp_middle dPPM386 (.INA (OPA[23]), .INB (OPA_[23]), .INC (OPA[24]), .IND (OPA_[24]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[503]) ); smpp_middle dPPM387 (.INA (OPA[24]), .INB (OPA_[24]), .INC (OPA[25]), .IND (OPA_[25]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[514]) ); smpp_middle dPPM388 (.INA (OPA[25]), .INB (OPA_[25]), .INC (OPA[26]), .IND (OPA_[26]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[524]) ); smpp_middle dPPM389 (.INA (OPA[26]), .INB (OPA_[26]), .INC (OPA[27]), .IND (OPA_[27]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[534]) ); smpp_middle dPPM390 (.INA (OPA[27]), .INB (OPA_[27]), .INC (OPA[28]), .IND (OPA_[28]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[543]) ); smpp_middle dPPM391 (.INA (OPA[28]), .INB (OPA_[28]), .INC (OPA[29]), .IND (OPA_[29]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[552]) ); smpp_middle dPPM392 (.INA (OPA[29]), .INB (OPA_[29]), .INC (OPA[30]), .IND (OPA_[30]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[560]) ); smpp_middle dPPM393 (.INA (OPA[30]), .INB (OPA_[30]), .INC (OPA[31]), .IND (OPA_[31]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[568]) ); smpp_middle dPPM394 (.INA (OPA[31]), .INB (OPA_[31]), .INC (OPA[32]), .IND (OPA_[32]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[575]) ); smpp_middle dPPM395 (.INA (OPA[32]), .INB (OPA_[32]), .INC (OPA[33]), .IND (OPA_[33]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[581]) ); assign SUMMAND[582] = LOGIC_ONE; smpp_high dPPH11 (.INA (OPA[33]), .INB (OPA_[33]), .TWOPOS (INT_MULTIPLIER[44]), .TWONEG (INT_MULTIPLIER[45]), .ONEPOS (INT_MULTIPLIER[46]), .ONENEG (INT_MULTIPLIER[47]), .PPBIT (SUMMAND[588]) ); smdecoder dDEC12 (.INA (OPB[23]), .INB (OPB[24]), .INC (OPB[25]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]) ); smpp_low dPPL12 (.INA (OPA[0]), .INB (OPA_[0]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[180]) ); smr_gate dRGATE12 (.INA (OPB[23]), .INB (OPB[24]), .INC (OPB[25]), .PPBIT (SUMMAND[181]) ); smpp_middle dPPM396 (.INA (OPA[0]), .INB (OPA_[0]), .INC (OPA[1]), .IND (OPA_[1]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[194]) ); smpp_middle dPPM397 (.INA (OPA[1]), .INB (OPA_[1]), .INC (OPA[2]), .IND (OPA_[2]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[207]) ); smpp_middle dPPM398 (.INA (OPA[2]), .INB (OPA_[2]), .INC (OPA[3]), .IND (OPA_[3]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[222]) ); smpp_middle dPPM399 (.INA (OPA[3]), .INB (OPA_[3]), .INC (OPA[4]), .IND (OPA_[4]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[236]) ); smpp_middle dPPM400 (.INA (OPA[4]), .INB (OPA_[4]), .INC (OPA[5]), .IND (OPA_[5]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[252]) ); smpp_middle dPPM401 (.INA (OPA[5]), .INB (OPA_[5]), .INC (OPA[6]), .IND (OPA_[6]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[267]) ); smpp_middle dPPM402 (.INA (OPA[6]), .INB (OPA_[6]), .INC (OPA[7]), .IND (OPA_[7]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[284]) ); smpp_middle dPPM403 (.INA (OPA[7]), .INB (OPA_[7]), .INC (OPA[8]), .IND (OPA_[8]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[300]) ); smpp_middle dPPM404 (.INA (OPA[8]), .INB (OPA_[8]), .INC (OPA[9]), .IND (OPA_[9]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[318]) ); smpp_middle dPPM405 (.INA (OPA[9]), .INB (OPA_[9]), .INC (OPA[10]), .IND (OPA_[10]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[336]) ); smpp_middle dPPM406 (.INA (OPA[10]), .INB (OPA_[10]), .INC (OPA[11]), .IND (OPA_[11]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[353]) ); smpp_middle dPPM407 (.INA (OPA[11]), .INB (OPA_[11]), .INC (OPA[12]), .IND (OPA_[12]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[369]) ); smpp_middle dPPM408 (.INA (OPA[12]), .INB (OPA_[12]), .INC (OPA[13]), .IND (OPA_[13]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[385]) ); smpp_middle dPPM409 (.INA (OPA[13]), .INB (OPA_[13]), .INC (OPA[14]), .IND (OPA_[14]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[400]) ); smpp_middle dPPM410 (.INA (OPA[14]), .INB (OPA_[14]), .INC (OPA[15]), .IND (OPA_[15]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[415]) ); smpp_middle dPPM411 (.INA (OPA[15]), .INB (OPA_[15]), .INC (OPA[16]), .IND (OPA_[16]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[429]) ); smpp_middle dPPM412 (.INA (OPA[16]), .INB (OPA_[16]), .INC (OPA[17]), .IND (OPA_[17]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[443]) ); smpp_middle dPPM413 (.INA (OPA[17]), .INB (OPA_[17]), .INC (OPA[18]), .IND (OPA_[18]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[456]) ); smpp_middle dPPM414 (.INA (OPA[18]), .INB (OPA_[18]), .INC (OPA[19]), .IND (OPA_[19]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[469]) ); smpp_middle dPPM415 (.INA (OPA[19]), .INB (OPA_[19]), .INC (OPA[20]), .IND (OPA_[20]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[481]) ); smpp_middle dPPM416 (.INA (OPA[20]), .INB (OPA_[20]), .INC (OPA[21]), .IND (OPA_[21]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[493]) ); smpp_middle dPPM417 (.INA (OPA[21]), .INB (OPA_[21]), .INC (OPA[22]), .IND (OPA_[22]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[504]) ); smpp_middle dPPM418 (.INA (OPA[22]), .INB (OPA_[22]), .INC (OPA[23]), .IND (OPA_[23]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[515]) ); smpp_middle dPPM419 (.INA (OPA[23]), .INB (OPA_[23]), .INC (OPA[24]), .IND (OPA_[24]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[525]) ); smpp_middle dPPM420 (.INA (OPA[24]), .INB (OPA_[24]), .INC (OPA[25]), .IND (OPA_[25]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[535]) ); smpp_middle dPPM421 (.INA (OPA[25]), .INB (OPA_[25]), .INC (OPA[26]), .IND (OPA_[26]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[544]) ); smpp_middle dPPM422 (.INA (OPA[26]), .INB (OPA_[26]), .INC (OPA[27]), .IND (OPA_[27]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[553]) ); smpp_middle dPPM423 (.INA (OPA[27]), .INB (OPA_[27]), .INC (OPA[28]), .IND (OPA_[28]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[561]) ); smpp_middle dPPM424 (.INA (OPA[28]), .INB (OPA_[28]), .INC (OPA[29]), .IND (OPA_[29]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[569]) ); smpp_middle dPPM425 (.INA (OPA[29]), .INB (OPA_[29]), .INC (OPA[30]), .IND (OPA_[30]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[576]) ); smpp_middle dPPM426 (.INA (OPA[30]), .INB (OPA_[30]), .INC (OPA[31]), .IND (OPA_[31]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[583]) ); smpp_middle dPPM427 (.INA (OPA[31]), .INB (OPA_[31]), .INC (OPA[32]), .IND (OPA_[32]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[589]) ); smpp_middle dPPM428 (.INA (OPA[32]), .INB (OPA_[32]), .INC (OPA[33]), .IND (OPA_[33]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[594]) ); assign SUMMAND[595] = LOGIC_ONE; smpp_high dPPH12 (.INA (OPA[33]), .INB (OPA_[33]), .TWOPOS (INT_MULTIPLIER[48]), .TWONEG (INT_MULTIPLIER[49]), .ONEPOS (INT_MULTIPLIER[50]), .ONENEG (INT_MULTIPLIER[51]), .PPBIT (SUMMAND[600]) ); smdecoder dDEC13 (.INA (OPB[25]), .INB (OPB[26]), .INC (OPB[27]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]) ); smpp_low dPPL13 (.INA (OPA[0]), .INB (OPA_[0]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[208]) ); smr_gate dRGATE13 (.INA (OPB[25]), .INB (OPB[26]), .INC (OPB[27]), .PPBIT (SUMMAND[209]) ); smpp_middle dPPM429 (.INA (OPA[0]), .INB (OPA_[0]), .INC (OPA[1]), .IND (OPA_[1]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[223]) ); smpp_middle dPPM430 (.INA (OPA[1]), .INB (OPA_[1]), .INC (OPA[2]), .IND (OPA_[2]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[237]) ); smpp_middle dPPM431 (.INA (OPA[2]), .INB (OPA_[2]), .INC (OPA[3]), .IND (OPA_[3]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[253]) ); smpp_middle dPPM432 (.INA (OPA[3]), .INB (OPA_[3]), .INC (OPA[4]), .IND (OPA_[4]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[268]) ); smpp_middle dPPM433 (.INA (OPA[4]), .INB (OPA_[4]), .INC (OPA[5]), .IND (OPA_[5]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[285]) ); smpp_middle dPPM434 (.INA (OPA[5]), .INB (OPA_[5]), .INC (OPA[6]), .IND (OPA_[6]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[301]) ); smpp_middle dPPM435 (.INA (OPA[6]), .INB (OPA_[6]), .INC (OPA[7]), .IND (OPA_[7]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[319]) ); smpp_middle dPPM436 (.INA (OPA[7]), .INB (OPA_[7]), .INC (OPA[8]), .IND (OPA_[8]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[337]) ); smpp_middle dPPM437 (.INA (OPA[8]), .INB (OPA_[8]), .INC (OPA[9]), .IND (OPA_[9]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[354]) ); smpp_middle dPPM438 (.INA (OPA[9]), .INB (OPA_[9]), .INC (OPA[10]), .IND (OPA_[10]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[370]) ); smpp_middle dPPM439 (.INA (OPA[10]), .INB (OPA_[10]), .INC (OPA[11]), .IND (OPA_[11]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[386]) ); smpp_middle dPPM440 (.INA (OPA[11]), .INB (OPA_[11]), .INC (OPA[12]), .IND (OPA_[12]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[401]) ); smpp_middle dPPM441 (.INA (OPA[12]), .INB (OPA_[12]), .INC (OPA[13]), .IND (OPA_[13]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[416]) ); smpp_middle dPPM442 (.INA (OPA[13]), .INB (OPA_[13]), .INC (OPA[14]), .IND (OPA_[14]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[430]) ); smpp_middle dPPM443 (.INA (OPA[14]), .INB (OPA_[14]), .INC (OPA[15]), .IND (OPA_[15]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[444]) ); smpp_middle dPPM444 (.INA (OPA[15]), .INB (OPA_[15]), .INC (OPA[16]), .IND (OPA_[16]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[457]) ); smpp_middle dPPM445 (.INA (OPA[16]), .INB (OPA_[16]), .INC (OPA[17]), .IND (OPA_[17]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[470]) ); smpp_middle dPPM446 (.INA (OPA[17]), .INB (OPA_[17]), .INC (OPA[18]), .IND (OPA_[18]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[482]) ); smpp_middle dPPM447 (.INA (OPA[18]), .INB (OPA_[18]), .INC (OPA[19]), .IND (OPA_[19]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[494]) ); smpp_middle dPPM448 (.INA (OPA[19]), .INB (OPA_[19]), .INC (OPA[20]), .IND (OPA_[20]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[505]) ); smpp_middle dPPM449 (.INA (OPA[20]), .INB (OPA_[20]), .INC (OPA[21]), .IND (OPA_[21]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[516]) ); smpp_middle dPPM450 (.INA (OPA[21]), .INB (OPA_[21]), .INC (OPA[22]), .IND (OPA_[22]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[526]) ); smpp_middle dPPM451 (.INA (OPA[22]), .INB (OPA_[22]), .INC (OPA[23]), .IND (OPA_[23]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[536]) ); smpp_middle dPPM452 (.INA (OPA[23]), .INB (OPA_[23]), .INC (OPA[24]), .IND (OPA_[24]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[545]) ); smpp_middle dPPM453 (.INA (OPA[24]), .INB (OPA_[24]), .INC (OPA[25]), .IND (OPA_[25]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[554]) ); smpp_middle dPPM454 (.INA (OPA[25]), .INB (OPA_[25]), .INC (OPA[26]), .IND (OPA_[26]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[562]) ); smpp_middle dPPM455 (.INA (OPA[26]), .INB (OPA_[26]), .INC (OPA[27]), .IND (OPA_[27]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[570]) ); smpp_middle dPPM456 (.INA (OPA[27]), .INB (OPA_[27]), .INC (OPA[28]), .IND (OPA_[28]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[577]) ); smpp_middle dPPM457 (.INA (OPA[28]), .INB (OPA_[28]), .INC (OPA[29]), .IND (OPA_[29]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[584]) ); smpp_middle dPPM458 (.INA (OPA[29]), .INB (OPA_[29]), .INC (OPA[30]), .IND (OPA_[30]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[590]) ); smpp_middle dPPM459 (.INA (OPA[30]), .INB (OPA_[30]), .INC (OPA[31]), .IND (OPA_[31]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[596]) ); smpp_middle dPPM460 (.INA (OPA[31]), .INB (OPA_[31]), .INC (OPA[32]), .IND (OPA_[32]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[601]) ); smpp_middle dPPM461 (.INA (OPA[32]), .INB (OPA_[32]), .INC (OPA[33]), .IND (OPA_[33]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[605]) ); assign SUMMAND[606] = LOGIC_ONE; smpp_high dPPH13 (.INA (OPA[33]), .INB (OPA_[33]), .TWOPOS (INT_MULTIPLIER[52]), .TWONEG (INT_MULTIPLIER[53]), .ONEPOS (INT_MULTIPLIER[54]), .ONENEG (INT_MULTIPLIER[55]), .PPBIT (SUMMAND[610]) ); smdecoder dDEC14 (.INA (OPB[27]), .INB (OPB[28]), .INC (OPB[29]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]) ); smpp_low dPPL14 (.INA (OPA[0]), .INB (OPA_[0]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[238]) ); smr_gate dRGATE14 (.INA (OPB[27]), .INB (OPB[28]), .INC (OPB[29]), .PPBIT (SUMMAND[239]) ); smpp_middle dPPM462 (.INA (OPA[0]), .INB (OPA_[0]), .INC (OPA[1]), .IND (OPA_[1]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[254]) ); smpp_middle dPPM463 (.INA (OPA[1]), .INB (OPA_[1]), .INC (OPA[2]), .IND (OPA_[2]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[269]) ); smpp_middle dPPM464 (.INA (OPA[2]), .INB (OPA_[2]), .INC (OPA[3]), .IND (OPA_[3]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[286]) ); smpp_middle dPPM465 (.INA (OPA[3]), .INB (OPA_[3]), .INC (OPA[4]), .IND (OPA_[4]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[302]) ); smpp_middle dPPM466 (.INA (OPA[4]), .INB (OPA_[4]), .INC (OPA[5]), .IND (OPA_[5]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[320]) ); smpp_middle dPPM467 (.INA (OPA[5]), .INB (OPA_[5]), .INC (OPA[6]), .IND (OPA_[6]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[338]) ); smpp_middle dPPM468 (.INA (OPA[6]), .INB (OPA_[6]), .INC (OPA[7]), .IND (OPA_[7]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[355]) ); smpp_middle dPPM469 (.INA (OPA[7]), .INB (OPA_[7]), .INC (OPA[8]), .IND (OPA_[8]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[371]) ); smpp_middle dPPM470 (.INA (OPA[8]), .INB (OPA_[8]), .INC (OPA[9]), .IND (OPA_[9]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[387]) ); smpp_middle dPPM471 (.INA (OPA[9]), .INB (OPA_[9]), .INC (OPA[10]), .IND (OPA_[10]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[402]) ); smpp_middle dPPM472 (.INA (OPA[10]), .INB (OPA_[10]), .INC (OPA[11]), .IND (OPA_[11]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[417]) ); smpp_middle dPPM473 (.INA (OPA[11]), .INB (OPA_[11]), .INC (OPA[12]), .IND (OPA_[12]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[431]) ); smpp_middle dPPM474 (.INA (OPA[12]), .INB (OPA_[12]), .INC (OPA[13]), .IND (OPA_[13]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[445]) ); smpp_middle dPPM475 (.INA (OPA[13]), .INB (OPA_[13]), .INC (OPA[14]), .IND (OPA_[14]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[458]) ); smpp_middle dPPM476 (.INA (OPA[14]), .INB (OPA_[14]), .INC (OPA[15]), .IND (OPA_[15]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[471]) ); smpp_middle dPPM477 (.INA (OPA[15]), .INB (OPA_[15]), .INC (OPA[16]), .IND (OPA_[16]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[483]) ); smpp_middle dPPM478 (.INA (OPA[16]), .INB (OPA_[16]), .INC (OPA[17]), .IND (OPA_[17]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[495]) ); smpp_middle dPPM479 (.INA (OPA[17]), .INB (OPA_[17]), .INC (OPA[18]), .IND (OPA_[18]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[506]) ); smpp_middle dPPM480 (.INA (OPA[18]), .INB (OPA_[18]), .INC (OPA[19]), .IND (OPA_[19]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[517]) ); smpp_middle dPPM481 (.INA (OPA[19]), .INB (OPA_[19]), .INC (OPA[20]), .IND (OPA_[20]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[527]) ); smpp_middle dPPM482 (.INA (OPA[20]), .INB (OPA_[20]), .INC (OPA[21]), .IND (OPA_[21]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[537]) ); smpp_middle dPPM483 (.INA (OPA[21]), .INB (OPA_[21]), .INC (OPA[22]), .IND (OPA_[22]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[546]) ); smpp_middle dPPM484 (.INA (OPA[22]), .INB (OPA_[22]), .INC (OPA[23]), .IND (OPA_[23]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[555]) ); smpp_middle dPPM485 (.INA (OPA[23]), .INB (OPA_[23]), .INC (OPA[24]), .IND (OPA_[24]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[563]) ); smpp_middle dPPM486 (.INA (OPA[24]), .INB (OPA_[24]), .INC (OPA[25]), .IND (OPA_[25]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[571]) ); smpp_middle dPPM487 (.INA (OPA[25]), .INB (OPA_[25]), .INC (OPA[26]), .IND (OPA_[26]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[578]) ); smpp_middle dPPM488 (.INA (OPA[26]), .INB (OPA_[26]), .INC (OPA[27]), .IND (OPA_[27]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[585]) ); smpp_middle dPPM489 (.INA (OPA[27]), .INB (OPA_[27]), .INC (OPA[28]), .IND (OPA_[28]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[591]) ); smpp_middle dPPM490 (.INA (OPA[28]), .INB (OPA_[28]), .INC (OPA[29]), .IND (OPA_[29]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[597]) ); smpp_middle dPPM491 (.INA (OPA[29]), .INB (OPA_[29]), .INC (OPA[30]), .IND (OPA_[30]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[602]) ); smpp_middle dPPM492 (.INA (OPA[30]), .INB (OPA_[30]), .INC (OPA[31]), .IND (OPA_[31]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[607]) ); smpp_middle dPPM493 (.INA (OPA[31]), .INB (OPA_[31]), .INC (OPA[32]), .IND (OPA_[32]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[611]) ); smpp_middle dPPM494 (.INA (OPA[32]), .INB (OPA_[32]), .INC (OPA[33]), .IND (OPA_[33]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[614]) ); assign SUMMAND[615] = LOGIC_ONE; smpp_high dPPH14 (.INA (OPA[33]), .INB (OPA_[33]), .TWOPOS (INT_MULTIPLIER[56]), .TWONEG (INT_MULTIPLIER[57]), .ONEPOS (INT_MULTIPLIER[58]), .ONENEG (INT_MULTIPLIER[59]), .PPBIT (SUMMAND[618]) ); smdecoder dDEC15 (.INA (OPB[29]), .INB (OPB[30]), .INC (OPB[31]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]) ); smpp_low dPPL15 (.INA (OPA[0]), .INB (OPA_[0]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[270]) ); smr_gate dRGATE15 (.INA (OPB[29]), .INB (OPB[30]), .INC (OPB[31]), .PPBIT (SUMMAND[271]) ); smpp_middle dPPM495 (.INA (OPA[0]), .INB (OPA_[0]), .INC (OPA[1]), .IND (OPA_[1]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[287]) ); smpp_middle dPPM496 (.INA (OPA[1]), .INB (OPA_[1]), .INC (OPA[2]), .IND (OPA_[2]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[303]) ); smpp_middle dPPM497 (.INA (OPA[2]), .INB (OPA_[2]), .INC (OPA[3]), .IND (OPA_[3]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[321]) ); smpp_middle dPPM498 (.INA (OPA[3]), .INB (OPA_[3]), .INC (OPA[4]), .IND (OPA_[4]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[339]) ); smpp_middle dPPM499 (.INA (OPA[4]), .INB (OPA_[4]), .INC (OPA[5]), .IND (OPA_[5]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[356]) ); smpp_middle dPPM500 (.INA (OPA[5]), .INB (OPA_[5]), .INC (OPA[6]), .IND (OPA_[6]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[372]) ); smpp_middle dPPM501 (.INA (OPA[6]), .INB (OPA_[6]), .INC (OPA[7]), .IND (OPA_[7]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[388]) ); smpp_middle dPPM502 (.INA (OPA[7]), .INB (OPA_[7]), .INC (OPA[8]), .IND (OPA_[8]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[403]) ); smpp_middle dPPM503 (.INA (OPA[8]), .INB (OPA_[8]), .INC (OPA[9]), .IND (OPA_[9]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[418]) ); smpp_middle dPPM504 (.INA (OPA[9]), .INB (OPA_[9]), .INC (OPA[10]), .IND (OPA_[10]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[432]) ); smpp_middle dPPM505 (.INA (OPA[10]), .INB (OPA_[10]), .INC (OPA[11]), .IND (OPA_[11]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[446]) ); smpp_middle dPPM506 (.INA (OPA[11]), .INB (OPA_[11]), .INC (OPA[12]), .IND (OPA_[12]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[459]) ); smpp_middle dPPM507 (.INA (OPA[12]), .INB (OPA_[12]), .INC (OPA[13]), .IND (OPA_[13]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[472]) ); smpp_middle dPPM508 (.INA (OPA[13]), .INB (OPA_[13]), .INC (OPA[14]), .IND (OPA_[14]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[484]) ); smpp_middle dPPM509 (.INA (OPA[14]), .INB (OPA_[14]), .INC (OPA[15]), .IND (OPA_[15]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[496]) ); smpp_middle dPPM510 (.INA (OPA[15]), .INB (OPA_[15]), .INC (OPA[16]), .IND (OPA_[16]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[507]) ); smpp_middle dPPM511 (.INA (OPA[16]), .INB (OPA_[16]), .INC (OPA[17]), .IND (OPA_[17]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[518]) ); smpp_middle dPPM512 (.INA (OPA[17]), .INB (OPA_[17]), .INC (OPA[18]), .IND (OPA_[18]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[528]) ); smpp_middle dPPM513 (.INA (OPA[18]), .INB (OPA_[18]), .INC (OPA[19]), .IND (OPA_[19]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[538]) ); smpp_middle dPPM514 (.INA (OPA[19]), .INB (OPA_[19]), .INC (OPA[20]), .IND (OPA_[20]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[547]) ); smpp_middle dPPM515 (.INA (OPA[20]), .INB (OPA_[20]), .INC (OPA[21]), .IND (OPA_[21]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[556]) ); smpp_middle dPPM516 (.INA (OPA[21]), .INB (OPA_[21]), .INC (OPA[22]), .IND (OPA_[22]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[564]) ); smpp_middle dPPM517 (.INA (OPA[22]), .INB (OPA_[22]), .INC (OPA[23]), .IND (OPA_[23]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[572]) ); smpp_middle dPPM518 (.INA (OPA[23]), .INB (OPA_[23]), .INC (OPA[24]), .IND (OPA_[24]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[579]) ); smpp_middle dPPM519 (.INA (OPA[24]), .INB (OPA_[24]), .INC (OPA[25]), .IND (OPA_[25]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[586]) ); smpp_middle dPPM520 (.INA (OPA[25]), .INB (OPA_[25]), .INC (OPA[26]), .IND (OPA_[26]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[592]) ); smpp_middle dPPM521 (.INA (OPA[26]), .INB (OPA_[26]), .INC (OPA[27]), .IND (OPA_[27]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[598]) ); smpp_middle dPPM522 (.INA (OPA[27]), .INB (OPA_[27]), .INC (OPA[28]), .IND (OPA_[28]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[603]) ); smpp_middle dPPM523 (.INA (OPA[28]), .INB (OPA_[28]), .INC (OPA[29]), .IND (OPA_[29]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[608]) ); smpp_middle dPPM524 (.INA (OPA[29]), .INB (OPA_[29]), .INC (OPA[30]), .IND (OPA_[30]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[612]) ); smpp_middle dPPM525 (.INA (OPA[30]), .INB (OPA_[30]), .INC (OPA[31]), .IND (OPA_[31]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[616]) ); smpp_middle dPPM526 (.INA (OPA[31]), .INB (OPA_[31]), .INC (OPA[32]), .IND (OPA_[32]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[619]) ); smpp_middle dPPM527 (.INA (OPA[32]), .INB (OPA_[32]), .INC (OPA[33]), .IND (OPA_[33]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[621]) ); assign SUMMAND[622] = LOGIC_ONE; smpp_high dPPH15 (.INA (OPA[33]), .INB (OPA_[33]), .TWOPOS (INT_MULTIPLIER[60]), .TWONEG (INT_MULTIPLIER[61]), .ONEPOS (INT_MULTIPLIER[62]), .ONENEG (INT_MULTIPLIER[63]), .PPBIT (SUMMAND[624]) ); smdecoder dDEC16 (.INA (OPB[31]), .INB (OPB[32]), .INC (OPB[33]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]) ); smpp_low dPPL16 (.INA (OPA[0]), .INB (OPA_[0]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[304]) ); smr_gate dRGATE16 (.INA (OPB[31]), .INB (OPB[32]), .INC (OPB[33]), .PPBIT (SUMMAND[305]) ); smpp_middle dPPM528 (.INA (OPA[0]), .INB (OPA_[0]), .INC (OPA[1]), .IND (OPA_[1]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[322]) ); smpp_middle dPPM529 (.INA (OPA[1]), .INB (OPA_[1]), .INC (OPA[2]), .IND (OPA_[2]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[340]) ); smpp_middle dPPM530 (.INA (OPA[2]), .INB (OPA_[2]), .INC (OPA[3]), .IND (OPA_[3]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[357]) ); smpp_middle dPPM531 (.INA (OPA[3]), .INB (OPA_[3]), .INC (OPA[4]), .IND (OPA_[4]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[373]) ); smpp_middle dPPM532 (.INA (OPA[4]), .INB (OPA_[4]), .INC (OPA[5]), .IND (OPA_[5]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[389]) ); smpp_middle dPPM533 (.INA (OPA[5]), .INB (OPA_[5]), .INC (OPA[6]), .IND (OPA_[6]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[404]) ); smpp_middle dPPM534 (.INA (OPA[6]), .INB (OPA_[6]), .INC (OPA[7]), .IND (OPA_[7]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[419]) ); smpp_middle dPPM535 (.INA (OPA[7]), .INB (OPA_[7]), .INC (OPA[8]), .IND (OPA_[8]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[433]) ); smpp_middle dPPM536 (.INA (OPA[8]), .INB (OPA_[8]), .INC (OPA[9]), .IND (OPA_[9]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[447]) ); smpp_middle dPPM537 (.INA (OPA[9]), .INB (OPA_[9]), .INC (OPA[10]), .IND (OPA_[10]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[460]) ); smpp_middle dPPM538 (.INA (OPA[10]), .INB (OPA_[10]), .INC (OPA[11]), .IND (OPA_[11]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[473]) ); smpp_middle dPPM539 (.INA (OPA[11]), .INB (OPA_[11]), .INC (OPA[12]), .IND (OPA_[12]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[485]) ); smpp_middle dPPM540 (.INA (OPA[12]), .INB (OPA_[12]), .INC (OPA[13]), .IND (OPA_[13]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[497]) ); smpp_middle dPPM541 (.INA (OPA[13]), .INB (OPA_[13]), .INC (OPA[14]), .IND (OPA_[14]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[508]) ); smpp_middle dPPM542 (.INA (OPA[14]), .INB (OPA_[14]), .INC (OPA[15]), .IND (OPA_[15]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[519]) ); smpp_middle dPPM543 (.INA (OPA[15]), .INB (OPA_[15]), .INC (OPA[16]), .IND (OPA_[16]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[529]) ); smpp_middle dPPM544 (.INA (OPA[16]), .INB (OPA_[16]), .INC (OPA[17]), .IND (OPA_[17]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[539]) ); smpp_middle dPPM545 (.INA (OPA[17]), .INB (OPA_[17]), .INC (OPA[18]), .IND (OPA_[18]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[548]) ); smpp_middle dPPM546 (.INA (OPA[18]), .INB (OPA_[18]), .INC (OPA[19]), .IND (OPA_[19]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[557]) ); smpp_middle dPPM547 (.INA (OPA[19]), .INB (OPA_[19]), .INC (OPA[20]), .IND (OPA_[20]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[565]) ); smpp_middle dPPM548 (.INA (OPA[20]), .INB (OPA_[20]), .INC (OPA[21]), .IND (OPA_[21]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[573]) ); smpp_middle dPPM549 (.INA (OPA[21]), .INB (OPA_[21]), .INC (OPA[22]), .IND (OPA_[22]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[580]) ); smpp_middle dPPM550 (.INA (OPA[22]), .INB (OPA_[22]), .INC (OPA[23]), .IND (OPA_[23]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[587]) ); smpp_middle dPPM551 (.INA (OPA[23]), .INB (OPA_[23]), .INC (OPA[24]), .IND (OPA_[24]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[593]) ); smpp_middle dPPM552 (.INA (OPA[24]), .INB (OPA_[24]), .INC (OPA[25]), .IND (OPA_[25]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[599]) ); smpp_middle dPPM553 (.INA (OPA[25]), .INB (OPA_[25]), .INC (OPA[26]), .IND (OPA_[26]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[604]) ); smpp_middle dPPM554 (.INA (OPA[26]), .INB (OPA_[26]), .INC (OPA[27]), .IND (OPA_[27]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[609]) ); smpp_middle dPPM555 (.INA (OPA[27]), .INB (OPA_[27]), .INC (OPA[28]), .IND (OPA_[28]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[613]) ); smpp_middle dPPM556 (.INA (OPA[28]), .INB (OPA_[28]), .INC (OPA[29]), .IND (OPA_[29]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[617]) ); smpp_middle dPPM557 (.INA (OPA[29]), .INB (OPA_[29]), .INC (OPA[30]), .IND (OPA_[30]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[620]) ); smpp_middle dPPM558 (.INA (OPA[30]), .INB (OPA_[30]), .INC (OPA[31]), .IND (OPA_[31]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[623]) ); smpp_middle dPPM559 (.INA (OPA[31]), .INB (OPA_[31]), .INC (OPA[32]), .IND (OPA_[32]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[625]) ); smpp_middle dPPM560 (.INA (OPA[32]), .INB (OPA_[32]), .INC (OPA[33]), .IND (OPA_[33]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[626]) ); assign SUMMAND[627] = LOGIC_ONE; smpp_high dPPH16 (.INA (OPA[33]), .INB (OPA_[33]), .TWOPOS (INT_MULTIPLIER[64]), .TWONEG (INT_MULTIPLIER[65]), .ONEPOS (INT_MULTIPLIER[66]), .ONENEG (INT_MULTIPLIER[67]), .PPBIT (SUMMAND[628]) ); endmodule // Simple cells module smpp_low (ONEPOS, ONENEG, TWONEG, INA, INB, PPBIT); input ONEPOS; input ONENEG; input TWONEG; input INA; input INB; output PPBIT; assign PPBIT = (ONEPOS & INA) | (ONENEG & INB) | TWONEG; endmodule module smpp_middle (ONEPOS, ONENEG, TWOPOS, TWONEG, INA, INB, INC, IND, PPBIT); input ONEPOS; input ONENEG; input TWOPOS; input TWONEG; input INA; input INB; input INC; input IND; output PPBIT; assign PPBIT = ~ ((~ (INA & TWOPOS)) & (~ (INB & TWONEG)) & (~ (INC & ONEPOS)) & (~ (IND & ONENEG))); endmodule module smpp_high (ONEPOS, ONENEG, TWOPOS, TWONEG, INA, INB, PPBIT); input ONEPOS; input ONENEG; input TWOPOS; input TWONEG; input INA; input INB; output PPBIT; assign PPBIT = ~ ((INA & ONEPOS) | (INB & ONENEG) | (INA & TWOPOS) | (INB & TWONEG)); endmodule module smr_gate (INA, INB, INC, PPBIT); input INA; input INB; input INC; output PPBIT; assign PPBIT = (~ (INA & INB)) & INC; endmodule module smdecoder (INA, INB, INC, TWOPOS, TWONEG, ONEPOS, ONENEG); input INA; input INB; input INC; output TWOPOS; output TWONEG; output ONEPOS; output ONENEG; assign TWOPOS = ~ (~ (INA & INB & (~ INC))); assign TWONEG = ~ (~ ((~ INA) & (~ INB) & INC)); assign ONEPOS = ((~ INA) & INB & (~ INC)) | ((~ INC) & (~ INB) & INA); assign ONENEG = (INA & (~ INB) & INC) | (INC & INB & (~ INA)); endmodule module smfulladder (DATA_A, DATA_B, DATA_C, SAVE, CARRY); input DATA_A; input DATA_B; input DATA_C; output SAVE; output CARRY; wire TMP; assign TMP = DATA_A ^ DATA_B; assign SAVE = TMP ^ DATA_C; assign CARRY = ~ ((~ (TMP & DATA_C)) & (~ (DATA_A & DATA_B))); endmodule module smhalfadder (DATA_A, DATA_B, SAVE, CARRY); input DATA_A; input DATA_B; output SAVE; output CARRY; assign SAVE = DATA_A ^ DATA_B; assign CARRY = DATA_A & DATA_B; endmodule module smffa ( input clk, input en_d1, input D, output reg Q ); always @ (posedge clk) begin Q <= D; end endmodule module smffb ( input clk, input en_d2, input D, output reg Q ); always @ (posedge clk) begin Q <= D; end endmodule module sminvblock (GIN, GOUT); input GIN; output GOUT; assign GOUT = ~ GIN; endmodule module smxxor1 (A, B, GIN, SUM); input A; input B; input GIN; output SUM; assign SUM = (~ (A ^ B)) ^ GIN; endmodule module smblock0 (A, B, POUT, GOUT); input A; input B; output POUT; output GOUT; assign POUT = ~ (A | B); assign GOUT = ~ (A & B); endmodule module smblock1 (PIN1, PIN2, GIN1, GIN2, POUT, GOUT); input PIN1; input PIN2; input GIN1; input GIN2; output POUT; output GOUT; assign POUT = ~ (PIN1 | PIN2); assign GOUT = ~ (GIN2 & (PIN2 | GIN1)); endmodule module smblock2 (PIN1, PIN2, GIN1, GIN2, POUT, GOUT); input PIN1; input PIN2; input GIN1; input GIN2; output POUT; output GOUT; assign POUT = ~ (PIN1 & PIN2); assign GOUT = ~ (GIN2 | (PIN2 & GIN1)); endmodule module smblock1a (PIN2, GIN1, GIN2, GOUT); input PIN2; input GIN1; input GIN2; output GOUT; assign GOUT = ~ (GIN2 & (PIN2 | GIN1)); endmodule module smblock2a (PIN2, GIN1, GIN2, GOUT); input PIN2; input GIN1; input GIN2; output GOUT; assign GOUT = ~ (GIN2 | (PIN2 & GIN1)); endmodule // verilog_format: on // Local Variables: // compile-command: "vlint --brief --nowarn=MULTMF,MODLNM t_math_wallace_mul.v" // End: verilator-5.042/test_regress/t/t_class_assign_cond.py0000755000542200017500000000073415101701376023446 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_assert_synth.v0000644000542200017500000000521515101701376022331 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg a; initial a = 1'b1; reg b_fc; initial b_fc = 1'b0; reg b_pc; initial b_pc = 1'b0; reg b_oh; initial b_oh = 1'b0; reg b_oc; initial b_oc = 1'b0; wire a_l = ~a; wire b_oc_l = ~b_oc; // Note we must ensure that full, parallel, etc, only fire during // edges (not mid-cycle), and must provide a way to turn them off. // SystemVerilog provides: $asserton and $assertoff. // verilator lint_off CASEINCOMPLETE always @* begin // Note not all tools support directives on casez's `ifdef ATTRIBUTES case ({a,b_fc}) // synopsys full_case `else case ({a,b_fc}) `endif 2'b0_0: ; 2'b0_1: ; 2'b1_0: ; // Note no default endcase priority case ({a,b_fc}) 2'b0_0: ; 2'b0_1: ; 2'b1_0: ; // Note no default endcase end always @* begin `ifdef ATTRIBUTES case (1'b1) // synopsys full_case parallel_case `else `ifdef FAILING_FULL case (1'b1) // synopsys parallel_case `else case (1'b1) // synopsys parallel_full `endif `endif a: ; b_pc: ; endcase end `ifdef NOT_YET_VERILATOR // Unsupported // ambit synthesis one_hot "a, b_oh" // cadence one_cold "a_l, b_oc_l" `endif integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin a <= 1'b1; b_fc <= 1'b0; b_pc <= 1'b0; b_oh <= 1'b0; b_oc <= 1'b0; end if (cyc==2) begin a <= 1'b0; b_fc <= 1'b1; b_pc <= 1'b1; b_oh <= 1'b1; b_oc <= 1'b1; end if (cyc==3) begin a <= 1'b1; b_fc <= 1'b0; b_pc <= 1'b0; b_oh <= 1'b0; b_oc <= 1'b0; end if (cyc==4) begin `ifdef FAILING_FULL b_fc <= 1'b1; `endif `ifdef FAILING_PARALLEL b_pc <= 1'b1; `endif `ifdef FAILING_OH b_oh <= 1'b1; `endif `ifdef FAILING_OC b_oc <= 1'b1; `endif end if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end end initial begin : test_info $info ("Start of $info test"); $info ("Middle of $info test"); $info ("End of $info test"); end : test_info endmodule verilator-5.042/test_regress/t/t_func_nansi_dup_bad.py0000755000542200017500000000076615101701376023600 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_concat_large_bad.v0000644000542200017500000000046715101701376023036 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2015 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; wire [32767:0] a = {32768{1'b1}}; initial begin $stop; end endmodule verilator-5.042/test_regress/t/t_semaphore_bad.py0000755000542200017500000000076315101701376022565 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_flag_hier1_bad.out0000644000542200017500000000043715101701376022755 0ustar mahmoudyfreeshell%Error: --hierarchical must not be set with --hierarchical-child or --hierarchical-block ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: --hierarchical-block must be set when --hierarchical-child is set %Error: Exiting due to verilator-5.042/test_regress/t/t_dynarray_init.v0000644000542200017500000000161015101701376022452 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module t; int a1[] = '{12, 13}; int a2[] = {14, 15}; int a3[] = '{16}; int a4[] = {17}; int a5[] = {}; initial begin `checkh(a1.size, 2); `checkh(a1[0], 12); `checkh(a1[1], 13); `checkh(a2.size, 2); `checkh(a2[0], 14); `checkh(a2[1], 15); `checkh(a3.size, 1); `checkh(a3[0], 16); `checkh(a4.size, 1); `checkh(a4[0], 17); `checkh(a5.size, 0); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_assert_ctl_arg_unsup.v0000644000542200017500000000076115101701376024032 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t; let OFF = 4; let EXPECT = 16; let UNIQUE = 32; let UNIQUE0 = 64; let PRIORITY = 128; initial begin $assertcontrol(OFF, EXPECT); $assertcontrol(OFF, UNIQUE); $assertcontrol(OFF, UNIQUE0); $assertcontrol(OFF, PRIORITY); end endmodule verilator-5.042/test_regress/t/t_lint_colonplus_bad.py0000755000542200017500000000076315101701376023646 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_union_hard_bad.py0000755000542200017500000000076315101701376022730 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lib.py0000755000542200017500000000351515101701376020540 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt', 'xsim') test.top_filename = "t/t_lib_prot.v" if test.benchmark: test.sim_time = test.benchmark * 100 trace_opt = "" if re.search(r'--no-trace', ' '.join(test.driver_verilator_flags)) else "-trace" secret_prefix = "secret" secret_dir = test.obj_dir + "/" + secret_prefix test.mkdir_ok(secret_dir) while True: # Always compile the secret file with Verilator no matter what simulator # we are testing with test.run(logfile=secret_dir + "/vlt_compile.log", cmd=["perl", os.environ["VERILATOR_ROOT"] + "/bin/verilator", '--no-timing', trace_opt, "--prefix", "Vt_lib_prot_secret", "-cc", "-Mdir", secret_dir, "--lib-create", secret_prefix, "t/t_lib_prot_secret.v"], verilator_run=True) # yapf:disable test.run(logfile=secret_dir + "/secret_gcc.log", cmd=[os.environ["MAKE"], "-C", secret_dir, "-f", "Vt_lib_prot_secret.mk"]) test.compile(verilator_flags2=['--no-timing', trace_opt, "-LDFLAGS", secret_prefix + "/libsecret.a", secret_dir + "/secret.sv"], xsim_flags2=[secret_dir + "/secret.sv"]) # yapf:disable test.execute(xsim_run_flags2=["--sv_lib", secret_dir + "/libsecret", "--dpi_absolute"]) test.passes() break verilator-5.042/test_regress/t/t_assert_clock_event_unsup.v0000644000542200017500000000142015101701376024704 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ clk ); input clk; int cyc = 0; logic val = 0; always @(posedge clk) begin cyc <= cyc + 1; val = ~val; end property check(int cyc_mod_2, logic expected); @(posedge clk) cyc % 2 == cyc_mod_2 |=> val == expected; endproperty property check_if_1(int cyc_mod_2); @(negedge clk) check(cyc_mod_2, 1); endproperty assert property(check_if_1(1)) else begin // Assertion should fail $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_disable_inside.py0000755000542200017500000000101315101701376022717 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(timing_loop=True, verilator_flags2=["--timing"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_unroll_pragma.v0000644000542200017500000000176515101701376022453 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `ifdef TEST_DISABLE `define PRAGMA /*verilator unroll_disable*/ `elsif TEST_FULL `define PRAGMA /*verilator unroll_full*/ `elsif TEST_NONE `define PRAGMA `endif module t; int i, j; // This must always unroll for (genvar g = 0; g < 10; ++g) begin initial $c("gened();"); end initial begin // Test a loop smaller than --unroll-count `PRAGMA for (i = 0; i < 2; ++i) begin `PRAGMA for (j = 0; j < 2; ++j) begin $c("small();"); end end // Test a loop larger than --unroll-count `PRAGMA for (i = 0; i < 5; ++i) begin `PRAGMA for (j = 0; j < 5; ++j) begin $c("large();"); end end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_struct_unpacked_init.v0000644000542200017500000000101415101701376024015 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; parameter P = 4'h5; struct { // Can't legally be packed bit [3:0] m_lo = P; bit [3:0] m_hi; } s; initial begin s.m_hi = 4'ha; if (s.m_lo != 4'h5) $stop; if (s.m_hi != 4'ha) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_dynarray_method.v0000644000542200017500000001210115101701376022764 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); module t; string s[] = { "hello", "sad", "sad", "world" }; initial begin int d[]; int de[]; // Empty int qv[$]; // Value returns int qvunused[$]; // Value returns (unused) int qi[$]; // Index returns int i; d = '{1, 2, 2, 4, 3}; `checkp(d, "'{'h1, 'h2, 'h2, 'h4, 'h3}"); d = {1, 2, 2, 4, 3}; `checkp(d, "'{'h1, 'h2, 'h2, 'h4, 'h3}"); // sort/rsort with clause is the field to use for the sorting d.sort; `checkp(d, "'{'h1, 'h2, 'h2, 'h3, 'h4}"); d.sort with (10 - item); `checkp(d, "'{'h4, 'h3, 'h2, 'h2, 'h1}"); d.sort(x) with (10 - x); `checkp(d, "'{'h4, 'h3, 'h2, 'h2, 'h1}"); de.sort(x) with (10 - x); `checkp(de, "'{}"); d.rsort; `checkp(d, "'{'h4, 'h3, 'h2, 'h2, 'h1}"); d.rsort with (10 - item); `checkp(d, "'{'h1, 'h2, 'h2, 'h3, 'h4}"); de.rsort(x) with (10 - x); `checkp(d, "'{'h1, 'h2, 'h2, 'h3, 'h4}"); d = '{2, 2, 4, 1, 3}; qv = d.unique; `checkp(qv, "'{'h2, 'h4, 'h1, 'h3}"); qv = de.unique; `checkh(qv.size(), 0); qi = d.unique_index; qv.sort; `checkp(qi, "'{'h0, 'h2, 'h3, 'h4}"); qi = de.unique_index; `checkh(qi.size(), 0); d.reverse; `checkp(d, "'{'h3, 'h1, 'h4, 'h2, 'h2}"); de.reverse; `checkh(de.size(), 0); d.shuffle(); d.sort; `checkp(d, "'{'h1, 'h2, 'h2, 'h3, 'h4}"); de.shuffle(); `checkh(de.size(), 0); // These require an with clause or are illegal // TODO add a lint check that with clause is provided qv = d.find with (item == 2); `checkp(qv, "'{'h2, 'h2}"); qv = d.find_first with (item == 2); `checkp(qv, "'{'h2}"); qv = d.find_last with (item == 2); `checkp(qv, "'{'h2}"); qv = d.find with (item == 20); `checkh(qv.size, 0); qv = d.find_first with (item == 20); `checkh(qv.size, 0); qv = d.find_last with (item == 20); `checkh(qv.size, 0); // Check gate eater with Lambda variable removal qvunused = d.find with (item == 20); qi = d.find_index with (item == 2); qi.sort; `checkp(qi, "'{'h1, 'h2}"); qi = d.find_first_index with (item == 2); `checkp(qi, "'{'h1}"); qi = d.find_last_index with (item == 2); `checkp(qi, "'{'h2}"); i = 2; qi = d.find_index with (item == i); qi.sort; `checkp(qi, "'{'h1, 'h2}"); qi = d.find_index with (item == 20); qi.sort; `checkh(qi.size, 0); qi = d.find_first_index with (item == 20); `checkh(qi.size, 0); qi = d.find_last_index with (item == 20); `checkh(qi.size, 0); qi = d.find_index with (item.index == 2); `checkp(qi, "'{'h2}"); qv = d.min; `checkp(qv, "'{'h1}"); qv = d.max; `checkp(qv, "'{'h4}"); qv = de.min; `checkp(qv, "'{}"); qv = de.max; `checkp(qv, "'{}"); // Reduction methods i = d.sum; `checkh(i, 32'hc); i = d.sum with (item + 1); `checkh(i, 32'h11); i = d.sum(myi) with (myi + 1); `checkh(i, 32'h11); i = d.sum with (1); // unused 'index' `checkh(i, 32'h5); i = d.sum(unused) with (1); // unused 'unused' `checkh(i, 32'h5); i = d.product; `checkh(i, 32'h30); i = d.product with (item + 1); `checkh(i, 32'h168); i = de.sum; `checkh(i, 32'h0); i = de.product; `checkh(i, 32'h0); d = '{32'b1100, 32'b1010}; i = d.and; `checkh(i, 32'b1000); i = d.and with (item + 1); `checkh(i, 32'b1001); i = d.or; `checkh(i, 32'b1110); i = d.or with (item + 1); `checkh(i, 32'b1111); i = d.xor; `checkh(i, 32'b0110); i = d.xor with (item + 1); `checkh(i, 32'b0110); i = de.and; `checkh(i, 32'b0); i = de.or; `checkh(i, 32'b0); i = de.xor; `checkh(i, 32'b0); `checks(s[1], "sad"); qi = s.find_first_index with (item == "sad"); `checkh(qi.size, 1); `checkh(qi[0], 1); qi = s.find_last_index with (item == "sad"); `checkh(qi.size, 1); `checkh(qi[0], 2); d = '{1, 2}; de = '{1, 2}; `checkh(d == de, 1'b1); `checkh(d != de, 1'b0); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_assert_basic_cover.py0000755000542200017500000000150215101701376023624 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_assert_basic.v" test.compile(verilator_flags2=['--assert --cc --coverage-user']) test.execute() #Needs work print("-Info: NOT checking for coverage") #test.file_grep(test.coverage_filename, r't=>'psl_cover',o=>'cover',c=>2\);') #test.file_grep(test.coverage_filename, r'DefaultClock.*,c=>1\);') #test.file_grep(test.coverage_filename, r'ToggleLogIf.*,c=>9\);') test.passes() verilator-5.042/test_regress/t/t_typename.py0000755000542200017500000000100315101701376021602 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_struct_nest_uarray.v0000644000542200017500000000174615101701376023550 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); typedef struct { struct { struct { logic [31:0] next; } val; } el[1]; } pstr_t; module t; typedef struct { struct { struct { logic [31:0] next; } val; } el[1]; } str_t; str_t str; pstr_t pstr; initial begin str.el[0].val.next = 6; `checkp(str, "'{el:'{'{val:'{next:'h6}}}}"); pstr.el[0].val.next = 6; `checkp(str, "'{el:'{'{val:'{next:'h6}}}}"); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_cover_main.out0000644000542200017500000000014015101701376022257 0ustar mahmoudyfreeshell# SystemC::Coverage-3 C 'ft/t_cover_main.vl9n4tlinepagev_line/toblockS9-11ht' 1 verilator-5.042/test_regress/t/t_user_type_xassign.py0000755000542200017500000000073415101701376023545 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_if_deep.v0000644000542200017500000001357315101701376021204 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [31:0] out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out (out[31:0]), // Inputs .clk (clk), .in (in[31:0])); // Aggregate outputs into a single result vector wire [63:0] result = {32'h0, out}; // What checksum will we end up with `define EXPECTED_SUM 64'h966e272fd829e672 // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs out, // Inputs clk, in ); input clk; input [31:0] in; output [31:0] out; /*AUTOREG*/ // Beginning of automatic regs (for this module's undeclared outputs) reg [31:0] out; // End of automatics `ifdef verilator `define dontOptimize $c1("1") `else `define dontOptimize 1'b1 `endif always @(posedge clk) begin out <= in; // verilog_format: off if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (in[0]) out <= ~in; // verilog_format: on end endmodule verilator-5.042/test_regress/t/t_enum_overlap_bad.out0000644000542200017500000000065315101701376023450 0ustar mahmoudyfreeshell%Error: t/t_enum_overlap_bad.v:12:11: Overlapping enumeration value: 'e1b' : ... note: In instance 't' 12 | e1b=1 | ^~~ t/t_enum_overlap_bad.v:10:11: ... Location of original declaration 10 | e1, | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_time_stamp64.py0000755000542200017500000000116215101701376022302 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') # Verilator before 4.033 had 'double sc_time_stamp()', make sure new form compiles test.vl_time_stamp64 = True test.compile(verilator_flags2=['-DVL_TIME_STAMP64=1']) test.execute() test.passes() verilator-5.042/test_regress/t/t_fallback_bad.py0000755000542200017500000000076615101701376022344 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_wrapper_reuse_context_bad.out0000644000542200017500000000021315101701376025373 0ustar mahmoudyfreeshell%Error: Adding model 'TOP' when time is non-zero. ... Suggest check time(), or for restarting model use a new VerilatedContext Aborting... verilator-5.042/test_regress/t/t_clocking_virtual.py0000755000542200017500000000077115101701376023332 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_assert_sampled.py0000755000542200017500000000077115101701376023001 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--assert']) test.execute() test.passes() verilator-5.042/test_regress/t/t_randomize_method_nclass_bad.v0000644000542200017500000000045015101701376025300 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin randomize(1); srandom(1); end endmodule verilator-5.042/test_regress/t/t_covergroup_unsup_ign.py0000755000542200017500000000110615101701376024246 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_covergroup_unsup.v" test.lint(verilator_flags2=['--assert --coverage --Wno-COVERIGN +define+T_COVERGROUP_UNSUP_IGN']) test.passes() verilator-5.042/test_regress/t/t_class_extends_int_param_bad.out0000644000542200017500000000055315101701376025644 0ustar mahmoudyfreeshell%Error: t/t_class_extends_int_param_bad.v:9:23: Attempting to extend using non-class : ... note: In instance 't' 9 | class Bar #(type T=int) extends T; | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_var_pins_bad.py0000755000542200017500000000107215101701376022415 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = 't/t_EXAMPLE.v' test.lint(verilator_flags2=["--pins-bv 99"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_assert_synth_parallel.py0000755000542200017500000000133615101701376024373 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_assert_synth.v" test.compile(v_flags2=['+define+FAILING_PARALLEL', '+define+ATTRIBUTES'], verilator_flags2=['--assert'], nc_flags2=['+assert']) test.execute(check_finished=False, fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_param_named.py0000755000542200017500000000073415101701376022236 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_case_enum_incomplete_bad.py0000755000542200017500000000102515101701376024750 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=['--assert'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_gen_defparam_nfound_bad.out0000644000542200017500000000041115101701376024725 0ustar mahmoudyfreeshell%Error: t/t_gen_defparam_nfound_bad.v:9:17: In defparam, instance z never declared 9 | defparam z.W = 3; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_preproc_defarg_bad.out0000644000542200017500000000116315101701376023733 0ustar mahmoudyfreeshell%Error: t/t_preproc_defarg_bad.v:13:4: Illegal text before '(' that starts define arguments ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_preproc_defarg_bad.v:13:8: Define passed too many arguments: A1 %Error: t/t_preproc_defarg_bad.v:15:4: Illegal text before '(' that starts define arguments %Error: t/t_preproc_defarg_bad.v:16:10: Define passed too many arguments: A2 %Error: t/t_preproc_defarg_bad.v:21:1: EOF in define argument list %Error: t/t_preproc_defarg_bad.v:21:1: Expecting ( to begin argument list for define reference `A2 %Error: Exiting due to verilator-5.042/test_regress/t/t_expect.py0000755000542200017500000000103315101701376021253 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert --timing'], fails=True) test.passes() verilator-5.042/test_regress/t/t_display_wide.py0000755000542200017500000000100015101701376022432 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_pp_circdef_bad.v0000644000542200017500000000070315101701376022504 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // // bug445 `define WIDTH 12 `define SEL_NUM_BITS `WIDTH-`SEL_NUM_BITS +: `SEL_NUM_BITS `define SEL_BITS `WIDTH-`SEL_NUM_BITS +: `SEL_NUM_BITS `define ADDR_BITS 0 +: `WIDTH-`SEL_NUM_BITS typedef logic [`SEL_NUM_BITS-1:0] d_t; verilator-5.042/test_regress/t/t_case_orig.py0000755000542200017500000000073415101701376021725 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_var_ref_bad3.py0000755000542200017500000000076315101701376022311 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_select_plusloop.py0000755000542200017500000000073415101701376023206 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_udp_bad_multi_output.py0000755000542200017500000000076615101701376024227 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface_generic_modport_bad3.v0000644000542200017500000000106615101701376025674 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 interface inf; int v; int o; modport mp ( input o ); endinterface module GenericModule (interface.mp a); initial begin #1; if (a.v != 7) $stop; end endmodule module t; inf inf_inst(); GenericModule genericModule (inf_inst); initial begin inf_inst.v = 7; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_param_implicit_bad.py0000755000542200017500000000076615101701376023577 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_flag_values_bad.out0000644000542200017500000000045715101701376023246 0ustar mahmoudyfreeshell%Error: --output-split-cfuncs must be >= 0: -1 ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: --output-split-ctrace must be >= 0: -1 %Error: --preproc-token-limit must be > 0: 0 %Error: --reloop-limit must be >= 2: -1 %Error: Exiting due to verilator-5.042/test_regress/t/t_class_builtin_bad.py0000755000542200017500000000076615101701376023440 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_gen_cond_bitrange.py0000755000542200017500000000073415101701376023421 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_langext_3.py0000755000542200017500000000100715101701376021650 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') # This is a compile only test. test.compile(v_flags2=["+1364-2005ext+v"]) test.passes() verilator-5.042/test_regress/t/t_timing_wait2.v0000644000542200017500000000117715101701376022203 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; bit s[3:0] = {0, 0, 0, 0}; initial begin wait (s[1]); s[0] = 1; $display("0"); end initial begin wait (s[2]); s[1] = 1; $display("1"); #1 $write("*-* All Finished *-*\n"); $finish; end initial begin wait (s[3]); s[2] = 1; $display("2"); end initial begin s[3] = 1; end initial #2 $stop; // timeout endmodule verilator-5.042/test_regress/t/t_class_super_bad3.out0000644000542200017500000000042215101701376023354 0ustar mahmoudyfreeshell%Error: t/t_class_super_bad3.v:10:5: Syntax error: 'super' must be first name component, or after 'this.' 10 | i.super.i = 1; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_cover_lib__4.out0000644000542200017500000000002615101701376022466 0ustar mahmoudyfreeshell# SystemC::Coverage-3 verilator-5.042/test_regress/t/t_force_port_inline.py0000755000542200017500000000076715101701376023500 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(verilator_flags2=['--binary']) test.execute() test.passes() verilator-5.042/test_regress/t/t_class_extends2.v0000644000542200017500000000521115101701376022520 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package Pkg; class Base0; class BaseInnerOnly; int inneronly; function new(); inneronly = 10; if (inneronly != 10) $stop; endfunction endclass class BaseInnerOver; int innerover; function new(); innerover = 10; if (innerover != 10) $stop; endfunction endclass int baseonly; int baseover; BaseInnerOnly inneronly = new; BaseInnerOver innerover = new; function void b_set_bo(int v); baseover = v; endfunction function int b_get_bo(); return baseover; endfunction function int get_bo(); return baseover; endfunction function void b_set_io(int v); innerover.innerover = v; endfunction function int b_get_io(); return innerover.innerover; endfunction function int get_io(); return innerover.innerover; endfunction endclass endpackage // We need to import Base0, as verilator currently doesn't support // multiple `::` references, but we would need to do that to reference // `BaseInnerOnly` class inside `Ext` class. import Pkg::Base0; class Ext extends Pkg::Base0; class BaseInnerOver; int innerover; function new(); innerover = 20; if (innerover != 20) $stop; endfunction endclass int baseover; int extonly; BaseInnerOnly inneronly = new; BaseInnerOver innerover = new; function void e_set_bo(int v); baseover = v; endfunction function int e_get_bo(); return baseover; endfunction function int get_bo(); return baseover; endfunction function void e_set_io(int v); innerover.innerover = v; endfunction function int e_get_io(); return innerover.innerover; endfunction function int get_io(); return innerover.innerover; endfunction endclass module t; initial begin Ext c; c = new; c.baseonly = 10; c.baseover = 20; c.extonly = 30; c.inneronly.inneronly = 40; c.innerover.innerover = 50; if (c.baseonly != 10) $stop; if (c.baseover != 20) $stop; if (c.extonly != 30) $stop; if (c.inneronly.inneronly != 40) $stop; if (c.innerover.innerover != 50) $stop; c.b_set_bo(100); c.e_set_bo(200); c.b_set_io(300); c.e_set_io(400); if (c.b_get_bo() != 100) $stop; if (c.e_get_bo() != 200) $stop; if (c.get_bo() != 200) $stop; if (c.b_get_io() != 300) $stop; if (c.e_get_io() != 400) $stop; if (c.get_io() != 400) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_forceable_public_flat.py0000755000542200017500000000126115101701376024254 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() files = test.glob_some(test.obj_dir + "/" + test.vm_prefix + "*.h") test.file_grep_any(files, r' u_sub__DOT__a__VforceRd') test.file_grep_any(files, r' u_sub__DOT__a__VforceEn') test.file_grep_any(files, r' u_sub__DOT__a__VforceVal') test.passes() verilator-5.042/test_regress/t/t_implements_collision_bad.py0000755000542200017500000000076615101701376025035 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_struct_unaligned.py0000755000542200017500000000107515101701376023343 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') # Note: need to run at a higher optimization level to reproduce the issue test.benchmark = True test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_vpi_const_type.v0000644000542200017500000000207615101701376022652 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2010 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import "DPI-C" context function int mon_check(); module t (/*AUTOARG*/ ); /*verilator public_module*/ parameter int intParam /*verilator public_flat_rd*/ = 5; parameter real realParam /*verilator public_flat_rd*/ = 2.3; parameter time timeParam /*verilator public_flat_rd*/ = 0; parameter string strParam /*verilator public_flat_rd*/ = "abc"; logic [31:0] signal_rw /*verilator public_flat_rw*/; logic [31:0] signal_rd /*verilator public_flat_rd*/; int status; initial begin status = mon_check(); if (status!=0) begin $write("%%Error: t_vpi_const_type.cpp:%0d: C Test failed\n", status); $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule : t verilator-5.042/test_regress/t/t_class_func_nvoid_bad.v0000644000542200017500000000307115101701376023726 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls; function int fi(); return 10; endfunction function void fv(); endfunction task t(); endtask static function int sfi(); return 10; endfunction static function void sfv(); endfunction static task st(); endtask endclass module t; function int mod_fi(); return 10; endfunction function void mod_fv(); endfunction task mod_t(); endtask initial begin Cls c; c = new; // For test of calling function in void context, see t_func_void_bad.v // Module if (mod_fi() != 10) $stop; // OK void'(mod_fi()); // OK mod_fv(); // Warn IGNOREDRETURN void'(mod_fv()); // OK if (mod_fv() == 10) $stop; // Bad call of task as function mod_t(); // OK if (mod_t() == 10) $stop; // Bad call of task as function // Member functions if (c.fi() != 10) $stop; // OK void'(c.fi()); // OK c.fv(); // Ok void'(c.fv()); // OK if (c.fv() == 10) $stop; // Bad c.t(); // OK if (c.t() == 10) $stop; // Bad // Static member functions if (c.sfi() != 10) $stop; // OK void'(c.sfi()); // OK c.sfv(); // Ok void'(c.sfv()); // OK if (c.sfv() == 10) $stop; // Bad c.st(); // OK if (c.st() == 10) $stop; // Bad $stop; end endmodule verilator-5.042/test_regress/t/t_const_overflow_bad.py0000755000542200017500000000076615101701376023656 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_cover_assert.out0000644000542200017500000000043515101701376022643 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_cover_assert.v:42:16: Unsupported: Assert not allowed under another assert 42 | A2: assert (b); | ^~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_inst_darray.py0000755000542200017500000000073415101701376022311 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_var_sc_bv.v0000644000542200017500000001403615101701376021550 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2008 by Lane Brooks. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs o_29,o_29_old, o_30,o_30_old, o_31,o_31_old, o_32,o_32_old, o_59,o_59_old, o_60,o_60_old, o_62,o_62_old, o_64,o_64_old, o_119,o_119_old, o_120,o_120_old, o_121,o_121_old, o_127,o_127_old, o_128,o_128_old, o_255,o_255_old, o_256,o_256_old, // Inputs i_29,i_29_old, i_30,i_30_old, i_31,i_31_old, i_32,i_32_old, i_59,i_59_old, i_60,i_60_old, i_62,i_62_old, i_64,i_64_old, i_119,i_119_old, i_120,i_120_old, i_121,i_121_old, i_127,i_127_old, i_128,i_128_old, i_255,i_255_old, i_256,i_256_old ); input [255:0] i_29; output wire [255:0] o_29; input [255:0] i_29_old; output wire [255:0] o_29_old; input [255:0] i_30; output wire [255:0] o_30; input [255:0] i_30_old; output wire [255:0] o_30_old; input [255:0] i_31; output wire [255:0] o_31; input [255:0] i_31_old; output wire [255:0] o_31_old; input [255:0] i_32; output wire [255:0] o_32; input [255:0] i_32_old; output wire [255:0] o_32_old; input [255:0] i_59; output wire [255:0] o_59; input [255:0] i_59_old; output wire [255:0] o_59_old; input [255:0] i_60; output wire [255:0] o_60; input [255:0] i_60_old; output wire [255:0] o_60_old; input [255:0] i_62; output wire [255:0] o_62; input [255:0] i_62_old; output wire [255:0] o_62_old; input [255:0] i_64; output wire [255:0] o_64; input [255:0] i_64_old; output wire [255:0] o_64_old; input [255:0] i_119; output wire [255:0] o_119; input [255:0] i_119_old; output wire [255:0] o_119_old; input [255:0] i_120; output wire [255:0] o_120; input [255:0] i_120_old; output wire [255:0] o_120_old; input [255:0] i_121; output wire [255:0] o_121; input [255:0] i_121_old; output wire [255:0] o_121_old; input [255:0] i_127; output wire [255:0] o_127; input [255:0] i_127_old; output wire [255:0] o_127_old; input [255:0] i_128; output wire [255:0] o_128; input [255:0] i_128_old; output wire [255:0] o_128_old; input [255:0] i_255; output wire [255:0] o_255; input [255:0] i_255_old; output wire [255:0] o_255_old; input [255:0] i_256; output wire [255:0] o_256; input [255:0] i_256_old; output wire [255:0] o_256_old; sub sub (.*); endmodule module sub (/*AUTOARG*/ // Outputs o_29,o_29_old, o_30,o_30_old, o_31,o_31_old, o_32,o_32_old, o_59,o_59_old, o_60,o_60_old, o_62,o_62_old, o_64,o_64_old, o_119,o_119_old, o_120,o_120_old, o_121,o_121_old, o_127,o_127_old, o_128,o_128_old, o_255,o_255_old, o_256,o_256_old, // Inputs i_29,i_29_old, i_30,i_30_old, i_31,i_31_old, i_32,i_32_old, i_59,i_59_old, i_60,i_60_old, i_62,i_62_old, i_64,i_64_old, i_119,i_119_old, i_120,i_120_old, i_121,i_121_old, i_127,i_127_old, i_128,i_128_old, i_255,i_255_old, i_256,i_256_old ); input [255:0] i_29; output wire [255:0] o_29; input [255:0] i_29_old; output wire [255:0] o_29_old; input [255:0] i_30; output wire [255:0] o_30; input [255:0] i_30_old; output wire [255:0] o_30_old; input [255:0] i_31; output wire [255:0] o_31; input [255:0] i_31_old; output wire [255:0] o_31_old; input [255:0] i_32; output wire [255:0] o_32; input [255:0] i_32_old; output wire [255:0] o_32_old; input [255:0] i_59; output wire [255:0] o_59; input [255:0] i_59_old; output wire [255:0] o_59_old; input [255:0] i_60; output wire [255:0] o_60; input [255:0] i_60_old; output wire [255:0] o_60_old; input [255:0] i_62; output wire [255:0] o_62; input [255:0] i_62_old; output wire [255:0] o_62_old; input [255:0] i_64; output wire [255:0] o_64; input [255:0] i_64_old; output wire [255:0] o_64_old; input [255:0] i_119; output wire [255:0] o_119; input [255:0] i_119_old; output wire [255:0] o_119_old; input [255:0] i_120; output wire [255:0] o_120; input [255:0] i_120_old; output wire [255:0] o_120_old; input [255:0] i_121; output wire [255:0] o_121; input [255:0] i_121_old; output wire [255:0] o_121_old; input [255:0] i_127; output wire [255:0] o_127; input [255:0] i_127_old; output wire [255:0] o_127_old; input [255:0] i_128; output wire [255:0] o_128; input [255:0] i_128_old; output wire [255:0] o_128_old; input [255:0] i_255; output wire [255:0] o_255; input [255:0] i_255_old; output wire [255:0] o_255_old; input [255:0] i_256; output wire [255:0] o_256; input [255:0] i_256_old; output wire [255:0] o_256_old; assign o_29 = i_29; assign o_29_old = i_29_old; assign o_30 = i_30; assign o_30_old = i_30_old; assign o_31 = i_31; assign o_31_old = i_31_old; assign o_32 = i_32; assign o_32_old = i_32_old; assign o_59 = i_59; assign o_59_old = i_59_old; assign o_60 = i_60; assign o_60_old = i_60_old; assign o_62 = i_62; assign o_62_old = i_62_old; assign o_64 = i_64; assign o_64_old = i_64_old; assign o_119 = i_119; assign o_119_old = i_119_old; assign o_120 = i_120; assign o_120_old = i_120_old; assign o_121 = i_121; assign o_121_old = i_121_old; assign o_127 = i_127; assign o_127_old = i_127_old; assign o_128 = i_128; assign o_128_old = i_128_old; assign o_255 = i_255; assign o_255_old = i_255_old; assign o_256 = i_256; assign o_256_old = i_256_old; endmodule verilator-5.042/test_regress/t/t_split_var_4.py0000755000542200017500000000133015101701376022211 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--stats', '-DENABLE_SPLIT_VAR=1', "-fno-dfg"]) test.execute() test.file_grep(test.stats, r'SplitVar,\s+packed variables split due to attribute\s+(\d+)', 1) test.file_grep(test.stats, r'SplitVar,\s+unpacked arrays split due to attribute\s+(\d+)', 0) test.passes() verilator-5.042/test_regress/t/t_class_scope_import_bad.py0000755000542200017500000000076615101701376024475 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_trace_dumpvars_dyn_fst_0.py0000755000542200017500000000130315101701376024747 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_trace_dumpvars_dyn.cpp" test.top_filename = "t/t_trace_dumpvars_dyn.v" test.compile(make_main=False, verilator_flags2=["--trace-fst --exe", test.pli_filename]) test.execute() test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_static_order.py0000755000542200017500000000073415101701376023641 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_unroll_unopt_io.v0000644000542200017500000000105115101701376023024 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Outputs zeros, // Inputs num ); parameter WIDTH = 1; input logic [WIDTH-1:0] num; output logic [$clog2(WIDTH+1)-1:0] zeros; integer i; always_comb begin i = 0; while ((i < WIDTH) & ~num[WIDTH-1-i]) i = i + 1; zeros = i[$clog2(WIDTH+1) - 1 : 0]; end endmodule verilator-5.042/test_regress/t/t_class_param_subtype_bad_paren.out0000644000542200017500000000055015101701376026175 0ustar mahmoudyfreeshell%Error: t/t_class_param_subtype.v:32:5: Reference to parameterized class without #() (IEEE 1800-2023 8.25.1) : ... Suggest use 'CParam#()' 32 | CParam::type_t val_0 = 100; | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_incr_void.v0000644000542200017500000000233115101701376021553 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Drew Ranck. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; int cyc = 0; always @ (posedge clk) begin : main cyc <= cyc + 1; if (cyc > 100) begin $write("*-* All Finished *-*\n"); $finish(); end end logic [3:0] count_d; logic [3:0] count_q = '0; logic [3:0] want_count_d; logic [3:0] want_count_q = '0; always_ff @(posedge clk) begin : flops count_q <= count_d; want_count_q <= want_count_d; end always @(posedge clk) begin : simple_check if (cyc > 0) begin if (count_q !== want_count_q) begin $error("%m: cyc=%0d, count_q (%0d) !== want_count_q (%0d)", cyc, count_q, want_count_q); $stop; // don't finish to fail the test. end end end always_comb begin : update_golden_counts want_count_d = want_count_q; want_count_d += 1'b1; end // make sure an implicit void cast on n++ works as expected. always_comb begin : update_counts count_d = count_q; count_d++; end endmodule verilator-5.042/test_regress/t/t_class_func_static_bad.v0000644000542200017500000000103015101701376024067 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; class C; task static task_st(int x); // BAD - methods have automatic lifetime int y; y = 2 * x; endtask function static int func_st(int x); // BAD - methods have automatic lifetime int y; y = 2 * x; return y; endfunction endclass initial $stop; endmodule verilator-5.042/test_regress/t/t_package_dup_bad2.v0000644000542200017500000000055715101701376022742 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package Pkg; endpackage module t; IOBUF iocell ( .O (in), .IO(pad), .I ('0), .T (~oe) ); endmodule package Pkg; endpackage verilator-5.042/test_regress/t/t_opt_assemble_cellarray_off.py0000755000542200017500000000115215101701376025332 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.top_filename = "t/t_opt_life.v" test.compile(verilator_flags2=['--stats', '-fno-assemble']) test.file_grep_not(test.stats, r'Optimizations, Concat merges\s+(\d+)') test.passes() verilator-5.042/test_regress/t/t_case_onehot.py0000755000542200017500000000073415101701376022261 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_extern_bad.out0000644000542200017500000000167215101701376023450 0ustar mahmoudyfreeshell%Error: t/t_class_extern_bad.v:9:15: Duplicate declaration of task: 'extern nodef' 9 | extern task nodef(); | ^~~~~ t/t_class_extern_bad.v:8:15: ... Location of original declaration 8 | extern task nodef(); | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error-PROTOTYPEMIS: t/t_class_extern_bad.v:8:15: Definition not found for extern prototype 'nodef' 8 | extern task nodef(); | ^~~~~ ... For error description see https://verilator.org/warn/PROTOTYPEMIS?v=latest %Error-PROTOTYPEMIS: t/t_class_extern_bad.v:9:15: Definition not found for extern prototype 'nodef' 9 | extern task nodef(); | ^~~~~ %Error: t/t_class_extern_bad.v:12:6: extern not found that declares 'noproto' 12 | task Base1::noproto(); | ^~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_init_concat.v0000644000542200017500000000443515101701376022100 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg [31:0] wr_data; reg wr_en; wire [31:0] rd_data; wire [1:0] rd_guards; wire [1:0] rd_guardsok; regfile regfile (/*AUTOINST*/ // Outputs .rd_data (rd_data[31:0]), .rd_guards (rd_guards[1:0]), .rd_guardsok (rd_guardsok[1:0]), // Inputs .wr_data (wr_data[31:0]), .wr_en (wr_en), .clk (clk)); initial wr_en = 0; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin if (!rd_guards[0]) $stop; if (!rd_guardsok[0]) $stop; wr_en <= 1'b1; wr_data <= 32'hfeedf; end if (cyc==2) begin wr_en <= 0; end if (cyc==3) begin wr_en <= 0; if (rd_data != 32'hfeedf) $stop; if (rd_guards != 2'b11) $stop; if (rd_guardsok != 2'b11) $stop; end if (cyc==4) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module regfile ( input [31:0] wr_data, input wr_en, output reg [31:0] rd_data, output [1:0] rd_guards /*verilator public*/, output [1:0] rd_guardsok /*verilator public*/, input clk ); always @(posedge clk) begin if (wr_en) begin rd_data <= wr_data; end end // this initial statement will induce correct initialize behavior // initial rd_guards= { 2'b11 }; assign rd_guards= { rd_data[0], 1'b1 }; assign rd_guardsok[0] = 1'b1; assign rd_guardsok[1] = rd_data[0]; endmodule // regfile verilator-5.042/test_regress/t/t_class_param_nconst_bad.v0000644000542200017500000000051115101701376024254 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls #(parameter PARAM = 12); endclass module t; Cls #(.PARAM($random)) c; // Bad param name endmodule verilator-5.042/test_regress/t/t_dfg_multidriver_dfg_bad.py0000755000542200017500000000111315101701376024576 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["-fdfg-synthesize-all", "-fno-const-before-dfg"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_runflag_quiet.v0000644000542200017500000000054615101701376022452 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 timeunit 1us; timeprecision 1ns; module t; initial begin #10; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_var_nonamebegin__log.out0000644000542200017500000000050715101701376024276 0ustar mahmoudyfreeshellingen: {mod}.genblk1 top.t.genblk1 d3a: {mod}.d3nameda top.t.unnamedblk1.d3nameda b2: {mod} top.t.unnamedblk2 b3n: {mod}.b3named: top.t.unnamedblk2.b3named b3: {mod} top.t.unnamedblk2.unnamedblk3 b4: {mod} top.t.unnamedblk2.unnamedblk3.unnamedblk4 t1 {mod}.tsk top.t.tsk t2 {mod}.tsk top.t.tsk.unnamedblk7 *-* All Finished *-* verilator-5.042/test_regress/t/t_randomize_method_with.v0000644000542200017500000001057015101701376024166 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `define check_rand(cl, field) \ begin \ longint prev_result; \ int ok = 0; \ void'(cl.randomize()); \ prev_result = longint'(field); \ repeat(9) begin \ longint result; \ void'(cl.randomize()); \ result = longint'(field); \ if (result != prev_result) ok = 1; \ prev_result = result; \ end \ if (ok != 1) $stop; \ end class Boo; function new(); boo = 6; endfunction int unsigned boo; endclass class Foo extends Boo; rand int unsigned a; rand int unsigned b; int x; function new(int x); this.x = x; endfunction constraint constr1_c { b < x; } function bit test_this_randomize; return this.randomize() with { a <= boo; } == 1; endfunction endclass // Current AstWith representation makes VARs of caller indistinguishable from VARs of randomized // object if both the caller and callee are the same module, but different instances. // That's why for the purpose of this test, the caller derives a different class class Bar extends Boo; // Give the local variables a different scope by defining the functino under Bar static function bit test_local_constrdep(Foo foo, int c); return foo.randomize() with { a <= c; a > 1; x % a == 0; } == 1; endfunction function bit test_capture_of_callers_derived_var(Foo foo); boo = 4; foo.a = 3; return (foo.randomize() with { a == local::boo; } == 1) && (foo.a == 4); endfunction static function bit test_capture_of_callees_derived_var(Foo foo); foo.a = 5; return (foo.randomize() with { a == boo; } == 1) && (foo.a == 6); endfunction static function bit test_capture_of_local_qualifier(Foo foo); foo.a = 5; return (foo.randomize() with { a == boo; } == 1) && (foo.a == 6); endfunction endclass class Baz; rand int v; endclass class Baz2; rand int v; function bit test_this_randomize; return this.randomize() with { v == 5; } == 1; endfunction endclass module submodule(); int sub_var = 7; endmodule function automatic int return_2(); return 2; endfunction class Cls; rand int a; rand int b; endclass class Cls2 extends Cls; rand int c; endclass module mwith(); submodule sub1(); submodule sub2(); function automatic int return_3(); return 3; endfunction initial begin int c = 30; Foo foo = new(c); Baz baz = new; typedef Baz baz_t; baz_t baz1 = new; Baz2 baz2 = new; Bar bar = new; Cls2 cls2 = new; Cls cls = cls2; $display("foo.x = %d", foo.x); $display("-----------------"); repeat (20) begin if (Bar::test_local_constrdep(foo, 5)) begin $display("foo.a = %d", foo.a); $display("foo.b = %d", foo.b); $display("-----------------"); if (!(foo.a inside {2, 3, 5})) $stop; if (foo.b >= foo.x) $stop; if (foo.a > c) $stop; if (foo.a <= 1) $stop; sub1.sub_var = foo.a; end else $display("Failed to randomize foo with inline constraints"); end if (cls.randomize() with { b == 1;} != 1) $stop; if (cls.b != 1) $stop; `check_rand(cls2, cls2.a); `check_rand(cls2, cls2.c); // Check randomize as a task // verilator lint_off IGNOREDRETURN cls.randomize() with { b == 2;}; // verilator lint_on IGNOREDRETURN if (cls.b != 2) $stop; // Check capture of a static variable if (foo.randomize() with { a > sub1.sub_var; } != 1) $stop; // Check reference to a function if (foo.randomize() with { a > return_2(); } != 1) $stop; // Check randomization of class with no constraints if (baz.randomize() with { v inside {[2:10]}; } != 1) $stop; if (baz1.randomize() with { v inside {[2:10]}; } != 1) $stop; // Check randomization with captured non-static variable from different AstNodeModule if (!bar.test_capture_of_callers_derived_var(foo)) $stop; // Check randomization with non-captured non-static variable from different AstNodeModule if (!Bar::test_capture_of_callees_derived_var(foo)) $stop; // Check this.randomize() if (!foo.test_this_randomize()) $stop; // Check this.randomize() with no constraints if (!baz2.test_this_randomize()) $stop; $write("*-* All Finished *-*\n"); $finish(); end endmodule verilator-5.042/test_regress/t/t_sys_readmem_s.mem0000644000542200017500000000055715101701376022752 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test data file // // Copyright 2006 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 @4 654 @a 65a 65b 65c verilator-5.042/test_regress/t/t_class_method_str_literal.py0000755000542200017500000000073415101701376025043 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_local_typedef_bad.out0000644000542200017500000000141115101701376024744 0ustar mahmoudyfreeshell%Error-ENCAPSULATED: t/t_class_local_typedef_bad.v:13:8: 't1' is hidden as 'local' within this context (IEEE 1800-2023 8.18) 13 | Cls::t1 var1; | ^~ t/t_class_local_typedef_bad.v:13:8: ... Location of definition 9 | local typedef bit t1; | ^~ ... For error description see https://verilator.org/warn/ENCAPSULATED?v=latest %Error-ENCAPSULATED: t/t_class_local_typedef_bad.v:14:8: 't2' is hidden as 'protected' within this context (IEEE 1800-2023 8.18) 14 | Cls::t2 var2; | ^~ t/t_class_local_typedef_bad.v:14:8: ... Location of definition 10 | protected typedef bit t2; | ^~ %Error: Exiting due to verilator-5.042/test_regress/t/t_class_extern_typeref.py0000755000542200017500000000073415101701376024222 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_cast_param_logic.v0000644000542200017500000000065615101701376023076 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t #( parameter type data_t = logic ) ( input data_t[7:0] in_data ); typedef data_t[7:0] in_data_t; in_data_t out_data; always_comb out_data = in_data_t'(in_data); endmodule verilator-5.042/test_regress/t/t_assoc2.v0000644000542200017500000000244015101701376020772 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; int imap[int]; // associative array of an associative array logic [31:0] a [logic [31:0]][logic [63:0]]; task static disp(); int i = 60; imap[i++] = 600; imap[i++] = 601; foreach (imap[k]) $display("imap[%0d] = %0d", k, imap[k]); endtask always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 1) begin a[5][8] = 8; a[5][9] = 9; imap[10] = 100; imap[11] = 101; end else if (cyc == 2) begin `checkh(a[5][8], 8); `checkh(a[5][9], 9); disp(); $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_preproc_eof1_bad.out0000644000542200017500000000030115101701376023326 0ustar mahmoudyfreeshell%Error: t/t_preproc_eof1_bad.v:9:1: EOF in '/* ... */' block comment ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_enum_int.v0000644000542200017500000000555715101701376021432 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; enum integer { EP_State_IDLE , EP_State_CMDSHIFT0 , EP_State_CMDSHIFT13 , EP_State_CMDSHIFT14 , EP_State_CMDSHIFT15 , EP_State_CMDSHIFT16 , EP_State_DWAIT , EP_State_DSHIFT0 , EP_State_DSHIFT1 , EP_State_DSHIFT15 } m_state_xr, m_state2_xr; // Beginning of automatic ASCII enum decoding reg [79:0] m_stateAscii_xr; // Decode of m_state_xr always @(m_state_xr) begin case ({m_state_xr}) EP_State_IDLE: m_stateAscii_xr = "idle "; EP_State_CMDSHIFT0: m_stateAscii_xr = "cmdshift0 "; EP_State_CMDSHIFT13: m_stateAscii_xr = "cmdshift13"; EP_State_CMDSHIFT14: m_stateAscii_xr = "cmdshift14"; EP_State_CMDSHIFT15: m_stateAscii_xr = "cmdshift15"; EP_State_CMDSHIFT16: m_stateAscii_xr = "cmdshift16"; EP_State_DWAIT: m_stateAscii_xr = "dwait "; EP_State_DSHIFT0: m_stateAscii_xr = "dshift0 "; EP_State_DSHIFT1: m_stateAscii_xr = "dshift1 "; EP_State_DSHIFT15: m_stateAscii_xr = "dshift15 "; default: m_stateAscii_xr = "%Error "; endcase end // End of automatics integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; //$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b); if (cyc==1) begin m_state_xr <= EP_State_IDLE; m_state2_xr <= EP_State_IDLE; end if (cyc==2) begin if (m_stateAscii_xr != "idle ") $stop; m_state_xr <= EP_State_CMDSHIFT13; if (m_state2_xr != EP_State_IDLE) $stop; m_state2_xr <= EP_State_CMDSHIFT13; end if (cyc==3) begin if (m_stateAscii_xr != "cmdshift13") $stop; m_state_xr <= EP_State_CMDSHIFT16; if (m_state2_xr != EP_State_CMDSHIFT13) $stop; m_state2_xr <= EP_State_CMDSHIFT16; end if (cyc==4) begin if (m_stateAscii_xr != "cmdshift16") $stop; m_state_xr <= EP_State_DWAIT; if (m_state2_xr != EP_State_CMDSHIFT16) $stop; m_state2_xr <= EP_State_DWAIT; end if (cyc==9) begin if (m_stateAscii_xr != "dwait ") $stop; if (m_state2_xr != EP_State_DWAIT) $stop; $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.042/test_regress/t/t_inst_sv.py0000755000542200017500000000073415101701376021457 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_case_write2.v0000644000542200017500000000215315101701376022010 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [63:0] crc; integer fd; integer fdtmp; t_case_write2_tasks tasks (); integer cyc; initial cyc = 0; always @ (posedge clk) begin $fwrite(fd, "[%0d] crc=%x ", cyc, crc); tasks.big_case(fd, crc[31:0]); $fwrite(fd, "\n"); end always @ (posedge clk) begin //$write("[%0t] cyc==%0d crc=%x\n", $time, cyc, crc); cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; if (cyc==1) begin crc <= 64'h00000000_00000097; $write("%s", {"Open ", `STRINGIFY(`TEST_OBJ_DIR), "/t_case_write2_logger.log\n"}); fdtmp = $fopen({`STRINGIFY(`TEST_OBJ_DIR), "/t_case_write2_logger.log"}, "w"); fd <= fdtmp; end if (cyc==90) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_queue_unknown_sel.py0000755000542200017500000000071415101701376023536 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.passes() verilator-5.042/test_regress/t/t_sys_writemem.gold2.mem0000644000542200017500000000003015101701376023637 0ustar mahmoudyfreeshell10 11 12 13 14 15 16 17 verilator-5.042/test_regress/t/t_embed1_wrap.v0000644000542200017500000000531715101701376021774 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t_embed1_wrap (/*AUTOARG*/ // Outputs bit_out, vec_out, wide_out, did_init_out, // Inputs clk, bit_in, vec_in, wide_in, is_ref ); /*AUTOINOUTMODULE("t_embed1_child")*/ // Beginning of automatic in/out/inouts (from specific module) output bit bit_out; output bit [30:0] vec_out; output bit [123:0] wide_out; output bit did_init_out; input clk; input bit_in; input [30:0] vec_in; input [123:0] wide_in; input is_ref; // End of automatics `ifdef verilator // Import $t_embed_child__initial etc as a DPI function `endif //TODO would like __'s as in {PREFIX}__initial but presently illegal for users to do this import "DPI-C" context function void t_embed_child_initial(); import "DPI-C" context function void t_embed_child_final(); import "DPI-C" context function void t_embed_child_eval(); import "DPI-C" context function void t_embed_child_io_eval ( //TODO we support bit, but not logic input bit clk, input bit bit_in, input bit [30:0] vec_in, input bit [123:0] wide_in, input bit is_ref, output bit bit_out, output bit [30:0] vec_out, output bit [123:0] wide_out, output bit did_init_out); initial begin // Load all values t_embed_child_initial(); end // Only if system verilog, and if a "final" block in the code final begin t_embed_child_final(); end bit _temp_bit_out; bit _temp_did_init_out; bit [30:0] _temp_vec_out; bit [123:0] _temp_wide_out; always @* begin t_embed_child_io_eval( clk, bit_in, vec_in, wide_in, is_ref, _temp_bit_out, _temp_vec_out, _temp_wide_out, _temp_did_init_out ); // TODO might eliminate these temporaries bit_out = _temp_bit_out; did_init_out = _temp_did_init_out; end // Send all variables every cycle, // or have a sensitivity routine for each? // How to make sure we call eval at end of variable changes? // #0 (though not verilator compatible!) // TODO for now, we know what changes when always @ (posedge clk) begin vec_out <= _temp_vec_out; wide_out <= _temp_wide_out; end endmodule verilator-5.042/test_regress/t/t_time_vpi_1us1ns.py0000755000542200017500000000140215101701376023011 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.pli_filename = "t/t_time_vpi_c.cpp" test.top_filename = "t/t_time_vpi.v" test.main_time_multiplier = 1e-6 / 1e-9 test.compile( v_flags2=['+define+time_scale_units=1us +define+time_scale_prec=1ns', test.pli_filename], verilator_flags2=['--vpi --trace-vcd']) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_pp_underline_bad.v0000644000542200017500000000062215101701376023072 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; // verilator_no_inline_module initial begin case (1'b1) // synopsys_full_case 1'b0: $stop; endcase $stop; // Should have failed end endmodule verilator-5.042/test_regress/t/t_event_method_bad.v0000644000542200017500000000045115101701376023067 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; event e1; initial begin e1.bad_method(); end endmodule verilator-5.042/test_regress/t/t_class_defaultparam_import.v0000644000542200017500000000044315101701376025025 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 package foo; class bar#(type T=int); endclass endpackage; import foo::bar; verilator-5.042/test_regress/t/t_func_public.v0000644000542200017500000001436215101701376022077 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; tpub p1 (.clk(clk), .i(32'd1)); tpub p2 (.clk(clk), .i(32'd2)); integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin `ifdef verilator $c("this->publicTop();"); `endif end if (cyc==20) begin $write("*-* All Finished *-*\n"); $finish; end end end task publicTop; // verilator public // We have different optimizations if only one of something, so try it out. $write("Hello in publicTop\n"); endtask task test_task(input [19:0] in [2], output [19:0] out [2]); // Issue 3316 // verilator public out[0] = in[1]; out[1] = in[0]; endtask endmodule module tpub ( input clk, input [31:0] i); reg [23:0] var_long; reg [59:0] var_quad; reg [71:0] var_wide; reg var_bool; // verilator lint_off BLKANDNBLK reg [11:0] var_flop; // verilator lint_on BLKANDNBLK reg [23:0] got_long /*verilator public*/; reg [59:0] got_quad /*verilator public*/; reg [71:0] got_wide /*verilator public*/; reg got_bool /*verilator public*/; integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; // cyc==1 is in top level if (cyc==2) begin publicNoArgs; publicSetBool(1'b1); publicSetLong(24'habca); publicSetQuad(60'h4444_3333_2222); publicSetWide(72'h12_5678_9123_1245_2352); var_flop <= 12'habe; end if (cyc==3) begin if (1'b1 != publicGetSetBool(1'b0)) $stop; if (24'habca != publicGetSetLong(24'h1234)) $stop; if (60'h4444_3333_2222 != publicGetSetQuad(60'h123_4567_89ab)) $stop; if (72'h12_5678_9123_1245_2352 != publicGetSetWide(72'hac_abca_aaaa_bbbb_1234)) $stop; end if (cyc==4) begin publicGetBool(got_bool); if (1'b0 != got_bool) $stop; publicGetLong(got_long); if (24'h1234 != got_long) $stop; publicGetQuad(got_quad); if (60'h123_4567_89ab != got_quad) $stop; publicGetWide(got_wide); if (72'hac_abca_aaaa_bbbb_1234 != got_wide) $stop; end // `ifdef VERILATOR_PUBLIC_TASKS if (cyc==11) begin $c("this->publicNoArgs();"); $c("this->publicSetBool(true);"); $c("this->publicSetLong(0x11bca);"); $c("this->publicSetQuad(0x66655554444ULL);"); $c("this->publicSetFlop(0x321);"); //Unsupported: $c("WData w[3] = {0x12, 0x5678_9123, 0x1245_2352}; publicSetWide(w);"); end if (cyc==12) begin $c("this->got_bool = this->publicGetSetBool(true);"); $c("this->got_long = this->publicGetSetLong(0x11bca);"); $c("this->got_quad = this->publicGetSetQuad(0xaaaabbbbccccULL);"); end if (cyc==13) begin $c("{ bool gb; this->publicGetBool(gb); this->got_bool=gb; }"); if (1'b1 != got_bool) $stop; $c("this->publicGetLong(this->got_long);"); if (24'h11bca != got_long) $stop; $c("{ uint64_t qq; this->publicGetQuad(qq); this->got_quad=qq; }"); if (60'haaaa_bbbb_cccc != got_quad) $stop; $c("{ WData gw[3]; this->publicGetWide(gw); VL_ASSIGN_W(72,this->got_wide,gw); }"); if (72'hac_abca_aaaa_bbbb_1234 != got_wide) $stop; //Below doesn't work, because we're calling it inside the loop that sets var_flop // if (12'h321 != var_flop) $stop; end if (cyc==14) begin if ($c32("this->publicInstNum()") != i) $stop; end `endif end end task publicEmpty; // verilator public begin end endtask task publicNoArgs; // verilator public $write("Hello in publicNoArgs\n"); endtask task publicSetBool; // verilator public input in_bool; var_bool = in_bool; endtask task publicSetLong; // verilator public input [23:0] in_long; reg [23:0] not_long; begin not_long = ~in_long; // Test that we can have local variables var_long = ~not_long; end endtask task publicSetQuad; // verilator public input [59:0] in_quad; var_quad = in_quad; endtask task publicSetFlop; // verilator public input [11:0] in_flop; var_flop = in_flop; endtask task publicSetWide; // verilator public input [71:0] in_wide; var_wide = in_wide; endtask task publicGetBool; // verilator public output out_bool; out_bool = var_bool; endtask task publicGetLong; // verilator public output [23:0] out_long; out_long = var_long; endtask task publicGetQuad; // verilator public output [59:0] out_quad; out_quad = var_quad; endtask task publicGetWide; // verilator public output [71:0] out_wide; out_wide = var_wide; endtask function publicGetSetBool; // verilator public input in_bool; begin publicGetSetBool = var_bool; var_bool = in_bool; end endfunction function [23:0] publicGetSetLong; // verilator public input [23:0] in_long; begin publicGetSetLong = var_long; var_long = in_long; end endfunction function [59:0] publicGetSetQuad; // verilator public input [59:0] in_quad; begin publicGetSetQuad = var_quad; var_quad = in_quad; end endfunction function [71:0] publicGetSetWide; // Can't be public, as no wide return types in C++ input [71:0] in_wide; begin publicGetSetWide = var_wide; var_wide = in_wide; end endfunction `ifdef VERILATOR_PUBLIC_TASKS function [31:0] publicInstNum; // verilator public publicInstNum = i; endfunction `endif endmodule verilator-5.042/test_regress/t/t_dpi_var.v0000644000542200017500000000715015101701376021227 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2010 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; wire monclk = ~clk; int in; int in_a; int in_b; int fr_a; int fr_b; int fr_a2; int fr_b2; int fr_chk; sub sub (.*); // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d in=%x sub.in_a=%x sub.in_b=%x fr_a=%x fr_b=%x fr_a2=%x fr_b2=%x fr_chk=%x\n", $time, cyc, in, sub.in_a, sub.in_b, fr_a, fr_b, fr_a2, fr_b2, fr_chk); `endif cyc <= cyc + 1; in <= {in[30:0], in[31]^in[2]^in[0]}; // The inputs to sub will be updated externally on the neg-edge so these // don't matter for the result in_a <= in_a + 1; in_b <= in_b + 1; if (cyc==0) begin // Setup in <= 32'hd70a4497; in_a <= 0; in_b <= 0; end else if (cyc<3) begin end else if (cyc<10) begin if (fr_chk != fr_a) $stop; if (fr_chk != fr_b) $stop; if (fr_chk != fr_a2) $stop; if (fr_chk != fr_b2) $stop; end else if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end always @(posedge t.monclk) begin mon_eval(); end endmodule `ifdef ATTRIBUTES import "DPI-C" context function void mon_scope_name (input string formatted /*verilator sformat*/ ); `else import "DPI-C" context function void mon_scope_name (input string formatted); `endif import "DPI-C" context function void mon_register_b(string name, int isOut, int n, int addend); import "DPI-C" context function void mon_register_done(); import "DPI-C" context function void mon_eval(); module sub (/*AUTOARG*/ // Outputs fr_a, fr_b, fr_a2, fr_b2, fr_chk, // Inputs in, in_a, in_b ); `systemc_imp_header void mon_class_name(const char* namep); void mon_register_a(const char* namep, void* sigp, bool isOut, int n, int addend); `verilog /* verilator lint_off ASSIGNIN */ `ifdef ATTRIBUTES // Sensitivity list accepted for backward compatibility but ignored input int in /*verilator public_flat_rd*/; input int in_a /*verilator public_flat_rw @(posedge t.monclk)*/; input int in_b /*verilator public_flat_rw*/; output int fr_a /*verilator public_flat_rw @(posedge t.monclk)*/; output int fr_b /*verilator public_flat_rw*/; `else input int in; input int in_a; input int in_b; output int fr_a; output int fr_b; `endif output int fr_a2; output int fr_b2; output int fr_chk; /* verilator lint_on ASSIGNIN */ always @* fr_a2 = in_a + 1; always @* fr_b2 = in_b + 1; always @* fr_chk = in + 1; initial begin // Test the naming $c("mon_class_name(this->name());"); mon_scope_name("%m"); // Scheme A - pass pointer directly $c("mon_register_a(\"in\", &", in, ", false, 0, 1);"); $c("mon_register_a(\"fr_a\", &", fr_a, ", true, 0, 1);"); $c("mon_register_a(\"in\", &", in, ", false, 1, 0);"); $c("mon_register_a(\"in_a\", &", in_a, ", true, 1, 0);"); // Scheme B - use VPIish callbacks to see what signals exist mon_register_b("in", 0, 2, 1); mon_register_b("fr_b", 1, 2, 1); mon_register_b("in", 0, 3, 0); mon_register_b("in_b", 1, 3, 0); mon_register_done(); end endmodule verilator-5.042/test_regress/t/t_impure_cond_empty_if.v0000644000542200017500000000115715101701376024004 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class uvm_component; int x; function void set_x(); x = 1; endfunction function new(); if(call_set_return_false()); endfunction function bit call_set_return_false; set_x(); return 0; endfunction endclass module t; initial begin automatic uvm_component a = new; if (a.x != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_param_if_blk.v0000644000542200017500000000640615101701376022214 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013. // SPDX-License-Identifier: CC0-1.0 // bug648 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [7:0] datai = crc[7:0]; wire enable = crc[8]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) logic [7:0] datao; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .datao (datao[7:0]), // Inputs .clk (clk), .datai (datai[7:0]), .enable (enable)); // Aggregate outputs into a single result vector wire [63:0] result = {56'h0, datao}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h9d550d82d38926fa if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule `define FAIL 1 module Nested ( input logic clk, input logic x, output logic y ); logic t; always_comb t = x ^ 1'b1; always_ff @(posedge clk) begin if (clk) y <= t; end endmodule module Test ( input logic clk, input logic [7:0] datai, input logic enable, output logic [7:0] datao ); logic [7:0] datat; for (genvar i = 0; i < 8; i++) begin if (i%4 != 3) begin `ifndef FAIL logic t; always_comb begin t = datai[i] ^ 1'b1; end always_ff @(posedge clk) begin if (clk) datat[i] <= t; end `else Nested nested_i ( .clk(clk), .x(datai[i]), .y(datat[i]) //<== via Vcellout wire ); `endif always_comb begin casez (enable) 1'b1: datao[i] = datat[i]; 1'b0: datao[i] = '0; default: datao[i] = 'x; endcase end end else begin always_ff @(posedge clk) begin if (clk) datat[i] <= 0; //<== assign delayed end always_comb begin casez (enable) 1'b1: datao[i] = datat[i] ^ 1'b1; 1'b0: datao[i] = '1; default: datao[i] = 'x; endcase end end end endmodule verilator-5.042/test_regress/t/t_assign_expr.py0000755000542200017500000000073415101701376022314 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_while_cond_is_stmt.v0000644000542200017500000000142415101701376023456 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Test of select from constant // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; function int unsigned nth_power_of_2(input int unsigned n); nth_power_of_2 = 1; while (n != 0) begin n = n - 1; nth_power_of_2 = nth_power_of_2 << 1; end endfunction initial begin // Evaluating the function call in the loop condition used // to cause an infinite loop at run-time while (nth_power_of_2(8) != 256) begin $display("2**8 != 256 ?!"); $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_cover_expr_max.out0000644000542200017500000011312715101701376023170 0ustar mahmoudyfreeshell// // verilator_coverage annotation // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class cls; rand int x; endclass module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; logic [63:32] cyc2; always_comb cyc2 = cyc; integer some_int; integer other_int; logic some_bool; wire t1 = cyc[0]; wire t2 = cyc[1]; wire t3 = cyc[2]; wire t4 = cyc[3]; localparam bit ONE = 1'b1; localparam bit ZERO = 1'b0; function automatic bit invert(bit x); %000005 return ~x; -000004 point: comment=(x==0) => 1 hier=top.t -000005 point: comment=(x==1) => 0 hier=top.t endfunction function automatic bit and_oper(bit a, bit b); %000005 return a & b; -000004 point: comment=(a==0) => 0 hier=top.t -000002 point: comment=(a==1 && b==1) => 1 hier=top.t -000005 point: comment=(b==0) => 0 hier=top.t endfunction localparam int NUM_INTFS = 4; intf the_intfs [NUM_INTFS-1:0] (); genvar intf_i; for (intf_i = 0; intf_i < NUM_INTFS; intf_i++) begin always_comb the_intfs[intf_i].t = cyc[intf_i]; end always @ (posedge clk) begin cyc <= cyc + 1; %000004 if ((~cyc[0] && cyc[1]) || (~cyc[2] && cyc[3])) $write(""); -000002 point: comment=(cyc[0]==0 && cyc[1]==1) => 1 hier=top.t -000002 point: comment=(cyc[0]==1 && cyc[2]==1) => 0 hier=top.t -000004 point: comment=(cyc[0]==1 && cyc[3]==0) => 0 hier=top.t -000002 point: comment=(cyc[1]==0 && cyc[2]==1) => 0 hier=top.t -000003 point: comment=(cyc[1]==0 && cyc[3]==0) => 0 hier=top.t -000002 point: comment=(cyc[2]==0 && cyc[3]==1) => 1 hier=top.t %000004 if ((~cyc2[32] && cyc2[33]) || (~cyc2[34] && cyc2[35])) $write(""); -000002 point: comment=(cyc2[32]==0 && cyc2[33]==1) => 1 hier=top.t -000002 point: comment=(cyc2[32]==1 && cyc2[34]==1) => 0 hier=top.t -000004 point: comment=(cyc2[32]==1 && cyc2[35]==0) => 0 hier=top.t -000002 point: comment=(cyc2[33]==0 && cyc2[34]==1) => 0 hier=top.t -000003 point: comment=(cyc2[33]==0 && cyc2[35]==0) => 0 hier=top.t -000002 point: comment=(cyc2[34]==0 && cyc2[35]==1) => 1 hier=top.t %000004 if ((~the_intfs[0].t && the_intfs[1].t) || (~the_intfs[2].t && the_intfs[3].t)) $write(""); -000002 point: comment=(the_intfs[0].t==0 && the_intfs[1].t==1) => 1 hier=top.t -000002 point: comment=(the_intfs[0].t==1 && the_intfs[2].t==1) => 0 hier=top.t -000004 point: comment=(the_intfs[0].t==1 && the_intfs[3].t==0) => 0 hier=top.t -000002 point: comment=(the_intfs[1].t==0 && the_intfs[2].t==1) => 0 hier=top.t -000003 point: comment=(the_intfs[1].t==0 && the_intfs[3].t==0) => 0 hier=top.t -000002 point: comment=(the_intfs[2].t==0 && the_intfs[3].t==1) => 1 hier=top.t %000004 if ((~t1 && t2) || (~t3 && t4)) $write(""); -000002 point: comment=(t1==0 && t2==1) => 1 hier=top.t -000002 point: comment=(t1==1 && t3==1) => 0 hier=top.t -000004 point: comment=(t1==1 && t4==0) => 0 hier=top.t -000002 point: comment=(t2==0 && t3==1) => 0 hier=top.t -000003 point: comment=(t2==0 && t4==0) => 0 hier=top.t -000002 point: comment=(t3==0 && t4==1) => 1 hier=top.t %000005 if (t3 && (t1 == t2)) $write(""); -000005 point: comment=((t1 == t2)==0) => 0 hier=top.t -000005 point: comment=(t3==0) => 0 hier=top.t -000002 point: comment=(t3==1 && (t1 == t2)==1) => 1 hier=top.t %000005 if (123 == (124 - 32'(t1 || t2))) $write(""); -000002 point: comment=(t1==0 && t2==0) => 0 hier=top.t -000005 point: comment=(t1==1) => 1 hier=top.t -000004 point: comment=(t2==1) => 1 hier=top.t %000004 some_int <= (t2 || t3) ? 345 : 567; -000003 point: comment=(t2==0 && t3==0) => 0 hier=top.t -000004 point: comment=(t2==1) => 1 hier=top.t -000004 point: comment=(t3==1) => 1 hier=top.t %000005 some_bool <= t1 && t2; -000004 point: comment=(t1==0) => 0 hier=top.t -000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t %000005 if (t1 & t2) $write(""); -000004 point: comment=(t1==0) => 0 hier=top.t -000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t %000004 if ((!t1 && t2) | (~t3 && t4)) $write(""); -000002 point: comment=(t1==0 && t2==1) => 1 hier=top.t -000002 point: comment=(t1==1 && t3==1) => 0 hier=top.t -000004 point: comment=(t1==1 && t4==0) => 0 hier=top.t -000002 point: comment=(t2==0 && t3==1) => 0 hier=top.t -000003 point: comment=(t2==0 && t4==0) => 0 hier=top.t -000002 point: comment=(t3==0 && t4==1) => 1 hier=top.t %000003 if (t1 ^ t2) $write(""); -000002 point: comment=(t1==0 && t2==0) => 0 hier=top.t -000002 point: comment=(t1==0 && t2==1) => 1 hier=top.t -000003 point: comment=(t1==1 && t2==0) => 1 hier=top.t -000002 point: comment=(t1==1 && t2==1) => 0 hier=top.t %000005 if (~(t1 & t2)) $write(""); -000004 point: comment=(t1==0) => 1 hier=top.t -000002 point: comment=(t1==1 && t2==1) => 0 hier=top.t -000005 point: comment=(t2==0) => 1 hier=top.t %000004 if (t1 -> t2) $write(""); -000004 point: comment=(t1==0) => 1 hier=top.t -000003 point: comment=(t1==1 && t2==0) => 0 hier=top.t -000004 point: comment=(t2==1) => 1 hier=top.t %000003 if (t1 <-> t2) $write(""); -000002 point: comment=(t1==0 && t2==0) => 1 hier=top.t -000002 point: comment=(t1==0 && t2==1) => 0 hier=top.t -000003 point: comment=(t1==1 && t2==0) => 0 hier=top.t -000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t %000005 if (&cyc[2:0]) $write(""); -000004 point: comment=(cyc[2:0][0]==0) => 0 hier=top.t -000001 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 1 hier=top.t -000005 point: comment=(cyc[2:0][1]==0) => 0 hier=top.t -000005 point: comment=(cyc[2:0][2]==0) => 0 hier=top.t %000007 if (&cyc[3:2]) $write(""); -000005 point: comment=(cyc[3:2][0]==0) => 0 hier=top.t -000000 point: comment=(cyc[3:2][0]==1 && cyc[3:2][1]==1) => 1 hier=top.t -000007 point: comment=(cyc[3:2][1]==0) => 0 hier=top.t %000005 if (|cyc[2:0]) $write(""); -000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 0 hier=top.t -000005 point: comment=(cyc[2:0][0]==1) => 1 hier=top.t -000004 point: comment=(cyc[2:0][1]==1) => 1 hier=top.t -000004 point: comment=(cyc[2:0][2]==1) => 1 hier=top.t %000002 if (^cyc[2:0]) $write(""); -000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 0 hier=top.t -000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==1) => 1 hier=top.t -000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==1 && cyc[2:0][2]==0) => 1 hier=top.t -000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 0 hier=top.t -000002 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 1 hier=top.t -000001 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==0 && cyc[2:0][2]==1) => 0 hier=top.t -000001 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==0) => 0 hier=top.t -000001 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 1 hier=top.t %000005 if (|cyc[2:0] || cyc[3]) $write(""); -000000 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0 && cyc[3]==0) => 0 hier=top.t -000005 point: comment=(cyc[2:0][0]==1) => 1 hier=top.t -000004 point: comment=(cyc[2:0][1]==1) => 1 hier=top.t -000004 point: comment=(cyc[2:0][2]==1) => 1 hier=top.t -000002 point: comment=(cyc[3]==1) => 1 hier=top.t %000005 if (t1 & t2 & 1'b1) $write(""); -000000 point: comment=(1'h1==0) => 0 hier=top.t -000004 point: comment=(t1==0) => 0 hier=top.t -000002 point: comment=(t1==1 && t2==1 && 1'h1==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t %000009 if (t1 & t2 & 1'b0) $write(""); -000009 point: comment=(1'h0==0) => 0 hier=top.t -000004 point: comment=(t1==0) => 0 hier=top.t -000000 point: comment=(t1==1 && t2==1 && 1'h0==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t %000005 if (t1 & t2 & ONE) $write(""); -000000 point: comment=(ONE==0) => 0 hier=top.t -000004 point: comment=(t1==0) => 0 hier=top.t -000002 point: comment=(t1==1 && t2==1 && ONE==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t %000009 if (t1 & t2 & ZERO) $write(""); -000009 point: comment=(ZERO==0) => 0 hier=top.t -000004 point: comment=(t1==0) => 0 hier=top.t -000000 point: comment=(t1==1 && t2==1 && ZERO==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t %000005 if (t1 && t2) begin -000004 point: comment=(t1==0) => 0 hier=top.t -000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t $write(""); %000003 end else if (t1 || t2) begin -000002 point: comment=(t1==0 && t2==0) => 0 hier=top.t -000003 point: comment=(t1==1) => 1 hier=top.t -000002 point: comment=(t2==1) => 1 hier=top.t $write(""); end %000005 if (invert(t1) && t2) $write(""); -000005 point: comment=(invert(t1)==0) => 0 hier=top.t -000002 point: comment=(invert(t1)==1 && t2==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t if (and_oper(t1, t2)) $write(""); %000005 if (t2 && t3) begin -000005 point: comment=(t2==0) => 0 hier=top.t -000002 point: comment=(t2==1 && t3==1) => 1 hier=top.t -000005 point: comment=(t3==0) => 0 hier=top.t %000001 if (t1 && t2) $write(""); -000001 point: comment=(t1==0) => 0 hier=top.t -000001 point: comment=(t1==1 && t2==1) => 1 hier=top.t -000000 point: comment=(t2==0) => 0 hier=top.t end if (0 == 1) begin for (int loop_var = 0; loop_var < 1; loop_var++) begin %000000 if (cyc[loop_var] && t2) $write(""); -000000 point: comment=(cyc[loop_var[4:0]+:1]==0) => 0 hier=top.t -000000 point: comment=(cyc[loop_var[4:0]+:1]==1 && t2==1) => 1 hier=top.t -000000 point: comment=(t2==0) => 0 hier=top.t end end // stop at the first layer even if there's more to find %000007 if ((cyc[3+32'(t1 && t2)+:2] == cyc[5+32'(t3 || t4)+:2]) || cyc[31]) $write(""); -000002 point: comment=((cyc[(32'sh3 + (t1 && t2))[4:0]+:2] == cyc[(32'sh5 + (t3 || t4))[4:0]+:2])==0 && cyc[31]==0) => 0 hier=top.t -000007 point: comment=((cyc[(32'sh3 + (t1 && t2))[4:0]+:2] == cyc[(32'sh5 + (t3 || t4))[4:0]+:2])==1) => 1 hier=top.t -000000 point: comment=(cyc[31]==1) => 1 hier=top.t // impossible branches and redundant terms %000005 if ((t1 && t2) && ~(t1 && t3) && (t1 || t4)) $write(""); -000003 point: comment=(t1==0 && t4==0) => 0 hier=top.t -000004 point: comment=(t1==0) => 0 hier=top.t -000000 point: comment=(t1==1 && t2==1 && t3==0 && t4==1) => 1 hier=top.t -000001 point: comment=(t1==1 && t2==1 && t3==0) => 1 hier=top.t -000002 point: comment=(t1==1 && t3==1) => 0 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t %000005 if ((cyc[0] && cyc[1]) && ~(cyc[0] && cyc[2]) && (cyc[0] || cyc[3])) $write(""); -000003 point: comment=(cyc[0]==0 && cyc[3]==0) => 0 hier=top.t -000004 point: comment=(cyc[0]==0) => 0 hier=top.t -000000 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[3]==1) => 1 hier=top.t -000001 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0) => 1 hier=top.t -000002 point: comment=(cyc[0]==1 && cyc[2]==1) => 0 hier=top.t -000005 point: comment=(cyc[1]==0) => 0 hier=top.t // demonstrate current limitations of term matching scheme %000005 if ((cyc[0] && cyc[1]) && ~(cyc[1-1] && cyc[2]) && (cyc[2-2] || cyc[3])) $write(""); -000002 point: comment=(cyc[(32'sh1 - 32'sh1)[4:0]+:1]==1 && cyc[2]==1) => 0 hier=top.t -000003 point: comment=(cyc[(32'sh2 - 32'sh2)[4:0]+:1]==0 && cyc[3]==0) => 0 hier=top.t -000004 point: comment=(cyc[0]==0) => 0 hier=top.t -000000 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[(32'sh1 - 32'sh1)[4:0]+:1]==0 && cyc[(32'sh2 - 32'sh2)[4:0]+:1]==1) => 1 hier=top.t -000000 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[(32'sh1 - 32'sh1)[4:0]+:1]==0 && cyc[3]==1) => 1 hier=top.t -000001 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[(32'sh2 - 32'sh2)[4:0]+:1]==1) => 1 hier=top.t -000000 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[3]==1) => 1 hier=top.t -000005 point: comment=(cyc[1]==0) => 0 hier=top.t //verilator coverage_off if (t1 && t2) $write(""); //verilator coverage_on if ((~t1 && t2) %000004 || -000002 point: comment=(t1==0 && t2==1) => 1 hier=top.t -000002 point: comment=(t1==1 && t3==1) => 0 hier=top.t -000004 point: comment=(t1==1 && t4==0) => 0 hier=top.t -000002 point: comment=(t2==0 && t3==1) => 0 hier=top.t -000003 point: comment=(t2==0 && t4==0) => 0 hier=top.t -000002 point: comment=(t3==0 && t4==1) => 1 hier=top.t (~t3 && t4)) $write(""); // intentionally testing wonkified expression terms if ( cyc[ 0 %000005 ] & -000004 point: comment=(cyc[0]==0) => 0 hier=top.t -000002 point: comment=(cyc[0]==1 && cyc[1]==1) => 1 hier=top.t -000005 point: comment=(cyc[1]==0) => 0 hier=top.t cyc [1]) $write(""); // for now each ternary condition is considered in isolation %000005 other_int <= t1 ? t2 ? 1 : 2 : 3; -000004 point: comment=(t1==0) => 0 hier=top.t -000005 point: comment=(t1==1) => 1 hier=top.t // no expression coverage for multi-bit expressions if ((cyc[1:0] & cyc[3:2]) == 2'b11) $write(""); // truth table is too large %000001 if (^cyc[6:0]) $write(""); -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t -000001 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t -000001 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t -000001 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t -000001 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t -000001 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t -000001 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t -000001 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t -000001 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t -000001 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t -000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t // this one is too big even for t_cover_expr_max if (^cyc) $write(""); if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end always_comb begin %000005 if (t1 && t2) $write(""); -000005 point: comment=(t1==0) => 0 hier=top.t -000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t end logic ta, tb, tc; initial begin cls obj = new; cls null_obj = null; int q[5]; int qv[$]; q = '{1, 2, 2, 4, 3}; // lambas not handled // NB: there is a bug w/ tracing find_first (maybe lambdas in general?) // tracing_off does not work around the bug qv = q.find_first with (item[0] & item[1]); ta = '1; tb = '0; tc = '0; %000001 while (ta || tb || tc) begin -000001 point: comment=(ta==0 && tb==0 && tc==0) => 0 hier=top.t -000000 point: comment=(ta==1) => 1 hier=top.t -000000 point: comment=(tb==1) => 1 hier=top.t -000000 point: comment=(tc==1) => 1 hier=top.t tc = tb; tb = ta; ta = '0; end if (!bit'(obj.randomize() with {x < 100;})) $write(""); if (null_obj != null && null_obj.x == 5) $write(""); end sub the_sub_1 (.p(t1), .q(t2)); sub the_sub_2 (.p(t3), .q(t4)); // TODO -- non-process expressions sub the_sub_3 (.p(t1 ? t2 : t3), .q(t4)); // TODO // pragma for expr coverage off / on // investigate cover point sorting in annotated source // consider reporting don't care terms // // Branches which are statically impossible to reach are still reported. // E.g. // -000000 point: comment=(t1=1 && t2=1 && 1'h0=1) => 1 hier=top.t // These could potentially be pruned, but they currently follow suit for // what branch coverage does. Perhaps a switch should be added to not // count statically impossible things. endmodule module sub ( input p, input q ); always_comb begin ~000019 if (p && q) $write(""); +000017 point: comment=(p==0) => 0 hier=top.t.the_sub_* -000002 point: comment=(p==1 && q==1) => 1 hier=top.t.the_sub_* +000019 point: comment=(q==0) => 0 hier=top.t.the_sub_* end endmodule interface intf(); logic t; endinterface verilator-5.042/test_regress/t/t_class_param_extends.py0000755000542200017500000000073415101701376024011 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_iface_array_topmodule_bad.py0000755000542200017500000000076615101701376026170 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dpi_arg_output_type.cpp0000644000542200017500000006107015101701376024207 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2020 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include #include #include // clang-format off #if defined(NCSC) // Used by NC's svdpi.h to pick up svLogicVecVal with _.aval and _.bval fields, // rather than the IEEE 1800-2005 version which has _.a and _.b fields. # define DPI_COMPATIBILITY_VERSION_1800v2012 #endif #include "svdpi.h" #if defined(VERILATOR) // Verilator # include "Vt_dpi_arg_output_type__Dpi.h" typedef long long sv_longint_t; typedef unsigned long long sv_longint_unsigned_t; # define NO_SHORTREAL #elif defined(VCS) // VCS # include "../vc_hdrs.h" typedef long long sv_longint_t; typedef unsigned long long sv_longint_unsigned_t; # define NO_TIME #elif defined(NCSC) // NC # include "dpi-exp.h" # include "dpi-imp.h" typedef long long sv_longint_t; typedef unsigned long long sv_longint_unsigned_t; # define NO_TIME # define NO_INTEGER # define NO_SHORTREAL #elif defined(MS) // ModelSim # include "dpi.h" typedef int64_t sv_longint_t; typedef uint64_t sv_longint_unsigned_t; # else # error "Unknown simulator for DPI test" #endif // clang-format on //====================================================================== // Implementations of imported functions //====================================================================== void set_bvals(svLogicVecVal* v, unsigned n); void set_bvals(svLogicVecVal* v, unsigned n) { for (unsigned i = 0; i < n; i++) v[i].bval = 0; } // Basic types as per IEEE 1800-2023 35.5.6 void i_byte(char* o) { static int n = 0; *o = 10 - n++; } void i_byte_unsigned(unsigned char* o) { static int n = 0; *o = 20 - n++; } void i_shortint(short* o) { static int n = 0; *o = 30 - n++; } void i_shortint_unsigned(unsigned short* o) { static int n = 0; *o = 40 - n++; } void i_int(int* o) { static int n = 0; *o = 50 - n++; } void i_int_unsigned(unsigned* o) { static int n = 0; *o = 60 - n++; } void i_longint(sv_longint_t* o) { static int n = 0; *o = 70 - n++; } void i_longint_unsigned(sv_longint_unsigned_t* o) { static int n = 0; *o = 80 - n++; } #ifndef NO_TIME void i_time(svLogicVecVal* o) { static int n = 0; o[0].aval = 90 - n++; o[1].aval = 0; set_bvals(o, 2); } #endif #ifndef NO_INTEGER void i_integer(svLogicVecVal* o) { static int n = 0; o->aval = 100 - n++; set_bvals(o, 1); } #endif void i_real(double* o) { static int n = 0; *o = (-2.0 * n++ - 1.0) / 2.0; } #ifndef NO_SHORTREAL void i_shortreal(float* o) { static int n = 0; *o = (-4.0f * n++ - 1.0f) / 4.0f; } #endif void i_chandle(void** o) { static int n = 0; printf("i_chandle %d\n", n); *o = (n++ % 2) ? reinterpret_cast(&i_chandle) : NULL; } void i_string(const char** o) { static int n = 0; printf("i_string %d\n", n); *o = (n++ % 2) ? "Hello" : "World"; } void i_bit(svBit* o) { static int n = 0; printf("i_bit %d\n", n); *o = !(n++ % 2); } void i_logic(svLogic* o) { static int n = 0; printf("i_logic %d\n", n); *o = n++ % 2; } // Basic types via typedefs void i_byte_t(char* o) { static int n = 0; const char r = 10 - n; n += 2; *o = r; } void i_byte_unsigned_t(unsigned char* o) { static int n = 0; const unsigned char r = 20 - n; n += 2; *o = r; } void i_shortint_t(short* o) { static int n = 0; const short r = 30 - n; n += 2; *o = r; } void i_shortint_unsigned_t(unsigned short* o) { static int n = 0; const unsigned short r = 40 - n; n += 2; *o = r; } void i_int_t(int* o) { static int n = 0; const int r = 50 - n; n += 2; *o = r; } void i_int_unsigned_t(unsigned* o) { static int n = 0; const unsigned r = 60 - n; n += 2; *o = r; } void i_longint_t(sv_longint_t* o) { static int n = 0; const long long r = 70 - n; n += 2; *o = r; } void i_longint_unsigned_t(sv_longint_unsigned_t* o) { static int n = 0; const unsigned long long r = 80 - n; n += 2; *o = r; } #ifndef NO_TIME void i_time_t(svLogicVecVal* o) { static int n = 0; o[0].aval = 90 - n; o[1].aval = 0; set_bvals(o, 2); n += 2; } #endif #ifndef NO_INTEGER void i_integer_t(svLogicVecVal* o) { static int n = 0; o->aval = 100 - n; set_bvals(o, 1); n += 2; } #endif void i_real_t(double* o) { static int n = 0; const double r = (-2.0 * n - 1.0) / 2.0; n += 2; *o = r; } #ifndef NO_SHORTREAL void i_shortreal_t(float* o) { static int n = 0; const float r = (-4.0f * n - 1.0f) / 4.0f; n += 2; *o = r; } #endif void i_chandle_t(void** o) { static int n = 0; printf("i_chandle_t %d\n", n); *o = (n++ % 2) ? reinterpret_cast(&i_chandle) : NULL; } void i_string_t(const char** o) { static int n = 0; printf("i_string_t %d\n", n); *o = (n++ % 2) ? "Hello" : "World"; } void i_bit_t(svBit* o) { static int n = 0; printf("i_bit_t %d\n", n); *o = !(n++ % 2); } void i_logic_t(svLogic* o) { static int n = 0; printf("i_logic_t %d\n", n); *o = n++ % 2; } // 2-state packed arrays void i_array_2_state_1(svBitVecVal* o) { static int n = 0; printf("i_array_2_state_1 %d\n", n); *o = !(n++ % 2); } void i_array_2_state_32(svBitVecVal* o) { static int n = 0; printf("i_array_2_state_32 %d\n", n); *o = 0xffffffffU << n++; } void i_array_2_state_33(svBitVecVal* o) { static int n = 0; printf("i_array_2_state_33 %d\n", n); o[0] = 0xffffffffU << n++; o[1] = 1; } void i_array_2_state_64(svBitVecVal* o) { static int n = 0; printf("i_array_2_state_64 %d\n", n); o[0] = 0xffffffffU << n++; o[1] = -1; } void i_array_2_state_65(svBitVecVal* o) { static int n = 0; printf("i_array_2_state_65 %d\n", n); o[0] = 0xffffffffU << n++; o[1] = -1; o[2] = 1; } void i_array_2_state_128(svBitVecVal* o) { static int n = 0; printf("i_array_2_state_128 %d\n", n); o[0] = 0xffffffffU << n++; o[1] = -1; o[2] = -1; o[3] = -1; } // 2-state packed structures void i_struct_2_state_1(svBitVecVal* o) { static int n = 0; printf("i_struct_2_state_1 %d\n", n); *o = !(n++ % 2); } void i_struct_2_state_32(svBitVecVal* o) { static int n = 0; printf("i_struct_2_state_32 %d\n", n); *o = 0xffffffffU << n++; } void i_struct_2_state_33(svBitVecVal* o) { static int n = 0; printf("i_struct_2_state_33 %d\n", n); o[0] = 0xffffffffU << n++; o[1] = 1; } void i_struct_2_state_64(svBitVecVal* o) { static int n = 0; printf("i_struct_2_state_64 %d\n", n); o[0] = 0xffffffffU << n++; o[1] = -1; } void i_struct_2_state_65(svBitVecVal* o) { static int n = 0; printf("i_struct_2_state_65 %d\n", n); o[0] = 0xffffffffU << n++; o[1] = -1; o[2] = 1; } void i_struct_2_state_128(svBitVecVal* o) { static int n = 0; printf("i_struct_2_state_128 %d\n", n); o[0] = 0xffffffffU << n++; o[1] = -1; o[2] = -1; o[3] = -1; } // 2-state packed unions void i_union_2_state_1(svBitVecVal* o) { static int n = 0; printf("i_union_2_state_1 %d\n", n); *o = !(n++ % 2); } void i_union_2_state_32(svBitVecVal* o) { static int n = 0; printf("i_union_2_state_32 %d\n", n); *o = 0xffffffffU << n++; } void i_union_2_state_33(svBitVecVal* o) { static int n = 0; printf("i_union_2_state_33 %d\n", n); o[0] = 0xffffffffU << n++; o[1] = 1; } void i_union_2_state_64(svBitVecVal* o) { static int n = 0; printf("i_union_2_state_64 %d\n", n); o[0] = 0xffffffffU << n++; o[1] = -1; } void i_union_2_state_65(svBitVecVal* o) { static int n = 0; printf("i_union_2_state_65 %d\n", n); o[0] = 0xffffffffU << n++; o[1] = -1; o[2] = 1; } void i_union_2_state_128(svBitVecVal* o) { static int n = 0; printf("i_union_2_state_128 %d\n", n); o[0] = 0xffffffffU << n++; o[1] = -1; o[2] = -1; o[3] = -1; } // 4-state packed arrays void i_array_4_state_1(svLogicVecVal* o) { static int n = 0; printf("i_array_4_state_1 %d\n", n); o->aval = !(n++ % 2); set_bvals(o, 1); } void i_array_4_state_32(svLogicVecVal* o) { static int n = 0; printf("i_array_4_state_32 %d\n", n); o->aval = 0xffffffffU << n++; set_bvals(o, 1); } void i_array_4_state_33(svLogicVecVal* o) { static int n = 0; printf("i_array_4_state_33 %d\n", n); o[0].aval = 0xffffffffU << n++; o[1].aval = 1; set_bvals(o, 2); } void i_array_4_state_64(svLogicVecVal* o) { static int n = 0; printf("i_array_4_state_64 %d\n", n); o[0].aval = 0xffffffffU << n++; o[1].aval = -1; set_bvals(o, 2); } void i_array_4_state_65(svLogicVecVal* o) { static int n = 0; printf("i_array_4_state_65 %d\n", n); o[0].aval = 0xffffffffU << n++; o[1].aval = -1; o[2].aval = 1; set_bvals(o, 3); } void i_array_4_state_128(svLogicVecVal* o) { static int n = 0; printf("i_array_4_state_128 %d\n", n); o[0].aval = 0xffffffffU << n++; o[1].aval = -1; o[2].aval = -1; o[3].aval = -1; set_bvals(o, 4); } // 4-state packed structures void i_struct_4_state_1(svLogicVecVal* o) { static int n = 0; printf("i_struct_4_state_1 %d\n", n); o->aval = !(n++ % 2); set_bvals(o, 1); } void i_struct_4_state_32(svLogicVecVal* o) { static int n = 0; printf("i_struct_4_state_32 %d\n", n); o->aval = 0xffffffffU << n++; set_bvals(o, 1); } void i_struct_4_state_33(svLogicVecVal* o) { static int n = 0; printf("i_struct_4_state_33 %d\n", n); o[0].aval = 0xffffffffU << n++; o[1].aval = 1; set_bvals(o, 2); } void i_struct_4_state_64(svLogicVecVal* o) { static int n = 0; printf("i_struct_4_state_64 %d\n", n); o[0].aval = 0xffffffffU << n++; o[1].aval = -1; set_bvals(o, 2); } void i_struct_4_state_65(svLogicVecVal* o) { static int n = 0; printf("i_struct_4_state_65 %d\n", n); o[0].aval = 0xffffffffU << n++; o[1].aval = -1; o[2].aval = 1; set_bvals(o, 3); } void i_struct_4_state_128(svLogicVecVal* o) { static int n = 0; printf("i_struct_4_state_128 %d\n", n); o[0].aval = 0xffffffffU << n++; o[1].aval = -1; o[2].aval = -1; o[3].aval = -1; set_bvals(o, 4); } // 4-state packed unions void i_union_4_state_1(svLogicVecVal* o) { static int n = 0; printf("i_union_4_state_1 %d\n", n); o->aval = !(n++ % 2); set_bvals(o, 1); } void i_union_4_state_32(svLogicVecVal* o) { static int n = 0; printf("i_union_4_state_32 %d\n", n); o->aval = 0xffffffffU << n++; set_bvals(o, 1); } void i_union_4_state_33(svLogicVecVal* o) { static int n = 0; printf("i_union_4_state_33 %d\n", n); o[0].aval = 0xffffffffU << n++; o[1].aval = 1; set_bvals(o, 2); } void i_union_4_state_64(svLogicVecVal* o) { static int n = 0; printf("i_union_4_state_64 %d\n", n); o[0].aval = 0xffffffffU << n++; o[1].aval = -1; set_bvals(o, 2); } void i_union_4_state_65(svLogicVecVal* o) { static int n = 0; printf("i_union_4_state_65 %d\n", n); o[0].aval = 0xffffffffU << n++; o[1].aval = -1; o[2].aval = 1; set_bvals(o, 3); } void i_union_4_state_128(svLogicVecVal* o) { static int n = 0; printf("i_union_4_state_128 %d\n", n); o[0].aval = 0xffffffffU << n++; o[1].aval = -1; o[2].aval = -1; o[3].aval = -1; set_bvals(o, 4); } //====================================================================== // Check exported functions //====================================================================== #define stop() \ do { \ printf(__FILE__ ":%d Bad value\n", __LINE__); \ abort(); \ } while (0) void check_bvals(const svLogicVecVal* v, unsigned n); void check_bvals(const svLogicVecVal* v, unsigned n) { for (unsigned i = 0; i < n; i++) { if (v[i].bval != 0) { printf(__FILE__ ":%d Bad svLogicVecVal bval\n", __LINE__); abort(); } } } void check_exports() { static unsigned n = 0; char x_byte; unsigned char x_byte_unsigned; short x_shortint; unsigned short x_shortint_unsigned; int x_int; unsigned x_int_unsigned; sv_longint_t x_longint; sv_longint_unsigned_t x_longint_unsigned; #ifndef NO_TIME svLogicVecVal x_time[2]; #endif #ifndef NO_INTEGER svLogicVecVal x_integer[1]; #endif double x_real; #ifndef NO_SHORTREAL float x_shortreal; #endif void* x_chandle; const char* x_string; svBit x_bit; svLogic x_logic; char x_byte_t; unsigned char x_byte_unsigned_t; short x_shortint_t; unsigned short x_shortint_unsigned_t; int x_int_t; unsigned x_int_unsigned_t; sv_longint_t x_longint_t; sv_longint_unsigned_t x_longint_unsigned_t; #ifndef NO_TIME svLogicVecVal x_time_t[2]; #endif #ifndef NO_INTEGER svLogicVecVal x_integer_t[1]; #endif double x_real_t; #ifndef NO_SHORTREAL float x_shortreal_t; #endif void* x_chandle_t; const char* x_string_t; svBit x_bit_t; svLogic x_logic_t; svBitVecVal x_array_2_state_1[1]; svBitVecVal x_array_2_state_32[1]; svBitVecVal x_array_2_state_33[2]; svBitVecVal x_array_2_state_64[2]; svBitVecVal x_array_2_state_65[3]; svBitVecVal x_array_2_state_128[4]; svBitVecVal x_struct_2_state_1[1]; svBitVecVal x_struct_2_state_32[1]; svBitVecVal x_struct_2_state_33[2]; svBitVecVal x_struct_2_state_64[2]; svBitVecVal x_struct_2_state_65[3]; svBitVecVal x_struct_2_state_128[4]; svBitVecVal x_union_2_state_1[1]; svBitVecVal x_union_2_state_32[1]; svBitVecVal x_union_2_state_33[2]; svBitVecVal x_union_2_state_64[2]; svBitVecVal x_union_2_state_65[3]; svBitVecVal x_union_2_state_128[4]; svLogicVecVal x_array_4_state_1[1]; svLogicVecVal x_array_4_state_32[1]; svLogicVecVal x_array_4_state_33[2]; svLogicVecVal x_array_4_state_64[2]; svLogicVecVal x_array_4_state_65[3]; svLogicVecVal x_array_4_state_128[4]; svLogicVecVal x_struct_4_state_1[1]; svLogicVecVal x_struct_4_state_32[1]; svLogicVecVal x_struct_4_state_33[2]; svLogicVecVal x_struct_4_state_64[2]; svLogicVecVal x_struct_4_state_65[3]; svLogicVecVal x_struct_4_state_128[4]; svLogicVecVal x_union_4_state_1[1]; svLogicVecVal x_union_4_state_32[1]; svLogicVecVal x_union_4_state_33[2]; svLogicVecVal x_union_4_state_64[2]; svLogicVecVal x_union_4_state_65[3]; svLogicVecVal x_union_4_state_128[4]; // Basic types as per IEEE 1800-2023 35.5.6 e_byte(&x_byte); if (x_byte != 10 + n) stop(); e_byte_unsigned(&x_byte_unsigned); if (x_byte_unsigned != 20 + n) stop(); e_shortint(&x_shortint); if (x_shortint != 30 + n) stop(); e_shortint_unsigned(&x_shortint_unsigned); if (x_shortint_unsigned != 40 + n) stop(); e_int(&x_int); if (x_int != 50 + n) stop(); e_int_unsigned(&x_int_unsigned); if (x_int_unsigned != 60 + n) stop(); e_longint(&x_longint); if (x_longint != 70 + n) stop(); e_longint_unsigned(&x_longint_unsigned); if (x_longint_unsigned != 80 + n) stop(); #ifndef NO_TIME e_time(x_time); if (x_time[0].aval != 90 + n || x_time[1].aval != 0) stop(); check_bvals(x_time, 2); #endif #ifndef NO_INTEGER e_integer(x_integer); if (x_integer[0].aval != 100 + n) stop(); check_bvals(x_integer, 1); #endif e_real(&x_real); if (x_real != 1.0 * n + 0.5) stop(); #ifndef NO_SHORTREAL e_shortreal(&x_shortreal); if (x_shortreal != 1.0f * n + 0.25f) stop(); #endif e_chandle(&x_chandle); if (x_chandle != NULL) stop(); e_string(&x_string); if ((n % 2) == 0) { if (std::strcmp(x_string, "Hello") != 0) stop(); } else { if (std::strcmp(x_string, "World") != 0) stop(); } e_bit(&x_bit); if (x_bit != (n % 2)) stop(); e_logic(&x_logic); if (x_logic != !(n % 2)) stop(); // Basic types via tyepdef e_byte_t(&x_byte_t); if (x_byte_t != 10 + 2 * n) stop(); e_byte_unsigned_t(&x_byte_unsigned_t); if (x_byte_unsigned_t != 20 + 2 * n) stop(); e_shortint_t(&x_shortint_t); if (x_shortint_t != 30 + 2 * n) stop(); e_shortint_unsigned_t(&x_shortint_unsigned_t); if (x_shortint_unsigned_t != 40 + 2 * n) stop(); e_int_t(&x_int_t); if (x_int_t != 50 + 2 * n) stop(); e_int_unsigned_t(&x_int_unsigned_t); if (x_int_unsigned_t != 60 + 2 * n) stop(); e_longint_t(&x_longint_t); if (x_longint_t != 70 + 2 * n) stop(); e_longint_unsigned_t(&x_longint_unsigned_t); if (x_longint_unsigned_t != 80 + 2 * n) stop(); #ifndef NO_TIME e_time_t(x_time_t); if (x_time_t[0].aval != 90 + 2 * n || x_time_t[1].aval != 0) stop(); check_bvals(x_time_t, 2); #endif #ifndef NO_INTEGER e_integer_t(x_integer_t); if (x_integer_t[0].aval != 100 + 2 * n) stop(); check_bvals(x_integer_t, 1); #endif e_real_t(&x_real_t); if (x_real_t != 1.0 * (2 * n) + 0.5) stop(); #ifndef NO_SHORTREAL e_shortreal_t(&x_shortreal_t); if (x_shortreal_t != 1.0f * (2 * n) + 0.25f) stop(); #endif e_chandle_t(&x_chandle_t); if (x_chandle_t != NULL) stop(); e_string_t(&x_string_t); if ((n % 2) == 0) { if (std::strcmp(x_string_t, "Hello") != 0) stop(); } else { if (std::strcmp(x_string_t, "World") != 0) stop(); } e_bit_t(&x_bit_t); if (x_bit_t != (n % 2)) stop(); e_logic_t(&x_logic_t); if (x_logic_t != !(n % 2)) stop(); const int m = n == 0 ? 0 : n - 1; // 2-state packed arrays e_array_2_state_1(x_array_2_state_1); if (x_array_2_state_1[0] != (n % 2)) stop(); e_array_2_state_32(x_array_2_state_32); if (x_array_2_state_32[0] != 0xffffffff >> n) stop(); e_array_2_state_33(x_array_2_state_33); if (x_array_2_state_33[1] != 1 >> n) stop(); if (x_array_2_state_33[0] != 0xffffffff >> m) stop(); e_array_2_state_64(x_array_2_state_64); if (x_array_2_state_64[1] != 0xffffffff >> n) stop(); if (x_array_2_state_64[0] != 0xffffffff) stop(); e_array_2_state_65(x_array_2_state_65); if (x_array_2_state_65[2] != 1 >> n) stop(); if (x_array_2_state_65[1] != 0xffffffff >> m) stop(); if (x_array_2_state_65[0] != 0xffffffff) stop(); e_array_2_state_128(x_array_2_state_128); if (x_array_2_state_128[3] != 0xffffffff >> n) stop(); if (x_array_2_state_128[2] != 0xffffffff) stop(); if (x_array_2_state_128[1] != 0xffffffff) stop(); if (x_array_2_state_64[0] != 0xffffffff) stop(); // 2-state packed structures e_struct_2_state_1(x_struct_2_state_1); if (x_struct_2_state_1[0] != (n % 2)) stop(); e_struct_2_state_32(x_struct_2_state_32); if (x_struct_2_state_32[0] != 0xffffffff >> n) stop(); e_struct_2_state_33(x_struct_2_state_33); if (x_struct_2_state_33[1] != 1 >> n) stop(); if (x_struct_2_state_33[0] != 0xffffffff >> m) stop(); e_struct_2_state_64(x_struct_2_state_64); if (x_struct_2_state_64[1] != 0xffffffff >> n) stop(); if (x_struct_2_state_64[0] != 0xffffffff) stop(); e_struct_2_state_65(x_struct_2_state_65); if (x_struct_2_state_65[2] != 1 >> n) stop(); if (x_struct_2_state_65[1] != 0xffffffff >> m) stop(); if (x_struct_2_state_65[0] != 0xffffffff) stop(); e_struct_2_state_128(x_struct_2_state_128); if (x_struct_2_state_128[3] != 0xffffffff >> n) stop(); if (x_struct_2_state_128[2] != 0xffffffff) stop(); if (x_struct_2_state_128[1] != 0xffffffff) stop(); if (x_struct_2_state_64[0] != 0xffffffff) stop(); // 2-state packed unions e_union_2_state_1(x_union_2_state_1); if (x_union_2_state_1[0] != (n % 2)) stop(); e_union_2_state_32(x_union_2_state_32); if (x_union_2_state_32[0] != 0xffffffff >> n) stop(); e_union_2_state_33(x_union_2_state_33); if (x_union_2_state_33[1] != 1 >> n) stop(); if (x_union_2_state_33[0] != 0xffffffff >> m) stop(); e_union_2_state_64(x_union_2_state_64); if (x_union_2_state_64[1] != 0xffffffff >> n) stop(); if (x_union_2_state_64[0] != 0xffffffff) stop(); e_union_2_state_65(x_union_2_state_65); if (x_union_2_state_65[2] != 1 >> n) stop(); if (x_union_2_state_65[1] != 0xffffffff >> m) stop(); if (x_union_2_state_65[0] != 0xffffffff) stop(); e_union_2_state_128(x_union_2_state_128); if (x_union_2_state_128[3] != 0xffffffff >> n) stop(); if (x_union_2_state_128[2] != 0xffffffff) stop(); if (x_union_2_state_128[1] != 0xffffffff) stop(); if (x_union_2_state_64[0] != 0xffffffff) stop(); // 4-state packed arrays e_array_4_state_1(x_array_4_state_1); if (x_array_4_state_1[0].aval != (n % 2)) stop(); e_array_4_state_32(x_array_4_state_32); if (x_array_4_state_32[0].aval != 0xffffffff >> n) stop(); e_array_4_state_33(x_array_4_state_33); if (x_array_4_state_33[1].aval != 1 >> n) stop(); if (x_array_4_state_33[0].aval != 0xffffffff >> m) stop(); e_array_4_state_64(x_array_4_state_64); if (x_array_4_state_64[1].aval != 0xffffffff >> n) stop(); if (x_array_4_state_64[0].aval != 0xffffffff) stop(); e_array_4_state_65(x_array_4_state_65); if (x_array_4_state_65[2].aval != 1 >> n) stop(); if (x_array_4_state_65[1].aval != 0xffffffff >> m) stop(); if (x_array_4_state_65[0].aval != 0xffffffff) stop(); e_array_4_state_128(x_array_4_state_128); if (x_array_4_state_128[3].aval != 0xffffffff >> n) stop(); if (x_array_4_state_128[2].aval != 0xffffffff) stop(); if (x_array_4_state_128[1].aval != 0xffffffff) stop(); if (x_array_4_state_64[0].aval != 0xffffffff) stop(); check_bvals(x_array_4_state_1, 1); check_bvals(x_array_4_state_32, 1); check_bvals(x_array_4_state_33, 2); check_bvals(x_array_4_state_64, 2); check_bvals(x_array_4_state_65, 3); check_bvals(x_array_4_state_128, 4); // 4-state packed structures e_struct_4_state_1(x_struct_4_state_1); if (x_struct_4_state_1[0].aval != (n % 2)) stop(); e_struct_4_state_32(x_struct_4_state_32); if (x_struct_4_state_32[0].aval != 0xffffffff >> n) stop(); e_struct_4_state_33(x_struct_4_state_33); if (x_struct_4_state_33[1].aval != 1 >> n) stop(); if (x_struct_4_state_33[0].aval != 0xffffffff >> m) stop(); e_struct_4_state_64(x_struct_4_state_64); if (x_struct_4_state_64[1].aval != 0xffffffff >> n) stop(); if (x_struct_4_state_64[0].aval != 0xffffffff) stop(); e_struct_4_state_65(x_struct_4_state_65); if (x_struct_4_state_65[2].aval != 1 >> n) stop(); if (x_struct_4_state_65[1].aval != 0xffffffff >> m) stop(); if (x_struct_4_state_65[0].aval != 0xffffffff) stop(); e_struct_4_state_128(x_struct_4_state_128); if (x_struct_4_state_128[3].aval != 0xffffffff >> n) stop(); if (x_struct_4_state_128[2].aval != 0xffffffff) stop(); if (x_struct_4_state_128[1].aval != 0xffffffff) stop(); if (x_struct_4_state_64[0].aval != 0xffffffff) stop(); check_bvals(x_struct_4_state_1, 1); check_bvals(x_struct_4_state_32, 1); check_bvals(x_struct_4_state_33, 2); check_bvals(x_struct_4_state_64, 2); check_bvals(x_struct_4_state_65, 3); check_bvals(x_struct_4_state_128, 4); // 4-state packed unions e_union_4_state_1(x_union_4_state_1); if (x_union_4_state_1[0].aval != (n % 2)) stop(); e_union_4_state_32(x_union_4_state_32); if (x_union_4_state_32[0].aval != 0xffffffff >> n) stop(); e_union_4_state_33(x_union_4_state_33); if (x_union_4_state_33[1].aval != 1 >> n) stop(); if (x_union_4_state_33[0].aval != 0xffffffff >> m) stop(); e_union_4_state_64(x_union_4_state_64); if (x_union_4_state_64[1].aval != 0xffffffff >> n) stop(); if (x_union_4_state_64[0].aval != 0xffffffff) stop(); e_union_4_state_65(x_union_4_state_65); if (x_union_4_state_65[2].aval != 1 >> n) stop(); if (x_union_4_state_65[1].aval != 0xffffffff >> m) stop(); if (x_union_4_state_65[0].aval != 0xffffffff) stop(); e_union_4_state_128(x_union_4_state_128); if (x_union_4_state_128[3].aval != 0xffffffff >> n) stop(); if (x_union_4_state_128[2].aval != 0xffffffff) stop(); if (x_union_4_state_128[1].aval != 0xffffffff) stop(); if (x_union_4_state_64[0].aval != 0xffffffff) stop(); check_bvals(x_union_4_state_1, 1); check_bvals(x_union_4_state_32, 1); check_bvals(x_union_4_state_33, 2); check_bvals(x_union_4_state_64, 2); check_bvals(x_union_4_state_65, 3); check_bvals(x_union_4_state_128, 4); n++; } verilator-5.042/test_regress/t/t_sys_readmem_bad_addr.v0000644000542200017500000000061315101701376023710 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg [175:0] hex [15:0]; initial begin $readmemh("t/t_sys_readmem_bad_addr.mem", hex); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_module_input_default_value_noinl.py0000755000542200017500000000105315101701376026570 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_module_input_default_value.v" test.compile(v_flags2=["-fno-inline"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_mem_fifo.py0000755000542200017500000000073415101701376021553 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_math_synmul.py0000755000542200017500000000102515101701376022324 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["-Wno-UNOPTTHREADS"]) test.execute(check_finished=True) test.passes() verilator-5.042/test_regress/t/t_case_zx_bad.v0000644000542200017500000000070015101701376022037 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs value ); input [3:0] value; always @ (/*AS*/value) begin casez (value) 4'b0000: $stop; 4'b1xxx: $stop; default: $stop; endcase end endmodule verilator-5.042/test_regress/t/t_math_signed6.v0000644000542200017500000000171615101701376022155 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Iztok Jeras. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module t; // signed source logic signed [8-1:0] src; // destination structure struct packed { logic signed [16-1:0] s; logic unsigned [16-1:0] u; } dst; initial begin // bug882 // verilator lint_off WIDTH src = 8'sh05; dst = '{s: src, u: src}; `checkh (dst.s, 16'h0005); `checkh (dst.u, 16'h0005); src = 8'shf5; dst = '{s: src, u: src}; `checkh (dst.s, 16'hfff5); `checkh (dst.u, 16'hfff5); // verilator lint_on WIDTH $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_const_number_bad.out0000644000542200017500000000273115101701376023451 0ustar mahmoudyfreeshell%Error: t/t_const_number_bad.v:9:29: Number is missing value digits: 32'd 9 | parameter integer FOO2 = 32'd-6; | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_const_number_bad.v:10:29: Number is missing value digits: 32'd 10 | parameter integer FOO3 = 32'd; | ^~~~ %Error: t/t_const_number_bad.v:11:29: Number is missing value digits: 32'h 11 | parameter integer FOO4 = 32'h; | ^~~~ %Error: t/t_const_number_bad.v:13:29: Illegal character in binary constant: 2 13 | parameter integer FOO5 = 32'b2; | ^~~~~ %Error: t/t_const_number_bad.v:14:29: Illegal character in octal constant 14 | parameter integer FOO6 = 32'o8; | ^~~~~ %Error: t/t_const_number_bad.v:17:33: Illegal character in binary constant: 4 17 | parameter logic [3:0] FOO7 = 1'b1?4'hF:4'h1; | ^~~~~~ %Error: t/t_const_number_bad.v:17:33: Too many digits for 1 bit number: '1'b1?4' 17 | parameter logic [3:0] FOO7 = 1'b1?4'hF:4'h1; | ^~~~~~ %Error: t/t_const_number_bad.v:17:39: syntax error, unexpected INTEGER NUMBER, expecting ';' 17 | parameter logic [3:0] FOO7 = 1'b1?4'hF:4'h1; | ^~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_trace_two_hdrfst_cc.py0000755000542200017500000000246215101701376024000 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Test tracing with two models instanced import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t_trace_two_a.v" test.pli_filename = "t/t_trace_two_cc.cpp" test.compile(make_main=False, verilator_make_gmake=False, top_filename='t_trace_two_b.v', vm_prefix='Vt_trace_two_b', verilator_flags2=['--trace-fst --trace-threads 1']) test.run(logfile=test.obj_dir + "/make_first_ALL.log", cmd=[ os.environ["MAKE"], "-C", "" + test.obj_dir, "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp" ]) test.compile( make_main=False, top_filename='t_trace_two_a.v', make_flags=['CPPFLAGS_ADD="-DTEST_HDR_TRACE=1 -DTEST_FST=1"'], verilator_flags2=['-exe', '--trace-fst --trace-threads 1', '-DTEST_FST', test.pli_filename]) test.execute() if test.vlt_all: test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_langext_order_sub.v0000644000542200017500000000055215101701376023310 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // A test of the +verilog2001ext+ and +verilog2005ext+ flags. // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilator lint_off SYMRSVDWORD module t_langext_order_sub(input do); endmodule verilator-5.042/test_regress/t/t_queue_method_bad.py0000755000542200017500000000076315101701376023266 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_flag_language_bad.out0000644000542200017500000000025015101701376023521 0ustar mahmoudyfreeshell%Error: Unknown language specified: 1-2-3-4 ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_queue_void_ops.py0000755000542200017500000000073415101701376023020 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_disable_fork_notiming.out0000644000542200017500000000054415101701376024475 0ustar mahmoudyfreeshell%Error-NOTIMING: t/t_disable_fork_notiming.v:8:12: Support for disable fork statement requires --timing : ... note: In instance 't' 8 | initial disable fork; | ^~~~~~~ ... For error description see https://verilator.org/warn/NOTIMING?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_lint_vcmarker_bad.out0000644000542200017500000000075715101701376023621 0ustar mahmoudyfreeshell%Error: t/t_lint_vcmarker_bad.v:9:1: Version control conflict marker in file 9 | <<<<<<< HEAD | ^~~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_lint_vcmarker_bad.v:11:1: Version control conflict marker in file 11 | ======= | ^~~~~~~~~~~ %Error: t/t_lint_vcmarker_bad.v:13:1: Version control conflict marker in file 13 | >>>>>>> MERGE | ^~~~~~~~~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_class_nested.py0000755000542200017500000000077515101701376022446 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--exe --main"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_timing_always.v0000644000542200017500000000201615101701376022446 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `ifdef TEST_VERBOSE `define WRITE_VERBOSE(args) $write args `else `define WRITE_VERBOSE(args) `endif module t; bit clk = 0; always #3 clk = ~clk; bit flag_a; bit flag_b; always @(posedge clk) begin `WRITE_VERBOSE(("[%0t] b <= 0\n", $time)); flag_b <= 1'b0; #2 `WRITE_VERBOSE(("[%0t] a <= 1\n", $time)); flag_a <= 1'b1; #2 `WRITE_VERBOSE(("[%0t] b <= 1\n", $time)); flag_b <= 1'b1; end always @(flag_a) if ($time > 0) begin #1 `WRITE_VERBOSE(("[%0t] Checking if b == 0\n", $time)); if (flag_b !== 1'b0) $stop; #2 `WRITE_VERBOSE(("[%0t] Checking if b == 1\n", $time)); if (flag_b !== 1'b1) $stop; #10 $write("*-* All Finished *-*\n"); $finish; end initial #20 $stop; // timeout endmodule verilator-5.042/test_regress/t/t_timing_trace_fst.py0000755000542200017500000000117715101701376023315 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_timing_trace.v" test.compile(verilator_flags2=["--binary --trace-fst -Wno-MINTYPMAXDLY"]) test.execute() test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/uvm/0000755000542200017500000000000015101701376017675 5ustar mahmoudyfreeshellverilator-5.042/test_regress/t/uvm/uvm_pkg_all_v2017_1_0_nodpi.svh0000644000542200017500000566544315101701376025435 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Concatenated UVM header for internal testing // SPDX-License-Identifier: Apache-2.0 //---------------------------------------------------------------------- // To recreate: // Using verilator_ext_tests: // t_uvm_hello_v2017_1_0_nodpi --gold // //---------------------------------------------------------------------- // Copyright 2007-2011 Mentor Graphics Corporation // Copyright 2011 Synopsys, Inc. // Copyright 2007-2018 Cadence Design Systems, Inc. // Copyright 2013 NVIDIA Corporation // All Rights Reserved Worldwide // // Licensed under the Apache License, Version 2.0 (the // "License"); you may not use this file except in // compliance with the License. You may obtain a copy of // the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in // writing, software distributed under the License is // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // CONDITIONS OF ANY KIND, either express or implied. See // the License for the specific language governing // permissions and limitations under the License. //---------------------------------------------------------------------- `define UVM_NO_DPI `define UVM_PKG_SV `define UVM_MACROS_SVH `define UVM_STRING_QUEUE_STREAMING_PACK(q) uvm_pkg::m_uvm_string_queue_join(q) `define uvm_typename(X) $typename(X) `define uvm_delay(TIME) #(TIME); `define UVM_VERSION_DEFINES_SVH `define UVM_VERSION 2016 `define UVM_GLOBAL_DEFINES_SVH `define UVM_MAX_STREAMBITS 4096 `define UVM_PACKER_MAX_BYTES `UVM_MAX_STREAMBITS `define UVM_DEFAULT_TIMEOUT 9200s `define UVM_MESSAGE_DEFINES_SVH `define UVM_LINE_WIDTH 120 `define UVM_NUM_LINES 120 `define uvm_file `__FILE__ `define uvm_line `__LINE__ `define uvm_info(ID, MSG, VERBOSITY) \ begin \ if (uvm_report_enabled(VERBOSITY,UVM_INFO,ID)) \ uvm_report_info (ID, MSG, VERBOSITY, `uvm_file, `uvm_line, "", 1); \ end `define uvm_warning(ID, MSG) \ begin \ if (uvm_report_enabled(UVM_NONE,UVM_WARNING,ID)) \ uvm_report_warning (ID, MSG, UVM_NONE, `uvm_file, `uvm_line, "", 1); \ end `define uvm_error(ID, MSG) \ begin \ if (uvm_report_enabled(UVM_NONE,UVM_ERROR,ID)) \ uvm_report_error (ID, MSG, UVM_NONE, `uvm_file, `uvm_line, "", 1); \ end `define uvm_fatal(ID, MSG) \ begin \ if (uvm_report_enabled(UVM_NONE,UVM_FATAL,ID)) \ uvm_report_fatal (ID, MSG, UVM_NONE, `uvm_file, `uvm_line, "", 1); \ end `define uvm_info_context(ID, MSG, VERBOSITY, RO) \ begin \ if (RO.uvm_report_enabled(VERBOSITY,UVM_INFO,ID)) \ RO.uvm_report_info (ID, MSG, VERBOSITY, `uvm_file, `uvm_line, "", 1); \ end `define uvm_warning_context(ID, MSG, RO) \ begin \ if (RO.uvm_report_enabled(UVM_NONE,UVM_WARNING,ID)) \ RO.uvm_report_warning (ID, MSG, UVM_NONE, `uvm_file, `uvm_line, "", 1); \ end `define uvm_error_context(ID, MSG, RO) \ begin \ if (RO.uvm_report_enabled(UVM_NONE,UVM_ERROR,ID)) \ RO.uvm_report_error (ID, MSG, UVM_NONE, `uvm_file, `uvm_line, "", 1); \ end `define uvm_fatal_context(ID, MSG, RO) \ begin \ if (RO.uvm_report_enabled(UVM_NONE,UVM_FATAL,ID)) \ RO.uvm_report_fatal (ID, MSG, UVM_NONE, `uvm_file, `uvm_line, "", 1); \ end `define uvm_message_begin(SEVERITY, ID, MSG, VERBOSITY, FILE, LINE, RM) \ begin \ if (uvm_report_enabled(VERBOSITY,SEVERITY,ID)) begin \ uvm_report_message __uvm_msg; \ if (RM == null) RM = uvm_report_message::new_report_message(); \ __uvm_msg = RM; \ __uvm_msg.set_report_message(SEVERITY, ID, MSG, VERBOSITY, FILE, LINE, ""); `define uvm_message_end \ uvm_process_report_message(__uvm_msg); \ end \ end `define uvm_message_context_begin(SEVERITY, ID, MSG, VERBOSITY, FILE, LINE, RO, RM) \ begin \ uvm_report_object __report_object; \ __report_object = RO; \ if (__report_object.uvm_report_enabled(VERBOSITY,SEVERITY,ID)) begin \ uvm_report_message __uvm_msg; \ if (RM == null) RM = uvm_report_message::new_report_message(); \ __uvm_msg = RM; \ __uvm_msg.set_report_message(SEVERITY, ID, MSG, VERBOSITY, FILE, LINE, ""); `define uvm_message_context_end \ __report_object.uvm_process_report_message(__uvm_msg); \ end \ end `define uvm_info_begin(ID, MSG, VERBOSITY, RM = __uvm_msg) \ `uvm_message_begin(UVM_INFO, ID, MSG, VERBOSITY, `uvm_file, `uvm_line, RM) `define uvm_info_end \ `uvm_message_end `define uvm_warning_begin(ID, MSG, RM = __uvm_msg) \ `uvm_message_begin(UVM_WARNING, ID, MSG, UVM_NONE, `uvm_file, `uvm_line, RM) `define uvm_warning_end \ `uvm_message_end `define uvm_error_begin(ID, MSG, RM = __uvm_msg) \ `uvm_message_begin(UVM_ERROR, ID, MSG, UVM_NONE, `uvm_file, `uvm_line, RM) `define uvm_error_end \ `uvm_message_end `define uvm_fatal_begin(ID, MSG, RM = __uvm_msg) \ `uvm_message_begin(UVM_FATAL, ID, MSG, UVM_NONE, `uvm_file, `uvm_line, RM) `define uvm_fatal_end \ `uvm_message_end `define uvm_info_context_begin(ID, MSG, VERBOSITY, RO, RM = __uvm_msg) \ `uvm_message_context_begin(UVM_INFO, ID, MSG, VERBOSITY, `uvm_file, `uvm_line, RO, RM) `define uvm_info_context_end \ `uvm_message_context_end `define uvm_warning_context_begin(ID, MSG, RO, RM = __uvm_msg) \ `uvm_message_context_begin(UVM_WARNING, ID, MSG, UVM_NONE, `uvm_file, `uvm_line, RO, RM) `define uvm_warning_context_end \ `uvm_message_context_end `define uvm_error_context_begin(ID, MSG, RO, RM = __uvm_msg) \ `uvm_message_context_begin(UVM_ERROR, ID, MSG, UVM_NONE, `uvm_file, `uvm_line, RO, RM) `define uvm_error_context_end \ `uvm_message_context_end `define uvm_fatal_context_begin(ID, MSG, RO, RM = __uvm_msg) \ `uvm_message_context_begin(UVM_FATAL, ID, MSG, UVM_NONE, `uvm_file, `uvm_line, RO, RM) `define uvm_fatal_context_end \ `uvm_message_context_end `define uvm_message_add_tag(NAME, VALUE, ACTION=(UVM_LOG|UVM_RM_RECORD)) \ __uvm_msg.add_string(NAME, VALUE, ACTION); `define uvm_message_add_int(VAR, RADIX, LABEL="", ACTION=(UVM_LOG|UVM_RM_RECORD)) \ if (LABEL == "") \ __uvm_msg.add_int(`"VAR`", VAR, $bits(VAR), RADIX, ACTION); \ else \ __uvm_msg.add_int(LABEL, VAR, $bits(VAR), RADIX, ACTION); `define uvm_message_add_string(VAR, LABEL="", ACTION=(UVM_LOG|UVM_RM_RECORD)) \ if (LABEL == "") \ __uvm_msg.add_string(`"VAR`", VAR, ACTION); \ else \ __uvm_msg.add_string(LABEL, VAR, ACTION); `define uvm_message_add_object(VAR, LABEL="", ACTION=(UVM_LOG|UVM_RM_RECORD)) \ if (LABEL == "") \ __uvm_msg.add_object(`"VAR`", VAR, ACTION); \ else \ __uvm_msg.add_object(LABEL, VAR, ACTION); `define UVM_PHASE_DEFINES_SVH `define m_uvm_task_phase(PHASE,COMP,PREFIX) \ class PREFIX``PHASE``_phase extends uvm_task_phase; \ virtual task exec_task(uvm_component comp, uvm_phase phase); \ COMP comp_; \ if ($cast(comp_,comp)) \ comp_.``PHASE``_phase(phase); \ endtask \ local static PREFIX``PHASE``_phase m_inst; \ `uvm_type_name_decl(`"PREFIX``PHASE``_phase`") \ static function PREFIX``PHASE``_phase get(); \ if(m_inst == null) begin \ m_inst = new; \ end \ return m_inst; \ endfunction \ protected function new(string name=`"PHASE`"); \ super.new(name); \ endfunction \ endclass \ `define m_uvm_topdown_phase(PHASE,COMP,PREFIX) \ class PREFIX``PHASE``_phase extends uvm_topdown_phase; \ virtual function void exec_func(uvm_component comp, uvm_phase phase); \ COMP comp_; \ if ($cast(comp_,comp)) \ comp_.``PHASE``_phase(phase); \ endfunction \ local static PREFIX``PHASE``_phase m_inst; \ `uvm_type_name_decl(`"PREFIX``PHASE``_phase`") \ static function PREFIX``PHASE``_phase get(); \ if(m_inst == null) begin \ m_inst = new(); \ end \ return m_inst; \ endfunction \ protected function new(string name=`"PHASE`"); \ super.new(name); \ endfunction \ endclass \ `define m_uvm_bottomup_phase(PHASE,COMP,PREFIX) \ class PREFIX``PHASE``_phase extends uvm_bottomup_phase; \ virtual function void exec_func(uvm_component comp, uvm_phase phase); \ COMP comp_; \ if ($cast(comp_,comp)) \ comp_.``PHASE``_phase(phase); \ endfunction \ static PREFIX``PHASE``_phase m_inst; \ `uvm_type_name_decl(`"PREFIX``PHASE``_phase`") \ static function PREFIX``PHASE``_phase get(); \ if(m_inst == null) begin \ m_inst = new(); \ end \ return m_inst; \ endfunction \ protected function new(string name=`"PHASE`"); \ super.new(name); \ endfunction \ endclass \ `define uvm_builtin_task_phase(PHASE) \ `m_uvm_task_phase(PHASE,uvm_component,uvm_) `define uvm_builtin_topdown_phase(PHASE) \ `m_uvm_topdown_phase(PHASE,uvm_component,uvm_) `define uvm_builtin_bottomup_phase(PHASE) \ `m_uvm_bottomup_phase(PHASE,uvm_component,uvm_) `define uvm_user_task_phase(PHASE,COMP,PREFIX) \ `m_uvm_task_phase(PHASE,COMP,PREFIX) `define uvm_user_topdown_phase(PHASE,COMP,PREFIX) \ `m_uvm_topdown_phase(PHASE,COMP,PREFIX) `define uvm_user_bottomup_phase(PHASE,COMP,PREFIX) \ `m_uvm_bottomup_phase(PHASE,COMP,PREFIX) `define UVM_PRINTER_DEFINES_SVH `define uvm_print_int(VALUE, SIZE, RADIX=UVM_NORADIX, VALUE_TYPE=integral, PRINTER=printer) \ `uvm_print_named_int(`"VALUE`", VALUE, SIZE, RADIX, VALUE_TYPE, PRINTER) `define uvm_print_named_int(NAME, VALUE, SIZE, RADIX=UVM_NORADIX, VALUE_TYPE=integral, PRINTER=printer) \ if (SIZE > 64) \ PRINTER.print_field(NAME, VALUE, SIZE, RADIX, ".", `"VALUE_TYPE`"); \ else \ PRINTER.print_field_int(NAME, VALUE, SIZE, RADIX, ".", `"VALUE_TYPE`"); `define uvm_print_real(VALUE, PRINTER=printer) \ `uvm_print_named_real(`"VALUE`", VALUE, PRINTER) `define uvm_print_named_real(NAME, VALUE, PRINTER=printer) \ PRINTER.print_real(NAME, VALUE); `define uvm_print_enum(TYPE, VALUE, PRINTER=printer) \ `uvm_print_named_enum(TYPE, `"VALUE`", VALUE, PRINTER) `define uvm_print_named_enum(TYPE, NAME, VALUE, PRINTER=printer) \ if (VALUE.name() == "") \ `uvm_print_named_int(NAME, VALUE, $bits(VALUE), UVM_NORADIX, TYPE, PRINTER) \ else \ PRINTER.print_generic(NAME, `"TYPE`", $bits(VALUE), VALUE.name()); `define uvm_print_object(VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, PRINTER=printer) \ `uvm_print_named_object(`"VALUE`", VALUE, RECURSION_POLICY, PRINTER) `define uvm_print_named_object(NAME, VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, PRINTER=printer) \ if ((RECURSION_POLICY != UVM_DEFAULT_POLICY) && \ (RECURSION_POLICY != PRINTER.get_recursion_policy())) begin \ uvm_recursion_policy_enum __saved_recursion_policy = PRINTER.get_recursion_policy(); \ PRINTER.set_recursion_policy(RECURSION_POLICY); \ `m_uvm_print_named_object(NAME, VALUE, PRINTER) \ PRINTER.set_recursion_policy(__saved_recursion_policy); \ end \ else begin \ `m_uvm_print_named_object(NAME, VALUE, PRINTER) \ end `define m_uvm_print_named_object(NAME, VALUE, PRINTER) \ if (PRINTER.object_printed(VALUE, PRINTER.get_recursion_policy()) != uvm_policy::NEVER) begin \ uvm_recursion_policy_enum __saved_recursion_policy = PRINTER.get_recursion_policy(); \ PRINTER.set_recursion_policy(UVM_REFERENCE); \ PRINTER.print_object(NAME, VALUE); \ PRINTER.set_recursion_policy(__saved_recursion_policy); \ end \ else begin \ PRINTER.print_object(NAME, VALUE); \ end `define uvm_print_string(VALUE, PRINTER=printer) \ `uvm_print_named_string(`"VALUE`", VALUE, PRINTER) `define uvm_print_named_string(NAME, VALUE, PRINTER=printer) \ PRINTER.print_string(NAME, VALUE); `define uvm_print_qda_int(ARRAY_TYPE, VALUE, RADIX=UVM_NORADIX, VALUE_TYPE=integral, PRINTER=printer) \ `uvm_print_named_qda_int(ARRAY_TYPE, `"VALUE`", VALUE, RADIX, VALUE_TYPE, PRINTER) `define uvm_print_named_qda_int(ARRAY_TYPE, NAME, VALUE, RADIX=UVM_NORADIX, VALUE_TYPE=integral, PRINTER=printer) \ begin \ int __tmp_max = $right(VALUE) + 1; \ PRINTER.print_array_header(NAME, \ __tmp_max, \ `"ARRAY_TYPE``(``VALUE_TYPE``)`"); \ if ((PRINTER.get_max_depth() == -1) || \ (PRINTER.get_active_object_depth() < PRINTER.get_max_depth()+1)) begin \ int __tmp_begin_elements, __tmp_end_elements; \ __tmp_begin_elements = PRINTER.get_begin_elements(); \ __tmp_end_elements = PRINTER.get_end_elements(); \ /* Fast Bypass */ \ if (__tmp_begin_elements == -1 || __tmp_end_elements == -1) begin \ foreach (VALUE[__tmp_index]) begin \ `uvm_print_named_int($sformatf("[%0d]", __tmp_index), \ VALUE[__tmp_index], \ $bits(VALUE[__tmp_index]), \ RADIX, \ VALUE_TYPE, \ PRINTER) \ end \ end \ else begin \ int __tmp_curr; \ foreach(VALUE[__tmp_index]) begin \ if (__tmp_curr < __tmp_begin_elements) begin \ `uvm_print_named_int($sformatf("[%0d]", __tmp_index), \ VALUE[__tmp_index], \ $bits(VALUE[__tmp_index]), \ RADIX, \ VALUE_TYPE, \ PRINTER) \ end \ else \ break; \ __tmp_curr++; \ end \ if (__tmp_curr < __tmp_max ) begin \ if ((__tmp_max - __tmp_end_elements) > __tmp_curr) \ __tmp_curr = __tmp_max - __tmp_end_elements; \ if (__tmp_curr < __tmp_begin_elements) \ __tmp_curr = __tmp_begin_elements; \ else \ PRINTER.print_array_range(__tmp_begin_elements, __tmp_curr-1); \ while (__tmp_curr < __tmp_max) begin \ `uvm_print_named_int($sformatf("[%0d]", __tmp_curr), \ VALUE[__tmp_curr], \ $bits(VALUE[__tmp_curr]), \ RADIX, \ VALUE_TYPE, \ PRINTER) \ __tmp_curr++; \ end \ end \ end \ end \ PRINTER.print_array_footer(__tmp_max); \ end `define uvm_print_array_int(VALUE, RADIX=UVM_NORADIX, VALUE_TYPE=integral, PRINTER=printer) \ `uvm_print_named_qda_int(da, `"VALUE`", VALUE, RADIX, VALUE_TYPE, PRINTER) `define uvm_print_named_array_int(NAME, VALUE, RADIX=UVM_NORADIX, VALUE_TYPE=integral, PRINTER=printer) \ `uvm_print_named_qda_int(da, NAME, VALUE, RADIX, VALUE_TYPE, PRINTER) `define uvm_print_sarray_int(VALUE, RADIX=UVM_RADIX, VALUE_TYPE=integral, PRINTER=printer) \ `uvm_print_named_qda_int(sa, `"VALUE`", VALUE, RADIX, VALUE_TYPE, PRINTER) `define uvm_print_named_sarray_int(NAME, VALUE, RADIX=UVM_NORADIX, VALUE_TYPE=integral, PRINTER=printer) \ `uvm_print_named_qda_int(sa, NAME, VALUE, RADIX, VALUE_TYPE, PRINTER) `define uvm_print_queue_int(VALUE, RADIX=UVM_NORADIX, VALUE_TYPE=integral, PRINTER=printer) \ `uvm_print_named_qda_int(queue, `"VALUE`", VALUE, RADIX, VALUE_TYPE, PRINTER) `define uvm_print_named_queue_int(NAME, VALUE, RADIX=UVM_NORADIX, VALUE_TYPE=integral, PRINTER=printer) \ `uvm_print_named_qda_int(queue, NAME, VALUE, RADIX, VALUE_TYPE, PRINTER) `define uvm_print_qda_real(ARRAY_TYPE, VALUE, PRINTER=printer) \ `uvm_print_named_qda_real(ARRAY_TYPE, `"VALUE`", VALUE, PRINTER) `define uvm_print_named_qda_real(ARRAY_TYPE, NAME, VALUE, PRINTER=printer) \ begin \ int __tmp_max = $right(VALUE) + 1; \ PRINTER.print_array_header(NAME, \ __tmp_max, \ `"ARRAY_TYPE``(real)`"); \ if ((PRINTER.get_max_depth() == -1) || \ (PRINTER.get_active_object_depth() < PRINTER.get_max_depth()+1)) begin \ int __tmp_begin_elements, __tmp_end_elements; \ __tmp_begin_elements = PRINTER.get_begin_elements(); \ __tmp_end_elements = PRINTER.get_end_elements(); \ /* Fast Bypass */ \ if (__tmp_begin_elements == -1 || __tmp_end_elements == -1) begin \ foreach (VALUE[__tmp_index]) begin \ `uvm_print_named_real($sformatf("[%0d]", __tmp_index), \ VALUE[__tmp_index], \ PRINTER) \ end \ end \ else begin \ int __tmp_curr; \ foreach(VALUE[__tmp_index]) begin \ if (__tmp_curr < __tmp_begin_elements) begin \ `uvm_print_named_real($sformatf("[%0d]", __tmp_index), \ VALUE[__tmp_index], \ PRINTER) \ end \ else \ break; \ __tmp_curr++; \ end \ if (__tmp_curr < __tmp_max ) begin \ if ((__tmp_max - __tmp_end_elements) > __tmp_curr) \ __tmp_curr = __tmp_max - __tmp_end_elements; \ if (__tmp_curr < __tmp_begin_elements) \ __tmp_curr = __tmp_begin_elements; \ else \ PRINTER.print_array_range(__tmp_begin_elements, __tmp_curr-1); \ while (__tmp_curr < __tmp_max) begin \ `uvm_print_named_real($sformatf("[%0d]", __tmp_curr), \ VALUE[__tmp_curr], \ PRINTER) \ __tmp_curr++; \ end \ end \ end \ end \ PRINTER.print_array_footer(__tmp_max); \ end `define uvm_print_array_real(VALUE, PRINTER=printer) \ `uvm_print_named_qda_real(da, `"VALUE`", VALUE, PRINTER) `define uvm_print_named_array_real(NAME, VALUE, PRINTER=printer) \ `uvm_print_named_qda_real(da, NAME, VALUE, PRINTER) `define uvm_print_sarray_real(VALUE, PRINTER=printer) \ `uvm_print_named_qda_real(sa, `"VALUE`", VALUE, PRINTER) `define uvm_print_named_sarray_real(NAME, VALUE, PRINTER=printer) \ `uvm_print_named_qda_real(sa, NAME, VALUE, PRINTER) `define uvm_print_queue_real(VALUE,PRINTER=printer) \ `uvm_print_named_qda_real(queue, `"VALUE`", VALUE, PRINTER) `define uvm_print_named_queue_real(NAME, VALUE, PRINTER=printer) \ `uvm_print_named_qda_real(queue, NAME, VALUE, PRINTER) `define uvm_print_qda_enum(ARRAY_TYPE, TYPE, VALUE, PRINTER=printer) \ `uvm_print_named_qda_enum(ARRAY_TYPE, TYPE, `"VALUE`", VALUE, PRINTER) `define uvm_print_named_qda_enum(ARRAY_TYPE, TYPE, NAME, VALUE, PRINTER=printer) \ begin \ int __tmp_max = $right(VALUE) + 1; \ PRINTER.print_array_header(NAME, \ __tmp_max, \ {`"ARRAY_TYPE``(`", `"TYPE`", ")"}); \ if ((PRINTER.get_max_depth() == -1) || \ (PRINTER.get_active_object_depth() < PRINTER.get_max_depth()+1)) begin \ int __tmp_begin_elements, __tmp_end_elements; \ __tmp_begin_elements = PRINTER.get_begin_elements(); \ __tmp_end_elements = PRINTER.get_end_elements(); \ /* Fast Bypass */ \ if (__tmp_begin_elements == -1 || __tmp_end_elements == -1) begin \ foreach (VALUE[__tmp_index]) begin \ `uvm_print_named_enum(TYPE, \ $sformatf("[%0d]", __tmp_index), \ VALUE[__tmp_index], \ PRINTER) \ end \ end \ else begin \ int __tmp_curr; \ foreach(VALUE[__tmp_index]) begin \ if (__tmp_curr < __tmp_begin_elements) begin \ `uvm_print_named_enum(TYPE, \ $sformatf("[%0d]", __tmp_index), \ VALUE[__tmp_index], \ PRINTER) \ end \ else \ break; \ __tmp_curr++; \ end \ if (__tmp_curr < __tmp_max ) begin \ if ((__tmp_max - __tmp_end_elements) > __tmp_curr) \ __tmp_curr = __tmp_max - __tmp_end_elements; \ if (__tmp_curr < __tmp_begin_elements) \ __tmp_curr = __tmp_begin_elements; \ else \ PRINTER.print_array_range(__tmp_begin_elements, __tmp_curr-1); \ while (__tmp_curr < __tmp_max) begin \ `uvm_print_named_enum(TYPE, \ $sformatf("[%0d]", __tmp_curr), \ VALUE[__tmp_curr], \ PRINTER) \ __tmp_curr++; \ end \ end \ end \ end \ PRINTER.print_array_footer(__tmp_max); \ end `define uvm_print_array_enum(TYPE, VALUE, PRINTER=printer) \ `uvm_print_named_qda_enum(da, `"VALUE`", TYPE, VALUE, PRINTER) `define uvm_print_named_array_enum(TYPE, NAME, VALUE, PRINTER=printer) \ `uvm_print_named_qda_enum(da, TYPE, NAME, VALUE, PRINTER) `define uvm_print_sarray_enum(TYPE, VALUE, PRINTER=printer) \ `uvm_print_named_qda_enum(sa, TYPE, `"VALUE`", VALUE, PRINTER) `define uvm_print_named_sarray_enum(TYPE, NAME, VALUE, PRINTER=printer) \ `uvm_print_named_qda_enum(sa, TYPE, NAME, VALUE, PRINTER) `define uvm_print_queue_enum(TYPE, VALUE, PRINTER=printer) \ `uvm_print_named_qda_enum(queue, TYPE, `"VALUE`", VALUE, PRINTER) `define uvm_print_named_queue_enum(TYPE, NAME, VALUE, PRINTER=printer) \ `uvm_print_named_qda_enum(queue, TYPE, NAME, VALUE, PRINTER) `define uvm_print_qda_object(ARRAY_TYPE, VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, PRINTER=printer) \ `uvm_print_named_qda_object(ARRAY_TYPE, `"VALUE`", VALUE, RECURSION_POLICY, PRINTER) `define uvm_print_named_qda_object(ARRAY_TYPE, NAME, VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, PRINTER=printer) \ begin \ int __tmp_max = $right(VALUE) + 1; \ PRINTER.print_array_header(NAME, \ __tmp_max, \ `"ARRAY_TYPE``(object)`"); \ if ((PRINTER.get_max_depth() == -1) || \ (PRINTER.get_active_object_depth() < PRINTER.get_max_depth()+1)) begin \ uvm_recursion_policy_enum __tmp_recursion_policy; \ int __tmp_begin_elements, __tmp_end_elements; \ __tmp_begin_elements = PRINTER.get_begin_elements(); \ __tmp_end_elements = PRINTER.get_end_elements(); \ __tmp_recursion_policy = PRINTER.get_recursion_policy(); \ if ((RECURSION_POLICY != UVM_DEFAULT_POLICY) && \ (__tmp_recursion_policy != RECURSION_POLICY)) \ PRINTER.set_recursion_policy(RECURSION_POLICY); \ /* Fast Bypass */ \ if (__tmp_begin_elements == -1 || __tmp_end_elements == -1) begin \ foreach (VALUE[__tmp_index]) begin \ `m_uvm_print_named_object($sformatf("[%0d]", __tmp_index), \ VALUE[__tmp_index], \ PRINTER) \ end \ end \ else begin \ int __tmp_curr; \ foreach(VALUE[__tmp_index]) begin \ if (__tmp_curr < __tmp_begin_elements) begin \ `m_uvm_print_named_object($sformatf("[%0d]", __tmp_index), \ VALUE[__tmp_index], \ PRINTER) \ end \ else \ break; \ __tmp_curr++; \ end \ if (__tmp_curr < __tmp_max ) begin \ if ((__tmp_max - __tmp_end_elements) > __tmp_curr) \ __tmp_curr = __tmp_max - __tmp_end_elements; \ if (__tmp_curr < __tmp_begin_elements) \ __tmp_curr = __tmp_begin_elements; \ else \ PRINTER.print_array_range(__tmp_begin_elements, __tmp_curr-1); \ while (__tmp_curr < __tmp_max) begin \ `m_uvm_print_named_object($sformatf("[%0d]", __tmp_curr), \ VALUE[__tmp_curr], \ PRINTER) \ __tmp_curr++; \ end \ end \ end \ if ((RECURSION_POLICY != UVM_DEFAULT_POLICY) && \ (__tmp_recursion_policy != RECURSION_POLICY)) \ PRINTER.set_recursion_policy(__tmp_recursion_policy); \ end \ PRINTER.print_array_footer(__tmp_max); \ end `define uvm_print_array_object(VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, PRINTER=printer) \ `uvm_print_named_qda_object(da, `"VALUE`", VALUE, RECURSION_POLICY, PRINTER) `define uvm_print_named_array_object(NAME, VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, PRINTER=printer) \ `uvm_print_named_qda_object(da, NAME, VALUE, RECURSION_POLICY, PRINTER) `define uvm_print_sarray_object(VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, PRINTER=printer) \ `uvm_print_named_qda_object(sa, `"VALUE`", VALUE, RECURSION_POLICY, PRINTER) `define uvm_print_named_sarray_object(NAME, VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, PRINTER=printer) \ `uvm_print_named_qda_object(sa, NAME, VALUE, RECURSION_POLICY, PRINTER) `define uvm_print_queue_object(VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, PRINTER=printer) \ `uvm_print_named_qda_object(queue, `"VALUE`", VALUE, RECURSION_POLICY, PRINTER) `define uvm_print_named_queue_object(NAME, VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, PRINTER=printer) \ `uvm_print_named_qda_object(queue, NAME, VALUE, RECURSION_POLICY, PRINTER) `define uvm_print_qda_string(ARRAY_TYPE, VALUE, PRINTER=printer) \ `uvm_print_named_qda_string(ARRAY_TYPE, `"VALUE`", VALUE, PRINTER) `define uvm_print_named_qda_string(ARRAY_TYPE, NAME, VALUE, PRINTER=printer) \ begin \ int __tmp_max = $right(VALUE) + 1; \ PRINTER.print_array_header(NAME, \ __tmp_max, \ `"ARRAY_TYPE``(string)`"); \ if ((PRINTER.get_max_depth() == -1) || \ (PRINTER.get_active_object_depth() < PRINTER.get_max_depth()+1)) begin \ int __tmp_begin_elements, __tmp_end_elements; \ __tmp_begin_elements = PRINTER.get_begin_elements(); \ __tmp_end_elements = PRINTER.get_end_elements(); \ /* Fast Bypass */ \ if (__tmp_begin_elements == -1 || __tmp_end_elements == -1) begin \ foreach (VALUE[__tmp_index]) begin \ `uvm_print_named_string($sformatf("[%0d]", __tmp_index), \ VALUE[__tmp_index], \ PRINTER) \ end \ end \ else begin \ int __tmp_curr; \ foreach(VALUE[__tmp_index]) begin \ if (__tmp_curr < __tmp_begin_elements) begin \ `uvm_print_named_string($sformatf("[%0d]", __tmp_index), \ VALUE[__tmp_index], \ PRINTER) \ end \ else \ break; \ __tmp_curr++; \ end \ if (__tmp_curr < __tmp_max ) begin \ if ((__tmp_max - __tmp_end_elements) > __tmp_curr) \ __tmp_curr = __tmp_max - __tmp_end_elements; \ if (__tmp_curr < __tmp_begin_elements) \ __tmp_curr = __tmp_begin_elements; \ else \ PRINTER.print_array_range(__tmp_begin_elements, __tmp_curr-1); \ while (__tmp_curr < __tmp_max) begin \ `uvm_print_named_string($sformatf("[%0d]", __tmp_curr), \ VALUE[__tmp_curr], \ PRINTER) \ __tmp_curr++; \ end \ end \ end \ end \ PRINTER.print_array_footer(__tmp_max); \ end `define uvm_print_array_string(VALUE, PRINTER=printer) \ `uvm_print_named_qda_string(da, `"VALUE`", VALUE, PRINTER) `define uvm_print_named_array_string(NAME, VALUE, PRINTER=printer) \ `uvm_print_named_qda_string(da, NAME, VALUE, PRINTER) `define uvm_print_sarray_string(VALUE, PRINTER=printer) \ `uvm_print_named_qda_string(sa, `"VALUE`", VALUE, PRINTER) `define uvm_print_named_sarray_string(NAME, VALUE, PRINTER=printer) \ `uvm_print_named_qda_string(sa, NAME, VALUE, PRINTER) `define uvm_print_queue_string(VALUE, PRINTER=printer) \ `uvm_print_named_qda_string(queue, `"VALUE`", VALUE, PRINTER) `define uvm_print_named_queue_string(NAME, VALUE, PRINTER=printer) \ `uvm_print_named_qda_string(queue, NAME, VALUE, PRINTER) `define uvm_print_aa_int_string(VALUE, RADIX=UVM_NORADIX, VALUE_TYPE=integral, PRINTER=printer) \ `uvm_print_named_aa_int_string(`"VALUE`", VALUE, RADIX, VALUE_TYPE, PRINTER) `define uvm_print_named_aa_int_string(NAME, VALUE, RADIX=UVM_NORADIX, VALUE_TYPE=integral, PRINTER=printer) \ begin \ PRINTER.print_array_header(NAME, \ VALUE.num(), \ `"aa(``VALUE_TYPE``,string)`"); \ if ((PRINTER.get_max_depth() == -1) || \ (PRINTER.get_active_object_depth() < PRINTER.get_max_depth()+1)) begin \ foreach(VALUE[__tmp_index]) \ `uvm_print_named_int($sformatf("[%s]", __tmp_index), \ VALUE[__tmp_index], \ $bits(VALUE[__tmp_index]), \ RADIX, \ VALUE_TYPE, \ PRINTER ) \ end \ PRINTER.print_array_footer(VALUE.num()); \ end `define uvm_print_aa_object_string(VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, PRINTER=printer) \ `uvm_print_named_aa_object_string(`"VALUE`", VALUE, RECURSION_POLICY, PRINTER) `define uvm_print_named_aa_object_string(NAME, VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, PRINTER=printer) \ begin \ PRINTER.print_array_header(NAME, \ VALUE.num(), \ "aa(object,string)"); \ if ((PRINTER.get_max_depth() == -1) || \ (PRINTER.get_active_object_depth() < PRINTER.get_max_depth()+1)) begin \ uvm_recursion_policy_enum __tmp_recursion_policy; \ __tmp_recursion_policy = PRINTER.get_recursion_policy(); \ if ((RECURSION_POLICY != UVM_DEFAULT_POLICY) && \ (__tmp_recursion_policy != RECURSION_POLICY)) \ PRINTER.set_recursion_policy(RECURSION_POLICY); \ foreach(VALUE[__tmp_index]) \ `m_uvm_print_named_object($sformatf("[%s]", __tmp_index), \ VALUE[__tmp_index], \ PRINTER ) \ if ((RECURSION_POLICY != UVM_DEFAULT_POLICY) && \ (__tmp_recursion_policy != RECURSION_POLICY)) \ PRINTER.set_recursion_policy(__tmp_recursion_policy); \ end \ PRINTER.print_array_footer(VALUE.num()); \ end `define uvm_print_aa_string_string(VALUE, PRINTER=printer) \ `uvm_print_named_aa_string_string(`"VALUE`", VALUE, PRINTER) `define uvm_print_named_aa_string_string(NAME, VALUE, PRINTER=printer) \ begin \ PRINTER.print_array_header(NAME, \ VALUE.num(), \ "aa(string,string)"); \ if ((PRINTER.get_max_depth() == -1) || \ (PRINTER.get_active_object_depth() < PRINTER.get_max_depth()+1)) begin \ foreach(VALUE[__tmp_index]) \ `uvm_print_named_string($sformatf("[%s]", __tmp_index), \ VALUE[__tmp_index], \ PRINTER ) \ end \ PRINTER.print_array_footer(VALUE.num()); \ end `define uvm_print_aa_int_int(VALUE, RADIX=UVM_NORADIX, VALUE_TYPE=int, INDEX_TYPE=int, PRINTER=printer) \ `uvm_print_named_aa_int_int(`"VALUE`", VALUE, RADIX, VALUE_TYPE, INDEX_TYPE, PRINTER) `define uvm_print_named_aa_int_int(NAME, VALUE, RADIX=UVM_NORADIX, VALUE_TYPE=int, INDEX_TYPE=int, PRINTER=printer) \ begin \ PRINTER.print_array_header(NAME, \ VALUE.num(), \ `"aa(``VALUE_TYPE``,``INDEX_TYPE``)`"); \ if ((PRINTER.get_max_depth() == -1) || \ (PRINTER.get_active_object_depth() < PRINTER.get_max_depth()+1)) begin \ foreach(VALUE[__tmp_index]) \ `uvm_print_named_int($sformatf("[%0d]", __tmp_index), \ VALUE[__tmp_index], \ $bits(VALUE[__tmp_index]), \ RADIX, \ VALUE_TYPE, \ PRINTER ) \ end \ PRINTER.print_array_footer(VALUE.num()); \ end `define uvm_print_aa_object_int(VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, INDEX_TYPE=int, PRINTER=printer) \ `uvm_print_named_aa_object_int(`"VALUE`", VALUE, RECURSION_POLICY, INDEX_TYPE, PRINTER) `define uvm_print_named_aa_object_int(NAME, VALUE, RECURSION_POLICY=UVM_DEFAULT_POLICY, INDEX_TYPE=int, PRINTER=printer) \ begin \ PRINTER.print_array_header(NAME, \ VALUE.num(), \ `"aa(object,``INDEX_TYPE``)`"); \ if ((PRINTER.get_max_depth() == -1) || \ (PRINTER.get_active_object_depth() < PRINTER.get_max_depth()+1)) begin \ uvm_recursion_policy_enum __tmp_recursion_policy; \ __tmp_recursion_policy = PRINTER.get_recursion_policy(); \ if ((RECURSION_POLICY != UVM_DEFAULT_POLICY) && \ (__tmp_recursion_policy != RECURSION_POLICY)) \ PRINTER.set_recursion_policy(RECURSION_POLICY); \ foreach(VALUE[__tmp_index]) \ `m_uvm_print_named_object($sformatf("[%0d]", __tmp_index), \ VALUE[__tmp_index], \ PRINTER ) \ if ((RECURSION_POLICY != UVM_DEFAULT_POLICY) && \ (__tmp_recursion_policy != RECURSION_POLICY)) \ PRINTER.set_recursion_policy(__tmp_recursion_policy); \ end \ PRINTER.print_array_footer(VALUE.num()); \ end `define uvm_print_aa_string_int(VALUE, INDEX_TYPE=int, PRINTER=printer) \ `uvm_print_named_aa_string_int(`"VALUE`", VALUE, INDEX_TYPE, PRINTER) `define uvm_print_named_aa_string_int(NAME, VALUE, INDEX_TYPE=int, PRINTER=printer) \ begin \ PRINTER.print_array_header(NAME, \ VALUE.num(), \ `"aa(string,``INDEX_TYPE``)`"); \ if ((PRINTER.get_max_depth() == -1) || \ (PRINTER.get_active_object_depth() < PRINTER.get_max_depth()+1)) begin \ foreach(VALUE[__tmp_index]) \ `uvm_print_named_string($sformatf("[%0d]", __tmp_index), \ VALUE[__tmp_index], \ PRINTER ) \ end \ PRINTER.print_array_footer(VALUE.num()); \ end `define uvm_print_aa_int_enum(ENUM_TYPE, VALUE, RADIX=UVM_NORADIX, VALUE_TYPE=int, PRINTER=printer) \ `uvm_print_named_aa_int_enum(`"VALUE`", ENUM_TYPE, VALUE, RADIX, VALUE_TYPE, PRINTER) `define uvm_print_named_aa_int_enum(NAME, ENUM_TYPE, VALUE, RADIX=UVM_NORADIX, VALUE_TYPE=int, PRINTER=printer) \ begin \ PRINTER.print_array_header(NAME, \ VALUE.num(), \ `"aa(``VALUE_TYPE``,``ENUM_TYPE``)`"); \ if ((PRINTER.get_max_depth() == -1) || \ (PRINTER.get_active_object_depth() < PRINTER.get_max_depth()+1)) begin \ foreach(VALUE[__tmp_index]) \ `uvm_print_named_int((__tmp_index.name() == "") ? $sformatf("[%s'(%0d)]", `"ENUM_TYPE`",__tmp_index) \ : $sformatf("[%s]", __tmp_index.name()), \ VALUE[__tmp_index], \ $bits(VALUE[__tmp_index]), \ RADIX, \ VALUE_TYPE, \ PRINTER ) \ end \ PRINTER.print_array_footer(VALUE.num()); \ end `define UVM_COMPARER_DEFINES_SVH `define m_uvm_compare_threshold_begin(COMPARER) \ if ((!COMPARER.get_threshold() || \ (COMPARER.get_result() < COMPARER.get_threshold()))) begin \ `define m_uvm_compare_threshold_end \ end `define m_uvm_compare_begin(LVALUE, RVALUE, COMPARER=comparer) \ `m_uvm_compare_threshold_begin(COMPARER) \ if ((LVALUE) !== (RVALUE)) begin \ `define m_uvm_compare_end \ end \ `m_uvm_compare_threshold_end `define uvm_compare_int(LVALUE, RVALUE, RADIX, COMPARER=comparer) \ `uvm_compare_named_int(`"LVALUE`", LVALUE, RVALUE, RADIX, COMPARER) `define uvm_compare_named_int(NAME, LVALUE, RVALUE, RADIX, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ if ($bits(LVALUE) <= 64) \ void'(COMPARER.compare_field_int(NAME , LVALUE, RVALUE, $bits(LVALUE), RADIX)); \ else \ void'(COMPARER.compare_field(NAME , LVALUE, RVALUE, $bits(LVALUE), RADIX)); \ `m_uvm_compare_end `define uvm_compare_enum(LVALUE, RVALUE, TYPE, COMPARER=comparer) \ `uvm_compare_named_enum(`"LVALUE`", LVALUE, RVALUE, TYPE, COMPARER) `define uvm_compare_named_enum(NAME, LVALUE, RVALUE, TYPE, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ void'(COMPARER.compare_string(NAME , \ $sformatf("%s'(%s)", `"TYPE`", LVALUE.name()), \ $sformatf("%s'(%s)", `"TYPE`", RVALUE.name())) ); \ `m_uvm_compare_end `define uvm_compare_real(LVALUE, RVALUE, COMPARER=comparer) \ `uvm_compare_named_real(`"LVALUE`", LVALUE, RVALUE, COMPARER) `define uvm_compare_named_real(NAME, LVALUE, RVALUE, COMPARER=comparer) \ `m_uvm_compare_threshold_begin(COMPARER) \ if ((LVALUE) != (RVALUE)) begin \ void'(COMPARER.compare_field_real(NAME , LVALUE, RVALUE)); \ end \ `m_uvm_compare_threshold_end `define uvm_compare_object(LVALUE, RVALUE, POLICY=UVM_DEFAULT_POLICY, COMPARER=comparer) \ `uvm_compare_named_object(`"LVALUE`", LVALUE, RVALUE, POLICY, COMPARER) `define uvm_compare_named_object(NAME, LVALUE, RVALUE, POLICY=UVM_DEFAULT_POLICY, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ uvm_recursion_policy_enum prev_rec__; \ prev_rec__ = COMPARER.get_recursion_policy(); \ if (POLICY != UVM_DEFAULT_POLICY) \ COMPARER.set_recursion_policy(POLICY); \ `m_uvm_compare_named_object(NAME, LVALUE, RVALUE, COMPARER) \ if (POLICY != UVM_DEFAULT_POLICY) \ COMPARER.set_recursion_policy(prev_rec__); \ `m_uvm_compare_end `define m_uvm_compare_named_object(NAME, LVALUE, RVALUE, COMPARER) \ if (COMPARER.get_recursion_policy() != UVM_REFERENCE) begin \ bit rv; \ uvm_policy::recursion_state_e state; \ state = COMPARER.object_compared(LVALUE, RVALUE, COMPARER.get_recursion_policy(), rv); \ if ((state == uvm_policy::FINISHED) && \ !rv) \ COMPARER.print_msg($sformatf("'%s' miscompared using saved return value", NAME)); \ else if (state == uvm_policy::NEVER) \ void'(COMPARER.compare_object(NAME, LVALUE, RVALUE)); \ /* else skip to avoid infinite loop */ \ end \ else begin \ void'(COMPARER.compare_object(NAME, LVALUE, RVALUE)); \ end `define uvm_compare_string(LVALUE, RVALUE, COMPARER=comparer) \ `uvm_compare_named_string(`"LVALUE`", LVALUE, RVALUE, COMPARER) `define uvm_compare_named_string(NAME, LVALUE, RVALUE, COMPARER=comparer) \ `m_uvm_compare_threshold_begin(COMPARER) \ if ((LVALUE) != (RVALUE)) begin \ void'(COMPARER.compare_string(NAME , LVALUE, RVALUE)); \ end \ `m_uvm_compare_threshold_end `define uvm_compare_sarray_int(LVALUE, RVALUE, RADIX, COMPARER=comparer) \ `uvm_compare_named_sarray_int(`"LVALUE`", LVALUE, RVALUE, RADIX, COMPARER) `define uvm_compare_named_sarray_int(NAME, LVALUE, RVALUE, RADIX, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ foreach (LVALUE[i]) begin \ `uvm_compare_named_int($sformatf("%s[%0d]", NAME, i), \ LVALUE[i], \ RVALUE[i], \ RADIX, \ COMPARER) \ end \ `m_uvm_compare_end `define uvm_compare_qda_int(LVALUE, RVALUE, RADIX, COMPARER=comparer) \ `uvm_compare_named_qda_int(`"LVALUE`", LVALUE, RVALUE, RADIX, COMPARER) `define uvm_compare_named_qda_int(NAME, LVALUE, RVALUE, RADIX, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ `uvm_compare_named_int($sformatf("%s.size()", NAME), \ LVALUE.size(), \ RVALUE.size(), \ UVM_DEC, \ COMPARER) \ `uvm_compare_named_sarray_int(NAME, LVALUE, RVALUE, RADIX, COMPARER) \ `m_uvm_compare_end `define uvm_compare_sarray_real(LVALUE, RVALUE, COMPARER=comparer) \ `uvm_compare_named_sarray_real(`"LVALUE`", LVALUE, RVALUE,COMPARER) `define uvm_compare_named_sarray_real(NAME, LVALUE, RVALUE, COMPARER=comparer) \ `m_uvm_compare_threshold_begin(COMPARER) \ if ((LVALUE) != (RVALUE)) begin \ foreach (LVALUE[i]) begin \ `uvm_compare_named_real($sformatf("%s[%0d]", NAME, i), \ LVALUE[i], \ RVALUE[i], \ COMPARER) \ end \ end \ `m_uvm_compare_threshold_end `define uvm_compare_qda_real(LVALUE, RVALUE, COMPARER=comparer) \ `uvm_compare_named_qda_real(`"LVALUE`", LVALUE, RVALUE, COMPARER) `define uvm_compare_named_qda_real(NAME, LVALUE, RVALUE, COMPARER=comparer) \ `m_uvm_compare_threshold_begin(COMPARER) \ `uvm_compare_named_real($sformatf("%s.size()", NAME), \ LVALUE.size(), \ RVALUE.size(), \ COMPARER) \ `uvm_compare_named_sarray_real(NAME, LVALUE, RVALUE, COMPARER) \ `m_uvm_compare_threshold_end `define uvm_compare_sarray_enum(LVALUE, RVALUE, TYPE, COMPARER=comparer) \ `uvm_compare_named_sarray_enum(`"LVALUE`", LVALUE, RVALUE, TYPE, COMPARER) `define uvm_compare_named_sarray_enum(NAME, LVALUE, RVALUE, TYPE, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ foreach (LVALUE[i]) begin \ `uvm_compare_named_enum($sformatf("%s[%0d]", NAME, i), \ LVALUE[i], \ RVALUE[i], \ TYPE, \ COMPARER) \ end \ `m_uvm_compare_end `define uvm_compare_qda_enum(LVALUE, RVALUE, TYPE, COMPARER=comparer) \ `uvm_compare_named_qda_enum(`"LVALUE`", LVALUE, RVALUE, TYPE, COMPARER) `define uvm_compare_named_qda_enum(NAME, LVALUE, RVALUE, TYPE, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ `uvm_compare_named_int($sformatf("%s.size()", NAME), \ LVALUE.size(), \ RVALUE.size(), \ UVM_DEC, \ COMPARER) \ `uvm_compare_named_sarray_enum(NAME, LVALUE, RVALUE, TYPE, COMPARER) \ `m_uvm_compare_end `define uvm_compare_sarray_object(LVALUE, RVALUE, POLICY=UVM_DEFAULT_POLICY, COMPARER=comparer) \ `uvm_compare_named_sarray_object(`"LVALUE`", LVALUE, RVALUE, POLICY, COMPARER) `define uvm_compare_named_sarray_object(NAME, LVALUE, RVALUE, POLICY=UVM_DEFAULT_POLICY, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ uvm_recursion_policy_enum prev_rec__; \ prev_rec__ = COMPARER.get_recursion_policy(); \ if (POLICY != UVM_DEFAULT_POLICY) \ COMPARER.set_recursion_policy(POLICY); \ foreach (LVALUE[i]) begin \ `m_uvm_compare_named_object($sformatf("%s[%0d]", NAME, i), \ LVALUE[i], \ RVALUE[i], \ COMPARER) \ end \ if (POLICY != UVM_DEFAULT_POLICY) \ COMPARER.set_recursion_policy(prev_rec__); \ `m_uvm_compare_end `define uvm_compare_qda_object(LVALUE, RVALUE, POLICY=UVM_DEFAULT_POLICY, COMPARER=comparer) \ `uvm_compare_named_qda_object(`"LVALUE`", LVALUE, RVALUE, POLICY, COMPARER) `define uvm_compare_named_qda_object(NAME, LVALUE, RVALUE, POLICY=UVM_DEFAULT_POLICY, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ `uvm_compare_named_int($sformatf("%s.size()", NAME), \ LVALUE.size(), \ RVALUE.size(), \ UVM_DEC, \ COMPARER) \ `uvm_compare_named_sarray_object(NAME, LVALUE, RVALUE, POLICY, COMPARER) \ `m_uvm_compare_end `define uvm_compare_sarray_string(LVALUE, RVALUE, COMPARER=comparer) \ `uvm_compare_named_sarray_string(`"LVALUE`", LVALUE, RVALUE, COMPARER) `define uvm_compare_named_sarray_string(NAME, LVALUE, RVALUE, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ foreach (LVALUE[i]) begin \ `uvm_compare_named_string($sformatf("%s[%0d]", NAME, i), \ LVALUE[i], \ RVALUE[i], \ COMPARER) \ end \ `m_uvm_compare_end `define uvm_compare_qda_string(LVALUE, RVALUE, COMPARER=comparer) \ `uvm_compare_named_qda_string(`"LVALUE`", LVALUE, RVALUE, COMPARER) `define uvm_compare_named_qda_string(NAME, LVALUE, RVALUE, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ `uvm_compare_named_int($sformatf("%s.size()", NAME), \ LVALUE.size(), \ RVALUE.size(), \ UVM_DEC, \ COMPARER) \ `uvm_compare_named_sarray_string(NAME, LVALUE, RVALUE, COMPARER) \ `m_uvm_compare_end `define uvm_compare_aa_int_string(LVALUE, RVALUE, RADIX, COMPARER=comparer) \ `uvm_compare_named_aa_int_string(`"LVALUE`", LVALUE, RVALUE, RADIX, COMPARER) `define uvm_compare_named_aa_int_string(NAME, LVALUE, RVALUE, RADIX, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ foreach(LVALUE[i]) begin \ if (!RVALUE.exists(i)) begin \ COMPARER.print_msg($sformatf("%s: Key '%s' not in RHS", NAME, i)); \ end \ else begin \ `uvm_compare_named_int($sformatf("%s[%s]", NAME, i), \ LVALUE[i], \ RVALUE[i], \ RADIX, \ COMPARER) \ end \ end \ foreach(RVALUE[i]) begin \ if(!LVALUE.exists(i)) begin \ COMPARER.print_msg($sformatf("%s: Key '%s' not in LHS", NAME, i)); \ end \ end \ `m_uvm_compare_end `define uvm_compare_aa_object_string(LVALUE, RVALUE, POLICY=UVM_DEFAULT_POLICY, COMPARER=comparer) \ `uvm_compare_named_aa_object_string(`"LVALUE`", LVALUE, RVALUE, POLICY, COMPARER) `define uvm_compare_named_aa_object_string(NAME, LVALUE, RVALUE, POLICY=UVM_DEFAULT_POLICY, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ uvm_recursion_policy_enum prev_rec__; \ prev_rec__ = COMPARER.get_recursion_policy(); \ if (POLICY != UVM_DEFAULT_POLICY) \ COMPARER.set_recursion_policy(POLICY); \ foreach(LVALUE[i]) begin \ if (!RVALUE.exists(i)) begin \ COMPARER.print_msg($sformatf("%s: Key '%s' not in RHS", NAME, i)); \ end \ else begin \ `m_uvm_compare_named_object($sformatf("%s[%s]", NAME, i), \ LVALUE[i], \ RVALUE[i], \ COMPARER) \ end \ end \ foreach(RVALUE[i]) begin \ if(!LVALUE.exists(i)) begin \ COMPARER.print_msg($sformatf("%s: Key '%s' not in LHS", NAME, i)); \ end \ end \ if (POLICY != UVM_DEFAULT_POLICY) \ COMPARER.set_recursion_policy(prev_rec__); \ `m_uvm_compare_end `define uvm_compare_aa_string_string(LVALUE, RVALUE, COMPARER=comparer) \ `uvm_compare_named_aa_string_string(`"LVALUE`", LVALUE, RVALUE, COMPARER) `define uvm_compare_named_aa_string_string(NAME, LVALUE, RVALUE, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ foreach(LVALUE[i]) begin \ if (!RVALUE.exists(i)) begin \ COMPARER.print_msg($sformatf("%s: Key '%s' not in RHS", NAME, i)); \ end \ else begin \ `uvm_compare_named_string($sformatf("%s[%s]", NAME, i), \ LVALUE[i], \ RVALUE[i], \ COMPARER) \ end \ end \ foreach(RVALUE[i]) begin \ if(!LVALUE.exists(i)) begin \ COMPARER.print_msg($sformatf("%s: Key '%s' not in LHS", NAME, i)); \ end \ end \ `m_uvm_compare_end `define uvm_compare_aa_int_int(LVALUE, RVALUE, RADIX, COMPARER=comparer) \ `uvm_compare_named_aa_int_int(`"LVALUE`", LVALUE, RVALUE, RADIX, COMPARER) `define uvm_compare_named_aa_int_int(NAME, LVALUE, RVALUE, RADIX, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ foreach(LVALUE[i]) begin \ if (!RVALUE.exists(i)) begin \ COMPARER.print_msg($sformatf("%s: Key '%0d' not in RHS", NAME, i)); \ end \ else begin \ `uvm_compare_named_int($sformatf("%s[%d]", NAME, i), \ LVALUE[i], \ RVALUE[i], \ RADIX, \ COMPARER) \ end \ end \ foreach(RVALUE[i]) begin \ if(!LVALUE.exists(i)) begin \ COMPARER.print_msg($sformatf("%s: Key '%0d' not in LHS", NAME, i)); \ end \ end \ `m_uvm_compare_end `define uvm_compare_aa_object_int(LVALUE, RVALUE, POLICY=UVM_DEFAULT_POLICY, COMPARER=comparer) \ `uvm_compare_named_aa_object_int(`"LVALUE`", LVALUE, RVALUE, POLICY, COMPARER) `define uvm_compare_named_aa_object_int(NAME, LVALUE, RVALUE, POLICY=UVM_DEFAULT_POLICY, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ uvm_recursion_policy_enum prev_rec__; \ prev_rec__ = COMPARER.get_recursion_policy(); \ if (POLICY != UVM_DEFAULT_POLICY) \ COMPARER.set_recursion_policy(POLICY); \ foreach(LVALUE[i]) begin \ if (!RVALUE.exists(i)) begin \ COMPARER.print_msg($sformatf("%s: Key '%0d' not in RHS", NAME, i)); \ end \ else begin \ `m_uvm_compare_named_object($sformatf("%s[%s]", NAME, i), \ LVALUE[i], \ RVALUE[i], \ COMPARER) \ end \ end \ foreach(RVALUE[i]) begin \ if(!LVALUE.exists(i)) begin \ COMPARER.print_msg($sformatf("%s: Key '%0d' not in LHS", NAME, i)); \ end \ end \ if (POLICY != UVM_DEFAULT_POLICY) \ COMPARER.set_recursion_policy(prev_rec__); \ `m_uvm_compare_end `define uvm_compare_aa_string_int(LVALUE, RVALUE, COMPARER=comparer) \ `uvm_compare_named_aa_string_int(`"LVALUE`", LVALUE, RVALUE, COMPARER) `define uvm_compare_named_aa_string_int(NAME, LVALUE, RVALUE, COMPARER=comparer) \ `m_uvm_compare_begin(LVALUE, RVALUE, COMPARER) \ foreach(LVALUE[i]) begin \ if (!RVALUE.exists(i)) begin \ COMPARER.print_msg($sformatf("%s: Key '%d' not in RHS", NAME, i)); \ end \ else begin \ `uvm_compare_named_string($sformatf("%s[%d]", NAME, i), \ LVALUE[i], \ RVALUE[i], \ COMPARER) \ end \ end \ foreach(RVALUE[i]) begin \ if(!LVALUE.exists(i)) begin \ COMPARER.print_msg($sformatf("%s: Key '%d' not in LHS", NAME, i)); \ end \ end \ `m_uvm_compare_end `define UVM_RECORDER_DEFINES_SVH `define uvm_record_attribute(TR_HANDLE,NAME,VALUE,RECORDER=recorder) \ RECORDER.record_generic(NAME, $sformatf("%p", VALUE)); `define uvm_record_int(NAME,VALUE,SIZE,RADIX = UVM_NORADIX,RECORDER=recorder) \ if (RECORDER != null && RECORDER.is_open()) begin \ if (RECORDER.use_record_attribute()) \ `uvm_record_attribute(RECORDER.get_record_attribute_handle(),NAME,VALUE,RECORDER) \ else \ if (SIZE > 64) \ RECORDER.record_field(NAME, VALUE, SIZE, RADIX); \ else \ RECORDER.record_field_int(NAME, VALUE, SIZE, RADIX); \ end `define uvm_record_string(NAME,VALUE,RECORDER=recorder) \ if (RECORDER != null && RECORDER.is_open()) begin \ if (RECORDER.use_record_attribute()) \ `uvm_record_attribute(RECORDER.get_record_attribute_handle(),NAME,VALUE,RECORDER) \ else \ RECORDER.record_string(NAME,VALUE); \ end `define uvm_record_time(NAME,VALUE,RECORDER=recorder) \ if (RECORDER != null && RECORDER.is_open()) begin \ if (RECORDER.use_record_attribute()) \ `uvm_record_attribute(RECORDER.get_record_attribute_handle(),NAME,VALUE,RECORDER) \ else \ RECORDER.record_time(NAME,VALUE); \ end `define uvm_record_real(NAME,VALUE,RECORDER=recorder) \ if (RECORDER != null && RECORDER.is_open()) begin \ if (RECORDER.use_record_attribute()) \ `uvm_record_attribute(RECORDER.get_record_attribute_handle(),NAME,VALUE,RECORDER) \ else \ RECORDER.record_field_real(NAME,VALUE); \ end `define uvm_record_field(NAME,VALUE,RECORDER=recorder) \ if (RECORDER != null && RECORDER.is_open()) begin \ if (RECORDER.use_record_attribute()) begin \ `uvm_record_attribute(RECORDER.get_record_attribute_handle(),NAME,VALUE,RECORDER) \ end \ else \ RECORDER.record_generic(NAME, $sformatf("%p", VALUE)); \ end `define uvm_record_enum(NAME,VALUE,TYPE,RECORDER=recorder) \ if (RECORDER != null && RECORDER.is_open()) begin \ if (RECORDER.use_record_attribute()) begin \ `uvm_record_attribute(RECORDER.get_record_attribute_handle(),NAME,VALUE,RECORDER) \ end \ else begin \ if (VALUE.name() == "") \ RECORDER.record_generic(NAME, $sformatf("%0d", VALUE), `"TYPE`"); \ else \ RECORDER.record_generic(NAME, VALUE.name(), `"TYPE`"); \ end \ end `define uvm_record_qda_int(ARG, RADIX,RECORDER=recorder) \ begin \ int sz__ = $size(ARG); \ if(sz__ == 0) begin \ `uvm_record_int(`"ARG`", 0, 32, UVM_DEC,RECORDER) \ end \ else if(sz__ < 10) begin \ foreach(ARG[i]) begin \ string nm__ = $sformatf("%s[%0d]", `"ARG`", i); \ `uvm_record_int(nm__, ARG[i], $bits(ARG[i]), RADIX, RECORDER) \ end \ end \ else begin \ for(int i=0; i<5; ++i) begin \ string nm__ = $sformatf("%s[%0d]", `"ARG`", i); \ `uvm_record_int(nm__, ARG[i], $bits(ARG[i]), RADIX, RECORDER) \ end \ for(int i=sz__-5; i sz__) \ void'(VAR.pop_back()); \ for (int i=0; i tmp_size__) \ void'(VAR.pop_back()); \ for (int i = 0; i < tmp_size__; i++) \ `uvm_unpack_real(VAR[i], PACKER) \ end `define UVM_COPIER_DEFINES_SVH `define uvm_copy_object(LVALUE, RVALUE, POLICY=UVM_DEFAULT_POLICY, COPIER=copier) \ if (LVALUE != RVALUE) begin \ if ((RVALUE == null) || \ (POLICY == UVM_REFERENCE) || \ ((POLICY == UVM_DEFAULT_POLICY) && \ (COPIER.get_recursion_policy() == UVM_REFERENCE))) begin \ LVALUE = RVALUE; \ end \ else begin \ uvm_object lvalue_ref__; \ if (!COPIER.get_first_copy(RVALUE,lvalue_ref__) || !$cast(LVALUE,lvalue_ref__)) begin \ uvm_recursion_policy_enum prev_pol__ = COPIER.get_recursion_policy(); \ uvm_recursion_policy_enum curr_pol__; \ if (POLICY != UVM_DEFAULT_POLICY) \ COPIER.set_recursion_policy(POLICY); \ curr_pol__ = COPIER.get_recursion_policy(); \ if (LVALUE == null) begin \ if (($cast(LVALUE, RVALUE.create(RVALUE.get_name())) == 0) || \ (LVALUE == null)) begin \ `uvm_fatal("UVM/COPY/NULL_CREATE", \ {"Could not create '", RVALUE.get_full_name(), \ "' of type '", RVALUE.get_type_name(), \ "', into '", `"LVALUE`", "'."}) \ end \ else begin \ COPIER.copy_object(LVALUE, RVALUE); \ end \ end \ else begin \ if (COPIER.object_copied(LVALUE, RVALUE, curr_pol__) == uvm_policy::STARTED) begin \ `uvm_warning("UVM/COPY/LOOP", \ {"Loop detected in copy operation (LHS:'", \ LVALUE.get_full_name(), \ "', RHS:'", \ RVALUE.get_full_name(), \ "')"}) \ end \ else begin \ COPIER.copy_object(LVALUE, RVALUE); \ end \ end \ if (POLICY != UVM_DEFAULT_POLICY) \ COPIER.set_recursion_policy(prev_pol__); \ end \ end \ end `define uvm_copy_aa_object(LVALUE, RVALUE, POLICY=UVM_DEFAULT_POLICY, COPIER=copier) \ if ((POLICY == UVM_REFERENCE) || !RVALUE.size()) \ LVALUE = RVALUE; \ else begin \ LVALUE.delete(); \ foreach(RVALUE[i]) \ `uvm_copy_object(LVALUE[i], RVALUE[i], POLICY, COPIER) \ end `define uvm_copier_get_function(FUNCTION) \ function int get_``FUNCTION``_copy(uvm_object rhs, ref uvm_object lhs); \ if (m_recur_states.exists(rhs)) \ return m_recur_states[rhs].FUNCTION(lhs); \ return 0; \ endfunction : get_``FUNCTION``_copy `define UVM_OBJECT_DEFINES_SVH `define UVM_FIELD_FLAG_SIZE UVM_FIELD_FLAG_RESERVED_BITS `define uvm_field_utils_begin(T) \ function void do_execute_op( uvm_field_op op ); \ super.do_execute_op(op); \ __m_uvm_execute_field_op(op); \ endfunction : do_execute_op \ local function void __m_uvm_execute_field_op( uvm_field_op __local_op__ ); \ uvm_field_flag_t local_op_type__; /* Used to avoid re-querying */ \ T local_rhs__; /* Used for $casting copy and compare */ \ uvm_resource_base local_rsrc__; /* Used for UVM_SET ops */ \ string local_rsrc_name__; \ uvm_object local_obj__; /* Used when trying to read uvm_object resources */ \ bit local_success__; /* Used when trying to read resources */ \ typedef T __local_type__; /* Used for referring to type T in field macros */ \ int local_size__; /* Used when unpacking size values */ \ /* All possible policy classes */ \ /* Using the same name as the do_* methods, allows macro reuse */ \ uvm_printer __local_printer__; \ uvm_comparer __local_comparer__; \ uvm_recorder __local_recorder__; \ uvm_packer __local_packer__; \ uvm_copier __local_copier__; \ void'($cast(local_rhs__, __local_op__.get_rhs())); \ if (($cast(local_rsrc__, __local_op__.get_rhs())) && \ (local_rsrc__ != null)) \ local_rsrc_name__ = local_rsrc__.get_name(); \ local_op_type__ = __local_op__.get_op_type(); \ case (local_op_type__) \ UVM_PRINT: begin \ $cast(__local_printer__, __local_op__.get_policy()); \ end \ UVM_COMPARE: begin \ if (local_rhs__ == null) return; \ $cast(__local_comparer__, __local_op__.get_policy()); \ end \ UVM_RECORD: begin \ $cast(__local_recorder__, __local_op__.get_policy()); \ end \ UVM_PACK, UVM_UNPACK: begin \ $cast(__local_packer__, __local_op__.get_policy()); \ end \ UVM_COPY: begin \ if (local_rhs__ == null) return; \ $cast(__local_copier__, __local_op__.get_policy()); \ end \ UVM_SET: begin \ if (local_rsrc__ == null) return; \ end \ default: \ return; /* unknown op, just return */ \ endcase \ `define uvm_field_utils_end \ endfunction : __m_uvm_execute_field_op `define uvm_object_utils(T) \ `m_uvm_object_registry_internal(T,T) \ `m_uvm_object_create_func(T) \ `uvm_type_name_decl(`"T`") `define uvm_object_param_utils(T) \ `m_uvm_object_registry_param(T) \ `m_uvm_object_create_func(T) `define uvm_object_utils_begin(T) \ `uvm_object_utils(T) \ `uvm_field_utils_begin(T) `define uvm_object_param_utils_begin(T) \ `uvm_object_param_utils(T) \ `uvm_field_utils_begin(T) `define uvm_object_abstract_utils(T) \ `m_uvm_object_abstract_registry_internal(T,T) \ `uvm_type_name_decl(`"T`") `define uvm_object_abstract_param_utils(T) \ `m_uvm_object_abstract_registry_param(T) `define uvm_object_abstract_utils_begin(T) \ `uvm_object_abstract_utils(T) \ `uvm_field_utils_begin(T) `define uvm_object_abstract_param_utils_begin(T) \ `uvm_object_abstract_param_utils(T) \ `uvm_field_utils_begin(T) `define uvm_object_utils_end \ `uvm_field_utils_end `define uvm_component_utils(T) \ `m_uvm_component_registry_internal(T,T) \ `uvm_type_name_decl(`"T`") \ `define uvm_component_param_utils(T) \ `m_uvm_component_registry_param(T) \ `define uvm_component_utils_begin(T) \ `uvm_component_utils(T) \ `uvm_field_utils_begin(T) `define uvm_component_param_utils_begin(T) \ `uvm_component_param_utils(T) \ `uvm_field_utils_begin(T) `define uvm_component_abstract_utils(T) \ `m_uvm_component_abstract_registry_internal(T,T) \ `uvm_type_name_decl(`"T`") \ `define uvm_component_abstract_param_utils(T) \ `m_uvm_component_abstract_registry_param(T) \ `define uvm_component_abstract_utils_begin(T) \ `uvm_component_abstract_utils(T) \ `uvm_field_utils_begin(T) `define uvm_component_abstract_param_utils_begin(T) \ `uvm_component_abstract_param_utils(T) \ `uvm_field_utils_begin(T) `define uvm_component_utils_end \ `uvm_field_utils_end `define uvm_object_registry(T,S) \ typedef uvm_object_registry#(T,S) type_id; \ static function type_id get_type(); \ return type_id::get(); \ endfunction \ virtual function uvm_object_wrapper get_object_type(); \ return type_id::get(); \ endfunction `define uvm_component_registry(T,S) \ typedef uvm_component_registry #(T,S) type_id; \ static function type_id get_type(); \ return type_id::get(); \ endfunction \ virtual function uvm_object_wrapper get_object_type(); \ return type_id::get(); \ endfunction `define uvm_declare_type_alias(TYPE,NAME,SFX=) \ static bit m__alias_declared``SFX = TYPE::type_id::set_type_alias(NAME); `define uvm_new_func \ function new (string name, uvm_component parent); \ super.new(name, parent); \ endfunction `define m_uvm_object_create_func(T) \ function uvm_object create (string name=""); \ T tmp; \ if (name=="") tmp = new(); \ else tmp = new(name); \ return tmp; \ endfunction `define uvm_type_name_decl(TNAME_STRING) \ static function string type_name(); \ return TNAME_STRING; \ endfunction : type_name \ virtual function string get_type_name(); \ return TNAME_STRING; \ endfunction : get_type_name `define m_uvm_object_registry_internal(T,S) \ typedef uvm_object_registry#(T,`"S`") type_id; \ static function type_id get_type(); \ return type_id::get(); \ endfunction \ virtual function uvm_object_wrapper get_object_type(); \ return type_id::get(); \ endfunction `define m_uvm_object_registry_param(T) \ typedef uvm_object_registry #(T) type_id; \ static function type_id get_type(); \ return type_id::get(); \ endfunction \ virtual function uvm_object_wrapper get_object_type(); \ return type_id::get(); \ endfunction `define m_uvm_object_abstract_registry_internal(T,S) \ typedef uvm_abstract_object_registry#(T,`"S`") type_id; \ static function type_id get_type(); \ return type_id::get(); \ endfunction \ virtual function uvm_object_wrapper get_object_type(); \ return type_id::get(); \ endfunction `define m_uvm_object_abstract_registry_param(T) \ typedef uvm_abstract_object_registry #(T) type_id; \ static function type_id get_type(); \ return type_id::get(); \ endfunction \ virtual function uvm_object_wrapper get_object_type(); \ return type_id::get(); \ endfunction `define m_uvm_component_registry_internal(T,S) \ typedef uvm_component_registry #(T,`"S`") type_id; \ static function type_id get_type(); \ return type_id::get(); \ endfunction \ virtual function uvm_object_wrapper get_object_type(); \ return type_id::get(); \ endfunction `define m_uvm_component_registry_param(T) \ typedef uvm_component_registry #(T) type_id; \ static function type_id get_type(); \ return type_id::get(); \ endfunction \ virtual function uvm_object_wrapper get_object_type(); \ return type_id::get(); \ endfunction `define m_uvm_component_abstract_registry_internal(T,S) \ typedef uvm_abstract_component_registry #(T,`"S`") type_id; \ static function type_id get_type(); \ return type_id::get(); \ endfunction \ virtual function uvm_object_wrapper get_object_type(); \ return type_id::get(); \ endfunction `define m_uvm_component_abstract_registry_param(T) \ typedef uvm_abstract_component_registry #(T) type_id; \ static function type_id get_type(); \ return type_id::get(); \ endfunction \ virtual function uvm_object_wrapper get_object_type(); \ return type_id::get(); \ endfunction `define m_uvm_field_radix(FLAG) uvm_radix_enum'((FLAG)&(UVM_RADIX)) `define m_uvm_field_recursion(FLAG) uvm_recursion_policy_enum'((FLAG)&(UVM_RECURSION)) `define m_uvm_field_begin(ARG, FLAG) \ begin \ case (local_op_type__) `define m_uvm_field_end(ARG) \ endcase \ end `define m_uvm_field_op_begin(OP, FLAG) \ UVM_``OP: \ if (!((FLAG)&UVM_NO``OP)) begin `define m_uvm_field_op_end(OP) \ end `define uvm_field_int(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG,FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_int(ARG, local_rhs__.ARG, `m_uvm_field_radix(FLAG), __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ `uvm_pack_int(ARG, __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ `uvm_unpack_int(ARG, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `uvm_record_int(`"ARG`", \ ARG, \ $bits(ARG), \ `m_uvm_field_radix(FLAG), \ __local_recorder__) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_int(ARG, $bits(ARG), `m_uvm_field_radix(FLAG),,__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_resource_builtin_int_read(local_success__, \ local_rsrc__, \ ARG, \ this) \ /* TODO if(local_success__ && printing matches) */ \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_object(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG,FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ `uvm_copy_object(ARG, local_rhs__.ARG, `m_uvm_field_recursion(FLAG), __local_copier__) \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_object(ARG, local_rhs__.ARG, `m_uvm_field_recursion(FLAG), __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ if (`m_uvm_field_recursion(FLAG) != UVM_REFERENCE) \ `uvm_pack_object(ARG, __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ if (`m_uvm_field_recursion(FLAG) != UVM_REFERENCE) \ `uvm_unpack_object(ARG, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ __local_recorder__.record_object(`"ARG`", ARG); \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_object(ARG, `m_uvm_field_recursion(FLAG),__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_resource_read(local_success__, \ local_rsrc__, \ uvm_object, \ local_obj__, \ this) \ if (local_success__) begin \ if (local_obj__ == null) begin \ ARG = null; \ end else if (!$cast(ARG, local_obj__)) begin \ `uvm_warning("UVM/FIELDS/OBJ_TYPE", $sformatf("Can't set field '%s' on '%s' with '%s' type", \ `"ARG`", \ this.get_full_name(), \ local_obj__.get_type_name())) \ end \ /* TODO if(local_success__ && printing matches) */ \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_string(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG, FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_string(ARG, local_rhs__.ARG, __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ `uvm_pack_string(ARG, __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ `uvm_unpack_string(ARG, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `uvm_record_string(`"ARG`", ARG, __local_recorder__) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ __local_printer__.print_string(`"ARG`", ARG); \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_resource_read(local_success__, \ local_rsrc__, \ string, \ ARG, \ this) \ /* TODO if(local_success__ && printing matches) */ \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_enum(T,ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG, FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_enum(ARG, local_rhs__.ARG, T, __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ `uvm_pack_enum(ARG, __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ `uvm_unpack_enum(ARG, T, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `uvm_record_enum(`"ARG`", ARG, T, __local_recorder__) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ if (`m_uvm_field_radix(FLAG) inside {UVM_NORADIX, UVM_ENUM, UVM_STRING}) \ `uvm_print_enum(T, ARG,__local_printer__) \ else \ `uvm_print_int(ARG, $bits(ARG), `m_uvm_field_radix(FLAG),T,__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_resource_enum_read(local_success__, \ local_rsrc__, \ T, \ ARG, \ this) \ /* TODO if(local_success__ && printing matches) */ \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_real(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG,FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_real(ARG, local_rhs__.ARG, __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ `uvm_pack_real(ARG, __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ `uvm_unpack_real(ARG, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `uvm_record_real(`"ARG`", ARG, __local_recorder__) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ __local_printer__.print_real(`"ARG`", ARG); \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_resource_real_read(local_success__, \ local_rsrc__, \ ARG, \ this) \ /* TODO if(local_success__ && printing matches) */ \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_event(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG,FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `m_uvm_compare_begin(ARG, local_rhs__.ARG, __local_comparer__) \ __local_comparer__.print_msg({`"ARG`", " event miscompare"}); \ `m_uvm_compare_end \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ __local_printer__.print_generic(`"ARG`", "event", -1, ""); \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_sarray_int(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG,FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_sarray_int(ARG, local_rhs__.ARG, `m_uvm_field_radix(FLAG), __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ `uvm_pack_sarray(ARG, __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ `uvm_unpack_sarray(ARG, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `uvm_record_qda_int(ARG, `m_uvm_field_radix(FLAG), __local_recorder__) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_sarray_int(ARG, \ `m_uvm_field_radix(FLAG),, \ __local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_warning("UVM/FIELDS/SARRAY_SIZE", $sformatf("Static array '%s.%s' cannot be resized via configuration.", get_full_name(), `"ARG`") ) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ int local_index__; \ /* TODO: Non-decimal indexes */ \ int local_code__ = $sscanf(local_index_str__, "%d", local_index__); \ if (local_code__ > 0) begin \ if ((local_index__ >= $size(ARG)) || (local_index__ < 0)) begin \ `uvm_warning("UVM/FIELDS/SARRAY_IDX", $sformatf("Index '%d' is not valid for static array '%s.%s' of size '%0d'", \ local_index__, \ get_full_name(), \ `"ARG`", \ $size(ARG))) \ end \ else begin \ `uvm_resource_builtin_int_read(local_success__, \ local_rsrc__, \ ARG[local_index__], \ this) \ end \ end \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_sarray_object(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG, FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ foreach(ARG[i]) begin \ `uvm_copy_object(ARG[i], local_rhs__.ARG[i], `m_uvm_field_recursion(FLAG), __local_copier__) \ end \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_sarray_object(ARG, local_rhs__.ARG, `m_uvm_field_recursion(FLAG), __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ if (`m_uvm_field_recursion(FLAG) != UVM_REFERENCE) \ foreach(ARG[i]) \ `uvm_pack_object(ARG[i], __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ if (`m_uvm_field_recursion(FLAG) != UVM_REFERENCE) \ foreach(ARG[i]) \ `uvm_unpack_object(ARG[i], __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `uvm_record_qda_object(ARG, __local_recorder__) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_sarray_object(ARG, `m_uvm_field_recursion(FLAG), __local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_warning("UVM/FIELDS/SARRAY_SIZE", $sformatf("Static array '%s.%s' cannot be resized via configuration.", get_full_name(), `"ARG`") ) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ int local_index__; \ /* TODO: Non-decimal indexes */ \ int local_code__ = $sscanf(local_index_str__, "%d", local_index__); \ if (local_code__ > 0) begin \ if ((local_index__ >= $size(ARG)) || (local_index__ < 0)) begin \ `uvm_warning("UVM/FIELDS/SARRAY_IDX", $sformatf("Index '%d' is not valid for static array '%s.%s' of size '%0d'", \ local_index__, \ get_full_name(), \ `"ARG`", \ $size(ARG))) \ end \ else begin \ `uvm_resource_read(local_success__, \ local_rsrc__, \ uvm_object, \ local_obj__, \ this) \ if (local_success__) begin \ if (local_obj__ == null) begin \ ARG[local_index__] = null; \ end else if (!$cast(ARG[local_index__], local_obj__)) begin \ `uvm_warning("UVM/FIELDS/OBJ_TYPE", $sformatf("Can't set field '%s[%d]' on '%s' with '%s' type", \ `"ARG`", \ local_index__, \ this.get_full_name(), \ local_obj__.get_type_name())) \ end \ end \ end \ end \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_sarray_string(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG,FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_sarray_string(ARG, local_rhs__.ARG, __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ foreach(ARG[i]) \ `uvm_pack_string(ARG[i], __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ foreach(ARG[i]) \ `uvm_unpack_string(ARG[i], __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `uvm_record_qda_string(ARG, __local_recorder__) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_sarray_string(ARG,__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_warning("UVM/FIELDS/SARRAY_SIZE", $sformatf("Static array '%s.%s' cannot be resized via configuration.", get_full_name(), `"ARG`") ) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ int local_index__; \ /* TODO: Non-decimal indexes */ \ int local_code__ = $sscanf(local_index_str__, "%d", local_index__); \ if (local_code__ > 0) begin \ if ((local_index__ >= $size(ARG)) || (local_index__ < 0)) begin \ `uvm_warning("UVM/FIELDS/SARRAY_IDX", $sformatf("Index '%d' is not valid for static array '%s.%s' of size '%0d'", \ local_index__, \ get_full_name(), \ `"ARG`", \ $size(ARG))) \ end \ else begin \ `uvm_resource_read(local_success__, \ local_rsrc__, \ string, \ ARG[local_index__], \ this) \ end \ end \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_sarray_enum(T,ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG,FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_sarray_enum(ARG, local_rhs__.ARG, T, __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ foreach (ARG[i]) \ `uvm_pack_enumN(ARG[i], $bits(T), __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ foreach (ARG[i]) \ `uvm_unpack_enumN(ARG[i], $bits(T), T, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `uvm_record_qda_enum(ARG, T, __local_recorder__) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_sarray_enum(T, ARG ,__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_warning("UVM/FIELDS/SARRAY_SIZE", $sformatf("Static array '%s.%s' cannot be resized via configuration.", get_full_name(), `"ARG`") ) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ int local_index__; \ /* TODO: Non-decimal indexes */ \ int local_code__ = $sscanf(local_index_str__, "%d", local_index__); \ if (local_code__ > 0) begin \ if ((local_index__ >= $size(ARG)) || (local_index__ < 0)) begin \ `uvm_warning("UVM/FIELDS/SARRAY_IDX", $sformatf("Index '%d' is not valid for static array '%s.%s' of size '%0d'", \ local_index__, \ get_full_name(), \ `"ARG`", \ $size(ARG))) \ end \ else begin \ `uvm_resource_enum_read(local_success__, \ local_rsrc__, \ T, \ ARG[local_index__], \ this) \ end \ end \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define m_uvm_queue_resize(ARG, SZ) \ if (ARG.size() > SZ) \ ARG = ARG[0:SZ-1]; \ else \ while (ARG.size() < SZ) ARG.push_back(ARG[SZ]); `define m_uvm_da_resize(ARG, SZ) \ if (ARG.size() != SZ) ARG = new[SZ](ARG); `define m_uvm_field_qda_int(TYPE,ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG,FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_qda_int(ARG, local_rhs__.ARG, `m_uvm_field_radix(FLAG), __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ `uvm_pack_``TYPE``(ARG, __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ `uvm_unpack_``TYPE``(ARG, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `uvm_record_qda_int(ARG, `m_uvm_field_radix(FLAG), __local_recorder__) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_qda_int(TYPE, ARG, `m_uvm_field_radix(FLAG),,__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_resource_builtin_int_read(local_success__, \ local_rsrc__, \ local_size__, \ this) \ if (local_success__) \ `m_uvm_``TYPE``_resize(ARG, local_size__) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ int local_index__; \ /* TODO: Non-decimal indexes */ \ int local_code__ = $sscanf(local_index_str__, "%d", local_index__); \ if (local_code__ > 0) begin \ if (local_index__ < 0) begin \ `uvm_warning("UVM/FIELDS/QDA_IDX", $sformatf("Index '%0d' is not valid for field '%s.%s' of size '%0d'", \ local_index__, \ get_full_name(), \ `"ARG`", \ ARG.size() ) ) \ end \ else begin \ bit tmp_stream__[]; \ `uvm_resource_builtin_int_read(local_success__, \ local_rsrc__, \ { << bit { tmp_stream__ }}, \ this) \ if (local_success__) begin \ if (local_index__ >= ARG.size()) \ `m_uvm_``TYPE``_resize(ARG, local_index__ + 1) \ tmp_stream__ = new[$bits(ARG[local_index__])] (tmp_stream__); \ ARG[local_index__] = { << bit { tmp_stream__ }}; \ end \ end \ end \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_array_int(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_qda_int(da,ARG,FLAG) `define m_uvm_field_qda_object(TYPE,ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG,FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ if ((`m_uvm_field_recursion(FLAG) == UVM_REFERENCE) || !local_rhs__.ARG.size()) \ ARG = local_rhs__.ARG; \ else begin \ `m_uvm_``TYPE``_resize(ARG, local_rhs__.ARG.size()) \ foreach (ARG[i]) \ `uvm_copy_object(ARG[i], local_rhs__.ARG[i], `m_uvm_field_recursion(FLAG), __local_copier__) \ end \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_qda_object(ARG, local_rhs__.ARG, `m_uvm_field_recursion(FLAG), __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ __local_packer__.pack_field_int(ARG.size(), 32); \ foreach (ARG[i]) \ `uvm_pack_object(ARG[i], __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ local_size__ = __local_packer__.unpack_field_int(32); \ `m_uvm_``TYPE``_resize(ARG, local_size__); \ foreach (ARG[i]) \ `uvm_unpack_object(ARG[i], __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `uvm_record_qda_object(ARG, __local_recorder__) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_qda_object(TYPE, ARG, `m_uvm_field_recursion(FLAG),__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_resource_builtin_int_read(local_success__, \ local_rsrc__, \ local_size__, \ this) \ if (local_success__) \ `m_uvm_``TYPE``_resize(ARG, local_size__) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ int local_index__; \ /* TODO: Non-decimal indexes */ \ int local_code__ = $sscanf(local_index_str__, "%d", local_index__); \ if (local_code__ > 0) begin \ if (local_index__ < 0) begin \ `uvm_warning("UVM/FIELDS/QDA_IDX", $sformatf("Index '%0d' is not valid for field '%s.%s' of size '%0d'", \ local_index__, \ get_full_name(), \ `"ARG`", \ ARG.size() ) ) \ end \ else begin \ `uvm_resource_read(local_success__, \ local_rsrc__, \ uvm_object, \ local_obj__, \ this) \ if (local_success__) begin \ if (local_index__ >= ARG.size()) \ `m_uvm_``TYPE``_resize(ARG, local_index__ + 1) \ if (local_obj__ == null) begin \ ARG[local_index__] = null; \ end else if (!$cast(ARG[local_index__], local_obj__)) begin \ `uvm_error("UVM/FIELDS/QDA_OBJ_TYPE", \ $sformatf("Can't set field '%s[%0d]' on '%s' with '%s' type", \ `"ARG`", \ local_index__, \ this.get_full_name(), \ local_obj__.get_type_name())) \ end \ end \ end \ end \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_array_object(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_qda_object(da,ARG,FLAG) `define uvm_field_array_string(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_qda_string(da,ARG,FLAG) `define m_uvm_field_qda_string(TYPE,ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG,FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_qda_string(ARG, local_rhs__.ARG, __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ __local_packer__.pack_field_int(ARG.size(), 32); \ foreach (ARG[i]) \ `uvm_pack_string(ARG[i], __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ local_size__ = __local_packer__.unpack_field_int(32); \ `m_uvm_``TYPE``_resize(ARG, local_size__) \ foreach (ARG[i]) \ `uvm_unpack_string(ARG[i], __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `uvm_record_qda_string(ARG, __local_recorder__) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_qda_string(TYPE, ARG,__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_resource_builtin_int_read(local_success__, \ local_rsrc__, \ local_size__, \ this) \ if (local_success__) \ `m_uvm_``TYPE``_resize(ARG, local_size__) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ int local_index__; \ /* TODO: Non-decimal indexes */ \ int local_code__ = $sscanf(local_index_str__, "%d", local_index__); \ if (local_code__ > 0) begin \ if (local_index__ < 0) begin \ `uvm_warning("UVM/FIELDS/QDA_IDX", $sformatf("Index '%0d' is not valid for field '%s.%s' of size '%0d'", \ local_index__, \ get_full_name(), \ `"ARG`", \ ARG.size() ) ) \ end \ else begin \ string tmp_string__; \ `uvm_resource_read(local_success__, \ local_rsrc__, \ string, \ tmp_string__, \ this) \ if (local_success__) begin \ if (local_index__ >= ARG.size()) \ `m_uvm_``TYPE``_resize(ARG, local_index__ + 1) \ ARG[local_index__] = tmp_string__; \ end \ end \ end \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_array_enum(T,ARG,FLAG=UVM_DEFAULT) \ `m_field_qda_enum(da,T,ARG,FLAG) `define m_field_qda_enum(TYPE,T,ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG,FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_qda_enum(ARG, local_rhs__.ARG, T, __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ __local_packer__.pack_field_int(ARG.size(), 32); \ foreach (ARG[i]) \ `uvm_pack_enumN(ARG[i], $bits(T), __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ local_size__ = __local_packer__.unpack_field_int(32); \ `m_uvm_``TYPE``_resize(ARG, local_size__) \ foreach (ARG[i]) \ `uvm_unpack_enumN(ARG[i], $bits(T), T, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `uvm_record_qda_enum(ARG, T, __local_recorder__) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_qda_enum(TYPE, T, ARG,__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_resource_builtin_int_read(local_success__, \ local_rsrc__, \ local_size__, \ this) \ if (local_success__) \ `m_uvm_``TYPE``_resize(ARG, local_size__) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ int local_index__; \ /* TODO: Non-decimal indexes */ \ int local_code__ = $sscanf(local_index_str__, "%d", local_index__); \ if (local_code__ > 0) begin \ if (local_index__ < 0) begin \ `uvm_warning("UVM/FIELDS/QDA_IDX", $sformatf("Index '%0d' is not valid for field '%s.%s' of size '%0d'", \ local_index__, \ get_full_name(), \ `"ARG`", \ ARG.size() ) ) \ end \ else begin \ T tmp_enum__; \ `uvm_resource_enum_read(local_success__, \ local_rsrc__, \ T, \ tmp_enum__, \ this) \ if (local_success__) begin \ if (local_index__ >= ARG.size()) \ `m_uvm_``TYPE``_resize(ARG, local_index__ + 1) \ ARG[local_index__] = tmp_enum__; \ end \ end \ end \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_queue_int(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_qda_int(queue,ARG,FLAG) `define uvm_field_queue_object(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_qda_object(queue,ARG,FLAG) `define uvm_field_queue_string(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_qda_string(queue,ARG,FLAG) `define uvm_field_queue_enum(T,ARG,FLAG=UVM_DEFAULT) \ `m_field_qda_enum(queue,T,ARG,FLAG) `define uvm_field_aa_int_string(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG, FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_aa_int_string(ARG, local_rhs__.ARG, `m_uvm_field_radix(FLAG), __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ `uvm_pack_aa_int_string(ARG, __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ `uvm_unpack_aa_int_string(ARG, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_aa_int_string(ARG, `m_uvm_field_radix(FLAG), int, __local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_warning("UVM/FIELDS/AA_SIZE", $sformatf("Associative array '%s.%s' cannot be resized via configuration.", get_full_name(), `"ARG`") ) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ `uvm_resource_builtin_int_read(local_success__, \ local_rsrc__, \ ARG[local_index__], \ this) \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_aa_object_string(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG, FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ `uvm_copy_aa_object(ARG, local_rhs__.ARG, `m_uvm_field_recursion(FLAG), __local_copier__) \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_aa_object_string(ARG, local_rhs__.ARG, `m_uvm_field_recursion(FLAG), __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ if (`m_uvm_field_recursion(FLAG) != UVM_REFERENCE) \ `uvm_pack_aa_object_string(ARG, __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ if (`m_uvm_field_recursion(FLAG) != UVM_REFERENCE) \ `uvm_unpack_aa_object_string(ARG, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_aa_object_string(ARG, `m_uvm_field_recursion(FLAG),__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_warning("UVM/FIELDS/AA_SIZE", $sformatf("Associative array '%s.%s' cannot be resized via configuration.", get_full_name(), `"ARG`") ) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ `uvm_resource_read(local_success__, \ local_rsrc__, \ uvm_object, \ local_obj__, \ this) \ if (local_success__) begin \ if (local_obj__ == null) begin \ ARG[local_index__] = null; \ end else if (!$cast(ARG[local_index__], local_obj__)) begin \ `uvm_warning("UVM/FIELDS/OBJ_TYPE", $sformatf("Can't set field '%s[%s]' on '%s' with '%s' type", \ `"ARG`", \ local_index__, \ this.get_full_name(), \ local_obj__.get_type_name())) \ end \ end \ /* TODO if(local_success__ && printing matches) */ \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_aa_string_string(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG, FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_aa_string_string(ARG, local_rhs__.ARG, __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ `uvm_pack_aa_string_string(ARG, __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ `uvm_unpack_aa_string_string(ARG, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_aa_string_string(ARG,__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_warning("UVM/FIELDS/AA_SIZE", $sformatf("Associative array '%s.%s' cannot be resized via configuration.", get_full_name(), `"ARG`") ) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ `uvm_resource_read(local_success__, \ local_rsrc__, \ string, \ ARG[local_index__], \ this) \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_aa_object_int(ARG,FLAG=UVM_DEFAULT) \ `uvm_field_aa_object_key(int, ARG, FLAG) `define uvm_field_aa_object_key(KEY, ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG, FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ `uvm_copy_aa_object(ARG, local_rhs__.ARG, `m_uvm_field_recursion(FLAG), __local_copier__) \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_aa_object_int(ARG, local_rhs__.ARG, `m_uvm_field_recursion(FLAG), __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ if (`m_uvm_field_recursion(FLAG) != UVM_REFERENCE) \ `uvm_pack_aa_object_intN(ARG, $bits(KEY), __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ if (`m_uvm_field_recursion(FLAG) != UVM_REFERENCE) \ `uvm_unpack_aa_object_intN(ARG, $bits(KEY), __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_aa_object_int(ARG, `m_uvm_field_recursion(FLAG), KEY,__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_warning("UVM/FIELDS/SARRAY_SIZE", $sformatf("Static array '%s.%s' cannot be resized via configuration.", get_full_name(), `"ARG`") ) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ KEY local_index__; \ /* TODO: Non-decimal indexes */ \ int local_code__ = $sscanf(local_index_str__, "%d", local_index__); \ if (local_code__ > 0) begin \ `uvm_resource_read(local_success__, \ local_rsrc__, \ uvm_object, \ local_obj__, \ this) \ if (local_success__) begin \ if (local_obj__ == null) begin \ ARG[local_index__] = null; \ end else if (!$cast(ARG[local_index__], local_obj__)) begin \ `uvm_warning("UVM/FIELDS/OBJ_TYPE", $sformatf("Can't set field '%s[%d]' on '%s' with '%s' type", \ `"ARG`", \ local_index__, \ this.get_full_name(), \ local_obj__.get_type_name())) \ end \ end \ end \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_aa_string_int(ARG,FLAG=UVM_DEFAULT) \ `uvm_field_aa_string_key(int, ARG, FLAG) `define uvm_field_aa_string_key(KEY, ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG, FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_aa_string_int(ARG, local_rhs__.ARG, __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ `uvm_pack_aa_string_intN(ARG, $bits(KEY), __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ `uvm_unpack_aa_string_intN(ARG, $bits(KEY), __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(PRINT,FLAG) \ /* TODO */ \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_warning("UVM/FIELDS/SARRAY_SIZE", $sformatf("Static array '%s.%s' cannot be resized via configuration.", get_full_name(), `"ARG`") ) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ KEY local_index__; \ /* TODO: Non-decimal indexes */ \ int local_code__ = $sscanf(local_index_str__, "%d", local_index__); \ if (local_code__ > 0) begin \ `uvm_resource_read(local_success__, \ local_rsrc__, \ string, \ ARG[local_index__], \ this) \ end \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_aa_int_int(ARG,FLAG=UVM_DEFAULT) \ `uvm_field_aa_int_key(int, ARG, FLAG) \ `define uvm_field_aa_int_int_unsigned(ARG,FLAG=UVM_DEFAULT) \ `uvm_field_aa_int_key(int unsigned, ARG, FLAG) `define uvm_field_aa_int_integer(ARG,FLAG=UVM_DEFAULT) \ `uvm_field_aa_int_key(integer, ARG, FLAG) `define uvm_field_aa_int_integer_unsigned(ARG,FLAG=UVM_DEFAULT) \ `uvm_field_aa_int_key(integer unsigned, ARG, FLAG) `define uvm_field_aa_int_byte(ARG,FLAG=UVM_DEFAULT) \ `uvm_field_aa_int_key(byte, ARG, FLAG) `define uvm_field_aa_int_byte_unsigned(ARG,FLAG=UVM_DEFAULT) \ `uvm_field_aa_int_key(byte unsigned, ARG, FLAG) `define uvm_field_aa_int_shortint(ARG,FLAG=UVM_DEFAULT) \ `uvm_field_aa_int_key(shortint, ARG, FLAG) `define uvm_field_aa_int_shortint_unsigned(ARG,FLAG=UVM_DEFAULT) \ `uvm_field_aa_int_key(shortint unsigned, ARG, FLAG) `define uvm_field_aa_int_longint(ARG,FLAG=UVM_DEFAULT) \ `uvm_field_aa_int_key(longint, ARG, FLAG) `define uvm_field_aa_int_longint_unsigned(ARG,FLAG=UVM_DEFAULT) \ `uvm_field_aa_int_key(longint unsigned, ARG, FLAG) `define uvm_field_aa_int_key(KEY, ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG, FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_aa_int_int(ARG, local_rhs__.ARG, `m_uvm_field_radix(FLAG), __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ `uvm_pack_aa_int_intN(ARG, $bits(KEY), __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ `uvm_unpack_aa_int_intN(ARG, $bits(KEY), __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_aa_int_int(ARG, `m_uvm_field_radix(FLAG), , KEY,__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_warning("UVM/FIELDS/AA_SIZE", $sformatf("Associative array '%s.%s' cannot be resized via configuration.", get_full_name(), `"ARG`") ) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ KEY local_index__; \ /* TODO: Non-decimal indexes */ \ int local_code__ = $sscanf(local_index_str__, "%d", local_index__); \ if (local_code__ > 0) begin \ `uvm_resource_int_read(local_success__, \ local_rsrc__, \ KEY, \ ARG[local_index__], \ this) \ end \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_aa_int_enumkey(KEY, ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG, FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_aa_int_int(ARG, local_rhs__.ARG, `m_uvm_field_radix(FLAG), __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ `uvm_pack_aa_int_enum(ARG, KEY, __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ `uvm_unpack_aa_int_enum(ARG, KEY, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_aa_int_enum(KEY, ARG, `m_uvm_field_radix(FLAG),,__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_warning("UVM/FIELDS/AA_SIZE", $sformatf("Associative array '%s.%s' cannot be resized via configuration.", get_full_name(), `"ARG`") ) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ KEY local_index__; \ bit[$bits(KEY)-1:0] local_bit_index__; \ /* TODO: Non-decimal indexes */ \ int local_code__ = $sscanf(local_index_str__, "%d", local_bit_index__); \ if (local_code__ > 0) begin \ local_index__ = KEY'(local_bit_index__); \ `uvm_resource_int_read(local_success__, \ local_rsrc__, \ KEY, \ ARG[local_index__], \ this) \ end \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_sarray_real(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG,FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_sarray_real(ARG, local_rhs__.ARG, __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ `uvm_pack_sarray_real(ARG, __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ `uvm_unpack_sarray_real(ARG, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `uvm_record_qda_real(ARG, __local_recorder__) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_sarray_real(ARG,__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_warning("UVM/FIELDS/SARRAY_SIZE", $sformatf("Static array '%s.%s' cannot be resized via configuration.", get_full_name(), `"ARG`") ) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ int local_index__; \ /* TODO: Non-decimal indexes */ \ int local_code__ = $sscanf(local_index_str__, "%d", local_index__); \ if (local_code__ > 0) begin \ if ((local_index__ >= $size(ARG)) || (local_index__ < 0)) begin \ `uvm_warning("UVM/FIELDS/SARRAY_IDX", $sformatf("Index '%d' is not valid for static array '%s.%s' of size '%0d'", \ local_index__, \ get_full_name(), \ `"ARG`", \ $size(ARG))) \ end \ else begin \ `uvm_resource_real_read(local_success__, \ local_rsrc__, \ ARG[local_index__], \ this) \ end \ end \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define m_uvm_field_qda_real(TYPE,ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_begin(ARG,FLAG) \ `m_uvm_field_op_begin(COPY,FLAG) \ ARG = local_rhs__.ARG; \ `m_uvm_field_op_end(COPY) \ `m_uvm_field_op_begin(COMPARE,FLAG) \ `uvm_compare_qda_real(ARG, local_rhs__.ARG, __local_comparer__) \ `m_uvm_field_op_end(COMPARE) \ `m_uvm_field_op_begin(PACK,FLAG) \ `uvm_pack_``TYPE``_real(ARG, __local_packer__) \ `m_uvm_field_op_end(PACK) \ `m_uvm_field_op_begin(UNPACK,FLAG) \ `uvm_unpack_``TYPE``_real(ARG, __local_packer__) \ `m_uvm_field_op_end(UNPACK) \ `m_uvm_field_op_begin(RECORD,FLAG) \ `uvm_record_qda_real(ARG, __local_recorder__) \ `m_uvm_field_op_end(RECORD) \ `m_uvm_field_op_begin(PRINT,FLAG) \ `uvm_print_qda_real(TYPE, ARG,__local_printer__) \ `m_uvm_field_op_end(PRINT) \ `m_uvm_field_op_begin(SET,FLAG) \ if(local_rsrc_name__ == `"ARG`") begin \ `uvm_resource_real_read(local_success__, \ local_rsrc__, \ local_size__, \ this) \ if (local_success__) \ `m_uvm_``TYPE``_resize(ARG, local_size__) \ end \ else begin \ string local_name__ = {`"ARG`", "["}; \ if (local_rsrc_name__.len() && \ local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && \ local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin \ string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), \ local_rsrc_name__.len()-2); \ int local_index__; \ /* TODO: Non-decimal indexes */ \ int local_code__ = $sscanf(local_index_str__, "%d", local_index__); \ if (local_code__ > 0) begin \ if (local_index__ < 0) begin \ `uvm_warning("UVM/FIELDS/QDA_IDX", $sformatf("Index '%0d' is not valid for field '%s.%s' of size '%0d'", \ local_index__, \ get_full_name(), \ `"ARG`", \ ARG.size() ) ) \ end \ else begin \ real tmp_real__; \ `uvm_resource_real_read(local_success__, \ local_rsrc__, \ tmp_real__, \ this) \ if (local_success__) begin \ if (local_index__ >= ARG.size()) \ `m_uvm_``TYPE``_resize(ARG, local_index__ + 1) \ ARG[local_index__] = tmp_real__; \ end \ end \ end \ end \ end \ `m_uvm_field_op_end(SET) \ `m_uvm_field_end(ARG) `define uvm_field_array_real(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_qda_real(da,ARG,FLAG) `define uvm_field_queue_real(ARG,FLAG=UVM_DEFAULT) \ `m_uvm_field_qda_real(queue,ARG,FLAG) `define uvm_blocking_put_imp_decl(SFX) \ class uvm_blocking_put_imp``SFX #(type T=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(T,T)); \ `UVM_IMP_COMMON(`UVM_TLM_BLOCKING_PUT_MASK,`"uvm_blocking_put_imp``SFX`",IMP) \ `UVM_BLOCKING_PUT_IMP_SFX(SFX, m_imp, T, t) \ endclass `define uvm_nonblocking_put_imp_decl(SFX) \ class uvm_nonblocking_put_imp``SFX #(type T=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(T,T)); \ `UVM_IMP_COMMON(`UVM_TLM_NONBLOCKING_PUT_MASK,`"uvm_nonblocking_put_imp``SFX`",IMP) \ `UVM_NONBLOCKING_PUT_IMP_SFX( SFX, m_imp, T, t) \ endclass `define uvm_put_imp_decl(SFX) \ class uvm_put_imp``SFX #(type T=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(T,T)); \ `UVM_IMP_COMMON(`UVM_TLM_PUT_MASK,`"uvm_put_imp``SFX`",IMP) \ `UVM_BLOCKING_PUT_IMP_SFX(SFX, m_imp, T, t) \ `UVM_NONBLOCKING_PUT_IMP_SFX(SFX, m_imp, T, t) \ endclass `define uvm_blocking_get_imp_decl(SFX) \ class uvm_blocking_get_imp``SFX #(type T=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(T,T)); \ `UVM_IMP_COMMON(`UVM_TLM_BLOCKING_GET_MASK,`"uvm_blocking_get_imp``SFX`",IMP) \ `UVM_BLOCKING_GET_IMP_SFX(SFX, m_imp, T, t) \ endclass `define uvm_nonblocking_get_imp_decl(SFX) \ class uvm_nonblocking_get_imp``SFX #(type T=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(T,T)); \ `UVM_IMP_COMMON(`UVM_TLM_NONBLOCKING_GET_MASK,`"uvm_nonblocking_get_imp``SFX`",IMP) \ `UVM_NONBLOCKING_GET_IMP_SFX(SFX, m_imp, T, t) \ endclass `define uvm_get_imp_decl(SFX) \ class uvm_get_imp``SFX #(type T=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(T,T)); \ `UVM_IMP_COMMON(`UVM_TLM_GET_MASK,`"uvm_get_imp``SFX`",IMP) \ `UVM_BLOCKING_GET_IMP_SFX(SFX, m_imp, T, t) \ `UVM_NONBLOCKING_GET_IMP_SFX(SFX, m_imp, T, t) \ endclass `define uvm_blocking_peek_imp_decl(SFX) \ class uvm_blocking_peek_imp``SFX #(type T=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(T,T)); \ `UVM_IMP_COMMON(`UVM_TLM_BLOCKING_PEEK_MASK,`"uvm_blocking_peek_imp``SFX`",IMP) \ `UVM_BLOCKING_PEEK_IMP_SFX(SFX, m_imp, T, t) \ endclass `define uvm_nonblocking_peek_imp_decl(SFX) \ class uvm_nonblocking_peek_imp``SFX #(type T=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(T,T)); \ `UVM_IMP_COMMON(`UVM_TLM_NONBLOCKING_PEEK_MASK,`"uvm_nonblocking_peek_imp``SFX`",IMP) \ `UVM_NONBLOCKING_PEEK_IMP_SFX(SFX, m_imp, T, t) \ endclass `define uvm_peek_imp_decl(SFX) \ class uvm_peek_imp``SFX #(type T=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(T,T)); \ `UVM_IMP_COMMON(`UVM_TLM_PEEK_MASK,`"uvm_peek_imp``SFX`",IMP) \ `UVM_BLOCKING_PEEK_IMP_SFX(SFX, m_imp, T, t) \ `UVM_NONBLOCKING_PEEK_IMP_SFX(SFX, m_imp, T, t) \ endclass `define uvm_blocking_get_peek_imp_decl(SFX) \ class uvm_blocking_get_peek_imp``SFX #(type T=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(T,T)); \ `UVM_IMP_COMMON(`UVM_TLM_BLOCKING_GET_PEEK_MASK,`"uvm_blocking_get_peek_imp``SFX`",IMP) \ `UVM_BLOCKING_GET_IMP_SFX(SFX, m_imp, T, t) \ `UVM_BLOCKING_PEEK_IMP_SFX(SFX, m_imp, T, t) \ endclass `define uvm_nonblocking_get_peek_imp_decl(SFX) \ class uvm_nonblocking_get_peek_imp``SFX #(type T=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(T,T)); \ `UVM_IMP_COMMON(`UVM_TLM_NONBLOCKING_GET_PEEK_MASK,`"uvm_nonblocking_get_peek_imp``SFX`",IMP) \ `UVM_NONBLOCKING_GET_IMP_SFX(SFX, m_imp, T, t) \ `UVM_NONBLOCKING_PEEK_IMP_SFX(SFX, m_imp, T, t) \ endclass `define uvm_get_peek_imp_decl(SFX) \ class uvm_get_peek_imp``SFX #(type T=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(T,T)); \ `UVM_IMP_COMMON(`UVM_TLM_GET_PEEK_MASK,`"uvm_get_peek_imp``SFX`",IMP) \ `UVM_BLOCKING_GET_IMP_SFX(SFX, m_imp, T, t) \ `UVM_NONBLOCKING_GET_IMP_SFX(SFX, m_imp, T, t) \ `UVM_BLOCKING_PEEK_IMP_SFX(SFX, m_imp, T, t) \ `UVM_NONBLOCKING_PEEK_IMP_SFX(SFX, m_imp, T, t) \ endclass `define uvm_blocking_master_imp_decl(SFX) \ class uvm_blocking_master_imp``SFX #(type REQ=int, type RSP=int, type IMP=int, \ type REQ_IMP=IMP, type RSP_IMP=IMP) \ extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); \ typedef IMP this_imp_type; \ typedef REQ_IMP this_req_type; \ typedef RSP_IMP this_rsp_type; \ `UVM_MS_IMP_COMMON(`UVM_TLM_BLOCKING_MASTER_MASK,`"uvm_blocking_master_imp``SFX`") \ \ `UVM_BLOCKING_PUT_IMP_SFX(SFX, m_req_imp, REQ, t) \ \ `UVM_BLOCKING_GET_IMP_SFX(SFX, m_rsp_imp, RSP, t) \ `UVM_BLOCKING_PEEK_IMP_SFX(SFX, m_rsp_imp, RSP, t) \ \ endclass `define uvm_nonblocking_master_imp_decl(SFX) \ class uvm_nonblocking_master_imp``SFX #(type REQ=int, type RSP=int, type IMP=int, \ type REQ_IMP=IMP, type RSP_IMP=IMP) \ extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); \ typedef IMP this_imp_type; \ typedef REQ_IMP this_req_type; \ typedef RSP_IMP this_rsp_type; \ `UVM_MS_IMP_COMMON(`UVM_TLM_NONBLOCKING_MASTER_MASK,`"uvm_nonblocking_master_imp``SFX`") \ \ `UVM_NONBLOCKING_PUT_IMP_SFX(SFX, m_req_imp, REQ, t) \ \ `UVM_NONBLOCKING_GET_IMP_SFX(SFX, m_rsp_imp, RSP, t) \ `UVM_NONBLOCKING_PEEK_IMP_SFX(SFX, m_rsp_imp, RSP, t) \ \ endclass `define uvm_master_imp_decl(SFX) \ class uvm_master_imp``SFX #(type REQ=int, type RSP=int, type IMP=int, \ type REQ_IMP=IMP, type RSP_IMP=IMP) \ extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); \ typedef IMP this_imp_type; \ typedef REQ_IMP this_req_type; \ typedef RSP_IMP this_rsp_type; \ `UVM_MS_IMP_COMMON(`UVM_TLM_MASTER_MASK,`"uvm_master_imp``SFX`") \ \ `UVM_BLOCKING_PUT_IMP_SFX(SFX, m_req_imp, REQ, t) \ `UVM_NONBLOCKING_PUT_IMP_SFX(SFX, m_req_imp, REQ, t) \ \ `UVM_BLOCKING_GET_IMP_SFX(SFX, m_rsp_imp, RSP, t) \ `UVM_BLOCKING_PEEK_IMP_SFX(SFX, m_rsp_imp, RSP, t) \ `UVM_NONBLOCKING_GET_IMP_SFX(SFX, m_rsp_imp, RSP, t) \ `UVM_NONBLOCKING_PEEK_IMP_SFX(SFX, m_rsp_imp, RSP, t) \ \ endclass `define uvm_blocking_slave_imp_decl(SFX) \ class uvm_blocking_slave_imp``SFX #(type REQ=int, type RSP=int, type IMP=int, \ type REQ_IMP=IMP, type RSP_IMP=IMP) \ extends uvm_port_base #(uvm_tlm_if_base #(RSP, REQ)); \ typedef IMP this_imp_type; \ typedef REQ_IMP this_req_type; \ typedef RSP_IMP this_rsp_type; \ `UVM_MS_IMP_COMMON(`UVM_TLM_BLOCKING_SLAVE_MASK,`"uvm_blocking_slave_imp``SFX`") \ \ `UVM_BLOCKING_PUT_IMP_SFX(SFX, m_rsp_imp, RSP, t) \ \ `UVM_BLOCKING_GET_IMP_SFX(SFX, m_req_imp, REQ, t) \ `UVM_BLOCKING_PEEK_IMP_SFX(SFX, m_req_imp, REQ, t) \ \ endclass `define uvm_nonblocking_slave_imp_decl(SFX) \ class uvm_nonblocking_slave_imp``SFX #(type REQ=int, type RSP=int, type IMP=int, \ type REQ_IMP=IMP, type RSP_IMP=IMP) \ extends uvm_port_base #(uvm_tlm_if_base #(RSP, REQ)); \ typedef IMP this_imp_type; \ typedef REQ_IMP this_req_type; \ typedef RSP_IMP this_rsp_type; \ `UVM_MS_IMP_COMMON(`UVM_TLM_NONBLOCKING_SLAVE_MASK,`"uvm_nonblocking_slave_imp``SFX`") \ \ `UVM_NONBLOCKING_PUT_IMP_SFX(SFX, m_rsp_imp, RSP, t) \ \ `UVM_NONBLOCKING_GET_IMP_SFX(SFX, m_req_imp, REQ, t) \ `UVM_NONBLOCKING_PEEK_IMP_SFX(SFX, m_req_imp, REQ, t) \ \ endclass `define uvm_slave_imp_decl(SFX) \ class uvm_slave_imp``SFX #(type REQ=int, type RSP=int, type IMP=int, \ type REQ_IMP=IMP, type RSP_IMP=IMP) \ extends uvm_port_base #(uvm_tlm_if_base #(RSP, REQ)); \ typedef IMP this_imp_type; \ typedef REQ_IMP this_req_type; \ typedef RSP_IMP this_rsp_type; \ `UVM_MS_IMP_COMMON(`UVM_TLM_SLAVE_MASK,`"uvm_slave_imp``SFX`") \ \ `UVM_BLOCKING_PUT_IMP_SFX(SFX, m_rsp_imp, RSP, t) \ `UVM_NONBLOCKING_PUT_IMP_SFX(SFX, m_rsp_imp, RSP, t) \ \ `UVM_BLOCKING_GET_IMP_SFX(SFX, m_req_imp, REQ, t) \ `UVM_BLOCKING_PEEK_IMP_SFX(SFX, m_req_imp, REQ, t) \ `UVM_NONBLOCKING_GET_IMP_SFX(SFX, m_req_imp, REQ, t) \ `UVM_NONBLOCKING_PEEK_IMP_SFX(SFX, m_req_imp, REQ, t) \ \ endclass `define uvm_blocking_transport_imp_decl(SFX) \ class uvm_blocking_transport_imp``SFX #(type REQ=int, type RSP=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); \ `UVM_IMP_COMMON(`UVM_TLM_BLOCKING_TRANSPORT_MASK,`"uvm_blocking_transport_imp``SFX`",IMP) \ `UVM_BLOCKING_TRANSPORT_IMP_SFX(SFX, m_imp, REQ, RSP, req, rsp) \ endclass `define uvm_nonblocking_transport_imp_decl(SFX) \ class uvm_nonblocking_transport_imp``SFX #(type REQ=int, type RSP=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); \ `UVM_IMP_COMMON(`UVM_TLM_NONBLOCKING_TRANSPORT_MASK,`"uvm_nonblocking_transport_imp``SFX`",IMP) \ `UVM_NONBLOCKING_TRANSPORT_IMP_SFX(SFX, m_imp, REQ, RSP, req, rsp) \ endclass `define uvm_non_blocking_transport_imp_decl(SFX) \ `uvm_nonblocking_transport_imp_decl(SFX) `define uvm_transport_imp_decl(SFX) \ class uvm_transport_imp``SFX #(type REQ=int, type RSP=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); \ `UVM_IMP_COMMON(`UVM_TLM_TRANSPORT_MASK,`"uvm_transport_imp``SFX`",IMP) \ `UVM_BLOCKING_TRANSPORT_IMP_SFX(SFX, m_imp, REQ, RSP, req, rsp) \ `UVM_NONBLOCKING_TRANSPORT_IMP_SFX(SFX, m_imp, REQ, RSP, req, rsp) \ endclass `define uvm_analysis_imp_decl(SFX) \ class uvm_analysis_imp``SFX #(type T=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(T,T)); \ `UVM_IMP_COMMON(`UVM_TLM_ANALYSIS_MASK,`"uvm_analysis_imp``SFX`",IMP) \ function void write( input T t); \ m_imp.write``SFX( t); \ endfunction \ \ endclass `define UVM_BLOCKING_PUT_IMP_SFX(SFX, imp, TYPE, arg) \ task put( input TYPE arg); imp.put``SFX( arg); endtask `define UVM_BLOCKING_GET_IMP_SFX(SFX, imp, TYPE, arg) \ task get( output TYPE arg); imp.get``SFX( arg); endtask `define UVM_BLOCKING_PEEK_IMP_SFX(SFX, imp, TYPE, arg) \ task peek( output TYPE arg);imp.peek``SFX( arg); endtask `define UVM_NONBLOCKING_PUT_IMP_SFX(SFX, imp, TYPE, arg) \ function bit try_put( input TYPE arg); \ if( !imp.try_put``SFX( arg)) return 0; \ return 1; \ endfunction \ function bit can_put(); return imp.can_put``SFX(); endfunction `define UVM_NONBLOCKING_GET_IMP_SFX(SFX, imp, TYPE, arg) \ function bit try_get( output TYPE arg); \ if( !imp.try_get``SFX( arg)) return 0; \ return 1; \ endfunction \ function bit can_get(); return imp.can_get``SFX(); endfunction `define UVM_NONBLOCKING_PEEK_IMP_SFX(SFX, imp, TYPE, arg) \ function bit try_peek( output TYPE arg); \ if( !imp.try_peek``SFX( arg)) return 0; \ return 1; \ endfunction \ function bit can_peek(); return imp.can_peek``SFX(); endfunction `define UVM_BLOCKING_TRANSPORT_IMP_SFX(SFX, imp, REQ, RSP, req_arg, rsp_arg) \ task transport( input REQ req_arg, output RSP rsp_arg); \ imp.transport``SFX(req_arg, rsp_arg); \ endtask `define UVM_NONBLOCKING_TRANSPORT_IMP_SFX(SFX, imp, REQ, RSP, req_arg, rsp_arg) \ function bit nb_transport( input REQ req_arg, output RSP rsp_arg); \ if(imp) return imp.nb_transport``SFX(req_arg, rsp_arg); \ endfunction `define UVM_SEQ_ITEM_PULL_IMP(imp, REQ, RSP, req_arg, rsp_arg) \ function void disable_auto_item_recording(); imp.disable_auto_item_recording(); endfunction \ function bit is_auto_item_recording_enabled(); return imp.is_auto_item_recording_enabled(); endfunction \ task get_next_item(output REQ req_arg); imp.get_next_item(req_arg); endtask \ task try_next_item(output REQ req_arg); imp.try_next_item(req_arg); endtask \ function void item_done(input RSP rsp_arg = null); imp.item_done(rsp_arg); endfunction \ task wait_for_sequences(); imp.wait_for_sequences(); endtask \ function bit has_do_available(); return imp.has_do_available(); endfunction \ function void put_response(input RSP rsp_arg); imp.put_response(rsp_arg); endfunction \ task get(output REQ req_arg); imp.get(req_arg); endtask \ task peek(output REQ req_arg); imp.peek(req_arg); endtask \ task put(input RSP rsp_arg); imp.put(rsp_arg); endtask `define UVM_TLM_BLOCKING_PUT_MASK (1<<0) `define UVM_TLM_BLOCKING_GET_MASK (1<<1) `define UVM_TLM_BLOCKING_PEEK_MASK (1<<2) `define UVM_TLM_BLOCKING_TRANSPORT_MASK (1<<3) `define UVM_TLM_NONBLOCKING_PUT_MASK (1<<4) `define UVM_TLM_NONBLOCKING_GET_MASK (1<<5) `define UVM_TLM_NONBLOCKING_PEEK_MASK (1<<6) `define UVM_TLM_NONBLOCKING_TRANSPORT_MASK (1<<7) `define UVM_TLM_ANALYSIS_MASK (1<<8) `define UVM_TLM_MASTER_BIT_MASK (1<<9) `define UVM_TLM_SLAVE_BIT_MASK (1<<10) `define UVM_TLM_PUT_MASK (`UVM_TLM_BLOCKING_PUT_MASK | `UVM_TLM_NONBLOCKING_PUT_MASK) `define UVM_TLM_GET_MASK (`UVM_TLM_BLOCKING_GET_MASK | `UVM_TLM_NONBLOCKING_GET_MASK) `define UVM_TLM_PEEK_MASK (`UVM_TLM_BLOCKING_PEEK_MASK | `UVM_TLM_NONBLOCKING_PEEK_MASK) `define UVM_TLM_BLOCKING_GET_PEEK_MASK (`UVM_TLM_BLOCKING_GET_MASK | `UVM_TLM_BLOCKING_PEEK_MASK) `define UVM_TLM_BLOCKING_MASTER_MASK (`UVM_TLM_BLOCKING_PUT_MASK | `UVM_TLM_BLOCKING_GET_MASK | `UVM_TLM_BLOCKING_PEEK_MASK | `UVM_TLM_MASTER_BIT_MASK) `define UVM_TLM_BLOCKING_SLAVE_MASK (`UVM_TLM_BLOCKING_PUT_MASK | `UVM_TLM_BLOCKING_GET_MASK | `UVM_TLM_BLOCKING_PEEK_MASK | `UVM_TLM_SLAVE_BIT_MASK) `define UVM_TLM_NONBLOCKING_GET_PEEK_MASK (`UVM_TLM_NONBLOCKING_GET_MASK | `UVM_TLM_NONBLOCKING_PEEK_MASK) `define UVM_TLM_NONBLOCKING_MASTER_MASK (`UVM_TLM_NONBLOCKING_PUT_MASK | `UVM_TLM_NONBLOCKING_GET_MASK | `UVM_TLM_NONBLOCKING_PEEK_MASK | `UVM_TLM_MASTER_BIT_MASK) `define UVM_TLM_NONBLOCKING_SLAVE_MASK (`UVM_TLM_NONBLOCKING_PUT_MASK | `UVM_TLM_NONBLOCKING_GET_MASK | `UVM_TLM_NONBLOCKING_PEEK_MASK | `UVM_TLM_SLAVE_BIT_MASK) `define UVM_TLM_GET_PEEK_MASK (`UVM_TLM_GET_MASK | `UVM_TLM_PEEK_MASK) `define UVM_TLM_MASTER_MASK (`UVM_TLM_BLOCKING_MASTER_MASK | `UVM_TLM_NONBLOCKING_MASTER_MASK) `define UVM_TLM_SLAVE_MASK (`UVM_TLM_BLOCKING_SLAVE_MASK | `UVM_TLM_NONBLOCKING_SLAVE_MASK) `define UVM_TLM_TRANSPORT_MASK (`UVM_TLM_BLOCKING_TRANSPORT_MASK | `UVM_TLM_NONBLOCKING_TRANSPORT_MASK) `define UVM_SEQ_ITEM_GET_NEXT_ITEM_MASK (1<<0) `define UVM_SEQ_ITEM_TRY_NEXT_ITEM_MASK (1<<1) `define UVM_SEQ_ITEM_ITEM_DONE_MASK (1<<2) `define UVM_SEQ_ITEM_HAS_DO_AVAILABLE_MASK (1<<3) `define UVM_SEQ_ITEM_WAIT_FOR_SEQUENCES_MASK (1<<4) `define UVM_SEQ_ITEM_PUT_RESPONSE_MASK (1<<5) `define UVM_SEQ_ITEM_PUT_MASK (1<<6) `define UVM_SEQ_ITEM_GET_MASK (1<<7) `define UVM_SEQ_ITEM_PEEK_MASK (1<<8) `define UVM_SEQ_ITEM_PULL_MASK (`UVM_SEQ_ITEM_GET_NEXT_ITEM_MASK | `UVM_SEQ_ITEM_TRY_NEXT_ITEM_MASK | \ `UVM_SEQ_ITEM_ITEM_DONE_MASK | `UVM_SEQ_ITEM_HAS_DO_AVAILABLE_MASK | \ `UVM_SEQ_ITEM_WAIT_FOR_SEQUENCES_MASK | `UVM_SEQ_ITEM_PUT_RESPONSE_MASK | \ `UVM_SEQ_ITEM_PUT_MASK | `UVM_SEQ_ITEM_GET_MASK | `UVM_SEQ_ITEM_PEEK_MASK) `define UVM_SEQ_ITEM_UNI_PULL_MASK (`UVM_SEQ_ITEM_GET_NEXT_ITEM_MASK | `UVM_SEQ_ITEM_TRY_NEXT_ITEM_MASK | \ `UVM_SEQ_ITEM_ITEM_DONE_MASK | `UVM_SEQ_ITEM_HAS_DO_AVAILABLE_MASK | \ `UVM_SEQ_ITEM_WAIT_FOR_SEQUENCES_MASK | `UVM_SEQ_ITEM_GET_MASK | \ `UVM_SEQ_ITEM_PEEK_MASK) `define UVM_SEQ_ITEM_PUSH_MASK (`UVM_SEQ_ITEM_PUT_MASK) `define UVM_TLM_IMPS_SVH `define UVM_BLOCKING_PUT_IMP(imp, TYPE, arg) \ task put (TYPE arg); \ imp.put(arg); \ endtask `define UVM_NONBLOCKING_PUT_IMP(imp, TYPE, arg) \ function bit try_put (TYPE arg); \ return imp.try_put(arg); \ endfunction \ function bit can_put(); \ return imp.can_put(); \ endfunction `define UVM_BLOCKING_GET_IMP(imp, TYPE, arg) \ task get (output TYPE arg); \ imp.get(arg); \ endtask `define UVM_NONBLOCKING_GET_IMP(imp, TYPE, arg) \ function bit try_get (output TYPE arg); \ return imp.try_get(arg); \ endfunction \ function bit can_get(); \ return imp.can_get(); \ endfunction `define UVM_BLOCKING_PEEK_IMP(imp, TYPE, arg) \ task peek (output TYPE arg); \ imp.peek(arg); \ endtask `define UVM_NONBLOCKING_PEEK_IMP(imp, TYPE, arg) \ function bit try_peek (output TYPE arg); \ return imp.try_peek(arg); \ endfunction \ function bit can_peek(); \ return imp.can_peek(); \ endfunction `define UVM_BLOCKING_TRANSPORT_IMP(imp, REQ, RSP, req_arg, rsp_arg) \ task transport (REQ req_arg, output RSP rsp_arg); \ imp.transport(req_arg, rsp_arg); \ endtask `define UVM_NONBLOCKING_TRANSPORT_IMP(imp, REQ, RSP, req_arg, rsp_arg) \ function bit nb_transport (REQ req_arg, output RSP rsp_arg); \ return imp.nb_transport(req_arg, rsp_arg); \ endfunction `define UVM_PUT_IMP(imp, TYPE, arg) \ `UVM_BLOCKING_PUT_IMP(imp, TYPE, arg) \ `UVM_NONBLOCKING_PUT_IMP(imp, TYPE, arg) `define UVM_GET_IMP(imp, TYPE, arg) \ `UVM_BLOCKING_GET_IMP(imp, TYPE, arg) \ `UVM_NONBLOCKING_GET_IMP(imp, TYPE, arg) `define UVM_PEEK_IMP(imp, TYPE, arg) \ `UVM_BLOCKING_PEEK_IMP(imp, TYPE, arg) \ `UVM_NONBLOCKING_PEEK_IMP(imp, TYPE, arg) `define UVM_BLOCKING_GET_PEEK_IMP(imp, TYPE, arg) \ `UVM_BLOCKING_GET_IMP(imp, TYPE, arg) \ `UVM_BLOCKING_PEEK_IMP(imp, TYPE, arg) `define UVM_NONBLOCKING_GET_PEEK_IMP(imp, TYPE, arg) \ `UVM_NONBLOCKING_GET_IMP(imp, TYPE, arg) \ `UVM_NONBLOCKING_PEEK_IMP(imp, TYPE, arg) `define UVM_GET_PEEK_IMP(imp, TYPE, arg) \ `UVM_BLOCKING_GET_PEEK_IMP(imp, TYPE, arg) \ `UVM_NONBLOCKING_GET_PEEK_IMP(imp, TYPE, arg) `define UVM_TRANSPORT_IMP(imp, REQ, RSP, req_arg, rsp_arg) \ `UVM_BLOCKING_TRANSPORT_IMP(imp, REQ, RSP, req_arg, rsp_arg) \ `UVM_NONBLOCKING_TRANSPORT_IMP(imp, REQ, RSP, req_arg, rsp_arg) `define UVM_TLM_GET_TYPE_NAME(NAME) \ virtual function string get_type_name(); \ return NAME; \ endfunction `define UVM_PORT_COMMON(MASK,TYPE_NAME) \ function new (string name, uvm_component parent, \ int min_size=1, int max_size=1); \ super.new (name, parent, UVM_PORT, min_size, max_size); \ m_if_mask = MASK; \ endfunction \ `UVM_TLM_GET_TYPE_NAME(TYPE_NAME) `define UVM_SEQ_PORT(MASK,TYPE_NAME) \ function new (string name, uvm_component parent, \ int min_size=0, int max_size=1); \ super.new (name, parent, UVM_PORT, min_size, max_size); \ m_if_mask = MASK; \ endfunction \ `UVM_TLM_GET_TYPE_NAME(TYPE_NAME) `define UVM_EXPORT_COMMON(MASK,TYPE_NAME) \ function new (string name, uvm_component parent, \ int min_size=1, int max_size=1); \ super.new (name, parent, UVM_EXPORT, min_size, max_size); \ m_if_mask = MASK; \ endfunction \ `UVM_TLM_GET_TYPE_NAME(TYPE_NAME) `define UVM_IMP_COMMON(MASK,TYPE_NAME,IMP) \ local IMP m_imp; \ function new (string name, IMP imp); \ super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); \ m_imp = imp; \ m_if_mask = MASK; \ endfunction \ `UVM_TLM_GET_TYPE_NAME(TYPE_NAME) `define UVM_MS_IMP_COMMON(MASK,TYPE_NAME) \ local this_req_type m_req_imp; \ local this_rsp_type m_rsp_imp; \ function new (string name, this_imp_type imp, \ this_req_type req_imp = null, this_rsp_type rsp_imp = null); \ super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); \ if(req_imp==null) $cast(req_imp, imp); \ if(rsp_imp==null) $cast(rsp_imp, imp); \ m_req_imp = req_imp; \ m_rsp_imp = rsp_imp; \ m_if_mask = MASK; \ endfunction \ `UVM_TLM_GET_TYPE_NAME(TYPE_NAME) `define uvm_create(SEQ_OR_ITEM, SEQR=get_sequencer()) \ begin \ uvm_object_wrapper w_; \ w_ = SEQ_OR_ITEM.get_type(); \ $cast(SEQ_OR_ITEM , create_item(w_, SEQR, `"SEQ_OR_ITEM`"));\ end `define uvm_do(SEQ_OR_ITEM, SEQR=get_sequencer(), PRIORITY=-1, CONSTRAINTS={}) \ begin \ `uvm_create(SEQ_OR_ITEM, SEQR) \ `uvm_rand_send(SEQ_OR_ITEM, PRIORITY, CONSTRAINTS) \ end `define uvm_send(SEQ_OR_ITEM, PRIORITY=-1) \ begin \ uvm_sequence_base __seq; \ if (!$cast(__seq,SEQ_OR_ITEM)) begin \ start_item(SEQ_OR_ITEM, PRIORITY);\ finish_item(SEQ_OR_ITEM, PRIORITY);\ end \ else __seq.start(__seq.get_sequencer(), this, PRIORITY, 0);\ end `define uvm_rand_send(SEQ_OR_ITEM, PRIORITY=-1, CONSTRAINTS={}) \ begin \ uvm_sequence_base __seq; \ if ( SEQ_OR_ITEM.is_item() ) begin \ start_item(SEQ_OR_ITEM, PRIORITY);\ if ( ! SEQ_OR_ITEM.randomize() with CONSTRAINTS ) begin \ `uvm_warning("RNDFLD", "Randomization failed in uvm_rand_send action") \ end\ finish_item(SEQ_OR_ITEM, PRIORITY);\ end \ else if ( $cast( __seq, SEQ_OR_ITEM ) ) begin \ __seq.set_item_context(this,SEQ_OR_ITEM.get_sequencer()); \ if ( __seq.get_randomize_enabled() ) begin \ if ( ! SEQ_OR_ITEM.randomize() with CONSTRAINTS ) begin \ `uvm_warning("RNDFLD", "Randomization failed in uvm_rand_send action") \ end \ end \ __seq.start(__seq.get_sequencer(), this, PRIORITY, 0);\ end \ else begin \ `uvm_warning("NOT_SEQ_OR_ITEM", "Object passed uvm_rand_send appears to be neither a sequence or item." ) \ end \ end `define uvm_add_to_seq_lib(TYPE,LIBTYPE) \ static bit add_``TYPE``_to_seq_lib_``LIBTYPE =\ LIBTYPE::m_add_typewide_sequence(TYPE::get_type()); `define uvm_sequence_library_utils(TYPE) \ \ static protected uvm_object_wrapper m_typewide_sequences[$]; \ \ function void init_sequence_library(); \ foreach (TYPE::m_typewide_sequences[i]) \ sequences.push_back(TYPE::m_typewide_sequences[i]); \ endfunction \ \ static function void add_typewide_sequence(uvm_object_wrapper seq_type); \ if (m_static_check(seq_type)) \ TYPE::m_typewide_sequences.push_back(seq_type); \ endfunction \ \ static function void add_typewide_sequences(uvm_object_wrapper seq_types[$]); \ foreach (seq_types[i]) \ TYPE::add_typewide_sequence(seq_types[i]); \ endfunction \ \ static function bit m_add_typewide_sequence(uvm_object_wrapper seq_type); \ TYPE::add_typewide_sequence(seq_type); \ return 1; \ endfunction `define uvm_declare_p_sequencer(SEQUENCER) \ SEQUENCER p_sequencer;\ virtual function void m_set_p_sequencer();\ super.m_set_p_sequencer(); \ if( !$cast(p_sequencer, m_sequencer)) \ `uvm_fatal("DCLPSQ", \ $sformatf("%m %s Error casting p_sequencer, please verify that this sequence/sequence item is intended to execute on this type of sequencer", get_full_name())) \ endfunction `define UVM_CB_MACROS_SVH `define uvm_register_cb(T,CB) \ static local bit m_register_cb_``CB = uvm_callbacks#(T,CB)::m_register_pair(`"T`",`"CB`"); `define uvm_set_super_type(T,ST) \ static local bit m_register_``T``ST = uvm_derived_callbacks#(T,ST)::register_super_type(`"T`",`"ST`"); `define uvm_do_callbacks(T,CB,METHOD) \ `uvm_do_obj_callbacks(T,CB,this,METHOD) `define uvm_do_obj_callbacks(T,CB,OBJ,METHOD) \ begin \ uvm_callback_iter#(T,CB) iter = new(OBJ); \ CB cb = iter.first(); \ while(cb != null) begin \ `uvm_cb_trace_noobj(cb,$sformatf(`"Executing callback method 'METHOD' for callback %s (CB) from %s (T)`",cb.get_name(), OBJ.get_full_name())) \ cb.METHOD; \ cb = iter.next(); \ end \ end `define uvm_do_callbacks_exit_on(T,CB,METHOD,VAL) \ `uvm_do_obj_callbacks_exit_on(T,CB,this,METHOD,VAL) \ `define uvm_do_obj_callbacks_exit_on(T,CB,OBJ,METHOD,VAL) \ begin \ uvm_callback_iter#(T,CB) iter = new(OBJ); \ CB cb = iter.first(); \ while(cb != null) begin \ if (cb.METHOD == VAL) begin \ `uvm_cb_trace_noobj(cb,$sformatf(`"Executed callback method 'METHOD' for callback %s (CB) from %s (T) : returned value VAL (other callbacks will be ignored)`",cb.get_name(), OBJ.get_full_name())) \ return VAL; \ end \ `uvm_cb_trace_noobj(cb,$sformatf(`"Executed callback method 'METHOD' for callback %s (CB) from %s (T) : did not return value VAL`",cb.get_name(), OBJ.get_full_name())) \ cb = iter.next(); \ end \ return 1-VAL; \ end `define uvm_cb_trace_noobj(CB,OPER) /* null */ `define uvm_cb_trace(OBJ,CB,OPER) /* null */ `define UVM_REG_ADDR_WIDTH 64 `define UVM_REG_DATA_WIDTH 64 `define UVM_REG_BYTENABLE_WIDTH ((`UVM_REG_DATA_WIDTH-1)/8+1) `define UVM_REG_CVR_WIDTH 32 package uvm_pkg; `define UVM_DPI_SVH `define UVM_HDL_NO_DPI `define UVM_REGEX_NO_DPI `define UVM_CMDLINE_NO_DPI `define UVM_HDL__SVH `define UVM_HDL_MAX_WIDTH 1024 parameter int UVM_HDL_MAX_WIDTH = 1024; typedef logic [UVM_HDL_MAX_WIDTH-1:0] uvm_hdl_data_t; function int uvm_hdl_check_path(string path); uvm_report_fatal("UVM_HDL_CHECK_PATH", $sformatf("uvm_hdl DPI routines are compiled off. Recompile without +define+UVM_HDL_NO_DPI")); return 0; endfunction function int uvm_hdl_deposit(string path, uvm_hdl_data_t value); uvm_report_fatal("UVM_HDL_DEPOSIT", $sformatf("uvm_hdl DPI routines are compiled off. Recompile without +define+UVM_HDL_NO_DPI")); return 0; endfunction function int uvm_hdl_force(string path, uvm_hdl_data_t value); uvm_report_fatal("UVM_HDL_FORCE", $sformatf("uvm_hdl DPI routines are compiled off. Recompile without +define+UVM_HDL_NO_DPI")); return 0; endfunction task uvm_hdl_force_time(string path, uvm_hdl_data_t value, time force_time=0); uvm_report_fatal("UVM_HDL_FORCE_TIME", $sformatf("uvm_hdl DPI routines are compiled off. Recompile without +define+UVM_HDL_NO_DPI")); endtask function int uvm_hdl_release(string path, output uvm_hdl_data_t value); uvm_report_fatal("UVM_HDL_RELEASE", $sformatf("uvm_hdl DPI routines are compiled off. Recompile without +define+UVM_HDL_NO_DPI")); return 0; endfunction function int uvm_hdl_read(string path, output uvm_hdl_data_t value); uvm_report_fatal("UVM_HDL_READ", $sformatf("uvm_hdl DPI routines are compiled off. Recompile without +define+UVM_HDL_NO_DPI")); return 0; endfunction function string uvm_dpi_get_next_arg(int init=0); return ""; endfunction function string uvm_dpi_get_tool_name(); return "?"; endfunction function string uvm_dpi_get_tool_version(); return "?"; endfunction function chandle uvm_dpi_regcomp(string regex); return null; endfunction function int uvm_dpi_regexec(chandle preg, string str); return 0; endfunction function void uvm_dpi_regfree(chandle preg); endfunction function int uvm_re_match(string re, string str); int e, es, s, ss; string tmp; e = 0; s = 0; es = 0; ss = 0; if(re.len() == 0) return 0; if(re[0] == "^") re = re.substr(1, re.len()-1); while (s != str.len() && re.getc(e) != "*") begin if ((re.getc(e) != str.getc(s)) && (re.getc(e) != "?")) return 1; e++; s++; end while (s != str.len()) begin if (re.getc(e) == "*") begin e++; if (e == re.len()) begin return 0; end es = e; ss = s+1; end else if (re.getc(e) == str.getc(s) || re.getc(e) == "?") begin e++; s++; end else begin e = es; s = ss++; end end while (e < re.len() && re.getc(e) == "*") e++; if(e == re.len()) begin return 0; end else begin return 1; end endfunction function string uvm_glob_to_re(string glob); return glob; endfunction `define UVM_BASE_SVH typedef class uvm_cmdline_processor; `define UVM_VERSION_SVH parameter string UVM_VERSION_STRING = "Accellera:1800.2-2017:UVM:1.0"; function string uvm_revision_string(); return UVM_VERSION_STRING; endfunction parameter UVM_STREAMBITS = 4096; typedef logic signed [UVM_STREAMBITS-1:0] uvm_bitstream_t; typedef logic signed [63:0] uvm_integral_t; parameter UVM_FIELD_FLAG_RESERVED_BITS = 28; typedef bit [UVM_FIELD_FLAG_RESERVED_BITS-1 : 0] uvm_field_flag_t; typedef enum uvm_field_flag_t { UVM_BIN = 'h1000000, UVM_DEC = 'h2000000, UVM_UNSIGNED = 'h3000000, UVM_UNFORMAT2 = 'h4000000, UVM_UNFORMAT4 = 'h5000000, UVM_OCT = 'h6000000, UVM_HEX = 'h7000000, UVM_STRING = 'h8000000, UVM_TIME = 'h9000000, UVM_ENUM = 'ha000000, UVM_REAL = 'hb000000, UVM_REAL_DEC = 'hc000000, UVM_REAL_EXP = 'hd000000, UVM_NORADIX = 0 } uvm_radix_enum; parameter UVM_RADIX = 'hf000000; function string uvm_radix_to_string(uvm_radix_enum radix); case(radix) UVM_BIN: return "b"; UVM_OCT: return "o"; UVM_DEC: return "d"; UVM_HEX: return "h"; UVM_UNSIGNED: return "u"; UVM_UNFORMAT2: return "u"; UVM_UNFORMAT4: return "z"; UVM_STRING: return "s"; UVM_TIME: return "t"; UVM_ENUM: return "s"; UVM_REAL: return "g"; UVM_REAL_DEC: return "f"; UVM_REAL_EXP: return "e"; default: return "x"; endcase endfunction typedef enum uvm_field_flag_t { UVM_DEFAULT_POLICY = 0, UVM_DEEP = (1<<16), UVM_SHALLOW = (1<<17), UVM_REFERENCE = (1<<18) } uvm_recursion_policy_enum; parameter UVM_RECURSION = (UVM_DEEP|UVM_SHALLOW|UVM_REFERENCE); typedef enum bit { UVM_PASSIVE=0, UVM_ACTIVE=1 } uvm_active_passive_enum; parameter uvm_field_flag_t UVM_MACRO_NUMFLAGS = 19; parameter uvm_field_flag_t UVM_DEFAULT = 'b000010101010101; parameter uvm_field_flag_t UVM_ALL_ON = 'b000000101010101; parameter uvm_field_flag_t UVM_FLAGS_ON = 'b000000101010101; parameter uvm_field_flag_t UVM_FLAGS_OFF = 0; parameter uvm_field_flag_t UVM_COPY = (1<<0); parameter uvm_field_flag_t UVM_NOCOPY = (1<<1); parameter uvm_field_flag_t UVM_COMPARE = (1<<2); parameter uvm_field_flag_t UVM_NOCOMPARE = (1<<3); parameter uvm_field_flag_t UVM_PRINT = (1<<4); parameter uvm_field_flag_t UVM_NOPRINT = (1<<5); parameter uvm_field_flag_t UVM_RECORD = (1<<6); parameter uvm_field_flag_t UVM_NORECORD = (1<<7); parameter uvm_field_flag_t UVM_PACK = (1<<8); parameter uvm_field_flag_t UVM_NOPACK = (1<<9); parameter uvm_field_flag_t UVM_UNPACK = (1<<10); parameter uvm_field_flag_t UVM_NOUNPACK = UVM_NOPACK; parameter uvm_field_flag_t UVM_SET = (1<<11); parameter uvm_field_flag_t UVM_NOSET = (1<<12); parameter uvm_field_flag_t UVM_NODEFPRINT = (1<<15); parameter uvm_field_flag_t UVM_MACRO_EXTRAS = (1<"; uvm_object_value_str.itoa(v.get_inst_id()); uvm_object_value_str = {"@",uvm_object_value_str}; endfunction function string uvm_leaf_scope (string full_name, byte scope_separator = "."); byte bracket_match; int pos; int bmatches; bmatches = 0; case(scope_separator) "[": bracket_match = "]"; "(": bracket_match = ")"; "<": bracket_match = ">"; "{": bracket_match = "}"; default: bracket_match = ""; endcase if(bracket_match != "" && bracket_match != full_name[full_name.len()-1]) bracket_match = ""; for(pos=full_name.len()-1; pos>0; --pos) begin if(full_name[pos] == bracket_match) bmatches++; else if(full_name[pos] == scope_separator) begin bmatches--; if(!bmatches || (bracket_match == "")) break; end end if(pos) begin if(scope_separator != ".") pos--; uvm_leaf_scope = full_name.substr(pos+1,full_name.len()-1); end else begin uvm_leaf_scope = full_name; end endfunction function string uvm_bitstream_to_string (uvm_bitstream_t value, int size, uvm_radix_enum radix=UVM_NORADIX, string radix_str=""); if (radix == UVM_DEC && value[size-1] === 1) return $sformatf("%0d", value); if($isunknown(value)) begin uvm_bitstream_t _t; _t=0; for(int idx=0;idx 0 && (arg[i] != "[")) begin --i; if((arg[i] == "*") || (arg[i] == "?")) i=0; else if((arg[i] < "0") || (arg[i] > "9") && (arg[i] != "[")) begin uvm_get_array_index_int = -1; i=0; end end else begin is_wildcard = 0; return 0; end if(i>0) begin arg = arg.substr(i+1, arg.len()-2); uvm_get_array_index_int = arg.atoi(); is_wildcard = 0; end endfunction function string uvm_get_array_index_string(string arg, output bit is_wildcard); int i; uvm_get_array_index_string = ""; is_wildcard = 1; i = arg.len() - 1; if(arg[i] == "]") while(i > 0 && (arg[i] != "[")) begin if((arg[i] == "*") || (arg[i] == "?")) i=0; --i; end if(i>0) begin uvm_get_array_index_string = arg.substr(i+1, arg.len()-2); is_wildcard = 0; end endfunction function bit uvm_is_array(string arg); return arg[arg.len()-1] == "]"; endfunction function automatic bit uvm_has_wildcard (string arg); uvm_has_wildcard = 0; if( (arg.len() > 1) && (arg[0] == "/") && (arg[arg.len()-1] == "/") ) return 1; foreach(arg[i]) if( (arg[i] == "*") || (arg[i] == "+") || (arg[i] == "?") ) uvm_has_wildcard = 1; endfunction typedef class uvm_component; typedef class uvm_root; typedef class uvm_report_object; function automatic string m_uvm_string_queue_join(ref string i[$]); m_uvm_string_queue_join = {>>{i}}; endfunction typedef class uvm_factory; typedef class uvm_default_factory; typedef class uvm_report_server; typedef class uvm_default_report_server; typedef class uvm_root; typedef class uvm_visitor; typedef class uvm_component_name_check_visitor; typedef class uvm_component; typedef class uvm_comparer; typedef class uvm_copier; typedef class uvm_packer; typedef class uvm_printer; typedef class uvm_table_printer; typedef class uvm_tr_database; typedef class uvm_text_tr_database; typedef class uvm_resource_pool; typedef class uvm_default_coreservice_t; virtual class uvm_coreservice_t; pure virtual function uvm_factory get_factory(); pure virtual function void set_factory(uvm_factory f); pure virtual function uvm_report_server get_report_server(); pure virtual function void set_report_server(uvm_report_server server); pure virtual function uvm_tr_database get_default_tr_database(); pure virtual function void set_default_tr_database(uvm_tr_database db); pure virtual function void set_component_visitor(uvm_visitor#(uvm_component) v); pure virtual function uvm_visitor#(uvm_component) get_component_visitor(); pure virtual function uvm_root get_root(); pure virtual function void set_phase_max_ready_to_end(int max); pure virtual function int get_phase_max_ready_to_end(); pure virtual function void set_default_printer(uvm_printer printer); pure virtual function uvm_printer get_default_printer(); pure virtual function void set_default_packer(uvm_packer packer); pure virtual function uvm_packer get_default_packer(); pure virtual function void set_default_comparer(uvm_comparer comparer); pure virtual function uvm_comparer get_default_comparer(); pure virtual function int unsigned get_global_seed(); pure virtual function void set_default_copier(uvm_copier copier); pure virtual function uvm_copier get_default_copier(); pure virtual function bit get_uvm_seeding(); pure virtual function void set_uvm_seeding(bit enable); pure virtual function void set_resource_pool (uvm_resource_pool pool); pure virtual function uvm_resource_pool get_resource_pool(); pure virtual function void set_resource_pool_default_precedence(int unsigned precedence); pure virtual function int unsigned get_resource_pool_default_precedence(); local static uvm_coreservice_t inst; static function uvm_coreservice_t get(); if(inst==null) uvm_init(null); return inst; endfunction static function void set(uvm_coreservice_t cs); inst=cs; endfunction endclass class uvm_default_coreservice_t extends uvm_coreservice_t; local uvm_factory factory; virtual function uvm_factory get_factory(); if(factory==null) begin uvm_default_factory f; f=new; factory=f; end return factory; endfunction virtual function void set_factory(uvm_factory f); factory = f; endfunction local uvm_tr_database tr_database; virtual function uvm_tr_database get_default_tr_database(); if (tr_database == null) begin process p = process::self(); uvm_text_tr_database tx_db; string s; if(p != null) s = p.get_randstate(); tx_db = new("default_tr_database"); tr_database = tx_db; if(p != null) p.set_randstate(s); end return tr_database; endfunction : get_default_tr_database virtual function void set_default_tr_database(uvm_tr_database db); tr_database = db; endfunction : set_default_tr_database local uvm_report_server report_server; virtual function uvm_report_server get_report_server(); if(report_server==null) begin uvm_default_report_server f; f=new; report_server=f; end return report_server; endfunction virtual function void set_report_server(uvm_report_server server); report_server=server; endfunction virtual function uvm_root get_root(); return uvm_root::m_uvm_get_root(); endfunction local uvm_visitor#(uvm_component) _visitor; virtual function void set_component_visitor(uvm_visitor#(uvm_component) v); _visitor=v; endfunction virtual function uvm_visitor#(uvm_component) get_component_visitor(); if(_visitor==null) begin uvm_component_name_check_visitor v = new("name-check-visitor"); _visitor=v; end return _visitor; endfunction local uvm_printer m_printer ; virtual function void set_default_printer(uvm_printer printer); m_printer = printer ; endfunction virtual function uvm_printer get_default_printer(); if (m_printer == null) begin m_printer = uvm_table_printer::get_default() ; end return m_printer ; endfunction local uvm_packer m_packer ; virtual function void set_default_packer(uvm_packer packer); m_packer = packer ; endfunction virtual function uvm_packer get_default_packer(); if (m_packer == null) begin m_packer = new("uvm_default_packer") ; end return m_packer ; endfunction local uvm_comparer m_comparer ; virtual function void set_default_comparer(uvm_comparer comparer); m_comparer = comparer ; endfunction virtual function uvm_comparer get_default_comparer(); if (m_comparer == null) begin m_comparer = new("uvm_default_comparer") ; end return m_comparer ; endfunction local int m_default_max_ready_to_end_iters = 20; virtual function void set_phase_max_ready_to_end(int max); m_default_max_ready_to_end_iters = max; endfunction virtual function int get_phase_max_ready_to_end(); return m_default_max_ready_to_end_iters; endfunction local uvm_resource_pool m_rp ; virtual function void set_resource_pool (uvm_resource_pool pool); m_rp = pool; endfunction virtual function uvm_resource_pool get_resource_pool(); if(m_rp == null) m_rp = new(); return m_rp; endfunction local int unsigned m_default_precedence = 1000; virtual function void set_resource_pool_default_precedence(int unsigned precedence); m_default_precedence = precedence; endfunction virtual function int unsigned get_resource_pool_default_precedence(); return m_default_precedence; endfunction local int unsigned m_uvm_global_seed = $urandom; virtual function int unsigned get_global_seed(); return m_uvm_global_seed; endfunction local bit m_use_uvm_seeding = 1; virtual function bit get_uvm_seeding(); return m_use_uvm_seeding; endfunction : get_uvm_seeding virtual function void set_uvm_seeding(bit enable); m_use_uvm_seeding = enable; endfunction : set_uvm_seeding local uvm_copier m_copier ; virtual function void set_default_copier(uvm_copier copier); m_copier = copier ; endfunction virtual function uvm_copier get_default_copier(); if (m_copier == null) begin m_copier = new("uvm_default_copier") ; end return m_copier ; endfunction endclass typedef class uvm_root; typedef class uvm_report_object; typedef class uvm_report_message; task run_test (string test_name=""); uvm_root top; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); top = cs.get_root(); top.run_test(test_name); endtask function uvm_report_object uvm_get_report_object(); uvm_root top; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); top = cs.get_root(); return top; endfunction function int uvm_report_enabled (int verbosity, uvm_severity severity=UVM_INFO, string id=""); uvm_root top; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); top = cs.get_root(); return top.uvm_report_enabled(verbosity,severity,id); endfunction function void uvm_report( uvm_severity severity, string id, string message, int verbosity = (severity == uvm_severity'(UVM_ERROR)) ? UVM_LOW : (severity == uvm_severity'(UVM_FATAL)) ? UVM_NONE : UVM_MEDIUM, string filename = "", int line = 0, string context_name = "", bit report_enabled_checked = 0); uvm_root top; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); top = cs.get_root(); top.uvm_report(severity, id, message, verbosity, filename, line, context_name, report_enabled_checked); endfunction export "DPI-C" function m__uvm_report_dpi; function void m__uvm_report_dpi(int severity, string id, string message, int verbosity, string filename, int line); uvm_report(uvm_severity'(severity), id, message, verbosity, filename, line); endfunction : m__uvm_report_dpi function void uvm_report_info(string id, string message, int verbosity = UVM_MEDIUM, string filename = "", int line = 0, string context_name = "", bit report_enabled_checked = 0); uvm_root top; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); top = cs.get_root(); top.uvm_report_info(id, message, verbosity, filename, line, context_name, report_enabled_checked); endfunction function void uvm_report_warning(string id, string message, int verbosity = UVM_MEDIUM, string filename = "", int line = 0, string context_name = "", bit report_enabled_checked = 0); uvm_root top; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); top = cs.get_root(); top.uvm_report_warning(id, message, verbosity, filename, line, context_name, report_enabled_checked); endfunction function void uvm_report_error(string id, string message, int verbosity = UVM_NONE, string filename = "", int line = 0, string context_name = "", bit report_enabled_checked = 0); uvm_root top; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); top = cs.get_root(); top.uvm_report_error(id, message, verbosity, filename, line, context_name, report_enabled_checked); endfunction function void uvm_report_fatal(string id, string message, int verbosity = UVM_NONE, string filename = "", int line = 0, string context_name = "", bit report_enabled_checked = 0); uvm_root top; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); top = cs.get_root(); top.uvm_report_fatal(id, message, verbosity, filename, line, context_name, report_enabled_checked); endfunction function void uvm_process_report_message(uvm_report_message report_message); uvm_root top; uvm_coreservice_t cs; process p; p = process::self(); cs = uvm_coreservice_t::get(); top = cs.get_root(); top.uvm_process_report_message(report_message); endfunction function bit uvm_string_to_severity (string sev_str, output uvm_severity sev); case (sev_str) "UVM_INFO": sev = UVM_INFO; "UVM_WARNING": sev = UVM_WARNING; "UVM_ERROR": sev = UVM_ERROR; "UVM_FATAL": sev = UVM_FATAL; default: return 0; endcase return 1; endfunction function automatic bit uvm_string_to_action (string action_str, output uvm_action action); string actions[$]; uvm_split_string(action_str,"|",actions); uvm_string_to_action = 1; action = 0; foreach(actions[i]) begin case (actions[i]) "UVM_NO_ACTION": action |= UVM_NO_ACTION; "UVM_DISPLAY": action |= UVM_DISPLAY; "UVM_LOG": action |= UVM_LOG; "UVM_COUNT": action |= UVM_COUNT; "UVM_EXIT": action |= UVM_EXIT; "UVM_CALL_HOOK": action |= UVM_CALL_HOOK; "UVM_STOP": action |= UVM_STOP; "UVM_RM_RECORD": action |= UVM_RM_RECORD; default: uvm_string_to_action = 0; endcase end endfunction function bit uvm_is_match (string expr, string str); string s; s = uvm_glob_to_re(expr); return (uvm_re_match(s, str) == 0); endfunction parameter UVM_LINE_WIDTH = 120; parameter UVM_NUM_LINES = 120; parameter UVM_SMALL_STRING = UVM_LINE_WIDTH*8-1; parameter UVM_LARGE_STRING = UVM_LINE_WIDTH*UVM_NUM_LINES*8-1; function logic[UVM_LARGE_STRING:0] uvm_string_to_bits(string str); $swrite(uvm_string_to_bits, "%0s", str); endfunction function uvm_core_state get_core_state(); return m_uvm_core_state; endfunction function void uvm_init(uvm_coreservice_t cs=null); uvm_default_coreservice_t dcs; if(get_core_state()!=UVM_CORE_UNINITIALIZED) begin if (get_core_state() == UVM_CORE_PRE_INIT) begin dcs = new(); uvm_coreservice_t::set(dcs); begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"UVM/INIT/MULTI")) uvm_report_fatal ("UVM/INIT/MULTI", "Non-recoverable race during uvm_init", UVM_NONE, "t/uvm/src/base/uvm_globals.svh", 335, "", 1); end end else begin uvm_coreservice_t actual; actual = uvm_coreservice_t::get(); if ((cs != actual) && (cs != null)) begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"UVM/INIT/MULTI")) uvm_report_warning ("UVM/INIT/MULTI", "uvm_init() called after library has already completed initialization, subsequent calls are ignored!", UVM_NONE, "t/uvm/src/base/uvm_globals.svh", 344, "", 1); end end return; end m_uvm_core_state=UVM_CORE_PRE_INIT; if(cs == null) begin dcs = new(); cs = dcs; end uvm_coreservice_t::set(cs); m_uvm_core_state=UVM_CORE_INITIALIZING; foreach(uvm_deferred_init[idx]) begin uvm_deferred_init[idx].initialize(); end uvm_deferred_init.delete(); begin uvm_root top; top = uvm_root::get(); top.report_header(); top.m_check_uvm_field_flag_size(); top.m_check_verbosity(); end m_uvm_core_state=UVM_CORE_INITIALIZED; endfunction function string uvm_bits_to_string(logic [UVM_LARGE_STRING:0] str); $swrite(uvm_bits_to_string, "%0s", str); endfunction task uvm_wait_for_nba_region; int nba; int next_nba; next_nba++; nba <= next_nba; @(nba); endtask function automatic void uvm_split_string (string str, byte sep, ref string values[$]); int s = 0, e = 0; values.delete(); while(e < str.len()) begin for(s=e; e"; endfunction virtual function uvm_object create (string name=""); return null; endfunction extern virtual function uvm_object clone (); extern function void print (uvm_printer printer=null); extern function string sprint (uvm_printer printer=null); extern virtual function void do_print (uvm_printer printer); extern virtual function string convert2string(); extern function void record (uvm_recorder recorder=null); extern virtual function void do_record (uvm_recorder recorder); extern function void copy (uvm_object rhs, uvm_copier copier=null); extern virtual function void do_copy (uvm_object rhs); extern function bit compare (uvm_object rhs, uvm_comparer comparer=null); extern virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); extern function int pack (ref bit bitstream[], input uvm_packer packer=null); extern function int pack_bytes (ref byte unsigned bytestream[], input uvm_packer packer=null); extern function int pack_ints (ref int unsigned intstream[], input uvm_packer packer=null); extern function int pack_longints (ref longint unsigned longintstream[], input uvm_packer packer=null); extern virtual function void do_pack (uvm_packer packer); extern function int unpack (ref bit bitstream[], input uvm_packer packer=null); extern function int unpack_bytes (ref byte unsigned bytestream[], input uvm_packer packer=null); extern function int unpack_ints (ref int unsigned intstream[], input uvm_packer packer=null); extern function int unpack_longints (ref longint unsigned longintstream[], input uvm_packer packer=null); extern virtual function void do_unpack (uvm_packer packer); extern virtual function void do_execute_op ( uvm_field_op op); extern virtual function void set_local(uvm_resource_base rsrc) ; extern local function void m_pack (inout uvm_packer packer); extern local function void m_unpack_pre (inout uvm_packer packer); extern local function int m_unpack_post (uvm_packer packer); extern virtual function void m_unsupported_set_local(uvm_resource_base rsrc); local string m_leaf_name; local int m_inst_id; static protected int m_inst_count; extern virtual function void __m_uvm_field_automation (uvm_object tmp_data__, uvm_field_flag_t what__, string str__); extern protected virtual function uvm_report_object m_get_report_object(); endclass function uvm_object::new (string name=""); m_inst_id = m_inst_count++; m_leaf_name = name; endfunction function bit uvm_object::get_uvm_seeding(); uvm_coreservice_t cs = uvm_coreservice_t::get(); return cs.get_uvm_seeding(); endfunction function void uvm_object::set_uvm_seeding(bit enable); uvm_coreservice_t cs = uvm_coreservice_t::get(); cs.set_uvm_seeding(enable); endfunction function void uvm_object::reseed (); if(get_uvm_seeding()) this.srandom(uvm_create_random_seed(get_type_name(), get_full_name())); endfunction function uvm_object_wrapper uvm_object::get_type(); uvm_report_error("NOTYPID", "get_type not implemented in derived class.", UVM_NONE); return null; endfunction function int uvm_object::get_inst_id(); return m_inst_id; endfunction function uvm_object_wrapper uvm_object::get_object_type(); uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory factory=cs.get_factory(); if(get_type_name() == "") return null; return factory.find_wrapper_by_name(get_type_name()); endfunction function int uvm_object::get_inst_count(); return m_inst_count; endfunction function string uvm_object::get_name (); return m_leaf_name; endfunction function string uvm_object::get_full_name (); return get_name(); endfunction function void uvm_object::set_name (string name); m_leaf_name = name; endfunction function void uvm_object::print(uvm_printer printer=null); if (printer==null) printer = uvm_printer::get_default(); $fwrite(printer.get_file(),sprint(printer)); endfunction function string uvm_object::sprint(uvm_printer printer=null); string name; if(printer==null) printer = uvm_printer::get_default(); if (printer.get_active_object_depth() == 0) begin printer.flush() ; name = printer.get_root_enabled() ? get_full_name() : get_name(); end else begin name = get_name(); end printer.print_object(name,this); return printer.emit(); endfunction function string uvm_object::convert2string(); return ""; endfunction function void uvm_object::set_local(uvm_resource_base rsrc) ; if(rsrc==null) begin return ; end else begin begin uvm_field_op op; op = uvm_field_op::m_get_available_op(); op.set(UVM_SET,null,rsrc); this.do_execute_op(op); op.m_recycle(); end end endfunction function void uvm_object::m_unsupported_set_local(uvm_resource_base rsrc); return; endfunction function uvm_object uvm_object::clone(); uvm_object tmp; tmp = this.create(get_name()); if(tmp == null) uvm_report_warning("CRFLD", $sformatf("The create method failed for %s, object cannot be cloned", get_name()), UVM_NONE); else tmp.copy(this); return(tmp); endfunction function void uvm_object::copy (uvm_object rhs, uvm_copier copier=null); uvm_coreservice_t coreservice ; uvm_copier m_copier; if(rhs == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"OBJ/COPY")) uvm_report_error ("OBJ/COPY", "Passing a null object to be copied", UVM_NONE, "t/uvm/src/base/uvm_object.svh", 1138, "", 1); end return; end if(copier == null) begin coreservice = uvm_coreservice_t::get() ; m_copier = coreservice.get_default_copier() ; end else m_copier = copier; if(m_copier.get_active_object_depth() == 0) m_copier.flush(); m_copier.copy_object(this,rhs); endfunction function void uvm_object::do_copy (uvm_object rhs); return; endfunction function bit uvm_object::compare (uvm_object rhs, uvm_comparer comparer=null); if (comparer == null) comparer = uvm_comparer::get_default(); if (comparer.get_active_object_depth() == 0) comparer.flush() ; compare = comparer.compare_object(get_name(),this,rhs); endfunction function bit uvm_object::do_compare (uvm_object rhs, uvm_comparer comparer); return 1; endfunction function void uvm_object::__m_uvm_field_automation (uvm_object tmp_data__, uvm_field_flag_t what__, string str__ ); return; endfunction function void uvm_object::do_print(uvm_printer printer); return; endfunction function void uvm_object::m_pack (inout uvm_packer packer); if (packer == null) packer = uvm_packer::get_default(); if(packer.get_active_object_depth() == 0) packer.flush(); packer.pack_object(this); endfunction function int uvm_object::pack (ref bit bitstream [], input uvm_packer packer =null ); m_pack(packer); packer.get_packed_bits(bitstream); return packer.get_packed_size(); endfunction function int uvm_object::pack_bytes (ref byte unsigned bytestream [], input uvm_packer packer=null ); m_pack(packer); packer.get_packed_bytes(bytestream); return packer.get_packed_size(); endfunction function int uvm_object::pack_ints (ref int unsigned intstream [], input uvm_packer packer=null ); m_pack(packer); packer.get_packed_ints(intstream); return packer.get_packed_size(); endfunction function int uvm_object::pack_longints (ref longint unsigned longintstream [], input uvm_packer packer=null ); m_pack(packer); packer.get_packed_longints(longintstream); return packer.get_packed_size(); endfunction function void uvm_object::do_pack (uvm_packer packer ); if (packer == null) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/OBJ/PACK/NULL")) uvm_report_error ("UVM/OBJ/PACK/NULL", "uvm_object::do_pack called with null packer!", UVM_NONE, "t/uvm/src/base/uvm_object.svh", 1265, "", 1); end return; endfunction function void uvm_object::m_unpack_pre (inout uvm_packer packer); if (packer == null) packer = uvm_packer::get_default(); if(packer.get_active_object_depth() == 0) packer.flush(); endfunction function int uvm_object::m_unpack_post (uvm_packer packer); int size_before_unpack = packer.get_packed_size(); packer.unpack_object(this); return size_before_unpack - packer.get_packed_size(); endfunction function int uvm_object::unpack (ref bit bitstream [], input uvm_packer packer=null); m_unpack_pre(packer); packer.set_packed_bits(bitstream); return m_unpack_post(packer); endfunction function int uvm_object::unpack_bytes (ref byte unsigned bytestream [], input uvm_packer packer=null); m_unpack_pre(packer); packer.set_packed_bytes(bytestream); return m_unpack_post(packer); endfunction function int uvm_object::unpack_ints (ref int unsigned intstream [], input uvm_packer packer=null); m_unpack_pre(packer); packer.set_packed_ints(intstream); return m_unpack_post(packer); endfunction function int uvm_object::unpack_longints (ref longint unsigned longintstream [], input uvm_packer packer=null); m_unpack_pre(packer); packer.set_packed_longints(longintstream); return m_unpack_post(packer); endfunction function void uvm_object::do_execute_op ( uvm_field_op op); endfunction function void uvm_object::do_unpack (uvm_packer packer); if (packer == null) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/OBJ/UNPACK/NULL")) uvm_report_error ("UVM/OBJ/UNPACK/NULL", "uvm_object::do_unpack called with null packer!", UVM_NONE, "t/uvm/src/base/uvm_object.svh", 1345, "", 1); end return; endfunction function void uvm_object::record (uvm_recorder recorder=null); if(recorder == null) return; recorder.record_object(get_name(), this); endfunction function void uvm_object::do_record (uvm_recorder recorder); return; endfunction function uvm_report_object uvm_object::m_get_report_object(); return null; endfunction typedef class uvm_object; typedef class uvm_component; typedef class uvm_object_wrapper; typedef class uvm_factory_override; typedef struct {uvm_object_wrapper m_type; string m_type_name;} m_uvm_factory_type_pair_t; class uvm_factory_queue_class; uvm_factory_override queue[$]; endclass virtual class uvm_factory; static function uvm_factory get(); uvm_coreservice_t s; s = uvm_coreservice_t::get(); return s.get_factory(); endfunction static function void set(uvm_factory f); uvm_coreservice_t s; s = uvm_coreservice_t::get(); s.set_factory(f); endfunction pure virtual function void register (uvm_object_wrapper obj); pure virtual function void set_inst_override_by_type (uvm_object_wrapper original_type, uvm_object_wrapper override_type, string full_inst_path); pure virtual function void set_inst_override_by_name (string original_type_name, string override_type_name, string full_inst_path); pure virtual function void set_type_override_by_type (uvm_object_wrapper original_type, uvm_object_wrapper override_type, bit replace=1); pure virtual function void set_type_override_by_name (string original_type_name, string override_type_name, bit replace=1); pure virtual function uvm_object create_object_by_type (uvm_object_wrapper requested_type, string parent_inst_path="", string name=""); pure virtual function uvm_component create_component_by_type (uvm_object_wrapper requested_type, string parent_inst_path="", string name, uvm_component parent); pure virtual function uvm_object create_object_by_name (string requested_type_name, string parent_inst_path="", string name=""); pure virtual function bit is_type_name_registered (string type_name); pure virtual function bit is_type_registered (uvm_object_wrapper obj); pure virtual function uvm_component create_component_by_name (string requested_type_name, string parent_inst_path="", string name, uvm_component parent); pure virtual function void set_type_alias(string alias_type_name, uvm_object_wrapper original_type); pure virtual function void set_inst_alias(string alias_type_name, uvm_object_wrapper original_type, string full_inst_path); pure virtual function void debug_create_by_type (uvm_object_wrapper requested_type, string parent_inst_path="", string name=""); pure virtual function void debug_create_by_name (string requested_type_name, string parent_inst_path="", string name=""); pure virtual function uvm_object_wrapper find_override_by_type (uvm_object_wrapper requested_type, string full_inst_path); pure virtual function uvm_object_wrapper find_override_by_name (string requested_type_name, string full_inst_path); pure virtual function uvm_object_wrapper find_wrapper_by_name (string type_name); pure virtual function void print (int all_types=1); endclass class uvm_default_factory extends uvm_factory; extern virtual function void register (uvm_object_wrapper obj); extern virtual function void set_inst_override_by_type (uvm_object_wrapper original_type, uvm_object_wrapper override_type, string full_inst_path); extern virtual function void set_inst_override_by_name (string original_type_name, string override_type_name, string full_inst_path); extern virtual function void set_type_override_by_type (uvm_object_wrapper original_type, uvm_object_wrapper override_type, bit replace=1); extern virtual function void set_type_override_by_name (string original_type_name, string override_type_name, bit replace=1); extern virtual function void set_type_alias(string alias_type_name, uvm_object_wrapper original_type); extern virtual function void set_inst_alias(string alias_type_name, uvm_object_wrapper original_type, string full_inst_path); extern virtual function uvm_object create_object_by_type (uvm_object_wrapper requested_type, string parent_inst_path="", string name=""); extern virtual function uvm_component create_component_by_type (uvm_object_wrapper requested_type, string parent_inst_path="", string name, uvm_component parent); extern virtual function uvm_object create_object_by_name (string requested_type_name, string parent_inst_path="", string name=""); extern virtual function uvm_component create_component_by_name (string requested_type_name, string parent_inst_path="", string name, uvm_component parent); extern virtual function bit is_type_name_registered (string type_name); extern virtual function bit is_type_registered (uvm_object_wrapper obj); extern virtual function void debug_create_by_type (uvm_object_wrapper requested_type, string parent_inst_path="", string name=""); extern virtual function void debug_create_by_name (string requested_type_name, string parent_inst_path="", string name=""); extern virtual function uvm_object_wrapper find_override_by_type (uvm_object_wrapper requested_type, string full_inst_path); extern virtual function uvm_object_wrapper find_override_by_name (string requested_type_name, string full_inst_path); extern virtual function uvm_object_wrapper find_wrapper_by_name (string type_name); extern virtual function void print (int all_types=1); extern protected function void m_debug_create (string requested_type_name, uvm_object_wrapper requested_type, string parent_inst_path, string name); extern protected function void m_debug_display(string requested_type_name, uvm_object_wrapper result, string full_inst_path); extern function uvm_object_wrapper m_resolve_type_name(string requested_type_name); extern function uvm_object_wrapper m_resolve_type_name_by_inst(string requested_type_name, string full_inst_path); extern function bit m_matches_type_pair(m_uvm_factory_type_pair_t match_type_pair, uvm_object_wrapper requested_type, string requested_type_name); extern function bit m_matches_type_override(uvm_factory_override override, uvm_object_wrapper requested_type, string requested_type_name, string full_inst_path="", bit match_original_type = 1, bit resolve_null_type_by_inst=0); extern function bit m_matches_inst_override(uvm_factory_override override, uvm_object_wrapper requested_type, string requested_type_name, string full_inst_path=""); typedef struct { m_uvm_factory_type_pair_t orig; string alias_type_name; string full_inst_path; } m_inst_typename_alias_t; protected bit m_types[uvm_object_wrapper]; protected bit m_lookup_strs[string]; protected uvm_object_wrapper m_type_names[string]; protected m_inst_typename_alias_t m_inst_aliases[$]; protected uvm_factory_override m_type_overrides[$]; protected uvm_factory_override m_inst_overrides[$]; local uvm_factory_override m_override_info[$]; local static bit m_debug_pass; extern function bit check_inst_override_exists (uvm_object_wrapper original_type, string original_type_name, uvm_object_wrapper override_type, string override_type_name, string full_inst_path); endclass virtual class uvm_object_wrapper; virtual function uvm_object create_object (string name=""); return null; endfunction virtual function uvm_component create_component (string name, uvm_component parent); return null; endfunction pure virtual function string get_type_name(); virtual function void initialize(); endfunction endclass class uvm_factory_override; string full_inst_path; m_uvm_factory_type_pair_t orig; m_uvm_factory_type_pair_t ovrd; bit replace; bit selected; int unsigned used; bit has_wildcard; function new (string full_inst_path="", string orig_type_name="", uvm_object_wrapper orig_type=null, uvm_object_wrapper ovrd_type, string ovrd_type_name="", bit replace=0); this.full_inst_path= full_inst_path; this.orig.m_type_name = orig_type_name; this.orig.m_type = orig_type; this.ovrd.m_type_name = ovrd_type_name; this.ovrd.m_type = ovrd_type; this.replace = replace; this.has_wildcard = m_has_wildcard(full_inst_path); endfunction function bit m_has_wildcard(string nm); foreach (nm[i]) if(nm[i] == "*" || nm[i] == "?") return 1; return 0; endfunction endclass function void uvm_default_factory::register (uvm_object_wrapper obj); if (obj == null) begin uvm_report_fatal ("NULLWR", "Attempting to register a null object with the factory", UVM_NONE); end if (obj.get_type_name() != "" && obj.get_type_name() != "") begin if (m_type_names.exists(obj.get_type_name())) uvm_report_warning("TPRGED", {"Type name '",obj.get_type_name(), "' already registered with factory. No string-based lookup ", "support for multiple types with the same type name."}, UVM_NONE); else m_type_names[obj.get_type_name()] = obj; end if (m_types.exists(obj)) begin if (obj.get_type_name() != "" && obj.get_type_name() != "") uvm_report_warning("TPRGED", {"Object type '",obj.get_type_name(), "' already registered with factory. "}, UVM_NONE); end else begin uvm_factory_override overrides[$]; m_types[obj] = 1; overrides = {m_type_overrides, m_inst_overrides}; foreach (overrides[index]) begin if(m_matches_type_pair(.match_type_pair(overrides[index].orig), .requested_type(null), .requested_type_name(obj.get_type_name()))) begin overrides[index].orig.m_type = obj; end if(m_matches_type_pair(.match_type_pair(overrides[index].ovrd), .requested_type(null), .requested_type_name(obj.get_type_name()))) begin overrides[index].ovrd.m_type = obj; end end end endfunction function void uvm_default_factory::set_type_override_by_type (uvm_object_wrapper original_type, uvm_object_wrapper override_type, bit replace=1); bit replaced; if (original_type == override_type) begin if (original_type.get_type_name() == "" || original_type.get_type_name() == "") uvm_report_warning("TYPDUP", {"Original and override type ", "arguments are identical"}, UVM_NONE); else uvm_report_warning("TYPDUP", {"Original and override type ", "arguments are identical: ", original_type.get_type_name()}, UVM_NONE); end if (!m_types.exists(original_type)) register(original_type); if (!m_types.exists(override_type)) register(override_type); foreach (m_type_overrides[index]) begin if(m_matches_type_override(.override(m_type_overrides[index]), .requested_type(original_type), .requested_type_name(original_type.get_type_name()))) begin string msg; msg = {"Original object type '",original_type.get_type_name(), "' already registered to produce '", m_type_overrides[index].ovrd.m_type_name,"'"}; if (!replace) begin msg = {msg, ". Set 'replace' argument to replace the existing entry."}; uvm_report_info("TPREGD", msg, UVM_MEDIUM); return; end msg = {msg, ". Replacing with override to produce type '", override_type.get_type_name(),"'."}; uvm_report_info("TPREGR", msg, UVM_MEDIUM); replaced = 1; m_type_overrides[index].orig.m_type = original_type; m_type_overrides[index].orig.m_type_name = original_type.get_type_name(); m_type_overrides[index].ovrd.m_type = override_type; m_type_overrides[index].ovrd.m_type_name = override_type.get_type_name(); m_type_overrides[index].replace = replace; end else if (m_type_overrides[index].orig.m_type == null) begin break; end end if (!replaced) begin uvm_factory_override override; override = new(.orig_type(original_type), .orig_type_name(original_type.get_type_name()), .ovrd_type(override_type), .ovrd_type_name(override_type.get_type_name()), .replace(replace)); m_type_overrides.push_front(override); end endfunction function void uvm_default_factory::set_type_override_by_name (string original_type_name, string override_type_name, bit replace=1); bit replaced; uvm_object_wrapper original_type; uvm_object_wrapper override_type; if(m_type_names.exists(original_type_name)) original_type = m_type_names[original_type_name]; if(m_type_names.exists(override_type_name)) override_type = m_type_names[override_type_name]; if (original_type_name == override_type_name) begin uvm_report_warning("TYPDUP", {"Requested and actual type name ", " arguments are identical: ",original_type_name,". Ignoring this override."}, UVM_NONE); return; end foreach (m_type_overrides[index]) begin if(m_matches_type_override(.override(m_type_overrides[index]), .requested_type(original_type), .requested_type_name(original_type_name))) begin if (!replace) begin uvm_report_info("TPREGD", {"Original type '",original_type_name, "'/'",m_type_overrides[index].orig.m_type_name, "' already registered to produce '",m_type_overrides[index].ovrd.m_type_name, "'. Set 'replace' argument to replace the existing entry."}, UVM_MEDIUM); return; end uvm_report_info("TPREGR", {"Original object type '",original_type_name, "'/'",m_type_overrides[index].orig.m_type_name, "' already registered to produce '",m_type_overrides[index].ovrd.m_type_name, "'. Replacing with override to produce type '",override_type_name,"'."}, UVM_MEDIUM); replaced = 1; m_type_overrides[index].ovrd.m_type = override_type; m_type_overrides[index].ovrd.m_type_name = override_type_name; m_type_overrides[index].replace = replace; end else if ((m_type_overrides[index].orig.m_type == null) || (original_type == null)) begin break; end end if (original_type == null) m_lookup_strs[original_type_name] = 1; if (!replaced) begin uvm_factory_override override; override = new(.orig_type(original_type), .orig_type_name(original_type_name), .ovrd_type(override_type), .ovrd_type_name(override_type_name), .replace(replace) ); m_type_overrides.push_front(override); end endfunction function bit uvm_default_factory::check_inst_override_exists (uvm_object_wrapper original_type, string original_type_name, uvm_object_wrapper override_type, string override_type_name, string full_inst_path); uvm_factory_override override; foreach (m_inst_overrides[i]) begin override = m_inst_overrides[i]; if (override.full_inst_path == full_inst_path && override.orig.m_type == original_type && override.orig.m_type_name == original_type_name && override.ovrd.m_type == override_type && override.ovrd.m_type_name == override_type_name) begin uvm_report_info("DUPOVRD",{"Instance override for '", original_type_name,"' already exists: override type '", override_type_name,"' with full_inst_path '", full_inst_path,"'"},UVM_HIGH); return 1; end end return 0; endfunction function void uvm_default_factory::set_inst_override_by_type (uvm_object_wrapper original_type, uvm_object_wrapper override_type, string full_inst_path); uvm_factory_override override; if (!m_types.exists(original_type)) register(original_type); if (!m_types.exists(override_type)) register(override_type); if (check_inst_override_exists(original_type, original_type.get_type_name(), override_type, override_type.get_type_name(), full_inst_path)) return; override = new(.full_inst_path(full_inst_path), .orig_type(original_type), .orig_type_name(original_type.get_type_name()), .ovrd_type(override_type), .ovrd_type_name(override_type.get_type_name())); m_inst_overrides.push_back(override); endfunction function void uvm_default_factory::set_inst_override_by_name (string original_type_name, string override_type_name, string full_inst_path); uvm_factory_override override; uvm_object_wrapper original_type; uvm_object_wrapper override_type; if(m_type_names.exists(original_type_name)) original_type = m_type_names[original_type_name]; if(m_type_names.exists(override_type_name)) override_type = m_type_names[override_type_name]; if (original_type == null) m_lookup_strs[original_type_name] = 1; override = new(.full_inst_path(full_inst_path), .orig_type(original_type), .orig_type_name(original_type_name), .ovrd_type(override_type), .ovrd_type_name(override_type_name)); if (check_inst_override_exists(original_type, original_type_name, override_type, override_type_name, full_inst_path)) return; m_inst_overrides.push_back(override); endfunction function void uvm_default_factory::set_type_alias(string alias_type_name, uvm_object_wrapper original_type); if (!is_type_registered(original_type)) uvm_report_warning("BDTYP",{"Cannot define alias of type '", original_type.get_type_name(),"' because it is not registered with the factory."}, UVM_NONE); else begin if (!m_type_names.exists(alias_type_name)) begin uvm_factory_override overrides[$]; m_type_names[alias_type_name] = original_type; overrides = {m_type_overrides, m_inst_overrides}; foreach (overrides[index]) begin if(m_matches_type_pair(.match_type_pair(overrides[index].orig), .requested_type(null), .requested_type_name(alias_type_name))) begin overrides[index].orig.m_type = original_type; end if(m_matches_type_pair(.match_type_pair(overrides[index].ovrd), .requested_type(null), .requested_type_name(alias_type_name))) begin overrides[index].ovrd.m_type = original_type; end end end end endfunction function void uvm_default_factory::set_inst_alias(string alias_type_name, uvm_object_wrapper original_type, string full_inst_path); string original_type_name; m_inst_typename_alias_t orig_type_alias_per_inst; original_type_name = original_type.get_type_name(); if (!is_type_registered(original_type)) uvm_report_warning("BDTYP",{"Cannot define alias of type '", original_type_name,"' because it is not registered with the factory."}, UVM_NONE); else begin orig_type_alias_per_inst.alias_type_name = alias_type_name; orig_type_alias_per_inst.full_inst_path = full_inst_path; orig_type_alias_per_inst.orig.m_type_name = original_type_name; orig_type_alias_per_inst.orig.m_type = original_type; m_inst_aliases.push_back(orig_type_alias_per_inst); end endfunction function uvm_object uvm_default_factory::create_object_by_name (string requested_type_name, string parent_inst_path="", string name=""); uvm_object_wrapper wrapper; string inst_path; if (parent_inst_path == "") inst_path = name; else if (name != "") inst_path = {parent_inst_path,".",name}; else inst_path = parent_inst_path; m_override_info.delete(); wrapper = find_override_by_name(requested_type_name, inst_path); if (wrapper==null) begin wrapper = m_resolve_type_name_by_inst(requested_type_name,inst_path); if(wrapper == null) begin uvm_report_warning("BDTYP",{"Cannot create an object of type '", requested_type_name,"' because it is not registered with the factory."}, UVM_NONE); return null; end end return wrapper.create_object(name); endfunction function uvm_object uvm_default_factory::create_object_by_type (uvm_object_wrapper requested_type, string parent_inst_path="", string name=""); string full_inst_path; if (parent_inst_path == "") full_inst_path = name; else if (name != "") full_inst_path = {parent_inst_path,".",name}; else full_inst_path = parent_inst_path; m_override_info.delete(); requested_type = find_override_by_type(requested_type, full_inst_path); return requested_type.create_object(name); endfunction function bit uvm_default_factory::is_type_name_registered (string type_name); return (m_type_names.exists(type_name)); endfunction function bit uvm_default_factory::is_type_registered (uvm_object_wrapper obj); return (m_types.exists(obj)); endfunction function uvm_component uvm_default_factory::create_component_by_name (string requested_type_name, string parent_inst_path="", string name, uvm_component parent); uvm_object_wrapper wrapper; string inst_path; if (parent_inst_path == "") inst_path = name; else if (name != "") inst_path = {parent_inst_path,".",name}; else inst_path = parent_inst_path; m_override_info.delete(); wrapper = find_override_by_name(requested_type_name, inst_path); if (wrapper == null) begin if(!m_type_names.exists(requested_type_name)) begin uvm_report_warning("BDTYP",{"Cannot create a component of type '", requested_type_name,"' because it is not registered with the factory."}, UVM_NONE); return null; end wrapper = m_type_names[requested_type_name]; end return wrapper.create_component(name, parent); endfunction function uvm_component uvm_default_factory::create_component_by_type (uvm_object_wrapper requested_type, string parent_inst_path="", string name, uvm_component parent); string full_inst_path; if (parent_inst_path == "") full_inst_path = name; else if (name != "") full_inst_path = {parent_inst_path,".",name}; else full_inst_path = parent_inst_path; m_override_info.delete(); requested_type = find_override_by_type(requested_type, full_inst_path); return requested_type.create_component(name, parent); endfunction function uvm_object_wrapper uvm_default_factory::find_wrapper_by_name(string type_name); uvm_object_wrapper wrapper = m_resolve_type_name(type_name); if (wrapper != null) return wrapper; uvm_report_warning("UnknownTypeName", {"find_wrapper_by_name: Type name '",type_name, "' not registered with the factory."}, UVM_NONE); endfunction function uvm_object_wrapper uvm_default_factory::find_override_by_name (string requested_type_name, string full_inst_path); uvm_object_wrapper rtype; uvm_factory_override lindex; rtype = m_resolve_type_name_by_inst(requested_type_name,full_inst_path); if(full_inst_path != "") begin foreach(m_inst_overrides[i]) begin if(m_matches_inst_override(.override(m_inst_overrides[i]), .requested_type(rtype), .requested_type_name(requested_type_name), .full_inst_path(full_inst_path))) begin m_override_info.push_back(m_inst_overrides[i]); if (lindex == null) begin lindex = m_inst_overrides[i]; if (!m_debug_pass) begin break; end end end end end if ((lindex == null) || m_debug_pass) begin uvm_factory_override matched_overrides[$]; foreach (m_type_overrides[index]) begin if(m_matches_type_override(.override(m_type_overrides[index]), .requested_type(rtype), .requested_type_name(requested_type_name), .full_inst_path(full_inst_path), .resolve_null_type_by_inst(1))) begin matched_overrides.push_back(m_type_overrides[index]); if ((lindex == null) || (lindex.replace == 0)) begin lindex = m_type_overrides[index]; if (!m_debug_pass && lindex.replace) begin break; end end end end if(matched_overrides.size() != 0) begin if (m_debug_pass) begin m_override_info = {m_override_info,matched_overrides}; end else begin m_override_info.push_back(matched_overrides[$]); end end end if (lindex != null) begin uvm_object_wrapper override = lindex.ovrd.m_type; lindex.used++; if (m_debug_pass) begin lindex.selected = 1; end if(!m_matches_type_override(.override(lindex), .requested_type(rtype), .requested_type_name(requested_type_name), .full_inst_path(full_inst_path), .match_original_type(0), .resolve_null_type_by_inst(1))) begin if(override == null) begin override = find_override_by_name(lindex.ovrd.m_type_name,full_inst_path); end else begin override = find_override_by_type(override,full_inst_path); end end else if(override == null) begin override = m_resolve_type_name_by_inst(lindex.ovrd.m_type_name,full_inst_path); end if(override == null) begin uvm_report_error("TYPNTF", {"Cannot resolve override for original type '", lindex.orig.m_type_name,"' because the override type '", lindex.ovrd.m_type_name, "' is not registered with the factory."}, UVM_NONE); end return override; end return null; endfunction function uvm_object_wrapper uvm_default_factory::find_override_by_type(uvm_object_wrapper requested_type, string full_inst_path); uvm_object_wrapper override; uvm_factory_override lindex; uvm_factory_queue_class qc; foreach (m_override_info[index]) begin if ( m_override_info[index].orig.m_type == requested_type) begin uvm_report_error("OVRDLOOP", "Recursive loop detected while finding override.", UVM_NONE); m_override_info[index].used++; if (!m_debug_pass) debug_create_by_type (requested_type, full_inst_path); return requested_type; end end if(full_inst_path != "") begin foreach(m_inst_overrides[i]) begin if(m_matches_inst_override(.override(m_inst_overrides[i]), .requested_type(requested_type), .requested_type_name(requested_type.get_type_name()), .full_inst_path(full_inst_path))) begin m_override_info.push_back(m_inst_overrides[i]); if (lindex == null) begin lindex = m_inst_overrides[i]; if (!m_debug_pass) begin break; end end end end end if ((lindex == null) || m_debug_pass) begin uvm_factory_override matched_overrides[$]; foreach (m_type_overrides[index]) begin if(m_matches_type_override(.override(m_type_overrides[index]), .requested_type(requested_type), .requested_type_name(requested_type.get_type_name()), .full_inst_path(full_inst_path), .resolve_null_type_by_inst(1))) begin matched_overrides.push_back(m_type_overrides[index]); if ((lindex == null) || (lindex.replace == 0)) begin lindex = m_type_overrides[index]; if (!m_debug_pass && lindex.replace) begin break; end end end end if(matched_overrides.size() != 0) begin if (m_debug_pass) begin m_override_info = {m_override_info,matched_overrides}; end else begin m_override_info.push_back(matched_overrides[$]); end end end if (lindex != null) begin uvm_object_wrapper override = lindex.ovrd.m_type; lindex.used++; if (m_debug_pass) begin lindex.selected = 1; end if(!m_matches_type_override(.override(lindex), .requested_type(requested_type), .requested_type_name(requested_type.get_type_name()), .full_inst_path(full_inst_path), .match_original_type(0), .resolve_null_type_by_inst(1))) begin if(override == null) begin override = find_override_by_name(lindex.ovrd.m_type_name,full_inst_path); end else begin override = find_override_by_type(override,full_inst_path); end end else if(override == null) begin override = m_resolve_type_name_by_inst(lindex.ovrd.m_type_name,full_inst_path); end if(override == null) begin uvm_report_error("TYPNTF", {"Cannot resolve override for original type '", lindex.orig.m_type_name,"' because the override type '", lindex.ovrd.m_type_name, "' is not registered with the factory."}, UVM_NONE); end return override; end return requested_type; endfunction function void uvm_default_factory::print (int all_types=1); string key; string qs[$]; qs.push_back("\n#### Factory Configuration (*)\n\n"); if(!m_type_overrides.size() && !m_inst_overrides.size()) qs.push_back(" No instance or type overrides are registered with this factory\n"); else begin int max1,max2,max3; string dash = "---------------------------------------------------------------------------------------------------"; string space= " "; if(!m_inst_overrides.size()) qs.push_back("No instance overrides are registered with this factory\n"); else begin foreach(m_inst_overrides[j]) begin if (m_inst_overrides[j].orig.m_type_name.len() > max1) max1=m_inst_overrides[j].orig.m_type_name.len(); if (m_inst_overrides[j].full_inst_path.len() > max2) max2=m_inst_overrides[j].full_inst_path.len(); if (m_inst_overrides[j].ovrd.m_type_name.len() > max3) max3=m_inst_overrides[j].ovrd.m_type_name.len(); end if (max1 < 14) max1 = 14; if (max2 < 13) max2 = 13; if (max3 < 13) max3 = 13; qs.push_back("Instance Overrides:\n\n"); qs.push_back($sformatf(" %0s%0s %0s%0s %0s%0s\n","Requested Type",space.substr(1,max1-14), "Override Path", space.substr(1,max2-13), "Override Type", space.substr(1,max3-13))); qs.push_back($sformatf(" %0s %0s %0s\n",dash.substr(1,max1), dash.substr(1,max2), dash.substr(1,max3))); foreach(m_inst_overrides[j]) begin qs.push_back($sformatf(" %0s%0s %0s%0s",m_inst_overrides[j].orig.m_type_name, space.substr(1,max1-m_inst_overrides[j].orig.m_type_name.len()), m_inst_overrides[j].full_inst_path, space.substr(1,max2-m_inst_overrides[j].full_inst_path.len()))); qs.push_back($sformatf(" %0s\n", m_inst_overrides[j].ovrd.m_type_name)); end end if (!m_type_overrides.size()) qs.push_back("\nNo type overrides are registered with this factory\n"); else begin if (max1 < 14) max1 = 14; if (max2 < 13) max2 = 13; if (max3 < 13) max3 = 13; foreach (m_type_overrides[i]) begin if (m_type_overrides[i].orig.m_type_name.len() > max1) max1=m_type_overrides[i].orig.m_type_name.len(); if (m_type_overrides[i].ovrd.m_type_name.len() > max2) max2=m_type_overrides[i].ovrd.m_type_name.len(); end if (max1 < 14) max1 = 14; if (max2 < 13) max2 = 13; qs.push_back("\nType Overrides:\n\n"); qs.push_back($sformatf(" %0s%0s %0s%0s\n","Requested Type",space.substr(1,max1-14), "Override Type", space.substr(1,max2-13))); qs.push_back($sformatf(" %0s %0s\n",dash.substr(1,max1), dash.substr(1,max2))); for (int index=m_type_overrides.size()-1; index>=0; index--) qs.push_back($sformatf(" %0s%0s %0s\n", m_type_overrides[index].orig.m_type_name, space.substr(1,max1-m_type_overrides[index].orig.m_type_name.len()), m_type_overrides[index].ovrd.m_type_name)); end end if (all_types >= 1 && m_type_names.first(key)) begin bit banner; qs.push_back($sformatf("\nAll types registered with the factory: %0d total\n",m_types.num())); do begin if (!(all_types < 2 && uvm_is_match("uvm_*", m_type_names[key].get_type_name())) && key == m_type_names[key].get_type_name()) begin if (!banner) begin qs.push_back(" Type Name\n"); qs.push_back(" ---------\n"); banner=1; end qs.push_back($sformatf(" %s\n", m_type_names[key].get_type_name())); end end while(m_type_names.next(key)); end qs.push_back("(*) Types with no associated type name will be printed as \n\n####\n\n"); begin if (uvm_report_enabled(UVM_NONE,UVM_INFO,"UVM/FACTORY/PRINT")) uvm_report_info ("UVM/FACTORY/PRINT", uvm_pkg::m_uvm_string_queue_join(qs), UVM_NONE, "t/uvm/src/base/uvm_factory.svh", 1875, "", 1); end endfunction function void uvm_default_factory::debug_create_by_name (string requested_type_name, string parent_inst_path="", string name=""); m_debug_create(requested_type_name, null, parent_inst_path, name); endfunction function void uvm_default_factory::debug_create_by_type (uvm_object_wrapper requested_type, string parent_inst_path="", string name=""); m_debug_create("", requested_type, parent_inst_path, name); endfunction function void uvm_default_factory::m_debug_create (string requested_type_name, uvm_object_wrapper requested_type, string parent_inst_path, string name); string full_inst_path; uvm_object_wrapper result; if (parent_inst_path == "") full_inst_path = name; else if (name != "") full_inst_path = {parent_inst_path,".",name}; else full_inst_path = parent_inst_path; m_override_info.delete(); if (requested_type == null) begin if (!m_type_names.exists(requested_type_name) && !m_lookup_strs.exists(requested_type_name)) begin uvm_report_warning("Factory Warning", {"The factory does not recognize '", requested_type_name,"' as a registered type."}, UVM_NONE); return; end m_debug_pass = 1; result = find_override_by_name(requested_type_name,full_inst_path); end else begin m_debug_pass = 1; if (!m_types.exists(requested_type)) register(requested_type); result = find_override_by_type(requested_type,full_inst_path); if (requested_type_name == "") requested_type_name = requested_type.get_type_name(); end m_debug_display(requested_type_name, result, full_inst_path); m_debug_pass = 0; foreach (m_override_info[index]) m_override_info[index].selected = 0; endfunction function void uvm_default_factory::m_debug_display (string requested_type_name, uvm_object_wrapper result, string full_inst_path); int max1,max2,max3; string dash = "---------------------------------------------------------------------------------------------------"; string space= " "; string qs[$]; qs.push_back("\n#### Factory Override Information (*)\n\n"); qs.push_back( $sformatf("Given a request for an object of type '%s' with an instance\npath of '%s' the factory encountered\n\n", requested_type_name,full_inst_path)); if (m_override_info.size() == 0) qs.push_back("no relevant overrides.\n\n"); else begin qs.push_back("the following relevant overrides. An 'x' next to a match indicates a\nmatch that was ignored.\n\n"); foreach (m_override_info[i]) begin if (m_override_info[i].orig.m_type_name.len() > max1) max1=m_override_info[i].orig.m_type_name.len(); if (m_override_info[i].full_inst_path.len() > max2) max2=m_override_info[i].full_inst_path.len(); if (m_override_info[i].ovrd.m_type_name.len() > max3) max3=m_override_info[i].ovrd.m_type_name.len(); end if (max1 < 13) max1 = 13; if (max2 < 13) max2 = 13; if (max3 < 13) max3 = 13; qs.push_back($sformatf("Original Type%0s Instance Path%0s Override Type%0s\n", space.substr(1,max1-13),space.substr(1,max2-13),space.substr(1,max3-13))); qs.push_back($sformatf(" %0s %0s %0s\n",dash.substr(1,max1), dash.substr(1,max2), dash.substr(1,max3))); foreach (m_override_info[i]) begin qs.push_back($sformatf("%s%0s%0s\n", m_override_info[i].selected ? " " : "x ", m_override_info[i].orig.m_type_name, space.substr(1,max1-m_override_info[i].orig.m_type_name.len()))); qs.push_back($sformatf(" %0s%0s", m_override_info[i].full_inst_path, space.substr(1,max2-m_override_info[i].full_inst_path.len()))); qs.push_back($sformatf(" %0s%0s", m_override_info[i].ovrd.m_type_name, space.substr(1,max3-m_override_info[i].ovrd.m_type_name.len()))); if (m_override_info[i].full_inst_path == "*") qs.push_back(" "); else qs.push_back("\n"); end qs.push_back("\n"); end qs.push_back("Result:\n\n"); qs.push_back($sformatf(" The factory will produce an object of type '%0s'\n", result == null ? requested_type_name : result.get_type_name())); qs.push_back("\n(*) Types with no associated type name will be printed as \n\n####\n\n"); begin if (uvm_report_enabled(UVM_NONE,UVM_INFO,"UVM/FACTORY/DUMP")) uvm_report_info ("UVM/FACTORY/DUMP", uvm_pkg::m_uvm_string_queue_join(qs), UVM_NONE, "t/uvm/src/base/uvm_factory.svh", 2015, "", 1); end endfunction function uvm_object_wrapper uvm_default_factory::m_resolve_type_name(string requested_type_name); uvm_object_wrapper wrapper=null; if(m_type_names.exists(requested_type_name)) wrapper = m_type_names[requested_type_name]; return wrapper; endfunction function uvm_object_wrapper uvm_default_factory::m_resolve_type_name_by_inst(string requested_type_name, string full_inst_path); uvm_object_wrapper wrapper=null; m_inst_typename_alias_t type_alias_inst[$]; type_alias_inst = m_inst_aliases.find(i) with ((i.alias_type_name == requested_type_name) && uvm_is_match(i.full_inst_path,full_inst_path)); if (type_alias_inst.size() > 0) begin wrapper = type_alias_inst[0].orig.m_type; end else begin wrapper = m_resolve_type_name(requested_type_name); end return wrapper; endfunction function bit uvm_default_factory::m_matches_type_pair(m_uvm_factory_type_pair_t match_type_pair, uvm_object_wrapper requested_type, string requested_type_name); return ((match_type_pair.m_type != null) && (match_type_pair.m_type == requested_type) || (match_type_pair.m_type_name != "" && match_type_pair.m_type_name != "" && match_type_pair.m_type_name == requested_type_name)); endfunction function bit uvm_default_factory::m_matches_inst_override(uvm_factory_override override, uvm_object_wrapper requested_type, string requested_type_name, string full_inst_path=""); m_uvm_factory_type_pair_t match_type_pair = override.orig ; if(match_type_pair.m_type == null) begin match_type_pair.m_type = m_resolve_type_name_by_inst(match_type_pair.m_type_name, full_inst_path); end if (m_matches_type_pair(.match_type_pair(match_type_pair), .requested_type(requested_type), .requested_type_name(requested_type_name))) begin if(override.has_wildcard) begin return (override.full_inst_path == "*" || uvm_is_match(override.full_inst_path,full_inst_path)); end else begin return (override.full_inst_path == full_inst_path); end end return 0; endfunction function bit uvm_default_factory::m_matches_type_override(uvm_factory_override override, uvm_object_wrapper requested_type, string requested_type_name, string full_inst_path="", bit match_original_type = 1, bit resolve_null_type_by_inst=0); m_uvm_factory_type_pair_t match_type_pair = match_original_type ? override.orig : override.ovrd; if(match_type_pair.m_type == null) begin if(resolve_null_type_by_inst) begin match_type_pair.m_type = m_resolve_type_name_by_inst(match_type_pair.m_type_name,full_inst_path); end else begin match_type_pair.m_type = m_resolve_type_name(match_type_pair.m_type_name); end end return m_matches_type_pair(.match_type_pair(match_type_pair), .requested_type(requested_type), .requested_type_name(requested_type_name)); endfunction `define UVM_REGISTRY_SVH typedef class uvm_registry_common; typedef class uvm_registry_component_creator; typedef class uvm_registry_object_creator; class uvm_component_registry #(type T=uvm_component, string Tname="") extends uvm_object_wrapper; typedef uvm_component_registry #(T,Tname) this_type; typedef uvm_registry_common#( this_type, uvm_registry_component_creator, T, Tname ) common_type; virtual function uvm_component create_component (string name, uvm_component parent); T obj; obj = new(name, parent); return obj; endfunction static function string type_name(); return common_type::type_name(); endfunction : type_name virtual function string get_type_name(); common_type common = common_type::get(); return common.get_type_name(); endfunction static function this_type get(); static this_type m_inst; if (m_inst == null) m_inst = new(); return m_inst; endfunction virtual function void initialize(); common_type common = common_type::get(); common.initialize(); endfunction static function T create(string name, uvm_component parent, string contxt=""); return common_type::create( name, parent, contxt ); endfunction static function void set_type_override (uvm_object_wrapper override_type, bit replace=1); common_type::set_type_override( override_type, replace ); endfunction static function void set_inst_override(uvm_object_wrapper override_type, string inst_path, uvm_component parent=null); common_type::set_inst_override( override_type, inst_path, parent ); endfunction static function bit set_type_alias(string alias_name); common_type::set_type_alias( alias_name ); return 1; endfunction endclass class uvm_object_registry #(type T=uvm_object, string Tname="") extends uvm_object_wrapper; typedef uvm_object_registry #(T,Tname) this_type; typedef uvm_registry_common#( this_type, uvm_registry_object_creator, T, Tname ) common_type; virtual function uvm_object create_object(string name=""); T obj; if (name=="") obj = new(); else obj = new(name); return obj; endfunction static function string type_name(); return common_type::type_name(); endfunction : type_name virtual function string get_type_name(); common_type common = common_type::get(); return common.get_type_name(); endfunction static function this_type get(); static this_type m_inst; if (m_inst == null) m_inst = new(); return m_inst; endfunction static function T create (string name="", uvm_component parent=null, string contxt=""); return common_type::create( name, parent, contxt ); endfunction static function void set_type_override (uvm_object_wrapper override_type, bit replace=1); common_type::set_type_override( override_type, replace ); endfunction static function void set_inst_override(uvm_object_wrapper override_type, string inst_path, uvm_component parent=null); common_type::set_inst_override( override_type, inst_path, parent ); endfunction static function bit set_type_alias(string alias_name); common_type::set_type_alias( alias_name ); return 1; endfunction virtual function void initialize(); common_type common = common_type::get(); common.initialize(); endfunction endclass class uvm_abstract_component_registry #(type T=uvm_component, string Tname="") extends uvm_object_wrapper; typedef uvm_abstract_component_registry #(T,Tname) this_type; typedef uvm_registry_common#( this_type, uvm_registry_component_creator, T, Tname ) common_type; virtual function uvm_component create_component (string name, uvm_component parent); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/ABST_RGTRY/CREATE_ABSTRACT_CMPNT")) uvm_report_error ("UVM/ABST_RGTRY/CREATE_ABSTRACT_CMPNT", $sformatf( "Cannot create an instance of abstract class %s (with name %s and parent %s). Check for missing factory overrides for %s.", this.get_type_name(), name, parent.get_full_name(), this.get_type_name() ), UVM_NONE, "t/uvm/src/base/uvm_registry.svh", 308, "", 1); end return null; endfunction static function string type_name(); return common_type::type_name(); endfunction : type_name virtual function string get_type_name(); common_type common = common_type::get(); return common.get_type_name(); endfunction static function this_type get(); static this_type m_inst; if (m_inst == null) m_inst = new(); return m_inst; endfunction static function T create(string name, uvm_component parent, string contxt=""); return common_type::create( name, parent, contxt ); endfunction static function void set_type_override (uvm_object_wrapper override_type, bit replace=1); common_type::set_type_override( override_type, replace ); endfunction static function void set_inst_override(uvm_object_wrapper override_type, string inst_path, uvm_component parent=null); common_type::set_inst_override( override_type, inst_path, parent ); endfunction static function bit set_type_alias(string alias_name); common_type::set_type_alias( alias_name ); return 1; endfunction virtual function void initialize(); common_type common = common_type::get(); common.initialize(); endfunction endclass class uvm_abstract_object_registry #(type T=uvm_object, string Tname="") extends uvm_object_wrapper; typedef uvm_abstract_object_registry #(T,Tname) this_type; typedef uvm_registry_common#( this_type, uvm_registry_object_creator, T, Tname ) common_type; virtual function uvm_object create_object(string name=""); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/ABST_RGTRY/CREATE_ABSTRACT_OBJ")) uvm_report_error ("UVM/ABST_RGTRY/CREATE_ABSTRACT_OBJ", $sformatf( "Cannot create an instance of abstract class %s (with name %s). Check for missing factory overrides for %s.", this.get_type_name(), name, this.get_type_name() ), UVM_NONE, "t/uvm/src/base/uvm_registry.svh", 428, "", 1); end return null; endfunction static function string type_name(); return common_type::type_name(); endfunction : type_name virtual function string get_type_name(); common_type common = common_type::get(); return common.get_type_name(); endfunction static function this_type get(); static this_type m_inst; if (m_inst == null) m_inst = new(); return m_inst; endfunction static function T create (string name="", uvm_component parent=null, string contxt=""); return common_type::create( name, parent, contxt ); endfunction static function void set_type_override (uvm_object_wrapper override_type, bit replace=1); common_type::set_type_override( override_type, replace ); endfunction static function void set_inst_override(uvm_object_wrapper override_type, string inst_path, uvm_component parent=null); common_type::set_inst_override( override_type, inst_path, parent ); endfunction static function bit set_type_alias(string alias_name); common_type::set_type_alias( alias_name ); return 1; endfunction virtual function void initialize(); common_type common = common_type::get(); common.initialize(); endfunction endclass class uvm_registry_common #( type Tregistry=int, type Tcreator=int, type Tcreated=int, string Tname="" ); typedef uvm_registry_common#(Tregistry,Tcreator,Tcreated,Tname) this_type; local static string m__type_aliases[$]; static function string type_name(); if((Tname == "") && (m__type_aliases.size() != 0)) begin return m__type_aliases[0]; end return Tname; endfunction : type_name virtual function string get_type_name(); return type_name(); endfunction static function this_type get(); static this_type m_inst; if (m_inst == null) m_inst = new(); return m_inst; endfunction : get static function Tcreated create(string name, uvm_component parent, string contxt); uvm_object obj; if (contxt == "" && parent != null) contxt = parent.get_full_name(); obj = Tcreator::create_by_type( Tregistry::get(), contxt, name, parent ); if (!$cast(create, obj)) begin string msg; msg = {"Factory did not return a ", Tcreator::base_type_name(), " of type '",Tregistry::type_name, "'. A component of type '",obj == null ? "null" : obj.get_type_name(), "' was returned instead. Name=",name," Parent=", parent==null?"null":parent.get_type_name()," contxt=",contxt}; uvm_report_fatal("FCTTYP", msg, UVM_NONE); end endfunction static function void set_type_override (uvm_object_wrapper override_type, bit replace); uvm_factory factory=uvm_factory::get(); factory.set_type_override_by_type(Tregistry::get(),override_type,replace); endfunction static function void set_inst_override(uvm_object_wrapper override_type, string inst_path, uvm_component parent); string full_inst_path; uvm_factory factory=uvm_factory::get(); if (parent != null) begin if (inst_path == "") inst_path = parent.get_full_name(); else inst_path = {parent.get_full_name(),".",inst_path}; end factory.set_inst_override_by_type(Tregistry::get(),override_type,inst_path); endfunction static function void set_type_alias(string alias_name); m__type_aliases.push_back(alias_name); m__type_aliases.sort(); if (uvm_pkg::get_core_state() != UVM_CORE_UNINITIALIZED) begin uvm_factory factory = uvm_factory::get(); Tregistry rgtry = Tregistry::get(); if (factory.is_type_registered(rgtry)) begin factory.set_type_alias(alias_name,rgtry); end end endfunction static function bit __deferred_init(); Tregistry rgtry = Tregistry::get(); if (uvm_pkg::get_core_state() == UVM_CORE_UNINITIALIZED) begin uvm_pkg::uvm_deferred_init.push_back(rgtry); end else begin rgtry.initialize(); end return 1; endfunction local static bit m__initialized=__deferred_init(); virtual function void initialize(); uvm_factory factory =uvm_factory::get(); Tregistry rgtry = Tregistry::get(); factory.register(rgtry); foreach(m__type_aliases[i]) begin factory.set_type_alias(m__type_aliases[i],rgtry); end endfunction endclass virtual class uvm_registry_component_creator; static function uvm_component create_by_type( uvm_object_wrapper obj_wrpr, string contxt, string name, uvm_component parent ); uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory factory = cs.get_factory(); return factory.create_component_by_type( obj_wrpr, contxt, name, parent ); endfunction static function string base_type_name(); return "component"; endfunction endclass virtual class uvm_registry_object_creator; static function uvm_object create_by_type( uvm_object_wrapper obj_wrpr, string contxt, string name, uvm_object unused ); uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory factory = cs.get_factory(); unused = unused; return factory.create_object_by_type( obj_wrpr, contxt, name ); endfunction static function string base_type_name(); return "object"; endfunction endclass class uvm_pool #(type KEY=int, T=uvm_void) extends uvm_object; typedef uvm_pool #(KEY,T) this_type; static protected this_type m_global_pool; protected T pool[KEY]; typedef uvm_object_registry #(uvm_pool #(KEY,T)) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_pool #(KEY,T) tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_pool"; endfunction : type_name virtual function string get_type_name(); return "uvm_pool"; endfunction : get_type_name function new (string name=""); super.new(name); endfunction static function this_type get_global_pool (); if (m_global_pool==null) m_global_pool = new("pool"); return m_global_pool; endfunction static function T get_global (KEY key); this_type gpool; gpool = get_global_pool(); return gpool.get(key); endfunction virtual function T get (KEY key); if (!pool.exists(key)) begin T default_value; pool[key] = default_value; end return pool[key]; endfunction virtual function void add (KEY key, T item); pool[key] = item; endfunction virtual function int num (); return pool.num(); endfunction virtual function void delete (KEY key); if (!exists(key)) begin uvm_report_warning("POOLDEL", $sformatf("delete: pool key doesn't exist. Ignoring delete request")); return; end pool.delete(key); endfunction virtual function int exists (KEY key); return pool.exists(key); endfunction virtual function int first (ref KEY key); return pool.first(key); endfunction virtual function int last (ref KEY key); return pool.last(key); endfunction virtual function int next (ref KEY key); return pool.next(key); endfunction virtual function int prev (ref KEY key); return pool.prev(key); endfunction virtual function void do_copy (uvm_object rhs); this_type p; KEY key; super.do_copy(rhs); if (rhs==null || !$cast(p, rhs)) return; pool = p.pool; endfunction virtual function void do_print (uvm_printer printer); string v; int cnt; string item; KEY key; printer.print_array_header("pool",pool.num(),"aa_object_string"); if (pool.first(key)) do begin item.itoa(cnt); item = {"[-key",item,"--]"}; $swrite(v,pool[key]); printer.print_generic(item,"",-1,v,"["); end while (pool.next(key)); printer.print_array_footer(); endfunction endclass class uvm_object_string_pool #(type T=uvm_object) extends uvm_pool #(string,T); typedef uvm_object_string_pool #(T) this_type; static protected this_type m_global_pool; typedef uvm_object_registry #(uvm_object_string_pool#(T)) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_object_string_pool#(T) tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_obj_str_pool"; endfunction : type_name virtual function string get_type_name(); return "uvm_obj_str_pool"; endfunction : get_type_name function new (string name=""); super.new(name); endfunction static function this_type get_global_pool (); if (m_global_pool==null) m_global_pool = new("global_pool"); return m_global_pool; endfunction static function T get_global (string key); this_type gpool; gpool = get_global_pool(); return gpool.get(key); endfunction virtual function T get (string key); if (!pool.exists(key)) pool[key] = new (key); return pool[key]; endfunction virtual function void delete (string key); if (!exists(key)) begin uvm_report_warning("POOLDEL", $sformatf("delete: key '%s' doesn't exist", key)); return; end pool.delete(key); endfunction virtual function void do_print (uvm_printer printer); string key; printer.print_array_header("pool",pool.num(),"aa_object_string"); if (pool.first(key)) do printer.print_object({"[",key,"]"}, pool[key],"["); while (pool.next(key)); printer.print_array_footer(); endfunction endclass typedef class uvm_barrier; typedef class uvm_event; typedef uvm_object_string_pool #(uvm_barrier) uvm_barrier_pool ; typedef uvm_object_string_pool #(uvm_event#(uvm_object)) uvm_event_pool ; `define UVM_QUEUE_SVH class uvm_queue #(type T=int) extends uvm_object; typedef uvm_queue #(T) this_type; typedef uvm_object_registry #(uvm_queue#(T)) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_queue#(T) tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_queue"; endfunction : type_name virtual function string get_type_name(); return "uvm_queue"; endfunction : get_type_name static local this_type m_global_queue; protected T queue[$]; function new (string name=""); super.new(name); endfunction static function this_type get_global_queue (); if (m_global_queue==null) m_global_queue = new("global_queue"); return m_global_queue; endfunction static function T get_global (int index); this_type gqueue; gqueue = get_global_queue(); return gqueue.get(index); endfunction virtual function T get (int index); T default_value; if (index >= size() || index < 0) begin uvm_report_warning("QUEUEGET", $sformatf("get: given index out of range for queue of size %0d. Ignoring get request",size())); return default_value; end return queue[index]; endfunction virtual function int size (); return queue.size(); endfunction virtual function void insert (int index, T item); if (index >= size() || index < 0) begin uvm_report_warning("QUEUEINS", $sformatf("insert: given index out of range for queue of size %0d. Ignoring insert request",size())); return; end queue.insert(index,item); endfunction virtual function void delete (int index=-1); if (index >= size() || index < -1) begin uvm_report_warning("QUEUEDEL", $sformatf("delete: given index out of range for queue of size %0d. Ignoring delete request",size())); return; end if (index == -1) queue.delete(); else queue.delete(index); endfunction virtual function T pop_front(); return queue.pop_front(); endfunction virtual function T pop_back(); return queue.pop_back(); endfunction virtual function void push_front(T item); queue.push_front(item); endfunction virtual function void push_back(T item); queue.push_back(item); endfunction virtual task wait_until_not_empty(); wait(queue.size() > 0); endtask virtual function void do_copy (uvm_object rhs); this_type p; super.do_copy(rhs); if (rhs == null || !$cast(p, rhs)) return; queue = p.queue; endfunction virtual function string convert2string(); return $sformatf("%p",queue); endfunction endclass class uvm_spell_chkr #(type T=int); typedef T tab_t[string]; static const int unsigned max = '1; static function bit check ( ref tab_t strtab, input string s); string key; int distance; int unsigned min; string min_key[$]; if(strtab.exists(s)) begin return 1; end min = max; foreach(strtab[key]) begin distance = levenshtein_distance(key, s); if(distance < 0) continue; if(distance < min) begin min = distance; min_key.delete(); min_key.push_back(key); continue; end if(distance == min) begin min_key.push_back(key); end end if(min == max) begin begin if (uvm_report_enabled(UVM_NONE,UVM_INFO,"UVM/CONFIGDB/SPELLCHK")) uvm_report_info ("UVM/CONFIGDB/SPELLCHK", $sformatf("%s not located, no alternatives to suggest", s), UVM_NONE, "t/uvm/src/base/uvm_spell_chkr.svh", 110, "", 1); end end else begin string q[$]; foreach(min_key[i]) begin q.push_back(min_key[i]); q.push_back("|"); end if(q.size()) void'(q.pop_back()); begin if (uvm_report_enabled(UVM_NONE,UVM_INFO,"UVM/CONFIGDB/SPELLCHK")) uvm_report_info ("UVM/CONFIGDB/SPELLCHK", $sformatf("%s not located, did you mean %s", s, uvm_pkg::m_uvm_string_queue_join(q)), UVM_NONE, "t/uvm/src/base/uvm_spell_chkr.svh", 124, "", 1); end end return 0; endfunction static local function int levenshtein_distance(string s, string t); int k, i, j, n, m, cost, distance; int d[]; n = s.len() + 1; m = t.len() + 1; if(n == 1 || m == 1) return -1; d = new[m*n]; for(k = 0; k < n; k++) d[k] = k; for(k = 0; k < m; k++) d[k*n] = k; for(i = 1; i < n; i++) begin for(j = 1; j < m; j++) begin cost = !(s[i-1] == t[j-1]); d[j*n+i] = minimum(d[(j-1)*n+i]+1, d[j*n+i-1]+1, d[(j-1)*n+i-1]+cost); end end distance = d[n*m-1]; return distance; endfunction static local function int minimum(int a, int b, int c); int min = a; if(b < min) min = b; if(c < min) min = c; return min; endfunction endclass typedef class uvm_resource_base; class uvm_resource_types; typedef bit[1:0] override_t; typedef enum override_t { TYPE_OVERRIDE = 2'b01, NAME_OVERRIDE = 2'b10 } override_e; typedef uvm_queue#(uvm_resource_base) rsrc_q_t; typedef enum { PRI_HIGH, PRI_LOW } priority_e; typedef struct { time read_time; time write_time; int unsigned read_count; int unsigned write_count; } access_t; endclass class uvm_resource_options; static local bit auditing = 1; static function void turn_on_auditing(); auditing = 1; endfunction static function void turn_off_auditing(); auditing = 0; endfunction static function bit is_auditing(); return auditing; endfunction endclass virtual class uvm_resource_base extends uvm_object; protected bit modified; protected bit read_only; uvm_resource_types::access_t access[string]; function new(string name = ""); super.new(name); modified = 0; read_only = 0; endfunction pure virtual function uvm_resource_base get_type_handle(); function void set_read_only(); read_only = 1; endfunction function void set_read_write(); read_only = 0; endfunction function bit is_read_only(); return read_only; endfunction task wait_modified(); wait (modified == 1); modified = 0; endtask function string convert2string(); return $sformatf("(%s) %s", m_value_type_name(), m_value_as_string()); endfunction pure virtual function string m_value_type_name(); pure virtual function string m_value_as_string(); function void do_print(uvm_printer printer); super.do_print(printer); printer.print_generic_element("val", m_value_type_name(), "", m_value_as_string()); endfunction : do_print function void record_read_access(uvm_object accessor = null); string str; uvm_resource_types::access_t access_record; if(!uvm_resource_options::is_auditing()) return; if(accessor != null) str = accessor.get_full_name(); else str = ""; if(access.exists(str)) access_record = access[str]; else init_access_record(access_record); access_record.read_count++; access_record.read_time = $realtime; access[str] = access_record; endfunction function void record_write_access(uvm_object accessor = null); string str; if(uvm_resource_options::is_auditing()) begin if(accessor != null) begin uvm_resource_types::access_t access_record; string str; str = accessor.get_full_name(); if(access.exists(str)) access_record = access[str]; else init_access_record(access_record); access_record.write_count++; access_record.write_time = $realtime; access[str] = access_record; end end endfunction virtual function void print_accessors(); string str; uvm_component comp; uvm_resource_types::access_t access_record; string qs[$]; if(access.num() == 0) return; foreach (access[i]) begin str = i; access_record = access[str]; qs.push_back($sformatf("%s reads: %0d @ %0t writes: %0d @ %0t\n",str, access_record.read_count, access_record.read_time, access_record.write_count, access_record.write_time)); end begin if (uvm_report_enabled(UVM_NONE,UVM_INFO,"UVM/RESOURCE/ACCESSOR")) uvm_report_info ("UVM/RESOURCE/ACCESSOR", uvm_pkg::m_uvm_string_queue_join(qs), UVM_NONE, "t/uvm/src/base/uvm_resource_base.svh", 532, "", 1); end endfunction function void init_access_record (inout uvm_resource_types::access_t access_record); access_record.read_time = 0; access_record.write_time = 0; access_record.read_count = 0; access_record.write_count = 0; endfunction endclass class get_t; string name; string scope; uvm_resource_base rsrc; time t; endclass typedef class uvm_tree_printer ; class uvm_resource_pool; uvm_resource_types::rsrc_q_t rtab [string]; uvm_resource_types::rsrc_q_t ttab [uvm_resource_base]; typedef struct { string scope ; int unsigned precedence; } rsrc_info_t ; static rsrc_info_t ri_tab [uvm_resource_base]; get_t get_record [$]; function new(); endfunction static function uvm_resource_pool get(); uvm_resource_pool t_rp; uvm_coreservice_t cs = uvm_coreservice_t::get(); t_rp = cs.get_resource_pool(); return t_rp; endfunction function bit spell_check(string s); return uvm_spell_chkr#(uvm_resource_types::rsrc_q_t)::check(rtab, s); endfunction function void set_scope (uvm_resource_base rsrc, string scope); uvm_resource_types::rsrc_q_t rq; string name; uvm_resource_base type_handle; uvm_resource_base r; int unsigned i; if(rsrc == null) begin uvm_report_warning("NULLRASRC", "attempting to set scope of a null resource"); return; end name = rsrc.get_name(); if ((name != "") && rtab.exists(name)) begin rq = rtab[name]; for(i = 0; i < rq.size(); i++) begin r = rq.get(i); if(r == rsrc) begin ri_tab[rsrc].scope = uvm_glob_to_re(scope); return ; end end end if (rq == null) rq = new(name); rq.push_back(rsrc); rtab[name] = rq; type_handle = rsrc.get_type_handle(); if(ttab.exists(type_handle)) rq = ttab[type_handle]; else rq = new(); rq.push_back(rsrc); ttab[type_handle] = rq; ri_tab[rsrc].scope = uvm_glob_to_re(scope); ri_tab[rsrc].precedence = get_default_precedence(); endfunction function void set_override(uvm_resource_base rsrc, string scope = ""); string s = scope; set_scope(rsrc, s); set_priority(rsrc, uvm_resource_types::PRI_HIGH); endfunction function void set_name_override(uvm_resource_base rsrc, string scope = ""); string s = scope; set_scope(rsrc, s); set_priority_name(rsrc, uvm_resource_types::PRI_HIGH); endfunction function void set_type_override(uvm_resource_base rsrc, string scope = ""); string s = scope; set_scope(rsrc, s); set_priority_type(rsrc, uvm_resource_types::PRI_HIGH); endfunction virtual function bit get_scope(uvm_resource_base rsrc, output string scope); uvm_resource_types::rsrc_q_t rq; string name; uvm_resource_base r; int unsigned i; if(rsrc == null) return 0; name = rsrc.get_name(); if((name != "") && rtab.exists(name)) begin rq = rtab[name]; for(i = 0; i < rq.size(); i++) begin r = rq.get(i); if(r == rsrc) begin scope = ri_tab[rsrc].scope; return 1; end end end scope = ""; return 0; endfunction virtual function void delete ( uvm_resource_base rsrc ); string name; uvm_resource_base type_handle; if (rsrc != null) begin name = rsrc.get_name(); if(name != "") begin if(rtab.exists(name)) rtab.delete(name); end type_handle = rsrc.get_type_handle(); if(ttab.exists(type_handle)) begin int q_size = ttab[type_handle].size(); if (q_size == 1) ttab.delete(type_handle); else begin int i; for (i=0; i prec) begin rsrc = r; prec = c_prec; end end return rsrc; endfunction static function void sort_by_precedence(ref uvm_resource_types::rsrc_q_t q); uvm_resource_types::rsrc_q_t all[int]; uvm_resource_base r; int unsigned prec; for(int i=0; i", scope, null); return null; end rsrc = q.get(0); push_get_record("", scope, rsrc); return rsrc; endfunction function uvm_resource_types::rsrc_q_t lookup_regex_names(string scope, string name, uvm_resource_base type_handle = null); return lookup_name(scope, name, type_handle, 0); endfunction function uvm_resource_types::rsrc_q_t lookup_regex(string re, scope); uvm_resource_types::rsrc_q_t rq; uvm_resource_types::rsrc_q_t result_q; int unsigned i; uvm_resource_base r; string s; result_q = new(); foreach (rtab[name]) begin if ( ! uvm_is_match(re, name) ) continue; rq = rtab[name]; for(i = 0; i < rq.size(); i++) begin r = rq.get(i); if(ri_tab.exists(r) && uvm_is_match(ri_tab[r].scope, scope)) result_q.push_back(r); end end return result_q; endfunction function uvm_resource_types::rsrc_q_t lookup_scope(string scope); uvm_resource_types::rsrc_q_t rq; uvm_resource_base r; int unsigned i; int unsigned err; uvm_resource_types::rsrc_q_t q = new(); string name; if(rtab.last(name)) begin do begin rq = rtab[name]; for(int i = 0; i < rq.size(); ++i) begin r = rq.get(i); if(ri_tab.exists(r) && uvm_is_match(ri_tab[r].scope, scope)) begin q.push_back(r); end end end while(rtab.prev(name)); end return q; endfunction local function void set_priority_queue(uvm_resource_base rsrc, ref uvm_resource_types::rsrc_q_t q, uvm_resource_types::priority_e pri); uvm_resource_base r; int unsigned i; string msg; string name = rsrc.get_name(); for(i = 0; i < q.size(); i++) begin r = q.get(i); if(r == rsrc) break; end if(r != rsrc) begin $sformat(msg, "Handle for resource named %s is not in the name name; cannot change its priority", name); uvm_report_error("NORSRC", msg); return; end q.delete(i); case(pri) uvm_resource_types::PRI_HIGH: q.push_front(rsrc); uvm_resource_types::PRI_LOW: q.push_back(rsrc); endcase endfunction function void set_priority_type(uvm_resource_base rsrc, uvm_resource_types::priority_e pri); uvm_resource_base type_handle; string msg; uvm_resource_types::rsrc_q_t q; if(rsrc == null) begin uvm_report_warning("NULLRASRC", "attempting to change the serach priority of a null resource"); return; end type_handle = rsrc.get_type_handle(); if(!ttab.exists(type_handle)) begin $sformat(msg, "Type handle for resrouce named %s not found in type map; cannot change its search priority", rsrc.get_name()); uvm_report_error("RNFTYPE", msg); return; end q = ttab[type_handle]; set_priority_queue(rsrc, q, pri); endfunction function void set_priority_name(uvm_resource_base rsrc, uvm_resource_types::priority_e pri); string name; string msg; uvm_resource_types::rsrc_q_t q; if(rsrc == null) begin uvm_report_warning("NULLRASRC", "attempting to change the serach priority of a null resource"); return; end name = rsrc.get_name(); if(!rtab.exists(name)) begin $sformat(msg, "Resrouce named %s not found in name map; cannot change its search priority", name); uvm_report_error("RNFNAME", msg); return; end q = rtab[name]; set_priority_queue(rsrc, q, pri); endfunction function void set_priority (uvm_resource_base rsrc, uvm_resource_types::priority_e pri); set_priority_type(rsrc, pri); set_priority_name(rsrc, pri); endfunction static function void set_default_precedence( int unsigned precedence); uvm_coreservice_t cs = uvm_coreservice_t::get(); cs.set_resource_pool_default_precedence(precedence); endfunction static function int unsigned get_default_precedence(); uvm_coreservice_t cs = uvm_coreservice_t::get(); return cs.get_resource_pool_default_precedence(); endfunction virtual function void set_precedence(uvm_resource_base r, int unsigned p=uvm_resource_pool::get_default_precedence()); uvm_resource_types::rsrc_q_t q; string name; int unsigned i; uvm_resource_base rsrc; if(r == null) begin uvm_report_warning("NULLRASRC", "attempting to set precedence of a null resource"); return; end name = r.get_name(); if(rtab.exists(name)) begin q = rtab[name]; for(i = 0; i < q.size(); i++) begin rsrc = q.get(i); if(rsrc == r) break; end end if(r != rsrc) begin uvm_report_warning("NORSRC", $sformatf("resource named %s is not placed within the pool", name)); return; end ri_tab[r].precedence = p; endfunction virtual function int unsigned get_precedence(uvm_resource_base r); uvm_resource_types::rsrc_q_t q; string name; int unsigned i; uvm_resource_base rsrc; if(r == null) begin uvm_report_warning("NULLRASRC", "attempting to get precedence of a null resource"); return uvm_resource_pool::get_default_precedence(); end name = r.get_name(); if(rtab.exists(name)) begin q = rtab[name]; for(i = 0; i < q.size(); i++) begin rsrc = q.get(i); if(rsrc == r) break; end end if(r != rsrc) begin uvm_report_warning("NORSRC", $sformatf("resource named %s is not placed within the pool", name)); return uvm_resource_pool::get_default_precedence(); end return ri_tab[r].precedence; endfunction function void m_print_resources(uvm_printer printer, uvm_resource_types::rsrc_q_t rq, bit audit = 0); printer.push_element(rq.get_name(), "uvm_queue#(uvm_resource_base)", $sformatf("%0d",rq.size()), uvm_object_value_str(rq)); for(int i=0; i"); else m_print_resources(printer, rq, audit); begin if (uvm_report_enabled(UVM_NONE,UVM_INFO,"UVM/RESOURCE_POOL/PRINT_QUEUE")) uvm_report_info ("UVM/RESOURCE_POOL/PRINT_QUEUE", printer.emit(), UVM_NONE, "t/uvm/src/base/uvm_resource.svh", 1071, "", 1); end endfunction function void dump(bit audit = 0, uvm_printer printer = null); string name; static uvm_tree_printer m_printer; if (m_printer == null) begin m_printer = new(); m_printer.set_type_name_enabled(1); end if (printer == null) printer = m_printer; printer.flush(); printer.push_element("uvm_resource_pool", "", $sformatf("%0d",rtab.size()), ""); foreach (rtab[name]) begin m_print_resources(printer, rtab[name], audit); end printer.pop_element(); begin if (uvm_report_enabled(UVM_NONE,UVM_INFO,"UVM/RESOURCE/DUMP")) uvm_report_info ("UVM/RESOURCE/DUMP", printer.emit(), UVM_NONE, "t/uvm/src/base/uvm_resource.svh", 1108, "", 1); end endfunction endclass class uvm_resource #(type T=int) extends uvm_resource_base; typedef uvm_resource#(T) this_type; static this_type my_type = get_type(); protected T val; typedef uvm_object_registry#(this_type) type_id; virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction : get_object_type virtual function uvm_object create (string name=""); this_type tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction : create static function string type_name(); return $sformatf("uvm_resource#(%s)", $typename(T)); endfunction : type_name virtual function string get_type_name(); return $sformatf("uvm_resource#(%s)", $typename(T)); endfunction : get_type_name function new(string name=""); super.new(name); endfunction virtual function string m_value_type_name(); return $typename(T); endfunction : m_value_type_name virtual function string m_value_as_string(); return $sformatf("%0p", val); endfunction : m_value_as_string static function this_type get_type(); if(my_type == null) my_type = new(); return my_type; endfunction function uvm_resource_base get_type_handle(); return get_type(); endfunction function T read(uvm_object accessor = null); record_read_access(accessor); return val; endfunction function void write(T t, uvm_object accessor = null); if(is_read_only()) begin uvm_report_error("resource", $sformatf("resource %s is read only -- cannot modify", get_name())); return; end if(val == t) return; record_write_access(accessor); val = t; modified = 1; endfunction static function this_type get_highest_precedence(ref uvm_resource_types::rsrc_q_t q); this_type rsrc; this_type r; uvm_resource_types::rsrc_q_t tq; uvm_resource_base rb; uvm_resource_pool rp = uvm_resource_pool::get(); if(q.size() == 0) return null; tq = new(); rsrc = null; for(int i = 0; i < q.size(); ++i) begin if($cast(r, q.get(i))) begin tq.push_back(r) ; end end rb = rp.get_highest_precedence(tq); if (!$cast(rsrc, rb)) return null; return rsrc; endfunction endclass `define UVM_RESOURCE_GET_FCNS(base_type) \ static function this_subtype get_by_name(string scope, string name, bit rpterr = 1); \ this_subtype t; \ uvm_resource_base b = uvm_resource#(base_type)::get_by_name(scope, name, rpterr); \ if(!$cast(t, b)) \ `uvm_fatal("BADCAST", "cannot cast resource to resource subtype") \ return t; \ endfunction \ \ static function this_subtype get_by_type(string scope = "", \ uvm_resource_base type_handle); \ this_subtype t; \ uvm_resource_base b = uvm_resource#(base_type)::get_by_type(scope, type_handle); \ if(!$cast(t, b)) \ `uvm_fatal("BADCAST", "cannot cast resource to resource subtype") \ return t; \ endfunction class uvm_int_rsrc extends uvm_resource #(int); typedef uvm_int_rsrc this_subtype; function new(string name, string s = "*"); uvm_resource_pool rp; super.new(name); rp = uvm_resource_pool::get(); rp.set_scope(this, s); endfunction function string convert2string(); string s; $sformat(s, "%0d", read()); return s; endfunction endclass class uvm_string_rsrc extends uvm_resource #(string); typedef uvm_string_rsrc this_subtype; function new(string name, string s = "*"); uvm_resource_pool rp; super.new(name); rp = uvm_resource_pool::get(); rp.set_scope(this, s); endfunction function string convert2string(); return read(); endfunction endclass class uvm_obj_rsrc extends uvm_resource #(uvm_object); typedef uvm_obj_rsrc this_subtype; function new(string name, string s = "*"); uvm_resource_pool rp; super.new(name); rp = uvm_resource_pool::get(); rp.set_scope(this, s); endfunction endclass class uvm_bit_rsrc #(int unsigned N=1) extends uvm_resource #(bit[N-1:0]); typedef uvm_bit_rsrc#(N) this_subtype; function new(string name, string s = "*"); uvm_resource_pool rp; super.new(name); rp = uvm_resource_pool::get(); rp.set_scope(this, s); endfunction function string convert2string(); string s; $sformat(s, "%0b", read()); return s; endfunction endclass class uvm_byte_rsrc #(int unsigned N=1) extends uvm_resource #(bit[7:0][N-1:0]); typedef uvm_byte_rsrc#(N) this_subtype; function new(string name, string s = "*"); uvm_resource_pool rp; super.new(name); rp = uvm_resource_pool::get(); rp.set_scope(this, s); endfunction function string convert2string(); string s; $sformat(s, "%0x", read()); return s; endfunction endclass typedef class uvm_resource_db_options; typedef class uvm_cmdline_processor; class uvm_resource_db #(type T=uvm_object); typedef uvm_resource #(T) rsrc_t; protected function new(); endfunction static function rsrc_t get_by_type(string scope); uvm_resource_pool rp = uvm_resource_pool::get(); uvm_resource_base rsrc_base; rsrc_t rsrc; string msg; uvm_resource_base type_handle = rsrc_t::get_type(); if(type_handle == null) return null; rsrc_base = rp.get_by_type(scope, type_handle); if(!$cast(rsrc, rsrc_base)) begin $sformat(msg, "Resource with specified type handle in scope %s was not located", scope); begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RSRCNF")) uvm_report_warning ("RSRCNF", msg, UVM_NONE, "t/uvm/src/base/uvm_resource_db.svh", 84, "", 1); end return null; end return rsrc; endfunction static function rsrc_t get_by_name(string scope, string name, bit rpterr=1); uvm_resource_pool rp = uvm_resource_pool::get(); uvm_resource_base rsrc_base; rsrc_t rsrc; string msg; rsrc_base = rp.get_by_name(scope, name, rsrc_t::get_type(), rpterr); if(rsrc_base == null) return null; if(!$cast(rsrc, rsrc_base)) begin if(rpterr) begin $sformat(msg, "Resource with name %s in scope %s has incorrect type", name, scope); begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RSRCTYPE")) uvm_report_warning ("RSRCTYPE", msg, UVM_NONE, "t/uvm/src/base/uvm_resource_db.svh", 115, "", 1); end end return null; end return rsrc; endfunction static function rsrc_t set_default(string scope, string name); rsrc_t r; uvm_resource_pool rp = uvm_resource_pool::get(); r = new(name); rp.set_scope(r, scope); return r; endfunction protected static function void m_show_msg( input string id, input string rtype, input string action, input string scope, input string name, input uvm_object accessor, input rsrc_t rsrc); T foo; string msg=$typename(foo); $sformat(msg, "%s scope='%s' name='%s' (type %s) %s accessor=%s = %s", rtype,scope,name, msg,action, (accessor != null) ? accessor.get_full_name() : "", rsrc==null?"null (failed lookup)":rsrc.convert2string()); begin if (uvm_report_enabled(UVM_LOW,UVM_INFO,id)) uvm_report_info (id, msg, UVM_LOW, "t/uvm/src/base/uvm_resource_db.svh", 161, "", 1); end endfunction static function void set(input string scope, input string name, T val, input uvm_object accessor = null); uvm_resource_pool rp = uvm_resource_pool::get(); rsrc_t rsrc = new(name); rsrc.write(val, accessor); rp.set_scope(rsrc, scope); if(uvm_resource_db_options::is_tracing()) m_show_msg("RSRCDB/SET", "Resource","set", scope, name, accessor, rsrc); endfunction static function void set_anonymous(input string scope, T val, input uvm_object accessor = null); uvm_resource_pool rp = uvm_resource_pool::get(); rsrc_t rsrc = new(""); rsrc.write(val, accessor); rp.set_scope(rsrc, scope); if(uvm_resource_db_options::is_tracing()) m_show_msg("RSRCDB/SETANON","Resource", "set", scope, "", accessor, rsrc); endfunction static function void set_override(input string scope, input string name, T val, uvm_object accessor = null); uvm_resource_pool rp = uvm_resource_pool::get(); rsrc_t rsrc = new(name); rsrc.write(val, accessor); rp.set_override(rsrc, scope); if(uvm_resource_db_options::is_tracing()) m_show_msg("RSRCDB/SETOVRD", "Resource","set", scope, name, accessor, rsrc); endfunction static function void set_override_type(input string scope, input string name, T val, uvm_object accessor = null); uvm_resource_pool rp = uvm_resource_pool::get(); rsrc_t rsrc = new(name); rsrc.write(val, accessor); rp.set_type_override(rsrc, scope); if(uvm_resource_db_options::is_tracing()) m_show_msg("RSRCDB/SETOVRDTYP","Resource", "set", scope, name, accessor, rsrc); endfunction static function void set_override_name(input string scope, input string name, T val, uvm_object accessor = null); uvm_resource_pool rp = uvm_resource_pool::get(); rsrc_t rsrc = new(name); rsrc.write(val, accessor); rp.set_name_override(rsrc, scope); if(uvm_resource_db_options::is_tracing()) m_show_msg("RSRCDB/SETOVRDNAM","Resource", "set", scope, name, accessor, rsrc); endfunction static function bit read_by_name(input string scope, input string name, inout T val, input uvm_object accessor = null); rsrc_t rsrc = get_by_name(scope, name); if(uvm_resource_db_options::is_tracing()) m_show_msg("RSRCDB/RDBYNAM","Resource", "read", scope, name, accessor, rsrc); if(rsrc == null) return 0; val = rsrc.read(accessor); return 1; endfunction static function bit read_by_type(input string scope, inout T val, input uvm_object accessor = null); rsrc_t rsrc = get_by_type(scope); if(uvm_resource_db_options::is_tracing()) m_show_msg("RSRCDB/RDBYTYP", "Resource","read", scope, "", accessor, rsrc); if(rsrc == null) return 0; val = rsrc.read(accessor); return 1; endfunction static function bit write_by_name(input string scope, input string name, input T val, input uvm_object accessor = null); rsrc_t rsrc = get_by_name(scope, name); if(uvm_resource_db_options::is_tracing()) m_show_msg("RSRCDB/WR","Resource", "written", scope, name, accessor, rsrc); if(rsrc == null) return 0; rsrc.write(val, accessor); return 1; endfunction static function bit write_by_type(input string scope, input T val, input uvm_object accessor = null); rsrc_t rsrc = get_by_type(scope); if(uvm_resource_db_options::is_tracing()) m_show_msg("RSRCDB/WRTYP", "Resource","written", scope, "", accessor, rsrc); if(rsrc == null) return 0; rsrc.write(val, accessor); return 1; endfunction static function void dump(); uvm_resource_pool rp = uvm_resource_pool::get(); rp.dump(); endfunction endclass class uvm_resource_db_options; static local bit ready; static local bit tracing; static function void turn_on_tracing(); if (!ready) init(); tracing = 1; endfunction static function void turn_off_tracing(); if (!ready) init(); tracing = 0; endfunction static function bit is_tracing(); if (!ready) init(); return tracing; endfunction static local function void init(); uvm_cmdline_processor clp; string trace_args[$]; clp = uvm_cmdline_processor::get_inst(); if (clp.get_arg_matches("+UVM_RESOURCE_DB_TRACE", trace_args)) begin tracing = 1; end ready = 1; endfunction endclass typedef class uvm_phase; class m_uvm_waiter; string inst_name; string field_name; event trigger; function new (string inst_name, string field_name); this.inst_name = inst_name; this.field_name = field_name; endfunction endclass typedef class uvm_root; typedef class uvm_config_db_options; class uvm_config_db#(type T=int) extends uvm_resource_db#(T); static uvm_pool#(string,uvm_resource#(T)) m_rsc[uvm_component]; static local uvm_queue#(m_uvm_waiter) m_waiters[string]; static function bit get(uvm_component cntxt, string inst_name, string field_name, inout T value); uvm_resource#(T) r; uvm_resource_pool rp = uvm_resource_pool::get(); uvm_resource_types::rsrc_q_t rq; uvm_coreservice_t cs = uvm_coreservice_t::get(); if(cntxt == null) cntxt = cs.get_root(); if(inst_name == "") inst_name = cntxt.get_full_name(); else if(cntxt.get_full_name() != "") inst_name = {cntxt.get_full_name(), ".", inst_name}; rq = rp.lookup_regex_names(inst_name, field_name, uvm_resource#(T)::get_type()); r = uvm_resource#(T)::get_highest_precedence(rq); if(uvm_config_db_options::is_tracing()) m_show_msg("CFGDB/GET", "Configuration","read", inst_name, field_name, cntxt, r); if(r == null) return 0; value = r.read(cntxt); return 1; endfunction static function void set(uvm_component cntxt, string inst_name, string field_name, T value); uvm_root top; uvm_phase curr_phase; uvm_resource#(T) r; bit exists; string lookup; uvm_pool#(string,uvm_resource#(T)) pool; string rstate; uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_resource_pool rp = cs.get_resource_pool(); int unsigned precedence; process p = process::self(); if(p != null) rstate = p.get_randstate(); top = cs.get_root(); curr_phase = top.m_current_phase; if(cntxt == null) cntxt = top; if(inst_name == "") inst_name = cntxt.get_full_name(); else if(cntxt.get_full_name() != "") inst_name = {cntxt.get_full_name(), ".", inst_name}; if(!m_rsc.exists(cntxt)) begin m_rsc[cntxt] = new; end pool = m_rsc[cntxt]; lookup = {inst_name, "__M_UVM__", field_name}; if(!pool.exists(lookup)) begin r = new(field_name); rp.set_scope(r, inst_name); pool.add(lookup, r); end else begin r = pool.get(lookup); exists = 1; end if(curr_phase != null && curr_phase.get_name() == "build") precedence = cs.get_resource_pool_default_precedence() - (cntxt.get_depth()); else precedence = cs.get_resource_pool_default_precedence(); rp.set_precedence(r, precedence); r.write(value, cntxt); rp.set_priority_name(r, uvm_resource_types::PRI_HIGH); if(m_waiters.exists(field_name)) begin m_uvm_waiter w; for(int i=0; iw.trigger; end end if(p != null) p.set_randstate(rstate); if(uvm_config_db_options::is_tracing()) m_show_msg("CFGDB/SET", "Configuration","set", inst_name, field_name, cntxt, r); endfunction static function bit exists(uvm_component cntxt, string inst_name, string field_name, bit spell_chk=0); uvm_coreservice_t cs = uvm_coreservice_t::get(); if(cntxt == null) cntxt = cs.get_root(); if(inst_name == "") inst_name = cntxt.get_full_name(); else if(cntxt.get_full_name() != "") inst_name = {cntxt.get_full_name(), ".", inst_name}; return (uvm_resource_db#(T)::get_by_name(inst_name,field_name,spell_chk) != null); endfunction static task wait_modified(uvm_component cntxt, string inst_name, string field_name); process p = process::self(); string rstate = p.get_randstate(); m_uvm_waiter waiter; uvm_coreservice_t cs = uvm_coreservice_t::get(); if(cntxt == null) cntxt = cs.get_root(); if(cntxt != cs.get_root()) begin if(inst_name != "") inst_name = {cntxt.get_full_name(),".",inst_name}; else inst_name = cntxt.get_full_name(); end waiter = new(inst_name, field_name); if(!m_waiters.exists(field_name)) m_waiters[field_name] = new; m_waiters[field_name].push_back(waiter); p.set_randstate(rstate); @waiter.trigger; for(int i=0; i 1) begin string msg_queue[$]; msg_queue.push_back("("); foreach (matching_ops[i]) begin msg_queue.push_back(matching_ops[i]); if (i != matching_ops.size() - 1) msg_queue.push_back(","); end msg_queue.push_back(")"); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/FIELD_OP/SET_BAD_OP_TYPE")) uvm_report_error ("UVM/FIELD_OP/SET_BAD_OP_TYPE", {"set() was passed op_type matching multiple operations: ", uvm_pkg::m_uvm_string_queue_join(msg_queue)}, UVM_NONE, "t/uvm/src/base/uvm_field_op.svh", 88, "", 1); end end if(m_is_set == 0) begin m_op_type = op_type; m_policy = policy; m_object = rhs; m_is_set = 1'b1; end else begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/FIELD_OP/SET")) uvm_report_error ("UVM/FIELD_OP/SET", "Attempting to set values in policy without flushing", UVM_NONE, "t/uvm/src/base/uvm_field_op.svh", 98, "", 1); end endfunction virtual function string get_op_name(); case(m_op_type) UVM_COPY : return "copy"; UVM_COMPARE : return "compare"; UVM_PRINT : return "print"; UVM_RECORD : return "record"; UVM_PACK : return "pack"; UVM_UNPACK : return "unpack"; UVM_SET : return "set"; default: return ""; endcase endfunction virtual function uvm_field_flag_t get_op_type(); if(m_is_set == 1'b1) return m_op_type; else begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/FIELD_OP/GET_OP_TYPE")) uvm_report_error ("UVM/FIELD_OP/GET_OP_TYPE", "Calling get_op_type() before calling set() is not allowed", UVM_NONE, "t/uvm/src/base/uvm_field_op.svh", 120, "", 1); end endfunction virtual function uvm_policy get_policy(); if(m_is_set == 1'b1) return m_policy; else begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/FIELD_OP/GET_POLICY")) uvm_report_error ("UVM/FIELD_OP/GET_POLICY", "Attempting to call get_policy() before calling set() is not allowed", UVM_NONE, "t/uvm/src/base/uvm_field_op.svh", 129, "", 1); end endfunction virtual function uvm_object get_rhs(); if(m_is_set == 1'b1) return m_object; else begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/FIELD_OP/GET_RHS")) uvm_report_error ("UVM/FIELD_OP/GET_RHS", "Calling get_rhs() before calling set() is not allowed", UVM_NONE, "t/uvm/src/base/uvm_field_op.svh", 137, "", 1); end endfunction function bit user_hook_enabled(); if(m_is_set == 1'b1) return m_user_hook; else begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/FIELD_OP/GET_USER_HOOK")) uvm_report_error ("UVM/FIELD_OP/GET_USER_HOOK", "Attempting to get_user_hook before calling set() is not allowed", UVM_NONE, "t/uvm/src/base/uvm_field_op.svh", 145, "", 1); end endfunction function void disable_user_hook(); m_user_hook = 1'b0; endfunction static uvm_field_op m_recycled_op[$] ; virtual function void flush(); m_policy = null; m_object = null; m_user_hook = 1'b1; m_is_set = 0; endfunction function void m_recycle(); this.flush(); m_recycled_op.push_back(this); endfunction : m_recycle static function uvm_field_op m_get_available_op() ; uvm_field_op field_op ; if (m_recycled_op.size() > 0) field_op = m_recycled_op.pop_back() ; else field_op = uvm_field_op::type_id::create("field_op"); return field_op ; endfunction endclass class uvm_copier extends uvm_policy; typedef uvm_object_registry#(uvm_copier,"uvm_copier") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_copier tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_copier"; endfunction : type_name virtual function string get_type_name(); return "uvm_copier"; endfunction : get_type_name uvm_recursion_policy_enum policy = UVM_DEFAULT_POLICY; function new(string name="uvm_copier") ; super.new(name); endfunction recursion_state_e m_recur_states[uvm_object ][uvm_object ][uvm_recursion_policy_enum ]; virtual function void copy_object ( uvm_object lhs, uvm_object rhs); uvm_field_op field_op; if (get_recursion_policy() == UVM_REFERENCE) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM_COPY_POLICY")) uvm_report_error ("UVM_COPY_POLICY", "Attempting to make a copy of a object which is a reference", UVM_NONE, "t/uvm/src/base/uvm_copier.svh", 82, "", 1); end return; end if (rhs == null || lhs == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM_COPY_NULL_OBJ")) uvm_report_error ("UVM_COPY_NULL_OBJ", "Attempting to make a copy of a object with null src/target", UVM_NONE, "t/uvm/src/base/uvm_copier.svh", 87, "", 1); end return; end push_active_object(lhs); m_recur_states[rhs][lhs][get_recursion_policy()] = uvm_policy::STARTED; field_op = uvm_field_op::m_get_available_op() ; field_op.set(UVM_COPY,this,rhs); lhs.do_execute_op(field_op); if (field_op.user_hook_enabled()) begin lhs.do_copy(rhs); end field_op.m_recycle(); m_recur_states[rhs][lhs][get_recursion_policy()] = uvm_policy::FINISHED; void'(pop_active_object()); endfunction virtual function recursion_state_e object_copied( uvm_object lhs, uvm_object rhs, uvm_recursion_policy_enum recursion ); if (!m_recur_states.exists(rhs)) return NEVER ; else if (!m_recur_states[rhs].exists(lhs)) return NEVER ; else if (!m_recur_states[rhs][lhs].exists(recursion)) return NEVER ; else begin return m_recur_states[rhs][lhs][recursion]; end endfunction function void flush(); m_recur_states.delete(); endfunction virtual function void set_recursion_policy (uvm_recursion_policy_enum policy); this.policy = policy; endfunction virtual function uvm_recursion_policy_enum get_recursion_policy(); return policy; endfunction function int unsigned get_num_copies(uvm_object rhs); if (m_recur_states.exists(rhs)) return m_recur_states[rhs].size(); return 0; endfunction : get_num_copies function int get_first_copy(uvm_object rhs, ref uvm_object lhs); if (m_recur_states.exists(rhs)) return m_recur_states[rhs].first(lhs); return 0; endfunction : get_first_copy function int get_next_copy(uvm_object rhs, ref uvm_object lhs); if (m_recur_states.exists(rhs)) return m_recur_states[rhs].next(lhs); return 0; endfunction : get_next_copy function int get_last_copy(uvm_object rhs, ref uvm_object lhs); if (m_recur_states.exists(rhs)) return m_recur_states[rhs].last(lhs); return 0; endfunction : get_last_copy function int get_prev_copy(uvm_object rhs, ref uvm_object lhs); if (m_recur_states.exists(rhs)) return m_recur_states[rhs].prev(lhs); return 0; endfunction : get_prev_copy static function void set_default (uvm_copier copier) ; uvm_coreservice_t coreservice ; coreservice = uvm_coreservice_t::get() ; coreservice.set_default_copier(copier) ; endfunction static function uvm_copier get_default () ; uvm_coreservice_t coreservice ; coreservice = uvm_coreservice_t::get() ; return coreservice.get_default_copier() ; endfunction endclass typedef class m_uvm_printer_knobs; typedef class uvm_printer_element; typedef class uvm_structure_proxy; virtual class uvm_printer extends uvm_policy; typedef uvm_abstract_object_registry#(uvm_printer,"uvm_printer") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_printer"; endfunction : type_name virtual function string get_type_name(); return "uvm_printer"; endfunction : get_type_name extern function new(string name="") ; bit m_flushed ; local m_uvm_printer_knobs knobs ; protected function m_uvm_printer_knobs get_knobs() ; return knobs; endfunction extern static function void set_default(uvm_printer printer) ; extern static function uvm_printer get_default() ; extern virtual function void print_field (string name, uvm_bitstream_t value, int size, uvm_radix_enum radix=UVM_NORADIX, byte scope_separator=".", string type_name=""); extern virtual function void print_field_int (string name, uvm_integral_t value, int size, uvm_radix_enum radix=UVM_NORADIX, byte scope_separator=".", string type_name=""); extern virtual function void print_object (string name, uvm_object value, byte scope_separator="."); extern virtual function void print_object_header (string name, uvm_object value, byte scope_separator="."); extern virtual function void print_string (string name, string value, byte scope_separator="."); uvm_policy::recursion_state_e m_recur_states[uvm_object][uvm_recursion_policy_enum ] ; extern virtual function uvm_policy::recursion_state_e object_printed ( uvm_object value, uvm_recursion_policy_enum recursion); extern virtual function void print_time (string name, time value, byte scope_separator="."); extern virtual function void print_real (string name, real value, byte scope_separator="."); extern virtual function void print_generic (string name, string type_name, int size, string value, byte scope_separator="."); extern virtual function void print_generic_element (string name, string type_name, string size, string value); extern virtual function string emit (); extern virtual function void flush (); extern virtual function void set_name_enabled (bit enabled); extern virtual function bit get_name_enabled (); extern virtual function void set_type_name_enabled (bit enabled); extern virtual function bit get_type_name_enabled (); extern virtual function void set_size_enabled (bit enabled); extern virtual function bit get_size_enabled (); extern virtual function void set_id_enabled (bit enabled); extern virtual function bit get_id_enabled (); extern virtual function void set_radix_enabled (bit enabled); extern virtual function bit get_radix_enabled (); extern virtual function void set_radix_string (uvm_radix_enum radix, string prefix); extern virtual function string get_radix_string (uvm_radix_enum radix); extern virtual function void set_default_radix (uvm_radix_enum radix); extern virtual function uvm_radix_enum get_default_radix (); extern virtual function void set_root_enabled (bit enabled); extern virtual function bit get_root_enabled (); extern virtual function void set_recursion_policy (uvm_recursion_policy_enum policy); extern virtual function uvm_recursion_policy_enum get_recursion_policy (); extern virtual function void set_max_depth (int depth); extern virtual function int get_max_depth (); extern virtual function void set_file (UVM_FILE fl); extern virtual function UVM_FILE get_file (); extern virtual function void set_line_prefix (string prefix); extern virtual function string get_line_prefix (); extern virtual function void set_begin_elements (int elements = 5); extern virtual function int get_begin_elements (); extern virtual function void set_end_elements (int elements = 5); extern virtual function int get_end_elements (); local uvm_printer_element m_element_stack[$] ; protected function int m_get_stack_size(); return m_element_stack.size(); endfunction extern protected virtual function uvm_printer_element get_bottom_element (); extern protected virtual function uvm_printer_element get_top_element (); extern virtual function void push_element ( string name, string type_name, string size, string value="" ); extern virtual function void pop_element (); extern function uvm_printer_element get_unused_element() ; uvm_printer_element m_recycled_elements[$]; extern virtual function void print_array_header(string name, int size, string arraytype="array", byte scope_separator="."); extern virtual function void print_array_range (int min, int max); extern virtual function void print_array_footer (int size = 0); extern function bit istop (); extern function string index_string (int index, string name=""); string m_string; endclass class uvm_printer_element extends uvm_object; extern function new (string name=""); extern virtual function void set (string element_name = "", string element_type_name = "", string element_size = "", string element_value = "" ); extern virtual function void set_element_name (string element_name); extern virtual function string get_element_name (); extern virtual function void set_element_type_name (string element_type_name); extern virtual function string get_element_type_name (); extern virtual function void set_element_size (string element_size); extern virtual function string get_element_size (); extern virtual function void set_element_value (string element_value); extern virtual function string get_element_value (); extern function void add_child(uvm_printer_element child) ; extern function void get_children(ref uvm_printer_element children[$], input bit recurse) ; extern function void clear_children() ; local string m_name ; local string m_type_name ; local string m_size ; local string m_value ; local uvm_printer_element m_children[$] ; endclass class uvm_printer_element_proxy extends uvm_structure_proxy#(uvm_printer_element); extern function new (string name=""); extern virtual function void get_immediate_children(uvm_printer_element s, ref uvm_printer_element children[$]); endclass : uvm_printer_element_proxy class uvm_table_printer extends uvm_printer; typedef uvm_object_registry#(uvm_table_printer,"uvm_table_printer") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_table_printer tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_table_printer"; endfunction : type_name virtual function string get_type_name(); return "uvm_table_printer"; endfunction : get_type_name extern function new(string name=""); extern virtual function string emit(); extern virtual function string m_emit_element(uvm_printer_element element, int unsigned level); local static uvm_table_printer m_default_table_printer ; local static string m_space ; extern static function void set_default(uvm_table_printer printer) ; extern static function uvm_table_printer get_default() ; extern virtual function void set_indent(int indent) ; extern virtual function int get_indent() ; extern virtual function void flush() ; protected int m_max_name=4; protected int m_max_type=4; protected int m_max_size=4; protected int m_max_value=5; extern virtual function void pop_element(); endclass class uvm_tree_printer extends uvm_printer; protected string m_newline = "\n"; protected string m_linefeed ; typedef uvm_object_registry#(uvm_tree_printer,"uvm_tree_printer") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_tree_printer tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_tree_printer"; endfunction : type_name virtual function string get_type_name(); return "uvm_tree_printer"; endfunction : get_type_name extern function new(string name=""); local static uvm_tree_printer m_default_tree_printer ; extern static function void set_default(uvm_tree_printer printer) ; extern static function uvm_tree_printer get_default() ; extern virtual function void set_indent(int indent) ; extern virtual function int get_indent() ; extern virtual function void set_separators(string separators) ; extern virtual function string get_separators() ; extern virtual function void flush() ; extern virtual function string emit(); extern virtual function string m_emit_element(uvm_printer_element element, int unsigned level); endclass class uvm_line_printer extends uvm_tree_printer; typedef uvm_object_registry#(uvm_line_printer,"uvm_line_printer") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_line_printer tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_line_printer"; endfunction : type_name virtual function string get_type_name(); return "uvm_line_printer"; endfunction : get_type_name extern function new(string name=""); local static uvm_line_printer m_default_line_printer ; extern static function void set_default(uvm_line_printer printer) ; extern static function uvm_line_printer get_default() ; extern virtual function void set_separators(string separators) ; extern virtual function string get_separators() ; extern virtual function void flush() ; endclass class m_uvm_printer_knobs; bit identifier = 1; bit type_name = 1; bit size = 1; int depth = -1; bit reference = 1; int begin_elements = 5; int end_elements = 5; string prefix = ""; int indent = 2; bit show_root = 0; int mcd = UVM_STDOUT; string separator = "{}"; bit show_radix = 1; uvm_radix_enum default_radix = UVM_HEX; string dec_radix = "'d"; string bin_radix = "'b"; string oct_radix = "'o"; string unsigned_radix = "'d"; string hex_radix = "'h"; uvm_recursion_policy_enum recursion_policy ; endclass function uvm_printer::new(string name=""); super.new(name); knobs = new ; flush(); endfunction function void uvm_printer::set_default(uvm_printer printer) ; uvm_coreservice_t coreservice ; coreservice = uvm_coreservice_t::get() ; coreservice.set_default_printer(printer) ; endfunction function uvm_printer uvm_printer::get_default() ; uvm_coreservice_t coreservice ; coreservice = uvm_coreservice_t::get() ; return coreservice.get_default_printer() ; endfunction function void uvm_printer::print_field (string name, uvm_bitstream_t value, int size, uvm_radix_enum radix=UVM_NORADIX, byte scope_separator=".", string type_name=""); string sz_str, val_str; if(type_name == "") begin if(radix == UVM_TIME) type_name ="time"; else if(radix == UVM_STRING) type_name ="string"; else type_name ="integral"; end sz_str.itoa(size); if(radix == UVM_NORADIX) radix = get_default_radix(); val_str = uvm_bitstream_to_string (value, size, radix, get_radix_string(radix)); name = uvm_leaf_scope(name,scope_separator); push_element(name,type_name,sz_str,val_str); pop_element() ; endfunction function void uvm_printer::print_field_int (string name, uvm_integral_t value, int size, uvm_radix_enum radix=UVM_NORADIX, byte scope_separator=".", string type_name=""); string sz_str, val_str; if(type_name == "") begin if(radix == UVM_TIME) type_name ="time"; else if(radix == UVM_STRING) type_name ="string"; else type_name ="integral"; end sz_str.itoa(size); if(radix == UVM_NORADIX) radix = get_default_radix(); val_str = uvm_integral_to_string (value, size, radix, get_radix_string(radix)); name = uvm_leaf_scope(name,scope_separator); push_element(name,type_name,sz_str,val_str); pop_element() ; endfunction function string uvm_printer::emit (); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"NO_OVERRIDE")) uvm_report_error ("NO_OVERRIDE", "emit() method not overridden in printer subtype", UVM_NONE, "t/uvm/src/base/uvm_printer.svh", 999, "", 1); end return ""; endfunction function void uvm_printer::flush (); uvm_printer_element element = get_bottom_element() ; uvm_printer_element all_descendent_elements[$] ; element = get_bottom_element() ; if (element != null) begin element.get_children(all_descendent_elements,1) ; foreach (all_descendent_elements[i]) begin m_recycled_elements.push_back(all_descendent_elements[i]) ; all_descendent_elements[i].clear_children() ; end element.clear_children(); m_recycled_elements.push_back(element) ; m_element_stack.delete() ; end m_recur_states.delete(); m_flushed = 1 ; endfunction function void uvm_printer::set_name_enabled (bit enabled); knobs.identifier = enabled ; endfunction function bit uvm_printer::get_name_enabled (); return knobs.identifier ; endfunction function void uvm_printer::set_type_name_enabled (bit enabled); knobs.type_name = enabled ; endfunction function bit uvm_printer::get_type_name_enabled (); return knobs.type_name ; endfunction function void uvm_printer::set_size_enabled (bit enabled); knobs.size = enabled ; endfunction function bit uvm_printer::get_size_enabled (); return knobs.size ; endfunction function void uvm_printer::set_id_enabled (bit enabled); knobs.reference = enabled ; endfunction function bit uvm_printer::get_id_enabled (); return knobs.reference ; endfunction function void uvm_printer::set_radix_enabled (bit enabled); knobs.show_radix = enabled ; endfunction function bit uvm_printer::get_radix_enabled (); return knobs.show_radix ; endfunction function void uvm_printer::set_radix_string (uvm_radix_enum radix, string prefix); if (radix == UVM_DEC) knobs.dec_radix = prefix ; else if (radix == UVM_BIN) knobs.bin_radix = prefix ; else if (radix == UVM_OCT) knobs.oct_radix = prefix ; else if (radix == UVM_UNSIGNED) knobs.unsigned_radix = prefix ; else if (radix == UVM_HEX) knobs.hex_radix = prefix ; else begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"PRINTER_UNKNOWN_RADIX")) uvm_report_warning ("PRINTER_UNKNOWN_RADIX", $sformatf("set_radix_string called with unsupported radix %s",radix), UVM_NONE, "t/uvm/src/base/uvm_printer.svh", 1065, "", 1); end endfunction function string uvm_printer::get_radix_string (uvm_radix_enum radix); if (radix == UVM_DEC) return knobs.dec_radix ; else if (radix == UVM_BIN) return knobs.bin_radix ; else if (radix == UVM_OCT) return knobs.oct_radix ; else if (radix == UVM_UNSIGNED) return knobs.unsigned_radix ; else if (radix == UVM_HEX) return knobs.hex_radix ; else return ""; endfunction function void uvm_printer::set_default_radix (uvm_radix_enum radix); knobs.default_radix = radix ; endfunction function uvm_radix_enum uvm_printer::get_default_radix (); return knobs.default_radix ; endfunction function void uvm_printer::set_root_enabled (bit enabled); knobs.show_root = enabled ; endfunction function bit uvm_printer::get_root_enabled (); return knobs.show_root ; endfunction function void uvm_printer::set_recursion_policy (uvm_recursion_policy_enum policy); knobs.recursion_policy = policy ; endfunction function uvm_recursion_policy_enum uvm_printer::get_recursion_policy (); return knobs.recursion_policy ; endfunction function void uvm_printer::set_max_depth (int depth); knobs.depth = depth ; endfunction function int uvm_printer::get_max_depth (); return knobs.depth ; endfunction function void uvm_printer::set_file (UVM_FILE fl); knobs.mcd = fl ; endfunction function UVM_FILE uvm_printer::get_file (); return knobs.mcd ; endfunction function void uvm_printer::set_line_prefix (string prefix); knobs.prefix = prefix ; endfunction function string uvm_printer::get_line_prefix (); return knobs.prefix ; endfunction function void uvm_printer::set_begin_elements (int elements = 5); knobs.begin_elements = elements ; endfunction function int uvm_printer::get_begin_elements (); return knobs.begin_elements ; endfunction function void uvm_printer::set_end_elements (int elements = 5); knobs.end_elements = elements ; endfunction function int uvm_printer::get_end_elements (); return knobs.end_elements ; endfunction function uvm_printer_element uvm_printer::get_bottom_element (); if (m_element_stack.size() > 0) return m_element_stack[0] ; else return null ; endfunction function uvm_printer_element uvm_printer::get_top_element (); if (m_element_stack.size() > 0) return m_element_stack[$] ; else return null ; endfunction function uvm_printer_element_proxy::new (string name=""); super.new(name) ; endfunction function void uvm_printer_element_proxy::get_immediate_children(uvm_printer_element s, ref uvm_printer_element children[$]); s.get_children(children,0) ; endfunction function void uvm_printer::push_element ( string name, string type_name, string size, string value=""); uvm_printer_element element ; uvm_printer_element parent ; element = get_unused_element() ; parent = get_top_element() ; element.set(name,type_name,size,value); if (parent != null) parent.add_child(element) ; m_element_stack.push_back(element) ; endfunction function void uvm_printer::pop_element (); if (m_element_stack.size() > 1) begin void'(m_element_stack.pop_back()); end endfunction function uvm_printer_element uvm_printer::get_unused_element() ; uvm_printer_element element ; if (m_recycled_elements.size() > 0) begin element = m_recycled_elements.pop_back() ; end else begin element = new() ; end return element ; endfunction function void uvm_printer::print_array_header (string name, int size, string arraytype="array", byte scope_separator="."); push_element(name,arraytype,$sformatf("%0d",size),"-"); endfunction function void uvm_printer::print_array_footer (int size=0); pop_element() ; endfunction function void uvm_printer::print_array_range(int min, int max); string tmpstr; if(min == -1 && max == -1) return; if(min == -1) min = max; if(max == -1) max = min; if(max < min) return; print_generic_element("...", "...", "...", "..."); endfunction function void uvm_printer::print_object_header (string name, uvm_object value, byte scope_separator="."); if(name == "") name = ""; push_element(name, (value != null) ? value.get_type_name() : "object", "-", get_id_enabled() ? uvm_object_value_str(value) : "-"); endfunction function void uvm_printer::print_object (string name, uvm_object value, byte scope_separator="."); uvm_component comp, child_comp; uvm_field_op field_op ; uvm_recursion_policy_enum recursion_policy; recursion_policy = get_recursion_policy(); if ((value == null) || (recursion_policy == UVM_REFERENCE) || (get_max_depth() == get_active_object_depth())) begin print_object_header(name,value,scope_separator); pop_element(); end else begin push_active_object(value); m_recur_states[value][recursion_policy] = uvm_policy::STARTED ; print_object_header(name,value,scope_separator); if($cast(comp, value)) begin string name; if (comp.get_first_child(name)) do begin child_comp = comp.get_child(name); if(child_comp.print_enabled) this.print_object(name,child_comp); end while (comp.get_next_child(name)); end field_op = uvm_field_op::m_get_available_op() ; field_op.set(UVM_PRINT,this,null); value.do_execute_op(field_op); if (field_op.user_hook_enabled()) value.do_print(this); field_op.m_recycle(); pop_element() ; m_recur_states[value][recursion_policy] = uvm_policy::FINISHED ; void'(pop_active_object()); end endfunction function bit uvm_printer::istop (); return (get_active_object_depth() == 0); endfunction function void uvm_printer::print_generic (string name, string type_name, int size, string value, byte scope_separator="."); push_element(name, type_name, (size == -2 ? "..." : $sformatf("%0d",size)), value); pop_element(); endfunction function void uvm_printer::print_generic_element (string name, string type_name, string size, string value); push_element(name,type_name,size,value); pop_element() ; endfunction function void uvm_printer::print_time (string name, time value, byte scope_separator="."); print_field_int(name, value, 64, UVM_TIME, scope_separator); endfunction function void uvm_printer::print_string (string name, string value, byte scope_separator="."); push_element(name, "string", $sformatf("%0d",value.len()), (value == "" ? "\"\"" : value)); pop_element() ; endfunction function uvm_policy::recursion_state_e uvm_printer::object_printed (uvm_object value, uvm_recursion_policy_enum recursion); if (!m_recur_states.exists(value)) return NEVER ; if (!m_recur_states[value].exists(recursion)) return NEVER ; else return m_recur_states[value][recursion] ; endfunction function void uvm_printer::print_real (string name, real value, byte scope_separator="."); push_element(name,"real","64",$sformatf("%f",value)); pop_element() ; endfunction function string uvm_printer::index_string(int index, string name=""); index_string.itoa(index); index_string = { name, "[", index_string, "]" }; endfunction function uvm_printer_element::new (string name = ""); super.new(name) ; endfunction function void uvm_printer_element::set (string element_name = "", string element_type_name = "", string element_size = "", string element_value = "" ); m_name = element_name ; m_type_name = element_type_name ; m_size = element_size ; m_value = element_value ; endfunction function void uvm_printer_element::set_element_name (string element_name); m_name = element_name ; endfunction function string uvm_printer_element::get_element_name (); return m_name ; endfunction function void uvm_printer_element::set_element_type_name (string element_type_name); m_type_name = element_type_name ; endfunction function string uvm_printer_element::get_element_type_name (); return m_type_name ; endfunction function void uvm_printer_element::set_element_size (string element_size); m_size = element_size ; endfunction function string uvm_printer_element::get_element_size (); return m_size ; endfunction function void uvm_printer_element::set_element_value (string element_value); m_value = element_value ; endfunction function string uvm_printer_element::get_element_value (); return m_value ; endfunction function void uvm_printer_element::add_child(uvm_printer_element child) ; m_children.push_back(child) ; endfunction function void uvm_printer_element::get_children(ref uvm_printer_element children[$], input bit recurse) ; foreach (m_children[i]) begin children.push_back(m_children[i]) ; if (recurse) begin m_children[i].get_children(children,1) ; end end endfunction function void uvm_printer_element::clear_children() ; m_children.delete() ; endfunction function uvm_table_printer::new(string name=""); super.new(name); endfunction function void uvm_table_printer::pop_element(); int name_len; int level ; uvm_printer_element popped ; string name_str ; string type_name_str ; string size_str ; string value_str ; popped = get_top_element() ; level = m_get_stack_size() - 1 ; name_str = popped.get_element_name() ; type_name_str = popped.get_element_type_name() ; size_str = popped.get_element_size() ; value_str = popped.get_element_value() ; if ((name_str.len() + (get_indent() * level)) > m_max_name) m_max_name = (name_str.len() + (get_indent() * level)); if (type_name_str.len() > m_max_type) m_max_type = type_name_str.len(); if (size_str.len() > m_max_size) m_max_size = size_str.len(); if (value_str.len() > m_max_value) m_max_value = value_str.len(); super.pop_element() ; endfunction function string uvm_table_printer::emit(); string s; string user_format; static string dash; string dashes; string linefeed; if (!m_flushed) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/PRINT/NO_FLUSH")) uvm_report_error ("UVM/PRINT/NO_FLUSH", "printer emit() method called twice without intervening uvm_printer::flush()", UVM_NONE, "t/uvm/src/base/uvm_printer.svh", 1516, "", 1); end end else m_flushed = 0 ; linefeed = {"\n", get_line_prefix()}; begin int q[5]; int m; int qq[$]; q = '{m_max_name,m_max_type,m_max_size,m_max_value,100}; qq = q.max; m = qq[0]; if(dash.len() 0) && (value_str[0] == "@")) result = {result,"(",element.get_element_type_name(),value_str,") "}; else if (get_type_name_enabled() && (element.get_element_type_name() != "" || element.get_element_type_name() != "-" || element.get_element_type_name() != "...")) result = {result,"(",element.get_element_type_name(),") "}; if (get_size_enabled()) begin if (element.get_element_size() != "" || element.get_element_size() != "-") result = {result,"(",element.get_element_size(),") "}; end if (element_children.size() > 0) begin result = {result, string'(separators[0]), m_linefeed}; end else result = {result, value_str, " ", m_linefeed}; foreach (element_children[i]) begin result = {result, m_emit_element(element_children[i],level+1)} ; end if (element_children.size() > 0) begin result = {result, indent_str, string'(separators[1]), m_linefeed}; end end return result ; endfunction : m_emit_element function void uvm_table_printer::set_default(uvm_table_printer printer) ; m_default_table_printer = printer ; endfunction function uvm_table_printer uvm_table_printer::get_default() ; if (m_default_table_printer == null) begin m_default_table_printer = new("uvm_default_table_printer") ; end return m_default_table_printer ; endfunction function void uvm_table_printer::set_indent(int indent) ; m_uvm_printer_knobs _knobs = get_knobs(); _knobs.indent = indent ; endfunction function int uvm_table_printer::get_indent() ; m_uvm_printer_knobs _knobs = get_knobs(); return _knobs.indent ; endfunction function void uvm_table_printer::flush() ; super.flush() ; m_max_name=4; m_max_type=4; m_max_size=4; m_max_value=5; endfunction function void uvm_tree_printer::set_default(uvm_tree_printer printer) ; m_default_tree_printer = printer ; endfunction function uvm_tree_printer uvm_tree_printer::get_default() ; if (m_default_tree_printer == null) begin m_default_tree_printer = new("uvm_default_tree_printer") ; end return m_default_tree_printer ; endfunction function uvm_line_printer::new(string name="") ; super.new(name); m_newline = " "; set_indent(0); endfunction function void uvm_line_printer::set_default(uvm_line_printer printer) ; m_default_line_printer = printer ; endfunction function uvm_line_printer uvm_line_printer::get_default() ; if (m_default_line_printer == null) begin m_default_line_printer = new("uvm_default_line_printer") ; end return m_default_line_printer ; endfunction function void uvm_line_printer::set_separators(string separators) ; m_uvm_printer_knobs _knobs = get_knobs(); if (separators.len() < 2) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/PRINT/SHORT_SEP")) uvm_report_error ("UVM/PRINT/SHORT_SEP", $sformatf("Bad call: set_separators(%s) (Argument must have at least 2 characters)",separators), UVM_NONE, "t/uvm/src/base/uvm_printer.svh", 1888, "", 1); end end _knobs.separator = separators ; endfunction function string uvm_line_printer::get_separators() ; m_uvm_printer_knobs _knobs = get_knobs(); return _knobs.separator ; endfunction function void uvm_line_printer::flush() ; super.flush() ; endfunction class uvm_comparer extends uvm_policy; typedef uvm_object_registry#(uvm_comparer,"uvm_comparer") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_comparer tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_comparer"; endfunction : type_name virtual function string get_type_name(); return "uvm_comparer"; endfunction : get_type_name extern virtual function void flush(); extern virtual function uvm_policy::recursion_state_e object_compared( uvm_object lhs, uvm_object rhs, uvm_recursion_policy_enum recursion, output bit ret_val ); extern virtual function string get_miscompares(); extern virtual function int unsigned get_result(); extern virtual function void set_result(int unsigned result) ; extern virtual function void set_recursion_policy( uvm_recursion_policy_enum policy); extern virtual function uvm_recursion_policy_enum get_recursion_policy(); extern virtual function void set_check_type( bit enabled ); extern virtual function bit get_check_type(); extern virtual function void set_show_max (int unsigned show_max); extern virtual function int unsigned get_show_max (); extern virtual function void set_verbosity (int unsigned verbosity); extern virtual function int unsigned get_verbosity (); extern virtual function void set_severity (uvm_severity severity); extern virtual function uvm_severity get_severity (); extern virtual function void set_threshold (int unsigned threshold); extern virtual function int unsigned get_threshold (); typedef struct { recursion_state_e state; bit ret_val; } state_info_t ; state_info_t m_recur_states[uvm_object ][uvm_object ][uvm_recursion_policy_enum ]; local uvm_recursion_policy_enum policy = UVM_DEFAULT_POLICY; local int unsigned show_max = 1; local int unsigned verbosity = UVM_LOW; local uvm_severity sev = UVM_INFO; local string miscompares = ""; local bit check_type = 1; local int unsigned result = 0; local int unsigned m_threshold; function new(string name=""); super.new(name); m_threshold = 1; endfunction static function void set_default (uvm_comparer comparer) ; uvm_coreservice_t coreservice ; coreservice = uvm_coreservice_t::get() ; coreservice.set_default_comparer(comparer) ; endfunction static function uvm_comparer get_default () ; uvm_coreservice_t coreservice ; coreservice = uvm_coreservice_t::get() ; return coreservice.get_default_comparer() ; endfunction virtual function bit compare_field (string name, uvm_bitstream_t lhs, uvm_bitstream_t rhs, int size, uvm_radix_enum radix=UVM_NORADIX); uvm_bitstream_t mask; string msg; if(size <= 64) return compare_field_int(name, lhs, rhs, size, radix); mask = -1; mask >>= (UVM_STREAMBITS-size); if((lhs & mask) !== (rhs & mask)) begin case (radix) UVM_BIN: begin $swrite(msg, "%s: lhs = 'b%0b : rhs = 'b%0b", name, lhs&mask, rhs&mask); end UVM_OCT: begin $swrite(msg, "%s: lhs = 'o%0o : rhs = 'o%0o", name, lhs&mask, rhs&mask); end UVM_DEC: begin $swrite(msg, "%s: lhs = %0d : rhs = %0d", name, lhs&mask, rhs&mask); end UVM_TIME: begin $swrite(msg, "%s: lhs = %0t : rhs = %0t", name, lhs&mask, rhs&mask); end UVM_STRING: begin $swrite(msg, "%s: lhs = %0s : rhs = %0s", name, lhs&mask, rhs&mask); end UVM_ENUM: begin $swrite(msg, "%s: lhs = %0d : rhs = %0d", name, lhs&mask, rhs&mask); end default: begin $swrite(msg, "%s: lhs = 'h%0x : rhs = 'h%0x", name, lhs&mask, rhs&mask); end endcase print_msg(msg); return 0; end return 1; endfunction virtual function bit compare_field_int (string name, uvm_integral_t lhs, uvm_integral_t rhs, int size, uvm_radix_enum radix=UVM_NORADIX); logic [63:0] mask; string msg; mask = -1; mask >>= (64-size); if((lhs & mask) !== (rhs & mask)) begin case (radix) UVM_BIN: begin $swrite(msg, "%s: lhs = 'b%0b : rhs = 'b%0b", name, lhs&mask, rhs&mask); end UVM_OCT: begin $swrite(msg, "%s: lhs = 'o%0o : rhs = 'o%0o", name, lhs&mask, rhs&mask); end UVM_DEC: begin $swrite(msg, "%s: lhs = %0d : rhs = %0d", name, lhs&mask, rhs&mask); end UVM_TIME: begin $swrite(msg, "%s: lhs = %0t : rhs = %0t", name, lhs&mask, rhs&mask); end UVM_STRING: begin $swrite(msg, "%s: lhs = %0s : rhs = %0s", name, lhs&mask, rhs&mask); end UVM_ENUM: begin $swrite(msg, "%s: lhs = %0d : rhs = %0d", name, lhs&mask, rhs&mask); end default: begin $swrite(msg, "%s: lhs = 'h%0x : rhs = 'h%0x", name, lhs&mask, rhs&mask); end endcase print_msg(msg); return 0; end return 1; endfunction virtual function bit compare_field_real (string name, real lhs, real rhs); string msg; if(lhs != rhs) begin $swrite(msg, name, ": lhs = ", lhs, " : rhs = ", rhs); print_msg(msg); return 0; end return 1; endfunction local string m_object_names[$]; local function string m_current_context(string name=""); if (m_object_names.size() == 0) return name; else if ((m_object_names.size() == 1) && (name=="")) return m_object_names[0]; else begin string full_name; foreach(m_object_names[i]) begin if (i == m_object_names.size() - 1) full_name = {full_name, m_object_names[i]}; else full_name = {full_name, m_object_names[i], "."}; end if (name != "") return {full_name, ".", name}; else return full_name; end endfunction : m_current_context virtual function bit compare_object (string name, uvm_object lhs, uvm_object rhs); int old_result ; uvm_field_op field_op ; uvm_policy::recursion_state_e prev_state; bit ret_val = 1; if (rhs == lhs) return ret_val; m_object_names.push_back(name); if (policy == UVM_REFERENCE && lhs != rhs) begin print_msg_object(lhs, rhs); ret_val = 0; end if (ret_val && (rhs == null || lhs == null)) begin print_msg_object(lhs, rhs); ret_val = 0; end if (ret_val) begin prev_state = object_compared(lhs,rhs,get_recursion_policy(),ret_val); if (prev_state != uvm_policy::NEVER) begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"UVM/COPIER/LOOP")) uvm_report_warning ("UVM/COPIER/LOOP", {"Possible loop when comparing '", lhs.get_full_name(), "' to '", rhs.get_full_name(), "'"}, UVM_NONE, "t/uvm/src/base/uvm_comparer.svh", 465, "", 1); end push_active_object(lhs); m_recur_states[lhs][rhs][get_recursion_policy()] = '{uvm_policy::STARTED,0}; old_result = get_result(); if (get_check_type() && (lhs.get_object_type() != rhs.get_object_type())) begin if(lhs.get_type_name() != rhs.get_type_name()) begin print_msg({"type: lhs = \"", lhs.get_type_name(), "\" : rhs = \"", rhs.get_type_name(), "\""}); end else begin print_msg({"get_object_type() for ",lhs.get_name()," does not match get_object_type() for ",rhs.get_name()}); end end field_op = uvm_field_op::m_get_available_op(); field_op.set(UVM_COMPARE,this,rhs); lhs.do_execute_op(field_op); if (field_op.user_hook_enabled()) begin ret_val = lhs.do_compare(rhs,this); end field_op.m_recycle(); if (ret_val && (get_result() > old_result)) ret_val = 0; m_recur_states[lhs][rhs][get_recursion_policy()] = '{uvm_policy::FINISHED,ret_val}; void'(pop_active_object()); end void'(m_object_names.pop_back()); if (!ret_val && (get_active_object_depth() == 0)) begin string msg ; if(get_result()) begin if (get_show_max() && (get_show_max() < get_result())) $swrite(msg, "%0d Miscompare(s) (%0d shown) for object ", result, show_max); else $swrite(msg, "%0d Miscompare(s) for object ", result); end uvm_pkg::uvm_report(sev, "MISCMP", $sformatf("%s%s@%0d vs. %s@%0d", msg, (lhs == null) ? "" : lhs.get_name(), (lhs == null) ? 0 : lhs.get_inst_id(), (rhs == null) ? "" : rhs.get_name(), (rhs == null) ? 0 : rhs.get_inst_id()), get_verbosity(), "t/uvm/src/base/uvm_comparer.svh", 525); end return ret_val; endfunction virtual function bit compare_string (string name, string lhs, string rhs); string msg; if(lhs != rhs) begin msg = { name, ": lhs = \"", lhs, "\" : rhs = \"", rhs, "\""}; print_msg(msg); return 0; end return 1; endfunction function void print_msg (string msg); string tmp = m_current_context(msg); result++; if((get_show_max() == 0) || (get_result() <= get_show_max())) begin msg = {"Miscompare for ", tmp}; uvm_pkg::uvm_report(sev, "MISCMP", msg, get_verbosity(), "t/uvm/src/base/uvm_comparer.svh", 573); end miscompares = { miscompares, tmp, "\n" }; endfunction function void print_msg_object(uvm_object lhs, uvm_object rhs); string tmp = $sformatf("%s: lhs = @%0d : rhs = @%0d", m_current_context(), (lhs != null ? lhs.get_inst_id() : 0), (rhs != null ? rhs.get_inst_id() : 0)); result++; if((get_show_max() == 0) || (get_result() <= get_show_max())) begin uvm_pkg::uvm_report(sev, "MISCMP", {"Miscompare for ", tmp}, get_verbosity(), "t/uvm/src/base/uvm_comparer.svh", 599); end miscompares = { miscompares, tmp, "\n" }; endfunction int depth; bit compare_map[uvm_object][uvm_object]; endclass function void uvm_comparer::flush(); miscompares = "" ; check_type = 1 ; result = 0 ; m_recur_states.delete(); endfunction function uvm_policy::recursion_state_e uvm_comparer::object_compared( uvm_object lhs, uvm_object rhs, uvm_recursion_policy_enum recursion, output bit ret_val ); if (!m_recur_states.exists(lhs)) return NEVER ; else if (!m_recur_states[lhs].exists(rhs)) return NEVER ; else if (!m_recur_states[lhs][rhs].exists(recursion)) return NEVER ; else begin if (m_recur_states[lhs][rhs][recursion].state == FINISHED) ret_val = m_recur_states[lhs][rhs][recursion].ret_val; return m_recur_states[lhs][rhs][recursion].state ; end endfunction function string uvm_comparer::get_miscompares(); return miscompares ; endfunction function int unsigned uvm_comparer::get_result(); return result ; endfunction function void uvm_comparer::set_result(int unsigned result); this.result = result ; endfunction function void uvm_comparer::set_recursion_policy( uvm_recursion_policy_enum policy); this.policy = policy ; endfunction function uvm_recursion_policy_enum uvm_comparer::get_recursion_policy(); return policy ; endfunction function void uvm_comparer::set_check_type( bit enabled ); check_type = enabled ; endfunction function bit uvm_comparer::get_check_type(); return check_type ; endfunction function void uvm_comparer::set_show_max (int unsigned show_max); this.show_max = show_max ; endfunction function int unsigned uvm_comparer::get_show_max(); return show_max ; endfunction function void uvm_comparer::set_verbosity (int unsigned verbosity); this.verbosity = verbosity ; endfunction function int unsigned uvm_comparer::get_verbosity(); return verbosity ; endfunction function void uvm_comparer::set_severity (uvm_severity severity); sev = severity ; endfunction function uvm_severity uvm_comparer::get_severity(); return sev ; endfunction function void uvm_comparer::set_threshold (int unsigned threshold); m_threshold = threshold; endfunction function int unsigned uvm_comparer::get_threshold(); return m_threshold; endfunction typedef bit signed [(4096*8)-1:0] uvm_pack_bitstream_t; class uvm_packer extends uvm_policy; typedef uvm_object_registry#(uvm_packer,"uvm_packer") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_packer tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_packer"; endfunction : type_name virtual function string get_type_name(); return "uvm_packer"; endfunction : get_type_name uvm_factory m_factory; local uvm_object m_object_references[int]; extern virtual function void set_packed_bits (ref bit unsigned stream[]); extern virtual function void set_packed_bytes (ref byte unsigned stream[]); extern virtual function void set_packed_ints (ref int unsigned stream[]); extern virtual function void set_packed_longints (ref longint unsigned stream[]); extern virtual function void get_packed_bits (ref bit unsigned stream[]); extern virtual function void get_packed_bytes (ref byte unsigned stream[]); extern virtual function void get_packed_ints (ref int unsigned stream[]); extern virtual function void get_packed_longints (ref longint unsigned stream[]); static function void set_default (uvm_packer packer) ; uvm_coreservice_t coreservice ; coreservice = uvm_coreservice_t::get() ; coreservice.set_default_packer(packer) ; endfunction static function uvm_packer get_default () ; uvm_coreservice_t coreservice ; coreservice = uvm_coreservice_t::get() ; return coreservice.get_default_packer() ; endfunction extern virtual function void flush (); extern virtual function void pack_field (uvm_bitstream_t value, int size); extern function new(string name=""); extern virtual function void pack_field_int (uvm_integral_t value, int size); extern virtual function void pack_bits(ref bit value[], input int size = -1); extern virtual function void pack_bytes(ref byte value[], input int size = -1); extern virtual function void pack_ints(ref int value[], input int size = -1); extern virtual function void pack_string (string value); extern virtual function void pack_time (time value); extern virtual function void pack_real (real value); extern virtual function void pack_object (uvm_object value); extern virtual function void pack_object_with_meta (uvm_object value); extern virtual function void pack_object_wrapper (uvm_object_wrapper value); extern virtual function bit is_null (); extern virtual function bit is_object_wrapper(); extern virtual function uvm_bitstream_t unpack_field (int size); extern virtual function uvm_integral_t unpack_field_int (int size); extern virtual function void unpack_bits(ref bit value[], input int size = -1); extern virtual function void unpack_bytes(ref byte value[], input int size = -1); extern virtual function void unpack_ints(ref int value[], input int size = -1); extern virtual function string unpack_string (); extern virtual function time unpack_time (); extern virtual function real unpack_real (); extern virtual function void unpack_object (uvm_object value); extern virtual function void unpack_object_with_meta (inout uvm_object value); extern virtual function uvm_object_wrapper unpack_object_wrapper(); extern virtual function int get_packed_size(); static bit bitstream[]; static bit fabitstream[]; int m_pack_iter; int m_unpack_iter; bit reverse_order; byte byte_size = 8; int word_size = 16; bit nopack; uvm_pack_bitstream_t m_bits; extern function void index_error(int index, string id, int sz); extern function bit enough_bits(int needed, string id); endclass function void uvm_packer::index_error(int index, string id, int sz); uvm_report_error("PCKIDX", $sformatf("index %0d for get_%0s too large; valid index range is 0-%0d.", index,id,((m_pack_iter+sz-1)/sz)-1), UVM_NONE); endfunction function bit uvm_packer::enough_bits(int needed, string id); if ((m_pack_iter - m_unpack_iter) < needed) begin uvm_report_error("PCKSZ", $sformatf("%0d bits needed to unpack %0s, yet only %0d available.", needed, id, (m_pack_iter - m_unpack_iter)), UVM_NONE); return 0; end return 1; endfunction function int uvm_packer::get_packed_size(); return m_pack_iter - m_unpack_iter; endfunction function void uvm_packer::flush(); m_pack_iter = 64; m_unpack_iter = 64; m_bits = 0; m_object_references.delete(); m_object_references[0] = null; m_factory = null; super.flush(); endfunction : flush function void uvm_packer::get_packed_bits(ref bit unsigned stream[]); stream = new[m_pack_iter]; m_bits[31:0] = m_pack_iter; m_bits[63:32] = m_unpack_iter; for (int i=0;i> ($bits(T)-(m_pack_iter%$bits(T)))); \ stream[i] = v; \ end \ endfunction function void uvm_packer::get_packed_bytes (ref byte unsigned stream[] ); int sz; byte v; sz = (m_pack_iter + $high(v)) / $bits(byte); m_bits[31:0] = m_pack_iter; m_bits[63:32] = m_unpack_iter; stream = new[sz]; foreach (stream[i]) begin if (i != sz-1 || (m_pack_iter % $bits(byte)) == 0) v = m_bits[ i* $bits(byte) +: $bits(byte) ]; else v = m_bits[ i* $bits(byte) +: $bits(byte) ] & ({$bits(byte){1'b1}} >> ($bits(byte)-(m_pack_iter%$bits(byte)))); stream[i] = v; end endfunction function void uvm_packer::get_packed_ints (ref int unsigned stream[] ); int sz; int v; sz = (m_pack_iter + $high(v)) / $bits(int); m_bits[31:0] = m_pack_iter; m_bits[63:32] = m_unpack_iter; stream = new[sz]; foreach (stream[i]) begin if (i != sz-1 || (m_pack_iter % $bits(int)) == 0) v = m_bits[ i* $bits(int) +: $bits(int) ]; else v = m_bits[ i* $bits(int) +: $bits(int) ] & ({$bits(int){1'b1}} >> ($bits(int)-(m_pack_iter%$bits(int)))); stream[i] = v; end endfunction function void uvm_packer::get_packed_longints (ref longint unsigned stream[] ); int sz; longint v; sz = (m_pack_iter + $high(v)) / $bits(longint); m_bits[31:0] = m_pack_iter; m_bits[63:32] = m_unpack_iter; stream = new[sz]; foreach (stream[i]) begin if (i != sz-1 || (m_pack_iter % $bits(longint)) == 0) v = m_bits[ i* $bits(longint) +: $bits(longint) ]; else v = m_bits[ i* $bits(longint) +: $bits(longint) ] & ({$bits(longint){1'b1}} >> ($bits(longint)-(m_pack_iter%$bits(longint)))); stream[i] = v; end endfunction `undef M__UVM_GET_PACKED function void uvm_packer::set_packed_bits (ref bit stream []); int bit_size; bit_size = stream.size(); for (int i=0;i value.size()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/BASE/PACKER/BAD_SIZE")) uvm_report_error ("UVM/BASE/PACKER/BAD_SIZE", $sformatf("pack_bits called with size '%0d', which exceeds value.size() of '%0d'", size, value.size()), UVM_NONE, "t/uvm/src/base/uvm_packer.svh", 797, "", 1); end return; end for (int i=0; i max_size) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/BASE/PACKER/BAD_SIZE")) uvm_report_error ("UVM/BASE/PACKER/BAD_SIZE", $sformatf("pack_bytes called with size '%0d', which exceeds value size of '%0d'", size, max_size), UVM_NONE, "t/uvm/src/base/uvm_packer.svh", 824, "", 1); end return; end else begin int idx_select; for (int i=0; i max_size) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/BASE/PACKER/BAD_SIZE")) uvm_report_error ("UVM/BASE/PACKER/BAD_SIZE", $sformatf("pack_ints called with size '%0d', which exceeds value size of '%0d'", size, max_size), UVM_NONE, "t/uvm/src/base/uvm_packer.svh", 858, "", 1); end return; end else begin int idx_select; for (int i=0; i value.size()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/BASE/PACKER/BAD_SIZE")) uvm_report_error ("UVM/BASE/PACKER/BAD_SIZE", $sformatf("unpack_bits called with size '%0d', which exceeds value.size() of '%0d'", size, value.size()), UVM_NONE, "t/uvm/src/base/uvm_packer.svh", 1076, "", 1); end return; end if (enough_bits(size, "integral")) begin m_unpack_iter += size; for (int i=0; i max_size) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/BASE/PACKER/BAD_SIZE")) uvm_report_error ("UVM/BASE/PACKER/BAD_SIZE", $sformatf("unpack_bytes called with size '%0d', which exceeds value size of '%0d'", size, value.size()), UVM_NONE, "t/uvm/src/base/uvm_packer.svh", 1104, "", 1); end return; end else begin if (enough_bits(size, "integral")) begin m_unpack_iter += size; for (int i=0; i max_size) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/BASE/PACKER/BAD_SIZE")) uvm_report_error ("UVM/BASE/PACKER/BAD_SIZE", $sformatf("unpack_ints called with size '%0d', which exceeds value size of '%0d'", size, value.size()), UVM_NONE, "t/uvm/src/base/uvm_packer.svh", 1136, "", 1); end return; end else begin if (enough_bits(size, "integral")) begin m_unpack_iter += size; for (int i=0; i' is not supported in links for 'uvm_tr_database'", UVM_NONE, "t/uvm/src/base/uvm_tr_database.svh", 158, "", 1); end return; end if (rhs == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"UVM/TR_DB/BAD_LINK")) uvm_report_warning ("UVM/TR_DB/BAD_LINK", "right hand side '' is not supported in links for 'uvm_tr_database'", UVM_NONE, "t/uvm/src/base/uvm_tr_database.svh", 163, "", 1); end return; end if (!$cast(s_lhs, lhs) && !$cast(r_lhs, lhs)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"UVM/TR_DB/BAD_LINK")) uvm_report_warning ("UVM/TR_DB/BAD_LINK", $sformatf("left hand side of type '%s' not supported in links for 'uvm_tr_database'", lhs.get_type_name()), UVM_NONE, "t/uvm/src/base/uvm_tr_database.svh", 171, "", 1); end return; end if (!$cast(s_rhs, rhs) && !$cast(r_rhs, rhs)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"UVM/TR_DB/BAD_LINK")) uvm_report_warning ("UVM/TR_DB/BAD_LINK", $sformatf("right hand side of type '%s' not supported in links for 'uvm_record_datbasae'", rhs.get_type_name()), UVM_NONE, "t/uvm/src/base/uvm_tr_database.svh", 178, "", 1); end return; end if (r_lhs != null) begin s_lhs = r_lhs.get_stream(); end if (r_rhs != null) begin s_rhs = r_rhs.get_stream(); end if ((s_lhs != null) && (s_lhs.get_db() != this)) begin db = s_lhs.get_db(); begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"UVM/TR_DB/BAD_LINK")) uvm_report_warning ("UVM/TR_DB/BAD_LINK", $sformatf("attempt to link stream from '%s' into '%s'", db.get_name(), this.get_name()), UVM_NONE, "t/uvm/src/base/uvm_tr_database.svh", 193, "", 1); end return; end if ((s_rhs != null) && (s_rhs.get_db() != this)) begin db = s_rhs.get_db(); begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"UVM/TR_DB/BAD_LINK")) uvm_report_warning ("UVM/TR_DB/BAD_LINK", $sformatf("attempt to link stream from '%s' into '%s'", db.get_name(), this.get_name()), UVM_NONE, "t/uvm/src/base/uvm_tr_database.svh", 200, "", 1); end return; end do_establish_link(link); endfunction : establish_link pure virtual protected function bit do_open_db(); pure virtual protected function bit do_close_db(); pure virtual protected function uvm_tr_stream do_open_stream(string name, string scope, string type_name); pure virtual protected function void do_establish_link(uvm_link_base link); endclass : uvm_tr_database typedef class uvm_recorder; typedef class uvm_tr_stream; typedef class uvm_link_base; typedef class uvm_simple_lock_dap; typedef class uvm_text_tr_stream; class uvm_text_tr_database extends uvm_tr_database; local uvm_simple_lock_dap#(string) m_filename_dap; UVM_FILE m_file; typedef uvm_object_registry#(uvm_text_tr_database,"uvm_text_tr_database") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_text_tr_database tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_text_tr_database"; endfunction : type_name virtual function string get_type_name(); return "uvm_text_tr_database"; endfunction : get_type_name function new(string name="unnamed-uvm_text_tr_database"); super.new(name); m_filename_dap = new("filename_dap"); m_filename_dap.set("tr_db.log"); endfunction : new protected virtual function bit do_open_db(); if (m_file == 0) begin m_file = $fopen(m_filename_dap.get(), "a+"); if (m_file != 0) m_filename_dap.lock(); end return (m_file != 0); endfunction : do_open_db protected virtual function bit do_close_db(); if (m_file != 0) begin fork $fclose(m_file); join_none m_filename_dap.unlock(); end return 1; endfunction : do_close_db protected virtual function uvm_tr_stream do_open_stream(string name, string scope, string type_name); uvm_text_tr_stream m_stream = uvm_text_tr_stream::type_id::create(name); return m_stream; endfunction : do_open_stream protected virtual function void do_establish_link(uvm_link_base link); uvm_recorder r_lhs, r_rhs; uvm_object lhs = link.get_lhs(); uvm_object rhs = link.get_rhs(); void'($cast(r_lhs, lhs)); void'($cast(r_rhs, rhs)); if ((r_lhs == null) || (r_rhs == null)) return; else begin uvm_parent_child_link pc_link; uvm_related_link re_link; if ($cast(pc_link, link)) begin $fdisplay(m_file," LINK @%0t {TXH1:%0d TXH2:%0d RELATION=%0s}", $time, r_lhs.get_handle(), r_rhs.get_handle(), "child"); end else if ($cast(re_link, link)) begin $fdisplay(m_file," LINK @%0t {TXH1:%0d TXH2:%0d RELATION=%0s}", $time, r_lhs.get_handle(), r_rhs.get_handle(), ""); end end endfunction : do_establish_link function void set_file_name(string filename); if (filename == "") begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"UVM/TXT_DB/EMPTY_NAME")) uvm_report_warning ("UVM/TXT_DB/EMPTY_NAME", "Ignoring attempt to set file name to ''!", UVM_NONE, "t/uvm/src/base/uvm_text_tr_database.svh", 191, "", 1); end return; end if (!m_filename_dap.try_set(filename)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"UVM/TXT_DB/SET_AFTER_OPEN")) uvm_report_warning ("UVM/TXT_DB/SET_AFTER_OPEN", "Ignoring attempt to change file name after opening the db!", UVM_NONE, "t/uvm/src/base/uvm_text_tr_database.svh", 197, "", 1); end return; end endfunction : set_file_name endclass : uvm_text_tr_database class m_uvm_tr_stream_cfg; uvm_tr_database db; string scope; string stream_type_name; endclass : m_uvm_tr_stream_cfg typedef class uvm_set_before_get_dap; typedef class uvm_text_recorder; virtual class uvm_tr_stream extends uvm_object; local uvm_set_before_get_dap#(m_uvm_tr_stream_cfg) m_cfg_dap; local bit m_records[uvm_recorder]; local bit m_warn_null_cfg; local bit m_is_opened; local bit m_is_closed; function new(string name="unnamed-uvm_tr_stream"); super.new(name); m_cfg_dap = new("cfg_dap"); endfunction : new local static int m_ids_by_stream[uvm_tr_stream]; function uvm_tr_database get_db(); m_uvm_tr_stream_cfg m_cfg; if (!m_cfg_dap.try_get(m_cfg)) begin if (m_warn_null_cfg == 1) begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"UVM/REC_STR/NO_CFG")) uvm_report_warning ("UVM/REC_STR/NO_CFG", $sformatf("attempt to retrieve DB from '%s' before it was set!", get_name()), UVM_NONE, "t/uvm/src/base/uvm_tr_stream.svh", 94, "", 1); end m_warn_null_cfg = 0; return null; end return m_cfg.db; endfunction : get_db function string get_scope(); m_uvm_tr_stream_cfg m_cfg; if (!m_cfg_dap.try_get(m_cfg)) begin if (m_warn_null_cfg == 1) begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"UVM/REC_STR/NO_CFG")) uvm_report_warning ("UVM/REC_STR/NO_CFG", $sformatf("attempt to retrieve scope from '%s' before it was set!", get_name()), UVM_NONE, "t/uvm/src/base/uvm_tr_stream.svh", 109, "", 1); end m_warn_null_cfg = 0; return ""; end return m_cfg.scope; endfunction : get_scope function string get_stream_type_name(); m_uvm_tr_stream_cfg m_cfg; if (!m_cfg_dap.try_get(m_cfg)) begin if (m_warn_null_cfg == 1) begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"UVM/REC_STR/NO_CFG")) uvm_report_warning ("UVM/REC_STR/NO_CFG", $sformatf("attempt to retrieve STREAM_TYPE_NAME from '%s' before it was set!", get_name()), UVM_NONE, "t/uvm/src/base/uvm_tr_stream.svh", 124, "", 1); end m_warn_null_cfg = 0; return ""; end return m_cfg.stream_type_name; endfunction : get_stream_type_name function void close(); if (!is_open()) return; do_close(); foreach (m_records[idx]) if (idx.is_open()) idx.close(); m_is_opened = 0; m_is_closed = 1; endfunction : close function void free(); process p; string s; uvm_tr_database db; if (!is_open() && !is_closed()) return; if (is_open()) close(); do_free(); foreach (m_records[idx]) idx.free(); db = get_db(); m_is_closed = 0; p = process::self(); if(p != null) s = p.get_randstate(); m_cfg_dap = new("cfg_dap"); if(p != null) p.set_randstate(s); m_warn_null_cfg = 1; if (m_ids_by_stream.exists(this)) m_free_id(m_ids_by_stream[this]); if (db != null) db.m_free_stream(this); endfunction : free function void m_do_open(uvm_tr_database db, string scope="", string stream_type_name=""); m_uvm_tr_stream_cfg m_cfg; uvm_tr_database m_db; if (db == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/REC_STR/NULL_DB")) uvm_report_error ("UVM/REC_STR/NULL_DB", $sformatf("Illegal attempt to set DB for '%s' to ''", this.get_full_name()), UVM_NONE, "t/uvm/src/base/uvm_tr_stream.svh", 217, "", 1); end return; end if (m_cfg_dap.try_get(m_cfg)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/REC_STR/RE_CFG")) uvm_report_error ("UVM/REC_STR/RE_CFG", $sformatf("Illegal attempt to re-open '%s'", this.get_full_name()), UVM_NONE, "t/uvm/src/base/uvm_tr_stream.svh", 224, "", 1); end end else begin m_cfg = new(); m_cfg.db = db; m_cfg.scope = scope; m_cfg.stream_type_name = stream_type_name; m_cfg_dap.set(m_cfg); m_is_opened = 1; do_open(db, scope, stream_type_name); end endfunction : m_do_open function bit is_open(); return m_is_opened; endfunction : is_open function bit is_closed(); return m_is_closed; endfunction : is_closed function uvm_recorder open_recorder(string name, time open_time = 0, string type_name=""); time m_time = (open_time == 0) ? $time : open_time; if (!is_open()) return null; else begin process p = process::self(); string s; if (p != null) s = p.get_randstate(); open_recorder = do_open_recorder(name, m_time, type_name); if (open_recorder != null) begin m_records[open_recorder] = 1; open_recorder.m_do_open(this, m_time, type_name); end if (p != null) p.set_randstate(s); end endfunction : open_recorder function void m_free_recorder(uvm_recorder recorder); if (m_records.exists(recorder)) m_records.delete(recorder); endfunction : m_free_recorder function unsigned get_recorders(ref uvm_recorder q[$]); q.delete(); foreach (m_records[idx]) q.push_back(idx); return q.size(); endfunction : get_recorders local static uvm_tr_stream m_streams_by_id[int]; function int get_handle(); if (!is_open() && !is_closed()) begin return 0; end else begin int handle = get_inst_id(); if (m_ids_by_stream.exists(this) && m_ids_by_stream[this] != handle) m_streams_by_id.delete(m_ids_by_stream[this]); m_streams_by_id[handle] = this; m_ids_by_stream[this] = handle; return handle; end endfunction : get_handle static function uvm_tr_stream get_stream_from_handle(int id); if (id == 0) return null; if ($isunknown(id) || !m_streams_by_id.exists(id)) return null; return m_streams_by_id[id]; endfunction : get_stream_from_handle static function void m_free_id(int id); uvm_tr_stream stream; if (!$isunknown(id) && m_streams_by_id.exists(id)) stream = m_streams_by_id[id]; if (stream != null) begin m_streams_by_id.delete(id); m_ids_by_stream.delete(stream); end endfunction : m_free_id protected virtual function void do_open(uvm_tr_database db, string scope, string stream_type_name); endfunction : do_open protected virtual function void do_close(); endfunction : do_close protected virtual function void do_free(); endfunction : do_free protected virtual function uvm_recorder do_open_recorder(string name, time open_time, string type_name); return null; endfunction : do_open_recorder endclass : uvm_tr_stream class uvm_text_tr_stream extends uvm_tr_stream; local uvm_text_tr_database m_text_db; typedef uvm_object_registry#(uvm_text_tr_stream,"uvm_text_tr_stream") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_text_tr_stream tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_text_tr_stream"; endfunction : type_name virtual function string get_type_name(); return "uvm_text_tr_stream"; endfunction : get_type_name function void do_execute_op( uvm_field_op op ); super.do_execute_op(op); __m_uvm_execute_field_op(op); endfunction : do_execute_op local function void __m_uvm_execute_field_op( uvm_field_op __local_op__ ); uvm_field_flag_t local_op_type__; uvm_text_tr_stream local_rhs__; uvm_resource_base local_rsrc__; string local_rsrc_name__; uvm_object local_obj__; bit local_success__; typedef uvm_text_tr_stream __local_type__; int local_size__; uvm_printer __local_printer__; uvm_comparer __local_comparer__; uvm_recorder __local_recorder__; uvm_packer __local_packer__; uvm_copier __local_copier__; void'($cast(local_rhs__, __local_op__.get_rhs())); if (($cast(local_rsrc__, __local_op__.get_rhs())) && (local_rsrc__ != null)) local_rsrc_name__ = local_rsrc__.get_name(); local_op_type__ = __local_op__.get_op_type(); case (local_op_type__) UVM_PRINT: begin $cast(__local_printer__, __local_op__.get_policy()); end UVM_COMPARE: begin if (local_rhs__ == null) return; $cast(__local_comparer__, __local_op__.get_policy()); end UVM_RECORD: begin $cast(__local_recorder__, __local_op__.get_policy()); end UVM_PACK, UVM_UNPACK: begin $cast(__local_packer__, __local_op__.get_policy()); end UVM_COPY: begin if (local_rhs__ == null) return; $cast(__local_copier__, __local_op__.get_policy()); end UVM_SET: begin if (local_rsrc__ == null) return; end default: return; endcase endfunction : __m_uvm_execute_field_op function new(string name="unnamed-uvm_text_tr_stream"); super.new(name); endfunction : new protected virtual function void do_open(uvm_tr_database db, string scope, string stream_type_name); $cast(m_text_db, db); if (m_text_db.open_db()) $fdisplay(m_text_db.m_file, " CREATE_STREAM @%0t {NAME:%s T:%s SCOPE:%s STREAM:%0d}", $time, this.get_name(), stream_type_name, scope, this.get_handle()); endfunction : do_open protected virtual function void do_close(); if (m_text_db.open_db()) $fdisplay(m_text_db.m_file, " CLOSE_STREAM @%0t {NAME:%s T:%s SCOPE:%s STREAM:%0d}", $time, this.get_name(), this.get_stream_type_name(), this.get_scope(), this.get_handle()); endfunction : do_close protected virtual function void do_free(); if (m_text_db.open_db()) $fdisplay(m_text_db.m_file, " FREE_STREAM @%0t {NAME:%s T:%s SCOPE:%s STREAM:%0d}", $time, this.get_name(), this.get_stream_type_name(), this.get_scope(), this.get_handle()); m_text_db = null; return; endfunction : do_free protected virtual function uvm_recorder do_open_recorder(string name, time open_time, string type_name); if (m_text_db.open_db()) begin return uvm_text_recorder::type_id::create(name); end return null; endfunction : do_open_recorder endclass : uvm_text_tr_stream typedef class uvm_report_message; virtual class uvm_recorder extends uvm_policy; typedef uvm_abstract_object_registry#(uvm_recorder,"uvm_recorder") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_recorder"; endfunction : type_name virtual function string get_type_name(); return "uvm_recorder"; endfunction : get_type_name local uvm_set_before_get_dap#(uvm_tr_stream) m_stream_dap; local bit m_warn_null_stream; local bit m_is_opened; local bit m_is_closed; local time m_open_time; local time m_close_time; int recording_depth; uvm_radix_enum default_radix = UVM_HEX; bit identifier = 1; local uvm_recursion_policy_enum policy = UVM_DEFAULT_POLICY; virtual function void set_recursion_policy(uvm_recursion_policy_enum policy); this.policy = policy; endfunction : set_recursion_policy virtual function uvm_recursion_policy_enum get_recursion_policy(); return this.policy; endfunction : get_recursion_policy virtual function void flush(); policy = UVM_DEFAULT_POLICY; identifier = 1; free(); endfunction : flush local static int m_ids_by_recorder[uvm_recorder]; function new(string name = "uvm_recorder"); super.new(name); m_stream_dap = new("stream_dap"); m_warn_null_stream = 1; endfunction function uvm_tr_stream get_stream(); if (!m_stream_dap.try_get(get_stream)) begin if (m_warn_null_stream == 1) begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"UVM/REC/NO_CFG")) uvm_report_warning ("UVM/REC/NO_CFG", $sformatf("attempt to retrieve STREAM from '%s' before it was set!", get_name()), UVM_NONE, "t/uvm/src/base/uvm_recorder.svh", 178, "", 1); end m_warn_null_stream = 0; end endfunction : get_stream function void close(time close_time = 0); if (close_time == 0) close_time = $realtime; if (!is_open()) return; do_close(close_time); m_is_opened = 0; m_is_closed = 1; m_close_time = close_time; endfunction : close function void free(time close_time = 0); process p=process::self(); string s; uvm_tr_stream stream; if (!is_open() && !is_closed()) return; if (is_open()) begin close(close_time); end do_free(); stream = get_stream(); m_is_closed = 0; if(p != null) s=p.get_randstate(); m_stream_dap = new("stream_dap"); if(p != null) p.set_randstate(s); m_warn_null_stream = 1; if (m_ids_by_recorder.exists(this)) m_free_id(m_ids_by_recorder[this]); if (stream != null) stream.m_free_recorder(this); endfunction : free function bit is_open(); return m_is_opened; endfunction : is_open function time get_open_time(); return m_open_time; endfunction : get_open_time function bit is_closed(); return m_is_closed; endfunction : is_closed function time get_close_time(); return m_close_time; endfunction : get_close_time function void m_do_open(uvm_tr_stream stream, time open_time, string type_name); uvm_tr_stream m_stream; if (stream == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/REC/NULL_STREAM")) uvm_report_error ("UVM/REC/NULL_STREAM", $sformatf("Illegal attempt to set STREAM for '%s' to ''", this.get_name()), UVM_NONE, "t/uvm/src/base/uvm_recorder.svh", 287, "", 1); end return; end if (m_stream_dap.try_get(m_stream)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/REC/RE_INIT")) uvm_report_error ("UVM/REC/RE_INIT", $sformatf("Illegal attempt to re-initialize '%s'", this.get_name()), UVM_NONE, "t/uvm/src/base/uvm_recorder.svh", 294, "", 1); end return; end m_stream_dap.set(stream); m_open_time = open_time; m_is_opened = 1; do_open(stream, open_time, type_name); endfunction : m_do_open local static uvm_recorder m_recorders_by_id[int]; local static int m_id; static function void m_free_id(int id); uvm_recorder recorder; if ((!$isunknown(id)) && (m_recorders_by_id.exists(id))) recorder = m_recorders_by_id[id]; if (recorder != null) begin m_recorders_by_id.delete(id); m_ids_by_recorder.delete(recorder); end endfunction : m_free_id function int get_handle(); if (!is_open() && !is_closed()) begin return 0; end else begin int handle = get_inst_id(); if (m_ids_by_recorder.exists(this) && m_ids_by_recorder[this] != handle) m_recorders_by_id.delete(m_ids_by_recorder[this]); m_recorders_by_id[handle] = this; m_ids_by_recorder[this] = handle; return handle; end endfunction : get_handle static function uvm_recorder get_recorder_from_handle(int id); if (id == 0) return null; if (($isunknown(id)) || (!m_recorders_by_id.exists(id))) return null; return m_recorders_by_id[id]; endfunction : get_recorder_from_handle function void record_field(string name, uvm_bitstream_t value, int size, uvm_radix_enum radix=UVM_NORADIX); if (get_stream() == null) begin return; end do_record_field(name, value, size, radix); endfunction : record_field function void record_field_int(string name, uvm_integral_t value, int size, uvm_radix_enum radix=UVM_NORADIX); if (get_stream() == null) begin return; end do_record_field_int(name, value, size, radix); endfunction : record_field_int function void record_field_real(string name, real value); if (get_stream() == null) begin return; end do_record_field_real(name, value); endfunction : record_field_real function void record_object(string name, uvm_object value); if (get_stream() == null) begin return; end if (value == null) do_record_object(name, value); else begin push_active_object(value); do_record_object(name, value); void'(pop_active_object()); end endfunction : record_object function void record_string(string name, string value); if (get_stream() == null) begin return; end do_record_string(name, value); endfunction : record_string function void record_time(string name, time value); if (get_stream() == null) begin return; end do_record_time(name, value); endfunction : record_time function void record_generic(string name, string value, string type_name=""); if (get_stream() == null) begin return; end do_record_generic(name, value, type_name); endfunction : record_generic virtual function bit use_record_attribute(); return 0; endfunction : use_record_attribute virtual function int get_record_attribute_handle(); return get_handle(); endfunction : get_record_attribute_handle protected virtual function void do_open(uvm_tr_stream stream, time open_time, string type_name); endfunction : do_open protected virtual function void do_close(time close_time); endfunction : do_close protected virtual function void do_free(); endfunction : do_free pure virtual protected function void do_record_field(string name, uvm_bitstream_t value, int size, uvm_radix_enum radix); pure virtual protected function void do_record_field_int(string name, uvm_integral_t value, int size, uvm_radix_enum radix); pure virtual protected function void do_record_field_real(string name, real value); virtual protected function void do_record_object(string name, uvm_object value); if ((get_recursion_policy() != UVM_REFERENCE) && (value != null)) begin uvm_field_op field_op = uvm_field_op::m_get_available_op(); field_op.set(UVM_RECORD, this, null); value.do_execute_op(field_op); if (field_op.user_hook_enabled()) value.do_record(this); field_op.m_recycle(); end endfunction : do_record_object pure virtual protected function void do_record_string(string name, string value); pure virtual protected function void do_record_time(string name, time value); pure virtual protected function void do_record_generic(string name, string value, string type_name); virtual function bit open_file(); return 0; endfunction virtual function int create_stream (string name, string t, string scope); return -1; endfunction virtual function void m_set_attribute (int txh, string nm, string value); endfunction virtual function void set_attribute (int txh, string nm, logic [1023:0] value, uvm_radix_enum radix, int numbits=1024); endfunction virtual function int check_handle_kind (string htype, int handle); return 0; endfunction virtual function int begin_tr(string txtype, int stream, string nm, string label="", string desc="", time begin_time=0); return -1; endfunction virtual function void end_tr (int handle, time end_time=0); endfunction virtual function void link_tr(int h1, int h2, string relation=""); endfunction virtual function void free_tr(int handle); endfunction endclass class uvm_text_recorder extends uvm_recorder; typedef uvm_object_registry#(uvm_text_recorder,"uvm_text_recorder") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_text_recorder tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_text_recorder"; endfunction : type_name virtual function string get_type_name(); return "uvm_text_recorder"; endfunction : get_type_name uvm_text_tr_database m_text_db; function new(string name="unnamed-uvm_text_recorder"); super.new(name); endfunction : new protected virtual function void do_open(uvm_tr_stream stream, time open_time, string type_name); $cast(m_text_db, stream.get_db()); if (m_text_db.open_db()) $fdisplay(m_text_db.m_file, " OPEN_RECORDER @%0t {TXH:%0d STREAM:%0d NAME:%s TIME:%0t TYPE=\"%0s\"}", $realtime, this.get_handle(), stream.get_handle(), this.get_name(), open_time, type_name); endfunction : do_open protected virtual function void do_close(time close_time); if (m_text_db.open_db()) begin $fdisplay(m_text_db.m_file, " CLOSE_RECORDER @%0t {TXH:%0d TIME=%0t}", $realtime, this.get_handle(), close_time); end endfunction : do_close protected virtual function void do_free(); if (m_text_db.open_db()) begin $fdisplay(m_text_db.m_file, " FREE_RECORDER @%0t {TXH:%0d}", $realtime, this.get_handle()); end m_text_db = null; endfunction : do_free protected virtual function void do_record_field(string name, uvm_bitstream_t value, int size, uvm_radix_enum radix); if (!radix) radix = default_radix; write_attribute(m_current_context(name), value, radix, size); endfunction : do_record_field protected virtual function void do_record_field_int(string name, uvm_integral_t value, int size, uvm_radix_enum radix); if (!radix) radix = default_radix; write_attribute_int(m_current_context(name), value, radix, size); endfunction : do_record_field_int protected virtual function void do_record_field_real(string name, real value); bit [63:0] ival = $realtobits(value); write_attribute_int(m_current_context(name), ival, UVM_REAL, 64); endfunction : do_record_field_real local string m_object_names[$]; local function string m_current_context(string name=""); if (m_object_names.size() == 0) return name; else if ((m_object_names.size() == 1) && (name=="")) return m_object_names[0]; else begin string full_name; foreach(m_object_names[i]) begin if (i == m_object_names.size() - 1) full_name = {full_name, m_object_names[i]}; else full_name = {full_name, m_object_names[i], "."}; end if (name != "") return {full_name, ".", name}; else return full_name; end endfunction : m_current_context protected virtual function void do_record_object(string name, uvm_object value); int v; string str; if(identifier) begin if(value != null) begin v = value.get_inst_id(); end write_attribute_int("inst_id", v, UVM_DEC, 32); end if (get_active_object_depth() > 1) m_object_names.push_back(name); super.do_record_object(name, value); if (get_active_object_depth() > 1) void'(m_object_names.pop_back()); endfunction : do_record_object protected virtual function void do_record_string(string name, string value); if (m_text_db.open_db()) begin $fdisplay(m_text_db.m_file, " SET_ATTR @%0t {TXH:%0d NAME:%s VALUE:%s RADIX:%s BITS=%0d}", $realtime, this.get_handle(), m_current_context(name), value, "UVM_STRING", 8+value.len()); end endfunction : do_record_string protected virtual function void do_record_time(string name, time value); write_attribute_int(m_current_context(name), value, UVM_TIME, 64); endfunction : do_record_time protected virtual function void do_record_generic(string name, string value, string type_name); write_attribute(m_current_context(name), uvm_string_to_bits(value), UVM_STRING, 8+value.len()); endfunction : do_record_generic function void write_attribute(string nm, uvm_bitstream_t value, uvm_radix_enum radix, int numbits=$bits(uvm_bitstream_t)); if (m_text_db.open_db()) begin $fdisplay(m_text_db.m_file, " SET_ATTR @%0t {TXH:%0d NAME:%s VALUE:%s RADIX:%s BITS=%0d}", $realtime, this.get_handle(), nm, uvm_bitstream_to_string(value, numbits, radix), radix.name(), numbits); end endfunction : write_attribute function void write_attribute_int(string nm, uvm_integral_t value, uvm_radix_enum radix, int numbits=$bits(uvm_bitstream_t)); if (m_text_db.open_db()) begin $fdisplay(m_text_db.m_file, " SET_ATTR @%0t {TXH:%0d NAME:%s VALUE:%s RADIX:%s BITS=%0d}", $realtime, this.get_handle(), nm, uvm_integral_to_string(value, numbits, radix), radix.name(), numbits); end endfunction : write_attribute_int string filename; bit filename_set; virtual function bit open_file(); if (!filename_set) begin m_text_db.set_file_name(filename); end return m_text_db.open_db(); endfunction virtual function int create_stream (string name, string t, string scope); uvm_text_tr_stream stream; if (open_file()) begin $cast(stream,m_text_db.open_stream(name, scope, t)); return stream.get_handle(); end return 0; endfunction virtual function void m_set_attribute (int txh, string nm, string value); if (open_file()) begin UVM_FILE file = m_text_db.m_file; $fdisplay(file," SET_ATTR @%0t {TXH:%0d NAME:%s VALUE:%s}", $realtime,txh,nm,value); end endfunction virtual function void set_attribute (int txh, string nm, logic [1023:0] value, uvm_radix_enum radix, int numbits=1024); if (open_file()) begin UVM_FILE file = m_text_db.m_file; $fdisplay(file, " SET_ATTR @%0t {TXH:%0d NAME:%s VALUE:%s RADIX:%s BITS=%0d}", $realtime, txh, nm, uvm_bitstream_to_string(value, numbits, radix), radix.name(), numbits); end endfunction virtual function int check_handle_kind (string htype, int handle); return ((uvm_recorder::get_recorder_from_handle(handle) != null) || (uvm_tr_stream::get_stream_from_handle(handle) != null)); endfunction virtual function int begin_tr(string txtype, int stream, string nm, string label="", string desc="", time begin_time=0); if (open_file()) begin uvm_tr_stream stream_obj = uvm_tr_stream::get_stream_from_handle(stream); uvm_recorder recorder; if (stream_obj == null) return -1; recorder = stream_obj.open_recorder(nm, begin_time, txtype); return recorder.get_handle(); end return -1; endfunction virtual function void end_tr (int handle, time end_time=0); if (open_file()) begin uvm_recorder record = uvm_recorder::get_recorder_from_handle(handle); if (record != null) begin record.close(end_time); end end endfunction virtual function void link_tr(int h1, int h2, string relation=""); if (open_file()) $fdisplay(m_text_db.m_file," LINK @%0t {TXH1:%0d TXH2:%0d RELATION=%0s}", $realtime,h1,h2,relation); endfunction virtual function void free_tr(int handle); if (open_file()) begin uvm_recorder record = uvm_recorder::get_recorder_from_handle(handle); if (record != null) begin record.free(); end end endfunction endclass : uvm_text_recorder typedef class uvm_object; typedef class uvm_event; typedef class uvm_callback; typedef class uvm_callbacks; virtual class uvm_event_callback#(type T=uvm_object) extends uvm_callback; function new (string name=""); super.new(name); endfunction virtual function bit pre_trigger (uvm_event#(T) e, T data); return 0; endfunction virtual function void post_trigger (uvm_event#(T) e, T data); return; endfunction virtual function uvm_object create (string name=""); return null; endfunction endclass virtual class uvm_event_base extends uvm_object; typedef uvm_abstract_object_registry#(uvm_event_base,"uvm_event_base") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_event_base"; endfunction : type_name virtual function string get_type_name(); return "uvm_event_base"; endfunction : get_type_name protected event m_event; protected int num_waiters; protected bit on; protected time trigger_time=0; function new (string name=""); super.new(name); endfunction virtual task wait_on (bit delta = 0); if (on) begin if (delta) #0; return; end num_waiters++; @on; endtask virtual task wait_off (bit delta = 0); if (!on) begin if (delta) #0; return; end num_waiters++; @on; endtask virtual task wait_trigger (); num_waiters++; @m_event; endtask virtual task wait_ptrigger (); if (m_event.triggered) return; num_waiters++; @m_event; endtask virtual function time get_trigger_time (); return trigger_time; endfunction virtual function bit is_on (); return (on == 1); endfunction virtual function bit is_off (); return (on == 0); endfunction virtual function void reset (bit wakeup = 0); event e; if (wakeup) ->m_event; m_event = e; num_waiters = 0; on = 0; trigger_time = 0; endfunction virtual function void cancel (); if (num_waiters > 0) num_waiters--; endfunction virtual function int get_num_waiters (); return num_waiters; endfunction virtual function void do_print (uvm_printer printer); printer.print_field_int("num_waiters", num_waiters, $bits(num_waiters), UVM_DEC, ".", "int"); printer.print_field_int("on", on, $bits(on), UVM_BIN, ".", "bit"); printer.print_time("trigger_time", trigger_time); endfunction virtual function void do_copy (uvm_object rhs); uvm_event_base e; super.do_copy(rhs); if(!$cast(e, rhs) || (e==null)) return; m_event = e.m_event; num_waiters = e.num_waiters; on = e.on; trigger_time = e.trigger_time; endfunction endclass class uvm_event#(type T=uvm_object) extends uvm_event_base; typedef uvm_event#(T) this_type; typedef uvm_event_callback#(T) cb_type; typedef uvm_callbacks#(this_type, cb_type) cbs_type; static local function bit m_register_cb(); return uvm_callbacks#(this_type,cb_type)::m_register_pair( "uvm_pkg::uvm_event#(T)", "uvm_pkg::uvm_event_callback#(T)" ); endfunction : m_register_cb static local bit m_cb_registered = m_register_cb(); typedef uvm_object_registry #(this_type) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); this_type tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction virtual function string get_type_name(); return "uvm_pkg::uvm_event#(T)"; endfunction : get_type_name local T trigger_data; local T default_data; function new (string name=""); super.new(name); endfunction virtual task wait_trigger_data (output T data); wait_trigger(); data = get_trigger_data(); endtask virtual task wait_ptrigger_data (output T data); wait_ptrigger(); data = get_trigger_data(); endtask virtual function void trigger (T data=get_default_data()); int skip; cb_type cb_q[$]; skip=0; cbs_type::get_all(cb_q, this); foreach (cb_q[i]) skip += cb_q[i].pre_trigger(this, data); if (skip==0) begin ->m_event; foreach (cb_q[i]) cb_q[i].post_trigger(this, data); num_waiters = 0; on = 1; trigger_time = $realtime; trigger_data = data; end endfunction virtual function T get_trigger_data (); return trigger_data; endfunction virtual function T get_default_data(); return default_data; endfunction : get_default_data virtual function void set_default_data(T data); default_data = data; endfunction : set_default_data virtual function void do_print (uvm_printer printer); uvm_event#(uvm_object) oe; cb_type cb_q[$]; super.do_print(printer); cbs_type::get_all(cb_q, this); printer.print_array_header("callbacks", cb_q.size(), "queue"); foreach(cb_q[e]) printer.print_object($sformatf("[%0d]", e), cb_q[e], "["); printer.print_array_footer(cb_q.size()); if ($cast(oe, this)) begin printer.print_object("trigger_data", oe.get_trigger_data()); end else begin uvm_event#(string) se; if ($cast(se, this)) printer.print_string("trigger_data", se.get_trigger_data()); end endfunction virtual function void do_copy (uvm_object rhs); this_type e; cb_type cb_q[$]; super.do_copy(rhs); if(!$cast(e, rhs) || (e==null)) return; trigger_data = e.trigger_data; begin cbs_type::get_all(cb_q, this); foreach(cb_q[i]) cbs_type::delete(this, cb_q[i]); cb_q.delete(); cbs_type::get_all(cb_q, e); foreach(cb_q[i]) cbs_type::add(this, cb_q[i]); end endfunction endclass class uvm_barrier extends uvm_object; local int threshold; local int num_waiters; local bit at_threshold; local bit auto_reset; local uvm_event#(uvm_object) m_event; typedef uvm_object_registry#(uvm_barrier,"uvm_barrier") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_barrier tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_barrier"; endfunction : type_name virtual function string get_type_name(); return "uvm_barrier"; endfunction : get_type_name function new (string name="", int threshold=0); super.new(name); m_event = new({"barrier_",name}); this.threshold = threshold; num_waiters = 0; auto_reset = 1; at_threshold = 0; endfunction virtual task wait_for(); if (at_threshold) return; num_waiters++; if (num_waiters >= threshold) begin if (!auto_reset) at_threshold=1; m_trigger(); return; end m_event.wait_trigger(); endtask virtual function void reset (bit wakeup=1); at_threshold = 0; if (num_waiters) begin if (wakeup) m_event.trigger(); else m_event.reset(); end num_waiters = 0; endfunction virtual function void set_auto_reset (bit value=1); at_threshold = 0; auto_reset = value; endfunction virtual function void set_threshold (int threshold); this.threshold = threshold; if (threshold <= num_waiters) reset(1); endfunction virtual function int get_threshold (); return threshold; endfunction virtual function int get_num_waiters (); return num_waiters; endfunction virtual function void cancel (); m_event.cancel(); num_waiters = m_event.get_num_waiters(); endfunction local task m_trigger(); m_event.trigger(); num_waiters=0; #0; endtask virtual function void do_print (uvm_printer printer); printer.print_field_int("threshold", threshold, $bits(threshold), UVM_DEC, ".", "int"); printer.print_field_int("num_waiters", num_waiters, $bits(num_waiters), UVM_DEC, ".", "int"); printer.print_field_int("at_threshold", at_threshold, $bits(at_threshold), UVM_BIN, ".", "bit"); printer.print_field_int("auto_reset", auto_reset, $bits(auto_reset), UVM_BIN, ".", "bit"); endfunction virtual function void do_copy (uvm_object rhs); uvm_barrier b; super.do_copy(rhs); if(!$cast(b, rhs) || (b==null)) return; threshold = b.threshold; num_waiters = b.num_waiters; at_threshold = b.at_threshold; auto_reset = b.auto_reset; m_event = b.m_event; endfunction endclass typedef class uvm_root; typedef class uvm_callback; typedef class uvm_callbacks_base; class uvm_typeid_base; static string typename; static uvm_callbacks_base typeid_map[uvm_typeid_base]; static uvm_typeid_base type_map[uvm_callbacks_base]; endclass class uvm_typeid#(type T=uvm_object) extends uvm_typeid_base; static uvm_typeid#(T) m_b_inst; static function uvm_typeid#(T) get(); if(m_b_inst == null) m_b_inst = new; return m_b_inst; endfunction endclass class uvm_callbacks_base extends uvm_object; typedef uvm_callbacks_base this_type; static bit m_tracing = 1; static this_type m_b_inst; static uvm_pool#(uvm_object,uvm_queue#(uvm_callback)) m_pool; static function this_type m_initialize(); if(m_b_inst == null) begin m_b_inst = new; m_pool = new; end return m_b_inst; endfunction this_type m_this_type[$]; uvm_typeid_base m_super_type; uvm_typeid_base m_derived_types[$]; virtual function bit m_am_i_a(uvm_object obj); return 0; endfunction virtual function bit m_is_for_me(uvm_callback cb); return 0; endfunction virtual function bit m_is_registered(uvm_object obj, uvm_callback cb); return 0; endfunction virtual function uvm_queue#(uvm_callback) m_get_tw_cb_q(uvm_object obj); return null; endfunction virtual function void m_add_tw_cbs(uvm_callback cb, uvm_apprepend ordering); endfunction virtual function bit m_delete_tw_cbs(uvm_callback cb); return 0; endfunction function bit check_registration(uvm_object obj, uvm_callback cb); this_type dt; if (m_is_registered(obj,cb)) return 1; foreach(m_this_type[i]) if(m_b_inst != m_this_type[i] && m_this_type[i].m_is_registered(obj,cb)) return 1; if(obj == null) begin foreach(m_derived_types[i]) begin dt = uvm_typeid_base::typeid_map[m_derived_types[i] ]; if(dt != null && dt.check_registration(null,cb)) return 1; end end return 0; endfunction endclass class uvm_typed_callbacks#(type T=uvm_object) extends uvm_callbacks_base; static uvm_queue#(uvm_callback) m_tw_cb_q; static string m_typename; typedef uvm_typed_callbacks#(T) this_type; typedef uvm_callbacks_base super_type; static this_type m_t_inst; static function this_type m_initialize(); if(m_t_inst == null) begin void'(super_type::m_initialize()); m_t_inst = new; m_t_inst.m_tw_cb_q = new("typewide_queue"); end return m_t_inst; endfunction virtual function bit m_am_i_a(uvm_object obj); T this_type; if (obj == null) return 1; return($cast(this_type,obj)); endfunction virtual function uvm_queue#(uvm_callback) m_get_tw_cb_q(uvm_object obj); if(m_am_i_a(obj)) begin foreach(m_derived_types[i]) begin super_type dt; dt = uvm_typeid_base::typeid_map[m_derived_types[i] ]; if(dt != null && dt != this) begin m_get_tw_cb_q = dt.m_get_tw_cb_q(obj); if(m_get_tw_cb_q != null) return m_get_tw_cb_q; end end return m_t_inst.m_tw_cb_q; end else return null; endfunction static function int m_cb_find(uvm_queue#(uvm_callback) q, uvm_callback cb); for(int i=0; i str.len() ? max_cb_name : str.len(); str = "(*)"; max_inst_name = max_inst_name > str.len() ? max_inst_name : str.len(); end if(obj ==null) begin if(m_t_inst.m_pool.first(bobj)) begin do if($cast(me,bobj)) break; while(m_t_inst.m_pool.next(bobj)); end if(me != null || m_t_inst.m_tw_cb_q.size()) begin qs.push_back($sformatf("Registered callbacks for all instances of %s\n", tname)); qs.push_back("---------------------------------------------------------------\n"); end if(me != null) begin do begin if($cast(me,bobj)) begin q = m_t_inst.m_pool.get(bobj); if (q==null) begin q=new; m_t_inst.m_pool.add(bobj,q); end for(int i=0; i str.len() ? max_cb_name : str.len(); str = bobj.get_full_name(); max_inst_name = max_inst_name > str.len() ? max_inst_name : str.len(); end end end while (m_t_inst.m_pool.next(bobj)); end else begin qs.push_back($sformatf("No callbacks registered for any instances of type %s\n", tname)); end end else begin if(m_t_inst.m_pool.exists(bobj) || m_t_inst.m_tw_cb_q.size()) begin qs.push_back($sformatf("Registered callbacks for instance %s of %s\n", obj.get_full_name(), tname)); qs.push_back("---------------------------------------------------------------\n"); end if(m_t_inst.m_pool.exists(bobj)) begin q = m_t_inst.m_pool.get(bobj); if(q==null) begin q=new; m_t_inst.m_pool.add(bobj,q); end for(int i=0; i str.len() ? max_cb_name : str.len(); str = bobj.get_full_name(); max_inst_name = max_inst_name > str.len() ? max_inst_name : str.len(); end end end if(!cbq.size()) begin if(obj == null) str = "*"; else str = obj.get_full_name(); qs.push_back($sformatf("No callbacks registered for instance %s of type %s\n", str, tname)); end foreach (cbq[i]) begin qs.push_back($sformatf("%s %s %s on %s %s\n", cbq[i], blanks.substr(0,max_cb_name-cbq[i].len()-1), inst_q[i], blanks.substr(0,max_inst_name - inst_q[i].len()-1), mode_q[i])); end begin if (uvm_report_enabled(UVM_NONE,UVM_INFO,"UVM/CB/DISPLAY")) uvm_report_info ("UVM/CB/DISPLAY", uvm_pkg::m_uvm_string_queue_join(qs), UVM_NONE, "t/uvm/src/base/uvm_callback.svh", 428, "", 1); end m_tracing = 1; endfunction endclass class uvm_callbacks #(type T=uvm_object, type CB=uvm_callback) extends uvm_typed_callbacks#(T); typedef uvm_typed_callbacks#(T) super_type; typedef uvm_callbacks#(T,CB) this_type; local static this_type m_inst; static uvm_typeid_base m_typeid; static uvm_typeid_base m_cb_typeid; static string m_typename; static string m_cb_typename; static uvm_callbacks#(T,uvm_callback) m_base_inst; bit m_registered; static function this_type get(); if (m_inst == null) begin uvm_typeid_base cb_base_type; void'(super_type::m_initialize()); cb_base_type = uvm_typeid#(uvm_callback)::get(); m_cb_typeid = uvm_typeid#(CB)::get(); m_typeid = uvm_typeid#(T)::get(); m_inst = new; if (cb_base_type == m_cb_typeid) begin $cast(m_base_inst, m_inst); m_t_inst = m_base_inst; uvm_typeid_base::typeid_map[m_typeid] = m_inst; uvm_typeid_base::type_map[m_b_inst] = m_typeid; end else begin m_base_inst = uvm_callbacks#(T,uvm_callback)::get(); m_base_inst.m_this_type.push_back(m_inst); end if (m_inst == null) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"CB/INTERNAL")) uvm_report_fatal ("CB/INTERNAL", "get(): m_inst is null", UVM_NONE, "t/uvm/src/base/uvm_callback.svh", 540, "", 1); end end return m_inst; endfunction static function bit m_register_pair(string tname="", cbname=""); this_type inst = get(); m_typename = tname; super_type::m_typename = tname; m_typeid.typename = tname; m_cb_typename = cbname; m_cb_typeid.typename = cbname; inst.m_registered = 1; return 1; endfunction virtual function bit m_is_registered(uvm_object obj, uvm_callback cb); if(m_is_for_me(cb) && m_am_i_a(obj)) begin return m_registered; end endfunction virtual function bit m_is_for_me(uvm_callback cb); CB this_cb; return($cast(this_cb,cb)); endfunction static function void add(T obj, uvm_callback cb, uvm_apprepend ordering=UVM_APPEND); uvm_queue#(uvm_callback) q; string nm,tnm; void'(get()); if (cb==null) begin if (obj==null) nm = "(*)"; else nm = obj.get_full_name(); if (m_base_inst.m_typename!="") tnm = m_base_inst.m_typename; else if (obj != null) tnm = obj.get_type_name(); else tnm = "uvm_object"; uvm_report_error("CBUNREG", {"Null callback object cannot be registered with object ", nm, " (", tnm, ")"}, UVM_NONE); return; end if (!m_base_inst.check_registration(obj,cb)) begin if (obj==null) nm = "(*)"; else nm = obj.get_full_name(); if (m_base_inst.m_typename!="") tnm = m_base_inst.m_typename; else if(obj != null) tnm = obj.get_type_name(); else tnm = "uvm_object"; uvm_report_warning("CBUNREG", {"Callback ", cb.get_name(), " cannot be registered with object ", nm, " because callback type ", cb.get_type_name(), " is not registered with object type ", tnm }, UVM_NONE); end if(obj == null) begin if (m_cb_find(m_t_inst.m_tw_cb_q,cb) != -1) begin if (m_base_inst.m_typename!="") tnm = m_base_inst.m_typename; else tnm = "uvm_object"; uvm_report_warning("CBPREG", {"Callback object ", cb.get_name(), " is already registered with type ", tnm }, UVM_NONE); end else begin m_t_inst.m_add_tw_cbs(cb,ordering); end end else begin q = m_base_inst.m_pool.get(obj); if (q==null) begin q=new; m_base_inst.m_pool.add(obj,q); end if(q.size() == 0) begin uvm_report_object o; if($cast(o,obj)) begin uvm_queue#(uvm_callback) qr; void'(uvm_callbacks#(uvm_report_object, uvm_callback)::get()); qr = uvm_callbacks#(uvm_report_object,uvm_callback)::m_t_inst.m_tw_cb_q; for(int i=0; i=0; --itr) if ($cast(cb, q.get(itr)) && cb.callback_mode()) return cb; return null; endfunction static function CB get_next (ref int itr, input T obj); uvm_queue#(uvm_callback) q; CB cb; void'(get()); m_get_q(q,obj); for(itr = itr+1; itr= 0; --itr) if($cast(cb, q.get(itr)) && cb.callback_mode()) return cb; return null; endfunction static function void get_all ( ref CB all_callbacks[$], input T obj=null ); uvm_queue#(uvm_callback) q; CB cb; CB callbacks_to_append[$]; CB unique_callbacks_to_append[$]; void'( get() ); if ((obj == null) || (!m_pool.exists(obj))) begin for (int qi=0; qi= m_max_quit_count); endfunction function int get_severity_count(uvm_severity severity); return m_severity_count[severity]; endfunction function void set_severity_count(uvm_severity severity, int count); m_severity_count[severity] = count < 0 ? 0 : count; endfunction function void incr_severity_count(uvm_severity severity); m_severity_count[severity]++; endfunction function void reset_severity_counts(); uvm_severity s; s = s.first(); forever begin m_severity_count[s] = 0; if(s == s.last()) break; s = s.next(); end endfunction function int get_id_count(string id); if(m_id_count.exists(id)) return m_id_count[id]; return 0; endfunction function void set_id_count(string id, int count); m_id_count[id] = count < 0 ? 0 : count; endfunction function void incr_id_count(string id); if(m_id_count.exists(id)) m_id_count[id]++; else m_id_count[id] = 1; endfunction virtual function void set_message_database(uvm_tr_database database); m_message_db = database; endfunction : set_message_database virtual function uvm_tr_database get_message_database(); return m_message_db; endfunction : get_message_database virtual function void get_severity_set(output uvm_severity q[$]); foreach(m_severity_count[idx]) q.push_back(idx); endfunction virtual function void get_id_set(output string q[$]); foreach(m_id_count[idx]) q.push_back(idx); endfunction function void f_display(UVM_FILE file, string str); if (file == 0) $display("%s", str); else $fdisplay(file, "%s", str); endfunction virtual function void process_report_message(uvm_report_message report_message); uvm_report_handler l_report_handler = report_message.get_report_handler(); process p = process::self(); bit report_ok = 1; report_message.set_report_server(this); if(report_ok) report_ok = uvm_report_catcher::process_all_report_catchers(report_message); if(uvm_action_type'(report_message.get_action()) == UVM_NO_ACTION) report_ok = 0; if(report_ok) begin string m; uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_report_server svr = cs.get_report_server(); if (report_message.get_action() & (UVM_LOG|UVM_DISPLAY)) m = svr.compose_report_message(report_message); svr.execute_report_message(report_message, m); end endfunction virtual function void execute_report_message(uvm_report_message report_message, string composed_message); process p = process::self(); incr_severity_count(report_message.get_severity()); incr_id_count(report_message.get_id()); if (record_all_messages) report_message.set_action(report_message.get_action() | UVM_RM_RECORD); if(report_message.get_action() & UVM_RM_RECORD) begin uvm_tr_stream stream; uvm_report_object ro = report_message.get_report_object(); uvm_report_handler rh = report_message.get_report_handler(); if (m_streams.exists(ro.get_name()) && (m_streams[ro.get_name()].exists(rh.get_name()))) stream = m_streams[ro.get_name()][rh.get_name()]; if (stream == null) begin uvm_tr_database db; db = get_message_database(); if (db == null) begin uvm_coreservice_t cs = uvm_coreservice_t::get(); db = cs.get_default_tr_database(); end if (db != null) begin stream = db.open_stream(ro.get_name(), rh.get_name(), "MESSAGES"); m_streams[ro.get_name()][rh.get_name()] = stream; end end if (stream != null) begin uvm_recorder recorder = stream.open_recorder(report_message.get_name(),,report_message.get_type_name()); if (recorder != null) begin report_message.record(recorder); recorder.free(); end end end if(report_message.get_action() & UVM_DISPLAY) $display("%s", composed_message); if(report_message.get_action() & UVM_LOG) if( (report_message.get_file() == 0) || (report_message.get_file() != 32'h8000_0001) ) begin UVM_FILE tmp_file = report_message.get_file(); if((report_message.get_file() & 32'h8000_0000) == 0) begin tmp_file = report_message.get_file() & 32'hffff_fffe; end f_display(tmp_file, composed_message); end if(report_message.get_action() & UVM_COUNT) begin if(get_max_quit_count() != 0) begin incr_quit_count(); if(is_quit_count_reached()) begin report_message.set_action(report_message.get_action() | UVM_EXIT); end end end if(report_message.get_action() & UVM_EXIT) begin uvm_root l_root; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); l_root = cs.get_root(); l_root.die(); end if (report_message.get_action() & UVM_STOP) $stop; endfunction virtual function string compose_report_message(uvm_report_message report_message, string report_object_name = ""); string sev_string; uvm_severity l_severity; uvm_verbosity l_verbosity; string filename_line_string; string time_str; string line_str; string context_str; string verbosity_str; string terminator_str; string msg_body_str; uvm_report_message_element_container el_container; string prefix; uvm_report_handler l_report_handler; l_severity = report_message.get_severity(); sev_string = l_severity.name(); if (report_message.get_filename() != "") begin line_str.itoa(report_message.get_line()); filename_line_string = {report_message.get_filename(), "(", line_str, ") "}; end $swrite(time_str, "%0t", $time); if (report_message.get_context() != "") context_str = {"@@", report_message.get_context()}; if (show_verbosity) begin if ($cast(l_verbosity, report_message.get_verbosity())) verbosity_str = l_verbosity.name(); else verbosity_str.itoa(report_message.get_verbosity()); verbosity_str = {"(", verbosity_str, ")"}; end if (show_terminator) terminator_str = {" -",sev_string}; el_container = report_message.get_element_container(); if (el_container.size() == 0) msg_body_str = report_message.get_message(); else begin uvm_printer uvm_default_printer = uvm_printer::get_default() ; prefix = uvm_default_printer.get_line_prefix(); uvm_default_printer.set_line_prefix(" +"); msg_body_str = {report_message.get_message(), "\n", el_container.sprint()}; uvm_default_printer.set_line_prefix(prefix); end if (report_object_name == "") begin l_report_handler = report_message.get_report_handler(); report_object_name = l_report_handler.get_full_name(); end compose_report_message = {sev_string, verbosity_str, " ", filename_line_string, "@ ", time_str, ": ", report_object_name, context_str, " [", report_message.get_id(), "] ", msg_body_str, terminator_str}; endfunction virtual function void report_summarize(UVM_FILE file = UVM_STDOUT); string id; string name; string output_str; string q[$]; uvm_report_catcher::summarize(); q.push_back("\n--- UVM Report Summary ---\n\n"); if(m_max_quit_count != 0) begin if ( m_quit_count >= m_max_quit_count ) q.push_back("Quit count reached!\n"); q.push_back($sformatf("Quit count : %5d of %5d\n",m_quit_count, m_max_quit_count)); end q.push_back("** Report counts by severity\n"); foreach(m_severity_count[s]) begin q.push_back($sformatf("%s :%5d\n", s.name(), m_severity_count[s])); end if (enable_report_id_count_summary) begin q.push_back("** Report counts by id\n"); foreach(m_id_count[id]) q.push_back($sformatf("[%s] %5d\n", id, m_id_count[id])); end begin if (uvm_report_enabled(UVM_NONE,UVM_INFO,"UVM/REPORT/SERVER")) uvm_report_info ("UVM/REPORT/SERVER", uvm_pkg::m_uvm_string_queue_join(q), UVM_NONE, "t/uvm/src/base/uvm_report_server.svh", 864, "", 1); end endfunction endclass `define UVM_REPORT_HANDLER_SVH typedef class uvm_report_object; typedef class uvm_report_server; typedef uvm_pool#(string, uvm_action) uvm_id_actions_array; typedef uvm_pool#(string, UVM_FILE) uvm_id_file_array; typedef uvm_pool#(string, int) uvm_id_verbosities_array; typedef uvm_pool#(uvm_severity, uvm_severity) uvm_sev_override_array; class uvm_report_handler extends uvm_object; int m_max_verbosity_level; uvm_id_verbosities_array id_verbosities; uvm_id_verbosities_array severity_id_verbosities[uvm_severity]; uvm_id_actions_array id_actions; uvm_action severity_actions[uvm_severity]; uvm_id_actions_array severity_id_actions[uvm_severity]; uvm_sev_override_array sev_overrides; uvm_sev_override_array sev_id_overrides [string]; UVM_FILE default_file_handle; uvm_id_file_array id_file_handles; UVM_FILE severity_file_handles[uvm_severity]; uvm_id_file_array severity_id_file_handles[uvm_severity]; typedef uvm_object_registry#(uvm_report_handler,"uvm_report_handler") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_report_handler tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_report_handler"; endfunction : type_name virtual function string get_type_name(); return "uvm_report_handler"; endfunction : get_type_name function new(string name = "uvm_report_handler"); super.new(name); initialize(); endfunction virtual function void do_print (uvm_printer printer); uvm_verbosity l_verbosity; uvm_severity l_severity; string idx; int l_int; if ($cast(l_verbosity, m_max_verbosity_level)) printer.print_generic("max_verbosity_level", "uvm_verbosity", 32, l_verbosity.name()); else printer.print_field("max_verbosity_level", m_max_verbosity_level, 32, UVM_DEC, ".", "int"); if(id_verbosities.first(idx)) begin printer.print_array_header("id_verbosities",id_verbosities.num(), "uvm_pool"); do begin l_int = id_verbosities.get(idx); if ($cast(l_verbosity, l_int)) printer.print_generic($sformatf("[%s]", idx), "uvm_verbosity", 32, l_verbosity.name()); else begin string l_str; l_str.itoa(l_int); printer.print_generic($sformatf("[%s]", idx), "int", 32, l_str); end end while(id_verbosities.next(idx)); printer.print_array_footer(); end if(severity_id_verbosities.size() != 0) begin int _total_cnt; foreach (severity_id_verbosities[l_severity]) _total_cnt += severity_id_verbosities[l_severity].num(); printer.print_array_header("severity_id_verbosities", _total_cnt, "array"); if(severity_id_verbosities.first(l_severity)) begin do begin uvm_id_verbosities_array id_v_ary = severity_id_verbosities[l_severity]; if(id_v_ary.first(idx)) do begin l_int = id_v_ary.get(idx); if ($cast(l_verbosity, l_int)) printer.print_generic($sformatf("[%s:%s]", l_severity.name(), idx), "uvm_verbosity", 32, l_verbosity.name()); else begin string l_str; l_str.itoa(l_int); printer.print_generic($sformatf("[%s:%s]", l_severity.name(), idx), "int", 32, l_str); end end while(id_v_ary.next(idx)); end while(severity_id_verbosities.next(l_severity)); end printer.print_array_footer(); end if(id_actions.first(idx)) begin printer.print_array_header("id_actions",id_actions.num(), "uvm_pool"); do begin l_int = id_actions.get(idx); printer.print_generic($sformatf("[%s]", idx), "uvm_action", 32, format_action(l_int)); end while(id_actions.next(idx)); printer.print_array_footer(); end if(severity_actions.first(l_severity)) begin printer.print_array_header("severity_actions",4,"array"); do begin printer.print_generic($sformatf("[%s]", l_severity.name()), "uvm_action", 32, format_action(severity_actions[l_severity])); end while(severity_actions.next(l_severity)); printer.print_array_footer(); end if(severity_id_actions.size() != 0) begin int _total_cnt; foreach (severity_id_actions[l_severity]) _total_cnt += severity_id_actions[l_severity].num(); printer.print_array_header("severity_id_actions", _total_cnt, "array"); if(severity_id_actions.first(l_severity)) begin do begin uvm_id_actions_array id_a_ary = severity_id_actions[l_severity]; if(id_a_ary.first(idx)) do begin printer.print_generic($sformatf("[%s:%s]", l_severity.name(), idx), "uvm_action", 32, format_action(id_a_ary.get(idx))); end while(id_a_ary.next(idx)); end while(severity_id_actions.next(l_severity)); end printer.print_array_footer(); end if(sev_overrides.first(l_severity)) begin printer.print_array_header("sev_overrides",sev_overrides.num(), "uvm_pool"); do begin uvm_severity l_severity_new = sev_overrides.get(l_severity); printer.print_generic($sformatf("[%s]", l_severity.name()), "uvm_severity", 32, l_severity_new.name()); end while(sev_overrides.next(l_severity)); printer.print_array_footer(); end if(sev_id_overrides.size() != 0) begin int _total_cnt; foreach (sev_id_overrides[idx]) _total_cnt += sev_id_overrides[idx].num(); printer.print_array_header("sev_id_overrides", _total_cnt, "array"); if(sev_id_overrides.first(idx)) begin do begin uvm_sev_override_array sev_o_ary = sev_id_overrides[idx]; if(sev_o_ary.first(l_severity)) do begin uvm_severity new_sev = sev_o_ary.get(l_severity); printer.print_generic($sformatf("[%s:%s]", l_severity.name(), idx), "uvm_severity", 32, new_sev.name()); end while(sev_o_ary.next(l_severity)); end while(sev_id_overrides.next(idx)); end printer.print_array_footer(); end printer.print_field("default_file_handle", default_file_handle, 32, UVM_HEX, ".", "int"); if(id_file_handles.first(idx)) begin printer.print_array_header("id_file_handles",id_file_handles.num(), "uvm_pool"); do begin printer.print_field($sformatf("[%s]", idx), id_file_handles.get(idx), 32, UVM_HEX, ".", "UVM_FILE"); end while(id_file_handles.next(idx)); printer.print_array_footer(); end if(severity_file_handles.first(l_severity)) begin printer.print_array_header("severity_file_handles",4,"array"); do begin printer.print_field($sformatf("[%s]", l_severity.name()), severity_file_handles[l_severity], 32, UVM_HEX, ".", "UVM_FILE"); end while(severity_file_handles.next(l_severity)); printer.print_array_footer(); end if(severity_id_file_handles.size() != 0) begin int _total_cnt; foreach (severity_id_file_handles[l_severity]) _total_cnt += severity_id_file_handles[l_severity].num(); printer.print_array_header("severity_id_file_handles", _total_cnt, "array"); if(severity_id_file_handles.first(l_severity)) begin do begin uvm_id_file_array id_f_ary = severity_id_file_handles[l_severity]; if(id_f_ary.first(idx)) do begin printer.print_field($sformatf("[%s:%s]", l_severity.name(), idx), id_f_ary.get(idx), 32, UVM_HEX, ".", "UVM_FILE"); end while(id_f_ary.next(idx)); end while(severity_id_file_handles.next(l_severity)); end printer.print_array_footer(); end endfunction virtual function void process_report_message(uvm_report_message report_message); process p = process::self(); uvm_report_server srvr = uvm_report_server::get_server(); string id = report_message.get_id(); uvm_severity severity = report_message.get_severity(); if(sev_id_overrides.exists(id)) begin if(sev_id_overrides[id].exists(uvm_severity'(severity))) begin severity = sev_id_overrides[id].get(severity); report_message.set_severity(severity); end end else begin if(sev_overrides.exists(severity)) begin severity = sev_overrides.get(severity); report_message.set_severity(severity); end end report_message.set_file(get_file_handle(severity, id)); report_message.set_report_handler(this); report_message.set_action(get_action(severity, id)); srvr.process_report_message(report_message); endfunction static function string format_action(uvm_action action); string s; if(uvm_action_type'(action) == UVM_NO_ACTION) begin s = "NO ACTION"; end else begin s = ""; if(action & UVM_DISPLAY) s = {s, "DISPLAY "}; if(action & UVM_LOG) s = {s, "LOG "}; if(action & UVM_RM_RECORD) s = {s, "RM_RECORD "}; if(action & UVM_COUNT) s = {s, "COUNT "}; if(action & UVM_CALL_HOOK) s = {s, "CALL_HOOK "}; if(action & UVM_EXIT) s = {s, "EXIT "}; if(action & UVM_STOP) s = {s, "STOP "}; end return s; endfunction function void initialize(); set_default_file(0); m_max_verbosity_level = UVM_MEDIUM; id_actions=new(); id_verbosities=new(); id_file_handles=new(); sev_overrides=new(); set_severity_action(UVM_INFO, UVM_DISPLAY); set_severity_action(UVM_WARNING, UVM_DISPLAY); set_severity_action(UVM_ERROR, UVM_DISPLAY | UVM_COUNT); set_severity_action(UVM_FATAL, UVM_DISPLAY | UVM_EXIT); set_severity_file(UVM_INFO, default_file_handle); set_severity_file(UVM_WARNING, default_file_handle); set_severity_file(UVM_ERROR, default_file_handle); set_severity_file(UVM_FATAL, default_file_handle); endfunction local function UVM_FILE get_severity_id_file(uvm_severity severity, string id); uvm_id_file_array array; if(severity_id_file_handles.exists(severity)) begin array = severity_id_file_handles[severity]; if(array.exists(id)) return array.get(id); end if(id_file_handles.exists(id)) return id_file_handles.get(id); if(severity_file_handles.exists(severity)) return severity_file_handles[severity]; return default_file_handle; endfunction function void set_verbosity_level(int verbosity_level); m_max_verbosity_level = verbosity_level; endfunction function int get_verbosity_level(uvm_severity severity=UVM_INFO, string id="" ); uvm_id_verbosities_array array; if(severity_id_verbosities.exists(severity)) begin array = severity_id_verbosities[severity]; if(array.exists(id)) begin return array.get(id); end end if(id_verbosities.exists(id)) begin return id_verbosities.get(id); end return m_max_verbosity_level; endfunction function uvm_action get_action(uvm_severity severity, string id); uvm_id_actions_array array; if(severity_id_actions.exists(severity)) begin array = severity_id_actions[severity]; if(array.exists(id)) return array.get(id); end if(id_actions.exists(id)) return id_actions.get(id); return severity_actions[severity]; endfunction function UVM_FILE get_file_handle(uvm_severity severity, string id); UVM_FILE file; file = get_severity_id_file(severity, id); if (file != 0) return file; if (id_file_handles.exists(id)) begin file = id_file_handles.get(id); if (file != 0) return file; end if (severity_file_handles.exists(severity)) begin file = severity_file_handles[severity]; if(file != 0) return file; end return default_file_handle; endfunction function void set_severity_action(input uvm_severity severity, input uvm_action action); severity_actions[severity] = action; endfunction function void set_id_action(input string id, input uvm_action action); id_actions.add(id, action); endfunction function void set_severity_id_action(uvm_severity severity, string id, uvm_action action); if(!severity_id_actions.exists(severity)) severity_id_actions[severity] = new; severity_id_actions[severity].add(id,action); endfunction function void set_id_verbosity(input string id, input int verbosity); id_verbosities.add(id, verbosity); endfunction function void set_severity_id_verbosity(uvm_severity severity, string id, int verbosity); if(!severity_id_verbosities.exists(severity)) severity_id_verbosities[severity] = new; severity_id_verbosities[severity].add(id,verbosity); endfunction function void set_default_file (UVM_FILE file); default_file_handle = file; endfunction function void set_severity_file (uvm_severity severity, UVM_FILE file); severity_file_handles[severity] = file; endfunction function void set_id_file (string id, UVM_FILE file); id_file_handles.add(id, file); endfunction function void set_severity_id_file(uvm_severity severity, string id, UVM_FILE file); if(!severity_id_file_handles.exists(severity)) severity_id_file_handles[severity] = new; severity_id_file_handles[severity].add(id, file); endfunction function void set_severity_override(uvm_severity cur_severity, uvm_severity new_severity); sev_overrides.add(cur_severity, new_severity); endfunction function void set_severity_id_override(uvm_severity cur_severity, string id, uvm_severity new_severity); uvm_sev_override_array arr; if(!sev_id_overrides.exists(id)) sev_id_overrides[id] = new; sev_id_overrides[id].add(cur_severity, new_severity); endfunction virtual function void report( uvm_severity severity, string name, string id, string message, int verbosity_level=UVM_MEDIUM, string filename="", int line=0, uvm_report_object client=null ); bit l_report_enabled = 0; uvm_report_message l_report_message; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); if (!uvm_report_enabled(verbosity_level, UVM_INFO, id)) return; if (client==null) client = cs.get_root(); l_report_message = uvm_report_message::new_report_message(); l_report_message.set_report_message(severity, id, message, verbosity_level, filename, line, name); l_report_message.set_report_object(client); l_report_message.set_action(get_action(severity,id)); process_report_message(l_report_message); endfunction endclass : uvm_report_handler `define UVM_REPORT_CLIENT_SVH typedef class uvm_component; typedef class uvm_env; typedef class uvm_root; class uvm_report_object extends uvm_object; uvm_report_handler m_rh; local bit m_rh_set; local function void m_rh_init(); if (!m_rh_set) set_report_handler(uvm_report_handler::type_id::create(get_name())); endfunction : m_rh_init function new(string name = ""); super.new(name); endfunction function uvm_report_object uvm_get_report_object(); return this; endfunction function int uvm_report_enabled(int verbosity, uvm_severity severity = UVM_INFO, string id = ""); if (get_report_verbosity_level(severity, id) < verbosity) return 0; return 1; endfunction virtual function void uvm_report( uvm_severity severity, string id, string message, int verbosity = (severity == uvm_severity'(UVM_ERROR)) ? UVM_LOW : (severity == uvm_severity'(UVM_FATAL)) ? UVM_NONE : UVM_MEDIUM, string filename = "", int line = 0, string context_name = "", bit report_enabled_checked =0); uvm_report_message l_report_message; if ((severity == UVM_INFO) && (report_enabled_checked == 0)) begin if (!uvm_report_enabled(verbosity, severity, id)) return; end l_report_message = uvm_report_message::new_report_message(); l_report_message.set_report_message(severity, id, message, verbosity, filename, line, context_name); uvm_process_report_message(l_report_message); endfunction virtual function void uvm_report_info( string id, string message, int verbosity = UVM_MEDIUM, string filename = "", int line = 0, string context_name = "", bit report_enabled_checked = 0); uvm_report (UVM_INFO, id, message, verbosity, filename, line, context_name, report_enabled_checked); endfunction virtual function void uvm_report_warning( string id, string message, int verbosity = UVM_MEDIUM, string filename = "", int line = 0, string context_name = "", bit report_enabled_checked = 0); uvm_report (UVM_WARNING, id, message, verbosity, filename, line, context_name, report_enabled_checked); endfunction virtual function void uvm_report_error( string id, string message, int verbosity = UVM_NONE, string filename = "", int line = 0, string context_name = "", bit report_enabled_checked = 0); uvm_report (UVM_ERROR, id, message, verbosity, filename, line, context_name, report_enabled_checked); endfunction virtual function void uvm_report_fatal( string id, string message, int verbosity = UVM_NONE, string filename = "", int line = 0, string context_name = "", bit report_enabled_checked = 0); uvm_report (UVM_FATAL, id, message, verbosity, filename, line, context_name, report_enabled_checked); endfunction virtual function void uvm_process_report_message(uvm_report_message report_message); m_rh_init(); report_message.set_report_object(this); m_rh.process_report_message(report_message); endfunction function int get_report_verbosity_level(uvm_severity severity=UVM_INFO, string id=""); m_rh_init(); return m_rh.get_verbosity_level(severity, id); endfunction function int get_report_max_verbosity_level(); m_rh_init(); return m_rh.m_max_verbosity_level; endfunction function void set_report_verbosity_level (int verbosity_level); m_rh_init(); m_rh.set_verbosity_level(verbosity_level); endfunction function void set_report_id_verbosity (string id, int verbosity); m_rh_init(); m_rh.set_id_verbosity(id, verbosity); endfunction function void set_report_severity_id_verbosity (uvm_severity severity, string id, int verbosity); m_rh_init(); m_rh.set_severity_id_verbosity(severity, id, verbosity); endfunction function int get_report_action(uvm_severity severity, string id); m_rh_init(); return m_rh.get_action(severity,id); endfunction function void set_report_severity_action (uvm_severity severity, uvm_action action); m_rh_init(); m_rh.set_severity_action(severity, action); endfunction function void set_report_id_action (string id, uvm_action action); m_rh_init(); m_rh.set_id_action(id, action); endfunction function void set_report_severity_id_action (uvm_severity severity, string id, uvm_action action); m_rh_init(); m_rh.set_severity_id_action(severity, id, action); endfunction function int get_report_file_handle(uvm_severity severity, string id); m_rh_init(); return m_rh.get_file_handle(severity,id); endfunction function void set_report_default_file (UVM_FILE file); m_rh_init(); m_rh.set_default_file(file); endfunction function void set_report_id_file (string id, UVM_FILE file); m_rh_init(); m_rh.set_id_file(id, file); endfunction function void set_report_severity_file (uvm_severity severity, UVM_FILE file); m_rh_init(); m_rh.set_severity_file(severity, file); endfunction function void set_report_severity_id_file (uvm_severity severity, string id, UVM_FILE file); m_rh_init(); m_rh.set_severity_id_file(severity, id, file); endfunction function void set_report_severity_override(uvm_severity cur_severity, uvm_severity new_severity); m_rh_init(); m_rh.set_severity_override(cur_severity, new_severity); endfunction function void set_report_severity_id_override(uvm_severity cur_severity, string id, uvm_severity new_severity); m_rh_init(); m_rh.set_severity_id_override(cur_severity, id, new_severity); endfunction function void set_report_handler(uvm_report_handler handler); m_rh = handler; m_rh_set = 1; endfunction function uvm_report_handler get_report_handler(); m_rh_init(); return m_rh; endfunction function void reset_report_handler; m_rh_init(); m_rh.initialize(); endfunction endclass typedef class uvm_event; typedef class uvm_event_pool; typedef class uvm_component; typedef class uvm_parent_child_link; virtual class uvm_transaction extends uvm_object; extern function new (string name="", uvm_component initiator=null); extern function void accept_tr (time accept_time = 0); extern virtual protected function void do_accept_tr (); extern function int begin_tr (time begin_time = 0); extern function int begin_child_tr (time begin_time = 0, int parent_handle = 0); extern virtual protected function void do_begin_tr (); extern function void end_tr (time end_time=0, bit free_handle=1); extern virtual protected function void do_end_tr (); extern function int get_tr_handle (); extern function void disable_recording (); extern function void enable_recording (uvm_tr_stream stream); extern function bit is_recording_enabled(); extern function bit is_active (); extern function uvm_event_pool get_event_pool (); extern function void set_initiator (uvm_component initiator); extern function uvm_component get_initiator (); extern function time get_accept_time (); extern function time get_begin_time (); extern function time get_end_time (); extern function void set_transaction_id(int id); extern function int get_transaction_id(); const local uvm_event_pool events = new("events"); extern virtual function void do_print (uvm_printer printer); extern virtual function void do_record (uvm_recorder recorder); extern virtual function void do_copy (uvm_object rhs); extern protected function int m_begin_tr (time begin_time=0, int parent_handle=0); local int m_transaction_id = -1; local time begin_time=-1; local time end_time=-1; local time accept_time=-1; local uvm_component initiator; local uvm_tr_stream stream_handle; local uvm_recorder tr_recorder; endclass function uvm_transaction::new (string name="", uvm_component initiator = null); super.new(name); this.initiator = initiator; m_transaction_id = -1; endfunction function void uvm_transaction::set_transaction_id(int id); m_transaction_id = id; endfunction function int uvm_transaction::get_transaction_id(); return (m_transaction_id); endfunction function void uvm_transaction::set_initiator(uvm_component initiator); this.initiator = initiator; endfunction function uvm_component uvm_transaction::get_initiator(); return initiator; endfunction function uvm_event_pool uvm_transaction::get_event_pool(); return events; endfunction function bit uvm_transaction::is_active(); return (end_time == -1); endfunction function time uvm_transaction::get_begin_time (); return begin_time; endfunction function time uvm_transaction::get_end_time (); return end_time; endfunction function time uvm_transaction::get_accept_time (); return accept_time; endfunction function void uvm_transaction::do_accept_tr(); return; endfunction function void uvm_transaction::do_begin_tr(); return; endfunction function void uvm_transaction::do_end_tr(); return; endfunction function void uvm_transaction::do_print (uvm_printer printer); string str; uvm_component tmp_initiator; super.do_print(printer); if(accept_time != -1) printer.print_time("accept_time", accept_time); if(begin_time != -1) printer.print_time("begin_time", begin_time); if(end_time != -1) printer.print_time("end_time", end_time); if(initiator != null) begin tmp_initiator = initiator; $swrite(str,"@%0d", tmp_initiator.get_inst_id()); printer.print_generic("initiator", initiator.get_type_name(), -1, str); end endfunction function void uvm_transaction::do_copy (uvm_object rhs); uvm_transaction txn; super.do_copy(rhs); if(rhs == null) return; if(!$cast(txn, rhs) ) return; accept_time = txn.accept_time; begin_time = txn.begin_time; end_time = txn.end_time; initiator = txn.initiator; stream_handle = txn.stream_handle; tr_recorder = txn.tr_recorder; endfunction function void uvm_transaction::do_record (uvm_recorder recorder); string s; super.do_record(recorder); if(accept_time != -1) recorder.record_field("accept_time", accept_time, $bits(accept_time), UVM_TIME); if(initiator != null) begin uvm_recursion_policy_enum p = recorder.get_recursion_policy(); recorder.set_recursion_policy(UVM_REFERENCE); recorder.record_object("initiator", initiator); recorder.set_recursion_policy(p); end endfunction function int uvm_transaction::get_tr_handle (); if (tr_recorder != null) return tr_recorder.get_handle(); else return 0; endfunction function void uvm_transaction::disable_recording (); this.stream_handle = null; endfunction function void uvm_transaction::enable_recording (uvm_tr_stream stream); this.stream_handle = stream; endfunction : enable_recording function bit uvm_transaction::is_recording_enabled (); return (this.stream_handle != null); endfunction function void uvm_transaction::accept_tr (time accept_time = 0); uvm_event#(uvm_object) e; if(accept_time != 0) this.accept_time = accept_time; else this.accept_time = $realtime; do_accept_tr(); e = events.get("accept"); if(e!=null) e.trigger(); endfunction function int uvm_transaction::begin_tr (time begin_time=0); return m_begin_tr(begin_time); endfunction function int uvm_transaction::begin_child_tr (time begin_time=0, int parent_handle=0); return m_begin_tr(begin_time, parent_handle); endfunction function int uvm_transaction::m_begin_tr (time begin_time=0, int parent_handle=0); time tmp_time = (begin_time == 0) ? $realtime : begin_time; uvm_recorder parent_recorder; if (parent_handle != 0) parent_recorder = uvm_recorder::get_recorder_from_handle(parent_handle); if (tr_recorder != null) end_tr(tmp_time); if(is_recording_enabled()) begin uvm_tr_database db = stream_handle.get_db(); this.end_time = -1; this.begin_time = tmp_time; if(parent_recorder == null) tr_recorder = stream_handle.open_recorder(get_type_name(), this.begin_time, "Begin_No_Parent, Link"); else begin tr_recorder = stream_handle.open_recorder(get_type_name(), this.begin_time, "Begin_End, Link"); if (tr_recorder != null) db.establish_link(uvm_parent_child_link::get_link(parent_recorder, tr_recorder)); end if (tr_recorder != null) m_begin_tr = tr_recorder.get_handle(); else m_begin_tr = 0; end else begin tr_recorder = null; this.end_time = -1; this.begin_time = tmp_time; m_begin_tr = 0; end do_begin_tr(); begin uvm_event#(uvm_object) begin_event ; begin_event = events.get("begin"); begin_event.trigger(); end endfunction function void uvm_transaction::end_tr (time end_time=0, bit free_handle=1); this.end_time = (end_time == 0) ? $realtime : end_time; do_end_tr(); if(is_recording_enabled() && (tr_recorder != null)) begin record(tr_recorder); tr_recorder.close(this.end_time); if(free_handle) begin tr_recorder.free(); end end tr_recorder = null; begin uvm_event#(uvm_object) end_event ; end_event = events.get("end") ; end_event.trigger(); end endfunction typedef class uvm_sequencer_base; typedef class uvm_domain; typedef class uvm_task_phase; typedef class uvm_phase_cb; class uvm_phase extends uvm_object; static local bit m_register_cb_uvm_phase_cb = uvm_callbacks#(uvm_phase,uvm_phase_cb)::m_register_pair("uvm_phase","uvm_phase_cb"); extern function new(string name="uvm_phase", uvm_phase_type phase_type=UVM_PHASE_SCHEDULE, uvm_phase parent=null); extern function uvm_phase_type get_phase_type(); extern virtual function void set_max_ready_to_end_iterations(int max); extern virtual function int get_max_ready_to_end_iterations(); extern static function void set_default_max_ready_to_end_iterations(int max); extern static function int get_default_max_ready_to_end_iterations(); extern function uvm_phase_state get_state(); extern function int get_run_count(); extern function uvm_phase find_by_name(string name, bit stay_in_scope=1); extern function uvm_phase find(uvm_phase phase, bit stay_in_scope=1); extern function bit is(uvm_phase phase); extern function bit is_before(uvm_phase phase); extern function bit is_after(uvm_phase phase); virtual function void exec_func(uvm_component comp, uvm_phase phase); endfunction virtual task exec_task(uvm_component comp, uvm_phase phase); endtask extern function void add(uvm_phase phase, uvm_phase with_phase=null, uvm_phase after_phase=null, uvm_phase before_phase=null, uvm_phase start_with_phase=null, uvm_phase end_with_phase=null ); extern function uvm_phase get_parent(); extern virtual function string get_full_name(); extern function uvm_phase get_schedule(bit hier = 0); extern function string get_schedule_name(bit hier = 0); extern function uvm_domain get_domain(); extern function uvm_phase get_imp(); extern function string get_domain_name(); extern function void get_adjacent_predecessor_nodes(ref uvm_phase pred[]); extern function void get_adjacent_successor_nodes(ref uvm_phase succ[]); extern function void m_report_null_objection(uvm_object obj, string description, int count, string action); extern virtual function void raise_objection (uvm_object obj, string description="", int count=1); extern virtual function void drop_objection (uvm_object obj, string description="", int count=1); extern virtual function int get_objection_count( uvm_object obj=null ); extern function void sync(uvm_domain target, uvm_phase phase=null, uvm_phase with_phase=null); extern function void unsync(uvm_domain target, uvm_phase phase=null, uvm_phase with_phase=null); extern task wait_for_state(uvm_phase_state state, uvm_wait_op op=UVM_EQ); extern function void jump(uvm_phase phase); extern function void set_jump_phase(uvm_phase phase) ; extern function void end_prematurely() ; extern static function void jump_all(uvm_phase phase); extern function uvm_phase get_jump_target(); protected uvm_phase_type m_phase_type; protected uvm_phase m_parent; uvm_phase m_imp; local uvm_phase_state m_state; local int m_run_count; local process m_phase_proc; local static int m_default_max_ready_to_end_iters = 20; local int max_ready_to_end_iters = get_default_max_ready_to_end_iterations(); int m_num_procs_not_yet_returned; extern function uvm_phase m_find_predecessor(uvm_phase phase, bit stay_in_scope=1, uvm_phase orig_phase=null); extern function uvm_phase m_find_successor(uvm_phase phase, bit stay_in_scope=1, uvm_phase orig_phase=null); extern function uvm_phase m_find_predecessor_by_name(string name, bit stay_in_scope=1, uvm_phase orig_phase=null); extern function uvm_phase m_find_successor_by_name(string name, bit stay_in_scope=1, uvm_phase orig_phase=null); extern function void m_print_successors(); virtual function void traverse(uvm_component comp, uvm_phase phase, uvm_phase_state state); endfunction virtual function void execute(uvm_component comp, uvm_phase phase); endfunction protected bit m_predecessors[uvm_phase]; protected bit m_successors[uvm_phase]; protected uvm_phase m_end_node; static protected bit m_executing_phases[uvm_phase]; function uvm_phase get_begin_node(); if (m_imp != null) return this; return null; endfunction function uvm_phase get_end_node(); return m_end_node; endfunction local uvm_phase m_sync[$]; local uvm_objection phase_done; local int unsigned m_ready_to_end_count; function int unsigned get_ready_to_end_count(); return m_ready_to_end_count; endfunction extern local function void get_predecessors_for_successors(output bit pred_of_succ[uvm_phase]); extern local task m_wait_for_pred(); local bit m_jump_bkwd; local bit m_jump_fwd; local uvm_phase m_jump_phase; local bit m_premature_end; extern function void clear(uvm_phase_state state = UVM_PHASE_DORMANT); extern function void clear_successors( uvm_phase_state state = UVM_PHASE_DORMANT, uvm_phase end_state=null); local static mailbox #(uvm_phase) m_phase_hopper = new(); extern static task m_run_phases(); extern local task execute_phase(); extern local function void m_terminate_phase(); extern local function void m_print_termination_state(); extern local task wait_for_self_and_siblings_to_drop(); extern function void kill(); extern function void kill_successors(); protected static bit m_phase_trace; local static bit m_use_ovm_run_semantic; function string convert2string(); string s; s = $sformatf("phase: %s parent=%s pred=%s succ=%s",get_name(), (m_parent==null) ? "null" : get_schedule_name(), m_aa2string(m_predecessors), m_aa2string(m_successors)); return s; endfunction local function string m_aa2string(bit aa[uvm_phase]); string s; int i; s = "'{ "; foreach (aa[ph]) begin uvm_phase n = ph; s = {s, (n == null) ? "null" : n.get_name(), (i == aa.num()-1) ? "" : ", "}; i++; end s = {s, " }"}; return s; endfunction function bit is_domain(); return (m_phase_type == UVM_PHASE_DOMAIN); endfunction virtual function void m_get_transitive_children(ref uvm_phase phases[$]); foreach (m_successors[succ]) begin phases.push_back(succ); succ.m_get_transitive_children(phases); end endfunction function uvm_objection get_objection(); uvm_phase imp; uvm_task_phase tp; imp = get_imp(); if ((get_phase_type() != UVM_PHASE_NODE) || (imp == null) || !$cast(tp, imp)) begin return null; end if (phase_done == null) begin phase_done = uvm_objection::type_id::create({get_name(), "_objection"}); end return phase_done; endfunction endclass class uvm_phase_state_change extends uvm_object; typedef uvm_object_registry#(uvm_phase_state_change,"uvm_phase_state_change") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_phase_state_change tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_phase_state_change"; endfunction : type_name virtual function string get_type_name(); return "uvm_phase_state_change"; endfunction : get_type_name uvm_phase m_phase; uvm_phase_state m_prev_state; uvm_phase m_jump_to; function new(string name = "uvm_phase_state_change"); super.new(name); endfunction virtual function uvm_phase_state get_state(); return m_phase.get_state(); endfunction virtual function uvm_phase_state get_prev_state(); return m_prev_state; endfunction function uvm_phase jump_to(); return m_jump_to; endfunction endclass class uvm_phase_cb extends uvm_callback; function new(string name="unnamed-uvm_phase_cb"); super.new(name); endfunction : new virtual function void phase_state_change(uvm_phase phase, uvm_phase_state_change change); endfunction endclass typedef uvm_callbacks#(uvm_phase, uvm_phase_cb) uvm_phase_cb_pool ; typedef class uvm_cmdline_processor; `define UVM_PH_TRACE(ID,MSG,PH,VERB) \ `uvm_info(ID, {$sformatf("Phase '%0s' (id=%0d) ", \ PH.get_full_name(), PH.get_inst_id()),MSG}, VERB) function uvm_phase::new(string name="uvm_phase", uvm_phase_type phase_type=UVM_PHASE_SCHEDULE, uvm_phase parent=null); super.new(name); m_phase_type = phase_type; if ((name == "common") && (phase_type == UVM_PHASE_DOMAIN)) m_state = UVM_PHASE_DORMANT; m_run_count = 0; m_parent = parent; begin uvm_cmdline_processor clp = uvm_cmdline_processor::get_inst(); string val; if (clp.get_arg_value("+UVM_PHASE_TRACE", val)) m_phase_trace = 1; else m_phase_trace = 0; if (clp.get_arg_value("+UVM_USE_OVM_RUN_SEMANTIC", val)) m_use_ovm_run_semantic = 1; else m_use_ovm_run_semantic = 0; end if (parent == null && (phase_type == UVM_PHASE_SCHEDULE || phase_type == UVM_PHASE_DOMAIN )) begin m_end_node = new({name,"_end"}, UVM_PHASE_TERMINAL, this); this.m_successors[m_end_node] = 1; m_end_node.m_predecessors[this] = 1; end endfunction function void uvm_phase::add(uvm_phase phase, uvm_phase with_phase=null, uvm_phase after_phase=null, uvm_phase before_phase=null, uvm_phase start_with_phase=null, uvm_phase end_with_phase=null ); uvm_phase new_node, begin_node, end_node, tmp_node; uvm_phase_state_change state_chg; if (phase == null) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH/NULL")) uvm_report_fatal ("PH/NULL", "add: phase argument is null", UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 754, "", 1); end if (with_phase != null && with_phase.get_phase_type() == UVM_PHASE_IMP) begin string nm = with_phase.get_name(); with_phase = find(with_phase); if (with_phase == null) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BAD_ADD")) uvm_report_fatal ("PH_BAD_ADD", {"cannot find with_phase '",nm,"' within node '",get_name(),"'"}, UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 761, "", 1); end end if (before_phase != null && before_phase.get_phase_type() == UVM_PHASE_IMP) begin string nm = before_phase.get_name(); before_phase = find(before_phase); if (before_phase == null) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BAD_ADD")) uvm_report_fatal ("PH_BAD_ADD", {"cannot find before_phase '",nm,"' within node '",get_name(),"'"}, UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 769, "", 1); end end if (after_phase != null && after_phase.get_phase_type() == UVM_PHASE_IMP) begin string nm = after_phase.get_name(); after_phase = find(after_phase); if (after_phase == null) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BAD_ADD")) uvm_report_fatal ("PH_BAD_ADD", {"cannot find after_phase '",nm,"' within node '",get_name(),"'"}, UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 777, "", 1); end end if (start_with_phase != null && start_with_phase.get_phase_type() == UVM_PHASE_IMP) begin string nm = start_with_phase.get_name(); start_with_phase = find(start_with_phase); if (start_with_phase == null) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BAD_ADD")) uvm_report_fatal ("PH_BAD_ADD", {"cannot find start_with_phase '",nm,"' within node '",get_name(),"'"}, UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 785, "", 1); end end if (end_with_phase != null && end_with_phase.get_phase_type() == UVM_PHASE_IMP) begin string nm = end_with_phase.get_name(); end_with_phase = find(end_with_phase); if (end_with_phase == null) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BAD_ADD")) uvm_report_fatal ("PH_BAD_ADD", {"cannot find end_with_phase '",nm,"' within node '",get_name(),"'"}, UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 793, "", 1); end end if (((with_phase != null) + (after_phase != null) + (start_with_phase != null)) > 1) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BAD_ADD")) uvm_report_fatal ("PH_BAD_ADD", "only one of with_phase/after_phase/start_with_phase may be specified as they all specify predecessor", UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 798, "", 1); end if (((with_phase != null) + (before_phase != null) + (end_with_phase != null)) > 1) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BAD_ADD")) uvm_report_fatal ("PH_BAD_ADD", "only one of with_phase/before_phase/end_with_phase may be specified as they all specify successor", UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 802, "", 1); end if (before_phase == this || after_phase == m_end_node || with_phase == m_end_node || start_with_phase == m_end_node || end_with_phase == m_end_node) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BAD_ADD")) uvm_report_fatal ("PH_BAD_ADD", "cannot add before begin node, after end node, or with end nodes", UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 810, "", 1); end if (before_phase != null && after_phase != null) begin if (!after_phase.is_before(before_phase)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BAD_ADD")) uvm_report_fatal ("PH_BAD_ADD", {"Phase '",before_phase.get_name(), "' is not before phase '",after_phase.get_name(),"'"}, UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 815, "", 1); end end end if (before_phase != null && start_with_phase != null) begin if (!start_with_phase.is_before(before_phase)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BAD_ADD")) uvm_report_fatal ("PH_BAD_ADD", {"Phase '",before_phase.get_name(), "' is not before phase '",start_with_phase.get_name(),"'"}, UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 822, "", 1); end end end if (end_with_phase != null && after_phase != null) begin if (!after_phase.is_before(end_with_phase)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BAD_ADD")) uvm_report_fatal ("PH_BAD_ADD", {"Phase '",end_with_phase.get_name(), "' is not before phase '",after_phase.get_name(),"'"}, UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 829, "", 1); end end end if (phase.get_phase_type() == UVM_PHASE_IMP) begin uvm_task_phase tp; new_node = new(phase.get_name(),UVM_PHASE_NODE,this); new_node.m_imp = phase; begin_node = new_node; end_node = new_node; end else begin begin_node = phase; end_node = phase.m_end_node; phase.m_parent = this; end if (with_phase==null && after_phase==null && before_phase==null && start_with_phase==null && end_with_phase==null) begin before_phase = m_end_node; end if (m_phase_trace) begin uvm_phase_type typ = phase.get_phase_type(); begin if (uvm_report_enabled(UVM_DEBUG,UVM_INFO,"PH/TRC/ADD_PH")) uvm_report_info ("PH/TRC/ADD_PH", {get_name()," (",m_phase_type.name(),") ADD_PHASE: phase=",phase.get_full_name()," (", typ.name(),", inst_id=",$sformatf("%0d",phase.get_inst_id()),")", " with_phase=", (with_phase == null) ? "null" : with_phase.get_name(), " start_with_phase=", (start_with_phase == null) ? "null" : start_with_phase.get_name(), " end_with_phase=", (end_with_phase == null) ? "null" : end_with_phase.get_name(), " after_phase=", (after_phase == null) ? "null" : after_phase.get_name(), " before_phase=", (before_phase == null) ? "null" : before_phase.get_name(), " new_node=", (new_node == null) ? "null" : {new_node.get_name(), " inst_id=", $sformatf("%0d",new_node.get_inst_id())}, " begin_node=", (begin_node == null) ? "null" : begin_node.get_name(), " end_node=", (end_node == null) ? "null" : end_node.get_name()}, UVM_DEBUG, "t/uvm/src/base/uvm_phase.svh", 878, "", 1); end end if (with_phase != null) begin begin_node.m_predecessors = with_phase.m_predecessors; foreach (with_phase.m_predecessors[pred]) pred.m_successors[begin_node] = 1; end_node.m_successors = with_phase.m_successors; foreach (with_phase.m_successors[succ]) succ.m_predecessors[end_node] = 1; end if (start_with_phase != null) begin begin_node.m_predecessors = start_with_phase.m_predecessors; foreach (start_with_phase.m_predecessors[pred]) begin pred.m_successors[begin_node] = 1; end if (before_phase == null && end_with_phase == null) begin end_node.m_successors = m_end_node.m_successors ; foreach (m_end_node.m_successors[succ]) begin succ.m_predecessors[end_node] = 1; end end end if (end_with_phase != null) begin end_node.m_successors = end_with_phase.m_successors; foreach (end_with_phase.m_successors[succ]) begin succ.m_predecessors[end_node] = 1; end if (after_phase == null && start_with_phase == null) begin begin_node.m_predecessors = this.m_predecessors ; foreach (this.m_predecessors[pred]) begin pred.m_successors[begin_node] = 1; end end end if (before_phase != null) begin if (after_phase == null && start_with_phase == null) begin foreach (before_phase.m_predecessors[pred]) begin pred.m_successors.delete(before_phase); pred.m_successors[begin_node] = 1; end begin_node.m_predecessors = before_phase.m_predecessors; before_phase.m_predecessors.delete(); end else if (before_phase.m_predecessors.exists(after_phase)) begin before_phase.m_predecessors.delete(after_phase); end before_phase.m_predecessors[end_node] = 1; end_node.m_successors.delete() ; end_node.m_successors[before_phase] = 1; end if (after_phase != null) begin if (before_phase == null && end_with_phase == null) begin foreach (after_phase.m_successors[succ]) begin succ.m_predecessors.delete(after_phase); succ.m_predecessors[end_node] = 1; end end_node.m_successors = after_phase.m_successors; after_phase.m_successors.delete(); end else if (after_phase.m_successors.exists(before_phase)) begin after_phase.m_successors.delete(before_phase); end after_phase.m_successors[begin_node] = 1; begin_node.m_predecessors.delete(); begin_node.m_predecessors[after_phase] = 1; end if (new_node == null) tmp_node = phase; else tmp_node = new_node; state_chg = uvm_phase_state_change::type_id::create(tmp_node.get_name()); state_chg.m_phase = tmp_node; state_chg.m_jump_to = null; state_chg.m_prev_state = tmp_node.m_state; tmp_node.m_state = UVM_PHASE_DORMANT; begin uvm_callback_iter#(uvm_phase,uvm_phase_cb) iter = new(this); uvm_phase_cb cb = iter.first(); while(cb != null) begin cb.phase_state_change(tmp_node, state_chg); cb = iter.next(); end end endfunction function uvm_phase uvm_phase::get_parent(); return m_parent; endfunction function uvm_phase uvm_phase::get_imp(); return m_imp; endfunction function uvm_phase uvm_phase::get_schedule(bit hier=0); uvm_phase sched; sched = this; if (hier) while (sched.m_parent != null && (sched.m_parent.get_phase_type() == UVM_PHASE_SCHEDULE)) sched = sched.m_parent; if (sched.m_phase_type == UVM_PHASE_SCHEDULE) return sched; if (sched.m_phase_type == UVM_PHASE_NODE) if (m_parent != null && m_parent.m_phase_type != UVM_PHASE_DOMAIN) return m_parent; return null; endfunction function uvm_domain uvm_phase::get_domain(); uvm_phase phase; phase = this; while (phase != null && phase.m_phase_type != UVM_PHASE_DOMAIN) phase = phase.m_parent; if (phase == null) return null; if(!$cast(get_domain,phase)) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH/INTERNAL")) uvm_report_fatal ("PH/INTERNAL", "get_domain: m_phase_type is DOMAIN but $cast to uvm_domain fails", UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 1035, "", 1); end endfunction function string uvm_phase::get_domain_name(); uvm_domain domain; domain = get_domain(); if (domain == null) return "unknown"; return domain.get_name(); endfunction function string uvm_phase::get_schedule_name(bit hier=0); uvm_phase sched; string s; sched = get_schedule(hier); if (sched == null) return ""; s = sched.get_name(); while (sched.m_parent != null && sched.m_parent != sched && (sched.m_parent.get_phase_type() == UVM_PHASE_SCHEDULE)) begin sched = sched.m_parent; s = {sched.get_name(),(s.len()>0?".":""),s}; end return s; endfunction function string uvm_phase::get_full_name(); string dom, sch; if (m_phase_type == UVM_PHASE_IMP) return get_name(); get_full_name = get_domain_name(); sch = get_schedule_name(); if (sch != "") get_full_name = {get_full_name, ".", sch}; if (m_phase_type != UVM_PHASE_DOMAIN && m_phase_type != UVM_PHASE_SCHEDULE) get_full_name = {get_full_name, ".", get_name()}; endfunction function uvm_phase_type uvm_phase::get_phase_type(); return m_phase_type; endfunction function void uvm_phase::set_max_ready_to_end_iterations(int max); max_ready_to_end_iters = max; endfunction function int uvm_phase::get_max_ready_to_end_iterations(); return max_ready_to_end_iters; endfunction function void uvm_phase::set_default_max_ready_to_end_iterations(int max); m_default_max_ready_to_end_iters = max; endfunction function int uvm_phase::get_default_max_ready_to_end_iterations(); return m_default_max_ready_to_end_iters; endfunction function uvm_phase_state uvm_phase::get_state(); return m_state; endfunction function int uvm_phase::get_run_count(); return m_run_count; endfunction function void uvm_phase::m_print_successors(); uvm_phase found; static string spaces = " "; static int level; if (m_phase_type == UVM_PHASE_DOMAIN) level = 0; begin if (uvm_report_enabled(UVM_NONE,UVM_INFO,"UVM/PHASE/SUCC")) uvm_report_info ("UVM/PHASE/SUCC", $sformatf("%s%s (%s) id=%0d",spaces.substr(0,level*2),get_name(), m_phase_type.name(),get_inst_id()), UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 1150, "", 1); end level++; foreach (m_successors[succ]) begin succ.m_print_successors(); end level--; endfunction function uvm_phase uvm_phase::m_find_predecessor(uvm_phase phase, bit stay_in_scope=1, uvm_phase orig_phase=null); uvm_phase found; if (phase == null) begin return null ; end if (phase == m_imp || phase == this) return this; foreach (m_predecessors[pred]) begin uvm_phase orig; orig = (orig_phase==null) ? this : orig_phase; if (!stay_in_scope || (pred.get_schedule() == orig.get_schedule()) || (pred.get_domain() == orig.get_domain())) begin found = pred.m_find_predecessor(phase,stay_in_scope,orig); if (found != null) return found; end end return null; endfunction function uvm_phase uvm_phase::m_find_predecessor_by_name(string name, bit stay_in_scope=1, uvm_phase orig_phase=null); uvm_phase found; if (get_name() == name) return this; foreach (m_predecessors[pred]) begin uvm_phase orig; orig = (orig_phase==null) ? this : orig_phase; if (!stay_in_scope || (pred.get_schedule() == orig.get_schedule()) || (pred.get_domain() == orig.get_domain())) begin found = pred.m_find_predecessor_by_name(name,stay_in_scope,orig); if (found != null) return found; end end return null; endfunction function uvm_phase uvm_phase::m_find_successor(uvm_phase phase, bit stay_in_scope=1, uvm_phase orig_phase=null); uvm_phase found; if (phase == null) begin return null ; end if (phase == m_imp || phase == this) begin return this; end foreach (m_successors[succ]) begin uvm_phase orig; orig = (orig_phase==null) ? this : orig_phase; if (!stay_in_scope || (succ.get_schedule() == orig.get_schedule()) || (succ.get_domain() == orig.get_domain())) begin found = succ.m_find_successor(phase,stay_in_scope,orig); if (found != null) begin return found; end end end return null; endfunction function uvm_phase uvm_phase::m_find_successor_by_name(string name, bit stay_in_scope=1, uvm_phase orig_phase=null); uvm_phase found; if (get_name() == name) return this; foreach (m_successors[succ]) begin uvm_phase orig; orig = (orig_phase==null) ? this : orig_phase; if (!stay_in_scope || (succ.get_schedule() == orig.get_schedule()) || (succ.get_domain() == orig.get_domain())) begin found = succ.m_find_successor_by_name(name,stay_in_scope,orig); if (found != null) return found; end end return null; endfunction function uvm_phase uvm_phase::find(uvm_phase phase, bit stay_in_scope=1); if (phase == m_imp || phase == this) return phase; find = m_find_predecessor(phase,stay_in_scope,this); if (find == null) find = m_find_successor(phase,stay_in_scope,this); endfunction function uvm_phase uvm_phase::find_by_name(string name, bit stay_in_scope=1); if (get_name() == name) return this; find_by_name = m_find_predecessor_by_name(name,stay_in_scope,this); if (find_by_name == null) find_by_name = m_find_successor_by_name(name,stay_in_scope,this); endfunction function bit uvm_phase::is(uvm_phase phase); return (m_imp == phase || this == phase); endfunction function bit uvm_phase::is_before(uvm_phase phase); return (!is(phase) && m_find_successor(phase,0,this) != null); endfunction function bit uvm_phase::is_after(uvm_phase phase); return (!is(phase) && m_find_predecessor(phase,0,this) != null); endfunction task uvm_phase::execute_phase(); uvm_task_phase task_phase; uvm_root top; uvm_phase_state_change state_chg; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); top = cs.get_root(); foreach (m_predecessors[pred]) wait (pred.m_state == UVM_PHASE_DONE); if (m_state == UVM_PHASE_DONE) return; state_chg = uvm_phase_state_change::type_id::create(get_name()); state_chg.m_phase = this; state_chg.m_jump_to = null; state_chg.m_prev_state = m_state; m_state = UVM_PHASE_SYNCING; begin uvm_callback_iter#(uvm_phase,uvm_phase_cb) iter = new(this); uvm_phase_cb cb = iter.first(); while(cb != null) begin cb.phase_state_change(this, state_chg); cb = iter.next(); end end #0; if (m_sync.size()) begin foreach (m_sync[i]) begin wait (m_sync[i].m_state >= UVM_PHASE_SYNCING); end end m_run_count++; if (m_phase_trace) begin begin if (uvm_report_enabled(UVM_LOW,UVM_INFO,"PH/TRC/STRT")) uvm_report_info ("PH/TRC/STRT", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),"Starting phase"}, UVM_LOW, "t/uvm/src/base/uvm_phase.svh", 1366, "", 1); end end if (m_phase_type != UVM_PHASE_NODE) begin state_chg.m_prev_state = m_state; m_state = UVM_PHASE_STARTED; begin uvm_callback_iter#(uvm_phase,uvm_phase_cb) iter = new(this); uvm_phase_cb cb = iter.first(); while(cb != null) begin cb.phase_state_change(this, state_chg); cb = iter.next(); end end #0; state_chg.m_prev_state = m_state; m_state = UVM_PHASE_EXECUTING; begin uvm_callback_iter#(uvm_phase,uvm_phase_cb) iter = new(this); uvm_phase_cb cb = iter.first(); while(cb != null) begin cb.phase_state_change(this, state_chg); cb = iter.next(); end end #0; end else begin state_chg.m_prev_state = m_state; m_state = UVM_PHASE_STARTED; begin uvm_callback_iter#(uvm_phase,uvm_phase_cb) iter = new(this); uvm_phase_cb cb = iter.first(); while(cb != null) begin cb.phase_state_change(this, state_chg); cb = iter.next(); end end m_imp.traverse(top,this,UVM_PHASE_STARTED); m_ready_to_end_count = 0 ; #0; if (!$cast(task_phase,m_imp)) begin state_chg.m_prev_state = m_state; m_state = UVM_PHASE_EXECUTING; begin uvm_callback_iter#(uvm_phase,uvm_phase_cb) iter = new(this); uvm_phase_cb cb = iter.first(); while(cb != null) begin cb.phase_state_change(this, state_chg); cb = iter.next(); end end #0; m_imp.traverse(top,this,UVM_PHASE_EXECUTING); end else begin m_executing_phases[this] = 1; state_chg.m_prev_state = m_state; m_state = UVM_PHASE_EXECUTING; begin uvm_callback_iter#(uvm_phase,uvm_phase_cb) iter = new(this); uvm_phase_cb cb = iter.first(); while(cb != null) begin cb.phase_state_change(this, state_chg); cb = iter.next(); end end fork : master_phase_process begin m_phase_proc = process::self(); task_phase.traverse(top,this,UVM_PHASE_EXECUTING); wait(0); end join_none uvm_wait_for_nba_region(); fork begin fork begin wait (m_premature_end); begin if (uvm_report_enabled(UVM_DEBUG,UVM_INFO,"PH/TRC/EXE/JUMP")) uvm_report_info ("PH/TRC/EXE/JUMP", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),"PHASE EXIT ON JUMP REQUEST"}, UVM_DEBUG, "t/uvm/src/base/uvm_phase.svh", 1446, "", 1); end end begin bit do_ready_to_end ; uvm_objection phase_done; phase_done = get_objection(); if (phase_done.get_objection_total(top) || m_use_ovm_run_semantic && m_imp.get_name() == "run") begin if (!phase_done.m_top_all_dropped) phase_done.wait_for(UVM_ALL_DROPPED, top); begin if (uvm_report_enabled(UVM_DEBUG,UVM_INFO,"PH/TRC/EXE/ALLDROP")) uvm_report_info ("PH/TRC/EXE/ALLDROP", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),"PHASE EXIT ALL_DROPPED"}, UVM_DEBUG, "t/uvm/src/base/uvm_phase.svh", 1459, "", 1); end end else begin if (m_phase_trace) begin if (uvm_report_enabled(UVM_LOW,UVM_INFO,"PH/TRC/SKIP")) uvm_report_info ("PH/TRC/SKIP", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),"No objections raised, skipping phase"}, UVM_LOW, "t/uvm/src/base/uvm_phase.svh", 1462, "", 1); end end wait_for_self_and_siblings_to_drop() ; do_ready_to_end = 1; while (do_ready_to_end) begin uvm_wait_for_nba_region(); begin if (uvm_report_enabled(UVM_DEBUG,UVM_INFO,"PH_READY_TO_END")) uvm_report_info ("PH_READY_TO_END", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),"PHASE READY TO END"}, UVM_DEBUG, "t/uvm/src/base/uvm_phase.svh", 1474, "", 1); end m_ready_to_end_count++; if (m_phase_trace) begin if (uvm_report_enabled(UVM_HIGH,UVM_INFO,"PH_READY_TO_END_CB")) uvm_report_info ("PH_READY_TO_END_CB", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),"CALLING READY_TO_END CB"}, UVM_HIGH, "t/uvm/src/base/uvm_phase.svh", 1477, "", 1); end state_chg.m_prev_state = m_state; m_state = UVM_PHASE_READY_TO_END; begin uvm_callback_iter#(uvm_phase,uvm_phase_cb) iter = new(this); uvm_phase_cb cb = iter.first(); while(cb != null) begin cb.phase_state_change(this, state_chg); cb = iter.next(); end end if (m_imp != null) m_imp.traverse(top,this,UVM_PHASE_READY_TO_END); uvm_wait_for_nba_region(); wait_for_self_and_siblings_to_drop(); do_ready_to_end = (m_state == UVM_PHASE_EXECUTING) && (m_ready_to_end_count < get_max_ready_to_end_iterations()) ; end end begin if (this.get_name() == "run") begin if (top.phase_timeout == 0) wait(top.phase_timeout != 0); if (m_phase_trace) begin if (uvm_report_enabled(UVM_HIGH,UVM_INFO,"PH/TRC/TO_WAIT")) uvm_report_info ("PH/TRC/TO_WAIT", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),$sformatf("STARTING PHASE TIMEOUT WATCHDOG (timeout == %t)", top.phase_timeout)}, UVM_HIGH, "t/uvm/src/base/uvm_phase.svh", 1497, "", 1); end #(top.phase_timeout); if ($time == 9200s) begin if (m_phase_trace) begin if (uvm_report_enabled(UVM_LOW,UVM_INFO,"PH/TRC/TIMEOUT")) uvm_report_info ("PH/TRC/TIMEOUT", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),"PHASE TIMEOUT WATCHDOG EXPIRED"}, UVM_LOW, "t/uvm/src/base/uvm_phase.svh", 1501, "", 1); end foreach (m_executing_phases[p]) begin uvm_objection p_phase_done; p_phase_done = p.get_objection(); if ((p_phase_done != null) && (p_phase_done.get_objection_total() > 0)) begin if (m_phase_trace) begin if (uvm_report_enabled(UVM_LOW,UVM_INFO,"PH/TRC/TIMEOUT/OBJCTN")) uvm_report_info ("PH/TRC/TIMEOUT/OBJCTN", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),$sformatf("Phase '%s' has outstanding objections:\n%s", p.get_full_name(), p_phase_done.convert2string())}, UVM_LOW, "t/uvm/src/base/uvm_phase.svh", 1510, "", 1); end end end begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_TIMEOUT")) uvm_report_fatal ("PH_TIMEOUT", $sformatf("Default timeout of %0t hit, indicating a probable testbench issue", 9200s), UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 1516, "", 1); end end else begin if (m_phase_trace) begin if (uvm_report_enabled(UVM_LOW,UVM_INFO,"PH/TRC/TIMEOUT")) uvm_report_info ("PH/TRC/TIMEOUT", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),"PHASE TIMEOUT WATCHDOG EXPIRED"}, UVM_LOW, "t/uvm/src/base/uvm_phase.svh", 1520, "", 1); end foreach (m_executing_phases[p]) begin uvm_objection p_phase_done; p_phase_done = p.get_objection(); if ((p_phase_done != null) && (p_phase_done.get_objection_total() > 0)) begin if (m_phase_trace) begin if (uvm_report_enabled(UVM_LOW,UVM_INFO,"PH/TRC/TIMEOUT/OBJCTN")) uvm_report_info ("PH/TRC/TIMEOUT/OBJCTN", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),$sformatf("Phase '%s' has outstanding objections:\n%s", p.get_full_name(), p_phase_done.convert2string())}, UVM_LOW, "t/uvm/src/base/uvm_phase.svh", 1529, "", 1); end end end begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_TIMEOUT")) uvm_report_fatal ("PH_TIMEOUT", $sformatf("Explicit timeout of %0t hit, indicating a probable testbench issue", top.phase_timeout), UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 1535, "", 1); end end if (m_phase_trace) begin if (uvm_report_enabled(UVM_DEBUG,UVM_INFO,"PH/TRC/EXE/3")) uvm_report_info ("PH/TRC/EXE/3", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),"PHASE EXIT TIMEOUT"}, UVM_DEBUG, "t/uvm/src/base/uvm_phase.svh", 1538, "", 1); end end else begin wait (0); end end join_any disable fork; end join end end m_executing_phases.delete(this); if (m_phase_type == UVM_PHASE_NODE) begin if(m_premature_end) begin if(m_jump_phase != null) begin state_chg.m_jump_to = m_jump_phase; begin if (uvm_report_enabled(UVM_MEDIUM,UVM_INFO,"PH_JUMP")) uvm_report_info ("PH_JUMP", $sformatf("phase %s (schedule %s, domain %s) is jumping to phase %s", get_name(), get_schedule_name(), get_domain_name(), m_jump_phase.get_name()), UVM_MEDIUM, "t/uvm/src/base/uvm_phase.svh", 1582, "", 1); end end else begin begin if (uvm_report_enabled(UVM_MEDIUM,UVM_INFO,"PH_JUMP")) uvm_report_info ("PH_JUMP", $sformatf("phase %s (schedule %s, domain %s) is ending prematurely", get_name(), get_schedule_name(), get_domain_name()), UVM_MEDIUM, "t/uvm/src/base/uvm_phase.svh", 1588, "", 1); end end #0; if (m_phase_trace) begin if (uvm_report_enabled(UVM_HIGH,UVM_INFO,"PH_END")) uvm_report_info ("PH_END", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),"ENDING PHASE PREMATURELY"}, UVM_HIGH, "t/uvm/src/base/uvm_phase.svh", 1594, "", 1); end end else begin if (task_phase == null) m_wait_for_pred(); end if (m_phase_trace) begin if (uvm_report_enabled(UVM_HIGH,UVM_INFO,"PH_END")) uvm_report_info ("PH_END", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),"ENDING PHASE"}, UVM_HIGH, "t/uvm/src/base/uvm_phase.svh", 1608, "", 1); end state_chg.m_prev_state = m_state; m_state = UVM_PHASE_ENDED; begin uvm_callback_iter#(uvm_phase,uvm_phase_cb) iter = new(this); uvm_phase_cb cb = iter.first(); while(cb != null) begin cb.phase_state_change(this, state_chg); cb = iter.next(); end end if (m_imp != null) m_imp.traverse(top,this,UVM_PHASE_ENDED); #0; state_chg.m_prev_state = m_state; if(m_premature_end) m_state = UVM_PHASE_JUMPING; else m_state = UVM_PHASE_CLEANUP ; begin uvm_callback_iter#(uvm_phase,uvm_phase_cb) iter = new(this); uvm_phase_cb cb = iter.first(); while(cb != null) begin cb.phase_state_change(this, state_chg); cb = iter.next(); end end if (m_phase_proc != null) begin m_phase_proc.kill(); m_phase_proc = null; end #0; begin uvm_objection objection = get_objection(); if (objection != null) objection.clear(); end end m_premature_end = 0 ; if(m_jump_fwd || m_jump_bkwd) begin if(m_jump_fwd) begin clear_successors(UVM_PHASE_DONE,m_jump_phase); end m_jump_phase.clear_successors(); end else begin if (m_phase_trace) begin if (uvm_report_enabled(UVM_LOW,UVM_INFO,"PH/TRC/DONE")) uvm_report_info ("PH/TRC/DONE", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),"Completed phase"}, UVM_LOW, "t/uvm/src/base/uvm_phase.svh", 1650, "", 1); end state_chg.m_prev_state = m_state; m_state = UVM_PHASE_DONE; begin uvm_callback_iter#(uvm_phase,uvm_phase_cb) iter = new(this); uvm_phase_cb cb = iter.first(); while(cb != null) begin cb.phase_state_change(this, state_chg); cb = iter.next(); end end m_phase_proc = null; #0; end #0; begin uvm_objection objection; objection = get_objection(); if (objection != null) objection.clear(); end if(m_jump_fwd || m_jump_bkwd) begin void'(m_phase_hopper.try_put(m_jump_phase)); m_jump_phase = null; m_jump_fwd = 0; m_jump_bkwd = 0; end else if (m_successors.size() == 0) begin top.m_phase_all_done=1; end else begin foreach (m_successors[succ]) begin if(succ.m_state < UVM_PHASE_SCHEDULED) begin state_chg.m_prev_state = succ.m_state; state_chg.m_phase = succ; succ.m_state = UVM_PHASE_SCHEDULED; begin uvm_callback_iter#(uvm_phase,uvm_phase_cb) iter = new(this); uvm_phase_cb cb = iter.first(); while(cb != null) begin cb.phase_state_change(succ, state_chg); cb = iter.next(); end end #0; void'(m_phase_hopper.try_put(succ)); if (m_phase_trace) begin if (uvm_report_enabled(UVM_LOW,UVM_INFO,"PH/TRC/SCHEDULED")) uvm_report_info ("PH/TRC/SCHEDULED", {$sformatf("Phase '%0s' (id=%0d) ", succ.get_full_name(), succ.get_inst_id()),{"Scheduled from phase ",get_full_name()}}, UVM_LOW, "t/uvm/src/base/uvm_phase.svh", 1689, "", 1); end end end end endtask function void uvm_phase::get_adjacent_predecessor_nodes(ref uvm_phase pred[]); bit done; bit predecessors[uvm_phase]; int idx; foreach (m_predecessors[p]) predecessors[p] = 1; do begin done = 1; foreach (predecessors[p]) begin if (p.get_phase_type() != UVM_PHASE_NODE) begin predecessors.delete(p); foreach (p.m_predecessors[next_p]) predecessors[next_p] = 1; done = 0; end end end while (!done); pred = new [predecessors.size()]; foreach (predecessors[p]) begin pred[idx++] = p; end endfunction : get_adjacent_predecessor_nodes function void uvm_phase::get_adjacent_successor_nodes(ref uvm_phase succ[]); bit done; bit successors[uvm_phase]; int idx; foreach (m_successors[s]) successors[s] = 1; do begin done = 1; foreach (successors[s]) begin if (s.get_phase_type() != UVM_PHASE_NODE) begin successors.delete(s); foreach (s.m_successors[next_s]) successors[next_s] = 1; done = 0; end end end while (!done); succ = new [successors.size()]; foreach (successors[s]) begin succ[idx++] = s; end endfunction : get_adjacent_successor_nodes function void uvm_phase::get_predecessors_for_successors(output bit pred_of_succ[uvm_phase]); bit done; uvm_phase successors[]; get_adjacent_successor_nodes(successors); foreach (successors[s]) foreach (successors[s].m_predecessors[pred]) pred_of_succ[pred] = 1; do begin done=1; foreach (pred_of_succ[pred]) begin if (pred.get_phase_type() != UVM_PHASE_NODE) begin pred_of_succ.delete(pred); foreach (pred.m_predecessors[next_pred]) pred_of_succ[next_pred] = 1; done =0; end end end while (!done); pred_of_succ.delete(this); endfunction task uvm_phase::m_wait_for_pred(); bit pred_of_succ[uvm_phase]; get_predecessors_for_successors(pred_of_succ); foreach (pred_of_succ[sibling]) begin if (m_phase_trace) begin string s; s = $sformatf("Waiting for phase '%s' (%0d) to be READY_TO_END. Current state is %s", sibling.get_name(),sibling.get_inst_id(),sibling.m_state.name()); begin if (uvm_report_enabled(UVM_HIGH,UVM_INFO,"PH/TRC/WAIT_PRED_OF_SUCC")) uvm_report_info ("PH/TRC/WAIT_PRED_OF_SUCC", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),s}, UVM_HIGH, "t/uvm/src/base/uvm_phase.svh", 1803, "", 1); end end sibling.wait_for_state(UVM_PHASE_READY_TO_END, UVM_GTE); if (m_phase_trace) begin string s; s = $sformatf("Phase '%s' (%0d) is now READY_TO_END. Releasing phase", sibling.get_name(),sibling.get_inst_id()); begin if (uvm_report_enabled(UVM_HIGH,UVM_INFO,"PH/TRC/WAIT_PRED_OF_SUCC")) uvm_report_info ("PH/TRC/WAIT_PRED_OF_SUCC", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),s}, UVM_HIGH, "t/uvm/src/base/uvm_phase.svh", 1812, "", 1); end end end if (m_phase_trace) begin if (pred_of_succ.num()) begin string s = "( "; foreach (pred_of_succ[pred]) s = {s, pred.get_full_name()," "}; s = {s, ")"}; begin if (uvm_report_enabled(UVM_HIGH,UVM_INFO,"PH/TRC/WAIT_PRED_OF_SUCC")) uvm_report_info ("PH/TRC/WAIT_PRED_OF_SUCC", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),{"*** All pred to succ ",s," in READY_TO_END state, so ending phase ***"}}, UVM_HIGH, "t/uvm/src/base/uvm_phase.svh", 1824, "", 1); end end else begin begin if (uvm_report_enabled(UVM_HIGH,UVM_INFO,"PH/TRC/WAIT_PRED_OF_SUCC")) uvm_report_info ("PH/TRC/WAIT_PRED_OF_SUCC", {$sformatf("Phase '%0s' (id=%0d) ", this.get_full_name(), this.get_inst_id()),"*** No pred to succ other than myself, so ending phase ***"}, UVM_HIGH, "t/uvm/src/base/uvm_phase.svh", 1828, "", 1); end end end #0; endtask function void uvm_phase::m_report_null_objection(uvm_object obj, string description, int count, string action); string m_action; string m_addon; string m_obj_name = (obj == null) ? "uvm_top" : obj.get_full_name(); if ((action == "raise") || (action == "drop")) begin if (count != 1) m_action = $sformatf("%s %0d objections", action, count); else m_action = $sformatf("%s an objection", action); end else if (action == "get_objection_count") begin m_action = "call get_objection_count"; end if (this.get_phase_type() == UVM_PHASE_IMP) begin m_addon = " (This is a UVM_PHASE_IMP, you have to query the schedule to find the UVM_PHASE_NODE)"; end begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/PH/NULL_OBJECTION")) uvm_report_error ("UVM/PH/NULL_OBJECTION", $sformatf("'%s' attempted to %s on '%s', however '%s' is not a task-based phase node! %s", m_obj_name, m_action, get_name(), get_name(), m_addon), UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 1869, "", 1); end endfunction : m_report_null_objection function void uvm_phase::raise_objection (uvm_object obj, string description="", int count=1); uvm_objection phase_done; phase_done = get_objection(); if (phase_done != null) phase_done.raise_objection(obj,description,count); else m_report_null_objection(obj, description, count, "raise"); endfunction function void uvm_phase::drop_objection (uvm_object obj, string description="", int count=1); uvm_objection phase_done; phase_done = get_objection(); if (phase_done != null) phase_done.drop_objection(obj,description,count); else m_report_null_objection(obj, description, count, "drop"); endfunction function int uvm_phase::get_objection_count (uvm_object obj=null); uvm_objection phase_done; phase_done = get_objection(); if (phase_done != null) return phase_done.get_objection_count(obj); else begin m_report_null_objection(obj, "" , 0, "get_objection_count"); return 0; end endfunction : get_objection_count function void uvm_phase::sync(uvm_domain target, uvm_phase phase=null, uvm_phase with_phase=null); if (!this.is_domain()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BADSYNC")) uvm_report_fatal ("PH_BADSYNC", "sync() called from a non-domain phase schedule node", UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 1923, "", 1); end end else if (target == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BADSYNC")) uvm_report_fatal ("PH_BADSYNC", "sync() called with a null target domain", UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 1926, "", 1); end end else if (!target.is_domain()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BADSYNC")) uvm_report_fatal ("PH_BADSYNC", "sync() called with a non-domain phase schedule node as target", UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 1929, "", 1); end end else if (phase == null && with_phase != null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BADSYNC")) uvm_report_fatal ("PH_BADSYNC", "sync() called with null phase and non-null with phase", UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 1932, "", 1); end end else if (phase == null) begin int visited[uvm_phase]; uvm_phase queue[$]; queue.push_back(this); visited[this] = 1; while (queue.size()) begin uvm_phase node; node = queue.pop_front(); if (node.m_imp != null) begin sync(target, node.m_imp); end foreach (node.m_successors[succ]) begin if (!visited.exists(succ)) begin queue.push_back(succ); visited[succ] = 1; end end end end else begin uvm_phase from_node, to_node; int found_to[$], found_from[$]; if(with_phase == null) with_phase = phase; from_node = find(phase); to_node = target.find(with_phase); if(from_node == null || to_node == null) return; found_to = from_node.m_sync.find_index(node) with (node == to_node); found_from = to_node.m_sync.find_index(node) with (node == from_node); if (found_to.size() == 0) from_node.m_sync.push_back(to_node); if (found_from.size() == 0) to_node.m_sync.push_back(from_node); end endfunction function void uvm_phase::unsync(uvm_domain target, uvm_phase phase=null, uvm_phase with_phase=null); if (!this.is_domain()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BADSYNC")) uvm_report_fatal ("PH_BADSYNC", "unsync() called from a non-domain phase schedule node", UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 1977, "", 1); end end else if (target == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BADSYNC")) uvm_report_fatal ("PH_BADSYNC", "unsync() called with a null target domain", UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 1979, "", 1); end end else if (!target.is_domain()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BADSYNC")) uvm_report_fatal ("PH_BADSYNC", "unsync() called with a non-domain phase schedule node as target", UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 1981, "", 1); end end else if (phase == null && with_phase != null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BADSYNC")) uvm_report_fatal ("PH_BADSYNC", "unsync() called with null phase and non-null with phase", UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 1983, "", 1); end end else if (phase == null) begin int visited[uvm_phase]; uvm_phase queue[$]; queue.push_back(this); visited[this] = 1; while (queue.size()) begin uvm_phase node; node = queue.pop_front(); if (node.m_imp != null) unsync(target,node.m_imp); foreach (node.m_successors[succ]) begin if (!visited.exists(succ)) begin queue.push_back(succ); visited[succ] = 1; end end end end else begin uvm_phase from_node, to_node; int found_to[$], found_from[$]; if(with_phase == null) with_phase = phase; from_node = find(phase); to_node = target.find(with_phase); if(from_node == null || to_node == null) return; found_to = from_node.m_sync.find_index(node) with (node == to_node); found_from = to_node.m_sync.find_index(node) with (node == from_node); if (found_to.size()) from_node.m_sync.delete(found_to[0]); if (found_from.size()) to_node.m_sync.delete(found_from[0]); end endfunction task uvm_phase::wait_for_state(uvm_phase_state state, uvm_wait_op op=UVM_EQ); case (op) UVM_EQ: wait((state&m_state) != 0); UVM_NE: wait((state&m_state) == 0); UVM_LT: wait(m_state < state); UVM_LTE: wait(m_state <= state); UVM_GT: wait(m_state > state); UVM_GTE: wait(m_state >= state); endcase endtask function void uvm_phase::set_jump_phase(uvm_phase phase) ; uvm_phase d; if ((m_state < UVM_PHASE_STARTED) || (m_state > UVM_PHASE_ENDED) ) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"JMPPHIDL")) uvm_report_error ("JMPPHIDL", { "Attempting to jump from phase \"", get_name(), "\" which is not currently active (current state is ", m_state.name(), "). The jump will not happen until the phase becomes ", "active."}, UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 2051, "", 1); end end d = m_find_predecessor(phase,0); if (d == null) begin d = m_find_successor(phase,0); if (d == null) begin string msg; $sformat(msg,{"phase %s is neither a predecessor or successor of ", "phase %s or is non-existant, so we cannot jump to it. ", "Phase control flow is now undefined so the simulation ", "must terminate"}, phase.get_name(), get_name()); begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BADJUMP")) uvm_report_fatal ("PH_BADJUMP", msg, UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 2077, "", 1); end end else begin m_jump_fwd = 1; begin if (uvm_report_enabled(UVM_DEBUG,UVM_INFO,"PH_JUMPF")) uvm_report_info ("PH_JUMPF", $sformatf("jumping forward to phase %s", phase.get_name()), UVM_DEBUG, "t/uvm/src/base/uvm_phase.svh", 2082, "", 1); end end end else begin m_jump_bkwd = 1; begin if (uvm_report_enabled(UVM_DEBUG,UVM_INFO,"PH_JUMPB")) uvm_report_info ("PH_JUMPB", $sformatf("jumping backward to phase %s", phase.get_name()), UVM_DEBUG, "t/uvm/src/base/uvm_phase.svh", 2088, "", 1); end end m_jump_phase = d; endfunction function void uvm_phase::end_prematurely() ; m_premature_end = 1 ; endfunction function void uvm_phase::jump(uvm_phase phase); set_jump_phase(phase) ; end_prematurely() ; endfunction function void uvm_phase::jump_all(uvm_phase phase); begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"NOTIMPL")) uvm_report_warning ("NOTIMPL", "uvm_phase::jump_all is not implemented and has been replaced by uvm_domain::jump_all", UVM_NONE, "t/uvm/src/base/uvm_phase.svh", 2120, "", 1); end endfunction function uvm_phase uvm_phase::get_jump_target(); return m_jump_phase; endfunction function void uvm_phase::clear(uvm_phase_state state = UVM_PHASE_DORMANT); uvm_objection phase_done; phase_done = get_objection(); m_state = state; m_phase_proc = null; if (phase_done != null) phase_done.clear(this); endfunction function void uvm_phase::clear_successors(uvm_phase_state state = UVM_PHASE_DORMANT, uvm_phase end_state=null); if(this == end_state) return; clear(state); foreach(m_successors[succ]) begin succ.clear_successors(state, end_state); end endfunction task uvm_phase::wait_for_self_and_siblings_to_drop() ; bit need_to_check_all = 1 ; uvm_root top; uvm_coreservice_t cs; bit siblings[uvm_phase]; cs = uvm_coreservice_t::get(); top = cs.get_root(); get_predecessors_for_successors(siblings); foreach (m_sync[i]) begin siblings[m_sync[i]] = 1; end while (need_to_check_all) begin uvm_objection phase_done; phase_done = get_objection(); need_to_check_all = 0 ; if ((phase_done != null) && (phase_done.get_objection_total(top) != 0)) begin m_state = UVM_PHASE_EXECUTING ; phase_done.wait_for(UVM_ALL_DROPPED, top); need_to_check_all = 1 ; end foreach(siblings[sib]) begin uvm_objection sib_phase_done; sib_phase_done = sib.get_objection(); sib.wait_for_state(UVM_PHASE_EXECUTING, UVM_GTE); if ((sib_phase_done != null) && (sib_phase_done.get_objection_total(top) != 0)) begin m_state = UVM_PHASE_EXECUTING ; sib_phase_done.wait_for(UVM_ALL_DROPPED, top); need_to_check_all = 1 ; end end end endtask function void uvm_phase::kill(); begin if (uvm_report_enabled(UVM_DEBUG,UVM_INFO,"PH_KILL")) uvm_report_info ("PH_KILL", {"killing phase '", get_name(),"'"}, UVM_DEBUG, "t/uvm/src/base/uvm_phase.svh", 2214, "", 1); end if (m_phase_proc != null) begin m_phase_proc.kill(); m_phase_proc = null; end endfunction function void uvm_phase::kill_successors(); foreach (m_successors[succ]) succ.kill_successors(); kill(); endfunction task uvm_phase::m_run_phases(); uvm_root top; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); top = cs.get_root(); begin uvm_phase ph = uvm_domain::get_common_domain(); void'(m_phase_hopper.try_put(ph)); end m_uvm_core_state=UVM_CORE_RUNNING; forever begin uvm_phase phase; m_phase_hopper.get(phase); fork begin phase.execute_phase(); end join_none #0; end endtask function void uvm_phase::m_terminate_phase(); uvm_objection phase_done; phase_done = get_objection(); if (phase_done != null) phase_done.clear(this); endfunction function void uvm_phase::m_print_termination_state(); uvm_root top; uvm_coreservice_t cs; uvm_objection phase_done; phase_done = get_objection(); cs = uvm_coreservice_t::get(); top = cs.get_root(); if (phase_done != null) begin begin if (uvm_report_enabled(UVM_DEBUG,UVM_INFO,"PH_TERMSTATE")) uvm_report_info ("PH_TERMSTATE", $sformatf("phase %s outstanding objections = %0d", get_name(), phase_done.get_objection_total(top)), UVM_DEBUG, "t/uvm/src/base/uvm_phase.svh", 2293, "", 1); end end else begin begin if (uvm_report_enabled(UVM_DEBUG,UVM_INFO,"PH_TERMSTATE")) uvm_report_info ("PH_TERMSTATE", $sformatf("phase %s has no outstanding objections", get_name()), UVM_DEBUG, "t/uvm/src/base/uvm_phase.svh", 2299, "", 1); end end endfunction typedef class uvm_build_phase; typedef class uvm_connect_phase; typedef class uvm_end_of_elaboration_phase; typedef class uvm_start_of_simulation_phase; typedef class uvm_run_phase; typedef class uvm_extract_phase; typedef class uvm_check_phase; typedef class uvm_report_phase; typedef class uvm_final_phase; typedef class uvm_pre_reset_phase; typedef class uvm_reset_phase; typedef class uvm_post_reset_phase; typedef class uvm_pre_configure_phase; typedef class uvm_configure_phase; typedef class uvm_post_configure_phase; typedef class uvm_pre_main_phase; typedef class uvm_main_phase; typedef class uvm_post_main_phase; typedef class uvm_pre_shutdown_phase; typedef class uvm_shutdown_phase; typedef class uvm_post_shutdown_phase; uvm_phase build_ph; uvm_phase connect_ph; uvm_phase end_of_elaboration_ph; uvm_phase start_of_simulation_ph; uvm_phase run_ph; uvm_phase extract_ph; uvm_phase check_ph; uvm_phase report_ph; class uvm_domain extends uvm_phase; static local uvm_domain m_uvm_domain; static local uvm_domain m_domains[string]; static local uvm_phase m_uvm_schedule; static function void get_domains(output uvm_domain domains[string]); domains = m_domains; endfunction static function uvm_phase get_uvm_schedule(); void'(get_uvm_domain()); return m_uvm_schedule; endfunction static function uvm_domain get_common_domain(); uvm_domain domain; if(m_domains.exists("common")) domain = m_domains["common"]; if (domain != null) return domain; domain = new("common"); domain.add(uvm_build_phase::get()); domain.add(uvm_connect_phase::get()); domain.add(uvm_end_of_elaboration_phase::get()); domain.add(uvm_start_of_simulation_phase::get()); domain.add(uvm_run_phase::get()); domain.add(uvm_extract_phase::get()); domain.add(uvm_check_phase::get()); domain.add(uvm_report_phase::get()); domain.add(uvm_final_phase::get()); build_ph = domain.find(uvm_build_phase::get()); connect_ph = domain.find(uvm_connect_phase::get()); end_of_elaboration_ph = domain.find(uvm_end_of_elaboration_phase::get()); start_of_simulation_ph = domain.find(uvm_start_of_simulation_phase::get()); run_ph = domain.find(uvm_run_phase::get()); extract_ph = domain.find(uvm_extract_phase::get()); check_ph = domain.find(uvm_check_phase::get()); report_ph = domain.find(uvm_report_phase::get()); domain = get_uvm_domain(); m_domains["common"].add(domain, .with_phase(m_domains["common"].find(uvm_run_phase::get()))); return m_domains["common"]; endfunction static function void add_uvm_phases(uvm_phase schedule); schedule.add(uvm_pre_reset_phase::get()); schedule.add(uvm_reset_phase::get()); schedule.add(uvm_post_reset_phase::get()); schedule.add(uvm_pre_configure_phase::get()); schedule.add(uvm_configure_phase::get()); schedule.add(uvm_post_configure_phase::get()); schedule.add(uvm_pre_main_phase::get()); schedule.add(uvm_main_phase::get()); schedule.add(uvm_post_main_phase::get()); schedule.add(uvm_pre_shutdown_phase::get()); schedule.add(uvm_shutdown_phase::get()); schedule.add(uvm_post_shutdown_phase::get()); endfunction static function uvm_domain get_uvm_domain(); if (m_uvm_domain == null) begin m_uvm_domain = new("uvm"); m_uvm_schedule = new("uvm_sched", UVM_PHASE_SCHEDULE); add_uvm_phases(m_uvm_schedule); m_uvm_domain.add(m_uvm_schedule); end return m_uvm_domain; endfunction function new(string name); super.new(name,UVM_PHASE_DOMAIN); if (m_domains.exists(name)) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UNIQDOMNAM")) uvm_report_error ("UNIQDOMNAM", $sformatf("Domain created with non-unique name '%s'", name), UVM_NONE, "t/uvm/src/base/uvm_domain.svh", 183, "", 1); end m_domains[name] = this; endfunction function void jump(uvm_phase phase); uvm_phase phases[$]; m_get_transitive_children(phases); phases = phases.find(item) with (item.get_state() inside {[UVM_PHASE_STARTED:UVM_PHASE_CLEANUP]}); foreach(phases[idx]) if(phases[idx].is_before(phase) || phases[idx].is_after(phase)) phases[idx].jump(phase); endfunction static function void jump_all(uvm_phase phase); uvm_domain domains[string]; uvm_domain::get_domains(domains); foreach(domains[idx]) domains[idx].jump(phase); endfunction endclass virtual class uvm_bottomup_phase extends uvm_phase; function new(string name); super.new(name,UVM_PHASE_IMP); endfunction virtual function void traverse(uvm_component comp, uvm_phase phase, uvm_phase_state state); string name; uvm_domain phase_domain =phase.get_domain(); uvm_domain comp_domain = comp.get_domain(); if (comp.get_first_child(name)) do traverse(comp.get_child(name), phase, state); while(comp.get_next_child(name)); if (m_phase_trace) begin if (uvm_report_enabled(UVM_DEBUG,UVM_INFO,"PH_TRACE")) uvm_report_info ("PH_TRACE", $sformatf("bottomup-phase phase=%s state=%s comp=%s comp.domain=%s phase.domain=%s", phase.get_name(), state.name(), comp.get_full_name(),comp_domain.get_name(),phase_domain.get_name()), UVM_DEBUG, "t/uvm/src/base/uvm_bottomup_phase.svh", 64, "", 1); end if (phase_domain == uvm_domain::get_common_domain() || phase_domain == comp_domain) begin case (state) UVM_PHASE_STARTED: begin comp.m_current_phase = phase; comp.m_apply_verbosity_settings(phase); comp.phase_started(phase); end UVM_PHASE_EXECUTING: begin uvm_phase ph = this; if (comp.m_phase_imps.exists(this)) ph = comp.m_phase_imps[this]; ph.execute(comp, phase); end UVM_PHASE_READY_TO_END: begin comp.phase_ready_to_end(phase); end UVM_PHASE_ENDED: begin comp.phase_ended(phase); comp.m_current_phase = null; end default: begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BADEXEC")) uvm_report_fatal ("PH_BADEXEC", "bottomup phase traverse internal error", UVM_NONE, "t/uvm/src/base/uvm_bottomup_phase.svh", 88, "", 1); end endcase end endfunction virtual function void execute(uvm_component comp, uvm_phase phase); process proc = process::self(); proc.srandom(uvm_create_random_seed(phase.get_type_name(), comp.get_full_name())); comp.m_current_phase = phase; exec_func(comp,phase); endfunction endclass virtual class uvm_topdown_phase extends uvm_phase; function new(string name); super.new(name,UVM_PHASE_IMP); endfunction virtual function void traverse(uvm_component comp, uvm_phase phase, uvm_phase_state state); string name; uvm_domain phase_domain = phase.get_domain(); uvm_domain comp_domain = comp.get_domain(); if (m_phase_trace) begin if (uvm_report_enabled(UVM_DEBUG,UVM_INFO,"PH_TRACE")) uvm_report_info ("PH_TRACE", $sformatf("topdown-phase phase=%s state=%s comp=%s comp.domain=%s phase.domain=%s", phase.get_name(), state.name(), comp.get_full_name(),comp_domain.get_name(),phase_domain.get_name()), UVM_DEBUG, "t/uvm/src/base/uvm_topdown_phase.svh", 59, "", 1); end if (phase_domain == uvm_domain::get_common_domain() || phase_domain == comp_domain) begin case (state) UVM_PHASE_STARTED: begin comp.m_current_phase = phase; comp.m_apply_verbosity_settings(phase); comp.phase_started(phase); end UVM_PHASE_EXECUTING: begin if (!(phase.get_name() == "build" && comp.m_build_done)) begin uvm_phase ph = this; comp.m_phasing_active++; if (comp.m_phase_imps.exists(this)) ph = comp.m_phase_imps[this]; ph.execute(comp, phase); comp.m_phasing_active--; end end UVM_PHASE_READY_TO_END: begin comp.phase_ready_to_end(phase); end UVM_PHASE_ENDED: begin comp.phase_ended(phase); comp.m_current_phase = null; end default: begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BADEXEC")) uvm_report_fatal ("PH_BADEXEC", "topdown phase traverse internal error", UVM_NONE, "t/uvm/src/base/uvm_topdown_phase.svh", 87, "", 1); end endcase end if(comp.get_first_child(name)) do traverse(comp.get_child(name), phase, state); while(comp.get_next_child(name)); endfunction virtual function void execute(uvm_component comp, uvm_phase phase); process proc = process::self(); proc.srandom(uvm_create_random_seed(phase.get_type_name(), comp.get_full_name())); comp.m_current_phase = phase; exec_func(comp,phase); endfunction endclass virtual class uvm_task_phase extends uvm_phase; function new(string name); super.new(name,UVM_PHASE_IMP); endfunction virtual function void traverse(uvm_component comp, uvm_phase phase, uvm_phase_state state); phase.m_num_procs_not_yet_returned = 0; m_traverse(comp, phase, state); endfunction function void m_traverse(uvm_component comp, uvm_phase phase, uvm_phase_state state); string name; uvm_domain phase_domain =phase.get_domain(); uvm_domain comp_domain = comp.get_domain(); uvm_sequencer_base seqr; if (comp.get_first_child(name)) do m_traverse(comp.get_child(name), phase, state); while(comp.get_next_child(name)); if (m_phase_trace) begin if (uvm_report_enabled(UVM_DEBUG,UVM_INFO,"PH_TRACE")) uvm_report_info ("PH_TRACE", $sformatf("topdown-phase phase=%s state=%s comp=%s comp.domain=%s phase.domain=%s", phase.get_name(), state.name(), comp.get_full_name(),comp_domain.get_name(),phase_domain.get_name()), UVM_DEBUG, "t/uvm/src/base/uvm_task_phase.svh", 94, "", 1); end if (phase_domain == uvm_domain::get_common_domain() || phase_domain == comp_domain) begin case (state) UVM_PHASE_STARTED: begin comp.m_current_phase = phase; comp.m_apply_verbosity_settings(phase); comp.phase_started(phase); if ($cast(seqr, comp)) seqr.start_phase_sequence(phase); end UVM_PHASE_EXECUTING: begin uvm_phase ph = this; if (comp.m_phase_imps.exists(this)) ph = comp.m_phase_imps[this]; ph.execute(comp, phase); end UVM_PHASE_READY_TO_END: begin comp.phase_ready_to_end(phase); end UVM_PHASE_ENDED: begin if ($cast(seqr, comp)) seqr.stop_phase_sequence(phase); comp.phase_ended(phase); comp.m_current_phase = null; end default: begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PH_BADEXEC")) uvm_report_fatal ("PH_BADEXEC", "task phase traverse internal error", UVM_NONE, "t/uvm/src/base/uvm_task_phase.svh", 122, "", 1); end endcase end endfunction virtual function void execute(uvm_component comp, uvm_phase phase); fork begin process proc; proc = process::self(); proc.srandom(uvm_create_random_seed(phase.get_type_name(), comp.get_full_name())); phase.m_num_procs_not_yet_returned++; exec_task(comp,phase); phase.m_num_procs_not_yet_returned--; end join_none endfunction endclass class uvm_build_phase extends uvm_topdown_phase; virtual function void exec_func(uvm_component comp, uvm_phase phase); comp.build_phase(phase); endfunction local static uvm_build_phase m_inst; static function string type_name(); return "uvm_build_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_build_phase"; endfunction : get_type_name static function uvm_build_phase get(); if(m_inst == null) m_inst = new(); return m_inst; endfunction protected function new(string name="build"); super.new(name); endfunction endclass class uvm_connect_phase extends uvm_bottomup_phase; virtual function void exec_func(uvm_component comp, uvm_phase phase); comp.connect_phase(phase); endfunction local static uvm_connect_phase m_inst; static function string type_name(); return "uvm_connect_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_connect_phase"; endfunction : get_type_name static function uvm_connect_phase get(); if(m_inst == null) m_inst = new(); return m_inst; endfunction protected function new(string name="connect"); super.new(name); endfunction endclass class uvm_end_of_elaboration_phase extends uvm_bottomup_phase; virtual function void exec_func(uvm_component comp, uvm_phase phase); comp.end_of_elaboration_phase(phase); endfunction local static uvm_end_of_elaboration_phase m_inst; static function string type_name(); return "uvm_end_of_elaboration_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_end_of_elaboration_phase"; endfunction : get_type_name static function uvm_end_of_elaboration_phase get(); if(m_inst == null) begin m_inst = new(); end return m_inst; endfunction protected function new(string name="end_of_elaboration"); super.new(name); endfunction endclass class uvm_start_of_simulation_phase extends uvm_bottomup_phase; virtual function void exec_func(uvm_component comp, uvm_phase phase); comp.start_of_simulation_phase(phase); endfunction local static uvm_start_of_simulation_phase m_inst; static function string type_name(); return "uvm_start_of_simulation_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_start_of_simulation_phase"; endfunction : get_type_name static function uvm_start_of_simulation_phase get(); if(m_inst == null) m_inst = new(); return m_inst; endfunction protected function new(string name="start_of_simulation"); super.new(name); endfunction endclass class uvm_run_phase extends uvm_task_phase; virtual task exec_task(uvm_component comp, uvm_phase phase); comp.run_phase(phase); endtask local static uvm_run_phase m_inst; static function string type_name(); return "uvm_run_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_run_phase"; endfunction : get_type_name static function uvm_run_phase get(); if(m_inst == null) m_inst = new; return m_inst; endfunction protected function new(string name="run"); super.new(name); endfunction endclass class uvm_extract_phase extends uvm_bottomup_phase; virtual function void exec_func(uvm_component comp, uvm_phase phase); comp.extract_phase(phase); endfunction local static uvm_extract_phase m_inst; static function string type_name(); return "uvm_extract_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_extract_phase"; endfunction : get_type_name static function uvm_extract_phase get(); if(m_inst == null) m_inst = new(); return m_inst; endfunction protected function new(string name="extract"); super.new(name); endfunction endclass class uvm_check_phase extends uvm_bottomup_phase; virtual function void exec_func(uvm_component comp, uvm_phase phase); comp.check_phase(phase); endfunction local static uvm_check_phase m_inst; static function string type_name(); return "uvm_check_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_check_phase"; endfunction : get_type_name static function uvm_check_phase get(); if(m_inst == null) m_inst = new(); return m_inst; endfunction protected function new(string name="check"); super.new(name); endfunction endclass class uvm_report_phase extends uvm_bottomup_phase; virtual function void exec_func(uvm_component comp, uvm_phase phase); comp.report_phase(phase); endfunction local static uvm_report_phase m_inst; static function string type_name(); return "uvm_report_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_report_phase"; endfunction : get_type_name static function uvm_report_phase get(); if(m_inst == null) m_inst = new(); return m_inst; endfunction protected function new(string name="report"); super.new(name); endfunction endclass class uvm_final_phase extends uvm_topdown_phase; virtual function void exec_func(uvm_component comp, uvm_phase phase); comp.final_phase(phase); endfunction local static uvm_final_phase m_inst; static function string type_name(); return "uvm_final_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_final_phase"; endfunction : get_type_name static function uvm_final_phase get(); if(m_inst == null) m_inst = new(); return m_inst; endfunction protected function new(string name="final"); super.new(name); endfunction endclass class uvm_pre_reset_phase extends uvm_task_phase; virtual task exec_task(uvm_component comp, uvm_phase phase); comp.pre_reset_phase(phase); endtask local static uvm_pre_reset_phase m_inst; static function string type_name(); return "uvm_pre_reset_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_pre_reset_phase"; endfunction : get_type_name static function uvm_pre_reset_phase get(); if(m_inst == null) m_inst = new; return m_inst; endfunction protected function new(string name="pre_reset"); super.new(name); endfunction endclass class uvm_reset_phase extends uvm_task_phase; virtual task exec_task(uvm_component comp, uvm_phase phase); comp.reset_phase(phase); endtask local static uvm_reset_phase m_inst; static function string type_name(); return "uvm_reset_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_reset_phase"; endfunction : get_type_name static function uvm_reset_phase get(); if(m_inst == null) m_inst = new; return m_inst; endfunction protected function new(string name="reset"); super.new(name); endfunction endclass class uvm_post_reset_phase extends uvm_task_phase; virtual task exec_task(uvm_component comp, uvm_phase phase); comp.post_reset_phase(phase); endtask local static uvm_post_reset_phase m_inst; static function string type_name(); return "uvm_post_reset_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_post_reset_phase"; endfunction : get_type_name static function uvm_post_reset_phase get(); if(m_inst == null) m_inst = new; return m_inst; endfunction protected function new(string name="post_reset"); super.new(name); endfunction endclass class uvm_pre_configure_phase extends uvm_task_phase; virtual task exec_task(uvm_component comp, uvm_phase phase); comp.pre_configure_phase(phase); endtask local static uvm_pre_configure_phase m_inst; static function string type_name(); return "uvm_pre_configure_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_pre_configure_phase"; endfunction : get_type_name static function uvm_pre_configure_phase get(); if(m_inst == null) m_inst = new; return m_inst; endfunction protected function new(string name="pre_configure"); super.new(name); endfunction endclass class uvm_configure_phase extends uvm_task_phase; virtual task exec_task(uvm_component comp, uvm_phase phase); comp.configure_phase(phase); endtask local static uvm_configure_phase m_inst; static function string type_name(); return "uvm_configure_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_configure_phase"; endfunction : get_type_name static function uvm_configure_phase get(); if(m_inst == null) m_inst = new; return m_inst; endfunction protected function new(string name="configure"); super.new(name); endfunction endclass class uvm_post_configure_phase extends uvm_task_phase; virtual task exec_task(uvm_component comp, uvm_phase phase); comp.post_configure_phase(phase); endtask local static uvm_post_configure_phase m_inst; static function string type_name(); return "uvm_post_configure_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_post_configure_phase"; endfunction : get_type_name static function uvm_post_configure_phase get(); if(m_inst == null) m_inst = new; return m_inst; endfunction protected function new(string name="post_configure"); super.new(name); endfunction endclass class uvm_pre_main_phase extends uvm_task_phase; virtual task exec_task(uvm_component comp, uvm_phase phase); comp.pre_main_phase(phase); endtask local static uvm_pre_main_phase m_inst; static function string type_name(); return "uvm_pre_main_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_pre_main_phase"; endfunction : get_type_name static function uvm_pre_main_phase get(); if(m_inst == null) m_inst = new; return m_inst; endfunction protected function new(string name="pre_main"); super.new(name); endfunction endclass class uvm_main_phase extends uvm_task_phase; virtual task exec_task(uvm_component comp, uvm_phase phase); comp.main_phase(phase); endtask local static uvm_main_phase m_inst; static function string type_name(); return "uvm_main_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_main_phase"; endfunction : get_type_name static function uvm_main_phase get(); if(m_inst == null) m_inst = new; return m_inst; endfunction protected function new(string name="main"); super.new(name); endfunction endclass class uvm_post_main_phase extends uvm_task_phase; virtual task exec_task(uvm_component comp, uvm_phase phase); comp.post_main_phase(phase); endtask local static uvm_post_main_phase m_inst; static function string type_name(); return "uvm_post_main_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_post_main_phase"; endfunction : get_type_name static function uvm_post_main_phase get(); if(m_inst == null) m_inst = new; return m_inst; endfunction protected function new(string name="post_main"); super.new(name); endfunction endclass class uvm_pre_shutdown_phase extends uvm_task_phase; virtual task exec_task(uvm_component comp, uvm_phase phase); comp.pre_shutdown_phase(phase); endtask local static uvm_pre_shutdown_phase m_inst; static function string type_name(); return "uvm_pre_shutdown_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_pre_shutdown_phase"; endfunction : get_type_name static function uvm_pre_shutdown_phase get(); if(m_inst == null) m_inst = new; return m_inst; endfunction protected function new(string name="pre_shutdown"); super.new(name); endfunction endclass class uvm_shutdown_phase extends uvm_task_phase; virtual task exec_task(uvm_component comp, uvm_phase phase); comp.shutdown_phase(phase); endtask local static uvm_shutdown_phase m_inst; static function string type_name(); return "uvm_shutdown_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_shutdown_phase"; endfunction : get_type_name static function uvm_shutdown_phase get(); if(m_inst == null) m_inst = new; return m_inst; endfunction protected function new(string name="shutdown"); super.new(name); endfunction endclass class uvm_post_shutdown_phase extends uvm_task_phase; virtual task exec_task(uvm_component comp, uvm_phase phase); comp.post_shutdown_phase(phase); endtask local static uvm_post_shutdown_phase m_inst; static function string type_name(); return "uvm_post_shutdown_phase"; endfunction : type_name virtual function string get_type_name(); return "uvm_post_shutdown_phase"; endfunction : get_type_name static function uvm_post_shutdown_phase get(); if(m_inst == null) m_inst = new; return m_inst; endfunction protected function new(string name="post_shutdown"); super.new(name); endfunction endclass virtual class uvm_run_test_callback extends uvm_callback; extern function new( string name="uvm_run_test_callback"); virtual function void pre_run_test(); endfunction virtual function void post_run_test(); endfunction virtual function void pre_abort(); endfunction extern static function bit add( uvm_run_test_callback cb ); extern static function bit delete( uvm_run_test_callback cb ); extern static function void m_do_pre_run_test(); extern static function void m_do_post_run_test(); extern static function void m_do_pre_abort(); local static uvm_run_test_callback m_registered_cbs[$]; endclass : uvm_run_test_callback function uvm_run_test_callback::new( string name="uvm_run_test_callback"); super.new( name ); endfunction function bit uvm_run_test_callback::add( uvm_run_test_callback cb ); bit found; int unsigned i; if ( cb == null ) begin return 0; end found = 0; i = 0; while ( ! found && ( i < m_registered_cbs.size() ) ) begin if ( m_registered_cbs[ i ] == cb ) begin found = 1; end ++i; end if ( ! found ) begin m_registered_cbs.push_back( cb ); end return ! found; endfunction function bit uvm_run_test_callback::delete( uvm_run_test_callback cb ); int cb_idxs[$]; if ( cb == null ) begin return 0; end cb_idxs = m_registered_cbs.find_index( item ) with ( item == cb ); foreach ( cb_idxs[ i ] ) begin m_registered_cbs.delete( i ); end return ( cb_idxs.size() > 0 ); endfunction function void uvm_run_test_callback::m_do_pre_run_test(); foreach ( m_registered_cbs[ i ] ) begin m_registered_cbs[ i ].pre_run_test(); end endfunction function void uvm_run_test_callback::m_do_post_run_test(); foreach ( m_registered_cbs[ i ] ) begin m_registered_cbs[ i ].post_run_test(); end endfunction function void uvm_run_test_callback::m_do_pre_abort(); foreach ( m_registered_cbs[ i ] ) begin m_registered_cbs[ i ].pre_abort(); end endfunction typedef class uvm_objection; typedef class uvm_sequence_base; typedef class uvm_sequence_item; virtual class uvm_component extends uvm_report_object; extern function new (string name, uvm_component parent); extern virtual function uvm_component get_parent (); extern virtual function string get_full_name (); extern function void get_children(ref uvm_component children[$]); extern function uvm_component get_child (string name); extern function int get_next_child (ref string name); extern function int get_first_child (ref string name); extern function int get_num_children (); extern function int has_child (string name); extern virtual function void set_name (string name); extern function uvm_component lookup (string name); extern function int unsigned get_depth(); extern virtual function void build_phase(uvm_phase phase); extern virtual function void connect_phase(uvm_phase phase); extern virtual function void end_of_elaboration_phase(uvm_phase phase); extern virtual function void start_of_simulation_phase(uvm_phase phase); extern virtual task run_phase(uvm_phase phase); extern virtual task pre_reset_phase(uvm_phase phase); extern virtual task reset_phase(uvm_phase phase); extern virtual task post_reset_phase(uvm_phase phase); extern virtual task pre_configure_phase(uvm_phase phase); extern virtual task configure_phase(uvm_phase phase); extern virtual task post_configure_phase(uvm_phase phase); extern virtual task pre_main_phase(uvm_phase phase); extern virtual task main_phase(uvm_phase phase); extern virtual task post_main_phase(uvm_phase phase); extern virtual task pre_shutdown_phase(uvm_phase phase); extern virtual task shutdown_phase(uvm_phase phase); extern virtual task post_shutdown_phase(uvm_phase phase); extern virtual function void extract_phase(uvm_phase phase); extern virtual function void check_phase(uvm_phase phase); extern virtual function void report_phase(uvm_phase phase); extern virtual function void final_phase(uvm_phase phase); extern virtual function void phase_started (uvm_phase phase); extern virtual function void phase_ready_to_end (uvm_phase phase); extern virtual function void phase_ended (uvm_phase phase); extern function void set_domain(uvm_domain domain, int hier=1); extern function uvm_domain get_domain(); extern virtual protected function void define_domain(uvm_domain domain); extern virtual task suspend (); extern virtual task resume (); extern virtual function void resolve_bindings (); extern function string massage_scope(string scope); extern virtual function void apply_config_settings (bit verbose = 0); extern virtual function bit use_automatic_config(); extern function void print_config(bit recurse = 0, bit audit = 0); extern function void print_config_with_audit(bit recurse = 0); static bit print_config_matches; virtual function void raised (uvm_objection objection, uvm_object source_obj, string description, int count); endfunction virtual function void dropped (uvm_objection objection, uvm_object source_obj, string description, int count); endfunction virtual task all_dropped (uvm_objection objection, uvm_object source_obj, string description, int count); endtask extern function uvm_component create_component (string requested_type_name, string name); extern function uvm_object create_object (string requested_type_name, string name=""); extern static function void set_type_override_by_type (uvm_object_wrapper original_type, uvm_object_wrapper override_type, bit replace=1); extern function void set_inst_override_by_type(string relative_inst_path, uvm_object_wrapper original_type, uvm_object_wrapper override_type); extern static function void set_type_override(string original_type_name, string override_type_name, bit replace=1); extern function void set_inst_override(string relative_inst_path, string original_type_name, string override_type_name); extern function void print_override_info(string requested_type_name, string name=""); extern function void set_report_id_verbosity_hier (string id, int verbosity); extern function void set_report_severity_id_verbosity_hier(uvm_severity severity, string id, int verbosity); extern function void set_report_severity_action_hier (uvm_severity severity, uvm_action action); extern function void set_report_id_action_hier (string id, uvm_action action); extern function void set_report_severity_id_action_hier(uvm_severity severity, string id, uvm_action action); extern function void set_report_default_file_hier (UVM_FILE file); extern function void set_report_severity_file_hier (uvm_severity severity, UVM_FILE file); extern function void set_report_id_file_hier (string id, UVM_FILE file); extern function void set_report_severity_id_file_hier(uvm_severity severity, string id, UVM_FILE file); extern function void set_report_verbosity_level_hier (int verbosity); virtual function void pre_abort; endfunction extern function void accept_tr (uvm_transaction tr, time accept_time = 0); extern virtual protected function void do_accept_tr (uvm_transaction tr); extern function int begin_tr (uvm_transaction tr, string stream_name="main", string label="", string desc="", time begin_time=0, int parent_handle=0); extern virtual protected function void do_begin_tr (uvm_transaction tr, string stream_name, int tr_handle); extern function void end_tr (uvm_transaction tr, time end_time=0, bit free_handle=1); extern virtual protected function void do_end_tr (uvm_transaction tr, int tr_handle); extern function int record_error_tr (string stream_name="main", uvm_object info=null, string label="error_tr", string desc="", time error_time=0, bit keep_active=0); extern function int record_event_tr (string stream_name="main", uvm_object info=null, string label="event_tr", string desc="", time event_time=0, bit keep_active=0); extern virtual function uvm_tr_stream get_tr_stream(string name, string stream_type_name=""); extern virtual function void free_tr_stream(uvm_tr_stream stream); bit print_enabled = 1; uvm_tr_database tr_database; extern virtual function uvm_tr_database get_tr_database(); extern virtual function void set_tr_database(uvm_tr_database db); protected uvm_domain m_domain; uvm_phase m_phase_imps[uvm_phase]; uvm_phase m_current_phase; protected process m_phase_process; bit m_build_done; int m_phasing_active; extern function void set_local(uvm_resource_base rsrc) ; uvm_component m_parent; protected uvm_component m_children[string]; protected uvm_component m_children_by_handle[uvm_component]; extern protected virtual function bit m_add_child(uvm_component child); extern local virtual function void m_set_full_name(); extern function void do_resolve_bindings(); extern function void do_flush(); extern virtual function void flush (); extern local function void m_extract_name(string name , output string leaf , output string remainder ); extern virtual function uvm_object create (string name=""); extern virtual function uvm_object clone (); local uvm_tr_stream m_streams[string][string]; local uvm_recorder m_tr_h[uvm_transaction]; extern protected function int m_begin_tr (uvm_transaction tr, int parent_handle=0, string stream_name="main", string label="", string desc="", time begin_time=0); string m_name; typedef uvm_abstract_component_registry#(uvm_component, "uvm_component") type_id; static function string type_name(); return "uvm_component"; endfunction : type_name virtual function string get_type_name(); return "uvm_component"; endfunction : get_type_name protected uvm_event_pool event_pool; int unsigned recording_detail = UVM_NONE; extern function void do_print(uvm_printer printer); extern function void m_set_cl_msg_args; extern function void m_set_cl_verb; extern function void m_set_cl_action; extern function void m_set_cl_sev; extern function void m_apply_verbosity_settings(uvm_phase phase); typedef struct { string comp; string phase; time offset; uvm_verbosity verbosity; string id; } m_verbosity_setting; m_verbosity_setting m_verbosity_settings[$]; static m_verbosity_setting m_time_settings[$]; extern function void m_do_pre_abort; uvm_resource_base m_unsupported_resource_base = null; extern function void m_unsupported_set_local(uvm_resource_base rsrc); typedef struct { string arg; string args[$]; int unsigned used; } uvm_cmdline_parsed_arg_t; static uvm_cmdline_parsed_arg_t m_uvm_applied_cl_action[$]; static uvm_cmdline_parsed_arg_t m_uvm_applied_cl_sev[$]; endclass : uvm_component typedef class uvm_cmdline_processor; typedef class uvm_component_proxy; typedef class uvm_top_down_visitor_adapter; typedef class uvm_report_message; typedef class uvm_report_object; typedef class uvm_report_handler; typedef class uvm_default_report_server; class uvm_root extends uvm_component; extern static function uvm_root get(); uvm_cmdline_processor clp; virtual function string get_type_name(); return "uvm_root"; endfunction extern virtual task run_test (string test_name=""); virtual function void die(); uvm_report_server l_rs = uvm_report_server::get_server(); m_uvm_core_state=UVM_CORE_PRE_ABORT; m_do_pre_abort(); uvm_run_test_callback::m_do_pre_abort(); l_rs.report_summarize(); m_uvm_core_state=UVM_CORE_ABORTED; $finish; endfunction extern function void set_timeout(time timeout, bit overridable=1); local bit finish_on_completion = 1; virtual function bit get_finish_on_completion(); return finish_on_completion; endfunction : get_finish_on_completion virtual function void set_finish_on_completion(bit f); finish_on_completion = f; endfunction : set_finish_on_completion extern function uvm_component find (string comp_match); extern function void find_all (string comp_match, ref uvm_component comps[$], input uvm_component comp=null); extern function void print_topology (uvm_printer printer=null); bit enable_print_topology = 0; extern function void set_enable_print_topology (bit enable); extern function bit get_enable_print_topology (); time phase_timeout = 9200s; extern function void m_find_all_recurse(string comp_match, ref uvm_component comps[$], input uvm_component comp=null); extern protected function new (); extern protected virtual function bit m_add_child (uvm_component child); extern function void build_phase(uvm_phase phase); extern local function void m_do_verbosity_settings(); extern local function void m_do_timeout_settings(); extern local function void m_do_factory_settings(); extern local function void m_process_inst_override(string ovr); extern local function void m_process_type_override(string ovr); extern local function void m_do_config_settings(); extern local function void m_do_max_quit_settings(); extern local function void m_do_dump_args(); extern local function void m_process_config(string cfg, bit is_int); extern local function void m_process_default_sequence(string cfg); extern function void m_check_verbosity(); extern function void m_check_uvm_field_flag_size(); extern virtual function void report_header(UVM_FILE file = 0); static local uvm_root m_inst; extern virtual task run_phase (uvm_phase phase); function void phase_started(uvm_phase phase); if (phase == end_of_elaboration_ph) begin do_resolve_bindings(); if (enable_print_topology) print_topology(); begin uvm_report_server srvr; srvr = uvm_report_server::get_server(); if(srvr.get_severity_count(UVM_ERROR) > 0) begin uvm_report_fatal("BUILDERR", "stopping due to build errors", UVM_NONE); end end end endfunction bit m_phase_all_done; extern static function uvm_root m_uvm_get_root(); static local bit m_relnotes_done=0; function void end_of_elaboration_phase(uvm_phase phase); uvm_component_proxy p = new("proxy"); uvm_top_down_visitor_adapter#(uvm_component) adapter = new("adapter"); uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_visitor#(uvm_component) v = cs.get_component_visitor(); adapter.accept(this, v, p); endfunction endclass function uvm_root uvm_root::get(); uvm_coreservice_t cs = uvm_coreservice_t::get(); return cs.get_root(); endfunction function uvm_root::new(); uvm_report_handler rh; super.new("__top__", null); rh = new("reporter"); set_report_handler(rh); if (m_inst != null) begin begin if (m_inst.uvm_report_enabled(UVM_NONE,UVM_FATAL,"UVM/ROOT/MULTI")) m_inst.uvm_report_fatal ("UVM/ROOT/MULTI", "Attempting to construct multiple roots", UVM_NONE, "t/uvm/src/base/uvm_root.svh", 378, "", 1); end return; end m_inst = this; clp = uvm_cmdline_processor::get_inst(); endfunction function uvm_root uvm_root::m_uvm_get_root(); if (m_inst == null) begin uvm_root top; top = new(); if (top != m_inst) return null; top.m_domain = uvm_domain::get_uvm_domain(); end return m_inst; endfunction function void uvm_root::report_header(UVM_FILE file = 0); string q[$]; uvm_report_server srvr; uvm_cmdline_processor clp; string args[$]; srvr = uvm_report_server::get_server(); clp = uvm_cmdline_processor::get_inst(); if (clp.get_arg_matches("+UVM_NO_RELNOTES", args)) return; if (!m_relnotes_done) begin q.push_back("\n *********** IMPORTANT RELEASE NOTES ************\n"); m_relnotes_done = 1; q.push_back("\n This implementation of the UVM Library deviates from the 1800.2-2017\n"); q.push_back(" standard. See the DEVIATIONS.md file contained in the release\n"); q.push_back(" for more details.\n"); end q.push_back("\n----------------------------------------------------------------\n"); q.push_back({uvm_revision_string(),"\n"}); q.push_back("\n"); q.push_back("All copyright owners for this kit are listed in NOTICE.txt\n"); q.push_back("All Rights Reserved Worldwide\n"); q.push_back("----------------------------------------------------------------\n"); if(m_relnotes_done) q.push_back("\n (Specify +UVM_NO_RELNOTES to turn off this notice)\n"); begin if (uvm_report_enabled(UVM_LOW,UVM_INFO,"UVM/RELNOTES")) uvm_report_info ("UVM/RELNOTES", uvm_pkg::m_uvm_string_queue_join(q), UVM_LOW, "t/uvm/src/base/uvm_root.svh", 449, "", 1); end endfunction task uvm_root::run_test(string test_name=""); uvm_report_server l_rs; uvm_factory factory; bit testname_plusarg; int test_name_count; string test_names[$]; string msg; uvm_component uvm_test_top; process phase_runner_proc; uvm_run_test_callback::m_do_pre_run_test(); factory=uvm_factory::get(); m_uvm_core_state=UVM_CORE_PRE_RUN; testname_plusarg = 0; uvm_objection::m_init_objections(); m_do_dump_args(); if ($value$plusargs("UVM_TESTNAME=%s", test_name)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_INFO,"NO_DPI_TSTNAME")) uvm_report_info ("NO_DPI_TSTNAME", "UVM_NO_DPI defined--getting UVM_TESTNAME directly, without DPI", UVM_NONE, "t/uvm/src/base/uvm_root.svh", 517, "", 1); end testname_plusarg = 1; end if (test_name != "") begin if(m_children.exists("uvm_test_top")) begin uvm_report_fatal("TTINST", "An uvm_test_top already exists via a previous call to run_test", UVM_NONE); #0; end $cast(uvm_test_top, factory.create_component_by_name(test_name, "", "uvm_test_top", null)); if (uvm_test_top == null) begin msg = testname_plusarg ? {"command line +UVM_TESTNAME=",test_name} : {"call to run_test(",test_name,")"}; uvm_report_fatal("INVTST", {"Requested test from ",msg, " not found." }, UVM_NONE); end end if (m_children.num() == 0) begin uvm_report_fatal("NOCOMP", {"No components instantiated. You must either instantiate", " at least one component before calling run_test or use", " run_test to do so. To run a test using run_test,", " use +UVM_TESTNAME or supply the test name in", " the argument to run_test(). Exiting simulation."}, UVM_NONE); return; end begin if(test_name=="") uvm_report_info("RNTST", "Running test ...", UVM_LOW); else if (test_name == uvm_test_top.get_type_name()) uvm_report_info("RNTST", {"Running test ",test_name,"..."}, UVM_LOW); else uvm_report_info("RNTST", {"Running test ",uvm_test_top.get_type_name()," (via factory override for test \"",test_name,"\")..."}, UVM_LOW); end fork begin phase_runner_proc = process::self(); uvm_phase::m_run_phases(); end join_none #0; wait (m_phase_all_done == 1); m_uvm_core_state=UVM_CORE_POST_RUN; phase_runner_proc.kill(); l_rs = uvm_report_server::get_server(); uvm_run_test_callback::m_do_post_run_test(); l_rs.report_summarize(); m_uvm_core_state=UVM_CORE_FINISHED; if (get_finish_on_completion()) $finish; endtask function void uvm_root::find_all(string comp_match, ref uvm_component comps[$], input uvm_component comp=null); if (comp==null) comp = this; m_find_all_recurse(comp_match, comps, comp); endfunction function uvm_component uvm_root::find (string comp_match); uvm_component comp_list[$]; find_all(comp_match,comp_list); if (comp_list.size() > 1) uvm_report_warning("MMATCH", $sformatf("Found %0d components matching '%s'. Returning first match, %0s.", comp_list.size(),comp_match,comp_list[0].get_full_name()), UVM_NONE); if (comp_list.size() == 0) begin uvm_report_warning("CMPNFD", {"Component matching '",comp_match, "' was not found in the list of uvm_components"}, UVM_NONE); return null; end return comp_list[0]; endfunction function void uvm_root::print_topology(uvm_printer printer=null); if (m_children.num()==0) begin uvm_report_warning("EMTCOMP", "print_topology - No UVM components to print.", UVM_NONE); return; end if (printer==null) printer = uvm_printer::get_default(); begin if (uvm_report_enabled(UVM_NONE,UVM_INFO,"UVMTOP")) uvm_report_info ("UVMTOP", "UVM testbench topology:", UVM_NONE, "t/uvm/src/base/uvm_root.svh", 640, "", 1); end print(printer) ; endfunction function void uvm_root::set_timeout(time timeout, bit overridable=1); static bit m_uvm_timeout_overridable = 1; if (m_uvm_timeout_overridable == 0) begin uvm_report_info("NOTIMOUTOVR", $sformatf("The global timeout setting of %0d is not overridable to %0d due to a previous setting.", phase_timeout, timeout), UVM_NONE); return; end m_uvm_timeout_overridable = overridable; phase_timeout = timeout; endfunction function void uvm_root::m_find_all_recurse(string comp_match, ref uvm_component comps[$], input uvm_component comp=null); string name; if (comp.get_first_child(name)) do begin this.m_find_all_recurse(comp_match, comps, comp.get_child(name)); end while (comp.get_next_child(name)); if (uvm_is_match(comp_match, comp.get_full_name()) && comp.get_name() != "") comps.push_back(comp); endfunction function bit uvm_root::m_add_child (uvm_component child); if(super.m_add_child(child)) begin return 1; end else return 0; endfunction function void uvm_root::build_phase(uvm_phase phase); super.build_phase(phase); m_set_cl_msg_args(); m_do_verbosity_settings(); m_do_timeout_settings(); m_do_factory_settings(); m_do_config_settings(); m_do_max_quit_settings(); endfunction function void uvm_root::m_do_verbosity_settings(); string set_verbosity_settings[$]; string split_vals[$]; uvm_verbosity tmp_verb; void'(clp.get_arg_values("+uvm_set_verbosity=", set_verbosity_settings)); for(int i = 0; i < set_verbosity_settings.size(); i++) begin uvm_split_string(set_verbosity_settings[i], ",", split_vals); if(split_vals.size() < 4 || split_vals.size() > 5) begin uvm_report_warning("INVLCMDARGS", $sformatf("Invalid number of arguments found on the command line for setting '+uvm_set_verbosity=%s'. Setting ignored.", set_verbosity_settings[i]), UVM_NONE, "", ""); end if(!clp.m_convert_verb(split_vals[2], tmp_verb)) begin uvm_report_warning("INVLCMDVERB", $sformatf("Invalid verbosity found on the command line for setting '%s'.", set_verbosity_settings[i]), UVM_NONE, "", ""); end end endfunction function void uvm_root::m_do_timeout_settings(); string timeout_settings[$]; string timeout; string split_timeout[$]; int timeout_count; time timeout_int; string override_spec; timeout_count = clp.get_arg_values("+UVM_TIMEOUT=", timeout_settings); if (timeout_count == 0) return; else begin timeout = timeout_settings[0]; if (timeout_count > 1) begin string timeout_list; string sep; for (int i = 0; i < timeout_settings.size(); i++) begin if (i != 0) sep = "; "; timeout_list = {timeout_list, sep, timeout_settings[i]}; end uvm_report_warning("MULTTIMOUT", $sformatf("Multiple (%0d) +UVM_TIMEOUT arguments provided on the command line. '%s' will be used. Provided list: %s.", timeout_count, timeout, timeout_list), UVM_NONE); end uvm_report_info("TIMOUTSET", $sformatf("'+UVM_TIMEOUT=%s' provided on the command line is being applied.", timeout), UVM_NONE); void'($sscanf(timeout,"%d,%s",timeout_int,override_spec)); case(override_spec) "YES" : set_timeout(timeout_int, 1); "NO" : set_timeout(timeout_int, 0); default : set_timeout(timeout_int, 1); endcase end endfunction function void uvm_root::m_do_factory_settings(); string args[$]; void'(clp.get_arg_matches("/^\\+(UVM_SET_INST_OVERRIDE|uvm_set_inst_override)=/",args)); foreach(args[i]) begin m_process_inst_override(args[i].substr(23, args[i].len()-1)); end void'(clp.get_arg_matches("/^\\+(UVM_SET_TYPE_OVERRIDE|uvm_set_type_override)=/",args)); foreach(args[i]) begin m_process_type_override(args[i].substr(23, args[i].len()-1)); end endfunction function void uvm_root::m_process_inst_override(string ovr); string split_val[$]; uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory factory=cs.get_factory(); uvm_split_string(ovr, ",", split_val); if(split_val.size() != 3 ) begin uvm_report_error("UVM_CMDLINE_PROC", {"Invalid setting for +uvm_set_inst_override=", ovr, ", setting must specify ,,"}, UVM_NONE); return; end uvm_report_info("INSTOVR", {"Applying instance override from the command line: +uvm_set_inst_override=", ovr}, UVM_NONE); factory.set_inst_override_by_name(split_val[0], split_val[1], split_val[2]); endfunction function void uvm_root::m_process_type_override(string ovr); string split_val[$]; int replace=1; uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory factory=cs.get_factory(); uvm_split_string(ovr, ",", split_val); if(split_val.size() > 3 || split_val.size() < 2) begin uvm_report_error("UVM_CMDLINE_PROC", {"Invalid setting for +uvm_set_type_override=", ovr, ", setting must specify ,[,]"}, UVM_NONE); return; end if(split_val.size() == 3) begin if(split_val[2]=="0") replace = 0; else if (split_val[2] == "1") replace = 1; else begin uvm_report_error("UVM_CMDLINE_PROC", {"Invalid replace arg for +uvm_set_type_override=", ovr ," value must be 0 or 1"}, UVM_NONE); return; end end uvm_report_info("UVM_CMDLINE_PROC", {"Applying type override from the command line: +uvm_set_type_override=", ovr}, UVM_NONE); factory.set_type_override_by_name(split_val[0], split_val[1], replace); endfunction function void uvm_root::m_process_config(string cfg, bit is_int); uvm_bitstream_t v; string split_val[$]; uvm_root m_uvm_top; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); m_uvm_top = cs.get_root(); uvm_split_string(cfg, ",", split_val); if(split_val.size() == 1) begin uvm_report_error("UVM_CMDLINE_PROC", {"Invalid +uvm_set_config command\"", cfg, "\" missing field and value: component is \"", split_val[0], "\""}, UVM_NONE); return; end if(split_val.size() == 2) begin uvm_report_error("UVM_CMDLINE_PROC", {"Invalid +uvm_set_config command\"", cfg, "\" missing value: component is \"", split_val[0], "\" field is \"", split_val[1], "\""}, UVM_NONE); return; end if(split_val.size() > 3) begin uvm_report_error("UVM_CMDLINE_PROC", $sformatf("Invalid +uvm_set_config command\"%s\" : expected only 3 fields (component, field and value).", cfg), UVM_NONE); return; end if(is_int) begin if(split_val[2].len() > 2) begin string base, extval; base = split_val[2].substr(0,1); extval = split_val[2].substr(2,split_val[2].len()-1); case(base) "'b" : v = extval.atobin(); "0b" : v = extval.atobin(); "'o" : v = extval.atooct(); "'d" : v = extval.atoi(); "'h" : v = extval.atohex(); "'x" : v = extval.atohex(); "0x" : v = extval.atohex(); default : v = split_val[2].atoi(); endcase end else begin v = split_val[2].atoi(); end uvm_report_info("UVM_CMDLINE_PROC", {"Applying config setting from the command line: +uvm_set_config_int=", cfg}, UVM_NONE); uvm_config_int::set(m_uvm_top, split_val[0], split_val[1], v); end else begin uvm_report_info("UVM_CMDLINE_PROC", {"Applying config setting from the command line: +uvm_set_config_string=", cfg}, UVM_NONE); uvm_config_string::set(m_uvm_top, split_val[0], split_val[1], split_val[2]); end endfunction function void uvm_root::m_process_default_sequence(string cfg); string split_val[$]; uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_root m_uvm_top = cs.get_root(); uvm_factory f = cs.get_factory(); uvm_object_wrapper w; uvm_split_string(cfg, ",", split_val); if(split_val.size() == 1) begin uvm_report_error("UVM_CMDLINE_PROC", {"Invalid +uvm_set_default_sequence command\"", cfg, "\" missing phase and type: sequencer is \"", split_val[0], "\""}, UVM_NONE); return; end if(split_val.size() == 2) begin uvm_report_error("UVM_CMDLINE_PROC", {"Invalid +uvm_set_default_sequence command\"", cfg, "\" missing type: sequencer is \"", split_val[0], "\" phase is \"", split_val[1], "\""}, UVM_NONE); return; end if(split_val.size() > 3) begin uvm_report_error("UVM_CMDLINE_PROC", $sformatf("Invalid +uvm_set_default_sequence command\"%s\" : expected only 3 fields (sequencer, phase and type).", cfg), UVM_NONE); return; end w = f.find_wrapper_by_name(split_val[2]); if (w == null) begin uvm_report_error("UVM_CMDLINE_PROC", $sformatf("Invalid type '%s' provided to +uvm_set_default_sequence", split_val[2]), UVM_NONE); return; end else begin uvm_report_info("UVM_CMDLINE_PROC", {"Setting default sequence from the command line: +uvm_set_default_sequence=", cfg}, UVM_NONE); uvm_config_db#(uvm_object_wrapper)::set(this, {split_val[0], ".", split_val[1]}, "default_sequence", w); end endfunction : m_process_default_sequence function void uvm_root::m_do_config_settings(); string args[$]; void'(clp.get_arg_matches("/^\\+(UVM_SET_CONFIG_INT|uvm_set_config_int)=/",args)); foreach(args[i]) begin m_process_config(args[i].substr(20, args[i].len()-1), 1); end void'(clp.get_arg_matches("/^\\+(UVM_SET_CONFIG_STRING|uvm_set_config_string)=/",args)); foreach(args[i]) begin m_process_config(args[i].substr(23, args[i].len()-1), 0); end void'(clp.get_arg_matches("/^\\+(UVM_SET_DEFAULT_SEQUENCE|uvm_set_default_sequence)=/", args)); foreach(args[i]) begin m_process_default_sequence(args[i].substr(26, args[i].len()-1)); end endfunction function void uvm_root::m_do_max_quit_settings(); uvm_report_server srvr; string max_quit_settings[$]; int max_quit_count; string max_quit; string split_max_quit[$]; int max_quit_int; srvr = uvm_report_server::get_server(); max_quit_count = clp.get_arg_values("+UVM_MAX_QUIT_COUNT=", max_quit_settings); if (max_quit_count == 0) return; else begin max_quit = max_quit_settings[0]; if (max_quit_count > 1) begin string max_quit_list; string sep; for (int i = 0; i < max_quit_settings.size(); i++) begin if (i != 0) sep = "; "; max_quit_list = {max_quit_list, sep, max_quit_settings[i]}; end uvm_report_warning("MULTMAXQUIT", $sformatf("Multiple (%0d) +UVM_MAX_QUIT_COUNT arguments provided on the command line. '%s' will be used. Provided list: %s.", max_quit_count, max_quit, max_quit_list), UVM_NONE); end uvm_report_info("MAXQUITSET", $sformatf("'+UVM_MAX_QUIT_COUNT=%s' provided on the command line is being applied.", max_quit), UVM_NONE); uvm_split_string(max_quit, ",", split_max_quit); max_quit_int = split_max_quit[0].atoi(); case(split_max_quit[1]) "YES" : srvr.set_max_quit_count(max_quit_int, 1); "NO" : srvr.set_max_quit_count(max_quit_int, 0); default : srvr.set_max_quit_count(max_quit_int, 1); endcase end endfunction function void uvm_root::m_do_dump_args(); string dump_args[$]; string all_args[$]; string out_string; if(clp.get_arg_matches("+UVM_DUMP_CMDLINE_ARGS", dump_args)) begin clp.get_args(all_args); foreach (all_args[idx]) begin uvm_report_info("DUMPARGS", $sformatf("idx=%0d arg=[%s]",idx,all_args[idx]), UVM_NONE); end end endfunction function void uvm_root::m_check_verbosity(); string verb_string; string verb_settings[$]; int verb_count; int plusarg; int verbosity = UVM_MEDIUM; verb_count = $value$plusargs("UVM_VERBOSITY=%s",verb_string); if (verb_count) verb_settings.push_back(verb_string); if (verb_count > 0) begin verb_string = verb_settings[0]; plusarg = 1; end if (verb_count > 1) begin string verb_list; string sep; for (int i = 0; i < verb_settings.size(); i++) begin if (i != 0) sep = ", "; verb_list = {verb_list, sep, verb_settings[i]}; end uvm_report_warning("MULTVERB", $sformatf("Multiple (%0d) +UVM_VERBOSITY arguments provided on the command line. '%s' will be used. Provided list: %s.", verb_count, verb_string, verb_list), UVM_NONE); end if(plusarg == 1) begin case(verb_string) "UVM_NONE" : verbosity = UVM_NONE; "NONE" : verbosity = UVM_NONE; "UVM_LOW" : verbosity = UVM_LOW; "LOW" : verbosity = UVM_LOW; "UVM_MEDIUM" : verbosity = UVM_MEDIUM; "MEDIUM" : verbosity = UVM_MEDIUM; "UVM_HIGH" : verbosity = UVM_HIGH; "HIGH" : verbosity = UVM_HIGH; "UVM_FULL" : verbosity = UVM_FULL; "FULL" : verbosity = UVM_FULL; "UVM_DEBUG" : verbosity = UVM_DEBUG; "DEBUG" : verbosity = UVM_DEBUG; default : begin verbosity = verb_string.atoi(); if(verbosity > 0) uvm_report_info("NSTVERB", $sformatf("Non-standard verbosity value, using provided '%0d'.", verbosity), UVM_NONE); if(verbosity == 0) begin verbosity = UVM_MEDIUM; uvm_report_warning("ILLVERB", "Illegal verbosity value, using default of UVM_MEDIUM.", UVM_NONE); end end endcase end set_report_verbosity_level_hier(verbosity); endfunction function void uvm_root::m_check_uvm_field_flag_size(); if ( (UVM_FIELD_FLAG_RESERVED_BITS) < UVM_FIELD_FLAG_RESERVED_BITS ) begin uvm_report_fatal( "BAD_FIELD_FLAG_SZ", $sformatf( "Macro UVM_FIELD_FLAG_SIZE is set to %0d which is less than the required minimum of UVM_FIELD_FLAG_RESERVED_BITS (%0d).", UVM_FIELD_FLAG_RESERVED_BITS, UVM_FIELD_FLAG_RESERVED_BITS ) ); end endfunction task uvm_root::run_phase (uvm_phase phase); foreach(m_uvm_applied_cl_action[idx]) if(m_uvm_applied_cl_action[idx].used==0) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"INVLCMDARGS")) uvm_report_warning ("INVLCMDARGS", $sformatf("\"+uvm_set_action=%s\" never took effect due to a mismatching component pattern",m_uvm_applied_cl_action[idx].arg), UVM_NONE, "t/uvm/src/base/uvm_root.svh", 1130, "", 1); end end foreach(m_uvm_applied_cl_sev[idx]) if(m_uvm_applied_cl_sev[idx].used==0) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"INVLCMDARGS")) uvm_report_warning ("INVLCMDARGS", $sformatf("\"+uvm_set_severity=%s\" never took effect due to a mismatching component pattern",m_uvm_applied_cl_sev[idx].arg), UVM_NONE, "t/uvm/src/base/uvm_root.svh", 1134, "", 1); end end if($time > 0) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"RUNPHSTIME")) uvm_report_fatal ("RUNPHSTIME", {"The run phase must start at time 0, current time is ", $sformatf("%0t", $realtime), ". No non-zero delays are allowed before ", "run_test(), and pre-run user defined phases may not consume ", "simulation time before the start of the run phase."}, UVM_NONE, "t/uvm/src/base/uvm_root.svh", 1141, "", 1); end endtask function void uvm_root::set_enable_print_topology (bit enable); enable_print_topology = enable; endfunction function bit uvm_root::get_enable_print_topology(); return enable_print_topology; endfunction function uvm_component::new (string name, uvm_component parent); string error_str; uvm_root top; uvm_coreservice_t cs; super.new(name); if (parent==null && name == "__top__") begin set_name(""); return; end cs = uvm_coreservice_t::get(); top = cs.get_root(); begin uvm_phase bld; uvm_domain common; common = uvm_domain::get_common_domain(); bld = common.find(uvm_build_phase::get()); if (bld == null) uvm_report_fatal("COMP/INTERNAL", "attempt to find build phase object failed",UVM_NONE); if (bld.get_state() == UVM_PHASE_DONE) begin uvm_report_fatal("ILLCRT", {"It is illegal to create a component ('", name,"' under '", (parent == null ? top.get_full_name() : parent.get_full_name()), "') after the build phase has ended."}, UVM_NONE); end end if (name == "") begin name.itoa(m_inst_count); name = {"COMP_", name}; end if(parent == this) begin begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"THISPARENT")) uvm_report_fatal ("THISPARENT", "cannot set the parent of a component to itself", UVM_NONE, "t/uvm/src/base/uvm_component.svh", 1635, "", 1); end end if (parent == null) parent = top; if(uvm_report_enabled(UVM_MEDIUM+1, UVM_INFO, "NEWCOMP")) begin if (uvm_report_enabled(UVM_MEDIUM+1,UVM_INFO,"NEWCOMP")) uvm_report_info ("NEWCOMP", {"Creating ", (parent==top?"uvm_top":parent.get_full_name()),".",name}, UVM_MEDIUM+1, "t/uvm/src/base/uvm_component.svh", 1643, "", 1); end if (parent.has_child(name) && this != parent.get_child(name)) begin if (parent == top) begin error_str = {"Name '",name,"' is not unique to other top-level ", "instances. If parent is a module, build a unique name by combining the ", "the module name and component name: $sformatf(\"\%m.\%s\",\"",name,"\")."}; begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"CLDEXT")) uvm_report_fatal ("CLDEXT", error_str, UVM_NONE, "t/uvm/src/base/uvm_component.svh", 1650, "", 1); end end else begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"CLDEXT")) uvm_report_fatal ("CLDEXT", $sformatf("Cannot set '%s' as a child of '%s', %s", name, parent.get_full_name(), "which already has a child by that name."), UVM_NONE, "t/uvm/src/base/uvm_component.svh", 1656, "", 1); end return; end m_parent = parent; set_name(name); if (!m_parent.m_add_child(this)) m_parent = null; event_pool = new("event_pool"); m_domain = parent.m_domain; reseed(); if (!uvm_config_db #(uvm_bitstream_t)::get(this, "", "recording_detail", recording_detail)) void'(uvm_config_db #(int)::get(this, "", "recording_detail", recording_detail)); m_rh.set_name(get_full_name()); set_report_verbosity_level(parent.get_report_verbosity_level()); m_set_cl_msg_args(); endfunction function bit uvm_component::m_add_child(uvm_component child); if (m_children.exists(child.get_name()) && m_children[child.get_name()] != child) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"BDCLD")) uvm_report_warning ("BDCLD", $sformatf("A child with the name '%0s' (type=%0s) already exists.", child.get_name(), m_children[child.get_name()].get_type_name()), UVM_NONE, "t/uvm/src/base/uvm_component.svh", 1695, "", 1); end return 0; end if (m_children_by_handle.exists(child)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"BDCHLD")) uvm_report_warning ("BDCHLD", $sformatf("A child with the name '%0s' %0s %0s'", child.get_name(), "already exists in parent under name '", m_children_by_handle[child].get_name()), UVM_NONE, "t/uvm/src/base/uvm_component.svh", 1704, "", 1); end return 0; end m_children[child.get_name()] = child; m_children_by_handle[child] = child; return 1; endfunction function void uvm_component::get_children(ref uvm_component children[$]); foreach(m_children[i]) children.push_back(m_children[i]); endfunction function int uvm_component::get_first_child(ref string name); return m_children.first(name); endfunction function int uvm_component::get_next_child(ref string name); return m_children.next(name); endfunction function uvm_component uvm_component::get_child(string name); if (m_children.exists(name)) return m_children[name]; begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"NOCHILD")) uvm_report_warning ("NOCHILD", {"Component with name '",name, "' is not a child of component '",get_full_name(),"'"}, UVM_NONE, "t/uvm/src/base/uvm_component.svh", 1754, "", 1); end return null; endfunction function int uvm_component::has_child(string name); return m_children.exists(name); endfunction function int uvm_component::get_num_children(); return m_children.num(); endfunction function string uvm_component::get_full_name (); if(m_name == "") return get_name(); else return m_name; endfunction function uvm_component uvm_component::get_parent (); return m_parent; endfunction function void uvm_component::set_name (string name); if(m_name != "") begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"INVSTNM")) uvm_report_error ("INVSTNM", $sformatf("It is illegal to change the name of a component. The component name will not be changed to \"%s\"", name), UVM_NONE, "t/uvm/src/base/uvm_component.svh", 1801, "", 1); end return; end super.set_name(name); m_set_full_name(); endfunction function void uvm_component::m_set_full_name(); uvm_root top; if ($cast(top, m_parent) || m_parent==null) m_name = get_name(); else m_name = {m_parent.get_full_name(), ".", get_name()}; foreach (m_children[c]) begin uvm_component tmp; tmp = m_children[c]; tmp.m_set_full_name(); end endfunction function uvm_component uvm_component::lookup( string name ); string leaf , remainder; uvm_component comp; uvm_root top; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); top = cs.get_root(); comp = this; m_extract_name(name, leaf, remainder); if (leaf == "") begin comp = top; m_extract_name(remainder, leaf, remainder); end if (!comp.has_child(leaf)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"Lookup Error")) uvm_report_warning ("Lookup Error", $sformatf("Cannot find child %0s",leaf), UVM_NONE, "t/uvm/src/base/uvm_component.svh", 1852, "", 1); end return null; end if( remainder != "" ) return comp.m_children[leaf].lookup(remainder); return comp.m_children[leaf]; endfunction function int unsigned uvm_component::get_depth(); if(m_name == "") return 0; get_depth = 1; foreach(m_name[i]) if(m_name[i] == ".") ++get_depth; endfunction function void uvm_component::m_extract_name(input string name , output string leaf , output string remainder ); int i , len; len = name.len(); for( i = 0; i < name.len(); i++ ) begin if( name[i] == "." ) begin break; end end if( i == len ) begin leaf = name; remainder = ""; return; end leaf = name.substr( 0 , i - 1 ); remainder = name.substr( i + 1 , len - 1 ); return; endfunction function void uvm_component::flush(); return; endfunction function void uvm_component::do_flush(); foreach( m_children[s] ) m_children[s].do_flush(); flush(); endfunction function uvm_object uvm_component::create (string name =""); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"ILLCRT")) uvm_report_error ("ILLCRT", "create cannot be called on a uvm_component. Use create_component instead.", UVM_NONE, "t/uvm/src/base/uvm_component.svh", 1934, "", 1); end return null; endfunction function uvm_object uvm_component::clone (); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"ILLCLN")) uvm_report_error ("ILLCLN", $sformatf("Attempting to clone '%s'. Clone cannot be called on a uvm_component. The clone target variable will be set to null.", get_full_name()), UVM_NONE, "t/uvm/src/base/uvm_component.svh", 1943, "", 1); end return null; endfunction function void uvm_component::print_override_info (string requested_type_name, string name=""); uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory factory=cs.get_factory(); factory.debug_create_by_name(requested_type_name, get_full_name(), name); endfunction function uvm_component uvm_component::create_component (string requested_type_name, string name); uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory factory=cs.get_factory(); return factory.create_component_by_name(requested_type_name, get_full_name(), name, this); endfunction function uvm_object uvm_component::create_object (string requested_type_name, string name=""); uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory factory=cs.get_factory(); return factory.create_object_by_name(requested_type_name, get_full_name(), name); endfunction function void uvm_component::set_type_override (string original_type_name, string override_type_name, bit replace=1); uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory factory=cs.get_factory(); factory.set_type_override_by_name(original_type_name,override_type_name, replace); endfunction function void uvm_component::set_type_override_by_type (uvm_object_wrapper original_type, uvm_object_wrapper override_type, bit replace=1); uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory factory=cs.get_factory(); factory.set_type_override_by_type(original_type, override_type, replace); endfunction function void uvm_component::set_inst_override (string relative_inst_path, string original_type_name, string override_type_name); string full_inst_path; uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory factory=cs.get_factory(); if (relative_inst_path == "") full_inst_path = get_full_name(); else full_inst_path = {get_full_name(), ".", relative_inst_path}; factory.set_inst_override_by_name( original_type_name, override_type_name, full_inst_path); endfunction function void uvm_component::set_inst_override_by_type (string relative_inst_path, uvm_object_wrapper original_type, uvm_object_wrapper override_type); string full_inst_path; uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory factory=cs.get_factory(); if (relative_inst_path == "") full_inst_path = get_full_name(); else full_inst_path = {get_full_name(), ".", relative_inst_path}; factory.set_inst_override_by_type(original_type, override_type, full_inst_path); endfunction function void uvm_component::set_report_id_verbosity_hier( string id, int verbosity); set_report_id_verbosity(id, verbosity); foreach( m_children[c] ) m_children[c].set_report_id_verbosity_hier(id, verbosity); endfunction function void uvm_component::set_report_severity_id_verbosity_hier( uvm_severity severity, string id, int verbosity); set_report_severity_id_verbosity(severity, id, verbosity); foreach( m_children[c] ) m_children[c].set_report_severity_id_verbosity_hier(severity, id, verbosity); endfunction function void uvm_component::set_report_severity_action_hier( uvm_severity severity, uvm_action action); set_report_severity_action(severity, action); foreach( m_children[c] ) m_children[c].set_report_severity_action_hier(severity, action); endfunction function void uvm_component::set_report_id_action_hier( string id, uvm_action action); set_report_id_action(id, action); foreach( m_children[c] ) m_children[c].set_report_id_action_hier(id, action); endfunction function void uvm_component::set_report_severity_id_action_hier( uvm_severity severity, string id, uvm_action action); set_report_severity_id_action(severity, id, action); foreach( m_children[c] ) m_children[c].set_report_severity_id_action_hier(severity, id, action); endfunction function void uvm_component::set_report_severity_file_hier( uvm_severity severity, UVM_FILE file); set_report_severity_file(severity, file); foreach( m_children[c] ) m_children[c].set_report_severity_file_hier(severity, file); endfunction function void uvm_component::set_report_default_file_hier( UVM_FILE file); set_report_default_file(file); foreach( m_children[c] ) m_children[c].set_report_default_file_hier(file); endfunction function void uvm_component::set_report_id_file_hier( string id, UVM_FILE file); set_report_id_file(id, file); foreach( m_children[c] ) m_children[c].set_report_id_file_hier(id, file); endfunction function void uvm_component::set_report_severity_id_file_hier ( uvm_severity severity, string id, UVM_FILE file); set_report_severity_id_file(severity, id, file); foreach( m_children[c] ) m_children[c].set_report_severity_id_file_hier(severity, id, file); endfunction function void uvm_component::set_report_verbosity_level_hier(int verbosity); set_report_verbosity_level(verbosity); foreach( m_children[c] ) m_children[c].set_report_verbosity_level_hier(verbosity); endfunction function void uvm_component::build_phase(uvm_phase phase); m_build_done = 1; if (use_automatic_config()) apply_config_settings(print_config_matches); endfunction function void uvm_component::connect_phase(uvm_phase phase); return; endfunction function void uvm_component::start_of_simulation_phase(uvm_phase phase); return; endfunction function void uvm_component::end_of_elaboration_phase(uvm_phase phase); return; endfunction task uvm_component::run_phase(uvm_phase phase); return; endtask function void uvm_component::extract_phase(uvm_phase phase); return; endfunction function void uvm_component::check_phase(uvm_phase phase); return; endfunction function void uvm_component::report_phase(uvm_phase phase); return; endfunction function void uvm_component::final_phase(uvm_phase phase); return; endfunction task uvm_component::pre_reset_phase(uvm_phase phase); return; endtask task uvm_component::reset_phase(uvm_phase phase); return; endtask task uvm_component::post_reset_phase(uvm_phase phase); return; endtask task uvm_component::pre_configure_phase(uvm_phase phase); return; endtask task uvm_component::configure_phase(uvm_phase phase); return; endtask task uvm_component::post_configure_phase(uvm_phase phase); return; endtask task uvm_component::pre_main_phase(uvm_phase phase); return; endtask task uvm_component::main_phase(uvm_phase phase); return; endtask task uvm_component::post_main_phase(uvm_phase phase); return; endtask task uvm_component::pre_shutdown_phase(uvm_phase phase); return; endtask task uvm_component::shutdown_phase(uvm_phase phase); return; endtask task uvm_component::post_shutdown_phase(uvm_phase phase); return; endtask function void uvm_component::phase_started(uvm_phase phase); endfunction function void uvm_component::phase_ended(uvm_phase phase); endfunction function void uvm_component::phase_ready_to_end (uvm_phase phase); endfunction function void uvm_component::define_domain(uvm_domain domain); uvm_phase schedule; schedule = domain.find_by_name("uvm_sched"); if (schedule == null) begin uvm_domain common; schedule = new("uvm_sched", UVM_PHASE_SCHEDULE); uvm_domain::add_uvm_phases(schedule); domain.add(schedule); common = uvm_domain::get_common_domain(); if (common.find(domain,0) == null) common.add(domain,.with_phase(uvm_run_phase::get())); end endfunction function void uvm_component::set_domain(uvm_domain domain, int hier=1); m_domain = domain; define_domain(domain); if (hier) foreach (m_children[c]) m_children[c].set_domain(domain); endfunction function uvm_domain uvm_component::get_domain(); return m_domain; endfunction task uvm_component::suspend(); begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"COMP/SPND/UNIMP")) uvm_report_warning ("COMP/SPND/UNIMP", "suspend() not implemented", UVM_NONE, "t/uvm/src/base/uvm_component.svh", 2395, "", 1); end endtask task uvm_component::resume(); begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"COMP/RSUM/UNIMP")) uvm_report_warning ("COMP/RSUM/UNIMP", "resume() not implemented", UVM_NONE, "t/uvm/src/base/uvm_component.svh", 2403, "", 1); end endtask function void uvm_component::resolve_bindings(); return; endfunction function void uvm_component::do_resolve_bindings(); foreach( m_children[s] ) m_children[s].do_resolve_bindings(); resolve_bindings(); endfunction function void uvm_component::accept_tr (uvm_transaction tr, time accept_time=0); uvm_event#(uvm_object) e; if(tr == null) return; tr.accept_tr(accept_time); do_accept_tr(tr); e = event_pool.get("accept_tr"); if(e!=null) e.trigger(); endfunction function int uvm_component::begin_tr (uvm_transaction tr, string stream_name="main", string label="", string desc="", time begin_time=0, int parent_handle=0); return m_begin_tr(tr, parent_handle, stream_name, label, desc, begin_time); endfunction function uvm_tr_database uvm_component::get_tr_database(); if (tr_database == null) begin uvm_coreservice_t cs = uvm_coreservice_t::get(); tr_database = cs.get_default_tr_database(); end return tr_database; endfunction : get_tr_database function void uvm_component::set_tr_database(uvm_tr_database db); tr_database = db; endfunction : set_tr_database function uvm_tr_stream uvm_component::get_tr_stream( string name, string stream_type_name="" ); uvm_tr_database db = get_tr_database(); if (!m_streams.exists(name) || !m_streams[name].exists(stream_type_name)) m_streams[name][stream_type_name] = db.open_stream(name, this.get_full_name(), stream_type_name); return m_streams[name][stream_type_name]; endfunction : get_tr_stream function void uvm_component::free_tr_stream(uvm_tr_stream stream); if (stream == null) return; if (!m_streams.exists(stream.get_name()) || !m_streams[stream.get_name()].exists(stream.get_stream_type_name())) return; if (m_streams[stream.get_name()][stream.get_stream_type_name()] != stream) return; m_streams[stream.get_name()].delete(stream.get_type_name()); if (m_streams[stream.get_name()].size() == 0) m_streams.delete(stream.get_name()); if (stream.is_open() || stream.is_closed()) begin stream.free(); end endfunction : free_tr_stream function int uvm_component::m_begin_tr (uvm_transaction tr, int parent_handle=0, string stream_name="main", string label="", string desc="", time begin_time=0); uvm_event#(uvm_object) e; string name; string kind; uvm_tr_database db; int handle, link_handle; uvm_tr_stream stream; uvm_recorder recorder, parent_recorder, link_recorder; if (tr == null) return 0; db = get_tr_database(); if (parent_handle != 0) parent_recorder = uvm_recorder::get_recorder_from_handle(parent_handle); if (parent_recorder == null) begin uvm_sequence_item seq; if ($cast(seq,tr)) begin uvm_sequence_base parent_seq = seq.get_parent_sequence(); if (parent_seq != null) begin parent_recorder = parent_seq.m_tr_recorder; end end end if(parent_recorder != null) begin link_handle = tr.begin_child_tr(begin_time, parent_recorder.get_handle()); end else begin link_handle = tr.begin_tr(begin_time); end if (link_handle != 0) link_recorder = uvm_recorder::get_recorder_from_handle(link_handle); if (tr.get_name() != "") name = tr.get_name(); else name = tr.get_type_name(); if (uvm_verbosity'(recording_detail) != UVM_NONE) begin if (stream_name == "") stream_name = "main"; stream = get_tr_stream(stream_name, "TVM"); if (stream != null ) begin kind = (parent_recorder == null) ? "Begin_No_Parent, Link" : "Begin_End, Link"; recorder = stream.open_recorder(name, begin_time, kind); if (recorder != null) begin if (label != "") recorder.record_string("label", label); if (desc != "") recorder.record_string("desc", desc); if (parent_recorder != null) begin tr_database.establish_link(uvm_parent_child_link::get_link(parent_recorder, recorder)); end if (link_recorder != null) begin tr_database.establish_link(uvm_related_link::get_link(recorder, link_recorder)); end m_tr_h[tr] = recorder; end end handle = (recorder == null) ? 0 : recorder.get_handle(); do_begin_tr(tr, stream_name, handle); end e = event_pool.get("begin_tr"); if (e!=null) e.trigger(tr); return handle; endfunction function void uvm_component::end_tr (uvm_transaction tr, time end_time=0, bit free_handle=1); uvm_event#(uvm_object) e; uvm_recorder recorder; if (tr == null) return; tr.end_tr(end_time,free_handle); if (uvm_verbosity'(recording_detail) != UVM_NONE) begin if (m_tr_h.exists(tr)) begin recorder = m_tr_h[tr]; do_end_tr(tr, recorder.get_handle()); m_tr_h.delete(tr); tr.record(recorder); recorder.close(end_time); if (free_handle) recorder.free(); end else begin do_end_tr(tr, 0); end end e = event_pool.get("end_tr"); if(e!=null) e.trigger(); endfunction function int uvm_component::record_error_tr (string stream_name="main", uvm_object info=null, string label="error_tr", string desc="", time error_time=0, bit keep_active=0); uvm_recorder recorder; string etype; uvm_tr_stream stream; int handle; if(keep_active) etype = "Error, Link"; else etype = "Error"; if(error_time == 0) error_time = $realtime; if (stream_name == "") stream_name = "main"; stream = get_tr_stream(stream_name, "TVM"); handle = 0; if (stream != null) begin recorder = stream.open_recorder(label, error_time, etype); if (recorder != null) begin if (label != "") recorder.record_string("label", label); if (desc != "") recorder.record_string("desc", desc); if (info!=null) info.record(recorder); recorder.close(error_time); if (keep_active == 0) begin recorder.free(); end else begin handle = recorder.get_handle(); end end end return handle; endfunction function int uvm_component::record_event_tr (string stream_name="main", uvm_object info=null, string label="event_tr", string desc="", time event_time=0, bit keep_active=0); uvm_recorder recorder; string etype; int handle; uvm_tr_stream stream; if(keep_active) etype = "Event, Link"; else etype = "Event"; if(event_time == 0) event_time = $realtime; if (stream_name == "") stream_name = "main"; stream = get_tr_stream(stream_name, "TVM"); handle = 0; if (stream != null) begin recorder = stream.open_recorder(label, event_time, etype); if (recorder != null) begin if (label != "") recorder.record_string("label", label); if (desc != "") recorder.record_string("desc", desc); if (info!=null) info.record(recorder); recorder.close(event_time); if (keep_active == 0) begin recorder.free(); end else begin handle = recorder.get_handle(); end end end return handle; endfunction function void uvm_component::do_accept_tr (uvm_transaction tr); return; endfunction function void uvm_component::do_begin_tr (uvm_transaction tr, string stream_name, int tr_handle); return; endfunction function void uvm_component::do_end_tr (uvm_transaction tr, int tr_handle); return; endfunction function string uvm_component::massage_scope(string scope); if(scope == "") return "^$"; if(scope == "*") return {get_full_name(), ".*"}; if(scope == "uvm_test_top") return "uvm_test_top"; if(scope[0] == ".") return {get_full_name(), scope}; return {get_full_name(), ".", scope}; endfunction function bit uvm_component::use_automatic_config(); return 1; endfunction function void uvm_component::apply_config_settings (bit verbose=0); uvm_resource_pool rp = uvm_resource_pool::get(); uvm_queue#(uvm_resource_base) rq; uvm_resource_base r; rq = rp.lookup_scope(get_full_name()); rp.sort_by_precedence(rq); for(int i=rq.size()-1; i>=0; --i) begin r = rq.get(i); if(verbose) uvm_report_info("CFGAPL",$sformatf("applying configuration to field %s", r.get_name()),UVM_NONE); set_local(r); end endfunction function void uvm_component::print_config(bit recurse = 0, audit = 0); uvm_resource_pool rp = uvm_resource_pool::get(); uvm_report_info("CFGPRT","visible resources:",UVM_INFO); rp.print_resources(rp.lookup_scope(get_full_name()), audit); if(recurse) begin uvm_component c; foreach(m_children[name]) begin c = m_children[name]; c.print_config(recurse, audit); end end endfunction function void uvm_component::print_config_with_audit(bit recurse = 0); print_config(recurse, 1); endfunction function void uvm_component::do_print(uvm_printer printer); super.do_print(printer); if(uvm_verbosity'(recording_detail) != UVM_NONE) case (recording_detail) UVM_LOW : printer.print_generic("recording_detail", "uvm_verbosity", $bits(recording_detail), "UVM_LOW"); UVM_MEDIUM : printer.print_generic("recording_detail", "uvm_verbosity", $bits(recording_detail), "UVM_MEDIUM"); UVM_HIGH : printer.print_generic("recording_detail", "uvm_verbosity", $bits(recording_detail), "UVM_HIGH"); UVM_FULL : printer.print_generic("recording_detail", "uvm_verbosity", $bits(recording_detail), "UVM_FULL"); default : printer.print_field_int("recording_detail", recording_detail, $bits(recording_detail), UVM_DEC, , "integral"); endcase endfunction function void uvm_component::set_local(uvm_resource_base rsrc) ; bit success; if((rsrc != null) && (rsrc.get_name() == "recording_detail")) begin begin begin uvm_resource#(uvm_integral_t) __tmp_rsrc__; success = $cast(__tmp_rsrc__, rsrc); if (success) begin recording_detail = __tmp_rsrc__.read(this); end end if (!success) begin uvm_resource#(uvm_bitstream_t) __tmp_rsrc__; success = $cast(__tmp_rsrc__, rsrc); if (success) begin recording_detail = __tmp_rsrc__.read(this); end end if (!success) begin uvm_resource#(int) __tmp_rsrc__; success = $cast(__tmp_rsrc__, rsrc); if (success) begin recording_detail = __tmp_rsrc__.read(this); end end if (!success) begin uvm_resource#(int unsigned) __tmp_rsrc__; success = $cast(__tmp_rsrc__, rsrc); if (success) begin recording_detail = __tmp_rsrc__.read(this); end end end end if (!success) super.set_local(rsrc); endfunction function void uvm_component::m_unsupported_set_local(uvm_resource_base rsrc); m_unsupported_resource_base = rsrc; endfunction typedef class uvm_cmdline_processor; function void uvm_component::m_set_cl_msg_args; string s_; process p_; p_=process::self(); if(p_!=null) s_=p_.get_randstate(); else begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"UVM")) uvm_report_warning ("UVM", "run_test() invoked from a non process context", UVM_NONE, "t/uvm/src/base/uvm_component.svh", 3043, "", 1); end m_set_cl_verb(); m_set_cl_action(); m_set_cl_sev(); if(p_!=null) p_.set_randstate(s_); endfunction function void uvm_component::m_set_cl_verb; static string values[$]; static bit first = 1; string args[$]; uvm_cmdline_processor clp = uvm_cmdline_processor::get_inst(); uvm_root top; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); top = cs.get_root(); if(first) begin string t[$]; m_verbosity_setting setting; void'(clp.get_arg_values("+uvm_set_verbosity=",values)); foreach(values[i]) begin args.delete(); uvm_split_string(values[i], ",", args); if(((args.size() == 4) || (args.size() == 5)) && (clp.m_convert_verb(args[2], setting.verbosity) == 1) ) t.push_back(values[i]); else uvm_report_warning("UVM/CMDLINE",$sformatf("argument %s not recognized and therefore dropped",values[i])); end values=t; first=0; end foreach(values[i]) begin m_verbosity_setting setting; args.delete(); uvm_split_string(values[i], ",", args); begin setting.comp = args[0]; setting.id = args[1]; void'(clp.m_convert_verb(args[2],setting.verbosity)); setting.phase = args[3]; setting.offset = 0; if(args.size() == 5) setting.offset = args[4].atoi(); if((setting.phase == "time") && (this == top)) begin m_time_settings.push_back(setting); end if (uvm_is_match(setting.comp, get_full_name()) ) begin if((setting.phase == "" || setting.phase == "build" || setting.phase == "time") && (setting.offset == 0) ) begin if(setting.id == "_ALL_") set_report_verbosity_level(setting.verbosity); else set_report_id_verbosity(setting.id, setting.verbosity); end else begin if(setting.phase != "time") begin m_verbosity_settings.push_back(setting); end end end end end if(this == top) begin fork begin time last_time = 0; if (m_time_settings.size() > 0) m_time_settings.sort() with ( item.offset ); foreach(m_time_settings[i]) begin uvm_component comps[$]; top.find_all(m_time_settings[i].comp,comps); #(m_time_settings[i].offset - last_time); last_time = m_time_settings[i].offset; if(m_time_settings[i].id == "_ALL_") begin foreach(comps[j]) begin comps[j].set_report_verbosity_level(m_time_settings[i].verbosity); end end else begin foreach(comps[j]) begin comps[j].set_report_id_verbosity(m_time_settings[i].id, m_time_settings[i].verbosity); end end end end join_none end endfunction function void uvm_component::m_set_cl_action; static bit initialized = 0; uvm_severity sev; uvm_action action; uvm_cmdline_processor uvm_cmdline_proc = uvm_cmdline_processor::get_inst(); if(!initialized) begin string values[$]; void'(uvm_cmdline_proc.get_arg_values("+uvm_set_action=",values)); foreach(values[idx]) begin uvm_cmdline_parsed_arg_t t; string args[$]; uvm_split_string(values[idx], ",", args); if(args.size() != 4) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"INVLCMDARGS")) uvm_report_warning ("INVLCMDARGS", $sformatf("+uvm_set_action requires 4 arguments, but %0d given for command +uvm_set_action=%s, Usage: +uvm_set_action=,,,", args.size(), values[idx]), UVM_NONE, "t/uvm/src/base/uvm_component.svh", 3169, "", 1); end continue; end if((args[2] != "_ALL_") && !uvm_string_to_severity(args[2], sev)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"INVLCMDARGS")) uvm_report_warning ("INVLCMDARGS", $sformatf("Bad severity argument \"%s\" given to command +uvm_set_action=%s, Usage: +uvm_set_action=,,,", args[2], values[idx]), UVM_NONE, "t/uvm/src/base/uvm_component.svh", 3173, "", 1); end continue; end if(!uvm_string_to_action(args[3], action)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"INVLCMDARGS")) uvm_report_warning ("INVLCMDARGS", $sformatf("Bad action argument \"%s\" given to command +uvm_set_action=%s, Usage: +uvm_set_action=,,,", args[3], values[idx]), UVM_NONE, "t/uvm/src/base/uvm_component.svh", 3177, "", 1); end continue; end t.args=args; t.arg=values[idx]; m_uvm_applied_cl_action.push_back(t); end initialized=1; end foreach(m_uvm_applied_cl_action[i]) begin string args[$] = m_uvm_applied_cl_action[i].args; if (!uvm_is_match(args[0], get_full_name()) ) continue; void'(uvm_string_to_severity(args[2], sev)); void'(uvm_string_to_action(args[3], action)); m_uvm_applied_cl_action[i].used++; if(args[1] == "_ALL_") begin if(args[2] == "_ALL_") begin set_report_severity_action(UVM_INFO, action); set_report_severity_action(UVM_WARNING, action); set_report_severity_action(UVM_ERROR, action); set_report_severity_action(UVM_FATAL, action); end else begin set_report_severity_action(sev, action); end end else begin if(args[2] == "_ALL_") begin set_report_id_action(args[1], action); end else begin set_report_severity_id_action(sev, args[1], action); end end end endfunction function void uvm_component::m_set_cl_sev; static bit initialized; uvm_severity orig_sev, sev; uvm_cmdline_processor uvm_cmdline_proc = uvm_cmdline_processor::get_inst(); if(!initialized) begin string values[$]; void'(uvm_cmdline_proc.get_arg_values("+uvm_set_severity=",values)); foreach(values[idx]) begin uvm_cmdline_parsed_arg_t t; string args[$]; uvm_split_string(values[idx], ",", args); if(args.size() != 4) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"INVLCMDARGS")) uvm_report_warning ("INVLCMDARGS", $sformatf("+uvm_set_severity requires 4 arguments, but %0d given for command +uvm_set_severity=%s, Usage: +uvm_set_severity=,,,", args.size(), values[idx]), UVM_NONE, "t/uvm/src/base/uvm_component.svh", 3240, "", 1); end continue; end if(args[2] != "_ALL_" && !uvm_string_to_severity(args[2], orig_sev)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"INVLCMDARGS")) uvm_report_warning ("INVLCMDARGS", $sformatf("Bad severity argument \"%s\" given to command +uvm_set_severity=%s, Usage: +uvm_set_severity=,,,", args[2], values[idx]), UVM_NONE, "t/uvm/src/base/uvm_component.svh", 3244, "", 1); end continue; end if(!uvm_string_to_severity(args[3], sev)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"INVLCMDARGS")) uvm_report_warning ("INVLCMDARGS", $sformatf("Bad severity argument \"%s\" given to command +uvm_set_severity=%s, Usage: +uvm_set_severity=,,,", args[3], values[idx]), UVM_NONE, "t/uvm/src/base/uvm_component.svh", 3248, "", 1); end continue; end t.args=args; t.arg=values[idx]; m_uvm_applied_cl_sev.push_back(t); end initialized=1; end foreach(m_uvm_applied_cl_sev[i]) begin string args[$]=m_uvm_applied_cl_sev[i].args; if (!uvm_is_match(args[0], get_full_name()) ) continue; void'(uvm_string_to_severity(args[2], orig_sev)); void'(uvm_string_to_severity(args[3], sev)); m_uvm_applied_cl_sev[i].used++; if(args[1] == "_ALL_" && args[2] == "_ALL_") begin set_report_severity_override(UVM_INFO,sev); set_report_severity_override(UVM_WARNING,sev); set_report_severity_override(UVM_ERROR,sev); set_report_severity_override(UVM_FATAL,sev); end else if(args[1] == "_ALL_") begin set_report_severity_override(orig_sev,sev); end else if(args[2] == "_ALL_") begin set_report_severity_id_override(UVM_INFO,args[1],sev); set_report_severity_id_override(UVM_WARNING,args[1],sev); set_report_severity_id_override(UVM_ERROR,args[1],sev); set_report_severity_id_override(UVM_FATAL,args[1],sev); end else begin set_report_severity_id_override(orig_sev,args[1],sev); end end endfunction function void uvm_component::m_apply_verbosity_settings(uvm_phase phase); int i; while (i < m_verbosity_settings.size()) begin if(phase.get_name() == m_verbosity_settings[i].phase) begin if( m_verbosity_settings[i].offset == 0 ) begin if(m_verbosity_settings[i].id == "_ALL_") set_report_verbosity_level(m_verbosity_settings[i].verbosity); else set_report_id_verbosity(m_verbosity_settings[i].id, m_verbosity_settings[i].verbosity); end else begin process p = process::self(); string p_rand = p.get_randstate(); fork begin m_verbosity_setting setting = m_verbosity_settings[i]; #setting.offset; if(setting.id == "_ALL_") set_report_verbosity_level(setting.verbosity); else set_report_id_verbosity(setting.id, setting.verbosity); end join_none p.set_randstate(p_rand); end m_verbosity_settings.delete(i); continue; end i++; end endfunction function void uvm_component::m_do_pre_abort; foreach(m_children[i]) m_children[i].m_do_pre_abort(); pre_abort(); endfunction `define UVM_OBJECTION_SVH typedef class uvm_objection_context_object; typedef class uvm_objection; typedef class uvm_sequence_base; typedef class uvm_objection_callback; typedef uvm_callbacks #(uvm_objection,uvm_objection_callback) uvm_objection_cbs_t; typedef class uvm_cmdline_processor; class uvm_objection_events; int waiters; event raised; event dropped; event all_dropped; endclass class uvm_objection extends uvm_report_object; static local bit m_register_cb_uvm_objection_callback = uvm_callbacks#(uvm_objection,uvm_objection_callback)::m_register_pair("uvm_objection","uvm_objection_callback"); protected bit m_trace_mode; protected int m_source_count[uvm_object]; protected int m_total_count [uvm_object]; protected time m_drain_time [uvm_object]; protected uvm_objection_events m_events [uvm_object]; bit m_top_all_dropped; protected uvm_root m_top; static uvm_objection m_objections[$]; local static uvm_objection_context_object m_context_pool[$]; local process m_drain_proc[uvm_object]; local static uvm_objection_context_object m_scheduled_list[$]; local uvm_objection_context_object m_scheduled_contexts[uvm_object]; local uvm_objection_context_object m_forked_list[$]; local uvm_objection_context_object m_forked_contexts[uvm_object]; protected bit m_prop_mode = 1; protected bit m_cleared; function new(string name=""); uvm_cmdline_processor clp; uvm_coreservice_t cs_ ; string trace_args[$]; super.new(name); cs_ = uvm_coreservice_t::get(); m_top = cs_.get_root(); set_report_verbosity_level(m_top.get_report_verbosity_level()); clp = uvm_cmdline_processor::get_inst(); if(clp.get_arg_matches("+UVM_OBJECTION_TRACE", trace_args)) begin m_trace_mode=1; end m_objections.push_back(this); endfunction function bit trace_mode (int mode=-1); trace_mode = m_trace_mode; if(mode == 0) m_trace_mode = 0; else if(mode == 1) m_trace_mode = 1; endfunction function void m_report(uvm_object obj, uvm_object source_obj, string description, int count, string action); int _count = m_source_count.exists(obj) ? m_source_count[obj] : 0; int _total = m_total_count.exists(obj) ? m_total_count[obj] : 0; if (!uvm_report_enabled(UVM_NONE,UVM_INFO,"OBJTN_TRC") || !m_trace_mode) return; if (source_obj == obj) uvm_report_info("OBJTN_TRC", $sformatf("Object %0s %0s %0d objection(s)%s: count=%0d total=%0d", obj.get_full_name()==""?"uvm_top":obj.get_full_name(), action, count, description != ""? {" (",description,")"}:"", _count, _total), UVM_NONE); else begin int cpath = 0, last_dot=0; string sname = source_obj.get_full_name(), nm = obj.get_full_name(); int max = sname.len() > nm.len() ? nm.len() : sname.len(); while((sname[cpath] == nm[cpath]) && (cpath < max)) begin if(sname[cpath] == ".") last_dot = cpath; cpath++; end if(last_dot) sname = sname.substr(last_dot+1, sname.len()); uvm_report_info("OBJTN_TRC", $sformatf("Object %0s %0s %0d objection(s) %0s its total (%s from source object %s%s): count=%0d total=%0d", obj.get_full_name()==""?"uvm_top":obj.get_full_name(), action=="raised"?"added":"subtracted", count, action=="raised"?"to":"from", action, sname, description != ""?{", ",description}:"", _count, _total), UVM_NONE); end endfunction function uvm_object m_get_parent(uvm_object obj); uvm_component comp; uvm_sequence_base seq; if ($cast(comp, obj)) begin obj = comp.get_parent(); end else if ($cast(seq, obj)) begin obj = seq.get_sequencer(); end else obj = m_top; if (obj == null) obj = m_top; return obj; endfunction function void m_propagate (uvm_object obj, uvm_object source_obj, string description, int count, bit raise, int in_top_thread); if (obj != null && obj != m_top) begin obj = m_get_parent(obj); if(raise) m_raise(obj, source_obj, description, count); else m_drop(obj, source_obj, description, count, in_top_thread); end endfunction function void set_propagate_mode (bit prop_mode); if (!m_top_all_dropped && (get_objection_total() != 0)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/BASE/OBJTN/PROP_MODE")) uvm_report_error ("UVM/BASE/OBJTN/PROP_MODE", {"The propagation mode of '", this.get_full_name(), "' cannot be changed while the objection is raised ", "or draining!"}, UVM_NONE, "t/uvm/src/base/uvm_objection.svh", 265, "", 1); end return; end m_prop_mode = prop_mode; endfunction : set_propagate_mode function bit get_propagate_mode(); return m_prop_mode; endfunction : get_propagate_mode virtual function void raise_objection (uvm_object obj=null, string description="", int count=1); if(obj == null) obj = m_top; m_cleared = 0; m_top_all_dropped = 0; m_raise (obj, obj, description, count); endfunction function void m_raise (uvm_object obj, uvm_object source_obj, string description="", int count=1); int idx; uvm_objection_context_object ctxt; if (count == 0) return; if (m_total_count.exists(obj)) m_total_count[obj] += count; else m_total_count[obj] = count; if (source_obj==obj) begin if (m_source_count.exists(obj)) m_source_count[obj] += count; else m_source_count[obj] = count; end if (m_trace_mode) m_report(obj,source_obj,description,count,"raised"); raised(obj, source_obj, description, count); idx = 0; while (idx < m_scheduled_list.size()) begin if ((m_scheduled_list[idx].obj == obj) && (m_scheduled_list[idx].objection == this)) begin ctxt = m_scheduled_list[idx]; m_scheduled_list.delete(idx); break; end idx++; end if (ctxt == null) begin idx = 0; while (idx < m_forked_list.size()) begin if (m_forked_list[idx].obj == obj) begin ctxt = m_forked_list[idx]; m_forked_list.delete(idx); m_scheduled_contexts.delete(ctxt.obj); break; end idx++; end end if (ctxt == null) begin if (m_forked_contexts.exists(obj)) begin ctxt = m_forked_contexts[obj]; m_forked_contexts.delete(obj); m_drain_proc[obj].kill(); m_drain_proc.delete(obj); end end if (ctxt == null) begin if (!m_prop_mode && obj != m_top) m_raise(m_top,source_obj,description,count); else if (obj != m_top) m_propagate(obj, source_obj, description, count, 1, 0); end else begin int diff_count; diff_count = count - ctxt.count; if (diff_count != 0) begin if (diff_count > 0) begin if (!m_prop_mode && obj != m_top) m_raise(m_top, source_obj, description, diff_count); else if (obj != m_top) m_propagate(obj, source_obj, description, diff_count, 1, 0); end else begin diff_count = -diff_count; if (!m_prop_mode && obj != m_top) m_drop(m_top, source_obj, description, diff_count); else if (obj != m_top) m_propagate(obj, source_obj, description, diff_count, 0, 0); end end ctxt.clear(); m_context_pool.push_back(ctxt); end endfunction virtual function void drop_objection (uvm_object obj=null, string description="", int count=1); if(obj == null) obj = m_top; m_drop (obj, obj, description, count, 0); endfunction function void m_drop (uvm_object obj, uvm_object source_obj, string description="", int count=1, int in_top_thread=0); if (count == 0) return; if (!m_total_count.exists(obj) || (count > m_total_count[obj])) begin if(m_cleared) return; uvm_report_fatal("OBJTN_ZERO", {"Object \"", obj.get_full_name(), "\" attempted to drop objection '",this.get_name(),"' count below zero"}); return; end if (obj == source_obj) begin if (!m_source_count.exists(obj) || (count > m_source_count[obj])) begin if(m_cleared) return; uvm_report_fatal("OBJTN_ZERO", {"Object \"", obj.get_full_name(), "\" attempted to drop objection '",this.get_name(),"' count below zero"}); return; end m_source_count[obj] -= count; end m_total_count[obj] -= count; if (m_trace_mode) m_report(obj,source_obj,description,count,"dropped"); dropped(obj, source_obj, description, count); if (m_total_count[obj] != 0) begin if (!m_prop_mode && obj != m_top) m_drop(m_top,source_obj,description, count, in_top_thread); else if (obj != m_top) begin this.m_propagate(obj, source_obj, description, count, 0, in_top_thread); end end else begin uvm_objection_context_object ctxt; if (m_context_pool.size()) ctxt = m_context_pool.pop_front(); else ctxt = new; ctxt.obj = obj; ctxt.source_obj = source_obj; ctxt.description = description; ctxt.count = count; ctxt.objection = this; m_scheduled_list.push_back(ctxt); end endfunction virtual function void clear(uvm_object obj=null); string name; int idx; if (obj==null) obj=m_top; name = obj.get_full_name(); if (name == "") name = "uvm_top"; else name = obj.get_full_name(); if (!m_top_all_dropped && get_objection_total(m_top)) uvm_report_warning("OBJTN_CLEAR",{"Object '",name, "' cleared objection counts for ",get_name()}); m_source_count.delete(); m_total_count.delete(); idx = 0; while (idx < m_scheduled_list.size()) begin if (m_scheduled_list[idx].objection == this) begin m_scheduled_list[idx].clear(); m_context_pool.push_back(m_scheduled_list[idx]); m_scheduled_list.delete(idx); end else begin idx++; end end m_scheduled_contexts.delete(); while (m_forked_list.size()) begin m_forked_list[0].clear(); m_context_pool.push_back(m_forked_list[0]); void'(m_forked_list.pop_front()); end foreach (m_forked_contexts[o]) begin m_drain_proc[o].kill(); m_drain_proc.delete(o); m_forked_contexts[o].clear(); m_context_pool.push_back(m_forked_contexts[o]); m_forked_contexts.delete(o); end m_top_all_dropped = 0; m_cleared = 1; if (m_events.exists(m_top)) ->m_events[m_top].all_dropped; endfunction static task m_execute_scheduled_forks(); while(1) begin wait(m_scheduled_list.size() != 0); if(m_scheduled_list.size() != 0) begin uvm_objection_context_object c; c = m_scheduled_list.pop_front(); c.objection.m_scheduled_contexts[c.obj] = c; c.objection.m_forked_list.push_back(c); fork : guard automatic uvm_objection objection = c.objection; begin if (objection.m_forked_list.size() > 0) begin uvm_objection_context_object ctxt; ctxt = objection.m_forked_list.pop_front(); objection.m_scheduled_contexts.delete(ctxt.obj); objection.m_forked_contexts[ctxt.obj] = ctxt; objection.m_drain_proc[ctxt.obj] = process::self(); objection.m_forked_drain(ctxt.obj, ctxt.source_obj, ctxt.description, ctxt.count, 1); objection.m_drain_proc.delete(ctxt.obj); objection.m_forked_contexts.delete(ctxt.obj); ctxt.clear(); m_context_pool.push_back(ctxt); end end join_none : guard end end endtask task m_forked_drain (uvm_object obj, uvm_object source_obj, string description="", int count=1, int in_top_thread=0); if (m_drain_time.exists(obj)) #(m_drain_time[obj]); if (m_trace_mode) m_report(obj,source_obj,description,count,"all_dropped"); all_dropped(obj,source_obj,description, count); wait fork; if (m_source_count.exists(obj) && m_source_count[obj] == 0) m_source_count.delete(obj); if (m_total_count.exists(obj) && m_total_count[obj] == 0) m_total_count.delete(obj); if (!m_prop_mode && obj != m_top) m_drop(m_top,source_obj,description, count, 1); else if (obj != m_top) m_propagate(obj, source_obj, description, count, 0, 1); endtask static function void m_init_objections(); fork uvm_objection::m_execute_scheduled_forks(); join_none endfunction function void set_drain_time (uvm_object obj=null, time drain); if (obj==null) obj = m_top; m_drain_time[obj] = drain; endfunction virtual function void raised (uvm_object obj, uvm_object source_obj, string description, int count); uvm_component comp; if ($cast(comp,obj)) comp.raised(this, source_obj, description, count); begin uvm_callback_iter#(uvm_objection,uvm_objection_callback) iter = new(this); uvm_objection_callback cb = iter.first(); while(cb != null) begin cb.raised(this,obj,source_obj,description,count); cb = iter.next(); end end if (m_events.exists(obj)) ->m_events[obj].raised; endfunction virtual function void dropped (uvm_object obj, uvm_object source_obj, string description, int count); uvm_component comp; if($cast(comp,obj)) comp.dropped(this, source_obj, description, count); begin uvm_callback_iter#(uvm_objection,uvm_objection_callback) iter = new(this); uvm_objection_callback cb = iter.first(); while(cb != null) begin cb.dropped(this,obj,source_obj,description,count); cb = iter.next(); end end if (m_events.exists(obj)) ->m_events[obj].dropped; endfunction virtual task all_dropped (uvm_object obj, uvm_object source_obj, string description, int count); uvm_component comp; if($cast(comp,obj)) comp.all_dropped(this, source_obj, description, count); begin uvm_callback_iter#(uvm_objection,uvm_objection_callback) iter = new(this); uvm_objection_callback cb = iter.first(); while(cb != null) begin cb.all_dropped(this,obj,source_obj,description,count); cb = iter.next(); end end if (m_events.exists(obj)) ->m_events[obj].all_dropped; if (obj == m_top) m_top_all_dropped = 1; endtask function void get_objectors(ref uvm_object list[$]); list.delete(); foreach (m_source_count[obj]) list.push_back(obj); endfunction task wait_for(uvm_objection_event objt_event, uvm_object obj=null); if (obj==null) obj = m_top; if (!m_events.exists(obj)) begin m_events[obj] = new; end m_events[obj].waiters++; case (objt_event) UVM_RAISED: @(m_events[obj].raised); UVM_DROPPED: @(m_events[obj].dropped); UVM_ALL_DROPPED: @(m_events[obj].all_dropped); endcase m_events[obj].waiters--; if (m_events[obj].waiters == 0) m_events.delete(obj); endtask task wait_for_total_count(uvm_object obj=null, int count=0); if (obj==null) obj = m_top; if(!m_total_count.exists(obj) && count == 0) return; if (count == 0) wait (!m_total_count.exists(obj) && count == 0); else wait (m_total_count.exists(obj) && m_total_count[obj] == count); endtask function int get_objection_count (uvm_object obj=null); if (obj==null) obj = m_top; if (!m_source_count.exists(obj)) return 0; return m_source_count[obj]; endfunction function int get_objection_total (uvm_object obj=null); if (obj==null) obj = m_top; if (!m_total_count.exists(obj)) return 0; else return m_total_count[obj]; endfunction function time get_drain_time (uvm_object obj=null); if (obj==null) obj = m_top; if (!m_drain_time.exists(obj)) return 0; return m_drain_time[obj]; endfunction protected function string m_display_objections(uvm_object obj=null, bit show_header=1); static string blank=" "; string s; int total; uvm_object list[string]; uvm_object curr_obj; int depth; string name; string this_obj_name; string curr_obj_name; foreach (m_total_count[o]) begin uvm_object theobj = o; if ( m_total_count[o] > 0) list[theobj.get_full_name()] = theobj; end if (obj==null) obj = m_top; total = get_objection_total(obj); s = $sformatf("The total objection count is %0d\n",total); if (total == 0) return s; s = {s,"---------------------------------------------------------\n"}; s = {s,"Source Total \n"}; s = {s,"Count Count Object\n"}; s = {s,"---------------------------------------------------------\n"}; this_obj_name = obj.get_full_name(); curr_obj_name = this_obj_name; do begin curr_obj = list[curr_obj_name]; depth=0; foreach (curr_obj_name[i]) if (curr_obj_name[i] == ".") depth++; name = curr_obj_name; for (int i=curr_obj_name.len()-1;i >= 0; i--) if (curr_obj_name[i] == ".") begin name = curr_obj_name.substr(i+1,curr_obj_name.len()-1); break; end if (curr_obj_name == "") name = "uvm_top"; else depth++; s = {s, $sformatf("%-6d %-6d %s%s\n", m_source_count.exists(curr_obj) ? m_source_count[curr_obj] : 0, m_total_count.exists(curr_obj) ? m_total_count[curr_obj] : 0, blank.substr(0,2*depth), name)}; end while (list.next(curr_obj_name) && curr_obj_name.substr(0,this_obj_name.len()-1) == this_obj_name); s = {s,"---------------------------------------------------------\n"}; return s; endfunction function string convert2string(); return m_display_objections(m_top,1); endfunction function void display_objections(uvm_object obj=null, bit show_header=1); string m = m_display_objections(obj,show_header); begin if (uvm_report_enabled(UVM_NONE,UVM_INFO,"UVM/OBJ/DISPLAY")) uvm_report_info ("UVM/OBJ/DISPLAY", m, UVM_NONE, "t/uvm/src/base/uvm_objection.svh", 1033, "", 1); end endfunction typedef uvm_object_registry#(uvm_objection,"uvm_objection") type_id; static function type_id get_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_objection tmp = new(name); return tmp; endfunction virtual function string get_type_name (); return "uvm_objection"; endfunction function void do_copy (uvm_object rhs); uvm_objection _rhs; $cast(_rhs, rhs); m_source_count = _rhs.m_source_count; m_total_count = _rhs.m_total_count; m_drain_time = _rhs.m_drain_time; m_prop_mode = _rhs.m_prop_mode; endfunction endclass typedef class uvm_cmdline_processor; class uvm_objection_context_object; uvm_object obj; uvm_object source_obj; string description; int count; uvm_objection objection; function void clear(); obj = null; source_obj = null; description = ""; count = 0; objection = null; endfunction : clear endclass typedef uvm_objection uvm_callbacks_objection; class uvm_objection_callback extends uvm_callback; function new(string name); super.new(name); endfunction virtual function void raised (uvm_objection objection, uvm_object obj, uvm_object source_obj, string description, int count); endfunction virtual function void dropped (uvm_objection objection, uvm_object obj, uvm_object source_obj, string description, int count); endfunction virtual task all_dropped (uvm_objection objection, uvm_object obj, uvm_object source_obj, string description, int count); endtask endclass `define UVM_HEARTBEAT_SVH typedef enum { UVM_ALL_ACTIVE, UVM_ONE_ACTIVE, UVM_ANY_ACTIVE, UVM_NO_HB_MODE } uvm_heartbeat_modes; typedef class uvm_heartbeat_callback; typedef uvm_callbacks #(uvm_objection,uvm_heartbeat_callback) uvm_heartbeat_cbs_t ; typedef class uvm_objection_callback; class uvm_heartbeat extends uvm_object; protected uvm_objection m_objection; protected uvm_heartbeat_callback m_cb; protected uvm_component m_cntxt; protected uvm_heartbeat_modes m_mode; protected uvm_component m_hblist[$]; protected uvm_event#(uvm_object) m_event; protected bit m_started; protected event m_stop_event; function new(string name, uvm_component cntxt, uvm_objection objection=null); uvm_coreservice_t cs; super.new(name); m_objection = objection; cs = uvm_coreservice_t::get(); if(cntxt != null) m_cntxt = cntxt; else m_cntxt = cs.get_root(); m_cb = new({name,"_cb"},m_cntxt); endfunction function uvm_heartbeat_modes set_mode (uvm_heartbeat_modes mode = UVM_NO_HB_MODE); set_mode = m_mode; if(mode == UVM_ANY_ACTIVE || mode == UVM_ONE_ACTIVE || mode == UVM_ALL_ACTIVE) m_mode = mode; endfunction function void set_heartbeat (uvm_event#(uvm_object) e, ref uvm_component comps[$]); uvm_object c; foreach(comps[i]) begin c = comps[i]; if(!m_cb.cnt.exists(c)) m_cb.cnt[c]=0; if(!m_cb.last_trigger.exists(c)) m_cb.last_trigger[c]=0; end if(e==null && m_event==null) return; start(e); endfunction function void add (uvm_component comp); uvm_object c = comp; if(m_cb.cnt.exists(c)) return; m_cb.cnt[c]=0; m_cb.last_trigger[c]=0; endfunction function void remove (uvm_component comp); uvm_object c = comp; if(m_cb.cnt.exists(c)) m_cb.cnt.delete(c); if(m_cb.last_trigger.exists(c)) m_cb.last_trigger.delete(c); endfunction function void start (uvm_event#(uvm_object) e=null); if(m_event == null && e == null) begin m_cntxt.uvm_report_warning("NOEVNT", { "start() was called for: ", get_name(), " with a null trigger and no currently set trigger" }, UVM_NONE); return; end if((m_event != null) && (e != m_event) && m_started) begin m_cntxt.uvm_report_error("ILHBVNT", { "start() was called for: ", get_name(), " with trigger ", e.get_name(), " which is different ", "from the original trigger ", m_event.get_name() }, UVM_NONE); return; end if(e != null) m_event = e; m_enable_cb(); m_start_hb_process(); endfunction function void stop (); m_started = 0; ->m_stop_event; m_disable_cb(); endfunction function void m_start_hb_process(); if(m_started) return; m_started = 1; fork m_hb_process; join_none endfunction protected bit m_added; function void m_enable_cb; void'(m_cb.callback_mode(1)); if(m_objection == null) return; if(!m_added) uvm_heartbeat_cbs_t::add(m_objection, m_cb); m_added = 1; endfunction function void m_disable_cb; void'(m_cb.callback_mode(0)); endfunction task m_hb_process; uvm_object obj; bit triggered; time last_trigger=0; fork begin while(1) begin m_event.wait_trigger(); if(triggered) begin case (m_mode) UVM_ALL_ACTIVE: begin foreach(m_cb.cnt[idx]) begin obj = idx; if(!m_cb.cnt[obj]) begin m_cntxt.uvm_report_fatal("HBFAIL", $sformatf("Did not recieve an update of %s for component %s since last event trigger at time %0t : last update time was %0t", m_objection.get_name(), obj.get_full_name(), last_trigger, m_cb.last_trigger[obj]), UVM_NONE); end end end UVM_ANY_ACTIVE: begin if(m_cb.cnt.num() && !m_cb.objects_triggered()) begin string s; foreach(m_cb.cnt[idx]) begin obj = idx; s={s,"\n ",obj.get_full_name()}; end m_cntxt.uvm_report_fatal("HBFAIL", $sformatf("Did not recieve an update of %s on any component since last event trigger at time %0t. The list of registered components is:%s", m_objection.get_name(), last_trigger, s), UVM_NONE); end end UVM_ONE_ACTIVE: begin if(m_cb.objects_triggered() > 1) begin string s; foreach(m_cb.cnt[idx]) begin obj = idx; if(m_cb.cnt[obj]) $swrite(s,"%s\n %s (updated: %0t)", s, obj.get_full_name(), m_cb.last_trigger[obj]); end m_cntxt.uvm_report_fatal("HBFAIL", $sformatf("Recieved update of %s from more than one component since last event trigger at time %0t. The list of triggered components is:%s", m_objection.get_name(), last_trigger, s), UVM_NONE); end if(m_cb.cnt.num() && !m_cb.objects_triggered()) begin string s; foreach(m_cb.cnt[idx]) begin obj = idx; s={s,"\n ",obj.get_full_name()}; end m_cntxt.uvm_report_fatal("HBFAIL", $sformatf("Did not recieve an update of %s on any component since last event trigger at time %0t. The list of registered components is:%s", m_objection.get_name(), last_trigger, s), UVM_NONE); end end endcase end m_cb.reset_counts(); last_trigger = $realtime; triggered = 1; end end @(m_stop_event); join_any disable fork; endtask endclass class uvm_heartbeat_callback extends uvm_objection_callback; int cnt [uvm_object]; time last_trigger [uvm_object]; uvm_object target; uvm_coreservice_t cs = uvm_coreservice_t::get(); function new(string name, uvm_object target); super.new(name); if (target != null) this.target = target; else this.target = cs.get_root(); endfunction virtual function void raised (uvm_objection objection, uvm_object obj, uvm_object source_obj, string description, int count); if(obj == target) begin if(!cnt.exists(source_obj)) cnt[source_obj] = 0; cnt[source_obj] = cnt[source_obj]+1; last_trigger[source_obj] = $realtime; end endfunction virtual function void dropped (uvm_objection objection, uvm_object obj, uvm_object source_obj, string description, int count); raised(objection,obj,source_obj,description,count); endfunction function void reset_counts; foreach(cnt[i]) cnt[i] = 0; endfunction function int objects_triggered; objects_triggered = 0; foreach(cnt[i]) if (cnt[i] != 0) objects_triggered++; endfunction endclass class uvm_cmd_line_verb; string comp_path; string id; uvm_verbosity verb; int exec_time; endclass typedef class uvm_cmdline_processor; uvm_cmdline_processor uvm_cmdline_proc; class uvm_cmdline_processor extends uvm_report_object; static local uvm_cmdline_processor m_inst; static function uvm_cmdline_processor get_inst(); if(m_inst == null) m_inst = new("uvm_cmdline_proc"); uvm_cmdline_proc = m_inst; return m_inst; endfunction protected string m_argv[$]; protected string m_plus_argv[$]; protected string m_uvm_argv[$]; function void get_args (output string args[$]); args = m_argv; endfunction function void get_plusargs (output string args[$]); args = m_plus_argv; endfunction function void get_uvm_args (output string args[$]); args = m_uvm_argv; endfunction function int get_arg_matches (string match, ref string args[$]); bit match_is_regex = (match.len() > 2) && (match[0] == "/") && (match[match.len()-1] == "/"); int len = match.len(); args.delete(); foreach (m_argv[i]) begin if ( match_is_regex && uvm_is_match( match, m_argv[i] ) ) begin args.push_back( m_argv[i] ); end else if((m_argv[i].len() >= len) && (m_argv[i].substr(0,len - 1) == match)) begin args.push_back(m_argv[i]); end end return args.size(); endfunction function int get_arg_value (string match, ref string value); int chars = match.len(); get_arg_value = 0; foreach (m_argv[i]) begin if(m_argv[i].len() >= chars) begin if(m_argv[i].substr(0,chars-1) == match) begin get_arg_value++; if(get_arg_value == 1) value = m_argv[i].substr(chars,m_argv[i].len()-1); end end end endfunction function int get_arg_values (string match, ref string values[$]); int chars = match.len(); values.delete(); foreach (m_argv[i]) begin if(m_argv[i].len() >= chars) begin if(m_argv[i].substr(0,chars-1) == match) values.push_back(m_argv[i].substr(chars,m_argv[i].len()-1)); end end return values.size(); endfunction function string get_tool_name (); return uvm_dpi_get_tool_name(); endfunction function string get_tool_version (); return uvm_dpi_get_tool_version(); endfunction function new(string name = ""); string s; string sub; int doInit=1; super.new(name); do begin s = uvm_dpi_get_next_arg(doInit); doInit=0; if(s!="") begin m_argv.push_back(s); if(s[0] == "+") begin m_plus_argv.push_back(s); end if(s.len() >= 4 && (s[0]=="-" || s[0]=="+")) begin sub = s.substr(1,3); sub = sub.toupper(); if(sub == "UVM") m_uvm_argv.push_back(s); end end end while(s!=""); endfunction function bit m_convert_verb(string verb_str, output uvm_verbosity verb_enum); case (verb_str) "NONE" : begin verb_enum = UVM_NONE; return 1; end "UVM_NONE" : begin verb_enum = UVM_NONE; return 1; end "LOW" : begin verb_enum = UVM_LOW; return 1; end "UVM_LOW" : begin verb_enum = UVM_LOW; return 1; end "MEDIUM" : begin verb_enum = UVM_MEDIUM; return 1; end "UVM_MEDIUM" : begin verb_enum = UVM_MEDIUM; return 1; end "HIGH" : begin verb_enum = UVM_HIGH; return 1; end "UVM_HIGH" : begin verb_enum = UVM_HIGH; return 1; end "FULL" : begin verb_enum = UVM_FULL; return 1; end "UVM_FULL" : begin verb_enum = UVM_FULL; return 1; end "DEBUG" : begin verb_enum = UVM_DEBUG; return 1; end "UVM_DEBUG" : begin verb_enum = UVM_DEBUG; return 1; end default : begin return 0; end endcase endfunction endclass virtual class uvm_visitor#(type NODE=uvm_component) extends uvm_object; function new (string name = ""); super.new(name); endfunction virtual function void begin_v(); endfunction virtual function void end_v(); endfunction pure virtual function void visit(NODE node); endclass virtual class uvm_structure_proxy#(type STRUCTURE=uvm_component) extends uvm_object; function new (string name = ""); super.new(name); endfunction pure virtual function void get_immediate_children(STRUCTURE s, ref STRUCTURE children[$]); endclass virtual class uvm_visitor_adapter#(type STRUCTURE=uvm_component,VISITOR=uvm_visitor#(STRUCTURE)) extends uvm_object; pure virtual function void accept(STRUCTURE s, VISITOR v,uvm_structure_proxy#(STRUCTURE) p, bit invoke_begin_end=1); function new (string name = ""); super.new(name); endfunction endclass class uvm_top_down_visitor_adapter#(type STRUCTURE=uvm_component,VISITOR=uvm_visitor#(STRUCTURE)) extends uvm_visitor_adapter#(STRUCTURE,VISITOR); function new (string name = ""); super.new(name); endfunction virtual function void accept(STRUCTURE s, VISITOR v,uvm_structure_proxy#(STRUCTURE) p, bit invoke_begin_end=1); STRUCTURE c[$]; if(invoke_begin_end) v.begin_v(); v.visit(s); p.get_immediate_children(s, c); foreach(c[idx]) accept(c[idx],v,p,0); if(invoke_begin_end) v.end_v(); endfunction endclass class uvm_bottom_up_visitor_adapter#(type STRUCTURE=uvm_component,VISITOR=uvm_visitor#(STRUCTURE)) extends uvm_visitor_adapter#(STRUCTURE,VISITOR); function new (string name = ""); super.new(name); endfunction virtual function void accept(STRUCTURE s, VISITOR v,uvm_structure_proxy#(STRUCTURE) p, bit invoke_begin_end=1); STRUCTURE c[$]; if(invoke_begin_end) v.begin_v(); p.get_immediate_children(s, c); foreach(c[idx]) accept(c[idx],v,p,0); v.visit(s); if(invoke_begin_end) v.end_v(); endfunction endclass class uvm_by_level_visitor_adapter#(type STRUCTURE=uvm_component,VISITOR=uvm_visitor#(STRUCTURE)) extends uvm_visitor_adapter#(STRUCTURE,VISITOR); function new (string name = ""); super.new(name); endfunction virtual function void accept(STRUCTURE s, VISITOR v,uvm_structure_proxy#(STRUCTURE) p, bit invoke_begin_end=1); STRUCTURE c[$]; c.push_back(s); if(invoke_begin_end) v.begin_v(); while(c.size() > 0) begin STRUCTURE q[$]; foreach(c[idx]) begin STRUCTURE t[$]; v.visit(c[idx]); p.get_immediate_children(c[idx], t); q = {q,t}; end c=q; end if(invoke_begin_end) v.end_v(); endfunction endclass class uvm_component_proxy extends uvm_structure_proxy#(uvm_component); virtual function void get_immediate_children(STRUCTURE s, ref STRUCTURE children[$]); s.get_children(children); endfunction function new (string name = ""); super.new(name); endfunction endclass class uvm_component_name_check_visitor extends uvm_visitor#(uvm_component); local uvm_root _root; virtual function string get_name_constraint(); return "/^[][[:alnum:](){}_:-]([][[:alnum:](){} _:-]*[][[:alnum:](){}_:-])?$/"; endfunction virtual function void visit(NODE node); if(_root != node) begin if ( ! uvm_is_match( get_name_constraint(), node.get_name() ) ) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"UVM/COMP/NAME")) uvm_report_warning ("UVM/COMP/NAME", $sformatf("the name \"%s\" of the component \"%s\" violates the uvm component name constraints",node.get_name(),node.get_full_name()), UVM_NONE, "t/uvm/src/base/uvm_traversal.svh", 274, "", 1); end end end endfunction function new (string name = ""); super.new(name); endfunction virtual function void begin_v(); uvm_coreservice_t cs = uvm_coreservice_t::get(); _root = cs.get_root(); begin if (uvm_report_enabled(UVM_NONE,UVM_INFO,"UVM/COMP/NAMECHECK")) uvm_report_info ("UVM/COMP/NAMECHECK", "This implementation of the component name checks requires DPI to be enabled", UVM_NONE, "t/uvm/src/base/uvm_traversal.svh", 289, "", 1); end endfunction endclass `define UVM_DAP_SVH virtual class uvm_set_get_dap_base#(type T=int) extends uvm_object; typedef uvm_set_get_dap_base#(T) this_type; function new(string name="unnamed-uvm_set_get_dap_base#(T)"); super.new(name); endfunction : new pure virtual function void set(T value); pure virtual function bit try_set(T value); pure virtual function T get(); pure virtual function bit try_get(output T value); endclass : uvm_set_get_dap_base class uvm_simple_lock_dap#(type T=int) extends uvm_set_get_dap_base#(T); typedef uvm_simple_lock_dap#(T) this_type; typedef uvm_object_registry #(uvm_simple_lock_dap#(T)) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_simple_lock_dap#(T) tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction local T m_value; local bit m_locked; function new(string name="unnamed-uvm_simple_lock_dap#(T)"); super.new(name); m_locked = 0; endfunction : new virtual function void set(T value); if (m_locked) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/SIMPLE_LOCK_DAP/SAG")) uvm_report_error ("UVM/SIMPLE_LOCK_DAP/SAG", $sformatf("Attempt to set new value on '%s', but the data access policy forbids setting while locked!", get_full_name()), UVM_NONE, "t/uvm/src/dap/uvm_simple_lock_dap.svh", 68, "", 1); end else begin m_value = value; end endfunction : set virtual function bit try_set(T value); if (m_locked) return 0; else begin m_value = value; return 1; end endfunction : try_set virtual function T get(); return m_value; endfunction : get virtual function bit try_get(output T value); value = get(); return 1; endfunction : try_get function void lock(); m_locked = 1; endfunction : lock function void unlock(); m_locked = 0; endfunction : unlock function bit is_locked(); return m_locked; endfunction : is_locked virtual function void do_copy(uvm_object rhs); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/SIMPLE_LOCK_DAP/CPY")) uvm_report_error ("UVM/SIMPLE_LOCK_DAP/CPY", "'copy()' is not supported for 'uvm_simple_lock_dap#(T)'", UVM_NONE, "t/uvm/src/dap/uvm_simple_lock_dap.svh", 144, "", 1); end endfunction : do_copy virtual function void do_pack(uvm_packer packer); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/SIMPLE_LOCK_DAP/PCK")) uvm_report_error ("UVM/SIMPLE_LOCK_DAP/PCK", "'pack()' is not supported for 'uvm_simple_lock_dap#(T)'", UVM_NONE, "t/uvm/src/dap/uvm_simple_lock_dap.svh", 149, "", 1); end endfunction : do_pack virtual function void do_unpack(uvm_packer packer); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/SIMPLE_LOCK_DAP/UPK")) uvm_report_error ("UVM/SIMPLE_LOCK_DAP/UPK", "'unpack()' is not supported for 'uvm_simple_lock_dap#(T)'", UVM_NONE, "t/uvm/src/dap/uvm_simple_lock_dap.svh", 154, "", 1); end endfunction : do_unpack virtual function string convert2string(); if (m_locked) return $sformatf("(%s) %0p [LOCKED]", $typename(m_value), m_value); else return $sformatf("(%s) %0p [UNLOCKED]", $typename(m_value), m_value); endfunction : convert2string virtual function void do_print(uvm_printer printer); super.do_print(printer); printer.print_field("lock_state", m_locked, $bits(m_locked)); printer.print_generic("value", $typename(m_value), 0, $sformatf("%0p", m_value)); endfunction : do_print endclass class uvm_get_to_lock_dap#(type T=int) extends uvm_set_get_dap_base#(T); typedef uvm_get_to_lock_dap#(T) this_type; typedef uvm_object_registry #(uvm_get_to_lock_dap#(T)) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_get_to_lock_dap#(T) tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction local T m_value; local bit m_locked; function new(string name="unnamed-uvm_get_to_lock_dap#(T)"); super.new(name); m_locked = 0; endfunction : new virtual function void set(T value); if (m_locked) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/GET_TO_LOCK_DAP/SAG")) uvm_report_error ("UVM/GET_TO_LOCK_DAP/SAG", $sformatf("Attempt to set new value on '%s', but the data access policy forbids setting after a get!", get_full_name()), UVM_NONE, "t/uvm/src/dap/uvm_get_to_lock_dap.svh", 67, "", 1); end else begin m_value = value; end endfunction : set virtual function bit try_set(T value); if (m_locked) return 0; else begin m_value = value; return 1; end endfunction : try_set virtual function T get(); m_locked = 1; return m_value; endfunction : get virtual function bit try_get(output T value); value = get(); return 1; endfunction : try_get virtual function void do_copy(uvm_object rhs); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/GET_TO_LOCK_DAP/CPY")) uvm_report_error ("UVM/GET_TO_LOCK_DAP/CPY", "'copy()' is not supported for 'uvm_get_to_lock_dap#(T)'", UVM_NONE, "t/uvm/src/dap/uvm_get_to_lock_dap.svh", 119, "", 1); end endfunction : do_copy virtual function void do_pack(uvm_packer packer); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/GET_TO_LOCK_DAP/PCK")) uvm_report_error ("UVM/GET_TO_LOCK_DAP/PCK", "'pack()' is not supported for 'uvm_get_to_lock_dap#(T)'", UVM_NONE, "t/uvm/src/dap/uvm_get_to_lock_dap.svh", 124, "", 1); end endfunction : do_pack virtual function void do_unpack(uvm_packer packer); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/GET_TO_LOCK_DAP/UPK")) uvm_report_error ("UVM/GET_TO_LOCK_DAP/UPK", "'unpack()' is not supported for 'uvm_get_to_lock_dap#(T)'", UVM_NONE, "t/uvm/src/dap/uvm_get_to_lock_dap.svh", 129, "", 1); end endfunction : do_unpack virtual function string convert2string(); if (m_locked) return $sformatf("(%s) %0p [LOCKED]", $typename(m_value), m_value); else return $sformatf("(%s) %0p [UNLOCKED]", $typename(m_value), m_value); endfunction : convert2string virtual function void do_print(uvm_printer printer); super.do_print(printer); printer.print_field_int("lock_state", m_locked, $bits(m_locked)); printer.print_generic("value", $typename(m_value), 0, $sformatf("%0p", m_value)); endfunction : do_print endclass class uvm_set_before_get_dap#(type T=int) extends uvm_set_get_dap_base#(T); typedef uvm_set_before_get_dap#(T) this_type; typedef uvm_object_registry #(uvm_set_before_get_dap#(T)) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_set_before_get_dap#(T) tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction local T m_value; local bit m_set; function new(string name="unnamed-uvm_set_before_get_dap#(T)"); super.new(name); m_set = 0; endfunction : new virtual function void set(T value); m_set = 1; m_value = value; endfunction : set virtual function bit try_set(T value); set(value); return 1; endfunction : try_set virtual function T get(); if (!m_set) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/SET_BEFORE_GET_DAP/NO_SET")) uvm_report_error ("UVM/SET_BEFORE_GET_DAP/NO_SET", $sformatf("Attempt to get value on '%s', but the data access policy forbits calling 'get' prior to calling 'set' or 'try_set'!", get_full_name()), UVM_NONE, "t/uvm/src/dap/uvm_set_before_get_dap.svh", 117, "", 1); end end return m_value; endfunction : get virtual function bit try_get(output T value); if (!m_set) begin return 0; end else begin value = m_value; return 1; end endfunction : try_get virtual function void do_copy(uvm_object rhs); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/SET_BEFORE_GET_DAP/CPY")) uvm_report_error ("UVM/SET_BEFORE_GET_DAP/CPY", "'copy()' is not supported for 'uvm_set_before_get_dap#(T)'", UVM_NONE, "t/uvm/src/dap/uvm_set_before_get_dap.svh", 149, "", 1); end endfunction : do_copy virtual function void do_pack(uvm_packer packer); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/SET_BEFORE_GET_DAP/PCK")) uvm_report_error ("UVM/SET_BEFORE_GET_DAP/PCK", "'pack()' is not supported for 'uvm_set_before_get_dap#(T)'", UVM_NONE, "t/uvm/src/dap/uvm_set_before_get_dap.svh", 154, "", 1); end endfunction : do_pack virtual function void do_unpack(uvm_packer packer); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/SET_BEFORE_GET_DAP/UPK")) uvm_report_error ("UVM/SET_BEFORE_GET_DAP/UPK", "'unpack()' is not supported for 'uvm_set_before_get_dap#(T)'", UVM_NONE, "t/uvm/src/dap/uvm_set_before_get_dap.svh", 159, "", 1); end endfunction : do_unpack virtual function string convert2string(); if (m_set) return $sformatf("(%s) %0p [SET]", $typename(m_value), m_value); else return $sformatf("(%s) %0p [UNSET]", $typename(m_value), m_value); endfunction : convert2string virtual function void do_print(uvm_printer printer); super.do_print(printer); printer.print_field_int("set_state", m_set, $bits(m_set)); printer.print_generic("value", $typename(m_value), 0, $sformatf("%0p", m_value)); endfunction : do_print endclass `define UVM_TASK_ERROR "UVM TLM interface task not implemented" `define UVM_FUNCTION_ERROR "UVM TLM interface function not implemented" virtual class uvm_tlm_if_base #(type T1=int, type T2=int); virtual task put( input T1 t ); uvm_report_error("put", "UVM TLM interface task not implemented", UVM_NONE); endtask virtual task get( output T2 t ); uvm_report_error("get", "UVM TLM interface task not implemented", UVM_NONE); endtask virtual task peek( output T2 t ); uvm_report_error("peek", "UVM TLM interface task not implemented", UVM_NONE); endtask virtual function bit try_put( input T1 t ); uvm_report_error("try_put", "UVM TLM interface function not implemented", UVM_NONE); return 0; endfunction virtual function bit can_put(); uvm_report_error("can_put", "UVM TLM interface function not implemented", UVM_NONE); return 0; endfunction virtual function bit try_get( output T2 t ); uvm_report_error("try_get", "UVM TLM interface function not implemented", UVM_NONE); return 0; endfunction virtual function bit can_get(); uvm_report_error("can_get", "UVM TLM interface function not implemented", UVM_NONE); return 0; endfunction virtual function bit try_peek( output T2 t ); uvm_report_error("try_peek", "UVM TLM interface function not implemented", UVM_NONE); return 0; endfunction virtual function bit can_peek(); uvm_report_error("can_ppeek", "UVM TLM interface function not implemented", UVM_NONE); return 0; endfunction virtual task transport( input T1 req , output T2 rsp ); uvm_report_error("transport", "UVM TLM interface task not implemented", UVM_NONE); endtask virtual function bit nb_transport(input T1 req, output T2 rsp); uvm_report_error("nb_transport", "UVM TLM interface function not implemented", UVM_NONE); return 0; endfunction virtual function void write( input T1 t ); uvm_report_error("write", "UVM TLM interface function not implemented", UVM_NONE); endfunction endclass `define UVM_SEQ_ITEM_TASK_ERROR "Sequencer interface task not implemented" `define UVM_SEQ_ITEM_FUNCTION_ERROR "Sequencer interface function not implemented" virtual class uvm_sqr_if_base #(type T1=uvm_object, T2=T1); virtual task get_next_item(output T1 t); uvm_report_error("get_next_item", "Sequencer interface task not implemented", UVM_NONE); endtask virtual task try_next_item(output T1 t); uvm_report_error("try_next_item", "Sequencer interface task not implemented", UVM_NONE); endtask virtual function void item_done(input T2 t = null); uvm_report_error("item_done", "Sequencer interface function not implemented", UVM_NONE); endfunction virtual task wait_for_sequences(); uvm_report_error("wait_for_sequences", "Sequencer interface task not implemented", UVM_NONE); endtask virtual function bit has_do_available(); uvm_report_error("has_do_available", "Sequencer interface function not implemented", UVM_NONE); return 0; endfunction virtual task get(output T1 t); uvm_report_error("get", "Sequencer interface task not implemented", UVM_NONE); endtask virtual task peek(output T1 t); uvm_report_error("peek", "Sequencer interface task not implemented", UVM_NONE); endtask virtual task put(input T2 t); uvm_report_error("put", "Sequencer interface task not implemented", UVM_NONE); endtask virtual function void put_response(input T2 t); uvm_report_error("put_response", "Sequencer interface function not implemented", UVM_NONE); endfunction virtual function void disable_auto_item_recording(); uvm_report_error("disable_auto_item_recording", "Sequencer interface function not implemented", UVM_NONE); endfunction virtual function bit is_auto_item_recording_enabled(); uvm_report_error("is_auto_item_recording_enabled", "Sequencer interface function not implemented", UVM_NONE); return 0; endfunction endclass const int UVM_UNBOUNDED_CONNECTIONS = -1; const string s_connection_error_id = "Connection Error"; const string s_connection_warning_id = "Connection Warning"; const string s_spaces = " "; typedef class uvm_port_component_base; typedef uvm_port_component_base uvm_port_list[string]; virtual class uvm_port_component_base extends uvm_component; function new (string name, uvm_component parent); super.new(name,parent); endfunction pure virtual function void get_connected_to(ref uvm_port_list list); pure virtual function bit is_port(); pure virtual function bit is_export(); pure virtual function bit is_imp(); virtual function bit use_automatic_config(); return 0; endfunction : use_automatic_config virtual task do_task_phase (uvm_phase phase); endtask endclass class uvm_port_component #(type PORT=uvm_object) extends uvm_port_component_base; PORT m_port; function new (string name, uvm_component parent, PORT port); super.new(name,parent); if (port == null) uvm_report_fatal("Bad usage", "Null handle to port", UVM_NONE); m_port = port; endfunction virtual function string get_type_name(); if(m_port == null) return "uvm_port_component"; return m_port.get_type_name(); endfunction virtual function void resolve_bindings(); m_port.resolve_bindings(); endfunction function PORT get_port(); return m_port; endfunction virtual function void get_connected_to(ref uvm_port_list list); PORT list1[string]; m_port.get_connected_to(list1); list.delete(); foreach(list1[name]) begin list[name] = list1[name].get_comp(); end endfunction function bit is_port (); return m_port.is_port(); endfunction function bit is_export (); return m_port.is_export(); endfunction function bit is_imp (); return m_port.is_imp(); endfunction endclass virtual class uvm_port_base #(type IF=uvm_void) extends IF; typedef uvm_port_base #(IF) this_type; protected int unsigned m_if_mask; protected this_type m_if; protected int unsigned m_def_index; uvm_port_component #(this_type) m_comp; local this_type m_provided_by[string]; local this_type m_provided_to[string]; local uvm_port_type_e m_port_type; local int m_min_size; local int m_max_size; local bit m_resolved; local this_type m_imp_list[string]; function new (string name, uvm_component parent, uvm_port_type_e port_type, int min_size=0, int max_size=1); uvm_component comp; int tmp; m_port_type = port_type; m_min_size = min_size; m_max_size = max_size; m_comp = new(name, parent, this); if (!uvm_config_int::get(m_comp, "", "check_connection_relationships",tmp)) m_comp.set_report_id_action(s_connection_warning_id, UVM_NO_ACTION); endfunction function string get_name(); return m_comp.get_name(); endfunction virtual function string get_full_name(); return m_comp.get_full_name(); endfunction virtual function uvm_component get_parent(); return m_comp.get_parent(); endfunction virtual function uvm_port_component_base get_comp(); return m_comp; endfunction virtual function string get_type_name(); case( m_port_type ) UVM_PORT : return "port"; UVM_EXPORT : return "export"; UVM_IMPLEMENTATION : return "implementation"; endcase endfunction function int max_size (); return m_max_size; endfunction function int min_size (); return m_min_size; endfunction function bit is_unbounded (); return (m_max_size == UVM_UNBOUNDED_CONNECTIONS); endfunction function bit is_port (); return m_port_type == UVM_PORT; endfunction function bit is_export (); return m_port_type == UVM_EXPORT; endfunction function bit is_imp (); return m_port_type == UVM_IMPLEMENTATION; endfunction function int size (); return m_imp_list.num(); endfunction function void set_if (int index=0); m_if = get_if(index); if (m_if != null) m_def_index = index; endfunction function int m_get_if_mask(); return m_if_mask; endfunction function void set_default_index (int index); m_def_index = index; endfunction virtual function void connect (this_type provider); uvm_root top; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); top = cs.get_root(); if (end_of_elaboration_ph.get_state() == UVM_PHASE_EXECUTING || end_of_elaboration_ph.get_state() == UVM_PHASE_DONE ) begin m_comp.uvm_report_warning("Late Connection", {"Attempt to connect ",this.get_full_name()," (of type ",this.get_type_name(), ") at or after end_of_elaboration phase. Ignoring."}); return; end if (provider == null) begin m_comp.uvm_report_error(s_connection_error_id, "Cannot connect to null port handle", UVM_NONE); return; end if (provider == this) begin m_comp.uvm_report_error(s_connection_error_id, "Cannot connect a port instance to itself", UVM_NONE); return; end if ((provider.m_if_mask & m_if_mask) != m_if_mask) begin m_comp.uvm_report_error(s_connection_error_id, {provider.get_full_name(), " (of type ",provider.get_type_name(), ") does not provide the complete interface required of this port (type ", get_type_name(),")"}, UVM_NONE); return; end if (is_imp()) begin m_comp.uvm_report_error(s_connection_error_id, $sformatf( "Cannot call an imp port's connect method. An imp is connected only to the component passed in its constructor. (You attempted to bind this imp to %s)", provider.get_full_name()), UVM_NONE); return; end if (is_export() && provider.is_port()) begin m_comp.uvm_report_error(s_connection_error_id, $sformatf( "Cannot connect exports to ports Try calling port.connect(export) instead. (You attempted to bind this export to %s).", provider.get_full_name()), UVM_NONE); return; end void'(m_check_relationship(provider)); m_provided_by[provider.get_full_name()] = provider; provider.m_provided_to[get_full_name()] = this; endfunction function void debug_connected_to (int level=0, int max_level=-1); int sz, num, curr_num; string s_sz; static string indent, save; this_type port; if (level < 0) level = 0; if (level == 0) begin save = ""; indent=" "; end if (max_level != -1 && level >= max_level) return; num = m_provided_by.num(); if (m_provided_by.num() != 0) begin foreach (m_provided_by[nm]) begin curr_num++; port = m_provided_by[nm]; save = {save, indent, " | \n"}; save = {save, indent, " |_",nm," (",port.get_type_name(),")\n"}; indent = (num > 1 && curr_num != num) ? {indent," | "}:{indent, " "}; port.debug_connected_to(level+1, max_level); indent = indent.substr(0,indent.len()-4-1); end end if (level == 0) begin if (save != "") save = {"This port's fanout network:\n\n ", get_full_name()," (",get_type_name(),")\n",save,"\n"}; if (m_imp_list.num() == 0) begin uvm_root top; uvm_coreservice_t cs; cs = uvm_coreservice_t::get(); top = cs.get_root(); if (end_of_elaboration_ph.get_state() == UVM_PHASE_EXECUTING || end_of_elaboration_ph.get_state() == UVM_PHASE_DONE ) save = {save," Connected implementations: none\n"}; else save = {save, " Connected implementations: not resolved until end-of-elab\n"}; end else begin save = {save," Resolved implementation list:\n"}; foreach (m_imp_list[nm]) begin port = m_imp_list[nm]; s_sz.itoa(sz); save = {save, indent, s_sz, ": ",nm," (",port.get_type_name(),")\n"}; sz++; end end m_comp.uvm_report_info("debug_connected_to", save); end endfunction function void debug_provided_to (int level=0, int max_level=-1); string nm; int num,curr_num; this_type port; static string indent, save; if (level < 0) level = 0; if (level == 0) begin save = ""; indent = " "; end if (max_level != -1 && level > max_level) return; num = m_provided_to.num(); if (num != 0) begin foreach (m_provided_to[nm]) begin curr_num++; port = m_provided_to[nm]; save = {save, indent, " | \n"}; save = {save, indent, " |_",nm," (",port.get_type_name(),")\n"}; indent = (num > 1 && curr_num != num) ? {indent," | "}:{indent, " "}; port.debug_provided_to(level+1, max_level); indent = indent.substr(0,indent.len()-4-1); end end if (level == 0) begin if (save != "") save = {"This port's fanin network:\n\n ", get_full_name()," (",get_type_name(),")\n",save,"\n"}; if (m_provided_to.num() == 0) save = {save,indent,"This port has not been bound\n"}; m_comp.uvm_report_info("debug_provided_to", save); end endfunction function void get_connected_to (ref uvm_port_base #(IF) list[string]); this_type port; list.delete(); foreach (m_provided_by[name]) begin port = m_provided_by[name]; list[name] = port; end endfunction function void get_provided_to (ref uvm_port_base #(IF) list[string]); this_type port; list.delete(); foreach (m_provided_to[name]) begin port = m_provided_to[name]; list[name] = port; end endfunction local function bit m_check_relationship (this_type provider); string s; this_type from; uvm_component from_parent; uvm_component to_parent; uvm_component from_gparent; uvm_component to_gparent; if (get_type_name() == "uvm_analysis_port") return 1; from = this; from_parent = get_parent(); to_parent = provider.get_parent(); if (from_parent == null || to_parent == null) return 1; from_gparent = from_parent.get_parent(); to_gparent = to_parent.get_parent(); if (from.is_port() && provider.is_port() && from_gparent != to_parent) begin s = {provider.get_full_name(), " (of type ",provider.get_type_name(), ") is not up one level of hierarchy from this port. ", "A port-to-port connection takes the form ", "child_component.child_port.connect(parent_port)"}; m_comp.uvm_report_warning(s_connection_warning_id, s, UVM_NONE); return 0; end else if (from.is_port() && (provider.is_export() || provider.is_imp()) && from_gparent != to_gparent) begin s = {provider.get_full_name(), " (of type ",provider.get_type_name(), ") is not at the same level of hierarchy as this port. ", "A port-to-export connection takes the form ", "component1.port.connect(component2.export)"}; m_comp.uvm_report_warning(s_connection_warning_id, s, UVM_NONE); return 0; end else if (from.is_export() && (provider.is_export() || provider.is_imp()) && from_parent != to_gparent) begin s = {provider.get_full_name(), " (of type ",provider.get_type_name(), ") is not down one level of hierarchy from this export. ", "An export-to-export or export-to-imp connection takes the form ", "parent_export.connect(child_component.child_export)"}; m_comp.uvm_report_warning(s_connection_warning_id, s, UVM_NONE); return 0; end return 1; endfunction local function void m_add_list (this_type provider); string sz; this_type imp; for (int i = 0; i < provider.size(); i++) begin imp = provider.get_if(i); if (!m_imp_list.exists(imp.get_full_name())) m_imp_list[imp.get_full_name()] = imp; end endfunction virtual function void resolve_bindings(); if (m_resolved) return; if (is_imp()) begin m_imp_list[get_full_name()] = this; end else begin foreach (m_provided_by[nm]) begin this_type port; port = m_provided_by[nm]; port.resolve_bindings(); m_add_list(port); end end m_resolved = 1; if (size() < min_size() ) begin m_comp.uvm_report_error(s_connection_error_id, $sformatf("connection count of %0d does not meet required minimum of %0d", size(), min_size()), UVM_NONE); end if (max_size() != UVM_UNBOUNDED_CONNECTIONS && size() > max_size() ) begin m_comp.uvm_report_error(s_connection_error_id, $sformatf("connection count of %0d exceeds maximum of %0d", size(), max_size()), UVM_NONE); end if (size()) set_if(0); endfunction function uvm_port_base #(IF) get_if(int index=0); string s; if (size()==0) begin m_comp.uvm_report_warning("get_if", "Port size is zero; cannot get interface at any index", UVM_NONE); return null; end if (index < 0 || index >= size()) begin $sformat(s, "Index %0d out of range [0,%0d]", index, size()-1); m_comp.uvm_report_warning(s_connection_error_id, s, UVM_NONE); return null; end foreach (m_imp_list[nm]) begin if (index == 0) return m_imp_list[nm]; index--; end endfunction endclass class uvm_blocking_put_imp #(type T=int, type IMP=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); local IMP m_imp; function new (string name, IMP imp); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); m_imp = imp; m_if_mask = (1<<0); endfunction virtual function string get_type_name(); return "uvm_blocking_put_imp"; endfunction task put (T t); m_imp.put(t); endtask endclass class uvm_nonblocking_put_imp #(type T=int, type IMP=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); local IMP m_imp; function new (string name, IMP imp); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); m_imp = imp; m_if_mask = (1<<4); endfunction virtual function string get_type_name(); return "uvm_nonblocking_put_imp"; endfunction function bit try_put (T t); return m_imp.try_put(t); endfunction function bit can_put(); return m_imp.can_put(); endfunction endclass class uvm_put_imp #(type T=int, type IMP=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); local IMP m_imp; function new (string name, IMP imp); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); m_imp = imp; m_if_mask = ((1<<0) | (1<<4)); endfunction virtual function string get_type_name(); return "uvm_put_imp"; endfunction task put (T t); m_imp.put(t); endtask function bit try_put (T t); return m_imp.try_put(t); endfunction function bit can_put(); return m_imp.can_put(); endfunction endclass class uvm_blocking_get_imp #(type T=int, type IMP=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); local IMP m_imp; function new (string name, IMP imp); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); m_imp = imp; m_if_mask = (1<<1); endfunction virtual function string get_type_name(); return "uvm_blocking_get_imp"; endfunction task get (output T t); m_imp.get(t); endtask endclass class uvm_nonblocking_get_imp #(type T=int, type IMP=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); local IMP m_imp; function new (string name, IMP imp); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); m_imp = imp; m_if_mask = (1<<5); endfunction virtual function string get_type_name(); return "uvm_nonblocking_get_imp"; endfunction function bit try_get (output T t); return m_imp.try_get(t); endfunction function bit can_get(); return m_imp.can_get(); endfunction endclass class uvm_get_imp #(type T=int, type IMP=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); local IMP m_imp; function new (string name, IMP imp); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); m_imp = imp; m_if_mask = ((1<<1) | (1<<5)); endfunction virtual function string get_type_name(); return "uvm_get_imp"; endfunction task get (output T t); m_imp.get(t); endtask function bit try_get (output T t); return m_imp.try_get(t); endfunction function bit can_get(); return m_imp.can_get(); endfunction endclass class uvm_blocking_peek_imp #(type T=int, type IMP=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); local IMP m_imp; function new (string name, IMP imp); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); m_imp = imp; m_if_mask = (1<<2); endfunction virtual function string get_type_name(); return "uvm_blocking_peek_imp"; endfunction task peek (output T t); m_imp.peek(t); endtask endclass class uvm_nonblocking_peek_imp #(type T=int, type IMP=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); local IMP m_imp; function new (string name, IMP imp); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); m_imp = imp; m_if_mask = (1<<6); endfunction virtual function string get_type_name(); return "uvm_nonblocking_peek_imp"; endfunction function bit try_peek (output T t); return m_imp.try_peek(t); endfunction function bit can_peek(); return m_imp.can_peek(); endfunction endclass class uvm_peek_imp #(type T=int, type IMP=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); local IMP m_imp; function new (string name, IMP imp); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); m_imp = imp; m_if_mask = ((1<<2) | (1<<6)); endfunction virtual function string get_type_name(); return "uvm_peek_imp"; endfunction task peek (output T t); m_imp.peek(t); endtask function bit try_peek (output T t); return m_imp.try_peek(t); endfunction function bit can_peek(); return m_imp.can_peek(); endfunction endclass class uvm_blocking_get_peek_imp #(type T=int, type IMP=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); local IMP m_imp; function new (string name, IMP imp); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); m_imp = imp; m_if_mask = ((1<<1) | (1<<2)); endfunction virtual function string get_type_name(); return "uvm_blocking_get_peek_imp"; endfunction task get (output T t); m_imp.get(t); endtask task peek (output T t); m_imp.peek(t); endtask endclass class uvm_nonblocking_get_peek_imp #(type T=int, type IMP=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); local IMP m_imp; function new (string name, IMP imp); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); m_imp = imp; m_if_mask = ((1<<5) | (1<<6)); endfunction virtual function string get_type_name(); return "uvm_nonblocking_get_peek_imp"; endfunction function bit try_get (output T t); return m_imp.try_get(t); endfunction function bit can_get(); return m_imp.can_get(); endfunction function bit try_peek (output T t); return m_imp.try_peek(t); endfunction function bit can_peek(); return m_imp.can_peek(); endfunction endclass class uvm_get_peek_imp #(type T=int, type IMP=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); local IMP m_imp; function new (string name, IMP imp); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); m_imp = imp; m_if_mask = (((1<<1) | (1<<5)) | ((1<<2) | (1<<6))); endfunction virtual function string get_type_name(); return "uvm_get_peek_imp"; endfunction task get (output T t); m_imp.get(t); endtask task peek (output T t); m_imp.peek(t); endtask function bit try_get (output T t); return m_imp.try_get(t); endfunction function bit can_get(); return m_imp.can_get(); endfunction function bit try_peek (output T t); return m_imp.try_peek(t); endfunction function bit can_peek(); return m_imp.can_peek(); endfunction endclass class uvm_blocking_master_imp #(type REQ=int, type RSP=REQ, type IMP=int, type REQ_IMP=IMP, type RSP_IMP=IMP) extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); typedef IMP this_imp_type; typedef REQ_IMP this_req_type; typedef RSP_IMP this_rsp_type; local this_req_type m_req_imp; local this_rsp_type m_rsp_imp; function new (string name, this_imp_type imp, this_req_type req_imp = null, this_rsp_type rsp_imp = null); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); if(req_imp==null) $cast(req_imp, imp); if(rsp_imp==null) $cast(rsp_imp, imp); m_req_imp = req_imp; m_rsp_imp = rsp_imp; m_if_mask = ((1<<0) | (1<<1) | (1<<2) | (1<<9)); endfunction virtual function string get_type_name(); return "uvm_blocking_master_imp"; endfunction task put (REQ t); m_req_imp.put(t); endtask task get (output RSP t); m_rsp_imp.get(t); endtask task peek (output RSP t); m_rsp_imp.peek(t); endtask endclass class uvm_nonblocking_master_imp #(type REQ=int, type RSP=REQ, type IMP=int, type REQ_IMP=IMP, type RSP_IMP=IMP) extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); typedef IMP this_imp_type; typedef REQ_IMP this_req_type; typedef RSP_IMP this_rsp_type; local this_req_type m_req_imp; local this_rsp_type m_rsp_imp; function new (string name, this_imp_type imp, this_req_type req_imp = null, this_rsp_type rsp_imp = null); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); if(req_imp==null) $cast(req_imp, imp); if(rsp_imp==null) $cast(rsp_imp, imp); m_req_imp = req_imp; m_rsp_imp = rsp_imp; m_if_mask = ((1<<4) | (1<<5) | (1<<6) | (1<<9)); endfunction virtual function string get_type_name(); return "uvm_nonblocking_master_imp"; endfunction function bit try_put (REQ t); return m_req_imp.try_put(t); endfunction function bit can_put(); return m_req_imp.can_put(); endfunction function bit try_get (output RSP t); return m_rsp_imp.try_get(t); endfunction function bit can_get(); return m_rsp_imp.can_get(); endfunction function bit try_peek (output RSP t); return m_rsp_imp.try_peek(t); endfunction function bit can_peek(); return m_rsp_imp.can_peek(); endfunction endclass class uvm_master_imp #(type REQ=int, type RSP=REQ, type IMP=int, type REQ_IMP=IMP, type RSP_IMP=IMP) extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); typedef IMP this_imp_type; typedef REQ_IMP this_req_type; typedef RSP_IMP this_rsp_type; local this_req_type m_req_imp; local this_rsp_type m_rsp_imp; function new (string name, this_imp_type imp, this_req_type req_imp = null, this_rsp_type rsp_imp = null); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); if(req_imp==null) $cast(req_imp, imp); if(rsp_imp==null) $cast(rsp_imp, imp); m_req_imp = req_imp; m_rsp_imp = rsp_imp; m_if_mask = (((1<<0) | (1<<1) | (1<<2) | (1<<9)) | ((1<<4) | (1<<5) | (1<<6) | (1<<9))); endfunction virtual function string get_type_name(); return "uvm_master_imp"; endfunction task put (REQ t); m_req_imp.put(t); endtask function bit try_put (REQ t); return m_req_imp.try_put(t); endfunction function bit can_put(); return m_req_imp.can_put(); endfunction task get (output RSP t); m_rsp_imp.get(t); endtask task peek (output RSP t); m_rsp_imp.peek(t); endtask function bit try_get (output RSP t); return m_rsp_imp.try_get(t); endfunction function bit can_get(); return m_rsp_imp.can_get(); endfunction function bit try_peek (output RSP t); return m_rsp_imp.try_peek(t); endfunction function bit can_peek(); return m_rsp_imp.can_peek(); endfunction endclass class uvm_blocking_slave_imp #(type REQ=int, type RSP=REQ, type IMP=int, type REQ_IMP=IMP, type RSP_IMP=IMP) extends uvm_port_base #(uvm_tlm_if_base #(RSP, REQ)); typedef IMP this_imp_type; typedef REQ_IMP this_req_type; typedef RSP_IMP this_rsp_type; local this_req_type m_req_imp; local this_rsp_type m_rsp_imp; function new (string name, this_imp_type imp, this_req_type req_imp = null, this_rsp_type rsp_imp = null); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); if(req_imp==null) $cast(req_imp, imp); if(rsp_imp==null) $cast(rsp_imp, imp); m_req_imp = req_imp; m_rsp_imp = rsp_imp; m_if_mask = ((1<<0) | (1<<1) | (1<<2) | (1<<10)); endfunction virtual function string get_type_name(); return "uvm_blocking_slave_imp"; endfunction task put (RSP t); m_rsp_imp.put(t); endtask task get (output REQ t); m_req_imp.get(t); endtask task peek (output REQ t); m_req_imp.peek(t); endtask endclass class uvm_nonblocking_slave_imp #(type REQ=int, type RSP=REQ, type IMP=int, type REQ_IMP=IMP, type RSP_IMP=IMP) extends uvm_port_base #(uvm_tlm_if_base #(RSP, REQ)); typedef IMP this_imp_type; typedef REQ_IMP this_req_type; typedef RSP_IMP this_rsp_type; local this_req_type m_req_imp; local this_rsp_type m_rsp_imp; function new (string name, this_imp_type imp, this_req_type req_imp = null, this_rsp_type rsp_imp = null); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); if(req_imp==null) $cast(req_imp, imp); if(rsp_imp==null) $cast(rsp_imp, imp); m_req_imp = req_imp; m_rsp_imp = rsp_imp; m_if_mask = ((1<<4) | (1<<5) | (1<<6) | (1<<10)); endfunction virtual function string get_type_name(); return "uvm_nonblocking_slave_imp"; endfunction function bit try_put (RSP t); return m_rsp_imp.try_put(t); endfunction function bit can_put(); return m_rsp_imp.can_put(); endfunction function bit try_get (output REQ t); return m_req_imp.try_get(t); endfunction function bit can_get(); return m_req_imp.can_get(); endfunction function bit try_peek (output REQ t); return m_req_imp.try_peek(t); endfunction function bit can_peek(); return m_req_imp.can_peek(); endfunction endclass class uvm_slave_imp #(type REQ=int, type RSP=REQ, type IMP=int, type REQ_IMP=IMP, type RSP_IMP=IMP) extends uvm_port_base #(uvm_tlm_if_base #(RSP, REQ)); typedef IMP this_imp_type; typedef REQ_IMP this_req_type; typedef RSP_IMP this_rsp_type; local this_req_type m_req_imp; local this_rsp_type m_rsp_imp; function new (string name, this_imp_type imp, this_req_type req_imp = null, this_rsp_type rsp_imp = null); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); if(req_imp==null) $cast(req_imp, imp); if(rsp_imp==null) $cast(rsp_imp, imp); m_req_imp = req_imp; m_rsp_imp = rsp_imp; m_if_mask = (((1<<0) | (1<<1) | (1<<2) | (1<<10)) | ((1<<4) | (1<<5) | (1<<6) | (1<<10))); endfunction virtual function string get_type_name(); return "uvm_slave_imp"; endfunction task put (RSP t); m_rsp_imp.put(t); endtask function bit try_put (RSP t); return m_rsp_imp.try_put(t); endfunction function bit can_put(); return m_rsp_imp.can_put(); endfunction task get (output REQ t); m_req_imp.get(t); endtask task peek (output REQ t); m_req_imp.peek(t); endtask function bit try_get (output REQ t); return m_req_imp.try_get(t); endfunction function bit can_get(); return m_req_imp.can_get(); endfunction function bit try_peek (output REQ t); return m_req_imp.try_peek(t); endfunction function bit can_peek(); return m_req_imp.can_peek(); endfunction endclass class uvm_blocking_transport_imp #(type REQ=int, type RSP=REQ, type IMP=int) extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); local IMP m_imp; function new (string name, IMP imp); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); m_imp = imp; m_if_mask = (1<<3); endfunction virtual function string get_type_name(); return "uvm_blocking_transport_imp"; endfunction task transport (REQ req, output RSP rsp); m_imp.transport(req, rsp); endtask endclass class uvm_nonblocking_transport_imp #(type REQ=int, type RSP=REQ, type IMP=int) extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); local IMP m_imp; function new (string name, IMP imp); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); m_imp = imp; m_if_mask = (1<<7); endfunction virtual function string get_type_name(); return "uvm_nonblocking_transport_imp"; endfunction function bit nb_transport (REQ req, output RSP rsp); return m_imp.nb_transport(req, rsp); endfunction endclass class uvm_transport_imp #(type REQ=int, type RSP=REQ, type IMP=int) extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); local IMP m_imp; function new (string name, IMP imp); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); m_imp = imp; m_if_mask = ((1<<3) | (1<<7)); endfunction virtual function string get_type_name(); return "uvm_transport_imp"; endfunction task transport (REQ req, output RSP rsp); m_imp.transport(req, rsp); endtask function bit nb_transport (REQ req, output RSP rsp); return m_imp.nb_transport(req, rsp); endfunction endclass class uvm_blocking_put_port #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = (1<<0); endfunction virtual function string get_type_name(); return "uvm_blocking_put_port"; endfunction task put (T t); this.m_if.put(t); endtask endclass class uvm_nonblocking_put_port #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = (1<<4); endfunction virtual function string get_type_name(); return "uvm_nonblocking_put_port"; endfunction function bit try_put (T t); return this.m_if.try_put(t); endfunction function bit can_put(); return this.m_if.can_put(); endfunction endclass class uvm_put_port #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = ((1<<0) | (1<<4)); endfunction virtual function string get_type_name(); return "uvm_put_port"; endfunction task put (T t); this.m_if.put(t); endtask function bit try_put (T t); return this.m_if.try_put(t); endfunction function bit can_put(); return this.m_if.can_put(); endfunction endclass class uvm_blocking_get_port #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = (1<<1); endfunction virtual function string get_type_name(); return "uvm_blocking_get_port"; endfunction task get (output T t); this.m_if.get(t); endtask endclass class uvm_nonblocking_get_port #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = (1<<5); endfunction virtual function string get_type_name(); return "uvm_nonblocking_get_port"; endfunction function bit try_get (output T t); return this.m_if.try_get(t); endfunction function bit can_get(); return this.m_if.can_get(); endfunction endclass class uvm_get_port #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = ((1<<1) | (1<<5)); endfunction virtual function string get_type_name(); return "uvm_get_port"; endfunction task get (output T t); this.m_if.get(t); endtask function bit try_get (output T t); return this.m_if.try_get(t); endfunction function bit can_get(); return this.m_if.can_get(); endfunction endclass class uvm_blocking_peek_port #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = (1<<2); endfunction virtual function string get_type_name(); return "uvm_blocking_peek_port"; endfunction task peek (output T t); this.m_if.peek(t); endtask endclass class uvm_nonblocking_peek_port #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = (1<<6); endfunction virtual function string get_type_name(); return "uvm_nonblocking_peek_port"; endfunction function bit try_peek (output T t); return this.m_if.try_peek(t); endfunction function bit can_peek(); return this.m_if.can_peek(); endfunction endclass class uvm_peek_port #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = ((1<<2) | (1<<6)); endfunction virtual function string get_type_name(); return "uvm_peek_port"; endfunction task peek (output T t); this.m_if.peek(t); endtask function bit try_peek (output T t); return this.m_if.try_peek(t); endfunction function bit can_peek(); return this.m_if.can_peek(); endfunction endclass class uvm_blocking_get_peek_port #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = ((1<<1) | (1<<2)); endfunction virtual function string get_type_name(); return "uvm_blocking_get_peek_port"; endfunction task get (output T t); this.m_if.get(t); endtask task peek (output T t); this.m_if.peek(t); endtask endclass class uvm_nonblocking_get_peek_port #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = ((1<<5) | (1<<6)); endfunction virtual function string get_type_name(); return "uvm_nonblocking_get_peek_port"; endfunction function bit try_get (output T t); return this.m_if.try_get(t); endfunction function bit can_get(); return this.m_if.can_get(); endfunction function bit try_peek (output T t); return this.m_if.try_peek(t); endfunction function bit can_peek(); return this.m_if.can_peek(); endfunction endclass class uvm_get_peek_port #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = (((1<<1) | (1<<5)) | ((1<<2) | (1<<6))); endfunction virtual function string get_type_name(); return "uvm_get_peek_port"; endfunction task get (output T t); this.m_if.get(t); endtask task peek (output T t); this.m_if.peek(t); endtask function bit try_get (output T t); return this.m_if.try_get(t); endfunction function bit can_get(); return this.m_if.can_get(); endfunction function bit try_peek (output T t); return this.m_if.try_peek(t); endfunction function bit can_peek(); return this.m_if.can_peek(); endfunction endclass class uvm_blocking_master_port #(type REQ=int, type RSP=REQ) extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = ((1<<0) | (1<<1) | (1<<2) | (1<<9)); endfunction virtual function string get_type_name(); return "uvm_blocking_master_port"; endfunction task put (REQ t); this.m_if.put(t); endtask task get (output RSP t); this.m_if.get(t); endtask task peek (output RSP t); this.m_if.peek(t); endtask endclass class uvm_nonblocking_master_port #(type REQ=int, type RSP=REQ) extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = ((1<<4) | (1<<5) | (1<<6) | (1<<9)); endfunction virtual function string get_type_name(); return "uvm_nonblocking_master_port"; endfunction function bit try_put (REQ t); return this.m_if.try_put(t); endfunction function bit can_put(); return this.m_if.can_put(); endfunction function bit try_get (output RSP t); return this.m_if.try_get(t); endfunction function bit can_get(); return this.m_if.can_get(); endfunction function bit try_peek (output RSP t); return this.m_if.try_peek(t); endfunction function bit can_peek(); return this.m_if.can_peek(); endfunction endclass class uvm_master_port #(type REQ=int, type RSP=REQ) extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = (((1<<0) | (1<<1) | (1<<2) | (1<<9)) | ((1<<4) | (1<<5) | (1<<6) | (1<<9))); endfunction virtual function string get_type_name(); return "uvm_master_port"; endfunction task put (REQ t); this.m_if.put(t); endtask function bit try_put (REQ t); return this.m_if.try_put(t); endfunction function bit can_put(); return this.m_if.can_put(); endfunction task get (output RSP t); this.m_if.get(t); endtask task peek (output RSP t); this.m_if.peek(t); endtask function bit try_get (output RSP t); return this.m_if.try_get(t); endfunction function bit can_get(); return this.m_if.can_get(); endfunction function bit try_peek (output RSP t); return this.m_if.try_peek(t); endfunction function bit can_peek(); return this.m_if.can_peek(); endfunction endclass class uvm_blocking_slave_port #(type REQ=int, type RSP=REQ) extends uvm_port_base #(uvm_tlm_if_base #(RSP, REQ)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = ((1<<0) | (1<<1) | (1<<2) | (1<<10)); endfunction virtual function string get_type_name(); return "uvm_blocking_slave_port"; endfunction task put (RSP t); this.m_if.put(t); endtask task get (output REQ t); this.m_if.get(t); endtask task peek (output REQ t); this.m_if.peek(t); endtask endclass class uvm_nonblocking_slave_port #(type REQ=int, type RSP=REQ) extends uvm_port_base #(uvm_tlm_if_base #(RSP, REQ)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = ((1<<4) | (1<<5) | (1<<6) | (1<<10)); endfunction virtual function string get_type_name(); return "uvm_nonblocking_slave_port"; endfunction function bit try_put (RSP t); return this.m_if.try_put(t); endfunction function bit can_put(); return this.m_if.can_put(); endfunction function bit try_get (output REQ t); return this.m_if.try_get(t); endfunction function bit can_get(); return this.m_if.can_get(); endfunction function bit try_peek (output REQ t); return this.m_if.try_peek(t); endfunction function bit can_peek(); return this.m_if.can_peek(); endfunction endclass class uvm_slave_port #(type REQ=int, type RSP=REQ) extends uvm_port_base #(uvm_tlm_if_base #(RSP, REQ)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = (((1<<0) | (1<<1) | (1<<2) | (1<<10)) | ((1<<4) | (1<<5) | (1<<6) | (1<<10))); endfunction virtual function string get_type_name(); return "uvm_slave_port"; endfunction task put (RSP t); this.m_if.put(t); endtask function bit try_put (RSP t); return this.m_if.try_put(t); endfunction function bit can_put(); return this.m_if.can_put(); endfunction task get (output REQ t); this.m_if.get(t); endtask task peek (output REQ t); this.m_if.peek(t); endtask function bit try_get (output REQ t); return this.m_if.try_get(t); endfunction function bit can_get(); return this.m_if.can_get(); endfunction function bit try_peek (output REQ t); return this.m_if.try_peek(t); endfunction function bit can_peek(); return this.m_if.can_peek(); endfunction endclass class uvm_blocking_transport_port #(type REQ=int, type RSP=REQ) extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = (1<<3); endfunction virtual function string get_type_name(); return "uvm_blocking_transport_port"; endfunction task transport (REQ req, output RSP rsp); this.m_if.transport(req, rsp); endtask endclass class uvm_nonblocking_transport_port #(type REQ=int, type RSP=REQ) extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = (1<<7); endfunction virtual function string get_type_name(); return "uvm_nonblocking_transport_port"; endfunction function bit nb_transport (REQ req, output RSP rsp); return this.m_if.nb_transport(req, rsp); endfunction endclass class uvm_transport_port #(type REQ=int, type RSP=REQ) extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = ((1<<3) | (1<<7)); endfunction virtual function string get_type_name(); return "uvm_transport_port"; endfunction task transport (REQ req, output RSP rsp); this.m_if.transport(req, rsp); endtask function bit nb_transport (REQ req, output RSP rsp); return this.m_if.nb_transport(req, rsp); endfunction endclass class uvm_blocking_put_export #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = (1<<0); endfunction virtual function string get_type_name(); return "uvm_blocking_put_export"; endfunction task put (T t); this.m_if.put(t); endtask endclass class uvm_nonblocking_put_export #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = (1<<4); endfunction virtual function string get_type_name(); return "uvm_nonblocking_put_export"; endfunction function bit try_put (T t); return this.m_if.try_put(t); endfunction function bit can_put(); return this.m_if.can_put(); endfunction endclass class uvm_put_export #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = ((1<<0) | (1<<4)); endfunction virtual function string get_type_name(); return "uvm_put_export"; endfunction task put (T t); this.m_if.put(t); endtask function bit try_put (T t); return this.m_if.try_put(t); endfunction function bit can_put(); return this.m_if.can_put(); endfunction endclass class uvm_blocking_get_export #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = (1<<1); endfunction virtual function string get_type_name(); return "uvm_blocking_get_export"; endfunction task get (output T t); this.m_if.get(t); endtask endclass class uvm_nonblocking_get_export #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = (1<<5); endfunction virtual function string get_type_name(); return "uvm_nonblocking_get_export"; endfunction function bit try_get (output T t); return this.m_if.try_get(t); endfunction function bit can_get(); return this.m_if.can_get(); endfunction endclass class uvm_get_export #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = ((1<<1) | (1<<5)); endfunction virtual function string get_type_name(); return "uvm_get_export"; endfunction task get (output T t); this.m_if.get(t); endtask function bit try_get (output T t); return this.m_if.try_get(t); endfunction function bit can_get(); return this.m_if.can_get(); endfunction endclass class uvm_blocking_peek_export #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = (1<<2); endfunction virtual function string get_type_name(); return "uvm_blocking_peek_export"; endfunction task peek (output T t); this.m_if.peek(t); endtask endclass class uvm_nonblocking_peek_export #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = (1<<6); endfunction virtual function string get_type_name(); return "uvm_nonblocking_peek_export"; endfunction function bit try_peek (output T t); return this.m_if.try_peek(t); endfunction function bit can_peek(); return this.m_if.can_peek(); endfunction endclass class uvm_peek_export #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = ((1<<2) | (1<<6)); endfunction virtual function string get_type_name(); return "uvm_peek_export"; endfunction task peek (output T t); this.m_if.peek(t); endtask function bit try_peek (output T t); return this.m_if.try_peek(t); endfunction function bit can_peek(); return this.m_if.can_peek(); endfunction endclass class uvm_blocking_get_peek_export #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = ((1<<1) | (1<<2)); endfunction virtual function string get_type_name(); return "uvm_blocking_get_peek_export"; endfunction task get (output T t); this.m_if.get(t); endtask task peek (output T t); this.m_if.peek(t); endtask endclass class uvm_nonblocking_get_peek_export #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = ((1<<5) | (1<<6)); endfunction virtual function string get_type_name(); return "uvm_nonblocking_get_peek_export"; endfunction function bit try_get (output T t); return this.m_if.try_get(t); endfunction function bit can_get(); return this.m_if.can_get(); endfunction function bit try_peek (output T t); return this.m_if.try_peek(t); endfunction function bit can_peek(); return this.m_if.can_peek(); endfunction endclass class uvm_get_peek_export #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = (((1<<1) | (1<<5)) | ((1<<2) | (1<<6))); endfunction virtual function string get_type_name(); return "uvm_get_peek_export"; endfunction task get (output T t); this.m_if.get(t); endtask task peek (output T t); this.m_if.peek(t); endtask function bit try_get (output T t); return this.m_if.try_get(t); endfunction function bit can_get(); return this.m_if.can_get(); endfunction function bit try_peek (output T t); return this.m_if.try_peek(t); endfunction function bit can_peek(); return this.m_if.can_peek(); endfunction endclass class uvm_blocking_master_export #(type REQ=int, type RSP=REQ) extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = ((1<<0) | (1<<1) | (1<<2) | (1<<9)); endfunction virtual function string get_type_name(); return "uvm_blocking_master_export"; endfunction task put (REQ t); this.m_if.put(t); endtask task get (output RSP t); this.m_if.get(t); endtask task peek (output RSP t); this.m_if.peek(t); endtask endclass class uvm_nonblocking_master_export #(type REQ=int, type RSP=REQ) extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = ((1<<4) | (1<<5) | (1<<6) | (1<<9)); endfunction virtual function string get_type_name(); return "uvm_nonblocking_master_export"; endfunction function bit try_put (REQ t); return this.m_if.try_put(t); endfunction function bit can_put(); return this.m_if.can_put(); endfunction function bit try_get (output RSP t); return this.m_if.try_get(t); endfunction function bit can_get(); return this.m_if.can_get(); endfunction function bit try_peek (output RSP t); return this.m_if.try_peek(t); endfunction function bit can_peek(); return this.m_if.can_peek(); endfunction endclass class uvm_master_export #(type REQ=int, type RSP=REQ) extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = (((1<<0) | (1<<1) | (1<<2) | (1<<9)) | ((1<<4) | (1<<5) | (1<<6) | (1<<9))); endfunction virtual function string get_type_name(); return "uvm_master_export"; endfunction task put (REQ t); this.m_if.put(t); endtask function bit try_put (REQ t); return this.m_if.try_put(t); endfunction function bit can_put(); return this.m_if.can_put(); endfunction task get (output RSP t); this.m_if.get(t); endtask task peek (output RSP t); this.m_if.peek(t); endtask function bit try_get (output RSP t); return this.m_if.try_get(t); endfunction function bit can_get(); return this.m_if.can_get(); endfunction function bit try_peek (output RSP t); return this.m_if.try_peek(t); endfunction function bit can_peek(); return this.m_if.can_peek(); endfunction endclass class uvm_blocking_slave_export #(type REQ=int, type RSP=REQ) extends uvm_port_base #(uvm_tlm_if_base #(RSP, REQ)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = ((1<<0) | (1<<1) | (1<<2) | (1<<10)); endfunction virtual function string get_type_name(); return "uvm_blocking_slave_export"; endfunction task put (RSP t); this.m_if.put(t); endtask task get (output REQ t); this.m_if.get(t); endtask task peek (output REQ t); this.m_if.peek(t); endtask endclass class uvm_nonblocking_slave_export #(type REQ=int, type RSP=REQ) extends uvm_port_base #(uvm_tlm_if_base #(RSP, REQ)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = ((1<<4) | (1<<5) | (1<<6) | (1<<10)); endfunction virtual function string get_type_name(); return "uvm_nonblocking_slave_export"; endfunction function bit try_put (RSP t); return this.m_if.try_put(t); endfunction function bit can_put(); return this.m_if.can_put(); endfunction function bit try_get (output REQ t); return this.m_if.try_get(t); endfunction function bit can_get(); return this.m_if.can_get(); endfunction function bit try_peek (output REQ t); return this.m_if.try_peek(t); endfunction function bit can_peek(); return this.m_if.can_peek(); endfunction endclass class uvm_slave_export #(type REQ=int, type RSP=REQ) extends uvm_port_base #(uvm_tlm_if_base #(RSP, REQ)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = (((1<<0) | (1<<1) | (1<<2) | (1<<10)) | ((1<<4) | (1<<5) | (1<<6) | (1<<10))); endfunction virtual function string get_type_name(); return "uvm_slave_export"; endfunction task put (RSP t); this.m_if.put(t); endtask function bit try_put (RSP t); return this.m_if.try_put(t); endfunction function bit can_put(); return this.m_if.can_put(); endfunction task get (output REQ t); this.m_if.get(t); endtask task peek (output REQ t); this.m_if.peek(t); endtask function bit try_get (output REQ t); return this.m_if.try_get(t); endfunction function bit can_get(); return this.m_if.can_get(); endfunction function bit try_peek (output REQ t); return this.m_if.try_peek(t); endfunction function bit can_peek(); return this.m_if.can_peek(); endfunction endclass class uvm_blocking_transport_export #(type REQ=int, type RSP=REQ) extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = (1<<3); endfunction virtual function string get_type_name(); return "uvm_blocking_transport_export"; endfunction task transport (REQ req, output RSP rsp); this.m_if.transport(req, rsp); endtask endclass class uvm_nonblocking_transport_export #(type REQ=int, type RSP=REQ) extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = (1<<7); endfunction virtual function string get_type_name(); return "uvm_nonblocking_transport_export"; endfunction function bit nb_transport (REQ req, output RSP rsp); return this.m_if.nb_transport(req, rsp); endfunction endclass class uvm_transport_export #(type REQ=int, type RSP=REQ) extends uvm_port_base #(uvm_tlm_if_base #(REQ, RSP)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = ((1<<3) | (1<<7)); endfunction virtual function string get_type_name(); return "uvm_transport_export"; endfunction task transport (REQ req, output RSP rsp); this.m_if.transport(req, rsp); endtask function bit nb_transport (REQ req, output RSP rsp); return this.m_if.nb_transport(req, rsp); endfunction endclass class uvm_analysis_port # (type T = int) extends uvm_port_base # (uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent); super.new (name, parent, UVM_PORT, 0, UVM_UNBOUNDED_CONNECTIONS); m_if_mask = (1<<8); endfunction virtual function string get_type_name(); return "uvm_analysis_port"; endfunction function void write (input T t); uvm_tlm_if_base # (T, T) tif; for (int i = 0; i < this.size(); i++) begin tif = this.get_if (i); if ( tif == null ) uvm_report_fatal ("NTCONN", {"No uvm_tlm interface is connected to ", get_full_name(), " for executing write()"}, UVM_NONE); tif.write (t); end endfunction endclass class uvm_analysis_imp #(type T=int, type IMP=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); local IMP m_imp; function new (string name, IMP imp); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); m_imp = imp; m_if_mask = (1<<8); endfunction virtual function string get_type_name(); return "uvm_analysis_imp"; endfunction function void write (input T t); m_imp.write (t); endfunction endclass class uvm_analysis_export #(type T=int) extends uvm_port_base #(uvm_tlm_if_base #(T,T)); function new (string name, uvm_component parent = null); super.new (name, parent, UVM_EXPORT, 1, UVM_UNBOUNDED_CONNECTIONS); m_if_mask = (1<<8); endfunction virtual function string get_type_name(); return "uvm_analysis_export"; endfunction function void write (input T t); uvm_tlm_if_base #(T, T) tif; for (int i = 0; i < this.size(); i++) begin tif = this.get_if (i); if (tif == null) uvm_report_fatal ("NTCONN", {"No uvm_tlm interface is connected to ", get_full_name(), " for executing write()"}, UVM_NONE); tif.write (t); end endfunction endclass `define UVM_TLM_FIFO_TASK_ERROR "fifo channel task not implemented" `define UVM_TLM_FIFO_FUNCTION_ERROR "fifo channel function not implemented" class uvm_tlm_event; event trigger; endclass virtual class uvm_tlm_fifo_base #(type T=int) extends uvm_component; typedef uvm_abstract_component_registry #(uvm_tlm_fifo_base #(T)) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction typedef uvm_tlm_fifo_base #(T) this_type; uvm_put_imp #(T, this_type) put_export; uvm_get_peek_imp #(T, this_type) get_peek_export; uvm_analysis_port #(T) put_ap; uvm_analysis_port #(T) get_ap; uvm_put_imp #(T, this_type) blocking_put_export; uvm_put_imp #(T, this_type) nonblocking_put_export; uvm_get_peek_imp #(T, this_type) blocking_get_export; uvm_get_peek_imp #(T, this_type) nonblocking_get_export; uvm_get_peek_imp #(T, this_type) get_export; uvm_get_peek_imp #(T, this_type) blocking_peek_export; uvm_get_peek_imp #(T, this_type) nonblocking_peek_export; uvm_get_peek_imp #(T, this_type) peek_export; uvm_get_peek_imp #(T, this_type) blocking_get_peek_export; uvm_get_peek_imp #(T, this_type) nonblocking_get_peek_export; function new(string name, uvm_component parent = null); super.new(name, parent); put_export = new("put_export", this); blocking_put_export = put_export; nonblocking_put_export = put_export; get_peek_export = new("get_peek_export", this); blocking_get_peek_export = get_peek_export; nonblocking_get_peek_export = get_peek_export; blocking_get_export = get_peek_export; nonblocking_get_export = get_peek_export; get_export = get_peek_export; blocking_peek_export = get_peek_export; nonblocking_peek_export = get_peek_export; peek_export = get_peek_export; put_ap = new("put_ap", this); get_ap = new("get_ap", this); endfunction virtual function bit use_automatic_config(); return 0; endfunction : use_automatic_config virtual function void flush(); uvm_report_error("flush", "fifo channel function not implemented", UVM_NONE); endfunction virtual function int size(); uvm_report_error("size", "fifo channel function not implemented", UVM_NONE); return 0; endfunction virtual task put(T t); uvm_report_error("put", "fifo channel task not implemented", UVM_NONE); endtask virtual task get(output T t); uvm_report_error("get", "fifo channel task not implemented", UVM_NONE); endtask virtual task peek(output T t); uvm_report_error("peek", "fifo channel task not implemented", UVM_NONE); endtask virtual function bit try_put(T t); uvm_report_error("try_put", "fifo channel function not implemented", UVM_NONE); return 0; endfunction virtual function bit try_get(output T t); uvm_report_error("try_get", "fifo channel function not implemented", UVM_NONE); return 0; endfunction virtual function bit try_peek(output T t); uvm_report_error("try_peek", "fifo channel function not implemented", UVM_NONE); return 0; endfunction virtual function bit can_put(); uvm_report_error("can_put", "fifo channel function not implemented", UVM_NONE); return 0; endfunction virtual function bit can_get(); uvm_report_error("can_get", "fifo channel function not implemented", UVM_NONE); return 0; endfunction virtual function bit can_peek(); uvm_report_error("can_peek", "fifo channel function not implemented", UVM_NONE); return 0; endfunction virtual function uvm_tlm_event ok_to_put(); uvm_report_error("ok_to_put", "fifo channel function not implemented", UVM_NONE); return null; endfunction virtual function uvm_tlm_event ok_to_get(); uvm_report_error("ok_to_get", "fifo channel function not implemented", UVM_NONE); return null; endfunction virtual function uvm_tlm_event ok_to_peek(); uvm_report_error("ok_to_peek", "fifo channel function not implemented", UVM_NONE); return null; endfunction virtual function bit is_empty(); uvm_report_error("is_empty", "fifo channel function not implemented", UVM_NONE); return 0; endfunction virtual function bit is_full(); uvm_report_error("is_full", "fifo channel function not implemented"); return 0; endfunction virtual function int used(); uvm_report_error("used", "fifo channel function not implemented", UVM_NONE); return 0; endfunction endclass typedef class uvm_tlm_event; class uvm_tlm_fifo #(type T=int) extends uvm_tlm_fifo_base #(T); typedef uvm_component_registry #(uvm_tlm_fifo#(T)) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_tlm_fifo #(T)"; endfunction : type_name virtual function string get_type_name(); return "uvm_tlm_fifo #(T)"; endfunction : get_type_name local mailbox #( T ) m; local int m_size; protected int m_pending_blocked_gets; function new(string name, uvm_component parent = null, int size = 1); super.new(name, parent); m = new( size ); m_size = size; endfunction virtual function int size(); return m_size; endfunction virtual function int used(); return m.num(); endfunction virtual function bit is_empty(); return (m.num() == 0); endfunction virtual function bit is_full(); return (m_size != 0) && (m.num() == m_size); endfunction virtual task put( input T t ); m.put( t ); put_ap.write( t ); endtask virtual task get( output T t ); m_pending_blocked_gets++; m.get( t ); m_pending_blocked_gets--; get_ap.write( t ); endtask virtual task peek( output T t ); m.peek( t ); endtask virtual function bit try_get( output T t ); if( !m.try_get( t ) ) begin return 0; end get_ap.write( t ); return 1; endfunction virtual function bit try_peek( output T t ); if( !m.try_peek( t ) ) begin return 0; end return 1; endfunction virtual function bit try_put( input T t ); if( !m.try_put( t ) ) begin return 0; end put_ap.write( t ); return 1; endfunction virtual function bit can_put(); return m_size == 0 || m.num() < m_size; endfunction virtual function bit can_get(); return m.num() > 0 && m_pending_blocked_gets == 0; endfunction virtual function bit can_peek(); return m.num() > 0; endfunction virtual function void flush(); T t; bit r; r = 1; while( r ) r = try_get( t ) ; if( m.num() > 0 && m_pending_blocked_gets != 0 ) begin uvm_report_error("flush failed" , "there are blocked gets preventing the flush", UVM_NONE); end endfunction endclass class uvm_tlm_analysis_fifo #(type T = int) extends uvm_tlm_fifo #(T); typedef uvm_component_registry #(uvm_tlm_analysis_fifo#(T)) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_tlm_analysis_fifo #(T)"; endfunction : type_name virtual function string get_type_name(); return "uvm_tlm_analysis_fifo #(T)"; endfunction : get_type_name uvm_analysis_imp #(T, uvm_tlm_analysis_fifo #(T)) analysis_export; function new(string name , uvm_component parent = null); super.new(name, parent, 0); analysis_export = new("analysis_export", this); endfunction function void write(input T t); void'(this.try_put(t)); endfunction endclass class uvm_tlm_req_rsp_channel #(type REQ=int, type RSP=REQ) extends uvm_component; typedef uvm_tlm_req_rsp_channel #(REQ, RSP) this_type; typedef uvm_component_registry #(uvm_tlm_req_rsp_channel#(REQ,RSP)) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_tlm_req_rsp_channel #(REQ,RSP)"; endfunction : type_name virtual function string get_type_name(); return "uvm_tlm_req_rsp_channel #(REQ,RSP)"; endfunction : get_type_name uvm_put_export #(REQ) put_request_export; uvm_get_peek_export #(RSP) get_peek_response_export; uvm_get_peek_export #(REQ) get_peek_request_export; uvm_put_export #(RSP) put_response_export; uvm_analysis_port #(REQ) request_ap; uvm_analysis_port #(RSP) response_ap; uvm_master_imp #(REQ, RSP, this_type, uvm_tlm_fifo #(REQ), uvm_tlm_fifo #(RSP)) master_export; uvm_slave_imp #(REQ, RSP, this_type, uvm_tlm_fifo #(REQ), uvm_tlm_fifo #(RSP)) slave_export; uvm_put_export #(REQ) blocking_put_request_export, nonblocking_put_request_export; uvm_get_peek_export #(REQ) get_request_export, blocking_get_request_export, nonblocking_get_request_export, peek_request_export, blocking_peek_request_export, nonblocking_peek_request_export, blocking_get_peek_request_export, nonblocking_get_peek_request_export; uvm_put_export #(RSP) blocking_put_response_export, nonblocking_put_response_export; uvm_get_peek_export #(RSP) get_response_export, blocking_get_response_export, nonblocking_get_response_export, peek_response_export, blocking_peek_response_export, nonblocking_peek_response_export, blocking_get_peek_response_export, nonblocking_get_peek_response_export; uvm_master_imp #(REQ, RSP, this_type, uvm_tlm_fifo #(REQ), uvm_tlm_fifo #(RSP)) blocking_master_export, nonblocking_master_export; uvm_slave_imp #(REQ, RSP, this_type, uvm_tlm_fifo #(REQ), uvm_tlm_fifo #(RSP)) blocking_slave_export, nonblocking_slave_export; protected uvm_tlm_fifo #(REQ) m_request_fifo; protected uvm_tlm_fifo #(RSP) m_response_fifo; function new (string name, uvm_component parent=null, int request_fifo_size=1, int response_fifo_size=1); super.new (name, parent); m_request_fifo = new ("request_fifo", this, request_fifo_size); m_response_fifo = new ("response_fifo", this, response_fifo_size); request_ap = new ("request_ap", this); response_ap = new ("response_ap", this); put_request_export = new ("put_request_export", this); get_peek_request_export = new ("get_peek_request_export", this); put_response_export = new ("put_response_export", this); get_peek_response_export = new ("get_peek_response_export", this); master_export = new ("master_export", this, m_request_fifo, m_response_fifo); slave_export = new ("slave_export", this, m_request_fifo, m_response_fifo); create_aliased_exports(); set_report_id_action_hier(s_connection_error_id, UVM_NO_ACTION); endfunction virtual function void connect_phase(uvm_phase phase); put_request_export.connect (m_request_fifo.put_export); get_peek_request_export.connect (m_request_fifo.get_peek_export); m_request_fifo.put_ap.connect (request_ap); put_response_export.connect (m_response_fifo.put_export); get_peek_response_export.connect (m_response_fifo.get_peek_export); m_response_fifo.put_ap.connect (response_ap); endfunction function void create_aliased_exports(); blocking_put_request_export = put_request_export; nonblocking_put_request_export = put_request_export; get_request_export = get_peek_request_export; blocking_get_request_export = get_peek_request_export; nonblocking_get_request_export = get_peek_request_export; peek_request_export = get_peek_request_export; blocking_peek_request_export = get_peek_request_export; nonblocking_peek_request_export = get_peek_request_export; blocking_get_peek_request_export = get_peek_request_export; nonblocking_get_peek_request_export = get_peek_request_export; blocking_put_response_export = put_response_export; nonblocking_put_response_export = put_response_export; get_response_export = get_peek_response_export; blocking_get_response_export = get_peek_response_export; nonblocking_get_response_export = get_peek_response_export; peek_response_export = get_peek_response_export; blocking_peek_response_export = get_peek_response_export; nonblocking_peek_response_export = get_peek_response_export; blocking_get_peek_response_export = get_peek_response_export; nonblocking_get_peek_response_export = get_peek_response_export; blocking_master_export = master_export; nonblocking_master_export = master_export; blocking_slave_export = slave_export; nonblocking_slave_export = slave_export; endfunction endclass class uvm_tlm_transport_channel #(type REQ=int, type RSP=REQ) extends uvm_tlm_req_rsp_channel #(REQ, RSP); typedef uvm_component_registry #(uvm_tlm_transport_channel#(REQ,RSP)) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_tlm_transport_channel #(REQ,RSP)"; endfunction : type_name virtual function string get_type_name(); return "uvm_tlm_transport_channel #(REQ,RSP)"; endfunction : get_type_name typedef uvm_tlm_transport_channel #(REQ, RSP) this_type; uvm_transport_imp #(REQ, RSP, this_type) transport_export; function new (string name, uvm_component parent=null); super.new(name, parent, 1, 1); transport_export = new("transport_export", this); endfunction task transport (REQ request, output RSP response ); this.m_request_fifo.put( request ); this.m_response_fifo.get( response ); endtask function bit nb_transport (REQ req, output RSP rsp ); if(this.m_request_fifo.try_put(req)) return this.m_response_fifo.try_get(rsp); else return 0; endfunction endclass class uvm_seq_item_pull_port #(type REQ=int, type RSP=REQ) extends uvm_port_base #(uvm_sqr_if_base #(REQ, RSP)); function new (string name, uvm_component parent, int min_size=0, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = ((1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) | (1<<8)); endfunction virtual function string get_type_name(); return "uvm_seq_item_pull_port"; endfunction function void disable_auto_item_recording(); this.m_if.disable_auto_item_recording(); endfunction function bit is_auto_item_recording_enabled(); return this.m_if.is_auto_item_recording_enabled(); endfunction task get_next_item(output REQ t); this.m_if.get_next_item(t); endtask task try_next_item(output REQ t); this.m_if.try_next_item(t); endtask function void item_done(input RSP t = null); this.m_if.item_done(t); endfunction task wait_for_sequences(); this.m_if.wait_for_sequences(); endtask function bit has_do_available(); return this.m_if.has_do_available(); endfunction function void put_response(input RSP t); this.m_if.put_response(t); endfunction task get(output REQ t); this.m_if.get(t); endtask task peek(output REQ t); this.m_if.peek(t); endtask task put(input RSP t); this.m_if.put(t); endtask bit print_enabled; endclass class uvm_seq_item_pull_export #(type REQ=int, type RSP=REQ) extends uvm_port_base #(uvm_sqr_if_base #(REQ, RSP)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = ((1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) | (1<<8)); endfunction virtual function string get_type_name(); return "uvm_seq_item_pull_export"; endfunction function void disable_auto_item_recording(); this.m_if.disable_auto_item_recording(); endfunction function bit is_auto_item_recording_enabled(); return this.m_if.is_auto_item_recording_enabled(); endfunction task get_next_item(output REQ t); this.m_if.get_next_item(t); endtask task try_next_item(output REQ t); this.m_if.try_next_item(t); endtask function void item_done(input RSP t = null); this.m_if.item_done(t); endfunction task wait_for_sequences(); this.m_if.wait_for_sequences(); endtask function bit has_do_available(); return this.m_if.has_do_available(); endfunction function void put_response(input RSP t); this.m_if.put_response(t); endfunction task get(output REQ t); this.m_if.get(t); endtask task peek(output REQ t); this.m_if.peek(t); endtask task put(input RSP t); this.m_if.put(t); endtask endclass class uvm_seq_item_pull_imp #(type REQ=int, type RSP=REQ, type IMP=int) extends uvm_port_base #(uvm_sqr_if_base #(REQ, RSP)); local IMP m_imp; function new (string name, IMP imp); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); m_imp = imp; m_if_mask = ((1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) | (1<<8)); endfunction virtual function string get_type_name(); return "uvm_seq_item_pull_imp"; endfunction function void disable_auto_item_recording(); m_imp.disable_auto_item_recording(); endfunction function bit is_auto_item_recording_enabled(); return m_imp.is_auto_item_recording_enabled(); endfunction task get_next_item(output REQ t); m_imp.get_next_item(t); endtask task try_next_item(output REQ t); m_imp.try_next_item(t); endtask function void item_done(input RSP t = null); m_imp.item_done(t); endfunction task wait_for_sequences(); m_imp.wait_for_sequences(); endtask function bit has_do_available(); return m_imp.has_do_available(); endfunction function void put_response(input RSP t); m_imp.put_response(t); endfunction task get(output REQ t); m_imp.get(t); endtask task peek(output REQ t); m_imp.peek(t); endtask task put(input RSP t); m_imp.put(t); endtask endclass class uvm_class_pair #(type T1=int, T2=T1) extends uvm_object; typedef uvm_class_pair #(T1, T2 ) this_type; typedef uvm_object_registry #(this_type) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); this_type tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_class_pair #(T1,T2)"; endfunction : type_name virtual function string get_type_name(); return "uvm_class_pair #(T1,T2)"; endfunction : get_type_name T1 first; T2 second; function new (string name="", T1 f=null, T2 s=null); super.new(name); if (f == null) first = new; else first = f; if (s == null) second = new; else second = s; endfunction virtual function string convert2string; string s; $sformat(s, "pair : %s, %s", first.convert2string(), second.convert2string()); return s; endfunction virtual function bit do_compare(uvm_object rhs, uvm_comparer comparer); this_type rhs_; if(!$cast(rhs_,rhs)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"WRONG_TYPE")) uvm_report_error ("WRONG_TYPE", {"do_compare: rhs argument is not of type '",get_type_name(),"'"}, UVM_NONE, "t/uvm/src/comps/uvm_pair.svh", 88, "", 1); end return 0; end return first.compare(rhs_.first) && second.compare(rhs_.second); endfunction virtual function void do_copy (uvm_object rhs); this_type rhs_; if(!$cast(rhs_,rhs)) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"WRONG_TYPE")) uvm_report_fatal ("WRONG_TYPE", {"do_copy: rhs argument is not of type '",get_type_name(),"'"}, UVM_NONE, "t/uvm/src/comps/uvm_pair.svh", 97, "", 1); end first.copy(rhs_.first); second.copy(rhs_.second); endfunction endclass class uvm_built_in_pair #(type T1=int, T2=T1) extends uvm_object; typedef uvm_built_in_pair #(T1,T2) this_type; typedef uvm_object_registry #(this_type) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); this_type tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_built_in_pair #(T1,T2)"; endfunction : type_name virtual function string get_type_name(); return "uvm_built_in_pair #(T1,T2)"; endfunction : get_type_name T1 first; T2 second; function new (string name=""); super.new(name); endfunction virtual function string convert2string; return $sformatf("built-in pair : %p, %p", first, second); endfunction virtual function bit do_compare(uvm_object rhs, uvm_comparer comparer); this_type rhs_; if(!$cast(rhs_,rhs)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"WRONG_TYPE")) uvm_report_error ("WRONG_TYPE", {"do_compare: rhs argument is not of type '",get_type_name(),"'"}, UVM_NONE, "t/uvm/src/comps/uvm_pair.svh", 146, "", 1); end return 0; end return first == rhs_.first && second == rhs_.second; endfunction function void do_copy (uvm_object rhs); this_type rhs_; if(!$cast(rhs_,rhs)) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"WRONG_TYPE")) uvm_report_fatal ("WRONG_TYPE", {"do_copy: rhs argument is not of type '",get_type_name(),"'"}, UVM_NONE, "t/uvm/src/comps/uvm_pair.svh", 155, "", 1); end first = rhs_.first; second = rhs_.second; endfunction endclass class uvm_built_in_comp #(type T=int); static function bit comp(T a, T b); return a == b; endfunction endclass class uvm_built_in_converter #(type T=int); static function string convert2string(input T t); return $sformatf("%p" , t ); endfunction endclass class uvm_built_in_clone #(type T=int); static function T clone(input T from); return from; endfunction endclass class uvm_class_comp #(type T=int); static function bit comp(input T a, input T b); return a.compare(b); endfunction endclass class uvm_class_converter #(type T=int); static function string convert2string(input T t); return t.convert2string(); endfunction endclass class uvm_class_clone #(type T=int); static function uvm_object clone(input T from); return from.clone(); endfunction endclass class uvm_in_order_comparator #( type T = int , type comp_type = uvm_built_in_comp #( T ) , type convert = uvm_built_in_converter #( T ) , type pair_type = uvm_built_in_pair #( T ) ) extends uvm_component; typedef uvm_in_order_comparator #(T,comp_type,convert,pair_type) this_type; typedef uvm_component_registry #(this_type) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_in_order_comparator #(T,comp_type,convert,pair_type)"; endfunction : type_name virtual function string get_type_name(); return "uvm_in_order_comparator #(T,comp_type,convert,pair_type)"; endfunction : get_type_name uvm_analysis_export #(T) before_export; uvm_analysis_export #(T) after_export; uvm_analysis_port #(pair_type) pair_ap; local uvm_tlm_analysis_fifo #(T) m_before_fifo; local uvm_tlm_analysis_fifo #(T) m_after_fifo; int m_matches, m_mismatches; function new(string name, uvm_component parent); super.new(name, parent); before_export = new("before_export", this); after_export = new("after_export", this); pair_ap = new("pair_ap", this); m_before_fifo = new("before", this); m_after_fifo = new("after", this); m_matches = 0; m_mismatches = 0; endfunction virtual function void connect_phase(uvm_phase phase); before_export.connect(m_before_fifo.analysis_export); after_export.connect(m_after_fifo.analysis_export); endfunction virtual task run_phase(uvm_phase phase); pair_type pair; T b; T a; string s; super.run_phase(phase); forever begin m_before_fifo.get(b); m_after_fifo.get(a); if(!comp_type::comp(b, a)) begin $sformat(s, "%s differs from %s", convert::convert2string(a), convert::convert2string(b)); uvm_report_warning("Comparator Mismatch", s); m_mismatches++; end else begin s = convert::convert2string(b); uvm_report_info("Comparator Match", s); m_matches++; end pair = new("after/before"); pair.first = a; pair.second = b; pair_ap.write(pair); end endtask virtual function void flush(); m_matches = 0; m_mismatches = 0; endfunction endclass class uvm_in_order_built_in_comparator #(type T=int) extends uvm_in_order_comparator #(T); typedef uvm_in_order_built_in_comparator #(T) this_type; typedef uvm_component_registry #(this_type) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_in_order_built_in_comparator #(T)"; endfunction : type_name virtual function string get_type_name(); return "uvm_in_order_built_in_comparator #(T)"; endfunction : get_type_name function new(string name, uvm_component parent); super.new(name, parent); endfunction endclass class uvm_in_order_class_comparator #( type T = int ) extends uvm_in_order_comparator #( T , uvm_class_comp #( T ) , uvm_class_converter #( T ) , uvm_class_pair #( T, T ) ); typedef uvm_in_order_class_comparator #(T) this_type; typedef uvm_component_registry #(this_type) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_in_order_class_comparator #(T)"; endfunction : type_name virtual function string get_type_name(); return "uvm_in_order_class_comparator #(T)"; endfunction : get_type_name function new( string name , uvm_component parent); super.new( name, parent ); endfunction endclass class uvm_algorithmic_comparator #( type BEFORE=int, type AFTER=int, type TRANSFORMER=int) extends uvm_component; typedef uvm_algorithmic_comparator #( BEFORE , AFTER , TRANSFORMER ) this_type; typedef uvm_component_registry #(this_type) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_algorithmic_comparator #(BEFORE,AFTER,TRANSFORMER)"; endfunction : type_name virtual function string get_type_name(); return "uvm_algorithmic_comparator #(BEFORE,AFTER,TRANSFORMER)"; endfunction : get_type_name uvm_analysis_imp #(BEFORE, this_type) before_export; uvm_analysis_export #(AFTER) after_export; local uvm_in_order_class_comparator #(AFTER) comp; local TRANSFORMER m_transformer; function new(string name, uvm_component parent=null, TRANSFORMER transformer=null); super.new( name , parent ); m_transformer = transformer; comp = new("comp", this ); before_export = new("before_analysis_export" , this ); after_export = new("after_analysis_export" , this ); endfunction virtual function void connect_phase(uvm_phase phase); after_export.connect( comp.after_export ); endfunction function void write( input BEFORE b ); comp.before_export.write( m_transformer.transform( b ) ); endfunction endclass virtual class uvm_subscriber #(type T=int) extends uvm_component; typedef uvm_subscriber #(T) this_type; uvm_analysis_imp #(T, this_type) analysis_export; function new (string name, uvm_component parent); super.new(name, parent); analysis_export = new("analysis_imp", this); endfunction pure virtual function void write(T t); endclass virtual class uvm_monitor extends uvm_component; typedef uvm_abstract_component_registry #(uvm_monitor,"uvm_monitor") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_monitor"; endfunction : type_name virtual function string get_type_name(); return "uvm_monitor"; endfunction : get_type_name function new (string name, uvm_component parent); super.new(name, parent); endfunction endclass typedef class uvm_sequence_item; class uvm_driver #(type REQ=uvm_sequence_item, type RSP=REQ) extends uvm_component; typedef uvm_component_registry #(uvm_driver#(REQ,RSP)) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_driver #(REQ,RSP)"; endfunction : type_name virtual function string get_type_name(); return "uvm_driver #(REQ,RSP)"; endfunction : get_type_name uvm_seq_item_pull_port #(REQ, RSP) seq_item_port; uvm_seq_item_pull_port #(REQ, RSP) seq_item_prod_if; uvm_analysis_port #(RSP) rsp_port; REQ req; RSP rsp; function new (string name, uvm_component parent); super.new(name, parent); seq_item_port = new("seq_item_port", this); rsp_port = new("rsp_port", this); seq_item_prod_if = seq_item_port; endfunction virtual function void end_of_elaboration_phase(uvm_phase phase); if(seq_item_port.size<1) begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"DRVCONNECT")) uvm_report_warning ("DRVCONNECT", "the driver is not connected to a sequencer via the standard mechanisms enabled by connect()", UVM_NONE, "t/uvm/src/comps/uvm_driver.svh", 90, "", 1); end endfunction endclass class uvm_push_driver #(type REQ=uvm_sequence_item, type RSP=REQ) extends uvm_component; typedef uvm_component_registry #(uvm_push_driver#(REQ,RSP)) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_push_driver #(REQ,RSP)"; endfunction : type_name virtual function string get_type_name(); return "uvm_push_driver #(REQ,RSP)"; endfunction : get_type_name uvm_blocking_put_imp #(REQ, uvm_push_driver #(REQ,RSP)) req_export; uvm_analysis_port #(RSP) rsp_port; REQ req; RSP rsp; function new (string name, uvm_component parent); super.new(name, parent); req_export = new("req_export", this); rsp_port = new("rsp_port", this); endfunction function void check_port_connections(); if (req_export.size() != 1) uvm_report_fatal("Connection Error", $sformatf("Must connect to seq_item_port(%0d)", req_export.size()), UVM_NONE); endfunction virtual function void end_of_elaboration_phase(uvm_phase phase); super.end_of_elaboration_phase(phase); check_port_connections(); endfunction virtual task put(REQ item); uvm_report_fatal("UVM_PUSH_DRIVER", "Put task for push driver is not implemented", UVM_NONE); endtask endclass virtual class uvm_scoreboard extends uvm_component; typedef uvm_abstract_component_registry #(uvm_scoreboard,"uvm_scoreboard") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_scoreboard"; endfunction : type_name virtual function string get_type_name(); return "uvm_scoreboard"; endfunction : get_type_name function new (string name, uvm_component parent); super.new(name, parent); endfunction endclass virtual class uvm_agent extends uvm_component; uvm_active_passive_enum is_active = UVM_ACTIVE; typedef uvm_abstract_component_registry #(uvm_agent,"uvm_agent") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_agent"; endfunction : type_name virtual function string get_type_name(); return "uvm_agent"; endfunction : get_type_name function new (string name, uvm_component parent); super.new(name, parent); endfunction function void build_phase(uvm_phase phase); int active; uvm_resource_pool rp; uvm_resource_types::rsrc_q_t rq; bit found; super.build_phase(phase); rp = uvm_resource_pool::get(); rq = rp.lookup_name(get_full_name(), "is_active", null, 0); uvm_resource_pool::sort_by_precedence(rq); for (int i = 0; i < rq.size() && !found; i++) begin uvm_resource_base rsrc = rq.get(i); begin begin uvm_resource#(uvm_active_passive_enum) __tmp_rsrc__; found = $cast(__tmp_rsrc__, rsrc); if (found) begin is_active = __tmp_rsrc__.read(this); end end if (!found) begin uvm_active_passive_enum __tmp_val__; string __tmp_string_val__; bit __tmp_success_val__; begin uvm_resource#(string) __tmp_rsrc__; __tmp_success_val__ = $cast(__tmp_rsrc__, rsrc); if (__tmp_success_val__) begin __tmp_string_val__ = __tmp_rsrc__.read(this); end end if (__tmp_success_val__ && uvm_enum_wrapper#(uvm_active_passive_enum)::from_name(__tmp_string_val__, __tmp_val__)) begin is_active = __tmp_val__; found = __tmp_success_val__; end end if (!found) begin typedef bit [$bits(uvm_active_passive_enum)-1:0] __tmp_int_t__; __tmp_int_t__ __tmp_int_val__; bit __tmp_success_val__; begin begin uvm_resource#(__tmp_int_t__) __tmp_rsrc__; __tmp_success_val__ = $cast(__tmp_rsrc__, rsrc); if (__tmp_success_val__) begin __tmp_int_val__ = __tmp_rsrc__.read(this); end end if (!__tmp_success_val__) begin begin uvm_resource#(uvm_integral_t) __tmp_rsrc__; __tmp_success_val__ = $cast(__tmp_rsrc__, rsrc); if (__tmp_success_val__) begin __tmp_int_val__ = __tmp_rsrc__.read(this); end end if (!__tmp_success_val__) begin uvm_resource#(uvm_bitstream_t) __tmp_rsrc__; __tmp_success_val__ = $cast(__tmp_rsrc__, rsrc); if (__tmp_success_val__) begin __tmp_int_val__ = __tmp_rsrc__.read(this); end end if (!__tmp_success_val__) begin uvm_resource#(int) __tmp_rsrc__; __tmp_success_val__ = $cast(__tmp_rsrc__, rsrc); if (__tmp_success_val__) begin __tmp_int_val__ = __tmp_rsrc__.read(this); end end if (!__tmp_success_val__) begin uvm_resource#(int unsigned) __tmp_rsrc__; __tmp_success_val__ = $cast(__tmp_rsrc__, rsrc); if (__tmp_success_val__) begin __tmp_int_val__ = __tmp_rsrc__.read(this); end end end end if (__tmp_success_val__) begin is_active = uvm_active_passive_enum'(__tmp_int_val__); found = __tmp_success_val__; end end end end endfunction virtual function uvm_active_passive_enum get_is_active(); return is_active; endfunction endclass virtual class uvm_env extends uvm_component; typedef uvm_abstract_component_registry #(uvm_env,"uvm_env") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_env"; endfunction : type_name virtual function string get_type_name(); return "uvm_env"; endfunction : get_type_name function new (string name="env", uvm_component parent=null); super.new(name,parent); endfunction endclass virtual class uvm_test extends uvm_component; typedef uvm_abstract_component_registry #(uvm_test,"uvm_test") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_test"; endfunction : type_name virtual function string get_type_name(); return "uvm_test"; endfunction : get_type_name function new (string name, uvm_component parent); super.new(name,parent); endfunction endclass typedef class uvm_sequence_base; typedef class uvm_sequencer_base; class uvm_sequence_item extends uvm_transaction; local int m_sequence_id = -1; protected bit m_use_sequence_info; protected int m_depth = -1; protected uvm_sequencer_base m_sequencer; protected uvm_sequence_base m_parent_sequence; static bit issued1,issued2; bit print_sequence_info; function new (string name = "uvm_sequence_item"); super.new(name); endfunction function string get_type_name(); return "uvm_sequence_item"; endfunction typedef uvm_object_registry#(uvm_sequence_item,"uvm_sequence_item") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function void set_sequence_id(int id); m_sequence_id = id; endfunction function int get_sequence_id(); return (m_sequence_id); endfunction function void set_item_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer = null); set_use_sequence_info(1); if (parent_seq != null) set_parent_sequence(parent_seq); if (sequencer == null && m_parent_sequence != null) sequencer = m_parent_sequence.get_sequencer(); set_sequencer(sequencer); if (m_parent_sequence != null) set_depth(m_parent_sequence.get_depth() + 1); reseed(); endfunction function void set_use_sequence_info(bit value); m_use_sequence_info = value; endfunction function bit get_use_sequence_info(); return (m_use_sequence_info); endfunction function void set_id_info(uvm_sequence_item item); if (item == null) begin uvm_report_fatal(get_full_name(), "set_id_info called with null parameter", UVM_NONE); end this.set_transaction_id(item.get_transaction_id()); this.set_sequence_id(item.get_sequence_id()); endfunction virtual function void set_sequencer(uvm_sequencer_base sequencer); m_sequencer = sequencer; m_set_p_sequencer(); endfunction function uvm_sequencer_base get_sequencer(); return m_sequencer; endfunction function void set_parent_sequence(uvm_sequence_base parent); m_parent_sequence = parent; endfunction function uvm_sequence_base get_parent_sequence(); return (m_parent_sequence); endfunction function void set_depth(int value); m_depth = value; endfunction function int get_depth(); if (m_depth != -1) begin return (m_depth); end if (m_parent_sequence == null) begin m_depth = 1; end else begin m_depth = m_parent_sequence.get_depth() + 1; end return (m_depth); endfunction virtual function bit is_item(); return(1); endfunction function string get_full_name(); if(m_parent_sequence != null) get_full_name = {m_parent_sequence.get_full_name(), "."}; else if(m_sequencer!=null) get_full_name = {m_sequencer.get_full_name(), "."}; if(get_name() != "") get_full_name = {get_full_name, get_name()}; else begin get_full_name = {get_full_name, "_item"}; end endfunction function string get_root_sequence_name(); uvm_sequence_base root_seq; root_seq = get_root_sequence(); if (root_seq == null) return ""; else return root_seq.get_name(); endfunction virtual function void m_set_p_sequencer(); return; endfunction function uvm_sequence_base get_root_sequence(); uvm_sequence_item root_seq_base; uvm_sequence_base root_seq; root_seq_base = this; while(1) begin if(root_seq_base.get_parent_sequence()!=null) begin root_seq_base = root_seq_base.get_parent_sequence(); $cast(root_seq, root_seq_base); end else return root_seq; end endfunction function string get_sequence_path(); uvm_sequence_item this_item; string seq_path; this_item = this; seq_path = this.get_name(); while(1) begin if(this_item.get_parent_sequence()!=null) begin this_item = this_item.get_parent_sequence(); seq_path = {this_item.get_name(), ".", seq_path}; end else return seq_path; end endfunction virtual function uvm_report_object uvm_get_report_object(); if(m_sequencer == null) begin uvm_coreservice_t cs = uvm_coreservice_t::get(); return cs.get_root(); end else return m_sequencer; endfunction function int uvm_report_enabled(int verbosity, uvm_severity severity=UVM_INFO, string id=""); uvm_report_object l_report_object = uvm_get_report_object(); if (l_report_object.get_report_verbosity_level(severity, id) < verbosity) return 0; return 1; endfunction virtual function void uvm_report( uvm_severity severity, string id, string message, int verbosity = (severity == uvm_severity'(UVM_ERROR)) ? UVM_LOW : (severity == uvm_severity'(UVM_FATAL)) ? UVM_NONE : UVM_MEDIUM, string filename = "", int line = 0, string context_name = "", bit report_enabled_checked = 0); uvm_report_message l_report_message; if (report_enabled_checked == 0) begin if (!uvm_report_enabled(verbosity, severity, id)) return; end l_report_message = uvm_report_message::new_report_message(); l_report_message.set_report_message(severity, id, message, verbosity, filename, line, context_name); uvm_process_report_message(l_report_message); endfunction virtual function void uvm_report_info( string id, string message, int verbosity = UVM_MEDIUM, string filename = "", int line = 0, string context_name = "", bit report_enabled_checked = 0); this.uvm_report(UVM_INFO, id, message, verbosity, filename, line, context_name, report_enabled_checked); endfunction virtual function void uvm_report_warning( string id, string message, int verbosity = UVM_MEDIUM, string filename = "", int line = 0, string context_name = "", bit report_enabled_checked = 0); this.uvm_report(UVM_WARNING, id, message, verbosity, filename, line, context_name, report_enabled_checked); endfunction virtual function void uvm_report_error( string id, string message, int verbosity = UVM_NONE, string filename = "", int line = 0, string context_name = "", bit report_enabled_checked = 0); this.uvm_report(UVM_ERROR, id, message, verbosity, filename, line, context_name, report_enabled_checked); endfunction virtual function void uvm_report_fatal( string id, string message, int verbosity = UVM_NONE, string filename = "", int line = 0, string context_name = "", bit report_enabled_checked = 0); this.uvm_report(UVM_FATAL, id, message, verbosity, filename, line, context_name, report_enabled_checked); endfunction virtual function void uvm_process_report_message (uvm_report_message report_message); uvm_report_object l_report_object = uvm_get_report_object(); report_message.set_report_object(l_report_object); if (report_message.get_context() == "") report_message.set_context(get_sequence_path()); l_report_object.m_rh.process_report_message(report_message); endfunction function void do_print (uvm_printer printer); string temp_str0, temp_str1; int depth = get_depth(); super.do_print(printer); if(print_sequence_info || m_use_sequence_info) begin printer.print_field_int("depth", depth, $bits(depth), UVM_DEC, ".", "int"); if(m_parent_sequence != null) begin temp_str0 = m_parent_sequence.get_name(); temp_str1 = m_parent_sequence.get_full_name(); end printer.print_string("parent sequence (name)", temp_str0); printer.print_string("parent sequence (full name)", temp_str1); temp_str1 = ""; if(m_sequencer != null) begin temp_str1 = m_sequencer.get_full_name(); end printer.print_string("sequencer", temp_str1); end endfunction endclass typedef uvm_config_db#(uvm_sequence_base) uvm_config_seq; typedef class uvm_sequence_request; class uvm_sequence_process_wrapper; process pid; uvm_sequence_base seq; endclass : uvm_sequence_process_wrapper virtual class uvm_sequencer_base extends uvm_component; typedef enum {SEQ_TYPE_REQ, SEQ_TYPE_LOCK} seq_req_t; protected uvm_sequence_request arb_sequence_q[$]; protected bit arb_completed[int]; protected uvm_sequence_base lock_list[$]; protected uvm_sequence_base reg_sequences[int]; protected int m_sequencer_id; protected int m_lock_arb_size; protected int m_arb_size; protected int m_wait_for_item_sequence_id, m_wait_for_item_transaction_id; protected int m_wait_relevant_count = 0 ; protected int m_max_zero_time_wait_relevant_count = 10; protected time m_last_wait_relevant_time = 0 ; local uvm_sequencer_arb_mode m_arbitration = UVM_SEQ_ARB_FIFO; local static int g_request_id; local static int g_sequence_id = 1; local static int g_sequencer_id = 1; extern function new (string name, uvm_component parent); extern function bit is_child (uvm_sequence_base parent, uvm_sequence_base child); extern virtual function int user_priority_arbitration(int avail_sequences[$]); extern virtual task execute_item(uvm_sequence_item item); protected uvm_sequence_process_wrapper m_default_sequences[uvm_phase]; extern virtual function void start_phase_sequence(uvm_phase phase); extern virtual function void stop_phase_sequence(uvm_phase phase); extern virtual task wait_for_grant(uvm_sequence_base sequence_ptr, int item_priority = -1, bit lock_request = 0); extern virtual task wait_for_item_done(uvm_sequence_base sequence_ptr, int transaction_id); extern function bit is_blocked(uvm_sequence_base sequence_ptr); extern function bit has_lock(uvm_sequence_base sequence_ptr); extern virtual task lock(uvm_sequence_base sequence_ptr); extern virtual task grab(uvm_sequence_base sequence_ptr); extern virtual function void unlock(uvm_sequence_base sequence_ptr); extern virtual function void ungrab(uvm_sequence_base sequence_ptr); extern virtual function void stop_sequences(); extern virtual function bit is_grabbed(); extern virtual function uvm_sequence_base current_grabber(); extern virtual function bit has_do_available(); extern function void set_arbitration(UVM_SEQ_ARB_TYPE val); extern function UVM_SEQ_ARB_TYPE get_arbitration(); extern virtual task wait_for_sequences(); extern virtual function void send_request(uvm_sequence_base sequence_ptr, uvm_sequence_item t, bit rerandomize = 0); extern virtual function void set_max_zero_time_wait_relevant_count(int new_val) ; extern virtual function uvm_sequence_base get_arbitration_sequence( int index ); extern protected function void grant_queued_locks(); extern protected task m_select_sequence(); extern protected function int m_choose_next_request(); extern task m_wait_for_arbitration_completed(int request_id); extern function void m_set_arbitration_completed(int request_id); extern local task m_lock_req(uvm_sequence_base sequence_ptr, bit lock); extern function void m_unlock_req(uvm_sequence_base sequence_ptr); extern local function void remove_sequence_from_queues(uvm_sequence_base sequence_ptr); extern function void m_sequence_exiting(uvm_sequence_base sequence_ptr); extern function void kill_sequence(uvm_sequence_base sequence_ptr); extern virtual function void analysis_write(uvm_sequence_item t); extern function void do_print (uvm_printer printer); extern virtual function int m_register_sequence(uvm_sequence_base sequence_ptr); extern protected virtual function void m_unregister_sequence(int sequence_id); extern protected function uvm_sequence_base m_find_sequence(int sequence_id); extern protected function void m_update_lists(); extern function string convert2string(); extern protected virtual function int m_find_number_driver_connections(); extern protected task m_wait_arb_not_equal(); extern protected task m_wait_for_available_sequence(); extern protected function int m_get_seq_item_priority(uvm_sequence_request seq_q_entry); int m_is_relevant_completed; local bit m_auto_item_recording = 1; virtual function void disable_auto_item_recording(); m_auto_item_recording = 0; endfunction virtual function bit is_auto_item_recording_enabled(); return m_auto_item_recording; endfunction static uvm_sequencer_base all_sequencer_insts[int unsigned]; endclass function uvm_sequencer_base::new (string name, uvm_component parent); super.new(name, parent); m_sequencer_id = g_sequencer_id++; m_lock_arb_size = -1; all_sequencer_insts[m_sequencer_id]=this; endfunction function void uvm_sequencer_base::do_print (uvm_printer printer); super.do_print(printer); printer.print_array_header("arbitration_queue", arb_sequence_q.size()); foreach (arb_sequence_q[i]) printer.print_string($sformatf("[%0d]", i), $sformatf("%s@seqid%0d",arb_sequence_q[i].request.name(),arb_sequence_q[i].sequence_id), "["); printer.print_array_footer(arb_sequence_q.size()); printer.print_array_header("lock_queue", lock_list.size()); foreach(lock_list[i]) printer.print_string($sformatf("[%0d]", i), $sformatf("%s@seqid%0d",lock_list[i].get_full_name(),lock_list[i].get_sequence_id()), "["); printer.print_array_footer(lock_list.size()); endfunction function void uvm_sequencer_base::m_update_lists(); m_lock_arb_size++; endfunction function string uvm_sequencer_base::convert2string(); string s; $sformat(s, " -- arb i/id/type: "); foreach (arb_sequence_q[i]) begin $sformat(s, "%s %0d/%0d/%s ", s, i, arb_sequence_q[i].sequence_id, arb_sequence_q[i].request.name()); end $sformat(s, "%s\n -- lock_list i/id: ", s); foreach (lock_list[i]) begin $sformat(s, "%s %0d/%0d",s, i, lock_list[i].get_sequence_id()); end return(s); endfunction function int uvm_sequencer_base::m_find_number_driver_connections(); return 0; endfunction function int uvm_sequencer_base::m_register_sequence(uvm_sequence_base sequence_ptr); if (sequence_ptr.m_get_sqr_sequence_id(m_sequencer_id, 1) > 0) return sequence_ptr.get_sequence_id(); sequence_ptr.m_set_sqr_sequence_id(m_sequencer_id, g_sequence_id++); reg_sequences[sequence_ptr.get_sequence_id()] = sequence_ptr; return sequence_ptr.get_sequence_id(); endfunction function uvm_sequence_base uvm_sequencer_base::m_find_sequence(int sequence_id); uvm_sequence_base seq_ptr; int i; if (sequence_id == -1) begin if (reg_sequences.first(i)) begin return(reg_sequences[i]); end return(null); end if (!reg_sequences.exists(sequence_id)) return null; return reg_sequences[sequence_id]; endfunction function void uvm_sequencer_base::m_unregister_sequence(int sequence_id); if (!reg_sequences.exists(sequence_id)) return; reg_sequences.delete(sequence_id); endfunction function int uvm_sequencer_base::user_priority_arbitration(int avail_sequences[$]); return avail_sequences[0]; endfunction function void uvm_sequencer_base::grant_queued_locks(); begin uvm_sequence_request zombies[$]; zombies = arb_sequence_q.find(item) with (item.request==SEQ_TYPE_LOCK && item.process_id.status inside {process::KILLED,process::FINISHED}); foreach(zombies[idx]) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"SEQLCKZMB")) uvm_report_error ("SEQLCKZMB", $sformatf("The task responsible for requesting a lock on sequencer '%s' for sequence '%s' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues", this.get_full_name(), zombies[idx].sequence_ptr.get_full_name()), UVM_NONE, "t/uvm/src/seq/uvm_sequencer_base.svh", 557, "", 1); end remove_sequence_from_queues(zombies[idx].sequence_ptr); end end begin int lock_req_indices[$]; lock_req_indices = arb_sequence_q.find_first_index(item) with (item.request==SEQ_TYPE_LOCK && is_blocked(item.sequence_ptr) == 0); if(lock_req_indices.size()) begin uvm_sequence_request lock_req = arb_sequence_q[lock_req_indices[0]]; lock_list.push_back(lock_req.sequence_ptr); m_set_arbitration_completed(lock_req.request_id); arb_sequence_q.delete(lock_req_indices[0]); m_update_lists(); end end endfunction task uvm_sequencer_base::m_select_sequence(); int selected_sequence; do begin wait_for_sequences(); selected_sequence = m_choose_next_request(); if (selected_sequence == -1) begin m_wait_for_available_sequence(); end end while (selected_sequence == -1); if (selected_sequence >= 0) begin m_set_arbitration_completed(arb_sequence_q[selected_sequence].request_id); arb_sequence_q.delete(selected_sequence); m_update_lists(); end endtask function int uvm_sequencer_base::m_choose_next_request(); int i, temp; int avail_sequence_count; int sum_priority_val; int avail_sequences[$]; int highest_sequences[$]; int highest_pri; string s; avail_sequence_count = 0; grant_queued_locks(); i = 0; while (i < arb_sequence_q.size()) begin if ((arb_sequence_q[i].process_id.status == process::KILLED) || (arb_sequence_q[i].process_id.status == process::FINISHED)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"SEQREQZMB")) uvm_report_error ("SEQREQZMB", $sformatf("The task responsible for requesting a wait_for_grant on sequencer '%s' for sequence '%s' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues", this.get_full_name(), arb_sequence_q[i].sequence_ptr.get_full_name()), UVM_NONE, "t/uvm/src/seq/uvm_sequencer_base.svh", 625, "", 1); end remove_sequence_from_queues(arb_sequence_q[i].sequence_ptr); continue; end if (i < arb_sequence_q.size()) if (arb_sequence_q[i].request == SEQ_TYPE_REQ) if (is_blocked(arb_sequence_q[i].sequence_ptr) == 0) if (arb_sequence_q[i].sequence_ptr.is_relevant() == 1) begin if (m_arbitration == UVM_SEQ_ARB_FIFO) begin return i; end else avail_sequences.push_back(i); end i++; end if (m_arbitration == UVM_SEQ_ARB_FIFO) begin return -1; end if (avail_sequences.size() < 1) begin return -1; end if (avail_sequences.size() == 1) begin return avail_sequences[0]; end if (lock_list.size() > 0) begin for (i = 0; i < avail_sequences.size(); i++) begin if (is_blocked(arb_sequence_q[avail_sequences[i]].sequence_ptr) != 0) begin avail_sequences.delete(i); i--; end end if (avail_sequences.size() < 1) return -1; if (avail_sequences.size() == 1) return avail_sequences[0]; end if (m_arbitration == UVM_SEQ_ARB_WEIGHTED) begin sum_priority_val = 0; for (i = 0; i < avail_sequences.size(); i++) begin sum_priority_val += m_get_seq_item_priority(arb_sequence_q[avail_sequences[i]]); end temp = $urandom_range(sum_priority_val-1, 0); sum_priority_val = 0; for (i = 0; i < avail_sequences.size(); i++) begin if ((m_get_seq_item_priority(arb_sequence_q[avail_sequences[i]]) + sum_priority_val) > temp) begin return avail_sequences[i]; end sum_priority_val += m_get_seq_item_priority(arb_sequence_q[avail_sequences[i]]); end uvm_report_fatal("Sequencer", "UVM Internal error in weighted arbitration code", UVM_NONE); end if (m_arbitration == UVM_SEQ_ARB_RANDOM) begin i = $urandom_range(avail_sequences.size()-1, 0); return avail_sequences[i]; end if ((m_arbitration == UVM_SEQ_ARB_STRICT_FIFO) || m_arbitration == UVM_SEQ_ARB_STRICT_RANDOM) begin highest_pri = 0; for (i = 0; i < avail_sequences.size(); i++) begin if (m_get_seq_item_priority(arb_sequence_q[avail_sequences[i]]) > highest_pri) begin highest_sequences.delete(); highest_sequences.push_back(avail_sequences[i]); highest_pri = m_get_seq_item_priority(arb_sequence_q[avail_sequences[i]]); end else if (m_get_seq_item_priority(arb_sequence_q[avail_sequences[i]]) == highest_pri) begin highest_sequences.push_back(avail_sequences[i]); end end if (m_arbitration == UVM_SEQ_ARB_STRICT_FIFO) begin return(highest_sequences[0]); end i = $urandom_range(highest_sequences.size()-1, 0); return highest_sequences[i]; end if (m_arbitration == UVM_SEQ_ARB_USER) begin i = user_priority_arbitration( avail_sequences); highest_sequences = avail_sequences.find with (item == i); if (highest_sequences.size() == 0) begin uvm_report_fatal("Sequencer", $sformatf("Error in User arbitration, sequence %0d not available\n%s", i, convert2string()), UVM_NONE); end return(i); end uvm_report_fatal("Sequencer", "Internal error: Failed to choose sequence", UVM_NONE); endfunction task uvm_sequencer_base::m_wait_arb_not_equal(); wait (m_arb_size != m_lock_arb_size); endtask task uvm_sequencer_base::m_wait_for_available_sequence(); int i; int is_relevant_entries[$]; m_arb_size = m_lock_arb_size; for (i = 0; i < arb_sequence_q.size(); i++) begin if (arb_sequence_q[i].request == SEQ_TYPE_REQ) begin if (is_blocked(arb_sequence_q[i].sequence_ptr) == 0) begin if (arb_sequence_q[i].sequence_ptr.is_relevant() == 0) begin is_relevant_entries.push_back(i); end end end end if (is_relevant_entries.size() == 0) begin m_wait_arb_not_equal(); return; end fork begin fork begin fork begin m_is_relevant_completed = 0; for(i = 0; i < is_relevant_entries.size(); i++) begin fork automatic int k = i; begin arb_sequence_q[is_relevant_entries[k]].sequence_ptr.wait_for_relevant(); if ($realtime != m_last_wait_relevant_time) begin m_last_wait_relevant_time = $realtime ; m_wait_relevant_count = 0 ; end else begin m_wait_relevant_count++ ; if (m_wait_relevant_count > m_max_zero_time_wait_relevant_count) begin begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"SEQRELEVANTLOOP")) uvm_report_fatal ("SEQRELEVANTLOOP", $sformatf("Zero time loop detected, passed wait_for_relevant %0d times without time advancing",m_wait_relevant_count), UVM_NONE, "t/uvm/src/seq/uvm_sequencer_base.svh", 798, "", 1); end end end m_is_relevant_completed = 1; end join_none end wait (m_is_relevant_completed > 0); end begin m_wait_arb_not_equal(); end join_any end join_any disable fork; end join endtask function int uvm_sequencer_base::m_get_seq_item_priority(uvm_sequence_request seq_q_entry); if (seq_q_entry.item_priority != -1) begin if (seq_q_entry.item_priority <= 0) begin uvm_report_fatal("SEQITEMPRI", $sformatf("Sequence item from %s has illegal priority: %0d", seq_q_entry.sequence_ptr.get_full_name(), seq_q_entry.item_priority), UVM_NONE); end return seq_q_entry.item_priority; end if (seq_q_entry.sequence_ptr.get_priority() < 0) begin uvm_report_fatal("SEQDEFPRI", $sformatf("Sequence %s has illegal priority: %0d", seq_q_entry.sequence_ptr.get_full_name(), seq_q_entry.sequence_ptr.get_priority()), UVM_NONE); end return seq_q_entry.sequence_ptr.get_priority(); endfunction task uvm_sequencer_base::m_wait_for_arbitration_completed(int request_id); int lock_arb_size; forever begin lock_arb_size = m_lock_arb_size; if (arb_completed.exists(request_id)) begin arb_completed.delete(request_id); return; end wait (lock_arb_size != m_lock_arb_size); end endtask function void uvm_sequencer_base::m_set_arbitration_completed(int request_id); arb_completed[request_id] = 1; endfunction function bit uvm_sequencer_base::is_child (uvm_sequence_base parent, uvm_sequence_base child); uvm_sequence_base child_parent; if (child == null) begin uvm_report_fatal("uvm_sequencer", "is_child passed null child", UVM_NONE); end if (parent == null) begin uvm_report_fatal("uvm_sequencer", "is_child passed null parent", UVM_NONE); end child_parent = child.get_parent_sequence(); while (child_parent != null) begin if (child_parent.get_inst_id() == parent.get_inst_id()) begin return 1; end child_parent = child_parent.get_parent_sequence(); end return 0; endfunction class m_uvm_sqr_seq_base extends uvm_sequence_base; function new(string name="unnamed-m_uvm_sqr_seq_base"); super.new(name); endfunction : new endclass : m_uvm_sqr_seq_base task uvm_sequencer_base::execute_item(uvm_sequence_item item); m_uvm_sqr_seq_base seq; seq = new("execute_item_seq"); item.set_sequencer(this); item.set_parent_sequence(seq); seq.set_sequencer(this); seq.start_item(item); seq.finish_item(item); endtask task uvm_sequencer_base::wait_for_grant(uvm_sequence_base sequence_ptr, int item_priority = -1, bit lock_request = 0); uvm_sequence_request req_s; int my_seq_id; if (sequence_ptr == null) uvm_report_fatal("uvm_sequencer", "wait_for_grant passed null sequence_ptr", UVM_NONE); my_seq_id = m_register_sequence(sequence_ptr); if (lock_request == 1) begin req_s = new(); req_s.grant = 0; req_s.sequence_id = my_seq_id; req_s.request = SEQ_TYPE_LOCK; req_s.sequence_ptr = sequence_ptr; req_s.request_id = g_request_id++; req_s.process_id = process::self(); arb_sequence_q.push_back(req_s); end req_s = new(); req_s.grant = 0; req_s.request = SEQ_TYPE_REQ; req_s.sequence_id = my_seq_id; req_s.item_priority = item_priority; req_s.sequence_ptr = sequence_ptr; req_s.request_id = g_request_id++; req_s.process_id = process::self(); arb_sequence_q.push_back(req_s); m_update_lists(); m_wait_for_arbitration_completed(req_s.request_id); req_s.sequence_ptr.m_wait_for_grant_semaphore++; endtask task uvm_sequencer_base::wait_for_item_done(uvm_sequence_base sequence_ptr, int transaction_id); int sequence_id; sequence_id = sequence_ptr.m_get_sqr_sequence_id(m_sequencer_id, 1); m_wait_for_item_sequence_id = -1; m_wait_for_item_transaction_id = -1; if (transaction_id == -1) wait (m_wait_for_item_sequence_id == sequence_id); else wait ((m_wait_for_item_sequence_id == sequence_id && m_wait_for_item_transaction_id == transaction_id)); endtask function bit uvm_sequencer_base::is_blocked(uvm_sequence_base sequence_ptr); if (sequence_ptr == null) uvm_report_fatal("uvm_sequence_controller", "is_blocked passed null sequence_ptr", UVM_NONE); foreach (lock_list[i]) begin if ((lock_list[i].get_inst_id() != sequence_ptr.get_inst_id()) && (is_child(lock_list[i], sequence_ptr) == 0)) begin return 1; end end return 0; endfunction function bit uvm_sequencer_base::has_lock(uvm_sequence_base sequence_ptr); int my_seq_id; if (sequence_ptr == null) uvm_report_fatal("uvm_sequence_controller", "has_lock passed null sequence_ptr", UVM_NONE); my_seq_id = m_register_sequence(sequence_ptr); foreach (lock_list[i]) begin if (lock_list[i].get_inst_id() == sequence_ptr.get_inst_id()) begin return 1; end end return 0; endfunction task uvm_sequencer_base::m_lock_req(uvm_sequence_base sequence_ptr, bit lock); int my_seq_id; uvm_sequence_request new_req; if (sequence_ptr == null) uvm_report_fatal("uvm_sequence_controller", "lock_req passed null sequence_ptr", UVM_NONE); my_seq_id = m_register_sequence(sequence_ptr); new_req = new(); new_req.grant = 0; new_req.sequence_id = sequence_ptr.get_sequence_id(); new_req.request = SEQ_TYPE_LOCK; new_req.sequence_ptr = sequence_ptr; new_req.request_id = g_request_id++; new_req.process_id = process::self(); if (lock == 1) begin arb_sequence_q.push_back(new_req); end else begin arb_sequence_q.push_front(new_req); m_update_lists(); end grant_queued_locks(); m_wait_for_arbitration_completed(new_req.request_id); endtask function void uvm_sequencer_base::m_unlock_req(uvm_sequence_base sequence_ptr); if (sequence_ptr == null) begin uvm_report_fatal("uvm_sequencer", "m_unlock_req passed null sequence_ptr", UVM_NONE); end begin int q[$]; int seqid=sequence_ptr.get_inst_id(); q=lock_list.find_first_index(item) with (item.get_inst_id() == seqid); if(q.size()==1) begin lock_list.delete(q[0]); grant_queued_locks(); m_update_lists(); end else uvm_report_warning("SQRUNL", {"Sequence '", sequence_ptr.get_full_name(), "' called ungrab / unlock, but didn't have lock"}, UVM_NONE); end endfunction task uvm_sequencer_base::lock(uvm_sequence_base sequence_ptr); m_lock_req(sequence_ptr, 1); endtask task uvm_sequencer_base::grab(uvm_sequence_base sequence_ptr); m_lock_req(sequence_ptr, 0); endtask function void uvm_sequencer_base::unlock(uvm_sequence_base sequence_ptr); m_unlock_req(sequence_ptr); endfunction function void uvm_sequencer_base::ungrab(uvm_sequence_base sequence_ptr); m_unlock_req(sequence_ptr); endfunction function void uvm_sequencer_base::remove_sequence_from_queues( uvm_sequence_base sequence_ptr); int i; int seq_id; seq_id = sequence_ptr.m_get_sqr_sequence_id(m_sequencer_id, 0); i = 0; do begin if (arb_sequence_q.size() > i) begin if ((arb_sequence_q[i].sequence_id == seq_id) || (is_child(sequence_ptr, arb_sequence_q[i].sequence_ptr))) begin if (sequence_ptr.get_sequence_state() == UVM_FINISHED) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"SEQFINERR")) uvm_report_error ("SEQFINERR", $sformatf("Parent sequence '%s' should not finish before all items from itself and items from descendent sequences are processed. The item request from the sequence '%s' is being removed.", sequence_ptr.get_full_name(), arb_sequence_q[i].sequence_ptr.get_full_name()), UVM_NONE, "t/uvm/src/seq/uvm_sequencer_base.svh", 1153, "", 1); end arb_sequence_q.delete(i); m_update_lists(); end else begin i++; end end end while (i < arb_sequence_q.size()); i = 0; do begin if (lock_list.size() > i) begin if ((lock_list[i].get_inst_id() == sequence_ptr.get_inst_id()) || (is_child(sequence_ptr, lock_list[i]))) begin if (sequence_ptr.get_sequence_state() == UVM_FINISHED) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"SEQFINERR")) uvm_report_error ("SEQFINERR", $sformatf("Parent sequence '%s' should not finish before locks from itself and descedent sequences are removed. The lock held by the child sequence '%s' is being removed.",sequence_ptr.get_full_name(), lock_list[i].get_full_name()), UVM_NONE, "t/uvm/src/seq/uvm_sequencer_base.svh", 1172, "", 1); end lock_list.delete(i); m_update_lists(); end else begin i++; end end end while (i < lock_list.size()); m_unregister_sequence(sequence_ptr.m_get_sqr_sequence_id(m_sequencer_id, 1)); endfunction function void uvm_sequencer_base::stop_sequences(); uvm_sequence_base seq_ptr; seq_ptr = m_find_sequence(-1); while (seq_ptr != null) begin kill_sequence(seq_ptr); seq_ptr = m_find_sequence(-1); end endfunction function void uvm_sequencer_base::m_sequence_exiting(uvm_sequence_base sequence_ptr); remove_sequence_from_queues(sequence_ptr); endfunction function void uvm_sequencer_base::kill_sequence(uvm_sequence_base sequence_ptr); remove_sequence_from_queues(sequence_ptr); sequence_ptr.m_kill(); endfunction function bit uvm_sequencer_base::is_grabbed(); return (lock_list.size() != 0); endfunction function uvm_sequence_base uvm_sequencer_base::current_grabber(); if (lock_list.size() == 0) begin return null; end return lock_list[lock_list.size()-1]; endfunction function bit uvm_sequencer_base::has_do_available(); foreach (arb_sequence_q[i]) begin if ((arb_sequence_q[i].sequence_ptr.is_relevant() == 1) && (is_blocked(arb_sequence_q[i].sequence_ptr) == 0)) begin return 1; end end return 0; endfunction function void uvm_sequencer_base::set_arbitration(UVM_SEQ_ARB_TYPE val); m_arbitration = val; endfunction function UVM_SEQ_ARB_TYPE uvm_sequencer_base::get_arbitration(); return m_arbitration; endfunction function uvm_sequence_base uvm_sequencer_base::get_arbitration_sequence( int index); return arb_sequence_q[index].sequence_ptr; endfunction function void uvm_sequencer_base::analysis_write(uvm_sequence_item t); return; endfunction task uvm_sequencer_base::wait_for_sequences(); uvm_wait_for_nba_region(); endtask function void uvm_sequencer_base::send_request(uvm_sequence_base sequence_ptr, uvm_sequence_item t, bit rerandomize = 0); return; endfunction function void uvm_sequencer_base::set_max_zero_time_wait_relevant_count(int new_val) ; m_max_zero_time_wait_relevant_count = new_val ; endfunction function void uvm_sequencer_base::start_phase_sequence(uvm_phase phase); uvm_resource_pool rp = uvm_resource_pool::get(); uvm_resource_types::rsrc_q_t rq; uvm_sequence_base seq; uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory f = cs.get_factory(); rq = rp.lookup_name({get_full_name(), ".", phase.get_name(), "_phase"}, "default_sequence", null, 0); uvm_resource_pool::sort_by_precedence(rq); for (int i = 0; seq == null && i < rq.size(); i++) begin uvm_resource_base rsrc = rq.get(i); uvm_resource#(uvm_sequence_base) sbr; uvm_resource#(uvm_object_wrapper) owr; if ($cast(sbr, rsrc) && sbr != null) begin seq = sbr.read(this); if (seq == null) begin begin if (uvm_report_enabled(UVM_FULL,UVM_INFO,"UVM/SQR/PH/DEF/SB/NULL")) uvm_report_info ("UVM/SQR/PH/DEF/SB/NULL", {"Default phase sequence for phase '", phase.get_name(),"' explicitly disabled"}, UVM_FULL, "t/uvm/src/seq/uvm_sequencer_base.svh", 1341, "", 1); end return; end end else if ($cast(owr, rsrc) && owr != null) begin uvm_object_wrapper wrapper; wrapper = owr.read(this); if (wrapper == null) begin begin if (uvm_report_enabled(UVM_FULL,UVM_INFO,"UVM/SQR/PH/DEF/OW/NULL")) uvm_report_info ("UVM/SQR/PH/DEF/OW/NULL", {"Default phase sequence for phase '", phase.get_name(),"' explicitly disabled"}, UVM_FULL, "t/uvm/src/seq/uvm_sequencer_base.svh", 1353, "", 1); end return; end if (!$cast(seq, f.create_object_by_type(wrapper, get_full_name(), wrapper.get_type_name())) || seq == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"PHASESEQ")) uvm_report_warning ("PHASESEQ", {"Default sequence for phase '", phase.get_name(),"' %s is not a sequence type"}, UVM_NONE, "t/uvm/src/seq/uvm_sequencer_base.svh", 1361, "", 1); end return; end end end if (seq == null) begin begin if (uvm_report_enabled(UVM_FULL,UVM_INFO,"PHASESEQ")) uvm_report_info ("PHASESEQ", {"No default phase sequence for phase '", phase.get_name(),"'"}, UVM_FULL, "t/uvm/src/seq/uvm_sequencer_base.svh", 1369, "", 1); end return; end begin if (uvm_report_enabled(UVM_FULL,UVM_INFO,"PHASESEQ")) uvm_report_info ("PHASESEQ", {"Starting default sequence '", seq.get_type_name(),"' for phase '", phase.get_name(),"'"}, UVM_FULL, "t/uvm/src/seq/uvm_sequencer_base.svh", 1374, "", 1); end seq.print_sequence_info = 1; seq.set_sequencer(this); seq.reseed(); seq.set_starting_phase(phase); if (seq.get_randomize_enabled() && !seq.randomize()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"STRDEFSEQ")) uvm_report_warning ("STRDEFSEQ", {"Randomization failed for default sequence '", seq.get_type_name(),"' for phase '", phase.get_name(),"'"}, UVM_NONE, "t/uvm/src/seq/uvm_sequencer_base.svh", 1383, "", 1); end return; end fork begin uvm_sequence_process_wrapper w = new(); w.pid = process::self(); w.seq = seq; w.pid.srandom(uvm_create_random_seed(seq.get_type_name(), this.get_full_name())); m_default_sequences[phase] = w; seq.start(this); m_default_sequences.delete(phase); end join_none endfunction function void uvm_sequencer_base::stop_phase_sequence(uvm_phase phase); if (m_default_sequences.exists(phase)) begin begin if (uvm_report_enabled(UVM_FULL,UVM_INFO,"PHASESEQ")) uvm_report_info ("PHASESEQ", {"Killing default sequence '", m_default_sequences[phase].seq.get_type_name(), "' for phase '", phase.get_name(), "'"}, UVM_FULL, "t/uvm/src/seq/uvm_sequencer_base.svh", 1409, "", 1); end m_default_sequences[phase].seq.kill(); end else begin begin if (uvm_report_enabled(UVM_FULL,UVM_INFO,"PHASESEQ")) uvm_report_info ("PHASESEQ", {"No default sequence to kill for phase '", phase.get_name(), "'"}, UVM_FULL, "t/uvm/src/seq/uvm_sequencer_base.svh", 1415, "", 1); end end endfunction : stop_phase_sequence class uvm_sequence_request; bit grant; int sequence_id; int request_id; int item_priority; process process_id; uvm_sequencer_base::seq_req_t request; uvm_sequence_base sequence_ptr; endclass class uvm_sequencer_analysis_fifo #(type RSP = uvm_sequence_item) extends uvm_tlm_fifo #(RSP); uvm_analysis_imp #(RSP, uvm_sequencer_analysis_fifo #(RSP)) analysis_export; uvm_sequencer_base sequencer_ptr; function new (string name, uvm_component parent = null); super.new(name, parent, 0); analysis_export = new ("analysis_export", this); endfunction function void write(input RSP t); if (sequencer_ptr == null) uvm_report_fatal ("SEQRNULL", "The sequencer pointer is null when attempting a write", UVM_NONE); sequencer_ptr.analysis_write(t); endfunction endclass virtual class uvm_sequencer_param_base #(type REQ = uvm_sequence_item, type RSP = REQ) extends uvm_sequencer_base; typedef uvm_sequencer_param_base #( REQ , RSP) this_type; typedef REQ req_type; typedef RSP rsp_type; REQ m_last_req_buffer[$]; RSP m_last_rsp_buffer[$]; protected int m_num_last_reqs = 1; protected int num_last_items = m_num_last_reqs; protected int m_num_last_rsps = 1; protected int m_num_reqs_sent; protected int m_num_rsps_received; uvm_sequencer_analysis_fifo #(RSP) sqr_rsp_analysis_fifo; extern function new (string name, uvm_component parent); extern virtual function void send_request(uvm_sequence_base sequence_ptr, uvm_sequence_item t, bit rerandomize = 0); function REQ get_current_item(); REQ t; if (m_req_fifo.try_peek(t) == 0) return null; return t; endfunction extern function int get_num_reqs_sent(); extern function void set_num_last_reqs(int unsigned max); extern function int unsigned get_num_last_reqs(); function REQ last_req(int unsigned n = 0); if(n > m_num_last_reqs) begin uvm_report_warning("HSTOB", $sformatf("Invalid last access (%0d), the max history is %0d", n, m_num_last_reqs)); return null; end if(n == m_last_req_buffer.size()) return null; return m_last_req_buffer[n]; endfunction uvm_analysis_export #(RSP) rsp_export; extern function int get_num_rsps_received(); extern function void set_num_last_rsps(int unsigned max); extern function int unsigned get_num_last_rsps(); function RSP last_rsp(int unsigned n = 0); if(n > m_num_last_rsps) begin uvm_report_warning("HSTOB", $sformatf("Invalid last access (%0d), the max history is %0d", n, m_num_last_rsps)); return null; end if(n == m_last_rsp_buffer.size()) return null; return m_last_rsp_buffer[n]; endfunction extern function void m_last_rsp_push_front(RSP item); extern function void put_response (RSP t); extern virtual function void build_phase(uvm_phase phase); extern virtual function void connect_phase(uvm_phase phase); extern virtual function void do_print (uvm_printer printer); extern virtual function void analysis_write(uvm_sequence_item t); extern function void m_last_req_push_front(REQ item); uvm_tlm_fifo #(REQ) m_req_fifo; endclass function uvm_sequencer_param_base::new (string name, uvm_component parent); super.new(name, parent); rsp_export = new("rsp_export", this); sqr_rsp_analysis_fifo = new("sqr_rsp_analysis_fifo", this); sqr_rsp_analysis_fifo.print_enabled = 0; m_req_fifo = new("req_fifo", this); m_req_fifo.print_enabled = 0; endfunction function void uvm_sequencer_param_base::do_print (uvm_printer printer); super.do_print(printer); printer.print_field_int("num_last_reqs", m_num_last_reqs, $bits(m_num_last_reqs), UVM_DEC); printer.print_field_int("num_last_rsps", m_num_last_rsps, $bits(m_num_last_rsps), UVM_DEC); endfunction function void uvm_sequencer_param_base::connect_phase(uvm_phase phase); super.connect_phase(phase); rsp_export.connect(sqr_rsp_analysis_fifo.analysis_export); endfunction function void uvm_sequencer_param_base::build_phase(uvm_phase phase); super.build_phase(phase); sqr_rsp_analysis_fifo.sequencer_ptr = this; endfunction function void uvm_sequencer_param_base::send_request(uvm_sequence_base sequence_ptr, uvm_sequence_item t, bit rerandomize = 0); REQ param_t; if (sequence_ptr == null) begin uvm_report_fatal("SNDREQ", "Send request sequence_ptr is null", UVM_NONE); end if (sequence_ptr.m_wait_for_grant_semaphore < 1) begin uvm_report_fatal("SNDREQ", "Send request called without wait_for_grant", UVM_NONE); end sequence_ptr.m_wait_for_grant_semaphore--; if ($cast(param_t, t)) begin if (rerandomize == 1) begin if (!param_t.randomize()) begin uvm_report_warning("SQRSNDREQ", "Failed to rerandomize sequence item in send_request"); end end if (param_t.get_transaction_id() == -1) begin param_t.set_transaction_id(sequence_ptr.m_next_transaction_id++); end m_last_req_push_front(param_t); end else begin uvm_report_fatal("SQRSNDREQCAST",$sformatf("send_request failed to cast sequence item"), UVM_NONE); end param_t.set_sequence_id(sequence_ptr.m_get_sqr_sequence_id(m_sequencer_id, 1)); t.set_sequencer(this); if (m_req_fifo.try_put(param_t) != 1) begin uvm_report_fatal("SQRSNDREQGNI", "Concurrent calls to get_next_item() not supported. Consider using a semaphore to ensure that concurrent processes take turns in the driver", UVM_NONE); end m_num_reqs_sent++; grant_queued_locks(); endfunction function void uvm_sequencer_param_base::put_response (RSP t); uvm_sequence_base sequence_ptr; if (t == null) begin uvm_report_fatal("SQRPUT", "Driver put a null response", UVM_NONE); end m_last_rsp_push_front(t); m_num_rsps_received++; if (t.get_sequence_id() == -1) begin uvm_report_fatal("SQRPUT", "Driver put a response with null sequence_id", UVM_NONE); return; end sequence_ptr = m_find_sequence(t.get_sequence_id()); if (sequence_ptr != null) begin if (sequence_ptr.get_use_response_handler() == 1) begin sequence_ptr.response_handler(t); return; end sequence_ptr.put_response(t); end else begin uvm_report_warning("Sequencer", $sformatf("Dropping response for sequence %0d, sequence not found. Probable cause: sequence exited or has been killed", t.get_sequence_id())); end endfunction function void uvm_sequencer_param_base::analysis_write(uvm_sequence_item t); RSP response; if (!$cast(response, t)) begin uvm_report_fatal("ANALWRT", "Failure to cast analysis port write item", UVM_NONE); end put_response(response); endfunction function int uvm_sequencer_param_base::get_num_reqs_sent(); return m_num_reqs_sent; endfunction function int uvm_sequencer_param_base::get_num_rsps_received(); return m_num_rsps_received; endfunction function void uvm_sequencer_param_base::set_num_last_reqs(int unsigned max); if(max > 1024) begin uvm_report_warning("HSTOB", $sformatf("Invalid last size; 1024 is the maximum and will be used")); max = 1024; end while((m_last_req_buffer.size() != 0) && (m_last_req_buffer.size() > max)) void'(m_last_req_buffer.pop_back()); m_num_last_reqs = max; num_last_items = max; endfunction function int unsigned uvm_sequencer_param_base::get_num_last_reqs(); return m_num_last_reqs; endfunction function void uvm_sequencer_param_base::m_last_req_push_front(REQ item); if(!m_num_last_reqs) return; if(m_last_req_buffer.size() == m_num_last_reqs) void'(m_last_req_buffer.pop_back()); this.m_last_req_buffer.push_front(item); endfunction function void uvm_sequencer_param_base::set_num_last_rsps(int unsigned max); if(max > 1024) begin uvm_report_warning("HSTOB", $sformatf("Invalid last size; 1024 is the maximum and will be used")); max = 1024; end while((m_last_rsp_buffer.size() != 0) && (m_last_rsp_buffer.size() > max)) begin void'(m_last_rsp_buffer.pop_back()); end m_num_last_rsps = max; endfunction function int unsigned uvm_sequencer_param_base::get_num_last_rsps(); return m_num_last_rsps; endfunction function void uvm_sequencer_param_base::m_last_rsp_push_front(RSP item); if(!m_num_last_rsps) return; if(m_last_rsp_buffer.size() == m_num_last_rsps) void'(m_last_rsp_buffer.pop_back()); this.m_last_rsp_buffer.push_front(item); endfunction class uvm_sequencer #(type REQ=uvm_sequence_item, RSP=REQ) extends uvm_sequencer_param_base #(REQ, RSP); typedef uvm_sequencer #( REQ , RSP) this_type; bit sequence_item_requested; bit get_next_item_called; typedef uvm_component_registry #(this_type) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction extern function new (string name, uvm_component parent=null); extern virtual function void stop_sequences(); extern virtual function string get_type_name(); uvm_seq_item_pull_imp #(REQ, RSP, this_type) seq_item_export; extern virtual task get_next_item (output REQ t); extern virtual task try_next_item (output REQ t); extern virtual function void item_done (RSP item = null); extern virtual task put (RSP t); extern task get (output REQ t); extern task peek (output REQ t); extern function void item_done_trigger(RSP item = null); function RSP item_done_get_trigger_data(); return last_rsp(0); endfunction extern protected virtual function int m_find_number_driver_connections(); endclass typedef uvm_sequencer #(uvm_sequence_item) uvm_virtual_sequencer; function uvm_sequencer::new (string name, uvm_component parent=null); super.new(name, parent); seq_item_export = new ("seq_item_export", this); endfunction function void uvm_sequencer::stop_sequences(); REQ t; super.stop_sequences(); sequence_item_requested = 0; get_next_item_called = 0; if (m_req_fifo.used()) begin uvm_report_info(get_full_name(), "Sequences stopped. Removing request from sequencer fifo"); m_req_fifo.flush(); end endfunction function string uvm_sequencer::get_type_name(); return "uvm_sequencer"; endfunction function int uvm_sequencer::m_find_number_driver_connections(); uvm_port_base #(uvm_sqr_if_base #(REQ, RSP)) provided_to_port_list[string]; seq_item_export.get_provided_to(provided_to_port_list); return provided_to_port_list.num(); endfunction task uvm_sequencer::get_next_item(output REQ t); REQ req_item; if (get_next_item_called == 1) uvm_report_error(get_full_name(), "Get_next_item called twice without item_done or get in between", UVM_NONE); if (!sequence_item_requested) m_select_sequence(); sequence_item_requested = 1; get_next_item_called = 1; m_req_fifo.peek(t); endtask task uvm_sequencer::try_next_item(output REQ t); int selected_sequence; time arb_time; uvm_sequence_base seq; if (get_next_item_called == 1) begin uvm_report_error(get_full_name(), "get_next_item/try_next_item called twice without item_done or get in between", UVM_NONE); return; end wait_for_sequences(); selected_sequence = m_choose_next_request(); if (selected_sequence == -1) begin t = null; return; end m_set_arbitration_completed(arb_sequence_q[selected_sequence].request_id); seq = arb_sequence_q[selected_sequence].sequence_ptr; arb_sequence_q.delete(selected_sequence); m_update_lists(); sequence_item_requested = 1; get_next_item_called = 1; wait_for_sequences(); if (!m_req_fifo.try_peek(t)) uvm_report_error("TRY_NEXT_BLOCKED", {"try_next_item: the selected sequence '", seq.get_full_name(), "' did not produce an item within an NBA delay. ", "Sequences should not consume time between calls to start_item and finish_item. ", "Returning null item."}, UVM_NONE); endtask function void uvm_sequencer::item_done(RSP item = null); REQ t; sequence_item_requested = 0; get_next_item_called = 0; if (m_req_fifo.try_get(t) == 0) begin uvm_report_fatal("SQRBADITMDN", {"Item_done() called with no outstanding requests.", " Each call to item_done() must be paired with a previous call to get_next_item()."}); end else begin m_wait_for_item_sequence_id = t.get_sequence_id(); m_wait_for_item_transaction_id = t.get_transaction_id(); end if (item != null) begin seq_item_export.put_response(item); end grant_queued_locks(); endfunction task uvm_sequencer::put (RSP t); put_response(t); endtask task uvm_sequencer::get(output REQ t); if (sequence_item_requested == 0) begin m_select_sequence(); end sequence_item_requested = 1; m_req_fifo.peek(t); item_done(); endtask task uvm_sequencer::peek(output REQ t); if (sequence_item_requested == 0) begin m_select_sequence(); end sequence_item_requested = 1; m_req_fifo.peek(t); endtask function void uvm_sequencer::item_done_trigger(RSP item = null); item_done(item); endfunction class uvm_push_sequencer #(type REQ=uvm_sequence_item, RSP=REQ) extends uvm_sequencer_param_base #(REQ, RSP); typedef uvm_push_sequencer #( REQ , RSP) this_type; uvm_blocking_put_port #(REQ) req_port; function new (string name, uvm_component parent=null); super.new(name, parent); req_port = new ("req_port", this); endfunction task run_phase(uvm_phase phase); REQ t; int selected_sequence; fork super.run_phase(phase); forever begin m_select_sequence(); m_req_fifo.get(t); req_port.put(t); m_wait_for_item_sequence_id = t.get_sequence_id(); m_wait_for_item_transaction_id = t.get_transaction_id(); end join endtask protected virtual function int m_find_number_driver_connections(); return req_port.size(); endfunction endclass virtual class uvm_sequence_base extends uvm_sequence_item; typedef uvm_abstract_object_registry#(uvm_sequence_base,"uvm_sequence_base") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_sequence_base"; endfunction : type_name virtual function string get_type_name(); return "uvm_sequence_base"; endfunction : get_type_name protected uvm_sequence_state m_sequence_state; int m_next_transaction_id = 1; local int m_priority = -1; uvm_recorder m_tr_recorder; int m_wait_for_grant_semaphore; protected int m_sqr_seq_ids[int]; protected bit children_array[uvm_sequence_base]; protected uvm_sequence_item response_queue[$]; protected int response_queue_depth = 8; protected bit response_queue_error_report_enabled; local bit do_not_randomize; protected process m_sequence_process; local bit m_use_response_handler; local bit is_rel_default; local bit wait_rel_default; function new (string name = "uvm_sequence"); super.new(name); m_sequence_state = UVM_CREATED; m_wait_for_grant_semaphore = 0; m_init_phase_daps(1); endfunction virtual function bit get_randomize_enabled(); return (do_not_randomize == 0); endfunction : get_randomize_enabled virtual function void set_randomize_enabled(bit enable); do_not_randomize = !enable; endfunction : set_randomize_enabled virtual function bit is_item(); return 0; endfunction function uvm_sequence_state_enum get_sequence_state(); return m_sequence_state; endfunction task wait_for_sequence_state(int unsigned state_mask); wait (m_sequence_state & state_mask); endtask function int get_tr_handle(); if (m_tr_recorder != null) return m_tr_recorder.get_handle(); else return 0; endfunction virtual task start (uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence = null, int this_priority = -1, bit call_pre_post = 1); bit old_automatic_phase_objection; set_item_context(parent_sequence, sequencer); if (!(m_sequence_state inside {UVM_CREATED,UVM_STOPPED,UVM_FINISHED})) begin uvm_report_fatal("SEQ_NOT_DONE", {"Sequence ", get_full_name(), " already started"},UVM_NONE); end if (m_parent_sequence != null) begin m_parent_sequence.children_array[this] = 1; end if (this_priority < -1) begin uvm_report_fatal("SEQPRI", $sformatf("Sequence %s start has illegal priority: %0d", get_full_name(), this_priority), UVM_NONE); end if (this_priority < 0) begin if (parent_sequence == null) this_priority = 100; else this_priority = parent_sequence.get_priority(); end clear_response_queue(); m_priority = this_priority; if (m_sequencer != null) begin int handle; if (m_parent_sequence == null) begin handle = m_sequencer.begin_tr(this, get_name()); m_tr_recorder = uvm_recorder::get_recorder_from_handle(handle); end else begin handle = m_sequencer.begin_tr(.tr(this), .stream_name(get_root_sequence_name()), .parent_handle((m_parent_sequence.m_tr_recorder == null) ? 0 : m_parent_sequence.m_tr_recorder.get_handle())); m_tr_recorder = uvm_recorder::get_recorder_from_handle(handle); end end set_sequence_id(-1); if (m_sequencer != null) begin void'(m_sequencer.m_register_sequence(this)); end m_sequence_state = UVM_PRE_START; fork begin m_sequence_process = process::self(); #0; if (get_automatic_phase_objection()) begin m_safe_raise_starting_phase("automatic phase objection"); end pre_start(); if (call_pre_post == 1) begin m_sequence_state = UVM_PRE_BODY; #0; pre_body(); end if (parent_sequence != null) begin parent_sequence.pre_do(0); parent_sequence.mid_do(this); end m_sequence_state = UVM_BODY; #0; body(); m_sequence_state = UVM_ENDED; #0; if (parent_sequence != null) begin parent_sequence.post_do(this); end if (call_pre_post == 1) begin m_sequence_state = UVM_POST_BODY; #0; post_body(); end m_sequence_state = UVM_POST_START; #0; post_start(); if (get_automatic_phase_objection()) begin m_safe_drop_starting_phase("automatic phase objection"); end m_sequence_state = UVM_FINISHED; #0; end join if (m_sequencer != null) begin m_sequencer.end_tr(this); end if (m_sequence_state != UVM_STOPPED) begin clean_exit_sequence(); end #0; if ((m_parent_sequence != null) && (m_parent_sequence.children_array.exists(this))) begin m_parent_sequence.children_array.delete(this); end old_automatic_phase_objection = get_automatic_phase_objection(); m_init_phase_daps(1); set_automatic_phase_objection(old_automatic_phase_objection); endtask function void clean_exit_sequence(); if (m_sequencer != null) m_sequencer.m_sequence_exiting(this); else foreach(m_sqr_seq_ids[seqrID]) begin uvm_sequencer_base s = uvm_sequencer_base::all_sequencer_insts[seqrID]; s.m_sequence_exiting(this); end m_sqr_seq_ids.delete(); endfunction virtual task pre_start(); return; endtask virtual task pre_body(); return; endtask virtual task pre_do(bit is_item); return; endtask virtual function void mid_do(uvm_sequence_item this_item); return; endfunction virtual task body(); uvm_report_warning("uvm_sequence_base", "Body definition undefined"); return; endtask virtual function void post_do(uvm_sequence_item this_item); return; endfunction virtual task post_body(); return; endtask virtual task post_start(); return; endtask local uvm_get_to_lock_dap#(bit) m_automatic_phase_objection_dap; local uvm_get_to_lock_dap#(uvm_phase) m_starting_phase_dap; function void m_init_phase_daps(bit create); string apo_name = $sformatf("%s.automatic_phase_objection", get_full_name()); string sp_name = $sformatf("%s.starting_phase", get_full_name()); if (create) begin m_automatic_phase_objection_dap = uvm_get_to_lock_dap#(bit)::type_id::create(apo_name, get_sequencer()); m_starting_phase_dap = uvm_get_to_lock_dap#(uvm_phase)::type_id::create(sp_name, get_sequencer()); end else begin m_automatic_phase_objection_dap.set_name(apo_name); m_starting_phase_dap.set_name(sp_name); end endfunction : m_init_phase_daps function uvm_phase get_starting_phase(); return m_starting_phase_dap.get(); endfunction : get_starting_phase function void set_starting_phase(uvm_phase phase); m_starting_phase_dap.set(phase); endfunction : set_starting_phase function void set_automatic_phase_objection(bit value); m_automatic_phase_objection_dap.set(value); endfunction : set_automatic_phase_objection function bit get_automatic_phase_objection(); return m_automatic_phase_objection_dap.get(); endfunction : get_automatic_phase_objection function void m_safe_raise_starting_phase(string description = "", int count = 1); uvm_phase starting_phase = get_starting_phase(); if (starting_phase != null) starting_phase.raise_objection(this, description, count); endfunction : m_safe_raise_starting_phase function void m_safe_drop_starting_phase(string description = "", int count = 1); uvm_phase starting_phase = get_starting_phase(); if (starting_phase != null) starting_phase.drop_objection(this, description, count); endfunction : m_safe_drop_starting_phase function void set_priority (int value); m_priority = value; endfunction function int get_priority(); return m_priority; endfunction virtual function bit is_relevant(); is_rel_default = 1; return 1; endfunction virtual task wait_for_relevant(); event e; wait_rel_default = 1; if (is_rel_default != wait_rel_default) uvm_report_fatal("RELMSM", "is_relevant() was implemented without defining wait_for_relevant()", UVM_NONE); @e; endtask task lock(uvm_sequencer_base sequencer = null); if (sequencer == null) sequencer = m_sequencer; if (sequencer == null) uvm_report_fatal("LOCKSEQR", "Null m_sequencer reference", UVM_NONE); sequencer.lock(this); endtask task grab(uvm_sequencer_base sequencer = null); if (sequencer == null) begin if (m_sequencer == null) begin uvm_report_fatal("GRAB", "Null m_sequencer reference", UVM_NONE); end m_sequencer.grab(this); end else begin sequencer.grab(this); end endtask function void unlock(uvm_sequencer_base sequencer = null); if (sequencer == null) begin if (m_sequencer == null) begin uvm_report_fatal("UNLOCK", "Null m_sequencer reference", UVM_NONE); end m_sequencer.unlock(this); end else begin sequencer.unlock(this); end endfunction function void ungrab(uvm_sequencer_base sequencer = null); unlock(sequencer); endfunction function bit is_blocked(); return m_sequencer.is_blocked(this); endfunction function bit has_lock(); return m_sequencer.has_lock(this); endfunction function void kill(); if (m_sequence_process != null) begin if (m_sequencer == null) begin m_kill(); if (get_automatic_phase_objection()) begin m_safe_drop_starting_phase("automatic phase objection"); end return; end m_sequencer.kill_sequence(this); if (get_automatic_phase_objection()) begin m_safe_drop_starting_phase("automatic phase objection"); end return; end endfunction virtual function void do_kill(); return; endfunction function void m_kill(); do_kill(); foreach(children_array[i]) begin i.kill(); end if (m_sequence_process != null) begin m_sequence_process.kill; m_sequence_process = null; end m_sequence_state = UVM_STOPPED; if ((m_parent_sequence != null) && (m_parent_sequence.children_array.exists(this))) m_parent_sequence.children_array.delete(this); clean_exit_sequence(); endfunction protected function uvm_sequence_item create_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name); uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory factory=cs.get_factory(); $cast(create_item, factory.create_object_by_type( type_var, this.get_full_name(), name )); create_item.set_item_context(this, l_sequencer); endfunction virtual task start_item (uvm_sequence_item item, int set_priority = -1, uvm_sequencer_base sequencer=null); if(item == null) begin uvm_report_fatal("NULLITM", {"attempting to start a null item from sequence '", get_full_name(), "'"}, UVM_NONE); return; end if ( ! item.is_item() ) begin uvm_report_fatal("SEQNOTITM", {"attempting to start a sequence using start_item() from sequence '", get_full_name(), "'. Use seq.start() instead."}, UVM_NONE); return; end if (sequencer == null) sequencer = item.get_sequencer(); if(sequencer == null) sequencer = get_sequencer(); if(sequencer == null) begin uvm_report_fatal("SEQ",{"neither the item's sequencer nor dedicated sequencer has been supplied to start item in ",get_full_name()},UVM_NONE); return; end item.set_item_context(this, sequencer); if (set_priority < 0) set_priority = get_priority(); sequencer.wait_for_grant(this, set_priority); if (sequencer.is_auto_item_recording_enabled()) begin void'(sequencer.begin_tr(.tr(item), .stream_name(item.get_root_sequence_name()), .label("Transactions"), .parent_handle((m_tr_recorder == null) ? 0 : m_tr_recorder.get_handle()))); end pre_do(1); endtask virtual task finish_item (uvm_sequence_item item, int set_priority = -1); uvm_sequencer_base sequencer; sequencer = item.get_sequencer(); if (sequencer == null) begin uvm_report_fatal("STRITM", "sequence_item has null sequencer", UVM_NONE); end mid_do(item); sequencer.send_request(this, item); sequencer.wait_for_item_done(this, -1); if (sequencer.is_auto_item_recording_enabled()) begin sequencer.end_tr(item); end post_do(item); endtask virtual task wait_for_grant(int item_priority = -1, bit lock_request = 0); if (m_sequencer == null) begin uvm_report_fatal("WAITGRANT", "Null m_sequencer reference", UVM_NONE); end m_sequencer.wait_for_grant(this, item_priority, lock_request); endtask virtual function void send_request(uvm_sequence_item request, bit rerandomize = 0); if (m_sequencer == null) begin uvm_report_fatal("SENDREQ", "Null m_sequencer reference", UVM_NONE); end m_sequencer.send_request(this, request, rerandomize); endfunction virtual task wait_for_item_done(int transaction_id = -1); if (m_sequencer == null) begin uvm_report_fatal("WAITITEMDONE", "Null m_sequencer reference", UVM_NONE); end m_sequencer.wait_for_item_done(this, transaction_id); endtask function void use_response_handler(bit enable); m_use_response_handler = enable; endfunction function bit get_use_response_handler(); return m_use_response_handler; endfunction virtual function void response_handler(uvm_sequence_item response); return; endfunction function void set_response_queue_error_report_enabled(bit value); response_queue_error_report_enabled = value; endfunction : set_response_queue_error_report_enabled function bit get_response_queue_error_report_enabled(); return response_queue_error_report_enabled; endfunction : get_response_queue_error_report_enabled function void set_response_queue_depth(int value); response_queue_depth = value; endfunction function int get_response_queue_depth(); return response_queue_depth; endfunction virtual function void clear_response_queue(); response_queue.delete(); endfunction virtual function void put_base_response(input uvm_sequence_item response); if ((response_queue_depth == -1) || (response_queue.size() < response_queue_depth)) begin response_queue.push_back(response); return; end if (response_queue_error_report_enabled) begin uvm_report_error(get_full_name(), "Response queue overflow, response was dropped", UVM_NONE); end endfunction virtual function void put_response (uvm_sequence_item response_item); put_base_response(response_item); endfunction virtual task get_base_response(output uvm_sequence_item response, input int transaction_id = -1); int queue_size, i; if (response_queue.size() == 0) wait (response_queue.size() != 0); if (transaction_id == -1) begin response = response_queue.pop_front(); return; end forever begin queue_size = response_queue.size(); for (i = 0; i < queue_size; i++) begin if (response_queue[i].get_transaction_id() == transaction_id) begin $cast(response,response_queue[i]); response_queue.delete(i); return; end end wait (response_queue.size() != queue_size); end endtask function int m_get_sqr_sequence_id(int sequencer_id, bit update_sequence_id); if (m_sqr_seq_ids.exists(sequencer_id)) begin if (update_sequence_id == 1) begin set_sequence_id(m_sqr_seq_ids[sequencer_id]); end return m_sqr_seq_ids[sequencer_id]; end if (update_sequence_id == 1) set_sequence_id(-1); return -1; endfunction function void m_set_sqr_sequence_id(int sequencer_id, int sequence_id); m_sqr_seq_ids[sequencer_id] = sequence_id; set_sequence_id(sequence_id); endfunction endclass virtual class uvm_sequence #(type REQ = uvm_sequence_item, type RSP = REQ) extends uvm_sequence_base; typedef uvm_sequencer_param_base #(REQ, RSP) sequencer_t; sequencer_t param_sequencer; REQ req; RSP rsp; function new (string name = "uvm_sequence"); super.new(name); endfunction function void send_request(uvm_sequence_item request, bit rerandomize = 0); REQ m_request; if (m_sequencer == null) begin uvm_report_fatal("SSENDREQ", "Null m_sequencer reference", UVM_NONE); end if (!$cast(m_request, request)) begin uvm_report_fatal("SSENDREQ", "Failure to cast uvm_sequence_item to request", UVM_NONE); end m_sequencer.send_request(this, m_request, rerandomize); endfunction function REQ get_current_item(); if (!$cast(param_sequencer, m_sequencer)) uvm_report_fatal("SGTCURR", "Failure to cast m_sequencer to the parameterized sequencer", UVM_NONE); return (param_sequencer.get_current_item()); endfunction virtual task get_response(output RSP response, input int transaction_id = -1); uvm_sequence_item rsp; get_base_response( rsp, transaction_id); $cast(response,rsp); endtask virtual function void put_response(uvm_sequence_item response_item); RSP response; if (!$cast(response, response_item)) begin uvm_report_fatal("PUTRSP", "Failure to cast response in put_response", UVM_NONE); end put_base_response(response_item); endfunction function void do_print (uvm_printer printer); super.do_print(printer); printer.print_object("req", req); printer.print_object("rsp", rsp); endfunction endclass typedef class uvm_sequence_library_cfg; class uvm_sequence_library #(type REQ=uvm_sequence_item,RSP=REQ) extends uvm_sequence #(REQ,RSP); typedef uvm_object_registry #(uvm_sequence_library#(REQ,RSP)) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_sequence_library#(REQ,RSP) tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_sequence_library #(REQ,RSP)"; endfunction : type_name virtual function string get_type_name(); return "uvm_sequence_library #(REQ,RSP)"; endfunction : get_type_name extern function new(string name=""); uvm_sequence_lib_mode selection_mode; int unsigned min_random_count=10; int unsigned max_random_count=10; protected int unsigned sequences_executed; rand int unsigned sequence_count = 10; rand int unsigned select_rand; randc bit [15:0] select_randc; protected int seqs_distrib[string] = '{default:0}; protected uvm_object_wrapper sequences[$]; constraint valid_rand_selection { select_rand inside {[0:sequences.size()-1]}; } constraint valid_randc_selection { select_randc inside {[0:sequences.size()-1]}; } constraint valid_sequence_count { sequence_count inside {[min_random_count:max_random_count]}; } extern virtual function int unsigned select_sequence(int unsigned max); extern static function void add_typewide_sequence(uvm_object_wrapper seq_type); extern static function void add_typewide_sequences(uvm_object_wrapper seq_types[$]); extern function void add_sequence(uvm_object_wrapper seq_type); extern virtual function void add_sequences(uvm_object_wrapper seq_types[$]); extern virtual function void remove_sequence(uvm_object_wrapper seq_type); extern virtual function void get_sequences(ref uvm_object_wrapper seq_types[$]); extern virtual function uvm_object_wrapper get_sequence(int unsigned idx); extern function void init_sequence_library(); typedef uvm_sequence_library #(REQ,RSP) this_type; static protected uvm_object_wrapper m_typewide_sequences[$]; bit m_abort; extern static function bit m_static_check(uvm_object_wrapper seq_type); extern static function bit m_check(uvm_object_wrapper seq_type, this_type lib); extern function bit m_dyn_check(uvm_object_wrapper seq_type); extern function void m_get_config(); extern static function bit m_add_typewide_sequence(uvm_object_wrapper seq_type); extern virtual task execute(uvm_object_wrapper wrap); extern virtual task body(); extern virtual function void do_print(uvm_printer printer); extern function void pre_randomize(); endclass class uvm_sequence_library_cfg extends uvm_object; typedef uvm_object_registry#(uvm_sequence_library_cfg,"uvm_sequence_library_cfg") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_sequence_library_cfg tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_sequence_library_cfg"; endfunction : type_name virtual function string get_type_name(); return "uvm_sequence_library_cfg"; endfunction : get_type_name uvm_sequence_lib_mode selection_mode; int unsigned min_random_count; int unsigned max_random_count; function new(string name="", uvm_sequence_lib_mode mode=UVM_SEQ_LIB_RAND, int unsigned min=1, int unsigned max=10); super.new(name); selection_mode = mode; min_random_count = min; max_random_count = max; endfunction endclass function uvm_sequence_library::new(string name=""); super.new(name); init_sequence_library(); valid_rand_selection.constraint_mode(0); valid_randc_selection.constraint_mode(0); endfunction function bit uvm_sequence_library::m_add_typewide_sequence(uvm_object_wrapper seq_type); this_type::add_typewide_sequence(seq_type); return 1; endfunction function void uvm_sequence_library::add_typewide_sequence(uvm_object_wrapper seq_type); if (m_static_check(seq_type)) m_typewide_sequences.push_back(seq_type); endfunction function void uvm_sequence_library::add_typewide_sequences(uvm_object_wrapper seq_types[$]); foreach (seq_types[i]) add_typewide_sequence(seq_types[i]); endfunction function void uvm_sequence_library::add_sequence(uvm_object_wrapper seq_type); if (m_dyn_check(seq_type)) sequences.push_back(seq_type); endfunction function void uvm_sequence_library::add_sequences(uvm_object_wrapper seq_types[$]); foreach (seq_types[i]) add_sequence(seq_types[i]); endfunction function void uvm_sequence_library::remove_sequence(uvm_object_wrapper seq_type); foreach (sequences[i]) if (sequences[i] == seq_type) begin sequences.delete(i); return; end endfunction function void uvm_sequence_library::get_sequences(ref uvm_object_wrapper seq_types[$]); foreach (sequences[i]) seq_types.push_back(sequences[i]); endfunction function uvm_object_wrapper uvm_sequence_library::get_sequence(int unsigned idx); if(idx < sequences.size()) return sequences[idx]; else begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"SEQ_LIB/GET_SEQ")) uvm_report_error ("SEQ_LIB/GET_SEQ", $sformatf("idx %0d > number of sequences in library", idx), UVM_NONE, "t/uvm/src/seq/uvm_sequence_library.svh", 453, "", 1); end return null; end endfunction function int unsigned uvm_sequence_library::select_sequence(int unsigned max); static int unsigned counter; select_sequence = counter; counter++; if (counter >= max) counter = 0; endfunction function void uvm_sequence_library::init_sequence_library(); foreach (this_type::m_typewide_sequences[i]) sequences.push_back(this_type::m_typewide_sequences[i]); endfunction function bit uvm_sequence_library::m_static_check(uvm_object_wrapper seq_type); if (!m_check(seq_type,null)) return 0; foreach (m_typewide_sequences[i]) if (m_typewide_sequences[i] == seq_type) return 0; return 1; endfunction function bit uvm_sequence_library::m_dyn_check(uvm_object_wrapper seq_type); if (!m_check(seq_type,this)) return 0; foreach (sequences[i]) if (sequences[i] == seq_type) return 0; return 1; endfunction function bit uvm_sequence_library::m_check(uvm_object_wrapper seq_type, this_type lib); uvm_object obj; uvm_sequence_base seq; uvm_root top; uvm_coreservice_t cs; string name; string typ; obj = seq_type.create_object(); name = (lib == null) ? type_name() : lib.get_full_name(); typ = (lib == null) ? type_name() : lib.get_type_name(); cs = uvm_coreservice_t::get(); top = cs.get_root(); if (!$cast(seq, obj)) begin begin if (top.uvm_report_enabled(UVM_NONE,UVM_ERROR,"SEQLIB/BAD_SEQ_TYPE")) top.uvm_report_error ("SEQLIB/BAD_SEQ_TYPE", {"Object '",obj.get_type_name(), "' is not a sequence. Cannot add to sequence library '",name, "'"}, UVM_NONE, "t/uvm/src/seq/uvm_sequence_library.svh", 538, "", 1); end return 0; end return 1; endfunction function void uvm_sequence_library::pre_randomize(); m_get_config(); endfunction function void uvm_sequence_library::m_get_config(); uvm_sequence_library_cfg cfg; string phase_name; uvm_phase starting_phase = get_starting_phase(); if (starting_phase != null) begin phase_name = {starting_phase.get_name(),"_phase"}; end if (uvm_config_db #(uvm_sequence_library_cfg)::get(m_sequencer, phase_name, "default_sequence.config", cfg) ) begin selection_mode = cfg.selection_mode; min_random_count = cfg.min_random_count; max_random_count = cfg.max_random_count; end else begin void'(uvm_config_db #(int unsigned)::get(m_sequencer, phase_name, "default_sequence.min_random_count", min_random_count) ); void'(uvm_config_db #(int unsigned)::get(m_sequencer, phase_name, "default_sequence.max_random_count", max_random_count) ); void'(uvm_config_db #(uvm_sequence_lib_mode)::get(m_sequencer, phase_name, "default_sequence.selection_mode", selection_mode) ); end if (max_random_count == 0) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"SEQLIB/MAX_ZERO")) uvm_report_warning ("SEQLIB/MAX_ZERO", $sformatf("max_random_count (%0d) zero. Nothing will be done.", max_random_count), UVM_NONE, "t/uvm/src/seq/uvm_sequence_library.svh", 593, "", 1); end if (min_random_count > max_random_count) min_random_count = max_random_count; end else if (min_random_count > max_random_count) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"SEQLIB/MIN_GT_MAX")) uvm_report_error ("SEQLIB/MIN_GT_MAX", $sformatf("min_random_count (%0d) greater than max_random_count (%0d). Setting min to max.", min_random_count,max_random_count), UVM_NONE, "t/uvm/src/seq/uvm_sequence_library.svh", 600, "", 1); end min_random_count = max_random_count; end else begin if (selection_mode == UVM_SEQ_LIB_ITEM) begin uvm_sequencer #(REQ,RSP) seqr; uvm_object_wrapper lhs = REQ::get_type(); uvm_object_wrapper rhs = uvm_sequence_item::get_type(); if (lhs == rhs) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"SEQLIB/BASE_ITEM")) uvm_report_error ("SEQLIB/BASE_ITEM", {"selection_mode cannot be UVM_SEQ_LIB_ITEM when ", "the REQ type is the base uvm_sequence_item. Using UVM_SEQ_LIB_RAND mode"}, UVM_NONE, "t/uvm/src/seq/uvm_sequence_library.svh", 610, "", 1); end selection_mode = UVM_SEQ_LIB_RAND; end if (m_sequencer == null || !$cast(seqr,m_sequencer)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"SEQLIB/VIRT_SEQ")) uvm_report_error ("SEQLIB/VIRT_SEQ", {"selection_mode cannot be UVM_SEQ_LIB_ITEM when ", "running as a virtual sequence. Using UVM_SEQ_LIB_RAND mode"}, UVM_NONE, "t/uvm/src/seq/uvm_sequence_library.svh", 615, "", 1); end selection_mode = UVM_SEQ_LIB_RAND; end end end endfunction task uvm_sequence_library::body(); uvm_object_wrapper wrap; uvm_phase starting_phase = get_starting_phase(); if (m_sequencer == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"SEQLIB/VIRT_SEQ")) uvm_report_fatal ("SEQLIB/VIRT_SEQ", {"Sequence library 'm_sequencer' handle is null ", " no current support for running as a virtual sequence."}, UVM_NONE, "t/uvm/src/seq/uvm_sequence_library.svh", 634, "", 1); end return; end if (sequences.size() == 0) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"SEQLIB/NOSEQS")) uvm_report_error ("SEQLIB/NOSEQS", "Sequence library does not contain any sequences. Did you forget to call init_sequence_library() in the constructor?", UVM_NONE, "t/uvm/src/seq/uvm_sequence_library.svh", 639, "", 1); end return; end if (!get_randomize_enabled()) m_get_config(); m_safe_raise_starting_phase({"starting sequence library ",get_full_name()," (", get_type_name(),")"}); begin if (uvm_report_enabled(UVM_LOW,UVM_INFO,"SEQLIB/START")) uvm_report_info ("SEQLIB/START", $sformatf("Starting sequence library %s in %s phase: %0d iterations in mode %s", get_type_name(), (starting_phase != null ? starting_phase.get_name() : "unknown"), sequence_count, selection_mode.name()), UVM_LOW, "t/uvm/src/seq/uvm_sequence_library.svh", 652, "", 1); end begin if (uvm_report_enabled(UVM_FULL,UVM_INFO,"SEQLIB/SPRINT")) uvm_report_info ("SEQLIB/SPRINT", {"\n",sprint(uvm_table_printer::get_default())}, UVM_FULL, "t/uvm/src/seq/uvm_sequence_library.svh", 654, "", 1); end case (selection_mode) UVM_SEQ_LIB_RAND: begin valid_rand_selection.constraint_mode(1); valid_sequence_count.constraint_mode(0); for (int i=1; i<=sequence_count; i++) begin if (!randomize(select_rand)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"SEQLIB/RAND_FAIL")) uvm_report_error ("SEQLIB/RAND_FAIL", "Random sequence selection failed", UVM_NONE, "t/uvm/src/seq/uvm_sequence_library.svh", 663, "", 1); end break; end else begin wrap = sequences[select_rand]; end execute(wrap); end valid_rand_selection.constraint_mode(0); valid_sequence_count.constraint_mode(1); end UVM_SEQ_LIB_RANDC: begin uvm_object_wrapper q[$]; valid_randc_selection.constraint_mode(1); valid_sequence_count.constraint_mode(0); for (int i=1; i<=sequence_count; i++) begin if (!randomize(select_randc)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"SEQLIB/RANDC_FAIL")) uvm_report_error ("SEQLIB/RANDC_FAIL", "Random sequence selection failed", UVM_NONE, "t/uvm/src/seq/uvm_sequence_library.svh", 681, "", 1); end break; end else begin wrap = sequences[select_randc]; end q.push_back(wrap); end valid_randc_selection.constraint_mode(0); valid_sequence_count.constraint_mode(1); foreach(q[i]) execute(q[i]); valid_randc_selection.constraint_mode(0); valid_sequence_count.constraint_mode(1); end UVM_SEQ_LIB_ITEM: begin for (int i=1; i<=sequence_count; i++) begin wrap = REQ::get_type(); execute(wrap); end end UVM_SEQ_LIB_USER: begin for (int i=1; i<=sequence_count; i++) begin int user_selection; user_selection = select_sequence(sequences.size()-1); if (user_selection >= sequences.size()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"SEQLIB/USER_FAIL")) uvm_report_error ("SEQLIB/USER_FAIL", "User sequence selection out of range", UVM_NONE, "t/uvm/src/seq/uvm_sequence_library.svh", 709, "", 1); end wrap = REQ::get_type(); end else begin wrap = sequences[user_selection]; end execute(wrap); end end default: begin begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"SEQLIB/RAND_MODE")) uvm_report_fatal ("SEQLIB/RAND_MODE", $sformatf("Unknown random sequence selection mode: %0d",selection_mode), UVM_NONE, "t/uvm/src/seq/uvm_sequence_library.svh", 721, "", 1); end end endcase begin if (uvm_report_enabled(UVM_LOW,UVM_INFO,"SEQLIB/END")) uvm_report_info ("SEQLIB/END", {"Ending sequence library in phase ", (starting_phase != null ? starting_phase.get_name() : "unknown")}, UVM_LOW, "t/uvm/src/seq/uvm_sequence_library.svh", 726, "", 1); end begin if (uvm_report_enabled(UVM_HIGH,UVM_INFO,"SEQLIB/DSTRB")) uvm_report_info ("SEQLIB/DSTRB", $sformatf("%p",seqs_distrib), UVM_HIGH, "t/uvm/src/seq/uvm_sequence_library.svh", 728, "", 1); end m_safe_drop_starting_phase({"starting sequence library ",get_full_name()," (", get_type_name(),")"}); endtask task uvm_sequence_library::execute(uvm_object_wrapper wrap); uvm_object obj; uvm_sequence_item seq_or_item; uvm_sequence_base seq_base; REQ req_item; uvm_coreservice_t cs = uvm_coreservice_t::get(); uvm_factory factory=cs.get_factory(); obj = factory.create_object_by_type(wrap,get_full_name(), $sformatf("%s:%0d",wrap.get_type_name(),sequences_executed+1)); if (!$cast(seq_base, obj)) begin if (!$cast(req_item, obj)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"SEQLIB/WRONG_ITEM_TYPE")) uvm_report_error ("SEQLIB/WRONG_ITEM_TYPE", {"The item created by '", get_full_name(), "' when in 'UVM_SEQ_LIB_ITEM' mode doesn't match the REQ type which was passed in to the uvm_sequence_library#(REQ[,RSP]), this can happen if the REQ type which was passed in was a pure-virtual type. Either configure the factory overrides to properly generate items for this sequence library, or do not execute this sequence library in UVM_SEQ_LIB_ITEM mode."}, UVM_NONE, "t/uvm/src/seq/uvm_sequence_library.svh", 756, "", 1); end return; end end void'($cast(seq_or_item,obj)); begin if (uvm_report_enabled(UVM_FULL,UVM_INFO,"SEQLIB/EXEC")) uvm_report_info ("SEQLIB/EXEC", {"Executing ",(seq_or_item.is_item() ? "item " : "sequence "),seq_or_item.get_name(), " (",seq_or_item.get_type_name(),")"}, UVM_FULL, "t/uvm/src/seq/uvm_sequence_library.svh", 764, "", 1); end seq_or_item.print_sequence_info = 1; begin uvm_sequence_base __seq; if ( seq_or_item.is_item() ) begin start_item(seq_or_item, -1); if ( ! seq_or_item.randomize() with {} ) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RNDFLD")) uvm_report_warning ("RNDFLD", "Randomization failed in uvm_rand_send action", UVM_NONE, "t/uvm/src/seq/uvm_sequence_library.svh", 766, "", 1); end end finish_item(seq_or_item, -1); end else if ( $cast( __seq, seq_or_item ) ) begin __seq.set_item_context(this,seq_or_item.get_sequencer()); if ( __seq.get_randomize_enabled() ) begin if ( ! seq_or_item.randomize() with {} ) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RNDFLD")) uvm_report_warning ("RNDFLD", "Randomization failed in uvm_rand_send action", UVM_NONE, "t/uvm/src/seq/uvm_sequence_library.svh", 766, "", 1); end end end __seq.start(__seq.get_sequencer(), this, -1, 0); end else begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"NOT_SEQ_OR_ITEM")) uvm_report_warning ("NOT_SEQ_OR_ITEM", "Object passed uvm_rand_send appears to be neither a sequence or item.", UVM_NONE, "t/uvm/src/seq/uvm_sequence_library.svh", 766, "", 1); end end end seqs_distrib[seq_or_item.get_type_name()] = seqs_distrib[seq_or_item.get_type_name()]+1; sequences_executed++; endtask function void uvm_sequence_library::do_print(uvm_printer printer); printer.print_field_int("min_random_count",min_random_count,32,UVM_DEC,,"int unsigned"); printer.print_field_int("max_random_count",max_random_count,32,UVM_DEC,,"int unsigned"); printer.print_generic("selection_mode","uvm_sequence_lib_mode",32,selection_mode.name()); printer.print_field_int("sequence_count",sequence_count,32,UVM_DEC,,"int unsigned"); printer.print_array_header("typewide_sequences",m_typewide_sequences.size(),"queue_object_types"); foreach (m_typewide_sequences[i]) printer.print_generic($sformatf("[%0d]",i),"uvm_object_wrapper","-",m_typewide_sequences[i].get_type_name()); printer.print_array_footer(); printer.print_array_header("sequences",sequences.size(),"queue_object_types"); foreach (sequences[i]) printer.print_generic($sformatf("[%0d]",i),"uvm_object_wrapper","-",sequences[i].get_type_name()); printer.print_array_footer(); printer.print_array_header("seqs_distrib",seqs_distrib.num(),"as_int_string"); foreach (seqs_distrib[typ]) begin printer.print_field_int({"[",typ,"]"},seqs_distrib[typ],32,,UVM_DEC,"int unsigned"); end printer.print_array_footer(); endfunction typedef uvm_sequence #(uvm_sequence_item, uvm_sequence_item) uvm_default_sequence_type; typedef uvm_sequencer #(uvm_sequence_item, uvm_sequence_item) uvm_default_sequencer_type; typedef uvm_driver #(uvm_sequence_item, uvm_sequence_item) uvm_default_driver_type; typedef uvm_sequencer_param_base #(uvm_sequence_item, uvm_sequence_item) uvm_default_sequencer_param_type; `define UVM_TLM_NB_FW_MASK (1<<0) `define UVM_TLM_NB_BW_MASK (1<<1) `define UVM_TLM_B_MASK (1<<2) class uvm_time; static local real m_resolution = 1.0e-12; local real m_res; local time m_time; local string m_name; static function void set_time_resolution(real res); m_resolution = res; endfunction function new(string name = "uvm_tlm_time", real res = 0); m_name = name; m_res = (res == 0) ? m_resolution : res; reset(); endfunction function string get_name(); return m_name; endfunction function void reset(); m_time = 0; endfunction local function real to_m_res(real t, time scaled, real secs); return t/real'(scaled) * (secs/m_res); endfunction function real get_realtime(time scaled, real secs = 1.0e-9); return m_time*real'(scaled) * m_res/secs; endfunction function void incr(real t, time scaled, real secs = 1.0e-9); if (t < 0.0) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/TIMENEG")) uvm_report_error ("UVM/TLM/TIMENEG", {"Cannot increment uvm_tlm_time variable ", m_name, " by a negative value"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm_time.svh", 134, "", 1); end return; end if (scaled == 0) begin begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"UVM/TLM/BADSCALE")) uvm_report_fatal ("UVM/TLM/BADSCALE", "uvm_tlm_time::incr() called with a scaled time literal that is smaller than the current timescale", UVM_NONE, "t/uvm/src/tlm2/uvm_tlm_time.svh", 139, "", 1); end end m_time += to_m_res(t, scaled, secs); endfunction function void decr(real t, time scaled, real secs); if (t < 0.0) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/TIMENEG")) uvm_report_error ("UVM/TLM/TIMENEG", {"Cannot decrement uvm_tlm_time variable ", m_name, " by a negative value"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm_time.svh", 161, "", 1); end return; end if (scaled == 0) begin begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"UVM/TLM/BADSCALE")) uvm_report_fatal ("UVM/TLM/BADSCALE", "uvm_tlm_time::decr() called with a scaled time literal that is smaller than the current timescale", UVM_NONE, "t/uvm/src/tlm2/uvm_tlm_time.svh", 166, "", 1); end end m_time -= to_m_res(t, scaled, secs); if (m_time < 0.0) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/TOODECR")) uvm_report_error ("UVM/TLM/TOODECR", {"Cannot decrement uvm_tlm_time variable ", m_name, " to a negative value"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm_time.svh", 172, "", 1); end reset(); end endfunction function real get_abstime(real secs); return m_time*m_res/secs; endfunction function void set_abstime(real t, real secs); m_time = t*secs/m_res; endfunction endclass typedef uvm_time uvm_tlm_time; typedef enum { UVM_TLM_READ_COMMAND, UVM_TLM_WRITE_COMMAND, UVM_TLM_IGNORE_COMMAND } uvm_tlm_command_e; typedef enum { UVM_TLM_OK_RESPONSE = 1, UVM_TLM_INCOMPLETE_RESPONSE = 0, UVM_TLM_GENERIC_ERROR_RESPONSE = -1, UVM_TLM_ADDRESS_ERROR_RESPONSE = -2, UVM_TLM_COMMAND_ERROR_RESPONSE = -3, UVM_TLM_BURST_ERROR_RESPONSE = -4, UVM_TLM_BYTE_ENABLE_ERROR_RESPONSE = -5 } uvm_tlm_response_status_e; typedef class uvm_tlm_extension_base; class uvm_tlm_generic_payload extends uvm_sequence_item; rand bit [63:0] m_address; rand uvm_tlm_command_e m_command; rand byte unsigned m_data[]; rand int unsigned m_length; rand uvm_tlm_response_status_e m_response_status; bit m_dmi; rand byte unsigned m_byte_enable[]; rand int unsigned m_byte_enable_length; rand int unsigned m_streaming_width; protected uvm_tlm_extension_base m_extensions [uvm_tlm_extension_base]; local rand uvm_tlm_extension_base m_rand_exts[]; typedef uvm_object_registry#(uvm_tlm_generic_payload,"uvm_tlm_generic_payload") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_tlm_generic_payload tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_tlm_generic_payload"; endfunction : type_name virtual function string get_type_name(); return "uvm_tlm_generic_payload"; endfunction : get_type_name function new(string name=""); super.new(name); m_address = 0; m_command = UVM_TLM_IGNORE_COMMAND; m_length = 0; m_response_status = UVM_TLM_INCOMPLETE_RESPONSE; m_dmi = 0; m_byte_enable_length = 0; m_streaming_width = 0; endfunction function void do_print(uvm_printer printer); byte unsigned be; super.do_print(printer); printer.print_field_int ("address", m_address, 64, UVM_HEX); printer.print_generic ("command", "uvm_tlm_command_e", 32, m_command.name()); printer.print_generic ("response_status", "uvm_tlm_response_status_e", 32, m_response_status.name()); printer.print_field_int ("streaming_width", m_streaming_width, 32, UVM_HEX); printer.print_array_header("data", m_length, "darray(byte)"); for (int i=0; i < m_length && i < m_data.size(); i++) begin if (m_byte_enable_length) begin be = m_byte_enable[i % m_byte_enable_length]; printer.print_generic ($sformatf("[%0d]",i), "byte", 8, $sformatf("'h%h%s",m_data[i],((be=='hFF) ? "" : " x"))); end else printer.print_generic ($sformatf("[%0d]",i), "byte", 8, $sformatf("'h%h",m_data[i])); end printer.print_array_footer(); begin string name; printer.print_array_header("extensions", m_extensions.num(), "aa(obj,obj)"); foreach (m_extensions[ext_]) begin uvm_tlm_extension_base ext = m_extensions[ext_]; name = {"[",ext.get_name(),"]"}; printer.print_object(name, ext, "["); end printer.print_array_footer(); end endfunction function void do_copy(uvm_object rhs); uvm_tlm_generic_payload gp; super.do_copy(rhs); $cast(gp, rhs); m_address = gp.m_address; m_command = gp.m_command; m_data = gp.m_data; m_dmi = gp.m_dmi; m_length = gp.m_length; m_response_status = gp.m_response_status; m_byte_enable = gp.m_byte_enable; m_streaming_width = gp.m_streaming_width; m_byte_enable_length = gp.m_byte_enable_length; m_extensions.delete(); foreach (gp.m_extensions[ext]) $cast(m_extensions[ext], gp.m_extensions[ext].clone()); endfunction `define m_uvm_tlm_fast_compare_int(VALUE,RADIX,NAME="") \ if ( (!comparer.get_threshold() || (comparer.get_result() < comparer.get_threshold())) && \ ((VALUE) != (gp.VALUE)) ) begin \ string name = (NAME == "") ? `"VALUE`" : NAME; \ void'(comparer.compare_field_int(name , VALUE, gp.VALUE, $bits(VALUE), RADIX)); \ end `define m_uvm_tlm_fast_compare_enum(VALUE,TYPE,NAME="") \ if ( (!comparer.get_threshold() || (comparer.get_result() < comparer.get_threshold())) && \ ((VALUE) != (gp.VALUE)) ) begin \ string name = (NAME == "") ? `"VALUE`" : NAME; \ void'( comparer.compare_string(name, \ $sformatf("%s'(%s)", `"TYPE`", VALUE.name()), \ $sformatf("%s'(%s)", `"TYPE`", gp.VALUE.name())) ); \ end function bit do_compare(uvm_object rhs, uvm_comparer comparer); uvm_tlm_generic_payload gp; do_compare = super.do_compare(rhs, comparer); $cast(gp, rhs); if ( (!comparer.get_threshold() || (comparer.get_result() < comparer.get_threshold())) && ((m_address) != (gp.m_address)) ) begin string name = ("" == "") ? "m_address" : ""; void'(comparer.compare_field_int(name , m_address, gp.m_address, $bits(m_address), UVM_HEX)); end if ( (!comparer.get_threshold() || (comparer.get_result() < comparer.get_threshold())) && ((m_command) != (gp.m_command)) ) begin string name = ("" == "") ? "m_command" : ""; void'( comparer.compare_string(name, $sformatf("%s'(%s)", "uvm_tlm_command_e", m_command.name()), $sformatf("%s'(%s)", "uvm_tlm_command_e", gp.m_command.name())) ); end if ( (!comparer.get_threshold() || (comparer.get_result() < comparer.get_threshold())) && ((m_length) != (gp.m_length)) ) begin string name = ("" == "") ? "m_length" : ""; void'(comparer.compare_field_int(name , m_length, gp.m_length, $bits(m_length), UVM_UNSIGNED)); end if ( (!comparer.get_threshold() || (comparer.get_result() < comparer.get_threshold())) && ((m_dmi) != (gp.m_dmi)) ) begin string name = ("" == "") ? "m_dmi" : ""; void'(comparer.compare_field_int(name , m_dmi, gp.m_dmi, $bits(m_dmi), UVM_BIN)); end if ( (!comparer.get_threshold() || (comparer.get_result() < comparer.get_threshold())) && ((m_byte_enable_length) != (gp.m_byte_enable_length)) ) begin string name = ("" == "") ? "m_byte_enable_length" : ""; void'(comparer.compare_field_int(name , m_byte_enable_length, gp.m_byte_enable_length, $bits(m_byte_enable_length), UVM_UNSIGNED)); end if ( (!comparer.get_threshold() || (comparer.get_result() < comparer.get_threshold())) && ((m_response_status) != (gp.m_response_status)) ) begin string name = ("" == "") ? "m_response_status" : ""; void'( comparer.compare_string(name, $sformatf("%s'(%s)", "uvm_tlm_response_status_e", m_response_status.name()), $sformatf("%s'(%s)", "uvm_tlm_response_status_e", gp.m_response_status.name())) ); end if ( (!comparer.get_threshold() || (comparer.get_result() < comparer.get_threshold())) && ((m_streaming_width) != (gp.m_streaming_width)) ) begin string name = ("" == "") ? "m_streaming_width" : ""; void'(comparer.compare_field_int(name , m_streaming_width, gp.m_streaming_width, $bits(m_streaming_width), UVM_UNSIGNED)); end if ( (!comparer.get_threshold() || (comparer.get_result() < comparer.get_threshold())) && m_byte_enable_length == gp.m_byte_enable_length ) begin for (int i=0; i < m_byte_enable_length && i < m_byte_enable.size(); i++) begin if ( (!comparer.get_threshold() || (comparer.get_result() < comparer.get_threshold())) && ((m_byte_enable[i]) != (gp.m_byte_enable[i])) ) begin string name = ($sformatf("m_byte_enable[%0d]", i) == "") ? "m_byte_enable[i]" : $sformatf("m_byte_enable[%0d]", i); void'(comparer.compare_field_int(name , m_byte_enable[i], gp.m_byte_enable[i], $bits(m_byte_enable[i]), UVM_HEX)); end end end if ( (!comparer.get_threshold() || (comparer.get_result() < comparer.get_threshold())) && m_length == gp.m_length ) begin byte unsigned be; for (int i=0; i < m_length && i < m_data.size(); i++) begin if (m_byte_enable_length) begin be = m_byte_enable[i % m_byte_enable_length]; end else begin be = 8'hFF; end if ( (!comparer.get_threshold() || (comparer.get_result() < comparer.get_threshold())) && ((m_data[i] & be) != (gp.m_data[i] & be)) ) begin string name = ($sformatf("m_data[%0d] & %0x", i, be) == "") ? "m_data[i] & be" : $sformatf("m_data[%0d] & %0x", i, be); void'(comparer.compare_field_int(name , m_data[i] & be, gp.m_data[i] & be, $bits(m_data[i] & be), UVM_HEX)); end end end if ( !comparer.get_threshold() || (comparer.get_result() < comparer.get_threshold()) ) foreach (m_extensions[ext_]) begin uvm_tlm_extension_base ext = ext_; uvm_tlm_extension_base rhs_ext = gp.m_extensions.exists(ext) ? gp.m_extensions[ext] : null; void'(comparer.compare_object(ext.get_name(), m_extensions[ext], rhs_ext)); if ( !comparer.get_threshold() || (comparer.get_result() < comparer.get_threshold()) ) break; end if (comparer.get_result()) begin string msg = $sformatf("GP miscompare between '%s' and '%s':\nlhs = %s\nrhs = %s", get_full_name(), gp.get_full_name(), this.convert2string(), gp.convert2string()); comparer.print_msg(msg); end return (comparer.get_result() == 0); endfunction `undef m_uvm_tlm_fast_compare_int `undef m_uvm_tlm_fast_compare_enum function void do_pack(uvm_packer packer); super.do_pack(packer); if (m_length > m_data.size()) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PACK_DATA_ARR")) uvm_report_fatal ("PACK_DATA_ARR", $sformatf("Data array m_length property (%0d) greater than m_data.size (%0d)", m_length,m_data.size()), UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_generic_payload.svh", 562, "", 1); end if (m_byte_enable_length > m_byte_enable.size()) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"PACK_DATA_ARR")) uvm_report_fatal ("PACK_DATA_ARR", $sformatf("Data array m_byte_enable_length property (%0d) greater than m_byte_enable.size (%0d)", m_byte_enable_length,m_byte_enable.size()), UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_generic_payload.svh", 566, "", 1); end begin bit __array[]; { << bit { __array}} = m_address; __array = new [64] (__array); packer.pack_bits(__array, 64); end begin bit __array[]; { << bit { __array}} = m_command; __array = new [32] (__array); packer.pack_bits(__array, 32); end begin bit __array[]; { << bit { __array}} = m_length; __array = new [32] (__array); packer.pack_bits(__array, 32); end begin bit __array[]; { << bit { __array}} = m_dmi; __array = new [1] (__array); packer.pack_bits(__array, 1); end for (int i=0; i 64) recorder.record_field("address", m_address, $bits(m_address), UVM_NORADIX); else recorder.record_field_int("address", m_address, $bits(m_address), UVM_NORADIX); end if (recorder != null && recorder.is_open()) begin if (recorder.use_record_attribute()) recorder.record_generic("command", $sformatf("%p", m_command.name())); else recorder.record_string("command",m_command.name()); end if (recorder != null && recorder.is_open()) begin if (recorder.use_record_attribute()) recorder.record_generic("data_length", $sformatf("%p", m_length)); else if ($bits(m_length) > 64) recorder.record_field("data_length", m_length, $bits(m_length), UVM_NORADIX); else recorder.record_field_int("data_length", m_length, $bits(m_length), UVM_NORADIX); end if (recorder != null && recorder.is_open()) begin if (recorder.use_record_attribute()) recorder.record_generic("byte_enable_length", $sformatf("%p", m_byte_enable_length)); else if ($bits(m_byte_enable_length) > 64) recorder.record_field("byte_enable_length", m_byte_enable_length, $bits(m_byte_enable_length), UVM_NORADIX); else recorder.record_field_int("byte_enable_length", m_byte_enable_length, $bits(m_byte_enable_length), UVM_NORADIX); end if (recorder != null && recorder.is_open()) begin if (recorder.use_record_attribute()) recorder.record_generic("response_status", $sformatf("%p", m_response_status.name())); else recorder.record_string("response_status",m_response_status.name()); end if (recorder != null && recorder.is_open()) begin if (recorder.use_record_attribute()) recorder.record_generic("streaming_width", $sformatf("%p", m_streaming_width)); else if ($bits(m_streaming_width) > 64) recorder.record_field("streaming_width", m_streaming_width, $bits(m_streaming_width), UVM_NORADIX); else recorder.record_field_int("streaming_width", m_streaming_width, $bits(m_streaming_width), UVM_NORADIX); end for (int i=0; i < m_length; i++) if (recorder != null && recorder.is_open()) begin if (recorder.use_record_attribute()) recorder.record_generic($sformatf("\\data[%0d] ", i), $sformatf("%p", m_data[i])); else if ($bits(m_data[i]) > 64) recorder.record_field($sformatf("\\data[%0d] ", i), m_data[i], $bits(m_data[i]), UVM_NORADIX); else recorder.record_field_int($sformatf("\\data[%0d] ", i), m_data[i], $bits(m_data[i]), UVM_NORADIX); end for (int i=0; i < m_byte_enable_length; i++) if (recorder != null && recorder.is_open()) begin if (recorder.use_record_attribute()) recorder.record_generic($sformatf("\\byte_en[%0d] ", i), $sformatf("%p", m_byte_enable[i])); else if ($bits(m_byte_enable[i]) > 64) recorder.record_field($sformatf("\\byte_en[%0d] ", i), m_byte_enable[i], $bits(m_byte_enable[i]), UVM_NORADIX); else recorder.record_field_int($sformatf("\\byte_en[%0d] ", i), m_byte_enable[i], $bits(m_byte_enable[i]), UVM_NORADIX); end foreach (m_extensions[ext]) recorder.record_object(ext.get_name(),m_extensions[ext]); endfunction function string convert2string(); string msg; string s; $sformat(msg, "%s %s [0x%16x] =", super.convert2string(), m_command.name(), m_address); for(int unsigned i = 0; i < m_length; i++) begin if (!m_byte_enable_length || (m_byte_enable[i % m_byte_enable_length] == 'hFF)) $sformat(s, " %02x", m_data[i]); else $sformat(s, " --"); msg = { msg , s }; end msg = { msg, " (status=", get_response_string(), ")" }; return msg; endfunction virtual function uvm_tlm_command_e get_command(); return m_command; endfunction virtual function void set_command(uvm_tlm_command_e command); m_command = command; endfunction virtual function bit is_read(); return (m_command == UVM_TLM_READ_COMMAND); endfunction virtual function void set_read(); set_command(UVM_TLM_READ_COMMAND); endfunction virtual function bit is_write(); return (m_command == UVM_TLM_WRITE_COMMAND); endfunction virtual function void set_write(); set_command(UVM_TLM_WRITE_COMMAND); endfunction virtual function void set_address(bit [63:0] addr); m_address = addr; endfunction virtual function bit [63:0] get_address(); return m_address; endfunction virtual function void get_data (output byte unsigned p []); p = m_data; endfunction virtual function void set_data(ref byte unsigned p []); m_data = p; endfunction virtual function int unsigned get_data_length(); return m_length; endfunction virtual function void set_data_length(int unsigned length); m_length = length; endfunction virtual function int unsigned get_streaming_width(); return m_streaming_width; endfunction virtual function void set_streaming_width(int unsigned width); m_streaming_width = width; endfunction virtual function void get_byte_enable(output byte unsigned p[]); p = m_byte_enable; endfunction virtual function void set_byte_enable(ref byte unsigned p[]); m_byte_enable = p; endfunction virtual function int unsigned get_byte_enable_length(); return m_byte_enable_length; endfunction virtual function void set_byte_enable_length(int unsigned length); m_byte_enable_length = length; endfunction virtual function void set_dmi_allowed(bit dmi); m_dmi = dmi; endfunction virtual function bit is_dmi_allowed(); return m_dmi; endfunction virtual function uvm_tlm_response_status_e get_response_status(); return m_response_status; endfunction virtual function void set_response_status(uvm_tlm_response_status_e status); m_response_status = status; endfunction virtual function bit is_response_ok(); return (int'(m_response_status) > 0); endfunction virtual function bit is_response_error(); return !is_response_ok(); endfunction virtual function string get_response_string(); case(m_response_status) UVM_TLM_OK_RESPONSE : return "OK"; UVM_TLM_INCOMPLETE_RESPONSE : return "INCOMPLETE"; UVM_TLM_GENERIC_ERROR_RESPONSE : return "GENERIC_ERROR"; UVM_TLM_ADDRESS_ERROR_RESPONSE : return "ADDRESS_ERROR"; UVM_TLM_COMMAND_ERROR_RESPONSE : return "COMMAND_ERROR"; UVM_TLM_BURST_ERROR_RESPONSE : return "BURST_ERROR"; UVM_TLM_BYTE_ENABLE_ERROR_RESPONSE : return "BYTE_ENABLE_ERROR"; endcase return "UNKNOWN_RESPONSE"; endfunction function uvm_tlm_extension_base set_extension(uvm_tlm_extension_base ext); uvm_tlm_extension_base ext_handle = ext.get_type_handle(); if(!m_extensions.exists(ext_handle)) set_extension = null; else set_extension = m_extensions[ext_handle]; m_extensions[ext_handle] = ext; endfunction function int get_num_extensions(); return m_extensions.num(); endfunction: get_num_extensions function uvm_tlm_extension_base get_extension(uvm_tlm_extension_base ext_handle); if(!m_extensions.exists(ext_handle)) return null; return m_extensions[ext_handle]; endfunction function void clear_extension(uvm_tlm_extension_base ext_handle); if(m_extensions.exists(ext_handle)) m_extensions.delete(ext_handle); else begin if (uvm_report_enabled(UVM_MEDIUM,UVM_INFO,"GP_EXT")) uvm_report_info ("GP_EXT", $sformatf("Unable to find extension to clear"), UVM_MEDIUM, "t/uvm/src/tlm2/uvm_tlm2_generic_payload.svh", 965, "", 1); end endfunction function void clear_extensions(); m_extensions.delete(); endfunction function void pre_randomize(); int i; m_rand_exts = new [m_extensions.num()]; foreach (m_extensions[ext_]) begin uvm_tlm_extension_base ext = ext_; m_rand_exts[i++] = m_extensions[ext]; end endfunction function void post_randomize(); m_rand_exts.delete(); endfunction endclass typedef uvm_tlm_generic_payload uvm_tlm_gp; virtual class uvm_tlm_extension_base extends uvm_object; function new(string name = ""); super.new(name); endfunction pure virtual function uvm_tlm_extension_base get_type_handle(); pure virtual function string get_type_handle_name(); virtual function void do_copy(uvm_object rhs); super.do_copy(rhs); endfunction virtual function uvm_object create (string name=""); return null; endfunction endclass class uvm_tlm_extension #(type T=int) extends uvm_tlm_extension_base; typedef uvm_tlm_extension#(T) this_type; local static this_type m_my_tlm_ext_type = ID(); function new(string name=""); super.new(name); endfunction static function this_type ID(); if (m_my_tlm_ext_type == null) m_my_tlm_ext_type = new(); return m_my_tlm_ext_type; endfunction virtual function uvm_tlm_extension_base get_type_handle(); return ID(); endfunction virtual function string get_type_handle_name(); return $typename(T); endfunction virtual function uvm_object create (string name=""); return null; endfunction endclass typedef class uvm_time; typedef enum { UNINITIALIZED_PHASE, BEGIN_REQ, END_REQ, BEGIN_RESP, END_RESP } uvm_tlm_phase_e; typedef enum { UVM_TLM_ACCEPTED, UVM_TLM_UPDATED, UVM_TLM_COMPLETED } uvm_tlm_sync_e; `define UVM_TLM_TASK_ERROR "TLM-2 interface task not implemented" `define UVM_TLM_FUNCTION_ERROR "UVM TLM 2 interface function not implemented" class uvm_tlm_if #(type T=uvm_tlm_generic_payload, type P=uvm_tlm_phase_e); virtual function uvm_tlm_sync_e nb_transport_fw(T t, ref P p, input uvm_tlm_time delay); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"nb_transport_fw")) uvm_report_error ("nb_transport_fw", "UVM TLM 2 interface function not implemented", UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_ifs.svh", 115, "", 1); end return UVM_TLM_ACCEPTED; endfunction virtual function uvm_tlm_sync_e nb_transport_bw(T t, ref P p, input uvm_tlm_time delay); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"nb_transport_bw")) uvm_report_error ("nb_transport_bw", "UVM TLM 2 interface function not implemented", UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_ifs.svh", 158, "", 1); end return UVM_TLM_ACCEPTED; endfunction virtual task b_transport(T t, uvm_tlm_time delay); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"b_transport")) uvm_report_error ("b_transport", "TLM-2 interface task not implemented", UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_ifs.svh", 182, "", 1); end endtask endclass `define UVM_TLM_NB_TRANSPORT_FW_IMP(imp, T, P, t, p, delay) \ function uvm_tlm_sync_e nb_transport_fw(T t, ref P p, input uvm_tlm_time delay); \ if (delay == null) begin \ `uvm_error("UVM/TLM/NULLDELAY", \ {get_full_name(), \ ".nb_transport_fw() called with 'null' delay"}) \ return UVM_TLM_COMPLETED; \ end \ return imp.nb_transport_fw(t, p, delay); \ endfunction `define UVM_TLM_NB_TRANSPORT_BW_IMP(imp, T, P, t, p, delay) \ function uvm_tlm_sync_e nb_transport_bw(T t, ref P p, input uvm_tlm_time delay); \ if (delay == null) begin \ `uvm_error("UVM/TLM/NULLDELAY", \ {get_full_name(), \ ".nb_transport_bw() called with 'null' delay"}) \ return UVM_TLM_COMPLETED; \ end \ return imp.nb_transport_bw(t, p, delay); \ endfunction `define UVM_TLM_B_TRANSPORT_IMP(imp, T, t, delay) \ task b_transport(T t, uvm_tlm_time delay); \ if (delay == null) begin \ `uvm_error("UVM/TLM/NULLDELAY", \ {get_full_name(), \ ".b_transport() called with 'null' delay"}) \ return; \ end \ imp.b_transport(t, delay); \ endtask class uvm_tlm_b_transport_imp #(type T=uvm_tlm_generic_payload, type IMP=int) extends uvm_port_base #(uvm_tlm_if #(T)); local IMP m_imp; function new (string name, IMP imp); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); m_imp = imp; m_if_mask = (1<<2); endfunction virtual function string get_type_name(); return "uvm_tlm_b_transport_imp"; endfunction task b_transport(T t, uvm_tlm_time delay); if (delay == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/NULLDELAY")) uvm_report_error ("UVM/TLM/NULLDELAY", {get_full_name(), ".b_transport() called with 'null' delay"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_imps.svh", 173, "", 1); end return; end m_imp.b_transport(t, delay); endtask endclass class uvm_tlm_nb_transport_fw_imp #(type T=uvm_tlm_generic_payload, type P=uvm_tlm_phase_e, type IMP=int) extends uvm_port_base #(uvm_tlm_if #(T,P)); local IMP m_imp; function new (string name, IMP imp); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); m_imp = imp; m_if_mask = (1<<0); endfunction virtual function string get_type_name(); return "uvm_tlm_nb_transport_fw_imp"; endfunction function uvm_tlm_sync_e nb_transport_fw(T t, ref P p, input uvm_tlm_time delay); if (delay == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/NULLDELAY")) uvm_report_error ("UVM/TLM/NULLDELAY", {get_full_name(), ".nb_transport_fw() called with 'null' delay"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_imps.svh", 190, "", 1); end return UVM_TLM_COMPLETED; end return m_imp.nb_transport_fw(t, p, delay); endfunction endclass class uvm_tlm_nb_transport_bw_imp #(type T=uvm_tlm_generic_payload, type P=uvm_tlm_phase_e, type IMP=int) extends uvm_port_base #(uvm_tlm_if #(T,P)); local IMP m_imp; function new (string name, IMP imp); super.new (name, imp, UVM_IMPLEMENTATION, 1, 1); m_imp = imp; m_if_mask = (1<<1); endfunction virtual function string get_type_name(); return "uvm_tlm_nb_transport_bw_imp"; endfunction function uvm_tlm_sync_e nb_transport_bw(T t, ref P p, input uvm_tlm_time delay); if (delay == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/NULLDELAY")) uvm_report_error ("UVM/TLM/NULLDELAY", {get_full_name(), ".nb_transport_bw() called with 'null' delay"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_imps.svh", 207, "", 1); end return UVM_TLM_COMPLETED; end return m_imp.nb_transport_bw(t, p, delay); endfunction endclass class uvm_tlm_b_transport_port #(type T=uvm_tlm_generic_payload) extends uvm_port_base #(uvm_tlm_if #(T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = (1<<2); endfunction virtual function string get_type_name(); return "uvm_tlm_b_transport_port"; endfunction task b_transport(T t, uvm_tlm_time delay); if (delay == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/NULLDELAY")) uvm_report_error ("UVM/TLM/NULLDELAY", {get_full_name(), ".b_transport() called with 'null' delay"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_ports.svh", 41, "", 1); end return; end this.m_if.b_transport(t, delay); endtask endclass class uvm_tlm_nb_transport_fw_port #(type T=uvm_tlm_generic_payload, type P=uvm_tlm_phase_e) extends uvm_port_base #(uvm_tlm_if #(T,P)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = (1<<0); endfunction virtual function string get_type_name(); return "uvm_tlm_nb_transport_fw_port"; endfunction function uvm_tlm_sync_e nb_transport_fw(T t, ref P p, input uvm_tlm_time delay); if (delay == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/NULLDELAY")) uvm_report_error ("UVM/TLM/NULLDELAY", {get_full_name(), ".nb_transport_fw() called with 'null' delay"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_ports.svh", 59, "", 1); end return UVM_TLM_COMPLETED; end return this.m_if.nb_transport_fw(t, p, delay); endfunction endclass class uvm_tlm_nb_transport_bw_port #(type T=uvm_tlm_generic_payload, type P=uvm_tlm_phase_e) extends uvm_port_base #(uvm_tlm_if #(T,P)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = (1<<1); endfunction virtual function string get_type_name(); return "uvm_tlm_nb_transport_bw_port"; endfunction function uvm_tlm_sync_e nb_transport_bw(T t, ref P p, input uvm_tlm_time delay); if (delay == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/NULLDELAY")) uvm_report_error ("UVM/TLM/NULLDELAY", {get_full_name(), ".nb_transport_bw() called with 'null' delay"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_ports.svh", 78, "", 1); end return UVM_TLM_COMPLETED; end return this.m_if.nb_transport_bw(t, p, delay); endfunction endclass class uvm_tlm_b_transport_export #(type T=uvm_tlm_generic_payload) extends uvm_port_base #(uvm_tlm_if #(T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = (1<<2); endfunction virtual function string get_type_name(); return "uvm_tlm_b_transport_export"; endfunction task b_transport(T t, uvm_tlm_time delay); if (delay == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/NULLDELAY")) uvm_report_error ("UVM/TLM/NULLDELAY", {get_full_name(), ".b_transport() called with 'null' delay"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_exports.svh", 39, "", 1); end return; end this.m_if.b_transport(t, delay); endtask endclass class uvm_tlm_nb_transport_fw_export #(type T=uvm_tlm_generic_payload, type P=uvm_tlm_phase_e) extends uvm_port_base #(uvm_tlm_if #(T,P)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = (1<<0); endfunction virtual function string get_type_name(); return "uvm_tlm_nb_transport_fw_export"; endfunction function uvm_tlm_sync_e nb_transport_fw(T t, ref P p, input uvm_tlm_time delay); if (delay == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/NULLDELAY")) uvm_report_error ("UVM/TLM/NULLDELAY", {get_full_name(), ".nb_transport_fw() called with 'null' delay"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_exports.svh", 53, "", 1); end return UVM_TLM_COMPLETED; end return this.m_if.nb_transport_fw(t, p, delay); endfunction endclass class uvm_tlm_nb_transport_bw_export #(type T=uvm_tlm_generic_payload, type P=uvm_tlm_phase_e) extends uvm_port_base #(uvm_tlm_if #(T,P)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = (1<<1); endfunction virtual function string get_type_name(); return "uvm_tlm_nb_transport_bw_export"; endfunction function uvm_tlm_sync_e nb_transport_bw(T t, ref P p, input uvm_tlm_time delay); if (delay == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/NULLDELAY")) uvm_report_error ("UVM/TLM/NULLDELAY", {get_full_name(), ".nb_transport_bw() called with 'null' delay"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_exports.svh", 68, "", 1); end return UVM_TLM_COMPLETED; end return this.m_if.nb_transport_bw(t, p, delay); endfunction endclass virtual class uvm_tlm_b_target_socket_base #(type T=uvm_tlm_generic_payload) extends uvm_port_base #(uvm_tlm_if #(T)); function new (string name, uvm_component parent); super.new (name, parent, UVM_IMPLEMENTATION, 1, 1); m_if_mask = (1<<2); endfunction virtual function string get_type_name(); return "uvm_tlm_b_target_socket"; endfunction endclass virtual class uvm_tlm_b_initiator_socket_base #(type T=uvm_tlm_generic_payload) extends uvm_port_base #(uvm_tlm_if #(T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = (1<<2); endfunction virtual function string get_type_name(); return "uvm_tlm_b_initiator_socket"; endfunction task b_transport(T t, uvm_tlm_time delay); if (delay == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/NULLDELAY")) uvm_report_error ("UVM/TLM/NULLDELAY", {get_full_name(), ".b_transport() called with 'null' delay"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets_base.svh", 77, "", 1); end return; end this.m_if.b_transport(t, delay); endtask endclass virtual class uvm_tlm_nb_target_socket_base #(type T=uvm_tlm_generic_payload, type P=uvm_tlm_phase_e) extends uvm_port_base #(uvm_tlm_if #(T,P)); uvm_tlm_nb_transport_bw_port #(T,P) bw_port; function new (string name, uvm_component parent); super.new (name, parent, UVM_IMPLEMENTATION, 1, 1); m_if_mask = (1<<0); endfunction virtual function string get_type_name(); return "uvm_tlm_nb_target_socket"; endfunction function uvm_tlm_sync_e nb_transport_bw(T t, ref P p, input uvm_tlm_time delay); if (delay == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/NULLDELAY")) uvm_report_error ("UVM/TLM/NULLDELAY", {get_full_name(), ".nb_transport_bw() called with 'null' delay"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets_base.svh", 102, "", 1); end return UVM_TLM_COMPLETED; end return bw_port.nb_transport_bw(t, p, delay); endfunction endclass virtual class uvm_tlm_nb_initiator_socket_base #(type T=uvm_tlm_generic_payload, type P=uvm_tlm_phase_e) extends uvm_port_base #(uvm_tlm_if #(T,P)); function new (string name, uvm_component parent); super.new (name, parent, UVM_PORT, 1, 1); m_if_mask = (1<<0); endfunction virtual function string get_type_name(); return "uvm_tlm_nb_initiator_socket"; endfunction function uvm_tlm_sync_e nb_transport_fw(T t, ref P p, input uvm_tlm_time delay); if (delay == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/NULLDELAY")) uvm_report_error ("UVM/TLM/NULLDELAY", {get_full_name(), ".nb_transport_fw() called with 'null' delay"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets_base.svh", 125, "", 1); end return UVM_TLM_COMPLETED; end return this.m_if.nb_transport_fw(t, p, delay); endfunction endclass virtual class uvm_tlm_nb_passthrough_initiator_socket_base #(type T=uvm_tlm_generic_payload, type P=uvm_tlm_phase_e) extends uvm_port_base #(uvm_tlm_if #(T,P)); uvm_tlm_nb_transport_bw_export #(T,P) bw_export; function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = (1<<0); bw_export = new("bw_export", get_comp()); endfunction virtual function string get_type_name(); return "uvm_tlm_nb_passthrough_initiator_socket"; endfunction function uvm_tlm_sync_e nb_transport_fw(T t, ref P p, input uvm_tlm_time delay); if (delay == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/NULLDELAY")) uvm_report_error ("UVM/TLM/NULLDELAY", {get_full_name(), ".nb_transport_fw() called with 'null' delay"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets_base.svh", 155, "", 1); end return UVM_TLM_COMPLETED; end return this.m_if.nb_transport_fw(t, p, delay); endfunction function uvm_tlm_sync_e nb_transport_bw(T t, ref P p, input uvm_tlm_time delay); if (delay == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/NULLDELAY")) uvm_report_error ("UVM/TLM/NULLDELAY", {get_full_name(), ".nb_transport_bw() called with 'null' delay"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets_base.svh", 156, "", 1); end return UVM_TLM_COMPLETED; end return bw_export.nb_transport_bw(t, p, delay); endfunction endclass virtual class uvm_tlm_nb_passthrough_target_socket_base #(type T=uvm_tlm_generic_payload, type P=uvm_tlm_phase_e) extends uvm_port_base #(uvm_tlm_if #(T,P)); uvm_tlm_nb_transport_bw_port #(T,P) bw_port; function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = (1<<0); bw_port = new("bw_port", get_comp()); endfunction virtual function string get_type_name(); return "uvm_tlm_nb_passthrough_target_socket"; endfunction function uvm_tlm_sync_e nb_transport_fw(T t, ref P p, input uvm_tlm_time delay); if (delay == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/NULLDELAY")) uvm_report_error ("UVM/TLM/NULLDELAY", {get_full_name(), ".nb_transport_fw() called with 'null' delay"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets_base.svh", 183, "", 1); end return UVM_TLM_COMPLETED; end return this.m_if.nb_transport_fw(t, p, delay); endfunction function uvm_tlm_sync_e nb_transport_bw(T t, ref P p, input uvm_tlm_time delay); if (delay == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/NULLDELAY")) uvm_report_error ("UVM/TLM/NULLDELAY", {get_full_name(), ".nb_transport_bw() called with 'null' delay"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets_base.svh", 184, "", 1); end return UVM_TLM_COMPLETED; end return bw_port.nb_transport_bw(t, p, delay); endfunction endclass virtual class uvm_tlm_b_passthrough_initiator_socket_base #(type T=uvm_tlm_generic_payload) extends uvm_port_base #(uvm_tlm_if #(T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_PORT, min_size, max_size); m_if_mask = (1<<2); endfunction virtual function string get_type_name(); return "uvm_tlm_b_passthrough_initiator_socket"; endfunction task b_transport(T t, uvm_tlm_time delay); if (delay == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/NULLDELAY")) uvm_report_error ("UVM/TLM/NULLDELAY", {get_full_name(), ".b_transport() called with 'null' delay"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets_base.svh", 200, "", 1); end return; end this.m_if.b_transport(t, delay); endtask endclass virtual class uvm_tlm_b_passthrough_target_socket_base #(type T=uvm_tlm_generic_payload) extends uvm_port_base #(uvm_tlm_if #(T)); function new (string name, uvm_component parent, int min_size=1, int max_size=1); super.new (name, parent, UVM_EXPORT, min_size, max_size); m_if_mask = (1<<2); endfunction virtual function string get_type_name(); return "uvm_tlm_b_passthrough_target_socket"; endfunction task b_transport(T t, uvm_tlm_time delay); if (delay == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/NULLDELAY")) uvm_report_error ("UVM/TLM/NULLDELAY", {get_full_name(), ".b_transport() called with 'null' delay"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets_base.svh", 217, "", 1); end return; end this.m_if.b_transport(t, delay); endtask endclass class uvm_tlm_b_initiator_socket #(type T=uvm_tlm_generic_payload) extends uvm_tlm_b_initiator_socket_base #(T); function new(string name, uvm_component parent); super.new(name, parent); endfunction function void connect(this_type provider); uvm_tlm_b_passthrough_initiator_socket_base #(T) initiator_pt_socket; uvm_tlm_b_passthrough_target_socket_base #(T) target_pt_socket; uvm_tlm_b_target_socket_base #(T) target_socket; uvm_component c; super.connect(provider); if($cast(initiator_pt_socket, provider) || $cast(target_pt_socket, provider) || $cast(target_socket, provider)) return; c = get_comp(); begin if (c.uvm_report_enabled(UVM_NONE,UVM_ERROR,get_type_name())) c.uvm_report_error (get_type_name(), "type mismatch in connect -- connection cannot be completed", UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets.svh", 87, "", 1); end endfunction endclass class uvm_tlm_b_target_socket #(type IMP=int, type T=uvm_tlm_generic_payload) extends uvm_tlm_b_target_socket_base #(T); local IMP m_imp; function new (string name, uvm_component parent, IMP imp = null); super.new (name, parent); if (imp == null) $cast(m_imp, parent); else m_imp = imp; if (m_imp == null) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM2/NOIMP")) uvm_report_error ("UVM/TLM2/NOIMP", {"b_target socket ", name, " has no implementation"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets.svh", 121, "", 1); end endfunction function void connect(this_type provider); uvm_component c; super.connect(provider); c = get_comp(); begin if (c.uvm_report_enabled(UVM_NONE,UVM_ERROR,get_type_name())) c.uvm_report_error (get_type_name(), "You cannot call connect() on a target termination socket", UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets.svh", 134, "", 1); end endfunction task b_transport(T t, uvm_tlm_time delay); if (delay == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/NULLDELAY")) uvm_report_error ("UVM/TLM/NULLDELAY", {get_full_name(), ".b_transport() called with 'null' delay"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets.svh", 137, "", 1); end return; end m_imp.b_transport(t, delay); endtask endclass class uvm_tlm_nb_initiator_socket #(type IMP=int, type T=uvm_tlm_generic_payload, type P=uvm_tlm_phase_e) extends uvm_tlm_nb_initiator_socket_base #(T,P); uvm_tlm_nb_transport_bw_imp #(T,P,IMP) bw_imp; function new(string name, uvm_component parent, IMP imp = null); super.new (name, parent); if (imp == null) $cast(imp, parent); if (imp == null) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM2/NOIMP")) uvm_report_error ("UVM/TLM2/NOIMP", {"nb_initiator socket ", name, " has no implementation"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets.svh", 168, "", 1); end bw_imp = new("bw_imp", imp); endfunction function void connect(this_type provider); uvm_tlm_nb_passthrough_initiator_socket_base #(T,P) initiator_pt_socket; uvm_tlm_nb_passthrough_target_socket_base #(T,P) target_pt_socket; uvm_tlm_nb_target_socket_base #(T,P) target_socket; uvm_component c; super.connect(provider); if($cast(initiator_pt_socket, provider)) begin initiator_pt_socket.bw_export.connect(bw_imp); return; end if($cast(target_pt_socket, provider)) begin target_pt_socket.bw_port.connect(bw_imp); return; end if($cast(target_socket, provider)) begin target_socket.bw_port.connect(bw_imp); return; end c = get_comp(); begin if (c.uvm_report_enabled(UVM_NONE,UVM_ERROR,get_type_name())) c.uvm_report_error (get_type_name(), "type mismatch in connect -- connection cannot be completed", UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets.svh", 200, "", 1); end endfunction endclass class uvm_tlm_nb_target_socket #(type IMP=int, type T=uvm_tlm_generic_payload, type P=uvm_tlm_phase_e) extends uvm_tlm_nb_target_socket_base #(T,P); local IMP m_imp; function new (string name, uvm_component parent, IMP imp = null); super.new (name, parent); if (imp == null) $cast(m_imp, parent); else m_imp = imp; bw_port = new("bw_port", get_comp()); if (m_imp == null) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM2/NOIMP")) uvm_report_error ("UVM/TLM2/NOIMP", {"nb_target socket ", name, " has no implementation"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets.svh", 236, "", 1); end endfunction function void connect(this_type provider); uvm_component c; super.connect(provider); c = get_comp(); begin if (c.uvm_report_enabled(UVM_NONE,UVM_ERROR,get_type_name())) c.uvm_report_error (get_type_name(), "You cannot call connect() on a target termination socket", UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets.svh", 249, "", 1); end endfunction function uvm_tlm_sync_e nb_transport_fw(T t, ref P p, input uvm_tlm_time delay); if (delay == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/TLM/NULLDELAY")) uvm_report_error ("UVM/TLM/NULLDELAY", {get_full_name(), ".nb_transport_fw() called with 'null' delay"}, UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets.svh", 252, "", 1); end return UVM_TLM_COMPLETED; end return m_imp.nb_transport_fw(t, p, delay); endfunction endclass class uvm_tlm_b_passthrough_initiator_socket #(type T=uvm_tlm_generic_payload) extends uvm_tlm_b_passthrough_initiator_socket_base #(T); function new(string name, uvm_component parent); super.new(name, parent); endfunction function void connect(this_type provider); uvm_tlm_b_passthrough_initiator_socket_base #(T) initiator_pt_socket; uvm_tlm_b_passthrough_target_socket_base #(T) target_pt_socket; uvm_tlm_b_target_socket_base #(T) target_socket; uvm_component c; super.connect(provider); if($cast(initiator_pt_socket, provider) || $cast(target_pt_socket, provider) || $cast(target_socket, provider)) return; c = get_comp(); begin if (c.uvm_report_enabled(UVM_NONE,UVM_ERROR,get_type_name())) c.uvm_report_error (get_type_name(), "type mismatch in connect -- connection cannot be completed", UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets.svh", 290, "", 1); end endfunction endclass class uvm_tlm_b_passthrough_target_socket #(type T=uvm_tlm_generic_payload) extends uvm_tlm_b_passthrough_target_socket_base #(T); function new(string name, uvm_component parent); super.new(name, parent); endfunction function void connect(this_type provider); uvm_tlm_b_passthrough_target_socket_base #(T) target_pt_socket; uvm_tlm_b_target_socket_base #(T) target_socket; uvm_component c; super.connect(provider); if($cast(target_pt_socket, provider) || $cast(target_socket, provider)) return; c = get_comp(); begin if (c.uvm_report_enabled(UVM_NONE,UVM_ERROR,get_type_name())) c.uvm_report_error (get_type_name(), "type mismatch in connect -- connection cannot be completed", UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets.svh", 323, "", 1); end endfunction endclass class uvm_tlm_nb_passthrough_initiator_socket #(type T=uvm_tlm_generic_payload, type P=uvm_tlm_phase_e) extends uvm_tlm_nb_passthrough_initiator_socket_base #(T,P); function new(string name, uvm_component parent); super.new(name, parent); endfunction function void connect(this_type provider); uvm_tlm_nb_passthrough_initiator_socket_base #(T,P) initiator_pt_socket; uvm_tlm_nb_passthrough_target_socket_base #(T,P) target_pt_socket; uvm_tlm_nb_target_socket_base #(T,P) target_socket; uvm_component c; super.connect(provider); if($cast(initiator_pt_socket, provider)) begin bw_export.connect(initiator_pt_socket.bw_export); return; end if($cast(target_pt_socket, provider)) begin target_pt_socket.bw_port.connect(bw_export); return; end if($cast(target_socket, provider)) begin target_socket.bw_port.connect(bw_export); return; end c = get_comp(); begin if (c.uvm_report_enabled(UVM_NONE,UVM_ERROR,get_type_name())) c.uvm_report_error (get_type_name(), "type mismatch in connect -- connection cannot be completed", UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets.svh", 375, "", 1); end endfunction endclass class uvm_tlm_nb_passthrough_target_socket #(type T=uvm_tlm_generic_payload, type P=uvm_tlm_phase_e) extends uvm_tlm_nb_passthrough_target_socket_base #(T,P); function new(string name, uvm_component parent); super.new(name, parent); endfunction function void connect(this_type provider); uvm_tlm_nb_passthrough_target_socket_base #(T,P) target_pt_socket; uvm_tlm_nb_target_socket_base #(T,P) target_socket; uvm_component c; super.connect(provider); if($cast(target_pt_socket, provider)) begin target_pt_socket.bw_port.connect(bw_port); return; end if($cast(target_socket, provider)) begin target_socket.bw_port.connect(bw_port); return; end c = get_comp(); begin if (c.uvm_report_enabled(UVM_NONE,UVM_ERROR,get_type_name())) c.uvm_report_error (get_type_name(), "type mismatch in connect -- connection cannot be completed", UVM_NONE, "t/uvm/src/tlm2/uvm_tlm2_sockets.svh", 419, "", 1); end endfunction endclass `define UVM_REG_MODEL__SV typedef class uvm_reg_field; typedef class uvm_vreg_field; typedef class uvm_reg; typedef class uvm_reg_file; typedef class uvm_vreg; typedef class uvm_reg_block; typedef class uvm_mem; typedef class uvm_reg_item; typedef class uvm_reg_map; typedef class uvm_reg_map_info; typedef class uvm_reg_sequence; typedef class uvm_reg_adapter; typedef class uvm_reg_indirect_data; typedef bit unsigned [64-1:0] uvm_reg_data_t ; typedef logic unsigned [64-1:0] uvm_reg_data_logic_t ; typedef bit unsigned [64-1:0] uvm_reg_addr_t ; typedef logic unsigned [64-1:0] uvm_reg_addr_logic_t ; typedef bit unsigned [((64-1)/8+1)-1:0] uvm_reg_byte_en_t ; typedef bit [32-1:0] uvm_reg_cvr_t ; typedef struct { string path; int offset; int size; } uvm_hdl_path_slice; typedef uvm_resource_db#(uvm_reg_cvr_t) uvm_reg_cvr_rsrc_db; typedef enum { UVM_IS_OK, UVM_NOT_OK, UVM_HAS_X } uvm_status_e; typedef enum { UVM_FRONTDOOR, UVM_BACKDOOR, UVM_PREDICT, UVM_DEFAULT_DOOR } uvm_door_e; typedef enum { UVM_NO_CHECK, UVM_CHECK } uvm_check_e; typedef enum { UVM_NO_ENDIAN, UVM_LITTLE_ENDIAN, UVM_BIG_ENDIAN, UVM_LITTLE_FIFO, UVM_BIG_FIFO } uvm_endianness_e; typedef enum { UVM_REG, UVM_FIELD, UVM_MEM } uvm_elem_kind_e; typedef enum { UVM_READ, UVM_WRITE, UVM_BURST_READ, UVM_BURST_WRITE } uvm_access_e; typedef enum { UVM_NO_HIER, UVM_HIER } uvm_hier_e; typedef enum { UVM_PREDICT_DIRECT, UVM_PREDICT_READ, UVM_PREDICT_WRITE } uvm_predict_e; typedef enum uvm_reg_cvr_t { UVM_NO_COVERAGE = 'h0000, UVM_CVR_REG_BITS = 'h0001, UVM_CVR_ADDR_MAP = 'h0002, UVM_CVR_FIELD_VALS = 'h0004, UVM_CVR_ALL = -1 } uvm_coverage_model_e; typedef enum bit [63:0] { UVM_DO_REG_HW_RESET = 64'h0000_0000_0000_0001, UVM_DO_REG_BIT_BASH = 64'h0000_0000_0000_0002, UVM_DO_REG_ACCESS = 64'h0000_0000_0000_0004, UVM_DO_MEM_ACCESS = 64'h0000_0000_0000_0008, UVM_DO_SHARED_ACCESS = 64'h0000_0000_0000_0010, UVM_DO_MEM_WALK = 64'h0000_0000_0000_0020, UVM_DO_ALL_REG_MEM_TESTS = 64'hffff_ffff_ffff_ffff } uvm_reg_mem_tests_e; class uvm_hdl_path_concat; uvm_hdl_path_slice slices[]; function void set(uvm_hdl_path_slice t[]); slices = t; endfunction function void add_slice(uvm_hdl_path_slice slice); slices = new [slices.size()+1] (slices); slices[slices.size()-1] = slice; endfunction function void add_path(string path, int unsigned offset = -1, int unsigned size = -1); uvm_hdl_path_slice t; t.offset = offset; t.path = path; t.size = size; add_slice(t); endfunction endclass function automatic string uvm_hdl_concat2string(uvm_hdl_path_concat concat); string image = "{"; if (concat.slices.size() == 1 && concat.slices[0].offset == -1 && concat.slices[0].size == -1) return concat.slices[0].path; foreach (concat.slices[i]) begin uvm_hdl_path_slice slice=concat.slices[i]; image = { image, (i == 0) ? "" : ", ", slice.path }; if (slice.offset >= 0) image = { image, "@", $sformatf("[%0d +: %0d]", slice.offset, slice.size) }; end image = { image, "}" }; return image; endfunction typedef struct packed { uvm_reg_addr_t min; uvm_reg_addr_t max; int unsigned stride; } uvm_reg_map_addr_range; class uvm_reg_item extends uvm_sequence_item; typedef uvm_object_registry#(uvm_reg_item,"uvm_reg_item") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_reg_item tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_reg_item"; endfunction : type_name virtual function string get_type_name(); return "uvm_reg_item"; endfunction : get_type_name uvm_elem_kind_e element_kind; uvm_object element; rand uvm_access_e kind; rand uvm_reg_data_t value[]; constraint max_values { value.size() > 0 && value.size() < 1000; } rand uvm_reg_addr_t offset; uvm_status_e status; uvm_reg_map local_map; uvm_reg_map map; uvm_door_e path; rand uvm_sequence_base parent; int prior = -1; rand uvm_object extension; string bd_kind; string fname; int lineno; function new(string name=""); super.new(name); value = new[1]; endfunction virtual function string convert2string(); string s,value_s; s = {"kind=",kind.name(), " ele_kind=",element_kind.name(), " ele_name=",element==null?"null":element.get_full_name() }; if (value.size() > 1 && uvm_report_enabled(UVM_HIGH, UVM_INFO, "RegModel")) begin value_s = "'{"; foreach (value[i]) value_s = {value_s,$sformatf("%0h,",value[i])}; value_s[value_s.len()-1]="}"; end else value_s = $sformatf("%0h",value[0]); s = {s, " value=",value_s}; if (element_kind == UVM_MEM) s = {s, $sformatf(" offset=%0h",offset)}; s = {s," map=",(map==null?"null":map.get_full_name())," path=",path.name()}; s = {s," status=",status.name()}; return s; endfunction virtual function void do_copy(uvm_object rhs); uvm_reg_item rhs_; if (rhs == null) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"REG/NULL")) uvm_report_fatal ("REG/NULL", "do_copy: rhs argument is null", UVM_NONE, "t/uvm/src/reg/uvm_reg_item.svh", 215, "", 1); end if (!$cast(rhs_,rhs)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"WRONG_TYPE")) uvm_report_error ("WRONG_TYPE", "Provided rhs is not of type uvm_reg_item", UVM_NONE, "t/uvm/src/reg/uvm_reg_item.svh", 218, "", 1); end return; end super.do_copy(rhs); element_kind = rhs_.element_kind; element = rhs_.element; kind = rhs_.kind; value = rhs_.value; offset = rhs_.offset; status = rhs_.status; local_map = rhs_.local_map; map = rhs_.map; path = rhs_.path; extension = rhs_.extension; bd_kind = rhs_.bd_kind; parent = rhs_.parent; prior = rhs_.prior; fname = rhs_.fname; lineno = rhs_.lineno; endfunction endclass typedef struct { uvm_access_e kind; uvm_reg_addr_t addr; uvm_reg_data_t data; int n_bits; uvm_reg_byte_en_t byte_en; uvm_status_e status; } uvm_reg_bus_op; virtual class uvm_reg_adapter extends uvm_object; typedef uvm_abstract_object_registry#(uvm_reg_adapter,"uvm_reg_adapter") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_reg_adapter"; endfunction : type_name virtual function string get_type_name(); return "uvm_reg_adapter"; endfunction : get_type_name function new(string name=""); super.new(name); endfunction bit supports_byte_enable; bit provides_responses; uvm_sequence_base parent_sequence; pure virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); pure virtual function void bus2reg(uvm_sequence_item bus_item, ref uvm_reg_bus_op rw); local uvm_reg_item m_item; virtual function uvm_reg_item get_item(); return m_item; endfunction virtual function void m_set_item(uvm_reg_item item); m_item = item; endfunction endclass class uvm_reg_tlm_adapter extends uvm_reg_adapter; typedef uvm_object_registry#(uvm_reg_tlm_adapter,"uvm_reg_tlm_adapter") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_reg_tlm_adapter tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_reg_tlm_adapter"; endfunction : type_name virtual function string get_type_name(); return "uvm_reg_tlm_adapter"; endfunction : get_type_name function new(string name = "uvm_reg_tlm_adapter"); super.new(name); endfunction virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); uvm_tlm_gp gp = uvm_tlm_gp::type_id::create("tlm_gp",, this.get_full_name()); int nbytes = (rw.n_bits-1)/8+1; uvm_reg_addr_t addr=rw.addr; if (rw.kind == UVM_WRITE) gp.set_command(UVM_TLM_WRITE_COMMAND); else gp.set_command(UVM_TLM_READ_COMMAND); gp.set_address(addr); gp.m_byte_enable = new [nbytes]; gp.m_byte_enable_length = nbytes; gp.set_streaming_width (nbytes); gp.m_data = new [gp.get_streaming_width()]; gp.m_length = nbytes; for (int i = 0; i < nbytes; i++) begin gp.m_data[i] = rw.data[i*8+:8]; gp.m_byte_enable[i] = (i > nbytes) ? 8'h00 : (rw.byte_en[i] ? 8'hFF : 8'h00); end return gp; endfunction virtual function void bus2reg(uvm_sequence_item bus_item, ref uvm_reg_bus_op rw); uvm_tlm_gp gp; int nbytes; if (bus_item == null) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"REG/NULL_ITEM")) uvm_report_fatal ("REG/NULL_ITEM", "bus2reg: bus_item argument is null", UVM_NONE, "t/uvm/src/reg/uvm_reg_adapter.svh", 228, "", 1); end if (!$cast(gp,bus_item)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"WRONG_TYPE")) uvm_report_error ("WRONG_TYPE", "Provided bus_item is not of type uvm_tlm_gp", UVM_NONE, "t/uvm/src/reg/uvm_reg_adapter.svh", 231, "", 1); end return; end if (gp.get_command() == UVM_TLM_WRITE_COMMAND) rw.kind = UVM_WRITE; else rw.kind = UVM_READ; rw.addr = gp.get_address(); rw.byte_en = 0; foreach (gp.m_byte_enable[i]) rw.byte_en[i] = gp.m_byte_enable[i]; rw.data = 0; foreach (gp.m_data[i]) rw.data[i*8+:8] = gp.m_data[i]; rw.status = (gp.is_response_ok()) ? UVM_IS_OK : UVM_NOT_OK; endfunction endclass class uvm_predict_s; bit addr[uvm_reg_addr_t]; uvm_reg_item reg_item; endclass class uvm_reg_predictor #(type BUSTYPE=int) extends uvm_component; typedef uvm_component_registry #(uvm_reg_predictor#(BUSTYPE)) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction uvm_analysis_imp #(BUSTYPE, uvm_reg_predictor #(BUSTYPE)) bus_in; uvm_analysis_port #(uvm_reg_item) reg_ap; uvm_reg_map map; uvm_reg_adapter adapter; function new (string name, uvm_component parent); super.new(name, parent); bus_in = new("bus_in", this); reg_ap = new("reg_ap", this); endfunction static function string type_name(); static string m_type_name; if (m_type_name == "") begin BUSTYPE t; t = BUSTYPE::type_id::create("t"); m_type_name = {"uvm_reg_predictor #(", t.get_type_name(), ")"}; end return m_type_name; endfunction virtual function string get_type_name(); return type_name(); endfunction : get_type_name virtual function void pre_predict(uvm_reg_item rw); endfunction local uvm_predict_s m_pending[uvm_reg]; virtual function void write(BUSTYPE tr); uvm_reg rg; uvm_reg_bus_op rw; if (adapter == null) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"REG/WRITE/NULL")) uvm_report_fatal ("REG/WRITE/NULL", "write: adapter handle is null", UVM_NONE, "t/uvm/src/reg/uvm_reg_predictor.svh", 160, "", 1); end rw.byte_en = -1; adapter.bus2reg(tr,rw); rg = map.get_reg_by_offset(rw.addr, (rw.kind == UVM_READ)); if (rg != null) begin bit found; uvm_reg_item reg_item; uvm_reg_map local_map; uvm_reg_map_info map_info; uvm_predict_s predict_info; uvm_reg_indirect_data ireg; uvm_reg ir; if (!m_pending.exists(rg)) begin uvm_reg_item item = new; predict_info =new; item.element_kind = UVM_REG; item.element = rg; item.path = UVM_PREDICT; item.map = map; item.kind = rw.kind; predict_info.reg_item = item; m_pending[rg] = predict_info; end predict_info = m_pending[rg]; reg_item = predict_info.reg_item; if (predict_info.addr.exists(rw.addr)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"REG_PREDICT_COLLISION")) uvm_report_error ("REG_PREDICT_COLLISION", {"Collision detected for register '", rg.get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_predictor.svh", 194, "", 1); end m_pending.delete(rg); end local_map = rg.get_local_map(map); map_info = local_map.get_reg_map_info(rg); ir=($cast(ireg, rg))?ireg.get_indirect_reg():rg; foreach (map_info.addr[i]) begin if (rw.addr == map_info.addr[i]) begin found = 1; reg_item.value[0] |= rw.data << (i * map.get_n_bytes()*8); predict_info.addr[rw.addr] = 1; if (predict_info.addr.num() == map_info.addr.size()) begin uvm_predict_e predict_kind = (reg_item.kind == UVM_WRITE) ? UVM_PREDICT_WRITE : UVM_PREDICT_READ; if (reg_item.kind == UVM_READ && local_map.get_check_on_read() && reg_item.status != UVM_NOT_OK) begin void'(rg.do_check(ir.get_mirrored_value(), reg_item.value[0], local_map)); end pre_predict(reg_item); ir.XsampleX(reg_item.value[0], rw.byte_en, reg_item.kind == UVM_READ, local_map); begin uvm_reg_block blk = rg.get_parent(); blk.XsampleX(map_info.offset, reg_item.kind == UVM_READ, local_map); end rg.do_predict(reg_item, predict_kind, rw.byte_en); if(reg_item.kind == UVM_WRITE) begin if (uvm_report_enabled(UVM_HIGH,UVM_INFO,"REG_PREDICT")) uvm_report_info ("REG_PREDICT", {"Observed WRITE transaction to register ", ir.get_full_name(), ": value='h", $sformatf("%0h",reg_item.value[0]), " : updated value = 'h", $sformatf("%0h",ir.get())}, UVM_HIGH, "t/uvm/src/reg/uvm_reg_predictor.svh", 235, "", 1); end else begin if (uvm_report_enabled(UVM_HIGH,UVM_INFO,"REG_PREDICT")) uvm_report_info ("REG_PREDICT", {"Observed READ transaction to register ", ir.get_full_name(), ": value='h", $sformatf("%0h",reg_item.value[0])}, UVM_HIGH, "t/uvm/src/reg/uvm_reg_predictor.svh", 239, "", 1); end reg_ap.write(reg_item); m_pending.delete(rg); end break; end end if (!found) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"REG_PREDICT_INTERNAL")) uvm_report_error ("REG_PREDICT_INTERNAL", {"Unexpected failed address lookup for register '", rg.get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_predictor.svh", 248, "", 1); end end else begin begin if (uvm_report_enabled(UVM_FULL,UVM_INFO,"REG_PREDICT_NOT_FOR_ME")) uvm_report_info ("REG_PREDICT_NOT_FOR_ME", {"Observed transaction does not target a register: ", $sformatf("%p",tr)}, UVM_FULL, "t/uvm/src/reg/uvm_reg_predictor.svh", 253, "", 1); end end endfunction virtual function void check_phase(uvm_phase phase); string q[$]; super.check_phase(phase); foreach (m_pending[l]) begin uvm_reg rg=l; q.push_back($sformatf("\n%s",rg.get_full_name())); end if (m_pending.num() > 0) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"PENDING REG ITEMS")) uvm_report_error ("PENDING REG ITEMS", $sformatf("There are %0d incomplete register transactions still pending completion:%s",m_pending.num(),uvm_pkg::m_uvm_string_queue_join(q)), UVM_NONE, "t/uvm/src/reg/uvm_reg_predictor.svh", 274, "", 1); end end endfunction endclass class uvm_reg_sequence #(type BASE=uvm_sequence #(uvm_reg_item)) extends BASE; typedef uvm_object_registry #(uvm_reg_sequence #(BASE)) type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_reg_sequence #(BASE) tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction uvm_reg_block model; uvm_reg_adapter adapter; uvm_sequencer #(uvm_reg_item) reg_seqr; function new (string name="uvm_reg_sequence_inst"); super.new(name); endfunction virtual task body(); if (m_sequencer == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"NO_SEQR")) uvm_report_fatal ("NO_SEQR", {"Sequence executing as translation sequence, ", "but is not associated with a sequencer (m_sequencer == null)"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_sequence.svh", 127, "", 1); end end if (reg_seqr == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"REG_XLATE_NO_SEQR")) uvm_report_warning ("REG_XLATE_NO_SEQR", {"Executing RegModel translation sequence on sequencer ", m_sequencer.get_full_name(),"' does not have an upstream sequencer defined. ", "Execution of register items available only via direct calls to 'do_reg_item'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_sequence.svh", 133, "", 1); end wait(0); end begin if (uvm_report_enabled(UVM_LOW,UVM_INFO,"REG_XLATE_SEQ_START")) uvm_report_info ("REG_XLATE_SEQ_START", {"Starting RegModel translation sequence on sequencer ", m_sequencer.get_full_name(),"'"}, UVM_LOW, "t/uvm/src/reg/uvm_reg_sequence.svh", 138, "", 1); end forever begin uvm_reg_item reg_item; reg_seqr.peek(reg_item); do_reg_item(reg_item); reg_seqr.get(reg_item); #0; end endtask typedef enum { LOCAL, UPSTREAM } seq_parent_e; seq_parent_e parent_select = LOCAL; uvm_sequence_base upstream_parent; virtual task do_reg_item(uvm_reg_item rw); string rws=rw.convert2string(); if (m_sequencer == null) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"REG/DO_ITEM/NULL")) uvm_report_fatal ("REG/DO_ITEM/NULL", "do_reg_item: m_sequencer is null", UVM_NONE, "t/uvm/src/reg/uvm_reg_sequence.svh", 161, "", 1); end if (adapter == null) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"REG/DO_ITEM/NULL")) uvm_report_fatal ("REG/DO_ITEM/NULL", "do_reg_item: adapter handle is null", UVM_NONE, "t/uvm/src/reg/uvm_reg_sequence.svh", 163, "", 1); end begin if (uvm_report_enabled(UVM_HIGH,UVM_INFO,"DO_RW_ACCESS")) uvm_report_info ("DO_RW_ACCESS", {"Doing transaction: ",rws}, UVM_HIGH, "t/uvm/src/reg/uvm_reg_sequence.svh", 165, "", 1); end if (parent_select == LOCAL) begin upstream_parent = rw.parent; rw.parent = this; end if (rw.kind == UVM_WRITE) rw.local_map.do_bus_write(rw, m_sequencer, adapter); else rw.local_map.do_bus_read(rw, m_sequencer, adapter); if (parent_select == LOCAL) rw.parent = upstream_parent; endtask virtual task write_reg(input uvm_reg rg, output uvm_status_e status, input uvm_reg_data_t value, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); if (rg == null) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"NO_REG")) uvm_report_error ("NO_REG", "Register argument is null", UVM_NONE, "t/uvm/src/reg/uvm_reg_sequence.svh", 211, "", 1); end else rg.write(status,value,path,map,this,prior,extension,fname,lineno); endtask virtual task read_reg(input uvm_reg rg, output uvm_status_e status, output uvm_reg_data_t value, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); if (rg == null) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"NO_REG")) uvm_report_error ("NO_REG", "Register argument is null", UVM_NONE, "t/uvm/src/reg/uvm_reg_sequence.svh", 229, "", 1); end else rg.read(status,value,path,map,this,prior,extension,fname,lineno); endtask virtual task poke_reg(input uvm_reg rg, output uvm_status_e status, input uvm_reg_data_t value, input string kind = "", input uvm_object extension = null, input string fname = "", input int lineno = 0); if (rg == null) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"NO_REG")) uvm_report_error ("NO_REG", "Register argument is null", UVM_NONE, "t/uvm/src/reg/uvm_reg_sequence.svh", 246, "", 1); end else rg.poke(status,value,kind,this,extension,fname,lineno); endtask virtual task peek_reg(input uvm_reg rg, output uvm_status_e status, output uvm_reg_data_t value, input string kind = "", input uvm_object extension = null, input string fname = "", input int lineno = 0); if (rg == null) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"NO_REG")) uvm_report_error ("NO_REG", "Register argument is null", UVM_NONE, "t/uvm/src/reg/uvm_reg_sequence.svh", 263, "", 1); end else rg.peek(status,value,kind,this,extension,fname,lineno); endtask virtual task update_reg(input uvm_reg rg, output uvm_status_e status, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); if (rg == null) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"NO_REG")) uvm_report_error ("NO_REG", "Register argument is null", UVM_NONE, "t/uvm/src/reg/uvm_reg_sequence.svh", 281, "", 1); end else rg.update(status,path,map,this,prior,extension,fname,lineno); endtask virtual task mirror_reg(input uvm_reg rg, output uvm_status_e status, input uvm_check_e check = UVM_NO_CHECK, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); if (rg == null) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"NO_REG")) uvm_report_error ("NO_REG", "Register argument is null", UVM_NONE, "t/uvm/src/reg/uvm_reg_sequence.svh", 300, "", 1); end else rg.mirror(status,check,path,map,this,prior,extension,fname,lineno); endtask virtual task write_mem(input uvm_mem mem, output uvm_status_e status, input uvm_reg_addr_t offset, input uvm_reg_data_t value, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); if (mem == null) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"NO_MEM")) uvm_report_error ("NO_MEM", "Memory argument is null", UVM_NONE, "t/uvm/src/reg/uvm_reg_sequence.svh", 320, "", 1); end else mem.write(status,offset,value,path,map,this,prior,extension,fname,lineno); endtask virtual task read_mem(input uvm_mem mem, output uvm_status_e status, input uvm_reg_addr_t offset, output uvm_reg_data_t value, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); if (mem == null) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"NO_MEM")) uvm_report_error ("NO_MEM", "Memory argument is null", UVM_NONE, "t/uvm/src/reg/uvm_reg_sequence.svh", 339, "", 1); end else mem.read(status,offset,value,path,map,this,prior,extension,fname,lineno); endtask virtual task poke_mem(input uvm_mem mem, output uvm_status_e status, input uvm_reg_addr_t offset, input uvm_reg_data_t value, input string kind = "", input uvm_object extension = null, input string fname = "", input int lineno = 0); if (mem == null) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"NO_MEM")) uvm_report_error ("NO_MEM", "Memory argument is null", UVM_NONE, "t/uvm/src/reg/uvm_reg_sequence.svh", 357, "", 1); end else mem.poke(status,offset,value,kind,this,extension,fname,lineno); endtask virtual task peek_mem(input uvm_mem mem, output uvm_status_e status, input uvm_reg_addr_t offset, output uvm_reg_data_t value, input string kind = "", input uvm_object extension = null, input string fname = "", input int lineno = 0); if (mem == null) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"NO_MEM")) uvm_report_error ("NO_MEM", "Memory argument is null", UVM_NONE, "t/uvm/src/reg/uvm_reg_sequence.svh", 375, "", 1); end else mem.peek(status,offset,value,kind,this,extension,fname,lineno); endtask virtual function void put_response(uvm_sequence_item response_item); put_base_response(response_item); endfunction endclass virtual class uvm_reg_frontdoor extends uvm_reg_sequence #(uvm_sequence #(uvm_sequence_item)); typedef uvm_abstract_object_registry#(uvm_reg_frontdoor,"uvm_reg_frontdoor") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_reg_frontdoor"; endfunction : type_name virtual function string get_type_name(); return "uvm_reg_frontdoor"; endfunction : get_type_name uvm_reg_item rw_info; uvm_sequencer_base sequencer; function new(string name=""); super.new(name); endfunction string fname; int lineno; endclass: uvm_reg_frontdoor typedef class uvm_reg; typedef class uvm_mem; typedef class uvm_reg_backdoor; class uvm_reg_cbs extends uvm_callback; typedef uvm_object_registry#(uvm_reg_cbs,"uvm_reg_cbs") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_reg_cbs tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_reg_cbs"; endfunction : type_name virtual function string get_type_name(); return "uvm_reg_cbs"; endfunction : get_type_name function new(string name = "uvm_reg_cbs"); super.new(name); endfunction virtual task pre_write(uvm_reg_item rw); endtask virtual task post_write(uvm_reg_item rw); endtask virtual task pre_read(uvm_reg_item rw); endtask virtual task post_read(uvm_reg_item rw); endtask virtual function void post_predict(input uvm_reg_field fld, input uvm_reg_data_t previous, inout uvm_reg_data_t value, input uvm_predict_e kind, input uvm_door_e path, input uvm_reg_map map); endfunction virtual function void encode(ref uvm_reg_data_t data[]); endfunction virtual function void decode(ref uvm_reg_data_t data[]); endfunction endclass typedef uvm_callbacks#(uvm_reg, uvm_reg_cbs) uvm_reg_cb ; typedef uvm_callback_iter#(uvm_reg, uvm_reg_cbs) uvm_reg_cb_iter ; typedef uvm_callbacks#(uvm_reg_backdoor, uvm_reg_cbs) uvm_reg_bd_cb ; typedef uvm_callback_iter#(uvm_reg_backdoor, uvm_reg_cbs) uvm_reg_bd_cb_iter ; typedef uvm_callbacks#(uvm_mem, uvm_reg_cbs) uvm_mem_cb ; typedef uvm_callback_iter#(uvm_mem, uvm_reg_cbs) uvm_mem_cb_iter ; typedef uvm_callbacks#(uvm_reg_field, uvm_reg_cbs) uvm_reg_field_cb ; typedef uvm_callback_iter#(uvm_reg_field, uvm_reg_cbs) uvm_reg_field_cb_iter ; class uvm_reg_read_only_cbs extends uvm_reg_cbs; function new(string name = "uvm_reg_read_only_cbs"); super.new(name); endfunction typedef uvm_object_registry#(uvm_reg_read_only_cbs,"uvm_reg_read_only_cbs") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_reg_read_only_cbs tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_reg_read_only_cbs"; endfunction : type_name virtual function string get_type_name(); return "uvm_reg_read_only_cbs"; endfunction : get_type_name virtual task pre_write(uvm_reg_item rw); string name = rw.element.get_full_name(); if (rw.status != UVM_IS_OK) return; if (rw.element_kind == UVM_FIELD) begin uvm_reg_field fld; uvm_reg rg; $cast(fld, rw.element); rg = fld.get_parent(); name = rg.get_full_name(); end begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/REG/READONLY")) uvm_report_error ("UVM/REG/READONLY", {name, " is read-only. Cannot call write() method."}, UVM_NONE, "t/uvm/src/reg/uvm_reg_cbs.svh", 232, "", 1); end rw.status = UVM_NOT_OK; endtask local static uvm_reg_read_only_cbs m_me; local static function uvm_reg_read_only_cbs get(); if (m_me == null) m_me = new; return m_me; endfunction static function void add(uvm_reg rg); uvm_reg_field flds[$]; uvm_reg_cb::add(rg, get()); rg.get_fields(flds); foreach (flds[i]) begin uvm_reg_field_cb::add(flds[i], get()); end endfunction static function void remove(uvm_reg rg); uvm_reg_cb_iter cbs = new(rg); uvm_reg_field flds[$]; void'(cbs.first()); while (cbs.get_cb() != get()) begin if (cbs.get_cb() == null) return; void'(cbs.next()); end uvm_reg_cb::delete(rg, get()); rg.get_fields(flds); foreach (flds[i]) begin uvm_reg_field_cb::delete(flds[i], get()); end endfunction endclass class uvm_reg_write_only_cbs extends uvm_reg_cbs; function new(string name = "uvm_reg_write_only_cbs"); super.new(name); endfunction typedef uvm_object_registry#(uvm_reg_write_only_cbs,"uvm_reg_write_only_cbs") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_reg_write_only_cbs tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_reg_write_only_cbs"; endfunction : type_name virtual function string get_type_name(); return "uvm_reg_write_only_cbs"; endfunction : get_type_name virtual task pre_read(uvm_reg_item rw); string name = rw.element.get_full_name(); if (rw.status != UVM_IS_OK) return; if (rw.element_kind == UVM_FIELD) begin uvm_reg_field fld; uvm_reg rg; $cast(fld, rw.element); rg = fld.get_parent(); name = rg.get_full_name(); end begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/REG/WRTEONLY")) uvm_report_error ("UVM/REG/WRTEONLY", {name, " is write-only. Cannot call read() method."}, UVM_NONE, "t/uvm/src/reg/uvm_reg_cbs.svh", 316, "", 1); end rw.status = UVM_NOT_OK; endtask local static uvm_reg_write_only_cbs m_me; local static function uvm_reg_write_only_cbs get(); if (m_me == null) m_me = new; return m_me; endfunction static function void add(uvm_reg rg); uvm_reg_field flds[$]; uvm_reg_cb::add(rg, get()); rg.get_fields(flds); foreach (flds[i]) begin uvm_reg_field_cb::add(flds[i], get()); end endfunction static function void remove(uvm_reg rg); uvm_reg_cb_iter cbs = new(rg); uvm_reg_field flds[$]; void'(cbs.first()); while (cbs.get_cb() != get()) begin if (cbs.get_cb() == null) return; void'(cbs.next()); end uvm_reg_cb::delete(rg, get()); rg.get_fields(flds); foreach (flds[i]) begin uvm_reg_field_cb::delete(flds[i], get()); end endfunction endclass typedef class uvm_reg_cbs; virtual class uvm_reg_backdoor extends uvm_object; typedef uvm_abstract_object_registry#(uvm_reg_backdoor,"uvm_reg_backdoor") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_reg_backdoor"; endfunction : type_name virtual function string get_type_name(); return "uvm_reg_backdoor"; endfunction : get_type_name function new(string name = ""); super.new(name); endfunction: new protected task do_pre_read(uvm_reg_item rw); pre_read(rw); begin uvm_callback_iter#(uvm_reg_backdoor,uvm_reg_cbs) iter = new(this); uvm_reg_cbs cb = iter.first(); while(cb != null) begin cb.pre_read(rw); cb = iter.next(); end end endtask protected task do_post_read(uvm_reg_item rw); uvm_callback_iter#(uvm_reg_backdoor, uvm_reg_cbs) iter = new(this); for(uvm_reg_cbs cb = iter.last(); cb != null; cb=iter.prev()) cb.decode(rw.value); begin uvm_callback_iter#(uvm_reg_backdoor,uvm_reg_cbs) iter = new(this); uvm_reg_cbs cb = iter.first(); while(cb != null) begin cb.post_read(rw); cb = iter.next(); end end post_read(rw); endtask protected task do_pre_write(uvm_reg_item rw); uvm_callback_iter#(uvm_reg_backdoor, uvm_reg_cbs) iter = new(this); pre_write(rw); begin uvm_callback_iter#(uvm_reg_backdoor,uvm_reg_cbs) iter = new(this); uvm_reg_cbs cb = iter.first(); while(cb != null) begin cb.pre_write(rw); cb = iter.next(); end end for(uvm_reg_cbs cb = iter.first(); cb != null; cb = iter.next()) cb.encode(rw.value); endtask protected task do_post_write(uvm_reg_item rw); begin uvm_callback_iter#(uvm_reg_backdoor,uvm_reg_cbs) iter = new(this); uvm_reg_cbs cb = iter.first(); while(cb != null) begin cb.post_write(rw); cb = iter.next(); end end post_write(rw); endtask extern virtual task write(uvm_reg_item rw); extern virtual task read(uvm_reg_item rw); extern virtual function void read_func(uvm_reg_item rw); extern virtual function bit is_auto_updated(uvm_reg_field field); extern virtual local task wait_for_change(uvm_object element); extern function void start_update_thread(uvm_object element); extern function void kill_update_thread(uvm_object element); extern function bit has_update_threads(); virtual task pre_read(uvm_reg_item rw); endtask virtual task post_read(uvm_reg_item rw); endtask virtual task pre_write(uvm_reg_item rw); endtask virtual task post_write(uvm_reg_item rw); endtask string fname; int lineno; local process m_update_thread[uvm_object]; static local bit m_register_cb_uvm_reg_cbs = uvm_callbacks#(uvm_reg_backdoor,uvm_reg_cbs)::m_register_pair("uvm_reg_backdoor","uvm_reg_cbs"); endclass: uvm_reg_backdoor function bit uvm_reg_backdoor::is_auto_updated(uvm_reg_field field); return 0; endfunction task uvm_reg_backdoor::wait_for_change(uvm_object element); begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"RegModel")) uvm_report_fatal ("RegModel", "uvm_reg_backdoor::wait_for_change() method has not been overloaded", UVM_NONE, "t/uvm/src/reg/uvm_reg_backdoor.svh", 171, "", 1); end endtask function void uvm_reg_backdoor::start_update_thread(uvm_object element); uvm_reg rg; if (this.m_update_thread.exists(element)) begin this.kill_update_thread(element); end if (!$cast(rg,element)) return; fork begin uvm_reg_field fields[$]; this.m_update_thread[element] = process::self(); rg.get_fields(fields); forever begin uvm_status_e status; uvm_reg_data_t val; uvm_reg_item r_item = new("bd_r_item"); r_item.element = rg; r_item.element_kind = UVM_REG; this.read(r_item); val = r_item.value[0]; if (r_item.status != UVM_IS_OK) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Backdoor read of register '%s' failed.", rg.get_name()), UVM_NONE, "t/uvm/src/reg/uvm_reg_backdoor.svh", 206, "", 1); end end foreach (fields[i]) begin if (this.is_auto_updated(fields[i])) begin r_item.value[0] = (val >> fields[i].get_lsb_pos()) & ((1 << fields[i].get_n_bits())-1); fields[i].do_predict(r_item); end end this.wait_for_change(element); end end join_none endfunction function void uvm_reg_backdoor::kill_update_thread(uvm_object element); if (this.m_update_thread.exists(element)) begin this.m_update_thread[element].kill(); this.m_update_thread.delete(element); end endfunction function bit uvm_reg_backdoor::has_update_threads(); return this.m_update_thread.num() > 0; endfunction task uvm_reg_backdoor::write(uvm_reg_item rw); begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"RegModel")) uvm_report_fatal ("RegModel", "uvm_reg_backdoor::write() method has not been overloaded", UVM_NONE, "t/uvm/src/reg/uvm_reg_backdoor.svh", 248, "", 1); end endtask task uvm_reg_backdoor::read(uvm_reg_item rw); do_pre_read(rw); read_func(rw); do_post_read(rw); endtask function void uvm_reg_backdoor::read_func(uvm_reg_item rw); begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"RegModel")) uvm_report_fatal ("RegModel", "uvm_reg_backdoor::read_func() method has not been overloaded", UVM_NONE, "t/uvm/src/reg/uvm_reg_backdoor.svh", 264, "", 1); end rw.status = UVM_NOT_OK; endfunction typedef class uvm_reg_cbs; class uvm_reg_field extends uvm_object; rand uvm_reg_data_t value; local uvm_reg_data_t m_mirrored; local uvm_reg_data_t m_desired; local string m_access; local uvm_reg m_parent; local int unsigned m_lsb; local int unsigned m_size; local bit m_volatile; local uvm_reg_data_t m_reset[string]; local bit m_written; local bit m_read_in_progress; local bit m_write_in_progress; local string m_fname; local int m_lineno; local int m_cover_on; local bit m_individually_accessible; local uvm_check_e m_check; local static int m_max_size; local static bit m_policy_names[string]; constraint uvm_reg_field_valid { if (64 > m_size) { value < (64'h1 << m_size); } } typedef uvm_object_registry#(uvm_reg_field,"uvm_reg_field") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_reg_field tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_reg_field"; endfunction : type_name virtual function string get_type_name(); return "uvm_reg_field"; endfunction : get_type_name extern function new(string name = "uvm_reg_field"); extern function void configure(uvm_reg parent, int unsigned size, int unsigned lsb_pos, string access, bit volatile, uvm_reg_data_t reset, bit has_reset, bit is_rand, bit individually_accessible); extern virtual function string get_full_name(); extern virtual function uvm_reg get_parent(); extern virtual function uvm_reg get_register(); extern virtual function int unsigned get_lsb_pos(); extern virtual function int unsigned get_n_bits(); extern static function int unsigned get_max_size(); extern virtual function string set_access(string mode); extern static function bit define_access(string name); local static bit m_predefined = m_predefine_policies(); extern local static function bit m_predefine_policies(); extern virtual function string get_access(uvm_reg_map map = null); extern virtual function bit is_known_access(uvm_reg_map map = null); extern virtual function void set_volatility(bit volatile); extern virtual function bit is_volatile(); extern virtual function void set(uvm_reg_data_t value, string fname = "", int lineno = 0); extern virtual function uvm_reg_data_t get(string fname = "", int lineno = 0); extern virtual function uvm_reg_data_t get_mirrored_value(string fname = "", int lineno = 0); extern virtual function void reset(string kind = "HARD"); extern virtual function uvm_reg_data_t get_reset(string kind = "HARD"); extern virtual function bit has_reset(string kind = "HARD", bit delete = 0); extern virtual function void set_reset(uvm_reg_data_t value, string kind = "HARD"); extern virtual function bit needs_update(); extern virtual task write (output uvm_status_e status, input uvm_reg_data_t value, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); extern virtual task read (output uvm_status_e status, output uvm_reg_data_t value, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); extern virtual task poke (output uvm_status_e status, input uvm_reg_data_t value, input string kind = "", input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); extern virtual task peek (output uvm_status_e status, output uvm_reg_data_t value, input string kind = "", input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); extern virtual task mirror(output uvm_status_e status, input uvm_check_e check = UVM_NO_CHECK, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); extern function void set_compare(uvm_check_e check=UVM_CHECK); extern function uvm_check_e get_compare(); extern function bit is_indv_accessible (uvm_door_e path, uvm_reg_map local_map); extern function bit predict (uvm_reg_data_t value, uvm_reg_byte_en_t be = -1, uvm_predict_e kind = UVM_PREDICT_DIRECT, uvm_door_e path = UVM_FRONTDOOR, uvm_reg_map map = null, string fname = "", int lineno = 0); extern virtual function uvm_reg_data_t XpredictX (uvm_reg_data_t cur_val, uvm_reg_data_t wr_val, uvm_reg_map map); extern virtual function uvm_reg_data_t XupdateX(); extern function bit Xcheck_accessX (input uvm_reg_item rw, output uvm_reg_map_info map_info); extern virtual task do_write(uvm_reg_item rw); extern virtual task do_read(uvm_reg_item rw); extern virtual function void do_predict (uvm_reg_item rw, uvm_predict_e kind=UVM_PREDICT_DIRECT, uvm_reg_byte_en_t be = -1); extern function void pre_randomize(); extern function void post_randomize(); static local bit m_register_cb_uvm_reg_cbs = uvm_callbacks#(uvm_reg_field,uvm_reg_cbs)::m_register_pair("uvm_reg_field","uvm_reg_cbs"); virtual task pre_write (uvm_reg_item rw); endtask virtual task post_write (uvm_reg_item rw); endtask virtual task pre_read (uvm_reg_item rw); endtask virtual task post_read (uvm_reg_item rw); endtask extern virtual function void do_print (uvm_printer printer); extern virtual function string convert2string; extern virtual function uvm_object clone(); extern virtual function void do_copy (uvm_object rhs); extern virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); extern virtual function void do_pack (uvm_packer packer); extern virtual function void do_unpack (uvm_packer packer); endclass: uvm_reg_field function uvm_reg_field::new(string name = "uvm_reg_field"); super.new(name); endfunction: new function void uvm_reg_field::configure(uvm_reg parent, int unsigned size, int unsigned lsb_pos, string access, bit volatile, uvm_reg_data_t reset, bit has_reset, bit is_rand, bit individually_accessible); m_parent = parent; if (size == 0) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Field \"%s\" cannot have 0 bits", get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_reg_field.svh", 416, "", 1); end size = 1; end m_size = size; m_volatile = volatile; m_access = access.toupper(); m_lsb = lsb_pos; m_cover_on = UVM_NO_COVERAGE; m_written = 0; m_check = volatile ? UVM_NO_CHECK : UVM_CHECK; m_individually_accessible = individually_accessible; if (has_reset) set_reset(reset); m_parent.add_field(this); if (!m_policy_names.exists(m_access)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Access policy '",access, "' for field '",get_full_name(),"' is not defined. Setting to RW"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_field.svh", 436, "", 1); end m_access = "RW"; end if (size > m_max_size) m_max_size = size; case (access) "RO", "RC", "RS", "WC", "WS", "W1C", "W1S", "W1T", "W0C", "W0S", "W0T", "W1SRC", "W1CRS", "W0SRC", "W0CRS", "WSRC", "WCRS", "WOC", "WOS": is_rand = 0; endcase if (!is_rand) value.rand_mode(0); endfunction: configure function uvm_reg uvm_reg_field::get_parent(); return m_parent; endfunction: get_parent function string uvm_reg_field::get_full_name(); return {m_parent.get_full_name(), ".", get_name()}; endfunction: get_full_name function uvm_reg uvm_reg_field::get_register(); return m_parent; endfunction: get_register function int unsigned uvm_reg_field::get_lsb_pos(); return m_lsb; endfunction: get_lsb_pos function int unsigned uvm_reg_field::get_n_bits(); return m_size; endfunction: get_n_bits function int unsigned uvm_reg_field::get_max_size(); return m_max_size; endfunction: get_max_size function bit uvm_reg_field::is_known_access(uvm_reg_map map = null); string acc = get_access(map); case (acc) "RO", "RW", "RC", "RS", "WC", "WS", "W1C", "W1S", "W1T", "W0C", "W0S", "W0T", "WRC", "WRS", "W1SRC", "W1CRS", "W0SRC", "W0CRS", "WSRC", "WCRS", "WO", "WOC", "WOS", "W1", "WO1" : return 1; endcase return 0; endfunction function string uvm_reg_field::get_access(uvm_reg_map map = null); string field_access = m_access; if (map == uvm_reg_map::backdoor()) return field_access; case (m_parent.get_rights(map)) "RW": return field_access; "RO": case (field_access) "RW", "RO", "WC", "WS", "W1C", "W1S", "W1T", "W0C", "W0S", "W0T", "W1" : field_access = "RO"; "RC", "WRC", "W1SRC", "W0SRC", "WSRC" : field_access = "RC"; "RS", "WRS", "W1CRS", "W0CRS", "WCRS" : field_access = "RS"; "WO", "WOC", "WOS", "WO1": begin field_access = "NOACCESS"; end endcase "WO": case (field_access) "RW","WRC","WRS" : field_access = "WO"; "W1SRC" : field_access = "W1S"; "W0SRC": field_access = "W0S"; "W1CRS": field_access = "W1C"; "W0CRS": field_access = "W0C"; "WCRS": field_access = "WC"; "W1" : field_access = "W1"; "WO1" : field_access = "WO1"; "WSRC" : field_access = "WS"; "RO","RC","RS": field_access = "NOACCESS"; endcase default: begin field_access = "NOACCESS"; begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Register '",m_parent.get_full_name(), "' containing field '",get_name(),"' is mapped in map '", map.get_full_name(),"' with unknown access right '", m_parent.get_rights(map), "'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_field.svh", 570, "", 1); end end endcase return field_access; endfunction: get_access function string uvm_reg_field::set_access(string mode); set_access = m_access; m_access = mode.toupper(); if (!m_policy_names.exists(m_access)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Access policy '",m_access, "' is not a defined field access policy"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_field.svh", 584, "", 1); end m_access = set_access; end endfunction: set_access function bit uvm_reg_field::define_access(string name); if (!m_predefined) m_predefined = m_predefine_policies(); name = name.toupper(); if (m_policy_names.exists(name)) return 0; m_policy_names[name] = 1; return 1; endfunction function bit uvm_reg_field::m_predefine_policies(); if (m_predefined) return 1; m_predefined = 1; void'(define_access("RO")); void'(define_access("RW")); void'(define_access("RC")); void'(define_access("RS")); void'(define_access("WRC")); void'(define_access("WRS")); void'(define_access("WC")); void'(define_access("WS")); void'(define_access("WSRC")); void'(define_access("WCRS")); void'(define_access("W1C")); void'(define_access("W1S")); void'(define_access("W1T")); void'(define_access("W0C")); void'(define_access("W0S")); void'(define_access("W0T")); void'(define_access("W1SRC")); void'(define_access("W1CRS")); void'(define_access("W0SRC")); void'(define_access("W0CRS")); void'(define_access("WO")); void'(define_access("WOC")); void'(define_access("WOS")); void'(define_access("W1")); void'(define_access("WO1")); return 1; endfunction function void uvm_reg_field::set_volatility(bit volatile); m_volatile = volatile; endfunction function bit uvm_reg_field::is_volatile(); return m_volatile; endfunction function uvm_reg_data_t uvm_reg_field::XpredictX (uvm_reg_data_t cur_val, uvm_reg_data_t wr_val, uvm_reg_map map); uvm_reg_data_t mask = ('b1 << m_size)-1; case (get_access(map)) "RO": return cur_val; "RW": return wr_val; "RC": return cur_val; "RS": return cur_val; "WC": return '0; "WS": return mask; "WRC": return wr_val; "WRS": return wr_val; "WSRC": return mask; "WCRS": return '0; "W1C": return cur_val & (~wr_val); "W1S": return cur_val | wr_val; "W1T": return cur_val ^ wr_val; "W0C": return cur_val & wr_val; "W0S": return cur_val | (~wr_val & mask); "W0T": return cur_val ^ (~wr_val & mask); "W1SRC": return cur_val | wr_val; "W1CRS": return cur_val & (~wr_val); "W0SRC": return cur_val | (~wr_val & mask); "W0CRS": return cur_val & wr_val; "WO": return wr_val; "WOC": return '0; "WOS": return mask; "W1": return (m_written) ? cur_val : wr_val; "WO1": return (m_written) ? cur_val : wr_val; "NOACCESS": return cur_val; default: return wr_val; endcase begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"RegModel")) uvm_report_fatal ("RegModel", "uvm_reg_field::XpredictX(): Internal error", UVM_NONE, "t/uvm/src/reg/uvm_reg_field.svh", 691, "", 1); end return 0; endfunction: XpredictX function bit uvm_reg_field::predict (uvm_reg_data_t value, uvm_reg_byte_en_t be = -1, uvm_predict_e kind = UVM_PREDICT_DIRECT, uvm_door_e path = UVM_FRONTDOOR, uvm_reg_map map = null, string fname = "", int lineno = 0); uvm_reg_item rw = new; rw.value[0] = value; rw.path = path; rw.map = map; rw.fname = fname; rw.lineno = lineno; do_predict(rw, kind, be); predict = (rw.status == UVM_NOT_OK) ? 0 : 1; endfunction: predict function void uvm_reg_field::do_predict(uvm_reg_item rw, uvm_predict_e kind = UVM_PREDICT_DIRECT, uvm_reg_byte_en_t be = -1); uvm_reg_data_t field_val = rw.value[0] & ((1 << m_size)-1); if (rw.status != UVM_NOT_OK) rw.status = UVM_IS_OK; if (!be[0]) return; m_fname = rw.fname; m_lineno = rw.lineno; case (kind) UVM_PREDICT_WRITE: begin uvm_reg_field_cb_iter cbs = new(this); if (rw.path == UVM_FRONTDOOR || rw.path == UVM_PREDICT) field_val = XpredictX(m_mirrored, field_val, rw.map); m_written = 1; for (uvm_reg_cbs cb = cbs.first(); cb != null; cb = cbs.next()) cb.post_predict(this, m_mirrored, field_val, UVM_PREDICT_WRITE, rw.path, rw.map); field_val &= ('b1 << m_size)-1; end UVM_PREDICT_READ: begin uvm_reg_field_cb_iter cbs = new(this); if (rw.path == UVM_FRONTDOOR || rw.path == UVM_PREDICT) begin string acc = get_access(rw.map); if (acc == "RC" || acc == "WRC" || acc == "WSRC" || acc == "W1SRC" || acc == "W0SRC") field_val = 0; else if (acc == "RS" || acc == "WRS" || acc == "WCRS" || acc == "W1CRS" || acc == "W0CRS") field_val = ('b1 << m_size)-1; else if (acc == "WO" || acc == "WOC" || acc == "WOS" || acc == "WO1" || acc == "NOACCESS") return; end for (uvm_reg_cbs cb = cbs.first(); cb != null; cb = cbs.next()) cb.post_predict(this, m_mirrored, field_val, UVM_PREDICT_READ, rw.path, rw.map); field_val &= ('b1 << m_size)-1; end UVM_PREDICT_DIRECT: begin if (m_parent.is_busy()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Trying to predict value of field '", get_name(),"' while register '",m_parent.get_full_name(), "' is being accessed"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_field.svh", 797, "", 1); end rw.status = UVM_NOT_OK; end end endcase m_mirrored = field_val; m_desired = field_val; this.value = field_val; endfunction: do_predict function uvm_reg_data_t uvm_reg_field::XupdateX(); XupdateX = 0; case (m_access) "RO": XupdateX = m_desired; "RW": XupdateX = m_desired; "RC": XupdateX = m_desired; "RS": XupdateX = m_desired; "WRC": XupdateX = m_desired; "WRS": XupdateX = m_desired; "WC": XupdateX = m_desired; "WS": XupdateX = m_desired; "WSRC": XupdateX = m_desired; "WCRS": XupdateX = m_desired; "W1C": XupdateX = ~m_desired; "W1S": XupdateX = m_desired; "W1T": XupdateX = m_desired ^ m_mirrored; "W0C": XupdateX = m_desired; "W0S": XupdateX = ~m_desired; "W0T": XupdateX = ~(m_desired ^ m_mirrored); "W1SRC": XupdateX = m_desired; "W1CRS": XupdateX = ~m_desired; "W0SRC": XupdateX = ~m_desired; "W0CRS": XupdateX = m_desired; "WO": XupdateX = m_desired; "WOC": XupdateX = m_desired; "WOS": XupdateX = m_desired; "W1": XupdateX = m_desired; "WO1": XupdateX = m_desired; default: XupdateX = m_desired; endcase XupdateX &= (1 << m_size) - 1; endfunction: XupdateX function void uvm_reg_field::set(uvm_reg_data_t value, string fname = "", int lineno = 0); uvm_reg_data_t mask = ('b1 << m_size)-1; m_fname = fname; m_lineno = lineno; if (value >> m_size) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", $sformatf("Specified value (0x%h) greater than field \"%s\" size (%0d bits)", value, get_name(), m_size), UVM_NONE, "t/uvm/src/reg/uvm_reg_field.svh", 863, "", 1); end value &= mask; end if (m_parent.is_busy()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"UVM/FLD/SET/BSY")) uvm_report_warning ("UVM/FLD/SET/BSY", $sformatf("Setting the value of field \"%s\" while containing register \"%s\" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.", get_name(), m_parent.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_reg_field.svh", 870, "", 1); end end case (m_access) "RO": m_desired = m_desired; "RW": m_desired = value; "RC": m_desired = m_desired; "RS": m_desired = m_desired; "WC": m_desired = '0; "WS": m_desired = mask; "WRC": m_desired = value; "WRS": m_desired = value; "WSRC": m_desired = mask; "WCRS": m_desired = '0; "W1C": m_desired = m_desired & (~value); "W1S": m_desired = m_desired | value; "W1T": m_desired = m_desired ^ value; "W0C": m_desired = m_desired & value; "W0S": m_desired = m_desired | (~value & mask); "W0T": m_desired = m_desired ^ (~value & mask); "W1SRC": m_desired = m_desired | value; "W1CRS": m_desired = m_desired & (~value); "W0SRC": m_desired = m_desired | (~value & mask); "W0CRS": m_desired = m_desired & value; "WO": m_desired = value; "WOC": m_desired = '0; "WOS": m_desired = mask; "W1": m_desired = (m_written) ? m_desired : value; "WO1": m_desired = (m_written) ? m_desired : value; default: m_desired = value; endcase this.value = m_desired; endfunction: set function uvm_reg_data_t uvm_reg_field::get(string fname = "", int lineno = 0); m_fname = fname; m_lineno = lineno; get = m_desired; endfunction: get function uvm_reg_data_t uvm_reg_field::get_mirrored_value(string fname = "", int lineno = 0); m_fname = fname; m_lineno = lineno; get_mirrored_value = m_mirrored; endfunction: get_mirrored_value function void uvm_reg_field::reset(string kind = "HARD"); if (!m_reset.exists(kind)) return; m_mirrored = m_reset[kind]; m_desired = m_mirrored; value = m_mirrored; if (kind == "HARD") m_written = 0; endfunction: reset function bit uvm_reg_field::has_reset(string kind = "HARD", bit delete = 0); if (!m_reset.exists(kind)) return 0; if (delete) m_reset.delete(kind); return 1; endfunction: has_reset function uvm_reg_data_t uvm_reg_field::get_reset(string kind = "HARD"); if (!m_reset.exists(kind)) return m_desired; return m_reset[kind]; endfunction: get_reset function void uvm_reg_field::set_reset(uvm_reg_data_t value, string kind = "HARD"); m_reset[kind] = value & ((1<> m_size) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"uvm_reg_field::write(): Value greater than field '", get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_field.svh", 1092, "", 1); end rw.value[0] &= ((1<> m_lsb) & ((1<0) begin prev_lsb = fields[fld_idx-1].get_lsb_pos(); prev_sz = fields[fld_idx-1].get_n_bits(); end if (fld_idx < fields.size()-1) begin next_lsb = fields[fld_idx+1].get_lsb_pos(); next_sz = fields[fld_idx+1].get_n_bits(); end if (fld_idx == 0 && ((next_lsb % bus_sz) == 0 || (next_lsb - this_sz) > (next_lsb % bus_sz))) return 1; else if (fld_idx == (fields.size()-1) && ((this_lsb % bus_sz) == 0 || (this_lsb - (prev_lsb + prev_sz)) >= (this_lsb % bus_sz))) return 1; else begin if ((this_lsb % bus_sz) == 0) begin if ((next_lsb % bus_sz) == 0 || (next_lsb - (this_lsb + this_sz)) >= (next_lsb % bus_sz)) return 1; end else begin if ( (next_lsb - (this_lsb + this_sz)) >= (next_lsb % bus_sz) && ((this_lsb - (prev_lsb + prev_sz)) >= (this_lsb % bus_sz)) ) return 1; end end end end begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Target bus does not support byte enabling, and the field '", get_full_name(),"' is not the only field within the entire bus width. ", "Individual field access will not be available. ", "Accessing complete register instead."}, UVM_NONE, "t/uvm/src/reg/uvm_reg_field.svh", 1422, "", 1); end return 0; endfunction task uvm_reg_field::poke(output uvm_status_e status, input uvm_reg_data_t value, input string kind = "", input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_reg_data_t tmp; m_fname = fname; m_lineno = lineno; if (value >> m_size) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"uvm_reg_field::poke(): Value exceeds size of field '", get_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_field.svh", 1446, "", 1); end value &= value & ((1<> m_lsb) & ((1< 64) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Virtual field \"%s\" cannot have more than %0d bits", this.get_full_name(), 64), UVM_NONE, "t/uvm/src/reg/uvm_vreg_field.svh", 327, "", 1); end size = 64; end this.size = size; this.lsb = lsb_pos; this.parent.add_field(this); endfunction: configure function string uvm_vreg_field::get_full_name(); get_full_name = {this.parent.get_full_name(), ".", this.get_name()}; endfunction: get_full_name function uvm_vreg uvm_vreg_field::get_register(); get_register = this.parent; endfunction: get_register function uvm_vreg uvm_vreg_field::get_parent(); get_parent = this.parent; endfunction: get_parent function int unsigned uvm_vreg_field::get_lsb_pos_in_register(); get_lsb_pos_in_register = this.lsb; endfunction: get_lsb_pos_in_register function int unsigned uvm_vreg_field::get_n_bits(); get_n_bits = this.size; endfunction: get_n_bits function string uvm_vreg_field::get_access(uvm_reg_map map = null); if (this.parent.get_memory() == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot call uvm_vreg_field::get_rights() on unimplemented virtual field \"%s\"", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg_field.svh", 368, "", 1); end return "RW"; end return this.parent.get_access(map); endfunction: get_access task uvm_vreg_field::write(input longint unsigned idx, output uvm_status_e status, input uvm_reg_data_t value, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_reg_data_t tmp; uvm_reg_data_t segval; uvm_reg_addr_t segoff; uvm_status_e st; int flsb, fmsb, rmwbits; int segsiz, segn; uvm_mem mem; uvm_door_e rm_path; uvm_vreg_field_cb_iter cbs = new(this); this.fname = fname; this.lineno = lineno; write_in_progress = 1'b1; mem = this.parent.get_memory(); if (mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot call uvm_vreg_field::write() on unimplemented virtual register \"%s\"", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg_field.svh", 404, "", 1); end status = UVM_NOT_OK; return; end if (path == UVM_DEFAULT_DOOR) begin uvm_reg_block blk = this.parent.get_block(); path = blk.get_default_door(); end status = UVM_IS_OK; this.parent.XatomicX(1); if (value >> this.size) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", $sformatf("Writing value 'h%h that is greater than field \"%s\" size (%0d bits)", value, this.get_full_name(), this.get_n_bits()), UVM_NONE, "t/uvm/src/reg/uvm_vreg_field.svh", 419, "", 1); end value &= value & ((1< 0) begin uvm_reg_addr_t segn; mem.read(st, segoff, tmp, rm_path, map, parent, , extension, fname, lineno); if (st != UVM_IS_OK && st != UVM_HAS_X) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Unable to read LSB bits in %s[%0d] to for RMW cycle on virtual field %s.", mem.get_full_name(), segoff, this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg_field.svh", 453, "", 1); end status = UVM_NOT_OK; this.parent.XatomicX(0); return; end value = (value << rmwbits) | (tmp & ((1< 0) begin if (segn > 0) begin mem.read(st, segoff + segn - 1, tmp, rm_path, map, parent,, extension, fname, lineno); if (st != UVM_IS_OK && st != UVM_HAS_X) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Unable to read MSB bits in %s[%0d] to for RMW cycle on virtual field %s.", mem.get_full_name(), segoff+segn-1, this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg_field.svh", 472, "", 1); end status = UVM_NOT_OK; this.parent.XatomicX(0); return; end end value |= (tmp & ~((1<> segsiz; end this.post_write(idx, value, path, map, status); for (uvm_vreg_field_cbs cb = cbs.first(); cb != null; cb = cbs.next()) begin cb.fname = this.fname; cb.lineno = this.lineno; cb.post_write(this, idx, value, path, map, status); end this.parent.XatomicX(0); begin if (uvm_report_enabled(UVM_MEDIUM,UVM_INFO,"RegModel")) uvm_report_info ("RegModel", $sformatf("Wrote virtual field \"%s\"[%0d] via %s with: 'h%h", this.get_full_name(), idx, (path == UVM_FRONTDOOR) ? "frontdoor" : "backdoor", value), UVM_MEDIUM, "t/uvm/src/reg/uvm_vreg_field.svh", 505, "", 1); end write_in_progress = 1'b0; this.fname = ""; this.lineno = 0; endtask: write task uvm_vreg_field::read(input longint unsigned idx, output uvm_status_e status, output uvm_reg_data_t value, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_reg_data_t tmp; uvm_reg_data_t segval; uvm_reg_addr_t segoff; uvm_status_e st; int flsb, lsb; int segsiz, segn; uvm_mem mem; uvm_vreg_field_cb_iter cbs = new(this); this.fname = fname; this.lineno = lineno; read_in_progress = 1'b1; mem = this.parent.get_memory(); if (mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot call uvm_vreg_field::read() on unimplemented virtual register \"%s\"", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg_field.svh", 540, "", 1); end status = UVM_NOT_OK; return; end if (path == UVM_DEFAULT_DOOR) begin uvm_reg_block blk = this.parent.get_block(); path = blk.get_default_door(); end status = UVM_IS_OK; this.parent.XatomicX(1); value = 0; this.pre_read(idx, path, map); for (uvm_vreg_field_cbs cb = cbs.first(); cb != null; cb = cbs.next()) begin cb.fname = this.fname; cb.lineno = this.lineno; cb.pre_read(this, idx, path, map); end segsiz = mem.get_n_bytes() * 8; flsb = this.get_lsb_pos_in_register(); segoff = this.parent.get_offset_in_memory(idx) + (flsb / segsiz); lsb = flsb % segsiz; segn = (lsb + this.get_n_bits() - 1) / segsiz + 1; segoff += segn - 1; repeat (segn) begin value = value << segsiz; mem.read(st, segoff, tmp, path, map, parent, , extension, fname, lineno); if (st != UVM_IS_OK && st != UVM_HAS_X) status = UVM_NOT_OK; segoff--; value |= tmp; end value = value >> lsb; value &= (1<> this.size) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", $sformatf("Writing value 'h%h that is greater than field \"%s\" size (%0d bits)", value, this.get_full_name(), this.get_n_bits()), UVM_NONE, "t/uvm/src/reg/uvm_vreg_field.svh", 644, "", 1); end value &= value & ((1< 0) begin uvm_reg_addr_t segn; mem.peek(st, segoff, tmp, "", parent, extension, fname, lineno); if (st != UVM_IS_OK && st != UVM_HAS_X) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Unable to read LSB bits in %s[%0d] to for RMW cycle on virtual field %s.", mem.get_full_name(), segoff, this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg_field.svh", 666, "", 1); end status = UVM_NOT_OK; this.parent.XatomicX(0); return; end value = (value << rmwbits) | (tmp & ((1< 0) begin if (segn > 0) begin mem.peek(st, segoff + segn - 1, tmp, "", parent, extension, fname, lineno); if (st != UVM_IS_OK && st != UVM_HAS_X) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Unable to read MSB bits in %s[%0d] to for RMW cycle on virtual field %s.", mem.get_full_name(), segoff+segn-1, this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg_field.svh", 685, "", 1); end status = UVM_NOT_OK; this.parent.XatomicX(0); return; end end value |= (tmp & ~((1<> segsiz; end this.parent.XatomicX(0); begin if (uvm_report_enabled(UVM_MEDIUM,UVM_INFO,"RegModel")) uvm_report_info ("RegModel", $sformatf("Wrote virtual field \"%s\"[%0d] with: 'h%h", this.get_full_name(), idx, value), UVM_MEDIUM, "t/uvm/src/reg/uvm_vreg_field.svh", 707, "", 1); end this.fname = ""; this.lineno = 0; endtask: poke task uvm_vreg_field::peek(input longint unsigned idx, output uvm_status_e status, output uvm_reg_data_t value, input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_reg_data_t tmp; uvm_reg_data_t segval; uvm_reg_addr_t segoff; uvm_status_e st; int flsb, lsb; int segsiz, segn; uvm_mem mem; this.fname = fname; this.lineno = lineno; mem = this.parent.get_memory(); if (mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot call uvm_vreg_field::peek() on unimplemented virtual register \"%s\"", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg_field.svh", 735, "", 1); end status = UVM_NOT_OK; return; end status = UVM_IS_OK; this.parent.XatomicX(1); value = 0; segsiz = mem.get_n_bytes() * 8; flsb = this.get_lsb_pos_in_register(); segoff = this.parent.get_offset_in_memory(idx) + (flsb / segsiz); lsb = flsb % segsiz; segn = (lsb + this.get_n_bits() - 1) / segsiz + 1; segoff += segn - 1; repeat (segn) begin value = value << segsiz; mem.peek(st, segoff, tmp, "", parent, extension, fname, lineno); if (st != UVM_IS_OK && st != UVM_HAS_X) status = UVM_NOT_OK; segoff--; value |= tmp; end value = value >> lsb; value &= (1< m_max_size) m_max_size = n_bits; endfunction: new function void uvm_reg::configure (uvm_reg_block blk_parent, uvm_reg_file regfile_parent=null, string hdl_path = ""); if (blk_parent == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/REG/CFG/NOBLK")) uvm_report_error ("UVM/REG/CFG/NOBLK", {"uvm_reg::configure() called without a parent block for instance \"", get_name(), "\" of register type \"", get_type_name(), "\"."}, UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 623, "", 1); end return; end m_parent = blk_parent; m_parent.add_reg(this); m_regfile_parent = regfile_parent; if (hdl_path != "") add_hdl_path_slice(hdl_path, -1, -1); endfunction: configure function void uvm_reg::add_field(uvm_reg_field field); int offset; int idx; if (m_locked) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", "Cannot add field to locked register model", UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 642, "", 1); end return; end if (field == null) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"RegModel")) uvm_report_fatal ("RegModel", "Attempting to register NULL field", UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 646, "", 1); end offset = field.get_lsb_pos(); idx = -1; foreach (m_fields[i]) begin if (offset < m_fields[i].get_lsb_pos()) begin int j = i; m_fields.insert(j, field); idx = i; break; end end if (idx < 0) begin m_fields.push_back(field); idx = m_fields.size()-1; end m_n_used_bits += field.get_n_bits(); if (m_n_used_bits > m_n_bits) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Fields use more bits (%0d) than available in register \"%s\" (%0d)", m_n_used_bits, get_name(), m_n_bits), UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 671, "", 1); end end if (idx > 0) begin if (m_fields[idx-1].get_lsb_pos() + m_fields[idx-1].get_n_bits() > offset) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Field %s overlaps field %s in register \"%s\"", m_fields[idx-1].get_name(), field.get_name(), get_name()), UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 680, "", 1); end end end if (idx < m_fields.size()-1) begin if (offset + field.get_n_bits() > m_fields[idx+1].get_lsb_pos()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Field %s overlaps field %s in register \"%s\"", field.get_name(), m_fields[idx+1].get_name(), get_name()), UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 689, "", 1); end end end endfunction: add_field function void uvm_reg::Xlock_modelX(); if (m_locked) return; m_locked = 1; endfunction function void uvm_reg::set_frontdoor(uvm_reg_frontdoor ftdr, uvm_reg_map map = null, string fname = "", int lineno = 0); uvm_reg_map_info map_info; ftdr.fname = m_fname; ftdr.lineno = m_lineno; map = get_local_map(map); if (map == null) return; map_info = map.get_reg_map_info(this); if (map_info == null) map.add_reg(this, -1, "RW", 1, ftdr); else begin map_info.frontdoor = ftdr; end endfunction: set_frontdoor function uvm_reg_frontdoor uvm_reg::get_frontdoor(uvm_reg_map map = null); uvm_reg_map_info map_info; map = get_local_map(map); if (map == null) return null; map_info = map.get_reg_map_info(this); return map_info.frontdoor; endfunction: get_frontdoor function void uvm_reg::set_backdoor(uvm_reg_backdoor bkdr, string fname = "", int lineno = 0); bkdr.fname = fname; bkdr.lineno = lineno; if (m_backdoor != null && m_backdoor.has_update_threads()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", "Previous register backdoor still has update threads running. Backdoors with active mirroring should only be set before simulation starts.", UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 750, "", 1); end end m_backdoor = bkdr; endfunction: set_backdoor function uvm_reg_backdoor uvm_reg::get_backdoor(bit inherited = 1); if (m_backdoor == null && inherited) begin uvm_reg_block blk = get_parent(); uvm_reg_backdoor bkdr; while (blk != null) begin bkdr = blk.get_backdoor(); if (bkdr != null) begin m_backdoor = bkdr; break; end blk = blk.get_parent(); end end return m_backdoor; endfunction: get_backdoor function void uvm_reg::clear_hdl_path(string kind = "RTL"); if (kind == "ALL") begin m_hdl_paths_pool = new("hdl_paths"); return; end if (kind == "") begin if (m_regfile_parent != null) kind = m_regfile_parent.get_default_hdl_path(); else kind = m_parent.get_default_hdl_path(); end if (!m_hdl_paths_pool.exists(kind)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Unknown HDL Abstraction '",kind,"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 793, "", 1); end return; end m_hdl_paths_pool.delete(kind); endfunction function void uvm_reg::add_hdl_path(uvm_hdl_path_slice slices[], string kind = "RTL"); uvm_queue #(uvm_hdl_path_concat) paths = m_hdl_paths_pool.get(kind); uvm_hdl_path_concat concat = new(); concat.set(slices); paths.push_back(concat); endfunction function void uvm_reg::add_hdl_path_slice(string name, int offset, int size, bit first = 0, string kind = "RTL"); uvm_queue #(uvm_hdl_path_concat) paths = m_hdl_paths_pool.get(kind); uvm_hdl_path_concat concat; if (first || paths.size() == 0) begin concat = new(); paths.push_back(concat); end else concat = paths.get(paths.size()-1); concat.add_path(name, offset, size); endfunction function bit uvm_reg::has_hdl_path(string kind = ""); if (kind == "") begin if (m_regfile_parent != null) kind = m_regfile_parent.get_default_hdl_path(); else kind = m_parent.get_default_hdl_path(); end return m_hdl_paths_pool.exists(kind); endfunction function void uvm_reg::get_hdl_path_kinds (ref string kinds[$]); string kind; kinds.delete(); if (!m_hdl_paths_pool.first(kind)) return; do kinds.push_back(kind); while (m_hdl_paths_pool.next(kind)); endfunction function void uvm_reg::get_hdl_path(ref uvm_hdl_path_concat paths[$], input string kind = ""); uvm_queue #(uvm_hdl_path_concat) hdl_paths; if (kind == "") begin if (m_regfile_parent != null) kind = m_regfile_parent.get_default_hdl_path(); else kind = m_parent.get_default_hdl_path(); end if (!has_hdl_path(kind)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Register does not have hdl path defined for abstraction '",kind,"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 877, "", 1); end return; end hdl_paths = m_hdl_paths_pool.get(kind); for (int i=0; i 1 && map == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"set_offset requires a non-null map when register '", get_full_name(),"' belongs to more than one map."}, UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 949, "", 1); end return; end map = get_local_map(map); if (map == null) return; map.m_set_reg_offset(this, offset, unmapped); endfunction function void uvm_reg::set_parent(uvm_reg_block blk_parent, uvm_reg_file regfile_parent); if (m_parent != null) begin end m_parent = blk_parent; m_regfile_parent = regfile_parent; endfunction function uvm_reg_block uvm_reg::get_parent(); return get_block(); endfunction function uvm_reg_file uvm_reg::get_regfile(); return m_regfile_parent; endfunction function string uvm_reg::get_full_name(); if (m_regfile_parent != null) return {m_regfile_parent.get_full_name(), ".", get_name()}; if (m_parent != null) return {m_parent.get_full_name(), ".", get_name()}; return get_name(); endfunction: get_full_name function void uvm_reg::add_map(uvm_reg_map map); m_maps[map] = 1; endfunction function void uvm_reg::get_maps(ref uvm_reg_map maps[$]); foreach (m_maps[map]) maps.push_back(map); endfunction function int uvm_reg::get_n_maps(); return m_maps.num(); endfunction function bit uvm_reg::is_in_map(uvm_reg_map map); if (m_maps.exists(map)) return 1; foreach (m_maps[l]) begin uvm_reg_map local_map = l; uvm_reg_map parent_map = local_map.get_parent_map(); while (parent_map != null) begin if (parent_map == map) return 1; parent_map = parent_map.get_parent_map(); end end return 0; endfunction function uvm_reg_map uvm_reg::get_local_map(uvm_reg_map map); if (map == null) return get_default_map(); if (m_maps.exists(map)) return map; foreach (m_maps[l]) begin uvm_reg_map local_map=l; uvm_reg_map parent_map = local_map.get_parent_map(); while (parent_map != null) begin if (parent_map == map) return local_map; parent_map = parent_map.get_parent_map(); end end begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Register '",get_full_name(),"' is not contained within map '",map.get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 1062, "", 1); end return null; endfunction function uvm_reg_map uvm_reg::get_default_map(); if (m_maps.num() == 0) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Register '",get_full_name(),"' is not registered with any map"}, UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 1075, "", 1); end return null; end if (m_maps.num() == 1) begin uvm_reg_map map; void'(m_maps.first(map)); return map; end foreach (m_maps[l]) begin uvm_reg_map map = l; uvm_reg_block blk = map.get_parent(); uvm_reg_map default_map = blk.get_default_map(); if (default_map != null) begin uvm_reg_map local_map = get_local_map(default_map); if (local_map != null) return local_map; end end begin uvm_reg_map map; void'(m_maps.first(map)); return map; end endfunction function string uvm_reg::get_rights(uvm_reg_map map = null); uvm_reg_map_info info; map = get_local_map(map); if (map == null) return "RW"; info = map.get_reg_map_info(this); return info.rights; endfunction function uvm_reg_block uvm_reg::get_block(); get_block = m_parent; endfunction function uvm_reg_addr_t uvm_reg::get_offset(uvm_reg_map map = null); uvm_reg_map_info map_info; uvm_reg_map orig_map = map; map = get_local_map(map); if (map == null) return -1; map_info = map.get_reg_map_info(this); if (map_info.unmapped) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Register '",get_name(), "' is unmapped in map '", ((orig_map == null) ? map.get_full_name() : orig_map.get_full_name()),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 1151, "", 1); end return -1; end return map_info.offset; endfunction function int uvm_reg::get_addresses(uvm_reg_map map=null, ref uvm_reg_addr_t addr[]); uvm_reg_map_info map_info; uvm_reg_map orig_map = map; map = get_local_map(map); if (map == null) return -1; map_info = map.get_reg_map_info(this); if (map_info.unmapped) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Register '",get_name(), "' is unmapped in map '", ((orig_map == null) ? map.get_full_name() : orig_map.get_full_name()),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 1177, "", 1); end return -1; end addr = map_info.addr; return map.get_n_bytes(); endfunction function uvm_reg_addr_t uvm_reg::get_address(uvm_reg_map map = null); uvm_reg_addr_t addr[]; void'(get_addresses(map,addr)); return addr[0]; endfunction function int unsigned uvm_reg::get_n_bits(); return m_n_bits; endfunction function int unsigned uvm_reg::get_n_bytes(); return ((m_n_bits-1) / 8) + 1; endfunction function int unsigned uvm_reg::get_max_size(); return m_max_size; endfunction: get_max_size function void uvm_reg::get_fields(ref uvm_reg_field fields[$]); foreach(m_fields[i]) fields.push_back(m_fields[i]); endfunction function uvm_reg_field uvm_reg::get_field_by_name(string name); foreach (m_fields[i]) if (m_fields[i].get_name() == name) return m_fields[i]; begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Unable to locate field '",name, "' in register '",get_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 1232, "", 1); end return null; endfunction function string uvm_reg::Xget_fields_accessX(uvm_reg_map map); bit is_R; bit is_W; foreach(m_fields[i]) begin case (m_fields[i].get_access(map)) "RO", "RC", "RS": is_R = 1; "WO", "WOC", "WOS", "WO1": is_W = 1; default: return "RW"; endcase if (is_R && is_W) return "RW"; end case ({is_R, is_W}) 2'b01: return "WO"; 2'b10: return "RO"; endcase return "RW"; endfunction function void uvm_reg::include_coverage(string scope, uvm_reg_cvr_t models, uvm_object accessor = null); uvm_reg_cvr_rsrc_db::set({"uvm_reg::", scope}, "include_coverage", models, accessor); endfunction function uvm_reg_cvr_t uvm_reg::build_coverage(uvm_reg_cvr_t models); build_coverage = UVM_NO_COVERAGE; void'(uvm_reg_cvr_rsrc_db::read_by_name({"uvm_reg::", get_full_name()}, "include_coverage", build_coverage, this)); return build_coverage & models; endfunction: build_coverage function void uvm_reg::add_coverage(uvm_reg_cvr_t models); m_has_cover |= models; endfunction: add_coverage function bit uvm_reg::has_coverage(uvm_reg_cvr_t models); return ((m_has_cover & models) == models); endfunction: has_coverage function uvm_reg_cvr_t uvm_reg::set_coverage(uvm_reg_cvr_t is_on); if (is_on == uvm_reg_cvr_t'(UVM_NO_COVERAGE)) begin m_cover_on = is_on; return m_cover_on; end m_cover_on = m_has_cover & is_on; return m_cover_on; endfunction: set_coverage function bit uvm_reg::get_coverage(uvm_reg_cvr_t is_on); if (has_coverage(is_on) == 0) return 0; return ((m_cover_on & is_on) == is_on); endfunction: get_coverage function void uvm_reg::set(uvm_reg_data_t value, string fname = "", int lineno = 0); m_fname = fname; m_lineno = lineno; foreach (m_fields[i]) m_fields[i].set((value >> m_fields[i].get_lsb_pos()) & ((1 << m_fields[i].get_n_bits()) - 1)); endfunction: set function bit uvm_reg::predict (uvm_reg_data_t value, uvm_reg_byte_en_t be = -1, uvm_predict_e kind = UVM_PREDICT_DIRECT, uvm_door_e path = UVM_FRONTDOOR, uvm_reg_map map = null, string fname = "", int lineno = 0); uvm_reg_item rw = new; rw.value[0] = value; rw.path = path; rw.map = map; rw.fname = fname; rw.lineno = lineno; do_predict(rw, kind, be); predict = (rw.status == UVM_NOT_OK) ? 0 : 1; endfunction: predict function void uvm_reg::do_predict(uvm_reg_item rw, uvm_predict_e kind = UVM_PREDICT_DIRECT, uvm_reg_byte_en_t be = -1); uvm_reg_data_t reg_value = rw.value[0]; m_fname = rw.fname; m_lineno = rw.lineno; if (rw.status ==UVM_IS_OK ) rw.status = UVM_IS_OK; if (m_is_busy && kind == UVM_PREDICT_DIRECT) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Trying to predict value of register '", get_full_name(),"' while it is being accessed"}, UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 1395, "", 1); end rw.status = UVM_NOT_OK; return; end foreach (m_fields[i]) begin rw.value[0] = (reg_value >> m_fields[i].get_lsb_pos()) & ((1 << m_fields[i].get_n_bits())-1); m_fields[i].do_predict(rw, kind, be>>(m_fields[i].get_lsb_pos()/8)); end rw.value[0] = reg_value; endfunction: do_predict function uvm_reg_data_t uvm_reg::get(string fname = "", int lineno = 0); m_fname = fname; m_lineno = lineno; get = 0; foreach (m_fields[i]) get |= m_fields[i].get() << m_fields[i].get_lsb_pos(); endfunction: get function uvm_reg_data_t uvm_reg::get_mirrored_value(string fname = "", int lineno = 0); m_fname = fname; m_lineno = lineno; get_mirrored_value = 0; foreach (m_fields[i]) get_mirrored_value |= m_fields[i].get_mirrored_value() << m_fields[i].get_lsb_pos(); endfunction: get_mirrored_value function void uvm_reg::reset(string kind = "HARD"); foreach (m_fields[i]) m_fields[i].reset(kind); void'(m_atomic.try_get(1)); m_atomic.put(1); m_process = null; Xset_busyX(0); endfunction: reset function uvm_reg_data_t uvm_reg::get_reset(string kind = "HARD"); get_reset = 0; foreach (m_fields[i]) get_reset |= m_fields[i].get_reset(kind) << m_fields[i].get_lsb_pos(); endfunction: get_reset function bit uvm_reg::has_reset(string kind = "HARD", bit delete = 0); has_reset = 0; foreach (m_fields[i]) begin has_reset |= m_fields[i].has_reset(kind, delete); if (!delete && has_reset) return 1; end endfunction: has_reset function void uvm_reg::set_reset(uvm_reg_data_t value, string kind = "HARD"); foreach (m_fields[i]) begin m_fields[i].set_reset(value >> m_fields[i].get_lsb_pos(), kind); end endfunction: set_reset function bit uvm_reg::needs_update(); needs_update = 0; foreach (m_fields[i]) begin if (m_fields[i].needs_update()) begin return 1; end end endfunction: needs_update task uvm_reg::update(output uvm_status_e status, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_reg_data_t upd; status = UVM_IS_OK; if (!needs_update()) return; upd = 0; foreach (m_fields[i]) upd |= m_fields[i].XupdateX() << m_fields[i].get_lsb_pos(); write(status, upd, path, map, parent, prior, extension, fname, lineno); endtask: update task uvm_reg::write(output uvm_status_e status, input uvm_reg_data_t value, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_reg_item rw; XatomicX(1); set(value); rw = uvm_reg_item::type_id::create("write_item",,get_full_name()); rw.element = this; rw.element_kind = UVM_REG; rw.kind = UVM_WRITE; rw.value[0] = value; rw.path = path; rw.map = map; rw.parent = parent; rw.prior = prior; rw.extension = extension; rw.fname = fname; rw.lineno = lineno; do_write(rw); status = rw.status; XatomicX(0); endtask task uvm_reg::do_write (uvm_reg_item rw); uvm_reg_cb_iter cbs = new(this); uvm_reg_map_info map_info; uvm_reg_data_t value; m_fname = rw.fname; m_lineno = rw.lineno; if (!Xcheck_accessX(rw,map_info)) return; XatomicX(1); m_write_in_progress = 1'b1; rw.value[0] &= ((1 << m_n_bits)-1); value = rw.value[0]; rw.status = UVM_IS_OK; begin : pre_write_callbacks uvm_reg_data_t msk; int lsb; foreach (m_fields[i]) begin uvm_reg_field_cb_iter cbs = new(m_fields[i]); uvm_reg_field f = m_fields[i]; lsb = f.get_lsb_pos(); msk = ((1<> lsb; f.pre_write(rw); for (uvm_reg_cbs cb=cbs.first(); cb!=null; cb=cbs.next()) begin rw.element = f; rw.element_kind = UVM_FIELD; cb.pre_write(rw); end value = (value & ~msk) | (rw.value[0] << lsb); end end rw.element = this; rw.element_kind = UVM_REG; rw.value[0] = value; pre_write(rw); for (uvm_reg_cbs cb=cbs.first(); cb!=null; cb=cbs.next()) cb.pre_write(rw); if (rw.status != UVM_IS_OK) begin m_write_in_progress = 1'b0; XatomicX(0); return; end case (rw.path) UVM_BACKDOOR: begin uvm_reg_data_t final_val; uvm_reg_backdoor bkdr = get_backdoor(); if (rw.map != null) rw.local_map = rw.map; else rw.local_map = get_default_map(); value = rw.value[0]; rw.kind = UVM_READ; if (bkdr != null) bkdr.read(rw); else backdoor_read(rw); if (rw.status == UVM_NOT_OK) begin m_write_in_progress = 1'b0; return; end begin foreach (m_fields[i]) begin uvm_reg_data_t field_val; int lsb = m_fields[i].get_lsb_pos(); int sz = m_fields[i].get_n_bits(); field_val = m_fields[i].XpredictX((rw.value[0] >> lsb) & ((1<> lsb) & ((1<> f.get_lsb_pos()) & ((1<> f.get_lsb_pos()) & ((1<> hdl_concat.slices[j].offset; slice &= (1 << hdl_concat.slices[j].size)-1; ok &= uvm_hdl_deposit(hdl_concat.slices[j].path, slice); end end end rw.status = (ok ? UVM_IS_OK : UVM_NOT_OK); endtask task uvm_reg::backdoor_read (uvm_reg_item rw); rw.status = backdoor_read_func(rw); endtask function uvm_status_e uvm_reg::backdoor_read_func(uvm_reg_item rw); uvm_hdl_path_concat paths[$]; uvm_reg_data_t val; bit ok=1; get_full_hdl_path(paths,rw.bd_kind); foreach (paths[i]) begin uvm_hdl_path_concat hdl_concat = paths[i]; val = 0; foreach (hdl_concat.slices[j]) begin begin if (uvm_report_enabled(UVM_DEBUG,UVM_INFO,"RegMem")) uvm_report_info ("RegMem", $sformatf("backdoor_read from %s ", hdl_concat.slices[j].path), UVM_DEBUG, "t/uvm/src/reg/uvm_reg.svh", 2184, "", 1); end if (hdl_concat.slices[j].offset < 0) begin ok &= uvm_hdl_read(hdl_concat.slices[j].path,val); continue; end begin uvm_reg_data_t slice; int k = hdl_concat.slices[j].offset; ok &= uvm_hdl_read(hdl_concat.slices[j].path, slice); repeat (hdl_concat.slices[j].size) begin val[k++] = slice[0]; slice >>= 1; end end end val &= (1 << m_n_bits)-1; if (i == 0) rw.value[0] = val; if (val != rw.value[0]) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Backdoor read of register %s with multiple HDL copies: values are not the same: %0h at path '%s', and %0h at path '%s'. Returning first value.", get_full_name(), rw.value[0], uvm_hdl_concat2string(paths[0]), val, uvm_hdl_concat2string(paths[i])), UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 2212, "", 1); end return UVM_NOT_OK; end begin if (uvm_report_enabled(UVM_DEBUG,UVM_INFO,"RegMem")) uvm_report_info ("RegMem", $sformatf("returned backdoor value 0x%0x",rw.value[0]), UVM_DEBUG, "t/uvm/src/reg/uvm_reg.svh", 2216, "", 1); end end rw.status = (ok) ? UVM_IS_OK : UVM_NOT_OK; return rw.status; endfunction task uvm_reg::poke(output uvm_status_e status, input uvm_reg_data_t value, input string kind = "", input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_reg_backdoor bkdr = get_backdoor(); uvm_reg_item rw; m_fname = fname; m_lineno = lineno; if (bkdr == null && !has_hdl_path(kind)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"No backdoor access available to poke register '",get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 2244, "", 1); end status = UVM_NOT_OK; return; end if (!m_is_locked_by_field) XatomicX(1); rw = uvm_reg_item::type_id::create("reg_poke_item",,get_full_name()); rw.element = this; rw.path = UVM_BACKDOOR; rw.element_kind = UVM_REG; rw.kind = UVM_WRITE; rw.bd_kind = kind; rw.value[0] = value & ((1 << m_n_bits)-1); rw.parent = parent; rw.extension = extension; rw.fname = fname; rw.lineno = lineno; if (bkdr != null) bkdr.write(rw); else backdoor_write(rw); status = rw.status; begin if (uvm_report_enabled(UVM_HIGH,UVM_INFO,"RegModel")) uvm_report_info ("RegModel", $sformatf("Poked register \"%s\": 'h%h", get_full_name(), value), UVM_HIGH, "t/uvm/src/reg/uvm_reg.svh", 2273, "", 1); end do_predict(rw, UVM_PREDICT_WRITE); if (!m_is_locked_by_field) XatomicX(0); endtask: poke task uvm_reg::peek(output uvm_status_e status, output uvm_reg_data_t value, input string kind = "", input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_reg_backdoor bkdr = get_backdoor(); uvm_reg_item rw; m_fname = fname; m_lineno = lineno; if (bkdr == null && !has_hdl_path(kind)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("No backdoor access available to peek register \"%s\"", get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 2301, "", 1); end status = UVM_NOT_OK; return; end if(!m_is_locked_by_field) XatomicX(1); rw = uvm_reg_item::type_id::create("mem_peek_item",,get_full_name()); rw.element = this; rw.path = UVM_BACKDOOR; rw.element_kind = UVM_REG; rw.kind = UVM_READ; rw.bd_kind = kind; rw.parent = parent; rw.extension = extension; rw.fname = fname; rw.lineno = lineno; if (bkdr != null) bkdr.read(rw); else backdoor_read(rw); status = rw.status; value = rw.value[0]; begin if (uvm_report_enabled(UVM_HIGH,UVM_INFO,"RegModel")) uvm_report_info ("RegModel", $sformatf("Peeked register \"%s\": 'h%h", get_full_name(), value), UVM_HIGH, "t/uvm/src/reg/uvm_reg.svh", 2330, "", 1); end do_predict(rw, UVM_PREDICT_READ); if (!m_is_locked_by_field) XatomicX(0); endtask: peek function bit uvm_reg::do_check(input uvm_reg_data_t expected, input uvm_reg_data_t actual, uvm_reg_map map); uvm_reg_data_t valid_bits_mask = 0; foreach(m_fields[i]) begin string acc = m_fields[i].get_access(map); acc = acc.substr(0, 1); if (!(m_fields[i].get_compare() == UVM_NO_CHECK ||acc == "WO")) begin valid_bits_mask |= ((1 << m_fields[i].get_n_bits())-1)<< m_fields[i].get_lsb_pos(); end end if ((actual&valid_bits_mask) === (expected&valid_bits_mask)) return 1; begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Register \"%s\" value read from DUT (0x%h) does not match mirrored value (0x%h) (valid bit mask = 0x%h)", get_full_name(), actual, expected,valid_bits_mask), UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 2357, "", 1); end foreach(m_fields[i]) begin string acc = m_fields[i].get_access(map); acc = acc.substr(0, 1); if (!(m_fields[i].get_compare() == UVM_NO_CHECK || acc == "WO")) begin uvm_reg_data_t mask = ((1 << m_fields[i].get_n_bits())-1); uvm_reg_data_t val = actual >> m_fields[i].get_lsb_pos() & mask; uvm_reg_data_t exp = expected >> m_fields[i].get_lsb_pos() & mask; if (val !== exp) begin begin if (uvm_report_enabled(UVM_NONE,UVM_INFO,"RegModel")) uvm_report_info ("RegModel", $sformatf("Field %s (%s[%0d:%0d]) mismatch read=%0d'h%0h mirrored=%0d'h%0h ", m_fields[i].get_name(), get_full_name(), m_fields[i].get_lsb_pos() + m_fields[i].get_n_bits() - 1, m_fields[i].get_lsb_pos(), m_fields[i].get_n_bits(), val, m_fields[i].get_n_bits(), exp), UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 2376, "", 1); end end end end return 0; endfunction task uvm_reg::mirror(output uvm_status_e status, input uvm_check_e check = UVM_NO_CHECK, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_reg_data_t v; uvm_reg_data_t exp; uvm_reg_backdoor bkdr = get_backdoor(); XatomicX(1); m_fname = fname; m_lineno = lineno; if (path == UVM_DEFAULT_DOOR) path = m_parent.get_default_door(); if (path == UVM_BACKDOOR && (bkdr != null || has_hdl_path())) map = uvm_reg_map::backdoor(); else map = get_local_map(map); if (map == null) return; if (check == UVM_CHECK) exp = get_mirrored_value(); XreadX(status, v, path, map, parent, prior, extension, fname, lineno); if (status == UVM_NOT_OK) begin XatomicX(0); return; end if (check == UVM_CHECK) void'(do_check(exp, v, map)); XatomicX(0); endtask: mirror task uvm_reg::XatomicX(bit on); process m_reg_process; m_reg_process=process::self(); if (on) begin if (m_reg_process == m_process) return; m_atomic.get(1); m_process = m_reg_process; end else begin void'(m_atomic.try_get(1)); m_atomic.put(1); m_process = null; end endtask: XatomicX function string uvm_reg::convert2string(); string res_str; string t_str; bit with_debug_info; string prefix; $sformat(convert2string, "Register %s -- %0d bytes, mirror value:'h%h", get_full_name(), get_n_bytes(),get()); if (m_maps.num()==0) convert2string = {convert2string, " (unmapped)\n"}; else convert2string = {convert2string, "\n"}; foreach (m_maps[map]) begin uvm_reg_map parent_map = map; int unsigned offset; while (parent_map != null) begin uvm_reg_map this_map = parent_map; parent_map = this_map.get_parent_map(); offset = parent_map == null ? this_map.get_base_addr(UVM_NO_HIER) : parent_map.get_submap_offset(this_map); prefix = {prefix, " "}; begin uvm_endianness_e e = this_map.get_endian(); $sformat(convert2string, "%sMapped in '%s' -- %d bytes, %s, offset 'h%0h\n", prefix, this_map.get_full_name(), this_map.get_n_bytes(), e.name(), offset); end end end prefix = " "; foreach(m_fields[i]) begin $sformat(convert2string, "%s\n%s", convert2string, m_fields[i].convert2string()); end if (m_read_in_progress == 1'b1) begin if (m_fname != "" && m_lineno != 0) $sformat(res_str, "%s:%0d ",m_fname, m_lineno); convert2string = {convert2string, "\n", res_str, "currently executing read method"}; end if ( m_write_in_progress == 1'b1) begin if (m_fname != "" && m_lineno != 0) $sformat(res_str, "%s:%0d ",m_fname, m_lineno); convert2string = {convert2string, "\n", res_str, "currently executing write method"}; end endfunction: convert2string function void uvm_reg::do_print (uvm_printer printer); uvm_reg_field f[$]; super.do_print(printer); get_fields(f); foreach(f[i]) printer.print_generic(f[i].get_name(),f[i].get_type_name(),-2,f[i].convert2string()); endfunction function uvm_object uvm_reg::clone(); begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"RegModel")) uvm_report_fatal ("RegModel", "RegModel registers cannot be cloned", UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 2528, "", 1); end return null; endfunction function void uvm_reg::do_copy(uvm_object rhs); begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"RegModel")) uvm_report_fatal ("RegModel", "RegModel registers cannot be copied", UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 2535, "", 1); end endfunction function bit uvm_reg::do_compare (uvm_object rhs, uvm_comparer comparer); begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", "RegModel registers cannot be compared", UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 2543, "", 1); end return 0; endfunction function void uvm_reg::do_pack (uvm_packer packer); begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", "RegModel registers cannot be packed", UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 2551, "", 1); end endfunction function void uvm_reg::do_unpack (uvm_packer packer); begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", "RegModel registers cannot be unpacked", UVM_NONE, "t/uvm/src/reg/uvm_reg.svh", 2558, "", 1); end endfunction typedef class uvm_reg_indirect_ftdr_seq; class uvm_reg_indirect_data extends uvm_reg; protected uvm_reg m_idx; protected uvm_reg m_tbl[]; function new(string name = "uvm_reg_indirect", int unsigned n_bits, int has_cover); super.new(name,n_bits,has_cover); endfunction: new virtual function void build(); endfunction: build function void configure (uvm_reg idx, uvm_reg reg_a[], uvm_reg_block blk_parent, uvm_reg_file regfile_parent = null); super.configure(blk_parent, regfile_parent, ""); m_idx = idx; m_tbl = reg_a; uvm_resource_db#(bit)::set({"REG::", get_full_name()}, "NO_REG_TESTS", 1); foreach (m_maps[map]) begin add_frontdoors(map); end endfunction virtual function void add_map(uvm_reg_map map); super.add_map(map); add_frontdoors(map); endfunction local function void add_frontdoors(uvm_reg_map map); foreach (m_tbl[i]) begin uvm_reg_indirect_ftdr_seq fd; if (m_tbl[i] == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,get_full_name())) uvm_report_error (get_full_name(), $sformatf("Indirect register #%0d is NULL", i), UVM_NONE, "t/uvm/src/reg/uvm_reg_indirect.svh", 90, "", 1); end continue; end fd = new(m_idx, i, this); if (m_tbl[i].is_in_map(map)) m_tbl[i].set_frontdoor(fd, map); else map.add_reg(m_tbl[i], -1, "RW", 1, fd); end endfunction virtual function void do_predict (uvm_reg_item rw, uvm_predict_e kind = UVM_PREDICT_DIRECT, uvm_reg_byte_en_t be = -1); if (m_idx.get() >= m_tbl.size()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,get_full_name())) uvm_report_error (get_full_name(), $sformatf("Address register %s has a value (%0d) greater than the maximum indirect register array size (%0d)", m_idx.get_full_name(), m_idx.get(), m_tbl.size()), UVM_NONE, "t/uvm/src/reg/uvm_reg_indirect.svh", 105, "", 1); end rw.status = UVM_NOT_OK; return; end begin int unsigned idx = m_idx.get(); m_tbl[idx].do_predict(rw, kind, be); end endfunction virtual function uvm_reg_map get_local_map(uvm_reg_map map); return m_idx.get_local_map(map); endfunction virtual function void add_field (uvm_reg_field field); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,get_full_name())) uvm_report_error (get_full_name(), "Cannot add field to an indirect data access register", UVM_NONE, "t/uvm/src/reg/uvm_reg_indirect.svh", 126, "", 1); end endfunction virtual function void set (uvm_reg_data_t value, string fname = "", int lineno = 0); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,get_full_name())) uvm_report_error (get_full_name(), "Cannot set() an indirect data access register", UVM_NONE, "t/uvm/src/reg/uvm_reg_indirect.svh", 132, "", 1); end endfunction virtual function uvm_reg_data_t get(string fname = "", int lineno = 0); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,get_full_name())) uvm_report_error (get_full_name(), "Cannot get() an indirect data access register", UVM_NONE, "t/uvm/src/reg/uvm_reg_indirect.svh", 137, "", 1); end return 0; endfunction virtual function uvm_reg get_indirect_reg(string fname = "", int lineno = 0); int unsigned idx = m_idx.get_mirrored_value(); return(m_tbl[idx]); endfunction virtual function bit needs_update(); return 0; endfunction virtual task write(output uvm_status_e status, input uvm_reg_data_t value, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); if (path == UVM_DEFAULT_DOOR) begin uvm_reg_block blk = get_parent(); path = blk.get_default_door(); end if (path == UVM_BACKDOOR) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,get_full_name())) uvm_report_warning (get_full_name(), "Cannot backdoor-write an indirect data access register. Switching to frontdoor.", UVM_NONE, "t/uvm/src/reg/uvm_reg_indirect.svh", 167, "", 1); end path = UVM_FRONTDOOR; end begin uvm_reg_item rw; XatomicX(1); rw = uvm_reg_item::type_id::create("write_item",,get_full_name()); rw.element = this; rw.element_kind = UVM_REG; rw.kind = UVM_WRITE; rw.value[0] = value; rw.path = path; rw.map = map; rw.parent = parent; rw.prior = prior; rw.extension = extension; rw.fname = fname; rw.lineno = lineno; do_write(rw); status = rw.status; XatomicX(0); end endtask virtual task read(output uvm_status_e status, output uvm_reg_data_t value, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); if (path == UVM_DEFAULT_DOOR) begin uvm_reg_block blk = get_parent(); path = blk.get_default_door(); end if (path == UVM_BACKDOOR) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,get_full_name())) uvm_report_warning (get_full_name(), "Cannot backdoor-read an indirect data access register. Switching to frontdoor.", UVM_NONE, "t/uvm/src/reg/uvm_reg_indirect.svh", 214, "", 1); end path = UVM_FRONTDOOR; end super.read(status, value, path, map, parent, prior, extension, fname, lineno); endtask virtual task poke(output uvm_status_e status, input uvm_reg_data_t value, input string kind = "", input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,get_full_name())) uvm_report_error (get_full_name(), "Cannot poke() an indirect data access register", UVM_NONE, "t/uvm/src/reg/uvm_reg_indirect.svh", 228, "", 1); end status = UVM_NOT_OK; endtask virtual task peek(output uvm_status_e status, output uvm_reg_data_t value, input string kind = "", input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,get_full_name())) uvm_report_error (get_full_name(), "Cannot peek() an indirect data access register", UVM_NONE, "t/uvm/src/reg/uvm_reg_indirect.svh", 239, "", 1); end status = UVM_NOT_OK; endtask virtual task update(output uvm_status_e status, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); status = UVM_IS_OK; endtask virtual task mirror(output uvm_status_e status, input uvm_check_e check = UVM_NO_CHECK, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); status = UVM_IS_OK; endtask endclass : uvm_reg_indirect_data class uvm_reg_indirect_ftdr_seq extends uvm_reg_frontdoor; local uvm_reg m_addr_reg; local uvm_reg m_data_reg; local int m_idx; function new(uvm_reg addr_reg, int idx, uvm_reg data_reg); super.new("uvm_reg_indirect_ftdr_seq"); m_addr_reg = addr_reg; m_idx = idx; m_data_reg = data_reg; endfunction: new virtual task body(); uvm_reg_item rw; $cast(rw,rw_info.clone()); rw.element = m_addr_reg; rw.kind = UVM_WRITE; rw.value[0]= m_idx; m_addr_reg.XatomicX(1); m_data_reg.XatomicX(1); m_addr_reg.do_write(rw); if (rw.status == UVM_NOT_OK) return; $cast(rw,rw_info.clone()); rw.element = m_data_reg; if (rw_info.kind == UVM_WRITE) m_data_reg.do_write(rw); else begin m_data_reg.do_read(rw); rw_info.value[0] = rw.value[0]; end m_addr_reg.XatomicX(0); m_data_reg.XatomicX(0); rw_info.status = rw.status; endtask endclass class uvm_reg_fifo extends uvm_reg; local uvm_reg_field value; local int m_set_cnt; local int unsigned m_size; rand uvm_reg_data_t fifo[$]; constraint valid_fifo_size { fifo.size() <= m_size; } function new(string name = "reg_fifo", int unsigned size, int unsigned n_bits, int has_cover); super.new(name,n_bits,has_cover); m_size = size; endfunction virtual function void build(); value = uvm_reg_field::type_id::create("value"); value.configure(this, get_n_bits(), 0, "RW", 0, 32'h0, 1, 0, 1); endfunction function void set_compare(uvm_check_e check=UVM_CHECK); value.set_compare(check); endfunction function int unsigned size(); return fifo.size(); endfunction function int unsigned capacity(); return m_size; endfunction virtual function void set(uvm_reg_data_t value, string fname = "", int lineno = 0); value &= ((1 << get_n_bits())-1); if (fifo.size() == m_size) begin return; end super.set(value,fname,lineno); m_set_cnt++; fifo.push_back(this.value.value); endfunction virtual task update(output uvm_status_e status, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_reg_data_t upd; if (!m_set_cnt || fifo.size() == 0) return; m_update_in_progress = 1; for (int i=fifo.size()-m_set_cnt; m_set_cnt > 0; i++, m_set_cnt--) begin if (i >= 0) begin write(status,fifo[i],path,map,parent,prior,extension,fname,lineno); end end m_update_in_progress = 0; endtask virtual function uvm_reg_data_t get(string fname="", int lineno=0); return fifo[0]; endfunction virtual function void do_predict(uvm_reg_item rw, uvm_predict_e kind = UVM_PREDICT_DIRECT, uvm_reg_byte_en_t be = -1); super.do_predict(rw,kind,be); if (rw.status == UVM_NOT_OK) return; case (kind) UVM_PREDICT_WRITE, UVM_PREDICT_DIRECT: begin if (fifo.size() != m_size && !m_update_in_progress) fifo.push_back(this.value.value); end UVM_PREDICT_READ: begin uvm_reg_data_t value = rw.value[0] & ((1 << get_n_bits())-1); uvm_reg_data_t mirror_val; if (fifo.size() == 0) begin return; end mirror_val = fifo.pop_front(); if (this.value.get_compare() == UVM_CHECK && mirror_val != value) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"MIRROR_MISMATCH")) uvm_report_warning ("MIRROR_MISMATCH", $sformatf("Observed DUT read value 'h%0h != mirror value 'h%0h",value,mirror_val), UVM_NONE, "t/uvm/src/reg/uvm_reg_fifo.svh", 237, "", 1); end end end endcase endfunction virtual task pre_write(uvm_reg_item rw); if (m_set_cnt && !m_update_in_progress) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"Needs Update")) uvm_report_error ("Needs Update", "Must call update() after set() and before write()", UVM_NONE, "t/uvm/src/reg/uvm_reg_fifo.svh", 259, "", 1); end rw.status = UVM_NOT_OK; return; end if (fifo.size() >= m_size && !m_update_in_progress) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"FIFO Full")) uvm_report_error ("FIFO Full", "Write to full FIFO ignored", UVM_NONE, "t/uvm/src/reg/uvm_reg_fifo.svh", 264, "", 1); end rw.status = UVM_NOT_OK; return; end endtask virtual task pre_read(uvm_reg_item rw); if (fifo.size() == 0) begin rw.status = UVM_NOT_OK; return; end endtask function void post_randomize(); m_set_cnt = 0; endfunction endclass class uvm_reg_file extends uvm_object; local uvm_reg_block parent; local uvm_reg_file m_rf; local string default_hdl_path = "RTL"; local uvm_object_string_pool #(uvm_queue #(string)) hdl_paths_pool; typedef uvm_object_registry#(uvm_reg_file,"uvm_reg_file") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction function uvm_object create (string name=""); uvm_reg_file tmp; if (name=="") tmp = new(); else tmp = new(name); return tmp; endfunction static function string type_name(); return "uvm_reg_file"; endfunction : type_name virtual function string get_type_name(); return "uvm_reg_file"; endfunction : get_type_name extern function new (string name=""); extern function void configure (uvm_reg_block blk_parent, uvm_reg_file regfile_parent, string hdl_path = ""); extern virtual function string get_full_name(); extern virtual function uvm_reg_block get_parent (); extern virtual function uvm_reg_block get_block (); extern virtual function uvm_reg_file get_regfile (); extern function void clear_hdl_path (string kind = "RTL"); extern function void add_hdl_path (string path, string kind = "RTL"); extern function bit has_hdl_path (string kind = ""); extern function void get_hdl_path (ref string paths[$], input string kind = ""); extern function void get_full_hdl_path (ref string paths[$], input string kind = "", input string separator = "."); extern function void set_default_hdl_path (string kind); extern function string get_default_hdl_path (); extern virtual function void do_print (uvm_printer printer); extern virtual function string convert2string(); extern virtual function uvm_object clone (); extern virtual function void do_copy (uvm_object rhs); extern virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); extern virtual function void do_pack (uvm_packer packer); extern virtual function void do_unpack (uvm_packer packer); endclass: uvm_reg_file function uvm_reg_file::new(string name=""); super.new(name); hdl_paths_pool = new("hdl_paths"); endfunction: new function void uvm_reg_file::configure(uvm_reg_block blk_parent, uvm_reg_file regfile_parent, string hdl_path = ""); if (blk_parent == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/RFILE/CFG/NOBLK")) uvm_report_error ("UVM/RFILE/CFG/NOBLK", {"uvm_reg_file::configure() called without a parent block for instance \"", get_name(), "\" of register file type \"", get_type_name(), "\"."}, UVM_NONE, "t/uvm/src/reg/uvm_reg_file.svh", 148, "", 1); end return; end this.parent = blk_parent; this.m_rf = regfile_parent; this.add_hdl_path(hdl_path); endfunction: configure function uvm_reg_block uvm_reg_file::get_block(); get_block = this.parent; endfunction: get_block function uvm_reg_file uvm_reg_file::get_regfile(); return m_rf; endfunction function void uvm_reg_file::clear_hdl_path(string kind = "RTL"); if (kind == "ALL") begin hdl_paths_pool = new("hdl_paths"); return; end if (kind == "") begin if (m_rf != null) kind = m_rf.get_default_hdl_path(); else kind = parent.get_default_hdl_path(); end if (!hdl_paths_pool.exists(kind)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Unknown HDL Abstraction '",kind,"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_file.svh", 188, "", 1); end return; end hdl_paths_pool.delete(kind); endfunction function void uvm_reg_file::add_hdl_path(string path, string kind = "RTL"); uvm_queue #(string) paths; paths = hdl_paths_pool.get(kind); paths.push_back(path); endfunction function bit uvm_reg_file::has_hdl_path(string kind = ""); if (kind == "") begin if (m_rf != null) kind = m_rf.get_default_hdl_path(); else kind = parent.get_default_hdl_path(); end return hdl_paths_pool.exists(kind); endfunction function void uvm_reg_file::get_hdl_path(ref string paths[$], input string kind = ""); uvm_queue #(string) hdl_paths; if (kind == "") begin if (m_rf != null) kind = m_rf.get_default_hdl_path(); else kind = parent.get_default_hdl_path(); end if (!has_hdl_path(kind)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Register does not have hdl path defined for abstraction '",kind,"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_file.svh", 237, "", 1); end return; end hdl_paths = hdl_paths_pool.get(kind); for (int i=0; i= min_offset; start_offset <= max_offset - len + 1; } constraint uvm_mem_mam_policy_no_overlap { foreach (in_use[i]) { !(start_offset <= in_use[i].Xend_offsetX && start_offset + len - 1 >= in_use[i].Xstart_offsetX); } } endclass class uvm_mem_mam_cfg; rand int unsigned n_bytes; rand bit [63:0] start_offset; rand bit [63:0] end_offset; rand uvm_mem_mam::alloc_mode_e mode; rand uvm_mem_mam::locality_e locality; constraint uvm_mem_mam_cfg_valid { end_offset > start_offset; n_bytes < 64; } endclass function uvm_mem_region::new(bit [63:0] start_offset, bit [63:0] end_offset, int unsigned len, int unsigned n_bytes, uvm_mem_mam parent); this.Xstart_offsetX = start_offset; this.Xend_offsetX = end_offset; this.len = len; this.n_bytes = n_bytes; this.parent = parent; this.XvregX = null; endfunction: new function bit [63:0] uvm_mem_region::get_start_offset(); return this.Xstart_offsetX; endfunction: get_start_offset function bit [63:0] uvm_mem_region::get_end_offset(); return this.Xend_offsetX; endfunction: get_end_offset function int unsigned uvm_mem_region::get_len(); return this.len; endfunction: get_len function int unsigned uvm_mem_region::get_n_bytes(); return this.n_bytes; endfunction: get_n_bytes function string uvm_mem_region::convert2string(); $sformat(convert2string, "['h%h:'h%h]", this.Xstart_offsetX, this.Xend_offsetX); endfunction: convert2string function void uvm_mem_region::release_region(); this.parent.release_region(this); endfunction function uvm_mem uvm_mem_region::get_memory(); return this.parent.get_memory(); endfunction: get_memory function uvm_vreg uvm_mem_region::get_virtual_registers(); return this.XvregX; endfunction: get_virtual_registers function uvm_mem_mam::new(string name, uvm_mem_mam_cfg cfg, uvm_mem mem = null); this.cfg = cfg; this.memory = mem; this.default_alloc = new; endfunction: new function uvm_mem_mam_cfg uvm_mem_mam::reconfigure(uvm_mem_mam_cfg cfg = null); uvm_root top; uvm_coreservice_t cs; if (cfg == null) return this.cfg; cs = uvm_coreservice_t::get(); top = cs.get_root(); if (cfg.n_bytes !== this.cfg.n_bytes) begin top.uvm_report_error("uvm_mem_mam", $sformatf("Cannot reconfigure Memory Allocation Manager with a different number of bytes (%0d !== %0d)", cfg.n_bytes, this.cfg.n_bytes), UVM_LOW); return this.cfg; end foreach (this.in_use[i]) begin if (this.in_use[i].get_start_offset() < cfg.start_offset || this.in_use[i].get_end_offset() > cfg.end_offset) begin top.uvm_report_error("uvm_mem_mam", $sformatf("Cannot reconfigure Memory Allocation Manager with a currently allocated region outside of the managed address range ([%0d:%0d] outside of [%0d:%0d])", this.in_use[i].get_start_offset(), this.in_use[i].get_end_offset(), cfg.start_offset, cfg.end_offset), UVM_LOW); return this.cfg; end end reconfigure = this.cfg; this.cfg = cfg; endfunction: reconfigure function uvm_mem_region uvm_mem_mam::reserve_region(bit [63:0] start_offset, int unsigned n_bytes, string fname = "", int lineno = 0); bit [63:0] end_offset; this.fname = fname; this.lineno = lineno; if (n_bytes == 0) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", "Cannot reserve 0 bytes", UVM_NONE, "t/uvm/src/reg/uvm_mem_mam.svh", 638, "", 1); end return null; end if (start_offset < this.cfg.start_offset) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot reserve before start of memory space: 'h%h < 'h%h", start_offset, this.cfg.start_offset), UVM_NONE, "t/uvm/src/reg/uvm_mem_mam.svh", 644, "", 1); end return null; end end_offset = start_offset + ((n_bytes-1) / this.cfg.n_bytes); n_bytes = (end_offset - start_offset + 1) * this.cfg.n_bytes; if (end_offset > this.cfg.end_offset) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot reserve past end of memory space: 'h%h > 'h%h", end_offset, this.cfg.end_offset), UVM_NONE, "t/uvm/src/reg/uvm_mem_mam.svh", 653, "", 1); end return null; end begin if (uvm_report_enabled(UVM_MEDIUM,UVM_INFO,"RegModel")) uvm_report_info ("RegModel", $sformatf("Attempting to reserve ['h%h:'h%h]...", start_offset, end_offset), UVM_MEDIUM, "t/uvm/src/reg/uvm_mem_mam.svh", 658, "", 1); end foreach (this.in_use[i]) begin if (start_offset <= this.in_use[i].get_end_offset() && end_offset >= this.in_use[i].get_start_offset()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot reserve ['h%h:'h%h] because it overlaps with %s", start_offset, end_offset, this.in_use[i].convert2string()), UVM_NONE, "t/uvm/src/reg/uvm_mem_mam.svh", 669, "", 1); end return null; end if (start_offset > this.in_use[i].get_start_offset()) begin reserve_region = new(start_offset, end_offset, end_offset - start_offset + 1, n_bytes, this); this.in_use.insert(i, reserve_region); return reserve_region; end end reserve_region = new(start_offset, end_offset, end_offset - start_offset + 1, n_bytes, this); this.in_use.push_back(reserve_region); endfunction: reserve_region function uvm_mem_region uvm_mem_mam::request_region(int unsigned n_bytes, uvm_mem_mam_policy alloc = null, string fname = "", int lineno = 0); this.fname = fname; this.lineno = lineno; if (alloc == null) alloc = this.default_alloc; alloc.len = (n_bytes-1) / this.cfg.n_bytes + 1; alloc.min_offset = this.cfg.start_offset; alloc.max_offset = this.cfg.end_offset; alloc.in_use = this.in_use; if (!alloc.randomize()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", "Unable to randomize policy", UVM_NONE, "t/uvm/src/reg/uvm_mem_mam.svh", 702, "", 1); end return null; end return reserve_region(alloc.start_offset, n_bytes); endfunction: request_region function void uvm_mem_mam::release_region(uvm_mem_region region); if (region == null) return; foreach (this.in_use[i]) begin if (this.in_use[i] == region) begin this.in_use.delete(i); return; end end begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Attempting to release unallocated region\n", region.convert2string()}, UVM_NONE, "t/uvm/src/reg/uvm_mem_mam.svh", 721, "", 1); end endfunction: release_region function void uvm_mem_mam::release_all_regions(); in_use.delete(); endfunction: release_all_regions function string uvm_mem_mam::convert2string(); convert2string = "Allocated memory regions:\n"; foreach (this.in_use[i]) begin $sformat(convert2string, "%s %s\n", convert2string, this.in_use[i].convert2string()); end endfunction: convert2string function uvm_mem_region uvm_mem_mam::for_each(bit reset = 0); if (reset) this.for_each_idx = -1; this.for_each_idx++; if (this.for_each_idx >= this.in_use.size()) begin return null; end return this.in_use[this.for_each_idx]; endfunction: for_each function uvm_mem uvm_mem_mam::get_memory(); return this.memory; endfunction: get_memory task uvm_mem_region::write(output uvm_status_e status, input uvm_reg_addr_t offset, input uvm_reg_data_t value, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_mem mem = this.parent.get_memory(); this.fname = fname; this.lineno = lineno; if (mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", "Cannot use uvm_mem_region::write() on a region that was allocated by a Memory Allocation Manager that was not associated with a uvm_mem instance", UVM_NONE, "t/uvm/src/reg/uvm_mem_mam.svh", 773, "", 1); end status = UVM_NOT_OK; return; end if (offset > this.len) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Attempting to write to an offset outside of the allocated region (%0d > %0d)", offset, this.len), UVM_NONE, "t/uvm/src/reg/uvm_mem_mam.svh", 781, "", 1); end status = UVM_NOT_OK; return; end mem.write(status, offset + this.get_start_offset(), value, path, map, parent, prior, extension); endtask: write task uvm_mem_region::read(output uvm_status_e status, input uvm_reg_addr_t offset, output uvm_reg_data_t value, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_mem mem = this.parent.get_memory(); this.fname = fname; this.lineno = lineno; if (mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", "Cannot use uvm_mem_region::read() on a region that was allocated by a Memory Allocation Manager that was not associated with a uvm_mem instance", UVM_NONE, "t/uvm/src/reg/uvm_mem_mam.svh", 806, "", 1); end status = UVM_NOT_OK; return; end if (offset > this.len) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Attempting to read from an offset outside of the allocated region (%0d > %0d)", offset, this.len), UVM_NONE, "t/uvm/src/reg/uvm_mem_mam.svh", 814, "", 1); end status = UVM_NOT_OK; return; end mem.read(status, offset + this.get_start_offset(), value, path, map, parent, prior, extension); endtask: read task uvm_mem_region::burst_write(output uvm_status_e status, input uvm_reg_addr_t offset, input uvm_reg_data_t value[], input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_mem mem = this.parent.get_memory(); this.fname = fname; this.lineno = lineno; if (mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", "Cannot use uvm_mem_region::burst_write() on a region that was allocated by a Memory Allocation Manager that was not associated with a uvm_mem instance", UVM_NONE, "t/uvm/src/reg/uvm_mem_mam.svh", 839, "", 1); end status = UVM_NOT_OK; return; end if (offset + value.size() > this.len) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Attempting to burst-write to an offset outside of the allocated region (burst to [%0d:%0d] > mem_size %0d)", offset,offset+value.size(),this.len), UVM_NONE, "t/uvm/src/reg/uvm_mem_mam.svh", 847, "", 1); end status = UVM_NOT_OK; return; end mem.burst_write(status, offset + get_start_offset(), value, path, map, parent, prior, extension); endtask: burst_write task uvm_mem_region::burst_read(output uvm_status_e status, input uvm_reg_addr_t offset, output uvm_reg_data_t value[], input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_mem mem = this.parent.get_memory(); this.fname = fname; this.lineno = lineno; if (mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", "Cannot use uvm_mem_region::burst_read() on a region that was allocated by a Memory Allocation Manager that was not associated with a uvm_mem instance", UVM_NONE, "t/uvm/src/reg/uvm_mem_mam.svh", 873, "", 1); end status = UVM_NOT_OK; return; end if (offset + value.size() > this.len) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Attempting to burst-read to an offset outside of the allocated region (burst to [%0d:%0d] > mem_size %0d)", offset,offset+value.size(),this.len), UVM_NONE, "t/uvm/src/reg/uvm_mem_mam.svh", 881, "", 1); end status = UVM_NOT_OK; return; end mem.burst_read(status, offset + get_start_offset(), value, path, map, parent, prior, extension); endtask: burst_read task uvm_mem_region::poke(output uvm_status_e status, input uvm_reg_addr_t offset, input uvm_reg_data_t value, input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_mem mem = this.parent.get_memory(); this.fname = fname; this.lineno = lineno; if (mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", "Cannot use uvm_mem_region::poke() on a region that was allocated by a Memory Allocation Manager that was not associated with a uvm_mem instance", UVM_NONE, "t/uvm/src/reg/uvm_mem_mam.svh", 904, "", 1); end status = UVM_NOT_OK; return; end if (offset > this.len) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Attempting to poke to an offset outside of the allocated region (%0d > %0d)", offset, this.len), UVM_NONE, "t/uvm/src/reg/uvm_mem_mam.svh", 912, "", 1); end status = UVM_NOT_OK; return; end mem.poke(status, offset + this.get_start_offset(), value, "", parent, extension); endtask: poke task uvm_mem_region::peek(output uvm_status_e status, input uvm_reg_addr_t offset, output uvm_reg_data_t value, input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_mem mem = this.parent.get_memory(); this.fname = fname; this.lineno = lineno; if (mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", "Cannot use uvm_mem_region::peek() on a region that was allocated by a Memory Allocation Manager that was not associated with a uvm_mem instance", UVM_NONE, "t/uvm/src/reg/uvm_mem_mam.svh", 933, "", 1); end status = UVM_NOT_OK; return; end if (offset > this.len) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Attempting to peek from an offset outside of the allocated region (%0d > %0d)", offset, this.len), UVM_NONE, "t/uvm/src/reg/uvm_mem_mam.svh", 941, "", 1); end status = UVM_NOT_OK; return; end mem.peek(status, offset + this.get_start_offset(), value, "", parent, extension); endtask: peek typedef class uvm_mem_region; typedef class uvm_mem_mam; typedef class uvm_vreg_cbs; class uvm_vreg extends uvm_object; static local bit m_register_cb_uvm_vreg_cbs = uvm_callbacks#(uvm_vreg,uvm_vreg_cbs)::m_register_pair("uvm_vreg","uvm_vreg_cbs"); local bit locked; local uvm_reg_block parent; local int unsigned n_bits; local int unsigned n_used_bits; local uvm_vreg_field fields[$]; local uvm_mem mem; local uvm_reg_addr_t offset; local int unsigned incr; local longint unsigned size; local bit is_static; local uvm_mem_region region; local semaphore atomic; local string fname; local int lineno; local bit read_in_progress; local bit write_in_progress; extern function new(string name, int unsigned n_bits); extern function void configure(uvm_reg_block parent, uvm_mem mem = null, longint unsigned size = 0, uvm_reg_addr_t offset = 0, int unsigned incr = 0); extern virtual function bit implement(longint unsigned n, uvm_mem mem = null, uvm_reg_addr_t offset = 0, int unsigned incr = 0); extern virtual function uvm_mem_region allocate(longint unsigned n, uvm_mem_mam mam, uvm_mem_mam_policy alloc = null); extern virtual function uvm_mem_region get_region(); extern virtual function void release_region(); extern virtual function void set_parent(uvm_reg_block parent); extern function void Xlock_modelX(); extern function void add_field(uvm_vreg_field field); extern task XatomicX(bit on); extern virtual function string get_full_name(); extern virtual function uvm_reg_block get_parent(); extern virtual function uvm_reg_block get_block(); extern virtual function uvm_mem get_memory(); extern virtual function int get_n_maps (); extern function bit is_in_map (uvm_reg_map map); extern virtual function void get_maps (ref uvm_reg_map maps[$]); extern virtual function string get_rights(uvm_reg_map map = null); extern virtual function string get_access(uvm_reg_map map = null); extern virtual function int unsigned get_size(); extern virtual function int unsigned get_n_bytes(); extern virtual function int unsigned get_n_memlocs(); extern virtual function int unsigned get_incr(); extern virtual function void get_fields(ref uvm_vreg_field fields[$]); extern virtual function uvm_vreg_field get_field_by_name(string name); extern virtual function uvm_reg_addr_t get_offset_in_memory(longint unsigned idx); extern virtual function uvm_reg_addr_t get_address(longint unsigned idx, uvm_reg_map map = null); extern virtual task write(input longint unsigned idx, output uvm_status_e status, input uvm_reg_data_t value, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); extern virtual task read(input longint unsigned idx, output uvm_status_e status, output uvm_reg_data_t value, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); extern virtual task poke(input longint unsigned idx, output uvm_status_e status, input uvm_reg_data_t value, input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); extern virtual task peek(input longint unsigned idx, output uvm_status_e status, output uvm_reg_data_t value, input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); extern function void reset(string kind = "HARD"); virtual task pre_write(longint unsigned idx, ref uvm_reg_data_t wdat, ref uvm_door_e path, ref uvm_reg_map map); endtask: pre_write virtual task post_write(longint unsigned idx, uvm_reg_data_t wdat, uvm_door_e path, uvm_reg_map map, ref uvm_status_e status); endtask: post_write virtual task pre_read(longint unsigned idx, ref uvm_door_e path, ref uvm_reg_map map); endtask: pre_read virtual task post_read(longint unsigned idx, ref uvm_reg_data_t rdat, input uvm_door_e path, input uvm_reg_map map, ref uvm_status_e status); endtask: post_read extern virtual function void do_print (uvm_printer printer); extern virtual function string convert2string; extern virtual function uvm_object clone(); extern virtual function void do_copy (uvm_object rhs); extern virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); extern virtual function void do_pack (uvm_packer packer); extern virtual function void do_unpack (uvm_packer packer); endclass: uvm_vreg virtual class uvm_vreg_cbs extends uvm_callback; typedef uvm_abstract_object_registry#(uvm_vreg_cbs,"uvm_vreg_cbs") type_id; static function type_id get_type(); return type_id::get(); endfunction virtual function uvm_object_wrapper get_object_type(); return type_id::get(); endfunction static function string type_name(); return "uvm_vreg_cbs"; endfunction : type_name virtual function string get_type_name(); return "uvm_vreg_cbs"; endfunction : get_type_name string fname; int lineno; function new(string name = "uvm_reg_cbs"); super.new(name); endfunction virtual task pre_write(uvm_vreg rg, longint unsigned idx, ref uvm_reg_data_t wdat, ref uvm_door_e path, ref uvm_reg_map map); endtask: pre_write virtual task post_write(uvm_vreg rg, longint unsigned idx, uvm_reg_data_t wdat, uvm_door_e path, uvm_reg_map map, ref uvm_status_e status); endtask: post_write virtual task pre_read(uvm_vreg rg, longint unsigned idx, ref uvm_door_e path, ref uvm_reg_map map); endtask: pre_read virtual task post_read(uvm_vreg rg, longint unsigned idx, ref uvm_reg_data_t rdat, input uvm_door_e path, input uvm_reg_map map, ref uvm_status_e status); endtask: post_read endclass: uvm_vreg_cbs typedef uvm_callbacks#(uvm_vreg, uvm_vreg_cbs) uvm_vreg_cb ; typedef uvm_callback_iter#(uvm_vreg, uvm_vreg_cbs) uvm_vreg_cb_iter ; function uvm_vreg::new(string name, int unsigned n_bits); super.new(name); if (n_bits == 0) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Virtual register \"%s\" cannot have 0 bits", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 425, "", 1); end n_bits = 1; end if (n_bits > 64) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Virtual register \"%s\" cannot have more than %0d bits (%0d)", this.get_full_name(), 64, n_bits), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 429, "", 1); end n_bits = 64; end this.n_bits = n_bits; this.locked = 0; endfunction: new function void uvm_vreg::configure(uvm_reg_block parent, uvm_mem mem = null, longint unsigned size = 0, uvm_reg_addr_t offset = 0, int unsigned incr = 0); this.parent = parent; this.n_used_bits = 0; if (mem != null) begin void'(this.implement(size, mem, offset, incr)); this.is_static = 1; end else begin this.mem = null; this.is_static = 0; end this.parent.add_vreg(this); this.atomic = new(1); endfunction: configure function void uvm_vreg::Xlock_modelX(); if (this.locked) return; this.locked = 1; endfunction: Xlock_modelX function void uvm_vreg::add_field(uvm_vreg_field field); int offset; int idx; if (this.locked) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", "Cannot add virtual field to locked virtual register model", UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 473, "", 1); end return; end if (field == null) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"RegModel")) uvm_report_fatal ("RegModel", "Attempting to register NULL virtual field", UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 477, "", 1); end offset = field.get_lsb_pos_in_register(); idx = -1; foreach (this.fields[i]) begin if (offset < this.fields[i].get_lsb_pos_in_register()) begin int j = i; this.fields.insert(j, field); idx = i; break; end end if (idx < 0) begin this.fields.push_back(field); idx = this.fields.size()-1; end this.n_used_bits += field.get_n_bits(); if (this.n_used_bits > this.n_bits) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Virtual fields use more bits (%0d) than available in virtual register \"%s\" (%0d)", this.n_used_bits, this.get_full_name(), this.n_bits), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 501, "", 1); end end if (idx > 0) begin if (this.fields[idx-1].get_lsb_pos_in_register() + this.fields[idx-1].get_n_bits() > offset) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Field %s overlaps field %s in virtual register \"%s\"", this.fields[idx-1].get_name(), field.get_name(), this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 511, "", 1); end end end if (idx < this.fields.size()-1) begin if (offset + field.get_n_bits() > this.fields[idx+1].get_lsb_pos_in_register()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Field %s overlaps field %s in virtual register \"%s\"", field.get_name(), this.fields[idx+1].get_name(), this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 520, "", 1); end end end endfunction: add_field task uvm_vreg::XatomicX(bit on); if (on) this.atomic.get(1); else begin void'(this.atomic.try_get(1)); this.atomic.put(1); end endtask: XatomicX function void uvm_vreg::reset(string kind = "HARD"); void'(this.atomic.try_get(1)); this.atomic.put(1); endfunction: reset function string uvm_vreg::get_full_name(); uvm_reg_block blk; get_full_name = this.get_name(); blk = this.get_block(); if (blk == null) return get_full_name; if (blk.get_parent() == null) return get_full_name; get_full_name = {this.parent.get_full_name(), ".", get_full_name}; endfunction: get_full_name function void uvm_vreg::set_parent(uvm_reg_block parent); this.parent = parent; endfunction: set_parent function uvm_reg_block uvm_vreg::get_parent(); get_parent = this.parent; endfunction: get_parent function uvm_reg_block uvm_vreg::get_block(); get_block = this.parent; endfunction: get_block function bit uvm_vreg::implement(longint unsigned n, uvm_mem mem = null, uvm_reg_addr_t offset = 0, int unsigned incr = 0); uvm_mem_region region; if(n < 1) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Attempting to implement virtual register \"%s\" with a subscript less than one doesn't make sense",this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 579, "", 1); end return 0; end if (mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Attempting to implement virtual register \"%s\" using a NULL uvm_mem reference", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 584, "", 1); end return 0; end if (this.is_static) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Virtual register \"%s\" is static and cannot be dynamically implemented", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 589, "", 1); end return 0; end if (mem.get_block() != this.parent) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Attempting to implement virtual register \"%s\" on memory \"%s\" in a different block", this.get_full_name(), mem.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 596, "", 1); end return 0; end begin int min_incr = (this.get_n_bytes()-1) / mem.get_n_bytes() + 1; if (incr == 0) incr = min_incr; if (min_incr > incr) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Virtual register \"%s\" increment is too small (%0d): Each virtual register requires at least %0d locations in memory \"%s\".", this.get_full_name(), incr, min_incr, mem.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 606, "", 1); end return 0; end end if (offset + (n * incr) > mem.get_size()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Given Offset for Virtual register \"%s[%0d]\" is too big for memory %s@'h%0h", this.get_full_name(), n, mem.get_full_name(), offset), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 613, "", 1); end return 0; end region = mem.mam.reserve_region(offset,n*incr*mem.get_n_bytes()); if (region == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Could not allocate a memory region for virtual register \"%s\"", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 620, "", 1); end return 0; end if (this.mem != null) begin begin if (uvm_report_enabled(UVM_MEDIUM,UVM_INFO,"RegModel")) uvm_report_info ("RegModel", $sformatf("Virtual register \"%s\" is being moved re-implemented from %s@'h%0h to %s@'h%0h", this.get_full_name(), this.mem.get_full_name(), this.offset, mem.get_full_name(), offset), UVM_MEDIUM, "t/uvm/src/reg/uvm_vreg.svh", 629, "", 1); end this.release_region(); end this.region = region; this.mem = mem; this.size = n; this.offset = offset; this.incr = incr; this.mem.Xadd_vregX(this); return 1; endfunction: implement function uvm_mem_region uvm_vreg::allocate(longint unsigned n, uvm_mem_mam mam, uvm_mem_mam_policy alloc=null); uvm_mem mem; if(n < 1) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Attempting to implement virtual register \"%s\" with a subscript less than one doesn't make sense",this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 652, "", 1); end return null; end if (mam == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Attempting to implement virtual register \"%s\" using a NULL uvm_mem_mam reference", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 657, "", 1); end return null; end if (this.is_static) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Virtual register \"%s\" is static and cannot be dynamically allocated", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 662, "", 1); end return null; end mem = mam.get_memory(); if (mem.get_block() != this.parent) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Attempting to allocate virtual register \"%s\" on memory \"%s\" in a different block", this.get_full_name(), mem.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 670, "", 1); end return null; end begin int min_incr = (this.get_n_bytes()-1) / mem.get_n_bytes() + 1; if (incr == 0) incr = min_incr; if (min_incr < incr) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Virtual register \"%s\" increment is too small (%0d): Each virtual register requires at least %0d locations in memory \"%s\".", this.get_full_name(), incr, min_incr, mem.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 680, "", 1); end return null; end end allocate = mam.request_region(n*incr*mem.get_n_bytes(), alloc); if (allocate == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Could not allocate a memory region for virtual register \"%s\"", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 688, "", 1); end return null; end if (this.mem != null) begin begin if (uvm_report_enabled(UVM_MEDIUM,UVM_INFO,"RegModel")) uvm_report_info ("RegModel", $sformatf("Virtual register \"%s\" is being moved from %s@'h%0h to %s@'h%0h", this.get_full_name(), this.mem.get_full_name(), this.offset, mem.get_full_name(), allocate.get_start_offset()), UVM_MEDIUM, "t/uvm/src/reg/uvm_vreg.svh", 698, "", 1); end this.release_region(); end this.region = allocate; this.mem = mam.get_memory(); this.offset = allocate.get_start_offset(); this.size = n; this.incr = incr; this.mem.Xadd_vregX(this); endfunction: allocate function uvm_mem_region uvm_vreg::get_region(); return this.region; endfunction: get_region function void uvm_vreg::release_region(); if (this.is_static) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Virtual register \"%s\" is static and cannot be dynamically released", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 721, "", 1); end return; end if (this.mem != null) this.mem.Xdelete_vregX(this); if (this.region != null) begin this.region.release_region(); end this.region = null; this.mem = null; this.size = 0; this.offset = 0; this.reset(); endfunction: release_region function uvm_mem uvm_vreg::get_memory(); return this.mem; endfunction: get_memory function uvm_reg_addr_t uvm_vreg::get_offset_in_memory(longint unsigned idx); if (this.mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot call uvm_vreg::get_offset_in_memory() on unimplemented virtual register \"%s\"", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 749, "", 1); end return 0; end return this.offset + idx * this.incr; endfunction function uvm_reg_addr_t uvm_vreg::get_address(longint unsigned idx, uvm_reg_map map = null); if (this.mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot get address of of unimplemented virtual register \"%s\".", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 760, "", 1); end return 0; end return this.mem.get_address(this.get_offset_in_memory(idx), map); endfunction: get_address function int unsigned uvm_vreg::get_size(); if (this.size == 0) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot call uvm_vreg::get_size() on unimplemented virtual register \"%s\"", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 771, "", 1); end return 0; end return this.size; endfunction: get_size function int unsigned uvm_vreg::get_n_bytes(); return ((this.n_bits-1) / 8) + 1; endfunction: get_n_bytes function int unsigned uvm_vreg::get_n_memlocs(); if (this.mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot call uvm_vreg::get_n_memlocs() on unimplemented virtual register \"%s\"", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 787, "", 1); end return 0; end return (this.get_n_bytes()-1) / this.mem.get_n_bytes() + 1; endfunction: get_n_memlocs function int unsigned uvm_vreg::get_incr(); if (this.incr == 0) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot call uvm_vreg::get_incr() on unimplemented virtual register \"%s\"", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 798, "", 1); end return 0; end return this.incr; endfunction: get_incr function int uvm_vreg::get_n_maps(); if (this.mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot call uvm_vreg::get_n_maps() on unimplemented virtual register \"%s\"", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 809, "", 1); end return 0; end return this.mem.get_n_maps(); endfunction: get_n_maps function void uvm_vreg::get_maps(ref uvm_reg_map maps[$]); if (this.mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot call uvm_vreg::get_maps() on unimplemented virtual register \"%s\"", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 820, "", 1); end return; end this.mem.get_maps(maps); endfunction: get_maps function bit uvm_vreg::is_in_map(uvm_reg_map map); if (this.mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot call uvm_vreg::is_in_map() on unimplemented virtual register \"%s\"", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 831, "", 1); end return 0; end return this.mem.is_in_map(map); endfunction function string uvm_vreg::get_access(uvm_reg_map map = null); if (this.mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot call uvm_vreg::get_rights() on unimplemented virtual register \"%s\"", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 842, "", 1); end return "RW"; end return this.mem.get_access(map); endfunction: get_access function string uvm_vreg::get_rights(uvm_reg_map map = null); if (this.mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot call uvm_vreg::get_rights() on unimplemented virtual register \"%s\"", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 853, "", 1); end return "RW"; end return this.mem.get_rights(map); endfunction: get_rights function void uvm_vreg::get_fields(ref uvm_vreg_field fields[$]); foreach(this.fields[i]) fields.push_back(this.fields[i]); endfunction: get_fields function uvm_vreg_field uvm_vreg::get_field_by_name(string name); foreach (this.fields[i]) begin if (this.fields[i].get_name() == name) begin return this.fields[i]; end end begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", $sformatf("Unable to locate field \"%s\" in virtual register \"%s\".", name, this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 874, "", 1); end get_field_by_name = null; endfunction: get_field_by_name task uvm_vreg::write(input longint unsigned idx, output uvm_status_e status, input uvm_reg_data_t value, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_vreg_cb_iter cbs = new(this); uvm_reg_addr_t addr; uvm_reg_data_t tmp; uvm_reg_data_t msk; int lsb; this.write_in_progress = 1'b1; this.fname = fname; this.lineno = lineno; if (this.mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot write to unimplemented virtual register \"%s\".", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 899, "", 1); end status = UVM_NOT_OK; return; end if (path == UVM_DEFAULT_DOOR) path = this.parent.get_default_door(); foreach (fields[i]) begin uvm_vreg_field_cb_iter cbs = new(fields[i]); uvm_vreg_field f = fields[i]; lsb = f.get_lsb_pos_in_register(); msk = ((1<> lsb; f.pre_write(idx, tmp, path, map); for (uvm_vreg_field_cbs cb = cbs.first(); cb != null; cb = cbs.next()) begin cb.fname = this.fname; cb.lineno = this.lineno; cb.pre_write(f, idx, tmp, path, map); end value = (value & ~msk) | (tmp << lsb); end this.pre_write(idx, value, path, map); for (uvm_vreg_cbs cb = cbs.first(); cb != null; cb = cbs.next()) begin cb.fname = this.fname; cb.lineno = this.lineno; cb.pre_write(this, idx, value, path, map); end addr = this.offset + (idx * this.incr); lsb = 0; status = UVM_IS_OK; for (int i = 0; i < this.get_n_memlocs(); i++) begin uvm_status_e s; msk = ((1<<(this.mem.get_n_bytes()*8))-1) << lsb; tmp = (value & msk) >> lsb; this.mem.write(s, addr + i, tmp, path, map , parent, , extension, fname, lineno); if (s != UVM_IS_OK && s != UVM_HAS_X) status = s; lsb += this.mem.get_n_bytes() * 8; end for (uvm_vreg_cbs cb = cbs.first(); cb != null; cb = cbs.next()) begin cb.fname = this.fname; cb.lineno = this.lineno; cb.post_write(this, idx, value, path, map, status); end this.post_write(idx, value, path, map, status); foreach (fields[i]) begin uvm_vreg_field_cb_iter cbs = new(fields[i]); uvm_vreg_field f = fields[i]; lsb = f.get_lsb_pos_in_register(); msk = ((1<> lsb; for (uvm_vreg_field_cbs cb = cbs.first(); cb != null; cb = cbs.next()) begin cb.fname = this.fname; cb.lineno = this.lineno; cb.post_write(f, idx, tmp, path, map, status); end f.post_write(idx, tmp, path, map, status); value = (value & ~msk) | (tmp << lsb); end begin if (uvm_report_enabled(UVM_MEDIUM,UVM_INFO,"RegModel")) uvm_report_info ("RegModel", $sformatf("Wrote virtual register \"%s\"[%0d] via %s with: 'h%h", this.get_full_name(), idx, (path == UVM_FRONTDOOR) ? "frontdoor" : "backdoor", value), UVM_MEDIUM, "t/uvm/src/reg/uvm_vreg.svh", 976, "", 1); end this.write_in_progress = 1'b0; this.fname = ""; this.lineno = 0; endtask: write task uvm_vreg::read(input longint unsigned idx, output uvm_status_e status, output uvm_reg_data_t value, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_vreg_cb_iter cbs = new(this); uvm_reg_addr_t addr; uvm_reg_data_t tmp; uvm_reg_data_t msk; int lsb; this.read_in_progress = 1'b1; this.fname = fname; this.lineno = lineno; if (this.mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot read from unimplemented virtual register \"%s\".", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 1005, "", 1); end status = UVM_NOT_OK; return; end if (path == UVM_DEFAULT_DOOR) path = this.parent.get_default_door(); foreach (fields[i]) begin uvm_vreg_field_cb_iter cbs = new(fields[i]); uvm_vreg_field f = fields[i]; f.pre_read(idx, path, map); for (uvm_vreg_field_cbs cb = cbs.first(); cb != null; cb = cbs.next()) begin cb.fname = this.fname; cb.lineno = this.lineno; cb.pre_read(f, idx, path, map); end end this.pre_read(idx, path, map); for (uvm_vreg_cbs cb = cbs.first(); cb != null; cb = cbs.next()) begin cb.fname = this.fname; cb.lineno = this.lineno; cb.pre_read(this, idx, path, map); end addr = this.offset + (idx * this.incr); lsb = 0; value = 0; status = UVM_IS_OK; for (int i = 0; i < this.get_n_memlocs(); i++) begin uvm_status_e s; this.mem.read(s, addr + i, tmp, path, map, parent, , extension, fname, lineno); if (s != UVM_IS_OK && s != UVM_HAS_X) status = s; value |= tmp << lsb; lsb += this.mem.get_n_bytes() * 8; end for (uvm_vreg_cbs cb = cbs.first(); cb != null; cb = cbs.next()) begin cb.fname = this.fname; cb.lineno = this.lineno; cb.post_read(this, idx, value, path, map, status); end this.post_read(idx, value, path, map, status); foreach (fields[i]) begin uvm_vreg_field_cb_iter cbs = new(fields[i]); uvm_vreg_field f = fields[i]; lsb = f.get_lsb_pos_in_register(); msk = ((1<> lsb; for (uvm_vreg_field_cbs cb = cbs.first(); cb != null; cb = cbs.next()) begin cb.fname = this.fname; cb.lineno = this.lineno; cb.post_read(f, idx, tmp, path, map, status); end f.post_read(idx, tmp, path, map, status); value = (value & ~msk) | (tmp << lsb); end begin if (uvm_report_enabled(UVM_MEDIUM,UVM_INFO,"RegModel")) uvm_report_info ("RegModel", $sformatf("Read virtual register \"%s\"[%0d] via %s: 'h%h", this.get_full_name(), idx, (path == UVM_FRONTDOOR) ? "frontdoor" : "backdoor", value), UVM_MEDIUM, "t/uvm/src/reg/uvm_vreg.svh", 1078, "", 1); end this.read_in_progress = 1'b0; this.fname = ""; this.lineno = 0; endtask: read task uvm_vreg::poke(input longint unsigned idx, output uvm_status_e status, input uvm_reg_data_t value, input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_reg_addr_t addr; uvm_reg_data_t tmp; uvm_reg_data_t msk; int lsb; this.fname = fname; this.lineno = lineno; if (this.mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot poke in unimplemented virtual register \"%s\".", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 1101, "", 1); end status = UVM_NOT_OK; return; end addr = this.offset + (idx * this.incr); lsb = 0; status = UVM_IS_OK; for (int i = 0; i < this.get_n_memlocs(); i++) begin uvm_status_e s; msk = ((1<<(this.mem.get_n_bytes() * 8))-1) << lsb; tmp = (value & msk) >> lsb; this.mem.poke(status, addr + i, tmp, "", parent, extension, fname, lineno); if (s != UVM_IS_OK && s != UVM_HAS_X) status = s; lsb += this.mem.get_n_bytes() * 8; end begin if (uvm_report_enabled(UVM_MEDIUM,UVM_INFO,"RegModel")) uvm_report_info ("RegModel", $sformatf("Poked virtual register \"%s\"[%0d] with: 'h%h", this.get_full_name(), idx, value), UVM_MEDIUM, "t/uvm/src/reg/uvm_vreg.svh", 1123, "", 1); end this.fname = ""; this.lineno = 0; endtask: poke task uvm_vreg::peek(input longint unsigned idx, output uvm_status_e status, output uvm_reg_data_t value, input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_reg_addr_t addr; uvm_reg_data_t tmp; uvm_reg_data_t msk; int lsb; this.fname = fname; this.lineno = lineno; if (this.mem == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot peek in from unimplemented virtual register \"%s\".", this.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_vreg.svh", 1145, "", 1); end status = UVM_NOT_OK; return; end addr = this.offset + (idx * this.incr); lsb = 0; value = 0; status = UVM_IS_OK; for (int i = 0; i < this.get_n_memlocs(); i++) begin uvm_status_e s; this.mem.peek(status, addr + i, tmp, "", parent, extension, fname, lineno); if (s != UVM_IS_OK && s != UVM_HAS_X) status = s; value |= tmp << lsb; lsb += this.mem.get_n_bytes() * 8; end begin if (uvm_report_enabled(UVM_MEDIUM,UVM_INFO,"RegModel")) uvm_report_info ("RegModel", $sformatf("Peeked virtual register \"%s\"[%0d]: 'h%h", this.get_full_name(), idx, value), UVM_MEDIUM, "t/uvm/src/reg/uvm_vreg.svh", 1166, "", 1); end this.fname = ""; this.lineno = 0; endtask: peek function void uvm_vreg::do_print (uvm_printer printer); super.do_print(printer); printer.print_generic("initiator", parent.get_type_name(), -1, convert2string()); endfunction function string uvm_vreg::convert2string(); string res_str; string t_str; bit with_debug_info; $sformat(convert2string, "Virtual register %s -- ", this.get_full_name()); if (this.size == 0) $sformat(convert2string, "%sunimplemented", convert2string); else begin uvm_reg_map maps[$]; mem.get_maps(maps); $sformat(convert2string, "%s[%0d] in %0s['h%0h+'h%0h]\n", convert2string, this.size, this.mem.get_full_name(), this.offset, this.incr); foreach (maps[i]) begin uvm_reg_addr_t addr0 = this.get_address(0, maps[i]); $sformat(convert2string, " Address in map '%s' -- @'h%0h+%0h", maps[i].get_full_name(), addr0, this.get_address(1, maps[i]) - addr0); end end foreach(this.fields[i]) begin $sformat(convert2string, "%s\n%s", convert2string, this.fields[i].convert2string()); end endfunction: convert2string function uvm_object uvm_vreg::clone(); return null; endfunction function void uvm_vreg::do_copy (uvm_object rhs); endfunction function bit uvm_vreg::do_compare (uvm_object rhs, uvm_comparer comparer); return 0; endfunction function void uvm_vreg::do_pack (uvm_packer packer); endfunction function void uvm_vreg::do_unpack (uvm_packer packer); endfunction class uvm_mem extends uvm_object; typedef enum {UNKNOWNS, ZEROES, ONES, ADDRESS, VALUE, INCR, DECR} init_e; local bit m_locked; local bit m_read_in_progress; local bit m_write_in_progress; local string m_access; local longint unsigned m_size; local uvm_reg_block m_parent; local bit m_maps[uvm_reg_map]; local int unsigned m_n_bits; local uvm_reg_backdoor m_backdoor; local bit m_is_powered_down; local int m_has_cover; local int m_cover_on; local string m_fname; local int m_lineno; local bit m_vregs[uvm_vreg]; local uvm_object_string_pool #(uvm_queue #(uvm_hdl_path_concat)) m_hdl_paths_pool; local static int unsigned m_max_size; extern function new (string name, longint unsigned size, int unsigned n_bits, string access = "RW", int has_coverage = UVM_NO_COVERAGE); extern function void configure (uvm_reg_block parent, string hdl_path = ""); extern virtual function void set_offset (uvm_reg_map map, uvm_reg_addr_t offset, bit unmapped = 0); extern virtual function void set_parent(uvm_reg_block parent); extern function void add_map(uvm_reg_map map); extern function void Xlock_modelX(); extern function void Xadd_vregX(uvm_vreg vreg); extern function void Xdelete_vregX(uvm_vreg vreg); uvm_mem_mam mam; extern virtual function string get_full_name(); extern virtual function uvm_reg_block get_parent (); extern virtual function uvm_reg_block get_block (); extern virtual function int get_n_maps (); extern function bit is_in_map (uvm_reg_map map); extern virtual function void get_maps (ref uvm_reg_map maps[$]); extern function uvm_reg_map get_local_map (uvm_reg_map map); extern function uvm_reg_map get_default_map (); extern virtual function string get_rights (uvm_reg_map map = null); extern virtual function string get_access(uvm_reg_map map = null); extern function longint unsigned get_size(); extern function int unsigned get_n_bytes(); extern function int unsigned get_n_bits(); extern static function int unsigned get_max_size(); extern virtual function void get_virtual_registers(ref uvm_vreg regs[$]); extern virtual function void get_virtual_fields(ref uvm_vreg_field fields[$]); extern virtual function uvm_vreg get_vreg_by_name(string name); extern virtual function uvm_vreg_field get_vfield_by_name(string name); extern virtual function uvm_vreg get_vreg_by_offset(uvm_reg_addr_t offset, uvm_reg_map map = null); extern virtual function uvm_reg_addr_t get_offset (uvm_reg_addr_t offset = 0, uvm_reg_map map = null); extern virtual function uvm_reg_addr_t get_address(uvm_reg_addr_t offset = 0, uvm_reg_map map = null); extern virtual function int get_addresses(uvm_reg_addr_t offset = 0, uvm_reg_map map=null, ref uvm_reg_addr_t addr[]); extern virtual task write(output uvm_status_e status, input uvm_reg_addr_t offset, input uvm_reg_data_t value, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); extern virtual task read(output uvm_status_e status, input uvm_reg_addr_t offset, output uvm_reg_data_t value, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); extern virtual task burst_write(output uvm_status_e status, input uvm_reg_addr_t offset, input uvm_reg_data_t value[], input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); extern virtual task burst_read(output uvm_status_e status, input uvm_reg_addr_t offset, ref uvm_reg_data_t value[], input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); extern virtual task poke(output uvm_status_e status, input uvm_reg_addr_t offset, input uvm_reg_data_t value, input string kind = "", input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); extern virtual task peek(output uvm_status_e status, input uvm_reg_addr_t offset, output uvm_reg_data_t value, input string kind = "", input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); extern protected function bit Xcheck_accessX (input uvm_reg_item rw, output uvm_reg_map_info map_info); extern virtual task do_write (uvm_reg_item rw); extern virtual task do_read (uvm_reg_item rw); extern function void set_frontdoor(uvm_reg_frontdoor ftdr, uvm_reg_map map = null, string fname = "", int lineno = 0); extern function uvm_reg_frontdoor get_frontdoor(uvm_reg_map map = null); extern function void set_backdoor (uvm_reg_backdoor bkdr, string fname = "", int lineno = 0); extern function uvm_reg_backdoor get_backdoor(bit inherited = 1); extern function void clear_hdl_path (string kind = "RTL"); extern function void add_hdl_path (uvm_hdl_path_slice slices[], string kind = "RTL"); extern function void add_hdl_path_slice(string name, int offset, int size, bit first = 0, string kind = "RTL"); extern function bit has_hdl_path (string kind = ""); extern function void get_hdl_path (ref uvm_hdl_path_concat paths[$], input string kind = ""); extern function void get_full_hdl_path (ref uvm_hdl_path_concat paths[$], input string kind = "", input string separator = "."); extern function void get_hdl_path_kinds (ref string kinds[$]); extern virtual protected task backdoor_read(uvm_reg_item rw); extern virtual task backdoor_write(uvm_reg_item rw); extern virtual function uvm_status_e backdoor_read_func(uvm_reg_item rw); static local bit m_register_cb_uvm_reg_cbs = uvm_callbacks#(uvm_mem,uvm_reg_cbs)::m_register_pair("uvm_mem","uvm_reg_cbs"); virtual task pre_write(uvm_reg_item rw); endtask virtual task post_write(uvm_reg_item rw); endtask virtual task pre_read(uvm_reg_item rw); endtask virtual task post_read(uvm_reg_item rw); endtask extern protected function uvm_reg_cvr_t build_coverage(uvm_reg_cvr_t models); extern virtual protected function void add_coverage(uvm_reg_cvr_t models); extern virtual function bit has_coverage(uvm_reg_cvr_t models); extern virtual function uvm_reg_cvr_t set_coverage(uvm_reg_cvr_t is_on); extern virtual function bit get_coverage(uvm_reg_cvr_t is_on); protected virtual function void sample(uvm_reg_addr_t offset, bit is_read, uvm_reg_map map); endfunction function void XsampleX(uvm_reg_addr_t addr, bit is_read, uvm_reg_map map); sample(addr, is_read, map); endfunction extern virtual function void do_print (uvm_printer printer); extern virtual function string convert2string(); extern virtual function uvm_object clone(); extern virtual function void do_copy (uvm_object rhs); extern virtual function bit do_compare (uvm_object rhs, uvm_comparer comparer); extern virtual function void do_pack (uvm_packer packer); extern virtual function void do_unpack (uvm_packer packer); endclass: uvm_mem function uvm_mem::new (string name, longint unsigned size, int unsigned n_bits, string access = "RW", int has_coverage = UVM_NO_COVERAGE); super.new(name); m_locked = 0; if (n_bits == 0) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Memory '",get_full_name(),"' cannot have 0 bits"}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 537, "", 1); end n_bits = 1; end m_size = size; m_n_bits = n_bits; m_backdoor = null; m_access = access.toupper(); m_has_cover = has_coverage; m_hdl_paths_pool = new("hdl_paths"); if (n_bits > m_max_size) m_max_size = n_bits; endfunction: new function void uvm_mem::configure(uvm_reg_block parent, string hdl_path=""); if (parent == null) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"REG/NULL_PARENT")) uvm_report_fatal ("REG/NULL_PARENT", "configure: parent argument is null", UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 559, "", 1); end m_parent = parent; if (m_access != "RW" && m_access != "RO") begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Memory '",get_full_name(),"' can only be RW or RO"}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 564, "", 1); end m_access = "RW"; end begin uvm_mem_mam_cfg cfg = new; cfg.n_bytes = ((m_n_bits-1) / 8) + 1; cfg.start_offset = 0; cfg.end_offset = m_size-1; cfg.mode = uvm_mem_mam::GREEDY; cfg.locality = uvm_mem_mam::BROAD; mam = new(get_full_name(), cfg, this); end m_parent.add_mem(this); if (hdl_path != "") add_hdl_path_slice(hdl_path, -1, -1); endfunction: configure function void uvm_mem::set_offset (uvm_reg_map map, uvm_reg_addr_t offset, bit unmapped = 0); uvm_reg_map orig_map = map; if (m_maps.num() > 1 && map == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"set_offset requires a non-null map when memory '", get_full_name(),"' belongs to more than one map."}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 597, "", 1); end return; end map = get_local_map(map); if (map == null) return; map.m_set_mem_offset(this, offset, unmapped); endfunction function void uvm_mem::add_map(uvm_reg_map map); m_maps[map] = 1; endfunction function void uvm_mem::Xlock_modelX(); m_locked = 1; endfunction: Xlock_modelX function string uvm_mem::get_full_name(); if (m_parent == null) return get_name(); return {m_parent.get_full_name(), ".", get_name()}; endfunction: get_full_name function uvm_reg_block uvm_mem::get_block(); return m_parent; endfunction: get_block function int uvm_mem::get_n_maps(); return m_maps.num(); endfunction: get_n_maps function void uvm_mem::get_maps(ref uvm_reg_map maps[$]); foreach (m_maps[map]) maps.push_back(map); endfunction function bit uvm_mem::is_in_map(uvm_reg_map map); if (m_maps.exists(map)) return 1; foreach (m_maps[l]) begin uvm_reg_map local_map=l; uvm_reg_map parent_map = local_map.get_parent_map(); while (parent_map != null) begin if (parent_map == map) return 1; parent_map = parent_map.get_parent_map(); end end return 0; endfunction function uvm_reg_map uvm_mem::get_local_map(uvm_reg_map map); if (map == null) return get_default_map(); if (m_maps.exists(map)) return map; foreach (m_maps[l]) begin uvm_reg_map local_map = l; uvm_reg_map parent_map = local_map.get_parent_map(); while (parent_map != null) begin if (parent_map == map) return local_map; parent_map = parent_map.get_parent_map(); end end begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Memory '",get_full_name(),"' is not contained within map '",map.get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 694, "", 1); end return null; endfunction function uvm_reg_map uvm_mem::get_default_map(); if (m_maps.num() == 0) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Memory '",get_full_name(),"' is not registered with any map"}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 706, "", 1); end return null; end if (m_maps.num() == 1) begin void'(m_maps.first(get_default_map)); end foreach (m_maps[l]) begin uvm_reg_map map = l; uvm_reg_block blk = map.get_parent(); uvm_reg_map default_map = blk.get_default_map(); if (default_map != null) begin uvm_reg_map local_map = get_local_map(default_map); if (local_map != null) return local_map; end end void'(m_maps.first(get_default_map)); endfunction function string uvm_mem::get_access(uvm_reg_map map = null); get_access = m_access; if (get_n_maps() == 1) return get_access; map = get_local_map(map); if (map == null) return get_access; case (get_rights(map)) "RW": return get_access; "RO": case (get_access) "RW", "RO": get_access = "RO"; "WO": begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"WO memory '",get_full_name(), "' restricted to RO in map '",map.get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 754, "", 1); end default: begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Memory '",get_full_name(), "' has invalid access mode, '",get_access,"'"}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 757, "", 1); end endcase "WO": case (get_access) "RW", "WO": get_access = "WO"; "RO": begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"RO memory '",get_full_name(), "' restricted to WO in map '",map.get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 765, "", 1); end default: begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Memory '",get_full_name(), "' has invalid access mode, '",get_access,"'"}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 768, "", 1); end endcase default: begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Shared memory '",get_full_name(), "' is not shared in map '",map.get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 772, "", 1); end endcase endfunction: get_access function string uvm_mem::get_rights(uvm_reg_map map = null); uvm_reg_map_info info; if (m_maps.num() <= 1) begin return "RW"; end map = get_local_map(map); if (map == null) return "RW"; info = map.get_mem_map_info(this); return info.rights; endfunction: get_rights function uvm_reg_addr_t uvm_mem::get_offset(uvm_reg_addr_t offset = 0, uvm_reg_map map = null); uvm_reg_map_info map_info; uvm_reg_map orig_map = map; map = get_local_map(map); if (map == null) return -1; map_info = map.get_mem_map_info(this); if (map_info.unmapped) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Memory '",get_name(), "' is unmapped in map '", ((orig_map == null) ? map.get_full_name() : orig_map.get_full_name()),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 817, "", 1); end return -1; end return map_info.offset; endfunction: get_offset function void uvm_mem::get_virtual_registers(ref uvm_vreg regs[$]); foreach (m_vregs[vreg]) regs.push_back(vreg); endfunction function void uvm_mem::get_virtual_fields(ref uvm_vreg_field fields[$]); foreach (m_vregs[l]) begin uvm_vreg vreg = l; vreg.get_fields(fields); end endfunction: get_virtual_fields function uvm_vreg_field uvm_mem::get_vfield_by_name(string name); uvm_vreg_field vfields[$]; get_virtual_fields(vfields); foreach (vfields[i]) if (vfields[i].get_name() == name) return vfields[i]; begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Unable to find virtual field '",name, "' in memory '",get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 860, "", 1); end return null; endfunction: get_vfield_by_name function uvm_vreg uvm_mem::get_vreg_by_name(string name); foreach (m_vregs[l]) begin uvm_vreg vreg = l; if (vreg.get_name() == name) return vreg; end begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Unable to find virtual register '",name, "' in memory '",get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 877, "", 1); end return null; endfunction: get_vreg_by_name function uvm_vreg uvm_mem::get_vreg_by_offset(uvm_reg_addr_t offset, uvm_reg_map map = null); begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", "uvm_mem::get_vreg_by_offset() not yet implemented", UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 887, "", 1); end return null; endfunction: get_vreg_by_offset function int uvm_mem::get_addresses(uvm_reg_addr_t offset = 0, uvm_reg_map map=null, ref uvm_reg_addr_t addr[]); uvm_reg_map_info map_info; uvm_reg_map system_map; uvm_reg_map orig_map = map; map = get_local_map(map); if (map == null) return 0; map_info = map.get_mem_map_info(this); if (map_info.unmapped) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Memory '",get_name(), "' is unmapped in map '", ((orig_map == null) ? map.get_full_name() : orig_map.get_full_name()),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 913, "", 1); end return 0; end addr = map_info.addr; foreach (addr[i]) addr[i] = addr[i] + map_info.mem_range.stride * offset; return map.get_n_bytes(); endfunction function uvm_reg_addr_t uvm_mem::get_address(uvm_reg_addr_t offset = 0, uvm_reg_map map = null); uvm_reg_addr_t addr[]; void'(get_addresses(offset, map, addr)); return addr[0]; endfunction function longint unsigned uvm_mem::get_size(); return m_size; endfunction: get_size function int unsigned uvm_mem::get_n_bits(); return m_n_bits; endfunction: get_n_bits function int unsigned uvm_mem::get_max_size(); return m_max_size; endfunction: get_max_size function int unsigned uvm_mem::get_n_bytes(); return (m_n_bits - 1) / 8 + 1; endfunction: get_n_bytes function uvm_reg_cvr_t uvm_mem::build_coverage(uvm_reg_cvr_t models); build_coverage = UVM_NO_COVERAGE; void'(uvm_reg_cvr_rsrc_db::read_by_name({"uvm_reg::", get_full_name()}, "include_coverage", build_coverage, this)); return build_coverage & models; endfunction: build_coverage function void uvm_mem::add_coverage(uvm_reg_cvr_t models); m_has_cover |= models; endfunction: add_coverage function bit uvm_mem::has_coverage(uvm_reg_cvr_t models); return ((m_has_cover & models) == models); endfunction: has_coverage function uvm_reg_cvr_t uvm_mem::set_coverage(uvm_reg_cvr_t is_on); if (is_on == uvm_reg_cvr_t'(UVM_NO_COVERAGE)) begin m_cover_on = is_on; return m_cover_on; end m_cover_on = m_has_cover & is_on; return m_cover_on; endfunction: set_coverage function bit uvm_mem::get_coverage(uvm_reg_cvr_t is_on); if (has_coverage(is_on) == 0) return 0; return ((m_cover_on & is_on) == is_on); endfunction: get_coverage task uvm_mem::write(output uvm_status_e status, input uvm_reg_addr_t offset, input uvm_reg_data_t value, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_reg_item rw = uvm_reg_item::type_id::create("mem_write",,get_full_name()); rw.element = this; rw.element_kind = UVM_MEM; rw.kind = UVM_WRITE; rw.offset = offset; rw.value[0] = value; rw.path = path; rw.map = map; rw.parent = parent; rw.prior = prior; rw.extension = extension; rw.fname = fname; rw.lineno = lineno; do_write(rw); status = rw.status; endtask: write task uvm_mem::read(output uvm_status_e status, input uvm_reg_addr_t offset, output uvm_reg_data_t value, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_reg_item rw; rw = uvm_reg_item::type_id::create("mem_read",,get_full_name()); rw.element = this; rw.element_kind = UVM_MEM; rw.kind = UVM_READ; rw.value[0] = 0; rw.offset = offset; rw.path = path; rw.map = map; rw.parent = parent; rw.prior = prior; rw.extension = extension; rw.fname = fname; rw.lineno = lineno; do_read(rw); status = rw.status; value = rw.value[0]; endtask: read task uvm_mem::burst_write(output uvm_status_e status, input uvm_reg_addr_t offset, input uvm_reg_data_t value[], input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_reg_item rw; rw = uvm_reg_item::type_id::create("mem_burst_write",,get_full_name()); rw.element = this; rw.element_kind = UVM_MEM; rw.kind = UVM_BURST_WRITE; rw.offset = offset; rw.value = value; rw.path = path; rw.map = map; rw.parent = parent; rw.prior = prior; rw.extension = extension; rw.fname = fname; rw.lineno = lineno; do_write(rw); status = rw.status; endtask: burst_write task uvm_mem::burst_read(output uvm_status_e status, input uvm_reg_addr_t offset, ref uvm_reg_data_t value[], input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_reg_item rw; rw = uvm_reg_item::type_id::create("mem_burst_read",,get_full_name()); rw.element = this; rw.element_kind = UVM_MEM; rw.kind = UVM_BURST_READ; rw.offset = offset; rw.value = value; rw.path = path; rw.map = map; rw.parent = parent; rw.prior = prior; rw.extension = extension; rw.fname = fname; rw.lineno = lineno; do_read(rw); status = rw.status; value = rw.value; endtask: burst_read task uvm_mem::do_write(uvm_reg_item rw); uvm_mem_cb_iter cbs = new(this); uvm_reg_map_info map_info; m_fname = rw.fname; m_lineno = rw.lineno; if (!Xcheck_accessX(rw, map_info)) return; m_write_in_progress = 1'b1; rw.status = UVM_IS_OK; pre_write(rw); for (uvm_reg_cbs cb=cbs.first(); cb!=null; cb=cbs.next()) cb.pre_write(rw); if (rw.status != UVM_IS_OK) begin m_write_in_progress = 1'b0; return; end rw.status = UVM_NOT_OK; if (rw.path == UVM_FRONTDOOR) begin uvm_reg_map system_map = rw.local_map.get_root_map(); if (map_info.frontdoor != null) begin uvm_reg_frontdoor fd = map_info.frontdoor; fd.rw_info = rw; if (fd.sequencer == null) fd.sequencer = system_map.get_sequencer(); fd.start(fd.sequencer, rw.parent); end else begin rw.local_map.do_write(rw); end if (rw.status != UVM_NOT_OK) for (uvm_reg_addr_t idx = rw.offset; idx <= rw.offset + rw.value.size(); idx++) begin XsampleX(map_info.mem_range.stride * idx, 0, rw.map); m_parent.XsampleX(map_info.offset + (map_info.mem_range.stride * idx), 0, rw.map); end end else begin if (get_access(rw.map) inside {"RW", "WO"}) begin uvm_reg_backdoor bkdr = get_backdoor(); if (bkdr != null) bkdr.write(rw); else backdoor_write(rw); end else rw.status = UVM_NOT_OK; end post_write(rw); for (uvm_reg_cbs cb=cbs.first(); cb!=null; cb=cbs.next()) cb.post_write(rw); if (uvm_report_enabled(UVM_HIGH, UVM_INFO, "RegModel")) begin string path_s,value_s,pre_s,range_s; if (rw.path == UVM_FRONTDOOR) path_s = (map_info.frontdoor != null) ? "user frontdoor" : {"map ",rw.map.get_full_name()}; else path_s = (get_backdoor() != null) ? "user backdoor" : "DPI backdoor"; if (rw.value.size() > 1) begin value_s = "='{"; pre_s = "Burst "; foreach (rw.value[i]) value_s = {value_s,$sformatf("%0h,",rw.value[i])}; value_s[value_s.len()-1]="}"; range_s = $sformatf("[%0d:%0d]",rw.offset,rw.offset+rw.value.size()); end else begin value_s = $sformatf("=%0h",rw.value[0]); range_s = $sformatf("[%0d]",rw.offset); end begin if (uvm_report_enabled(UVM_HIGH,UVM_INFO,"RegModel")) uvm_report_info ("RegModel", {pre_s,"Wrote memory via ",path_s,": ", get_full_name(),range_s,value_s}, UVM_HIGH, "t/uvm/src/reg/uvm_mem.svh", 1265, "", 1); end end m_write_in_progress = 1'b0; endtask: do_write task uvm_mem::do_read(uvm_reg_item rw); uvm_mem_cb_iter cbs = new(this); uvm_reg_map_info map_info; m_fname = rw.fname; m_lineno = rw.lineno; if (!Xcheck_accessX(rw, map_info)) return; m_read_in_progress = 1'b1; rw.status = UVM_IS_OK; pre_read(rw); for (uvm_reg_cbs cb=cbs.first(); cb!=null; cb=cbs.next()) cb.pre_read(rw); if (rw.status != UVM_IS_OK) begin m_read_in_progress = 1'b0; return; end rw.status = UVM_NOT_OK; if (rw.path == UVM_FRONTDOOR) begin uvm_reg_map system_map = rw.local_map.get_root_map(); if (map_info.frontdoor != null) begin uvm_reg_frontdoor fd = map_info.frontdoor; fd.rw_info = rw; if (fd.sequencer == null) fd.sequencer = system_map.get_sequencer(); fd.start(fd.sequencer, rw.parent); end else begin rw.local_map.do_read(rw); end if (rw.status != UVM_NOT_OK) for (uvm_reg_addr_t idx = rw.offset; idx <= rw.offset + rw.value.size(); idx++) begin XsampleX(map_info.mem_range.stride * idx, 1, rw.map); m_parent.XsampleX(map_info.offset + (map_info.mem_range.stride * idx), 1, rw.map); end end else begin if (get_access(rw.map) inside {"RW", "RO"}) begin uvm_reg_backdoor bkdr = get_backdoor(); if (bkdr != null) bkdr.read(rw); else backdoor_read(rw); end else rw.status = UVM_NOT_OK; end post_read(rw); for (uvm_reg_cbs cb=cbs.first(); cb!=null; cb=cbs.next()) cb.post_read(rw); if (uvm_report_enabled(UVM_HIGH, UVM_INFO, "RegModel")) begin string path_s,value_s,pre_s,range_s; if (rw.path == UVM_FRONTDOOR) path_s = (map_info.frontdoor != null) ? "user frontdoor" : {"map ",rw.map.get_full_name()}; else path_s = (get_backdoor() != null) ? "user backdoor" : "DPI backdoor"; if (rw.value.size() > 1) begin value_s = "='{"; pre_s = "Burst "; foreach (rw.value[i]) value_s = {value_s,$sformatf("%0h,",rw.value[i])}; value_s[value_s.len()-1]="}"; range_s = $sformatf("[%0d:%0d]",rw.offset,(rw.offset+rw.value.size())); end else begin value_s = $sformatf("=%0h",rw.value[0]); range_s = $sformatf("[%0d]",rw.offset); end begin if (uvm_report_enabled(UVM_HIGH,UVM_INFO,"RegModel")) uvm_report_info ("RegModel", {pre_s,"Read memory via ",path_s,": ", get_full_name(),range_s,value_s}, UVM_HIGH, "t/uvm/src/reg/uvm_mem.svh", 1373, "", 1); end end m_read_in_progress = 1'b0; endtask: do_read function bit uvm_mem::Xcheck_accessX(input uvm_reg_item rw, output uvm_reg_map_info map_info); if (rw.offset >= m_size) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,get_type_name())) uvm_report_error (get_type_name(), $sformatf("Offset 'h%0h exceeds size of memory, 'h%0h", rw.offset, m_size), UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 1389, "", 1); end rw.status = UVM_NOT_OK; return 0; end if (rw.path == UVM_DEFAULT_DOOR) rw.path = m_parent.get_default_door(); if (rw.path == UVM_BACKDOOR) begin if (get_backdoor() == null && !has_hdl_path()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"No backdoor access available for memory '",get_full_name(), "' . Using frontdoor instead."}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 1401, "", 1); end rw.path = UVM_FRONTDOOR; end else if (rw.map == null) begin if (get_default_map() != null) rw.map = get_default_map(); else rw.map = uvm_reg_map::backdoor(); end end if (rw.path != UVM_BACKDOOR) begin rw.local_map = get_local_map(rw.map); if (rw.local_map == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,get_type_name())) uvm_report_error (get_type_name(), {"No transactor available to physically access memory from map '", rw.map.get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 1420, "", 1); end rw.status = UVM_NOT_OK; return 0; end map_info = rw.local_map.get_mem_map_info(this); if (map_info.frontdoor == null) begin if (map_info.unmapped) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Memory '",get_full_name(), "' unmapped in map '", rw.map.get_full_name(), "' and does not have a user-defined frontdoor"}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 1432, "", 1); end rw.status = UVM_NOT_OK; return 0; end if ((rw.value.size() > 1)) begin if (get_n_bits() > rw.local_map.get_n_bytes()*8) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot burst a %0d-bit memory through a narrower data path (%0d bytes)", get_n_bits(), rw.local_map.get_n_bytes()*8), UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 1441, "", 1); end rw.status = UVM_NOT_OK; return 0; end if (rw.offset + rw.value.size() > m_size) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Burst of size 'd%0d starting at offset 'd%0d exceeds size of memory, 'd%0d", rw.value.size(), rw.offset, m_size), UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 1448, "", 1); end return 0; end end end if (rw.map == null) rw.map = rw.local_map; end return 1; endfunction task uvm_mem::poke(output uvm_status_e status, input uvm_reg_addr_t offset, input uvm_reg_data_t value, input string kind = "", input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_reg_item rw; uvm_reg_backdoor bkdr = get_backdoor(); m_fname = fname; m_lineno = lineno; if (bkdr == null && !has_hdl_path(kind)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"No backdoor access available in memory '", get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 1484, "", 1); end status = UVM_NOT_OK; return; end rw = uvm_reg_item::type_id::create("mem_poke_item",,get_full_name()); rw.element = this; rw.path = UVM_BACKDOOR; rw.element_kind = UVM_MEM; rw.kind = UVM_WRITE; rw.offset = offset; rw.value[0] = value & ((1 << m_n_bits)-1); rw.bd_kind = kind; rw.parent = parent; rw.extension = extension; rw.fname = fname; rw.lineno = lineno; if (bkdr != null) bkdr.write(rw); else backdoor_write(rw); status = rw.status; begin if (uvm_report_enabled(UVM_HIGH,UVM_INFO,"RegModel")) uvm_report_info ("RegModel", $sformatf("Poked memory '%s[%0d]' with value 'h%h", get_full_name(), offset, value), UVM_HIGH, "t/uvm/src/reg/uvm_mem.svh", 1511, "", 1); end endtask: poke task uvm_mem::peek(output uvm_status_e status, input uvm_reg_addr_t offset, output uvm_reg_data_t value, input string kind = "", input uvm_sequence_base parent = null, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_reg_backdoor bkdr = get_backdoor(); uvm_reg_item rw; m_fname = fname; m_lineno = lineno; if (bkdr == null && !has_hdl_path(kind)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"No backdoor access available in memory '", get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 1534, "", 1); end status = UVM_NOT_OK; return; end rw = uvm_reg_item::type_id::create("mem_peek_item",,get_full_name()); rw.element = this; rw.path = UVM_BACKDOOR; rw.element_kind = UVM_MEM; rw.kind = UVM_READ; rw.offset = offset; rw.bd_kind = kind; rw.parent = parent; rw.extension = extension; rw.fname = fname; rw.lineno = lineno; if (bkdr != null) bkdr.read(rw); else backdoor_read(rw); status = rw.status; value = rw.value[0]; begin if (uvm_report_enabled(UVM_HIGH,UVM_INFO,"RegModel")) uvm_report_info ("RegModel", $sformatf("Peeked memory '%s[%0d]' has value 'h%h", get_full_name(), offset, value), UVM_HIGH, "t/uvm/src/reg/uvm_mem.svh", 1561, "", 1); end endtask: peek function void uvm_mem::set_frontdoor(uvm_reg_frontdoor ftdr, uvm_reg_map map = null, string fname = "", int lineno = 0); uvm_reg_map_info map_info; m_fname = fname; m_lineno = lineno; map = get_local_map(map); if (map == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Memory '",get_full_name(), "' not found in map '", map.get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 1583, "", 1); end return; end map_info = map.get_mem_map_info(this); map_info.frontdoor = ftdr; endfunction: set_frontdoor function uvm_reg_frontdoor uvm_mem::get_frontdoor(uvm_reg_map map = null); uvm_reg_map_info map_info; map = get_local_map(map); if (map == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Memory '",get_full_name(), "' not found in map '", map.get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 1602, "", 1); end return null; end map_info = map.get_mem_map_info(this); return map_info.frontdoor; endfunction: get_frontdoor function void uvm_mem::set_backdoor(uvm_reg_backdoor bkdr, string fname = "", int lineno = 0); m_fname = fname; m_lineno = lineno; m_backdoor = bkdr; endfunction: set_backdoor function uvm_reg_backdoor uvm_mem::get_backdoor(bit inherited = 1); if (m_backdoor == null && inherited) begin uvm_reg_block blk = get_parent(); uvm_reg_backdoor bkdr; while (blk != null) begin bkdr = blk.get_backdoor(); if (bkdr != null) begin m_backdoor = bkdr; break; end blk = blk.get_parent(); end end return m_backdoor; endfunction: get_backdoor function uvm_status_e uvm_mem::backdoor_read_func(uvm_reg_item rw); uvm_hdl_path_concat paths[$]; uvm_hdl_data_t val; bit ok=1; get_full_hdl_path(paths,rw.bd_kind); foreach (rw.value[mem_idx]) begin string idx; idx.itoa(rw.offset + mem_idx); foreach (paths[i]) begin uvm_hdl_path_concat hdl_concat = paths[i]; val = 0; foreach (hdl_concat.slices[j]) begin string hdl_path = {hdl_concat.slices[j].path, "[", idx, "]"}; begin if (uvm_report_enabled(UVM_DEBUG,UVM_INFO,"RegModel")) uvm_report_info ("RegModel", {"backdoor_read from ",hdl_path}, UVM_DEBUG, "t/uvm/src/reg/uvm_mem.svh", 1667, "", 1); end if (hdl_concat.slices[j].offset < 0) begin ok &= uvm_hdl_read(hdl_path, val); continue; end begin uvm_reg_data_t slice; int k = hdl_concat.slices[j].offset; ok &= uvm_hdl_read(hdl_path, slice); repeat (hdl_concat.slices[j].size) begin val[k++] = slice[0]; slice >>= 1; end end end val &= (1 << m_n_bits)-1; if (i == 0) rw.value[mem_idx] = val; if (val != rw.value[mem_idx]) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Backdoor read of register %s with multiple HDL copies: values are not the same: %0h at path '%s', and %0h at path '%s'. Returning first value.", get_full_name(), rw.value[mem_idx], uvm_hdl_concat2string(paths[0]), val, uvm_hdl_concat2string(paths[i])), UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 1692, "", 1); end return UVM_NOT_OK; end end end rw.status = (ok) ? UVM_IS_OK : UVM_NOT_OK; return rw.status; endfunction task uvm_mem::backdoor_read(uvm_reg_item rw); rw.status = backdoor_read_func(rw); endtask task uvm_mem::backdoor_write(uvm_reg_item rw); uvm_hdl_path_concat paths[$]; bit ok=1; get_full_hdl_path(paths,rw.bd_kind); foreach (rw.value[mem_idx]) begin string idx; idx.itoa(rw.offset + mem_idx); foreach (paths[i]) begin uvm_hdl_path_concat hdl_concat = paths[i]; foreach (hdl_concat.slices[j]) begin begin if (uvm_report_enabled(UVM_DEBUG,UVM_INFO,"RegModel")) uvm_report_info ("RegModel", $sformatf("backdoor_write to %s ",hdl_concat.slices[j].path), UVM_DEBUG, "t/uvm/src/reg/uvm_mem.svh", 1727, "", 1); end if (hdl_concat.slices[j].offset < 0) begin ok &= uvm_hdl_deposit({hdl_concat.slices[j].path,"[", idx, "]"},rw.value[mem_idx]); continue; end begin uvm_reg_data_t slice; slice = rw.value[mem_idx] >> hdl_concat.slices[j].offset; slice &= (1 << hdl_concat.slices[j].size)-1; ok &= uvm_hdl_deposit({hdl_concat.slices[j].path, "[", idx, "]"}, slice); end end end end rw.status = (ok ? UVM_IS_OK : UVM_NOT_OK); endtask function void uvm_mem::clear_hdl_path(string kind = "RTL"); if (kind == "ALL") begin m_hdl_paths_pool = new("hdl_paths"); return; end if (kind == "") kind = m_parent.get_default_hdl_path(); if (!m_hdl_paths_pool.exists(kind)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Unknown HDL Abstraction '",kind,"'"}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 1760, "", 1); end return; end m_hdl_paths_pool.delete(kind); endfunction function void uvm_mem::add_hdl_path(uvm_hdl_path_slice slices[], string kind = "RTL"); uvm_queue #(uvm_hdl_path_concat) paths = m_hdl_paths_pool.get(kind); uvm_hdl_path_concat concat = new(); concat.set(slices); paths.push_back(concat); endfunction function void uvm_mem::add_hdl_path_slice(string name, int offset, int size, bit first = 0, string kind = "RTL"); uvm_queue #(uvm_hdl_path_concat) paths=m_hdl_paths_pool.get(kind); uvm_hdl_path_concat concat; if (first || paths.size() == 0) begin concat = new(); paths.push_back(concat); end else concat = paths.get(paths.size()-1); concat.add_path(name, offset, size); endfunction function bit uvm_mem::has_hdl_path(string kind = ""); if (kind == "") kind = m_parent.get_default_hdl_path(); return m_hdl_paths_pool.exists(kind); endfunction function void uvm_mem::get_hdl_path(ref uvm_hdl_path_concat paths[$], input string kind = ""); uvm_queue #(uvm_hdl_path_concat) hdl_paths; if (kind == "") kind = m_parent.get_default_hdl_path(); if (!has_hdl_path(kind)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Memory does not have hdl path defined for abstraction '",kind,"'"}, UVM_NONE, "t/uvm/src/reg/uvm_mem.svh", 1822, "", 1); end return; end hdl_paths = m_hdl_paths_pool.get(kind); for (int i=0; i= range.min && addrs[i] <= range.max) begin string a; a = $sformatf("%0h",addrs[i]); begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"In map '",get_full_name(),"' register '", rg.get_full_name(), "' overlaps with address range of memory '", top_map.m_mems_by_offset[range].get_full_name(),"': 'h",a}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 716, "", 1); end end end end info.addr = addrs; end end if (unmapped) begin info.offset = -1; info.unmapped = 1; end else begin info.offset = offset; info.unmapped = 0; end end endfunction function void uvm_reg_map::add_mem(uvm_mem mem, uvm_reg_addr_t offset, string rights = "RW", bit unmapped=0, uvm_reg_frontdoor frontdoor=null); if (m_mems_info.exists(mem)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Memory '",mem.get_name(), "' has already been added to map '",get_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 746, "", 1); end return; end if (mem.get_parent() != get_parent()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Memory '",mem.get_full_name(),"' may not be added to address map '", get_full_name(),"' : they are not in the same block"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 753, "", 1); end return; end mem.add_map(this); begin uvm_reg_map_info info = new; info.offset = offset; info.rights = rights; info.unmapped = unmapped; info.frontdoor = frontdoor; m_mems_info[mem] = info; end endfunction: add_mem function void uvm_reg_map::m_set_mem_offset(uvm_mem mem, uvm_reg_addr_t offset, bit unmapped); if (!m_mems_info.exists(mem)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Cannot modify offset of memory '",mem.get_full_name(), "' in address map '",get_full_name(), "' : memory not mapped in that address map"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 781, "", 1); end return; end begin uvm_reg_map_info info = m_mems_info[mem]; uvm_reg_block blk = get_parent(); uvm_reg_map top_map = get_root_map(); uvm_reg_addr_t addrs[]; if (blk.is_locked()) begin if (!info.unmapped) begin foreach (top_map.m_mems_by_offset[range]) begin if (top_map.m_mems_by_offset[range] == mem) top_map.m_mems_by_offset.delete(range); end end if (!unmapped) begin uvm_reg_addr_t addrs[],addrs_max[]; uvm_reg_addr_t min, max, min2, max2; int unsigned stride; void'(get_physical_addresses(offset,0,mem.get_n_bytes(),addrs)); min = (addrs[0] < addrs[addrs.size()-1]) ? addrs[0] : addrs[addrs.size()-1]; min2 = addrs[0]; void'(get_physical_addresses(offset,(mem.get_size()-1), mem.get_n_bytes(),addrs_max)); max = (addrs_max[0] > addrs_max[addrs_max.size()-1]) ? addrs_max[0] : addrs_max[addrs_max.size()-1]; max2 = addrs_max[0]; stride = mem.get_n_bytes()/get_addr_unit_bytes(); foreach (top_map.m_regs_by_offset[reg_addr]) begin if (reg_addr >= min && reg_addr <= max) begin string a,b; a = $sformatf("[%0h:%0h]",min,max); b = $sformatf("%0h",reg_addr); begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"In map '",get_full_name(),"' memory '", mem.get_full_name(), "' with range ",a, " overlaps with address of existing register '", top_map.m_regs_by_offset[reg_addr].get_full_name(),"': 'h",b}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 829, "", 1); end end end foreach (top_map.m_mems_by_offset[range]) begin if (min <= range.max && max >= range.max || min <= range.min && max >= range.min || min >= range.min && max <= range.max) begin string a,b; a = $sformatf("[%0h:%0h]",min,max); b = $sformatf("[%0h:%0h]",range.min,range.max); begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"In map '",get_full_name(),"' memory '", mem.get_full_name(), "' with range ",a, " overlaps existing memory with range '", top_map.m_mems_by_offset[range].get_full_name(),"': ",b}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 843, "", 1); end end end begin uvm_reg_map_addr_range range = '{ min, max, stride}; top_map.m_mems_by_offset[range] = mem; info.addr = addrs; info.mem_range = range; end end end if (unmapped) begin info.offset = -1; info.unmapped = 1; end else begin info.offset = offset; info.unmapped = 0; end end endfunction function void uvm_reg_map::add_submap (uvm_reg_map child_map, uvm_reg_addr_t offset); uvm_reg_map parent_map; if (child_map == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Attempting to add NULL map to map '",get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 877, "", 1); end return; end parent_map = child_map.get_parent_map(); if (parent_map != null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Map '", child_map.get_full_name(), "' is already a child of map '", parent_map.get_full_name(), "'. Cannot also be a child of map '", get_full_name(), "'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 890, "", 1); end return; end begin : n_bytes_match_check if (m_n_bytes > child_map.get_n_bytes(UVM_NO_HIER)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", $sformatf("Adding %0d-byte submap '%s' to %0d-byte parent map '%s'", child_map.get_n_bytes(UVM_NO_HIER), child_map.get_full_name(), m_n_bytes, get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 900, "", 1); end end end child_map.add_parent_map(this,offset); set_submap_offset(child_map, offset); endfunction: add_submap function void uvm_reg_map::reset(string kind = "SOFT"); uvm_reg regs[$]; get_registers(regs); foreach (regs[i]) begin regs[i].reset(kind); end endfunction function void uvm_reg_map::add_parent_map(uvm_reg_map parent_map, uvm_reg_addr_t offset); if (parent_map == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Attempting to add NULL parent map to map '",get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 930, "", 1); end return; end if (m_parent_map != null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Map \"%s\" already a submap of map \"%s\" at offset 'h%h", get_full_name(), m_parent_map.get_full_name(), m_parent_map.get_submap_offset(this)), UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 938, "", 1); end return; end m_parent_map = parent_map; parent_map.m_submaps[this] = offset; endfunction: add_parent_map function void uvm_reg_map::set_sequencer(uvm_sequencer_base sequencer, uvm_reg_adapter adapter=null); if (sequencer == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"REG_NULL_SQR")) uvm_report_error ("REG_NULL_SQR", "Null reference specified for bus sequencer", UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 954, "", 1); end return; end if (adapter == null) begin begin if (uvm_report_enabled(UVM_MEDIUM,UVM_INFO,"REG_NO_ADAPT")) uvm_report_info ("REG_NO_ADAPT", {"Adapter not specified for map '",get_full_name(), "'. Accesses via this map will send abstract 'uvm_reg_item' items to sequencer '", sequencer.get_full_name(),"'"}, UVM_MEDIUM, "t/uvm/src/reg/uvm_reg_map.svh", 961, "", 1); end end m_sequencer = sequencer; m_adapter = adapter; endfunction function uvm_reg_block uvm_reg_map::get_parent(); return m_parent; endfunction function uvm_reg_map uvm_reg_map::get_parent_map(); return m_parent_map; endfunction function uvm_reg_map uvm_reg_map::get_root_map(); return (m_parent_map == null) ? this : m_parent_map.get_root_map(); endfunction: get_root_map function uvm_reg_addr_t uvm_reg_map::get_base_addr(uvm_hier_e hier=UVM_HIER); uvm_reg_map child = this; if (hier == UVM_NO_HIER || m_parent_map == null) return m_base_addr; get_base_addr = m_parent_map.get_submap_offset(this); get_base_addr += m_parent_map.get_base_addr(UVM_HIER); endfunction function int unsigned uvm_reg_map::get_n_bytes(uvm_hier_e hier=UVM_HIER); if (hier == UVM_NO_HIER) return m_n_bytes; return m_system_n_bytes; endfunction function int unsigned uvm_reg_map::get_addr_unit_bytes(); return (m_byte_addressing) ? 1 : m_n_bytes; endfunction function uvm_endianness_e uvm_reg_map::get_endian(uvm_hier_e hier=UVM_HIER); if (hier == UVM_NO_HIER || m_parent_map == null) return m_endian; return m_parent_map.get_endian(hier); endfunction function uvm_sequencer_base uvm_reg_map::get_sequencer(uvm_hier_e hier=UVM_HIER); if (hier == UVM_NO_HIER || m_parent_map == null) return m_sequencer; return m_parent_map.get_sequencer(hier); endfunction function uvm_reg_adapter uvm_reg_map::get_adapter(uvm_hier_e hier=UVM_HIER); if (hier == UVM_NO_HIER || m_parent_map == null) return m_adapter; return m_parent_map.get_adapter(hier); endfunction function void uvm_reg_map::get_submaps(ref uvm_reg_map maps[$], input uvm_hier_e hier=UVM_HIER); foreach (m_submaps[submap]) maps.push_back(submap); if (hier == UVM_HIER) foreach (m_submaps[submap_]) begin uvm_reg_map submap=submap_; submap.get_submaps(maps); end endfunction function void uvm_reg_map::get_registers(ref uvm_reg regs[$], input uvm_hier_e hier=UVM_HIER); foreach (m_regs_info[rg]) regs.push_back(rg); if (hier == UVM_HIER) foreach (m_submaps[submap_]) begin uvm_reg_map submap=submap_; submap.get_registers(regs); end endfunction function void uvm_reg_map::get_fields(ref uvm_reg_field fields[$], input uvm_hier_e hier=UVM_HIER); foreach (m_regs_info[rg_]) begin uvm_reg rg = rg_; rg.get_fields(fields); end if (hier == UVM_HIER) foreach (this.m_submaps[submap_]) begin uvm_reg_map submap=submap_; submap.get_fields(fields); end endfunction function void uvm_reg_map::get_memories(ref uvm_mem mems[$], input uvm_hier_e hier=UVM_HIER); foreach (m_mems_info[mem]) mems.push_back(mem); if (hier == UVM_HIER) foreach (m_submaps[submap_]) begin uvm_reg_map submap=submap_; submap.get_memories(mems); end endfunction function void uvm_reg_map::get_virtual_registers(ref uvm_vreg regs[$], input uvm_hier_e hier=UVM_HIER); uvm_mem mems[$]; get_memories(mems,hier); foreach (mems[i]) mems[i].get_virtual_registers(regs); endfunction function void uvm_reg_map::get_virtual_fields(ref uvm_vreg_field fields[$], input uvm_hier_e hier=UVM_HIER); uvm_vreg regs[$]; get_virtual_registers(regs,hier); foreach (regs[i]) regs[i].get_fields(fields); endfunction function string uvm_reg_map::get_full_name(); if (m_parent == null) return get_name(); else return {m_parent.get_full_name(), ".", get_name()}; endfunction function uvm_reg_map_info uvm_reg_map::get_mem_map_info(uvm_mem mem, bit error=1); if (!m_mems_info.exists(mem)) begin if (error) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"REG_NO_MAP")) uvm_report_error ("REG_NO_MAP", {"Memory '",mem.get_name(),"' not in map '",get_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1157, "", 1); end return null; end return m_mems_info[mem]; endfunction function uvm_reg_map_info uvm_reg_map::get_reg_map_info(uvm_reg rg, bit error=1); uvm_reg_map_info result; if (!m_regs_info.exists(rg)) begin if (error) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"REG_NO_MAP")) uvm_report_error ("REG_NO_MAP", {"Register '",rg.get_name(),"' not in map '",get_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1170, "", 1); end return null; end result = m_regs_info[rg]; if(!result.is_initialized) begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"map '",get_name(),"' does not seem to be initialized correctly, check that the top register model is locked()"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1175, "", 1); end return result; endfunction function void uvm_reg_map::set_base_addr(uvm_reg_addr_t offset); if (m_parent_map != null) begin m_parent_map.set_submap_offset(this, offset); end else begin m_base_addr = offset; if (m_parent.is_locked()) begin uvm_reg_map top_map = get_root_map(); top_map.Xinit_address_mapX(); end end endfunction function int unsigned uvm_reg_map::get_size(); int unsigned max_addr; int unsigned addr; foreach (m_regs_info[rg_]) begin uvm_reg rg = rg_; addr = m_regs_info[rg].offset + ((rg.get_n_bytes()-1)/m_n_bytes); if (addr > max_addr) max_addr = addr; end foreach (m_mems_info[mem_]) begin uvm_mem mem = mem_; addr = m_mems_info[mem].offset + (mem.get_size() * (((mem.get_n_bytes()-1)/m_n_bytes)+1)) -1; if (addr > max_addr) max_addr = addr; end foreach (m_submaps[submap_]) begin uvm_reg_map submap=submap_; addr = m_submaps[submap] + submap.get_size(); if (addr > max_addr) max_addr = addr; end return max_addr + 1; endfunction function void uvm_reg_map::Xverify_map_configX(); bit error; uvm_reg_map root_map = get_root_map(); if (root_map.get_adapter() == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Map '",root_map.get_full_name(), "' does not have an adapter registered"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1243, "", 1); end error++; end if (root_map.get_sequencer() == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Map '",root_map.get_full_name(), "' does not have a sequencer registered"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1248, "", 1); end error++; end if (error) begin begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"RegModel")) uvm_report_fatal ("RegModel", {"Must register an adapter and sequencer ", "for each top-level map in RegModel model"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1253, "", 1); end return; end endfunction function int uvm_reg_map::get_physical_addresses_to_map( uvm_reg_addr_t base_addr, uvm_reg_addr_t mem_offset, int unsigned n_bytes, ref uvm_reg_addr_t addr[], input uvm_reg_map parent_map, ref int unsigned byte_offset, input uvm_mem mem=null ); int bus_width = get_n_bytes(UVM_NO_HIER); uvm_reg_map up_map; uvm_reg_addr_t local_addr[]; uvm_reg_addr_t lbase_addr; up_map = get_parent_map(); lbase_addr = up_map==null ? get_base_addr(UVM_NO_HIER): up_map.get_submap_offset(this); if(up_map!=parent_map) begin uvm_reg_addr_t lb; uvm_reg_addr_t laddr; begin if(mem_offset) begin base_addr+=mem_offset*mem.get_n_bytes()/get_addr_unit_bytes(); end laddr=lbase_addr + base_addr*get_addr_unit_bytes()/up_map.get_addr_unit_bytes(); lb = (base_addr*get_addr_unit_bytes()) % up_map.get_addr_unit_bytes(); byte_offset += lb; end return up_map.get_physical_addresses_to_map(laddr, 0, n_bytes+lb, addr,parent_map,byte_offset); end else begin uvm_reg_addr_t lbase_addr2; local_addr= new[ceil(n_bytes,bus_width)]; lbase_addr2 = base_addr; if(mem_offset) if(mem!=null && (mem.get_n_bytes() >= get_addr_unit_bytes())) begin lbase_addr2 = base_addr + mem_offset*mem.get_n_bytes()/get_addr_unit_bytes(); byte_offset += (mem_offset*mem.get_n_bytes() % get_addr_unit_bytes()); end else begin lbase_addr2 = base_addr + mem_offset; end case (get_endian(UVM_NO_HIER)) UVM_LITTLE_ENDIAN: begin foreach (local_addr[i]) begin local_addr[i] = lbase_addr2 + i*bus_width/get_addr_unit_bytes(); end end UVM_BIG_ENDIAN: begin foreach (local_addr[i]) begin local_addr[i] = lbase_addr2 + (local_addr.size()-1-i)*bus_width/get_addr_unit_bytes() ; end end UVM_LITTLE_FIFO: begin foreach (local_addr[i]) begin local_addr[i] = lbase_addr2; end end UVM_BIG_FIFO: begin foreach (local_addr[i]) begin local_addr[i] = lbase_addr2; end end default: begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/REG/MAPNOENDIANESS")) uvm_report_error ("UVM/REG/MAPNOENDIANESS", {"Map has no specified endianness. ", $sformatf("Cannot access %0d bytes register via its %0d byte \"%s\" interface", n_bytes, bus_width, get_full_name())}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1347, "", 1); end end endcase addr = new [local_addr.size()] (local_addr); foreach(addr[idx]) addr[idx] += lbase_addr; end endfunction function int uvm_reg_map::get_physical_addresses(uvm_reg_addr_t base_addr, uvm_reg_addr_t mem_offset, int unsigned n_bytes, ref uvm_reg_addr_t addr[]); int unsigned skip; return get_physical_addresses_to_map(base_addr, mem_offset, n_bytes, addr,null,skip); endfunction function void uvm_reg_map::set_submap_offset(uvm_reg_map submap, uvm_reg_addr_t offset); if (submap == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"REG/NULL")) uvm_report_error ("REG/NULL", "set_submap_offset: submap handle is null", UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1385, "", 1); end return; end m_submaps[submap] = offset; if (m_parent.is_locked()) begin uvm_reg_map root_map = get_root_map(); root_map.Xinit_address_mapX(); end endfunction function uvm_reg_addr_t uvm_reg_map::get_submap_offset(uvm_reg_map submap); if (submap == null) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"REG/NULL")) uvm_report_error ("REG/NULL", "set_submap_offset: submap handle is null", UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1400, "", 1); end return -1; end if (!m_submaps.exists(submap)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Map '",submap.get_full_name(), "' is not a submap of '",get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1405, "", 1); end return -1; end return m_submaps[submap]; endfunction function uvm_reg uvm_reg_map::get_reg_by_offset(uvm_reg_addr_t offset, bit read = 1); if (!m_parent.is_locked()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot get register by offset: Block %s is not locked.", m_parent.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1417, "", 1); end return null; end if (!read && m_regs_by_offset_wo.exists(offset)) return m_regs_by_offset_wo[offset]; if (m_regs_by_offset.exists(offset)) return m_regs_by_offset[offset]; return null; endfunction function uvm_mem uvm_reg_map::get_mem_by_offset(uvm_reg_addr_t offset); if (!m_parent.is_locked()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Cannot memory register by offset: Block %s is not locked.", m_parent.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1435, "", 1); end return null; end foreach (m_mems_by_offset[range]) begin if (range.min <= offset && offset <= range.max) begin return m_mems_by_offset[range]; end end return null; endfunction function void uvm_reg_map::Xinit_address_mapX(); int unsigned bus_width; uvm_reg_map top_map = get_root_map(); if (this == top_map) begin top_map.m_regs_by_offset.delete(); top_map.m_regs_by_offset_wo.delete(); top_map.m_mems_by_offset.delete(); end foreach (m_submaps[l]) begin uvm_reg_map map=l; map.Xinit_address_mapX(); end foreach (m_regs_info[rg_]) begin uvm_reg rg = rg_; m_regs_info[rg].is_initialized=1; if (!m_regs_info[rg].unmapped) begin string rg_acc = rg.Xget_fields_accessX(this); uvm_reg_addr_t addrs[]; bus_width = get_physical_addresses(m_regs_info[rg].offset,0,rg.get_n_bytes(),addrs); foreach (addrs[i]) begin uvm_reg_addr_t addr = addrs[i]; if (top_map.m_regs_by_offset.exists(addr) && (top_map.m_regs_by_offset[addr] != rg)) begin uvm_reg rg2 = top_map.m_regs_by_offset[addr]; string rg2_acc = rg2.Xget_fields_accessX(this); if (rg_acc == "RO" && rg2_acc == "WO") begin top_map.m_regs_by_offset[addr] = rg; uvm_reg_read_only_cbs::add(rg); top_map.m_regs_by_offset_wo[addr] = rg2; uvm_reg_write_only_cbs::add(rg2); end else if (rg_acc == "WO" && rg2_acc == "RO") begin top_map.m_regs_by_offset_wo[addr] = rg; uvm_reg_write_only_cbs::add(rg); uvm_reg_read_only_cbs::add(rg2); end else begin string a; a = $sformatf("%0h",addr); begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"In map '",get_full_name(),"' register '", rg.get_full_name(), "' maps to same address as register '", top_map.m_regs_by_offset[addr].get_full_name(),"': 'h",a}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1503, "", 1); end end end else top_map.m_regs_by_offset[addr] = rg; foreach (top_map.m_mems_by_offset[range]) begin if (addr >= range.min && addr <= range.max) begin string a,b; a = $sformatf("%0h",addr); b = $sformatf("[%0h:%0h]",range.min,range.max); begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"In map '",get_full_name(),"' register '", rg.get_full_name(), "' with address ",a, "maps to same address as memory '", top_map.m_mems_by_offset[range].get_full_name(),"': ",b}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1517, "", 1); end end end end m_regs_info[rg].addr = addrs; end end foreach (m_mems_info[mem_]) begin uvm_mem mem = mem_; if (!m_mems_info[mem].unmapped) begin uvm_reg_addr_t addrs[],addrs_max[]; uvm_reg_addr_t min, max, min2, max2; int unsigned stride; int unsigned bo; bus_width = get_physical_addresses_to_map(m_mems_info[mem].offset,0,mem.get_n_bytes(),addrs,null,bo,mem); min = (addrs[0] < addrs[addrs.size()-1]) ? addrs[0] : addrs[addrs.size()-1]; void'(get_physical_addresses_to_map(m_mems_info[mem].offset,(mem.get_size()-1),mem.get_n_bytes(),addrs_max,null,bo,mem)); max = (addrs_max[0] > addrs_max[addrs_max.size()-1]) ? addrs_max[0] : addrs_max[addrs_max.size()-1]; stride = mem.get_n_bytes()/get_addr_unit_bytes(); if(mem.get_n_bytes() get_addr_unit_bytes()) if(mem.get_n_bytes() % get_addr_unit_bytes()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"UVM/REG/ADDR")) uvm_report_warning ("UVM/REG/ADDR", $sformatf("memory %s is not matching the word width of the enclosing map %s \ (one memory word not fitting into k map addresses)", mem.get_full_name(),get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1571, "", 1); end end if(mem.get_n_bytes() < get_addr_unit_bytes()) if(get_addr_unit_bytes() % mem.get_n_bytes()) begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"UVM/REG/ADDR")) uvm_report_warning ("UVM/REG/ADDR", $sformatf("the memory %s is not matching the word width of the enclosing map %s \ (one map address doesnt cover k memory words)", mem.get_full_name(),get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1578, "", 1); end if(mem.get_n_bits() % 8) begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"UVM/REG/ADDR")) uvm_report_warning ("UVM/REG/ADDR", $sformatf("this implementation of UVM requires memory words to be k*8 bits (mem %s \ has %0d bit words)",mem.get_full_name(),mem.get_n_bits()), UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1582, "", 1); end foreach (top_map.m_regs_by_offset[reg_addr]) begin if (reg_addr >= min && reg_addr <= max) begin string a; a = $sformatf("%0h",reg_addr); begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"In map '",get_full_name(),"' memory '", mem.get_full_name(), "' maps to same address as register '", top_map.m_regs_by_offset[reg_addr].get_full_name(),"': 'h",a}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1590, "", 1); end end end foreach (top_map.m_mems_by_offset[range]) begin if (min <= range.max && max >= range.max || min <= range.min && max >= range.min || min >= range.min && max <= range.max) if(top_map.m_mems_by_offset[range]!=mem) begin string a; a = $sformatf("[%0h:%0h]",min,max); begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"In map '",get_full_name(),"' memory '", mem.get_full_name(), "' overlaps with address range of memory '", top_map.m_mems_by_offset[range].get_full_name(),"': 'h",a}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1604, "", 1); end end end begin uvm_reg_map_addr_range range = '{ min, max, stride}; top_map.m_mems_by_offset[ range ] = mem; m_mems_info[mem].addr = addrs; m_mems_info[mem].mem_range = range; end end end if (bus_width == 0) bus_width = m_n_bytes; m_system_n_bytes = bus_width; endfunction function void uvm_reg_map::Xget_bus_infoX(uvm_reg_item rw, output uvm_reg_map_info map_info, output int size, output int lsb, output int addr_skip); if (rw.element_kind == UVM_MEM) begin uvm_mem mem; if(rw.element == null || !$cast(mem,rw.element)) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"REG/CAST")) uvm_report_fatal ("REG/CAST", {"uvm_reg_item 'element_kind' is UVM_MEM, ", "but 'element' does not point to a memory: ",rw.get_name()}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1639, "", 1); end map_info = get_mem_map_info(mem); size = mem.get_n_bits(); end else if (rw.element_kind == UVM_REG) begin uvm_reg rg; if(rw.element == null || !$cast(rg,rw.element)) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"REG/CAST")) uvm_report_fatal ("REG/CAST", {"uvm_reg_item 'element_kind' is UVM_REG, ", "but 'element' does not point to a register: ",rw.get_name()}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1647, "", 1); end map_info = get_reg_map_info(rg); size = rg.get_n_bits(); end else if (rw.element_kind == UVM_FIELD) begin uvm_reg_field field; if(rw.element == null || !$cast(field,rw.element)) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"REG/CAST")) uvm_report_fatal ("REG/CAST", {"uvm_reg_item 'element_kind' is UVM_FIELD, ", "but 'element' does not point to a field: ",rw.get_name()}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1655, "", 1); end map_info = get_reg_map_info(field.get_parent()); size = field.get_n_bits(); lsb = field.get_lsb_pos(); addr_skip = lsb/(get_n_bytes()*8); end endfunction task uvm_reg_map::do_write(uvm_reg_item rw); uvm_sequence_base tmp_parent_seq; uvm_reg_map system_map = get_root_map(); uvm_reg_adapter adapter = system_map.get_adapter(); uvm_sequencer_base sequencer = system_map.get_sequencer(); uvm_reg_seq_base parent_proxy; if (adapter != null && adapter.parent_sequence != null) begin uvm_object o; uvm_sequence_base seq; o = adapter.parent_sequence.clone(); if (o == null) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"REG/CLONE")) uvm_report_fatal ("REG/CLONE", {"failed to clone adapter's parent sequence: '", adapter.parent_sequence.get_full_name(), "' (of type '", adapter.parent_sequence.get_type_name(), "')"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1686, "", 1); end if (!$cast(seq, o)) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"REG/CAST")) uvm_report_fatal ("REG/CAST", {"failed to cast: '", o.get_full_name(), "' (of type '", o.get_type_name(), "') to uvm_sequence_base!"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1693, "", 1); end seq.set_parent_sequence(rw.parent); rw.parent = seq; tmp_parent_seq = seq; end if (rw.parent == null) begin parent_proxy = new("default_parent_seq"); rw.parent = parent_proxy; tmp_parent_seq = rw.parent; end if (adapter == null) begin uvm_event#(uvm_object) end_event ; uvm_event_pool ep; ep = rw.get_event_pool(); end_event = ep.get("end") ; rw.set_sequencer(sequencer); rw.parent.start_item(rw,rw.prior); rw.parent.finish_item(rw); end_event.wait_on(); end else begin do_bus_write(rw, sequencer, adapter); end if (tmp_parent_seq != null) sequencer.m_sequence_exiting(tmp_parent_seq); endtask task uvm_reg_map::do_read(uvm_reg_item rw); uvm_sequence_base tmp_parent_seq; uvm_reg_map system_map = get_root_map(); uvm_reg_adapter adapter = system_map.get_adapter(); uvm_sequencer_base sequencer = system_map.get_sequencer(); uvm_reg_seq_base parent_proxy; if (adapter != null && adapter.parent_sequence != null) begin uvm_object o; uvm_sequence_base seq; o = adapter.parent_sequence.clone(); if (o == null) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"REG/CLONE")) uvm_report_fatal ("REG/CLONE", {"failed to clone adapter's parent sequence: '", adapter.parent_sequence.get_full_name(), "' (of type '", adapter.parent_sequence.get_type_name(), "')"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1745, "", 1); end if (!$cast(seq, o)) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"REG/CAST")) uvm_report_fatal ("REG/CAST", {"failed to cast: '", o.get_full_name(), "' (of type '", o.get_type_name(), "') to uvm_sequence_base!"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1752, "", 1); end seq.set_parent_sequence(rw.parent); rw.parent = seq; tmp_parent_seq = seq; end if (rw.parent == null) begin parent_proxy = new("default_parent_seq"); rw.parent = parent_proxy; tmp_parent_seq = rw.parent; end if (adapter == null) begin uvm_event#(uvm_object) end_event ; uvm_event_pool ep; ep = rw.get_event_pool(); end_event = ep.get("end") ; rw.set_sequencer(sequencer); rw.parent.start_item(rw,rw.prior); rw.parent.finish_item(rw); end_event.wait_on(); end else begin do_bus_read(rw, sequencer, adapter); end if (tmp_parent_seq != null) sequencer.m_sequence_exiting(tmp_parent_seq); endtask task uvm_reg_map::do_bus_write (uvm_reg_item rw, uvm_sequencer_base sequencer, uvm_reg_adapter adapter); do_bus_access(rw, sequencer, adapter); endtask task uvm_reg_map::perform_accesses(ref uvm_reg_bus_op accesses[$], input uvm_reg_item rw, input uvm_reg_adapter adapter, input uvm_sequencer_base sequencer); string op; uvm_reg_data_logic_t data; uvm_endianness_e endian; op=(rw.kind inside {UVM_READ,UVM_BURST_READ}) ? "Read" : "Wrote"; endian=get_endian(UVM_NO_HIER); if(policy!=null) policy.order(accesses); foreach(accesses[i]) begin uvm_reg_bus_op rw_access=accesses[i]; uvm_sequence_item bus_req; if ((rw_access.kind == UVM_WRITE) && (endian == UVM_BIG_ENDIAN)) begin { >> { rw_access.data }} = { << byte { rw_access.data}}; end adapter.m_set_item(rw); bus_req = adapter.reg2bus(rw_access); adapter.m_set_item(null); if (bus_req == null) begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"RegMem")) uvm_report_fatal ("RegMem", {"adapter [",adapter.get_name(),"] didnt return a bus transaction"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_map.svh", 1823, "", 1); end bus_req.set_sequencer(sequencer); rw.parent.start_item(bus_req,rw.prior); if (rw.parent != null && i == 0) rw.parent.mid_do(rw); rw.parent.finish_item(bus_req); begin uvm_event#(uvm_object) end_event ; uvm_event_pool ep; ep = bus_req.get_event_pool(); end_event = ep.get("end") ; end_event.wait_on(); end if (adapter.provides_responses) begin uvm_sequence_item bus_rsp; uvm_access_e op; rw.parent.get_base_response(bus_rsp,bus_req.get_transaction_id()); adapter.bus2reg(bus_rsp,rw_access); end else begin adapter.bus2reg(bus_req,rw_access); end if ((rw_access.kind == UVM_READ) && (endian == UVM_BIG_ENDIAN)) begin { >> { rw_access.data }} = { << byte { rw_access.data}}; end rw.status = rw_access.status; begin data = rw_access.data & ((1<>bit_shift) & 'hff; p[idx]=n; end if(extra_byte) p.push_back(ac); end accesses.delete(); foreach(adr[i]) begin uvm_reg_bus_op rw_access; uvm_reg_data_t data; for(int i0=0;i0=0;i--) begin if(rw_access.byte_en[i]==0) rw_access.n_bits-=8; else break; end accesses.push_back(rw_access); end perform_accesses(accesses, rw, adapter, sequencer); if(rw.kind inside {UVM_READ,UVM_BURST_READ}) begin p.delete(); foreach(accesses[i0]) for(int i1=0;i1 max_size) max_size = uvm_reg_field::get_max_size(); if (uvm_mem::get_max_size() > max_size) max_size = uvm_mem::get_max_size(); if (max_size > 64) begin begin if (uvm_report_enabled(UVM_NONE,UVM_FATAL,"RegModel")) uvm_report_fatal ("RegModel", $sformatf("Register model requires that UVM_REG_DATA_WIDTH be defined as %0d or greater. Currently defined as %0d", max_size, 64), UVM_NONE, "t/uvm/src/reg/uvm_reg_block.svh", 1153, "", 1); end end Xinit_address_mapsX(); if(m_root_names[get_name()]>1) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"UVM/REG/DUPLROOT")) uvm_report_error ("UVM/REG/DUPLROOT", $sformatf("There are %0d root register models named \"%s\". The names of the root register models have to be unique", m_root_names[get_name()], get_name()), UVM_NONE, "t/uvm/src/reg/uvm_reg_block.svh", 1162, "", 1); end -> m_uvm_lock_model_complete; end endfunction function string uvm_reg_block::get_full_name(); if (parent == null) return get_name(); return {parent.get_full_name(), ".", get_name()}; endfunction: get_full_name function void uvm_reg_block::get_fields(ref uvm_reg_field fields[$], input uvm_hier_e hier=UVM_HIER); foreach (regs[rg_]) begin uvm_reg rg = rg_; rg.get_fields(fields); end if (hier == UVM_HIER) foreach (blks[blk_]) begin uvm_reg_block blk = blk_; blk.get_fields(fields); end endfunction: get_fields function void uvm_reg_block::get_virtual_fields(ref uvm_vreg_field fields[$], input uvm_hier_e hier=UVM_HIER); foreach (vregs[vreg_]) begin uvm_vreg vreg = vreg_; vreg.get_fields(fields); end if (hier == UVM_HIER) foreach (blks[blk_]) begin uvm_reg_block blk = blk_; blk.get_virtual_fields(fields); end endfunction: get_virtual_fields function void uvm_reg_block::get_registers(ref uvm_reg regs[$], input uvm_hier_e hier=UVM_HIER); foreach (this.regs[rg]) regs.push_back(rg); if (hier == UVM_HIER) foreach (blks[blk_]) begin uvm_reg_block blk = blk_; blk.get_registers(regs); end endfunction: get_registers function void uvm_reg_block::get_virtual_registers(ref uvm_vreg regs[$], input uvm_hier_e hier=UVM_HIER); foreach (vregs[rg]) regs.push_back(rg); if (hier == UVM_HIER) foreach (blks[blk_]) begin uvm_reg_block blk = blk_; blk.get_virtual_registers(regs); end endfunction: get_virtual_registers function void uvm_reg_block::get_memories(ref uvm_mem mems[$], input uvm_hier_e hier=UVM_HIER); foreach (this.mems[mem_]) begin uvm_mem mem = mem_; mems.push_back(mem); end if (hier == UVM_HIER) foreach (blks[blk_]) begin uvm_reg_block blk = blk_; blk.get_memories(mems); end endfunction: get_memories function void uvm_reg_block::get_blocks(ref uvm_reg_block blks[$], input uvm_hier_e hier=UVM_HIER); foreach (this.blks[blk_]) begin uvm_reg_block blk = blk_; blks.push_back(blk); if (hier == UVM_HIER) blk.get_blocks(blks); end endfunction: get_blocks function void uvm_reg_block::get_root_blocks(ref uvm_reg_block blks[$]); foreach (m_roots[blk]) begin blks.push_back(blk); end endfunction function int uvm_reg_block::find_blocks(input string name, ref uvm_reg_block blks[$], input uvm_reg_block root = null, input uvm_object accessor = null); uvm_reg_block r[$]; uvm_reg_block b[$]; if (root != null) begin name = {root.get_full_name(), ".", name}; b='{root}; end else begin get_root_blocks(b); end foreach(b[idx]) begin r.push_back(b[idx]); b[idx].get_blocks(r); end blks.delete(); foreach(r[idx]) begin if ( uvm_is_match( name, r[idx].get_full_name() ) ) blks.push_back(r[idx]); end return blks.size(); endfunction function uvm_reg_block uvm_reg_block::find_block(input string name, input uvm_reg_block root = null, input uvm_object accessor = null); uvm_reg_block blks[$]; if (!find_blocks(name, blks, root, accessor)) return null; if (blks.size() > 1) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"MRTH1BLK")) uvm_report_warning ("MRTH1BLK", {"More than one block matched the name \"", name, "\"."}, UVM_NONE, "t/uvm/src/reg/uvm_reg_block.svh", 1341, "", 1); end end return blks[0]; endfunction function void uvm_reg_block::get_maps(ref uvm_reg_map maps[$]); foreach (this.maps[map]) maps.push_back(map); endfunction function uvm_reg_block uvm_reg_block::get_parent(); get_parent = this.parent; endfunction: get_parent function uvm_reg_block uvm_reg_block::get_block_by_name(string name); if (get_name() == name) return this; foreach (blks[blk_]) begin uvm_reg_block blk = blk_; if (blk.get_name() == name) return blk; end foreach (blks[blk_]) begin uvm_reg_block blk = blk_; uvm_reg_block subblks[$]; blk_.get_blocks(subblks, UVM_HIER); foreach (subblks[j]) if (subblks[j].get_name() == name) return subblks[j]; end begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Unable to locate block '",name, "' in block '",get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_block.svh", 1395, "", 1); end return null; endfunction: get_block_by_name function uvm_reg uvm_reg_block::get_reg_by_name(string name); foreach (regs[rg_]) begin uvm_reg rg = rg_; if (rg.get_name() == name) return rg; end foreach (blks[blk_]) begin uvm_reg_block blk = blk_; uvm_reg subregs[$]; blk_.get_registers(subregs, UVM_HIER); foreach (subregs[j]) if (subregs[j].get_name() == name) return subregs[j]; end begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Unable to locate register '",name, "' in block '",get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_block.svh", 1422, "", 1); end return null; endfunction: get_reg_by_name function uvm_vreg uvm_reg_block::get_vreg_by_name(string name); foreach (vregs[rg_]) begin uvm_vreg rg = rg_; if (rg.get_name() == name) return rg; end foreach (blks[blk_]) begin uvm_reg_block blk = blk_; uvm_vreg subvregs[$]; blk_.get_virtual_registers(subvregs, UVM_HIER); foreach (subvregs[j]) if (subvregs[j].get_name() == name) return subvregs[j]; end begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Unable to locate virtual register '",name, "' in block '",get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_block.svh", 1449, "", 1); end return null; endfunction: get_vreg_by_name function uvm_mem uvm_reg_block::get_mem_by_name(string name); foreach (mems[mem_]) begin uvm_mem mem = mem_; if (mem.get_name() == name) return mem; end foreach (blks[blk_]) begin uvm_reg_block blk = blk_; uvm_mem submems[$]; blk_.get_memories(submems, UVM_HIER); foreach (submems[j]) if (submems[j].get_name() == name) return submems[j]; end begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Unable to locate memory '",name, "' in block '",get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_block.svh", 1476, "", 1); end return null; endfunction: get_mem_by_name function uvm_reg_field uvm_reg_block::get_field_by_name(string name); foreach (regs[rg_]) begin uvm_reg rg = rg_; uvm_reg_field fields[$]; rg.get_fields(fields); foreach (fields[i]) if (fields[i].get_name() == name) return fields[i]; end foreach (blks[blk_]) begin uvm_reg_block blk = blk_; uvm_reg subregs[$]; blk_.get_registers(subregs, UVM_HIER); foreach (subregs[j]) begin uvm_reg_field fields[$]; subregs[j].get_fields(fields); foreach (fields[i]) if (fields[i].get_name() == name) return fields[i]; end end begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Unable to locate field '",name, "' in block '",get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_block.svh", 1511, "", 1); end return null; endfunction: get_field_by_name function uvm_vreg_field uvm_reg_block::get_vfield_by_name(string name); foreach (vregs[rg_]) begin uvm_vreg rg =rg_; uvm_vreg_field fields[$]; rg.get_fields(fields); foreach (fields[i]) if (fields[i].get_name() == name) return fields[i]; end foreach (blks[blk_]) begin uvm_reg_block blk = blk_; uvm_vreg subvregs[$]; blk_.get_virtual_registers(subvregs, UVM_HIER); foreach (subvregs[j]) begin uvm_vreg_field fields[$]; subvregs[j].get_fields(fields); foreach (fields[i]) if (fields[i].get_name() == name) return fields[i]; end end begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Unable to locate virtual field '",name, "' in block '",get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_block.svh", 1547, "", 1); end return null; endfunction: get_vfield_by_name function uvm_reg_cvr_t uvm_reg_block::set_coverage(uvm_reg_cvr_t is_on); this.cover_on = this.has_cover & is_on; foreach (regs[rg_]) begin uvm_reg rg = rg_; void'(rg.set_coverage(is_on)); end foreach (mems[mem_]) begin uvm_mem mem = mem_; void'(mem.set_coverage(is_on)); end foreach (blks[blk_]) begin uvm_reg_block blk = blk_; void'(blk.set_coverage(is_on)); end return this.cover_on; endfunction: set_coverage function void uvm_reg_block::sample_values(); foreach (regs[rg_]) begin uvm_reg rg = rg_; rg.sample_values(); end foreach (blks[blk_]) begin uvm_reg_block blk = blk_; blk.sample_values(); end endfunction function void uvm_reg_block::XsampleX(uvm_reg_addr_t addr, bit is_read, uvm_reg_map map); sample(addr, is_read, map); if (parent != null) begin end endfunction function uvm_reg_cvr_t uvm_reg_block::build_coverage(uvm_reg_cvr_t models); build_coverage = UVM_NO_COVERAGE; void'(uvm_reg_cvr_rsrc_db::read_by_name({"uvm_reg::", get_full_name()}, "include_coverage", build_coverage, this)); return build_coverage & models; endfunction: build_coverage function void uvm_reg_block::add_coverage(uvm_reg_cvr_t models); this.has_cover |= models; endfunction: add_coverage function bit uvm_reg_block::has_coverage(uvm_reg_cvr_t models); return ((this.has_cover & models) == models); endfunction: has_coverage function bit uvm_reg_block::get_coverage(uvm_reg_cvr_t is_on = UVM_CVR_ALL); if (this.has_coverage(is_on) == 0) return 0; return ((this.cover_on & is_on) == is_on); endfunction: get_coverage function void uvm_reg_block::reset(string kind = "HARD"); foreach (regs[rg_]) begin uvm_reg rg = rg_; rg.reset(kind); end foreach (blks[blk_]) begin uvm_reg_block blk = blk_; blk.reset(kind); end endfunction function bit uvm_reg_block::needs_update(); needs_update = 0; foreach (regs[rg_]) begin uvm_reg rg = rg_; if (rg.needs_update()) return 1; end foreach (blks[blk_]) begin uvm_reg_block blk =blk_; if (blk.needs_update()) return 1; end endfunction: needs_update task uvm_reg_block::update(output uvm_status_e status, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); status = UVM_IS_OK; if (!needs_update()) begin begin if (uvm_report_enabled(UVM_HIGH,UVM_INFO,"RegModel")) uvm_report_info ("RegModel", $sformatf("%s:%0d - RegModel block %s does not need updating", fname, lineno, this.get_name()), UVM_HIGH, "t/uvm/src/reg/uvm_reg_block.svh", 1694, "", 1); end return; end begin if (uvm_report_enabled(UVM_HIGH,UVM_INFO,"RegModel")) uvm_report_info ("RegModel", $sformatf("%s:%0d - Updating model block %s with %s path", fname, lineno, this.get_name(), path.name ), UVM_HIGH, "t/uvm/src/reg/uvm_reg_block.svh", 1699, "", 1); end foreach (regs[rg_]) begin uvm_reg rg = rg_; if (rg.needs_update()) begin rg.update(status, path, null, parent, prior, extension); if (status != UVM_IS_OK && status != UVM_HAS_X) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", $sformatf("Register \"%s\" could not be updated", rg.get_full_name()), UVM_NONE, "t/uvm/src/reg/uvm_reg_block.svh", 1707, "", 1); end return; end end end foreach (blks[blk_]) begin uvm_reg_block blk = blk_; blk.update(status,path,parent,prior,extension,fname,lineno); end endtask: update task uvm_reg_block::mirror(output uvm_status_e status, input uvm_check_e check = UVM_NO_CHECK, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_status_e final_status = UVM_IS_OK; foreach (regs[rg_]) begin uvm_reg rg = rg_; rg.mirror(status, check, path, null, parent, prior, extension, fname, lineno); if (status != UVM_IS_OK && status != UVM_HAS_X) begin final_status = status; end end foreach (blks[blk_]) begin uvm_reg_block blk = blk_; blk.mirror(status, check, path, parent, prior, extension, fname, lineno); if (status != UVM_IS_OK && status != UVM_HAS_X) begin final_status = status; end end endtask: mirror task uvm_reg_block::write_reg_by_name(output uvm_status_e status, input string name, input uvm_reg_data_t data, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_reg rg; this.fname = fname; this.lineno = lineno; status = UVM_NOT_OK; rg = this.get_reg_by_name(name); if (rg != null) rg.write(status, data, path, map, parent, prior, extension); endtask: write_reg_by_name task uvm_reg_block::read_reg_by_name(output uvm_status_e status, input string name, output uvm_reg_data_t data, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_reg rg; this.fname = fname; this.lineno = lineno; status = UVM_NOT_OK; rg = this.get_reg_by_name(name); if (rg != null) rg.read(status, data, path, map, parent, prior, extension); endtask: read_reg_by_name task uvm_reg_block::write_mem_by_name(output uvm_status_e status, input string name, input uvm_reg_addr_t offset, input uvm_reg_data_t data, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_mem mem; this.fname = fname; this.lineno = lineno; status = UVM_NOT_OK; mem = get_mem_by_name(name); if (mem != null) mem.write(status, offset, data, path, map, parent, prior, extension); endtask: write_mem_by_name task uvm_reg_block::read_mem_by_name(output uvm_status_e status, input string name, input uvm_reg_addr_t offset, output uvm_reg_data_t data, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); uvm_mem mem; this.fname = fname; this.lineno = lineno; status = UVM_NOT_OK; mem = get_mem_by_name(name); if (mem != null) mem.read(status, offset, data, path, map, parent, prior, extension); endtask: read_mem_by_name task uvm_reg_block::readmemh(string filename); endtask: readmemh task uvm_reg_block::writememh(string filename); endtask: writememh function uvm_reg_map uvm_reg_block::create_map(string name, uvm_reg_addr_t base_addr, int unsigned n_bytes, uvm_endianness_e endian, bit byte_addressing=1); uvm_reg_map map; map = uvm_reg_map::type_id::create(name,,this.get_full_name()); map.configure(this,base_addr,n_bytes,endian,byte_addressing); add_map(map); return map; endfunction function void uvm_reg_block::add_map(uvm_reg_map map); if (this.locked) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", "Cannot add map to locked model", UVM_NONE, "t/uvm/src/reg/uvm_reg_block.svh", 1890, "", 1); end return; end if (this.maps.exists(map)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Map '",map.get_name(), "' already exists in '",get_full_name(),"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_block.svh", 1896, "", 1); end return; end this.maps[map] = 1; if (maps.num() == 1) default_map = map; endfunction: add_map function uvm_reg_map uvm_reg_block::get_map_by_name(string name); uvm_reg_map maps[$]; this.get_maps(maps); foreach (maps[i]) if (maps[i].get_name() == name) return maps[i]; foreach (maps[i]) begin uvm_reg_map submaps[$]; maps[i].get_submaps(submaps, UVM_HIER); foreach (submaps[j]) if (submaps[j].get_name() == name) return submaps[j]; end begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Map with name '",name,"' does not exist in block"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_block.svh", 1928, "", 1); end return null; endfunction function void uvm_reg_block::set_default_map(uvm_reg_map map); if (!maps.exists(map)) begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Map '",map.get_full_name(),"' does not exist in block"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_block.svh", 1937, "", 1); end default_map = map; endfunction function uvm_reg_map uvm_reg_block::get_default_map(); return default_map; endfunction function uvm_door_e uvm_reg_block::get_default_door(); if (this.default_path != UVM_DEFAULT_DOOR) return this.default_path; if (this.parent != null) return this.parent.get_default_door(); return UVM_FRONTDOOR; endfunction function void uvm_reg_block::set_default_door(uvm_door_e door); this.default_path = door; endfunction function void uvm_reg_block::Xinit_address_mapsX(); foreach (maps[map_]) begin uvm_reg_map map = map_; map.Xinit_address_mapX(); end endfunction function void uvm_reg_block::set_backdoor(uvm_reg_backdoor bkdr, string fname = "", int lineno = 0); bkdr.fname = fname; bkdr.lineno = lineno; if (this.backdoor != null && this.backdoor.has_update_threads()) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", "Previous register backdoor still has update threads running. Backdoors with active mirroring should only be set before simulation starts.", UVM_NONE, "t/uvm/src/reg/uvm_reg_block.svh", 2000, "", 1); end end this.backdoor = bkdr; endfunction: set_backdoor function uvm_reg_backdoor uvm_reg_block::get_backdoor(bit inherited = 1); if (backdoor == null && inherited) begin uvm_reg_block blk = get_parent(); while (blk != null) begin uvm_reg_backdoor bkdr = blk.get_backdoor(); if (bkdr != null) return bkdr; blk = blk.get_parent(); end end return this.backdoor; endfunction: get_backdoor function void uvm_reg_block::clear_hdl_path(string kind = "RTL"); if (kind == "ALL") begin hdl_paths_pool = new("hdl_paths"); return; end if (kind == "") kind = get_default_hdl_path(); if (!hdl_paths_pool.exists(kind)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"RegModel")) uvm_report_warning ("RegModel", {"Unknown HDL Abstraction '",kind,"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_block.svh", 2036, "", 1); end return; end hdl_paths_pool.delete(kind); endfunction function void uvm_reg_block::add_hdl_path(string path, string kind = "RTL"); uvm_queue #(string) paths; paths = hdl_paths_pool.get(kind); paths.push_back(path); endfunction function bit uvm_reg_block::has_hdl_path(string kind = ""); if (kind == "") begin kind = get_default_hdl_path(); end return hdl_paths_pool.exists(kind); endfunction function void uvm_reg_block::get_hdl_path(ref string paths[$], input string kind = ""); uvm_queue #(string) hdl_paths; if (kind == "") kind = get_default_hdl_path(); if (!has_hdl_path(kind)) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"RegModel")) uvm_report_error ("RegModel", {"Block does not have hdl path defined for abstraction '",kind,"'"}, UVM_NONE, "t/uvm/src/reg/uvm_reg_block.svh", 2077, "", 1); end return; end hdl_paths = hdl_paths_pool.get(kind); for (int i=0; i 0) begin mem.read(status, k-1, val, UVM_FRONTDOOR, maps[j], this); if (status != UVM_IS_OK) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"uvm_mem_walk_seq")) uvm_report_error ("uvm_mem_walk_seq", $sformatf("Status was %s when reading \"%s[%0d]\" through map \"%s\".", status.name(), mem.get_full_name(), k, maps[j].get_full_name()), UVM_NONE, "t/uvm/src/reg/sequences/uvm_mem_walk_seq.svh", 143, "", 1); end end else begin exp = ~(k-1) & ((1'b1< 32) val = uvm_reg_data_t'(val << 32) | $random; if (mode == "RO") begin mem.peek(status, k, exp); if (status != UVM_IS_OK) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"uvm_mem_access_seq")) uvm_report_error ("uvm_mem_access_seq", $sformatf("Status was %s when reading \"%s[%0d]\" through backdoor.", status.name(), mem.get_full_name(), k), UVM_NONE, "t/uvm/src/reg/sequences/uvm_mem_access_seq.svh", 124, "", 1); end end end else exp = val; mem.write(status, k, val, UVM_FRONTDOOR, maps[j], this); if (status != UVM_IS_OK) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"uvm_mem_access_seq")) uvm_report_error ("uvm_mem_access_seq", $sformatf("Status was %s when writing \"%s[%0d]\" through map \"%s\".", status.name(), mem.get_full_name(), k, maps[j].get_full_name()), UVM_NONE, "t/uvm/src/reg/sequences/uvm_mem_access_seq.svh", 132, "", 1); end end #1; val = 'x; mem.peek(status, k, val); if (status != UVM_IS_OK) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"uvm_mem_access_seq")) uvm_report_error ("uvm_mem_access_seq", $sformatf("Status was %s when reading \"%s[%0d]\" through backdoor.", status.name(), mem.get_full_name(), k), UVM_NONE, "t/uvm/src/reg/sequences/uvm_mem_access_seq.svh", 140, "", 1); end end else begin if (val !== exp) begin begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"uvm_mem_access_seq")) uvm_report_error ("uvm_mem_access_seq", $sformatf("Backdoor \"%s[%0d]\" read back as 'h%h instead of 'h%h.", mem.get_full_name(), k, val, exp), UVM_NONE, "t/uvm/src/reg/sequences/uvm_mem_access_seq.svh", 145, "", 1); end end end exp = ~exp & ((1'b1< local_size__) abstractions = abstractions[0:local_size__-1]; else while (abstractions.size() < local_size__) abstractions.push_back(abstractions[local_size__]); foreach (abstractions[i]) abstractions[i] = __local_packer__.unpack_string(); end UVM_RECORD: if (!((UVM_DEFAULT)&UVM_NORECORD)) begin begin int sz__; foreach (abstractions[i]) sz__ = i; if(sz__ == 0) begin if (__local_recorder__ != null && __local_recorder__.is_open()) begin if (__local_recorder__.use_record_attribute()) __local_recorder__.record_generic("abstractions", $sformatf("%p", 0)); else if (32 > 64) __local_recorder__.record_field("abstractions", 0, 32, UVM_DEC); else __local_recorder__.record_field_int("abstractions", 0, 32, UVM_DEC); end end else if(sz__ < 10) begin foreach(abstractions[i]) begin string nm__ = $sformatf("%s[%0d]", "abstractions", i); if (__local_recorder__ != null && __local_recorder__.is_open()) begin if (__local_recorder__.use_record_attribute()) __local_recorder__.record_generic(nm__, $sformatf("%p", abstractions[i])); else __local_recorder__.record_string(nm__,abstractions[i]); end end end else begin for(int i=0; i<5; ++i) begin string nm__ = $sformatf("%s[%0d]", "abstractions", i); if (__local_recorder__ != null && __local_recorder__.is_open()) begin if (__local_recorder__.use_record_attribute()) __local_recorder__.record_generic(nm__, $sformatf("%p", abstractions[i])); else __local_recorder__.record_string(nm__,abstractions[i]); end end for(int i=sz__-5; i __tmp_curr) __tmp_curr = __tmp_max - __tmp_end_elements; if (__tmp_curr < __tmp_begin_elements) __tmp_curr = __tmp_begin_elements; else __local_printer__.print_array_range(__tmp_begin_elements, __tmp_curr-1); while (__tmp_curr < __tmp_max) begin __local_printer__.print_string($sformatf("[%0d]", __tmp_curr), abstractions[__tmp_curr]); __tmp_curr++; end end end end __local_printer__.print_array_footer(__tmp_max); end end UVM_SET: if (!((UVM_DEFAULT)&UVM_NOSET)) begin if(local_rsrc_name__ == "abstractions") begin begin begin uvm_resource#(uvm_integral_t) __tmp_rsrc__; local_success__ = $cast(__tmp_rsrc__, local_rsrc__); if (local_success__) begin local_size__ = __tmp_rsrc__.read(this); end end if (!local_success__) begin uvm_resource#(uvm_bitstream_t) __tmp_rsrc__; local_success__ = $cast(__tmp_rsrc__, local_rsrc__); if (local_success__) begin local_size__ = __tmp_rsrc__.read(this); end end if (!local_success__) begin uvm_resource#(int) __tmp_rsrc__; local_success__ = $cast(__tmp_rsrc__, local_rsrc__); if (local_success__) begin local_size__ = __tmp_rsrc__.read(this); end end if (!local_success__) begin uvm_resource#(int unsigned) __tmp_rsrc__; local_success__ = $cast(__tmp_rsrc__, local_rsrc__); if (local_success__) begin local_size__ = __tmp_rsrc__.read(this); end end end if (local_success__) if (abstractions.size() > local_size__) abstractions = abstractions[0:local_size__-1]; else while (abstractions.size() < local_size__) abstractions.push_back(abstractions[local_size__]); end else begin string local_name__ = {"abstractions", "["}; if (local_rsrc_name__.len() && local_rsrc_name__[local_rsrc_name__.len()-1] == "]" && local_rsrc_name__.substr(0, local_name__.len()-1) == local_name__) begin string local_index_str__ = local_rsrc_name__.substr(local_name__.len(), local_rsrc_name__.len()-2); int local_index__; int local_code__ = $sscanf(local_index_str__, "%d", local_index__); if (local_code__ > 0) begin if (local_index__ < 0) begin begin if (uvm_report_enabled(UVM_NONE,UVM_WARNING,"UVM/FIELDS/QDA_IDX")) uvm_report_warning ("UVM/FIELDS/QDA_IDX", $sformatf("Index '%0d' is not valid for field '%s.%s' of size '%0d'", local_index__, get_full_name(), "abstractions", abstractions.size() ), UVM_NONE, "t/uvm/src/reg/sequences/uvm_reg_mem_hdl_paths_seq.svh", 59, "", 1); end end else begin string tmp_string__; begin uvm_resource#(string) __tmp_rsrc__; local_success__ = $cast(__tmp_rsrc__, local_rsrc__); if (local_success__) begin tmp_string__ = __tmp_rsrc__.read(this); end end if (local_success__) begin if (local_index__ >= abstractions.size()) if (abstractions.size() > local_index__ + 1) abstractions = abstractions[0:local_index__ + 1-1]; else while (abstractions.size() < local_index__ + 1) abstractions.push_back(abstractions[local_index__ + 1]); abstractions[local_index__] = tmp_string__; end end end end end end endcase end endfunction : __m_uvm_execute_field_op function new(string name="uvm_reg_mem_hdl_paths_seq"); super.new(name); endfunction virtual task body(); if (model == null) begin uvm_report_error("uvm_reg_mem_hdl_paths_seq", "Register model handle is null"); return; end begin if (uvm_report_enabled(UVM_LOW,UVM_INFO,"uvm_reg_mem_hdl_paths_seq")) uvm_report_info ("uvm_reg_mem_hdl_paths_seq", {"checking HDL paths for all registers/memories in ", model.get_full_name()}, UVM_LOW, "t/uvm/src/reg/sequences/uvm_reg_mem_hdl_paths_seq.svh", 76, "", 1); end if (abstractions.size() == 0) do_block(model, ""); else begin foreach (abstractions[i]) do_block(model, abstractions[i]); end begin if (uvm_report_enabled(UVM_LOW,UVM_INFO,"uvm_reg_mem_hdl_paths_seq")) uvm_report_info ("uvm_reg_mem_hdl_paths_seq", "HDL path validation completed ", UVM_LOW, "t/uvm/src/reg/sequences/uvm_reg_mem_hdl_paths_seq.svh", 85, "", 1); end endtask: body virtual task reset_blk(uvm_reg_block blk); endtask protected virtual function void do_block(uvm_reg_block blk, string kind); uvm_reg regs[$]; uvm_mem mems[$]; begin if (uvm_report_enabled(UVM_MEDIUM,UVM_INFO,"uvm_reg_mem_hdl_paths_seq")) uvm_report_info ("uvm_reg_mem_hdl_paths_seq", {"Validating HDL paths in ", blk.get_full_name(), " for ", (kind == "") ? "default" : kind, " design abstraction"}, UVM_MEDIUM, "t/uvm/src/reg/sequences/uvm_reg_mem_hdl_paths_seq.svh", 104, "", 1); end blk.get_registers(regs, UVM_NO_HIER); foreach (regs[i]) check_reg(regs[i], kind); blk.get_memories(mems, UVM_NO_HIER); foreach (mems[i]) check_mem(mems[i], kind); begin uvm_reg_block blks[$]; blk.get_blocks(blks); foreach (blks[i]) begin do_block(blks[i], kind); end end endfunction: do_block protected virtual function void check_reg(uvm_reg r, string kind); uvm_hdl_path_concat paths[$]; if(!r.has_hdl_path(kind)) return; r.get_full_hdl_path(paths, kind); if (paths.size() == 0) return; foreach(paths[p]) begin uvm_hdl_path_concat path=paths[p]; foreach (path.slices[j]) begin string p_ = path.slices[j].path; uvm_reg_data_t d; if (!uvm_hdl_read(p_,d)) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"uvm_reg_mem_hdl_paths_seq")) uvm_report_error ("uvm_reg_mem_hdl_paths_seq", $sformatf("HDL path \"%s\" for register \"%s\" is not readable", p_, r.get_full_name()), UVM_NONE, "t/uvm/src/reg/sequences/uvm_reg_mem_hdl_paths_seq.svh", 145, "", 1); end if (!uvm_hdl_check_path(p_)) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"uvm_reg_mem_hdl_paths_seq")) uvm_report_error ("uvm_reg_mem_hdl_paths_seq", $sformatf("HDL path \"%s\" for register \"%s\" is not accessible", p_, r.get_full_name()), UVM_NONE, "t/uvm/src/reg/sequences/uvm_reg_mem_hdl_paths_seq.svh", 149, "", 1); end end end endfunction protected virtual function void check_mem(uvm_mem m, string kind); uvm_hdl_path_concat paths[$]; if(!m.has_hdl_path(kind)) return; m.get_full_hdl_path(paths, kind); if (paths.size() == 0) return; foreach(paths[p]) begin uvm_hdl_path_concat path=paths[p]; foreach (path.slices[j]) begin string p_ = path.slices[j].path; if(!uvm_hdl_check_path(p_)) begin if (uvm_report_enabled(UVM_NONE,UVM_ERROR,"uvm_reg_mem_hdl_paths_seq")) uvm_report_error ("uvm_reg_mem_hdl_paths_seq", $sformatf("HDL path \"%s\" for memory \"%s\" is not accessible", p_, m.get_full_name()), UVM_NONE, "t/uvm/src/reg/sequences/uvm_reg_mem_hdl_paths_seq.svh", 174, "", 1); end end end endfunction endclass: uvm_reg_mem_hdl_paths_seq endpackage verilator-5.042/test_regress/t/uvm/dpi/0000755000542200017500000000000015101701376020451 5ustar mahmoudyfreeshellverilator-5.042/test_regress/t/uvm/dpi/uvm_common.c0000644000542200017500000000335315101701376023000 0ustar mahmoudyfreeshell//---------------------------------------------------------------------- // Copyright 2010-2011 Mentor Graphics Corporation // Copyright 2010-2013 Synopsys, Inc. // Copyright 2010-2018 Cadence Design Systems, Inc. // Copyright 2010 AMD // Copyright 2013 NVIDIA Corporation // All Rights Reserved Worldwide // // Licensed under the Apache License, Version 2.0 (the // "License"); you may not use this file except in // compliance with the License. You may obtain a copy of // the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in // writing, software distributed under the License is // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // CONDITIONS OF ANY KIND, either express or implied. See // the License for the specific language governing // permissions and limitations under the License. //---------------------------------------------------------------------- // Implementation of common methods for DPI extern void m__uvm_report_dpi(int,const char*,const char*,int,const char*, int); #if defined(XCELIUM) || defined(NCSC) const static char* uvm_package_scope_name = "uvm_pkg::"; #else const static char* uvm_package_scope_name = "uvm_pkg"; #endif void m_uvm_report_dpi( int severity, char* id, char* message, int verbosity, char* file, int linenum) { svScope old_scope = svSetScope(svGetScopeFromName(uvm_package_scope_name)); m__uvm_report_dpi(severity, id, message, verbosity, file, linenum); svSetScope(old_scope); } int int_str_max ( int radix_bits ) { int val = INT_MAX; int ret = 1; while ((val = (val /radix_bits))) ret++; return ret; } verilator-5.042/test_regress/t/uvm/dpi/uvm_svcmd_dpi.c0000644000542200017500000000674415101701376023467 0ustar mahmoudyfreeshell// //------------------------------------------------------------------------------ // Copyright 2011-2014 Mentor Graphics Corporation // Copyright 2011-2018 Cadence Design Systems, Inc. // Copyright 2010-2012 AMD // Copyright 2013 NVIDIA Corporation // All Rights Reserved Worldwide // // Licensed under the Apache License, Version 2.0 (the // "License"); you may not use this file except in // compliance with the License. You may obtain a copy of // the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in // writing, software distributed under the License is // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // CONDITIONS OF ANY KIND, either express or implied. See // the License for the specific language governing // permissions and limitations under the License. //------------------------------------------------------------------------------ #include "uvm_dpi.h" #include #define ARGV_STACK_PTR_SIZE 32 // the total number of arguments (minus the -f/-F minus associated filenames) int argc_total; // the ptr to the array of ptrs to the args char** argv_stack=NULL; char ** argv_ptr=NULL; void push_data(int lvl,char *entry, int cmd) { if(cmd==0) argc_total++; else *argv_ptr++=entry; } // walk one level (potentially recursive) void walk_level(int lvl, int argc, char**argv,int cmd) { int idx; for(idx=0; ((lvl==0) && idx0) && (*argv));idx++,argv++) { if(strcmp(*argv, "-f") && strcmp(*argv, "-F")) { push_data(lvl,*argv,cmd); } else { argv++; idx++; char **n=(char**) *argv; walk_level(lvl+1,argc,++n,cmd); } } } const char *uvm_dpi_get_next_arg_c (int init) { s_vpi_vlog_info info; static int idx=0; if(init==1) { // free if necessary free(argv_stack); argc_total=0; vpi_get_vlog_info(&info); walk_level(0,info.argc,info.argv,0); argv_stack = (char**) malloc (sizeof(char*)*argc_total); argv_ptr=argv_stack; walk_level(0,info.argc,info.argv,1); idx=0; argv_ptr=argv_stack; } if(idx++>=argc_total) return NULL; return *argv_ptr++; } extern char* uvm_dpi_get_tool_name_c () { s_vpi_vlog_info info; vpi_get_vlog_info(&info); return info.product; } extern char* uvm_dpi_get_tool_version_c () { s_vpi_vlog_info info; vpi_get_vlog_info(&info); return info.version; } extern regex_t* uvm_dpi_regcomp (char* pattern) { regex_t* re = (regex_t*) malloc (sizeof(regex_t)); int status = regcomp(re, pattern, REG_NOSUB|REG_EXTENDED); if(status) { const char * err_str = "uvm_dpi_regcomp : Unable to compile regex: |%s|, Element 0 is: %c"; char buffer[strlen(err_str) + strlen(pattern) + 1]; sprintf(buffer, err_str, pattern, pattern[0]); m_uvm_report_dpi(M_UVM_ERROR, (char*)"UVM/DPI/REGCOMP", &buffer[0], M_UVM_NONE, (char*) __FILE__, __LINE__); regfree(re); free (re); return NULL; } return re; } extern int uvm_dpi_regexec (regex_t* re, char* str) { if(!re ) { return 1; } return regexec(re, str, (size_t)0, NULL, 0); } extern void uvm_dpi_regfree (regex_t* re) { if(!re) return; regfree(re); free (re); } verilator-5.042/test_regress/t/uvm/dpi/uvm_dpi.svh0000644000542200017500000000254315101701376022642 0ustar mahmoudyfreeshell//---------------------------------------------------------------------- // Copyright 2010-2011 Mentor Graphics Corporation // Copyright 2010 Synopsys, Inc. // Copyright 2010-2018 Cadence Design Systems, Inc. // Copyright 2010 AMD // All Rights Reserved Worldwide // // Licensed under the Apache License, Version 2.0 (the // "License"); you may not use this file except in // compliance with the License. You may obtain a copy of // the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in // writing, software distributed under the License is // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // CONDITIONS OF ANY KIND, either express or implied. See // the License for the specific language governing // permissions and limitations under the License. //---------------------------------------------------------------------- `ifndef UVM_DPI_SVH `define UVM_DPI_SVH // // Top-level file for DPI subroutines used by UVM. // // Tool-specific distribution overlays may be required. // // To use UVM without any tool-specific overlay, use +defin+UVM_NO_DPI // `ifdef UVM_NO_DPI `define UVM_HDL_NO_DPI `define UVM_REGEX_NO_DPI `define UVM_CMDLINE_NO_DPI `endif `include "dpi/uvm_hdl.svh" `include "dpi/uvm_svcmd_dpi.svh" `include "dpi/uvm_regex.svh" `endif // UVM_DPI_SVH verilator-5.042/test_regress/t/uvm/dpi/uvm_hdl_verilator.c0000644000542200017500000002356115101701376024351 0ustar mahmoudyfreeshell//---------------------------------------------------------------------- // Copyright 2007-2023 Cadence Design Systems, Inc. // Copyright 2009-2011 Mentor Graphics Corporation // Copyright 2013-2024 NVIDIA Corporation // Copyright 2010-2011 Synopsys, Inc. // All Rights Reserved Worldwide // // Licensed under the Apache License, Version 2.0 (the // "License"); you may not use this file except in // compliance with the License. You may obtain a copy of // the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in // writing, software distributed under the License is // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // CONDITIONS OF ANY KIND, either express or implied. See // the License for the specific language governing // permissions and limitations under the License. //---------------------------------------------------------------------- //---------------------------------------------------------------------- // Git details (see DEVELOPMENT.md): // // $File$ // $Rev$ // $Hash$ // //---------------------------------------------------------------------- #include "svdpi.h" #include "vpi_user.h" #include #include #include static void m_uvm_error(const char *ID, const char *msg, ...); static int uvm_hdl_set_vlog(char *path, p_vpi_vecval value, PLI_INT32 flag); static int uvm_hdl_get_vlog(char *path, p_vpi_vecval value, PLI_INT32 flag, int partsel); static int uvm_hdl_max_width(); // static print buffer static char m_uvm_temp_print_buffer[1024]; // static print error static void m_uvm_error(const char *id, const char *msg, ...) { va_list argptr; va_start(argptr, msg); vsprintf(m_uvm_temp_print_buffer, msg, argptr); va_end(argptr); m_uvm_report_dpi(M_UVM_ERROR, (char *)id, &m_uvm_temp_print_buffer[0], M_UVM_NONE, (char *)__FILE__, __LINE__); } /* * UVM HDL access C code. * */ /* * This C code checks to see if there is PLI handle * with a value set to define the maximum bit width. * * If no such variable is found, then the default * width of 1024 is used. * * This function should only get called once or twice, * its return value is cached in the caller. * */ static int UVM_HDL_MAX_WIDTH = 0; static int uvm_hdl_max_width() { if (!UVM_HDL_MAX_WIDTH) { vpiHandle ms; s_vpi_value value_s = {vpiIntVal, {0}}; ms = vpi_handle_by_name((PLI_BYTE8 *)"uvm_pkg::UVM_HDL_MAX_WIDTH", 0); if (ms == 0) { UVM_HDL_MAX_WIDTH = 1024; /* If nothing else is defined, this is the DEFAULT */ } else { vpi_get_value(ms, &value_s); UVM_HDL_MAX_WIDTH = value_s.value.integer; } } return UVM_HDL_MAX_WIDTH; } /* * Internals: Given a path, look at the path name and determine * the handle and any partsel's needed to access it. */ static vpiHandle uvm_hdl_handle_by_name_partsel(char *path, int *is_partsel_ptr, int *hi_ptr, int *lo_ptr) { vpiHandle r; char *path_ptr; char *path_base_ptr; int temp; *is_partsel_ptr = 0; if (!path || !path[0]) return 0; // If direct lookup works, go with that r = vpi_handle_by_name(path, 0); if (r) return r; // Find array subscript path_ptr = (char *)(path + strlen(path) - 1); if (*path_ptr != ']') return 0; while (path_ptr != path && *path_ptr != ':' && *path_ptr != '[') --path_ptr; if (path_ptr == path) return 0; *lo_ptr = *hi_ptr = atoi(path_ptr + 1); *is_partsel_ptr = 1; if (*path_ptr == ':') { --path_ptr; // back over : while (path_ptr != path && *path_ptr != '[') --path_ptr; *hi_ptr = atoi(path_ptr + 1); if (path_ptr == path) return 0; } if (*lo_ptr > *hi_ptr) { temp = *lo_ptr; *lo_ptr = *hi_ptr; *hi_ptr = temp; } path_base_ptr = strndup(path, (path_ptr - path)); r = vpi_handle_by_name(path_base_ptr, 0); if (!r) return 0; { vpiHandle rh; s_vpi_value value; int decl_ranged = 0; int decl_lo; int decl_hi; int decl_left = -1; int decl_right = -1; rh = vpi_handle(vpiLeftRange, r); if (rh) { value.format = vpiIntVal; vpi_get_value(rh, &value); decl_left = value.value.integer; vpi_release_handle(rh); } rh = vpi_handle(vpiRightRange, r); if (rh) { value.format = vpiIntVal; vpi_get_value(rh, &value); decl_ranged = 1; decl_right = value.value.integer; vpi_release_handle(rh); } if (!decl_ranged) { // vpi_printf((PLI_BYTE8 *)"Outside declaration '%s' range %d:%d\n", // path, decl_left, decl_right); return 0; } // vpi_printf((PLI_BYTE8 *)"%s:%d: req %d:%d decl %d:%d for '%s'\n", // __FILE__, __LINE__, *hi_ptr, *lo_ptr, decl_left, decl_right, path); decl_lo = (decl_left < decl_right) ? decl_left : decl_right; decl_hi = (decl_left > decl_right) ? decl_left : decl_right; if (*lo_ptr < decl_lo) return 0; if (*hi_ptr > decl_hi) return 0; *lo_ptr -= decl_lo; *hi_ptr -= decl_lo; } return r; } /* * Given a path, look the path name up using the PLI, * and set it to 'value'. */ static int uvm_hdl_set_vlog(char *path, p_vpi_vecval value, PLI_INT32 flag) { vpiHandle r; s_vpi_value value_s = {vpiIntVal, {0}}; s_vpi_time time_s = {vpiSimTime, 0, 0, 0.0}; int is_partsel, hi, lo; int size; static int s_maxsize = -1; if (flag == vpiForceFlag || flag == vpiReleaseFlag) { // It appears other simulator interfaces likewise don't support this m_uvm_error("UVM/DPI/VLOG_GET", "Unsupported: uvh_hdl_force/uvm_hdl_release on hdl path '%s'", path); return 0; } r = uvm_hdl_handle_by_name_partsel(path, &is_partsel, &hi, &lo); if (r == 0) { m_uvm_error("UVM/DPI/HDL_SET", "set: unable to locate hdl path (%s)\n Either the name is incorrect, " "or you may not have PLI/ACC visibility to that name", path); return 0; } if (!is_partsel) { value_s.format = vpiVectorVal; value_s.value.vector = value; vpi_put_value(r, &value_s, &time_s, flag); } else { if (s_maxsize == -1) s_maxsize = uvm_hdl_max_width(); size = vpi_get(vpiSize, r); if (size > s_maxsize) { m_uvm_error("UVM/DPI/VLOG_PUT", "hdl path '%s' is %0d bits, but the maximum size is %0d. " "You can increase the maximum via a compile-time flag: " "+define+UVM_HDL_MAX_WIDTH=", path, size, s_maxsize); vpi_release_handle(r); return 0; } value_s.format = vpiVectorVal; vpi_get_value(r, &value_s); for (int i = 0; i < (((hi - lo + 1) / 32) + 1); ++i) { int subsize = hi - (lo + (i << 5)) + 1; if (subsize > 32) subsize = 32; svPutPartselLogic(&value_s.value.vector[i], value[i], lo + (i << 5), subsize); } vpi_put_value(r, &value_s, &time_s, flag); } vpi_release_handle(r); return 1; } /* * Given a path, look the path name up using the PLI * and return its 'value'. */ static int uvm_hdl_get_vlog(char *path, p_vpi_vecval value, PLI_INT32 flag, int partsel) { static int s_maxsize = -1; int i, size, chunks; vpiHandle r; s_vpi_value value_s; int is_partsel, hi, lo; r = uvm_hdl_handle_by_name_partsel(path, &is_partsel, &hi, &lo); if (r == 0) { m_uvm_error("UVM/DPI/VLOG_GET", "unable to locate hdl path (%s)\n Either the name is incorrect, or you " "may not have PLI/ACC visibility to that name", path); return 0; } if (s_maxsize == -1) s_maxsize = uvm_hdl_max_width(); size = vpi_get(vpiSize, r); if (size > s_maxsize) { m_uvm_error("UVM/DPI/VLOG_GET", "hdl path '%s' is %0d bits, but the maximum size is %0d. " "You can increase the maximum via a compile-time flag: " "+define+UVM_HDL_MAX_WIDTH=", path, size, s_maxsize); vpi_release_handle(r); return 0; } chunks = (size - 1) / 32 + 1; value_s.format = vpiVectorVal; vpi_get_value(r, &value_s); // Note upper bits are not cleared, other simulators do likewise if (!is_partsel) { // Keep as separate branch as subroutine can potentially inline and highly optimize for (i = 0; i < chunks; ++i) { value[i].aval = value_s.value.vector[i].aval; value[i].bval = value_s.value.vector[i].bval; } } else { // Verilator supports > 32 bit widths, which is an extension to IEEE DPI svGetPartselLogic(value, value_s.value.vector, lo, hi - lo + 1); } // vpi_printf((PLI_BYTE8 *)"uvm_hdl_get_vlog(%s,%0x)\n", path, value[0].aval); vpi_release_handle(r); return 1; } /* * Given a path, look the path name up using the PLI, * but don't set or get. Just check. * * Return 0 if NOT found. * Return 1 if found. */ int uvm_hdl_check_path(char *path) { vpiHandle handle; handle = vpi_handle_by_name(path, 0); return (handle != 0); } /* * Given a path, look the path name up using the PLI * or the FLI, and return its 'value'. */ int uvm_hdl_read(char *path, p_vpi_vecval value) { return uvm_hdl_get_vlog(path, value, vpiNoDelay, 0); } /* * Given a path, look the path name up using the PLI * or the FLI, and set it to 'value'. */ int uvm_hdl_deposit(char *path, p_vpi_vecval value) { return uvm_hdl_set_vlog(path, value, vpiNoDelay); } /* * Given a path, look the path name up using the PLI * or the FLI, and set it to 'value'. */ int uvm_hdl_force(char *path, p_vpi_vecval value) { return uvm_hdl_set_vlog(path, value, vpiForceFlag); } /* * Given a path, look the path name up using the PLI * or the FLI, and release it. */ int uvm_hdl_release_and_read(char *path, p_vpi_vecval value) { return uvm_hdl_set_vlog(path, value, vpiReleaseFlag); } /* * Given a path, look the path name up using the PLI * or the FLI, and release it. */ int uvm_hdl_release(char *path) { s_vpi_vecval value; return uvm_hdl_set_vlog(path, &value, vpiReleaseFlag); } verilator-5.042/test_regress/t/uvm/dpi/uvm_hdl.svh0000644000542200017500000001303415101701376022632 0ustar mahmoudyfreeshell//------------------------------------------------------------ // Copyright 2007-2011 Mentor Graphics Corporation // Copyright 2015 Analog Devices, Inc. // Copyright 2010 Synopsys, Inc. // Copyright 2010-2018 Cadence Design Systems, Inc. // Copyright 2014-2018 NVIDIA Corporation // Copyright 2014 Cisco Systems, Inc. // Copyright 2012 Accellera Systems Initiative // All Rights Reserved Worldwide // // Licensed under the Apache License, Version 2.0 (the // "License"); you may not use this file except in // compliance with the License. You may obtain a copy of // the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in // writing, software distributed under the License is // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // CONDITIONS OF ANY KIND, either express or implied. See // the License for the specific language governing // permissions and limitations under the License. //------------------------------------------------------------ // TITLE -- NODOCS -- UVM HDL Backdoor Access support routines. // // These routines provide an interface to the DPI/PLI // implementation of backdoor access used by registers. // // If you DON'T want to use the DPI HDL API, then compile your // SystemVerilog code with the vlog switch //: vlog ... +define+UVM_HDL_NO_DPI ... // `ifndef UVM_HDL__SVH `define UVM_HDL__SVH `ifndef UVM_HDL_MAX_WIDTH `define UVM_HDL_MAX_WIDTH 1024 `endif /* * VARIABLE -- NODOCS -- UVM_HDL_MAX_WIDTH * Sets the maximum size bit vector for backdoor access. * This parameter will be looked up by the * DPI-C code using: * vpi_handle_by_name( * "uvm_pkg::UVM_HDL_MAX_WIDTH", 0); */ // @uvm-ieee 1800.2-2020 manual 19.6.1 parameter int UVM_HDL_MAX_WIDTH = `UVM_HDL_MAX_WIDTH; typedef logic [UVM_HDL_MAX_WIDTH-1:0] uvm_hdl_data_t; `ifndef UVM_HDL_NO_DPI // Function -- NODOCS -- uvm_hdl_check_path // // Checks that the given HDL ~path~ exists. Returns 0 if NOT found, 1 otherwise. // import "DPI-C" context function int uvm_hdl_check_path(string path); // Function -- NODOCS -- uvm_hdl_deposit // // Sets the given HDL ~path~ to the specified ~value~. // Returns 1 if the call succeeded, 0 otherwise. // import "DPI-C" context function int uvm_hdl_deposit(string path, uvm_hdl_data_t value); // Function -- NODOCS -- uvm_hdl_force // // Forces the ~value~ on the given ~path~. Returns 1 if the call succeeded, 0 otherwise. // import "DPI-C" context function int uvm_hdl_force(string path, uvm_hdl_data_t value); // Function -- NODOCS -- uvm_hdl_force_time // // Forces the ~value~ on the given ~path~ for the specified amount of ~force_time~. // If ~force_time~ is 0, is called. // Returns 1 if the call succeeded, 0 otherwise. // task uvm_hdl_force_time(string path, uvm_hdl_data_t value, time force_time = 0); if (force_time == 0) begin void'(uvm_hdl_deposit(path, value)); return; end if (!uvm_hdl_force(path, value)) return; #force_time; void'(uvm_hdl_release_and_read(path, value)); endtask // Function -- NODOCS -- uvm_hdl_release_and_read // // Releases a value previously set with . // Returns 1 if the call succeeded, 0 otherwise. ~value~ is set to // the HDL value after the release. For 'reg', the value will still be // the forced value until it has been procedurally reassigned. For 'wire', // the value will change immediately to the resolved value of its // continuous drivers, if any. If none, its value remains as forced until // the next direct assignment. // import "DPI-C" context function int uvm_hdl_release_and_read(string path, inout uvm_hdl_data_t value); // Function -- NODOCS -- uvm_hdl_release // // Releases a value previously set with . // Returns 1 if the call succeeded, 0 otherwise. // import "DPI-C" context function int uvm_hdl_release(string path); // Function -- NODOCS -- uvm_hdl_read() // // Gets the value at the given ~path~. // Returns 1 if the call succeeded, 0 otherwise. // import "DPI-C" context function int uvm_hdl_read(string path, output uvm_hdl_data_t value); `else function int uvm_hdl_check_path(string path); uvm_report_fatal("UVM_HDL_CHECK_PATH", $sformatf("uvm_hdl DPI routines are compiled off. Recompile without +define+UVM_HDL_NO_DPI")); return 0; endfunction function int uvm_hdl_deposit(string path, uvm_hdl_data_t value); uvm_report_fatal("UVM_HDL_DEPOSIT", $sformatf("uvm_hdl DPI routines are compiled off. Recompile without +define+UVM_HDL_NO_DPI")); return 0; endfunction function int uvm_hdl_force(string path, uvm_hdl_data_t value); uvm_report_fatal("UVM_HDL_FORCE", $sformatf("uvm_hdl DPI routines are compiled off. Recompile without +define+UVM_HDL_NO_DPI")); return 0; endfunction task uvm_hdl_force_time(string path, uvm_hdl_data_t value, time force_time=0); uvm_report_fatal("UVM_HDL_FORCE_TIME", $sformatf("uvm_hdl DPI routines are compiled off. Recompile without +define+UVM_HDL_NO_DPI")); endtask function int uvm_hdl_release(string path); uvm_report_fatal("UVM_HDL_RELEASE", $sformatf("uvm_hdl DPI routines are compiled off. Recompile without +define+UVM_HDL_NO_DPI")); return 0; endfunction function int uvm_hdl_read(string path, output uvm_hdl_data_t value); uvm_report_fatal("UVM_HDL_READ", $sformatf("uvm_hdl DPI routines are compiled off. Recompile without +define+UVM_HDL_NO_DPI")); return 0; endfunction `endif `endif verilator-5.042/test_regress/t/uvm/dpi/uvm_dpi.cc0000644000542200017500000000420115101701376022420 0ustar mahmoudyfreeshell//---------------------------------------------------------------------- // Copyright 2010-2017 Mentor Graphics Corporation // Copyright 2010-2013 Synopsys, Inc. // Copyright 2010-2018 Cadence Design Systems, Inc. // Copyright 2013 NVIDIA Corporation // All Rights Reserved Worldwide // // Licensed under the Apache License, Version 2.0 (the // "License"); you may not use this file except in // compliance with the License. You may obtain a copy of // the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in // writing, software distributed under the License is // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // CONDITIONS OF ANY KIND, either express or implied. See // the License for the specific language governing // permissions and limitations under the License. //---------------------------------------------------------------------- // // Top-level file that includes all of the C/C++ files required // by UVM // // The C code may be compiled by compiling this top file only, // or by compiling individual files then linking them together. // #ifdef __cplusplus extern "C" { #endif #include #include "uvm_dpi.h" // Avoid -Wmissing-definitions int uvm_re_match(const char * re, const char *str); const char * uvm_glob_to_re(const char *glob); int uvm_hdl_check_path(char *path); int uvm_hdl_read(char *path, p_vpi_vecval value); int uvm_hdl_deposit(char *path, p_vpi_vecval value); int uvm_hdl_force(char *path, p_vpi_vecval value); int uvm_hdl_release_and_read(char *path, p_vpi_vecval value); int uvm_hdl_release(char *path); void push_data(int lvl,char *entry, int cmd); void walk_level(int lvl, int argc, char**argv,int cmd); const char *uvm_dpi_get_next_arg_c (int init); extern char* uvm_dpi_get_tool_name_c (); extern char* uvm_dpi_get_tool_version_c (); extern regex_t* uvm_dpi_regcomp (char* pattern); extern int uvm_dpi_regexec (regex_t* re, char* str); extern void uvm_dpi_regfree (regex_t* re); #include "uvm_common.c" #include "uvm_regex.cc" #include "uvm_hdl.c" #include "uvm_svcmd_dpi.c" #ifdef __cplusplus } #endif verilator-5.042/test_regress/t/uvm/dpi/uvm_dpi.h0000644000542200017500000000533115101701376022267 0ustar mahmoudyfreeshell//---------------------------------------------------------------------- // Copyright 2010-2017 Mentor Graphics Corporation // Copyright 2010 Synopsys, Inc. // Copyright 2010-2018 Cadence Design Systems, Inc. // Copyright 2013 NVIDIA Corporation // All Rights Reserved Worldwide // // Licensed under the Apache License, Version 2.0 (the // "License"); you may not use this file except in // compliance with the License. You may obtain a copy of // the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in // writing, software distributed under the License is // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // CONDITIONS OF ANY KIND, either express or implied. See // the License for the specific language governing // permissions and limitations under the License. //---------------------------------------------------------------------- // // Top level header filke that wraps all requirements which // are common to the various C/C++ files in UVM. // #ifndef UVM_DPI__H #define UVM_DPI__H #include #include "vpi_user.h" #include "veriuser.h" #include "svdpi.h" #include #include #include #include #include // The following consts and method call are for // internal usage by the UVM DPI implementation, // and are not intended for public use. static const int M_UVM_INFO = 0; static const int M_UVM_WARNING = 1; static const int M_UVM_ERROR = 2; static const int M_UVM_FATAL = 3; static const int M_UVM_NONE = 0; static const int M_UVM_LOW = 100; static const int M_UVM_MEDIUM = 200; static const int M_UVM_HIGH = 300; static const int M_UVM_FULL = 400; static const int M_UVM_DEBUG = 500; void m_uvm_report_dpi(int severity, char* id, char* message, int verbosity, char* file, int linenum); int int_str_max( int ); int uvm_re_match(const char * re, const char *str); const char * uvm_glob_to_re(const char *glob); int uvm_hdl_check_path(char *path); int uvm_hdl_read(char *path, p_vpi_vecval value); int uvm_hdl_deposit(char *path, p_vpi_vecval value); int uvm_hdl_force(char *path, p_vpi_vecval value); int uvm_hdl_release_and_read(char *path, p_vpi_vecval value); int uvm_hdl_release(char *path); void push_data(int lvl,char *entry, int cmd); void walk_level(int lvl, int argc, char**argv,int cmd); const char *uvm_dpi_get_next_arg_c (int init); extern char* uvm_dpi_get_tool_name_c (); extern char* uvm_dpi_get_tool_version_c (); extern regex_t* uvm_dpi_regcomp (char* pattern); extern int uvm_dpi_regexec (regex_t* re, char* str); extern void uvm_dpi_regfree (regex_t* re); #endif verilator-5.042/test_regress/t/uvm/dpi/.clang-format0000644000542200017500000000722615101701376023033 0ustar mahmoudyfreeshell--- Language: Cpp # BasedOnStyle: LLVM AccessModifierOffset: -4 AlignAfterOpenBracket: Align AlignConsecutiveAssignments: false AlignConsecutiveDeclarations: false AlignEscapedNewlines: DontAlign AlignOperands: true AlignTrailingComments: false AllowAllParametersOfDeclarationOnNextLine: true AllowShortBlocksOnASingleLine: true AllowShortCaseLabelsOnASingleLine: true AllowShortFunctionsOnASingleLine: All AllowShortIfStatementsOnASingleLine: true AllowShortLoopsOnASingleLine: true AlwaysBreakAfterDefinitionReturnType: None AlwaysBreakAfterReturnType: None AlwaysBreakBeforeMultilineStrings: false AlwaysBreakTemplateDeclarations: true BinPackArguments: true BinPackParameters: true BraceWrapping: AfterClass: false AfterControlStatement: false AfterEnum: false AfterFunction: false AfterNamespace: false AfterObjCDeclaration: false AfterStruct: false AfterUnion: false AfterExternBlock: false BeforeCatch: false BeforeElse: false IndentBraces: false SplitEmptyFunction: true SplitEmptyRecord: true SplitEmptyNamespace: true BreakBeforeBinaryOperators: All BreakBeforeBraces: Attach BreakBeforeInheritanceComma: false BreakBeforeTernaryOperators: true BreakConstructorInitializersBeforeComma: false BreakConstructorInitializers: BeforeComma BreakAfterJavaFieldAnnotations: false BreakStringLiterals: true ColumnLimit: 99 CommentPragmas: '^ IWYU pragma:' CompactNamespaces: false ConstructorInitializerAllOnOneLineOrOnePerLine: false ConstructorInitializerIndentWidth: 2 ContinuationIndentWidth: 2 Cpp11BracedListStyle: true DerivePointerAlignment: false DisableFormat: false ExperimentalAutoDetectBinPacking: false FixNamespaceComments: true ForEachMacros: - Q_FOREACH - BOOST_FOREACH # Include grouping/sorting SortIncludes: true IncludeBlocks: Regroup IncludeCategories: - Regex: '"V3Pch.*\.h"' Priority: -2 # Precompiled headers - Regex: '"(config_build|verilated_config|verilatedos)\.h"' Priority: -1 # Sepecials before main header - Regex: '(<|")verilated.*' Priority: 1 # Runtime headers - Regex: '"V3.*__gen.*\.h"' Priority: 3 # Generated internal headers separately - Regex: '"V3.*"' Priority: 2 # Internal header - Regex: '".*"' Priority: 4 # Other non-system headers - Regex: '<[[:alnum:]_.]+>' Priority: 5 # Simple system headers next - Regex: '<.*>' Priority: 6 # Other system headers next IncludeIsMainRegex: '$' IndentCaseLabels: false IndentPPDirectives: None IndentWidth: 2 IndentWrappedFunctionNames: false JavaScriptQuotes: Leave JavaScriptWrapImports: true KeepEmptyLinesAtTheStartOfBlocks: true MacroBlockBegin: '' MacroBlockEnd: '' MaxEmptyLinesToKeep: 1 NamespaceIndentation: None ObjCBlockIndentWidth: 2 ObjCSpaceAfterProperty: false ObjCSpaceBeforeProtocolList: true PenaltyBreakAssignment: 2 PenaltyBreakBeforeFirstCallParameter: 19 PenaltyBreakComment: 300 PenaltyBreakFirstLessLess: 120 PenaltyBreakString: 1000 PenaltyExcessCharacter: 1000000 PenaltyReturnTypeOnItsOwnLine: 60 PointerAlignment: Right ReflowComments: true SortUsingDeclarations: true SpaceAfterCStyleCast: false SpaceAfterTemplateKeyword: true SpaceBeforeAssignmentOperators: true SpaceBeforeParens: ControlStatements SpaceInEmptyParentheses: false SpacesBeforeTrailingComments: 2 SpacesInAngles: false SpacesInContainerLiterals: true SpacesInCStyleCastParentheses: false SpacesInLineCommentPrefix: Minimum: 0 Maximum: -1 SpacesInParentheses: false SpacesInSquareBrackets: false Standard: Cpp11 TabWidth: 8 UseTab: Never ... verilator-5.042/test_regress/t/uvm/dpi/uvm_hdl.c0000644000542200017500000000245415101701376022260 0ustar mahmoudyfreeshell//---------------------------------------------------------------------- // Copyright 2009-2011 Mentor Graphics Corporation // Copyright 2010-2011 Synopsys, Inc. // Copyright 2007-2018 Cadence Design Systems, Inc. // Copyright 2013 NVIDIA Corporation // All Rights Reserved Worldwide // // Licensed under the Apache License, Version 2.0 (the // "License"); you may not use this file except in // compliance with the License. You may obtain a copy of // the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in // writing, software distributed under the License is // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // CONDITIONS OF ANY KIND, either express or implied. See // the License for the specific language governing // permissions and limitations under the License. //---------------------------------------------------------------------- // hdl vendor backends are defined for VCS,QUESTA,VERILATOR,XCELIUM #if defined(VCS) || defined(VCSMX) #include "uvm_hdl_vcs.c" #else #ifdef QUESTA #include "uvm_hdl_questa.c" #else #ifdef VERILATOR #include "uvm_hdl_verilator.c" #else #if defined(XCELIUM) || defined(NCSC) #include "uvm_hdl_xcelium.c" #else #error "hdl vendor backend is missing" #endif #endif #endif #endif verilator-5.042/test_regress/t/uvm/dpi/uvm_regex.cc0000644000542200017500000001511115101701376022760 0ustar mahmoudyfreeshell//---------------------------------------------------------------------- // Copyright 2007-2011 Mentor Graphics Corporation // Copyright 2010-2018 Cadence Design Systems, Inc. // Copyright 2013-2014 NVIDIA Corporation // All Rights Reserved Worldwide // // Licensed under the Apache License, Version 2.0 (the // "License"); you may not use this file except in // compliance with the License. You may obtain a copy of // the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in // writing, software distributed under the License is // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // CONDITIONS OF ANY KIND, either express or implied. See // the License for the specific language governing // permissions and limitations under the License. //---------------------------------------------------------------------- #include "uvm_dpi.h" #include const char uvm_re_bracket_char = '/'; #define UVM_REGEX_MAX_LENGTH 2048 static char uvm_re[UVM_REGEX_MAX_LENGTH+4]; static const char* empty_regex="/^$/"; //-------------------------------------------------------------------- // uvm_re_match // // Match a string to a regular expression. The regex is first lookup // up in the regex cache to see if it has already been compiled. If // so, the compile version is retrieved from the cache. Otherwise, it // is compiled and cached for future use. After compilation the // matching is done using regexec(). //-------------------------------------------------------------------- int uvm_re_match(const char * re, const char *str) { regex_t *rexp; int err; // safety check. Args should never be ~null~ since this is called // from DPI. But we'll check anyway. if(re == NULL) return 1; if(str == NULL) return 1; int len = strlen(re); char * rex = &uvm_re[0]; if (len > UVM_REGEX_MAX_LENGTH) { const char* err_str = "uvm_re_match : regular expression greater than max %0d: |%s|"; char buffer[strlen(err_str) + int_str_max(10) + strlen(re)]; sprintf(buffer, err_str, UVM_REGEX_MAX_LENGTH, re); m_uvm_report_dpi(M_UVM_ERROR, (char*) "UVM/DPI/REGEX_MAX", &buffer[0], M_UVM_NONE, (char*)__FILE__, __LINE__); return 1; } // we copy the regexp because we need to remove any brackets around it strncpy(&uvm_re[0],re,UVM_REGEX_MAX_LENGTH); if (len>1 && (re[0] == uvm_re_bracket_char) && re[len-1] == uvm_re_bracket_char) { uvm_re[len-1] = '\0'; rex++; } rexp = (regex_t*)malloc(sizeof(regex_t)); if (rexp == NULL) { m_uvm_report_dpi(M_UVM_ERROR, (char*) "UVM/DPI/REGEX_ALLOC", (char*) "uvm_re_match: internal memory allocation error", M_UVM_NONE, (char*)__FILE__, __LINE__); return 1; } err = regcomp(rexp, rex, REG_EXTENDED); if (err != 0) { regerror(err,rexp,uvm_re,UVM_REGEX_MAX_LENGTH-1); const char * err_str = "uvm_re_match : invalid glob or regular expression: |%s||%s|"; char buffer[strlen(err_str) + strlen(re) + strlen(uvm_re)+1]; sprintf(buffer, err_str, re, uvm_re); m_uvm_report_dpi(M_UVM_ERROR, (char*) "UVM/DPI/REGEX_INV", &buffer[0], M_UVM_NONE, (char*)__FILE__, __LINE__); regfree(rexp); free(rexp); return err; } err = regexec(rexp, str, 0, NULL, 0); //vpi_printf((PLI_BYTE8*) "UVM_INFO: uvm_re_match: re=%s str=%s ERR=%0d\n",rex,str,err); regfree(rexp); free(rexp); return err; } //-------------------------------------------------------------------- // uvm_glob_to_re // // Convert a glob expression to a normal regular expression. //-------------------------------------------------------------------- const char * uvm_glob_to_re(const char *glob) { const char *p; int len; // safety check. Glob should never be ~null~ since this is called // from DPI. But we'll check anyway. if(glob == NULL) return NULL; len = strlen(glob); if (len > 2040) { const char * err_str = "uvm_re_match : glob expression greater than max 2040: |%s|"; char buffer[strlen(err_str) + strlen(glob)+1]; sprintf(buffer, err_str, glob); m_uvm_report_dpi(M_UVM_ERROR, (char*) "UVM/DPI/REGEX_MAX", &buffer[0], M_UVM_NONE, (char*)__FILE__, __LINE__); return glob; } // If either of the following cases appear then return an empty string // // 1. The glob string is empty (it has zero characters) // 2. The glob string has a single character that is the // uvm_re_bracket_char (i.e. "/") if(len == 0 || (len == 1 && *glob == uvm_re_bracket_char)) { return empty_regex; } // If bracketed with the /glob/, then it's already a regex if(glob[0] == uvm_re_bracket_char && glob[len-1] == uvm_re_bracket_char) { strcpy(uvm_re,glob); return &uvm_re[0]; } else { // Convert the glob to a true regular expression (Posix syntax) len = 0; uvm_re[len++] = uvm_re_bracket_char; // ^ goes at the beginning... if (*glob != '^') uvm_re[len++] = '^'; for(p = glob; *p; p++) { // Replace the glob metacharacters with corresponding regular // expression metacharacters. switch(*p) { case '*': uvm_re[len++] = '.'; uvm_re[len++] = '*'; break; case '+': uvm_re[len++] = '.'; uvm_re[len++] = '+'; break; case '.': uvm_re[len++] = '\\'; uvm_re[len++] = '.'; break; case '?': uvm_re[len++] = '.'; break; case '[': uvm_re[len++] = '\\'; uvm_re[len++] = '['; break; case ']': uvm_re[len++] = '\\'; uvm_re[len++] = ']'; break; case '(': uvm_re[len++] = '\\'; uvm_re[len++] = '('; break; case ')': uvm_re[len++] = '\\'; uvm_re[len++] = ')'; break; default: uvm_re[len++] = *p; break; } } } // Let's check to see if the regular expression is bounded by ^ at // the beginning and $ at the end. If not, add those characters in // the appropriate position. if (uvm_re[len-1] != '$') uvm_re[len++] = '$'; uvm_re[len++] = uvm_re_bracket_char; uvm_re[len++] = '\0'; return &uvm_re[0]; } verilator-5.042/test_regress/t/uvm/dpi/uvm_svcmd_dpi.svh0000644000542200017500000000412015101701376024027 0ustar mahmoudyfreeshell// //------------------------------------------------------------------------------ // Copyright 2010-2011 Mentor Graphics Corporation // Copyright 2013-2018 Cadence Design Systems, Inc. // Copyright 2010-2012 AMD // All Rights Reserved Worldwide // // Licensed under the Apache License, Version 2.0 (the // "License"); you may not use this file except in // compliance with the License. You may obtain a copy of // the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in // writing, software distributed under the License is // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // CONDITIONS OF ANY KIND, either express or implied. See // the License for the specific language governing // permissions and limitations under the License. //------------------------------------------------------------------------------ // Import DPI functions used by the interface to generate the // lists. `ifndef UVM_CMDLINE_NO_DPI import "DPI-C" function string uvm_dpi_get_next_arg_c (int init); import "DPI-C" function string uvm_dpi_get_tool_name_c (); import "DPI-C" function string uvm_dpi_get_tool_version_c (); function string uvm_dpi_get_next_arg(int init=0); return uvm_dpi_get_next_arg_c(init); endfunction function string uvm_dpi_get_tool_name(); return uvm_dpi_get_tool_name_c(); endfunction function string uvm_dpi_get_tool_version(); return uvm_dpi_get_tool_version_c(); endfunction import "DPI-C" function chandle uvm_dpi_regcomp(string regex); import "DPI-C" function int uvm_dpi_regexec(chandle preg, string str); import "DPI-C" function void uvm_dpi_regfree(chandle preg); `else function string uvm_dpi_get_next_arg(int init=0); return ""; endfunction function string uvm_dpi_get_tool_name(); return "?"; endfunction function string uvm_dpi_get_tool_version(); return "?"; endfunction function chandle uvm_dpi_regcomp(string regex); return null; endfunction function int uvm_dpi_regexec(chandle preg, string str); return 0; endfunction function void uvm_dpi_regfree(chandle preg); endfunction `endif verilator-5.042/test_regress/t/uvm/dpi/uvm_regex.svh0000644000542200017500000000435715101701376023205 0ustar mahmoudyfreeshell//---------------------------------------------------------------------- // Copyright 2010-2012 Mentor Graphics Corporation // Copyright 2010-2018 Cadence Design Systems, Inc. // All Rights Reserved Worldwide // // Licensed under the Apache License, Version 2.0 (the // "License"); you may not use this file except in // compliance with the License. You may obtain a copy of // the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in // writing, software distributed under the License is // distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // CONDITIONS OF ANY KIND, either express or implied. See // the License for the specific language governing // permissions and limitations under the License. //---------------------------------------------------------------------- `ifndef UVM_REGEX_NO_DPI import "DPI-C" context function int uvm_re_match(string re, string str); import "DPI-C" context function string uvm_glob_to_re(string glob); `else // The Verilog only version does not match regular expressions, // it only does glob style matching. function int uvm_re_match(string re, string str); int e, es, s, ss; string tmp; e = 0; s = 0; es = 0; ss = 0; if(re.len() == 0) return 0; // The ^ used to be used to remove the implicit wildcard, but now we don't // use implicit wildcard so this character is just stripped. if(re[0] == "^") re = re.substr(1, re.len()-1); //This loop is only needed when the first character of the re may not //be a *. while (s != str.len() && re.getc(e) != "*") begin if ((re.getc(e) != str.getc(s)) && (re.getc(e) != "?")) return 1; e++; s++; end while (s != str.len()) begin if (re.getc(e) == "*") begin e++; if (e == re.len()) begin return 0; end es = e; ss = s+1; end else if (re.getc(e) == str.getc(s) || re.getc(e) == "?") begin e++; s++; end else begin e = es; s = ss++; end end while (e < re.len() && re.getc(e) == "*") e++; if(e == re.len()) begin return 0; end else begin return 1; end endfunction function string uvm_glob_to_re(string glob); return glob; endfunction `endif verilator-5.042/test_regress/t/t_param_width.v0000644000542200017500000000156715101701376022110 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2016 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // See issue #1991 module t (/*AUTOARG*/ // Inputs clk ); input clk; socket #(3'b000) s0(); socket #(3'b010) s1(); socket #(2'b10) s2(); socket #(2'b11) s3(); always_ff @ (posedge clk) begin if (s0.ADDR != 0) $stop; if (s1.ADDR != 2) $stop; if (s2.ADDR != 2) $stop; if (s3.ADDR != 3) $stop; if ($bits(s0.ADDR) != 3) $stop; if ($bits(s1.ADDR) != 3) $stop; if ($bits(s2.ADDR) != 2) $stop; if ($bits(s3.ADDR) != 2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module socket #(ADDR)(); initial $display("bits %0d, addr %b", $bits(ADDR), ADDR); endmodule verilator-5.042/test_regress/t/t_constraint_unpacked_array.py0000755000542200017500000000104615101701376025223 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_case_66bits_no_const_eager.py0000755000542200017500000000104315101701376025141 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_case_66bits.v" test.compile(verilator_flags2=['-fno-const-eager']) test.execute() test.passes() verilator-5.042/test_regress/t/t_order_quad.v0000644000542200017500000000100215101701376021716 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // See issue #762 module t(a0, y); input [3:0] a0; // verilator lint_off UNOPTFLAT output [44:0] y; assign y[40] = 0; assign y[30] = 0; assign { y[44:41], y[39:31], y[29:0] } = { 6'b000000, a0, 7'b0000000, y[40], y[30], y[30], y[30], y[30], 21'b000000000000000000000 }; endmodule verilator-5.042/test_regress/t/t_chg_first.v0000644000542200017500000000354515101701376021557 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk, fastclk ); input clk; input fastclk; // surefire lint_off_line UDDIXN integer _mode; initial _mode=0; reg [31:0] ord1; initial ord1 = 32'h1111; wire [31:0] ord2; reg [31:0] ord3; wire [31:0] ord4; wire [31:0] ord5; wire [31:0] ord6; wire [31:0] ord7; // verilator lint_off UNOPT t_chg_a a ( .a(ord1), .a_p1(ord2), .b(ord4), .b_p1(ord5), .c(ord3), .c_p1(ord4), .d(ord6), .d_p1(ord7) ); // surefire lint_off ASWEMB assign ord6 = ord5 + 1; // verilator lint_on UNOPT always @ (/*AS*/ord2) ord3 = ord2 + 1; always @ (fastclk) begin // surefire lint_off_line ALWLTR ALWMTR if (_mode==1) begin //$write("[%0t] t_chg: %d: Values: %x %x %x %x %x %x %x\n", $time,fastclk,ord1,ord2,ord3,ord4,ord5,ord6,ord7); //if (ord2 == 2 && ord7 != 7) $stop; end end always @ (posedge clk) begin if (_mode==0) begin $write("[%0t] t_chg: Running\n", $time); _mode<=1; ord1 <= 1; end else if (_mode==1) begin _mode<=2; if (ord7 !== 7) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module t_chg_a (/*AUTOARG*/ // Outputs a_p1, b_p1, c_p1, d_p1, // Inputs a, b, c, d ); input [31:0] a; output [31:0] a_p1; wire [31:0] a_p1 = a + 1; input [31:0] b; output [31:0] b_p1; wire [31:0] b_p1 = b + 1; input [31:0] c; output [31:0] c_p1; wire [31:0] c_p1 = c + 1; input [31:0] d; output [31:0] d_p1; wire [31:0] d_p1 = d + 1; endmodule verilator-5.042/test_regress/t/t_vlcov_opt_user.info.out0000644000542200017500000000460215101701376024147 0ustar mahmoudyfreeshellTN:verilator_coverage SF:t/t_assert_ctl_arg.v DA:49,1 BRDA:49,0,0,1 BRDA:49,0,1,1 BRDA:49,0,2,0 BRDA:49,0,3,0 BRDA:49,0,4,0 BRDA:49,0,5,0 DA:51,0 BRDA:51,0,0,0 BRDA:51,0,1,0 BRDA:51,0,2,0 BRDA:51,0,3,0 BRDA:51,0,4,0 BRDA:51,0,5,0 DA:56,1 BRDA:56,0,0,0 BRDA:56,0,1,0 BRDA:56,0,2,0 BRDA:56,0,3,1 BRDA:56,0,4,0 BRDA:56,0,5,1 DA:58,0 BRDA:58,0,0,0 BRDA:58,0,1,0 BRDA:58,0,2,0 BRDA:58,0,3,0 BRDA:58,0,4,0 BRDA:58,0,5,0 DA:63,1 BRDA:63,0,0,0 BRDA:63,0,1,0 BRDA:63,0,2,1 BRDA:63,0,3,0 BRDA:63,0,4,1 BRDA:63,0,5,0 DA:65,0 BRDA:65,0,0,0 BRDA:65,0,1,0 BRDA:65,0,2,0 BRDA:65,0,3,0 BRDA:65,0,4,0 BRDA:65,0,5,0 DA:69,0 BRDA:69,0,0,0 BRDA:69,0,1,0 BRDA:69,0,2,0 BRDA:69,0,3,0 BRDA:69,0,4,0 BRDA:69,0,5,0 DA:71,1 BRDA:71,0,0,1 BRDA:71,0,1,1 BRDA:71,0,2,1 BRDA:71,0,3,1 BRDA:71,0,4,1 BRDA:71,0,5,1 DA:73,0 BRDA:73,0,0,0 BRDA:73,0,1,0 BRDA:73,0,2,0 BRDA:73,0,3,0 BRDA:73,0,4,0 BRDA:73,0,5,0 DA:76,1 BRDA:76,0,0,1 BRDA:76,0,1,1 BRDA:76,0,2,0 BRDA:76,0,3,1 BRDA:76,0,4,0 BRDA:76,0,5,1 DA:78,1 BRDA:78,0,0,1 BRDA:78,0,1,1 BRDA:78,0,2,1 BRDA:78,0,3,1 BRDA:78,0,4,1 BRDA:78,0,5,1 DA:80,1 BRDA:80,0,0,1 BRDA:80,0,1,1 BRDA:80,0,2,0 BRDA:80,0,3,0 BRDA:80,0,4,0 BRDA:80,0,5,0 DA:82,1 BRDA:82,0,0,1 BRDA:82,0,1,1 BRDA:82,0,2,0 BRDA:82,0,3,0 BRDA:82,0,4,0 BRDA:82,0,5,0 DA:84,0 BRDA:84,0,0,0 BRDA:84,0,1,0 BRDA:84,0,2,0 BRDA:84,0,3,0 BRDA:84,0,4,0 BRDA:84,0,5,0 DA:86,1 BRDA:86,0,0,1 BRDA:86,0,1,1 BRDA:86,0,2,0 BRDA:86,0,3,0 BRDA:86,0,4,0 BRDA:86,0,5,0 DA:88,0 BRDA:88,0,0,0 BRDA:88,0,1,0 BRDA:88,0,2,0 BRDA:88,0,3,0 BRDA:88,0,4,0 BRDA:88,0,5,0 DA:90,1 BRDA:90,0,0,1 BRDA:90,0,1,1 BRDA:90,0,2,1 BRDA:90,0,3,1 BRDA:90,0,4,1 BRDA:90,0,5,1 DA:92,0 BRDA:92,0,0,0 BRDA:92,0,1,0 BRDA:92,0,2,0 BRDA:92,0,3,0 BRDA:92,0,4,0 BRDA:92,0,5,0 DA:97,0 BRDA:97,0,0,0 BRDA:97,0,1,0 BRDA:97,0,2,0 BRDA:97,0,3,0 BRDA:97,0,4,0 BRDA:97,0,5,0 DA:100,1 BRDA:100,0,0,1 BRDA:100,0,1,1 BRDA:100,0,2,1 BRDA:100,0,3,1 BRDA:100,0,4,1 BRDA:100,0,5,1 DA:103,0 BRDA:103,0,0,0 BRDA:103,0,1,0 BRDA:103,0,2,0 BRDA:103,0,3,0 BRDA:103,0,4,0 BRDA:103,0,5,0 DA:106,1 BRDA:106,0,0,1 BRDA:106,0,1,1 BRDA:106,0,2,1 BRDA:106,0,3,1 BRDA:106,0,4,1 BRDA:106,0,5,1 DA:108,1 BRDA:108,0,0,1 BRDA:108,0,1,1 BRDA:108,0,2,1 BRDA:108,0,3,1 BRDA:108,0,4,1 BRDA:108,0,5,1 DA:110,0 BRDA:110,0,0,0 BRDA:110,0,1,0 BRDA:110,0,2,0 BRDA:110,0,3,0 BRDA:110,0,4,0 BRDA:110,0,5,0 DA:112,1 BRDA:112,0,0,1 BRDA:112,0,1,1 BRDA:112,0,2,1 BRDA:112,0,3,0 BRDA:112,0,4,1 BRDA:112,0,5,0 DA:192,0 DA:193,0 BRF:150 BRH:0 end_of_record verilator-5.042/test_regress/t/t_enum_large_methods.v0000644000542200017500000000272315101701376023445 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t (/*AUTOARG*/ // Inputs clk ); input clk; typedef enum { E01 = 'h1, ELARGE = 'hf00d } my_t; integer cyc = 0; my_t e; string all; // Check runtime always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==0) begin // Setup e <= E01; end else if (cyc==1) begin `checks(e.name, "E01"); `checkh(e.next, ELARGE); e <= ELARGE; end else if (cyc==3) begin `checks(e.name, "ELARGE"); `checkh(e.next, E01); `checkh(e.prev, E01); e <= E01; end else if (cyc==20) begin e <= my_t'('h11); // Unknown end else if (cyc==21) begin `checks(e.name, ""); // Unknown end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_genvar_for_bad.out0000644000542200017500000000221215101701376023075 0ustar mahmoudyfreeshell%Error: t/t_genvar_for_bad.v:23:12: Genvar 'i' used outside generate for loop (IEEE 1800-2023 27.4) 23 | for (i = 0; i < N; i = i + 1) begin | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_genvar_for_bad.v:23:19: Genvar 'i' used outside generate for loop (IEEE 1800-2023 27.4) 23 | for (i = 0; i < N; i = i + 1) begin | ^ %Error: t/t_genvar_for_bad.v:24:21: Genvar 'i' used outside generate for loop (IEEE 1800-2023 27.4) 24 | ov[i] <= iv[i]; | ^ %Error: t/t_genvar_for_bad.v:24:12: Genvar 'i' used outside generate for loop (IEEE 1800-2023 27.4) 24 | ov[i] <= iv[i]; | ^ %Error: t/t_genvar_for_bad.v:23:30: Genvar 'i' used outside generate for loop (IEEE 1800-2023 27.4) 23 | for (i = 0; i < N; i = i + 1) begin | ^ %Error: t/t_genvar_for_bad.v:23:26: Genvar 'i' used outside generate for loop (IEEE 1800-2023 27.4) 23 | for (i = 0; i < N; i = i + 1) begin | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_param_hier_bad.py0000755000542200017500000000143415101701376022705 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.extract(in_filename=test.top_filename, out_filename=test.root + "/docs/gen/ex_HIERPARAM_faulty.rst", lines="34-36") test.extract(in_filename=test.golden_filename, out_filename=test.root + "/docs/gen/ex_HIERPARAM_msg.rst", lines="1-4") test.passes() verilator-5.042/test_regress/t/t_trace_cat_reopen.out0000644000542200017500000001745015101701376023446 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $date Sat Feb 23 20:18:07 2013 $end $timescale 1ps $end $scope module top $end $var wire 1 $ clk $end $scope module t $end $var wire 1 $ clk $end $var wire 32 # cyc [31:0] $end $upscope $end $upscope $end $enddefinitions $end #0 b00000000000000000000000000000001 # 1$ #1 0$ #2 b00000000000000000000000000000010 # 1$ #3 0$ #4 b00000000000000000000000000000011 # 1$ #5 0$ #6 b00000000000000000000000000000100 # 1$ #7 0$ #8 b00000000000000000000000000000101 # 1$ #9 0$ #10 b00000000000000000000000000000110 # 1$ #11 0$ #12 b00000000000000000000000000000111 # 1$ #13 0$ #14 b00000000000000000000000000001000 # 1$ #15 0$ #16 b00000000000000000000000000001001 # 1$ #17 0$ #18 b00000000000000000000000000001010 # 1$ #19 0$ #20 b00000000000000000000000000001011 # 1$ #21 0$ #22 b00000000000000000000000000001100 # 1$ #23 0$ #24 b00000000000000000000000000001101 # 1$ #25 0$ #26 b00000000000000000000000000001110 # 1$ #27 0$ #28 b00000000000000000000000000001111 # 1$ #29 0$ #30 b00000000000000000000000000010000 # 1$ #31 0$ #32 b00000000000000000000000000010001 # 1$ #33 0$ #34 b00000000000000000000000000010010 # 1$ #35 0$ #36 b00000000000000000000000000010011 # 1$ #37 0$ #38 b00000000000000000000000000010100 # 1$ #39 0$ #40 b00000000000000000000000000010101 # 1$ #41 0$ #42 b00000000000000000000000000010110 # 1$ #43 0$ #44 b00000000000000000000000000010111 # 1$ #45 0$ #46 b00000000000000000000000000011000 # 1$ #47 0$ #48 b00000000000000000000000000011001 # 1$ #49 0$ #50 b00000000000000000000000000011010 # 1$ #51 0$ #52 b00000000000000000000000000011011 # 1$ #53 0$ #54 b00000000000000000000000000011100 # 1$ #55 0$ #56 b00000000000000000000000000011101 # 1$ #57 0$ #58 b00000000000000000000000000011110 # 1$ #59 0$ #60 b00000000000000000000000000011111 # 1$ #61 0$ #62 b00000000000000000000000000100000 # 1$ #63 0$ #64 b00000000000000000000000000100001 # 1$ #65 0$ #66 b00000000000000000000000000100010 # 1$ #67 0$ #68 b00000000000000000000000000100011 # 1$ #69 0$ #70 b00000000000000000000000000100100 # 1$ #71 0$ #72 b00000000000000000000000000100101 # 1$ #73 0$ #74 b00000000000000000000000000100110 # 1$ #75 0$ #76 b00000000000000000000000000100111 # 1$ #77 0$ #78 b00000000000000000000000000101000 # 1$ #79 0$ #80 b00000000000000000000000000101001 # 1$ #81 0$ #82 b00000000000000000000000000101010 # 1$ #83 0$ #84 b00000000000000000000000000101011 # 1$ #85 0$ #86 b00000000000000000000000000101100 # 1$ #87 0$ #88 b00000000000000000000000000101101 # 1$ #89 0$ #90 b00000000000000000000000000101110 # 1$ #91 0$ #92 b00000000000000000000000000101111 # 1$ #93 0$ #94 b00000000000000000000000000110000 # 1$ #95 0$ #96 b00000000000000000000000000110001 # 1$ #97 0$ #98 b00000000000000000000000000110010 # 1$ #99 0$ #100 b00000000000000000000000000110011 # 1$ #101 0$ #102 b00000000000000000000000000110100 # 1$ #103 0$ #104 b00000000000000000000000000110101 # 1$ #105 0$ #106 b00000000000000000000000000110110 # 1$ #107 0$ #108 b00000000000000000000000000110111 # 1$ #109 0$ #110 b00000000000000000000000000111000 # 1$ #111 0$ #112 b00000000000000000000000000111001 # 1$ #113 0$ #114 b00000000000000000000000000111010 # 1$ #115 0$ #116 b00000000000000000000000000111011 # 1$ #117 0$ #118 b00000000000000000000000000111100 # 1$ #119 0$ #120 b00000000000000000000000000111101 # 1$ #121 0$ #122 b00000000000000000000000000111110 # 1$ #123 0$ #124 b00000000000000000000000000111111 # 1$ #125 0$ #126 b00000000000000000000000001000000 # 1$ #127 0$ #128 b00000000000000000000000001000001 # 1$ #129 0$ #130 b00000000000000000000000001000010 # 1$ #131 0$ #132 b00000000000000000000000001000011 # 1$ #133 0$ #134 b00000000000000000000000001000100 # 1$ #135 0$ #136 b00000000000000000000000001000101 # 1$ #137 0$ #138 b00000000000000000000000001000110 # 1$ #139 0$ #140 b00000000000000000000000001000111 # 1$ #141 0$ #142 b00000000000000000000000001001000 # 1$ #143 0$ #144 b00000000000000000000000001001001 # 1$ #145 0$ #146 b00000000000000000000000001001010 # 1$ #147 0$ #148 b00000000000000000000000001001011 # 1$ #149 0$ #150 b00000000000000000000000001001100 # 1$ #151 0$ #152 b00000000000000000000000001001101 # 1$ #153 0$ #154 b00000000000000000000000001001110 # 1$ #155 0$ #156 b00000000000000000000000001001111 # 1$ #157 0$ #158 b00000000000000000000000001010000 # 1$ #159 0$ #160 b00000000000000000000000001010001 # 1$ #161 0$ #162 b00000000000000000000000001010010 # 1$ #163 0$ #164 b00000000000000000000000001010011 # 1$ #165 0$ #166 b00000000000000000000000001010100 # 1$ #167 0$ #168 b00000000000000000000000001010101 # 1$ #169 0$ #170 b00000000000000000000000001010110 # 1$ #171 0$ #172 b00000000000000000000000001010111 # 1$ #173 0$ #174 b00000000000000000000000001011000 # 1$ #175 0$ #176 b00000000000000000000000001011001 # 1$ #177 0$ #178 b00000000000000000000000001011010 # 1$ #179 0$ #180 b00000000000000000000000001011011 # 1$ #181 0$ #182 b00000000000000000000000001011100 # 1$ #183 0$ #184 b00000000000000000000000001011101 # 1$ #185 0$ #186 b00000000000000000000000001011110 # 1$ #187 0$ #188 b00000000000000000000000001011111 # 1$ #189 0$ #190 b00000000000000000000000001100000 # 1$ #191 0$ #192 b00000000000000000000000001100001 # 1$ #193 0$ #194 b00000000000000000000000001100010 # 1$ #195 0$ #196 b00000000000000000000000001100011 # 1$ #197 0$ #198 b00000000000000000000000001100100 # 1$ #199 0$ #200 b00000000000000000000000001100101 # 1$ #201 0$ #202 b00000000000000000000000001100110 # 1$ #203 0$ #204 b00000000000000000000000001100111 # 1$ #205 0$ #206 b00000000000000000000000001101000 # 1$ #207 0$ #208 b00000000000000000000000001101001 # 1$ #209 0$ #210 b00000000000000000000000001101010 # 1$ #211 0$ #212 b00000000000000000000000001101011 # 1$ #213 0$ #214 b00000000000000000000000001101100 # 1$ #215 0$ #216 b00000000000000000000000001101101 # 1$ #217 0$ #218 b00000000000000000000000001101110 # 1$ #219 0$ #220 b00000000000000000000000001101111 # 1$ #221 0$ #222 b00000000000000000000000001110000 # 1$ #223 0$ #224 b00000000000000000000000001110001 # 1$ #225 0$ #226 b00000000000000000000000001110010 # 1$ #227 0$ #228 b00000000000000000000000001110011 # 1$ #229 0$ #230 b00000000000000000000000001110100 # 1$ #231 0$ #232 b00000000000000000000000001110101 # 1$ #233 0$ #234 b00000000000000000000000001110110 # 1$ #235 0$ #236 b00000000000000000000000001110111 # 1$ #237 0$ #238 b00000000000000000000000001111000 # 1$ #239 0$ #240 b00000000000000000000000001111001 # 1$ #241 0$ #242 b00000000000000000000000001111010 # 1$ #243 0$ #244 b00000000000000000000000001111011 # 1$ #245 0$ #246 b00000000000000000000000001111100 # 1$ #247 0$ #248 b00000000000000000000000001111101 # 1$ #249 0$ #250 b00000000000000000000000001111110 # 1$ #251 0$ #252 b00000000000000000000000001111111 # 1$ #253 0$ #254 b00000000000000000000000010000000 # 1$ #255 0$ #256 b00000000000000000000000010000001 # 1$ #257 0$ #258 b00000000000000000000000010000010 # 1$ #259 0$ #260 b00000000000000000000000010000011 # 1$ #261 0$ #262 b00000000000000000000000010000100 # 1$ #263 0$ #264 b00000000000000000000000010000101 # 1$ #265 0$ #266 b00000000000000000000000010000110 # 1$ #267 0$ #268 b00000000000000000000000010000111 # 1$ #269 0$ #270 b00000000000000000000000010001000 # 1$ #271 0$ #272 b00000000000000000000000010001001 # 1$ #273 0$ #274 b00000000000000000000000010001010 # 1$ #275 0$ #276 b00000000000000000000000010001011 # 1$ #277 0$ #278 b00000000000000000000000010001100 # 1$ #279 0$ #280 b00000000000000000000000010001101 # 1$ #281 0$ #282 b00000000000000000000000010001110 # 1$ #283 0$ #284 b00000000000000000000000010001111 # 1$ #285 0$ #286 b00000000000000000000000010010000 # 1$ #287 0$ #288 b00000000000000000000000010010001 # 1$ #289 0$ #290 b00000000000000000000000010010010 # 1$ #291 0$ #292 b00000000000000000000000010010011 # 1$ #293 0$ #294 b00000000000000000000000010010100 # 1$ #295 0$ #296 b00000000000000000000000010010101 # 1$ #297 0$ #298 b00000000000000000000000010010110 # 1$ #299 0$ verilator-5.042/test_regress/t/t_string_byte.v0000644000542200017500000000145615101701376022137 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t; // Unpacked byte from string IEEE 1800-2023 5.9 byte bh[3:0] = "hi2"; byte bl[0:3] = "lo2"; initial begin `checkh(bh[0], "2"); `checkh(bh[1], "i"); `checkh(bh[2], "h"); `checkh(bh[3], 0); `checkh(bl[0], 0); `checkh(bl[1], "l"); `checkh(bl[2], "o"); `checkh(bl[3], "2"); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_clocking_sched_timing.py0000755000542200017500000000112415101701376024272 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_clocking_sched.v" test.compile(timing_loop=True, verilator_flags2=["--timing"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_tri_no_top.py0000755000542200017500000000114615101701376022144 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile( make_top_shell=False, make_main=False, verilator_flags2=["--binary --pins-inout-enables", test.t_dir + "/t_tri_top_en_out.v"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_unpacked_concat_bad.out0000644000542200017500000000150215101701376024067 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_unpacked_concat_bad.v:12:46: Unsupported: Non-1 replication to form 'bit[31:0]$[1:0]' data type : ... note: In instance 't' 12 | localparam bit_int_t count_bits [1:0] = {2{$bits(count_t)}}; | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: t/t_unpacked_concat_bad.v:12:46: Assignment pattern missed initializing elements: 0 : ... note: In instance 't' 12 | localparam bit_int_t count_bits [1:0] = {2{$bits(count_t)}}; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_cover_line_tri_gate_cond.py0000755000542200017500000000140415101701376024773 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_tri_gate.cpp" test.top_filename = "t/t_tri_gate.v" test.compile(make_top_shell=False, make_main=False, v_flags2=['+define+T_COND'], make_flags=['CPPFLAGS_ADD=-DT_COND'], verilator_flags2=["--exe", test.pli_filename, "--coverage-line"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_impure_cond_empty_if.py0000755000542200017500000000073415101701376024172 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_assoc_wildcard_map.out0000644000542200017500000000060415101701376023760 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_assoc_wildcard_map.v:17:15: Unsupported: Wildcard array 'map' method (IEEE 1800-2023 7.12.5) : ... note: In instance 't' 17 | res = a.map(el) with (el == 2); | ^~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_inst_dtree_inld.py0000755000542200017500000000107515101701376023137 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_inst_dtree.v" test.compile(v_flags2=['+define+INLINE_D'], verilator_flags2=['-trace']) test.execute() test.passes() verilator-5.042/test_regress/t/t_opt_const_red.v0000644000542200017500000002603115101701376022444 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) logic a1; // From test of Test.v logic a10; // From test of Test.v logic a11; // From test of Test.v logic a2; // From test of Test.v logic a3; // From test of Test.v logic a4; // From test of Test.v logic a5; // From test of Test.v logic a6; // From test of Test.v logic a7; // From test of Test.v logic a8; // From test of Test.v logic a9; // From test of Test.v logic o1; // From test of Test.v logic o10; // From test of Test.v logic o11; // From test of Test.v logic o2; // From test of Test.v logic o3; // From test of Test.v logic o4; // From test of Test.v logic o5; // From test of Test.v logic o6; // From test of Test.v logic o7; // From test of Test.v logic o8; // From test of Test.v logic o9; // From test of Test.v logic x1; // From test of Test.v logic x2; // From test of Test.v logic x3; // From test of Test.v logic x4; // From test of Test.v logic x5; // From test of Test.v logic x6; // From test of Test.v logic x7; // From test of Test.v logic x8; // From test of Test.v logic x9; // From test of Test.v logic z1; // From test of Test.v logic z2; // From test of Test.v logic z3; // From test of Test.v logic z4; // From test of Test.v logic z5; // From test of Test.v logic z6; // From test of Test.v logic z7; // From test of Test.v // End of automatics wire [15:0] vec_i = crc[15:0]; wire [31:0] i = crc[31:0]; logic b8_i; logic b12_i; logic match1_o; logic match2_o; Test test(/*AUTOINST*/ // Outputs .a1 (a1), .a2 (a2), .a3 (a3), .a4 (a4), .a5 (a5), .a6 (a6), .a7 (a7), .a8 (a8), .a9 (a9), .a10 (a10), .a11 (a11), .o1 (o1), .o2 (o2), .o3 (o3), .o4 (o4), .o5 (o5), .o6 (o6), .o7 (o7), .o8 (o8), .o9 (o9), .o10 (o10), .o11 (o11), .x1 (x1), .x2 (x2), .x3 (x3), .x4 (x4), .x5 (x5), .x6 (x6), .x7 (x7), .x8 (x8), .x9 (x9), .z1 (z1), .z2 (z2), .z3 (z3), .z4 (z4), .z5 (z5), .z6 (z6), .z7 (z7), // Inputs .clk (clk), .i (i[31:0])); match i_match( .vec_i ( i[15:0] ), .b8_i ( b8_i ), .b12_i ( b12_i ), .match1_o ( match1_o ), .match2_o ( match2_o ) ); // Aggregate outputs into a single result vector // verilator lint_off WIDTH wire [63:0] result = {a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11, o1,o2,o3,o4,o5,o6,o7,o8,o9,o10,o11, x1,x2,x3,x4,x5,x6,x7,x8,x9}; // verilator lint_on WIDTH // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); $display("a %b %b %b %b %b %b %b %b %b %b %b", a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11); $display("o %b %b %b %b %b %b %b %b %b %b %b", o1, o2, o3, o4, o5, o6, o7, o8, o9, o10, o11); $display("x %b %b %b %b %b %b %b %b %b", x1, x2, x3, x4, x5, x6, x7, x8, x9); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc == 0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; b8_i <= 1'b0; b12_i <= 1'b0; end else if (cyc < 10) begin sum <= '0; end else if (cyc < 99) begin if (a1 != a2) $stop; if (a1 != a3) $stop; if (a1 != a4) $stop; if (a1 != a5) $stop; if (a6 != a7) $stop; if (a8 != a9) $stop; if (o1 != o2) $stop; if (o1 != o3) $stop; if (o1 != o4) $stop; if (o1 != o5) $stop; if (o6 != o7) $stop; if (o8 != o9) $stop; if (x1 != x2) $stop; if (x1 != x3) $stop; if (x1 != x4) $stop; if (x1 != x5) $stop; if (x1 != x6) $stop; if (x1 != x7) $stop; if (z1 != '0) $stop; if (z2 != '1) $stop; if (z3 != '0) $stop; if (z4 != '0) $stop; if (z5 != '1) $stop; if (z6 != '1) $stop; if (z7 != '0) $stop; if (match1_o != match2_o) begin $write("[%0t] cyc==%0d m1=%d != m2=%d\n", $time, cyc, match1_o, match2_o); $stop; end end else begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h727fb78d09c1981e if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test(/*AUTOARG*/ // Outputs a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, o1, o2, o3, o4, o5, o6, o7, o8, o9, o10, o11, x1, x2, x3, x4, x5, x6, x7, x8, x9, z1, z2, z3, z4, z5, z6, z7, // Inputs clk, i ); input clk; input [31:0] i; output logic a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11; output logic o1, o2, o3, o4, o5, o6, o7, o8, o9, o10, o11; output logic x1, x2, x3, x4, x5, x6, x7, x8, x9; output logic z1, z2, z3, z4, z5, z6, z7; logic [127:0] d; logic [17:0] e; always_ff @(posedge clk) d <= {i, ~i, ~i, i}; always_ff @(posedge clk) e <= i[17:00]; always_ff @(posedge clk) begin a1 <= (i[5] & ~i[3] & i[1]); a2 <= (i[5]==1 & i[3]==0 & i[1]==1); a3 <= &{i[5], ~i[3], i[1]}; a4 <= ((i & 32'b101010) == 32'b100010); a5 <= ((i & 32'b001010) == 32'b000010) & i[5]; a6 <= &i[5:3]; a7 <= i[5] & i[4] & i[3] & i[5] & i[4]; a8 <= &(~i[5:3]); a9 <= ~i[5] & !i[4] & !i[3] && ~i[5] && !i[4]; a10 <= ~(i[5] & ~d[3]) & (!i[5] & d[1]); // cannot be optimized a11 <= d[0] & d[33] & d[66] & d[99] & !d[31] & !d[62] & !d[93] & !d[124] & e[0] & !e[1] & e[2]; // o1 <= (~i[5] | i[3] | ~i[1]); o2 <= (i[5]!=1 | i[3]!=0 | i[1]!=1); o3 <= |{~i[5], i[3], ~i[1]}; o4 <= ((i & 32'b101010) != 32'b100010); o5 <= ((i & 32'b001010) != 32'b000010) | !i[5]; o6 <= |i[5:3]; o7 <= i[5] | i[4] | i[3] | i[5] | i[4]; o8 <= |(~i[5:3]); o9 <= ~i[5] | !i[4] | ~i[3] || !i[5] || ~i[4]; o10 <= ~(~i[5] | d[3]) | (i[5] | ~d[1]); // cannot be optimized o11 <= d[0] | d[33] | d[66] | d[99] | !d[31] | !d[62] | !d[93] | !d[124] | e[0] | !e[1] | e[2]; // x1 <= (i[5] ^ ~i[3] ^ i[1]); x2 <= (i[5]==1 ^ i[3]==0 ^ i[1]==1); x3 <= ^{i[5], ~i[3], i[1]}; x4 <= ^((i & 32'b101010) ^ 32'b001000); x5 <= ^((i & 32'b001010) ^ 32'b001000) ^ i[5]; x6 <= i[5] ^ ~i[3] ^ i[1] ^ i[3] ^ !i[1] ^ i[3] ^ ~i[1]; x7 <= i[5] ^ (^((i & 32'b001010) ^ 32'b001000)); x8 <= ~(~i[5] ^ d[3]) ^ (i[5] ^ ~d[1]); x9 <= d[0] ^ d[33] ^ d[66] ^ d[99] ^ !d[31] ^ !d[62] ^ !d[93] ^ !d[124] ^ e[0] ^ !e[1] ^ e[2]; // // All zero/all one cases z1 <= (i[5] & ~i[3] & ~i[5]); z2 <= (~i[5] | i[3] | i[5]); z3 <= (i[5] ^ ~i[3] ^ ~i[5] ^ i[3]); z4 <= &(i[0] && !i[0]); z5 <= |(i[1] || !i[1]); z6 <= ^(i[2] ^ !i[2]); z7 <= ^(i[2] ^ i[2]); end endmodule module match ( input logic [15:0] vec_i, input logic b8_i, input logic b12_i, output logic match1_o, output logic match2_o ); always_comb begin match1_o = 1'b0; if ( (vec_i[1:0] == 2'b0) && (vec_i[4] == 1'b0) && (vec_i[8] == b8_i) && (vec_i[12] == b12_i) ) begin match1_o = 1'b1; end end always_comb begin match2_o = 1'b0; if ( (vec_i[1:0] == 2'b0) && (vec_i[8] == b8_i) && (vec_i[12] == b12_i) && (vec_i[4] == 1'b0) ) begin match2_o = 1'b1; end end endmodule verilator-5.042/test_regress/t/t_semaphore_concurrent.v0000644000542200017500000000144515101701376024031 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Liam Braun. // SPDX-License-Identifier: CC0-1.0 module t(); semaphore s; // Stand-in for a task that should only be run by one thread at a time task automatic exclusive_task; $display("%0t", $time); #1; endtask task automatic call_exclusive_task; s.get(1); exclusive_task(); s.put(1); endtask initial begin s = new(1); fork call_exclusive_task(); call_exclusive_task(); call_exclusive_task(); call_exclusive_task(); join $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_castdyn.py0000755000542200017500000000073415101701376021437 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_struct_init.v0000644000542200017500000000667715101701376022167 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; //Several simulators don't support this. //typedef struct pack2; // Forward declaration typedef struct packed { // [3:0] logic b3; logic b2; logic b1; logic b0; } b4_t; typedef struct packed { // [3:0] b4_t x1; b4_t x0; } b4x2_t; typedef union q4_t; // Forward typedef union packed { // [3:0] bit [3:0] quad0; b4_t quad1; } q4_t; typedef struct packed { // [5:0] logic msb; q4_t four; logic lsb; } pack2_t; typedef union packed { // [5:0] pack2_t pack2; bit [6:1] pvec; // Vector not allowed in packed structure, per spec: // logic vec[6]; // logic vec2d[2][3]; } pack3_t; const b4_t b4_const_a = '{1'b1, 1'b0, 1'b0, 1'b1}; // Cast to a pattern - note bits are tagged out of order const b4_t b4_const_b = b4_t'{ b1 : 1'b0, b0 : 1'b1, b3 : 1'b1, b2 : 1'b0 }; wire b4_t b4_wire; assign b4_wire = '{1'b1, 1'b0, 1'b1, 1'b0}; pack2_t arr[2]; `ifdef T_STRUCT_INIT_BAD const b4_t b4_const_c = '{b1: 1'b1, b1: 1'b0, b0:1'b0, b2: 1'b1, b3: 1'b1}; `endif initial begin pack3_t tsu; tsu = 6'b110110; // 543210 if (tsu!=6'b110110) $stop; if (tsu[5:4]!=2'b11) $stop; if (tsu[5:4] == tsu[1:0]) $stop; // Not a good extraction test if LSB subtraction doesn't matter if (tsu.pvec!=6'b110110) $stop; if (tsu.pvec[6:5]!=2'b11) $stop; if (tsu.pack2[5:1] != 5'b11011) $stop; if (tsu.pack2.msb != 1'b1) $stop; if (tsu.pack2.lsb != 1'b0) $stop; if (tsu.pack2.four.quad0 != 4'b1011) $stop; if (tsu.pack2.four.quad1.b0 != 1'b1) $stop; if (tsu.pack2.four.quad1.b1 != 1'b1) $stop; if (tsu.pack2.four.quad1.b2 != 1'b0) $stop; if (tsu.pack2.four.quad1.b3 != 1'b1) $stop; // tsu = 1'b0 ? '0 : '{pvec: 6'b101011}; if (tsu!=6'b101011) $stop; // arr[0] = 6'b101010; arr[1] = 6'b010101; if (arr[0].four !== 4'b0101) $stop; if (arr[1].four !== 4'b1010) $stop; // // Initialization begin b4_t q; q = '{1'b1, 1'b1, 1'b0, 1'b0}; if (q != 4'b1100) $stop; end begin b4_t q; q = '{3{1'b1}, 1'b0}; if (q != 4'b1110) $stop; end begin b4_t q; q = '{4{1'b1}}; // Repeats the {} if (q != 4'b1111) $stop; end begin b4x2_t m; m = '{4'b1001, '{1'b1, 1'b0, 1'b1, 1'b1}}; if (m != 8'b10011011) $stop; end begin b4_t q; q = '{default:1'b1}; if (q != 4'b1111) $stop; end begin b4_t q; q = '{b0:1'b1, b2:1'b1, b3:1'b1, b1:1'b0}; if (q != 4'b1101) $stop; end begin b4_t q; q = '{b2:1'b0, default:1'b1}; if (q != 4'b1011) $stop; end if (b4_const_a != 4'b1001) $stop; if (b4_const_b != 4'b1001) $stop; if (b4_wire != 4'b1010) $stop; if (pat(4'b1100, 4'b1100)) $stop; if (pat('{1'b1, 1'b0, 1'b1, 1'b1}, 4'b1011)) $stop; $write("*-* All Finished *-*\n"); $finish; end function pat(b4_t in, logic [3:0] cmp); if (in !== cmp) $stop; pat = 1'b0; endfunction endmodule verilator-5.042/test_regress/t/t_altera_lpm_xor.py0000755000542200017500000000111115101701376022770 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) test.compile(verilator_flags2=["--top-module", module]) test.passes() verilator-5.042/test_regress/t/t_class_param_enum_bad.out0000644000542200017500000000156615101701376024271 0ustar mahmoudyfreeshell%Error: t/t_class_param_enum_bad.v:20:31: Assign RHS expects a CLASSREFDTYPE 'Converter__Tz2', got CLASSREFDTYPE 'Converter__Tz1' : ... note: In instance 't' 20 | Converter#(bit) conv2 = conv1; | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error-ENUMVALUE: t/t_class_param_enum_bad.v:21:19: Implicit conversion to enum 'enum{}$unit::enum_t' from 'logic[31:0]' (IEEE 1800-2023 6.19.3) : ... note: In instance 't' : ... Suggest use enum's mnemonic, or static cast 21 | conv1.toInt(0); | ^ ... For error description see https://verilator.org/warn/ENUMVALUE?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_property_pexpr.py0000755000542200017500000000073415101701376023074 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_param_type2.py0000755000542200017500000000073515101701376022216 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() #test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_dumpvars_dyn_vcd_0.out0000644000542200017500000001255215101701376025113 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $var wire 1 , clk $end $scope module t $end $var wire 1 , clk $end $var wire 32 # cyc [31:0] $end $scope module sub1a $end $var wire 32 - ADD [31:0] $end $var wire 32 # cyc [31:0] $end $var wire 32 $ value [31:0] $end $scope module sub2a $end $var wire 32 . ADD [31:0] $end $var wire 32 # cyc [31:0] $end $var wire 32 % value [31:0] $end $upscope $end $scope module sub2b $end $var wire 32 / ADD [31:0] $end $var wire 32 # cyc [31:0] $end $var wire 32 & value [31:0] $end $upscope $end $scope module sub2c $end $var wire 32 0 ADD [31:0] $end $var wire 32 # cyc [31:0] $end $var wire 32 ' value [31:0] $end $upscope $end $upscope $end $scope module sub1b $end $var wire 32 1 ADD [31:0] $end $var wire 32 # cyc [31:0] $end $var wire 32 ( value [31:0] $end $scope module sub2a $end $var wire 32 2 ADD [31:0] $end $var wire 32 # cyc [31:0] $end $var wire 32 ) value [31:0] $end $upscope $end $scope module sub2b $end $var wire 32 3 ADD [31:0] $end $var wire 32 # cyc [31:0] $end $var wire 32 * value [31:0] $end $upscope $end $scope module sub2c $end $var wire 32 4 ADD [31:0] $end $var wire 32 # cyc [31:0] $end $var wire 32 + value [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 b00000000000000000000000000000000 # b00000000000000000000000000001010 $ b00000000000000000000000000001011 % b00000000000000000000000000001100 & b00000000000000000000000000001101 ' b00000000000000000000000000010100 ( b00000000000000000000000000010101 ) b00000000000000000000000000010110 * b00000000000000000000000000010111 + 0, b00000000000000000000000000001010 - b00000000000000000000000000001011 . b00000000000000000000000000001100 / b00000000000000000000000000001101 0 b00000000000000000000000000010100 1 b00000000000000000000000000010101 2 b00000000000000000000000000010110 3 b00000000000000000000000000010111 4 #1 b00000000000000000000000000000001 # b00000000000000000000000000001011 $ b00000000000000000000000000001100 % b00000000000000000000000000001101 & b00000000000000000000000000001110 ' b00000000000000000000000000010101 ( b00000000000000000000000000010110 ) b00000000000000000000000000010111 * b00000000000000000000000000011000 + 1, #2 0, #3 b00000000000000000000000000000010 # b00000000000000000000000000001100 $ b00000000000000000000000000001101 % b00000000000000000000000000001110 & b00000000000000000000000000001111 ' b00000000000000000000000000010110 ( b00000000000000000000000000010111 ) b00000000000000000000000000011000 * b00000000000000000000000000011001 + 1, #4 0, #5 b00000000000000000000000000000011 # b00000000000000000000000000001101 $ b00000000000000000000000000001110 % b00000000000000000000000000001111 & b00000000000000000000000000010000 ' b00000000000000000000000000010111 ( b00000000000000000000000000011000 ) b00000000000000000000000000011001 * b00000000000000000000000000011010 + 1, #6 0, #7 b00000000000000000000000000000100 # b00000000000000000000000000001110 $ b00000000000000000000000000001111 % b00000000000000000000000000010000 & b00000000000000000000000000010001 ' b00000000000000000000000000011000 ( b00000000000000000000000000011001 ) b00000000000000000000000000011010 * b00000000000000000000000000011011 + 1, #8 0, #9 b00000000000000000000000000000101 # b00000000000000000000000000001111 $ b00000000000000000000000000010000 % b00000000000000000000000000010001 & b00000000000000000000000000010010 ' b00000000000000000000000000011001 ( b00000000000000000000000000011010 ) b00000000000000000000000000011011 * b00000000000000000000000000011100 + 1, #10 0, #11 b00000000000000000000000000000110 # b00000000000000000000000000010000 $ b00000000000000000000000000010001 % b00000000000000000000000000010010 & b00000000000000000000000000010011 ' b00000000000000000000000000011010 ( b00000000000000000000000000011011 ) b00000000000000000000000000011100 * b00000000000000000000000000011101 + 1, #12 0, #13 b00000000000000000000000000000111 # b00000000000000000000000000010001 $ b00000000000000000000000000010010 % b00000000000000000000000000010011 & b00000000000000000000000000010100 ' b00000000000000000000000000011011 ( b00000000000000000000000000011100 ) b00000000000000000000000000011101 * b00000000000000000000000000011110 + 1, #14 0, #15 b00000000000000000000000000001000 # b00000000000000000000000000010010 $ b00000000000000000000000000010011 % b00000000000000000000000000010100 & b00000000000000000000000000010101 ' b00000000000000000000000000011100 ( b00000000000000000000000000011101 ) b00000000000000000000000000011110 * b00000000000000000000000000011111 + 1, #16 0, #17 b00000000000000000000000000001001 # b00000000000000000000000000010011 $ b00000000000000000000000000010100 % b00000000000000000000000000010101 & b00000000000000000000000000010110 ' b00000000000000000000000000011101 ( b00000000000000000000000000011110 ) b00000000000000000000000000011111 * b00000000000000000000000000100000 + 1, #18 0, #19 b00000000000000000000000000001010 # b00000000000000000000000000010100 $ b00000000000000000000000000010101 % b00000000000000000000000000010110 & b00000000000000000000000000010111 ' b00000000000000000000000000011110 ( b00000000000000000000000000011111 ) b00000000000000000000000000100000 * b00000000000000000000000000100001 + 1, #20 0, verilator-5.042/test_regress/t/TestCheck.h0000644000542200017500000000603415101701376021117 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2013-2025 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #ifndef TEST_CHECK_H_ #define TEST_CHECK_H_ #include extern int errors; #ifdef TEST_VERBOSE static const bool verbose = true; #else static const bool verbose = false; #endif //====================================================================== // Use cout to avoid issues with %d/%lx etc #define TEST_CHECK(got, exp, test) \ do { \ if (!(test)) { \ std::cout << std::dec << "%Error: " << __FILE__ << ":" << __LINE__ \ << ": GOT = " << (got) << " EXP = " << (exp) << std::endl; \ ++errors; \ } \ } while (0) #define TEST_CHECK_EQ(got, exp) TEST_CHECK(got, exp, ((got) == (exp))); #define TEST_CHECK_NE(got, exp) TEST_CHECK(got, exp, ((got) != (exp))); #define TEST_CHECK_CSTR(got, exp) TEST_CHECK(got, exp, 0 == std::strcmp((got), (exp))); #define TEST_CHECK_HEX_EQ(got, exp) \ do { \ if ((got) != (exp)) { \ std::cout << std::dec << "%Error: " << __FILE__ << ":" << __LINE__ << std::hex \ << ": GOT=" << (got) << " EXP=" << (exp) << std::endl; \ ++errors; \ } \ } while (0) #define TEST_CHECK_HEX_NE(got, exp) \ do { \ if ((got) == (exp)) { \ std::cout << std::dec << "%Error: " << __FILE__ << ":" << __LINE__ << std::hex \ << ": GOT=" << (got) << " EXP!=" << (exp) << std::endl; \ ++errors; \ } \ } while (0) #define TEST_CHECK_Z(got) \ do { \ if ((got)) { \ std::cout << std::dec << "%Error: " << __FILE__ << ":" << __LINE__ << std::hex \ << ": GOT!= NULL EXP=NULL" << std::endl; \ ++errors; \ } \ } while (0) #define TEST_CHECK_NZ(got) \ do { \ if (!(got)) { \ std::cout << std::dec << "%Error: " << __FILE__ << ":" << __LINE__ << std::hex \ << ": GOT= NULL EXP!=NULL" << std::endl; \ ++errors; \ } \ } while (0) #define TEST_CHECK_REAL_EQ(got, exp, delta) \ do { \ if (std::fabs(got - exp) > delta) { \ std::cout << std::dec << "%Error: " << __FILE__ << ":" << __LINE__ << std::showpoint \ << ": GOT=" << (got) << " EXP=" << (exp) << " +/- " << (delta) \ << std::endl; \ ++errors; \ } \ } while (0) //====================================================================== #define TEST_VERBOSE_PRINTF(format, ...) \ do { \ if (verbose) printf(format, ##__VA_ARGS__); \ } while (0) #endif // Guard verilator-5.042/test_regress/t/t_var_bad_sv.out0000644000542200017500000000126115101701376022250 0ustar mahmoudyfreeshell%Error: t/t_var_bad_sv.v:8:8: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier. : ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language. 8 | reg do; | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_var_bad_sv.v:9:14: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier. 9 | mod mod (.do(bar)); | ^~ %Error: t/t_var_bad_sv.v:9:16: syntax error, unexpected '(', expecting ')' 9 | mod mod (.do(bar)); | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_typedef_port.v0000644000542200017500000000527115101701376022311 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef reg [2:0] threeansi_t; module t (/*AUTOARG*/ // Inputs clk ); input clk; typedef reg [2:0] three_t; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [2:0] in = crc[2:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) threeansi_t outa; // From testa of TestAnsi.v three_t outna; // From test of TestNonAnsi.v // End of automatics TestNonAnsi test (// Outputs .out (outna), /*AUTOINST*/ // Inputs .clk (clk), .in (in)); TestAnsi testa (// Outputs .out (outa), /*AUTOINST*/ // Inputs .clk (clk), .in (in)); // Aggregate outputs into a single result vector wire [63:0] result = {57'h0, outna, 1'b0, outa}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h018decfea0a8828a if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module TestNonAnsi (/*AUTOARG*/ // Outputs out, // Inputs clk, in ); typedef reg [2:0] three_t; input clk; input three_t in; output three_t out; always @(posedge clk) begin out <= ~in; end endmodule module TestAnsi ( input clk, input threeansi_t in, output threeansi_t out ); always @(posedge clk) begin out <= ~in; end endmodule // Local Variables: // verilog-typedef-regexp: "_t$" // End: verilator-5.042/test_regress/t/t_lint_repeat_bad.py0000755000542200017500000000076615101701376023113 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_unpacked_str_pair.v0000644000542200017500000000257615101701376023307 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; typedef string array_of_string_t[]; typedef struct { string positive; string negative; } filter_expression_parts_t; function automatic array_of_string_t split_by_char(string c, string s); string parts[$]; int last_char_position = -1; for (int i = 0; i < s.len(); i++) begin if (i == s.len()-1) parts.push_back(s.substr(last_char_position+1, i)); if (string'(s[i]) == c) begin parts.push_back(s.substr(last_char_position+1, i-1)); last_char_position = i; end end $display("%p", parts); return parts; endfunction function filter_expression_parts_t get_filter_expression_parts(string raw_filter); string parts[]; parts = split_by_char("-", raw_filter); return '{ parts[0], parts[1] }; endfunction initial begin string raw_filter = "parta-partb"; filter_expression_parts_t parts = get_filter_expression_parts(raw_filter); $display("%p", parts); if (parts.positive != "parta") $stop; if (parts.negative != "partb") $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_trace_no_top_name2_fst.py0000755000542200017500000000127715101701376024407 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.pli_filename = "t/t_trace_no_top_name2.cpp" test.top_filename = "t/t_trace_no_top_name2.v" test.compile(make_main=False, verilator_flags2=["--trace-fst --exe", test.pli_filename]) test.execute() test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_force_assign.py0000755000542200017500000000073415101701376022434 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_timing_fork_join.v0000644000542200017500000000507315101701376023134 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; event event1; event event2; event event3; initial begin fork begin /*empty*/ end #8 $write("[%0t] fork..join process 1\n", $time); #4 $write("[%0t] fork..join process 2\n", $time); #2 $write("[%0t] fork..join process 3\n", $time); $write("[%0t] fork..join process 4\n", $time); begin : fork_in_fork #16 $write("[%0t] fork in fork starts\n", $time); fork #16 $write("[%0t] fork..join process 5\n", $time); #8 $write("[%0t] fork..join process 6\n", $time); #4 $write("[%0t] fork..join process 7\n", $time); $write("[%0t] fork..join process 8\n", $time); join $write("[%0t] fork..join in fork ends\n", $time); end join #32 $write("[%0t] main process\n", $time); fork begin @event1; $write("fork..join_any process 1\n"); ->event1; end $write("fork..join_any process 2\n"); join_any $write("back in main process\n"); #1 ->event1; #1 fork #2 $write("fork..join_any process 1\n"); begin @event1; $write("fork..join_any process 2\n"); ->event1; end join_any $write("back in main process\n"); #1 ->event1; @event1; // Order of triggering: // p1->event2 ==> p2->event3 ==> p3->event3 ==> p2->event2 ==> p1->event3 ==> p3->event1 fork begin #1 $write("fork..join_none process 1\n"); ->event2; @event2 $write("fork..join_none process 1 again\n"); #1 ->event3; end begin @event2 $write("fork..join_none process 2\n"); #1 ->event3; @event3 $write("fork..join_none process 2 again\n"); #1 ->event2; end begin @event3 $write("fork..join_none process 3\n"); #1 ->event3; @event3 $write("fork..join_none process 3 again\n"); ->event1; end join_none $write("in main process\n"); @event1; $write("*-* All Finished *-*\n"); $finish; end initial #100 $stop; // timeout // Test optimized-out fork statements: reg a; initial fork a = 1; join endmodule verilator-5.042/test_regress/t/t_force_assign.v0000644000542200017500000000066215101701376022246 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t; reg [2:0] a = 0; initial begin a = 1; if (a != 1) $stop; force a = 2; if (a != 2) $stop; a = 3; if (a != 2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_delay.py0000755000542200017500000000103015101701376021056 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['-Wno-STMTDLY -Wno-ASSIGNDLY --no-timing']) test.execute() test.passes() verilator-5.042/test_regress/t/t_math_shift_noexpand.py0000755000542200017500000000103515101701376024007 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_math_shift.v" test.compile(verilator_flags2=['-fno-expand']) test.execute() test.passes() verilator-5.042/test_regress/t/t_semaphore_concurrent.out0000644000542200017500000000003515101701376024365 0ustar mahmoudyfreeshell0 1 2 3 *-* All Finished *-* verilator-5.042/test_regress/t/t_math_signed3.v0000644000542200017500000000740415101701376022152 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module t; // verilator lint_off WIDTH wire [1:0] bug729_au = ~0; wire signed [1:0] bug729_as = ~0; wire [2:0] bug729_b = ~0; // the $signed output is unsigned because the input is unsigned; the signedness does not change. wire [0:0] bug729_yuu = $signed(2'b11) == 3'b111; //1'b0 wire [0:0] bug729_ysu = $signed(2'SB11) == 3'b111; //1'b0 wire [0:0] bug729_yus = $signed(2'b11) == 3'sb111; //1'b1 wire [0:0] bug729_yss = $signed(2'sb11) == 3'sb111; //1'b1 wire [0:0] bug729_zuu = 2'sb11 == 3'b111; //1'b0 wire [0:0] bug729_zsu = 2'sb11 == 3'b111; //1'b0 wire [0:0] bug729_zus = 2'sb11 == 3'sb111; //1'b1 wire [0:0] bug729_zss = 2'sb11 == 3'sb111; //1'b1 wire [3:0] bug733_a = 4'b0010; wire [3:0] bug733_yu = $signed(|bug733_a); // 4'b1111 note | is always unsigned wire signed [3:0] bug733_ys = $signed(|bug733_a); // 4'b1111 wire [3:0] bug733_zu = $signed(2'b11); // 4'b1111 wire signed [3:0] bug733_zs = $signed(2'sb11); // 4'b1111 // When RHS of assignment is fewer bits than lhs, RHS sign or zero extends based on RHS's sign wire [3:0] bug733_qu = 2'sb11; // 4'b1111 wire signed [3:0] bug733_qs = 2'sb11; // 4'b1111 reg signed [32:0] bug349_s; reg signed [32:0] bug349_u; wire signed [1:0] sb11 = 2'sb11; wire [3:0] subout_u; sub sub (.a(2'sb11), .z(subout_u)); initial begin #1; `checkh(subout_u, 4'b1111); end wire [5:0] cond_a = 1'b1 ? 3'sb111 : 5'sb11111; initial begin #1; `checkh(cond_a, 6'b111111); end wire [5:0] cond_b = 1'b0 ? 3'sb111 : 5'sb11111; initial begin #1; `checkh(cond_b, 6'b111111); end bit cmp; initial begin #1; // verilator lint_on WIDTH `checkh(bug729_yuu, 1'b0); `checkh(bug729_ysu, 1'b0); `checkh(bug729_yus, 1'b1); `checkh(bug729_yss, 1'b1); `checkh(bug729_zuu, 1'b0); `checkh(bug729_zsu, 1'b0); `checkh(bug729_zus, 1'b1); `checkh(bug729_zss, 1'b1); `checkh(bug733_yu, 4'b1111); `checkh(bug733_ys, 4'b1111); `checkh(bug733_zu, 4'b1111); `checkh(bug733_zs, 4'b1111); `checkh(bug733_qu, 4'b1111); `checkh(bug733_qs, 4'b1111); // verilator lint_off WIDTH bug349_s = 4'sb1111; `checkh(bug349_s, 33'h1ffffffff); bug349_u = 4'sb1111; `checkh(bug349_u, 33'h1ffffffff); bug349_s = 4'sb1111 - 1'b1; `checkh(bug349_s,33'he); bug349_s = 4'sb1111 - 5'b00001; `checkh(bug349_s,33'he); cmp = 3'sb111 == 4'b111; `checkh(cmp, 1); cmp = 3'sb111 == 4'sb111; `checkh(cmp, 0); cmp = 3'sb111 != 4'b111; `checkh(cmp, 0); cmp = 3'sb111 != 4'sb111; `checkh(cmp, 1); cmp = 3'sb111 === 4'b111; `checkh(cmp, 1); cmp = 3'sb111 === 4'sb111; `checkh(cmp, 0); case (2'sb11) 4'b1111: $stop; default: ; endcase case (sb11) 4'b1111: $stop; default: ; endcase case (2'sb11) 4'sb1111: ; default: $stop; endcase case (sb11) 4'sb1111: ; default: $stop; endcase $write("*-* All Finished *-*\n"); $finish; end endmodule module sub(input [3:0] a, output [3:0] z); assign z = a; endmodule verilator-5.042/test_regress/t/t_gen_intdot2.py0000755000542200017500000000073415101701376022206 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_covergroup_new_override_bad.v0000644000542200017500000000051615101701376025353 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off COVERIGN */ module t(); covergroup cg; function new(); endfunction endgroup endmodule verilator-5.042/test_regress/t/t_dpi_import_hdr_only.py0000755000542200017500000000242615101701376024036 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap import filecmp test.scenarios('simulator') test.top_filename = "t/t_dpi_import.v" tmp_dir = test.obj_dir + "/dpi-hdr" test.mkdir_ok(tmp_dir) test.compile( # Override default flags also verilator_flags=["-Wall -Wno-DECLFILENAME -Mdir " + tmp_dir + " --dpi-hdr-only"], verilator_make_gmake=False) files = glob.glob(tmp_dir + "/*") if len(files) < 1: test.error("Did not produce DPI header") if len(files) > 1: test.error("Too many files created:" + ', '.join(files)) tmp_header = files[0] print("============" + tmp_header) if not re.search(r'__Dpi\.h$', tmp_header): test.error("Unexpected file " + tmp_header) test.compile(verilator_flags2=["-Wall -Wno-DECLFILENAME"], verilator_make_gmake=False) files = glob.glob(test.obj_dir + "/*__Dpi.h") header = files[0] if not filecmp.cmp(tmp_header, header): test.error("DPI header files are not the same") test.passes() verilator-5.042/test_regress/t/t_forceable_net.v0000644000542200017500000000404015101701376022366 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module t ( input wire clk, input wire rst, output reg [31:0] cyc ); always @(posedge clk) begin if (rst) begin cyc <= 0; end else begin cyc <= cyc +1; end end `ifdef CMT wire net_1 /* verilator forceable */; wire [7:0] net_8 /* verilator forceable */; `else wire net_1; wire [7:0] net_8; `endif assign net_1 = ~cyc[0]; assign net_8 = ~cyc[1 +: 8]; wire obs_1 = net_1; wire [7:0] obs_8 = net_8; always @ (posedge clk) begin $display("%d: %x %x", cyc, obs_8, obs_1); if (!rst) begin case (cyc) 3: begin `checkh (obs_1, 0); `checkh (obs_8, ~cyc[1 +: 8]); end 4: begin `checkh (obs_1, 0); `checkh (obs_8, 8'h5f); end 5: begin `checkh (obs_1, 1); `checkh (obs_8, 8'h5f); end 6, 7: begin `checkh (obs_1, 1); `checkh (obs_8, 8'hf5); end 8: begin `checkh (obs_1, ~cyc[0]); `checkh (obs_8, 8'hf5); end 10, 11: begin `checkh (obs_1, 1); `checkh (obs_8, 8'h5a); end 12, 13: begin `checkh (obs_1, 0); `checkh (obs_8, 8'ha5); end default: begin `checkh ({obs_8, obs_1}, ~cyc[0 +: 9]); end endcase end if (cyc == 30) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_threads_counter_1.py0000755000542200017500000000105015101701376023373 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vltmt') test.top_filename = "t/t_threads_counter.v" test.compile(verilator_flags2=['--cc'], threads=1) test.execute() test.passes() verilator-5.042/test_regress/t/t_struct_initial_assign_public.py0000755000542200017500000000107715101701376025732 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_struct_initial_assign.v" test.compile(verilator_flags2=["--timing", "--public-flat-rw"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_generic_task.v0000644000542200017500000000113015101701376024251 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 interface inf; int v; task setup(); v = 3; endtask endinterface interface inf2; int k; endinterface module GenericModule (interface a); initial begin a.setup(); end endmodule module t; inf inf_inst(); GenericModule genericModule (inf_inst); initial begin #1; if (inf_inst.v != 3) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_assert_always_unsup.py0000755000542200017500000000105515101701376024102 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.leak_check_disable() test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert'], fails=True) test.passes() verilator-5.042/test_regress/t/t_trace_max.out0000644000542200017500000000110515101701376022102 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $var wire 1 # clk $end $scope module t $end $var wire 1 # clk $end $var wire 32 $ cyc [31:0] $end $upscope $end $upscope $end $enddefinitions $end #0 0# b00000000000000000000000000000000 $ #10 1# b00000000000000000000000000000001 $ #15 0# #20 1# b00000000000000000000000000000010 $ #25 0# #30 1# b00000000000000000000000000000011 $ #35 0# #40 1# b00000000000000000000000000000100 $ #45 0# #50 1# b00000000000000000000000000000101 $ #55 0# #60 1# b00000000000000000000000000000110 $ verilator-5.042/test_regress/t/t_interface_modport_dir_bad.v0000644000542200017500000000234215101701376024751 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Driss Hafdi // SPDX-License-Identifier: CC0-1.0 interface validData ( input wire clk, input wire rst ); logic data; logic valid; modport sink ( input data, valid, clk, rst ); modport source ( input clk, rst, output data, valid ); endinterface module sinkMod ( validData.sink ctrl, output logic valid_data ); always_ff @(posedge ctrl.clk) begin if (ctrl.valid) valid_data <= ctrl.data; end endmodule module sourceMod ( validData.source ctrl ); always_ff @(posedge ctrl.clk) begin ctrl.data <= ~ctrl.data; ctrl.valid <= ~ctrl.valid; end endmodule module parentSourceMod ( validData.sink ctrl ); sourceMod source_i (.ctrl); endmodule module t (/*AUTOARG*/ // Outputs data, // Inputs clk, rst ); input clk; input rst; output logic data; validData ctrl(.clk, .rst); sinkMod sink_i (.ctrl, .valid_data(data)); parentSourceMod source_i (.ctrl); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_func_arg_complex.py0000755000542200017500000000112415101701376023277 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(v_flags2=[ "-Wno-PKGNODECL -Wno-UNPACKED -Wno-IMPLICITSTATIC -Wno-CONSTRAINTIGN -Wno-MISINDENT", "--error-limit 200" ]) test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_unused.py0000755000542200017500000000102315101701376022313 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--lint-only --bbox-sys --bbox-unsup -Wall -Wno-DECLFILENAME"]) test.passes() verilator-5.042/test_regress/t/t_uniqueif_fail3.py0000755000542200017500000000131415101701376022670 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_uniqueif.v" test.compile(v_flags2=['+define+FAILING_ASSERTION3'], verilator_flags2=['--assert'], nc_flags2=['+assert'], fails=test.nc) test.execute(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_timing_split.v0000644000542200017500000000142315101701376022302 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Jomit626. // SPDX-License-Identifier: CC0-1.0 module t (); logic clk = 0; logic data = 0; always #5 clk <= ~clk; task static foo(); @(negedge clk); data = 1; @(negedge clk); data = 0; endtask `define foo8()\ foo();foo();foo();foo();foo();foo();foo();foo() `define foo64()\ `foo8();`foo8();`foo8();`foo8();`foo8();`foo8();`foo8();`foo8() `define foo512()\ `foo64();`foo64();`foo64();`foo64();`foo64();`foo64();`foo64();`foo64() initial begin `foo512(); `foo512(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_class_extends_arg_super_bad.v0000644000542200017500000000075215101701376025320 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Base; int m_s = 2; function new(int def = 3); m_s = def; endfunction endclass class Cls5 extends Base(5); int m_a; function new(int def = 42); super.new(33); // Bad, can't super.new with extends args m_a = def; endfunction endclass verilator-5.042/test_regress/t/t_lint_implicit_bad.out0000644000542200017500000000205715101701376023614 0ustar mahmoudyfreeshell%Warning-IMPLICIT: t/t_lint_implicit.v:11:11: Signal definition not found, creating implicitly: 'b' 11 | assign b = 1'b1; | ^ ... For warning description see https://verilator.org/warn/IMPLICIT?v=latest ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message. %Warning-IMPLICIT: t/t_lint_implicit.v:13:14: Signal definition not found, creating implicitly: 'nt0' 13 | or OR0 (nt0, a, b); | ^~~ %Warning-IMPLICIT: t/t_lint_implicit.v:16:12: Signal definition not found, creating implicitly: 'dummy1' : ... Suggested alternative: 'dummy_ip' 16 | assign {dummy1, dummy2} = dummy_ip; | ^~~~~~ %Warning-IMPLICIT: t/t_lint_implicit.v:16:20: Signal definition not found, creating implicitly: 'dummy2' : ... Suggested alternative: 'dummy1' 16 | assign {dummy1, dummy2} = dummy_ip; | ^~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_trace_array.out0000644000542200017500000340131515101701376022445 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $var wire 1 [K clk $end $scope module t $end $var wire 1 [K clk $end $var wire 32 # cyc [31:0] $end $scope module biggie $end $var wire 131073 $ d [131072:0] $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 b00000000000000000000000000000000 # b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $ 0[K #10 b00000000000000000000000000000001 # b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111110111011011111101011001110 $ 1[K #15 0[K #20 b00000000000000000000000000000010 # b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111101110110111111010110011100 $ 1[K #25 0[K #30 b00000000000000000000000000000011 # b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111011101101111110101100111000 $ 1[K #35 0[K #40 b00000000000000000000000000000100 # b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111110111011011111101011001110000 $ 1[K #45 0[K #50 b00000000000000000000000000000101 # b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111101110110111111010110011100000 $ 1[K #55 0[K #60 b00000000000000000000000000000110 # b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111011101101111110101100111000000 $ 1[K verilator-5.042/test_regress/t/t_process_fork.v0000644000542200017500000000126015101701376022276 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; process job[] = new [8]; initial begin foreach (job[j]) fork begin $write("job started\n"); job[j] = process::self(); end join_none foreach (job[j]) begin wait (job[j]); end $write("all jobs started\n"); foreach (job[j]) begin job[j].await(); end $write("all jobs finished\n"); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_display_string.v0000644000542200017500000000142215101701376022632 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; function automatic string foo(int i); return $sformatf("'%d'", i); // %0d does not work here endfunction real r = 1.234; string bar = foo(1); localparam string pbar = foo(1); initial begin $write("String: "); $display("' 1'"); $write("foo(1): "); $display(foo(1)); $write("s f(1): "); $display("%s", foo(1)); $write("s parm: "); $display("%s", pbar); $write("s strg: "); $display("%s", bar); $write("r: "); $display(r); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_param_x_unique.py0000755000542200017500000000101615101701376023001 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--trace-fst --x-assign unique"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_package_ddecl.py0000755000542200017500000000100515101701376022510 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--binary --no-timing']) test.execute() test.passes() verilator-5.042/test_regress/t/t_opt_merge_cond_no_extend.v0000644000542200017500000000066515101701376024636 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 module t ( input wire clk, input wire [7:0] i, input wire a, output reg [7:0] o ); reg cond = 0; always @(posedge clk) begin if (cond) o = i; cond = a; if (cond) o = ~i; end endmodule verilator-5.042/test_regress/t/t_real_out_of_bounds.py0000755000542200017500000000073715101701376023645 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_assoc_wildcard.py0000755000542200017500000000073415101701376022753 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_struct_packed_write_read.py0000755000542200017500000000073415101701376025032 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_flag_output_groups_bad.py0000755000542200017500000000106015101701376024521 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=['--output-groups -2'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_flag_getenv.v0000644000542200017500000000034615101701376022064 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define EMPTY 1 verilator-5.042/test_regress/t/t_runflag_bad__d.out0000644000542200017500000000017015101701376023046 0ustar mahmoudyfreeshell%Error: COMMAND_LINE:0: Argument '+verilator+prof+exec+window+' must be an unsigned integer, greater than 0 Aborting... verilator-5.042/test_regress/t/t_pp_defparen_bad.v0000644000542200017500000000041315101701376022667 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define test(a1,a2) ((a1) + (a2)) `test val ( 1,2) verilator-5.042/test_regress/t/t_for_assign.v0000644000542200017500000000202215101701376021726 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t; int a, b; int sum; // Complicated assignment cases initial begin sum = 0; for (integer a=0; a<3; ) begin a = a + 1; sum = sum + a; end `checkd(sum, 6); // foperator_assignment sum = 0; for (integer a=0; a<3; a=a+1, sum += a) ; `checkd(sum, 6); // inc_or_dec_expression sum = 0; for (integer a=0; a<3; a++, ++sum) ; `checkd(sum, 3); // task_subroutine_call sum = 0; for (integer a=0; a<3; a++, sum += $clog2(a)) ; `checkd(sum, 3); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_alias_unsup.v0000644000542200017500000000444615101701376022133 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias' // // Simple bi-directional alias test. // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 // verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); // verilog_format: on module t ( /*AUTOARG*/ // Inputs clk ); input clk; int cyc; reg [63:0] crc; reg [63:0] sum; // Values to swap and locations for the swapped values. wire [31:0] x_fwd = crc[31:0]; wire [31:0] y_fwd; wire [31:0] x_bwd; wire [31:0] y_bwd = crc[63:32]; Test test1 ( .a(x_fwd), .b(y_fwd) ); Test test2 ( .a(x_bwd), .b(y_bwd) ); // Test loop always @(posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x x_fwd=%x y_bwd=%x\n", $time, cyc, crc, x_fwd, y_bwd); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= {x_fwd, y_bwd} ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc == 0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc < 10) begin sum <= '0; end else if (cyc < 90) begin end else if (cyc == 99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); `checkh(crc, 64'hc77bb9b3784ea091); // What checksum will we end up with (above print should match) `checkh(sum, 64'h5a3868140accd91d); $write("*-* All Finished *-*\n"); $finish; end end endmodule // Swap the byte order of two args. module Test ( inout wire [31:0] a, inout wire [31:0] b ); alias {a[7:0], a[15:8], a[23:16], a[31:24]} = b; // Equivalent to // wire [31:0] a_prime; // wire [31:0] b_prime; // assign b_prime = {a[7:0],a[15:8],a[23:16],a[31:24]}; // assign {a_prime[7:0],a_prime[15:8],a_prime[23:16],a_prime[31:24]} = b; // assign b = b_prime; // assign a = a_prime; endmodule verilator-5.042/test_regress/t/t_func_refio_bad.out0000644000542200017500000000060015101701376023063 0ustar mahmoudyfreeshell%Error: t/t_func_refio_bad.v:16:17: Ref argument requires matching types; port 'q' requires 'integer$[$]' but connection is 'logic[31:0]'. : ... note: In instance 't' 16 | queue_set(42); | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_trace_cat_renew__0100.out0000644000542200017500000000503215101701376024066 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $var wire 1 # clk $end $scope module t $end $var wire 1 # clk $end $var wire 32 $ cyc [31:0] $end $upscope $end $upscope $end $enddefinitions $end #100 1# b00000000000000000000000000110010 $ #101 0# #102 1# b00000000000000000000000000110011 $ #103 0# #104 1# b00000000000000000000000000110100 $ #105 0# #106 1# b00000000000000000000000000110101 $ #107 0# #108 1# b00000000000000000000000000110110 $ #109 0# #110 1# b00000000000000000000000000110111 $ #111 0# #112 1# b00000000000000000000000000111000 $ #113 0# #114 1# b00000000000000000000000000111001 $ #115 0# #116 1# b00000000000000000000000000111010 $ #117 0# #118 1# b00000000000000000000000000111011 $ #119 0# #120 1# b00000000000000000000000000111100 $ #121 0# #122 1# b00000000000000000000000000111101 $ #123 0# #124 1# b00000000000000000000000000111110 $ #125 0# #126 1# b00000000000000000000000000111111 $ #127 0# #128 1# b00000000000000000000000001000000 $ #129 0# #130 1# b00000000000000000000000001000001 $ #131 0# #132 1# b00000000000000000000000001000010 $ #133 0# #134 1# b00000000000000000000000001000011 $ #135 0# #136 1# b00000000000000000000000001000100 $ #137 0# #138 1# b00000000000000000000000001000101 $ #139 0# #140 1# b00000000000000000000000001000110 $ #141 0# #142 1# b00000000000000000000000001000111 $ #143 0# #144 1# b00000000000000000000000001001000 $ #145 0# #146 1# b00000000000000000000000001001001 $ #147 0# #148 1# b00000000000000000000000001001010 $ #149 0# #150 1# b00000000000000000000000001001011 $ #151 0# #152 1# b00000000000000000000000001001100 $ #153 0# #154 1# b00000000000000000000000001001101 $ #155 0# #156 1# b00000000000000000000000001001110 $ #157 0# #158 1# b00000000000000000000000001001111 $ #159 0# #160 1# b00000000000000000000000001010000 $ #161 0# #162 1# b00000000000000000000000001010001 $ #163 0# #164 1# b00000000000000000000000001010010 $ #165 0# #166 1# b00000000000000000000000001010011 $ #167 0# #168 1# b00000000000000000000000001010100 $ #169 0# #170 1# b00000000000000000000000001010101 $ #171 0# #172 1# b00000000000000000000000001010110 $ #173 0# #174 1# b00000000000000000000000001010111 $ #175 0# #176 1# b00000000000000000000000001011000 $ #177 0# #178 1# b00000000000000000000000001011001 $ #179 0# #180 1# b00000000000000000000000001011010 $ #181 0# #182 1# b00000000000000000000000001011011 $ #183 0# #184 1# b00000000000000000000000001011100 $ #185 0# #186 1# b00000000000000000000000001011101 $ #187 0# #188 1# b00000000000000000000000001011110 $ #189 0# verilator-5.042/test_regress/t/t_preproc_eof3_bad.v0000644000542200017500000000035715101701376023001 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define FOO(a,b) `FOO(1, verilator-5.042/test_regress/t/t_past_strobe.out0000644000542200017500000000023415101701376022466 0ustar mahmoudyfreeshell1 == 1, 0 == 0 2 == 2, 1 == 1 3 == 3, 2 == 2 4 == 4, 3 == 3 5 == 5, 4 == 4 6 == 6, 5 == 5 7 == 7, 6 == 6 8 == 8, 7 == 7 9 == 9, 8 == 8 *-* All Finished *-* verilator-5.042/test_regress/t/t_verilated_debug.py0000755000542200017500000000125115101701376023112 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.verilated_debug = True test.compile(verilator_flags2=[]) test.execute() if not test.vltmt: # vltmt output may vary between thread exec order test.files_identical(test.obj_dir + "/vlt_sim.log", test.golden_filename, "logfile") test.passes() verilator-5.042/test_regress/t/t_clk_latch.py0000755000542200017500000000073415101701376021716 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_xml_deprecated_bad.py0000755000542200017500000000114315101701376023553 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = 't/t_EXAMPLE.v' test.lint(verilator_flags2=["--xml-only --xml-output /dev/null"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_unpacked_concat_bad2.v0000644000542200017500000000117215101701376023612 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2023 by Yutetsu TAKATSUKASA. // SPDX-License-Identifier: CC0-1.0 module t; logic [7:0] s0; logic [7:0] s1[1:2]; logic [7:0] s2[1:4]; logic [7:0] s3[2][2]; typedef int AI3[1:3]; AI3 A3; logic [31:0] A9_logic[1:9]; initial begin // RHS has too many elements. s1 = {s0, s2}; s2 = {s1, s0, s0, s0}; // Incompatible type s2 = {s0, s3}; A9_logic = {A3, 4, 5, A3, 6}; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_type.v0000644000542200017500000000212315101701376020557 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; real x; real y; var type(x+y) z; localparam type x_type = type(x); x_type value; initial begin value = 1.234; if (value != 1.234) $stop(); x = 1.2; y = 2.3; z = x + y; if (z != (1.2+2.3)) $stop; z = type(z)'(22); if (z != 22.0) $stop; $write("*-* All Finished *-*\n"); $finish; end localparam type x_minus_y_type = type(x-y); sub_real #(.the_type (x_minus_y_type)) the_sub_real_1(); sub_real #(.the_type (type(x-y))) the_sub_real_2(); localparam type type1 = type(x*y); type1 type1_var; localparam type type2 = type(type1_var/y); sub_real #(.the_type (type2)) the_sub_real_3(); endmodule module sub_real #( parameter type the_type = bit ) (); the_type the_value; initial begin the_value = 4.567; if (the_value != 4.567) $stop(); end endmodule verilator-5.042/test_regress/t/t_past_funcs.py0000755000542200017500000000077115101701376022140 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--assert']) test.execute() test.passes() verilator-5.042/test_regress/t/t_concat_opt.v0000644000542200017500000000352015101701376021731 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2004 by Jie Xu. // SPDX-License-Identifier: CC0-1.0 // // The test was added together with the concat optimization. module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg [31:0] in_a; reg [31:0] in_b; reg [31:0] in_c; reg [31:0] in_d; reg [31:0] in_e; reg [15:0] in_f; wire [31:0] in_g; assign in_g = in_a << 4; reg [31:0] out_x; reg [31:0] out_y; reg [31:0] out_z; reg [31:0] out_o; reg [31:0] out_p; reg [31:0] out_q; assign out_x = {in_a[31:16] & in_f, in_a[15:0] & in_f}; assign out_y = {in_a[31:18] & in_b[31:18], in_a[17:0] & in_b[17:0]}; assign out_z = {in_c[31:14] & in_d[31:14] & in_e[31:14], in_c[13:0] & in_d[13:0] & in_e[13:0]}; assign out_o = out_z | out_y; assign out_p = {in_a[31:16] & in_f | in_e[31:16], in_a[15:0] & in_f | in_e[15:0]}; assign out_q = {{in_a[31:25] ^ in_g[31:25], in_a[24:16] ^ in_g[24:16]}, {in_a[15:5] ^ in_g[15:5], in_a[4:0] ^ in_g[4:0]}}; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; in_a <= cyc; in_b <= cyc + 1; in_c <= cyc + 3; in_d <= cyc + 8; in_e <= cyc; in_f <= cyc[15:0]; if (out_x != (in_a & {2{in_f}})) $stop; if (out_y != (in_a&in_b)) $stop; if (out_z != (in_e&in_d&in_c)) $stop; if (out_o != (((in_a&in_b)|(in_c&in_e&in_d)))) $stop; if (out_p != (in_a & {2{in_f}} | in_e)) $stop; if (out_q != (in_a ^ in_g)) $stop; if (cyc==100) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.042/test_regress/t/t_unconnected_bad.v0000644000542200017500000000043015101701376022710 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `unconnected_drive `unconnected_drive pull2 module t; endmodule verilator-5.042/test_regress/t/t_interface_ar3.py0000755000542200017500000000112715101701376022474 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile( fails=test.vlt_all, # Verilator unsupported, bug546 expect_filename=test.golden_filename) if not test.vlt_all: test.execute() test.passes() verilator-5.042/test_regress/t/t_xml_flat_pub_mod.out0000644000542200017500000000404515101701376023460 0ustar mahmoudyfreeshell verilator-5.042/test_regress/t/t_concat_unpack.py0000755000542200017500000000073415101701376022602 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_scope_vlt.vlt0000644000542200017500000000060015101701376023310 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `verilator_config tracing_off -scope "t*" -levels 0 tracing_on -scope "t.clk" tracing_on -scope "t.sub1a" -levels 1 tracing_on -scope "t.sub1b" -levels 2 tracing_off -scope "*.sub2a.ADD" verilator-5.042/test_regress/t/t_vlt_match_contents.vlt0000644000542200017500000000126415101701376024041 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Ethan Sifferman. // SPDX-License-Identifier: CC0-1.0 `verilator_config lint_off -rule DECLFILENAME -file "*/t_vlt_match_contents.v" -contents "* MATCH_VERSION*" lint_off -rule UNUSEDSIGNAL -file "*/t_vlt_match_contents.v" -contents "* MATCH_VERSION*" -match "*MATCH_VERSION*" lint_off -rule UNUSEDSIGNAL -file "*/t_vlt_match_contents.v" -contents "* MATCH_VERSION*" -match "*usignal_contents_suppress*" lint_off -rule UNUSEDSIGNAL -file "*/t_vlt_match_contents.v" -contents "* NOT_VERSION*" -match "*usignal_contents_mismatch*" verilator-5.042/test_regress/t/t_class_inc.py0000755000542200017500000000073415101701376021730 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_randomize_method_complex_bad.out0000644000542200017500000000072215101701376026030 0ustar mahmoudyfreeshell%Error: t/t_randomize_method_complex_bad.v:17:9: 'randomize() with' on a non-class-instance 'int' 17 | i.randomize() with { v < 5; }); | ^~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_randomize_method_complex_bad.v:17:28: Can't find definition of variable: 'v' 17 | i.randomize() with { v < 5; }); | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_class_param_comma_bad.out0000644000542200017500000000167215101701376024417 0ustar mahmoudyfreeshell%Error: t/t_class_param_comma_bad.v:16:22: syntax error, unexpected ')', expecting IDENTIFIER-for-type 16 | Cls #(.PARAMB(14),) ce; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_class_param_comma_bad.v:17:13: syntax error, unexpected ')', expecting IDENTIFIER-for-type 17 | Cls #(14,) cf; | ^ %Error: t/t_class_param_comma_bad.v:18:14: syntax error, unexpected ')', expecting IDENTIFIER-for-type 18 | Cls2 #(15,) cg; | ^ %Error: t/t_class_param_comma_bad.v:19:23: syntax error, unexpected ')', expecting IDENTIFIER-for-type 19 | Cls2 #(.PARAMB(16),) ch; | ^ %Error: t/t_class_param_comma_bad.v:20:23: syntax error, unexpected ')', expecting IDENTIFIER-for-type 20 | Cls2 #(.PARAMC(17),) ci; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_concat_opt.py0000755000542200017500000000073415101701376022123 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_find_ifc.v0000644000542200017500000000043115101701376023357 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface t_interface_find_ifc; logic [3:0] value; endinterface verilator-5.042/test_regress/t/t_package_identifier_bad.py0000755000542200017500000000076615101701376024402 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_vlt_warn_file_bad.out0000644000542200017500000000102515101701376023601 0ustar mahmoudyfreeshell%Warning-WIDTHTRUNC: t/t_vlt_warn_file_bad.v:11:17: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's CONST '64'h1' generates 64 bits. : ... note: In instance 't' 11 | int warn_t = 64'h1; | ^~~~~ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_package_twodeep.py0000755000542200017500000000073415101701376023114 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_select_width.v0000644000542200017500000000121515101701376022255 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Outputs vlan, // Inputs clk, pkt_data ); parameter WIDTH = 320; input clk; input [2559:0] pkt_data; output reg [15:0] vlan; always @(posedge clk) begin // verilator lint_off WIDTHCONCAT // verilator lint_off WIDTHTRUNC vlan <= pkt_data[ { (WIDTH-12), 3'b0 } - 1 -: 16]; // verilator lint_on WIDTHCONCAT // verilator lint_on WIDTHTRUNC end endmodule verilator-5.042/test_regress/t/t_hier_block_sc.py0000755000542200017500000000275315101701376022563 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_hier_block.v" # CI environment offers 2 VCPUs, 2 thread setting causes the following warning. # %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. # So use 6 threads here though it's not optimal in performance, but ok. # stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. test.clean_objs() test.compile(v_flags2=['t/t_hier_block.cpp'], verilator_flags2=[ '--sc', '--stats', '--hierarchical', '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"' ], threads=(6 if test.vltmt else 1)) test.execute() test.file_grep(test.obj_dir + "/Vsub0/sub0.sv", r'^module\s+(\S+)\s+', "sub0") test.file_grep(test.obj_dir + "/Vsub1/sub1.sv", r'^module\s+(\S+)\s+', "sub1") test.file_grep(test.obj_dir + "/Vsub2/sub2.sv", r'^module\s+(\S+)\s+', "sub2") test.file_grep(test.stats, r'HierBlock,\s+Hierarchical blocks\s+(\d+)', 14) test.file_grep(test.run_log_filename, r'MACRO:(\S+) is defined', "cplusplus") test.passes() verilator-5.042/test_regress/t/t_pp_resetall_bad.out0000644000542200017500000000050315101701376023260 0ustar mahmoudyfreeshell%Error: t/t_pp_resetall_bad.v:9:1: syntax error, unexpected `resetall 9 | `resetall | ^~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Cannot continue ... This fatal error may be caused by the earlier error(s); resolve those first. verilator-5.042/test_regress/t/t_std_randomize_mod.v0000644000542200017500000000152215101701376023301 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by PlanV GmbH. // SPDX-License-Identifier: CC0-1.0 module t_scope_std_randomize; bit [7:0] addr; bit [15:0] data; function bit run(); int ready; int success; bit [7:0] old_addr; bit [15:0] old_data; int old_ready; old_addr = addr; old_data = data; old_ready = ready; success = randomize(addr, ready); // std::randomize if (success == 0) return 0; if (addr == old_addr && data != old_data && ready == old_ready) begin return 0; end return 1; endfunction initial begin bit ok = 0; int success; ok = 0; ok = run(); if (!ok) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_class_param_bad_paren.py0000755000542200017500000000076615101701376024257 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_time.v0000644000542200017500000000356615101701376020550 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Paul Wright. // SPDX-License-Identifier: CC0-1.0 /* Working through the $time example from IEEE Std 1364-2005 ** Section 17.7.1 ** The example uses a 10ns timeunit with a 1ns timeprecision ** For 16ns $time should return 2 ** For 32ns $time should return 3 **/ `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t (); timeunit 10ns; timeprecision 1ns; longint should_be_2, should_be_3; real should_be_1p6, should_be_3p2; initial begin : initial_blk1 should_be_2 = 0; should_be_3 = 0; #(16ns); $display("$time=%0t=%0d, $realtime=%g", $time(), $time(), $realtime()); should_be_2 = $time(); should_be_1p6 = $realtime(); #(16ns); $display("$time=%0t=%0d, $realtime=%g", $time(), $time(), $realtime()); should_be_3 = $time(); should_be_3p2 = $realtime(); #(16ns); $finish(1); end initial begin : initial_blk2 #(100ns); $display("%%Error: We should not get here"); $stop; end function bit real_chk(input real tvar, input real evar); real diff; diff = tvar - evar; return (diff < 1e-9) && (diff > -1e-9); endfunction final begin : last_blk $display("Info: should_be_2 = %0d", should_be_2); $display("Info: should_be_3 = %0d", should_be_3); `checkd(should_be_2, 2); `checkd(should_be_3, 3); chk_2 : assert(should_be_2 == 2); chk_3 : assert(should_be_3 == 3); chk_1p6 : assert(real_chk(should_be_1p6, 1.6)); chk_3p2 : assert(real_chk(should_be_3p2, 3.2)); $write("*-* All Finished *-*\n"); end endmodule verilator-5.042/test_regress/t/t_var_ref.v0000644000542200017500000000357615101701376021237 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv));; end while(0); module t(/*AUTOARG*/ // Inputs clk ); input clk; int cyc; int vr; int va[2]; `ifdef T_NOINLINE // verilator no_inline_module `endif //==== task fun(ref int r, const ref int c); `ifdef T_NOINLINE // verilator no_inline_task `endif `checkh(c, 32'h1234); r = 32'h4567; endtask initial begin int ci; int ri; ci = 32'h1234; fun(ri, ci); `checkh(ri, 32'h4567); end //==== task fun_array(ref int af[2], const ref int cf[2]); `ifdef T_NOINLINE // verilator no_inline_task `endif `checkh(cf[0], 32'h1234); `checkh(cf[1], 32'h2345); af[0] = 32'h5678; af[1] = 32'h6789; endtask // Not checkint - element of unpacked array initial begin int ca[2]; int ra[2]; ca[0] = 32'h1234; ca[1] = 32'h2345; fun_array(ra, ca); `checkh(ra[0], 32'h5678); `checkh(ra[1], 32'h6789); end //==== sub sub(.clk, .vr, .va); always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 0) begin vr <= 32'h789; va[0] <= 32'h89a; va[1] <= 32'h9ab; end else if (cyc == 2) begin `checkh(vr, 32'h987); `checkh(va[0], 32'ha98); `checkh(va[1], 32'ha9b); $write("*-* All Finished *-*\n"); $finish; end end endmodule module sub(input clk, ref int vr, ref int va[2]); always @(posedge clk) begin vr <= 32'h987; va[0] <= 32'ha98; va[1] <= 32'ha9b; end endmodule verilator-5.042/test_regress/t/t_force_readwrite_unsup.out0000644000542200017500000000073715101701376024547 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_force_readwrite_unsup.v:25:18: Unsupported: Signals used via read-write reference cannot be forced 25 | cls.take_ref(a); | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_force_readwrite_unsup.v:26:18: Unsupported: Signals used via read-write reference cannot be forced 26 | cls.take_ref(b); | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_interface_generic_modport_function2.py0000755000542200017500000000101315101701376027150 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(timing_loop=True, verilator_flags2=['--timing']) test.execute() test.passes() verilator-5.042/test_regress/t/t_randomize_local_param.py0000755000542200017500000000070615101701376024313 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.042/test_regress/t/t_inside3.py0000755000542200017500000000073415101701376021330 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_foreach_noivar.v0000644000542200017500000000137215101701376022570 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t; reg [63:0] sum; // Checked not in objects reg [2:1] [4:3] array [5:6] [7:8]; initial begin sum = 0; foreach (array[]) begin // NOP ++sum; end `checkh(sum, 0); sum = 0; foreach (array[,,]) begin // NOP ++sum; end `checkh(sum, 0); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_class_local_typedef_bad.py0000755000542200017500000000076615101701376024604 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_tri_inout_pins_inout.py0000755000542200017500000000125415101701376024253 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.top_filename = "t/t_tri_inout.v" test.scenarios('vlt_all') test.pli_filename = "t/t_tri_inout.cpp" test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe --pins-inout-enables", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_math_reverse.v0000644000542200017500000000446415101701376022274 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg [7:0] crc; // Build up assignments wire [7:0] bitrev; assign bitrev[7] = crc[0]; assign bitrev[6] = crc[1]; assign bitrev[5] = crc[2]; assign bitrev[4] = crc[3]; assign bitrev[0] = crc[7]; assign bitrev[1] = crc[6]; assign bitrev[2] = crc[5]; assign bitrev[3] = crc[4]; // Build up always assignments reg [7:0] bitrevb; always @ (/*AS*/crc) begin bitrevb[7] = crc[0]; bitrevb[6] = crc[1]; bitrevb[5] = crc[2]; bitrevb[4] = crc[3]; bitrevb[0] = crc[7]; bitrevb[1] = crc[6]; bitrevb[2] = crc[5]; bitrevb[3] = crc[4]; end // Build up always assignments reg [7:0] bitrevr; always @ (posedge clk) begin bitrevr[7] <= crc[0]; bitrevr[6] <= crc[1]; bitrevr[5] <= crc[2]; bitrevr[4] <= crc[3]; bitrevr[0] <= crc[7]; bitrevr[1] <= crc[6]; bitrevr[2] <= crc[5]; bitrevr[3] <= crc[4]; end always @ (posedge clk) begin if (cyc!=0) begin cyc<=cyc+1; //$write("cyc=%0d crc=%x r=%x\n", cyc, crc, bitrev); crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; if (cyc==1) begin crc <= 8'hed; end if (cyc==2 && bitrev!=8'hb7) $stop; if (cyc==3 && bitrev!=8'h5b) $stop; if (cyc==4 && bitrev!=8'h2d) $stop; if (cyc==5 && bitrev!=8'h16) $stop; if (cyc==6 && bitrev!=8'h8b) $stop; if (cyc==7 && bitrev!=8'hc5) $stop; if (cyc==8 && bitrev!=8'he2) $stop; if (cyc==9 && bitrev!=8'hf1) $stop; if (bitrevb != bitrev) $stop; if (cyc==3 && bitrevr!=8'hb7) $stop; if (cyc==4 && bitrevr!=8'h5b) $stop; if (cyc==5 && bitrevr!=8'h2d) $stop; if (cyc==6 && bitrevr!=8'h16) $stop; if (cyc==7 && bitrevr!=8'h8b) $stop; if (cyc==8 && bitrevr!=8'hc5) $stop; if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.042/test_regress/t/t_clocking_sched_timing_forkproc.py0000755000542200017500000000112315101701376026176 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_clocking_sched.v" test.compile(timing_loop=True, verilator_flags2=["--timing"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_nba_mixed_update_clocked.py0000755000542200017500000000164015101701376024743 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(verilator_flags2=["--stats", "--unroll-count", "1"]) test.execute() test.file_grep(test.stats, r'NBA, variables using ShadowVar scheme\s+(\d+)', 1) test.file_grep(test.stats, r'NBA, variables using ShadowVarMasked scheme\s+(\d+)', 2) test.file_grep(test.stats, r'NBA, variables using FlagUnique scheme\s+(\d+)', 1) test.file_grep(test.stats, r'Optimizations, Loop unrolling, Unrolled loops\s+(\d+)', 0) test.file_grep_not(test.stats, r'Warnings, Suppressed BLKANDNBLK') test.passes() verilator-5.042/test_regress/t/t_dfg_multidriver_dfg_bad.v0000644000542200017500000000303515101701376024415 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 `default_nettype none module t( input wire [10:0] i, input wire [10:0] j [4], input wire [10:0] k [4], output wire [10:0] o ); logic [10:0] a; assign a[3:0] = i[3:0]; assign a[4:1] = ~i[4:1]; assign a[3] = ~i[3]; assign a[8:5] = i[8:5]; assign a[7:6] = ~i[7:6]; assign a[9] = i[9]; assign a[9] = ~i[9]; assign a[10] = i[10]; logic [10:0] u [4]; assign u = j; assign u = k; logic [10:0] v [4]; assign v = j; assign v[1] = i; logic [10:0] w [4]; assign w[0] = i; assign w = j; logic [10:0] x [4]; assign x[3] = i; assign x[3][3:2] = ~i[1:0]; // No warning for w[2]! assign x[2][3:2] = ~i[1:0]; assign x[2][1:0] = ~i[1:0]; logic [10:0] y; always_comb begin y = i; {y[1:0], y[2:1]} = i[3:0] + 4'd5; end logic [10:0] z; always_comb begin z[2:0] = i[2:0]; z[7:5] = i[7:5]; end always_comb begin z[6:4] = i[6:4]; z[3:1] = i[3:1]; end assign z[10:7] = i[10:7]; sub sub_1(i); assign sub_1.a = i; sub sub_2(i); assign sub_2.a[10:5] = i[10:5]; assign sub_2.a[3:0] = i[3:0]; assign o = a ^ u[3] ^ v[3] ^ w[3] ^ x[3] ^ y ^ z ^ sub_1.a ^ sub_2.a; endmodule module sub(input wire [10:0] i); logic [10:0] a; assign a[5:2] = i[5:2]; endmodule verilator-5.042/test_regress/t/t_flag_make_cmake_sc.v0000644000542200017500000000057515101701376023342 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; always @ (posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_slice_struct_array_modport.py0000755000542200017500000000070615101701376025436 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.042/test_regress/t/t_class_func_dot.py0000755000542200017500000000073415101701376022760 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_mem_func.v0000644000542200017500000000611415101701376021373 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [2:0] q; // From test of Test.v // End of automatics Test test ( // Outputs .q (q[2:0]), // Inputs .clk (clk), .reset_l (crc[0]), .enable (crc[2]), .q_var0 (crc[19:10]), .q_var2 (crc[29:20]), .q_var4 (crc[39:30]), .q_var6 (crc[49:40]) /*AUTOINST*/); // Aggregate outputs into a single result vector wire [63:0] result = {61'h0,q}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; `define EXPECTED_SUM 64'h58b162c58d6e35ba if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test ( input clk, input reset_l, input enable, input [ 9:0] q_var0, input [ 9:0] q_var2, input [ 9:0] q_var4, input [ 9:0] q_var6, output reg [2:0] q ); reg [7:0] p1_r [6:0]; always @(posedge clk) begin if (!reset_l) begin p1_r[0] <= 'b0; p1_r[1] <= 'b0; p1_r[2] <= 'b0; p1_r[3] <= 'b0; p1_r[4] <= 'b0; p1_r[5] <= 'b0; p1_r[6] <= 'b0; end else if (enable) begin : pass1 match(q_var0, q_var2, q_var4, q_var6); end end // verilator lint_off WIDTH always @(posedge clk) begin : l reg [10:0] bd; reg [3:0] idx; q = 0; bd = 0; for (idx=0; idx<7; idx=idx+1) begin q = idx+1; bd = bd + p1_r[idx]; end end task match; input [9:0] p0, p1, p2, p3; reg [9:0] p[3:0]; begin p[0] = p0; p[1] = p1; p[2] = p2; p[3] = p3; p1_r[0] <= p[0]; p1_r[1] <= p[1]; end endtask endmodule verilator-5.042/test_regress/t/t_class_param_lvalue.py0000755000542200017500000000070615101701376023626 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.042/test_regress/t/t_package_struct.py0000755000542200017500000000100015101701376022754 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_define_override.py0000755000542200017500000000111415101701376023114 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["+define+TEST_MACRO=20 +define+TEST_MACRO=50"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_fork_repeat.py0000755000542200017500000000077115101701376022274 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_mem_slice_dtype_bad.out0000644000542200017500000000050315101701376024110 0ustar mahmoudyfreeshell%Error: t/t_mem_slice_dtype_bad.v:23:45: ADD unexpected in assignment to unpacked array 23 | completed_cnt[id] <= completed_cnt_dp + 1; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_runflag_uninit_bad.py0000755000542200017500000000110615101701376023616 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(v_flags2=["--savable --exe", test.pli_filename], make_main=False) test.execute(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_opt_dead_task.v0000644000542200017500000000202115101701376022374 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t ( input clk ); // AstLet and AstProperty are also NodeFTasks, but lets are substituted earlier and properties should be "used" by their asserts so also not deadified let nclk = ~clk; assert property (@(posedge clk) 1); function void livefunc(); endfunction task livetask; endtask // Tasks/functions that are called somewhere will not be deadified initial begin livefunc(); livetask(); $finish; end // These should be deadified task deadfunc(); deeptask2(); endtask task deadtask; deeptask1(); endtask // A chain of dead tasks calling each other to ensure V3Dead can remove chained dead tasks task deeptask1; deeptask2(); endtask task deeptask2; deeptask3(); endtask task deeptask3; deeptask4(); endtask task deeptask4; endtask endmodule verilator-5.042/test_regress/t/t_json_only_flat_pub_mod.v0000644000542200017500000000060715101701376024330 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module foo(input logic i_clk); /* verilator public_module */ endmodule // --flatten forces inlining of public module foo. module top(input logic i_clk); foo f(.*); endmodule verilator-5.042/test_regress/t/t_event_copy.v0000644000542200017500000001003015101701376021745 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `ifdef TEST_VERBOSE `define WRITE_VERBOSE(args) $write args `else `define WRITE_VERBOSE(args) `endif module t(/*AUTOARG*/ // Inputs clk ); input clk; event e1; event e2; event e3; event e4; `ifndef IVERILOG event ev [3:0]; `endif int cyc; int last_event; always @(e1) begin `WRITE_VERBOSE(("[%0t] e1\n", $time)); `ifndef IVERILOG if (!e1.triggered) $stop; `endif last_event[1] = 1; end always @(e2) begin `WRITE_VERBOSE(("[%0t] e2\n", $time)); last_event[2] = 1; end always @(e3) begin `WRITE_VERBOSE(("[%0t] e3\n", $time)); last_event[3] = 1; end always @(e4) begin `WRITE_VERBOSE(("[%0t] e4\n", $time)); last_event[4] = 1; end always @(posedge clk) begin `WRITE_VERBOSE(("[%0t] cyc=%0d last_event=%5b\n", $time, cyc, last_event)); cyc <= cyc + 1; if (cyc == 1) begin // Check no initial trigger if (last_event != 0) $stop; end // else if (cyc == 10) begin last_event = 0; -> e1; end else if (cyc == 12) begin if (last_event != 32'b10) $stop; last_event = 0; end else if (cyc == 13) begin // Check not still triggering if (last_event != 0) $stop; last_event = 0; end // else if (cyc == 20) begin last_event = 0; `ifdef IVERILOG -> e2; `else // Events are both references and events themselves. I.e. 'event e' // declaration means 'event e = new'. Then e is a reference to that // created event. // // Always having indirection is bad for performance, so Verilator // should have 'event e' as an "EVENTVALUE" stored as a char, or // ideally a one bit field reference (not vector as that can't be // V3Ordered). // // Then events once copied become EVENTREFs, much like a ClassRef which // points to an EVENTVALUE. Thus a Verilog "event" starts as an // EVENTVALUE, and if an assignment is made it becomes an EVENTVALUE // and an EVENTREF initing to that EVENTVALUE. // // All static scheduling for events would go out the window once an // event can be pointed to by an EVENTREF, as basically any EVENTREF // activation could be activating any event. A graph algorithm could // determine what events/eventrefs are associated and only // pessamistically schedule those events (users of EVENTVALUES) that // are ever pointed to by an EVENTREF. e4 = e3; // Old handle to e4 e3 = e2; // Same event, also triggers e2 // IEEE 1800-2023 15.5.5.1 says that this causes a merge, and the below // should also activate the "old e3". However we could not find any // simulator that actually does this. Instead the "old e3" becomes // unreachable (via old handle), but is reachable by "e4" as assigned // earlier. ->> e3; // Delayed `endif end else if (cyc == 22) begin if (last_event != 32'b100) $stop; last_event = 0; -> e2; // IEEE says triggers e3, but does not end else if (cyc == 24) begin if (last_event != 32'b100) $stop; last_event = 0; -> e4; // Triggers old e3 end else if (cyc == 26) begin if (last_event != 32'b1000) $stop; last_event = 0; end // else if (cyc == 30) begin last_event = 0; `ifndef IVERILOG e3 = null; -> e3; // Triggers nothing `endif end else if (cyc == 32) begin if (last_event != 0) $stop; last_event = 0; end else if (cyc == 99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_debug_sigsegv_bad.py0000755000542200017500000000136615101701376023417 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.setenv("ASAN_OPTIONS", "handle_segv=0") test.leak_check_disable() test.lint(v_flags=["--debug-sigsegv"], fails='any') test.file_grep(test.compile_log_filename, r'%Error: Verilator internal fault, sorry. Suggest trying --debug --gdbbt') test.file_grep(test.compile_log_filename, r'Command Failed') test.passes() verilator-5.042/test_regress/t/t_const_number_unsized_parse.py0000755000542200017500000000151415101701376025420 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') if test.have_dev_gcov: test.skip("Too slow with code coverage") test.top_filename = f"{test.obj_dir}/in.v" with open(test.top_filename, "w", encoding="utf8") as f: f.write("module top;\n") for i in range(50000): f.write(f" int x{i} = 'd{i};\n") f.write("endmodule\n") test.timeout(30 if not test.have_dev_asan else 60) test.lint(verilator_flags2=[f"--max-num-width {2**29}"]) test.passes() verilator-5.042/test_regress/t/t_dist_contributors.py0000755000542200017500000000516415101701376023554 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') Contributors = {'github action': True} Authors = {} def read_contributors(filename): with open(filename, 'r', encoding="utf8") as fh: # Assumes git .mailmap format for line in fh: line = line.rstrip() line = re.sub(r' *<[^>]*>', '', line) Contributors[line] = True def read_user(): cmd = "cd " + test.root + " && git diff-index --quiet HEAD --" changes = test.run_capture(cmd, check=False) changes = changes.rstrip() if changes == "": if test.verbose: print("No git changes") else: # Uncommitted changes, so check the user's git name user = test.run_capture("git config user.name") user = user.rstrip() if user: Authors[user] = True def read_authors(): # Check recent commits in case did commit cmd = "git log '--pretty=format:%aN <%aE>' | head -5" git_auths = test.run_capture(cmd) for line in git_auths.splitlines(): line = re.sub(r' *<[^>]*>', '', line) Authors[line] = True def check(): read_contributors(test.root + "/docs/CONTRIBUTORS") read_user() read_authors() for author in sorted(Authors.keys()): if test.verbose: print("Check: " + author) if re.search(r'\[bot\]', author): continue if author in Contributors: continue # Slower subset-of-string test ok = False for contrib2 in sorted(Contributors.keys()): if author in contrib2: ok = True break if ok: continue test.error("Certify your contribution by sorted-inserting '" + author + "' into docs/CONTRIBUTORS.\n" " If '" + author + "' is not your real name, please fix 'name=' in ~/.gitconfig\n" " Also check your https://github.com account's Settings->Profile->Name\n" " matches your ~/.gitconfig 'name='.\n") if 'VERILATOR_TEST_NO_CONTRIBUTORS' in os.environ: test.skip("Skipping due to VERILATOR_TEST_NO_CONTRIBUTORS") if not os.path.exists(test.root + "/.git"): test.skip("Not in a git repository") check() test.passes() verilator-5.042/test_regress/t/t_randomize_bbox.py0000755000542200017500000000102515101701376022766 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_randomize.v" test.lint(verilator_flags=["--bbox-unsup"], fails=True) test.passes() verilator-5.042/test_regress/t/t_vpi_dump.iv.out0000644000542200017500000003562415101701376022414 0ustar mahmoudyfreeshellt (vpiModule) t vpiNet: t.a (vpiNet) t.a t.clk (vpiNet) t.clk vpiReg: t.x (vpiReg) t.x vpiParameter: t.do_generate (vpiParameter) t.do_generate vpiConstType=vpiBinaryConst t.long_int (vpiParameter) t.long_int vpiConstType=vpiBinaryConst vpiPort: x (vpiPort) (null) clk (vpiPort) (null) a (vpiPort) (null) vpiInternalScope: t.arr[1] (vpiGenScope) t.arr[1] vpiParameter: t.arr[1].i (vpiParameter) t.arr[1].i vpiConstType=vpiBinaryConst vpiInternalScope: t.arr[1].arr (vpiModule) t.arr[1].arr vpiReg: t.arr[1].arr.check (vpiReg) t.arr[1].arr.check t.arr[1].arr.rfr (vpiReg) t.arr[1].arr.rfr t.arr[1].arr.sig (vpiReg) t.arr[1].arr.sig t.arr[1].arr.verbose (vpiReg) t.arr[1].arr.verbose vpiParameter: t.arr[1].arr.LENGTH (vpiParameter) t.arr[1].arr.LENGTH vpiConstType=vpiBinaryConst t.arr[2] (vpiGenScope) t.arr[2] vpiParameter: t.arr[2].i (vpiParameter) t.arr[2].i vpiConstType=vpiBinaryConst vpiInternalScope: t.arr[2].arr (vpiModule) t.arr[2].arr vpiReg: t.arr[2].arr.check (vpiReg) t.arr[2].arr.check t.arr[2].arr.rfr (vpiReg) t.arr[2].arr.rfr t.arr[2].arr.sig (vpiReg) t.arr[2].arr.sig t.arr[2].arr.verbose (vpiReg) t.arr[2].arr.verbose vpiParameter: t.arr[2].arr.LENGTH (vpiParameter) t.arr[2].arr.LENGTH vpiConstType=vpiBinaryConst t.cond_scope (vpiGenScope) t.cond_scope vpiParameter: t.cond_scope.scoped_wire (vpiParameter) t.cond_scope.scoped_wire vpiConstType=vpiBinaryConst vpiInternalScope: t.cond_scope.scoped_sub (vpiModule) t.cond_scope.scoped_sub vpiNet: t.cond_scope.scoped_sub.redundant (vpiNet) t.cond_scope.scoped_sub.redundant vpiReg: t.cond_scope.scoped_sub.subsig1 (vpiReg) t.cond_scope.scoped_sub.subsig1 t.cond_scope.scoped_sub.subsig2 (vpiReg) t.cond_scope.scoped_sub.subsig2 t.cond_scope.sub_wrap_gen (vpiModule) t.cond_scope.sub_wrap_gen vpiInternalScope: t.cond_scope.sub_wrap_gen.my_sub (vpiModule) t.cond_scope.sub_wrap_gen.my_sub vpiNet: t.cond_scope.sub_wrap_gen.my_sub.redundant (vpiNet) t.cond_scope.sub_wrap_gen.my_sub.redundant vpiReg: t.cond_scope.sub_wrap_gen.my_sub.subsig1 (vpiReg) t.cond_scope.sub_wrap_gen.my_sub.subsig1 t.cond_scope.sub_wrap_gen.my_sub.subsig2 (vpiReg) t.cond_scope.sub_wrap_gen.my_sub.subsig2 t.intf_arr[0] (vpiModule) t.intf_arr[0] t.intf_arr[1] (vpiModule) t.intf_arr[1] t.outer_scope[1] (vpiGenScope) t.outer_scope[1] vpiParameter: t.outer_scope[1].i (vpiParameter) t.outer_scope[1].i vpiConstType=vpiBinaryConst t.outer_scope[1].scoped_param (vpiParameter) t.outer_scope[1].scoped_param vpiConstType=vpiBinaryConst vpiInternalScope: t.outer_scope[1].inner_scope[1] (vpiGenScope) t.outer_scope[1].inner_scope[1] vpiParameter: t.outer_scope[1].inner_scope[1].j (vpiParameter) t.outer_scope[1].inner_scope[1].j vpiConstType=vpiBinaryConst t.outer_scope[1].inner_scope[1].scoped_param_inner (vpiParameter) t.outer_scope[1].inner_scope[1].scoped_param_inner vpiConstType=vpiBinaryConst vpiInternalScope: t.outer_scope[1].inner_scope[1].arr (vpiModule) t.outer_scope[1].inner_scope[1].arr vpiReg: t.outer_scope[1].inner_scope[1].arr.check (vpiReg) t.outer_scope[1].inner_scope[1].arr.check t.outer_scope[1].inner_scope[1].arr.rfr (vpiReg) t.outer_scope[1].inner_scope[1].arr.rfr t.outer_scope[1].inner_scope[1].arr.sig (vpiReg) t.outer_scope[1].inner_scope[1].arr.sig t.outer_scope[1].inner_scope[1].arr.verbose (vpiReg) t.outer_scope[1].inner_scope[1].arr.verbose vpiParameter: t.outer_scope[1].inner_scope[1].arr.LENGTH (vpiParameter) t.outer_scope[1].inner_scope[1].arr.LENGTH vpiConstType=vpiBinaryConst t.outer_scope[1].inner_scope[2] (vpiGenScope) t.outer_scope[1].inner_scope[2] vpiParameter: t.outer_scope[1].inner_scope[2].j (vpiParameter) t.outer_scope[1].inner_scope[2].j vpiConstType=vpiBinaryConst t.outer_scope[1].inner_scope[2].scoped_param_inner (vpiParameter) t.outer_scope[1].inner_scope[2].scoped_param_inner vpiConstType=vpiBinaryConst vpiInternalScope: t.outer_scope[1].inner_scope[2].arr (vpiModule) t.outer_scope[1].inner_scope[2].arr vpiReg: t.outer_scope[1].inner_scope[2].arr.check (vpiReg) t.outer_scope[1].inner_scope[2].arr.check t.outer_scope[1].inner_scope[2].arr.rfr (vpiReg) t.outer_scope[1].inner_scope[2].arr.rfr t.outer_scope[1].inner_scope[2].arr.sig (vpiReg) t.outer_scope[1].inner_scope[2].arr.sig t.outer_scope[1].inner_scope[2].arr.verbose (vpiReg) t.outer_scope[1].inner_scope[2].arr.verbose vpiParameter: t.outer_scope[1].inner_scope[2].arr.LENGTH (vpiParameter) t.outer_scope[1].inner_scope[2].arr.LENGTH vpiConstType=vpiBinaryConst t.outer_scope[1].inner_scope[3] (vpiGenScope) t.outer_scope[1].inner_scope[3] vpiParameter: t.outer_scope[1].inner_scope[3].j (vpiParameter) t.outer_scope[1].inner_scope[3].j vpiConstType=vpiBinaryConst t.outer_scope[1].inner_scope[3].scoped_param_inner (vpiParameter) t.outer_scope[1].inner_scope[3].scoped_param_inner vpiConstType=vpiBinaryConst vpiInternalScope: t.outer_scope[1].inner_scope[3].arr (vpiModule) t.outer_scope[1].inner_scope[3].arr vpiReg: t.outer_scope[1].inner_scope[3].arr.check (vpiReg) t.outer_scope[1].inner_scope[3].arr.check t.outer_scope[1].inner_scope[3].arr.rfr (vpiReg) t.outer_scope[1].inner_scope[3].arr.rfr t.outer_scope[1].inner_scope[3].arr.sig (vpiReg) t.outer_scope[1].inner_scope[3].arr.sig t.outer_scope[1].inner_scope[3].arr.verbose (vpiReg) t.outer_scope[1].inner_scope[3].arr.verbose vpiParameter: t.outer_scope[1].inner_scope[3].arr.LENGTH (vpiParameter) t.outer_scope[1].inner_scope[3].arr.LENGTH vpiConstType=vpiBinaryConst t.outer_scope[2] (vpiGenScope) t.outer_scope[2] vpiParameter: t.outer_scope[2].i (vpiParameter) t.outer_scope[2].i vpiConstType=vpiBinaryConst t.outer_scope[2].scoped_param (vpiParameter) t.outer_scope[2].scoped_param vpiConstType=vpiBinaryConst vpiInternalScope: t.outer_scope[2].inner_scope[1] (vpiGenScope) t.outer_scope[2].inner_scope[1] vpiParameter: t.outer_scope[2].inner_scope[1].j (vpiParameter) t.outer_scope[2].inner_scope[1].j vpiConstType=vpiBinaryConst t.outer_scope[2].inner_scope[1].scoped_param_inner (vpiParameter) t.outer_scope[2].inner_scope[1].scoped_param_inner vpiConstType=vpiBinaryConst vpiInternalScope: t.outer_scope[2].inner_scope[1].arr (vpiModule) t.outer_scope[2].inner_scope[1].arr vpiReg: t.outer_scope[2].inner_scope[1].arr.check (vpiReg) t.outer_scope[2].inner_scope[1].arr.check t.outer_scope[2].inner_scope[1].arr.rfr (vpiReg) t.outer_scope[2].inner_scope[1].arr.rfr t.outer_scope[2].inner_scope[1].arr.sig (vpiReg) t.outer_scope[2].inner_scope[1].arr.sig t.outer_scope[2].inner_scope[1].arr.verbose (vpiReg) t.outer_scope[2].inner_scope[1].arr.verbose vpiParameter: t.outer_scope[2].inner_scope[1].arr.LENGTH (vpiParameter) t.outer_scope[2].inner_scope[1].arr.LENGTH vpiConstType=vpiBinaryConst t.outer_scope[2].inner_scope[2] (vpiGenScope) t.outer_scope[2].inner_scope[2] vpiParameter: t.outer_scope[2].inner_scope[2].j (vpiParameter) t.outer_scope[2].inner_scope[2].j vpiConstType=vpiBinaryConst t.outer_scope[2].inner_scope[2].scoped_param_inner (vpiParameter) t.outer_scope[2].inner_scope[2].scoped_param_inner vpiConstType=vpiBinaryConst vpiInternalScope: t.outer_scope[2].inner_scope[2].arr (vpiModule) t.outer_scope[2].inner_scope[2].arr vpiReg: t.outer_scope[2].inner_scope[2].arr.check (vpiReg) t.outer_scope[2].inner_scope[2].arr.check t.outer_scope[2].inner_scope[2].arr.rfr (vpiReg) t.outer_scope[2].inner_scope[2].arr.rfr t.outer_scope[2].inner_scope[2].arr.sig (vpiReg) t.outer_scope[2].inner_scope[2].arr.sig t.outer_scope[2].inner_scope[2].arr.verbose (vpiReg) t.outer_scope[2].inner_scope[2].arr.verbose vpiParameter: t.outer_scope[2].inner_scope[2].arr.LENGTH (vpiParameter) t.outer_scope[2].inner_scope[2].arr.LENGTH vpiConstType=vpiBinaryConst t.outer_scope[2].inner_scope[3] (vpiGenScope) t.outer_scope[2].inner_scope[3] vpiParameter: t.outer_scope[2].inner_scope[3].j (vpiParameter) t.outer_scope[2].inner_scope[3].j vpiConstType=vpiBinaryConst t.outer_scope[2].inner_scope[3].scoped_param_inner (vpiParameter) t.outer_scope[2].inner_scope[3].scoped_param_inner vpiConstType=vpiBinaryConst vpiInternalScope: t.outer_scope[2].inner_scope[3].arr (vpiModule) t.outer_scope[2].inner_scope[3].arr vpiReg: t.outer_scope[2].inner_scope[3].arr.check (vpiReg) t.outer_scope[2].inner_scope[3].arr.check t.outer_scope[2].inner_scope[3].arr.rfr (vpiReg) t.outer_scope[2].inner_scope[3].arr.rfr t.outer_scope[2].inner_scope[3].arr.sig (vpiReg) t.outer_scope[2].inner_scope[3].arr.sig t.outer_scope[2].inner_scope[3].arr.verbose (vpiReg) t.outer_scope[2].inner_scope[3].arr.verbose vpiParameter: t.outer_scope[2].inner_scope[3].arr.LENGTH (vpiParameter) t.outer_scope[2].inner_scope[3].arr.LENGTH vpiConstType=vpiBinaryConst t.outer_scope[3] (vpiGenScope) t.outer_scope[3] vpiParameter: t.outer_scope[3].i (vpiParameter) t.outer_scope[3].i vpiConstType=vpiBinaryConst t.outer_scope[3].scoped_param (vpiParameter) t.outer_scope[3].scoped_param vpiConstType=vpiBinaryConst vpiInternalScope: t.outer_scope[3].inner_scope[1] (vpiGenScope) t.outer_scope[3].inner_scope[1] vpiParameter: t.outer_scope[3].inner_scope[1].j (vpiParameter) t.outer_scope[3].inner_scope[1].j vpiConstType=vpiBinaryConst t.outer_scope[3].inner_scope[1].scoped_param_inner (vpiParameter) t.outer_scope[3].inner_scope[1].scoped_param_inner vpiConstType=vpiBinaryConst vpiInternalScope: t.outer_scope[3].inner_scope[1].arr (vpiModule) t.outer_scope[3].inner_scope[1].arr vpiReg: t.outer_scope[3].inner_scope[1].arr.check (vpiReg) t.outer_scope[3].inner_scope[1].arr.check t.outer_scope[3].inner_scope[1].arr.rfr (vpiReg) t.outer_scope[3].inner_scope[1].arr.rfr t.outer_scope[3].inner_scope[1].arr.sig (vpiReg) t.outer_scope[3].inner_scope[1].arr.sig t.outer_scope[3].inner_scope[1].arr.verbose (vpiReg) t.outer_scope[3].inner_scope[1].arr.verbose vpiParameter: t.outer_scope[3].inner_scope[1].arr.LENGTH (vpiParameter) t.outer_scope[3].inner_scope[1].arr.LENGTH vpiConstType=vpiBinaryConst t.outer_scope[3].inner_scope[2] (vpiGenScope) t.outer_scope[3].inner_scope[2] vpiParameter: t.outer_scope[3].inner_scope[2].j (vpiParameter) t.outer_scope[3].inner_scope[2].j vpiConstType=vpiBinaryConst t.outer_scope[3].inner_scope[2].scoped_param_inner (vpiParameter) t.outer_scope[3].inner_scope[2].scoped_param_inner vpiConstType=vpiBinaryConst vpiInternalScope: t.outer_scope[3].inner_scope[2].arr (vpiModule) t.outer_scope[3].inner_scope[2].arr vpiReg: t.outer_scope[3].inner_scope[2].arr.check (vpiReg) t.outer_scope[3].inner_scope[2].arr.check t.outer_scope[3].inner_scope[2].arr.rfr (vpiReg) t.outer_scope[3].inner_scope[2].arr.rfr t.outer_scope[3].inner_scope[2].arr.sig (vpiReg) t.outer_scope[3].inner_scope[2].arr.sig t.outer_scope[3].inner_scope[2].arr.verbose (vpiReg) t.outer_scope[3].inner_scope[2].arr.verbose vpiParameter: t.outer_scope[3].inner_scope[2].arr.LENGTH (vpiParameter) t.outer_scope[3].inner_scope[2].arr.LENGTH vpiConstType=vpiBinaryConst t.outer_scope[3].inner_scope[3] (vpiGenScope) t.outer_scope[3].inner_scope[3] vpiParameter: t.outer_scope[3].inner_scope[3].j (vpiParameter) t.outer_scope[3].inner_scope[3].j vpiConstType=vpiBinaryConst t.outer_scope[3].inner_scope[3].scoped_param_inner (vpiParameter) t.outer_scope[3].inner_scope[3].scoped_param_inner vpiConstType=vpiBinaryConst vpiInternalScope: t.outer_scope[3].inner_scope[3].arr (vpiModule) t.outer_scope[3].inner_scope[3].arr vpiReg: t.outer_scope[3].inner_scope[3].arr.check (vpiReg) t.outer_scope[3].inner_scope[3].arr.check t.outer_scope[3].inner_scope[3].arr.rfr (vpiReg) t.outer_scope[3].inner_scope[3].arr.rfr t.outer_scope[3].inner_scope[3].arr.sig (vpiReg) t.outer_scope[3].inner_scope[3].arr.sig t.outer_scope[3].inner_scope[3].arr.verbose (vpiReg) t.outer_scope[3].inner_scope[3].arr.verbose vpiParameter: t.outer_scope[3].inner_scope[3].arr.LENGTH (vpiParameter) t.outer_scope[3].inner_scope[3].arr.LENGTH vpiConstType=vpiBinaryConst t.sub (vpiModule) t.sub vpiNet: t.sub.redundant (vpiNet) t.sub.redundant vpiReg: t.sub.subsig1 (vpiReg) t.sub.subsig1 t.sub.subsig2 (vpiReg) t.sub.subsig2 t.sub_wrap (vpiModule) t.sub_wrap vpiInternalScope: t.sub_wrap.my_sub (vpiModule) t.sub_wrap.my_sub vpiNet: t.sub_wrap.my_sub.redundant (vpiNet) t.sub_wrap.my_sub.redundant vpiReg: t.sub_wrap.my_sub.subsig1 (vpiReg) t.sub_wrap.my_sub.subsig1 t.sub_wrap.my_sub.subsig2 (vpiReg) t.sub_wrap.my_sub.subsig2 *-* All Finished *-* t/t_vpi_dump.v:76: $finish called at 0 (1s) verilator-5.042/test_regress/t/t_interface_generic_function.v0000644000542200017500000000114715101701376025144 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 interface inf; int v; function int get(); return v; endfunction endinterface interface inf2; int k; endinterface module GenericModule (interface a); initial begin #1; if (a.get() != 4) $stop; end endmodule module t; inf inf_inst(); GenericModule genericModule (inf_inst); initial begin inf_inst.v = 4; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_leak.v0000644000542200017500000000107015101701376020512 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); sub sub (); input clk; integer cyc=1; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==2) begin // Not $finish; as we don't want a message to scroll by $c("Verilated::threadContextp()->gotFinish(true);"); end end endmodule module sub; /* verilator public_module */ endmodule verilator-5.042/test_regress/t/t_func_return.v0000644000542200017500000000335715101701376022142 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // bug420 typedef logic [7-1:0] wb_ind_t; typedef logic [7-1:0] id_t; module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; /*AUTOWIRE*/ wire [6:0] out = line_wb_ind( in[6:0] ); // Aggregate outputs into a single result vector wire [63:0] result = {57'h0, out}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'hc918fa0aa882a206 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end function wb_ind_t line_wb_ind( id_t id ); if( id[$bits(id_t)-1] == 0 ) return {2'b00, id[$bits(wb_ind_t)-3:0]}; else return {2'b01, id[$bits(wb_ind_t)-3:0]}; endfunction // line_wb_ind endmodule verilator-5.042/test_regress/t/t_vpi_time_cb_c.cpp0000644000542200017500000001133015101701376022675 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "vpi_user.h" #include #include #include #include extern "C" { #include } // These require the above. Comment prevents clang-format moving them #include "TestCheck.h" #include "TestSimulator.h" #include "TestVpi.h" int errors = 0; unsigned int callback_count1 = 0; unsigned int callback_count2 = 0; unsigned int callback_time1 = 0; unsigned int callback_time2 = 0; //====================================================================== static int _never_cb(p_cb_data cb_data) { TEST_CHECK_EQ(0, 1); // Should never get called return 0; } static int _time_cb1(p_cb_data cb_data) { s_vpi_time t; t.type = vpiSimTime; vpi_get_time(0, &t); TEST_VERBOSE_PRINTF("time_cb1: %d\n", t.low); ++callback_count1; if (callback_time1) TEST_CHECK_EQ(callback_time1, t.low); callback_time1 = t.low + 1; // Next call t_cb_data cb_data_n; bzero(&cb_data_n, sizeof(cb_data_n)); { cb_data_n.reason = cbAfterDelay; t.type = vpiSimTime; t.high = 0; t.low = 1; cb_data_n.time = &t; cb_data_n.cb_rtn = _time_cb1; TestVpiHandle cb_data_n1_h = vpi_register_cb(&cb_data_n); TEST_CHECK_EQ(vpi_get(vpiType, cb_data_n1_h), vpiCallback); } { // Test cancelling a callback cb_data_n.reason = cbAfterDelay; t.type = vpiSimTime; t.high = 0; t.low = 1; cb_data_n.time = &t; cb_data_n.cb_rtn = _never_cb; TestVpiHandle cb_h = vpi_register_cb(&cb_data_n); vpi_remove_cb(cb_h); cb_h.freed(); } return 0; } static int _time_cb2(p_cb_data cb_data) { // One-shot s_vpi_time t; t.type = vpiSimTime; vpi_get_time(0, &t); TEST_VERBOSE_PRINTF("time_cb2: %d\n", t.low); if (callback_time2) TEST_CHECK_EQ(callback_time2, t.low); ++callback_count2; t_cb_data cb_data_n; bzero(&cb_data_n, sizeof(cb_data_n)); cb_data_n.reason = cbAfterDelay; t.type = vpiSimTime; t.high = 0; t.low = 1; cb_data_n.time = &t; cb_data_n.cb_rtn = _time_cb2; TestVpiHandle cb_data_n2_h = vpi_register_cb(&cb_data_n); TEST_CHECK_EQ(vpi_get(vpiType, cb_data_n2_h), vpiCallback); return 0; } static vpiHandle callback_handles3[2] = {NULL, NULL}; static int _time_cb3(p_cb_data cb_data) { size_t cb_id = (size_t)cb_data->user_data; size_t cb_id_other = cb_id ? 0 : 1; TEST_VERBOSE_PRINTF("time_cb_3: %d\n", (int)cb_id); TEST_CHECK_NZ(callback_handles3[cb_id]); TEST_CHECK_NZ(callback_handles3[cb_id_other]); vpi_remove_cb(callback_handles3[cb_id_other]); callback_handles3[0] = callback_handles3[1] = NULL; return 0; } extern "C" void dpii_init() { TEST_VERBOSE_PRINTF("-dpii_init()\n"); t_cb_data cb_data_n1, cb_data_n2, cb_data_n3; bzero(&cb_data_n1, sizeof(cb_data_n1)); bzero(&cb_data_n2, sizeof(cb_data_n2)); bzero(&cb_data_n3, sizeof(cb_data_n3)); s_vpi_time t1, t2, t3; cb_data_n1.reason = cbAfterDelay; t1.type = vpiSimTime; t1.high = 0; t1.low = 3; cb_data_n1.time = &t1; cb_data_n1.cb_rtn = _time_cb1; TestVpiHandle cb_data_n1_h = vpi_register_cb(&cb_data_n1); TEST_CHECK_EQ(vpi_get(vpiType, cb_data_n1_h), vpiCallback); cb_data_n2.reason = cbAfterDelay; t2.type = vpiSimTime; t2.high = 0; t2.low = 4; cb_data_n2.time = &t2; cb_data_n2.cb_rtn = _time_cb2; TestVpiHandle cb_data_n2_h = vpi_register_cb(&cb_data_n2); cb_data_n3.reason = cbAfterDelay; t3.type = vpiSimTime; t3.high = 0; t3.low = 5; cb_data_n3.time = &t3; cb_data_n3.cb_rtn = _time_cb3; cb_data_n3.user_data = (PLI_BYTE8*)0; callback_handles3[0] = vpi_register_cb(&cb_data_n3); cb_data_n3.user_data = (PLI_BYTE8*)1; callback_handles3[1] = vpi_register_cb(&cb_data_n3); } extern "C" void dpii_final() { TEST_VERBOSE_PRINTF("-dpii_final()\n"); // Allow some slop as cb might be before/after this call TEST_CHECK(callback_count1, 1010, (callback_count1 >= 1000 && callback_count1 <= 1020)); TEST_CHECK(callback_count2, 1010, (callback_count2 >= 1000 && callback_count2 <= 1020)); if (errors) { vpi_control(vpiStop); } else { printf("*-* All Finished *-*\n"); } } verilator-5.042/test_regress/t/t_covergroup_in_class.v0000644000542200017500000000066115101701376023651 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off COVERIGN */ class myClass; covergroup embeddedCg; endgroup function new(); real r; embeddedCg = new(); embeddedCg.sample(); r = embeddedCg.get_coverage(); endfunction endclass verilator-5.042/test_regress/t/t_var_nonamebegin.out0000644000542200017500000000233215101701376023274 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $var wire 1 # clk $end $var wire 1 $ reset_l $end $scope module t $end $var wire 1 # clk $end $var wire 1 $ reset_l $end $var wire 1 % inmod $end $var wire 32 & rawmod [31:0] $end $scope module genblk1 $end $var wire 32 ' ingen [31:0] $end $upscope $end $scope module unnamedblk1 $end $var wire 32 ( upa [31:0] $end $scope module d3nameda $end $var wire 32 ) d3a [31:0] $end $upscope $end $upscope $end $scope module unnamedblk2 $end $var wire 32 * b2 [31:0] $end $scope module b3named $end $var wire 32 + b3n [31:0] $end $upscope $end $scope module unnamedblk3 $end $var wire 32 , b3 [31:0] $end $scope module unnamedblk4 $end $var wire 32 - b4 [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 0# 0$ 0% b00000000000000000000000000000000 & b00000000000000000000000000000000 ' b00000000000000000000000000000000 ( b00000000000000000000000000000000 ) b00000000000000000000000000000000 * b00000000000000000000000000000000 + b00000000000000000000000000000000 , b00000000000000000000000000000000 - verilator-5.042/test_regress/t/t_opt_merge_cond_motion_branch.v0000644000542200017500000000130315101701376025463 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Based on ivtest's pr540.v by Steve Williams. module t; bit fail = 0; bit abort = 0; initial begin abort = 1; // Set here so it's non-constant, otherwise ifs gets folded begin: block if (abort) disable block; fail = 1; // Don't try to move this in order to merge the 2 ifs if (abort) $display("unreachable"); end if (fail) $error("block disable FAILED"); $write("*-* All Finished *-*\n"); $finish(0); end endmodule verilator-5.042/test_regress/t/t_interface_generic_bad4.py0000755000542200017500000000102515101701376024312 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=['--timing'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_for_break.py0000755000542200017500000000073415101701376021724 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_case_enum_incomplete_bad.out0000644000542200017500000000063715101701376025134 0ustar mahmoudyfreeshell%Warning-CASEINCOMPLETE: t/t_case_enum_incomplete_bad.v:14:14: Enum item 'S1' not covered by case 14 | unique case (state) | ^~~~ ... For warning description see https://verilator.org/warn/CASEINCOMPLETE?v=latest ... Use "/* verilator lint_off CASEINCOMPLETE */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_string_type_methods.py0000755000542200017500000000073415101701376024064 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_constraint_countones.py0000755000542200017500000000104615101701376024250 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_enum_public.cpp0000644000542200017500000000152115101701376022416 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include "Vt_enum_public.h" #include "Vt_enum_public_p3.h" #include "Vt_enum_public_p62.h" double sc_time_stamp() { return 0; } int main(int argc, char* argv[]) { Verilated::debug(0); Verilated::commandArgs(argc, argv); VM_PREFIX* topp = new VM_PREFIX; // Make sure public tag worked if (Vt_enum_public_p3::ZERO == Vt_enum_public_p3::ONE) {} if (Vt_enum_public_p62::ZERO == Vt_enum_public_p62::ALLONE) {} for (int i = 0; i < 10; i++) { // topp->eval(); } topp->final(); VL_DO_DANGLING(delete topp, topp); } verilator-5.042/test_regress/t/t_case_default_bad.v0000644000542200017500000000067015101701376023030 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs value ); input [3:0] value; always @ (/*AS*/value) begin case (value) default: $stop; 4'd0000: $stop; default: $stop; endcase end endmodule verilator-5.042/test_regress/t/t_dpi_arg_output_unpack.v0000644000542200017500000015505615101701376024202 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2020 by Yutetsu TAKATSUKASA. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VCS `define NO_TIME `endif `ifdef NC `define NO_TIME `define NO_INTEGER `define NO_SHORTREAL `endif `ifdef MS `define NO_BITS_TO_SCALAR `endif `ifdef VERILATOR `define NO_SHORTREAL `define NO_UNPACK_STRUCT `endif `ifdef NO_BITS_TO_SCALAR `define ARE_SAME(act, exp) ($bits((act)) == 1 ? (act) == ((exp) & 1) : (act) == (exp)) `else `define ARE_SAME(act, exp) ((act) == (($bits(act))'(exp))) `endif `define CHECK_VAL(act, exp) if (`ARE_SAME(act, exp)) begin \ if (ENABLE_VERBOSE_MESSAGE)$display(`"act`", ":", (act), " as expected"); \ end else begin \ $display("Mismatch %s expected:%d actual:%d at %d", `"act`", \ int'(exp), \ int'(act), `__LINE__); \ $stop; \ end `define CHECK_0D(val) \ `CHECK_VAL((val), 42) `define CHECK_1D(val) \ `CHECK_VAL(val[0], 43); \ `CHECK_VAL(val[1], 44) `define CHECK_2D(val) \ `CHECK_VAL(val[0][1], 45); \ `CHECK_VAL(val[1][1], 46); \ `CHECK_VAL(val[2][1], 47) `define CHECK_3D(val) \ `CHECK_VAL(val[0][0][0], 48); \ `CHECK_VAL(val[1][0][0], 49); \ `CHECK_VAL(val[2][0][0], 50); \ `CHECK_VAL(val[3][0][0], 51) `define CHECK_1D1(val) \ `CHECK_VAL(val[0], 52) `define CHECK_2D1(val) \ `CHECK_VAL(val[0][0], 53) `define CHECK_3D1(val) \ `CHECK_VAL(val[0][0][0], 54) `define CHECK_CHANDLE_VAL(act, exp) if ((act) == (exp)) begin \ if (ENABLE_VERBOSE_MESSAGE)$display(`"act`", ":non-null as expected"); \ end else begin \ $display("Mismatch %s expected:%s but %s at %d", `"act`", \ (exp) ? "null" : "non-null", (act) ? "null" : "non-null", `__LINE__); \ $stop; \ end `define CHECK_STRING_VAL(act, exp) if ((act) == (exp)) begin \ if (ENABLE_VERBOSE_MESSAGE)$display(`"act`", ":", (act), " as expected"); \ end else begin \ $display("Mismatch %s expected:%s actual:%s at %d", \ `"act`", (exp), (act), `__LINE__); \ $stop; \ end `define SET_VALUES(val) \ val[3][2][1] = 42; \ val[2][1][0] = 43; val[2][1][1] = 44; \ val[1][0][1] = 45; val[1][1][1] = 46; val[1][2][1] = 47; \ val[0][0][0] = 48; val[1][0][0] = 49; val[2][0][0] = 50; val[3][0][0] = 51 module t; localparam ENABLE_VERBOSE_MESSAGE = 0; // Legal output argument types for DPI functions //====================================================================== // Type definitions //====================================================================== typedef byte byte_array_t[4][3][2]; typedef byte byte_array1_t[1][1][1]; typedef byte unsigned byte_unsigned_array_t[4][3][2]; typedef byte unsigned byte_unsigned_array1_t[1][1][1]; typedef shortint shortint_array_t[4][3][2]; typedef shortint shortint_array1_t[1][1][1]; typedef shortint unsigned shortint_unsigned_array_t[4][3][2]; typedef shortint unsigned shortint_unsigned_array1_t[1][1][1]; typedef int int_array_t[4][3][2]; typedef int int_array1_t[1][1][1]; typedef int unsigned int_unsigned_array_t[4][3][2]; typedef int unsigned int_unsigned_array1_t[1][1][1]; typedef longint longint_array_t[4][3][2]; typedef longint longint_array1_t[1][1][1]; typedef longint unsigned longint_unsigned_array_t[4][3][2]; typedef longint unsigned longint_unsigned_array1_t[1][1][1]; `ifndef NO_TIME typedef time time_array_t[4][3][2]; typedef time time_array1_t[1][1][1]; `endif `ifndef NO_INTEGER typedef integer integer_array_t[4][3][2]; typedef integer integer_array1_t[1][1][1]; `endif typedef real real_array_t[4][3][2]; typedef real real_array1_t[1][1][1]; `ifndef NO_SHORTREAL typedef shortreal shortreal_array_t[4][3][2]; typedef shortreal shortreal_array1_t[1][1][1]; `endif typedef chandle chandle_array_t[4][3][2]; typedef chandle chandle_array1_t[1][1][1]; typedef string string_array_t[4][3][2]; typedef string string_array1_t[1][1][1]; typedef bit bit1_array_t[4][3][2]; typedef bit bit1_array1_t[1][1][1]; typedef bit [6:0] bit7_array_t[4][3][2]; typedef bit [6:0] bit7_array1_t[1][1][1]; typedef bit [120:0] bit121_array_t[4][3][2]; typedef bit [120:0] bit121_array1_t[1][1][1]; typedef logic logic1_array_t[4][3][2]; typedef logic logic1_array1_t[1][1][1]; typedef logic [6:0] logic7_array_t[4][3][2]; typedef logic [6:0] logic7_array1_t[1][1][1]; typedef logic [120:0] logic121_array_t[4][3][2]; typedef logic [120:0] logic121_array1_t[1][1][1]; typedef struct packed { logic [6:0] val; } pack_struct_t; typedef pack_struct_t pack_struct_array_t[4][3][2]; typedef pack_struct_t pack_struct_array1_t[1][1][1]; `ifndef NO_UNPACK_STRUCT typedef struct { logic [120:0] val; } unpack_struct_t; typedef unpack_struct_t unpack_struct_array_t[4][3][2]; typedef unpack_struct_t unpack_struct_array1_t[1][1][1]; `endif //====================================================================== // Imports //====================================================================== // Returns non-null pointer import "DPI-C" function chandle get_non_null(); import "DPI-C" function void i_byte_0d(output byte val); import "DPI-C" function void i_byte_1d(output byte val[2]); import "DPI-C" function void i_byte_2d(output byte val[3][2]); import "DPI-C" function void i_byte_3d(output byte_array_t val); import "DPI-C" function void i_byte_1d1(output byte val[1]); import "DPI-C" function void i_byte_2d1(output byte val[1][1]); import "DPI-C" function void i_byte_3d1(output byte_array1_t val); import "DPI-C" function void i_byte_unsigned_0d(output byte unsigned val); import "DPI-C" function void i_byte_unsigned_1d(output byte unsigned val[2]); import "DPI-C" function void i_byte_unsigned_2d(output byte unsigned val[3][2]); import "DPI-C" function void i_byte_unsigned_3d(output byte_unsigned_array_t val); import "DPI-C" function void i_byte_unsigned_1d1(output byte unsigned val[1]); import "DPI-C" function void i_byte_unsigned_2d1(output byte unsigned val[1][1]); import "DPI-C" function void i_byte_unsigned_3d1(output byte_unsigned_array1_t val); import "DPI-C" function void i_shortint_0d(output shortint val); import "DPI-C" function void i_shortint_1d(output shortint val[2]); import "DPI-C" function void i_shortint_2d(output shortint val[3][2]); import "DPI-C" function void i_shortint_3d(output shortint_array_t val); import "DPI-C" function void i_shortint_1d1(output shortint val[1]); import "DPI-C" function void i_shortint_2d1(output shortint val[1][1]); import "DPI-C" function void i_shortint_3d1(output shortint_array1_t val); import "DPI-C" function void i_shortint_unsigned_0d(output shortint unsigned val); import "DPI-C" function void i_shortint_unsigned_1d(output shortint unsigned val[2]); import "DPI-C" function void i_shortint_unsigned_2d(output shortint unsigned val[3][2]); import "DPI-C" function void i_shortint_unsigned_3d(output shortint_unsigned_array_t val); import "DPI-C" function void i_shortint_unsigned_1d1(output shortint unsigned val[1]); import "DPI-C" function void i_shortint_unsigned_2d1(output shortint unsigned val[1][1]); import "DPI-C" function void i_shortint_unsigned_3d1(output shortint_unsigned_array1_t val); import "DPI-C" function void i_int_0d(output int val); import "DPI-C" function void i_int_1d(output int val[2]); import "DPI-C" function void i_int_2d(output int val[3][2]); import "DPI-C" function void i_int_3d(output int_array_t val); import "DPI-C" function void i_int_1d1(output int val[1]); import "DPI-C" function void i_int_2d1(output int val[1][1]); import "DPI-C" function void i_int_3d1(output int_array1_t val); import "DPI-C" function void i_int_unsigned_0d(output int unsigned val); import "DPI-C" function void i_int_unsigned_1d(output int unsigned val[2]); import "DPI-C" function void i_int_unsigned_2d(output int unsigned val[3][2]); import "DPI-C" function void i_int_unsigned_3d(output int_unsigned_array_t val); import "DPI-C" function void i_int_unsigned_1d1(output int unsigned val[1]); import "DPI-C" function void i_int_unsigned_2d1(output int unsigned val[1][1]); import "DPI-C" function void i_int_unsigned_3d1(output int_unsigned_array1_t val); import "DPI-C" function void i_longint_0d(output longint val); import "DPI-C" function void i_longint_1d(output longint val[2]); import "DPI-C" function void i_longint_2d(output longint val[3][2]); import "DPI-C" function void i_longint_3d(output longint_array_t val); import "DPI-C" function void i_longint_1d1(output longint val[1]); import "DPI-C" function void i_longint_2d1(output longint val[1][1]); import "DPI-C" function void i_longint_3d1(output longint_array1_t val); import "DPI-C" function void i_longint_unsigned_0d(output longint unsigned val); import "DPI-C" function void i_longint_unsigned_1d(output longint unsigned val[2]); import "DPI-C" function void i_longint_unsigned_2d(output longint unsigned val[3][2]); import "DPI-C" function void i_longint_unsigned_3d(output longint_unsigned_array_t val); import "DPI-C" function void i_longint_unsigned_1d1(output longint unsigned val[1]); import "DPI-C" function void i_longint_unsigned_2d1(output longint unsigned val[1][1]); import "DPI-C" function void i_longint_unsigned_3d1(output longint_unsigned_array1_t val); `ifndef NO_TIME import "DPI-C" function void i_time_0d(output time val); import "DPI-C" function void i_time_1d(output time val[2]); import "DPI-C" function void i_time_2d(output time val[3][2]); import "DPI-C" function void i_time_3d(output time_array_t val); import "DPI-C" function void i_time_1d1(output time val[1]); import "DPI-C" function void i_time_2d1(output time val[1][1]); import "DPI-C" function void i_time_3d1(output time_array1_t val); `endif `ifndef NO_INTEGER import "DPI-C" function void i_integer_0d(output integer val); import "DPI-C" function void i_integer_1d(output integer val[2]); import "DPI-C" function void i_integer_2d(output integer val[3][2]); import "DPI-C" function void i_integer_3d(output integer_array_t val); import "DPI-C" function void i_integer_1d1(output integer val[1]); import "DPI-C" function void i_integer_2d1(output integer val[1][1]); import "DPI-C" function void i_integer_3d1(output integer_array1_t val); `endif import "DPI-C" function void i_real_0d(output real val); import "DPI-C" function void i_real_1d(output real val[2]); import "DPI-C" function void i_real_2d(output real val[3][2]); import "DPI-C" function void i_real_3d(output real_array_t val); import "DPI-C" function void i_real_1d1(output real val[1]); import "DPI-C" function void i_real_2d1(output real val[1][1]); import "DPI-C" function void i_real_3d1(output real_array1_t val); `ifndef NO_SHORTREAL import "DPI-C" function void i_shortreal_0d(output shortreal val); import "DPI-C" function void i_shortreal_1d(output shortreal val[2]); import "DPI-C" function void i_shortreal_2d(output shortreal val[3][2]); import "DPI-C" function void i_shortreal_3d(output shortreal_array_t val); import "DPI-C" function void i_shortreal_1d1(output shortreal val[1]); import "DPI-C" function void i_shortreal_2d1(output shortreal val[1][1]); import "DPI-C" function void i_shortreal_3d1(output shortreal_array1_t val); `endif import "DPI-C" function void i_chandle_0d(output chandle val); import "DPI-C" function void i_chandle_1d(output chandle val[2]); import "DPI-C" function void i_chandle_2d(output chandle val[3][2]); import "DPI-C" function void i_chandle_3d(output chandle_array_t val); import "DPI-C" function void i_chandle_1d1(output chandle val[1]); import "DPI-C" function void i_chandle_2d1(output chandle val[1][1]); import "DPI-C" function void i_chandle_3d1(output chandle_array1_t val); import "DPI-C" function void i_string_0d(output string val); import "DPI-C" function void i_string_1d(output string val[2]); import "DPI-C" function void i_string_2d(output string val[3][2]); import "DPI-C" function void i_string_3d(output string_array_t val); import "DPI-C" function void i_string_1d1(output string val[1]); import "DPI-C" function void i_string_2d1(output string val[1][1]); import "DPI-C" function void i_string_3d1(output string_array1_t val); import "DPI-C" function void i_bit1_0d(output bit val); import "DPI-C" function void i_bit1_1d(output bit val[2]); import "DPI-C" function void i_bit1_2d(output bit val[3][2]); import "DPI-C" function void i_bit1_3d(output bit1_array_t val); import "DPI-C" function void i_bit1_1d1(output bit val[1]); import "DPI-C" function void i_bit1_2d1(output bit val[1][1]); import "DPI-C" function void i_bit1_3d1(output bit1_array1_t val); import "DPI-C" function void i_bit7_0d(output bit[6:0] val); import "DPI-C" function void i_bit7_1d(output bit[6:0] val[2]); import "DPI-C" function void i_bit7_2d(output bit[6:0] val[3][2]); import "DPI-C" function void i_bit7_3d(output bit7_array_t val); import "DPI-C" function void i_bit7_1d1(output bit[6:0] val[1]); import "DPI-C" function void i_bit7_2d1(output bit[6:0] val[1][1]); import "DPI-C" function void i_bit7_3d1(output bit7_array1_t val); import "DPI-C" function void i_bit121_0d(output bit[120:0] val); import "DPI-C" function void i_bit121_1d(output bit[120:0] val[2]); import "DPI-C" function void i_bit121_2d(output bit[120:0] val[3][2]); import "DPI-C" function void i_bit121_3d(output bit121_array_t val); import "DPI-C" function void i_bit121_1d1(output bit[120:0] val[1]); import "DPI-C" function void i_bit121_2d1(output bit[120:0] val[1][1]); import "DPI-C" function void i_bit121_3d1(output bit121_array1_t val); import "DPI-C" function void i_logic1_0d(output logic val); import "DPI-C" function void i_logic1_1d(output logic val[2]); import "DPI-C" function void i_logic1_2d(output logic val[3][2]); import "DPI-C" function void i_logic1_3d(output logic1_array_t val); import "DPI-C" function void i_logic1_1d1(output logic val[1]); import "DPI-C" function void i_logic1_2d1(output logic val[1][1]); import "DPI-C" function void i_logic1_3d1(output logic1_array1_t val); import "DPI-C" function void i_logic7_0d(output logic[6:0] val); import "DPI-C" function void i_logic7_1d(output logic[6:0] val[2]); import "DPI-C" function void i_logic7_2d(output logic[6:0] val[3][2]); import "DPI-C" function void i_logic7_3d(output logic7_array_t val); import "DPI-C" function void i_logic7_1d1(output logic[6:0] val[1]); import "DPI-C" function void i_logic7_2d1(output logic[6:0] val[1][1]); import "DPI-C" function void i_logic7_3d1(output logic7_array1_t val); import "DPI-C" function void i_logic121_0d(output logic[120:0] val); import "DPI-C" function void i_logic121_1d(output logic[120:0] val[2]); import "DPI-C" function void i_logic121_2d(output logic[120:0] val[3][2]); import "DPI-C" function void i_logic121_3d(output logic121_array_t val); import "DPI-C" function void i_logic121_1d1(output logic[120:0] val[1]); import "DPI-C" function void i_logic121_2d1(output logic[120:0] val[1][1]); import "DPI-C" function void i_logic121_3d1(output logic121_array1_t val); import "DPI-C" function void i_pack_struct_0d(output pack_struct_t val); import "DPI-C" function void i_pack_struct_1d(output pack_struct_t val[2]); import "DPI-C" function void i_pack_struct_2d(output pack_struct_t val[3][2]); import "DPI-C" function void i_pack_struct_3d(output pack_struct_array_t val); import "DPI-C" function void i_pack_struct_1d1(output pack_struct_t val[1]); import "DPI-C" function void i_pack_struct_2d1(output pack_struct_t val[1][1]); import "DPI-C" function void i_pack_struct_3d1(output pack_struct_array1_t val); `ifndef NO_UNPACK_STRUCT import "DPI-C" function void i_unpack_struct_0d(output unpack_struct_t val); import "DPI-C" function void i_unpack_struct_1d(output unpack_struct_t val[2]); import "DPI-C" function void i_unpack_struct_2d(output unpack_struct_t val[3][2]); import "DPI-C" function void i_unpack_struct_3d(output unpack_struct_array_t val); import "DPI-C" function void i_unpack_struct_1d1(output unpack_struct_t val[1]); import "DPI-C" function void i_unpack_struct_2d1(output unpack_struct_t val[1][1]); import "DPI-C" function void i_unpack_struct_3d1(output unpack_struct_array1_t val); `endif //====================================================================== // Exports //====================================================================== export "DPI-C" function e_byte_0d; export "DPI-C" function e_byte_1d; export "DPI-C" function e_byte_2d; export "DPI-C" function e_byte_3d; export "DPI-C" function e_byte_1d1; export "DPI-C" function e_byte_2d1; export "DPI-C" function e_byte_3d1; export "DPI-C" function e_byte_unsigned_0d; export "DPI-C" function e_byte_unsigned_1d; export "DPI-C" function e_byte_unsigned_2d; export "DPI-C" function e_byte_unsigned_3d; export "DPI-C" function e_byte_unsigned_1d1; export "DPI-C" function e_byte_unsigned_2d1; export "DPI-C" function e_byte_unsigned_3d1; export "DPI-C" function e_shortint_0d; export "DPI-C" function e_shortint_1d; export "DPI-C" function e_shortint_2d; export "DPI-C" function e_shortint_3d; export "DPI-C" function e_shortint_1d1; export "DPI-C" function e_shortint_2d1; export "DPI-C" function e_shortint_3d1; export "DPI-C" function e_shortint_unsigned_0d; export "DPI-C" function e_shortint_unsigned_1d; export "DPI-C" function e_shortint_unsigned_2d; export "DPI-C" function e_shortint_unsigned_3d; export "DPI-C" function e_shortint_unsigned_1d1; export "DPI-C" function e_shortint_unsigned_2d1; export "DPI-C" function e_shortint_unsigned_3d1; export "DPI-C" function e_int_0d; export "DPI-C" function e_int_1d; export "DPI-C" function e_int_2d; export "DPI-C" function e_int_3d; export "DPI-C" function e_int_1d1; export "DPI-C" function e_int_2d1; export "DPI-C" function e_int_3d1; export "DPI-C" function e_int_unsigned_0d; export "DPI-C" function e_int_unsigned_1d; export "DPI-C" function e_int_unsigned_2d; export "DPI-C" function e_int_unsigned_3d; export "DPI-C" function e_int_unsigned_1d1; export "DPI-C" function e_int_unsigned_2d1; export "DPI-C" function e_int_unsigned_3d1; export "DPI-C" function e_longint_0d; export "DPI-C" function e_longint_1d; export "DPI-C" function e_longint_2d; export "DPI-C" function e_longint_3d; export "DPI-C" function e_longint_1d1; export "DPI-C" function e_longint_2d1; export "DPI-C" function e_longint_3d1; export "DPI-C" function e_longint_unsigned_0d; export "DPI-C" function e_longint_unsigned_1d; export "DPI-C" function e_longint_unsigned_2d; export "DPI-C" function e_longint_unsigned_3d; export "DPI-C" function e_longint_unsigned_1d1; export "DPI-C" function e_longint_unsigned_2d1; export "DPI-C" function e_longint_unsigned_3d1; `ifndef NO_TIME export "DPI-C" function e_time_0d; export "DPI-C" function e_time_1d; export "DPI-C" function e_time_2d; export "DPI-C" function e_time_3d; export "DPI-C" function e_time_1d1; export "DPI-C" function e_time_2d1; export "DPI-C" function e_time_3d1; `endif `ifndef NO_INTEGER export "DPI-C" function e_integer_0d; export "DPI-C" function e_integer_1d; export "DPI-C" function e_integer_2d; export "DPI-C" function e_integer_3d; export "DPI-C" function e_integer_1d1; export "DPI-C" function e_integer_2d1; export "DPI-C" function e_integer_3d1; `endif export "DPI-C" function e_real_0d; export "DPI-C" function e_real_1d; export "DPI-C" function e_real_2d; export "DPI-C" function e_real_3d; export "DPI-C" function e_real_1d1; export "DPI-C" function e_real_2d1; export "DPI-C" function e_real_3d1; `ifndef NO_SHORTREAL export "DPI-C" function e_shortreal_0d; export "DPI-C" function e_shortreal_1d; export "DPI-C" function e_shortreal_2d; export "DPI-C" function e_shortreal_3d; export "DPI-C" function e_shortreal_1d1; export "DPI-C" function e_shortreal_2d1; export "DPI-C" function e_shortreal_3d1; `endif export "DPI-C" function e_chandle_0d; export "DPI-C" function e_chandle_1d; export "DPI-C" function e_chandle_2d; export "DPI-C" function e_chandle_3d; export "DPI-C" function e_chandle_1d1; export "DPI-C" function e_chandle_2d1; export "DPI-C" function e_chandle_3d1; export "DPI-C" function e_string_0d; export "DPI-C" function e_string_1d; export "DPI-C" function e_string_2d; export "DPI-C" function e_string_3d; export "DPI-C" function e_string_1d1; export "DPI-C" function e_string_2d1; export "DPI-C" function e_string_3d1; export "DPI-C" function e_bit1_0d; export "DPI-C" function e_bit1_1d; export "DPI-C" function e_bit1_2d; export "DPI-C" function e_bit1_3d; export "DPI-C" function e_bit1_1d1; export "DPI-C" function e_bit1_2d1; export "DPI-C" function e_bit1_3d1; export "DPI-C" function e_bit7_0d; export "DPI-C" function e_bit7_1d; export "DPI-C" function e_bit7_2d; export "DPI-C" function e_bit7_3d; export "DPI-C" function e_bit7_1d1; export "DPI-C" function e_bit7_2d1; export "DPI-C" function e_bit7_3d1; export "DPI-C" function e_bit121_0d; export "DPI-C" function e_bit121_1d; export "DPI-C" function e_bit121_2d; export "DPI-C" function e_bit121_3d; export "DPI-C" function e_bit121_1d1; export "DPI-C" function e_bit121_2d1; export "DPI-C" function e_bit121_3d1; export "DPI-C" function e_logic1_0d; export "DPI-C" function e_logic1_1d; export "DPI-C" function e_logic1_2d; export "DPI-C" function e_logic1_3d; export "DPI-C" function e_logic1_1d1; export "DPI-C" function e_logic1_2d1; export "DPI-C" function e_logic1_3d1; export "DPI-C" function e_logic7_0d; export "DPI-C" function e_logic7_1d; export "DPI-C" function e_logic7_2d; export "DPI-C" function e_logic7_3d; export "DPI-C" function e_logic7_1d1; export "DPI-C" function e_logic7_2d1; export "DPI-C" function e_logic7_3d1; export "DPI-C" function e_logic121_0d; export "DPI-C" function e_logic121_1d; export "DPI-C" function e_logic121_2d; export "DPI-C" function e_logic121_3d; export "DPI-C" function e_logic121_1d1; export "DPI-C" function e_logic121_2d1; export "DPI-C" function e_logic121_3d1; export "DPI-C" function e_pack_struct_0d; export "DPI-C" function e_pack_struct_1d; export "DPI-C" function e_pack_struct_2d; export "DPI-C" function e_pack_struct_3d; export "DPI-C" function e_pack_struct_1d1; export "DPI-C" function e_pack_struct_2d1; export "DPI-C" function e_pack_struct_3d1; `ifndef NO_UNPACK_STRUCT export "DPI-C" function e_unpack_struct_0d; export "DPI-C" function e_unpack_struct_1d; export "DPI-C" function e_unpack_struct_2d; export "DPI-C" function e_unpack_struct_3d; export "DPI-C" function e_unpack_struct_1d1; export "DPI-C" function e_unpack_struct_2d1; export "DPI-C" function e_unpack_struct_3d1; `endif //====================================================================== // Definitions of exported functions //====================================================================== `define SET_0D(val) \ /* verilator lint_off WIDTH */ \ val = 42 \ /* verilator lint_on WIDTH */ `define SET_1D(val) \ /* verilator lint_off WIDTH */ \ val[0] = 43; val[1] = 44 \ /* verilator lint_on WIDTH */ `define SET_2D(val) \ /* verilator lint_off WIDTH */ \ val[0][1] = 45; val[1][1] = 46; val[2][1] = 47 \ /* verilator lint_on WIDTH */ `define SET_3D(val) \ /* verilator lint_off WIDTH */ \ val[0][0][0] = 48; val[1][0][0] = 49; val[2][0][0] = 50; val[3][0][0] = 51 \ /* verilator lint_on WIDTH */ `define SET_1D1(val) \ /* verilator lint_off WIDTH */ \ val[0] = 52; \ /* verilator lint_on WIDTH */ `define SET_2D1(val) \ /* verilator lint_off WIDTH */ \ val[0][0] = 53; \ /* verilator lint_on WIDTH */ `define SET_3D1(val) \ /* verilator lint_off WIDTH */ \ val[0][0][0] = 54; \ /* verilator lint_on WIDTH */ function void e_byte_0d(output byte val); `SET_0D(val); endfunction function void e_byte_1d(output byte val[2]); `SET_1D(val); endfunction function void e_byte_2d(output byte val[3][2]); `SET_2D(val); endfunction function void e_byte_3d(output byte_array_t val); `SET_3D(val); endfunction function void e_byte_1d1(output byte val[1]); `SET_1D1(val); endfunction function void e_byte_2d1(output byte val[1][1]); `SET_2D1(val); endfunction function void e_byte_3d1(output byte_array1_t val); `SET_3D1(val); endfunction function void e_byte_unsigned_0d(output byte unsigned val); `SET_0D(val); endfunction function void e_byte_unsigned_1d(output byte unsigned val[2]); `SET_1D(val); endfunction function void e_byte_unsigned_2d(output byte unsigned val[3][2]); `SET_2D(val); endfunction function void e_byte_unsigned_3d(output byte_unsigned_array_t val); `SET_3D(val); endfunction function void e_byte_unsigned_1d1(output byte unsigned val[1]); `SET_1D1(val); endfunction function void e_byte_unsigned_2d1(output byte unsigned val[1][1]); `SET_2D1(val); endfunction function void e_byte_unsigned_3d1(output byte_unsigned_array1_t val); `SET_3D1(val); endfunction function void e_shortint_0d(output shortint val); `SET_0D(val); endfunction function void e_shortint_1d(output shortint val[2]); `SET_1D(val); endfunction function void e_shortint_2d(output shortint val[3][2]); `SET_2D(val); endfunction function void e_shortint_3d(output shortint_array_t val); `SET_3D(val); endfunction function void e_shortint_1d1(output shortint val[1]); `SET_1D1(val); endfunction function void e_shortint_2d1(output shortint val[1][1]); `SET_2D1(val); endfunction function void e_shortint_3d1(output shortint_array1_t val); `SET_3D1(val); endfunction function void e_shortint_unsigned_0d(output shortint unsigned val); `SET_0D(val); endfunction function void e_shortint_unsigned_1d(output shortint unsigned val[2]); `SET_1D(val); endfunction function void e_shortint_unsigned_2d(output shortint unsigned val[3][2]); `SET_2D(val); endfunction function void e_shortint_unsigned_3d(output shortint_unsigned_array_t val); `SET_3D(val); endfunction function void e_shortint_unsigned_1d1(output shortint unsigned val[1]); `SET_1D1(val); endfunction function void e_shortint_unsigned_2d1(output shortint unsigned val[1][1]); `SET_2D1(val); endfunction function void e_shortint_unsigned_3d1(output shortint_unsigned_array1_t val); `SET_3D1(val); endfunction function void e_int_0d(output int val); `SET_0D(val); endfunction function void e_int_1d(output int val[2]); `SET_1D(val); endfunction function void e_int_2d(output int val[3][2]); `SET_2D(val); endfunction function void e_int_3d(output int_array_t val); `SET_3D(val); endfunction function void e_int_1d1(output int val[1]); `SET_1D1(val); endfunction function void e_int_2d1(output int val[1][1]); `SET_2D1(val); endfunction function void e_int_3d1(output int_array1_t val); `SET_3D1(val); endfunction function void e_int_unsigned_0d(output int unsigned val); `SET_0D(val); endfunction function void e_int_unsigned_1d(output int unsigned val[2]); `SET_1D(val); endfunction function void e_int_unsigned_2d(output int unsigned val[3][2]); `SET_2D(val); endfunction function void e_int_unsigned_3d(output int_unsigned_array_t val); `SET_3D(val); endfunction function void e_int_unsigned_1d1(output int unsigned val[1]); `SET_1D1(val); endfunction function void e_int_unsigned_2d1(output int unsigned val[1][1]); `SET_2D1(val); endfunction function void e_int_unsigned_3d1(output int_unsigned_array1_t val); `SET_3D1(val); endfunction function void e_longint_0d(output longint val); `SET_0D(val); endfunction function void e_longint_1d(output longint val[2]); `SET_1D(val); endfunction function void e_longint_2d(output longint val[3][2]); `SET_2D(val); endfunction function void e_longint_3d(output longint_array_t val); `SET_3D(val); endfunction function void e_longint_1d1(output longint val[1]); `SET_1D1(val); endfunction function void e_longint_2d1(output longint val[1][1]); `SET_2D1(val); endfunction function void e_longint_3d1(output longint_array1_t val); `SET_3D1(val); endfunction function void e_longint_unsigned_0d(output longint unsigned val); `SET_0D(val); endfunction function void e_longint_unsigned_1d(output longint unsigned val[2]); `SET_1D(val); endfunction function void e_longint_unsigned_2d(output longint unsigned val[3][2]); `SET_2D(val); endfunction function void e_longint_unsigned_3d(output longint_unsigned_array_t val); `SET_3D(val); endfunction function void e_longint_unsigned_1d1(output longint unsigned val[1]); `SET_1D1(val); endfunction function void e_longint_unsigned_2d1(output longint unsigned val[1][1]); `SET_2D1(val); endfunction function void e_longint_unsigned_3d1(output longint_unsigned_array1_t val); `SET_3D1(val); endfunction `ifndef NO_TIME function void e_time_0d(output time val); `SET_0D(val); endfunction function void e_time_1d(output time val[2]); `SET_1D(val); endfunction function void e_time_2d(output time val[3][2]); `SET_2D(val); endfunction function void e_time_3d(output time_array_t val); `SET_3D(val); endfunction function void e_time_1d1(output time val[1]); `SET_1D1(val); endfunction function void e_time_2d1(output time val[1][1]); `SET_2D1(val); endfunction function void e_time_3d1(output time_array1_t val); `SET_3D1(val); endfunction `endif `ifndef NO_INTEGER function void e_integer_0d(output integer val); `SET_0D(val); endfunction function void e_integer_1d(output integer val[2]); `SET_1D(val); endfunction function void e_integer_2d(output integer val[3][2]); `SET_2D(val); endfunction function void e_integer_3d(output integer_array_t val); `SET_3D(val); endfunction function void e_integer_1d1(output integer val[1]); `SET_1D1(val); endfunction function void e_integer_2d1(output integer val[1][1]); `SET_2D1(val); endfunction function void e_integer_3d1(output integer_array1_t val); `SET_3D1(val); endfunction `endif function void e_real_0d(output real val); `SET_0D(val); endfunction function void e_real_1d(output real val[2]); `SET_1D(val); endfunction function void e_real_2d(output real val[3][2]); `SET_2D(val); endfunction function void e_real_3d(output real_array_t val); `SET_3D(val); endfunction function void e_real_1d1(output real val[1]); `SET_1D1(val); endfunction function void e_real_2d1(output real val[1][1]); `SET_2D1(val); endfunction function void e_real_3d1(output real_array1_t val); `SET_3D1(val); endfunction `ifndef NO_SHORTREAL function void e_shortreal_0d(output shortreal val); `SET_0D(val); endfunction function void e_shortreal_1d(output shortreal val[2]); `SET_1D(val); endfunction function void e_shortreal_2d(output shortreal val[3][2]); `SET_2D(val); endfunction function void e_shortreal_3d(output shortreal_array_t val); `SET_3D(val); endfunction function void e_shortreal_1d1(output shortreal val[1]); `SET_1D1(val); endfunction function void e_shortreal_2d1(output shortreal val[1][1]); `SET_2D1(val); endfunction function void e_shortreal_3d1(output shortreal_array1_t val); `SET_3D1(val); endfunction `endif function void e_chandle_0d(output chandle val); val = get_non_null(); endfunction function void e_chandle_1d(output chandle val[2]); val[0] = get_non_null(); val[1] = get_non_null(); endfunction function void e_chandle_2d(output chandle val[3][2]); val[0][1] = get_non_null(); val[1][1] = get_non_null(); val[2][1] = get_non_null(); endfunction function void e_chandle_3d(output chandle_array_t val); val[0][0][0] = get_non_null(); val[1][0][0] = get_non_null(); val[2][0][0] = get_non_null(); val[3][0][0] = get_non_null(); endfunction function void e_chandle_1d1(output chandle val[1]); val[0] = get_non_null(); endfunction function void e_chandle_2d1(output chandle val[1][1]); val[0][0] = get_non_null(); endfunction function void e_chandle_3d1(output chandle_array1_t val); val[0][0][0] = get_non_null(); endfunction function void e_string_0d(output string val); val = "42"; endfunction function void e_string_1d(output string val[2]); val[0] = "43"; val[1] = "44"; endfunction function void e_string_2d(output string val[3][2]); val[0][1] = "45"; val[1][1] = "46"; val[2][1] = "47"; endfunction function void e_string_3d(output string_array_t val); val[0][0][0] = "48"; val[1][0][0] = "49"; val[2][0][0] = "50"; val[3][0][0] = "51"; endfunction function void e_string_1d1(output string val[1]); val[0] = "52"; endfunction function void e_string_2d1(output string val[1][1]); val[0][0] = "53"; endfunction function void e_string_3d1(output string_array1_t val); val[0][0][0] = "54"; endfunction function void e_bit1_0d(output bit val); `SET_0D(val); endfunction function void e_bit1_1d(output bit val[2]); `SET_1D(val); endfunction function void e_bit1_2d(output bit val[3][2]); `SET_2D(val); endfunction function void e_bit1_3d(output bit1_array_t val); `SET_3D(val); endfunction function void e_bit1_1d1(output bit val[1]); `SET_1D1(val); endfunction function void e_bit1_2d1(output bit val[1][1]); `SET_2D1(val); endfunction function void e_bit1_3d1(output bit1_array1_t val); `SET_3D1(val); endfunction function void e_bit7_0d(output bit[6:0] val); `SET_0D(val); endfunction function void e_bit7_1d(output bit[6:0] val[2]); `SET_1D(val); endfunction function void e_bit7_2d(output bit[6:0] val[3][2]); `SET_2D(val); endfunction function void e_bit7_3d(output bit7_array_t val); `SET_3D(val); endfunction function void e_bit7_1d1(output bit[6:0] val[1]); `SET_1D1(val); endfunction function void e_bit7_2d1(output bit[6:0] val[1][1]); `SET_2D1(val); endfunction function void e_bit7_3d1(output bit7_array1_t val); `SET_3D1(val); endfunction function void e_bit121_0d(output bit[120:0] val); `SET_0D(val); endfunction function void e_bit121_1d(output bit[120:0] val[2]); `SET_1D(val); endfunction function void e_bit121_2d(output bit[120:0] val[3][2]); `SET_2D(val); endfunction function void e_bit121_3d(output bit121_array_t val); `SET_3D(val); endfunction function void e_bit121_1d1(output bit[120:0] val[1]); `SET_1D1(val); endfunction function void e_bit121_2d1(output bit[120:0] val[1][1]); `SET_2D1(val); endfunction function void e_bit121_3d1(output bit121_array1_t val); `SET_3D1(val); endfunction function void e_logic1_0d(output logic val); `SET_0D(val); endfunction function void e_logic1_1d(output logic val[2]); `SET_1D(val); endfunction function void e_logic1_2d(output logic val[3][2]); `SET_2D(val); endfunction function void e_logic1_3d(output logic1_array_t val); `SET_3D(val); endfunction function void e_logic1_1d1(output logic val[1]); `SET_1D1(val); endfunction function void e_logic1_2d1(output logic val[1][1]); `SET_2D1(val); endfunction function void e_logic1_3d1(output logic1_array1_t val); `SET_3D1(val); endfunction function void e_logic7_0d(output logic[6:0] val); `SET_0D(val); endfunction function void e_logic7_1d(output logic[6:0] val[2]); `SET_1D(val); endfunction function void e_logic7_2d(output logic[6:0] val[3][2]); `SET_2D(val); endfunction function void e_logic7_3d(output logic7_array_t val); `SET_3D(val); endfunction function void e_logic7_1d1(output logic[6:0] val[1]); `SET_1D1(val); endfunction function void e_logic7_2d1(output logic[6:0] val[1][1]); `SET_2D1(val); endfunction function void e_logic7_3d1(output logic7_array1_t val); `SET_3D1(val); endfunction function void e_logic121_0d(output logic[120:0] val); `SET_0D(val); endfunction function void e_logic121_1d(output logic[120:0] val[2]); `SET_1D(val); endfunction function void e_logic121_2d(output logic[120:0] val[3][2]); `SET_2D(val); endfunction function void e_logic121_3d(output logic121_array_t val); `SET_3D(val); endfunction function void e_logic121_1d1(output logic[120:0] val[1]); `SET_1D1(val); endfunction function void e_logic121_2d1(output logic[120:0] val[1][1]); `SET_2D1(val); endfunction function void e_logic121_3d1(output logic121_array1_t val); `SET_3D1(val); endfunction function void e_pack_struct_0d(output pack_struct_t val); `SET_0D(val); endfunction function void e_pack_struct_1d(output pack_struct_t val[2]); `SET_1D(val); endfunction function void e_pack_struct_2d(output pack_struct_t val[3][2]); `SET_2D(val); endfunction function void e_pack_struct_3d(output pack_struct_array_t val); `SET_3D(val); endfunction function void e_pack_struct_1d1(output pack_struct_t val[1]); `SET_1D1(val); endfunction function void e_pack_struct_2d1(output pack_struct_t val[1][1]); `SET_2D1(val); endfunction function void e_pack_struct_3d1(output pack_struct_array1_t val); `SET_3D1(val); endfunction `ifndef NO_UNPACK_STRUCT function void e_unpack_struct_0d(output unpack_struct_t val); val.val = 42; endfunction function void e_unpack_struct_1d(output unpack_struct_t val[2]); val[0].val = 43; val[1].val = 44; endfunction function void e_unpack_struct_2d(output unpack_struct_t val[3][2]); val[0][1].val = 45; val[1][1].val = 46; val[2][1].val = 47; endfunction function void e_unpack_struct_3d(output unpack_struct_array_t val); val[0][0][0].val = 48; val[1][0][0].val = 49; val[2][0][0].val = 50; val[3][0][0].val = 51; endfunction function void e_unpack_struct_1d1(output unpack_struct_t val[1]); val[0].val = 52; endfunction function void e_unpack_struct_2d1(output unpack_struct_t val[1][1]); val[0][0].val = 53; endfunction function void e_unpack_struct_3d1(output unpack_struct_array1_t val); val[0][0][0].val = 54; endfunction `endif //====================================================================== // Invoke all imported functions //====================================================================== import "DPI-C" context function void check_exports(); initial begin byte_array_t byte_array; byte_array1_t byte_array1; byte_unsigned_array_t byte_unsigned_array; byte_unsigned_array1_t byte_unsigned_array1; shortint_array_t shortint_array; shortint_array1_t shortint_array1; shortint_unsigned_array_t shortint_unsigned_array; shortint_unsigned_array1_t shortint_unsigned_array1; int_array_t int_array; int_array1_t int_array1; int_unsigned_array_t int_unsigned_array; int_unsigned_array1_t int_unsigned_array1; longint_array_t longint_array; longint_array1_t longint_array1; longint_unsigned_array_t longint_unsigned_array; longint_unsigned_array1_t longint_unsigned_array1; `ifndef NO_TIME time_array_t time_array; time_array1_t time_array1; `endif `ifndef NO_INTEGER integer_array_t integer_array; integer_array1_t integer_array1; `endif real_array_t real_array; real_array1_t real_array1; `ifndef NO_SHORTREAL shortreal_array_t shortreal_array; shortreal_array1_t shortreal_array1; `endif chandle_array_t chandle_array; chandle_array1_t chandle_array1; string_array_t string_array; string_array1_t string_array1; bit1_array_t bit1_array; bit1_array1_t bit1_array1; bit7_array_t bit7_array; bit7_array1_t bit7_array1; bit121_array_t bit121_array; bit121_array1_t bit121_array1; logic1_array_t logic1_array; logic1_array1_t logic1_array1; logic7_array_t logic7_array; logic7_array1_t logic7_array1; logic121_array_t logic121_array; logic121_array1_t logic121_array1; pack_struct_array_t pack_struct_array; pack_struct_array1_t pack_struct_array1; `ifndef NO_UNPACK_STRUCT unpack_struct_array_t unpack_struct_array; unpack_struct_array1_t unpack_struct_array1; `endif i_byte_0d(byte_array[3][2][1]); `CHECK_0D(byte_array[3][2][1]); i_byte_1d(byte_array[2][1]); `CHECK_1D(byte_array[2][1]); i_byte_2d(byte_array[1]); `CHECK_2D(byte_array[1]); i_byte_3d(byte_array); `CHECK_3D(byte_array); i_byte_1d1(byte_array1[0][0]); `CHECK_1D1(byte_array1[0][0]); i_byte_2d1(byte_array1[0]); `CHECK_2D1(byte_array1[0]); i_byte_3d1(byte_array1); `CHECK_3D1(byte_array1); i_byte_unsigned_0d(byte_unsigned_array[3][2][1]); `CHECK_0D(byte_unsigned_array[3][2][1]); i_byte_unsigned_1d(byte_unsigned_array[2][1]); `CHECK_1D(byte_unsigned_array[2][1]); i_byte_unsigned_2d(byte_unsigned_array[1]); `CHECK_2D(byte_unsigned_array[1]); i_byte_unsigned_3d(byte_unsigned_array); `CHECK_3D(byte_unsigned_array); i_byte_unsigned_1d1(byte_unsigned_array1[0][0]); `CHECK_1D1(byte_unsigned_array1[0][0]); i_byte_unsigned_2d1(byte_unsigned_array1[0]); `CHECK_2D1(byte_unsigned_array1[0]); i_byte_unsigned_3d1(byte_unsigned_array1); `CHECK_3D1(byte_unsigned_array1); i_shortint_0d(shortint_array[3][2][1]); `CHECK_0D(shortint_array[3][2][1]); i_shortint_1d(shortint_array[2][1]); `CHECK_1D(shortint_array[2][1]); i_shortint_2d(shortint_array[1]); `CHECK_2D(shortint_array[1]); i_shortint_3d(shortint_array); `CHECK_3D(shortint_array); i_shortint_1d1(shortint_array1[0][0]); `CHECK_1D1(shortint_array1[0][0]); i_shortint_2d1(shortint_array1[0]); `CHECK_2D1(shortint_array1[0]); i_shortint_3d1(shortint_array1); `CHECK_3D1(shortint_array1); i_shortint_unsigned_0d(shortint_unsigned_array[3][2][1]); `CHECK_0D(shortint_unsigned_array[3][2][1]); i_shortint_unsigned_1d(shortint_unsigned_array[2][1]); `CHECK_1D(shortint_unsigned_array[2][1]); i_shortint_unsigned_2d(shortint_unsigned_array[1]); `CHECK_2D(shortint_unsigned_array[1]); i_shortint_unsigned_3d(shortint_unsigned_array); `CHECK_3D(shortint_unsigned_array); i_shortint_unsigned_1d1(shortint_unsigned_array1[0][0]); `CHECK_1D1(shortint_unsigned_array1[0][0]); i_shortint_unsigned_2d1(shortint_unsigned_array1[0]); `CHECK_2D1(shortint_unsigned_array1[0]); i_shortint_unsigned_3d1(shortint_unsigned_array1); `CHECK_3D1(shortint_unsigned_array1); i_int_0d(int_array[3][2][1]); `CHECK_0D(int_array[3][2][1]); i_int_1d(int_array[2][1]); `CHECK_1D(int_array[2][1]); i_int_2d(int_array[1]); `CHECK_2D(int_array[1]); i_int_3d(int_array); `CHECK_3D(int_array); i_int_1d1(int_array1[0][0]); `CHECK_1D1(int_array1[0][0]); i_int_2d1(int_array1[0]); `CHECK_2D1(int_array1[0]); i_int_3d1(int_array1); `CHECK_3D1(int_array1); i_int_unsigned_0d(int_unsigned_array[3][2][1]); `CHECK_0D(int_unsigned_array[3][2][1]); i_int_unsigned_1d(int_unsigned_array[2][1]); `CHECK_1D(int_unsigned_array[2][1]); i_int_unsigned_2d(int_unsigned_array[1]); `CHECK_2D(int_unsigned_array[1]); i_int_unsigned_3d(int_unsigned_array); `CHECK_3D(int_unsigned_array); i_int_unsigned_1d1(int_unsigned_array1[0][0]); `CHECK_1D1(int_unsigned_array1[0][0]); i_int_unsigned_2d1(int_unsigned_array1[0]); `CHECK_2D1(int_unsigned_array1[0]); i_int_unsigned_3d1(int_unsigned_array1); `CHECK_3D1(int_unsigned_array1); i_longint_0d(longint_array[3][2][1]); `CHECK_0D(longint_array[3][2][1]); i_longint_1d(longint_array[2][1]); `CHECK_1D(longint_array[2][1]); i_longint_2d(longint_array[1]); `CHECK_2D(longint_array[1]); i_longint_3d(longint_array); `CHECK_3D(longint_array); i_longint_1d1(longint_array1[0][0]); `CHECK_1D1(longint_array1[0][0]); i_longint_2d1(longint_array1[0]); `CHECK_2D1(longint_array1[0]); i_longint_3d1(longint_array1); `CHECK_3D1(longint_array1); i_longint_unsigned_0d(longint_unsigned_array[3][2][1]); `CHECK_0D(longint_unsigned_array[3][2][1]); i_longint_unsigned_1d(longint_unsigned_array[2][1]); `CHECK_1D(longint_unsigned_array[2][1]); i_longint_unsigned_2d(longint_unsigned_array[1]); `CHECK_2D(longint_unsigned_array[1]); i_longint_unsigned_3d(longint_unsigned_array); `CHECK_3D(longint_unsigned_array); i_longint_unsigned_1d1(longint_unsigned_array1[0][0]); `CHECK_1D1(longint_unsigned_array1[0][0]); i_longint_unsigned_2d1(longint_unsigned_array1[0]); `CHECK_2D1(longint_unsigned_array1[0]); i_longint_unsigned_3d1(longint_unsigned_array1); `CHECK_3D1(longint_unsigned_array1); `ifndef NO_TIME i_time_0d(time_array[3][2][1]); `CHECK_0D(time_array[3][2][1]); i_time_1d(time_array[2][1]); `CHECK_1D(time_array[2][1]); i_time_2d(time_array[1]); `CHECK_2D(time_array[1]); i_time_3d(time_array); `CHECK_3D(time_array); i_time_1d1(time_array1[0][0]); `CHECK_1D1(time_array1[0][0]); i_time_2d1(time_array1[0]); `CHECK_2D1(time_array1[0]); i_time_3d1(time_array1); `CHECK_3D1(time_array1); `endif `ifndef NO_INTEGER i_integer_0d(integer_array[3][2][1]); `CHECK_0D(integer_array[3][2][1]); i_integer_1d(integer_array[2][1]); `CHECK_1D(integer_array[2][1]); i_integer_2d(integer_array[1]); `CHECK_2D(integer_array[1]); i_integer_3d(integer_array); `CHECK_3D(integer_array); i_integer_1d1(integer_array1[0][0]); `CHECK_1D1(integer_array1[0][0]); i_integer_2d1(integer_array1[0]); `CHECK_2D1(integer_array1[0]); i_integer_3d1(integer_array1); `CHECK_3D1(integer_array1); `endif i_real_0d(real_array[3][2][1]); `CHECK_0D(real_array[3][2][1]); i_real_1d(real_array[2][1]); `CHECK_1D(real_array[2][1]); i_real_2d(real_array[1]); `CHECK_2D(real_array[1]); i_real_3d(real_array); `CHECK_3D(real_array); i_real_1d1(real_array1[0][0]); `CHECK_1D1(real_array1[0][0]); i_real_2d1(real_array1[0]); `CHECK_2D1(real_array1[0]); i_real_3d1(real_array1); `CHECK_3D1(real_array1); `ifndef NO_SHORTREAL i_shortreal_0d(shortreal_array[3][2][1]); `CHECK_0D(shortreal_array[3][2][1]); i_shortreal_1d(shortreal_array[2][1]); `CHECK_1D(shortreal_array[2][1]); i_shortreal_2d(shortreal_array[1]); `CHECK_2D(shortreal_array[1]); i_shortreal_3d(shortreal_array); `CHECK_3D(shortreal_array); i_shortreal_1d1(shortreal_array1[0][0]); `CHECK_1D1(shortreal_array1[0][0]); i_shortreal_2d1(shortreal_array1[0]); `CHECK_2D1(shortreal_array1[0]); i_shortreal_3d1(shortreal_array1); `CHECK_3D1(shortreal_array1); `endif for (int i = 0; i < 4; ++i) for (int j = 0; j < 3; ++j) for (int k = 0; k < 2; ++k) chandle_array[i][j][k] = null; i_chandle_0d(chandle_array[3][2][1]); `CHECK_CHANDLE_VAL(chandle_array[3][2][1], get_non_null()); i_chandle_1d(chandle_array[2][1]); `CHECK_CHANDLE_VAL(chandle_array[2][1][0], get_non_null()); `CHECK_CHANDLE_VAL(chandle_array[2][1][1], get_non_null()); i_chandle_2d(chandle_array[1]); `CHECK_CHANDLE_VAL(chandle_array[1][0][1], get_non_null()); `CHECK_CHANDLE_VAL(chandle_array[1][1][1], get_non_null()); `CHECK_CHANDLE_VAL(chandle_array[1][2][1], get_non_null()); i_chandle_3d(chandle_array); `CHECK_CHANDLE_VAL(chandle_array[0][0][0], get_non_null()); `CHECK_CHANDLE_VAL(chandle_array[1][0][0], get_non_null()); `CHECK_CHANDLE_VAL(chandle_array[2][0][0], get_non_null()); `CHECK_CHANDLE_VAL(chandle_array[3][0][0], get_non_null()); i_chandle_1d1(chandle_array1[0][0]); `CHECK_CHANDLE_VAL(chandle_array1[0][0][0], get_non_null()); i_chandle_2d1(chandle_array1[0]); `CHECK_CHANDLE_VAL(chandle_array1[0][0][0], get_non_null()); i_chandle_3d1(chandle_array1); `CHECK_CHANDLE_VAL(chandle_array1[0][0][0], get_non_null()); i_string_0d(string_array[3][2][1]); `CHECK_STRING_VAL(string_array[3][2][1], "42"); i_string_1d(string_array[2][1]); `CHECK_STRING_VAL(string_array[2][1][0], "43"); `CHECK_STRING_VAL(string_array[2][1][1], "44"); i_string_2d(string_array[1]); `CHECK_STRING_VAL(string_array[1][0][1], "45"); `CHECK_STRING_VAL(string_array[1][1][1], "46"); `CHECK_STRING_VAL(string_array[1][2][1], "47"); i_string_3d(string_array); `CHECK_STRING_VAL(string_array[0][0][0], "48"); `CHECK_STRING_VAL(string_array[1][0][0], "49"); `CHECK_STRING_VAL(string_array[2][0][0], "50"); `CHECK_STRING_VAL(string_array[3][0][0], "51"); i_string_1d1(string_array1[0][0]); `CHECK_STRING_VAL(string_array1[0][0][0], "52"); i_string_2d1(string_array1[0]); `CHECK_STRING_VAL(string_array1[0][0][0], "53"); i_string_3d1(string_array1); `CHECK_STRING_VAL(string_array1[0][0][0], "54"); i_bit1_0d(bit1_array[3][2][1]); `CHECK_0D(bit1_array[3][2][1]); i_bit1_1d(bit1_array[2][1]); `CHECK_1D(bit1_array[2][1]); i_bit1_2d(bit1_array[1]); `CHECK_2D(bit1_array[1]); i_bit1_3d(bit1_array); `CHECK_3D(bit1_array); i_bit1_1d1(bit1_array1[0][0]); `CHECK_1D1(bit1_array1[0][0]); i_bit1_2d1(bit1_array1[0]); `CHECK_2D1(bit1_array1[0]); i_bit1_3d1(bit1_array1); `CHECK_3D1(bit1_array1); i_bit7_0d(bit7_array[3][2][1]); `CHECK_0D(bit7_array[3][2][1]); i_bit7_1d(bit7_array[2][1]); `CHECK_1D(bit7_array[2][1]); i_bit7_2d(bit7_array[1]); `CHECK_2D(bit7_array[1]); i_bit7_3d(bit7_array); `CHECK_3D(bit7_array); i_bit7_1d1(bit7_array1[0][0]); `CHECK_1D1(bit7_array1[0][0]); i_bit7_2d1(bit7_array1[0]); `CHECK_2D1(bit7_array1[0]); i_bit7_3d1(bit7_array1); `CHECK_3D1(bit7_array1); i_bit121_0d(bit121_array[3][2][1]); `CHECK_0D(bit121_array[3][2][1]); i_bit121_1d(bit121_array[2][1]); `CHECK_1D(bit121_array[2][1]); i_bit121_2d(bit121_array[1]); `CHECK_2D(bit121_array[1]); i_bit121_3d(bit121_array); `CHECK_3D(bit121_array); i_bit121_1d1(bit121_array1[0][0]); `CHECK_1D1(bit121_array1[0][0]); i_bit121_2d1(bit121_array1[0]); `CHECK_2D1(bit121_array1[0]); i_bit121_3d1(bit121_array1); `CHECK_3D1(bit121_array1); i_logic1_0d(logic1_array[3][2][1]); `CHECK_0D(logic1_array[3][2][1]); i_logic1_1d(logic1_array[2][1]); `CHECK_1D(logic1_array[2][1]); i_logic1_2d(logic1_array[1]); `CHECK_2D(logic1_array[1]); i_logic1_3d(logic1_array); `CHECK_3D(logic1_array); i_logic1_1d1(logic1_array1[0][0]); `CHECK_1D1(logic1_array1[0][0]); i_logic1_2d1(logic1_array1[0]); `CHECK_2D1(logic1_array1[0]); i_logic1_3d1(logic1_array1); `CHECK_3D1(logic1_array1); i_logic7_0d(logic7_array[3][2][1]); `CHECK_0D(logic7_array[3][2][1]); i_logic7_1d(logic7_array[2][1]); `CHECK_1D(logic7_array[2][1]); i_logic7_2d(logic7_array[1]); `CHECK_2D(logic7_array[1]); i_logic7_3d(logic7_array); `CHECK_3D(logic7_array); i_logic7_1d1(logic7_array1[0][0]); `CHECK_1D1(logic7_array1[0][0]); i_logic7_2d1(logic7_array1[0]); `CHECK_2D1(logic7_array1[0]); i_logic7_3d1(logic7_array1); `CHECK_3D1(logic7_array1); i_logic121_0d(logic121_array[3][2][1]); `CHECK_0D(logic121_array[3][2][1]); i_logic121_1d(logic121_array[2][1]); `CHECK_1D(logic121_array[2][1]); i_logic121_2d(logic121_array[1]); `CHECK_2D(logic121_array[1]); i_logic121_3d(logic121_array); `CHECK_3D(logic121_array); i_logic121_1d1(logic121_array1[0][0]); `CHECK_1D1(logic121_array1[0][0]); i_logic121_2d1(logic121_array1[0]); `CHECK_2D1(logic121_array1[0]); i_logic121_3d1(logic121_array1); `CHECK_3D1(logic121_array1); i_pack_struct_0d(pack_struct_array[3][2][1]); `CHECK_0D(pack_struct_array[3][2][1]); i_pack_struct_1d(pack_struct_array[2][1]); `CHECK_1D(pack_struct_array[2][1]); i_pack_struct_2d(pack_struct_array[1]); `CHECK_2D(pack_struct_array[1]); i_pack_struct_3d(pack_struct_array); `CHECK_3D(pack_struct_array); i_pack_struct_1d1(pack_struct_array1[0][0]); `CHECK_1D1(pack_struct_array1[0][0]); i_pack_struct_2d1(pack_struct_array1[0]); `CHECK_2D1(pack_struct_array1[0]); i_pack_struct_3d1(pack_struct_array1); `CHECK_3D1(pack_struct_array1); `SET_VALUES(pack_struct_array); i_pack_struct_0d(pack_struct_array[3][2][1]); i_pack_struct_1d(pack_struct_array[2][1]); i_pack_struct_2d(pack_struct_array[1]); i_pack_struct_3d(pack_struct_array); `ifndef NO_UNPACK_STRUCT i_unpack_struct_0d(unpack_struct_array[3][2][1]); `CHECK_VAL(unpack_struct_array[3][2][1].val, 42); i_unpack_struct_1d(unpack_struct_array[2][1]); `CHECK_VAL(unpack_struct_array[2][1][0].val, 43); `CHECK_VAL(unpack_struct_array[2][1][1].val, 44); i_unpack_struct_2d(unpack_struct_array[1]); `CHECK_VAL(unpack_struct_array[1][0][1].val, 45); `CHECK_VAL(unpack_struct_array[1][1][1].val, 46); `CHECK_VAL(unpack_struct_array[1][2][1].val, 47); i_unpack_struct_3d(unpack_struct_array); `CHECK_VAL(unpack_struct_array[0][0][0].val, 48); `CHECK_VAL(unpack_struct_array[1][0][0].val, 49); `CHECK_VAL(unpack_struct_array[2][0][0].val, 50); `CHECK_VAL(unpack_struct_array[3][0][0].val, 51); i_unpack_struct_1d1(unpack_struct_array1[0][0]); `CHECK_VAL(unpack_struct_array1[0][0][0].val, 52); i_unpack_struct_2d1(unpack_struct_array1[0]); `CHECK_VAL(unpack_struct_array1[0][0][0].val, 53); i_unpack_struct_3d1(unpack_struct_array1); `CHECK_VAL(unpack_struct_array1[0][0][0].val, 54); `endif check_exports(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_scheduling_0.py0000755000542200017500000000073415101701376022336 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_gate_basic_specify_bad.out0000644000542200017500000000267615101701376024566 0ustar mahmoudyfreeshell%Warning-SPECIFYIGN: t/t_gate_basic.v:50:27: Ignoring unsupported: specify block construct 50 | (nt0 *> nt0) = (0, 0); | ^ ... For warning description see https://verilator.org/warn/SPECIFYIGN?v=latest ... Use "/* verilator lint_off SPECIFYIGN */" and lint_on around source to disable this message. %Warning-SPECIFYIGN: t/t_gate_basic.v:60:32: Ignoring unsupported: specify block construct 60 | (A1 *> Q) = (a$A1$Y, a$A1$Y); | ^ %Error-NEEDTIMINGOPT: t/t_gate_basic.v:24:10: Use --timing or --no-timing to specify how timing controls should be handled : ... note: In instance 't' 24 | not #(0.108) NT0 (nt0, a[0]); | ^ ... For error description see https://verilator.org/warn/NEEDTIMINGOPT?v=latest %Error-NEEDTIMINGOPT: t/t_gate_basic.v:25:10: Use --timing or --no-timing to specify how timing controls should be handled : ... note: In instance 't' 25 | and #1 AN0 (an0, a[0], b[0]); | ^ %Error-NEEDTIMINGOPT: t/t_gate_basic.v:26:10: Use --timing or --no-timing to specify how timing controls should be handled : ... note: In instance 't' 26 | nand #(2,3) ND0 (nd0, a[0], b[0], b[1]); | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_trace_fst_sc_cmake.v0000644000542200017500000000444415101701376023405 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // Author: Yu-Sheng Lin johnjohnlys@media.ee.ntu.edu.tw // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; int cyc; reg rstn; parameter real fst_gparam_real = 1.23; localparam real fst_lparam_real = 4.56; real fst_real = 1.23; integer fst_integer; bit fst_bit; logic fst_logic; int fst_int; shortint fst_shortint; longint fst_longint; byte fst_byte; parameter fst_parameter = 123; localparam fst_lparam = 456; supply0 fst_supply0; supply1 fst_supply1; tri0 fst_tri0; tri1 fst_tri1; tri fst_tri; wire fst_wire; logic [4:0] state; Test test (/*AUTOINST*/ // Outputs .state (state[4:0]), // Inputs .clk (clk), .rstn (rstn)); // Test loop always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==0) begin // Setup rstn <= ~'1; end else if (cyc<10) begin rstn <= ~'1; end else if (cyc<90) begin rstn <= ~'0; end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test ( input clk, input rstn, output logic [4:0] state ); logic [4:0] state_w; logic [4:0] state_array [3]; assign state = state_array[0]; always_comb begin state_w[4] = state_array[2][0]; state_w[3] = state_array[2][4]; state_w[2] = state_array[2][3] ^ state_array[2][0]; state_w[1] = state_array[2][2]; state_w[0] = state_array[2][1]; end always_ff @(posedge clk or negedge rstn) begin if (!rstn) begin for (int i = 0; i < 3; i++) state_array[i] <= 'b1; end else begin for (int i = 0; i < 2; i++) state_array[i] <= state_array[i+1]; state_array[2] <= state_w; end end endmodule verilator-5.042/test_regress/t/t_select_crazy.py0000755000542200017500000000073415101701376022461 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_opt_table_string.out0000644000542200017500000000023015101701376023474 0ustar mahmoudyfreeshellcyle 0 = case-0 cyle 1 = case-1 cyle 2 = case-2 cyle 3 = default cyle 4 = case-4 cyle 5 = case-5 cyle 6 = default cyle 7 = default *-* All Finished *-* verilator-5.042/test_regress/t/t_randomize_complex_associative_arrays.v0000644000542200017500000000252315101701376027274 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class SubClass; rand bit [2:0] field; function new (); field = 0; endfunction endclass class MyClass; SubClass sc_inst2[int]; function new (); sc_inst2[1] = new; endfunction endclass; class Deep; MyClass sc_inst1; function new (); sc_inst1 = new; endfunction endclass; class WeNeedToGoDeeper; Deep sc_inst; function new (); sc_inst = new; endfunction endclass; module t; initial begin WeNeedToGoDeeper cl_inst[string]; MyClass cl_inst2[int]; cl_inst["val1"] = new; cl_inst2[0] = new; repeat(10) begin if (cl_inst["val1"].sc_inst.sc_inst1.sc_inst2[1].randomize() with {field inside {1, 2, 3};} == 0) begin $stop; end if (cl_inst["val1"].sc_inst.sc_inst1.sc_inst2[1].field < 1 || cl_inst["val1"].sc_inst.sc_inst1.sc_inst2[1].field > 3) begin $stop; end if (cl_inst2[0].sc_inst2[1].randomize() with {field inside {1, 2, 3};} == 0) begin $stop; end if (cl_inst2[0].sc_inst2[1].field < 1 || cl_inst2[0].sc_inst2[1].field > 3) begin $stop; end end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_class_super_new2.v0000644000542200017500000000114615101701376023060 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Tudor Timi. // SPDX-License-Identifier: CC0-1.0 class svunit_base; function new(string name); endfunction endclass class svunit_testcase extends svunit_base; function new(string name); super.new(name); endfunction endclass module dut_unit_test; svunit_testcase svunit_ut = new("dut_ut"); endmodule module t; dut_unit_test dut_ut(); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_gen_for_shuffle.v0000644000542200017500000000403615101701376022736 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [31:0] out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out (out[31:0]), // Inputs .in (in[31:0])); // Aggregate outputs into a single result vector wire [63:0] result = {32'h0, out}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h3e3a62edb61f8c7f if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs out, // Inputs in ); input [31:0] in; output [31:0] out; genvar i; generate for (i=0; i<16; i=i+1) begin : gblk assign out[i*2+1:i*2] = in[(30-i*2)+1:(30-i*2)]; end endgenerate endmodule verilator-5.042/test_regress/t/t_langext_3.v0000644000542200017500000000101715101701376021463 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // A test of the +verilog2001ext+ and +verilog2005ext+ flags. // // This source code uses the uwire declaration, which is only valid in Verilog // 2005. // // Compile only test, so no need for "All Finished" output. // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; uwire w; // Only in Verilog 2005 endmodule verilator-5.042/test_regress/t/t_preproc_ifexpr_bad.v0000644000542200017500000000121415101701376023433 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `begin_keywords "1800-2023" `define ONE `undef ZERO `elsif ( ONE ) // BAD: elsif without if `endif `ifdef ( ) // BAD: Missing value `endif `ifdef ( && ZERO) // BAD: Expr `endif `ifdef ( ZERO && ) // BAD: Expr `endif `ifdef ( 1 ) // BAD: Constant `endif `ifdef ( ONE & ZERO) // BAD: Operator `endif `ifdef ( % ) // BAD: % is syntax error `endif `ifdef ) // BAD: ) without ( `endif `ifdef ( ONE // BAD: Missing paren `endif verilator-5.042/test_regress/t/t_dpi_unpack_bad.v0000644000542200017500000000174215101701376022527 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2020 by Yutetsu TAKATSUKASA. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; logic [2:0] sig0[3]; logic [2:0] sig1[3][2]; bit [2:0] sig2[3][3]; import "DPI-C" function void import_func0(input logic [3:0] in [0:2]); import "DPI-C" function void import_func1(input logic [2:0] in [0:2]); import "DPI-C" function void import_func2(input logic [2:0] in [0:2][0:2]); initial begin // packed width differs import_func0(sig0); // dimension differs import_func1(sig1); // unpacked extent differs import_func2(sig1); // bit v.s. logic mismatch import_func2(sig2); // packed var for unpacked port import_func0(sig0[1]); end endmodule verilator-5.042/test_regress/t/t_math_pow5.v0000644000542200017500000000362615101701376021512 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [67:0] q; reg signed [67:0] qs; initial begin q = 68'he_12345678_9abcdef0 ** 68'h3; if (q != 68'hcee3cb96ce96cf000) $stop; // q = 68'he_12345678_9abcdef0 ** 68'h5_6789abcd_ef012345; if (q != 68'h0) $stop; // qs = 68'she_12345678_9abcdef0 ** 68'sh3; if (qs != 68'shcee3cb96ce96cf000) $stop; // qs = 68'she_12345678_9abcdef0 ** 68'sh5_6789abcd_ef012345; if (qs != 68'h0) $stop; end reg [67:0] left; reg [67:0] right; wire [67:0] outu = left ** right; wire signed [67:0] outs = $signed(left) ** $signed(right); integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; `ifdef TEST_VERBOSE $write("%d %x %x %x %x\n", cyc, left, right, outu, outs); `endif if (cyc==1) begin left <= 68'h1; right <= '0; end if (cyc==2) begin if (outu != 68'h1) $stop; if (outs != 68'h1) $stop; end if (cyc==3) begin left <= 68'he_12345678_9abcdef0; right <= 68'h3; end if (cyc==4) begin if (outu != 68'hcee3cb96ce96cf000) $stop; if (outs != 68'hcee3cb96ce96cf000) $stop; end if (cyc==5) begin left <= 68'he_12345678_9abcdef0; right <= 68'h5_6789abcd_ef012345; end if (cyc==6) begin if (outu != 68'h0) $stop; if (outs != 68'h0) $stop; end if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.042/test_regress/t/t_func_endian.v0000644000542200017500000000536215101701376022057 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; wire noswap = crc[32]; wire nibble = crc[33]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [31:0] out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out (out[31:0]), // Inputs .clk (clk), .noswap (noswap), .nibble (nibble), .in (in[31:0])); // Aggregate outputs into a single result vector wire [63:0] result = {32'h0, out}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; if (sum !== 64'h89522c3f5e5ca324) $stop; $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs out, // Inputs clk, noswap, nibble, in ); input clk; input noswap; input nibble; input [31:0] in; output [31:0] out; function [7:0] EndianSwap; input Nibble; input [7:0] Data; begin EndianSwap = (Nibble ? { Data[0], Data[1], Data[2], Data[3], Data[4], Data[5], Data[6], Data[7] } : { 4'h0, Data[0], Data[1], Data[2], Data[3] }); end endfunction assign out[31:24] = (noswap ? in[31:24] : EndianSwap(nibble, in[31:24])); assign out[23:16] = (noswap ? in[23:16] : EndianSwap(nibble, in[23:16])); assign out[15:8] = (noswap ? in[15:8] : EndianSwap(nibble, in[15:8])); assign out[7:0] = (noswap ? in[7:0] : EndianSwap(nibble, in[7:0])); endmodule verilator-5.042/test_regress/t/t_property.py0000755000542200017500000000077615101701376021664 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--assert --cc']) test.execute() test.passes() verilator-5.042/test_regress/t/t_struct_initial_assign.v0000644000542200017500000000351415101701376024204 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Issue #5381 typedef struct packed { logic field0; logic field1; } str_t; module t (/*AUTOARG*/ // Inputs clk ); input clk; str_t bar_in; str_t bar_out; Sub sub(bar_in, bar_out); // Test procedure initial begin integer i; str_t initOut; bar_in = '0; // Set bar_in to 0 initially // Wait for the first falling edge of the clock @(negedge clk); // Capture the initial output value initOut = bar_out; // Apply stimulus for 10 clock cycles for (i = 0; i < 10; i = i + 1) begin if (i > 0) begin bar_in = '1; // Switch to 1 after the first cycle end @(negedge clk); // Check if the output field0 has changed $display("bar_out.field0 = %h", bar_out.field0); $display("initOut.field0 = %h", initOut.field0); if (bar_out.field0 !== initOut.field0) begin $display("%%Error: bar_out value changed when it should not have"); $stop; end end $write("*-* All Finished *-*\n"); $finish; end endmodule module Sub ( input str_t bar_in, output str_t bar_out ); // This is a continuous assignment always_comb begin bar_out.field1 = bar_in.field1; end // This should be an initial assignment, but verilator thinks it's a continous assignment logic temp0 = bar_in.field0; // If it is observed (verilator public, coverage, etc.), then it switches correctly to initial // logic temp0 /* verilator public */ = bar_in.field0; always_comb begin bar_out.field0 = temp0; end endmodule verilator-5.042/test_regress/t/t_gate_basic.py0000755000542200017500000000101715101701376022046 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--no-timing", "-Wno-SPECIFYIGN"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_clk_gen.py0000755000542200017500000000073415101701376021374 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_preproc_inc4.vh0000644000542200017500000000036615101701376022344 0ustar mahmoudyfreeshell// DESCRIPTION: Verilog::Preproc: Example source code // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2000-2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define T_PREPROC_INC4 verilator-5.042/test_regress/t/t_unpacked_struct_eq.v0000644000542200017500000000404515101701376023466 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Use this file as a template for submitting bugs, etc. // This module takes a single clock input, and should either // $write("*-* All Finished *-*\n"); // $finish; // on success, or $stop. // // The code as shown applies a random vector to the Test // module, then calculates a CRC on the Test module's outputs. // // **If you do not wish for your code to be released to the public // please note it here, otherwise:** // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; typedef struct{ bit [31:0] subarr[4]; } arr_str_t; typedef struct { string txt; struct { bit m0; bit [3:0] m1; bit [7:0] arr[2][3]; arr_str_t str[5]; } sub; } struct_t; struct_t s1; struct_t s2; struct_t s3; assign {s1.sub.m0, s1.sub.m1} = {1'b0, 4'h5}; assign {s2.sub.m0, s2.sub.m1} = {1'b0, 4'h5}; assign s1.txt = "text"; assign s2.txt = "text"; assign {s1.sub.arr[0][0], s2.sub.arr[0][0]} = {8'h01, 8'h01}; assign {s1.sub.arr[0][1], s2.sub.arr[0][1]} = {8'h02, 8'h02}; assign {s1.sub.arr[0][2], s2.sub.arr[0][2]} = {8'h03, 8'h03}; assign {s1.sub.arr[1][0], s2.sub.arr[1][0]} = {8'h04, 8'h04}; assign {s1.sub.arr[1][1], s2.sub.arr[1][1]} = {8'h05, 8'h05}; assign {s1.sub.arr[1][2], s2.sub.arr[1][2]} = {8'h06, 8'h06}; assign {s3.sub.m0, s3.sub.m1} = {1'b0, 4'h5}; assign s3.txt = "text"; assign s3.sub.arr[0][0] = 8'h01; assign s3.sub.arr[0][1] = 8'h02; assign s3.sub.arr[0][2] = 8'h03; assign s3.sub.arr[1][0] = 8'h24; // One mismatch assign s3.sub.arr[1][1] = 8'h05; assign s3.sub.arr[1][2] = 8'h06; initial begin #1; if(s3 == s1) $stop; if(s1 == s2 && s3 != s1) begin $write("*-* All Finished *-*\n"); $finish; end else begin $fatal; end end endmodule verilator-5.042/test_regress/t/t_opt_expand_keep_widths.py0000755000542200017500000000103515101701376024514 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--binary']) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_mod_mod.py0000755000542200017500000000077315101701376021413 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_compiler_include_dpi.v0000644000542200017500000000147215101701376023755 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2024 by Antmicro. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; int a = 123; int b = 321; int out; import "DPI-C" function void dpii_add (int a, int b, ref int out); import "DPI-C" function int dpii_add_check (int actual, int expected); initial begin dpii_add(a, b, out); if (dpii_add_check(out, (a + b)) != 1) begin $write("%%Error: Failure in DPI tests\n"); $stop; end else begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_name_collision.py0000755000542200017500000000077315101701376022770 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--coverage']) test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_genunnamed_bad.v0000644000542200017500000000112515101701376023554 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; parameter P = 1; if (P) ; if (P) begin initial $display; end else begin initial $display; end for (genvar v = 0; v < P; ++v) ; for (genvar v = 0; v < P; ++v) begin initial $display; end case (P) 1: initial begin end 2: begin initial begin end end endcase endmodule verilator-5.042/test_regress/t/t_mem_multi_io3.cpp0000644000542200017500000000105115101701376022654 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // This file ONLY is placed into the Public Domain, for any use, // without warranty. // SPDX-License-Identifier: CC0-1.0 #include VM_PREFIX_INCLUDE VM_PREFIX* tb = nullptr; bool pass = true; double sc_time_stamp() { return 0; } #ifdef SYSTEMC_VERSION int sc_main(int, char**) #else int main() #endif { Verilated::debug(0); tb = new VM_PREFIX{"tb"}; tb->final(); VL_DO_DANGLING(delete tb, tb); // Just a constructor test VL_PRINTF("*-* All Finished *-*\n"); return 0; } verilator-5.042/test_regress/t/t_array_packed_endian.py0000755000542200017500000000073415101701376023735 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_array_non_blocking_loop.py0000755000542200017500000000073415101701376024663 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_sys_fstrobe.out0000644000542200017500000000016015101701376022501 0ustar mahmoudyfreeshell[110] cyc=11 [110] cyc=11 also 00000000000000000000000000010010b 00000013h 00000000024o [230] cyc=23 new-strobe verilator-5.042/test_regress/t/t_vams_wreal.py0000755000542200017500000000073415101701376022132 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_implements.v0000644000542200017500000000272715101701376021765 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface class Icempty; endclass : Icempty interface class Icls1; localparam LP1 = 1; pure virtual function int icf1; pure virtual function int icfboth; pure virtual function int icfpartial; endclass interface class Iext1 extends Icls1; pure virtual function int icf101; endclass interface class Icls2; pure virtual function int icf2(int in); pure virtual function int icfboth; endclass virtual class Base implements Iext1, Icls2; virtual function int icf1; return 1; endfunction virtual function int icf101; return 101; endfunction virtual function int icf2(int in); return in + 2; endfunction virtual function int icfboth; return 3; endfunction pure virtual function int icfpartial; endclass class Cls extends Base; virtual function int icfpartial; return 62; endfunction endclass module t; Cls c; Iext1 i1; initial begin if (Icls1::LP1 != 1) $stop; c = new; if (c.icf1() != 1) $stop; if (c.icf101() != 101) $stop; if (c.icf2(1000) != 1002) $stop; if (c.icfpartial() != 62) $stop; i1 = c; if (i1.icf1() != 1) $stop; if (i1.icf101() != 101) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_trace_scope_no_inline.py0000755000542200017500000000113615101701376024310 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["--cc --trace-vcd -fno-inline t/" + test.name + ".vlt"]) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_param_resolve_args.py0000755000542200017500000000073415101701376023645 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_array_query.v0000644000542200017500000000255215101701376022147 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: System Verilog test of array querying functions. // // This code instantiates a module that calls the various array querying // functions. // // This file ONLY is placed into the Public Domain, for any use, without // warranty. // SPDX-License-Identifier: CC0-1.0 // Contributed 2012 by Jeremy Bennett, Embecosm. module t (/*AUTOARG*/ // Inputs clk ); input clk; wire a = clk; wire b = 1'b0; reg c; array_test array_test_i (/*AUTOINST*/ // Inputs .clk (clk)); endmodule // Check the array sizing functions work correctly. module array_test #( parameter LEFT = 5, RIGHT = 55) (/*AUTOARG*/ // Inputs clk ); input clk; // verilator lint_off ASCRANGE reg [7:0] a [LEFT:RIGHT]; // verilator lint_on ASCRANGE typedef reg [7:0] r_t; integer l; integer r; integer s; always @(posedge clk) begin l = $left (a); r = $right (a); s = $size (a); `ifdef TEST_VERBOSE $write ("$left (a) = %d, $right (a) = %d, $size (a) = %d\n", l, r, s); `endif if ((l != LEFT) || (r != RIGHT) || (s != (RIGHT - LEFT + 1))) $stop; if ($left(r_t)!=7 || $right(r_t)!=0 || $size(r_t)!=8 || $bits(r_t) !=8) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_assert_synth_parallel_vlt.out0000644000542200017500000000060615101701376025433 0ustar mahmoudyfreeshell[0] -Info: t_assert_synth.v:115: top.t.test_info: Start of $info test [0] -Info: t_assert_synth.v:116: top.t.test_info: Middle of $info test [0] -Info: t_assert_synth.v:117: top.t.test_info: End of $info test [40] %Error: t_assert_synth.v:55: Assertion failed in top.t: synthesis parallel_case, but multiple matches found for '1'h1' %Error: t/t_assert_synth.v:55: Verilog $stop Aborting... verilator-5.042/test_regress/t/t_string_octal.v0000644000542200017500000000266415101701376022300 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checko(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t; string s; initial begin s = $sformatf("\099 \119 \121"); // Q Q Q // $display("%o %o %o %o %o", s[0], s[1], s[2], s[3], s[4]); // Results vary by simulator. Some possibilities: // 0 0 0 0 0 // 40 71 71 40 11 // 71 71 40 11 071 s = $sformatf("\088 \108 \110"); // H H H // $display("%o %o %o %o %o", s[0], s[1], s[2], s[3], s[4]); // Results vary by simulator. Some possibilities: // 0 0 0 0 0 // 40 70 70 40 10 // 70 70 40 10 70 s = $sformatf("\102\3\12."); // B\023\312. // $display("%o %o %o %o %o", s[0], s[1], s[2], s[3], s[4]); `checko(s[0], 8'o102); `checko(s[1], 8'o003); `checko(s[2], 8'o012); `checko(s[3], 8'o056); s = $sformatf("\102.\3.\12\103"); // B.\023.C // $display("%o %o %o %o %o", s[0], s[1], s[2], s[3], s[4]); `checko(s[0], 8'o102); `checko(s[2], 8'o003); `checko(s[4], 8'o012); `checko(s[5], 8'o103); $display("*-* All Finished *-*"); $finish; end endmodule verilator-5.042/test_regress/t/t_udp_sequential_bad.out0000644000542200017500000000051515101701376023773 0ustar mahmoudyfreeshell%Error: t/t_udp_sequential_bad.v:8:8: For combinational UDP, the output must not be a 'reg' data type : ... note: In instance 'top' 8 | output dout; | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_dynarray_multid.v0000644000542200017500000001226215101701376023012 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t; integer a1 [][]; integer a2 [2][]; integer a3 [][] = '{'{1, 2, 3}, '{4, 5, 6}}; integer a4 [][] = '{{7, 8, 9}, {10, 11, 12}}; integer a5 [][] = '{3{'{13, 14}}}; integer aa1 [string][]; integer wa1 [*][]; integer qa1 [$][]; struct { integer i; integer a[]; } s1; integer a[] = '{1,2,3}; logic [7:0][3:0] a6 [][]; initial begin `checkh(a1.size, 0); a1 = new [3]; `checkh(a1.size, 3); `checkh($size(a1), 3); `checkh($high(a1), 2); `checkh($right(a1), 2); foreach (a1[i]) a1[i] = new [i + 1]; foreach (a1[i]) begin `checkh(a1[i].size, i + 1); `checkh($size(a1[i]), i + 1); `checkh($high(a1[i]), i); `checkh($right(a1[i]), i); end foreach (a1[i, j]) a1[i][j] = i * 10 + j; `checkh(a1[0][0], 0); `checkh(a1[1][0], 10); `checkh(a1[1][1], 11); `checkh(a1[2][0], 20); `checkh(a1[2][1], 21); `checkh(a1[2][2], 22); `checkh(a1[2].sum, 63); foreach (a1[i]) a1[i].delete; foreach (a1[i]) begin `checkh(a1[i].size, 0); end a1.delete; `checkh(a1.size, 0); a1 = new [2]; `checkh(a1.size, 2); foreach (a1[i]) a1[i] = new [i + 2]; foreach (a1[i]) begin `checkh(a1[i].size, i + 2); end foreach (a2[i]) begin `checkh(a2[i].size, 0); end foreach (a2[i]) a2[i] = new [i + 1]; foreach (a2[i]) begin `checkh(a2[i].size, i + 1); end foreach (a2[i]) a2[i].delete; foreach (a2[i]) begin `checkh(a2[i].size, 0); end `checkh(a3.size, 2); foreach (a3[i]) begin `checkh(a3[i].size, 3); end `checkh(a3[0][0], 1); `checkh(a3[0][1], 2); `checkh(a3[0][2], 3); `checkh(a3[1][0], 4); `checkh(a3[1][1], 5); `checkh(a3[1][2], 6); `checkh(a4.size, 2); foreach (a4[i]) begin `checkh(a4[i].size, 3); end `checkh(a4[0][0], 7); `checkh(a4[0][1], 8); `checkh(a4[0][2], 9); `checkh(a4[1][0], 10); `checkh(a4[1][1], 11); `checkh(a4[1][2], 12); `checkh(a5.size, 3); foreach (a5[i]) begin `checkh(a5[i].size, 2); end `checkh(a5[0][0], 13); `checkh(a5[0][1], 14); `checkh(a5[1][0], 13); `checkh(a5[1][1], 14); `checkh(a5[2][0], 13); `checkh(a5[2][1], 14); a5 = a4; `checkh(a5.size, 2); foreach (a5[i]) begin `checkh(a5[i].size, 3); end `checkh(a5[0][0], 7); `checkh(a5[0][1], 8); `checkh(a5[0][2], 9); `checkh(a5[1][0], 10); `checkh(a5[1][1], 11); `checkh(a5[1][2], 12); a4 = '{'{15, 16}, '{17, 18}}; `checkh(a4.size, 2); foreach (a4[i]) begin `checkh(a4[i].size, 2); end `checkh(a4[0][0], 15); `checkh(a4[0][1], 16); `checkh(a4[1][0], 17); `checkh(a4[1][1], 18); a4 = '{{19}, {20}, {21, 22}}; `checkh(a4.size, 3); `checkh(a4[0].size, 1); `checkh(a4[1].size, 1); `checkh(a4[2].size, 2); `checkh(a4[0][0], 19); `checkh(a4[1][0], 20); `checkh(a4[2][0], 21); `checkh(a4[2][1], 22); a5 = '{2{a}}; `checkh(a5.size, 2); foreach (a5[i]) begin `checkh(a5[i].size, 3); end `checkh(a5[0][0], 1); `checkh(a5[0][1], 2); `checkh(a5[0][2], 3); `checkh(a5[1][0], 1); `checkh(a5[1][1], 2); `checkh(a5[1][2], 3); a5 = '{}; `checkh(a5.size, 0); a5 = '{2{'{}}}; `checkh(a5.size, 2); foreach (a5[i]) begin `checkh(a5[i].size, 0); end aa1["k1"] = new [3]; `checkh(aa1["k1"].size, 3); aa1["k1"].delete; wa1[1] = new [3]; `checkh(wa1[1].size, 3); wa1[1].delete; qa1.push_back(a); `checkh(qa1[0].size, 3); qa1[0] = new [4]; `checkh(qa1[0].size, 4); qa1[0].delete; qa1[$-1].delete; `checkh(qa1[$-1].size, 0); qa1.delete; `checkh(qa1.size, 0); `checkh(qa1[$-1].size, 0); `checkh(qa1.size, 0); s1.a = new [4]; `checkh(s1.a.size, 4); s1.a.delete; `checkh($dimensions(a1), 3); `checkh($dimensions(a2), 3); `checkh($dimensions(aa1), 3); `checkh($dimensions(wa1), 3); `checkh($dimensions(qa1), 3); `checkh($dimensions(a), 2); `checkh($dimensions(a6), 4); `checkh($unpacked_dimensions(a1), 2); `checkh($unpacked_dimensions(a2), 2); `checkh($unpacked_dimensions(aa1), 2); `checkh($unpacked_dimensions(wa1), 2); `checkh($unpacked_dimensions(qa1), 2); `checkh($unpacked_dimensions(a), 1); `checkh($unpacked_dimensions(a6), 2); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_math_precedence.v0000644000542200017500000001137215101701376022712 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; wire [1:0] a = crc[1 +: 2]; wire [1:0] b = crc[3 +: 2]; wire [1:0] c = crc[5 +: 2]; wire [1:0] d = crc[7 +: 2]; wire [1:0] e = crc[9 +: 2]; wire [1:0] f = crc[11+: 2]; wire [1:0] g = crc[13+: 2]; // left () [] :: . // unary + - ! ~ & ~& | ~| ^ ~^ ^~ ++ -- (unary) // left ** // left * / % // left + - (binary) // left << >> <<< >>> // left < <= > >= inside dist // left == != === !== ==? !=? // left & (binary) // left ^ ~^ ^~ (binary) // left | (binary) // left && // left || // left ? : // right -> // none = += -= *= /= %= &= ^= |= <<= >>= <<<= >>>= := :/ <= // {} {{}} concatenation wire [1:0] bnz = (b==2'b0) ? 2'b11 : b; wire [1:0] cnz = (c==2'b0) ? 2'b11 : c; wire [1:0] dnz = (d==2'b0) ? 2'b11 : d; wire [1:0] enz = (e==2'b0) ? 2'b11 : e; // verilator lint_off WIDTH // Do a few in each group wire [1:0] o1 = ~ a; // Can't get more than one reduction to parse wire [1:0] o2 = ^ b; // Can't get more than one reduction to parse wire [1:0] o3 = a ** b ** c; // Some simulators botch this wire [1:0] o4 = a * b / cnz % dnz * enz; wire [1:0] o5 = a + b - c + d; wire [1:0] o6 = a << b >> c <<< d >>> e <<< f; wire [1:0] o7 = a < b <= c; wire [1:0] o8 = a == b != c === d == e; wire [1:0] o9 = a & b & c; wire [1:0] o10 = a ^ b ~^ c ^~ d ^ a; wire [1:0] o11 = a | b | c; wire [1:0] o12 = a && b && c; wire [1:0] o13 = a || b || c; wire [1:0] o14 = a ? b ? c : d : e; wire [1:0] o15 = a ? b : c ? d : e; // Now cross each pair of groups wire [1:0] x1 = ~ a ** ~ b ** ~c; // Some simulators botch this wire [1:0] x2 = a ** b * c ** d; // Some simulators botch this wire [1:0] x3 = a + b * c + d; wire [1:0] x4 = a + b << c + d; wire [1:0] x5 = a == b << c == d; wire [1:0] x6 = a & b << c & d; wire [1:0] x7 = a ^ b & c ^ d; wire [1:0] x8 = a | b ^ c | d; wire [1:0] x9 = a && b | c && d; wire [1:0] x10 = a || b && c || d; wire [1:0] x11 = a ? b || c : d ? e : f; // verilator lint_on WIDTH function [1:0] pow (input [1:0] x, input [1:0] y); casez ({x,y}) 4'b00_??: pow = 2'b00; 4'b01_00: pow = 2'b01; 4'b01_01: pow = 2'b01; 4'b01_10: pow = 2'b01; 4'b01_11: pow = 2'b01; 4'b10_00: pow = 2'b01; 4'b10_01: pow = 2'b10; 4'b10_10: pow = 2'b00; 4'b10_11: pow = 2'b00; 4'b11_00: pow = 2'b01; 4'b11_01: pow = 2'b11; 4'b11_10: pow = 2'b01; 4'b11_11: pow = 2'b11; endcase endfunction // Aggregate outputs into a single result vector wire [63:0] result = {12'h0, x11,x10,x9,x8,x7,x6,x5,x4,x3,x2,x1, o15,o14,o13,o12,o11,o10,o9,o8,o7,o6,o5,o4,o3,o2,o1}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x ", $time, cyc, crc, result); $write(" %b",o1); $write(" %b",o2); $write(" %b",o3); $write(" %b",o4); $write(" %b",o5); $write(" %b",o6); $write(" %b",o7); $write(" %b",o8); $write(" %b",o9); $write(" %b",o10); $write(" %b",o11); $write(" %b",o12); $write(" %b",o13); $write(" %b",o14); $write(" %b",o15); // Now cross each pair of groups $write(" %b",x1); $write(" %b",x2); $write(" %b",x3); $write(" %b",x4); $write(" %b",x5); $write(" %b",x6); $write(" %b",x7); $write(" %b",x8); $write(" %b",x9); $write(" %b",x10); $write(" %b",x11); $write("\n"); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h2756ea365ec7520e if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_package_dup_bad.py0000755000542200017500000000076615101701376023050 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_trace_two_dump_sc.py0000755000542200017500000000250515101701376023471 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t_trace_two_a.v" test.pli_filename = "t/t_trace_two_sc.cpp" if not test.have_sc: test.skip("No SystemC installed") test.compile(make_main=False, verilator_make_gmake=False, top_filename='t_trace_two_b.v', vm_prefix='Vt_trace_two_b', verilator_flags2=['-sc -trace']) test.run(logfile=test.obj_dir + "/make_first_ALL.log", cmd=[ os.environ["MAKE"], "-C", test.obj_dir, "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp" ]) test.compile(make_main=False, top_filename='t_trace_two_a.v', verilator_flags2=['-sc', '-exe', '-trace', test.pli_filename], v_flags2=['+define+TEST_DUMP']) test.execute() if test.vlt_all: test.file_grep(test.trace_filename, r'\$enddefinitions') test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_typedef_consistency_0.v0000644000542200017500000000150215101701376024076 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package pkg; typedef logic l; endpackage module t(/*AUTOARG*/ // Inputs clk ); input clk; wire logic o_logic; // Using 'pkg::l' instead of 'logic' should make no difference wire pkg::l o_alias; sub sub_logic(o_logic); sub sub_alias(o_alias); assign o_logic = clk; assign o_alias = clk; always @(posedge clk) begin $display("o_logic: %b o_alias: %b", o_logic, o_alias); // Whatever the answer is, it should be the same if (o_logic !== o_alias) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module sub(output wire o); endmodule verilator-5.042/test_regress/t/t_select_little.py0000755000542200017500000000073415101701376022626 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_flag_only_bad3.py0000755000542200017500000000123415101701376022631 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_flag_main.v" test.lint(verilator_flags2=[ "-Wall -Wno-DEPRECATED --lint-only -Wno-fatal --dpi-hdr-only --xml-only --json-only" ], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dpi_instr_count_large_hier.py0000755000542200017500000000151415101701376025353 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vltmt') test.clean_objs() test.top_filename = "t/t_dpi_instr_count_large.v" test.compile( v_flags2=["t/t_dpi_instr_count_large.cpp"], verilator_flags2=[ "--hierarchical", "--instr-count-dpi 999999999", # Force UNOPTTHREADS error to cause Contraction limit increase beyond UINT32 "--threads-max-mtasks 1", "-Wno-UNOPTTHREADS" ], threads=2) test.execute() test.passes() verilator-5.042/test_regress/t/t_flag_decoration_no.py0000755000542200017500000000141715101701376023605 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_flag_decoration.v" test.compile(verilator_flags2=["--no-decoration"]) test.file_grep(test.obj_dir + "/V" + test.name + ".h", r'\n// CONSTRUCTORS') test.file_grep_not(test.obj_dir + "/V" + test.name + ".h", r'\n // CONSTRUCTORS') test.file_grep_not(test.obj_dir + "/V" + test.name + ".h", r'/\*t/t_flag_decoration') test.passes() verilator-5.042/test_regress/t/t_scheduling_4.v0000644000542200017500000000230515101701376022150 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2022 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VERILATOR // The '$c1(1)' is there to prevent inlining of the signal by V3Gate `define IMPURE_ONE $c(1); `else // Use standard $random (chaces of getting 2 consecutive zeroes is zero). `define IMPURE_ONE |($random | $random); `endif module top( clk ); input clk; reg clk_half = 0; reg [31:0] cyc = 0; reg [31:0] a = 1, b = 2, c = 2; always @(posedge clk) begin $display("tick %d: a: %d, b: %d, c: %d", cyc, a, b, c); // Check invariant if (cyc > 0) begin if (a !== cyc + 1) $stop; if (b !== cyc + 2) $stop; if (c !== cyc + 2) $stop; end // End of test if (cyc == 100) begin $write("*-* All Finished *-*\n"); $finish; end cyc <= cyc + 1; end always @(edge cyc[0]) a = cyc + `IMPURE_ONE; always @(edge a[0]) b = a + `IMPURE_ONE; assign c = a + `IMPURE_ONE; endmodule verilator-5.042/test_regress/t/t_force_immediate_release.py0000755000542200017500000000076315101701376024610 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_select_lhs_oob2.py0000755000542200017500000000073415101701376023040 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_forceable_net.vlt0000644000542200017500000000041015101701376022723 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 `verilator_config forceable -module "*" -var "net_*" verilator-5.042/test_regress/t/t_enum_recurse_bad2.py0000755000542200017500000000076615101701376023363 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_struct_array_assignment_delayed.py0000755000542200017500000000101315101701376026422 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(timing_loop=True, verilator_flags2=["--timing"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_param_const_part.v0000644000542200017500000000126715101701376023142 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2015 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; function integer bottom_4bits; input [7:0] i; bottom_4bits = 0; bottom_4bits[3:0] = i[3:0]; endfunction function integer bottom_2_unknown; input [7:0] i; // bottom_4bits = 0; 'x bottom_2_unknown[1:0] = i[1:0]; endfunction localparam P = bottom_4bits(8'h13); localparam BU = bottom_2_unknown(8'h13); initial begin if (P != 3) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_public_clk.v0000644000542200017500000000133515101701376021711 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: public clock signal // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2022 by Todd Strader // SPDX-License-Identifier: CC0-1.0 `ifdef VERILATOR // The '$c1(1)' is there to prevent inlining of the signal by V3Gate `define IMPURE_ONE ($c(1)) `else // Use standard $random (chaces of getting 2 consecutive zeroes is zero). `define IMPURE_ONE (|($random | $random)) `endif module t (); logic clk /* verilator public_flat_rw */; int count; wire other_clk = `IMPURE_ONE & clk; always_ff @(posedge other_clk) begin count <= count + 1; if (count == 10) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_timing_delay_callstack.py0000755000542200017500000000077115101701376024461 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_gate_implicit.v0000644000542200017500000000411115101701376022407 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire RBL2; // From t of Test.v // End of automatics wire RWL1 = crc[2]; wire RWL2 = crc[3]; Test t (/*AUTOINST*/ // Outputs .RBL2 (RBL2), // Inputs .RWL1 (RWL1), .RWL2 (RWL2)); // Aggregate outputs into a single result vector wire [63:0] result = {63'h0, RBL2}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'hb6d6b86aa20a882a if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test ( output RBL2, input RWL1, RWL2); // verilator lint_off IMPLICIT not I1 (RWL2_n, RWL2); bufif1 I2 (RBL2, n3, 1'b1); Mxor I3 (n3, RWL1, RWL2_n); // verilator lint_on IMPLICIT endmodule module Mxor (output out, input a, b); assign out = (a ^ b); endmodule verilator-5.042/test_regress/t/t_bitsel_wire_array_bad.py0000755000542200017500000000102015101701376024273 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') # Compile time only test test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_func_nansi_mism_bad.out0000644000542200017500000000172515101701376024125 0ustar mahmoudyfreeshell%Error: t/t_func_nansi_mism_bad.v:12:11: Non-ANSI I/O declaration of signal conflicts with type declaration: 'bad1' 12 | input [15:0] bad1; | ^ t/t_func_nansi_mism_bad.v:13:5: ... Location of other declaration 13 | shortint bad1; | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_func_nansi_mism_bad.v:17:11: Non-ANSI I/O declaration of signal conflicts with type declaration: 'bad2' 17 | input [31:0] bad2; | ^ t/t_func_nansi_mism_bad.v:18:5: ... Location of other declaration 18 | T bad2; | ^ %Error: t/t_func_nansi_mism_bad.v:22:11: Non-ANSI I/O declaration of signal conflicts with type declaration: 'bad3' 22 | input [7:0] bad3; | ^ t/t_func_nansi_mism_bad.v:23:5: ... Location of other declaration 23 | reg [3:0] bad3; | ^~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_flag_woff_bad.py0000755000542200017500000000110015101701376022516 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--lint-only -Wno-NOSUCHERRORASTHIS"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_constraint_json_only.out0000644000542200017500000003623215101701376024426 0ustar mahmoudyfreeshell{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"(E)","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"UNLINKED", "modulesp": [ {"type":"MODULE","name":"t","addr":"(F)","loc":"d,67:8,67:9","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"t","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"p","addr":"(G)","loc":"d,69:11,69:12","dtypep":"(H)","origName":"p","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"Packet","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"INITIAL","name":"","addr":"(I)","loc":"d,71:4,71:11","isSuspendable":false,"needProcess":false, "stmtsp": [ {"type":"BEGIN","name":"","addr":"(J)","loc":"d,71:12,71:17","implied":false,"needProcess":false,"unnamed":true,"declsp": [], "stmtsp": [ {"type":"DISPLAY","name":"","addr":"(K)","loc":"d,73:7,73:13", "fmtp": [ {"type":"SFORMATF","name":"*-* All Finished *-*\\n","addr":"(L)","loc":"d,73:7,73:13","dtypep":"(M)","exprsp": [],"scopeNamep": []} ],"filep": []}, {"type":"FINISH","name":"","addr":"(N)","loc":"d,74:7,74:14"} ]} ]} ]}, {"type":"PACKAGE","name":"$unit","addr":"(E)","loc":"a,0:0,0:0","origName":"__024unit","level":3,"modPublic":false,"inLibrary":true,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"CLASS","name":"Packet","addr":"(O)","loc":"d,7:1,7:6","isExtended":false,"isInterfaceClass":false,"isVirtual":false,"origName":"Packet","level":4,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","classOrPackagep":"UNLINKED","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"header","addr":"(P)","loc":"d,8:13,8:19","dtypep":"(Q)","origName":"header","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VAUTOMI","varType":"MEMBER","dtypeName":"int","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"length","addr":"(R)","loc":"d,9:13,9:19","dtypep":"(Q)","origName":"length","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VAUTOMI","varType":"MEMBER","dtypeName":"int","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"sublength","addr":"(S)","loc":"d,10:13,10:22","dtypep":"(Q)","origName":"sublength","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VAUTOMI","varType":"MEMBER","dtypeName":"int","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"if_4","addr":"(T)","loc":"d,11:13,11:17","dtypep":"(U)","origName":"if_4","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VAUTOMI","varType":"MEMBER","dtypeName":"bit","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"iff_5_6","addr":"(V)","loc":"d,12:13,12:20","dtypep":"(U)","origName":"iff_5_6","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VAUTOMI","varType":"MEMBER","dtypeName":"bit","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"if_state_ok","addr":"(W)","loc":"d,13:13,13:24","dtypep":"(U)","origName":"if_state_ok","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VAUTOMI","varType":"MEMBER","dtypeName":"bit","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"array","addr":"(X)","loc":"d,15:13,15:18","dtypep":"(Y)","origName":"array","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VAUTOMI","varType":"MEMBER","dtypeName":"","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"state","addr":"(Z)","loc":"d,17:11,17:16","dtypep":"(M)","origName":"state","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VAUTOMI","varType":"MEMBER","dtypeName":"string","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"FUNC","name":"strings_equal","addr":"(AB)","loc":"d,61:17,61:30","dtypep":"(U)","method":true,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"strings_equal", "fvarp": [ {"type":"VAR","name":"strings_equal","addr":"(BB)","loc":"d,61:17,61:30","dtypep":"(U)","origName":"strings_equal","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":true,"isFuncLocal":true,"lifetime":"VAUTOM","varType":"MEMBER","dtypeName":"bit","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ],"classOrPackagep": [], "stmtsp": [ {"type":"VAR","name":"a","addr":"(CB)","loc":"d,61:38,61:39","dtypep":"(M)","origName":"a","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":true,"lifetime":"VAUTOMI","varType":"MEMBER","dtypeName":"string","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"b","addr":"(DB)","loc":"d,61:48,61:49","dtypep":"(M)","origName":"b","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":true,"lifetime":"VAUTOMI","varType":"MEMBER","dtypeName":"string","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"ASSIGN","name":"","addr":"(EB)","loc":"d,62:7,62:13","dtypep":"(U)", "rhsp": [ {"type":"EQN","name":"","addr":"(FB)","loc":"d,62:16,62:18","dtypep":"(GB)", "lhsp": [ {"type":"VARREF","name":"a","addr":"(HB)","loc":"d,62:14,62:15","dtypep":"(M)","access":"RD","varp":"(CB)","varScopep":"UNLINKED","classOrPackagep":"(O)"} ], "rhsp": [ {"type":"VARREF","name":"b","addr":"(IB)","loc":"d,62:19,62:20","dtypep":"(M)","access":"RD","varp":"(DB)","varScopep":"UNLINKED","classOrPackagep":"(O)"} ]} ], "lhsp": [ {"type":"VARREF","name":"strings_equal","addr":"(JB)","loc":"d,62:7,62:13","dtypep":"(U)","access":"WR","varp":"(BB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": []} ],"scopeNamep": []}, {"type":"FUNC","name":"new","addr":"(KB)","loc":"d,7:1,7:6","dtypep":"(LB)","method":true,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"new","fvarp": [],"classOrPackagep": [],"stmtsp": [],"scopeNamep": []}, {"type":"VAR","name":"constraint","addr":"(MB)","loc":"d,7:1,7:6","dtypep":"(NB)","origName":"constraint","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"MEMBER","dtypeName":"VlRandomizer","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ],"extendsp": []} ]} ],"filesp": [], "miscsp": [ {"type":"TYPETABLE","name":"","addr":"(C)","loc":"a,0:0,0:0","constraintRefp":"UNLINKED","emptyQueuep":"UNLINKED","queueIndexp":"UNLINKED","streamp":"UNLINKED","voidp":"(LB)", "typesp": [ {"type":"BASICDTYPE","name":"logic","addr":"(GB)","loc":"d,22:14,22:15","dtypep":"(GB)","keyword":"logic","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(OB)","loc":"d,25:21,25:22","dtypep":"(OB)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"string","addr":"(M)","loc":"d,73:7,73:13","dtypep":"(M)","keyword":"string","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"int","addr":"(Q)","loc":"d,8:9,8:12","dtypep":"(Q)","keyword":"int","range":"31:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"bit","addr":"(U)","loc":"d,11:9,11:12","dtypep":"(U)","keyword":"bit","generic":true,"rangep": []}, {"type":"UNPACKARRAYDTYPE","name":"","addr":"(Y)","loc":"d,15:18,15:19","dtypep":"(Y)","isCompound":false,"declRange":"[0:1]","generic":false,"refDTypep":"(Q)","childDTypep": [], "rangep": [ {"type":"RANGE","name":"","addr":"(PB)","loc":"d,15:18,15:19","ascending":true,"fromBracket":true, "leftp": [ {"type":"CONST","name":"32'h0","addr":"(QB)","loc":"d,15:19,15:20","dtypep":"(OB)"} ], "rightp": [ {"type":"CONST","name":"32'h1","addr":"(RB)","loc":"d,15:19,15:20","dtypep":"(OB)"} ]} ]}, {"type":"VOIDDTYPE","name":"","addr":"(LB)","loc":"d,7:1,7:6","dtypep":"(LB)","generic":false}, {"type":"CLASSREFDTYPE","name":"Packet","addr":"(H)","loc":"d,69:4,69:10","dtypep":"(H)","generic":false,"classp":"(O)","classOrPackagep":"(O)","paramsp": []}, {"type":"BASICDTYPE","name":"VlRandomizer","addr":"(NB)","loc":"d,7:1,7:6","dtypep":"(NB)","keyword":"VlRandomizer","generic":true,"rangep": []} ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ {"type":"MODULE","name":"@CONST-POOL@","addr":"(SB)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], "stmtsp": [ {"type":"SCOPE","name":"@CONST-POOL@","addr":"(TB)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(SB)","varsp": [],"blocksp": [],"inlinesp": []} ]} ]} ]} verilator-5.042/test_regress/t/t_unroll_automatic_task_fork.v0000644000542200017500000000357715101701376025240 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Targets issue 6194 module t; logic clk; initial begin clk = 0; forever #(1) clk = ~clk; end task automatic task_example(int module_id, int channel); $display("task_example start: module %0d, channel %0d", module_id, channel); @(posedge clk); $display("task_example end: module %0d, channel %0d", module_id, channel); endtask initial begin : initial_block for (int m = 0; m < 2; m++) begin for (int i = 0; i < 2; i++) begin : forked_loop automatic int mod = m; automatic int ch = i; fork : forked_block task_example(mod, ch); join end end #10 $write("*-* Test 1 Finished *-*\n"); for (int m = 0; m < 2; m++) begin for (int i = 0; i < 2; i++) begin : forked_loop automatic int mod = m; automatic int ch = i; fork : forked_block task_example(mod, ch); join_any end end #10 $write("*-* Test 2 Finished *-*\n"); for (int m = 0; m < 2; m++) begin for (int i = 0; i < 2; i++) begin : forked_loop automatic int mod = m; automatic int ch = i; fork : forked_block task_example(mod, ch); $display("extra statement"); join_any end end #10 $write("*-* Test 3 Finished *-*\n"); for (int m = 0; m < 2; m++) begin for (int i = 0; i < 2; i++) begin : forked_loop automatic int mod = m; automatic int ch = i; fork : forked_block task_example(mod, ch); join_none end end #10 $write("*-* Test 4 Finished *-*\n"); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_notiming.out0000644000542200017500000000523415101701376021772 0ustar mahmoudyfreeshell%Warning-STMTDLY: t/t_notiming.v:12:8: Ignoring delay on this statement due to --no-timing : ... note: In instance 't' 12 | #1 | ^ ... For warning description see https://verilator.org/warn/STMTDLY?v=latest ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message. %Error-NOTIMING: t/t_notiming.v:13:8: Fork statements require --timing : ... note: In instance 't' 13 | fork @e; @e; join; | ^~~~ ... For error description see https://verilator.org/warn/NOTIMING?v=latest %Error-NOTIMING: t/t_notiming.v:14:8: Event control statement in this location requires --timing : ... note: In instance 't' : ... With --no-timing, suggest have one event control statement per procedure, at the top of the procedure 14 | @e | ^ %Error-NOTIMING: t/t_notiming.v:15:8: Wait statements require --timing : ... note: In instance 't' 15 | wait(x == 4) | ^~~~ %Error-NOTIMING: t/t_notiming.v:19:8: Event control statement in this location requires --timing : ... note: In instance 't' : ... With --no-timing, suggest have one event control statement per procedure, at the top of the procedure 19 | @e | ^ %Warning-STMTDLY: t/t_notiming.v:26:12: Ignoring delay on this statement due to --no-timing : ... note: In instance 't' 26 | initial #1 ->e; | ^ %Warning-STMTDLY: t/t_notiming.v:27:12: Ignoring delay on this statement due to --no-timing : ... note: In instance 't' 27 | initial #2 $stop; | ^ %Error-NOTIMING: t/t_notiming.v:33:10: mailbox::put() requires --timing : ... note: In instance 't' 33 | m.put(i); | ^~~ %Error-NOTIMING: t/t_notiming.v:34:10: mailbox::get() requires --timing : ... note: In instance 't' 34 | m.get(i); | ^~~ %Error-NOTIMING: t/t_notiming.v:35:10: mailbox::peek() requires --timing : ... note: In instance 't' 35 | m.peek(i); | ^~~~ %Error-NOTIMING: t/t_notiming.v:36:10: semaphore::get() requires --timing : ... note: In instance 't' 36 | s.get(); | ^~~ %Error: Exiting due to verilator-5.042/test_regress/t/.gitattributes0000644000542200017500000000002615101701376021757 0ustar mahmoudyfreeshellt_dos*.pl -crlf verilator-5.042/test_regress/t/t_inst_comma.v0000644000542200017500000000335015101701376021732 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2015 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; parameter ONE = 1; wire [17:10] bitout; reg [7:0] allbits; reg [15:0] onebit; sub #(1) sub0 (allbits, onebit[1:0], bitout[10]), sub1 (allbits, onebit[3:2], bitout[11]), sub2 (allbits, onebit[5:4], bitout[12]), sub3 (allbits, onebit[7:6], bitout[13]), sub4 (allbits, onebit[9:8], bitout[14]), sub5 (allbits, onebit[11:10], bitout[15]), sub6 (allbits, onebit[13:12], bitout[16]), sub7 (allbits, onebit[15:14], bitout[17]); integer x; always @ (posedge clk) begin //$write("%x\n", bitout); if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin allbits <= 8'hac; onebit <= 16'hc01a; end if (cyc==2) begin if (bitout !== 8'h07) $stop; allbits <= 8'hca; onebit <= 16'h1f01; end if (cyc==3) begin if (bitout !== 8'h41) $stop; if (sub0.bitout !== 1'b1) $stop; if (sub1.bitout !== 1'b0) $stop; $write("*-* All Finished *-*\n"); $finish; end end end endmodule `ifdef USE_INLINE `define INLINE_MODULE /*verilator inline_module*/ `else `define INLINE_MODULE /*verilator public_module*/ `endif module sub (input [7:0] allbits, input [1:0] onebit, output bitout); `INLINE_MODULE parameter integer P = 0; initial if (P != 1) $stop; assign bitout = (^ onebit) ^ (^ allbits); endmodule verilator-5.042/test_regress/t/t_specparam.v0000644000542200017500000000253315101701376021556 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; specify specparam tdevice_PU = 3e8; specparam Tdelay11 = 1.1; // verilator lint_off MINTYPMAXDLY specparam Tmintypmax = 1.0:1.1:1.2; specparam PATHPULSE$a$b = (3.0:3.1:3.2, 4.0:4.1:4.2); specparam PATHPULSE$a$c = (3.0:3.1:3.2); specparam randomize = 1; // Special parser corner-case endspecify // Support in other simulators is limited for module specparams specparam Tmod34 = 3.4, Tmod35 = 3.5; // IEEE 6.20.5 allowed in body // Support in other simulators is limited for ranged specparams specparam [5:2] Tranged = 4'b1011; localparam real PATHPULSE$normal$var = 6.78; reg PoweredUp; wire DelayIn, DelayOut; assign #tdevice_PU DelayOut = DelayIn; initial begin PoweredUp = 1'b0; #tdevice_PU PoweredUp = 1'b1; if (Tdelay11 != 1.1) $stop; `ifdef VERILATOR if (Tmintypmax != 1.1) $stop; if (PATHPULSE$a$b != 3.1) $stop; if (PATHPULSE$a$c != 3.1) $stop; `endif if (Tranged != 4'b1011) $stop; if (Tmod34 != 3.4) $stop; if (Tmod35 != 3.5) $stop; if (PATHPULSE$normal$var != 6.78) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_var_dup_bad.out0000644000542200017500000001133415101701376022412 0ustar mahmoudyfreeshell%Error: t/t_var_dup_bad.v:17:11: Duplicate declaration of signal: 'a' 17 | reg a; | ^ t/t_var_dup_bad.v:16:11: ... Location of original declaration 16 | reg a; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_var_dup_bad.v:20:12: Duplicate declaration of signal: 'l' 20 | integer l; | ^ t/t_var_dup_bad.v:19:12: ... Location of original declaration 19 | integer l; | ^ %Error: t/t_var_dup_bad.v:23:12: Duplicate declaration of signal: 'b' 23 | bit b; | ^ t/t_var_dup_bad.v:22:12: ... Location of original declaration 22 | bit b; | ^ %Error: t/t_var_dup_bad.v:26:11: Duplicate declaration of signal: 'o' 26 | output o; | ^ t/t_var_dup_bad.v:25:11: ... Location of original declaration 25 | output o; | ^ %Error: t/t_var_dup_bad.v:29:11: Duplicate declaration of signal: 'i' 29 | input i; | ^ t/t_var_dup_bad.v:28:11: ... Location of original declaration 28 | input i; | ^ %Error: t/t_var_dup_bad.v:32:11: Duplicate declaration of signal: 'oi' 32 | input oi; | ^~ t/t_var_dup_bad.v:31:11: ... Location of original declaration 31 | output oi; | ^~ %Error: t/t_var_dup_bad.v:36:11: Duplicate declaration of signal: 'og' 36 | reg og; | ^~ t/t_var_dup_bad.v:34:11: ... Location of original declaration 34 | output og; | ^~ %Error: t/t_var_dup_bad.v:39:15: Duplicate declaration of signal: 'org' 39 | output reg org; | ^~~ t/t_var_dup_bad.v:38:15: ... Location of original declaration 38 | output reg org; | ^~~ %Error: t/t_var_dup_bad.v:66:11: Duplicate declaration of signal: 'bad_reout_port' 66 | output bad_reout_port; | ^~~~~~~~~~~~~~ t/t_var_dup_bad.v:64:11: ... Location of original declaration 64 | output bad_reout_port | ^~~~~~~~~~~~~~ %Error: t/t_var_dup_bad.v:73:9: Duplicate declaration of signal: 'bad_rewire' 73 | wire bad_rewire; | ^~~~~~~~~~ t/t_var_dup_bad.v:70:16: ... Location of original declaration 70 | (output wire bad_rewire, | ^~~~~~~~~~ %Error: t/t_var_dup_bad.v:74:9: Duplicate declaration of signal: 'bad_rereg' 74 | reg bad_rereg; | ^~~~~~~~~ t/t_var_dup_bad.v:71:15: ... Location of original declaration 71 | output reg bad_rereg | ^~~~~~~~~ %Error: t/t_var_dup_bad.v:13:7: Duplicate declaration of port: 'oi' 13 | i, oi | ^~ t/t_var_dup_bad.v:31:11: ... Location of original declaration 31 | output oi; | ^~ %Error: t/t_var_dup_bad.v:50:4: Duplicate declaration of port: 'bad_duport' 50 | bad_duport | ^~~~~~~~~~ t/t_var_dup_bad.v:52:11: ... Location of original declaration 52 | output bad_duport; | ^~~~~~~~~~ %Error: t/t_var_dup_bad.v:58:11: Duplicate declaration of port: 'bad_mixport' 58 | output bad_mixport | ^~~~~~~~~~~ t/t_var_dup_bad.v:58:11: ... Location of original declaration 58 | output bad_mixport | ^~~~~~~~~~~ %Error: t/t_var_dup_bad.v:41:9: Can't find definition of variable: 'bad_duport' 41 | sub0 sub0(.*); | ^~~~ %Error: t/t_var_dup_bad.v:41:9: Duplicate pin connection: 'bad_duport' 41 | sub0 sub0(.*); | ^~~~ t/t_var_dup_bad.v:41:9: ... Location of original pin connection 41 | sub0 sub0(.*); | ^~~~ %Error: t/t_var_dup_bad.v:42:9: Can't find definition of variable: 'bad_mixport' : ... Suggested alternative: 'bad_duport' 42 | sub1 sub1(.*); | ^~~~ %Error: t/t_var_dup_bad.v:42:9: Duplicate pin connection: 'bad_mixport' 42 | sub1 sub1(.*); | ^~~~ t/t_var_dup_bad.v:42:9: ... Location of original pin connection 42 | sub1 sub1(.*); | ^~~~ %Error: t/t_var_dup_bad.v:43:9: Can't find definition of variable: 'bad_reout_port' : ... Suggested alternative: 'bad_duport' 43 | sub2 sub2(.*); | ^~~~ %Error: t/t_var_dup_bad.v:44:9: Can't find definition of variable: 'bad_rewire' 44 | sub3 sub3(.*); | ^~~~ %Error: t/t_var_dup_bad.v:44:9: Can't find definition of variable: 'bad_rereg' : ... Suggested alternative: 'bad_rewire' 44 | sub3 sub3(.*); | ^~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_var_top_struct.py0000755000542200017500000000071415101701376023046 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.passes() verilator-5.042/test_regress/t/t_class_method_bad.out0000644000542200017500000000061115101701376023413 0ustar mahmoudyfreeshell%Error: t/t_class_method_bad.v:18:9: Class method 'meth3' not found in class 'Cls2' : ... note: In instance 't' : ... Suggested alternative: 'meth2' 18 | c.meth3(); | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_array_non_blocking_loop.v0000644000542200017500000000204715101701376024474 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Demonstrate struct literal param assignment problem // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface intf #( parameter int WRITE_DATA_WIDTH) (); logic [WRITE_DATA_WIDTH-1:0] writedata; endinterface module t( /*AUTOARG*/ clk ); input clk; generate genvar num_chunks; for (num_chunks = 1; num_chunks <= 2; num_chunks++) begin : gen_n localparam int decoded_width = 55 * num_chunks; intf #( .WRITE_DATA_WIDTH(decoded_width)) the_intf (); always @(posedge clk) begin for (int i = 0; i < decoded_width; i++) the_intf.writedata[i] <= '1; $display("%0d", the_intf.writedata); end end endgenerate // finish report always @ (posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_math_pick.v0000644000542200017500000000471715101701376021550 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire pick1 = crc[0]; wire [13:0][1:0] data1 = crc[27+1:1]; wire [3:0][2:0][1:0] data2 = crc[23+29:29]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) logic [15:0] [1:0] datao; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .datao (datao/*[15:0][1:0]*/), // Inputs .pick1 (pick1), .data1 (data1/*[13:0][1:0]*/), .data2 (data2/*[2:0][3:0][1:0]*/)); // Aggregate outputs into a single result vector wire [63:0] result = {32'h0, datao}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h3ff4bf0e6407b281 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test ( input logic pick1, input logic [13:0] [1:0] data1, // 14 x 2 = 28 bits input logic [ 3:0] [2:0] [1:0] data2, // 4 x 3 x 2 = 24 bits output logic [15:0] [1:0] datao // 16 x 2 = 32 bits ); // verilator lint_off WIDTH always_comb datao[13: 0] // 28 bits = (pick1) ? {data1} // 28 bits : {'0, data2}; // 25-28 bits, perhaps not legal as '0 is unsized // verilator lint_on WIDTH always_comb datao[15:14] = '0; endmodule verilator-5.042/test_regress/t/t_timing_nba_2.v0000644000542200017500000000210115101701376022122 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t; logic clk1 = 0, clk2 = 0, clk3 = 0, clk4 = 0; always #2 clk1 = ~clk1; assign #1 clk2 = clk1; assign #1 clk3 = clk2; assign #1 clk4 = clk3; int x = 0; int cyc = 0; always @(posedge clk1) begin if (x != 0) $stop; `ifdef TEST_VERBOSE $display("[%0t] clk1 | x=%0d cyc=%0d", $realtime, x, cyc); `endif @(posedge clk2); `ifdef TEST_VERBOSE $display("[%0t] clk2 | x=%0d cyc=%0d", $realtime, x, cyc); `endif x <= x + 1; cyc <= cyc + 1; if (cyc == 10) begin $write("*-* All Finished *-*\n"); $finish; end end always @(posedge clk3) begin `ifdef TEST_VERBOSE $display("[%0t] clk3 | x=%0d cyc=%0d", $realtime, x, cyc); `endif @(posedge clk4); `ifdef TEST_VERBOSE $display("[%0t] clk4 | x=%0d cyc=%0d", $realtime, x, cyc); `endif x <= x - 1; end endmodule verilator-5.042/test_regress/t/t_savable_class_bad.v0000644000542200017500000000072715101701376023216 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls; int imembera; endclass : Cls module t; initial begin Cls c; if (c != null) $stop; c = new; c.imembera = 10; if (c.imembera != 10) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_case_enum_incomplete_wildcard_bad.out0000644000542200017500000000166715101701376027011 0ustar mahmoudyfreeshell%Warning-CASEINCOMPLETE: t/t_case_enum_incomplete_wildcard_bad.v:26:16: Enum item 'S10' not covered by case 26 | unique case (state) | ^~~~ ... For warning description see https://verilator.org/warn/CASEINCOMPLETE?v=latest ... Use "/* verilator lint_off CASEINCOMPLETE */" and lint_on around source to disable this message. %Warning-CASEINCOMPLETE: t/t_case_enum_incomplete_wildcard_bad.v:30:16: Enum item 'S00' not covered by case 30 | unique case (state) | ^~~~ %Warning-CASEINCOMPLETE: t/t_case_enum_incomplete_wildcard_bad.v:35:16: Enum item 'S10' not covered by case 35 | unique casez (state) | ^~~~~ %Warning-CASEINCOMPLETE: t/t_case_enum_incomplete_wildcard_bad.v:40:9: Case values incompletely covered (example pattern 0x3) 40 | case (state) | ^~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_interface1_modport.v0000644000542200017500000000212615101701376023366 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Very simple test for interface pathclearing interface ifc; integer hidden_from_isub; integer value; modport out_modport (output value); endinterface module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=1; ifc itop(); sub c1 (.isub(itop), .i_value(4)); always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==20) begin if (itop.value != 4) $stop; itop.hidden_from_isub = 20; if (itop.hidden_from_isub != 20) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module sub `ifdef NANSI // bug868 ( isub, i_value ); ifc.out_modport isub; // Note parenthesis are not legal here input integer i_value; `else ( ifc.out_modport isub, input integer i_value ); `endif always @* begin isub.value = i_value; end endmodule verilator-5.042/test_regress/t/t_select_2d.v0000644000542200017500000000405015101701376021443 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [4:0] cnt_i = (crc[4:0] <= 5'd17) ? crc[4:0] : 5'd0; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) logic [63:0] out_o; // From test of Test.v // End of automatics Test test(/*AUTOINST*/ // Outputs .out_o (out_o[63:0]), // Inputs .cnt_i (cnt_i[4:0])); // Aggregate outputs into a single result vector wire [63:0] result = out_o; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc == 0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc < 10) begin sum <= '0; end else if (cyc < 90) begin end else if (cyc == 99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h1f324087bbba0bfa if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (input logic [4:0] cnt_i, output logic [63:0] out_o); logic [17:0][63:0] data; initial begin for (int a = 0; a < 18; ++a) data[a] = {8{a[7:0]}}; end // verilator lint_off WIDTH assign out_o = data[5'd17 - cnt_i]; endmodule verilator-5.042/test_regress/t/t_hier_block_int.v0000644000542200017500000000215415101701376022555 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2025 by Antmicro. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t(/*AUTOARG*/ // inputs clk ); input clk; byte out1; shortint out2; int out3; longint out4; integer out5; time out6; sub sub(out1, out2, out3, out4, out5, out6); always_ff @(posedge clk) begin if (out1 == 1 && out2 == 2 && out3 == 3 && out4 == 4 && out5 == 5 && out6 == 6) begin $write("*-* All Finished *-*\n"); $finish; end else begin $write("Mismatch\n"); $stop; end end endmodule module sub( output byte out1, output shortint out2, output int out3, output longint out4, output integer out5, output time out6 ); /*verilator hier_block*/ assign out1 = 1; assign out2 = 2; assign out3 = 3; assign out4 = 4; assign out5 = 5; assign out6 = 6; endmodule verilator-5.042/test_regress/t/t_typedef_fwd_bad.out0000644000542200017500000000470315101701376023254 0ustar mahmoudyfreeshell%Error: t/t_typedef_fwd.v:18:5: Reference to 'enum_t' before declaration (IEEE 1800-2023 6.18) : ... Suggest move the declaration before the reference, or use a forward typedef 18 | enum_t m_e; | ^~~~~~ t/t_typedef_fwd.v:26:24: ... Location of original declaration 26 | typedef enum {N = 0} enum_t; | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_typedef_fwd.v:19:5: Reference to 'struct_t' before declaration (IEEE 1800-2023 6.18) : ... Suggest move the declaration before the reference, or use a forward typedef 19 | struct_t m_s; | ^~~~~~~~ t/t_typedef_fwd.v:28:34: ... Location of original declaration 28 | typedef struct packed {int s;} struct_t; | ^~~~~~~~ %Error: t/t_typedef_fwd.v:20:5: Reference to 'union_t' before declaration (IEEE 1800-2023 6.18) : ... Suggest move the declaration before the reference, or use a forward typedef 20 | union_t m_u; | ^~~~~~~ t/t_typedef_fwd.v:29:33: ... Location of original declaration 29 | typedef union packed {int s;} union_t; | ^~~~~~~ %Error: t/t_typedef_fwd.v:21:5: Reference to 'ClsB' before declaration (IEEE 1800-2023 6.18) : ... Suggest move the declaration before the reference, or use a forward typedef 21 | ClsB m_b; | ^~~~ t/t_typedef_fwd.v:31:3: ... Location of original declaration 31 | class ClsB; | ^~~~~ %Error: t/t_typedef_fwd.v:22:5: Reference to 'IfC' before declaration (IEEE 1800-2023 6.18) : ... Suggest move the declaration before the reference, or use a forward typedef 22 | IfC m_i; | ^~~ t/t_typedef_fwd.v:34:13: ... Location of original declaration 34 | interface class IfC; | ^~~~~ %Error: t/t_typedef_fwd.v:23:5: Reference to 'generic_t' before declaration (IEEE 1800-2023 6.18) : ... Suggest move the declaration before the reference, or use a forward typedef 23 | generic_t m_g; | ^~~~~~~~~ t/t_typedef_fwd.v:37:15: ... Location of original declaration 37 | typedef int generic_t; | ^~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_randomize_rand_mode_bad.v0000644000542200017500000000115715101701376024412 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Packet; int m_val; rand int m_other_val; rand logic [7:0] m_pack; function int get_rand_mode; return rand_mode(); endfunction endclass module t; Packet p; initial begin p = new; p.m_val.rand_mode(0); p.m_pack[0].rand_mode(0); $display("p.rand_mode()=%0d", p.rand_mode()); $display(p.rand_mode(0)); p.m_other_val.rand_mode(); end endmodule verilator-5.042/test_regress/t/t_unpacked_concat_bad3.v0000644000542200017500000000053515101701376023615 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Driss Hafdi. // SPDX-License-Identifier: CC0-1.0 module t; localparam logic [7:0] TOO_FEW [5] = '{0, 1, 2**8-1}; // Bad initial begin $display("%p", TOO_FEW); $stop; end endmodule verilator-5.042/test_regress/t/t_interface_generic_iface_param.v0000644000542200017500000000111515101701376025541 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 interface inf #(PARAM); logic[PARAM-1:0] v; endinterface module GenericModule (interface a); initial begin #1; if (a.v != 7) $stop; if (a.PARAM != 13) $stop; end endmodule module t; inf #(.PARAM(13)) inf_inst(); GenericModule genericModule (inf_inst); initial begin inf_inst.v = 7; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_dpi_var.cpp0000644000542200017500000001175515101701376021552 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include VM_PREFIX_INCLUDE #include "verilated.h" #include "verilated_syms.h" #include "svdpi.h" //====================================================================== struct MyMon { uint32_t* sigsp[2]; uint32_t addend = 0; MyMon() { sigsp[0] = NULL; sigsp[1] = NULL; } }; MyMon mons[4]; void mon_register_a(const char* namep, void* sigp, bool isOut, int n, int addend) { // Callback from initial block in monitor #ifdef TEST_VERBOSE VL_PRINTF("- mon_register_a(\"%s\", %p, %d, %d, %d);\n", namep, sigp, isOut, n, addend); #endif mons[n].sigsp[isOut] = (uint32_t*)sigp; mons[n].addend = addend; } void mon_do(MyMon* monp) { if (!monp->sigsp[0]) vl_fatal(__FILE__, __LINE__, "", "never registered"); if (!monp->sigsp[1]) vl_fatal(__FILE__, __LINE__, "", "never registered"); *monp->sigsp[1] = (*(monp->sigsp[0])) + monp->addend; #ifdef TEST_VERBOSE VL_PRINTF("- mon_do(%08x(&%p) -> %08x(&%p));\n", *(monp->sigsp[0]), monp->sigsp[0], *(monp->sigsp[1]), monp->sigsp[1]); #endif } void mon_class_name(const char* namep) { #ifdef TEST_VERBOSE VL_PRINTF("- mon_class_name(\"%s\");\n", namep); #endif // Check the C's calling name of "" doesn't lead to extra dots in the name() if (namep && namep[0] == '.') vl_fatal(__FILE__, __LINE__, "", ("Unexp class name "s + namep).c_str()); } extern "C" void mon_scope_name(const char* namep); void mon_scope_name(const char* namep) { const char* modp = svGetNameFromScope(svGetScope()); #ifdef TEST_VERBOSE VL_PRINTF("- mon_scope_name('%s', \"%s\");\n", modp, namep); #endif if (std::strcmp(namep, "t.sub")) vl_fatal(__FILE__, __LINE__, "", ("Unexp scope name "s + namep).c_str()); if (std::strcmp(modp, "t.sub")) vl_fatal(__FILE__, __LINE__, "", ("Unexp dpiscope name "s + modp).c_str()); } extern "C" void mon_register_b(const char* namep, int isOut, int n, int addend) { const char* modp = svGetNameFromScope(svGetScope()); #ifdef TEST_VERBOSE VL_PRINTF("- mon_register_b('%s', \"%s\", %d, %d %d);\n", modp, namep, isOut, n, addend); #endif // Use scope to get pointer and size of signal const VerilatedScope* scopep = Verilated::dpiScope(); const VerilatedVar* varp = scopep->varFind(namep); if (!varp) { VL_PRINTF("%%Warning: mon_register_b signal not found: \"%s\"\n", namep); } else if (varp->vltype() != VLVT_UINT32) { VL_PRINTF("%%Warning: wrong type for signal: \"%s\"\n", namep); } else { uint32_t* datap = (uint32_t*)(varp->datap()); VL_PRINTF("- mon_register_b('%s', \"%s\", %p, %d);\n", modp, namep, datap, isOut); mons[n].sigsp[isOut] = (uint32_t*)(varp->datap()); mons[n].addend = addend; } } extern "C" void mon_register_done(); void mon_register_done() { #ifdef TEST_VERBOSE const char* modp = svGetNameFromScope(svGetScope()); VL_PRINTF("- mon_register_done('%s');\n", modp); #endif // Print list of all signals - if we didn't register2 anything we'd pick them off here const VerilatedScope* scopep = Verilated::dpiScope(); if (VerilatedVarNameMap* varsp = scopep->varsp()) { for (VerilatedVarNameMap::const_iterator it = varsp->begin(); it != varsp->end(); ++it) { VL_PRINTF("- mon2: %s\n", it->first); } } } extern "C" void mon_eval(); void mon_eval() { // Callback from always@ negedge mon_do(&mons[0]); mon_do(&mons[1]); mon_do(&mons[2]); mon_do(&mons[3]); } //====================================================================== int main(int argc, char** argv) { const std::unique_ptr contextp{new VerilatedContext}; uint64_t sim_time = 1100; contextp->debug(0); contextp->commandArgs(argc, argv); const std::unique_ptr topp{new VM_PREFIX{contextp.get(), // Note null name - we're flattening it out ""}}; // clang-format off #ifdef VERILATOR # ifdef TEST_VERBOSE contextp->scopesDump(); # endif #endif // clang-format on topp->eval(); topp->clk = 0; contextp->timeInc(10); while (contextp->time() < sim_time && !contextp->gotFinish()) { contextp->timeInc(1); topp->eval(); topp->clk = !topp->clk; // mon_do(); } if (!contextp->gotFinish()) { vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); } topp->final(); return 0; } verilator-5.042/test_regress/t/t_wrapper_context.py0000755000542200017500000000223315101701376023212 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Multiple Model Test Module # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile( make_top_shell=False, make_main=False, # link threads library, add custom .cpp code, add tracing & coverage support verilator_flags2=["--exe", test.pli_filename, "--trace-vcd --coverage -cc"], threads=1, make_flags=['CPPFLAGS_ADD=-DVL_NO_LEGACY']) test.execute() test.files_identical_sorted(test.obj_dir + "/coverage_top0.dat", "t/t_wrapper_context__top0.dat.out") test.files_identical_sorted(test.obj_dir + "/coverage_top1.dat", "t/t_wrapper_context__top1.dat.out") test.vcd_identical(test.obj_dir + "/trace0.vcd", "t/t_wrapper_context__trace0.vcd.out") test.vcd_identical(test.obj_dir + "/trace1.vcd", "t/t_wrapper_context__trace1.vcd.out") test.passes() verilator-5.042/test_regress/t/t_repeat.py0000755000542200017500000000073415101701376021252 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_cover_sys_unsup.v0000644000542200017500000000265015101701376023051 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias' // // Simple bi-directional alias test. // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; real r; int i; initial begin // control_constant = `SV_COV_START, `SV_COV_STOP, `SV_COV_RESET, `SV_COV_CHECK // coverage_type = `SV_COV_ASSERTION, `SV_COV_FSM_STATE, `SV_COV_STATEMENT,`SV_COV_TOGGLE // scope_def = [`SV_COV_MODULE, "unique module def name"], [`SV_COV_HIER, "module name"], // [`SV_COV_MODULE, instance_name], [`SV_COV_HIER, instance_name] i = $coverage_control(`SV_COV_START, `SV_COV_TOGGLE, `SV_COV_MODULE, t); // returns `SV_COV_OK, `SV_COV_ERROR, `SV_COV_NOCOV, `SV_COV_PARTIAL i = $coverage_get(`SV_COV_TOGGLE, `SV_COV_MODULE, t); // returns number or `SC_COV_OVERFLOW, `SC_COV_ERROR, `SV_COV_NOCOV i = $coverage_get_max(`SV_COV_TOGGLE, `SV_COV_MODULE, t); // returns number or `SC_COV_OVERFLOW, `SC_COV_ERROR, `SV_COV_NOCOV r = $get_coverage(); $set_coverage_db_name("filename"); i = $coverage_save(coverage_type, "filename"); // returns `SV_COV_OK, `SC_COV_NOCOV, `SC_COV_ERROR $load_coverage_db("filename"); i = $coverage_merge(coverage_type, "filename"); // returns `SV_COV_OK, `SC_COV_NOCOV, `SC_COV_ERROR $finish; end endmodule verilator-5.042/test_regress/t/t_udp_binary.v0000644000542200017500000000056115101701376021736 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Test that a standalone primitive can be a top level module primitive p(output id_2, input id_1); table 1 : 0; 0 : 1; endtable endprimitive verilator-5.042/test_regress/t/t_wrapper_clone.out0000644000542200017500000000032615101701376023003 0ustar mahmoudyfreeshellcounter = 0 counter = 1 counter = 2 counter = 3 counter = 4 counter = 5 child: here we go counter = 6 counter = 7 counter = 8 parent: here we go counter = 6 counter = 7 counter = 8 *-* All Finished *-* verilator-5.042/test_regress/t/t_stream_type.py0000755000542200017500000000104715101701376022324 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') # Doesn't currently compile due to issue #6574 test.compile(verilator_make_gmake=False) # test.execute() test.passes() verilator-5.042/test_regress/t/t_hier_trace_noinl.py0000755000542200017500000000140415101701376023271 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_hier_trace.v" test.compile(verilator_flags2=[ '--trace-vcd', '-j 4', 't/t_hier_trace_sub/t_hier_trace.vlt', '--top-module t', '--hierarchical', '--fno-inline', '-F t/t_hier_trace_sub/top.F' ]) test.execute(all_run_flags=['-j 4']) test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_reloop_offset.v0000644000542200017500000000175715101701376022460 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 `define show(x) $display("oarray[%2d] is %2d", x, oarray[x]) module t; int iarray [63:0]; int oarray [63:0]; initial begin for (int i = 0; i < 64 ; i = i + 1) begin iarray[i] = i; oarray[i] = 0; end for (int i = 0; i < 63; i = i + 1) begin oarray[i] = iarray[i + 1]; end $display("shift down 1"); `show(63); `show(62); `show(61); `show(32); `show(2); `show(1); `show(0); for (int i = 63; i >= 2 ; i = i - 1) begin oarray[i] = iarray[i - 2]; end $display("shift up 2"); `show(63); `show(62); `show(61); `show(32); `show(2); `show(1); `show(0); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_lint_subout_bad.out0000644000542200017500000000152315101701376023320 0ustar mahmoudyfreeshell%Error-PORTSHORT: t/t_lint_subout_bad.v:12:14: Output port is connected to a constant pin, electrical short : ... note: In instance 't' 12 | sub sub1(.out({32'b0, sig})); | ^~~ ... For error description see https://verilator.org/warn/PORTSHORT?v=latest %Error-PORTSHORT: t/t_lint_subout_bad.v:13:14: Output port is connected to a constant pin, electrical short : ... note: In instance 't' 13 | sub sub2(.out({32'b1, sig})); | ^~~ %Error-PORTSHORT: t/t_lint_subout_bad.v:11:14: Output port is connected to a constant pin, electrical short : ... note: In instance 't' 11 | sub sub0(.out(33'b0)); | ^~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_a1_first_cc.v0000644000542200017500000000061715101701376021761 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; // Test loop always @ (posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_class_param_subtype2.py0000755000542200017500000000073415101701376024114 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_sys_readmem_assoc__c_b.mem.out0000644000542200017500000000005115101701376025355 0ustar mahmoudyfreeshell02 03 04 05 06 07 @8 10 @c 14 15 @12c 0a verilator-5.042/test_regress/t/t_inst_dtree_inlc.py0000755000542200017500000000107515101701376023136 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_inst_dtree.v" test.compile(v_flags2=['+define+INLINE_C'], verilator_flags2=['-trace']) test.execute() test.passes() verilator-5.042/test_regress/t/t_property_sexpr_unsup.v0000644000542200017500000000601315101701376024137 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 1; bit val = 0; Ieee ieee(); always @(posedge clk) begin if (cyc != 0) begin cyc <= cyc + 1; val = ~val; if (cyc == 10) begin $write("*-* All Finished *-*\n"); $finish; end end end `ifdef PARSING_TIME assert property (@(posedge clk) val ##1 val) $display("[%0t] var with single delay stmt, fileline:%d", $time, `__LINE__); assert property (@(posedge clk) ##1 val ##2 val) $display("[%0t] sequence stmt, fileline:%d", $time, `__LINE__); `else assert property (@(posedge clk) ##1 1 |-> 1) $display("[%0t] single delay with const implication stmt, fileline:%d", $time, `__LINE__); assert property (@(posedge clk) ##1 1 |-> not (val)) $display("[%0t] single delay implication with negated var stmt, fileline:%d", $time, `__LINE__); assert property (@(posedge clk) 1 |-> ##1 val) $display("[%0t] single delay implication with negated var stmt, fileline:%d", $time, `__LINE__); assert property (@(posedge clk) (##1 val) |-> (not val)) $display("[%0t] single delay with negated implication stmt, fileline:%d", $time, `__LINE__); assert property (@(posedge clk) ##1 (val) |-> not (val)) $display("[%0t] single delay with negated implication brackets stmt, fileline:%d", $time, `__LINE__); assert property (@(posedge clk) ((val) |-> not (val))) $display("[%0t] disable iff with negated implication stmt, fileline:%d", $time, `__LINE__); assert property (@(posedge clk) ##1 1 |-> 0) $display("[%0t] disable iff with cond implication stmt, fileline:%d", $time, `__LINE__); assert property (@(posedge clk) (##1 val) |-> (##1 val)) $display("[%0t] two delays implication stmt, fileline:%d", $time, `__LINE__); assert property (@(posedge clk) disable iff (cyc != 5) ##1 0) $display("[%0t] disable iff stmt, fileline:%d", $time, `__LINE__); assume property (@(posedge clk) disable iff (cyc != 5) ##1 0) $display("[%0t] disable iff stmt, fileline:%d", $time, `__LINE__); cover property (@(posedge clk) disable iff (cyc != 5) ##1 0) $display("[%0t] disable iff stmt, fileline:%d", $time, `__LINE__); `endif endmodule // Test parsing only module Ieee; // IEEE 1800-2023 16.6 bit a; integer b; byte q[$]; logic clk; `ifdef PARSING_TIME property p1; $rose(a) |-> q[0]; endproperty property p2; integer l_b; ($rose(a), l_b = b) |-> ##[3:10] q[l_b]; endproperty bit [2:0] count = 0; realtime t; always @(posedge clk) begin if (count == 0) t = $realtime; count++; end property p3; @(posedge clk) count == 7 |-> $realtime - t < 50.5; endproperty property p4; realtime l_t; @(posedge clk) (count == 0, l_t = $realtime) ##1 (count == 7)[->1] |-> $realtime - l_t < 50.5; endproperty // IEEE 1800-2023 16.12.3 assert property (@clk not a ##1 b); `endif endmodule verilator-5.042/test_regress/t/t_process_task.v0000644000542200017500000000127215101701376022302 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t(); std::process proc; logic clk = 0; logic b = 0; always #1 clk = ~clk; task kill_me_after_1ns(); fork #1 proc.kill(); #3 begin $write("*-* All Finished *-*\n"); $finish; end join_none endtask always @(posedge clk) begin if (!b) begin proc = std::process::self(); kill_me_after_1ns(); b = 1; end else begin $stop; end end endmodule verilator-5.042/test_regress/t/t_dist_attributes_bad.out0000644000542200017500000040262515101701376024172 0ustar mahmoudyfreeshell%Error: "TestClass::cm_ae_NO_ANNOTATION(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:204: [] TestClass::cm_ae_NO_ANNOTATION(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:146: [mt_safe, pure] TestClass::cm_ae_NO_ANNOTATION(VerilatedMutex &) %Error: "TestClass::cm_ae_VL_ACQUIRE(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:204: [acquire] TestClass::cm_ae_VL_ACQUIRE(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:146: [mt_safe, pure, acquire] TestClass::cm_ae_VL_ACQUIRE(VerilatedMutex &) %Error: "TestClass::cm_ae_VL_ACQUIRE_SHARED(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:204: [acquire] TestClass::cm_ae_VL_ACQUIRE_SHARED(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:146: [mt_safe, pure, acquire] TestClass::cm_ae_VL_ACQUIRE_SHARED(VerilatedMutex &) %Error: "TestClass::cm_ae_VL_EXCLUDES(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:204: [excludes] TestClass::cm_ae_VL_EXCLUDES(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:146: [mt_safe, pure, excludes] TestClass::cm_ae_VL_EXCLUDES(VerilatedMutex &) %Error: "TestClass::cm_ae_VL_MT_SAFE(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:204: [mt_safe] TestClass::cm_ae_VL_MT_SAFE(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:146: [mt_safe, pure] TestClass::cm_ae_VL_MT_SAFE(VerilatedMutex &) %Error: "TestClass::cm_ae_VL_MT_SAFE_EXCLUDES(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:204: [excludes] TestClass::cm_ae_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:146: [mt_safe, pure, excludes] TestClass::cm_ae_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) %Error: "TestClass::cm_ae_VL_MT_SAFE_POSTINIT(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:204: [mt_safe_postinit] TestClass::cm_ae_VL_MT_SAFE_POSTINIT(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:146: [mt_safe, mt_safe_postinit, pure] TestClass::cm_ae_VL_MT_SAFE_POSTINIT(VerilatedMutex &) %Error: "TestClass::cm_ae_VL_MT_START(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:204: [mt_start, requires] TestClass::cm_ae_VL_MT_START(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:146: [mt_start, mt_safe, pure, requires] TestClass::cm_ae_VL_MT_START(VerilatedMutex &) %Error: "TestClass::cm_ae_VL_MT_UNSAFE(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:204: [mt_unsafe] TestClass::cm_ae_VL_MT_UNSAFE(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:146: [mt_safe, mt_unsafe, pure] TestClass::cm_ae_VL_MT_UNSAFE(VerilatedMutex &) %Error: "TestClass::cm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:204: [mt_unsafe_one] TestClass::cm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:146: [mt_safe, mt_unsafe_one, pure] TestClass::cm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "TestClass::cm_ae_VL_PURE(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:204: [pure] TestClass::cm_ae_VL_PURE(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:146: [mt_safe, pure] TestClass::cm_ae_VL_PURE(VerilatedMutex &) %Error: "TestClass::cm_ae_VL_RELEASE(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:204: [release] TestClass::cm_ae_VL_RELEASE(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:146: [mt_safe, pure, release] TestClass::cm_ae_VL_RELEASE(VerilatedMutex &) %Error: "TestClass::cm_ae_VL_RELEASE_SHARED(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:204: [release] TestClass::cm_ae_VL_RELEASE_SHARED(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:146: [mt_safe, pure, release] TestClass::cm_ae_VL_RELEASE_SHARED(VerilatedMutex &) %Error: "TestClass::cm_ae_VL_REQUIRES(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:204: [requires] TestClass::cm_ae_VL_REQUIRES(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:146: [mt_safe, pure, requires] TestClass::cm_ae_VL_REQUIRES(VerilatedMutex &) %Error: "TestClass::cm_test_caller_smethod_VL_MT_SAFE(VerilatedMutex &)" is mtsafe but calls non-mtsafe function(s) t/t_dist_attributes/mt_enabled.cpp:155: [mt_safe] TestClass::cm_test_caller_smethod_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:191: [mt_unsafe] TestClass::cm_au_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:191: [mt_unsafe_one] TestClass::cm_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:199: [mt_unsafe] TestClass::cm_aa_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:199: [mt_unsafe_one] TestClass::cm_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:204: [mt_unsafe] TestClass::cm_ae_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:204: [mt_unsafe_one] TestClass::cm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:209: [mt_safe, mt_unsafe, pure] TestClass::cm_ea_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:209: [mt_safe, mt_unsafe_one, pure] TestClass::cm_ea_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "TestClass::cm_test_caller_smethod_VL_MT_START(VerilatedMutex &)" is stable_tree but calls non-stable_tree or non-mtsafe t/t_dist_attributes/mt_enabled.cpp:155: [mt_start, requires] TestClass::cm_test_caller_smethod_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:191: [mt_unsafe] TestClass::cm_au_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:191: [mt_unsafe_one] TestClass::cm_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:199: [mt_unsafe] TestClass::cm_aa_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:199: [mt_unsafe_one] TestClass::cm_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:204: [mt_unsafe] TestClass::cm_ae_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:204: [mt_unsafe_one] TestClass::cm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:209: [mt_safe, mt_unsafe, pure] TestClass::cm_ea_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:209: [mt_safe, mt_unsafe_one, pure] TestClass::cm_ea_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "TestClass::cm_test_caller_smethod_VL_PURE(VerilatedMutex &)" is pure but calls non-pure function(s) t/t_dist_attributes/mt_enabled.cpp:155: [pure] TestClass::cm_test_caller_smethod_VL_PURE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:191: [] TestClass::cm_au_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:191: [acquire] TestClass::cm_au_VL_ACQUIRE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:191: [acquire] TestClass::cm_au_VL_ACQUIRE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:191: [excludes] TestClass::cm_au_VL_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:191: [mt_safe] TestClass::cm_au_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:191: [excludes] TestClass::cm_au_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:191: [mt_safe_postinit] TestClass::cm_au_VL_MT_SAFE_POSTINIT(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:191: [mt_start, requires] TestClass::cm_au_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:191: [mt_unsafe] TestClass::cm_au_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:191: [mt_unsafe_one] TestClass::cm_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:191: [release] TestClass::cm_au_VL_RELEASE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:191: [release] TestClass::cm_au_VL_RELEASE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:191: [requires] TestClass::cm_au_VL_REQUIRES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_ACQUIRE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_PURE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_RELEASE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_RELEASE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_REQUIRES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:199: [] TestClass::cm_aa_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:199: [acquire] TestClass::cm_aa_VL_ACQUIRE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:199: [acquire] TestClass::cm_aa_VL_ACQUIRE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:199: [excludes] TestClass::cm_aa_VL_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:199: [mt_safe] TestClass::cm_aa_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:199: [excludes] TestClass::cm_aa_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:199: [mt_safe_postinit] TestClass::cm_aa_VL_MT_SAFE_POSTINIT(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:199: [mt_start, requires] TestClass::cm_aa_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:199: [mt_unsafe] TestClass::cm_aa_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:199: [mt_unsafe_one] TestClass::cm_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:199: [release] TestClass::cm_aa_VL_RELEASE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:199: [release] TestClass::cm_aa_VL_RELEASE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:199: [requires] TestClass::cm_aa_VL_REQUIRES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:204: [] TestClass::cm_ae_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:204: [acquire] TestClass::cm_ae_VL_ACQUIRE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:204: [acquire] TestClass::cm_ae_VL_ACQUIRE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:204: [excludes] TestClass::cm_ae_VL_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:204: [mt_safe] TestClass::cm_ae_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:204: [excludes] TestClass::cm_ae_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:204: [mt_safe_postinit] TestClass::cm_ae_VL_MT_SAFE_POSTINIT(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:204: [mt_start, requires] TestClass::cm_ae_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:204: [mt_unsafe] TestClass::cm_ae_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:204: [mt_unsafe_one] TestClass::cm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:204: [release] TestClass::cm_ae_VL_RELEASE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:204: [release] TestClass::cm_ae_VL_RELEASE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:204: [requires] TestClass::cm_ae_VL_REQUIRES(VerilatedMutex &) %Error: "TestClass::cm_test_caller_smethod_hdr_VL_MT_SAFE(VerilatedMutex &)" is mtsafe but calls non-mtsafe function(s) t/t_dist_attributes/mt_enabled.h:212: [mt_safe] TestClass::cm_test_caller_smethod_hdr_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:191: [mt_unsafe] TestClass::cm_au_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:191: [mt_unsafe_one] TestClass::cm_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:199: [mt_unsafe] TestClass::cm_aa_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:199: [mt_unsafe_one] TestClass::cm_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:204: [mt_unsafe] TestClass::cm_ae_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:204: [mt_unsafe_one] TestClass::cm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:209: [mt_safe, mt_unsafe, pure] TestClass::cm_ea_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:209: [mt_safe, mt_unsafe_one, pure] TestClass::cm_ea_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "TestClass::cm_test_caller_smethod_hdr_VL_MT_START(VerilatedMutex &)" is stable_tree but calls non-stable_tree or non-mtsafe t/t_dist_attributes/mt_enabled.h:212: [mt_start, requires] TestClass::cm_test_caller_smethod_hdr_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:191: [mt_unsafe] TestClass::cm_au_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:191: [mt_unsafe_one] TestClass::cm_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:199: [mt_unsafe] TestClass::cm_aa_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:199: [mt_unsafe_one] TestClass::cm_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:204: [mt_unsafe] TestClass::cm_ae_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:204: [mt_unsafe_one] TestClass::cm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:209: [mt_safe, mt_unsafe, pure] TestClass::cm_ea_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:209: [mt_safe, mt_unsafe_one, pure] TestClass::cm_ea_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "TestClass::cm_test_caller_smethod_hdr_VL_PURE(VerilatedMutex &)" is pure but calls non-pure function(s) t/t_dist_attributes/mt_enabled.h:212: [pure] TestClass::cm_test_caller_smethod_hdr_VL_PURE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:191: [] TestClass::cm_au_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:191: [acquire] TestClass::cm_au_VL_ACQUIRE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:191: [acquire] TestClass::cm_au_VL_ACQUIRE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:191: [excludes] TestClass::cm_au_VL_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:191: [mt_safe] TestClass::cm_au_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:191: [excludes] TestClass::cm_au_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:191: [mt_safe_postinit] TestClass::cm_au_VL_MT_SAFE_POSTINIT(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:191: [mt_start, requires] TestClass::cm_au_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:191: [mt_unsafe] TestClass::cm_au_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:191: [mt_unsafe_one] TestClass::cm_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:191: [release] TestClass::cm_au_VL_RELEASE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:191: [release] TestClass::cm_au_VL_RELEASE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:191: [requires] TestClass::cm_au_VL_REQUIRES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_ACQUIRE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_PURE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_RELEASE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_RELEASE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_REQUIRES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:199: [] TestClass::cm_aa_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:199: [acquire] TestClass::cm_aa_VL_ACQUIRE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:199: [acquire] TestClass::cm_aa_VL_ACQUIRE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:199: [excludes] TestClass::cm_aa_VL_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:199: [mt_safe] TestClass::cm_aa_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:199: [excludes] TestClass::cm_aa_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:199: [mt_safe_postinit] TestClass::cm_aa_VL_MT_SAFE_POSTINIT(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:199: [mt_start, requires] TestClass::cm_aa_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:199: [mt_unsafe] TestClass::cm_aa_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:199: [mt_unsafe_one] TestClass::cm_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:199: [release] TestClass::cm_aa_VL_RELEASE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:199: [release] TestClass::cm_aa_VL_RELEASE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:199: [requires] TestClass::cm_aa_VL_REQUIRES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:204: [] TestClass::cm_ae_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:204: [acquire] TestClass::cm_ae_VL_ACQUIRE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:204: [acquire] TestClass::cm_ae_VL_ACQUIRE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:204: [excludes] TestClass::cm_ae_VL_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:204: [mt_safe] TestClass::cm_ae_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:204: [excludes] TestClass::cm_ae_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:204: [mt_safe_postinit] TestClass::cm_ae_VL_MT_SAFE_POSTINIT(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:204: [mt_start, requires] TestClass::cm_ae_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:204: [mt_unsafe] TestClass::cm_ae_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:204: [mt_unsafe_one] TestClass::cm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:204: [release] TestClass::cm_ae_VL_RELEASE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:204: [release] TestClass::cm_ae_VL_RELEASE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:204: [requires] TestClass::cm_ae_VL_REQUIRES(VerilatedMutex &) %Error: "TestClass::cm_ua_VL_ACQUIRE(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_ACQUIRE(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:137: [acquire] TestClass::cm_ua_VL_ACQUIRE(VerilatedMutex &) %Error: "TestClass::cm_ua_VL_ACQUIRE_SHARED(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:137: [acquire] TestClass::cm_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) %Error: "TestClass::cm_ua_VL_EXCLUDES(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_EXCLUDES(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:137: [excludes] TestClass::cm_ua_VL_EXCLUDES(VerilatedMutex &) %Error: "TestClass::cm_ua_VL_MT_SAFE(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_SAFE(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:137: [mt_safe] TestClass::cm_ua_VL_MT_SAFE(VerilatedMutex &) %Error: "TestClass::cm_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:137: [excludes] TestClass::cm_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) %Error: "TestClass::cm_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:137: [mt_safe_postinit] TestClass::cm_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) %Error: "TestClass::cm_ua_VL_MT_START(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_START(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:137: [mt_start, requires] TestClass::cm_ua_VL_MT_START(VerilatedMutex &) %Error: "TestClass::cm_ua_VL_MT_UNSAFE(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_UNSAFE(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:137: [mt_unsafe] TestClass::cm_ua_VL_MT_UNSAFE(VerilatedMutex &) %Error: "TestClass::cm_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:137: [mt_unsafe_one] TestClass::cm_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "TestClass::cm_ua_VL_PURE(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_PURE(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:137: [pure] TestClass::cm_ua_VL_PURE(VerilatedMutex &) %Error: "TestClass::cm_ua_VL_RELEASE(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_RELEASE(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:137: [release] TestClass::cm_ua_VL_RELEASE(VerilatedMutex &) %Error: "TestClass::cm_ua_VL_RELEASE_SHARED(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_RELEASE_SHARED(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:137: [release] TestClass::cm_ua_VL_RELEASE_SHARED(VerilatedMutex &) %Error: "TestClass::cm_ua_VL_REQUIRES(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:195: [] TestClass::cm_ua_VL_REQUIRES(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:137: [requires] TestClass::cm_ua_VL_REQUIRES(VerilatedMutex &) %Error: "TestClass::guarded_by_test_fail()" is mtsafe but calls non-mtsafe function(s) t/t_dist_attributes/mt_enabled.h:269: [mt_safe] TestClass::guarded_by_test_fail() t/t_dist_attributes/mt_enabled.h:104: [] GuardMe::safe_if_guarded_or_local() t/t_dist_attributes/mt_enabled.h:106: [] GuardMe::operator int() t/t_dist_attributes/mt_enabled.h:108: [] GuardMe::operator+=(int) %Error: "TestClass::icm_test_caller_smethod_VL_MT_SAFE(VerilatedMutex &)" is mtsafe but calls non-mtsafe function(s) t/t_dist_attributes/mt_enabled.cpp:175: [mt_safe] TestClass::icm_test_caller_smethod_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:235: [mt_unsafe] TestClass::icm_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:235: [mt_unsafe_one] TestClass::icm_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "TestClass::icm_test_caller_smethod_VL_MT_START(VerilatedMutex &)" is stable_tree but calls non-stable_tree or non-mtsafe t/t_dist_attributes/mt_enabled.cpp:175: [mt_start, requires] TestClass::icm_test_caller_smethod_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:235: [mt_unsafe] TestClass::icm_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:235: [mt_unsafe_one] TestClass::icm_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "TestClass::icm_test_caller_smethod_VL_PURE(VerilatedMutex &)" is pure but calls non-pure function(s) t/t_dist_attributes/mt_enabled.cpp:175: [pure] TestClass::icm_test_caller_smethod_VL_PURE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:235: [] TestClass::icm_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:235: [acquire] TestClass::icm_VL_ACQUIRE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:235: [acquire] TestClass::icm_VL_ACQUIRE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:235: [excludes] TestClass::icm_VL_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:235: [mt_safe] TestClass::icm_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:235: [excludes] TestClass::icm_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:235: [mt_safe_postinit] TestClass::icm_VL_MT_SAFE_POSTINIT(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:235: [mt_start, requires] TestClass::icm_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:235: [mt_unsafe] TestClass::icm_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:235: [mt_unsafe_one] TestClass::icm_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:235: [release] TestClass::icm_VL_RELEASE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:235: [release] TestClass::icm_VL_RELEASE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:235: [requires] TestClass::icm_VL_REQUIRES(VerilatedMutex &) %Error: "TestClass::icm_test_caller_smethod_hdr_VL_MT_SAFE(VerilatedMutex &)" is mtsafe but calls non-mtsafe function(s) t/t_dist_attributes/mt_enabled.h:238: [mt_safe] TestClass::icm_test_caller_smethod_hdr_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:235: [mt_unsafe] TestClass::icm_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:235: [mt_unsafe_one] TestClass::icm_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "TestClass::icm_test_caller_smethod_hdr_VL_MT_START(VerilatedMutex &)" is stable_tree but calls non-stable_tree or non-mtsafe t/t_dist_attributes/mt_enabled.h:238: [mt_start, requires] TestClass::icm_test_caller_smethod_hdr_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:235: [mt_unsafe] TestClass::icm_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:235: [mt_unsafe_one] TestClass::icm_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "TestClass::icm_test_caller_smethod_hdr_VL_PURE(VerilatedMutex &)" is pure but calls non-pure function(s) t/t_dist_attributes/mt_enabled.h:238: [pure] TestClass::icm_test_caller_smethod_hdr_VL_PURE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:235: [] TestClass::icm_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:235: [acquire] TestClass::icm_VL_ACQUIRE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:235: [acquire] TestClass::icm_VL_ACQUIRE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:235: [excludes] TestClass::icm_VL_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:235: [mt_safe] TestClass::icm_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:235: [excludes] TestClass::icm_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:235: [mt_safe_postinit] TestClass::icm_VL_MT_SAFE_POSTINIT(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:235: [mt_start, requires] TestClass::icm_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:235: [mt_unsafe] TestClass::icm_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:235: [mt_unsafe_one] TestClass::icm_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:235: [release] TestClass::icm_VL_RELEASE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:235: [release] TestClass::icm_VL_RELEASE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:235: [requires] TestClass::icm_VL_REQUIRES(VerilatedMutex &) %Error: "TestClass::iscm_test_caller_smethod_VL_MT_SAFE(VerilatedMutex &)" is mtsafe but calls non-mtsafe function(s) t/t_dist_attributes/mt_enabled.cpp:119: [mt_safe] TestClass::iscm_test_caller_smethod_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:170: [] TestClass::iscm_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:170: [mt_unsafe] TestClass::iscm_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:170: [mt_unsafe_one] TestClass::iscm_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "TestClass::iscm_test_caller_smethod_VL_MT_START(VerilatedMutex &)" is stable_tree but calls non-stable_tree or non-mtsafe t/t_dist_attributes/mt_enabled.cpp:119: [mt_start, requires] TestClass::iscm_test_caller_smethod_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:170: [] TestClass::iscm_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:170: [mt_unsafe] TestClass::iscm_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:170: [mt_unsafe_one] TestClass::iscm_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "TestClass::iscm_test_caller_smethod_VL_PURE(VerilatedMutex &)" is pure but calls non-pure function(s) t/t_dist_attributes/mt_enabled.cpp:119: [pure] TestClass::iscm_test_caller_smethod_VL_PURE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:170: [] TestClass::iscm_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:170: [acquire] TestClass::iscm_VL_ACQUIRE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:170: [acquire] TestClass::iscm_VL_ACQUIRE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:170: [excludes] TestClass::iscm_VL_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:170: [mt_safe] TestClass::iscm_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:170: [excludes] TestClass::iscm_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:170: [mt_safe_postinit] TestClass::iscm_VL_MT_SAFE_POSTINIT(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:170: [mt_start, requires] TestClass::iscm_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:170: [mt_unsafe] TestClass::iscm_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:170: [mt_unsafe_one] TestClass::iscm_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:170: [release] TestClass::iscm_VL_RELEASE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:170: [release] TestClass::iscm_VL_RELEASE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:170: [requires] TestClass::iscm_VL_REQUIRES(VerilatedMutex &) %Error: "TestClass::iscm_test_caller_smethod_hdr_VL_MT_SAFE(VerilatedMutex &)" is mtsafe but calls non-mtsafe function(s) t/t_dist_attributes/mt_enabled.h:173: [mt_safe] TestClass::iscm_test_caller_smethod_hdr_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:170: [] TestClass::iscm_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:170: [mt_unsafe] TestClass::iscm_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:170: [mt_unsafe_one] TestClass::iscm_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "TestClass::iscm_test_caller_smethod_hdr_VL_MT_START(VerilatedMutex &)" is stable_tree but calls non-stable_tree or non-mtsafe t/t_dist_attributes/mt_enabled.h:173: [mt_start, requires] TestClass::iscm_test_caller_smethod_hdr_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:170: [] TestClass::iscm_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:170: [mt_unsafe] TestClass::iscm_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:170: [mt_unsafe_one] TestClass::iscm_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "TestClass::iscm_test_caller_smethod_hdr_VL_PURE(VerilatedMutex &)" is pure but calls non-pure function(s) t/t_dist_attributes/mt_enabled.h:173: [pure] TestClass::iscm_test_caller_smethod_hdr_VL_PURE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:170: [] TestClass::iscm_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:170: [acquire] TestClass::iscm_VL_ACQUIRE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:170: [acquire] TestClass::iscm_VL_ACQUIRE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:170: [excludes] TestClass::iscm_VL_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:170: [mt_safe] TestClass::iscm_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:170: [excludes] TestClass::iscm_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:170: [mt_safe_postinit] TestClass::iscm_VL_MT_SAFE_POSTINIT(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:170: [mt_start, requires] TestClass::iscm_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:170: [mt_unsafe] TestClass::iscm_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:170: [mt_unsafe_one] TestClass::iscm_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:170: [release] TestClass::iscm_VL_RELEASE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:170: [release] TestClass::iscm_VL_RELEASE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:170: [requires] TestClass::iscm_VL_REQUIRES(VerilatedMutex &) %Error: "TestClass::scm_ae_NO_ANNOTATION(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:133: [] TestClass::scm_ae_NO_ANNOTATION(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:84: [mt_safe, pure] TestClass::scm_ae_NO_ANNOTATION(VerilatedMutex &) %Error: "TestClass::scm_ae_VL_ACQUIRE(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:133: [acquire] TestClass::scm_ae_VL_ACQUIRE(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:84: [mt_safe, pure, acquire] TestClass::scm_ae_VL_ACQUIRE(VerilatedMutex &) %Error: "TestClass::scm_ae_VL_ACQUIRE_SHARED(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:133: [acquire] TestClass::scm_ae_VL_ACQUIRE_SHARED(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:84: [mt_safe, pure, acquire] TestClass::scm_ae_VL_ACQUIRE_SHARED(VerilatedMutex &) %Error: "TestClass::scm_ae_VL_EXCLUDES(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:133: [excludes] TestClass::scm_ae_VL_EXCLUDES(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:84: [mt_safe, pure, excludes] TestClass::scm_ae_VL_EXCLUDES(VerilatedMutex &) %Error: "TestClass::scm_ae_VL_MT_SAFE(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:133: [mt_safe] TestClass::scm_ae_VL_MT_SAFE(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:84: [mt_safe, pure] TestClass::scm_ae_VL_MT_SAFE(VerilatedMutex &) %Error: "TestClass::scm_ae_VL_MT_SAFE_EXCLUDES(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:133: [excludes] TestClass::scm_ae_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:84: [mt_safe, pure, excludes] TestClass::scm_ae_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) %Error: "TestClass::scm_ae_VL_MT_SAFE_POSTINIT(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:133: [mt_safe_postinit] TestClass::scm_ae_VL_MT_SAFE_POSTINIT(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:84: [mt_safe, mt_safe_postinit, pure] TestClass::scm_ae_VL_MT_SAFE_POSTINIT(VerilatedMutex &) %Error: "TestClass::scm_ae_VL_MT_START(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:133: [mt_start, requires] TestClass::scm_ae_VL_MT_START(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:84: [mt_start, mt_safe, pure, requires] TestClass::scm_ae_VL_MT_START(VerilatedMutex &) %Error: "TestClass::scm_ae_VL_MT_UNSAFE(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:133: [mt_unsafe] TestClass::scm_ae_VL_MT_UNSAFE(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:84: [mt_safe, mt_unsafe, pure] TestClass::scm_ae_VL_MT_UNSAFE(VerilatedMutex &) %Error: "TestClass::scm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:133: [mt_unsafe_one] TestClass::scm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:84: [mt_safe, mt_unsafe_one, pure] TestClass::scm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "TestClass::scm_ae_VL_PURE(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:133: [pure] TestClass::scm_ae_VL_PURE(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:84: [mt_safe, pure] TestClass::scm_ae_VL_PURE(VerilatedMutex &) %Error: "TestClass::scm_ae_VL_RELEASE(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:133: [release] TestClass::scm_ae_VL_RELEASE(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:84: [mt_safe, pure, release] TestClass::scm_ae_VL_RELEASE(VerilatedMutex &) %Error: "TestClass::scm_ae_VL_RELEASE_SHARED(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:133: [release] TestClass::scm_ae_VL_RELEASE_SHARED(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:84: [mt_safe, pure, release] TestClass::scm_ae_VL_RELEASE_SHARED(VerilatedMutex &) %Error: "TestClass::scm_ae_VL_REQUIRES(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:133: [requires] TestClass::scm_ae_VL_REQUIRES(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:84: [mt_safe, pure, requires] TestClass::scm_ae_VL_REQUIRES(VerilatedMutex &) %Error: "TestClass::scm_test_caller_smethod_VL_MT_SAFE(VerilatedMutex &)" is mtsafe but calls non-mtsafe function(s) t/t_dist_attributes/mt_enabled.cpp:93: [mt_safe] TestClass::scm_test_caller_smethod_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:120: [] TestClass::scm_au_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:120: [mt_unsafe] TestClass::scm_au_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:120: [mt_unsafe_one] TestClass::scm_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_ACQUIRE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_PURE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_RELEASE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_RELEASE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_REQUIRES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:128: [] TestClass::scm_aa_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:128: [mt_unsafe] TestClass::scm_aa_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:128: [mt_unsafe_one] TestClass::scm_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:133: [] TestClass::scm_ae_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:133: [mt_unsafe] TestClass::scm_ae_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:133: [mt_unsafe_one] TestClass::scm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:138: [mt_safe, mt_unsafe, pure] TestClass::scm_ea_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:138: [mt_safe, mt_unsafe_one, pure] TestClass::scm_ea_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "TestClass::scm_test_caller_smethod_VL_MT_START(VerilatedMutex &)" is stable_tree but calls non-stable_tree or non-mtsafe t/t_dist_attributes/mt_enabled.cpp:93: [mt_start, requires] TestClass::scm_test_caller_smethod_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:120: [] TestClass::scm_au_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:120: [mt_unsafe] TestClass::scm_au_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:120: [mt_unsafe_one] TestClass::scm_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_ACQUIRE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_PURE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_RELEASE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_RELEASE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_REQUIRES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:128: [] TestClass::scm_aa_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:128: [mt_unsafe] TestClass::scm_aa_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:128: [mt_unsafe_one] TestClass::scm_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:133: [] TestClass::scm_ae_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:133: [mt_unsafe] TestClass::scm_ae_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:133: [mt_unsafe_one] TestClass::scm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:138: [mt_safe, mt_unsafe, pure] TestClass::scm_ea_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:138: [mt_safe, mt_unsafe_one, pure] TestClass::scm_ea_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "TestClass::scm_test_caller_smethod_VL_PURE(VerilatedMutex &)" is pure but calls non-pure function(s) t/t_dist_attributes/mt_enabled.cpp:93: [pure] TestClass::scm_test_caller_smethod_VL_PURE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:120: [] TestClass::scm_au_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:120: [acquire] TestClass::scm_au_VL_ACQUIRE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:120: [acquire] TestClass::scm_au_VL_ACQUIRE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:120: [excludes] TestClass::scm_au_VL_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:120: [mt_safe] TestClass::scm_au_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:120: [excludes] TestClass::scm_au_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:120: [mt_safe_postinit] TestClass::scm_au_VL_MT_SAFE_POSTINIT(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:120: [mt_start, requires] TestClass::scm_au_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:120: [mt_unsafe] TestClass::scm_au_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:120: [mt_unsafe_one] TestClass::scm_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:120: [release] TestClass::scm_au_VL_RELEASE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:120: [release] TestClass::scm_au_VL_RELEASE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:120: [requires] TestClass::scm_au_VL_REQUIRES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_ACQUIRE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_PURE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_RELEASE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_RELEASE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_REQUIRES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:128: [] TestClass::scm_aa_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:128: [acquire] TestClass::scm_aa_VL_ACQUIRE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:128: [acquire] TestClass::scm_aa_VL_ACQUIRE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:128: [excludes] TestClass::scm_aa_VL_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:128: [mt_safe] TestClass::scm_aa_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:128: [excludes] TestClass::scm_aa_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:128: [mt_safe_postinit] TestClass::scm_aa_VL_MT_SAFE_POSTINIT(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:128: [mt_start, requires] TestClass::scm_aa_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:128: [mt_unsafe] TestClass::scm_aa_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:128: [mt_unsafe_one] TestClass::scm_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:128: [release] TestClass::scm_aa_VL_RELEASE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:128: [release] TestClass::scm_aa_VL_RELEASE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:128: [requires] TestClass::scm_aa_VL_REQUIRES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:133: [] TestClass::scm_ae_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:133: [acquire] TestClass::scm_ae_VL_ACQUIRE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:133: [acquire] TestClass::scm_ae_VL_ACQUIRE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:133: [excludes] TestClass::scm_ae_VL_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:133: [mt_safe] TestClass::scm_ae_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:133: [excludes] TestClass::scm_ae_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:133: [mt_safe_postinit] TestClass::scm_ae_VL_MT_SAFE_POSTINIT(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:133: [mt_start, requires] TestClass::scm_ae_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:133: [mt_unsafe] TestClass::scm_ae_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:133: [mt_unsafe_one] TestClass::scm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:133: [release] TestClass::scm_ae_VL_RELEASE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:133: [release] TestClass::scm_ae_VL_RELEASE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:133: [requires] TestClass::scm_ae_VL_REQUIRES(VerilatedMutex &) %Error: "TestClass::scm_test_caller_smethod_hdr_VL_MT_SAFE(VerilatedMutex &)" is mtsafe but calls non-mtsafe function(s) t/t_dist_attributes/mt_enabled.h:141: [mt_safe] TestClass::scm_test_caller_smethod_hdr_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:120: [] TestClass::scm_au_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:120: [mt_unsafe] TestClass::scm_au_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:120: [mt_unsafe_one] TestClass::scm_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_ACQUIRE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_PURE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_RELEASE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_RELEASE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_REQUIRES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:128: [] TestClass::scm_aa_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:128: [mt_unsafe] TestClass::scm_aa_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:128: [mt_unsafe_one] TestClass::scm_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:133: [] TestClass::scm_ae_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:133: [mt_unsafe] TestClass::scm_ae_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:133: [mt_unsafe_one] TestClass::scm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:138: [mt_safe, mt_unsafe, pure] TestClass::scm_ea_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:138: [mt_safe, mt_unsafe_one, pure] TestClass::scm_ea_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "TestClass::scm_test_caller_smethod_hdr_VL_MT_START(VerilatedMutex &)" is stable_tree but calls non-stable_tree or non-mtsafe t/t_dist_attributes/mt_enabled.h:141: [mt_start, requires] TestClass::scm_test_caller_smethod_hdr_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:120: [] TestClass::scm_au_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:120: [mt_unsafe] TestClass::scm_au_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:120: [mt_unsafe_one] TestClass::scm_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_ACQUIRE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_PURE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_RELEASE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_RELEASE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_REQUIRES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:128: [] TestClass::scm_aa_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:128: [mt_unsafe] TestClass::scm_aa_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:128: [mt_unsafe_one] TestClass::scm_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:133: [] TestClass::scm_ae_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:133: [mt_unsafe] TestClass::scm_ae_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:133: [mt_unsafe_one] TestClass::scm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:138: [mt_safe, mt_unsafe, pure] TestClass::scm_ea_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:138: [mt_safe, mt_unsafe_one, pure] TestClass::scm_ea_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "TestClass::scm_test_caller_smethod_hdr_VL_PURE(VerilatedMutex &)" is pure but calls non-pure function(s) t/t_dist_attributes/mt_enabled.h:141: [pure] TestClass::scm_test_caller_smethod_hdr_VL_PURE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:120: [] TestClass::scm_au_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:120: [acquire] TestClass::scm_au_VL_ACQUIRE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:120: [acquire] TestClass::scm_au_VL_ACQUIRE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:120: [excludes] TestClass::scm_au_VL_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:120: [mt_safe] TestClass::scm_au_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:120: [excludes] TestClass::scm_au_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:120: [mt_safe_postinit] TestClass::scm_au_VL_MT_SAFE_POSTINIT(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:120: [mt_start, requires] TestClass::scm_au_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:120: [mt_unsafe] TestClass::scm_au_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:120: [mt_unsafe_one] TestClass::scm_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:120: [release] TestClass::scm_au_VL_RELEASE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:120: [release] TestClass::scm_au_VL_RELEASE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:120: [requires] TestClass::scm_au_VL_REQUIRES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_ACQUIRE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_PURE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_RELEASE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_RELEASE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_REQUIRES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:128: [] TestClass::scm_aa_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:128: [acquire] TestClass::scm_aa_VL_ACQUIRE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:128: [acquire] TestClass::scm_aa_VL_ACQUIRE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:128: [excludes] TestClass::scm_aa_VL_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:128: [mt_safe] TestClass::scm_aa_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:128: [excludes] TestClass::scm_aa_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:128: [mt_safe_postinit] TestClass::scm_aa_VL_MT_SAFE_POSTINIT(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:128: [mt_start, requires] TestClass::scm_aa_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:128: [mt_unsafe] TestClass::scm_aa_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:128: [mt_unsafe_one] TestClass::scm_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:128: [release] TestClass::scm_aa_VL_RELEASE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:128: [release] TestClass::scm_aa_VL_RELEASE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:128: [requires] TestClass::scm_aa_VL_REQUIRES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:133: [] TestClass::scm_ae_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:133: [acquire] TestClass::scm_ae_VL_ACQUIRE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:133: [acquire] TestClass::scm_ae_VL_ACQUIRE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:133: [excludes] TestClass::scm_ae_VL_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:133: [mt_safe] TestClass::scm_ae_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:133: [excludes] TestClass::scm_ae_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:133: [mt_safe_postinit] TestClass::scm_ae_VL_MT_SAFE_POSTINIT(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:133: [mt_start, requires] TestClass::scm_ae_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:133: [mt_unsafe] TestClass::scm_ae_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:133: [mt_unsafe_one] TestClass::scm_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:133: [release] TestClass::scm_ae_VL_RELEASE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:133: [release] TestClass::scm_ae_VL_RELEASE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:133: [requires] TestClass::scm_ae_VL_REQUIRES(VerilatedMutex &) %Error: "TestClass::scm_ua_VL_ACQUIRE(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_ACQUIRE(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:75: [acquire] TestClass::scm_ua_VL_ACQUIRE(VerilatedMutex &) %Error: "TestClass::scm_ua_VL_ACQUIRE_SHARED(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:75: [acquire] TestClass::scm_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) %Error: "TestClass::scm_ua_VL_EXCLUDES(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_EXCLUDES(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:75: [excludes] TestClass::scm_ua_VL_EXCLUDES(VerilatedMutex &) %Error: "TestClass::scm_ua_VL_MT_SAFE(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:75: [mt_safe] TestClass::scm_ua_VL_MT_SAFE(VerilatedMutex &) %Error: "TestClass::scm_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:75: [excludes] TestClass::scm_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) %Error: "TestClass::scm_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:75: [mt_safe_postinit] TestClass::scm_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) %Error: "TestClass::scm_ua_VL_MT_START(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_START(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:75: [mt_start, requires] TestClass::scm_ua_VL_MT_START(VerilatedMutex &) %Error: "TestClass::scm_ua_VL_MT_UNSAFE(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_UNSAFE(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:75: [mt_unsafe] TestClass::scm_ua_VL_MT_UNSAFE(VerilatedMutex &) %Error: "TestClass::scm_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:75: [mt_unsafe_one] TestClass::scm_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "TestClass::scm_ua_VL_PURE(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_PURE(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:75: [pure] TestClass::scm_ua_VL_PURE(VerilatedMutex &) %Error: "TestClass::scm_ua_VL_RELEASE(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_RELEASE(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:75: [release] TestClass::scm_ua_VL_RELEASE(VerilatedMutex &) %Error: "TestClass::scm_ua_VL_RELEASE_SHARED(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_RELEASE_SHARED(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:75: [release] TestClass::scm_ua_VL_RELEASE_SHARED(VerilatedMutex &) %Error: "TestClass::scm_ua_VL_REQUIRES(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:124: [] TestClass::scm_ua_VL_REQUIRES(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:75: [requires] TestClass::scm_ua_VL_REQUIRES(VerilatedMutex &) %Error: "TestClassConstructor::safe_function_calls_constructor_global_object_bad()" is stable_tree but calls non-stable_tree or non-mtsafe t/t_dist_attributes/mt_enabled.h:426: [stable_tree] TestClassConstructor::safe_function_calls_constructor_global_object_bad() t/t_dist_attributes/mt_enabled.h:355: [] DummyClass::dummy_function() %Error: "TestClassConstructor::safe_function_calls_constructor_global_object_member_bad()" is stable_tree but calls non-stable_tree or non-mtsafe t/t_dist_attributes/mt_enabled.h:429: [stable_tree] TestClassConstructor::safe_function_calls_constructor_global_object_member_bad() t/t_dist_attributes/mt_enabled.h:350: [] DummyClass2::dummy_function2() %Error: "TestClassConstructor::safe_function_calls_constructor_local_calls_class_global_bad()" is mtsafe but calls non-mtsafe function(s) t/t_dist_attributes/mt_enabled.h:423: [mt_safe] TestClassConstructor::safe_function_calls_constructor_local_calls_class_global_bad() t/t_dist_attributes/mt_enabled.h:280: [] StaticClass::static_class_function() %Error: "TestClassConstructor::safe_function_calls_constructor_local_calls_global_bad()" is mtsafe but calls non-mtsafe function(s) t/t_dist_attributes/mt_enabled.h:420: [mt_safe] TestClassConstructor::safe_function_calls_constructor_local_calls_global_bad() t/t_dist_attributes/mt_enabled.h:276: [] static_function() %Error: "TestClassConstructor::safe_function_calls_constructor_with_unsafepointer_bad()" is mtsafe but calls non-mtsafe function(s) t/t_dist_attributes/mt_enabled.h:412: [mt_safe] TestClassConstructor::safe_function_calls_constructor_with_unsafepointer_bad() t/t_dist_attributes/mt_enabled.h:311: [mt_unsafe] UnsafeFunction::unsafe_function() %Error: "TestClassConstructor::safe_function_calls_constructor_with_unsafereference_bad()" is mtsafe but calls non-mtsafe function(s) t/t_dist_attributes/mt_enabled.h:416: [mt_safe] TestClassConstructor::safe_function_calls_constructor_with_unsafereference_bad() t/t_dist_attributes/mt_enabled.h:311: [mt_unsafe] UnsafeFunction::unsafe_function() %Error: "TestClassConstructor::safe_function_local_function_global_bad()" is mtsafe but calls non-mtsafe function(s) t/t_dist_attributes/mt_enabled.h:398: [mt_safe] TestClassConstructor::safe_function_local_function_global_bad() t/t_dist_attributes/mt_enabled.h:276: [] static_function() %Error: "TestClassConstructor::safe_function_static_constructor_bad()" is mtsafe but calls non-mtsafe function(s) t/t_dist_attributes/mt_enabled.h:395: [mt_safe] TestClassConstructor::safe_function_static_constructor_bad() t/t_dist_attributes/mt_enabled.h:276: [] static_function() %Error: "TestClassConstructor::safe_function_unsafe_constructor_bad()" is mtsafe but calls non-mtsafe function(s) t/t_dist_attributes/mt_enabled.h:392: [mt_safe] TestClassConstructor::safe_function_unsafe_constructor_bad() t/t_dist_attributes/mt_enabled.h:285: [mt_unsafe] ConstructorCallsUnsafeLocalFunction::unsafe_function() %Error: "UnannotatedMtDisabledClass::unannotatedMtDisabledMethodBad()" defined in a file marked as VL_MT_DISABLED_CODE_UNIT has declaration(s) without VL_MT_DISABLED annotation t/t_dist_attributes/mt_disabled.h:27: [mt_disabled, excludes] UnannotatedMtDisabledClass::unannotatedMtDisabledMethodBad() [declaration] t/t_dist_attributes/mt_disabled.cpp:23: [] UnannotatedMtDisabledClass::unannotatedMtDisabledMethodBad() t/t_dist_attributes/mt_disabled.h:27: [] UnannotatedMtDisabledClass::unannotatedMtDisabledMethodBad() %Error: "UnannotatedMtDisabledClass::unannotatedMtDisabledStaticMethodBad()" defined in a file marked as VL_MT_DISABLED_CODE_UNIT has declaration(s) without VL_MT_DISABLED annotation t/t_dist_attributes/mt_disabled.h:28: [mt_disabled, excludes] UnannotatedMtDisabledClass::unannotatedMtDisabledStaticMethodBad() [declaration] t/t_dist_attributes/mt_disabled.cpp:26: [] UnannotatedMtDisabledClass::unannotatedMtDisabledStaticMethodBad() t/t_dist_attributes/mt_disabled.h:28: [] UnannotatedMtDisabledClass::unannotatedMtDisabledStaticMethodBad() %Error: "VirtualInheritance::Base1::func(int, int)" is pure but calls non-pure function(s) t/t_dist_attributes/mt_enabled.h:382: [pure] VirtualInheritance::Base1::func(int, int) t/t_dist_attributes/mt_enabled.h:384: [] VirtualInheritance::Derived::notPure() %Error: "VirtualInheritance::Base2::func()" is pure but calls non-pure function(s) t/t_dist_attributes/mt_enabled.h:383: [pure] VirtualInheritance::Base2::func() t/t_dist_attributes/mt_enabled.h:384: [] VirtualInheritance::Derived::notPure() %Error: "ifh_test_caller_func_VL_MT_SAFE(VerilatedMutex &)" is mtsafe but calls non-mtsafe function(s) t/t_dist_attributes/mt_enabled.cpp:53: [mt_safe] ifh_test_caller_func_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:94: [] ifh_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:94: [mt_unsafe] ifh_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:94: [mt_unsafe_one] ifh_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "ifh_test_caller_func_VL_MT_START(VerilatedMutex &)" is stable_tree but calls non-stable_tree or non-mtsafe t/t_dist_attributes/mt_enabled.cpp:53: [mt_start, requires] ifh_test_caller_func_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:94: [] ifh_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:94: [mt_unsafe] ifh_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:94: [mt_unsafe_one] ifh_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "ifh_test_caller_func_VL_PURE(VerilatedMutex &)" is pure but calls non-pure function(s) t/t_dist_attributes/mt_enabled.cpp:53: [pure] ifh_test_caller_func_VL_PURE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:94: [] ifh_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:94: [acquire] ifh_VL_ACQUIRE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:94: [acquire] ifh_VL_ACQUIRE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:94: [excludes] ifh_VL_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:94: [mt_safe] ifh_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:94: [excludes] ifh_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:94: [mt_safe_postinit] ifh_VL_MT_SAFE_POSTINIT(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:94: [mt_start, requires] ifh_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:94: [mt_unsafe] ifh_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:94: [mt_unsafe_one] ifh_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:94: [release] ifh_VL_RELEASE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:94: [release] ifh_VL_RELEASE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:94: [requires] ifh_VL_REQUIRES(VerilatedMutex &) %Error: "ifh_test_caller_func_hdr_VL_MT_SAFE(VerilatedMutex &)" is mtsafe but calls non-mtsafe function(s) t/t_dist_attributes/mt_enabled.h:97: [mt_safe] ifh_test_caller_func_hdr_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:94: [] ifh_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:94: [mt_unsafe] ifh_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:94: [mt_unsafe_one] ifh_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "ifh_test_caller_func_hdr_VL_MT_START(VerilatedMutex &)" is stable_tree but calls non-stable_tree or non-mtsafe t/t_dist_attributes/mt_enabled.h:97: [mt_start, requires] ifh_test_caller_func_hdr_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:94: [] ifh_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:94: [mt_unsafe] ifh_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:94: [mt_unsafe_one] ifh_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "ifh_test_caller_func_hdr_VL_PURE(VerilatedMutex &)" is pure but calls non-pure function(s) t/t_dist_attributes/mt_enabled.h:97: [pure] ifh_test_caller_func_hdr_VL_PURE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:94: [] ifh_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:94: [acquire] ifh_VL_ACQUIRE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:94: [acquire] ifh_VL_ACQUIRE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:94: [excludes] ifh_VL_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:94: [mt_safe] ifh_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:94: [excludes] ifh_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:94: [mt_safe_postinit] ifh_VL_MT_SAFE_POSTINIT(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:94: [mt_start, requires] ifh_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:94: [mt_unsafe] ifh_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:94: [mt_unsafe_one] ifh_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:94: [release] ifh_VL_RELEASE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:94: [release] ifh_VL_RELEASE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:94: [requires] ifh_VL_REQUIRES(VerilatedMutex &) %Error: "nsf_ae_NO_ANNOTATION(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:75: [] nsf_ae_NO_ANNOTATION(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:34: [mt_safe, pure] nsf_ae_NO_ANNOTATION(VerilatedMutex &) %Error: "nsf_ae_VL_ACQUIRE(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:75: [acquire] nsf_ae_VL_ACQUIRE(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:34: [mt_safe, pure, acquire] nsf_ae_VL_ACQUIRE(VerilatedMutex &) %Error: "nsf_ae_VL_ACQUIRE_SHARED(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:75: [acquire] nsf_ae_VL_ACQUIRE_SHARED(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:34: [mt_safe, pure, acquire] nsf_ae_VL_ACQUIRE_SHARED(VerilatedMutex &) %Error: "nsf_ae_VL_EXCLUDES(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:75: [excludes] nsf_ae_VL_EXCLUDES(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:34: [mt_safe, pure, excludes] nsf_ae_VL_EXCLUDES(VerilatedMutex &) %Error: "nsf_ae_VL_MT_SAFE(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:75: [mt_safe] nsf_ae_VL_MT_SAFE(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:34: [mt_safe, pure] nsf_ae_VL_MT_SAFE(VerilatedMutex &) %Error: "nsf_ae_VL_MT_SAFE_EXCLUDES(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:75: [excludes] nsf_ae_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:34: [mt_safe, pure, excludes] nsf_ae_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) %Error: "nsf_ae_VL_MT_SAFE_POSTINIT(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:75: [mt_safe_postinit] nsf_ae_VL_MT_SAFE_POSTINIT(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:34: [mt_safe, mt_safe_postinit, pure] nsf_ae_VL_MT_SAFE_POSTINIT(VerilatedMutex &) %Error: "nsf_ae_VL_MT_START(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:75: [mt_start, requires] nsf_ae_VL_MT_START(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:34: [mt_start, mt_safe, pure, requires] nsf_ae_VL_MT_START(VerilatedMutex &) %Error: "nsf_ae_VL_MT_UNSAFE(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:75: [mt_unsafe] nsf_ae_VL_MT_UNSAFE(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:34: [mt_safe, mt_unsafe, pure] nsf_ae_VL_MT_UNSAFE(VerilatedMutex &) %Error: "nsf_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:75: [mt_unsafe_one] nsf_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:34: [mt_safe, mt_unsafe_one, pure] nsf_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "nsf_ae_VL_PURE(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:75: [pure] nsf_ae_VL_PURE(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:34: [mt_safe, pure] nsf_ae_VL_PURE(VerilatedMutex &) %Error: "nsf_ae_VL_RELEASE(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:75: [release] nsf_ae_VL_RELEASE(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:34: [mt_safe, pure, release] nsf_ae_VL_RELEASE(VerilatedMutex &) %Error: "nsf_ae_VL_RELEASE_SHARED(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:75: [release] nsf_ae_VL_RELEASE_SHARED(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:34: [mt_safe, pure, release] nsf_ae_VL_RELEASE_SHARED(VerilatedMutex &) %Error: "nsf_ae_VL_REQUIRES(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:75: [requires] nsf_ae_VL_REQUIRES(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:34: [mt_safe, pure, requires] nsf_ae_VL_REQUIRES(VerilatedMutex &) %Error: "nsf_test_caller_func_VL_MT_SAFE(VerilatedMutex &)" is mtsafe but calls non-mtsafe function(s) t/t_dist_attributes/mt_enabled.cpp:42: [mt_safe] nsf_test_caller_func_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:62: [] nsf_au_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:62: [mt_unsafe] nsf_au_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:62: [mt_unsafe_one] nsf_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_ACQUIRE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_PURE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_RELEASE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_RELEASE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_REQUIRES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:70: [] nsf_aa_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:70: [mt_unsafe] nsf_aa_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:70: [mt_unsafe_one] nsf_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:75: [] nsf_ae_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:75: [mt_unsafe] nsf_ae_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:75: [mt_unsafe_one] nsf_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:80: [mt_safe, mt_unsafe, pure] nsf_ea_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:80: [mt_safe, mt_unsafe_one, pure] nsf_ea_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "nsf_test_caller_func_VL_MT_START(VerilatedMutex &)" is stable_tree but calls non-stable_tree or non-mtsafe t/t_dist_attributes/mt_enabled.cpp:42: [mt_start, requires] nsf_test_caller_func_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:62: [] nsf_au_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:62: [mt_unsafe] nsf_au_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:62: [mt_unsafe_one] nsf_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_ACQUIRE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_PURE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_RELEASE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_RELEASE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_REQUIRES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:70: [] nsf_aa_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:70: [mt_unsafe] nsf_aa_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:70: [mt_unsafe_one] nsf_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:75: [] nsf_ae_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:75: [mt_unsafe] nsf_ae_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:75: [mt_unsafe_one] nsf_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:80: [mt_safe, mt_unsafe, pure] nsf_ea_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:80: [mt_safe, mt_unsafe_one, pure] nsf_ea_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "nsf_test_caller_func_VL_PURE(VerilatedMutex &)" is pure but calls non-pure function(s) t/t_dist_attributes/mt_enabled.cpp:42: [pure] nsf_test_caller_func_VL_PURE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:62: [] nsf_au_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:62: [acquire] nsf_au_VL_ACQUIRE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:62: [acquire] nsf_au_VL_ACQUIRE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:62: [excludes] nsf_au_VL_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:62: [mt_safe] nsf_au_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:62: [excludes] nsf_au_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:62: [mt_safe_postinit] nsf_au_VL_MT_SAFE_POSTINIT(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:62: [mt_start, requires] nsf_au_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:62: [mt_unsafe] nsf_au_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:62: [mt_unsafe_one] nsf_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:62: [release] nsf_au_VL_RELEASE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:62: [release] nsf_au_VL_RELEASE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:62: [requires] nsf_au_VL_REQUIRES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_ACQUIRE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_PURE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_RELEASE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_RELEASE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_REQUIRES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:70: [] nsf_aa_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:70: [acquire] nsf_aa_VL_ACQUIRE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:70: [acquire] nsf_aa_VL_ACQUIRE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:70: [excludes] nsf_aa_VL_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:70: [mt_safe] nsf_aa_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:70: [excludes] nsf_aa_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:70: [mt_safe_postinit] nsf_aa_VL_MT_SAFE_POSTINIT(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:70: [mt_start, requires] nsf_aa_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:70: [mt_unsafe] nsf_aa_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:70: [mt_unsafe_one] nsf_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:70: [release] nsf_aa_VL_RELEASE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:70: [release] nsf_aa_VL_RELEASE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:70: [requires] nsf_aa_VL_REQUIRES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:75: [] nsf_ae_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:75: [acquire] nsf_ae_VL_ACQUIRE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:75: [acquire] nsf_ae_VL_ACQUIRE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:75: [excludes] nsf_ae_VL_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:75: [mt_safe] nsf_ae_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:75: [excludes] nsf_ae_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:75: [mt_safe_postinit] nsf_ae_VL_MT_SAFE_POSTINIT(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:75: [mt_start, requires] nsf_ae_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:75: [mt_unsafe] nsf_ae_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:75: [mt_unsafe_one] nsf_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:75: [release] nsf_ae_VL_RELEASE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:75: [release] nsf_ae_VL_RELEASE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:75: [requires] nsf_ae_VL_REQUIRES(VerilatedMutex &) %Error: "nsf_test_caller_func_hdr_VL_MT_SAFE(VerilatedMutex &)" is mtsafe but calls non-mtsafe function(s) t/t_dist_attributes/mt_enabled.h:83: [mt_safe] nsf_test_caller_func_hdr_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:62: [] nsf_au_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:62: [mt_unsafe] nsf_au_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:62: [mt_unsafe_one] nsf_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_ACQUIRE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_PURE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_RELEASE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_RELEASE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_REQUIRES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:70: [] nsf_aa_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:70: [mt_unsafe] nsf_aa_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:70: [mt_unsafe_one] nsf_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:75: [] nsf_ae_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:75: [mt_unsafe] nsf_ae_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:75: [mt_unsafe_one] nsf_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:80: [mt_safe, mt_unsafe, pure] nsf_ea_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:80: [mt_safe, mt_unsafe_one, pure] nsf_ea_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "nsf_test_caller_func_hdr_VL_MT_START(VerilatedMutex &)" is stable_tree but calls non-stable_tree or non-mtsafe t/t_dist_attributes/mt_enabled.h:83: [mt_start, requires] nsf_test_caller_func_hdr_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:62: [] nsf_au_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:62: [mt_unsafe] nsf_au_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:62: [mt_unsafe_one] nsf_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_ACQUIRE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_PURE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_RELEASE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_RELEASE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_REQUIRES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:70: [] nsf_aa_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:70: [mt_unsafe] nsf_aa_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:70: [mt_unsafe_one] nsf_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:75: [] nsf_ae_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:75: [mt_unsafe] nsf_ae_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:75: [mt_unsafe_one] nsf_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:80: [mt_safe, mt_unsafe, pure] nsf_ea_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:80: [mt_safe, mt_unsafe_one, pure] nsf_ea_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "nsf_test_caller_func_hdr_VL_PURE(VerilatedMutex &)" is pure but calls non-pure function(s) t/t_dist_attributes/mt_enabled.h:83: [pure] nsf_test_caller_func_hdr_VL_PURE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:62: [] nsf_au_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:62: [acquire] nsf_au_VL_ACQUIRE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:62: [acquire] nsf_au_VL_ACQUIRE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:62: [excludes] nsf_au_VL_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:62: [mt_safe] nsf_au_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:62: [excludes] nsf_au_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:62: [mt_safe_postinit] nsf_au_VL_MT_SAFE_POSTINIT(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:62: [mt_start, requires] nsf_au_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:62: [mt_unsafe] nsf_au_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:62: [mt_unsafe_one] nsf_au_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:62: [release] nsf_au_VL_RELEASE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:62: [release] nsf_au_VL_RELEASE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:62: [requires] nsf_au_VL_REQUIRES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_ACQUIRE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_PURE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_RELEASE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_RELEASE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_REQUIRES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:70: [] nsf_aa_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:70: [acquire] nsf_aa_VL_ACQUIRE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:70: [acquire] nsf_aa_VL_ACQUIRE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:70: [excludes] nsf_aa_VL_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:70: [mt_safe] nsf_aa_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:70: [excludes] nsf_aa_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:70: [mt_safe_postinit] nsf_aa_VL_MT_SAFE_POSTINIT(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:70: [mt_start, requires] nsf_aa_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:70: [mt_unsafe] nsf_aa_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:70: [mt_unsafe_one] nsf_aa_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:70: [release] nsf_aa_VL_RELEASE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:70: [release] nsf_aa_VL_RELEASE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:70: [requires] nsf_aa_VL_REQUIRES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:75: [] nsf_ae_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:75: [acquire] nsf_ae_VL_ACQUIRE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:75: [acquire] nsf_ae_VL_ACQUIRE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:75: [excludes] nsf_ae_VL_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:75: [mt_safe] nsf_ae_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:75: [excludes] nsf_ae_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:75: [mt_safe_postinit] nsf_ae_VL_MT_SAFE_POSTINIT(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:75: [mt_start, requires] nsf_ae_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:75: [mt_unsafe] nsf_ae_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:75: [mt_unsafe_one] nsf_ae_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:75: [release] nsf_ae_VL_RELEASE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:75: [release] nsf_ae_VL_RELEASE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.h:75: [requires] nsf_ae_VL_REQUIRES(VerilatedMutex &) %Error: "nsf_ua_VL_ACQUIRE(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_ACQUIRE(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:25: [acquire] nsf_ua_VL_ACQUIRE(VerilatedMutex &) %Error: "nsf_ua_VL_ACQUIRE_SHARED(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:25: [acquire] nsf_ua_VL_ACQUIRE_SHARED(VerilatedMutex &) %Error: "nsf_ua_VL_EXCLUDES(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_EXCLUDES(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:25: [excludes] nsf_ua_VL_EXCLUDES(VerilatedMutex &) %Error: "nsf_ua_VL_MT_SAFE(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:25: [mt_safe] nsf_ua_VL_MT_SAFE(VerilatedMutex &) %Error: "nsf_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:25: [excludes] nsf_ua_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) %Error: "nsf_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:25: [mt_safe_postinit] nsf_ua_VL_MT_SAFE_POSTINIT(VerilatedMutex &) %Error: "nsf_ua_VL_MT_START(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_START(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:25: [mt_start, requires] nsf_ua_VL_MT_START(VerilatedMutex &) %Error: "nsf_ua_VL_MT_UNSAFE(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_UNSAFE(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:25: [mt_unsafe] nsf_ua_VL_MT_UNSAFE(VerilatedMutex &) %Error: "nsf_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:25: [mt_unsafe_one] nsf_ua_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "nsf_ua_VL_PURE(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_PURE(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:25: [pure] nsf_ua_VL_PURE(VerilatedMutex &) %Error: "nsf_ua_VL_RELEASE(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_RELEASE(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:25: [release] nsf_ua_VL_RELEASE(VerilatedMutex &) %Error: "nsf_ua_VL_RELEASE_SHARED(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_RELEASE_SHARED(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:25: [release] nsf_ua_VL_RELEASE_SHARED(VerilatedMutex &) %Error: "nsf_ua_VL_REQUIRES(VerilatedMutex &)" declaration does not match definition t/t_dist_attributes/mt_enabled.h:66: [] nsf_ua_VL_REQUIRES(VerilatedMutex &) [declaration] t/t_dist_attributes/mt_enabled.cpp:25: [requires] nsf_ua_VL_REQUIRES(VerilatedMutex &) %Error: "sfc_test_caller_func_VL_MT_SAFE(VerilatedMutex &)" is mtsafe but calls non-mtsafe function(s) t/t_dist_attributes/mt_enabled.cpp:63: [mt_safe] sfc_test_caller_func_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.cpp:60: [] sfc_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.cpp:60: [mt_unsafe] sfc_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.cpp:60: [mt_unsafe_one] sfc_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "sfc_test_caller_func_VL_MT_START(VerilatedMutex &)" is stable_tree but calls non-stable_tree or non-mtsafe t/t_dist_attributes/mt_enabled.cpp:63: [mt_start, requires] sfc_test_caller_func_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.cpp:60: [] sfc_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.cpp:60: [mt_unsafe] sfc_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.cpp:60: [mt_unsafe_one] sfc_VL_MT_UNSAFE_ONE(VerilatedMutex &) %Error: "sfc_test_caller_func_VL_PURE(VerilatedMutex &)" is pure but calls non-pure function(s) t/t_dist_attributes/mt_enabled.cpp:63: [pure] sfc_test_caller_func_VL_PURE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.cpp:60: [] sfc_NO_ANNOTATION(VerilatedMutex &) t/t_dist_attributes/mt_enabled.cpp:60: [acquire] sfc_VL_ACQUIRE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.cpp:60: [acquire] sfc_VL_ACQUIRE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.cpp:60: [excludes] sfc_VL_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.cpp:60: [mt_safe] sfc_VL_MT_SAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.cpp:60: [excludes] sfc_VL_MT_SAFE_EXCLUDES(VerilatedMutex &) t/t_dist_attributes/mt_enabled.cpp:60: [mt_safe_postinit] sfc_VL_MT_SAFE_POSTINIT(VerilatedMutex &) t/t_dist_attributes/mt_enabled.cpp:60: [mt_start, requires] sfc_VL_MT_START(VerilatedMutex &) t/t_dist_attributes/mt_enabled.cpp:60: [mt_unsafe] sfc_VL_MT_UNSAFE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.cpp:60: [mt_unsafe_one] sfc_VL_MT_UNSAFE_ONE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.cpp:60: [release] sfc_VL_RELEASE(VerilatedMutex &) t/t_dist_attributes/mt_enabled.cpp:60: [release] sfc_VL_RELEASE_SHARED(VerilatedMutex &) t/t_dist_attributes/mt_enabled.cpp:60: [requires] sfc_VL_REQUIRES(VerilatedMutex &) %Error: "unannotatedMtDisabledFunctionBad()" defined in a file marked as VL_MT_DISABLED_CODE_UNIT has declaration(s) without VL_MT_DISABLED annotation t/t_dist_attributes/mt_disabled.h:20: [mt_disabled, excludes] unannotatedMtDisabledFunctionBad() [declaration] t/t_dist_attributes/mt_disabled.cpp:20: [] unannotatedMtDisabledFunctionBad() t/t_dist_attributes/mt_disabled.h:20: [] unannotatedMtDisabledFunctionBad() t/t_dist_attributes/mt_disabled.h:23: [] unannotatedMtDisabledFunctionBad() Number of functions reported unsafe: 230 verilator-5.042/test_regress/t/t_param_type4.py0000755000542200017500000000073415101701376022217 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_vpi_unimpl.py0000755000542200017500000000113415101701376022147 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe --vpi --no-l2name", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_dump.v0000644000542200017500000001152415101701376020550 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [31:0] out; // From test of Test.v // End of automatics Test test(/*AUTOINST*/ // Outputs .out (out[31:0]), // Inputs .clk (clk), .in (in[31:0])); // Aggregate outputs into a single result vector wire [63:0] result = {32'h0, out}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc == 0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc < 10) begin sum <= '0; end else if (cyc < 90) begin end else if (cyc == 99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h4afe43fb79d7b71e if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test(/*AUTOARG*/ // Outputs out, // Inputs clk, in ); // Replace this module with the device under test. // // Change the code in the t module to apply values to the inputs and // merge the output values into the result vector. input clk; input [31:0] in; output reg [31:0] out; always @(posedge clk) begin out <= in; // Assert control dump test. $assertoff; $assertkill; assert(0); $asserton; $assertcontrol(3, 8); begin : blk disable blk; end end initial begin assert_simple_immediate_else: assert(0) else $display("fail"); assert_simple_immediate_stmt: assert(0) $display("pass"); assert_simple_immediate_stmt_else: assert(0) $display("pass"); else $display("fail"); assume_simple_immediate: assume(0); assume_simple_immediate_else: assume(0) else $display("fail"); assume_simple_immediate_stmt: assume(0) $display("pass"); assume_simple_immediate_stmt_else: assume(0) $display("pass"); else $display("fail"); end assert_observed_deferred_immediate: assert #0 (0); assert_observed_deferred_immediate_else: assert #0 (0) else $display("fail"); assert_observed_deferred_immediate_stmt: assert #0 (0) $display("pass"); assert_observed_deferred_immediate_stmt_else: assert #0 (0) $display("pass"); else $display("fail"); assume_observed_deferred_immediate: assume #0 (0); assume_observed_deferred_immediate_else: assume #0 (0) else $display("fail"); assume_observed_deferred_immediate_stmt: assume #0 (0) $display("pass"); assume_observed_deferred_immediate_stmt_else: assume #0 (0) $display("pass"); else $display("fail"); assert_final_deferred_immediate: assert final (0); assert_final_deferred_immediate_else: assert final (0) else $display("fail"); assert_final_deferred_immediate_stmt: assert final (0) $display("pass"); assert_final_deferred_immediate_stmt_else: assert final (0) $display("pass"); else $display("fail"); assume_final_deferred_immediate: assume final (0); assume_final_deferred_immediate_else: assume final (0) else $display("fail"); assume_final_deferred_immediate_stmt: assume final (0) $display("pass"); assume_final_deferred_immediate_stmt_else: assume final (0) $display("pass"); else $display("fail"); property prop(); @(posedge clk) 0 endproperty assert_concurrent: assert property (prop); assert_concurrent_else: assert property(prop) else $display("fail"); assert_concurrent_stmt: assert property(prop) $display("pass"); assert_concurrent_stmt_else: assert property(prop) $display("pass"); else $display("fail"); assume_concurrent: assume property(prop); assume_concurrent_else: assume property(prop) else $display("fail"); assume_concurrent_stmt: assume property(prop) $display("pass"); assume_concurrent_stmt_else: assume property(prop) $display("pass"); else $display("fail"); cover_concurrent: cover property(prop); cover_concurrent_stmt: cover property(prop) $display("pass"); restrict property (prop); endmodule verilator-5.042/test_regress/t/t_vlcov_rewrite.py0000755000542200017500000000151515101701376022662 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') for basename in [ "t_vlcov_data_a.dat", "t_vlcov_data_b.dat", "t_vlcov_data_c.dat", "t_vlcov_data_d.dat" ]: test.run(cmd=[ os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "t/" + basename, "--write", test.obj_dir + "/" + basename ], tee=False, verilator_run=True) test.files_identical(test.obj_dir + "/" + basename, "t/" + basename) test.passes() verilator-5.042/test_regress/t/t_lint_bsspace_bad.out0000644000542200017500000000114715101701376023421 0ustar mahmoudyfreeshell%Warning-BSSPACE: t/t_lint_bsspace_bad.v:10:21: Backslash followed by whitespace, perhaps the whitespace is accidental? 10 | `define FOO blak \ | ^ ... For warning description see https://verilator.org/warn/BSSPACE?v=latest ... Use "/* verilator lint_off BSSPACE */" and lint_on around source to disable this message. %Error: t/t_lint_bsspace_bad.v:11:4: syntax error, unexpected IDENTIFIER 11 | blak | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_delay_var.py0000755000542200017500000000101015101701376021724 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["--binary"]) if not test.vlt: test.execute() test.passes() verilator-5.042/test_regress/t/t_unopt_converge_unopt_bad.py0000755000542200017500000000110415101701376025052 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_unopt_converge.v" test.compile(verilator_flags2=["-fno-dfg"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_timing_debug2.out0000644000542200017500000031056015101701376022666 0ustar mahmoudyfreeshell-V{t#,#}- Verilated::debug is on. Message prefix indicates {,}. -V{t#,#}+ Vt_timing_debug2___024root___ctor_var_reset -V{t#,#}+ Vt_timing_debug2___024unit__03a__03aBaseClass__Vclpkg___ctor_var_reset -V{t#,#}+ Vt_timing_debug2___024unit___ctor_var_reset -V{t#,#}+ Vt_timing_debug2_t___ctor_var_reset -V{t#,#}+ Vt_timing_debug2_t__03a__03aAssignDelayClass__Vclpkg___ctor_var_reset -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass__Vclpkg___ctor_var_reset -V{t#,#}+ Vt_timing_debug2_t__03a__03aDelay10__Vclpkg___ctor_var_reset -V{t#,#}+ Vt_timing_debug2_t__03a__03aDelay20__Vclpkg___ctor_var_reset -V{t#,#}+ Vt_timing_debug2_t__03a__03aDelay40__Vclpkg___ctor_var_reset -V{t#,#}+ Vt_timing_debug2_t__03a__03aDelayClass__Vclpkg___ctor_var_reset -V{t#,#}+ Vt_timing_debug2_t__03a__03aEventClass__Vclpkg___ctor_var_reset -V{t#,#}+ Vt_timing_debug2_t__03a__03aForkClass__Vclpkg___ctor_var_reset -V{t#,#}+ Vt_timing_debug2_t__03a__03aForkDelayClass__Vclpkg___ctor_var_reset -V{t#,#}+ Vt_timing_debug2_t__03a__03aLocalWaitClass__Vclpkg___ctor_var_reset -V{t#,#}+ Vt_timing_debug2_t__03a__03aNoDelay__Vclpkg___ctor_var_reset -V{t#,#}+ Vt_timing_debug2_t__03a__03aWaitClass__Vclpkg___ctor_var_reset -V{t#,#}+++++TOP Evaluate Vt_timing_debug2::eval_step -V{t#,#}+ Vt_timing_debug2___024root___eval_debug_assertions -V{t#,#}+ Initial -V{t#,#}+ Vt_timing_debug2___024root___eval_static -V{t#,#}+ Vt_timing_debug2_t___eval_static__TOP__t -V{t#,#}+ Vt_timing_debug2___024unit__03a__03aBaseClass::new -V{t#,#}+ Vt_timing_debug2___024unit__03a__03aBaseClass::_ctor_var_reset -V{t#,#}+ Vt_timing_debug2_t__03a__03aEventClass::new -V{t#,#}+ Vt_timing_debug2_t__03a__03aEventClass::_ctor_var_reset -V{t#,#}+ Vt_timing_debug2___024unit__03a__03aBaseClass::new -V{t#,#}+ Vt_timing_debug2___024unit__03a__03aBaseClass::_ctor_var_reset -V{t#,#}+ Vt_timing_debug2_t__03a__03aWaitClass::new -V{t#,#}+ Vt_timing_debug2_t__03a__03aWaitClass::_ctor_var_reset -V{t#,#}+ Vt_timing_debug2___024unit__03a__03aBaseClass::new -V{t#,#}+ Vt_timing_debug2___024unit__03a__03aBaseClass::_ctor_var_reset -V{t#,#}+ Vt_timing_debug2_t__03a__03aLocalWaitClass::new -V{t#,#}+ Vt_timing_debug2_t__03a__03aLocalWaitClass::_ctor_var_reset -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::new -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::_ctor_var_reset -V{t#,#}+ Vt_timing_debug2___024root___eval_initial -V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__0 -V{t#,#} Suspending process waiting for @([event] t.ec.e) at t/t_timing_class.v:111 -V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__1 -V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__2 -V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__3 -V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__4 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_count_5 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:97 -V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__5 -V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__6 -V{t#,#}+ Vt_timing_debug2_t__03a__03aDelayClass::new -V{t#,#}+ Vt_timing_debug2_t__03a__03aDelayClass::_ctor_var_reset -V{t#,#}+ Vt_timing_debug2_t__03a__03aDelay10::new -V{t#,#}+ Vt_timing_debug2_t__03a__03aDelay10::_ctor_var_reset -V{t#,#}+ Vt_timing_debug2_t__03a__03aDelayClass::new -V{t#,#}+ Vt_timing_debug2_t__03a__03aDelayClass::_ctor_var_reset -V{t#,#}+ Vt_timing_debug2_t__03a__03aDelay20::new -V{t#,#}+ Vt_timing_debug2_t__03a__03aDelay20::_ctor_var_reset -V{t#,#}+ Vt_timing_debug2_t__03a__03aDelayClass::new -V{t#,#}+ Vt_timing_debug2_t__03a__03aDelayClass::_ctor_var_reset -V{t#,#}+ Vt_timing_debug2_t__03a__03aDelay40::new -V{t#,#}+ Vt_timing_debug2_t__03a__03aDelay40::_ctor_var_reset -V{t#,#}+ Vt_timing_debug2_t__03a__03aDelayClass::new -V{t#,#}+ Vt_timing_debug2_t__03a__03aDelayClass::_ctor_var_reset -V{t#,#}+ Vt_timing_debug2_t__03a__03aNoDelay::new -V{t#,#}+ Vt_timing_debug2_t__03a__03aNoDelay::_ctor_var_reset -V{t#,#}+ Vt_timing_debug2_t__03a__03aAssignDelayClass::new -V{t#,#}+ Vt_timing_debug2_t__03a__03aAssignDelayClass::_ctor_var_reset -V{t#,#}+ Vt_timing_debug2_t__03a__03aDelay10::__VnoInFunc_do_delay -V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__7 -V{t#,#}+ Vt_timing_debug2_t__03a__03aForkClass::new -V{t#,#}+ Vt_timing_debug2_t__03a__03aForkClass::_ctor_var_reset -V{t#,#}+ Vt_timing_debug2_t__03a__03aForkClass::__VnoInFunc_do_fork -V{t#,#}+ Vt_timing_debug2_t__03a__03aForkClass::__VnoInFunc_do_fork____Vfork_1__0 -V{t#,#}+ Vt_timing_debug2_t__03a__03aForkClass::__VnoInFunc_do_fork____Vfork_1__1 -V{t#,#}+ Vt_timing_debug2_t__03a__03aForkClass::__VnoInFunc_do_fork____Vfork_1__1____Vfork_2__0 -V{t#,#}+ Vt_timing_debug2_t__03a__03aForkClass::__VnoInFunc_do_fork____Vfork_1__1____Vfork_2__1 -V{t#,#} Awaiting join of fork at: t/t_timing_class.v:250 -V{t#,#} Awaiting join of fork at: t/t_timing_class.v:245 -V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__8 -V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__9 -V{t#,#}+ Vt_timing_debug2___024root___eval_settle -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug2___024root___eval -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:97 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:97 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:97 -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#} Committing processes waiting for @([event] t.ec.e): -V{t#,#} - Process waiting at t/t_timing_class.v:111 -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug2::eval_step -V{t#,#}+ Vt_timing_debug2___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug2___024root___eval -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:97 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:97 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:97 -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 5: Process waiting at t/t_timing_class.v:131 -V{t#,#} Awaiting time 10: Process waiting at t/t_timing_class.v:173 -V{t#,#} Awaiting time 10: Process waiting at t/t_timing_class.v:247 -V{t#,#} Awaiting time 20: Process waiting at t/t_timing_class.v:119 -V{t#,#} Awaiting time 20: Process waiting at t/t_timing_class.v:252 -V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:257 -V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:120 -V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:122 -V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 -V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:97 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:97 -V{t#,#} Process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:97 awaiting resumption -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 2 is active: @([true] __VdynSched.evaluate()) -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} Resuming processes: -V{t#,#} - Process waiting at t/t_timing_class.v:97 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:97 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:98 -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:98 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:98 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:98 -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:98 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:98 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:98 -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug2::eval_step -V{t#,#}+ Vt_timing_debug2___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug2___024root___eval -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:98 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:98 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:98 -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 10: Process waiting at t/t_timing_class.v:173 -V{t#,#} Awaiting time 10: Process waiting at t/t_timing_class.v:247 -V{t#,#} Awaiting time 10: Process waiting at t/t_timing_class.v:131 -V{t#,#} Awaiting time 20: Process waiting at t/t_timing_class.v:119 -V{t#,#} Awaiting time 20: Process waiting at t/t_timing_class.v:252 -V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:257 -V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:120 -V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:122 -V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 -V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:173 -V{t#,#}+ Vt_timing_debug2_t__03a__03aDelay20::__VnoInFunc_do_delay -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:247 -V{t#,#} Process forked at t/t_timing_class.v:246 finished -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:98 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:98 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:98 -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:98 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:98 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:98 -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug2::eval_step -V{t#,#}+ Vt_timing_debug2___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug2___024root___eval -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:98 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:98 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:98 -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 15: Process waiting at t/t_timing_class.v:131 -V{t#,#} Awaiting time 20: Process waiting at t/t_timing_class.v:119 -V{t#,#} Awaiting time 20: Process waiting at t/t_timing_class.v:252 -V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:257 -V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:174 -V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:120 -V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:122 -V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 -V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:98 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:98 -V{t#,#} Process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:98 awaiting resumption -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 2 is active: @([true] __VdynSched.evaluate()) -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} Resuming processes: -V{t#,#} - Process waiting at t/t_timing_class.v:98 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:98 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:99 -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:99 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:99 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:99 -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:99 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:99 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:99 -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug2::eval_step -V{t#,#}+ Vt_timing_debug2___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug2___024root___eval -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:99 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:99 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:99 -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 20: Process waiting at t/t_timing_class.v:119 -V{t#,#} Awaiting time 20: Process waiting at t/t_timing_class.v:252 -V{t#,#} Awaiting time 20: Process waiting at t/t_timing_class.v:131 -V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:257 -V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:174 -V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:120 -V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:122 -V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 -V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:119 -V{t#,#}+ Vt_timing_debug2_t__03a__03aEventClass::__VnoInFunc_wake -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:252 -V{t#,#}+ Vt_timing_debug2_t__03a__03aForkDelayClass::new -V{t#,#}+ Vt_timing_debug2_t__03a__03aForkDelayClass::_ctor_var_reset -V{t#,#} Process forked at t/t_timing_class.v:251 finished -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:99 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:99 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:99 -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([event] t.ec.e) -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} Ready processes waiting for @([event] t.ec.e): -V{t#,#} - Process waiting at t/t_timing_class.v:111 -V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:111 -V{t#,#}+ Vt_timing_debug2_t__03a__03aEventClass::__VnoInFunc_sleep -V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:99 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:99 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:99 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#} Doing post updates for processes: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_nba -V{t#,#}+ Vt_timing_debug2_t___nba_sequent__TOP__t__0 -V{t#,#}+ Vt_timing_debug2_t__03a__03aEventClass::__VnoInFunc_inc_trig_count -V{t#,#}+ Vt_timing_debug2___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:99 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:99 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:99 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#} Doing post updates for processes: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug2::eval_step -V{t#,#}+ Vt_timing_debug2___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug2___024root___eval -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:99 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:99 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:99 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#} Doing post updates for processes: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 25: Process waiting at t/t_timing_class.v:131 -V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:257 -V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:174 -V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:120 -V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:122 -V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 -V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:99 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:99 -V{t#,#} Process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:99 awaiting resumption -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 2 is active: @([true] __VdynSched.evaluate()) -V{t#,#} Doing post updates for processes: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} Resuming processes: -V{t#,#} - Process waiting at t/t_timing_class.v:99 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:99 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:100 -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:100 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:100 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:100 -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#} Doing post updates for processes: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:100 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:100 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:100 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#} Doing post updates for processes: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug2::eval_step -V{t#,#}+ Vt_timing_debug2___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug2___024root___eval -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:100 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:100 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:100 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#} Doing post updates for processes: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:257 -V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:174 -V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:131 -V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:120 -V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:122 -V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 -V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:257 -V{t#,#}+ Vt_timing_debug2_t__03a__03aForkDelayClass::__VnoInFunc_do_delay -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:174 -V{t#,#}+ Vt_timing_debug2_t__03a__03aDelay40::__VnoInFunc_do_delay -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:100 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:100 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:100 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#} Doing post updates for processes: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:100 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:100 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:100 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#} Doing post updates for processes: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug2::eval_step -V{t#,#}+ Vt_timing_debug2___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug2___024root___eval -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:100 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:100 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:100 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#} Doing post updates for processes: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 35: Process waiting at t/t_timing_class.v:131 -V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:120 -V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:122 -V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:238 -V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:175 -V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 -V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:100 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:100 -V{t#,#} Process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:100 awaiting resumption -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 2 is active: @([true] __VdynSched.evaluate()) -V{t#,#} Doing post updates for processes: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} Resuming processes: -V{t#,#} - Process waiting at t/t_timing_class.v:100 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:100 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:101 -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:101 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:101 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:101 -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#} Doing post updates for processes: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:101 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:101 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:101 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#} Doing post updates for processes: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug2::eval_step -V{t#,#}+ Vt_timing_debug2___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug2___024root___eval -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:101 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:101 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:101 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#} Doing post updates for processes: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:120 -V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:131 -V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:122 -V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:238 -V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:175 -V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 -V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:120 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:101 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:101 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:101 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([event] t.ec.e) -V{t#,#} 'act' region trigger index 2 is active: @([true] __VdynSched.evaluate()) -V{t#,#} Doing post updates for processes: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting resumption -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} No ready processes waiting for @([event] t.ec.e) -V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Resuming processes: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#}+ Vt_timing_debug2_t__03a__03aEventClass::__VnoInFunc_inc_trig_count -V{t#,#}+ Vt_timing_debug2_t__03a__03aWaitClass::__VnoInFunc_await -V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:101 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:58 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:101 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:101 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 -V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_nba -V{t#,#}+ Vt_timing_debug2_t___nba_sequent__TOP__t__0 -V{t#,#}+ Vt_timing_debug2_t__03a__03aEventClass::__VnoInFunc_inc_trig_count -V{t#,#}+ Vt_timing_debug2___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:101 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:58 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:101 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:101 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 -V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug2::eval_step -V{t#,#}+ Vt_timing_debug2___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug2___024root___eval -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:101 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:58 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:101 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:101 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 -V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 45: Process waiting at t/t_timing_class.v:131 -V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:122 -V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:238 -V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:175 -V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 -V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:101 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:58 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:101 -V{t#,#} Process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:101 awaiting resumption -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 -V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 2 is active: @([true] __VdynSched.evaluate()) -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} Resuming processes: -V{t#,#} - Process waiting at t/t_timing_class.v:101 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:101 -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:58 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 -V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:58 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 -V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug2::eval_step -V{t#,#}+ Vt_timing_debug2___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug2___024root___eval -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:58 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 -V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:122 -V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:131 -V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:238 -V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:175 -V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 -V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:122 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:58 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 -V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:58 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 -V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug2::eval_step -V{t#,#}+ Vt_timing_debug2___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug2___024root___eval -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:58 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 -V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 55: Process waiting at t/t_timing_class.v:131 -V{t#,#} Awaiting time 60: Process waiting at t/t_timing_class.v:123 -V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:238 -V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:175 -V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 -V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:58 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 -V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:58 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 -V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug2::eval_step -V{t#,#}+ Vt_timing_debug2___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug2___024root___eval -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:58 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 -V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 60: Process waiting at t/t_timing_class.v:123 -V{t#,#} Awaiting time 60: Process waiting at t/t_timing_class.v:131 -V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:238 -V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:175 -V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 -V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:123 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:58 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 -V{t#,#} Process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 awaiting resumption -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 2 is active: @([true] __VdynSched.evaluate()) -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} Resuming processes: -V{t#,#} - Process waiting at t/t_timing_class.v:58 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 -V{t#,#}+ Vt_timing_debug2_t__03a__03aLocalWaitClass::__VnoInFunc_await -V{t#,#}+ Vt_timing_debug2_t__03a__03aLocalWaitClass::__VnoInFunc_await____Vfork_1__0 -V{t#,#} Suspending process waiting for @([true] ((32'sh2a == t::LocalWaitClass.a) | (32'sh64 != t::LocalWaitClass.b))) at t/t_timing_class.v:75 -V{t#,#}+ Vt_timing_debug2_t__03a__03aLocalWaitClass::__VnoInFunc_await____Vfork_1__1 -V{t#,#} Awaiting join of fork at: t/t_timing_class.v:74 -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:75 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:75 -V{t#,#} Suspending process waiting for @([true] ((32'sh2a == t::LocalWaitClass.a) | (32'sh64 != t::LocalWaitClass.b))) at t/t_timing_class.v:75 -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:75 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:75 -V{t#,#} Suspending process waiting for @([true] ((32'sh2a == t::LocalWaitClass.a) | (32'sh64 != t::LocalWaitClass.b))) at t/t_timing_class.v:75 -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug2::eval_step -V{t#,#}+ Vt_timing_debug2___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug2___024root___eval -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:75 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:75 -V{t#,#} Suspending process waiting for @([true] ((32'sh2a == t::LocalWaitClass.a) | (32'sh64 != t::LocalWaitClass.b))) at t/t_timing_class.v:75 -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 65: Process waiting at t/t_timing_class.v:131 -V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:238 -V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:175 -V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:76 -V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 -V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:75 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:75 -V{t#,#} Suspending process waiting for @([true] ((32'sh2a == t::LocalWaitClass.a) | (32'sh64 != t::LocalWaitClass.b))) at t/t_timing_class.v:75 -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:75 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:75 -V{t#,#} Suspending process waiting for @([true] ((32'sh2a == t::LocalWaitClass.a) | (32'sh64 != t::LocalWaitClass.b))) at t/t_timing_class.v:75 -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug2::eval_step -V{t#,#}+ Vt_timing_debug2___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug2___024root___eval -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:75 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:75 -V{t#,#} Suspending process waiting for @([true] ((32'sh2a == t::LocalWaitClass.a) | (32'sh64 != t::LocalWaitClass.b))) at t/t_timing_class.v:75 -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:238 -V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:175 -V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:76 -V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:131 -V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 -V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:238 -V{t#,#} Process forked at t/t_timing_class.v:256 finished -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:250 -V{t#,#} Process forked at t/t_timing_class.v:250 finished -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:245 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:175 -V{t#,#}+ Vt_timing_debug2_t__03a__03aNoDelay::__VnoInFunc_do_delay -V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__6____Vfork_1__0 -V{t#,#}+ Vt_timing_debug2_t__03a__03aAssignDelayClass::__VnoInFunc_do_assign -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:76 -V{t#,#} Process forked at t/t_timing_class.v:76 finished -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:75 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:75 -V{t#,#} Process waiting for @([true] ((32'sh2a == t::LocalWaitClass.a) | (32'sh64 != t::LocalWaitClass.b))) at t/t_timing_class.v:75 awaiting resumption -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 2 is active: @([true] __VdynSched.evaluate()) -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} Resuming processes: -V{t#,#} - Process waiting at t/t_timing_class.v:75 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:75 -V{t#,#} Process forked at t/t_timing_class.v:75 finished -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:74 -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} No suspended processes waiting for dynamic trigger evaluation -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} No suspended processes waiting for dynamic trigger evaluation -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug2::eval_step -V{t#,#}+ Vt_timing_debug2___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug2___024root___eval -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} No suspended processes waiting for dynamic trigger evaluation -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 75: Process waiting at t/t_timing_class.v:224 -V{t#,#} Awaiting time 75: Process waiting at t/t_timing_class.v:131 -V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 -V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:190 -V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:224 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} No suspended processes waiting for dynamic trigger evaluation -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} No suspended processes waiting for dynamic trigger evaluation -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug2::eval_step -V{t#,#}+ Vt_timing_debug2___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug2___024root___eval -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} No suspended processes waiting for dynamic trigger evaluation -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 -V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:190 -V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:131 -V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:136 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:190 -V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__6____Vfork_2__0 -V{t#,#}+ Vt_timing_debug2_t__03a__03aAssignDelayClass::__VnoInFunc_do_assign -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} No suspended processes waiting for dynamic trigger evaluation -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} No suspended processes waiting for dynamic trigger evaluation -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug2::eval_step -V{t#,#}+ Vt_timing_debug2___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug2___024root___eval -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} No suspended processes waiting for dynamic trigger evaluation -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 85: Process waiting at t/t_timing_class.v:230 -V{t#,#} Awaiting time 85: Process waiting at t/t_timing_class.v:131 -V{t#,#} Awaiting time 90: Process waiting at t/t_timing_class.v:190 -V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:230 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} No suspended processes waiting for dynamic trigger evaluation -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} No suspended processes waiting for dynamic trigger evaluation -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug2::eval_step -V{t#,#}+ Vt_timing_debug2___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug2___024root___eval -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} No suspended processes waiting for dynamic trigger evaluation -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 90: Process waiting at t/t_timing_class.v:190 -V{t#,#} Awaiting time 90: Process waiting at t/t_timing_class.v:131 -V{t#,#} Awaiting time 100: Process waiting at t/t_timing_class.v:231 -V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:190 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} No suspended processes waiting for dynamic trigger evaluation -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} No suspended processes waiting for dynamic trigger evaluation -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug2::eval_step -V{t#,#}+ Vt_timing_debug2___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug2___024root___eval -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} No suspended processes waiting for dynamic trigger evaluation -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 95: Process waiting at t/t_timing_class.v:131 -V{t#,#} Awaiting time 100: Process waiting at t/t_timing_class.v:231 -V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} No suspended processes waiting for dynamic trigger evaluation -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} No suspended processes waiting for dynamic trigger evaluation -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug2::eval_step -V{t#,#}+ Vt_timing_debug2___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug2___024root___eval -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} No suspended processes waiting for dynamic trigger evaluation -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 100: Process waiting at t/t_timing_class.v:231 -V{t#,#} Awaiting time 100: Process waiting at t/t_timing_class.v:131 -V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:231 *-* All Finished *-* -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} No suspended processes waiting for dynamic trigger evaluation -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act -V{t#,#} No suspended processes waiting for dynamic trigger evaluation -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+ Vt_timing_debug2___024root___eval_final verilator-5.042/test_regress/t/t_gate_chained.py0000755000542200017500000000321015101701376022355 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = test.obj_dir + "/t_gate_chained.v" def gen(filename): with open(filename, 'w', encoding="utf8") as fh: fh.write("// Generated by t_gate_chained.py\n") fh.write("module t (clk,i,sel,o);\n") fh.write(" input clk;\n") fh.write(" input [63:0] i;\n") fh.write(" input [15:0] sel;\n") fh.write(" output [63:0] o;\n") fh.write("\n") prev = "i" n = 9000 for i in range(1, n): fh.write( (" wire [63:0] ass%04x = (sel == 16'h%04x) ? 64'h0 : " + prev + ";\n") % (i, i)) prev = "ass%04x" % i fh.write("\n") fh.write(" wire [63:0] o = " + prev + ";\n") fh.write("\n") fh.write(" always @ (posedge clk) begin\n") fh.write(' $write("*-* All Finished *-*\\n");' + "\n") fh.write(' $finish;' + "\n") fh.write(" end\n") fh.write("endmodule\n") gen(test.top_filename) test.compile( verilator_flags2=["--stats --x-assign fast --x-initial fast", "-Wno-UNOPTTHREADS -fno-dfg"]) test.execute() # Must be <<9000 above to prove this worked test.file_grep(test.stats, r'Optimizations, Gate sigs deleted\s+(\d+)', 8554) test.passes() verilator-5.042/test_regress/t/t_class_param_extends.v0000644000542200017500000000376015101701376023625 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Code your testbench here // or browse Examples class Base #(parameter PBASE = 12); bit [PBASE-1:0] member; function bit [PBASE-1:0] get_member; return member; endfunction function int get_p; return PBASE; endfunction endclass class Cls #(parameter P = 13) extends Base #(P); endclass typedef Cls#(8) Cls8_t; class Getter1; function int get_int; return 1; endfunction endclass class Getter2; function int get_int; return 2; endfunction endclass class Foo #(type T=Getter1); T foo_field; int x; function new(int y); foo_field = new; x = y; endfunction endclass class Bar #(type S=Getter2) extends Foo#(S); T field; function new(int y); super.new(y); field = new; endfunction function int get_field_int; return field.get_int(); endfunction function int get_foo_field_int; return foo_field.get_int(); endfunction endclass // See also t_class_param_mod.v module t; Cls #(.P(4)) c4; Cls8_t c8; Bar b; initial begin c4 = new; c8 = new; b = new(1); if (c4.PBASE != 4) $stop; if (c8.PBASE != 8) $stop; if (c4.get_p() != 4) $stop; if (c8.get_p() != 8) $stop; // verilator lint_off WIDTH c4.member = 32'haaaaaaaa; c8.member = 32'haaaaaaaa; // verilator lint_on WIDTH if (c4.member != 4'ha) $stop; if (c4.get_member() != 4'ha) $stop; if (c8.member != 8'haa) $stop; if (c8.get_member() != 8'haa) $stop; $display("c4 = %s", $sformatf("%p", c4)); if ($sformatf("%p", c4) != "'{member:'ha}") $stop; if (b.x != 1) $stop; if (b.get_field_int() != 2) $stop; if (b.get_foo_field_int() != 2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_var_bad_hide2.v0000644000542200017500000000076315101701376022257 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; // Arguable, but we won't throw a hidden warning on tcp_port parameter tcp_port = 5678; import "DPI-C" function int dpii_func ( input integer tcp_port, output longint obj ); // 't' is hidden: integer t; endmodule verilator-5.042/test_regress/t/t_display_concat.py0000755000542200017500000000100015101701376022751 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_bitsel_enum.v0000644000542200017500000000133215101701376022105 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Jonathon Donaldson. // SPDX-License-Identifier: CC0-1.0 module t_bitsel_enum ( output out0, output out1 ); localparam [6:0] CNST_VAL = 7'h22; enum logic [6:0] { ENUM_VAL = 7'h33 } MyEnum; assign out0 = CNST_VAL[0]; // Not supported by NC-verilog nor VCS, but other simulators do assign out1 = ENUM_VAL[0]; // named values of an enumeration should act like constants so this should work just like the line above works initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_array_pattern_2d.py0000755000542200017500000000073415101701376023232 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_std_randomize_unsup_bad.v0000644000542200017500000000075515101701376024511 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; initial begin int a, b; if (std::randomize(a, b) != 1) $stop; if (std::randomize(a, b) with { 2 < a; a < 7; b < a; } != 1) $stop; if (!(2 < a && a < 7 && b < a)) $stop; $write("-*-* All Finished *-*-\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_var_const_bad.v0000644000542200017500000000072515101701376022410 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; const logic [2:0] five = 3'd5; always @ (posedge clk) begin five = 3'd4; if (five !== 3'd5) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_class_ref_bad.v0000644000542200017500000000062015101701376022345 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class ClsRight; string m_s; endclass module t; string s; initial begin // verilator lint_off PKGNODECL s = ClsRigh::m_s; // Bad typo, issue #5475 end endmodule verilator-5.042/test_regress/t/t_verilated_debug.out0000644000542200017500000000523215101701376023271 0ustar mahmoudyfreeshell-V{t#,#}- Verilated::debug is on. Message prefix indicates {,}. -V{t#,#}+ Vt_verilated_debug___024root___ctor_var_reset internalsDump: Version: Verilator ### Argv: obj_vlt/t_verilated_debug/Vt_verilated_debug scopesDump: -V{t#,#}+++++TOP Evaluate Vt_verilated_debug::eval_step -V{t#,#}+ Vt_verilated_debug___024root___eval_debug_assertions -V{t#,#}+ Initial -V{t#,#}+ Vt_verilated_debug___024root___eval_static -V{t#,#}+ Vt_verilated_debug___024root___eval_initial -V{t#,#}+ Vt_verilated_debug___024root___eval_initial__TOP Data: w96: 000000aa 000000bb 000000cc -V{t#,#}+ Vt_verilated_debug___024root___eval_settle -V{t#,#}+ Eval -V{t#,#}+ Vt_verilated_debug___024root___eval -V{t#,#}+ Vt_verilated_debug___024root___eval_phase__act -V{t#,#}+ Vt_verilated_debug___024root___eval_triggers__act -V{t#,#}+ Vt_verilated_debug___024root___dump_triggers__act -V{t#,#}+ Vt_verilated_debug___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_verilated_debug___024root___trigger_orInto__act -V{t#,#}+ Vt_verilated_debug___024root___eval_phase__nba -V{t#,#}+ Vt_verilated_debug___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_verilated_debug::eval_step -V{t#,#}+ Vt_verilated_debug___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_verilated_debug___024root___eval -V{t#,#}+ Vt_verilated_debug___024root___eval_phase__act -V{t#,#}+ Vt_verilated_debug___024root___eval_triggers__act -V{t#,#}+ Vt_verilated_debug___024root___dump_triggers__act -V{t#,#}+ Vt_verilated_debug___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @(posedge clk) -V{t#,#}+ Vt_verilated_debug___024root___trigger_orInto__act -V{t#,#}+ Vt_verilated_debug___024root___eval_phase__nba -V{t#,#}+ Vt_verilated_debug___024root___trigger_anySet__act -V{t#,#}+ Vt_verilated_debug___024root___eval_nba -V{t#,#}+ Vt_verilated_debug___024root___nba_sequent__TOP__0 *-* All Finished *-* -V{t#,#}+ Vt_verilated_debug___024root___trigger_clear__act -V{t#,#}+ Vt_verilated_debug___024root___eval_phase__act -V{t#,#}+ Vt_verilated_debug___024root___eval_triggers__act -V{t#,#}+ Vt_verilated_debug___024root___dump_triggers__act -V{t#,#}+ Vt_verilated_debug___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_verilated_debug___024root___trigger_orInto__act -V{t#,#}+ Vt_verilated_debug___024root___eval_phase__nba -V{t#,#}+ Vt_verilated_debug___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+ Vt_verilated_debug___024root___eval_final verilator-5.042/test_regress/t/t_interface_notpublic.py0000755000542200017500000000073415101701376024011 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_mod_interface_array0.py0000755000542200017500000000073415101701376024047 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_primitive.py0000755000542200017500000000107115101701376023153 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=["--trace-vcd"]) test.execute() if test.vlt_all: test.file_grep(test.trace_filename, "sub_t_i") test.passes() verilator-5.042/test_regress/t/t_class_extends_default.out0000644000542200017500000000044315101701376024506 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_class_extends_default.v:14:25: Unsupported: 'extends' with 'default' 14 | class Cls1 extends Base1(default); | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_hierarchy_identifier_bad.py0000755000542200017500000000076315101701376024762 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_const.py0000755000542200017500000000073415101701376021120 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_timing_fork_comb.py0000755000542200017500000000101015101701376023266 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary -Wno-UNOPTFLAT"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_select_bad_range4.py0000755000542200017500000000077615101701376023325 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_cover_toggle_width.py0000755000542200017500000000120015101701376023635 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_cover_toggle.v" test.compile(verilator_flags2=['--cc --coverage-toggle --coverage-max-width 1025']) test.execute() test.file_grep(test.obj_dir + "/coverage.dat", "largeish") test.passes() verilator-5.042/test_regress/t/t_mod_recurse.py0000755000542200017500000000073415101701376022301 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_clocking_bad2.out0000644000542200017500000000152415101701376022625 0ustar mahmoudyfreeshell%Error: t/t_clocking_bad2.v:15:32: 1step not allowed as output skew 15 | default input #1 output #1step; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_clocking_bad2.v:16:23: Multiple default input skews not allowed 16 | default input #2 output #2; | ^ %Error: t/t_clocking_bad2.v:16:33: Multiple default output skews not allowed 16 | default input #2 output #2; | ^ %Error: t/t_clocking_bad2.v:17:15: 1step not allowed as output skew 17 | output #1step out; | ^ %Error: t/t_clocking_bad2.v:18:8: Multiple clockvars with the same name not allowed 18 | output out; | ^~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_enum_base_bad.out0000644000542200017500000000514215101701376022710 0ustar mahmoudyfreeshell%Error: t/t_enum_base_bad.v:11:11: Enum data type must be an integer atom or vector type (IEEE 1800-2023 6.19) : ... note: In instance 't' 11 | typedef enum s_t { | ^~~~ t/t_enum_base_bad.v:9:11: ... Location of failing data type 'struct{}t.s_t' 9 | typedef struct {int a;} s_t; | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_enum_base_bad.v:16:3: Enum data type must be an integer atom or vector type (IEEE 1800-2023 6.19) : ... note: In instance 't' 16 | enum int_t [1:0] { | ^~~~ t/t_enum_base_bad.v:15:11: ... Location of failing data type 'int' 15 | typedef int int_t; | ^~~ %Error: t/t_enum_base_bad.v:21:3: Enum data type must be an integer atom or vector type (IEEE 1800-2023 6.19) : ... note: In instance 't' 21 | enum d2_t { | ^~~~ t/t_enum_base_bad.v:20:11: ... Location of failing data type 'bit[1:0]' 20 | typedef bit [1:0][1:0] d2_t; | ^~~ %Error: t/t_enum_base_bad.v:25:3: Enum data type must be an integer atom or vector type (IEEE 1800-2023 6.19) : ... note: In instance 't' 25 | enum logic [1:0][1:0] { | ^~~~ t/t_enum_base_bad.v:25:8: ... Location of failing data type 'logic[1:0]' 25 | enum logic [1:0][1:0] { | ^~~~~ %Error: t/t_enum_base_bad.v:30:3: Enum data type must be an integer atom or vector type (IEEE 1800-2023 6.19) : ... note: In instance 't' 30 | enum str_t { | ^~~~ t/t_enum_base_bad.v:29:11: ... Location of failing data type 'struct{}t.str_t' 29 | typedef struct packed {int x;} str_t; | ^~~~~~ %Error: t/t_enum_base_bad.v:35:3: Enum data type must be an integer atom or vector type (IEEE 1800-2023 6.19) : ... note: In instance 't' 35 | enum enum_t { | ^~~~ t/t_enum_base_bad.v:34:11: ... Location of failing data type 'enum{}t.enum_t' 34 | typedef enum {ENUM_VAL} enum_t; | ^~~~ %Error: t/t_enum_base_bad.v:40:3: Enum data type must be an integer atom or vector type (IEEE 1800-2023 6.19) : ... note: In instance 't' 40 | enum array2_t { | ^~~~ t/t_enum_base_bad.v:39:25: ... Location of failing data type 'logic$[1:0]' 39 | typedef logic array2_t[1:0]; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_var_pins_scui.py0000755000542200017500000000444715101701376022643 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.pli_filename = "t/t_var_pinsizes.cpp" test.top_filename = "t/t_var_pinsizes.v" test.compile(verilator_flags2=["-sc -pins-uint8 --trace-vcd --exe", test.pli_filename], make_main=False) test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_in\s+&i1;') test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_in\s+&i8;') test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_in\s+&i16;') test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_in\s+&i32;') test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_in\s+&i64;') test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_in\s>\s+&i65;') test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_in\s>\s+&ibv1;') test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_in\s>\s+&ibv16;') test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_out\s+&o1;') test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_out\s+&o8;') test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_out\s+&o16;') test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_out\s+&o32;') test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_out\s+&o64;') test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_out\s>\s+&o65;') test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_out\s>\s+&obv1;') test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_out\s>\s+&obv16;') test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_pinnotfound.v0000644000542200017500000000067315101701376023177 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off PINNOTFOUND */ module a; localparam A=1; generate if (A==0) begin b b_inst1 (.x(1'b0)); // nonexistent port b #(.PX(1'b0)) b_inst2 (); // nonexistent parameter end endgenerate endmodule module b; endmodule verilator-5.042/test_regress/t/t_math_shortreal_unsup_bad.out0000644000542200017500000000063315101701376025220 0ustar mahmoudyfreeshell%Warning-SHORTREAL: t/t_math_shortreal_unsup_bad.v:9:4: Unsupported: shortreal being promoted to real (suggest use real instead) 9 | shortreal s; | ^~~~~~~~~ ... For warning description see https://verilator.org/warn/SHORTREAL?v=latest ... Use "/* verilator lint_off SHORTREAL */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_trace_complex_fst.out0000644000542200017500000001136715101701376023653 0ustar mahmoudyfreeshell$date Tue Jun 10 19:02:36 2025 $end $version fstWriter $end $timescale 1ps $end $scope module top $end $attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end $attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end $var wire 1 ! clk $end $scope module $unit $end $var bit 1 " global_bit $end $upscope $end $scope module t $end $var wire 1 ! clk $end $var integer 32 # cyc [31:0] $end $var bit 2 $ v_strp [1:0] $end $var bit 4 % v_strp_strp [3:0] $end $var bit 2 & v_unip_strp [1:0] $end $var bit 2 ' v_arrp [2:1] $end $var bit 4 ( v_arrp_arrp [3:0] $end $var bit 4 ) v_arrp_strp [3:0] $end $var bit 1 * v_arru[1] $end $var bit 1 + v_arru[2] $end $var bit 1 , v_arru_arru[3][1] $end $var bit 1 - v_arru_arru[3][2] $end $var bit 1 . v_arru_arru[4][1] $end $var bit 1 / v_arru_arru[4][2] $end $var bit 2 0 v_arru_arrp[3] [2:1] $end $var bit 2 1 v_arru_arrp[4] [2:1] $end $var bit 2 2 v_arru_strp[3] [1:0] $end $var bit 2 3 v_arru_strp[4] [1:0] $end $var real 64 4 v_real $end $var real 64 5 v_arr_real[0] $end $var real 64 6 v_arr_real[1] $end $var longint 64 7 v_chandle [63:0] $end $var logic 64 8 v_str32x2 [63:0] $end $attrbegin misc 07 "" 1 $end $var int 32 9 v_enumed [31:0] $end $attrbegin misc 07 "" 1 $end $var int 32 : v_enumed2 [31:0] $end $attrbegin misc 07 "" 2 $end $var logic 3 ; v_enumb [2:0] $end $var logic 6 < v_enumb2_str [5:0] $end $var logic 8 = unpacked_array[-2] [7:0] $end $var logic 8 > unpacked_array[-1] [7:0] $end $var logic 8 ? unpacked_array[0] [7:0] $end $var bit 1 @ LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end $scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end $var parameter 32 A PARAM [31:0] $end $upscope $end $scope module p2 $end $var parameter 32 B PARAM [31:0] $end $upscope $end $scope module p3 $end $var parameter 32 C PARAM [31:0] $end $upscope $end $scope module unnamedblk1 $end $var integer 32 D b [31:0] $end $scope module unnamedblk2 $end $var integer 32 E a [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b00000000000000000000000000000000 E b00000000000000000000000000000000 D b00000000000000000000000000000011 C b00000000000000000000000000000010 B b00000000000000000000000000000100 A 0@ b00000000 ? b00000000 > b00000000 = b000000 < b000 ; b00000000000000000000000000000000 : b00000000000000000000000000000000 9 b0000000000000000000000000000000000000000000000000000000011111111 8 b0000000000000000000000000000000000000000000000000000000000000000 7 r0 6 r0 5 r0 4 b00 3 b00 2 b00 1 b00 0 0/ 0. 0- 0, 0+ 0* b0000 ) b0000 ( b00 ' b00 & b0000 % b00 $ b00000000000000000000000000000000 # 1" 0! $end #10 1! b00000000000000000000000000000001 # b11 $ b1111 % b11 & b11 ' b1111 ( b1111 ) b11 0 b11 1 b11 2 b11 3 r0.1 4 r0.2 5 r0.3 6 b0000000000000000000000000000000100000000000000000000000011111110 8 b00000000000000000000000000000001 9 b00000000000000000000000000000010 : b111 ; b00000000000000000000000000000101 D b00000000000000000000000000000101 E #15 0! #20 1! b110 ; b00000000000000000000000000000100 : b00000000000000000000000000000010 9 b0000000000000000000000000000001000000000000000000000000011111101 8 r0.6 6 r0.4 5 r0.2 4 b00 3 b00 2 b00 1 b00 0 b0000 ) b0000 ( b00 ' b00 & b0000 % b00 $ b00000000000000000000000000000010 # b111111 < #25 0! #30 1! b110110 < b00000000000000000000000000000011 # b11 $ b1111 % b11 & b11 ' b1111 ( b1111 ) b11 0 b11 1 b11 2 b11 3 r0.3 4 r0.6000000000000001 5 r0.8999999999999999 6 b0000000000000000000000000000001100000000000000000000000011111100 8 b00000000000000000000000000000011 9 b00000000000000000000000000000110 : b101 ; #35 0! #40 1! b100 ; b00000000000000000000000000001000 : b00000000000000000000000000000100 9 b0000000000000000000000000000010000000000000000000000000011111011 8 r1.2 6 r0.8 5 r0.4 4 b00 3 b00 2 b00 1 b00 0 b0000 ) b0000 ( b00 ' b00 & b0000 % b00 $ b00000000000000000000000000000100 # b101101 < #45 0! #50 1! b100100 < b00000000000000000000000000000101 # b11 $ b1111 % b11 & b11 ' b1111 ( b1111 ) b11 0 b11 1 b11 2 b11 3 r0.5 4 r1 5 r1.5 6 b0000000000000000000000000000010100000000000000000000000011111010 8 b00000000000000000000000000000101 9 b00000000000000000000000000001010 : b011 ; #55 0! #60 1! b010 ; b00000000000000000000000000001100 : b00000000000000000000000000000110 9 b0000000000000000000000000000011000000000000000000000000011111001 8 r1.8 6 r1.2 5 r0.6 4 b00 3 b00 2 b00 1 b00 0 b0000 ) b0000 ( b00 ' b00 & b0000 % b00 $ b00000000000000000000000000000110 # b011011 < verilator-5.042/test_regress/t/t_cxx_equal_to.py0000755000542200017500000000105615101701376022463 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_cxx_equal_to.v" test.compile(verilator_flags2=['--binary --trace-vcd']) test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_abort_saif.py0000755000542200017500000000124415101701376023256 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_trace_abort.v" test.golden_filename = "t/t_trace_abort_saif.out" test.compile(verilator_flags2=['--cc --trace-saif']) test.execute(fails=True) test.saif_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_func_return_bad.v0000644000542200017500000000110215101701376022732 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; task t1; return 1; // Shouldn't return value endtask function int f1; return; // Should return value endfunction initial begin return; // Not under function continue; // Not under loop break; // Not under loop begin : foo end disable foo; // Disabling outside block end endmodule verilator-5.042/test_regress/t/t_timing_class_static_delay.v0000644000542200017500000000112015101701376024773 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `define DELAY 10 class Foo; task wait_dynamically(); #`DELAY; endtask static task wait_statically(); #`DELAY; endtask endclass module t; Foo foo = new; initial begin foo.wait_dynamically(); if ($time != `DELAY) $stop; Foo::wait_statically(); if ($time != 2*`DELAY) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_with_suggest_bad.v0000644000542200017500000000076315101701376023130 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias' // // Simple bi-directional alias test. // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin int q[$]; int qv[$]; // Value returns q = '{1, 2, 2, 4, 3}; qv = q.find with (itemm == 2); qv = q.find(misspelled) with (misspelledd == 2); end endmodule verilator-5.042/test_regress/t/t_dpi_import.v0000644000542200017500000002463415101701376021757 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VCS `define NO_SHORTREAL `define NO_TIME `endif `ifdef NC `define NO_SHORTREAL `define NO_TIME `endif `ifdef VERILATOR // Unsupported `define NO_SHORTREAL `endif module t (/*AUTOARG*/ // Inputs clk ); input clk; typedef struct packed { bit [47:0] lo; bit [47:0] hi; } str_t; typedef struct packed { int a; int b; } substr_t; // Allowed import return types: // void, byte, shortint, int, longint, real, shortreal, chandle, and string // Scalar bit and logic // // Allowed argument types: // Same as above plus packed arrays import "DPI-C" pure function bit dpii_f_bit (input bit i); import "DPI-C" pure function bit [8-1:0] dpii_f_bit8 (input bit [8-1:0] i); import "DPI-C" pure function bit [9-1:0] dpii_f_bit9 (input bit [9-1:0] i); import "DPI-C" pure function bit [16-1:0] dpii_f_bit16 (input bit [16-1:0] i); import "DPI-C" pure function bit [17-1:0] dpii_f_bit17 (input bit [17-1:0] i); import "DPI-C" pure function bit [32-1:0] dpii_f_bit32 (input bit [32-1:0] i); // Illegal to return > 32 bits, so we use longint import "DPI-C" pure function longint dpii_f_bit33 (input bit [33-1:0] i); import "DPI-C" pure function longint dpii_f_bit64 (input bit [64-1:0] i); import "DPI-C" pure function int dpii_f_int (input int i); import "DPI-C" pure function byte dpii_f_byte (input byte i); import "DPI-C" pure function shortint dpii_f_shortint (input shortint i); import "DPI-C" pure function longint dpii_f_longint (input longint i); import "DPI-C" pure function chandle dpii_f_chandle (input chandle i); import "DPI-C" pure function string dpii_f_string (input string i); import "DPI-C" pure function real dpii_f_real (input real i); `ifndef NO_SHORTREAL import "DPI-C" pure function shortreal dpii_f_shortreal(input shortreal i); `endif import "DPI-C" pure function void dpii_v_bit (input bit i, output bit o); import "DPI-C" pure function void dpii_v_int (input int i, output int o); import "DPI-C" pure function void dpii_v_byte (input byte i, output byte o); import "DPI-C" pure function void dpii_v_shortint (input shortint i, output shortint o); import "DPI-C" pure function void dpii_v_longint (input longint i, output longint o); import "DPI-C" pure function void dpii_v_struct (input str_t i, output str_t o); import "DPI-C" pure function void dpii_v_substruct(input substr_t i, output int o); import "DPI-C" pure function void dpii_v_chandle (input chandle i, output chandle o); import "DPI-C" pure function void dpii_v_string (input string i, inout string o); import "DPI-C" pure function void dpii_v_real (input real i, output real o); import "DPI-C" pure function void dpii_v_uint (input int unsigned i, output int unsigned o); import "DPI-C" pure function void dpii_v_ushort (input shortint unsigned i, output shortint unsigned o); import "DPI-C" pure function void dpii_v_ulong (input longint unsigned i, output longint unsigned o); `ifndef NO_SHORTREAL import "DPI-C" pure function void dpii_v_shortreal(input shortreal i, output shortreal o); `endif import "DPI-C" pure function void dpii_v_bit64 (input bit [64-1:0] i, output bit [64-1:0] o); import "DPI-C" pure function void dpii_v_bit95 (input bit [95-1:0] i, output bit [95-1:0] o); import "DPI-C" pure function void dpii_v_bit96 (input bit [96-1:0] i, output bit [96-1:0] o); import "DPI-C" pure function void dpii_v_reg (input reg i, output reg o); import "DPI-C" pure function void dpii_v_reg15 (input reg [14:0] i, output reg [14:0] o); import "DPI-C" pure function void dpii_v_reg95 (input reg [94:0] i, output reg [94:0] o); import "DPI-C" pure function void dpii_v_integer (input integer i, output integer o); `ifndef NO_TIME import "DPI-C" pure function void dpii_v_time (input time i, output time o); `endif import "DPI-C" pure function int dpii_f_strlen(input string i); import "DPI-C" function string dpii_f_null(); import "DPI-C" function void dpii_f_void(); // Try a task import "DPI-C" task dpii_t_void(); import "DPI-C" context task dpii_t_void_context(); import "DPI-C" task dpii_t_int(input int i, output int o); // Try non-pure, aliasing with name import "DPI-C" dpii_fa_bit = function int oth_f_int1(input int i); import "DPI-C" dpii_fa_bit = function int oth_f_int2(input int i); // Check Verilator doesn't convert double underscores import "DPI-C" pure function int dpii__under___score(input int i); bit i_b, o_b; bit [7:0] i_b8; bit [8:0] i_b9; bit [15:0] i_b16; bit [16:0] i_b17; bit [31:0] i_b32; bit [32:0] i_b33, o_b33; bit [63:0] i_b64, o_b64; bit [94:0] i_b95, o_b95; bit [95:0] i_b96, o_b96; int i_i, o_i; byte i_y, o_y; shortint i_s, o_s; longint i_l, o_l; str_t i_t, o_t; substr_t i_ss; int o_ss; int unsigned i_iu, o_iu; shortint unsigned i_su, o_su; longint unsigned i_lu, o_lu; // verilator lint_off UNDRIVEN chandle i_c, o_c; string i_n, o_n; // verilator lint_on UNDRIVEN real i_d, o_d; `ifndef NO_SHORTREAL shortreal i_f, o_f; `endif reg i_r, o_r; reg [14:0] i_r15, o_r15; reg [94:0] i_r95, o_r95; integer i_in, o_in; time i_tm, o_tm; bit [94:0] wide; bit [6*8:1] string6; initial begin wide = 95'h15caff7a73c48afee4ffcb57; i_b = 1'b1; i_b8 = {1'b1,wide[8-2:0]}; i_b9 = {1'b1,wide[9-2:0]}; i_b16 = {1'b1,wide[16-2:0]}; i_b17 = {1'b1,wide[17-2:0]}; i_b32 = {1'b1,wide[32-2:0]}; i_b33 = {1'b1,wide[33-2:0]}; i_b64 = {1'b1,wide[64-2:0]}; i_b95 = {1'b1,wide[95-2:0]}; i_b96 = {1'b1,wide[96-2:0]}; i_i = {1'b1,wide[32-2:0]}; i_iu= {1'b1,wide[32-2:0]}; i_y = {1'b1,wide[8-2:0]}; i_s = {1'b1,wide[16-2:0]}; i_su= {1'b1,wide[16-2:0]}; i_l = {1'b1,wide[64-2:0]}; i_lu= {1'b1,wide[64-2:0]}; i_t = {1'b1,wide[95-1:0]}; i_d = 32.1; i_ss.a = 32'h054321ab; i_ss.b = 32'h05a43b21; `ifndef NO_SHORTREAL i_f = 30.2; `endif i_r = '0; i_r15 = wide[14:0]; i_r95 = wide[94:0]; i_in = -1234; i_tm = 62; if (dpii_f_bit (i_b) !== ~i_b) $stop; if (dpii_f_bit8 (i_b8) !== ~i_b8) $stop; if (dpii_f_bit9 (i_b9) !== ~i_b9) $stop; if (dpii_f_bit16 (i_b16) !== ~i_b16) $stop; if (dpii_f_bit17 (i_b17) !== ~i_b17) $stop; if (dpii_f_bit32 (i_b32) !== ~i_b32) $stop; // These return different sizes, so we need to truncate // verilator lint_off WIDTH o_b33 = dpii_f_bit33 (i_b33); o_b64 = dpii_f_bit64 (i_b64); // verilator lint_on WIDTH if (o_b33 !== ~i_b33) $stop; if (o_b64 !== ~i_b64) $stop; if (dpii_f_bit (i_b) !== ~i_b) $stop; if (dpii_f_int (i_i) !== ~i_i) $stop; if (dpii_f_byte (i_y) !== ~i_y) $stop; if (dpii_f_shortint (i_s) !== ~i_s) $stop; if (dpii_f_longint (i_l) !== ~i_l) $stop; if (dpii_f_chandle (i_c) !== i_c) $stop; if (dpii_f_string (i_n) != i_n) $stop; if (dpii_f_real (i_d) != i_d+1.5) $stop; `ifndef NO_SHORTREAL if (dpii_f_shortreal(i_f) != i_f+1.5) $stop; `endif dpii_v_bit (i_b,o_b); if (o_b !== ~i_b) $stop; dpii_v_int (i_i,o_i); if (o_i !== ~i_i) $stop; dpii_v_byte (i_y,o_y); if (o_y !== ~i_y) $stop; dpii_v_shortint (i_s,o_s); if (o_s !== ~i_s) $stop; dpii_v_longint (i_l,o_l); if (o_l !== ~i_l) $stop; dpii_v_uint (i_iu,o_iu); if (o_iu !== ~i_iu) $stop; dpii_v_ushort (i_su,o_su); if (o_su !== ~i_su) $stop; dpii_v_ulong (i_lu,o_lu); if (o_lu !== ~i_lu) $stop; dpii_v_struct (i_t,o_t); if (o_t !== ~i_t) $stop; dpii_v_substruct(i_ss,o_ss); if (o_ss !== i_ss.a - i_ss.b) $stop; dpii_v_chandle (i_c,o_c); if (o_c !== i_c) $stop; dpii_v_string (i_n,o_n); if (o_n != i_n) $stop; dpii_v_real (i_d,o_d); if (o_d != i_d+1.5) $stop; `ifndef NO_SHORTREAL dpii_v_shortreal(i_f,o_f); if (o_f != i_f+1.5) $stop; `endif dpii_v_bit64 (i_b64,o_b64); if (o_b64 !== ~i_b64) $stop; dpii_v_bit95 (i_b95,o_b95); if (o_b95 !== ~i_b95) $stop; dpii_v_bit96 (i_b96,o_b96); if (o_b96 !== ~i_b96) $stop; dpii_v_reg (i_r,o_r); if (o_r !== ~i_r) $stop; dpii_v_reg15 (i_r15,o_r15); if (o_r15 !== ~i_r15) $stop; dpii_v_reg95 (i_r95,o_r95); if (o_r95 !== ~i_r95) $stop; dpii_v_integer (i_in,o_in); if (o_in != ~i_in) $stop; `ifndef NO_TIME dpii_v_time (i_tm,o_tm); if (o_tm != ~i_tm) $stop; `endif if (dpii_f_strlen("") != 0) $stop; if (dpii_f_strlen("s") != 1) $stop; if (dpii_f_strlen("st") != 2) $stop; if (dpii_f_strlen("str") != 3) $stop; if (dpii_f_strlen("stri") != 4) $stop; if (dpii_f_strlen("string_l") != 8) $stop; if (dpii_f_strlen("string_len") != 10) $stop; string6 = "hello6"; `ifdef VERILATOR string6 = $c48(string6); // Don't optimize away - want to see the constant conversion function `endif if (dpii_f_strlen(string6) != 6) $stop; if (dpii_f_null() != "") $stop; dpii_f_void(); dpii_t_void(); dpii_t_void_context(); i_i = 32'h456789ab; dpii_t_int(i_i, o_i); if (o_b !== ~i_b) $stop; // Check alias if (oth_f_int1(32'd123) !== ~32'd123) $stop; if (oth_f_int2(32'd124) !== ~32'd124) $stop; if (dpii__under___score(32'd60) != 32'd61) $stop; $write("*-* All Finished *-*\n"); $finish; end always @ (posedge clk) begin i_b <= ~i_b; // This once mis-threw a BLKSEQ warning dpii_v_bit(i_b, o_b); if (o_b !== ~i_b) $stop; end endmodule verilator-5.042/test_regress/t/t_timing_clkgen1.py0000755000542200017500000000101315101701376022654 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary -Wno-MINTYPMAXDLY"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_nba_hier.v0000644000542200017500000000457115101701376021356 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); module t; logic clk = 1'b0; always #5 clk = ~clk; logic [7:0] x; sub a_0(); sub a_1(); always @(posedge clk) begin a_0.x[3:0] <= ~x[3:0]; a_1.x[7:0] <= ~x; end sub b_0(); sub b_1(); always begin // Having this @posedge here makes this a 'suspendable' process, causing // the use of the FlagUnique scheme @(posedge clk); b_0.x[3:0] <= ~x[3:0]; b_1.x[7:0] <= ~x; end sub c_0(); sub c_1(); always @(posedge clk) begin c_0.x[3:0] <= ~x[3:0]; c_1.x[7:0] <= ~x; end assign c_0.x[9:8] = 2'd1; assign c_1.x[9:8] = 2'd2; sub d_0(); sub d_1(); always @(posedge clk) begin d_0.y[0][3:0] <= ~x[3:0]; d_1.y[0][7:0] <= ~x; end sub e_0(); sub e_1(); always @(posedge clk) begin for (int i = 0; i < 2; ++i) begin e_0.y[i][3:0] <= ~x[3:0]; e_1.y[i][7:0] <= ~x; end end initial begin #1; x = 8'hcc; @(posedge clk); @(negedge clk); `checkh(a_0.x[3:0], 4'h3); `checkh(a_1.x[7:0], 8'h33); `checkh(b_0.x[3:0], 4'h3); `checkh(b_1.x[7:0], 8'h33); `checkh(c_0.x[3:0], 4'h3); `checkh(c_0.x[9:8], 2'h1); `checkh(c_1.x[7:0], 8'h33); `checkh(c_1.x[9:8], 2'h2); `checkh(d_0.y[0][3:0], 4'h3); `checkh(d_1.y[0][7:0], 8'h33); for (int i = 0; i < 2; ++i) begin `checkh(e_0.y[i][3:0], 4'h3); `checkh(e_1.y[i][7:0], 8'h33); end #1; x = 8'h55; @(posedge clk); @(negedge clk); `checkh(a_0.x[3:0], 4'ha); `checkh(a_1.x[7:0], 8'haa); `checkh(b_0.x[3:0], 4'ha); `checkh(b_1.x[7:0], 8'haa); `checkh(c_0.x[3:0], 4'ha); `checkh(c_0.x[9:8], 2'h1); `checkh(c_1.x[7:0], 8'haa); `checkh(c_1.x[9:8], 2'h2); `checkh(d_0.y[0][3:0], 4'ha); `checkh(d_1.y[0][7:0], 8'haa); for (int i = 0; i < 2; ++i) begin `checkh(e_0.y[i][3:0], 4'ha); `checkh(e_1.y[i][7:0], 8'haa); end #1; $finish; end endmodule module sub; logic [9:0] x; logic [9:0] y [99]; endmodule verilator-5.042/test_regress/t/t_gen_defparam_bad.out0000644000542200017500000000106515101701376023362 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_gen_defparam_bad.v:9:12: Unsupported: defparam with no dot 9 | id_15 = id_14; | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_gen_defparam_bad.v:11:18: Unsupported: defparam with no dot 11 | defparam id_8 = 1, id_9 = 1; | ^ %Error-UNSUPPORTED: t/t_gen_defparam_bad.v:11:28: Unsupported: defparam with no dot 11 | defparam id_8 = 1, id_9 = 1; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_param_concat.v0000644000542200017500000000120215101701376022222 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; parameter UNSIZED = 10; integer cyc=1; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==1) begin if ({UNSIZED,UNSIZED+1} != {32'd10, 32'd11}) $stop; if ({2{UNSIZED}} != {32'd10, 32'd10}) $stop; end if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_flag_make_gmake.py0000755000542200017500000000103115101701376023033 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_flag_make_cmake.v" test.compile(verilator_flags2=['--make gmake']) test.passes() verilator-5.042/test_regress/t/t_flag_skipidentical.v0000644000542200017500000000035215101701376023414 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; endmodule verilator-5.042/test_regress/t/t_sys_file_scan2.v0000644000542200017500000000223715101701376022507 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t; int cfg_file, f_stat; reg [8*8:1] fname; int index; int count; initial begin cfg_file = $fopen("t/t_sys_file_scan2.dat", "r"); f_stat = $fscanf(cfg_file, "%s", fname); `checkd(f_stat, 1); `checks(fname, "vec"); f_stat = $fscanf(cfg_file, "%d", index); `checkd(f_stat, 1); `checkd(index, 6163); f_stat = $fscanf(cfg_file, "%d", count); `checkd(f_stat, 1); `checkd(count, 16); //eof f_stat = $fscanf(cfg_file, "%s", fname); `checkd(f_stat, -1); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_flag_csplit.py0000755000542200017500000001033215101701376022254 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') def check_splits(): got1 = False gotSyms1 = False for filename in test.glob_some(test.obj_dir + "/*.cpp"): if re.search(r'Syms__1', filename): gotSyms1 = True elif re.search(r'__1', filename): got1 = True if not got1: test.error("No __1 split file found") if not gotSyms1: test.error("No Syms__1 split file found") def check_no_all_file(): for filename in test.glob_some(test.obj_dir + "/*.cpp"): if re.search(r'__ALL.cpp', filename): test.error("__ALL.cpp file found: " + filename) def check_cpp(filename): size = os.path.getsize(filename) if test.verbose: print(" File %6d %s\n" % (size, filename)) funcs = [] with open(filename, 'r', encoding="utf8") as fh: for line in fh: m = re.search(r'^(void|IData)\s+(.*::.*){', line) if not m: continue func = m.group(2) func = re.sub(r'\(.*$', '', func) if test.verbose: print("\tFunc " + func) if (re.search(r'(::_eval_initial_loop$', func) or re.search(r'::__Vconfigure$', func) or re.search(r'::trace$', func) or re.search(r'::traceInit$', func) or re.search(r'::traceFull$', func) or re.search(r'::final$', func) or re.search(r'::prepareClone$', func) or re.search(r'::atClone$', func)): continue funcs.append(func) if len(funcs) > 0: test.error("Split had multiple functions in $filename\n\t" + "\n\t".join(funcs)) def check_gcc_flags(filename): with open(filename, 'r', encoding="utf8") as fh: for line in fh: line = line.rstrip() if test.verbose: print(":log: " + line) if re.search(r'' + test.vm_prefix + r'\S*\.cpp', line): filetype = "slow" if re.search(r'(Slow|Syms)', line) else "fast" opt = "fast" if re.search(r'-O2', line) else "slow" if test.verbose: print(filetype + ", " + opt + ", " + line) if filetype != opt: test.error(filetype + " file compiled as if was " + opt + ": " + line) elif re.search(r'.cpp', line) and not re.search(r'-Os', line): test.error("library file not compiled with OPT_GLOBAL: " + line) # This rule requires GNU make > 4.1 (or so, known broken in 3.81) #%__Slow.o: %__Slow.cpp # $(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_SLOW) -c -o $@ $< if not test.make_version or float(test.make_version) < 4.1: test.skip("Test requires GNU Make version >= 4.1") test.compile(v_flags2=["--trace-vcd", "--output-split 1", "--output-split-cfuncs 1", "--exe", "../" + test.main_filename], verilator_make_gmake=False) # yapf:disable # We don't use the standard test_regress rules, as want to test the rules # properly build test.run(logfile=test.obj_dir + "/vlt_gcc.log", tee=test.verbose, cmd=[os.environ["MAKE"], "-C " + test.obj_dir, "-f "+test.vm_prefix+".mk", "-j 4", "VM_PREFIX="+test.vm_prefix, "TEST_OBJ_DIR="+test.obj_dir, "CPPFLAGS_DRIVER=-D"+test.name.upper(), ("CPPFLAGS_DRIVER2=-DTEST_VERBOSE=1" if test.verbose else ""), "OPT_FAST=-O2", "OPT_SLOW=-O0", "OPT_GLOBAL=-Os", ]) # yapf:disable test.execute() # Splitting should set VM_PARALLEL_BUILDS to 1 by default test.file_grep(test.obj_dir + "/" + test.vm_prefix + "_classes.mk", r'VM_PARALLEL_BUILDS\s*=\s*1') check_splits() check_no_all_file() check_gcc_flags(test.obj_dir + "/vlt_gcc.log") test.passes() verilator-5.042/test_regress/t/t_inst_pin_place_bad.v0000644000542200017500000000071715101701376023402 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2023 by Anthony Donlon. // SPDX-License-Identifier: CC0-1.0 module sub # ( parameter PARAM_A = 1, parameter type PARAM_B = logic ) ( input pin_1 ); endmodule module t; parameter type PARAM_B = string; sub #( .PARAM_B(PARAM_B), .pin_1(1) ) i_sub ( .PARAM_A(1) ); endmodule verilator-5.042/test_regress/t/t_randstate_seed_bad.v0000644000542200017500000000125315101701376023374 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls; function void test; automatic string s; s = get_randstate(); // Vlt only result check if (s[0] !== "R") $fatal(2, $sformatf("Bad get_randstate = '%s'", s)); set_randstate("000bad"); // Bad set_randstate("Zdlffjfmkmhodjcnddlffjfmkmhodjcnd"); // Bad endfunction endclass module t; initial begin Cls c; c = new; c.test; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_package_local_bad.py0000755000542200017500000000076615101701376023352 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dfg_synthesis.py0000755000542200017500000000706215101701376022644 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.sim_time = 2000000 if not os.path.exists(test.root + "/.git"): test.skip("Not in a git repository") # Generate the equivalence checks and declaration boilerplate rdFile = test.top_filename plistFile = test.obj_dir + "/portlist.vh" pdeclFile = test.obj_dir + "/portdecl.vh" checkFile = test.obj_dir + "/checks.h" nAlwaysSynthesized = 0 nAlwaysNotSynthesized = 0 nAlwaysReverted = 0 with open(rdFile, 'r', encoding="utf8") as rdFh, \ open(plistFile, 'w', encoding="utf8") as plistFh, \ open(pdeclFile, 'w', encoding="utf8") as pdeclFh, \ open(checkFile, 'w', encoding="utf8") as checkFh: for line in rdFh: if re.search(r'^\s*always.*//\s*nosynth$', line): nAlwaysNotSynthesized += 1 elif re.search(r'^\s*always.*//\s*revert$', line): nAlwaysReverted += 1 elif re.search(r'^\s*always', line): nAlwaysSynthesized += 1 line = line.split("//")[0] m = re.search(r'`signal\((\w+),', line) if not m: continue sig = m.group(1) plistFh.write(sig + ",\n") pdeclFh.write("output " + sig + ";\n") checkFh.write("if (ref." + sig + " != opt." + sig + ") {\n") checkFh.write(" std::cout << \"Mismatched " + sig + "\" << std::endl;\n") checkFh.write(" std::cout << \"Ref: 0x\" << std::hex << (ref." + sig + " + 0) << std::endl;\n") checkFh.write(" std::cout << \"Opt: 0x\" << std::hex << (opt." + sig + " + 0) << std::endl;\n") checkFh.write(" std::exit(1);\n") checkFh.write("}\n") # Compile un-optimized test.compile(verilator_flags2=[ "--stats", "--build", "-fno-dfg", "+incdir+" + test.obj_dir, "-Mdir", test.obj_dir + "/obj_ref", "--prefix", "Vref", "-Wno-UNOPTFLAT" ]) # yapf:disable test.file_grep_not(test.obj_dir + "/obj_ref/Vref__stats.txt", r'DFG.*Synthesis') # Compile optimized - also builds executable test.compile(verilator_flags2=[ "--stats", "--build", "--fdfg-synthesize-all", "-fno-dfg-pre-inline", "-fno-dfg-post-inline", "--exe", "+incdir+" + test.obj_dir, "-Mdir", test.obj_dir + "/obj_opt", "--prefix", "Vopt", "-fno-const-before-dfg", # Otherwise V3Const makes testing painful "-fno-split", # Dfg will take care of it "--debug", "--debugi", "0", "--dumpi-tree", "0", "-CFLAGS \"-I .. -I ../obj_ref\"", "../obj_ref/Vref__ALL.a", "../../t/" + test.name + ".cpp" ]) # yapf:disable test.file_grep(test.obj_dir + "/obj_opt/Vopt__stats.txt", r'DFG scoped Synthesis, synt / always blocks considered\s+(\d+)$', nAlwaysSynthesized + nAlwaysReverted + nAlwaysNotSynthesized) test.file_grep(test.obj_dir + "/obj_opt/Vopt__stats.txt", r'DFG scoped Synthesis, synt / always blocks synthesized\s+(\d+)$', nAlwaysSynthesized + nAlwaysReverted) test.file_grep(test.obj_dir + "/obj_opt/Vopt__stats.txt", r'DFG scoped Synthesis, synt / reverted \(multidrive\)\s+(\d)$', nAlwaysReverted) # Execute test to check equivalence test.execute(executable=test.obj_dir + "/obj_opt/Vopt") test.passes() verilator-5.042/test_regress/t/t_trace_ascendingrange_fst.py0000755000542200017500000000167515101701376025001 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_ascendingrange.v" # CI environment offers 2 VCPUs, 2 thread setting causes the following warning. # %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. # Strangely, asking for more threads makes it go away. test.compile(verilator_flags2=['--cc --trace-fst --trace-params -Wno-ASCRANGE'], threads=(6 if test.vltmt else 1)) test.execute() test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_func_lib_sub.v0000644000542200017500000000433315101701376022235 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define zednkw 200 module BreadAddrDP (zfghtn, cjtmau, vipmpg, knquim, kqxkkr); input zfghtn; input [4:0] cjtmau; input vipmpg; input [7:0] knquim; input [7:0] kqxkkr; reg covfok; reg [15:0] xwieqw; reg [2:0] ofnjjt; reg [37:0] hdsejo[1:0]; reg wxxzgd, tceppr, ratebp, fjizkr, iwwrnq; reg vrqrih, ryyjxy; reg fgzsox; wire xdjikl = ~wxxzgd & ~tceppr & ~ratebp & fjizkr; wire iytyol = ~wxxzgd & ~tceppr & ratebp & ~fjizkr & ~xwieqw[10]; wire dywooz = ~wxxzgd & ~tceppr & ratebp & ~fjizkr & xwieqw[10]; wire qnpfus = ~wxxzgd & ~tceppr & ratebp & fjizkr; wire fqlkrg = ~wxxzgd & tceppr & ~ratebp & ~fjizkr; wire ktsveg = hdsejo[0][6] | (hdsejo[0][37:34] == 4'h1); wire smxixw = vrqrih | (ryyjxy & ktsveg); wire [7:0] grvsrs, kyxrft, uxhkka; wire [7:0] eianuv = 8'h01 << ofnjjt; wire [7:0] jvpnxn = {8{qnpfus}} & eianuv; wire [7:0] zlnzlj = {8{fqlkrg}} & eianuv; wire [7:0] nahzat = {8{iytyol}} & eianuv; genvar i; generate for (i=0;i<8;i=i+1) begin : dnlpyw DecCountReg4 bzpytc (zfghtn, fgzsox, zlnzlj[i], knquim[3:0], covfok, grvsrs[i]); DecCountReg4 oghukp (zfghtn, fgzsox, zlnzlj[i], knquim[7:4], covfok, kyxrft[i]); DecCountReg4 ttvjoo (zfghtn, fgzsox, nahzat[i], kqxkkr[3:0], covfok, uxhkka[i]); end endgenerate endmodule module DecCountReg4 (clk, fgzsox, fckiyr, uezcjy, covfok, juvlsh); input clk, fgzsox, fckiyr, covfok; input [3:0] uezcjy; output juvlsh; task Xinit; begin `ifdef TEST_HARNESS khgawe = 1'b0; `endif end endtask function X; input vrdejo; begin `ifdef TEST_HARNESS if ((vrdejo & ~vrdejo) !== 1'h0) khgawe = 1'b1; `endif X = vrdejo; end endfunction task Xcheck; input vzpwwy; begin end endtask reg [3:0] udbvtl; assign juvlsh = |udbvtl; wire [3:0] mppedc = {4{fgzsox}} & (fckiyr ? uezcjy : (udbvtl - 4'h1)); wire qqibou = ((juvlsh | fckiyr) & covfok) | ~fgzsox; always @(posedge clk) begin Xinit; if (X(qqibou)) udbvtl <= #`zednkw mppedc; Xcheck(fgzsox); end endmodule verilator-5.042/test_regress/t/t_time_vpi_1ns1ns.out0000644000542200017500000000164515101701376023167 0ustar mahmoudyfreeshell:: In top.t Time scale of t is 1ns / 1ns [60] time%0d=60 123%0t=123 dig%0t=5432109877 dig%0d=5432109877 rdig%0t=5432109877 rdig%0f=5432109876.543210 acc%0t=12345678901234567890 acc%0d=12345678901234567890 [60.000000ns] time%0d=60 123%0t=123.000000ns dig%0t=5432109877.000000ns dig%0d=5432109877 rdig%0t=5432109876.543210ns rdig%0f=5432109876.543210 acc%0t=12345678901234567890.000000ns acc%0d=12345678901234567890 [60.000000ns] stime%0t=60.000000ns stime%0d=60 stime%0f=60.000000 [60.000000ns] rtime%0t=60.000000ns rtime%0d=60 rtime%0f=60.000000 global svGetTime = 0 0,60 global svGetTimeUnit = 0 -9 svGetTmePrecision = 0 -9 global vpiSimTime = 0,60 vpiScaledRealTime = 60 global vpiTimeUnit = -9 vpiTimePrecision = -9 top.t svGetTime = 0 0,60 top.t svGetTimeUnit = 0 -9 svGetTmePrecision = 0 -9 top.t vpiSimTime = 0,60 vpiScaledRealTime = 60 top.t vpiTimeUnit = -9 vpiTimePrecision = -9 *-* All Finished *-* verilator-5.042/test_regress/t/t_inst_noname_bad.py0000755000542200017500000000076615101701376023117 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_method_bad.py0000755000542200017500000000076615101701376023252 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dfg_3726.py0000755000542200017500000000070615101701376021212 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.passes() verilator-5.042/test_regress/t/t_vpi_public_params.v0000644000542200017500000000247715101701376023311 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2010 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef USE_VPI_NOT_DPI //We call it via $c so we can verify DPI isn't required - see bug572 `else import "DPI-C" context function int mon_check(); `endif // Copy of t_vpi_public_params.v but with the inline public taken out module t #( parameter int WIDTH = 32 ) (/*AUTOARG*/ // Inputs clk ); `ifdef VERILATOR `systemc_header extern "C" int mon_check(); `verilog `endif input clk; localparam int DEPTH = 16; localparam longint PARAM_LONG = 64'hFEDCBA9876543210; localparam string PARAM_STR = "'some string value'"; reg [WIDTH-1:0] mem0 [DEPTH:1]; integer i, status; // Test loop initial begin `ifdef VERILATOR status = $c32("mon_check()"); `endif `ifdef IVERILOG status = $mon_check(); `endif `ifndef USE_VPI_NOT_DPI status = mon_check(); `endif if (status!=0) begin $write("%%Error: t_vpi_param.cpp:%0d: C Test failed\n", status); $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule : t verilator-5.042/test_regress/t/t_class_eq.py0000755000542200017500000000077115101701376021565 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--binary']) test.execute() test.passes() verilator-5.042/test_regress/t/t_enum_type_bad.out0000644000542200017500000000216415101701376022760 0ustar mahmoudyfreeshell%Error-ENUMVALUE: t/t_enum_type_bad.v:28:11: Implicit conversion to enum 'enum{}t.e_t' from 'logic[31:0]' (IEEE 1800-2023 6.19.3) : ... note: In instance 't' : ... Suggest use enum's mnemonic, or static cast 28 | e = 1; | ^ ... For error description see https://verilator.org/warn/ENUMVALUE?v=latest %Error-ENUMVALUE: t/t_enum_type_bad.v:29:11: Implicit conversion to enum 'enum{}t.o_t' from 'enum{}t.e_t' (IEEE 1800-2023 6.19.3) : ... note: In instance 't' : ... Suggest use enum's mnemonic, or static cast 29 | o = e; | ^ %Error-ENUMVALUE: t/t_enum_type_bad.v:35:15: Implicit conversion to enum 'enum{}t.o_t' from 'enum{}t.e_t' (IEEE 1800-2023 6.19.3) : ... note: In instance 't' : ... Suggest use enum's mnemonic, or static cast 35 | o = str.m_e; | ^~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_timing_suspendable_deep.v0000644000542200017500000000120215101701376024444 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module for specialized type default values // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro. // SPDX-License-Identifier: CC0-1.0 `timescale 1ns/1ns event evt; class Baz; virtual task do_something(); endtask endclass class Foo extends Baz; endclass class Bar extends Foo; virtual task do_something(); @evt $display("Hello"); endtask endclass module top(); initial begin Bar bar; bar = new; fork #10 bar.do_something(); #20 $display("world!"); #10 ->evt; join end endmodule verilator-5.042/test_regress/t/t_trace_noflag_bad.py0000755000542200017500000000140415101701376023217 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile( # We need to list verilated_vcd_c.cpp because without --trace Verilator # won't build it itself automatically. verilator_flags2=["--cc --exe", "t/" + test.name + "_c.cpp", "verilated_vcd_c.cpp"], make_top_shell=False, make_main=False) test.execute(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_export_packed_struct2.v0000644000542200017500000000301715101701376024117 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Kefa Chen. // SPDX-License-Identifier: CC0-1.0 // Packed struct in package package TEST_TYPES; typedef union soft packed { logic [64 : 0] a; logic [2 : 0] b; } sub_t; typedef struct packed { struct packed { // Anonymous packed struct logic a; } anon; TEST_TYPES::sub_t [2:0][2:0][2:0] b; } in_t /*verilator public*/; typedef struct packed { TEST_TYPES::sub_t [2:0][2:0][2:0] b; struct packed {logic a;} anon; } out_t /*verilator public*/; endpackage // Packed struct in class class cls_in; typedef struct packed { logic a; TEST_TYPES::sub_t [2:0][2:0][2:0] b; } in_t /*verilator public*/; endclass //cls module add ( input TEST_TYPES::in_t op1, //input cls_in op2, output TEST_TYPES::out_t out ); cls_in::in_t op2 /*verilator public_flat*/; assign op2.a = op1.anon.a; generate for (genvar i = 0; i < 3; ++i) begin for (genvar j = 0; j < 3; ++j) begin for (genvar k = 0; k < 3; ++k) begin assign op2.b[i][j][k] = op1.b[i][j][k]; end end end endgenerate assign out.anon.a = op1.anon.a + op2.a; generate for (genvar i = 0; i < 3; ++i) begin for (genvar j = 0; j < 3; ++j) begin for (genvar k = 0; k < 3; ++k) begin assign out.b[i][j][k] = op1.b[i][j][k] + op2.b[i][j][k]; end end end endgenerate endmodule verilator-5.042/test_regress/t/t_assert_synth_parallel.vlt0000644000542200017500000000042015101701376024536 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. // SPDX-License-Identifier: CC0-1.0 `verilator_config parallel_case -file "t/t_assert_synth.v" -lines 55 verilator-5.042/test_regress/t/t_wide_temp_while_cond.cpp0000644000542200017500000000077415101701376024275 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // Copyright 2025 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 //************************************************************************* extern "C" int identity(int x) { return x; } verilator-5.042/test_regress/t/t_mem_multidim_trace.py0000755000542200017500000000105215101701376023624 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_mem_multidim.v" test.compile(verilator_flags2=['--cc --trace-vcd']) test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_ref_trace_inla.py0000755000542200017500000000132215101701376024741 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_ref_trace.v" test.golden_filename = "t/t_interface_ref_trace.out" test.compile(v_flags2=['+define+NO_INLINE_A'], verilator_flags2=['--trace-structs --trace-vcd']) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_inside_assoc_unsup.v0000644000542200017500000000050015101701376023470 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; int assoc[int]; bit m; initial begin m = (10 inside {assoc}); end endmodule verilator-5.042/test_regress/t/t_string_size.v0000644000542200017500000000502215101701376022137 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Outputs outempty64 ); output [63:0] outempty64; parameter string OS = "O"; parameter OI = "O"; // B is an integer of width 8 // verilator lint_off WIDTH parameter string EMPTYS = ""; parameter EMPTYI = ""; // B is an integer of width 8 parameter bit [23:0] EMPTY24 = ""; parameter bit [63:0] EMPTY64 = ""; // verilator lint_on WIDTH parameter bit [31:0] NEST = "NEST"; parameter bit [31:0] TEST = "TEST"; string s; // verilator lint_off WIDTH assign outempty64 = ""; // verilator lint_on WIDTH initial begin // IEEE: "Leading 0s are never printed" but that does not mean spaces are not $display(">%s< == >< (or > < also legal)", "\000"); $display(">%s< == >< (or > < also legal)", ""); $display(">%s< == > <", 32'h0); // Numeric context, so IEEE 1800-2023 11.10.3 "" is a "\000" if ($bits("") != 8) $stop; if ("" != "\000") $stop; if ($bits("A") != 8) $stop; s = ""; if (s.len != 0) $stop; // IEEE 1800-2023 6.16 "\000" assigned to string is ignored s = "\000yo\000"; if (s.len != 2) $stop; if (s != "yo") $stop; if ($bits(EMPTYI) != 8) $stop; if (EMPTYI != "\000") $stop; // verilator lint_off WIDTH if (EMPTYI == "TEST") $stop; if (EMPTYI == TEST) $stop; // verilator lint_on WIDTH if ($bits(EMPTY24) != 24) $stop; if (EMPTY24 != 0) $stop; $display(">%s< == > <", EMPTY24); if ($bits(EMPTY64) != 64) $stop; if (EMPTY64 != 0) $stop; $display(">%s< == > <", EMPTY64); if ($bits(EMPTYS) != 0) $stop; if (EMPTYS == "TEST") $stop; // Illegal in some simulators as not both strings if (EMPTYS == TEST) $stop; $display(">%s< == ><", EMPTYS); if ($bits(OS) != 8) $stop; if (OS != "O") $stop; if (OS == "TEST") $stop; // Illegal in some simulators as not both strings if (OS == TEST) $stop; if ($bits(OI) != 8) $stop; if (OI != "O") $stop; // verilator lint_off WIDTH if (OI == "TEST") $stop; if (OI == TEST) $stop; // verilator lint_on WIDTH if ($bits(outempty64) != 64) $stop; if (outempty64 != 64'h00_00_00_00_00_00_00_00) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_virtual_interface_method_bad.out0000644000542200017500000000056715101701376026026 0ustar mahmoudyfreeshell%Error: t/t_virtual_interface_method_bad.v:11:10: Member reference from interface to 'x' is not referencing a valid task or function : ... note: In instance 't' 11 | v_if.x(); | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_flag_x_initial_bad.out0000644000542200017500000000033415101701376023721 0ustar mahmoudyfreeshell%Error: Unknown setting for --x-initial: 'bad_one' ... Suggest '0', 'fast', or 'unique' ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_virtual_interface_delayed.py0000755000542200017500000000077115101701376025170 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--binary']) test.execute() test.passes() verilator-5.042/test_regress/t/t_clocking_out_on_change.v0000644000542200017500000000263515101701376024267 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t; logic clk = 0; initial forever #5 clk = ~clk; int cyc = 0; always @(posedge clk) begin cyc <= cyc + 1; if (cyc == 4) begin $write("*-* All Finished *-*\n"); $finish(); end end // Skew 0 logic ok1 = 1; always @(posedge clk) if (cyc == 0) begin if (!ok1) $stop; #1 cb.ok1 <= 0; #1 if (!ok1) $stop; end else if (cyc == 1) begin if (!ok1) $stop; #1 if (ok1) $stop; end else if (cyc == 2) ok1 <= 1; else if (!ok1) $stop; // Skew > 0 logic ok2 = 1; always @(posedge clk) if (cyc == 0) begin if (!ok2) $stop; #1 cb.ok2 <= 0; #2 if (!ok2) $stop; #3 if (!ok2) $stop; end else if (cyc == 1) begin if (!ok2) $stop; #1 if (!ok2) $stop; #2 if (ok2) $stop; end else if (cyc == 2) ok2 <= 1; else if (!ok2) $stop; // No timing logic ok3 = 0; always @(posedge clk) if (cyc == 0) ok3 <= 1; else if (cyc == 1) if (!ok3) $stop; // Clocking (used in all tests) clocking cb @(posedge clk); output ok1; output #1 ok2; output ok3; endclocking endmodule verilator-5.042/test_regress/t/t_math_shortreal.py0000755000542200017500000000073415101701376023006 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_forceable_var_trace.vcd.out0000644000542200017500000000525015101701376024667 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $var wire 1 # clk $end $var wire 1 $ rst $end $var wire 32 % cyc [31:0] $end $scope module t $end $var wire 1 # clk $end $var wire 1 $ rst $end $var wire 32 % cyc [31:0] $end $var wire 1 & tmp_1 $end $var wire 8 ' tmp_8 [7:0] $end $var wire 1 ( var_1 $end $var wire 8 ) var_8 [7:0] $end $var wire 1 ( obs_1 $end $var wire 8 ) obs_8 [7:0] $end $upscope $end $upscope $end $enddefinitions $end #0 0# 1$ b00000000000000000000000000000000 % 0& b00000000 ' 0( b00000000 ) #5 1# 0$ #10 0# #15 1# b00000000000000000000000000000001 % #20 0# #25 1# b00000000000000000000000000000010 % 1& 1( #30 0# #35 1# b00000000000000000000000000000011 % 0& b00000001 ' 0( b00000001 ) #40 0# #45 1# b00000000000000000000000000000100 % 1& 1( #50 0# #55 1# b00000000000000000000000000000101 % 0& b00000010 ' 0( b00000010 ) #60 0# #65 1# b00000000000000000000000000000110 % 1& 1( #70 0# #75 1# b00000000000000000000000000000111 % 0& b00000011 ' 0( b00000011 ) #80 0# #85 1# b00000000000000000000000000001000 % 1& 1( #90 0# #95 1# b00000000000000000000000000001001 % 0& b00000100 ' 0( b00000100 ) #100 0# #105 1# b00000000000000000000000000001010 % 1& 1( #110 0# #115 1# b00000000000000000000000000001011 % 0& b00000101 ' 0( b00000101 ) #120 0# #125 1# b00000000000000000000000000001100 % 1& 1( #130 0# #135 1# b00000000000000000000000000001101 % 0& b00000110 ' b00000110 ) #140 0# #145 1# b00000000000000000000000000001110 % 1& b11110101 ) #150 0# #155 1# b00000000000000000000000000001111 % 0& b00000111 ' 0( #160 0# #165 1# b00000000000000000000000000010000 % 1& b01011111 ) #170 0# #175 1# b00000000000000000000000000010001 % 0& b00001000 ' #180 0# #185 1# b00000000000000000000000000010010 % 1& 1( #190 0# #195 1# b00000000000000000000000000010011 % 0& b00001001 ' 0( b00001001 ) #200 0# #205 1# b00000000000000000000000000010100 % 1& 1( b01011010 ) #210 0# #215 1# b00000000000000000000000000010101 % 0& b00001010 ' #220 0# #225 1# b00000000000000000000000000010110 % 1& 0( b10100101 ) #230 0# #235 1# b00000000000000000000000000010111 % 0& b00001011 ' #240 0# #245 1# b00000000000000000000000000011000 % 1& 1( b00001011 ) #250 0# #255 1# b00000000000000000000000000011001 % 0& b00001100 ' 0( b00001100 ) #260 0# #265 1# b00000000000000000000000000011010 % 1& 1( #270 0# #275 1# b00000000000000000000000000011011 % 0& b00001101 ' 0( b00001101 ) #280 0# #285 1# b00000000000000000000000000011100 % 1& 1( #290 0# #295 1# b00000000000000000000000000011101 % 0& b00001110 ' 0( b00001110 ) #300 0# #305 1# b00000000000000000000000000011110 % 1& 1( #310 0# #315 1# b00000000000000000000000000011111 % 0& b00001111 ' 0( b00001111 ) verilator-5.042/test_regress/t/t_gate_array.v0000644000542200017500000000533015101701376021717 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( input clk ); integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [7:0] a = crc[7:0]; wire [7:0] b = crc[15:8]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [63:0] out; // From test of Test.v wire [63:0] out2; // From test of Test.v // End of automatics Test test ( /*AUTOINST*/ // Outputs .out (out[63:0]), .out2 (out2[63:0]), // Inputs .clk (clk), .a (a[7:0]), .b (b[7:0])); // Aggregate outputs into a single result vector wire [63:0] result = {out}; // Test loop always @(posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc == 0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc < 10) begin sum <= 64'h0; end else if (cyc < 90) begin if (out2 !== out) $stop; end else if (cyc == 99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h0908a1f2194d24ee if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test ( input clk, input [7:0] a, input [7:0] b, output reg [63:0] out, output reg [63:0] out2 ); // Also cover comma syntax and u0a[7:0] (out[7:0], a[7:0], b[7:0]), u0b[7:0] (out2[7:0], a[7:0], b[7:0]); and u1a[7:0] (out[15:8], a[0], b[7:0]), u1b[7:0] (out2[15:8], a[0], b[7:0]); and u2a[7:0] (out[23:16], a[0], b[0]), u2b[7:0] (out2[23:16], a[0], b[0]); nand u3a[7:0] (out[31:24], a[0], b[7:0]), u3b[7:0] (out2[31:24], a[0], b[7:0]); or u4a[7:0] (out[39:32], a[0], b[7:0]), u4b[7:0] (out2[39:32], a[0], b[7:0]); nor u5a[7:0] (out[47:40], a[0], b[7:0]), u5b[7:0] (out2[47:40], a[0], b[7:0]); xor u6a[7:0] (out[55:48], a[0], b[7:0]), u6b[7:0] (out2[55:48], a[0], b[7:0]); xnor u7a[7:0] (out[63:56], a[0], b[7:0]), u7b[7:0] (out2[63:56], a[0], b[7:0]); endmodule verilator-5.042/test_regress/t/t_sys_file_basic_uz.dat0000644000542200017500000003600015101701376023576 0ustar mahmoudyfreeshell  !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~€‚ƒ„…†‡ˆ‰Š‹ŒŽ‘’“”•–—˜™š›œžŸ ¡¢£¤¥¦§¨©ª«¬­®¯°±²³´µ¶·¸¹º»¼½¾¿ÀÁÂÃÄÅÆÇÈÉÊËÌÍÎÏÐÑÒÓÔÕÖ×ØÙÚÛÜÝÞßàáâãäåæçèéêëìíîïðñòóôõö÷øùúûüýþÿ  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0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary --main-top-name '-' --trace-vcd -Wno-MULTITOP"]) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_randomize_complex_member_bad.v0000644000542200017500000000150015101701376025450 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class SubClass; rand bit [2:0] field; function new (); field = 0; endfunction endclass class MyClass; SubClass sc_inst2[2]; function new (); sc_inst2[1] = new; endfunction endclass; class Deep; MyClass sc_inst1; function new (); sc_inst1 = new; endfunction endclass; class WeNeedToGoDeeper; Deep sc_inst; function new (); sc_inst = new; endfunction endclass; module t; initial begin WeNeedToGoDeeper cl_inst[100]; cl_inst[1] = new; if (cl_inst[1].sc_inst.sc_inst2.sc_inst2[1].randomize() with {field inside {1, 2, 3};} == 0) begin $stop; end end endmodule verilator-5.042/test_regress/t/t_cover_expr_array_class.py0000755000542200017500000000100015101701376024514 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--coverage-expr']) test.execute() test.passes() verilator-5.042/test_regress/t/t_assigndly_dynamic.v0000644000542200017500000000303215101701376023277 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `ifdef WITH_DELAY `define DELAY #1 `define TIME_AFTER_FIRST_WAIT 2 `define TIME_AFTER_SECOND_WAIT 3 `else `define DELAY `define TIME_AFTER_FIRST_WAIT 1 `define TIME_AFTER_SECOND_WAIT 1 `endif class nba_waiter; // Task taken from UVM task wait_for_nba_region; static int nba; int next_nba; next_nba++; nba <= `DELAY next_nba; @(nba); endtask endclass class Foo; task bar(logic a, logic b); static int x; static int y; // bar's local vars and intravals could be overwritten by other locals if (a) x <= `DELAY 'hDEAD; if (b) y <= `DELAY 'hBEEF; #2 if (x != 'hDEAD) $stop; endtask endclass module t; nba_waiter waiter = new; Foo foo = new; event e; int cnt = 0; initial begin #1 ->e; if (cnt != 0) $stop; cnt++; waiter.wait_for_nba_region; ->e; if (cnt != 2) $stop; if ($time != `TIME_AFTER_FIRST_WAIT) $stop; cnt++; waiter.wait_for_nba_region; if (cnt != 4) $stop; if ($time != `TIME_AFTER_SECOND_WAIT) $stop; foo.bar(1, 1); #2 $write("*-* All Finished *-*\n"); $finish; end initial begin @e if (cnt != 1) $stop; cnt++; @e if (cnt != 3) $stop; cnt++; end endmodule verilator-5.042/test_regress/t/t_vams_kwd_bad.out0000644000542200017500000002374315101701376022574 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_vams_kwd_bad.v:12:8: Unsupported: AMS reserved word not implemented: 'above' 12 | int above; | ^~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: t/t_vams_kwd_bad.v:12:13: syntax error, unexpected ';', expecting '(' 12 | int above; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:13:8: Unsupported: AMS reserved word not implemented: 'abs' 13 | int abs; | ^~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:14:8: Unsupported: AMS reserved word not implemented: 'absdelay' 14 | int absdelay; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:15:8: Unsupported: AMS reserved word not implemented: 'abstol' 15 | int abstol; | ^~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:16:8: Unsupported: AMS reserved word not implemented: 'ac_stim' 16 | int ac_stim; | ^~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:17:8: Unsupported: AMS reserved word not implemented: 'access' 17 | int access; | ^~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:18:8: Unsupported: AMS reserved word not implemented: 'acos' 18 | int acos; | ^~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:19:8: Unsupported: AMS reserved word not implemented: 'acosh' 19 | int acosh; | ^~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:20:8: Unsupported: AMS reserved word not implemented: 'aliasparam' 20 | int aliasparam; | ^~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:21:8: Unsupported: AMS reserved word not implemented: 'analog' 21 | int analog; | ^~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:22:8: Unsupported: AMS reserved word not implemented: 'analysis' 22 | int analysis; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:23:8: Unsupported: AMS reserved word not implemented: 'assert' 23 | int assert; | ^~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:24:8: Unsupported: AMS reserved word not implemented: 'branch' 24 | int branch; | ^~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:25:8: Unsupported: AMS reserved word not implemented: 'connect' 25 | int connect; | ^~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:26:8: Unsupported: AMS reserved word not implemented: 'connectmodule' 26 | int connectmodule; | ^~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:27:8: Unsupported: AMS reserved word not implemented: 'connectrules' 27 | int connectrules; | ^~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:28:8: Unsupported: AMS reserved word not implemented: 'continuous' 28 | int continuous; | ^~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:29:8: Unsupported: AMS reserved word not implemented: 'cross' 29 | int cross; | ^~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:30:8: Unsupported: AMS reserved word not implemented: 'ddt' 30 | int ddt; | ^~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:31:8: Unsupported: AMS reserved word not implemented: 'ddt_nature' 31 | int ddt_nature; | ^~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:32:8: Unsupported: AMS reserved word not implemented: 'ddx' 32 | int ddx; | ^~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:33:8: Unsupported: AMS reserved word not implemented: 'discipline' 33 | int discipline; | ^~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:34:8: Unsupported: AMS reserved word not implemented: 'discrete' 34 | int discrete; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:35:8: Unsupported: AMS reserved word not implemented: 'domain' 35 | int domain; | ^~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:36:8: Unsupported: AMS reserved word not implemented: 'driver_update' 36 | int driver_update; | ^~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:37:8: Unsupported: AMS reserved word not implemented: 'endconnectrules' 37 | int endconnectrules; | ^~~~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:38:8: Unsupported: AMS reserved word not implemented: 'enddiscipline' 38 | int enddiscipline; | ^~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:39:8: Unsupported: AMS reserved word not implemented: 'endnature' 39 | int endnature; | ^~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:40:8: Unsupported: AMS reserved word not implemented: 'endparamset' 40 | int endparamset; | ^~~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:41:8: Unsupported: AMS reserved word not implemented: 'exclude' 41 | int exclude; | ^~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:42:8: Unsupported: AMS reserved word not implemented: 'final_step' 42 | int final_step; | ^~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:43:8: Unsupported: AMS reserved word not implemented: 'flicker_noise' 43 | int flicker_noise; | ^~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:44:8: Unsupported: AMS reserved word not implemented: 'flow' 44 | int flow; | ^~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:45:8: Unsupported: AMS reserved word not implemented: 'from' 45 | int from; | ^~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:46:8: Unsupported: AMS reserved word not implemented: 'ground' 46 | int ground; | ^~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:47:8: Unsupported: AMS reserved word not implemented: 'idt' 47 | int idt; | ^~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:48:8: Unsupported: AMS reserved word not implemented: 'idt_nature' 48 | int idt_nature; | ^~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:49:8: Unsupported: AMS reserved word not implemented: 'idtmod' 49 | int idtmod; | ^~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:50:8: Unsupported: AMS reserved word not implemented: 'inf' 50 | int inf; | ^~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:51:8: Unsupported: AMS reserved word not implemented: 'initial_step' 51 | int initial_step; | ^~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:52:8: Unsupported: AMS reserved word not implemented: 'laplace_nd' 52 | int laplace_nd; | ^~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:53:8: Unsupported: AMS reserved word not implemented: 'laplace_np' 53 | int laplace_np; | ^~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:54:8: Unsupported: AMS reserved word not implemented: 'laplace_zd' 54 | int laplace_zd; | ^~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:55:8: Unsupported: AMS reserved word not implemented: 'laplace_zp' 55 | int laplace_zp; | ^~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:56:8: Unsupported: AMS reserved word not implemented: 'last_crossing' 56 | int last_crossing; | ^~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:57:8: Unsupported: AMS reserved word not implemented: 'limexp' 57 | int limexp; | ^~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:58:8: Unsupported: AMS reserved word not implemented: 'max' 58 | int max; | ^~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:59:8: Unsupported: AMS reserved word not implemented: 'merged' 59 | int merged; | ^~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:60:8: Unsupported: AMS reserved word not implemented: 'min' 60 | int min; | ^~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:61:8: Unsupported: AMS reserved word not implemented: 'nature' 61 | int nature; | ^~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:62:8: Unsupported: AMS reserved word not implemented: 'net_resolution' 62 | int net_resolution; | ^~~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:63:8: Unsupported: AMS reserved word not implemented: 'noise_table' 63 | int noise_table; | ^~~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:64:8: Unsupported: AMS reserved word not implemented: 'paramset' 64 | int paramset; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:65:8: Unsupported: AMS reserved word not implemented: 'potential' 65 | int potential; | ^~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:66:8: Unsupported: AMS reserved word not implemented: 'resolveto' 66 | int resolveto; | ^~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:67:8: Unsupported: AMS reserved word not implemented: 'slew' 67 | int slew; | ^~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:68:8: Unsupported: AMS reserved word not implemented: 'split' 68 | int split; | ^~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:69:8: Unsupported: AMS reserved word not implemented: 'timer' 69 | int timer; | ^~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:70:8: Unsupported: AMS reserved word not implemented: 'transition' 70 | int transition; | ^~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:71:8: Unsupported: AMS reserved word not implemented: 'units' 71 | int units; | ^~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:72:8: Unsupported: AMS reserved word not implemented: 'white_noise' 72 | int white_noise; | ^~~~~~~~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:73:8: Unsupported: AMS reserved word not implemented: 'zi_nd' 73 | int zi_nd; | ^~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:74:8: Unsupported: AMS reserved word not implemented: 'zi_np' 74 | int zi_np; | ^~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:75:8: Unsupported: AMS reserved word not implemented: 'zi_zd' 75 | int zi_zd; | ^~~~~ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:76:8: Unsupported: AMS reserved word not implemented: 'zi_zp' 76 | int zi_zp; | ^~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_tri_gate_bufif0.py0000755000542200017500000000136515101701376023024 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_tri_gate.cpp" test.top_filename = "t/t_tri_gate.v" test.compile(make_top_shell=False, make_main=False, v_flags2=['+define+T_BUFIF0'], make_flags=['CPPFLAGS_ADD=-DT_BUFIF0'], verilator_flags2=["--exe", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_strength_equal_strength.v0000644000542200017500000000227315101701376024547 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 interface inter #(parameter W) (input logic cond, output wire a); // Example: wire (weak0, weak1) [W-1:0] b = '1; assign (strong0, strong1) b = cond ? 'b0 : 'bz; assign a = b[10]; endinterface module t (clk1, clk2); input wire clk1; input wire clk2; wire (weak0, weak1) a = 0; assign (supply0, supply1) a = 1'bz; assign (pull0, pull1) a = 1; wire [2:0] b; assign b = 3'b101; assign (supply0, supply1) b = 3'b01z; wire c; and (weak0, weak1) (c, clk1, clk2); assign (strong0, strong1) c = 'z; assign (pull0, pull1) c = 0; wire d; inter #(.W(32)) i(.cond(1'b1), .a(d)); always begin if (a === 1 && b === 3'b011 && c === 0 && d === 0) begin $write("*-* All Finished *-*\n"); $finish; end else begin $write("Error: a = %b, b = %b, c = %b, d = %b", a, b, c, d); $write("expected: a = %b, b = %b, c = %b, d = %b\n", clk1, 3'b011, 0, 0); $stop; end end endmodule verilator-5.042/test_regress/t/t_constraint_assoc_arr_others.py0000755000542200017500000000104615101701376025573 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_cover_expr_queue_class.v0000644000542200017500000000111415101701376024342 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Class1; int value0 = 7; endclass module t; initial begin int i = 0; Class1 q[$]; repeat(15) begin Class1 x = new; q = { q, x }; end while (i < q.size()) begin if ((q[i].value0 > 8) || (q[i].value0 < 5)) $stop; i += 1; end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_process_copy_constr.py0000755000542200017500000000077115101701376024073 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--timing"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_strength_highz.v0000644000542200017500000000101615101701376022625 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; wire (weak0, highz1) a = 1; wire (strong1, highz0) b = 0; wire (highz0, pull1) c = 0; wire (highz1, supply0) d = 1; always begin if (a === 1'bz && b === 1'bz && c === 1'bz && d === 1'bz) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_lint_implicit.v0000644000542200017500000000061515101701376022442 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (a,z); input a; output z; assign b = 1'b1; or OR0 (nt0, a, b); logic [1:0] dummy_ip; assign {dummy1, dummy2} = dummy_ip; assign z = nt0; endmodule verilator-5.042/test_regress/t/t_class_param_extra_bad.v0000644000542200017500000000053715101701376024103 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; class Cls1; typedef bit bool_t; endclass localparam Cls1#(123, integer, "text")::bool_t PARAM = 1; endmodule verilator-5.042/test_regress/t/t_vpi_put_value_array.py0000755000542200017500000000141615101701376024050 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(make_top_shell=False, make_main=False, make_pli=True, verilator_flags2=["--exe --vpi --no-l2name", test.pli_filename], iv_flags2=["-g2005-sv -D USE_VPI_NOT_DPI"], v_flags2=["+define+USE_VPI_NOT_DPI +define+VERILATOR_COMMENTS"]) test.execute(use_libvpi=True) test.passes() verilator-5.042/test_regress/t/t_struct_contents.py0000755000542200017500000000073415101701376023233 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_var_overzero.v0000644000542200017500000000735715101701376022337 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs dout, // Inputs clk, rstn, dval0, dval1 ); input clk; input rstn; output wire [7:0] dout; input [7:0] dval0; input [7:0] dval1; wire [7:0] dbgsel_w = '0; tsub tsub (/*AUTOINST*/ // Outputs .dout (dout[7:0]), // Inputs .clk (clk), .rstn (rstn), .dval0 (dval0[7:0]), .dval1 (dval1[7:0]), .dbgsel_w (dbgsel_w[7:0])); endmodule module tsub (/*AUTOARG*/ // Outputs dout, // Inputs clk, rstn, dval0, dval1, dbgsel_w ); input clk; input rstn; input [7:0] dval0; input [7:0] dval1; input [7:0] dbgsel_w; output [7:0] dout; wire [7:0] dout = dout0 | dout1; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [7:0] dout0; // From sub0 of sub0.v wire [7:0] dout1; // From sub1 of sub1.v // End of automatics initial begin $write("*-* All Finished *-*\n"); $finish; end reg [7:0] dbgsel_msk; always_comb begin reg [7:0] mask; mask = 8'hff; dbgsel_msk = (dbgsel_w & mask); end // TODO this should optimize away, but presently does not because // V3Gate constifies then doesn't see all other input edges have disappeared reg [7:0] dbgsel; always @(posedge clk) begin if ((rstn == 0)) begin dbgsel <= 0; end else begin dbgsel <= dbgsel_msk; end end sub0 sub0 (/*AUTOINST*/ // Outputs .dout0 (dout0[7:0]), // Inputs .rstn (rstn), .clk (clk), .dval0 (dval0[7:0]), .dbgsel (dbgsel[7:0])); sub1 sub1 (/*AUTOINST*/ // Outputs .dout1 (dout1[7:0]), // Inputs .rstn (rstn), .clk (clk), .dval1 (dval1[7:0]), .dbgsel (dbgsel[7:0])); endmodule module sub0 ( /*AUTOARG*/ // Outputs dout0, // Inputs rstn, clk, dval0, dbgsel ); input rstn; input clk; input [7:0] dval0; input [7:0] dbgsel; output reg [7:0] dout0; reg [7:0] dbgsel_d1r; always_comb begin // verilator lint_off WIDTH if (((dbgsel_d1r >= 34) && (dbgsel_d1r < 65))) begin // verilator lint_on WIDTH dout0 = dval0; end else begin dout0 = 0; end end always @(posedge clk) begin if ((rstn == 0)) begin dbgsel_d1r <= 0; end else begin dbgsel_d1r <= dbgsel; end end endmodule module sub1 ( /*AUTOARG*/ // Outputs dout1, // Inputs rstn, clk, dval1, dbgsel ); input rstn; input clk; input [7:0] dval1; input [7:0] dbgsel; output reg [7:0] dout1; reg [7:0] dbgsel_d1r; always_comb begin if (((dbgsel_d1r >= 84) && (dbgsel_d1r < 95))) begin dout1 = dval1; end else begin dout1 = 0; end end always @(posedge clk) begin if ((rstn == 0)) begin dbgsel_d1r <= 0; end else begin dbgsel_d1r <= dbgsel; end end endmodule verilator-5.042/test_regress/t/t_sc_vl_assign_sbw.v0000644000542200017500000000143215101701376023125 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2024 by Antmicro. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t( input [255:0] in, output [255:0] out ); // do not optimize assignment logic tmp = $c(0); typedef logic[255:0] biguint; assign out = in + biguint'(tmp); always @(out) begin if (in !== 1) begin $write("'in' mismatch: (1 !== %d)\n", logic'(in)); $stop; end else if (out !== 1) begin $write("'out' mismatch: (1 !== %d)\n", logic'(out)); $stop; end end endmodule verilator-5.042/test_regress/t/t_param_concat.py0000755000542200017500000000100215101701376022406 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--Wno-WIDTHCONCAT"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_mod_longname.py0000755000542200017500000000073415101701376022431 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_extends_aliased_real_bad.v0000644000542200017500000000056515101701376025740 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; class bar #(type T) extends T; endclass typedef real real_t; bar #(real_t) bar_real_t; initial begin $stop; end endmodule verilator-5.042/test_regress/t/t_func_no_paren.py0000755000542200017500000000070615101701376022605 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.042/test_regress/t/t_checker_top.py0000755000542200017500000000074315101701376022260 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["--assert"]) test.passes() verilator-5.042/test_regress/t/t_implements_missing_bad.v0000644000542200017500000000072515101701376024320 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface class Icls1; pure virtual function int icf1; pure virtual function int icf2; endclass class Cls implements Icls1; virtual function int icf1; return 1; endfunction // Bad missing icf2 endclass module t; Cls c; endmodule verilator-5.042/test_regress/t/t_force_input_assign_bad.v0000644000542200017500000000107715101701376024274 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module sub(input [1:0] i); endmodule module t; sub s1(1); sub s2(1); sub s3(1); sub s4(1); sub s5(1); initial begin // these should fail s1.i = 2; force s1.i = '1; s2.i = 2; release s2.i; force s3.i = '1; assign s3.i = 2; // these should not force s4.i = '1; release s5.i; end endmodule verilator-5.042/test_regress/t/t_flag_values_bad.py0000755000542200017500000000121415101701376023062 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=[ "--output-split-cfuncs -1", "--output-split-ctrace -1", "--preproc-token-limit 0", "--reloop-limit -1" ], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_struct_packed_write_read.v0000644000542200017500000001255315101701376024646 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2009 by Iztok Jeras. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; localparam NO = 10; // number of access events // packed structures struct packed { logic e0; logic [1:0] e1; logic [3:0] e2; logic [7:0] e3; } struct_dsc; // descending range structure /* verilator lint_off ASCRANGE */ struct packed { logic e0; logic [0:1] e1; logic [0:3] e2; logic [0:7] e3; } struct_asc; // ascending range structure /* verilator lint_on ASCRANGE */ localparam WS = 15; // $bits(struct_dsc) integer cnt = 0; // event counter always @ (posedge clk) begin cnt <= cnt + 1; end // finish report always @ (posedge clk) if ((cnt[30:2]==NO) && (cnt[1:0]==2'd0)) begin $write("*-* All Finished *-*\n"); $finish; end // descending range always @ (posedge clk) if (cnt[1:0]==2'd0) begin // initialize to defaaults (all bits to 0) if (cnt[30:2]==0) struct_dsc <= '0; else if (cnt[30:2]==1) struct_dsc <= '0; else if (cnt[30:2]==2) struct_dsc <= '0; else if (cnt[30:2]==3) struct_dsc <= '0; else if (cnt[30:2]==4) struct_dsc <= '0; else if (cnt[30:2]==5) struct_dsc <= '0; end else if (cnt[1:0]==2'd1) begin // write value to structure if (cnt[30:2]==0) begin end else if (cnt[30:2]==1) struct_dsc <= '1; else if (cnt[30:2]==2) struct_dsc.e0 <= '1; else if (cnt[30:2]==3) struct_dsc.e1 <= '1; else if (cnt[30:2]==4) struct_dsc.e2 <= '1; else if (cnt[30:2]==5) struct_dsc.e3 <= '1; end else if (cnt[1:0]==2'd2) begin // check structure value if (cnt[30:2]==0) begin if (struct_dsc !== 15'b000000000000000) begin $display("%b", struct_dsc); $stop(); end end else if (cnt[30:2]==1) begin if (struct_dsc !== 15'b111111111111111) begin $display("%b", struct_dsc); $stop(); end end else if (cnt[30:2]==2) begin if (struct_dsc !== 15'b100000000000000) begin $display("%b", struct_dsc); $stop(); end end else if (cnt[30:2]==3) begin if (struct_dsc !== 15'b011000000000000) begin $display("%b", struct_dsc); $stop(); end end else if (cnt[30:2]==4) begin if (struct_dsc !== 15'b000111100000000) begin $display("%b", struct_dsc); $stop(); end end else if (cnt[30:2]==5) begin if (struct_dsc !== 15'b000000011111111) begin $display("%b", struct_dsc); $stop(); end end end else if (cnt[1:0]==2'd3) begin // read value from structure (not a very good test for now) if (cnt[30:2]==0) begin if (struct_dsc !== {WS{1'b0}}) $stop(); end else if (cnt[30:2]==1) begin if (struct_dsc !== {WS{1'b1}}) $stop(); end else if (cnt[30:2]==2) begin if (struct_dsc.e0 !== { 1{1'b1}}) $stop(); end else if (cnt[30:2]==3) begin if (struct_dsc.e1 !== { 2{1'b1}}) $stop(); end else if (cnt[30:2]==4) begin if (struct_dsc.e2 !== { 4{1'b1}}) $stop(); end else if (cnt[30:2]==5) begin if (struct_dsc.e3 !== { 8{1'b1}}) $stop(); end end // ascending range always @ (posedge clk) if (cnt[1:0]==2'd0) begin // initialize to defaaults (all bits to 0) if (cnt[30:2]==0) struct_asc <= '0; else if (cnt[30:2]==1) struct_asc <= '0; else if (cnt[30:2]==2) struct_asc <= '0; else if (cnt[30:2]==3) struct_asc <= '0; else if (cnt[30:2]==4) struct_asc <= '0; else if (cnt[30:2]==5) struct_asc <= '0; end else if (cnt[1:0]==2'd1) begin // write value to structure if (cnt[30:2]==0) begin end else if (cnt[30:2]==1) struct_asc <= '1; else if (cnt[30:2]==2) struct_asc.e0 <= '1; else if (cnt[30:2]==3) struct_asc.e1 <= '1; else if (cnt[30:2]==4) struct_asc.e2 <= '1; else if (cnt[30:2]==5) struct_asc.e3 <= '1; end else if (cnt[1:0]==2'd2) begin // check structure value if (cnt[30:2]==0) begin if (struct_asc !== 15'b000000000000000) begin $display("%b", struct_asc); $stop(); end end else if (cnt[30:2]==1) begin if (struct_asc !== 15'b111111111111111) begin $display("%b", struct_asc); $stop(); end end else if (cnt[30:2]==2) begin if (struct_asc !== 15'b100000000000000) begin $display("%b", struct_asc); $stop(); end end else if (cnt[30:2]==3) begin if (struct_asc !== 15'b011000000000000) begin $display("%b", struct_asc); $stop(); end end else if (cnt[30:2]==4) begin if (struct_asc !== 15'b000111100000000) begin $display("%b", struct_asc); $stop(); end end else if (cnt[30:2]==5) begin if (struct_asc !== 15'b000000011111111) begin $display("%b", struct_asc); $stop(); end end end else if (cnt[1:0]==2'd3) begin // read value from structure (not a very good test for now) if (cnt[30:2]==0) begin if (struct_asc !== {WS{1'b0}}) $stop(); end else if (cnt[30:2]==1) begin if (struct_asc !== {WS{1'b1}}) $stop(); end else if (cnt[30:2]==2) begin if (struct_asc.e0 !== { 1{1'b1}}) $stop(); end else if (cnt[30:2]==3) begin if (struct_asc.e1 !== { 2{1'b1}}) $stop(); end else if (cnt[30:2]==4) begin if (struct_asc.e2 !== { 4{1'b1}}) $stop(); end else if (cnt[30:2]==5) begin if (struct_asc.e3 !== { 8{1'b1}}) $stop(); end end endmodule verilator-5.042/test_regress/t/t_define_override_empty.py0000755000542200017500000000133015101701376024332 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.top_filename = "t/t_define_override.v" #test.lint(verilator_flags2=["+define+TEST_MACRO"], fails=True, expect_filename=test.golden_filename) test.compile(verilator_flags2=["-Wno-DEFOVERRIDE -Wno-REDEFMACRO +define+TEST_MACRO"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_type_param_collision.py0000755000542200017500000000105115101701376024177 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_type_param.v" test.compile(verilator_flags2=["--debug-collision"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_unopt_converge_print_bad.py0000755000542200017500000000133315101701376025045 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_unopt_converge.v" #test.verilated_debug = 1 test.compile(v_flags2=['+define+ALLOW_UNOPT', '--output-split 0', "-fno-dfg"], make_flags=['CPPFLAGS_ADD=-DVL_DEBUG']) if test.vlt_all: test.execute(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_enum_recurse_bad2.out0000644000542200017500000000044115101701376023525 0ustar mahmoudyfreeshell%Error: t/t_enum_recurse_bad2.v:8:14: Self-referential enumerated type definition 8 | typedef enum foo_t { A = 'b0, B = 'b1 } foo_t; | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_opt_dead.v0000644000542200017500000000105015101701376021353 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class EmptyClass_Dead; endclass module Mod_Dead; class ModClass_Dead; int memberb_dead; endclass endmodule //TODO dead check with class extends module t; generate if (0) begin Mod_Dead cell_dead(); end endgenerate initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_trace_array_fst_portable_sc.py0000755000542200017500000000143215101701376025513 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_trace_array.v" test.golden_filename = "t/t_trace_array_fst_sc.out" if not test.have_sc: test.skip("No SystemC installed") test.compile(verilator_flags2=[ '--sc --trace-fst --trace-structs --trace-max-width 0', '-CFLAGS -DVL_PORTABLE_ONLY' ]) test.execute() test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dpi_export_scope_bad.py0000755000542200017500000000106415101701376024143 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=["--binary", test.pli_filename]) test.execute(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_hier_block_type_param_nested.py0000755000542200017500000000077715101701376025665 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--hierarchical']) test.execute() test.passes() verilator-5.042/test_regress/t/t_bind2.py0000755000542200017500000000073415101701376020770 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_style_bad.out0000644000542200017500000000433615101701376023144 0ustar mahmoudyfreeshell%Warning-DECLFILENAME: t/t_lint_style_bad.v:7:8: Filename 't_lint_style_bad' does not match MODULE name: 't' 7 | module t; | ^ ... For warning description see https://verilator.org/warn/DECLFILENAME?v=latest ... Use "/* verilator lint_off DECLFILENAME */" and lint_on around source to disable this message. %Warning-VARHIDDEN: t/t_lint_style_bad.v:12:14: Declaration of signal hides declaration in upper scope: 'top' 12 | output top; | ^~~ t/t_lint_style_bad.v:9:12: ... Location of original declaration 9 | integer top; | ^~~ ... For warning description see https://verilator.org/warn/VARHIDDEN?v=latest ... Use "/* verilator lint_off VARHIDDEN */" and lint_on around source to disable this message. %Warning-VARHIDDEN: t/t_lint_style_bad.v:18:18: Declaration of signal hides declaration in upper scope: 'top' 18 | integer top; | ^~~ t/t_lint_style_bad.v:9:12: ... Location of original declaration 9 | integer top; | ^~~ %Warning-UNUSEDSIGNAL: t/t_lint_style_bad.v:9:12: Signal is not driven, nor used: 'top' : ... note: In instance 't' 9 | integer top; | ^~~ ... For warning description see https://verilator.org/warn/UNUSEDSIGNAL?v=latest ... Use "/* verilator lint_off UNUSEDSIGNAL */" and lint_on around source to disable this message. %Warning-UNDRIVEN: t/t_lint_style_bad.v:12:14: Signal is not driven: 'top' : ... note: In instance 't' 12 | output top; | ^~~ ... For warning description see https://verilator.org/warn/UNDRIVEN?v=latest ... Use "/* verilator lint_off UNDRIVEN */" and lint_on around source to disable this message. %Warning-UNUSEDSIGNAL: t/t_lint_style_bad.v:18:18: Signal is not driven, nor used: 'top' : ... note: In instance 't' 18 | integer top; | ^~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_timing_intra_assign_nolocalize.py0000755000542200017500000000115415101701376026236 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_timing_intra_assign.v" test.golden_filename = "t/t_timing_intra_assign.out" test.compile(verilator_flags2=["--binary -fno-localize"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_net_delay.py0000755000542200017500000000110715101701376021731 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.lint(verilator_flags2=['-Wall -Wno-DECLFILENAME --no-timing'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_static_order.v0000644000542200017500000000224215101701376023447 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class ClsZ; function new(); $display("ClsZ::new"); endfunction endclass class ClsA; function new(); $display("ClsA::new"); endfunction function void access; $display("ClsA::access"); endfunction endclass class ClsB; static ClsZ z = new; function new(); $display("ClsB::new"); endfunction function void access; $display("ClsB::access"); endfunction endclass class ClsC; // Elaboration will call these static ClsA a = new; static ClsB b = new; function new(); $display("ClsC::new"); endfunction function void access; $display("ClsC::access"); a = new; a.access; endfunction endclass module t; function void makec; ClsC c; $display("c = new;"); c = new; $display("c.access;"); c.access; endfunction initial begin $display("makec;"); makec; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_queue_concat_assign.py0000755000542200017500000000073415101701376024011 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_static_member_sel.py0000755000542200017500000000073415101701376024640 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_math_svl.v0000644000542200017500000001037515101701376021423 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [15:0] l; reg [49:0] q; reg [79:0] w; int lc; reg lo; reg l0; int qc; reg qo; reg q0; int wc; reg wo; reg w0; always @* begin lc = $countones(l); lo = $onehot(l); l0 = $onehot0(l); wc = $countones(w); wo = $onehot(w); w0 = $onehot0(w); qc = $countones(q); qo = $onehot(q); q0 = $onehot0(q); end integer cyc; initial cyc=1; integer cyc_com; always_comb begin cyc_com = cyc; end integer cyc_d1; always_ff @ (posedge clk) begin cyc_d1 <= cyc_com; end initial begin // Constification check if ($countones(32'b11001011101) != 7) $stop; if ($countones(32'b0) != 0) $stop; if ($isunknown(32'b11101x11111) != 1) $stop; if ($isunknown(32'b11101011111) != 0) $stop; if ($isunknown(32'b10zzzzzzzzz) != 1) $stop; if ($bits(0) != 32'd32) $stop; if ($bits(lc) != 32) $stop; if ($onehot(32'b00000001000000) != 1'b1) $stop; if ($onehot(32'b00001001000000) != 1'b0) $stop; if ($onehot(32'b0) != 1'b0) $stop; if ($onehot0(32'b00000001000000) != 1'b1) $stop; if ($onehot0(32'b00001001000000) != 1'b0) $stop; if ($onehot0(32'b0) != 1'b1) $stop; end always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; //$write("%d %x %d %x %x %x %d %x %x %x %d %x %x\n", // cyc, l, lc, lo, l0, q,qc,qo,q0, w,wc,wo,w0); if (cyc_com != cyc_com) $stop; if (cyc_d1 != cyc-1) $stop; if (cyc==1) begin l <= 16'b0; q <= 50'h0; w <= 80'h0; end if (cyc==2) begin l <= ~16'b0; q <= ~50'h0; w <= ~80'h0; // if ({lc,lo,l0} != {32'd0,1'b0,1'b1}) $stop; if ({qc,qo,q0} != {32'd0,1'b0,1'b1}) $stop; if ({wc,wo,w0} != {32'd0,1'b0,1'b1}) $stop; end if (cyc==3) begin l <= 16'b0010110010110111; q <= 50'h01_1111_0001; w <= 80'h0100_0000_0f00_00f0_0000; // if ({lc,lo,l0} != {32'd16,1'b0,1'b0}) $stop; if ({qc,qo,q0} != {32'd50,1'b0,1'b0}) $stop; if ({wc,wo,w0} != {32'd80,1'b0,1'b0}) $stop; end if (cyc==4) begin l <= 16'b0000010000000000; q <= 50'h1_0000_0000; w <= 80'h010_00000000_00000000; // if ({lc,lo,l0} != {32'd9,1'b0,1'b0}) $stop; if ({qc,qo,q0} != {32'd6,1'b0,1'b0}) $stop; if ({wc,wo,w0} != {32'd9,1'b0,1'b0}) $stop; end if (cyc==5) begin l <= 16'b0000000100000000; q <= 50'h8000_0000_0000; w <= 80'h10_00000000_00000000; // if ({lc,lo,l0} != {32'd1,1'b1,1'b1}) $stop; if ({qc,qo,q0} != {32'd1,1'b1,1'b1}) $stop; if ({wc,wo,w0} != {32'd1,1'b1,1'b1}) $stop; end if (cyc==6) begin l <= 16'b0000100100000000; q <= 50'h01_00000100; w <= 80'h01_00000100_00000000; // if ({lc,lo,l0} != {32'd1,1'b1,1'b1}) $stop; if ({qc,qo,q0} != {32'd1,1'b1,1'b1}) $stop; if ({wc,wo,w0} != {32'd1,1'b1,1'b1}) $stop; end if (cyc==7) begin // if ({lc,lo,l0} != {32'd2,1'b0,1'b0}) $stop; if ({qc,qo,q0} != {32'd2,1'b0,1'b0}) $stop; if ({wc,wo,w0} != {32'd2,1'b0,1'b0}) $stop; end if (cyc==8) begin end if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end end initial begin if ($isunknown(4'b000x) !== 1'b1) $stop; if ($isunknown(4'b000z) !== 1'b1) $stop; if ($isunknown(4'b00xz) !== 1'b1) $stop; if ($isunknown(4'b0000) !== 1'b0) $stop; end final begin $write("Goodbye world, at cycle %0d\n", cyc); end endmodule verilator-5.042/test_regress/t/t_trace_primitive.v0000644000542200017500000000142515101701376022770 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014 by Jie Xu. // SPDX-License-Identifier: CC0-1.0 module t ( clk ); input clk; integer cyc; initial cyc = 0; reg a; reg b; reg z; sub_t sub_t_i (z, a, b); always @ (posedge clk) begin cyc <= cyc + 1; a <= cyc[0]; b <= cyc[1]; if (cyc > 10) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule primitive CINV (a, b); output b; input a; `ifdef VERILATOR assign b = ~a; `else table //b a 0 : ? : 1; 1 : ? : 0; endtable `endif endprimitive module sub_t (z, x, y); input x, y; output z; assign z = x & y; endmodule verilator-5.042/test_regress/t/t_sys_monitor_dotted.v0000644000542200017500000000415115101701376023531 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface addsub_ifc; logic [7:0] a, b; logic doAdd0; logic clk; logic rst_n; logic [7:0] result; logic overflow; endinterface module adder_sub_8bit ( input logic clk, input logic rst_n, input logic [7:0] a, input logic [7:0] b, input logic doAdd0, output logic [7:0] result, output logic overflow ); logic [7:0] b_modified; logic [8:0] temp_result; assign b_modified = doAdd0 ? b : ~b + 8'b1; always_comb begin temp_result = {1'b0, a} + {1'b0, b_modified}; end always_ff @(posedge clk or negedge rst_n) begin if (!rst_n) begin result <= 8'h0; overflow <= 1'b0; end else begin result <= temp_result[7:0]; overflow <= (a[7] == b_modified[7] && result[7] != a[7]); end end endmodule module t; addsub_ifc dut_ifc(); adder_sub_8bit dut ( .clk(dut_ifc.clk), .rst_n(dut_ifc.rst_n), .a(dut_ifc.a), .b(dut_ifc.b), .doAdd0(dut_ifc.doAdd0), .result(dut_ifc.result), .overflow(dut_ifc.overflow) ); initial begin dut_ifc.clk = 0; forever #5 dut_ifc.clk = ~dut_ifc.clk; end initial begin dut_ifc.rst_n = 0; dut_ifc.a = 8'h0; dut_ifc.b = 8'h0; dut_ifc.doAdd0 = 1'b1; #10 dut_ifc.rst_n = 1; #10; dut_ifc.a = 8'h35; dut_ifc.b = 8'h42; dut_ifc.doAdd0 = 1'b1; #20; $write("*-* All Finished *-*\n"); $finish; end initial begin $display("[%0t] Initial rst_n=%b a=%h b=%h doAdd0=%b result=%h overflow=%b", $time, dut_ifc.rst_n, dut_ifc.a, dut_ifc.b, dut_ifc.doAdd0, dut_ifc.result, dut_ifc.overflow); $monitor("[%0t] Monitor rst_n=%b a=%h b=%h doAdd0=%b result=%h overflow=%b", $time, dut_ifc.rst_n, dut_ifc.a, dut_ifc.b, dut_ifc.doAdd0, dut_ifc.result, dut_ifc.overflow); end endmodule verilator-5.042/test_regress/t/t_delay_timing.py0000755000542200017500000000114415101701376022433 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_delay.v" test.main_time_multiplier = 10e-7 / 10e-9 test.compile(timing_loop=True, verilator_flags2=['--timing -Wno-ZERODLY']) test.execute() test.passes() verilator-5.042/test_regress/t/t_static_dup_name.v0000644000542200017500000000122715101701376022741 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; function void do_stuff(); static int some_int; begin: block0 static int some_int; end begin: block1 static int some_int; end begin static int some_int; end begin: block2 begin: block3 static int some_int; end begin static int some_int; end end endfunction initial begin $write("*-* All Finished *-*\n"); $finish(); end endmodule verilator-5.042/test_regress/t/t_inside_nonint.v0000644000542200017500000000140715101701376022442 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 function bit check_string(string s); if (s inside {"RW", "WO"}) return 1'b1; return 1'b0; endfunction function bit check_double(real d); if (d inside {0.0, 2.5}) return 1'b1; return 1'b0; endfunction module t(); initial begin if (!check_string("WO")) $stop; if (!check_string("RW")) $stop; if (check_string("ABC")) $stop; if (!check_double(0.0)) $stop; if (!check_double(2.5)) $stop; if (check_double(1.0)) $stop; $display("*-* All Finished *-*"); $finish; end endmodule verilator-5.042/test_regress/t/t_pgo_profoutofdate_bad.v0000644000542200017500000000117315101701376024136 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; // Test loop always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule `verilator_config profile_data -model "x" -mtask "h7baded98__0" -cost 64'd12345678901234567890 profile_data -model "x" -mtask "hb56134bd__0" -cost 945 verilator-5.042/test_regress/t/t_event_control_timing.out0000644000542200017500000000004715101701376024373 0ustar mahmoudyfreeshell[10] Got [15] Got *-* All Finished *-* verilator-5.042/test_regress/t/t_lint_defparam.py0000755000542200017500000000070315101701376022573 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint() test.passes() verilator-5.042/test_regress/t/t_var_ref_static.py0000755000542200017500000000076315101701376022767 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_bitsel_over32.py0000755000542200017500000000075415101701376022456 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--trace-vcd']) test.passes() verilator-5.042/test_regress/t/t_lint_ftask_output_assign_bad.out0000644000542200017500000000156515101701376026101 0ustar mahmoudyfreeshell%Error-PROCASSWIRE: t/t_lint_ftask_output_assign_bad.v:21:11: Passed wire on output or inout subroutine argument, expected expression that is valid on the left hand side of a procedural assignment (IEEE 1800-2023 13.5): 'wire_out' : ... note: In instance 't' 21 | set_f(wire_out, in); | ^~~~~~~~ ... For error description see https://verilator.org/warn/PROCASSWIRE?v=latest %Error-PROCASSWIRE: t/t_lint_ftask_output_assign_bad.v:23:14: Passed wire on output or inout subroutine argument, expected expression that is valid on the left hand side of a procedural assignment (IEEE 1800-2023 13.5): 'wire_out' : ... note: In instance 't' 23 | set_task(wire_out, in); | ^~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_lint_historical.v0000644000542200017500000001042115101701376022765 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; // Test all warnings, including those that are historically removed still parse // verilator lint_off ALWCOMBORDER // verilator lint_off ALWNEVER // verilator lint_off ASCRANGE // verilator lint_off ASSIGNDLY // verilator lint_off ASSIGNEQEXPR // verilator lint_off ASSIGNIN // verilator lint_off BADSTDPRAGMA // verilator lint_off BADVLTPRAGMA // verilator lint_off BLKANDNBLK // verilator lint_off BLKLOOPINIT // verilator lint_off BLKSEQ // verilator lint_off BSSPACE // verilator lint_off CASEINCOMPLETE // verilator lint_off CASEOVERLAP // verilator lint_off CASEWITHX // verilator lint_off CASEX // verilator lint_off CASTCONST // verilator lint_off CDCRSTLOGIC // verilator lint_off CLKDATA // verilator lint_off CMPCONST // verilator lint_off COLONPLUS // verilator lint_off COMBDLY // verilator lint_off CONSTRAINTIGN // verilator lint_off CONTASSREG // verilator lint_off COVERIGN // verilator lint_off DECLFILENAME // verilator lint_off DEFOVERRIDE // verilator lint_off DEFPARAM // verilator lint_off DEPRECATED // verilator lint_off ENCAPSULATED // verilator lint_off ENDLABEL // verilator lint_off ENUMITEMWIDTH // verilator lint_off ENUMVALUE // verilator lint_off EOFNEWLINE // verilator lint_off FUNCTIMECTL // verilator lint_off GENCLK // verilator lint_off GENUNNAMED // verilator lint_off HIERBLOCK // verilator lint_off HIERPARAM // verilator lint_off IFDEPTH // verilator lint_off IGNOREDRETURN // verilator lint_off IMPERFECTSCH // verilator lint_off IMPLICIT // verilator lint_off IMPLICITSTATIC // verilator lint_off IMPORTSTAR // verilator lint_off IMPURE // verilator lint_off INCABSPATH // verilator lint_off INFINITELOOP // verilator lint_off INITIALDLY // verilator lint_off INSECURE // verilator lint_off LATCH // verilator lint_off LITENDIAN // verilator lint_off MINTYPMAXDLY // verilator lint_off MISINDENT // verilator lint_off MODDUP // verilator lint_off MODMISSING // verilator lint_off MULTIDRIVEN // verilator lint_off MULTITOP // verilator lint_off NEWERSTD // verilator lint_off NOEFFECT // verilator lint_off NOLATCH // verilator lint_off NONSTD // verilator lint_off NORETURN // verilator lint_off NULLPORT // verilator lint_off PARAMNODEFAULT // verilator lint_off PINCONNECTEMPTY // verilator lint_off PINMISSING // verilator lint_off PINNOCONNECT // verilator lint_off PINNOTFOUND // verilator lint_off PKGNODECL // verilator lint_off PREPROCZERO // verilator lint_off PROCASSINIT // verilator lint_off PROCASSWIRE // verilator lint_off PROFOUTOFDATE // verilator lint_off PROTECTED // verilator lint_off PROTOTYPEMIS // verilator lint_off RANDC // verilator lint_off REALCVT // verilator lint_off REDEFMACRO // verilator lint_off RISEFALLDLY // verilator lint_off SELRANGE // verilator lint_off SHORTREAL // verilator lint_off SIDEEFFECT // verilator lint_off SPECIFYIGN // verilator lint_off SPLITVAR // verilator lint_off STATICVAR // verilator lint_off STMTDLY // verilator lint_off SYMRSVDWORD // verilator lint_off SYNCASYNCNET // verilator lint_off TICKCOUNT // verilator lint_off TIMESCALEMOD // verilator lint_off UNDRIVEN // verilator lint_off UNOPT // verilator lint_off UNOPTFLAT // verilator lint_off UNOPTTHREADS // verilator lint_off UNPACKED // verilator lint_off UNSIGNED // verilator lint_off UNUSEDGENVAR // verilator lint_off UNUSEDLOOP // verilator lint_off UNUSEDPARAM // verilator lint_off UNUSEDSIGNAL // verilator lint_off USERERROR // verilator lint_off USERFATAL // verilator lint_off USERINFO // verilator lint_off USERWARN // verilator lint_off VARHIDDEN // verilator lint_off WAITCONST // verilator lint_off WIDTH // verilator lint_off WIDTHCONCAT // verilator lint_off WIDTHEXPAND // verilator lint_off WIDTHTRUNC // verilator lint_off WIDTHXZEXPAND // verilator lint_off ZERODLY // verilator lint_off ZEROREPL endmodule verilator-5.042/test_regress/t/t_const_number_v_bad.py0000755000542200017500000000106515101701376023621 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["--language 1364-2005"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_timescale_udp.py0000755000542200017500000000073415101701376022610 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_const_dec_mixed_bad.out0000644000542200017500000000047315101701376024103 0ustar mahmoudyfreeshell%Error: t/t_const_dec_mixed_bad.v:9:30: Mixing X/Z/? with digits not legal in decimal constant: x_1 9 | parameter [200:0] MIXED = 32'dx_1; | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_randomize_from_randomized_class.py0000755000542200017500000000104615101701376026403 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_func_flip.v0000644000542200017500000000267015101701376021552 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define INT_RANGE 31:0 `define INT_RANGE 31:0 // Duplicate identical defs are OK `define INT_RANGE_MAX 31 `define VECTOR_RANGE 511:0 module t (clk); // verilator lint_off WIDTH parameter WIDTH = 16; // Must be a power of 2 parameter WIDTH_LOG2 = 4; // set to log2(WIDTH) parameter USE_BS = 1; // set to 1 for enable input clk; function [`VECTOR_RANGE] func_tree_left; input [`VECTOR_RANGE] x; // x[width-1:0] is the input vector reg [`VECTOR_RANGE] flip; begin flip = 'd0; func_tree_left = flip; end endfunction reg [WIDTH-1:0] a; // value to be shifted reg [WIDTH-1:0] tree_left; always @(a) begin : barrel_shift tree_left = func_tree_left (a); end // barrel_shift integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin a = 5; end if (cyc==2) begin $display ("%x\n",tree_left); //if (tree_left != 'd15) $stop; $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.042/test_regress/t/t_mod_interface_array1.py0000755000542200017500000000073415101701376024050 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_gen_upscope.out0000644000542200017500000000061215101701376022450 0ustar mahmoudyfreeshellcreated tag with scope = top.t.tag created tag with scope = top.t.b.gen[0].tag created tag with scope = top.t.b.gen[1].tag mod a has scope = top.t mod a has tag = top.t.tag mod b has scope = top.t.b mod b has tag = top.t.tag mod c has scope = top.t.b.gen[0].c mod c has tag = top.t.b.gen[0].tag mod c has scope = top.t.b.gen[1].c mod c has tag = top.t.b.gen[1].tag *-* All Finished *-* verilator-5.042/test_regress/t/t_assoc_wildcard_bad.py0000755000542200017500000000076315101701376023563 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_unsigned_bad.py0000755000542200017500000000076615101701376023447 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_trace_two_b.v0000644000542200017500000000101315101701376022063 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; integer c_trace_on; real r; sub sub (); always @ (posedge clk) begin if (cyc != 0) begin r <= r + 0.1; end end endmodule module sub; integer inside_sub_a = 2; endmodule verilator-5.042/test_regress/t/t_implements_noinherit_bad.py0000755000542200017500000000076615101701376025041 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_std_waiver_no.v0000644000542200017500000000061215101701376022442 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Rather than look at waivers, just check we included it `ifdef _VERILATED_STD_WAIVER_VLT_ `error "Shouldn't have included _VERILATED_STD_WAIVER_VLT_" `endif module t; endmodule verilator-5.042/test_regress/t/t_const_sel_sel_extend.v0000644000542200017500000000067615101701376024014 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 module t( output wire res ); function automatic logic foo(logic bar); foo = '0; endfunction logic a, b; logic [0:0][1:0] array; assign b = 0; assign a = foo(b); assign res = array[a][a]; endmodule verilator-5.042/test_regress/t/t_class_member_bad.py0000755000542200017500000000076615101701376023241 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_latch_8.v0000644000542200017500000000136115101701376022151 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2025 by Yutetsu TAKATSUKASA // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t(input wire clk); logic [2:0] v = 3'd0; logic [2:0] v_plus_1; always_comb begin : blk_comb if (v[0]) begin : blk_if automatic logic [2:0] tmp0; // This automatic variable cannot be a latch tmp0 = v + 3'd1; v_plus_1 = tmp0; end else begin : blk_else v_plus_1 = v | 3'd1; end end always @(posedge clk) begin : blk_ff automatic logic [2:0] tmp_auto; tmp_auto = v_plus_1; v <= tmp_auto; $display("v:%d", v); end endmodule verilator-5.042/test_regress/t/t_math_cv_concat.py0000755000542200017500000000101015101701376022726 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--binary', '-fno-expand']) test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_dumpvars_dyn_saif_1.py0000755000542200017500000000130515101701376025100 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_trace_dumpvars_dyn.cpp" test.top_filename = "t/t_trace_dumpvars_dyn.v" test.compile(make_main=False, verilator_flags2=["--trace-saif --exe", test.pli_filename]) test.execute() test.saif_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_property_pexpr_unsup.out0000644000542200017500000001246715101701376024510 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:25:13: Unsupported: strong (in property expression) 25 | strong(a); | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:29:11: Unsupported: weak (in property expression) 29 | weak(a); | ^ %Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:33:9: Unsupported: until (in property expression) 33 | a until b; | ^~~~~ %Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:37:9: Unsupported: s_until (in property expression) 37 | a s_until b; | ^~~~~~~ %Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:41:9: Unsupported: until_with (in property expression) 41 | a until_with b; | ^~~~~~~~~~ %Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:45:9: Unsupported: s_until_with (in property expression) 45 | a s_until_with b; | ^~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:49:9: Unsupported: #-# (in property expression) 49 | a #-# b; | ^~~ %Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:53:9: Unsupported: #=# (in property expression) 53 | a #=# b; | ^~~ %Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:57:7: Unsupported: nexttime (in property expression) 57 | nexttime a; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:61:7: Unsupported: nexttime[] (in property expression) 61 | nexttime [2] a; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:65:7: Unsupported: s_nexttime (in property expression) 65 | s_nexttime a; | ^~~~~~~~~~ %Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:69:7: Unsupported: s_nexttime[] (in property expression) 69 | s_nexttime [2] a; | ^~~~~~~~~~ %Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:73:16: Unsupported: always (in property expression) 73 | nexttime always a; | ^~~~~~ %Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:73:7: Unsupported: nexttime (in property expression) 73 | nexttime always a; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:77:20: Unsupported: always (in property expression) 77 | nexttime [2] always a; | ^~~~~~ %Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:77:7: Unsupported: nexttime[] (in property expression) 77 | nexttime [2] always a; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:81:20: Unsupported: always (in property expression) 81 | nexttime [2] always a; | ^~~~~~ %Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:81:7: Unsupported: nexttime[] (in property expression) 81 | nexttime [2] always a; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:85:16: Unsupported: s_eventually (in property expression) 85 | nexttime s_eventually a; | ^~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:85:7: Unsupported: nexttime (in property expression) 85 | nexttime s_eventually a; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:89:35: Unsupported: always (in property expression) 89 | nexttime s_eventually [2:$] always a; | ^~~~~~ %Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:89:16: Unsupported: s_eventually[] (in property expression) 89 | nexttime s_eventually [2:$] always a; | ^~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:89:7: Unsupported: nexttime (in property expression) 89 | nexttime s_eventually [2:$] always a; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:93:17: Unsupported: accept_on (in property expression) 93 | accept_on (a) b; | ^ %Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:97:22: Unsupported: sync_accept_on (in property expression) 97 | sync_accept_on (a) b; | ^ %Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:101:17: Unsupported: reject_on (in property expression) 101 | reject_on (a) b; | ^ %Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:105:22: Unsupported: sync_reject_on (in property expression) 105 | sync_reject_on (a) b; | ^ %Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:108:27: Unsupported: property argument data type 108 | property p_arg_propery(property inprop); | ^~~~~~~~ %Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:111:27: Unsupported: sequence argument data type 111 | property p_arg_seqence(sequence inseq); | ^~~~~~~~ %Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:116:7: Unsupported: property case expression 116 | case (a) endcase | ^~~~ %Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:119:7: Unsupported: property case expression 119 | case (a) default: b; endcase | ^~~~ %Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:122:7: Unsupported: property case expression 122 | if (a) b | ^~ %Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:125:7: Unsupported: property case expression 125 | if (a) b else c | ^~ %Error: Exiting due to verilator-5.042/test_regress/t/t_typedef_unused_bad.out0000644000542200017500000000047515101701376024001 0ustar mahmoudyfreeshell%Error: t/t_typedef_unused_bad.v:9:9: Forward typedef unused or does not resolve to a data type (IEEE 1800-2023 6.18): 'fwd_undecl_t' 9 | typedef fwd_undecl_t; | ^~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_inst_notunsized.py0000755000542200017500000000077615101701376023237 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["-Wno-IMPLICIT"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_difftree.out0000644000542200017500000000063615101701376021737 0ustar mahmoudyfreeshell@@ -2,7 +2,7 @@ NETLIST 0x {a0aa} $root [1ps/1ps] 1: MODULE 0x {d19ai} t L2 [1ps] 1:2: PORT 0x {d21ae} clk + 1:2: VAR 0x {d23ak} @dt=0@ clkmod INPUT PORT 1:2:1: BASICDTYPE 0x {d23ak} @dt=this@(nw0) LOGIC_IMPLICIT kwd=LOGIC_IMPLICIT 3: TYPETABLE 0x {a0aa} logic -> BASICDTYPE 0x {d55ap} @dt=this@(G/nw1) logic [GENERIC] kwd=logic verilator-5.042/test_regress/t/t_inst_tree_inl1_pub1.py0000755000542200017500000000272215101701376023637 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_inst_tree.v" out_filename = test.obj_dir + "/V" + test.name + ".tree.json" test.compile(v_flags2=[ "--no-json-edit-nums", "-fno-dfg-post-inline", "t/" + test.name + ".vlt", test.wno_unopthreads_for_few_cores ]) if test.vlt_all: test.file_grep( out_filename, r'{"type":"VAR","name":"u.u0.u0.z0",.*"loc":"\w,70:[^"]*",.*"origName":"z0",.*"isSigPublic":true,.*"dtypeName":"logic",.*"isSigUserRdPublic":true.*"isSigUserRWPublic":true' ) test.file_grep( out_filename, r'{"type":"VAR","name":"u.u0.u0.u0.u0.z1",.*"loc":"\w,85:[^"]*",.*"origName":"z1",.*"isSigPublic":true,.*"dtypeName":"logic",.*"isSigUserRdPublic":true,.*"isSigUserRWPublic":true' ) test.file_grep( out_filename, r'{"type":"VAR","name":"u.u0.u1.u0.u0.z",.*"loc":"\w,83:[^"]*",.*"origName":"z",.*,"isSigPublic":true,.*dtypeName":"logic",.*"isSigUserRdPublic":true,.*"isSigUserRWPublic":true' ) test.execute() test.file_grep(test.run_log_filename, r"\] (%m|.*t\.ps): Clocked") test.passes() verilator-5.042/test_regress/t/t_var_ref_bad2.v0000644000542200017500000000112615101701376022114 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Make sure type errors aren't suppressable // verilator lint_off WIDTH module t; task checkset(const ref int bad_const_set); bad_const_set = 32'h4567; // Bad setting const endtask task checkset2(ref int int_ref); endtask initial begin int i; byte bad_non_int; checkset(i); checkset2(bad_non_int); // Type mismatch end endmodule verilator-5.042/test_regress/t/t_cover_assert.v0000644000542200017500000000164315101701376022303 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; bit a; bit b; // Test loop always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 0) begin a <= '0; b <= '0; end else if (cyc == 10) begin a <= '1; b <= '1; end else if (cyc == 11) begin a <= '0; b <= '1; end else if (cyc == 99) begin $write("*-* All Finished *-*\n"); $finish; end end always_ff @(posedge clk) begin C1: cover property(a) begin // Assert under cover legal in some other simulators A2: assert (b); end end endmodule verilator-5.042/test_regress/t/t_param_array9.v0000644000542200017500000000172615101701376022175 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module p_i_match #( parameter type S_IS_T, parameter S_IS_T S_IS ) (); endmodule module ring #( parameter type I_T ) (); localparam int unsigned N_SS = (18 / 2) / 2; localparam int unsigned N_P_IS = (18 / 2) - 1; typedef int s_is_t[N_P_IS-1:0]; function automatic s_is_t gen_s_is(); for (int st = 0; st < N_SS; st++) begin for (int i = 0; i < 2; i++) begin if (st * 2 + i < N_P_IS) begin int delta = ((st + 1) * 2) + i; gen_s_is[st*2+i] = i; end end end endfunction localparam s_is_t S_IS = gen_s_is(); p_i_match #( .S_IS_T(s_is_t), .S_IS(S_IS) ) p ( .*); endmodule module t; typedef logic [4:0] i_t; ring #( .I_T(i_t) ) dut ( .*); endmodule verilator-5.042/test_regress/t/t_trace_rollover.py0000755000542200017500000000174415101701376023016 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t_trace_cat.v" test.compile(make_top_shell=False, make_main=False, v_flags2=["--trace-vcd --exe", test.pli_filename]) test.execute() os.system("cat " + test.obj_dir + "/simrollover_cat*.vcd " + " > " + test.obj_dir + "/simall.vcd") test.vcd_identical(test.obj_dir + "/simall.vcd", test.golden_filename) test.file_grep_not(test.obj_dir + "/simrollover_cat0000.vcd", r'^#') test.file_grep(test.obj_dir + "/simrollover_cat0001.vcd", r'^#') test.file_grep(test.obj_dir + "/simrollover_cat0002.vcd", r'^#') test.passes() verilator-5.042/test_regress/t/t_force_func.v0000644000542200017500000000173115101701376021713 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); end while(0) function bit [1:0] get_arg (bit [1:0] x); return x; endfunction module t; bit [1:0] a; bit [1:0] b = 1; initial begin #1 a = 0; force b = get_arg(a); `checkh(a, 0); `checkh(b, 0); a = 1; #1; `checkh(a, 1); `checkh(b, 1); a = 2; #1; `checkh(a, 2); // TODO // IEEE 1800-2023 10.6 // Assignment shall be reevaluated while the assign or force is in effect. `checkh(b, 2); a = 3; #1; `checkh(a, 3); `checkh(b, 3); release b; `checkh(a, 3); `checkh(b, 3); b = 2; `checkh(b, 2); #1 $finish; end endmodule verilator-5.042/test_regress/t/t_var_ref_bad2.py0000755000542200017500000000076615101701376022313 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_covergroup_with_sample_args_too_few_bad.out0000644000542200017500000000063315101701376030277 0ustar mahmoudyfreeshell%Error: t/t_covergroup_with_sample_args_too_few_bad.v:16:10: Missing argument on non-defaulted argument 'is_read' in function call to FUNC 'sample' : ... note: In instance 't' 16 | cov1.sample(1); | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_a1_first_cc.py0000755000542200017500000000164115101701376022145 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # show-config: This test runs the very first time we've executed Verilator # after building so we make sure to run with --gdbbt, so if it dumps we'll # get a trace. import vltest_bootstrap test.scenarios('vlt') test.leak_check_disable() DEBUG_QUIET = "--debug --debugi 0 --gdbbt --no-dump-tree" test.run( cmd=[ "perl", os.environ["VERILATOR_ROOT"] + "/bin/verilator", # DEBUG_QUIET, "-V" ], verilator_run=True) test.compile(verilator_flags2=[DEBUG_QUIET, "--trace-vcd"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_width_shift_bad.v0000644000542200017500000000172515101701376023755 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (input signed [3:0] i4, output signed [2:0] ol3, output signed [3:0] ol4, output signed [4:0] ol5, output signed [2:0] or3, output signed [3:0] or4, output signed [4:0] or5, output signed [2:0] os3, output signed [3:0] os4, output signed [4:0] os5); assign ol3 = i4 << 1; // WIDTHTRUNC assign ol4 = i4 << 1; assign ol5 = i4 << 1; // WIDTHEXPAND, but ok due to shift amount 1 assign or3 = i4 >> 1; // WIDTHTRUNC, currently warn, but in future ok due to shift amount 1? assign or4 = i4 >> 1; assign or5 = i4 >> 1; // WIDTHEXPAND assign os3 = i4 >>> 1; // WIDTHTRUNC, currently warn, but in future ok due to shift amount 1? assign os4 = i4 >>> 1; assign os5 = i4 >>> 1; // WIDTHEXPAND endmodule verilator-5.042/test_regress/t/t_typedef_id_bad.py0000755000542200017500000000077615101701376022722 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_flag_future.v0000644000542200017500000000063215101701376022104 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin // verilator lint_off FUTURE1 $write("*-* All Finished *-*\n"); $finish; // verilator FUTURE2 // verilator FUTURE2 blah blah end endmodule verilator-5.042/test_regress/t/t_pp_defparen_bad.py0000755000542200017500000000102415101701376023054 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["-Wpedantic"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_flag_nomod_bad.out0000644000542200017500000000023615101701376023056 0ustar mahmoudyfreeshell%Error: No top level module found ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_math_vliw.v0000644000542200017500000000654315101701376021602 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc = 0; reg [7:0] crc; reg [223:0] sum; wire [255:0] mglehy = {32{~crc}}; wire [215:0] drricx = {27{crc}}; wire [15:0] apqrli = {2{~crc}}; wire [2:0] szlfpf = crc[2:0]; wire [15:0] dzosui = {2{crc}}; wire [31:0] zndrba = {16{crc[1:0]}}; wire [223:0] bxiouf; vliw vliw ( // Outputs .bxiouf (bxiouf), // Inputs .mglehy (mglehy[255:0]), .drricx (drricx[215:0]), .apqrli (apqrli[15:0]), .szlfpf (szlfpf[2:0]), .dzosui (dzosui[15:0]), .zndrba (zndrba[31:0])); always @ (posedge clk) begin cyc <= cyc + 1; crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; if (cyc==0) begin // Setup crc <= 8'hed; sum <= 224'h0; end else if (cyc<90) begin //$write("[%0t] cyc==%0d BXI=%x\n", $time, cyc, bxiouf); sum <= {sum[222:0],sum[223]} ^ bxiouf; end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%b %x\n", $time, cyc, crc, sum); if (crc !== 8'b01110000) $stop; if (sum !== 224'h1fdff998855c3c38d467e28124847831f9ad6d4a09f2801098f032a8) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module vliw ( input[255:0] mglehy, input[215:0] drricx, input[15:0] apqrli, input[2:0] szlfpf, input[15:0] dzosui, input[31:0] zndrba, output wire [223:0] bxiouf ); wire [463:0] zhknfc = ({29{~apqrli}} & {mglehy, drricx[215:8]}) | ({29{apqrli}} & {mglehy[247:0], drricx}); wire [335:0] umntwz = ({21{~dzosui}} & zhknfc[463:128]) | ({21{dzosui}} & zhknfc[335:0]); wire [335:0] viuvoc = umntwz << {szlfpf, 4'b0000}; wire [223:0] rzyeut = viuvoc[335:112]; assign bxiouf = {rzyeut[7:0], rzyeut[15:8], rzyeut[23:16], rzyeut[31:24], rzyeut[39:32], rzyeut[47:40], rzyeut[55:48], rzyeut[63:56], rzyeut[71:64], rzyeut[79:72], rzyeut[87:80], rzyeut[95:88], rzyeut[103:96], rzyeut[111:104], rzyeut[119:112], rzyeut[127:120], rzyeut[135:128], rzyeut[143:136], rzyeut[151:144], rzyeut[159:152], rzyeut[167:160], rzyeut[175:168], rzyeut[183:176], rzyeut[191:184], rzyeut[199:192], rzyeut[207:200], rzyeut[215:208], rzyeut[223:216]}; endmodule verilator-5.042/test_regress/t/t_udp_binary_top.py0000755000542200017500000000100215101701376022775 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=['--binary --top-module p']) test.execute() test.passes() verilator-5.042/test_regress/t/t_sys_readmem_bad_addr2.v0000644000542200017500000000061415101701376023773 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg [175:0] hex [15:0]; initial begin $readmemh("t/t_sys_readmem_bad_addr2.mem", hex); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_param_sel_range.py0000755000542200017500000000076415101701376023114 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["--lint-only -Wno-SELRANGE"]) test.passes() verilator-5.042/test_regress/t/t_inst_long_bad.v0000644000542200017500000000070015101701376022377 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_ inst (); endmodule verilator-5.042/test_regress/t/t_rand_stability_process.py0000755000542200017500000000076115101701376024540 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_math_pow5.py0000755000542200017500000000073415101701376021675 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_dpi_string.py0000755000542200017500000000077515101701376022141 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=["t/t_dpi_string_c.cpp"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_generic_function_bad.py0000755000542200017500000000102515101701376026133 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=['--timing'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_fork.v0000644000542200017500000000070115101701376020537 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin fork : fblk begin $write("Forked"); end begin $write("*-* All Finished *-*\n"); $finish; end join : fblk end endmodule verilator-5.042/test_regress/t/t_const_dec_mixed_bad.py0000755000542200017500000000076615101701376023734 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_preproc_stringend_bad.py0000755000542200017500000000076615101701376024334 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_package_identifier_bad.out0000644000542200017500000000043615101701376024550 0ustar mahmoudyfreeshell%Error: t/t_package_identifier_bad.v:15:20: Package/class for ':: reference' not found: 'Bar' 15 | int baz = Foo::Bar::baz; | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_var_dup2_bad.out0000644000542200017500000000231415101701376022472 0ustar mahmoudyfreeshell%Error: t/t_var_dup2_bad.v:13:9: Duplicate declaration of signal: 'bad_o_w' : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2023 23.2.2.2) 13 | wire bad_o_w; | ^~~~~~~ t/t_var_dup2_bad.v:10:11: ... Location of original declaration 10 | output bad_o_w, | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_var_dup2_bad.v:14:9: Duplicate declaration of signal: 'bad_o_r' 14 | reg bad_o_r; | ^~~~~~~ t/t_var_dup2_bad.v:11:11: ... Location of original declaration 11 | output bad_o_r); | ^~~~~~~ %Error: t/t_var_dup2_bad.v:17:9: Duplicate declaration of signal: 'bad_w_r' 17 | reg bad_w_r; | ^~~~~~~ t/t_var_dup2_bad.v:16:9: ... Location of original declaration 16 | wire bad_w_r; | ^~~~~~~ %Error: t/t_var_dup2_bad.v:20:9: Duplicate declaration of signal: 'bad_r_w' 20 | reg bad_r_w; | ^~~~~~~ t/t_var_dup2_bad.v:19:9: ... Location of original declaration 19 | wire bad_r_w; | ^~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_flag_compiler.v0000644000542200017500000000334715101701376022412 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [89:0] in; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [89:0] out; // From test of Test.v wire [44:0] line0; wire [44:0] line1; // End of automatics Test test (/*AUTOINST*/ // Outputs .out (out[89:0]), .line0 (line0[44:0]), .line1 (line1[44:0]), // Inputs .clk (clk), .in (in[89:0])); // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d in=%x out=%x\n", $time, cyc, in, out); `endif cyc <= cyc + 1; if (cyc==0) begin // Setup in <= 90'h3FFFFFFFFFFFFFFFFFFFFFF; end else if (cyc==10) begin if (in==out) begin $write("*-* All Finished *-*\n"); $finish; end else begin $write("*-* Failed!! *-*\n"); $finish; end end end endmodule module Test (/*AUTOARG*/ // Outputs line0, line1, out, // Inputs clk, in ); input clk; input [89:0] in; output reg [44:0] line0; output reg [44:0] line1; output reg [89:0] out; assign {line0,line1} = in; always @(posedge clk) begin out <= {line0,line1}; end endmodule verilator-5.042/test_regress/t/t_time_param.py0000755000542200017500000000077115101701376022111 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--binary']) test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_import_name2_bad.py0000755000542200017500000000110115101701376024207 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_opt_const_dfg.py0000755000542200017500000000145615101701376022624 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_opt_const.v" test.pli_filename = "t/t_opt_const.cpp" test.compile(verilator_flags2=["-Wno-UNOPTTHREADS", "--stats", test.pli_filename]) test.execute() if test.vlt: test.file_grep(test.stats, r'Optimizations, Const bit op reduction\s+(\d+)', 37) test.file_grep(test.stats, r'SplitVar, packed variables split automatically\s+(\d+)', 1) test.passes() verilator-5.042/test_regress/t/t_udp_noname.v0000644000542200017500000000162315101701376021727 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg a1; wire a2 = ~a1; wire o1, o2; udp (o1, a1); udp (o2, a2); integer cyc; initial cyc = 0; // Test loop always @ (posedge clk) begin cyc <= cyc + 1; a1 <= cyc[0]; if (cyc==0) begin end else if (cyc<90) begin if (o1 != cyc[0]) $stop; if (o2 != !cyc[0]) $stop; end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule primitive udp(o,a); output o; input a; `ifdef verilator wire o = ~a; `else table //o a 0 : 1; 1 : 0; endtable `endif endprimitive verilator-5.042/test_regress/t/t_assert_procedural_clk_bad.out0000644000542200017500000000143515101701376025325 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_assert_procedural_clk_bad.v:21:13: Unsupported: Procedural concurrent assertion with clocking event inside always (IEEE 1800-2023 16.14.6) : ... note: In instance 't' 21 | assume property (@(posedge clk) cyc == 9); | ^~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_assert_procedural_clk_bad.v:22:13: Unsupported: Procedural concurrent assertion with clocking event inside always (IEEE 1800-2023 16.14.6) : ... note: In instance 't' 22 | assume property (@(negedge clk) cyc == 9); | ^~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_math_sign_extend.py0000755000542200017500000000073415101701376023312 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_tri_public.v0000644000542200017500000000335715101701376021744 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Unsupported tristate construct error // // This is a compile only regression test of tristate handling for bug514 // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Rob Stoddard. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs out, // Inputs data, up_down, clk, reset ); //----------Output Ports-------------- output [7:0] out; //------------Input Ports-------------- //input [7:0] data ; input [7:0] data; input up_down, clk, reset; //------------Internal Variables-------- reg [7:0] out; logic [7:0] q_out; //-------------Code Starts Here------- always @(posedge clk) if (reset) begin // active high reset out <= 8'b0 ; end else if (up_down) begin out <= out + 1; end else begin out <= q_out; end // verilator lint_off PINMISSING sub_mod sub_mod ( .clk(clk), .data(data), .reset(reset), .q(q_out) ); // verilator lint_on PINMISSING endmodule module sub_mod (/*AUTOARG*/ // Outputs q, test_out, // Inouts test_inout, // Inputs data, clk, reset ); //-----------Input Ports--------------- input [7:0] data /*verilator public*/; input clk, reset; inout test_inout; // Get rid of this, the problem goes away. //-----------Output Ports--------------- output [7:0] q; output test_out; // Not assigned, no problem. logic [7:0] que; // Uncomment this line, the error goes away. //assign test_inout = que; assign q = que; always @ ( posedge clk) if (~reset) begin que <= 8'b0; end else begin que <= data; end endmodule verilator-5.042/test_regress/t/t_display_time.v0000644000542200017500000000375215101701376022272 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `timescale 1ns/1ns module t (/*AUTOARG*/ // Inputs clk ); input clk; always @ (posedge clk) begin if ($time >= 10) begin // Display formatting $write; // Check missing arguments work $write("default: [%0t] 0t time [%t] No0 time p=%p 0p=%0p\n", $time, $time, $time, $time); $timeformat(-9, 0, "", 0); $write("-9,0,,0: [%0t] 0t time [%t] No0 time p=%p 0p=%0p\n", $time, $time, $time, $time); $timeformat(-9, 0, "", 10); $write("-9,0,,10: [%0t] 0t time [%t] No0 time p=%p 0p=%0p\n", $time, $time, $time, $time); $timeformat(-9, 0, "ns", 5); $write("-9,0,ns,5: [%0t] 0t time [%t] No0 time p=%p 0p=%0p\n", $time, $time, $time, $time); $timeformat(-9, 3, "ns", 8); $write("-9,3,ns,8: [%0t] 0t time [%t] No0 time p=%p 0p=%0p\n", $time, $time, $time, $time); $timeformat(-9, 3, "ns"); $write("-9,3,ns : [%0t] 0t time [%t] No0 time p=%p 0p=%0p\n", $time, $time, $time, $time); $timeformat(-9, 3); $write("-9,3: [%0t] 0t time [%t] No0 time p=%p 0p=%0p\n", $time, $time, $time, $time); $timeformat(-9); $write("-9: [%0t] 0t time [%t] No0 time p=%p 0p=%0p\n", $time, $time, $time, $time); $timeformat(); $write(": [%0t] 0t time [%t] No0 time p=%p 0p=%0p\n", $time, $time, $time, $time); $timeformat(-9,,,); $write("-9,,,: [%0t] 0t time [%t] No0 time p=%p 0p=%0p\n", $time, $time, $time, $time); $write("\n"); $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_cover_expr_array_class.v0000644000542200017500000000113315101701376024335 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Class1; int value0 = 7; endclass module t; initial begin int i = 0; Class1 q[15]; for (int j = 0; j < 15; j = j + 1) begin Class1 x = new; q[j] = x; end while (i < 15) begin if ((q[i].value0 > 8) || (q[i].value0 < 5)) $stop; i += 1; end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_inst_dtree_inlab.py0000755000542200017500000000111615101701376023272 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_inst_dtree.v" test.compile(v_flags2=['+define+INLINE_A +define+INLINE_B'], verilator_flags2=['-trace']) test.execute() test.passes() verilator-5.042/test_regress/t/t_order_dpi_export_1.py0000755000542200017500000000105615101701376023560 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_cat_reopen.py0000755000542200017500000000151315101701376023263 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_trace_cat.cpp" test.top_filename = "t/t_trace_cat.v" test.compile(make_top_shell=False, make_main=False, v_flags2=["--trace-vcd --exe", test.pli_filename]) test.execute() test.vcd_identical(test.obj_dir + "/simpart_0000.vcd", "t/" + test.name + "__0000.out") test.vcd_identical(test.obj_dir + "/simpart_0100.vcd", "t/" + test.name + "__0100.out") test.passes() verilator-5.042/test_regress/t/t_trace_dumpvars_dyn_vcd_1.out0000644000542200017500000000717515101701376025121 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $scope module t $end $var wire 32 # cyc [31:0] $end $scope module sub1a $end $var wire 32 - ADD [31:0] $end $var wire 32 # cyc [31:0] $end $var wire 32 $ value [31:0] $end $scope module sub2a $end $upscope $end $scope module sub2b $end $upscope $end $scope module sub2c $end $upscope $end $upscope $end $scope module sub1b $end $var wire 32 1 ADD [31:0] $end $var wire 32 # cyc [31:0] $end $var wire 32 ( value [31:0] $end $scope module sub2a $end $var wire 32 2 ADD [31:0] $end $var wire 32 # cyc [31:0] $end $var wire 32 ) value [31:0] $end $upscope $end $scope module sub2b $end $var wire 32 3 ADD [31:0] $end $var wire 32 # cyc [31:0] $end $var wire 32 * value [31:0] $end $upscope $end $scope module sub2c $end $var wire 32 4 ADD [31:0] $end $var wire 32 # cyc [31:0] $end $var wire 32 + value [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 b00000000000000000000000000000000 # b00000000000000000000000000001010 $ b00000000000000000000000000010100 ( b00000000000000000000000000010101 ) b00000000000000000000000000010110 * b00000000000000000000000000010111 + b00000000000000000000000000001010 - b00000000000000000000000000010100 1 b00000000000000000000000000010101 2 b00000000000000000000000000010110 3 b00000000000000000000000000010111 4 #1 b00000000000000000000000000000001 # b00000000000000000000000000001011 $ b00000000000000000000000000010101 ( b00000000000000000000000000010110 ) b00000000000000000000000000010111 * b00000000000000000000000000011000 + #3 b00000000000000000000000000000010 # b00000000000000000000000000001100 $ b00000000000000000000000000010110 ( b00000000000000000000000000010111 ) b00000000000000000000000000011000 * b00000000000000000000000000011001 + #5 b00000000000000000000000000000011 # b00000000000000000000000000001101 $ b00000000000000000000000000010111 ( b00000000000000000000000000011000 ) b00000000000000000000000000011001 * b00000000000000000000000000011010 + #7 b00000000000000000000000000000100 # b00000000000000000000000000001110 $ b00000000000000000000000000011000 ( b00000000000000000000000000011001 ) b00000000000000000000000000011010 * b00000000000000000000000000011011 + #9 b00000000000000000000000000000101 # b00000000000000000000000000001111 $ b00000000000000000000000000011001 ( b00000000000000000000000000011010 ) b00000000000000000000000000011011 * b00000000000000000000000000011100 + #11 b00000000000000000000000000000110 # b00000000000000000000000000010000 $ b00000000000000000000000000011010 ( b00000000000000000000000000011011 ) b00000000000000000000000000011100 * b00000000000000000000000000011101 + #13 b00000000000000000000000000000111 # b00000000000000000000000000010001 $ b00000000000000000000000000011011 ( b00000000000000000000000000011100 ) b00000000000000000000000000011101 * b00000000000000000000000000011110 + #15 b00000000000000000000000000001000 # b00000000000000000000000000010010 $ b00000000000000000000000000011100 ( b00000000000000000000000000011101 ) b00000000000000000000000000011110 * b00000000000000000000000000011111 + #17 b00000000000000000000000000001001 # b00000000000000000000000000010011 $ b00000000000000000000000000011101 ( b00000000000000000000000000011110 ) b00000000000000000000000000011111 * b00000000000000000000000000100000 + #19 b00000000000000000000000000001010 # b00000000000000000000000000010100 $ b00000000000000000000000000011110 ( b00000000000000000000000000011111 ) b00000000000000000000000000100000 * b00000000000000000000000000100001 + #20 verilator-5.042/test_regress/t/t_hier_block_chained.py0000755000542200017500000000274115101701376023546 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.init_benchmarksim() test.cycles = (int(test.benchmark) if test.benchmark else 100000) test.sim_time = test.cycles * 10 + 1000 THREADS = 2 HIER_BLOCK_THREADS = 2 HIER_THREADS = 4 config_file = test.t_dir + "/" + test.name + ".vlt" test.compile( benchmarksim=1, v_flags2=[ config_file, "+define+SIM_CYCLES=" + str(test.cycles), "--hierarchical", "--stats", (f"-DWORKERS={HIER_BLOCK_THREADS}" if test.vltmt and HIER_BLOCK_THREADS > 1 else ""), (f"--hierarchical-threads {HIER_THREADS}" if test.vltmt and HIER_THREADS > 1 else "") ], threads=(THREADS if test.vltmt else 1), context_threads=(max(HIER_THREADS, THREADS) if test.vltmt else 1)) if test.vltmt: test.file_grep(test.obj_dir + "/V" + test.name + "__hier.dir/V" + test.name + "__stats.txt", r'Optimizations, Thread schedule count\s+(\d+)', 4) test.file_grep(test.obj_dir + "/V" + test.name + "__hier.dir/V" + test.name + "__stats.txt", r'Optimizations, Thread schedule total tasks\s+(\d+)', 6) test.execute() test.passes() verilator-5.042/test_regress/t/t_class_param_extends2.v0000644000542200017500000000136415101701376023705 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class Foo #(type T=bit); int x = $bits(T); endclass class Bar #(type S=int) extends Foo#(S); endclass typedef Bar#() bar_default_t; class Baz; Bar#(logic[7:0]) bar_string; int bar_x; function new; bar_string = new; bar_x = bar_string.x; endfunction endclass typedef Baz baz_t; module t; initial begin bar_default_t bar_default = new; baz_t baz = new; if (bar_default.x != 32) $stop; if (baz.bar_x != 8) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_virtual_interface_method.v0000644000542200017500000000562615101701376024657 0ustar mahmoudyfreeshell// Copyright 2003 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // Create stimulus and Drive the interface class DriverStim; protected virtual example_if v_if; task run(); bit[7:0] x; bit[7:0] y; v_if.reset(); forever begin x++; y++; $display("[DriverStim] initiating calculation, x: %8b y: %8b", x, y); v_if.initiate_calculation(x, y); end endtask: run function void bind_if(virtual example_if v_if); this.v_if = v_if; endfunction: bind_if endclass: DriverStim // Monitor returns from interface and check them class MonitorCheck; localparam NUM_TXNS = 10; protected virtual example_if v_if; task run(); logic[8:0] result; int txns_received = 0; forever begin v_if.wait_for_result(result); $display( "[MonitorCheck] (%d) result %7b carry_out %1b", txns_received, result[7:0], result[8] ); if(++txns_received == NUM_TXNS) begin $write("*-* All Finished *-*\n"); $finish(); end end endtask: run function void bind_if(virtual example_if v_if); this.v_if = v_if; endfunction: bind_if endclass: MonitorCheck module example( input logic clk, input logic rstn, input logic[7:0] x, input logic[7:0] y, output logic[8:0] z ); // 8 bit full adder always_ff @(posedge clk) if(!rstn) z <= '0; else z <= x + y; endmodule: example // interfaces with the DUT interface example_if(); localparam CLK_FREQ_MHz = 400; localparam CLK_PERIOD = 1/((CLK_FREQ_MHz * 1e6) * (1e-12)); logic clk; logic rstn; logic[7:0] x; logic[7:0] y; logic[8:0] z; initial begin: clk_gen forever #(CLK_PERIOD/2) clk = !clk; end: clk_gen task reset(); $display("reset called"); rstn = 0; @(posedge clk); $display("clock tick"); rstn = 1; @(posedge clk); endtask: reset event calc_clkd; task initiate_calculation( input logic[7:0] x_in, input logic[7:0] y_in ); x = x_in; y = y_in; @(posedge clk); ->calc_clkd; endtask: initiate_calculation task wait_for_result(output logic[8:0] result); @(calc_clkd); result = z; endtask: wait_for_result endinterface: example_if module t; example_if example_if_inst(); example DUT( .clk (example_if_inst.clk), .rstn(example_if_inst.rstn), .x (example_if_inst.x), .y (example_if_inst.y), .z (example_if_inst.z) ); initial begin: main DriverStim driverStim = new(); MonitorCheck monitorCheck = new(); driverStim.bind_if(example_if_inst); monitorCheck.bind_if(example_if_inst); fork driverStim.run(); monitorCheck.run(); join_none end: main endmodule: t verilator-5.042/test_regress/t/t_inst_port_array.v0000644000542200017500000000212315101701376023015 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Alex Solomatnikov. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; logic [6-1:0] foo[4-1:0]; //initial $display("%m: %p\n", foo); //initial $display("%m: %p\n", foo[3:0]); // VCS not supported %p with slice //logic [6-1:0] foo2[4-1:0][5:6]; //initial $display("%m: %p\n", foo2[3:0][5:6]); // This is not legal dut #(.W(6), .D(4)) udut(.clk(clk), .foo(foo[4-1:0])); endmodule module dut #(parameter W = 1, parameter D = 1) (input logic clk, input logic [W-1:0] foo[D-1:0]); genvar i, j; generate for (j = 0; j < D; j++) begin for (i = 0; i < W; i++) begin suba ua(.clk(clk), .foo(foo[j][i])); end end endgenerate endmodule module suba (input logic clk, input logic foo); always @(posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_class_assign_bad.v0000644000542200017500000000114215101701376023055 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class Cls; endclass : Cls class Cls2; endclass class ClsExt extends Cls; endclass typedef Cls2 cls2_t; module t; Cls c; Cls2 c2; cls2_t ct2; ClsExt c_ext; task t(Cls c); endtask function void f(ClsExt c); endfunction initial begin c = 0; c = 1; c = c2; c_ext = c; ct2 = c; t(0); t(1); t(c2); f(c); end endmodule verilator-5.042/test_regress/t/t_func_dotted_inl2_vlt.py0000755000542200017500000000175015101701376024100 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_func_dotted.v" out_filename = test.obj_dir + "/V" + test.name + ".tree.json" test.compile(v_flags2=["--no-json-edit-nums", "t/t_func_dotted_inl2.vlt"]) if test.vlt_all: modps = test.file_grep( out_filename, r'{"type":"MODULE","name":"mb","addr":"([^"]*)","loc":"\w,99:[^"]*",.*"origName":"mb"') modp = modps[0][0] test.file_grep( out_filename, r'{"type":"CELL","name":"t.ma0.mb0","addr":"[^"]*","loc":"\w,87:[^"]*",.*"origName":"mb0",.*"modp":"([^"]*)"', modp) test.execute() test.passes() verilator-5.042/test_regress/t/t_class_func_static_bad.py0000755000542200017500000000076615101701376024274 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_eofnewline_vlt.vlt0000644000542200017500000000047115101701376024210 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `verilator_config lint_off -rule EOFNEWLINE --file "*.v" -match "Missing newline at end of file*" verilator-5.042/test_regress/t/t_var_in_fork.v0000644000542200017500000000261115101701376022077 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 int static_var; module t(); event evt; task send_event(); ->evt; endtask class Foo; task do_something(int captured_var); fork begin int my_var; int my_other_var; my_var = captured_var; my_other_var = captured_var; /* Capture the same value "twice" */ my_var++; static_var++; /* Write to a value with static lifetime (valid) */ $display("Vars in forked process: %0d %0d", my_var, my_other_var); if (my_var != 2) $stop; if (my_other_var != 1) $stop; send_event(); end join_none $display("Leaving fork's parent"); endtask endclass initial begin Foo foo; foo = new; static_var = 0; foo.do_something(1); end always @(evt) begin $display("Static variable: %0d", static_var); if (static_var != 1) $stop; fork begin automatic int my_auto_var = 0; my_auto_var++; $display("Automatic variable in fork: %0d", my_auto_var); if (my_auto_var != 1) $stop; end join_none $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_vlt_warn.v0000644000542200017500000000132215101701376021432 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Try inline config `ifdef verilator `verilator_config lint_off -rule CASEX -file "t/t_vlt_warn.v" `verilog `endif module t; reg width_warn_var_line18 = 2'b11; // Width warning - must be line 18 reg width_warn2_var_line19 = 2'b11; // Width warning - must be line 19 reg width_warn3_var_line20 = 2'b11; // Width warning - must be line 20 initial begin casex (1'b1) 1'b0: $stop; endcase $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_lint_declfilename_bbox.py0000755000542200017500000000075115101701376024441 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--lint-only -Wall"]) test.passes() verilator-5.042/test_regress/t/t_lint_implicit_def_bad.v0000644000542200017500000000104315101701376024062 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (a,z); input a; output z; sub sub (); assign imp_warn = 1'b1; // verilator lint_off IMPLICIT assign imp_ok = 1'b1; `default_nettype none assign imp_err = 1'b1; `default_nettype wire assign imp_ok2 = 1'b1; endmodule `default_nettype none `resetall module sub; assign imp_ok3 = 1'b1; endmodule verilator-5.042/test_regress/t/t_lint_noreturn_bad.py0000755000542200017500000000160315101701376023476 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_lint_noreturn.v" test.lint(verilator_flags2=['-Wall -Wno-DECLFILENAME'], fails=True, expect_filename=test.golden_filename) test.extract(in_filename=test.top_filename, out_filename=test.root + "/docs/gen/ex_NORETURN_faulty.rst", lines="11-12") test.extract(in_filename=test.golden_filename, out_filename=test.root + "/docs/gen/ex_NORETURN_msg.rst", lines="1-1") test.passes() verilator-5.042/test_regress/t/t_process_notiming.py0000755000542200017500000000115515101701376023352 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_process.v" test.lint(expect_filename=test.golden_filename, v_flags2=["+define+T_PROCESS+std::process", "--no-timing"], fails=True) test.passes() verilator-5.042/test_regress/t/t_static_function_in_class.py0000755000542200017500000000073415101701376025041 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_covergroup_with_sample_args_default.v0000644000542200017500000000074215101701376027112 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off COVERIGN */ module t; covergroup cg_with_sample(int init) with function sample (int addr, bit is_read = 1'b0); endgroup cg_with_sample cov1 = new(7); function void run(); cov1.sample(5); cov1.sample(6, 1'b1); endfunction endmodule verilator-5.042/test_regress/t/t_preproc_nodef_bad.py0000755000542200017500000000077615101701376023433 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_assert_ctl_arg.out0000644000542200017500000010012015101701376023130 0ustar mahmoudyfreeshell========== Running all asserts at: t/t_assert_ctl_arg.v:49 ========== Testing assert_simple_immediate at t/t_assert_ctl_arg.v:49 [0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. -Info: t/t_assert_ctl_arg.v:137: Verilog $stop, ignored due to +verilator+error+limit Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:49 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:49 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:49 [0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:49 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:49 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:49 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:49 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:49 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:49 Passed 'top.t.cover_simple_immediate_stmt_49' at t/t_assert_ctl_arg.v:49 ========== Running all asserts at: t/t_assert_ctl_arg.v:51 ========== Testing assert_simple_immediate at t/t_assert_ctl_arg.v:51 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:51 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:51 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:51 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:51 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:51 ========== Running all asserts at: t/t_assert_ctl_arg.v:56 ========== Testing assert_simple_immediate at t/t_assert_ctl_arg.v:56 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:56 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:56 [0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:56 Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:56 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:56 [0] %Error: t_assert_ctl_arg.v:157: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:56 Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:56 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:56 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:56 Passed 'top.t.cover_observed_deferred_immediate_stmt_56' at t/t_assert_ctl_arg.v:56 ========== Running all asserts at: t/t_assert_ctl_arg.v:58 ========== Testing assert_simple_immediate at t/t_assert_ctl_arg.v:58 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:58 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:58 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:58 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:58 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:58 ========== Running all asserts at: t/t_assert_ctl_arg.v:63 ========== Testing assert_simple_immediate at t/t_assert_ctl_arg.v:63 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:63 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:63 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:63 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:63 [0] %Error: t_assert_ctl_arg.v:165: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:63 Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:63 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:63 [0] %Error: t_assert_ctl_arg.v:171: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:63 Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:63 Passed 'top.t.cover_final_deferred_immediate_stmt_63' at t/t_assert_ctl_arg.v:63 ========== Running all asserts at: t/t_assert_ctl_arg.v:65 ========== Testing assert_simple_immediate at t/t_assert_ctl_arg.v:65 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:65 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:65 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:65 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:65 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:65 ========== Running all asserts at: t/t_assert_ctl_arg.v:69 ========== Testing assert_simple_immediate at t/t_assert_ctl_arg.v:69 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:69 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:69 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:69 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:69 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:69 ========== Running all asserts at: t/t_assert_ctl_arg.v:71 ========== Testing assert_simple_immediate at t/t_assert_ctl_arg.v:71 [0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:71 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:71 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:71 [0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:71 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:71 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:71 [0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:71 Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:71 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:71 [0] %Error: t_assert_ctl_arg.v:157: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:71 Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:71 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:71 [0] %Error: t_assert_ctl_arg.v:165: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:71 Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:71 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:71 [0] %Error: t_assert_ctl_arg.v:171: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:71 Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:71 Passed 'top.t.cover_simple_immediate_stmt_71' at t/t_assert_ctl_arg.v:71 Passed 'top.t.cover_observed_deferred_immediate_stmt_71' at t/t_assert_ctl_arg.v:71 Passed 'top.t.cover_final_deferred_immediate_stmt_71' at t/t_assert_ctl_arg.v:71 ========== Running all asserts at: t/t_assert_ctl_arg.v:73 ========== Testing assert_simple_immediate at t/t_assert_ctl_arg.v:73 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:73 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:73 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:73 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:73 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:73 ========== Running all asserts at: t/t_assert_ctl_arg.v:76 ========== Testing assert_simple_immediate at t/t_assert_ctl_arg.v:76 [0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:76 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:76 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:76 [0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:76 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:76 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:76 [0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:76 Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:76 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:76 [0] %Error: t_assert_ctl_arg.v:157: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:76 Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:76 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:76 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:76 Passed 'top.t.cover_simple_immediate_stmt_76' at t/t_assert_ctl_arg.v:76 Passed 'top.t.cover_observed_deferred_immediate_stmt_76' at t/t_assert_ctl_arg.v:76 ========== Running all asserts at: t/t_assert_ctl_arg.v:78 ========== Testing assert_simple_immediate at t/t_assert_ctl_arg.v:78 [0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:78 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:78 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:78 [0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:78 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:78 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:78 [0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:78 Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:78 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:78 [0] %Error: t_assert_ctl_arg.v:157: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:78 Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:78 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:78 [0] %Error: t_assert_ctl_arg.v:165: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:78 Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:78 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:78 [0] %Error: t_assert_ctl_arg.v:171: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:78 Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:78 Passed 'top.t.cover_simple_immediate_stmt_78' at t/t_assert_ctl_arg.v:78 Passed 'top.t.cover_observed_deferred_immediate_stmt_78' at t/t_assert_ctl_arg.v:78 Passed 'top.t.cover_final_deferred_immediate_stmt_78' at t/t_assert_ctl_arg.v:78 ========== Running all asserts at: t/t_assert_ctl_arg.v:80 ========== Testing assert_simple_immediate at t/t_assert_ctl_arg.v:80 [0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:80 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:80 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:80 [0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:80 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:80 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:80 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:80 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:80 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:80 Passed 'top.t.cover_simple_immediate_stmt_80' at t/t_assert_ctl_arg.v:80 ========== Running all asserts at: t/t_assert_ctl_arg.v:82 ========== Testing assert_simple_immediate at t/t_assert_ctl_arg.v:82 [0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:82 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:82 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:82 [0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:82 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:82 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:82 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:82 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:82 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:82 Passed 'top.t.cover_simple_immediate_stmt_82' at t/t_assert_ctl_arg.v:82 ========== Running all asserts at: t/t_assert_ctl_arg.v:84 ========== Testing assert_simple_immediate at t/t_assert_ctl_arg.v:84 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:84 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:84 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:84 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:84 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:84 ========== Running all asserts at: t/t_assert_ctl_arg.v:86 ========== Testing assert_simple_immediate at t/t_assert_ctl_arg.v:86 [0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:86 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:86 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:86 [0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:86 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:86 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:86 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:86 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:86 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:86 Passed 'top.t.cover_simple_immediate_stmt_86' at t/t_assert_ctl_arg.v:86 ========== Running all asserts at: t/t_assert_ctl_arg.v:88 ========== Testing assert_simple_immediate at t/t_assert_ctl_arg.v:88 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:88 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:88 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:88 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:88 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:88 ========== Running all asserts at: t/t_assert_ctl_arg.v:90 ========== Testing assert_simple_immediate at t/t_assert_ctl_arg.v:90 [0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:90 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:90 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:90 [0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:90 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:90 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:90 [0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:90 Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:90 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:90 [0] %Error: t_assert_ctl_arg.v:157: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:90 Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:90 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:90 [0] %Error: t_assert_ctl_arg.v:165: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:90 Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:90 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:90 [0] %Error: t_assert_ctl_arg.v:171: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:90 Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:90 Passed 'top.t.cover_simple_immediate_stmt_90' at t/t_assert_ctl_arg.v:90 Passed 'top.t.cover_observed_deferred_immediate_stmt_90' at t/t_assert_ctl_arg.v:90 Passed 'top.t.cover_final_deferred_immediate_stmt_90' at t/t_assert_ctl_arg.v:90 ========== Running all asserts at: t/t_assert_ctl_arg.v:92 ========== Testing assert_simple_immediate at t/t_assert_ctl_arg.v:92 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:92 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:92 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:92 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:92 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:92 ========== Running all asserts at: t/t_assert_ctl_arg.v:97 ========== Testing assert_simple_immediate at t/t_assert_ctl_arg.v:97 [0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:97 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:97 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:97 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:97 [0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:97 Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:97 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:97 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:97 [0] %Error: t_assert_ctl_arg.v:165: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:97 Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:97 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:97 ========== Running all asserts at: t/t_assert_ctl_arg.v:100 ========== Testing assert_simple_immediate at t/t_assert_ctl_arg.v:100 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:100 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:100 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:100 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:100 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:100 Passed 'top.t.cover_simple_immediate_stmt_100' at t/t_assert_ctl_arg.v:100 Passed 'top.t.cover_observed_deferred_immediate_stmt_100' at t/t_assert_ctl_arg.v:100 Passed 'top.t.cover_final_deferred_immediate_stmt_100' at t/t_assert_ctl_arg.v:100 ========== Running all asserts at: t/t_assert_ctl_arg.v:103 ========== Testing assert_simple_immediate at t/t_assert_ctl_arg.v:103 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:103 [0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:103 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:103 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:103 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:103 [0] %Error: t_assert_ctl_arg.v:157: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:103 Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:103 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:103 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:103 [0] %Error: t_assert_ctl_arg.v:171: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:103 Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:103 ========== Running all asserts at: t/t_assert_ctl_arg.v:106 ========== Testing assert_simple_immediate at t/t_assert_ctl_arg.v:106 [0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:106 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:106 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:106 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:106 [0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:106 Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:106 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:106 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:106 [0] %Error: t_assert_ctl_arg.v:165: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:106 Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:106 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:106 Passed 'top.t.cover_simple_immediate_stmt_106' at t/t_assert_ctl_arg.v:106 Passed 'top.t.cover_observed_deferred_immediate_stmt_106' at t/t_assert_ctl_arg.v:106 Passed 'top.t.cover_final_deferred_immediate_stmt_106' at t/t_assert_ctl_arg.v:106 ========== Running all asserts at: t/t_assert_ctl_arg.v:108 ========== Testing assert_simple_immediate at t/t_assert_ctl_arg.v:108 [0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:108 Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:108 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:108 [0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:108 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:108 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:108 [0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:108 Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:108 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:108 [0] %Error: t_assert_ctl_arg.v:157: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:108 Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:108 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:108 [0] %Error: t_assert_ctl_arg.v:165: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:108 Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:108 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:108 [0] %Error: t_assert_ctl_arg.v:171: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:108 Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:108 Passed 'top.t.cover_simple_immediate_stmt_108' at t/t_assert_ctl_arg.v:108 Passed 'top.t.cover_observed_deferred_immediate_stmt_108' at t/t_assert_ctl_arg.v:108 Passed 'top.t.cover_final_deferred_immediate_stmt_108' at t/t_assert_ctl_arg.v:108 ========== Running all asserts at: t/t_assert_ctl_arg.v:110 ========== Testing assert_simple_immediate at t/t_assert_ctl_arg.v:110 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:110 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:110 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:110 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:110 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:110 ========== Running all asserts at: t/t_assert_ctl_arg.v:112 ========== Testing assert_simple_immediate at t/t_assert_ctl_arg.v:112 Testing assume_simple_immediate at t/t_assert_ctl_arg.v:112 [0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:112 Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:112 Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:112 Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:112 Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:112 Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:112 [0] %Error: t_assert_ctl_arg.v:171: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:112 Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:112 Passed 'top.t.cover_simple_immediate_stmt_112' at t/t_assert_ctl_arg.v:112 Passed 'top.t.cover_final_deferred_immediate_stmt_112' at t/t_assert_ctl_arg.v:112 Disabling concurrent asserts, time: 10 Enabling concurrent asserts, time: 20 *-* All Finished *-* [20] %Error: t_assert_ctl_arg.v:182: Assertion failed in top.t.concurrent.assert_concurrent: 'assert' failed. Failed 'top.t.concurrent.assert_concurrent_else' at t/t_assert_ctl_arg.v:183 Failed 'top.t.concurrent.assert_concurrent_stmt_else' at t/t_assert_ctl_arg.v:185 [20] %Error: t_assert_ctl_arg.v:187: Assertion failed in top.t.concurrent.assume_concurrent: 'assert' failed. Failed 'top.t.concurrent.assume_concurrent_else' at t/t_assert_ctl_arg.v:188 Failed 'top.t.concurrent.assume_concurrent_stmt_else' at t/t_assert_ctl_arg.v:190 verilator-5.042/test_regress/t/t_bind2.v0000644000542200017500000000421115101701376020574 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Ed Lander. // SPDX-License-Identifier: CC0-1.0 // verilator lint_off WIDTH `define stop $stop `define checkh(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t ( /*AUTOARG*/ // Inputs clk ); input clk; reg [7:0] p1; reg [7:0] p2; reg [7:0] p3; initial begin p1 = 8'h01; p2 = 8'h02; p3 = 8'h03; end parameter int PARAM1 = 8'h11; parameter int PARAM2 = 8'h12; parameter int PARAM3 = 8'h13; targetmod i_targetmod ( /*AUTOINST*/ // Inputs .clk (clk)); //Binding i_targetmod to mycheck --instantiates i_mycheck inside i_targetmod //PARAM1 not over-riden (as mycheck) (=> 0x31) //PARAM2 explicitly bound to targetmod value (=> 0x22) //PARAM3 explicitly bound to top value (=> 0x13) //p1 implictly bound (.*), takes value from targetmod (=> 0x04) //p2 explictly bound to targetmod (=> 0x05) //p3 explictly bound to top (=> 0x03) // Alternative unsupported form is i_targetmod bind targetmod mycheck #( .PARAM2(PARAM2), .PARAM3(PARAM3) ) i_mycheck ( .p2(p2), .p3(p3), .*); endmodule module targetmod ( input clk ); reg [7:0] p1; reg [7:0] p2; reg [7:0] p3; parameter int PARAM1 = 8'h21; parameter int PARAM2 = 8'h22; parameter int PARAM3 = 8'h23; initial begin p1 = 8'h04; p2 = 8'h05; p3 = 8'h06; end endmodule module mycheck ( /*AUTOARG*/ // Inputs clk, p1, p2, p3 ); input clk; input [7:0] p1; input [7:0] p2; input [7:0] p3; parameter int PARAM1 = 8'h31; parameter int PARAM2 = 8'h32; parameter int PARAM3 = 8'h33; always @(posedge clk) begin `checkh(PARAM1, 8'h31); `checkh(PARAM2, 8'h22); `checkh(PARAM3, 8'h23); `checkh(p1, 8'h04); `checkh(p2, 8'h05); `checkh(p3, 8'h06); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_trace_two_sc.cpp0000644000542200017500000000330315101701376022570 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test // // Copyright 2003-2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // clang-format off #include "verilatedos.h" #include VM_PREFIX_INCLUDE #include "Vt_trace_two_b.h" #include "verilated.h" #ifdef TEST_HDR_TRACE # include "verilated_vcd_sc.h" #endif // clang-format on // Compile in place #include "Vt_trace_two_b__ALL.cpp" // General headers #include "verilated.h" #include "systemc.h" VM_PREFIX* ap; Vt_trace_two_b* bp; int sc_main(int argc, char** argv) { Verilated::debug(0); Verilated::traceEverOn(true); Verilated::commandArgs(argc, argv); sc_signal clk; sc_time sim_time(1100, SC_NS); srand48(5); ap = new VM_PREFIX{"topa"}; bp = new Vt_trace_two_b{"topb"}; ap->clk(clk); bp->clk(clk); #ifdef TEST_HDR_TRACE VerilatedVcdSc* tfp = new VerilatedVcdSc; sc_core::sc_start(sc_core::SC_ZERO_TIME); ap->trace(tfp, 99); bp->trace(tfp, 99); tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); #endif { clk = false; sc_start(10, SC_NS); } while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) { clk = !clk; sc_start(5, SC_NS); } if (!Verilated::gotFinish()) { vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); } ap->final(); bp->final(); #ifdef TEST_HDR_TRACE if (tfp) tfp->close(); #endif VL_DO_DANGLING(delete ap, ap); VL_DO_DANGLING(delete bp, bp); return 0; } verilator-5.042/test_regress/t/t_timing_off.v0000644000542200017500000000163215101701376021723 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; event e1; event e2; initial begin int x; // verilator timing_off #1 fork @e1; @e2; join; @e1 wait(x == 4) x = #1 8; // verilator timing_on if (x != 8) $stop; if ($time != 0) $stop; // verilator timing_off @e2; // verilator timing_on @e1; if ((e1.triggered && e2.triggered) || (!e1.triggered && !e2.triggered)) $stop; if ($time != 2) $stop; $write("*-* All Finished *-*\n"); $finish; end initial #2 ->e1; // verilator timing_off initial #2 ->e2; // verilator timing_on initial #3 $stop; // timeout initial #1 @(e1, e2) #1 $stop; // timeout endmodule verilator-5.042/test_regress/t/t_parse_delay.py0000755000542200017500000000076515101701376022266 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--binary --no-timing']) test.passes() verilator-5.042/test_regress/t/t_inst_array_connect.py0000755000542200017500000000073415101701376023656 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_math_divw.v0000644000542200017500000001747715101701376021602 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; // verilator lint_off WIDTH //============================================================ reg bad; initial begin bad=0; c96(96'h0_0000_0000_0000_0000, 96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0000, 96'h0); c96(96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0000, 96'h0_0000_0000_0000_0000, 96'h0); c96(96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0002, 96'h4_4444_4444_4444_4444, 96'h0); c96(96'h8_8888_8888_8888_8888, 96'h0_2000_0000_0000_0000, 96'h0_0000_0000_0000_0044, 96'h0_0888_8888_8888_8888); c96(96'h8_8888_8888_8888_8888, 96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0001, 96'h0); c96(96'h8_8888_8888_8888_8888, 96'h8_8888_8888_8888_8889, 96'h0_0000_0000_0000_0000, 96'h8_8888_8888_8888_8888); c96(96'h1_0000_0000_8eba_434a, 96'h0_0000_0000_0000_0001, 96'h1_0000_0000_8eba_434a, 96'h0); c96(96'h0003, 96'h0002, 96'h0001, 96'h0001); c96(96'h0003, 96'h0003, 96'h0001, 96'h0000); c96(96'h0003, 96'h0004, 96'h0000, 96'h0003); c96(96'h0000, 96'hffff, 96'h0000, 96'h0000); c96(96'hffff, 96'h0001, 96'hffff, 96'h0000); c96(96'hffff, 96'hffff, 96'h0001, 96'h0000); c96(96'hffff, 96'h0003, 96'h5555, 96'h0000); c96(96'hffff_ffff, 96'h0001, 96'hffff_ffff, 96'h0000); c96(96'hffff_ffff, 96'hffff, 96'h0001_0001, 96'h0000); c96(96'hfffe_ffff, 96'hffff, 96'h0000_ffff, 96'hfffe); c96(96'h1234_5678, 96'h9abc, 96'h0000_1e1e, 96'h2c70); c96(96'h0000_0000, 96'h0001_0000, 96'h0000, 96'h0000_0000); c96(96'h0007_0000, 96'h0003_0000, 96'h0002, 96'h0001_0000); c96(96'h0007_0005, 96'h0003_0000, 96'h0002, 96'h0001_0005); c96(96'h0006_0000, 96'h0002_0000, 96'h0003, 96'h0000_0000); c96(96'h8000_0001, 96'h4000_7000, 96'h0001, 96'h3fff_9001); c96(96'hbcde_789a, 96'hbcde_789a, 96'h0001, 96'h0000_0000); c96(96'hbcde_789b, 96'hbcde_789a, 96'h0001, 96'h0000_0001); c96(96'hbcde_7899, 96'hbcde_789a, 96'h0000, 96'hbcde_7899); c96(96'hffff_ffff, 96'hffff_ffff, 96'h0001, 96'h0000_0000); c96(96'hffff_ffff, 96'h0001_0000, 96'hffff, 96'h0000_ffff); c96(96'h0123_4567_89ab, 96'h0001_0000, 96'h0123_4567, 96'h0000_89ab); c96(96'h8000_fffe_0000, 96'h8000_ffff, 96'h0000_ffff, 96'h7fff_ffff); c96(96'h8000_0000_0003, 96'h2000_0000_0001, 96'h0003, 96'h2000_0000_0000); c96(96'hffff_ffff_0000_0000, 96'h0001_0000_0000, 96'hffff_ffff, 96'h0000_0000_0000); c96(96'hffff_ffff_0000_0000, 96'hffff_0000_0000, 96'h0001_0001, 96'h0000_0000_0000); c96(96'hfffe_ffff_0000_0000, 96'hffff_0000_0000, 96'h0000_ffff, 96'hfffe_0000_0000); c96(96'h1234_5678_0000_0000, 96'h9abc_0000_0000, 96'h0000_1e1e, 96'h2c70_0000_0000); c96(96'h0000_0000_0000_0000, 96'h0001_0000_0000_0000, 96'h0000, 96'h0000_0000_0000_0000); c96(96'h0007_0000_0000_0000, 96'h0003_0000_0000_0000, 96'h0002, 96'h0001_0000_0000_0000); c96(96'h0007_0005_0000_0000, 96'h0003_0000_0000_0000, 96'h0002, 96'h0001_0005_0000_0000); c96(96'h0006_0000_0000_0000, 96'h0002_0000_0000_0000, 96'h0003, 96'h0000_0000_0000_0000); c96(96'h8000_0001_0000_0000, 96'h4000_7000_0000_0000, 96'h0001, 96'h3fff_9001_0000_0000); c96(96'hbcde_789a_0000_0000, 96'hbcde_789a_0000_0000, 96'h0001, 96'h0000_0000_0000_0000); c96(96'hbcde_789b_0000_0000, 96'hbcde_789a_0000_0000, 96'h0001, 96'h0000_0001_0000_0000); c96(96'hbcde_7899_0000_0000, 96'hbcde_789a_0000_0000, 96'h0000, 96'hbcde_7899_0000_0000); c96(96'hffff_ffff_0000_0000, 96'hffff_ffff_0000_0000, 96'h0001, 96'h0000_0000_0000_0000); c96(96'hffff_ffff_0000_0000, 96'h0001_0000_0000_0000, 96'hffff, 96'h0000_ffff_0000_0000); c96(96'h7fff_8000_0000_0000, 96'h8000_0000_0001, 96'h0000_fffe, 96'h7fff_ffff_0002); c96(96'h8000_0000_fffe_0000, 96'h8000_0000_ffff, 96'h0000_ffff, 96'h7fff_ffff_ffff); c96(96'h0008_8888_8888_8888_8888, 96'h0002_0000_0000_0000, 96'h0004_4444, 96'h0000_8888_8888_8888); if (bad) $stop; $write("*-* All Finished *-*\n"); $finish; end task c96; input [95:0] u; input [95:0] v; input [95:0] expq; input [95:0] expr; c96u( u, v, expq, expr); c96s( u, v, expq, expr); c96s(-u, v,-expq,-expr); c96s( u,-v,-expq, expr); c96s(-u,-v, expq,-expr); endtask task c96u; input [95:0] u; input [95:0] v; input [95:0] expq; input [95:0] expr; reg [95:0] gotq; reg [95:0] gotr; gotq = u/v; gotr = u%v; if (gotq != expq && v!=0) begin bad = 1; end if (gotr != expr && v!=0) begin bad = 1; end if (bad `ifdef TEST_VERBOSE || 1 `endif ) begin $write(" %x /u %x = got %x exp %x %% got %x exp %x", u,v,gotq,expq,gotr,expr); // Test for v=0 to prevent Xs causing grief if (gotq != expq && v!=0) $write(" BADQ"); if (gotr != expr && v!=0) $write(" BADR"); $write("\n"); end endtask task c96s; input signed [95:0] u; input signed [95:0] v; input signed [95:0] expq; input signed [95:0] expr; reg signed [95:0] gotq; reg signed [95:0] gotr; gotq = u/v; gotr = u%v; if (gotq != expq && v!=0) begin bad = 1; end if (gotr != expr && v!=0) begin bad = 1; end if (bad `ifdef TEST_VERBOSE || 1 `endif ) begin $write(" %x /s %x = got %x exp %x %% got %x exp %x", u,v,gotq,expq,gotr,expr); // Test for v=0 to prevent Xs causing grief if (gotq != expq && v!=0) $write(" BADQ"); if (gotr != expr && v!=0) $write(" BADR"); $write("\n"); end endtask endmodule verilator-5.042/test_regress/t/t_gen_ifelse.v0000644000542200017500000000125215101701376021700 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module s; parameter A = 0; generate if (A == 1) int i; else if (A == 2) int i; else int i; endgenerate generate if (A == 1) int i; else if (A == 2) int i; else int i; endgenerate endmodule module t; s #(0) s0(); s #(1) s1(); s #(2) s2(); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_unroll_genf.py0000755000542200017500000000073415101701376022304 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_unused_bad.py0000755000542200017500000000117615101701376023132 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=[ "--lint-only --bbox-sys --bbox-unsup -Wall -Wno-DECLFILENAME", "--unused-regexp 'cmdln*'" ], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_gen_nonconst_bad.out0000644000542200017500000000113115101701376023436 0ustar mahmoudyfreeshell%Error-MODMISSING: t/t_gen_nonconst_bad.v:8:4: Cannot find file containing module: 'nfound' 8 | nfound nfound(); | ^~~~~~ ... For error description see https://verilator.org/warn/MODMISSING?v=latest ... This may be because there's no search path specified with -I. ... Looked in: nfound nfound.v nfound.sv obj_dir/nfound obj_dir/nfound.v obj_dir/nfound.sv %Error: Exiting due to verilator-5.042/test_regress/t/t_gate_unsup.v0000644000542200017500000000133615101701376021755 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; wire d, en, nc, pc; // verilator lint_off IMPLICIT cmos (cm0, d, nc, pc); rcmos (rc0, d, nc, pc); nmos (nm0, d, en); pmos (pm0, d, en); rnmos (rn0, d, en); rpmos (rp0, d, en); rtran (rt0, d); tran (tr0, d); rtranif0 (r00, d, en); rtranif1 (r10, d, en); tranif0 (t00, d, en); tranif1 (t10, d, en); // verilator lint_on IMPLICIT initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_class_extern_typeref.v0000644000542200017500000000153515101701376024034 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class uvm_process_guard#(type T=int); T m_context; extern function T get_context(); extern function new(T ctxt); endclass // When this moves into class, note it's not uvm_process_guard#()::T // but rather the T specific to the parameterized class function uvm_process_guard::T uvm_process_guard::get_context(); return this.m_context; endfunction function uvm_process_guard::new(uvm_process_guard::T ctxt); this.m_context = ctxt; endfunction : new class uvm_sequence_base; typedef uvm_process_guard#(uvm_sequence_base) m_guard_t; endclass module t; initial begin uvm_sequence_base c; c = new; $finish; end endmodule verilator-5.042/test_regress/t/t_queue_unknown_sel.v0000644000542200017500000003343215101701376023353 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Alex Solomatnikov. // SPDX-License-Identifier: CC0-1.0 package z_pkg; localparam int OPCODEW=3; localparam int CIDW=4; localparam int SIDW=10; localparam int CTAGW=7; localparam int STAGW=9; localparam int STATEW=3; localparam int ADDRW=37; localparam int DATAW=256; localparam int MASKW=DATAW/8; localparam int SIZEW=4; typedef enum logic [OPCODEW-1:0] { A = 3'h 0, B = 3'h 1 } a_op_t; typedef enum logic [OPCODEW-1:0] { C = 3'h 0, D = 3'h 1 } b_op_t; typedef enum logic [OPCODEW-1:0] { E = 3'h 0, F = 3'h 1 } c_op_t; typedef enum logic [OPCODEW-1:0] { G = 3'h 0, H = 3'h 1 } d_op_t; typedef logic [CIDW-1:0] cid_t; typedef logic [SIDW-1:0] sid_t; typedef logic [CTAGW-1:0] ctag_t; typedef logic [STAGW-1:0] stag_t; typedef logic [STATEW-1:0] state_t; typedef logic [ADDRW-1:0] address_t; typedef logic [SIZEW-1:0] size_t; typedef logic [DATAW-1:0] data_t; typedef logic [MASKW-1:0] mask_t; typedef struct packed { cid_t cid; a_op_t opcode; address_t address; } x1_ch_t; typedef struct packed { cid_t cid; b_op_t opcode; address_t address; } x2_ch_t; typedef struct packed { cid_t cid; sid_t sid; ctag_t ctag; stag_t stag; c_op_t opcode; state_t state2; state_t state3; address_t address; logic f4; size_t size; logic f2; } x3_ch_t; typedef struct packed { cid_t cid; sid_t sid; ctag_t ctag; stag_t stag; d_op_t opcode; state_t state1; logic f4; logic f1; size_t size; logic f3; } x4_ch_t; typedef struct packed { cid_t cid; ctag_t ctag; stag_t stag; d_op_t opcode; logic f1; logic f3; } x5_ch_t; typedef struct packed { logic last; logic corrupt; } x6_ch_t; typedef struct packed { sid_t sid; stag_t stag; } x7_ch_t; typedef enum { CH_X1, CH_Y1, CH_Y2, CH_X2, CH_X3, CH_Y3, CH_X4, CH_X5, CH_X6, CH_X7 } channel_t; parameter channel_t CH_ALL[CH_X7+1] = '{CH_X1, CH_Y1, CH_Y2, CH_X2, CH_X3, CH_Y3, CH_X4, CH_X5, CH_X6, CH_X7}; typedef enum { TXN_0, TXN_1, TXN_2, TXN_3, TXN_4, TXN_5, TXN_6, TXN_7 } txn_type_t; function txn_type_t txn_type(bit [2:0] opcode, channel_t ch); case(opcode) 3'd0: begin case(ch) CH_X1: txn_type = TXN_1; CH_X2: txn_type = TXN_7; CH_X3: txn_type = TXN_7; CH_Y3: txn_type = TXN_7; CH_X4: txn_type = TXN_2; CH_X6: txn_type = TXN_2; default: txn_type = TXN_0; endcase end 3'd1: begin case(ch) CH_Y1: txn_type = TXN_3; CH_X2: txn_type = TXN_4; CH_X3: txn_type = TXN_5; CH_Y3: txn_type = TXN_5; CH_X5: txn_type = TXN_6; default: txn_type = TXN_0; endcase end 3'd2: begin case(ch) CH_Y1: txn_type = TXN_7; CH_X2: txn_type = TXN_7; CH_X3: txn_type = TXN_7; CH_Y3: txn_type = TXN_7; CH_X4: txn_type = TXN_7; CH_X6: txn_type = TXN_7; default: txn_type = TXN_0; endcase end 3'd3: begin case(ch) CH_Y1: txn_type = TXN_7; CH_X2: txn_type = TXN_7; CH_X3: txn_type = TXN_7; CH_Y3: txn_type = TXN_7; CH_X5: txn_type = TXN_7; default: txn_type = TXN_0; endcase end 3'd4: begin case(ch) CH_X1: txn_type = TXN_7; CH_X2: txn_type = TXN_7; CH_X3: txn_type = TXN_7; CH_Y3: txn_type = TXN_7; CH_X4: txn_type = TXN_7; CH_X6: txn_type = TXN_7; CH_X7: txn_type = TXN_7; default: txn_type = TXN_0; endcase end 3'd5: begin case(ch) CH_Y1: txn_type = TXN_7; CH_X2: txn_type = TXN_7; CH_X3: txn_type = TXN_7; CH_Y3: txn_type = TXN_7; CH_X5: txn_type = TXN_7; default: txn_type = TXN_0; endcase end 3'd6: begin case(ch) CH_X3: txn_type = TXN_7; CH_Y3: txn_type = TXN_7; CH_X5: txn_type = TXN_7; default: txn_type = TXN_0; endcase end 3'd7: begin case(ch) CH_Y2: txn_type = TXN_7; default: txn_type = TXN_0; endcase end endcase endfunction endpackage interface z_if; import z_pkg::*; logic x1_valid; x1_ch_t x1; logic x2_valid; x2_ch_t x2; logic x3_valid; x3_ch_t x3; logic x4_valid; x4_ch_t x4; logic x5_valid; x5_ch_t x5; logic x6_valid; x6_ch_t x6; data_t x6_data; logic x7_valid; x7_ch_t x7; function automatic logic x2_trig(); return x2_valid; endfunction function automatic logic x4_trig(); return x4_valid; endfunction function automatic logic x5_trig(); return x5_valid; endfunction function automatic logic x6_trig(); return x6_valid; endfunction modport sender ( output x1_valid, output x1, input x2_valid, input x2, output x3_valid, output x3, input x4_valid, input x4, input x5_valid, input x5, input x6_valid, input x6, input x6_data, output x7_valid, output x7, import x2_trig, import x4_trig, import x5_trig, import x6_trig ); modport receiver ( input x1_valid, input x1, output x2_valid, output x2, input x3_valid, input x3, output x4_valid, output x4, output x5_valid, output x5, output x6_valid, output x6, output x6_data, input x7_valid, input x7, import x2_trig, import x4_trig, import x5_trig, import x6_trig ); endinterface class z_txn_class; rand z_pkg::txn_type_t req_txn_type; rand z_pkg::cid_t cid; rand z_pkg::sid_t sid; rand z_pkg::ctag_t ctag; rand z_pkg::stag_t stag; rand z_pkg::size_t size; rand z_pkg::address_t address; rand z_pkg::state_t state1; rand z_pkg::state_t state2; rand z_pkg::state_t state3; rand logic f1; rand logic f2; rand logic f3; rand logic f4; z_pkg::data_t data[]; z_pkg::mask_t mask[]; bit corrupt[]; logic [2:0] req_opcode; endclass module z_bfm_sender import z_pkg::*; ( input logic clk, input logic reset_l, z_if.sender z_if_sender ); channel_t ch; typedef z_txn_class z_txn_q_t[$]; z_txn_q_t z_txn_qs[ch.num()]; z_txn_class z_txn[ch.num()]; always @(posedge clk or negedge reset_l) begin if (!reset_l) begin z_if_sender.x1_valid <= '0; z_if_sender.x3_valid <= '0; z_if_sender.x7_valid <= '0; end else begin foreach (CH_ALL[i]) begin case(CH_ALL[i]) CH_X1: begin if (z_txn_qs[i].size() > 0) begin z_txn[i] = z_txn_qs[i].pop_front(); z_if_sender.x1_valid <= '1; z_if_sender.x1.cid <= z_txn[i].cid; z_if_sender.x1.opcode <= a_op_t'(z_txn[i].req_opcode); z_if_sender.x1.address <= z_txn[i].address; end end CH_X3: begin if (z_txn_qs[i].size() > 0) begin z_txn[i] = z_txn_qs[i].pop_front(); z_if_sender.x3_valid <= '1; z_if_sender.x3.cid <= z_txn[i].cid; z_if_sender.x3.sid <= z_txn[i].sid; z_if_sender.x3.ctag <= z_txn[i].ctag; z_if_sender.x3.stag <= z_txn[i].stag; z_if_sender.x3.opcode <= c_op_t'(z_txn[i].req_opcode); z_if_sender.x3.state2 <= z_txn[i].state2; z_if_sender.x3.state3 <= z_txn[i].state3; z_if_sender.x3.address <= z_txn[i].address; z_if_sender.x3.f4 <= z_txn[i].f4; z_if_sender.x3.size <= z_txn[i].size; z_if_sender.x3.f2 <= z_txn[i].f2; end end CH_X7: begin if (z_txn_qs[i].size() > 0) begin z_txn[i] = z_txn_qs[i].pop_front(); z_if_sender.x7.sid <= z_txn[i].sid; z_if_sender.x7.stag <= z_txn[i].stag; end end CH_X2: begin if (z_if_sender.x2_trig()) begin z_txn[i] = new; z_txn[i].req_txn_type = txn_type(z_if_sender.x2.opcode, ch); z_txn[i].cid = z_if_sender.x2.cid; z_txn[i].address = z_if_sender.x2.address; z_txn_qs[i].push_back(z_txn[i]); end end CH_X4: begin if (z_if_sender.x4_trig()) begin z_txn[i] = new; z_txn[i].req_txn_type = txn_type(z_if_sender.x4.opcode, ch); z_txn[i].cid = z_if_sender.x4.cid; z_txn[i].sid = z_if_sender.x4.sid; z_txn[i].ctag = z_if_sender.x4.ctag; z_txn[i].stag = z_if_sender.x4.stag; z_txn[i].state1 = z_if_sender.x4.state1; z_txn[i].f1 = z_if_sender.x4.f1; z_txn[i].f4 = z_if_sender.x4.f4; z_txn[i].size = z_if_sender.x4.size; z_txn[i].f3 = z_if_sender.x4.f3; z_txn_qs[i].push_back(z_txn[i]); end end CH_X5: begin if (z_if_sender.x5_trig()) begin z_txn[i] = new; z_txn[i].req_txn_type = txn_type(z_if_sender.x5.opcode, ch); z_txn[i].cid = z_if_sender.x5.cid; z_txn[i].ctag = z_if_sender.x5.ctag; z_txn[i].f1 = z_if_sender.x5.f1; z_txn_qs[i].push_back(z_txn[i]); end end CH_X6: begin if (z_if_sender.x6_trig()) begin z_txn[i] = new; z_txn[i].data = new[1]; z_txn[i].corrupt = new[1]; z_txn[i].data[0] = z_if_sender.x6_data; z_txn[i].corrupt[0] = z_if_sender.x6.corrupt; z_txn_qs[i].push_back(z_txn[i]); end end endcase end end end endmodule module test_core_wrapper ( input logic clk, input logic reset_l, z_if.sender z, mmio_z ); z_bfm_sender mem_z_bfm( .z_if_sender(z), .*); z_bfm_sender mmio_z_bfm( .z_if_sender(mmio_z), .*); endmodule module t ( input clk, input reset_l ); z_if z(), mmio_z(); test_core_wrapper tile( .z (z.sender), .mmio_z(mmio_z.sender), .*); endmodule verilator-5.042/test_regress/t/t_dpi_binary_c.h0000644000542200017500000000105415101701376022204 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // Empty file just to check that GCC finds it properly verilator-5.042/test_regress/t/t_lint_implicit_type_bad.out0000644000542200017500000000131315101701376024647 0ustar mahmoudyfreeshell%Error: t/t_lint_implicit_type_bad.v:15:11: Data type used where a non-data type is expected: 'imp_typedef_conflict' 15 | assign imp_typedef_conflict = 1'b1; | ^~~~~~~~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_lint_implicit_type_bad.v:16:11: Data type used where a non-data type is expected: 'imp_Cls_conflict' 16 | assign imp_Cls_conflict = 1'b1; | ^~~~~~~~~~~~~~~~ %Error: t/t_lint_implicit_type_bad.v:17:11: Data type used where a non-data type is expected: 'imp_PARAM_conflict' 17 | assign imp_PARAM_conflict = 1'b1; | ^~~~~~~~~~~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_vpi_var.v0000644000542200017500000001140615101701376021250 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2010 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef USE_VPI_NOT_DPI //We call it via $c so we can verify DPI isn't required - see bug572 `else import "DPI-C" context function int mon_check(); `endif module t (/*AUTOARG*/ // Outputs x, // Inputs clk, a ); `ifdef VERILATOR `systemc_header extern "C" int mon_check(); `verilog `endif input clk; input [7:0] a; output reg [7:0] x; reg onebit /*verilator public_flat_rw @(posedge clk) */; reg [2:1] twoone /*verilator public_flat_rw @(posedge clk) */; reg [2:1] fourthreetwoone[4:3] /*verilator public_flat_rw @(posedge clk) */; reg LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND /*verilator public_flat_rw*/; // verilator lint_off ASCRANGE reg [0:61] quads[2:3] /*verilator public_flat_rw @(posedge clk) */; // verilator lint_on ASCRANGE reg [31:0] count /*verilator public_flat */; reg [31:0] half_count /*verilator public_flat_rd */ = 0; reg [31:0] delayed /*verilator public_flat_rw */; reg [31:0] delayed_mem [16] /*verilator public_flat_rw */; reg [7:0] text_byte /*verilator public_flat_rw @(posedge clk) */; reg [15:0] text_half /*verilator public_flat_rw @(posedge clk) */; reg [31:0] text_word /*verilator public_flat_rw @(posedge clk) */; reg [63:0] text_long /*verilator public_flat_rw @(posedge clk) */; reg [511:0] text /*verilator public_flat_rw @(posedge clk) */; reg [2047:0] too_big /*verilator public_flat_rw @(posedge clk) */; integer status; real real1 /*verilator public_flat_rw */; string str1 /*verilator public_flat_rw */; // specifically public and not public_flat_rw here so as to induce the C++ // keyword collision localparam int nullptr /*verilator public */ = 123; logic [31:0] some_mem [4] /* verilator public_flat_rd */ = {0, 0, 0, 432}; sub sub(); // Test loop initial begin count = 0; delayed = 0; onebit = 1'b0; fourthreetwoone[3] = 0; // stop icarus optimizing away text_byte = "B"; text_half = "Hf"; text_word = "Word"; text_long = "Long64b"; text = "Verilog Test module"; too_big = "some text"; real1 = 1.0; str1 = "hello"; `ifdef VERILATOR status = $c32("mon_check()"); `endif `ifdef IVERILOG status = $mon_check(); `endif `ifndef USE_VPI_NOT_DPI status = mon_check(); `endif if (status!=0) begin $write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status); $stop; end $write("%%Info: Checking results\n"); if (onebit != 1'b1) $stop; if (quads[2] != 62'h12819213_abd31a1c) $stop; if (quads[3] != 62'h1c77bb9b_3784ea09) $stop; if (text_byte != "A") $stop; if (text_half != "T2") $stop; if (text_word != "Tree") $stop; if (text_long != "44Four44") $stop; if (text != "lorem ipsum") $stop; if (str1 != "something a lot longer than hello") $stop; if (real1 > 123456.7895 || real1 < 123456.7885 ) $stop; end always @(posedge clk) begin count <= count + 2; if (count[1]) half_count <= half_count + 2; if (count == 1000) begin if (delayed != 123) $stop; if (delayed_mem[7] != 456) $stop; $write("*-* All Finished *-*\n"); $finish; end end genvar i; generate for (i=1; i<=6; i=i+1) begin : arr arr #(.LENGTH(i)) arr(); end endgenerate genvar k; generate for (k=1; k<=6; k=k+1) begin : subs sub subsub(); end endgenerate endmodule : t module sub; reg subsig1 /*verilator public_flat_rw*/; reg subsig2 /*verilator public_flat_rd*/; `ifdef IVERILOG // stop icarus optimizing signals away wire redundant = subsig1 | subsig2; `endif endmodule : sub module arr; parameter LENGTH = 1; reg [LENGTH-1:0] sig /*verilator public_flat_rw*/; reg [LENGTH-1:0] rfr /*verilator public_flat_rw*/; reg check /*verilator public_flat_rw*/; reg verbose /*verilator public_flat_rw*/; initial begin sig = {LENGTH{1'b0}}; rfr = {LENGTH{1'b0}}; end always @(posedge check) begin if (verbose) $display("%m : %x %x", sig, rfr); if (check && sig != rfr) $stop; check <= 0; end endmodule : arr verilator-5.042/test_regress/t/t_timing_timescale.out0000644000542200017500000000102615101701376023456 0ustar mahmoudyfreeshell[0] clkb is 1 [5e-07] clkb is 0 [1e-06] clkb is 1 [1.5e-06] clkb is 0 [1.75e-06] Initial finishing, clkb = 0 [2e-06] clkb is 1 [2.5e-06] clkb is 0 [3e-06] clkb is 1 [3.5e-06] clkb is 0 [4e-06] clkb is 1 [4.5e-06] clkb is 0 [5e-06] clkb is 1 [5.5e-06] clkb is 0 [6e-06] clkb is 1 [6.5e-06] clkb is 0 [7e-06] clkb is 1 [7.5e-06] clkb is 0 [8e-06] clkb is 1 [8.5e-06] clkb is 0 [9e-06] clkb is 1 [9.5e-06] clkb is 0 [1e-05] clkb is 1 [1e-05] Finishing (t.bot) *-* All Finished *-* [10500] final (t) [1.05e-05] final (t.bot) count was 21 verilator-5.042/test_regress/t/t_cover_expr_dyn_array_class.py0000755000542200017500000000100015101701376025366 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--coverage-expr']) test.execute() test.passes() verilator-5.042/test_regress/t/t_math_real_random.py0000755000542200017500000000073415101701376023266 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_udp_sequential.v0000644000542200017500000000262515101701376022627 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Mike Thyer. // SPDX-License-Identifier: CC0-1.0 primitive d_edge_ff (q, clock, data); output q; reg q; input clock, data; initial q = 1'b1; table // clock data q q+ // obtain output on rising edge of clock F 0 : ? : 0 ; (10) 1 : ? : 1 ; R 0 : ? : 1 ; (0?) 1 : ? : 0 ; endtable endprimitive module t (/*AUTOARG*/ // Inputs clk ); input clk; reg d, q; d_edge_ff g (q, clk, d); int cycle=0; initial d = 0; always @(posedge clk or negedge clk) begin cycle <= cycle+1; if (cycle==0) begin d = 1; end else if (cycle==1) begin d = 0; if (q != 1) $stop; end else if (cycle==2) begin if (q != 1) $stop; end else if (cycle==3) begin if (q != 0) $stop; end else if (cycle==4) begin d = 1; if (q != 1) $stop; end else if (cycle==5) begin $display("d=%d clk=%d cycle=%0d", d, clk, cycle); if (q != 1) $stop; end else if (cycle==6) begin if (q != 0) $stop; end else if (cycle==7) begin if (q != 1) $stop; end else if (cycle >= 8) begin if (q != 0) $stop;; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_interface_array2.v0000644000542200017500000000277515101701376023033 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Johan Bjork. // SPDX-License-Identifier: CC0-1.0 interface intf; logic logic_in_intf; modport source(output logic_in_intf); modport sink(input logic_in_intf); endinterface module modify_interface ( input logic value, intf.source intf_inst ); assign intf_inst.logic_in_intf = value; endmodule function integer return_3(); return 3; endfunction module t #( parameter N = 6 )(); intf ifs[N-1:0] (); logic [N-1:0] data; assign data = {1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1}; generate genvar i; for (i = 0;i < 3; i++) begin assign ifs[i].logic_in_intf = data[i]; end endgenerate // verilator lint_off SIDEEFFECT modify_interface m3 ( .value(data[return_3()]), .intf_inst(ifs[return_3()])); // verilator lint_on SIDEEFFECT modify_interface m4 ( .value(data[4]), .intf_inst(ifs[4])); modify_interface m5 ( .value(~ifs[4].logic_in_intf), .intf_inst(ifs[5])); generate genvar j; for (j = 0;j < N-1; j++) begin initial begin #1; if (ifs[j].logic_in_intf != data[j]) $stop; end end endgenerate initial begin #1; if (ifs[5].logic_in_intf != ~ifs[4].logic_in_intf) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_type_compare_bad.v0000644000542200017500000000074315101701376023101 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin // Syntax error, so not checking: if (type(real) == 1)) $stop; // Bad case (type(real)) 1: $stop; // Bad default: $finish; endcase $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_srandom_class_dep.py0000755000542200017500000000071415101701376023450 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.passes() verilator-5.042/test_regress/t/t_gen_defparam_bad.v0000644000542200017500000000050115101701376023012 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; defparam id_13.id_14 = -id_13, id_15 = id_14; defparam id_8 = 1, id_9 = 1; endmodule verilator-5.042/test_regress/t/t_lint_numwidth.v0000644000542200017500000000046215101701376022467 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 logic [65535:0] a = 65536'd1; logic [65536:0] b = 65537'd1; logic [131071:0] c = 131072'd1; verilator-5.042/test_regress/t/t_interface_top_bad.v0000644000542200017500000000074315101701376023234 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface ifc; logic [3:0] value; logic reset; modport counter_mp (input reset, output value); modport core_mp (output reset, input value); endinterface module t (// Inputs input clk, ifc.counter_mp c_data ); integer cyc=1; endmodule verilator-5.042/test_regress/t/t_flag_timescale.py0000755000542200017500000000104115101701376022721 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["-timescale 1ms/1us"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_func_complex.py0000755000542200017500000000073415101701376022454 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_array_packed_sysfunct.v0000644000542200017500000001474115101701376024172 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2009 by Iztok Jeras. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t (/*AUTOARG*/ // Inputs clk ); input clk; // parameters for array sizes localparam WA = 4; localparam WB = 6; localparam WC = 8; // 2D packed arrays logic [WA+1:2] [WB+1:2] [WC+1:2] array_dsc; // descending range array /* verilator lint_off ASCRANGE */ logic [2:WA+1] [2:WB+1] [2:WC+1] array_asc; // ascending range array /* verilator lint_on ASCRANGE */ logic [1:0] array_unpk [3:2][1:0]; integer cnt = 0; integer slc = 0; // slice type integer dim = 0; // dimension integer wdt = 0; // width initial begin `checkh($dimensions (array_unpk), 3); `ifndef VCS `checkh($unpacked_dimensions (array_unpk), 2); // IEEE 2009 `endif `checkh($bits (array_unpk), 2*2*2); `checkh($low (array_unpk), 2); `checkh($high (array_unpk), 3); `checkh($left (array_unpk), 3); `checkh($right(array_unpk), 2); `checkh($increment(array_unpk), 1); `checkh($size (array_unpk), 2); end // event counter always @ (posedge clk) begin cnt <= cnt + 1; end // finish report always @ (posedge clk) if ( (cnt[30:4]==3) && (cnt[3:2]==2'd3) && (cnt[1:0]==2'd3) ) begin $write("*-* All Finished *-*\n"); $finish; end integer slc_next; // calculation of dimention sizes always @ (posedge clk) begin // slicing type counter case (cnt[3:2]) 2'd0 : begin slc_next = 0; end // full array 2'd1 : begin slc_next = 1; end // single array element 2'd2 : begin slc_next = 2; end // half array default: begin slc_next = 0; end endcase slc <= slc_next; // dimension counter case (cnt[1:0]) 2'd0 : begin dim <= 1; wdt <= (slc_next==1) ? WA/2 : (slc_next==2) ? WA/2 : WA; end 2'd1 : begin dim <= 2; wdt <= WB; end 2'd2 : begin dim <= 3; wdt <= WC; end default: begin dim <= 0; wdt <= 0; end endcase end always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("cnt[30:4]=%0d slc=%0d dim=%0d wdt=%0d\n", cnt[30:4], slc, dim, wdt); `endif if (cnt[30:4]==1) begin // descending range if (slc==0) begin // full array `checkh($dimensions (array_dsc), 3); `checkh($bits (array_dsc), WA*WB*WC); if ((dim>=1)&&(dim<=3)) begin `checkh($left (array_dsc, dim), wdt+1); `checkh($right (array_dsc, dim), 2 ); `checkh($low (array_dsc, dim), 2 ); `checkh($high (array_dsc, dim), wdt+1); `checkh($increment (array_dsc, dim), 1 ); `checkh($size (array_dsc, dim), wdt ); end end else if (slc==1) begin // single array element `checkh($dimensions (array_dsc[2]), 2); `checkh($bits (array_dsc[2]), WB*WC); if ((dim>=2)&&(dim<=3)) begin `checkh($left (array_dsc[2], dim-1), wdt+1); `checkh($right (array_dsc[2], dim-1), 2 ); `checkh($low (array_dsc[2], dim-1), 2 ); `checkh($high (array_dsc[2], dim-1), wdt+1); `checkh($increment (array_dsc[2], dim-1), 1 ); `checkh($size (array_dsc[2], dim-1), wdt ); end `ifndef VERILATOR // Unsupported slices don't maintain size correctly end else if (slc==2) begin // half array `checkh($dimensions (array_dsc[WA/2+1:2]), 3); `checkh($bits (array_dsc[WA/2+1:2]), WA/2*WB*WC); if ((dim>=1)&&(dim<=3)) begin `checkh($left (array_dsc[WA/2+1:2], dim), wdt+1); `checkh($right (array_dsc[WA/2+1:2], dim), 2 ); `checkh($low (array_dsc[WA/2+1:2], dim), 2 ); `checkh($high (array_dsc[WA/2+1:2], dim), wdt+1); `checkh($increment (array_dsc[WA/2+1:2], dim), 1 ); `checkh($size (array_dsc[WA/2+1:2], dim), wdt); end `endif end end else if (cnt[30:4]==2) begin // ascending range if (slc==0) begin // full array `checkh($dimensions (array_asc), 3); `checkh($bits (array_asc), WA*WB*WC); if ((dim>=1)&&(dim<=3)) begin `checkh($left (array_asc, dim), 2 ); `checkh($right (array_asc, dim), wdt+1); `checkh($low (array_asc, dim), 2 ); `checkh($high (array_asc, dim), wdt+1); `checkh($increment (array_asc, dim), -1 ); `checkh($size (array_asc, dim), wdt ); end end else if (slc==1) begin // single array element `checkh($dimensions (array_asc[2]), 2); `checkh($bits (array_asc[2]), WB*WC); if ((dim>=2)&&(dim<=3)) begin `checkh($left (array_asc[2], dim-1), 2 ); `checkh($right (array_asc[2], dim-1), wdt+1); `checkh($low (array_asc[2], dim-1), 2 ); `checkh($high (array_asc[2], dim-1), wdt+1); `checkh($increment (array_asc[2], dim-1), -1 ); `checkh($size (array_asc[2], dim-1), wdt ); end `ifndef VERILATOR // Unsupported slices don't maintain size correctly end else if (slc==2) begin // half array `checkh($dimensions (array_asc[2:WA/2+1]), 3); `checkh($bits (array_asc[2:WA/2+1]), WA/2*WB*WC); if ((dim>=1)&&(dim<=3)) begin `checkh($left (array_asc[2:WA/2+1], dim), 2 ); `checkh($right (array_asc[2:WA/2+1], dim), wdt+1); `checkh($low (array_asc[2:WA/2+1], dim), 2 ); `checkh($high (array_asc[2:WA/2+1], dim), wdt+1); `checkh($increment (array_asc[2:WA/2+1], dim), -1 ); `checkh($size (array_asc[2:WA/2+1], dim), wdt ); end `endif end end end endmodule verilator-5.042/test_regress/t/t_type_compare_bad.out0000644000542200017500000000051215101701376023435 0ustar mahmoudyfreeshell%Error: t/t_type_compare_bad.v:12:9: Case(type) statement requires items that have type() items : ... note: In instance 't' 12 | 1: $stop; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_output_groups.v0000644000542200017500000000164615101701376022546 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 virtual class Base; pure virtual function int get_param; endclass class Foo#(int N = 17) extends Base; function int get_param; return N; endfunction endclass module t (/*AUTOARG*/ // Inputs clk ); input clk; localparam MAX = 128; Base q[$]; generate // should result in many C++ files genvar i; for (i = 0; i < MAX; i++) initial begin Foo#(i) item = new; q.push_back(item); end endgenerate always @(posedge clk) begin static int sum = 0; foreach (q[i]) sum += q[i].get_param(); if (sum != MAX * (MAX - 1) / 2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_uvm_dpi.out0000644000542200017500000000317415101701376021612 0ustar mahmoudyfreeshellUVM Report t/t_uvm_dpi.v:42: id message uvm_dpi_get_tool_name_c() = Verilator = uvm_re = uvm_hdl_check_path = uvm_hdl_read simple variable = uvm_hdl_read not found (bad) === UVM Report expected on next line: UVM Report ../../t/uvm/dpi/uvm_hdl_verilator.c:54: UVM/DPI/HDL_SET set: unable to locate hdl path (t.__DEPOSIT_NOT_FOUND) Either the name is incorrect, or you may not have PLI/ACC visibility to that name = uvm_hdl_deposit simple variable = uvm_hdl_read single bit = uvm_hdl_deposit single bit = uvm_hdl_read multi-bit = uvm_hdl_deposit multi-bit = uvm_hdl_deposit bad ranges === UVM Report expected on next line: UVM Report ../../t/uvm/dpi/uvm_hdl_verilator.c:54: UVM/DPI/HDL_SET set: unable to locate hdl path (t.exposed[10:3]) Either the name is incorrect, or you may not have PLI/ACC visibility to that name === UVM Report expected on next line: UVM Report ../../t/uvm/dpi/uvm_hdl_verilator.c:54: UVM/DPI/HDL_SET set: unable to locate hdl path (t.exposed[99:15]) Either the name is incorrect, or you may not have PLI/ACC visibility to that name = uvm_hdl_force === UVM Report expected on next line: UVM Report ../../t/uvm/dpi/uvm_hdl_verilator.c:54: UVM/DPI/VLOG_GET Unsupported: uvh_hdl_force/uvm_hdl_release on hdl path 't.exposed' = uvm_hdl_release === UVM Report expected on next line: UVM Report ../../t/uvm/dpi/uvm_hdl_verilator.c:54: UVM/DPI/VLOG_GET Unsupported: uvh_hdl_force/uvm_hdl_release on hdl path 't.exposed' = uvm_hdl_release_and_read === UVM Report expected on next line: UVM Report ../../t/uvm/dpi/uvm_hdl_verilator.c:54: UVM/DPI/VLOG_GET Unsupported: uvh_hdl_force/uvm_hdl_release on hdl path 't.exposed' *-* All Finished *-* verilator-5.042/test_regress/t/t_flag_comp_limit_parens.py0000755000542200017500000000120115101701376024455 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["--comp-limit-parens 2"]) test.execute() files = test.glob_some(test.obj_dir + "/" + test.vm_prefix + "___024root__*__Slow.cpp") test.file_grep_any(files, r'Vdeeptemp') test.passes() verilator-5.042/test_regress/t/t_config_param.out0000644000542200017500000000223115101701376022565 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_config_param.v:24:4: Unsupported: config localparam declaration 24 | localparam P1 = "cfg.p1"; | ^~~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_config_param.v:25:4: Unsupported: config localparam declaration 25 | localparam P2 = "cfg.p2"; | ^~~~~~~~~~ %Error-UNSUPPORTED: t/t_config_param.v:27:26: Unsupported: 'config use' parameter assignment 27 | instance t.u_1a use #(.P1(), .P2("override.u_a.p2")); | ^ %Error-UNSUPPORTED: t/t_config_param.v:27:33: Unsupported: 'config use' parameter assignment 27 | instance t.u_1a use #(.P1(), .P2("override.u_a.p2")); | ^ %Error-UNSUPPORTED: t/t_config_param.v:29:26: Unsupported: 'config use' parameter assignment 29 | instance t.u_1c use #(.P1(P1), .P2(P2)); | ^ %Error-UNSUPPORTED: t/t_config_param.v:29:35: Unsupported: 'config use' parameter assignment 29 | instance t.u_1c use #(.P1(P1), .P2(P2)); | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_unpacked_str_init.py0000755000542200017500000000075515101701376023502 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() # No execute, not self-checking test.passes() verilator-5.042/test_regress/t/t_type_param_circ_bad.py0000755000542200017500000000077615101701376023747 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_stream_queue.v0000644000542200017500000000110515101701376022274 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; int i_header; int i_len; byte i_data[]; int i_crc; int o_header; int o_len; byte o_data[]; int o_crc; initial begin byte pkt[$]; i_header = 12; i_len = 5; i_data = new[5]; i_crc = 42; pkt = {<<8{i_header, i_len, i_data, i_crc}}; {<<8{o_header, o_len, o_data, o_crc}} = pkt; $finish; end endmodule verilator-5.042/test_regress/t/t_inst_signed1.py0000755000542200017500000000073415101701376022361 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_complex.py0000755000542200017500000000203415101701376022612 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--cc --trace-vcd']) test.execute() test.file_grep(test.trace_filename, r' v_arrp ') test.file_grep(test.trace_filename, r' v_arrp_arrp ') test.file_grep(test.trace_filename, r' v_arrp_strp ') test.file_grep(test.trace_filename, r' v_arru\[') test.file_grep(test.trace_filename, r' v_arru_arrp\[') test.file_grep(test.trace_filename, r' v_arru_arru\[') test.file_grep(test.trace_filename, r' v_arru_strp\[') test.file_grep(test.trace_filename, r' v_strp ') test.file_grep(test.trace_filename, r' v_strp_strp ') test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_math_wallace.v0000644000542200017500000000533115101701376022223 0ustar mahmoudyfreeshell// -*- Verilog -*- // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg negate; reg enable; wire [31:0] datA = crc[31:0]; wire [31:0] datB = crc[63:32]; // Predict result wire [63:0] muled = (negate ? (-{32'h0, datA} * {32'h0, datB}) : ({32'h0, datA} * {32'h0, datB})); reg [63:0] muled_d1; reg [63:0] muled_d2; reg [63:0] muled_d3; reg enable_d1; reg enable_d2; always @(posedge clk) enable_d1 <= enable; always @(posedge clk) enable_d2 <= enable_d1; always @(posedge clk) if (enable) muled_d1 <= muled; always @(posedge clk) if (enable_d1) muled_d2 <= muled_d1; always @(posedge clk) if (enable_d2) muled_d3 <= muled_d2; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [64:0] product_d3; // From test of t_math_wallace_mul.v // End of automatics t_math_wallace_mul test ( /*AUTOINST*/ // Outputs .product_d3 (product_d3[64:0]), // Inputs .clk (clk), .enable (enable), .negate (negate), .datA (datA[31:0]), .datB (datB[31:0])); integer cycs_enabled; initial cycs_enabled = 0; // Test loop always @(posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x a*b=%x wallace=%x\n", $time, cyc, crc, muled_d3, product_d3[63:0]); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; negate <= cyc[0]; // Toggle negation //enable <= 1'b1; // 100% activity factor enable <= cyc[4]; // 50% activity factor //enable <= cyc[4]&cyc[3]; // 25% activity factor if (enable) cycs_enabled = cycs_enabled + 1; if (cyc == 0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else begin if (product_d3[63:0] != muled_d3) begin $write("[%0t] BAD product, got=%x exp=%x\n", $time, product_d3[63:0], muled_d3); $stop; end if (cyc == 99) begin if (crc !== 64'hc77bb9b3784ea091) $stop; end `ifndef SIM_CYCLES `define SIM_CYCLES 99 `endif if (cyc == `SIM_CYCLES) begin $write("- Cycles=%0d, Activity factor=%0d%%\n", cyc, ((cycs_enabled * 100) / cyc)); $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.042/test_regress/t/t_class_param_comma_bad.v0000644000542200017500000000125715101701376024054 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls #(parameter PARAMB = 12); endclass class Cls2 #(parameter PARAMB = 13, parameter PARAMC = 14); endclass module t; Cls #(.PARAMBAD(1)) c; // Bad param name Cls #(13, 1) cd; // Bad param number Cls #(.PARAMB(14),) ce; // Bad superfluous comma Cls #(14,) cf; // Bad superfluous comma Cls2 #(15,) cg; // Bad superfluous comma Cls2 #(.PARAMB(16),) ch; // Bad superfluous comma Cls2 #(.PARAMC(17),) ci; // Bad superfluous comma endmodule verilator-5.042/test_regress/t/t_flag_lib_dpi.py0000755000542200017500000000212215101701376022356 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.run(logfile=test.obj_dir + "/vlt_compile.log", cmd=[ "perl", os.environ["VERILATOR_ROOT"] + "/bin/verilator", "-cc", "--build", '--no-timing', "-Mdir", test.obj_dir, "t/t_flag_lib_dpi.v", test.t_dir + "/t_flag_lib_dpi.cpp", test.t_dir + "/t_flag_lib_dpi_main.cpp" ], verilator_run=True) test.run( logfile=test.obj_dir + "/cxx_compile.log", cmd=[ "cd " + test.obj_dir # + " && cp " + test.t_dir + "/t_flag_lib_dpi.mk t_flag_lib_dpi.mk" # + " && " + os.environ["MAKE"] + " -f t_flag_lib_dpi.mk t_flag_lib_dpi_test" # + " && ./t_flag_lib_dpi_test" ]) test.passes() verilator-5.042/test_regress/t/t_trace_array_fst_threads_1.py0000755000542200017500000000131615101701376025071 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_trace_array.v" test.golden_filename = "t/t_trace_array_fst.out" test.compile( verilator_flags2=['--cc --trace-fst --trace-threads 1 --trace-structs --trace-max-width 0']) test.execute() test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_structu_dataType_assignment.py0000755000542200017500000000100115101701376025552 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--structs-packed']) test.execute() test.passes() verilator-5.042/test_regress/t/t_case_huge_sub3.v0000644000542200017500000003371315101701376022466 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t_case_huge_sub3 (/*AUTOARG*/ // Outputs outr, // Inputs clk, index ); input clk; input [9:0] index; output logic [3:0] outr; // ============================= // Created from Pthon3: // for i in range(256): // print(" 8'h%02x: begin outr <= outr^index[8:5]^4'h%01x; end" // % (i, random.randint(0,15))) // Reset cheating initial outr = 4'b0; always @(posedge clk) begin // verilog_format: off case (index[7:0]) 8'h00: begin outr <= 4'h0; end 8'h01: begin /*No Change*/ end 8'h02: begin outr <= outr^index[8:5]^4'ha; end 8'h03: begin outr <= outr^index[8:5]^4'h4; end 8'h04: begin outr <= outr^index[8:5]^4'hd; end 8'h05: begin outr <= outr^index[8:5]^4'h1; end 8'h06: begin outr <= outr^index[8:5]^4'hf; end 8'h07: begin outr <= outr^index[8:5]^4'he; end 8'h08: begin outr <= outr^index[8:5]^4'h0; end 8'h09: begin outr <= outr^index[8:5]^4'h4; end 8'h0a: begin outr <= outr^index[8:5]^4'h5; end 8'h0b: begin outr <= outr^index[8:5]^4'ha; end 8'h0c: begin outr <= outr^index[8:5]^4'h2; end 8'h0d: begin outr <= outr^index[8:5]^4'hf; end 8'h0e: begin outr <= outr^index[8:5]^4'h5; end 8'h0f: begin outr <= outr^index[8:5]^4'h0; end 8'h10: begin outr <= outr^index[8:5]^4'h3; end 8'h11: begin outr <= outr^index[8:5]^4'hb; end 8'h12: begin outr <= outr^index[8:5]^4'h0; end 8'h13: begin outr <= outr^index[8:5]^4'hf; end 8'h14: begin outr <= outr^index[8:5]^4'h3; end 8'h15: begin outr <= outr^index[8:5]^4'h5; end 8'h16: begin outr <= outr^index[8:5]^4'h7; end 8'h17: begin outr <= outr^index[8:5]^4'h2; end 8'h18: begin outr <= outr^index[8:5]^4'h3; end 8'h19: begin outr <= outr^index[8:5]^4'hb; end 8'h1a: begin outr <= outr^index[8:5]^4'h5; end 8'h1b: begin outr <= outr^index[8:5]^4'h4; end 8'h1c: begin outr <= outr^index[8:5]^4'h2; end 8'h1d: begin outr <= outr^index[8:5]^4'hf; end 8'h1e: begin outr <= outr^index[8:5]^4'h0; end 8'h1f: begin outr <= outr^index[8:5]^4'h4; end 8'h20: begin outr <= outr^index[8:5]^4'h6; end 8'h21: begin outr <= outr^index[8:5]^4'ha; end 8'h22: begin outr <= outr^index[8:5]^4'h6; end 8'h23: begin outr <= outr^index[8:5]^4'hb; end 8'h24: begin outr <= outr^index[8:5]^4'ha; end 8'h25: begin outr <= outr^index[8:5]^4'he; end 8'h26: begin outr <= outr^index[8:5]^4'h7; end 8'h27: begin outr <= outr^index[8:5]^4'ha; end 8'h28: begin outr <= outr^index[8:5]^4'h3; end 8'h29: begin outr <= outr^index[8:5]^4'h8; end 8'h2a: begin outr <= outr^index[8:5]^4'h1; end 8'h2b: begin outr <= outr^index[8:5]^4'h8; end 8'h2c: begin outr <= outr^index[8:5]^4'h4; end 8'h2d: begin outr <= outr^index[8:5]^4'h4; end 8'h2e: begin outr <= outr^index[8:5]^4'he; end 8'h2f: begin outr <= outr^index[8:5]^4'h8; end 8'h30: begin outr <= outr^index[8:5]^4'ha; end 8'h31: begin outr <= outr^index[8:5]^4'h7; end 8'h32: begin outr <= outr^index[8:5]^4'h0; end 8'h33: begin outr <= outr^index[8:5]^4'h3; end 8'h34: begin outr <= outr^index[8:5]^4'h1; end 8'h35: begin outr <= outr^index[8:5]^4'h3; end 8'h36: begin outr <= outr^index[8:5]^4'h4; end 8'h37: begin outr <= outr^index[8:5]^4'h6; end 8'h38: begin outr <= outr^index[8:5]^4'h4; end 8'h39: begin outr <= outr^index[8:5]^4'hb; end 8'h3a: begin outr <= outr^index[8:5]^4'h7; end 8'h3b: begin outr <= outr^index[8:5]^4'h1; end 8'h3c: begin outr <= outr^index[8:5]^4'h2; end 8'h3d: begin outr <= outr^index[8:5]^4'h0; end 8'h3e: begin outr <= outr^index[8:5]^4'h2; end 8'h3f: begin outr <= outr^index[8:5]^4'ha; end 8'h40: begin outr <= outr^index[8:5]^4'h7; end 8'h41: begin outr <= outr^index[8:5]^4'h5; end 8'h42: begin outr <= outr^index[8:5]^4'h5; end 8'h43: begin outr <= outr^index[8:5]^4'h4; end 8'h44: begin outr <= outr^index[8:5]^4'h8; end 8'h45: begin outr <= outr^index[8:5]^4'h5; end 8'h46: begin outr <= outr^index[8:5]^4'hf; end 8'h47: begin outr <= outr^index[8:5]^4'h6; end 8'h48: begin outr <= outr^index[8:5]^4'h7; end 8'h49: begin outr <= outr^index[8:5]^4'h4; end 8'h4a: begin outr <= outr^index[8:5]^4'ha; end 8'h4b: begin outr <= outr^index[8:5]^4'hd; end 8'h4c: begin outr <= outr^index[8:5]^4'hb; end 8'h4d: begin outr <= outr^index[8:5]^4'hf; end 8'h4e: begin outr <= outr^index[8:5]^4'hd; end 8'h4f: begin outr <= outr^index[8:5]^4'h7; end 8'h50: begin outr <= outr^index[8:5]^4'h9; end 8'h51: begin outr <= outr^index[8:5]^4'ha; end 8'h52: begin outr <= outr^index[8:5]^4'hf; end 8'h53: begin outr <= outr^index[8:5]^4'h3; end 8'h54: begin outr <= outr^index[8:5]^4'h1; end 8'h55: begin outr <= outr^index[8:5]^4'h0; end 8'h56: begin outr <= outr^index[8:5]^4'h2; end 8'h57: begin outr <= outr^index[8:5]^4'h9; end 8'h58: begin outr <= outr^index[8:5]^4'h2; end 8'h59: begin outr <= outr^index[8:5]^4'h4; end 8'h5a: begin outr <= outr^index[8:5]^4'hc; end 8'h5b: begin outr <= outr^index[8:5]^4'hd; end 8'h5c: begin outr <= outr^index[8:5]^4'h3; end 8'h5d: begin outr <= outr^index[8:5]^4'hb; end 8'h5e: begin outr <= outr^index[8:5]^4'hd; end 8'h5f: begin outr <= outr^index[8:5]^4'h7; end 8'h60: begin outr <= outr^index[8:5]^4'h7; end 8'h61: begin outr <= outr^index[8:5]^4'h3; end 8'h62: begin outr <= outr^index[8:5]^4'h3; end 8'h63: begin outr <= outr^index[8:5]^4'hb; end 8'h64: begin outr <= outr^index[8:5]^4'h9; end 8'h65: begin outr <= outr^index[8:5]^4'h4; end 8'h66: begin outr <= outr^index[8:5]^4'h3; end 8'h67: begin outr <= outr^index[8:5]^4'h6; end 8'h68: begin outr <= outr^index[8:5]^4'h7; end 8'h69: begin outr <= outr^index[8:5]^4'h7; end 8'h6a: begin outr <= outr^index[8:5]^4'hf; end 8'h6b: begin outr <= outr^index[8:5]^4'h6; end 8'h6c: begin outr <= outr^index[8:5]^4'h8; end 8'h6d: begin outr <= outr^index[8:5]^4'he; end 8'h6e: begin outr <= outr^index[8:5]^4'h4; end 8'h6f: begin outr <= outr^index[8:5]^4'h6; end 8'h70: begin outr <= outr^index[8:5]^4'hc; end 8'h71: begin outr <= outr^index[8:5]^4'h9; end 8'h72: begin outr <= outr^index[8:5]^4'h5; end 8'h73: begin outr <= outr^index[8:5]^4'ha; end 8'h74: begin outr <= outr^index[8:5]^4'h7; end 8'h75: begin outr <= outr^index[8:5]^4'h0; end 8'h76: begin outr <= outr^index[8:5]^4'h1; end 8'h77: begin outr <= outr^index[8:5]^4'he; end 8'h78: begin outr <= outr^index[8:5]^4'ha; end 8'h79: begin outr <= outr^index[8:5]^4'h7; end 8'h7a: begin outr <= outr^index[8:5]^4'hf; end 8'h7b: begin outr <= outr^index[8:5]^4'he; end 8'h7c: begin outr <= outr^index[8:5]^4'h6; end 8'h7d: begin outr <= outr^index[8:5]^4'hc; end 8'h7e: begin outr <= outr^index[8:5]^4'hc; end 8'h7f: begin outr <= outr^index[8:5]^4'h0; end 8'h80: begin outr <= outr^index[8:5]^4'h0; end 8'h81: begin outr <= outr^index[8:5]^4'hd; end 8'h82: begin outr <= outr^index[8:5]^4'hb; end 8'h83: begin outr <= outr^index[8:5]^4'hc; end 8'h84: begin outr <= outr^index[8:5]^4'h2; end 8'h85: begin outr <= outr^index[8:5]^4'h8; end 8'h86: begin outr <= outr^index[8:5]^4'h3; end 8'h87: begin outr <= outr^index[8:5]^4'ha; end 8'h88: begin outr <= outr^index[8:5]^4'he; end 8'h89: begin outr <= outr^index[8:5]^4'h9; end 8'h8a: begin outr <= outr^index[8:5]^4'h1; end 8'h8b: begin outr <= outr^index[8:5]^4'h1; end 8'h8c: begin outr <= outr^index[8:5]^4'hc; end 8'h8d: begin outr <= outr^index[8:5]^4'h2; end 8'h8e: begin outr <= outr^index[8:5]^4'h2; end 8'h8f: begin outr <= outr^index[8:5]^4'hd; end 8'h90: begin outr <= outr^index[8:5]^4'h0; end 8'h91: begin outr <= outr^index[8:5]^4'h6; end 8'h92: begin outr <= outr^index[8:5]^4'h7; end 8'h93: begin outr <= outr^index[8:5]^4'hc; end 8'h94: begin outr <= outr^index[8:5]^4'hb; end 8'h95: begin outr <= outr^index[8:5]^4'h3; end 8'h96: begin outr <= outr^index[8:5]^4'h0; end 8'h97: begin outr <= outr^index[8:5]^4'hc; end 8'h98: begin outr <= outr^index[8:5]^4'hc; end 8'h99: begin outr <= outr^index[8:5]^4'hb; end 8'h9a: begin outr <= outr^index[8:5]^4'h6; end 8'h9b: begin outr <= outr^index[8:5]^4'h5; end 8'h9c: begin outr <= outr^index[8:5]^4'h5; end 8'h9d: begin outr <= outr^index[8:5]^4'h4; end 8'h9e: begin outr <= outr^index[8:5]^4'h7; end 8'h9f: begin outr <= outr^index[8:5]^4'he; end 8'ha0: begin outr <= outr^index[8:5]^4'hc; end 8'ha1: begin outr <= outr^index[8:5]^4'hc; end 8'ha2: begin outr <= outr^index[8:5]^4'h0; end 8'ha3: begin outr <= outr^index[8:5]^4'h1; end 8'ha4: begin outr <= outr^index[8:5]^4'hd; end 8'ha5: begin outr <= outr^index[8:5]^4'h3; end 8'ha6: begin outr <= outr^index[8:5]^4'hc; end 8'ha7: begin outr <= outr^index[8:5]^4'h2; end 8'ha8: begin outr <= outr^index[8:5]^4'h3; end 8'ha9: begin outr <= outr^index[8:5]^4'hd; end 8'haa: begin outr <= outr^index[8:5]^4'h5; end 8'hab: begin outr <= outr^index[8:5]^4'hb; end 8'hac: begin outr <= outr^index[8:5]^4'he; end 8'had: begin outr <= outr^index[8:5]^4'h0; end 8'hae: begin outr <= outr^index[8:5]^4'hf; end 8'haf: begin outr <= outr^index[8:5]^4'h9; end 8'hb0: begin outr <= outr^index[8:5]^4'hf; end 8'hb1: begin outr <= outr^index[8:5]^4'h7; end 8'hb2: begin outr <= outr^index[8:5]^4'h9; end 8'hb3: begin outr <= outr^index[8:5]^4'hf; end 8'hb4: begin outr <= outr^index[8:5]^4'he; end 8'hb5: begin outr <= outr^index[8:5]^4'h3; end 8'hb6: begin outr <= outr^index[8:5]^4'he; end 8'hb7: begin outr <= outr^index[8:5]^4'h8; end 8'hb8: begin outr <= outr^index[8:5]^4'hf; end 8'hb9: begin outr <= outr^index[8:5]^4'hd; end 8'hba: begin outr <= outr^index[8:5]^4'h3; end 8'hbb: begin outr <= outr^index[8:5]^4'h5; end 8'hbc: begin outr <= outr^index[8:5]^4'hd; end 8'hbd: begin outr <= outr^index[8:5]^4'ha; end 8'hbe: begin outr <= outr^index[8:5]^4'h7; end 8'hbf: begin outr <= outr^index[8:5]^4'he; end 8'hc0: begin outr <= outr^index[8:5]^4'h2; end 8'hc1: begin outr <= outr^index[8:5]^4'he; end 8'hc2: begin outr <= outr^index[8:5]^4'h9; end 8'hc3: begin outr <= outr^index[8:5]^4'hb; end 8'hc4: begin outr <= outr^index[8:5]^4'h0; end 8'hc5: begin outr <= outr^index[8:5]^4'h5; end 8'hc6: begin outr <= outr^index[8:5]^4'h9; end 8'hc7: begin outr <= outr^index[8:5]^4'h6; end 8'hc8: begin outr <= outr^index[8:5]^4'ha; end 8'hc9: begin outr <= outr^index[8:5]^4'hf; end 8'hca: begin outr <= outr^index[8:5]^4'h3; end 8'hcb: begin outr <= outr^index[8:5]^4'hb; end 8'hcc: begin outr <= outr^index[8:5]^4'he; end 8'hcd: begin outr <= outr^index[8:5]^4'h2; end 8'hce: begin outr <= outr^index[8:5]^4'h5; end 8'hcf: begin outr <= outr^index[8:5]^4'hf; end 8'hd0: begin outr <= outr^index[8:5]^4'h2; end 8'hd1: begin outr <= outr^index[8:5]^4'h9; end 8'hd2: begin outr <= outr^index[8:5]^4'hb; end 8'hd3: begin outr <= outr^index[8:5]^4'h8; end 8'hd4: begin outr <= outr^index[8:5]^4'h0; end 8'hd5: begin outr <= outr^index[8:5]^4'h2; end 8'hd6: begin outr <= outr^index[8:5]^4'hb; end 8'hd7: begin outr <= outr^index[8:5]^4'h2; end 8'hd8: begin outr <= outr^index[8:5]^4'ha; end 8'hd9: begin outr <= outr^index[8:5]^4'hf; end 8'hda: begin outr <= outr^index[8:5]^4'h8; end 8'hdb: begin outr <= outr^index[8:5]^4'h4; end 8'hdc: begin outr <= outr^index[8:5]^4'he; end 8'hdd: begin outr <= outr^index[8:5]^4'h6; end 8'hde: begin outr <= outr^index[8:5]^4'h9; end 8'hdf: begin outr <= outr^index[8:5]^4'h9; end 8'he0: begin outr <= outr^index[8:5]^4'h7; end 8'he1: begin outr <= outr^index[8:5]^4'h0; end 8'he2: begin outr <= outr^index[8:5]^4'h9; end 8'he3: begin outr <= outr^index[8:5]^4'h3; end 8'he4: begin outr <= outr^index[8:5]^4'h2; end 8'he5: begin outr <= outr^index[8:5]^4'h4; end 8'he6: begin outr <= outr^index[8:5]^4'h5; end 8'he7: begin outr <= outr^index[8:5]^4'h5; end 8'he8: begin outr <= outr^index[8:5]^4'hf; end 8'he9: begin outr <= outr^index[8:5]^4'ha; end 8'hea: begin outr <= outr^index[8:5]^4'hc; end 8'heb: begin outr <= outr^index[8:5]^4'hd; end 8'hec: begin outr <= outr^index[8:5]^4'h1; end 8'hed: begin outr <= outr^index[8:5]^4'h5; end 8'hee: begin outr <= outr^index[8:5]^4'h9; end 8'hef: begin outr <= outr^index[8:5]^4'h0; end 8'hf0: begin outr <= outr^index[8:5]^4'hd; end 8'hf1: begin outr <= outr^index[8:5]^4'hf; end 8'hf2: begin outr <= outr^index[8:5]^4'h4; end 8'hf3: begin outr <= outr^index[8:5]^4'ha; end 8'hf4: begin outr <= outr^index[8:5]^4'h8; end 8'hf5: begin outr <= outr^index[8:5]^4'he; end 8'hf6: begin outr <= outr^index[8:5]^4'he; end 8'hf7: begin outr <= outr^index[8:5]^4'h1; end 8'hf8: begin outr <= outr^index[8:5]^4'h6; end 8'hf9: begin outr <= outr^index[8:5]^4'h0; end 8'hfa: begin outr <= outr^index[8:5]^4'h5; end 8'hfb: begin outr <= outr^index[8:5]^4'h1; end 8'hfc: begin outr <= outr^index[8:5]^4'h8; end 8'hfd: begin outr <= outr^index[8:5]^4'h6; end 8'hfe: begin outr <= outr^index[8:5]^4'h1; end default: begin outr <= outr^index[8:5]^4'h6; end endcase // verilog_format: on end endmodule verilator-5.042/test_regress/t/t_duplicated_gen_blocks_bad.v0000644000542200017500000000056115101701376024714 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t; parameter X = 2; begin : block end begin : block end if (X > 0) begin : block1 end if (X > 1) begin : block1 end endmodule verilator-5.042/test_regress/t/t_math_precedence.py0000755000542200017500000000073415101701376023100 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_typedef_id_bad.v0000644000542200017500000000041415101701376022521 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 int i; class Cls #(parameter type P_T = i); endclass verilator-5.042/test_regress/t/t_sys_readmem_assoc.py0000755000542200017500000000132115101701376023463 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.files_identical(test.obj_dir + "/t_sys_writemem_c_b.mem", "t/t_sys_readmem_assoc__c_b.mem.out") test.files_identical(test.obj_dir + "/t_sys_writemem_w_h.mem", "t/t_sys_readmem_assoc__w_h.mem.out") test.passes() verilator-5.042/test_regress/t/t_dpi_accessors.py0000755000542200017500000000130515101701376022606 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # 8-Mar-2012: Modifications for this test contributed by Jeremy Bennett and # Jie Xu. import vltest_bootstrap test.scenarios('simulator') test.compile(make_top_shell=False, make_main=False, verilator_flags2=["-Wno-BLKANDNBLK -language 1800-2005 --exe", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_unroll_nested.py0000755000542200017500000000104115101701376022637 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=['+define+TEST_DISABLE']) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_width_cast.v0000644000542200017500000000156015101701376022761 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t; wire [5:0] b1 = 6'b101101; wire [5:0] b2 = 6'b011110; logic [5:0] a6; logic [9:0] a10; initial begin // issue #3417 a6 = b2 - b1; `checkh(a6, 6'h31); a10 = 10'(b2 - b1); `checkh(a10, 10'h3f1); // This being not 31 indicates operator expands `checkh($bits(10'(b1)), 10); `checkh($bits(10'(b2 - b1)), 10); `checkh($bits(b2 - b1), 6); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_lint_implicit_port.v0000644000542200017500000000115115101701376023502 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; logic oe; read r (.clk(clk), .data( ( ( oe == 1'd001 ) && implicit_write ) ) ); sets s (.clk(clk), .enable(implicit_write)); read u (.clk(clk), .data(~implicit_also)); endmodule module sets ( input clk, output enable ); assign enable = 1'b0; endmodule module read ( input clk, input data ); endmodule verilator-5.042/test_regress/t/t_opt_table_packed_array.out0000644000542200017500000000036515101701376024624 0ustar mahmoudyfreeshellcyle 0 = { 3, 2, 1, 0 } cyle 1 = { 4, 3, 2, 1 } cyle 2 = { 5, 4, 3, 4 } cyle 3 = { 15, 15, 15, 15 } cyle 4 = { 7, 6, 5, 4 } cyle 5 = { 8, 7, 6, 5 } cyle 6 = { 15, 15, 15, 15 } cyle 7 = { 15, 15, 15, 15 } *-* All Finished *-* verilator-5.042/test_regress/t/t_alw_split_cond.v0000644000542200017500000000242415101701376022603 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 //bug1604 module t (/*AUTOARG*/ // Outputs two, // Inputs clk, aresetn, ten ); input wire clk; input wire aresetn; input reg [9:0] ten; output reg [1:0] two; // Passes with this //output reg [1:0] rx; //output reg [1:0] ry; function [1:0] func ( input [1:0] p0_x, input [1:0] p0_y, input [1:0] p1_x, input [1:0] p1_y, input [1:0] sel); reg [1:0] rx; reg [1:0] ry; `ifdef NOT_DEF // This way works rx = sel == 2'b10 ? p1_x : p0_x; ry = sel == 2'b10 ? p1_y : p0_y; `else // This way fails to compile if (sel == 2'b10) begin rx = p1_x; ry = p1_y; end else begin rx = p0_x; ry = p0_y; end `endif // Note rx and ry are unused //func = rx | ry; // Also passes func = 0; endfunction always @(*) begin two = func( ten[8 +: 2], ten[6 +: 2], ten[4 +: 2], ten[2 +: 2], ten[0 +: 2]); end endmodule verilator-5.042/test_regress/t/t_param_type_fwd.v0000644000542200017500000000164715101701376022611 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef enum { ONE } e_t; typedef struct { int m_i; } s_t; typedef union { int m_i; } u_t; class c_t; endclass interface class ic_t; endclass module sub; parameter type enum E_t; parameter type struct S_t; parameter type union U_t; parameter type class C_t; parameter type interface class IC_t; endmodule class Cls #(parameter type enum E_t, parameter type struct S_t, parameter type union U_t, parameter type class C_t, parameter type interface class IC_t); endclass module t; sub #(.E_t(e_t), .S_t(s_t), .U_t(u_t), .C_t(c_t), .IC_t(ic_t)) sub(); Cls #(.E_t(e_t), .S_t(s_t), .U_t(u_t), .C_t(c_t), .IC_t(ic_t)) c; initial begin c = new; end endmodule verilator-5.042/test_regress/t/t_a2_first_sc.py0000755000542200017500000000144315101701376022166 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # This test runs the very first time we've executed Verilator --sc # after building so we make sure to run with --gdbbt, so if it dumps we'll # get a trace. import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_a1_first_cc.v" test.leak_check_disable() DEBUG_QUIET = "--debug --debugi 0 --gdbbt --no-dump-tree" test.compile(verilator_flags2=[DEBUG_QUIET, "-sc --trace-vcd"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_tri_no_top.v0000644000542200017500000000252115101701376021754 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Paul Wright. // SPDX-License-Identifier: CC0-1.0 // The module t_tri_top_en_out is used to test that we can // force verilator to include __en and __out variables for // inouts. This test checks that the tests within that module // pass. They should pass regardless of the presence of C or // SystemVerilog in the level above. module t_tri_no_top (); timeunit 1ns; timeprecision 1ps; wire single_bit_io; wire bidir_single_bit_io; wire [63:0] bus_64_io; wire [63:0] bidir_bus_64_io; wire [127:0] bus_128_io; wire [127:0] bidir_bus_128_io; reg [3:0] drv_en; reg test_en; wire loop_done; wire sub_io; t_tri_top_en_out t_tri_top_en_out (.*); initial begin test_en = 1'b1; drv_en = 4'd0; forever begin @(loop_done); if (loop_done === 1'b1) begin if (drv_en == 4'hf) begin test_en = 1'b0; end else begin drv_en++; end end end end // initial begin endmodule // top verilator-5.042/test_regress/t/t_for_disable_dot.py0000755000542200017500000000073415101701376023111 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_vlt_warn_file_bad_b.vh0000644000542200017500000000040515101701376023711 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module sub; int warn_sub = 64'h1; endmodule verilator-5.042/test_regress/t/t_vpi_module.py0000755000542200017500000000124515101701376022133 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile( make_top_shell=False, make_main=False, make_pli=True, iv_flags2=["-g2005-sv"], verilator_flags2=["+define+USE_DOLLAR_C32 --exe --vpi --no-l2name", test.pli_filename]) test.execute(use_libvpi=True) test.passes() verilator-5.042/test_regress/t/t_wire_self_bad.py0000755000542200017500000000107615101701376022557 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--lint-only --language 1800-2017"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_assert_clock_event_unsup.out0000644000542200017500000000043515101701376025253 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_assert_clock_event_unsup.v:26:7: Unsupported: Clock event before property call and in its body 26 | @(negedge clk) | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_with.py0000755000542200017500000000073415101701376020745 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_math_arith.py0000755000542200017500000000073415101701376022112 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_module_input_default_value_3_bad.out0000644000542200017500000000057715101701376026607 0ustar mahmoudyfreeshell%Error-ASSIGNIN: t/t_module_input_default_value_3_bad.v:16:11: Assigning to input/const variable: 'i' : ... note: In instance 't.u_dut_should_fail_compile1' 16 | initial i = 1'b0; | ^ ... For error description see https://verilator.org/warn/ASSIGNIN?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_constraint_inheritance.py0000755000542200017500000000104615101701376024524 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_xml_flat_vlvbound.py0000755000542200017500000000135315101701376023515 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') out_filename = test.obj_dir + "/V" + test.name + ".xml" test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only', '--flatten'], verilator_make_gmake=False, make_top_shell=False, make_main=False) test.files_identical(out_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_param_real.py0000755000542200017500000000073415101701376022075 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_dpi_argtype_bad.out0000644000542200017500000000066115101701376023262 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_dpi_argtype_bad.v:13:41: Unsupported: DPI argument of type REFDTYPE 'foo_t' : ... For best portability, use bit, byte, int, or longint 13 | import "DPI-C" task dpix_twice(foo_t arg); | ^~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_timing_clkgen2.py0000755000542200017500000000100715101701376022660 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary -Wwarn-BLKSEQ"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_timing_nba_1.py0000755000542200017500000000077115101701376022322 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_runflag_bad__a.out0000644000542200017500000000013215101701376023041 0ustar mahmoudyfreeshell%Error: COMMAND_LINE:0: Unknown runtime argument: +verilator+bad+flag+testing Aborting... verilator-5.042/test_regress/t/t_flag_make_json.py0000755000542200017500000000176115101701376022732 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_flag_make_cmake.v" test.compile(verilator_flags2=['--make json'], verilator_make_gmake=False, verilator_make_cmake=False) nout = test.run_capture("jq --version", check=False) version_match = re.search(r'jq-([0-9.]+)', nout, re.IGNORECASE) if not version_match: test.skip("jq is not installed") json_filename = test.obj_dir + "/" + test.vm_prefix + ".json" if not os.path.exists(json_filename): test.error(json_filename + " does not exist") test.run(cmd=['cat "' + json_filename + '" | jq ".version"']) test.passes() verilator-5.042/test_regress/t/t_assigndly_deep_ref.v0000644000542200017500000000265615101701376023437 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 interface Iface; bit clk; int x; clocking cb @(posedge clk); default input #0 output #0; inout x; endclocking endinterface class Foo; virtual Iface iface; function new(virtual Iface tmp); iface = tmp; endfunction task update(virtual Iface tmp); iface = tmp; endtask endclass class Bar; Foo foo; function new(Foo tmp); foo = tmp; endfunction task update(Foo tmp); foo = tmp; endtask task assignment(); foo.iface.cb.x <= 8; endtask endclass module t; Iface iface(); Iface iface2(); task clockSome(); #2; iface.clk = ~iface.clk; iface2.clk = ~iface2.clk; #2; iface.clk = ~iface.clk; iface2.clk = ~iface2.clk; endtask initial begin Foo foo = new(iface); Foo foo2 = new(iface2); Bar bar = new(foo); clockSome(); if (iface.x != 0) $stop; if (iface2.x != 0) $stop; bar.assignment(); clockSome(); if (iface.x != 8) $stop; if (iface2.x != 0) $stop; foo.update(iface2); clockSome(); if (iface.x != 8) $stop; if (iface2.x != 0) $stop; bar.update(foo2); clockSome(); if (iface.x != 8) $stop; if (iface2.x != 0) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_randomize_neasted_unsup.out0000644000542200017500000000057115101701376025072 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_randomize_neasted_unsup.v:17:41: Unsupported: randomize() nested in inline randomize() constraints 17 | if (a.randomize() with {rdata == aa.randomize();} == 0) $stop; | ^~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_param_sel_range_bad.out0000644000542200017500000000076415101701376024076 0ustar mahmoudyfreeshell%Warning-SELRANGE: t/t_param_sel_range.v:43:35: Selection index out of range: 7:7 outside 4:0 : ... note: In instance 't.u2' 43 | r_rst[i] <= r_rst[i-1]; | ^ ... For warning description see https://verilator.org/warn/SELRANGE?v=latest ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_flag_invalid2_bad.py0000755000542200017500000000102715101701376023275 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, verilator_flags2=['+invalid-plus'], expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_func_named.v0000644000542200017500000000172415101701376021703 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t; function automatic int f( int j = 1, int s = 0 ); return (j<<16) | s; endfunction initial begin `checkh( f(.j(2), .s(1)) , 32'h2_0001 ); `checkh( f(.s(1)) , 32'h1_0001 ); `checkh( f(, 1) , 32'h1_0001 ); `checkh( f(.j(2)) , 32'h2_0000 ); `checkh( f(.s(1), .j(2)) , 32'h2_0001 ); `checkh( f(.s(), .j()) , 32'h1_0000 ); `checkh( f(2) , 32'h2_0000 ); `checkh( f() , 32'h1_0000 ); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_trace_public.out0000644000542200017500000000473615101701376022610 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $var wire 1 5 CLK $end $var wire 1 6 RESET $end $scope module t $end $var wire 1 5 CLK $end $var wire 1 # RESET $end $scope module glbl $end $var wire 1 7 GSR $end $upscope $end $var wire 2 $ vec[3] [2:1] $end $var wire 2 % vec[4] [2:1] $end $var wire 32 & val [31:0] $end $scope module little $end $var wire 1 5 clk $end $var wire 8 ' i8 [0:7] $end $var wire 49 ( i48 [1:49] $end $var wire 128 * i128 [63:190] $end $upscope $end $scope module neg $end $var wire 1 5 clk $end $var wire 8 . i8 [0:-7] $end $var wire 48 / i48 [-1:-48] $end $var wire 128 1 i128 [63:-64] $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 1# b00 $ b00 % b00000000000000000000000000000000 & b00000000 ' b0000000000000000000000000000000000000000000000000 ( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 * b00000000 . b000000000000000000000000000000000000000000000000 / b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 1 05 16 17 #3 b11111111 ' b1111111111111111111111111111111111111111111111111 ( b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 * b11111111 . b111111111111111111111111111111111111111111111111 / b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 1 15 #6 05 #7 07 #9 0# b00000000 ' b0000000000000000000000000000000000000000000000000 ( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 * b00000000 . b000000000000000000000000000000000000000000000000 / b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 1 15 06 #12 05 #15 b00000000000000000000000000000001 & b11111111 ' b1111111111111111111111111111111111111111111111111 ( b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 * b11111111 . b111111111111111111111111111111111111111111111111 / b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 1 15 #18 05 #20 verilator-5.042/test_regress/t/t_forceable_var_cmt.py0000755000542200017500000000125315101701376023424 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.pli_filename = "t/t_forceable_var.cpp" test.top_filename = "t/t_forceable_var.v" test.compile(make_top_shell=False, make_main=False, verilator_flags2=['-DCMT=1', '--exe', test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_dpi_shortcircuit.v0000644000542200017500000002230715101701376023162 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VCS `define NO_SHORTREAL `endif `ifdef NC `define NO_SHORTREAL `endif `ifdef VERILATOR // Unsupported `define NO_SHORTREAL `endif module t; // Note these are NOT pure. import "DPI-C" function void dpii_clear(); import "DPI-C" function int dpii_count(input int ctr); import "DPI-C" function bit dpii_inc0(input int ctr); import "DPI-C" function bit dpii_inc1(input int ctr); import "DPI-C" function bit dpii_incx(input int ctr, input bit value); integer i; integer j; bit b; int errors; task check1(integer line, bit got, bit ex); if (got != ex) begin $display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex); errors++; end endtask task check(integer line, int got, int ex); if (got != ex) begin $display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex); errors++; end endtask // Test loop initial begin // Spec says && || -> and ?: short circuit, no others do. // Check both constant & non constants. dpii_clear(); check1(`__LINE__, (1'b0 && dpii_inc0(0)), 1'b0); check1(`__LINE__, (1'b1 && dpii_inc0(1)), 1'b0); check1(`__LINE__, (dpii_inc0(2) && dpii_inc0(3)), 1'b0); check1(`__LINE__, (dpii_inc1(4) && dpii_inc0(5)), 1'b0); check1(`__LINE__, (dpii_inc0(6) && dpii_inc1(7)), 1'b0); check1(`__LINE__, (!(dpii_inc1(8) && dpii_inc1(9))), 1'b0); check1(`__LINE__, (dpii_inc0(10) && 1'b0), 1'b0); check1(`__LINE__, (dpii_inc0(11) && 1'b1), 1'b0); check (`__LINE__, dpii_count(0), 0); check (`__LINE__, dpii_count(1), 1); check (`__LINE__, dpii_count(2), 1); check (`__LINE__, dpii_count(3), 0); check (`__LINE__, dpii_count(4), 1); check (`__LINE__, dpii_count(5), 1); check (`__LINE__, dpii_count(6), 1); check (`__LINE__, dpii_count(7), 0); check (`__LINE__, dpii_count(8), 1); check (`__LINE__, dpii_count(9), 1); check (`__LINE__, dpii_count(10), 1); check (`__LINE__, dpii_count(11), 1); // dpii_clear(); check1(`__LINE__, (1'b0 & dpii_inc0(0)), 1'b0); check1(`__LINE__, (1'b1 & dpii_inc0(1)), 1'b0); check1(`__LINE__, (dpii_inc0(2) & dpii_inc0(3)), 1'b0); check1(`__LINE__, (dpii_inc1(4) & dpii_inc0(5)), 1'b0); check1(`__LINE__, (dpii_inc0(6) & dpii_inc1(7)), 1'b0); check1(`__LINE__, (!(dpii_inc1(8) & dpii_inc1(9))), 1'b0); check1(`__LINE__, (dpii_inc0(10) & 1'b0), 1'b0); check1(`__LINE__, (dpii_inc0(11) & 1'b1), 1'b0); check (`__LINE__, dpii_count(0), 1); check (`__LINE__, dpii_count(1), 1); check (`__LINE__, dpii_count(2), 1); check (`__LINE__, dpii_count(3), 1); check (`__LINE__, dpii_count(4), 1); check (`__LINE__, dpii_count(5), 1); check (`__LINE__, dpii_count(6), 1); check (`__LINE__, dpii_count(7), 1); check (`__LINE__, dpii_count(8), 1); check (`__LINE__, dpii_count(9), 1); check (`__LINE__, dpii_count(10), 1); check (`__LINE__, dpii_count(11), 1); // dpii_clear(); check1(`__LINE__, (1'b0 || dpii_inc0(0)), 1'b0); check1(`__LINE__, (1'b1 || dpii_inc0(1)), 1'b1); check1(`__LINE__, (dpii_inc0(2) || dpii_inc0(3)), 1'b0); check1(`__LINE__, (dpii_inc1(4) || dpii_inc0(5)), 1'b1); check1(`__LINE__, (dpii_inc0(6) || dpii_inc1(7)), 1'b1); check1(`__LINE__, (!(dpii_inc1(8) || dpii_inc1(9))), 1'b0); check1(`__LINE__, (dpii_inc0(10) || 1'b0), 1'b0); check1(`__LINE__, (dpii_inc0(11) || 1'b1), 1'b1); check (`__LINE__, dpii_count(0), 1); check (`__LINE__, dpii_count(1), 0); check (`__LINE__, dpii_count(2), 1); check (`__LINE__, dpii_count(3), 1); check (`__LINE__, dpii_count(4), 1); check (`__LINE__, dpii_count(5), 0); check (`__LINE__, dpii_count(6), 1); check (`__LINE__, dpii_count(7), 1); check (`__LINE__, dpii_count(8), 1); check (`__LINE__, dpii_count(9), 0); check (`__LINE__, dpii_count(10), 1); check (`__LINE__, dpii_count(11), 1); // dpii_clear(); check1(`__LINE__, (1'b0 | dpii_inc0(0)), 1'b0); check1(`__LINE__, (1'b1 | dpii_inc0(1)), 1'b1); check1(`__LINE__, (dpii_inc0(2) | dpii_inc0(3)), 1'b0); check1(`__LINE__, (dpii_inc1(4) | dpii_inc0(5)), 1'b1); check1(`__LINE__, (dpii_inc0(6) | dpii_inc1(7)), 1'b1); check1(`__LINE__, (!(dpii_inc1(8) | dpii_inc1(9))), 1'b0); check1(`__LINE__, (dpii_inc0(10) | 1'b0), 1'b0); check1(`__LINE__, (dpii_inc0(11) | 1'b1), 1'b1); check (`__LINE__, dpii_count(0), 1); check (`__LINE__, dpii_count(1), 1); check (`__LINE__, dpii_count(2), 1); check (`__LINE__, dpii_count(3), 1); check (`__LINE__, dpii_count(4), 1); check (`__LINE__, dpii_count(5), 1); check (`__LINE__, dpii_count(6), 1); check (`__LINE__, dpii_count(7), 1); check (`__LINE__, dpii_count(8), 1); check (`__LINE__, dpii_count(9), 1); check (`__LINE__, dpii_count(10), 1); check (`__LINE__, dpii_count(11), 1); // dpii_clear(); check1(`__LINE__, (1'b0 -> dpii_inc0(0)), 1'b1); check1(`__LINE__, (1'b1 -> dpii_inc0(1)), 1'b0); check1(`__LINE__, (dpii_inc0(2) -> dpii_inc0(3)), 1'b1); check1(`__LINE__, (dpii_inc1(4) -> dpii_inc0(5)), 1'b0); check1(`__LINE__, (dpii_inc0(6) -> dpii_inc1(7)), 1'b1); check1(`__LINE__, (!(dpii_inc1(8) -> dpii_inc1(9))), 1'b0); check (`__LINE__, dpii_count(0), 0); check (`__LINE__, dpii_count(1), 1); check (`__LINE__, dpii_count(2), 1); check (`__LINE__, dpii_count(3), 0); check (`__LINE__, dpii_count(4), 1); check (`__LINE__, dpii_count(5), 1); check (`__LINE__, dpii_count(6), 1); check (`__LINE__, dpii_count(7), 0); check (`__LINE__, dpii_count(8), 1); check (`__LINE__, dpii_count(9), 1); // dpii_clear(); check1(`__LINE__, (1'b0 ? dpii_inc0(0) : dpii_inc0(1)), 1'b0); check1(`__LINE__, (1'b1 ? dpii_inc0(2) : dpii_inc0(3)), 1'b0); check1(`__LINE__, (dpii_inc0(4) ? dpii_inc0(5) : dpii_inc0(6)), 1'b0); check1(`__LINE__, (dpii_inc1(7) ? dpii_inc0(8) : dpii_inc0(9)), 1'b0); check (`__LINE__, dpii_count(0), 0); check (`__LINE__, dpii_count(1), 1); check (`__LINE__, dpii_count(2), 1); check (`__LINE__, dpii_count(3), 0); check (`__LINE__, dpii_count(4), 1); check (`__LINE__, dpii_count(5), 0); check (`__LINE__, dpii_count(6), 1); check (`__LINE__, dpii_count(7), 1); check (`__LINE__, dpii_count(8), 1); check (`__LINE__, dpii_count(9), 0); // dpii_clear(); check1(`__LINE__, (1'b0 * dpii_inc0(0)), 1'b0); check1(`__LINE__, (1'b1 * dpii_inc0(1)), 1'b0); check1(`__LINE__, (dpii_inc0(2) * dpii_inc0(3)), 1'b0); check1(`__LINE__, (dpii_inc1(4) * dpii_inc0(5)), 1'b0); check1(`__LINE__, (dpii_inc0(6) * dpii_inc1(7)), 1'b0); check1(`__LINE__, (!(dpii_inc1(8) * dpii_inc1(9))), 1'b0); check (`__LINE__, dpii_count(0), 1); check (`__LINE__, dpii_count(1), 1); check (`__LINE__, dpii_count(2), 1); check (`__LINE__, dpii_count(3), 1); check (`__LINE__, dpii_count(4), 1); check (`__LINE__, dpii_count(5), 1); check (`__LINE__, dpii_count(6), 1); check (`__LINE__, dpii_count(7), 1); check (`__LINE__, dpii_count(8), 1); check (`__LINE__, dpii_count(9), 1); // dpii_clear(); check1(`__LINE__, (1'b0 + dpii_inc0(0)), 1'b0); check1(`__LINE__, (1'b1 + dpii_inc0(1)), 1'b1); check1(`__LINE__, (dpii_inc0(2) + dpii_inc0(3)), 1'b0); check1(`__LINE__, (dpii_inc1(4) + dpii_inc0(5)), 1'b1); check1(`__LINE__, (dpii_inc0(6) + dpii_inc1(7)), 1'b1); check1(`__LINE__, (dpii_inc1(8) + dpii_inc1(9)), 1'b0); check (`__LINE__, dpii_count(0), 1); check (`__LINE__, dpii_count(1), 1); check (`__LINE__, dpii_count(2), 1); check (`__LINE__, dpii_count(3), 1); check (`__LINE__, dpii_count(4), 1); check (`__LINE__, dpii_count(5), 1); check (`__LINE__, dpii_count(6), 1); check (`__LINE__, dpii_count(7), 1); check (`__LINE__, dpii_count(8), 1); check (`__LINE__, dpii_count(9), 1); // // Something a lot more complicated dpii_clear(); for (i=0; i<64; i++) begin b = ( ((dpii_incx(0,i[0]) && (dpii_incx(1,i[1]) || dpii_incx(2,i[2]) | dpii_incx(3,i[3]))) // | not || || dpii_incx(4,i[4])) -> dpii_incx(5,i[5])); end check (`__LINE__, dpii_count(0), 64); check (`__LINE__, dpii_count(1), 32); check (`__LINE__, dpii_count(2), 16); check (`__LINE__, dpii_count(3), 16); check (`__LINE__, dpii_count(4), 36); check (`__LINE__, dpii_count(5), 46); if (|errors) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_assert_implication.py0000755000542200017500000000077615101701376023671 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--assert --cc']) test.execute() test.passes() verilator-5.042/test_regress/t/t_queue_method3_bad.v0000644000542200017500000000116415101701376023157 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; typedef struct packed { int x, y; } point; initial begin point points_q[$]; point points_qv[$]; points_q.push_back(point'{1, 2}); // `index` should be treated as normal member select, // but the member is not present in the struct points_qv = points_q.find_first(a) with (a.x.index == 0); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_randomize_method_complex_bad.v0000644000542200017500000000065115101701376025467 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class Cls; Cls f; rand int r; endclass module t; Cls x = new; int i; initial $display( x.f.randomize(), x.f.randomize() with { r < 5; }, i.randomize() with { v < 5; }); endmodule verilator-5.042/test_regress/t/t_select_bad_range3.py0000755000542200017500000000077615101701376023324 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_public_clk.py0000755000542200017500000000106015101701376022072 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_dpi_export_bad.out0000644000542200017500000000050515101701376023125 0ustar mahmoudyfreeshell%Error: t/t_dpi_export_bad.v:10:24: Can't find definition of exported task/function: 'dpix_bad_missing' 10 | export "DPI-C" task dpix_bad_missing; | ^~~~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_property_sexpr_parse_unsup.out0000644000542200017500000000461115101701376025675 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:29:39: Unsupported: ## (in sequence expression) 29 | assert property (@(posedge clk) val ##1 val) $display("[%0t] var with single delay stmt, fileline:%d", $time, 29); | ^~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:30:43: Unsupported: ## (in sequence expression) 30 | assert property (@(posedge clk) ##1 val ##2 val) $display("[%0t] sequence stmt, fileline:%d", $time, 30); | ^~ %Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:71:14: Unsupported: sequence match items 71 | ($rose(a), l_b = b) |-> ##[3:10] q[l_b]; | ^ %Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:71:29: Unsupported: ## range cycle delay range expression 71 | ($rose(a), l_b = b) |-> ##[3:10] q[l_b]; | ^~ %Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:70:13: Unsupported: property variable declaration 70 | integer l_b; | ^~~ %Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:88:16: Unsupported: sequence match items 88 | (count == 0, l_t = $realtime) ##1 (count == 7)[->1] |-> $realtime - l_t < 50.5; | ^ %Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:88:51: Unsupported: [-> boolean abbrev expression 88 | (count == 0, l_t = $realtime) ##1 (count == 7)[->1] |-> $realtime - l_t < 50.5; | ^~~ %Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:88:54: Unsupported: boolean abbrev (in sequence expression) 88 | (count == 0, l_t = $realtime) ##1 (count == 7)[->1] |-> $realtime - l_t < 50.5; | ^ %Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:88:35: Unsupported: ## (in sequence expression) 88 | (count == 0, l_t = $realtime) ##1 (count == 7)[->1] |-> $realtime - l_t < 50.5; | ^~ %Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:86:14: Unsupported: property variable declaration 86 | realtime l_t; | ^~~ %Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:92:31: Unsupported: ## (in sequence expression) 92 | assert property (@clk not a ##1 b); | ^~ %Error: Exiting due to verilator-5.042/test_regress/t/t_unroll_signed.v0000644000542200017500000000771215101701376022453 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; // Check empty blocks task EmptyFor; /* verilator public */ integer i; begin for (i = 0; i < 2; i = i+1) begin end end endtask // Check look unroller reg signed signed_tests_only = 1'sb1; integer total; integer i; reg [31:0] iu; reg [31:0] dly_to_ensure_was_unrolled [1:0]; reg [2:0] i3; integer cyc; initial cyc = 0; always @ (posedge clk) begin cyc <= cyc + 1; case (cyc) 1: begin // >= signed total = 0; for (i=5; i>=0; i=i-1) begin total = total - i -1; dly_to_ensure_was_unrolled[i] <= i; end if (total != -21) $stop; end 2: begin // > signed total = 0; for (i=5; i>0; i=i-1) begin total = total - i -1; dly_to_ensure_was_unrolled[i] <= i; end if (total != -20) $stop; end 3: begin // < signed total = 0; for (i=1; i<5; i=i+1) begin total = total - i -1; dly_to_ensure_was_unrolled[i] <= i; end if (total != -14) $stop; end 4: begin // <= signed total = 0; for (i=1; i<=5; i=i+1) begin total = total - i -1; dly_to_ensure_was_unrolled[i] <= i; end if (total != -20) $stop; end // UNSIGNED 5: begin // >= unsigned total = 0; for (iu=5; iu>=1; iu=iu-1) begin total = total - iu -1; dly_to_ensure_was_unrolled[iu] <= iu; end if (total != -20) $stop; end 6: begin // > unsigned total = 0; for (iu=5; iu>1; iu=iu-1) begin total = total - iu -1; dly_to_ensure_was_unrolled[iu] <= iu; end if (total != -18) $stop; end 7: begin // < unsigned total = 0; for (iu=1; iu<5; iu=iu+1) begin total = total - iu -1; dly_to_ensure_was_unrolled[iu] <= iu; end if (total != -14) $stop; end 8: begin // <= unsigned total = 0; for (iu=1; iu<=5; iu=iu+1) begin total = total - iu -1; dly_to_ensure_was_unrolled[iu] <= iu; end if (total != -20) $stop; end //=== 9: begin // mostly cover a small index total = 0; for (i3=3'd0; i3<3'd7; i3=i3+3'd1) begin total = total - {29'd0,i3} -1; dly_to_ensure_was_unrolled[i3[0]] <= 0; end if (total != -28) $stop; end //=== 10: begin // mostly cover a small index total = 0; for (i3=0; i3<3'd7; i3=i3+3'd1) begin total = total - {29'd0,i3} -1; dly_to_ensure_was_unrolled[i3[0]] <= 0; end if (total != -28) $stop; end //=== 11: begin // width violation on <, causes extend total = 0; for (i3=3'd0; i3<7; i3=i3+1) begin total = total - {29'd0,i3} -1; dly_to_ensure_was_unrolled[i3[0]] <= 0; end if (total != -28) $stop; end //=== // width violation on <, causes extend signed // Unsupported as yet //=== 19: begin $write("*-* All Finished *-*\n"); $finish; end default: ; endcase end endmodule verilator-5.042/test_regress/t/t_class_fwd_cc.v0000644000542200017500000000111015101701376022203 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package Pkg; typedef class Fwd; virtual class Virt; pure virtual function Fwd get_root(); endclass class Ext extends Virt; virtual function Fwd get_root(); return Fwd::m_uvm_get_root(); endfunction endclass class Fwd; static function Fwd m_uvm_get_root(); return null; endfunction endclass endpackage verilator-5.042/test_regress/t/t_var_dup2_bad.py0000755000542200017500000000076615101701376022327 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_array_index_increment.v0000644000542200017500000000526515101701376024161 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; string test_string = "abcd"; int array3d[2][3][4] = '{ '{ '{ 0, 1, 2, 3}, '{ 4, 5, 6, 7}, '{ 8, 9, 10, 11} }, '{ '{ 12, 13, 14, 15}, '{ 16, 17, 18, 19}, '{ 20, 21, 22, 23} } }; int pos; int val; int i; byte b; int data[4] = '{1, 2, 3, 4}; generate genvar j; int gdata[4]; for (j=0; j < 5; j++) begin initial if (j >= 5) $stop; end for (j=0; j < 5; ++j) begin initial if (j >= 5) $stop; end for (j=10; j >= 5; j--) begin initial if (j < 5) $stop; end for (j=10; j >= 5; --j) begin initial if (j < 5) $stop; end endgenerate initial begin pos = 0; pos++; if (pos != 1) $stop; array3d[0][0][0]++; if (array3d[0][0][0] != 1) $stop; --array3d[0][0][0]; if (array3d[0][0][0] != 0) $stop; pos = 2; b = test_string[--pos]; if (b !== "b") $stop; if (pos !== 1) $stop; pos = 1; b = test_string[++pos]; if (b !== "c") $stop; if (pos !== 2) $stop; pos = 3; b = test_string[pos--]; if (b !== "d") $stop; if (pos !== 2) $stop; pos = 0; b = test_string[pos++]; if (b !== "a") $stop; if (pos !== 1) $stop; pos = 0; val = array3d[++pos][--pos][++pos]; if (pos !== 1) $stop; if (val !== 13) $stop; pos = 0; val = array3d[++pos][pos--][++pos]; if (pos !== 1) $stop; if (val !== 17) $stop; for (i=0; data[++i]<4;) begin // loop with multiple statements pos = i; val = data[i]; end if (pos !== 2) $stop; if (i !== 3) $stop; if (val !== 3) $stop; i = 0; while (data[i++]<4) begin // loop with multiple statements pos = i; val = data[i]; end if (pos !== 3) $stop; if (i !== 4) $stop; if (val !== 4) $stop; pos = 0; if (1 == 1) begin pos++; end if (pos != 1) $stop; pos = 0; if (1 == 1) pos++; if (pos != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_covergroup_with_sample_args_too_few_bad.py0000755000542200017500000000077415101701376030131 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dfg_4943.py0000755000542200017500000000070615101701376021214 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.passes() verilator-5.042/test_regress/t/t_alias_force.py0000755000542200017500000000073415101701376022241 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_langext_1.v0000644000542200017500000000232015101701376021457 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // A test of the +verilog1995ext+ and +verilog2001ext+ flags. // // This source code contains constructs that are valid in Verilog 2001 and // SystemVerilog 2005/2009, but not in Verilog 1995. So it should fail if we // set the language to be 1995, but not 2001. // // Compile only test, so no need for "All Finished" output. // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; wire [1:0] res; // Instantiate the test test test_i (// Outputs .res (res[1:0]), // Inputs .clk (clk), .in (1'b1)); endmodule module test (// Outputs res, // Inputs clk, in ); output reg [1:0] res; input clk; input in; // This is a Verilog 2001 test generate genvar i; for (i=0; i<2; i=i+1) begin always @(posedge clk) begin res[i:i] <= in; end end endgenerate endmodule verilator-5.042/test_regress/t/t_vpi_repetitive_cbs.py0000755000542200017500000000136215101701376023655 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(make_top_shell=False, make_main=False, make_pli=True, verilator_flags2=["--exe --vpi", test.pli_filename], iv_flags2=["-g2005-sv -D USE_VPI_NOT_DPI -DIVERILOG"], v_flags2=["+define+USE_VPI_NOT_DPI"]) test.execute(use_libvpi=True) test.passes() verilator-5.042/test_regress/t/t_queue_method3_bad.py0000755000542200017500000000076315101701376023351 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_opt_slice.py0000755000542200017500000000110215101701376021741 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--sc', '--stats']) test.file_grep(test.stats, r'Optimizations, Slice array assignments\s+(\d+)', 5) test.passes() verilator-5.042/test_regress/t/t_disable_within_task_unsup.v0000644000542200017500000000114515101701376025042 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 task disable_fork_blk; disable t.init.fork_blk; endtask module t; initial begin : init int x = 0; fork : fork_blk begin x = 1; disable_fork_blk(); x = 2; end begin #1; x = 3; end join if (x != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_struct_init.py0000755000542200017500000000073415101701376022341 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_cat.py0000755000542200017500000000145115101701376021714 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(make_top_shell=False, make_main=False, v_flags2=["--trace-vcd --exe", test.pli_filename]) test.execute() os.system("cat " + test.obj_dir + "/simpart_0000.vcd " + " " + test.obj_dir + "/simpart_0000_cat*.vcd > " + test.obj_dir + "/simall.vcd") test.vcd_identical(test.obj_dir + "/simall.vcd", test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_xml_tag.out0000644000542200017500000001264215101701376021602 0ustar mahmoudyfreeshell verilator-5.042/test_regress/t/t_fork_timing.py0000755000542200017500000000102415101701376022273 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_fork.v" test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_param_default_presv_bad.py0000755000542200017500000000115715101701376024623 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.top_filename = "t/t_param_default_bad.v" test.lint(verilator_flags2=["--lint-only --language 1800-2005"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_member_bad.out0000644000542200017500000000160015101701376023401 0ustar mahmoudyfreeshell%Error: t/t_class_member_bad.v:18:9: Member 'memb3' not found in class 'Cls2' : ... note: In instance 't' : ... Suggested alternative: 'memb2' 18 | c.memb3 = 3; | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Warning-WIDTHTRUNC: t/t_class_member_bad.v:18:15: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CONST '?32?sh3' generates 32 or 2 bits. : ... note: In instance 't' 18 | c.memb3 = 3; | ^ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_property_sexpr_bad.v0000644000542200017500000000076015101701376023516 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ // Inputs clk ); input clk; bit val; always @(negedge clk) begin $write("*-* All Finished *-*\n"); $finish; end assert property (@(posedge clk) ##1 not val) $display("[%0t] single delay with negated var stmt, fileline:%d", $time, `__LINE__); endmodule verilator-5.042/test_regress/t/t_clocking_react.py0000755000542200017500000000077115101701376022742 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_jumps_do_while.py0000755000542200017500000000077115101701376023003 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--assert']) test.execute() test.passes() verilator-5.042/test_regress/t/t_const_number_v_bad.v0000644000542200017500000000103215101701376023425 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Test of Verilog and SystemVerilog integer literal differences // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Ethan Sifferman. // SPDX-License-Identifier: CC0-1.0 module t; // "unbased_unsized_literal" is SystemVerilog only // Should fail with "NEWERSTD" wire [127:0] FOO1 = '0; wire [127:0] FOO2 = '1; wire [127:0] FOO3 = 'x; wire [127:0] FOO4 = 'X; wire [127:0] FOO5 = 'z; wire [127:0] FOO6 = 'Z; endmodule verilator-5.042/test_regress/t/t_alias_simple.py0000755000542200017500000000073415101701376022434 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_mod_automatic.py0000755000542200017500000000073415101701376022617 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_local_typedef_bad.v0000755000542200017500000000063215101701376024411 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; class Cls; local typedef bit t1; protected typedef bit t2; endclass Cls::t1 var1; // BAD: access error expected Cls::t2 var2; // BAD: access error expected endmodule verilator-5.042/test_regress/t/t_tri_inout2.py0000755000542200017500000000073415101701376022070 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_randomize_array.py0000755000542200017500000000104615101701376023155 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_delay.v0000644000542200017500000000247415101701376020705 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `timescale 100ns/1ns module t (/*AUTOARG*/ // Inputs clk ); input clk; int cyc; reg [31:0] dly0; wire [31:0] dly1; wire [31:0] dly2 = dly1 + 32'h1; wire [31:0] dly3; wire [31:0] dly4; typedef struct packed { int dly; } dly_s_t; dly_s_t dly_s; assign #(1.2000000000000000) dly1 = dly0 + 32'h1; assign #(sub.delay) dly3 = dly1 + 1; assign #sub.delay dly4 = dly1 + 1; sub sub(); always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 1) begin dly0 <= #0 32'h11; end else if (cyc == 2) begin dly0 <= #0.12 dly0 + 32'h12; end else if (cyc == 3) begin if (dly0 !== 32'h23) $stop; if (dly2 !== 32'h25) $stop; end else if (cyc == 4) begin dly_s.dly = 55; dly0 <= #(dly_s.dly) 32'h55; //dly0 <= # dly_s.dly 32'h55; // Unsupported, issue #2410 end else if (cyc == 99) begin if (dly3 !== 32'h57) $stop; $write("*-* All Finished *-*\n"); #100 $finish; end end endmodule module sub; realtime delay = 2.3; endmodule verilator-5.042/test_regress/t/t_inside_extend.py0000755000542200017500000000077315101701376022617 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["-Wno-WIDTH"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_clk_latchgate.v0000644000542200017500000001174515101701376022375 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // // -------------------------------------------------------- // Bug Description: // // Issue: The gated clock gclk_vld[0] toggles but dvld[0] // input to the flop does not propagate to the output // signal entry_vld[0] correctly. The value that propagates // is the new value of dvld[0] not the one just before the // posedge of gclk_vld[0]. // -------------------------------------------------------- // Define to see the bug with test failing with gated clock 'gclk_vld' // Comment out the define to see the test passing with ungated clock 'clk' `define GATED_CLK_TESTCASE 1 // A side effect of the problem is this warning, disabled by default // Test Bench module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; // Take CRC data and apply to testblock inputs wire [7:0] dvld = crc[7:0]; wire [7:0] ff_en_e1 = crc[15:8]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [7:0] entry_vld; // From test of Test.v wire [7:0] ff_en_vld; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .ff_en_vld (ff_en_vld[7:0]), .entry_vld (entry_vld[7:0]), // Inputs .clk (clk), .dvld (dvld[7:0]), .ff_en_e1 (ff_en_e1[7:0])); reg err_code; reg ffq_clk_active; reg [7:0] prv_dvld; initial begin err_code = 0; ffq_clk_active = 0; end always @ (posedge clk) begin prv_dvld = test.dvld; end always @ (negedge test.ff_entry_dvld_0.clk) begin ffq_clk_active = 1; if (test.entry_vld[0] !== prv_dvld[0]) err_code = 1; end // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x ", $time, cyc, crc); $display(" en=%b fen=%b d=%b ev=%b", test.flop_en_vld[0], test.ff_en_vld[0], test.dvld[0], test.entry_vld[0]); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; if (cyc<3) begin crc <= 64'h5aef0c8d_d70a4497; end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x\n", $time, cyc, crc); if (ffq_clk_active == 0) begin $display ("----"); $display ("%%Error: TESTCASE FAILED with no Clock arriving at FFQs"); $display ("----"); $stop; end else if (err_code) begin $display ("----"); $display ("%%Error: TESTCASE FAILED with invalid propagation of 'd' to 'q' of FFQs"); $display ("----"); $stop; end else begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module llq (clk, d, q); parameter WIDTH = 32; input clk; input [WIDTH-1:0] d; output [WIDTH-1:0] q; reg [WIDTH-1:0] qr; /* verilator lint_off COMBDLY */ /* verilator lint_off LATCH */ always @(clk or d) if (clk == 1'b0) qr <= d; /* verilator lint_on LATCH */ /* verilator lint_on COMBDLY */ assign q = qr; endmodule module ffq (clk, d, q); parameter WIDTH = 32; input clk; input [WIDTH-1:0] d; output [WIDTH-1:0] q; reg [WIDTH-1:0] qr; always @(posedge clk) qr <= d; assign q = qr; endmodule // DUT module module Test (/*AUTOARG*/ // Outputs ff_en_vld, entry_vld, // Inputs clk, dvld, ff_en_e1 ); input clk; input [7:0] dvld; input [7:0] ff_en_e1; output [7:0] ff_en_vld; output wire [7:0] entry_vld; wire [7:0] gclk_vld; wire [7:0] ff_en_vld; reg [7:0] flop_en_vld; always @(posedge clk) flop_en_vld <= ff_en_e1; // clock gating `ifdef GATED_CLK_TESTCASE assign gclk_vld = {8{clk}} & ff_en_vld; `else assign gclk_vld = {8{clk}}; `endif // latch for avoiding glitch on the clock gating control llq #(8) dp_ff_en_vld (.clk(clk), .d(flop_en_vld), .q(ff_en_vld)); // flops that use the gated clock signal ffq #(1) ff_entry_dvld_0 (.clk(gclk_vld[0]), .d(dvld[0]), .q(entry_vld[0])); ffq #(1) ff_entry_dvld_1 (.clk(gclk_vld[1]), .d(dvld[1]), .q(entry_vld[1])); ffq #(1) ff_entry_dvld_2 (.clk(gclk_vld[2]), .d(dvld[2]), .q(entry_vld[2])); ffq #(1) ff_entry_dvld_3 (.clk(gclk_vld[3]), .d(dvld[3]), .q(entry_vld[3])); ffq #(1) ff_entry_dvld_4 (.clk(gclk_vld[4]), .d(dvld[4]), .q(entry_vld[4])); ffq #(1) ff_entry_dvld_5 (.clk(gclk_vld[5]), .d(dvld[5]), .q(entry_vld[5])); ffq #(1) ff_entry_dvld_6 (.clk(gclk_vld[6]), .d(dvld[6]), .q(entry_vld[6])); ffq #(1) ff_entry_dvld_7 (.clk(gclk_vld[7]), .d(dvld[7]), .q(entry_vld[7])); endmodule verilator-5.042/test_regress/t/t_property_sexpr_unsup.py0000755000542200017500000000111015101701376024316 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert', '--timing', '--error-limit 1000'], fails=True) test.passes() verilator-5.042/test_regress/t/t_unoptflat_simple_bad.py0000755000542200017500000000112715101701376024162 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_unoptflat_simple.v" # Compile only test.compile(verilator_flags2=["-fno-dfg"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_typedef_circ_bad.out0000644000542200017500000000053615101701376023414 0ustar mahmoudyfreeshell%Error: t/t_typedef_circ_bad.v:8:9: Typedef's type is circular: a_t 8 | typedef a_t b_t; | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_typedef_circ_bad.v:9:9: Typedef's type is circular: b_t 9 | typedef b_t a_t; | ^~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_func_uninit.v0000644000542200017500000000127615101701376022127 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilator lint_off NORETURN function int zeroed; endfunction function automatic integer what_bit; input [31:0] a; // what_bit = 0; for (int i = 31; i >= 0; i = i - 1) begin if (a[i] == 1'b1) begin what_bit = i; end end endfunction module t; parameter ZERO = zeroed(); parameter PP = what_bit(0); initial begin if (ZERO != 0) $stop; if (PP != 'x) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_stream_bitqueue.py0000755000542200017500000000073415101701376023170 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_checker_top.v0000644000542200017500000000061315101701376022066 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Not super-sensical to have checker without module, but useful for --lint-only checker check_equal (bit clk, int a, int b); assert property (@(posedge clk) a == b); endchecker verilator-5.042/test_regress/t/t_unopt_converge_ndbg_bad.out0000644000542200017500000000013315101701376024774 0ustar mahmoudyfreeshell%Error: t/t_unopt_converge.v:7: Settle region did not converge after 100 tries Aborting... verilator-5.042/test_regress/t/t_preproc_dos.py0000755000542200017500000000212315101701376022303 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap import runpy test.scenarios('vlt') test.top_filename = test.obj_dir + "/" + test.name + ".v" test.golden_filename = test.obj_dir + "/" + test.name + ".out" # Rather then having to maintain a new .v and .out, add returns # to all lines of the existing t_preproc test. wholefile = test.file_contents(test.t_dir + "/t_preproc.v") wholefile = re.sub(r'\n', r'\r\n', wholefile) test.write_wholefile(test.obj_dir + "/" + test.name + ".v", wholefile) wholefile = test.file_contents(test.t_dir + "/t_preproc.out") wholefile = re.sub(r't/t_preproc.v', test.obj_dir + "/t_preproc_dos.v", wholefile) # Fix `line's test.write_wholefile(test.golden_filename, wholefile) runpy.run_path('t/t_preproc.py', globals()) verilator-5.042/test_regress/t/t_parse_eof_qqq_bad.py0000755000542200017500000000110515101701376023416 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=['--debug-preproc-passthru', '--no-std'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_param_in_func_noinline.py0000755000542200017500000000172715101701376024471 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_param_in_func.v" test.compile(verilator_flags2=["--stats", "+define+NO_INLINE=1"]) test.execute() # The parameter array should have been put in the constant pool if test.vlt_all: test.file_grep(test.stats, r'ConstPool, Tables emitted\s+(\d+)', 3) # Shouldn't have any references to the parameter array for filename in (test.glob_some(test.obj_dir + "/" + test.vm_prefix + "*.h") + test.glob_some(test.obj_dir + "/" + test.vm_prefix + "*.cpp")): test.file_grep_not(filename, r'digits') test.passes() verilator-5.042/test_regress/t/t_vlt_warn_bad.py0000755000542200017500000000114315101701376022427 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_vlt_warn.v" test.lint(verilator_flags2=["--lint-only t/t_vlt_warn_bad.vlt"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_constraint_mode_unsup.v0000644000542200017500000000077515101701376024233 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Packet; int m_one; static constraint cons { m_one > 0 && m_one < 2; } endclass module t; Packet p; initial begin p = new; $display("p.cons.constraint_mode()=%0d", p.cons.constraint_mode()); p.cons.constraint_mode(0); p.constraint_mode(0); end endmodule verilator-5.042/test_regress/t/t_timing_timescale.py0000755000542200017500000000103515101701376023302 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_clocking_empty_block.py0000755000542200017500000000077115101701376024154 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_verilated_header.v0000644000542200017500000000066515101701376023076 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `include "verilated.v" module t; initial begin `verilator_file_descriptor i; `coverage_block_off i = $fopen("/dev/null", "r"); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_array_pattern_bad3.out0000644000542200017500000000137015101701376023707 0ustar mahmoudyfreeshell%Error: t/t_array_pattern_bad3.v:20:15: Assignment pattern key used multiple times: 1 : ... note: In instance 't' 20 | 1: '1}; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_array_pattern_bad3.v:21:13: Assignment pattern with too many elements : ... note: In instance 't' 21 | arr = '{'0, '1, '0, '1}; | ^~ %Error: t/t_array_pattern_bad3.v:22:13: Assignment pattern missed initializing elements: 2 : ... note: In instance 't' 22 | arr = '{'0, '1}; | ^~ %Error: Exiting due to verilator-5.042/test_regress/t/t_alw_dly.py0000755000542200017500000000073415101701376021425 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_alias_var_bad.out0000644000542200017500000000100615101701376022706 0ustar mahmoudyfreeshell%Error: t/t_alias_var_bad.v:18:9: Only nets are allowed in alias (IEEE 1800-2023 10.11): 'a' : ... note: In instance 't' 18 | alias a = b; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_alias_var_bad.v:18:13: Only nets are allowed in alias (IEEE 1800-2023 10.11): 'b' : ... note: In instance 't' 18 | alias a = b; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_typedef_unused_bad.v0000644000542200017500000000040115101701376023424 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef logic ok_t; typedef fwd_undecl_t; verilator-5.042/test_regress/t/t_genvar_for_bad.v0000644000542200017500000000103515101701376022535 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ // Outputs ov, // Inputs clk, iv ); parameter N = 4; input clk; input [63:0] iv[N-1:0]; output logic [63:0] ov[N-1:0]; genvar i; generate always @(posedge clk) begin for (i = 0; i < N; i = i + 1) begin ov[i] <= iv[i]; end end endgenerate endmodule verilator-5.042/test_regress/t/t_lint_setout_bad_noinl.py0000755000542200017500000000114415101701376024344 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.top_filename = "t/t_lint_setout_bad.v" test.lint(verilator_flags2=["--lint-only -fno-inline"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_new_return.v0000644000542200017500000000124515101701376023157 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ clk ); input clk; class foo; int a; function new; a = 1; return; a = 2; endfunction function int get_a; return a; endfunction endclass foo foo_i; initial foo_i = new; always @(posedge clk) begin if (foo_i.get_a() == 1) begin $write("*-* All Finished *-*\n"); $finish; end else $stop; end endmodule verilator-5.042/test_regress/t/t_lint_in_inc_bad.v0000644000542200017500000000037015101701376022673 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `include "t_lint_in_inc_bad_1.vh" verilator-5.042/test_regress/t/t_unroll_complexcond.py0000755000542200017500000000073415101701376023700 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_tri_gate_nmos.py0000755000542200017500000000136115101701376022621 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_tri_gate.cpp" test.top_filename = "t/t_tri_gate.v" test.compile(make_top_shell=False, make_main=False, v_flags2=['+define+T_NMOS'], make_flags=['CPPFLAGS_ADD=-DT_NMOS'], verilator_flags2=["--exe", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_gate_primitives_implicit_net.py0000755000542200017500000000107415101701376025723 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["-Wno-fatal --no-skip-identical"], expect_filename=test.golden_filename) test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_max.v0000644000542200017500000000106115101701376021541 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( input clk ); int cyc; logic [95:0] wide1; logic [15:0] wide2[16]; // 256 bits logic deep1[24]; always @(posedge clk) begin wide1[31:0] = cyc; wide2[2] = cyc[15:0]; deep1[3] = cyc[0]; cyc <= cyc + 1; if (cyc == 5) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_assoc_compare.py0000755000542200017500000000073415101701376022610 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_x_rand_stability_add.out0000644000542200017500000000105615101701376024313 0ustar mahmoudyfreeshelluninitialized = 0xf5bbcbc0 x_assigned (initial) = 0x00000000 uninitialized2 = 0xa979eb54 big = 0xa20c93ac50d8c57d4c80949aa68e82775da6af98ce08f75dc6ccfad97b059a33 random_init = 0x952aaa76 top.t.the_sub_yes_inline_1 no_init 0x4a544f7798b83fc8 top.t.the_sub_yes_inline_2 no_init 0x19b7000ee0472c9 top.t.the_sub_no_inline_1 no_init 0x38121a34978975dd top.t.the_sub_no_inline_2 no_init 0x9022c84ae0fa3cf6 rand = 0xe3e54aaa rand = 0xe85acf2d rand = 0x15e12c6a rand = 0x0f7f28c0 rand = 0xe189c52a x_assigned = 0x486aeb2d Last rand = 0xf0700dbf *-* All Finished *-* verilator-5.042/test_regress/t/t_xml_output.v0000644000542200017500000000042215101701376022016 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module m (input clk); // verilator tag foo_op endmodule verilator-5.042/test_regress/t/t_math_div.py0000755000542200017500000000073415101701376021565 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_mod_interface_array4.py0000755000542200017500000000073415101701376024053 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_typename.v0000644000542200017500000000500515101701376021422 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define printtype(mytype, expec) $write({"\"", $typename(mytype), "\" ==? \"", expec, "\"\n"}); // Copied from 20.6.1 Type name function in IEEE 1800-2017 // source code // $typename would return typedef bit node; // "bit" node [2:0] X; // "bit [2:0]" int signed Y; // "int" package A; enum {A,B,C=99} X; // "enum{A=32'sd0,B=32'sd1,C=32'sd99}A::e$1" typedef bit [9:1'b1] word_t; // "A::bit[9:1]" localparam type WORD_T = word_t; endpackage : A import A::*; // moved into t // module top; // typedef struct {node A,B;} AB_t; // AB_t AB[10]; // "struct{bit A;bit B;}top.AB_t$[0:9]" // endmodule module t; real r; logic l; typedef bit mybit_t; localparam type MYBIT_T = mybit_t; mybit_t [2:0] bitp20; mybit_t bitu32 [3:2]; mybit_t bitu31 [3:1][4:5]; string assoc[longint]; int q[$]; int q3[$:3]; bit dyn[] = '{0, 0}; class Cls; int m_c; endclass typedef union {node A,B;} UAB_t; // From LRM typedef struct {node A,B;} AB_t; AB_t AB[10]; // "struct{bit A;bit B;}top.AB_t$[0:9]" initial begin // $write({$typename(real), "\n"}); `printtype(real, "real"); `printtype(bit, "bit"); `printtype(int, "int"); `printtype(logic, "logic"); `printtype(string, "string"); `printtype(r, "real"); `printtype(l, "logic"); `printtype(mybit_t, "bit"); `printtype(bitp20, "bit[2:0]"); `printtype(bitu32, "bit$[3:2]"); `printtype(bitu31, "bit$[3:1][4:5]"); $write("\n"); // from LRM `printtype(node, "bit"); `printtype(X, "bit[2:0]"); `printtype(Y, "int"); `printtype(A::word_t, "bit[9:1]"); `printtype(A::WORD_T, "bit[9:1]"); `printtype(assoc, "string$[longint]"); `printtype(q, "int$[$]"); `printtype(q3, "int$[$:3]"); // Some omit :3 - need it so != unbounded `printtype(dyn, "bit$[]"); $display; `printtype(A::X, "enum{A=32'sd0,B=32'sd1,C=32'sd99}A::"); // Some have just "enum " `printtype(AB_t, "struct{bit A;bit B;}"); `printtype(AB, "struct{bit A;bit B;}top.AB_t$[0:9]"); `printtype(UAB_t, "union{bit A;bit B;}"); `printtype(Cls, "class{}t.Cls "); $display; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_preproc_resolve.out0000644000542200017500000000114415101701376023353 0ustar mahmoudyfreeshell`begin_keywords "1800-2023" `verilator_config lint_off -rule NONSTD `begin_keywords "1800-2023" `timescale 1ns/1ps module top( input logic clk, input logic rst, output logic top_out ); submod u_submod ( .clk (clk), .rst (rst), .out_signal(top_out) ); endmodule `begin_keywords "1800-2023" `timescale 1ns/1ps module submod( input logic clk, input logic rst, output logic out_signal ); always_ff @(posedge clk or posedge rst) begin if (rst) begin out_signal <= 1'b0; end else begin out_signal <= ~out_signal; end end endmodule verilator-5.042/test_regress/t/t_interface_colon_bad.v0000644000542200017500000000056315101701376023544 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface iface; function static func; endfunction endinterface module t; initial begin iface::func(); // BAD $stop; end endmodule verilator-5.042/test_regress/t/t_x_rand_stability_zeros.out0000644000542200017500000000076315101701376024731 0ustar mahmoudyfreeshelluninitialized = 0x00000000 x_assigned (initial) = 0x00000000 uninitialized2 = 0x00000000 big = 0x0000000000000000000000000000000000000000000000000000000000000000 random_init = 0x952aaa76 top.t.the_sub_yes_inline_1 no_init 0x0 top.t.the_sub_yes_inline_2 no_init 0x0 top.t.the_sub_no_inline_1 no_init 0x0 top.t.the_sub_no_inline_2 no_init 0x0 rand = 0xe3e54aaa rand = 0xe85acf2d rand = 0x15e12c6a rand = 0x0f7f28c0 rand = 0xe189c52a x_assigned = 0x486aeb2d Last rand = 0xf0700dbf *-* All Finished *-* verilator-5.042/test_regress/t/t_array_index_side.py0000755000542200017500000000073715101701376023306 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_param_real2_collision.py0000755000542200017500000000105215101701376024224 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_param_real2.v" test.compile(verilator_flags2=["--debug-collision"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_hier_block_struct_nohier.py0000755000542200017500000000101215101701376025031 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_hier_block_struct.v" test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_math_shift_sel.py0000755000542200017500000000073415101701376022763 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_gen_mislevel.py0000755000542200017500000000073415101701376022443 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_genvar_for_bad.py0000755000542200017500000000076615101701376022735 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dpi_accessors_macros_inc.vh0000644000542200017500000000173515101701376024774 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Generic accessor macros for test of DPI accessors // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // // Contributed by Jeremy Bennett and Jie Xu // // See t_dpi_accessors.v for details of the test. This file should be included // by the top level module to define the generic accessor macros. // Accessor macros, to keep stuff concise `define R_ACCESS(type_spec, name, expr) \ export "DPI-C" function name``_read; \ function bit type_spec name``_read; \ name``_read = (expr); \ endfunction `define W_ACCESS(type_spec, name, expr) \ export "DPI-C" task name``_write; \ task name``_write; \ input bit type_spec in; \ expr = in; \ endtask `define RW_ACCESS(type_spec, name, expr) \ `R_ACCESS (type_spec, name, expr); \ `W_ACCESS (type_spec, name, expr) verilator-5.042/test_regress/t/t_math_imm2.py0000755000542200017500000000105615101701376021645 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_xml_flat_pub_mod.py0000755000542200017500000000135315101701376023303 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') out_filename = test.obj_dir + "/V" + test.name + ".xml" test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only', '--flatten'], verilator_make_gmake=False, make_top_shell=False, make_main=False) test.files_identical(out_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_eq_wild_unsup.py0000755000542200017500000000076315101701376022652 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_preproc_debugi.v0000644000542200017500000000073315101701376022574 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define FOO `define BAR(aa,bb) aa bb `FOO `BAR(aa,bb) `ifdef FOO `else `endif `ifndef FOO `elsif FOO `endif `define STRINGIFY(x) `"x`" `define CONCAT(a, b) a``b `STRINGIFY(x) `CONCAT(x,y) `undef FOO `undefineall `ifdef NEVER `error "should not get" `endif verilator-5.042/test_regress/t/t_sys_monitor_changes.py0000755000542200017500000000103515101701376024042 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_slice_cmp.py0000755000542200017500000000073415101701376021730 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_gen11.v0000644000542200017500000000131315101701376022531 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty. // SPDX-License-Identifier: CC0-1.0 // bug998 interface intf #(parameter PARAM = 0) (); logic val; function integer func (); return 5; endfunction endinterface module t1(intf mod_intf); initial begin $display("%m %d", mod_intf.val); end endmodule module t2(intf mod_intfs [1:0]); generate begin t1 t(.mod_intf(mod_intfs[0])); end endgenerate endmodule module t(); intf #(.PARAM(1)) my_intf [1:0] (); t2 t2 (.mod_intfs(my_intf)); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_opt_dead_task.py0000755000542200017500000000113015101701376022562 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--stats"]) if test.vlt_all: test.file_grep(test.stats, r'Optimizations, deadified FTasks\s+(\d+)', 6) test.execute() test.passes() verilator-5.042/test_regress/t/t_timing_clkgen2.v0000644000542200017500000000152015101701376022472 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `ifdef TEST_VERBOSE `define WRITE_VERBOSE(args) $write args `else `define WRITE_VERBOSE(args) `endif module t; logic clk = 0; logic clk_inv; int cnt1 = 0; int cnt2 = 0; always #4 clk = ~clk; always @(posedge clk) begin cnt1 <= cnt1 + 1; `WRITE_VERBOSE(("[%0t] clk (%b)\n", $time, clk)); end assign #2 clk_inv = ~clk; initial forever begin @(posedge clk_inv) cnt2++; `WRITE_VERBOSE(("[%0t] clk_inv (%b)\n", $time, clk_inv)); end initial #81 begin if (cnt1 != 10 && cnt2 != 10) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_reloop_cam.py0000755000542200017500000000136715101701376022115 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=[ "-unroll-count 1024", "--expand-limit 1024", test.wno_unopthreads_for_few_cores, "--stats" ]) test.execute() if test.vlt_all: test.file_grep(test.stats, r'Optimizations, Reloop iterations\s+(\d+)', 768) test.file_grep(test.stats, r'Optimizations, Reloops\s+(\d+)', 3) test.passes() verilator-5.042/test_regress/t/t_assert_inside_cond_bad.out0000644000542200017500000000025615101701376024612 0ustar mahmoudyfreeshell[10] %Error: t_assert_inside_cond.v:39: Assertion failed in top.t: unique case, but none matched for '12'h389' %Error: t/t_assert_inside_cond.v:39: Verilog $stop Aborting... verilator-5.042/test_regress/t/t_math_wide_bad.py0000755000542200017500000000076615101701376022546 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface_array3.py0000755000542200017500000000077115101701376023214 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--binary']) test.execute() test.passes() verilator-5.042/test_regress/t/t_dfg_synthesis.cpp0000644000542200017500000000246215101701376022772 0ustar mahmoudyfreeshell// // DESCRIPTION: Verilator: DFG optimizer equivalence testing // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 // #include #include #include #include #include void rngUpdate(uint64_t& x) { x ^= x << 13; x ^= x >> 7; x ^= x << 17; } int main(int, char**) { // Create contexts VerilatedContext ctx; // Create models Vref ref{&ctx}; Vopt opt{&ctx}; uint64_t rand_a = 0x5aef0c8dd70a4497; uint64_t rand_b = 0xf0c0a8dd75ae4497; uint64_t srand_a = 0x00fa8dcc7ae4957; uint64_t srand_b = 0x0fa8dc7ae3c9574; for (size_t n = 0; n < 200000; ++n) { // Update rngs rngUpdate(rand_a); rngUpdate(rand_b); rngUpdate(srand_a); rngUpdate(srand_b); // Assign inputs ref.rand_a = opt.rand_a = rand_a; ref.rand_b = opt.rand_b = rand_b; ref.srand_a = opt.srand_a = srand_a; ref.srand_b = opt.srand_b = srand_b; // Evaluate both models ref.eval(); opt.eval(); // Check equivalence #include "checks.h" // increment time ctx.timeInc(1); } std::cout << "*-* All Finished *-*\n"; } verilator-5.042/test_regress/t/t_math_red.v0000644000542200017500000000354315101701376021370 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc = 0; reg [67:0] r; wire and_reduce = &r; wire or_reduce = |r; wire xor_reduce = ^r; wire xnor_reduce = ~^r; wire check_equal = r == 68'hffff_ffff_ffff_ffff_f; always @(posedge clk) begin `ifdef TEST_VERBOSE $display("cyc=%0d, r = %x, and_reduce = %x, or=%x xor=%x check_equal = %x", cyc, r, and_reduce, or_reduce, xor_reduce, check_equal); `endif cyc <= cyc + 1; if (cyc == 1) begin r <= 68'd0; end else if (cyc == 10) begin `checkh(r, 68'h0000_0000_0000_0000_0); `checkh(and_reduce, '0); `checkh(or_reduce, '0); `checkh(xor_reduce, '0); `checkh(xnor_reduce, '1); r <= 68'hffff_ffff_ffff_ffff_e; end else if (cyc == 11) begin `checkh(r, 68'hffff_ffff_ffff_ffff_e); `checkh(and_reduce, '0); `checkh(or_reduce, '1); `checkh(xor_reduce, '1); `checkh(xnor_reduce, '0); r <= 68'hffff_ffff_ffff_ffff_f; end else if (cyc == 12) begin `checkh(r, 68'hffff_ffff_ffff_ffff_f); `checkh(and_reduce, '1); `checkh(or_reduce, '1); `checkh(xor_reduce, '0); `checkh(xnor_reduce, '1); end else if (cyc == 90) begin $write("*-* All Finished *-*\n"); $finish; end else begin r <= 68'd0; end end endmodule verilator-5.042/test_regress/t/t_assert_synth_full_vlt.out0000644000542200017500000000056515101701376024605 0ustar mahmoudyfreeshell[0] -Info: t_assert_synth.v:115: top.t.test_info: Start of $info test [0] -Info: t_assert_synth.v:116: top.t.test_info: Middle of $info test [0] -Info: t_assert_synth.v:117: top.t.test_info: End of $info test [40] %Error: t_assert_synth.v:40: Assertion failed in top.t: priority case, but non-match found for '2'h3' %Error: t/t_assert_synth.v:40: Verilog $stop Aborting... verilator-5.042/test_regress/t/t_gen_missing_bad2.v0000644000542200017500000000061015101701376022767 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; if ($test$plusargs("BAD-non-constant")) begin initial $stop; end case (1) $test$plusargs("BAD-non-constant"): initial $stop; endcase endmodule verilator-5.042/test_regress/t/t_tri_ifbegin.v0000644000542200017500000000216215101701376022062 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; tri pad_io_h; tri pad_io_l; sub sub (.*); endmodule module sub (/*AUTOARG*/ // Inouts pad_io_h, pad_io_l ); parameter USE = 1'b1; parameter DIFFERENTIAL = 1'b1; parameter BIDIR = 1'b1; inout pad_io_h; inout pad_io_l; wire [31:0] dqs_out_dtap_delay; generate if (USE) begin: output_strobe wire aligned_os_oe; wire aligned_strobe; if (BIDIR) begin reg sig_h_r = 1'b0; reg sig_l_r = 1'b0; always @* begin sig_h_r = ~aligned_os_oe ? aligned_strobe : 1'bz; if (DIFFERENTIAL) sig_l_r = ~aligned_os_oe ? ~aligned_strobe : 1'bz; end assign pad_io_h = sig_h_r; if (DIFFERENTIAL) assign pad_io_l = sig_l_r; end end endgenerate endmodule verilator-5.042/test_regress/t/t_randomize_queue_constraints.v0000644000542200017500000000252315101701376025425 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `define check_rand(cl, field, cond) \ begin \ longint prev_result; \ int ok = 0; \ if (!bit'(cl.randomize())) $stop; \ prev_result = longint'(field); \ if (!(cond)) $stop; \ repeat(9) begin \ longint result; \ if (!bit'(cl.randomize())) $stop; \ result = longint'(field); \ if (!(cond)) $stop; \ if (result != prev_result) ok = 1; \ prev_result = result; \ end \ if (ok != 1) $stop; \ end class Foo; rand int m_intQueue[$]; rand int m_idx; function new; m_intQueue = '{10{0}}; endfunction constraint int_queue_c { m_idx inside {[0:9]}; m_intQueue[m_idx] == m_idx + 1; foreach (m_intQueue[i]) { m_intQueue[i] inside {[0:127]}; } } endclass module t_randomize_queue_constraints; initial begin Foo foo = new; `check_rand(foo, foo.m_idx, foo.m_idx inside {[0:9]} && foo.m_intQueue[foo.m_idx] == foo.m_idx + 1); $display("Queue: %p", foo.m_intQueue); `check_rand(foo, foo.m_intQueue[3], foo.m_intQueue[5] inside {[0:127]}); $display("Queue: %p", foo.m_intQueue); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_trace_array_fst_sc.out0000644000542200017500000340127515101701376024013 0ustar mahmoudyfreeshell$date Tue Oct 7 13:26:27 2025 $end $version fstWriter $end $timescale 1ps $end $scope module top $end $scope module t $end $var wire 1 ! clk $end $var integer 32 " cyc [31:0] $end $scope struct biggie $end $var logic 131073 # d [131072:0] $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 # b00000000000000000000000000000000 " 0! $end #10 1! b00000000000000000000000000000001 " b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111110111011011111101011001110 # #15 0! #20 1! b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111101110110111111010110011100 # b00000000000000000000000000000010 " #25 0! #30 1! b00000000000000000000000000000011 " b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111011101101111110101100111000 # #35 0! #40 1! b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111110111011011111101011001110000 # b00000000000000000000000000000100 " #45 0! #50 1! b00000000000000000000000000000101 " b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111101110110111111010110011100000 # #55 0! #60 1! b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000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# b00000000000000000000000000000110 " #64 verilator-5.042/test_regress/t/t_trace_binary.v0000644000542200017500000000071415101701376022244 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" module t; int sig; initial begin sig = 10; $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); $dumpvars(); #20; sig = 20; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_array_mda.v0000644000542200017500000000352015101701376021537 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // msg2946 int A [7][1], B [8][1]; int a [1], b [1]; always_ff @(posedge clk) begin a <= A[crc[2:0]]; b <= B[crc[2:0]]; end wire [63:0] result = {a[0], b[0]}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; A[0][0] <= 32'h1_0; A[1][0] <= 32'h1_1; A[2][0] <= 32'h1_2; A[3][0] <= 32'h1_3; A[4][0] <= 32'h1_4; A[5][0] <= 32'h1_5; A[6][0] <= 32'h1_6; B[0][0] <= 32'h2_0; B[1][0] <= 32'h2_1; B[2][0] <= 32'h2_2; B[3][0] <= 32'h2_3; B[4][0] <= 32'h2_4; B[5][0] <= 32'h2_5; B[6][0] <= 32'h2_6; B[7][0] <= 32'h2_7; end else if (cyc<10) begin sum <= '0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h619f75c3a6d948bd if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_sys_fread.py0000755000542200017500000000140015101701376021740 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') def gen(filename): with open(filename, 'w', encoding="latin-1") as fh: for copy in range(0, 32): # pylint: disable=unused-variable for i in range(0, 256): fh.write(chr(i)) gen(test.obj_dir + "/t_sys_fread.mem") test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_preproc_eof4_bad.out0000644000542200017500000000026415101701376023341 0ustar mahmoudyfreeshell%Error: t/t_preproc_eof4_bad.v:8:1: Unterminated string ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_a3_selftest.py0000755000542200017500000000117215101701376022203 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_EXAMPLE.v" test.compile(verilator_flags2=['--debug-self-test'], verilator_make_gmake=False, make_top_shell=False, make_main=False) test.passes() verilator-5.042/test_regress/t/t_dpi_arg_inout_unpack.v0000644000542200017500000023030415101701376023766 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2020 by Yutetsu TAKATSUKASA. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VCS `define NO_TIME `endif `ifdef NC `define NO_TIME `define NO_INTEGER `define NO_SHORTREAL `endif `ifdef MS `define NO_BITS_TO_SCALAR `endif `ifdef VERILATOR `define NO_SHORTREAL `define NO_UNPACK_STRUCT //%Error-TASKNSVAR: Unsupported: Function/task input argument is not simple variable `define NO_INOUT_COMPLEX_TYPE `endif `ifdef NO_BITS_TO_SCALAR `define ARE_SAME(act, exp) ($bits((act)) == 1 ? (act) == ((exp) & 1) : (act) == (exp)) `else `define ARE_SAME(act, exp) ((act) == (($bits(act))'(exp))) `endif `define CHECK_VAL(act, exp) if (`ARE_SAME(act, exp)) begin \ if (ENABLE_VERBOSE_MESSAGE)$display(`"act`", ":", (act), " as expected"); \ end else begin \ $display("Mismatch %s expected:%d actual:%d at %d", `"act`", int'(exp), int'(act), `__LINE__); \ $stop; \ end `define CHECK_CHANDLE_VAL(act, exp) if ((act) == (exp)) begin \ if (ENABLE_VERBOSE_MESSAGE)$display(`"act`", ":non-null as expected"); \ end else begin \ $display("Mismatch %s expected:%s but %s at %d", `"act`", \ (exp) != null ? "null" : "non-null", \ (act) != null ? "null" : "non-null", `__LINE__); \ $stop; \ end `define CHECK_STRING_VAL(act, exp) if ((act) == (exp)) begin \ if (ENABLE_VERBOSE_MESSAGE)$display(`"act`", ":", (act), " as expected"); \ end else begin \ $display("Mismatch %s expected:%s actual:%s at %d", `"act`", (exp), (act), `__LINE__); \ $stop; \ end `define UPDATE_VAL(var, val) `CHECK_VAL(var, val); var += 1 `define UPDATE_0D(val) \ `UPDATE_VAL(val, 42) `define UPDATE_1D(val) \ `UPDATE_VAL(val[0], 43); \ `UPDATE_VAL(val[1], 44) `define UPDATE_2D(val) \ `UPDATE_VAL(val[0][1], 45); \ `UPDATE_VAL(val[1][1], 46); \ `UPDATE_VAL(val[2][1], 47) `define UPDATE_3D(val) \ `UPDATE_VAL(val[0][0][0], 48); \ `UPDATE_VAL(val[1][0][0], 49); \ `UPDATE_VAL(val[2][0][0], 50); \ `UPDATE_VAL(val[3][0][0], 51) `define UPDATE_1D1(val) \ `UPDATE_VAL(val[0], 52) `define UPDATE_2D1(val) \ `UPDATE_VAL(val[0][0], 53) `define UPDATE_3D1(val) \ `UPDATE_VAL(val[0][0][0], 54) `define CHECK_0D(val) \ `CHECK_VAL((val), 43) `define CHECK_1D(val) \ `CHECK_VAL(val[0], 44); \ `CHECK_VAL(val[1], 45) `define CHECK_2D(val) \ `CHECK_VAL(val[0][1], 46); \ `CHECK_VAL(val[1][1], 47); \ `CHECK_VAL(val[2][1], 48) `define CHECK_3D(val) \ `CHECK_VAL(val[0][0][0], 49); \ `CHECK_VAL(val[1][0][0], 50); \ `CHECK_VAL(val[2][0][0], 51); \ `CHECK_VAL(val[3][0][0], 52) `define CHECK_1D1(val) \ `CHECK_VAL(val[0], 53) `define CHECK_2D1(val) \ `CHECK_VAL(val[0][0], 54) `define CHECK_3D1(val) \ `CHECK_VAL(val[0][0][0], 55) `define CHECK_DOUBLE_VAL(act, exp) if ((act) == (exp)) begin \ if (ENABLE_VERBOSE_MESSAGE)$display("%s:%f as expected", `"act`", (act)); \ end else begin \ $display("Mismatch %s expected:%d actual:%f at %f", `"act`", (exp), (act), `__LINE__); \ $stop; \ end `define CHECK_DOUBLE_0D(val) \ `CHECK_DOUBLE_VAL((val), 43.0) `define CHECK_DOUBLE_1D(val) \ `CHECK_DOUBLE_VAL(val[0], 44.0); \ `CHECK_DOUBLE_VAL(val[1], 45.0) `define CHECK_DOUBLE_2D(val) \ `CHECK_DOUBLE_VAL(val[0][1], 46.0); \ `CHECK_DOUBLE_VAL(val[1][1], 47.0); \ `CHECK_DOUBLE_VAL(val[2][1], 48.0) `define CHECK_DOUBLE_3D(val) \ `CHECK_DOUBLE_VAL(val[0][0][0], 49.0); \ `CHECK_DOUBLE_VAL(val[1][0][0], 50.0); \ `CHECK_DOUBLE_VAL(val[2][0][0], 51.0); \ `CHECK_DOUBLE_VAL(val[3][0][0], 52.0) `define CHECK_DOUBLE_1D1(val) \ `CHECK_DOUBLE_VAL(val[0], 53.0) `define CHECK_DOUBLE_2D1(val) \ `CHECK_DOUBLE_VAL(val[0][0], 54.0) `define CHECK_DOUBLE_3D1(val) \ `CHECK_DOUBLE_VAL(val[0][0][0], 55.0) `define SET_VALUE_0D(val) \ /*verilator lint_off WIDTH */ \ val = 42 \ /*verilator lint_on WIDTH */ `define SET_VALUE_1D(val) \ /*verilator lint_off WIDTH */ \ val[0] = 43; val[1] = 44 \ /*verilator lint_on WIDTH */ `define SET_VALUE_2D(val) \ /*verilator lint_off WIDTH */ \ val[0][1] = 45; val[1][1] = 46; val[2][1] = 47 \ /*verilator lint_on WIDTH */ `define SET_VALUE_3D(val) \ /*verilator lint_off WIDTH */ \ val[3][2][1] = 42; \ val[2][1][0] = 43; val[2][1][1] = 44; \ val[1][0][1] = 45; val[1][1][1] = 46; val[1][2][1] = 47; \ val[0][0][0] = 48; val[1][0][0] = 49; val[2][0][0] = 50; val[3][0][0] = 51 \ /*verilator lint_on WIDTH */ `define SET_VALUE_1D1(val) \ /*verilator lint_off WIDTH */ \ val[0] = 52; \ /*verilator lint_on WIDTH */ `define SET_VALUE_2D1(val) \ /*verilator lint_off WIDTH */ \ val[0][0] = 53; \ /*verilator lint_on WIDTH */ `define SET_VALUE_3D1(val) \ /*verilator lint_off WIDTH */ \ val[0][0][0] = 54; \ /*verilator lint_on WIDTH */ module t; localparam ENABLE_VERBOSE_MESSAGE = 0; // Legal output argument types for DPI functions //====================================================================== // Type definitions //====================================================================== typedef byte byte_t; typedef byte_t byte_array_t[4][3][2]; typedef byte_t byte_array1_t[1][1][1]; typedef byte unsigned byte_unsigned_t; typedef byte_unsigned_t byte_unsigned_array_t[4][3][2]; typedef byte_unsigned_t byte_unsigned_array1_t[1][1][1]; typedef shortint shortint_t; typedef shortint_t shortint_array_t[4][3][2]; typedef shortint_t shortint_array1_t[1][1][1]; typedef shortint unsigned shortint_unsigned_t; typedef shortint_unsigned_t shortint_unsigned_array_t[4][3][2]; typedef shortint_unsigned_t shortint_unsigned_array1_t[1][1][1]; typedef int int_t; typedef int_t int_array_t[4][3][2]; typedef int_t int_array1_t[1][1][1]; typedef int unsigned int_unsigned_t; typedef int_unsigned_t int_unsigned_array_t[4][3][2]; typedef int_unsigned_t int_unsigned_array1_t[1][1][1]; typedef longint longint_t; typedef longint_t longint_array_t[4][3][2]; typedef longint_t longint_array1_t[1][1][1]; typedef longint unsigned longint_unsigned_t; typedef longint_unsigned_t longint_unsigned_array_t[4][3][2]; typedef longint_unsigned_t longint_unsigned_array1_t[1][1][1]; `ifndef NO_TIME typedef time time_t; typedef time_t time_array_t[4][3][2]; typedef time_t time_array1_t[1][1][1]; `endif `ifndef NO_INTEGER typedef integer integer_t; typedef integer_t integer_array_t[4][3][2]; typedef integer_t integer_array1_t[1][1][1]; `endif typedef real real_t; typedef real_t real_array_t[4][3][2]; typedef real_t real_array1_t[1][1][1]; `ifndef NO_SHORTREAL typedef shortreal shortreal_t; typedef shortreal_t shortreal_array_t[4][3][2]; typedef shortreal_t shortreal_array1_t[1][1][1]; `endif typedef chandle chandle_t; typedef chandle_t chandle_array_t[4][3][2]; typedef chandle_t chandle_array1_t[1][1][1]; typedef string string_t; typedef string_t string_array_t[4][3][2]; typedef string_t string_array1_t[1][1][1]; typedef bit bit1_t; typedef bit1_t bit1_array_t[4][3][2]; typedef bit1_t bit1_array1_t[1][1][1]; typedef bit [6:0] bit7_t; typedef bit7_t bit7_array_t[4][3][2]; typedef bit7_t bit7_array1_t[1][1][1]; typedef bit [120:0] bit121_t; typedef bit121_t bit121_array_t[4][3][2]; typedef bit121_t bit121_array1_t[1][1][1]; typedef logic logic1_t; typedef logic1_t logic1_array_t[4][3][2]; typedef logic1_t logic1_array1_t[1][1][1]; typedef logic [6:0] logic7_t; typedef logic7_t logic7_array_t[4][3][2]; typedef logic7_t logic7_array1_t[1][1][1]; typedef logic [120:0] logic121_t; typedef logic121_t logic121_array_t[4][3][2]; typedef logic121_t logic121_array1_t[1][1][1]; typedef struct packed { logic [6:0] val; } pack_struct_t; typedef pack_struct_t pack_struct_array_t[4][3][2]; typedef pack_struct_t pack_struct_array1_t[1][1][1]; `ifndef NO_UNPACK_STRUCT typedef struct { logic [120:0] val; } unpack_struct_t; typedef unpack_struct_t unpack_struct_array_t[4][3][2]; typedef unpack_struct_t unpack_struct_array1_t[1][1][1]; `endif //====================================================================== // Imports //====================================================================== // Returns non-null pointer import "DPI-C" function chandle get_non_null(); import "DPI-C" function void i_byte_0d(inout byte_t val); import "DPI-C" function void i_byte_1d(inout byte_t val[2]); import "DPI-C" function void i_byte_2d(inout byte_t val[3][2]); import "DPI-C" function void i_byte_3d(inout byte_array_t val); import "DPI-C" function void i_byte_1d1(inout byte_t val[1]); import "DPI-C" function void i_byte_2d1(inout byte_t val[1][1]); import "DPI-C" function void i_byte_3d1(inout byte_array1_t val); import "DPI-C" function void i_byte_unsigned_0d(inout byte unsigned val); import "DPI-C" function void i_byte_unsigned_1d(inout byte unsigned val[2]); import "DPI-C" function void i_byte_unsigned_2d(inout byte unsigned val[3][2]); import "DPI-C" function void i_byte_unsigned_3d(inout byte_unsigned_array_t val); import "DPI-C" function void i_byte_unsigned_1d1(inout byte unsigned val[1]); import "DPI-C" function void i_byte_unsigned_2d1(inout byte unsigned val[1][1]); import "DPI-C" function void i_byte_unsigned_3d1(inout byte_unsigned_array1_t val); import "DPI-C" function void i_shortint_0d(inout shortint val); import "DPI-C" function void i_shortint_1d(inout shortint val[2]); import "DPI-C" function void i_shortint_2d(inout shortint val[3][2]); import "DPI-C" function void i_shortint_3d(inout shortint_array_t val); import "DPI-C" function void i_shortint_1d1(inout shortint val[1]); import "DPI-C" function void i_shortint_2d1(inout shortint val[1][1]); import "DPI-C" function void i_shortint_3d1(inout shortint_array1_t val); import "DPI-C" function void i_shortint_unsigned_0d(inout shortint unsigned val); import "DPI-C" function void i_shortint_unsigned_1d(inout shortint unsigned val[2]); import "DPI-C" function void i_shortint_unsigned_2d(inout shortint unsigned val[3][2]); import "DPI-C" function void i_shortint_unsigned_3d(inout shortint_unsigned_array_t val); import "DPI-C" function void i_shortint_unsigned_1d1(inout shortint unsigned val[1]); import "DPI-C" function void i_shortint_unsigned_2d1(inout shortint unsigned val[1][1]); import "DPI-C" function void i_shortint_unsigned_3d1(inout shortint_unsigned_array1_t val); import "DPI-C" function void i_int_0d(inout int val); import "DPI-C" function void i_int_1d(inout int val[2]); import "DPI-C" function void i_int_2d(inout int val[3][2]); import "DPI-C" function void i_int_3d(inout int_array_t val); import "DPI-C" function void i_int_1d1(inout int val[1]); import "DPI-C" function void i_int_2d1(inout int val[1][1]); import "DPI-C" function void i_int_3d1(inout int_array1_t val); import "DPI-C" function void i_int_unsigned_0d(inout int unsigned val); import "DPI-C" function void i_int_unsigned_1d(inout int unsigned val[2]); import "DPI-C" function void i_int_unsigned_2d(inout int unsigned val[3][2]); import "DPI-C" function void i_int_unsigned_3d(inout int_unsigned_array_t val); import "DPI-C" function void i_int_unsigned_1d1(inout int unsigned val[1]); import "DPI-C" function void i_int_unsigned_2d1(inout int unsigned val[1][1]); import "DPI-C" function void i_int_unsigned_3d1(inout int_unsigned_array1_t val); import "DPI-C" function void i_longint_0d(inout longint val); import "DPI-C" function void i_longint_1d(inout longint val[2]); import "DPI-C" function void i_longint_2d(inout longint val[3][2]); import "DPI-C" function void i_longint_3d(inout longint_array_t val); import "DPI-C" function void i_longint_1d1(inout longint val[1]); import "DPI-C" function void i_longint_2d1(inout longint val[1][1]); import "DPI-C" function void i_longint_3d1(inout longint_array1_t val); import "DPI-C" function void i_longint_unsigned_0d(inout longint unsigned val); import "DPI-C" function void i_longint_unsigned_1d(inout longint unsigned val[2]); import "DPI-C" function void i_longint_unsigned_2d(inout longint unsigned val[3][2]); import "DPI-C" function void i_longint_unsigned_3d(inout longint_unsigned_array_t val); import "DPI-C" function void i_longint_unsigned_1d1(inout longint unsigned val[1]); import "DPI-C" function void i_longint_unsigned_2d1(inout longint unsigned val[1][1]); import "DPI-C" function void i_longint_unsigned_3d1(inout longint_unsigned_array1_t val); `ifndef NO_TIME import "DPI-C" function void i_time_0d(inout time val); import "DPI-C" function void i_time_1d(inout time val[2]); import "DPI-C" function void i_time_2d(inout time val[3][2]); import "DPI-C" function void i_time_3d(inout time_array_t val); import "DPI-C" function void i_time_1d1(inout time val[1]); import "DPI-C" function void i_time_2d1(inout time val[1][1]); import "DPI-C" function void i_time_3d1(inout time_array1_t val); `endif `ifndef NO_INTEGER import "DPI-C" function void i_integer_0d(inout integer val); import "DPI-C" function void i_integer_1d(inout integer val[2]); import "DPI-C" function void i_integer_2d(inout integer val[3][2]); import "DPI-C" function void i_integer_3d(inout integer_array_t val); import "DPI-C" function void i_integer_1d1(inout integer val[1]); import "DPI-C" function void i_integer_2d1(inout integer val[1][1]); import "DPI-C" function void i_integer_3d1(inout integer_array1_t val); `endif import "DPI-C" function void i_real_0d(inout real val); import "DPI-C" function void i_real_1d(inout real val[2]); import "DPI-C" function void i_real_2d(inout real val[3][2]); import "DPI-C" function void i_real_3d(inout real_array_t val); import "DPI-C" function void i_real_1d1(inout real val[1]); import "DPI-C" function void i_real_2d1(inout real val[1][1]); import "DPI-C" function void i_real_3d1(inout real_array1_t val); `ifndef NO_SHORTREAL import "DPI-C" function void i_shortreal_0d(inout shortreal val); import "DPI-C" function void i_shortreal_1d(inout shortreal val[2]); import "DPI-C" function void i_shortreal_2d(inout shortreal val[3][2]); import "DPI-C" function void i_shortreal_3d(inout shortreal_array_t val); import "DPI-C" function void i_shortreal_1d1(inout shortreal val[1]); import "DPI-C" function void i_shortreal_2d1(inout shortreal val[1][1]); import "DPI-C" function void i_shortreal_3d1(inout shortreal_array1_t val); `endif import "DPI-C" function void i_chandle_0d(inout chandle val); import "DPI-C" function void i_chandle_1d(inout chandle val[2]); import "DPI-C" function void i_chandle_2d(inout chandle val[3][2]); import "DPI-C" function void i_chandle_3d(inout chandle_array_t val); import "DPI-C" function void i_chandle_1d1(inout chandle val[1]); import "DPI-C" function void i_chandle_2d1(inout chandle val[1][1]); import "DPI-C" function void i_chandle_3d1(inout chandle_array1_t val); import "DPI-C" function void i_string_0d(inout string val); import "DPI-C" function void i_string_1d(inout string val[2]); import "DPI-C" function void i_string_2d(inout string val[3][2]); import "DPI-C" function void i_string_3d(inout string_array_t val); import "DPI-C" function void i_string_1d1(inout string val[1]); import "DPI-C" function void i_string_2d1(inout string val[1][1]); import "DPI-C" function void i_string_3d1(inout string_array1_t val); import "DPI-C" function void i_bit1_0d(inout bit val); import "DPI-C" function void i_bit1_1d(inout bit val[2]); import "DPI-C" function void i_bit1_2d(inout bit val[3][2]); import "DPI-C" function void i_bit1_3d(inout bit1_array_t val); import "DPI-C" function void i_bit1_1d1(inout bit val[1]); import "DPI-C" function void i_bit1_2d1(inout bit val[1][1]); import "DPI-C" function void i_bit1_3d1(inout bit1_array1_t val); import "DPI-C" function void i_bit7_0d(inout bit[6:0] val); import "DPI-C" function void i_bit7_1d(inout bit[6:0] val[2]); import "DPI-C" function void i_bit7_2d(inout bit[6:0] val[3][2]); import "DPI-C" function void i_bit7_3d(inout bit7_array_t val); import "DPI-C" function void i_bit7_1d1(inout bit[6:0] val[1]); import "DPI-C" function void i_bit7_2d1(inout bit[6:0] val[1][1]); import "DPI-C" function void i_bit7_3d1(inout bit7_array1_t val); import "DPI-C" function void i_bit121_0d(inout bit[120:0] val); import "DPI-C" function void i_bit121_1d(inout bit[120:0] val[2]); import "DPI-C" function void i_bit121_2d(inout bit[120:0] val[3][2]); import "DPI-C" function void i_bit121_3d(inout bit121_array_t val); import "DPI-C" function void i_bit121_1d1(inout bit[120:0] val[1]); import "DPI-C" function void i_bit121_2d1(inout bit[120:0] val[1][1]); import "DPI-C" function void i_bit121_3d1(inout bit121_array1_t val); import "DPI-C" function void i_logic1_0d(inout logic val); import "DPI-C" function void i_logic1_1d(inout logic val[2]); import "DPI-C" function void i_logic1_2d(inout logic val[3][2]); import "DPI-C" function void i_logic1_3d(inout logic1_array_t val); import "DPI-C" function void i_logic1_1d1(inout logic val[1]); import "DPI-C" function void i_logic1_2d1(inout logic val[1][1]); import "DPI-C" function void i_logic1_3d1(inout logic1_array1_t val); import "DPI-C" function void i_logic7_0d(inout logic[6:0] val); import "DPI-C" function void i_logic7_1d(inout logic[6:0] val[2]); import "DPI-C" function void i_logic7_2d(inout logic[6:0] val[3][2]); import "DPI-C" function void i_logic7_3d(inout logic7_array_t val); import "DPI-C" function void i_logic7_1d1(inout logic[6:0] val[1]); import "DPI-C" function void i_logic7_2d1(inout logic[6:0] val[1][1]); import "DPI-C" function void i_logic7_3d1(inout logic7_array1_t val); import "DPI-C" function void i_logic121_0d(inout logic[120:0] val); import "DPI-C" function void i_logic121_1d(inout logic[120:0] val[2]); import "DPI-C" function void i_logic121_2d(inout logic[120:0] val[3][2]); import "DPI-C" function void i_logic121_3d(inout logic121_array_t val); import "DPI-C" function void i_logic121_1d1(inout logic[120:0] val[1]); import "DPI-C" function void i_logic121_2d1(inout logic[120:0] val[1][1]); import "DPI-C" function void i_logic121_3d1(inout logic121_array1_t val); import "DPI-C" function void i_pack_struct_0d(inout pack_struct_t val); import "DPI-C" function void i_pack_struct_1d(inout pack_struct_t val[2]); import "DPI-C" function void i_pack_struct_2d(inout pack_struct_t val[3][2]); import "DPI-C" function void i_pack_struct_3d(inout pack_struct_array_t val); import "DPI-C" function void i_pack_struct_1d1(inout pack_struct_t val[1]); import "DPI-C" function void i_pack_struct_2d1(inout pack_struct_t val[1][1]); import "DPI-C" function void i_pack_struct_3d1(inout pack_struct_array1_t val); `ifndef NO_UNPACK_STRUCT import "DPI-C" function void i_unpack_struct_0d(inout unpack_struct_t val); import "DPI-C" function void i_unpack_struct_1d(inout unpack_struct_t val[2]); import "DPI-C" function void i_unpack_struct_2d(inout unpack_struct_t val[3][2]); import "DPI-C" function void i_unpack_struct_3d(inout unpack_struct_array_t val); import "DPI-C" function void i_unpack_struct_1d1(inout unpack_struct_t val[1]); import "DPI-C" function void i_unpack_struct_2d1(inout unpack_struct_t val[1][1]); import "DPI-C" function void i_unpack_struct_3d1(inout unpack_struct_array1_t val); `endif //====================================================================== // Exports //====================================================================== export "DPI-C" function e_byte_0d; export "DPI-C" function e_byte_1d; export "DPI-C" function e_byte_2d; export "DPI-C" function e_byte_3d; export "DPI-C" function e_byte_1d1; export "DPI-C" function e_byte_2d1; export "DPI-C" function e_byte_3d1; export "DPI-C" function e_byte_unsigned_0d; export "DPI-C" function e_byte_unsigned_1d; export "DPI-C" function e_byte_unsigned_2d; export "DPI-C" function e_byte_unsigned_3d; export "DPI-C" function e_byte_unsigned_1d1; export "DPI-C" function e_byte_unsigned_2d1; export "DPI-C" function e_byte_unsigned_3d1; export "DPI-C" function e_shortint_0d; export "DPI-C" function e_shortint_1d; export "DPI-C" function e_shortint_2d; export "DPI-C" function e_shortint_3d; export "DPI-C" function e_shortint_1d1; export "DPI-C" function e_shortint_2d1; export "DPI-C" function e_shortint_3d1; export "DPI-C" function e_shortint_unsigned_0d; export "DPI-C" function e_shortint_unsigned_1d; export "DPI-C" function e_shortint_unsigned_2d; export "DPI-C" function e_shortint_unsigned_3d; export "DPI-C" function e_shortint_unsigned_1d1; export "DPI-C" function e_shortint_unsigned_2d1; export "DPI-C" function e_shortint_unsigned_3d1; export "DPI-C" function e_int_0d; export "DPI-C" function e_int_1d; export "DPI-C" function e_int_2d; export "DPI-C" function e_int_3d; export "DPI-C" function e_int_1d1; export "DPI-C" function e_int_2d1; export "DPI-C" function e_int_3d1; export "DPI-C" function e_int_unsigned_0d; export "DPI-C" function e_int_unsigned_1d; export "DPI-C" function e_int_unsigned_2d; export "DPI-C" function e_int_unsigned_3d; export "DPI-C" function e_int_unsigned_1d1; export "DPI-C" function e_int_unsigned_2d1; export "DPI-C" function e_int_unsigned_3d1; export "DPI-C" function e_longint_0d; export "DPI-C" function e_longint_1d; export "DPI-C" function e_longint_2d; export "DPI-C" function e_longint_3d; export "DPI-C" function e_longint_1d1; export "DPI-C" function e_longint_2d1; export "DPI-C" function e_longint_3d1; export "DPI-C" function e_longint_unsigned_0d; export "DPI-C" function e_longint_unsigned_1d; export "DPI-C" function e_longint_unsigned_2d; export "DPI-C" function e_longint_unsigned_3d; export "DPI-C" function e_longint_unsigned_1d1; export "DPI-C" function e_longint_unsigned_2d1; export "DPI-C" function e_longint_unsigned_3d1; `ifndef NO_TIME export "DPI-C" function e_time_0d; export "DPI-C" function e_time_1d; export "DPI-C" function e_time_2d; export "DPI-C" function e_time_3d; export "DPI-C" function e_time_1d1; export "DPI-C" function e_time_2d1; export "DPI-C" function e_time_3d1; `endif `ifndef NO_INTEGER export "DPI-C" function e_integer_0d; export "DPI-C" function e_integer_1d; export "DPI-C" function e_integer_2d; export "DPI-C" function e_integer_3d; export "DPI-C" function e_integer_1d1; export "DPI-C" function e_integer_2d1; export "DPI-C" function e_integer_3d1; `endif export "DPI-C" function e_real_0d; export "DPI-C" function e_real_1d; export "DPI-C" function e_real_2d; export "DPI-C" function e_real_3d; export "DPI-C" function e_real_1d1; export "DPI-C" function e_real_2d1; export "DPI-C" function e_real_3d1; `ifndef NO_SHORTREAL export "DPI-C" function e_shortreal_0d; export "DPI-C" function e_shortreal_1d; export "DPI-C" function e_shortreal_2d; export "DPI-C" function e_shortreal_3d; export "DPI-C" function e_shortreal_1d1; export "DPI-C" function e_shortreal_2d1; export "DPI-C" function e_shortreal_3d1; `endif export "DPI-C" function e_chandle_0d; export "DPI-C" function e_chandle_1d; export "DPI-C" function e_chandle_2d; export "DPI-C" function e_chandle_3d; export "DPI-C" function e_chandle_1d1; export "DPI-C" function e_chandle_2d1; export "DPI-C" function e_chandle_3d1; export "DPI-C" function e_string_0d; export "DPI-C" function e_string_1d; export "DPI-C" function e_string_2d; export "DPI-C" function e_string_3d; export "DPI-C" function e_string_1d1; export "DPI-C" function e_string_2d1; export "DPI-C" function e_string_3d1; export "DPI-C" function e_bit1_0d; export "DPI-C" function e_bit1_1d; export "DPI-C" function e_bit1_2d; export "DPI-C" function e_bit1_3d; export "DPI-C" function e_bit1_1d1; export "DPI-C" function e_bit1_2d1; export "DPI-C" function e_bit1_3d1; export "DPI-C" function e_bit7_0d; export "DPI-C" function e_bit7_1d; export "DPI-C" function e_bit7_2d; export "DPI-C" function e_bit7_3d; export "DPI-C" function e_bit7_1d1; export "DPI-C" function e_bit7_2d1; export "DPI-C" function e_bit7_3d1; export "DPI-C" function e_bit121_0d; export "DPI-C" function e_bit121_1d; export "DPI-C" function e_bit121_2d; export "DPI-C" function e_bit121_3d; export "DPI-C" function e_bit121_1d1; export "DPI-C" function e_bit121_2d1; export "DPI-C" function e_bit121_3d1; export "DPI-C" function e_logic1_0d; export "DPI-C" function e_logic1_1d; export "DPI-C" function e_logic1_2d; export "DPI-C" function e_logic1_3d; export "DPI-C" function e_logic1_1d1; export "DPI-C" function e_logic1_2d1; export "DPI-C" function e_logic1_3d1; export "DPI-C" function e_logic7_0d; export "DPI-C" function e_logic7_1d; export "DPI-C" function e_logic7_2d; export "DPI-C" function e_logic7_3d; export "DPI-C" function e_logic7_1d1; export "DPI-C" function e_logic7_2d1; export "DPI-C" function e_logic7_3d1; export "DPI-C" function e_logic121_0d; export "DPI-C" function e_logic121_1d; export "DPI-C" function e_logic121_2d; export "DPI-C" function e_logic121_3d; export "DPI-C" function e_logic121_1d1; export "DPI-C" function e_logic121_2d1; export "DPI-C" function e_logic121_3d1; export "DPI-C" function e_pack_struct_0d; export "DPI-C" function e_pack_struct_1d; export "DPI-C" function e_pack_struct_2d; export "DPI-C" function e_pack_struct_3d; export "DPI-C" function e_pack_struct_1d1; export "DPI-C" function e_pack_struct_2d1; export "DPI-C" function e_pack_struct_3d1; `ifndef NO_UNPACK_STRUCT export "DPI-C" function e_unpack_struct_0d; export "DPI-C" function e_unpack_struct_1d; export "DPI-C" function e_unpack_struct_2d; export "DPI-C" function e_unpack_struct_3d; export "DPI-C" function e_unpack_struct_1d1; export "DPI-C" function e_unpack_struct_2d1; export "DPI-C" function e_unpack_struct_3d1; `endif //====================================================================== // Definitions of exported functions //====================================================================== function void e_byte_0d(inout byte val); `UPDATE_0D(val); endfunction function void e_byte_1d(inout byte val[2]); `UPDATE_1D(val); endfunction function void e_byte_2d(inout byte val[3][2]); `UPDATE_2D(val); endfunction function void e_byte_3d(inout byte_array_t val); `UPDATE_3D(val); endfunction function void e_byte_1d1(inout byte val[1]); `UPDATE_1D1(val); endfunction function void e_byte_2d1(inout byte val[1][1]); `UPDATE_2D1(val); endfunction function void e_byte_3d1(inout byte_array1_t val); `UPDATE_3D1(val); endfunction function void e_byte_unsigned_0d(inout byte unsigned val); `UPDATE_0D(val); endfunction function void e_byte_unsigned_1d(inout byte unsigned val[2]); `UPDATE_1D(val); endfunction function void e_byte_unsigned_2d(inout byte unsigned val[3][2]); `UPDATE_2D(val); endfunction function void e_byte_unsigned_3d(inout byte_unsigned_array_t val); `UPDATE_3D(val); endfunction function void e_byte_unsigned_1d1(inout byte unsigned val[1]); `UPDATE_1D1(val); endfunction function void e_byte_unsigned_2d1(inout byte unsigned val[1][1]); `UPDATE_2D1(val); endfunction function void e_byte_unsigned_3d1(inout byte_unsigned_array1_t val); `UPDATE_3D1(val); endfunction function void e_shortint_0d(inout shortint val); `UPDATE_0D(val); endfunction function void e_shortint_1d(inout shortint val[2]); `UPDATE_1D(val); endfunction function void e_shortint_2d(inout shortint val[3][2]); `UPDATE_2D(val); endfunction function void e_shortint_3d(inout shortint_array_t val); `UPDATE_3D(val); endfunction function void e_shortint_1d1(inout shortint val[1]); `UPDATE_1D1(val); endfunction function void e_shortint_2d1(inout shortint val[1][1]); `UPDATE_2D1(val); endfunction function void e_shortint_3d1(inout shortint_array1_t val); `UPDATE_3D1(val); endfunction function void e_shortint_unsigned_0d(inout shortint unsigned val); `UPDATE_0D(val); endfunction function void e_shortint_unsigned_1d(inout shortint unsigned val[2]); `UPDATE_1D(val); endfunction function void e_shortint_unsigned_2d(inout shortint unsigned val[3][2]); `UPDATE_2D(val); endfunction function void e_shortint_unsigned_3d(inout shortint_unsigned_array_t val); `UPDATE_3D(val); endfunction function void e_shortint_unsigned_1d1(inout shortint unsigned val[1]); `UPDATE_1D1(val); endfunction function void e_shortint_unsigned_2d1(inout shortint unsigned val[1][1]); `UPDATE_2D1(val); endfunction function void e_shortint_unsigned_3d1(inout shortint_unsigned_array1_t val); `UPDATE_3D1(val); endfunction function void e_int_0d(inout int val); `UPDATE_0D(val); endfunction function void e_int_1d(inout int val[2]); `UPDATE_1D(val); endfunction function void e_int_2d(inout int val[3][2]); `UPDATE_2D(val); endfunction function void e_int_3d(inout int_array_t val); `UPDATE_3D(val); endfunction function void e_int_1d1(inout int val[1]); `UPDATE_1D1(val); endfunction function void e_int_2d1(inout int val[1][1]); `UPDATE_2D1(val); endfunction function void e_int_3d1(inout int_array1_t val); `UPDATE_3D1(val); endfunction function void e_int_unsigned_0d(inout int unsigned val); `UPDATE_0D(val); endfunction function void e_int_unsigned_1d(inout int unsigned val[2]); `UPDATE_1D(val); endfunction function void e_int_unsigned_2d(inout int unsigned val[3][2]); `UPDATE_2D(val); endfunction function void e_int_unsigned_3d(inout int_unsigned_array_t val); `UPDATE_3D(val); endfunction function void e_int_unsigned_1d1(inout int unsigned val[1]); `UPDATE_1D1(val); endfunction function void e_int_unsigned_2d1(inout int unsigned val[1][1]); `UPDATE_2D1(val); endfunction function void e_int_unsigned_3d1(inout int_unsigned_array1_t val); `UPDATE_3D1(val); endfunction function void e_longint_0d(inout longint val); `UPDATE_0D(val); endfunction function void e_longint_1d(inout longint val[2]); `UPDATE_1D(val); endfunction function void e_longint_2d(inout longint val[3][2]); `UPDATE_2D(val); endfunction function void e_longint_3d(inout longint_array_t val); `UPDATE_3D(val); endfunction function void e_longint_1d1(inout longint val[1]); `UPDATE_1D1(val); endfunction function void e_longint_2d1(inout longint val[1][1]); `UPDATE_2D1(val); endfunction function void e_longint_3d1(inout longint_array1_t val); `UPDATE_3D1(val); endfunction function void e_longint_unsigned_0d(inout longint unsigned val); `UPDATE_0D(val); endfunction function void e_longint_unsigned_1d(inout longint unsigned val[2]); `UPDATE_1D(val); endfunction function void e_longint_unsigned_2d(inout longint unsigned val[3][2]); `UPDATE_2D(val); endfunction function void e_longint_unsigned_3d(inout longint_unsigned_array_t val); `UPDATE_3D(val); endfunction function void e_longint_unsigned_1d1(inout longint unsigned val[1]); `UPDATE_1D1(val); endfunction function void e_longint_unsigned_2d1(inout longint unsigned val[1][1]); `UPDATE_2D1(val); endfunction function void e_longint_unsigned_3d1(inout longint_unsigned_array1_t val); `UPDATE_3D1(val); endfunction `ifndef NO_TIME function void e_time_0d(inout time val); `UPDATE_0D(val); endfunction function void e_time_1d(inout time val[2]); `UPDATE_1D(val); endfunction function void e_time_2d(inout time val[3][2]); `UPDATE_2D(val); endfunction function void e_time_3d(inout time_array_t val); `UPDATE_3D(val); endfunction function void e_time_1d1(inout time val[1]); `UPDATE_1D1(val); endfunction function void e_time_2d1(inout time val[1][1]); `UPDATE_2D1(val); endfunction function void e_time_3d1(inout time_array1_t val); `UPDATE_3D1(val); endfunction `endif `ifndef NO_INTEGER function void e_integer_0d(inout integer val); `UPDATE_0D(val); endfunction function void e_integer_1d(inout integer val[2]); `UPDATE_1D(val); endfunction function void e_integer_2d(inout integer val[3][2]); `UPDATE_2D(val); endfunction function void e_integer_3d(inout integer_array_t val); `UPDATE_3D(val); endfunction function void e_integer_1d1(inout integer val[1]); `UPDATE_1D1(val); endfunction function void e_integer_2d1(inout integer val[1][1]); `UPDATE_2D1(val); endfunction function void e_integer_3d1(inout integer_array1_t val); `UPDATE_3D1(val); endfunction `endif function void e_real_0d(inout real val); `UPDATE_0D(val); endfunction function void e_real_1d(inout real val[2]); `UPDATE_1D(val); endfunction function void e_real_2d(inout real val[3][2]); `UPDATE_2D(val); endfunction function void e_real_3d(inout real_array_t val); `UPDATE_3D(val); endfunction function void e_real_1d1(inout real val[1]); `UPDATE_1D1(val); endfunction function void e_real_2d1(inout real val[1][1]); `UPDATE_2D1(val); endfunction function void e_real_3d1(inout real_array1_t val); `UPDATE_3D1(val); endfunction `ifndef NO_SHORTREAL function void e_shortreal_0d(inout shortreal val); `UPDATE_0D(val); endfunction function void e_shortreal_1d(inout shortreal val[2]); `UPDATE_1D(val); endfunction function void e_shortreal_2d(inout shortreal val[3][2]); `UPDATE_2D(val); endfunction function void e_shortreal_3d(inout shortreal_array_t val); `UPDATE_3D(val); endfunction function void e_shortreal_1d1(inout shortreal val[1]); `UPDATE_1D1(val); endfunction function void e_shortreal_2d1(inout shortreal val[1][1]); `UPDATE_2D1(val); endfunction function void e_shortreal_3d1(inout shortreal_array1_t val); `UPDATE_3D1(val); endfunction `endif function void e_chandle_0d(inout chandle val); `CHECK_CHANDLE_VAL(val, get_non_null()); val = null; endfunction function void e_chandle_1d(inout chandle val[2]); `CHECK_CHANDLE_VAL(val[0], get_non_null()); `CHECK_CHANDLE_VAL(val[1], get_non_null()); val[0] = null; val[1] = null; endfunction function void e_chandle_2d(inout chandle val[3][2]); `CHECK_CHANDLE_VAL(val[0][1], get_non_null()); `CHECK_CHANDLE_VAL(val[1][1], get_non_null()); `CHECK_CHANDLE_VAL(val[2][1], get_non_null()); val[0][1] = null; val[1][1] = null; val[2][1] = null; endfunction function void e_chandle_3d(inout chandle_array_t val); `CHECK_CHANDLE_VAL(val[0][0][0], get_non_null()); `CHECK_CHANDLE_VAL(val[1][0][0], get_non_null()); `CHECK_CHANDLE_VAL(val[2][0][0], get_non_null()); `CHECK_CHANDLE_VAL(val[3][0][0], get_non_null()); val[0][0][0] = null; val[1][0][0] = null; val[2][0][0] = null; val[3][0][0] = null; endfunction function void e_chandle_1d1(inout chandle val[1]); `CHECK_CHANDLE_VAL(val[0], get_non_null()); val[0] = null; endfunction function void e_chandle_2d1(inout chandle val[1][1]); `CHECK_CHANDLE_VAL(val[0][0], get_non_null()); val[0][0] = null; endfunction function void e_chandle_3d1(inout chandle_array1_t val); `CHECK_CHANDLE_VAL(val[0][0][0], get_non_null()); val[0][0][0] = null; endfunction function void e_string_0d(inout string val); `CHECK_STRING_VAL(val, "42"); val = "43"; endfunction function void e_string_1d(inout string val[2]); `CHECK_STRING_VAL(val[0], "43"); `CHECK_STRING_VAL(val[1], "44"); val[0] = "44"; val[1] = "45"; endfunction function void e_string_2d(inout string val[3][2]); `CHECK_STRING_VAL(val[0][1], "45"); `CHECK_STRING_VAL(val[1][1], "46"); `CHECK_STRING_VAL(val[2][1], "47"); val[0][1] = "46"; val[1][1] = "47"; val[2][1] = "48"; endfunction function void e_string_3d(inout string_array_t val); `CHECK_STRING_VAL(val[0][0][0], "48"); `CHECK_STRING_VAL(val[1][0][0], "49"); `CHECK_STRING_VAL(val[2][0][0], "50"); `CHECK_STRING_VAL(val[3][0][0], "51"); val[0][0][0] = "49"; val[1][0][0] = "50"; val[2][0][0] = "51"; val[3][0][0] = "52"; endfunction function void e_string_1d1(inout string val[1]); `CHECK_STRING_VAL(val[0], "52"); val[0] = "53"; endfunction function void e_string_2d1(inout string val[1][1]); `CHECK_STRING_VAL(val[0][0], "53"); val[0][0] = "54"; endfunction function void e_string_3d1(inout string_array1_t val); `CHECK_STRING_VAL(val[0][0][0], "54"); val[0][0][0] = "55"; endfunction function void e_bit1_0d(inout bit val); `UPDATE_0D(val); endfunction function void e_bit1_1d(inout bit val[2]); `UPDATE_1D(val); endfunction function void e_bit1_2d(inout bit val[3][2]); `UPDATE_2D(val); endfunction function void e_bit1_3d(inout bit1_array_t val); `UPDATE_3D(val); endfunction function void e_bit1_1d1(inout bit val[1]); `UPDATE_1D1(val); endfunction function void e_bit1_2d1(inout bit val[1][1]); `UPDATE_2D1(val); endfunction function void e_bit1_3d1(inout bit1_array1_t val); `UPDATE_3D1(val); endfunction function void e_bit7_0d(inout bit[6:0] val); `UPDATE_0D(val); endfunction function void e_bit7_1d(inout bit[6:0] val[2]); `UPDATE_1D(val); endfunction function void e_bit7_2d(inout bit[6:0] val[3][2]); `UPDATE_2D(val); endfunction function void e_bit7_3d(inout bit7_array_t val); `UPDATE_3D(val); endfunction function void e_bit7_1d1(inout bit[6:0] val[1]); `UPDATE_1D1(val); endfunction function void e_bit7_2d1(inout bit[6:0] val[1][1]); `UPDATE_2D1(val); endfunction function void e_bit7_3d1(inout bit7_array1_t val); `UPDATE_3D1(val); endfunction function void e_bit121_0d(inout bit[120:0] val); `UPDATE_0D(val); endfunction function void e_bit121_1d(inout bit[120:0] val[2]); `UPDATE_1D(val); endfunction function void e_bit121_2d(inout bit[120:0] val[3][2]); `UPDATE_2D(val); endfunction function void e_bit121_3d(inout bit121_array_t val); `UPDATE_3D(val); endfunction function void e_bit121_1d1(inout bit[120:0] val[1]); `UPDATE_1D1(val); endfunction function void e_bit121_2d1(inout bit[120:0] val[1][1]); `UPDATE_2D1(val); endfunction function void e_bit121_3d1(inout bit121_array1_t val); `UPDATE_3D1(val); endfunction function void e_logic1_0d(inout logic val); `UPDATE_0D(val); endfunction function void e_logic1_1d(inout logic val[2]); `UPDATE_1D(val); endfunction function void e_logic1_2d(inout logic val[3][2]); `UPDATE_2D(val); endfunction function void e_logic1_3d(inout logic1_array_t val); `UPDATE_3D(val); endfunction function void e_logic1_1d1(inout logic val[1]); `UPDATE_1D1(val); endfunction function void e_logic1_2d1(inout logic val[1][1]); `UPDATE_2D1(val); endfunction function void e_logic1_3d1(inout logic1_array1_t val); `UPDATE_3D1(val); endfunction function void e_logic7_0d(inout logic[6:0] val); `UPDATE_0D(val); endfunction function void e_logic7_1d(inout logic[6:0] val[2]); `UPDATE_1D(val); endfunction function void e_logic7_2d(inout logic[6:0] val[3][2]); `UPDATE_2D(val); endfunction function void e_logic7_3d(inout logic7_array_t val); `UPDATE_3D(val); endfunction function void e_logic7_1d1(inout logic[6:0] val[1]); `UPDATE_1D1(val); endfunction function void e_logic7_2d1(inout logic[6:0] val[1][1]); `UPDATE_2D1(val); endfunction function void e_logic7_3d1(inout logic7_array1_t val); `UPDATE_3D1(val); endfunction function void e_logic121_0d(inout logic[120:0] val); `UPDATE_0D(val); endfunction function void e_logic121_1d(inout logic[120:0] val[2]); `UPDATE_1D(val); endfunction function void e_logic121_2d(inout logic[120:0] val[3][2]); `UPDATE_2D(val); endfunction function void e_logic121_3d(inout logic121_array_t val); `UPDATE_3D(val); endfunction function void e_logic121_1d1(inout logic[120:0] val[1]); `UPDATE_1D1(val); endfunction function void e_logic121_2d1(inout logic[120:0] val[1][1]); `UPDATE_2D1(val); endfunction function void e_logic121_3d1(inout logic121_array1_t val); `UPDATE_3D1(val); endfunction function void e_pack_struct_0d(inout pack_struct_t val); `UPDATE_0D(val); endfunction function void e_pack_struct_1d(inout pack_struct_t val[2]); `UPDATE_1D(val); endfunction function void e_pack_struct_2d(inout pack_struct_t val[3][2]); `UPDATE_2D(val); endfunction function void e_pack_struct_3d(inout pack_struct_array_t val); `UPDATE_3D(val); endfunction function void e_pack_struct_1d1(inout pack_struct_t val[1]); `UPDATE_1D1(val); endfunction function void e_pack_struct_2d1(inout pack_struct_t val[1][1]); `UPDATE_2D1(val); endfunction function void e_pack_struct_3d1(inout pack_struct_array1_t val); `UPDATE_3D1(val); endfunction `ifndef NO_UNPACK_STRUCT function void e_unpack_struct_0d(inout unpack_struct_t val); `CHECK_VAL(val.val, 42); val.val = 43; endfunction function void e_unpack_struct_1d(inout unpack_struct_t val[2]); `CHECK_VAL(val[0].val, 43); `CHECK_VAL(val[1].val, 44); val[0].val = 44; val[1].val = 45; endfunction function void e_unpack_struct_2d(inout unpack_struct_t val[3][2]); `CHECK_VAL(val[0][1].val, 45); `CHECK_VAL(val[1][1].val, 46); `CHECK_VAL(val[2][1].val, 47); val[0][1].val = 46; val[1][1].val = 47; val[2][1].val = 48; endfunction function void e_unpack_struct_3d(inout unpack_struct_array_t val); `CHECK_VAL(val[0][0][0].val, 48); `CHECK_VAL(val[1][0][0].val, 49); `CHECK_VAL(val[2][0][0].val, 50); `CHECK_VAL(val[3][0][0].val, 51); val[0][0][0].val = 49; val[1][0][0].val = 50; val[2][0][0].val = 51; val[3][0][0].val = 52; endfunction function void e_unpack_struct_1d1(inout unpack_struct_t val[1]); `CHECK_VAL(val[0].val, 52); val[0].val = 53; endfunction function void e_unpack_struct_2d1(inout unpack_struct_t val[1][1]); `CHECK_VAL(val[0][0].val, 53); val[0][0].val = 54; endfunction function void e_unpack_struct_3d1(inout unpack_struct_array1_t val); `CHECK_VAL(val[0][0][0].val, 54); val[0][0][0].val = 55; endfunction `endif //====================================================================== // Invoke all imported functions //====================================================================== import "DPI-C" context function void check_exports(); initial begin byte_t byte_array_0d; byte_t byte_array_1d[2]; byte_t byte_array_2d[3][2]; byte_array_t byte_array_3d; byte_t byte_array_1d1[1]; byte_t byte_array_2d1[1][1]; byte_array1_t byte_array_3d1; byte_unsigned_t byte_unsigned_array_0d; byte_unsigned_t byte_unsigned_array_1d[2]; byte_unsigned_t byte_unsigned_array_2d[3][2]; byte_unsigned_array_t byte_unsigned_array_3d; byte_unsigned_t byte_unsigned_array_1d1[1]; byte_unsigned_t byte_unsigned_array_2d1[1][1]; byte_unsigned_array1_t byte_unsigned_array_3d1; shortint_t shortint_array_0d; shortint_t shortint_array_1d[2]; shortint_t shortint_array_2d[3][2]; shortint_array_t shortint_array_3d; shortint_t shortint_array_1d1[1]; shortint_t shortint_array_2d1[1][1]; shortint_array1_t shortint_array_3d1; shortint_unsigned_t shortint_unsigned_array_0d; shortint_unsigned_t shortint_unsigned_array_1d[2]; shortint_unsigned_t shortint_unsigned_array_2d[3][2]; shortint_unsigned_array_t shortint_unsigned_array_3d; shortint_unsigned_t shortint_unsigned_array_1d1[1]; shortint_unsigned_t shortint_unsigned_array_2d1[1][1]; shortint_unsigned_array1_t shortint_unsigned_array_3d1; int_t int_array_0d; int_t int_array_1d[2]; int_t int_array_2d[3][2]; int_array_t int_array_3d; int_t int_array_1d1[1]; int_t int_array_2d1[1][1]; int_array1_t int_array_3d1; int_unsigned_t int_unsigned_array_0d; int_unsigned_t int_unsigned_array_1d[2]; int_unsigned_t int_unsigned_array_2d[3][2]; int_unsigned_array_t int_unsigned_array_3d; int_unsigned_t int_unsigned_array_1d1[1]; int_unsigned_t int_unsigned_array_2d1[1][1]; int_unsigned_array1_t int_unsigned_array_3d1; longint_t longint_array_0d; longint_t longint_array_1d[2]; longint_t longint_array_2d[3][2]; longint_array_t longint_array_3d; longint_t longint_array_1d1[1]; longint_t longint_array_2d1[1][1]; longint_array1_t longint_array_3d1; longint_unsigned_t longint_unsigned_array_0d; longint_unsigned_t longint_unsigned_array_1d[2]; longint_unsigned_t longint_unsigned_array_2d[3][2]; longint_unsigned_array_t longint_unsigned_array_3d; longint_unsigned_t longint_unsigned_array_1d1[1]; longint_unsigned_t longint_unsigned_array_2d1[1][1]; longint_unsigned_array1_t longint_unsigned_array_3d1; `ifndef NO_TIME time_t time_array_0d; time_t time_array_1d[2]; time_t time_array_2d[3][2]; time_array_t time_array_3d; time_t time_array_1d1[1]; time_t time_array_2d1[1][1]; time_array1_t time_array_3d1; `endif `ifndef NO_INTEGER integer_t integer_array_0d; integer_t integer_array_1d[2]; integer_t integer_array_2d[3][2]; integer_array_t integer_array_3d; integer_t integer_array_1d1[1]; integer_t integer_array_2d1[1][1]; integer_array1_t integer_array_3d1; `endif real_t real_array_0d; real_t real_array_1d[2]; real_t real_array_2d[3][2]; real_array_t real_array_3d; real_t real_array_1d1[1]; real_t real_array_2d1[1][1]; real_array1_t real_array_3d1; `ifndef NO_SHORTREAL shortreal_t shortreal_array_0d; shortreal_t shortreal_array_1d[2]; shortreal_t shortreal_array_2d[3][2]; shortreal_array_t shortreal_array_3d; shortreal_t shortreal_array_1d1[1]; shortreal_t shortreal_array_2d1[1][1]; shortreal_array1_t shortreal_array_3d1; `endif chandle_t chandle_array_0d; chandle_t chandle_array_1d[2]; chandle_t chandle_array_2d[3][2]; chandle_array_t chandle_array_3d; chandle_t chandle_array_1d1[1]; chandle_t chandle_array_2d1[1][1]; chandle_array1_t chandle_array_3d1; string_t string_array_0d; string_t string_array_1d[2]; string_t string_array_2d[3][2]; string_array_t string_array_3d; string_t string_array_1d1[1]; string_t string_array_2d1[1][1]; string_array1_t string_array_3d1; bit1_t bit1_array_0d; bit1_t bit1_array_1d[2]; bit1_t bit1_array_2d[3][2]; bit1_array_t bit1_array_3d; bit1_t bit1_array_1d1[1]; bit1_t bit1_array_2d1[1][1]; bit1_array1_t bit1_array_3d1; bit7_t bit7_array_0d; bit7_t bit7_array_1d[2]; bit7_t bit7_array_2d[3][2]; bit7_array_t bit7_array_3d; bit7_t bit7_array_1d1[1]; bit7_t bit7_array_2d1[1][1]; bit7_array1_t bit7_array_3d1; bit121_t bit121_array_0d; bit121_t bit121_array_1d[2]; bit121_t bit121_array_2d[3][2]; bit121_array_t bit121_array_3d; bit121_t bit121_array_1d1[1]; bit121_t bit121_array_2d1[1][1]; bit121_array1_t bit121_array_3d1; logic1_t logic1_array_0d; logic1_t logic1_array_1d[2]; logic1_t logic1_array_2d[3][2]; logic1_array_t logic1_array_3d; logic1_t logic1_array_1d1[1]; logic1_t logic1_array_2d1[1][1]; logic1_array1_t logic1_array_3d1; logic7_t logic7_array_0d; logic7_t logic7_array_1d[2]; logic7_t logic7_array_2d[3][2]; logic7_array_t logic7_array_3d; logic7_t logic7_array_1d1[1]; logic7_t logic7_array_2d1[1][1]; logic7_array1_t logic7_array_3d1; logic121_t logic121_array_0d; logic121_t logic121_array_1d[2]; logic121_t logic121_array_2d[3][2]; logic121_array_t logic121_array_3d; logic121_t logic121_array_1d1[1]; logic121_t logic121_array_2d1[1][1]; logic121_array1_t logic121_array_3d1; pack_struct_t pack_struct_array_0d; pack_struct_t pack_struct_array_1d[2]; pack_struct_t pack_struct_array_2d[3][2]; pack_struct_array_t pack_struct_array_3d; pack_struct_t pack_struct_array_1d1[1]; pack_struct_t pack_struct_array_2d1[1][1]; pack_struct_array1_t pack_struct_array_3d1; `ifndef NO_UNPACK_STRUCT unpack_struct_array_t unpack_struct_array_3d; unpack_struct_array1_t unpack_struct_array_3d1; `endif `SET_VALUE_0D(byte_array_0d); `SET_VALUE_1D(byte_array_1d); `SET_VALUE_2D(byte_array_2d); `SET_VALUE_3D(byte_array_3d); `ifndef NO_INOUT_COMPLEX_TYPE i_byte_0d(byte_array_3d[3][2][1]); `CHECK_0D(byte_array_3d[3][2][1]); i_byte_1d(byte_array_3d[2][1]); `CHECK_1D(byte_array_3d[2][1]); i_byte_2d(byte_array_3d[1]); `CHECK_2D(byte_array_3d[1]); `endif i_byte_0d(byte_array_0d); `CHECK_0D(byte_array_0d); i_byte_1d(byte_array_1d); `CHECK_1D(byte_array_1d); i_byte_2d(byte_array_2d); `CHECK_2D(byte_array_2d); i_byte_3d(byte_array_3d); `CHECK_3D(byte_array_3d); `SET_VALUE_1D1(byte_array_1d1); `SET_VALUE_2D1(byte_array_2d1); `SET_VALUE_3D1(byte_array_3d1); i_byte_1d1(byte_array_1d1); `CHECK_1D1(byte_array_1d1); i_byte_2d1(byte_array_2d1); `CHECK_2D1(byte_array_2d1); i_byte_3d1(byte_array_3d1); `CHECK_3D1(byte_array_3d1); `SET_VALUE_0D(byte_unsigned_array_0d); `SET_VALUE_1D(byte_unsigned_array_1d); `SET_VALUE_2D(byte_unsigned_array_2d); `SET_VALUE_3D(byte_unsigned_array_3d); `ifndef NO_INOUT_COMPLEX_TYPE i_byte_unsigned_0d(byte_unsigned_array_3d[3][2][1]); `CHECK_0D(byte_unsigned_array_3d[3][2][1]); i_byte_unsigned_1d(byte_unsigned_array_3d[2][1]); `CHECK_1D(byte_unsigned_array_3d[2][1]); i_byte_unsigned_2d(byte_unsigned_array_3d[1]); `CHECK_2D(byte_unsigned_array_3d[1]); `endif i_byte_unsigned_0d(byte_unsigned_array_0d); `CHECK_0D(byte_unsigned_array_0d); i_byte_unsigned_1d(byte_unsigned_array_1d); `CHECK_1D(byte_unsigned_array_1d); i_byte_unsigned_2d(byte_unsigned_array_2d); `CHECK_2D(byte_unsigned_array_2d); i_byte_unsigned_3d(byte_unsigned_array_3d); `CHECK_3D(byte_unsigned_array_3d); `SET_VALUE_1D1(byte_unsigned_array_1d1); `SET_VALUE_2D1(byte_unsigned_array_2d1); `SET_VALUE_3D1(byte_unsigned_array_3d1); i_byte_unsigned_1d1(byte_unsigned_array_1d1); `CHECK_1D1(byte_unsigned_array_1d1); i_byte_unsigned_2d1(byte_unsigned_array_2d1); `CHECK_2D1(byte_unsigned_array_2d1); i_byte_unsigned_3d1(byte_unsigned_array_3d1); `CHECK_3D1(byte_unsigned_array_3d1); `SET_VALUE_0D(shortint_array_0d); `SET_VALUE_1D(shortint_array_1d); `SET_VALUE_2D(shortint_array_2d); `SET_VALUE_3D(shortint_array_3d); `ifndef NO_INOUT_COMPLEX_TYPE i_shortint_0d(shortint_array_3d[3][2][1]); `CHECK_0D(shortint_array_3d[3][2][1]); i_shortint_1d(shortint_array_3d[2][1]); `CHECK_1D(shortint_array_3d[2][1]); i_shortint_2d(shortint_array_3d[1]); `CHECK_2D(shortint_array_3d[1]); `endif i_shortint_0d(shortint_array_0d); `CHECK_0D(shortint_array_0d); i_shortint_1d(shortint_array_1d); `CHECK_1D(shortint_array_1d); i_shortint_2d(shortint_array_2d); `CHECK_2D(shortint_array_2d); i_shortint_3d(shortint_array_3d); `CHECK_3D(shortint_array_3d); `SET_VALUE_1D1(shortint_array_1d1); `SET_VALUE_2D1(shortint_array_2d1); `SET_VALUE_3D1(shortint_array_3d1); i_shortint_1d1(shortint_array_1d1); `CHECK_1D1(shortint_array_1d1); i_shortint_2d1(shortint_array_2d1); `CHECK_2D1(shortint_array_2d1); i_shortint_3d1(shortint_array_3d1); `CHECK_3D1(shortint_array_3d1); `SET_VALUE_0D(shortint_unsigned_array_0d); `SET_VALUE_1D(shortint_unsigned_array_1d); `SET_VALUE_2D(shortint_unsigned_array_2d); `SET_VALUE_3D(shortint_unsigned_array_3d); `ifndef NO_INOUT_COMPLEX_TYPE i_shortint_unsigned_0d(shortint_unsigned_array_3d[3][2][1]); `CHECK_0D(shortint_unsigned_array_3d[3][2][1]); i_shortint_unsigned_1d(shortint_unsigned_array_3d[2][1]); `CHECK_1D(shortint_unsigned_array_3d[2][1]); i_shortint_unsigned_2d(shortint_unsigned_array_3d[1]); `CHECK_2D(shortint_unsigned_array_3d[1]); `endif i_shortint_unsigned_0d(shortint_unsigned_array_0d); `CHECK_0D(shortint_unsigned_array_0d); i_shortint_unsigned_1d(shortint_unsigned_array_1d); `CHECK_1D(shortint_unsigned_array_1d); i_shortint_unsigned_2d(shortint_unsigned_array_2d); `CHECK_2D(shortint_unsigned_array_2d); i_shortint_unsigned_3d(shortint_unsigned_array_3d); `CHECK_3D(shortint_unsigned_array_3d); `SET_VALUE_1D1(shortint_unsigned_array_1d1); `SET_VALUE_2D1(shortint_unsigned_array_2d1); `SET_VALUE_3D1(shortint_unsigned_array_3d1); i_shortint_unsigned_1d1(shortint_unsigned_array_1d1); `CHECK_1D1(shortint_unsigned_array_1d1); i_shortint_unsigned_2d1(shortint_unsigned_array_2d1); `CHECK_2D1(shortint_unsigned_array_2d1); i_shortint_unsigned_3d1(shortint_unsigned_array_3d1); `CHECK_3D1(shortint_unsigned_array_3d1); `SET_VALUE_0D(int_array_0d); `SET_VALUE_1D(int_array_1d); `SET_VALUE_2D(int_array_2d); `SET_VALUE_3D(int_array_3d); `ifndef NO_INOUT_COMPLEX_TYPE i_int_0d(int_array_3d[3][2][1]); `CHECK_0D(int_array_3d[3][2][1]); i_int_1d(int_array_3d[2][1]); `CHECK_1D(int_array_3d[2][1]); i_int_2d(int_array_3d[1]); `CHECK_2D(int_array_3d[1]); `endif i_int_0d(int_array_0d); `CHECK_0D(int_array_0d); i_int_1d(int_array_1d); `CHECK_1D(int_array_1d); i_int_2d(int_array_2d); `CHECK_2D(int_array_2d); i_int_3d(int_array_3d); `CHECK_3D(int_array_3d); `SET_VALUE_1D1(int_array_1d1); `SET_VALUE_2D1(int_array_2d1); `SET_VALUE_3D1(int_array_3d1); i_int_1d1(int_array_1d1); `CHECK_1D1(int_array_1d1); i_int_2d1(int_array_2d1); `CHECK_2D1(int_array_2d1); i_int_3d1(int_array_3d1); `CHECK_3D1(int_array_3d1); `SET_VALUE_0D(int_unsigned_array_0d); `SET_VALUE_1D(int_unsigned_array_1d); `SET_VALUE_2D(int_unsigned_array_2d); `SET_VALUE_3D(int_unsigned_array_3d); `ifndef NO_INOUT_COMPLEX_TYPE i_int_unsigned_0d(int_unsigned_array_3d[3][2][1]); `CHECK_0D(int_unsigned_array_3d[3][2][1]); i_int_unsigned_1d(int_unsigned_array_3d[2][1]); `CHECK_1D(int_unsigned_array_3d[2][1]); i_int_unsigned_2d(int_unsigned_array_3d[1]); `CHECK_2D(int_unsigned_array_3d[1]); `endif i_int_unsigned_0d(int_unsigned_array_0d); `CHECK_0D(int_unsigned_array_0d); i_int_unsigned_1d(int_unsigned_array_1d); `CHECK_1D(int_unsigned_array_1d); i_int_unsigned_2d(int_unsigned_array_2d); `CHECK_2D(int_unsigned_array_2d); i_int_unsigned_3d(int_unsigned_array_3d); `CHECK_3D(int_unsigned_array_3d); `SET_VALUE_1D1(int_unsigned_array_1d1); `SET_VALUE_2D1(int_unsigned_array_2d1); `SET_VALUE_3D1(int_unsigned_array_3d1); i_int_unsigned_1d1(int_unsigned_array_1d1); `CHECK_1D1(int_unsigned_array_1d1); i_int_unsigned_2d1(int_unsigned_array_2d1); `CHECK_2D1(int_unsigned_array_2d1); i_int_unsigned_3d1(int_unsigned_array_3d1); `CHECK_3D1(int_unsigned_array_3d1); `SET_VALUE_0D(longint_array_0d); `SET_VALUE_1D(longint_array_1d); `SET_VALUE_2D(longint_array_2d); `SET_VALUE_3D(longint_array_3d); `ifndef NO_INOUT_COMPLEX_TYPE i_longint_0d(longint_array_3d[3][2][1]); `CHECK_0D(longint_array_3d[3][2][1]); i_longint_1d(longint_array_3d[2][1]); `CHECK_1D(longint_array_3d[2][1]); i_longint_2d(longint_array_3d[1]); `CHECK_2D(longint_array_3d[1]); `endif i_longint_0d(longint_array_0d); `CHECK_0D(longint_array_0d); i_longint_1d(longint_array_1d); `CHECK_1D(longint_array_1d); i_longint_2d(longint_array_2d); `CHECK_2D(longint_array_2d); i_longint_3d(longint_array_3d); `CHECK_3D(longint_array_3d); `SET_VALUE_1D1(longint_array_1d1); `SET_VALUE_2D1(longint_array_2d1); `SET_VALUE_3D1(longint_array_3d1); i_longint_1d1(longint_array_1d1); `CHECK_1D1(longint_array_1d1); i_longint_2d1(longint_array_2d1); `CHECK_2D1(longint_array_2d1); i_longint_3d1(longint_array_3d1); `CHECK_3D1(longint_array_3d1); `SET_VALUE_0D(longint_unsigned_array_0d); `SET_VALUE_1D(longint_unsigned_array_1d); `SET_VALUE_2D(longint_unsigned_array_2d); `SET_VALUE_3D(longint_unsigned_array_3d); `ifndef NO_INOUT_COMPLEX_TYPE i_longint_unsigned_0d(longint_unsigned_array_3d[3][2][1]); `CHECK_0D(longint_unsigned_array_3d[3][2][1]); i_longint_unsigned_1d(longint_unsigned_array_3d[2][1]); `CHECK_1D(longint_unsigned_array_3d[2][1]); i_longint_unsigned_2d(longint_unsigned_array_3d[1]); `CHECK_2D(longint_unsigned_array_3d[1]); `endif i_longint_unsigned_0d(longint_unsigned_array_0d); `CHECK_0D(longint_unsigned_array_0d); i_longint_unsigned_1d(longint_unsigned_array_1d); `CHECK_1D(longint_unsigned_array_1d); i_longint_unsigned_2d(longint_unsigned_array_2d); `CHECK_2D(longint_unsigned_array_2d); i_longint_unsigned_3d(longint_unsigned_array_3d); `CHECK_3D(longint_unsigned_array_3d); `SET_VALUE_1D1(longint_unsigned_array_1d1); `SET_VALUE_2D1(longint_unsigned_array_2d1); `SET_VALUE_3D1(longint_unsigned_array_3d1); i_longint_unsigned_1d1(longint_unsigned_array_1d1); `CHECK_1D1(longint_unsigned_array_1d1); i_longint_unsigned_2d1(longint_unsigned_array_2d1); `CHECK_2D1(longint_unsigned_array_2d1); i_longint_unsigned_3d1(longint_unsigned_array_3d1); `CHECK_3D1(longint_unsigned_array_3d1); `ifndef NO_TIME `SET_VALUE_0D(time_array_0d); `SET_VALUE_1D(time_array_1d); `SET_VALUE_2D(time_array_2d); `SET_VALUE_3D(time_array_3d); `ifndef NO_INOUT_COMPLEX_TYPE i_time_0d(time_array_3d[3][2][1]); `CHECK_0D(time_array_3d[3][2][1]); i_time_1d(time_array_3d[2][1]); `CHECK_1D(time_array_3d[2][1]); i_time_2d(time_array_3d[1]); `CHECK_2D(time_array_3d[1]); `endif i_time_0d(time_array_0d); `CHECK_0D(time_array_0d); i_time_1d(time_array_1d); `CHECK_1D(time_array_1d); i_time_2d(time_array_2d); `CHECK_2D(time_array_2d); i_time_3d(time_array_3d); `CHECK_3D(time_array_3d); `SET_VALUE_1D1(time_array_1d1); `SET_VALUE_2D1(time_array_2d1); `SET_VALUE_3D1(time_array_3d1); i_time_1d1(time_array_1d1); `CHECK_1D1(time_array_1d1); i_time_2d1(time_array_2d1); `CHECK_2D1(time_array_2d1); i_time_3d1(time_array_3d1); `CHECK_3D1(time_array_3d1); `endif `ifndef NO_INTEGER `SET_VALUE_0D(integer_array_0d); `SET_VALUE_1D(integer_array_1d); `SET_VALUE_2D(integer_array_2d); `SET_VALUE_3D(integer_array_3d); `ifndef NO_INOUT_COMPLEX_TYPE i_integer_0d(integer_array_3d[3][2][1]); `CHECK_0D(integer_array_3d[3][2][1]); i_integer_1d(integer_array_3d[2][1]); `CHECK_1D(integer_array_3d[2][1]); i_integer_2d(integer_array_3d[1]); `CHECK_2D(integer_array_3d[1]); `endif i_integer_0d(integer_array_0d); `CHECK_0D(integer_array_0d); i_integer_1d(integer_array_1d); `CHECK_1D(integer_array_1d); i_integer_2d(integer_array_2d); `CHECK_2D(integer_array_2d); i_integer_3d(integer_array_3d); `CHECK_3D(integer_array_3d); `SET_VALUE_1D1(integer_array_1d1); `SET_VALUE_2D1(integer_array_2d1); `SET_VALUE_3D1(integer_array_3d1); i_integer_1d1(integer_array_1d1); `CHECK_1D1(integer_array_1d1); i_integer_2d1(integer_array_2d1); `CHECK_2D1(integer_array_2d1); i_integer_3d1(integer_array_3d1); `CHECK_3D1(integer_array_3d1); `endif `SET_VALUE_0D(real_array_0d); `SET_VALUE_1D(real_array_1d); `SET_VALUE_2D(real_array_2d); `SET_VALUE_3D(real_array_3d); `ifndef NO_INOUT_COMPLEX_TYPE i_real_0d(real_array_3d[3][2][1]); `CHECK_DOUBLE_0D(real_array_3d[3][2][1]); i_real_1d(real_array_3d[2][1]); `CHECK_DOUBLE_1D(real_array_3d[2][1]); i_real_2d(real_array_3d[1]); `CHECK_DOUBLE_2D(real_array_3d[1]); `endif i_real_0d(real_array_0d); `CHECK_DOUBLE_0D(real_array_0d); i_real_1d(real_array_1d); `CHECK_DOUBLE_1D(real_array_1d); i_real_2d(real_array_2d); `CHECK_DOUBLE_2D(real_array_2d); i_real_3d(real_array_3d); `CHECK_DOUBLE_3D(real_array_3d); `SET_VALUE_1D1(real_array_1d1); `SET_VALUE_2D1(real_array_2d1); `SET_VALUE_3D1(real_array_3d1); i_real_1d1(real_array_1d1); `CHECK_1D1(real_array_1d1); i_real_2d1(real_array_2d1); `CHECK_2D1(real_array_2d1); i_real_3d1(real_array_3d1); `CHECK_3D1(real_array_3d1); `ifndef NO_SHORTREAL `SET_VALUE_0D(shortreal_array_0d); `SET_VALUE_1D(shortreal_array_1d); `SET_VALUE_2D(shortreal_array_2d); `SET_VALUE_3D(shortreal_array_3d); `ifndef NO_INOUT_COMPLEX_TYPE i_shortreal_0d(shortreal_array_3d[3][2][1]); `CHECK_DOUBLE_0D(shortreal_array_3d[3][2][1]); i_shortreal_1d(shortreal_array_3d[2][1]); `CHECK_DOUBLE_1D(shortreal_array_3d[2][1]); i_shortreal_2d(shortreal_array_3d[1]); `CHECK_DOUBLE_2D(shortreal_array_3d[1]); `endif i_shortreal_0d(shortreal_array_0d); `CHECK_DOUBLE_0D(shortreal_array_0d); i_shortreal_1d(shortreal_array_1d); `CHECK_DOUBLE_1D(shortreal_array_1d); i_shortreal_2d(shortreal_array_2d); `CHECK_DOUBLE_2D(shortreal_array_2d); i_shortreal_3d(shortreal_array_3d); `CHECK_DOUBLE_3D(shortreal_array_3d); `SET_VALUE_1D1(shortreal_array_1d1); `SET_VALUE_2D1(shortreal_array_2d1); `SET_VALUE_3D1(shortreal_array_3d1); i_shortreal_1d1(shortreal_array_1d1); `CHECK_1D1(shortreal_array_1d1); i_shortreal_2d1(shortreal_array_2d1); `CHECK_2D1(shortreal_array_2d1); i_shortreal_3d1(shortreal_array_3d1); `CHECK_3D1(shortreal_array_3d1); `endif for (int i = 0; i < 4; ++i) for (int j = 0; j < 3; ++j) for (int k = 0; k < 2; ++k) chandle_array_3d[i][j][k] = null; `ifndef NO_INOUT_COMPLEX_TYPE i_chandle_0d(chandle_array_3d[3][2][1]); `CHECK_CHANDLE_VAL(chandle_array_3d[3][2][1], get_non_null()); i_chandle_1d(chandle_array_3d[2][1]); `CHECK_CHANDLE_VAL(chandle_array_3d[2][1][0], get_non_null()); `CHECK_CHANDLE_VAL(chandle_array_3d[2][1][1], get_non_null()); i_chandle_2d(chandle_array_3d[1]); `CHECK_CHANDLE_VAL(chandle_array_3d[1][0][1], get_non_null()); `CHECK_CHANDLE_VAL(chandle_array_3d[1][1][1], get_non_null()); `CHECK_CHANDLE_VAL(chandle_array_3d[1][2][1], get_non_null()); `endif chandle_array_0d = null; i_chandle_0d(chandle_array_0d); `CHECK_CHANDLE_VAL(chandle_array_0d, get_non_null()); chandle_array_1d[0] = null; chandle_array_1d[1] = null; i_chandle_1d(chandle_array_1d); `CHECK_CHANDLE_VAL(chandle_array_1d[0], get_non_null()); `CHECK_CHANDLE_VAL(chandle_array_1d[1], get_non_null()); chandle_array_2d[0][1] = null; chandle_array_2d[1][1] = null; chandle_array_2d[2][1] = null; i_chandle_2d(chandle_array_2d); `CHECK_CHANDLE_VAL(chandle_array_2d[0][1], get_non_null()); `CHECK_CHANDLE_VAL(chandle_array_2d[1][1], get_non_null()); `CHECK_CHANDLE_VAL(chandle_array_2d[2][1], get_non_null()); i_chandle_3d(chandle_array_3d); `CHECK_CHANDLE_VAL(chandle_array_3d[0][0][0], get_non_null()); `CHECK_CHANDLE_VAL(chandle_array_3d[1][0][0], get_non_null()); `CHECK_CHANDLE_VAL(chandle_array_3d[2][0][0], get_non_null()); `CHECK_CHANDLE_VAL(chandle_array_3d[3][0][0], get_non_null()); chandle_array_1d1[0] = null; i_chandle_1d1(chandle_array_1d1); `CHECK_CHANDLE_VAL(chandle_array_1d1[0], get_non_null()); chandle_array_2d1[0][0] = null; i_chandle_2d1(chandle_array_2d1); `CHECK_CHANDLE_VAL(chandle_array_2d1[0][0], get_non_null()); chandle_array_3d1[0][0][0] = null; i_chandle_3d1(chandle_array_3d1); `CHECK_CHANDLE_VAL(chandle_array_3d1[0][0][0], get_non_null()); `ifndef NO_INOUT_COMPLEX_TYPE string_array_3d[3][2][1] = "42"; i_string_0d(string_array_3d[3][2][1]); `CHECK_STRING_VAL(string_array_3d[3][2][1], "43"); string_array_3d[2][1][0] = "43"; string_array_3d[2][1][1] = "44"; i_string_1d(string_array_3d[2][1]); `CHECK_STRING_VAL(string_array_3d[2][1][0], "44"); `CHECK_STRING_VAL(string_array_3d[2][1][1], "45"); string_array_3d[1][0][1] = "45"; string_array_3d[1][1][1] = "46"; string_array_3d[1][2][1] = "47"; i_string_2d(string_array_3d[1]); `CHECK_STRING_VAL(string_array_3d[1][0][1], "46"); `CHECK_STRING_VAL(string_array_3d[1][1][1], "47"); `CHECK_STRING_VAL(string_array_3d[1][2][1], "48"); `endif string_array_0d = "42"; i_string_0d(string_array_0d); `CHECK_STRING_VAL(string_array_0d, "43"); string_array_1d[0] = "43"; string_array_1d[1] = "44"; i_string_1d(string_array_1d); `CHECK_STRING_VAL(string_array_1d[0], "44"); `CHECK_STRING_VAL(string_array_1d[1], "45"); string_array_2d[0][1] = "45"; string_array_2d[1][1] = "46"; string_array_2d[2][1] = "47"; i_string_2d(string_array_2d); `CHECK_STRING_VAL(string_array_2d[0][1], "46"); `CHECK_STRING_VAL(string_array_2d[1][1], "47"); `CHECK_STRING_VAL(string_array_2d[2][1], "48"); string_array_3d[0][0][0] = "48"; string_array_3d[1][0][0] = "49"; string_array_3d[2][0][0] = "50"; string_array_3d[3][0][0] = "51"; i_string_3d(string_array_3d); `CHECK_STRING_VAL(string_array_3d[0][0][0], "49"); `CHECK_STRING_VAL(string_array_3d[1][0][0], "50"); `CHECK_STRING_VAL(string_array_3d[2][0][0], "51"); `CHECK_STRING_VAL(string_array_3d[3][0][0], "52"); string_array_1d1[0] = "52"; i_string_1d1(string_array_1d1); `CHECK_STRING_VAL(string_array_1d1[0], "53"); string_array_2d1[0][0] = "53"; i_string_2d1(string_array_2d1); `CHECK_STRING_VAL(string_array_2d1[0][0], "54"); string_array_3d1[0][0][0] = "54"; i_string_3d1(string_array_3d1); `CHECK_STRING_VAL(string_array_3d1[0][0][0], "55"); `SET_VALUE_0D(bit1_array_0d); `SET_VALUE_1D(bit1_array_1d); `SET_VALUE_2D(bit1_array_2d); `SET_VALUE_3D(bit1_array_3d); `ifndef NO_INOUT_COMPLEX_TYPE i_bit1_0d(bit1_array_3d[3][2][1]); `CHECK_0D(bit1_array_3d[3][2][1]); i_bit1_1d(bit1_array_3d[2][1]); `CHECK_1D(bit1_array_3d[2][1]); i_bit1_2d(bit1_array_3d[1]); `CHECK_2D(bit1_array_3d[1]); `endif i_bit1_0d(bit1_array_0d); `CHECK_0D(bit1_array_0d); i_bit1_1d(bit1_array_1d); `CHECK_1D(bit1_array_1d); i_bit1_2d(bit1_array_2d); `CHECK_2D(bit1_array_2d); i_bit1_3d(bit1_array_3d); `CHECK_3D(bit1_array_3d); `SET_VALUE_1D1(bit1_array_1d1); `SET_VALUE_2D1(bit1_array_2d1); `SET_VALUE_3D1(bit1_array_3d1); i_bit1_1d1(bit1_array_1d1); `CHECK_1D1(bit1_array_1d1); i_bit1_2d1(bit1_array_2d1); `CHECK_2D1(bit1_array_2d1); i_bit1_3d1(bit1_array_3d1); `CHECK_3D1(bit1_array_3d1); `SET_VALUE_0D(bit7_array_0d); `SET_VALUE_1D(bit7_array_1d); `SET_VALUE_2D(bit7_array_2d); `SET_VALUE_3D(bit7_array_3d); `ifndef NO_INOUT_COMPLEX_TYPE i_bit7_0d(bit7_array_3d[3][2][1]); `CHECK_0D(bit7_array_3d[3][2][1]); i_bit7_1d(bit7_array_3d[2][1]); `CHECK_1D(bit7_array_3d[2][1]); i_bit7_2d(bit7_array_3d[1]); `CHECK_2D(bit7_array_3d[1]); `endif i_bit7_0d(bit7_array_0d); `CHECK_0D(bit7_array_0d); i_bit7_1d(bit7_array_1d); `CHECK_1D(bit7_array_1d); i_bit7_2d(bit7_array_2d); `CHECK_2D(bit7_array_2d); i_bit7_3d(bit7_array_3d); `CHECK_3D(bit7_array_3d); `SET_VALUE_1D1(bit7_array_1d1); `SET_VALUE_2D1(bit7_array_2d1); `SET_VALUE_3D1(bit7_array_3d1); i_bit7_1d1(bit7_array_1d1); `CHECK_1D1(bit7_array_1d1); i_bit7_2d1(bit7_array_2d1); `CHECK_2D1(bit7_array_2d1); i_bit7_3d1(bit7_array_3d1); `CHECK_3D1(bit7_array_3d1); `SET_VALUE_0D(bit121_array_0d); `SET_VALUE_1D(bit121_array_1d); `SET_VALUE_2D(bit121_array_2d); `SET_VALUE_3D(bit121_array_3d); `ifndef NO_INOUT_COMPLEX_TYPE i_bit121_0d(bit121_array_3d[3][2][1]); `CHECK_0D(bit121_array_3d[3][2][1]); i_bit121_1d(bit121_array_3d[2][1]); `CHECK_1D(bit121_array_3d[2][1]); i_bit121_2d(bit121_array_3d[1]); `CHECK_2D(bit121_array_3d[1]); `endif i_bit121_0d(bit121_array_0d); `CHECK_0D(bit121_array_0d); i_bit121_1d(bit121_array_1d); `CHECK_1D(bit121_array_1d); i_bit121_2d(bit121_array_2d); `CHECK_2D(bit121_array_2d); i_bit121_3d(bit121_array_3d); `CHECK_3D(bit121_array_3d); `SET_VALUE_1D1(bit121_array_1d1); `SET_VALUE_2D1(bit121_array_2d1); `SET_VALUE_3D1(bit121_array_3d1); i_bit121_1d1(bit121_array_1d1); `CHECK_1D1(bit121_array_1d1); i_bit121_2d1(bit121_array_2d1); `CHECK_2D1(bit121_array_2d1); i_bit121_3d1(bit121_array_3d1); `CHECK_3D1(bit121_array_3d1); `SET_VALUE_0D(logic1_array_0d); `SET_VALUE_1D(logic1_array_1d); `SET_VALUE_2D(logic1_array_2d); `SET_VALUE_3D(logic1_array_3d); `ifndef NO_INOUT_COMPLEX_TYPE i_logic1_0d(logic1_array_3d[3][2][1]); `CHECK_0D(logic1_array_3d[3][2][1]); i_logic1_1d(logic1_array_3d[2][1]); `CHECK_1D(logic1_array_3d[2][1]); i_logic1_2d(logic1_array_3d[1]); `CHECK_2D(logic1_array_3d[1]); `endif i_logic1_0d(logic1_array_0d); `CHECK_0D(logic1_array_0d); i_logic1_1d(logic1_array_1d); `CHECK_1D(logic1_array_1d); i_logic1_2d(logic1_array_2d); `CHECK_2D(logic1_array_2d); i_logic1_3d(logic1_array_3d); `CHECK_3D(logic1_array_3d); `SET_VALUE_1D1(logic1_array_1d1); `SET_VALUE_2D1(logic1_array_2d1); `SET_VALUE_3D1(logic1_array_3d1); i_logic1_1d1(logic1_array_1d1); `CHECK_1D1(logic1_array_1d1); i_logic1_2d1(logic1_array_2d1); `CHECK_2D1(logic1_array_2d1); i_logic1_3d1(logic1_array_3d1); `CHECK_3D1(logic1_array_3d1); `SET_VALUE_0D(logic7_array_0d); `SET_VALUE_1D(logic7_array_1d); `SET_VALUE_2D(logic7_array_2d); `SET_VALUE_3D(logic7_array_3d); `ifndef NO_INOUT_COMPLEX_TYPE i_logic7_0d(logic7_array_3d[3][2][1]); `CHECK_0D(logic7_array_3d[3][2][1]); i_logic7_1d(logic7_array_3d[2][1]); `CHECK_1D(logic7_array_3d[2][1]); i_logic7_2d(logic7_array_3d[1]); `CHECK_2D(logic7_array_3d[1]); `endif i_logic7_0d(logic7_array_0d); `CHECK_0D(logic7_array_0d); i_logic7_1d(logic7_array_1d); `CHECK_1D(logic7_array_1d); i_logic7_2d(logic7_array_2d); `CHECK_2D(logic7_array_2d); i_logic7_3d(logic7_array_3d); `CHECK_3D(logic7_array_3d); `SET_VALUE_1D1(logic7_array_1d1); `SET_VALUE_2D1(logic7_array_2d1); `SET_VALUE_3D1(logic7_array_3d1); i_logic7_1d1(logic7_array_1d1); `CHECK_1D1(logic7_array_1d1); i_logic7_2d1(logic7_array_2d1); `CHECK_2D1(logic7_array_2d1); i_logic7_3d1(logic7_array_3d1); `CHECK_3D1(logic7_array_3d1); `SET_VALUE_0D(logic121_array_0d); `SET_VALUE_1D(logic121_array_1d); `SET_VALUE_2D(logic121_array_2d); `SET_VALUE_3D(logic121_array_3d); `ifndef NO_INOUT_COMPLEX_TYPE i_logic121_0d(logic121_array_3d[3][2][1]); `CHECK_0D(logic121_array_3d[3][2][1]); i_logic121_1d(logic121_array_3d[2][1]); `CHECK_1D(logic121_array_3d[2][1]); i_logic121_2d(logic121_array_3d[1]); `CHECK_2D(logic121_array_3d[1]); `endif i_logic121_0d(logic121_array_0d); `CHECK_0D(logic121_array_0d); i_logic121_1d(logic121_array_1d); `CHECK_1D(logic121_array_1d); i_logic121_2d(logic121_array_2d); `CHECK_2D(logic121_array_2d); i_logic121_3d(logic121_array_3d); `CHECK_3D(logic121_array_3d); `SET_VALUE_1D1(logic121_array_1d1); `SET_VALUE_2D1(logic121_array_2d1); `SET_VALUE_3D1(logic121_array_3d1); i_logic121_1d1(logic121_array_1d1); `CHECK_1D1(logic121_array_1d1); i_logic121_2d1(logic121_array_2d1); `CHECK_2D1(logic121_array_2d1); i_logic121_3d1(logic121_array_3d1); `CHECK_3D1(logic121_array_3d1); `SET_VALUE_0D(pack_struct_array_0d); `SET_VALUE_1D(pack_struct_array_1d); `SET_VALUE_2D(pack_struct_array_2d); `SET_VALUE_3D(pack_struct_array_3d); `ifndef NO_INOUT_COMPLEX_TYPE i_pack_struct_0d(pack_struct_array_3d[3][2][1]); `CHECK_0D(pack_struct_array_3d[3][2][1]); i_pack_struct_1d(pack_struct_array_3d[2][1]); `CHECK_1D(pack_struct_array_3d[2][1]); i_pack_struct_2d(pack_struct_array_3d[1]); `CHECK_2D(pack_struct_array_3d[1]); `endif i_pack_struct_0d(pack_struct_array_0d); `CHECK_0D(pack_struct_array_0d); i_pack_struct_1d(pack_struct_array_1d); `CHECK_1D(pack_struct_array_1d); i_pack_struct_2d(pack_struct_array_2d); `CHECK_2D(pack_struct_array_2d); i_pack_struct_3d(pack_struct_array_3d); `CHECK_3D(pack_struct_array_3d); `SET_VALUE_1D1(pack_struct_array_1d1); `SET_VALUE_2D1(pack_struct_array_2d1); `SET_VALUE_3D1(pack_struct_array_3d1); i_pack_struct_1d1(pack_struct_array_1d1); `CHECK_1D1(pack_struct_array_1d1); i_pack_struct_2d1(pack_struct_array_2d1); `CHECK_2D1(pack_struct_array_2d1); i_pack_struct_3d1(pack_struct_array_3d1); `CHECK_3D1(pack_struct_array_3d1); `ifndef NO_UNPACK_STRUCT unpack_struct_array_3d[3][2][1].val = 42; i_unpack_struct_0d(unpack_struct_array_3d[3][2][1]); `CHECK_VAL(unpack_struct_array_3d[3][2][1].val, 43); unpack_struct_array_3d[2][1][0].val = 43; unpack_struct_array_3d[2][1][1].val = 44; i_unpack_struct_1d(unpack_struct_array_3d[2][1]); `CHECK_VAL(unpack_struct_array_3d[2][1][0].val, 44); `CHECK_VAL(unpack_struct_array_3d[2][1][1].val, 45); unpack_struct_array_3d[1][0][1].val = 45; unpack_struct_array_3d[1][1][1].val = 46; unpack_struct_array_3d[1][2][1].val = 47; i_unpack_struct_2d(unpack_struct_array_3d[1]); `CHECK_VAL(unpack_struct_array_3d[1][0][1].val, 46); `CHECK_VAL(unpack_struct_array_3d[1][1][1].val, 47); `CHECK_VAL(unpack_struct_array_3d[1][2][1].val, 48); unpack_struct_array_3d[0][0][0].val = 48; unpack_struct_array_3d[1][0][0].val = 49; unpack_struct_array_3d[2][0][0].val = 50; unpack_struct_array_3d[3][0][0].val = 51; i_unpack_struct_3d(unpack_struct_array_3d); `CHECK_VAL(unpack_struct_array_3d[0][0][0].val, 49); `CHECK_VAL(unpack_struct_array_3d[1][0][0].val, 50); `CHECK_VAL(unpack_struct_array_3d[2][0][0].val, 51); `CHECK_VAL(unpack_struct_array_3d[3][0][0].val, 52); unpack_struct_array_3d1[0][0][0].val = 52; i_unpack_struct_1d1(unpack_struct_array_3d1[0][0]); `CHECK_VAL(unpack_struct_array_3d1[0][0][0].val, 53); unpack_struct_array_3d1[0][0][0].val = 53; i_unpack_struct_2d1(unpack_struct_array_3d1[0]); `CHECK_VAL(unpack_struct_array_3d1[0][0][0].val, 54); unpack_struct_array_3d1[0][0][0].val = 54; i_unpack_struct_3d1(unpack_struct_array_3d1); `CHECK_VAL(unpack_struct_array_3d1[0][0][0].val, 55); `endif check_exports(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_force_func.out0000644000542200017500000000032415101701376022252 0ustar mahmoudyfreeshell%Error: t/t_force_func.v:26: got='h0 exp='h00000001 %Error: t/t_force_func.v:34: got='h0 exp='h00000002 %Error: t/t_force_func.v:39: got='h0 exp='h00000003 %Error: t/t_force_func.v:43: got='h0 exp='h00000003 verilator-5.042/test_regress/t/t_flag_debugi9.v0000644000542200017500000000073115101701376022122 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs o, // Inputs i ); // Need some logic to get mtask debug fully covered input i; output wire o; assign o = i; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_interface_ar3.v0000644000542200017500000000260415101701376022307 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: SystemVerilog interface test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by Thierry Tambe. // SPDX-License-Identifier: CC0-1.0 module t ( input logic clk, output logic HRESETn ); int primsig[3]; ahb_slave_intf iinst[3] (primsig[2:0]); sub sub01 [2] (.clk, .infc(iinst[0:1])); sub sub2 (.clk, .infc(iinst[2])); initial begin primsig[0] = 30; primsig[1] = 31; primsig[2] = 32; iinst[0].data = 10; iinst[1].data = 11; iinst[2].data = 12; end int cyc = 0; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 10) begin if (iinst[0].primsig != 30) $stop; if (iinst[1].primsig != 31) $stop; if (iinst[2].primsig != 32) $stop; if (iinst[0].data != 10) $stop; if (iinst[1].data != 11) $stop; if (iinst[2].data != 12) $stop; if (sub01[0].internal != 10) $stop; if (sub01[1].internal != 11) $stop; if (sub2.internal != 12) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module sub ( input logic clk, ahb_slave_intf infc ); int internal; always_comb internal = infc.data; endmodule interface ahb_slave_intf ( input int primsig ); int data; endinterface verilator-5.042/test_regress/t/t_flag_ldflags.py0000755000542200017500000000342415101701376022376 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap import sys test.scenarios('vlt') CXX = os.environ["CXX"] test.run( cmd=[ "cd " + test.obj_dir # + " && " + CXX + " -c ../../t/t_flag_ldflags_a.cpp" # + " && ar -cr t_flag_ldflags_a.a t_flag_ldflags_a.o" # + " && ranlib t_flag_ldflags_a.a " ], check_finished=False) test.run( cmd=[ "cd " + test.obj_dir # + " && " + CXX + " -fPIC -c ../../t/t_flag_ldflags_so.cpp" # + " && " + CXX + " -shared -o t_flag_ldflags_so.so -lc t_flag_ldflags_so.o" ], check_finished=False) test.compile( # Pass multiple -D's so we check quoting works properly v_flags2=[ "-CFLAGS '-DCFLAGS_FROM_CMDLINE -DCFLAGS2_FROM_CMDLINE' ", "t/t_flag_ldflags_c.cpp", "t_flag_ldflags_a.a", "t_flag_ldflags_so.so" ]) # On OS X, LD_LIBRARY_PATH is ignored, so set rpath of the exe to find the .so if sys.platform == "darwin": test.run(cmd=[ "cd " + test.obj_dir + " && install_name_tool -add_rpath @executable_path/.", test.vm_prefix ], check_finished=False) test.run(cmd=[ "cd " + test.obj_dir + " && install_name_tool -change t_flag_ldflags_so.so" + " @rpath/t_flag_ldflags_so.so", test.vm_prefix ], check_finished=False) test.execute(run_env="LD_LIBRARY_PATH=" + test.obj_dir + ":" + test.getenv_def("LD_LIBRARY_PATH", "")) test.passes() verilator-5.042/test_regress/t/t_interface_size_bad.out0000644000542200017500000000140015101701376023735 0ustar mahmoudyfreeshell%Error: t/t_interface_size_bad.v:16:20: Illegal port connection 'foo', mismatch between port which is an interface array of size 5, and expression which is an interface array of size 4. : ... note: In instance 't' 16 | baz baz4_inst (.foo(foo4)); | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_interface_size_bad.v:17:20: Illegal port connection 'foo', mismatch between port which is an interface array of size 5, and expression which is an interface array of size 6. : ... note: In instance 't' 17 | baz baz6_inst (.foo(foo6)); | ^~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_timing_unset2.out0000644000542200017500000000310415101701376022727 0ustar mahmoudyfreeshell%Error-NEEDTIMINGOPT: t/t_timing_off.v:25:8: Use --timing or --no-timing to specify how event controls should be handled : ... note: In instance 't' 25 | @e1; | ^ ... For error description see https://verilator.org/warn/NEEDTIMINGOPT?v=latest %Error-NEEDTIMINGOPT: t/t_timing_off.v:33:12: Use --timing or --no-timing to specify how delays should be handled : ... note: In instance 't' 33 | initial #2 ->e1; | ^ %Error-NEEDTIMINGOPT: t/t_timing_off.v:37:12: Use --timing or --no-timing to specify how delays should be handled : ... note: In instance 't' 37 | initial #3 $stop; | ^ %Error-NEEDTIMINGOPT: t/t_timing_off.v:38:12: Use --timing or --no-timing to specify how delays should be handled : ... note: In instance 't' 38 | initial #1 @(e1, e2) #1 $stop; | ^ %Error-NEEDTIMINGOPT: t/t_timing_off.v:38:15: Use --timing or --no-timing to specify how event controls should be handled : ... note: In instance 't' 38 | initial #1 @(e1, e2) #1 $stop; | ^ %Error-NEEDTIMINGOPT: t/t_timing_off.v:38:25: Use --timing or --no-timing to specify how delays should be handled : ... note: In instance 't' 38 | initial #1 @(e1, e2) #1 $stop; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_flag_i_empty.v0000644000542200017500000000035215101701376022237 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2016 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; endmodule verilator-5.042/test_regress/t/t_trace_dumpvars_dyn_fst_1.out0000644000542200017500000000705315101701376025134 0ustar mahmoudyfreeshell$date Sat Jul 19 22:57:23 2025 $end $version fstWriter $end $timescale 1ps $end $scope module top $end $scope module t $end $var int 32 ! cyc [31:0] $end $scope module sub1a $end $var parameter 32 " ADD [31:0] $end $var wire 32 ! cyc [31:0] $end $var int 32 # value [31:0] $end $scope module sub2a $end $upscope $end $scope module sub2b $end $upscope $end $scope module sub2c $end $upscope $end $upscope $end $scope module sub1b $end $var parameter 32 $ ADD [31:0] $end $var wire 32 ! cyc [31:0] $end $var int 32 % value [31:0] $end $scope module sub2a $end $var parameter 32 & ADD [31:0] $end $var wire 32 ! cyc [31:0] $end $var int 32 ' value [31:0] $end $upscope $end $scope module sub2b $end $var parameter 32 ( ADD [31:0] $end $var wire 32 ! cyc [31:0] $end $var int 32 ) value [31:0] $end $upscope $end $scope module sub2c $end $var parameter 32 * ADD [31:0] $end $var wire 32 ! cyc [31:0] $end $var int 32 + value [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b00000000000000000000000000010111 + b00000000000000000000000000010111 * b00000000000000000000000000010110 ) b00000000000000000000000000010110 ( b00000000000000000000000000010101 ' b00000000000000000000000000010101 & b00000000000000000000000000010100 % b00000000000000000000000000010100 $ b00000000000000000000000000001010 # b00000000000000000000000000001010 " b00000000000000000000000000000000 ! $end #1 b00000000000000000000000000000001 ! b00000000000000000000000000001011 # b00000000000000000000000000010101 % b00000000000000000000000000010110 ' b00000000000000000000000000010111 ) b00000000000000000000000000011000 + #3 b00000000000000000000000000011001 + b00000000000000000000000000011000 ) b00000000000000000000000000010111 ' b00000000000000000000000000010110 % b00000000000000000000000000001100 # b00000000000000000000000000000010 ! #5 b00000000000000000000000000000011 ! b00000000000000000000000000001101 # b00000000000000000000000000010111 % b00000000000000000000000000011000 ' b00000000000000000000000000011001 ) b00000000000000000000000000011010 + #7 b00000000000000000000000000011011 + b00000000000000000000000000011010 ) b00000000000000000000000000011001 ' b00000000000000000000000000011000 % b00000000000000000000000000001110 # b00000000000000000000000000000100 ! #9 b00000000000000000000000000000101 ! b00000000000000000000000000001111 # b00000000000000000000000000011001 % b00000000000000000000000000011010 ' b00000000000000000000000000011011 ) b00000000000000000000000000011100 + #11 b00000000000000000000000000011101 + b00000000000000000000000000011100 ) b00000000000000000000000000011011 ' b00000000000000000000000000011010 % b00000000000000000000000000010000 # b00000000000000000000000000000110 ! #13 b00000000000000000000000000000111 ! b00000000000000000000000000010001 # b00000000000000000000000000011011 % b00000000000000000000000000011100 ' b00000000000000000000000000011101 ) b00000000000000000000000000011110 + #15 b00000000000000000000000000011111 + b00000000000000000000000000011110 ) b00000000000000000000000000011101 ' b00000000000000000000000000011100 % b00000000000000000000000000010010 # b00000000000000000000000000001000 ! #17 b00000000000000000000000000001001 ! b00000000000000000000000000010011 # b00000000000000000000000000011101 % b00000000000000000000000000011110 ' b00000000000000000000000000011111 ) b00000000000000000000000000100000 + #19 b00000000000000000000000000100001 + b00000000000000000000000000100000 ) b00000000000000000000000000011111 ' b00000000000000000000000000011110 % b00000000000000000000000000010100 # b00000000000000000000000000001010 ! #20 verilator-5.042/test_regress/t/t_stream_crc_example.v0000644000542200017500000000526015101701376023440 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilog_format: off `define stop $stop `define checkh(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv, expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); // verilog_format: on typedef bit bit_q_t[$]; module t ( /*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc = '0; reg [63:0] sum = '0; // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [31:0] out; // From test of Test.v // End of automatics Test test ( .clk, .in, .out ); // Aggregate outputs into a single result vector wire [63:0] result = {32'h0, out}; initial begin byte unsigned p[$]; byte unsigned po[$]; bit bits[$]; string s; p = {8'h84, 8'haa}; `checkh(p[0], 8'h84); `checkh(p[1], 8'haa); bits = {<<8{bit_q_t'({<<{p}})}}; bits.push_front(1'b0); po = {<<8{bit_q_t'({<<{bits}})}}; s = $sformatf("p=%p", p); `checks(s, "p='{'h84, 'haa}"); s = $sformatf("bits=%p", bits); `checks(s, "bits='{'h0, 'h0, 'h0, 'h1, 'h0, 'h0, 'h0, 'h0, 'h1, 'h0, 'h1, 'h0, 'h1, 'h0, 'h1, 'h0, 'h1}"); s = $sformatf("po=%p", po); `checks(s, "po='{'h8, 'h55, 'h80}"); end always_ff @(posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x sum=%x\n", $time, cyc, crc, result, sum); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc == 0) begin crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc < 10) begin sum <= '0; end else if (cyc == 99) begin `checkh(crc, 64'hc77bb9b3784ea091); `checkh(sum, 64'h9721d4e989defb24); $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test ( input logic clk, input logic [31:0] in, output logic [31:0] out ); byte unsigned p[$]; byte unsigned po[$]; bit bits[$]; always_ff @(posedge clk) begin p = {in[31:24], in[23:16], in[15:8], in[7:0]}; bits = {<<8{bit_q_t'({<<{p}})}}; bits.push_front(1'b0); po = {<<8{bit_q_t'({<<{bits}})}}; out <= {po[3], po[2], po[1], po[0]}; end endmodule verilator-5.042/test_regress/t/t_disable_outside4.py0000755000542200017500000000101315101701376023204 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(timing_loop=True, verilator_flags2=["--timing"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_covergroup_extends.py0000755000542200017500000000070615101701376023716 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.passes() verilator-5.042/test_regress/t/t_sys_readmem_assoc.v0000644000542200017500000000232115101701376023276 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" module t(/*AUTOARG*/ // Inputs clk ); input clk; int cyc; reg [5:0] assoc_c[int]; reg [95:0] assoc_w[int]; always_ff @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 1) begin assoc_c[300] = 10; // See if clearing must happen first // Also checks no BLKANDNBLK due to readmem/writemem end else if (cyc == 2) begin $readmemb("t/t_sys_readmem_b.mem", assoc_c); $display("assoc_c=%p", assoc_c); $writememh({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_writemem_c_b.mem"}, assoc_c); end else if (cyc == 3) begin $readmemb("t/t_sys_readmem_b.mem", assoc_w); // Not conditional with TEST_VERBOSE as found bug with wide display $display("assoc_w=%p", assoc_w); $writememh({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_writemem_w_h.mem"}, assoc_w); end else if (cyc == 4) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_interface_generic_modport_bad2.py0000755000542200017500000000102515101701376026054 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=['--timing'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_assert_future_bad.py0000755000542200017500000000076615101701376023500 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dist_untracked.py0000755000542200017500000000223715101701376022775 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') if not os.path.exists(test.root + "/.git"): test.skip("Not in a git repository") ### Must trim output before and after our file list warns = {} summary = None status = test.run_capture("cd " + test.root + " && git ls-files -o --exclude-standard") if test.verbose: print("-ST " + status) for filename in sorted(status.split()): if re.search('nodist', filename): continue warns[filename] = "File not in git or .gitignore: " + filename summary = "Files untracked in git or .gitignore:" if summary: # First warning lists everything as that's shown in the driver summary test.error(summary + " " + ' '.join(sorted(warns.keys()))) for filename in sorted(warns.keys()): test.error(warns[filename]) test.passes() verilator-5.042/test_regress/t/t_trace_complex_fst_sc.py0000755000542200017500000000124615101701376024157 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_complex.v" if not test.have_sc: test.skip("No SystemC installed") test.compile(verilator_flags2=['--sc --trace-fst']) test.execute() test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_inst_sv.v0000644000542200017500000000317015101701376021266 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; supply0 [1:0] low; supply1 [1:0] high; reg [7:0] isizedwire; reg ionewire; wire oonewire; wire [7:0] osizedreg; // From sub of t_inst_v2k_sub.v t_inst sub ( .osizedreg, .oonewire, // Inputs .isizedwire (isizedwire[7:0]), .* //.ionewire (ionewire) ); always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin ionewire <= 1'b1; isizedwire <= 8'd8; end if (cyc==2) begin if (low != 2'b00) $stop; if (high != 2'b11) $stop; if (oonewire !== 1'b1) $stop; if (isizedwire !== 8'd8) $stop; end if (cyc==3) begin ionewire <= 1'b0; isizedwire <= 8'd7; end if (cyc==4) begin if (oonewire !== 1'b0) $stop; if (isizedwire !== 8'd7) $stop; $write("*-* All Finished *-*\n"); $finish; end end end endmodule module t_inst ( output reg [7:0] osizedreg, output wire oonewire /*verilator public*/, input [7:0] isizedwire, input wire ionewire ); assign oonewire = ionewire; always @* begin osizedreg = isizedwire; end endmodule verilator-5.042/test_regress/t/t_comb_input_1.cpp0000644000542200017500000000233715101701376022501 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2022 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "verilated.h" #include "Vt_comb_input_1.h" #include "Vt_comb_input_1__Syms.h" #include int main(int argc, char** argv) { const std::unique_ptr contextp{new VerilatedContext}; contextp->debug(0); contextp->commandArgs(argc, argv); srand48(5); const std::unique_ptr topp{new VM_PREFIX}; topp->inc = 1; topp->clk = false; topp->eval(); while (!contextp->gotFinish() && contextp->time() < 100000) { contextp->timeInc(5); if (topp->clk) topp->inc += 1; topp->clk = !topp->clk; topp->eval(); } if (!contextp->gotFinish()) { vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); } return 0; } verilator-5.042/test_regress/t/t_hier_block0_bad.out0000644000542200017500000000232115101701376023127 0ustar mahmoudyfreeshell%Error: t/t_hier_block0_bad.v:21:11: 'sub0' has hier_block metacomment, hierarchical Verilation supports only integer/floating point/string and type param parameters : ... note: In instance 't' 21 | sub0 #(UNPACKED) i_sub0(.clk(clk), .in(8'(count)), .out(out0)); | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_hier_block0_bad.v:62:41: Cannot access non-port symbols inside hierarchical block : ... note: In instance 't.i_sub0' 62 | $display("%m: i_sub.x: %d", i_sub.x); | ^ %Error: t/t_hier_block0_bad.v:26:50: Cannot access non-port symbols inside hierarchical block : ... note: In instance 't' 26 | $display("%d i_sub0.ff: %d", count, i_sub0.ff); | ^~ %Error: t/t_hier_block0_bad.v:27:63: Cannot access scope inside hierarchical block 27 | $display("%d i_sub0.i_sub.out: %d", count, i_sub0.i_sub.out); | ^~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_lint_subout_bad.py0000755000542200017500000000111715101701376023143 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile( # No --lint-only as got compile error verilator_flags2=["--trace-vcd"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_inst_dtree_inlb.py0000755000542200017500000000107515101701376023135 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_inst_dtree.v" test.compile(v_flags2=['+define+INLINE_B'], verilator_flags2=['-trace']) test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_latch_bad_2.v0000644000542200017500000000053015101701376022746 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module for issue #1609 // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by Julien Margetts. // SPDX-License-Identifier: Unlicense module t (/*AUTOARG*/ a, b, o); input a; input b; output reg o; always_comb if (a) o = b; endmodule verilator-5.042/test_regress/t/t_constraint_state.py0000755000542200017500000000104615101701376023353 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_static_elab.py0000755000542200017500000000073415101701376022244 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_fork_dynscope.v0000644000542200017500000000270615101701376022452 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class Foo; task do_something(int arg_v); int dynscope_var; int x; dynscope_var = 0; fork #10 begin x = 0; // Test capturing a variable that needs to be modified $display("Incremented dynscope_var: %d", ++dynscope_var); if (dynscope_var != 1) $stop; // Check nested access fork #10 begin $display("Incremented x: %d", ++x); $display("Incremented dynscope_var: %d", ++dynscope_var); if (dynscope_var != 2) $stop; end join_none end #10 begin // Same as the first check, but with an argument // (so it needs to be copied to the dynamic scope instead of being moved there) $display("Incremented arg_v: %d", ++arg_v); if (arg_v != 2) $stop; end join_none // Check if regular access to arg_v has been substituted with access to its copy from // a dynamic scope $display("Incremented arg_v: %d", ++arg_v); if (arg_v != 1) $stop; endtask endclass module t(); initial begin Foo foo; foo = new; foo.do_something(0); #99 begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_math_cv_format.py0000755000542200017500000000077115101701376022764 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_event_control_expr_noinl.py0000755000542200017500000000125515101701376025107 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = 't_event_control_expr.v' test.compile( # do not test classes for multithreaded, as V3InstrCount doesn't handle MemberSel verilator_flags2=(['-fno-inline'] + ['-DNO_CLASS'] if test.vltmt else [])) test.execute() test.passes() verilator-5.042/test_regress/t/t_order_dpi_export_8.v0000644000542200017500000000221715101701376023401 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2022 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module testbench( /*AUTOARG*/ // Inputs clk ); input clk; // Top level input clock bit x = 0; wire y = x & $c(1); export "DPI-C" function set_x; function void set_x(bit val); x = val; endfunction; import "DPI-C" context function void call_set_x(bit val); bit q = 0; always @(posedge clk) q <= ~q; always @(edge q) call_set_x(q); int n = 0; always @(edge clk) begin // This always block needs to evaluate before the NBA to even_other // above is committed, as setting clocks via the set_other_clk uses // blocking assignment. $display("t=%t q=%d x=%d y=%d", $time, q, x, y); if (y !== q) $stop; if (n == 20) begin $write("*-* All Finished *-*\n"); $finish; end n += 1; end endmodule verilator-5.042/test_regress/t/t_dpi_import_mix_bad.out0000644000542200017500000000053515101701376023776 0ustar mahmoudyfreeshell%Error: t/t_dpi_import_mix_bad.v:11:32: Cannot mix DPI import, DPI export, class methods, and/or public on same function: 't.foo' 11 | import "DPI-C" function int foo (int i); | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_sys_time.py0000755000542200017500000000073415101701376021626 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_var_pinsizes.vlt0000644000542200017500000000050415101701376022653 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. // SPDX-License-Identifier: CC0-1.0 `verilator_config sc_bv -module "t" -var "ibv1_vlt" sc_bv -module "*" -var "ibv16_vlt" sc_bv -module "*" -var "obv*_vlt" verilator-5.042/test_regress/t/t_property_pexpr_unsup.py0000755000542200017500000000111215101701376024315 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(expect_filename=test.golden_filename, verilator_flags2=['--assert --error-limit 1000'], fails=test.vlt_all) test.passes() verilator-5.042/test_regress/t/t_wire_self_bad.out0000644000542200017500000000043015101701376022724 0ustar mahmoudyfreeshell%Error: t/t_wire_self_bad.v:11:16: Wire inputs its own output, creating circular logic (wire x=x) 11 | wire myself = myself; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_timing_fork_join.out0000644000542200017500000000116515101701376023474 0ustar mahmoudyfreeshell[0] fork..join process 4 [2] fork..join process 3 [4] fork..join process 2 [8] fork..join process 1 [16] fork in fork starts [16] fork..join process 8 [20] fork..join process 7 [24] fork..join process 6 [32] fork..join process 5 [32] fork..join in fork ends [64] main process fork..join_any process 2 back in main process fork..join_any process 1 fork..join_any process 1 back in main process fork..join_any process 2 in main process fork..join_none process 1 fork..join_none process 2 fork..join_none process 3 fork..join_none process 2 again fork..join_none process 1 again fork..join_none process 3 again *-* All Finished *-* verilator-5.042/test_regress/t/t_const_string_func.py0000755000542200017500000000073415101701376023521 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_process_notiming.out0000644000542200017500000000550115101701376023525 0ustar mahmoudyfreeshell%Error-NOTIMING: t/t_process.v:26:20: process::self() requires --timing : ... note: In instance 't' 26 | p = process::self(); | ^~~~ ... For error description see https://verilator.org/warn/NOTIMING?v=latest %Error-NOTIMING: t/t_process.v:27:13: process::status() requires --timing : ... note: In instance 't' 27 | if (p.status() != process::RUNNING) $stop; | ^~~~~~ %Error-NOTIMING: t/t_process.v:28:13: process::status() requires --timing : ... note: In instance 't' 28 | if (p.status() == process::WAITING) $stop; | ^~~~~~ %Error-NOTIMING: t/t_process.v:29:13: process::status() requires --timing : ... note: In instance 't' 29 | if (p.status() == process::SUSPENDED) $stop; | ^~~~~~ %Error-NOTIMING: t/t_process.v:30:13: process::status() requires --timing : ... note: In instance 't' 30 | if (p.status() == process::KILLED) $stop; | ^~~~~~ %Error-NOTIMING: t/t_process.v:31:13: process::status() requires --timing : ... note: In instance 't' 31 | if (p.status() == process::FINISHED) $stop; | ^~~~~~ %Error-NOTIMING: t/t_process.v:33:16: process::kill() requires --timing : ... note: In instance 't' 33 | if (0) p.kill(); | ^~~~ %Error-NOTIMING: t/t_process.v:34:16: process::await() requires --timing : ... note: In instance 't' 34 | if (0) p.await(); | ^~~~~ %Error-NOTIMING: t/t_process.v:35:16: process::suspend() requires --timing : ... note: In instance 't' 35 | if (0) p.suspend(); | ^~~~~~~ %Error-NOTIMING: t/t_process.v:36:16: process::resume() requires --timing : ... note: In instance 't' 36 | if (0) p.resume(); | ^~~~~~ %Error-NOTIMING: t/t_process.v:38:9: process::srandom() requires --timing : ... note: In instance 't' 38 | p.srandom(0); | ^~~~~~~ %Error-NOTIMING: t/t_process.v:39:9: process::set_randstate() requires --timing : ... note: In instance 't' 39 | p.set_randstate(p.get_randstate()); | ^~~~~~~~~~~~~ %Error-NOTIMING: t/t_process.v:39:25: process::get_randstate() requires --timing : ... note: In instance 't' 39 | p.set_randstate(p.get_randstate()); | ^~~~~~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_lint_incabspath_bad.out0000644000542200017500000000065615101701376024121 0ustar mahmoudyfreeshell%Warning-INCABSPATH: t/t_lint_incabspath.v:7:10: Suggest `include with absolute path be made relative, and use +include: /dev/null 7 | `include "/dev/null" | ^~~~~~~~~~~ ... For warning description see https://verilator.org/warn/INCABSPATH?v=latest ... Use "/* verilator lint_off INCABSPATH */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_param_width_loc_bad.v0000644000542200017500000000063715101701376023550 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Driss Hafdi. // SPDX-License-Identifier: CC0-1.0 module t; // bug1624 test #(.PARAM(32'd0)) test_i(); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule module test #( parameter logic PARAM = 1'b0 ) (); endmodule verilator-5.042/test_regress/t/t_unroll_complexcond.v0000644000542200017500000000200215101701376023500 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This files is used to generated the BLKLOOPINIT error which // is actually caused by not being able to unroll the for loop. // // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Jie Xu. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [3:0] tmp [3:0]; initial begin tmp[0] = 4'b0000; tmp[2] = 4'b0010; tmp[3] = 4'b0011; end // Test loop always @ (posedge clk) begin int i; int j; for (i = 0;(i < 4) && (i > 1); i++) begin tmp[i] <= tmp[i-i]; end if (tmp[0] != 4'b0000) $stop; if (tmp[3] != 4'b0011) $stop; j = 0; for (i=$c32("1"); i<3; ++i) j++; if (j!=2) $stop; j = 0; for (i=1; i<$c32("3"); ++i) j++; if (j!=2) $stop; j = 0; for (i=1; i<3; i=i+$c32("1")) j++; if (j!=2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_sequence_sexpr_unsup.out0000644000542200017500000002442515101701376024434 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:27:4: Unsupported: sequence 27 | sequence s_a; | ^~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:30:4: Unsupported: sequence 30 | sequence s_var; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:35:4: Unsupported: sequence 35 | sequence s_within; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:36:9: Unsupported: within (in sequence expression) 36 | a within(b); | ^~~~~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:39:4: Unsupported: sequence 39 | sequence s_and; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:40:9: Unsupported: and (in sequence expression) 40 | a and b; | ^~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:43:4: Unsupported: sequence 43 | sequence s_or; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:44:9: Unsupported: or (in sequence expression) 44 | a or b; | ^~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:47:4: Unsupported: sequence 47 | sequence s_throughout; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:48:9: Unsupported: throughout (in sequence expression) 48 | a throughout b; | ^~~~~~~~~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:51:4: Unsupported: sequence 51 | sequence s_intersect; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:52:9: Unsupported: intersect (in sequence expression) 52 | a intersect b; | ^~~~~~~~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:55:4: Unsupported: sequence 55 | sequence s_uni_cycdelay_id; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:56:7: Unsupported: ## id cycle delay range expression 56 | ## DELAY b; | ^~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:58:4: Unsupported: sequence 58 | sequence s_uni_cycdelay_pid; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:59:7: Unsupported: ## () cycle delay range expression 59 | ## ( DELAY ) b; | ^~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:61:4: Unsupported: sequence 61 | sequence s_uni_cycdelay_range; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:62:7: Unsupported: ## range cycle delay range expression 62 | ## [1:2] b; | ^~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:64:4: Unsupported: sequence 64 | sequence s_uni_cycdelay_star; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:65:7: Unsupported: ## [*] cycle delay range expression 65 | ## [*] b; | ^~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:67:4: Unsupported: sequence 67 | sequence s_uni_cycdelay_plus; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:68:7: Unsupported: ## [+] cycle delay range expression 68 | ## [+] b; | ^~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:71:4: Unsupported: sequence 71 | sequence s_cycdelay_int; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:72:9: Unsupported: ## (in sequence expression) 72 | a ## 1 b; | ^~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:74:4: Unsupported: sequence 74 | sequence s_cycdelay_id; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:75:9: Unsupported: ## id cycle delay range expression 75 | a ## DELAY b; | ^~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:75:9: Unsupported: ## (in sequence expression) 75 | a ## DELAY b; | ^~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:77:4: Unsupported: sequence 77 | sequence s_cycdelay_pid; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:78:9: Unsupported: ## () cycle delay range expression 78 | a ## ( DELAY ) b; | ^~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:78:9: Unsupported: ## (in sequence expression) 78 | a ## ( DELAY ) b; | ^~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:80:4: Unsupported: sequence 80 | sequence s_cycdelay_range; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:81:9: Unsupported: ## range cycle delay range expression 81 | a ## [1:2] b; | ^~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:81:9: Unsupported: ## (in sequence expression) 81 | a ## [1:2] b; | ^~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:83:4: Unsupported: sequence 83 | sequence s_cycdelay_star; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:84:9: Unsupported: ## [*] cycle delay range expression 84 | a ## [*] b; | ^~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:84:9: Unsupported: ## (in sequence expression) 84 | a ## [*] b; | ^~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:86:4: Unsupported: sequence 86 | sequence s_cycdelay_plus; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:87:9: Unsupported: ## [+] cycle delay range expression 87 | a ## [+] b; | ^~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:87:9: Unsupported: ## (in sequence expression) 87 | a ## [+] b; | ^~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:90:4: Unsupported: sequence 90 | sequence s_booleanabbrev_brastar_int; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:91:9: Unsupported: [*] boolean abbrev expression 91 | a [* 1 ]; | ^~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:91:12: Unsupported: boolean abbrev (in sequence expression) 91 | a [* 1 ]; | ^ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:93:4: Unsupported: sequence 93 | sequence s_booleanabbrev_brastar; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:94:9: Unsupported: [*] boolean abbrev expression 94 | a [*]; | ^~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:94:9: Unsupported: boolean abbrev (in sequence expression) 94 | a [*]; | ^~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:96:4: Unsupported: sequence 96 | sequence s_booleanabbrev_plus; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:97:9: Unsupported: [+] boolean abbrev expression 97 | a [+]; | ^~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:97:9: Unsupported: boolean abbrev (in sequence expression) 97 | a [+]; | ^~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:99:4: Unsupported: sequence 99 | sequence s_booleanabbrev_eq; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:100:9: Unsupported: [= boolean abbrev expression 100 | a [= 1]; | ^~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:100:12: Unsupported: boolean abbrev (in sequence expression) 100 | a [= 1]; | ^ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:102:4: Unsupported: sequence 102 | sequence s_booleanabbrev_eq_range; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:103:9: Unsupported: [= boolean abbrev expression 103 | a [= 1:2]; | ^~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:103:12: Unsupported: boolean abbrev (in sequence expression) 103 | a [= 1:2]; | ^ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:105:4: Unsupported: sequence 105 | sequence s_booleanabbrev_minusgt; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:106:9: Unsupported: [-> boolean abbrev expression 106 | a [-> 1]; | ^~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:106:13: Unsupported: boolean abbrev (in sequence expression) 106 | a [-> 1]; | ^ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:108:4: Unsupported: sequence 108 | sequence s_booleanabbrev_minusgt_range; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:109:9: Unsupported: [-> boolean abbrev expression 109 | a [-> 1:2]; | ^~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:109:13: Unsupported: boolean abbrev (in sequence expression) 109 | a [-> 1:2]; | ^ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:112:4: Unsupported: sequence 112 | sequence p_arg_seqence(sequence inseq); | ^~~~~~~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:112:27: Unsupported: sequence argument data type 112 | sequence p_arg_seqence(sequence inseq); | ^~~~~~~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:116:4: Unsupported: sequence 116 | sequence s_firstmatch_a; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:117:7: Unsupported: first_match (in sequence expression) 117 | first_match (a); | ^~~~~~~~~~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:119:4: Unsupported: sequence 119 | sequence s_firstmatch_ab; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:120:7: Unsupported: first_match (in sequence expression) 120 | first_match (a, res0 = 1); | ^~~~~~~~~~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:122:4: Unsupported: sequence 122 | sequence s_firstmatch_abc; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:123:7: Unsupported: first_match (in sequence expression) 123 | first_match (a, res0 = 1, res1 = 2); | ^~~~~~~~~~~ %Warning-COVERIGN: t/t_sequence_sexpr_unsup.v:126:10: Ignoring unsupported: cover sequence 126 | cover sequence (s_a) $display(""); | ^~~~~~~~ ... For warning description see https://verilator.org/warn/COVERIGN?v=latest ... Use "/* verilator lint_off COVERIGN */" and lint_on around source to disable this message. %Warning-COVERIGN: t/t_sequence_sexpr_unsup.v:127:10: Ignoring unsupported: cover sequence 127 | cover sequence (@(posedge a) disable iff (b) s_a) $display(""); | ^~~~~~~~ %Warning-COVERIGN: t/t_sequence_sexpr_unsup.v:128:10: Ignoring unsupported: cover sequence 128 | cover sequence (disable iff (b) s_a) $display(""); | ^~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_alw_reorder.py0000755000542200017500000000210315101701376022267 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(verilator_flags2=["--stats"]) test.file_grep(test.stats, r'Optimizations, Split always\s+(\d+)', 0) # Important: if reorder succeeded, we should see no dly vars. # Equally important: twin test t_alw_noreorder should see dly vars, # is identical to this test except for disabling the reorder step. for filename in (test.glob_some(test.obj_dir + "/" + test.vm_prefix + "*.h") + test.glob_some(test.obj_dir + "/" + test.vm_prefix + "*.cpp")): test.file_grep_not(filename, r'dly__t__DOT__v1') test.file_grep_not(filename, r'dly__t__DOT__v2') test.file_grep_not(filename, r'dly__t__DOT__v3') test.execute() test.passes() verilator-5.042/test_regress/t/t_cast.py0000755000542200017500000000073415101701376020724 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_covergroup_with_function_foo_bad.out0000644000542200017500000000050715101701376026750 0ustar mahmoudyfreeshell%Error: t/t_covergroup_with_function_foo_bad.v:9:35: Coverage sampling function must be named 'sample' 9 | covergroup cg_bad with function foo(int x); | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_castdyn_bbox.py0000755000542200017500000000101215101701376022437 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.top_filename = "t/t_castdyn.v" test.lint(verilator_flags2=['-bbox-unsup']) test.passes() verilator-5.042/test_regress/t/t_opt_balance_cats.v0000644000542200017500000000170215101701376023061 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(i, o); localparam N = 2000; // Deliberately not multiple of 32 input i; wire [N-1:0] i; output o; wire [N-1:0] o; for (genvar n = 0 ; n + 31 < N ; n += 32) begin assign o[n+ 0 +: 1] = i[(N-1-n)- 0 -: 1]; assign o[n+ 1 +: 1] = i[(N-1-n)- 1 -: 1]; assign o[n+ 2 +: 2] = i[(N-1-n)- 2 -: 2]; assign o[n+ 4 +: 4] = i[(N-1-n)- 4 -: 4]; assign o[n+ 8 +: 8] = i[(N-1-n)- 8 -: 8]; assign o[n+16 +: 8] = i[(N-1-n)-16 -: 8]; assign o[n+24 +: 4] = i[(N-1-n)-24 -: 4]; assign o[n+28 +: 2] = i[(N-1-n)-28 -: 2]; assign o[n+30 +: 1] = i[(N-1-n)-30 -: 1]; assign o[n+31 +: 1] = i[(N-1-n)-31 -: 1]; end for (genvar n = N / 32 * 32; n < N ; ++n) begin assign o[n] = i[N-1-n]; end endmodule verilator-5.042/test_regress/t/t_assert_dup_bad.v0000644000542200017500000000071715101701376022564 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; covlabel: cover property (@(posedge clk) cyc==5); covlabel: // Error: Duplicate block_identifier cover property (@(posedge clk) cyc==5); endmodule verilator-5.042/test_regress/t/t_flag_supported_1.out0000755000542200017500000000000215101701376023373 0ustar mahmoudyfreeshell1 verilator-5.042/test_regress/t/t_runflag_bad__c.out0000644000542200017500000000015715101701376023052 0ustar mahmoudyfreeshell%Error: COMMAND_LINE:0: Argument '+verilator+rand+reset+' must be an unsigned integer, less than 3 Aborting... verilator-5.042/test_regress/t/t_assert_imm_nz_bad.py0000755000542200017500000000102215101701376023441 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert'], fails=True) test.passes() verilator-5.042/test_regress/t/t_lint_unusedloop_removed_bad.v0000644000542200017500000001577215101701376025366 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 // verilator lint_off BLKSEQ // verilator lint_off DECLFILENAME module t(/*AUTOARG*/ // Inputs clk, reset_l ); input clk; input reset_l; parametrized_initial#(.REPETITIONS(0)) parametrized_initial0(); parametrized_initial#(.REPETITIONS(1)) parametrized_initial1(); parametrized_initial#(.REPETITIONS(2)) parametrized_initial2(); non_parametrized_initial non_parametrized_initial(); with_always with_always(.clk(clk)); const_condition const_condition(); loop_with_param loop_with_param(); if_with_param if_with_param(); clock_init_race clock_init_race(.clk(clk), .reset_l(reset_l)); endmodule // module unused - no warning for any of statements inside module unused(input clk); bit unused_variable_while; bit unused_variable_do_while; bit unused_variable_for; const bit always_false = 0; always @(posedge clk) begin while(unused_variable_while) begin unused_variable_while <= 1; end do begin unused_variable_do_while <= 1; end while (unused_variable_do_while); for (int i = 0; i < 5; i++) begin unused_variable_for <= 1; end while(always_false) begin $write("This will not be printed\n"); end do begin $write("This will not be printed\n"); end while (always_false); for (int i = 0; always_false; i++) begin $write("This will not be printed\n"); end end endmodule // no warning for loops under parameterized module module parametrized_initial #(parameter REPETITIONS = 0); int prints_while = 0; int prints_do_while = 0; // loops with evaluation depending on REPETITIONS initial begin while(prints_while < REPETITIONS) begin prints_while = prints_while + 1; $write("Writing to console to avoid loop being optimized out\n"); end while(REPETITIONS < 0) begin $write("Writing to console to avoid loop being optimized out\n"); end for (int i = 0; i < REPETITIONS; i++) begin $write("Writing to console to avoid loop being optimized out\n"); end do begin prints_do_while = prints_do_while + 1; $write("Writing to console to avoid loop being optimized out\n"); end while (prints_do_while < REPETITIONS); end // loop not changing variable used for output int param_unused_while = 0; initial begin while(param_unused_while < REPETITIONS) begin param_unused_while = param_unused_while + 1; end end const logic always_false = 0; // loops with empty bodies initial begin while(0); while(always_false); while(REPETITIONS < 0); end endmodule module non_parametrized_initial; int prints_do_while = 0; const int always_zero = 0; // loops with evaluation depending on always_zero initial begin while(always_zero < 0) begin $write("This will not be printed\n"); end // unrolled - no warning for (int i = 0; i < always_zero; i++) begin $write("This will not be printed\n"); end // inlined - no warning do begin prints_do_while = prints_do_while + 1; $write("Writing to console to avoid loop being optimized out\n"); end while (prints_do_while < always_zero); end // loop not changing variable used for output int param_unused_while = 0; int param_unused_do_while = 0; int param_unused_for = 0; initial begin // warning while(param_unused_while < always_zero) begin param_unused_while++; end // unrolled - no warning for (int i = 0; i < 5; i++) begin param_unused_for = 1; end // inlined - no warning do begin param_unused_do_while = 1; end while (param_unused_do_while > 0); end const logic always_false = 0; // loops with empty bodies - warning initial begin while(0); while(always_false); while(always_zero < 0); do ; while(0); // unrolled - no warning for (int i = 0; i < 1; i++); end endmodule // warning for all unused loops under always module with_always(input clk); const logic always_false = 0; always @(posedge clk) begin while(0); while(always_false) begin $write("Test"); end end endmodule module const_condition; const logic always_zero = 0; // loops with const false condition - warning initial begin while(always_zero) begin $write("This will not be printed\n"); end for (int i = 0; always_zero; i++) begin $write("This will not be printed\n"); end for (int i = 0; i < always_zero; i++) begin $write("This will not be printed\n"); end // inlined - no warning do begin $write("This will be printed\n"); end while (always_zero); end endmodule // loop with param - no warning module loop_with_param; parameter ZERO_PARAM = 0; int prints = 2; initial begin for (int i = 0; ZERO_PARAM; i++) begin $write("This will not be printed\n"); end while (ZERO_PARAM != ZERO_PARAM) begin $write("This will not be printed\n"); end while(prints > ZERO_PARAM) begin prints--; end end endmodule module if_with_param; parameter ZERO_PARAM = 0; parameter ONE_PARAM = 1; initial begin if (ZERO_PARAM) begin // loop under false parameterized if - no warning int prints = 0; while(prints < 5) begin prints++; end $write("Prints %d\n", prints); end else if (!ONE_PARAM) begin // loop under false parameterized if - no warning int prints = 0; while(prints < 5) begin prints++; end $write("Prints %d\n", prints); end else begin // loop under true parameterized if - no warning int prints = 0; while(prints < 5) begin prints++; end $write("Prints %d\n", prints); end end endmodule module clock_init_race(input clk, input reset_l); logic m_2_clock; logic m_3_clock; logic m_2_reset = reset_l; logic m_3_reset = reset_l; assign m_2_clock = clk; assign m_3_clock = clk; int m_3_counter; initial begin $write("*-* START TEST *-*\n"); end always @(posedge clk) begin if (m_3_counter == 25) begin $write("*-* All Finished *-*\n"); $finish(); end end bit m_2_ticked; always @(posedge m_2_clock) if (!m_2_reset) begin m_2_ticked = 1'b1; end always @(negedge m_2_clock) m_2_ticked = 1'b0; always @(posedge m_3_clock) if (!m_3_reset) begin $write("*-* m_3_clocked *-*\n"); // loop empty - unused loop warning while (m_2_ticked); m_3_counter += 1; end endmodule verilator-5.042/test_regress/t/t_class_func_arg_unused.v0000644000542200017500000000122215101701376024131 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package uvm_pkg; class uvm_reg_field; // extends uvm_object; function void configure(bit overde, bit is_rand); if (overde) is_rand = 0; if (!is_rand) ; // value.rand_mode(0); // See issue #4567 endfunction endclass endpackage module t; initial begin uvm_pkg::uvm_reg_field c = new; c.configure(1, 0); c.configure(0, 0); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_randcase.py0000755000542200017500000000073415101701376021552 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_gen6.py0000755000542200017500000000073415101701376022651 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_var_bad_hide.out0000644000542200017500000000146715101701376022541 0ustar mahmoudyfreeshell%Warning-VARHIDDEN: t/t_var_bad_hide.v:16:14: Declaration of signal hides declaration in upper scope: 'top' 16 | output top; | ^~~ t/t_var_bad_hide.v:13:12: ... Location of original declaration 13 | integer top; | ^~~ ... For warning description see https://verilator.org/warn/VARHIDDEN?v=latest ... Use "/* verilator lint_off VARHIDDEN */" and lint_on around source to disable this message. %Warning-VARHIDDEN: t/t_var_bad_hide.v:22:18: Declaration of signal hides declaration in upper scope: 'top' 22 | integer top; | ^~~ t/t_var_bad_hide.v:13:12: ... Location of original declaration 13 | integer top; | ^~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_trace_cat.out0000644000542200017500000001172515101701376022075 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $var wire 1 # clk $end $scope module t $end $var wire 1 # clk $end $var wire 32 $ cyc [31:0] $end $upscope $end $upscope $end $enddefinitions $end #0 1# b00000000000000000000000000000000 $ #1 0# #2 1# b00000000000000000000000000000001 $ #3 0# #4 1# b00000000000000000000000000000010 $ #5 0# #6 1# b00000000000000000000000000000011 $ #7 0# #8 1# b00000000000000000000000000000100 $ #9 0# #10 1# b00000000000000000000000000000101 $ #11 0# #12 1# b00000000000000000000000000000110 $ #13 0# #14 1# b00000000000000000000000000000111 $ #15 0# #16 1# b00000000000000000000000000001000 $ #17 0# #18 1# b00000000000000000000000000001001 $ #19 0# #20 1# b00000000000000000000000000001010 $ #21 0# #22 1# b00000000000000000000000000001011 $ #23 0# #24 1# b00000000000000000000000000001100 $ #25 0# #26 1# b00000000000000000000000000001101 $ #27 0# #28 1# b00000000000000000000000000001110 $ #29 0# #30 1# b00000000000000000000000000001111 $ #31 0# #32 1# b00000000000000000000000000010000 $ #33 0# #34 1# b00000000000000000000000000010001 $ #35 0# #36 1# b00000000000000000000000000010010 $ #37 0# #38 1# b00000000000000000000000000010011 $ #39 0# #40 1# b00000000000000000000000000010100 $ #41 0# #42 1# b00000000000000000000000000010101 $ #43 0# #44 1# b00000000000000000000000000010110 $ #45 0# #46 1# b00000000000000000000000000010111 $ #47 0# #48 1# b00000000000000000000000000011000 $ #49 0# #50 1# b00000000000000000000000000011001 $ #51 0# #52 1# b00000000000000000000000000011010 $ #53 0# #54 1# b00000000000000000000000000011011 $ #55 0# #56 1# b00000000000000000000000000011100 $ #57 0# #58 1# b00000000000000000000000000011101 $ #59 0# #60 1# b00000000000000000000000000011110 $ #61 0# #62 1# b00000000000000000000000000011111 $ #63 0# #64 1# b00000000000000000000000000100000 $ #65 0# #66 1# b00000000000000000000000000100001 $ #67 0# #68 1# b00000000000000000000000000100010 $ #69 0# #70 1# b00000000000000000000000000100011 $ #71 0# #72 1# b00000000000000000000000000100100 $ #73 0# #74 1# b00000000000000000000000000100101 $ #75 0# #76 1# b00000000000000000000000000100110 $ #77 0# #78 1# b00000000000000000000000000100111 $ #79 0# #80 1# b00000000000000000000000000101000 $ #81 0# #82 1# b00000000000000000000000000101001 $ #83 0# #84 1# b00000000000000000000000000101010 $ #85 0# #86 1# b00000000000000000000000000101011 $ #87 0# #88 1# b00000000000000000000000000101100 $ #89 0# #90 1# b00000000000000000000000000101101 $ #91 0# #92 1# b00000000000000000000000000101110 $ #93 0# #94 1# b00000000000000000000000000101111 $ #95 0# #96 1# b00000000000000000000000000110000 $ #97 0# #98 1# b00000000000000000000000000110001 $ #99 0# #100 1# b00000000000000000000000000110010 $ #101 0# #102 1# b00000000000000000000000000110011 $ #103 0# #104 1# b00000000000000000000000000110100 $ #105 0# #106 1# b00000000000000000000000000110101 $ #107 0# #108 1# b00000000000000000000000000110110 $ #109 0# #110 1# b00000000000000000000000000110111 $ #111 0# #112 1# b00000000000000000000000000111000 $ #113 0# #114 1# b00000000000000000000000000111001 $ #115 0# #116 1# b00000000000000000000000000111010 $ #117 0# #118 1# b00000000000000000000000000111011 $ #119 0# #120 1# b00000000000000000000000000111100 $ #121 0# #122 1# b00000000000000000000000000111101 $ #123 0# #124 1# b00000000000000000000000000111110 $ #125 0# #126 1# b00000000000000000000000000111111 $ #127 0# #128 1# b00000000000000000000000001000000 $ #129 0# #130 1# b00000000000000000000000001000001 $ #131 0# #132 1# b00000000000000000000000001000010 $ #133 0# #134 1# b00000000000000000000000001000011 $ #135 0# #136 1# b00000000000000000000000001000100 $ #137 0# #138 1# b00000000000000000000000001000101 $ #139 0# #140 1# b00000000000000000000000001000110 $ #141 0# #142 1# b00000000000000000000000001000111 $ #143 0# #144 1# b00000000000000000000000001001000 $ #145 0# #146 1# b00000000000000000000000001001001 $ #147 0# #148 1# b00000000000000000000000001001010 $ #149 0# #150 1# b00000000000000000000000001001011 $ #151 0# #152 1# b00000000000000000000000001001100 $ #153 0# #154 1# b00000000000000000000000001001101 $ #155 0# #156 1# b00000000000000000000000001001110 $ #157 0# #158 1# b00000000000000000000000001001111 $ #159 0# #160 1# b00000000000000000000000001010000 $ #161 0# #162 1# b00000000000000000000000001010001 $ #163 0# #164 1# b00000000000000000000000001010010 $ #165 0# #166 1# b00000000000000000000000001010011 $ #167 0# #168 1# b00000000000000000000000001010100 $ #169 0# #170 1# b00000000000000000000000001010101 $ #171 0# #172 1# b00000000000000000000000001010110 $ #173 0# #174 1# b00000000000000000000000001010111 $ #175 0# #176 1# b00000000000000000000000001011000 $ #177 0# #178 1# b00000000000000000000000001011001 $ #179 0# #180 1# b00000000000000000000000001011010 $ #181 0# #182 1# b00000000000000000000000001011011 $ #183 0# #184 1# b00000000000000000000000001011100 $ #185 0# #186 1# b00000000000000000000000001011101 $ #187 0# #188 1# b00000000000000000000000001011110 $ #189 0# verilator-5.042/test_regress/t/t_dpi_export.py0000755000542200017500000000120715101701376022143 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # irun -sv top.v t_dpi_export.v -cpost t_dpi_export_c.c -end import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=["t/t_dpi_export_c.cpp"], verilator_flags2=["-Wall -Wno-DECLFILENAME -no-l2name"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_preproc_inc_bad.py0000755000542200017500000000105615101701376023101 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint( fails=True, # The .vh file has the error, not the .v file expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_display_string.py0000755000542200017500000000100015101701376023010 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dist_error_format.py0000755000542200017500000000606015101701376023514 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') # Check all error messages match our standard format # This assumes .out files cover all important errors def formats(): files = test.root + "/test_regress/t/*.out" warns = {} lnmatch = 0 for filename in test.glob_some(files): if re.search(r'\.sarif\.out', filename): continue wholefile = test.file_contents(filename) filename = os.path.basename(filename) if re.search(r'(Exiting due to|%Error|%Warning)', wholefile): lineno = 0 for line in wholefile.splitlines(): lineno += 1 line = re.sub(r'(\$display|\$write).*\".*%(Error|Warning)', '', line) line = re.sub(r'<---.*', '', line) if (re.search(r'(Error|Warning)', line) and not re.search(r'^\s* " + test.obj_dir + "/" + test.name + "__nccover.html\n") test.run(logfile=test.obj_dir + "/" + test.name + "__nccover.log", tee=False, cmd=[test.getenv_def("VERILATOR_ICCR", 'iccr'), "-test", test.name, cf]) test.file_grep(test.run_log_filename, r'COVER: Cyc==4') test.file_grep(test.run_log_filename, r'COVER: Cyc==5') test.file_grep(test.run_log_filename, r'COVER: Cyc==6') # Allow old SystemC::Coverage format dump, or new binary dump test.file_grep(test.coverage_filename, r'(cyc_eq_5.*,c=>[^0]|cyc_eq_5.* [1-9][0-9]*\n)') test.passes() verilator-5.042/test_regress/t/t_property_negated.v0000644000542200017500000000157315101701376023161 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `define MAX 10 module t (/*AUTOARG*/ clk ); input clk; int cyc = 0; logic [`MAX:0] val = {`MAX+1{1'b0}}; initial val[0] = 1; Test1 t1(clk, cyc, val); always @(posedge clk) begin cyc <= cyc + 1; $display("val = %20b", val); if (cyc < `MAX) begin val[cyc] <= 0; val[cyc+1] <= 1; end else begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test1 ( clk, cyc, val ); input clk; input [`MAX:0] val; input integer cyc; assert property(@(posedge clk) not (&val)); assert property(@(posedge clk) (not ~|val)); endmodule verilator-5.042/test_regress/t/t_wait.out0000644000542200017500000000365515101701376021117 0ustar mahmoudyfreeshell%Error-NOTIMING: t/t_wait.v:12:7: Wait statements require --timing : ... note: In instance 't' 12 | wait (value == 1); | ^~~~ ... For error description see https://verilator.org/warn/NOTIMING?v=latest %Error-NOTIMING: t/t_wait.v:14:7: Wait statements require --timing : ... note: In instance 't' 14 | wait (0); | ^~~~ %Error-NOTIMING: t/t_wait.v:17:7: Wait statements require --timing : ... note: In instance 't' 17 | wait (value == 2); | ^~~~ %Error-NOTIMING: t/t_wait.v:20:7: Wait statements require --timing : ... note: In instance 't' 20 | wait (value == 3) if (value != 3) $stop; | ^~~~ %Warning-STMTDLY: t/t_wait.v:25:7: Ignoring delay on this statement due to --no-timing : ... note: In instance 't' 25 | #10; | ^ ... For warning description see https://verilator.org/warn/STMTDLY?v=latest ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message. %Warning-STMTDLY: t/t_wait.v:27:7: Ignoring delay on this statement due to --no-timing : ... note: In instance 't' 27 | #10; | ^ %Warning-STMTDLY: t/t_wait.v:29:7: Ignoring delay on this statement due to --no-timing : ... note: In instance 't' 29 | #10; | ^ %Warning-STMTDLY: t/t_wait.v:31:7: Ignoring delay on this statement due to --no-timing : ... note: In instance 't' 31 | #10; | ^ %Warning-STMTDLY: t/t_wait.v:33:7: Ignoring delay on this statement due to --no-timing : ... note: In instance 't' 33 | #10; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_struct_pat.v0000644000542200017500000000552115101701376021773 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; typedef struct { int a; int b; byte c; } sabcu_t; typedef struct packed { int a; int b; byte c; } sabcp_t; sabcu_t abcu; sabcp_t abcp; typedef struct { int a; int b4[4]; } sab4u_t; typedef struct packed { int a; bit [3:0][31:0] b4; } sab4p_t; typedef struct { int i; real r; } sir_t; sab4u_t ab4u[2][3]; sab4p_t ab4p[2][3]; sir_t sir; initial begin abcp = '{1, 2, 3}; abcu = '{1, 2, 3}; if (abcp.a !== 1) $stop; if (abcp.b !== 2) $stop; if (abcp.c !== 3) $stop; if (abcu.a !== 1) $stop; if (abcu.b !== 2) $stop; if (abcu.c !== 3) $stop; abcp = '{3{40}}; abcu = '{3{40}}; if (abcp.a !== 40) $stop; if (abcp.b !== 40) $stop; if (abcp.c !== 40) $stop; if (abcu.a !== 40) $stop; if (abcu.b !== 40) $stop; if (abcu.c !== 40) $stop; abcp = '{default:4, int:5}; abcu = '{default:4, int:5}; if (abcp.a !== 5) $stop; if (abcp.b !== 5) $stop; if (abcp.c !== 4) $stop; if (abcu.a !== 5) $stop; if (abcu.b !== 5) $stop; if (abcu.c !== 4) $stop; abcp = '{int:6, byte:7, int:8}; abcu = '{int:6, byte:7, int:8}; if (abcp.a !== 8) $stop; if (abcp.b !== 8) $stop; if (abcp.c !== 7) $stop; if (abcu.a !== 8) $stop; if (abcu.b !== 8) $stop; if (abcu.c !== 7) $stop; ab4p = '{2{'{3{'{10, '{2{20, 30}}}}}}}; ab4u = '{2{'{3{'{10, '{2{20, 30}}}}}}}; $display("%p", ab4p); if (ab4p[0][0].a !== 10) $stop; if (ab4p[0][0].b4[0] !== 30) $stop; if (ab4p[0][0].b4[1] !== 20) $stop; if (ab4p[0][0].b4[2] !== 30) $stop; if (ab4p[0][0].b4[3] !== 20) $stop; if (ab4p[1][2].a !== 10) $stop; if (ab4p[1][2].b4[0] !== 30) $stop; if (ab4p[1][2].b4[1] !== 20) $stop; if (ab4p[1][2].b4[2] !== 30) $stop; if (ab4p[1][2].b4[3] !== 20) $stop; $display("%p", ab4u); if (ab4u[0][0].a !== 10) $stop; if (ab4u[0][0].b4[0] !== 20) $stop; if (ab4u[0][0].b4[1] !== 30) $stop; if (ab4u[0][0].b4[2] !== 20) $stop; if (ab4u[0][0].b4[3] !== 30) $stop; if (ab4u[1][2].a !== 10) $stop; if (ab4u[1][2].b4[0] !== 20) $stop; if (ab4u[1][2].b4[1] !== 30) $stop; if (ab4u[1][2].b4[2] !== 20) $stop; if (ab4u[1][2].b4[3] !== 30) $stop; sir = '{1, 2.2}; if (sir.i !== 1) $stop; if (sir.r !== 2.2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_xml_output.out0000644000542200017500000000163115101701376022363 0ustar mahmoudyfreeshell verilator-5.042/test_regress/t/t_math_eq_bad.py0000755000542200017500000000076615101701376022223 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_math_strwidth.py0000755000542200017500000000074715101701376022657 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=[]) test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_timing1.py0000755000542200017500000000130615101701376022514 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile( verilator_flags=[ # Custom as don't want -cc "-Mdir", test.obj_dir, "--debug-check" ], verilator_flags2=['--binary --trace-vcd'], make_main=False) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_hier_block_nohier.py0000755000542200017500000000264115101701376023436 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # This test makes sure that the internal check of t_hier_block.v is correct. # --hierarchical option is not set intentionally. import vltest_bootstrap # stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. test.clean_objs() test.scenarios('vlt_all') test.top_filename = "t/t_hier_block.v" # CI environment offers 2 VCPUs, 2 thread setting causes the following warning. # %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. # So use 6 threads here though it's not optimal in performance, but ok. test.compile(v_flags2=['t/t_hier_block.cpp'], verilator_flags2=[ '--stats', '+define+USE_VLT', 't/t_hier_block_vlt.vlt', '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"' ], threads=(6 if test.vltmt else 1)) test.execute() test.file_grep_not(test.stats, r'HierBlock,\s+Hierarchical blocks\s+(\d+)') test.file_grep(test.run_log_filename, r'MACRO:(\S+) is defined', "cplusplus") test.passes() verilator-5.042/test_regress/t/t_time_stamp64.v0000644000542200017500000000103215101701376022110 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under The Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 1) begin $write("[%0t] In %m: Hi\n", $time); $printtimescale; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_dynarray_bits.py0000755000542200017500000000076615101701376022651 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface_virtual_timing.v0000644000542200017500000000207715101701376024663 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 interface Bus; logic [15:0] data; endinterface module t; Bus intf1(), intf2(); virtual Bus vif1 = intf1, vif2 = intf2; task assign_to_vif2(); if ($c("0")) return; #1 vif2.data = 'hfafa; #1; endtask initial forever begin intf1.data = 'hdead; if ($c("1")) begin #1 vif2.data = 'hbeef; #1; end intf1.data = 'hcafe; if ($c("0")); else begin #1 vif2.data = 'hface; #1; end intf1.data = 'hfeed; while ($time < 5) begin #1 vif2.data = 'hdeed; #1; end intf1.data = 'hdeaf; assign_to_vif2; intf1.data = 'hbebe; #1 $write("*-* All Finished *-*\n"); $finish; end always @(vif1.data) begin if ($time < 9) $write("[%0t] vif1.data==%h\n", $time, vif1.data); end always @(intf2.data) begin if ($time < 9) $write("[%0t] intf2.data==%h\n", $time, intf2.data); end endmodule verilator-5.042/test_regress/t/t_assigndly_dynamic_delay.py0000755000542200017500000000107015101701376024643 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_assigndly_dynamic" test.compile(verilator_flags2=["--binary +define+WITH_DELAY"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_if_deep.py0000755000542200017500000000106515101701376021363 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile( # We have deep expressions we want to test) verilator_flags2=["--compiler msvc"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_flag_werror_bad2.py0000755000542200017500000000110215101701376023161 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_flag_werror.v" test.lint(fails=True, verilator_flags=["-cc -Werror-WIDTH"], expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_semaphore_always.py0000755000542200017500000000077115101701376023336 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--timing"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_gen_div0.v0000644000542200017500000000137315101701376021277 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOINST*/); Test #( .BIT_WIDTH (72), .BYTE_WIDTH (9) ) u_test_inst(); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule module Test (); parameter BIT_WIDTH = ""; parameter BYTE_WIDTH = ""; localparam BYTES = BIT_WIDTH / BYTE_WIDTH; wire [BYTES - 1:0] i; wire [BYTES - 1:0] o; genvar g; generate for (g = 0; g < BYTES; g = g + 1) begin: gen assign o[g] = (i[g] !== 1'b0); end endgenerate endmodule verilator-5.042/test_regress/t/t_func_refio_bad.py0000755000542200017500000000077615101701376022725 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_static_function_in_class.v0000644000542200017500000000266215101701376024655 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Simple static elaboration case // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 class string_utils; typedef string array_of_string[]; static function array_of_string split_by_dash(string s); string parts[$]; int last_char_position = -1; for (int i = 0; i < s.len(); i++) begin if (i == s.len()-1) begin parts.push_back(s.substr(last_char_position+1, i)); end // Can't remove this, because then the code will work if (string'(s[i]) == "-") begin parts.push_back(s.substr(last_char_position+1, i-1)); last_char_position = i; end end // for (int i = 0; i < s.len(); i++) return parts; endfunction // split_by_dash endclass // string_utils class filter; local static filter single_instance; static function filter get(); if (single_instance == null) single_instance = new(); return single_instance; endfunction // get local function new(); string parts[] = string_utils::split_by_dash("*"); if (parts.size() != 1) $fatal(0, "Expected single element"); if (parts[0] != "*") $fatal(0, "Expected element to be *"); endfunction // new endclass // filter module t; const filter _filter = filter::get(); initial begin $write("*-* All Finished *-*\n"); $finish(); end endmodule verilator-5.042/test_regress/t/t_mod_nomod.v0000644000542200017500000000042715101701376021556 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // See issue #1381 logic root_var; // No module statements.... verilator-5.042/test_regress/t/t_tri_top_en_out_bad.v0000644000542200017500000000063515101701376023443 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Paul Wright. // SPDX-License-Identifier: CC0-1.0 // // A submodule to ensure that __en and __out propagate upwards // This version of the test should fail `define T_TRI_TOP_NAME t_tri_top_en_out_bad `define SKIP_TIMING 1 `include "t_tri_top_en_out.v" verilator-5.042/test_regress/t/t_cover_lib.py0000755000542200017500000000226215101701376021734 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(v_flags2=["--coverage t/t_cover_lib_c.cpp"], verilator_flags2=["--exe -Wall -Wno-DECLFILENAME"], make_flags=['CPPFLAGS_ADD=-DTEST_OBJ_DIR="' + test.obj_dir + '"'], make_top_shell=False, make_main=False) test.execute() test.files_identical_sorted(test.obj_dir + "/coverage1.dat", "t/t_cover_lib__1.out") test.files_identical_sorted(test.obj_dir + "/coverage2.dat", "t/t_cover_lib__2.out") test.files_identical_sorted(test.obj_dir + "/coverage3.dat", "t/t_cover_lib__3.out") test.files_identical_sorted(test.obj_dir + "/coverage4.dat", "t/t_cover_lib__4.out") test.files_identical_sorted(test.obj_dir + "/coverage1_per_instance.dat", "t/t_cover_lib__1_per_instance.out") test.passes() verilator-5.042/test_regress/t/t_interface_array.v0000644000542200017500000000345615101701376022746 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Functionally demonstrate an array of interfaces // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 interface foo_intf; bit a; modport source ( output a ); modport sink ( input a ); endinterface function integer identity (input integer val); return val; endfunction module t (/*AUTOARG*/ // Inputs clk ); input clk; localparam N = 5; bit [N-1:0] a_in; bit [N-1:0] a_out; bit [N-1:0] ack_out; foo_intf foos [N-1:0] (); // Deferred link dotting with genvars generate genvar i; for (i = 0; i < N-4; i++) begin : someLoop assign ack_out[i] = a_in[i]; assign foos[i].a = a_in[i]; assign a_out[i] = foos[i].a; end endgenerate // Defferred link dotting with localparam localparam THE_LP = N-3; assign ack_out[THE_LP] = a_in[THE_LP]; assign foos[THE_LP].a = a_in[THE_LP]; assign a_out[THE_LP] = foos[THE_LP].a; // Defferred link dotting with arithmetic expression assign ack_out[N-2] = a_in[N-2]; assign foos[N-2].a = a_in[N-2]; assign a_out[N-2] = foos[N-2].a; // Defferred link dotting with funcrefs assign ack_out[identity(N-1)] = a_in[identity(N-1)]; assign foos[identity(N-1)].a = a_in[identity(N-1)]; assign a_out[identity(N-1)] = foos[identity(N-1)].a; initial a_in = '0; always @(posedge clk) begin a_in <= a_in + { {N-1 {1'b0}}, 1'b1 }; if (ack_out != a_out) begin $display("%%Error: Interface and non-interface paths do not match: 0b%b 0b%b", ack_out, a_out); $stop; end if (& a_in) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_tri_struct_packed.out0000644000542200017500000000007615101701376023656 0ustar mahmoudyfreeshell%Error: t/t_tri_struct_packed.v:25: Verilog $stop Aborting... verilator-5.042/test_regress/t/t_dpi_result_type_bad.py0000755000542200017500000000106615101701376024012 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename, verilator_flags2=["-Wall --error-limit 0"]) test.passes() verilator-5.042/test_regress/t/t_extract_static_const_multimodule.out0000644000542200017500000000036315101701376027013 0ustar mahmoudyfreeshell0x88888888 0x66666666 0x44444444 0x22222222 0x1111111122222222333333334444444455555555666666667777777788888888 0x77777777 0x55555555 0x33333333 0x11111111 0x1111111122222222333333334444444455555555666666667777777788888888 *-* All Finished *-* verilator-5.042/test_regress/t/t_event_control_assign.v0000644000542200017500000000250115101701376024023 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 int evt_recv_cnt; int new_evt_recv_cnt; module t(); class Foo; event evt1; task automatic send_evt(); fork #10 begin ->evt1; end begin event new_event; #20; // This should cause an event merge but for now we don't support that. evt1 = new_event; end #30 begin @evt1 $display("Received a new event"); new_evt_recv_cnt++; end join_none endtask task wait_for_event(); fork begin @evt1 $display("Received evt1"); evt_recv_cnt++; end join_none endtask endclass initial begin Foo foo1; foo1 = new; evt_recv_cnt = 0; new_evt_recv_cnt = 0; for (int i = 0; i < 4; i++) begin foo1.wait_for_event(); #10; foo1.send_evt(); #90; $display("- end of iteration -"); if (evt_recv_cnt != i + 1) $stop; if (new_evt_recv_cnt != i) $stop; end if (evt_recv_cnt != 4) $stop; if (new_evt_recv_cnt != 3) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_string_dyn_num.py0000755000542200017500000000100015101701376023014 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_enum_bad_hide.py0000755000542200017500000000107515101701376022534 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["--lint-only -Wwarn-VARHIDDEN"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_trace_two_hdrfst_cc.out0000644000542200017500000000363215101701376024154 0ustar mahmoudyfreeshell$date Wed Feb 23 00:03:39 2022 $end $version fstWriter $end $timescale 1ps $end $scope module topa $end $var wire 1 ! clk $end $scope module t $end $var wire 1 ! clk $end $var integer 32 " cyc [31:0] $end $var integer 32 # c_trace_on [31:0] $end $scope module sub $end $var integer 32 $ inside_sub_a [31:0] $end $upscope $end $upscope $end $upscope $end $scope module topb $end $var wire 1 % clk $end $scope module t $end $var wire 1 % clk $end $var integer 32 & cyc [31:0] $end $var integer 32 ' c_trace_on [31:0] $end $var real 64 ( r $end $scope module sub $end $var integer 32 ) inside_sub_a [31:0] $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b00000000000000000000000000000010 ) r0 ( b00000000000000000000000000000000 ' b00000000000000000000000000000001 & 0% b00000000000000000000000000000001 $ b00000000000000000000000000000000 # b00000000000000000000000000000001 " 0! $end #10 1! b00000000000000000000000000000010 " b00000000000000000000000000000011 # 1% r0.1 ( #15 0% 0! #20 1! 1% r0.2 ( b00000000000000000000000000000100 # b00000000000000000000000000000011 " #25 0% 0! #30 1! 1% b00000000000000000000000000000100 " b00000000000000000000000000000101 # r0.3 ( #35 0% 0! #40 1! 1% r0.4 ( b00000000000000000000000000000110 # b00000000000000000000000000000101 " #45 0% 0! #50 1! 1% b00000000000000000000000000000110 " b00000000000000000000000000000111 # r0.5 ( #55 0% 0! #60 1! 1% r0.6 ( b00000000000000000000000000001000 # b00000000000000000000000000000111 " #65 0% 0! #70 1! 1% b00000000000000000000000000001000 " b00000000000000000000000000001001 # r0.7 ( #75 0% 0! #80 1! 1% r0.7999999999999999 ( b00000000000000000000000000001010 # b00000000000000000000000000001001 " #85 0% 0! #90 1! 1% b00000000000000000000000000001010 " b00000000000000000000000000001011 # r0.8999999999999999 ( #95 0% 0! #100 1! 1% r0.9999999999999999 ( b00000000000000000000000000001100 # b00000000000000000000000000001011 " verilator-5.042/test_regress/t/t_altera_lpm_inv.py0000755000542200017500000000111115101701376022754 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) test.compile(verilator_flags2=["--top-module", module]) test.passes() verilator-5.042/test_regress/t/t_param_array.v0000644000542200017500000000505515101701376022103 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 module t; typedef enum int { PADTYPE_DEFAULT = 32'd0, PADTYPE_GPIO, PADTYPE_VDD, PADTYPE_GND } t_padtype; localparam int STR_PINID [0:15] = '{ "DEF", "ERR", "ERR", "ERR", "ERR", "ERR", "ERR", "ERR", "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7" }; typedef struct packed { t_padtype padtype; int aux; } t_pin_descriptor; localparam t_pin_descriptor PINOUT[ 1: 6] = '{ '{default:0, padtype:PADTYPE_GPIO, aux:1}, '{default:0, padtype:PADTYPE_GPIO}, '{default:0, padtype:PADTYPE_GPIO}, '{default:0, padtype:PADTYPE_GPIO}, '{default:0, padtype:PADTYPE_VDD}, '{default:0, padtype:PADTYPE_GND} }; localparam int PINOUT_SIZE = 6; localparam int PINOUT_WA[1:PINOUT_SIZE][3] = '{ '{0, PADTYPE_GPIO, 0}, '{1, PADTYPE_GPIO, 0}, '{2, PADTYPE_GPIO, 0}, '{5, PADTYPE_GPIO, 0}, '{6, PADTYPE_VDD, 0}, '{8, PADTYPE_GND , 0} }; const int pinout_static_const[1:PINOUT_SIZE][3] = '{ '{0, PADTYPE_GPIO, 0}, '{1, PADTYPE_GPIO, 0}, '{2, PADTYPE_GPIO, 0}, '{5, PADTYPE_GPIO, 0}, '{6, PADTYPE_VDD, 0}, '{8, PADTYPE_GND , 0} }; // Make sure consants propagate checkstr #(.PINID(STR_PINID[1]), .EXP("ERR")) substr1 (); checkstr #(.PINID(STR_PINID[8]), .EXP("PA0")) substr8 (); initial begin $display("PINID1 %s", STR_PINID[1]); $display("PINID8 %s", STR_PINID[8]); if (STR_PINID[1] != "ERR") $stop; if (STR_PINID[8] != "PA0") $stop; if (pinout_static_const[1][0] != 0) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module checkstr; parameter int PINID = " "; parameter int EXP = " "; initial begin $display("PID %s EXP %s", PINID, EXP); if (EXP != "ERR" && EXP != "PA0") $stop; if (PINID != EXP) $stop; end endmodule verilator-5.042/test_regress/t/t_property_sexpr_bad.out0000644000542200017500000000072315101701376024057 0ustar mahmoudyfreeshell%Error: t/t_property_sexpr_bad.v:20:39: Syntax error: unexpected 'not' in sequence expression : ... note: In instance 't' 20 | assert property (@(posedge clk) ##1 not val) $display("[%0t] single delay with negated var stmt, fileline:%d", $time, 20); | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_flag_expand_limit.v0000644000542200017500000000110315101701376023241 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // issue3005 module t #(parameter NV = 2000) ( input a, input w1, input [127:0] w2, output [ 31:0] o, input [319:0] bi, output [319:0] bo ); // verilator lint_off WIDTH wire [NV-1:0] d = a ? NV'(0) : {NV{w2}}; // verilator lint_on WIDTH assign o = d[31:0]; assign bo = ~bi; endmodule verilator-5.042/test_regress/t/t_recursive_module_bug.py0000755000542200017500000000071415101701376024201 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.passes() verilator-5.042/test_regress/t/t_timing_events.py0000755000542200017500000000076315101701376022647 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_queue_void_ops.v0000644000542200017500000001431415101701376022631 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; int cyc = 0; // Test for https://github.com/verilator/verilator/issues/3364 // Make sure all SV queue API is supported and verilator can generate // compile-able C++ models for it. // simple queue logic [31:0] my_int_queue [$]; // On the functions and tasks, the my_int_queue.pop_[front|back]() call will // have nodep->firstAbovep() != nullptr. Because the pop_front or pop_back is // the first node on the "list". // To fix this, V3Width.cpp will not use firstAbovep(), and instead us // isStandalongStmt() -- which checks if the pop_front or pop_back is // 2nd or later, or if it's first in the list that it's in a "block" of code. // For functions/tasks, that is checked with: // VN_IS(backp(), NodeFTask)=True, so even though function automatic void f_pop_back__my_int_queue(); void'(my_int_queue.pop_back()); endfunction : f_pop_back__my_int_queue function automatic void f_pop_front__my_int_queue(); void'(my_int_queue.pop_front()); endfunction : f_pop_front__my_int_queue task automatic t_pop_back__my_int_queue(); void'(my_int_queue.pop_back()); endtask : t_pop_back__my_int_queue task automatic t_pop_front__my_int_queue(); void'(my_int_queue.pop_front()); endtask : t_pop_front__my_int_queue task automatic do_random_queue_operation(); bit [7:0] rand_op; int rand_index; logic [31:0] item; rand_op = 8'($urandom_range(32, 0)); case(rand_op) 8'd0: ; // nop // pushes (2x of these) 8'd1, 8'd2: my_int_queue.push_back($urandom); 8'd3, 8'd4: my_int_queue.push_front($urandom); // delete: 8'd5: my_int_queue.delete(); // insert(index, item): 8'd6: begin rand_index = $urandom_range(my_int_queue.size()); my_int_queue.insert(rand_index, item); end // shuffle 8'd7: my_int_queue.shuffle(); // Various pops for rand_op >= 8: // pops to var // V3Width debug -- firstAbovep()=ASSIGN (which I guess does the ; for us // so we don't need the queue op to // do it.) // isStandalongStmt() will ignore ASSIGN, return false (NodeAssign is // child of AstNodeStmt) 8'd8: if (my_int_queue.size() > 0) item = my_int_queue.pop_front(); 8'd9: if (my_int_queue.size() > 0) item = my_int_queue.pop_back(); // pops to the void // V3Width debug -- firstAbovep()=IF // This is fixed with isStandalongStmt() -- VN_IS(backp(), NodeIf)=True 8'd10: if (my_int_queue.size() > 0) void'(my_int_queue.pop_front()); 8'd11: if (my_int_queue.size() > 0) void'(my_int_queue.pop_back()); // pop result to the lhs of a condition, and do something with it. 8'd12: if (my_int_queue.size() > 0) // V3Width debug -- firstAbovep()=LTE (good we don't want a ; here) if (my_int_queue.pop_front() <= 2022) my_int_queue.push_front(3022); // living in the year 3022. // pop result to the rhs of a condition, and do something with it. 8'd13: if (my_int_queue.size() > 0) // V3Width debug -- firstAbovep()=GT (good we don't want a ; here) if (4022 > my_int_queue.pop_front()) my_int_queue.push_front(3023); // living in the year 3023. // pops to the void after yet another case: // V3Width debug -- firstAbovep()=CASEITEM (not a nullptr) // This is fixed with isStandalongStmt() -- VN_IS(backp(), CaseItem)=True 8'd14: case (my_int_queue.size() > 0) 0: ; 1: void'(my_int_queue.pop_front()); default: ; endcase // case (my_int_queue.size() > 0) // V3Width debug -- firstAbovep()=CASEITEM (not a nullptr) // backp()->nextp()=CASEITEM (different one) // This is fixed with isStandalongStmt() -- VN_IS(backp(), CaseItem)=True 8'd15: case (my_int_queue.size() > 0) 0: ; 1: void'(my_int_queue.pop_back()); default; endcase // case (my_int_queue.size() > 0) // pops in a function or task 8'd16: if (my_int_queue.size() > 0) f_pop_back__my_int_queue(); 8'd17: if (my_int_queue.size() > 0) f_pop_front__my_int_queue(); 8'd18: if (my_int_queue.size() > 0) t_pop_back__my_int_queue(); 8'd19: if (my_int_queue.size() > 0) t_pop_front__my_int_queue(); // But what if we put some dummy code before the pop_back() or pop_front(): 8'd20: begin if (my_int_queue.size() > 0) begin ; // dummy line // V3Width debug -- firstAbovep()=BEGIN (is not nullptr). // This is fixed with isStandalongStmt() -- VN_IS(backp(), NodeIf)=True void'(my_int_queue.pop_back()); end end 8'd21: begin automatic int temp_int = 0; if (my_int_queue.size() > 0) begin temp_int = 5; // dummy line // V3Width debug -- firstAbovep()=nullptr (good) void'(my_int_queue.pop_back()); end end 8'd22: begin if (my_int_queue.size() > 0) begin automatic int some_temp_dummy_int; some_temp_dummy_int = 42; // V3Width debug -- firstAbovep()=nullptr (good) void'(my_int_queue.pop_back()); end end 8'd23: begin if (my_int_queue.size() > 0) begin // no dummy here, just a 'begin' helper before it. // V3Width debug -- firstAbovep()=BEGIN (is not nullptr). // This is fixed with isStandalongStmt() -- VN_IS(backp(), NodeIf)=True void'(my_int_queue.pop_back()); end end // What about an if of something else, followed by a pop_front? 8'd24: begin automatic int temp_int = 0; if (my_int_queue.size() == 0) begin // dummy temp_int = 1000; end void'(my_int_queue.pop_front()); // firstAbovep() should be nullptr here. end default: ; // nop endcase // case (rand_op) endtask : do_random_queue_operation always @ (posedge clk) begin : main cyc <= cyc + 1; do_random_queue_operation(); if (cyc > 100) begin $write("*-* All Finished *-*\n"); $finish(); end end endmodule : t verilator-5.042/test_regress/t/t_gate_inline_wide_noexclude_other_scope.v0000644000542200017500000000124415101701376027527 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 localparam N = 256; // Wider than expand limit. module t( input wire [N-1:0] i, output wire [N-1:0] o ); // Do not exclude from inlining wides referenced in different scope. wire [N-1:0] wide = N ~^ i; sub sub(i, wide, o); endmodule module sub(input wire [N-1:0] i, input wire [N-1:0] wide, output logic [N-1:0] o); initial begin for (integer n = 0; n < N ; ++n) begin o[n] = i[N-1-n] | wide[N-1-n]; end end endmodule verilator-5.042/test_regress/t/t_delay_compare.py0000755000542200017500000000101015101701376022562 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["--binary"]) if not test.vlt: test.execute() test.passes() verilator-5.042/test_regress/t/t_mem_packed.v0000644000542200017500000001177215101701376021675 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; //Simple debug: //wire [1:1] wir_a [3:3] [2:2]; //11 //logic [1:1] log_a [3:3] [2:2]; //12 //wire [3:3] [2:2] [1:1] wir_p; //13 //logic [3:3] [2:2] [1:1] log_p; //14 integer cyc; initial cyc = 0; `ifdef IVERILOG reg [7:0] arr [3:0]; wire [7:0] arr_w [3:0]; `else reg [3:0] [7:0] arr; wire [3:0] [7:0] arr_w; `endif reg [7:0] sum; reg [7:0] sum_w; integer i0; initial begin for (i0=0; i0<5; i0=i0+1) begin arr[i0] = 1 << (i0[1:0]*2); end end assign arr_w = arr; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==0) begin // Setup sum <= 0; sum_w <= 0; end else if (cyc >= 10 && cyc < 14) begin sum <= sum + arr[cyc-10]; sum_w <= sum_w + arr_w[cyc-10]; end else if (cyc==99) begin $write("[%0t] cyc==%0d sum=%x\n", $time, cyc, sum); if (sum != 8'h55) $stop; if (sum != sum_w) $stop; $write("*-* All Finished *-*\n"); $finish; end end // Test ordering of packed dimensions logic [31:0] data_out; logic [31:0] data_out2; logic [0:0] [2:0] [31:0] data_in; logic [31:0] data_in2 [0:0] [2:0]; assign data_out = data_in[0][0] + data_in[0][1] + data_in[0][2]; assign data_out2 = data_in2[0][0] + data_in2[0][1] + data_in2[0][2]; logic [31:0] last_data_out; always @ (posedge clk) begin if (cyc <= 2) begin data_in[0][0] <= 0; data_in[0][1] <= 0; data_in[0][2] <= 0; data_in2[0][0] <= 0; data_in2[0][1] <= 0; data_in2[0][2] <= 0; end else if (cyc > 2 && cyc < 99) begin data_in[0][0] <= data_in[0][0] + 1; data_in[0][1] <= data_in[0][1] + 1; data_in[0][2] <= data_in[0][2] + 1; data_in2[0][0] <= data_in2[0][0] + 1; data_in2[0][1] <= data_in2[0][1] + 1; data_in2[0][2] <= data_in2[0][2] + 1; last_data_out <= data_out; `ifdef TEST_VERBOSE $write("data_out %0x %0x\n", data_out, last_data_out); `endif if (cyc > 4 && data_out != last_data_out + 3) $stop; if (cyc > 4 && data_out != data_out2) $stop; end end // Test for mixed implicit/explicit dimensions and all implicit packed bit [3:0][7:0][1:0] vld [1:0][1:0]; bit [3:0][7:0][1:0] vld2; // There are specific nodes for Or, Xor, Xnor and And logic vld_or; logic vld2_or; assign vld_or = |vld[0][0]; assign vld2_or = |vld2; logic vld_xor; logic vld2_xor; assign vld_xor = ^vld[0][0]; assign vld2_xor = ^vld2; logic vld_xnor; logic vld2_xnor; assign vld_xnor = ~^vld[0][0]; assign vld2_xnor = ~^vld2; logic vld_and; logic vld2_and; assign vld_and = &vld[0][0]; assign vld2_and = &vld2; // Bit reductions should be cloned, other unary operations should clone the // entire assign. bit [3:0][7:0][1:0] not_lhs; bit [3:0][7:0][1:0] not_rhs; assign not_lhs = ~not_rhs; // Test an AstNodeUniop that shouldn't be expanded bit [3:0][7:0][1:0] vld2_inv; assign vld2_inv = ~vld2; initial begin for (int i=0; i<4; i=i+2) begin for (int j=0; j<8; j=j+2) begin vld[0][0][i][j] = 2'b00; vld[0][0][i+1][j+1] = 2'b00; vld2[i][j] = 2'b00; vld2[i+1][j+1] = 2'b00; not_rhs[i][j] = i[1:0]; not_rhs[i+1][j+1] = i[1:0]; end end end logic [3:0] expect_cyc; initial expect_cyc = 'd15; always @(posedge clk) begin expect_cyc <= expect_cyc + 1; for (int i=0; i<4; i=i+1) begin for (int j=0; j<8; j=j+1) begin vld[0][0][i][j] <= vld[0][0][i][j] + 1; vld2[i][j] <= vld2[i][j] + 1; if (not_rhs[i][j] != ~not_lhs[i][j]) $stop; not_rhs[i][j] <= not_rhs[i][j] + 1; end end if (cyc % 8 == 0) begin vld[0][0][0][0] <= vld[0][0][0][0] - 1; vld2[0][0] <= vld2[0][0] - 1; end if (expect_cyc < 8 && !vld_xor) $stop; else if (expect_cyc > 7 && vld_xor) $stop; if (expect_cyc < 8 && vld_xnor) $stop; else if (expect_cyc > 7 && !vld_xnor) $stop; if (expect_cyc == 15 && vld_or) $stop; else if (expect_cyc == 11 && vld_or) $stop; else if (expect_cyc != 15 && expect_cyc != 11 && !vld_or) $stop; if (expect_cyc == 10 && !vld_and) $stop; else if (expect_cyc == 14 && !vld_and) $stop; else if (expect_cyc != 10 && expect_cyc != 14 && vld_and) $stop; if (vld_xor != vld2_xor) $stop; if (vld_xnor != vld2_xnor) $stop; if (vld_or != vld2_or) $stop; if (vld_and != vld2_and) $stop; end endmodule verilator-5.042/test_regress/t/t_alias_width_bad.py0000755000542200017500000000076315101701376023072 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface_gen10.py0000755000542200017500000000073415101701376022724 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_enumeration.py0000755000542200017500000000073415101701376022320 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_randcase_bad.v0000644000542200017500000000066515101701376022175 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Test of select from constant // // This tests issue #508, bit select of constant fails // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin randcase // Bad all zero weights 0 : $stop; endcase $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_static_in_loop_unsup.v0000644000542200017500000000110715101701376024037 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; initial begin int x = 0; while (x < 10) begin : outer_loop int y = 0; while (y < x) begin : inner_loop static int a = 0; a++; y++; end x++; end if (outer_loop.inner_loop.a != 45) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_constraint_pure_missing_bad.out0000644000542200017500000000075115101701376025723 0ustar mahmoudyfreeshell%Error: t/t_constraint_pure_missing_bad.v:11:1: Class 'Cls' extends 'Base' but is missing constraint implementation for 'raint' (IEEE 1800-2023 18.5.2) 11 | class Cls extends Base; | ^~~~~ t/t_constraint_pure_missing_bad.v:8:21: ... Location of interface class's pure constraint 8 | pure constraint raint; | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_tri_pull_bad.v0000644000542200017500000000043515101701376022242 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2010 by Lane Brooks. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; wire A; pullup p1(A); pulldown p2(A); endmodule verilator-5.042/test_regress/t/t_pli_bbox.py0000755000542200017500000000100615101701376021561 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_pli_bad.v" test.lint(verilator_flags2=["--bbox-sys"]) test.passes() verilator-5.042/test_regress/t/t_cuse_forward.v0000644000542200017500000000152615101701376022267 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class Baz; endclass class Bar#(type T) extends T; endclass class Foo; typedef struct { int field; } Zee; task t1(); // Refer to Baz CLASSREFDTYPE node in implementation (via CLASSEXTENDS) Bar#(Baz) b = new; endtask // Refer to the very same Baz CLASSREFDTYPE node again, this time within interface task t2(Bar#(Baz)::T b); endtask endclass class Moo; // Use Foo::Zee to cause inclusion of Foo's header file Foo::Zee z; endclass module t(); initial begin // Use Moo in top module to add Moo to root, causing inclusion of Foo header into // root header. Moo moo; moo = new; end endmodule verilator-5.042/test_regress/t/t_queue_arg.py0000755000542200017500000000073415101701376021747 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_queue_empty_bad.v0000644000542200017500000000055115101701376022751 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin int i; i = {} + 1; i = {}; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_constraint_method_bad.out0000644000542200017500000000052615101701376024477 0ustar mahmoudyfreeshell%Error: t/t_constraint_method_bad.v:13:12: No such constraint method 'bad_method' : ... note: In instance 't' 13 | cons.bad_method(1); | ^~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_property_sexpr.out0000644000542200017500000001426415101701376023256 0ustar mahmoudyfreeshell[4] single delay with const stmt, fileline:115 [5] concurrent assert else, fileline:167 [6] single delay with const stmt, fileline:115 [7] concurrent assert stmt, fileline:166 [8] single delay with const stmt, fileline:115 [9] concurrent assert else, fileline:167 [11] concurrent assert else, fileline:167 [12] single delay with var stmt, fileline:118 [13] concurrent assert else, fileline:167 [14] single delay with var else, fileline:119 [15] concurrent assert stmt, fileline:166 [16] single delay with var stmt, fileline:118 [17] concurrent assert else, fileline:167 [18] single delay with var else, fileline:119 [19] concurrent assert else, fileline:167 [20] single delay with var stmt, fileline:118 [21] concurrent assert else, fileline:167 [23] concurrent assert stmt, fileline:166 [25] concurrent assert else, fileline:167 [26] single multi-cycle delay with var else, fileline:123 [27] concurrent assert else, fileline:167 [28] single multi-cycle delay with var stmt, fileline:122 [29] concurrent assert else, fileline:167 [30] single multi-cycle delay with var else, fileline:123 [31] concurrent assert stmt, fileline:166 [33] concurrent assert else, fileline:167 [34] single delay with var brackets 1 else, fileline:127 [35] concurrent assert else, fileline:167 [36] single delay with var brackets 1 stmt, fileline:126 [37] concurrent assert else, fileline:167 [38] single delay with var brackets 1 else, fileline:127 [39] concurrent assert stmt, fileline:166 [40] single delay with var brackets 1 stmt, fileline:126 [41] concurrent assert else, fileline:167 [43] concurrent assert else, fileline:167 [44] single delay with var brackets 2 stmt, fileline:130 [45] concurrent assert else, fileline:167 [46] single delay with var brackets 2 else, fileline:131 [47] concurrent assert stmt, fileline:166 [48] single delay with var brackets 2 stmt, fileline:130 [49] concurrent assert else, fileline:167 [50] single delay with var brackets 2 else, fileline:131 [51] concurrent assert else, fileline:167 [53] concurrent assert else, fileline:167 [54] single delay with negated var else, fileline:135 [55] concurrent assert stmt, fileline:166 [56] single delay with negated var stmt, fileline:134 [57] concurrent assert else, fileline:167 [58] single delay with negated var else, fileline:135 [59] concurrent assert else, fileline:167 [60] single delay with negated var else, fileline:135 [61] concurrent assert else, fileline:167 [63] concurrent assert stmt, fileline:166 [64] single delay with negated var else, fileline:139 [65] concurrent assert else, fileline:167 [66] single delay with negated var stmt, fileline:138 [67] concurrent assert else, fileline:167 [68] single delay with negated var else, fileline:139 [69] concurrent assert else, fileline:167 [70] single delay with negated var stmt, fileline:138 [71] concurrent assert stmt, fileline:166 [73] concurrent assert else, fileline:167 [74] single delay with negated var brackets stmt, fileline:142 [75] concurrent assert else, fileline:167 [76] single delay with negated var brackets else, fileline:144 [77] concurrent assert else, fileline:167 [78] single delay with negated var brackets stmt, fileline:142 [79] concurrent assert stmt, fileline:166 [80] single delay with negated var brackets else, fileline:144 [81] concurrent assert else, fileline:167 [83] concurrent assert else, fileline:167 [84] single delay with negated var brackets else, fileline:148 [85] concurrent assert else, fileline:167 [87] concurrent assert stmt, fileline:166 [88] single delay with negated var brackets else, fileline:148 [89] concurrent assert else, fileline:167 [91] concurrent assert else, fileline:167 [93] concurrent assert else, fileline:167 [94] single delay with nested not else, fileline:152 [95] concurrent assert stmt, fileline:166 [96] single delay with nested not stmt, fileline:151 [97] concurrent assert else, fileline:167 [98] single delay with nested not else, fileline:152 [99] concurrent assert else, fileline:167 [100] single delay with nested not stmt, fileline:151 [101] concurrent assert else, fileline:167 [103] concurrent assert stmt, fileline:166 [105] concurrent assert else, fileline:167 [107] concurrent assert else, fileline:167 [109] concurrent assert else, fileline:167 [111] concurrent assert stmt, fileline:166 [113] concurrent assert else, fileline:167 [114] property, fileline:162 [115] concurrent assert else, fileline:167 [116] property, fileline:163 [117] concurrent assert else, fileline:167 [118] property, fileline:162 [119] concurrent assert stmt, fileline:166 [120] property, fileline:163 [121] concurrent assert else, fileline:167 [123] concurrent assert else, fileline:167 [125] concurrent assert else, fileline:167 [127] concurrent assert stmt, fileline:166 [129] concurrent assert else, fileline:167 [131] concurrent assert else, fileline:167 [133] concurrent assert else, fileline:167 [135] concurrent assert stmt, fileline:166 [137] concurrent assert else, fileline:167 [139] concurrent assert else, fileline:167 [141] concurrent assert else, fileline:167 [143] concurrent assert stmt, fileline:166 [145] concurrent assert else, fileline:167 [147] concurrent assert else, fileline:167 [149] concurrent assert else, fileline:167 [151] concurrent assert stmt, fileline:166 [153] concurrent assert else, fileline:167 [155] concurrent assert else, fileline:167 [157] concurrent assert else, fileline:167 [159] concurrent assert stmt, fileline:166 [161] concurrent assert else, fileline:167 [163] concurrent assert else, fileline:167 [165] concurrent assert else, fileline:167 [167] concurrent assert stmt, fileline:166 [169] concurrent assert else, fileline:167 [171] concurrent assert else, fileline:167 [173] concurrent assert else, fileline:167 [175] concurrent assert stmt, fileline:166 [177] concurrent assert else, fileline:167 [179] concurrent assert else, fileline:167 [181] concurrent assert else, fileline:167 [183] concurrent assert stmt, fileline:166 [185] concurrent assert else, fileline:167 [187] concurrent assert else, fileline:167 [189] concurrent assert else, fileline:167 [191] concurrent assert stmt, fileline:166 [193] concurrent assert else, fileline:167 [195] concurrent assert else, fileline:167 [197] concurrent assert else, fileline:167 [199] concurrent assert stmt, fileline:166 *-* All Finished *-* verilator-5.042/test_regress/t/t_class_extends_protect_ids.py0000755000542200017500000000161215101701376025224 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_class_extends.v" # This test makes randomly named .cpp/.h files, which tend to collect, so remove them first for filename in (glob.glob(test.obj_dir + "/*_PS*.cpp") + glob.glob(test.obj_dir + "/*_PS*.h") + glob.glob(test.obj_dir + "/*.d")): test.unlink_ok(filename) test.compile( make_flags=['VM_PARALLEL_BUILDS=1'], # bug2775 verilator_flags2=["--protect-ids", "--protect-key SECRET_KEY"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_class_new_return.py0000755000542200017500000000073415101701376023347 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_gen10_noinl.py0000755000542200017500000000104015101701376024112 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_gen10.v" test.compile(v_flags2=["-fno-inline"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_param_implicit_local_bad.v0000644000542200017500000000205715101701376024556 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2023 by Anthony Donlon. // SPDX-License-Identifier: CC0-1.0 module t; class NestedCls #( parameter A = 0 ); parameter B = 0; endclass NestedCls #(1, 2) cls; mod1 # ( 3, 4, 5 ) i_mod1 (); mod2 # ( 5, 12, 13 ) i_mod2 (); mod3 # ( 7, 24, 25 ) i_mod3 (); intf1 # ( 8, 15, 17 ) i_intf1 (); prgm1 # ( 9, 40, 41 ) i_prgm1 (); endmodule `define CHECK_PARAMS if (A**2 + B**2 != C**2) $error("A**2 + B**2 != C**2") module mod1 # ( parameter A = 1, B = 1 ); parameter C = 1; `CHECK_PARAMS; endmodule module mod2 (); parameter A = 1, B = 1, C = 1; `CHECK_PARAMS; endmodule module mod3 #() (); parameter A = 1, B = 1, C = 1; `CHECK_PARAMS; endmodule interface intf1 # ( parameter A = 1, B = 1 ); parameter C = 1; `CHECK_PARAMS; endinterface program prgm1 # ( parameter A = 1, B = 1 ); parameter C = 1; `CHECK_PARAMS; endprogram verilator-5.042/test_regress/t/t_cuse_forward.py0000755000542200017500000000070615101701376022454 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.passes() verilator-5.042/test_regress/t/t_dpi_binary_c.cpp0000644000542200017500000000137515101701376022545 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "t_dpi_binary_c.h" #include "svdpi.h" #include //====================================================================== extern "C" void dpic_final(); void dpic_final() { printf("%s:\n", __func__); printf("*-* All Finished *-*\n"); } verilator-5.042/test_regress/t/t_param_real2.py0000755000542200017500000000073415101701376022157 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_func_no_parentheses_bad.py0000755000542200017500000000105515101701376024625 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) if not test.vlt_all: test.execute() test.passes() verilator-5.042/test_regress/t/t_for_funcbound.v0000644000542200017500000000314215101701376022431 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer j; integer hit_count; reg [63:0] cam_lookup_hit_vector; strings strings (); task show; input [8*8-1:0] str; reg [7:0] char; integer loc; begin $write("[%0t] ", $time); strings.stringStart(8*8-1); for (char = strings.stringByte(str); !strings.isNull(char); char = strings.stringByte(str)) begin $write("%c",char); end $write("\n"); end endtask integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin show("hello\000xx"); end if (cyc==2) begin show("world\000xx"); end if (cyc==4) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module strings; // **NOT** reentrant, just a test! integer index; task stringStart; input [31:0] bits; begin index = (bits-1)/8; end endtask function isNull; input [7:0] chr; isNull = (chr == 8'h0); endfunction function [7:0] stringByte; input [8*8-1:0] str; begin if (index<=0) stringByte=8'h0; else stringByte = str[index*8 +: 8]; index = index - 1; end endfunction endmodule verilator-5.042/test_regress/t/t_select_bound1.v0000644000542200017500000000473715101701376022342 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // bug823 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [2:0] in = crc[2:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [3:0] mask; // From test of Test.v wire [3:0] out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out (out[3:0]), .mask (mask[3:0]), // Inputs .clk (clk), .in (in[2:0])); // Aggregate outputs into a single result vector wire [63:0] result = {60'h0, out & mask}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x out=%b mask=%b\n", $time, cyc, crc, out, mask); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc<10) begin sum <= '0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'ha9d3a7a69d2bea75 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs out, mask, // Inputs clk, in ); input clk; input [2:0] in; output reg [3:0] out; output reg [3:0] mask; localparam [15:5] P = 11'h1ac; always @(posedge clk) begin // verilator lint_off WIDTH out <= P[15 + in -: 5]; // verilator lint_on WIDTH end always @(posedge clk) begin mask[3] <= ((15 + in - 5) < 12); mask[2] <= ((15 + in - 5) < 13); mask[1] <= ((15 + in - 5) < 14); mask[0] <= ((15 + in - 5) < 15); end endmodule verilator-5.042/test_regress/t/t_interface_virtual_sched_act.py0000755000542200017500000000103515101701376025470 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_mem_multi_io.py0000755000542200017500000000113615101701376022446 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile( # Disable inlining, this test is trivial without it verilator_flags2=["-fno-inline --trace-vcd"], verilator_flags3=[]) test.execute() test.passes() verilator-5.042/test_regress/t/t_config_libmap.out0000644000542200017500000000370515101701376022740 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_config_libmap.map:9:1: Unsupported: IEEE 1800-2001-config lib.map reserved word not implemented: 'include' : ... Suggest unless in a lib.map file, want `include instead 9 | include ./t_config_libmap_inc.map | ^~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: t/t_config_libmap.map:9:9: syntax error, unexpected '.' 9 | include ./t_config_libmap_inc.map | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error-UNSUPPORTED: t/t_config_libmap.map:11:1: Unsupported: IEEE 1800-2001-config lib.map reserved word not implemented: 'library' 11 | library rtllib *.v; | ^~~~~~~ %Error-UNSUPPORTED: t/t_config_libmap.map:12:1: Unsupported: IEEE 1800-2001-config lib.map reserved word not implemented: 'library' 12 | library rtllib2 *.v, *.sv; | ^~~~~~~ %Error-UNSUPPORTED: t/t_config_libmap.map:13:1: Unsupported: IEEE 1800-2001-config lib.map reserved word not implemented: 'library' 13 | library rtllib3 *.v -incdir *.vh; | ^~~~~~~ %Error-UNSUPPORTED: t/t_config_libmap.map:13:22: Unsupported: IEEE 1800-2001-config lib.map reserved word not implemented: 'incdir' 13 | library rtllib3 *.v -incdir *.vh; | ^~~~~~ %Error-UNSUPPORTED: t/t_config_libmap.map:14:1: Unsupported: IEEE 1800-2001-config lib.map reserved word not implemented: 'library' 14 | library rtllib4 *.v -incdir *.vh, *.svh; | ^~~~~~~ %Error-UNSUPPORTED: t/t_config_libmap.map:14:22: Unsupported: IEEE 1800-2001-config lib.map reserved word not implemented: 'incdir' 14 | library rtllib4 *.v -incdir *.vh, *.svh; | ^~~~~~ %Error-UNSUPPORTED: t/t_config_libmap.map:17:1: Unsupported: IEEE 1800-2001-config lib.map reserved word not implemented: 'library' 17 | library gatelib . | ^~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_math_cond_huge.py0000755000542200017500000000073415101701376022736 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_unsup_mixed.v0000644000542200017500000000122515101701376023166 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2016 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( input wire clk, input wire a, input wire b ); integer q; // bug1120 always @ (a or posedge clk) begin if (a) q = 0; else q = q + 1; end // bug934 integer qb; always @((a && b) or posedge clk) begin if (a) qb = 0; else qb = qb + 1; end always @(posedge clk) $display("%d", qb); // So qb is not optimized away endmodule verilator-5.042/test_regress/t/t_lint_inherit.py0000755000542200017500000000075115101701376022461 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["-fno-dfg"]) test.passes() verilator-5.042/test_regress/t/t_pp_defkwd_bad.out0000644000542200017500000000035115101701376022712 0ustar mahmoudyfreeshell%Error: t/t_pp_defkwd_bad.v:8:18: Attempting to define built-in directive: '`define' (IEEE 1800-2023 22.5.1) ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_interface_typo_bad.v0000644000542200017500000000102315101701376023415 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2016 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 //bug1097 interface foo_intf; endinterface module submod ( foo_intf foo ); endmodule module t; // Intentional typo, compiler should point this out, or that fo_intf does // not match foo_intf on the submod port map fo_intf the_foo(); submod submod_inst ( .foo (the_foo) ); endmodule verilator-5.042/test_regress/t/t_array_pattern_enum.v0000644000542200017500000000120215101701376023472 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package Pkg; typedef enum { RED=0, GREEN=1, BLUE=2 } color_t; typedef struct { color_t pixels[32]; } line_t; typedef struct { line_t line[32]; } screen_t; endpackage module t; Pkg::screen_t screen; initial begin screen = '{ default: '0, Pkg::color_t: Pkg::RED}; $display("%p", screen); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_dpi_sys_c.cpp0000644000542200017500000000217515101701376022076 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "svdpi.h" #include //====================================================================== // clang-format off #if defined(VERILATOR) # include "Vt_dpi_sys__Dpi.h" #elif defined(VCS) # include "../vc_hdrs.h" #elif defined(CADENCE) # define NEED_EXTERNS #else # error "Unknown simulator for DPI test" #endif // clang-format on #ifdef NEED_EXTERNS extern "C" { extern void dpii_sys_task(int i); extern int dpii_sys_func(int i); } #endif //====================================================================== static int hidden = 0; void dpii_sys_task(int i) { hidden = i; } int dpii_sys_func(int i) { return i + hidden; } verilator-5.042/test_regress/t/t_hier_task.py0000755000542200017500000000073415101701376021743 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_clocked_release_combo.v0000644000542200017500000000207415101701376024066 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 // verilator lint_off MULTIDRIVEN module t (/*AUTOARG*/ // Inputs clk ); input clk; logic [31:0] lhs1, lhs2, rhs; logic cond = 0; always_comb lhs1 = rhs; assign lhs2 = rhs; always @(posedge clk) rhs = '1; always @(negedge clk) begin if (cond) begin force lhs1 = 'hdeadbeef; force lhs2 = 'hfeedface; end else begin release lhs1; release lhs2; end end int cyc = 0; always @(posedge clk) begin cyc <= cyc + 1; if (cyc == 0) cond <= 1; if (cyc == 3) cond <= 0; if (cyc > 1 && cyc < 4) begin if (lhs1 != 'hdeadbeef) $stop; if (lhs2 != 'hfeedface) $stop; end if (cyc > 4 && cyc < 8) begin if (lhs1 != '1) $stop; if (lhs2 != '1) $stop; end if (cyc >= 8) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_debug_trace.py0000755000542200017500000000110215101701376022224 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile( # Check we can call dump() on graph, and other things v_flags=["--trace-vcd --debug --debugi 0 --debugi-V3Trace 9"]) test.passes() verilator-5.042/test_regress/t/t_timing_clkgen_unsup.out0000644000542200017500000000066615101701376024216 0ustar mahmoudyfreeshell%Warning-MINTYPMAXDLY: t/t_timing_clkgen1.v:9:13: Unsupported: minimum/typical/maximum delay expressions. Using the typical delay 9 | #(8.0:5:3) clk = 1; | ^ ... For warning description see https://verilator.org/warn/MINTYPMAXDLY?v=latest ... Use "/* verilator lint_off MINTYPMAXDLY */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_param_pattern_init.py0000755000542200017500000000073415101701376023652 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_select_crazy.v0000644000542200017500000000155315101701376022273 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Dotted reference that uses another dotted reference // as the select expression // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 interface foo_intf; logic a; endinterface function integer the_other_func (input integer val); return val; endfunction module t; genvar the_genvar; generate for (the_genvar = 0; the_genvar < 4; the_genvar++) begin: foo_loop foo foo_inst(); end endgenerate bar bar_inst(); logic x; assign x = foo_loop[bar_inst.THE_LP].foo_inst.y; //localparam N = 2; //assign x = foo_loop[N].foo_inst.y; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule module foo(); logic y; endmodule module bar(); localparam THE_LP = 2; endmodule verilator-5.042/test_regress/t/t_udp_bad_illegal_output.v0000755000542200017500000000153415101701376024315 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 primitive t_gate_comb(dout, a, b, c); input a, b, c; output dout; table r 0 1 : ?: 1; r ? 1 : ?: 1; r ? 0 : ?: 1; 0 1 0 : ?: 0; 1 1 ? : ?: *; f r 0 : ?: 0; 0 0 0 : ?: *; endtable endprimitive primitive t_gate_seq(dout, a, b, c); input a, b, c; output dout; table x 0 1 : 1; r ? 1 : 1; 0 1 0 : 0; 1 1 ? : *; 1 0 0 : 0; 0 0 0 : *; endtable endprimitive module top (a, b, c, o1, o2); input a, b, c; output o1, o2; t_gate_comb(o1, a, b, c); t_gate_seq(o2, a, b, c); endmodule verilator-5.042/test_regress/t/t_interface_modport_bad.py0000755000542200017500000000076615101701376024311 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_func_return_bad.out0000644000542200017500000000174715101701376023313 0ustar mahmoudyfreeshell%Error: t/t_func_return_bad.v:10:7: Return underneath a task shouldn't have return value 10 | return 1; | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_func_return_bad.v:13:7: Return underneath a function should have return value 13 | return; | ^~~~~~ %Error: t/t_func_return_bad.v:17:7: Return isn't underneath a task or function 17 | return; | ^~~~~~ %Error: t/t_func_return_bad.v:18:7: continue isn't underneath a loop 18 | continue; | ^~~~~~~~ %Error: t/t_func_return_bad.v:19:7: break isn't underneath a loop 19 | break; | ^~~~~ %Error-UNSUPPORTED: t/t_func_return_bad.v:22:7: disable isn't underneath a begin with name: 'foo' 22 | disable foo; | ^~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_func_while.py0000755000542200017500000000075415101701376022117 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--trace-vcd"]) test.passes() verilator-5.042/test_regress/t/t_lint_in_inc_bad_2.vh0000644000542200017500000000041215101701376023261 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module x; // Syntax error if if if; endmodule verilator-5.042/test_regress/t/t_dpi_threads_c.cpp0000644000542200017500000000427315101701376022713 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2018-2018 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "svdpi.h" #include #include #include #include //====================================================================== // clang-format off #if defined(VERILATOR) # ifdef T_DPI_THREADS_COLLIDE # include "Vt_dpi_threads_collide__Dpi.h" # else # include "Vt_dpi_threads__Dpi.h" # endif #elif defined(VCS) # include "../vc_hdrs.h" #elif defined(CADENCE) # define NEED_EXTERNS #else # error "Unknown simulator for DPI test" #endif // clang-format on #ifdef NEED_EXTERNS extern "C" { extern void dpii_sys_task(); extern int dpii_failure(); } #endif //====================================================================== struct state { std::atomic task_is_running; std::atomic failure; state() : task_is_running(false) , failure(false) {} }; static state st; void dpii_sys_task() { bool other_task_running = atomic_exchange(&st.task_is_running, true); if (other_task_running) { // Another task is running. This is a collision. st.failure = 1; std::cerr << "t_dpi_threads_c.cpp dpii_sys_task() saw threads collide.\n"; } else { std::cerr << "t_dpi_threads_c.cpp dpii_sys_task() no collision. @" << &st.task_is_running << "\n"; } // Spend some time in the DPI call, so that if we can have a collision // we probably will. Technically this is not guaranteed to detect every // race. However, one second is so much greater than the expected // runtime of everything else in the test, it really should pick up on // races just about all of the time. sleep(1); atomic_exchange(&st.task_is_running, false); } int dpii_failure() { return st.failure; } verilator-5.042/test_regress/t/t_math_cond_clean.py0000755000542200017500000000073415101701376023070 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_dpi_arg_output_type.out0000644000542200017500000001206115101701376024230 0ustar mahmoudyfreeshelli_chandle 0 i_string 0 i_bit 0 i_logic 0 i_chandle_t 0 i_string_t 0 i_bit_t 0 i_logic_t 0 i_array_2_state_1 0 i_array_2_state_32 0 i_array_2_state_33 0 i_array_2_state_64 0 i_array_2_state_65 0 i_array_2_state_128 0 i_struct_2_state_1 0 i_struct_2_state_32 0 i_struct_2_state_33 0 i_struct_2_state_64 0 i_struct_2_state_65 0 i_struct_2_state_128 0 i_union_2_state_1 0 i_union_2_state_32 0 i_union_2_state_33 0 i_union_2_state_64 0 i_union_2_state_65 0 i_union_2_state_128 0 i_array_4_state_1 0 i_array_4_state_32 0 i_array_4_state_33 0 i_array_4_state_64 0 i_array_4_state_65 0 i_array_4_state_128 0 i_struct_4_state_1 0 i_struct_4_state_32 0 i_struct_4_state_33 0 i_struct_4_state_64 0 i_struct_4_state_65 0 i_struct_4_state_128 0 i_union_4_state_1 0 i_union_4_state_32 0 i_union_4_state_33 0 i_union_4_state_64 0 i_union_4_state_65 0 i_union_4_state_128 0 e_chandle 0 e_string 0 e_bit 0 e_logic 0 e_chandle_t 0 e_string_t 0 e_bit_t 0 e_logic_t 0 e_array_2_state_1 0 e_array_2_state_32 0 e_array_2_state_33 0 e_array_2_state_64 0 e_array_2_state_65 0 e_array_2_state_128 0 e_struct_2_state_1 0 e_struct_2_state_32 0 e_struct_2_state_33 0 e_struct_2_state_64 0 e_struct_2_state_65 0 e_struct_2_state_128 0 e_union_2_state_1 0 e_union_2_state_32 0 e_union_2_state_33 0 e_union_2_state_64 0 e_union_2_state_65 0 e_union_2_state_128 0 e_array_4_state_1 0 e_array_4_state_32 0 e_array_4_state_33 0 e_array_4_state_64 0 e_array_4_state_65 0 e_array_4_state_128 0 e_struct_4_state_1 0 e_struct_4_state_32 0 e_struct_4_state_33 0 e_struct_4_state_64 0 e_struct_4_state_65 0 e_struct_4_state_128 0 e_union_4_state_1 0 e_union_4_state_32 0 e_union_4_state_33 0 e_union_4_state_64 0 e_union_4_state_65 0 e_union_4_state_128 0 i_chandle 1 i_string 1 i_bit 1 i_logic 1 i_chandle_t 1 i_string_t 1 i_bit_t 1 i_logic_t 1 i_array_2_state_1 1 i_array_2_state_32 1 i_array_2_state_33 1 i_array_2_state_64 1 i_array_2_state_65 1 i_array_2_state_128 1 i_struct_2_state_1 1 i_struct_2_state_32 1 i_struct_2_state_33 1 i_struct_2_state_64 1 i_struct_2_state_65 1 i_struct_2_state_128 1 i_union_2_state_1 1 i_union_2_state_32 1 i_union_2_state_33 1 i_union_2_state_64 1 i_union_2_state_65 1 i_union_2_state_128 1 i_array_4_state_1 1 i_array_4_state_32 1 i_array_4_state_33 1 i_array_4_state_64 1 i_array_4_state_65 1 i_array_4_state_128 1 i_struct_4_state_1 1 i_struct_4_state_32 1 i_struct_4_state_33 1 i_struct_4_state_64 1 i_struct_4_state_65 1 i_struct_4_state_128 1 i_union_4_state_1 1 i_union_4_state_32 1 i_union_4_state_33 1 i_union_4_state_64 1 i_union_4_state_65 1 i_union_4_state_128 1 e_chandle 1 e_string 1 e_bit 1 e_logic 1 e_chandle_t 1 e_string_t 1 e_bit_t 1 e_logic_t 1 e_array_2_state_1 1 e_array_2_state_32 1 e_array_2_state_33 1 e_array_2_state_64 1 e_array_2_state_65 1 e_array_2_state_128 1 e_struct_2_state_1 1 e_struct_2_state_32 1 e_struct_2_state_33 1 e_struct_2_state_64 1 e_struct_2_state_65 1 e_struct_2_state_128 1 e_union_2_state_1 1 e_union_2_state_32 1 e_union_2_state_33 1 e_union_2_state_64 1 e_union_2_state_65 1 e_union_2_state_128 1 e_array_4_state_1 1 e_array_4_state_32 1 e_array_4_state_33 1 e_array_4_state_64 1 e_array_4_state_65 1 e_array_4_state_128 1 e_struct_4_state_1 1 e_struct_4_state_32 1 e_struct_4_state_33 1 e_struct_4_state_64 1 e_struct_4_state_65 1 e_struct_4_state_128 1 e_union_4_state_1 1 e_union_4_state_32 1 e_union_4_state_33 1 e_union_4_state_64 1 e_union_4_state_65 1 e_union_4_state_128 1 i_chandle 2 i_string 2 i_bit 2 i_logic 2 i_chandle_t 2 i_string_t 2 i_bit_t 2 i_logic_t 2 i_array_2_state_1 2 i_array_2_state_32 2 i_array_2_state_33 2 i_array_2_state_64 2 i_array_2_state_65 2 i_array_2_state_128 2 i_struct_2_state_1 2 i_struct_2_state_32 2 i_struct_2_state_33 2 i_struct_2_state_64 2 i_struct_2_state_65 2 i_struct_2_state_128 2 i_union_2_state_1 2 i_union_2_state_32 2 i_union_2_state_33 2 i_union_2_state_64 2 i_union_2_state_65 2 i_union_2_state_128 2 i_array_4_state_1 2 i_array_4_state_32 2 i_array_4_state_33 2 i_array_4_state_64 2 i_array_4_state_65 2 i_array_4_state_128 2 i_struct_4_state_1 2 i_struct_4_state_32 2 i_struct_4_state_33 2 i_struct_4_state_64 2 i_struct_4_state_65 2 i_struct_4_state_128 2 i_union_4_state_1 2 i_union_4_state_32 2 i_union_4_state_33 2 i_union_4_state_64 2 i_union_4_state_65 2 i_union_4_state_128 2 e_chandle 2 e_string 2 e_bit 2 e_logic 2 e_chandle_t 2 e_string_t 2 e_bit_t 2 e_logic_t 2 e_array_2_state_1 2 e_array_2_state_32 2 e_array_2_state_33 2 e_array_2_state_64 2 e_array_2_state_65 2 e_array_2_state_128 2 e_struct_2_state_1 2 e_struct_2_state_32 2 e_struct_2_state_33 2 e_struct_2_state_64 2 e_struct_2_state_65 2 e_struct_2_state_128 2 e_union_2_state_1 2 e_union_2_state_32 2 e_union_2_state_33 2 e_union_2_state_64 2 e_union_2_state_65 2 e_union_2_state_128 2 e_array_4_state_1 2 e_array_4_state_32 2 e_array_4_state_33 2 e_array_4_state_64 2 e_array_4_state_65 2 e_array_4_state_128 2 e_struct_4_state_1 2 e_struct_4_state_32 2 e_struct_4_state_33 2 e_struct_4_state_64 2 e_struct_4_state_65 2 e_struct_4_state_128 2 e_union_4_state_1 2 e_union_4_state_32 2 e_union_4_state_33 2 e_union_4_state_64 2 e_union_4_state_65 2 e_union_4_state_128 2 *-* All Finished *-* verilator-5.042/test_regress/t/t_disable_fork_notiming.v0000644000542200017500000000040215101701376024124 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; initial disable fork; endmodule verilator-5.042/test_regress/t/t_interface_generic_iface_param.py0000755000542200017500000000077115101701376025736 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--timing']) test.execute() test.passes() verilator-5.042/test_regress/t/t_preproc_strify_join.v0000644000542200017500000000062715101701376023676 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 `define FOO foo `define BAR bar `define QUX qux `define STRIFY `"`FOO``-```BAR``-```QUX```" `define NESTED_STRIFY `"`STRIFY```" `define EMPTY `define EMPTY_STRIFY `"`EMPTY```" `STRIFY `NESTED_STRIFY `EMPTY_STRIFY verilator-5.042/test_regress/t/t_wrapper_legacy.cpp0000644000542200017500000001034415101701376023123 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2020 by Wilson Snyder and Marlon James. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include VM_PREFIX_INCLUDE #include #include #include #include // These require the above. Comment prevents clang-format moving them #include "TestCheck.h" // Empty legacy file (see comments inside it) #include "veriuser.h" int errors = 0; vluint64_t main_time = 0; #ifdef T_WRAPPER_LEGACY #elif defined(T_WRAPPER_LEGACY_TIME64) vluint64_t vl_time_stamp64() { return main_time; } #elif defined(T_WRAPPER_LEGACY_TIMED) double sc_time_stamp() { return main_time; } #endif int main(int argc, char** argv) { // Test that the old non-context Verilated:: calls all work // (This test should never get updated to use context) // Many used only by git@github.com:djg/verilated-rs.git Verilated::commandArgs(argc, argv); // Commonly used TEST_CHECK_CSTR(Verilated::commandArgsPlusMatch("not-matching"), ""); const char* argadd[] = {"+testingPlusAdd+2", nullptr}; Verilated::commandArgsAdd(1, argadd); TEST_CHECK_CSTR(Verilated::commandArgsPlusMatch("testingPlusAdd"), "+testingPlusAdd+2"); Verilated::assertOn(true); TEST_CHECK_EQ(Verilated::assertOn(), true); Verilated::calcUnusedSigs(true); TEST_CHECK_EQ(Verilated::calcUnusedSigs(), true); Verilated::debug(9); // Commonly used TEST_CHECK_EQ(Verilated::debug(), 9); Verilated::debug(0); Verilated::errorLimit(2); TEST_CHECK_EQ(Verilated::errorLimit(), 2); Verilated::fatalOnError(true); TEST_CHECK_EQ(Verilated::fatalOnError(), true); Verilated::fatalOnVpiError(true); TEST_CHECK_EQ(Verilated::fatalOnVpiError(), true); Verilated::gotError(false); TEST_CHECK_EQ(Verilated::gotError(), false); Verilated::gotFinish(false); TEST_CHECK_EQ(Verilated::gotFinish(), false); // Commonly used Verilated::mkdir(VL_STRINGIFY(TEST_OBJ_DIR) "/mkdired"); Verilated::randReset(0); TEST_CHECK_EQ(Verilated::randReset(), 0); Verilated::randSeed(1234); TEST_CHECK_EQ(Verilated::randSeed(), 1234); Verilated::traceEverOn(true); // Commonly used TEST_CHECK_CSTR(Verilated::productName(), Verilated::productName()); TEST_CHECK_CSTR(Verilated::productVersion(), Verilated::productVersion()); TEST_CHECK_EQ(Verilated::timeunit(), 12); TEST_CHECK_EQ(Verilated::timeprecision(), 12); TEST_CHECK_EQ(sizeof(vluint8_t), 1); // Intentional use of old typedef TEST_CHECK_EQ(sizeof(vluint16_t), 2); // Intentional use of old typedef TEST_CHECK_EQ(sizeof(vluint32_t), 4); // Intentional use of old typedef TEST_CHECK_EQ(sizeof(vluint64_t), 8); // Intentional use of old typedef TEST_CHECK_EQ(sizeof(vlsint8_t), 1); // Intentional use of old typedef TEST_CHECK_EQ(sizeof(vlsint16_t), 2); // Intentional use of old typedef TEST_CHECK_EQ(sizeof(vlsint32_t), 4); // Intentional use of old typedef TEST_CHECK_EQ(sizeof(vlsint64_t), 8); // Intentional use of old typedef VM_PREFIX* topp = new VM_PREFIX{}; topp->eval(); topp->clk = 0; VL_PRINTF("Starting\n"); vluint64_t sim_time = 100; while ( #ifdef T_WRAPPER_LEGACY Verilated::time() #else vl_time_stamp64() #endif < sim_time && !Verilated::gotFinish()) { TEST_CHECK_EQ(VL_TIME_Q(), main_time); TEST_CHECK_EQ(VL_TIME_D(), main_time); main_time += 1; #ifdef T_WRAPPER_LEGACY Verilated::timeInc(1); // Check reading and writing of time Verilated::time(Verilated::time()); #endif topp->clk = !topp->clk; topp->eval(); } topp->final(); Verilated::flushCall(); Verilated::runFlushCallbacks(); Verilated::internalsDump(); Verilated::scopesDump(); VL_DO_DANGLING(delete topp, topp); Verilated::runExitCallbacks(); return errors ? 10 : 0; } verilator-5.042/test_regress/t/t_randsequence_recurse.py0000755000542200017500000000105515101701376024174 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) if not test.vlt_all: test.execute() test.passes() verilator-5.042/test_regress/t/t_time_sc_ns.py0000755000542200017500000000121315101701376022106 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_time_sc.v" test.sc_time_resolution = 'SC_NS' test.compile(verilator_flags2=['-sc', '-timescale 1ns/1ns', '+define+TEST_EXPECT=20ns']) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_alias_cyclic_bad.py0000755000542200017500000000076315101701376023221 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_sys_queue_unsup.out0000644000542200017500000002202715101701376023421 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_sys_queue_unsup.v:22:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_initialize' 22 | $q_initialize(1, 1, 3, status); | ^~~~~~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:25:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_initialize' 25 | $q_initialize(2, 2, 2, status); | ^~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:28:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_initialize' 28 | $q_initialize(3, 0, 10, status); | ^~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:31:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_initialize' 31 | $q_initialize(3, 3, 10, status); | ^~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:34:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_initialize' 34 | $q_initialize(3, 1, 0, status); | ^~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:37:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_initialize' 37 | $q_initialize(3, 1, -1, status); | ^~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:40:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_initialize' 40 | $q_initialize(1, 2, 20, status); | ^~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:43:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_add' 43 | $q_add(3, 0, 0, status); | ^~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:46:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_remove' 46 | $q_remove(3, job, value, status); | ^~~~~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:49:11: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_full' 49 | res = $q_full(3, status); | ^~~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:52:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_exam' 52 | $q_exam(3, 1, value, status); | ^~~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:55:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_add' 55 | $q_add(2, 1, 1, status); | ^~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:58:11: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_full' 58 | res = $q_full(2, status); | ^~~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:62:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_add' 62 | $q_add(2, 1, 2, status); | ^~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:65:11: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_full' 65 | res = $q_full(2, status); | ^~~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:69:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_exam' 69 | $q_exam(2, 1, value, status); | ^~~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:72:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_exam' 72 | $q_exam(2, 3, value, status); | ^~~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:75:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_exam' 75 | $q_exam(2, 5, value, status); | ^~~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:79:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_add' 79 | $q_add(2, 1, 3, status); | ^~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:82:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_remove' 82 | $q_remove(2, job, value, status); | ^~~~~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:86:11: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_full' 86 | res = $q_full(2, status); | ^~~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:90:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_remove' 90 | $q_remove(2, job, value, status); | ^~~~~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:95:11: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_full' 95 | res = $q_full(2, status); | ^~~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:99:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_exam' 99 | $q_exam(2, 1, value, status); | ^~~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:102:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_exam' 102 | $q_exam(2, 3, value, status); | ^~~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:105:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_exam' 105 | $q_exam(2, 4, value, status); | ^~~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:109:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_remove' 109 | $q_remove(2, job, value, status); | ^~~~~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:113:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_add' 113 | $q_add(1, 2, 1, status); | ^~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:115:11: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_full' 115 | res = $q_full(1, status); | ^~~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:118:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_add' 118 | $q_add(1, 2, 2, status); | ^~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:120:11: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_full' 120 | res = $q_full(1, status); | ^~~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:123:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_add' 123 | $q_add(1, 2, 3, status); | ^~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:125:11: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_full' 125 | res = $q_full(1, status); | ^~~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:128:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_exam' 128 | $q_exam(1, 1, value, status); | ^~~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:131:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_exam' 131 | $q_exam(1, 3, value, status); | ^~~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:134:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_exam' 134 | $q_exam(1, 5, value, status); | ^~~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:138:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_add' 138 | $q_add(1, 2, 4, status); | ^~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:141:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_remove' 141 | $q_remove(1, job, value, status); | ^~~~~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:146:11: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_full' 146 | res = $q_full(1, status); | ^~~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:150:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_remove' 150 | $q_remove(1, job, value, status); | ^~~~~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:154:11: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_full' 154 | res = $q_full(1, status); | ^~~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:158:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_add' 158 | $q_add(1, 2, 4, status); | ^~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:160:11: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_full' 160 | res = $q_full(1, status); | ^~~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:164:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_remove' 164 | $q_remove(1, job, value, status); | ^~~~~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:168:11: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_full' 168 | res = $q_full(1, status); | ^~~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:171:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_remove' 171 | $q_remove(1, job, value, status); | ^~~~~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:175:11: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_full' 175 | res = $q_full(1, status); | ^~~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:178:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_exam' 178 | $q_exam(1, 1, value, status); | ^~~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:181:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_exam' 181 | $q_exam(1, 3, value, status); | ^~~~~~~ %Error-UNSUPPORTED: t/t_sys_queue_unsup.v:184:5: Unsupported: IEEE 1364-1995 reserved word not implemented: '$q_exam' 184 | $q_exam(1, 4, value, status); | ^~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_lint_defparam_bad.out0000644000542200017500000000074215101701376023560 0ustar mahmoudyfreeshell%Warning-DEFPARAM: t/t_lint_defparam.v:10:19: defparam is deprecated (IEEE 1800-2023 C.4.1) : ... Suggest use instantiation with #(.P(...etc...)) 10 | defparam sub.P = 2; | ^ ... For warning description see https://verilator.org/warn/DEFPARAM?v=latest ... Use "/* verilator lint_off DEFPARAM */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_lint_multidriven_bad.out0000644000542200017500000000202715101701376024341 0ustar mahmoudyfreeshell%Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:21:13: Signal has multiple driving blocks with different clocking: 't.mem' t/t_lint_multidriven_bad.v:24:5: ... Location of first driving block 24 | mem[a0] <= d0; | ^~~ t/t_lint_multidriven_bad.v:27:5: ... Location of other driving block 27 | mem[a0] <= d1; | ^~~ ... For warning description see https://verilator.org/warn/MULTIDRIVEN?v=latest ... Use "/* verilator lint_off MULTIDRIVEN */" and lint_on around source to disable this message. %Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:19:21: Signal has multiple driving blocks with different clocking: 'out2' t/t_lint_multidriven_bad.v:32:5: ... Location of first driving block 32 | out2[7:0] <= d0; | ^~~~ t/t_lint_multidriven_bad.v:35:5: ... Location of other driving block 35 | out2[15:8] <= d0; | ^~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_stack_check.v0000644000542200017500000000047315101701376022046 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_dpi_arg_input_unpack.cpp0000644000542200017500000011231415101701376024304 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2020 by Yutetsu TAKATSUKASA. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include #include #include #include #include // clang-format off #if defined(NCSC) // Used by NC's svdpi.h to pick up svLogicVecVal with _.aval and _.bval fields, // rather than the IEEE 1800-2005 version which has _.a and _.b fields. # define DPI_COMPATIBILITY_VERSION_1800v2012 #endif #include "svdpi.h" #if defined(VERILATOR) // Verilator # include "Vt_dpi_arg_input_unpack__Dpi.h" typedef long long sv_longint_t; typedef unsigned long long sv_longint_unsigned_t; typedef const void** sv_chandle_array_ptr_t; # define NO_SHORTREAL # define NO_UNPACK_STRUCT # define CONSTARG const #elif defined(VCS) // VCS # include "../vc_hdrs.h" typedef long long sv_longint_t; typedef unsigned long long sv_longint_unsigned_t; typedef void** sv_chandle_array_ptr_t; # define NO_TIME # define CONSTARG const #elif defined(NCSC) // NC # include "dpi-exp.h" # include "dpi-imp.h" typedef long long sv_longint_t; typedef unsigned long long sv_longint_unsigned_t; typedef void** sv_chandle_array_ptr_t; # define NO_TIME # define NO_INTEGER # define NO_SHORTREAL // Sadly NC does not declare pass-by reference input arguments as const # define CONSTARG #elif defined(MS) // ModelSim # include "dpi.h" typedef int64_t sv_longint_t; typedef uint64_t sv_longint_unsigned_t; typedef const void** sv_chandle_array_ptr_t; # define CONSTARG const #else # error "Unknown simulator for DPI test" #endif // clang-format on //====================================================================== // Implementations of imported functions //====================================================================== namespace { // unnamed namespace const bool VERBOSE_MESSAGE = false; #define stop() \ do { \ printf(__FILE__ ":%d Bad value\n", __LINE__); \ abort(); \ } while (0) template bool compare(const T& act, const T& exp) { if (exp == act) { if (VERBOSE_MESSAGE) std::cout << "OK Exp:" << exp << " actual:" << act << std::endl; return true; } else { std::cout << "NG Exp:" << exp << " actual:" << act << std::endl; return false; } } bool compare(const svLogicVecVal* v0, sv_longint_unsigned_t val, int bitwidth) { for (int i = 0; i < bitwidth; ++i) { const bool act_bit = svGetBitselLogic(v0, i); const bool exp_bit = (i < 64) ? ((val >> i) & 1) : false; if (act_bit != exp_bit) { std::cout << "Mismatch at bit:" << i << " exp:" << exp_bit << " act:" << act_bit; return false; } } if (VERBOSE_MESSAGE) { std::cout << "OK " << val << " as expected (width:" << bitwidth << ")" << std::endl; } return true; } bool compare(const svBitVecVal* v0, sv_longint_unsigned_t val, int bitwidth) { for (int i = 0; i < bitwidth; ++i) { const bool act_bit = svGetBitselBit(v0, i); const bool exp_bit = (i < 64) ? ((val >> i) & 1) : false; if (act_bit != exp_bit) { std::cout << "Mismatch at bit:" << i << " exp:" << exp_bit << " act:" << act_bit; return false; } } if (VERBOSE_MESSAGE) { std::cout << "OK " << val << " as expected (width:" << bitwidth << ")" << std::endl; } return true; } template bool check_0d(T v) { return compare(v, 42); } template bool check_1d(const T* v) { return compare(v[0], 43) && compare(v[1], 44); } template bool check_2d(const T* v) { return compare(v[0 * 2 + 1], 45) && compare(v[1 * 2 + 1], 46) && compare(v[2 * 2 + 1], 47); } template bool check_3d(const T* v) { return compare(v[(0 * 3 + 0) * 2 + 0], 48) && compare(v[(1 * 3 + 0) * 2 + 0], 49) && compare(v[(2 * 3 + 0) * 2 + 0], 50) && compare(v[(3 * 3 + 0) * 2 + 0], 51); } template bool check_1d1(const T* v) { return compare(v[0], 52); } template bool check_2d1(const T* v) { return compare(v[0], 53); } template bool check_3d1(const T* v) { return compare(v[0], 54); } bool check_0d(const svLogicVecVal* v, int bitwidth) { return compare(v, 42, bitwidth); } bool check_1d(const svLogicVecVal* v, int bitwidth) { const int unit = (bitwidth + 31) / 32; return compare(v + unit * 0, 43, bitwidth) && compare(v + unit * 1, 44, bitwidth); } bool check_2d(const svLogicVecVal* v, int bitwidth) { const int unit = (bitwidth + 31) / 32; return compare(v + unit * (0 * 2 + 1), 45, bitwidth) && compare(v + unit * (1 * 2 + 1), 46, bitwidth) && compare(v + unit * (2 * 2 + 1), 47, bitwidth); } bool check_3d(const svLogicVecVal* v, int bitwidth) { const int unit = (bitwidth + 31) / 32; return compare(v + unit * ((0 * 3 + 0) * 2 + 0), 48, bitwidth) && compare(v + unit * ((1 * 3 + 0) * 2 + 0), 49, bitwidth) && compare(v + unit * ((2 * 3 + 0) * 2 + 0), 50, bitwidth) && compare(v + unit * ((3 * 3 + 0) * 2 + 0), 51, bitwidth); } bool check_1d1(const svLogicVecVal* v, int bitwidth) { return compare(v, 52, bitwidth); } bool check_2d1(const svLogicVecVal* v, int bitwidth) { return compare(v, 53, bitwidth); } bool check_3d1(const svLogicVecVal* v, int bitwidth) { return compare(v, 54, bitwidth); } bool check_0d(const svBitVecVal* v, int bitwidth) { return compare(v, 42, bitwidth); } bool check_1d(const svBitVecVal* v, int bitwidth) { const int unit = (bitwidth + 31) / 32; return compare(v + unit * 0, 43, bitwidth) && compare(v + unit * 1, 44, bitwidth); } bool check_2d(const svBitVecVal* v, int bitwidth) { const int unit = (bitwidth + 31) / 32; return compare(v + unit * (0 * 2 + 1), 45, bitwidth) && compare(v + unit * (1 * 2 + 1), 46, bitwidth) && compare(v + unit * (2 * 2 + 1), 47, bitwidth); } bool check_3d(const svBitVecVal* v, int bitwidth) { const int unit = (bitwidth + 31) / 32; return compare(v + unit * ((0 * 3 + 0) * 2 + 0), 48, bitwidth) && compare(v + unit * ((1 * 3 + 0) * 2 + 0), 49, bitwidth) && compare(v + unit * ((2 * 3 + 0) * 2 + 0), 50, bitwidth) && compare(v + unit * ((3 * 3 + 0) * 2 + 0), 51, bitwidth); } bool check_1d1(const svBitVecVal* v, int bitwidth) { return compare(v, 52, bitwidth); } bool check_2d1(const svBitVecVal* v, int bitwidth) { return compare(v, 53, bitwidth); } bool check_3d1(const svBitVecVal* v, int bitwidth) { return compare(v, 54, bitwidth); } bool check_0d(const char* v) { return compare(v, "42"); } bool check_1d(const char** v) { return compare(v[0], "43") && compare(v[1], "44"); } bool check_2d(const char** v) { return compare(v[0 * 2 + 1], "45") && compare(v[1 * 2 + 1], "46") && compare(v[2 * 2 + 1], "47"); } bool check_3d(const char** v) { return compare(v[(0 * 3 + 0) * 2 + 0], "48") && compare(v[(1 * 3 + 0) * 2 + 0], "49") && compare(v[(2 * 3 + 0) * 2 + 0], "50") && compare(v[(3 * 3 + 0) * 2 + 0], "51"); } bool check_1d1(const char** v) { return compare(v[0], "52"); } bool check_2d1(const char** v) { return compare(v[0], "53"); } bool check_3d1(const char** v) { return compare(v[0], "54"); } template void set_values(T (&v)[4][3][2]) { for (int i = 0; i < 4; ++i) for (int j = 0; j < 3; ++j) for (int k = 0; k < 2; ++k) v[i][j][k] = 0; v[3][2][1] = 42; v[2][1][0] = 43; v[2][1][1] = 44; v[1][0][1] = 45; v[1][1][1] = 46; v[1][2][1] = 47; v[0][0][0] = 48; v[1][0][0] = 49; v[2][0][0] = 50; v[3][0][0] = 51; } void set_uint(svLogicVecVal* v0, sv_longint_unsigned_t val, int bitwidth) { for (int i = 0; i < bitwidth; ++i) { if (i < 64) svPutBitselLogic(v0, i, (val >> i) & 1); else svPutBitselLogic(v0, i, 0); } } void set_uint(svBitVecVal* v0, sv_longint_unsigned_t val, int bitwidth) { for (int i = 0; i < bitwidth; ++i) { if (i < 64) svPutBitselBit(v0, i, (val >> i) & 1); else svPutBitselBit(v0, i, 0); } } template void set_values(svLogicVecVal (&v)[4][3][2][N], int bitwidth) { for (int i = 0; i < 4; ++i) for (int j = 0; j < 3; ++j) for (int k = 0; k < 2; ++k) set_uint(v[i][j][k], 0, bitwidth); set_uint(v[3][2][1], 42, bitwidth); set_uint(v[2][1][0], 43, bitwidth); set_uint(v[2][1][1], 44, bitwidth); set_uint(v[1][0][1], 45, bitwidth); set_uint(v[1][1][1], 46, bitwidth); set_uint(v[1][2][1], 47, bitwidth); set_uint(v[0][0][0], 48, bitwidth); set_uint(v[1][0][0], 49, bitwidth); set_uint(v[2][0][0], 50, bitwidth); set_uint(v[3][0][0], 51, bitwidth); } template void set_values(svBitVecVal (&v)[4][3][2][N], int bitwidth) { for (int i = 0; i < 4; ++i) for (int j = 0; j < 3; ++j) for (int k = 0; k < 2; ++k) set_uint(v[i][j][k], 0, bitwidth); set_uint(v[3][2][1], 42, bitwidth); set_uint(v[2][1][0], 43, bitwidth); set_uint(v[2][1][1], 44, bitwidth); set_uint(v[1][0][1], 45, bitwidth); set_uint(v[1][1][1], 46, bitwidth); set_uint(v[1][2][1], 47, bitwidth); set_uint(v[0][0][0], 48, bitwidth); set_uint(v[1][0][0], 49, bitwidth); set_uint(v[2][0][0], 50, bitwidth); set_uint(v[3][0][0], 51, bitwidth); } sv_chandle_array_ptr_t add_const(void** ptr) { return static_cast(static_cast(ptr)); } } // unnamed namespace void* get_non_null() { static int v; return &v; } void i_byte_0d(char v) { if (!check_0d(v)) stop(); } void i_byte_1d(const char* v) { if (!check_1d(v)) stop(); } void i_byte_2d(const char* v) { if (!check_2d(v)) stop(); } void i_byte_3d(const char* v) { if (!check_3d(v)) stop(); } void i_byte_1d1(const char* v) { if (!check_1d1(v)) stop(); } void i_byte_2d1(const char* v) { if (!check_2d1(v)) stop(); } void i_byte_3d1(const char* v) { if (!check_3d1(v)) stop(); } void i_byte_unsigned_0d(unsigned char v) { if (!check_0d(v)) stop(); } void i_byte_unsigned_1d(const unsigned char* v) { if (!check_1d(v)) stop(); } void i_byte_unsigned_2d(const unsigned char* v) { if (!check_2d(v)) stop(); } void i_byte_unsigned_3d(const unsigned char* v) { if (!check_3d(v)) stop(); } void i_byte_unsigned_1d1(const unsigned char* v) { if (!check_1d1(v)) stop(); } void i_byte_unsigned_2d1(const unsigned char* v) { if (!check_2d1(v)) stop(); } void i_byte_unsigned_3d1(const unsigned char* v) { if (!check_3d1(v)) stop(); } void i_shortint_0d(short v) { if (!check_0d(v)) stop(); } void i_shortint_1d(const short* v) { if (!check_1d(v)) stop(); } void i_shortint_2d(const short* v) { if (!check_2d(v)) stop(); } void i_shortint_3d(const short* v) { if (!check_3d(v)) stop(); } void i_shortint_1d1(const short* v) { if (!check_1d1(v)) stop(); } void i_shortint_2d1(const short* v) { if (!check_2d1(v)) stop(); } void i_shortint_3d1(const short* v) { if (!check_3d1(v)) stop(); } void i_shortint_unsigned_0d(unsigned short v) { if (!check_0d(v)) stop(); } void i_shortint_unsigned_1d(const unsigned short* v) { if (!check_1d(v)) stop(); } void i_shortint_unsigned_2d(const unsigned short* v) { if (!check_2d(v)) stop(); } void i_shortint_unsigned_3d(const unsigned short* v) { if (!check_3d(v)) stop(); } void i_shortint_unsigned_1d1(const unsigned short* v) { if (!check_1d1(v)) stop(); } void i_shortint_unsigned_2d1(const unsigned short* v) { if (!check_2d1(v)) stop(); } void i_shortint_unsigned_3d1(const unsigned short* v) { if (!check_3d1(v)) stop(); } void i_int_0d(int v) { if (!check_0d(v)) stop(); } void i_int_1d(const int* v) { if (!check_1d(v)) stop(); } void i_int_2d(const int* v) { if (!check_2d(v)) stop(); } void i_int_3d(const int* v) { if (!check_3d(v)) stop(); } void i_int_1d1(const int* v) { if (!check_1d1(v)) stop(); } void i_int_2d1(const int* v) { if (!check_2d1(v)) stop(); } void i_int_3d1(const int* v) { if (!check_3d1(v)) stop(); } void i_int_unsigned_0d(unsigned v) { if (!check_0d(v)) stop(); } void i_int_unsigned_1d(const unsigned* v) { if (!check_1d(v)) stop(); } void i_int_unsigned_2d(const unsigned* v) { if (!check_2d(v)) stop(); } void i_int_unsigned_3d(const unsigned* v) { if (!check_3d(v)) stop(); } void i_int_unsigned_1d1(const unsigned* v) { if (!check_1d1(v)) stop(); } void i_int_unsigned_2d1(const unsigned* v) { if (!check_2d1(v)) stop(); } void i_int_unsigned_3d1(const unsigned* v) { if (!check_3d1(v)) stop(); } void i_longint_0d(sv_longint_t v) { if (!check_0d(v)) stop(); } void i_longint_1d(const sv_longint_t* v) { if (!check_1d(v)) stop(); } void i_longint_2d(const sv_longint_t* v) { if (!check_2d(v)) stop(); } void i_longint_3d(const sv_longint_t* v) { if (!check_3d(v)) stop(); } void i_longint_1d1(const sv_longint_t* v) { if (!check_1d1(v)) stop(); } void i_longint_2d1(const sv_longint_t* v) { if (!check_2d1(v)) stop(); } void i_longint_3d1(const sv_longint_t* v) { if (!check_3d1(v)) stop(); } void i_longint_unsigned_0d(sv_longint_unsigned_t v) { if (!check_0d(v)) stop(); } void i_longint_unsigned_1d(const sv_longint_unsigned_t* v) { if (!check_1d(v)) stop(); } void i_longint_unsigned_2d(const sv_longint_unsigned_t* v) { if (!check_2d(v)) stop(); } void i_longint_unsigned_3d(const sv_longint_unsigned_t* v) { if (!check_3d(v)) stop(); } void i_longint_unsigned_1d1(const sv_longint_unsigned_t* v) { if (!check_1d1(v)) stop(); } void i_longint_unsigned_2d1(const sv_longint_unsigned_t* v) { if (!check_2d1(v)) stop(); } void i_longint_unsigned_3d1(const sv_longint_unsigned_t* v) { if (!check_3d1(v)) stop(); } #ifndef NO_TIME void i_time_0d(CONSTARG svLogicVecVal* v) { if (!check_0d(v, 64)) stop(); } void i_time_1d(CONSTARG svLogicVecVal* v) { if (!check_1d(v, 64)) stop(); } void i_time_2d(CONSTARG svLogicVecVal* v) { if (!check_2d(v, 64)) stop(); } void i_time_3d(CONSTARG svLogicVecVal* v) { if (!check_3d(v, 64)) stop(); } void i_time_1d1(CONSTARG svLogicVecVal* v) { if (!check_1d1(v, 64)) stop(); } void i_time_2d1(CONSTARG svLogicVecVal* v) { if (!check_2d1(v, 64)) stop(); } void i_time_3d1(CONSTARG svLogicVecVal* v) { if (!check_3d1(v, 64)) stop(); } #endif #ifndef NO_INTEGER void i_integer_0d(CONSTARG svLogicVecVal* v) { if (!check_0d(v, 32)) stop(); } void i_integer_1d(CONSTARG svLogicVecVal* v) { if (!check_1d(v, 32)) stop(); } void i_integer_2d(CONSTARG svLogicVecVal* v) { if (!check_2d(v, 32)) stop(); } void i_integer_3d(CONSTARG svLogicVecVal* v) { if (!check_3d(v, 32)) stop(); } void i_integer_1d1(CONSTARG svLogicVecVal* v) { if (!check_1d1(v, 32)) stop(); } void i_integer_2d1(CONSTARG svLogicVecVal* v) { if (!check_2d1(v, 32)) stop(); } void i_integer_3d1(CONSTARG svLogicVecVal* v) { if (!check_3d1(v, 32)) stop(); } #endif void i_real_0d(double v) { if (!check_0d(v)) stop(); } void i_real_1d(CONSTARG double* v) { if (!check_1d(v)) stop(); } void i_real_2d(CONSTARG double* v) { if (!check_2d(v)) stop(); } void i_real_3d(CONSTARG double* v) { if (!check_3d(v)) stop(); } void i_real_1d1(CONSTARG double* v) { if (!check_1d1(v)) stop(); } void i_real_2d1(CONSTARG double* v) { if (!check_2d1(v)) stop(); } void i_real_3d1(CONSTARG double* v) { if (!check_3d1(v)) stop(); } #ifndef NO_SHORTREAL void i_shortreal_0d(float v) { if (!check_0d(v)) stop(); } void i_shortreal_1d(CONSTARG float* v) { if (!check_1d(v)) stop(); } void i_shortreal_2d(CONSTARG float* v) { if (!check_2d(v)) stop(); } void i_shortreal_3d(CONSTARG float* v) { if (!check_3d(v)) stop(); } void i_shortreal_1d1(CONSTARG float* v) { if (!check_1d1(v)) stop(); } void i_shortreal_2d1(CONSTARG float* v) { if (!check_2d1(v)) stop(); } void i_shortreal_3d1(CONSTARG float* v) { if (!check_3d1(v)) stop(); } #endif void i_chandle_0d(void* v) { if (!v) stop(); } void i_chandle_1d(sv_chandle_array_ptr_t v) { if (!v[0]) stop(); if (!v[1]) stop(); } void i_chandle_2d(sv_chandle_array_ptr_t v) { if (!v[2 * 0 + 1]) stop(); if (!v[2 * 1 + 1]) stop(); if (!v[2 * 2 + 1]) stop(); } void i_chandle_3d(sv_chandle_array_ptr_t v) { if (!v[(0 * 3 + 0) * 2 + 0]) stop(); if (!v[(1 * 3 + 0) * 2 + 0]) stop(); if (!v[(2 * 3 + 0) * 2 + 0]) stop(); if (!v[(3 * 3 + 0) * 2 + 0]) stop(); } void i_chandle_1d1(sv_chandle_array_ptr_t v) { if (!v[0]) stop(); } void i_chandle_2d1(sv_chandle_array_ptr_t v) { if (!v[0]) stop(); } void i_chandle_3d1(sv_chandle_array_ptr_t v) { if (!v[0]) stop(); } void i_string_0d(CONSTARG char* v) { if (!check_0d(v)) stop(); } void i_string_1d(CONSTARG char** v) { if (!check_1d(v)) stop(); } void i_string_2d(CONSTARG char** v) { if (!check_2d(v)) stop(); } void i_string_3d(CONSTARG char** v) { if (!check_3d(v)) stop(); } void i_string_1d1(CONSTARG char** v) { if (!check_1d1(v)) stop(); } void i_string_2d1(CONSTARG char** v) { if (!check_2d1(v)) stop(); } void i_string_3d1(CONSTARG char** v) { if (!check_3d1(v)) stop(); } void i_bit1_0d(CONSTARG svBit v) { if (!compare(v, sv_0)) stop(); } void i_bit1_1d(CONSTARG svBit* v) { if (!compare(v[0], sv_1)) stop(); if (!compare(v[1], sv_0)) stop(); } void i_bit1_2d(CONSTARG svBit* v) { if (!compare(v[0 * 2 + 1], sv_1)) stop(); if (!compare(v[1 * 2 + 1], sv_0)) stop(); if (!compare(v[2 * 2 + 1], sv_1)) stop(); } void i_bit1_3d(CONSTARG svBit* v) { if (!compare(v[(0 * 3 + 0) * 2 + 0], sv_0)) stop(); if (!compare(v[(1 * 3 + 0) * 2 + 0], sv_1)) stop(); if (!compare(v[(2 * 3 + 0) * 2 + 0], sv_0)) stop(); if (!compare(v[(3 * 3 + 0) * 2 + 0], sv_1)) stop(); } void i_bit1_1d1(CONSTARG svBit* v) { if (!compare(v[0], sv_0)) stop(); } void i_bit1_2d1(CONSTARG svBit* v) { if (!compare(v[0], sv_1)) stop(); } void i_bit1_3d1(CONSTARG svBit* v) { if (!compare(v[0], sv_0)) stop(); } void i_bit7_0d(CONSTARG svBitVecVal* v) { if (!check_0d(v, 7)) stop(); } void i_bit7_1d(CONSTARG svBitVecVal* v) { if (!check_1d(v, 7)) stop(); } void i_bit7_2d(CONSTARG svBitVecVal* v) { if (!check_2d(v, 7)) stop(); } void i_bit7_3d(CONSTARG svBitVecVal* v) { if (!check_3d(v, 7)) stop(); } void i_bit7_1d1(CONSTARG svBitVecVal* v) { if (!check_1d1(v, 7)) stop(); } void i_bit7_2d1(CONSTARG svBitVecVal* v) { if (!check_2d1(v, 7)) stop(); } void i_bit7_3d1(CONSTARG svBitVecVal* v) { if (!check_3d1(v, 7)) stop(); } void i_bit121_0d(CONSTARG svBitVecVal* v) { if (!check_0d(v, 121)) stop(); } void i_bit121_1d(CONSTARG svBitVecVal* v) { if (!check_1d(v, 121)) stop(); } void i_bit121_2d(CONSTARG svBitVecVal* v) { if (!check_2d(v, 121)) stop(); } void i_bit121_3d(CONSTARG svBitVecVal* v) { if (!check_3d(v, 121)) stop(); } void i_bit121_1d1(CONSTARG svBitVecVal* v) { if (!check_1d1(v, 121)) stop(); } void i_bit121_2d1(CONSTARG svBitVecVal* v) { if (!check_2d1(v, 121)) stop(); } void i_bit121_3d1(CONSTARG svBitVecVal* v) { if (!check_3d1(v, 121)) stop(); } void i_logic1_0d(CONSTARG svLogic v) { if (!compare(v, sv_0)) stop(); } void i_logic1_1d(CONSTARG svLogic* v) { if (!compare(v[0], sv_1)) stop(); if (!compare(v[1], sv_0)) stop(); } void i_logic1_2d(CONSTARG svLogic* v) { if (!compare(v[0 * 2 + 1], sv_1)) stop(); if (!compare(v[1 * 2 + 1], sv_0)) stop(); if (!compare(v[2 * 2 + 1], sv_1)) stop(); } void i_logic1_3d(CONSTARG svLogic* v) { if (!compare(v[(0 * 3 + 0) * 2 + 0], sv_0)) stop(); if (!compare(v[(1 * 3 + 0) * 2 + 0], sv_1)) stop(); if (!compare(v[(2 * 3 + 0) * 2 + 0], sv_0)) stop(); if (!compare(v[(3 * 3 + 0) * 2 + 0], sv_1)) stop(); } void i_logic1_1d1(CONSTARG svLogic* v) { if (!compare(v[0], sv_0)) stop(); } void i_logic1_2d1(CONSTARG svLogic* v) { if (!compare(v[0], sv_1)) stop(); } void i_logic1_3d1(CONSTARG svLogic* v) { if (!compare(v[0], sv_0)) stop(); } void i_logic7_0d(CONSTARG svLogicVecVal* v) { if (!check_0d(v, 7)) stop(); } void i_logic7_1d(CONSTARG svLogicVecVal* v) { if (!check_1d(v, 7)) stop(); } void i_logic7_2d(CONSTARG svLogicVecVal* v) { if (!check_2d(v, 7)) stop(); } void i_logic7_3d(CONSTARG svLogicVecVal* v) { if (!check_3d(v, 7)) stop(); } void i_logic7_1d1(CONSTARG svLogicVecVal* v) { if (!check_1d1(v, 7)) stop(); } void i_logic7_2d1(CONSTARG svLogicVecVal* v) { if (!check_2d1(v, 7)) stop(); } void i_logic7_3d1(CONSTARG svLogicVecVal* v) { if (!check_3d1(v, 7)) stop(); } void i_logic121_0d(CONSTARG svLogicVecVal* v) { if (!check_0d(v, 121)) stop(); } void i_logic121_1d(CONSTARG svLogicVecVal* v) { if (!check_1d(v, 121)) stop(); } void i_logic121_2d(CONSTARG svLogicVecVal* v) { if (!check_2d(v, 121)) stop(); } void i_logic121_3d(CONSTARG svLogicVecVal* v) { if (!check_3d(v, 121)) stop(); } void i_logic121_1d1(CONSTARG svLogicVecVal* v) { if (!check_1d1(v, 121)) stop(); } void i_logic121_2d1(CONSTARG svLogicVecVal* v) { if (!check_2d1(v, 121)) stop(); } void i_logic121_3d1(CONSTARG svLogicVecVal* v) { if (!check_3d1(v, 121)) stop(); } void i_pack_struct_0d(CONSTARG svLogicVecVal* v) { if (!check_0d(v, 7)) stop(); } void i_pack_struct_1d(CONSTARG svLogicVecVal* v) { if (!check_1d(v, 7)) stop(); } void i_pack_struct_2d(CONSTARG svLogicVecVal* v) { if (!check_2d(v, 7)) stop(); } void i_pack_struct_3d(CONSTARG svLogicVecVal* v) { if (!check_3d(v, 7)) stop(); } void i_pack_struct_1d1(CONSTARG svLogicVecVal* v) { if (!check_1d1(v, 7)) stop(); } void i_pack_struct_2d1(CONSTARG svLogicVecVal* v) { if (!check_2d1(v, 7)) stop(); } void i_pack_struct_3d1(CONSTARG svLogicVecVal* v) { if (!check_3d1(v, 7)) stop(); } #ifndef NO_UNPACK_STRUCT void i_unpack_struct_0d(CONSTARG unpack_struct_t* v) { if (!compare(v->val, 42, 121)) stop(); } void i_unpack_struct_1d(CONSTARG unpack_struct_t* v) { if (!compare(v[0].val, 43, 121)) stop(); if (!compare(v[1].val, 44, 121)) stop(); } void i_unpack_struct_2d(CONSTARG unpack_struct_t* v) { if (!compare(v[0 * 2 + 1].val, 45, 121)) stop(); if (!compare(v[1 * 2 + 1].val, 46, 121)) stop(); if (!compare(v[2 * 2 + 1].val, 47, 121)) stop(); } void i_unpack_struct_3d(CONSTARG unpack_struct_t* v) { if (!compare(v[(0 * 3 + 0) * 2 + 0].val, 48, 121)) stop(); if (!compare(v[(1 * 3 + 0) * 2 + 0].val, 49, 121)) stop(); if (!compare(v[(2 * 3 + 0) * 2 + 0].val, 50, 121)) stop(); if (!compare(v[(3 * 3 + 0) * 2 + 0].val, 51, 121)) stop(); } void i_unpack_struct_1d1(CONSTARG unpack_struct_t* v) { if (!compare(v[0].val, 52, 121)) stop(); } void i_unpack_struct_2d1(CONSTARG unpack_struct_t* v) { if (!compare(v[0].val, 53, 121)) stop(); } void i_unpack_struct_3d1(CONSTARG unpack_struct_t* v) { if (!compare(v[0].val, 54, 121)) stop(); } #endif void check_exports() { { char byte_array[4][3][2]; set_values(byte_array); e_byte_0d(byte_array[3][2][1]); e_byte_1d(&byte_array[2][1][0]); e_byte_2d(&byte_array[1][0][0]); e_byte_3d(&byte_array[0][0][0]); } { char array[1][1][1]; array[0][0][0] = 52; e_byte_1d1(&array[0][0][0]); array[0][0][0] = 53; e_byte_2d1(&array[0][0][0]); array[0][0][0] = 54; e_byte_3d1(&array[0][0][0]); } { unsigned char byte_unsigned_array[4][3][2]; set_values(byte_unsigned_array); e_byte_unsigned_0d(byte_unsigned_array[3][2][1]); e_byte_unsigned_1d(&byte_unsigned_array[2][1][0]); e_byte_unsigned_2d(&byte_unsigned_array[1][0][0]); e_byte_unsigned_3d(&byte_unsigned_array[0][0][0]); } { unsigned char array[1][1][1]; array[0][0][0] = 52; e_byte_unsigned_1d1(&array[0][0][0]); array[0][0][0] = 53; e_byte_unsigned_2d1(&array[0][0][0]); array[0][0][0] = 54; e_byte_unsigned_3d1(&array[0][0][0]); } { short shortint_array[4][3][2]; set_values(shortint_array); e_shortint_0d(shortint_array[3][2][1]); e_shortint_1d(&shortint_array[2][1][0]); e_shortint_2d(&shortint_array[1][0][0]); e_shortint_3d(&shortint_array[0][0][0]); } { short array[1][1][1]; array[0][0][0] = 52; e_shortint_1d1(&array[0][0][0]); array[0][0][0] = 53; e_shortint_2d1(&array[0][0][0]); array[0][0][0] = 54; e_shortint_3d1(&array[0][0][0]); } { unsigned short shortint_unsigned_array[4][3][2]; set_values(shortint_unsigned_array); e_shortint_unsigned_0d(shortint_unsigned_array[3][2][1]); e_shortint_unsigned_1d(&shortint_unsigned_array[2][1][0]); e_shortint_unsigned_2d(&shortint_unsigned_array[1][0][0]); e_shortint_unsigned_3d(&shortint_unsigned_array[0][0][0]); } { unsigned short array[1][1][1]; array[0][0][0] = 52; e_shortint_unsigned_1d1(&array[0][0][0]); array[0][0][0] = 53; e_shortint_unsigned_2d1(&array[0][0][0]); array[0][0][0] = 54; e_shortint_unsigned_3d1(&array[0][0][0]); } { int int_array[4][3][2]; set_values(int_array); e_int_0d(int_array[3][2][1]); e_int_1d(&int_array[2][1][0]); e_int_2d(&int_array[1][0][0]); e_int_3d(&int_array[0][0][0]); } { int array[1][1][1]; array[0][0][0] = 52; e_int_1d1(&array[0][0][0]); array[0][0][0] = 53; e_int_2d1(&array[0][0][0]); array[0][0][0] = 54; e_int_3d1(&array[0][0][0]); } { unsigned int int_unsigned_array[4][3][2]; set_values(int_unsigned_array); e_int_unsigned_0d(int_unsigned_array[3][2][1]); e_int_unsigned_1d(&int_unsigned_array[2][1][0]); e_int_unsigned_2d(&int_unsigned_array[1][0][0]); e_int_unsigned_3d(&int_unsigned_array[0][0][0]); } { unsigned int array[1][1][1]; array[0][0][0] = 52; e_int_unsigned_1d1(&array[0][0][0]); array[0][0][0] = 53; e_int_unsigned_2d1(&array[0][0][0]); array[0][0][0] = 54; e_int_unsigned_3d1(&array[0][0][0]); } { sv_longint_t longint_array[4][3][2]; set_values(longint_array); e_longint_0d(longint_array[3][2][1]); e_longint_1d(&longint_array[2][1][0]); e_longint_2d(&longint_array[1][0][0]); e_longint_3d(&longint_array[0][0][0]); } { sv_longint_t array[1][1][1]; array[0][0][0] = 52; e_longint_1d1(&array[0][0][0]); array[0][0][0] = 53; e_longint_2d1(&array[0][0][0]); array[0][0][0] = 54; e_longint_3d1(&array[0][0][0]); } { sv_longint_unsigned_t longint_unsigned_array[4][3][2]; set_values(longint_unsigned_array); e_longint_unsigned_0d(longint_unsigned_array[3][2][1]); e_longint_unsigned_1d(&longint_unsigned_array[2][1][0]); e_longint_unsigned_2d(&longint_unsigned_array[1][0][0]); e_longint_unsigned_3d(&longint_unsigned_array[0][0][0]); } { sv_longint_unsigned_t array[1][1][1]; array[0][0][0] = 52; e_longint_unsigned_1d1(&array[0][0][0]); array[0][0][0] = 53; e_longint_unsigned_2d1(&array[0][0][0]); array[0][0][0] = 54; e_longint_unsigned_3d1(&array[0][0][0]); } #ifndef NO_TIME { svLogicVecVal time_array[4][3][2][2]; set_values(time_array, 64); e_time_0d(time_array[3][2][1]); e_time_1d(time_array[2][1][0]); e_time_2d(&time_array[1][0][0][0]); e_time_3d(time_array[0][0][0]); } { svLogicVecVal array[1][1][1][2]; set_uint(array[0][0][0], 52, 64); e_time_1d1(array[0][0][0]); set_uint(array[0][0][0], 53, 64); e_time_2d1(array[0][0][0]); set_uint(array[0][0][0], 54, 64); e_time_3d1(array[0][0][0]); } #endif #ifndef NO_INTEGER { svLogicVecVal integer_array[4][3][2][1]; set_values(integer_array, 32); e_integer_0d(integer_array[3][2][1]); e_integer_1d(integer_array[2][1][0]); e_integer_2d(&integer_array[1][0][0][0]); e_integer_3d(integer_array[0][0][0]); } { svLogicVecVal array[1][1][1][1]; set_uint(array[0][0][0], 52, 32); e_integer_1d1(array[0][0][0]); set_uint(array[0][0][0], 53, 32); e_integer_2d1(array[0][0][0]); set_uint(array[0][0][0], 54, 32); e_integer_3d1(array[0][0][0]); } #endif { double real_array[4][3][2]; set_values(real_array); e_real_0d(real_array[3][2][1]); e_real_1d(&real_array[2][1][0]); e_real_2d(&real_array[1][0][0]); e_real_3d(&real_array[0][0][0]); } { double array[1][1][1]; array[0][0][0] = 52; e_real_1d1(&array[0][0][0]); array[0][0][0] = 53; e_real_2d1(&array[0][0][0]); array[0][0][0] = 54; e_real_3d1(&array[0][0][0]); } #ifndef NO_SHORTREAL { float shortreal_array[4][3][2]; set_values(shortreal_array); e_shortreal_0d(shortreal_array[3][2][1]); e_shortreal_1d(&shortreal_array[2][1][0]); e_shortreal_2d(&shortreal_array[1][0][0]); e_shortreal_3d(&shortreal_array[0][0][0]); } { float array[1][1][1]; array[0][0][0] = 52; e_shortreal_1d1(&array[0][0][0]); array[0][0][0] = 53; e_shortreal_2d1(&array[0][0][0]); array[0][0][0] = 54; e_shortreal_3d1(&array[0][0][0]); } #endif { void* chandle_array[4][3][2]; for (int i = 0; i < 4; ++i) for (int j = 0; j < 3; ++j) for (int k = 0; k < 2; ++k) chandle_array[i][j][k] = NULL; chandle_array[3][2][1] = get_non_null(); chandle_array[2][1][0] = get_non_null(); chandle_array[2][1][1] = get_non_null(); chandle_array[1][0][1] = get_non_null(); chandle_array[1][1][1] = get_non_null(); chandle_array[1][2][1] = get_non_null(); chandle_array[0][0][0] = get_non_null(); chandle_array[1][0][0] = get_non_null(); chandle_array[2][0][0] = get_non_null(); chandle_array[3][0][0] = get_non_null(); e_chandle_0d(chandle_array[3][2][1]); e_chandle_1d(add_const(&chandle_array[2][1][0])); e_chandle_2d(add_const(&chandle_array[1][0][0])); e_chandle_3d(add_const(&chandle_array[0][0][0])); } { void* array[1][1][1]; array[0][0][0] = get_non_null(); e_chandle_1d1(add_const(&array[0][0][0])); array[0][0][0] = get_non_null(); e_chandle_2d1(add_const(&array[0][0][0])); array[0][0][0] = get_non_null(); e_chandle_3d1(add_const(&array[0][0][0])); } { std::vector buf; buf.resize(4 * 3 * 2 * 16, '\0'); buf[((3 * 3 + 2) * 2 + 1) * 16 + 0] = '4'; buf[((3 * 3 + 2) * 2 + 1) * 16 + 1] = '2'; buf[((2 * 3 + 1) * 2 + 0) * 16 + 0] = '4'; buf[((2 * 3 + 1) * 2 + 0) * 16 + 1] = '3'; buf[((2 * 3 + 1) * 2 + 1) * 16 + 0] = '4'; buf[((2 * 3 + 1) * 2 + 1) * 16 + 1] = '4'; buf[((1 * 3 + 0) * 2 + 1) * 16 + 0] = '4'; buf[((1 * 3 + 0) * 2 + 1) * 16 + 1] = '5'; buf[((1 * 3 + 1) * 2 + 1) * 16 + 0] = '4'; buf[((1 * 3 + 1) * 2 + 1) * 16 + 1] = '6'; buf[((1 * 3 + 2) * 2 + 1) * 16 + 0] = '4'; buf[((1 * 3 + 2) * 2 + 1) * 16 + 1] = '7'; buf[((0 * 3 + 0) * 2 + 0) * 16 + 0] = '4'; buf[((0 * 3 + 0) * 2 + 0) * 16 + 1] = '8'; buf[((1 * 3 + 0) * 2 + 0) * 16 + 0] = '4'; buf[((1 * 3 + 0) * 2 + 0) * 16 + 1] = '9'; buf[((2 * 3 + 0) * 2 + 0) * 16 + 0] = '5'; buf[((2 * 3 + 0) * 2 + 0) * 16 + 1] = '0'; buf[((3 * 3 + 0) * 2 + 0) * 16 + 0] = '5'; buf[((3 * 3 + 0) * 2 + 0) * 16 + 1] = '1'; const char* string_array[4][3][2]; for (int i = 0; i < 4; ++i) for (int j = 0; j < 3; ++j) for (int k = 0; k < 2; ++k) string_array[i][j][k] = buf.data() + ((i * 3 + j) * 2 + k) * 16; e_string_0d(string_array[3][2][1]); e_string_1d(&string_array[2][1][0]); e_string_2d(&string_array[1][0][0]); e_string_3d(&string_array[0][0][0]); } { const char* array[1][1][1]; array[0][0][0] = "52"; e_string_1d1(&array[0][0][0]); array[0][0][0] = "53"; e_string_2d1(&array[0][0][0]); array[0][0][0] = "54"; e_string_3d1(&array[0][0][0]); } { svBitVecVal bit7_array[4][3][2][1]; set_values(bit7_array, 7); e_bit7_0d(bit7_array[3][2][1]); e_bit7_1d(bit7_array[2][1][0]); e_bit7_2d(bit7_array[1][0][0]); e_bit7_3d(bit7_array[0][0][0]); } { svBitVecVal array[1][1][1][1]; set_uint(array[0][0][0], 52, 7); e_bit7_1d1(array[0][0][0]); set_uint(array[0][0][0], 53, 7); e_bit7_2d1(array[0][0][0]); set_uint(array[0][0][0], 54, 7); e_bit7_3d1(array[0][0][0]); } { svBitVecVal bit121_array[4][3][2][4]; set_values(bit121_array, 121); e_bit121_0d(bit121_array[3][2][1]); e_bit121_1d(bit121_array[2][1][0]); e_bit121_2d(bit121_array[1][0][0]); e_bit121_3d(bit121_array[0][0][0]); } { svBitVecVal array[1][1][1][4]; set_uint(array[0][0][0], 52, 121); e_bit121_1d1(array[0][0][0]); set_uint(array[0][0][0], 53, 121); e_bit121_2d1(array[0][0][0]); set_uint(array[0][0][0], 54, 121); e_bit121_3d1(array[0][0][0]); } { svLogicVecVal logic7_array[4][3][2][1]; set_values(logic7_array, 7); e_logic7_0d(logic7_array[3][2][1]); e_logic7_1d(logic7_array[2][1][0]); e_logic7_2d(logic7_array[1][0][0]); e_logic7_3d(logic7_array[0][0][0]); } { svLogicVecVal array[1][1][1][1]; set_uint(array[0][0][0], 52, 7); e_logic7_1d1(array[0][0][0]); set_uint(array[0][0][0], 53, 7); e_logic7_2d1(array[0][0][0]); set_uint(array[0][0][0], 54, 7); e_logic7_3d1(array[0][0][0]); } { svLogicVecVal logic121_array[4][3][2][4]; set_values(logic121_array, 121); e_logic121_0d(logic121_array[3][2][1]); e_logic121_1d(logic121_array[2][1][0]); e_logic121_2d(logic121_array[1][0][0]); e_logic121_3d(logic121_array[0][0][0]); } { svLogicVecVal array[1][1][1][4]; set_uint(array[0][0][0], 52, 121); e_logic121_1d1(array[0][0][0]); set_uint(array[0][0][0], 53, 121); e_logic121_2d1(array[0][0][0]); set_uint(array[0][0][0], 54, 121); e_logic121_3d1(array[0][0][0]); } { svLogicVecVal pack_struct_array[4][3][2][1]; set_values(pack_struct_array, 7); e_pack_struct_0d(pack_struct_array[3][2][1]); e_pack_struct_1d(pack_struct_array[2][1][0]); e_pack_struct_2d(pack_struct_array[1][0][0]); e_pack_struct_3d(pack_struct_array[0][0][0]); } { svLogicVecVal array[1][1][1][1]; set_uint(array[0][0][0], 52, 7); e_pack_struct_1d1(array[0][0][0]); set_uint(array[0][0][0], 53, 7); e_pack_struct_2d1(array[0][0][0]); set_uint(array[0][0][0], 54, 7); e_pack_struct_3d1(array[0][0][0]); } #ifndef NO_UNPACK_STRUCT { unpack_struct_t unpack_struct_array[4][3][2]; set_uint(unpack_struct_array[3][2][1].val, 42, 121); set_uint(unpack_struct_array[2][1][0].val, 43, 121); set_uint(unpack_struct_array[2][1][1].val, 44, 121); set_uint(unpack_struct_array[1][0][1].val, 45, 121); set_uint(unpack_struct_array[1][1][1].val, 46, 121); set_uint(unpack_struct_array[1][2][1].val, 47, 121); set_uint(unpack_struct_array[0][0][0].val, 48, 121); set_uint(unpack_struct_array[1][0][0].val, 49, 121); set_uint(unpack_struct_array[2][0][0].val, 50, 121); set_uint(unpack_struct_array[3][0][0].val, 51, 121); e_unpack_struct_0d(&unpack_struct_array[3][2][1]); e_unpack_struct_1d(&unpack_struct_array[2][1][0]); e_unpack_struct_2d(&unpack_struct_array[1][0][0]); e_unpack_struct_3d(&unpack_struct_array[0][0][0]); } { unpack_struct_t unpack_struct_array[1][1][1]; set_uint(unpack_struct_array[0][0][0].val, 52, 121); e_unpack_struct_1d1(&unpack_struct_array[0][0][0]); set_uint(unpack_struct_array[0][0][0].val, 53, 121); e_unpack_struct_2d1(&unpack_struct_array[0][0][0]); set_uint(unpack_struct_array[0][0][0].val, 54, 121); e_unpack_struct_3d1(&unpack_struct_array[0][0][0]); } #endif } verilator-5.042/test_regress/t/t_timing_dpi_unsup.cpp0000644000542200017500000000045115101701376023472 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Toru Niina. // SPDX-License-Identifier: CC0-1.0 #include "Vt_timing_dpi__Dpi.h" int tb_c_wait() { tb_sv_wait(10); return 0; } verilator-5.042/test_regress/t/t_lint_unsup_mixed.py0000755000542200017500000000076015101701376023357 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--lint-only --bbox-unsup"]) test.passes() verilator-5.042/test_regress/t/t_func_no_lifetime_bad.v0000644000542200017500000000233115101701376023712 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 // Not legal to put "static" here, so no warning function int f_dunit_static(); int cnt = 0; // Ok to require "static" here somehday return ++cnt; endfunction // Not legal to put "static" here, so no warning task t_dunit_static(); int cnt = 0; // Ok to require "static" here somehday $display("%d", ++cnt); endtask task t_dunit_static_ok(input int in_ok = 1); static int cnt_ok = 0; // No warning here $display("%d", ++cnt_ok); endtask module t; function int f_implicit_static(); int cnt = 0; return ++cnt; endfunction task t_implicit_static(); int cnt = 0; $display("%d", ++cnt); endtask // verilator lint_off IMPLICITSTATIC function int f_implicit_but_lint_off(); int cnt = 0; return ++cnt; endfunction int a, b; initial begin a = f_dunit_static(); t_dunit_static(); t_dunit_static_ok(); a = f_implicit_static(); t_implicit_static(); b = f_implicit_but_lint_off(); $stop; end endmodule verilator-5.042/test_regress/t/t_process_task.py0000755000542200017500000000076115101701376022472 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_class_typedef.py0000755000542200017500000000073415101701376022617 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_const_func_dpi_bad.out0000644000542200017500000000160215101701376024772 0ustar mahmoudyfreeshell%Error: t/t_lint_const_func_dpi_bad.v:8:32: Constant function may not be DPI import (IEEE 1800-2023 13.4.3) : ... note: In instance 't' 8 | import "DPI-C" function int dpiFunc(); | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_lint_const_func_dpi_bad.v:9:23: Expecting expression to be constant, but can't determine constant for FUNCREF 'dpiFunc' : ... note: In instance 't' t/t_lint_const_func_dpi_bad.v:8:32: ... Location of non-constant FUNC 'dpiFunc': DPI import functions aren't simulatable t/t_lint_const_func_dpi_bad.v:9:23: ... Called from 'dpiFunc()' with parameters: 9 | localparam PARAM = dpiFunc(); | ^~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_trace_timing1.v0000644000542200017500000000143415101701376022330 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" module t; localparam CLOCK_CYCLE = 10; logic rst; logic clk; initial begin $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); $dumpvars; end always #(CLOCK_CYCLE/2) clk = ~clk; always begin rst = 1; clk = 0; $display("[%0t] rst: %d, rst: %d", $time, rst, rst); #CLOCK_CYCLE; rst = 0; $display("[%0t] rst: %d, rst: %d", $time, rst, rst); #CLOCK_CYCLE; $display("[%0t] rst: %d, rst: %d", $time, rst, rst); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_flag_topmodule_bad.py0000755000542200017500000000113615101701376023576 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_flag_topmodule.v" test.lint( fails=True, nc=False, # Need to get it not to give the prompt expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_sys_monitor_dotted.py0000755000542200017500000000077115101701376023723 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--binary']) test.execute() test.passes() verilator-5.042/test_regress/t/t_savable_timing_bad.out0000644000542200017500000000027715101701376023742 0ustar mahmoudyfreeshell%Error: Unsupported: --timing and --savable not supported together ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_past_unsup.v0000644000542200017500000000077715101701376022014 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs d, clk, num ); input d; input clk; input int num; always @ (posedge clk) begin if ($past(d, 1, 1)) $stop; // Unsup if ($past(d, 1, 1, )) $stop; // Unsup if ($past(d, 1, 1, @(posedge clk))) $stop; // Unsup end endmodule verilator-5.042/test_regress/t/t_disable_empty_outside.py0000755000542200017500000000101315101701376024336 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(timing_loop=True, verilator_flags2=["--timing"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_force_mid.py0000755000542200017500000000106015101701376021712 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_alias_hier_ref_bad.py0000755000542200017500000000076315101701376023536 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_func_call_super_arg.py0000755000542200017500000000073415101701376023767 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_langext_1d_bad.py0000755000542200017500000000116415101701376022624 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.top_filename = "t/t_langext_1.v" test.leak_check_disable() # This is a lint only test. test.lint(v_flags2=["+verilog1995ext+.v"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_latch_1.py0000755000542200017500000000070315101701376022327 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint() test.passes() verilator-5.042/test_regress/t/t_fork_join_none_any_nested.v0000644000542200017500000000174615101701376025020 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 event evt1, evt2, evt3; class Foo; task do_something(int cap1, int cap2); fork begin $display("outer fork: %d", cap1); fork $display("inner fork: %d", cap2); ->evt2; fork $display("innermost fork: %d", cap2); ->evt3; join_none join_none end ->evt1; join_any endtask endclass module t(); reg a, b, c; initial begin Foo foo; a = 1'b0; b = 1'b0; foo = new; foo.do_something(1, 2); end always @(evt1) begin a <= 1; end always @(evt2) begin b <= 1; end always @(evt3) begin c <= 1; end always @(a, b, c) begin if (a & b & c) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_extract_static_const_no_merge.py0000755000542200017500000000153115101701376026070 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_extract_static_const.v" test.golden_filename = "t/t_extract_static_const.out" test.compile(verilator_flags2=["--stats", "--fno-merge-const-pool"]) test.execute(expect_filename=test.golden_filename) if test.vlt_all: test.file_grep(test.stats, r'Optimizations, Prelim extracted value to ConstPool\s+(\d+)', 8) test.file_grep(test.stats, r'ConstPool, Constants emitted\s+(\d+)', 1) test.passes() verilator-5.042/test_regress/t/t_interface_generic_modport2.v0000644000542200017500000000105615101701376025064 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 interface inf; int v; modport mp ( output v ); endinterface module GenericModule (interface.mp a); initial begin a.v = 7; end endmodule module t; inf inf_inst(); GenericModule genericModule (inf_inst); initial begin #1; if (inf_inst.v != 7) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_stream_unpack_wider.v0000644000542200017500000000343615101701376023634 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t; initial begin logic [7:0] src_1 = 8'b1010_0011; // 8 bits wide source logic [1:0] dst_1 [3]; // 6 bits wide target logic [1:0] exp_1 [3]; // 6 bits wide target logic [1:0] src_2 [3] = '{2'b10, 2'b10, 2'b10}; // 6 bits wide source logic [7:0] dst_2; // 8 bits wide target logic [7:0] exp_2; // 8 bits wide target string expv; string gotv; // unpack as target, StreamR {>>{dst_1}} = src_1; exp_1 = '{2'b10, 2'b10, 2'b00}; expv = $sformatf("%p", exp_1); gotv = $sformatf("%p", dst_1); `checks(gotv, expv); // unpack as target, StreamL {<<{dst_1}} = src_1; exp_1 = '{2'b00, 2'b01, 2'b01}; expv = $sformatf("%p", exp_1); gotv = $sformatf("%p", dst_1); `checks(gotv, expv); // unpack as source, StreamR dst_2 = {>>{src_2}}; exp_2 = 8'b10101000; expv = $sformatf("%p", exp_2); gotv = $sformatf("%p", dst_2); `checks(gotv, expv); // unpack as source, StreamL dst_2 = {<<{src_2}}; exp_2 = 8'b01010100; expv = $sformatf("%p", exp_2); gotv = $sformatf("%p", dst_2); `checks(gotv, expv); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_func_impure_bad.py0000755000542200017500000000076315101701376023116 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_math_wide_inc.v0000644000542200017500000000506615101701376022401 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2023 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer i; reg [6:0] w7; reg [14:0] w15; reg [30:0] w31; reg [62:0] w63; reg [94:0] w95; integer cyc = 0; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d\n", $time, cyc); `endif cyc <= cyc + 1; if (cyc==0) begin // Setup w7 = {7{1'b1}}; w15 = {15{1'b1}}; w31 = {31{1'b1}}; w63 = {63{1'b1}}; w95 = {95{1'b1}}; end else if (cyc == 1) begin if (w7++ != {7{1'b1}}) $stop; if (w7 != {7{1'b0}}) $stop; if (w7-- != {7{1'b0}}) $stop; if (w7 != {7{1'b1}}) $stop; if (++w7 != {7{1'b0}}) $stop; if (w7 != {7{1'b0}}) $stop; if (--w7 != {7{1'b1}}) $stop; if (w7 != {7{1'b1}}) $stop; if (w15++ != {15{1'b1}}) $stop; if (w15 != {15{1'b0}}) $stop; if (w15-- != {15{1'b0}}) $stop; if (w15 != {15{1'b1}}) $stop; if (++w15 != {15{1'b0}}) $stop; if (w15 != {15{1'b0}}) $stop; if (--w15 != {15{1'b1}}) $stop; if (w15 != {15{1'b1}}) $stop; if (w31++ != {31{1'b1}}) $stop; if (w31 != {31{1'b0}}) $stop; if (w31-- != {31{1'b0}}) $stop; if (w31 != {31{1'b1}}) $stop; if (++w31 != {31{1'b0}}) $stop; if (w31 != {31{1'b0}}) $stop; if (--w31 != {31{1'b1}}) $stop; if (w31 != {31{1'b1}}) $stop; if (w63++ != {63{1'b1}}) $stop; if (w63 != {63{1'b0}}) $stop; if (w63-- != {63{1'b0}}) $stop; if (w63 != {63{1'b1}}) $stop; if (++w63 != {63{1'b0}}) $stop; if (w63 != {63{1'b0}}) $stop; if (--w63 != {63{1'b1}}) $stop; if (w63 != {63{1'b1}}) $stop; if (w95++ != {95{1'b1}}) $stop; if (w95 != {95{1'b0}}) $stop; if (w95-- != {95{1'b0}}) $stop; if (w95 != {95{1'b1}}) $stop; if (++w95 != {95{1'b0}}) $stop; if (w95 != {95{1'b0}}) $stop; if (--w95 != {95{1'b1}}) $stop; if (w95 != {95{1'b1}}) $stop; end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_timing_fork_taskcall.v0000644000542200017500000000072715101701376023774 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; task foo; #1 if ($time != 1) $stop; #1 if ($time != 2) $stop; #1 if ($time != 3) $stop; endtask initial fork foo; foo; foo; #4 begin $write("*-* All Finished *-*\n"); $finish; end join endmodule verilator-5.042/test_regress/t/t_func_defaults.py0000755000542200017500000000073415101701376022614 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_json_only_first.out0000644000542200017500000003661415101701376023375 0ustar mahmoudyfreeshell{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"UNLINKED", "modulesp": [ {"type":"MODULE","name":"t","addr":"(E)","loc":"d,7:8,7:9","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"t","level":2,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"q","addr":"(F)","loc":"d,15:22,15:23","dtypep":"(G)","origName":"q","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"clk","addr":"(H)","loc":"d,13:10,13:13","dtypep":"(I)","origName":"clk","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"d","addr":"(J)","loc":"d,14:16,14:17","dtypep":"(G)","origName":"d","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"between","addr":"(K)","loc":"d,17:22,17:29","dtypep":"(G)","origName":"between","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"CELL","name":"cell1","addr":"(L)","loc":"d,20:4,20:9","origName":"cell1","recursive":false,"modp":"(M)", "pinsp": [ {"type":"PIN","name":"q","addr":"(N)","loc":"d,20:12,20:13","svDotName":true,"svImplicit":false,"modVarp":"(O)","modPTypep":"UNLINKED", "exprp": [ {"type":"VARREF","name":"between","addr":"(P)","loc":"d,20:14,20:21","dtypep":"(G)","access":"WR","varp":"(K)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]}, {"type":"PIN","name":"clk","addr":"(Q)","loc":"d,21:12,21:15","svDotName":true,"svImplicit":false,"modVarp":"(R)","modPTypep":"UNLINKED", "exprp": [ {"type":"VARREF","name":"clk","addr":"(S)","loc":"d,21:42,21:45","dtypep":"(I)","access":"RD","varp":"(H)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]}, {"type":"PIN","name":"d","addr":"(T)","loc":"d,22:12,22:13","svDotName":true,"svImplicit":false,"modVarp":"(U)","modPTypep":"UNLINKED", "exprp": [ {"type":"VARREF","name":"d","addr":"(V)","loc":"d,22:42,22:43","dtypep":"(G)","access":"RD","varp":"(J)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ],"paramsp": [],"rangep": [],"intfRefsp": []}, {"type":"CELL","name":"cell2","addr":"(W)","loc":"d,25:6,25:11","origName":"cell2","recursive":false,"modp":"(X)", "pinsp": [ {"type":"PIN","name":"d","addr":"(Y)","loc":"d,25:14,25:15","svDotName":true,"svImplicit":false,"modVarp":"(Z)","modPTypep":"UNLINKED", "exprp": [ {"type":"VARREF","name":"between","addr":"(AB)","loc":"d,25:16,25:23","dtypep":"(G)","access":"RD","varp":"(K)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]}, {"type":"PIN","name":"q","addr":"(BB)","loc":"d,26:14,26:15","svDotName":true,"svImplicit":false,"modVarp":"(CB)","modPTypep":"UNLINKED", "exprp": [ {"type":"VARREF","name":"q","addr":"(DB)","loc":"d,26:42,26:43","dtypep":"(G)","access":"WR","varp":"(F)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]}, {"type":"PIN","name":"clk","addr":"(EB)","loc":"d,27:14,27:17","svDotName":true,"svImplicit":false,"modVarp":"(FB)","modPTypep":"UNLINKED", "exprp": [ {"type":"VARREF","name":"clk","addr":"(GB)","loc":"d,27:42,27:45","dtypep":"(I)","access":"RD","varp":"(H)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ],"paramsp": [],"rangep": [],"intfRefsp": []} ]}, {"type":"MODULE","name":"mod2","addr":"(X)","loc":"d,46:8,46:12","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"mod2","level":3,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"clk","addr":"(FB)","loc":"d,48:10,48:13","dtypep":"(I)","origName":"clk","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"d","addr":"(Z)","loc":"d,49:16,49:17","dtypep":"(G)","origName":"d","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"q","addr":"(CB)","loc":"d,50:22,50:23","dtypep":"(G)","origName":"q","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"ALWAYS","name":"","addr":"(HB)","loc":"d,53:13,53:14","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(IB)","loc":"d,53:13,53:14","dtypep":"(G)", "rhsp": [ {"type":"VARREF","name":"d","addr":"(JB)","loc":"d,49:16,49:17","dtypep":"(G)","access":"RD","varp":"(Z)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "lhsp": [ {"type":"VARREF","name":"q","addr":"(KB)","loc":"d,53:13,53:14","dtypep":"(G)","access":"WR","varp":"(CB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": [],"strengthSpecp": []} ]} ]}, {"type":"MODULE","name":"mod1__W4","addr":"(M)","loc":"d,31:8,31:12","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"mod1","level":3,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"WIDTH","addr":"(LB)","loc":"d,32:15,32:20","dtypep":"(MB)","origName":"WIDTH","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"GPARAM","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":true,"isParam":true,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [], "valuep": [ {"type":"CONST","name":"32'sh4","addr":"(NB)","loc":"d,19:18,19:19","dtypep":"(MB)"} ],"attrsp": []}, {"type":"VAR","name":"clk","addr":"(R)","loc":"d,34:24,34:27","dtypep":"(I)","origName":"clk","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"d","addr":"(U)","loc":"d,35:30,35:31","dtypep":"(G)","origName":"d","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"q","addr":"(O)","loc":"d,36:30,36:31","dtypep":"(G)","origName":"q","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"IGNORED","addr":"(OB)","loc":"d,39:15,39:22","dtypep":"(MB)","origName":"IGNORED","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"LPARAM","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":true,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [], "valuep": [ {"type":"CONST","name":"32'sh1","addr":"(PB)","loc":"d,39:25,39:26","dtypep":"(MB)"} ],"attrsp": []}, {"type":"ALWAYS","name":"","addr":"(QB)","loc":"d,41:4,41:10","keyword":"always","isSuspendable":false,"needProcess":false, "sentreep": [ {"type":"SENTREE","name":"","addr":"(RB)","loc":"d,41:11,41:12","isMulti":false, "sensesp": [ {"type":"SENITEM","name":"","addr":"(SB)","loc":"d,41:13,41:20","edgeType":"POS", "sensp": [ {"type":"VARREF","name":"clk","addr":"(TB)","loc":"d,41:21,41:24","dtypep":"(I)","access":"RD","varp":"(R)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"condp": []} ]} ], "stmtsp": [ {"type":"ASSIGNDLY","name":"","addr":"(UB)","loc":"d,42:8,42:10","dtypep":"(G)", "rhsp": [ {"type":"VARREF","name":"d","addr":"(VB)","loc":"d,42:11,42:12","dtypep":"(G)","access":"RD","varp":"(U)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "lhsp": [ {"type":"VARREF","name":"q","addr":"(WB)","loc":"d,42:6,42:7","dtypep":"(G)","access":"WR","varp":"(O)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": []} ]} ]} ],"filesp": [], "miscsp": [ {"type":"TYPETABLE","name":"","addr":"(C)","loc":"a,0:0,0:0","constraintRefp":"UNLINKED","emptyQueuep":"UNLINKED","queueIndexp":"UNLINKED","streamp":"UNLINKED","voidp":"(XB)", "typesp": [ {"type":"BASICDTYPE","name":"logic","addr":"(I)","loc":"d,34:24,34:27","dtypep":"(I)","keyword":"logic","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(G)","loc":"d,15:16,15:17","dtypep":"(G)","keyword":"logic","range":"3:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(MB)","loc":"d,19:18,19:19","dtypep":"(MB)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, {"type":"VOIDDTYPE","name":"","addr":"(XB)","loc":"a,0:0,0:0","dtypep":"(XB)","generic":false} ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ {"type":"MODULE","name":"@CONST-POOL@","addr":"(YB)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], "stmtsp": [ {"type":"SCOPE","name":"@CONST-POOL@","addr":"(ZB)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(YB)","varsp": [],"blocksp": [],"inlinesp": []} ]} ]} ]} verilator-5.042/test_regress/t/t_case_overlap_bad.v0000644000542200017500000000170615101701376023055 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: SystemVerilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Anthony Donlon. // SPDX-License-Identifier: CC0-1.0 module t; t1 i_t1(); endmodule module t1; int v = 0; logic [2:0] state; initial begin state = 2; casez (state) 3'b11?, 3'b???: v++; default; endcase casez (state) 3'b00?: $stop; 3'b001, 3'b000: $stop; default; endcase casez (state) 3'b111, 3'b0??: v++; 3'b11?: $stop; default; endcase casez (state) 3'b000, 3'b001, 3'b010, 3'b011: v++; 3'b001: $stop; default; endcase casez (state) 3'b000, 3'b001, 3'b010, 3'b011: v++; 3'b011: $stop; default; endcase end endmodule verilator-5.042/test_regress/t/t_checker_unsup.v0000644000542200017500000000311215101701376022433 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d\n", $time, cyc); `endif cyc <= cyc + 1; if (cyc == 0) begin end else if (cyc == 99) begin $write("*-* All Finished *-*\n"); $finish; end end Chk check(clk, cyc); checker checker_in_module; endchecker endmodule package Pkg; checker checker_in_pkg; endchecker endpackage checker Chk(input defaulted = 1'b0); bit clk; bit in; bit rst; rand bit randed; // TODO test this int counter = 0; int ival; final if (ival != 1234) $stop; genvar g; if (0) begin initial ival = 1; end else begin initial ival = 1234; end int ival2; case (1) 0: initial ival2 = 0; default: initial ival2 = 12345; endcase final if (ival2 != 12345) $stop; default clocking clk; // TODO test this default disable iff rst; // TODO test this checker ChkChk; // TODO flag unsupported endchecker function automatic int f; // TODO test this endfunction clocking cb1 @(posedge clk); // TODO test this input in; output out; endclocking always_ff @(posedge clk) counter <= counter + 1'b1; a1: assert property (@(posedge clk) counter == in); endchecker verilator-5.042/test_regress/t/t_dist_copyright.py0000755000542200017500000001001615101701376023017 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap import datetime test.scenarios('dist') RELEASE_OK_RE = r'(^test_regress/t/.*\.(cpp|h|map|mk|sv|v|vlt)|^test_regress/t_done/|^examples/)' EXEMPT_AUTHOR_RE = r'(^ci/|^nodist/fastcov.py|^nodist/fuzzer|^test_regress/t/.*\.(cpp|h|v|vlt)$)' EXEMPT_FILES_RE = r'(^\.|/\.|\.gitignore$|\.dat|\.gprof|\.mem|\.out$|\.png$|\.tree|\.vc$|\.vcd$|^\.)' EXEMPT_FILES_LIST = """ Artistic CITATION.cff CPPLINT.cfg LICENSE README.rst ci/ci-win-compile.ps1 ci/ci-win-test.ps1 ci/codecov docs/CONTRIBUTING.rst docs/CONTRIBUTORS docs/README.rst docs/security.rst docs/_static docs/gen docs/spelling.txt docs/verilated.dox include/gtkwave include/vltstd install-sh src/mkinstalldirs test_regress/t/t_altera_lpm.v test_regress/t/t_flag_f__3.v test_regress/t/t_fuzz_eof_bad.v test_regress/t/t_incr_void.v test_regress/t/t_property_unsup.v test_regress/t/t_sequence_first_match_unsup.v test_regress/t/tsub/t_flag_f_tsub.v test_regress/t/tsub/t_flag_f_tsub_inc.v test_regress/t/uvm/ verilator.pc.in """ Exempt_Files_List_Re = list(map(re.escape, EXEMPT_FILES_LIST.split())) Exempt_Files_List_Re = '^(' + '|'.join(Exempt_Files_List_Re) + ")" # pprint(Exempt_Files_List_Re) if not os.path.exists(test.root + "/.git"): test.skip("Not in a git repository") cmd = "cd " + test.root + " && git ls-files --exclude-standard" out = test.run_capture(cmd) year = datetime.datetime.now().year files = {} out = re.sub(r'\s+', ' ', out) for filename in out.split(): if re.search(EXEMPT_FILES_RE, filename): continue if re.search(Exempt_Files_List_Re, filename): continue files[filename] = True for filename in files: open_filename = os.path.join(test.root, filename) if not os.path.exists(open_filename): continue with open(open_filename, 'r', encoding="utf8") as fh: spdx = None copyright_msg = None release = False for line in fh: line = line.rstrip() if 'SPDX-License-Identifier:' in line: spdx = line elif re.search(r'Copyright 20[0-9][0-9]', line): copyright_msg = line if 'Wilson Snyder' in line: pass elif re.search(r'\.pl$', filename): pass elif re.search(EXEMPT_AUTHOR_RE, filename): pass else: if "test_regress/t" in filename: yeardash = str(year) else: yeardash = str(year) + '-' + str(year) print(" " + copyright_msg) test.error_keep_going(filename + ": Please use standard 'Copyright " + yeardash + " by Wilson Snyder'") elif (('Creative Commons Public Domain' in line) or ('freely copied and/or distributed' in line) or ('placed into the Public Domain' in line)): release = True release_note = "" if not re.search(RELEASE_OK_RE, filename): release_note = " (has copyright release, but not part of " + RELEASE_OK_RE + ")" if not copyright_msg and (not release or release_note): test.error_keep_going(filename + ": Please add standard 'Copyright " + str(year) + " ...', similar to in other files" + release_note) if not spdx: test.error_keep_going( filename + ": Please add standard 'SPDX-License_Identifier: ...', similar to in other files") test.passes() verilator-5.042/test_regress/t/t_interface_modport_import.v0000644000542200017500000000176215101701376024704 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // A test of the import parameter used with modport // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 interface test_if; // Interface variable logic data; // Modport modport mp( import myfunc, output data ); function automatic logic myfunc (input logic val); begin myfunc = (val == 1'b0); end endfunction endinterface // test_if module t (/*AUTOARG*/ // Inputs clk ); input clk; test_if i (); testmod testmod_i (.clk (clk), .i (i.mp)); endmodule module testmod ( input clk, test_if.mp i ); always @(posedge clk) begin i.data = 1'b0; if (i.myfunc (1'b0)) begin $write("*-* All Finished *-*\n"); $finish; end else begin $stop; end end endmodule verilator-5.042/test_regress/t/t_array_mda.py0000755000542200017500000000073415101701376021731 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_assigndly_dynamic_notiming_bad.v0000644000542200017500000000062615101701376026017 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class Cls; task bar; static int qux; qux <= '1; endtask endclass module t; initial begin Cls c; c.bar(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_class_param_func_return.v0000644000542200017500000000175315101701376024505 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class Foo #(type T=int); typedef Foo default_type; typedef Foo#(T) this_type; T x; function default_type get_default(); default_type o = new; return o; endfunction function this_type get_this(); this_type o = new; return o; endfunction endclass module t; Foo f_def1, f_def2; Foo#(bit) f_bit1, f_bit2; initial begin f_def1 = new; f_bit1 = new; f_def2 = f_def1.get_default(); if ($bits(f_def2.x) != 32) $stop; f_def2 = f_def1.get_this(); if ($bits(f_def2.x) != 32) $stop; f_def2 = f_bit1.get_default(); if ($bits(f_def2.x) != 32) $stop; f_bit2 = f_bit1.get_this(); if ($bits(f_bit2.x) != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_sys_fstrobe.py0000755000542200017500000000110015101701376022320 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') # Not vltmt due to possible race test.compile() test.execute() test.files_identical(test.obj_dir + "/open.log", test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dfg_break_cycles.cpp0000644000542200017500000000246215101701376023367 0ustar mahmoudyfreeshell// // DESCRIPTION: Verilator: DFG optimizer equivalence testing // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 // #include #include #include #include #include void rngUpdate(uint64_t& x) { x ^= x << 13; x ^= x >> 7; x ^= x << 17; } int main(int, char**) { // Create contexts VerilatedContext ctx; // Create models Vref ref{&ctx}; Vopt opt{&ctx}; uint64_t rand_a = 0x5aef0c8dd70a4497; uint64_t rand_b = 0xf0c0a8dd75ae4497; uint64_t srand_a = 0x00fa8dcc7ae4957; uint64_t srand_b = 0x0fa8dc7ae3c9574; for (size_t n = 0; n < 200000; ++n) { // Update rngs rngUpdate(rand_a); rngUpdate(rand_b); rngUpdate(srand_a); rngUpdate(srand_b); // Assign inputs ref.rand_a = opt.rand_a = rand_a; ref.rand_b = opt.rand_b = rand_b; ref.srand_a = opt.srand_a = srand_a; ref.srand_b = opt.srand_b = srand_b; // Evaluate both models ref.eval(); opt.eval(); // Check equivalence #include "checks.h" // increment time ctx.timeInc(1); } std::cout << "*-* All Finished *-*\n"; } verilator-5.042/test_regress/t/t_config_work.py0000755000542200017500000000135015101701376022274 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=[ '--binary', '--work liba', 't/t_config_work__liba.v', '--work libb', 't/t_config_work__libb.v' ]) test.execute() # Sort so that 'initial' scheduling order is not relevant test.files_identical_sorted(test.run_log_filename, test.golden_filename, is_logfile=True) test.passes() verilator-5.042/test_regress/t/t_class_ref_as_arg_cast.py0000755000542200017500000000071415101701376024257 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.passes() verilator-5.042/test_regress/t/t_vpi_zero_time_cb.cpp0000644000542200017500000001077015101701376023441 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #ifdef IS_VPI #include "vpi_user.h" #else #include "verilated.h" #include "verilated_vcd_c.h" #include "verilated_vpi.h" #include "Vt_vpi_zero_time_cb.h" #include "Vt_vpi_zero_time_cb__Dpi.h" #include "svdpi.h" #include #endif #include #include #include #include extern "C" { #include } // These require the above. Comment prevents clang-format moving them #include "TestCheck.h" #include "TestSimulator.h" #include "TestVpi.h" int errors = 0; unsigned int callback_count_zero_time = 0; unsigned int callback_count_start_of_sim = 0; //====================================================================== #ifdef IS_VPI static int _zero_time_cb(p_cb_data cb_data) { callback_count_zero_time++; return 0; } static int _start_of_sim_cb(p_cb_data cb_data) { #ifdef TEST_VERBOSE printf("-_start_of_sim_cb\n"); #endif t_cb_data cb_data_n; bzero(&cb_data_n, sizeof(cb_data_n)); s_vpi_time t; cb_data_n.reason = cbAfterDelay; t.type = vpiSimTime; t.high = 0; t.low = 0; cb_data_n.time = &t; cb_data_n.cb_rtn = _zero_time_cb; TestVpiHandle _cb_data_n_h = vpi_register_cb(&cb_data_n); callback_count_start_of_sim++; return 0; } static int _end_of_sim_cb(p_cb_data cb_data) { TEST_CHECK_EQ(callback_count_start_of_sim, 1); TEST_CHECK_EQ(callback_count_zero_time, 1); if (!errors) fprintf(stdout, "*-* All Finished *-*\n"); return 0; } // cver entry #ifdef __cplusplus extern "C" #endif // clang-format off void vpi_compat_bootstrap(void) { // clang-format on t_cb_data cb_data; bzero(&cb_data, sizeof(cb_data)); // VL_PRINTF("register start-of-sim callback\n"); cb_data.reason = cbStartOfSimulation; cb_data.time = 0; cb_data.cb_rtn = _start_of_sim_cb; TestVpiHandle _start_of_sim_cb_h = vpi_register_cb(&cb_data); cb_data.reason = cbEndOfSimulation; cb_data.time = 0; cb_data.cb_rtn = _end_of_sim_cb; TestVpiHandle _end_of_sim_cb_h = vpi_register_cb(&cb_data); } // icarus entry void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0}; #else int main(int argc, char** argv) { const std::unique_ptr contextp{new VerilatedContext}; uint64_t sim_time = 1100; contextp->debug(0); contextp->commandArgs(argc, argv); const std::unique_ptr topp{new VM_PREFIX{contextp.get(), // Note null name - we're flattening it out ""}}; // clang-format off #ifdef VERILATOR # ifdef TEST_VERBOSE contextp->scopesDump(); # endif #endif // clang-format on #if VM_TRACE contextp->traceEverOn(true); VL_PRINTF("Enabling waves...\n"); VerilatedVcdC* tfp = new VerilatedVcdC; topp->trace(tfp, 99); tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); #endif // Load and initialize the PLI application { const char* filenamep = VL_STRINGIFY(TEST_OBJ_DIR) "/libvpi.so"; void* lib = dlopen(filenamep, RTLD_LAZY); void* bootstrap = dlsym(lib, "vpi_compat_bootstrap"); if (!bootstrap) { const std::string msg = "%Error: Could not dlopen "s + filenamep; vl_fatal(__FILE__, __LINE__, "main", msg.c_str()); } ((void (*)(void))bootstrap)(); } VerilatedVpi::callCbs(cbStartOfSimulation); topp->eval(); topp->clk = 0; contextp->timeInc(1); while (contextp->time() < sim_time && !contextp->gotFinish()) { contextp->timeInc(1); topp->eval(); VerilatedVpi::callValueCbs(); VerilatedVpi::callTimedCbs(); topp->clk = !topp->clk; // mon_do(); #if VM_TRACE if (tfp) tfp->dump(contextp->time()); #endif } VerilatedVpi::callCbs(cbEndOfSimulation); if (!contextp->gotFinish()) { vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); } topp->final(); #if VM_TRACE if (tfp) tfp->close(); #endif return 0; } #endif verilator-5.042/test_regress/t/t_tri_gate.cpp0000644000542200017500000000253015101701376021713 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2008 by Lane Brooks. // SPDX-License-Identifier: CC0-1.0 #include VM_PREFIX_INCLUDE VM_PREFIX* tb = nullptr; bool check() { bool pass; int c = (tb->A >> tb->SEL) & 0x1; #ifdef TEST_VERBOSE bool verbose = true; #else bool verbose = false; #endif if (tb->W == c && tb->X == c && tb->Y == c && tb->Z == c) { pass = true; if (verbose) printf("- pass: "); } else { pass = false; verbose = true; printf("%%E-FAIL: "); } if (verbose) { printf("SEL=%d A=%d got: W=%d X=%d Y=%d Z=%d exp: WXYZ=%d\n", tb->SEL, tb->A, tb->W, tb->X, tb->Y, tb->Z, c); } return pass; } int main() { Verilated::debug(0); tb = new VM_PREFIX{"tb"}; // loop through every possibility and check the result bool pass = true; for (tb->SEL = 0; tb->SEL < 2; tb->SEL++) { for (tb->A = 0; tb->A < 4; tb->A++) { tb->eval(); if (!check()) pass = false; } } if (pass) { VL_PRINTF("*-* All Finished *-*\n"); tb->final(); } else { vl_fatal(__FILE__, __LINE__, "top", "Unexpected results from tristate test\n"); } VL_DO_DANGLING(delete tb, tb); return 0; } verilator-5.042/test_regress/t/t_xml_begin_hier.py0000755000542200017500000000133615101701376022744 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') out_filename = test.obj_dir + "/V" + test.name + ".xml" test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only'], verilator_make_gmake=False, make_top_shell=False, make_main=False) test.files_identical(out_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_inc_relink.v0000644000542200017500000000140115101701376021711 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 // Test if temporary vars are relinked if not used directly under FTASK. package A; // Create JUMPBLOCK; use n++ in it task t; automatic int n; if ($random) return; n = n++; endtask endpackage package B; // Create IF; use n++ in it int n; task t; if ($random) n = n++; endtask endpackage module C; // Like above but in a module int n = 0; initial if ($random) n = n++; endmodule module t; // Actually use those to test relinking C c(); initial begin A::t(); B::t(); end endmodule verilator-5.042/test_regress/t/t_module_class_static_method.py0000755000542200017500000000073415101701376025353 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_parse_eof_qqq_bad.out0000644000542200017500000000032615101701376023576 0ustar mahmoudyfreeshell%Error: t/t_parse_eof_qqq_bad.v:7:1: EOF in unterminated """ string 7 | """ | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_lint_in_inc_bad_1.vh0000644000542200017500000000037015101701376023263 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `include "t_lint_in_inc_bad_2.vh" verilator-5.042/test_regress/t/t_trace_ena_cc.py0000755000542200017500000000165215101701376022360 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_ena.v" test.compile(verilator_flags2=['-trace']) test.execute() if test.vlt_all: test.file_grep(test.obj_dir + "/V" + test.name + "__Trace__0__Slow.cpp", r'c_trace_on\"') test.file_grep_not(test.obj_dir + "/V" + test.name + "__Trace__0__Slow.cpp", r'_trace_off\"') test.file_grep(test.trace_filename, r'\$enddefinitions') test.file_grep_not(test.trace_filename, r'inside_sub') test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_opt_slice.v0000644000542200017500000000070215101701376021560 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs o1a2, // Inputs i1a2 ); input i1a2 [1:0]; output logic o1a2 [1:0]; always o1a2 = i1a2; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_enum_x_bad.out0000644000542200017500000000115015101701376022240 0ustar mahmoudyfreeshell%Error: t/t_enum_x_bad.v:9:21: Enum value with X/Zs cannot be assigned to non-fourstate type (IEEE 1800-2023 6.19) : ... note: In instance 't' 9 | enum bit [1:0] { BADX = 2'b1x } BAD1; | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_enum_x_bad.v:12:23: Enum value that is unassigned cannot follow value with X/Zs (IEEE 1800-2023 6.19) : ... note: In instance 't' 12 | e1 | ^~ %Error: Exiting due to verilator-5.042/test_regress/t/t_for_loop.v0000644000542200017500000000612115101701376021417 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [7:0] cyc; initial cyc = 0; reg [31:0] loops; reg [31:0] loops2; integer i; always @ (posedge clk) begin cyc <= cyc+8'd1; if (cyc == 8'd1) begin $write("[%0t] t_loop: Running\n", $time); // Unwind < loops = 0; loops2 = 0; for (i=0; i<16; i=i+1) begin loops = loops + i; // surefire lint_off_line ASWEMB loops2 = loops2 + i; // surefire lint_off_line ASWEMB end if (i !== 16) $stop; if (loops !== 120) $stop; if (loops2 !== 120) $stop; // Unwind <= loops = 0; for (i=0; i<=16; i=i+1) begin loops = loops + 1; end if (i !== 17) $stop; if (loops !== 17) $stop; // Don't unwind breaked loops loops = 0; for (i=0; i<16; i=i+1) begin loops = loops + 1; if (i==7) i=99; // break out of loop end if (loops !== 8) $stop; // Don't unwind large loops! loops = 0; for (i=0; i<100000; i=i+1) begin loops = loops + 1; end if (loops !== 100000) $stop; // Test post-increment loops = 0; for (i=0; i<=16; i++) begin loops = loops + 1; end if (i !== 17) $stop; if (loops !== 17) $stop; // Test pre-increment loops = 0; for (i=0; i<=16; ++i) begin loops = loops + 1; end if (i !== 17) $stop; if (loops !== 17) $stop; // Test post-decrement loops = 0; for (i=16; i>=0; i--) begin loops = loops + 1; end if (i !== -1) $stop; if (loops !== 17) $stop; // Test pre-decrement loops = 0; for (i=16; i>=0; --i) begin loops = loops + 1; end if (i !== -1) $stop; if (loops !== 17) $stop; // // 1800-2017 optionals init/expr/incr loops = 0; i = 0; for (; i<10; ++i) ++loops; if (loops !== 10) $stop; // loops = 0; i = 0; for (i=0; i<10; ) begin ++loops; ++i; end if (loops !== 10) $stop; // loops = 0; i = 0; for (; ; ++i) begin ++loops; break; end if (loops !== 1) $stop; // // bug1605 i = 1; for (i=20; 0; ) ; if (i != 20) $stop; for (i=30; i<10; i++) ; if (i != 30) $stop; // Comma loops = 0; for (i=0; i<20; ++i, ++loops); if (loops !== 20) $stop; loops = 0; for (i=0; i<20; ++loops, ++i); if (loops !== 20) $stop; // $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_math_concat64.py0000755000542200017500000000073415101701376022424 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_noreturn_param_bad.v0000644000542200017500000000066015101701376024472 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs o ); // verilator lint_off UNDRIVEN function integer no_rtn(); // <--- Warning: No return endfunction localparam WIDTH = no_rtn(); output [WIDTH-1:0] o; endmodule verilator-5.042/test_regress/t/t_varref_scope_in_interface.v0000755000542200017500000000114715101701376024772 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface iface #(parameter DWIDTH = 32)(); localparam TOTAL_PACKED_WIDTH = DWIDTH + 1; modport Tx(output sop, data, import unpack); logic sop; logic [DWIDTH - 1:0] data = '0; task static unpack(input logic [TOTAL_PACKED_WIDTH-1:0] packed_in, input logic sop_i); logic sop_nc; {data, sop_nc} <= packed_in; sop <= sop_i; endtask endinterface module t; iface ifc(); endmodule verilator-5.042/test_regress/t/t_interface_modport_dir_bad.out0000644000542200017500000000065615101701376025321 0ustar mahmoudyfreeshell%Error: t/t_interface_modport_dir_bad.v:52:25: Port connection 'ctrl' expected 'source' interface modport on pin connection but got 'sink' modport. : ... note: In instance 't.source_i' 52 | sourceMod source_i (.ctrl); | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_math_signed2.py0000755000542200017500000000073415101701376022336 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_pragma_protected.v0000644000542200017500000000424515101701376024153 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // This part should pass OK module t_lint_pragma_protected; `pragma protect begin_protected // Any amount of whitespace should be ok `pragma protect version=1 `pragma protect version = 1 `pragma protect version= 1 `pragma protect version =1 `pragma protect encrypt_agent="XXXXX" `pragma protect encrypt_agent_info="YYYYY" `pragma protect data_method="AES128-CBC" `pragma protect key_keyowner="BIG3#1" `pragma protect key_keyname="AAAAAA" `pragma protect key_method="RSA" `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `pragma protect key_block ICAgICAgICAgICAgICAgICAgIEdOVSBMRVNTRVIgR0VORVJBTCBQVUJMSUMgTElDRU5TRQogICAg KSAyMDA3IE== `pragma protect key_keyowner="BIG3#2" `pragma protect key_keyname="BBBBBB" `pragma protect key_method="RSA" `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `pragma protect key_block IEV2ZXJ5b25lIGlzIHBlcm1pdHRlZCB0byBjb3B5IGFuZCBkaXN0cmlidXRlIHZlcmJhdGltIGNv cGllcwogb2YgdGhpcyBsaWNlbnNlIGRvY3VtZW50LCBidXQgY2hhbmdpbmcgaXQgaXMgbm90IGFs bG93ZWQuCgoKICBUaGl= `pragma protect key_keyowner="BIG3#3" `pragma protect key_keyname="CCCCCCCC" `pragma protect key_method="RSA" `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `pragma protect key_block TGljZW5zZSBpbmNvcnBvcmF0ZXMKdGhlIHRlcm1zIGFuZCBjb25kaXRpb25zIG9mIHZlcnNpb24g MyBvZiB0aGUgR05VIEdlbmVyYWwgUHVibGljCkxpY2Vuc2UsIHN1cHBsZW1lbnRlZCBieSB0aGUg YWRkaXRpb25hbCBwZXJ= `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 295) `pragma protect data_block aW5pdGlvbnMuCgogIEFzIHVzZWQgaGVyZWluLCAidGhpcyBMaWNlbnNlIiByZWZlcnMgdG8gdmVy c2lvbiAzIG9mIHRoZSBHTlUgTGVzc2VyCkdlbmVyYWwgUHVibGljIExpY2Vuc2UsIGFuZCB0aGUg IkdOVSBHUEwiIHJlZmVycyB0byB2ZXJzaW9uIDMgb2YgdGhlIEdOVQpHZW5lcmFsIFB1YmxpYyBM aWNlbnNlLgoKICAiVGhlIExpYnJhcnkiIHJlZmVycyB0byBhIGNvdmVyZWQgd29yayBnb3Zlcm5l ZCBieSB0aGlzIExpY2Vuc2UsCm90aGVyIHRoYW4gYW4gQXBwbGljYXRpb24gb3IgYSBDb21iaW5l ZCBXb3JrIGFzIG== `pragma protect end_protected endmodule verilator-5.042/test_regress/t/t_timing_osc.v0000644000542200017500000000346315101701376021741 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" module tb_osc; timeunit 1s; timeprecision 1fs; logic dco_out; bhv_dco dco ( // Inputs .coarse_cw(8.0), .medium_cw(8.0), .fine_cw(32.0), // Outputs .rf_out(dco_out) ); initial begin $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); $dumpvars; `ifdef TEST_BENCHMARK #200ns; `else #3ns; `endif $write("*-* All Finished *-*\n"); $finish; end endmodule module bhv_dco ( input real coarse_cw, input real medium_cw, input real fine_cw, output logic rf_out ); parameter realtime coarse_ofst = 600ps; parameter realtime coarse_res = 60ps; parameter realtime medium_ofst = 130ps; parameter realtime medium_res = 6ps; parameter realtime fine_ofst = 70ps; parameter realtime fine_res = 0.2ps; timeunit 1s; timeprecision 1fs; realtime coarse_delay, medium_delay, fine_delay, jitter; assign coarse_delay = 0.5 * (coarse_cw * coarse_res + coarse_ofst ); assign medium_delay = 0.5 * (medium_cw * medium_res + medium_ofst ); assign fine_delay = 0.5 * ( fine_cw * fine_res + fine_ofst + jitter); assign jitter = 0; logic coarse_out, medium_out, fine_out; initial coarse_out = 0; always @ (fine_out) coarse_out <= #coarse_delay ~fine_out; assign #medium_delay medium_out = ~coarse_out; assign #fine_delay fine_out = ~medium_out; assign #50ps rf_out = fine_out; endmodule verilator-5.042/test_regress/t/t_dump_tree_dot.py0000755000542200017500000000101615101701376022616 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_EXAMPLE.v" test.lint(v_flags=["--lint-only --dump-tree-dot"]) test.passes() verilator-5.042/test_regress/t/t_struct_circ_bad.v0000644000542200017500000000064315101701376022735 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; typedef t1_t; typedef struct packed { t1_t x; // <--- Bad: Circular } t2_t; typedef t2_t [1:0] t3_t; typedef t3_t t1_t; // <--- Bad: Circular (or above) t1_t x; endmodule verilator-5.042/test_regress/t/t_net_dtype_bad.out0000644000542200017500000000405115101701376022743 0ustar mahmoudyfreeshell%Error: t/t_net_dtype_bad.v:25:15: Net 'bad_real' data type must be 4-state integral or array/union/struct of such (IEEE 1800-2023 6.7.1) : ... note: In instance 't' 25 | wire real_t bad_real; | ^~~~~~~~ t/t_net_dtype_bad.v:11:11: ... Location of failing data type 'real' 11 | typedef real real_t; | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_net_dtype_bad.v:27:12: Net 'bad_class' data type must be 4-state integral or array/union/struct of such (IEEE 1800-2023 6.7.1) : ... note: In instance 't' 27 | wire Cls bad_class; | ^~~~~~~~~ t/t_net_dtype_bad.v:27:8: ... Location of failing data type 'class{}Cls' 27 | wire Cls bad_class; | ^~~ %Error: t/t_net_dtype_bad.v:29:15: Net 'bad_string' data type must be 4-state integral or array/union/struct of such (IEEE 1800-2023 6.7.1) : ... note: In instance 't' 29 | wire string bad_string; | ^~~~~~~~~~ t/t_net_dtype_bad.v:29:8: ... Location of failing data type 'string' 29 | wire string bad_string; | ^~~~~~ %Error: t/t_net_dtype_bad.v:31:12: Net 'bad_bit' data type must be 4-state integral or array/union/struct of such (IEEE 1800-2023 6.7.1) : ... note: In instance 't' 31 | wire bit bad_bit; | ^~~~~~~ t/t_net_dtype_bad.v:31:8: ... Location of failing data type 'bit' 31 | wire bit bad_bit; | ^~~ %Error: t/t_net_dtype_bad.v:33:14: Net 'bad_struct' data type must be 4-state integral or array/union/struct of such (IEEE 1800-2023 6.7.1) : ... note: In instance 't' 33 | wire bad_t bad_struct; | ^~~~~~~~~~ t/t_net_dtype_bad.v:14:5: ... Location of failing data type 'bit' 14 | bit m_bit; | ^~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_sys_file_basic_uz.py0000755000542200017500000000137315101701376023466 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.unlink_ok(test.obj_dir + "/t_sys_file_basic_uz_test.log") test.compile() test.execute() test.files_identical(test.obj_dir + "/t_sys_file_basic_uz_test.log", test.golden_filename) test.files_identical(test.obj_dir + "/t_sys_file_basic_uz_test.bin", test.t_dir + "/t_sys_file_basic_uz.dat") test.passes() verilator-5.042/test_regress/t/t_uniqueif_fail3.out0000644000542200017500000000021515101701376023043 0ustar mahmoudyfreeshell[10] %Error: t_uniqueif.v:90: Assertion failed in top.t: 'unique if' statement violated %Error: t/t_uniqueif.v:90: Verilog $stop Aborting... verilator-5.042/test_regress/t/t_order_comboloop.v0000644000542200017500000000273515101701376022773 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; // verilator lint_off LATCH // verilator lint_off UNOPT // verilator lint_off UNOPTFLAT reg [31:0] runner; initial runner = 5; reg [31:0] runnerm1; reg [59:0] runnerq; reg [89:0] runnerw; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin `ifdef verilator if (runner != 0) $stop; // Initial settlement failed `endif end if (cyc==2) begin runner = 20; runnerq = 60'h0; runnerw = 90'h0; end if (cyc==3) begin if (runner != 0) $stop; $write("*-* All Finished *-*\n"); $finish; end end end // This forms a "loop" where we keep going through the always till runner=0 // This isn't "regular" beh code, but ensures our change detection is working properly always @ (/*AS*/runner) begin runnerm1 = runner - 32'd1; end always @ (/*AS*/runnerm1) begin if (runner > 0) begin runner = runnerm1; runnerq = runnerq - 60'd1; runnerw = runnerw - 90'd1; $write ("[%0t] runner=%d\n", $time, runner); end end endmodule verilator-5.042/test_regress/t/t_queue_output_func.py0000755000542200017500000000073415101701376023551 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_var_const_bad.out0000644000542200017500000000054715101701376022754 0ustar mahmoudyfreeshell%Error-CONSTWRITTEN: t/t_var_const_bad.v:17:7: Writing to 'const' data-typed variable 'five' (IEEE 1800-2023 6.20.6) : ... note: In instance 't' 17 | five = 3'd4; | ^~~~ ... For error description see https://verilator.org/warn/CONSTWRITTEN?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_interface_find.py0000755000542200017500000000073415101701376022732 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_type_param_circ_bad.out0000644000542200017500000000054115101701376024111 0ustar mahmoudyfreeshell%Error: t/t_type_param_circ_bad.v:14:22: Recursive type definition, or over 1000 types deep : ... note: In instance 't' 14 | # (parameter type SZ = SZ) | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_class_eq.v0000644000542200017500000000115715101701376021376 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(); class A; int num; function new(int num); this.num = num; endfunction endclass class B; static A obj = new(2); endclass class C; static A obj = new(5); endclass initial begin #1; $display("Bobj=%p Cobj=%p eq=%p", B::obj, C::obj, (B::obj == C::obj)); if (B::obj == C::obj) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_dfg_4943.v0000644000542200017500000000070215101701376021022 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module top(input wire i, output wire o); // Partially driven, and drives other var with non-DFG refs wire logic [1:0] x; assign x[0] = i; assign o = |x; wire logic [1:0] alt = x; always @(alt) $display(alt); endmodule verilator-5.042/test_regress/t/t_flag_runtime_debug.py0000755000542200017500000000117315101701376023612 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_flag_main.v" test.compile(verilator_flags2=['--binary --runtime-debug']) test.execute() test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".mk", r'VL_DEBUG=1') test.passes() verilator-5.042/test_regress/t/t_vlt_warn_ecode_bad.vlt0000644000542200017500000000051415101701376023741 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `verilator_config lint_off -rule BADRULENAME -file "t/t_vlt_warn.v" lint_on -rule BADRULENAME -file "t/t_vlt_warn.v" verilator-5.042/test_regress/t/t_interface_twod.py0000755000542200017500000000073415101701376022767 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_cover_line_expr_cc.py0000755000542200017500000000170615101701376023622 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_cover_expr.v" test.golden_filename = "t/t_cover_line_expr.out" test.compile(verilator_flags2=['--cc --coverage-line --coverage-expr']) test.execute() test.run(cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--annotate-points", "--annotate", test.obj_dir + "/annotated", test.obj_dir + "/coverage.dat"], verilator_run=True) # yapf:disable test.files_identical(test.obj_dir + "/annotated/t_cover_expr.v", test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_param_type_fwd_bad.py0000755000542200017500000000076315101701376023603 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_inst_pin_place_bad.out0000644000542200017500000000163215101701376023741 0ustar mahmoudyfreeshell%Warning-PINMISSING: t/t_inst_pin_place_bad.v:21:7: Instance has missing pin: 'pin_1' 21 | ) i_sub ( | ^~~~~ t/t_inst_pin_place_bad.v:11:11: ... Location of port declaration 11 | input pin_1 | ^~~~~ ... For warning description see https://verilator.org/warn/PINMISSING?v=latest ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message. %Error: t/t_inst_pin_place_bad.v:22:10: Instance attempts to connect to 'PARAM_A', but it is a parameter 22 | .PARAM_A(1) | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_inst_pin_place_bad.v:20:10: Instance attempts to override 'pin_1' as a parameter, but it is a port 20 | .pin_1(1) | ^~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_interface_virtual_timing.out0000644000542200017500000000034215101701376025216 0ustar mahmoudyfreeshell[0] vif1.data==dead [0] intf2.data==0000 [1] intf2.data==beef [2] vif1.data==cafe [3] intf2.data==face [4] vif1.data==feed [5] intf2.data==deed [6] vif1.data==deaf [7] intf2.data==fafa [8] vif1.data==bebe *-* All Finished *-* verilator-5.042/test_regress/t/t_cover_lib__1_per_instance.out0000644000542200017500000000125315101701376025220 0ustar mahmoudyfreeshell# SystemC::Coverage-3 C 'f../../t/t_cover_lib_c.cppl39t_userpagesp_user/t_cover_lib_cP0htop.a0.pi' 200 C 'f../../t/t_cover_lib_c.cppl39t_userpagesp_user/t_cover_lib_cP0htop.a1.pi' 300 C 'f../../t/t_cover_lib_c.cppl39t_userpagesp_user/t_cover_lib_cP1htop.a0.npi' 200 C 'f../../t/t_cover_lib_c.cppl39t_userpagesp_user/t_cover_lib_cP1htop.a1.npi' 300 C 'f../../t/t_cover_lib_c.cppl48t_userpagesp_user/t_cover_lib_cokept_onehmain' 100 C 'f../../t/t_cover_lib_c.cppl49t_userpagesp_user/t_cover_lib_cokept_twohmain' 210 C 'f../../t/t_cover_lib_c.cppl50t_userpagesp_user/t_cover_lib_colost_threehmain' 220 verilator-5.042/test_regress/t/t_var_sc_double.v0000644000542200017500000000050715101701376022411 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2025 by George Polack. // SPDX-License-Identifier: CC0-1.0 module t ( // Outputs o_z, // Inputs i_a ); input real i_a; output real o_z; assign o_z = i_a; endmodule verilator-5.042/test_regress/t/t_class_param_subtype.v0000644000542200017500000000174315101701376023645 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2023 by Anthony Donlon. // SPDX-License-Identifier: CC0-1.0 // Test for bug4281 class CParam #(parameter PARAM=10); typedef int type_t; endclass class CParam2 #(parameter PARAM=10); typedef int type_t; typedef logic [PARAM-1:0] type2_t; endclass `ifdef CONSTSIM module sub(); parameter N = 32; for (genvar i = 0; i < N/8; i = i + 1) begin initial begin end end // Test for bug4281, usage conflict of user2 with constant simulator in V3Param.cpp endmodule `endif module t; `ifdef BAD_PAREN CParam::type_t val_0 = 100; `else CParam#()::type_t val_0 = 100; `endif CParam2#()::type_t val_2 = 200; `ifdef CONSTSIM sub i_sub(); `endif initial begin if (val_0 != 100) $stop; if (val_2 != 200) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_lint_setout_bad.v0000644000542200017500000000120515101701376022755 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( input wire reset_l, input wire clk ); sub sub_I ( .clk(clk), .reset_l(reset_l), .cpu_if_timeout(1'b0) ); endmodule module sub ( input wire clk, reset_l, output reg cpu_if_timeout ); always @(posedge clk) begin if (!reset_l) begin cpu_if_timeout <= 1'b0; end else begin cpu_if_timeout <= 1'b0; end end endmodule verilator-5.042/test_regress/t/t_order_dpi_export_4.v0000644000542200017500000000274515101701376023403 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2021 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module testbench( /*AUTOARG*/ // Inputs clk ); input clk; // Top level input clock bit other_clk; // Dependent clock set via DPI bit third_clk; // Additional dependent clock set via DPI export "DPI-C" function set_other_clk; function void set_other_clk(bit val); other_clk = val; endfunction; export "DPI-C" function set_third_clk; function void set_third_clk(bit val); third_clk = val; endfunction; bit even_other = 1; import "DPI-C" context function void toggle_other_clk(bit val); always @(posedge clk) begin even_other <= ~even_other; toggle_other_clk(even_other); end bit even_third = 1; import "DPI-C" context function void toggle_third_clk(bit val); always @(posedge other_clk) begin even_third <= ~even_third; toggle_third_clk(even_third); end int n = 0; wire final_clk = $c1("1") & third_clk; always @(posedge final_clk) begin $display("[%0t] n=%0d", $time, n); if ($time != (8*n+1) * 500) $stop; if (n == 20) begin $write("*-* All Finished *-*\n"); $finish; end n += 1; end endmodule verilator-5.042/test_regress/t/t_sys_writemem.gold1.mem0000644000542200017500000000005215101701376023642 0ustar mahmoudyfreeshell02 03 04 05 06 07 10 00 00 00 14 15 00 00 verilator-5.042/test_regress/t/t_event_control_expr_unsup.v0000644000542200017500000000053215101701376024751 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t; int x; function bit foo; x += 1; return bit'(x % 2); endfunction always @(posedge foo()); endmodule verilator-5.042/test_regress/t/t_class_scope_import_bad.out0000644000542200017500000000042215101701376024636 0ustar mahmoudyfreeshell%Error: t/t_class_scope_import_bad.v:11:11: Import statement directly within a class scope is illegal 11 | import pkg::*; | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_interface_gen11.py0000755000542200017500000000073415101701376022725 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_binary.py0000755000542200017500000000125115101701376022427 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile( verilator_flags=[ # Custom as don't want -cc "-Mdir " + test.obj_dir, "--debug-check" ], verilator_flags2=['--binary --trace']) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_latch_2.py0000755000542200017500000000070315101701376022330 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint() test.passes() verilator-5.042/test_regress/t/t_const_bad.out0000644000542200017500000000225315101701376022100 0ustar mahmoudyfreeshell%Warning-WIDTHXZEXPAND: t/t_const_bad.v:13:39: Unsized constant being X/Z extended to 68 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : ... note: In instance 't' 13 | if (68'hx_xxxxxxxx_xxxxxxxx !== 'dX) $stop; | ^~~ ... For warning description see https://verilator.org/warn/WIDTHXZEXPAND?v=latest ... Use "/* verilator lint_off WIDTHXZEXPAND */" and lint_on around source to disable this message. %Warning-WIDTHXZEXPAND: t/t_const_bad.v:14:39: Unsized constant being X/Z extended to 68 bits: ?32?bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz : ... note: In instance 't' 14 | if (68'hz_zzzzzzzz_zzzzzzzz !== 'dZ) $stop; | ^~~ %Warning-WIDTHXZEXPAND: t/t_const_bad.v:15:39: Unsized constant being X/Z extended to 68 bits: ?32?bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz : ... note: In instance 't' 15 | if (68'h?_????????_???????? !== 'd?) $stop; | ^~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_dist_cinclude.py0000755000542200017500000000447015101701376022604 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') if not os.path.exists(test.root + "/.git"): test.skip("Not in a git repository") ### Must trim output before and after our file list cmd = "cd " + test.root + " && git ls-files --exclude-standard" files = test.run_capture(cmd) if test.verbose: print("ST " + files) names = {} for filename in files.split(): if "include/vltstd/vpi_user.h" in filename: # IEEE Standard file - can't change it continue if "include/gtkwave/" in filename: # Standard file - can't change it continue if "test_regress/t/uvm/dpi/" in filename: # Standard file - can't change it continue filename = os.path.join(test.root, filename) if not os.path.exists(filename): continue with open(filename, 'r', encoding='latin-1') as fh: for line in fh: if "include" not in line: continue line = line.rstrip() hit = (re.search(r'\bassert\.h', line) or re.search(r'\bctype\.h', line) or re.search(r'\berrno\.h', line) or re.search(r'\bfloat\.h', line) or re.search(r'\blimits\.h', line) or re.search(r'\blocale\.h', line) or re.search(r'\bmath\.h', line) or re.search(r'\bsetjmp\.h', line) or re.search(r'\bsignal\.h', line) or re.search(r'\bstdarg\.h', line) or re.search(r'\bstdbool\.h', line) or re.search(r'\bstddef\.h', line) or re.search(r'\bstdio\.h', line) or re.search(r'\bstdlib\.h', line) or re.search(r'\bstring\.h', line) or (re.search(r'\btime\.h', line) and not re.search(r'sys/time.h', line))) #Not yet: r'\bstdint\.h' if not hit: continue names[filename + ": " + line] = True if len(names): test.error("Files like stdint.h instead of cstdint:\n " + "\n ".join(sorted(names.keys()))) test.passes() verilator-5.042/test_regress/t/t_hier_block_chained.vlt0000644000542200017500000000052615101701376023717 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 `verilator_config hier_block -module "Calculate" hier_block -module "Check" `ifdef WORKERS hier_workers -module "Calculate" -workers `WORKERS `endif verilator-5.042/test_regress/t/t_extend.v0000644000542200017500000000353515101701376021075 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); /*verilator public_module*/ input clk; // No verilator_public needed, because it's outside the "" in the $c statement reg [7:0] cyc; initial cyc = 0; reg c_worked; reg [8:0] c_wider; wire one = 1'b1; always @ (posedge clk) begin cyc <= cyc + 8'd1; // coverage testing if (one) begin end if (!one) begin end if (cyc[0]) begin end if (!cyc[0]) begin end // multiple on a line if (cyc == 8'd1) begin c_worked <= 0; end if (cyc == 8'd2) begin `ifdef VERILATOR $c("VL_PRINTF(\"Calling $c, calling $c...\\n\");"); $c("VL_PRINTF(\"Cyc=%d\\n\",", cyc, ");"); c_worked <= $c("this->my_function()"); c_wider <= $c9("0x10"); `else c_worked <= 1'b1; c_wider <= 9'h10; `endif end if (cyc == 8'd3) begin if (c_worked !== 1'b1) $stop; if (c_wider !== 9'h10) $stop; $finish; end end `ifdef verilator `systemc_header #define DID_INT_HEADER 1 `systemc_interface #ifndef DID_INT_HEADER #error "`systemc_header didn't work" #endif bool m_did_ctor; uint32_t my_function() { if (!m_did_ctor) vl_fatal(__FILE__, __LINE__, __FILE__, "`systemc_ctor didn't work"); return 1; } `systemc_imp_header #define DID_IMP_HEADER 1 `systemc_implementation #ifndef DID_IMP_HEADER #error "`systemc_imp_header didn't work" #endif `systemc_ctor m_did_ctor = 1; `systemc_dtor printf("In systemc_dtor\n"); printf("*-* All Finished *-*\n"); `verilog // Test verilator comment after a endif `endif // verilator endmodule verilator-5.042/test_regress/t/t_string_add_bad.py0000755000542200017500000000076615101701376022723 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_tri_pullvec_bad.v0000644000542200017500000000075115101701376022741 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; tri [3:0] w; pullup p0 (w[0]); pulldown p1 (w[1]); pulldown p2 (w[2]); pullup p3 (w[3]); always_ff @ (posedge clk) begin if (w != 4'b1001) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_preproc_ifdefend_bad.py0000755000542200017500000000102515101701376024070 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, verilator_flags2=['--no-std'], expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_randsequence_bad.py0000755000542200017500000000076315101701376023257 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_x_rand_mt_stability_trace.py0000755000542200017500000000120615101701376025202 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios("vltmt") test.top_filename = "t/t_x_rand_stability.v" test.compile(verilator_flags2=["--x-initial unique", "--trace"]) test.execute(all_run_flags=["+verilator+rand+reset+2"], expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_ref_as_arg_cast.v0000644000542200017500000000062315101701376024070 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class Foo; static task bar(Foo f); endtask endclass class Qux extends Foo; endclass module t; initial begin Qux qux = new; Foo::bar(qux); Foo::bar(null); end endmodule verilator-5.042/test_regress/t/t_trace_no_top_name2_fst.out0000644000542200017500000000201615101701376024553 0ustar mahmoudyfreeshell$date Tue Jun 10 18:57:59 2025 $end $version fstWriter $end $timescale 1ps $end $scope module $rootio $end $var wire 1 ! clk $end $upscope $end $scope module foo_pkg $end $var int 32 " foo_func__Vstatic__b_current [31:0] $end $upscope $end $scope module t $end $var wire 1 ! clk $end $var int 32 # cyc [31:0] $end $scope module sub $end $var int 32 $ a [31:0] $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b00000000000000000000010010111100 $ b00000000000000000000000000000000 # b00000000000000000000000000000000 " 0! $end #1 1! b00000000000000000000000000000001 # #2 0! #3 1! b00000000000000000000000000000010 # #4 0! #5 1! b00000000000000000000000000000011 # #6 0! #7 1! b00000000000000000000000000000100 # #8 0! #9 1! b00000000000000000000000000000101 # #10 0! #11 1! b00000000000000000000000000000110 # #12 0! #13 1! b00000000000000000000000000000111 # #14 0! #15 1! b00000000000000000000000000001000 # #16 0! #17 1! b00000000000000000000000000001001 # #18 0! #19 1! b00000000000000000000000000001010 # #20 0! verilator-5.042/test_regress/t/t_clocker.v0000644000542200017500000000214715101701376021226 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Simple test of CLkDATA // // Trigger the CLKDATA detection // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Jie Xu. // SPDX-License-Identifier: CC0-1.0 localparam ID_MSB = 1; module t (/*AUTOARG*/ // Inputs clk, res, res8, res16 ); input clk; output reg res; // When not inlining the below may trigger CLKDATA output reg [7:0] res8; output reg [15:0] res16; wire [7:0] clkSet; wire clk_1; wire [2:0] clk_3; wire [3:0] clk_4; wire clk_final; reg [7:0] count; assign clkSet = {8{clk}}; assign clk_4 = clkSet[7:4]; assign clk_1 = clk_4[0];; // arraysel assign clk_3 = {3{clk_1}}; assign clk_final = clk_3[0]; assign res8 = {clk_3, 1'b0, clk_4}; assign res16 = {count, clk_3, clk_1, clk_4}; initial count = 0; always @(posedge clk_final or negedge clk_final) begin count = count + 1; res <= clk_final; if ( count == 8'hf) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_gantt_hier.py0000755000542200017500000000363015101701376022114 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Test for bin/verilator_gantt, import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_gantt.v" test.pli_filename = "t/t_gantt_c.cpp" test.compile( verilator_flags2=["--prof-exec", "--hierarchical", test.pli_filename], # Checks below care about thread count, so use 2 (minimum reasonable) threads=(2 if test.vltmt else 1)) test.execute(all_run_flags=[ "+verilator+prof+exec+start+2", " +verilator+prof+exec+window+2", " +verilator+prof+exec+file+" + test.obj_dir + "/profile_exec.dat", " +verilator+prof+vlt+file+" + test.obj_dir + "/profile.vlt"]) # yapf:disable gantt_log = test.obj_dir + "/gantt.log" # The profiling data goes direct to the runtime's STDOUT # (maybe that should go to a separate file - gantt.dat?) test.run(cmd=[ os.environ["VERILATOR_ROOT"] + "/bin/verilator_gantt", test.obj_dir + "/profile_exec.dat", "--vcd " + test.obj_dir + "/profile_exec.vcd", "| tee " + gantt_log ]) if test.vltmt: test.file_grep(gantt_log, r'Total threads += +(\d+)', 2) test.file_grep(gantt_log, r'Total mtasks += +(\d+)', 6) # Predicted thread utilization should be less than 100% test.file_grep_not(gantt_log, r'Thread utilization =\s*\d\d\d+\.\d+%') else: test.file_grep(gantt_log, r'Total threads += +(\d+)', 1) test.file_grep(gantt_log, r'Total mtasks += +(\d+)', 0) test.file_grep(gantt_log, r'\|\s+2\s+\|\s+2\.0+\s+\|\s+eval') # Diff to itself, just to check parsing test.vcd_identical(test.obj_dir + "/profile_exec.vcd", test.obj_dir + "/profile_exec.vcd") test.passes() verilator-5.042/test_regress/t/t_gate_implicit.py0000755000542200017500000000073415101701376022604 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_case_auto1.py0000755000542200017500000000073415101701376022016 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_comb_input_1.py0000755000542200017500000000110215101701376022337 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile( #make_top_shell = False, make_main=False, v_flags2=["--exe", test.pli_filename, "-fno-dfg"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_unpacked_init.py0000755000542200017500000000073415101701376022607 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_modport_bad.out0000644000542200017500000000055715101701376024463 0ustar mahmoudyfreeshell%Error: t/t_interface_modport_bad.v:23:8: Modport not found under interface 'ifc': 'oop_modport' : ... Suggested alternative: 'out_modport' 23 | ifc.oop_modport isub, | ^~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_param_type_collision.py0000755000542200017500000000105115101701376024177 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_param_type.v" test.compile(verilator_flags2=["--debug-collision"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_event.v0000644000542200017500000000347615101701376020733 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `ifdef TEST_VERBOSE `define WRITE_VERBOSE(args) $write args `else `define WRITE_VERBOSE(args) `endif module t(/*AUTOARG*/ // Inputs clk ); input clk; event e1; event e2; event e3; `ifndef IVERILOG event ev [3:0]; `endif int cyc = 0; int last_event = 0; always @(e1) begin `WRITE_VERBOSE(("[%0t] e1\n", $time)); if (!e1.triggered) $stop; last_event[1] = 1; end always @(e2) begin `WRITE_VERBOSE(("[%0t] e2\n", $time)); if (!e2.triggered) $stop; last_event[2] = 1; end always @(posedge clk) begin `WRITE_VERBOSE(("[%0t] cyc=%0d last_event=%5b\n", $time, cyc, last_event)); cyc <= cyc + 1; case (cyc) default: begin // Check no initial or spurious trigger if (last_event != 0) $stop; end // 10: begin if (last_event != 0) $stop; -> e1; if (!e1.triggered) $stop; if (e3.triggered) $stop; -> e3; if (!e3.triggered) $stop; end 11: begin if (last_event != 32'b10) $stop; last_event = 0; if (e3.triggered) $stop; end // 13: begin if (last_event != 0) $stop; ->> e2; if (e2.triggered) $stop; if (e3.triggered) $stop; end 14: begin if (last_event != 32'b100) $stop; last_event = 0; end // 99: begin $write("*-* All Finished *-*\n"); $finish; end endcase end endmodule verilator-5.042/test_regress/t/t_timing_clkgen3.v0000644000542200017500000000211315101701376022472 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `timescale 10ns / 1ns `ifdef TEST_VERBOSE `define WRITE_VERBOSE(args) $write args `else `define WRITE_VERBOSE(args) `endif module t; logic clk = 0; logic clk_copy; int cyc = 0; int cnt1 = 0; int cnt2 = 0; initial forever #1 clk = ~clk; always @(negedge clk) begin #0.75 cnt1++; `WRITE_VERBOSE(("[%0t] NEG clk (%b)\n", $time, clk)); end always @(posedge clk) begin cyc <= cyc + 1; #0.5 `WRITE_VERBOSE(("[%0t] POS clk (%b)\n", $time, clk)); if (cyc == 5) begin if (cnt1 != 4 && cnt2 != 9) $stop; $write("*-* All Finished *-*\n"); $finish; end end assign clk_copy = clk; always @(posedge clk_copy or negedge clk_copy) begin #0.25 cnt2++; `WRITE_VERBOSE(("[%0t] POS/NEG clk_copy (%b)\n", $time, clk_copy)); end initial #100 $stop; // timeout endmodule verilator-5.042/test_regress/t/t_hierarchy_unnamed.py0000755000542200017500000000070615101701376023456 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.042/test_regress/t/t_func_endian.py0000755000542200017500000000073415101701376022243 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_covergroup_with_sample_args_too_few_bad.v0000644000542200017500000000075315101701376027740 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off COVERIGN */ module t; covergroup cg_with_sample(int init) with function sample (int addr, bit is_read); endgroup cg_with_sample cov1 = new(0); function void run(); // Too few arguments (1 instead of 2) cov1.sample(1); endfunction endmodule verilator-5.042/test_regress/t/t_cast_size_bad.py0000755000542200017500000000076615101701376022571 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_strength_strongest_constant.py0000755000542200017500000000073415101701376025651 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_mod_longname.v0000644000542200017500000000346415101701376022246 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // The code as shown makes a really big file name with Verilator. // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 `define LONG_NAME_MOD modlongnameiuqyrewewriqyewroiquyweriuqyewriuyewrioryqoiewyriuewyrqrqioeyriuqyewriuqyeworqiurewyqoiuewyrqiuewoyewriuoeyqiuewryqiuewyroiqyewiuryqeiuwryuqiyreoiqyewiuryqewiruyqiuewyroiuqyewroiuyqewoiryqiewuyrqiuewyroqiyewriuqyewrewqroiuyqiuewyriuqyewroiqyewroiquewyriuqyewroiqewyriuqewyroiqyewroiyewoiuryqoiewyriuqyewiuryqoierwyqoiuewyrewoiuyqroiewuryewurqyoiweyrqiuewyreqwroiyweroiuyqweoiuryqiuewyroiuqyroie `define LONG_NAME_SUB sublongnameiuqyrewewriqyewroiquyweriuqyewriuyewrioryqoiewyriuewyrqrqioeyriuqyewriuqyeworqiurewyqoiuewyrqiuewoyewriuoeyqiuewryqiuewyroiqyewiuryqeiuwryuqiyreoiqyewiuryqewiruyqiuewyroiuqyewroiuyqewoiryqiewuyrqiuewyroqiyewriuqyewrewqroiuyqiuewyriuqyewroiqyewroiquewyriuqyewroiqewyriuqewyroiqyewroiyewoiuryqoiewyriuqyewiuryqoierwyqoiuewyrewoiuyqroiewuryewurqyoiweyrqiuewyreqwroiyweroiuyqweoiuryqiuewyroiuqyroie `define LONG_NAME_VAR varlongnameiuqyrewewriqyewroiquyweriuqyewriuyewrioryqoiewyriuewyrqrqioeyriuqyewriuqyeworqiurewyqoiuewyrqiuewoyewriuoeyqiuewryqiuewyroiqyewiuryqeiuwryuqiyreoiqyewiuryqewiruyqiuewyroiuqyewroiuyqewoiryqiewuyrqiuewyroqiyewriuqyewrewqroiuyqiuewyriuqyewroiqyewroiquewyriuqyewroiqewyriuqewyroiqyewroiyewoiuryqoiewyriuqyewiuryqoierwyqoiuewyrewoiuyqroiewuryewurqyoiweyrqiuewyreqwroiyweroiuyqweoiuryqiuewyroiuqyroie module t (); initial begin $write("*-* All Finished *-*\n"); $finish; end logic `LONG_NAME_VAR; `LONG_NAME_MOD `LONG_NAME_SUB (); endmodule module `LONG_NAME_MOD (); // Force Verilator to make a new class logic a1 /* verilator public */; endmodule verilator-5.042/test_regress/t/t_randomize_inline_var_ctl_unsup_1.py0000755000542200017500000000100115101701376026470 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface_virtual_sched_ico.out0000644000542200017500000000102715101701376025650 0ustar mahmoudyfreeshell[0] intf1.inc==00000000 [0] vif2.inc==00000001 [5000] intf1.inc==00000001 [10000] vif2.inc==00000002 [15000] intf1.inc==00000002 [20000] vif2.inc==00000003 [25000] intf1.inc==00000003 [30000] vif2.inc==00000004 [35000] intf1.inc==00000004 [40000] vif2.inc==00000005 [45000] intf1.inc==00000005 [50000] vif2.inc==00000006 [55000] intf1.inc==00000006 [60000] vif2.inc==00000007 [65000] intf1.inc==00000007 [70000] vif2.inc==00000008 [75000] intf1.inc==00000008 [80000] vif2.inc==00000009 [85000] intf1.inc==00000009 *-* All Finished *-* verilator-5.042/test_regress/t/t_flag_aslr_no.py0000755000542200017500000000077515101701376022425 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = 't/t_EXAMPLE.v' test.lint(v_flags2=["--no-aslr"]) test.passes() verilator-5.042/test_regress/t/t_dfg_3676.v0000644000542200017500000000103615101701376021025 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 // verilator lint_off UNOPTFLAT module t( input wire [3:0] i, output wire [2:0][3:0] o ); wire [2:0][3:0] v; // This circular logic used to trip up DFG decomposition assign v[0] = i; assign v[1][0] = v[0][1] | v[0][0]; assign o[1][2] = v[0][2]; assign o[2][1:0] = {v[1][0] , o[1][0]}; endmodule verilator-5.042/test_regress/t/t_assoc_method.v0000644000542200017500000001352015101701376022251 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); module t; typedef struct {int x, y;} point; function automatic int vec_len_squared(point p); return p.x * p.x + p.y * p.y; endfunction initial begin int q[int]; int qe[int]; // Empty int qv[$]; // Value returns int qi[$]; // Index returns point points_q[int]; point points_qv[$]; int i; bit b; q = '{10: 1, 11: 2, 12: 2, 13: 4, 14: 3}; `checkp(q, "'{'ha:'h1, 'hb:'h2, 'hc:'h2, 'hd:'h4, 'he:'h3}"); // NOT tested: with ... selectors //q.sort; // Not legal on assoc - see t_assoc_meth_bad //q.rsort; // Not legal on assoc - see t_assoc_meth_bad //q.reverse; // Not legal on assoc - see t_assoc_meth_bad //q.shuffle; // Not legal on assoc - see t_assoc_meth_bad `checkp(qe, "'{}"); qv = q.unique; `checkp(qv, "'{'h1, 'h2, 'h4, 'h3}"); qv = qe.unique; `checkp(qv, "'{}"); qi = q.unique_index; qi.sort; `checkp(qi, "'{'ha, 'hb, 'hd, 'he}"); qi = qe.unique_index; `checkp(qi, "'{}"); points_q[0] = point'{1, 2}; points_q[1] = point'{2, 4}; points_q[5] = point'{1, 4}; points_qv = points_q.unique(p) with (p.x); `checkh(points_qv.size, 2); qi = points_q.unique_index (p) with (p.x + p.y); qi.sort; `checkp(qi, "'{'h0, 'h1, 'h5}"); qi = points_q.find_first_index with (item.x == 1); `checkp(qi, "'{'h0}"); qi = points_q.find_first_index with (item.x == 10); `checkp(qi, "'{}"); qi = points_q.find_last_index with (item.x == 1); `checkp(qi, "'{'h5}"); qi = points_q.find_last_index with (item.x == 12); `checkp(qi, "'{}"); // These require an with clause or are illegal // TODO add a lint check that with clause is provided qv = q.find with (item == 2); `checkp(qv, "'{'h2, 'h2}"); qv = q.find_first with (item == 2); `checkp(qv, "'{'h2}"); qv = q.find_last with (item == 2); `checkp(qv, "'{'h2}"); qv = q.find with (item == 20); `checkp(qv, "'{}"); qv = q.find_first with (item == 20); `checkp(qv, "'{}"); qv = q.find_last with (item == 20); `checkp(qv, "'{}"); qi = q.find_index with (item == 2); qi.sort; `checkp(qi, "'{'hb, 'hc}"); qi = q.find_first_index with (item == 2); `checkp(qi, "'{'hb}"); qi = q.find_last_index with (item == 2); `checkp(qi, "'{'hc}"); qi = q.find_index with (item == 20); qi.sort; `checkp(qi, "'{}"); qi = q.find_first_index with (item == 20); `checkp(qi, "'{}"); qi = q.find_last_index with (item == 20); `checkp(qi, "'{}"); qi = q.find_index with (item.index == 12); `checkp(qi, "'{'hc}"); qi = q.find with (item.index == 12); `checkp(qi, "'{'h2}"); qv = q.min; `checkp(qv, "'{'h1}"); points_qv = points_q.min(p) with (p.x + p.y); if (points_qv[0].x != 1 || points_qv[0].y != 2) $stop; qv = q.max; `checkp(qv, "'{'h4}"); points_qv = points_q.max(p) with (p.x + p.y); if (points_qv[0].x != 2 || points_qv[0].y != 4) $stop; qv = qe.min; `checkp(qv, "'{}"); qv = qe.min(x) with (x + 1); `checkp(qv, "'{}"); qv = qe.max; `checkp(qv, "'{}"); qv = qe.max(x) with (x + 1); `checkp(qv, "'{}"); // Reduction methods i = q.sum; `checkh(i, 32'hc); i = q.sum with (item + 1); `checkh(i, 32'h11); i = q.product; `checkh(i, 32'h30); i = q.product with (item + 1); `checkh(i, 32'h168); i = qe.sum; `checkh(i, 32'h0); i = qe.sum with (item + 1); `checkh(i, 32'h0); i = qe.product; `checkh(i, 32'h0); i = qe.product with (item + 1); `checkh(i, 32'h0); q = '{10: 32'b1100, 11: 32'b1010}; i = q.and; `checkh(i, 32'b1000); i = q.and with (item + 1); `checkh(i, 32'b1001); i = q.or; `checkh(i, 32'b1110); i = q.or with (item + 1); `checkh(i, 32'b1111); i = q.xor; `checkh(i, 32'b0110); i = q.xor with (item + 1); `checkh(i, 32'b0110); i = qe.and; `checkh(i, 32'b0); i = qe.and with (item + 1); `checkh(i, 32'h0); i = qe.or; `checkh(i, 32'b0); i = qe.or with (item + 1); `checkh(i, 32'b0); i = qe.xor; `checkh(i, 32'b0); i = qe.xor with (item + 1); `checkh(i, 32'b0); i = q.and(); `checkh(i, 32'b1000); i = q.and() with (item + 1); `checkh(i, 32'b1001); i = q.or(); `checkh(i, 32'b1110); i = q.or() with (item + 1); `checkh(i, 32'b1111); i = q.xor(); `checkh(i, 32'b0110); i = q.xor() with (item + 1); `checkh(i, 32'b0110); i = qe.and(); `checkh(i, 32'b0); i = qe.or(); `checkh(i, 32'b0); i = qe.xor(); `checkh(i, 32'b0); q = '{10: 1, 11: 2}; qe = '{10: 1, 11: 2}; `checkh(q == qe, 1'b1); `checkh(q != qe, 1'b0); i = points_q.sum with (vec_len_squared(item)); `checkh(i, 32'h2a); i = points_q.product with (vec_len_squared(item)); `checkh(i, 32'h6a4); b = points_q.sum with (vec_len_squared(item) == 5); `checkh(b, 1'b1); b = points_q.sum with (vec_len_squared(item) == 0); `checkh(b, 1'b0); b = points_q.product with (vec_len_squared(item) inside {5, 17}); `checkh(b, 1'b0); b = points_q.sum with (vec_len_squared(item) inside {5, 17, 20}); `checkh(b, 1'b1); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_mod_interface_array3.v0000644000542200017500000000175415101701376023667 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Johan Bjork. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); interface a_if (); string s; endinterface module sub (output string s); initial s = $sformatf("%m"); endmodule module t; string str [2:0][1:0]; a_if iface [2:0][1:0] (); sub i_sub[2:0][1:0] (.s(str)); initial begin // TODO make self checking $display(iface[0][0]); $display(iface[0][1]); $display(iface[1][0]); $display(iface[1][1]); $display(iface[2][0]); $display(iface[2][1]); $display(str[0][0]); $display(str[0][1]); $display(str[1][0]); $display(str[1][1]); $display(str[2][0]); $display(str[2][1]); end endmodule verilator-5.042/test_regress/t/t_dpi_var_vlt.py0000755000542200017500000000271115101701376022300 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_dpi_var.v" test.pli_filename = "t/t_dpi_var.cpp" out_filename = test.obj_dir + "/V" + test.name + ".tree.json" test.compile(make_top_shell=False, make_main=False, verilator_flags2=[ "--no-json-edit-nums", "--exe --no-l2name", test.t_dir + "/t_dpi_var.vlt", test.pli_filename ]) if test.vlt_all: test.file_grep( out_filename, r'{"type":"VAR","name":"formatted",.*"origName":"formatted",.*"direction":"INPUT",.*"attrSFormat":true' ) test.file_grep( out_filename, r'{"type":"VAR","name":"t.sub.in",.*"origName":"in",.*"isSigUserRdPublic":true') test.file_grep( out_filename, r'{"type":"VAR","name":"t.sub.fr_a",.*"origName":"fr_a",.*"isSigUserRdPublic":true,.*"isSigUserRWPublic":true' ) test.file_grep( out_filename, r'{"type":"VAR","name":"t.sub.fr_b",.*"origName":"fr_b",.*"isSigUserRdPublic":true,.*"isSigUserRWPublic":true' ) test.execute() test.passes() verilator-5.042/test_regress/t/t_time_sscanf.v0000644000542200017500000000211415101701376022071 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilog_format: off `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); // verilog_format: on `timescale 1ns / 100ps module main; real r; integer rc; time t; // verilator lint_off REALCVT initial begin rc = $sscanf("8.125", "%f", r); // as real `checkd(rc, 1); `checkr(r, 8.125); rc = $sscanf("8125", "%t", r); // in ns but round to 100 ps `checkd(rc, 1); t = r; `checkr(t, 813); $timeformat(-3, 2, "ms", 10); rc = $sscanf("8.125", "%t", r); // in ms `checkd(rc, 1); t = r; `checkr(t, 8125000); $finish; end endmodule verilator-5.042/test_regress/t/t_alias_ports_unsup.out0000644000542200017500000000104315101701376023712 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_alias_ports_unsup.v:38:9: Unsupported: Port as alias argument: 'a' : ... note: In instance 't.s' 38 | alias a = b; | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_alias_ports_unsup.v:38:13: Unsupported: Port as alias argument: 'b' : ... note: In instance 't.s' 38 | alias a = b; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_flag_j_hier.py0000755000542200017500000000077315101701376022226 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=['--hierarchical -j --build-jobs 2']) test.passes() verilator-5.042/test_regress/t/t_sys_plusargs_bad.v0000644000542200017500000000110415101701376023140 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; integer p_i; initial begin // BAD: Missing argument if ($value$plusargs("NOTTHERE", p_i)!==0) $stop; // BAD: Bad letter if ($value$plusargs("INT=%z", p_i)!==0) $stop; // BAD: Multi letter if ($value$plusargs("INT=%x%x", p_i)!==0) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_mailbox_bad.py0000755000542200017500000000076315101701376022235 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface_gen2.py0000755000542200017500000000073415101701376022645 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_std_randomize_bad1.py0000755000542200017500000000076615101701376023530 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_cover_line_expr.out0000644000542200017500000005367315101701376023343 0ustar mahmoudyfreeshell// // verilator_coverage annotation // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 %000001 class cls; -000001 point: comment=block hier=top.$unit::cls__Vclpkg rand int x; endclass module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; %000001 initial cyc=1; -000001 point: comment=block hier=top.t logic [63:32] cyc2; %000001 always_comb cyc2 = cyc; -000001 point: comment=block hier=top.t integer some_int; integer other_int; logic some_bool; wire t1 = cyc[0]; wire t2 = cyc[1]; wire t3 = cyc[2]; wire t4 = cyc[3]; localparam bit ONE = 1'b1; localparam bit ZERO = 1'b0; %000009 function automatic bit invert(bit x); -000009 point: comment=block hier=top.t %000009 return ~x; -000009 point: comment=block hier=top.t -000004 point: comment=(x==0) => 1 hier=top.t -000005 point: comment=(x==1) => 0 hier=top.t endfunction %000009 function automatic bit and_oper(bit a, bit b); -000009 point: comment=block hier=top.t %000009 return a & b; -000009 point: comment=block hier=top.t -000004 point: comment=(a==0) => 0 hier=top.t -000002 point: comment=(a==1 && b==1) => 1 hier=top.t -000005 point: comment=(b==0) => 0 hier=top.t endfunction localparam int NUM_INTFS = 4; intf the_intfs [NUM_INTFS-1:0] (); genvar intf_i; %000004 for (intf_i = 0; intf_i < NUM_INTFS; intf_i++) begin -000004 point: comment=block hier=top.t %000004 always_comb the_intfs[intf_i].t = cyc[intf_i]; -000004 point: comment=block hier=top.t end %000009 always @ (posedge clk) begin -000009 point: comment=block hier=top.t %000009 cyc <= cyc + 1; -000009 point: comment=block hier=top.t %000005 if ((~cyc[0] && cyc[1]) || (~cyc[2] && cyc[3])) $write(""); -000005 point: comment=else hier=top.t -000002 point: comment=(cyc[0]==0 && cyc[1]==1) => 1 hier=top.t -000002 point: comment=(cyc[0]==1 && cyc[2]==1) => 0 hier=top.t -000004 point: comment=(cyc[0]==1 && cyc[3]==0) => 0 hier=top.t -000002 point: comment=(cyc[1]==0 && cyc[2]==1) => 0 hier=top.t -000003 point: comment=(cyc[1]==0 && cyc[3]==0) => 0 hier=top.t -000002 point: comment=(cyc[2]==0 && cyc[3]==1) => 1 hier=top.t -000004 point: comment=if hier=top.t %000005 if ((~cyc2[32] && cyc2[33]) || (~cyc2[34] && cyc2[35])) $write(""); -000005 point: comment=else hier=top.t -000002 point: comment=(cyc2[32]==0 && cyc2[33]==1) => 1 hier=top.t -000002 point: comment=(cyc2[32]==1 && cyc2[34]==1) => 0 hier=top.t -000004 point: comment=(cyc2[32]==1 && cyc2[35]==0) => 0 hier=top.t -000002 point: comment=(cyc2[33]==0 && cyc2[34]==1) => 0 hier=top.t -000003 point: comment=(cyc2[33]==0 && cyc2[35]==0) => 0 hier=top.t -000002 point: comment=(cyc2[34]==0 && cyc2[35]==1) => 1 hier=top.t -000004 point: comment=if hier=top.t %000005 if ((~the_intfs[0].t && the_intfs[1].t) || (~the_intfs[2].t && the_intfs[3].t)) $write(""); -000005 point: comment=else hier=top.t -000002 point: comment=(the_intfs[0].t==0 && the_intfs[1].t==1) => 1 hier=top.t -000002 point: comment=(the_intfs[0].t==1 && the_intfs[2].t==1) => 0 hier=top.t -000004 point: comment=(the_intfs[0].t==1 && the_intfs[3].t==0) => 0 hier=top.t -000002 point: comment=(the_intfs[1].t==0 && the_intfs[2].t==1) => 0 hier=top.t -000003 point: comment=(the_intfs[1].t==0 && the_intfs[3].t==0) => 0 hier=top.t -000002 point: comment=(the_intfs[2].t==0 && the_intfs[3].t==1) => 1 hier=top.t -000004 point: comment=if hier=top.t %000005 if ((~t1 && t2) || (~t3 && t4)) $write(""); -000005 point: comment=else hier=top.t -000002 point: comment=(t1==0 && t2==1) => 1 hier=top.t -000002 point: comment=(t1==1 && t3==1) => 0 hier=top.t -000004 point: comment=(t1==1 && t4==0) => 0 hier=top.t -000002 point: comment=(t2==0 && t3==1) => 0 hier=top.t -000003 point: comment=(t2==0 && t4==0) => 0 hier=top.t -000002 point: comment=(t3==0 && t4==1) => 1 hier=top.t -000004 point: comment=if hier=top.t %000007 if (t3 && (t1 == t2)) $write(""); -000007 point: comment=else hier=top.t -000005 point: comment=((t1 == t2)==0) => 0 hier=top.t -000005 point: comment=(t3==0) => 0 hier=top.t -000002 point: comment=(t3==1 && (t1 == t2)==1) => 1 hier=top.t -000002 point: comment=if hier=top.t %000007 if (123 == (124 - 32'(t1 || t2))) $write(""); -000002 point: comment=else hier=top.t -000002 point: comment=(t1==0 && t2==0) => 0 hier=top.t -000005 point: comment=(t1==1) => 1 hier=top.t -000004 point: comment=(t2==1) => 1 hier=top.t -000007 point: comment=if hier=top.t %000009 some_int <= (t2 || t3) ? 345 : 567; -000009 point: comment=block hier=top.t -000003 point: comment=(t2==0 && t3==0) => 0 hier=top.t -000004 point: comment=(t2==1) => 1 hier=top.t -000004 point: comment=(t3==1) => 1 hier=top.t -000006 point: comment=cond_then hier=top.t -000003 point: comment=cond_else hier=top.t %000009 some_bool <= t1 && t2; -000009 point: comment=block hier=top.t -000004 point: comment=(t1==0) => 0 hier=top.t -000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t %000007 if (t1 & t2) $write(""); -000007 point: comment=else hier=top.t -000004 point: comment=(t1==0) => 0 hier=top.t -000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t -000002 point: comment=if hier=top.t %000005 if ((!t1 && t2) | (~t3 && t4)) $write(""); -000005 point: comment=else hier=top.t -000002 point: comment=(t1==0 && t2==1) => 1 hier=top.t -000002 point: comment=(t1==1 && t3==1) => 0 hier=top.t -000004 point: comment=(t1==1 && t4==0) => 0 hier=top.t -000002 point: comment=(t2==0 && t3==1) => 0 hier=top.t -000003 point: comment=(t2==0 && t4==0) => 0 hier=top.t -000002 point: comment=(t3==0 && t4==1) => 1 hier=top.t -000004 point: comment=if hier=top.t %000005 if (t1 ^ t2) $write(""); -000004 point: comment=else hier=top.t -000002 point: comment=(t1==0 && t2==0) => 0 hier=top.t -000002 point: comment=(t1==0 && t2==1) => 1 hier=top.t -000003 point: comment=(t1==1 && t2==0) => 1 hier=top.t -000002 point: comment=(t1==1 && t2==1) => 0 hier=top.t -000005 point: comment=if hier=top.t %000007 if (~(t1 & t2)) $write(""); -000002 point: comment=else hier=top.t -000004 point: comment=(t1==0) => 1 hier=top.t -000002 point: comment=(t1==1 && t2==1) => 0 hier=top.t -000005 point: comment=(t2==0) => 1 hier=top.t -000007 point: comment=if hier=top.t %000006 if (t1 -> t2) $write(""); -000003 point: comment=else hier=top.t -000004 point: comment=(t1==0) => 1 hier=top.t -000003 point: comment=(t1==1 && t2==0) => 0 hier=top.t -000004 point: comment=(t2==1) => 1 hier=top.t -000006 point: comment=if hier=top.t %000005 if (t1 <-> t2) $write(""); -000005 point: comment=else hier=top.t -000002 point: comment=(t1==0 && t2==0) => 1 hier=top.t -000002 point: comment=(t1==0 && t2==1) => 0 hier=top.t -000003 point: comment=(t1==1 && t2==0) => 0 hier=top.t -000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t -000004 point: comment=if hier=top.t %000008 if (&cyc[2:0]) $write(""); -000008 point: comment=else hier=top.t -000004 point: comment=(cyc[2:0][0]==0) => 0 hier=top.t -000001 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 1 hier=top.t -000005 point: comment=(cyc[2:0][1]==0) => 0 hier=top.t -000005 point: comment=(cyc[2:0][2]==0) => 0 hier=top.t -000001 point: comment=if hier=top.t %000009 if (&cyc[3:2]) $write(""); -000009 point: comment=else hier=top.t -000005 point: comment=(cyc[3:2][0]==0) => 0 hier=top.t -000000 point: comment=(cyc[3:2][0]==1 && cyc[3:2][1]==1) => 1 hier=top.t -000007 point: comment=(cyc[3:2][1]==0) => 0 hier=top.t -000000 point: comment=if hier=top.t %000008 if (|cyc[2:0]) $write(""); -000001 point: comment=else hier=top.t -000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 0 hier=top.t -000005 point: comment=(cyc[2:0][0]==1) => 1 hier=top.t -000004 point: comment=(cyc[2:0][1]==1) => 1 hier=top.t -000004 point: comment=(cyc[2:0][2]==1) => 1 hier=top.t -000008 point: comment=if hier=top.t %000005 if (^cyc[2:0]) $write(""); -000004 point: comment=else hier=top.t -000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 0 hier=top.t -000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==1) => 1 hier=top.t -000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==1 && cyc[2:0][2]==0) => 1 hier=top.t -000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 0 hier=top.t -000002 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 1 hier=top.t -000001 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==0 && cyc[2:0][2]==1) => 0 hier=top.t -000001 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==0) => 0 hier=top.t -000001 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 1 hier=top.t -000005 point: comment=if hier=top.t %000009 if (|cyc[2:0] || cyc[3]) $write(""); -000000 point: comment=else hier=top.t -000000 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0 && cyc[3]==0) => 0 hier=top.t -000005 point: comment=(cyc[2:0][0]==1) => 1 hier=top.t -000004 point: comment=(cyc[2:0][1]==1) => 1 hier=top.t -000004 point: comment=(cyc[2:0][2]==1) => 1 hier=top.t -000002 point: comment=(cyc[3]==1) => 1 hier=top.t -000009 point: comment=if hier=top.t %000007 if (t1 & t2 & 1'b1) $write(""); -000007 point: comment=else hier=top.t -000000 point: comment=(1'h1==0) => 0 hier=top.t -000004 point: comment=(t1==0) => 0 hier=top.t -000002 point: comment=(t1==1 && t2==1 && 1'h1==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t -000002 point: comment=if hier=top.t %000009 if (t1 & t2 & 1'b0) $write(""); -000009 point: comment=else hier=top.t -000009 point: comment=(1'h0==0) => 0 hier=top.t -000004 point: comment=(t1==0) => 0 hier=top.t -000000 point: comment=(t1==1 && t2==1 && 1'h0==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t -000000 point: comment=if hier=top.t %000007 if (t1 & t2 & ONE) $write(""); -000007 point: comment=else hier=top.t -000000 point: comment=(ONE==0) => 0 hier=top.t -000004 point: comment=(t1==0) => 0 hier=top.t -000002 point: comment=(t1==1 && t2==1 && ONE==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t -000002 point: comment=if hier=top.t %000009 if (t1 & t2 & ZERO) $write(""); -000009 point: comment=else hier=top.t -000009 point: comment=(ZERO==0) => 0 hier=top.t -000004 point: comment=(t1==0) => 0 hier=top.t -000000 point: comment=(t1==1 && t2==1 && ZERO==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t -000000 point: comment=if hier=top.t %000005 if (t1 && t2) begin -000004 point: comment=(t1==0) => 0 hier=top.t -000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t -000002 point: comment=elsif hier=top.t %000002 $write(""); -000002 point: comment=elsif hier=top.t %000005 end else if (t1 || t2) begin -000005 point: comment=if hier=top.t -000002 point: comment=else hier=top.t -000002 point: comment=(t1==0 && t2==0) => 0 hier=top.t -000003 point: comment=(t1==1) => 1 hier=top.t -000002 point: comment=(t2==1) => 1 hier=top.t %000005 $write(""); -000005 point: comment=if hier=top.t end %000007 if (invert(t1) && t2) $write(""); -000007 point: comment=else hier=top.t -000005 point: comment=(invert(t1)==0) => 0 hier=top.t -000002 point: comment=(invert(t1)==1 && t2==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t -000002 point: comment=if hier=top.t %000007 if (and_oper(t1, t2)) $write(""); -000007 point: comment=else hier=top.t -000002 point: comment=if hier=top.t %000007 if (t2 && t3) begin -000007 point: comment=else hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t -000002 point: comment=(t2==1 && t3==1) => 1 hier=top.t -000005 point: comment=(t3==0) => 0 hier=top.t -000002 point: comment=if hier=top.t %000001 if (t1 && t2) $write(""); -000001 point: comment=if hier=top.t -000001 point: comment=else hier=top.t -000001 point: comment=(t1==0) => 0 hier=top.t -000001 point: comment=(t1==1 && t2==1) => 1 hier=top.t -000000 point: comment=(t2==0) => 0 hier=top.t end %000009 if (0 == 1) begin -000009 point: comment=else hier=top.t -000000 point: comment=if hier=top.t %000000 for (int loop_var = 0; loop_var < 1; loop_var++) begin -000000 point: comment=if hier=top.t -000000 point: comment=block hier=top.t %000000 if (cyc[loop_var] && t2) $write(""); -000000 point: comment=if hier=top.t -000000 point: comment=else hier=top.t -000000 point: comment=(cyc[loop_var[4:0]+:1]==0) => 0 hier=top.t -000000 point: comment=(cyc[loop_var[4:0]+:1]==1 && t2==1) => 1 hier=top.t -000000 point: comment=(t2==0) => 0 hier=top.t end end // stop at the first layer even if there's more to find %000007 if ((cyc[3+32'(t1 && t2)+:2] == cyc[5+32'(t3 || t4)+:2]) || cyc[31]) $write(""); -000002 point: comment=else hier=top.t -000002 point: comment=((cyc[(32'sh3 + (t1 && t2))[4:0]+:2] == cyc[(32'sh5 + (t3 || t4))[4:0]+:2])==0 && cyc[31]==0) => 0 hier=top.t -000007 point: comment=((cyc[(32'sh3 + (t1 && t2))[4:0]+:2] == cyc[(32'sh5 + (t3 || t4))[4:0]+:2])==1) => 1 hier=top.t -000000 point: comment=(cyc[31]==1) => 1 hier=top.t -000007 point: comment=if hier=top.t // impossible branches and redundant terms %000008 if ((t1 && t2) && ~(t1 && t3) && (t1 || t4)) $write(""); -000008 point: comment=else hier=top.t -000003 point: comment=(t1==0 && t4==0) => 0 hier=top.t -000004 point: comment=(t1==0) => 0 hier=top.t -000000 point: comment=(t1==1 && t2==1 && t3==0 && t4==1) => 1 hier=top.t -000001 point: comment=(t1==1 && t2==1 && t3==0) => 1 hier=top.t -000002 point: comment=(t1==1 && t3==1) => 0 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t -000001 point: comment=if hier=top.t %000008 if ((cyc[0] && cyc[1]) && ~(cyc[0] && cyc[2]) && (cyc[0] || cyc[3])) $write(""); -000008 point: comment=else hier=top.t -000003 point: comment=(cyc[0]==0 && cyc[3]==0) => 0 hier=top.t -000004 point: comment=(cyc[0]==0) => 0 hier=top.t -000000 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[3]==1) => 1 hier=top.t -000001 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0) => 1 hier=top.t -000002 point: comment=(cyc[0]==1 && cyc[2]==1) => 0 hier=top.t -000005 point: comment=(cyc[1]==0) => 0 hier=top.t -000001 point: comment=if hier=top.t // demonstrate current limitations of term matching scheme %000008 if ((cyc[0] && cyc[1]) && ~(cyc[1-1] && cyc[2]) && (cyc[2-2] || cyc[3])) $write(""); -000008 point: comment=else hier=top.t -000002 point: comment=(cyc[(32'sh1 - 32'sh1)[4:0]+:1]==1 && cyc[2]==1) => 0 hier=top.t -000003 point: comment=(cyc[(32'sh2 - 32'sh2)[4:0]+:1]==0 && cyc[3]==0) => 0 hier=top.t -000004 point: comment=(cyc[0]==0) => 0 hier=top.t -000000 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[(32'sh1 - 32'sh1)[4:0]+:1]==0 && cyc[(32'sh2 - 32'sh2)[4:0]+:1]==1) => 1 hier=top.t -000000 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[(32'sh1 - 32'sh1)[4:0]+:1]==0 && cyc[3]==1) => 1 hier=top.t -000001 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[(32'sh2 - 32'sh2)[4:0]+:1]==1) => 1 hier=top.t -000000 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[3]==1) => 1 hier=top.t -000005 point: comment=(cyc[1]==0) => 0 hier=top.t -000001 point: comment=if hier=top.t //verilator coverage_off if (t1 && t2) $write(""); //verilator coverage_on %000005 if ((~t1 && t2) -000005 point: comment=else hier=top.t -000004 point: comment=if hier=top.t %000004 || -000002 point: comment=(t1==0 && t2==1) => 1 hier=top.t -000002 point: comment=(t1==1 && t3==1) => 0 hier=top.t -000004 point: comment=(t1==1 && t4==0) => 0 hier=top.t -000002 point: comment=(t2==0 && t3==1) => 0 hier=top.t -000003 point: comment=(t2==0 && t4==0) => 0 hier=top.t -000002 point: comment=(t3==0 && t4==1) => 1 hier=top.t %000004 (~t3 && t4)) $write(""); -000004 point: comment=if hier=top.t // intentionally testing wonkified expression terms %000007 if ( -000007 point: comment=else hier=top.t -000002 point: comment=if hier=top.t cyc[ 0 %000005 ] & -000004 point: comment=(cyc[0]==0) => 0 hier=top.t -000002 point: comment=(cyc[0]==1 && cyc[1]==1) => 1 hier=top.t -000005 point: comment=(cyc[1]==0) => 0 hier=top.t cyc %000002 [1]) $write(""); -000002 point: comment=if hier=top.t // for now each ternary condition is considered in isolation %000009 other_int <= t1 ? t2 ? 1 : 2 : 3; -000004 point: comment=(t1==0) => 0 hier=top.t -000005 point: comment=(t1==1) => 1 hier=top.t -000005 point: comment=cond_then hier=top.t -000004 point: comment=cond_else hier=top.t -000002 point: comment=cond_then hier=top.t -000003 point: comment=cond_else hier=top.t -000009 point: comment=block hier=top.t // no expression coverage for multi-bit expressions %000009 if ((cyc[1:0] & cyc[3:2]) == 2'b11) $write(""); -000009 point: comment=else hier=top.t -000000 point: comment=if hier=top.t // truth table is too large %000005 if (^cyc[6:0]) $write(""); -000004 point: comment=else hier=top.t -000005 point: comment=if hier=top.t // this one is too big even for t_cover_expr_max %000005 if (^cyc) $write(""); -000004 point: comment=else hier=top.t -000005 point: comment=if hier=top.t %000008 if (cyc==9) begin -000008 point: comment=else hier=top.t -000001 point: comment=if hier=top.t %000001 $write("*-* All Finished *-*\n"); -000001 point: comment=if hier=top.t %000001 $finish; -000001 point: comment=if hier=top.t end end 000010 always_comb begin +000010 point: comment=block hier=top.t %000008 if (t1 && t2) $write(""); -000008 point: comment=else hier=top.t -000005 point: comment=(t1==0) => 0 hier=top.t -000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t -000002 point: comment=if hier=top.t end logic ta, tb, tc; %000001 initial begin -000001 point: comment=block hier=top.t %000001 cls obj = new; -000001 point: comment=block hier=top.t %000001 cls null_obj = null; -000001 point: comment=block hier=top.t int q[5]; int qv[$]; %000001 q = '{1, 2, 2, 4, 3}; -000001 point: comment=block hier=top.t // lambas not handled // NB: there is a bug w/ tracing find_first (maybe lambdas in general?) // tracing_off does not work around the bug %000001 qv = q.find_first with (item[0] & item[1]); -000001 point: comment=block hier=top.t %000001 ta = '1; -000001 point: comment=block hier=top.t %000001 tb = '0; -000001 point: comment=block hier=top.t %000001 tc = '0; -000001 point: comment=block hier=top.t %000003 while (ta || tb || tc) begin -000001 point: comment=(ta==0 && tb==0 && tc==0) => 0 hier=top.t -000000 point: comment=(ta==1) => 1 hier=top.t -000000 point: comment=(tb==1) => 1 hier=top.t -000000 point: comment=(tc==1) => 1 hier=top.t -000003 point: comment=block hier=top.t %000003 tc = tb; -000003 point: comment=block hier=top.t %000003 tb = ta; -000003 point: comment=block hier=top.t %000003 ta = '0; -000003 point: comment=block hier=top.t end %000001 if (!bit'(obj.randomize() with {x < 100;})) $write(""); -000000 point: comment=else hier=top.t -000001 point: comment=if hier=top.t %000001 if (null_obj != null && null_obj.x == 5) $write(""); -000001 point: comment=else hier=top.t -000000 point: comment=if hier=top.t end sub the_sub_1 (.p(t1), .q(t2)); sub the_sub_2 (.p(t3), .q(t4)); // TODO -- non-process expressions sub the_sub_3 (.p(t1 ? t2 : t3), .q(t4)); // TODO // pragma for expr coverage off / on // investigate cover point sorting in annotated source // consider reporting don't care terms // // Branches which are statically impossible to reach are still reported. // E.g. // -000000 point: comment=(t1=1 && t2=1 && 1'h0=1) => 1 hier=top.t // These could potentially be pruned, but they currently follow suit for // what branch coverage does. Perhaps a switch should be added to not // count statically impossible things. endmodule module sub ( input p, input q ); 000030 always_comb begin +000030 point: comment=block hier=top.t.the_sub_* ~000028 if (p && q) $write(""); +000028 point: comment=else hier=top.t.the_sub_* +000017 point: comment=(p==0) => 0 hier=top.t.the_sub_* -000002 point: comment=(p==1 && q==1) => 1 hier=top.t.the_sub_* +000019 point: comment=(q==0) => 0 hier=top.t.the_sub_* -000002 point: comment=if hier=top.t.the_sub_* end endmodule interface intf(); logic t; endinterface verilator-5.042/test_regress/t/t_param_chain.py0000755000542200017500000000073415101701376022234 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_struct_port.py0000755000542200017500000000073415101701376022362 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_array_unpacked_public.v0000644000542200017500000000063615101701376024133 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by Stefan Wallentowitz. // SPDX-License-Identifier: CC0-1.0 module t(); logic din [0:15]; array_test array_test_inst(.din(din)); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule module array_test( input din [0:15] ); endmodule verilator-5.042/test_regress/t/TestSimulator.h0000644000542200017500000000605615101701376022065 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2013-2025 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "vpi_user.h" #include #include class TestSimulator { private: struct SimTypes { bool verilator = false; bool icarus = false; bool mti = false; bool ncsim = false; bool vcs = false; bool questa = false; }; s_vpi_vlog_info m_info; SimTypes m_simulators; public: TestSimulator() { vpi_get_vlog_info(&m_info); if (0 == std::strcmp(m_info.product, "Verilator")) { m_simulators.verilator = true; } else if (0 == std::strcmp(m_info.product, "Icarus Verilog")) { m_simulators.icarus = true; } else if (0 == strncmp(m_info.product, "Chronologic Simulation VCS", std::strlen("Chronologic Simulation VCS"))) { m_simulators.vcs = true; } else if (0 == strcmp(m_info.product, "ModelSim for Questa-64")) { m_simulators.questa = true; } else { printf("%%Warning: %s:%d: Unknown simulator in TestSimulator.h: %s\n", __FILE__, __LINE__, m_info.product); } } ~TestSimulator() = default; // METHORS private: static TestSimulator& singleton() { static TestSimulator s_singleton; return s_singleton; } static const SimTypes& simulators() { return singleton().m_simulators; } public: static const s_vpi_vlog_info& get_info() { return singleton().m_info; } // Simulator names static bool is_icarus() { return simulators().icarus; } static bool is_verilator() { return simulators().verilator; } static bool is_mti() { return simulators().mti; } static bool is_ncsim() { return simulators().ncsim; } static bool is_vcs() { return simulators().vcs; } static bool is_questa() { return simulators().questa; } // Simulator properties static bool is_event_driven() { return !simulators().verilator; } static bool has_get_scalar() { return !simulators().icarus; } // return test level scope static const char* top() { if (simulators().verilator || simulators().icarus || simulators().questa) { return "t"; } else { return "top.t"; } } // return absolute scope of obj static const char* rooted(const char* obj) { static std::string buf; std::ostringstream os; os << top(); if (*obj) os << "." << obj; buf = os.str(); return buf.c_str(); } }; #define VPI_HANDLE(signal) \ vpi_handle_by_name(const_cast(TestSimulator::rooted(signal)), nullptr); verilator-5.042/test_regress/t/t_time_stamp_double.py0000755000542200017500000000121115101701376023455 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = 't/t_time_stamp64.v' # Verilator before 4.033 had 'double sc_time_stamp()', make sure this still compiles test.vl_time_stamp64 = False test.compile(verilator_flags2=[]) test.execute() test.passes() verilator-5.042/test_regress/t/t_vlt_warn_ecode_bad.py0000755000542200017500000000115115101701376023565 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_vlt_warn.v" test.lint(verilator_flags2=["--lint-only t/t_vlt_warn_ecode_bad.vlt"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_comb_loop_through_unpacked_array.py0000755000542200017500000000077115101701376026554 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(verilator_flags2=["-Wno-UNOPTFLAT", "-fno-dfg"]) test.passes() verilator-5.042/test_regress/t/t_package_import_override.v0000644000542200017500000000153415101701376024467 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package pkg; typedef enum logic [1:0] { INT, BLA, DUMMY } t_shadowed_enum; endpackage module sub import pkg::*; ( input logic INT, // This is also in the pkg::t_shadowed_enum, but it shadows it output logic dummy_out ); assign dummy_out = !INT; endmodule module t; logic my_wire; logic dummy_out; sub i_sub ( .INT(my_wire), .dummy_out(dummy_out) ); initial begin my_wire = 1'b0; repeat (2) begin my_wire = ~my_wire; #1ns; $display("my_wire = %b, dummy_out = %b", my_wire, dummy_out); end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_select_runtime_range.v0000644000542200017500000000406015101701376023776 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; reg [43:0] mi; reg [5:0] index; integer indexi; reg read; initial begin // Static mi = 44'b01010101010101010101010101010101010101010101; if (mi[0] !== 1'b1) $stop; if (mi[1 -: 2] !== 2'b01) $stop; `ifdef VERILATOR // verilator lint_off SELRANGE if (mi[-1] !== 1'bx && mi[-1] !== 1'b0) $stop; if (mi[0 -: 2] !== 2'b1x && 1'b0) $stop; if (mi[-1 -: 2] !== 2'bxx && 1'b0) $stop; // verilator lint_on SELRANGE `else if (mi[-1] !== 1'bx) $stop; if (mi[0 -: 2] !== 2'b1x) $stop; if (mi[-1 -: 2] !== 2'bxx) $stop; `endif end integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin mi = 44'h123; end if (cyc==2) begin index = 6'd43; indexi = 43; end if (cyc==3) begin read = mi[index]; if (read!==1'b0) $stop; read = mi[indexi]; if (read!==1'b0) $stop; end if (cyc==4) begin index = 6'd44; indexi = 44; end if (cyc==5) begin read = mi[index]; $display("-Illegal read value: %x", read); //if (read!==1'b1 && read!==1'bx) $stop; read = mi[indexi]; $display("-Illegal read value: %x", read); //if (read!==1'b1 && read!==1'bx) $stop; end if (cyc==6) begin indexi = -1; end if (cyc==7) begin read = mi[indexi]; $display("-Illegal read value: %x", read); //if (read!==1'b1 && read!==1'bx) $stop; end if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.042/test_regress/t/t_func_const_packed_struct_bad.py0000755000542200017500000000076615101701376025661 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface_ref_trace_noinl.out0000644000542200017500000004706515101701376025327 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $var wire 1 0 clk $end $scope module t $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $scope module intf_1 $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 $ value [31:0] $end $scope module the_struct $end $var wire 32 % val100 [31:0] $end $var wire 32 & val200 [31:0] $end $upscope $end $scope module inner $end $var wire 32 # cyc [31:0] $end $var wire 32 1 value [31:0] $end $upscope $end $upscope $end $scope module intf_2 $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 ' value [31:0] $end $scope module the_struct $end $var wire 32 ( val100 [31:0] $end $var wire 32 ) val200 [31:0] $end $upscope $end $scope module inner $end $var wire 32 # cyc [31:0] $end $var wire 32 2 value [31:0] $end $upscope $end $upscope $end $scope module s1 $end $scope module intf_for_struct $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 $ value [31:0] $end $scope module the_struct $end $var wire 32 % val100 [31:0] $end $var wire 32 & val200 [31:0] $end $upscope $end $scope module inner $end $var wire 32 # cyc [31:0] $end $var wire 32 1 value [31:0] $end $upscope $end $upscope $end $upscope $end $scope module s2 $end $scope module intf_for_struct $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 ' value [31:0] $end $scope module the_struct $end $var wire 32 ( val100 [31:0] $end $var wire 32 ) val200 [31:0] $end $upscope $end $scope module inner $end $var wire 32 # cyc [31:0] $end $var wire 32 2 value [31:0] $end $upscope $end $upscope $end $upscope $end $scope module c1 $end $scope module intf_for_check $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 $ value [31:0] $end $scope module the_struct $end $var wire 32 % val100 [31:0] $end $var wire 32 & val200 [31:0] $end $upscope $end $scope module inner $end $var wire 32 # cyc [31:0] $end $var wire 32 1 value [31:0] $end $upscope $end $upscope $end $upscope $end $scope module c2 $end $scope module intf_for_check $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 ' value [31:0] $end $scope module the_struct $end $var wire 32 ( val100 [31:0] $end $var wire 32 ) val200 [31:0] $end $upscope $end $scope module inner $end $var wire 32 # cyc [31:0] $end $var wire 32 2 value [31:0] $end $upscope $end $upscope $end $upscope $end $scope module a $end $scope module intf_one $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 $ value [31:0] $end $scope module the_struct $end $var wire 32 % val100 [31:0] $end $var wire 32 & val200 [31:0] $end $upscope $end $scope module inner $end $var wire 32 # cyc [31:0] $end $var wire 32 1 value [31:0] $end $upscope $end $upscope $end $scope module intf_two $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 ' value [31:0] $end $scope module the_struct $end $var wire 32 ( val100 [31:0] $end $var wire 32 ) val200 [31:0] $end $upscope $end $scope module inner $end $var wire 32 # cyc [31:0] $end $var wire 32 2 value [31:0] $end $upscope $end $upscope $end $scope module intf_in_sub_all $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 * value [31:0] $end $scope module the_struct $end $var wire 32 + val100 [31:0] $end $var wire 32 , val200 [31:0] $end $upscope $end $scope module inner $end $var wire 32 # cyc [31:0] $end $var wire 32 3 value [31:0] $end $upscope $end $upscope $end $scope module ac1 $end $scope module intf_for_check $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 $ value [31:0] $end $scope module the_struct $end $var wire 32 % val100 [31:0] $end $var wire 32 & val200 [31:0] $end $upscope $end $scope module inner $end $var wire 32 # cyc [31:0] $end $var wire 32 1 value [31:0] $end $upscope $end $upscope $end $upscope $end $scope module ac2 $end $scope module intf_for_check $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 ' value [31:0] $end $scope module the_struct $end $var wire 32 ( val100 [31:0] $end $var wire 32 ) val200 [31:0] $end $upscope $end $scope module inner $end $var wire 32 # cyc [31:0] $end $var wire 32 2 value [31:0] $end $upscope $end $upscope $end $upscope $end $scope module as3 $end $scope module intf_for_struct $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 * value [31:0] $end $scope module the_struct $end $var wire 32 + val100 [31:0] $end $var wire 32 , val200 [31:0] $end $upscope $end $scope module inner $end $var wire 32 # cyc [31:0] $end $var wire 32 3 value [31:0] $end $upscope $end $upscope $end $upscope $end $scope module ac3 $end $scope module intf_for_check $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 * value [31:0] $end $scope module the_struct $end $var wire 32 + val100 [31:0] $end $var wire 32 , val200 [31:0] $end $upscope $end $scope module inner $end $var wire 32 # cyc [31:0] $end $var wire 32 3 value [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module abcdefghijklmnopqrstuvwxyz $end $scope module intf_one $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 ' value [31:0] $end $scope module the_struct $end $var wire 32 ( val100 [31:0] $end $var wire 32 ) val200 [31:0] $end $upscope $end $scope module inner $end $var wire 32 # cyc [31:0] $end $var wire 32 2 value [31:0] $end $upscope $end $upscope $end $scope module intf_two $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 $ value [31:0] $end $scope module the_struct $end $var wire 32 % val100 [31:0] $end $var wire 32 & val200 [31:0] $end $upscope $end $scope module inner $end $var wire 32 # cyc [31:0] $end $var wire 32 1 value [31:0] $end $upscope $end $upscope $end $scope module intf_in_sub_all $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 - value [31:0] $end $scope module the_struct $end $var wire 32 . val100 [31:0] $end $var wire 32 / val200 [31:0] $end $upscope $end $scope module inner $end $var wire 32 # cyc [31:0] $end $var wire 32 4 value [31:0] $end $upscope $end $upscope $end $scope module ac1 $end $scope module intf_for_check $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 ' value [31:0] $end $scope module the_struct $end $var wire 32 ( val100 [31:0] $end $var wire 32 ) val200 [31:0] $end $upscope $end $scope module inner $end $var wire 32 # cyc [31:0] $end $var wire 32 2 value [31:0] $end $upscope $end $upscope $end $upscope $end $scope module ac2 $end $scope module intf_for_check $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 $ value [31:0] $end $scope module the_struct $end $var wire 32 % val100 [31:0] $end $var wire 32 & val200 [31:0] $end $upscope $end $scope module inner $end $var wire 32 # cyc [31:0] $end $var wire 32 1 value [31:0] $end $upscope $end $upscope $end $upscope $end $scope module as3 $end $scope module intf_for_struct $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 - value [31:0] $end $scope module the_struct $end $var wire 32 . val100 [31:0] $end $var wire 32 / val200 [31:0] $end $upscope $end $scope module inner $end $var wire 32 # cyc [31:0] $end $var wire 32 4 value [31:0] $end $upscope $end $upscope $end $upscope $end $scope module ac3 $end $scope module intf_for_check $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 - value [31:0] $end $scope module the_struct $end $var wire 32 . val100 [31:0] $end $var wire 32 / val200 [31:0] $end $upscope $end $scope module inner $end $var wire 32 # cyc [31:0] $end $var wire 32 4 value [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 b00000000000000000000000000000000 # b00000000000000000000000000000001 $ b00000000000000000000000001100101 % b00000000000000000000000011001001 & b00000000000000000000000000000010 ' b00000000000000000000000001100110 ( b00000000000000000000000011001010 ) b00000000000000000000001111101001 * b00000000000000000000010001001101 + b00000000000000000000010010110001 , b00000000000000000000001111101010 - b00000000000000000000010001001110 . b00000000000000000000010010110010 / 00 b00000000000000000000000000000000 1 b00000000000000000000000000000000 2 b00000000000000000000000000000000 3 b00000000000000000000000000000000 4 #10 b00000000000000000000000000000001 # b00000000000000000000000000000010 $ b00000000000000000000000001100110 % b00000000000000000000000011001010 & b00000000000000000000000000000011 ' b00000000000000000000000001100111 ( b00000000000000000000000011001011 ) b00000000000000000000001111101010 * b00000000000000000000010001001110 + b00000000000000000000010010110010 , b00000000000000000000001111101011 - b00000000000000000000010001001111 . b00000000000000000000010010110011 / 10 #15 00 #20 b00000000000000000000000000000010 # b00000000000000000000000000000011 $ b00000000000000000000000001100111 % b00000000000000000000000011001011 & b00000000000000000000000000000100 ' b00000000000000000000000001101000 ( b00000000000000000000000011001100 ) b00000000000000000000001111101011 * b00000000000000000000010001001111 + b00000000000000000000010010110011 , b00000000000000000000001111101100 - b00000000000000000000010001010000 . b00000000000000000000010010110100 / 10 #25 00 #30 b00000000000000000000000000000011 # b00000000000000000000000000000100 $ b00000000000000000000000001101000 % b00000000000000000000000011001100 & b00000000000000000000000000000101 ' b00000000000000000000000001101001 ( b00000000000000000000000011001101 ) b00000000000000000000001111101100 * b00000000000000000000010001010000 + b00000000000000000000010010110100 , b00000000000000000000001111101101 - b00000000000000000000010001010001 . b00000000000000000000010010110101 / 10 #35 00 #40 b00000000000000000000000000000100 # b00000000000000000000000000000101 $ b00000000000000000000000001101001 % b00000000000000000000000011001101 & b00000000000000000000000000000110 ' b00000000000000000000000001101010 ( b00000000000000000000000011001110 ) b00000000000000000000001111101101 * b00000000000000000000010001010001 + b00000000000000000000010010110101 , b00000000000000000000001111101110 - b00000000000000000000010001010010 . b00000000000000000000010010110110 / 10 #45 00 #50 b00000000000000000000000000000101 # b00000000000000000000000000000110 $ b00000000000000000000000001101010 % b00000000000000000000000011001110 & b00000000000000000000000000000111 ' b00000000000000000000000001101011 ( b00000000000000000000000011001111 ) b00000000000000000000001111101110 * b00000000000000000000010001010010 + b00000000000000000000010010110110 , b00000000000000000000001111101111 - b00000000000000000000010001010011 . b00000000000000000000010010110111 / 10 #55 00 #60 b00000000000000000000000000000110 # b00000000000000000000000000000111 $ b00000000000000000000000001101011 % b00000000000000000000000011001111 & b00000000000000000000000000001000 ' b00000000000000000000000001101100 ( b00000000000000000000000011010000 ) b00000000000000000000001111101111 * b00000000000000000000010001010011 + b00000000000000000000010010110111 , b00000000000000000000001111110000 - b00000000000000000000010001010100 . b00000000000000000000010010111000 / 10 #65 00 #70 b00000000000000000000000000000111 # b00000000000000000000000000001000 $ b00000000000000000000000001101100 % b00000000000000000000000011010000 & b00000000000000000000000000001001 ' b00000000000000000000000001101101 ( b00000000000000000000000011010001 ) b00000000000000000000001111110000 * b00000000000000000000010001010100 + b00000000000000000000010010111000 , b00000000000000000000001111110001 - b00000000000000000000010001010101 . b00000000000000000000010010111001 / 10 #75 00 #80 b00000000000000000000000000001000 # b00000000000000000000000000001001 $ b00000000000000000000000001101101 % b00000000000000000000000011010001 & b00000000000000000000000000001010 ' b00000000000000000000000001101110 ( b00000000000000000000000011010010 ) b00000000000000000000001111110001 * b00000000000000000000010001010101 + b00000000000000000000010010111001 , b00000000000000000000001111110010 - b00000000000000000000010001010110 . b00000000000000000000010010111010 / 10 #85 00 #90 b00000000000000000000000000001001 # b00000000000000000000000000001010 $ b00000000000000000000000001101110 % b00000000000000000000000011010010 & b00000000000000000000000000001011 ' b00000000000000000000000001101111 ( b00000000000000000000000011010011 ) b00000000000000000000001111110010 * b00000000000000000000010001010110 + b00000000000000000000010010111010 , b00000000000000000000001111110011 - b00000000000000000000010001010111 . b00000000000000000000010010111011 / 10 #95 00 #100 b00000000000000000000000000001010 # b00000000000000000000000000001011 $ b00000000000000000000000001101111 % b00000000000000000000000011010011 & b00000000000000000000000000001100 ' b00000000000000000000000001110000 ( b00000000000000000000000011010100 ) b00000000000000000000001111110011 * b00000000000000000000010001010111 + b00000000000000000000010010111011 , b00000000000000000000001111110100 - b00000000000000000000010001011000 . b00000000000000000000010010111100 / 10 #105 00 #110 b00000000000000000000000000001011 # b00000000000000000000000000001100 $ b00000000000000000000000001110000 % b00000000000000000000000011010100 & b00000000000000000000000000001101 ' b00000000000000000000000001110001 ( b00000000000000000000000011010101 ) b00000000000000000000001111110100 * b00000000000000000000010001011000 + b00000000000000000000010010111100 , b00000000000000000000001111110101 - b00000000000000000000010001011001 . b00000000000000000000010010111101 / 10 #115 00 #120 b00000000000000000000000000001100 # b00000000000000000000000000001101 $ b00000000000000000000000001110001 % b00000000000000000000000011010101 & b00000000000000000000000000001110 ' b00000000000000000000000001110010 ( b00000000000000000000000011010110 ) b00000000000000000000001111110101 * b00000000000000000000010001011001 + b00000000000000000000010010111101 , b00000000000000000000001111110110 - b00000000000000000000010001011010 . b00000000000000000000010010111110 / 10 #125 00 #130 b00000000000000000000000000001101 # b00000000000000000000000000001110 $ b00000000000000000000000001110010 % b00000000000000000000000011010110 & b00000000000000000000000000001111 ' b00000000000000000000000001110011 ( b00000000000000000000000011010111 ) b00000000000000000000001111110110 * b00000000000000000000010001011010 + b00000000000000000000010010111110 , b00000000000000000000001111110111 - b00000000000000000000010001011011 . b00000000000000000000010010111111 / 10 #135 00 #140 b00000000000000000000000000001110 # b00000000000000000000000000001111 $ b00000000000000000000000001110011 % b00000000000000000000000011010111 & b00000000000000000000000000010000 ' b00000000000000000000000001110100 ( b00000000000000000000000011011000 ) b00000000000000000000001111110111 * b00000000000000000000010001011011 + b00000000000000000000010010111111 , b00000000000000000000001111111000 - b00000000000000000000010001011100 . b00000000000000000000010011000000 / 10 #145 00 #150 b00000000000000000000000000001111 # b00000000000000000000000000010000 $ b00000000000000000000000001110100 % b00000000000000000000000011011000 & b00000000000000000000000000010001 ' b00000000000000000000000001110101 ( b00000000000000000000000011011001 ) b00000000000000000000001111111000 * b00000000000000000000010001011100 + b00000000000000000000010011000000 , b00000000000000000000001111111001 - b00000000000000000000010001011101 . b00000000000000000000010011000001 / 10 #155 00 #160 b00000000000000000000000000010000 # b00000000000000000000000000010001 $ b00000000000000000000000001110101 % b00000000000000000000000011011001 & b00000000000000000000000000010010 ' b00000000000000000000000001110110 ( b00000000000000000000000011011010 ) b00000000000000000000001111111001 * b00000000000000000000010001011101 + b00000000000000000000010011000001 , b00000000000000000000001111111010 - b00000000000000000000010001011110 . b00000000000000000000010011000010 / 10 #165 00 #170 b00000000000000000000000000010001 # b00000000000000000000000000010010 $ b00000000000000000000000001110110 % b00000000000000000000000011011010 & b00000000000000000000000000010011 ' b00000000000000000000000001110111 ( b00000000000000000000000011011011 ) b00000000000000000000001111111010 * b00000000000000000000010001011110 + b00000000000000000000010011000010 , b00000000000000000000001111111011 - b00000000000000000000010001011111 . b00000000000000000000010011000011 / 10 #175 00 #180 b00000000000000000000000000010010 # b00000000000000000000000000010011 $ b00000000000000000000000001110111 % b00000000000000000000000011011011 & b00000000000000000000000000010100 ' b00000000000000000000000001111000 ( b00000000000000000000000011011100 ) b00000000000000000000001111111011 * b00000000000000000000010001011111 + b00000000000000000000010011000011 , b00000000000000000000001111111100 - b00000000000000000000010001100000 . b00000000000000000000010011000100 / 10 #185 00 #190 b00000000000000000000000000010011 # b00000000000000000000000000010100 $ b00000000000000000000000001111000 % b00000000000000000000000011011100 & b00000000000000000000000000010101 ' b00000000000000000000000001111001 ( b00000000000000000000000011011101 ) b00000000000000000000001111111100 * b00000000000000000000010001100000 + b00000000000000000000010011000100 , b00000000000000000000001111111101 - b00000000000000000000010001100001 . b00000000000000000000010011000101 / 10 #195 00 #200 b00000000000000000000000000010100 # b00000000000000000000000000010101 $ b00000000000000000000000001111001 % b00000000000000000000000011011101 & b00000000000000000000000000010110 ' b00000000000000000000000001111010 ( b00000000000000000000000011011110 ) b00000000000000000000001111111101 * b00000000000000000000010001100001 + b00000000000000000000010011000101 , b00000000000000000000001111111110 - b00000000000000000000010001100010 . b00000000000000000000010011000110 / 10 #205 00 #210 b00000000000000000000000000010101 # b00000000000000000000000000010110 $ b00000000000000000000000001111010 % b00000000000000000000000011011110 & b00000000000000000000000000010111 ' b00000000000000000000000001111011 ( b00000000000000000000000011011111 ) b00000000000000000000001111111110 * b00000000000000000000010001100010 + b00000000000000000000010011000110 , b00000000000000000000001111111111 - b00000000000000000000010001100011 . b00000000000000000000010011000111 / 10 verilator-5.042/test_regress/t/t_opt_dead_enumpkg.py0000755000542200017500000000073415101701376023277 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_config_work.out0000644000542200017500000000021715101701376022451 0ustar mahmoudyfreeshell*-* All Finished *-* liba:m1 %m=t.u_1 %l=liba.m1 liba:m3 %m=t.u_1.u_13 %l=liba.m3 libb:m2 %m=t.u_2 %l=libb.m2 libb:m3 %m=t.u_2.u_23 %l=libb.m3 verilator-5.042/test_regress/t/t_dpi_arg_output_unpack__Dpi.out0000644000542200017500000003126215101701376025467 0ustar mahmoudyfreeshell// Verilated -*- C++ -*- // DESCRIPTION: Verilator output: Prototypes for DPI import and export functions. // // Verilator includes this file in all generated .cpp files that use DPI functions. // Manually include this file where DPI .c import functions are declared to ensure // the C functions match the expectations of the DPI imports. #ifndef VERILATED_VT_DPI_ARG_OUTPUT_UNPACK__DPI_H_ #define VERILATED_VT_DPI_ARG_OUTPUT_UNPACK__DPI_H_ // guard #include "svdpi.h" #ifdef __cplusplus extern "C" { #endif // DPI EXPORTS extern void e_bit121_0d(svBitVecVal* val); extern void e_bit121_1d(svBitVecVal* val); extern void e_bit121_1d1(svBitVecVal* val); extern void e_bit121_2d(svBitVecVal* val); extern void e_bit121_2d1(svBitVecVal* val); extern void e_bit121_3d(svBitVecVal* val); extern void e_bit121_3d1(svBitVecVal* val); extern void e_bit1_0d(svBit* val); extern void e_bit1_1d(svBit* val); extern void e_bit1_1d1(svBit* val); extern void e_bit1_2d(svBit* val); extern void e_bit1_2d1(svBit* val); extern void e_bit1_3d(svBit* val); extern void e_bit1_3d1(svBit* val); extern void e_bit7_0d(svBitVecVal* val); extern void e_bit7_1d(svBitVecVal* val); extern void e_bit7_1d1(svBitVecVal* val); extern void e_bit7_2d(svBitVecVal* val); extern void e_bit7_2d1(svBitVecVal* val); extern void e_bit7_3d(svBitVecVal* val); extern void e_bit7_3d1(svBitVecVal* val); extern void e_byte_0d(char* val); extern void e_byte_1d(char* val); extern void e_byte_1d1(char* val); extern void e_byte_2d(char* val); extern void e_byte_2d1(char* val); extern void e_byte_3d(char* val); extern void e_byte_3d1(char* val); extern void e_byte_unsigned_0d(unsigned char* val); extern void e_byte_unsigned_1d(unsigned char* val); extern void e_byte_unsigned_1d1(unsigned char* val); extern void e_byte_unsigned_2d(unsigned char* val); extern void e_byte_unsigned_2d1(unsigned char* val); extern void e_byte_unsigned_3d(unsigned char* val); extern void e_byte_unsigned_3d1(unsigned char* val); extern void e_chandle_0d(void** val); extern void e_chandle_1d(void** val); extern void e_chandle_1d1(void** val); extern void e_chandle_2d(void** val); extern void e_chandle_2d1(void** val); extern void e_chandle_3d(void** val); extern void e_chandle_3d1(void** val); extern void e_int_0d(int* val); extern void e_int_1d(int* val); extern void e_int_1d1(int* val); extern void e_int_2d(int* val); extern void e_int_2d1(int* val); extern void e_int_3d(int* val); extern void e_int_3d1(int* val); extern void e_int_unsigned_0d(unsigned int* val); extern void e_int_unsigned_1d(unsigned int* val); extern void e_int_unsigned_1d1(unsigned int* val); extern void e_int_unsigned_2d(unsigned int* val); extern void e_int_unsigned_2d1(unsigned int* val); extern void e_int_unsigned_3d(unsigned int* val); extern void e_int_unsigned_3d1(unsigned int* val); extern void e_integer_0d(svLogicVecVal* val); extern void e_integer_1d(svLogicVecVal* val); extern void e_integer_1d1(svLogicVecVal* val); extern void e_integer_2d(svLogicVecVal* val); extern void e_integer_2d1(svLogicVecVal* val); extern void e_integer_3d(svLogicVecVal* val); extern void e_integer_3d1(svLogicVecVal* val); extern void e_logic121_0d(svLogicVecVal* val); extern void e_logic121_1d(svLogicVecVal* val); extern void e_logic121_1d1(svLogicVecVal* val); extern void e_logic121_2d(svLogicVecVal* val); extern void e_logic121_2d1(svLogicVecVal* val); extern void e_logic121_3d(svLogicVecVal* val); extern void e_logic121_3d1(svLogicVecVal* val); extern void e_logic1_0d(svLogic* val); extern void e_logic1_1d(svLogic* val); extern void e_logic1_1d1(svLogic* val); extern void e_logic1_2d(svLogic* val); extern void e_logic1_2d1(svLogic* val); extern void e_logic1_3d(svLogic* val); extern void e_logic1_3d1(svLogic* val); extern void e_logic7_0d(svLogicVecVal* val); extern void e_logic7_1d(svLogicVecVal* val); extern void e_logic7_1d1(svLogicVecVal* val); extern void e_logic7_2d(svLogicVecVal* val); extern void e_logic7_2d1(svLogicVecVal* val); extern void e_logic7_3d(svLogicVecVal* val); extern void e_logic7_3d1(svLogicVecVal* val); extern void e_longint_0d(long long* val); extern void e_longint_1d(long long* val); extern void e_longint_1d1(long long* val); extern void e_longint_2d(long long* val); extern void e_longint_2d1(long long* val); extern void e_longint_3d(long long* val); extern void e_longint_3d1(long long* val); extern void e_longint_unsigned_0d(unsigned long long* val); extern void e_longint_unsigned_1d(unsigned long long* val); extern void e_longint_unsigned_1d1(unsigned long long* val); extern void e_longint_unsigned_2d(unsigned long long* val); extern void e_longint_unsigned_2d1(unsigned long long* val); extern void e_longint_unsigned_3d(unsigned long long* val); extern void e_longint_unsigned_3d1(unsigned long long* val); extern void e_pack_struct_0d(svLogicVecVal* val); extern void e_pack_struct_1d(svLogicVecVal* val); extern void e_pack_struct_1d1(svLogicVecVal* val); extern void e_pack_struct_2d(svLogicVecVal* val); extern void e_pack_struct_2d1(svLogicVecVal* val); extern void e_pack_struct_3d(svLogicVecVal* val); extern void e_pack_struct_3d1(svLogicVecVal* val); extern void e_real_0d(double* val); extern void e_real_1d(double* val); extern void e_real_1d1(double* val); extern void e_real_2d(double* val); extern void e_real_2d1(double* val); extern void e_real_3d(double* val); extern void e_real_3d1(double* val); extern void e_shortint_0d(short* val); extern void e_shortint_1d(short* val); extern void e_shortint_1d1(short* val); extern void e_shortint_2d(short* val); extern void e_shortint_2d1(short* val); extern void e_shortint_3d(short* val); extern void e_shortint_3d1(short* val); extern void e_shortint_unsigned_0d(unsigned short* val); extern void e_shortint_unsigned_1d(unsigned short* val); extern void e_shortint_unsigned_1d1(unsigned short* val); extern void e_shortint_unsigned_2d(unsigned short* val); extern void e_shortint_unsigned_2d1(unsigned short* val); extern void e_shortint_unsigned_3d(unsigned short* val); extern void e_shortint_unsigned_3d1(unsigned short* val); extern void e_string_0d(const char** val); extern void e_string_1d(const char** val); extern void e_string_1d1(const char** val); extern void e_string_2d(const char** val); extern void e_string_2d1(const char** val); extern void e_string_3d(const char** val); extern void e_string_3d1(const char** val); extern void e_time_0d(svLogicVecVal* val); extern void e_time_1d(svLogicVecVal* val); extern void e_time_1d1(svLogicVecVal* val); extern void e_time_2d(svLogicVecVal* val); extern void e_time_2d1(svLogicVecVal* val); extern void e_time_3d(svLogicVecVal* val); extern void e_time_3d1(svLogicVecVal* val); // DPI IMPORTS extern void check_exports(); extern void* get_non_null(); extern void i_bit121_0d(svBitVecVal* val); extern void i_bit121_1d(svBitVecVal* val); extern void i_bit121_1d1(svBitVecVal* val); extern void i_bit121_2d(svBitVecVal* val); extern void i_bit121_2d1(svBitVecVal* val); extern void i_bit121_3d(svBitVecVal* val); extern void i_bit121_3d1(svBitVecVal* val); extern void i_bit1_0d(svBit* val); extern void i_bit1_1d(svBit* val); extern void i_bit1_1d1(svBit* val); extern void i_bit1_2d(svBit* val); extern void i_bit1_2d1(svBit* val); extern void i_bit1_3d(svBit* val); extern void i_bit1_3d1(svBit* val); extern void i_bit7_0d(svBitVecVal* val); extern void i_bit7_1d(svBitVecVal* val); extern void i_bit7_1d1(svBitVecVal* val); extern void i_bit7_2d(svBitVecVal* val); extern void i_bit7_2d1(svBitVecVal* val); extern void i_bit7_3d(svBitVecVal* val); extern void i_bit7_3d1(svBitVecVal* val); extern void i_byte_0d(char* val); extern void i_byte_1d(char* val); extern void i_byte_1d1(char* val); extern void i_byte_2d(char* val); extern void i_byte_2d1(char* val); extern void i_byte_3d(char* val); extern void i_byte_3d1(char* val); extern void i_byte_unsigned_0d(unsigned char* val); extern void i_byte_unsigned_1d(unsigned char* val); extern void i_byte_unsigned_1d1(unsigned char* val); extern void i_byte_unsigned_2d(unsigned char* val); extern void i_byte_unsigned_2d1(unsigned char* val); extern void i_byte_unsigned_3d(unsigned char* val); extern void i_byte_unsigned_3d1(unsigned char* val); extern void i_chandle_0d(void** val); extern void i_chandle_1d(void** val); extern void i_chandle_1d1(void** val); extern void i_chandle_2d(void** val); extern void i_chandle_2d1(void** val); extern void i_chandle_3d(void** val); extern void i_chandle_3d1(void** val); extern void i_int_0d(int* val); extern void i_int_1d(int* val); extern void i_int_1d1(int* val); extern void i_int_2d(int* val); extern void i_int_2d1(int* val); extern void i_int_3d(int* val); extern void i_int_3d1(int* val); extern void i_int_unsigned_0d(unsigned int* val); extern void i_int_unsigned_1d(unsigned int* val); extern void i_int_unsigned_1d1(unsigned int* val); extern void i_int_unsigned_2d(unsigned int* val); extern void i_int_unsigned_2d1(unsigned int* val); extern void i_int_unsigned_3d(unsigned int* val); extern void i_int_unsigned_3d1(unsigned int* val); extern void i_integer_0d(svLogicVecVal* val); extern void i_integer_1d(svLogicVecVal* val); extern void i_integer_1d1(svLogicVecVal* val); extern void i_integer_2d(svLogicVecVal* val); extern void i_integer_2d1(svLogicVecVal* val); extern void i_integer_3d(svLogicVecVal* val); extern void i_integer_3d1(svLogicVecVal* val); extern void i_logic121_0d(svLogicVecVal* val); extern void i_logic121_1d(svLogicVecVal* val); extern void i_logic121_1d1(svLogicVecVal* val); extern void i_logic121_2d(svLogicVecVal* val); extern void i_logic121_2d1(svLogicVecVal* val); extern void i_logic121_3d(svLogicVecVal* val); extern void i_logic121_3d1(svLogicVecVal* val); extern void i_logic1_0d(svLogic* val); extern void i_logic1_1d(svLogic* val); extern void i_logic1_1d1(svLogic* val); extern void i_logic1_2d(svLogic* val); extern void i_logic1_2d1(svLogic* val); extern void i_logic1_3d(svLogic* val); extern void i_logic1_3d1(svLogic* val); extern void i_logic7_0d(svLogicVecVal* val); extern void i_logic7_1d(svLogicVecVal* val); extern void i_logic7_1d1(svLogicVecVal* val); extern void i_logic7_2d(svLogicVecVal* val); extern void i_logic7_2d1(svLogicVecVal* val); extern void i_logic7_3d(svLogicVecVal* val); extern void i_logic7_3d1(svLogicVecVal* val); extern void i_longint_0d(long long* val); extern void i_longint_1d(long long* val); extern void i_longint_1d1(long long* val); extern void i_longint_2d(long long* val); extern void i_longint_2d1(long long* val); extern void i_longint_3d(long long* val); extern void i_longint_3d1(long long* val); extern void i_longint_unsigned_0d(unsigned long long* val); extern void i_longint_unsigned_1d(unsigned long long* val); extern void i_longint_unsigned_1d1(unsigned long long* val); extern void i_longint_unsigned_2d(unsigned long long* val); extern void i_longint_unsigned_2d1(unsigned long long* val); extern void i_longint_unsigned_3d(unsigned long long* val); extern void i_longint_unsigned_3d1(unsigned long long* val); extern void i_pack_struct_0d(svLogicVecVal* val); extern void i_pack_struct_1d(svLogicVecVal* val); extern void i_pack_struct_1d1(svLogicVecVal* val); extern void i_pack_struct_2d(svLogicVecVal* val); extern void i_pack_struct_2d1(svLogicVecVal* val); extern void i_pack_struct_3d(svLogicVecVal* val); extern void i_pack_struct_3d1(svLogicVecVal* val); extern void i_real_0d(double* val); extern void i_real_1d(double* val); extern void i_real_1d1(double* val); extern void i_real_2d(double* val); extern void i_real_2d1(double* val); extern void i_real_3d(double* val); extern void i_real_3d1(double* val); extern void i_shortint_0d(short* val); extern void i_shortint_1d(short* val); extern void i_shortint_1d1(short* val); extern void i_shortint_2d(short* val); extern void i_shortint_2d1(short* val); extern void i_shortint_3d(short* val); extern void i_shortint_3d1(short* val); extern void i_shortint_unsigned_0d(unsigned short* val); extern void i_shortint_unsigned_1d(unsigned short* val); extern void i_shortint_unsigned_1d1(unsigned short* val); extern void i_shortint_unsigned_2d(unsigned short* val); extern void i_shortint_unsigned_2d1(unsigned short* val); extern void i_shortint_unsigned_3d(unsigned short* val); extern void i_shortint_unsigned_3d1(unsigned short* val); extern void i_string_0d(const char** val); extern void i_string_1d(const char** val); extern void i_string_1d1(const char** val); extern void i_string_2d(const char** val); extern void i_string_2d1(const char** val); extern void i_string_3d(const char** val); extern void i_string_3d1(const char** val); extern void i_time_0d(svLogicVecVal* val); extern void i_time_1d(svLogicVecVal* val); extern void i_time_1d1(svLogicVecVal* val); extern void i_time_2d(svLogicVecVal* val); extern void i_time_2d1(svLogicVecVal* val); extern void i_time_3d(svLogicVecVal* val); extern void i_time_3d1(svLogicVecVal* val); #ifdef __cplusplus } #endif #endif // guard verilator-5.042/test_regress/t/t_type.py0000755000542200017500000000073415101701376020753 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_property_sexpr_cov.v0000644000542200017500000000223115101701376023552 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ // Inputs clk ); input clk; bit [3:0] val = 0; event e1; event e2; integer cyc = 1; always @(negedge clk) begin val <= 4'(cyc % 4); if (cyc >= 0 && cyc <= 4) begin ->e1; `ifdef TEST_VERBOSE $display("[%0t] triggered e1", $time); `endif end if (cyc >= 5 && cyc <= 10) begin ->e2; `ifdef TEST_VERBOSE $display("[%0t] triggered e2", $time); `endif end `ifdef TEST_VERBOSE $display("cyc=%0d val=%0d", cyc, val); `endif cyc <= cyc + 1; if (cyc == 100) begin $write("*-* All Finished *-*\n"); $finish; end end cover property (@(e1) ##1 val[0]) $display("[%0t] cover property, fileline:%0d", $time, `__LINE__); cover property (@(e2) not ##1 val[1]) $display("[%0t] not cover property, fileline:%0d", $time, `__LINE__); cover property (@(posedge clk) ##3 val[0] && val[1]) $display("[%0t] concurrent cover, fileline:%0d", $time, `__LINE__); endmodule verilator-5.042/test_regress/t/t_struct_contents_bad.out0000644000542200017500000000504315101701376024213 0ustar mahmoudyfreeshell%Error: t/t_struct_contents_bad.v:20:19: Unpacked data type 'real' in packed struct/union (IEEE 1800-2023 7.2.1) : ... note: In instance 't' 20 | real r; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_struct_contents_bad.v:22:19: Unpacked data type 'real' in packed struct/union (IEEE 1800-2023 7.2.1) : ... note: In instance 't' 22 | shortreal sr; | ^~ %Error: t/t_struct_contents_bad.v:23:19: Unpacked data type 'real' in packed struct/union (IEEE 1800-2023 7.2.1) : ... note: In instance 't' 23 | realtime rt; | ^~ %Error: t/t_struct_contents_bad.v:24:19: Unpacked data type 'chandle' in packed struct/union (IEEE 1800-2023 7.2.1) : ... note: In instance 't' 24 | chandle ch; | ^~ %Error: t/t_struct_contents_bad.v:25:19: Unpacked data type 'string' in packed struct/union (IEEE 1800-2023 7.2.1) : ... note: In instance 't' 25 | string s; | ^ %Error: t/t_struct_contents_bad.v:26:19: Unpacked data type 'event' in packed struct/union (IEEE 1800-2023 7.2.1) : ... note: In instance 't' 26 | event e; | ^ %Error: t/t_struct_contents_bad.v:27:25: Unpacked data type 'struct{}t.struct_unpacked_t' in packed struct/union (IEEE 1800-2023 7.2.1) : ... note: In instance 't' 27 | struct_unpacked_t sp; | ^~ %Error: t/t_struct_contents_bad.v:28:24: Unpacked data type 'union{}t.union_unpacked_t' in packed struct/union (IEEE 1800-2023 7.2.1) : ... note: In instance 't' 28 | union_unpacked_t up; | ^~ %Error: t/t_struct_contents_bad.v:29:11: Unpacked data type 'int$[0:1]' in packed struct/union (IEEE 1800-2023 7.2.1) : ... note: In instance 't' 29 | int uarray[2]; | ^~~~~~ %Error: t/t_struct_contents_bad.v:30:11: Unpacked data type 'class{}Cls' in packed struct/union (IEEE 1800-2023 7.2.1) : ... note: In instance 't' 30 | Cls c; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_fork_join_none_virtual.py0000755000542200017500000000077115101701376024540 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_flag_hier1_bad.py0000755000542200017500000000125715101701376022602 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_hier_block.v" test.lint(fails=True, verilator_flags2=[ '--hierarchical', '--hierarchical-child 1', 'modName', ], expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_mod_bad.out0000644000542200017500000000057315101701376022721 0ustar mahmoudyfreeshell%Error: t/t_class_mod_bad.v:21:7: Package/class for ':: reference' not found: 'M' 21 | M::Cls p; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_class_mod_bad.v:21:7: Package/class for 'class/package reference' not found: 'M' 21 | M::Cls p; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_class_extern_args_bad.out0000644000542200017500000001305015101701376024455 0ustar mahmoudyfreeshell%Error-PROTOTYPEMIS: t/t_class_extern_args_bad.v:8:15: In prototype for 'func_bad', return data type does not match out-of-block declaration data-type (IEEE 1800-2023 8.24) : ... note: In instance 't' : ... Prototype data type: 'VOIDDTYPE' : ... Declaration data type: 'bit' 8 | extern task func_bad(); | ^~~~~~~~ t/t_class_extern_args_bad.v:19:10: ... Location of out-of-block declaration 19 | function bit Cls::func_bad(); | ^~~ ... For error description see https://verilator.org/warn/PROTOTYPEMIS?v=latest %Error-PROTOTYPEMIS: t/t_class_extern_args_bad.v:9:19: In prototype for 'f1_bad', return data type does not match out-of-block declaration data-type (IEEE 1800-2023 8.24) : ... note: In instance 't' : ... Prototype data type: 'int' : ... Declaration data type: 'bit' 9 | extern function int f1_bad(); | ^~~ t/t_class_extern_args_bad.v:23:10: ... Location of out-of-block declaration 23 | function bit Cls::f1_bad(); | ^~~ %Error-PROTOTYPEMIS: t/t_class_extern_args_bad.v:10:19: In prototype for 'f2_bad', return data type does not match out-of-block declaration data-type (IEEE 1800-2023 8.24) : ... note: In instance 't' : ... Prototype data type: 'int' : ... Declaration data type: 'VOIDDTYPE' 10 | extern function int f2_bad(); | ^~~ t/t_class_extern_args_bad.v:26:15: ... Location of out-of-block declaration 26 | function void Cls::f2_bad(); | ^~~ %Error-PROTOTYPEMIS: t/t_class_extern_args_bad.v:11:24: In prototype for 'f3_bad', return data type does not match out-of-block declaration data-type (IEEE 1800-2023 8.24) : ... note: In instance 't' : ... Prototype data type: 'VOIDDTYPE' : ... Declaration data type: 'bit' 11 | extern function void f3_bad(); | ^~~~~~ t/t_class_extern_args_bad.v:28:10: ... Location of out-of-block declaration 28 | function bit Cls::f3_bad(); | ^~~ %Error-PROTOTYPEMIS: t/t_class_extern_args_bad.v:12:34: In prototype for 'f1bit_bad', argument 'a' data-type does not match out-of-block declaration's data-type (IEEE 1800-2023 8.24) : ... note: In instance 't' : ... Prototype data type: 'int' : ... Declaration data type: 'bit' 12 | extern function void f1bit_bad(int a); | ^~~ t/t_class_extern_args_bad.v:32:30: ... Location of out-of-block declaration 32 | function void Cls::f1bit_bad(bit a); | ^~~ %Error-PROTOTYPEMIS: t/t_class_extern_args_bad.v:13:24: In prototype for 'f2args1_bad', the argumement counts do not match the out-of-block declaration (IEEE 1800-2023 8.24) : ... note: In instance 't' 13 | extern function void f2args1_bad(bit a); | ^~~~~~~~~~~ t/t_class_extern_args_bad.v:35:15: ... Location of out-of-block declaration 35 | function void Cls::f2args1_bad(bit a, bit b); | ^~~ %Error-PROTOTYPEMIS: t/t_class_extern_args_bad.v:14:24: In prototype for 'f2args2', the argumement counts do not match the out-of-block declaration (IEEE 1800-2023 8.24) : ... note: In instance 't' 14 | extern function void f2args2(bit a); | ^~~~~~~ t/t_class_extern_args_bad.v:38:15: ... Location of out-of-block declaration 38 | function void Cls::f2args2(bit a, bit b); | ^~~ %Error-PROTOTYPEMIS: t/t_class_extern_args_bad.v:15:24: In prototype for 'f2args3_bad', the argumement counts do not match the out-of-block declaration (IEEE 1800-2023 8.24) : ... note: In instance 't' 15 | extern function void f2args3_bad(bit a, bit b, bit c); | ^~~~~~~~~~~ t/t_class_extern_args_bad.v:41:15: ... Location of out-of-block declaration 41 | function void Cls::f2args3_bad(bit a, bit b); | ^~~ %Error-PROTOTYPEMIS: t/t_class_extern_args_bad.v:16:38: In prototype for 'farg_name_bad', argument 1 named 'declnamebad' mismatches out-of-block argument name 'declname' (IEEE 1800-2023 8.24) : ... note: In instance 't' 16 | extern function void farg_name_bad(bit declnamebad); | ^~~ t/t_class_extern_args_bad.v:44:34: ... Location of out-of-block declaration 44 | function void Cls::farg_name_bad(bit declname); | ^~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_interface_mismodport_bad.v0000644000542200017500000000116715101701376024630 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface ifc; integer ok; integer bad; modport out_modport (output ok); endinterface module t; integer cyc=1; ifc itop(); counter_ansi c1 (.isub(itop), .i_value(4'h4)); endmodule module counter_ansi ( ifc.out_modport isub, input logic [3:0] i_value ); always @* begin isub.ok = i_value; isub.bad = i_value; // Illegal access end endmodule verilator-5.042/test_regress/t/t_timing_wait_long.v0000644000542200017500000000302415101701376023131 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `timescale 1ns/1ps module timing_wait_long(); localparam real FULL_TIME = 5e6; /* verilator lint_off WIDTHTRUNC */ localparam [22:0] FIT_TIME = int'(5e6); localparam [21:0] TRUNCATED_TIME = int'(5e6); // 805696 /* verilator lint_on WIDTHTRUNC */ real realvar_time = 5e6; time timevar; initial begin #5ms; $display("Current realtime: %d == %d", time'($realtime), time'(1 * 5e9)); realvar_time = realvar_time + 1; #realvar_time; $display("Current realtime: %d == %d", time'($realtime), time'(2 * 5e6 + 1)); timevar = time'(realvar_time - 2); #timevar; $display("Current realtime: %d == %d", time'($realtime), time'(3 * 5e6)); $display("FULL_TIME: %f", FULL_TIME); #FULL_TIME; $display("Current realtime: %d == %d", time'($realtime), time'(4 * 5e6)); $display("FIT_TIME: %d -- %f", FIT_TIME, real'(FIT_TIME)); #FIT_TIME; $display("Current realtime: %d == %d", time'($realtime), time'(5 * 5e6)); $display("TRUNCATED_TIME: %d -- %f", TRUNCATED_TIME, real'(TRUNCATED_TIME)); #TRUNCATED_TIME; $display("Current realtime: %d == %d", time'($realtime), time'(5 * 5e6 + real'(int'(5e6) % 2**22))); $write("*-* All Finished *-*\n"); $finish(); end endmodule verilator-5.042/test_regress/t/t_func_begin2.v0000644000542200017500000000164515101701376021767 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module init; task t1; reg ba,bb,bc,bd,be,bf,bg,bh,bi,bj,bk,bl,bm,bn,bo,bp,bq,br,bs,bt,bu,bv,bw,bx,by,bz; reg ca,cb,cc,cd,ce,cf,cg,ch,ci,cj,ck,cl,cm,cn,co,cp,cq,cr,cs,ct,cu,cv,cw,cx,cy,cz; reg da,db,dc,dd,de,df,dg,dh,di,dj,dk,dl,dm,dn, dp,dq,dr,ds,dt,du,dv,dw,dx,dy,dz; begin : READER $display ("Time: %0t Instance: %m", $time); end endtask task t2; reg ba,bb,bc,bd,be,bf,bg,bh,bi,bj,bk,bl,bm,bn,bo,bp,bq,br,bs,bt,bu,bv,bw,bx,by,bz; begin : READER $display ("Time: %0t Instance: %m", $time); end endtask endmodule module test(); init u_ram1(); init u_ram2(); endmodule verilator-5.042/test_regress/t/t_timing_class.py0000755000542200017500000000076315101701376022450 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_pipe_filter_pf.pf0000755000542200017500000000362715101701376022742 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # mypy: disallow-untyped-defs # pylint: disable=C0103,C0114 # # DESCRIPTION: Verilator: Verilog Test example --pipe-filter script # # Copyright 2010 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import re import sys Debug = False if Debug: sys.stderr.write("t_pipe_filter_pf.pf: Hello from t_pipe_filter_pf.pf\n") for cmd in sys.stdin: if Debug: sys.stderr.write("t_pipe_filter_pf.pf: gotcmd: " + cmd) match = re.match(r'read "(.*)"', cmd) if match: filename = match.group(1) wholefile = "" # It's faster to slurp the whole file then scan (if needed) with open(filename, "r", encoding="utf8") as fh: wholefile = fh.read() if 'example_lint' in wholefile: # else short circuit lineno = 1 pos = 0 prefixes = [] while True: newpos = wholefile.find('\n', pos) if newpos < pos: break line = wholefile[pos:newpos] if 'example_lint' in line: # We don't have a way to specify this yet, so just for now # sys.stderr.write($line) prefixes.append("int lint_off_line_" + str(lineno) + " = 1;\n") lineno += 1 pos = newpos + 1 # sys.stderr.write("Line count: %d\n" % lineno) wholefile = ''.join(prefixes) + wholefile print("Content-Length: " + str(len(wholefile)) + "\n" + wholefile) sys.stdout.flush() else: sys.exit("t_pipe_filter_pf.pf: %Error: Unknown command: " + cmd) if Debug: sys.stderr.write("t_pipe_filter_pf.pf: Fin\n") sys.exit(0) verilator-5.042/test_regress/t/t_force_subnet.py0000755000542200017500000000073415101701376022450 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_x_rand_stability_trace.py0000755000542200017500000000120415101701376024500 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios("vlt") test.top_filename = "t/t_x_rand_stability.v" test.compile(verilator_flags2=["--x-initial unique", "--trace"]) test.execute(all_run_flags=["+verilator+rand+reset+2"], expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_math_countbits.py0000755000542200017500000000073415101701376023015 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_preproc_def09.py0000755000542200017500000000137215101701376022432 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') stdout_filename = os.path.join(test.obj_dir, test.name + "__test.vpp") test.compile(verilator_flags2=['-E'], verilator_make_gmake=False, make_top_shell=False, make_main=False, stdout_filename=stdout_filename) test.files_identical(stdout_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface_virtual_unused3.py0000755000542200017500000000071415101701376025144 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.passes() verilator-5.042/test_regress/t/t_typedef_no_bad.py0000755000542200017500000000102515101701376022726 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--json-only"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_inst_comma_inl1.py0000755000542200017500000000104215101701376023037 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_inst_comma.v" test.compile(v_flags2=['+define+USE_INLINE']) test.execute() test.passes() verilator-5.042/test_regress/t/t_covergroup_with_sample_zeroargs.py0000755000542200017500000000070615101701376026474 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.passes() verilator-5.042/test_regress/t/t_interface_generic_bad4.v0000644000542200017500000000121115101701376024121 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 interface inf; int v; endinterface interface inf2; int k; endinterface module GenericModule (interface a, interface b); initial begin #1; if (a.v != 7) $stop; if (b.k != 9) $stop; end endmodule module t; int inf_inst; inf2 inf_inst2(); GenericModule genericModule (inf_inst, inf_inst2); initial begin inf_inst.v = 7; inf_inst2.k = 9; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_math_eq_bad.out0000644000542200017500000000047715101701376022376 0ustar mahmoudyfreeshell%Error: t/t_math_eq_bad.v:13:13: Real is illegal operand to ?== operator : ... note: In instance 't' 13 | if (a ==? 1.0) $stop; | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_interface_typedef.out0000644000542200017500000000044315101701376023623 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_interface_typedef.v:46:4: Unsupported: SystemVerilog 2005 typedef in this context 46 | typedef ifc_if.struct_t struct_t; | ^~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_param_func.py0000755000542200017500000000071415101701376022103 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.passes() verilator-5.042/test_regress/t/t_inside_unpacked.py0000755000542200017500000000073415101701376023117 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_param_type_bad2.v0000644000542200017500000000046015101701376022631 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; localparam t = logic; // Bad localparam t2 = realtime; // Bad endmodule verilator-5.042/test_regress/t/t_select_bad_range2.out0000644000542200017500000000073315101701376023470 0ustar mahmoudyfreeshell%Warning-SELRANGE: t/t_select_bad_range2.v:51:21: Selection index out of range: 3:2 outside 1:0 : ... note: In instance 't.test' 51 | assign out32 = in[3:2]; | ^ ... For warning description see https://verilator.org/warn/SELRANGE?v=latest ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_force_mid.cpp0000644000542200017500000000263115101701376022046 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Test defines #define MAIN_TIME_MULTIPLIER 1 #include // OS header #include "verilatedos.h" // Generated header #include VM_PREFIX_INCLUDE // General headers #include "verilated.h" std::unique_ptr topp; int main(int argc, char** argv) { uint64_t sim_time = 1100; const std::unique_ptr contextp{new VerilatedContext}; contextp->commandArgs(argc, argv); contextp->debug(0); srand48(5); topp.reset(new Vt_force_mid{"top"}); topp->topin = 0x9; topp->eval(); { topp->clk = false; contextp->timeInc(10 * MAIN_TIME_MULTIPLIER); } while ((contextp->time() < sim_time * MAIN_TIME_MULTIPLIER) && !contextp->gotFinish()) { topp->clk = !topp->clk; topp->eval(); contextp->timeInc(1 * MAIN_TIME_MULTIPLIER); contextp->timeInc(1 * MAIN_TIME_MULTIPLIER); contextp->timeInc(1 * MAIN_TIME_MULTIPLIER); contextp->timeInc(1 * MAIN_TIME_MULTIPLIER); contextp->timeInc(1 * MAIN_TIME_MULTIPLIER); } if (!contextp->gotFinish()) { vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); } topp->final(); topp.reset(); return 0; } verilator-5.042/test_regress/t/t_lint_inherit.v0000644000542200017500000000241015101701376022265 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs q, // Inputs clk, d ); input clk; input d; output wire [1:0] q; // This demonstrates how warning disables should be propagated across module boundaries. m1 m1 (/*AUTOINST*/ // Outputs .q (q[1:0]), // Inputs .clk (clk), .d (d)); endmodule module m1 ( input clk, input d, output wire [1:0] q ); m2 m2 (/*AUTOINST*/ // Outputs .q (q[1:0]), // Inputs .clk (clk), .d (d)); endmodule module m2 ( input clk, input d, // Due to bug the below disable used to be ignored. // verilator lint_off UNOPT // verilator lint_off UNOPTFLAT output reg [1:0] q // verilator lint_on UNOPT // verilator lint_on UNOPTFLAT ); always @* begin q[1] = d; end always @* begin q[0] = q[1]; end endmodule verilator-5.042/test_regress/t/t_EXAMPLE.py0000755000542200017500000000073415101701376021065 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_select_ascending.py0000755000542200017500000000073415101701376023264 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_assert_ctl_concurrent_noinl.py0000755000542200017500000000107115101701376025571 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t_assert_ctl_concurrent.v" test.compile(verilator_flags2=["--binary --assert --fno-inline"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_cover_expr.v0000644000542200017500000001260515101701376021760 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class cls; rand int x; endclass module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; logic [63:32] cyc2; always_comb cyc2 = cyc; integer some_int; integer other_int; logic some_bool; wire t1 = cyc[0]; wire t2 = cyc[1]; wire t3 = cyc[2]; wire t4 = cyc[3]; localparam bit ONE = 1'b1; localparam bit ZERO = 1'b0; function automatic bit invert(bit x); return ~x; endfunction function automatic bit and_oper(bit a, bit b); return a & b; endfunction localparam int NUM_INTFS = 4; intf the_intfs [NUM_INTFS-1:0] (); genvar intf_i; for (intf_i = 0; intf_i < NUM_INTFS; intf_i++) begin always_comb the_intfs[intf_i].t = cyc[intf_i]; end always @ (posedge clk) begin cyc <= cyc + 1; if ((~cyc[0] && cyc[1]) || (~cyc[2] && cyc[3])) $write(""); if ((~cyc2[32] && cyc2[33]) || (~cyc2[34] && cyc2[35])) $write(""); if ((~the_intfs[0].t && the_intfs[1].t) || (~the_intfs[2].t && the_intfs[3].t)) $write(""); if ((~t1 && t2) || (~t3 && t4)) $write(""); if (t3 && (t1 == t2)) $write(""); if (123 == (124 - 32'(t1 || t2))) $write(""); some_int <= (t2 || t3) ? 345 : 567; some_bool <= t1 && t2; if (t1 & t2) $write(""); if ((!t1 && t2) | (~t3 && t4)) $write(""); if (t1 ^ t2) $write(""); if (~(t1 & t2)) $write(""); if (t1 -> t2) $write(""); if (t1 <-> t2) $write(""); if (&cyc[2:0]) $write(""); if (&cyc[3:2]) $write(""); if (|cyc[2:0]) $write(""); if (^cyc[2:0]) $write(""); if (|cyc[2:0] || cyc[3]) $write(""); if (t1 & t2 & 1'b1) $write(""); if (t1 & t2 & 1'b0) $write(""); if (t1 & t2 & ONE) $write(""); if (t1 & t2 & ZERO) $write(""); if (t1 && t2) begin $write(""); end else if (t1 || t2) begin $write(""); end if (invert(t1) && t2) $write(""); if (and_oper(t1, t2)) $write(""); if (t2 && t3) begin if (t1 && t2) $write(""); end if (0 == 1) begin for (int loop_var = 0; loop_var < 1; loop_var++) begin if (cyc[loop_var] && t2) $write(""); end end // stop at the first layer even if there's more to find if ((cyc[3+32'(t1 && t2)+:2] == cyc[5+32'(t3 || t4)+:2]) || cyc[31]) $write(""); // impossible branches and redundant terms if ((t1 && t2) && ~(t1 && t3) && (t1 || t4)) $write(""); if ((cyc[0] && cyc[1]) && ~(cyc[0] && cyc[2]) && (cyc[0] || cyc[3])) $write(""); // demonstrate current limitations of term matching scheme if ((cyc[0] && cyc[1]) && ~(cyc[1-1] && cyc[2]) && (cyc[2-2] || cyc[3])) $write(""); //verilator coverage_off if (t1 && t2) $write(""); //verilator coverage_on if ((~t1 && t2) || (~t3 && t4)) $write(""); // intentionally testing wonkified expression terms if ( cyc[ 0 ] & cyc [1]) $write(""); // for now each ternary condition is considered in isolation other_int <= t1 ? t2 ? 1 : 2 : 3; // no expression coverage for multi-bit expressions if ((cyc[1:0] & cyc[3:2]) == 2'b11) $write(""); // truth table is too large if (^cyc[6:0]) $write(""); // this one is too big even for t_cover_expr_max if (^cyc) $write(""); if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end always_comb begin if (t1 && t2) $write(""); end logic ta, tb, tc; initial begin cls obj = new; cls null_obj = null; int q[5]; int qv[$]; q = '{1, 2, 2, 4, 3}; // lambas not handled // NB: there is a bug w/ tracing find_first (maybe lambdas in general?) // tracing_off does not work around the bug qv = q.find_first with (item[0] & item[1]); ta = '1; tb = '0; tc = '0; while (ta || tb || tc) begin tc = tb; tb = ta; ta = '0; end if (!bit'(obj.randomize() with {x < 100;})) $write(""); if (null_obj != null && null_obj.x == 5) $write(""); end sub the_sub_1 (.p(t1), .q(t2)); sub the_sub_2 (.p(t3), .q(t4)); // TODO -- non-process expressions sub the_sub_3 (.p(t1 ? t2 : t3), .q(t4)); // TODO // pragma for expr coverage off / on // investigate cover point sorting in annotated source // consider reporting don't care terms // // Branches which are statically impossible to reach are still reported. // E.g. // -000000 point: comment=(t1=1 && t2=1 && 1'h0=1) => 1 hier=top.t // These could potentially be pruned, but they currently follow suit for // what branch coverage does. Perhaps a switch should be added to not // count statically impossible things. endmodule module sub ( input p, input q ); always_comb begin if (p && q) $write(""); end endmodule interface intf(); logic t; endinterface verilator-5.042/test_regress/t/t_lint_incabspath.v0000644000542200017500000000040015101701376022734 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `include "/dev/null" module t; endmodule verilator-5.042/test_regress/t/t_strength_equal_strength.py0000755000542200017500000000073415101701376024735 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_constraint.py0000755000542200017500000000111515101701376022150 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile(verilator_flags2=['-Wno-CONSTRAINTIGN']) test.execute() test.passes() verilator-5.042/test_regress/t/t_unoptflat_simple_2.v0000644000542200017500000000132615101701376023410 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Simple test of unoptflat // // Simple demonstration of an UNOPTFLAT combinatorial loop, using 3 bits. // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; /* verilator lint_off MULTIDRIVEN */ wire [2:0] x; /* verilator lint_on MULTIDRIVEN */ assign x[1:0] = { x[0], clk }; assign x[2:1] = x[1:0]; always @(posedge clk or negedge clk) begin `ifdef TEST_VERBOSE $write("x = %x\n", x); `endif if (x[2] != 0) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule // t verilator-5.042/test_regress/t/t_param_up_bad.v0000644000542200017500000000117215101701376022213 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2016 by Ian Thompson. // SPDX-License-Identifier: CC0-1.0 //bug1099 typedef struct packed { logic foo; } some_struct_t; module child (); logic a_bad; // bar is in the parent module, but illegal to reference without module name assign a_bad = bar.foo; endmodule module parent #( parameter PARAM = 0 ) ( ); some_struct_t bar; child c (); endmodule module t (); // The parameter must be anything other than the default parent #( 1 ) p (); endmodule verilator-5.042/test_regress/t/t_gen_genblk.py0000755000542200017500000000102615101701376022060 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.sim_time = 11000 test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_gantt.py0000755000542200017500000000360615101701376021110 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Test for bin/verilator_gantt, import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_gantt.v" test.pli_filename = "t/t_gantt_c.cpp" test.compile( verilator_flags2=["--prof-exec", test.pli_filename], # Checks below care about thread count, so use 2 (minimum reasonable) threads=(2 if test.vltmt else 1)) test.execute(all_run_flags=[ "+verilator+prof+exec+start+2", " +verilator+prof+exec+window+2", " +verilator+prof+exec+file+" + test.obj_dir + "/profile_exec.dat", " +verilator+prof+vlt+file+" + test.obj_dir + "/profile.vlt"]) # yapf:disable # The profiling data goes direct to the runtime's STDOUT # (maybe that should go to a separate file - gantt.dat?) gantt_log = test.obj_dir + "/gantt.log" test.run(cmd=[ os.environ["VERILATOR_ROOT"] + "/bin/verilator_gantt", test.obj_dir + "/profile_exec.dat", "--vcd " + test.obj_dir + "/profile_exec.vcd", "| tee " + gantt_log ]) if test.vltmt: test.file_grep(gantt_log, r'Total threads += +(\d+)', 2) test.file_grep(gantt_log, r'Total mtasks += +(\d+)', 6) # Predicted thread utilization should be less than 100% test.file_grep_not(gantt_log, r'Thread utilization =\s*\d\d\d+\.\d+%') else: test.file_grep(gantt_log, r'Total threads += +(\d+)', 1) test.file_grep(gantt_log, r'Total mtasks += +(\d+)', 0) test.file_grep(gantt_log, r'\|\s+2\s+\|\s+2\.0+\s+\|\s+eval') # Diff to itself, just to check parsing test.vcd_identical(test.obj_dir + "/profile_exec.vcd", test.obj_dir + "/profile_exec.vcd") test.passes() verilator-5.042/test_regress/t/t_param_type_bad3.py0000755000542200017500000000111015101701376023011 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint( # Bug1575 required trace to crash verilator_flags2=["--trace-vcd"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_timing_protect.py0000755000542200017500000000163115101701376023016 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_timing_fork_join.v" # Contains all relevant constructs if not test.have_coroutines: test.skip("No coroutine support") test.compile(verilator_flags2=["--binary --protect-ids", "--protect-key SECRET_KEY"]) test.execute() if test.vlt_all: # Check for secret in any outputs for filename in test.glob_some(test.obj_dir + "/*.[ch]*"): test.file_grep_not(filename, r'event[123]') test.file_grep_not(filename, r't_timing_fork_join') test.passes() verilator-5.042/test_regress/t/t_inst_param_comma_bad.out0000644000542200017500000000177415101701376024272 0ustar mahmoudyfreeshell%Error: t/t_inst_param_comma_bad.v:35:15: syntax error, unexpected ')', expecting IDENTIFIER-for-type 35 | M #(.P(13),) m1( | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_inst_param_comma_bad.v:40:11: syntax error, unexpected ')', expecting IDENTIFIER-for-type 40 | M #(14,) m2 ( | ^ %Error: t/t_inst_param_comma_bad.v:45:11: syntax error, unexpected ')', expecting IDENTIFIER-for-type 45 | M #(14,) m3 ( | ^ %Error: t/t_inst_param_comma_bad.v:50:15: syntax error, unexpected ')', expecting IDENTIFIER-for-type 50 | N #(.P(13),) n1( | ^ %Error: t/t_inst_param_comma_bad.v:55:11: syntax error, unexpected ')', expecting IDENTIFIER-for-type 55 | N #(14,) n2 ( | ^ %Error: t/t_inst_param_comma_bad.v:60:11: syntax error, unexpected ')', expecting IDENTIFIER-for-type 60 | N #(14,) n3 ( | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_udp_bad_comb_trigger.py0000755000542200017500000000076615101701376024120 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_always_comb_multidriven_bad.py0000755000542200017500000000103015101701376026536 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=['--lint-only'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_param_value.py0000755000542200017500000000073415101701376022266 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_math_cmp.v0000644000542200017500000001216215101701376021372 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [2:0] index_a; reg [2:0] index_b; prover #(4) p4 (/*AUTOINST*/ // Inputs .clk (clk), .index_a (index_a), .index_b (index_b)); prover #(32) p32 (/*AUTOINST*/ // Inputs .clk (clk), .index_a (index_a), .index_b (index_b)); prover #(63) p63 (/*AUTOINST*/ // Inputs .clk (clk), .index_a (index_a), .index_b (index_b)); prover #(64) p64 (/*AUTOINST*/ // Inputs .clk (clk), .index_a (index_a), .index_b (index_b)); prover #(72) p72 (/*AUTOINST*/ // Inputs .clk (clk), .index_a (index_a), .index_b (index_b)); prover #(126) p126 (/*AUTOINST*/ // Inputs .clk (clk), .index_a (index_a), .index_b (index_b)); prover #(128) p128 (/*AUTOINST*/ // Inputs .clk (clk), .index_a (index_a), .index_b (index_b)); integer cyc; initial cyc = 0; initial index_a = 3'b0; initial index_b = 3'b0; always @* begin index_a = cyc[2:0]; if (index_a>3'd4) index_a=3'd4; index_b = cyc[5:3]; if (index_b>3'd4) index_b=3'd4; end always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module prover ( input clk, input [2:0] index_a, input [2:0] index_b ); parameter WIDTH = 4; reg signed [WIDTH-1:0] as; reg signed [WIDTH-1:0] bs; wire [WIDTH-1:0] b = bs; // verilator lint_off LATCH always @* begin casez (index_a) 3'd0: as = {(WIDTH){1'd0}}; // 0 3'd1: as = {{(WIDTH-1){1'd0}}, 1'b1}; // 1 3'd2: as = {1'b0, {(WIDTH-1){1'd0}}}; // 127 or equiv 3'd3: as = {(WIDTH){1'd1}}; // -1 3'd4: as = {1'b1, {(WIDTH-1){1'd0}}}; // -128 or equiv default: $stop; endcase casez (index_b) 3'd0: bs = {(WIDTH){1'd0}}; // 0 3'd1: bs = {{(WIDTH-1){1'd0}}, 1'b1}; // 1 3'd2: bs = {1'b0, {(WIDTH-1){1'd0}}}; // 127 or equiv 3'd3: bs = {(WIDTH){1'd1}}; // -1 3'd4: bs = {1'b1, {(WIDTH-1){1'd0}}}; // -128 or equiv default: $stop; endcase end // verilator lint_on LATCH reg [7:0] results[4:0][4:0]; wire gt = as>b; wire gts = as>bs; wire gte = as>=b; wire gtes = as>=bs; wire lt = as2) begin `ifdef TEST_VERBOSE $write("results[%d][%d] = 8'b%b_%b_%b_%b_%b_%b_%b_%b;\n", index_a, index_b, gt, gts, gte, gtes, lt, lts, lte, ltes); `endif exp = results[index_a][index_b]; got = {gt, gts, gte, gtes, lt, lts, lte, ltes}; if (exp !== got) begin $display("%%Error: bad comparison width=%0d: %d/%d got=%b exp=%b", WIDTH, index_a,index_b,got, exp); $stop; end end end // Result table initial begin // Indexes: 0, 1, -1, 127, -128 // Gt Gts Gte Gtes Lt Lts Lte Ltes results[0][0] = 8'b0_0_1_1_0_0_1_1; results[0][1] = 8'b0_0_0_0_1_1_1_1; results[0][2] = 8'b0_0_1_1_0_0_1_1; results[0][3] = 8'b0_1_0_1_1_0_1_0; results[0][4] = 8'b0_1_0_1_1_0_1_0; results[1][0] = 8'b1_1_1_1_0_0_0_0; results[1][1] = 8'b0_0_1_1_0_0_1_1; results[1][2] = 8'b1_1_1_1_0_0_0_0; results[1][3] = 8'b0_1_0_1_1_0_1_0; results[1][4] = 8'b0_1_0_1_1_0_1_0; results[2][0] = 8'b0_0_1_1_0_0_1_1; results[2][1] = 8'b0_0_0_0_1_1_1_1; results[2][2] = 8'b0_0_1_1_0_0_1_1; results[2][3] = 8'b0_1_0_1_1_0_1_0; results[2][4] = 8'b0_1_0_1_1_0_1_0; results[3][0] = 8'b1_0_1_0_0_1_0_1; results[3][1] = 8'b1_0_1_0_0_1_0_1; results[3][2] = 8'b1_0_1_0_0_1_0_1; results[3][3] = 8'b0_0_1_1_0_0_1_1; results[3][4] = 8'b1_1_1_1_0_0_0_0; results[4][0] = 8'b1_0_1_0_0_1_0_1; results[4][1] = 8'b1_0_1_0_0_1_0_1; results[4][2] = 8'b1_0_1_0_0_1_0_1; results[4][3] = 8'b0_0_0_0_1_1_1_1; results[4][4] = 8'b0_0_1_1_0_0_1_1; end endmodule verilator-5.042/test_regress/t/t_unroll_stmt.out0000644000542200017500000000054115101701376022524 0ustar mahmoudyfreeshellloop_0 0 loop_0 1 loop_0 2 loop_1 0 5 loop_1 2 6 loop_1 4 7 loop_1 6 8 loop_1 8 9 loop_2 0 5 loop_2 1 5 loop_2 2 5 loop_2 3 5 loop_2 4 5 loop_3 4 0 loop_3 3 0 loop_3 2 0 loop_3 1 0 loop_3 0 0 loop_4 loop_5 1 loop_5 2 loop_5 3 loop_5 4 loop_5 5 loop_5 6 loop_5 7 loop_6 0 loop_6 1 loop_6 2 loop_6 3 loop_6 4 loop_6 5 stopping loop_6 *-* All Finished *-* verilator-5.042/test_regress/t/t_runflag.py0000755000542200017500000000222115101701376021421 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile() test.execute(all_run_flags=["+verilator+debug +verilator+debugi+9 +verilator+rand+reset+1"], logfile=test.obj_dir + "/vlt_1.log") test.file_grep(test.obj_dir + "/vlt_1.log", r'Verilated::debug is on') test.execute(all_run_flags=["+verilator+help"], fails=True, logfile=test.obj_dir + "/vlt_2.log") test.file_grep(test.obj_dir + "/vlt_2.log", r"For help, please see 'verilator --help'") test.execute(all_run_flags=["+verilator+V"], fails=True, logfile=test.obj_dir + "/vlt_3.log") test.file_grep(test.obj_dir + "/vlt_3.log", r'Version:') test.execute(all_run_flags=["+verilator+version"], fails=True, logfile=test.obj_dir + "/vlt_4.log") test.file_grep(test.obj_dir + "/vlt_4.log", r'Version:') test.passes() verilator-5.042/test_regress/t/t_trace_ascendingrange.out0000644000542200017500000002676115101701376024304 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $var wire 1 } clk $end $scope module t $end $var wire 8 ~ P [0:7] $end $var wire 1 } clk $end $var wire 32 # cyc [31:0] $end $var wire 8 !! Q [0:7] $end $var wire 1 $ v_a [0:0] $end $var wire 2 % v_b [0:1] $end $var wire 8 & v_c [0:7] $end $var wire 9 ' v_d [0:8] $end $var wire 16 ( v_e [0:15] $end $var wire 17 ) v_f [0:16] $end $var wire 32 * v_g [0:31] $end $var wire 33 + v_h [0:32] $end $var wire 64 - v_i [0:63] $end $var wire 65 / v_j [0:64] $end $var wire 128 2 v_k [0:127] $end $var wire 129 6 v_l [0:128] $end $var wire 256 ; v_m [0:255] $end $var wire 257 C v_n [0:256] $end $var wire 512 L v_o [0:511] $end $var wire 3 \ v_p [-1:1] $end $var wire 15 ] v_q [-7:7] $end $var wire 31 ^ v_r [-15:15] $end $var wire 63 _ v_s [-31:31] $end $var wire 127 a v_t [-63:63] $end $var wire 255 e v_u [-127:127] $end $var wire 511 m v_v [-255:255] $end $upscope $end $upscope $end $enddefinitions $end #0 b00000000000000000000000000000000 # 0$ b00 % b00000000 & b000000000 ' b0000000000000000 ( b00000000000000000 ) b00000000000000000000000000000000 * b000000000000000000000000000000000 + b0000000000000000000000000000000000000000000000000000000000000000 - b00000000000000000000000000000000000000000000000000000000000000000 / b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2 b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 6 b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L b000 \ b000000000000000 ] b0000000000000000000000000000000 ^ b000000000000000000000000000000000000000000000000000000000000000 _ b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m 0} b00001010 ~ b00010100 !! #10 b00000000000000000000000000000001 # 1$ b11 % b11111111 & b111111111 ' b1111111111111111 ( b11111111111111111 ) b11111111111111111111111111111111 * b111111111111111111111111111111111 + b1111111111111111111111111111111111111111111111111111111111111111 - b11111111111111111111111111111111111111111111111111111111111111111 / b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 2 b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 6 b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 ; b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 C b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 L b111 \ b111111111111111 ] b1111111111111111111111111111111 ^ b111111111111111111111111111111111111111111111111111111111111111 _ b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 a b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 e b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 m 1} #15 0} #20 b00000000000000000000000000000010 # 0$ b10 % b11111110 & b111111110 ' b1111111111111110 ( b11111111111111110 ) b11111111111111111111111111111110 * b111111111111111111111111111111110 + b1111111111111111111111111111111111111111111111111111111111111110 - b11111111111111111111111111111111111111111111111111111111111111110 / b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 2 b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 6 b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 ; b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 C b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 L b110 \ b111111111111110 ] b1111111111111111111111111111110 ^ b111111111111111111111111111111111111111111111111111111111111110 _ b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 a b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 e b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 m 1} #25 0} #30 b00000000000000000000000000000011 # b00 % b11111100 & b111111100 ' b1111111111111100 ( b11111111111111100 ) b11111111111111111111111111111100 * b111111111111111111111111111111100 + b1111111111111111111111111111111111111111111111111111111111111100 - b11111111111111111111111111111111111111111111111111111111111111100 / b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 2 b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 6 b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 ; b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 C b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 L b100 \ b111111111111100 ] b1111111111111111111111111111100 ^ b111111111111111111111111111111111111111111111111111111111111100 _ b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 a b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 e b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 m 1} verilator-5.042/test_regress/t/t_cover_line_sc.py0000755000542200017500000000121515101701376022577 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_cover_line.v" test.compile(verilator_flags2=['--sc --coverage-line +define+ATTRIBUTE']) test.execute() # Read the input .v file and do any CHECK_COVER requests test.inline_checks() test.passes() verilator-5.042/test_regress/t/t_lint_dtype_compare.py0000755000542200017500000000073415101701376023653 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_struct_array_assignment.py0000755000542200017500000000073415101701376024744 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_pp_line_bad.out0000644000542200017500000000216715101701376022404 0ustar mahmoudyfreeshell%Error: t/t_pp_line_bad.v:8:1: `line was not properly formed with '`line number "filename" level' 8 | `line 100 | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_pp_line_bad.v:9:1: `line was not properly formed with '`line number "filename" level' 9 | `line 200 somefile | ^ %Error: t/t_pp_line_bad.v:10:1: `line was not properly formed with '`line number "filename" level' 10 | `line 300 "somefile 1 | ^ %Error: t/t_pp_line_bad.v:11:1: `line was not properly formed with '`line number "filename" level' 11 | `line 400 "some file" | ^ %Error: t/t_pp_line_bad.v:12:1: `line was not properly formed with '`line number "filename" level' 12 | `line 500 "somefile" 3 | ^ %Error: t/t_pp_line_bad.v:13:1: `line was not properly formed with '`line number "filename" level' 13 | `line 600 "some file" 3 | ^ %Error: t/t_pp_line_bad.v:7:1: Define or directive not defined: '`line' 7 | `line | ^~~~~ %Error: t/t_pp_line_bad.v:14:1: `line was not properly formed with '`line number "filename" level' %Error: Exiting due to verilator-5.042/test_regress/t/t_x_rand_mt_stability_add.py0000755000542200017500000000121315101701376024632 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios("vltmt") test.top_filename = "t/t_x_rand_stability.v" test.compile(verilator_flags2=["--x-initial unique", "-DADD_SIGNAL"]) test.execute(all_run_flags=["+verilator+rand+reset+2"], expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_unpack_array_no_expand.py0000755000542200017500000000073415101701376024504 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_fork_func_bad.py0000755000542200017500000000103015101701376022542 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=['--lint-only'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_union_unpacked.v0000644000542200017500000000106015101701376022577 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; union { bit [7:0] val1; bit [3:0] val2; real r; } u; initial begin u.val1 = 8'h7c; if (u.val1 != 8'h7c) $stop; if (u.val2 != 4'hc) $stop; u.r = 1.24; if (u.r != 1.24) $stop; $display("%p", u); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_flag_ldflags.v0000644000542200017500000000133115101701376022203 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2010 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import "DPI-C" pure function void dpii_a_library(); import "DPI-C" pure function void dpii_c_library(); import "DPI-C" pure function void dpii_so_library(); module t (); initial begin dpii_a_library(); // From .a file dpii_c_library(); // From .cpp file dpii_so_library(); // From .so file $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_pp_lib_inc.vh0000644000542200017500000000034715101701376022052 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define WIDTH 10 verilator-5.042/test_regress/t/t_param_wide_io.v0000644000542200017500000000064315101701376022402 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2016 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // See issue #1991 module t #( parameter[96:0] P = 97'h12344321_12344321_12344327 ) ( input [P&7 - 1:0] in, output [P&7 - 1:0] out ); assign out = in; endmodule verilator-5.042/test_regress/t/t_parse_eof_attr_bad.v0000644000542200017500000000033615101701376023405 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 (* attr verilator-5.042/test_regress/t/t_semaphore_class.py0000755000542200017500000000075115101701376023141 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.passes() verilator-5.042/test_regress/t/t_assert_always_unsup.out0000644000542200017500000000163415101701376024261 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_assert_always_unsup.v:21:7: Unsupported: always[] (in property expression) 21 | always [2:5] a; | ^~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_assert_always_unsup.v:25:7: Unsupported: s_always (in property expression) 25 | s_always [2:5] a; | ^~~~~~~~ %Error-UNSUPPORTED: t/t_assert_always_unsup.v:29:7: Unsupported: eventually[] (in property expression) 29 | eventually [2:5] a; | ^~~~~~~~~~ %Error: t/t_assert_always_unsup.v:33:20: syntax error, unexpected ']', expecting ':' 33 | eventually [2] a; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Cannot continue ... This fatal error may be caused by the earlier error(s); resolve those first. verilator-5.042/test_regress/t/t_var_port_json_only.py0000755000542200017500000000135415101701376023717 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') out_filename = test.obj_dir + "/V" + test.name + ".tree.json" test.compile(verilator_flags2=['--no-std', '--json-only', '--no-json-edit-nums'], verilator_make_gmake=False, make_top_shell=False, make_main=False) test.files_identical(out_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dfg_bin_to_one_hot.v0000644000542200017500000003411115101701376023405 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define check(got ,exp) do if ((got) !== (exp)) begin $write("%%Error: %s:%0d: cyc=%0d got='h%x exp='h%x\n", `__FILE__,`__LINE__, cyc, (got), (exp)); `stop; end while(0) module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [31:0] cyc = 0; reg [6:0] cntA = 0; reg [6:0] cntB = 0; reg [6:0] cntC = 0; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc[0]) cntA <= cntA + 7'd1; if (cntA[0]) cntB <= cntB + 7'd1; if (cntB[0]) cntC <= cntC + 7'd1; if (cyc == 99) begin $write("*-* All Finished *-*\n"); $finish; end end // Should create decoder wire [127:0] cntAOneHot = { cntA == 7'd127, cntA == 7'd126, cntA == 7'd125, cntA == 7'd124, cntA == 7'd123, cntA == 7'd122, cntA == 7'd121, cntA == 7'd120, cntA == 7'd119, cntA == 7'd118, cntA == 7'd117, cntA == 7'd116, cntA == 7'd115, cntA == 7'd114, cntA == 7'd113, cntA == 7'd112, cntA == 7'd111, cntA == 7'd110, cntA == 7'd109, cntA == 7'd108, cntA == 7'd107, cntA == 7'd106, cntA == 7'd105, cntA == 7'd104, cntA == 7'd103, cntA == 7'd102, cntA == 7'd101, cntA == 7'd100, cntA == 7'd99, cntA == 7'd98, cntA == 7'd97, cntA == 7'd96, cntA == 7'd95, cntA == 7'd94, cntA == 7'd93, cntA == 7'd92, cntA == 7'd91, cntA == 7'd90, cntA == 7'd89, cntA == 7'd88, cntA == 7'd87, cntA == 7'd86, cntA == 7'd85, cntA == 7'd84, cntA == 7'd83, cntA == 7'd82, cntA == 7'd81, cntA == 7'd80, cntA == 7'd79, cntA == 7'd78, cntA == 7'd77, cntA == 7'd76, cntA == 7'd75, cntA == 7'd74, cntA == 7'd73, cntA == 7'd72, cntA == 7'd71, cntA == 7'd70, cntA == 7'd69, cntA == 7'd68, cntA == 7'd67, cntA == 7'd66, cntA == 7'd65, cntA == 7'd64, cntA == 7'd63, cntA == 7'd62, cntA == 7'd61, cntA == 7'd60, cntA == 7'd59, cntA == 7'd58, cntA == 7'd57, cntA == 7'd56, cntA == 7'd55, cntA == 7'd54, cntA == 7'd53, cntA == 7'd52, cntA == 7'd51, cntA == 7'd50, cntA == 7'd49, cntA == 7'd48, cntA == 7'd47, cntA == 7'd46, cntA == 7'd45, cntA == 7'd44, cntA == 7'd43, cntA == 7'd42, cntA == 7'd41, cntA == 7'd40, cntA == 7'd39, cntA == 7'd38, cntA == 7'd37, cntA == 7'd36, cntA == 7'd35, cntA == 7'd34, cntA == 7'd33, cntA == 7'd32, cntA == 7'd31, cntA == 7'd30, cntA == 7'd29, cntA == 7'd28, cntA == 7'd27, cntA == 7'd26, cntA == 7'd25, cntA == 7'd24, cntA == 7'd23, cntA == 7'd22, cntA == 7'd21, cntA == 7'd20, cntA == 7'd19, cntA == 7'd18, cntA == 7'd17, cntA == 7'd16, cntA == 7'd15, cntA == 7'd14, cntA == 7'd13, cntA == 7'd12, cntA == 7'd11, cntA == 7'd10, cntA == 7'd9, cntA == 7'd8, cntA == 7'd7, cntA == 7'd6, cntA == 7'd5, cntA == 7'd4, cntA == 7'd3, cntA == 7'd2, cntA == 7'd1, cntA == 7'd0 }; // Should create decoder - with temporary needed for index variabls wire [127:0] notCntAOneHot = { ~cntA == 7'd127, ~cntA == 7'd126, ~cntA == 7'd125, ~cntA == 7'd124, ~cntA == 7'd123, ~cntA == 7'd122, ~cntA == 7'd121, ~cntA == 7'd120, ~cntA == 7'd119, ~cntA == 7'd118, ~cntA == 7'd117, ~cntA == 7'd116, ~cntA == 7'd115, ~cntA == 7'd114, ~cntA == 7'd113, ~cntA == 7'd112, ~cntA == 7'd111, ~cntA == 7'd110, ~cntA == 7'd109, ~cntA == 7'd108, ~cntA == 7'd107, ~cntA == 7'd106, ~cntA == 7'd105, ~cntA == 7'd104, ~cntA == 7'd103, ~cntA == 7'd102, ~cntA == 7'd101, ~cntA == 7'd100, ~cntA == 7'd99, ~cntA == 7'd98, ~cntA == 7'd97, ~cntA == 7'd96, ~cntA == 7'd95, ~cntA == 7'd94, ~cntA == 7'd93, ~cntA == 7'd92, ~cntA == 7'd91, ~cntA == 7'd90, ~cntA == 7'd89, ~cntA == 7'd88, ~cntA == 7'd87, ~cntA == 7'd86, ~cntA == 7'd85, ~cntA == 7'd84, ~cntA == 7'd83, ~cntA == 7'd82, ~cntA == 7'd81, ~cntA == 7'd80, ~cntA == 7'd79, ~cntA == 7'd78, ~cntA == 7'd77, ~cntA == 7'd76, ~cntA == 7'd75, ~cntA == 7'd74, ~cntA == 7'd73, ~cntA == 7'd72, ~cntA == 7'd71, ~cntA == 7'd70, ~cntA == 7'd69, ~cntA == 7'd68, ~cntA == 7'd67, ~cntA == 7'd66, ~cntA == 7'd65, ~cntA == 7'd64, ~cntA == 7'd63, ~cntA == 7'd62, ~cntA == 7'd61, ~cntA == 7'd60, ~cntA == 7'd59, ~cntA == 7'd58, ~cntA == 7'd57, ~cntA == 7'd56, ~cntA == 7'd55, ~cntA == 7'd54, ~cntA == 7'd53, ~cntA == 7'd52, ~cntA == 7'd51, ~cntA == 7'd50, ~cntA == 7'd49, ~cntA == 7'd48, ~cntA == 7'd47, ~cntA == 7'd46, ~cntA == 7'd45, ~cntA == 7'd44, ~cntA == 7'd43, ~cntA == 7'd42, ~cntA == 7'd41, ~cntA == 7'd40, ~cntA == 7'd39, ~cntA == 7'd38, ~cntA == 7'd37, ~cntA == 7'd36, ~cntA == 7'd35, ~cntA == 7'd34, ~cntA == 7'd33, ~cntA == 7'd32, ~cntA == 7'd31, ~cntA == 7'd30, ~cntA == 7'd29, ~cntA == 7'd28, ~cntA == 7'd27, ~cntA == 7'd26, ~cntA == 7'd25, ~cntA == 7'd24, ~cntA == 7'd23, ~cntA == 7'd22, ~cntA == 7'd21, ~cntA == 7'd20, ~cntA == 7'd19, ~cntA == 7'd18, ~cntA == 7'd17, ~cntA == 7'd16, ~cntA == 7'd15, ~cntA == 7'd14, ~cntA == 7'd13, ~cntA == 7'd12, ~cntA == 7'd11, ~cntA == 7'd10, ~cntA == 7'd9, ~cntA == 7'd8, ~cntA == 7'd7, ~cntA == 7'd6, ~cntA == 7'd5, ~cntA == 7'd4, ~cntA == 7'd3, ~cntA == 7'd2, ~cntA == 7'd1, ~cntA == 7'd0 }; // Should create decoder wire stupidWayToWriteConstOne = 1'b0 + (cntB == 7'd127) + (cntB == 7'd126) + (cntB == 7'd125) + (cntB == 7'd124) + (cntB == 7'd123) + (cntB == 7'd122) + (cntB == 7'd121) + (cntB == 7'd120) + (cntB == 7'd119) + (cntB == 7'd118) + (cntB == 7'd117) + (cntB == 7'd116) + (cntB == 7'd115) + (cntB == 7'd114) + (cntB == 7'd113) + (cntB == 7'd112) + (cntB == 7'd111) + (cntB == 7'd110) + (cntB == 7'd109) + (cntB == 7'd108) + (cntB == 7'd107) + (cntB == 7'd106) + (cntB == 7'd105) + (cntB == 7'd104) + (cntB == 7'd103) + (cntB == 7'd102) + (cntB == 7'd101) + (cntB == 7'd100) + (cntB == 7'd99) + (cntB == 7'd98) + (cntB == 7'd97) + (cntB == 7'd96) + (cntB == 7'd95) + (cntB == 7'd94) + (cntB == 7'd93) + (cntB == 7'd92) + (cntB == 7'd91) + (cntB == 7'd90) + (cntB == 7'd89) + (cntB == 7'd88) + (cntB == 7'd87) + (cntB == 7'd86) + (cntB == 7'd85) + (cntB == 7'd84) + (cntB == 7'd83) + (cntB == 7'd82) + (cntB == 7'd81) + (cntB == 7'd80) + (cntB == 7'd79) + (cntB == 7'd78) + (cntB == 7'd77) + (cntB == 7'd76) + (cntB == 7'd75) + (cntB == 7'd74) + (cntB == 7'd73) + (cntB == 7'd72) + (cntB == 7'd71) + (cntB == 7'd70) + (cntB == 7'd69) + (cntB == 7'd68) + (cntB == 7'd67) + (cntB == 7'd66) + (cntB == 7'd65) + (cntB == 7'd64) + (cntB == 7'd63) + (cntB == 7'd62) + (cntB == 7'd61) + (cntB == 7'd60) + (cntB == 7'd59) + (cntB == 7'd58) + (cntB == 7'd57) + (cntB == 7'd56) + (cntB == 7'd55) + (cntB == 7'd54) + (cntB == 7'd53) + (cntB == 7'd52) + (cntB == 7'd51) + (cntB == 7'd50) + (cntB == 7'd49) + (cntB == 7'd48) + (cntB == 7'd47) + (cntB == 7'd46) + (cntB == 7'd45) + (cntB == 7'd44) + (cntB == 7'd43) + (cntB == 7'd42) + (cntB == 7'd41) + (cntB == 7'd40) + (cntB == 7'd39) + (cntB == 7'd38) + (cntB == 7'd37) + (cntB == 7'd36) + (cntB == 7'd35) + (cntB == 7'd34) + (cntB == 7'd33) + (cntB == 7'd32) + (cntB == 7'd31) + (cntB == 7'd30) + (cntB == 7'd29) + (cntB == 7'd28) + (cntB == 7'd27) + (cntB == 7'd26) + (cntB == 7'd25) + (cntB == 7'd24) + (cntB == 7'd23) + (cntB == 7'd22) + (cntB == 7'd21) + (cntB == 7'd20) + (cntB == 7'd19) + (cntB == 7'd18) + (cntB <= 7'd17); // Should not create decoder wire [6:0] twiceCntC = cntC == 7'd127 ? (7'd127 * 7'd2) : cntC == 7'd126 ? (7'd126 * 7'd2) : cntC == 7'd125 ? (7'd125 * 7'd2) : cntC == 7'd124 ? (7'd124 * 7'd2) : cntC == 7'd123 ? (7'd123 * 7'd2) : cntC == 7'd122 ? (7'd122 * 7'd2) : cntC == 7'd121 ? (7'd121 * 7'd2) : cntC == 7'd120 ? (7'd120 * 7'd2) : cntC == 7'd119 ? (7'd119 * 7'd2) : cntC == 7'd118 ? (7'd118 * 7'd2) : cntC == 7'd117 ? (7'd117 * 7'd2) : cntC == 7'd116 ? (7'd116 * 7'd2) : cntC == 7'd115 ? (7'd115 * 7'd2) : cntC == 7'd114 ? (7'd114 * 7'd2) : cntC == 7'd113 ? (7'd113 * 7'd2) : cntC == 7'd112 ? (7'd112 * 7'd2) : cntC == 7'd111 ? (7'd111 * 7'd2) : cntC == 7'd110 ? (7'd110 * 7'd2) : cntC == 7'd109 ? (7'd109 * 7'd2) : cntC == 7'd108 ? (7'd108 * 7'd2) : cntC == 7'd107 ? (7'd107 * 7'd2) : cntC == 7'd106 ? (7'd106 * 7'd2) : cntC == 7'd105 ? (7'd105 * 7'd2) : cntC == 7'd104 ? (7'd104 * 7'd2) : cntC == 7'd103 ? (7'd103 * 7'd2) : cntC == 7'd102 ? (7'd102 * 7'd2) : cntC == 7'd101 ? (7'd101 * 7'd2) : cntC == 7'd100 ? (7'd100 * 7'd2) : cntC == 7'd99 ? (7'd99 * 7'd2) : cntC == 7'd98 ? (7'd98 * 7'd2) : cntC == 7'd97 ? (7'd97 * 7'd2) : cntC == 7'd96 ? (7'd96 * 7'd2) : cntC == 7'd95 ? (7'd95 * 7'd2) : cntC == 7'd94 ? (7'd94 * 7'd2) : cntC == 7'd93 ? (7'd93 * 7'd2) : cntC == 7'd92 ? (7'd92 * 7'd2) : cntC == 7'd91 ? (7'd91 * 7'd2) : cntC == 7'd90 ? (7'd90 * 7'd2) : cntC == 7'd89 ? (7'd89 * 7'd2) : cntC == 7'd88 ? (7'd88 * 7'd2) : cntC == 7'd87 ? (7'd87 * 7'd2) : cntC == 7'd86 ? (7'd86 * 7'd2) : cntC == 7'd85 ? (7'd85 * 7'd2) : cntC == 7'd84 ? (7'd84 * 7'd2) : cntC == 7'd83 ? (7'd83 * 7'd2) : cntC == 7'd82 ? (7'd82 * 7'd2) : cntC == 7'd81 ? (7'd81 * 7'd2) : cntC == 7'd80 ? (7'd80 * 7'd2) : cntC == 7'd79 ? (7'd79 * 7'd2) : cntC == 7'd78 ? (7'd78 * 7'd2) : cntC == 7'd77 ? (7'd77 * 7'd2) : cntC == 7'd76 ? (7'd76 * 7'd2) : cntC == 7'd75 ? (7'd75 * 7'd2) : cntC == 7'd74 ? (7'd74 * 7'd2) : cntC == 7'd73 ? (7'd73 * 7'd2) : cntC == 7'd72 ? (7'd72 * 7'd2) : cntC == 7'd71 ? (7'd71 * 7'd2) : cntC == 7'd70 ? (7'd70 * 7'd2) : cntC == 7'd69 ? (7'd69 * 7'd2) : cntC == 7'd68 ? (7'd68 * 7'd2) : cntC == 7'd67 ? (7'd67 * 7'd2) : cntC == 7'd66 ? (7'd66 * 7'd2) : cntC == 7'd65 ? (7'd65 * 7'd2) : cntC == 7'd64 ? (7'd64 * 7'd2) : cntC == 7'd63 ? (7'd63 * 7'd2) : cntC == 7'd62 ? (7'd62 * 7'd2) : cntC == 7'd61 ? (7'd61 * 7'd2) : cntC == 7'd60 ? (7'd60 * 7'd2) : cntC == 7'd59 ? (7'd59 * 7'd2) : cntC == 7'd58 ? (7'd58 * 7'd2) : cntC == 7'd57 ? (7'd57 * 7'd2) : cntC == 7'd56 ? (7'd56 * 7'd2) : cntC == 7'd55 ? (7'd55 * 7'd2) : cntC == 7'd54 ? (7'd54 * 7'd2) : cntC == 7'd53 ? (7'd53 * 7'd2) : cntC == 7'd52 ? (7'd52 * 7'd2) : cntC == 7'd51 ? (7'd51 * 7'd2) : cntC == 7'd50 ? (7'd50 * 7'd2) : cntC == 7'd49 ? (7'd49 * 7'd2) : cntC == 7'd48 ? (7'd48 * 7'd2) : cntC == 7'd47 ? (7'd47 * 7'd2) : cntC == 7'd46 ? (7'd46 * 7'd2) : cntC == 7'd45 ? (7'd45 * 7'd2) : cntC == 7'd44 ? (7'd44 * 7'd2) : cntC == 7'd43 ? (7'd43 * 7'd2) : cntC == 7'd42 ? (7'd42 * 7'd2) : cntC == 7'd41 ? (7'd41 * 7'd2) : cntC == 7'd40 ? (7'd40 * 7'd2) : cntC == 7'd39 ? (7'd39 * 7'd2) : cntC == 7'd38 ? (7'd38 * 7'd2) : cntC == 7'd37 ? (7'd37 * 7'd2) : cntC == 7'd36 ? (7'd36 * 7'd2) : cntC == 7'd35 ? (7'd35 * 7'd2) : cntC == 7'd34 ? (7'd34 * 7'd2) : cntC == 7'd33 ? (7'd33 * 7'd2) : cntC == 7'd32 ? (7'd32 * 7'd2) : cntC == 7'd31 ? (7'd31 * 7'd2) : cntC == 7'd30 ? (7'd30 * 7'd2) : cntC == 7'd29 ? (7'd29 * 7'd2) : cntC == 7'd28 ? (7'd28 * 7'd2) : cntC == 7'd27 ? (7'd27 * 7'd2) : cntC == 7'd26 ? (7'd26 * 7'd2) : cntC == 7'd25 ? (7'd25 * 7'd2) : cntC == 7'd24 ? (7'd24 * 7'd2) : cntC == 7'd23 ? (7'd23 * 7'd2) : cntC == 7'd22 ? (7'd22 * 7'd2) : cntC == 7'd21 ? (7'd21 * 7'd2) : cntC == 7'd20 ? (7'd20 * 7'd2) : cntC == 7'd19 ? (7'd19 * 7'd2) : cntC == 7'd18 ? (7'd18 * 7'd2) : cntC == 7'd17 ? (7'd17 * 7'd2) : cntC == 7'd16 ? (7'd16 * 7'd2) : cntC == 7'd15 ? (7'd15 * 7'd2) : cntC == 7'd14 ? (7'd14 * 7'd2) : cntC == 7'd13 ? (7'd13 * 7'd2) : cntC == 7'd12 ? (7'd12 * 7'd2) : cntC == 7'd11 ? (7'd11 * 7'd2) : cntC == 7'd10 ? (7'd10 * 7'd2) : cntC == 7'd9 ? (7'd9 * 7'd2) : cntC == 7'd8 ? (7'd8 * 7'd2) : cntC == 7'd7 ? (7'd7 * 7'd2) : cntC == 7'd6 ? (7'd6 * 7'd2) : cntC == 7'd5 ? (7'd5 * 7'd2) : cntC == 7'd4 ? (7'd4 * 7'd2) : cntC == 7'd3 ? (7'd3 * 7'd2) : cntC == 7'd2 ? (7'd2 * 7'd2) : cntC == 7'd1 ? (7'd1 * 7'd2) : 7'd0; always @(posedge clk) begin `check(cntAOneHot[cntA], 1'b1); for (int i = 0; i < $bits(cntAOneHot); i = i + 1) begin if (i == int'(cntA)) continue; `check(cntAOneHot[i], 1'b0); end `check(notCntAOneHot[~cntA], 1'b1); for (int i = 0; i < $bits(notCntAOneHot); i = i + 1) begin if (i == {25'd0, ~cntA}) continue; `check(notCntAOneHot[i], 1'b0); end `check(stupidWayToWriteConstOne, 1'b1); `check(twiceCntC, cntC * 7'd2); end endmodule verilator-5.042/test_regress/t/t_priority_case.out0000644000542200017500000000156115101701376023021 0ustar mahmoudyfreeshell%Warning-CASEOVERLAP: t/t_priority_case.v:34:7: Case item ignored: every matching value is covered by an earlier condition 34 | 2'b ?1: out1 = 3'd1; | ^~~~~~ t/t_priority_case.v:33:7: ... Location of previous condition 33 | 2'b ?1: out1 = 3'd0; | ^~~~~~ ... For warning description see https://verilator.org/warn/CASEOVERLAP?v=latest ... Use "/* verilator lint_off CASEOVERLAP */" and lint_on around source to disable this message. %Warning-CASEOVERLAP: t/t_priority_case.v:44:7: Case item ignored: every matching value is covered by an earlier condition 44 | 2'b ?1: out1 = 3'd1; | ^~~~~~ t/t_priority_case.v:43:7: ... Location of previous condition 43 | 2'b ?1: out1 = 3'd0; | ^~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_lint_noreturn_param.v0000644000542200017500000000067615101701376023673 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; // verilator lint_off UNDRIVEN function integer log2m1(); // <--- Warning: No return endfunction localparam WIDTH = log2m1(); initial begin if (WIDTH !== {32{1'bx}}) $stop; $finish; end endmodule verilator-5.042/test_regress/t/t_time_sc_bad.out0000644000542200017500000000030615101701376022372 0ustar mahmoudyfreeshell%Error: SystemC's sc_set_time_resolution is 10^-9, which does not match Verilog timeprecision 10^-12. Suggest use 'sc_set_time_resolution(1s)', or Verilator '--timescale-override 1s/1s' Aborting... verilator-5.042/test_regress/t/t_var_types_bad.v0000644000542200017500000000316615101701376022430 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; // IEEE: integer_atom_type byte d_byte; shortint d_shortint; int d_int; longint d_longint; integer d_integer; time d_time; chandle d_chandle; // IEEE: integer_atom_type bit d_bit; logic d_logic; reg d_reg; bit [0:0] d_bit1; logic [0:0] d_logic1; reg [0:0] d_reg1; bit d_bitz; logic d_logicz; reg d_regz; // IEEE: non_integer_type //UNSUP shortreal d_shortreal; real d_real; realtime d_realtime; initial begin // below errors might cause spurious warnings // verilator lint_off WIDTH d_bitz[0] = 1'b1; // Illegal range d_logicz[0] = 1'b1; // Illegal range d_regz[0] = 1'b1; // Illegal range `ifndef VERILATOR //UNSUPPORTED, it's just a 64 bit int right now d_chandle[0] = 1'b1; // Illegal `endif d_real[0] = 1'b1; // Illegal d_realtime[0] = 1'b1; // Illegal // verilator lint_on WIDTH d_byte[0] = 1'b1; // OK d_shortint[0] = 1'b1; // OK d_int[0] = 1'b1; // OK d_longint[0] = 1'b1; // OK d_integer[0] = 1'b1; // OK d_time[0] = 1'b1; // OK d_bit1[0] = 1'b1; // OK d_logic1[0] = 1'b1; // OK d_reg1[0] = 1'b1; // OK end endmodule verilator-5.042/test_regress/t/t_lint_declfilename_bbox.v0000644000542200017500000000060115101701376024245 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t_lint_declfilename_bbox (); parameter IN = 0; if (IN) begin : gen_hasbbox // Should not warn, see bug2430 BLACKBOXED bboxed (); end endmodule verilator-5.042/test_regress/t/t_clk_concat.vlt0000644000542200017500000000044315101701376022241 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. // SPDX-License-Identifier: CC0-1.0 `verilator_config clocker -module "t" -var "clk*" no_clocker -module "t" -var "data_in" verilator-5.042/test_regress/t/t_interface_array_bad.py0000755000542200017500000000076615101701376023743 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_cast_size_bad.out0000644000542200017500000000144115101701376022734 0ustar mahmoudyfreeshell%Error: t/t_cast_size_bad.v:14:15: Size-changing cast to zero or negative size : ... note: In instance 't' 14 | b = (-1)'(a); | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Warning-WIDTHEXPAND: t/t_cast_size_bad.v:14:9: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits. : ... note: In instance 't' 14 | b = (-1)'(a); | ^ ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_timing_sched.v0000644000542200017500000000273115101701376022240 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; logic clk1 = 0; assign #3 clk1 = ~clk1; logic clk2 = 0; assign #11 clk2 = ~clk2; int a1 = 0; int b1 = 0; always @(posedge clk1) #4 a1 = a1 + 1; always @(posedge clk1) @(posedge clk2) b1 = b1 + 1; int a2 = 0; always_comb begin // verilator lint_off MULTIDRIVEN a2 = a1 << 1; // verilator lint_on MULTIDRIVEN `ifdef TEST_VERBOSE $display("[%0t] a2 = %0d", $time, a2); `endif end int b2 = 0; always_comb begin // verilator lint_off MULTIDRIVEN b2 = b1 << 2; // verilator lint_on MULTIDRIVEN `ifdef TEST_VERBOSE $display("[%0t] b2 = %0d", $time, b2); `endif end int c1 = 0; int c2 = 0; always @(b2, c1) begin c2 = c1 >> 3; c1 = b2 << 3; end always @(posedge clk1) if (a2 != a1 << 1) $stop; always @(posedge clk2) #1 if (b2 != b1 << 2) $stop; initial #78 begin `ifdef TEST_VERBOSE $display("a1=%0d, b1=%0d, a2=%0d, b2=%0d, c1=%0d, c2=%0d", a1, b1, a2, b2, c1, c2); `endif if (a1 != 12) $stop; if (b1 != 4) $stop; if (a2 != a1 << 1) $stop; if (b2 != b1 << 2) $stop; if (c1 != b2 << 3) $stop; if (c2 != c1 >> 3) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_let_recurse_bad.py0000755000542200017500000000076615101701376023121 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_vpi_cb_iter.cpp0000644000542200017500000001253415101701376022407 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2020 by Wilson Snyder and Marlon James. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "verilated.h" #include "verilated_vpi.h" #include VM_PREFIX_INCLUDE #include "vpi_user.h" #include #include #include #include #include extern "C" { #include } // These require the above. Comment prevents clang-format moving them #include "TestCheck.h" #include "TestSimulator.h" #include "TestVpi.h" int errors = 0; TestVpiHandle vh_value_cb; TestVpiHandle vh_rw_cb; unsigned int last_value_cb_time = 0; unsigned int last_rw_cb_time = 0; unsigned int main_time = 0; static void reregister_value_cb(); static void reregister_rw_cb(); static int the_value_callback(p_cb_data cb_data) { reregister_value_cb(); return 0; } static int the_rw_callback(p_cb_data cb_data) { reregister_rw_cb(); return 0; } static void reregister_value_cb() { if (vh_value_cb) { if (verbose) vpi_printf(const_cast("- Removing cbValueChange callback\n")); int ret = vpi_remove_cb(vh_value_cb); vh_value_cb.freed(); TEST_CHECK_EQ(ret, 1); if (verbose) { vpi_printf(const_cast("- last_value_cb_time %d , main_time %d\n"), last_value_cb_time, main_time); } TEST_CHECK_NE(main_time, last_value_cb_time); last_value_cb_time = main_time; } if (verbose) vpi_printf(const_cast("- Registering cbValueChange callback\n")); t_cb_data cb_data_testcase; bzero(&cb_data_testcase, sizeof(cb_data_testcase)); cb_data_testcase.cb_rtn = the_value_callback; cb_data_testcase.reason = cbValueChange; TestVpiHandle vh1 = VPI_HANDLE("count"); TEST_CHECK_NZ(vh1); s_vpi_value v; v.format = vpiSuppressVal; cb_data_testcase.obj = vh1; cb_data_testcase.value = &v; vh_value_cb = vpi_register_cb(&cb_data_testcase); TEST_CHECK_NZ(vh_value_cb); } static void reregister_rw_cb() { if (vh_rw_cb) { if (verbose) vpi_printf(const_cast("- Removing cbReadWriteSynch callback\n")); int ret = vpi_remove_cb(vh_rw_cb); vh_rw_cb.freed(); TEST_CHECK_EQ(ret, 1); if (verbose) { vpi_printf(const_cast("- last_rw_cb_time %d , main_time %d\n"), last_rw_cb_time, main_time); } TEST_CHECK_NE(main_time, last_rw_cb_time); last_rw_cb_time = main_time; } if (verbose) vpi_printf(const_cast("- Registering cbReadWriteSynch callback\n")); t_cb_data cb_data_testcase; bzero(&cb_data_testcase, sizeof(cb_data_testcase)); cb_data_testcase.cb_rtn = the_rw_callback; cb_data_testcase.reason = cbReadWriteSynch; vh_rw_cb = vpi_register_cb(&cb_data_testcase); TEST_CHECK_NZ(vh_rw_cb); } static int the_filler_callback(p_cb_data cb_data) { return 0; } static void register_filler_cb() { if (verbose) { vpi_printf(const_cast("- Registering filler cbReadWriteSynch callback\n")); } t_cb_data cb_data_1; bzero(&cb_data_1, sizeof(cb_data_1)); cb_data_1.cb_rtn = the_filler_callback; cb_data_1.reason = cbReadWriteSynch; TestVpiHandle cb_data_1_h = vpi_register_cb(&cb_data_1); TEST_CHECK_NZ(cb_data_1_h); if (verbose) { vpi_printf(const_cast("- Registering filler cbValueChange callback\n")); } t_cb_data cb_data_2; bzero(&cb_data_2, sizeof(cb_data_2)); cb_data_2.cb_rtn = the_filler_callback; cb_data_2.reason = cbValueChange; TestVpiHandle vh2 = VPI_HANDLE("count"); TEST_CHECK_NZ(vh2); s_vpi_value v; v.format = vpiSuppressVal; cb_data_2.obj = vh2; cb_data_2.value = &v; TestVpiHandle cb_data_2_h = vpi_register_cb(&cb_data_2); TEST_CHECK_NZ(cb_data_2_h); } double sc_time_stamp() { return main_time; } int main(int argc, char** argv) { const std::unique_ptr contextp{new VerilatedContext}; uint64_t sim_time = 100; contextp->debug(0); contextp->commandArgs(argc, argv); const std::unique_ptr topp{new VM_PREFIX{contextp.get(), // Note null name - we're flattening it out ""}}; reregister_value_cb(); TEST_CHECK_NZ(vh_value_cb); reregister_rw_cb(); TEST_CHECK_NZ(vh_rw_cb); register_filler_cb(); topp->eval(); topp->clk = 0; while (main_time < sim_time && !contextp->gotFinish()) { main_time += 1; if (verbose) VL_PRINTF("Sim Time %d got_error %d\n", main_time, errors); topp->clk = !topp->clk; topp->eval(); VerilatedVpi::callValueCbs(); VerilatedVpi::callCbs(cbReadWriteSynch); if (errors) vl_stop(__FILE__, __LINE__, "TOP-cpp"); } if (!contextp->gotFinish()) { vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); } topp->final(); return errors ? 10 : 0; } verilator-5.042/test_regress/t/t_foreach_blkname.v0000644000542200017500000000062215101701376022700 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; function void func(); int a[2]; begin int t; end foreach (a[i]) begin end begin int x; end endfunction endmodule verilator-5.042/test_regress/t/t_trace_complex_structs_saif.py0000755000542200017500000000131215101701376025401 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_complex.v" test.golden_filename = "t/t_trace_complex_structs_saif.out" test.compile(verilator_flags2=['--cc --trace-saif --trace-structs --no-trace-params']) test.execute() test.saif_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_case_onehot.v0000644000542200017500000000503515101701376022072 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [2:0] in = (crc[1:0]==0 ? 3'd0 : crc[1:0]==0 ? 3'd1 : crc[1:0]==0 ? 3'd2 : 3'd4); /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [31:0] out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out (out[31:0]), // Inputs .clk (clk), .in (in[2:0])); // Aggregate outputs into a single result vector wire [63:0] result = {32'h0, out}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h704ca23e2a83e1c5 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs out, // Inputs clk, in ); // Replace this module with the device under test. // // Change the code in the t module to apply values to the inputs and // merge the output values into the result vector. input clk; input [2:0] in; output reg [31:0] out; localparam ST_0 = 0; localparam ST_1 = 1; localparam ST_2 = 2; always @(posedge clk) begin case (1'b1) // synopsys parallel_case in[ST_0]: out <= 32'h1234; in[ST_1]: out <= 32'h4356; in[ST_2]: out <= 32'h9874; default: out <= 32'h1; endcase end endmodule verilator-5.042/test_regress/t/t_math_vgen.v0000644000542200017500000002466315101701376021563 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg check; initial check = 1'b0; // verilator lint_off WIDTH //============================================================ reg [ 1:0] W0095; //=3 reg [ 58:0] W0101; //=0000000FFFFFFFF always @(posedge clk) begin if (cyc==1) begin W0095 = ((2'h3)); W0101 = ({27'h0,({16{(W0095)}})}); end end always @(posedge clk) begin if (cyc==2) begin if ((W0101) != (59'h0FFFFFFFF)) if (check) $stop; end end //============================================================ reg [ 0:0] W1243; //=1 always @(posedge clk) begin if (cyc==1) begin W1243 = ((1'h1)); end end always @(posedge clk) begin if (cyc==2) begin // Width violation, but still... if (((-W1243) < 32'h01) != (1'h0)) if (check) $stop; if (({32{W1243}} < 32'h01) != (1'h0)) if (check) $stop; end end //============================================================ reg [ 0:0] W0344; //=0 always @(posedge clk) begin if (cyc==1) begin W0344 = 1'b0; end end always @(posedge clk) begin if (cyc==2) begin if ((W0344) != (1'h0)) if (check) $stop; if (({116{(((- 95'h7FFFFFFFFFFFFFFFFFFFFFFF) ^ 95'h7FFFFFFFFFFFFFFFFFFFFFFF ) == ({94'h0,W0344}))}})) if (check) $stop; end end //============================================================ reg [ 63:0] W0372; //=FFFFFFFFFFFFFFFF reg [118:0] W0420; //=7FFFFFFFFFFFFFFFFFFFFFFFFFFFFF reg [115:0] W0421; //=00000000000000000000000000000 always @(posedge clk) begin if (cyc==1) begin W0372 = ({64{((1'h1))}}); W0421 = 116'h0; W0420 = ({119{((W0372) <= (W0372))}}); end end always @(posedge clk) begin if (cyc==2) begin if ((W0420[(- (W0421[115:110]))]) != (1'h1)) if (check) $stop; end end //============================================================ // gcc_2_96_bug reg [ 31:0] W0161; //=FFFFFFFF reg [ 62:0] W0217; //=0000000000000000 reg [ 53:0] W0219; //=00000000000000 always @(posedge clk) begin if (cyc==1) begin W0161 = 32'hFFFFFFFF; W0217 = 63'h0; W0219 = 54'h0; end end always @(posedge clk) begin if (cyc==2) begin if ((W0161) != (32'hFFFFFFFF)) if (check) $stop; if (((- (W0161)) & ((W0217[62:31]) & ({25'h0,(W0219[53:47])}))) != (32'h00000000)) if (check) $stop; end end //============================================================ reg [119:0] W0592; //=000000000000000000000000000000 reg [ 7:0] W0593; //=70 always @(posedge clk) begin if (cyc==1) begin W0593 = (((8'h90)) * ((8'hFF))); W0592 = 120'h000000000000000000000000000000; end end always @(posedge clk) begin if (cyc==2) begin if (((W0592[119:9]) >> ((W0593))) != (111'h0000000000000000000000000000)) if (check) $stop; end end //============================================================ reg [127:0] WA1063 ; //=00000000000000000000000000000001 reg [ 34:0] WA1064 /*verilator public*/; //=7FFFFFFFF reg [ 62:0] WA1065 ; //=0000000000000000 reg [ 89:0] WA1066 /*verilator public*/; //=00000000000000000000001 reg [ 34:0] WA1067 ; //=7FFFFFFFF reg [111:0] WA1068; always @(check) begin WA1067 = (~ (35'h0)); WA1066 = (90'h00000000000000000000001); WA1065 = (WA1066[89:27]); WA1064 = (WA1067); WA1063 = (~ ((~ (128'hffffffffffffffffffffffffffffffff)) ^ (~ (128'h00000000000000000000000000000001)))); end always @(posedge clk) begin if (cyc==2) begin if ((WA1063[(WA1064[(WA1065[((5'h04) | (5'h0))+:4])+:3])+:112]) != 112'h0) if (check) $stop; end end //============================================================ reg [127:0] WB1063 ; //=00000000000000000000000000000001 reg [ 34:0] WB1064 /*verilator public*/; //=7FFFFFFFF reg [ 62:0] WB1065 ; //=0000000000000000 reg [ 89:0] WB1066 /*verilator public*/; //=00000000000000000000001 reg [ 34:0] WB1067 ; //=7FFFFFFFF reg [111:0] WB1068; always @(posedge clk) begin if (cyc==1) begin WB1067 = (~ (35'h0)); WB1066 = (90'h00000000000000000000001); end if (cyc==2) WB1065 <= (WB1066[89:27]); if (cyc==3) WB1064 <= (WB1067); if (cyc==4) WB1063 <= (~ ((~ (128'hffffffffffffffffffffffffffffffff)) ^ (~ (128'h00000000000000000000000000000001)))); if (cyc==5) WB1068 <= (WB1063[(WB1064[(WB1065[((5'h04) | (5'h0))+:4])+:3])+:112]); end always @(posedge clk) begin if (cyc==9) begin if (WB1068 != 112'h0) if (check) $stop; if ((WB1063[(WB1064[(WB1065[((5'h04) | (5'h0))+:4])+:3])+:112]) != 112'h0) if (check) $stop; end end //============================================================ reg signed [ 60:0] WC0064 ; //=1FFFFFFFFFFFFFFF reg signed [ 6:0] WC0065 ; //=00 reg signed [ 62:0] WC0067 /*verilator public*/; //=33250A3BFFFFFFFF always @(check) begin WC0064 = 61'sh1FFFFFFFFFFFFFFF; WC0065 = 7'sh0; if (((WC0064) >>> (WC0065)) != 61'sh1fffffffffffffff) if (check) $stop; end //============================================================ reg signed [ 76:0] W0234 ; //=00000000000000000000 reg signed [ 7:0] W0235 /*verilator public*/; //=B6 always @(check) begin W0235 = 8'shb6; W0234 = ((77'sh0001ffffffffffffffff) >>> (W0235)); if ((W0234) != 77'sh0) if (check) $stop; end //============================================================ reg signed [ 30:0] W0146 ; //=00000001 always @(check) begin : Block71 W0146 = (31'sh00000001); if ((W0146 >>> 6'sh3f) != 31'sh0) if (check) $stop; end //============================================================ reg signed [ 54:0] W0857 /*verilator public*/; //=7FFFFFFFFFFFFF always @(check) begin : Block405 W0857 = 55'sh7fffffffffffff; if ((63'sh7fffffffffffffff >>> (W0857[54:54] ? 7'sh56 : 7'sh7f)) != 63'sh7fffffffffffffff) if (check) $stop; end //============================================================ always @(posedge clk) begin if ((((122'sh3ffffffffffffffd3e48e0900000001 >>> 8'shff) >>> 8'b1) ) != 122'sh3ffffffffffffffffffffffffffffff) if (check) $stop; if (((95'sh7fff_ffff_ffffffff_ffffffff < 95'sh4a76_3d8b_0f4e3995_1146e342) != 1'h0)) if (check) $stop; end //============================================================ reg signed [ 82:0] W0226 ; //=47A4301EE3FB4133EE3DA always_comb begin : Block144 W0226 = 83'sh47A4301EE3FB4133EE3DA; if ((W0226 >>> 8'sh1a) != 83'sh7ffffff1e90c07b8fed04) if (check) $stop; end //============================================================ reg signed [ 68:0] W0792 /*verilator public*/; //=169351569551247E0C reg signed [ 68:0] W0793 ; //=1FFFFFFFFF4EB1A91A always @(posedge clk) begin W0793 <= 69'sh1f_ffffffff_4eb1a91a; W0792 <= (W0793 * 69'sh1F_0E989F3E_F15F509E); if (W0792 != 69'sh16_93515695_51247E0C) if (check) $stop; end //============================================================ reg signed [ 2:0] DW0515 /*verilator public*/; //=7 always @(posedge clk) begin DW0515 <= 3'sh7; if ($signed({62'h0,DW0515[1'h1]}) != 63'sh0000000000000001) if (check) $stop; end //============================================================ reg signed [ 62:0] W0753 ; //=004E20004ED93E26 reg [ 2:0] W0772 /*verilator public*/; //=7 always @(posedge clk) begin W0753 <= 63'sh004E20004ED93E26; //(63'sh7fffffffffffffff + (63'sh464eac8c4ed93e27 & (63'sh08cf6243ffffffff))); W0772 <= 3'h7; if ((W0772[(W0753 < 63'sh0876c66a7e29fabf)]) != 1'h1) if (check) $stop; if ((W0772[(63'sh004E20004ED93E26 < 63'sh0876c66a7e29fabf)]) != 1'h1) if (check) $stop; end //============================================================ reg [ 98:0] W1027 ; //=7FFFFFFFFFFFFFFFFFFFFFFFF always @(posedge clk) begin W1027 <= ~99'h0; // verilator lint_off CMPCONST if (((1'sb1 < (95'sh7fffffffffffffffffffffff >= 95'sh09deb904ffffffffe062d44c))) != 1'h0) if (check) $stop; // verilator lint_on CMPCONST end //============================================================ reg signed [ 5:0] W123_is_3f ; //=3F always @(posedge clk) begin W123_is_3f <= 6'sh3f; end always @(posedge clk) begin if (((~ ((32'sh088d1bcb) <<< W123_is_3f)) >>> 6'sh3f) != 32'shffffffff) if (check) $stop; end //============================================================ reg signed [105: 0] W0032 /*verilator public*/; //=106'h3ff0000000100000000bd597bb1 always @(check) begin : Block237 W0032 = 106'sh3ff0000000100000000bd597bb1; if ((106'sh1ca0000000000000000b96b8dc2 / 106'sh3ff0000000100000000bd597bb1) != 106'sh3fffffffffffffffffffffffe36) if (check) $stop; if ((106'sh1ca0000000000000000b96b8dc2 / W0032) != 106'sh3fffffffffffffffffffffffe36) if (check) $stop; end //============================================================ reg signed [ 83: 0] W0024 ; //=84'h0000000000000e1fe9094 reg signed [ 83: 0] W0025 ; //=84'h0f66afffffffe308b3d7c always @(posedge clk) begin W0024 <= 84'h0000000000000e1fe9094; W0025 <= 84'h0f66afffffffe308b3d7c; if ((W0024 % W0025) != 84'sh0000000000000e1fe9094) if (check) $stop; end //============================================================ always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==18) begin check <= 1'b1; end if (cyc==20) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.042/test_regress/t/t_hier_block_struct.v0000644000542200017500000000511315101701376023305 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Varun Koyyalagunta. // SPDX-License-Identifier: CC0-1.0 typedef struct packed { logic x; } nested_named_t; typedef struct packed { struct packed { logic x; } nested_anonymous; nested_named_t nested_named; logic [1:0] x; } nibble_t; module t( clk ); input clk; integer cyc = 0; logic [63:0] crc; logic [63:0] sum; // Take CRC data and apply to testblock inputs nibble_t[7:0] in; assign in = crc[31:0]; nibble_t[7:0] out; Test test( .out0 ({out[1], out[0]}), .out1 ({{out[5], out[4]}, {out[3], out[2]}}), .out2 (out[6]), .out3 (out[7]), .clk (clk), .in0 (in[0]), .in1 (in[1]), .in2 ({in[5], in[4], in[3], in[2]}), .in3 ({in[7], in[6]})); // Aggregate outputs into a single result vector wire [63:0] result = {32'h0, out}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc == 0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc < 10) begin sum <= '0; end else if (cyc < 90) begin end else if (cyc == 99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h4afe43fb79d7b71e if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test( // Outputs output nibble_t [1:0] out0, output nibble_t [1:0] out1[2], output nibble_t out2, output nibble_t out3, // Inputs input clk, input nibble_t in0, input nibble_t in1, input nibble_t [3:0] in2, input nibble_t in3[2] ); /*verilator hier_block*/ always @(posedge clk) begin {out3, out2, out1[0], out1[1], out0} <= {in3[0], in3[1], in2, in1, in0}; end endmodule verilator-5.042/test_regress/t/t_timing_fork_join_forkproc.py0000755000542200017500000000114015101701376025216 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_timing_fork_join.v" test.compile(verilator_flags2=["--binary --ftaskify-all-forked"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_assoc_enum.v0000644000542200017500000000227215101701376021737 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); class X; typedef enum int { INITIAL, RUNNING, SUSPENDED, COMPLETING, DONE } state_t; static string state_names[state_t] = '{ INITIAL: "INITIAL", RUNNING: "RUNNING", SUSPENDED: "SUSPENDED", COMPLETING: "COMPLETING", DONE: "DONE" }; protected state_t state; function new(); this.state = INITIAL; `checks(state_names[this.state], "INITIAL"); this.state = RUNNING; `checks(state_names[this.state], "RUNNING"); endfunction endclass module t;/*AUTOARG*/ initial begin X x = new; $finish; end endmodule verilator-5.042/test_regress/t/t_vpi_module.v0000644000542200017500000000446715101701376021756 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2010 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifndef IVERILOG import "DPI-C" context function int mon_check(); `endif package somepackage; int someint /*verilator public_flat_rw*/; endpackage module t (/*AUTOARG*/ // Inputs clk ); `ifdef USE_DOLLAR_C32 `systemc_header extern "C" int mon_check(); `verilog `endif input clk; integer status; wire a, b, x; A \mod.a (/*AUTOINST*/ // Outputs .x (x), // Inputs .clk (clk), .a (a), .b (b)); // Test loop initial begin `ifdef IVERILOG status = $mon_check(); `elsif USE_DOLLAR_C32 status = $c32("mon_check()"); `else status = mon_check(); `endif if (status!=0) begin $write("%%Error: t_vpi_module.cpp:%0d: C Test failed\n", status); $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule : t module A(/*AUTOARG*/ // Outputs x, // Inputs clk, a, b ); input clk; input a, b; output x; wire y, c; B \mod_b$ (/*AUTOINST*/ // Outputs .y (y), // Inputs .b (b), .c (c)); C \mod\c$ (/*AUTOINST*/ // Outputs .x (x), // Inputs .clk (clk), .a (a), .y (y)); endmodule : A module B(/*AUTOARG*/ // Outputs y, // Inputs b, c ); /*verilator public_module*/ input b, c; output reg y; always @(*) begin : myproc y = b ^ c; end endmodule module C(/*AUTOARG*/ // Outputs x, // Inputs clk, a, y ); input clk; input a, y; output reg x /* verilator public_flat_rw */; always @(posedge clk) begin x <= a & y; end endmodule verilator-5.042/test_regress/t/t_implements_noinherit_bad.out0000644000542200017500000000041215101701376025201 0ustar mahmoudyfreeshell%Error: t/t_implements_noinherit_bad.v:14:16: Can't find definition of variable: 'IP' 14 | $display(IP); | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_disable_genfor2.v0000644000542200017500000000106015101701376022622 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t; for (genvar j = 0; j < 3; j++) begin : genblk initial begin : init int i; begin : named for (i = 0; i < 10; ++i) begin : loop if (i == 5) disable named; end end if (i != 5) $stop; end end initial begin #1; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_func_void.v0000644000542200017500000000166015101701376021557 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; int side_effect; function int f1; input int in; f1 = in + 1; side_effect += in + 1; endfunction class Cls; static function int initialize(); return 6; endfunction endclass initial begin int got; side_effect = 1; // got = f1(10); if (got != 11) $stop; if (side_effect != 12) $stop; // verilator lint_off IGNOREDRETURN f1(20); // verilator lint_on IGNOREDRETURN if (side_effect != 33) $stop; // void'(f1(30)); if (side_effect != 64) $stop; // void'(Cls::initialize()); // $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_class_assign_bad.py0000755000542200017500000000076615101701376023256 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_unicode.py0000755000542200017500000000266715101701376021427 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = test.obj_dir + "/t_unicode.v" def c(code): # Appease https://www.virustotal.com NANO-Antivirus gives Trojan.Script.Vbs-heuristic flag return eval("c" + "h" + "r(" + str(code) + ")") # pylint: disable=eval-used # Greek Hi hi = "Greek: " + c(0xce) + c(0xb3) + c(0xce) + c(0xb5) + c(0xce) + c(0xb9) + c(0xce) + c(0xb1) def gen(filename): with open(filename, 'w', encoding="latin-1") as fh: fh.write(c(0xEF)) fh.write(c(0xBB)) fh.write(c(0xBF)) # BOM fh.write("// Bom\n") fh.write("// Generated by t_unicode.py\n") fh.write("module t;\n") fh.write(" // " + hi + "\n") fh.write(" initial begin\n") fh.write(" $write(\"" + hi + "\\n\");\n") fh.write(" $write(\"*-* All Finished *-*\\n\");\n") fh.write(" $finish;\n") fh.write(" end\n") fh.write("endmodule\n") gen(test.top_filename) test.compile() test.execute() test.file_grep(test.run_log_filename, hi) test.passes() verilator-5.042/test_regress/t/t_json_only_debugcheck.out0000644000542200017500000061265215101701376024334 0ustar mahmoudyfreeshell{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"(E)","stdPackagep":"UNLINKED","evalp":"(F)","evalNbap":"(G)","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"(H)", "modulesp": [ {"type":"MODULE","name":"$root","addr":"(I)","loc":"d,11:8,11:9","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"$root","level":1,"modPublic":true,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"clk","addr":"(J)","loc":"d,15:10,15:13","dtypep":"(K)","origName":"clk","isSc":false,"isPrimaryIO":true,"isPrimaryClock":true,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"t.e","addr":"(L)","loc":"d,24:9,24:10","dtypep":"(M)","origName":"e","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"my_t","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"__Vtrigprevexpr___TOP__clk__0","addr":"(N)","loc":"d,11:8,11:9","dtypep":"(K)","origName":"__Vtrigprevexpr___TOP__clk__0","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"MODULETEMP","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"t.cyc","addr":"(O)","loc":"d,23:17,23:20","dtypep":"(P)","origName":"cyc","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"integer","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"__VactIterCount","addr":"(Q)","loc":"d,11:8,11:9","dtypep":"(R)","origName":"__VactIterCount","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":true,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"MODULETEMP","dtypeName":"bit","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"__VactTriggered","addr":"(S)","loc":"d,11:8,11:9","dtypep":"(T)","origName":"__VactTriggered","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"MODULETEMP","dtypeName":"","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"__VnbaTriggered","addr":"(U)","loc":"d,11:8,11:9","dtypep":"(T)","origName":"__VnbaTriggered","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"MODULETEMP","dtypeName":"","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"CELL","name":"$unit","addr":"(V)","loc":"a,0:0,0:0","origName":"__024unit","recursive":false,"modp":"(E)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []}, {"type":"TOPSCOPE","name":"","addr":"(H)","loc":"d,11:8,11:9","senTreesp": [], "scopep": [ {"type":"SCOPE","name":"TOP","addr":"(W)","loc":"d,11:8,11:9","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(I)","varsp": [],"blocksp": [],"inlinesp": []} ]}, {"type":"CFUNC","name":"_eval_static","addr":"(X)","loc":"a,0:0,0:0","slow":true,"isStatic":false,"dpiExportDispatcher":false,"dpiExportImpl":false,"dpiImportPrototype":false,"dpiImportWrapper":false,"dpiContext":false,"isConstructor":false,"isDestructor":false,"isVirtual":false,"isCoroutine":false,"needProcess":false,"scopep":"(W)","argsp": [],"varsp": [], "stmtsp": [ {"type":"STMTEXPR","name":"","addr":"(Y)","loc":"d,11:8,11:9", "exprp": [ {"type":"CCALL","name":"","addr":"(Z)","loc":"d,11:8,11:9","dtypep":"(AB)","funcName":"_eval_static__TOP","funcp":"(BB)","argsp": []} ]}, {"type":"ASSIGN","name":"","addr":"(CB)","loc":"d,63:22,63:25","dtypep":"(DB)", "rhsp": [ {"type":"VARREF","name":"clk","addr":"(EB)","loc":"d,63:22,63:25","dtypep":"(DB)","access":"RD","varp":"(J)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "lhsp": [ {"type":"VARREF","name":"__Vtrigprevexpr___TOP__clk__0","addr":"(FB)","loc":"d,63:22,63:25","dtypep":"(DB)","access":"WR","varp":"(N)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": []} ]}, {"type":"CFUNC","name":"_eval_static__TOP","addr":"(BB)","loc":"d,11:8,11:9","slow":true,"isStatic":false,"dpiExportDispatcher":false,"dpiExportImpl":false,"dpiImportPrototype":false,"dpiImportWrapper":false,"dpiContext":false,"isConstructor":false,"isDestructor":false,"isVirtual":false,"isCoroutine":false,"needProcess":false,"scopep":"(W)","argsp": [],"varsp": [], "stmtsp": [ {"type":"ASSIGN","name":"","addr":"(GB)","loc":"d,23:23,23:24","dtypep":"(P)", "rhsp": [ {"type":"CONST","name":"32'sh0","addr":"(HB)","loc":"d,23:23,23:24","dtypep":"(IB)"} ], "lhsp": [ {"type":"VARREF","name":"t.cyc","addr":"(JB)","loc":"d,23:23,23:24","dtypep":"(P)","access":"WR","varp":"(O)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": []} ]}, {"type":"CFUNC","name":"_eval_initial","addr":"(KB)","loc":"a,0:0,0:0","slow":true,"isStatic":false,"dpiExportDispatcher":false,"dpiExportImpl":false,"dpiImportPrototype":false,"dpiImportWrapper":false,"dpiContext":false,"isConstructor":false,"isDestructor":false,"isVirtual":false,"isCoroutine":false,"needProcess":false,"scopep":"(W)","argsp": [],"varsp": [], "stmtsp": [ {"type":"STMTEXPR","name":"","addr":"(LB)","loc":"d,11:8,11:9", "exprp": [ {"type":"CCALL","name":"","addr":"(MB)","loc":"d,11:8,11:9","dtypep":"(AB)","funcName":"_eval_initial__TOP","funcp":"(NB)","argsp": []} ]} ]}, {"type":"CFUNC","name":"_eval_initial__TOP","addr":"(NB)","loc":"d,11:8,11:9","slow":true,"isStatic":false,"dpiExportDispatcher":false,"dpiExportImpl":false,"dpiImportPrototype":false,"dpiImportWrapper":false,"dpiContext":false,"isConstructor":false,"isDestructor":false,"isVirtual":false,"isCoroutine":false,"needProcess":false,"scopep":"(W)","argsp": [], "varsp": [ {"type":"VAR","name":"__Vtemp_1","addr":"(OB)","loc":"d,49:120,49:121","dtypep":"(PB)","origName":"__Vtemp_1","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"STMTTEMP","dtypeName":"string","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ], "stmtsp": [ {"type":"ASSIGN","name":"","addr":"(QB)","loc":"d,32:9,32:10","dtypep":"(RB)", "rhsp": [ {"type":"CONST","name":"4'h3","addr":"(SB)","loc":"d,32:11,32:14","dtypep":"(RB)"} ], "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(TB)","loc":"d,32:7,32:8","dtypep":"(RB)","access":"WR","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": []}, {"type":"IF","name":"","addr":"(UB)","loc":"d,38:10,38:12", "condp": [ {"type":"NEQ","name":"","addr":"(VB)","loc":"d,38:26,38:29","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"4'h4","addr":"(WB)","loc":"d,38:31,38:34","dtypep":"(RB)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(XB)","loc":"d,38:15,38:16","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(YB)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(BC)","loc":"d,38:15,38:16","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(DC)","loc":"d,38:15,38:16","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(FC)","loc":"d,38:15,38:16","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(GC)","loc":"d,38:15,38:16","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ], "thensp": [ {"type":"DISPLAY","name":"","addr":"(HC)","loc":"d,38:43,38:49", "fmtp": [ {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:38: got='h%x exp='h4\\n","addr":"(IC)","loc":"d,38:43,38:49","dtypep":"(PB)", "exprsp": [ {"type":"ARRAYSEL","name":"","addr":"(JC)","loc":"d,38:122,38:123","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(KC)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(LC)","loc":"d,38:122,38:123","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(MC)","loc":"d,38:122,38:123","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(NC)","loc":"d,38:122,38:123","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(OC)","loc":"d,38:122,38:123","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ],"scopeNamep": []} ],"filep": []}, {"type":"STOP","name":"","addr":"(PC)","loc":"d,38:142,38:147","isFatal":false} ],"elsesp": []}, {"type":"IF","name":"","addr":"(QC)","loc":"d,39:10,39:12", "condp": [ {"type":"NEQ","name":"","addr":"(RC)","loc":"d,39:34,39:37","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"4'h1","addr":"(SC)","loc":"d,39:39,39:42","dtypep":"(RB)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(TC)","loc":"d,39:15,39:16","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(UC)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(VC)","loc":"d,39:15,39:16","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(WC)","loc":"d,39:15,39:16","dtypep":"(EC)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(XC)","loc":"d,39:15,39:16","dtypep":"(CC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(YC)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(ZC)","loc":"d,39:15,39:16","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(AD)","loc":"d,39:15,39:16","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(BD)","loc":"d,39:15,39:16","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(CD)","loc":"d,39:15,39:16","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ]} ]} ], "thensp": [ {"type":"DISPLAY","name":"","addr":"(DD)","loc":"d,39:51,39:57", "fmtp": [ {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:39: got='h%x exp='h1\\n","addr":"(ED)","loc":"d,39:51,39:57","dtypep":"(PB)", "exprsp": [ {"type":"ARRAYSEL","name":"","addr":"(FD)","loc":"d,39:130,39:131","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(GD)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(HD)","loc":"d,39:130,39:131","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(ID)","loc":"d,39:130,39:131","dtypep":"(EC)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(JD)","loc":"d,39:130,39:131","dtypep":"(CC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(KD)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(LD)","loc":"d,39:130,39:131","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(MD)","loc":"d,39:130,39:131","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(ND)","loc":"d,39:130,39:131","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(OD)","loc":"d,39:130,39:131","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ]} ],"scopeNamep": []} ],"filep": []}, {"type":"STOP","name":"","addr":"(PD)","loc":"d,39:158,39:163","isFatal":false} ],"elsesp": []}, {"type":"IF","name":"","addr":"(QD)","loc":"d,40:10,40:12", "condp": [ {"type":"NEQ","name":"","addr":"(RD)","loc":"d,40:26,40:29","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"4'h1","addr":"(SD)","loc":"d,40:31,40:34","dtypep":"(RB)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(TD)","loc":"d,40:15,40:16","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(UD)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(VD)","loc":"d,40:15,40:16","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(WD)","loc":"d,40:15,40:16","dtypep":"(EC)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(XD)","loc":"d,40:15,40:16","dtypep":"(CC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(YD)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(ZD)","loc":"d,40:15,40:16","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(AE)","loc":"d,40:15,40:16","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(BE)","loc":"d,40:15,40:16","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(CE)","loc":"d,40:15,40:16","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ]} ]} ], "thensp": [ {"type":"DISPLAY","name":"","addr":"(DE)","loc":"d,40:43,40:49", "fmtp": [ {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:40: got='h%x exp='h1\\n","addr":"(EE)","loc":"d,40:43,40:49","dtypep":"(PB)", "exprsp": [ {"type":"ARRAYSEL","name":"","addr":"(FE)","loc":"d,40:122,40:123","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(GE)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(HE)","loc":"d,40:122,40:123","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(IE)","loc":"d,40:122,40:123","dtypep":"(EC)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(JE)","loc":"d,40:122,40:123","dtypep":"(CC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(KE)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(LE)","loc":"d,40:122,40:123","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(ME)","loc":"d,40:122,40:123","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(NE)","loc":"d,40:122,40:123","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(OE)","loc":"d,40:122,40:123","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ]} ],"scopeNamep": []} ],"filep": []}, {"type":"STOP","name":"","addr":"(PE)","loc":"d,40:142,40:147","isFatal":false} ],"elsesp": []}, {"type":"IF","name":"","addr":"(QE)","loc":"d,41:10,41:12", "condp": [ {"type":"NEQ","name":"","addr":"(RE)","loc":"d,41:42,41:45","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"4'h3","addr":"(SE)","loc":"d,41:47,41:50","dtypep":"(RB)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(TE)","loc":"d,41:15,41:16","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(UE)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(VE)","loc":"d,41:15,41:16","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(WE)","loc":"d,41:15,41:16","dtypep":"(EC)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(XE)","loc":"d,41:15,41:16","dtypep":"(CC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(YE)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(ZE)","loc":"d,41:15,41:16","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(AF)","loc":"d,41:15,41:16","dtypep":"(EC)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(BF)","loc":"d,41:15,41:16","dtypep":"(CC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(CF)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(DF)","loc":"d,41:15,41:16","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(EF)","loc":"d,41:15,41:16","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(FF)","loc":"d,41:15,41:16","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(GF)","loc":"d,41:15,41:16","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ]} ]} ]} ]} ], "thensp": [ {"type":"DISPLAY","name":"","addr":"(HF)","loc":"d,41:59,41:65", "fmtp": [ {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:41: got='h%x exp='h3\\n","addr":"(IF)","loc":"d,41:59,41:65","dtypep":"(PB)", "exprsp": [ {"type":"ARRAYSEL","name":"","addr":"(JF)","loc":"d,41:138,41:139","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(KF)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(LF)","loc":"d,41:138,41:139","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(MF)","loc":"d,41:138,41:139","dtypep":"(EC)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(NF)","loc":"d,41:138,41:139","dtypep":"(CC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(OF)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(PF)","loc":"d,41:138,41:139","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(QF)","loc":"d,41:138,41:139","dtypep":"(EC)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(RF)","loc":"d,41:138,41:139","dtypep":"(CC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(SF)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(TF)","loc":"d,41:138,41:139","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(UF)","loc":"d,41:138,41:139","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(VF)","loc":"d,41:138,41:139","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(WF)","loc":"d,41:138,41:139","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ]} ]} ]} ],"scopeNamep": []} ],"filep": []}, {"type":"STOP","name":"","addr":"(XF)","loc":"d,41:174,41:179","isFatal":false} ],"elsesp": []}, {"type":"IF","name":"","addr":"(YF)","loc":"d,42:10,42:12", "condp": [ {"type":"NEQ","name":"","addr":"(ZF)","loc":"d,42:34,42:37","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"4'h3","addr":"(AG)","loc":"d,42:39,42:42","dtypep":"(RB)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(BG)","loc":"d,42:15,42:16","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(CG)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(DG)","loc":"d,42:15,42:16","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(EG)","loc":"d,42:15,42:16","dtypep":"(EC)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(FG)","loc":"d,42:15,42:16","dtypep":"(CC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(GG)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(HG)","loc":"d,42:15,42:16","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(IG)","loc":"d,42:15,42:16","dtypep":"(EC)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(JG)","loc":"d,42:15,42:16","dtypep":"(CC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(KG)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(LG)","loc":"d,42:15,42:16","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(MG)","loc":"d,42:15,42:16","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(NG)","loc":"d,42:15,42:16","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(OG)","loc":"d,42:15,42:16","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ]} ]} ]} ]} ], "thensp": [ {"type":"DISPLAY","name":"","addr":"(PG)","loc":"d,42:51,42:57", "fmtp": [ {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:42: got='h%x exp='h3\\n","addr":"(QG)","loc":"d,42:51,42:57","dtypep":"(PB)", "exprsp": [ {"type":"ARRAYSEL","name":"","addr":"(RG)","loc":"d,42:130,42:131","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(SG)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(TG)","loc":"d,42:130,42:131","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(UG)","loc":"d,42:130,42:131","dtypep":"(EC)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(VG)","loc":"d,42:130,42:131","dtypep":"(CC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(WG)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(XG)","loc":"d,42:130,42:131","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(YG)","loc":"d,42:130,42:131","dtypep":"(EC)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(ZG)","loc":"d,42:130,42:131","dtypep":"(CC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(AH)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(BH)","loc":"d,42:130,42:131","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(CH)","loc":"d,42:130,42:131","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(DH)","loc":"d,42:130,42:131","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(EH)","loc":"d,42:130,42:131","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ]} ]} ]} ],"scopeNamep": []} ],"filep": []}, {"type":"STOP","name":"","addr":"(FH)","loc":"d,42:158,42:163","isFatal":false} ],"elsesp": []}, {"type":"IF","name":"","addr":"(GH)","loc":"d,43:10,43:12", "condp": [ {"type":"NEQ","name":"","addr":"(HH)","loc":"d,43:30,43:33","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"4'h3","addr":"(IH)","loc":"d,43:35,43:38","dtypep":"(RB)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(JH)","loc":"d,43:15,43:16","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(KH)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(LH)","loc":"d,43:15,43:16","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(MH)","loc":"d,43:15,43:16","dtypep":"(EC)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(NH)","loc":"d,43:15,43:16","dtypep":"(CC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(OH)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(PH)","loc":"d,43:15,43:16","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(QH)","loc":"d,43:15,43:16","dtypep":"(EC)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(RH)","loc":"d,43:15,43:16","dtypep":"(CC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(SH)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(TH)","loc":"d,43:15,43:16","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(UH)","loc":"d,43:15,43:16","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(VH)","loc":"d,43:15,43:16","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(WH)","loc":"d,43:15,43:16","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ]} ]} ]} ]} ], "thensp": [ {"type":"DISPLAY","name":"","addr":"(XH)","loc":"d,43:47,43:53", "fmtp": [ {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:43: got='h%x exp='h3\\n","addr":"(YH)","loc":"d,43:47,43:53","dtypep":"(PB)", "exprsp": [ {"type":"ARRAYSEL","name":"","addr":"(ZH)","loc":"d,43:126,43:127","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(AI)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(BI)","loc":"d,43:126,43:127","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(CI)","loc":"d,43:126,43:127","dtypep":"(EC)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(DI)","loc":"d,43:126,43:127","dtypep":"(CC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(EI)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(FI)","loc":"d,43:126,43:127","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(GI)","loc":"d,43:126,43:127","dtypep":"(EC)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(HI)","loc":"d,43:126,43:127","dtypep":"(CC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(II)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(JI)","loc":"d,43:126,43:127","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(KI)","loc":"d,43:126,43:127","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(LI)","loc":"d,43:126,43:127","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(MI)","loc":"d,43:126,43:127","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ]} ]} ]} ],"scopeNamep": []} ],"filep": []}, {"type":"STOP","name":"","addr":"(NI)","loc":"d,43:150,43:155","isFatal":false} ],"elsesp": []}, {"type":"IF","name":"","addr":"(OI)","loc":"d,44:10,44:12", "condp": [ {"type":"NEQ","name":"","addr":"(PI)","loc":"d,44:23,44:26","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"4'h1","addr":"(QI)","loc":"d,44:28,44:31","dtypep":"(RB)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(RI)","loc":"d,44:15,44:16","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(SI)","loc":"d,17:12,17:16","dtypep":"(TI)","access":"RD","varp":"(UI)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(VI)","loc":"d,44:15,44:16","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(WI)","loc":"d,44:15,44:16","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(XI)","loc":"d,44:15,44:16","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(YI)","loc":"d,44:15,44:16","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ], "thensp": [ {"type":"DISPLAY","name":"","addr":"(ZI)","loc":"d,44:40,44:46", "fmtp": [ {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:44: got='h%x exp='h1\\n","addr":"(AJ)","loc":"d,44:40,44:46","dtypep":"(PB)", "exprsp": [ {"type":"ARRAYSEL","name":"","addr":"(BJ)","loc":"d,44:119,44:120","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(CJ)","loc":"d,17:12,17:16","dtypep":"(TI)","access":"RD","varp":"(UI)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(DJ)","loc":"d,44:119,44:120","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(EJ)","loc":"d,44:119,44:120","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(FJ)","loc":"d,44:119,44:120","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(GJ)","loc":"d,44:119,44:120","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ],"scopeNamep": []} ],"filep": []}, {"type":"STOP","name":"","addr":"(HJ)","loc":"d,44:136,44:141","isFatal":false} ],"elsesp": []}, {"type":"IF","name":"","addr":"(IJ)","loc":"d,45:10,45:12", "condp": [ {"type":"NEQ","name":"","addr":"(JJ)","loc":"d,45:26,45:29","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"4'h1","addr":"(KJ)","loc":"d,45:31,45:34","dtypep":"(RB)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(LJ)","loc":"d,45:15,45:16","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(MJ)","loc":"d,17:12,17:16","dtypep":"(TI)","access":"RD","varp":"(UI)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(NJ)","loc":"d,45:15,45:16","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(OJ)","loc":"d,45:15,45:16","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(PJ)","loc":"d,45:15,45:16","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(QJ)","loc":"d,45:15,45:16","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ], "thensp": [ {"type":"DISPLAY","name":"","addr":"(RJ)","loc":"d,45:43,45:49", "fmtp": [ {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:45: got='h%x exp='h1\\n","addr":"(SJ)","loc":"d,45:43,45:49","dtypep":"(PB)", "exprsp": [ {"type":"ARRAYSEL","name":"","addr":"(TJ)","loc":"d,45:122,45:123","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(UJ)","loc":"d,17:12,17:16","dtypep":"(TI)","access":"RD","varp":"(UI)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(VJ)","loc":"d,45:122,45:123","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(WJ)","loc":"d,45:122,45:123","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(XJ)","loc":"d,45:122,45:123","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(YJ)","loc":"d,45:122,45:123","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ],"scopeNamep": []} ],"filep": []}, {"type":"STOP","name":"","addr":"(ZJ)","loc":"d,45:142,45:147","isFatal":false} ],"elsesp": []}, {"type":"IF","name":"","addr":"(AK)","loc":"d,46:10,46:12", "condp": [ {"type":"NEQ","name":"","addr":"(BK)","loc":"d,46:34,46:37","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"4'h4","addr":"(CK)","loc":"d,46:39,46:42","dtypep":"(RB)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(DK)","loc":"d,46:15,46:16","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(EK)","loc":"d,17:12,17:16","dtypep":"(TI)","access":"RD","varp":"(UI)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(FK)","loc":"d,46:15,46:16","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(GK)","loc":"d,46:15,46:16","dtypep":"(EC)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(HK)","loc":"d,46:15,46:16","dtypep":"(CC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(IK)","loc":"d,17:12,17:16","dtypep":"(TI)","access":"RD","varp":"(UI)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(JK)","loc":"d,46:15,46:16","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(KK)","loc":"d,46:15,46:16","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(LK)","loc":"d,46:15,46:16","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(MK)","loc":"d,46:15,46:16","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ]} ]} ], "thensp": [ {"type":"DISPLAY","name":"","addr":"(NK)","loc":"d,46:51,46:57", "fmtp": [ {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:46: got='h%x exp='h4\\n","addr":"(OK)","loc":"d,46:51,46:57","dtypep":"(PB)", "exprsp": [ {"type":"ARRAYSEL","name":"","addr":"(PK)","loc":"d,46:130,46:131","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(QK)","loc":"d,17:12,17:16","dtypep":"(TI)","access":"RD","varp":"(UI)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(RK)","loc":"d,46:130,46:131","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(SK)","loc":"d,46:130,46:131","dtypep":"(EC)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(TK)","loc":"d,46:130,46:131","dtypep":"(CC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(UK)","loc":"d,17:12,17:16","dtypep":"(TI)","access":"RD","varp":"(UI)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(VK)","loc":"d,46:130,46:131","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(WK)","loc":"d,46:130,46:131","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(XK)","loc":"d,46:130,46:131","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(YK)","loc":"d,46:130,46:131","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ]} ],"scopeNamep": []} ],"filep": []}, {"type":"STOP","name":"","addr":"(ZK)","loc":"d,46:158,46:163","isFatal":false} ],"elsesp": []}, {"type":"IF","name":"","addr":"(AL)","loc":"d,47:10,47:12", "condp": [ {"type":"NEQ","name":"","addr":"(BL)","loc":"d,47:26,47:29","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"4'h4","addr":"(CL)","loc":"d,47:31,47:34","dtypep":"(RB)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(DL)","loc":"d,47:15,47:16","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(EL)","loc":"d,17:12,17:16","dtypep":"(TI)","access":"RD","varp":"(UI)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(FL)","loc":"d,47:15,47:16","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(GL)","loc":"d,47:15,47:16","dtypep":"(EC)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(HL)","loc":"d,47:15,47:16","dtypep":"(CC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(IL)","loc":"d,17:12,17:16","dtypep":"(TI)","access":"RD","varp":"(UI)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(JL)","loc":"d,47:15,47:16","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(KL)","loc":"d,47:15,47:16","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(LL)","loc":"d,47:15,47:16","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(ML)","loc":"d,47:15,47:16","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ]} ]} ], "thensp": [ {"type":"DISPLAY","name":"","addr":"(NL)","loc":"d,47:43,47:49", "fmtp": [ {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:47: got='h%x exp='h4\\n","addr":"(OL)","loc":"d,47:43,47:49","dtypep":"(PB)", "exprsp": [ {"type":"ARRAYSEL","name":"","addr":"(PL)","loc":"d,47:122,47:123","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(QL)","loc":"d,17:12,17:16","dtypep":"(TI)","access":"RD","varp":"(UI)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(RL)","loc":"d,47:122,47:123","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(SL)","loc":"d,47:122,47:123","dtypep":"(EC)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(TL)","loc":"d,47:122,47:123","dtypep":"(CC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(UL)","loc":"d,17:12,17:16","dtypep":"(TI)","access":"RD","varp":"(UI)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(VL)","loc":"d,47:122,47:123","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(WL)","loc":"d,47:122,47:123","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(XL)","loc":"d,47:122,47:123","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(YL)","loc":"d,47:122,47:123","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ]} ],"scopeNamep": []} ],"filep": []}, {"type":"STOP","name":"","addr":"(ZL)","loc":"d,47:142,47:147","isFatal":false} ],"elsesp": []}, {"type":"IF","name":"","addr":"(AM)","loc":"d,49:10,49:12", "condp": [ {"type":"NEQN","name":"","addr":"(BM)","loc":"d,49:23,49:25","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"\\\"E03\\\"","addr":"(CM)","loc":"d,49:27,49:32","dtypep":"(PB)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(DM)","loc":"d,49:15,49:16","dtypep":"(PB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_name1","addr":"(EM)","loc":"d,17:12,17:16","dtypep":"(FM)","access":"RD","varp":"(GM)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(HM)","loc":"d,49:15,49:16","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(IM)","loc":"d,49:15,49:16","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(JM)","loc":"d,49:15,49:16","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(KM)","loc":"d,49:15,49:16","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ], "thensp": [ {"type":"ASSIGN","name":"","addr":"(LM)","loc":"d,49:120,49:121","dtypep":"(PB)", "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(MM)","loc":"d,49:120,49:121","dtypep":"(PB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_name1","addr":"(NM)","loc":"d,17:12,17:16","dtypep":"(FM)","access":"RD","varp":"(GM)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(OM)","loc":"d,49:120,49:121","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(PM)","loc":"d,49:120,49:121","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(QM)","loc":"d,49:120,49:121","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(RM)","loc":"d,49:120,49:121","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ], "lhsp": [ {"type":"VARREF","name":"__Vtemp_1","addr":"(SM)","loc":"d,49:120,49:121","dtypep":"(PB)","access":"WR","varp":"(OB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": []}, {"type":"DISPLAY","name":"","addr":"(TM)","loc":"d,49:41,49:47", "fmtp": [ {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:49: got='%@' exp='E03'\\n","addr":"(UM)","loc":"d,49:41,49:47","dtypep":"(PB)", "exprsp": [ {"type":"VARREF","name":"__Vtemp_1","addr":"(VM)","loc":"d,49:120,49:121","dtypep":"(PB)","access":"RD","varp":"(OB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"scopeNamep": []} ],"filep": []}, {"type":"STOP","name":"","addr":"(WM)","loc":"d,49:139,49:144","isFatal":false} ],"elsesp": []}, {"type":"ASSIGN","name":"","addr":"(XM)","loc":"d,55:9,55:10","dtypep":"(RB)", "rhsp": [ {"type":"CONST","name":"4'h4","addr":"(YM)","loc":"d,55:13,55:17","dtypep":"(RB)"} ], "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(ZM)","loc":"d,55:7,55:8","dtypep":"(RB)","access":"WR","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": []} ]}, {"type":"CFUNC","name":"_eval_final","addr":"(AN)","loc":"a,0:0,0:0","slow":true,"isStatic":false,"dpiExportDispatcher":false,"dpiExportImpl":false,"dpiImportPrototype":false,"dpiImportWrapper":false,"dpiContext":false,"isConstructor":false,"isDestructor":false,"isVirtual":false,"isCoroutine":false,"needProcess":false,"scopep":"(W)","argsp": [],"varsp": [],"stmtsp": []}, {"type":"CFUNC","name":"_eval_settle","addr":"(BN)","loc":"a,0:0,0:0","slow":true,"isStatic":false,"dpiExportDispatcher":false,"dpiExportImpl":false,"dpiImportPrototype":false,"dpiImportWrapper":false,"dpiContext":false,"isConstructor":false,"isDestructor":false,"isVirtual":false,"isCoroutine":false,"needProcess":false,"scopep":"(W)","argsp": [],"varsp": [],"stmtsp": []}, {"type":"CFUNC","name":"_eval_triggers__act","addr":"(CN)","loc":"a,0:0,0:0","slow":false,"isStatic":false,"dpiExportDispatcher":false,"dpiExportImpl":false,"dpiImportPrototype":false,"dpiImportWrapper":false,"dpiContext":false,"isConstructor":false,"isDestructor":false,"isVirtual":false,"isCoroutine":false,"needProcess":false,"scopep":"(W)","argsp": [],"varsp": [], "stmtsp": [ {"type":"ASSIGN","name":"","addr":"(DN)","loc":"d,11:8,11:9","dtypep":"(EN)", "rhsp": [ {"type":"CCAST","name":"","addr":"(FN)","loc":"d,63:14,63:21","dtypep":"(GN)","size":64, "lhsp": [ {"type":"CCAST","name":"","addr":"(HN)","loc":"d,63:14,63:21","dtypep":"(DB)","size":32, "lhsp": [ {"type":"AND","name":"","addr":"(IN)","loc":"d,63:14,63:21","dtypep":"(DB)", "lhsp": [ {"type":"CCAST","name":"","addr":"(JN)","loc":"d,63:22,63:25","dtypep":"(DB)","size":32, "lhsp": [ {"type":"VARREF","name":"clk","addr":"(KN)","loc":"d,63:22,63:25","dtypep":"(DB)","access":"RD","varp":"(J)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ], "rhsp": [ {"type":"NOT","name":"","addr":"(LN)","loc":"d,63:14,63:21","dtypep":"(DB)", "lhsp": [ {"type":"CCAST","name":"","addr":"(MN)","loc":"d,63:14,63:21","dtypep":"(DB)","size":32, "lhsp": [ {"type":"VARREF","name":"__Vtrigprevexpr___TOP__clk__0","addr":"(NN)","loc":"d,63:14,63:21","dtypep":"(DB)","access":"RD","varp":"(N)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ]} ], "lhsp": [ {"type":"ARRAYSEL","name":"","addr":"(ON)","loc":"d,11:8,11:9","dtypep":"(EN)", "fromp": [ {"type":"VARREF","name":"__VactTriggered","addr":"(PN)","loc":"d,11:8,11:9","dtypep":"(T)","access":"WR","varp":"(S)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"CONST","name":"32'h0","addr":"(QN)","loc":"d,11:8,11:9","dtypep":"(EC)"} ]} ],"timingControlp": []}, {"type":"ASSIGN","name":"","addr":"(RN)","loc":"d,63:22,63:25","dtypep":"(DB)", "rhsp": [ {"type":"VARREF","name":"clk","addr":"(SN)","loc":"d,63:22,63:25","dtypep":"(DB)","access":"RD","varp":"(J)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "lhsp": [ {"type":"VARREF","name":"__Vtrigprevexpr___TOP__clk__0","addr":"(TN)","loc":"d,63:22,63:25","dtypep":"(DB)","access":"WR","varp":"(N)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": []}, {"type":"CSTMT","name":"","addr":"(UN)","loc":"d,11:8,11:9", "nodesp": [ {"type":"TEXT","name":"","addr":"(VN)","loc":"d,11:8,11:9","text":"#ifdef VL_DEBUG\n"}, {"type":"TEXT","name":"","addr":"(WN)","loc":"d,11:8,11:9","text":"if (VL_UNLIKELY(vlSymsp->_vm_contextp__->debug())) {\n"}, {"type":"STMTEXPR","name":"","addr":"(XN)","loc":"d,11:8,11:9", "exprp": [ {"type":"CCALL","name":"","addr":"(YN)","loc":"d,11:8,11:9","dtypep":"(AB)","funcName":"_dump_triggers__act","funcp":"(ZN)", "argsp": [ {"type":"VARREF","name":"__VactTriggered","addr":"(AO)","loc":"d,11:8,11:9","dtypep":"(T)","access":"RD","varp":"(S)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"}, {"type":"CONST","name":"\\\"act\\\"","addr":"(BO)","loc":"d,11:8,11:9","dtypep":"(PB)"} ]} ]}, {"type":"TEXT","name":"","addr":"(CO)","loc":"d,11:8,11:9","text":"}\n"}, {"type":"TEXT","name":"","addr":"(DO)","loc":"d,11:8,11:9","text":"#endif"} ]} ]}, {"type":"CFUNC","name":"_dump_triggers__act","addr":"(ZN)","loc":"a,0:0,0:0","slow":true,"isStatic":true,"dpiExportDispatcher":false,"dpiExportImpl":false,"dpiImportPrototype":false,"dpiImportWrapper":false,"dpiContext":false,"isConstructor":false,"isDestructor":false,"isVirtual":false,"isCoroutine":false,"needProcess":false,"scopep":"(W)", "argsp": [ {"type":"VAR","name":"triggers","addr":"(EO)","loc":"a,0:0,0:0","dtypep":"(T)","origName":"triggers","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"CONSTREF","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":true,"lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"CRESET","name":"","addr":"(FO)","loc":"a,0:0,0:0","constructing":true, "varrefp": [ {"type":"VARREF","name":"triggers","addr":"(GO)","loc":"a,0:0,0:0","dtypep":"(T)","access":"WR","varp":"(EO)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]}, {"type":"VAR","name":"tag","addr":"(HO)","loc":"a,0:0,0:0","dtypep":"(PB)","origName":"tag","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"CONSTREF","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":true,"lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"string","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"CRESET","name":"","addr":"(IO)","loc":"a,0:0,0:0","constructing":true, "varrefp": [ {"type":"VARREF","name":"tag","addr":"(JO)","loc":"a,0:0,0:0","dtypep":"(PB)","access":"WR","varp":"(HO)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ],"varsp": [], "stmtsp": [ {"type":"IF","name":"","addr":"(KO)","loc":"d,11:8,11:9", "condp": [ {"type":"AND","name":"","addr":"(LO)","loc":"d,11:8,11:9","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"32'h1","addr":"(MO)","loc":"d,11:8,11:9","dtypep":"(EC)"} ], "rhsp": [ {"type":"NOT","name":"","addr":"(NO)","loc":"d,11:8,11:9","dtypep":"(DB)", "lhsp": [ {"type":"CCAST","name":"","addr":"(OO)","loc":"d,11:8,11:9","dtypep":"(DB)","size":32, "lhsp": [ {"type":"CCALL","name":"","addr":"(PO)","loc":"d,11:8,11:9","dtypep":"(DB)","funcName":"_trigger_anySet__act","funcp":"(QO)", "argsp": [ {"type":"VARREF","name":"triggers","addr":"(RO)","loc":"d,11:8,11:9","dtypep":"(T)","access":"WR","varp":"(EO)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ], "thensp": [ {"type":"CSTMT","name":"","addr":"(SO)","loc":"d,11:8,11:9", "nodesp": [ {"type":"TEXT","name":"","addr":"(TO)","loc":"d,11:8,11:9","text":"VL_DBG_MSGS(\" No '\" + "}, {"type":"VARREF","name":"tag","addr":"(UO)","loc":"d,11:8,11:9","dtypep":"(PB)","access":"RD","varp":"(HO)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"}, {"type":"TEXT","name":"","addr":"(VO)","loc":"d,11:8,11:9","text":" + \"' region triggers active\\n\");"} ]} ],"elsesp": []}, {"type":"IF","name":"","addr":"(WO)","loc":"d,11:8,11:9", "condp": [ {"type":"AND","name":"","addr":"(XO)","loc":"d,11:8,11:9","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"32'h1","addr":"(YO)","loc":"d,11:8,11:9","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(ZO)","loc":"d,11:8,11:9","dtypep":"(DB)","size":32, "lhsp": [ {"type":"ARRAYSEL","name":"","addr":"(AP)","loc":"d,11:8,11:9","dtypep":"(EN)", "fromp": [ {"type":"VARREF","name":"triggers","addr":"(BP)","loc":"d,11:8,11:9","dtypep":"(T)","access":"RD","varp":"(EO)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"CONST","name":"32'h0","addr":"(CP)","loc":"d,11:8,11:9","dtypep":"(EC)"} ]} ]} ]} ], "thensp": [ {"type":"CSTMT","name":"","addr":"(DP)","loc":"d,11:8,11:9", "nodesp": [ {"type":"TEXT","name":"","addr":"(EP)","loc":"d,11:8,11:9","text":"VL_DBG_MSGS(\" '\" + "}, {"type":"VARREF","name":"tag","addr":"(FP)","loc":"d,11:8,11:9","dtypep":"(PB)","access":"RD","varp":"(HO)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"}, {"type":"TEXT","name":"","addr":"(GP)","loc":"d,11:8,11:9","text":" + \"' region trigger index 0 is active: @(posedge clk)\\n\");"} ]} ],"elsesp": []} ]}, {"type":"CFUNC","name":"_trigger_anySet__act","addr":"(QO)","loc":"a,0:0,0:0","slow":false,"isStatic":true,"dpiExportDispatcher":false,"dpiExportImpl":false,"dpiImportPrototype":false,"dpiImportWrapper":false,"dpiContext":false,"isConstructor":false,"isDestructor":false,"isVirtual":false,"isCoroutine":false,"needProcess":false,"scopep":"(W)", "argsp": [ {"type":"VAR","name":"in","addr":"(HP)","loc":"a,0:0,0:0","dtypep":"(T)","origName":"in","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"CONSTREF","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":true,"lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"CRESET","name":"","addr":"(IP)","loc":"a,0:0,0:0","constructing":true, "varrefp": [ {"type":"VARREF","name":"in","addr":"(JP)","loc":"a,0:0,0:0","dtypep":"(T)","access":"WR","varp":"(HP)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ], "varsp": [ {"type":"VAR","name":"n","addr":"(KP)","loc":"a,0:0,0:0","dtypep":"(LP)","origName":"n","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":true,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":true,"lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"IData","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ], "stmtsp": [ {"type":"ASSIGN","name":"","addr":"(MP)","loc":"a,0:0,0:0","dtypep":"(LP)", "rhsp": [ {"type":"CONST","name":"32'h0","addr":"(NP)","loc":"a,0:0,0:0","dtypep":"(EC)"} ], "lhsp": [ {"type":"VARREF","name":"n","addr":"(OP)","loc":"a,0:0,0:0","dtypep":"(LP)","access":"WR","varp":"(KP)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": []}, {"type":"LOOP","name":"","addr":"(PP)","loc":"d,11:8,11:9","unroll":"default", "stmtsp": [ {"type":"IF","name":"","addr":"(QP)","loc":"d,11:8,11:9", "condp": [ {"type":"ARRAYSEL","name":"","addr":"(RP)","loc":"d,11:8,11:9","dtypep":"(EN)", "fromp": [ {"type":"VARREF","name":"in","addr":"(SP)","loc":"d,11:8,11:9","dtypep":"(T)","access":"RD","varp":"(HP)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"VARREF","name":"n","addr":"(TP)","loc":"d,11:8,11:9","dtypep":"(LP)","access":"RD","varp":"(KP)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ], "thensp": [ {"type":"CRETURN","name":"","addr":"(UP)","loc":"d,11:8,11:9", "lhsp": [ {"type":"CONST","name":"1'h1","addr":"(VP)","loc":"d,11:8,11:9","dtypep":"(DB)"} ]} ],"elsesp": []}, {"type":"ASSIGN","name":"","addr":"(WP)","loc":"a,0:0,0:0","dtypep":"(LP)", "rhsp": [ {"type":"ADD","name":"","addr":"(XP)","loc":"a,0:0,0:0","dtypep":"(LP)", "lhsp": [ {"type":"CCAST","name":"","addr":"(YP)","loc":"a,0:0,0:0","dtypep":"(EC)","size":32, "lhsp": [ {"type":"CONST","name":"32'h1","addr":"(ZP)","loc":"a,0:0,0:0","dtypep":"(EC)"} ]} ], "rhsp": [ {"type":"VARREF","name":"n","addr":"(AQ)","loc":"a,0:0,0:0","dtypep":"(LP)","access":"RD","varp":"(KP)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ], "lhsp": [ {"type":"VARREF","name":"n","addr":"(BQ)","loc":"a,0:0,0:0","dtypep":"(LP)","access":"WR","varp":"(KP)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": []}, {"type":"LOOPTEST","name":"","addr":"(CQ)","loc":"d,11:8,11:9", "condp": [ {"type":"GT","name":"","addr":"(DQ)","loc":"d,11:8,11:9","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"32'h1","addr":"(EQ)","loc":"d,11:8,11:9","dtypep":"(EC)"} ], "rhsp": [ {"type":"VARREF","name":"n","addr":"(FQ)","loc":"d,11:8,11:9","dtypep":"(LP)","access":"RD","varp":"(KP)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ],"contsp": []}, {"type":"CRETURN","name":"","addr":"(GQ)","loc":"d,11:8,11:9", "lhsp": [ {"type":"CONST","name":"1'h0","addr":"(HQ)","loc":"d,11:8,11:9","dtypep":"(DB)"} ]} ]}, {"type":"CFUNC","name":"_nba_sequent__TOP__0","addr":"(IQ)","loc":"d,23:17,23:20","slow":false,"isStatic":false,"dpiExportDispatcher":false,"dpiExportImpl":false,"dpiImportPrototype":false,"dpiImportWrapper":false,"dpiContext":false,"isConstructor":false,"isDestructor":false,"isVirtual":false,"isCoroutine":false,"needProcess":false,"scopep":"(W)","argsp": [], "varsp": [ {"type":"VAR","name":"__Vdly__t.cyc","addr":"(JQ)","loc":"d,23:17,23:20","dtypep":"(P)","origName":"__Vdly__t__DOT__cyc","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":true,"lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"integer","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"CRESET","name":"","addr":"(KQ)","loc":"d,23:17,23:20","constructing":true, "varrefp": [ {"type":"VARREF","name":"__Vdly__t.cyc","addr":"(LQ)","loc":"d,23:17,23:20","dtypep":"(P)","access":"WR","varp":"(JQ)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]}, {"type":"VAR","name":"__Vdly__t.e","addr":"(MQ)","loc":"d,24:9,24:10","dtypep":"(M)","origName":"__Vdly__t__DOT__e","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":true,"lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"my_t","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"CRESET","name":"","addr":"(NQ)","loc":"d,24:9,24:10","constructing":true, "varrefp": [ {"type":"VARREF","name":"__Vdly__t.e","addr":"(OQ)","loc":"d,24:9,24:10","dtypep":"(M)","access":"WR","varp":"(MQ)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]}, {"type":"VAR","name":"__Vtemp_1","addr":"(PQ)","loc":"d,70:123,70:124","dtypep":"(PB)","origName":"__Vtemp_1","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"STMTTEMP","dtypeName":"string","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"__Vtemp_2","addr":"(QQ)","loc":"d,80:123,80:124","dtypep":"(PB)","origName":"__Vtemp_2","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"STMTTEMP","dtypeName":"string","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"__Vtemp_3","addr":"(RQ)","loc":"d,90:123,90:124","dtypep":"(PB)","origName":"__Vtemp_3","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"STMTTEMP","dtypeName":"string","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ], "stmtsp": [ {"type":"ASSIGN","name":"","addr":"(SQ)","loc":"d,23:17,23:20","dtypep":"(P)", "rhsp": [ {"type":"VARREF","name":"t.cyc","addr":"(TQ)","loc":"d,23:17,23:20","dtypep":"(P)","access":"RD","varp":"(O)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "lhsp": [ {"type":"VARREF","name":"__Vdly__t.cyc","addr":"(UQ)","loc":"d,23:17,23:20","dtypep":"(P)","access":"WR","varp":"(JQ)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": []}, {"type":"ASSIGN","name":"","addr":"(VQ)","loc":"d,24:9,24:10","dtypep":"(RB)", "rhsp": [ {"type":"VARREF","name":"t.e","addr":"(WQ)","loc":"d,24:9,24:10","dtypep":"(RB)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "lhsp": [ {"type":"VARREF","name":"__Vdly__t.e","addr":"(XQ)","loc":"d,24:9,24:10","dtypep":"(RB)","access":"WR","varp":"(MQ)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": []}, {"type":"ASSIGNDLY","name":"","addr":"(YQ)","loc":"d,64:11,64:13","dtypep":"(P)", "rhsp": [ {"type":"ADD","name":"","addr":"(ZQ)","loc":"d,64:18,64:19","dtypep":"(P)", "lhsp": [ {"type":"CCAST","name":"","addr":"(AR)","loc":"d,64:20,64:21","dtypep":"(EC)","size":32, "lhsp": [ {"type":"CONST","name":"32'sh1","addr":"(BR)","loc":"d,64:20,64:21","dtypep":"(IB)"} ]} ], "rhsp": [ {"type":"VARREF","name":"t.cyc","addr":"(CR)","loc":"d,64:14,64:17","dtypep":"(P)","access":"RD","varp":"(O)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ], "lhsp": [ {"type":"VARREF","name":"__Vdly__t.cyc","addr":"(DR)","loc":"d,64:7,64:10","dtypep":"(P)","access":"WR","varp":"(JQ)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": []}, {"type":"IF","name":"","addr":"(ER)","loc":"d,65:7,65:9", "condp": [ {"type":"EQ","name":"","addr":"(FR)","loc":"d,65:14,65:16","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"32'sh0","addr":"(GR)","loc":"d,65:16,65:17","dtypep":"(IB)"} ], "rhsp": [ {"type":"VARREF","name":"t.cyc","addr":"(HR)","loc":"d,65:11,65:14","dtypep":"(P)","access":"RD","varp":"(O)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ], "thensp": [ {"type":"ASSIGNDLY","name":"","addr":"(IR)","loc":"d,67:12,67:14","dtypep":"(RB)", "rhsp": [ {"type":"CONST","name":"4'h1","addr":"(JR)","loc":"d,67:15,67:18","dtypep":"(RB)"} ], "lhsp": [ {"type":"VARREF","name":"__Vdly__t.e","addr":"(KR)","loc":"d,67:10,67:11","dtypep":"(RB)","access":"WR","varp":"(MQ)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": []} ], "elsesp": [ {"type":"IF","name":"","addr":"(LR)","loc":"d,69:12,69:14", "condp": [ {"type":"EQ","name":"","addr":"(MR)","loc":"d,69:19,69:21","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"32'sh1","addr":"(NR)","loc":"d,69:21,69:22","dtypep":"(IB)"} ], "rhsp": [ {"type":"VARREF","name":"t.cyc","addr":"(OR)","loc":"d,69:16,69:19","dtypep":"(P)","access":"RD","varp":"(O)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ], "thensp": [ {"type":"IF","name":"","addr":"(PR)","loc":"d,70:13,70:15", "condp": [ {"type":"NEQN","name":"","addr":"(QR)","loc":"d,70:26,70:28","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"\\\"E01\\\"","addr":"(RR)","loc":"d,70:30,70:35","dtypep":"(PB)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(SR)","loc":"d,70:18,70:19","dtypep":"(PB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_name1","addr":"(TR)","loc":"d,17:12,17:16","dtypep":"(FM)","access":"RD","varp":"(GM)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(UR)","loc":"d,70:18,70:19","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(VR)","loc":"d,70:18,70:19","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(WR)","loc":"d,70:18,70:19","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(XR)","loc":"d,70:18,70:19","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ], "thensp": [ {"type":"ASSIGN","name":"","addr":"(YR)","loc":"d,70:123,70:124","dtypep":"(PB)", "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(ZR)","loc":"d,70:123,70:124","dtypep":"(PB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_name1","addr":"(AS)","loc":"d,17:12,17:16","dtypep":"(FM)","access":"RD","varp":"(GM)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(BS)","loc":"d,70:123,70:124","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(CS)","loc":"d,70:123,70:124","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(DS)","loc":"d,70:123,70:124","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(ES)","loc":"d,70:123,70:124","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ], "lhsp": [ {"type":"VARREF","name":"__Vtemp_1","addr":"(FS)","loc":"d,70:123,70:124","dtypep":"(PB)","access":"WR","varp":"(PQ)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": []}, {"type":"DISPLAY","name":"","addr":"(GS)","loc":"d,70:44,70:50", "fmtp": [ {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:70: got='%@' exp='E01'\\n","addr":"(HS)","loc":"d,70:44,70:50","dtypep":"(PB)", "exprsp": [ {"type":"VARREF","name":"__Vtemp_1","addr":"(IS)","loc":"d,70:123,70:124","dtypep":"(PB)","access":"RD","varp":"(PQ)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"scopeNamep": []} ],"filep": []}, {"type":"STOP","name":"","addr":"(JS)","loc":"d,70:142,70:147","isFatal":false} ],"elsesp": []}, {"type":"IF","name":"","addr":"(KS)","loc":"d,71:13,71:15", "condp": [ {"type":"NEQ","name":"","addr":"(LS)","loc":"d,71:26,71:29","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"4'h3","addr":"(MS)","loc":"d,71:31,71:34","dtypep":"(RB)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(NS)","loc":"d,71:18,71:19","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(OS)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(PS)","loc":"d,71:18,71:19","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(QS)","loc":"d,71:18,71:19","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(RS)","loc":"d,71:18,71:19","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(SS)","loc":"d,71:18,71:19","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ], "thensp": [ {"type":"DISPLAY","name":"","addr":"(TS)","loc":"d,71:43,71:49", "fmtp": [ {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:71: got='h%x exp='h3\\n","addr":"(US)","loc":"d,71:43,71:49","dtypep":"(PB)", "exprsp": [ {"type":"ARRAYSEL","name":"","addr":"(VS)","loc":"d,71:122,71:123","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(WS)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(XS)","loc":"d,71:122,71:123","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(YS)","loc":"d,71:122,71:123","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(ZS)","loc":"d,71:122,71:123","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(AT)","loc":"d,71:122,71:123","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ],"scopeNamep": []} ],"filep": []}, {"type":"STOP","name":"","addr":"(BT)","loc":"d,71:139,71:144","isFatal":false} ],"elsesp": []}, {"type":"IF","name":"","addr":"(CT)","loc":"d,72:13,72:15", "condp": [ {"type":"NEQ","name":"","addr":"(DT)","loc":"d,72:29,72:32","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"4'h3","addr":"(ET)","loc":"d,72:34,72:37","dtypep":"(RB)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(FT)","loc":"d,72:18,72:19","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(GT)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(HT)","loc":"d,72:18,72:19","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(IT)","loc":"d,72:18,72:19","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(JT)","loc":"d,72:18,72:19","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(KT)","loc":"d,72:18,72:19","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ], "thensp": [ {"type":"DISPLAY","name":"","addr":"(LT)","loc":"d,72:46,72:52", "fmtp": [ {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:72: got='h%x exp='h3\\n","addr":"(MT)","loc":"d,72:46,72:52","dtypep":"(PB)", "exprsp": [ {"type":"ARRAYSEL","name":"","addr":"(NT)","loc":"d,72:125,72:126","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(OT)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(PT)","loc":"d,72:125,72:126","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(QT)","loc":"d,72:125,72:126","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(RT)","loc":"d,72:125,72:126","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(ST)","loc":"d,72:125,72:126","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ],"scopeNamep": []} ],"filep": []}, {"type":"STOP","name":"","addr":"(TT)","loc":"d,72:145,72:150","isFatal":false} ],"elsesp": []}, {"type":"IF","name":"","addr":"(UT)","loc":"d,73:13,73:15", "condp": [ {"type":"NEQ","name":"","addr":"(VT)","loc":"d,73:29,73:32","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"4'h4","addr":"(WT)","loc":"d,73:34,73:37","dtypep":"(RB)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(XT)","loc":"d,73:18,73:19","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(YT)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(ZT)","loc":"d,73:18,73:19","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(AU)","loc":"d,73:18,73:19","dtypep":"(EC)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(BU)","loc":"d,73:18,73:19","dtypep":"(CC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(CU)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(DU)","loc":"d,73:18,73:19","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(EU)","loc":"d,73:18,73:19","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(FU)","loc":"d,73:18,73:19","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(GU)","loc":"d,73:18,73:19","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ]} ]} ], "thensp": [ {"type":"DISPLAY","name":"","addr":"(HU)","loc":"d,73:46,73:52", "fmtp": [ {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:73: got='h%x exp='h4\\n","addr":"(IU)","loc":"d,73:46,73:52","dtypep":"(PB)", "exprsp": [ {"type":"ARRAYSEL","name":"","addr":"(JU)","loc":"d,73:125,73:126","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(KU)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(LU)","loc":"d,73:125,73:126","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(MU)","loc":"d,73:125,73:126","dtypep":"(EC)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(NU)","loc":"d,73:125,73:126","dtypep":"(CC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(OU)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(PU)","loc":"d,73:125,73:126","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(QU)","loc":"d,73:125,73:126","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(RU)","loc":"d,73:125,73:126","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(SU)","loc":"d,73:125,73:126","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ]} ],"scopeNamep": []} ],"filep": []}, {"type":"STOP","name":"","addr":"(TU)","loc":"d,73:145,73:150","isFatal":false} ],"elsesp": []}, {"type":"IF","name":"","addr":"(UU)","loc":"d,74:13,74:15", "condp": [ {"type":"NEQ","name":"","addr":"(VU)","loc":"d,74:26,74:29","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"4'h4","addr":"(WU)","loc":"d,74:31,74:34","dtypep":"(RB)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(XU)","loc":"d,74:18,74:19","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(YU)","loc":"d,17:12,17:16","dtypep":"(TI)","access":"RD","varp":"(UI)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(ZU)","loc":"d,74:18,74:19","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(AV)","loc":"d,74:18,74:19","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(BV)","loc":"d,74:18,74:19","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(CV)","loc":"d,74:18,74:19","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ], "thensp": [ {"type":"DISPLAY","name":"","addr":"(DV)","loc":"d,74:43,74:49", "fmtp": [ {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:74: got='h%x exp='h4\\n","addr":"(EV)","loc":"d,74:43,74:49","dtypep":"(PB)", "exprsp": [ {"type":"ARRAYSEL","name":"","addr":"(FV)","loc":"d,74:122,74:123","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(GV)","loc":"d,17:12,17:16","dtypep":"(TI)","access":"RD","varp":"(UI)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(HV)","loc":"d,74:122,74:123","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(IV)","loc":"d,74:122,74:123","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(JV)","loc":"d,74:122,74:123","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(KV)","loc":"d,74:122,74:123","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ],"scopeNamep": []} ],"filep": []}, {"type":"STOP","name":"","addr":"(LV)","loc":"d,74:139,74:144","isFatal":false} ],"elsesp": []}, {"type":"IF","name":"","addr":"(MV)","loc":"d,75:13,75:15", "condp": [ {"type":"NEQ","name":"","addr":"(NV)","loc":"d,75:29,75:32","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"4'h4","addr":"(OV)","loc":"d,75:34,75:37","dtypep":"(RB)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(PV)","loc":"d,75:18,75:19","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(QV)","loc":"d,17:12,17:16","dtypep":"(TI)","access":"RD","varp":"(UI)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(RV)","loc":"d,75:18,75:19","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(SV)","loc":"d,75:18,75:19","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(TV)","loc":"d,75:18,75:19","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(UV)","loc":"d,75:18,75:19","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ], "thensp": [ {"type":"DISPLAY","name":"","addr":"(VV)","loc":"d,75:46,75:52", "fmtp": [ {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:75: got='h%x exp='h4\\n","addr":"(WV)","loc":"d,75:46,75:52","dtypep":"(PB)", "exprsp": [ {"type":"ARRAYSEL","name":"","addr":"(XV)","loc":"d,75:125,75:126","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(YV)","loc":"d,17:12,17:16","dtypep":"(TI)","access":"RD","varp":"(UI)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(ZV)","loc":"d,75:125,75:126","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(AW)","loc":"d,75:125,75:126","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(BW)","loc":"d,75:125,75:126","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(CW)","loc":"d,75:125,75:126","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ],"scopeNamep": []} ],"filep": []}, {"type":"STOP","name":"","addr":"(DW)","loc":"d,75:145,75:150","isFatal":false} ],"elsesp": []}, {"type":"IF","name":"","addr":"(EW)","loc":"d,76:13,76:15", "condp": [ {"type":"NEQ","name":"","addr":"(FW)","loc":"d,76:29,76:32","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"4'h3","addr":"(GW)","loc":"d,76:34,76:37","dtypep":"(RB)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(HW)","loc":"d,76:18,76:19","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(IW)","loc":"d,17:12,17:16","dtypep":"(TI)","access":"RD","varp":"(UI)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(JW)","loc":"d,76:18,76:19","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(KW)","loc":"d,76:18,76:19","dtypep":"(EC)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(LW)","loc":"d,76:18,76:19","dtypep":"(CC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(MW)","loc":"d,17:12,17:16","dtypep":"(TI)","access":"RD","varp":"(UI)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(NW)","loc":"d,76:18,76:19","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(OW)","loc":"d,76:18,76:19","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(PW)","loc":"d,76:18,76:19","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(QW)","loc":"d,76:18,76:19","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ]} ]} ], "thensp": [ {"type":"DISPLAY","name":"","addr":"(RW)","loc":"d,76:46,76:52", "fmtp": [ {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:76: got='h%x exp='h3\\n","addr":"(SW)","loc":"d,76:46,76:52","dtypep":"(PB)", "exprsp": [ {"type":"ARRAYSEL","name":"","addr":"(TW)","loc":"d,76:125,76:126","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(UW)","loc":"d,17:12,17:16","dtypep":"(TI)","access":"RD","varp":"(UI)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(VW)","loc":"d,76:125,76:126","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(WW)","loc":"d,76:125,76:126","dtypep":"(EC)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(XW)","loc":"d,76:125,76:126","dtypep":"(CC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(YW)","loc":"d,17:12,17:16","dtypep":"(TI)","access":"RD","varp":"(UI)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(ZW)","loc":"d,76:125,76:126","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(AX)","loc":"d,76:125,76:126","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(BX)","loc":"d,76:125,76:126","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(CX)","loc":"d,76:125,76:126","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ]} ],"scopeNamep": []} ],"filep": []}, {"type":"STOP","name":"","addr":"(DX)","loc":"d,76:145,76:150","isFatal":false} ],"elsesp": []}, {"type":"ASSIGNDLY","name":"","addr":"(EX)","loc":"d,77:12,77:14","dtypep":"(RB)", "rhsp": [ {"type":"CONST","name":"4'h3","addr":"(FX)","loc":"d,77:15,77:18","dtypep":"(RB)"} ], "lhsp": [ {"type":"VARREF","name":"__Vdly__t.e","addr":"(GX)","loc":"d,77:10,77:11","dtypep":"(RB)","access":"WR","varp":"(MQ)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": []} ], "elsesp": [ {"type":"IF","name":"","addr":"(HX)","loc":"d,79:12,79:14", "condp": [ {"type":"EQ","name":"","addr":"(IX)","loc":"d,79:19,79:21","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"32'sh2","addr":"(JX)","loc":"d,79:21,79:22","dtypep":"(IB)"} ], "rhsp": [ {"type":"VARREF","name":"t.cyc","addr":"(KX)","loc":"d,79:16,79:19","dtypep":"(P)","access":"RD","varp":"(O)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ], "thensp": [ {"type":"IF","name":"","addr":"(LX)","loc":"d,80:13,80:15", "condp": [ {"type":"NEQN","name":"","addr":"(MX)","loc":"d,80:26,80:28","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"\\\"E03\\\"","addr":"(NX)","loc":"d,80:30,80:35","dtypep":"(PB)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(OX)","loc":"d,80:18,80:19","dtypep":"(PB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_name1","addr":"(PX)","loc":"d,17:12,17:16","dtypep":"(FM)","access":"RD","varp":"(GM)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(QX)","loc":"d,80:18,80:19","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(RX)","loc":"d,80:18,80:19","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(SX)","loc":"d,80:18,80:19","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(TX)","loc":"d,80:18,80:19","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ], "thensp": [ {"type":"ASSIGN","name":"","addr":"(UX)","loc":"d,80:123,80:124","dtypep":"(PB)", "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(VX)","loc":"d,80:123,80:124","dtypep":"(PB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_name1","addr":"(WX)","loc":"d,17:12,17:16","dtypep":"(FM)","access":"RD","varp":"(GM)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(XX)","loc":"d,80:123,80:124","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(YX)","loc":"d,80:123,80:124","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(ZX)","loc":"d,80:123,80:124","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(AY)","loc":"d,80:123,80:124","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ], "lhsp": [ {"type":"VARREF","name":"__Vtemp_2","addr":"(BY)","loc":"d,80:123,80:124","dtypep":"(PB)","access":"WR","varp":"(QQ)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": []}, {"type":"DISPLAY","name":"","addr":"(CY)","loc":"d,80:44,80:50", "fmtp": [ {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:80: got='%@' exp='E03'\\n","addr":"(DY)","loc":"d,80:44,80:50","dtypep":"(PB)", "exprsp": [ {"type":"VARREF","name":"__Vtemp_2","addr":"(EY)","loc":"d,80:123,80:124","dtypep":"(PB)","access":"RD","varp":"(QQ)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"scopeNamep": []} ],"filep": []}, {"type":"STOP","name":"","addr":"(FY)","loc":"d,80:142,80:147","isFatal":false} ],"elsesp": []}, {"type":"IF","name":"","addr":"(GY)","loc":"d,81:13,81:15", "condp": [ {"type":"NEQ","name":"","addr":"(HY)","loc":"d,81:26,81:29","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"4'h4","addr":"(IY)","loc":"d,81:31,81:34","dtypep":"(RB)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(JY)","loc":"d,81:18,81:19","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(KY)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(LY)","loc":"d,81:18,81:19","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(MY)","loc":"d,81:18,81:19","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(NY)","loc":"d,81:18,81:19","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(OY)","loc":"d,81:18,81:19","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ], "thensp": [ {"type":"DISPLAY","name":"","addr":"(PY)","loc":"d,81:43,81:49", "fmtp": [ {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:81: got='h%x exp='h4\\n","addr":"(QY)","loc":"d,81:43,81:49","dtypep":"(PB)", "exprsp": [ {"type":"ARRAYSEL","name":"","addr":"(RY)","loc":"d,81:122,81:123","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(SY)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(TY)","loc":"d,81:122,81:123","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(UY)","loc":"d,81:122,81:123","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(VY)","loc":"d,81:122,81:123","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(WY)","loc":"d,81:122,81:123","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ],"scopeNamep": []} ],"filep": []}, {"type":"STOP","name":"","addr":"(XY)","loc":"d,81:139,81:144","isFatal":false} ],"elsesp": []}, {"type":"IF","name":"","addr":"(YY)","loc":"d,82:13,82:15", "condp": [ {"type":"NEQ","name":"","addr":"(ZY)","loc":"d,82:29,82:32","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"4'h4","addr":"(AZ)","loc":"d,82:34,82:37","dtypep":"(RB)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(BZ)","loc":"d,82:18,82:19","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(CZ)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(DZ)","loc":"d,82:18,82:19","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(EZ)","loc":"d,82:18,82:19","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(FZ)","loc":"d,82:18,82:19","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(GZ)","loc":"d,82:18,82:19","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ], "thensp": [ {"type":"DISPLAY","name":"","addr":"(HZ)","loc":"d,82:46,82:52", "fmtp": [ {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:82: got='h%x exp='h4\\n","addr":"(IZ)","loc":"d,82:46,82:52","dtypep":"(PB)", "exprsp": [ {"type":"ARRAYSEL","name":"","addr":"(JZ)","loc":"d,82:125,82:126","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(KZ)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(LZ)","loc":"d,82:125,82:126","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(MZ)","loc":"d,82:125,82:126","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(NZ)","loc":"d,82:125,82:126","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(OZ)","loc":"d,82:125,82:126","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ],"scopeNamep": []} ],"filep": []}, {"type":"STOP","name":"","addr":"(PZ)","loc":"d,82:145,82:150","isFatal":false} ],"elsesp": []}, {"type":"IF","name":"","addr":"(QZ)","loc":"d,83:13,83:15", "condp": [ {"type":"NEQ","name":"","addr":"(RZ)","loc":"d,83:29,83:32","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"4'h1","addr":"(SZ)","loc":"d,83:34,83:37","dtypep":"(RB)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(TZ)","loc":"d,83:18,83:19","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(UZ)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(VZ)","loc":"d,83:18,83:19","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(WZ)","loc":"d,83:18,83:19","dtypep":"(EC)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(XZ)","loc":"d,83:18,83:19","dtypep":"(CC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(YZ)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(ZZ)","loc":"d,83:18,83:19","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(AAB)","loc":"d,83:18,83:19","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(BAB)","loc":"d,83:18,83:19","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(CAB)","loc":"d,83:18,83:19","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ]} ]} ], "thensp": [ {"type":"DISPLAY","name":"","addr":"(DAB)","loc":"d,83:46,83:52", "fmtp": [ {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:83: got='h%x exp='h1\\n","addr":"(EAB)","loc":"d,83:46,83:52","dtypep":"(PB)", "exprsp": [ {"type":"ARRAYSEL","name":"","addr":"(FAB)","loc":"d,83:125,83:126","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(GAB)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(HAB)","loc":"d,83:125,83:126","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(IAB)","loc":"d,83:125,83:126","dtypep":"(EC)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(JAB)","loc":"d,83:125,83:126","dtypep":"(CC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(KAB)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(LAB)","loc":"d,83:125,83:126","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(MAB)","loc":"d,83:125,83:126","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(NAB)","loc":"d,83:125,83:126","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(OAB)","loc":"d,83:125,83:126","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ]} ],"scopeNamep": []} ],"filep": []}, {"type":"STOP","name":"","addr":"(PAB)","loc":"d,83:145,83:150","isFatal":false} ],"elsesp": []}, {"type":"IF","name":"","addr":"(QAB)","loc":"d,84:13,84:15", "condp": [ {"type":"NEQ","name":"","addr":"(RAB)","loc":"d,84:26,84:29","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"4'h1","addr":"(SAB)","loc":"d,84:31,84:34","dtypep":"(RB)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(TAB)","loc":"d,84:18,84:19","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(UAB)","loc":"d,17:12,17:16","dtypep":"(TI)","access":"RD","varp":"(UI)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(VAB)","loc":"d,84:18,84:19","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(WAB)","loc":"d,84:18,84:19","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(XAB)","loc":"d,84:18,84:19","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(YAB)","loc":"d,84:18,84:19","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ], "thensp": [ {"type":"DISPLAY","name":"","addr":"(ZAB)","loc":"d,84:43,84:49", "fmtp": [ {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:84: got='h%x exp='h1\\n","addr":"(ABB)","loc":"d,84:43,84:49","dtypep":"(PB)", "exprsp": [ {"type":"ARRAYSEL","name":"","addr":"(BBB)","loc":"d,84:122,84:123","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(CBB)","loc":"d,17:12,17:16","dtypep":"(TI)","access":"RD","varp":"(UI)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(DBB)","loc":"d,84:122,84:123","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(EBB)","loc":"d,84:122,84:123","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(FBB)","loc":"d,84:122,84:123","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(GBB)","loc":"d,84:122,84:123","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ],"scopeNamep": []} ],"filep": []}, {"type":"STOP","name":"","addr":"(HBB)","loc":"d,84:139,84:144","isFatal":false} ],"elsesp": []}, {"type":"IF","name":"","addr":"(IBB)","loc":"d,85:13,85:15", "condp": [ {"type":"NEQ","name":"","addr":"(JBB)","loc":"d,85:29,85:32","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"4'h1","addr":"(KBB)","loc":"d,85:34,85:37","dtypep":"(RB)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(LBB)","loc":"d,85:18,85:19","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(MBB)","loc":"d,17:12,17:16","dtypep":"(TI)","access":"RD","varp":"(UI)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(NBB)","loc":"d,85:18,85:19","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(OBB)","loc":"d,85:18,85:19","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(PBB)","loc":"d,85:18,85:19","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(QBB)","loc":"d,85:18,85:19","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ], "thensp": [ {"type":"DISPLAY","name":"","addr":"(RBB)","loc":"d,85:46,85:52", "fmtp": [ {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:85: got='h%x exp='h1\\n","addr":"(SBB)","loc":"d,85:46,85:52","dtypep":"(PB)", "exprsp": [ {"type":"ARRAYSEL","name":"","addr":"(TBB)","loc":"d,85:125,85:126","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(UBB)","loc":"d,17:12,17:16","dtypep":"(TI)","access":"RD","varp":"(UI)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(VBB)","loc":"d,85:125,85:126","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(WBB)","loc":"d,85:125,85:126","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(XBB)","loc":"d,85:125,85:126","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(YBB)","loc":"d,85:125,85:126","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ],"scopeNamep": []} ],"filep": []}, {"type":"STOP","name":"","addr":"(ZBB)","loc":"d,85:145,85:150","isFatal":false} ],"elsesp": []}, {"type":"IF","name":"","addr":"(ACB)","loc":"d,86:13,86:15", "condp": [ {"type":"NEQ","name":"","addr":"(BCB)","loc":"d,86:29,86:32","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"4'h4","addr":"(CCB)","loc":"d,86:34,86:37","dtypep":"(RB)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(DCB)","loc":"d,86:18,86:19","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(ECB)","loc":"d,17:12,17:16","dtypep":"(TI)","access":"RD","varp":"(UI)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(FCB)","loc":"d,86:18,86:19","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(GCB)","loc":"d,86:18,86:19","dtypep":"(EC)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(HCB)","loc":"d,86:18,86:19","dtypep":"(CC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(ICB)","loc":"d,17:12,17:16","dtypep":"(TI)","access":"RD","varp":"(UI)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(JCB)","loc":"d,86:18,86:19","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(KCB)","loc":"d,86:18,86:19","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(LCB)","loc":"d,86:18,86:19","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(MCB)","loc":"d,86:18,86:19","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ]} ]} ], "thensp": [ {"type":"DISPLAY","name":"","addr":"(NCB)","loc":"d,86:46,86:52", "fmtp": [ {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:86: got='h%x exp='h4\\n","addr":"(OCB)","loc":"d,86:46,86:52","dtypep":"(PB)", "exprsp": [ {"type":"ARRAYSEL","name":"","addr":"(PCB)","loc":"d,86:125,86:126","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(QCB)","loc":"d,17:12,17:16","dtypep":"(TI)","access":"RD","varp":"(UI)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(RCB)","loc":"d,86:125,86:126","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(SCB)","loc":"d,86:125,86:126","dtypep":"(EC)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(TCB)","loc":"d,86:125,86:126","dtypep":"(CC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(UCB)","loc":"d,17:12,17:16","dtypep":"(TI)","access":"RD","varp":"(UI)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(VCB)","loc":"d,86:125,86:126","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(WCB)","loc":"d,86:125,86:126","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(XCB)","loc":"d,86:125,86:126","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(YCB)","loc":"d,86:125,86:126","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ]} ],"scopeNamep": []} ],"filep": []}, {"type":"STOP","name":"","addr":"(ZCB)","loc":"d,86:145,86:150","isFatal":false} ],"elsesp": []}, {"type":"ASSIGNDLY","name":"","addr":"(ADB)","loc":"d,87:12,87:14","dtypep":"(RB)", "rhsp": [ {"type":"CONST","name":"4'h4","addr":"(BDB)","loc":"d,87:15,87:18","dtypep":"(RB)"} ], "lhsp": [ {"type":"VARREF","name":"__Vdly__t.e","addr":"(CDB)","loc":"d,87:10,87:11","dtypep":"(RB)","access":"WR","varp":"(MQ)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": []} ], "elsesp": [ {"type":"IF","name":"","addr":"(DDB)","loc":"d,89:12,89:14", "condp": [ {"type":"EQ","name":"","addr":"(EDB)","loc":"d,89:19,89:21","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"32'sh3","addr":"(FDB)","loc":"d,89:21,89:22","dtypep":"(IB)"} ], "rhsp": [ {"type":"VARREF","name":"t.cyc","addr":"(GDB)","loc":"d,89:16,89:19","dtypep":"(P)","access":"RD","varp":"(O)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ], "thensp": [ {"type":"IF","name":"","addr":"(HDB)","loc":"d,90:13,90:15", "condp": [ {"type":"NEQN","name":"","addr":"(IDB)","loc":"d,90:26,90:28","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"\\\"E04\\\"","addr":"(JDB)","loc":"d,90:30,90:35","dtypep":"(PB)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(KDB)","loc":"d,90:18,90:19","dtypep":"(PB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_name1","addr":"(LDB)","loc":"d,17:12,17:16","dtypep":"(FM)","access":"RD","varp":"(GM)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(MDB)","loc":"d,90:18,90:19","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(NDB)","loc":"d,90:18,90:19","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(ODB)","loc":"d,90:18,90:19","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(PDB)","loc":"d,90:18,90:19","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ], "thensp": [ {"type":"ASSIGN","name":"","addr":"(QDB)","loc":"d,90:123,90:124","dtypep":"(PB)", "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(RDB)","loc":"d,90:123,90:124","dtypep":"(PB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_name1","addr":"(SDB)","loc":"d,17:12,17:16","dtypep":"(FM)","access":"RD","varp":"(GM)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(TDB)","loc":"d,90:123,90:124","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(UDB)","loc":"d,90:123,90:124","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(VDB)","loc":"d,90:123,90:124","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(WDB)","loc":"d,90:123,90:124","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ], "lhsp": [ {"type":"VARREF","name":"__Vtemp_3","addr":"(XDB)","loc":"d,90:123,90:124","dtypep":"(PB)","access":"WR","varp":"(RQ)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": []}, {"type":"DISPLAY","name":"","addr":"(YDB)","loc":"d,90:44,90:50", "fmtp": [ {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:90: got='%@' exp='E04'\\n","addr":"(ZDB)","loc":"d,90:44,90:50","dtypep":"(PB)", "exprsp": [ {"type":"VARREF","name":"__Vtemp_3","addr":"(AEB)","loc":"d,90:123,90:124","dtypep":"(PB)","access":"RD","varp":"(RQ)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"scopeNamep": []} ],"filep": []}, {"type":"STOP","name":"","addr":"(BEB)","loc":"d,90:142,90:147","isFatal":false} ],"elsesp": []}, {"type":"IF","name":"","addr":"(CEB)","loc":"d,91:13,91:15", "condp": [ {"type":"NEQ","name":"","addr":"(DEB)","loc":"d,91:26,91:29","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"4'h1","addr":"(EEB)","loc":"d,91:31,91:34","dtypep":"(RB)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(FEB)","loc":"d,91:18,91:19","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(GEB)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(HEB)","loc":"d,91:18,91:19","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(IEB)","loc":"d,91:18,91:19","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(JEB)","loc":"d,91:18,91:19","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(KEB)","loc":"d,91:18,91:19","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ], "thensp": [ {"type":"DISPLAY","name":"","addr":"(LEB)","loc":"d,91:43,91:49", "fmtp": [ {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:91: got='h%x exp='h1\\n","addr":"(MEB)","loc":"d,91:43,91:49","dtypep":"(PB)", "exprsp": [ {"type":"ARRAYSEL","name":"","addr":"(NEB)","loc":"d,91:122,91:123","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(OEB)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(PEB)","loc":"d,91:122,91:123","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(QEB)","loc":"d,91:122,91:123","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(REB)","loc":"d,91:122,91:123","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(SEB)","loc":"d,91:122,91:123","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ],"scopeNamep": []} ],"filep": []}, {"type":"STOP","name":"","addr":"(TEB)","loc":"d,91:139,91:144","isFatal":false} ],"elsesp": []}, {"type":"IF","name":"","addr":"(UEB)","loc":"d,92:13,92:15", "condp": [ {"type":"NEQ","name":"","addr":"(VEB)","loc":"d,92:29,92:32","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"4'h1","addr":"(WEB)","loc":"d,92:34,92:37","dtypep":"(RB)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(XEB)","loc":"d,92:18,92:19","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(YEB)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(ZEB)","loc":"d,92:18,92:19","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(AFB)","loc":"d,92:18,92:19","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(BFB)","loc":"d,92:18,92:19","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(CFB)","loc":"d,92:18,92:19","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ], "thensp": [ {"type":"DISPLAY","name":"","addr":"(DFB)","loc":"d,92:46,92:52", "fmtp": [ {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:92: got='h%x exp='h1\\n","addr":"(EFB)","loc":"d,92:46,92:52","dtypep":"(PB)", "exprsp": [ {"type":"ARRAYSEL","name":"","addr":"(FFB)","loc":"d,92:125,92:126","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(GFB)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(HFB)","loc":"d,92:125,92:126","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(IFB)","loc":"d,92:125,92:126","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(JFB)","loc":"d,92:125,92:126","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(KFB)","loc":"d,92:125,92:126","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ],"scopeNamep": []} ],"filep": []}, {"type":"STOP","name":"","addr":"(LFB)","loc":"d,92:145,92:150","isFatal":false} ],"elsesp": []}, {"type":"IF","name":"","addr":"(MFB)","loc":"d,93:13,93:15", "condp": [ {"type":"NEQ","name":"","addr":"(NFB)","loc":"d,93:29,93:32","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"4'h3","addr":"(OFB)","loc":"d,93:34,93:37","dtypep":"(RB)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(PFB)","loc":"d,93:18,93:19","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(QFB)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(RFB)","loc":"d,93:18,93:19","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(SFB)","loc":"d,93:18,93:19","dtypep":"(EC)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(TFB)","loc":"d,93:18,93:19","dtypep":"(CC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(UFB)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(VFB)","loc":"d,93:18,93:19","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(WFB)","loc":"d,93:18,93:19","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(XFB)","loc":"d,93:18,93:19","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(YFB)","loc":"d,93:18,93:19","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ]} ]} ], "thensp": [ {"type":"DISPLAY","name":"","addr":"(ZFB)","loc":"d,93:46,93:52", "fmtp": [ {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:93: got='h%x exp='h3\\n","addr":"(AGB)","loc":"d,93:46,93:52","dtypep":"(PB)", "exprsp": [ {"type":"ARRAYSEL","name":"","addr":"(BGB)","loc":"d,93:125,93:126","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(CGB)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(DGB)","loc":"d,93:125,93:126","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(EGB)","loc":"d,93:125,93:126","dtypep":"(EC)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(FGB)","loc":"d,93:125,93:126","dtypep":"(CC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(GGB)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(HGB)","loc":"d,93:125,93:126","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(IGB)","loc":"d,93:125,93:126","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(JGB)","loc":"d,93:125,93:126","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(KGB)","loc":"d,93:125,93:126","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ]} ],"scopeNamep": []} ],"filep": []}, {"type":"STOP","name":"","addr":"(LGB)","loc":"d,93:145,93:150","isFatal":false} ],"elsesp": []}, {"type":"IF","name":"","addr":"(MGB)","loc":"d,94:13,94:15", "condp": [ {"type":"NEQ","name":"","addr":"(NGB)","loc":"d,94:26,94:29","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"4'h3","addr":"(OGB)","loc":"d,94:31,94:34","dtypep":"(RB)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(PGB)","loc":"d,94:18,94:19","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(QGB)","loc":"d,17:12,17:16","dtypep":"(TI)","access":"RD","varp":"(UI)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(RGB)","loc":"d,94:18,94:19","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(SGB)","loc":"d,94:18,94:19","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(TGB)","loc":"d,94:18,94:19","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(UGB)","loc":"d,94:18,94:19","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ], "thensp": [ {"type":"DISPLAY","name":"","addr":"(VGB)","loc":"d,94:43,94:49", "fmtp": [ {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:94: got='h%x exp='h3\\n","addr":"(WGB)","loc":"d,94:43,94:49","dtypep":"(PB)", "exprsp": [ {"type":"ARRAYSEL","name":"","addr":"(XGB)","loc":"d,94:122,94:123","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(YGB)","loc":"d,17:12,17:16","dtypep":"(TI)","access":"RD","varp":"(UI)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(ZGB)","loc":"d,94:122,94:123","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(AHB)","loc":"d,94:122,94:123","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(BHB)","loc":"d,94:122,94:123","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(CHB)","loc":"d,94:122,94:123","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ],"scopeNamep": []} ],"filep": []}, {"type":"STOP","name":"","addr":"(DHB)","loc":"d,94:139,94:144","isFatal":false} ],"elsesp": []}, {"type":"IF","name":"","addr":"(EHB)","loc":"d,95:13,95:15", "condp": [ {"type":"NEQ","name":"","addr":"(FHB)","loc":"d,95:29,95:32","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"4'h3","addr":"(GHB)","loc":"d,95:34,95:37","dtypep":"(RB)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(HHB)","loc":"d,95:18,95:19","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(IHB)","loc":"d,17:12,17:16","dtypep":"(TI)","access":"RD","varp":"(UI)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(JHB)","loc":"d,95:18,95:19","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(KHB)","loc":"d,95:18,95:19","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(LHB)","loc":"d,95:18,95:19","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(MHB)","loc":"d,95:18,95:19","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ], "thensp": [ {"type":"DISPLAY","name":"","addr":"(NHB)","loc":"d,95:46,95:52", "fmtp": [ {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:95: got='h%x exp='h3\\n","addr":"(OHB)","loc":"d,95:46,95:52","dtypep":"(PB)", "exprsp": [ {"type":"ARRAYSEL","name":"","addr":"(PHB)","loc":"d,95:125,95:126","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(QHB)","loc":"d,17:12,17:16","dtypep":"(TI)","access":"RD","varp":"(UI)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(RHB)","loc":"d,95:125,95:126","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(SHB)","loc":"d,95:125,95:126","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(THB)","loc":"d,95:125,95:126","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(UHB)","loc":"d,95:125,95:126","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ],"scopeNamep": []} ],"filep": []}, {"type":"STOP","name":"","addr":"(VHB)","loc":"d,95:145,95:150","isFatal":false} ],"elsesp": []}, {"type":"IF","name":"","addr":"(WHB)","loc":"d,96:13,96:15", "condp": [ {"type":"NEQ","name":"","addr":"(XHB)","loc":"d,96:29,96:32","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"4'h1","addr":"(YHB)","loc":"d,96:34,96:37","dtypep":"(RB)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(ZHB)","loc":"d,96:18,96:19","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(AIB)","loc":"d,17:12,17:16","dtypep":"(TI)","access":"RD","varp":"(UI)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(BIB)","loc":"d,96:18,96:19","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(CIB)","loc":"d,96:18,96:19","dtypep":"(EC)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(DIB)","loc":"d,96:18,96:19","dtypep":"(CC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(EIB)","loc":"d,17:12,17:16","dtypep":"(TI)","access":"RD","varp":"(UI)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(FIB)","loc":"d,96:18,96:19","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(GIB)","loc":"d,96:18,96:19","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(HIB)","loc":"d,96:18,96:19","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(IIB)","loc":"d,96:18,96:19","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ]} ]} ], "thensp": [ {"type":"DISPLAY","name":"","addr":"(JIB)","loc":"d,96:46,96:52", "fmtp": [ {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:96: got='h%x exp='h1\\n","addr":"(KIB)","loc":"d,96:46,96:52","dtypep":"(PB)", "exprsp": [ {"type":"ARRAYSEL","name":"","addr":"(LIB)","loc":"d,96:125,96:126","dtypep":"(RB)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(MIB)","loc":"d,17:12,17:16","dtypep":"(TI)","access":"RD","varp":"(UI)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(NIB)","loc":"d,96:125,96:126","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(OIB)","loc":"d,96:125,96:126","dtypep":"(EC)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(PIB)","loc":"d,96:125,96:126","dtypep":"(CC)", "fromp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(QIB)","loc":"d,17:12,17:16","dtypep":"(TI)","access":"RD","varp":"(UI)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"AND","name":"","addr":"(RIB)","loc":"d,96:125,96:126","dtypep":"(CC)", "lhsp": [ {"type":"CONST","name":"32'h7","addr":"(SIB)","loc":"d,96:125,96:126","dtypep":"(EC)"} ], "rhsp": [ {"type":"CCAST","name":"","addr":"(TIB)","loc":"d,96:125,96:126","dtypep":"(CC)","size":32, "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(UIB)","loc":"d,96:125,96:126","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ]} ],"scopeNamep": []} ],"filep": []}, {"type":"STOP","name":"","addr":"(VIB)","loc":"d,96:145,96:150","isFatal":false} ],"elsesp": []}, {"type":"ASSIGNDLY","name":"","addr":"(WIB)","loc":"d,97:12,97:14","dtypep":"(RB)", "rhsp": [ {"type":"CONST","name":"4'h1","addr":"(XIB)","loc":"d,97:15,97:18","dtypep":"(RB)"} ], "lhsp": [ {"type":"VARREF","name":"__Vdly__t.e","addr":"(YIB)","loc":"d,97:10,97:11","dtypep":"(RB)","access":"WR","varp":"(MQ)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": []} ], "elsesp": [ {"type":"IF","name":"","addr":"(ZIB)","loc":"d,99:12,99:14", "condp": [ {"type":"EQ","name":"","addr":"(AJB)","loc":"d,99:19,99:21","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"32'sh63","addr":"(BJB)","loc":"d,99:21,99:23","dtypep":"(IB)"} ], "rhsp": [ {"type":"VARREF","name":"t.cyc","addr":"(CJB)","loc":"d,99:16,99:19","dtypep":"(P)","access":"RD","varp":"(O)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ], "thensp": [ {"type":"DISPLAY","name":"","addr":"(DJB)","loc":"d,100:10,100:16", "fmtp": [ {"type":"SFORMATF","name":"*-* All Finished *-*\\n","addr":"(EJB)","loc":"d,100:10,100:16","dtypep":"(PB)","exprsp": [],"scopeNamep": []} ],"filep": []}, {"type":"FINISH","name":"","addr":"(FJB)","loc":"d,101:10,101:17"} ],"elsesp": []} ]} ]} ]} ]}, {"type":"ASSIGN","name":"","addr":"(GJB)","loc":"d,23:17,23:20","dtypep":"(P)", "rhsp": [ {"type":"VARREF","name":"__Vdly__t.cyc","addr":"(HJB)","loc":"d,23:17,23:20","dtypep":"(P)","access":"RD","varp":"(JQ)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "lhsp": [ {"type":"VARREF","name":"t.cyc","addr":"(IJB)","loc":"d,23:17,23:20","dtypep":"(P)","access":"WR","varp":"(O)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": []}, {"type":"ASSIGN","name":"","addr":"(JJB)","loc":"d,24:9,24:10","dtypep":"(RB)", "rhsp": [ {"type":"VARREF","name":"__Vdly__t.e","addr":"(KJB)","loc":"d,24:9,24:10","dtypep":"(RB)","access":"RD","varp":"(MQ)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "lhsp": [ {"type":"VARREF","name":"t.e","addr":"(LJB)","loc":"d,24:9,24:10","dtypep":"(RB)","access":"WR","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": []} ]}, {"type":"CFUNC","name":"_eval_nba","addr":"(G)","loc":"a,0:0,0:0","slow":false,"isStatic":false,"dpiExportDispatcher":false,"dpiExportImpl":false,"dpiImportPrototype":false,"dpiImportWrapper":false,"dpiContext":false,"isConstructor":false,"isDestructor":false,"isVirtual":false,"isCoroutine":false,"needProcess":false,"scopep":"(W)","argsp": [],"varsp": [], "stmtsp": [ {"type":"IF","name":"","addr":"(MJB)","loc":"d,11:8,11:9", "condp": [ {"type":"AND","name":"","addr":"(NJB)","loc":"d,11:8,11:9","dtypep":"(GN)", "lhsp": [ {"type":"CONST","name":"64'h1","addr":"(OJB)","loc":"d,11:8,11:9","dtypep":"(GN)"} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(PJB)","loc":"d,11:8,11:9","dtypep":"(EN)", "fromp": [ {"type":"VARREF","name":"__VnbaTriggered","addr":"(QJB)","loc":"d,11:8,11:9","dtypep":"(T)","access":"RD","varp":"(U)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"CONST","name":"32'h0","addr":"(RJB)","loc":"d,11:8,11:9","dtypep":"(EC)"} ]} ]} ], "thensp": [ {"type":"STMTEXPR","name":"","addr":"(SJB)","loc":"d,23:17,23:20", "exprp": [ {"type":"CCALL","name":"","addr":"(TJB)","loc":"d,23:17,23:20","dtypep":"(AB)","funcName":"_nba_sequent__TOP__0","funcp":"(IQ)","argsp": []} ]} ],"elsesp": []} ]}, {"type":"CFUNC","name":"_trigger_orInto__act","addr":"(UJB)","loc":"a,0:0,0:0","slow":false,"isStatic":true,"dpiExportDispatcher":false,"dpiExportImpl":false,"dpiImportPrototype":false,"dpiImportWrapper":false,"dpiContext":false,"isConstructor":false,"isDestructor":false,"isVirtual":false,"isCoroutine":false,"needProcess":false,"scopep":"(W)", "argsp": [ {"type":"VAR","name":"out","addr":"(VJB)","loc":"a,0:0,0:0","dtypep":"(T)","origName":"out","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INOUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":true,"lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"CRESET","name":"","addr":"(WJB)","loc":"a,0:0,0:0","constructing":true, "varrefp": [ {"type":"VARREF","name":"out","addr":"(XJB)","loc":"a,0:0,0:0","dtypep":"(T)","access":"WR","varp":"(VJB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]}, {"type":"VAR","name":"in","addr":"(YJB)","loc":"a,0:0,0:0","dtypep":"(T)","origName":"in","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"CONSTREF","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":true,"lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"CRESET","name":"","addr":"(ZJB)","loc":"a,0:0,0:0","constructing":true, "varrefp": [ {"type":"VARREF","name":"in","addr":"(AKB)","loc":"a,0:0,0:0","dtypep":"(T)","access":"WR","varp":"(YJB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ], "varsp": [ {"type":"VAR","name":"n","addr":"(BKB)","loc":"a,0:0,0:0","dtypep":"(LP)","origName":"n","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":true,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":true,"lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"IData","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ], "stmtsp": [ {"type":"ASSIGN","name":"","addr":"(CKB)","loc":"a,0:0,0:0","dtypep":"(LP)", "rhsp": [ {"type":"CONST","name":"32'h0","addr":"(DKB)","loc":"a,0:0,0:0","dtypep":"(EC)"} ], "lhsp": [ {"type":"VARREF","name":"n","addr":"(EKB)","loc":"a,0:0,0:0","dtypep":"(LP)","access":"WR","varp":"(BKB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": []}, {"type":"LOOP","name":"","addr":"(FKB)","loc":"d,11:8,11:9","unroll":"default", "stmtsp": [ {"type":"ASSIGN","name":"","addr":"(GKB)","loc":"d,11:8,11:9","dtypep":"(EN)", "rhsp": [ {"type":"OR","name":"","addr":"(HKB)","loc":"d,11:8,11:9","dtypep":"(EN)", "lhsp": [ {"type":"ARRAYSEL","name":"","addr":"(IKB)","loc":"d,11:8,11:9","dtypep":"(EN)", "fromp": [ {"type":"VARREF","name":"out","addr":"(JKB)","loc":"d,11:8,11:9","dtypep":"(T)","access":"RD","varp":"(VJB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"VARREF","name":"n","addr":"(KKB)","loc":"d,11:8,11:9","dtypep":"(LP)","access":"RD","varp":"(BKB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ], "rhsp": [ {"type":"ARRAYSEL","name":"","addr":"(LKB)","loc":"d,11:8,11:9","dtypep":"(EN)", "fromp": [ {"type":"VARREF","name":"in","addr":"(MKB)","loc":"d,11:8,11:9","dtypep":"(T)","access":"RD","varp":"(YJB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"VARREF","name":"n","addr":"(NKB)","loc":"d,11:8,11:9","dtypep":"(LP)","access":"RD","varp":"(BKB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ], "lhsp": [ {"type":"ARRAYSEL","name":"","addr":"(OKB)","loc":"d,11:8,11:9","dtypep":"(EN)", "fromp": [ {"type":"VARREF","name":"out","addr":"(PKB)","loc":"d,11:8,11:9","dtypep":"(T)","access":"WR","varp":"(VJB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"VARREF","name":"n","addr":"(QKB)","loc":"d,11:8,11:9","dtypep":"(LP)","access":"RD","varp":"(BKB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ],"timingControlp": []}, {"type":"ASSIGN","name":"","addr":"(RKB)","loc":"a,0:0,0:0","dtypep":"(LP)", "rhsp": [ {"type":"ADD","name":"","addr":"(SKB)","loc":"a,0:0,0:0","dtypep":"(LP)", "lhsp": [ {"type":"CCAST","name":"","addr":"(TKB)","loc":"a,0:0,0:0","dtypep":"(EC)","size":32, "lhsp": [ {"type":"CONST","name":"32'h1","addr":"(UKB)","loc":"a,0:0,0:0","dtypep":"(EC)"} ]} ], "rhsp": [ {"type":"VARREF","name":"n","addr":"(VKB)","loc":"a,0:0,0:0","dtypep":"(LP)","access":"RD","varp":"(BKB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ], "lhsp": [ {"type":"VARREF","name":"n","addr":"(WKB)","loc":"a,0:0,0:0","dtypep":"(LP)","access":"WR","varp":"(BKB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": []}, {"type":"LOOPTEST","name":"","addr":"(XKB)","loc":"d,11:8,11:9", "condp": [ {"type":"GT","name":"","addr":"(YKB)","loc":"d,11:8,11:9","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"32'h1","addr":"(ZKB)","loc":"d,11:8,11:9","dtypep":"(EC)"} ], "rhsp": [ {"type":"VARREF","name":"n","addr":"(ALB)","loc":"d,11:8,11:9","dtypep":"(LP)","access":"RD","varp":"(BKB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ],"contsp": []} ]}, {"type":"CFUNC","name":"_eval_phase__act","addr":"(BLB)","loc":"a,0:0,0:0","slow":false,"isStatic":false,"dpiExportDispatcher":false,"dpiExportImpl":false,"dpiImportPrototype":false,"dpiImportWrapper":false,"dpiContext":false,"isConstructor":false,"isDestructor":false,"isVirtual":false,"isCoroutine":false,"needProcess":false,"scopep":"(W)","argsp": [],"varsp": [], "stmtsp": [ {"type":"STMTEXPR","name":"","addr":"(CLB)","loc":"d,11:8,11:9", "exprp": [ {"type":"CCALL","name":"","addr":"(DLB)","loc":"d,11:8,11:9","dtypep":"(AB)","funcName":"_eval_triggers__act","funcp":"(CN)","argsp": []} ]}, {"type":"STMTEXPR","name":"","addr":"(ELB)","loc":"d,11:8,11:9", "exprp": [ {"type":"CCALL","name":"","addr":"(FLB)","loc":"d,11:8,11:9","dtypep":"(AB)","funcName":"_trigger_orInto__act","funcp":"(UJB)", "argsp": [ {"type":"VARREF","name":"__VnbaTriggered","addr":"(GLB)","loc":"d,11:8,11:9","dtypep":"(T)","access":"WR","varp":"(U)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"}, {"type":"VARREF","name":"__VactTriggered","addr":"(HLB)","loc":"d,11:8,11:9","dtypep":"(T)","access":"RD","varp":"(S)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]}, {"type":"CRETURN","name":"","addr":"(ILB)","loc":"a,0:0,0:0", "lhsp": [ {"type":"CONST","name":"1'h0","addr":"(JLB)","loc":"a,0:0,0:0","dtypep":"(DB)"} ]} ]}, {"type":"CFUNC","name":"_trigger_clear__act","addr":"(KLB)","loc":"a,0:0,0:0","slow":false,"isStatic":true,"dpiExportDispatcher":false,"dpiExportImpl":false,"dpiImportPrototype":false,"dpiImportWrapper":false,"dpiContext":false,"isConstructor":false,"isDestructor":false,"isVirtual":false,"isCoroutine":false,"needProcess":false,"scopep":"(W)", "argsp": [ {"type":"VAR","name":"out","addr":"(LLB)","loc":"a,0:0,0:0","dtypep":"(T)","origName":"out","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":true,"lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"CRESET","name":"","addr":"(MLB)","loc":"a,0:0,0:0","constructing":true, "varrefp": [ {"type":"VARREF","name":"out","addr":"(NLB)","loc":"a,0:0,0:0","dtypep":"(T)","access":"WR","varp":"(LLB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ], "varsp": [ {"type":"VAR","name":"n","addr":"(OLB)","loc":"a,0:0,0:0","dtypep":"(LP)","origName":"n","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":true,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":true,"lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"IData","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ], "stmtsp": [ {"type":"ASSIGN","name":"","addr":"(PLB)","loc":"a,0:0,0:0","dtypep":"(LP)", "rhsp": [ {"type":"CONST","name":"32'h0","addr":"(QLB)","loc":"a,0:0,0:0","dtypep":"(EC)"} ], "lhsp": [ {"type":"VARREF","name":"n","addr":"(RLB)","loc":"a,0:0,0:0","dtypep":"(LP)","access":"WR","varp":"(OLB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": []}, {"type":"LOOP","name":"","addr":"(SLB)","loc":"d,11:8,11:9","unroll":"default", "stmtsp": [ {"type":"ASSIGN","name":"","addr":"(TLB)","loc":"d,11:8,11:9","dtypep":"(EN)", "rhsp": [ {"type":"CONST","name":"64'h0","addr":"(ULB)","loc":"d,11:8,11:9","dtypep":"(GN)"} ], "lhsp": [ {"type":"ARRAYSEL","name":"","addr":"(VLB)","loc":"d,11:8,11:9","dtypep":"(EN)", "fromp": [ {"type":"VARREF","name":"out","addr":"(WLB)","loc":"d,11:8,11:9","dtypep":"(T)","access":"WR","varp":"(LLB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ {"type":"VARREF","name":"n","addr":"(XLB)","loc":"d,11:8,11:9","dtypep":"(LP)","access":"RD","varp":"(OLB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ],"timingControlp": []}, {"type":"ASSIGN","name":"","addr":"(YLB)","loc":"a,0:0,0:0","dtypep":"(LP)", "rhsp": [ {"type":"ADD","name":"","addr":"(ZLB)","loc":"a,0:0,0:0","dtypep":"(LP)", "lhsp": [ {"type":"CCAST","name":"","addr":"(AMB)","loc":"a,0:0,0:0","dtypep":"(EC)","size":32, "lhsp": [ {"type":"CONST","name":"32'h1","addr":"(BMB)","loc":"a,0:0,0:0","dtypep":"(EC)"} ]} ], "rhsp": [ {"type":"VARREF","name":"n","addr":"(CMB)","loc":"a,0:0,0:0","dtypep":"(LP)","access":"RD","varp":"(OLB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ], "lhsp": [ {"type":"VARREF","name":"n","addr":"(DMB)","loc":"a,0:0,0:0","dtypep":"(LP)","access":"WR","varp":"(OLB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": []}, {"type":"LOOPTEST","name":"","addr":"(EMB)","loc":"d,11:8,11:9", "condp": [ {"type":"GT","name":"","addr":"(FMB)","loc":"d,11:8,11:9","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"32'h1","addr":"(GMB)","loc":"d,11:8,11:9","dtypep":"(EC)"} ], "rhsp": [ {"type":"VARREF","name":"n","addr":"(HMB)","loc":"d,11:8,11:9","dtypep":"(LP)","access":"RD","varp":"(OLB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ],"contsp": []} ]}, {"type":"CFUNC","name":"_eval_phase__nba","addr":"(IMB)","loc":"a,0:0,0:0","slow":false,"isStatic":false,"dpiExportDispatcher":false,"dpiExportImpl":false,"dpiImportPrototype":false,"dpiImportWrapper":false,"dpiContext":false,"isConstructor":false,"isDestructor":false,"isVirtual":false,"isCoroutine":false,"needProcess":false,"scopep":"(W)","argsp": [], "varsp": [ {"type":"VAR","name":"__VnbaExecute","addr":"(JMB)","loc":"d,11:8,11:9","dtypep":"(KMB)","origName":"__VnbaExecute","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":true,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":true,"lifetime":"NONE","varType":"MODULETEMP","dtypeName":"bit","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ], "stmtsp": [ {"type":"ASSIGN","name":"","addr":"(LMB)","loc":"a,0:0,0:0","dtypep":"(DB)", "rhsp": [ {"type":"CCALL","name":"","addr":"(MMB)","loc":"d,11:8,11:9","dtypep":"(DB)","funcName":"_trigger_anySet__act","funcp":"(QO)", "argsp": [ {"type":"VARREF","name":"__VnbaTriggered","addr":"(NMB)","loc":"d,11:8,11:9","dtypep":"(T)","access":"WR","varp":"(U)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ], "lhsp": [ {"type":"VARREF","name":"__VnbaExecute","addr":"(OMB)","loc":"a,0:0,0:0","dtypep":"(DB)","access":"WR","varp":"(JMB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": []}, {"type":"IF","name":"","addr":"(PMB)","loc":"a,0:0,0:0", "condp": [ {"type":"VARREF","name":"__VnbaExecute","addr":"(QMB)","loc":"a,0:0,0:0","dtypep":"(DB)","access":"RD","varp":"(JMB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "thensp": [ {"type":"STMTEXPR","name":"","addr":"(RMB)","loc":"a,0:0,0:0", "exprp": [ {"type":"CCALL","name":"","addr":"(SMB)","loc":"a,0:0,0:0","dtypep":"(AB)","funcName":"_eval_nba","funcp":"(G)","argsp": []} ]}, {"type":"STMTEXPR","name":"","addr":"(TMB)","loc":"d,11:8,11:9", "exprp": [ {"type":"CCALL","name":"","addr":"(UMB)","loc":"d,11:8,11:9","dtypep":"(AB)","funcName":"_trigger_clear__act","funcp":"(KLB)", "argsp": [ {"type":"VARREF","name":"__VnbaTriggered","addr":"(VMB)","loc":"d,11:8,11:9","dtypep":"(T)","access":"WR","varp":"(U)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ],"elsesp": []}, {"type":"CRETURN","name":"","addr":"(WMB)","loc":"a,0:0,0:0", "lhsp": [ {"type":"VARREF","name":"__VnbaExecute","addr":"(XMB)","loc":"a,0:0,0:0","dtypep":"(DB)","access":"RD","varp":"(JMB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]}, {"type":"CFUNC","name":"_eval","addr":"(F)","loc":"a,0:0,0:0","slow":false,"isStatic":false,"dpiExportDispatcher":false,"dpiExportImpl":false,"dpiImportPrototype":false,"dpiImportWrapper":false,"dpiContext":false,"isConstructor":false,"isDestructor":false,"isVirtual":false,"isCoroutine":false,"needProcess":false,"scopep":"(W)","argsp": [], "varsp": [ {"type":"VAR","name":"__VnbaIterCount","addr":"(YMB)","loc":"d,11:8,11:9","dtypep":"(R)","origName":"__VnbaIterCount","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":true,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":true,"lifetime":"NONE","varType":"MODULETEMP","dtypeName":"bit","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ], "stmtsp": [ {"type":"ASSIGN","name":"","addr":"(ZMB)","loc":"d,11:8,11:9","dtypep":"(R)", "rhsp": [ {"type":"CONST","name":"32'h0","addr":"(ANB)","loc":"d,11:8,11:9","dtypep":"(EC)"} ], "lhsp": [ {"type":"VARREF","name":"__VnbaIterCount","addr":"(BNB)","loc":"d,11:8,11:9","dtypep":"(R)","access":"WR","varp":"(YMB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": []}, {"type":"LOOP","name":"","addr":"(CNB)","loc":"a,0:0,0:0","unroll":"default", "stmtsp": [ {"type":"IF","name":"","addr":"(DNB)","loc":"a,0:0,0:0", "condp": [ {"type":"LT","name":"","addr":"(ENB)","loc":"a,0:0,0:0","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"32'h64","addr":"(FNB)","loc":"a,0:0,0:0","dtypep":"(EC)"} ], "rhsp": [ {"type":"VARREF","name":"__VnbaIterCount","addr":"(GNB)","loc":"a,0:0,0:0","dtypep":"(R)","access":"RD","varp":"(YMB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ], "thensp": [ {"type":"CSTMT","name":"","addr":"(HNB)","loc":"d,11:8,11:9", "nodesp": [ {"type":"TEXT","name":"","addr":"(INB)","loc":"d,11:8,11:9","text":"#ifdef VL_DEBUG\n"}, {"type":"STMTEXPR","name":"","addr":"(JNB)","loc":"d,11:8,11:9", "exprp": [ {"type":"CCALL","name":"","addr":"(KNB)","loc":"d,11:8,11:9","dtypep":"(AB)","funcName":"_dump_triggers__act","funcp":"(ZN)", "argsp": [ {"type":"VARREF","name":"__VnbaTriggered","addr":"(LNB)","loc":"d,11:8,11:9","dtypep":"(T)","access":"RD","varp":"(U)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"}, {"type":"CONST","name":"\\\"nba\\\"","addr":"(MNB)","loc":"d,11:8,11:9","dtypep":"(PB)"} ]} ]}, {"type":"TEXT","name":"","addr":"(NNB)","loc":"d,11:8,11:9","text":"#endif"} ]}, {"type":"CSTMT","name":"","addr":"(ONB)","loc":"a,0:0,0:0", "nodesp": [ {"type":"TEXT","name":"","addr":"(PNB)","loc":"a,0:0,0:0","text":"VL_FATAL_MT(\"t/t_enum_type_methods.v\", 11, \"\", \"NBA region did not converge after 100 tries\");"} ]} ],"elsesp": []}, {"type":"ASSIGN","name":"","addr":"(QNB)","loc":"d,11:8,11:9","dtypep":"(R)", "rhsp": [ {"type":"ADD","name":"","addr":"(RNB)","loc":"d,11:8,11:9","dtypep":"(R)", "lhsp": [ {"type":"CCAST","name":"","addr":"(SNB)","loc":"d,11:8,11:9","dtypep":"(EC)","size":32, "lhsp": [ {"type":"CONST","name":"32'h1","addr":"(TNB)","loc":"d,11:8,11:9","dtypep":"(EC)"} ]} ], "rhsp": [ {"type":"VARREF","name":"__VnbaIterCount","addr":"(UNB)","loc":"d,11:8,11:9","dtypep":"(R)","access":"RD","varp":"(YMB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ], "lhsp": [ {"type":"VARREF","name":"__VnbaIterCount","addr":"(VNB)","loc":"d,11:8,11:9","dtypep":"(R)","access":"WR","varp":"(YMB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": []}, {"type":"ASSIGN","name":"","addr":"(WNB)","loc":"d,11:8,11:9","dtypep":"(R)", "rhsp": [ {"type":"CONST","name":"32'h0","addr":"(XNB)","loc":"d,11:8,11:9","dtypep":"(EC)"} ], "lhsp": [ {"type":"VARREF","name":"__VactIterCount","addr":"(YNB)","loc":"d,11:8,11:9","dtypep":"(R)","access":"WR","varp":"(Q)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": []}, {"type":"LOOP","name":"","addr":"(ZNB)","loc":"a,0:0,0:0","unroll":"default", "stmtsp": [ {"type":"IF","name":"","addr":"(AOB)","loc":"a,0:0,0:0", "condp": [ {"type":"LT","name":"","addr":"(BOB)","loc":"a,0:0,0:0","dtypep":"(DB)", "lhsp": [ {"type":"CONST","name":"32'h64","addr":"(COB)","loc":"a,0:0,0:0","dtypep":"(EC)"} ], "rhsp": [ {"type":"VARREF","name":"__VactIterCount","addr":"(DOB)","loc":"a,0:0,0:0","dtypep":"(R)","access":"RD","varp":"(Q)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ], "thensp": [ {"type":"CSTMT","name":"","addr":"(EOB)","loc":"d,11:8,11:9", "nodesp": [ {"type":"TEXT","name":"","addr":"(FOB)","loc":"d,11:8,11:9","text":"#ifdef VL_DEBUG\n"}, {"type":"STMTEXPR","name":"","addr":"(GOB)","loc":"d,11:8,11:9", "exprp": [ {"type":"CCALL","name":"","addr":"(HOB)","loc":"d,11:8,11:9","dtypep":"(AB)","funcName":"_dump_triggers__act","funcp":"(ZN)", "argsp": [ {"type":"VARREF","name":"__VactTriggered","addr":"(IOB)","loc":"d,11:8,11:9","dtypep":"(T)","access":"RD","varp":"(S)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"}, {"type":"CONST","name":"\\\"act\\\"","addr":"(JOB)","loc":"d,11:8,11:9","dtypep":"(PB)"} ]} ]}, {"type":"TEXT","name":"","addr":"(KOB)","loc":"d,11:8,11:9","text":"#endif"} ]}, {"type":"CSTMT","name":"","addr":"(LOB)","loc":"a,0:0,0:0", "nodesp": [ {"type":"TEXT","name":"","addr":"(MOB)","loc":"a,0:0,0:0","text":"VL_FATAL_MT(\"t/t_enum_type_methods.v\", 11, \"\", \"Active region did not converge after 100 tries\");"} ]} ],"elsesp": []}, {"type":"ASSIGN","name":"","addr":"(NOB)","loc":"d,11:8,11:9","dtypep":"(R)", "rhsp": [ {"type":"ADD","name":"","addr":"(OOB)","loc":"d,11:8,11:9","dtypep":"(R)", "lhsp": [ {"type":"CCAST","name":"","addr":"(POB)","loc":"d,11:8,11:9","dtypep":"(EC)","size":32, "lhsp": [ {"type":"CONST","name":"32'h1","addr":"(QOB)","loc":"d,11:8,11:9","dtypep":"(EC)"} ]} ], "rhsp": [ {"type":"VARREF","name":"__VactIterCount","addr":"(ROB)","loc":"d,11:8,11:9","dtypep":"(R)","access":"RD","varp":"(Q)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ], "lhsp": [ {"type":"VARREF","name":"__VactIterCount","addr":"(SOB)","loc":"d,11:8,11:9","dtypep":"(R)","access":"WR","varp":"(Q)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": []}, {"type":"LOOPTEST","name":"","addr":"(TOB)","loc":"a,0:0,0:0", "condp": [ {"type":"CCALL","name":"","addr":"(UOB)","loc":"a,0:0,0:0","dtypep":"(DB)","funcName":"_eval_phase__act","funcp":"(BLB)","argsp": []} ]} ],"contsp": []}, {"type":"LOOPTEST","name":"","addr":"(VOB)","loc":"a,0:0,0:0", "condp": [ {"type":"CCALL","name":"","addr":"(WOB)","loc":"a,0:0,0:0","dtypep":"(DB)","funcName":"_eval_phase__nba","funcp":"(IMB)","argsp": []} ]} ],"contsp": []} ]}, {"type":"CFUNC","name":"_eval_debug_assertions","addr":"(XOB)","loc":"d,11:8,11:9","slow":false,"isStatic":false,"dpiExportDispatcher":false,"dpiExportImpl":false,"dpiImportPrototype":false,"dpiImportWrapper":false,"dpiContext":false,"isConstructor":false,"isDestructor":false,"isVirtual":false,"isCoroutine":false,"needProcess":false,"scopep":"UNLINKED","argsp": [],"varsp": [], "stmtsp": [ {"type":"IF","name":"","addr":"(YOB)","loc":"d,15:10,15:13", "condp": [ {"type":"AND","name":"","addr":"(ZOB)","loc":"d,15:10,15:13","dtypep":"(K)", "lhsp": [ {"type":"VARREF","name":"clk","addr":"(APB)","loc":"d,15:10,15:13","dtypep":"(K)","access":"RD","varp":"(J)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "rhsp": [ {"type":"CONST","name":"8'hfe","addr":"(BPB)","loc":"d,15:10,15:13","dtypep":"(CPB)"} ]} ], "thensp": [ {"type":"CSTMT","name":"","addr":"(DPB)","loc":"d,15:10,15:13", "nodesp": [ {"type":"TEXT","name":"","addr":"(EPB)","loc":"d,15:10,15:13","text":"Verilated::overWidthError(\"clk\");"} ]} ],"elsesp": []} ]}, {"type":"CFUNC","name":"_ctor_var_reset","addr":"(FPB)","loc":"d,11:8,11:9","slow":true,"isStatic":false,"dpiExportDispatcher":false,"dpiExportImpl":false,"dpiImportPrototype":false,"dpiImportWrapper":false,"dpiContext":false,"isConstructor":false,"isDestructor":false,"isVirtual":false,"isCoroutine":false,"needProcess":false,"scopep":"UNLINKED","argsp": [],"varsp": [], "stmtsp": [ {"type":"CRESET","name":"","addr":"(GPB)","loc":"d,15:10,15:13","constructing":true, "varrefp": [ {"type":"VARREF","name":"clk","addr":"(HPB)","loc":"d,15:10,15:13","dtypep":"(K)","access":"WR","varp":"(J)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]}, {"type":"CRESET","name":"","addr":"(IPB)","loc":"d,23:17,23:20","constructing":true, "varrefp": [ {"type":"VARREF","name":"t.cyc","addr":"(JPB)","loc":"d,23:17,23:20","dtypep":"(P)","access":"WR","varp":"(O)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]}, {"type":"CRESET","name":"","addr":"(KPB)","loc":"d,24:9,24:10","constructing":true, "varrefp": [ {"type":"VARREF","name":"t.e","addr":"(LPB)","loc":"d,24:9,24:10","dtypep":"(M)","access":"WR","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]}, {"type":"CRESET","name":"","addr":"(MPB)","loc":"d,11:8,11:9","constructing":true, "varrefp": [ {"type":"VARREF","name":"__VactTriggered","addr":"(NPB)","loc":"d,11:8,11:9","dtypep":"(T)","access":"WR","varp":"(S)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]}, {"type":"CRESET","name":"","addr":"(OPB)","loc":"d,11:8,11:9","constructing":true, "varrefp": [ {"type":"VARREF","name":"__Vtrigprevexpr___TOP__clk__0","addr":"(PPB)","loc":"d,11:8,11:9","dtypep":"(K)","access":"WR","varp":"(N)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]}, {"type":"CRESET","name":"","addr":"(QPB)","loc":"d,11:8,11:9","constructing":true, "varrefp": [ {"type":"VARREF","name":"__VnbaTriggered","addr":"(RPB)","loc":"d,11:8,11:9","dtypep":"(T)","access":"WR","varp":"(U)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]}, {"type":"CUSE","name":"$unit","addr":"(SPB)","loc":"a,0:0,0:0","useType":"INT_FWD"} ]}, {"type":"PACKAGE","name":"$unit","addr":"(E)","loc":"a,0:0,0:0","origName":"__024unit","level":0,"modPublic":false,"inLibrary":true,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"__Venumtab_enum_next1","addr":"(AC)","loc":"d,17:12,17:16","dtypep":"(ZB)","origName":"__Venumtab_enum_next1","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":true,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATIC","varType":"MODULETEMP","dtypeName":"","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [], "valuep": [ {"type":"INITARRAY","name":"","addr":"(TPB)","loc":"d,17:12,17:16","dtypep":"(ZB)","initList":" [1]=(UPB) [3]=(VPB) [4]=(WPB)", "defaultp": [ {"type":"CONST","name":"4'h0","addr":"(XPB)","loc":"d,17:12,17:16","dtypep":"(RB)"} ], "initsp": [ {"type":"INITITEM","name":"","addr":"(UPB)","loc":"d,17:12,17:16", "valuep": [ {"type":"CONST","name":"4'h3","addr":"(YPB)","loc":"d,19:30,19:31","dtypep":"(RB)"} ]}, {"type":"INITITEM","name":"","addr":"(VPB)","loc":"d,17:12,17:16", "valuep": [ {"type":"CONST","name":"4'h4","addr":"(ZPB)","loc":"d,20:30,20:31","dtypep":"(RB)"} ]}, {"type":"INITITEM","name":"","addr":"(WPB)","loc":"d,17:12,17:16", "valuep": [ {"type":"CONST","name":"4'h1","addr":"(AQB)","loc":"d,18:30,18:31","dtypep":"(RB)"} ]} ]} ],"attrsp": []}, {"type":"VAR","name":"__Venumtab_enum_prev1","addr":"(UI)","loc":"d,17:12,17:16","dtypep":"(TI)","origName":"__Venumtab_enum_prev1","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":true,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATIC","varType":"MODULETEMP","dtypeName":"","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [], "valuep": [ {"type":"INITARRAY","name":"","addr":"(BQB)","loc":"d,17:12,17:16","dtypep":"(TI)","initList":" [1]=(CQB) [3]=(DQB) [4]=(EQB)", "defaultp": [ {"type":"CONST","name":"4'h0","addr":"(FQB)","loc":"d,17:12,17:16","dtypep":"(RB)"} ], "initsp": [ {"type":"INITITEM","name":"","addr":"(CQB)","loc":"d,17:12,17:16", "valuep": [ {"type":"CONST","name":"4'h4","addr":"(GQB)","loc":"d,20:30,20:31","dtypep":"(RB)"} ]}, {"type":"INITITEM","name":"","addr":"(DQB)","loc":"d,17:12,17:16", "valuep": [ {"type":"CONST","name":"4'h1","addr":"(HQB)","loc":"d,18:30,18:31","dtypep":"(RB)"} ]}, {"type":"INITITEM","name":"","addr":"(EQB)","loc":"d,17:12,17:16", "valuep": [ {"type":"CONST","name":"4'h3","addr":"(IQB)","loc":"d,19:30,19:31","dtypep":"(RB)"} ]} ]} ],"attrsp": []}, {"type":"VAR","name":"__Venumtab_enum_name1","addr":"(GM)","loc":"d,17:12,17:16","dtypep":"(FM)","origName":"__Venumtab_enum_name1","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":true,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATIC","varType":"MODULETEMP","dtypeName":"","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [], "valuep": [ {"type":"INITARRAY","name":"","addr":"(JQB)","loc":"d,17:12,17:16","dtypep":"(FM)","initList":" [1]=(KQB) [3]=(LQB) [4]=(MQB)", "defaultp": [ {"type":"CONST","name":"\\\"\\\"","addr":"(NQB)","loc":"d,17:12,17:16","dtypep":"(PB)"} ], "initsp": [ {"type":"INITITEM","name":"","addr":"(KQB)","loc":"d,17:12,17:16", "valuep": [ {"type":"CONST","name":"\\\"E01\\\"","addr":"(OQB)","loc":"d,17:12,17:16","dtypep":"(PB)"} ]}, {"type":"INITITEM","name":"","addr":"(LQB)","loc":"d,17:12,17:16", "valuep": [ {"type":"CONST","name":"\\\"E03\\\"","addr":"(PQB)","loc":"d,17:12,17:16","dtypep":"(PB)"} ]}, {"type":"INITITEM","name":"","addr":"(MQB)","loc":"d,17:12,17:16", "valuep": [ {"type":"CONST","name":"\\\"E04\\\"","addr":"(QQB)","loc":"d,17:12,17:16","dtypep":"(PB)"} ]} ]} ],"attrsp": []}, {"type":"SCOPE","name":"$unit","addr":"(RQB)","loc":"a,0:0,0:0","aboveScopep":"(W)","aboveCellp":"(V)","modp":"(E)","varsp": [],"blocksp": [],"inlinesp": []}, {"type":"CFUNC","name":"_ctor_var_reset","addr":"(SQB)","loc":"a,0:0,0:0","slow":true,"isStatic":false,"dpiExportDispatcher":false,"dpiExportImpl":false,"dpiImportPrototype":false,"dpiImportWrapper":false,"dpiContext":false,"isConstructor":false,"isDestructor":false,"isVirtual":false,"isCoroutine":false,"needProcess":false,"scopep":"UNLINKED","argsp": [],"varsp": [], "stmtsp": [ {"type":"CRESET","name":"","addr":"(TQB)","loc":"d,17:12,17:16","constructing":true, "varrefp": [ {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(UQB)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"WR","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]}, {"type":"CRESET","name":"","addr":"(VQB)","loc":"d,17:12,17:16","constructing":true, "varrefp": [ {"type":"VARREF","name":"__Venumtab_enum_prev1","addr":"(WQB)","loc":"d,17:12,17:16","dtypep":"(TI)","access":"WR","varp":"(UI)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]}, {"type":"CRESET","name":"","addr":"(XQB)","loc":"d,17:12,17:16","constructing":true, "varrefp": [ {"type":"VARREF","name":"__Venumtab_enum_name1","addr":"(YQB)","loc":"d,17:12,17:16","dtypep":"(FM)","access":"WR","varp":"(GM)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ], "filesp": [ {"type":"CFILE","name":"obj_vlt/t_json_only_debugcheck/Vt_json_only_debugcheck__Syms.cpp","addr":"(ZQB)","loc":"a,0:0,0:0","source":true,"slow":true,"tblockp": []}, {"type":"CFILE","name":"obj_vlt/t_json_only_debugcheck/Vt_json_only_debugcheck__Syms.h","addr":"(ARB)","loc":"a,0:0,0:0","source":false,"slow":true,"tblockp": []}, {"type":"CFILE","name":"obj_vlt/t_json_only_debugcheck/Vt_json_only_debugcheck.h","addr":"(BRB)","loc":"a,0:0,0:0","source":false,"slow":false,"tblockp": []}, {"type":"CFILE","name":"obj_vlt/t_json_only_debugcheck/Vt_json_only_debugcheck.cpp","addr":"(CRB)","loc":"a,0:0,0:0","source":true,"slow":false,"tblockp": []}, {"type":"CFILE","name":"obj_vlt/t_json_only_debugcheck/Vt_json_only_debugcheck_$root.h","addr":"(DRB)","loc":"a,0:0,0:0","source":false,"slow":false,"tblockp": []}, {"type":"CFILE","name":"obj_vlt/t_json_only_debugcheck/Vt_json_only_debugcheck_$unit.h","addr":"(ERB)","loc":"a,0:0,0:0","source":false,"slow":false,"tblockp": []}, {"type":"CFILE","name":"obj_vlt/t_json_only_debugcheck/Vt_json_only_debugcheck_$root__Slow.cpp","addr":"(FRB)","loc":"a,0:0,0:0","source":true,"slow":true,"tblockp": []}, {"type":"CFILE","name":"obj_vlt/t_json_only_debugcheck/Vt_json_only_debugcheck_$root__0__Slow.cpp","addr":"(GRB)","loc":"a,0:0,0:0","source":true,"slow":true,"tblockp": []}, {"type":"CFILE","name":"obj_vlt/t_json_only_debugcheck/Vt_json_only_debugcheck_$root__0.cpp","addr":"(HRB)","loc":"a,0:0,0:0","source":true,"slow":false,"tblockp": []}, {"type":"CFILE","name":"obj_vlt/t_json_only_debugcheck/Vt_json_only_debugcheck_$unit__Slow.cpp","addr":"(IRB)","loc":"a,0:0,0:0","source":true,"slow":true,"tblockp": []}, {"type":"CFILE","name":"obj_vlt/t_json_only_debugcheck/Vt_json_only_debugcheck_$unit__0__Slow.cpp","addr":"(JRB)","loc":"a,0:0,0:0","source":true,"slow":true,"tblockp": []} ], "miscsp": [ {"type":"TYPETABLE","name":"","addr":"(C)","loc":"a,0:0,0:0","constraintRefp":"UNLINKED","emptyQueuep":"UNLINKED","queueIndexp":"UNLINKED","streamp":"UNLINKED","voidp":"(AB)", "typesp": [ {"type":"BASICDTYPE","name":"logic","addr":"(K)","loc":"d,33:24,33:27","dtypep":"(K)","keyword":"logic","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(EC)","loc":"d,53:16,53:17","dtypep":"(EC)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(KRB)","loc":"d,17:17,17:18","dtypep":"(KRB)","keyword":"logic","range":"3:0","generic":true,"rangep": []}, {"type":"ENUMDTYPE","name":"t.my_t","addr":"(LRB)","loc":"d,17:12,17:16","dtypep":"(LRB)","enum":true,"generic":false,"refDTypep":"(KRB)","childDTypep": [], "itemsp": [ {"type":"ENUMITEM","name":"E01","addr":"(MRB)","loc":"d,18:24,18:27","dtypep":"(RB)","rangep": [], "valuep": [ {"type":"CONST","name":"4'h1","addr":"(NRB)","loc":"d,18:30,18:31","dtypep":"(RB)"} ]}, {"type":"ENUMITEM","name":"E03","addr":"(ORB)","loc":"d,19:24,19:27","dtypep":"(RB)","rangep": [], "valuep": [ {"type":"CONST","name":"4'h3","addr":"(PRB)","loc":"d,19:30,19:31","dtypep":"(RB)"} ]}, {"type":"ENUMITEM","name":"E04","addr":"(QRB)","loc":"d,20:24,20:27","dtypep":"(RB)","rangep": [], "valuep": [ {"type":"CONST","name":"4'h4","addr":"(RRB)","loc":"d,20:30,20:31","dtypep":"(RB)"} ]} ]}, {"type":"BASICDTYPE","name":"integer","addr":"(P)","loc":"d,23:4,23:11","dtypep":"(P)","keyword":"integer","range":"31:0","generic":true,"rangep": []}, {"type":"REFDTYPE","name":"my_t","addr":"(M)","loc":"d,24:4,24:8","dtypep":"(LRB)","generic":false,"typedefp":"UNLINKED","refDTypep":"(LRB)","classOrPackagep":"UNLINKED","typeofp": [],"classOrPackageOpp": [],"paramsp": []}, {"type":"BASICDTYPE","name":"string","addr":"(PB)","loc":"d,28:4,28:10","dtypep":"(PB)","keyword":"string","generic":true,"rangep": []}, {"type":"UNPACKARRAYDTYPE","name":"","addr":"(ZB)","loc":"d,17:12,17:16","dtypep":"(ZB)","isCompound":false,"declRange":"[7:0]","generic":false,"refDTypep":"(LRB)","childDTypep": [], "rangep": [ {"type":"RANGE","name":"","addr":"(SRB)","loc":"d,17:12,17:16","ascending":false,"fromBracket":false, "leftp": [ {"type":"CONST","name":"32'h7","addr":"(TRB)","loc":"d,17:12,17:16","dtypep":"(EC)"} ], "rightp": [ {"type":"CONST","name":"32'h0","addr":"(URB)","loc":"d,17:12,17:16","dtypep":"(EC)"} ]} ]}, {"type":"UNPACKARRAYDTYPE","name":"","addr":"(TI)","loc":"d,17:12,17:16","dtypep":"(TI)","isCompound":false,"declRange":"[7:0]","generic":false,"refDTypep":"(LRB)","childDTypep": [], "rangep": [ {"type":"RANGE","name":"","addr":"(VRB)","loc":"d,17:12,17:16","ascending":false,"fromBracket":false, "leftp": [ {"type":"CONST","name":"32'h7","addr":"(WRB)","loc":"d,17:12,17:16","dtypep":"(EC)"} ], "rightp": [ {"type":"CONST","name":"32'h0","addr":"(XRB)","loc":"d,17:12,17:16","dtypep":"(EC)"} ]} ]}, {"type":"UNPACKARRAYDTYPE","name":"","addr":"(FM)","loc":"d,17:12,17:16","dtypep":"(FM)","isCompound":true,"declRange":"[7:0]","generic":false,"refDTypep":"(PB)","childDTypep": [], "rangep": [ {"type":"RANGE","name":"","addr":"(YRB)","loc":"d,17:12,17:16","ascending":false,"fromBracket":false, "leftp": [ {"type":"CONST","name":"32'h7","addr":"(ZRB)","loc":"d,17:12,17:16","dtypep":"(EC)"} ], "rightp": [ {"type":"CONST","name":"32'h0","addr":"(ASB)","loc":"d,17:12,17:16","dtypep":"(EC)"} ]} ]}, {"type":"BASICDTYPE","name":"logic","addr":"(IB)","loc":"d,23:23,23:24","dtypep":"(IB)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, {"type":"VOIDDTYPE","name":"","addr":"(AB)","loc":"a,0:0,0:0","dtypep":"(AB)","generic":false}, {"type":"BASICDTYPE","name":"bit","addr":"(EN)","loc":"a,0:0,0:0","dtypep":"(EN)","keyword":"bit","range":"63:0","generic":true,"rangep": []}, {"type":"UNPACKARRAYDTYPE","name":"","addr":"(T)","loc":"d,11:8,11:9","dtypep":"(T)","isCompound":false,"declRange":"[0:0]","generic":false,"refDTypep":"(EN)","childDTypep": [], "rangep": [ {"type":"RANGE","name":"","addr":"(BSB)","loc":"d,11:8,11:9","ascending":false,"fromBracket":false, "leftp": [ {"type":"CONST","name":"32'h0","addr":"(CSB)","loc":"d,11:8,11:9","dtypep":"(EC)"} ], "rightp": [ {"type":"CONST","name":"32'h0","addr":"(DSB)","loc":"d,11:8,11:9","dtypep":"(EC)"} ]} ]}, {"type":"BASICDTYPE","name":"IData","addr":"(LP)","loc":"a,0:0,0:0","dtypep":"(LP)","keyword":"IData","range":"31:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(GN)","loc":"d,63:14,63:21","dtypep":"(GN)","keyword":"logic","range":"63:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"bit","addr":"(KMB)","loc":"d,11:8,11:9","dtypep":"(KMB)","keyword":"bit","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"bit","addr":"(R)","loc":"d,11:8,11:9","dtypep":"(R)","keyword":"bit","range":"31:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(DB)","loc":"d,63:22,63:25","dtypep":"(DB)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(RB)","loc":"d,32:11,32:14","dtypep":"(RB)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(CC)","loc":"d,38:15,38:16","dtypep":"(CC)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(CPB)","loc":"d,15:10,15:13","dtypep":"(CPB)","keyword":"logic","range":"7:0","generic":true,"rangep": []} ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ {"type":"MODULE","name":"@CONST-POOL@","addr":"(ESB)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], "stmtsp": [ {"type":"SCOPE","name":"TOP","addr":"(FSB)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(ESB)","varsp": [],"blocksp": [],"inlinesp": []} ]} ]} ]} verilator-5.042/test_regress/t/t_dpi_string_c.cpp0000644000542200017500000000214715101701376022565 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "svdpi.h" #include #include //====================================================================== // clang-format off #if defined(VERILATOR) # include "Vt_dpi_string__Dpi.h" #elif defined(VCS) # include "../vc_hdrs.h" #elif defined(CADENCE) # define NEED_EXTERNS #else # error "Unknown simulator for DPI test" #endif // clang-format on #ifdef NEED_EXTERNS extern "C" { extern int dpii_string(const char* s); } #endif //====================================================================== int dpii_string(const char* s) { printf("dpii_string: %s\n", s); return std::strlen(s); } verilator-5.042/test_regress/t/t_lint_literal_bad.py0000755000542200017500000000076315101701376023264 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_tri_pullup_pins_inout.py0000755000542200017500000000125515101701376024437 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_tri_pullup.cpp" test.top_filename = "t/t_tri_pullup.v" test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe --pins-inout-enables", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_var_dotted1_inl1.py0000755000542200017500000000104315101701376023123 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_var_dotted1.v" test.compile(v_flags2=['+define+USE_INLINE']) test.execute() test.passes() verilator-5.042/test_regress/t/t_case_group.py0000755000542200017500000000073415101701376022121 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_param_first.v0000644000542200017500000001236515101701376022116 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; reg _ranit; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [4:0] par1; // From a1 of t_param_first_a.v wire [4:0] par2; // From a2 of t_param_first_a.v wire [4:0] par3; // From a3 of t_param_first_a.v wire [4:0] par4; // From a4 of t_param_first_a.v wire [1:0] varwidth1; // From a1 of t_param_first_a.v wire [2:0] varwidth2; // From a2 of t_param_first_a.v wire [3:0] varwidth3; // From a3 of t_param_first_a.v wire [3:0] varwidth4; // From a4 of t_param_first_a.v // End of automatics /*t_param_first_a AUTO_TEMPLATE ( .par (par@[])); .varwidth (varwidth@[])); */ parameter XX = 2'bXX; parameter THREE = 3; t_param_first_a #(1,5) a1 ( // Outputs .varwidth (varwidth1[1:0]), /*AUTOINST*/ // Outputs .par (par1[4:0])); // Templated t_param_first_a #(2,5) a2 ( // Outputs .varwidth (varwidth2[2:0]), /*AUTOINST*/ // Outputs .par (par2[4:0])); // Templated t_param_first_a #(THREE,5) a3 ( // Outputs .varwidth (varwidth3[3:0]), /*AUTOINST*/ // Outputs .par (par3[4:0])); // Templated t_param_first_a #(THREE,5) a4 ( // Outputs .varwidth (varwidth4[3:0]), /*AUTOINST*/ // Outputs .par (par4[4:0])); // Templated parameter THREE_BITS_WIDE = 3'b011; parameter THREE_2WIDE = 2'b11; parameter ALSO_THREE_WIDE = THREE_BITS_WIDE; parameter THREEPP_32_WIDE = 2*8*2+3; parameter THREEPP_3_WIDE = 3'd4*3'd4*3'd2+3'd3; // Yes folks VCS says 3 bits wide // Width propagation doesn't care about LHS vs RHS // But the width of a RHS/LHS on a upper node does affect lower nodes; // Thus must double-descend in width analysis. // VCS 7.0.1 is broken on this test! parameter T10 = (3'h7+3'h7)+4'h0; //initial if (T10!==4'd14) $stop; parameter T11 = 4'h0+(3'h7+3'h7); //initial if (T11!==4'd14) $stop; // Parameters assign LHS is affectively width zero. parameter T12 = THREE_2WIDE + THREE_2WIDE; initial if (T12!==2'd2) $stop; parameter T13 = THREE_2WIDE + 3; initial if (T13!==32'd6) $stop; // Must be careful about LSB's with extracts parameter [39:8] T14 = 32'h00_1234_56; initial if (T14[24:16]!==9'h34) $stop; // parameter THREEPP_32P_WIDE = 3'd4*3'd4*2+3'd3; parameter THREE_32_WIDE = 3%32; parameter THIRTYTWO = 2; // Param is 32 bits parameter [40:0] WIDEPARAM = 41'h12_3456789a; parameter [40:0] WIDEPARAM2 = WIDEPARAM; reg [7:0] eightb; reg [3:0] fourb; wire [7:0] eight = 8'b00010000; wire [1:0] eight2two = eight[THREE_32_WIDE+1:THREE_32_WIDE]; wire [2:0] threebits = ALSO_THREE_WIDE; // surefire lint_off CWCCXX initial _ranit = 0; always @ (posedge clk) begin if (!_ranit) begin _ranit <= 1; $write("[%0t] t_param: Running\n", $time); // $write(" %d %d %d\n", par1,par2,par3); if (par1!==5'd1) $stop; if (par2!==5'd2) $stop; if (par3!==5'd3) $stop; if (par4!==5'd3) $stop; if (varwidth1!==2'd2) $stop; if (varwidth2!==3'd2) $stop; if (varwidth3!==4'd2) $stop; if (varwidth4!==4'd2) $stop; if (threebits !== 3'b011) $stop; if (eight !== 8'b00010000) $stop; if (eight2two !== 2'b10) $stop; $write(" Params = %b %b\n %b %b\n", THREEPP_32_WIDE,THREEPP_3_WIDE, THIRTYTWO, THREEPP_32P_WIDE); if (THREEPP_32_WIDE !== 32'h23) $stop; if (THREEPP_3_WIDE !== 3'h3) $stop; if (THREEPP_32P_WIDE !== 32'h23) $stop; if (THIRTYTWO[1:0] !== 2'h2) $stop; if (THIRTYTWO !== 32'h2) $stop; if (THIRTYTWO !== 2) $stop; if ((THIRTYTWO[1:0]+2'b00) !== 2'b10) $stop; if ({1'b1,{THIRTYTWO[1:0]+2'b00}} !== 3'b110) $stop; if (XX===0 || XX===1 || XX===2 || XX===3) $stop; // Paradoxical but right, since 1'bx!=0 && !=1 // // Example of assignment LHS affecting expression widths. // verilator lint_off WIDTH // surefire lint_off ASWCMB // surefire lint_off ASWCBB eightb = (4'd8+4'd8)/4'd4; if (eightb!==8'd4) $stop; fourb = (4'd8+4'd8)/4'd4; if (fourb!==4'd0) $stop; fourb = (4'd8+8)/4'd4; if (fourb!==4'd4) $stop; // verilator lint_on WIDTH // surefire lint_on ASWCMB // surefire lint_on ASWCBB // $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_math_repl2_bad.out0000644000542200017500000000162215101701376023006 0ustar mahmoudyfreeshell%Error: t/t_math_repl2_bad.v:28:30: Replication value of < 0 or X/Z not legal (IEEE 1800-2023 11.4.12.1): '32'hfffffffb' : ... note: In instance 't' 28 | out <= {{(P24 - P29){1'b0}}, in}; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Warning-WIDTHTRUNC: t/t_math_repl2_bad.v:28:14: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS's REPLICATE generates 30 bits. : ... note: In instance 't' 28 | out <= {{(P24 - P29){1'b0}}, in}; | ^~ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_type_param.v0000644000542200017500000001021715101701376021742 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 package some_package; typedef logic [15:0] two_bytes_t; endpackage module foo #(parameter type bar = logic) (output int bar_size); localparam baz = $bits(bar); assign bar_size = baz; endmodule module foo_wrapper #(parameter bar_bits = 9) (output int bar_size); foo #(.bar (logic[bar_bits-1:0])) foo_inst (.bar_size (bar_size)); endmodule module t(); logic [7:0] qux1; int bar_size1; foo #(.bar (logic [ $bits(qux1) - 1 : 0])) foo_inst1 (.bar_size (bar_size1)); logic [7:0] qux2; int bar_size2; foo #(.bar (logic [ $bits(qux2) - 1 : 0])) foo_inst2 (.bar_size (bar_size2)); logic [7:0] qux3; int bar_size3; foo #(.bar (logic [ $bits(qux3) - 1 : 0])) foo_inst3 (.bar_size (bar_size3)); typedef struct packed { logic foo; logic bar; } some_struct_t; int bar_size4; foo #(.bar (some_struct_t [7:0])) foo_inst4 (.bar_size (bar_size4)); int bar_size5; foo #(.bar (some_struct_t [2:0] [5:0])) foo_inst5 (.bar_size (bar_size5)); int bar_size6; foo #(.bar (some_package::two_bytes_t [4-1:0])) foo_inst6 (.bar_size (bar_size6)); localparam bar_bits = 13; int bar_size_wrapper; foo_wrapper #(.bar_bits (bar_bits)) foo_wrapper_inst (.bar_size (bar_size_wrapper)); initial begin if ($bits(qux1) != foo_inst1.baz) begin $display("%m: bits of qux1 != bits of foo_inst1.baz (%0d, %0d)", $bits(qux1), foo_inst1.baz); $stop(); end if ($bits(qux2) != foo_inst2.baz) begin $display("%m: bits of qux2 != bits of foo_inst2.baz (%0d, %0d)", $bits(qux2), foo_inst2.baz); $stop(); end if ($bits(qux3) != foo_inst3.baz) begin $display("%m: bits of qux3 != bits of foo_inst3.baz (%0d, %0d)", $bits(qux3), foo_inst3.baz); $stop(); end if (bar_bits != foo_wrapper_inst.foo_inst.baz) begin $display("%m: bar_bits != bits of foo_wrapper_inst.foo_inst.baz (%0d, %0d)", bar_bits, foo_wrapper_inst.foo_inst.baz); $stop(); end if (bar_size1 != $bits(qux1)) begin $display("%m: bar_size1 != bits of qux1 (%0d, %0d)", bar_size1, $bits(qux1)); $stop(); end if (bar_size2 != $bits(qux2)) begin $display("%m: bar_size2 != bits of qux2 (%0d, %0d)", bar_size2, $bits(qux2)); $stop(); end if (bar_size3 != $bits(qux3)) begin $display("%m: bar_size3 != bits of qux3 (%0d, %0d)", bar_size3, $bits(qux3)); $stop(); end if (bar_size4 != $bits(some_struct_t)*8) begin $display("%m: bar_size4 != bits of some_struct_t * 8 (%0d, %0d)", bar_size4, $bits(some_struct_t) * 8); $stop(); end if (bar_size5 != $bits(some_struct_t)*3*6) begin $display("%m: bar_size5 != bits of some_struct_t * 3 * 6 (%0d, %0d)", bar_size5, $bits(some_struct_t) * 3 * 6); $stop(); end if (bar_size6 != $bits(some_package::two_bytes_t)*4) begin $display("%m: bar_size6 != bits of some_package::two_bytes_t * 4 (%0d, %0d)", bar_size6, $bits(some_package::two_bytes_t) * 4); $stop(); end if (bar_size_wrapper != bar_bits) begin $display("%m: bar_size_wrapper != bar_bits (%0d, %0d)", bar_size_wrapper, bar_bits); $stop(); end end genvar m; generate for (m = 1; m <= 8; m+=1) begin : gen_m initial begin if (m != foo_inst.baz) begin $display("%m: m != bits of foo_inst.baz (%0d, %0d)", m, foo_inst.baz); $stop(); end end foo #(.bar (logic[m-1:0])) foo_inst (.bar_size ()); end endgenerate initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_implements_collision.v0000644000542200017500000000131715101701376024032 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface class Icls1; pure virtual function int icfboth; endclass interface class Icls2; pure virtual function int icfboth; endclass interface class IclsBoth extends Icls1, Icls2; pure virtual function int icfboth; endclass class Cls implements IclsBoth; virtual function int icfboth; return 3; endfunction endclass module t; Cls c; initial begin c = new; if (c.icfboth() != 3) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_array_list_bad.py0000755000542200017500000000076615101701376022756 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_pp_recursedef_bad.out0000644000542200017500000000031515101701376023575 0ustar mahmoudyfreeshell%Error: t/t_pp_recursedef_bad.v:9:8012: Recursive `define substitution: `RECURSE ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_trace_complex_fst_threads_1_sc.py0000755000542200017500000000135615101701376026113 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_complex.v" test.golden_filename = "t/t_trace_complex_fst_sc.out" if not test.have_sc: test.skip("No SystemC installed") test.compile(verilator_flags2=['--sc --trace-fst --trace-threads 1']) test.execute() test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_clocking_bad5.out0000644000542200017500000000243315101701376022630 0ustar mahmoudyfreeshell%Error: t/t_clocking_bad5.v:29:20: Duplicate declaration of CLOCKING 'ck': '$global_clock' 29 | global clocking ogck @(posedge clk); endclocking | ^~~~ t/t_clocking_bad5.v:26:20: ... Location of original declaration 26 | global clocking ck @(posedge clk); endclocking | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_clocking_bad5.v:32:20: Duplicate declaration of CLOCKING 'ogck': '$global_clock' 32 | global clocking ck @(posedge clk); endclocking | ^~ t/t_clocking_bad5.v:29:20: ... Location of original declaration 29 | global clocking ogck @(posedge clk); endclocking | ^~~~ %Error: t/t_clocking_bad5.v:32:20: Duplicate declaration of CLOCKING 'ck': 'ck' 32 | global clocking ck @(posedge clk); endclocking | ^~ t/t_clocking_bad5.v:26:20: ... Location of original declaration 26 | global clocking ck @(posedge clk); endclocking | ^~ %Error: t/t_clocking_bad5.v:16:14: Can't find definition of variable: '$global_clock' 16 | always @ ($global_clock) $display; | ^~~~~~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_param_implicit_bad.out0000644000542200017500000000216515101701376023746 0ustar mahmoudyfreeshell%Error: t/t_param_implicit_bad.v:9:15: parameter port declarations require 'parameter' keyword before implicit data types (IEEE 1800-2023 6.20.1/A.2.1.1) : ... Suggest add 'parameter' before here 9 | module sub1 #([7:0] PAR1 = 1); | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_param_implicit_bad.v:12:42: parameter port declarations require 'parameter' keyword before implicit data types (IEEE 1800-2023 6.20.1/A.2.1.1) : ... Suggest add 'parameter' before here 12 | module sub2 #(parameter real PAR1 = 1.0, signed PAR2 = 2); | ^~~~~~ %Error: t/t_param_implicit_bad.v:15:43: parameter port declarations require 'parameter' keyword before implicit data types (IEEE 1800-2023 6.20.1/A.2.1.1) : ... Suggest add 'parameter' before here 15 | module sub3 #(localparam real PAR1 = 1.0, signed PAR2 = 2); | ^~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_lint_iface_topmodule2.v0000644000542200017500000000134415101701376024051 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Josh Redford. // SPDX-License-Identifier: CC0-1.0 interface my_if #( parameter integer DW = 8 ) (); logic valid; logic [DW-1:0] data; modport slave_mp ( input valid, input data ); modport master_mp ( output valid, output data ); endinterface module t ( input wire clk, my_if.slave_mp in_if, my_if.master_mp out_if ); assign out_if.valid = in_if.valid; assign out_if.data = in_if.data; endmodule verilator-5.042/test_regress/t/t_queue_var_slice.py0000755000542200017500000000073415101701376023145 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_param_noinit.v0000644000542200017500000000066115101701376023450 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // No init value is legal with classes, as long as not used without the parameter class Cls #(int A, int B); endclass module t; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_lint_noreturn_param_bad.out0000644000542200017500000000150715101701376025035 0ustar mahmoudyfreeshell%Warning-NORETURN: t/t_lint_noreturn_param_bad.v:14:20: Non-void function 'no_rtn' has no return value : ... note: In instance 't' 14 | function integer no_rtn(); | ^~~~~~ ... For warning description see https://verilator.org/warn/NORETURN?v=latest ... Use "/* verilator lint_off NORETURN */" and lint_on around source to disable this message. %Error: t/t_lint_noreturn_param_bad.v:19:16: left side of bit range isn't a two-state constant (IEEE 1800-2023 6.9.1) : ... note: In instance 't' 19 | output [WIDTH-1:0] o; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_flag_debugi9.py0000755000542200017500000000115315101701376022307 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(v_flags2=["--debug --debugi 9"], tee=False, verilator_make_gmake=False, make_top_shell=False, make_main=False) test.passes() verilator-5.042/test_regress/t/t_tri_pull2_bad.py0000755000542200017500000000077615101701376022522 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_hier_block_type_param_notfound_bad.out0000644000542200017500000000121715101701376027207 0ustar mahmoudyfreeshell%Error: Cannot open file containing hierarchical parameter declarations: '/does-not-exist' ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. ... Looked in: t//does-not-exist t//does-not-exist.v t//does-not-exist.sv /does-not-exist /does-not-exist.v /does-not-exist.sv obj_vlt/t_hier_block_type_param_notfound_bad//does-not-exist obj_vlt/t_hier_block_type_param_notfound_bad//does-not-exist.v obj_vlt/t_hier_block_type_param_notfound_bad//does-not-exist.sv %Error: Exiting due to verilator-5.042/test_regress/t/t_tri_array.out0000644000542200017500000000110315101701376022131 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_tri_array.v:25:25: Unsupported LHS tristate construct: ARRAYSEL : ... note: In instance 't' 25 | Pad pad1 (.pad(pad[g]), | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_tri_array.v:28:25: Unsupported LHS tristate construct: ARRAYSEL : ... note: In instance 't' 28 | Pad pad0 (.pad(pad[g]), | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_threads_counter_0.py0000755000542200017500000000105415101701376023376 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_threads_counter.v" test.compile(verilator_flags2=['--cc'], threads=1) test.execute() test.passes() verilator-5.042/test_regress/t/t_timing_fork_taskcall.py0000755000542200017500000000077115101701376024161 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_queue_empty_bad.py0000755000542200017500000000076315101701376023144 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_display_merge.v0000644000542200017500000000532615101701376022432 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; int one = `ifdef verilator $c32(1) `else 1 `endif ; initial begin $display("Merge:"); $write("This "); $write("should "); $display("merge"); $display("Merge:"); $write("This ", "", "should ", "", "also "); $display("merge"); $display("f"); $write(" 1=%0d a=%m 1=%0d", one, one); $display(" 1=%0d b=%m 1=%0d", one, one); $display(" pre"); $display(" t=%0d", $time); $display(" t2=%0d", $time); $display(" post"); $display(" t3=%0d", $time); $display(" t4=%0d t5=%0d", $time,$time,$time); $display("m"); $display(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d", $time,$time,$time,$time,$time); $display(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d", $time,$time,$time,$time,$time); $display("mm"); $display(""); $write("f"); $write(" a=%m"); $write(" b=%m"); $write(" pre"); $write(" t=%0d", $time); $write(" t2=%0d", $time); $write(" post"); $write(" t3=%0d", $time); $write(" t4=%0d t5=%0d", $time,$time,$time); $write("m"); $write(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d", $time,$time,$time,$time,$time); $write(" t=%0d t2=%0d t3=%0d t4=%0d t5=%0d", $time,$time,$time,$time,$time); $display("mm"); $display("very very very very very very very very very very very very very very very very very very very very very very"); $display("very very very very very very very very very very very very very very very very very very very very very very"); $display("very very very very very very very very very very very very very very very very very very very very very very"); $display("very very very very very very very very very very very very very very very very very very very very very very"); $display("very very very very very very very very very very very very very very very very very very very very very very"); $display("very very very very very very very very very very very very very very very very very very very very very very"); $display("very very very very very very very very very very very very very very very very very very very very very very"); $display("%0d%0d%0d%0d%0d %0d%0d%0d%0d%0d", one, one, one, one, one, one, one, one, one, one); $display("%0d%0d%0d%0d%0d %0d%0d%0d%0d%0d", one, one, one, one, one, one, one, one, one, one); $write("\n*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_dedupe_seq_logic.py0000755000542200017500000000111115101701376023253 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--stats"]) if test.vlt_all: test.file_grep(test.stats, r'Optimizations, Gate sigs deduped\s+(\d+)', 6) test.passes() verilator-5.042/test_regress/t/t_randomize_param_with.v0000644000542200017500000000247715101701376024015 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `define check_rand(cl, field, constr, cond) \ begin \ longint prev_result; \ int ok = 0; \ if (!bit'(cl.randomize() with { constr; })) $stop; \ prev_result = longint'(field); \ if (!(cond)) $stop; \ repeat(9) begin \ longint result; \ if (!bit'(cl.randomize() with { constr; })) $stop; \ result = longint'(field); \ if (!(cond)) $stop; \ if (result != prev_result) ok = 1; \ prev_result = result; \ end \ if (ok != 1) $stop; \ end class Cls #(int LIMIT = 3); rand int x; int y = -100; constraint x_limit { x <= LIMIT; }; endclass module t; initial begin Cls#() cd = new; Cls#(5) c5 = new; `check_rand(cd, cd.x, x > 0, cd.x > 0 && cd.x <= 3); `check_rand(cd, cd.x, x > y, cd.x > -100 && cd.x <= 3); if (cd.randomize() with {x > 3;} == 1) $stop; `check_rand(c5, c5.x, x > 0, c5.x > 0 && c5.x <= 5); `check_rand(c5, c5.x, x > y, c5.x > -100 && c5.x <= 5); if (c5.randomize() with {x >= 5;} == 0) $stop; if (c5.x != 5) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_func_rand.v0000644000542200017500000000142515101701376021541 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk, Rand); input clk; output reg [31:0] Rand; `ifdef verilator `systemc_interface unsigned int QxRandTbl (unsigned int tbl, unsigned int idx) { return 0xfeed0fad; } `verilog `endif function [31:0] QxRand32; /* verilator public */ input [7:0] tbl; input [7:0] idx; begin `ifdef verilator QxRand32 = $c("this->QxRandTbl(", tbl, ",", idx, ")"); `else QxRand32 = 32'hfeed0fad; `endif end endfunction always @(posedge clk) begin Rand <= #1 QxRand32 (8'h0, 8'h7); end endmodule verilator-5.042/test_regress/t/t_lint_pkg_colon_bad.v0000644000542200017500000000043315101701376023407 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (input mispkg::foo_t a); reg mispkgb::bar_t b; endmodule verilator-5.042/test_regress/t/t_opt_dead.py0000755000542200017500000000127115101701376021546 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() # bug2227, Verilator unsupported, class dead # This is what we really want: # test.file_grep_not(test.obj_dir + "/V"+test.name+"__Syms.h", r'dead') test.file_grep(test.obj_dir + "/V" + test.name + "__Syms.h", r'dead') test.passes() verilator-5.042/test_regress/t/t_eq_wild.py0000755000542200017500000000073415101701376021416 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_param_nconst_bad.py0000755000542200017500000000076615101701376024456 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_randomize_inline_var_ctl_unsup_2.py0000755000542200017500000000100115101701376026471 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_pkg_colon_bad.py0000755000542200017500000000076615101701376023606 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_comb_input_0.cpp0000644000542200017500000000233715101701376022500 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2022 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "verilated.h" #include "Vt_comb_input_0.h" #include "Vt_comb_input_0__Syms.h" #include int main(int argc, char** argv) { const std::unique_ptr contextp{new VerilatedContext}; contextp->debug(0); contextp->commandArgs(argc, argv); srand48(5); const std::unique_ptr topp{new VM_PREFIX}; topp->inc = 1; topp->clk = false; topp->eval(); while (!contextp->gotFinish() && contextp->time() < 100000) { contextp->timeInc(5); if (topp->clk) topp->inc += 1; topp->clk = !topp->clk; topp->eval(); } if (!contextp->gotFinish()) { vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); } return 0; } verilator-5.042/test_regress/t/t_var_pins_sc_uint.py0000755000542200017500000000343215101701376023335 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.pli_filename = "t/t_var_pinsizes.cpp" test.top_filename = "t/t_var_pinsizes.v" test.compile(verilator_flags2=["-sc --pins-sc-uint --trace-vcd --exe", test.pli_filename], make_main=False) def hgrep(re): test.file_grep(os.path.join(test.obj_dir, test.vm_prefix + ".h"), re) hgrep(r'sc_core::sc_in\s+&i1;') hgrep(r'sc_core::sc_in\s>\s+&i8;') hgrep(r'sc_core::sc_in\s>\s+&i16;') hgrep(r'sc_core::sc_in\s>\s+&i32;') hgrep(r'sc_core::sc_in\s>\s+&i64;') hgrep(r'sc_core::sc_in\s>\s+&i65;') hgrep(r'sc_core::sc_in\s>\s+&i128;') hgrep(r'sc_core::sc_in\s>\s+&i513;') hgrep(r'sc_core::sc_in\s>\s+&ibv1;') hgrep(r'sc_core::sc_in\s>\s+&ibv16;') hgrep(r'sc_core::sc_out\s+&o1;') hgrep(r'sc_core::sc_out\s>\s+&o8;') hgrep(r'sc_core::sc_out\s>\s+&o16;') hgrep(r'sc_core::sc_out\s>\s+&o32;') hgrep(r'sc_core::sc_out\s>\s+&o64;') hgrep(r'sc_core::sc_out\s>\s+&o65;') hgrep(r'sc_core::sc_out\s>\s+&o128;') hgrep(r'sc_core::sc_out\s>\s+&o513;') hgrep(r'sc_core::sc_out\s>\s+&obv1;') hgrep(r'sc_core::sc_out\s>\s+&obv16;') test.execute() test.passes() verilator-5.042/test_regress/t/t_disable_empty_outside.v0000644000542200017500000000115215101701376024154 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t; initial begin begin : blk int x = 0; fork : fork_blk begin end begin x = 1; #2; x = 2; end join_none #1; disable fork_blk; #2; if (x != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_process_fork.out0000644000542200017500000000023015101701376022634 0ustar mahmoudyfreeshelljob started job started job started job started job started job started job started job started all jobs started all jobs finished *-* All Finished *-* verilator-5.042/test_regress/t/t_event_control_star_never_bad.out0000644000542200017500000000110315101701376026054 0ustar mahmoudyfreeshell%Warning-ALWNEVER: t/t_event_control_star_never.v:9:3: 'always @*' will never execute as expression list is empty (no variables read) : ... note: In instance 't' : ... Suggest use 'always_comb' 9 | always @* a = 100; | ^~~~~~ ... For warning description see https://verilator.org/warn/ALWNEVER?v=latest ... Use "/* verilator lint_off ALWNEVER */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_scheduling_2.py0000755000542200017500000000073415101701376022340 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_dpi_argtype_bad.py0000755000542200017500000000077615101701376023115 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_constraint_soft_randc_bad.v0000644000542200017500000000052115101701376024772 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls1; randc int rc; constraint c_bad { soft rc > 4; } // Bad, no soft on randc endclass module t; endmodule verilator-5.042/test_regress/t/t_udp_bad_line_inputs.out0000644000542200017500000000040315101701376024146 0ustar mahmoudyfreeshell%Error: t/t_udp_bad_line_inputs.v:9:5: Incorrect number of input values, expected 1, got 5 9 | ? 1 ? 0 0 : 0; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_lint_importstar_bad.py0000755000542200017500000000110115101701376024017 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_threads_counter_4.py0000755000542200017500000000105015101701376023376 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vltmt') test.top_filename = "t/t_threads_counter.v" test.compile(verilator_flags2=['--cc'], threads=4) test.execute() test.passes() verilator-5.042/test_regress/t/t_func_dotted_inl1_vlt.py0000755000542200017500000000143615101701376024100 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_func_dotted.v" out_filename = test.obj_dir + "/V" + test.name + ".tree.json" test.compile(v_flags2=["--no-json-edit-nums", "t/t_func_dotted_inl1.vlt"]) if test.vlt_all: test.file_grep_not(out_filename, r'"ma0"') test.file_grep_not(out_filename, r'"mb0"') test.file_grep_not(out_filename, r'"mc0"') test.execute() test.passes() verilator-5.042/test_regress/t/t_enum_bad_circdecl.v0000644000542200017500000000047315101701376023206 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; typedef enum bad_redecl; typedef enum bad_redecl [2:0] {VALUE} bad_redecl; endmodule verilator-5.042/test_regress/t/t_func_begin2.py0000755000542200017500000000076615101701376022160 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["--lint-only --inline-mult 1"]) test.passes() verilator-5.042/test_regress/t/t_sys_writemem.gold8.mem0000644000542200017500000000005215101701376023651 0ustar mahmoudyfreeshell02 03 04 05 06 07 10 00 00 00 14 15 00 00 verilator-5.042/test_regress/t/t_enum_func.v0000644000542200017500000000304515101701376021561 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef enum { EN_ZERO, EN_ONE } En_t; module t (/*AUTOARG*/ // Inputs clk ); input clk; // Insure that we can declare a type with a function declaration function enum integer { EF_TRUE = 1, EF_FALSE = 0 } f_enum_inv ( input a); f_enum_inv = a ? EF_FALSE : EF_TRUE; endfunction initial begin if (f_enum_inv(1) != 0) $stop; if (f_enum_inv(0) != 1) $stop; end En_t a, z; sub sub (/*AUTOINST*/ // Outputs .z (z), // Inputs .a (a)); integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin a <= EN_ZERO; end if (cyc==2) begin a <= EN_ONE; if (z != EN_ONE) $stop; end if (cyc==3) begin if (z != EN_ZERO) $stop; end if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module sub (input En_t a, output En_t z); always @* z = (a==EN_ONE) ? EN_ZERO : EN_ONE; endmodule // Local Variables: // verilog-typedef-regexp: "_t$" // End: verilator-5.042/test_regress/t/t_timing_trace.out0000644000542200017500000000123115101701376022604 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module t $end $var wire 32 * CLK_PERIOD [31:0] $end $var wire 32 + CLK_HALF_PERIOD [31:0] $end $var wire 1 # rst $end $var wire 1 ( clk $end $var wire 1 $ a $end $var wire 1 ) b $end $var wire 1 % c $end $var wire 1 & d $end $var event 1 ' ev $end $upscope $end $enddefinitions $end #0 1# 0$ 1% 0& 1' 0( 1) b00000000000000000000000000001010 * b00000000000000000000000000000101 + #5 1( #10 0% 1' 0( #15 1( #20 1% 1' 0( #25 1( #30 0% 1' 0( #35 1( #40 1% 1' 0( #45 1( #50 0% 1' 0( #55 1( #60 1% 1' 0( #65 1( #70 0% 1' 0( #75 1( #80 1% 1' 0( #85 1( #90 0% 1' 0( #95 1( #100 0( 0) verilator-5.042/test_regress/t/t_inst_slice.py0000755000542200017500000000073415101701376022126 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_flag_make_cmake.v0000644000542200017500000000057515101701376022655 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; always @ (posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_lib_prot_delay_bad.out0000644000542200017500000000030015101701376023731 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: Unsupported: --lib-create with --timing and delays ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_flag_build_jobs_and_j.py0000755000542200017500000000123415101701376024226 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_flag_make_cmake.v" test.compile(verilator_flags2=[ '--exe --cc --build -j 10 --build-jobs 2 --stats', '../' + test.main_filename ]) test.execute() test.file_grep(test.stats, r'Build jobs: 2') test.passes() verilator-5.042/test_regress/t/t_trace_two_port_sc.out0000644000542200017500000000364315101701376023670 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module topa $end $scope module t $end $var wire 1 # clk $end $var wire 32 $ cyc [31:0] $end $var wire 32 % c_trace_on [31:0] $end $scope module sub $end $var wire 32 & inside_sub_a [31:0] $end $upscope $end $upscope $end $upscope $end $scope module topb $end $scope module t $end $var wire 1 ( clk $end $var wire 32 + cyc [31:0] $end $var wire 32 , c_trace_on [31:0] $end $var real 64 ) r $end $scope module sub $end $var wire 32 - inside_sub_a [31:0] $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 0# b00000000000000000000000000000001 $ b00000000000000000000000000000000 % 0( r0 ) b00000000000000000000000000000001 & b00000000000000000000000000000001 + b00000000000000000000000000000000 , b00000000000000000000000000000010 - #10000 1# b00000000000000000000000000000010 $ b00000000000000000000000000000011 % 1( r0.1 ) #15000 0# 0( #20000 1# b00000000000000000000000000000011 $ b00000000000000000000000000000100 % 1( r0.2 ) #25000 0# 0( #30000 1# b00000000000000000000000000000100 $ b00000000000000000000000000000101 % 1( r0.3 ) #35000 0# 0( #40000 1# b00000000000000000000000000000101 $ b00000000000000000000000000000110 % 1( r0.4 ) #45000 0# 0( #50000 1# b00000000000000000000000000000110 $ b00000000000000000000000000000111 % 1( r0.5 ) #55000 0# 0( #60000 1# b00000000000000000000000000000111 $ b00000000000000000000000000001000 % 1( r0.6 ) #65000 0# 0( #70000 1# b00000000000000000000000000001000 $ b00000000000000000000000000001001 % 1( r0.7 ) #75000 0# 0( #80000 1# b00000000000000000000000000001001 $ b00000000000000000000000000001010 % 1( r0.7999999999999999 ) #85000 0# 0( #90000 1# b00000000000000000000000000001010 $ b00000000000000000000000000001011 % 1( r0.8999999999999999 ) #95000 0# 0( #100000 1# b00000000000000000000000000001011 $ b00000000000000000000000000001100 % 1( r0.9999999999999999 ) verilator-5.042/test_regress/t/t_param_type_bad2.out0000644000542200017500000000116015101701376023171 0ustar mahmoudyfreeshell%Error: t/t_param_type_bad2.v:8:19: Operator VAR 't' expected non-datatype Initial value but 'logic' is a datatype. : ... note: In instance 't' 8 | localparam t = logic; | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_param_type_bad2.v:9:20: Operator VAR 't2' expected non-datatype Initial value but 'real' is a datatype. : ... note: In instance 't' 9 | localparam t2 = realtime; | ^~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_dfg_inline_forced.py0000755000542200017500000000070615101701376023411 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.passes() verilator-5.042/test_regress/t/t_package_dot.py0000755000542200017500000000073415101701376022233 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_star.v0000644000542200017500000000146015101701376022572 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=1; counter_io c_data(); counter_ansi c1 (.clk, .*); counter_ansi c2 (.clk, .c_data); always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==20) begin if (c_data.value != 12345) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule interface counter_io; integer value; endinterface module counter_ansi ( input clk, counter_io c_data ); always_ff @ (posedge clk) begin c_data.value <= 12345; end endmodule : counter_ansi verilator-5.042/test_regress/t/t_trace_scope_vlt.out0000644000542200017500000000740415101701376023323 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $var wire 1 ) clk $end $scope module t $end $var wire 1 ) clk $end $scope module sub1a $end $var wire 32 * ADD [31:0] $end $var wire 32 # cyc [31:0] $end $var wire 32 $ value [31:0] $end $upscope $end $scope module sub1b $end $var wire 32 + ADD [31:0] $end $var wire 32 # cyc [31:0] $end $var wire 32 % value [31:0] $end $scope module sub2a $end $var wire 32 # cyc [31:0] $end $var wire 32 & value [31:0] $end $upscope $end $scope module sub2b $end $var wire 32 , ADD [31:0] $end $var wire 32 # cyc [31:0] $end $var wire 32 ' value [31:0] $end $upscope $end $scope module sub2c $end $var wire 32 - ADD [31:0] $end $var wire 32 # cyc [31:0] $end $var wire 32 ( value [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 b00000000000000000000000000000000 # b00000000000000000000000000001010 $ b00000000000000000000000000010100 % b00000000000000000000000000010101 & b00000000000000000000000000010110 ' b00000000000000000000000000010111 ( 0) b00000000000000000000000000001010 * b00000000000000000000000000010100 + b00000000000000000000000000010110 , b00000000000000000000000000010111 - #10 b00000000000000000000000000000001 # b00000000000000000000000000001011 $ b00000000000000000000000000010101 % b00000000000000000000000000010110 & b00000000000000000000000000010111 ' b00000000000000000000000000011000 ( 1) #15 0) #20 b00000000000000000000000000000010 # b00000000000000000000000000001100 $ b00000000000000000000000000010110 % b00000000000000000000000000010111 & b00000000000000000000000000011000 ' b00000000000000000000000000011001 ( 1) #25 0) #30 b00000000000000000000000000000011 # b00000000000000000000000000001101 $ b00000000000000000000000000010111 % b00000000000000000000000000011000 & b00000000000000000000000000011001 ' b00000000000000000000000000011010 ( 1) #35 0) #40 b00000000000000000000000000000100 # b00000000000000000000000000001110 $ b00000000000000000000000000011000 % b00000000000000000000000000011001 & b00000000000000000000000000011010 ' b00000000000000000000000000011011 ( 1) #45 0) #50 b00000000000000000000000000000101 # b00000000000000000000000000001111 $ b00000000000000000000000000011001 % b00000000000000000000000000011010 & b00000000000000000000000000011011 ' b00000000000000000000000000011100 ( 1) #55 0) #60 b00000000000000000000000000000110 # b00000000000000000000000000010000 $ b00000000000000000000000000011010 % b00000000000000000000000000011011 & b00000000000000000000000000011100 ' b00000000000000000000000000011101 ( 1) #65 0) #70 b00000000000000000000000000000111 # b00000000000000000000000000010001 $ b00000000000000000000000000011011 % b00000000000000000000000000011100 & b00000000000000000000000000011101 ' b00000000000000000000000000011110 ( 1) #75 0) #80 b00000000000000000000000000001000 # b00000000000000000000000000010010 $ b00000000000000000000000000011100 % b00000000000000000000000000011101 & b00000000000000000000000000011110 ' b00000000000000000000000000011111 ( 1) #85 0) #90 b00000000000000000000000000001001 # b00000000000000000000000000010011 $ b00000000000000000000000000011101 % b00000000000000000000000000011110 & b00000000000000000000000000011111 ' b00000000000000000000000000100000 ( 1) #95 0) #100 b00000000000000000000000000001010 # b00000000000000000000000000010100 $ b00000000000000000000000000011110 % b00000000000000000000000000011111 & b00000000000000000000000000100000 ' b00000000000000000000000000100001 ( 1) #105 0) #110 b00000000000000000000000000001011 # b00000000000000000000000000010101 $ b00000000000000000000000000011111 % b00000000000000000000000000100000 & b00000000000000000000000000100001 ' b00000000000000000000000000100010 ( 1) verilator-5.042/test_regress/t/t_class_new_scoped.py0000755000542200017500000000072615101701376023306 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_preproc_inc_fn_bad.py0000755000542200017500000000105615101701376023564 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint( fails=True, # The .vh file has the error, not the .v file expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_opt_merge_cond.v0000644000542200017500000001525415101701376022573 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define check(got ,exp) do if ((got) !== (exp)) begin $write("%%Error: %s:%0d: cyc=%0d got='h%x exp='h%x\n", `__FILE__,`__LINE__, cyc, (got), (exp)); `stop; end while(0) module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc= 64'h5aef0c8d_d70a4497; reg [63:0] prev_crc; always @ (posedge clk) begin cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; prev_crc <= crc; if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end wire cond2 = &crc[1:0]; wire cond3 = &crc[2:0]; reg shuf_q [63:0]; always @(posedge clk) begin reg bits [63:0]; reg shuf_a [63:0]; reg shuf_b [63:0]; reg shuf_c [63:0]; reg shuf_d [63:0]; reg shuf_e [63:0]; // Unpack these to test core algorithm for (int i = 0; i < 64; i = i + 1) begin bits[i] = crc[i]; end for (int i = 0; i < 64; i = i + 1) begin shuf_a[i] = cyc[0] ? bits[i] : bits[63-i]; end if (cyc[1]) begin for (int i = 0; i < 64; i = i + 1) begin shuf_b[i] = cyc[0] ? bits[i] : bits[63-i]; end end else begin for (int i = 0; i < 64; i = i + 1) begin shuf_b[i] = cyc[0] ? bits[63-i] : bits[i]; end end // Also test merge under clean/bit extract for (int i = 0; i < 64; i = i + 1) begin shuf_c[i] = cyc[0] ? crc[i] : crc[63-i]; end // Merge with 'cond & value', 'value & cond', or 'cond' shuf_d[0] = cond2 ? bits[0] : bits[63]; for (int i = 1; i < 32; i = i + 2) begin shuf_d[i] = cond2 & bits[i]; end for (int i = 2; i < 32; i = i + 2) begin shuf_d[i] = bits[i] & cond2; end for (int i = 32; i < 64; i = i + 1) begin shuf_d[i] = cond2; end // Merge with an '&' also used for masking of LSB. shuf_e[0] = cond3 ? bits[0] : bits[63]; for (int i = 1; i < 64; i = i + 1) begin shuf_e[i] = cond3 & crc[0]; end // Also delayed.. for (int i = 0; i < 64; i = i + 1) begin shuf_q[i] <= cyc[0] ? crc[i] : crc[63-i]; end // Check results if (cyc[0]) begin for (int i = 0; i < 64; i = i + 1) `check(shuf_a[i], crc[i]); end else begin for (int i = 0; i < 64; i = i + 1) `check(shuf_a[i], crc[63-i]); end if (cyc[0] ~^ cyc[1]) begin for (int i = 0; i < 64; i = i + 1) `check(shuf_b[i], crc[i]); end else begin for (int i = 0; i < 64; i = i + 1) `check(shuf_b[i], crc[63-i]); end if (cyc[0]) begin for (int i = 0; i < 64; i = i + 1) `check(shuf_c[i], crc[i]); end else begin for (int i = 0; i < 64; i = i + 1) `check(shuf_c[i], crc[63-i]); end if (cond2) begin `check(shuf_d[0], crc[0]); for (int i = 1; i < 32; i = i + 1) `check(shuf_d[i], crc[i]); for (int i = 32; i < 63; i = i + 1) `check(shuf_d[i], 1'd1); end else begin `check(shuf_d[0], crc[63]); for (int i = 1; i < 32; i = i + 1) `check(shuf_d[i], 1'b0); for (int i = 32; i < 63; i = i + 1) `check(shuf_d[i], 1'd0); end if (cond3) begin `check(shuf_e[0], crc[0]); for (int i = 1; i < 63; i = i + 1) `check(shuf_e[i], crc[0]); end else begin `check(shuf_e[0], crc[63]); for (int i = 1; i < 63; i = i + 1) `check(shuf_e[i], 1'b0); end if (cyc > 0) begin if (~cyc[0]) begin for (int i = 0; i < 64; i = i + 1) `check(shuf_q[i], prev_crc[i]); end else begin for (int i = 0; i < 64; i = i + 1) `check(shuf_q[i], prev_crc[63-i]); end if (((cyc - 1) >> 1) % 2 == 1) begin for (int i = 0; i < 64; i = i + 1) `check(shuf_g[i], prev_crc[i]); end else begin for (int i = 0; i < 64; i = i + 1) `check(shuf_g[i], prev_crc[63-i]); end end if (cyc[2]) begin for (int i = 0; i < 64; i = i + 1) `check(shuf_w[i], crc[i]); end else begin for (int i = 0; i < 64; i = i + 1) `check(shuf_w[i], crc[63-i]); end end // Generated always reg shuf_g [63:0]; generate for (genvar i = 0 ; i < 64; i = i + 1) always @(posedge clk) begin shuf_g[i] <= cyc[1] ? crc[i] : crc[63-i]; end endgenerate // Generated assign wire shuf_w [63:0]; generate for (genvar i = 0 ; i < 64; i = i + 1) assign shuf_w[i] = cyc[2] ? crc[i] : crc[63-i]; endgenerate // Things not to merge always @(posedge clk) begin reg bits [63:0]; reg x; reg y; reg z; reg w; // Unpack these to test core algorithm for (int i = 0; i < 64; i = i + 1) begin bits[i] = crc[i]; end // Do not merge if condition appears in an LVALUE x = bits[0]; y = x ? bits[2] : bits[1]; x = x ? bits[3] : bits[4]; x = x ? bits[5] : bits[6]; `check(x, (bits[0] ? bits[3] : bits[4]) ? bits[5] : bits[6]); `check(y, bits[0] ? bits[2] : bits[1]); // However do merge when starting a new list in the same block with the // previous condition variable, but without the condition being an LVALUE x = cond2 ? bits[0] : bits[1]; y = cond2 & bits[2]; z = cond2 & bits[3]; w = cond2 & bits[4]; `check(x, cond2 ? bits[0] : bits[1]); `check(y, cond2 & bits[2]); `check(z, cond2 & bits[3]); `check(w, cond2 & bits[4]); // Do not merge if condition is not a pure expression $c("int _cnt = 0;"); x = $c("_cnt++") ? bits[0] : bits[1]; y = $c("_cnt++") ? bits[2] : bits[3]; z = $c("_cnt++") ? bits[4] : bits[5]; w = $c("_cnt++") ? bits[6] : bits[7]; $c("if (_cnt != 4) abort();"); `check(x, bits[1]); `check(y, bits[2]); `check(z, bits[4]); `check(w, bits[6]); // Do not merge with assignment under other statement x = cond2 ? bits[0] : bits[1]; if (bits[1]) begin y = cond2 ? bits[2] : bits[3]; end `check(x, cond2 ? bits[0] : bits[1]); if (bits[1]) begin `check(y, cond2 ? bits[2] : bits[3]); end // Do not merge with assignment under other statement x = cond2 ? bits[0] : bits[1]; if (bits[1]) begin y = cond2 & bits[2]; end `check(x, cond2 ? bits[0] : bits[1]); if (bits[1]) begin `check(y, cond2 & bits[2]); end end endmodule verilator-5.042/test_regress/t/t_dist_lint_py.py0000755000542200017500000000130415101701376022465 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') if 'VERILATOR_TEST_NO_LINT_PY' in os.environ: test.skip("Skipping due to VERILATOR_TEST_NO_LINT_PY") if not os.path.exists(test.root + "/.git"): test.skip("Not in a git repository") test.run(cmd=["cd " + test.root + " && " + os.environ["MAKE"] + " lint-py"]) test.passes() verilator-5.042/test_regress/t/t_class_reference_name_colision.v0000644000542200017500000000071215101701376025622 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class setup_coefficients; static function int create(); return 1; endfunction endclass class biquad_vseq; int c_setup = setup_coefficients::create(); function void setup_coefficients(); endfunction endclass: biquad_vseq verilator-5.042/test_regress/t/t_flag_stats.v0000644000542200017500000000067615101701376021740 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (b, b2); output reg [31:0] b; output reg [31:0] b2; // Need 2 vars of same width to cover V3Stats initial begin b = 11; b2 = 22; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_stream_unpack_lhs.out0000644000542200017500000000355315101701376023652 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_stream_unpack_lhs.v:113:38: Unsupported/Illegal: Assignment pattern member not underneath a supported construct: NEQ : ... note: In instance 't' 113 | if (unpacked_siz_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; | ^~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_stream_unpack_lhs.v:114:38: Unsupported/Illegal: Assignment pattern member not underneath a supported construct: NEQ : ... note: In instance 't' 114 | if (unpacked_asc_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; | ^~ %Error-UNSUPPORTED: t/t_stream_unpack_lhs.v:115:38: Unsupported/Illegal: Assignment pattern member not underneath a supported construct: NEQ : ... note: In instance 't' 115 | if (unpacked_des_dout != '{8'h76, 8'h54, 8'h32, 8'h10}) $stop; | ^~ %Error-UNSUPPORTED: t/t_stream_unpack_lhs.v:117:36: Unsupported/Illegal: Assignment pattern member not underneath a supported construct: NEQ : ... note: In instance 't' 117 | if (packed_siz_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; | ^~ %Error: Internal Error: t/t_stream_unpack_lhs.v:117:36: ../V3Width.cpp:#: Node has no type : ... note: In instance 't' 117 | if (packed_siz_dout != '{8'h01, 8'h23, 8'h45, 8'h67}) $stop; | ^~ ... This fatal error may be caused by the earlier error(s); resolve those first. verilator-5.042/test_regress/t/t_preproc_eof1_bad.v0000644000542200017500000000033115101701376022767 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 /* verilator-5.042/test_regress/t/t_sys_file_null.v0000644000542200017500000000113215101701376022444 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" module t; integer fd, cnt; initial begin fd = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/zeros.log"}, "w"); for (cnt = 0; cnt < 4; cnt = cnt + 1) $fwrite(fd, "%c", 8'd0); for (cnt = 0; cnt < 16; cnt = cnt + 4) $fwrite(fd, "%u", 32'd0); $fclose(fd); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_static_in_loop_unsup.out0000644000542200017500000000070015101701376024377 0ustar mahmoudyfreeshell%Warning-STATICVAR: t/t_static_in_loop_unsup.v:14:24: Static variable with assignment declaration declared in a loop converted to automatic 14 | static int a = 0; | ^ ... For warning description see https://verilator.org/warn/STATICVAR?v=latest ... Use "/* verilator lint_off STATICVAR */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_unopt_combo_isolate.py0000755000542200017500000000361315101701376024035 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_unopt_combo.v" out_filename = test.obj_dir + "/V" + test.name + ".tree.json" test.compile(verilator_flags2=["--no-json-edit-nums", "+define+ISOLATE", "--stats", "-fno-dfg"]) if test.vlt_all: test.file_grep(test.stats, r'Optimizations, isolate_assignments blocks\s+4') test.file_grep( out_filename, r'{"type":"VAR","name":"t.b",.*"loc":"\w,23:[^"]*",.*"origName":"b",.*"attrIsolateAssign":true,.*"dtypeName":"logic"' ) test.file_grep( out_filename, r'{"type":"VAR","name":"__Vfunc_t.file.get_31_16__0__Vfuncout",.*"loc":"\w,99:[^"]*",.*"origName":"__Vfunc_t__DOT__file__DOT__get_31_16__0__Vfuncout",.*"attrIsolateAssign":true,.*"dtypeName":"logic"' ) test.file_grep( out_filename, r'{"type":"VAR","name":"__Vfunc_t.file.get_31_16__0__t_crc",.*"loc":"\w,100:[^"]*",.*"origName":"__Vfunc_t__DOT__file__DOT__get_31_16__0__t_crc",.*"attrIsolateAssign":true,.*"dtypeName":"logic"' ) test.file_grep( out_filename, r'{"type":"VAR","name":"__Vtask_t.file.set_b_d__1__t_crc",.*"loc":"\w,112:[^"]*",.*"origName":"__Vtask_t__DOT__file__DOT__set_b_d__1__t_crc",.*"attrIsolateAssign":true,.*"dtypeName":"logic"' ) test.file_grep( out_filename, r'{"type":"VAR","name":"__Vtask_t.file.set_b_d__1__t_c",.*"loc":"\w,113:[^"]*",.*"origName":"__Vtask_t__DOT__file__DOT__set_b_d__1__t_c",.*"attrIsolateAssign":true,.*"dtypeName":"logic"' ) test.execute() test.passes() verilator-5.042/test_regress/t/t_timing_func_fork.v0000644000542200017500000000167315101701376023132 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t; function int f1; fork begin #1 $stop; end join_none f1 = 0; endfunction function int f2; fork begin int x; x = #5 0; $stop; end join_none f2 = 0; endfunction event e; function int f3; fork begin int x; @e $stop; x = 0; end join_none f3 = 0; endfunction function int f4; fork begin int x; x = @e 0; $stop; end join_none f4 = 0; endfunction int i; function int f5; fork begin int x; wait(i == 0) $stop; x = 0; end join_none f5 = 0; endfunction initial begin fork begin i = f1(); $write("*-* All Finished *-*\n"); $finish; end join_none end endmodule verilator-5.042/test_regress/t/t_interface_missing_bad.py0000755000542200017500000000076615101701376024276 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_queue_arg.v0000644000542200017500000000224715101701376021562 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); typedef struct { string name1; string name2; } names_t; class uvm_queue; names_t m_queue[$]; virtual function void push_back(names_t item); m_queue.push_back(item); endfunction endclass module t; uvm_queue q; initial begin q = new; // From uvm_queue#(uvm_acs_name_struct) __local_field_names__; q.push_back('{"n1", "n2"}); q.push_back('{"m1", "m2"}); q.m_queue.push_back('{"o1", "o2"}); $display("%p", q); `checks(q.m_queue[0].name1, "n1"); `checks(q.m_queue[0].name2, "n2"); `checks(q.m_queue[1].name1, "m1"); `checks(q.m_queue[1].name2, "m2"); `checks(q.m_queue[2].name1, "o1"); `checks(q.m_queue[2].name2, "o2"); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_sv_conditional.py0000755000542200017500000000073415101701376023005 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_parse_delay.v0000644000542200017500000000077215101701376022076 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; // verilator lint_off WIDTH reg [6:0] myreg1; initial begin myreg1 = # 100 7'd0; myreg1 = # 100 'b0; // [#] [100] ['b0] myreg1 = #100'b0; // [#] [100] ['b0] myreg1 = 100'b0; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_lint_unused_bad.out0000644000542200017500000001056715101701376023312 0ustar mahmoudyfreeshell%Warning-UNUSEDSIGNAL: t/t_lint_unused_bad.v:17:15: Bits of signal are not used: 'assunu1'[5:1] : ... note: In instance 't.sub' 17 | wire [5:0] assunu1 = 0; | ^~~~~~~ ... For warning description see https://verilator.org/warn/UNUSEDSIGNAL?v=latest ... Use "/* verilator lint_off UNUSEDSIGNAL */" and lint_on around source to disable this message. %Warning-UNDRIVEN: t/t_lint_unused_bad.v:21:17: Bits of signal are not driven: 'udrb2'[14:13,11] : ... note: In instance 't.sub' 21 | wire [15:10] udrb2; | ^~~~~ ... For warning description see https://verilator.org/warn/UNDRIVEN?v=latest ... Use "/* verilator lint_off UNDRIVEN */" and lint_on around source to disable this message. %Warning-UNUSEDSIGNAL: t/t_lint_unused_bad.v:26:15: Signal is not driven, nor used: 'unu3' : ... note: In instance 't.sub' 26 | wire unu3; | ^~~~ %Warning-UNUSEDSIGNAL: t/t_lint_unused_bad.v:28:15: Bits of signal are not driven, nor used: 'mixed'[3] : ... note: In instance 't.sub' 28 | wire [3:0] mixed; | ^~~~~ %Warning-UNUSEDSIGNAL: t/t_lint_unused_bad.v:28:15: Bits of signal are not used: 'mixed'[2] : ... note: In instance 't.sub' 28 | wire [3:0] mixed; | ^~~~~ %Warning-UNDRIVEN: t/t_lint_unused_bad.v:28:15: Bits of signal are not driven: 'mixed'[1] : ... note: In instance 't.sub' 28 | wire [3:0] mixed; | ^~~~~ %Warning-UNUSEDPARAM: t/t_lint_unused_bad.v:37:14: Parameter is not used: 'UNUSED_P' : ... note: In instance 't.sub' 37 | parameter UNUSED_P = 1; | ^~~~~~~~ ... For warning description see https://verilator.org/warn/UNUSEDPARAM?v=latest ... Use "/* verilator lint_off UNUSEDPARAM */" and lint_on around source to disable this message. %Warning-UNUSEDPARAM: t/t_lint_unused_bad.v:38:15: Parameter is not used: 'UNUSED_LP' : ... note: In instance 't.sub' 38 | localparam UNUSED_LP = 2; | ^~~~~~~~~ %Warning-UNUSEDGENVAR: t/t_lint_unused_bad.v:40:15: Genvar is not used: 'unused_gv' : ... note: In instance 't.sub' 40 | genvar unused_gv; | ^~~~~~~~~ ... For warning description see https://verilator.org/warn/UNUSEDGENVAR?v=latest ... Use "/* verilator lint_off UNUSEDGENVAR */" and lint_on around source to disable this message. %Warning-UNUSEDPARAM: t/t_lint_unused_bad.v:45:15: Parameter is not used: 'linter_param1' : ... note: In instance 't.sub' 45 | localparam linter_param1 = 1; | ^~~~~~~~~~~~~ %Warning-UNUSEDGENVAR: t/t_lint_unused_bad.v:46:11: Genvar is not used: 'linter_genvar1' : ... note: In instance 't.sub' 46 | genvar linter_genvar1; | ^~~~~~~~~~~~~~ %Warning-UNUSEDSIGNAL: t/t_lint_unused_bad.v:50:9: Signal is not driven, nor used: 'linter_sig2' : ... note: In instance 't.sub' 50 | wire linter_sig2; | ^~~~~~~~~~~ %Warning-UNUSEDGENVAR: t/t_lint_unused_bad.v:52:11: Genvar is not used: 'linter_genvar2' : ... note: In instance 't.sub' 52 | genvar linter_genvar2; | ^~~~~~~~~~~~~~ %Warning-UNUSEDSIGNAL: t/t_lint_unused_bad.v:56:9: Signal is not driven, nor used: 'linter_sig3' : ... note: In instance 't.sub' 56 | wire linter_sig3; | ^~~~~~~~~~~ %Warning-UNUSEDPARAM: t/t_lint_unused_bad.v:57:15: Parameter is not used: 'linter_param3' : ... note: In instance 't.sub' 57 | localparam linter_param3 = 3; | ^~~~~~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_parse_sync_bad.py0000755000542200017500000000076315101701376022750 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_math_shiftls.v0000644000542200017500000000115115101701376022263 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Zhen Yan. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkd(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__, `__LINE__, (gotv), (expv)); `stop; end while(0); module top (out33); output wire [6:0] out33; assign out33 = (7'o66 <<< 32'hFFFF_FFFF); initial begin #10; `checkd(out33, '0); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_assert_basic_fail.py0000755000542200017500000000124215101701376023422 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_assert_basic.v" test.compile(v_flags2=[ '+define+FAILING_ASSERTIONS', ('--assert' if test.vlt_all else ('+assert' if test.nc else '')) ], fails=test.nc) test.execute(fails=test.vlt_all) test.passes() verilator-5.042/test_regress/t/t_preproc_inc_recurse_bad.py0000755000542200017500000000076615101701376024640 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_var_const2.py0000755000542200017500000000070615101701376022051 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.042/test_regress/t/t_interface_virtual_sched_ico.v0000644000542200017500000000205215101701376025305 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 interface If; logic [31:0] inc; endinterface module top; logic clk = 0; logic [31:0] inc1 = 0; logic [31:0] inc2 = 0; int cyc = 0; If intf1(); If intf2(); virtual If vif1 = intf1; virtual If vif2 = intf2; // assign vif1.inc = inc1; always @(posedge clk) begin vif1.inc <= inc1; end assign intf2.inc = inc2; always @(posedge clk) begin cyc <= cyc + 1; if (cyc >= 10) begin $write("*-* All Finished *-*\n"); $finish; end end always @(intf1.inc) begin $write("[%0t] intf1.inc==%h\n", $time, intf1.inc); end always @(vif2.inc) begin $write("[%0t] vif2.inc==%h\n", $time, vif2.inc); end initial begin repeat (30) #5ns clk = ~clk; end initial begin inc1 = 1; inc2 = 1; repeat (8) begin #10ns; inc1 = inc1 + 1; inc2 = inc2 + 1; end end endmodule verilator-5.042/test_regress/t/t_public_seq.py0000755000542200017500000000106015101701376022111 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_vpi_sc.py0000755000542200017500000000116415101701376021253 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile( # Must not make shell/main or hides bug make_top_shell=False, make_main=False, verilator_flags2=["--exe --vpi --sc", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_inst_dtree_inlcd.py0000755000542200017500000000111615101701376023276 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_inst_dtree.v" test.compile(v_flags2=['+define+INLINE_C +define+INLINE_D'], verilator_flags2=['-trace']) test.execute() test.passes() verilator-5.042/test_regress/t/t_randomize_method_nclass_bad.out0000644000542200017500000000043615101701376025646 0ustar mahmoudyfreeshell%Error: t/t_randomize_method_nclass_bad.v:10:7: Calling implicit class method 'srandom' without being under class 10 | srandom(1); | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_assoc_wildcard_bad.v0000644000542200017500000000214215101701376023366 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef class Cls; class Cls; integer imembera; integer imemberb; endclass : Cls module t; initial begin string a [*]; string k; string v; Cls x; v = a.num("badarg"); v = a.size("badarg"); v = a.exists(); // Bad v = a.exists(k, "bad2"); a.delete(k, "bad2"); a.sort; // Not legal on assoc a.rsort; // Not legal on assoc a.reverse; // Not legal on assoc a.shuffle; // Not legal on assoc a.first; // Not legal on wildcard a.last; // Not legal on wildcard a.next; // Not legal on wildcard a.prev; // Not legal on wildcard a.unique_index; // Not legal on wildcard a.find_index; // Not legal on wildcard a.find_first_index; // Not legal on wildcard a.find_last_index; // Not legal on wildcard a[x] = "bad"; a.bad_not_defined(); end endmodule verilator-5.042/test_regress/t/t_class_param_bad2.out0000644000542200017500000000115015101701376023314 0ustar mahmoudyfreeshell%Error: t/t_class_param_bad2.v:12:4: Class parameter type without default value is never given value (IEEE 1800-2023 6.20.1): 'PARAMB' : ... note: In instance 't' 12 | Cls c; | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_class_param_bad2.v:7:18: Parameter type without default value is never given value (IEEE 1800-2023 6.20.1): 'PARAMB' : ... note: In instance 't' 7 | class Cls #(type PARAMB); | ^~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_lint_nolatch_bad.py0000755000542200017500000000076615101701376023263 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_scheduling_6.v0000644000542200017500000000157515101701376022162 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2022 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module top( clk ); input clk; reg clk_half = 0; reg [31:0] cyc = 0; reg [31:0] a, b, c; always @(posedge clk) begin $display("tick %d: a: %d, b: %d, c: %d", cyc, a, b, c); // Check invariant if (cyc + 1 !== a) $stop; if (cyc + 2 !== b) $stop; if (cyc + 2 !== c) $stop; // End of test if (cyc == 100) begin $write("*-* All Finished *-*\n"); $finish; end cyc <= cyc + 1; end always @(posedge clk) a = cyc + $c(1); always @(a) b = a + $c(1); assign c = a + $c(1); endmodule verilator-5.042/test_regress/t/t_class_modscope.v0000644000542200017500000000142015101701376022573 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module m(); class c; static function void fstatic(); `checkh(v, 42); v++; endfunction function void fnonstatic(); `checkh(v, 43); v++; endfunction endclass c classinst; int v; initial begin v=42; `checkh(v, 42); c::fstatic(); classinst = new(); classinst.fnonstatic(); `checkh(v, 44); $finish; end endmodule verilator-5.042/test_regress/t/t_inst_array_inl0.py0000755000542200017500000000104415101701376023062 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_inst_array.v" test.compile(v_flags2=['+define+NOUSE_INLINE']) test.execute() test.passes() verilator-5.042/test_regress/t/t_func_twocall.py0000755000542200017500000000073415101701376022452 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_paren_missing_bad.v0000644000542200017500000000053315101701376025265 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Goekce Aydos. // SPDX-License-Identifier: CC0-1.0 // Interface instantiation without parenthesis interface intf; endinterface module t; intf intf_i; initial $finish; endmodule verilator-5.042/test_regress/t/t_protect_ids_key.out0000644000542200017500000000532415101701376023335 0ustar mahmoudyfreeshell verilator-5.042/test_regress/t/t_interface_gen5.py0000755000542200017500000000073415101701376022650 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_stream2.py0000755000542200017500000000073415101701376021347 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_force_subvar.v0000644000542200017500000000264715101701376022271 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module t(/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; sub sub(); // Test loop always @ (posedge clk) begin cyc <= cyc + 1; // procedural var sub.subvar if (cyc == 50) begin `checkh(sub.subvar, 32'h666); force sub.subvar = 32'hffff; end else if (cyc == 51) begin `checkh(sub.subvar, 32'hffff); sub.subvar = 32'h543; // Ignored as still forced end else if (cyc == 52) begin `checkh(sub.subvar, 32'hffff); end else if (cyc == 53) begin release sub.subvar; end else if (cyc == 54) begin `checkh(sub.subvar, 32'hffff); // Retains value until next procedural change sub.subvar = 32'h544; end else if (cyc == 56) begin `checkh(sub.subvar, 32'h544); end // else if (cyc == 99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module sub; int subvar; initial subvar = 32'h666; endmodule verilator-5.042/test_regress/t/t_hier_block_sc_trace_fst.out0000644000542200017500000140634715101701376025001 0ustar mahmoudyfreeshell$date Thu Oct 30 10:15:53 2025 $end $version fstWriter $end $timescale 1ps $end $scope module top $end $attrbegin misc 07 $unit::enum_t 4 enum_val_0 enum_val_1 enum_val_2 enum_val_3 00 01 10 11 1 $end $scope module t $end $var parameter 32 ! PARAM_A [31:0] $end $var parameter 32 " PARAM_B [31:0] $end $var wire 1 # clk $end $var wire 8 $ out0 [7:0] $end $var wire 8 % out1 [7:0] $end $var wire 8 & out2 [7:0] $end $var wire 8 ' out3 [7:0] $end $var wire 8 ( out3_2 [7:0] $end $var wire 8 ) out5 [7:0] $end $var wire 8 * out6 [7:0] $end $var int 32 + count [31:0] $end $scope module i_delay0 $end $var parameter 32 , N [31:0] $end $var parameter 32 - WIDTH [31:0] $end $var wire 1 # clk $end $var wire 8 ' in [7:0] $end $var wire 8 ) out [7:0] $end $var logic 8 . tmp [7:0] $end $scope module genblk1 $end $scope module i_delay $end $var parameter 32 / N [31:0] $end $var parameter 32 - WIDTH [31:0] $end $var wire 1 # clk $end $var wire 8 . in [7:0] $end $var wire 8 ) out [7:0] $end $var logic 8 ) tmp [7:0] $end $upscope $end $upscope $end $upscope $end $scope module i_delay1 $end $var parameter 32 0 N [31:0] $end $var parameter 32 - WIDTH [31:0] $end $var wire 1 # clk $end $var wire 8 ) in [7:0] $end $var wire 8 * out [7:0] $end $var logic 8 1 tmp [7:0] $end $scope module genblk1 $end $scope module i_delay $end $var parameter 32 , N [31:0] $end $var parameter 32 - WIDTH [31:0] $end $var wire 1 # clk $end $var wire 8 1 in [7:0] $end $var wire 8 * out [7:0] $end $var logic 8 2 tmp [7:0] $end $scope module genblk1 $end $scope module i_delay $end $var parameter 32 / N [31:0] $end $var parameter 32 - WIDTH [31:0] $end $var wire 1 # clk $end $var wire 8 2 in [7:0] $end $var wire 8 * out [7:0] $end $var logic 8 * tmp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module i_sub0 $end $var wire 1 # clk $end $var wire 8 ' in [7:0] $end $var wire 8 $ out [7:0] $end $scope module i_sub0 $end $var wire 1 # clk $end $var wire 8 ' in [7:0] $end $var wire 8 $ out [7:0] $end $upscope $end $upscope $end $scope module i_sub1 $end $var wire 1 # clk $end $var wire 8 $ in [11:4] $end $var wire 8 % out [7:0] $end $upscope $end $scope module i_sub2 $end $var wire 1 # clk $end $var wire 8 % in [7:0] $end $var wire 8 & out [7:0] $end $upscope $end $scope module i_sub3 $end $var parameter 8 3 P0 [7:0] $end $var parameter 32 4 UNPACKED_ARRAY[0] [31:0] $end $var parameter 32 5 UNPACKED_ARRAY[1] [31:0] $end $var parameter 16 6 UNUSED [15:0] $end $attrbegin misc 07 "" 1 $end $var parameter 2 7 ENUM [1:0] $end $var wire 1 # clk $end $var wire 8 & in [7:0] $end $var wire 8 ' out [7:0] $end $var logic 8 8 ff [7:0] $end $var wire 8 ' out4 [7:0] $end $var wire 8 9 out4_2 [7:0] $end $scope module i_sub4_0 $end $var parameter 32 : P0 [31:0] $end $var real_parameter 64 ; P1 $end $var real_parameter 64 < P3 $end $var wire 1 # clk $end $var wire 8 8 in [7:0] $end $var wire 8 ' out [7:0] $end $var logic 8 ' ff [7:0] $end $var logic 128 = sub5_in[0][0] [127:0] $end $var logic 128 > sub5_in[0][1] [127:0] $end $var logic 128 ? sub5_in[0][2] [127:0] $end $var logic 128 @ sub5_in[1][0] [127:0] $end $var logic 128 A sub5_in[1][1] [127:0] $end $var logic 128 B sub5_in[1][2] [127:0] $end $var wire 8 C sub5_out[0][0] [7:0] $end $var wire 8 D sub5_out[0][1] [7:0] $end $var wire 8 E sub5_out[0][2] [7:0] $end $var wire 8 F sub5_out[1][0] [7:0] $end $var wire 8 G sub5_out[1][1] [7:0] $end $var wire 8 H sub5_out[1][2] [7:0] $end $var int 32 I count [31:0] $end $scope module i_sub5 $end $var wire 1 # clk $end $var wire 128 J in[0][0] [127:0] $end $var wire 128 K in[0][1] [127:0] $end $var wire 128 L in[0][2] [127:0] $end $var wire 128 M in[1][0] [127:0] $end $var wire 128 N in[1][1] [127:0] $end $var wire 128 O in[1][2] [127:0] $end $var wire 8 P out[0][0] [7:0] $end $var wire 8 Q out[0][1] [7:0] $end $var wire 8 R out[0][2] [7:0] $end $var wire 8 S out[1][0] [7:0] $end $var wire 8 T out[1][1] [7:0] $end $var wire 8 U out[1][2] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var int 32 V i [31:0] $end $scope module unnamedblk2 $end $var int 32 W j [31:0] $end $scope module unnamedblk3 $end $var byte 8 X exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module i_sub4_1 $end $var parameter 32 : P0 [31:0] $end $var real_parameter 64 ; P1 $end $var real_parameter 64 Y P3 $end $var wire 1 # clk $end $var wire 8 8 in [7:0] $end $var wire 8 9 out [7:0] $end $var logic 8 9 ff [7:0] $end $var logic 128 Z sub5_in[0][0] [127:0] $end $var logic 128 [ sub5_in[0][1] [127:0] $end $var logic 128 \ sub5_in[0][2] [127:0] $end $var logic 128 ] sub5_in[1][0] [127:0] $end $var logic 128 ^ sub5_in[1][1] [127:0] $end $var logic 128 _ sub5_in[1][2] [127:0] $end $var wire 8 ` sub5_out[0][0] [7:0] $end $var wire 8 a sub5_out[0][1] [7:0] $end $var wire 8 b sub5_out[0][2] [7:0] $end $var wire 8 c sub5_out[1][0] [7:0] $end $var wire 8 d sub5_out[1][1] [7:0] $end $var wire 8 e sub5_out[1][2] [7:0] $end $var int 32 f count [31:0] $end $scope module i_sub5 $end $var wire 1 # clk $end $var wire 128 g in[0][0] [127:0] $end $var wire 128 h in[0][1] [127:0] $end $var wire 128 i in[0][2] [127:0] $end $var wire 128 j in[1][0] [127:0] $end $var wire 128 k in[1][1] [127:0] $end $var wire 128 l in[1][2] [127:0] $end $var wire 8 m out[0][0] [7:0] $end $var wire 8 n out[0][1] [7:0] $end $var wire 8 o out[0][2] [7:0] $end $var wire 8 p out[1][0] [7:0] $end $var wire 8 q out[1][1] [7:0] $end $var wire 8 r out[1][2] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var int 32 s i [31:0] $end $scope module unnamedblk2 $end $var int 32 t j [31:0] $end $scope module unnamedblk3 $end $var byte 8 u exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module i_sub3_2 $end $var parameter 8 3 P0 [7:0] $end $var parameter 32 v UNPACKED_ARRAY[0] [31:0] $end $var parameter 32 w UNPACKED_ARRAY[1] [31:0] $end $var parameter 16 6 UNUSED [15:0] $end $attrbegin misc 07 "" 1 $end $var parameter 2 7 ENUM [1:0] $end $var wire 1 # clk $end $var wire 8 & in [7:0] $end $var wire 8 ( out [7:0] $end $var logic 8 x ff [7:0] $end $var wire 8 ( out4 [7:0] $end $var wire 8 y out4_2 [7:0] $end $scope module i_sub4_0 $end $var parameter 32 : P0 [31:0] $end $var real_parameter 64 ; P1 $end $var real_parameter 64 < P3 $end $var wire 1 # clk $end $var wire 8 x in [7:0] $end $var wire 8 ( out [7:0] $end $var logic 8 ( ff [7:0] $end $var logic 128 z sub5_in[0][0] [127:0] $end $var logic 128 { sub5_in[0][1] [127:0] $end $var logic 128 | sub5_in[0][2] [127:0] $end $var logic 128 } sub5_in[1][0] [127:0] $end $var logic 128 ~ sub5_in[1][1] [127:0] $end $var logic 128 !! sub5_in[1][2] [127:0] $end $var wire 8 "! sub5_out[0][0] [7:0] $end $var wire 8 #! sub5_out[0][1] [7:0] $end $var wire 8 $! sub5_out[0][2] [7:0] $end $var wire 8 %! sub5_out[1][0] [7:0] $end $var wire 8 &! sub5_out[1][1] [7:0] $end $var wire 8 '! sub5_out[1][2] [7:0] $end $var int 32 (! count [31:0] $end $scope module i_sub5 $end $var wire 1 # clk $end $var wire 128 )! in[0][0] [127:0] $end $var wire 128 *! in[0][1] [127:0] $end $var wire 128 +! in[0][2] [127:0] $end $var wire 128 ,! in[1][0] [127:0] $end $var wire 128 -! in[1][1] [127:0] $end $var wire 128 .! in[1][2] [127:0] $end $var wire 8 /! out[0][0] [7:0] $end $var wire 8 0! out[0][1] [7:0] $end $var wire 8 1! out[0][2] [7:0] $end $var wire 8 2! out[1][0] [7:0] $end $var wire 8 3! out[1][1] [7:0] $end $var wire 8 4! out[1][2] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var int 32 5! i [31:0] $end $scope module unnamedblk2 $end $var int 32 6! j [31:0] $end $scope module unnamedblk3 $end $var byte 8 7! exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module i_sub4_1 $end $var parameter 32 : P0 [31:0] $end $var real_parameter 64 ; P1 $end $var real_parameter 64 Y P3 $end $var wire 1 # clk $end $var wire 8 x in [7:0] $end $var wire 8 y out [7:0] $end $var logic 8 y ff [7:0] $end $var logic 128 8! sub5_in[0][0] [127:0] $end $var logic 128 9! sub5_in[0][1] [127:0] $end $var logic 128 :! sub5_in[0][2] [127:0] $end $var logic 128 ;! sub5_in[1][0] [127:0] $end $var logic 128 ! sub5_out[0][0] [7:0] $end $var wire 8 ?! sub5_out[0][1] [7:0] $end $var wire 8 @! sub5_out[0][2] [7:0] $end $var wire 8 A! sub5_out[1][0] [7:0] $end $var wire 8 B! sub5_out[1][1] [7:0] $end $var wire 8 C! sub5_out[1][2] [7:0] $end $var int 32 D! count [31:0] $end $scope module i_sub5 $end $var wire 1 # clk $end $var wire 128 E! in[0][0] [127:0] $end $var wire 128 F! in[0][1] [127:0] $end $var wire 128 G! in[0][2] [127:0] $end $var wire 128 H! in[1][0] [127:0] $end $var wire 128 I! in[1][1] [127:0] $end $var wire 128 J! in[1][2] [127:0] $end $var wire 8 K! out[0][0] [7:0] $end $var wire 8 L! out[0][1] [7:0] $end $var wire 8 M! out[0][2] [7:0] $end $var wire 8 N! out[1][0] [7:0] $end $var wire 8 O! out[1][1] [7:0] $end $var wire 8 P! out[1][2] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var int 32 Q! i [31:0] $end $scope module unnamedblk2 $end $var int 32 R! j [31:0] $end $scope module unnamedblk3 $end $var byte 8 S! exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub0.i_sub0 $end $var wire 1 T! clk $end $var wire 8 U! in [7:0] $end $var wire 8 V! out [7:0] $end $scope module sub0 $end $var wire 1 T! clk $end $var wire 8 U! in [7:0] $end $var wire 8 V! out [7:0] $end $var logic 8 W! ff [7:0] $end $upscope $end $upscope $end $scope module top.t.i_sub1 $end $var wire 1 X! clk $end $var wire 8 Y! in [11:4] $end $var wire 8 Z! out [7:0] $end $scope module sub1 $end $var wire 1 X! clk $end $var wire 8 Y! in [11:4] $end $var wire 8 Z! out [7:0] $end $var logic 8 [! ff [7:0] $end $upscope $end $upscope $end $scope module top.t.i_sub2 $end $attrbegin misc 07 $unit::enum_t 4 enum_val_0 enum_val_1 enum_val_2 enum_val_3 00 01 10 11 2 $end $var wire 1 \! clk $end $var wire 8 ]! in [7:0] $end $var wire 8 ^! out [7:0] $end $scope module sub2 $end $var wire 1 \! clk $end $var wire 8 ]! in [7:0] $end $var wire 8 ^! out [7:0] $end $var logic 8 _! ff [7:0] $end $scope interface in_ifs $end $var wire 1 \! clk $end $var logic 8 _! data [7:0] $end $upscope $end $scope interface out_ifs $end $var wire 1 \! clk $end $var logic 8 `! data [7:0] $end $upscope $end $scope module i_sub3 $end $scope interface in $end $var wire 1 \! clk $end $var logic 8 _! data [7:0] $end $upscope $end $scope interface out $end $var wire 1 \! clk $end $var logic 8 `! data [7:0] $end $upscope $end $var wire 8 _! in_wire [7:0] $end $var wire 8 `! out_1 [7:0] $end $var wire 8 a! out_2 [7:0] $end $scope module i_sub3 $end $var parameter 8 b! P0 [7:0] $end $var parameter 32 c! UNPACKED_ARRAY[0] [31:0] $end $var parameter 32 d! UNPACKED_ARRAY[1] [31:0] $end $var parameter 16 e! UNUSED [15:0] $end $attrbegin misc 07 "" 2 $end $var parameter 2 f! ENUM [1:0] $end $var wire 1 \! clk $end $var wire 8 _! in [7:0] $end $var wire 8 `! out [7:0] $end $var logic 8 g! ff [7:0] $end $var wire 8 `! out4 [7:0] $end $var wire 8 h! out4_2 [7:0] $end $scope module i_sub4_0 $end $var parameter 32 i! P0 [31:0] $end $var real_parameter 64 j! P1 $end $var real_parameter 64 k! P3 $end $var wire 1 \! clk $end $var wire 8 g! in [7:0] $end $var wire 8 `! out [7:0] $end $var logic 8 `! ff [7:0] $end $var logic 128 l! sub5_in[0][0] [127:0] $end $var logic 128 m! sub5_in[0][1] [127:0] $end $var logic 128 n! sub5_in[0][2] [127:0] $end $var logic 128 o! sub5_in[1][0] [127:0] $end $var logic 128 p! sub5_in[1][1] [127:0] $end $var logic 128 q! sub5_in[1][2] [127:0] $end $var wire 8 r! sub5_out[0][0] [7:0] $end $var wire 8 s! sub5_out[0][1] [7:0] $end $var wire 8 t! sub5_out[0][2] [7:0] $end $var wire 8 u! sub5_out[1][0] [7:0] $end $var wire 8 v! sub5_out[1][1] [7:0] $end $var wire 8 w! sub5_out[1][2] [7:0] $end $var int 32 x! count [31:0] $end $scope module i_sub5 $end $var wire 1 \! clk $end $var wire 128 y! in[0][0] [127:0] $end $var wire 128 z! in[0][1] [127:0] $end $var wire 128 {! in[0][2] [127:0] $end $var wire 128 |! in[1][0] [127:0] $end $var wire 128 }! in[1][1] [127:0] $end $var wire 128 ~! in[1][2] [127:0] $end $var wire 8 !" out[0][0] [7:0] $end $var wire 8 "" out[0][1] [7:0] $end $var wire 8 #" out[0][2] [7:0] $end $var wire 8 $" out[1][0] [7:0] $end $var wire 8 %" out[1][1] [7:0] $end $var wire 8 &" out[1][2] [7:0] $end $var int 32 '" count [31:0] $end $var wire 8 (" val0[0] [7:0] $end $var wire 8 )" val0[1] [7:0] $end $var wire 8 *" val1[0] [7:0] $end $var wire 8 +" val1[1] [7:0] $end $var wire 8 ," val2[0] [7:0] $end $var wire 8 -" val2[1] [7:0] $end $var wire 8 ." val3[0] [7:0] $end $var wire 8 /" val3[1] [7:0] $end $scope module i_sub0 $end $var parameter 32 0" P0 [31:0] $end $var parameter 32 1" P1 [31:0] $end $var wire 8 2" out[0] [7:0] $end $var wire 8 3" out[1] [7:0] $end $upscope $end $scope module i_sub1 $end $var parameter 32 0" P0 [31:0] $end $var parameter 32 1" P1 [31:0] $end $var wire 8 4" out[0] [7:0] $end $var wire 8 5" out[1] [7:0] $end $upscope $end $scope module i_sub2 $end $var parameter 32 0" P0 [31:0] $end $var parameter 32 1" P1 [31:0] $end $var wire 8 6" out[0] [7:0] $end $var wire 8 7" out[1] [7:0] $end $upscope $end $scope module i_sub3 $end $var parameter 32 0" P0 [31:0] $end $var parameter 32 8" P1 [31:0] $end $var wire 8 9" out[0] [7:0] $end $var wire 8 :" out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var int 32 ;" i [31:0] $end $scope module unnamedblk2 $end $var int 32 <" j [31:0] $end $scope module unnamedblk3 $end $var bit 128 =" exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module unnamedblk1 $end $var int 32 >" i [31:0] $end $scope module unnamedblk2 $end $var int 32 ?" j [31:0] $end $scope module unnamedblk3 $end $var byte 8 @" exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module i_sub4_1 $end $var parameter 32 i! P0 [31:0] $end $var real_parameter 64 j! P1 $end $var real_parameter 64 A" P3 $end $var wire 1 \! clk $end $var wire 8 g! in [7:0] $end $var wire 8 h! out [7:0] $end $var logic 8 h! ff [7:0] $end $var logic 128 B" sub5_in[0][0] [127:0] $end $var logic 128 C" sub5_in[0][1] [127:0] $end $var logic 128 D" sub5_in[0][2] [127:0] $end $var logic 128 E" sub5_in[1][0] [127:0] $end $var logic 128 F" sub5_in[1][1] [127:0] $end $var logic 128 G" sub5_in[1][2] [127:0] $end $var wire 8 H" sub5_out[0][0] [7:0] $end $var wire 8 I" sub5_out[0][1] [7:0] $end $var wire 8 J" sub5_out[0][2] [7:0] $end $var wire 8 K" sub5_out[1][0] [7:0] $end $var wire 8 L" sub5_out[1][1] [7:0] $end $var wire 8 M" sub5_out[1][2] [7:0] $end $var int 32 N" count [31:0] $end $scope module i_sub5 $end $var wire 1 \! clk $end $var wire 128 O" in[0][0] [127:0] $end $var wire 128 P" in[0][1] [127:0] $end $var wire 128 Q" in[0][2] [127:0] $end $var wire 128 R" in[1][0] [127:0] $end $var wire 128 S" in[1][1] [127:0] $end $var wire 128 T" in[1][2] [127:0] $end $var wire 8 U" out[0][0] [7:0] $end $var wire 8 V" out[0][1] [7:0] $end $var wire 8 W" out[0][2] [7:0] $end $var wire 8 X" out[1][0] [7:0] $end $var wire 8 Y" out[1][1] [7:0] $end $var wire 8 Z" out[1][2] [7:0] $end $var int 32 [" count [31:0] $end $var wire 8 \" val0[0] [7:0] $end $var wire 8 ]" val0[1] [7:0] $end $var wire 8 ^" val1[0] [7:0] $end $var wire 8 _" val1[1] [7:0] $end $var wire 8 `" val2[0] [7:0] $end $var wire 8 a" val2[1] [7:0] $end $var wire 8 b" val3[0] [7:0] $end $var wire 8 c" val3[1] [7:0] $end $scope module i_sub0 $end $var parameter 32 0" P0 [31:0] $end $var parameter 32 1" P1 [31:0] $end $var wire 8 d" out[0] [7:0] $end $var wire 8 e" out[1] [7:0] $end $upscope $end $scope module i_sub1 $end $var parameter 32 0" P0 [31:0] $end $var parameter 32 1" P1 [31:0] $end $var wire 8 f" out[0] [7:0] $end $var wire 8 g" out[1] [7:0] $end $upscope $end $scope module i_sub2 $end $var parameter 32 0" P0 [31:0] $end $var parameter 32 1" P1 [31:0] $end $var wire 8 h" out[0] [7:0] $end $var wire 8 i" out[1] [7:0] $end $upscope $end $scope module i_sub3 $end $var parameter 32 0" P0 [31:0] $end $var parameter 32 8" P1 [31:0] $end $var wire 8 j" out[0] [7:0] $end $var wire 8 k" out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var int 32 l" i [31:0] $end $scope module unnamedblk2 $end $var int 32 m" j [31:0] $end $scope module unnamedblk3 $end $var bit 128 n" exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module unnamedblk1 $end $var int 32 o" i [31:0] $end $scope module unnamedblk2 $end $var int 32 p" j [31:0] $end $scope module unnamedblk3 $end $var byte 8 q" exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module i_sub3_2 $end $var parameter 8 b! P0 [7:0] $end $var parameter 32 r" UNPACKED_ARRAY[0] [31:0] $end $var parameter 32 s" UNPACKED_ARRAY[1] [31:0] $end $var parameter 16 e! UNUSED [15:0] $end $attrbegin misc 07 "" 2 $end $var parameter 2 f! ENUM [1:0] $end $var wire 1 \! clk $end $var wire 8 _! in [7:0] $end $var wire 8 a! out [7:0] $end $var logic 8 t" ff [7:0] $end $var wire 8 a! out4 [7:0] $end $var wire 8 u" out4_2 [7:0] $end $scope module i_sub4_0 $end $var parameter 32 i! P0 [31:0] $end $var real_parameter 64 j! P1 $end $var real_parameter 64 k! P3 $end $var wire 1 \! clk $end $var wire 8 t" in [7:0] $end $var wire 8 a! out [7:0] $end $var logic 8 a! ff [7:0] $end $var logic 128 v" sub5_in[0][0] [127:0] $end $var logic 128 w" sub5_in[0][1] [127:0] $end $var logic 128 x" sub5_in[0][2] [127:0] $end $var logic 128 y" sub5_in[1][0] [127:0] $end $var logic 128 z" sub5_in[1][1] [127:0] $end $var logic 128 {" sub5_in[1][2] [127:0] $end $var wire 8 |" sub5_out[0][0] [7:0] $end $var wire 8 }" sub5_out[0][1] [7:0] $end $var wire 8 ~" sub5_out[0][2] [7:0] $end $var wire 8 !# sub5_out[1][0] [7:0] $end $var wire 8 "# sub5_out[1][1] [7:0] $end $var wire 8 ## sub5_out[1][2] [7:0] $end $var int 32 $# count [31:0] $end $scope module i_sub5 $end $var wire 1 \! clk $end $var wire 128 %# in[0][0] [127:0] $end $var wire 128 &# in[0][1] [127:0] $end $var wire 128 '# in[0][2] [127:0] $end $var wire 128 (# in[1][0] [127:0] $end $var wire 128 )# in[1][1] [127:0] $end $var wire 128 *# in[1][2] [127:0] $end $var wire 8 +# out[0][0] [7:0] $end $var wire 8 ,# out[0][1] [7:0] $end $var wire 8 -# out[0][2] [7:0] $end $var wire 8 .# out[1][0] [7:0] $end $var wire 8 /# out[1][1] [7:0] $end $var wire 8 0# out[1][2] [7:0] $end $var int 32 1# count [31:0] $end $var wire 8 2# val0[0] [7:0] $end $var wire 8 3# val0[1] [7:0] $end $var wire 8 4# val1[0] [7:0] $end $var wire 8 5# val1[1] [7:0] $end $var wire 8 6# val2[0] [7:0] $end $var wire 8 7# val2[1] [7:0] $end $var wire 8 8# val3[0] [7:0] $end $var wire 8 9# val3[1] [7:0] $end $scope module i_sub0 $end $var parameter 32 0" P0 [31:0] $end $var parameter 32 1" P1 [31:0] $end $var wire 8 :# out[0] [7:0] $end $var wire 8 ;# out[1] [7:0] $end $upscope $end $scope module i_sub1 $end $var parameter 32 0" P0 [31:0] $end $var parameter 32 1" P1 [31:0] $end $var wire 8 <# out[0] [7:0] $end $var wire 8 =# out[1] [7:0] $end $upscope $end $scope module i_sub2 $end $var parameter 32 0" P0 [31:0] $end $var parameter 32 1" P1 [31:0] $end $var wire 8 ># out[0] [7:0] $end $var wire 8 ?# out[1] [7:0] $end $upscope $end $scope module i_sub3 $end $var parameter 32 0" P0 [31:0] $end $var parameter 32 8" P1 [31:0] $end $var wire 8 @# out[0] [7:0] $end $var wire 8 A# out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var int 32 B# i [31:0] $end $scope module unnamedblk2 $end $var int 32 C# j [31:0] $end $scope module unnamedblk3 $end $var bit 128 D# exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module unnamedblk1 $end $var int 32 E# i [31:0] $end $scope module unnamedblk2 $end $var int 32 F# j [31:0] $end $scope module unnamedblk3 $end $var byte 8 G# exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module i_sub4_1 $end $var parameter 32 i! P0 [31:0] $end $var real_parameter 64 j! P1 $end $var real_parameter 64 A" P3 $end $var wire 1 \! clk $end $var wire 8 t" in [7:0] $end $var wire 8 u" out [7:0] $end $var logic 8 u" ff [7:0] $end $var logic 128 H# sub5_in[0][0] [127:0] $end $var logic 128 I# sub5_in[0][1] [127:0] $end $var logic 128 J# sub5_in[0][2] [127:0] $end $var logic 128 K# sub5_in[1][0] [127:0] $end $var logic 128 L# sub5_in[1][1] [127:0] $end $var logic 128 M# sub5_in[1][2] [127:0] $end $var wire 8 N# sub5_out[0][0] [7:0] $end $var wire 8 O# sub5_out[0][1] [7:0] $end $var wire 8 P# sub5_out[0][2] [7:0] $end $var wire 8 Q# sub5_out[1][0] [7:0] $end $var wire 8 R# sub5_out[1][1] [7:0] $end $var wire 8 S# sub5_out[1][2] [7:0] $end $var int 32 T# count [31:0] $end $scope module i_sub5 $end $var wire 1 \! clk $end $var wire 128 U# in[0][0] [127:0] $end $var wire 128 V# in[0][1] [127:0] $end $var wire 128 W# in[0][2] [127:0] $end $var wire 128 X# in[1][0] [127:0] $end $var wire 128 Y# in[1][1] [127:0] $end $var wire 128 Z# in[1][2] [127:0] $end $var wire 8 [# out[0][0] [7:0] $end $var wire 8 \# out[0][1] [7:0] $end $var wire 8 ]# out[0][2] [7:0] $end $var wire 8 ^# out[1][0] [7:0] $end $var wire 8 _# out[1][1] [7:0] $end $var wire 8 `# out[1][2] [7:0] $end $var int 32 a# count [31:0] $end $var wire 8 b# val0[0] [7:0] $end $var wire 8 c# val0[1] [7:0] $end $var wire 8 d# val1[0] [7:0] $end $var wire 8 e# val1[1] [7:0] $end $var wire 8 f# val2[0] [7:0] $end $var wire 8 g# val2[1] [7:0] $end $var wire 8 h# val3[0] [7:0] $end $var wire 8 i# val3[1] [7:0] $end $scope module i_sub0 $end $var parameter 32 0" P0 [31:0] $end $var parameter 32 1" P1 [31:0] $end $var wire 8 j# out[0] [7:0] $end $var wire 8 k# out[1] [7:0] $end $upscope $end $scope module i_sub1 $end $var parameter 32 0" P0 [31:0] $end $var parameter 32 1" P1 [31:0] $end $var wire 8 l# out[0] [7:0] $end $var wire 8 m# out[1] [7:0] $end $upscope $end $scope module i_sub2 $end $var parameter 32 0" P0 [31:0] $end $var parameter 32 1" P1 [31:0] $end $var wire 8 n# out[0] [7:0] $end $var wire 8 o# out[1] [7:0] $end $upscope $end $scope module i_sub3 $end $var parameter 32 0" P0 [31:0] $end $var parameter 32 8" P1 [31:0] $end $var wire 8 p# out[0] [7:0] $end $var wire 8 q# out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var int 32 r# i [31:0] $end $scope module unnamedblk2 $end $var int 32 s# j [31:0] $end $scope module unnamedblk3 $end $var bit 128 t# exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module unnamedblk1 $end $var int 32 u# i [31:0] $end $scope module unnamedblk2 $end $var int 32 v# j [31:0] $end $scope module unnamedblk3 $end $var byte 8 w# exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3.i_sub4_0.i_sub5 $end $var wire 1 x# clk $end $var wire 128 y# in[0][0] [127:0] $end $var wire 128 z# in[0][1] [127:0] $end $var wire 128 {# in[0][2] [127:0] $end $var wire 128 |# in[1][0] [127:0] $end $var wire 128 }# in[1][1] [127:0] $end $var wire 128 ~# in[1][2] [127:0] $end $var wire 8 !$ out[0][0] [7:0] $end $var wire 8 "$ out[0][1] [7:0] $end $var wire 8 #$ out[0][2] [7:0] $end $var wire 8 $$ out[1][0] [7:0] $end $var wire 8 %$ out[1][1] [7:0] $end $var wire 8 &$ out[1][2] [7:0] $end $scope module sub5 $end $var wire 1 x# clk $end $var wire 128 '$ in[0][0] [127:0] $end $var wire 128 ($ in[0][1] [127:0] $end $var wire 128 )$ in[0][2] [127:0] $end $var wire 128 *$ in[1][0] [127:0] $end $var wire 128 +$ in[1][1] [127:0] $end $var wire 128 ,$ in[1][2] [127:0] $end $var wire 8 -$ out[0][0] [7:0] $end $var wire 8 .$ out[0][1] [7:0] $end $var wire 8 /$ out[0][2] [7:0] $end $var wire 8 0$ out[1][0] [7:0] $end $var wire 8 1$ out[1][1] [7:0] $end $var wire 8 2$ out[1][2] [7:0] $end $var int 32 3$ count [31:0] $end $var wire 8 4$ val0[0] [7:0] $end $var wire 8 5$ val0[1] [7:0] $end $var wire 8 6$ val1[0] [7:0] $end $var wire 8 7$ val1[1] [7:0] $end $var wire 8 8$ val2[0] [7:0] $end $var wire 8 9$ val2[1] [7:0] $end $var wire 8 :$ val3[0] [7:0] $end $var wire 8 ;$ val3[1] [7:0] $end $scope module i_sub0 $end $var parameter 32 <$ P0 [31:0] $end $var parameter 32 =$ P1 [31:0] $end $var wire 8 >$ out[0] [7:0] $end $var wire 8 ?$ out[1] [7:0] $end $upscope $end $scope module i_sub1 $end $var parameter 32 <$ P0 [31:0] $end $var parameter 32 =$ P1 [31:0] $end $var wire 8 @$ out[0] [7:0] $end $var wire 8 A$ out[1] [7:0] $end $upscope $end $scope module i_sub2 $end $var parameter 32 <$ P0 [31:0] $end $var parameter 32 =$ P1 [31:0] $end $var wire 8 B$ out[0] [7:0] $end $var wire 8 C$ out[1] [7:0] $end $upscope $end $scope module i_sub3 $end $var parameter 32 <$ P0 [31:0] $end $var parameter 32 D$ P1 [31:0] $end $var wire 8 E$ out[0] [7:0] $end $var wire 8 F$ out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var int 32 G$ i [31:0] $end $scope module unnamedblk2 $end $var int 32 H$ j [31:0] $end $scope module unnamedblk3 $end $var bit 128 I$ exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3.i_sub4_1.i_sub5 $end $var wire 1 J$ clk $end $var wire 128 K$ in[0][0] [127:0] $end $var wire 128 L$ in[0][1] [127:0] $end $var wire 128 M$ in[0][2] [127:0] $end $var wire 128 N$ in[1][0] [127:0] $end $var wire 128 O$ in[1][1] [127:0] $end $var wire 128 P$ in[1][2] [127:0] $end $var wire 8 Q$ out[0][0] [7:0] $end $var wire 8 R$ out[0][1] [7:0] $end $var wire 8 S$ out[0][2] [7:0] $end $var wire 8 T$ out[1][0] [7:0] $end $var wire 8 U$ out[1][1] [7:0] $end $var wire 8 V$ out[1][2] [7:0] $end $scope module sub5 $end $var wire 1 J$ clk $end $var wire 128 W$ in[0][0] [127:0] $end $var wire 128 X$ in[0][1] [127:0] $end $var wire 128 Y$ in[0][2] [127:0] $end $var wire 128 Z$ in[1][0] [127:0] $end $var wire 128 [$ in[1][1] [127:0] $end $var wire 128 \$ in[1][2] [127:0] $end $var wire 8 ]$ out[0][0] [7:0] $end $var wire 8 ^$ out[0][1] [7:0] $end $var wire 8 _$ out[0][2] [7:0] $end $var wire 8 `$ out[1][0] [7:0] $end $var wire 8 a$ out[1][1] [7:0] $end $var wire 8 b$ out[1][2] [7:0] $end $var int 32 c$ count [31:0] $end $var wire 8 d$ val0[0] [7:0] $end $var wire 8 e$ val0[1] [7:0] $end $var wire 8 f$ val1[0] [7:0] $end $var wire 8 g$ val1[1] [7:0] $end $var wire 8 h$ val2[0] [7:0] $end $var wire 8 i$ val2[1] [7:0] $end $var wire 8 j$ val3[0] [7:0] $end $var wire 8 k$ val3[1] [7:0] $end $scope module i_sub0 $end $var parameter 32 l$ P0 [31:0] $end $var parameter 32 m$ P1 [31:0] $end $var wire 8 n$ out[0] [7:0] $end $var wire 8 o$ out[1] [7:0] $end $upscope $end $scope module i_sub1 $end $var parameter 32 l$ P0 [31:0] $end $var parameter 32 m$ P1 [31:0] $end $var wire 8 p$ out[0] [7:0] $end $var wire 8 q$ out[1] [7:0] $end $upscope $end $scope module i_sub2 $end $var parameter 32 l$ P0 [31:0] $end $var parameter 32 m$ P1 [31:0] $end $var wire 8 r$ out[0] [7:0] $end $var wire 8 s$ out[1] [7:0] $end $upscope $end $scope module i_sub3 $end $var parameter 32 l$ P0 [31:0] $end $var parameter 32 t$ P1 [31:0] $end $var wire 8 u$ out[0] [7:0] $end $var wire 8 v$ out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var int 32 w$ i [31:0] $end $scope module unnamedblk2 $end $var int 32 x$ j [31:0] $end $scope module unnamedblk3 $end $var bit 128 y$ exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3_2.i_sub4_0.i_sub5 $end $var wire 1 z$ clk $end $var wire 128 {$ in[0][0] [127:0] $end $var wire 128 |$ in[0][1] [127:0] $end $var wire 128 }$ in[0][2] [127:0] $end $var wire 128 ~$ in[1][0] [127:0] $end $var wire 128 !% in[1][1] [127:0] $end $var wire 128 "% in[1][2] [127:0] $end $var wire 8 #% out[0][0] [7:0] $end $var wire 8 $% out[0][1] [7:0] $end $var wire 8 %% out[0][2] [7:0] $end $var wire 8 &% out[1][0] [7:0] $end $var wire 8 '% out[1][1] [7:0] $end $var wire 8 (% out[1][2] [7:0] $end $scope module sub5 $end $var wire 1 z$ clk $end $var wire 128 )% in[0][0] [127:0] $end $var wire 128 *% in[0][1] [127:0] $end $var wire 128 +% in[0][2] [127:0] $end $var wire 128 ,% in[1][0] [127:0] $end $var wire 128 -% in[1][1] [127:0] $end $var wire 128 .% in[1][2] [127:0] $end $var wire 8 /% out[0][0] [7:0] $end $var wire 8 0% out[0][1] [7:0] $end $var wire 8 1% out[0][2] [7:0] $end $var wire 8 2% out[1][0] [7:0] $end $var wire 8 3% out[1][1] [7:0] $end $var wire 8 4% out[1][2] [7:0] $end $var int 32 5% count [31:0] $end $var wire 8 6% val0[0] [7:0] $end $var wire 8 7% val0[1] [7:0] $end $var wire 8 8% val1[0] [7:0] $end $var wire 8 9% val1[1] [7:0] $end $var wire 8 :% val2[0] [7:0] $end $var wire 8 ;% val2[1] [7:0] $end $var wire 8 <% val3[0] [7:0] $end $var wire 8 =% val3[1] [7:0] $end $scope module i_sub0 $end $var parameter 32 >% P0 [31:0] $end $var parameter 32 ?% P1 [31:0] $end $var wire 8 @% out[0] [7:0] $end $var wire 8 A% out[1] [7:0] $end $upscope $end $scope module i_sub1 $end $var parameter 32 >% P0 [31:0] $end $var parameter 32 ?% P1 [31:0] $end $var wire 8 B% out[0] [7:0] $end $var wire 8 C% out[1] [7:0] $end $upscope $end $scope module i_sub2 $end $var parameter 32 >% P0 [31:0] $end $var parameter 32 ?% P1 [31:0] $end $var wire 8 D% out[0] [7:0] $end $var wire 8 E% out[1] [7:0] $end $upscope $end $scope module i_sub3 $end $var parameter 32 >% P0 [31:0] $end $var parameter 32 F% P1 [31:0] $end $var wire 8 G% out[0] [7:0] $end $var wire 8 H% out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var int 32 I% i [31:0] $end $scope module unnamedblk2 $end $var int 32 J% j [31:0] $end $scope module unnamedblk3 $end $var bit 128 K% exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3_2.i_sub4_1.i_sub5 $end $var wire 1 L% clk $end $var wire 128 M% in[0][0] [127:0] $end $var wire 128 N% in[0][1] [127:0] $end $var wire 128 O% in[0][2] [127:0] $end $var wire 128 P% in[1][0] [127:0] $end $var wire 128 Q% in[1][1] [127:0] $end $var wire 128 R% in[1][2] [127:0] $end $var wire 8 S% out[0][0] [7:0] $end $var wire 8 T% out[0][1] [7:0] $end $var wire 8 U% out[0][2] [7:0] $end $var wire 8 V% out[1][0] [7:0] $end $var wire 8 W% out[1][1] [7:0] $end $var wire 8 X% out[1][2] [7:0] $end $scope module sub5 $end $var wire 1 L% clk $end $var wire 128 Y% in[0][0] [127:0] $end $var wire 128 Z% in[0][1] [127:0] $end $var wire 128 [% in[0][2] [127:0] $end $var wire 128 \% in[1][0] [127:0] $end $var wire 128 ]% in[1][1] [127:0] $end $var wire 128 ^% in[1][2] [127:0] $end $var wire 8 _% out[0][0] [7:0] $end $var wire 8 `% out[0][1] [7:0] $end $var wire 8 a% out[0][2] [7:0] $end $var wire 8 b% out[1][0] [7:0] $end $var wire 8 c% out[1][1] [7:0] $end $var wire 8 d% out[1][2] [7:0] $end $var int 32 e% count [31:0] $end $var wire 8 f% val0[0] [7:0] $end $var wire 8 g% val0[1] [7:0] $end $var wire 8 h% val1[0] [7:0] $end $var wire 8 i% val1[1] [7:0] $end $var wire 8 j% val2[0] [7:0] $end $var wire 8 k% val2[1] [7:0] $end $var wire 8 l% val3[0] [7:0] $end $var wire 8 m% val3[1] [7:0] $end $scope module i_sub0 $end $var parameter 32 n% P0 [31:0] $end $var parameter 32 o% P1 [31:0] $end $var wire 8 p% out[0] [7:0] $end $var wire 8 q% out[1] [7:0] $end $upscope $end $scope module i_sub1 $end $var parameter 32 n% P0 [31:0] $end $var parameter 32 o% P1 [31:0] $end $var wire 8 r% out[0] [7:0] $end $var wire 8 s% out[1] [7:0] $end $upscope $end $scope module i_sub2 $end $var parameter 32 n% P0 [31:0] $end $var parameter 32 o% P1 [31:0] $end $var wire 8 t% out[0] [7:0] $end $var wire 8 u% out[1] [7:0] $end $upscope $end $scope module i_sub3 $end $var parameter 32 n% P0 [31:0] $end $var parameter 32 v% P1 [31:0] $end $var wire 8 w% out[0] [7:0] $end $var wire 8 x% out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var int 32 y% i [31:0] $end $scope module unnamedblk2 $end $var int 32 z% j [31:0] $end $scope module unnamedblk3 $end $var bit 128 {% exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 {% b00000000000000000000000000000000 z% b00000000000000000000000000000000 y% b00000011 x% b00000001 w% b00000000000000000000000000000011 v% b00000010 u% b00000001 t% b00000010 s% b00000001 r% b00000010 q% b00000001 p% b00000000000000000000000000000010 o% b00000000000000000000000000000001 n% b00000011 m% b00000001 l% b00000010 k% b00000001 j% b00000010 i% b00000001 h% b00000010 g% b00000001 f% b00000000000000000000000000000000 e% b00000000 d% b00000000 c% b00000000 b% b00000000 a% b00000000 `% b00000000 _% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ^% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 [% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Z% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Y% b00000000 X% b00000000 W% b00000000 V% b00000000 U% b00000000 T% b00000000 S% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Q% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 O% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 M% 0L% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 K% b00000000000000000000000000000000 J% b00000000000000000000000000000000 I% b00000011 H% b00000001 G% b00000000000000000000000000000011 F% b00000010 E% b00000001 D% b00000010 C% b00000001 B% b00000010 A% b00000001 @% b00000000000000000000000000000010 ?% b00000000000000000000000000000001 >% b00000011 =% b00000001 <% b00000010 ;% b00000001 :% b00000010 9% b00000001 8% b00000010 7% b00000001 6% b00000000000000000000000000000000 5% b00000000 4% b00000000 3% b00000000 2% b00000000 1% b00000000 0% b00000000 /% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 .% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ,% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 *% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 )% b00000000 (% b00000000 '% b00000000 &% b00000000 %% b00000000 $% b00000000 #% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 "% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 !% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 }$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 {$ 0z$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y$ b00000000000000000000000000000000 x$ b00000000000000000000000000000000 w$ b00000011 v$ b00000001 u$ b00000000000000000000000000000011 t$ b00000010 s$ b00000001 r$ b00000010 q$ b00000001 p$ b00000010 o$ b00000001 n$ b00000000000000000000000000000010 m$ b00000000000000000000000000000001 l$ b00000011 k$ b00000001 j$ b00000010 i$ b00000001 h$ b00000010 g$ b00000001 f$ b00000010 e$ b00000001 d$ b00000000000000000000000000000000 c$ b00000000 b$ b00000000 a$ b00000000 `$ b00000000 _$ b00000000 ^$ b00000000 ]$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 [$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Z$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Y$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 X$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W$ b00000000 V$ b00000000 U$ b00000000 T$ b00000000 S$ b00000000 R$ b00000000 Q$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 O$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 M$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 K$ 0J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 I$ b00000000000000000000000000000000 H$ b00000000000000000000000000000000 G$ b00000011 F$ b00000001 E$ b00000000000000000000000000000011 D$ b00000010 C$ b00000001 B$ b00000010 A$ b00000001 @$ b00000010 ?$ b00000001 >$ b00000000000000000000000000000010 =$ b00000000000000000000000000000001 <$ b00000011 ;$ b00000001 :$ b00000010 9$ b00000001 8$ b00000010 7$ b00000001 6$ b00000010 5$ b00000001 4$ b00000000000000000000000000000000 3$ b00000000 2$ b00000000 1$ b00000000 0$ b00000000 /$ b00000000 .$ b00000000 -$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ,$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 *$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 )$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ($ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '$ b00000000 &$ b00000000 %$ b00000000 $$ b00000000 #$ b00000000 "$ b00000000 !$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 }# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 {# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y# 0x# b00000000 w# b00000000000000000000000000000000 v# b00000000000000000000000000000000 u# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t# b00000000000000000000000000000000 s# b00000000000000000000000000000000 r# b00000011 q# b00000001 p# b00000010 o# b00000001 n# b00000010 m# b00000001 l# b00000010 k# b00000001 j# b00000011 i# b00000001 h# b00000010 g# b00000001 f# b00000010 e# b00000001 d# b00000010 c# b00000001 b# b00000000000000000000000000000000 a# b00000000 `# b00000000 _# b00000000 ^# b00000000 ]# b00000000 \# b00000000 [# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Z# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Y# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 X# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 U# b00000000000000000000000000000000 T# b00000000 S# b00000000 R# b00000000 Q# b00000000 P# b00000000 O# b00000000 N# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 M# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 K# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 I# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H# b00000000 G# b00000000000000000000000000000000 F# b00000000000000000000000000000000 E# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 D# b00000000000000000000000000000000 C# b00000000000000000000000000000000 B# b00000011 A# b00000001 @# b00000010 ?# b00000001 ># b00000010 =# b00000001 <# b00000010 ;# b00000001 :# b00000011 9# b00000001 8# b00000010 7# b00000001 6# b00000010 5# b00000001 4# b00000010 3# b00000001 2# b00000000000000000000000000000000 1# b00000000 0# b00000000 /# b00000000 .# b00000000 -# b00000000 ,# b00000000 +# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 *# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 )# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 (# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 &# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 %# b00000000000000000000000000000000 $# b00000000 ## b00000000 "# b00000000 !# b00000000 ~" b00000000 }" b00000000 |" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 {" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 w" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v" b00000000 u" b00000000 t" b00000000000000000000000000000001 s" b00000000000000000000000000000000 r" b00000000 q" b00000000000000000000000000000000 p" b00000000000000000000000000000000 o" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n" b00000000000000000000000000000000 m" b00000000000000000000000000000000 l" b00000011 k" b00000001 j" b00000010 i" b00000001 h" b00000010 g" b00000001 f" b00000010 e" b00000001 d" b00000011 c" b00000001 b" b00000010 a" b00000001 `" b00000010 _" b00000001 ^" b00000010 ]" b00000001 \" b00000000000000000000000000000000 [" b00000000 Z" b00000000 Y" b00000000 X" b00000000 W" b00000000 V" b00000000 U" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 T" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 S" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Q" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 O" b00000000000000000000000000000000 N" b00000000 M" b00000000 L" b00000000 K" b00000000 J" b00000000 I" b00000000 H" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 G" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 E" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 D" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B" r5 A" b00000000 @" b00000000000000000000000000000000 ?" b00000000000000000000000000000000 >" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 =" b00000000000000000000000000000000 <" b00000000000000000000000000000000 ;" b00000011 :" b00000001 9" b00000000000000000000000000000011 8" b00000010 7" b00000001 6" b00000010 5" b00000001 4" b00000010 3" b00000001 2" b00000000000000000000000000000010 1" b00000000000000000000000000000001 0" b00000011 /" b00000001 ." b00000010 -" b00000001 ," b00000010 +" b00000001 *" b00000010 )" b00000001 (" b00000000000000000000000000000000 '" b00000000 &" b00000000 %" b00000000 $" b00000000 #" b00000000 "" b00000000 !" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 {! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y! b00000000000000000000000000000000 x! b00000000 w! b00000000 v! b00000000 u! b00000000 t! b00000000 s! b00000000 r! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 o! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l! r4.1 k! r3.1 j! b00000000000000000000000000000010 i! b00000000 h! b00000000 g! b11 f! b1111111111111101 e! b00000000000000000000000000000001 d! b00000000000000000000000000000000 c! b00000011 b! b00000000 a! b00000000 `! b00000000 _! b00000000 ^! b00000000 ]! 0\! b00000000 [! b00000000 Z! b00000000 Y! 0X! b00000000 W! b00000000 V! b00000000 U! 0T! b00000000 S! b00000000000000000000000000000000 R! b00000000000000000000000000000000 Q! b00000000 P! b00000000 O! b00000000 N! b00000000 M! b00000000 L! b00000000 K! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 G! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 E! b00000000000000000000000000000000 D! b00000000 C! b00000000 B! b00000000 A! b00000000 @! b00000000 ?! b00000000 >! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 =! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 = r4.1 < r3.1 ; b00000000000000000000000000000010 : b00000000 9 b00000000 8 b00 7 b1111111111111101 6 b00000000000000000000000000000001 5 b00000000000000000000000000000000 4 b00000001 3 b00000000 2 b00000000 1 b00000000000000000000000000000011 0 b00000000000000000000000000000001 / b00000000 . b00000000000000000000000000001000 - b00000000000000000000000000000010 , b00000000000000000000000000000000 + b00000000 * b00000000 ) b00000000 ( b00000000 ' b00000000 & b00000000 % b00000000 $ 0# b00000000000000000000000000101100 " b00000000000000000000000000100001 ! $end #10 1# b00000001 % b00000010 & b00000010 ' b00000010 ( b00000000000000000000000000000001 + b00000001 8 b00000010 9 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 > b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 ? b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 @ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 A b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 B b00000000000000000000000000000001 I b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 L b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 M b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 N b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 [ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 \ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ] b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ^ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _ b00000000000000000000000000000001 f b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 h b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 j b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 k b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 l b00000001 x b00000010 y b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 { b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 | b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 } b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 !! b00000000000000000000000000000001 (! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 *! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ,! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 -! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 .! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 9! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 :! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ;! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 b00000011 9 b00000011 8 b00000000000000000000000000000010 + b00000011 ( b00000011 ' b00000101 & b00000010 $ b00000010 . b00000110 C b00000101 D b00000100 E b00000011 F b00000010 G b00000001 H b00000110 P b00000101 Q b00000100 R b00000011 S b00000010 T b00000001 U b00000000000000000000000000000010 V b00000000000000000000000000000011 W b00000110 ` b00000101 a b00000100 b b00000011 c b00000010 d b00000001 e b00000110 m b00000101 n b00000100 o b00000011 p b00000010 q b00000001 r b00000000000000000000000000000010 s b00000000000000000000000000000011 t b00000110 "! b00000101 #! b00000100 $! b00000011 %! b00000010 &! b00000001 '! b00000110 /! b00000101 0! b00000100 1! b00000011 2! b00000010 3! b00000001 4! b00000000000000000000000000000010 5! b00000000000000000000000000000011 6! b00000110 >! b00000101 ?! b00000100 @! b00000011 A! b00000010 B! b00000001 C! b00000110 K! b00000101 L! b00000100 M! b00000011 N! b00000010 O! b00000001 P! b00000000000000000000000000000010 Q! b00000000000000000000000000000011 R! b00000010 V! b00000010 W! b00000010 Y! b00000110 r! b00000101 s! b00000100 t! b00000011 u! b00000010 v! b00000001 w! b00000110 !" b00000101 "" b00000100 #" b00000011 $" b00000010 %" b00000001 &" b00000000000000000000000000000010 ;" b00000000000000000000000000000011 <" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 =" b00000000000000000000000000000010 >" b00000000000000000000000000000011 ?" b00000110 H" b00000101 I" b00000100 J" b00000011 K" b00000010 L" b00000001 M" b00000110 U" b00000101 V" b00000100 W" b00000011 X" b00000010 Y" b00000001 Z" b00000000000000000000000000000010 l" b00000000000000000000000000000011 m" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 n" b00000000000000000000000000000010 o" b00000000000000000000000000000011 p" b00000110 |" b00000101 }" b00000100 ~" b00000011 !# b00000010 "# b00000001 ## b00000110 +# b00000101 ,# b00000100 -# b00000011 .# b00000010 /# b00000001 0# b00000000000000000000000000000010 B# b00000000000000000000000000000011 C# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 D# b00000000000000000000000000000010 E# b00000000000000000000000000000011 F# b00000110 N# b00000101 O# b00000100 P# b00000011 Q# b00000010 R# b00000001 S# b00000110 [# b00000101 \# b00000100 ]# b00000011 ^# b00000010 _# b00000001 `# b00000000000000000000000000000010 r# b00000000000000000000000000000011 s# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 t# b00000000000000000000000000000010 u# b00000000000000000000000000000011 v# b00000110 !$ b00000101 "$ b00000100 #$ b00000011 $$ b00000010 %$ b00000001 &$ b00000110 -$ b00000101 .$ b00000100 /$ b00000011 0$ b00000010 1$ b00000001 2$ b00000000000000000000000000000010 G$ b00000000000000000000000000000011 H$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 I$ b00000110 Q$ b00000101 R$ b00000100 S$ b00000011 T$ b00000010 U$ b00000001 V$ b00000110 ]$ b00000101 ^$ b00000100 _$ b00000011 `$ b00000010 a$ b00000001 b$ b00000000000000000000000000000010 w$ b00000000000000000000000000000011 x$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 y$ b00000110 #% b00000101 $% b00000100 %% b00000011 &% b00000010 '% b00000001 (% b00000110 /% b00000101 0% b00000100 1% b00000011 2% b00000010 3% b00000001 4% b00000000000000000000000000000010 I% b00000000000000000000000000000011 J% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 K% b00000110 S% b00000101 T% b00000100 U% b00000011 V% b00000010 W% b00000001 X% b00000110 _% b00000101 `% b00000100 a% b00000011 b% b00000010 c% b00000001 d% b00000000000000000000000000000010 y% b00000000000000000000000000000011 z% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 {% #25 0L% 0z$ 0J$ 0x# 0\! 0X! 0T! 0# #30 1# 1T! 1X! 1\! 1x# 1J$ 1z$ 1L% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 {% b00000000 d% b00000000 c% b00000000 b% b00000000 a% b00000000 `% b00000000 _% b00000000 X% b00000000 W% b00000000 V% b00000000 U% b00000000 T% b00000000 S% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 K% b00000000 4% b00000000 3% b00000000 2% b00000000 1% b00000000 0% b00000000 /% b00000000 (% b00000000 '% b00000000 &% b00000000 %% b00000000 $% b00000000 #% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y$ b00000000 b$ b00000000 a$ b00000000 `$ b00000000 _$ b00000000 ^$ b00000000 ]$ b00000000 V$ b00000000 U$ b00000000 T$ b00000000 S$ b00000000 R$ b00000000 Q$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 I$ b00000000 2$ b00000000 1$ b00000000 0$ b00000000 /$ b00000000 .$ b00000000 -$ b00000000 &$ b00000000 %$ b00000000 $$ b00000000 #$ b00000000 "$ b00000000 !$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t# b00000000 `# b00000000 _# b00000000 ^# b00000000 ]# b00000000 \# b00000000 [# b00000000 S# b00000000 R# b00000000 Q# b00000000 P# b00000000 O# b00000000 N# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 D# b00000000 0# b00000000 /# b00000000 .# b00000000 -# b00000000 ,# b00000000 +# b00000000 ## b00000000 "# b00000000 !# b00000000 ~" b00000000 }" b00000000 |" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n" b00000000 Z" b00000000 Y" b00000000 X" b00000000 W" b00000000 V" b00000000 U" b00000000 M" b00000000 L" b00000000 K" b00000000 J" b00000000 I" b00000000 H" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 =" b00000000 &" b00000000 %" b00000000 $" b00000000 #" b00000000 "" b00000000 !" b00000000 w! b00000000 v! b00000000 u! b00000000 t! b00000000 s! b00000000 r! b00000011 Y! b00000011 W! b00000011 V! b00000000 P! b00000000 O! b00000000 N! b00000000 M! b00000000 L! b00000000 K! b00000000 C! b00000000 B! b00000000 A! b00000000 @! b00000000 ?! b00000000 >! b00000000 4! b00000000 3! b00000000 2! b00000000 1! b00000000 0! b00000000 /! b00000000 '! b00000000 &! b00000000 %! b00000000 $! b00000000 #! b00000000 "! b00000000 r b00000000 q b00000000 p b00000000 o b00000000 n b00000000 m b00000000 e b00000000 d b00000000 c b00000000 b b00000000 a b00000000 ` b00000000 U b00000000 T b00000000 S b00000000 R b00000000 Q b00000000 P b00000000 H b00000000 G b00000000 F b00000000 E b00000000 D b00000000 C b00000011 . b00000011 $ b00000111 & b00000101 ' b00000101 ( b00000000000000000000000000000011 + b00000110 8 b00000101 9 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 > b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 ? b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 @ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 A b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 B b00000000000000000000000000000011 I b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 L b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 M b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 N b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 [ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 \ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ] b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ^ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _ b00000000000000000000000000000011 f b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 h b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 j b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 k b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 l b00000110 x b00000101 y b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 { b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 | b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 } b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 !! b00000000000000000000000000000011 (! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 *! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ,! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 -! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 .! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 9! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 :! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ;! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 b00001000 9 b00001000 8 b00000000000000000000000000000100 + b00001000 ( b00001000 ' b00001000 & b00000101 $ b00000101 . b00000110 C b00000101 D b00000100 E b00000011 F b00000010 G b00000001 H b00000110 P b00000101 Q b00000100 R b00000011 S b00000010 T b00000001 U b00000110 ` b00000101 a b00000100 b b00000011 c b00000010 d b00000001 e b00000110 m b00000101 n b00000100 o b00000011 p b00000010 q b00000001 r b00000110 "! b00000101 #! b00000100 $! b00000011 %! b00000010 &! b00000001 '! b00000110 /! b00000101 0! b00000100 1! b00000011 2! b00000010 3! b00000001 4! b00000110 >! b00000101 ?! b00000100 @! b00000011 A! b00000010 B! b00000001 C! b00000110 K! b00000101 L! b00000100 M! b00000011 N! b00000010 O! b00000001 P! b00000101 V! b00000101 W! b00000101 Y! b00000110 r! b00000101 s! b00000100 t! b00000011 u! b00000010 v! b00000001 w! b00000110 !" b00000101 "" b00000100 #" b00000011 $" b00000010 %" b00000001 &" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 =" b00000110 H" b00000101 I" b00000100 J" b00000011 K" b00000010 L" b00000001 M" b00000110 U" b00000101 V" b00000100 W" b00000011 X" b00000010 Y" b00000001 Z" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 n" b00000110 |" b00000101 }" b00000100 ~" b00000011 !# b00000010 "# b00000001 ## b00000110 +# b00000101 ,# b00000100 -# b00000011 .# b00000010 /# b00000001 0# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 D# b00000110 N# b00000101 O# b00000100 P# b00000011 Q# b00000010 R# b00000001 S# b00000110 [# b00000101 \# b00000100 ]# b00000011 ^# b00000010 _# b00000001 `# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 t# b00000110 !$ b00000101 "$ b00000100 #$ b00000011 $$ b00000010 %$ b00000001 &$ b00000110 -$ b00000101 .$ b00000100 /$ b00000011 0$ b00000010 1$ b00000001 2$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 I$ b00000110 Q$ b00000101 R$ b00000100 S$ b00000011 T$ b00000010 U$ b00000001 V$ b00000110 ]$ b00000101 ^$ b00000100 _$ b00000011 `$ b00000010 a$ b00000001 b$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 y$ b00000110 #% b00000101 $% b00000100 %% b00000011 &% b00000010 '% b00000001 (% b00000110 /% b00000101 0% b00000100 1% b00000011 2% b00000010 3% b00000001 4% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 K% b00000110 S% b00000101 T% b00000100 U% b00000011 V% b00000010 W% b00000001 X% b00000110 _% b00000101 `% b00000100 a% b00000011 b% b00000010 c% b00000001 d% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 {% b00000101 _! b00000010 1 #45 0L% 0z$ 0J$ 0x# 0\! 0X! 0T! 0# #50 1# 1T! 1X! 1\! 1x# 1J$ 1z$ 1L% b00000011 1 b00000110 _! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 {% b00000000 d% b00000000 c% b00000000 b% b00000000 a% b00000000 `% b00000000 _% b00000000 X% b00000000 W% b00000000 V% b00000000 U% b00000000 T% b00000000 S% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 K% b00000000 4% b00000000 3% b00000000 2% b00000000 1% b00000000 0% b00000000 /% b00000000 (% b00000000 '% b00000000 &% b00000000 %% b00000000 $% b00000000 #% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y$ b00000000 b$ b00000000 a$ b00000000 `$ b00000000 _$ b00000000 ^$ b00000000 ]$ b00000000 V$ b00000000 U$ b00000000 T$ b00000000 S$ b00000000 R$ b00000000 Q$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 I$ b00000000 2$ b00000000 1$ b00000000 0$ b00000000 /$ b00000000 .$ b00000000 -$ b00000000 &$ b00000000 %$ b00000000 $$ b00000000 #$ b00000000 "$ b00000000 !$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t# b00000000 `# b00000000 _# b00000000 ^# b00000000 ]# b00000000 \# b00000000 [# b00000000 S# b00000000 R# b00000000 Q# b00000000 P# b00000000 O# b00000000 N# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 D# b00000000 0# b00000000 /# b00000000 .# b00000000 -# b00000000 ,# b00000000 +# b00000000 ## b00000000 "# b00000000 !# b00000000 ~" b00000000 }" b00000000 |" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n" b00000000 Z" b00000000 Y" b00000000 X" b00000000 W" b00000000 V" b00000000 U" b00000000 M" b00000000 L" b00000000 K" b00000000 J" b00000000 I" b00000000 H" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 =" b00000000 &" b00000000 %" b00000000 $" b00000000 #" b00000000 "" b00000000 !" b00000000 w! b00000000 v! b00000000 u! b00000000 t! b00000000 s! b00000000 r! b00001000 Y! b00001000 W! b00001000 V! b00000000 P! b00000000 O! b00000000 N! b00000000 M! b00000000 L! b00000000 K! b00000000 C! b00000000 B! b00000000 A! b00000000 @! b00000000 ?! b00000000 >! b00000000 4! b00000000 3! b00000000 2! b00000000 1! b00000000 0! b00000000 /! b00000000 '! b00000000 &! b00000000 %! b00000000 $! b00000000 #! b00000000 "! b00000000 r b00000000 q b00000000 p b00000000 o b00000000 n b00000000 m b00000000 e b00000000 d b00000000 c b00000000 b b00000000 a b00000000 ` b00000000 U b00000000 T b00000000 S b00000000 R b00000000 Q b00000000 P b00000000 H b00000000 G b00000000 F b00000000 E b00000000 D b00000000 C b00001000 . b00001000 $ b00001010 ' b00001010 ( b00000000000000000000000000000101 + b00001001 8 b00001010 9 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 > b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 ? b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 @ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 A b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 B b00000000000000000000000000000101 I b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 L b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 M b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 N b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 [ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 \ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ] b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ^ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _ b00000000000000000000000000000101 f b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 h b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 j b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 k b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 l b00001001 x b00001010 y b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 { b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 | b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 } b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 !! b00000000000000000000000000000101 (! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 *! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ,! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 -! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 .! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 9! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 :! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ;! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 b00001011 9 b00000000000000000000000000000110 + b00001011 ( b00001011 ' b00001010 $ b00001010 . b00000110 C b00000101 D b00000100 E b00000011 F b00000010 G b00000001 H b00000110 P b00000101 Q b00000100 R b00000011 S b00000010 T b00000001 U b00000110 ` b00000101 a b00000100 b b00000011 c b00000010 d b00000001 e b00000110 m b00000101 n b00000100 o b00000011 p b00000010 q b00000001 r b00000110 "! b00000101 #! b00000100 $! b00000011 %! b00000010 &! b00000001 '! b00000110 /! b00000101 0! b00000100 1! b00000011 2! b00000010 3! b00000001 4! b00000110 >! b00000101 ?! b00000100 @! b00000011 A! b00000010 B! b00000001 C! b00000110 K! b00000101 L! b00000100 M! b00000011 N! b00000010 O! b00000001 P! b00001010 V! b00001010 W! b00001010 Y! b00000110 r! b00000101 s! b00000100 t! b00000011 u! b00000010 v! b00000001 w! b00000110 !" b00000101 "" b00000100 #" b00000011 $" b00000010 %" b00000001 &" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 =" b00000110 H" b00000101 I" b00000100 J" b00000011 K" b00000010 L" b00000001 M" b00000110 U" b00000101 V" b00000100 W" b00000011 X" b00000010 Y" b00000001 Z" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 n" b00000110 |" b00000101 }" b00000100 ~" b00000011 !# b00000010 "# b00000001 ## b00000110 +# b00000101 ,# b00000100 -# b00000011 .# b00000010 /# b00000001 0# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 D# b00000110 N# b00000101 O# b00000100 P# b00000011 Q# b00000010 R# b00000001 S# b00000110 [# b00000101 \# b00000100 ]# b00000011 ^# b00000010 _# b00000001 `# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 t# b00000110 !$ b00000101 "$ b00000100 #$ b00000011 $$ b00000010 %$ b00000001 &$ b00000110 -$ b00000101 .$ b00000100 /$ b00000011 0$ b00000010 1$ b00000001 2$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 I$ b00000110 Q$ b00000101 R$ b00000100 S$ b00000011 T$ b00000010 U$ b00000001 V$ b00000110 ]$ b00000101 ^$ b00000100 _$ b00000011 `$ b00000010 a$ b00000001 b$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 y$ b00000110 #% b00000101 $% b00000100 %% b00000011 &% b00000010 '% b00000001 (% b00000110 /% b00000101 0% b00000100 1% b00000011 2% b00000010 3% b00000001 4% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 K% b00000110 S% b00000101 T% b00000100 U% b00000011 V% b00000010 W% b00000001 X% b00000110 _% b00000101 `% b00000100 a% b00000011 b% b00000010 c% b00000001 d% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 {% b00001000 _! b00000101 1 b00001010 & b00001010 ^! b00001010 `! b00001010 a! b00001010 h! b00001010 u" b00000010 * #65 0L% 0z$ 0J$ 0x# 0\! 0X! 0T! 0# #70 1# 1T! 1X! 1\! 1x# 1J$ 1z$ 1L% b00000011 * b00001011 u" b00001011 h! b00001011 a! b00001011 `! b00001011 ^! b00001011 & b00001000 1 b00001011 _! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 {% b00000000 d% b00000000 c% b00000000 b% b00000000 a% b00000000 `% b00000000 _% b00000000 X% b00000000 W% b00000000 V% b00000000 U% b00000000 T% b00000000 S% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 K% b00000000 4% b00000000 3% b00000000 2% b00000000 1% b00000000 0% b00000000 /% b00000000 (% b00000000 '% b00000000 &% b00000000 %% b00000000 $% b00000000 #% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y$ b00000000 b$ b00000000 a$ b00000000 `$ b00000000 _$ b00000000 ^$ b00000000 ]$ b00000000 V$ b00000000 U$ b00000000 T$ b00000000 S$ b00000000 R$ b00000000 Q$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 I$ b00000000 2$ b00000000 1$ b00000000 0$ b00000000 /$ b00000000 .$ b00000000 -$ b00000000 &$ b00000000 %$ b00000000 $$ b00000000 #$ b00000000 "$ b00000000 !$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t# b00000000 `# b00000000 _# b00000000 ^# b00000000 ]# b00000000 \# b00000000 [# b00000000 S# b00000000 R# b00000000 Q# b00000000 P# b00000000 O# b00000000 N# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 D# b00000000 0# b00000000 /# b00000000 .# b00000000 -# b00000000 ,# b00000000 +# b00000000 ## b00000000 "# b00000000 !# b00000000 ~" b00000000 }" b00000000 |" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n" b00000000 Z" b00000000 Y" b00000000 X" b00000000 W" b00000000 V" b00000000 U" b00000000 M" b00000000 L" b00000000 K" b00000000 J" b00000000 I" b00000000 H" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 =" b00000000 &" b00000000 %" b00000000 $" b00000000 #" b00000000 "" b00000000 !" b00000000 w! b00000000 v! b00000000 u! b00000000 t! b00000000 s! b00000000 r! b00001011 Y! b00001011 W! b00001011 V! b00000000 P! b00000000 O! b00000000 N! b00000000 M! b00000000 L! b00000000 K! b00000000 C! b00000000 B! b00000000 A! b00000000 @! b00000000 ?! b00000000 >! b00000000 4! b00000000 3! b00000000 2! b00000000 1! b00000000 0! b00000000 /! b00000000 '! b00000000 &! b00000000 %! b00000000 $! b00000000 #! b00000000 "! b00000000 r b00000000 q b00000000 p b00000000 o b00000000 n b00000000 m b00000000 e b00000000 d b00000000 c b00000000 b b00000000 a b00000000 ` b00000000 U b00000000 T b00000000 S b00000000 R b00000000 Q b00000000 P b00000000 H b00000000 G b00000000 F b00000000 E b00000000 D b00000000 C b00001011 . b00001011 $ b00000000000000000000000000000111 + b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 > b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 ? b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 @ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 A b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 B b00000000000000000000000000000111 I b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 L b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 M b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 N b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 [ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 \ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ] b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ^ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _ b00000000000000000000000000000111 f b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 h b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 j b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 k b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 l b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 { b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 | b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 } b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 !! b00000000000000000000000000000111 (! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 *! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ,! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 -! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 .! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 9! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 :! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ;! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 b00000000000000000000000000001000 + b00000110 C b00000101 D b00000100 E b00000011 F b00000010 G b00000001 H b00000110 P b00000101 Q b00000100 R b00000011 S b00000010 T b00000001 U b00000110 ` b00000101 a b00000100 b b00000011 c b00000010 d b00000001 e b00000110 m b00000101 n b00000100 o b00000011 p b00000010 q b00000001 r b00000110 "! b00000101 #! b00000100 $! b00000011 %! b00000010 &! b00000001 '! b00000110 /! b00000101 0! b00000100 1! b00000011 2! b00000010 3! b00000001 4! b00000110 >! b00000101 ?! b00000100 @! b00000011 A! b00000010 B! b00000001 C! b00000110 K! b00000101 L! b00000100 M! b00000011 N! b00000010 O! b00000001 P! b00000110 r! b00000101 s! b00000100 t! b00000011 u! b00000010 v! b00000001 w! b00000110 !" b00000101 "" b00000100 #" b00000011 $" b00000010 %" b00000001 &" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 =" b00000110 H" b00000101 I" b00000100 J" b00000011 K" b00000010 L" b00000001 M" b00000110 U" b00000101 V" b00000100 W" b00000011 X" b00000010 Y" b00000001 Z" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 n" b00000110 |" b00000101 }" b00000100 ~" b00000011 !# b00000010 "# b00000001 ## b00000110 +# b00000101 ,# b00000100 -# b00000011 .# b00000010 /# b00000001 0# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 D# b00000110 N# b00000101 O# b00000100 P# b00000011 Q# b00000010 R# b00000001 S# b00000110 [# b00000101 \# b00000100 ]# b00000011 ^# b00000010 _# b00000001 `# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 t# b00000110 !$ b00000101 "$ b00000100 #$ b00000011 $$ b00000010 %$ b00000001 &$ b00000110 -$ b00000101 .$ b00000100 /$ b00000011 0$ b00000010 1$ b00000001 2$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 I$ b00000110 Q$ b00000101 R$ b00000100 S$ b00000011 T$ b00000010 U$ b00000001 V$ b00000110 ]$ b00000101 ^$ b00000100 _$ b00000011 `$ b00000010 a$ b00000001 b$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 y$ b00000110 #% b00000101 $% b00000100 %% b00000011 &% b00000010 '% b00000001 (% b00000110 /% b00000101 0% b00000100 1% b00000011 2% b00000010 3% b00000001 4% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 K% b00000110 S% b00000101 T% b00000100 U% b00000011 V% b00000010 W% b00000001 X% b00000110 _% b00000101 `% b00000100 a% b00000011 b% b00000010 c% b00000001 d% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 {% b00001101 _! b00001010 1 b00001101 & b00001101 ^! b00001101 `! b00001101 a! b00001101 h! b00001101 u" b00000101 * b00001101 ' b00001101 ( b00001101 9 b00001101 y b00001101 U! #85 0L% 0z$ 0J$ 0x# 0\! 0X! 0T! 0# #90 1# 1T! 1X! 1\! 1x# 1J$ 1z$ 1L% b00001110 U! b00001110 y b00001110 9 b00001110 ( b00001110 ' b00001000 * b00010000 u" b00010000 h! b00010000 a! b00010000 `! b00010000 ^! b00010000 & b00001011 1 b00001110 _! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 {% b00000000 d% b00000000 c% b00000000 b% b00000000 a% b00000000 `% b00000000 _% b00000000 X% b00000000 W% b00000000 V% b00000000 U% b00000000 T% b00000000 S% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 K% b00000000 4% b00000000 3% b00000000 2% b00000000 1% b00000000 0% b00000000 /% b00000000 (% b00000000 '% b00000000 &% b00000000 %% b00000000 $% b00000000 #% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y$ b00000000 b$ b00000000 a$ b00000000 `$ b00000000 _$ b00000000 ^$ b00000000 ]$ b00000000 V$ b00000000 U$ b00000000 T$ b00000000 S$ b00000000 R$ b00000000 Q$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 I$ b00000000 2$ b00000000 1$ b00000000 0$ b00000000 /$ b00000000 .$ b00000000 -$ b00000000 &$ b00000000 %$ b00000000 $$ b00000000 #$ b00000000 "$ b00000000 !$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t# b00000000 `# b00000000 _# b00000000 ^# b00000000 ]# b00000000 \# b00000000 [# b00000000 S# b00000000 R# b00000000 Q# b00000000 P# b00000000 O# b00000000 N# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 D# b00000000 0# b00000000 /# b00000000 .# b00000000 -# b00000000 ,# b00000000 +# b00000000 ## b00000000 "# b00000000 !# b00000000 ~" b00000000 }" b00000000 |" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n" b00000000 Z" b00000000 Y" b00000000 X" b00000000 W" b00000000 V" b00000000 U" b00000000 M" b00000000 L" b00000000 K" b00000000 J" b00000000 I" b00000000 H" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 =" b00000000 &" b00000000 %" b00000000 $" b00000000 #" b00000000 "" b00000000 !" b00000000 w! b00000000 v! b00000000 u! b00000000 t! b00000000 s! b00000000 r! b00000000 P! b00000000 O! b00000000 N! b00000000 M! b00000000 L! b00000000 K! b00000000 C! b00000000 B! b00000000 A! b00000000 @! b00000000 ?! b00000000 >! b00000000 4! b00000000 3! b00000000 2! b00000000 1! b00000000 0! b00000000 /! b00000000 '! b00000000 &! b00000000 %! b00000000 $! b00000000 #! b00000000 "! b00000000 r b00000000 q b00000000 p b00000000 o b00000000 n b00000000 m b00000000 e b00000000 d b00000000 c b00000000 b b00000000 a b00000000 ` b00000000 U b00000000 T b00000000 S b00000000 R b00000000 Q b00000000 P b00000000 H b00000000 G b00000000 F b00000000 E b00000000 D b00000000 C b00000000000000000000000000001001 + b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 > b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 ? b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 @ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 A b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 B b00000000000000000000000000001001 I b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 L b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 M b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 N b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 [ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 \ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ] b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ^ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _ b00000000000000000000000000001001 f b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 h b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 j b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 k b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 l b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 { b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 | b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 } b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 !! b00000000000000000000000000001001 (! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 *! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ,! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 -! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 .! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 9! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 :! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ;! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 b00000000000000000000000000001010 + b00000110 C b00000101 D b00000100 E b00000011 F b00000010 G b00000001 H b00000110 P b00000101 Q b00000100 R b00000011 S b00000010 T b00000001 U b00000110 ` b00000101 a b00000100 b b00000011 c b00000010 d b00000001 e b00000110 m b00000101 n b00000100 o b00000011 p b00000010 q b00000001 r b00000110 "! b00000101 #! b00000100 $! b00000011 %! b00000010 &! b00000001 '! b00000110 /! b00000101 0! b00000100 1! b00000011 2! b00000010 3! b00000001 4! b00000110 >! b00000101 ?! b00000100 @! b00000011 A! b00000010 B! b00000001 C! b00000110 K! b00000101 L! b00000100 M! b00000011 N! b00000010 O! b00000001 P! b00000110 r! b00000101 s! b00000100 t! b00000011 u! b00000010 v! b00000001 w! b00000110 !" b00000101 "" b00000100 #" b00000011 $" b00000010 %" b00000001 &" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 =" b00000110 H" b00000101 I" b00000100 J" b00000011 K" b00000010 L" b00000001 M" b00000110 U" b00000101 V" b00000100 W" b00000011 X" b00000010 Y" b00000001 Z" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 n" b00000110 |" b00000101 }" b00000100 ~" b00000011 !# b00000010 "# b00000001 ## b00000110 +# b00000101 ,# b00000100 -# b00000011 .# b00000010 /# b00000001 0# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 D# b00000110 N# b00000101 O# b00000100 P# b00000011 Q# b00000010 R# b00000001 S# b00000110 [# b00000101 \# b00000100 ]# b00000011 ^# b00000010 _# b00000001 `# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 t# b00000110 !$ b00000101 "$ b00000100 #$ b00000011 $$ b00000010 %$ b00000001 &$ b00000110 -$ b00000101 .$ b00000100 /$ b00000011 0$ b00000010 1$ b00000001 2$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 I$ b00000110 Q$ b00000101 R$ b00000100 S$ b00000011 T$ b00000010 U$ b00000001 V$ b00000110 ]$ b00000101 ^$ b00000100 _$ b00000011 `$ b00000010 a$ b00000001 b$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 y$ b00000110 #% b00000101 $% b00000100 %% b00000011 &% b00000010 '% b00000001 (% b00000110 /% b00000101 0% b00000100 1% b00000011 2% b00000010 3% b00000001 4% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 K% b00000110 S% b00000101 T% b00000100 U% b00000011 V% b00000010 W% b00000001 X% b00000110 _% b00000101 `% b00000100 a% b00000011 b% b00000010 c% b00000001 d% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 {% b00010010 & b00010010 ^! b00010010 `! b00010010 a! b00010010 h! b00010010 u" b00001010 * b00010000 ' b00010000 ( b00010000 9 b00010000 y b00010000 U! b00001110 ]! b00001110 [! b00001110 Z! b00001110 % b00001101 ) #105 0L% 0z$ 0J$ 0x# 0\! 0X! 0T! 0# #110 1# 1T! 1X! 1\! 1x# 1J$ 1z$ 1L% b00001110 ) b00001111 % b00001111 Z! b00001111 [! b00001111 ]! b00010011 U! b00010011 y b00010011 9 b00010011 ( b00010011 ' b00001011 * b00010011 u" b00010011 h! b00010011 a! b00010011 `! b00010011 ^! b00010011 & b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 {% b00000000 d% b00000000 c% b00000000 b% b00000000 a% b00000000 `% b00000000 _% b00000000 X% b00000000 W% b00000000 V% b00000000 U% b00000000 T% b00000000 S% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 K% b00000000 4% b00000000 3% b00000000 2% b00000000 1% b00000000 0% b00000000 /% b00000000 (% b00000000 '% b00000000 &% b00000000 %% b00000000 $% b00000000 #% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y$ b00000000 b$ b00000000 a$ b00000000 `$ b00000000 _$ b00000000 ^$ b00000000 ]$ b00000000 V$ b00000000 U$ b00000000 T$ b00000000 S$ b00000000 R$ b00000000 Q$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 I$ b00000000 2$ b00000000 1$ b00000000 0$ b00000000 /$ b00000000 .$ b00000000 -$ b00000000 &$ b00000000 %$ b00000000 $$ b00000000 #$ b00000000 "$ b00000000 !$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t# b00000000 `# b00000000 _# b00000000 ^# b00000000 ]# b00000000 \# b00000000 [# b00000000 S# b00000000 R# b00000000 Q# b00000000 P# b00000000 O# b00000000 N# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 D# b00000000 0# b00000000 /# b00000000 .# b00000000 -# b00000000 ,# b00000000 +# b00000000 ## b00000000 "# b00000000 !# b00000000 ~" b00000000 }" b00000000 |" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n" b00000000 Z" b00000000 Y" b00000000 X" b00000000 W" b00000000 V" b00000000 U" b00000000 M" b00000000 L" b00000000 K" b00000000 J" b00000000 I" b00000000 H" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 =" b00000000 &" b00000000 %" b00000000 $" b00000000 #" b00000000 "" b00000000 !" b00000000 w! b00000000 v! b00000000 u! b00000000 t! b00000000 s! b00000000 r! b00000000 P! b00000000 O! b00000000 N! b00000000 M! b00000000 L! b00000000 K! b00000000 C! b00000000 B! b00000000 A! b00000000 @! b00000000 ?! b00000000 >! b00000000 4! b00000000 3! b00000000 2! b00000000 1! b00000000 0! b00000000 /! b00000000 '! b00000000 &! b00000000 %! b00000000 $! b00000000 #! b00000000 "! b00000000 r b00000000 q b00000000 p b00000000 o b00000000 n b00000000 m b00000000 e b00000000 d b00000000 c b00000000 b b00000000 a b00000000 ` b00000000 U b00000000 T b00000000 S b00000000 R b00000000 Q b00000000 P b00000000 H b00000000 G b00000000 F b00000000 E b00000000 D b00000000 C b00000000000000000000000000001011 + b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 > b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 ? b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 @ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 A b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 B b00000000000000000000000000001011 I b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 L b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 M b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 N b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 [ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 \ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ] b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ^ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _ b00000000000000000000000000001011 f b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 h b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 j b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 k b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 l b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 { b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 | b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 } b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 !! b00000000000000000000000000001011 (! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 *! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ,! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 -! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 .! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 9! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 :! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ;! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 b00000000000000000000000000001100 + b00000110 C b00000101 D b00000100 E b00000011 F b00000010 G b00000001 H b00000110 P b00000101 Q b00000100 R b00000011 S b00000010 T b00000001 U b00000110 ` b00000101 a b00000100 b b00000011 c b00000010 d b00000001 e b00000110 m b00000101 n b00000100 o b00000011 p b00000010 q b00000001 r b00000110 "! b00000101 #! b00000100 $! b00000011 %! b00000010 &! b00000001 '! b00000110 /! b00000101 0! b00000100 1! b00000011 2! b00000010 3! b00000001 4! b00000110 >! b00000101 ?! b00000100 @! b00000011 A! b00000010 B! b00000001 C! b00000110 K! b00000101 L! b00000100 M! b00000011 N! b00000010 O! b00000001 P! b00000110 r! b00000101 s! b00000100 t! b00000011 u! b00000010 v! b00000001 w! b00000110 !" b00000101 "" b00000100 #" b00000011 $" b00000010 %" b00000001 &" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 =" b00000110 H" b00000101 I" b00000100 J" b00000011 K" b00000010 L" b00000001 M" b00000110 U" b00000101 V" b00000100 W" b00000011 X" b00000010 Y" b00000001 Z" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 n" b00000110 |" b00000101 }" b00000100 ~" b00000011 !# b00000010 "# b00000001 ## b00000110 +# b00000101 ,# b00000100 -# b00000011 .# b00000010 /# b00000001 0# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 D# b00000110 N# b00000101 O# b00000100 P# b00000011 Q# b00000010 R# b00000001 S# b00000110 [# b00000101 \# b00000100 ]# b00000011 ^# b00000010 _# b00000001 `# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 t# b00000110 !$ b00000101 "$ b00000100 #$ b00000011 $$ b00000010 %$ b00000001 &$ b00000110 -$ b00000101 .$ b00000100 /$ b00000011 0$ b00000010 1$ b00000001 2$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 I$ b00000110 Q$ b00000101 R$ b00000100 S$ b00000011 T$ b00000010 U$ b00000001 V$ b00000110 ]$ b00000101 ^$ b00000100 _$ b00000011 `$ b00000010 a$ b00000001 b$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 y$ b00000110 #% b00000101 $% b00000100 %% b00000011 &% b00000010 '% b00000001 (% b00000110 /% b00000101 0% b00000100 1% b00000011 2% b00000010 3% b00000001 4% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 K% b00000110 S% b00000101 T% b00000100 U% b00000011 V% b00000010 W% b00000001 X% b00000110 _% b00000101 `% b00000100 a% b00000011 b% b00000010 c% b00000001 d% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 {% b00010101 ' b00010101 ( b00010101 9 b00010101 y b00010101 U! b00010001 ]! b00010001 [! b00010001 Z! b00010001 % b00010000 ) b00010011 t" b00010011 g! b00001101 2 #125 0L% 0z$ 0J$ 0x# 0\! 0X! 0T! 0# #130 1# 1T! 1X! 1\! 1x# 1J$ 1z$ 1L% b00001110 2 b00010100 g! b00010100 t" b00010011 ) b00010100 % b00010100 Z! b00010100 [! b00010100 ]! b00010110 U! b00010110 y b00010110 9 b00010110 ( b00010110 ' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 {% b00000000 d% b00000000 c% b00000000 b% b00000000 a% b00000000 `% b00000000 _% b00000000 X% b00000000 W% b00000000 V% b00000000 U% b00000000 T% b00000000 S% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 K% b00000000 4% b00000000 3% b00000000 2% b00000000 1% b00000000 0% b00000000 /% b00000000 (% b00000000 '% b00000000 &% b00000000 %% b00000000 $% b00000000 #% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y$ b00000000 b$ b00000000 a$ b00000000 `$ b00000000 _$ b00000000 ^$ b00000000 ]$ b00000000 V$ b00000000 U$ b00000000 T$ b00000000 S$ b00000000 R$ b00000000 Q$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 I$ b00000000 2$ b00000000 1$ b00000000 0$ b00000000 /$ b00000000 .$ b00000000 -$ b00000000 &$ b00000000 %$ b00000000 $$ b00000000 #$ b00000000 "$ b00000000 !$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t# b00000000 `# b00000000 _# b00000000 ^# b00000000 ]# b00000000 \# b00000000 [# b00000000 S# b00000000 R# b00000000 Q# b00000000 P# b00000000 O# b00000000 N# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 D# 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b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 B b00000000000000000000000000001101 I b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 L b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 M b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 N b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 [ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 \ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ] b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ^ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _ b00000000000000000000000000001101 f b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 h b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 j b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 k b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 l b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 { b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 | b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 } b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 !! b00000000000000000000000000001101 (! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 *! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ,! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 -! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 .! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 9! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 :! 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b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _ b00000000000000000000000000010001 f b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 h b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 j b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 k b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 l b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 { b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 | b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 } b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 !! b00000000000000000000000000010001 (! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 *! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ,! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 -! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 .! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 9! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 :! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ;! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 #include #include #include VM_PREFIX_INCLUDE unsigned long long main_time = 0; double sc_time_stamp() { return (double)main_time; } int main(int argc, char** argv) { Verilated::debug(0); Verilated::traceEverOn(true); Verilated::commandArgs(argc, argv); std::unique_ptr top{new VM_PREFIX{"top"}}; std::unique_ptr tfp{new VerilatedVcdC}; top->trace(tfp.get(), 99); tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simno_trace_top.vcd"); top->clk = 0; while (main_time < 1900) { // Creates 2 files top->clk = !top->clk; top->eval(); tfp->dump((unsigned int)(main_time)); ++main_time; } tfp->close(); top->final(); tfp.reset(); top.reset(); printf("*-* All Finished *-*\n"); return 0; } verilator-5.042/test_regress/t/t_order_multidriven.py0000755000542200017500000000111415101701376023520 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(make_top_shell=False, make_main=False, v_flags2=["--trace-vcd --exe", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_param_named.v0000644000542200017500000000205615101701376022047 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); parameter PAR = 3; input clk; defparam m3.FROMDEFP = 19; m3 #(.P3(PAR), .P2(2)) m3(.clk(clk)); integer cyc=1; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==1) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module m3 #( parameter UNCH = 99, parameter P1 = 10, parameter P2 = 20, P3 = 30, parameter FROMDEFP = 11 ) (/*AUTOARG*/ // Inputs clk ); input clk; localparam LOC = 13; initial begin $display("%x %x %x",P1,P2,P3); end always @ (posedge clk) begin if (UNCH !== 99) $stop; if (P1 !== 10) $stop; if (P2 !== 2) $stop; if (P3 !== 3) $stop; if (FROMDEFP !== 19) $stop; end endmodule verilator-5.042/test_regress/t/t_inst_first.py0000755000542200017500000000102115101701376022144 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=[test.wno_unopthreads_for_few_cores]) test.execute() test.passes() verilator-5.042/test_regress/t/t_class_param_noinit_bad.out0000644000542200017500000000161215101701376024615 0ustar mahmoudyfreeshell%Error: t/t_class_param_noinit_bad.v:13:7: Class parameter without default value is never given value (IEEE 1800-2023 6.20.1): 'B' : ... note: In instance 't' 13 | Cls #(1) c; | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_class_param_noinit_bad.v:13:7: Class parameter type without default value is never given value (IEEE 1800-2023 6.20.1): 'T' : ... note: In instance 't' 13 | Cls #(1) c; | ^~~ %Error: t/t_class_param_noinit_bad.v:8:32: Parameter type without default value is never given value (IEEE 1800-2023 6.20.1): 'T' : ... note: In instance 't' 8 | class Cls #(int A, int B, type T); | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_dfg_synthesis_pre_inline.cpp0000644000542200017500000000246215101701376025176 0ustar mahmoudyfreeshell// // DESCRIPTION: Verilator: DFG optimizer equivalence testing // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 // #include #include #include #include #include void rngUpdate(uint64_t& x) { x ^= x << 13; x ^= x >> 7; x ^= x << 17; } int main(int, char**) { // Create contexts VerilatedContext ctx; // Create models Vref ref{&ctx}; Vopt opt{&ctx}; uint64_t rand_a = 0x5aef0c8dd70a4497; uint64_t rand_b = 0xf0c0a8dd75ae4497; uint64_t srand_a = 0x00fa8dcc7ae4957; uint64_t srand_b = 0x0fa8dc7ae3c9574; for (size_t n = 0; n < 200000; ++n) { // Update rngs rngUpdate(rand_a); rngUpdate(rand_b); rngUpdate(srand_a); rngUpdate(srand_b); // Assign inputs ref.rand_a = opt.rand_a = rand_a; ref.rand_b = opt.rand_b = rand_b; ref.srand_a = opt.srand_a = srand_a; ref.srand_b = opt.srand_b = srand_b; // Evaluate both models ref.eval(); opt.eval(); // Check equivalence #include "checks.h" // increment time ctx.timeInc(1); } std::cout << "*-* All Finished *-*\n"; } verilator-5.042/test_regress/t/t_param_avec.py0000755000542200017500000000073415101701376022070 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_opt_table_enum.py0000755000542200017500000000130215101701376022757 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--stats"]) if test.vlt_all: test.file_grep(test.stats, r'Optimizations, Tables created\s+(\d+)', 1) test.file_grep(test.stats, r'ConstPool, Tables emitted\s+(\d+)', 1) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_inst_missing_bad.py0000755000542200017500000000110515101701376023277 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["--lint-only --Wall -Wno-DECLFILENAME"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_constraint_assoc_arr_bad.v0000755000542200017500000000461615101701376024640 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by PlanV GmbH. // SPDX-License-Identifier: CC0-1.0 // Long String index associative array class AssocArrayString; rand int string_arr [string]; constraint c { string_arr["a_very_long_string"] == 65; } function new(); string_arr["a_very_long_string"] = 0; endfunction endclass class keyClass; int id; function new(); id = 3; endfunction endclass // Class index associative array class AssocArrayClass; rand bit [31:0] data [keyClass]; keyClass cl; // constraint c4 { foreach (data[i]) data[i] > 0;} Unsupported index type for an associative array in an iterative constraint. constraint c1 { data[cl] > 0;} // Illegal index expression of unpacked type in constraint. function new(); cl = new(); data[cl] = 32'd77; endfunction endclass typedef struct { int a; int b; } UnpackedIndexType; // Struct (unpacked) index associative array class AssocArrayUnpackedStruct; rand bit [31:0] data [UnpackedIndexType]; constraint c2 { foreach (data[i]) data[i] < 100; } // Illegal non-integral expression in random constraint. function new(); UnpackedIndexType idx; idx.a = 1; idx.b = 2; data[idx] = 32'd25; endfunction endclass // Array (unpacked) index associative array typedef logic [2:0] IndexArrayType[3]; class AssocArrayArrayIndex; rand bit [31:0] data [IndexArrayType]; constraint c3 { foreach (data[i]) data[i] > 0; } function new(); IndexArrayType idx; for (int j = 0; j < 4; j++) begin idx[j] = 3'd0; end data[idx] = 32'd75; endfunction endclass module t_constraint_assoc_arr_bad; AssocArrayString test_str; AssocArrayClass test_cls; AssocArrayUnpackedStruct test_unp_struct; AssocArrayArrayIndex test_unp_arr; int success = 0; initial begin test_str = new(); test_cls = new(); test_unp_struct = new(); test_unp_arr = new(); success += test_str.randomize(); success += test_cls.randomize(); success += test_unp_struct.randomize(); success += test_unp_arr.randomize(); if(success != 4) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_unbounded.v0000644000542200017500000000121015101701376021555 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(); localparam UNB = $; localparam int UNB2 = $; localparam SIX = 6; initial begin if ($bits($isunbounded(0)) !== 1) $stop; if ($isunbounded(0) !== 1'b0) $stop; if ($isunbounded(SIX) !== 0) $stop; if ($isunbounded($) !== 1) $stop; if ($isunbounded(UNB) !== 1) $stop; if ($isunbounded(UNB2) !== 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_randstate_obj.v0000644000542200017500000000134415101701376022421 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls; rand int length; endclass module t; int rand_result, v1, v2; string s; initial begin Cls c; c = new; s = c.get_randstate(); rand_result = c.randomize(); if (rand_result != 1) $stop; v1 = c.length; c.set_randstate(s); rand_result = c.randomize(); if (rand_result != 1) $stop; v2 = c.length; `ifdef VERILATOR // About half of the other simulators fail at this if (v1 != v2) $stop; `endif $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_dedupe_seq_logic.v0000644000542200017500000000532615101701376023101 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Dedupe optimization test. // // This file ONLY is placed into the Public Domain, for any use, // without warranty. // SPDX-License-Identifier: CC0-1.0 // Contributed 2012 by Varun Koyyalagunta, Centaur Technology. // // Test consists of the follow logic tree, which has many obvious // places for dedupe: /* output + --------------/ \-------------- / \ + + ----/ \----- ----/ \---- / + / + + / \ + / \ -/ \- a b -/ \- a b / \ / \ + + + + / \ / \ / \ / \ a b c d a b c d */ module t(sum,a,b,c,d,clk); output sum; input a,b,c,d,clk; wire left,right; add add(sum,left,right,clk); l l(left,a,b,c,d,clk); r r(right,a,b,c,d,clk); endmodule module l(sum,a,b,c,d,clk); output sum; input a,b,c,d,clk; wire left, right; add add(sum,left,right,clk); ll ll(left,a,b,c,d,clk); lr lr(right,a,b,c,d,clk); endmodule module ll(sum,a,b,c,d,clk); output sum; input a,b,c,d,clk; wire left, right; add add(sum,left,right,clk); lll lll(left,a,b,c,d,clk); llr llr(right,a,b,c,d,clk); endmodule module lll(sum,a,b,c,d,clk); output sum; input a,b,c,d,clk; add add(sum,a,b,clk); endmodule module llr(sum,a,b,c,d,clk); output sum; input a,b,c,d,clk; add add(sum,c,d,clk); endmodule module lr(sum,a,b,c,d,clk); output sum; input a,b,c,d,clk; add add(sum,a,b,clk); endmodule module r(sum,a,b,c,d,clk); output sum; input a,b,c,d,clk; wire left, right; add add(sum,left,right,clk); rl rl(left,a,b,c,d,clk); rr rr(right,a,b,c,d,clk); endmodule module rr(sum,a,b,c,d,clk); output sum; input a,b,c,d,clk; add add(sum,a,b,clk); endmodule module rl(sum,a,b,c,d,clk); output sum; input a,b,c,d,clk; wire left, right; add add(sum,left,right,clk); rll rll(left,a,b,c,d,clk); rlr rlr(right,a,b,c,d,clk); endmodule module rll(sum,a,b,c,d,clk); output sum; input a,b,c,d,clk; add2 add(sum,a,b,clk); endmodule module rlr(sum,a,b,c,d,clk); output sum; input a,b,c,d,clk; add2 add(sum,c,d,clk); endmodule module add(sum,x,y,clk); output reg sum; input x,y,clk; reg t1,t2; always @(posedge clk) begin sum <= x + y; end endmodule module add2(sum,x,y,clk); output reg sum; input x,y,clk; reg t1,t2; always @(posedge clk) begin sum <= x + y; end endmodule verilator-5.042/test_regress/t/t_interface_mismodport_bad.py0000755000542200017500000000076615101701376025022 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_package_export_bad2.py0000755000542200017500000000076615101701376023663 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_mem_slice_conc_bad.out0000644000542200017500000000161015101701376023705 0ustar mahmoudyfreeshell%Error-PROCASSWIRE: t/t_mem_slice_conc_bad.v:46:10: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'rst' : ... note: In instance 't' 46 | rst <= 1'b0; | ^~~ ... For error description see https://verilator.org/warn/PROCASSWIRE?v=latest %Error-PROCASSWIRE: t/t_mem_slice_conc_bad.v:50:10: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'rst' : ... note: In instance 't' 50 | rst <= 1'b1; | ^~~ %Error-PROCASSWIRE: t/t_mem_slice_conc_bad.v:53:10: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'rst' : ... note: In instance 't' 53 | rst <= 1'b0; | ^~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_trace_abort.out0000644000542200017500000000062515101701376022432 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $var wire 1 # clk $end $scope module t $end $var wire 1 # clk $end $var wire 3 $ cyc [2:0] $end $upscope $end $upscope $end $enddefinitions $end #0 0# b000 $ #10 1# b001 $ #15 0# #20 1# b010 $ #25 0# #30 1# b011 $ #35 0# #40 1# b100 $ #45 0# #50 1# b101 $ #55 0# #60 1# b110 $ #65 0# #70 1# b111 $ #75 0# verilator-5.042/test_regress/t/t_param_pattern2.py0000755000542200017500000000073415101701376022711 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_assert_ctl_concurrent.v0000644000542200017500000000150415101701376024205 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t; bit clock = 1'b0; bit reset = 1'b0; initial begin $assertkill; #10 reset = 1'b1; $display("%t: deassert reset %d", $time, reset); #40 $asserton; reset = 1'b0; $display("%t: deassert reset %d", $time, reset); #200 $display("%t: finish", $time); $write("*-* All Finished *-*\n"); $finish; end always #10 clock = ~clock; reg r = 1'b0; always @(posedge clock) if (reset) r <= 1'b1; assert_test: assert property (@(posedge clock) (reset | r)) else $error("%t: assertion triggered", $time); endmodule verilator-5.042/test_regress/t/t_tri_top_en_out_bad.py0000755000542200017500000000144315101701376023627 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(make_top_shell=False, make_main=1, verilator_make_gmake=True, verilator_flags2=["--exe --pins-inout-enables --no-timing -Wno-STMTDLY"]) test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + ".h", r'internal_sub_io__out') test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + ".h", r'internal_sub_io__en') test.passes() verilator-5.042/test_regress/t/t_dpi_qw_c.cpp0000644000542200017500000000274615101701376021713 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // Copyright 2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 //************************************************************************* #include "svdpi.h" #include #include //====================================================================== #ifdef VERILATOR #include "Vt_dpi_qw__Dpi.h" #else extern "C" { extern void set_value(const svBitVecVal* v); extern void poke_value(int i); } #endif //====================================================================== // Called from our Verilog code to run the tests void poke_value(int i) { printf("poke_value(%d)\n", i); const char* const scopeNamep = svGetNameFromScope(svGetScope()); printf("svGetNameFromScope=\"%s\"\n", scopeNamep); // clang-format off #ifdef VERILATOR static int didDump = 0; if (didDump++ == 0) { # ifdef TEST_VERBOSE Verilated::scopesDump(); # endif } #endif // clang-format on const svScope scope = svGetScopeFromName("top.t.a"); if (scope == NULL) { printf("%%Error: null scope for top.t.a\n"); return; } svSetScope(scope); svBitVecVal val[2]; val[0] = i; val[1] = 0; set_value(val); } verilator-5.042/test_regress/t/t_class_static_default_arg.py0000755000542200017500000000073415101701376025003 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_timing_nested_assignment_on_lhs.v0000644000542200017500000000143315101701376026224 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class uvm_object_wrapper; function string get_type_name; return "abcd"; endfunction endclass class uvm_default_factory; int m_type_names[string]; virtual function int register; uvm_object_wrapper obj; string name; m_type_names[(name = obj.get_type_name())] = 1; return m_type_names[name]; endfunction endclass module t; initial begin uvm_default_factory u = new; if (u.register() != 1) $stop; #1; // Needed only visit assignments in V3Timing $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_flag_only_bad.py0000755000542200017500000000123515101701376022547 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_flag_main.v" test.lint(verilator_flags2=[ "-Wno-DEPRECATED --binary -E --dpi-hdr-only --lint-only --xml-only --json-only -Wall" ], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dump_json.py0000755000542200017500000000122715101701376021766 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_dump.v" test.lint(v_flags=["--dump-tree-json --no-json-edit-nums"]) test.files_identical(test.obj_dir + "/Vt_dump_json_002_cellsort.tree.json", test.golden_filename, 'logfile') test.passes() verilator-5.042/test_regress/t/t_struct_notfound_bad.v0000644000542200017500000000057215101701376023652 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; typedef struct packed { bit m; } struct_t; struct_t s; initial begin s.nfmember = 0; // Member not found $finish; end endmodule verilator-5.042/test_regress/t/t_param_implicit_bad.v0000644000542200017500000000112415101701376023376 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // IEEE parameter_port_declaration has data_type but not data_type_or_implicit module sub1 #([7:0] PAR1 = 1); // <--- Error: requires 'parameter' endmodule module sub2 #(parameter real PAR1 = 1.0, signed PAR2 = 2); endmodule module sub3 #(localparam real PAR1 = 1.0, signed PAR2 = 2); endmodule module t; sub1 sub1(); sub2 sub2(); sub3 sub3(); initial $stop; endmodule verilator-5.042/test_regress/t/t_fuzz_eqne_bad.py0000755000542200017500000000076615101701376022613 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_flag_xinitial_unique.v0000644000542200017500000000071215101701376024000 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs value, value2 ); output reg [63:0] value; output wire [64:0] value2; assign value2 = {8'bx, 57'h12}; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_randomize_complex_arrays.py0000755000542200017500000000104615101701376025067 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_only.v0000644000542200017500000000042215101701376021605 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (); initial begin $stop; end endmodule verilator-5.042/test_regress/t/t_select_param.py0000755000542200017500000000073415101701376022431 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_randomize_from_randomized_class.v0000644000542200017500000000105615101701376026216 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class A; rand int j; endclass class B; A a; rand int i; function new(); a = new; i = 7; endfunction task r(); if (a.randomize() with { j == i; } == 0) $stop; endtask endclass module t; initial begin B b = new; b.r(); if (b.a.j != 7) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_debug_inputs_a.v0000644000542200017500000000044315101701376022571 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Dotted reference that uses another dotted reference // as the select expression // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t_debug_inputs_a; endmodule verilator-5.042/test_regress/t/t_interface_bind_public.v0000644000542200017500000000567415101701376024106 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2018 by Alex Solomatnikov. // SPDX-License-Identifier: CC0-1.0 interface hex2ram_if ( input bit trigger ); string instance_path = $sformatf("%m"); string testfile = ""; bit has_testfile = |($value$plusargs("testfile=%s", testfile)); bit armed = 1'b1; bit armed_trigger; initial begin $display("successfully bound hex2ram_if to %s", instance_path); armed = has_testfile && 1'b1; end assign armed_trigger = armed && trigger; always @(posedge armed_trigger) begin $display("%m(%0t): saw deassertion of reset", $time); end endinterface : hex2ram_if module t ( clk ); input clk; bit reset; wire success; SimpleTestHarness testHarness ( .clk(clk), .reset(reset), .io_success(success) ); integer cyc = 0; always @ (posedge clk) begin cyc = cyc + 1; if (cyc<10) begin reset <= '0; end else if (cyc<20) begin reset <= '1; end else if (cyc<30) begin reset <= '0; end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule bind testharness_ext hex2ram_if i_hex2ram (.trigger(!t.reset)); module testharness_ext ( input W0_clk, input [24:0] W0_addr, input W0_en, input [127:0] W0_data, input [0:0] W0_mask, input R0_clk, input [24:0] R0_addr, input R0_en, output [127:0] R0_data ); reg [24:0] reg_R0_addr; wire [127:0] R0_rdata_mask; reg [127:0] ram [33554431:0]; wire [127:0] W0_wdata_mask; always @(posedge R0_clk) if (R0_en) reg_R0_addr <= R0_addr; always @(posedge W0_clk) if (W0_en) begin if (W0_mask[0]) ram[W0_addr] <= W0_data ^ W0_wdata_mask; end assign R0_data = ram[reg_R0_addr] ^ R0_rdata_mask;; assign R0_rdata_mask = 0; assign W0_wdata_mask = 0; endmodule module SimpleTestHarness ( input clk, input reset, output io_success); wire [24:0] testharness_ext_R0_addr; wire testharness_ext_R0_en; wire testharness_ext_R0_clk; wire [127:0] testharness_ext_R0_data; wire [24:0] testharness_ext_W0_addr; wire testharness_ext_W0_en; wire testharness_ext_W0_clk; wire [127:0] testharness_ext_W0_data; wire [0:0] testharness_ext_W0_mask; testharness_ext testharness_ext ( .R0_addr(testharness_ext_R0_addr), .R0_en(testharness_ext_R0_en), .R0_clk(testharness_ext_R0_clk), .R0_data(testharness_ext_R0_data), .W0_addr(testharness_ext_W0_addr), .W0_en(testharness_ext_W0_en), .W0_clk(testharness_ext_W0_clk), .W0_data(testharness_ext_W0_data), .W0_mask(testharness_ext_W0_mask) ); endmodule verilator-5.042/test_regress/t/t_math_cv_concat.v0000644000542200017500000000167115101701376022555 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0h\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t; // Issue #5972 reg clk; reg signed [28:28] in1; reg signed [21:8] reg_10; // verilator lint_off WIDTHEXPAND always @(negedge clk) begin // Issue #5972 reg_10[14:8] <= {1'b1, ~((in1[28:28] & ~(in1[28:28])))}; end initial begin clk = 1; in1 = 1'b0; reg_10 = '0; #2; clk = 0; #2; `checkh(reg_10, 3); in1 = 1'b1; clk = 1; #2; clk = 0; #2; `checkh(reg_10, 3); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_sys_fmonitor.py0000755000542200017500000000104315101701376022517 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.files_identical(test.obj_dir + "/open.log", test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_vpi_module_dpi.py0000755000542200017500000000143615101701376022771 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_vpi_module.v" test.pli_filename = "t/t_vpi_module.cpp" test.vm_prefix = "Vt_vpi_module" test.compile(make_top_shell=False, make_main=False, make_pli=True, iv_flags2=["-g2005-sv"], verilator_flags2=["--exe --vpi --no-l2name", test.pli_filename]) test.execute(use_libvpi=True) test.passes() verilator-5.042/test_regress/t/t_preproc_elsif_bad.out0000644000542200017500000000117215101701376023605 0ustar mahmoudyfreeshell%Error: t/t_preproc_elsif_bad.v:9:8: `elsif with no matching `if 9 | `elsif A | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_preproc_elsif_bad.v:10:1: `endif with no matching `if 10 | `endif | ^~~~~~ %Error: t/t_preproc_elsif_bad.v:12:1: `else with no matching `if 12 | `else | ^~~~~ %Error: t/t_preproc_elsif_bad.v:13:1: `endif with no matching `if 13 | `endif | ^~~~~~ %Error: t/t_preproc_elsif_bad.v:15:8: Expecting `error string. Found: INCLUDE 15 | `error `include | ^~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_module_input_default_value_3_bad.py0000755000542200017500000000076615101701376026433 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_assign_bad.out0000644000542200017500000000373015101701376023424 0ustar mahmoudyfreeshell%Error: t/t_class_assign_bad.v:28:9: Assign RHS expects a CLASSREFDTYPE 'Cls', got BASICDTYPE 'logic' : ... note: In instance 't' 28 | c = 0; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_class_assign_bad.v:29:9: Assign RHS expects a CLASSREFDTYPE 'Cls', got BASICDTYPE 'logic' : ... note: In instance 't' 29 | c = 1; | ^ %Error: t/t_class_assign_bad.v:30:9: Assign RHS expects a CLASSREFDTYPE 'Cls', got CLASSREFDTYPE 'Cls2' : ... note: In instance 't' 30 | c = c2; | ^ %Error: t/t_class_assign_bad.v:31:13: Assign RHS expects a CLASSREFDTYPE 'ClsExt', got CLASSREFDTYPE 'Cls' : ... note: In instance 't' 31 | c_ext = c; | ^ %Error: t/t_class_assign_bad.v:32:11: Assign RHS expects a CLASSREFDTYPE 'Cls2', got CLASSREFDTYPE 'Cls' : ... note: In instance 't' 32 | ct2 = c; | ^ %Error: t/t_class_assign_bad.v:34:7: Function Argument expects a CLASSREFDTYPE 'Cls', got BASICDTYPE 'logic' : ... note: In instance 't' 34 | t(0); | ^ %Error: t/t_class_assign_bad.v:35:7: Function Argument expects a CLASSREFDTYPE 'Cls', got BASICDTYPE 'logic' : ... note: In instance 't' 35 | t(1); | ^ %Error: t/t_class_assign_bad.v:36:7: Function Argument expects a CLASSREFDTYPE 'Cls', got CLASSREFDTYPE 'Cls2' : ... note: In instance 't' 36 | t(c2); | ^ %Error: t/t_class_assign_bad.v:37:7: Function Argument expects a CLASSREFDTYPE 'ClsExt', got CLASSREFDTYPE 'Cls' : ... note: In instance 't' 37 | f(c); | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_interface_virtual_controlflow.py0000755000542200017500000000105215101701376026122 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary -fno-reorder"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dpi_open_oob_bad.out0000644000542200017500000000457415101701376023416 0ustar mahmoudyfreeshelldpii_nullptr: dpii_int_u3: %Warning: DPI svOpenArrayHandle function index 3 out of bounds; 1 outside [4:-4]. %Warning: DPI svOpenArrayHandle function index 2 out of bounds; 20 outside [-3:3]. %Warning: DPI svOpenArrayHandle function index 1 out of bounds; 10 outside [2:-2]. %Warning: DPI svOpenArrayHandle function called on 3 dimensional array using 1 dimensional function. dpii_real_u1: %Warning: DPI svOpenArrayHandle function unsupported datatype (8). %Warning: DPI svOpenArrayHandle function unsupported datatype (8). %Warning: DPI svOpenArrayHandle function unsupported datatype (8). %Warning: DPI svOpenArrayHandle function unsupported datatype (8). %Warning: DPI svOpenArrayHandle function unsupported datatype (8). %Warning: DPI svOpenArrayHandle function unsupported datatype (8). %Warning: DPI svOpenArrayHandle function unsupported datatype (8). %Warning: DPI svOpenArrayHandle function unsupported datatype (8). %Warning: DPI svOpenArrayHandle function unsupported datatype (8). %Warning: DPI svOpenArrayHandle function unsupported datatype (8). %Warning: DPI svOpenArrayHandle function unsupported datatype (8). %Warning: DPI svOpenArrayHandle function unsupported datatype (8). %Warning: DPI svOpenArrayHandle function unsupported datatype (8). %Warning: DPI svOpenArrayHandle function unsupported datatype (8). %Warning: DPI svOpenArrayHandle function unsupported datatype (8). %Warning: DPI svOpenArrayHandle function unsupported datatype (8). dpii_bit_u6: %Warning: DPI svOpenArrayHandle function called on 6 dimensional array using -1 dimensional function. %Warning: DPI svOpenArrayHandle function called on 6 dimensional array using -1 dimensional function. %Warning: DPI svOpenArrayHandle function called on 6 dimensional array using -1 dimensional function. %Warning: DPI svOpenArrayHandle function called on 6 dimensional array using -1 dimensional function. %Warning: DPI svOpenArrayHandle function called on 6 dimensional array using -1 dimensional function. %Warning: DPI svOpenArrayHandle function called on 6 dimensional array using -1 dimensional function. %Warning: DPI svOpenArrayHandle function called on 6 dimensional array using -1 dimensional function. %Warning: DPI svOpenArrayHandle function called on 6 dimensional array using -1 dimensional function. dpii_real_u6: %Warning: DPI svOpenArrayHandle function called on 6 dimensional array using -1 dimensional function. *-* All Finished *-* verilator-5.042/test_regress/t/t_altera_lpm_rom.py0000755000542200017500000000111115101701376022755 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) test.compile(verilator_flags2=["--top-module", module]) test.passes() verilator-5.042/test_regress/t/t_lint_realcvt_bad.out0000644000542200017500000000517415101701376023445 0ustar mahmoudyfreeshell%Warning-REALCVT: t/t_lint_realcvt_bad.v:12:17: Implicit conversion of real to integer 12 | time t_bad1 = 9.001ns; | ^~~~~~~ ... For warning description see https://verilator.org/warn/REALCVT?v=latest ... Use "/* verilator lint_off REALCVT */" and lint_on around source to disable this message. %Warning-REALCVT: t/t_lint_realcvt_bad.v:13:17: Implicit conversion of real to integer 13 | time t_bad2 = 9.999ns; | ^~~~~~~ %Warning-REALCVT: t/t_lint_realcvt_bad.v:17:17: Implicit conversion of real to integer 17 | time t_bad3 = 9ps; | ^~~ %Warning-REALCVT: t/t_lint_realcvt_bad.v:23:21: Implicit conversion of real to integer 23 | integer i_bad21 = 23.1; | ^~~~ %Error: t/t_lint_realcvt_bad.v:27:17: Expected integral input to SIGNED : ... note: In instance 'sub' 27 | i = $signed(1.0); | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_lint_realcvt_bad.v:28:19: Expected integral input to UNSIGNED : ... note: In instance 'sub' 28 | i = $unsigned(1.0); | ^~~ %Error: t/t_lint_realcvt_bad.v:29:10: Expected integral input to CONCAT : ... note: In instance 'sub' 29 | i = {1.2, 1.3}; | ^~~ %Error: t/t_lint_realcvt_bad.v:29:15: Expected integral input to CONCAT : ... note: In instance 'sub' 29 | i = {1.2, 1.3}; | ^~~ %Warning-WIDTHTRUNC: t/t_lint_realcvt_bad.v:29:7: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's REPLICATE generates 64 bits. : ... note: In instance 'sub' 29 | i = {1.2, 1.3}; | ^ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: t/t_lint_realcvt_bad.v:30:12: Expected integral input to REPLICATE : ... note: In instance 'sub' 30 | i = {6{1.2}}; | ^~~ %Warning-WIDTHTRUNC: t/t_lint_realcvt_bad.v:30:7: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's REPLICATE generates 192 bits. : ... note: In instance 'sub' 30 | i = {6{1.2}}; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_interface_generic_bad.out0000755000542200017500000000166015101701376024412 0ustar mahmoudyfreeshell%Warning-PINMISSING: t/t_interface_generic_bad.v:26:17: Instance has missing pin: 'b' 26 | GenericModule genericModule (inf_inst); | ^~~~~~~~~~~~~ t/t_interface_generic_bad.v:15:46: ... Location of port declaration 15 | module GenericModule (interface a, interface b); | ^ ... For warning description see https://verilator.org/warn/PINMISSING?v=latest ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message. %Error: t/t_interface_generic_bad.v:15:46: Interface port 'b' is not connected to interface/modport pin expression 15 | module GenericModule (interface a, interface b); | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_lint_iface_topmodule3.v0000644000542200017500000000264015101701376024052 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Josh Redford. // SPDX-License-Identifier: CC0-1.0 interface my_if #( parameter integer DW = 8 ) (input clk); localparam DW_LOCAL = DW; logic valid; logic [DW-1:0] data; modport slave_mp ( input valid, input data ); modport master_mp ( output valid, output data ); function automatic integer width(); return $bits(data); endfunction generate if (DW < 4) begin: dw_lt_4_G function automatic integer min_width(); return 4; endfunction end else begin: dw_ge_4_G function automatic integer min_width(); return 8; endfunction end endgenerate endinterface module t ( input wire clk, my_if in_if, my_if out_if ); assign out_if.valid = in_if.valid; assign out_if.data = in_if.data; my_if my_i (.clk(clk)); initial begin $display(in_if.DW_LOCAL); $display(in_if.width()); $display(in_if.dw_ge_4_G.min_width()); $display(out_if.DW_LOCAL); $display(out_if.width()); $display(out_if.dw_ge_4_G.min_width()); end endmodule verilator-5.042/test_regress/t/t_var_suggest_bad.out0000644000542200017500000000103015101701376023273 0ustar mahmoudyfreeshell%Error: t/t_var_suggest_bad.v:13:11: Can't find definition of variable: 'foobat' : ... Suggested alternative: 'foobar' 13 | if (foobat) $stop; | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_var_suggest_bad.v:14:7: Can't find definition of task/function: 'boobat' : ... Suggested alternative: 'boobar' 14 | boobat; | ^~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_lint_latch_bad.out0000644000542200017500000000233315101701376023072 0ustar mahmoudyfreeshell%Warning-COMBDLY: t/t_lint_latch_bad.v:18:10: Non-blocking assignment '<=' in combinational logic process : ... This will be executed as a blocking assignment '='! 18 | bl <= a; | ^~ ... For warning description see https://verilator.org/warn/COMBDLY?v=latest ... Use "/* verilator lint_off COMBDLY */" and lint_on around source to disable this message. *** See https://verilator.org/warn/COMBDLY?v=latest before disabling this, else you may end up with different sim results. %Warning-NOLATCH: t/t_lint_latch_bad.v:17:4: No latches detected in always_latch block 17 | always_latch begin | ^~~~~~~~~~~~ ... For warning description see https://verilator.org/warn/NOLATCH?v=latest ... Use "/* verilator lint_off NOLATCH */" and lint_on around source to disable this message. %Warning-COMBDLY: t/t_lint_latch_bad.v:25:10: Non-blocking assignment '<=' in combinational logic process : ... This will be executed as a blocking assignment '='! 25 | bc <= a; | ^~ %Error: Exiting due to verilator-5.042/test_regress/t/t_enum_base.py0000755000542200017500000000073415101701376021730 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_display_qqq.out0000644000542200017500000000007015101701376022466 0ustar mahmoudyfreeshellFirst "quoted" second third fourth *-* All Finished *-* verilator-5.042/test_regress/t/t_property_unsup.out0000644000542200017500000001767515101701376023300 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_property_unsup.v:62:41: Unsupported: eventually[] (in property expression) 62 | assert property (counter == 1 implies eventually[1: 2] counter == 3); | ^~~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_property_unsup.v:77:20: Unsupported: eventually[] (in property expression) 77 | assert property (eventually[0: 2] counter == 3); | ^~~~~~~~~~ %Error-UNSUPPORTED: t/t_property_unsup.v:87:21: Unsupported: always (in property expression) 87 | assert property ((always a) implies (always a)); | ^~~~~~ %Error-UNSUPPORTED: t/t_property_unsup.v:87:40: Unsupported: always (in property expression) 87 | assert property ((always a) implies (always a)); | ^~~~~~ %Error-UNSUPPORTED: t/t_property_unsup.v:89:26: Unsupported: always (in property expression) 89 | assert property ((a or(always b)) implies (a or(always b))); | ^~~~~~ %Error-UNSUPPORTED: t/t_property_unsup.v:89:23: Unsupported: or (in sequence expression) 89 | assert property ((a or(always b)) implies (a or(always b))); | ^~ %Error-UNSUPPORTED: t/t_property_unsup.v:89:51: Unsupported: always (in property expression) 89 | assert property ((a or(always b)) implies (a or(always b))); | ^~~~~~ %Error-UNSUPPORTED: t/t_property_unsup.v:89:48: Unsupported: or (in sequence expression) 89 | assert property ((a or(always b)) implies (a or(always b))); | ^~ %Error-UNSUPPORTED: t/t_property_unsup.v:91:21: Unsupported: eventually[] (in property expression) 91 | assert property ((eventually[0: 1] a) implies (eventually[0: 1] a)); | ^~~~~~~~~~ %Error-UNSUPPORTED: t/t_property_unsup.v:91:50: Unsupported: eventually[] (in property expression) 91 | assert property ((eventually[0: 1] a) implies (eventually[0: 1] a)); | ^~~~~~~~~~ %Error-UNSUPPORTED: t/t_property_unsup.v:93:21: Unsupported: s_eventually (in property expression) 93 | assert property ((s_eventually a) implies (s_eventually a)); | ^~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_property_unsup.v:93:46: Unsupported: s_eventually (in property expression) 93 | assert property ((s_eventually a) implies (s_eventually a)); | ^~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_property_unsup.v:95:23: Unsupported: until (in property expression) 95 | assert property ((a until b) implies (a until b)); | ^~~~~ %Error-UNSUPPORTED: t/t_property_unsup.v:95:43: Unsupported: until (in property expression) 95 | assert property ((a until b) implies (a until b)); | ^~~~~ %Error-UNSUPPORTED: t/t_property_unsup.v:97:23: Unsupported: s_until (in property expression) 97 | assert property ((a s_until b) implies (a s_until b)); | ^~~~~~~ %Error-UNSUPPORTED: t/t_property_unsup.v:97:45: Unsupported: s_until (in property expression) 97 | assert property ((a s_until b) implies (a s_until b)); | ^~~~~~~ %Error-UNSUPPORTED: t/t_property_unsup.v:99:23: Unsupported: until_with (in property expression) 99 | assert property ((a until_with b) implies (a until_with b)); | ^~~~~~~~~~ %Error-UNSUPPORTED: t/t_property_unsup.v:99:48: Unsupported: until_with (in property expression) 99 | assert property ((a until_with b) implies (a until_with b)); | ^~~~~~~~~~ %Error-UNSUPPORTED: t/t_property_unsup.v:101:23: Unsupported: s_until_with (in property expression) 101 | assert property ((a s_until_with b) implies (a s_until_with b)); | ^~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_property_unsup.v:101:50: Unsupported: s_until_with (in property expression) 101 | assert property ((a s_until_with b) implies (a s_until_with b)); | ^~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_property_unsup.v:105:23: Unsupported: #-# (in property expression) 105 | assert property ((a #-# b) implies (a #-# b)); | ^~~ %Error-UNSUPPORTED: t/t_property_unsup.v:105:41: Unsupported: #-# (in property expression) 105 | assert property ((a #-# b) implies (a #-# b)); | ^~~ %Error-UNSUPPORTED: t/t_property_unsup.v:115:21: Unsupported: always (in property expression) 115 | assert property ((always a) iff (always a)); | ^~~~~~ %Error-UNSUPPORTED: t/t_property_unsup.v:115:36: Unsupported: always (in property expression) 115 | assert property ((always a) iff (always a)); | ^~~~~~ %Error-UNSUPPORTED: t/t_property_unsup.v:117:21: Unsupported: eventually[] (in property expression) 117 | assert property ((eventually[0: 1] a) iff (eventually[0: 1] a)); | ^~~~~~~~~~ %Error-UNSUPPORTED: t/t_property_unsup.v:117:46: Unsupported: eventually[] (in property expression) 117 | assert property ((eventually[0: 1] a) iff (eventually[0: 1] a)); | ^~~~~~~~~~ %Error-UNSUPPORTED: t/t_property_unsup.v:119:21: Unsupported: s_eventually (in property expression) 119 | assert property ((s_eventually a) iff (s_eventually a)); | ^~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_property_unsup.v:119:42: Unsupported: s_eventually (in property expression) 119 | assert property ((s_eventually a) iff (s_eventually a)); | ^~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_property_unsup.v:121:23: Unsupported: until (in property expression) 121 | assert property ((a until b) iff (a until b)); | ^~~~~ %Error-UNSUPPORTED: t/t_property_unsup.v:121:39: Unsupported: until (in property expression) 121 | assert property ((a until b) iff (a until b)); | ^~~~~ %Error-UNSUPPORTED: t/t_property_unsup.v:123:23: Unsupported: s_until (in property expression) 123 | assert property ((a s_until b) iff (a s_until b)); | ^~~~~~~ %Error-UNSUPPORTED: t/t_property_unsup.v:123:41: Unsupported: s_until (in property expression) 123 | assert property ((a s_until b) iff (a s_until b)); | ^~~~~~~ %Error-UNSUPPORTED: t/t_property_unsup.v:125:23: Unsupported: until_with (in property expression) 125 | assert property ((a until_with b) iff (a until_with b)); | ^~~~~~~~~~ %Error-UNSUPPORTED: t/t_property_unsup.v:125:44: Unsupported: until_with (in property expression) 125 | assert property ((a until_with b) iff (a until_with b)); | ^~~~~~~~~~ %Error-UNSUPPORTED: t/t_property_unsup.v:127:23: Unsupported: s_until_with (in property expression) 127 | assert property ((a s_until_with b) iff (a s_until_with b)); | ^~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_property_unsup.v:127:46: Unsupported: s_until_with (in property expression) 127 | assert property ((a s_until_with b) iff (a s_until_with b)); | ^~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_property_unsup.v:131:23: Unsupported: #-# (in property expression) 131 | assert property ((a #-# b) iff (a #-# b)); | ^~~ %Error-UNSUPPORTED: t/t_property_unsup.v:131:37: Unsupported: #-# (in property expression) 131 | assert property ((a #-# b) iff (a #-# b)); | ^~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_time_vpi_100s10ms.out0000644000542200017500000000200715101701376023221 0ustar mahmoudyfreeshell:: In top.t Time scale of t is 100s / 10ms [100000000] time%0d=10000 123%0t=1230000 dig%0t=0 dig%0d=0 rdig%0t=543 rdig%0f=0.054321 acc%0t=123456789012345678900000 acc%0d=12345678901234567890 [1000000000000000.000000ns] time%0d=10000 123%0t=12300000000000.000000ns dig%0t=0.000000ns dig%0d=0 rdig%0t=5432109876.543210ns rdig%0f=0.054321 acc%0t=1234567890123456789000000000000.000000ns acc%0d=12345678901234567890 [1000000000000000.000000ns] stime%0t=1000000000000000.000000ns stime%0d=10000 stime%0f=10000.000000 [1000000000000000.000000ns] rtime%0t=1000000000000000.000000ns rtime%0d=10000 rtime%0f=10000.000000 global svGetTime = 0 0,100000000 global svGetTimeUnit = 0 -2 svGetTmePrecision = 0 -2 global vpiSimTime = 0,100000000 vpiScaledRealTime = 1e+08 global vpiTimeUnit = -2 vpiTimePrecision = -2 top.t svGetTime = 0 0,100000000 top.t svGetTimeUnit = 0 2 svGetTmePrecision = 0 -2 top.t vpiSimTime = 0,100000000 vpiScaledRealTime = 10000 top.t vpiTimeUnit = 2 vpiTimePrecision = -2 *-* All Finished *-* verilator-5.042/test_regress/t/t_enum_huge_methods_bad.out0000644000542200017500000000121015101701376024441 0ustar mahmoudyfreeshell%Error: t/t_enum_huge_methods_bad.v:15:18: Value too wide for 64-bits expected in this context 160'h12344567abcd12344567abcd 15 | ELARGE = 160'h1234_4567_abcd_1234_4567_abcd | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error-UNSUPPORTED: t/t_enum_huge_methods_bad.v:30:19: Unsupported: enum next/prev/name method on enum with > 64 bits 30 | $display(e.name); | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_fuzz_always_bad.py0000755000542200017500000000076615101701376023163 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_local_bad.py0000755000542200017500000000076615101701376023064 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_typedef_circ_bad.py0000755000542200017500000000077615101701376023246 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_export_packed_struct2.cpp0000644000542200017500000000707615101701376024445 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // Copyright 2024 by Kefa Chen. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 //************************************************************************* #include #include #include #include VM_PREFIX_INCLUDE #include VM_PREFIX_ROOT_INCLUDE #include "TestCheck.h" #include "Vt_export_packed_struct2___024unit__03a__03acls_in__Vclpkg.h" /* // Packed struct in package package TEST_TYPES; typedef union packed { logic [64:0] a; logic [2:0] b; } sub_t; typedef struct packed { struct packed { // Anonymous packed struct logic a; } anon; TEST_TYPES::sub_t [2:0][2:0][2:0] b; } in_t; typedef struct packed { TEST_TYPES::sub_t [2:0][2:0][2:0] b; struct packed {logic a;} anon; } out_t; endpackage // Packed struct in class class cls_in; typedef struct packed { logic a; TEST_TYPES::sub_t [2:0][2:0][2:0] b; } in_t; in_t in; endclass //cls */ #define CONCAT_IMPL(a, b) a##b #define CONCAT(a, b) CONCAT_IMPL(a, b) #define CONCAT5(a, b, c, d, e) CONCAT(CONCAT(CONCAT(CONCAT(a, b), c), d), e) #define EXPORTED_STRUCT_NAME(STRUCT_NAME, NUMBER) \ CONCAT5(VM_PREFIX, _, STRUCT_NAME, __struct__, NUMBER) #define EXPORTED_UNION_NAME(UNION_NAME, NUMBER) \ CONCAT5(VM_PREFIX, _, UNION_NAME, __union__, NUMBER) #define SUB_T EXPORTED_UNION_NAME(sub_t, 0) #define IN_T EXPORTED_STRUCT_NAME(in_t, 0) #define IN2_T EXPORTED_STRUCT_NAME(in_t, 1) #define OUT_T EXPORTED_STRUCT_NAME(out_t, 0) int errors = 0; int main(int argc, char** argv) { const std::unique_ptr contextp{new VerilatedContext}; contextp->debug(0); contextp->randReset(2); contextp->commandArgs(argc, argv); const std::unique_ptr adder{new VM_PREFIX{contextp.get()}}; { IN_T in; IN2_T tmp; OUT_T out; for (int i = 0; i < 3; ++i) { for (int j = 0; j < 3; ++j) { for (int k = 0; k < 3; ++k) { VL_SET_WQ(in.b[i][j][k].a, 0x1234123412341234UL); // Set last bit zero and upper bits one in.b[i][j][k].a[2] = 0xfe; } } } in.anon.a = 0x1; adder->op1 = in.get(); adder->eval(); out.set(adder->out); std::memset(reinterpret_cast(&tmp), 0xff, sizeof(tmp)); // `set` function should clear upper bits of `tmp.a` tmp.set(adder->rootp->add__DOT__op2); for (int i = 0; i < 3; ++i) { for (int j = 0; j < 3; ++j) { for (int k = 0; k < 3; ++k) { TEST_CHECK_EQ(tmp.b[i][j][k].a[0], 0x12341234); TEST_CHECK_EQ(tmp.b[i][j][k].a[1], 0x12341234); TEST_CHECK_EQ(tmp.b[i][j][k].a[2], 0); } } } TEST_CHECK_EQ(tmp.a, 0x1); for (int i = 0; i < 3; ++i) { for (int j = 0; j < 3; ++j) { for (int k = 0; k < 3; ++k) { TEST_CHECK_EQ(out.b[i][j][k].a[0], 0x24682468); TEST_CHECK_EQ(out.b[i][j][k].a[1], 0x24682468); TEST_CHECK_EQ(out.b[i][j][k].a[2], 0x0); } } } TEST_CHECK_EQ(out.anon.a, 0x0); } printf("*-* All Finished *-*\n"); return errors; } verilator-5.042/test_regress/t/t_clk_condflop.py0000755000542200017500000000073415101701376022427 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_param_func2.v0000644000542200017500000000270315101701376021777 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; sub #(.WIDTH(4)) sub4(); sub #(.WIDTH(8)) sub8(); logic [3:0] out4; logic [7:0] out8; initial begin out4 = sub4.orer(4'b1000); out8 = sub8.orer(8'b10000000); if (out4 != 4'b1011) $stop; if (out8 != 8'b10111111) $stop; out4 = sub4.orer2(4'b1000); out8 = sub8.orer2(8'b10000000); if (out4 != 4'b1001) $stop; if (out8 != 8'b10011111) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module sub; parameter WIDTH = 1; function automatic [WIDTH-1:0] orer; input [WIDTH-1:0] in; // IEEE provices no way to override this parameter, basically it's a localparam parameter MASK_W = WIDTH - 2; localparam [MASK_W-1:0] MASK = '1; // verilator lint_off WIDTH return in | MASK; // verilator lint_on WIDTH endfunction function automatic [WIDTH-1:0] orer2; input [WIDTH-1:0] in; // Same param names as other function to check we disambiguate // IEEE provices no way to override this parameter, basically it's a localparam parameter MASK_W = WIDTH - 3; localparam [MASK_W-1:0] MASK = '1; // verilator lint_off WIDTH return in | MASK; // verilator lint_on WIDTH endfunction endmodule verilator-5.042/test_regress/t/t_param_public.py0000755000542200017500000000121715101701376022425 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if test.vlt_all: test.compile(verilator_flags2=["-GTOP_PARAM=30 --exe", test.pli_filename], make_top_shell=False, make_main=False) else: test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_wait_no_triggered_bad.out0000755000542200017500000000071015101701376024445 0ustar mahmoudyfreeshell%Error: t/t_wait_no_triggered_bad.v:15:12: Wait statement conditions do not take raw events (IEEE 1800-2023 15.5.3) : ... note: In instance 't' : ... Suggest use 'e_my_event.triggered' 15 | wait(e_my_event); | ^~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_lint_pinnotfound_bad.py0000755000542200017500000000076615101701376024176 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_langext_2017ext.py0000755000542200017500000000105515101701376022623 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_langext_2.v" # This is a compile only test. test.compile(v_flags2=["+1800-2017ext+v"]) test.passes() verilator-5.042/test_regress/t/t_interface_ref_trace_saif.out0000644000542200017500000076156515101701376025142 0ustar mahmoudyfreeshell// Generated by verilated_saif (SAIFILE (SAIFVERSION "2.0") (DIRECTION "backward") (PROGRAM_NAME "Verilator") (DIVIDER / ) (TIMESCALE 1ps) (DURATION 210) (INSTANCE top (NET (clk (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 41)) ) (INSTANCE t (NET (clk (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 41)) (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE intf_1 (NET (clk (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 41)) (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22)) (value\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11)) (value\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 5)) (value\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (value\[4\] (T0 150) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE the_struct (NET (val100\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22)) (val100\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11)) (val100\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 6)) (val100\[3\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 3)) (val100\[4\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[5\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22)) (val200\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11)) (val200\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 5)) (val200\[3\] (T0 80) (T1 130) (TZ 0) (TX 0) (TB 0) (TC 3)) (val200\[4\] (T0 70) (T1 140) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[7\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE inner (NET (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[1\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[2\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[3\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[4\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) (INSTANCE intf_2 (NET (clk (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 41)) (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (value\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11)) (value\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 5)) (value\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (value\[4\] (T0 140) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE the_struct (NET (val100\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (val100\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11)) (val100\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 6)) (val100\[3\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 3)) (val100\[4\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[5\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (val200\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11)) (val200\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 5)) (val200\[3\] (T0 80) (T1 130) (TZ 0) (TX 0) (TB 0) (TC 3)) (val200\[4\] (T0 60) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[7\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE inner (NET (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[1\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[2\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[3\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[4\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) (INSTANCE a (INSTANCE intf_one (NET (clk (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 41)) (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22)) (value\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11)) (value\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 5)) (value\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (value\[4\] (T0 150) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE the_struct (NET (val100\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22)) (val100\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11)) (val100\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 6)) (val100\[3\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 3)) (val100\[4\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[5\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22)) (val200\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11)) (val200\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 5)) (val200\[3\] (T0 80) (T1 130) (TZ 0) (TX 0) (TB 0) (TC 3)) (val200\[4\] (T0 70) (T1 140) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[7\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE inner (NET (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[1\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[2\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[3\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[4\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) (INSTANCE intf_two (NET (clk (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 41)) (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (value\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11)) (value\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 5)) (value\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (value\[4\] (T0 140) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE the_struct (NET (val100\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (val100\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11)) (val100\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 6)) (val100\[3\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 3)) (val100\[4\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[5\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (val200\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11)) (val200\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 5)) (val200\[3\] (T0 80) (T1 130) (TZ 0) (TX 0) (TB 0) (TC 3)) (val200\[4\] (T0 60) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[7\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE inner (NET (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[1\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[2\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[3\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[4\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) (INSTANCE intf_in_sub_all (NET (clk (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 41)) (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22)) (value\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11)) (value\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 5)) (value\[3\] (T0 80) (T1 130) (TZ 0) (TX 0) (TB 0) (TC 3)) (value\[4\] (T0 70) (T1 140) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[5\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[7\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[8\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[9\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE the_struct (NET (val100\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22)) (val100\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11)) (val100\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 6)) (val100\[3\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 4)) (val100\[4\] (T0 50) (T1 160) (TZ 0) (TX 0) (TB 0) (TC 2)) (val100\[5\] (T0 190) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[10\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22)) (val200\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11)) (val200\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 5)) (val200\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (val200\[4\] (T0 60) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 2)) (val200\[5\] (T0 60) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 2)) (val200\[6\] (T0 150) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[7\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[10\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE inner (NET (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[1\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[2\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[3\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[4\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) (INSTANCE ac1 (INSTANCE intf_for_check (NET (clk (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 41)) (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22)) (value\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11)) (value\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 5)) (value\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (value\[4\] (T0 150) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE the_struct (NET (val100\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22)) (val100\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11)) (val100\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 6)) (val100\[3\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 3)) (val100\[4\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[5\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22)) (val200\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11)) (val200\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 5)) (val200\[3\] (T0 80) (T1 130) (TZ 0) (TX 0) (TB 0) (TC 3)) (val200\[4\] (T0 70) (T1 140) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[7\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE inner (NET (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[1\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[2\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[3\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[4\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) (INSTANCE ac2 (INSTANCE intf_for_check (NET (clk (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 41)) (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (value\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11)) (value\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 5)) (value\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (value\[4\] (T0 140) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE the_struct (NET (val100\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (val100\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11)) (val100\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 6)) (val100\[3\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 3)) (val100\[4\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[5\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (val200\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11)) (val200\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 5)) (val200\[3\] (T0 80) (T1 130) (TZ 0) (TX 0) (TB 0) (TC 3)) (val200\[4\] (T0 60) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[7\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE inner (NET (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[1\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[2\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[3\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[4\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) (INSTANCE ac3 (INSTANCE intf_for_check (NET (clk (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 41)) (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22)) (value\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11)) (value\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 5)) (value\[3\] (T0 80) (T1 130) (TZ 0) (TX 0) (TB 0) (TC 3)) (value\[4\] (T0 70) (T1 140) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[5\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[7\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[8\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[9\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE the_struct (NET (val100\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22)) (val100\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11)) (val100\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 6)) (val100\[3\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 4)) (val100\[4\] (T0 50) (T1 160) (TZ 0) (TX 0) (TB 0) (TC 2)) (val100\[5\] (T0 190) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[10\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22)) (val200\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11)) (val200\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 5)) (val200\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (val200\[4\] (T0 60) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 2)) (val200\[5\] (T0 60) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 2)) (val200\[6\] (T0 150) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[7\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[10\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE inner (NET (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[1\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[2\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[3\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[4\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) (INSTANCE as3 (INSTANCE intf_for_struct (NET (clk (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 41)) (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22)) (value\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11)) (value\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 5)) (value\[3\] (T0 80) (T1 130) (TZ 0) (TX 0) (TB 0) (TC 3)) (value\[4\] (T0 70) (T1 140) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[5\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[7\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[8\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[9\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE the_struct (NET (val100\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22)) (val100\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11)) (val100\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 6)) (val100\[3\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 4)) (val100\[4\] (T0 50) (T1 160) (TZ 0) (TX 0) (TB 0) (TC 2)) (val100\[5\] (T0 190) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[10\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22)) (val200\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11)) (val200\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 5)) (val200\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (val200\[4\] (T0 60) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 2)) (val200\[5\] (T0 60) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 2)) (val200\[6\] (T0 150) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[7\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[10\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE inner (NET (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[1\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[2\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[3\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[4\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) ) (INSTANCE abcdefghijklmnopqrstuvwxyz (INSTANCE intf_one (NET (clk (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 41)) (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (value\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11)) (value\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 5)) (value\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (value\[4\] (T0 140) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE the_struct (NET (val100\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (val100\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11)) (val100\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 6)) (val100\[3\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 3)) (val100\[4\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[5\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (val200\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11)) (val200\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 5)) (val200\[3\] (T0 80) (T1 130) (TZ 0) (TX 0) (TB 0) (TC 3)) (val200\[4\] (T0 60) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[7\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE inner (NET (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[1\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[2\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[3\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[4\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) (INSTANCE intf_two (NET (clk (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 41)) (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22)) (value\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11)) (value\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 5)) (value\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (value\[4\] (T0 150) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE the_struct (NET (val100\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22)) (val100\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11)) (val100\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 6)) (val100\[3\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 3)) (val100\[4\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[5\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22)) (val200\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11)) (val200\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 5)) (val200\[3\] (T0 80) (T1 130) (TZ 0) (TX 0) (TB 0) (TC 3)) (val200\[4\] (T0 70) (T1 140) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[7\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE inner (NET (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[1\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[2\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[3\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[4\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) (INSTANCE intf_in_sub_all (NET (clk (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 41)) (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (value\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11)) (value\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 5)) (value\[3\] (T0 80) (T1 130) (TZ 0) (TX 0) (TB 0) (TC 3)) (value\[4\] (T0 60) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[5\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[7\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[8\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[9\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE the_struct (NET (val100\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (val100\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11)) (val100\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 6)) (val100\[3\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 4)) (val100\[4\] (T0 50) (T1 160) (TZ 0) (TX 0) (TB 0) (TC 2)) (val100\[5\] (T0 180) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[10\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (val200\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11)) (val200\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 5)) (val200\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (val200\[4\] (T0 70) (T1 140) (TZ 0) (TX 0) (TB 0) (TC 2)) (val200\[5\] (T0 70) (T1 140) (TZ 0) (TX 0) (TB 0) (TC 2)) (val200\[6\] (T0 140) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[7\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[10\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE inner (NET (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[1\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[2\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[3\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[4\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) (INSTANCE ac1 (INSTANCE intf_for_check (NET (clk (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 41)) (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (value\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11)) (value\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 5)) (value\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (value\[4\] (T0 140) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE the_struct (NET (val100\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (val100\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11)) (val100\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 6)) (val100\[3\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 3)) (val100\[4\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[5\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (val200\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11)) (val200\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 5)) (val200\[3\] (T0 80) (T1 130) (TZ 0) (TX 0) (TB 0) (TC 3)) (val200\[4\] (T0 60) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[7\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE inner (NET (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[1\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[2\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[3\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[4\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) (INSTANCE ac2 (INSTANCE intf_for_check (NET (clk (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 41)) (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22)) (value\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11)) (value\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 5)) (value\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (value\[4\] (T0 150) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE the_struct (NET (val100\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22)) (val100\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11)) (val100\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 6)) (val100\[3\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 3)) (val100\[4\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[5\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22)) (val200\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11)) (val200\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 5)) (val200\[3\] (T0 80) (T1 130) (TZ 0) (TX 0) (TB 0) (TC 3)) (val200\[4\] (T0 70) (T1 140) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[7\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE inner (NET (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[1\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[2\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[3\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[4\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) (INSTANCE ac3 (INSTANCE intf_for_check (NET (clk (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 41)) (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (value\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11)) (value\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 5)) (value\[3\] (T0 80) (T1 130) (TZ 0) (TX 0) (TB 0) (TC 3)) (value\[4\] (T0 60) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[5\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[7\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[8\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[9\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE the_struct (NET (val100\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (val100\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11)) (val100\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 6)) (val100\[3\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 4)) (val100\[4\] (T0 50) (T1 160) (TZ 0) (TX 0) (TB 0) (TC 2)) (val100\[5\] (T0 180) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[10\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (val200\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11)) (val200\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 5)) (val200\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (val200\[4\] (T0 70) (T1 140) (TZ 0) (TX 0) (TB 0) (TC 2)) (val200\[5\] (T0 70) (T1 140) (TZ 0) (TX 0) (TB 0) (TC 2)) (val200\[6\] (T0 140) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[7\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[10\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE inner (NET (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[1\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[2\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[3\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[4\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) (INSTANCE as3 (INSTANCE intf_for_struct (NET (clk (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 41)) (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (value\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11)) (value\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 5)) (value\[3\] (T0 80) (T1 130) (TZ 0) (TX 0) (TB 0) (TC 3)) (value\[4\] (T0 60) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[5\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[7\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[8\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[9\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE the_struct (NET (val100\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (val100\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11)) (val100\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 6)) (val100\[3\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 4)) (val100\[4\] (T0 50) (T1 160) (TZ 0) (TX 0) (TB 0) (TC 2)) (val100\[5\] (T0 180) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[10\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (val200\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11)) (val200\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 5)) (val200\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (val200\[4\] (T0 70) (T1 140) (TZ 0) (TX 0) (TB 0) (TC 2)) (val200\[5\] (T0 70) (T1 140) (TZ 0) (TX 0) (TB 0) (TC 2)) (val200\[6\] (T0 140) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[7\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[10\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE inner (NET (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[1\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[2\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[3\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[4\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) ) (INSTANCE c1 (INSTANCE intf_for_check (NET (clk (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 41)) (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22)) (value\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11)) (value\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 5)) (value\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (value\[4\] (T0 150) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE the_struct (NET (val100\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22)) (val100\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11)) (val100\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 6)) (val100\[3\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 3)) (val100\[4\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[5\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22)) (val200\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11)) (val200\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 5)) (val200\[3\] (T0 80) (T1 130) (TZ 0) (TX 0) (TB 0) (TC 3)) (val200\[4\] (T0 70) (T1 140) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[7\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE inner (NET (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[1\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[2\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[3\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[4\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) (INSTANCE c2 (INSTANCE intf_for_check (NET (clk (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 41)) (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (value\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11)) (value\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 5)) (value\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (value\[4\] (T0 140) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE the_struct (NET (val100\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (val100\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11)) (val100\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 6)) (val100\[3\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 3)) (val100\[4\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[5\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (val200\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11)) (val200\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 5)) (val200\[3\] (T0 80) (T1 130) (TZ 0) (TX 0) (TB 0) (TC 3)) (val200\[4\] (T0 60) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[7\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE inner (NET (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[1\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[2\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[3\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[4\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) (INSTANCE s1 (INSTANCE intf_for_struct (NET (clk (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 41)) (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22)) (value\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11)) (value\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 5)) (value\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (value\[4\] (T0 150) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE the_struct (NET (val100\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22)) (val100\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11)) (val100\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 6)) (val100\[3\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 3)) (val100\[4\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[5\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22)) (val200\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11)) (val200\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 5)) (val200\[3\] (T0 80) (T1 130) (TZ 0) (TX 0) (TB 0) (TC 3)) (val200\[4\] (T0 70) (T1 140) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[7\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE inner (NET (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[1\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[2\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[3\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[4\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) (INSTANCE s2 (INSTANCE intf_for_struct (NET (clk (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 41)) (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (value\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11)) (value\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 5)) (value\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (value\[4\] (T0 140) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE the_struct (NET (val100\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (val100\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11)) (val100\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 6)) (val100\[3\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 3)) (val100\[4\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[5\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val100\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val100\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (val200\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11)) (val200\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 5)) (val200\[3\] (T0 80) (T1 130) (TZ 0) (TX 0) (TB 0) (TC 3)) (val200\[4\] (T0 60) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[7\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1)) (val200\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val200\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE inner (NET (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21)) (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[1\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[2\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[3\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[4\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) ) ) ) verilator-5.042/test_regress/t/t_var_sc_bv.py0000755000542200017500000000113015101701376021725 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename, "--sc -fno-inline"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_math_repl2_bad.v0000644000542200017500000000120615101701376022442 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Outputs out, // Inputs clk, in ); parameter P32 = 32; parameter P24 = 24; localparam P29 = P24 + 5; input clk; output reg [P24-1:0] out; input [P29 - 1:0] in; always @(posedge clk) begin if (P29 >= P24) begin out <= in[P29 - 1 -: P24]; end else begin out <= {{(P24 - P29){1'b0}}, in}; end end endmodule verilator-5.042/test_regress/t/t_clk_concat3.py0000755000542200017500000000073415101701376022155 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_xml_first.py0000755000542200017500000000133615101701376022000 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') out_filename = test.obj_dir + "/V" + test.name + ".xml" test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only'], verilator_make_gmake=False, make_top_shell=False, make_main=False) test.files_identical(out_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_historical.py0000755000542200017500000000074315101701376023161 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--lint-only"]) test.passes() verilator-5.042/test_regress/t/t_depth_flop.v0000644000542200017500000000563115101701376021731 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Outputs out, // Inputs clk_0, clk_1, clk_2, clk_3, clk_4, clk_5, clk_6, clk_7, clk_8, clk_9, clk_10, clk_11, clk_12, clk_13, clk_14, clk_15, clk_16, clk_17, clk_18, clk_19, rstn_0, rstn_1, rstn_2, rstn_3, rstn_4, rstn_5, rstn_6, rstn_7, rstn_8, rstn_9, rstn_10, rstn_11, rstn_12, rstn_13, rstn_14, rstn_15, rstn_16, rstn_17, rstn_18, rstn_19 ); input clk_0; input clk_1; input clk_2; input clk_3; input clk_4; input clk_5; input clk_6; input clk_7; input clk_8; input clk_9; input clk_10; input clk_11; input clk_12; input clk_13; input clk_14; input clk_15; input clk_16; input clk_17; input clk_18; input clk_19; input rstn_0; input rstn_1; input rstn_2; input rstn_3; input rstn_4; input rstn_5; input rstn_6; input rstn_7; input rstn_8; input rstn_9; input rstn_10; input rstn_11; input rstn_12; input rstn_13; input rstn_14; input rstn_15; input rstn_16; input rstn_17; input rstn_18; input rstn_19; // verilator lint_off MULTIDRIVEN output reg out [0:29-1]; always_ff @(posedge clk_0, negedge rstn_0) if ((rstn_0 == 0)) out[0] <= 0; always_ff @(posedge clk_1, negedge rstn_1) if ((rstn_1 == 0)) out[1] <= 0; always_ff @(posedge clk_2, negedge rstn_2) if ((rstn_2 == 0)) out[2] <= 0; always_ff @(posedge clk_3, negedge rstn_3) if ((rstn_3 == 0)) out[3] <= 0; always_ff @(posedge clk_4, negedge rstn_4) if ((rstn_4 == 0)) out[4] <= 0; always_ff @(posedge clk_5, negedge rstn_5) if ((rstn_5 == 0)) out[5] <= 0; always_ff @(posedge clk_6, negedge rstn_6) if ((rstn_6 == 0)) out[6] <= 0; always_ff @(posedge clk_7, negedge rstn_7) if ((rstn_7 == 0)) out[7] <= 0; always_ff @(posedge clk_8, negedge rstn_8) if ((rstn_8 == 0)) out[8] <= 0; always_ff @(posedge clk_9, negedge rstn_9) if ((rstn_9 == 0)) out[9] <= 0; always_ff @(posedge clk_10, negedge rstn_10) if ((rstn_10 == 0)) out[10] <= 0; always_ff @(posedge clk_11, negedge rstn_11) if ((rstn_11 == 0)) out[11] <= 0; always_ff @(posedge clk_12, negedge rstn_12) if ((rstn_12 == 0)) out[12] <= 0; always_ff @(posedge clk_13, negedge rstn_13) if ((rstn_13 == 0)) out[13] <= 0; always_ff @(posedge clk_14, negedge rstn_14) if ((rstn_14 == 0)) out[14] <= 0; always_ff @(posedge clk_15, negedge rstn_15) if ((rstn_15 == 0)) out[15] <= 0; always_ff @(posedge clk_16, negedge rstn_16) if ((rstn_16 == 0)) out[16] <= 0; always_ff @(posedge clk_17, negedge rstn_17) if ((rstn_17 == 0)) out[17] <= 0; always_ff @(posedge clk_18, negedge rstn_18) if ((rstn_18 == 0)) out[18] <= 0; always_ff @(posedge clk_19, negedge rstn_19) if ((rstn_19 == 0)) out[19] <= 0; endmodule verilator-5.042/test_regress/t/t_gantt_io.dat0000644000542200017500000017636415101701376021730 0ustar mahmoudyfreeshellVLPROFVERSION 2.0 VLPROF arg +verilator+prof+exec+start+2 VLPROF arg +verilator+prof+exec+window+2 VLPROF info numa 0,1,4,5;2,3,6,7 VLPROF stat yields 0 VLPROF stat threads 2 VLPROFPROC processor : 0 VLPROFPROC vendor_id : AuthenticTest VLPROFPROC cpu family : 23 VLPROFPROC model : 113 VLPROFPROC model name : Test Ryzen 9 3950X 16-Core Processor VLPROFPROC stepping : 0 VLPROFPROC microcode : 0x8701013 VLPROFPROC cpu MHz : 2134.599 VLPROFPROC cache size : 512 KB VLPROFPROC physical id : 0 VLPROFPROC siblings : 32 VLPROFPROC core id : 0 VLPROFPROC cpu cores : 16 VLPROFPROC apicid : 0 VLPROFPROC initial apicid : 0 VLPROFPROC fpu : yes VLPROFPROC fpu_exception : yes VLPROFPROC cpuid level : 16 VLPROFPROC wp : yes VLPROFPROC flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate sme ssbd mba sev ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr wbnoinvd arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif umip rdpid overflow_recov succor smca VLPROFPROC bugs : sysret_ss_attrs spectre_v1 spectre_v2 spec_store_bypass VLPROFPROC bogomips : 6987.10 VLPROFPROC TLB size : 3072 4K pages VLPROFPROC clflush size : 64 VLPROFPROC cache_alignment : 64 VLPROFPROC address sizes : 43 bits physical, 48 bits virtual VLPROFPROC power management: ts ttp tm hwpstate cpb eff_freq_ro [13] [14] VLPROFPROC VLPROFPROC processor : 1 VLPROFPROC vendor_id : AuthenticTest VLPROFPROC cpu family : 23 VLPROFPROC model : 113 VLPROFPROC model name : Test Ryzen 9 3950X 16-Core Processor VLPROFPROC stepping : 0 VLPROFPROC microcode : 0x8701013 VLPROFPROC cpu MHz : 1932.526 VLPROFPROC cache size : 512 KB VLPROFPROC physical id : 0 VLPROFPROC siblings : 32 VLPROFPROC core id : 1 VLPROFPROC cpu cores : 16 VLPROFPROC apicid : 2 VLPROFPROC initial apicid : 2 VLPROFPROC fpu : yes VLPROFPROC fpu_exception : yes VLPROFPROC cpuid level : 16 VLPROFPROC wp : yes VLPROFPROC flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate sme ssbd mba sev ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr wbnoinvd arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif umip rdpid overflow_recov succor smca VLPROFPROC bugs : sysret_ss_attrs spectre_v1 spectre_v2 spec_store_bypass VLPROFPROC bogomips : 6987.10 VLPROFPROC TLB size : 3072 4K pages VLPROFPROC clflush size : 64 VLPROFPROC cache_alignment : 64 VLPROFPROC address sizes : 43 bits physical, 48 bits virtual VLPROFPROC power management: ts ttp tm hwpstate cpb eff_freq_ro [13] [14] VLPROFPROC VLPROFPROC processor : 2 VLPROFPROC vendor_id : AuthenticTest VLPROFPROC cpu family : 23 VLPROFPROC model : 113 VLPROFPROC model name : Test Ryzen 9 3950X 16-Core Processor VLPROFPROC stepping : 0 VLPROFPROC microcode : 0x8701013 VLPROFPROC cpu MHz : 1862.405 VLPROFPROC cache size : 512 KB VLPROFPROC physical id : 0 VLPROFPROC siblings : 32 VLPROFPROC core id : 2 VLPROFPROC cpu cores : 16 VLPROFPROC apicid : 4 VLPROFPROC initial apicid : 4 VLPROFPROC fpu : yes VLPROFPROC fpu_exception : yes VLPROFPROC cpuid level : 16 VLPROFPROC wp : yes VLPROFPROC flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate sme ssbd mba sev ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr wbnoinvd arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif umip rdpid overflow_recov succor smca VLPROFPROC bugs : sysret_ss_attrs spectre_v1 spectre_v2 spec_store_bypass VLPROFPROC bogomips : 6987.10 VLPROFPROC TLB size : 3072 4K pages VLPROFPROC clflush size : 64 VLPROFPROC cache_alignment : 64 VLPROFPROC address sizes : 43 bits physical, 48 bits virtual VLPROFPROC power management: ts ttp tm hwpstate cpb eff_freq_ro [13] [14] VLPROFPROC VLPROFPROC processor : 3 VLPROFPROC vendor_id : AuthenticTest VLPROFPROC cpu family : 23 VLPROFPROC model : 113 VLPROFPROC model name : Test Ryzen 9 3950X 16-Core Processor VLPROFPROC stepping : 0 VLPROFPROC microcode : 0x8701013 VLPROFPROC cpu MHz : 1862.009 VLPROFPROC cache size : 512 KB VLPROFPROC physical id : 0 VLPROFPROC siblings : 32 VLPROFPROC core id : 3 VLPROFPROC cpu cores : 16 VLPROFPROC apicid : 6 VLPROFPROC initial apicid : 6 VLPROFPROC fpu : yes VLPROFPROC fpu_exception : yes VLPROFPROC cpuid level : 16 VLPROFPROC wp : yes VLPROFPROC flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate sme ssbd mba sev ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr wbnoinvd arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif umip rdpid overflow_recov succor smca VLPROFPROC bugs : sysret_ss_attrs spectre_v1 spectre_v2 spec_store_bypass VLPROFPROC bogomips : 6987.10 VLPROFPROC TLB size : 3072 4K pages VLPROFPROC clflush size : 64 VLPROFPROC cache_alignment : 64 VLPROFPROC address sizes : 43 bits physical, 48 bits virtual VLPROFPROC power management: ts ttp tm hwpstate cpb eff_freq_ro [13] [14] VLPROFPROC VLPROFPROC processor : 4 VLPROFPROC vendor_id : AuthenticTest VLPROFPROC cpu family : 23 VLPROFPROC model : 113 VLPROFPROC model name : Test Ryzen 9 3950X 16-Core Processor VLPROFPROC stepping : 0 VLPROFPROC microcode : 0x8701013 VLPROFPROC cpu MHz : 2195.832 VLPROFPROC cache size : 512 KB VLPROFPROC physical id : 0 VLPROFPROC siblings : 32 VLPROFPROC core id : 4 VLPROFPROC cpu cores : 16 VLPROFPROC apicid : 8 VLPROFPROC initial apicid : 8 VLPROFPROC fpu : yes VLPROFPROC fpu_exception : yes VLPROFPROC cpuid level : 16 VLPROFPROC wp : yes VLPROFPROC flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate sme ssbd mba sev ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr wbnoinvd arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif umip rdpid overflow_recov succor smca VLPROFPROC bugs : sysret_ss_attrs spectre_v1 spectre_v2 spec_store_bypass VLPROFPROC bogomips : 6987.10 VLPROFPROC TLB size : 3072 4K pages VLPROFPROC clflush size : 64 VLPROFPROC cache_alignment : 64 VLPROFPROC address sizes : 43 bits physical, 48 bits virtual VLPROFPROC power management: ts ttp tm hwpstate cpb eff_freq_ro [13] [14] VLPROFPROC VLPROFPROC processor : 5 VLPROFPROC vendor_id : AuthenticTest VLPROFPROC cpu family : 23 VLPROFPROC model : 113 VLPROFPROC model name : Test Ryzen 9 3950X 16-Core Processor VLPROFPROC stepping : 0 VLPROFPROC microcode : 0x8701013 VLPROFPROC cpu MHz : 2190.061 VLPROFPROC cache size : 512 KB VLPROFPROC physical id : 0 VLPROFPROC siblings : 32 VLPROFPROC core id : 5 VLPROFPROC cpu cores : 16 VLPROFPROC apicid : 10 VLPROFPROC initial apicid : 10 VLPROFPROC fpu : yes VLPROFPROC fpu_exception : yes VLPROFPROC cpuid level : 16 VLPROFPROC wp : yes VLPROFPROC flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate sme ssbd mba sev ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr wbnoinvd arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif umip rdpid overflow_recov succor smca VLPROFPROC bugs : sysret_ss_attrs spectre_v1 spectre_v2 spec_store_bypass VLPROFPROC bogomips : 6987.10 VLPROFPROC TLB size : 3072 4K pages VLPROFPROC clflush size : 64 VLPROFPROC cache_alignment : 64 VLPROFPROC address sizes : 43 bits physical, 48 bits virtual VLPROFPROC power management: ts ttp tm hwpstate cpb eff_freq_ro [13] [14] VLPROFPROC VLPROFPROC processor : 6 VLPROFPROC vendor_id : AuthenticTest VLPROFPROC cpu family : 23 VLPROFPROC model : 113 VLPROFPROC model name : Test Ryzen 9 3950X 16-Core Processor VLPROFPROC stepping : 0 VLPROFPROC microcode : 0x8701013 VLPROFPROC cpu MHz : 2203.924 VLPROFPROC cache size : 512 KB VLPROFPROC physical id : 0 VLPROFPROC siblings : 32 VLPROFPROC core id : 6 VLPROFPROC cpu cores : 16 VLPROFPROC apicid : 12 VLPROFPROC initial apicid : 12 VLPROFPROC fpu : yes VLPROFPROC fpu_exception : yes VLPROFPROC cpuid level : 16 VLPROFPROC wp : yes VLPROFPROC flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate sme ssbd mba sev ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr wbnoinvd arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif umip rdpid overflow_recov succor smca VLPROFPROC bugs : sysret_ss_attrs spectre_v1 spectre_v2 spec_store_bypass VLPROFPROC bogomips : 6987.10 VLPROFPROC TLB size : 3072 4K pages VLPROFPROC clflush size : 64 VLPROFPROC cache_alignment : 64 VLPROFPROC address sizes : 43 bits physical, 48 bits virtual VLPROFPROC power management: ts ttp tm hwpstate cpb eff_freq_ro [13] [14] VLPROFPROC VLPROFPROC processor : 7 VLPROFPROC vendor_id : AuthenticTest VLPROFPROC cpu family : 23 VLPROFPROC model : 113 VLPROFPROC model name : Test Ryzen 9 3950X 16-Core Processor VLPROFPROC stepping : 0 VLPROFPROC microcode : 0x8701013 VLPROFPROC cpu MHz : 2193.174 VLPROFPROC cache size : 512 KB VLPROFPROC physical id : 0 VLPROFPROC siblings : 32 VLPROFPROC core id : 7 VLPROFPROC cpu cores : 16 VLPROFPROC apicid : 14 VLPROFPROC initial apicid : 14 VLPROFPROC fpu : yes VLPROFPROC fpu_exception : yes VLPROFPROC cpuid level : 16 VLPROFPROC wp : yes VLPROFPROC flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate sme ssbd mba sev ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr wbnoinvd arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif umip rdpid overflow_recov succor smca VLPROFPROC bugs : sysret_ss_attrs spectre_v1 spectre_v2 spec_store_bypass VLPROFPROC bogomips : 6987.10 VLPROFPROC TLB size : 3072 4K pages VLPROFPROC clflush size : 64 VLPROFPROC cache_alignment : 64 VLPROFPROC address sizes : 43 bits physical, 48 bits virtual VLPROFPROC power management: ts ttp tm hwpstate cpb eff_freq_ro [13] [14] VLPROFPROC VLPROFPROC processor : 8 VLPROFPROC vendor_id : AuthenticTest VLPROFPROC cpu family : 23 VLPROFPROC model : 113 VLPROFPROC model name : Test Ryzen 9 3950X 16-Core Processor VLPROFPROC stepping : 0 VLPROFPROC microcode : 0x8701013 VLPROFPROC cpu MHz : 2203.449 VLPROFPROC cache size : 512 KB VLPROFPROC physical id : 0 VLPROFPROC siblings : 32 VLPROFPROC core id : 8 VLPROFPROC cpu cores : 16 VLPROFPROC apicid : 16 VLPROFPROC initial apicid : 16 VLPROFPROC fpu : yes VLPROFPROC fpu_exception : yes VLPROFPROC cpuid level : 16 VLPROFPROC wp : yes VLPROFPROC flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate sme ssbd mba sev ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr wbnoinvd arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif umip rdpid overflow_recov succor smca VLPROFPROC bugs : sysret_ss_attrs spectre_v1 spectre_v2 spec_store_bypass VLPROFPROC bogomips : 6987.10 VLPROFPROC TLB size : 3072 4K pages VLPROFPROC clflush size : 64 VLPROFPROC cache_alignment : 64 VLPROFPROC address sizes : 43 bits physical, 48 bits virtual VLPROFPROC power management: ts ttp tm hwpstate cpb eff_freq_ro [13] [14] VLPROFPROC VLPROFPROC processor : 9 VLPROFPROC vendor_id : AuthenticTest VLPROFPROC cpu family : 23 VLPROFPROC model : 113 VLPROFPROC model name : Test Ryzen 9 3950X 16-Core Processor VLPROFPROC stepping : 0 VLPROFPROC microcode : 0x8701013 VLPROFPROC cpu MHz : 2197.717 VLPROFPROC cache size : 512 KB VLPROFPROC physical id : 0 VLPROFPROC siblings : 32 VLPROFPROC core id : 9 VLPROFPROC cpu cores : 16 VLPROFPROC apicid : 18 VLPROFPROC initial apicid : 18 VLPROFPROC fpu : yes VLPROFPROC fpu_exception : yes VLPROFPROC cpuid level : 16 VLPROFPROC wp : yes VLPROFPROC flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate sme ssbd mba sev ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr wbnoinvd arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif umip rdpid overflow_recov succor smca VLPROFPROC bugs : sysret_ss_attrs spectre_v1 spectre_v2 spec_store_bypass VLPROFPROC bogomips : 6987.10 VLPROFPROC TLB size : 3072 4K pages VLPROFPROC clflush size : 64 VLPROFPROC cache_alignment : 64 VLPROFPROC address sizes : 43 bits physical, 48 bits virtual VLPROFPROC power management: ts ttp tm hwpstate cpb eff_freq_ro [13] [14] VLPROFPROC VLPROFPROC processor : 10 VLPROFPROC vendor_id : AuthenticTest VLPROFPROC cpu family : 23 VLPROFPROC model : 113 VLPROFPROC model name : Test Ryzen 9 3950X 16-Core Processor VLPROFPROC stepping : 0 VLPROFPROC microcode : 0x8701013 VLPROFPROC cpu MHz : 2195.928 VLPROFPROC cache size : 512 KB VLPROFPROC physical id : 0 VLPROFPROC siblings : 32 VLPROFPROC core id : 10 VLPROFPROC cpu cores : 16 VLPROFPROC apicid : 20 VLPROFPROC initial apicid : 20 VLPROFPROC fpu : yes VLPROFPROC fpu_exception : yes VLPROFPROC cpuid level : 16 VLPROFPROC wp : yes VLPROFPROC flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate sme ssbd mba sev ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr wbnoinvd arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif umip rdpid overflow_recov succor smca VLPROFPROC bugs : sysret_ss_attrs spectre_v1 spectre_v2 spec_store_bypass VLPROFPROC bogomips : 6987.10 VLPROFPROC TLB size : 3072 4K pages VLPROFPROC clflush size : 64 VLPROFPROC cache_alignment : 64 VLPROFPROC address sizes : 43 bits physical, 48 bits virtual VLPROFPROC power management: ts ttp tm hwpstate cpb eff_freq_ro [13] [14] VLPROFPROC VLPROFPROC processor : 11 VLPROFPROC vendor_id : AuthenticTest VLPROFPROC cpu family : 23 VLPROFPROC model : 113 VLPROFPROC model name : Test Ryzen 9 3950X 16-Core Processor VLPROFPROC stepping : 0 VLPROFPROC microcode : 0x8701013 VLPROFPROC cpu MHz : 1964.149 VLPROFPROC cache size : 512 KB VLPROFPROC physical id : 0 VLPROFPROC siblings : 32 VLPROFPROC core id : 11 VLPROFPROC cpu cores : 16 VLPROFPROC apicid : 22 VLPROFPROC initial apicid : 22 VLPROFPROC fpu : yes VLPROFPROC fpu_exception : yes VLPROFPROC cpuid level : 16 VLPROFPROC wp : yes VLPROFPROC flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate sme ssbd mba sev ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr wbnoinvd arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif umip rdpid overflow_recov succor smca VLPROFPROC bugs : sysret_ss_attrs spectre_v1 spectre_v2 spec_store_bypass VLPROFPROC bogomips : 6987.10 VLPROFPROC TLB size : 3072 4K pages VLPROFPROC clflush size : 64 VLPROFPROC cache_alignment : 64 VLPROFPROC address sizes : 43 bits physical, 48 bits virtual VLPROFPROC power management: ts ttp tm hwpstate cpb eff_freq_ro [13] [14] VLPROFPROC VLPROFPROC processor : 12 VLPROFPROC vendor_id : AuthenticTest VLPROFPROC cpu family : 23 VLPROFPROC model : 113 VLPROFPROC model name : Test Ryzen 9 3950X 16-Core Processor VLPROFPROC stepping : 0 VLPROFPROC microcode : 0x8701013 VLPROFPROC cpu MHz : 2194.738 VLPROFPROC cache size : 512 KB VLPROFPROC physical id : 0 VLPROFPROC siblings : 32 VLPROFPROC core id : 12 VLPROFPROC cpu cores : 16 VLPROFPROC apicid : 24 VLPROFPROC initial apicid : 24 VLPROFPROC fpu : yes VLPROFPROC fpu_exception : yes VLPROFPROC cpuid level : 16 VLPROFPROC wp : yes VLPROFPROC flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate sme ssbd mba sev ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr wbnoinvd arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif umip rdpid overflow_recov succor smca VLPROFPROC bugs : sysret_ss_attrs spectre_v1 spectre_v2 spec_store_bypass VLPROFPROC bogomips : 6987.10 VLPROFPROC TLB size : 3072 4K pages VLPROFPROC clflush size : 64 VLPROFPROC cache_alignment : 64 VLPROFPROC address sizes : 43 bits physical, 48 bits virtual VLPROFPROC power management: ts ttp tm hwpstate cpb eff_freq_ro [13] [14] VLPROFPROC VLPROFPROC processor : 13 VLPROFPROC vendor_id : AuthenticTest VLPROFPROC cpu family : 23 VLPROFPROC model : 113 VLPROFPROC model name : Test Ryzen 9 3950X 16-Core Processor VLPROFPROC stepping : 0 VLPROFPROC microcode : 0x8701013 VLPROFPROC cpu MHz : 2194.821 VLPROFPROC cache size : 512 KB VLPROFPROC physical id : 0 VLPROFPROC siblings : 32 VLPROFPROC core id : 13 VLPROFPROC cpu cores : 16 VLPROFPROC apicid : 26 VLPROFPROC initial apicid : 26 VLPROFPROC fpu : yes VLPROFPROC fpu_exception : yes VLPROFPROC cpuid level : 16 VLPROFPROC wp : yes VLPROFPROC flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate sme ssbd mba sev ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr wbnoinvd arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif umip rdpid overflow_recov succor smca VLPROFPROC bugs : sysret_ss_attrs spectre_v1 spectre_v2 spec_store_bypass VLPROFPROC bogomips : 6987.10 VLPROFPROC TLB size : 3072 4K pages VLPROFPROC clflush size : 64 VLPROFPROC cache_alignment : 64 VLPROFPROC address sizes : 43 bits physical, 48 bits virtual VLPROFPROC power management: ts ttp tm hwpstate cpb eff_freq_ro [13] [14] VLPROFPROC VLPROFPROC processor : 14 VLPROFPROC vendor_id : AuthenticTest VLPROFPROC cpu family : 23 VLPROFPROC model : 113 VLPROFPROC model name : Test Ryzen 9 3950X 16-Core Processor VLPROFPROC stepping : 0 VLPROFPROC microcode : 0x8701013 VLPROFPROC cpu MHz : 2196.191 VLPROFPROC cache size : 512 KB VLPROFPROC physical id : 0 VLPROFPROC siblings : 32 VLPROFPROC core id : 14 VLPROFPROC cpu cores : 16 VLPROFPROC apicid : 28 VLPROFPROC initial apicid : 28 VLPROFPROC fpu : yes VLPROFPROC fpu_exception : yes VLPROFPROC cpuid level : 16 VLPROFPROC wp : yes VLPROFPROC flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate sme ssbd mba sev ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr wbnoinvd arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif umip rdpid overflow_recov succor smca VLPROFPROC bugs : sysret_ss_attrs spectre_v1 spectre_v2 spec_store_bypass VLPROFPROC bogomips : 6987.10 VLPROFPROC TLB size : 3072 4K pages VLPROFPROC clflush size : 64 VLPROFPROC cache_alignment : 64 VLPROFPROC address sizes : 43 bits physical, 48 bits virtual VLPROFPROC power management: ts ttp tm hwpstate cpb eff_freq_ro [13] [14] VLPROFPROC VLPROFPROC processor : 15 VLPROFPROC vendor_id : AuthenticTest VLPROFPROC cpu family : 23 VLPROFPROC model : 113 VLPROFPROC model name : Test Ryzen 9 3950X 16-Core Processor VLPROFPROC stepping : 0 VLPROFPROC microcode : 0x8701013 VLPROFPROC cpu MHz : 2198.063 VLPROFPROC cache size : 512 KB VLPROFPROC physical id : 0 VLPROFPROC siblings : 32 VLPROFPROC core id : 15 VLPROFPROC cpu cores : 16 VLPROFPROC apicid : 30 VLPROFPROC initial apicid : 30 VLPROFPROC fpu : yes VLPROFPROC fpu_exception : yes VLPROFPROC cpuid level : 16 VLPROFPROC wp : yes VLPROFPROC flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate sme ssbd mba sev ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr wbnoinvd arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif umip rdpid overflow_recov succor smca VLPROFPROC bugs : sysret_ss_attrs spectre_v1 spectre_v2 spec_store_bypass VLPROFPROC bogomips : 6987.10 VLPROFPROC TLB size : 3072 4K pages VLPROFPROC clflush size : 64 VLPROFPROC cache_alignment : 64 VLPROFPROC address sizes : 43 bits physical, 48 bits virtual VLPROFPROC power management: ts ttp tm hwpstate cpb eff_freq_ro [13] [14] VLPROFPROC VLPROFPROC processor : 16 VLPROFPROC vendor_id : AuthenticTest VLPROFPROC cpu family : 23 VLPROFPROC model : 113 VLPROFPROC model name : Test Ryzen 9 3950X 16-Core Processor VLPROFPROC stepping : 0 VLPROFPROC microcode : 0x8701013 VLPROFPROC cpu MHz : 2152.652 VLPROFPROC cache size : 512 KB VLPROFPROC physical id : 0 VLPROFPROC siblings : 32 VLPROFPROC core id : 0 VLPROFPROC cpu cores : 16 VLPROFPROC apicid : 1 VLPROFPROC initial apicid : 1 VLPROFPROC fpu : yes VLPROFPROC fpu_exception : yes VLPROFPROC cpuid level : 16 VLPROFPROC wp : yes VLPROFPROC flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate sme ssbd mba sev ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr wbnoinvd arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif umip rdpid overflow_recov succor smca VLPROFPROC bugs : sysret_ss_attrs spectre_v1 spectre_v2 spec_store_bypass VLPROFPROC bogomips : 6987.10 VLPROFPROC TLB size : 3072 4K pages VLPROFPROC clflush size : 64 VLPROFPROC cache_alignment : 64 VLPROFPROC address sizes : 43 bits physical, 48 bits virtual VLPROFPROC power management: ts ttp tm hwpstate cpb eff_freq_ro [13] [14] VLPROFPROC VLPROFPROC processor : 17 VLPROFPROC vendor_id : AuthenticTest VLPROFPROC cpu family : 23 VLPROFPROC model : 113 VLPROFPROC model name : Test Ryzen 9 3950X 16-Core Processor VLPROFPROC stepping : 0 VLPROFPROC microcode : 0x8701013 VLPROFPROC cpu MHz : 2257.474 VLPROFPROC cache size : 512 KB VLPROFPROC physical id : 0 VLPROFPROC siblings : 32 VLPROFPROC core id : 1 VLPROFPROC cpu cores : 16 VLPROFPROC apicid : 3 VLPROFPROC initial apicid : 3 VLPROFPROC fpu : yes VLPROFPROC fpu_exception : yes VLPROFPROC cpuid level : 16 VLPROFPROC wp : yes VLPROFPROC flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate sme ssbd mba sev ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr wbnoinvd arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif umip rdpid overflow_recov succor smca VLPROFPROC bugs : sysret_ss_attrs spectre_v1 spectre_v2 spec_store_bypass VLPROFPROC bogomips : 6987.10 VLPROFPROC TLB size : 3072 4K pages VLPROFPROC clflush size : 64 VLPROFPROC cache_alignment : 64 VLPROFPROC address sizes : 43 bits physical, 48 bits virtual VLPROFPROC power management: ts ttp tm hwpstate cpb eff_freq_ro [13] [14] VLPROFPROC VLPROFPROC processor : 18 VLPROFPROC vendor_id : AuthenticTest VLPROFPROC cpu family : 23 VLPROFPROC model : 113 VLPROFPROC model name : Test Ryzen 9 3950X 16-Core Processor VLPROFPROC stepping : 0 VLPROFPROC microcode : 0x8701013 VLPROFPROC cpu MHz : 1862.896 VLPROFPROC cache size : 512 KB VLPROFPROC physical id : 0 VLPROFPROC siblings : 32 VLPROFPROC core id : 2 VLPROFPROC cpu cores : 16 VLPROFPROC apicid : 5 VLPROFPROC initial apicid : 5 VLPROFPROC fpu : yes VLPROFPROC fpu_exception : yes VLPROFPROC cpuid level : 16 VLPROFPROC wp : yes VLPROFPROC flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate sme ssbd mba sev ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr wbnoinvd arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif umip rdpid overflow_recov succor smca VLPROFPROC bugs : sysret_ss_attrs spectre_v1 spectre_v2 spec_store_bypass VLPROFPROC bogomips : 6987.10 VLPROFPROC TLB size : 3072 4K pages VLPROFPROC clflush size : 64 VLPROFPROC cache_alignment : 64 VLPROFPROC address sizes : 43 bits physical, 48 bits virtual VLPROFPROC power management: ts ttp tm hwpstate cpb eff_freq_ro [13] [14] VLPROFPROC VLPROFPROC processor : 19 VLPROFPROC vendor_id : AuthenticTest VLPROFPROC cpu family : 23 VLPROFPROC model : 113 VLPROFPROC model name : Test Ryzen 9 3950X 16-Core Processor VLPROFPROC stepping : 0 VLPROFPROC microcode : 0x8701013 VLPROFPROC cpu MHz : 1863.193 VLPROFPROC cache size : 512 KB VLPROFPROC physical id : 0 VLPROFPROC siblings : 32 VLPROFPROC core id : 3 VLPROFPROC cpu cores : 16 VLPROFPROC apicid : 7 VLPROFPROC initial apicid : 7 VLPROFPROC fpu : yes VLPROFPROC fpu_exception : yes VLPROFPROC cpuid level : 16 VLPROFPROC wp : yes VLPROFPROC flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate sme ssbd mba sev ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr wbnoinvd arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif umip rdpid overflow_recov succor smca VLPROFPROC bugs : sysret_ss_attrs spectre_v1 spectre_v2 spec_store_bypass VLPROFPROC bogomips : 6987.10 VLPROFPROC TLB size : 3072 4K pages VLPROFPROC clflush size : 64 VLPROFPROC cache_alignment : 64 VLPROFPROC address sizes : 43 bits physical, 48 bits virtual VLPROFPROC power management: ts ttp tm hwpstate cpb eff_freq_ro [13] [14] VLPROFPROC VLPROFPROC processor : 20 VLPROFPROC vendor_id : AuthenticTest VLPROFPROC cpu family : 23 VLPROFPROC model : 113 VLPROFPROC model name : Test Ryzen 9 3950X 16-Core Processor VLPROFPROC stepping : 0 VLPROFPROC microcode : 0x8701013 VLPROFPROC cpu MHz : 2189.303 VLPROFPROC cache size : 512 KB VLPROFPROC physical id : 0 VLPROFPROC siblings : 32 VLPROFPROC core id : 4 VLPROFPROC cpu cores : 16 VLPROFPROC apicid : 9 VLPROFPROC initial apicid : 9 VLPROFPROC fpu : yes VLPROFPROC fpu_exception : yes VLPROFPROC cpuid level : 16 VLPROFPROC wp : yes VLPROFPROC flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate sme ssbd mba sev ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr wbnoinvd arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif umip rdpid overflow_recov succor smca VLPROFPROC bugs : sysret_ss_attrs spectre_v1 spectre_v2 spec_store_bypass VLPROFPROC bogomips : 6987.10 VLPROFPROC TLB size : 3072 4K pages VLPROFPROC clflush size : 64 VLPROFPROC cache_alignment : 64 VLPROFPROC address sizes : 43 bits physical, 48 bits virtual VLPROFPROC power management: ts ttp tm hwpstate cpb eff_freq_ro [13] [14] VLPROFPROC VLPROFPROC processor : 21 VLPROFPROC vendor_id : AuthenticTest VLPROFPROC cpu family : 23 VLPROFPROC model : 113 VLPROFPROC model name : Test Ryzen 9 3950X 16-Core Processor VLPROFPROC stepping : 0 VLPROFPROC microcode : 0x8701013 VLPROFPROC cpu MHz : 2194.584 VLPROFPROC cache size : 512 KB VLPROFPROC physical id : 0 VLPROFPROC siblings : 32 VLPROFPROC core id : 5 VLPROFPROC cpu cores : 16 VLPROFPROC apicid : 11 VLPROFPROC initial apicid : 11 VLPROFPROC fpu : yes VLPROFPROC fpu_exception : yes VLPROFPROC cpuid level : 16 VLPROFPROC wp : yes VLPROFPROC flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate sme ssbd mba sev ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr wbnoinvd arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif umip rdpid overflow_recov succor smca VLPROFPROC bugs : sysret_ss_attrs spectre_v1 spectre_v2 spec_store_bypass VLPROFPROC bogomips : 6987.10 VLPROFPROC TLB size : 3072 4K pages VLPROFPROC clflush size : 64 VLPROFPROC cache_alignment : 64 VLPROFPROC address sizes : 43 bits physical, 48 bits virtual VLPROFPROC power management: ts ttp tm hwpstate cpb eff_freq_ro [13] [14] VLPROFPROC VLPROFPROC processor : 22 VLPROFPROC vendor_id : AuthenticTest VLPROFPROC cpu family : 23 VLPROFPROC model : 113 VLPROFPROC model name : Test Ryzen 9 3950X 16-Core Processor VLPROFPROC stepping : 0 VLPROFPROC microcode : 0x8701013 VLPROFPROC cpu MHz : 2195.060 VLPROFPROC cache size : 512 KB VLPROFPROC physical id : 0 VLPROFPROC siblings : 32 VLPROFPROC core id : 6 VLPROFPROC cpu cores : 16 VLPROFPROC apicid : 13 VLPROFPROC initial apicid : 13 VLPROFPROC fpu : yes VLPROFPROC fpu_exception : yes VLPROFPROC cpuid level : 16 VLPROFPROC wp : yes VLPROFPROC flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate sme ssbd mba sev ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr wbnoinvd arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif umip rdpid overflow_recov succor smca VLPROFPROC bugs : sysret_ss_attrs spectre_v1 spectre_v2 spec_store_bypass VLPROFPROC bogomips : 6987.10 VLPROFPROC TLB size : 3072 4K pages VLPROFPROC clflush size : 64 VLPROFPROC cache_alignment : 64 VLPROFPROC address sizes : 43 bits physical, 48 bits virtual VLPROFPROC power management: ts ttp tm hwpstate cpb eff_freq_ro [13] [14] VLPROFPROC VLPROFPROC processor : 23 VLPROFPROC vendor_id : AuthenticTest VLPROFPROC cpu family : 23 VLPROFPROC model : 113 VLPROFPROC model name : Test Ryzen 9 3950X 16-Core Processor VLPROFPROC stepping : 0 VLPROFPROC microcode : 0x8701013 VLPROFPROC cpu MHz : 2189.319 VLPROFPROC cache size : 512 KB VLPROFPROC physical id : 0 VLPROFPROC siblings : 32 VLPROFPROC core id : 7 VLPROFPROC cpu cores : 16 VLPROFPROC apicid : 15 VLPROFPROC initial apicid : 15 VLPROFPROC fpu : yes VLPROFPROC fpu_exception : yes VLPROFPROC cpuid level : 16 VLPROFPROC wp : yes VLPROFPROC flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate sme ssbd mba sev ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr wbnoinvd arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif umip rdpid overflow_recov succor smca VLPROFPROC bugs : sysret_ss_attrs spectre_v1 spectre_v2 spec_store_bypass VLPROFPROC bogomips : 6987.10 VLPROFPROC TLB size : 3072 4K pages VLPROFPROC clflush size : 64 VLPROFPROC cache_alignment : 64 VLPROFPROC address sizes : 43 bits physical, 48 bits virtual VLPROFPROC power management: ts ttp tm hwpstate cpb eff_freq_ro [13] [14] VLPROFPROC VLPROFPROC processor : 24 VLPROFPROC vendor_id : AuthenticTest VLPROFPROC cpu family : 23 VLPROFPROC model : 113 VLPROFPROC model name : Test Ryzen 9 3950X 16-Core Processor VLPROFPROC stepping : 0 VLPROFPROC microcode : 0x8701013 VLPROFPROC cpu MHz : 2195.031 VLPROFPROC cache size : 512 KB VLPROFPROC physical id : 0 VLPROFPROC siblings : 32 VLPROFPROC core id : 8 VLPROFPROC cpu cores : 16 VLPROFPROC apicid : 17 VLPROFPROC initial apicid : 17 VLPROFPROC fpu : yes VLPROFPROC fpu_exception : yes VLPROFPROC cpuid level : 16 VLPROFPROC wp : yes VLPROFPROC flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate sme ssbd mba sev ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr wbnoinvd arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif umip rdpid overflow_recov succor smca VLPROFPROC bugs : sysret_ss_attrs spectre_v1 spectre_v2 spec_store_bypass VLPROFPROC bogomips : 6987.10 VLPROFPROC TLB size : 3072 4K pages VLPROFPROC clflush size : 64 VLPROFPROC cache_alignment : 64 VLPROFPROC address sizes : 43 bits physical, 48 bits virtual VLPROFPROC power management: ts ttp tm hwpstate cpb eff_freq_ro [13] [14] VLPROFPROC VLPROFPROC processor : 25 VLPROFPROC vendor_id : AuthenticTest VLPROFPROC cpu family : 23 VLPROFPROC model : 113 VLPROFPROC model name : Test Ryzen 9 3950X 16-Core Processor VLPROFPROC stepping : 0 VLPROFPROC microcode : 0x8701013 VLPROFPROC cpu MHz : 2555.092 VLPROFPROC cache size : 512 KB VLPROFPROC physical id : 0 VLPROFPROC siblings : 32 VLPROFPROC core id : 9 VLPROFPROC cpu cores : 16 VLPROFPROC apicid : 19 VLPROFPROC initial apicid : 19 VLPROFPROC fpu : yes VLPROFPROC fpu_exception : yes VLPROFPROC cpuid level : 16 VLPROFPROC wp : yes VLPROFPROC flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate sme ssbd mba sev ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr wbnoinvd arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif umip rdpid overflow_recov succor smca VLPROFPROC bugs : sysret_ss_attrs spectre_v1 spectre_v2 spec_store_bypass VLPROFPROC bogomips : 6987.10 VLPROFPROC TLB size : 3072 4K pages VLPROFPROC clflush size : 64 VLPROFPROC cache_alignment : 64 VLPROFPROC address sizes : 43 bits physical, 48 bits virtual VLPROFPROC power management: ts ttp tm hwpstate cpb eff_freq_ro [13] [14] VLPROFPROC VLPROFPROC processor : 26 VLPROFPROC vendor_id : AuthenticTest VLPROFPROC cpu family : 23 VLPROFPROC model : 113 VLPROFPROC model name : Test Ryzen 9 3950X 16-Core Processor VLPROFPROC stepping : 0 VLPROFPROC microcode : 0x8701013 VLPROFPROC cpu MHz : 2191.830 VLPROFPROC cache size : 512 KB VLPROFPROC physical id : 0 VLPROFPROC siblings : 32 VLPROFPROC core id : 10 VLPROFPROC cpu cores : 16 VLPROFPROC apicid : 21 VLPROFPROC initial apicid : 21 VLPROFPROC fpu : yes VLPROFPROC fpu_exception : yes VLPROFPROC cpuid level : 16 VLPROFPROC wp : yes VLPROFPROC flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate sme ssbd mba sev ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr wbnoinvd arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif umip rdpid overflow_recov succor smca VLPROFPROC bugs : sysret_ss_attrs spectre_v1 spectre_v2 spec_store_bypass VLPROFPROC bogomips : 6987.10 VLPROFPROC TLB size : 3072 4K pages VLPROFPROC clflush size : 64 VLPROFPROC cache_alignment : 64 VLPROFPROC address sizes : 43 bits physical, 48 bits virtual VLPROFPROC power management: ts ttp tm hwpstate cpb eff_freq_ro [13] [14] VLPROFPROC VLPROFPROC processor : 27 VLPROFPROC vendor_id : AuthenticTest VLPROFPROC cpu family : 23 VLPROFPROC model : 113 VLPROFPROC model name : Test Ryzen 9 3950X 16-Core Processor VLPROFPROC stepping : 0 VLPROFPROC microcode : 0x8701013 VLPROFPROC cpu MHz : 2194.661 VLPROFPROC cache size : 512 KB VLPROFPROC physical id : 0 VLPROFPROC siblings : 32 VLPROFPROC core id : 11 VLPROFPROC cpu cores : 16 VLPROFPROC apicid : 23 VLPROFPROC initial apicid : 23 VLPROFPROC fpu : yes VLPROFPROC fpu_exception : yes VLPROFPROC cpuid level : 16 VLPROFPROC wp : yes VLPROFPROC flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate sme ssbd mba sev ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr wbnoinvd arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif umip rdpid overflow_recov succor smca VLPROFPROC bugs : sysret_ss_attrs spectre_v1 spectre_v2 spec_store_bypass VLPROFPROC bogomips : 6987.10 VLPROFPROC TLB size : 3072 4K pages VLPROFPROC clflush size : 64 VLPROFPROC cache_alignment : 64 VLPROFPROC address sizes : 43 bits physical, 48 bits virtual VLPROFPROC power management: ts ttp tm hwpstate cpb eff_freq_ro [13] [14] VLPROFPROC VLPROFPROC processor : 28 VLPROFPROC vendor_id : AuthenticTest VLPROFPROC cpu family : 23 VLPROFPROC model : 113 VLPROFPROC model name : Test Ryzen 9 3950X 16-Core Processor VLPROFPROC stepping : 0 VLPROFPROC microcode : 0x8701013 VLPROFPROC cpu MHz : 2194.445 VLPROFPROC cache size : 512 KB VLPROFPROC physical id : 0 VLPROFPROC siblings : 32 VLPROFPROC core id : 12 VLPROFPROC cpu cores : 16 VLPROFPROC apicid : 25 VLPROFPROC initial apicid : 25 VLPROFPROC fpu : yes VLPROFPROC fpu_exception : yes VLPROFPROC cpuid level : 16 VLPROFPROC wp : yes VLPROFPROC flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate sme ssbd mba sev ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr wbnoinvd arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif umip rdpid overflow_recov succor smca VLPROFPROC bugs : sysret_ss_attrs spectre_v1 spectre_v2 spec_store_bypass VLPROFPROC bogomips : 6987.10 VLPROFPROC TLB size : 3072 4K pages VLPROFPROC clflush size : 64 VLPROFPROC cache_alignment : 64 VLPROFPROC address sizes : 43 bits physical, 48 bits virtual VLPROFPROC power management: ts ttp tm hwpstate cpb eff_freq_ro [13] [14] VLPROFPROC VLPROFPROC processor : 29 VLPROFPROC vendor_id : AuthenticTest VLPROFPROC cpu family : 23 VLPROFPROC model : 113 VLPROFPROC model name : Test Ryzen 9 3950X 16-Core Processor VLPROFPROC stepping : 0 VLPROFPROC microcode : 0x8701013 VLPROFPROC cpu MHz : 2194.786 VLPROFPROC cache size : 512 KB VLPROFPROC physical id : 0 VLPROFPROC siblings : 32 VLPROFPROC core id : 13 VLPROFPROC cpu cores : 16 VLPROFPROC apicid : 27 VLPROFPROC initial apicid : 27 VLPROFPROC fpu : yes VLPROFPROC fpu_exception : yes VLPROFPROC cpuid level : 16 VLPROFPROC wp : yes VLPROFPROC flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate sme ssbd mba sev ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr wbnoinvd arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif umip rdpid overflow_recov succor smca VLPROFPROC bugs : sysret_ss_attrs spectre_v1 spectre_v2 spec_store_bypass VLPROFPROC bogomips : 6987.10 VLPROFPROC TLB size : 3072 4K pages VLPROFPROC clflush size : 64 VLPROFPROC cache_alignment : 64 VLPROFPROC address sizes : 43 bits physical, 48 bits virtual VLPROFPROC power management: ts ttp tm hwpstate cpb eff_freq_ro [13] [14] VLPROFPROC VLPROFPROC processor : 30 VLPROFPROC vendor_id : AuthenticTest VLPROFPROC cpu family : 23 VLPROFPROC model : 113 VLPROFPROC model name : Test Ryzen 9 3950X 16-Core Processor VLPROFPROC stepping : 0 VLPROFPROC microcode : 0x8701013 VLPROFPROC cpu MHz : 2189.282 VLPROFPROC cache size : 512 KB VLPROFPROC physical id : 0 VLPROFPROC siblings : 32 VLPROFPROC core id : 14 VLPROFPROC cpu cores : 16 VLPROFPROC apicid : 29 VLPROFPROC initial apicid : 29 VLPROFPROC fpu : yes VLPROFPROC fpu_exception : yes VLPROFPROC cpuid level : 16 VLPROFPROC wp : yes VLPROFPROC flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate sme ssbd mba sev ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr wbnoinvd arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif umip rdpid overflow_recov succor smca VLPROFPROC bugs : sysret_ss_attrs spectre_v1 spectre_v2 spec_store_bypass VLPROFPROC bogomips : 6987.10 VLPROFPROC TLB size : 3072 4K pages VLPROFPROC clflush size : 64 VLPROFPROC cache_alignment : 64 VLPROFPROC address sizes : 43 bits physical, 48 bits virtual VLPROFPROC power management: ts ttp tm hwpstate cpb eff_freq_ro [13] [14] VLPROFPROC VLPROFPROC processor : 31 VLPROFPROC vendor_id : AuthenticTest VLPROFPROC cpu family : 23 VLPROFPROC model : 113 VLPROFPROC model name : Test Ryzen 9 3950X 16-Core Processor VLPROFPROC stepping : 0 VLPROFPROC microcode : 0x8701013 VLPROFPROC cpu MHz : 2195.563 VLPROFPROC cache size : 512 KB VLPROFPROC physical id : 0 VLPROFPROC siblings : 32 VLPROFPROC core id : 15 VLPROFPROC cpu cores : 16 VLPROFPROC apicid : 31 VLPROFPROC initial apicid : 31 VLPROFPROC fpu : yes VLPROFPROC fpu_exception : yes VLPROFPROC cpuid level : 16 VLPROFPROC wp : yes VLPROFPROC flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate sme ssbd mba sev ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr wbnoinvd arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif umip rdpid overflow_recov succor smca VLPROFPROC bugs : sysret_ss_attrs spectre_v1 spectre_v2 spec_store_bypass VLPROFPROC bogomips : 6987.10 VLPROFPROC TLB size : 3072 4K pages VLPROFPROC clflush size : 64 VLPROFPROC cache_alignment : 64 VLPROFPROC address sizes : 43 bits physical, 48 bits virtual VLPROFPROC power management: ts ttp tm hwpstate cpb eff_freq_ro [13] [14] VLPROFPROC VLPROFTHREAD 0 VLPROFEXEC EXEC_GRAPH_BEGIN 945 VLPROFEXEC MTASK_BEGIN 2695 id 6 predictStart 0 cpu 19 VLPROFEXEC MTASK_BEGIN 3795 id 10 predictStart 196 cpu 19 hierBlock sub VLPROFEXEC MTASK_END 4850 predictCost 30 VLPROFEXEC MTASK_END 5905 predictCost 30 VLPROFEXEC MTASK_BEGIN 9695 id 10 predictStart 196 cpu 19 VLPROFEXEC MTASK_END 9870 predictCost 30 VLPROFEXEC EXEC_GRAPH_END 12180 VLPROFEXEC EXEC_GRAPH_BEGIN 14000 VLPROFEXEC MTASK_BEGIN 15610 id 6 predictStart 0 cpu 19 VLPROFEXEC MTASK_END 15820 predictCost 30 VLPROFEXEC THREAD_SCHEDULE_WAIT_BEGIN 20000 cpu 19 VLPROFEXEC THREAD_SCHEDULE_WAIT_END 21000 cpu 19 VLPROFEXEC MTASK_BEGIN 21700 id 10 predictStart 196 cpu 19 VLPROFEXEC MTASK_END 21875 predictCost 30 VLPROFEXEC EXEC_GRAPH_END 22085 VLPROFTHREAD 1 VLPROFEXEC MTASK_BEGIN 5495 id 5 predictStart 0 cpu 10 VLPROFEXEC MTASK_END 6090 predictCost 30 VLPROFEXEC MTASK_BEGIN 6300 id 7 predictStart 30 cpu 10 VLPROFEXEC MTASK_END 6895 predictCost 30 VLPROFEXEC MTASK_BEGIN 7490 id 8 predictStart 60 cpu 10 VLPROFEXEC MTASK_END 8540 predictCost 107 VLPROFEXEC MTASK_BEGIN 9135 id 9 predictStart 167 cpu 10 VLPROFEXEC MTASK_END 9730 predictCost 30 VLPROFEXEC MTASK_BEGIN 10255 id 11 predictStart 197 cpu 10 VLPROFEXEC MTASK_END 11060 predictCost 30 VLPROFEXEC MTASK_BEGIN 18375 id 5 predictStart 0 cpu 10 VLPROFEXEC MTASK_END 18970 predictCost 30 VLPROFEXEC MTASK_BEGIN 19145 id 7 predictStart 30 cpu 10 VLPROFEXEC MTASK_END 19320 predictCost 30 VLPROFEXEC MTASK_BEGIN 19670 id 8 predictStart 60 cpu 10 VLPROFEXEC MTASK_END 19810 predictCost 107 VLPROFEXEC MTASK_BEGIN 20650 id 9 predictStart 167 cpu 10 VLPROFEXEC MTASK_END 20720 predictCost 30 VLPROFEXEC MTASK_BEGIN 21140 id 11 predictStart 197 cpu 10 VLPROFEXEC MTASK_END 21245 predictCost 30 VLPROFEXEC THREAD_SCHEDULE_WAIT_BEGIN 22000 cpu 10 VLPROFEXEC THREAD_SCHEDULE_WAIT_END 23000 cpu 10 VLPROF stat ticks 23415 verilator-5.042/test_regress/t/t_lint_latch_bad_3.py0000755000542200017500000000076615101701376023150 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_vpi_public_depthn_3.py0000755000542200017500000000121515101701376023705 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_vpi_public_depthn.v" test.compile(verilator_flags2=['--public-depth 3']) test.execute() test.files_identical(test.run_log_filename, test.golden_filename, is_logfile=True, strip_hex=True) test.passes() verilator-5.042/test_regress/t/t_gen_cond_const.v0000644000542200017500000000257015101701376022566 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test for generate IF constants // // The given generate loop should have a constant expression as argument. This // test checks it really does evaluate as constant. // This file ONLY is placed into the Public Domain, for any use, without // warranty, 2012 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 `define MAX_SIZE 4 module t (/*AUTOARG*/ // Inputs clk ); input clk; // Set the parameters, so that we use a size less than MAX_SIZE test_gen #(.SIZE (2), .MASK (4'b1111)) i_test_gen (.clk (clk)); // This is only a compilation test, but for good measure we do one clock // cycle. integer count; initial begin count = 0; end always @(posedge clk) begin if (count == 1) begin $write("*-* All Finished *-*\n"); $finish; end else begin count = count + 1; end end endmodule // t module test_gen #( parameter SIZE = `MAX_SIZE, MASK = `MAX_SIZE'b0) (/*AUTOARG*/ // Inputs clk ); input clk; // Generate blocks that rely on short-circuiting of the logic to avoid // errors. generate if ((SIZE < 8'h04) && MASK[0]) begin always @(posedge clk) begin `ifdef TEST_VERBOSE $write ("Generate IF MASK[0] = %d\n", MASK[0]); `endif end end endgenerate endmodule verilator-5.042/test_regress/t/t_protect_ids_bad.py0000755000542200017500000000114715101701376023116 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=[ "--protect-ids", "--trace", "--public", "--vpi", ], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dpi_threads.py0000755000542200017500000000101715101701376022253 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vltmt') test.compile(v_flags2=["t/t_dpi_threads_c.cpp --no-threads-coarsen"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_virtual_opt.v0000644000542200017500000000146715101701376024200 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 interface Bus; logic [7:0] data; endinterface class Cls; virtual Bus vbus; function void check(logic [7:0] data); if (vbus.data != data) $stop; endfunction endclass module t (clk); input clk; int cyc = 0; Bus bus(); virtual Bus vbus; Cls obj; assign bus.data = 'hFA; always @(posedge clk) begin cyc <= cyc + 1; if (cyc == 1) begin obj = new; vbus = bus; obj.vbus = bus; end else if (cyc == 2) begin obj.check('hFA); $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_flag_woff.v0000644000542200017500000000101515101701376021527 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; // width warnings off due to command line wire A = 15'd1234; // width warnings off due to command line + manual switch // verilator lint_off WIDTH wire B = 15'd1234; // this turnon does nothing as off on command line // verilator lint_on WIDTH wire C = 15'd1234; endmodule verilator-5.042/test_regress/t/t_probdist_cmake.py0000755000542200017500000000106615101701376022757 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_probdist.v" test.compile(verilator_make_gmake=False, verilator_make_cmake=True) test.execute() test.passes() verilator-5.042/test_regress/t/t_process_bad.py0000755000542200017500000000106515101701376022254 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--json-only", "--timing"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_uses_this.py0000755000542200017500000000073415101701376023165 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_assigndly_dynamic_notiming_bad.py0000755000542200017500000000103315101701376026176 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.lint(verilator_flags2=["--no-timing"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_waiveroutput_allgood.py0000755000542200017500000000126015101701376024244 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_waiveroutput.v" out_filename = test.obj_dir + "/" + test.name + ".waiver_gen.vlt" # Note no Wall test.lint(v_flags2=['-Wno-WIDTH', '--waiver-output', out_filename]) test.files_identical(out_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_var_xref_bad.py0000755000542200017500000000077615101701376022422 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_stream_bad.out0000644000542200017500000000203615101701376022244 0ustar mahmoudyfreeshell%Error: t/t_stream_bad.v:14:25: Expecting expression to be constant, but can't convert a RAND to constant. : ... note: In instance 't' 14 | packed_data_32 = {<<$random{byte_in}}; | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_stream_bad.v:14:23: Slice size isn't a constant or basic data type. : ... note: In instance 't' 14 | packed_data_32 = {<<$random{byte_in}}; | ^~ %Error: t/t_stream_bad.v:15:25: Expecting expression to be constant, but variable isn't const: 'x' : ... note: In instance 't' 15 | packed_data_32 = {<') # for and test.file_grep(out_filename, r' signed=') # for test.file_grep(out_filename, r' func=') # for test.passes() verilator-5.042/test_regress/t/t_randomize_method_with_scoping.v0000644000542200017500000000540115101701376025705 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class c1; rand int c1_f; endclass class c2; rand int c2_f; endclass localparam int PARAM = 42; class Cls; rand int x; int q[$] = {0}; rand enum { ONE_Y, TWO_Y } y; virtual function int get_x(); return x; endfunction endclass class SubA extends Cls; c1 e = new; rand enum { AMBIG, ONE_A, TWO_A } en; function c1 get_c(); return e; endfunction function int op(int v); return v + 1; endfunction endclass class SubB extends Cls; int z; endclass class SubC extends SubB; c2 e = new; rand enum { AMBIG, ONE_B, TWO_B } en; SubA f = new; function c2 get_c(); return e; endfunction function int op(int v); return v - 1; endfunction function int doit; // access ambiguous names so width complains if we miss something doit = 1; f.x = 4; x = 5; doit = f.randomize() with { x == local::x; }; if (f.x != x) $stop; z = 6; doit &= f.randomize() with { x == z; }; if (f.x != z) $stop; doit &= f.randomize() with { e.c1_f == local::e.c2_f; }; doit &= f.randomize() with { get_x() == local::get_x(); }; doit &= f.randomize() with { get_c().c1_f == local::get_c().c2_f; }; doit &= f.randomize() with { (get_c).c1_f == (local::get_c).c2_f; }; f.y = ONE_Y; y = TWO_Y; doit &= f.randomize() with { y == local::y; }; if (f.y != y) $stop; f.en = SubA::ONE_A; doit &= f.randomize() with { en == AMBIG; }; if (doit != 1) $stop; if (f.en != SubA::AMBIG) $stop; doit &= f.randomize() with { x == PARAM; }; if (doit != 1) $stop; if (f.x != PARAM) $stop; f.en = SubA::ONE_A; doit &= f.randomize() with { en == ONE_A; }; doit &= f.randomize() with { local::en == local::AMBIG; }; en = ONE_B; doit &= f.randomize() with { local::en == ONE_B; }; doit &= f.randomize() with { x == local::op(op(0)); }; if (f.x != 0) $stop; doit &= f.randomize() with { x == op(local::op(1)); }; if (f.x != 1) $stop; doit &= f.randomize() with { x == local::op(op(local::op(op(0)))); }; if (f.x != 0) $stop; doit &= f.randomize() with { x == op(local::op(op(local::op(1)))); }; if (f.x != 1) $stop; doit &= f.randomize() with { foreach (q[i]) x == i; }; if (f.x != 0) $stop; endfunction endclass module t; SubC obj = new; initial begin if (obj.doit != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_flag_nomod_bad.v0000644000542200017500000000034615101701376022516 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define EMPTY 1 verilator-5.042/test_regress/t/t_altera_lpm_abs.py0000755000542200017500000000111115101701376022725 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) test.compile(verilator_flags2=["--top-module", module]) test.passes() verilator-5.042/test_regress/t/t_lint_width_genfor.v0000644000542200017500000000143215101701376023305 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs rc, rg, ri, rp ); parameter P = 15; output reg [3:0] rc; output reg [3:0] rg; output reg [3:0] ri; output reg [3:0] rp; for (genvar g=0; g < 15; ++g) begin // bug1487 // This isn't a width violation, as genvars are generally 32 bits initial begin rg = g; rp = P; rc = 1; end end initial begin for (integer i=0; i < 15; ++i) begin /* verilator lint_off WIDTH */ ri = i; /* verilator lint_on WIDTH */ end end endmodule verilator-5.042/test_regress/t/t_class_param_nested_bad.v0000644000542200017500000000253115101701376024236 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Arkadiusz Kozdra. // SPDX-License-Identifier: CC0-1.0 typedef class Cls; class Wrap #(parameter P = 13); function int get_p; return c1.get_p(); endfunction function new; c1 = new; endfunction Cls#(PMINUS1 + 1) c1; localparam PMINUS1 = P - 1; // Checking works when last endclass class Wrap2 #(parameter P = 35); function int get_p; return c1.get_p(); endfunction function new; c1 = new; endfunction Wrap#(PMINUS1 + 1) c1; localparam PMINUS1 = P - 1; // Checking works when last endclass class Cls #(parameter PBASE = 12); bit [PBASE-1:0] member; function bit [PBASE-1:0] get_member; return member; endfunction static function int get_p; return PBASE; endfunction typedef enum { E_PBASE = PBASE } enum_t; endclass typedef Cls#(8) Cls8_t; module t; Cls c12; Cls #(.PBASE(4)) c4; Cls8_t c8; Wrap #(.P(16)) w16; Wrap2 #(.P(32)) w32; Wrap2 #(Wrap#(19)::PBASE * 2) w38; initial begin c12 = new; c4 = new; c8 = new; w16 = new; w32 = new; w38 = new; if (w38.get_p() != 38) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_lint_top_bad.py0000755000542200017500000000106615101701376022427 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=['-O0 --trace-fst'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_flag_parameter_hier.py0000755000542200017500000000217515101701376023753 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile( # For Verilator, all PARAMs at all levels are overridden # Error if parameter not found #verilator_flags2 = ['-GPARAM=10 -Gtop.t.x.HIER=20'], # HIER would error verilator_flags2=['-GPARAM=10'], # For NC, always implies a hierarchy, only HIER will be set # Warns if sets nothing nc_flags2=['+defparam+PARAM=10 +defparam+top.t.x.HIER=20'], # For VCS, all PARAMs at all levels are overridden. Hierarchy not allowed. # Informational on all overrides vcs_flags2=['-pvalue+PARAM=10 -px.HIER=20'], # For icarus -P without hierarchy does nothing, only can ref into top iv_flags2=['-PPARAM=10', '-Ptop.HIER=30', '-Ptop.t.x.HIER=20']) test.execute() test.passes() verilator-5.042/test_regress/t/t_foreach_nindex_bad.v0000644000542200017500000000053015101701376023360 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; int array[2][2]; initial begin foreach (array[i, j, badk, badl]); // bad $stop; end endmodule verilator-5.042/test_regress/t/t_func_while2.v0000644000542200017500000000155015101701376022006 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilog_format: off `define stop $stop `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); // verilog_format: on module t; int i; string value; function automatic int count(); ++i; value = {value, $sformatf(" count%0d", i)}; return i; endfunction initial begin value = ""; i = 0; while (count() <= 2) begin // verilator unroll_disable value = {value, " loop"}; end `checks(value, " count1 loop count2 loop count3"); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_clk_concat3.v0000644000542200017500000000366215101701376021772 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty. // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off ASCRANGE */ module some_module ( input wrclk ); logic [ 1 : 0 ] some_state; logic [1:0] some_other_state; always @(posedge wrclk) begin case (some_state) 2'b11: if (some_other_state == 0) some_state <= 2'b00; default: $display ("This is a display statement"); endcase if (wrclk) some_other_state <= 0; end endmodule `define BROKEN module t1( input [-12:-9] i_clks, input i_clk0, input i_clk1 ); some_module some_module ( `ifdef BROKEN .wrclk (i_clks[-12]) `else .wrclk (i_clk1) `endif ); endmodule module t2( input [2:0] i_clks, input i_clk0, input i_clk1, input i_clk2, input i_data ); logic [-12:-9] the_clks; logic data_q; assign the_clks[-12] = i_clk1; assign the_clks[-11] = i_clk2; assign the_clks[-10] = i_clk1; assign the_clks[-9] = i_clk0; always @(posedge i_clk0) begin data_q <= i_data; end t1 t1 ( .i_clks (the_clks), .i_clk0 (i_clk0), .i_clk1 (i_clk1) ); endmodule module t( input clk0 /*verilator clocker*/, input clk1 /*verilator clocker*/, input clk2 /*verilator clocker*/, input data_in ); logic [2:0] clks; assign clks = {1'b0, clk1, clk0}; t2 t2 ( .i_clks (clks), .i_clk0 (clk0), .i_clk1 (clk1), .i_clk2 (clk2), .i_data (data_in) ); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_savable_coverage_bad.out0000644000542200017500000000030115101701376024232 0ustar mahmoudyfreeshell%Error: Unsupported: --coverage and --savable not supported together ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_inside_tolerance_unsup.out0000644000542200017500000000675715101701376024722 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_inside_tolerance_unsup.v:18:23: Unsupported: +/- range 18 | do if ((r inside {[1492 +/- 2]}) !== (1'b1)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", "t/t_inside_tolerance_unsup.v",18, (r inside {[1492 +/- 2]}), (1'b1), "r inside {[1492 +/- 2]}", "1'b1"); $stop; end while(0);; | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_inside_tolerance_unsup.v:18:160: Unsupported: +/- range 18 | do if ((r inside {[1492 +/- 2]}) !== (1'b1)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", "t/t_inside_tolerance_unsup.v",18, (r inside {[1492 +/- 2]}), (1'b1), "r inside {[1492 +/- 2]}", "1'b1"); $stop; end while(0);; | ^ %Error-UNSUPPORTED: t/t_inside_tolerance_unsup.v:19:23: Unsupported: +/- range 19 | do if ((r inside {[1482 +/- 2]}) !== (1'b0)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", "t/t_inside_tolerance_unsup.v",19, (r inside {[1482 +/- 2]}), (1'b0), "r inside {[1482 +/- 2]}", "1'b0"); $stop; end while(0);; | ^ %Error-UNSUPPORTED: t/t_inside_tolerance_unsup.v:19:160: Unsupported: +/- range 19 | do if ((r inside {[1482 +/- 2]}) !== (1'b0)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", "t/t_inside_tolerance_unsup.v",19, (r inside {[1482 +/- 2]}), (1'b0), "r inside {[1482 +/- 2]}", "1'b0"); $stop; end while(0);; | ^ %Error-UNSUPPORTED: t/t_inside_tolerance_unsup.v:20:23: Unsupported: +%- range 20 | do if ((r inside {[1490 +%- 10]}) !== (1'b1)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", "t/t_inside_tolerance_unsup.v",20, (r inside {[1490 +%- 10]}), (1'b1), "r inside {[1490 +%- 10]}", "1'b1"); $stop; end while(0);; | ^ %Error-UNSUPPORTED: t/t_inside_tolerance_unsup.v:20:161: Unsupported: +%- range 20 | do if ((r inside {[1490 +%- 10]}) !== (1'b1)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", "t/t_inside_tolerance_unsup.v",20, (r inside {[1490 +%- 10]}), (1'b1), "r inside {[1490 +%- 10]}", "1'b1"); $stop; end while(0);; | ^ %Error-UNSUPPORTED: t/t_inside_tolerance_unsup.v:21:23: Unsupported: +%- range 21 | do if ((r inside {[1090 +%- 10]}) !== (1'b0)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", "t/t_inside_tolerance_unsup.v",21, (r inside {[1090 +%- 10]}), (1'b0), "r inside {[1090 +%- 10]}", "1'b0"); $stop; end while(0);; | ^ %Error-UNSUPPORTED: t/t_inside_tolerance_unsup.v:21:161: Unsupported: +%- range 21 | do if ((r inside {[1090 +%- 10]}) !== (1'b0)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", "t/t_inside_tolerance_unsup.v",21, (r inside {[1090 +%- 10]}), (1'b0), "r inside {[1090 +%- 10]}", "1'b0"); $stop; end while(0);; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_lint_stmtdly_bad.py0000755000542200017500000000146215101701376023325 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--no-timing"], fails=True, expect_filename=test.golden_filename) test.extract(in_filename=test.top_filename, out_filename=test.root + "/docs/gen/ex_STMTDLY_faulty.rst", lines="10") test.extract(in_filename=test.golden_filename, out_filename=test.root + "/docs/gen/ex_STMTDLY_msg.rst", lines="1") test.passes() verilator-5.042/test_regress/t/t_timing_nba_1.v0000644000542200017500000000164615101701376022136 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; integer cyc = 0; reg [7:0] a; reg [127:0] b; always #1 begin cyc <= cyc + 1; if (cyc == 0) begin a <= 8'hFF; a[7] <= 1'b0; end else if (cyc == 1) begin `ifdef TEST_VERBOSE $write("a = %x\n", a); `endif if (a != 8'h7F) $stop; end else if (cyc == 2) begin b <= 128'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; b[127] <= 1'b0; end else if (cyc == 3) begin `ifdef TEST_VERBOSE $write("b = %x\n", b); `endif if (b != 128'h7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF) $stop; end else if (cyc > 3) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_hier_block_type_param_multiple_instances.v0000644000542200017500000000150515101701376030105 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t( clk ); input clk; logic [21:0] in1; logic [21:0] out1; assign in1 = 0; Test #(.TYPE_t(logic[21:0])) test(.out (out1), .in (in1)); logic [63:0] in2; logic [63:0] out2; assign in2 = 0; Test #(.TYPE_t(logic[63:0])) test2(.out (out2), .in (in2)); always @ (posedge clk) begin if (out1 !== ~in1) $stop; if (out2 !== ~in2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module Test #(parameter type TYPE_t = logic [4:0]) ( output TYPE_t out, input TYPE_t in ); /*verilator hier_block*/ assign out = ~ in; endmodule verilator-5.042/test_regress/t/t_flag_f_bad_getenvend.py0000755000542200017500000000106415101701376024052 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(v_flags2=["-f t/t_flag_f_bad_getenvend.vc"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_func_complex_noinl.py0000755000542200017500000000105015101701376023643 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 test.top_filename = "t/t_func_complex.v" import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=["+define+TEST_NOINLINE"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_hier_block_chained.v0000644000542200017500000002131415101701376023355 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 // Based on tests emitted by t_gate_tree.py module t (clk); input clk; logic reset; reg [255:0] v2_0; reg [255:0] v1_0; reg [255:0] v1_1; reg [255:0] v1_2; reg [255:0] v1_3; reg [255:0] v1_4; reg [255:0] v1_5; reg [255:0] v1_6; reg [255:0] v1_7; // verilator lint_off MULTIDRIVEN reg [255:0] dummy; // verilator lint_on MULTIDRIVEN Calculate calc0(.clk(clk), .reset(reset), .v1_0(v1_0), .v1_1(dummy), .v1_2(dummy), .v1_3(dummy), .v1_4(dummy), .v1_5(dummy), .v1_6(dummy), .v1_7(dummy)); Calculate calc1(.clk(clk), .reset(reset), .v1_0(dummy), .v1_1(v1_1), .v1_2(dummy), .v1_3(dummy), .v1_4(dummy), .v1_5(dummy), .v1_6(dummy), .v1_7(dummy)); Calculate calc2(.clk(clk), .reset(reset), .v1_0(dummy), .v1_1(dummy), .v1_2(v1_2), .v1_3(dummy), .v1_4(dummy), .v1_5(dummy), .v1_6(dummy), .v1_7(dummy)); Calculate calc3(.clk(clk), .reset(reset), .v1_0(dummy), .v1_1(dummy), .v1_2(dummy), .v1_3(v1_3), .v1_4(dummy), .v1_5(dummy), .v1_6(dummy), .v1_7(dummy)); Calculate calc4(.clk(clk), .reset(reset), .v1_0(dummy), .v1_1(dummy), .v1_2(dummy), .v1_3(dummy), .v1_4(v1_4), .v1_5(dummy), .v1_6(dummy), .v1_7(dummy)); Calculate calc5(.clk(clk), .reset(reset), .v1_0(dummy), .v1_1(dummy), .v1_2(dummy), .v1_3(dummy), .v1_4(dummy), .v1_5(v1_5), .v1_6(dummy), .v1_7(dummy)); Calculate calc6(.clk(clk), .reset(reset), .v1_0(dummy), .v1_1(dummy), .v1_2(dummy), .v1_3(dummy), .v1_4(dummy), .v1_5(dummy), .v1_6(v1_6), .v1_7(dummy)); Calculate calc7(.clk(clk), .reset(reset), .v1_0(dummy), .v1_1(dummy), .v1_2(dummy), .v1_3(dummy), .v1_4(dummy), .v1_5(dummy), .v1_6(dummy), .v1_7(v1_7)); always @ (posedge clk) v2_0 <= v1_0 + v1_1 + v1_2 + v1_3 + v1_4 + v1_5 + v1_6 + v1_7; Check chk(.clk(clk), .reset(reset), .v2_0(v2_0)); endmodule module Check(input clk, output logic reset, input reg [255:0] v2_0); integer cyc=0; always @ (posedge clk) begin cyc <= cyc + 1; `ifdef TEST_VERBOSE $write("[%0t] rst=%0x v0_0=%0x v1_0=%0x result=%0x\n", $time, reset, v0_0, v1_0, v2_0); `endif if (cyc==0) begin reset <= 1; end else if (cyc==10) begin reset <= 0; end `ifndef SIM_CYCLES `define SIM_CYCLES 99 `endif else if (cyc==`SIM_CYCLES) begin if (v2_0 != 256'd2017) $stop; $write("VARS=64 WIDTH=256 WORKINGSET=2KB\n"); $write("*-* All Finished *-*\n"); $finish; end end endmodule module Calculate(input clk, input reset, output reg [255:0] v1_0, output reg [255:0] v1_1, output reg [255:0] v1_2, output reg [255:0] v1_3, output reg [255:0] v1_4, output reg [255:0] v1_5, output reg [255:0] v1_6, output reg [255:0] v1_7 ); reg [255:0] v0_0; reg [255:0] v0_1; reg [255:0] v0_2; reg [255:0] v0_3; reg [255:0] v0_4; reg [255:0] v0_5; reg [255:0] v0_6; reg [255:0] v0_7; reg [255:0] v0_8; reg [255:0] v0_9; reg [255:0] v0_10; reg [255:0] v0_11; reg [255:0] v0_12; reg [255:0] v0_13; reg [255:0] v0_14; reg [255:0] v0_15; reg [255:0] v0_16; reg [255:0] v0_17; reg [255:0] v0_18; reg [255:0] v0_19; reg [255:0] v0_20; reg [255:0] v0_21; reg [255:0] v0_22; reg [255:0] v0_23; reg [255:0] v0_24; reg [255:0] v0_25; reg [255:0] v0_26; reg [255:0] v0_27; reg [255:0] v0_28; reg [255:0] v0_29; reg [255:0] v0_30; reg [255:0] v0_31; reg [255:0] v0_32; reg [255:0] v0_33; reg [255:0] v0_34; reg [255:0] v0_35; reg [255:0] v0_36; reg [255:0] v0_37; reg [255:0] v0_38; reg [255:0] v0_39; reg [255:0] v0_40; reg [255:0] v0_41; reg [255:0] v0_42; reg [255:0] v0_43; reg [255:0] v0_44; reg [255:0] v0_45; reg [255:0] v0_46; reg [255:0] v0_47; reg [255:0] v0_48; reg [255:0] v0_49; reg [255:0] v0_50; reg [255:0] v0_51; reg [255:0] v0_52; reg [255:0] v0_53; reg [255:0] v0_54; reg [255:0] v0_55; reg [255:0] v0_56; reg [255:0] v0_57; reg [255:0] v0_58; reg [255:0] v0_59; reg [255:0] v0_60; reg [255:0] v0_61; reg [255:0] v0_62; reg [255:0] v0_63; always @ (posedge clk) v0_0 <= reset ? 256'd1 : v0_1; always @ (posedge clk) v0_1 <= reset ? 256'd1 : v0_2; always @ (posedge clk) v0_2 <= reset ? 256'd2 : v0_3; always @ (posedge clk) v0_3 <= reset ? 256'd3 : v0_4; always @ (posedge clk) v0_4 <= reset ? 256'd4 : v0_5; always @ (posedge clk) v0_5 <= reset ? 256'd5 : v0_6; always @ (posedge clk) v0_6 <= reset ? 256'd6 : v0_7; always @ (posedge clk) v0_7 <= reset ? 256'd7 : v0_0; always @ (posedge clk) v0_8 <= reset ? 256'd8 : v0_9; always @ (posedge clk) v0_9 <= reset ? 256'd9 : v0_10; always @ (posedge clk) v0_10 <= reset ? 256'd10 : v0_11; always @ (posedge clk) v0_11 <= reset ? 256'd11 : v0_12; always @ (posedge clk) v0_12 <= reset ? 256'd12 : v0_13; always @ (posedge clk) v0_13 <= reset ? 256'd13 : v0_14; always @ (posedge clk) v0_14 <= reset ? 256'd14 : v0_15; always @ (posedge clk) v0_15 <= reset ? 256'd15 : v0_8; always @ (posedge clk) v0_16 <= reset ? 256'd16 : v0_17; always @ (posedge clk) v0_17 <= reset ? 256'd17 : v0_18; always @ (posedge clk) v0_18 <= reset ? 256'd18 : v0_19; always @ (posedge clk) v0_19 <= reset ? 256'd19 : v0_20; always @ (posedge clk) v0_20 <= reset ? 256'd20 : v0_21; always @ (posedge clk) v0_21 <= reset ? 256'd21 : v0_22; always @ (posedge clk) v0_22 <= reset ? 256'd22 : v0_23; always @ (posedge clk) v0_23 <= reset ? 256'd23 : v0_16; always @ (posedge clk) v0_24 <= reset ? 256'd24 : v0_25; always @ (posedge clk) v0_25 <= reset ? 256'd25 : v0_26; always @ (posedge clk) v0_26 <= reset ? 256'd26 : v0_27; always @ (posedge clk) v0_27 <= reset ? 256'd27 : v0_28; always @ (posedge clk) v0_28 <= reset ? 256'd28 : v0_29; always @ (posedge clk) v0_29 <= reset ? 256'd29 : v0_30; always @ (posedge clk) v0_30 <= reset ? 256'd30 : v0_31; always @ (posedge clk) v0_31 <= reset ? 256'd31 : v0_24; always @ (posedge clk) v0_32 <= reset ? 256'd32 : v0_33; always @ (posedge clk) v0_33 <= reset ? 256'd33 : v0_34; always @ (posedge clk) v0_34 <= reset ? 256'd34 : v0_35; always @ (posedge clk) v0_35 <= reset ? 256'd35 : v0_36; always @ (posedge clk) v0_36 <= reset ? 256'd36 : v0_37; always @ (posedge clk) v0_37 <= reset ? 256'd37 : v0_38; always @ (posedge clk) v0_38 <= reset ? 256'd38 : v0_39; always @ (posedge clk) v0_39 <= reset ? 256'd39 : v0_32; always @ (posedge clk) v0_40 <= reset ? 256'd40 : v0_41; always @ (posedge clk) v0_41 <= reset ? 256'd41 : v0_42; always @ (posedge clk) v0_42 <= reset ? 256'd42 : v0_43; always @ (posedge clk) v0_43 <= reset ? 256'd43 : v0_44; always @ (posedge clk) v0_44 <= reset ? 256'd44 : v0_45; always @ (posedge clk) v0_45 <= reset ? 256'd45 : v0_46; always @ (posedge clk) v0_46 <= reset ? 256'd46 : v0_47; always @ (posedge clk) v0_47 <= reset ? 256'd47 : v0_40; always @ (posedge clk) v0_48 <= reset ? 256'd48 : v0_49; always @ (posedge clk) v0_49 <= reset ? 256'd49 : v0_50; always @ (posedge clk) v0_50 <= reset ? 256'd50 : v0_51; always @ (posedge clk) v0_51 <= reset ? 256'd51 : v0_52; always @ (posedge clk) v0_52 <= reset ? 256'd52 : v0_53; always @ (posedge clk) v0_53 <= reset ? 256'd53 : v0_54; always @ (posedge clk) v0_54 <= reset ? 256'd54 : v0_55; always @ (posedge clk) v0_55 <= reset ? 256'd55 : v0_48; always @ (posedge clk) v0_56 <= reset ? 256'd56 : v0_57; always @ (posedge clk) v0_57 <= reset ? 256'd57 : v0_58; always @ (posedge clk) v0_58 <= reset ? 256'd58 : v0_59; always @ (posedge clk) v0_59 <= reset ? 256'd59 : v0_60; always @ (posedge clk) v0_60 <= reset ? 256'd60 : v0_61; always @ (posedge clk) v0_61 <= reset ? 256'd61 : v0_62; always @ (posedge clk) v0_62 <= reset ? 256'd62 : v0_63; always @ (posedge clk) v0_63 <= reset ? 256'd63 : v0_56; always @ (posedge clk) v1_0 <= v0_0 + v0_1 + v0_2 + v0_3 + v0_4 + v0_5 + v0_6 + v0_7; always @ (posedge clk) v1_1 <= v0_8 + v0_9 + v0_10 + v0_11 + v0_12 + v0_13 + v0_14 + v0_15; always @ (posedge clk) v1_2 <= v0_16 + v0_17 + v0_18 + v0_19 + v0_20 + v0_21 + v0_22 + v0_23; always @ (posedge clk) v1_3 <= v0_24 + v0_25 + v0_26 + v0_27 + v0_28 + v0_29 + v0_30 + v0_31; always @ (posedge clk) v1_4 <= v0_32 + v0_33 + v0_34 + v0_35 + v0_36 + v0_37 + v0_38 + v0_39; always @ (posedge clk) v1_5 <= v0_40 + v0_41 + v0_42 + v0_43 + v0_44 + v0_45 + v0_46 + v0_47; always @ (posedge clk) v1_6 <= v0_48 + v0_49 + v0_50 + v0_51 + v0_52 + v0_53 + v0_54 + v0_55; always @ (posedge clk) v1_7 <= v0_56 + v0_57 + v0_58 + v0_59 + v0_60 + v0_61 + v0_62 + v0_63; endmodule verilator-5.042/test_regress/t/t_lint_noreturn_bad.out0000644000542200017500000000072015101701376023651 0ustar mahmoudyfreeshell%Warning-NORETURN: t/t_lint_noreturn.v:11:16: Non-void function 'no_rtn' has no return value : ... note: In instance 't' 11 | function int no_rtn(); | ^~~~~~ ... For warning description see https://verilator.org/warn/NORETURN?v=latest ... Use "/* verilator lint_off NORETURN */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_implements_nested_bad.out0000644000542200017500000000051515101701376024470 0ustar mahmoudyfreeshell%Error: t/t_implements_nested_bad.v:9:17: Interface class shall not be nested within another interface class. (IEEE 1800-2023 8.26) 9 | interface class bad_cannot_nest; | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_lint_noreturn.py0000755000542200017500000000103115101701376022663 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.compile(verilator_flags2=['-Wall -Wno-DECLFILENAME -Wno-NORETURN']) test.execute() test.passes() verilator-5.042/test_regress/t/t_timing_sched_nba.py0000755000542200017500000000077115101701376023250 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_config_include_bad.py0000755000542200017500000000103015101701376023536 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["--lint-only"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_event_control_star.v0000644000542200017500000000132115101701376023507 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Based on ivtest's nested_impl_event1.v by Martin Whitaker. module t(); reg a; reg b; reg c; always @* begin // @(b or c) a = b; $display("[%0t] Triggered 1 @(b or c)", $time); @* a = c; // @(c) $display("[%0t] Triggered 2 @(c)", $time); end initial begin #10; b = 0; #10; b = 1; #10; c = 0; #10; c = 1; #10; c = 0; #10; $write("*-* All Finished *-*\n"); $finish(0); end endmodule verilator-5.042/test_regress/t/t_pli_bad.v0000644000542200017500000000074515101701376021200 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; integer i; initial begin $unknown_pli_task; $unknown_pli_task("arg", i); i = $unknown_pli_function; i = $unknown_pli_function("arg", i); $sformatff(); // Typo i = $sformatff(); // Typo $stop; end endmodule verilator-5.042/test_regress/t/t_mod_empty.py0000755000542200017500000000077715101701376021776 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--cc", "--dumpi-V3LinkDot", "6"]) test.passes() verilator-5.042/test_regress/t/t_trace_fst_sc_cmake.out0000644000542200017500000002546615101701376023756 0ustar mahmoudyfreeshell$date Sat Apr 5 13:56:27 2025 $end $version fstWriter $end $timescale 1ps $end $scope module top $end $scope module t $end $var wire 1 ! clk $end $var int 32 " cyc [31:0] $end $var logic 1 # rstn $end $var real_parameter 64 $ fst_gparam_real $end $var real_parameter 64 % fst_lparam_real $end $var real 64 $ fst_real $end $var integer 32 & fst_integer [31:0] $end $var bit 1 ' fst_bit $end $var logic 1 ( fst_logic $end $var int 32 ) fst_int [31:0] $end $var shortint 16 * fst_shortint [15:0] $end $var longint 64 + fst_longint [63:0] $end $var byte 8 , fst_byte [7:0] $end $var parameter 32 - fst_parameter [31:0] $end $var parameter 32 . fst_lparam [31:0] $end $var supply0 1 / fst_supply0 $end $var supply1 1 0 fst_supply1 $end $var tri0 1 / fst_tri0 $end $var tri1 1 0 fst_tri1 $end $var tri 1 1 fst_tri $end $var wire 1 2 fst_wire $end $var logic 5 3 state [4:0] $end $scope module test $end $var wire 1 ! clk $end $var wire 1 # rstn $end $var wire 5 3 state [4:0] $end $var logic 5 4 state_w [4:0] $end $var logic 5 5 state_array[0] [4:0] $end $var logic 5 6 state_array[1] [4:0] $end $var logic 5 7 state_array[2] [4:0] $end $scope module unnamedblk1 $end $var int 32 8 i [31:0] $end $upscope $end $scope module unnamedblk2 $end $var int 32 9 i [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b00000000000000000000000000000000 9 b00000000000000000000000000000000 8 b00000 7 b00000 6 b00000 5 b00000 4 b00000 3 02 01 10 0/ b00000000000000000000000111001000 . b00000000000000000000000001111011 - b00000000 , b0000000000000000000000000000000000000000000000000000000000000000 + b0000000000000000 * b00000000000000000000000000000000 ) 0( 0' b00000000000000000000000000000000 & r4.56 % r1.23 $ 0# b00000000000000000000000000000000 " 0! $end #10 1! b00000000000000000000000000000001 " b00001 3 b10100 4 b00001 5 b00001 6 b00001 7 b00000000000000000000000000000011 8 #15 0! #20 1! b00000000000000000000000000000010 " #25 0! #30 1! b00000000000000000000000000000011 " #35 0! #40 1! b00000000000000000000000000000100 " #45 0! #50 1! b00000000000000000000000000000101 " #55 0! #60 1! b00000000000000000000000000000110 " #65 0! #70 1! b00000000000000000000000000000111 " #75 0! #80 1! b00000000000000000000000000001000 " #85 0! #90 1! b00000000000000000000000000001001 " #95 0! #100 1! b00000000000000000000000000001010 " #105 0! #110 1! b00000000000000000000000000001011 " 1# #115 0! #120 1! b00000000000000000000000000001100 " b10100 7 b01010 4 b00000000000000000000000000000010 9 #125 0! #130 1! b00101 4 b01010 7 b00000000000000000000000000001101 " b10100 6 #135 0! #140 1! b01010 6 b00000000000000000000000000001110 " b00101 7 b10110 4 b10100 5 b10100 3 #145 0! #150 1! b01010 3 b01010 5 b01011 4 b10110 7 b00000000000000000000000000001111 " b00101 6 #155 0! #160 1! b10110 6 b00000000000000000000000000010000 " b01011 7 b10001 4 b00101 5 b00101 3 #165 0! #170 1! b10110 3 b10110 5 b11100 4 b10001 7 b00000000000000000000000000010001 " b01011 6 #175 0! #180 1! b10001 6 b00000000000000000000000000010010 " b11100 7 b01110 4 b01011 5 b01011 3 #185 0! #190 1! b10001 3 b10001 5 b00111 4 b01110 7 b00000000000000000000000000010011 " b11100 6 #195 0! #200 1! b01110 6 b00000000000000000000000000010100 " b00111 7 b10111 4 b11100 5 b11100 3 #205 0! #210 1! b01110 3 b01110 5 b11111 4 b10111 7 b00000000000000000000000000010101 " b00111 6 #215 0! #220 1! b10111 6 b00000000000000000000000000010110 " b11111 7 b11011 4 b00111 5 b00111 3 #225 0! #230 1! b10111 3 b10111 5 b11001 4 b11011 7 b00000000000000000000000000010111 " b11111 6 #235 0! #240 1! b11011 6 b00000000000000000000000000011000 " b11001 7 b11000 4 b11111 5 b11111 3 #245 0! #250 1! b11011 3 b11011 5 b01100 4 b11000 7 b00000000000000000000000000011001 " b11001 6 #255 0! #260 1! b11000 6 b00000000000000000000000000011010 " b01100 7 b00110 4 b11001 5 b11001 3 #265 0! #270 1! b11000 3 b11000 5 b00011 4 b00110 7 b00000000000000000000000000011011 " b01100 6 #275 0! #280 1! b00110 6 b00000000000000000000000000011100 " b00011 7 b10101 4 b01100 5 b01100 3 #285 0! #290 1! b00110 3 b00110 5 b11110 4 b10101 7 b00000000000000000000000000011101 " b00011 6 #295 0! #300 1! b10101 6 b00000000000000000000000000011110 " b11110 7 b01111 4 b00011 5 b00011 3 #305 0! #310 1! b10101 3 b10101 5 b10011 4 b01111 7 b00000000000000000000000000011111 " b11110 6 #315 0! #320 1! b01111 6 b00000000000000000000000000100000 " b10011 7 b11101 4 b11110 5 b11110 3 #325 0! #330 1! b01111 3 b01111 5 b11010 4 b11101 7 b00000000000000000000000000100001 " b10011 6 #335 0! #340 1! b11101 6 b00000000000000000000000000100010 " b11010 7 b01101 4 b10011 5 b10011 3 #345 0! #350 1! b11101 3 b11101 5 b10010 4 b01101 7 b00000000000000000000000000100011 " b11010 6 #355 0! #360 1! b01101 6 b00000000000000000000000000100100 " b10010 7 b01001 4 b11010 5 b11010 3 #365 0! #370 1! b01101 3 b01101 5 b10000 4 b01001 7 b00000000000000000000000000100101 " b10010 6 #375 0! #380 1! b01001 6 b00000000000000000000000000100110 " b10000 7 b01000 4 b10010 5 b10010 3 #385 0! #390 1! b01001 3 b01001 5 b00100 4 b01000 7 b00000000000000000000000000100111 " b10000 6 #395 0! #400 1! b01000 6 b00000000000000000000000000101000 " b00100 7 b00010 4 b10000 5 b10000 3 #405 0! #410 1! b01000 3 b01000 5 b00001 4 b00010 7 b00000000000000000000000000101001 " b00100 6 #415 0! #420 1! b00010 6 b00000000000000000000000000101010 " b00001 7 b10100 4 b00100 5 b00100 3 #425 0! #430 1! b00010 3 b00010 5 b01010 4 b10100 7 b00000000000000000000000000101011 " b00001 6 #435 0! #440 1! b10100 6 b00000000000000000000000000101100 " b01010 7 b00101 4 b00001 5 b00001 3 #445 0! #450 1! b10100 3 b10100 5 b10110 4 b00101 7 b00000000000000000000000000101101 " b01010 6 #455 0! #460 1! b00101 6 b00000000000000000000000000101110 " b10110 7 b01011 4 b01010 5 b01010 3 #465 0! #470 1! b00101 3 b00101 5 b10001 4 b01011 7 b00000000000000000000000000101111 " b10110 6 #475 0! #480 1! b01011 6 b00000000000000000000000000110000 " b10001 7 b11100 4 b10110 5 b10110 3 #485 0! #490 1! b01011 3 b01011 5 b01110 4 b11100 7 b00000000000000000000000000110001 " b10001 6 #495 0! #500 1! b11100 6 b00000000000000000000000000110010 " b01110 7 b00111 4 b10001 5 b10001 3 #505 0! #510 1! b11100 3 b11100 5 b10111 4 b00111 7 b00000000000000000000000000110011 " b01110 6 #515 0! #520 1! b00111 6 b00000000000000000000000000110100 " b10111 7 b11111 4 b01110 5 b01110 3 #525 0! #530 1! b00111 3 b00111 5 b11011 4 b11111 7 b00000000000000000000000000110101 " b10111 6 #535 0! #540 1! b11111 6 b00000000000000000000000000110110 " b11011 7 b11001 4 b10111 5 b10111 3 #545 0! #550 1! b11111 3 b11111 5 b11000 4 b11001 7 b00000000000000000000000000110111 " b11011 6 #555 0! #560 1! b11001 6 b00000000000000000000000000111000 " b11000 7 b01100 4 b11011 5 b11011 3 #565 0! #570 1! b11001 3 b11001 5 b00110 4 b01100 7 b00000000000000000000000000111001 " b11000 6 #575 0! #580 1! b01100 6 b00000000000000000000000000111010 " b00110 7 b00011 4 b11000 5 b11000 3 #585 0! #590 1! b01100 3 b01100 5 b10101 4 b00011 7 b00000000000000000000000000111011 " b00110 6 #595 0! #600 1! b00011 6 b00000000000000000000000000111100 " b10101 7 b11110 4 b00110 5 b00110 3 #605 0! #610 1! b00011 3 b00011 5 b01111 4 b11110 7 b00000000000000000000000000111101 " b10101 6 #615 0! #620 1! b11110 6 b00000000000000000000000000111110 " b01111 7 b10011 4 b10101 5 b10101 3 #625 0! #630 1! b11110 3 b11110 5 b11101 4 b10011 7 b00000000000000000000000000111111 " b01111 6 #635 0! #640 1! b10011 6 b00000000000000000000000001000000 " b11101 7 b11010 4 b01111 5 b01111 3 #645 0! #650 1! b10011 3 b10011 5 b01101 4 b11010 7 b00000000000000000000000001000001 " b11101 6 #655 0! #660 1! b11010 6 b00000000000000000000000001000010 " b01101 7 b10010 4 b11101 5 b11101 3 #665 0! #670 1! b11010 3 b11010 5 b01001 4 b10010 7 b00000000000000000000000001000011 " b01101 6 #675 0! #680 1! b10010 6 b00000000000000000000000001000100 " b01001 7 b10000 4 b01101 5 b01101 3 #685 0! #690 1! b10010 3 b10010 5 b01000 4 b10000 7 b00000000000000000000000001000101 " b01001 6 #695 0! #700 1! b10000 6 b00000000000000000000000001000110 " b01000 7 b00100 4 b01001 5 b01001 3 #705 0! #710 1! b10000 3 b10000 5 b00010 4 b00100 7 b00000000000000000000000001000111 " b01000 6 #715 0! #720 1! b00100 6 b00000000000000000000000001001000 " b00010 7 b00001 4 b01000 5 b01000 3 #725 0! #730 1! b00100 3 b00100 5 b10100 4 b00001 7 b00000000000000000000000001001001 " b00010 6 #735 0! #740 1! b00001 6 b00000000000000000000000001001010 " b10100 7 b01010 4 b00010 5 b00010 3 #745 0! #750 1! b00001 3 b00001 5 b00101 4 b01010 7 b00000000000000000000000001001011 " b10100 6 #755 0! #760 1! b01010 6 b00000000000000000000000001001100 " b00101 7 b10110 4 b10100 5 b10100 3 #765 0! #770 1! b01010 3 b01010 5 b01011 4 b10110 7 b00000000000000000000000001001101 " b00101 6 #775 0! #780 1! b10110 6 b00000000000000000000000001001110 " b01011 7 b10001 4 b00101 5 b00101 3 #785 0! #790 1! b10110 3 b10110 5 b11100 4 b10001 7 b00000000000000000000000001001111 " b01011 6 #795 0! #800 1! b10001 6 b00000000000000000000000001010000 " b11100 7 b01110 4 b01011 5 b01011 3 #805 0! #810 1! b10001 3 b10001 5 b00111 4 b01110 7 b00000000000000000000000001010001 " b11100 6 #815 0! #820 1! b01110 6 b00000000000000000000000001010010 " b00111 7 b10111 4 b11100 5 b11100 3 #825 0! #830 1! b01110 3 b01110 5 b11111 4 b10111 7 b00000000000000000000000001010011 " b00111 6 #835 0! #840 1! b10111 6 b00000000000000000000000001010100 " b11111 7 b11011 4 b00111 5 b00111 3 #845 0! #850 1! b10111 3 b10111 5 b11001 4 b11011 7 b00000000000000000000000001010101 " b11111 6 #855 0! #860 1! b11011 6 b00000000000000000000000001010110 " b11001 7 b11000 4 b11111 5 b11111 3 #865 0! #870 1! b11011 3 b11011 5 b01100 4 b11000 7 b00000000000000000000000001010111 " b11001 6 #875 0! #880 1! b11000 6 b00000000000000000000000001011000 " b01100 7 b00110 4 b11001 5 b11001 3 #885 0! #890 1! b11000 3 b11000 5 b00011 4 b00110 7 b00000000000000000000000001011001 " b01100 6 #895 0! #900 1! b00110 6 b00000000000000000000000001011010 " b00011 7 b10101 4 b01100 5 b01100 3 #905 0! #910 1! b00110 3 b00110 5 b11110 4 b10101 7 b00000000000000000000000001011011 " b00011 6 #915 0! #920 1! b10101 6 b00000000000000000000000001011100 " b11110 7 b01111 4 b00011 5 b00011 3 #925 0! #930 1! b10101 3 b10101 5 b10011 4 b01111 7 b00000000000000000000000001011101 " b11110 6 #935 0! #940 1! b01111 6 b00000000000000000000000001011110 " b10011 7 b11101 4 b11110 5 b11110 3 #945 0! #950 1! b01111 3 b01111 5 b11010 4 b11101 7 b00000000000000000000000001011111 " b10011 6 #955 0! #960 1! b11101 6 b00000000000000000000000001100000 " b11010 7 b01101 4 b10011 5 b10011 3 #965 0! #970 1! b11101 3 b11101 5 b10010 4 b01101 7 b00000000000000000000000001100001 " b11010 6 #975 0! #980 1! b01101 6 b00000000000000000000000001100010 " b10010 7 b01001 4 b11010 5 b11010 3 #985 0! #990 1! b01101 3 b01101 5 b10000 4 b01001 7 b00000000000000000000000001100011 " b10010 6 #995 0! #1000 1! b01001 6 b00000000000000000000000001100100 " b10000 7 b01000 4 b10010 5 b10010 3 #1004 verilator-5.042/test_regress/t/t_if_swap.v0000644000542200017500000000115515101701376021232 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer f; always @(posedge clk) begin if (!$feof(f)) begin $display("Doing stuff with file."); end // Commenting out these two lines fixes the fault else begin end if (!$feof(f)) begin end else begin $display("Not doing stuff with file."); end end endmodule verilator-5.042/test_regress/t/t_pp_lib_library.v0000644000542200017500000000054015101701376022570 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module library_cell(a); input [`WIDTH-1:0] a; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_display_signed.v0000644000542200017500000000326715101701376022606 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg signed [20:0] longp; reg signed [20:0] longn; reg signed [40:0] quadp; reg signed [40:0] quadn; reg signed [80:0] widep; reg signed [80:0] widen; initial begin longp = 21'shbbccc; longn = 21'shbbccc; longn[20] = 1'b1; quadp = 41'sh1_bbbb_cccc; quadn = 41'sh1_bbbb_cccc; quadn[40] = 1'b1; widep = 81'shbc_1234_5678_1234_5678; widen = 81'shbc_1234_5678_1234_5678; widen[40] = 1'b1; // Display formatting $display("[%0t] lp %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d %%p=%p %%0p=%0p", $time, longp, longp, longp, longp, longp, longp, longp, longp); $display("[%0t] ln %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d %%p=%p %%0p=%0p", $time, longn, longn, longn, longn, longn, longn, longn, longn); $display("[%0t] qp %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d %%p=%p %%0p=%0p", $time, quadp, quadp, quadp, quadp, quadp, quadp, quadp, quadp); $display("[%0t] qn %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d %%p=%p %%0p=%0p", $time, quadn, quadn, quadn, quadn, quadn, quadn, quadn, quadn); $display("[%0t] wp %%x=%x %%x=%x %%o=%o %%b=%b %%p=%p %%0p=%0p", $time, widep, widep, widep, widep, widep, widep); $display("[%0t] wn %%x=%x %%x=%x %%o=%o %%b=%b %%p=%p %%0p=%0p", $time, widen, widen, widen, widen, widen, widen); $display; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_sys_plusargs.py0000755000542200017500000000107715101701376022531 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=['-v', 't/t_flag_libinc.v']) test.execute(all_run_flags=['+PLUS +INT=1234 +STRSTR +REAL=1.2345 +IP%P101']) test.passes() verilator-5.042/test_regress/t/t_clk_concat4.py0000755000542200017500000000073415101701376022156 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_wire_trireg_unsup.py0000755000542200017500000000076315101701376023550 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_sys_readmem_b.mem0000644000542200017500000000067315101701376022730 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test data file // // Copyright 2006 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # SRecord style comment 010 0_1_1 100/*Space*/101// Space 110 111 @00_0_8 10000 @c 10100 10101 verilator-5.042/test_regress/t/t_func_recurse_param.v0000644000542200017500000000246415101701376023451 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilog_format: off `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); // verilog_format: on module t; function automatic int recurse_self; input int i; int r1; int r2; // Simulator support for statics in constant functions get varying results, not testing static int local_static = 10; automatic int local_automatic; // check each function call resets to zero if (i == 0) begin local_static = 0; recurse_self = 0; end else begin local_static = local_static + 1; local_automatic = local_automatic + 10; recurse_self = i + recurse_self(i - 1) * 2 + recurse_self(i - 1) * 3 + local_automatic; end endfunction localparam int F0 = recurse_self(0); localparam int F3 = recurse_self(3); localparam int F4 = recurse_self(4); initial begin `checkd(F0, 0); `checkd(F3, 348); `checkd(F4, 1754); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_lint_warn_line_bad.out0000644000542200017500000000100415101701376023747 0ustar mahmoudyfreeshell%Warning-WIDTHTRUNC: the_line_file:13:17: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's CONST '64'h1' generates 64 bits. : ... note: In instance 't' 13 | int warn_t = 64'h1; | ^~~~~ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_class_extends2.py0000755000542200017500000000101315101701376022702 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(make_flags=['VM_PARALLEL_BUILDS=1']) # bug2775) test.execute() test.passes() verilator-5.042/test_regress/t/t_typedef_fwd_bad.py0000755000542200017500000000110515101701376023071 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.top_filename = 't/t_typedef_fwd.v' test.lint(v_flags2=['+define+TEST_NO_TYPEDEFS'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_alw_reorder_no_acycsimp.py0000755000542200017500000000106015101701376024654 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = 't/t_alw_reorder.v' test.compile(verilator_flags2=["--stats", "-fno-acyc-simp"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_alw_combdly.v0000644000542200017500000000270015101701376022073 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg [31:0] a, b, c, d, e, f, g, h; always @ (*) begin // Test Verilog 2001 (*) // verilator lint_off COMBDLY c <= a | b; // verilator lint_on COMBDLY end always @ (posedge (clk)) begin // always bug 2008/4/18 d <= a | b; end always @ ((d)) begin // always bug 2008/4/18 e = d; end parameter CONSTANT = 1; always @ (e, 1'b0, CONSTANT) begin // not technically legal, see bug412 f = e; end always @ (1'b0, CONSTANT, f) begin // not technically legal, see bug412 g = f; end always @ ({CONSTANT, g}) begin // bug745 h = g; end //always @ ((posedge b) or (a or b)) begin // note both illegal always @ (posedge clk) begin if (cyc!=0) begin cyc<=cyc+1; if (cyc==1) begin a <= 32'hfeed0000; b <= 32'h0000face; end if (cyc==2) begin if (c != 32'hfeedface) $stop; end if (cyc==3) begin if (h != 32'hfeedface) $stop; end if (cyc==7) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.042/test_regress/t/t_static_dup_name.py0000755000542200017500000000077115101701376023132 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.verilated_randReset = 1 test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_virtual_pure.py0000755000542200017500000000073415101701376023700 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_constraint_state.v0000644000542200017500000000272715101701376023174 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `define check_rand(cl, field, cond) \ begin \ longint prev_result; \ int ok = 0; \ if (!bit'(cl.randomize())) $stop; \ prev_result = longint'(field); \ if (!(cond)) $stop; \ repeat(9) begin \ longint result; \ if (!bit'(cl.randomize())) $stop; \ result = longint'(field); \ if (!(cond)) $stop; \ if (result != prev_result) ok = 1; \ prev_result = result; \ end \ if (ok != 1) $stop; \ end class Foo; int x; endclass class Bar; rand int y; endclass class Packet; rand int rf; int state; rand int a; rand Foo foo; Bar bar; constraint c1 { rf == state; } constraint c2 { a > foo.x; a < bar.y; } function new(int s, int x, int y); state = s; foo = new; foo.x = x; bar = new; bar.y = y; endfunction endclass module t; Packet p; int v; initial begin p = new(123, 10, 20); v = p.randomize(); if (v != 1) $stop; if (p.rf != 123) $stop; `check_rand(p, p.a, p.a > 10 && p.a < 20) if (p.foo.x != 10) $stop; if (p.bar.y != 20) $stop; p.state = 234; v = p.randomize(); if (v != 1) $stop; if (p.rf != 234) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_param_pattern_init.v0000644000542200017500000000462415101701376023466 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); package some_pkg; localparam FOO = 5; localparam BAR = 6; typedef enum int { QUX = 7 } pkg_enum_t; endpackage module t (/*AUTOARG*/ // Inputs clk ); input clk; int cyc = 0; localparam int unsigned SPI_INDEX = 0; localparam int unsigned I2C_INDEX = 1; localparam int unsigned TMR_INDEX = 4; localparam logic [31:0] AHB_ADDR[6] = '{ SPI_INDEX: 32'h80001000, I2C_INDEX: 32'h80002000, TMR_INDEX: 32'h80003000, default: '0}; initial begin `checkh(AHB_ADDR[0], 32'h80001000); `checkh(AHB_ADDR[1], 32'h80002000); `checkh(AHB_ADDR[2], 32'h0); `checkh(AHB_ADDR[3], 32'h0); `checkh(AHB_ADDR[4], 32'h80003000); `checkh(AHB_ADDR[5], 32'h0); end genvar genvar_i; for (genvar_i = 0; genvar_i < 2; genvar_i++) begin: the_gen logic [31:0] gen_array [10]; always_comb gen_array = '{ genvar_i: 32'habcd, default: 0 }; always_ff @(posedge clk) begin `checkh(gen_array[genvar_i], 32'habcd); end end typedef enum int { ENUM_A = 0, ENUM_B, ENUM_C } enum_t; logic [31:0] enum_array [11]; always_comb enum_array = '{ ENUM_A: 32'h1234, ENUM_B: 32'h7777, ENUM_C: 32'ha5a5, default: 0 }; always_ff @(posedge clk) begin `checkh(enum_array[0], 32'h1234); `checkh(enum_array[1], 32'h7777); `checkh(enum_array[2], 32'ha5a5); end logic [31:0] package_array [8]; import some_pkg::*; always_comb package_array = '{ FOO: 32'h9876, BAR: 32'h1212, QUX: 32'h5432, default: 0 }; always_ff @(posedge clk) begin `checkh(package_array[5], 32'h9876); `checkh(package_array[6], 32'h1212); `checkh(package_array[7], 32'h5432); end always_ff @(posedge clk) begin cyc <= cyc + 1; if (cyc == 2) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_flag_parameter_bad.out0000644000542200017500000000033515101701376023722 0ustar mahmoudyfreeshell%Error: Parameters from the command line were not found in the design: PARAM_THAT_DOES_NON_EXIST ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_trace_packed_struct_fst_sc.py0000755000542200017500000000124415101701376025341 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_packed_struct.v" if not test.have_sc: test.skip("No SystemC installed") test.compile(v_flags2=["--sc --trace-fst"]) test.execute() test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_select_plus.py0000755000542200017500000000073415101701376022314 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_down_noinl.py0000755000542200017500000000103715101701376024155 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_down.v" test.compile(v_flags2=["-fno-inline"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_mod_topmodule_nest.v0000644000542200017500000000151415101701376023501 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This test verifies that a top-module can be specified which // is instantiated beneath another module in the compiled source // code, even when that top-module has a module both above and beside // it in the hierarchy. // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Dan Petrisko. // SPDX-License-Identifier: CC0-1.0 module top(/*AUTOARG*/ // Inputs clk ); input clk; always_ff @(posedge clk) begin $write("*-* All Finished *-*\n"); $finish(); end under under(); endmodule module under(/*AUTOARG*/ ); endmodule module faketop(/*AUTOARG*/ ); under under(); top top(); // Stop immediately if this module is instantiated initial begin $stop(); end endmodule verilator-5.042/test_regress/t/t_sys_rand_seed.v0000644000542200017500000000356715101701376022435 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; integer seeda; integer seedb; integer seedc; int valuea; int valueb; int valuec; int igna; int ignb; int ignc; initial begin // $random unlike $urandom updates the value if given seeda = 10; valuea = $random(seeda); seedb = 10; valueb = $random(seedb); if (valuea !== valueb) $stop; seeda = 10; valuea = $random(seeda); seedb = seeda; valueb = $random(seedb); seedc = seedb; valuec = $random(seedc); if (valuea == valueb && valueb == valuec) $stop; // May false fail 1 in 1^64 if (seeda == seedb && seedb == seedc) $stop; // May false fail 1 in 1^64 valuea = $urandom(10); valueb = $urandom(10); valuec = $urandom(10); if (valuea !== valueb && valueb != valuec) $stop; valuea = $urandom(10); valueb = $urandom(11); valuec = $urandom(12); if (valuea == valueb && valueb == valuec) $stop; // May false fail 1 in 1^64 $urandom(10); valuea = $urandom; $urandom(10); valueb = $urandom; $urandom(10); valuec = $urandom; if (valuea != valueb && valueb != valuec) $stop; // May false fail 1 in 1^64 igna = $urandom(10); valuea = $urandom; ignb = $urandom(10); valueb = $urandom; ignc = $urandom(10); valuec = $urandom; if (valuea != valueb && valueb != valuec) $stop; // May false fail 1 in 1^64 valuea = $urandom(10); valueb = $urandom(); valuec = $urandom(); if (valuea == valueb && valueb == valuec) $stop; // May false fail 1 in 1^64 $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_opt_const_big_or_tree.v0000644000542200017500000003213115101701376024150 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (input x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x16, x17, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, x28, x29, x30, x31, x32, x33, x34, x35, x36, x37, x38, x39, x40, x41, x42, x43, x44, x45, x46, x47, x48, x49, x50, x51, x52, x53, x54, x55, x56, x57, x58, x59, x60, x61, x62, x63, x64, x65, x66, x67, x68, x69, x70, x71, x72, x73, x74, x75, x76, x77, x78, x79, x80, x81, x82, x83, x84, x85, x86, x87, x88, x89, x90, x91, x92, x93, x94, x95, x96, x97, x98, x99, x100, x101, x102, x103, x104, x105, x106, x107, x108, x109, x110, x111, x112, x113, x114, x115, x116, x117, x118, x119, x120, x121, x122, x123, x124, x125, x126, x127, x128, x129, x130, x131, x132, x133, x134, x135, x136, x137, x138, x139, x140, x141, x142, x143, x144, x145, x146, x147, x148, x149, x150, x151, x152, x153, x154, x155, x156, x157, x158, x159, x160, x161, x162, x163, x164, x165, x166, x167, x168, x169, x170, x171, x172, x173, x174, x175, x176, x177, x178, x179, x180, x181, x182, x183, x184, x185, x186, x187, x188, x189, x190, x191, x192, x193, x194, x195, x196, x197, x198, x199, x200, x201, x202, x203, x204, x205, x206, x207, x208, x209, x210, x211, x212, x213, x214, x215, x216, x217, x218, x219, x220, x221, x222, x223, x224, x225, x226, x227, x228, x229, x230, x231, x232, x233, x234, x235, x236, x237, x238, x239, x240, x241, x242, x243, x244, x245, x246, x247, x248, x249, x250, x251, x252, x253, x254, x255, x256, x257, x258, x259, x260, x261, x262, x263, x264, x265, x266, x267, x268, x269, x270, x271, x272, x273, x274, x275, x276, x277, x278, x279, x280, x281, x282, x283, x284, x285, x286, x287, x288, x289, x290, x291, x292, x293, x294, x295, x296, x297, x298, x299, x300, x301, x302, x303, x304, x305, x306, x307, x308, x309, x310, x311, x312, x313, x314, x315, x316, x317, x318, x319, x320, x321, x322, x323, x324, x325, x326, x327, x328, x329, x330, x331, x332, x333, x334, x335, x336, x337, x338, x339, x340, x341, x342, x343, x344, x345, x346, x347, x348, x349, x350, x351, x352, x353, x354, x355, x356, x357, x358, x359, x360, x361, x362, x363, x364, x365, x366, x367, x368, x369, x370, x371, x372, x373, x374, x375, x376, x377, x378, x379, x380, x381, x382, x383, x384, x385, x386, x387, x388, x389, x390, x391, x392, x393, x394, x395, x396, x397, x398, x399, x400, x401, x402, x403, x404, x405, x406, x407, x408, x409, x410, x411, x412, x413, x414, x415, x416, x417, x418, x419, x420, x421, x422, x423, x424, x425, x426, x427, x428, x429, x430, x431, x432, x433, x434, x435, x436, x437, x438, x439, x440, x441, x442, x443, x444, x445, x446, x447, x448, x449, x450, x451, x452, x453, x454, x455, x456, x457, x458, x459, x460, x461, x462, x463, x464, x465, x466, x467, x468, x469, x470, x471, x472, x473, x474, x475, x476, x477, x478, x479, x480, x481, x482, x483, x484, x485, x486, x487, x488, x489, x490, x491, x492, x493, x494, x495, x496, x497, x498, x499, x500, x501, x502, x503, x504, x505, x506, x507, x508, x509, x510, x511, x512, x513, x514, x515, x516, x517, x518, x519, x520, x521, x522, x523, x524, x525, x526, x527, x528, x529, x530, x531, x532, x533, x534, x535, x536, x537, x538, x539, x540, x541, x542, x543, x544, x545, x546, x547, x548, x549, x550, x551, x552, x553, x554, x555, x556, x557, x558, x559, x560, x561, x562, x563, x564, x565, x566, x567, x568, x569, x570, x571, x572, x573, x574, x575, x576, x577, x578, x579, x580, x581, x582, x583, x584, x585, x586, x587, x588, x589, x590, x591, x592, x593, x594, x595, x596, x597, x598, x599, x600, x601, x602, x603, x604, x605, x606, x607, x608, x609, x610, x611, x612, x613, x614, x615, x616, x617, x618, x619, x620, x621, x622, x623, x624, x625, x626, x627, x628, x629, x630, x631, x632, x633, x634, x635, x636, x637, x638, x639, x640, x641, x642, x643, x644, x645, x646, x647, x648, x649, x650, x651, x652, x653, x654, x655, x656, x657, x658, x659, x660, x661, x662, x663, x664, x665, x666, x667, x668, x669, x670, x671, x672, x673, x674, x675, x676, x677, x678, x679, x680, x681, x682, x683, x684, x685, x686, x687, x688, x689, x690, x691, x692, x693, x694, x695, x696, x697, x698, x699, x700, x701, x702, x703, x704, x705, x706, x707, x708, x709, x710, x711, x712, x713, x714, x715, x716, x717, x718, x719, x720, x721, x722, x723, x724, x725, x726, x727, x728, x729, x730, x731, x732, x733, x734, x735, x736, x737, x738, x739, x740, x741, x742, x743, x744, x745, x746, x747, x748, x749, x750, x751, x752, x753, x754, x755, x756, x757, x758, x759, x760, x761, x762, x763, x764, x765, x766, x767, x768, x769, x770, x771, x772, x773, x774, x775, x776, x777, x778, x779, x780, x781, x782, x783, x784, x785, x786, x787, x788, x789, x790, x791, x792, x793, x794, x795, x796, x797, x798, x799, x800, x801, x802, x803, x804, x805, x806, x807, x808, x809, x810, x811, x812, x813, x814, x815, x816, x817, x818, x819, x820, x821, x822, x823, x824, x825, x826, x827, x828, x829, x830, x831, x832, x833, x834, x835, x836, x837, x838, x839, x840, x841, x842, x843, x844, x845, x846, x847, x848, x849, x850, x851, x852, x853, x854, x855, x856, x857, x858, x859, x860, x861, x862, x863, x864, x865, x866, x867, x868, x869, x870, x871, x872, x873, x874, x875, x876, x877, x878, x879, x880, x881, x882, x883, x884, x885, x886, x887, x888, x889, x890, x891, x892, x893, x894, x895, x896, x897, x898, x899, x900, x901, x902, x903, x904, x905, x906, x907, x908, x909, x910, x911, x912, x913, x914, x915, x916, x917, x918, x919, x920, x921, x922, x923, x924, x925, x926, x927, x928, x929, x930, x931, x932, x933, x934, x935, x936, x937, x938, x939, x940, x941, x942, x943, x944, x945, x946, x947, x948, x949, x950, x951, x952, x953, x954, x955, x956, x957, x958, x959, x960, x961, x962, x963, x964, x965, x966, x967, x968, x969, x970, x971, x972, x973, x974, x975, x976, x977, x978, x979, x980, x981, x982, x983, x984, x985, x986, x987, x988, x989, x990, x991, x992, x993, x994, x995, x996, x997, x998, x999, output [1:0] out ); assign out = {(x0 | x1 | x2 | x3 | x4 | x5 | x6 | x7 | x8 | x9 | x10 | x11 | x12 | x13 | x14 | x15 | x16 | x17 | x18 | x19 | x20 | x21 | x22 | x23 | x24 | x25 | x26 | x27 | x28 | x29 | x30 | x31 | x32 | x33 | x34 | x35 | x36 | x37 | x38 | x39 | x40 | x41 | x42 | x43 | x44 | x45 | x46 | x47 | x48 | x49 | x50 | x51 | x52 | x53 | x54 | x55 | x56 | x57 | x58 | x59 | x60 | x61 | x62 | x63 | x64 | x65 | x66 | x67 | x68 | x69 | x70 | x71 | x72 | x73 | x74 | x75 | x76 | x77 | x78 | x79 | x80 | x81 | x82 | x83 | x84 | x85 | x86 | x87 | x88 | x89 | x90 | x91 | x92 | x93 | x94 | x95 | x96 | x97 | x98 | x99 | x100 | x101 | x102 | x103 | x104 | x105 | x106 | x107 | x108 | x109 | x110 | x111 | x112 | x113 | x114 | x115 | x116 | x117 | x118 | x119 | x120 | x121 | x122 | x123 | x124 | x125 | x126 | x127 | x128 | x129 | x130 | x131 | x132 | x133 | x134 | x135 | x136 | x137 | x138 | x139 | x140 | x141 | x142 | x143 | x144 | x145 | x146 | x147 | x148 | x149 | x150 | x151 | x152 | x153 | x154 | x155 | x156 | x157 | x158 | x159 | x160 | x161 | x162 | x163 | x164 | x165 | x166 | x167 | x168 | x169 | x170 | x171 | x172 | x173 | x174 | x175 | x176 | x177 | x178 | x179 | x180 | x181 | x182 | x183 | x184 | x185 | x186 | x187 | x188 | x189 | x190 | x191 | x192 | x193 | x194 | x195 | x196 | x197 | x198 | x199 | x200 | x201 | x202 | x203 | x204 | x205 | x206 | x207 | x208 | x209 | x210 | x211 | x212 | x213 | x214 | x215 | x216 | x217 | x218 | x219 | x220 | x221 | x222 | x223 | x224 | x225 | x226 | x227 | x228 | x229 | x230 | x231 | x232 | x233 | x234 | x235 | x236 | x237 | x238 | x239 | x240 | x241 | x242 | x243 | x244 | x245 | x246 | x247 | x248 | x249 | x250 | x251 | x252 | x253 | x254 | x255 | x256 | x257 | x258 | x259 | x260 | x261 | x262 | x263 | x264 | x265 | x266 | x267 | x268 | x269 | x270 | x271 | x272 | x273 | x274 | x275 | x276 | x277 | x278 | x279 | x280 | x281 | x282 | x283 | x284 | x285 | x286 | x287 | x288 | x289 | x290 | x291 | x292 | x293 | x294 | x295 | x296 | x297 | x298 | x299 | x300 | x301 | x302 | x303 | x304 | x305 | x306 | x307 | x308 | x309 | x310 | x311 | x312 | x313 | x314 | x315 | x316 | x317 | x318 | x319 | x320 | x321 | x322 | x323 | x324 | x325 | x326 | x327 | x328 | x329 | x330 | x331 | x332 | x333 | x334 | x335 | x336 | x337 | x338 | x339 | x340 | x341 | x342 | x343 | x344 | x345 | x346 | x347 | x348 | x349 | x350 | x351 | x352 | x353 | x354 | x355 | x356 | x357 | x358 | x359 | x360 | x361 | x362 | x363 | x364 | x365 | x366 | x367 | x368 | x369 | x370 | x371 | x372 | x373 | x374 | x375 | x376 | x377 | x378 | x379 | x380 | x381 | x382 | x383 | x384 | x385 | x386 | x387 | x388 | x389 | x390 | x391 | x392 | x393 | x394 | x395 | x396 | x397 | x398 | x399 | x400 | x401 | x402 | x403 | x404 | x405 | x406 | x407 | x408 | x409 | x410 | x411 | x412 | x413 | x414 | x415 | x416 | x417 | x418 | x419 | x420 | x421 | x422 | x423 | x424 | x425 | x426 | x427 | x428 | x429 | x430 | x431 | x432 | x433 | x434 | x435 | x436 | x437 | x438 | x439 | x440 | x441 | x442 | x443 | x444 | x445 | x446 | x447 | x448 | x449 | x450 | x451 | x452 | x453 | x454 | x455 | x456 | x457 | x458 | x459 | x460 | x461 | x462 | x463 | x464 | x465 | x466 | x467 | x468 | x469 | x470 | x471 | x472 | x473 | x474 | x475 | x476 | x477 | x478 | x479 | x480 | x481 | x482 | x483 | x484 | x485 | x486 | x487 | x488 | x489 | x490 | x491 | x492 | x493 | x494 | x495 | x496 | x497 | x498 | x499 | x500 | x501 | x502 | x503 | x504 | x505 | x506 | x507 | x508 | x509 | x510 | x511 | x512 | x513 | x514 | x515 | x516 | x517 | x518 | x519 | x520 | x521 | x522 | x523 | x524 | x525 | x526 | x527 | x528 | x529 | x530 | x531 | x532 | x533 | x534 | x535 | x536 | x537 | x538 | x539 | x540 | x541 | x542 | x543 | x544 | x545 | x546 | x547 | x548 | x549 | x550 | x551 | x552 | x553 | x554 | x555 | x556 | x557 | x558 | x559 | x560 | x561 | x562 | x563 | x564 | x565 | x566 | x567 | x568 | x569 | x570 | x571 | x572 | x573 | x574 | x575 | x576 | x577 | x578 | x579 | x580 | x581 | x582 | x583 | x584 | x585 | x586 | x587 | x588 | x589 | x590 | x591 | x592 | x593 | x594 | x595 | x596 | x597 | x598 | x599 | x600 | x601 | x602 | x603 | x604 | x605 | x606 | x607 | x608 | x609 | x610 | x611 | x612 | x613 | x614 | x615 | x616 | x617 | x618 | x619 | x620 | x621 | x622 | x623 | x624 | x625 | x626 | x627 | x628 | x629 | x630 | x631 | x632 | x633 | x634 | x635 | x636 | x637 | x638 | x639 | x640 | x641 | x642 | x643 | x644 | x645 | x646 | x647 | x648 | x649 | x650 | x651 | x652 | x653 | x654 | x655 | x656 | x657 | x658 | x659 | x660 | x661 | x662 | x663 | x664 | x665 | x666 | x667 | x668 | x669 | x670 | x671 | x672 | x673 | x674 | x675 | x676 | x677 | x678 | x679 | x680 | x681 | x682 | x683 | x684 | x685 | x686 | x687 | x688 | x689 | x690 | x691 | x692 | x693 | x694 | x695 | x696 | x697 | x698 | x699 | x700 | x701 | x702 | x703 | x704 | x705 | x706 | x707 | x708 | x709 | x710 | x711 | x712 | x713 | x714 | x715 | x716 | x717 | x718 | x719 | x720 | x721 | x722 | x723 | x724 | x725 | x726 | x727 | x728 | x729 | x730 | x731 | x732 | x733 | x734 | x735 | x736 | x737 | x738 | x739 | x740 | x741 | x742 | x743 | x744 | x745 | x746 | x747 | x748 | x749 | x750 | x751 | x752 | x753 | x754 | x755 | x756 | x757 | x758 | x759 | x760 | x761 | x762 | x763 | x764 | x765 | x766 | x767 | x768 | x769 | x770 | x771 | x772 | x773 | x774 | x775 | x776 | x777 | x778 | x779 | x780 | x781 | x782 | x783 | x784 | x785 | x786 | x787 | x788 | x789 | x790 | x791 | x792 | x793 | x794 | x795 | x796 | x797 | x798 | x799 | x800 | x801 | x802 | x803 | x804 | x805 | x806 | x807 | x808 | x809 | x810 | x811 | x812 | x813 | x814 | x815 | x816 | x817 | x818 | x819 | x820 | x821 | x822 | x823 | x824 | x825 | x826 | x827 | x828 | x829 | x830 | x831 | x832 | x833 | x834 | x835 | x836 | x837 | x838 | x839 | x840 | x841 | x842 | x843 | x844 | x845 | x846 | x847 | x848 | x849 | x850 | x851 | x852 | x853 | x854 | x855 | x856 | x857 | x858 | x859 | x860 | x861 | x862 | x863 | x864 | x865 | x866 | x867 | x868 | x869 | x870 | x871 | x872 | x873 | x874 | x875 | x876 | x877 | x878 | x879 | x880 | x881 | x882 | x883 | x884 | x885 | x886 | x887 | x888 | x889 | x890 | x891 | x892 | x893 | x894 | x895 | x896 | x897 | x898 | x899 | x900 | x901 | x902 | x903 | x904 | x905 | x906 | x907 | x908 | x909 | x910 | x911 | x912 | x913 | x914 | x915 | x916 | x917 | x918 | x919 | x920 | x921 | x922 | x923 | x924 | x925 | x926 | x927 | x928 | x929 | x930 | x931 | x932 | x933 | x934 | x935 | x936 | x937 | x938 | x939 | x940 | x941 | x942 | x943 | x944 | x945 | x946 | x947 | x948 | x949 | x950 | x951 | x952 | x953 | x954 | x955 | x956 | x957 | x958 | x959 | x960 | x961 | x962 | x963 | x964 | x965 | x966 | x967 | x968 | x969 | x970 | x971 | x972 | x973 | x974 | x975 | x976 | x977 | x978 | x979 | x980 | x981 | x982 | x983 | x984 | x985 | x986 | x987 | x988 | x989 | x990 | x991 | x992 | x993 | x994 | x995 | x996 | x997 | x998 | x999), 1'b0}; endmodule verilator-5.042/test_regress/t/t_func_const_bad.v0000644000542200017500000000311215101701376022544 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; // Speced ignored: system calls. I think this is nasty, so we error instead. // Speced Illegal: inout/output/ref not allowed localparam B1 = f_bad_output(1, 2); function integer f_bad_output(input [31:0] a, output [31:0] o); f_bad_output = 0; endfunction // Speced Illegal: void // Speced Illegal: dotted localparam EIGHT = 8; localparam B2 = f_bad_dotted(2); function integer f_bad_dotted(input [31:0] a); f_bad_dotted = t.EIGHT; endfunction // Speced Illegal: ref to non-local var integer modvar; localparam B3 = f_bad_nonparam(3); function integer f_bad_nonparam(input [31:0] a); f_bad_nonparam = modvar; endfunction // Speced Illegal: needs constant function itself // Our own - infinite loop localparam B4 = f_bad_infinite(3); function integer f_bad_infinite(input [31:0] a); while (1) begin f_bad_infinite = 0; end endfunction // Our own - stop localparam BSTOP = f_bad_stop(3); function integer f_bad_stop(input [31:0] a); $stop; return 0; endfunction // Verify $fatal works with sformatf as argument localparam BFATAL = f_bad_fatal(3); function integer f_bad_fatal(input [31:0] a); for (integer i = 0; i < 3; i++) begin $display("Printing in loop: %s", $sformatf("%0d", i)); end $fatal(2, "%s", $sformatf("Fatal Error")); return 0; endfunction endmodule verilator-5.042/test_regress/t/t_priority_case.v0000644000542200017500000000274615101701376022465 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Rupert Swarbrick. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs value ); input [1:0] value; sub u_sub(.value(value), .out0(), .out1()); endmodule module sub (input logic [1:0] value, output logic [2:0] out0, output logic [2:0] out1); always_comb begin // This case statement shouldn't cause any warnings. Although the cases overlap (2'b11 matches // both 2'b?1 and 2'b1?), the second item matches 2'b10 and the first one doesn't. priority casez (value) 2'b ?1: out0 = 3'd0; 2'b 1?: out0 = 3'd1; default: out0 = 3'd2; endcase // This case statement *should* cause a warning: the second case is completely covered by the // first. priority casez (value) 2'b ?1: out1 = 3'd0; 2'b ?1: out1 = 3'd1; default: out1 = 3'd2; endcase // This case statement should cause a warning too: the second case and third cases are // completely covered by the first. But it should only cause one: like with overlapping cases, // we assume that the author messed up the first case, so there's no real benefit to reporting // each thing it subsumes. priority casez (value) 2'b ?1: out1 = 3'd0; 2'b ?1: out1 = 3'd1; 2'b 11: out1 = 3'd2; default: out1 = 3'd3; endcase end endmodule verilator-5.042/test_regress/t/t_savable_coverage_bad.py0000755000542200017500000000111715101701376024064 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(v_flags2=["--savable --coverage"], save_time=500, fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_inst_slice_part_select.py0000755000542200017500000000073415101701376024513 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_widthexpand_docs_bad.py0000755000542200017500000000204015101701376025145 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["--lint-only"], fails=test.vlt_all, expect_filename=test.golden_filename) test.extract(in_filename=test.top_filename, out_filename=test.root + "/docs/gen/ex_WIDTHEXPAND_1_faulty.rst", lines="8-10") test.extract(in_filename=test.golden_filename, out_filename=test.root + "/docs/gen/ex_WIDTHEXPAND_1_msg.rst", lineno_adjust=-7, regexp=r'Warning-WIDTH') test.extract(in_filename=test.top_filename, out_filename=test.root + "/docs/gen/ex_WIDTHEXPAND_1_fixed.rst", lines="18") test.passes() verilator-5.042/test_regress/t/t_trace_param_saif.out0000644000542200017500000001174015101701376023425 0ustar mahmoudyfreeshell// Generated by verilated_saif (SAIFILE (SAIFVERSION "2.0") (DIRECTION "backward") (PROGRAM_NAME "Verilator") (DIVIDER / ) (TIMESCALE 1ps) (DURATION 0) (INSTANCE top (NET (i_clk (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i_d\[0\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i_d\[1\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i_d\[2\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (o_q\[0\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (o_q\[1\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (o_q\[2\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE my_module_types (NET (MY_PARAM\[0\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) (MY_PARAM\[1\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) (MY_PARAM\[2\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM\[3\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM\[4\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM\[5\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM\[6\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM\[7\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM\[8\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM\[9\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM\[10\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM\[11\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM\[12\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM\[13\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM\[14\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM\[15\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM\[16\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM\[17\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM\[18\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM\[19\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM\[20\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM\[21\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM\[22\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM\[23\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM\[24\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM\[25\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM\[26\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM\[27\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM\[28\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM\[29\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM\[30\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM\[31\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM2\[0\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM2\[1\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM2\[2\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) (MY_PARAM2\[3\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) (MY_PARAM2\[4\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM2\[5\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM2\[6\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM2\[7\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM2\[8\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM2\[9\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM2\[10\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM2\[11\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM2\[12\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM2\[13\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM2\[14\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM2\[15\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM2\[16\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM2\[17\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM2\[18\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM2\[19\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM2\[20\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM2\[21\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM2\[22\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM2\[23\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM2\[24\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM2\[25\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM2\[26\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM2\[27\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM2\[28\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM2\[29\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM2\[30\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (MY_PARAM2\[31\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE t (NET (i_clk (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i_d\[0\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i_d\[1\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i_d\[2\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (o_q\[0\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (o_q\[1\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (o_q\[2\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) verilator-5.042/test_regress/t/t_timescale_parse.cpp0000644000542200017500000000102415101701376023252 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include VM_PREFIX_INCLUDE VM_PREFIX* tb = nullptr; double s_time = 0.0; double sc_time_stamp() { return s_time; } int main() { tb = new VM_PREFIX{"tb"}; s_time = 2 * 1e9; // e.g. 2 seconds in ns units tb->eval(); tb->eval(); tb->eval(); tb->final(); VL_DO_DANGLING(delete tb, tb); } verilator-5.042/test_regress/t/t_vlcov_opt_line.info.out0000644000542200017500000000154215101701376024120 0ustar mahmoudyfreeshellTN:verilator_coverage SF:t/t_cover_line.v DA:15,1 DA:18,1 DA:55,10 DA:83,1 DA:84,1 DA:85,1 DA:87,1 DA:88,1 DA:89,1 DA:91,7 BRDA:91,0,0,1 BRDA:91,0,1,7 DA:92,1 DA:93,1 DA:96,7 DA:97,7 DA:100,0 DA:101,0 DA:102,0 DA:104,0 DA:105,0 DA:106,0 DA:107,0 DA:110,1 DA:111,1 DA:113,1 DA:115,1 DA:127,1 DA:129,1 DA:140,20 DA:145,18 DA:164,20 DA:165,20 DA:174,18 DA:188,1 DA:189,1 DA:194,11 DA:199,11 DA:215,10 DA:216,10 DA:219,11 DA:221,11 DA:229,11 DA:230,1 DA:231,11 DA:232,11 DA:252,10 DA:265,10 DA:266,10 DA:267,1 DA:268,1 DA:269,1 DA:270,1 DA:271,1 DA:272,5 DA:276,10 DA:277,10 DA:287,0 DA:294,0 DA:300,1 DA:303,1 DA:304,20 DA:305,20 DA:314,1 DA:317,21 DA:318,21 DA:319,21 DA:322,10 DA:324,10 DA:330,10 DA:331,10 DA:332,10 DA:346,11 DA:350,11 DA:353,55 BRDA:353,0,0,11 BRDA:353,0,1,55 DA:354,55 DA:356,44 BRDA:356,0,0,11 BRDA:356,0,1,44 DA:357,44 BRF:6 BRH:4 end_of_record verilator-5.042/test_regress/t/t_var_vec_sel.v0000644000542200017500000000125615101701376022074 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // bug601 module t ( input clk, input [3:0] in3, // worky input [0:0] in2 [3:0], // worky input in1 [3:0], // no worky input [1:0] sel, output reg out1, output reg out2, output reg out3 ); always @(posedge clk) begin out3 <= in3[sel] ? in3[sel] : out3; out2 <= in2[sel] ? in2[sel] : out2; out1 <= in1[sel] ? in1[sel] : out1; // breaks $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_tri_select_eqcase.v0000644000542200017500000000127715101701376023265 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; wire [3:0] a = 4'b11z1; logic b = 1'bz === a[1]; logic c = 1'bz === a[2]; logic d = 2'bzz === 2'(a[1]); logic e = 2'b0z === 2'(a[1]); always begin if (b && !c && !d && e) begin $write("*-* All Finished *-*\n"); $finish; end else begin $write("Error: b = %b, c = %b, d = %b, e = %b ", b, c, d, e); $write("expected: b = 1, c = 0, d = 0, e = 1\n"); $stop; end end endmodule verilator-5.042/test_regress/t/t_func_refio_bad.v0000644000542200017500000000065115101701376022527 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(); typedef integer q_t[$]; function void queue_set(ref q_t q); q.push_back(42); endfunction initial begin q_t iq; queue_set(42); // 42 is bad, meant iq end endmodule verilator-5.042/test_regress/t/t_semaphore_bad.v0000644000542200017500000000060315101701376022370 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; semaphore s; initial begin s = new(4); if (s.bad_method() != 0) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_vlt_warn_file_bad.v0000644000542200017500000000046415101701376023245 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `include "t_vlt_warn_file_bad_b.vh" module t; sub sub(); int warn_t = 64'h1; endmodule verilator-5.042/test_regress/t/t_savable_format1_bad.py0000755000542200017500000000165315101701376023647 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap import time test.scenarios('vlt') test.top_filename = "t/t_savable.v" test.compile(v_flags2=["--savable"], save_time=500) test.execute(check_finished=False, all_run_flags=['+save_time=500']) if not os.path.exists(test.obj_dir + "/saved.vltsv"): test.error("Saved.vltsv not created") time.sleep(1) # Avoid make getting confused by very fast build test.compile(v_flags2=["--savable -GMODEL_WIDTH=40"], save_time=500) test.execute(all_run_flags=['+save_restore=1'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_altera_lpm_fifo.py0000755000542200017500000000111115101701376023103 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) test.compile(verilator_flags2=["--top-module", module]) test.passes() verilator-5.042/test_regress/t/t_math_repl3_bad.py0000755000542200017500000000076615101701376022643 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_strength_bufif1.v0000644000542200017500000000062415101701376022674 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; wire a; bufif1 (strong0, strong1) (a, 1'b1, 1'b1); always begin if (a) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_hier_block_type_param_nested.v0000644000542200017500000000201715101701376025464 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t( clk ); input clk; logic [2:0] in1; logic [2:0] out1; assign in1 = 0; Test #(.TYPE_t(logic[2:0])) test(.out (out1), .in (in1)); logic [3:0] in2; logic [3:0] out2; assign in2 = 0; Test #(.TYPE_t(logic[3:0])) test2(.out (out2), .in (in2)); always @ (posedge clk) begin if (out1 !== ~in1) $stop; if (out2 !== ~in2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module Test #(parameter type TYPE_t = logic [5:0]) ( output TYPE_t out, input TYPE_t in ); /*verilator hier_block*/ SubTest #(.TYPE_t(TYPE_t)) subTest(.out(out), .in(in)); endmodule module SubTest #(parameter type TYPE_t = logic [8:0]) ( output TYPE_t out, input TYPE_t in ); /*verilator hier_block*/ assign out = ~ in; endmodule verilator-5.042/test_regress/t/t_timing_unset3.out0000644000542200017500000000062515101701376022735 0ustar mahmoudyfreeshell%Error-NEEDTIMINGOPT: t/t_clocking_notiming.v:11:8: Use --timing or --no-timing to specify how clocking output skew greater than #0 should be handled : ... note: In instance 't' 11 | output #1 out; | ^~~~~~ ... For error description see https://verilator.org/warn/NEEDTIMINGOPT?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_disable_outside4.v0000644000542200017500000000117015101701376023022 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t; initial begin begin : blk int x = 0; fork begin #1; disable begin_blk; end begin : begin_blk x = 1; #2; x = 2; end join_none #3; if (x != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_interface_modport_inl.py0000755000542200017500000000116715101701376024341 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_modport.v" test.compile( # Avoid inlining so we find bugs in the non-inliner connection code verilator_flags2=["-fno-inline"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_arraysel_wide.v0000644000542200017500000000121715101701376022433 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs nnext, // Inputs inibble, onibble ); input [3:0] inibble; input [106:0] onibble; output reg [3:0] nnext [0:7]; // verilator lint_off WIDTH wire [2:0] selline = (onibble >>> 102) & 7; // verilator lint_on WIDTH always_comb begin for (integer i=0; i<8; i=i+1) begin nnext[i] = '0; end nnext[selline] = inibble; end endmodule verilator-5.042/test_regress/t/t_param_unreachable.v0000644000542200017500000000176115101701376023236 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Pierre-Henri Horrein // SPDX-License-Identifier: CC0-1.0 module t (input clk); parameter DEPTH = 1; reg [DEPTH-1:0] shiftreg_gen; reg [DEPTH-1:0] shiftreg; reg my_sr_input = '1; // shiftreg_gen is generated: it should not raise any warning or error always_ff @(posedge clk) begin shiftreg_gen[0] <= my_sr_input; end if (DEPTH > 1) begin always_ff @(posedge clk) begin shiftreg_gen[DEPTH-1:1] <= shiftreg_gen[DEPTH-2:0]; end end // shiftreg is not generated: it can raise a warning always_ff @(posedge clk) begin shiftreg[0] <= my_sr_input; /* verilator lint_off SELRANGE */ if (DEPTH > 1) shiftreg[DEPTH-1:1] <= shiftreg[DEPTH-2:0]; /* verilator lint_on SELRANGE */ end initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_pp_circ_subst_bad2.py0000755000542200017500000000115215101701376023514 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.top_filename = "t/t_pp_circ_subst_bad.v" test.lint(verilator_flags2=["--preproc-token-limit 20000"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_misstatic_bad.py0000755000542200017500000000076615101701376023772 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_flag_j_hier.v0000644000542200017500000000050315101701376022027 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t; logic a; s u_s(.a(a)); endmodule module s(output logic a); /*verilator hier_block*/ endmodule verilator-5.042/test_regress/t/t_clocking_bad4.out0000644000542200017500000000475415101701376022637 0ustar mahmoudyfreeshell%Error: t/t_clocking_bad4.v:23:15: Skew must be constant (IEEE 1800-2023 14.4) : ... note: In instance 't' 23 | input #cyc in; | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_clocking_bad4.v:24:16: Skew cannot be negative : ... note: In instance 't' 24 | input #(-1) out; | ^ %Error: t/t_clocking_bad4.v:31:11: Usage of cycle delays requires default clocking (IEEE 1800-2023 14.11) : ... note: In instance 't' 31 | always ##1; | ^~ %Error: t/t_clocking_bad4.v:32:15: Only non-blocking assignments can write to clockvars (IEEE 1800-2023 14.16) : ... note: In instance 't' 32 | always cb1.out = clk; | ^~~ %Error: t/t_clocking_bad4.v:33:15: Only non-blocking assignments can write to clockvars (IEEE 1800-2023 14.16) : ... note: In instance 't' 33 | assign cb1.out = clk; | ^~~ %Error: t/t_clocking_bad4.v:34:21: Only non-blocking assignments can write to clockvars (IEEE 1800-2023 14.16) : ... note: In instance 't' 34 | always write(cb1.out); | ^~~ %Error: t/t_clocking_bad4.v:35:22: Event controls cannot be used in synchronous drives (IEEE 1800-2023 14.16) : ... note: In instance 't' 35 | always cb1.out <= @(posedge clk) 1; | ^ %Error: t/t_clocking_bad4.v:36:22: Only cycle delays can be used in synchronous drives (IEEE 1800-2023 14.16) : ... note: In instance 't' 36 | always cb1.out <= #1 1; | ^ %Error: t/t_clocking_bad4.v:37:18: Cycle delays not allowed as intra-assignment delays (IEEE 1800-2023 14.11) : ... note: In instance 't' 37 | always out <= ##1 1; | ^~ %Error: t/t_clocking_bad4.v:40:12: Cannot write to input clockvar (IEEE 1800-2023 14.3) : ... note: In instance 't' 40 | cb1.in = 1; | ^~ %Error: t/t_clocking_bad4.v:41:21: Cannot read from output clockvar (IEEE 1800-2023 14.3) : ... note: In instance 't' 41 | $display(cb1.out); | ^~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_mod_interface_array2_noinl.py0000755000542200017500000000104515101701376025244 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_mod_interface_array2.v" test.compile(v_flags2=["-fno-inline"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_wire_behp1364_bad.out0000644000542200017500000000151715101701376023236 0ustar mahmoudyfreeshell%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:24:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'w' : ... note: In instance 't' 24 | w = 0; | ^ ... For error description see https://verilator.org/warn/PROCASSWIRE?v=latest %Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:25:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'o' : ... note: In instance 't' 25 | o = 0; | ^ %Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:26:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'oa' : ... note: In instance 't' 26 | oa = 0; | ^~ %Error: Exiting due to verilator-5.042/test_regress/t/t_unoptflat_simple.v0000644000542200017500000000113115101701376023161 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Simple test of unoptflat // // Simple demonstration of an UNOPTFLAT combinatorial loop, using just 2 bits. // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; wire [1:0] x = { x[0], clk }; always @(posedge clk or negedge clk) begin `ifdef TEST_VERBOSE $write("x = %x\n", x); `endif if (x[1] != 0) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_var_in_assign_bad.v0000644000542200017500000000074315101701376023234 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs value ); input [3:0] value; assign value = 4'h0; sub sub(.valueSub(value[3:0])); endmodule module sub (/*AUTOARG*/ // Inputs valueSub ); input [3:0] valueSub; assign valueSub = 4'h0; endmodule verilator-5.042/test_regress/t/t_func_crc.py0000755000542200017500000000124415101701376021551 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile( # We have deep expressions we want to test verilator_flags2=["--compiler msvc", "--stats"]) test.execute() if test.vlt: test.file_grep(test.stats, r'Optimizations, Const bit op reduction\s+(\d+)', 3888) test.passes() verilator-5.042/test_regress/t/t_tri_pull01.py0000755000542200017500000000073415101701376021765 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_width_arraydecl.v0000644000542200017500000000202215101701376023767 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 localparam UADDR_WIDTH = 4'd10; localparam UROM_WIDTH = 5'd17; localparam UROM_DEPTH = 11'd1024; module t( input clk, input [UADDR_WIDTH-1:0] mAddr, output logic [UROM_WIDTH-1:0] mOutput); // Issue #3959 reg [UROM_WIDTH-1:0] uRam[UROM_DEPTH]; always @(posedge clk) mOutput <= uRam[mAddr]; // Issue #6045 typedef enum logic [1:0] { e_0, e_1, e_2, e_3 } enum_e; typedef struct packed { integer unsigned x; integer unsigned y; } foo_s; typedef struct packed { integer unsigned y; } bar_s; // Warning due to concatenation, but this is actually a member assignment localparam foo_s FOO = '{ y: (1 << e_0) | (1 << e_3) , default: '0 }; // No warning localparam bar_s BAR = '{ y: (1 << e_0) | (1 << e_3) }; endmodule verilator-5.042/test_regress/t/t_flag_i_empty.py0000755000542200017500000000101315101701376022420 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["-Wno-MODDUP -I t_flag_i_empty.v t_flag_i_empty.v"]) test.passes() verilator-5.042/test_regress/t/t_math_signed4.py0000755000542200017500000000073415101701376022340 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_event_method_bad.out0000644000542200017500000000051015101701376023425 0ustar mahmoudyfreeshell%Error: t/t_event_method_bad.v:12:10: Unknown built-in event method 'bad_method' : ... note: In instance 't' 12 | e1.bad_method(); | ^~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_randomize_with_constraint.v0000644000542200017500000000116615101701376025073 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls; rand int m_x; int m_y = -1; endclass function int func1(Cls obj, int y); return obj.randomize() with ( m_x) { m_x > 0; m_x < y; }; endfunction function int func2(Cls obj, int y); return obj.randomize() with ( m_x) { m_x > 0; m_x < m_y; }; endfunction module t; initial begin Cls c; int i; c = new; i = func1(c, 2); i = func2(c, 2); end endmodule verilator-5.042/test_regress/t/t_display_string.out0000644000542200017500000000021415101701376023172 0ustar mahmoudyfreeshellString: ' 1' foo(1): ' 1' s f(1): ' 1' s parm: ' 1' s strg: ' 1' r: 1.234 *-* All Finished *-* verilator-5.042/test_regress/t/t_cast_class.v0000644000542200017500000000142315101701376021717 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Base; int b; endclass class BaseExtended extends Base; int e; endclass module t; Base v_cls_a; BaseExtended v_cls_ab; BaseExtended v_cls_ab1; initial begin v_cls_a = Base'(null); if (v_cls_a != null) $stop; v_cls_ab = new; v_cls_ab.b = 10; v_cls_ab.e = 20; v_cls_ab1 = BaseExtended'(v_cls_ab); if (v_cls_ab1.b != 10) $stop; if (v_cls_ab1.e != 20) $stop; v_cls_a = Base'(v_cls_ab); if (v_cls_a.b != 10) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_array_pattern_packed.py0000755000542200017500000000073415101701376024154 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_pli_bad.py0000755000542200017500000000076615101701376021371 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_virtual_pure.v0000644000542200017500000000102315101701376023502 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 virtual class VBase; pure virtual function int hello(); endclass class VA extends VBase; virtual function int hello; return 2; endfunction endclass module t; initial begin VA va = new; if (va.hello() != 2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_hier_block_libmod.py0000755000542200017500000000115515101701376023417 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(verilator_flags2=[ '--hierarchical', '-y', test.t_dir + '/t_flag_relinc_dir/chip', '+incdir+' + test.t_dir + '/t_flag_relinc_dir/include' ]) test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_ifdepth_bad.out0000644000542200017500000000074515101701376023427 0ustar mahmoudyfreeshell%Warning-IFDEPTH: t/t_lint_ifdepth_bad.v:22:12: Deep 'if' statement; suggest unique/priority to avoid slow logic : ... note: In instance 't' 22 | else if (value==11) begin end | ^~ ... For warning description see https://verilator.org/warn/IFDEPTH?v=latest ... Use "/* verilator lint_off IFDEPTH */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_lint_unused.v0000644000542200017500000000250715101701376022135 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" module t (/*AUTOARG*/ // Outputs out, // Inputs in ); input in; // inputs don't get flagged as undriven output out; // outputs don't get flagged as unused sub sub (); // Check we don't warn about unused UDP signals udp_mux2 udpsub (out, in, in, in); // Check ignoreds mark as used reg sysused; initial $bboxed(sysused); // Check file IO. The fopen is the "driver" all else a usage. integer infile; integer outfile; initial begin outfile = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/open.log"}, "w"); $fwrite(outfile, "1\n"); $fclose(outfile); infile = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/open.log"}, "r"); if ($fgetc(infile) != "1") begin end end wire _unused_ok; endmodule module sub; wire pub /*verilator public*/; // Ignore publics endmodule primitive udp_mux2 (q, a, b, s); output q; input a, b, s; table //a b s : out 1 ? 0 : 1 ; 0 ? 0 : 0 ; ? 1 1 : 1 ; ? 0 1 : 0 ; 0 0 x : 0 ; 1 1 x : 1 ; endtable endprimitive verilator-5.042/test_regress/t/t_math_shortcircuit_assocsel.v0000644000542200017500000000200715101701376025226 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; logic [31:0] dict [int]; // verilator lint_off WIDTHTRUNC function automatic logic f(int a); int dict_size = dict.size; logic next_exists = dict.next(a); // incorrectly inserts element at `a` logic next_nonzero = !next_exists || (dict[a] != 0); if (dict_size != dict.size) begin $display("Assertion failed: dict_size mismatch"); $display("Initial size: %0d, New size: %0d", dict_size, dict.size); $display("Dictionary contents:"); foreach (dict[key]) begin $display(" Key: %0d, Value: %0d", key, dict[key]); end $error; end return next_nonzero; endfunction initial begin logic r = f(0); $display(r); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_mod_uselib.py0000755000542200017500000000070615101701376022113 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.passes() verilator-5.042/test_regress/t/t_func_gen.v0000644000542200017500000000203315101701376021362 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2012 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; genvar g; logic [1:0] mask = 0; generate for (g=0; g<2; g++) begin : picker logic block_passed = 0; // Just for visualizing V3LinkDot debug function [3:0] pick; input [3:0] randnum; pick = randnum+g[3:0]; endfunction always @(posedge clk) begin if (pick(3)!=3+g[3:0]) $stop; else mask[g] = 1'b1; if (mask == 2'b11) begin // All iterations must be finished $write("*-* All Finished *-*\n"); $finish; end end end endgenerate endmodule verilator-5.042/test_regress/t/t_preproc_defarg_bad.py0000755000542200017500000000112515101701376023555 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint( fails=True, verilator_flags2=["-Wno-context"], # The .vh file has the error, not the .v file expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_strength_strong1_strong1_bad.out0000644000542200017500000000043215101701376025737 0ustar mahmoudyfreeshell%Error: t/t_strength_strong1_strong1_bad.v:8:19: syntax error, unexpected strong1 8 | wire (strong1, strong1) a = 1; | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_const_sel_sel_extend.py0000755000542200017500000000070615101701376024174 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.passes() verilator-5.042/test_regress/t/t_math_signed5.v0000644000542200017500000001352315101701376022153 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0) `define checkf(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0) `ifdef VERILATOR `define c(v,vs) ($c(vs)) // Don't constify a value `else `define c(v,vs) (v) `endif module t (/*AUTOARG*/ // Outputs ow4_u ); bit fail; reg signed [3:0] w4_s; reg signed [4:0] w5_s; reg [2:0] w3_u; reg [3:0] w4_u; reg [4:0] w5_u; reg [5:0] w6_u; reg [15:0] w16a_u; reg [15:0] w16_u; reg [31:0] w32_u; real r; reg signed [4:0] bug754_a; integer i; //verilator lint_off WIDTH wire a = (5'b0 == (5'sb11111 >>> 3'd7)); wire b = (5'sb11111 == (5'sb11111 >>> 3'd7)); wire c = (1'b0+(5'sb11111 >>> 3'd7)); wire d = (1'sb0+(5'sb11111 >>> 3'd7)); wire e = (5'b0 == (5'sb11111 / 5'sd3)); wire f = (5'sb0 == (5'sb11111 / 5'sd3)); wire g = (5'b01010 == (5'b11111 / 5'sd3)); initial begin // verilator lint_off STMTDLY #1; `ifdef VCS // I-2014.03 `checkh({a, b, c, d, e, f, g}, 7'b1101111); `else `checkh({a, b, c, d, e, f, g}, 7'b1101011); `endif //====================================================================== if ((-1 >>> 3) != -1) $stop; // Decimals are signed i = 3'sb111 >>> 3; `checkh(i, -1); i = -1 >>> 3; `checkh(i, -1); bug754_a = -1; w4_u = |0 != (bug754_a >>> 3'd7); `checkh(w4_u, 4'b0); // Sanity check: -1>>7 == -1 w5_u = (5'sb11111 >>> 3'd7); `checkh(w5_u, 5'b11111); // bug756 w4_u = (5'b0 == (5'sb11111 >>> 3'd7)); `checkh(w4_u, 4'b0001); w4_u = ((5'b0 == (5'sb11111 >>> 3'd7))); // Exp 0 Vlt 0 `checkh(w4_u, 4'b0001); w4_u = ((5'b01111 == (5'sb11111 / 5'sd2))); // Strength-reduces to >>> `ifdef VCS // I-2014.03 `checkh(w4_u, 4'b0000); // Wrong, gets 5'b0==..., unsigned does not propagate `else `checkh(w4_u, 4'b0001); // NC-Verilog, Modelsim, XSim, ... `endif // Does == sign propagate from lhs to rhs? Yes, but not in VCS w4_u = ((5'b01010 == (5'sb11111 / 5'sd3))); // Exp 0 Vlt 0 // Must be signed result (-1/3) to make this result zero `ifdef VCS // I-2014.03 `checkh(w4_u, 4'b0000); // Wrong, gets 5'b0==..., unsigned does not propagate // Somewhat questionable, as spec says division signed depends on only LHS and RHS, however differs from others `else `checkh(w4_u, 4'b0001); // NC-Verilog, Modelsim, XSim, ... `endif w4_u = (1'b0+(5'sb11111 >>> 3'd7)); // Exp 00000 Vlt 000000 Actually the signedness of result does NOT matter `checkh(w4_u, 4'b0000); w4_u = (5'sb0 == (5'sb11111 / 5'sd3)); // Must be signed result (-1/3) to make this result zero `checkh(w4_u, 4'b0001); // Does == width propagate from lhs to rhs? Yes w4_u = (3'b100==(3'b111 << 2)); `checkh(w4_u, 4'b0001); w4_u = (4'b100==(3'b111 << 2)); `checkh(w4_u, 4'b0000); w4_u = (4'b1100==(3'b111 << 2)); `checkh(w4_u, 4'b0001); // Does >>> sign propagate from input same as for +? Yes w4_u = (1'b0+(5'sb11111 >>> 3'd7)); `checkh(w4_u, 4'b0000); w4_u = (1'sb0+(5'sb11111 >>> 3'd7)); `checkh(w4_u, 4'b1111); // Does << width propagate from input same as for +? Yes w4_u = (3'b0+(3'b111 << 2)); `checkh(w4_u, 4'b1100); // width 4 =='s LHS w4_u = (4'b0+(3'b111 << 2)); `checkh(w4_u, 4'b1100); w4_u = (5'sb11111 == (5'sb11111 >>> 3'd7)); // WHAT? Signedness does propagate across ==????? `checkh(w4_u, 4'b0001); w4_u = ((5'b0 == (5'sb11111 >>> 3'd7))); `checkh(w4_u, 4'b0001); // bug756 w5_s = -1; w3_u = 7; w4_u = |0 != (w5_s >>> w3_u); `checkh(w4_u, 4'b0000); // bug763 w3_u = 2; w4_u = (w3_u >> 2'b11) >> 1; `checkh(w4_u, 4'b0000); // bug766 w16a_u = 16'h1234; w16_u = (w16a_u >> 16) >>> 32'h7ffffff1; `checkh(w16_u, 16'h0000); // bug768 w4_s = 4'sd4; w4_u = $signed(5'd1 > w4_s-w4_s); `checkh(w4_u, 4'b1111); w4_s = `c(4,"4"); // Eval at runtime w4_u = $signed(5'd1 > w4_s-w4_s); `checkh(w4_u, 4'b1111); // bug772 w4_s = w4_u << 1 <<< 0/0; `ifndef VERILATOR // In v4 can't check value as not 4-state `checkh(w4_s, 4'bxxxx); `endif // bug773 w5_u = `c(31, 31); w5_s = w5_u >> ((w5_u ? 1 : 2) << w5_u); `checkh(w5_s, 5'b0); // bug774 w4_u = `c(4, 5); w6_u = `c(6, 35); w4_u = 64'd0 | (w4_u << w6_u); `checkh(w4_u, 0); // bug776 w4_u = `c(4, 1); w4_u = (w4_u >> w4_u) ^~ (w4_u >> w4_u); `checkh(w4_u, 4'b1111); // bug828 // verilator lint_off WIDTH w32_u = 32'(signed'({4'b0001,5'b10000}) << 3); `checkh(w32_u, 32'h0000_0180); w32_u = 32'(signed'({4'b0011,5'b10000}) << 3); `checkh(w32_u, 32'h0000_0380); w32_u = signed'(32'({4'b0001,5'b10000}) << 3); `checkh(w32_u, 32'h0000_0180); w32_u = signed'(32'({4'b0011,5'b10000}) << 3); `checkh(w32_u, 32'h0000_0380); // verilator lint_on WIDTH w32_u = 32'(signed'({4'b0011,5'b10000})) << 3; // Check no width warning `checkh(w32_u, 32'h0000_0380); if (fail) $stop; $write("*-* All Finished *-*\n"); $finish; end // bug775 output [3:0] ow4_u; // Must be consumed assign ow4_u = ((0/0) ? 1 : 2) % 0; endmodule verilator-5.042/test_regress/t/t_trace_cat_reopen__0000.out0000644000542200017500000000526115101701376024241 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $var wire 1 # clk $end $scope module t $end $var wire 1 # clk $end $var wire 32 $ cyc [31:0] $end $upscope $end $upscope $end $enddefinitions $end #0 1# b00000000000000000000000000000000 $ #1 0# #2 1# b00000000000000000000000000000001 $ #3 0# #4 1# b00000000000000000000000000000010 $ #5 0# #6 1# b00000000000000000000000000000011 $ #7 0# #8 1# b00000000000000000000000000000100 $ #9 0# #10 1# b00000000000000000000000000000101 $ #11 0# #12 1# b00000000000000000000000000000110 $ #13 0# #14 1# b00000000000000000000000000000111 $ #15 0# #16 1# b00000000000000000000000000001000 $ #17 0# #18 1# b00000000000000000000000000001001 $ #19 0# #20 1# b00000000000000000000000000001010 $ #21 0# #22 1# b00000000000000000000000000001011 $ #23 0# #24 1# b00000000000000000000000000001100 $ #25 0# #26 1# b00000000000000000000000000001101 $ #27 0# #28 1# b00000000000000000000000000001110 $ #29 0# #30 1# b00000000000000000000000000001111 $ #31 0# #32 1# b00000000000000000000000000010000 $ #33 0# #34 1# b00000000000000000000000000010001 $ #35 0# #36 1# b00000000000000000000000000010010 $ #37 0# #38 1# b00000000000000000000000000010011 $ #39 0# #40 1# b00000000000000000000000000010100 $ #41 0# #42 1# b00000000000000000000000000010101 $ #43 0# #44 1# b00000000000000000000000000010110 $ #45 0# #46 1# b00000000000000000000000000010111 $ #47 0# #48 1# b00000000000000000000000000011000 $ #49 0# #50 1# b00000000000000000000000000011001 $ #51 0# #52 1# b00000000000000000000000000011010 $ #53 0# #54 1# b00000000000000000000000000011011 $ #55 0# #56 1# b00000000000000000000000000011100 $ #57 0# #58 1# b00000000000000000000000000011101 $ #59 0# #60 1# b00000000000000000000000000011110 $ #61 0# #62 1# b00000000000000000000000000011111 $ #63 0# #64 1# b00000000000000000000000000100000 $ #65 0# #66 1# b00000000000000000000000000100001 $ #67 0# #68 1# b00000000000000000000000000100010 $ #69 0# #70 1# b00000000000000000000000000100011 $ #71 0# #72 1# b00000000000000000000000000100100 $ #73 0# #74 1# b00000000000000000000000000100101 $ #75 0# #76 1# b00000000000000000000000000100110 $ #77 0# #78 1# b00000000000000000000000000100111 $ #79 0# #80 1# b00000000000000000000000000101000 $ #81 0# #82 1# b00000000000000000000000000101001 $ #83 0# #84 1# b00000000000000000000000000101010 $ #85 0# #86 1# b00000000000000000000000000101011 $ #87 0# #88 1# b00000000000000000000000000101100 $ #89 0# #90 1# b00000000000000000000000000101101 $ #91 0# #92 1# b00000000000000000000000000101110 $ #93 0# #94 1# b00000000000000000000000000101111 $ #95 0# #96 1# b00000000000000000000000000110000 $ #97 0# #98 1# b00000000000000000000000000110001 $ #99 0# verilator-5.042/test_regress/t/t_interface_generic_submod_param.v0000644000542200017500000000116315101701376025766 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module sub #(parameter P); endmodule package pkg; parameter A = 3; endpackage class B; int x; endclass module Gm (interface a); B b; sub#(.P(pkg::A + $bits(b.x))) s(); initial begin a.v = s.P; end endmodule interface inf; int v; endinterface module t; inf i(); Gm g(.a(i)); initial begin #1; if (i.v != 35) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_display_bad.py0000755000542200017500000000076315101701376022247 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_unused_bad.v0000644000542200017500000000417215101701376022743 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; sub sub (); endmodule module sub; wire pub /*verilator public*/; // Ignore publics wire [5:0] assunu1 = 0; // Assigned but unused wire [3:0] assunub2 = 0; // Assigned but bit 2 unused wire [15:10] udrb2; // [14:13,11] is undriven assign udrb2[15] = 0; assign udrb2[12] = 0; assign udrb2[10] = 0; wire unu3; // Totally unused wire [3:0] mixed; // [3] unused & undr, [2] unused, [1] undr, [0] ok assign mixed[2] = 0; assign mixed[0] = 0; wire [2:0] cmdln_off; // Suppressed by command line assign cmdln_off = 0; localparam THREE = 3; parameter UNUSED_P = 1; localparam UNUSED_LP = 2; genvar unused_gv; genvar ok_gv; // verilator lint_off UNUSEDSIGNAL wire linter_sig1; localparam linter_param1 = 1; genvar linter_genvar1; // verilator lint_on UNUSEDSIGNAL // verilator lint_off UNUSEDPARAM wire linter_sig2; localparam linter_param2 = 2; genvar linter_genvar2; // verilator lint_on UNUSEDPARAM // verilator lint_off UNUSEDGENVAR wire linter_sig3; localparam linter_param3 = 3; genvar linter_genvar3; // verilator lint_on UNUSEDGENVAR // verilator lint_off UNUSED wire linter_sig4; localparam linter_param4 = 4; genvar linter_genvar4; // verilator lint_on UNUSED case (2) 1: begin : named localparam BLOCK_PARAM = 10; end 2: begin : named localparam BLOCK_PARAM = 20; end 3: begin : named localparam BLOCK_PARAM = 30; end endcase initial begin if (0 && assunu1[0] != 0 && udrb2 != 0) begin end if (0 && assunub2[THREE] && assunub2[1:0]!=0) begin end if (0 && mixed[1:0] != 0) begin end if (named.BLOCK_PARAM != 20) $stop; end generate if (0) begin : gen_gv_if0 for (ok_gv = 0; ok_gv < 1; ++ok_gv) begin : gen_gv_if0_for end end endgenerate endmodule verilator-5.042/test_regress/t/t_dpi_sys.v0000644000542200017500000000146315101701376021256 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // Global is the most likely usage scenario import "DPI-C" dpii_sys_task = function void \$dpii_sys (int i); import "DPI-C" dpii_sys_func = function int \$dpii_func (int i); module t (); `ifndef verilator `error "Only Verilator supports PLI-ish DPI calls." `endif initial begin $dpii_sys(1); if ($dpii_func(2) != 3) $stop; $dpii_sys(10); if ($dpii_func(2) != 12) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_package.py0000755000542200017500000000073415101701376021365 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_super_new3.v0000644000542200017500000000111715101701376023057 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Base; int j; function new(int x); j = x; endfunction static function int get_default(); return 8; endfunction endclass class Derived extends Base; function new(); super.new(get_default()); endfunction endclass module t; initial begin Derived d = new; if (d.j != 8) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_math_signed_wire.py0000755000542200017500000000073415101701376023302 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_var_dotted2_inl1.py0000755000542200017500000000104315101701376023124 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_var_dotted2.v" test.compile(v_flags2=['+define+USE_INLINE']) test.execute() test.passes() verilator-5.042/test_regress/t/t_type_array.py0000755000542200017500000000073415101701376022151 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_timing_func_fork_bad.v0000644000542200017500000000155515101701376023737 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t; function int f1(output int o1); fork begin #1 $stop; f1 = 0; o1 = 0; end join_none endfunction function int f2(inout io2); fork begin f2 = #5 0; $stop; io2 = 0; end join_none endfunction event e; function int f3(output int o3); fork begin @e $stop; f3 = 0; o3 = 0; end join_none endfunction function int f4(inout int io4); fork begin f4 = @e 0; $stop; io4 = 0; end join_none endfunction int i; function int f5(output int o5); fork begin wait(i == 0) $stop; f5 = 0; o5 = 0; end join_none endfunction endmodule verilator-5.042/test_regress/t/t_class_new_scoped.v0000644000542200017500000000262015101701376023113 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); class Base; int m_ia = 10; function new(int i); m_ia = i; endfunction endclass class ClsNoArg extends Base; function new(); super.new(5); endfunction : new endclass class ClsArg extends Base; function new(int i, int j); super.new(i + j); endfunction endclass class ClsParam #(int ADD = 100) extends Base; function new(int def = 42); super.new(def + ADD); endfunction endclass module t; initial begin Base b; ClsNoArg c1; ClsArg c2; ClsParam#(100) c3; ClsParam#(200) c4; c1 = new; `checkd(c1.m_ia, 5); b = ClsNoArg::new; `checkd(b.m_ia, 5); c2 = new(20, 1); `checkd(c2.m_ia, 21); b = ClsArg::new(20, 1); `checkd(b.m_ia, 21); c3 = new(33); `checkd(c3.m_ia, 133); b = ClsParam#(100)::new(33); `checkd(b.m_ia, 133); c4 = new(44); `checkd(c4.m_ia, 244); b = ClsParam#(200)::new(44); `checkd(b.m_ia, 244); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_constraint_countones.v0000644000542200017500000000235715101701376024070 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 `define check_rand(cl, field, cond) \ begin \ longint prev_result; \ int ok = 0; \ if (!bit'(cl.randomize())) $stop; \ prev_result = longint'(field); \ if (!(cond)) $stop; \ repeat(9) begin \ longint result; \ if (!bit'(cl.randomize())) $stop; \ result = longint'(field); \ if (!(cond)) $stop; \ if (result != prev_result) ok = 1; \ prev_result = result; \ end \ if (ok != 1) $stop; \ end class Rand1; rand bit [4:0] x; constraint c {$countones(x) == 1;} endclass class Rand2; rand bit [5:0] x; rand bit [2:0] y; constraint c {10'b1 + 10'($countones(x + 6'(y))) == 3;} endclass class Rand3; rand bit [32:0] x; constraint c {$countones(x) == 1;} endclass module t; Rand1 r1 = new; Rand2 r2 = new; Rand3 r3 = new; initial begin `check_rand(r1, r1.x, $countones(r1.x) == 1); `check_rand(r2, r2.x, 10'b1 + 10'($countones(r2.x + 6'(r2.y))) == 3); `check_rand(r3, r3.x, $countones(r3.x) == 1); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_cover_sva_notflat.py0000755000542200017500000000151215101701376023503 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--assert --cc --coverage-user']) test.execute() #if test.nc: ... # See t_assert_cover.py for NC version # Allow old SystemC::Coverage format dump, or new binary dump # Check that the hierarchy doesn't include __PVT__ # Otherwise our coverage reports would look really ugly if test.vlt_all: test.file_grep(test.coverage_filename, r'(top\.t\.sub.*.cyc_eq_5)') test.passes() verilator-5.042/test_regress/t/t_public_seq.v0000644000542200017500000000220415101701376021724 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: public clock signal // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2022 by Todd Strader // SPDX-License-Identifier: CC0-1.0 `ifdef VERILATOR // The '$c1(1)' is there to prevent inlining of the signal by V3Gate `define IMPURE_ONE ($c(1)) `else // Use standard $random (chaces of getting 2 consecutive zeroes is zero). `define IMPURE_ONE (|($random | $random)) `endif module t ( input clk, input dummy_clk // Never toggled from C++ ); int count; logic [7:0] pub_byte /* verilator public_flat_rw */ = 123; logic [7:0] comb_byte; always_comb comb_byte = `IMPURE_ONE ? pub_byte : '0; always_ff @(posedge clk) begin count <= count + 1; if (comb_byte != pub_byte) begin $display("%%Error: comb_byte (%0d) != pub_byte (%0d)", comb_byte, pub_byte); $stop; end if (count == 10) begin $write("*-* All Finished *-*\n"); $finish; end end always_ff @(posedge dummy_clk) begin // verilator lint_off MULTIDRIVEN comb_byte = ~pub_byte; // verilator lint_on MULTIDRIVEN end endmodule verilator-5.042/test_regress/t/t_trace_saif_cmake.out0000644000542200017500000011141115101701376023401 0ustar mahmoudyfreeshell// Generated by verilated_saif (SAIFILE (SAIFVERSION "2.0") (DIRECTION "backward") (PROGRAM_NAME "Verilator") (DIVIDER / ) (TIMESCALE 1ps) (DURATION 1000) (INSTANCE top (NET (clk (T0 505) (T1 495) (TZ 0) (TX 0) (TB 0) (TC 199)) (state\[0\] (T0 410) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46)) (state\[1\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) (state\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44)) (state\[4\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) ) (INSTANCE t (NET (clk (T0 505) (T1 495) (TZ 0) (TX 0) (TB 0) (TC 199)) (cyc\[0\] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 100)) (cyc\[1\] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 50)) (cyc\[2\] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 25)) (cyc\[3\] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 12)) (cyc\[4\] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 6)) (cyc\[5\] (T0 640) (T1 360) (TZ 0) (TX 0) (TB 0) (TC 3)) (cyc\[6\] (T0 640) (T1 360) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (rstn (T0 110) (T1 890) (TZ 0) (TX 0) (TB 0) (TC 1)) (state\[0\] (T0 410) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46)) (state\[1\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) (state\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44)) (state\[4\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) (fst_gparam_real\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[32\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[33\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[34\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[35\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[36\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[37\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[38\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[39\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[40\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[41\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[42\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[43\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[44\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[45\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[46\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[47\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[48\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[49\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[50\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[51\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[52\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[53\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[54\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[55\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[56\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[57\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[58\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[59\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[60\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[61\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[62\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[63\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[32\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[33\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[34\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[35\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[36\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[37\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[38\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[39\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[40\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[41\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[42\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[43\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[44\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[45\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[46\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[47\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[48\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[49\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[50\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[51\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[52\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[53\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[54\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[55\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[56\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[57\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[58\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[59\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[60\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[61\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[62\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[63\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[32\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[33\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[34\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[35\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[36\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[37\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[38\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[39\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[40\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[41\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[42\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[43\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[44\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[45\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[46\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[47\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[48\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[49\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[50\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[51\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[52\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[53\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[54\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[55\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[56\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[57\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[58\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[59\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[60\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[61\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[62\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[63\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_bit (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_logic (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[32\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[33\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[34\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[35\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[36\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[37\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[38\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[39\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[40\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[41\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[42\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[43\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[44\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[45\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[46\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[47\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[48\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[49\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[50\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[51\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[52\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[53\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[54\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[55\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[56\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[57\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[58\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[59\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[60\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[61\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[62\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[63\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_byte\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_byte\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_byte\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_byte\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_byte\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_byte\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_byte\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_byte\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[0\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_parameter\[1\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_parameter\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[3\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_parameter\[4\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_parameter\[5\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_parameter\[6\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_parameter\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[3\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_lparam\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[6\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_lparam\[7\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_lparam\[8\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_lparam\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_supply0 (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_supply1 (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_tri0 (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_tri1 (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_tri (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_wire (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE test (NET (clk (T0 505) (T1 495) (TZ 0) (TX 0) (TB 0) (TC 199)) (rstn (T0 110) (T1 890) (TZ 0) (TX 0) (TB 0) (TC 1)) (state\[0\] (T0 410) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46)) (state\[1\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) (state\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44)) (state\[4\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) (state_w\[0\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_w\[1\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_w\[2\] (T0 430) (T1 570) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_w\[3\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 47)) (state_w\[4\] (T0 420) (T1 580) (TZ 0) (TX 0) (TB 0) (TC 48)) (state_array[0]\[0\] (T0 410) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_array[0]\[1\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) (state_array[0]\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_array[0]\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44)) (state_array[0]\[4\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) (state_array[1]\[0\] (T0 420) (T1 580) (TZ 0) (TX 0) (TB 0) (TC 47)) (state_array[1]\[1\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_array[1]\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_array[1]\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) (state_array[1]\[4\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_array[2]\[0\] (T0 420) (T1 580) (TZ 0) (TX 0) (TB 0) (TC 48)) (state_array[2]\[1\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_array[2]\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_array[2]\[3\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_array[2]\[4\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 47)) ) (INSTANCE unnamedblk1 (NET (i\[0\] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1)) (i\[1\] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1)) (i\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE unnamedblk2 (NET (i\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[1\] (T0 120) (T1 880) (TZ 0) (TX 0) (TB 0) (TC 1)) (i\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) ) ) verilator-5.042/test_regress/t/t_trace_complex_fst_thread.out0000644000542200017500000001030615101701376025172 0ustar mahmoudyfreeshell$date Wed May 1 19:09:18 2019 $end $version fstWriter $end $timescale 1ns $end $scope module top $end $var wire 1 ! clk $end $scope module t $end $var wire 1 ! clk $end $var integer 32 " cyc $end $var logic 2 # v_strp $end $var logic 4 $ v_strp_strp $end $var logic 2 % v_unip_strp $end $var logic 2 & v_arrp $end $var logic 4 ' v_arrp_arrp $end $var logic 4 ( v_arrp_strp $end $var logic 1 ) v_arru(1) $end $var logic 1 * v_arru(2) $end $var logic 1 + v_arru_arru(3)(1) $end $var logic 1 , v_arru_arru(3)(2) $end $var logic 1 - v_arru_arru(4)(1) $end $var logic 1 . v_arru_arru(4)(2) $end $var logic 2 / v_arru_arrp(3) $end $var logic 2 0 v_arru_arrp(4) $end $var logic 2 1 v_arru_strp(3) $end $var logic 2 2 v_arru_strp(4) $end $var real 64 3 v_real $end $var real 64 4 v_arr_real(0) $end $var real 64 5 v_arr_real(1) $end $var logic 64 6 v_str32x2 $end $attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end $attrbegin misc 07 "" 1 $end $var logic 32 7 v_enumed $end $attrbegin misc 07 "" 1 $end $var logic 32 8 v_enumed2 $end $attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end $attrbegin misc 07 "" 2 $end $var logic 3 9 v_enumb $end $scope module unnamedblk1 $end $var integer 32 : b $end $scope module unnamedblk2 $end $var integer 32 ; a $end $upscope $end $upscope $end $scope module p2 $end $var parameter 32 < PARAM $end $upscope $end $scope module p3 $end $var parameter 32 = PARAM $end $upscope $end $upscope $end $scope module $unit $end $var bit 1 > global_bit $end $upscope $end $upscope $end $enddefinitions $end $dumpvars 0! b00000000000000000000000000000000 " b00 # b0000 $ b00 % b00 & b0000 ' b0000 ( 0) 0* 0+ 0, 0- 0. b00 / b00 0 b00 1 b00 2 r0 3 r0 4 r0 5 b0000000000000000000000000000000000000000000000000000000011111111 6 b00000000000000000000000000000000 7 b00000000000000000000000000000000 8 b000 9 b00000000000000000000000000000000 : b00000000000000000000000000000000 ; b00000000000000000000000000000010 < b00000000000000000000000000000011 = 1> #10 b00000000000000000000000000000101 ; b00000000000000000000000000000101 : b111 9 b00000000000000000000000000000010 8 b00000000000000000000000000000001 7 b0000000000000000000000000000000100000000000000000000000011111110 6 r0.3 5 r0.2 4 r0.1 3 b11 2 b11 1 b11 0 b11 / b1111 ( b1111 ' b11 & b11 % b1111 $ b11 # b00000000000000000000000000000001 " 1! #15 0! #20 1! b00000000000000000000000000000010 " b00 # b0000 $ b00 % b00 & b0000 ' b0000 ( b00 / b00 0 b00 1 b00 2 r0.2 3 r0.4 4 r0.6 5 b0000000000000000000000000000001000000000000000000000000011111101 6 b00000000000000000000000000000010 7 b00000000000000000000000000000100 8 b110 9 b00000000000000000000000000000101 : b00000000000000000000000000000101 ; #25 0! #30 1! b00000000000000000000000000000101 ; b00000000000000000000000000000101 : b101 9 b00000000000000000000000000000110 8 b00000000000000000000000000000011 7 b0000000000000000000000000000001100000000000000000000000011111100 6 r0.8999999999999999 5 r0.6000000000000001 4 r0.3 3 b11 2 b11 1 b11 0 b11 / b1111 ( b1111 ' b11 & b11 % b1111 $ b11 # b00000000000000000000000000000011 " #35 0! #40 1! b00000000000000000000000000000100 " b00 # b0000 $ b00 % b00 & b0000 ' b0000 ( b00 / b00 0 b00 1 b00 2 r0.4 3 r0.8 4 r1.2 5 b0000000000000000000000000000010000000000000000000000000011111011 6 b00000000000000000000000000000100 7 b00000000000000000000000000001000 8 b100 9 b00000000000000000000000000000101 : b00000000000000000000000000000101 ; #45 0! #50 1! b00000000000000000000000000000101 ; b00000000000000000000000000000101 : b011 9 b00000000000000000000000000001010 8 b00000000000000000000000000000101 7 b0000000000000000000000000000010100000000000000000000000011111010 6 r1.5 5 r1 4 r0.5 3 b11 2 b11 1 b11 0 b11 / b1111 ( b1111 ' b11 & b11 % b1111 $ b11 # b00000000000000000000000000000101 " #55 0! #60 1! b00000000000000000000000000000110 " b00 # b0000 $ b00 % b00 & b0000 ' b0000 ( b00 / b00 0 b00 1 b00 2 r0.6 3 r1.2 4 r1.8 5 b0000000000000000000000000000011000000000000000000000000011111001 6 b00000000000000000000000000000110 7 b00000000000000000000000000001100 8 b010 9 b00000000000000000000000000000101 : b00000000000000000000000000000101 ; verilator-5.042/test_regress/t/t_inst_dtree_inlbc.py0000755000542200017500000000111615101701376023274 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_inst_dtree.v" test.compile(v_flags2=['+define+INLINE_B +define+INLINE_C'], verilator_flags2=['-trace']) test.execute() test.passes() verilator-5.042/test_regress/t/t_clk_concat5.py0000755000542200017500000000073415101701376022157 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_assert_elab.py0000755000542200017500000000073415101701376022256 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_mem_multiwire.v0000644000542200017500000000410315101701376022455 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; // verilator lint_off ASCRANGE wire [7:0] array [2:0][1:3]; wire [7:0] arrayNoColon [2][3]; // verilator lint_on ASCRANGE integer cyc; initial cyc = 0; integer i0,i1,i2; genvar g0,g1,g2; generate for (g0=0; g0<3; g0=g0+1) begin for (g1=1; g1<4; g1=g1+1) begin inst inst (.q(array[g0[1:0]] [g1[1:0]]), .cyc(cyc), .i0(g0[1:0]), .i1(g1[1:0])); end end endgenerate always @ (posedge clk) begin //$write("cyc==%0d\n",cyc); cyc <= cyc + 1; if (cyc==2) begin if (array[2][1] !== 8'h92) $stop; for (i0=0; i0<3; i0=i0+1) begin for (i1=1; i1<4; i1=i1+1) begin //$write(" array[%0d][%0d] == 8'h%x\n",i0,i1,array[i0[1:0]] [i1[1:0]]); if (array[i0[1:0]] [i1[1:0]] != {i0[1:0], i1[1:0], cyc[3:0]}) $stop; end end end else if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module inst (/*AUTOARG*/ // Outputs q, // Inputs cyc, i0, i1 ); output reg [7:0] q; input [31:0] cyc; input [1:0] i0; input [1:0] i1; inst2 inst2 (/*AUTOINST*/ // Inputs .cyc (cyc[31:0]), .i0 (i0[1:0]), .i1 (i1[1:0])); always @* begin q = {i0, i1, cyc[3:0]}; end endmodule module inst2 (/*AUTOARG*/ // Inputs cyc, i0, i1 ); /*verilator no_inline_module*/ // So we'll get a CELL under a GENFOR, without inlining input [31:0] cyc; input [1:0] i0; input [1:0] i1; initial begin if (cyc==32'h1) $write("[%0t] i0=%d i1=%d\n", $time, i0, i1); end endmodule verilator-5.042/test_regress/t/t_lint_procassinit_bad.out0000644000542200017500000000275115101701376024341 0ustar mahmoudyfreeshell%Warning-PROCASSINIT: t/t_lint_procassinit_bad.v:26:20: Procedural assignment to declaration with initial value: 'flop_out' : ... note: In instance 't' : ... Location of variable initialization 26 | logic flop_out = 1; | ^ t/t_lint_procassinit_bad.v:30:7: ... Location of variable process write : ... Perhaps should initialize instead using a reset in this process 30 | flop_out <= ~in; | ^~~~~~~~ ... For warning description see https://verilator.org/warn/PROCASSINIT?v=latest ... Use "/* verilator lint_off PROCASSINIT */" and lint_on around source to disable this message. %Warning-PROCASSINIT: t/t_lint_procassinit_bad.v:48:20: Procedural assignment to declaration with initial value: 'bad_comb' : ... note: In instance 't' : ... Location of variable initialization 48 | logic bad_comb = 1; | ^ t/t_lint_procassinit_bad.v:51:5: ... Location of variable process write : ... Perhaps should initialize instead using a reset in this process 51 | bad_comb = ok2; | ^~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_vlcov_opt_branch.info.out0000644000542200017500000000303715101701376024427 0ustar mahmoudyfreeshellTN:verilator_coverage SF:t/t_cover_line.v DA:56,10 BRDA:56,0,0,10 BRDA:56,0,1,0 DA:57,10 DA:58,10 DA:60,9 BRDA:60,0,0,1 BRDA:60,0,1,9 DA:61,9 BRDA:61,0,0,1 BRDA:61,0,1,9 DA:62,1 DA:63,1 DA:66,9 BRDA:66,0,0,1 BRDA:66,0,1,9 DA:67,9 BRDA:67,0,0,1 BRDA:67,0,1,9 DA:69,9 DA:70,9 DA:73,9 BRDA:73,0,0,1 BRDA:73,0,1,9 DA:74,9 BRDA:74,0,0,1 BRDA:74,0,1,9 DA:75,1 DA:76,1 DA:79,9 DA:80,9 DA:105,10 DA:106,10 DA:120,7 BRDA:120,0,0,1 BRDA:120,0,1,7 DA:121,1 DA:122,1 DA:141,18 BRDA:141,0,0,2 BRDA:141,0,1,18 DA:142,2 DA:166,20 BRDA:166,0,0,0 BRDA:166,0,1,20 DA:168,0 DA:170,18 BRDA:170,0,0,2 BRDA:170,0,1,18 DA:172,2 DA:190,1 BRDA:190,0,0,1 BRDA:190,0,1,0 DA:191,1 DA:195,11 BRDA:195,0,0,11 BRDA:195,0,1,0 DA:196,11 DA:200,11 BRDA:200,0,0,11 BRDA:200,0,1,0 DA:201,11 DA:222,10 BRDA:222,0,0,1 BRDA:222,0,1,10 DA:223,1 DA:225,10 BRDA:225,0,0,1 BRDA:225,0,1,10 DA:226,1 DA:253,9 BRDA:253,0,0,1 BRDA:253,0,1,9 DA:255,1 DA:256,1 BRDA:256,0,0,0 BRDA:256,0,1,1 DA:288,0 BRDA:288,0,0,0 BRDA:288,0,1,0 DA:289,0 DA:291,0 DA:292,0 DA:327,31 BRDA:327,0,0,0 BRDA:327,0,1,31 DA:328,28 BRDA:328,0,0,3 BRDA:328,0,1,28 DA:329,21 BRDA:329,0,0,21 BRDA:329,0,1,0 DA:331,7 BRDA:331,0,0,3 BRDA:331,0,1,7 DA:332,10 BRDA:332,0,0,0 BRDA:332,0,1,10 DA:334,19 BRDA:334,0,0,12 BRDA:334,0,1,19 BRDA:334,0,2,7 BRDA:334,0,3,5 DA:337,11 BRDA:337,0,0,11 BRDA:337,0,1,0 DA:343,11 BRDA:343,0,0,10 BRDA:343,0,1,11 DA:347,10 BRDA:347,0,0,0 BRDA:347,0,1,1 BRDA:347,0,2,1 BRDA:347,0,3,10 DA:348,10 DA:350,10 BRDA:350,0,0,1 BRDA:350,0,1,10 DA:360,11 BRDA:360,0,0,0 BRDA:360,0,1,11 DA:361,11 BRF:64 BRH:20 end_of_record verilator-5.042/test_regress/t/t_property_var_unsup.v0000644000542200017500000000143715101701376023573 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; int cyc; bit valid; property prop; int prevcyc; (valid, prevcyc = cyc) |=> (cyc == prevcyc + 1); endproperty default clocking @(posedge clk); endclocking assert property(prop); property with_def(int nine = 9); cyc == 9 |-> cyc == nine; endproperty assert property(with_def); always @(posedge clk) begin cyc <= cyc + 1; valid <= cyc == 5; if (cyc == 10) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_case_dupitems.py0000755000542200017500000000073415101701376022617 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_dpi_import_mix_bad.py0000755000542200017500000000076615101701376023630 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_trace_complex_params_fst.py0000755000542200017500000000121415101701376025030 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_complex.v" test.compile(verilator_flags2=['--cc --trace-fst --no-trace-structs --trace-params']) test.execute() test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_string_to_bit.py0000755000542200017500000000073415101701376022640 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_complex_params_saif.py0000755000542200017500000000131115101701376025154 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_complex.v" test.golden_filename = "t/t_trace_complex_params_saif.out" test.compile(verilator_flags2=['--cc --trace-saif --no-trace-structs --trace-params']) test.execute() test.saif_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_builtin_bad.v0000644000542200017500000000066415101701376023247 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls; function int rand_mode(bit onoff); return 1; endfunction function int constraint_mode(bit onoff); return 1; endfunction endclass module t; initial begin Cls c; end endmodule verilator-5.042/test_regress/t/t_assert_future.v0000644000542200017500000000467415101701376022506 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilog_format: off `define stop $stop `define checkd(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); // verilog_format: on module t ( /*AUTOARG*/ // Inputs clk ); input clk; global clocking @(posedge clk); endclocking logic a; //PASSES: int count_not_stable; // Counts changes assert property (@(posedge clk) $stable(a)) else count_not_stable = count_not_stable + 1; int count_not_stable_gclk; // Counts changes assert property (@(posedge clk) $stable_gclk(a)) else count_not_stable_gclk = count_not_stable_gclk + 1; int count_changing_gclk; assert property (@(posedge clk) $changing_gclk(a)) count_changing_gclk = count_changing_gclk + 1; int count_falling_gclk; assert property (@(posedge clk) $falling_gclk(a)) count_falling_gclk = count_falling_gclk + 1; int count_future_gclk; // Counts changes assert property (@(posedge clk) $future_gclk(a) != a) count_future_gclk = count_future_gclk + 1; int count_rising_gclk; assert property (@(posedge clk) $rising_gclk(a)) count_rising_gclk = count_rising_gclk + 1; int count_not_steady_gclk; // Counts changes assert property (@(posedge clk) $steady_gclk(a)) else count_not_steady_gclk = count_not_steady_gclk + 1; int cyc = 0; always @(posedge clk) begin `ifdef TEST_VERBOSE $display("[%0t] cyc=%0d a=%0x gs=%x gsc=%x", $time, cyc, a, count_not_stable, count_not_stable_gclk); `endif cyc <= cyc + 1; if (cyc <= 3) begin a <= 0; count_not_stable = 0; count_not_stable_gclk = 0; end else if (cyc == 4) begin a <= 0; // stable end else if (cyc == 5) begin a <= 1; // rise end else if (cyc == 6) begin a <= 1; // stable end else if (cyc == 7) begin a <= 0; // fall end else if (cyc == 10) begin `checkd(count_not_stable, 2); `checkd(count_not_stable_gclk, 2); `checkd(count_changing_gclk, 2); `checkd(count_falling_gclk, 1); `checkd(count_future_gclk, 2); `checkd(count_rising_gclk, 1); `checkd(count_not_steady_gclk, 2); $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_var_bad_hide.v0000644000542200017500000000076015101701376022172 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; // Check that the lint_on is obeyed. // verilator lint_off VARHIDDEN // verilator lint_on VARHIDDEN integer top; task x; output top; begin end endtask initial begin begin: lower integer top; end end endmodule verilator-5.042/test_regress/t/t_premit_rw.v0000644000542200017500000000130215101701376021604 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef struct packed { logic car_enable; logic [3-1:0] car_rpv; logic [2-1:0] car_sn; } car_s; module t (/*AUTOARG*/ // Outputs action, // Inputs rsp ); input rsp; output action; car_s rsp; car_s action; always @(*) begin action = rsp; if (rsp.car_enable == 1'b1) begin action.car_rpv[ action.car_sn] = 1'b0; // causing problem // OK //action.car_rpv[ rsp.car_sn] = 1'b0; end end endmodule verilator-5.042/test_regress/t/t_func_crc.v0000644000542200017500000002176715101701376021377 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [63:0] d; reg [31:0] c; wire [31:0] q = crc (d, c); reg [31:0] q_r; integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; q_r <= q; c <= q; d <= {d[62:0], ^d[63:48]}; //$write("%d crc(%x,%x)=%x\n", cyc, d, c, q); if (cyc==1) begin // Assign inputs randomly q_r <= 32'h12345678; c <= 32'h12345678; d <= 64'hffffffff_ffffffff; end if (cyc==2) begin d <= 64'hffffffff_ffffffff; end if (cyc==3) begin d <= 64'hffffffff_ffffffff; end if (cyc==4) begin d <= 64'h50183721_81a04b1a; end if (cyc==5) begin end if (cyc==9) begin if (q !== 32'h38295e96) $stop; $write("*-* All Finished *-*\n"); $finish; end end end function [31:0] crc; input [63:0] di; input [31:0] ci; reg [63:0] drev; begin drev = reverse(di); crc = newcrc(drev, ci); end endfunction function [63:0] reverse; input [63:0] di; integer i; begin reverse = 64'b0; for (i=0; i<64; i=i+1) reverse[i] = di[63-i]; end endfunction function [31:0] newcrc; input [63:0] D; input [31:0] C; reg [31:0] N; reg [31:0] DT; begin N = 32'b0; // Note this isn't a real CRC code; it's been munged for privacy N[0] = D[59]^D[53]^D[52]^D[49]^D[44]^D[41]^D[40]^D[39]^D[37]^D[32]^D[29]^D[26]^D[22]^D[21]^D[20]^D[16]^D[15]^D[14]^D[9]^D[7]^D[0] ^C[29]^C[27]^C[24]^C[23]^C[22]^C[21]^C[19]^C[15]^C[13]^C[10]^C[8]^C[3]^C[1]; N[1] = D[61]^D[57]^D[51]^D[47]^D[43]^D[37]^D[35]^D[32]^D[28]^D[24]^D[22]^D[21]^D[20]^D[16]^D[12]^D[11]^D[10]^D[8]^D[7]^D[6]^D[1]^D[0] ^C[30]^C[27]^C[26]^C[20]^C[16]^C[14]^C[13]^C[11]^C[10]^C[8]^C[5]^C[0]; N[2] = D[63]^D[62]^D[61]^D[60]^D[55]^D[54]^D[52]^D[44]^D[43]^D[42]^D[37]^D[34]^D[33]^D[29]^D[28]^D[25]^D[24]^D[23]^D[22]^D[18]^D[16]^D[15]^D[13]^D[12]^D[11] ^C[31]^C[30]^C[27]^C[22]^C[21]^C[18]^C[15]^C[12]^C[11]^C[10]^C[7]; N[3] = D[62]^D[54]^D[50]^D[47]^D[46]^D[38]^D[36]^D[35]^D[34]^D[33]^D[32]^D[30]^D[27]^D[25]^D[21]^D[20]^D[19]^D[17]^D[15]^D[11]^D[8]^D[5]^D[3]^D[1]^D[0] ^C[28]^C[25]^C[24]^C[13]^C[11]^C[9]^C[8]^C[7]^C[3]^C[1]; N[4] = D[57]^D[54]^D[53]^D[52]^D[45]^D[44]^D[43]^D[39]^D[37]^D[34]^D[33]^D[32]^D[31]^D[28]^D[24]^D[23]^D[20]^D[19]^D[15]^D[14]^D[10]^D[6]^D[1]^D[0] ^C[30]^C[24]^C[20]^C[16]^C[14]^C[11]^C[8]^C[7]^C[6]^C[5]^C[2]; N[5] = D[58]^D[57]^D[50]^D[49]^D[48]^D[47]^D[43]^D[39]^D[29]^D[26]^D[23]^D[22]^D[20]^D[18]^D[14]^D[10]^D[9]^D[6]^D[5]^D[4]^D[1] ^C[27]^C[24]^C[20]^C[19]^C[18]^C[14]^C[13]^C[12]^C[11]^C[8]^C[7]^C[1]; N[6] = D[63]^D[62]^D[61]^D[57]^D[51]^D[50]^D[47]^D[38]^D[37]^D[34]^D[30]^D[28]^D[27]^D[25]^D[21]^D[16]^D[15]^D[10]^D[9]^D[6]^D[5]^D[2]^D[1] ^C[31]^C[27]^C[25]^C[16]^C[13]^C[9]^C[8]^C[7]^C[0]; N[7] = ^D[62]^D[61]^D[59]^D[54]^D[52]^D[51]^D[49]^D[46]^D[45]^D[42]^D[41]^D[38]^D[35]^D[29]^D[26]^D[24]^D[15]^D[12]^D[11]^D[9]^D[2]^D[0] ^C[28]^C[27]^C[26]^C[20]^C[19]^C[18]^C[15]^C[12]^C[7]^C[4]; N[8] = D[62]^D[61]^D[60]^D[59]^D[52]^D[50]^D[48]^D[47]^D[46]^D[45]^D[44]^D[42]^D[41]^D[40]^D[30]^D[24]^D[23]^D[22]^D[19]^D[17]^D[11]^D[10]^D[7]^D[6]^D[2] ^C[31]^C[29]^C[27]^C[22]^C[21]^C[19]^C[17]^C[11]^C[9]^C[7]^C[6]; N[9] = D[62]^D[59]^D[58]^D[57]^D[54]^D[51]^D[50]^D[43]^D[41]^D[39]^D[28]^D[25]^D[24]^D[23]^D[22]^D[21]^D[18]^D[16]^D[15]^D[7] ^C[30]^C[29]^C[27]^C[25]^C[23]^C[22]^C[13]^C[12]^C[7]^C[6]^C[5]^C[1]; N[10] = D[61]^D[60]^D[58]^D[56]^D[54]^D[53]^D[51]^D[48]^D[46]^D[43]^D[42]^D[38]^D[37]^D[35]^D[33]^D[31]^D[30]^D[27]^D[26]^D[24]^D[19]^D[10]^D[8]^D[6]^D[1] ^C[31]^C[30]^C[26]^C[25]^C[24]^C[21]^C[16]^C[12]^C[3]^C[2]; N[11] = D[59]^D[57]^D[56]^D[50]^D[49]^D[48]^D[47]^D[46]^D[45]^D[42]^D[41]^D[40]^D[33]^D[32]^D[30]^D[25]^D[21]^D[15]^D[14]^D[13]^D[12]^D[11]^D[5]^D[1] ^C[27]^C[25]^C[24]^C[21]^C[16]^C[12]^C[7]^C[3]^C[2]^C[1]; N[12] = D[62]^D[61]^D[59]^D[58]^D[56]^D[55]^D[53]^D[48]^D[47]^D[44]^D[43]^D[35]^D[31]^D[30]^D[28]^D[24]^D[23]^D[21]^D[14]^D[5]^D[2] ^C[28]^C[26]^C[25]^C[23]^C[22]^C[18]^C[16]^C[15]^C[6]; N[13] = D[63]^D[60]^D[58]^D[57]^D[55]^D[54]^D[53]^D[51]^D[47]^D[45]^D[42]^D[41]^D[38]^D[28]^D[26]^D[25]^D[22]^D[20]^D[18]^D[17]^D[15]^D[13]^D[12]^D[11] ^C[29]^C[28]^C[25]^C[22]^C[19]^C[17]^C[16]^C[15]^C[14]^C[12]^C[10]^C[9]; N[14] = D[58]^D[56]^D[55]^D[52]^D[47]^D[43]^D[41]^D[40]^D[39]^D[38]^D[30]^D[26]^D[25]^D[22]^D[19]^D[17]^D[13]^D[11]^D[10]^D[9]^D[8]^D[3]^D[2]^D[0] ^C[31]^C[28]^C[20]^C[18]^C[17]^C[16]^C[15]^C[13]^C[11]^C[4]^C[2]^C[1]; N[15] = D[63]^D[62]^D[61]^D[59]^D[58]^D[48]^D[47]^D[43]^D[42]^D[35]^D[28]^D[26]^D[25]^D[24]^D[23]^D[22]^D[21]^D[20]^D[19]^D[17]^D[11]^D[7]^D[2] ^C[30]^C[29]^C[27]^C[24]^C[20]^C[17]^C[16]^C[15]^C[11]^C[9]^C[5]; N[16] = D[60]^D[57]^D[49]^D[46]^D[45]^D[43]^D[39]^D[36]^D[32]^D[30]^D[29]^D[28]^D[27]^D[26]^D[23]^D[20]^D[19]^D[17]^D[11]^D[8]^D[5]^D[1] ^C[28]^C[26]^C[23]^C[22]^C[18]^C[16]^C[13]^C[12]^C[10]^C[9]^C[6]; N[17] = D[63]^D[62]^D[61]^D[60]^D[58]^D[54]^D[53]^D[51]^D[48]^D[42]^D[41]^D[37]^D[36]^D[34]^D[28]^D[27]^D[26]^D[24]^D[13]^D[12]^D[9]^D[7]^D[4]^D[0] ^C[31]^C[30]^C[27]^C[23]^C[20]^C[17]^C[14]^C[9]^C[6]^C[4]^C[3]^C[0]; N[18] = D[63]^D[61]^D[59]^D[56]^D[52]^D[50]^D[47]^D[42]^D[37]^D[35]^D[34]^D[31]^D[30]^D[29]^D[22]^D[19]^D[17]^D[16]^D[11]^D[9]^D[8]^D[7] ^C[26]^C[22]^C[20]^C[19]^C[16]^C[11]^C[8]^C[6]^C[5]^C[0]; N[19] = D[62]^D[60]^D[52]^D[49]^D[44]^D[43]^D[42]^D[37]^D[33]^D[32]^D[29]^D[26]^D[19]^D[17]^D[16]^D[12]^D[10]^D[7]^D[6]^D[4]^D[3]^D[2] ^C[30]^C[29]^C[26]^C[25]^C[22]^C[19]^C[14]^C[7]^C[6]^C[5]^C[2]^C[0]; N[20] = D[63]^D[58]^D[54]^D[48]^D[47]^D[40]^D[39]^D[35]^D[34]^D[32]^D[31]^D[28]^D[27]^D[25]^D[18]^D[12]^D[9]^D[7]^D[5]^D[4]^D[3]^D[2]^D[1] ^C[31]^C[29]^C[28]^C[25]^C[19]^C[18]^C[17]^C[15]^C[10]^C[9]^C[6]^C[4]; N[21] = D[61]^D[59]^D[57]^D[56]^D[53]^D[48]^D[44]^D[43]^D[41]^D[35]^D[29]^D[26]^D[25]^D[20]^D[18]^D[17]^D[16]^D[12]^D[9]^D[6]^D[5]^D[3]^D[1] ^C[30]^C[27]^C[24]^C[23]^C[22]^C[21]^C[20]^C[13]^C[9]^C[3]^C[2]; N[22] = D[63]^D[62]^D[60]^D[57]^D[53]^D[51]^D[45]^D[44]^D[42]^D[34]^D[33]^D[27]^D[20]^D[19]^D[18]^D[15]^D[10]^D[9]^D[8]^D[4]^D[3] ^C[24]^C[23]^C[18]^C[17]^C[16]^C[14]^C[12]^C[11]^C[10]^C[9]^C[6]^C[5]; N[23] = D[58]^D[56]^D[54]^D[51]^D[47]^D[43]^D[42]^D[40]^D[37]^D[36]^D[33]^D[25]^D[23]^D[20]^D[18]^D[16]^D[15]^D[12]^D[10]^D[8]^D[7]^D[5]^D[3] ^C[31]^C[27]^C[26]^C[23]^C[21]^C[18]^C[15]^C[11]^C[10]^C[8]^C[7]^C[1]; N[24] = D[60]^D[59]^D[52]^D[50]^D[48]^D[44]^D[39]^D[36]^D[35]^D[31]^D[30]^D[28]^D[27]^D[23]^D[22]^D[21]^D[19]^D[14]^D[13]^D[12]^D[9]^D[4]^D[1]^D[0] ^C[27]^C[25]^C[23]^C[21]^C[17]^C[11]^C[10]^C[4]^C[0]; N[25] = D[61]^D[60]^D[56]^D[54]^D[51]^D[46]^D[43]^D[41]^D[40]^D[38]^D[37]^D[36]^D[29]^D[28]^D[27]^D[22]^D[17]^D[15]^D[10]^D[7]^D[4]^D[2] ^C[29]^C[28]^C[26]^C[23]^C[18]^C[14]^C[13]^C[12]^C[11]^C[9]^C[8]^C[6]; N[26] = D[63]^D[62]^D[58]^D[55]^D[54]^D[52]^D[50]^D[39]^D[37]^D[36]^D[35]^D[33]^D[31]^D[29]^D[27]^D[18]^D[14]^D[10]^D[3]^D[2]^D[0] ^C[31]^C[27]^C[26]^C[25]^C[24]^C[21]^C[13]^C[12]^C[10]^C[1]; N[27] = D[62]^D[60]^D[58]^D[56]^D[55]^D[54]^D[51]^D[44]^D[41]^D[36]^D[34]^D[32]^D[31]^D[29]^D[28]^D[27]^D[23]^D[17]^D[12]^D[11]^D[8]^D[6]^D[4]^D[2] ^C[31]^C[30]^C[28]^C[27]^C[23]^C[19]^C[17]^C[16]^C[14]^C[12]^C[11]^C[10]^C[3]; N[28] = D[57]^D[54]^D[53]^D[51]^D[50]^D[48]^D[40]^D[38]^D[34]^D[33]^D[31]^D[30]^D[29]^D[27]^D[23]^D[21]^D[14]^D[9]^D[7]^D[6]^D[5]^D[4]^D[0] ^C[31]^C[30]^C[26]^C[24]^C[15]^C[14]^C[13]^C[7]^C[6]^C[4]^C[3]^C[0]; N[29] = D[62]^D[60]^D[55]^D[46]^D[45]^D[44]^D[43]^D[41]^D[40]^D[35]^D[33]^D[32]^D[30]^D[28]^D[25]^D[23]^D[22]^D[13]^D[8]^D[7]^D[6]^D[5]^D[4]^D[3]^D[1]^D[0] ^C[31]^C[28]^C[27]^C[18]^C[11]^C[8]^C[6]^C[4]^C[2]^C[1]^C[0]; N[30] = D[63]^D[62]^D[59]^D[58]^D[55]^D[52]^D[47]^D[44]^D[36]^D[35]^D[34]^D[31]^D[29]^D[22]^D[21]^D[20]^D[19]^D[15]^D[14]^D[10]^D[6]^D[3]^D[2]^D[0] ^C[28]^C[25]^C[24]^C[22]^C[20]^C[15]^C[14]^C[12]^C[10]^C[9]^C[4]^C[0]; N[31] = D[61]^D[58]^D[56]^D[55]^D[54]^D[52]^D[51]^D[50]^D[49]^D[42]^D[38]^D[37]^D[36]^D[34]^D[31]^D[30]^D[27]^D[26]^D[23]^D[22]^D[21]^D[19]^D[18]^D[12]^D[0] ^C[28]^C[26]^C[24]^C[21]^C[17]^C[16]^C[14]^C[13]^C[10]^C[8]^C[2]; newcrc = N; end endfunction endmodule verilator-5.042/test_regress/t/t_cpure.py0000755000542200017500000000073415101701376021110 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_string_dyn_num.out0000644000542200017500000000017115101701376023200 0ustar mahmoudyfreeshellistr=' ' istr%0=' ' sstr='' istr=' A ' istr%0='A ' sstr='A' istr='B A ' istr%0='B A ' sstr='BA' *-* All Finished *-* verilator-5.042/test_regress/t/t_trace_complex_saif.out0000644000542200017500000012230715101701376023776 0ustar mahmoudyfreeshell// Generated by verilated_saif (SAIFILE (SAIFVERSION "2.0") (DIRECTION "backward") (PROGRAM_NAME "Verilator") (DIVIDER / ) (TIMESCALE 1ps) (DURATION 60) (INSTANCE top (NET (clk (T0 35) (T1 25) (TZ 0) (TX 0) (TB 0) (TC 11)) ) (INSTANCE $unit (NET (global_bit (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) ) ) (INSTANCE t (NET (clk (T0 35) (T1 25) (TZ 0) (TX 0) (TB 0) (TC 11)) (cyc\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (cyc\[1\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3)) (cyc\[2\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_strp\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_strp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_strp_strp\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_strp_strp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_strp_strp\[2\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_strp_strp\[3\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_unip_strp\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_unip_strp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arrp\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arrp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arrp_arrp\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arrp_arrp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arrp_arrp\[2\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arrp_arrp\[3\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arrp_strp\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arrp_strp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arrp_strp\[2\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arrp_strp\[3\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arru[1] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arru[2] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arru_arru[3][1] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arru_arru[3][2] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arru_arru[4][1] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arru_arru[4][2] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arru_arrp[3]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arru_arrp[3]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arru_arrp[4]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arru_arrp[4]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arru_strp[3]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arru_strp[3]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arru_strp[4]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arru_strp[4]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_real\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[32\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[33\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[34\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[35\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[36\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[37\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[38\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[39\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[40\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[41\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[42\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[43\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[44\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[45\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[46\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[47\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[48\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[49\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[50\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[51\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[52\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[53\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[54\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[55\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[56\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[57\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[58\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[59\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[60\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[61\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[62\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[63\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[32\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[33\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[34\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[35\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[36\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[37\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[38\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[39\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[40\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[41\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[42\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[43\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[44\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[45\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[46\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[47\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[48\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[49\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[50\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[51\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[52\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[53\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[54\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[55\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[56\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[57\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[58\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[59\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[60\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[61\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[62\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[63\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[32\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[33\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[34\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[35\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[36\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[37\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[38\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[39\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[40\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[41\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[42\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[43\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[44\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[45\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[46\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[47\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[48\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[49\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[50\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[51\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[52\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[53\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[54\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[55\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[56\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[57\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[58\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[59\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[60\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[61\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[62\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[63\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[32\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[33\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[34\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[35\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[36\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[37\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[38\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[39\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[40\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[41\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[42\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[43\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[44\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[45\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[46\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[47\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[48\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[49\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[50\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[51\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[52\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[53\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[54\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[55\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[56\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[57\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[58\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[59\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[60\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[61\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[62\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[63\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 7)) (v_str32x2\[1\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4)) (v_str32x2\[2\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_str32x2\[3\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_str32x2\[4\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_str32x2\[5\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_str32x2\[6\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_str32x2\[7\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_str32x2\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[32\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_str32x2\[33\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3)) (v_str32x2\[34\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_str32x2\[35\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[36\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[37\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[38\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[39\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[40\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[41\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[42\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[43\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[44\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[45\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[46\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[47\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[48\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[49\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[50\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[51\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[52\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[53\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[54\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[55\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[56\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[57\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[58\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[59\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[60\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[61\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[62\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_str32x2\[63\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_enumed\[1\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3)) (v_enumed\[2\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_enumed\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_enumed2\[2\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3)) (v_enumed2\[3\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_enumed2\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumb\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_enumb\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 3)) (v_enumb\[2\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_enumb2_str\[0\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 5)) (v_enumb2_str\[1\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3)) (v_enumb2_str\[2\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_enumb2_str\[3\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 5)) (v_enumb2_str\[4\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3)) (v_enumb2_str\[5\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2)) (unpacked_array[-2]\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-2]\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-2]\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-2]\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-2]\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-2]\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-2]\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-2]\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-1]\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-1]\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-1]\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-1]\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-1]\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-1]\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-1]\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-1]\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[0]\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[0]\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[0]\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[0]\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[0]\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[0]\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[0]\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[0]\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed (NET (PARAM\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[2\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (PARAM\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE p2 (NET (PARAM\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[1\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (PARAM\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE p3 (NET (PARAM\[0\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (PARAM\[1\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (PARAM\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE unnamedblk1 (NET (b\[0\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (b\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[2\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (b\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE unnamedblk2 (NET (a\[0\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (a\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[2\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (a\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) ) ) verilator-5.042/test_regress/t/t_timing_zerodly.py0000755000542200017500000000077115101701376023032 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_inst_recurse_bad.py0000755000542200017500000000076615101701376023312 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_assert_disable_count.v0000644000542200017500000000351115101701376023774 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); module t (/*AUTOARG*/ // Inputs clk ); input clk; int cyc; Sub sub (); default disable iff (cyc[0]); int a_false; always @(posedge clk iff !cyc[0]) begin if (cyc < 4 || cyc > 9) ; else a_false = a_false + 1; end int a0_false; a0: assert property (@(posedge clk) disable iff (cyc[0]) (cyc < 4 || cyc > 9)) else a0_false = a0_false + 1; int a1_false; // Note that Verilator supports $inferred_disable in general expression locations // This is a superset of what IEEE specifies a1: assert property (@(posedge clk) disable iff ($inferred_disable) (cyc < 4 || cyc > 9)) else a1_false = a1_false + 1; int a2_false; // Implicitly uses $inferred_disable a2: assert property (@(posedge clk) (cyc < 4 || cyc > 9)) else a2_false = a2_false + 1; int a3_false; // A different disable iff expression a3: assert property (@(posedge clk) disable iff (cyc == 5) (cyc < 4 || cyc > 9)) else a3_false = a3_false + 1; always @(posedge clk) begin cyc <= cyc + 1; if (cyc == 20) begin `checkd(a_false, 3); `checkd(a0_false, a_false); `checkd(a1_false, a_false); `checkd(a2_false, a_false); `checkd(a3_false, 5); $write("*-* All Finished *-*\n"); $finish; end end endmodule module Sub; initial begin if ($inferred_disable !== 0) $stop; end endmodule verilator-5.042/test_regress/t/t_param_array7.v0000644000542200017500000000350215101701376022165 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 typedef struct packed { longint a; longint b; longint c; } s_t; module t; localparam int C0 [4] = '{5, 6, 7, 8}; localparam bit [255:0] C1 [4] = '{9, 10, 11, 12}; localparam string C2 [2] = '{"baz", "quux"}; localparam s_t C3 [2] = '{'{a: 100, b: 200, c: 300}, '{a: 1000, b: 2000, c: 3000}}; a #( .P0(C0), .P1(C1), .P2(C2), .P3(C3) ) i_a (); endmodule module a #( parameter int P0 [4] = '{1, 2, 3, 4}, parameter bit [255:0] P1 [4] = '{1, 2, 3, 4}, parameter string P2 [2] = '{"foo", "bar"}, parameter s_t P3 [2] = '{'{a: 1, b: 2, c: 3}, '{a: 1, b: 2, c: 3}} ); int i; initial begin // Go via $c to ensure parameters are emitted i = $c("0"); if (P0[i] != 5) $stop; i = $c("1"); if (P0[i] != 6) $stop; i = $c("2"); if (P0[i] != 7) $stop; i = $c("3"); if (P0[i] != 8) $stop; i = $c("0"); if (P1[i] != 9) $stop; i = $c("1"); if (P1[i] != 10) $stop; i = $c("2"); if (P1[i] != 11) $stop; i = $c("3"); if (P1[i] != 12) $stop; i = $c("0"); if (P2[i] != "baz") $stop; i = $c("1"); if (P2[i] != "quux") $stop; i = $c("0"); if (P3[i].a != 100) $stop; i = $c("0"); if (P3[i].b != 200) $stop; i = $c("0"); if (P3[i].c != 300) $stop; i = $c("1"); if (P3[i].a != 1000) $stop; i = $c("1"); if (P3[i].b != 2000) $stop; i = $c("1"); if (P3[i].c != 3000) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_mailbox_bad.out0000644000542200017500000000054115101701376022403 0ustar mahmoudyfreeshell%Error: t/t_mailbox_bad.v:12:13: Class method 'bad_method' not found in class 'mailbox__Tz1' : ... note: In instance 't' 12 | if (m.bad_method() != 0) $stop; | ^~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_vpi_const_type.py0000755000542200017500000000120715101701376023033 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(make_top_shell=False, make_main=False, make_pli=True, verilator_flags2=["--exe --vpi --no-l2name", test.pli_filename]) test.execute(use_libvpi=True) test.passes() verilator-5.042/test_regress/t/t_func.v0000644000542200017500000000740015101701376020534 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg [2:0] value; reg [31:0] rglobal; reg [31:0] vec [1:0]; reg [31:0] n; int abcd; initial begin rglobal = 1; value = 2; if (add(value) != 3'd3) $stop; if (rglobal != 2) $stop; if (add(add(3'd1)) != 3'd3) $stop; if (rglobal != 4) $stop; if (munge4(4'b0010) != 4'b1011) $stop; if (toint(2) != 3) $stop; if (rglobal != 5) $stop; setit; incr(rglobal,rglobal,32'h10); if (rglobal != 32'h17) $stop; nop(32'h11); empty; empty(); rglobal = 32'h00000001; flipupperbit(rglobal,4'd4); flipupperbit(rglobal,4'd12); if (rglobal !== 32'h10100001) $stop; if (nil_func(32'h12,32'h12) != 32'h24) $stop; nil_task(32'h012,32'h112,rglobal); if (rglobal !== 32'h124) $stop; vec[0] = 32'h333; vec[1] = 32'habc; incr(vec[1],vec[0],vec[1]); if (vec[0] != 32'h333) $stop; if (vec[1] != 32'hdef) $stop; // verilator lint_off SELRANGE incr(vec[2],vec[0],vec[2]); // Reading/Writing past end of vector! // verilator lint_on SELRANGE n=1; nil(); if (n !== 10) $stop; // Functions called as tasks // verilator lint_off IGNOREDRETURN rglobal = 32'h4; if (inc_and_return(32'h2) != 32'h6) $stop; if (rglobal !== 32'h6) $stop; rglobal = 32'h6; inc_and_return(32'h3); if (rglobal !== 32'h9) $stop; // verilator lint_on IGNOREDRETURN abcd = 0; set_1_to_abcd; if (abcd != 1) $stop; set_2_to_abcd; if (abcd != 2) $stop; $write("*-* All Finished *-*\n"); $finish; end function [2:0] add; input [2:0] fromv; begin add = fromv + 3'd1; begin : named reg [31:0] flocal; flocal = 1; rglobal = rglobal + flocal; end : named // SystemVerilog end labels end endfunction function [3:0] munge4; input [3:0] fromv; // Different fromv than the 'fromv' signal above reg one; begin : named reg [1:0] flocal; // Function calling a function one = 1'b1; munge4 = {one, add(fromv[2:0])}; end endfunction task setit; reg [31:0] temp; begin temp = rglobal + 32'h1; rglobal = temp + 32'h1; end endtask task incr ( // Check a V2K style input/output list output [31:0] z, input [31:0] a, inc ); z = a + inc; endtask task nop; input [31:0] a; begin end endtask task empty; endtask task flipupperbit; inout [31:0] vector; input [3:0] bitnum; reg [4:0] bitnum2; begin bitnum2 = {1'b1, bitnum}; // A little math to test constant propagation vector[bitnum2] = vector[bitnum2] ^ 1'b1; end endtask task nil_task; input [31:0] a; input [31:0] b; output [31:0] q; // verilator no_inline_task q = nil_func(a, b); endtask function void nil; n = 10; endfunction function [31:0] nil_func; input [31:0] fa; input [31:0] fb; // verilator no_inline_task nil_func = fa + fb; endfunction function integer toint; input integer fa; toint = fa + 32'h1; endfunction function [31:0] inc_and_return; input [31:0] inc; rglobal = rglobal + inc; return rglobal; endfunction function void set_1_to_abcd; abcd = 1; endfunction task set_2_to_abcd; abcd = 2; endtask endmodule verilator-5.042/test_regress/t/t_trace_two_port_cc.py0000755000542200017500000000245215101701376023471 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Test tracing with two models instanced import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t_trace_two_a.v" test.pli_filename = "t/t_trace_two_cc.cpp" test.compile(make_main=False, verilator_make_gmake=False, top_filename='t_trace_two_b.v', vm_prefix='Vt_trace_two_b', verilator_flags2=['-trace']) test.run(logfile=test.obj_dir + "/make_first_ALL.log", cmd=[ os.environ["MAKE"], "-C", test.obj_dir, "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp" ]) test.compile(make_main=False, top_filename='t_trace_two_a.v', verilator_flags2=['-exe', '-trace', test.pli_filename], v_flags2=['+define+TEST_DUMPPORTS']) test.execute() if test.vlt_all: test.file_grep(test.trace_filename, r'\$enddefinitions') test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dfg_stats_patterns_scoped.out0000644000542200017500000001510315101701376025375 0ustar mahmoudyfreeshellDFG 'scoped' patterns with depth 1 9 (CONCAT _A:1 _B:a):b 8 (REDXOR _A:a):1 3 (AND _A:a _B:a)*:a 3 (NOT vA:a)*:a 2 (REPLICATE _A:a cA:a)*:b 1 (CONCAT '0:a _A:b):A 1 (CONCAT _A:1 _B:1):a 1 (NOT _A:a):a 1 (REDXOR _A:a)*:1 1 (REPLICATE _A:1 cA:a)*:b 1 (REPLICATE _A:a cA:b)*:b 1 (REPLICATE _A:a cA:b)*:c 1 (SEL@0 _A:a)*:1 1 (SEL@0 _A:a)*:b 1 (SEL@A _A:a):1 DFG 'scoped' patterns with depth 2 6 (CONCAT (REDXOR _A:a):1 (CONCAT _B:1 _C:b):c):d 3 (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a 3 (REDXOR (AND _A:a _B:a)*:a):1 1 (CONCAT '0:a (REPLICATE _A:a cA:a)*:b):A 1 (CONCAT (REDXOR _A:a)*:1 (CONCAT _B:1 _C:b):c):d 1 (CONCAT (REDXOR _A:a):1 (CONCAT _B:1 _C:1):b):c 1 (CONCAT (REDXOR _A:a):1 (REDXOR _B:b)*:1):c 1 (CONCAT (SEL@0 _A:a)*:1 (CONCAT _B:1 _C:b):c):d 1 (NOT (REPLICATE _A:a cA:b)*:b):b 1 (REDXOR (REPLICATE _A:1 cA:a)*:b):1 1 (REDXOR (REPLICATE _A:a cA:a)*:b)*:1 1 (REDXOR (REPLICATE _A:a cA:a)*:b):1 1 (REDXOR (REPLICATE _A:a cA:b)*:b):1 1 (REDXOR (REPLICATE _A:a cA:b)*:c):1 1 (REDXOR (SEL@0 _A:a)*:b):1 1 (REPLICATE (NOT _A:a):a cA:a)*:b 1 (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c 1 (REPLICATE (REPLICATE _A:a cA:b)*:b cA:b)*:c 1 (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b 1 (REPLICATE (SEL@A _A:a):1 cA:b)*:c 1 (SEL@0 (AND _A:a _B:a)*:a)*:1 1 (SEL@0 (REPLICATE _A:a cA:a)*:b)*:c 1 (SEL@A (AND _A:a _B:a)*:a):1 DFG 'scoped' patterns with depth 3 3 (REDXOR (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 2 (CONCAT (REDXOR (AND _A:a _B:a)*:a):1 (CONCAT (REDXOR _C:a):1 (CONCAT _D:1 _E:b):c):d):e 1 (CONCAT '0:a (REPLICATE (REPLICATE _A:b cA:a)*:a cA:a)*:c):A 1 (CONCAT (REDXOR (AND _A:a _B:a)*:a):1 (CONCAT (SEL@0 _C:a)*:1 (CONCAT _D:1 _E:b):c):d):e 1 (CONCAT (REDXOR (REPLICATE _A:1 cA:a)*:b):1 (CONCAT (REDXOR _B:c):1 (CONCAT _C:1 _D:d):e):f):g 1 (CONCAT (REDXOR (REPLICATE _A:a cA:a)*:b)*:1 (CONCAT (REDXOR _B:b):1 (CONCAT _C:1 _D:1):c):d):e 1 (CONCAT (REDXOR (REPLICATE _A:a cA:a)*:b):1 (CONCAT (REDXOR _B:c):1 (REDXOR _C:b)*:1):d):e 1 (CONCAT (REDXOR (REPLICATE _A:a cA:b)*:b):1 (CONCAT (REDXOR _B:c)*:1 (CONCAT _C:1 _D:d):e):f):g 1 (CONCAT (REDXOR (REPLICATE _A:a cA:b)*:c):1 (CONCAT (REDXOR _B:b):1 (CONCAT _C:1 _D:d):e):f):g 1 (CONCAT (REDXOR (SEL@0 _A:a)*:b):1 (REDXOR (REPLICATE _B:c cA:c)*:a)*:1):d 1 (CONCAT (SEL@0 (AND _A:a _B:a)*:a)*:1 (CONCAT (REDXOR _C:b):1 (CONCAT _D:1 _E:c):d):e):b 1 (NOT (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b):b 1 (REDXOR (REPLICATE (NOT _A:a):a cA:a)*:b):1 1 (REDXOR (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c):1 1 (REDXOR (REPLICATE (REPLICATE _A:a cA:b)*:b cA:b)*:c)*:1 1 (REDXOR (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b):1 1 (REDXOR (REPLICATE (SEL@A _A:a):1 cA:b)*:c):1 1 (REDXOR (SEL@0 (REPLICATE _A:a cA:a)*:b)*:c):1 1 (REPLICATE (NOT (REPLICATE _A:a cA:b)*:b):b cA:b)*:c 1 (REPLICATE (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c cB:a)*:a 1 (REPLICATE (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b cA:b)*:d 1 (REPLICATE (REPLICATE (SEL@A _A:a):1 cA:b)*:c cB:b)*:d 1 (REPLICATE (SEL@A (AND _A:a _B:a)*:a):1 cA:b)*:c 1 (SEL@0 (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a)*:1 1 (SEL@0 (REPLICATE (NOT _A:a):a cA:a)*:b)*:c 1 (SEL@A (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 DFG 'scoped' patterns with depth 4 1 (CONCAT '0:a (REPLICATE (REPLICATE (REPLICATE _A:b cA:a)*:c cA:a)*:a cA:a)*:d):A 1 (CONCAT (REDXOR (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 (CONCAT (REDXOR (AND _A:a _B:a)*:a):1 (CONCAT (REDXOR _C:a):1 (CONCAT _D:1 _E:b):c):d):e):f 1 (CONCAT (REDXOR (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 (CONCAT (REDXOR (AND _A:a _B:a)*:a):1 (CONCAT (SEL@0 _C:a)*:1 (CONCAT _D:1 _E:b):c):d):e):f 1 (CONCAT (REDXOR (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 (CONCAT (SEL@0 (AND _A:a _B:a)*:a)*:1 (CONCAT (REDXOR _C:b):1 (CONCAT _D:1 _E:c):d):e):b):f 1 (CONCAT (REDXOR (REPLICATE (NOT _A:a):a cA:a)*:b):1 (CONCAT (REDXOR (SEL@0 _B:b)*:c):1 (REDXOR (REPLICATE _A:a cA:a)*:b)*:1):d):e 1 (CONCAT (REDXOR (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c):1 (CONCAT (REDXOR (REPLICATE _B:c cB:a)*:a):1 (CONCAT (REDXOR _C:d)*:1 (CONCAT _D:1 _E:e):f):g):h):i 1 (CONCAT (REDXOR (REPLICATE (REPLICATE _A:a cA:b)*:b cA:b)*:c)*:1 (CONCAT (REDXOR (REPLICATE _B:b cA:b)*:c):1 (CONCAT (REDXOR _C:d):1 (REDXOR _D:c)*:1):e):f):g 1 (CONCAT (REDXOR (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b):1 (CONCAT (REDXOR (REPLICATE _B:b cA:b)*:d)*:1 (CONCAT (REDXOR _C:d):1 (CONCAT _D:1 _E:1):e):f):g):h 1 (CONCAT (REDXOR (REPLICATE (SEL@A _A:a):1 cA:b)*:c):1 (CONCAT (REDXOR (REPLICATE _B:c cB:b)*:d):1 (CONCAT (REDXOR _C:b):1 (CONCAT _D:1 _E:e):a):f):g):h 1 (CONCAT (REDXOR (SEL@0 (REPLICATE _A:a cA:a)*:b)*:c):1 (REDXOR (REPLICATE (REPLICATE _B:d cA:a)*:a cA:a)*:b)*:1):e 1 (CONCAT (SEL@0 (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a)*:1 (CONCAT (REDXOR (REPLICATE _A:1 cA:b)*:c):1 (CONCAT (REDXOR _B:d):1 (CONCAT _C:1 _D:a):e):f):g):c 1 (NOT (REPLICATE (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c cB:a)*:a):a 1 (REDXOR (REPLICATE (NOT (REPLICATE _A:a cA:b)*:b):b cA:b)*:c):1 1 (REDXOR (REPLICATE (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c cB:a)*:a):1 1 (REDXOR (REPLICATE (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b cA:b)*:d)*:1 1 (REDXOR (REPLICATE (REPLICATE (SEL@A _A:a):1 cA:b)*:c cB:b)*:d):1 1 (REDXOR (REPLICATE (SEL@A (AND _A:a _B:a)*:a):1 cA:b)*:c):1 1 (REDXOR (SEL@0 (REPLICATE (NOT _A:a):a cA:a)*:b)*:c):1 1 (REPLICATE (NOT (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b):b cA:b)*:d 1 (REPLICATE (REPLICATE (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c cB:a)*:a cB:a)*:d 1 (REPLICATE (REPLICATE (REPLICATE (SEL@A _A:a):1 cA:b)*:c cB:b)*:d cB:b)*:b 1 (REPLICATE (REPLICATE (SEL@A (AND _A:a _B:a)*:a):1 cA:b)*:c cB:b)*:d 1 (REPLICATE (SEL@A (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 cA:b)*:c 1 (SEL@0 (REPLICATE (NOT (REPLICATE _A:a cA:b)*:b):b cA:b)*:c)*:d verilator-5.042/test_regress/t/t_dfg_stats_patterns_post_inline.out0000644000542200017500000001512715101701376026451 0ustar mahmoudyfreeshellDFG 'post inline' patterns with depth 1 9 (CONCAT _A:1 _B:a):b 8 (REDXOR _A:a):1 3 (AND _A:a _B:a)*:a 3 (NOT vA:a)*:a 2 (REPLICATE _A:a cA:a)*:b 1 (CONCAT '0:a _A:b):A 1 (CONCAT _A:1 _B:1):a 1 (NOT _A:a):a 1 (REDXOR _A:a)*:1 1 (REPLICATE _A:1 cA:a)*:b 1 (REPLICATE _A:a cA:b)*:b 1 (REPLICATE _A:a cA:b)*:c 1 (SEL@0 _A:a)*:1 1 (SEL@0 _A:a)*:b 1 (SEL@A _A:a):1 DFG 'post inline' patterns with depth 2 6 (CONCAT (REDXOR _A:a):1 (CONCAT _B:1 _C:b):c):d 3 (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a 3 (REDXOR (AND _A:a _B:a)*:a):1 1 (CONCAT '0:a (REPLICATE _A:a cA:a)*:b):A 1 (CONCAT (REDXOR _A:a)*:1 (CONCAT _B:1 _C:b):c):d 1 (CONCAT (REDXOR _A:a):1 (CONCAT _B:1 _C:1):b):c 1 (CONCAT (REDXOR _A:a):1 (REDXOR _B:b)*:1):c 1 (CONCAT (SEL@0 _A:a)*:1 (CONCAT _B:1 _C:b):c):d 1 (NOT (REPLICATE _A:a cA:b)*:b):b 1 (REDXOR (REPLICATE _A:1 cA:a)*:b):1 1 (REDXOR (REPLICATE _A:a cA:a)*:b)*:1 1 (REDXOR (REPLICATE _A:a cA:a)*:b):1 1 (REDXOR (REPLICATE _A:a cA:b)*:b):1 1 (REDXOR (REPLICATE _A:a cA:b)*:c):1 1 (REDXOR (SEL@0 _A:a)*:b):1 1 (REPLICATE (NOT _A:a):a cA:a)*:b 1 (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c 1 (REPLICATE (REPLICATE _A:a cA:b)*:b cA:b)*:c 1 (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b 1 (REPLICATE (SEL@A _A:a):1 cA:b)*:c 1 (SEL@0 (AND _A:a _B:a)*:a)*:1 1 (SEL@0 (REPLICATE _A:a cA:a)*:b)*:c 1 (SEL@A (AND _A:a _B:a)*:a):1 DFG 'post inline' patterns with depth 3 3 (REDXOR (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 2 (CONCAT (REDXOR (AND _A:a _B:a)*:a):1 (CONCAT (REDXOR _C:a):1 (CONCAT _D:1 _E:b):c):d):e 1 (CONCAT '0:a (REPLICATE (REPLICATE _A:b cA:a)*:a cA:a)*:c):A 1 (CONCAT (REDXOR (AND _A:a _B:a)*:a):1 (CONCAT (SEL@0 _C:a)*:1 (CONCAT _D:1 _E:b):c):d):e 1 (CONCAT (REDXOR (REPLICATE _A:1 cA:a)*:b):1 (CONCAT (REDXOR _B:c):1 (CONCAT _C:1 _D:d):e):f):g 1 (CONCAT (REDXOR (REPLICATE _A:a cA:a)*:b)*:1 (CONCAT (REDXOR _B:b):1 (CONCAT _C:1 _D:1):c):d):e 1 (CONCAT (REDXOR (REPLICATE _A:a cA:a)*:b):1 (CONCAT (REDXOR _B:c):1 (REDXOR _C:b)*:1):d):e 1 (CONCAT (REDXOR (REPLICATE _A:a cA:b)*:b):1 (CONCAT (REDXOR _B:c)*:1 (CONCAT _C:1 _D:d):e):f):g 1 (CONCAT (REDXOR (REPLICATE _A:a cA:b)*:c):1 (CONCAT (REDXOR _B:b):1 (CONCAT _C:1 _D:d):e):f):g 1 (CONCAT (REDXOR (SEL@0 _A:a)*:b):1 (REDXOR (REPLICATE _B:c cA:c)*:a)*:1):d 1 (CONCAT (SEL@0 (AND _A:a _B:a)*:a)*:1 (CONCAT (REDXOR _C:b):1 (CONCAT _D:1 _E:c):d):e):b 1 (NOT (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b):b 1 (REDXOR (REPLICATE (NOT _A:a):a cA:a)*:b):1 1 (REDXOR (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c):1 1 (REDXOR (REPLICATE (REPLICATE _A:a cA:b)*:b cA:b)*:c)*:1 1 (REDXOR (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b):1 1 (REDXOR (REPLICATE (SEL@A _A:a):1 cA:b)*:c):1 1 (REDXOR (SEL@0 (REPLICATE _A:a cA:a)*:b)*:c):1 1 (REPLICATE (NOT (REPLICATE _A:a cA:b)*:b):b cA:b)*:c 1 (REPLICATE (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c cB:a)*:a 1 (REPLICATE (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b cA:b)*:d 1 (REPLICATE (REPLICATE (SEL@A _A:a):1 cA:b)*:c cB:b)*:d 1 (REPLICATE (SEL@A (AND _A:a _B:a)*:a):1 cA:b)*:c 1 (SEL@0 (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a)*:1 1 (SEL@0 (REPLICATE (NOT _A:a):a cA:a)*:b)*:c 1 (SEL@A (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 DFG 'post inline' patterns with depth 4 1 (CONCAT '0:a (REPLICATE (REPLICATE (REPLICATE _A:b cA:a)*:c cA:a)*:a cA:a)*:d):A 1 (CONCAT (REDXOR (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 (CONCAT (REDXOR (AND _A:a _B:a)*:a):1 (CONCAT (REDXOR _C:a):1 (CONCAT _D:1 _E:b):c):d):e):f 1 (CONCAT (REDXOR (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 (CONCAT (REDXOR (AND _A:a _B:a)*:a):1 (CONCAT (SEL@0 _C:a)*:1 (CONCAT _D:1 _E:b):c):d):e):f 1 (CONCAT (REDXOR (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 (CONCAT (SEL@0 (AND _A:a _B:a)*:a)*:1 (CONCAT (REDXOR _C:b):1 (CONCAT _D:1 _E:c):d):e):b):f 1 (CONCAT (REDXOR (REPLICATE (NOT _A:a):a cA:a)*:b):1 (CONCAT (REDXOR (SEL@0 _B:b)*:c):1 (REDXOR (REPLICATE _A:a cA:a)*:b)*:1):d):e 1 (CONCAT (REDXOR (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c):1 (CONCAT (REDXOR (REPLICATE _B:c cB:a)*:a):1 (CONCAT (REDXOR _C:d)*:1 (CONCAT _D:1 _E:e):f):g):h):i 1 (CONCAT (REDXOR (REPLICATE (REPLICATE _A:a cA:b)*:b cA:b)*:c)*:1 (CONCAT (REDXOR (REPLICATE _B:b cA:b)*:c):1 (CONCAT (REDXOR _C:d):1 (REDXOR _D:c)*:1):e):f):g 1 (CONCAT (REDXOR (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b):1 (CONCAT (REDXOR (REPLICATE _B:b cA:b)*:d)*:1 (CONCAT (REDXOR _C:d):1 (CONCAT _D:1 _E:1):e):f):g):h 1 (CONCAT (REDXOR (REPLICATE (SEL@A _A:a):1 cA:b)*:c):1 (CONCAT (REDXOR (REPLICATE _B:c cB:b)*:d):1 (CONCAT (REDXOR _C:b):1 (CONCAT _D:1 _E:e):a):f):g):h 1 (CONCAT (REDXOR (SEL@0 (REPLICATE _A:a cA:a)*:b)*:c):1 (REDXOR (REPLICATE (REPLICATE _B:d cA:a)*:a cA:a)*:b)*:1):e 1 (CONCAT (SEL@0 (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a)*:1 (CONCAT (REDXOR (REPLICATE _A:1 cA:b)*:c):1 (CONCAT (REDXOR _B:d):1 (CONCAT _C:1 _D:a):e):f):g):c 1 (NOT (REPLICATE (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c cB:a)*:a):a 1 (REDXOR (REPLICATE (NOT (REPLICATE _A:a cA:b)*:b):b cA:b)*:c):1 1 (REDXOR (REPLICATE (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c cB:a)*:a):1 1 (REDXOR (REPLICATE (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b cA:b)*:d)*:1 1 (REDXOR (REPLICATE (REPLICATE (SEL@A _A:a):1 cA:b)*:c cB:b)*:d):1 1 (REDXOR (REPLICATE (SEL@A (AND _A:a _B:a)*:a):1 cA:b)*:c):1 1 (REDXOR (SEL@0 (REPLICATE (NOT _A:a):a cA:a)*:b)*:c):1 1 (REPLICATE (NOT (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b):b cA:b)*:d 1 (REPLICATE (REPLICATE (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c cB:a)*:a cB:a)*:d 1 (REPLICATE (REPLICATE (REPLICATE (SEL@A _A:a):1 cA:b)*:c cB:b)*:d cB:b)*:b 1 (REPLICATE (REPLICATE (SEL@A (AND _A:a _B:a)*:a):1 cA:b)*:c cB:b)*:d 1 (REPLICATE (SEL@A (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 cA:b)*:c 1 (SEL@0 (REPLICATE (NOT (REPLICATE _A:a cA:b)*:b):b cA:b)*:c)*:d verilator-5.042/test_regress/t/t_mod_interface_clocking.v0000644000542200017500000000232315101701376024250 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 interface axi_if; logic clk; wire rlast; wire rvalid; clocking cb @(posedge clk); inout rlast, rvalid; endclocking modport md1(clocking cb, inout clk, rlast, rvalid); modport md2(clocking cb); endinterface module sub ( axi_if.md1 axi1, axi_if.md2 axi2 ); initial begin axi1.clk = 1'b0; #1 axi1.clk = 1'b1; #1 axi1.clk = 1'b0; #1 axi1.clk = 1'b1; end initial begin @(negedge axi1.rvalid); $display("[%0t] rvalid==%b", $time, axi1.rvalid); $display("[%0t] rlast is 1: ", $time, axi1.rlast === 1); if (axi1.rlast === 1) $stop; $write("*-* All Finished *-*\n"); $finish; end initial begin $display("[%0t] rvalid <= 1", $time); axi1.cb.rvalid <= 1'b1; @(posedge axi1.rvalid); $display("[%0t] rvalid <= 0", $time); axi1.cb.rvalid <= 1'b0; @(negedge axi1.clk); $display("[%0t] rlast <= 1", $time); axi2.cb.rlast <= 1'b1; end endmodule module t; axi_if axi_vi (); sub i_sub (.axi1(axi_vi), .axi2(axi_vi)); endmodule verilator-5.042/test_regress/t/t_gen_cond_bitrange_bad.v0000644000542200017500000000501715101701376024040 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test for short-circuiting in generate "if" // that should not work. // // The given generate loops should attempt to access invalid bits of mask and // trigger errors. // is defined by SIZE. However since the loop range is larger, this only works // if short-circuited evaluation of the generate loop is in place. // This file ONLY is placed into the Public Domain, for any use, without // warranty, 2012 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 `define MAX_SIZE 3 module t (/*AUTOARG*/ // Inputs clk ); input clk; // Set the parameters, so that we use a size less than MAX_SIZE test_gen #(.SIZE (2), .MASK (2'b11)) i_test_gen (.clk (clk)); // This is only a compilation test, so we can immediately finish always @(posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule // t module test_gen #( parameter SIZE = `MAX_SIZE, MASK = `MAX_SIZE'b0) (/*AUTOARG*/ // Inputs clk ); input clk; // Generate blocks that all have errors in applying short-circuting to // generate "if" conditionals. // Attempt to access invalid bits of MASK in different ways generate genvar g; for (g = 0; g < `MAX_SIZE; g = g + 1) begin if ((g < (SIZE + 1)) && MASK[g]) begin always @(posedge clk) begin `ifdef TEST_VERBOSE $write ("Logical AND generate if MASK [%1d] = %d\n", g, MASK[g]); `endif end end end endgenerate generate for (g = 0; g < `MAX_SIZE; g = g + 1) begin if ((g < SIZE) && MASK[g + 1]) begin always @(posedge clk) begin `ifdef TEST_VERBOSE $write ("Logical AND generate if MASK [%1d] = %d\n", g, MASK[g]); `endif end end end endgenerate // Attempt to short-circuit bitwise AND generate for (g = 0; g < `MAX_SIZE; g = g + 1) begin if ((g < (SIZE)) & MASK[g]) begin always @(posedge clk) begin `ifdef TEST_VERBOSE $write ("Bitwise AND generate if MASK [%1d] = %d\n", g, MASK[g]); `endif end end end endgenerate // Attempt to short-circuit bitwise OR generate for (g = 0; g < `MAX_SIZE; g = g + 1) begin if (!((g >= SIZE) | ~MASK[g])) begin always @(posedge clk) begin `ifdef TEST_VERBOSE $write ("Bitwise OR generate if MASK [%1d] = %d\n", g, MASK[g]); `endif end end end endgenerate endmodule verilator-5.042/test_regress/t/t_timing_write_expr.v0000644000542200017500000000114015101701376023333 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t; reg [7:0] vec1 [3:0], vec2 [3:0]; always for (int i = 0; i < 4; i++) vec2[i] = vec1[i]; initial begin #1 vec1[0] = 8'h0f; #1 vec1[1] = 8'h04; #1 vec1[2] = 8'h0e; #1 vec1[3] = 8'h0a; #1 for (int i = 0; i < 4; i++) if (vec1[i] != vec2[i]) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_sys_readmem_bad_notfound.py0000755000542200017500000000100015101701376025007 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_mailbox.v0000644000542200017500000000422415101701376021235 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Methods defined by IEEE: // class mailbox #(type T = dynamic_singular_type) ; // function new(int bound = 0); // function int num(); // task put( T message); // function int try_put( T message); // task get( ref T message ); // function int try_get( ref T message ); // task peek( ref T message ); // function int try_peek( ref T message ); // endclass `ifndef MAILBOX_T `define MAILBOX_T mailbox `endif // verilator lint_off DECLFILENAME module t; `MAILBOX_T #(int) m; int msg; int out; initial begin m = new(4); if (m.num() != 0) $stop; if (m.try_get(msg) > 0) $stop; msg = 123; m.put(msg); msg = 0; if (m.num() != 1) $stop; if (m.try_peek(out) <= 0) $stop; if (out != 123) $stop; if (m.num() != 1) $stop; out = 0; if (m.try_peek(out) <= 0) $stop; if (out != 123) $stop; out = 0; if (m.try_get(out) <= 0) $stop; if (out != 123) $stop; if (m.num() != 0) $stop; msg = 124; m.put(msg); out = 0; m.get(out); if (out != 124) $stop; msg = 125; m.put(msg); m.put(msg); if (m.try_put(msg) == 0) $stop; if (m.try_put(msg) == 0) $stop; if (m.num() != 4) $stop; if (m.try_put(msg) != 0) $stop; if (m.num() != 4) $stop; m.get(out); m.get(out); m.get(out); m.get(out); if (m.num() != 0) $stop; fork begin #10; // So later then get() starts below msg = 130; m.put(msg); msg = 131; m.put(msg); end begin if (m.try_get(msg) != 0) $stop; out = 0; m.get(out); // Blocks until put if (out != 130) $stop; out = 0; m.get(out); if (out != 131) $stop; end join $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_pli_bad.out0000644000542200017500000000222615101701376021536 0ustar mahmoudyfreeshell%Error: t/t_pli_bad.v:10:7: Unsupported or unknown PLI call: '$unknown_pli_task' 10 | $unknown_pli_task; | ^~~~~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_pli_bad.v:11:7: Unsupported or unknown PLI call: '$unknown_pli_task' 11 | $unknown_pli_task("arg", i); | ^~~~~~~~~~~~~~~~~ %Error: t/t_pli_bad.v:12:11: Unsupported or unknown PLI call: '$unknown_pli_function' 12 | i = $unknown_pli_function; | ^~~~~~~~~~~~~~~~~~~~~ %Error: t/t_pli_bad.v:13:11: Unsupported or unknown PLI call: '$unknown_pli_function' 13 | i = $unknown_pli_function("arg", i); | ^~~~~~~~~~~~~~~~~~~~~ %Error: t/t_pli_bad.v:15:7: Unsupported or unknown PLI call: '$sformatff' : ... Suggested alternative: '$sformatf' 15 | $sformatff(); | ^~~~~~~~~~ %Error: t/t_pli_bad.v:16:11: Unsupported or unknown PLI call: '$sformatff' : ... Suggested alternative: '$sformatf' 16 | i = $sformatff(); | ^~~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_covergroup_extends.v0000644000542200017500000000233115101701376023524 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off COVERIGN */ module t; class base; enum {red, green, blue} color; covergroup g1 (bit [3:0] a) with function sample(bit b); option.weight = 10; option.per_instance = 1; coverpoint a; coverpoint b; c: coverpoint color; endgroup function new(); g1 = new(0); endfunction endclass class derived extends base; bit d; covergroup extends g1; option.weight = 1; // overrides the weight from base g1 // uses per_instance = 1 from base g1 c: coverpoint color // overrides the c coverpoint in base g1 { ignore_bins ignore = {blue}; } coverpoint d; // adds new coverpoint cross a, d; // crosses new coverpoint with inherited one endgroup :g1 function new(); super.new(); endfunction endclass endmodule verilator-5.042/test_regress/t/t_func_dotted_inl1.py0000755000542200017500000000145615101701376023215 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_func_dotted.v" out_filename = test.obj_dir + "/V" + test.name + ".tree.json" test.compile(v_flags2=["--no-json-edit-nums", '+define+ATTRIBUTES', '+define+USE_INLINE']) if test.vlt_all: test.file_grep_not(out_filename, r'"ma0"') test.file_grep_not(out_filename, r'"mb0"') test.file_grep_not(out_filename, r'"mc0"') test.execute() test.passes() verilator-5.042/test_regress/t/t_flag_structs_packed_bad.py0000755000542200017500000000105615101701376024605 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.top_filename = "t/t_flag_structs_packed.v" test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dpi_open_elem.py0000755000542200017500000000111315101701376022561 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=["t/t_dpi_open_elem_c.cpp"], verilator_flags2=["-Wall -Wno-DECLFILENAME -unroll-count 1"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_flag_ldflags_so.cpp0000644000542200017500000000103715101701376023224 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* extern "C" { void dpii_so_library() {} }; verilator-5.042/test_regress/t/t_sys_readmem.py0000755000542200017500000000073415101701376022302 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_mem_slot.cpp0000644000542200017500000000307315101701376021737 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include VM_PREFIX_INCLUDE #include double sc_time_stamp() { return 0; } unsigned int Array[3]; unsigned int StepSim(Vt_mem_slot* sim, unsigned int slot, unsigned int bit, unsigned int val, unsigned int rslot) { #ifdef TEST_VERBOSE printf("StepSim: slot=%u bit=%u val=%u rslot=%u\n", slot, bit, val, rslot); #endif sim->SlotIdx = slot; sim->BitToChange = bit; sim->BitVal = val; sim->SlotToReturn = rslot; sim->Clk = 0; sim->eval(); sim->Clk = 1; sim->eval(); if (sim->OutputVal != Array[rslot]) { printf("%%Error: got %x - expected %x\n", sim->OutputVal, Array[rslot]); exit(1); } if (val) Array[slot] |= (1 << bit); else Array[slot] &= ~(1 << bit); return sim->OutputVal; } int main(int argc, char* argv[]) { Verilated::debug(0); Verilated::commandArgs(argc, argv); VM_PREFIX* sim = new VM_PREFIX; int slot, bit, i; // clear all bits in the array for (slot = 0; slot < 3; slot++) for (bit = 0; bit < 2; bit++) // StepSim(sim, slot, bit, 0, 0); printf("\nTesting\n"); for (i = 0; i < 100; i++) // StepSim(sim, random() % 3, random() % 2, random() % 2, random() % 3); sim->final(); VL_DO_DANGLING(delete sim, sim); printf("*-* All Finished *-*\n"); } verilator-5.042/test_regress/t/t_math_yosys.v0000644000542200017500000000514515101701376022004 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 Claire Wolf. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [7:0] y1; // From d1 of demo_001.v wire [7:0] y2; // From d1 of demo_001.v wire [7:0] y3; // From d1 of demo_001.v wire [7:0] y4; // From d1 of demo_001.v wire [31:0] z0; // From d2 of demo_002.v wire [31:0] z1; // From d2 of demo_002.v wire [31:0] z2; // From d2 of demo_002.v wire [31:0] z3; // From d2 of demo_002.v // End of automatics demo_001 d1(/*AUTOINST*/ // Outputs .y1 (y1[7:0]), .y2 (y2[7:0]), .y3 (y3[7:0]), .y4 (y4[7:0])); demo_002 d2(/*AUTOINST*/ // Outputs .z0 (z0[31:0]), .z1 (z1[31:0]), .z2 (z2[31:0]), .z3 (z3[31:0])); // Test loop always @ (posedge clk) begin cyc <= cyc + 1; if (y1 !== 8'h7b) $stop; if (y2 !== 8'h7c) $stop; if (y3 !== 8'h7b) $stop; if (y4 !== 8'h7c) $stop; if (z0 !== 32'h00000000) $stop; if (z1 !== 32'hffffffff) $stop; if (z2 !== 32'hffffffff) $stop; if (z3 !== 32'hffffffff) $stop; if (cyc == 99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module demo_001(y1, y2, y3, y4); output [7:0] y1, y2, y3, y4; // verilator lint_off REALCVT localparam [7:0] P1 = 123.45; localparam real P2 = 123.45; localparam real P3 = 123; localparam P4 = 123.45; // verilator lint_off WIDTH assign y1 = P1 + 0.2; assign y2 = P2 + 0.2; assign y3 = P3 + 0.2; assign y4 = P4 + 0.2; // verilator lint_on WIDTH endmodule module demo_002(z0, z1, z2, z3); output [31:0] z0, z1, z2, z3; // verilator lint_off WIDTH assign z0 = 1'bx >= (-1 * -1.17); // verilator lint_on WIDTH assign z1 = 1 ? 1 ? -1 : 'd0 : 0.0; assign z2 = 1 ? -1 : 1 ? 'd0 : 0.0; assign z3 = 1 ? -1 : 'd0; endmodule verilator-5.042/test_regress/t/t_let.py0000755000542200017500000000072615101701376020557 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_to_basic_assignment_bad.out0000755000542200017500000000050015101701376026146 0ustar mahmoudyfreeshell%Error: t/t_class_to_basic_assignment_bad.v:26:29: Assign RHS 'class{}Foo' cannot be assigned to non-class 'int' 26 | new_node.phase_done = get(); | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_func_under.v0000644000542200017500000000140115101701376021724 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [3:0] counter = 0; integer l2; function automatic log2 (input [3:0] x); integer log2 = (x < 2) ? 1 : (x < 4) ? 2 : (x < 8) ? 3 : 4; endfunction always @(posedge clk) begin counter <= counter + 1; l2 <= log2(counter); // bug589: This failed with (%Error: Internal Error: Function not underneath a statement): $display("log2(%d) == %d", counter, log2(counter)); // $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_time_sc_bad_mt.out0000644000542200017500000000030615101701376023072 0ustar mahmoudyfreeshell%Error: SystemC's sc_set_time_resolution is 10^-9, which does not match Verilog timeprecision 10^-12. Suggest use 'sc_set_time_resolution(1s)', or Verilator '--timescale-override 1s/1s' Aborting... verilator-5.042/test_regress/t/t_interface_array_nocolon_bad.py0000755000542200017500000000077615101701376025473 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_inst_nansi.py0000755000542200017500000000073415101701376022137 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_implements_nested.py0000755000542200017500000000070615101701376023510 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.042/test_regress/t/t_covergroup_in_class.py0000755000542200017500000000070615101701376024037 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.passes() verilator-5.042/test_regress/t/t_clk_inp_init.py0000755000542200017500000000103015101701376022422 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the # GNU Lesser General Public License Version 3 or the Perl Artistic # License Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(make_main=False, verilator_flags2=["--exe", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_clk_inp_init.cpp0000644000542200017500000000252315101701376022561 0ustar mahmoudyfreeshell// This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include VM_PREFIX_INCLUDE void oneTest(int argc, char** argv, int seed) { uint64_t sim_time = 1000; #ifdef TEST_VERBOSE VL_PRINTF("== Seed=%d\n", seed); #endif const std::unique_ptr contextp{new VerilatedContext}; contextp->commandArgs(argc, argv); // Randomise initial state srand48(seed); srand48(5); contextp->randReset(123); // Construct the Verilated model, from Vtop.h generated from Verilating const std::unique_ptr topp{new VM_PREFIX{contextp.get()}}; // Start not in reset topp->rst_n = 1; topp->clk = 0; topp->eval(); // Tick for a little bit while (contextp->time() < sim_time && !contextp->gotFinish()) { topp->clk = 0; topp->eval(); contextp->timeInc(5); topp->clk = 1; topp->eval(); contextp->timeInc(5); } if (!contextp->gotFinish()) { vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); } topp->final(); } int main(int argc, char** argv) { #if VL_DEBUG // Verilated::debug(1); #endif for (int seed = 123; seed < 133; ++seed) oneTest(argc, argv, seed); return 0; } verilator-5.042/test_regress/t/t_lint_sideeffect_bad.py0000755000542200017500000000076615101701376023734 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_alias_unsup.py0000755000542200017500000000077615101701376022323 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_struct_contents_bad.py0000755000542200017500000000076615101701376024046 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_fallback_bad.v0000644000542200017500000000136415101701376022151 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 int f = 5; task tsk; endtask package pkg; endpackage module subm; endmodule module submo; subm sub2(); endmodule module t; submo sub1(); class Base;endclass class Cls extends Base; task calltsk; super.tsk; this.tsk; super.f = 8; this.f = 8; sub1.sub2.tsk; pkg::f = 8; pkg::tsk(); sub1.sub2.f = 8; sub1.sub2.f.f = 8; endtask endclass Cls obj = new; initial begin obj.calltsk; if (f != 5) $stop; end endmodule verilator-5.042/test_regress/t/t_interface_modport_bad.v0000644000542200017500000000077115101701376024117 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface ifc; integer ok; modport out_modport (output ok); endinterface module t; ifc itop(); counter_ansi c1 (.isub(itop), .i_value(4'h4)); endmodule module counter_ansi ( ifc.oop_modport isub, // Bad input logic [3:0] i_value ); endmodule verilator-5.042/test_regress/t/t_let_recurse_bad.v0000644000542200017500000000067715101701376022734 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; let RECURSE(a) = (a == 1) ? 1 : RECURSE(a - 1); // BAD no recursion per IEEE 1800-2023 11.12 initial begin if (RECURSE(1) != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_concat_large_bad.out0000644000542200017500000000100015101701376023360 0ustar mahmoudyfreeshell%Warning-WIDTHCONCAT: t/t_concat_large_bad.v:9:29: More than a 8k bit replication is probably wrong: 32768 : ... note: In instance 't' 9 | wire [32767:0] a = {32768{1'b1}}; | ^ ... For warning description see https://verilator.org/warn/WIDTHCONCAT?v=latest ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_timing_nba_2.py0000755000542200017500000000077115101701376022323 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_stream3.v0000644000542200017500000000510515101701376021157 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; /*AUTOWIRE*/ generate for (genvar width=1; width<=16; width++) begin for (genvar amt=1; amt<=width; amt++) begin Test #(.WIDTH(width), .AMT(amt)) test (.ins(crc[width-1:0])); end end endgenerate // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x\n", $time, cyc, crc); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h0 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Inputs ins ); parameter WIDTH = 1; parameter AMT = 1; input [WIDTH-1:0] ins; reg [WIDTH-1:0] got; reg [WIDTH-1:0] expec; int istart; int bitn; int ostart; always @* begin got = { << AMT {ins}}; // Note always starts with right-most bit expec = 0; for (istart=0; istart= 0 && (ostart+bitn) < WIDTH && (ostart+bitn) >= 0) begin expec[ostart+bitn] = ins[istart+bitn]; end end end `ifdef TEST_VERBOSE $write("[%0t] exp %0d'b%b got %0d'b%b = { << %0d { %0d'b%b }}\n", $time, WIDTH, expec, WIDTH, got, AMT, WIDTH, ins); `endif `checkh(got, expec); end endmodule verilator-5.042/test_regress/t/t_lint_vcmarker_bad.v0000644000542200017500000000077415101701376023256 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; <<<<<<< HEAD // Intentional test: This conflict marker should be here initial $display("Hello"); ======= // Intentional test: This conflict marker should be here initial $display("Goodbye"); >>>>>>> MERGE // Intentional test: This conflict marker should be here endmodule verilator-5.042/test_regress/t/t_unroll_delay.v0000644000542200017500000000130215101701376022265 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; integer i; integer j; always @(i, j) $display("[%0t] B %0d %0d", $time, i, j); // See issue #4237 initial begin for(i = 1; i < 3 ; i = i + 1) begin $display(""); for(j = 6; j < 8; j = j + 1) begin $display("[%0t] A %0d %0d", $time, i, j); #1; $display("[%0t] C %0d %0d", $time, i, j); end #9; end #10; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_string_sel.py0000755000542200017500000000072615101701376022144 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_foreach.py0000755000542200017500000000201715101701376021375 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--assert']) test.execute() # We expect all loops should be unrolled by verilator, # none of the loop variables should exist in the output: for filename in test.glob_some(test.obj_dir + "/" + test.vm_prefix + "*.cpp"): test.file_grep_not(filename, r'index_') # Further, we expect that all logic within the loop should # have been evaluated inside the compiler. So there should be # no references to 'sum' in the .cpp. for filename in test.glob_some(test.obj_dir + "/" + test.vm_prefix + "*.cpp"): test.file_grep_not(filename, r'[^a-zA-Z]sum[^a-zA-Z]') test.passes() verilator-5.042/test_regress/t/t_struct_packed_sysfunct.py0000755000542200017500000000073415101701376024563 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_compiler_include.py0000755000542200017500000000130515101701376023302 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(make_top_shell=False, make_main=False, verilator_flags2=[ "--exe", test.pli_filename, "--compiler-include", test.t_dir + "/t_compiler_include.h", "--output-split 0" ]) test.execute() test.passes() verilator-5.042/test_regress/t/t_disable_genfor2.py0000755000542200017500000000077115101701376023020 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_mod_interface_clocking_bad.v0000644000542200017500000000107015101701376025054 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 interface mem_if ( input wire clk ); logic reset; clocking cb @(posedge clk); output reset; endclocking modport mp(input clk, clocking reset, clocking cx); endinterface module sub ( mem_if.mp x ); initial begin x.cb.reset <= 1; end endmodule module t (); logic clk = 0; mem_if m_if (clk); sub i_sub (m_if); endmodule verilator-5.042/test_regress/t/t_lint_vcmarker_bad.py0000755000542200017500000000076315101701376023442 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_scheduling_4.py0000755000542200017500000000073415101701376022342 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_assert_ctl_arg_noinl.py0000755000542200017500000000204615101701376024163 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t_assert_ctl_arg.v" test.pli_filename = "t/t_assert_ctl_arg.cpp" test.compile(make_top_shell=False, make_main=False, verilator_flags2=[ "--assert", "--timing", "--coverage-user", "--exe", test.pli_filename, "-fno-inline" ], nc_flags2=["+nccovoverwrite", "+nccoverage+all", "+nccovtest+" + test.name]) test.execute(all_run_flags=["+verilator+error+limit+100"], expect_filename=test.t_dir + "/t_assert_ctl_arg.out") test.files_identical(test.coverage_filename, test.t_dir + "/t_assert_ctl_arg.dat.out") test.passes() verilator-5.042/test_regress/t/t_interconnect.py0000755000542200017500000000107515101701376022464 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"], fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interconnect.v0000644000542200017500000000162115101701376022273 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Note: Other simulator's support for interconnect seems rare, the below might // not be correct code. module t; interconnect a; interconnect b; moda suba (.a, .b); modb #(.TA_t(real)) subb (.a(a), .b(b)); endmodule module moda ( output interconnect a, output interconnect b); modaa subaa (.a, .b); endmodule module modaa ( output real a, output int b); initial begin a = 1.234; b = 1234; end endmodule module modb #(parameter type TA_t = int) ( input TA_t a, input int b); initial begin #10; if (a != 1.234) $stop; if (b != 1234) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_func_outp.py0000755000542200017500000000073415101701376021774 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_disable_outside2.v0000644000542200017500000000133315101701376023021 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t; initial begin for (int i = 0; i < 3; i++) begin begin : blk int x = 0; fork : fork_blk begin x = 1; #2; x = 2; end join_none #1; if (i < 2) disable fork_blk; #2; if (i < 2 && x != 1) $stop; if (i == 2 && x != 2) $stop; end end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_constraint_json_only.py0000755000542200017500000000135415101701376024247 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') out_filename = test.obj_dir + "/V" + test.name + ".tree.json" test.compile( verilator_flags2=['--no-std', '--json-only', '--no-json-edit-nums', '-Wno-CONSTRAINTIGN'], verilator_make_gmake=False, make_top_shell=False, make_main=False) test.files_identical(out_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dpi_dup_bad.out0000644000542200017500000000131215101701376022371 0ustar mahmoudyfreeshell%Error: t/t_dpi_dup_bad.v:13:51: Duplicate declaration of DPI function with different signature: 'dpii_fa_bit' 13 | import "DPI-C" pure dpii_fa_bit = function int oth_f_int2(input int i, input int bad); | ^~~~~~~~~~ : ... New signature: pure int dpii_fa_bit (int, int) t/t_dpi_dup_bad.v:12:47: ... Original signature: int dpii_fa_bit (int) 12 | import "DPI-C" dpii_fa_bit = function int oth_f_int1(input int i); | ^~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_timing_fork_rec_method.py0000755000542200017500000000077115101701376024474 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_assert_ctl_arg.cpp0000644000542200017500000000724015101701376023114 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include "verilated_cov.h" #include #include VM_PREFIX_INCLUDE // These require the above. Comment prevents clang-format moving them #include "TestCheck.h" unsigned int main_time = 0; double sc_time_stamp() { return main_time; } //====================================================================== int errors = 0; void verilatedTest() { const std::unique_ptr contextp{new VerilatedContext}; // Assert enable/disable contextp->assertOn(true); TEST_CHECK_NZ(contextp->assertOn()); contextp->assertOn(false); TEST_CHECK_Z(contextp->assertOn()); TEST_CHECK_Z(contextp->assertOnGet(1, 1)); // Setting one type contextp->assertOnSet(1, 1); TEST_CHECK_NZ(contextp->assertOnGet(1, 1)); TEST_CHECK_NZ(contextp->assertOn()); TEST_CHECK_Z(contextp->assertOnGet(2, 2)); // Setting types contextp->assertOn(false); contextp->assertOnSet(1, 3); TEST_CHECK_NZ(contextp->assertOnGet(1, 3)); TEST_CHECK_NZ(contextp->assertOnGet(1, 2)); TEST_CHECK_NZ(contextp->assertOnGet(1, 1)); TEST_CHECK_Z(contextp->assertOnGet(1, 0)); TEST_CHECK_Z(contextp->assertOnGet(2, 0)); TEST_CHECK_Z(contextp->assertOnGet(0, 0)); // Setting multiple types separately contextp->assertOn(false); contextp->assertOnSet(0, 1); contextp->assertOnSet(1, 2); contextp->assertOnSet(2, 3); TEST_CHECK_NZ(contextp->assertOn()); TEST_CHECK_Z(contextp->assertOnGet(0, 1)); TEST_CHECK_Z(contextp->assertOnGet(1, 1)); TEST_CHECK_NZ(contextp->assertOnGet(1, 2)); TEST_CHECK_NZ(contextp->assertOnGet(2, 1)); TEST_CHECK_NZ(contextp->assertOnGet(2, 2)); TEST_CHECK_NZ(contextp->assertOnGet(2, 3)); TEST_CHECK_Z(contextp->assertOnGet(0, 2)); TEST_CHECK_Z(contextp->assertOnGet(4, 1)); TEST_CHECK_Z(contextp->assertOnGet(8, 7)); // Clearing selected types contextp->assertOn(true); contextp->assertOnClear(1, 3); contextp->assertOnClear(1, 4); TEST_CHECK_Z(contextp->assertOnGet(1, 1)); TEST_CHECK_Z(contextp->assertOnGet(1, 2)); TEST_CHECK_Z(contextp->assertOnGet(1, 4)); contextp->assertOnClear(4, 4); TEST_CHECK_Z(contextp->assertOnGet(4, 4)); TEST_CHECK_NZ(contextp->assertOnGet(4, 1)); TEST_CHECK_NZ(contextp->assertOnGet(4, 2)); TEST_CHECK_NZ(contextp->assertOn()); // Clearing all assert types contextp->assertOn(true); contextp->assertOnClear(255, 7); // Everything is disabled except internal asserts TEST_CHECK_NZ(contextp->assertOn()); contextp->assertOn(false); // Now everything is disabled TEST_CHECK_Z(contextp->assertOn()); } int main(int argc, char** argv) { verilatedTest(); if (errors) return 10; const std::unique_ptr contextp{new VerilatedContext}; contextp->threads(1); contextp->commandArgs(argc, argv); contextp->debug(0); srand48(5); const std::unique_ptr topp{new VM_PREFIX{"top"}}; constexpr uint64_t sim_time = 100; while ((contextp->time() < sim_time) && !contextp->gotFinish()) { topp->clk = !topp->clk; topp->eval(); contextp->timeInc(1); } const std::string filename = std::string{VL_STRINGIFY(TEST_OBJ_DIR) "/coverage.dat"}; contextp->coveragep()->write(filename); if (!contextp->gotFinish()) { vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); } topp->final(); return 0; } verilator-5.042/test_regress/t/t_hierarchy_identifier.v0000644000542200017500000000212615101701376023761 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Iztok Jeras. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; parameter SIZE = 8; integer cnt = 0; logic [SIZE-1:0] vld_for; logic vld_if = 1'b0; logic vld_else = 1'b0; genvar i; // event counter always @ (posedge clk) begin cnt <= cnt + 1; end // finish report always @ (posedge clk) if (cnt==SIZE) begin : \0escaped___name $write("*-* All Finished *-*\n"); $finish; end : \0escaped___name generate for (i=0; i0) begin : generate_if_if always @ (posedge clk) vld_if <= 1'b1; end : generate_if_if else begin : generate_if_else always @ (posedge clk) vld_else <= 1'b1; end : generate_if_else endgenerate endmodule : t verilator-5.042/test_regress/t/t_class_param_virtual_bad.py0000755000542200017500000000076315101701376024635 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_gen_for_shuffle.py0000755000542200017500000000073415101701376023125 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_struct_param_overflow.py0000755000542200017500000000073415101701376024421 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_for_local.v0000644000542200017500000000270115101701376021540 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [7:0] cyc; initial cyc = 0; reg [31:0] loops; reg [31:0] loops2; always @ (posedge clk) begin cyc <= cyc+8'd1; if (cyc == 8'd1) begin $write("[%0t] t_loop: Running\n", $time); // Unwind < loops = 0; loops2 = 0; for (int i=0; i<16; i=i+1) begin loops = loops + i; // surefire lint_off_line ASWEMB loops2 = loops2 + i; // surefire lint_off_line ASWEMB end if (loops !== 120) $stop; if (loops2 !== 120) $stop; // Check we can declare the same signal twice loops = 0; for (int i=0; i<=16; i=i+1) begin loops = loops + 1; end if (loops !== 17) $stop; // Check type is correct loops = 0; for (byte unsigned i=5; i>4; i=i+1) begin loops = loops + 1; end if (loops !== 251) $stop; // Check large loops loops = 0; for (int i=0; i<100000; i=i+1) begin loops = loops + 1; end if (loops !== 100000) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_math_svl2.v0000644000542200017500000000205115101701376021475 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin // New number format if ('0 !== {66{1'b0}}) $stop; if ('1 !== {66{1'b1}}) $stop; if ('x !== {66{1'bx}}) $stop; if ('z !== {66{1'bz}}) $stop; `ifndef NC // NC-Verilog 5.50-s09 chokes on this test if ("\v" != 8'd11) $stop; if ("\f" != 8'd12) $stop; if ("\a" != 8'd7) $stop; if ("\x9a" != 8'h9a) $stop; if ("\xf1" != 8'hf1) $stop; `endif end if (cyc==8) begin end if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.042/test_regress/t/t_interface_array2_noinl.py0000755000542200017500000000107415101701376024407 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_array2.v" test.compile(timing_loop=True, v_flags2=["-fno-inline --timing"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_sc_vl_assign_sbw.cpp0000644000542200017500000000144515101701376023446 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 #include VM_PREFIX_INCLUDE #include #include int sc_main(int argc, char* argv[]) { using namespace sc_core; VM_PREFIX* tb = new VM_PREFIX{"t"}; constexpr int val = 1; sc_signal> SC_NAMED(in, val); sc_signal> SC_NAMED(out); tb->in(in); tb->out(out); bool pass = out.read().iszero(); sc_start(1, SC_NS); pass &= !out.read().iszero(); pass &= out == val; tb->final(); VL_DO_DANGLING(delete tb, tb); if (pass) VL_PRINTF("*-* All Finished *-*\n"); return 0; } verilator-5.042/test_regress/t/t_disable_genfor_unsup.v0000644000542200017500000000115715101701376024001 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t; for (genvar j = 0; j < 3; j++) begin : genblk initial begin : init int i; begin : named for (i = 0; i < 10; ++i) begin : loop if (i == 5) disable t.genblk[0].init.named; end end if (j == 0 && i != 5) $stop; if (j != 0 && i != 10) $stop; end end initial begin #1; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_json_only_flat_pub_mod.py0000755000542200017500000000137115101701376024515 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') out_filename = test.obj_dir + "/V" + test.name + ".tree.json" test.compile(verilator_flags2=['--no-std', '--json-only', '--no-json-edit-nums', '--flatten'], verilator_make_gmake=False, make_top_shell=False, make_main=False) test.files_identical(out_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_tri_gen.py0000755000542200017500000000073415101701376021421 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_wrapper_legacy_time64.py0000755000542200017500000000133415101701376024163 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_wrapper_legacy.cpp" test.top_filename = "t/t_wrapper_legacy.v" test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename], make_flags=['CPPFLAGS_ADD=-DVL_TIME_STAMP64']) test.execute() test.passes() verilator-5.042/test_regress/t/t_module_input_default_value.v0000644000542200017500000001170615101701376025211 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Andrew Ranck // SPDX-License-Identifier: CC0-1.0 // Test for Issue#5358: Support default value on module input. // This test is not expected to fail. There are 3 DUTs using various defaulted (and not) input values, // with expected checks over a few cycles. module dut_default_input0 ( input logic required_input, input logic i = (1'b0 && 1'b0), // 0 output logic o ); assign o = i; endmodule module dut_default_input1 ( input logic i = 1'b1, input logic required_input, output logic o ); assign o = i; endmodule module dut_default_input_logic32 #( parameter bit [31:0] DefaultValueI = 32'h12345678 ) ( input logic [31:0] i = DefaultValueI, output logic [31:0] o ); assign o = i; endmodule module dut_default_input_wire32 ( input wire [31:0] i = 32'h12345678, output logic [31:0] o ); assign o = i; endmodule module t (/*AUTOARG*/ // Inputs clk ); input clk; int cyc = 0; wire logic1 = 1'b1; function automatic logic logic0_from_some_function(); return 1'b0; endfunction : logic0_from_some_function // 1800-2009, a few flavors to test: // 1. Port omitted from port list on instance (uses default value, NOT implicit net) // 2. Port included on instance and left open (uses default value) // 3. Port included on instance and overridden. // 1. DUT instances with default values and port omitted // instance names are u_dut*_default logic dut0_o_default; dut_default_input0 u_dut0_default (.required_input(1), /*.i(),*/ .o(dut0_o_default)); logic dut1_o_default; dut_default_input1 u_dut1_default (/*.i(),*/ .o(dut1_o_default), .required_input(1)); logic [31:0] dut_logic32_o_default; dut_default_input_logic32 u_dut_logic32_default (/*.i(),*/ .o(dut_logic32_o_default)); // 2. DUT instances with default values and port open // instance names are u_dut*_open logic dut0_o_open; dut_default_input0 u_dut0_open (.required_input(1), .i(), // open .o(dut0_o_open)); logic dut1_o_open; dut_default_input1 u_dut1_open (.i(), // open .o(dut1_o_open), .required_input(1)); logic [31:0] dut_logic32_o_open; dut_default_input_logic32 u_dut_logic32_open (.i(), // open .o(dut_logic32_o_open)); logic [31:0] dut_wire32_o_open; dut_default_input_wire32 u_dut_wire32_open (.i(), // open .o(dut_wire32_o_open)); // 3. DUT instances with overriden values // instance names are u_dut*_overriden // Have u_dut0_overriden get its overriden value from a signal logic dut0_o_overriden; dut_default_input0 u_dut0_overriden (.required_input(1), .i(logic1), // from wire .o(dut0_o_overriden)); // Have u_dut1_overriden get its overriden value from a function. logic dut1_o_overriden; dut_default_input1 u_dut1_overriden (.i(logic0_from_some_function()), // from function .o(dut1_o_overriden), .required_input(1)); logic [31:0] dut_logic32_o_overriden; logic [31:0] dut_logic32_want_overriden; dut_default_input_logic32 #(.DefaultValueI(32'h2222_3333) // dontcare, we're overriding on input ) u_dut_logic32_overriden (.i(32'h6789_2345 + 32'(cyc)), // from inline logic .o(dut_logic32_o_overriden)); assign dut_logic32_want_overriden = 32'h6789_2345 + 32'(cyc); // expected value i --> o always @(posedge clk) begin : main cyc <= cyc + 1; if (cyc > 2) begin // check these for a few cycles to make sure it's constant $display("%t %m: outputs - defaults got {%0d %0d %0x}, want {0 1 12345678}", $time, dut0_o_default, dut1_o_default, dut_logic32_o_default); if (dut0_o_default != 0) $error; if (dut1_o_default != 1) $error; if (dut_logic32_o_default != 32'h1234_5678) $error; $display("%t %m: outputs - open got {%0d %0d %0x}, want {0 1 12345678}", $time, dut0_o_open, dut1_o_open, dut_logic32_o_open); if (dut0_o_open != 0) $error; if (dut1_o_open != 1) $error; if (dut_logic32_o_open != 32'h1234_5678) $error; if (dut_wire32_o_open != 32'h1234_5678) $error; // despite the port map override. At least the parameter goes through? $display("%t %m: outputs - overrides got {%0d %0d %0x} want {1 0 %0x}", $time, dut0_o_overriden, dut1_o_overriden, dut_logic32_o_overriden, dut_logic32_want_overriden); if (dut0_o_overriden != 1) $error; if (dut1_o_overriden != 0) $error; if (dut_logic32_o_overriden != dut_logic32_want_overriden) $error; end if (cyc == 10) begin // done checking various DUTs and finish $display("%t %m: cyc=%0d", $time, cyc); $write("*-* All Finished *-*\n"); $finish(); end end endmodule : t verilator-5.042/test_regress/t/t_clocking_notiming.py0000755000542200017500000000102515101701376023461 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--no-timing"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_hier_trace.out0000644000542200017500000001403215101701376022247 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $var wire 1 # clk $end $var wire 1 $ reset_l $end $scope module t $end $var wire 1 # clk $end $var wire 1 $ reset_l $end $scope module u0_sub_top $end $var wire 1 # clk $end $var wire 1 $ reset_l $end $upscope $end $scope module u1_sub_top $end $var wire 1 # clk $end $var wire 1 $ reset_l $end $upscope $end $upscope $end $upscope $end $scope module top.t.u0_sub_top $end $var wire 1 & clk $end $var wire 1 ' reset_l $end $scope module sub_top $end $var wire 1 & clk $end $var wire 1 ' reset_l $end $scope module u0 $end $var wire 1 & clk $end $var wire 1 ' reset_l $end $upscope $end $scope module u1 $end $var wire 1 & clk $end $var wire 1 ' reset_l $end $upscope $end $scope module u2 $end $var wire 1 & clk $end $var wire 1 ' reset_l $end $upscope $end $scope module u3 $end $var wire 1 & clk $end $var wire 1 ' reset_l $end $upscope $end $scope module u4 $end $var wire 1 & clk $end $var wire 1 ' reset_l $end $upscope $end $scope module u5 $end $var wire 1 & clk $end $var wire 1 ' reset_l $end $upscope $end $scope module u6 $end $var wire 1 & clk $end $var wire 1 ' reset_l $end $upscope $end $scope module u7 $end $var wire 1 & clk $end $var wire 1 ' reset_l $end $upscope $end $upscope $end $upscope $end $scope module top.t.u1_sub_top $end $var wire 1 ) clk $end $var wire 1 * reset_l $end $scope module sub_top $end $var wire 1 ) clk $end $var wire 1 * reset_l $end $scope module u0 $end $var wire 1 ) clk $end $var wire 1 * reset_l $end $upscope $end $scope module u1 $end $var wire 1 ) clk $end $var wire 1 * reset_l $end $upscope $end $scope module u2 $end $var wire 1 ) clk $end $var wire 1 * reset_l $end $upscope $end $scope module u3 $end $var wire 1 ) clk $end $var wire 1 * reset_l $end $upscope $end $scope module u4 $end $var wire 1 ) clk $end $var wire 1 * reset_l $end $upscope $end $scope module u5 $end $var wire 1 ) clk $end $var wire 1 * reset_l $end $upscope $end $scope module u6 $end $var wire 1 ) clk $end $var wire 1 * reset_l $end $upscope $end $scope module u7 $end $var wire 1 ) clk $end $var wire 1 * reset_l $end $upscope $end $upscope $end $upscope $end $scope module top.t.u0_sub_top.sub_top.u0 $end $var wire 1 , clk $end $var wire 1 - reset_l $end $scope module detail_code $end $var wire 1 , clk $end $var wire 1 - reset_l $end $upscope $end $upscope $end $scope module top.t.u0_sub_top.sub_top.u1 $end $var wire 1 / clk $end $var wire 1 0 reset_l $end $scope module detail_code $end $var wire 1 / clk $end $var wire 1 0 reset_l $end $upscope $end $upscope $end $scope module top.t.u0_sub_top.sub_top.u2 $end $var wire 1 2 clk $end $var wire 1 3 reset_l $end $scope module detail_code $end $var wire 1 2 clk $end $var wire 1 3 reset_l $end $upscope $end $upscope $end $scope module top.t.u0_sub_top.sub_top.u3 $end $var wire 1 5 clk $end $var wire 1 6 reset_l $end $scope module detail_code $end $var wire 1 5 clk $end $var wire 1 6 reset_l $end $upscope $end $upscope $end $scope module top.t.u0_sub_top.sub_top.u4 $end $var wire 1 8 clk $end $var wire 1 9 reset_l $end $scope module detail_code $end $var wire 1 8 clk $end $var wire 1 9 reset_l $end $upscope $end $upscope $end $scope module top.t.u0_sub_top.sub_top.u5 $end $var wire 1 ; clk $end $var wire 1 < reset_l $end $scope module detail_code $end $var wire 1 ; clk $end $var wire 1 < reset_l $end $upscope $end $upscope $end $scope module top.t.u0_sub_top.sub_top.u6 $end $var wire 1 > clk $end $var wire 1 ? reset_l $end $scope module detail_code $end $var wire 1 > clk $end $var wire 1 ? reset_l $end $upscope $end $upscope $end $scope module top.t.u0_sub_top.sub_top.u7 $end $var wire 1 A clk $end $var wire 1 B reset_l $end $scope module detail_code $end $var wire 1 A clk $end $var wire 1 B reset_l $end $upscope $end $upscope $end $scope module top.t.u1_sub_top.sub_top.u0 $end $var wire 1 D clk $end $var wire 1 E reset_l $end $scope module detail_code $end $var wire 1 D clk $end $var wire 1 E reset_l $end $upscope $end $upscope $end $scope module top.t.u1_sub_top.sub_top.u1 $end $var wire 1 G clk $end $var wire 1 H reset_l $end $scope module detail_code $end $var wire 1 G clk $end $var wire 1 H reset_l $end $upscope $end $upscope $end $scope module top.t.u1_sub_top.sub_top.u2 $end $var wire 1 J clk $end $var wire 1 K reset_l $end $scope module detail_code $end $var wire 1 J clk $end $var wire 1 K reset_l $end $upscope $end $upscope $end $scope module top.t.u1_sub_top.sub_top.u3 $end $var wire 1 M clk $end $var wire 1 N reset_l $end $scope module detail_code $end $var wire 1 M clk $end $var wire 1 N reset_l $end $upscope $end $upscope $end $scope module top.t.u1_sub_top.sub_top.u4 $end $var wire 1 P clk $end $var wire 1 Q reset_l $end $scope module detail_code $end $var wire 1 P clk $end $var wire 1 Q reset_l $end $upscope $end $upscope $end $scope module top.t.u1_sub_top.sub_top.u5 $end $var wire 1 S clk $end $var wire 1 T reset_l $end $scope module detail_code $end $var wire 1 S clk $end $var wire 1 T reset_l $end $upscope $end $upscope $end $scope module top.t.u1_sub_top.sub_top.u6 $end $var wire 1 V clk $end $var wire 1 W reset_l $end $scope module detail_code $end $var wire 1 V clk $end $var wire 1 W reset_l $end $upscope $end $upscope $end $scope module top.t.u1_sub_top.sub_top.u7 $end $var wire 1 Y clk $end $var wire 1 Z reset_l $end $scope module detail_code $end $var wire 1 Y clk $end $var wire 1 Z reset_l $end $upscope $end $upscope $end $enddefinitions $end #0 0# 0$ 0& 0' 0) 0* 0, 0- 0/ 00 02 03 05 06 08 09 0; 0< 0> 0? 0A 0B 0D 0E 0G 0H 0J 0K 0M 0N 0P 0Q 0S 0T 0V 0W 0Y 0Z verilator-5.042/test_regress/t/t_inside_unpacked_param.out0000644000542200017500000000137015101701376024450 0ustar mahmoudyfreeshell%Error: t/t_inside_unpacked_param.v:13:35: Expecting expression to be constant, but can't convert a CMETHODHARD 'inside' to constant. : ... note: In instance 't' 13 | localparam HIT_INSIDE = HIT_LP inside {CHECKLIST_P}; | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_inside_unpacked_param.v:14:37: Expecting expression to be constant, but can't convert a CMETHODHARD 'inside' to constant. : ... note: In instance 't' 14 | localparam MISS_INSIDE = MISS_LP inside {CHECKLIST_P}; | ^~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_trace_string.py0000755000542200017500000000100115101701376022442 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--cc --trace-vcd']) test.execute() test.passes() verilator-5.042/test_regress/t/t_json_only_debugcheck.py0000755000542200017500000000146415101701376024151 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_enum_type_methods.v" out_filename = test.obj_dir + "/V" + test.name + ".tree.json" test.compile(verilator_flags2=['--no-std', '--debug-check', '--no-json-edit-nums', '--flatten'], verilator_make_gmake=False, make_top_shell=False, make_main=False) test.files_identical(out_filename, test.golden_filename, 'logfile') test.passes() verilator-5.042/test_regress/t/t_class_param_pkg.py0000755000542200017500000000073415101701376023120 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_param_implicit_string.v0000644000542200017500000000122415101701376024157 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilog_format: off `define stop $stop `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); // verilog_format: on module t; sub u_sub (); endmodule module sub #( parameter INDEX = 4096 ); parameter STRG = $sformatf("stringed[%0d]", INDEX); initial begin `checks(STRG, "stringed[4096]"); $finish; end endmodule verilator-5.042/test_regress/t/t_case_dupitems.v0000644000542200017500000000403015101701376022422 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [1:0] in = crc[1:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [1:0] out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out (out[1:0]), // Inputs .in (in[1:0])); // Aggregate outputs into a single result vector wire [63:0] result = {62'h0, out}; // What checksum will we end up with `define EXPECTED_SUM 64'hbb2d9709592f64bd // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs out, // Inputs in ); input [1:0] in; output reg [1:0] out; always @* begin // bug99: Internal Error: ../V3Ast.cpp:495: New node already linked? case (in[1:0]) 2'd0, 2'd1, 2'd2, 2'd3: begin out = in; end endcase end endmodule verilator-5.042/test_regress/t/t_dfg_regularize_circular.py0000755000542200017500000000070615101701376024646 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.passes() verilator-5.042/test_regress/t/t_interface_and_struct_pattern.v0000644000542200017500000000215515101701376025526 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: SystemVerilog interface test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Iztok Jeras. // SPDX-License-Identifier: CC0-1.0 package Package_pkg; typedef struct packed { int bar; int baz; } pkg_struct_t; endpackage interface intf #(parameter type data_type = bit) (input wire clk, input wire rst); data_type data; modport source ( input clk, rst, output data ); endinterface module sub ( intf.source bar, input clk, input rst); typedef struct packed { int foo; int baz; } struct_t; intf #(.data_type(struct_t)) the_intf (.*); Package_pkg::pkg_struct_t output_bar = Package_pkg::pkg_struct_t'{ bar: the_intf.data.foo, baz: the_intf.data.baz }; endmodule module t(clk); input clk; logic rst; intf bar (.*); sub the_sub ( .bar(bar), .clk, .rst ); // finish report always @ (posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_lint_infinite_bad.v0000644000542200017500000000063315101701376023243 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (); initial begin forever begin end // verilator lint_off UNSIGNED for (reg [31:0] i=0; i>=0; i=i+1) begin end $display; // So loop not eaten end endmodule verilator-5.042/test_regress/t/t_tri_select.cpp0000644000542200017500000000367015101701376022260 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include VM_PREFIX_INCLUDE VM_PREFIX* tb = nullptr; double sc_time_stamp() { return 0; } bool check() { bool pass = true; #ifdef TEST_VERBOSE bool verbose = true; #else bool verbose = false; #endif int Y = ((tb->OE1) & (!tb->OE2)) ? tb->A1 : ((!tb->OE1) & (tb->OE2)) ? tb->A2 : ((tb->OE1) & (tb->OE2)) ? (tb->A1 | tb->A2) : 3; // pullup int W = (((tb->OE2) ? (tb->A2 & 0x1) : 0) << tb->A1) | (((tb->OE1) ? (tb->A2 >> 1) & 0x1 : 0) << tb->A2); if (tb->Y1 == Y && tb->Y2 == Y && tb->Y3 == Y && tb->W == W) { pass = true; if (verbose) printf("- pass: "); } else { pass = false; verbose = true; printf("%%E-Fail: "); } if (verbose) printf("Read: OE1=%d OE2=%d A1=0x%x A2=0x%x Y1=0x%x Y2=0x%x Y3=0x%x W=0x%x Expected: " "Y1=Y2=Y3=%d and W=0x%x\n", tb->OE1, tb->OE2, tb->A1, tb->A2, tb->Y1, tb->Y2, tb->Y3, tb->W, Y, W); return pass; } int main() { Verilated::debug(0); tb = new VM_PREFIX{"tb"}; // loop through every possibility and check the result bool pass = true; for (tb->OE1 = 0; tb->OE1 < 2; tb->OE1++) { for (tb->OE2 = 0; tb->OE2 < 2; tb->OE2++) { for (tb->A1 = 0; tb->A1 < 4; tb->A1++) { for (tb->A2 = 0; tb->A2 < 4; tb->A2++) { tb->eval(); if (!check()) pass = false; } } } } if (pass) { VL_PRINTF("*-* All Finished *-*\n"); tb->final(); } else { vl_fatal(__FILE__, __LINE__, "top", "Unexpected results from t_tri_select\n"); } VL_DO_DANGLING(delete tb, tb); return 0; } verilator-5.042/test_regress/t/t_const_hi.v0000644000542200017500000000232215101701376021405 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [1:0] reg_i; reg [1049:0] pad0; reg [1049:0] reg_o; reg [1049:0] spad1; /*AUTOWIRE*/ always_comb begin if (reg_i[1] == 1'b1) reg_o = {986'd0, 64'hffff0000ffff0000}; else if (reg_i[0] == 1'b1) reg_o = {64'hffff0000ffff0000, 986'd0}; else reg_o = 1050'd0; end // Test loop always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 0) begin reg_i <= 2'b00; pad0 <= '1; spad1 <= '1; end else if (cyc == 1) begin reg_i <= 2'b01; end else if (cyc == 2) begin if (reg_o != {64'hffff0000ffff0000, 986'd0}) $stop; reg_i <= 2'b10; end else if (cyc == 99) begin if (reg_o != {986'd0, 64'hffff0000ffff0000}) $stop; if (pad0 != '1) $stop; if (spad1 != '1) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_dfg_3817.py0000755000542200017500000000070615101701376021213 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.passes() verilator-5.042/test_regress/t/t_strength_bufif1.out0000644000542200017500000000044515101701376023237 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_strength_bufif1.v:9:11: Unsupported: Strength specifier on this gate type 9 | bufif1 (strong0, strong1) (a, 1'b1, 1'b1); | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_inst_first.v0000644000542200017500000001024415101701376021765 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk, fastclk ); input clk; input fastclk; genvar unused; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire o_com; // From b of t_inst_first_b.v wire o_seq_d1r; // From b of t_inst_first_b.v // End of automatics integer _mode; // initial _mode=0 reg na,nb,nc,nd,ne; wire ma,mb,mc,md,me; wire da,db,dc,dd,de; reg [7:0] wa,wb,wc,wd,we; wire [7:0] qa,qb,qc,qd,qe; wire [5:0] ra; wire [4:0] rb; wire [29:0] rc; wire [63:0] rd; reg [5:0] sa; reg [4:0] sb; reg [29:0] sc; reg [63:0] sd; reg _guard1; initial _guard1=0; wire [104:0] r_wide = {ra,rb,rc,rd}; reg _guard2; initial _guard2=0; wire [98:0] r_wide0 = {rb,rc,rd}; reg _guard3; initial _guard3=0; wire [93:0] r_wide1 = {rc,rd}; reg _guard4; initial _guard4=0; wire [63:0] r_wide2 = {rd}; reg _guard5; initial _guard5=0; wire [168:0] r_wide3 = {ra,rb,rc,rd,rd}; reg [127:0] _guard6; initial _guard6=0; t_inst_first_a a ( .clk (clk), // Outputs .o_w5 ({ma,mb,mc,md,me}), .o_w5_d1r ({da,db,dc,dd,de}), .o_w40 ({qa,qb,qc,qd,qe}), .o_w104 ({ra,rb,rc,rd}), // Inputs .i_w5 ({na,nb,nc,nd,ne}), .i_w40 ({wa,wb,wc,wd,we}), .i_w104 ({sa,sb,sc,sd}) ); reg i_seq; reg i_com; wire [15:14] o2_comhigh; t_inst_first_b b ( .o2_com (o2_comhigh), .i2_com ({i_com,~i_com}), .wide_for_trace (128'h1234_5678_aaaa_bbbb_cccc_dddd), .wide_for_trace_2 (_guard6 + 128'h1234_5678_aaaa_bbbb_cccc_dddd), /*AUTOINST*/ // Outputs .o_seq_d1r (o_seq_d1r), .o_com (o_com), // Inputs .clk (clk), .i_seq (i_seq), .i_com (i_com)); // surefire lint_off STMINI initial _mode = 0; always @ (posedge fastclk) begin if (_mode==1) begin if (o_com !== ~i_com) $stop; if (o2_comhigh !== {~i_com,i_com}) $stop; end end always @ (posedge clk) begin //$write("[%0t] t_inst: MODE = %0x NA=%x MA=%x DA=%x\n", $time, _mode, // {na,nb,nc,nd,ne}, {ma,mb,mc,md,me}, {da,db,dc,dd,de}); $write("[%0t] t_inst: MODE = %0x IS=%x OS=%x\n", $time, _mode, i_seq, o_seq_d1r); if (_mode==0) begin $write("[%0t] t_inst: Running\n", $time); _mode<=1; {na,nb,nc,nd,ne} <= 5'b10110; {wa,wb,wc,wd,we} <= {8'ha, 8'hb, 8'hc, 8'hd, 8'he}; {sa,sb,sc,sd} <= {6'hf, 5'h3, 30'h12345, 32'h0abc_abcd, 32'h7654_3210}; // i_seq <= 1'b1; i_com <= 1'b1; end else if (_mode==1) begin _mode<=2; if ({ma,mb,mc,md,me} !== 5'b10110) $stop; if ({qa,qb,qc,qd,qe} !== {8'ha,8'hb,8'hc,8'hd,8'he}) $stop; if ({sa,sb,sc,sd} !== {6'hf, 5'h3, 30'h12345, 32'h0abc_abcd, 32'h7654_3210}) $stop; end else if (_mode==2) begin _mode<=3; if ({da,db,dc,dd,de} !== 5'b10110) $stop; if (o_seq_d1r !== ~i_seq) $stop; // $write("*-* All Finished *-*\n"); $finish; end if (|{_guard1,_guard2,_guard3,_guard4,_guard5,_guard6}) begin $write("Guard error %x %x %x %x %x\n",_guard1,_guard2,_guard3,_guard4,_guard5); $stop; end end // surefire lint_off UDDSDN wire _unused_ok = |{1'b1, r_wide0, r_wide1,r_wide2,r_wide3,r_wide}; endmodule verilator-5.042/test_regress/t/t_gate_basic.v0000644000542200017500000000561615101701376021671 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg [31:0] a; reg [31:0] b; wire [2:0] bf; buf BF0 (bf[0], a[0]), BF1 (bf[1], a[1]), BF2 (bf[2], a[2]); // verilator lint_off IMPLICIT not #(0.108) NT0 (nt0, a[0]); and #1 AN0 (an0, a[0], b[0]); nand #(2,3) ND0 (nd0, a[0], b[0], b[1]); or OR0 (or0, a[0], b[0]); nor NR0 (nr0, a[0], b[0], b[2]); xor (xo0, a[0], b[0]); xnor (xn0, a[0], b[0], b[2]); // verilator lint_on IMPLICIT wire [2:0] bfm; buf BFM (bfm[0], bfm[1], bfm[2], a[0]); wire [2:0] ntm; not NTM (ntm[0], ntm[1], ntm[2], a[0]); parameter BITS=32; wire [BITS-1:0] ba; buf BARRAY [BITS-1:0] (ba, a); `ifdef verilator specparam RAW_SP = 1; specify endspecify specify specparam CDS_LIBNAME = "foobar"; (nt0 *> nt0) = (0, 0); endspecify specify // delay parameters specparam a$A1$Y = 1.0, b$A0$Z = 1.0; // path delays (A1 *> Q) = (a$A1$Y, a$A1$Y); (A0 *> Q) = (b$A0$Y, a$A0$Z); if (C1) (IN => OUT) = (1,1); ifnone (IN => OUT) = (2,2); showcancelled Q; noshowcancelled Q; pulsestyle_ondetect Q; pulsestyle_onevent Q; // other unimplemented stuff $fullskew(); $hold(); $nochange(); $period(); $recovery(); $recrem(); $removal(); $setup(); $skew(); $timeskew(); $width(); endspecify `endif always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin a <= 32'h18f6b034; b <= 32'h834bf892; end if (cyc==2) begin a <= 32'h529ab56f; b <= 32'h7835a237; if (bf !== 3'b100) $stop; if (bfm != 3'b000) $stop; if (ntm != 3'b111) $stop; if (nt0 !== 1'b1) $stop; if (an0 !== 1'b0) $stop; if (nd0 !== 1'b1) $stop; if (or0 !== 1'b0) $stop; if (nr0 !== 1'b1) $stop; if (xo0 !== 1'b0) $stop; if (xn0 !== 1'b1) $stop; if (ba != 32'h18f6b034) $stop; end if (cyc==3) begin if (bf !== 3'b111) $stop; if (bfm != 3'b111) $stop; if (ntm != 3'b000) $stop; if (nt0 !== 1'b0) $stop; if (an0 !== 1'b1) $stop; if (nd0 !== 1'b0) $stop; if (or0 !== 1'b1) $stop; if (nr0 !== 1'b0) $stop; if (xo0 !== 1'b0) $stop; if (xn0 !== 1'b0) $stop; end if (cyc==4) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.042/test_regress/t/t_cover_expr_queue_class.py0000755000542200017500000000100015101701376024522 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--coverage-expr']) test.execute() test.passes() verilator-5.042/test_regress/t/t_select_bound2.v0000644000542200017500000000474015101701376022335 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // bug823 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [6:0] in = crc[6:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [3:0] mask; // From test of Test.v wire [3:0] out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out (out[3:0]), .mask (mask[3:0]), // Inputs .clk (clk), .in (in[6:0])); // Aggregate outputs into a single result vector wire [63:0] result = {60'h0, out & mask}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x out=%b mask=%b\n", $time, cyc, crc, out, mask); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc<10) begin sum <= '0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h4e9d3a74e9d3f656 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs out, mask, // Inputs clk, in ); input clk; input [6:0] in; // Note much wider than any index output reg [3:0] out; output reg [3:0] mask; localparam [15:5] P = 11'h1ac; always @(posedge clk) begin // verilator lint_off WIDTH out <= P[15 + in -: 5]; // verilator lint_on WIDTH mask[3] <= ((15 + in - 5) < 12); mask[2] <= ((15 + in - 5) < 13); mask[1] <= ((15 + in - 5) < 14); mask[0] <= ((15 + in - 5) < 15); end endmodule verilator-5.042/test_regress/t/t_flag_make_cmake_sc.py0000755000542200017500000000113015101701376023514 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # This test tests CMake support for SystemC import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_make_gmake=False, verilator_make_cmake=True, verilator_flags2=["-sc"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_initial_dlyass_bad.py0000755000542200017500000000104115101701376023600 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.top_filename = "t/t_initial_dlyass.v" test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_packed_concat.v0000644000542200017500000000124115101701376022354 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Driss Hafdi // SPDX-License-Identifier: CC0-1.0 module t; typedef logic [15:0] count_t; typedef bit [31:0] bit_int_t; // bug1627 localparam bit_int_t [1:0] count_bits = {2{$bits(count_t)}}; localparam bit_int_t [1:0] count_bitsc = {$bits(count_t), $bits(count_t)}; initial begin if (count_bits[0] != 16) $stop; if (count_bits[1] != 16) $stop; if (count_bitsc[0] != 16) $stop; if (count_bitsc[1] != 16) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_interface_generic_modport_function.v0000644000542200017500000000121415101701376026703 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 interface inf; int v; function int get(); return v; endfunction modport mp( import get ); endinterface interface inf2; int k; endinterface module GenericModule (interface.mp a); initial begin #1; if (a.get() != 4) $stop; end endmodule module t; inf inf_inst(); GenericModule genericModule (inf_inst); initial begin inf_inst.v = 4; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_clk_gen.v0000644000542200017500000000503315101701376021203 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg gendlyclk_r; reg [31:0] gendlydata_r; reg [31:0] dlydata_gr; reg genblkclk; reg [31:0] genblkdata; reg [31:0] blkdata_gr; wire [31:0] constwire = 32'h11; reg [31:0] initwire; integer i; initial begin for (i=0; i<10000; i=i+1) begin initwire = 32'h2200; end end wire [31:0] either = gendlydata_r | dlydata_gr | blkdata_gr | initwire | constwire; wire [31:0] either_unused = gendlydata_r | dlydata_gr | blkdata_gr | initwire | constwire; always @ (posedge clk) begin gendlydata_r <= 32'h0011_0000; gendlyclk_r <= 0; // surefire lint_off SEQASS genblkclk = 0; genblkdata = 0; if (cyc!=0) begin cyc <= cyc + 1; if (cyc==2) begin gendlyclk_r <= 1; gendlydata_r <= 32'h00540000; genblkclk = 1; genblkdata = 32'hace; $write("[%0t] Send pulse\n", $time); end if (cyc==3) begin genblkdata = 32'hdce; gendlydata_r <= 32'h00ff0000; if (either != 32'h87542211) $stop; $write("*-* All Finished *-*\n"); $finish; end end // surefire lint_on SEQASS end always @ (posedge gendlyclk_r) begin if ($time>0) begin // Hack, don't split the block $write("[%0t] Got gendlyclk_r, d=%x b=%x\n", $time, gendlydata_r, genblkdata); dlydata_gr <= 32'h80000000; // Delayed activity list will already be completed for gendlydata // because genclk is from a delayed assignment. // Thus we get the NEW not old value of gendlydata_r if (gendlydata_r != 32'h00540000) $stop; if (genblkdata != 32'hace) $stop; end end always @ (posedge genblkclk) begin if ($time>0) begin // Hack, don't split the block $write("[%0t] Got genblkclk, d=%x b=%x\n", $time, gendlydata_r, genblkdata); blkdata_gr <= 32'h07000000; // Clock from non-delayed assignment, we get old value of gendlydata_r `ifdef verilator `else // V3.2 races... technically legal if (gendlydata_r != 32'h00110000) $stop; `endif if (genblkdata != 32'hace) $stop; end end endmodule verilator-5.042/test_regress/t/t_sys_writemem_b.gold3.mem0000644000542200017500000000542015101701376024151 0ustar mahmoudyfreeshell00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 01000000000001000011011101100101010000110010000100100111011001010100001100100001000101110110010101000011001000010000011101100101010000110010000110101011110011011110111100010000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 01000000000010100011011101100101010000110010000100100111011001010100001100100001000101110110010101000011001000010000011101100101010000110010000110101011110011011110111100010001 01000000000010110011011101100101010000110010000100100111011001010100001100100001000101110110010101000011001000010000011101100101010000110010000110101011110011011110111100010010 01000000000011000011011101100101010000110010000100100111011001010100001100100001000101110110010101000011001000010000011101100101010000110010000110101011110011011110111100010011 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 verilator-5.042/test_regress/t/t_param_array7.py0000755000542200017500000000073415101701376022357 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_opt_table_display.v0000644000542200017500000000174515101701376023305 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs test, // Inputs clk ); input clk; output reg [5:0] test; parameter STATE1 = 6'b000001; parameter STATE2 = 6'b000010; parameter STATE3 = 6'b000100; parameter STATE4 = 6'b001000; parameter STATE5 = 6'b010000; parameter STATE6 = 6'b100000; always @(posedge clk) begin $display("Clocked"); case (test) STATE1: test <= STATE2; STATE2: test <= STATE3; STATE3: test <= STATE4; STATE4: test <= STATE5; STATE5: test <= STATE6; default: test <= STATE1; endcase end int cyc; always @(posedge clk) begin cyc <= cyc + 1; if (cyc == 10) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_array_pattern_bad2.v0000644000542200017500000000076015101701376023346 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // bug1364 module t (/*AUTOARG*/ // Inputs clk, res ); input clk; input res; typedef struct packed { logic [3:0] port_num; } info_t; info_t myinfo; always_comb myinfo = '{default: '0, default: '1}; // Bad endmodule verilator-5.042/test_regress/t/t_flag_woff_bad.out0000644000542200017500000000023715101701376022704 0ustar mahmoudyfreeshell%Error: Unknown warning specified: -Wno-NOSUCHERRORASTHIS ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. verilator-5.042/test_regress/t/t_inst_long_bad.out0000644000542200017500000000166215101701376022751 0ustar mahmoudyfreeshell%Error-MODMISSING: t/t_inst_long_bad.v:9:3: Cannot find file containing module: 'long_long_long_long_long_long___Vhsh1JZCXQVBM1QiASYlLmgTuAXYyUr7VAbJYwVHfiAD' 9 | long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_ inst (); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ... For error description see https://verilator.org/warn/MODMISSING?v=latest ... Note: Name is longer than 127 characters; automatic file lookup may have failed due to OS filename length limits. ... Suggest putting filename with this module/package onto command line instead. %Error: Exiting due to verilator-5.042/test_regress/t/t_sys_readmem_q.mem0000644000542200017500000000063315101701376022743 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test data file // // Copyright 2006 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 @4 dcba9876540004 @a dcba987654000a dcba987654000b dcba987654000c verilator-5.042/test_regress/t/t_dpi_name_bad.out0000644000542200017500000000103415101701376022522 0ustar mahmoudyfreeshell%Error: t/t_dpi_name_bad.v:11:32: DPI function has illegal characters in C identifier name: badly.named 11 | import "DPI-C" function int \badly.named (int i); | ^~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_dpi_name_bad.v:14:17: DPI function has illegal characters in C identifier name: badly.expt 14 | function int \badly.expt ; return 0; endfunction | ^~~~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_split_var_1_bad.out0000644000542200017500000001575115101701376023204 0ustar mahmoudyfreeshell%Warning-SPLITVAR: t/t_split_var_1_bad.v:7:13: 'should_show_warning_global0' has split_var metacomment, but will not be split because it is not declared in a module. 7 | logic [7:0] should_show_warning_global0 /*verilator split_var*/ ; | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ ... For warning description see https://verilator.org/warn/SPLITVAR?v=latest ... Use "/* verilator lint_off SPLITVAR */" and lint_on around source to disable this message. %Warning-SPLITVAR: t/t_split_var_1_bad.v:8:13: 'should_show_warning_global1' has split_var metacomment, but will not be split because it is not declared in a module. 8 | logic [7:0] should_show_warning_global1 [1:0] /*verilator split_var*/ ; | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ %Warning-SPLITVAR: t/t_split_var_1_bad.v:11:16: 'should_show_warning_ifs0' has split_var metacomment, but will not be split because it is not declared in a module. 11 | logic [7:0] should_show_warning_ifs0 /*verilator split_var*/ ; | ^~~~~~~~~~~~~~~~~~~~~~~~ %Warning-SPLITVAR: t/t_split_var_1_bad.v:12:16: 'should_show_warning_ifs1' has split_var metacomment, but will not be split because it is not declared in a module. 12 | logic [7:0] should_show_warning_ifs1 [1:0] /*verilator split_var*/ ; | ^~~~~~~~~~~~~~~~~~~~~~~~ %Warning-SPLITVAR: t/t_split_var_1_bad.v:40:14: 'cannot_split1' has split_var metacomment but will not be split because it is accessed from another module via a dot. 40 | i_sub0.cannot_split1[0] = 0; | ^~~~~~~~~~~~~ %Warning-SELRANGE: t/t_split_var_1_bad.v:90:33: Selection index out of range: 13 outside 12:10 : ... note: In instance 't.i_sub3' 90 | assign outwires[12] = inwires[13]; | ^ ... For warning description see https://verilator.org/warn/SELRANGE?v=latest ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Warning-WIDTHTRUNC: t/t_split_var_1_bad.v:41:31: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's FUNCREF 'bad_func' generates 32 bits. : ... note: In instance 't' 41 | i_sub0.cannot_split1[1] = bad_func(addr, rd_data0); | ^ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: t/t_split_var_1_bad.v:79:16: Illegal assignment of constant to unpacked array : ... note: In instance 't.i_sub2' 79 | assign b = a[0]; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Warning-SPLITVAR: t/t_split_var_1_bad.v:56:31: 'cannot_split0' has split_var metacomment but will not be split because index cannot be determined statically. : ... note: In instance 't.i_sub0' 56 | rd_data = cannot_split0[addr]; | ^~~~ %Warning-SPLITVAR: t/t_split_var_1_bad.v:90:34: 'inwires' has split_var metacomment but will not be split because index is out of range. : ... note: In instance 't.i_sub3' 90 | assign outwires[12] = inwires[13]; | ^~ %Warning-SPLITVAR: t/t_split_var_1_bad.v:17:9: 'should_show_warning0' has split_var metacomment but will not be split because it is not an aggregate type of bit nor logic. : ... note: In instance 't' 17 | real should_show_warning0 /*verilator split_var*/ ; | ^~~~~~~~~~~~~~~~~~~~ %Warning-SPLITVAR: t/t_split_var_1_bad.v:18:11: 'should_show_warning1' has split_var metacomment but will not be split because it is not an aggregate type of bit nor logic. : ... note: In instance 't' 18 | string should_show_warning1 /*verilator split_var*/ ; | ^~~~~~~~~~~~~~~~~~~~ %Warning-SPLITVAR: t/t_split_var_1_bad.v:19:11: 'should_show_warning2' has split_var metacomment but will not be split because its bitwidth is 1. : ... note: In instance 't' 19 | wire should_show_warning2 /*verilator split_var*/ ; | ^~~~~~~~~~~~~~~~~~~~ %Warning-SPLITVAR: t/t_split_var_1_bad.v:23:16: 'public_signal' has split_var metacomment but will not be split because it is public. : ... note: In instance 't' 23 | logic [1:0] public_signal /*verilator public*/ /*verilator split_var*/ ; | ^~~~~~~~~~~~~ %Warning-SPLITVAR: t/t_split_var_1_bad.v:31:44: 'inout_port' has split_var metacomment but will not be split because it is an inout port. : ... note: In instance 't' 31 | function int bad_func(inout logic [3:0] inout_port /*verilator split_var*/ , | ^~~~~~~~~~ %Warning-SPLITVAR: t/t_split_var_1_bad.v:32:42: 'ref_port' has split_var metacomment but will not be split because it is a ref argument. : ... note: In instance 't' 32 | ref logic [7:0] ref_port /*verilator split_var*/ ); | ^~~~~~~~ %Warning-SPLITVAR: t/t_split_var_1_bad.v:37:19: 'loop_idx' has split_var metacomment but will not be split because it is used as a loop variable. : ... note: In instance 't' 37 | logic [7:0] loop_idx /*verilator split_var*/ ; | ^~~~~~~~ %Warning-SPLITVAR: t/t_split_var_1_bad.v:62:11: 'cannot_split_genvar' has split_var metacomment but will not be split because it is not an aggregate type of bit nor logic. : ... note: In instance 't.i_sub1' 62 | genvar cannot_split_genvar /*verilator split_var*/ ; | ^~~~~~~~~~~~~~~~~~~ %Warning-SPLITVAR: t/t_split_var_1_bad.v:65:72: 'cannot_split' has split_var metacomment but will not be split because its bit range cannot be determined statically. : ... note: In instance 't.i_sub1' 65 | static logic [8:0] rd_tmp /*verilator split_var*/ = cannot_split[addr]; | ^ %Warning-SPLITVAR: t/t_split_var_1_bad.v:66:23: 'rd_tmp' has split_var metacomment but will not be split because its bit range cannot be determined statically. : ... note: In instance 't.i_sub1' 66 | rd_data = rd_tmp[{3'b0, addr[0]}+:8]; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_inst_prepost.v0000644000542200017500000000111115101701376022323 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; sub #(10,11,12,13) sub (); endmodule module sub (); parameter A = 0; parameter B = 1; ip ip(); parameter C = 2; parameter D = 3; initial begin if (A!=10) $stop; if (B!=11) $stop; if (C!=12) $stop; if (D!=13) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module ip; endmodule verilator-5.042/test_regress/t/t_dpi_instr_count_large.py0000755000542200017500000000140015101701376024336 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vltmt') test.clean_objs() test.compile( v_flags2=["t/t_dpi_instr_count_large.cpp"], verilator_flags2=[ "--instr-count-dpi 999999999", # Force UNOPTTHREADS error to cause Contraction limit increase beyond UINT32 "--threads-max-mtasks 1", "-Wno-UNOPTTHREADS" ], threads=2) test.execute() test.passes() verilator-5.042/test_regress/t/t_struct_contents_bad.v0000644000542200017500000000154715101701376023656 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; typedef enum logic [1:0] { ZERO, ONE } enum_t; typedef struct { bit a; } struct_unpacked_t; typedef union { bit a; } union_unpacked_t; class Cls; bit a; endclass // IEEE 1800-2023 7.2.1 typedef struct packed { real r; // BAD // verilator lint_off SHORTREAL shortreal sr; // BAD realtime rt; // BAD chandle ch; // BAD string s; // BAD event e; // BAD struct_unpacked_t sp; // BAD union_unpacked_t up; // BAD int uarray[2]; // BAD Cls c; // BAd } illegal_t; illegal_t s; initial begin $stop; end endmodule verilator-5.042/test_regress/t/t_inst_implicit.py0000755000542200017500000000073415101701376022641 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_debug_exit_parse.py0000755000542200017500000000111615101701376023276 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t_EXAMPLE.v" test.lint(verilator_flags2=["--debug-exit-parse"]) test.file_grep(test.compile_log_filename, r'--debug-exit-parse') test.passes() verilator-5.042/test_regress/t/t_stream5.py0000755000542200017500000000077115101701376021353 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_param_array2.v0000644000542200017500000000104615101701376022161 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; localparam int C[4] = '{5, 6, 7, 8}; a #(.P(C)) i_a (); endmodule module a #( parameter int P[4] = '{1, 2, 3, 4} ); initial begin if (P[0] != 5) $stop; if (P[1] != 6) $stop; if (P[2] != 7) $stop; if (P[3] != 8) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_math_pow7.py0000755000542200017500000000106015101701376021670 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_math_cv_bitop.py0000755000542200017500000000103515101701376022603 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dist_header_cc.py0000755000542200017500000000127015101701376022706 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') if not os.path.exists(test.root + "/.git"): test.skip("Not in a git repository") test.run(cmd=[ "cd " + test.root + "/src/obj_dbg && " + os.environ['MAKE'] + " -j 4 -k -f ../Makefile_obj VL_NOOPT=1 header_cc" ], check_finished=False) test.passes() verilator-5.042/test_regress/t/t_param_type2.v0000644000542200017500000000117415101701376022026 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Iztok Jeras. // SPDX-License-Identifier: CC0-1.0 package tt_pkg; typedef enum logic [1:0] {L0, L1, L2, L3} test_t; endpackage module t (/*AUTOARG*/ // Outputs ob ); output [1:0] ob; import tt_pkg::*; test_t a; test_t b; assign a = L0; assign ob = b; tt_buf #(.T_t(test_t)) u_test (.i(a), .o(b)); endmodule module tt_buf #( parameter type T_t = logic [0:0] ) ( input T_t i, output T_t o ); assign o = i; endmodule verilator-5.042/test_regress/t/t_interface_generic_task_bad.py0000755000542200017500000000102515101701376025250 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=['--timing'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_trace_fst.out0000644000542200017500000004347615101701376022132 0ustar mahmoudyfreeshell$date Tue Oct 21 18:20:37 2025 $end $version fstWriter $end $timescale 1ps $end $scope module top $end $var wire 1 ! clk $end $var wire 5 " state [4:0] $end $var wire 1 # fst_inout $end $scope module t $end $var wire 1 ! clk $end $var int 32 $ cyc [31:0] $end $var logic 1 % rstn $end $var wire 5 " state [4:0] $end $var real_parameter 64 & fst_gparam_real $end $var real_parameter 64 ' fst_lparam_real $end $var real 64 & fst_real $end $var integer 32 ( fst_integer [31:0] $end $var bit 1 ) fst_bit $end $var logic 1 * fst_logic $end $var int 32 + fst_int [31:0] $end $var shortint 16 , fst_shortint [15:0] $end $var longint 64 - fst_longint [63:0] $end $var byte 8 . fst_byte [7:0] $end $var time 64 / fst_time [63:0] $end $var parameter 32 0 fst_parameter [31:0] $end $var parameter 32 1 fst_lparam [31:0] $end $var supply0 1 2 fst_supply0 $end $var supply1 1 3 fst_supply1 $end $var tri0 1 2 fst_tri0 $end $var tri1 1 3 fst_tri1 $end $var tri 1 4 fst_tri $end $var triand 1 5 fst_triand $end $var trior 1 6 fst_trior $end $var triand 1 7 fst_wand $end $var trior 1 8 fst_wor $end $var wire 1 9 fst_wire $end $var wire 1 : fst_uwire $end $var wire 1 # fst_inout $end $scope module test $end $var wire 1 ! clk $end $var wire 1 % rstn $end $var wire 5 " state [4:0] $end $var logic 5 ; state_w [4:0] $end $var logic 5 < state_array[0] [4:0] $end $var logic 5 = state_array[1] [4:0] $end $var logic 5 > state_array[2] [4:0] $end $scope module unnamedblk1 $end $var int 32 ? i [31:0] $end $upscope $end $scope module unnamedblk2 $end $var int 32 @ i [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b00000000000000000000000000000000 @ b00000000000000000000000000000000 ? b00000 > b00000 = b00000 < b00000 ; 0: 09 08 07 06 05 04 13 02 b00000000000000000000000111001000 1 b00000000000000000000000001111011 0 b0000000000000000000000000000000000000000000000000000000000000000 / b00000000 . b0000000000000000000000000000000000000000000000000000000000000000 - b0000000000000000 , b00000000000000000000000000000000 + 0* 0) b00000000000000000000000000000000 ( r4.56 ' r1.23 & 0% b00000000000000000000000000000000 $ 0# b00000 " 0! $end #10 1! b00001 " b00000000000000000000000000000001 $ b0000000000000000000000000000000000000000000000000000000000001010 / b10100 ; b00001 < b00001 = b00001 > b00000000000000000000000000000011 ? #15 0! #20 1! b0000000000000000000000000000000000000000000000000000000000010100 / b00000000000000000000000000000010 $ #25 0! #30 1! b00000000000000000000000000000011 $ b0000000000000000000000000000000000000000000000000000000000011110 / #35 0! #40 1! b0000000000000000000000000000000000000000000000000000000000101000 / b00000000000000000000000000000100 $ #45 0! #50 1! b00000000000000000000000000000101 $ b0000000000000000000000000000000000000000000000000000000000110010 / #55 0! #60 1! b0000000000000000000000000000000000000000000000000000000000111100 / b00000000000000000000000000000110 $ #65 0! #70 1! b00000000000000000000000000000111 $ b0000000000000000000000000000000000000000000000000000000001000110 / #75 0! #80 1! b0000000000000000000000000000000000000000000000000000000001010000 / b00000000000000000000000000001000 $ #85 0! #90 1! b00000000000000000000000000001001 $ b0000000000000000000000000000000000000000000000000000000001011010 / #95 0! #100 1! b0000000000000000000000000000000000000000000000000000000001100100 / b00000000000000000000000000001010 $ #105 0! #110 1! b00000000000000000000000000001011 $ b0000000000000000000000000000000000000000000000000000000001101110 / 1% #115 0! #120 1! b0000000000000000000000000000000000000000000000000000000001111000 / b00000000000000000000000000001100 $ b10100 > b01010 ; b00000000000000000000000000000010 @ #125 0! #130 1! b00101 ; b01010 > b00000000000000000000000000001101 $ b0000000000000000000000000000000000000000000000000000000010000010 / b10100 = #135 0! #140 1! b01010 = b0000000000000000000000000000000000000000000000000000000010001100 / b00000000000000000000000000001110 $ b00101 > b10110 ; b10100 < b10100 " #145 0! #150 1! b01010 " b01010 < b01011 ; b10110 > b00000000000000000000000000001111 $ b0000000000000000000000000000000000000000000000000000000010010110 / b00101 = #155 0! #160 1! b10110 = b0000000000000000000000000000000000000000000000000000000010100000 / b00000000000000000000000000010000 $ b01011 > b10001 ; b00101 < b00101 " #165 0! #170 1! b10110 " b10110 < b11100 ; b10001 > b00000000000000000000000000010001 $ b0000000000000000000000000000000000000000000000000000000010101010 / b01011 = #175 0! #180 1! b10001 = b0000000000000000000000000000000000000000000000000000000010110100 / b00000000000000000000000000010010 $ b11100 > b01110 ; b01011 < b01011 " #185 0! #190 1! b10001 " b10001 < b00111 ; b01110 > b00000000000000000000000000010011 $ b0000000000000000000000000000000000000000000000000000000010111110 / b11100 = #195 0! #200 1! b01110 = b0000000000000000000000000000000000000000000000000000000011001000 / b00000000000000000000000000010100 $ b00111 > b10111 ; b11100 < b11100 " #205 0! #210 1! b01110 " b01110 < b11111 ; b10111 > b00000000000000000000000000010101 $ b0000000000000000000000000000000000000000000000000000000011010010 / b00111 = #215 0! #220 1! b10111 = b0000000000000000000000000000000000000000000000000000000011011100 / b00000000000000000000000000010110 $ b11111 > b11011 ; b00111 < b00111 " #225 0! #230 1! b10111 " b10111 < b11001 ; b11011 > b00000000000000000000000000010111 $ b0000000000000000000000000000000000000000000000000000000011100110 / b11111 = #235 0! #240 1! b11011 = b0000000000000000000000000000000000000000000000000000000011110000 / b00000000000000000000000000011000 $ b11001 > b11000 ; b11111 < b11111 " #245 0! #250 1! b11011 " b11011 < b01100 ; b11000 > b00000000000000000000000000011001 $ b0000000000000000000000000000000000000000000000000000000011111010 / b11001 = #255 0! #260 1! b11000 = b0000000000000000000000000000000000000000000000000000000100000100 / b00000000000000000000000000011010 $ b01100 > b00110 ; b11001 < b11001 " #265 0! #270 1! b11000 " b11000 < b00011 ; b00110 > b00000000000000000000000000011011 $ b0000000000000000000000000000000000000000000000000000000100001110 / b01100 = #275 0! #280 1! b00110 = b0000000000000000000000000000000000000000000000000000000100011000 / b00000000000000000000000000011100 $ b00011 > b10101 ; b01100 < b01100 " #285 0! #290 1! b00110 " b00110 < b11110 ; b10101 > b00000000000000000000000000011101 $ b0000000000000000000000000000000000000000000000000000000100100010 / b00011 = #295 0! #300 1! b10101 = b0000000000000000000000000000000000000000000000000000000100101100 / b00000000000000000000000000011110 $ b11110 > b01111 ; b00011 < b00011 " #305 0! #310 1! b10101 " b10101 < b10011 ; b01111 > b00000000000000000000000000011111 $ b0000000000000000000000000000000000000000000000000000000100110110 / b11110 = #315 0! #320 1! b01111 = b0000000000000000000000000000000000000000000000000000000101000000 / b00000000000000000000000000100000 $ b10011 > b11101 ; b11110 < b11110 " #325 0! #330 1! b01111 " b01111 < b11010 ; b11101 > b00000000000000000000000000100001 $ b0000000000000000000000000000000000000000000000000000000101001010 / b10011 = #335 0! #340 1! b11101 = b0000000000000000000000000000000000000000000000000000000101010100 / b00000000000000000000000000100010 $ b11010 > b01101 ; b10011 < b10011 " #345 0! #350 1! b11101 " b11101 < b10010 ; b01101 > b00000000000000000000000000100011 $ b0000000000000000000000000000000000000000000000000000000101011110 / b11010 = #355 0! #360 1! b01101 = b0000000000000000000000000000000000000000000000000000000101101000 / b00000000000000000000000000100100 $ b10010 > b01001 ; b11010 < b11010 " #365 0! #370 1! b01101 " b01101 < b10000 ; b01001 > b00000000000000000000000000100101 $ b0000000000000000000000000000000000000000000000000000000101110010 / b10010 = #375 0! #380 1! b01001 = b0000000000000000000000000000000000000000000000000000000101111100 / b00000000000000000000000000100110 $ b10000 > b01000 ; b10010 < b10010 " #385 0! #390 1! b01001 " b01001 < b00100 ; b01000 > b00000000000000000000000000100111 $ b0000000000000000000000000000000000000000000000000000000110000110 / b10000 = #395 0! #400 1! b01000 = b0000000000000000000000000000000000000000000000000000000110010000 / b00000000000000000000000000101000 $ b00100 > b00010 ; b10000 < b10000 " #405 0! #410 1! b01000 " b01000 < b00001 ; b00010 > b00000000000000000000000000101001 $ b0000000000000000000000000000000000000000000000000000000110011010 / b00100 = #415 0! #420 1! b00010 = b0000000000000000000000000000000000000000000000000000000110100100 / b00000000000000000000000000101010 $ b00001 > b10100 ; b00100 < b00100 " #425 0! #430 1! b00010 " b00010 < b01010 ; b10100 > b00000000000000000000000000101011 $ b0000000000000000000000000000000000000000000000000000000110101110 / b00001 = #435 0! #440 1! b10100 = b0000000000000000000000000000000000000000000000000000000110111000 / b00000000000000000000000000101100 $ b01010 > b00101 ; b00001 < b00001 " #445 0! #450 1! b10100 " b10100 < b10110 ; b00101 > b00000000000000000000000000101101 $ b0000000000000000000000000000000000000000000000000000000111000010 / b01010 = #455 0! #460 1! b00101 = b0000000000000000000000000000000000000000000000000000000111001100 / b00000000000000000000000000101110 $ b10110 > b01011 ; b01010 < b01010 " #465 0! #470 1! b00101 " b00101 < b10001 ; b01011 > b00000000000000000000000000101111 $ b0000000000000000000000000000000000000000000000000000000111010110 / b10110 = #475 0! #480 1! b01011 = b0000000000000000000000000000000000000000000000000000000111100000 / b00000000000000000000000000110000 $ b10001 > b11100 ; b10110 < b10110 " #485 0! #490 1! b01011 " b01011 < b01110 ; b11100 > b00000000000000000000000000110001 $ b0000000000000000000000000000000000000000000000000000000111101010 / b10001 = #495 0! #500 1! b11100 = b0000000000000000000000000000000000000000000000000000000111110100 / b00000000000000000000000000110010 $ b01110 > b00111 ; b10001 < b10001 " #505 0! #510 1! b11100 " b11100 < b10111 ; b00111 > b00000000000000000000000000110011 $ b0000000000000000000000000000000000000000000000000000000111111110 / b01110 = #515 0! #520 1! b00111 = b0000000000000000000000000000000000000000000000000000001000001000 / b00000000000000000000000000110100 $ b10111 > b11111 ; b01110 < b01110 " #525 0! #530 1! b00111 " b00111 < b11011 ; b11111 > b00000000000000000000000000110101 $ b0000000000000000000000000000000000000000000000000000001000010010 / b10111 = #535 0! #540 1! b11111 = b0000000000000000000000000000000000000000000000000000001000011100 / b00000000000000000000000000110110 $ b11011 > b11001 ; b10111 < b10111 " #545 0! #550 1! b11111 " b11111 < b11000 ; b11001 > b00000000000000000000000000110111 $ b0000000000000000000000000000000000000000000000000000001000100110 / b11011 = #555 0! #560 1! b11001 = b0000000000000000000000000000000000000000000000000000001000110000 / b00000000000000000000000000111000 $ b11000 > b01100 ; b11011 < b11011 " #565 0! #570 1! b11001 " b11001 < b00110 ; b01100 > b00000000000000000000000000111001 $ b0000000000000000000000000000000000000000000000000000001000111010 / b11000 = #575 0! #580 1! b01100 = b0000000000000000000000000000000000000000000000000000001001000100 / b00000000000000000000000000111010 $ b00110 > b00011 ; b11000 < b11000 " #585 0! #590 1! b01100 " b01100 < b10101 ; b00011 > b00000000000000000000000000111011 $ b0000000000000000000000000000000000000000000000000000001001001110 / b00110 = #595 0! #600 1! b00011 = b0000000000000000000000000000000000000000000000000000001001011000 / b00000000000000000000000000111100 $ b10101 > b11110 ; b00110 < b00110 " #605 0! #610 1! b00011 " b00011 < b01111 ; b11110 > b00000000000000000000000000111101 $ b0000000000000000000000000000000000000000000000000000001001100010 / b10101 = #615 0! #620 1! b11110 = b0000000000000000000000000000000000000000000000000000001001101100 / b00000000000000000000000000111110 $ b01111 > b10011 ; b10101 < b10101 " #625 0! #630 1! b11110 " b11110 < b11101 ; b10011 > b00000000000000000000000000111111 $ b0000000000000000000000000000000000000000000000000000001001110110 / b01111 = #635 0! #640 1! b10011 = b0000000000000000000000000000000000000000000000000000001010000000 / b00000000000000000000000001000000 $ b11101 > b11010 ; b01111 < b01111 " #645 0! #650 1! b10011 " b10011 < b01101 ; b11010 > b00000000000000000000000001000001 $ b0000000000000000000000000000000000000000000000000000001010001010 / b11101 = #655 0! #660 1! b11010 = b0000000000000000000000000000000000000000000000000000001010010100 / b00000000000000000000000001000010 $ b01101 > b10010 ; b11101 < b11101 " #665 0! #670 1! b11010 " b11010 < b01001 ; b10010 > b00000000000000000000000001000011 $ b0000000000000000000000000000000000000000000000000000001010011110 / b01101 = #675 0! #680 1! b10010 = b0000000000000000000000000000000000000000000000000000001010101000 / b00000000000000000000000001000100 $ b01001 > b10000 ; b01101 < b01101 " #685 0! #690 1! b10010 " b10010 < b01000 ; b10000 > b00000000000000000000000001000101 $ b0000000000000000000000000000000000000000000000000000001010110010 / b01001 = #695 0! #700 1! b10000 = b0000000000000000000000000000000000000000000000000000001010111100 / b00000000000000000000000001000110 $ b01000 > b00100 ; b01001 < b01001 " #705 0! #710 1! b10000 " b10000 < b00010 ; b00100 > b00000000000000000000000001000111 $ b0000000000000000000000000000000000000000000000000000001011000110 / b01000 = #715 0! #720 1! b00100 = b0000000000000000000000000000000000000000000000000000001011010000 / b00000000000000000000000001001000 $ b00010 > b00001 ; b01000 < b01000 " #725 0! #730 1! b00100 " b00100 < b10100 ; b00001 > b00000000000000000000000001001001 $ b0000000000000000000000000000000000000000000000000000001011011010 / b00010 = #735 0! #740 1! b00001 = b0000000000000000000000000000000000000000000000000000001011100100 / b00000000000000000000000001001010 $ b10100 > b01010 ; b00010 < b00010 " #745 0! #750 1! b00001 " b00001 < b00101 ; b01010 > b00000000000000000000000001001011 $ b0000000000000000000000000000000000000000000000000000001011101110 / b10100 = #755 0! #760 1! b01010 = b0000000000000000000000000000000000000000000000000000001011111000 / b00000000000000000000000001001100 $ b00101 > b10110 ; b10100 < b10100 " #765 0! #770 1! b01010 " b01010 < b01011 ; b10110 > b00000000000000000000000001001101 $ b0000000000000000000000000000000000000000000000000000001100000010 / b00101 = #775 0! #780 1! b10110 = b0000000000000000000000000000000000000000000000000000001100001100 / b00000000000000000000000001001110 $ b01011 > b10001 ; b00101 < b00101 " #785 0! #790 1! b10110 " b10110 < b11100 ; b10001 > b00000000000000000000000001001111 $ b0000000000000000000000000000000000000000000000000000001100010110 / b01011 = #795 0! #800 1! b10001 = b0000000000000000000000000000000000000000000000000000001100100000 / b00000000000000000000000001010000 $ b11100 > b01110 ; b01011 < b01011 " #805 0! #810 1! b10001 " b10001 < b00111 ; b01110 > b00000000000000000000000001010001 $ b0000000000000000000000000000000000000000000000000000001100101010 / b11100 = #815 0! #820 1! b01110 = b0000000000000000000000000000000000000000000000000000001100110100 / b00000000000000000000000001010010 $ b00111 > b10111 ; b11100 < b11100 " #825 0! #830 1! b01110 " b01110 < b11111 ; b10111 > b00000000000000000000000001010011 $ b0000000000000000000000000000000000000000000000000000001100111110 / b00111 = #835 0! #840 1! b10111 = b0000000000000000000000000000000000000000000000000000001101001000 / b00000000000000000000000001010100 $ b11111 > b11011 ; b00111 < b00111 " #845 0! #850 1! b10111 " b10111 < b11001 ; b11011 > b00000000000000000000000001010101 $ b0000000000000000000000000000000000000000000000000000001101010010 / b11111 = #855 0! #860 1! b11011 = b0000000000000000000000000000000000000000000000000000001101011100 / b00000000000000000000000001010110 $ b11001 > b11000 ; b11111 < b11111 " #865 0! #870 1! b11011 " b11011 < b01100 ; b11000 > b00000000000000000000000001010111 $ b0000000000000000000000000000000000000000000000000000001101100110 / b11001 = #875 0! #880 1! b11000 = b0000000000000000000000000000000000000000000000000000001101110000 / b00000000000000000000000001011000 $ b01100 > b00110 ; b11001 < b11001 " #885 0! #890 1! b11000 " b11000 < b00011 ; b00110 > b00000000000000000000000001011001 $ b0000000000000000000000000000000000000000000000000000001101111010 / b01100 = #895 0! #900 1! b00110 = b0000000000000000000000000000000000000000000000000000001110000100 / b00000000000000000000000001011010 $ b00011 > b10101 ; b01100 < b01100 " #905 0! #910 1! b00110 " b00110 < b11110 ; b10101 > b00000000000000000000000001011011 $ b0000000000000000000000000000000000000000000000000000001110001110 / b00011 = #915 0! #920 1! b10101 = b0000000000000000000000000000000000000000000000000000001110011000 / b00000000000000000000000001011100 $ b11110 > b01111 ; b00011 < b00011 " #925 0! #930 1! b10101 " b10101 < b10011 ; b01111 > b00000000000000000000000001011101 $ b0000000000000000000000000000000000000000000000000000001110100010 / b11110 = #935 0! #940 1! b01111 = b0000000000000000000000000000000000000000000000000000001110101100 / b00000000000000000000000001011110 $ b10011 > b11101 ; b11110 < b11110 " #945 0! #950 1! b01111 " b01111 < b11010 ; b11101 > b00000000000000000000000001011111 $ b0000000000000000000000000000000000000000000000000000001110110110 / b10011 = #955 0! #960 1! b11101 = b0000000000000000000000000000000000000000000000000000001111000000 / b00000000000000000000000001100000 $ b11010 > b01101 ; b10011 < b10011 " #965 0! #970 1! b11101 " b11101 < b10010 ; b01101 > b00000000000000000000000001100001 $ b0000000000000000000000000000000000000000000000000000001111001010 / b11010 = #975 0! #980 1! b01101 = b0000000000000000000000000000000000000000000000000000001111010100 / b00000000000000000000000001100010 $ b10010 > b01001 ; b11010 < b11010 " #985 0! #990 1! b01101 " b01101 < b10000 ; b01001 > b00000000000000000000000001100011 $ b0000000000000000000000000000000000000000000000000000001111011110 / b10010 = #995 0! #1000 1! b01001 = b0000000000000000000000000000000000000000000000000000001111101000 / b00000000000000000000000001100100 $ b10000 > b01000 ; b10010 < b10010 " verilator-5.042/test_regress/t/t_dfg_stats_patterns_scoped.py0000755000542200017500000000132515101701376025222 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_dfg_stats_patterns.v" test.compile( verilator_flags2=["--stats --no-skip-identical -fno-dfg-pre-inline -fno-dfg-post-inline"]) fn = test.glob_one(test.obj_dir + "/" + test.vm_prefix + "__stats_dfg_patterns*") test.files_identical(fn, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_select_bad_tri.py0000755000542200017500000000077615101701376022743 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_randstate_func.v0000644000542200017500000000166115101701376022604 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls; rand int length; function void test; automatic int rand_result, v1, v2; automatic string s; // UVM 2023 does a print, so check is ascii $display("get_randstate = '%s'", get_randstate()); s = get_randstate(); rand_result = randomize(); if (rand_result != 1) $stop; v1 = length; set_randstate(s); rand_result = randomize(); if (rand_result != 1) $stop; v2 = length; `ifdef VERILATOR // About half of the other simulators fail at this if (v1 != v2) $stop; `endif endfunction endclass module t; initial begin Cls c; c = new; c.test; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_timescale_parse.v0000644000542200017500000000370015101701376022740 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under The Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 //verilator lint_off REALCVT `define testmod(modname) \ module modname; \ time t; \ task check; t = 1ns; $write("%m %0t\n", t); endtask \ endmodule `timescale 100s/1fs `testmod(sp2) `timescale 10s/1fs `testmod(sp1) `timescale 1s/1fs `testmod(sp0) `timescale 100ms/1fs `testmod(sm1) `timescale 10ms/1fs `testmod(sm2) `timescale 1ms/1fs `testmod(sm3) `timescale 100us/1fs `testmod(sm4) `timescale 10us/1fs `testmod(sm5) `timescale 1us/1fs `testmod(sm6) `timescale 100ns/1fs `testmod(sm7) `timescale 10ns/1fs `testmod(sm8) `timescale 1ns/1fs `testmod(sm9) `timescale 100ps/1fs `testmod(sm10) `timescale 10ps/1fs `testmod(sm11) `timescale 1ps/1fs `testmod(sm12) `timescale 100 fs/1fs `testmod(sm13) `timescale 10fs/1 fs `testmod(sm14) `timescale 1 fs / 1 fs // Comment `testmod(sm15) module r0; timeunit 10ns / 1ns; task check; $write("%m %0t\n", $time); endtask endmodule module r1; timeunit 10ns; timeprecision 1ns; task check; $write("%m %0t\n", $time); endtask endmodule module t; sp2 sp2(); sp1 sp1(); sp0 sp0(); sm1 sm1(); sm2 sm2(); sm3 sm3(); sm4 sm4(); sm5 sm5(); sm6 sm6(); sm7 sm7(); sm8 sm8(); sm9 sm9(); sm10 sm10(); sm11 sm11(); sm12 sm12(); sm13 sm13(); sm14 sm14(); sm15 sm15(); r0 r0(); r1 r1(); final begin sp2.check(); sp1.check(); sp0.check(); sm1.check(); sm2.check(); sm3.check(); sm4.check(); sm5.check(); sm6.check(); sm7.check(); sm8.check(); sm9.check(); sm10.check(); sm11.check(); sm12.check(); sm13.check(); sm14.check(); sm15.check(); r0.check(); r1.check(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_process_std.py0000755000542200017500000000112015101701376022310 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_process.v" test.compile(v_flags2=["--binary", "+define+T_PROCESS+std::process"]) if not test.vlt_all: test.execute() test.passes() verilator-5.042/test_regress/t/t_flag_names.v0000644000542200017500000000111515101701376021672 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2016 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; sub sub (); endmodule module sub; //verilator no_inline_module string scope; initial begin scope = $sformatf("%m"); $write("[%0t] In %s\n", $time, scope); `ifdef VERILATOR if (scope != "top.l2Name.sub") $stop; `else if (scope != "top.t.sub") $stop; `endif $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_module_input_default_value_2_bad.py0000755000542200017500000000076615101701376026432 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_gate_inline_wide_noexclude_other_scope.py0000755000542200017500000000111415101701376027711 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=['--stats', '--expand-limit 5']) test.file_grep(test.stats, r'Optimizations, Gate excluded wide expressions\s+(\d+)', 0) test.passes() verilator-5.042/test_regress/t/t_func_uninit.py0000755000542200017500000000073415101701376022313 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_do_while.v0000644000542200017500000000237715101701376021403 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 function automatic int get_1; int a = 0; do begin int x = 1; a += x; end while (a < 0); return a; endfunction module t; int a; initial begin if (get_1() != 1) $stop; a = 0; do begin int x = 1; a += x; if (a == 1) begin a = 2; end end while (a < 0); if (a != 2) $stop; a = 1; do begin if (a == 1) begin a = 2; end if (a == 2) begin a = 3; end end while (a < 0); if (a != 3) $stop; a = 1; do begin if (a == 1) begin do begin a++; end while (a < 5); end if (a == 2) begin a = 3; end end while (a < 0); if (a != 5) $stop; a = 1; do begin do begin int x = 1; a += x; end while (a < 3); end while (a < 5); if (a != 5) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_pp_pragma_bad.out0000644000542200017500000000060415101701376022716 0ustar mahmoudyfreeshell%Error-BADSTDPRAGMA: t/t_pp_pragma_bad.v:7:1: `pragma is missing a pragma_expression. 7 | `pragma | ^~~~~~~ ... For error description see https://verilator.org/warn/BADSTDPRAGMA?v=latest `line 1 "t/t_pp_pragma_bad.v" 1 `line 3 "t/t_pp_pragma_bad.v" 0 `line 7 "t/t_pp_pragma_bad.v" 0 `pragma `line 9 "t/t_pp_pragma_bad.v" 0 %Error: Exiting due to verilator-5.042/test_regress/t/t_covergroup_args.v0000644000542200017500000000151315101701376023007 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 // verilator lint_off COVERIGN module t; covergroup cg(int var1, int var2 = 42); endgroup cg cov1 = new(69, 77); cg cov2 = new(69); int i, j; real r; function void x(); cov1.set_inst_name("the_inst_name"); cov1.start(); cov1.sample(); cov1.stop(); void'(cov2.get_coverage()); r = cov2.get_coverage(); r = cov2.get_coverage(i, j); // verilator lint_off IGNOREDRETURN cov2.get_inst_coverage(); // verilator lint_on IGNOREDRETURN r = cov2.get_inst_coverage(i, j); cg::get_coverage(); r = cg::get_coverage(); r = cg::get_coverage(i, j); endfunction endmodule verilator-5.042/test_regress/t/t_unroll_unopt_io.py0000755000542200017500000000076015101701376023220 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--x-assign fast']) test.passes() verilator-5.042/test_regress/t/t_func_types.py0000755000542200017500000000073415101701376022151 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_disable_bad.py0000755000542200017500000000076615101701376022210 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_bind.v0000644000542200017500000000271015101701376020514 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 bit a_finished; bit b_finished; module t (/*AUTOARG*/ // Inputs clk ); input clk; wire [31:0] o; wire si = 1'b0; ExampInst i (// Outputs .o (o[31:0]), // Inputs .i (1'b0) /*AUTOINST*/); Prog p (/*AUTOINST*/ // Inputs .si (si)); always @ (posedge clk) begin if (!a_finished) $stop; if (!b_finished) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module InstModule ( output logic [31:0] so, input si ); assign so = {32{si}}; endmodule program Prog (input si); initial a_finished = 1'b1; endprogram module ExampInst (o,i); output logic [31:0] o; input i; InstModule instName (// Outputs .so (o[31:0]), // Inputs .si (i) /*AUTOINST*/); //bind InstModule Prog instProg // (.si(si)); // Note is based on context of caller bind InstModule Prog instProg (/*AUTOBIND*/ .si (si)); endmodule // Check bind at top level bind InstModule Prog2 instProg2 (/*AUTOBIND*/ .si (si)); // Check program declared after bind program Prog2 (input si); initial b_finished = 1'b1; endprogram verilator-5.042/test_regress/t/t_case_inside_bad.out0000644000542200017500000000041415101701376023215 0ustar mahmoudyfreeshell%Error: t/t_case_inside_bad.v:9:20: Illegal to have inside on a casex/casez 9 | casex (1'bx) inside | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_flag_quiet_exit.py0000755000542200017500000000136015101701376023137 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_file_does_not_exist.v" # Tests for the error message and then the absence of the # "Command Failed" line test.compile(v_flags2=["--quiet-exit"], fails=True) test.file_grep_not(test.compile_log_filename, r'Exiting due to') test.file_grep_not(test.compile_log_filename, r'Command Failed') test.passes() verilator-5.042/test_regress/t/t_langext_3_bad.py0000755000542200017500000000112615101701376022460 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.top_filename = "t/t_langext_3.v" # This is a lint only test. test.lint(v_flags2=["+1364-2001ext+v"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_gate_opt.v0000644000542200017500000000152215101701376021402 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Yutetsu TAKATSUKASA. // SPDX-License-Identifier: CC0-1.0 // bug5101 module t (); logic [1:0] in0, in1, out; logic sel; assign in0 = 1; assign in1 = 2; assign sel = 1'b1; initial begin $display("out:%d", out); $write("*-* All Finished *-*\n"); $finish; end bug5101 u_bug5101(.in0, .in1, .sel, .out); endmodule module bug5101(input wire [1:0] in0, input wire [1:0] in1, input wire sel, output logic [1:0] out); // verilator no_inline_module function logic [1:0] incr(input [1:0] in); logic [1:0] tmp; tmp = in + 1; return tmp; endfunction always_comb if (sel) out = in0; else out = incr(in1); endmodule verilator-5.042/test_regress/t/t_trace_primitive_fst.py0000755000542200017500000000104015101701376024023 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_primitive.v" test.compile(v_flags2=["--trace-fst"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_flag_wpedantic_bad.v0000644000542200017500000000037115101701376023356 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg global; endmodule verilator-5.042/test_regress/t/t_cover_expr_trace.py0000755000542200017500000000176715101701376023333 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap from pathlib import Path test.scenarios('simulator') test.top_filename = "t/t_cover_expr.v" test.compile(verilator_flags2=['--cc', '--coverage-expr', '--trace-vcd']) test.execute() # Read the input .v file and do any CHECK_COVER requests test.inline_checks() test.run(cmd=[ os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--annotate-points", "--annotate", test.obj_dir + "/annotated", test.obj_dir + "/coverage.dat", ], verilator_run=True) top = Path(test.top_filename) test.files_identical(test.obj_dir + f"/annotated/{top.name}", test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_vpi_get.v0000644000542200017500000000456415101701376021246 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2010 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef USE_VPI_NOT_DPI //We call it via $c so we can verify DPI isn't required - see bug572 `else import "DPI-C" context function int mon_check(); `endif import "DPI-C" function void dpi_print(input string somestring); `ifdef VERILATOR_COMMENTS `define PUBLIC_FLAT_RD /*verilator public_flat_rd*/ `define PUBLIC_FLAT_RW /*verilator public_flat_rw @(posedge clk)*/ `else `define PUBLIC_FLAT_RD `define PUBLIC_FLAT_RW `endif interface intf #(parameter int param `PUBLIC_FLAT_RD = 7); localparam int lparam `PUBLIC_FLAT_RD = param + 1; logic [7:0] bytesig `PUBLIC_FLAT_RD; endinterface module t (/*AUTOARG*/ // Inputs input clk `PUBLIC_FLAT_RD, // test ports input [15:0] testin `PUBLIC_FLAT_RD, output [23:0] testout `PUBLIC_FLAT_RW ); `ifdef VERILATOR `systemc_header extern "C" int mon_check(); `verilog `endif reg onebit `PUBLIC_FLAT_RW; reg [2:1] twoone `PUBLIC_FLAT_RW; reg onetwo [1:2] `PUBLIC_FLAT_RW; reg [2:1] fourthreetwoone[4:3] `PUBLIC_FLAT_RW; reg [1:0] [1:0] twobytwo `PUBLIC_FLAT_RW; int theint `PUBLIC_FLAT_RW; integer status; `ifdef IVERILOG // stop icarus optimizing signals away wire redundant = onebit | onetwo[1] | twoone | fourthreetwoone[3] | twobytwo; `endif wire subin `PUBLIC_FLAT_RD; wire subout `PUBLIC_FLAT_RD; sub sub(.*); // Test loop initial begin dpi_print("foo"); `ifdef VERILATOR status = $c32("mon_check()"); `endif `ifdef IVERILOG status = $mon_check(); `endif `ifndef USE_VPI_NOT_DPI status = mon_check(); `endif if (status!=0) begin $write("%%Error: t_vpi_get.cpp:%0d: C Test failed\n", status); $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule : t module sub #( parameter int subparam `PUBLIC_FLAT_RD = 2 ) ( input subin `PUBLIC_FLAT_RD, output subout `PUBLIC_FLAT_RD ); intf the_intf(); endmodule : sub verilator-5.042/test_regress/t/t_dpi_binary.v0000644000542200017500000000101315101701376021713 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (); initial begin // All Finished is in dpic_final $finish; end import "DPI-C" context function void dpic_final(); final dpic_final(); endmodule verilator-5.042/test_regress/t/t_hier_block_trace_fst.out0000644000542200017500000140637115101701376024311 0ustar mahmoudyfreeshell$date Thu Oct 30 10:15:27 2025 $end $version fstWriter $end $timescale 1ps $end $scope module top $end $attrbegin misc 07 $unit::enum_t 4 enum_val_0 enum_val_1 enum_val_2 enum_val_3 00 01 10 11 1 $end $var wire 1 ! clk $end $scope module t $end $var parameter 32 " PARAM_A [31:0] $end $var parameter 32 # PARAM_B [31:0] $end $var wire 1 ! clk $end $var wire 8 $ out0 [7:0] $end $var wire 8 % out1 [7:0] $end $var wire 8 & out2 [7:0] $end $var wire 8 ' out3 [7:0] $end $var wire 8 ( out3_2 [7:0] $end $var wire 8 ) out5 [7:0] $end $var wire 8 * out6 [7:0] $end $var int 32 + count [31:0] $end $scope module i_delay0 $end $var parameter 32 , N [31:0] $end $var parameter 32 - WIDTH [31:0] $end $var wire 1 ! clk $end $var wire 8 ' in [7:0] $end $var wire 8 ) out [7:0] $end $var logic 8 . tmp [7:0] $end $scope module genblk1 $end $scope module i_delay $end $var parameter 32 / N [31:0] $end $var parameter 32 - WIDTH [31:0] $end $var wire 1 ! clk $end $var wire 8 . in [7:0] $end $var wire 8 ) out [7:0] $end $var logic 8 ) tmp [7:0] $end $upscope $end $upscope $end $upscope $end $scope module i_delay1 $end $var parameter 32 0 N [31:0] $end $var parameter 32 - WIDTH [31:0] $end $var wire 1 ! clk $end $var wire 8 ) in [7:0] $end $var wire 8 * out [7:0] $end $var logic 8 1 tmp [7:0] $end $scope module genblk1 $end $scope module i_delay $end $var parameter 32 , N [31:0] $end $var parameter 32 - WIDTH [31:0] $end $var wire 1 ! clk $end $var wire 8 1 in [7:0] $end $var wire 8 * out [7:0] $end $var logic 8 2 tmp [7:0] $end $scope module genblk1 $end $scope module i_delay $end $var parameter 32 / N [31:0] $end $var parameter 32 - WIDTH [31:0] $end $var wire 1 ! clk $end $var wire 8 2 in [7:0] $end $var wire 8 * out [7:0] $end $var logic 8 * tmp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module i_sub0 $end $var wire 1 ! clk $end $var wire 8 ' in [7:0] $end $var wire 8 $ out [7:0] $end $scope module i_sub0 $end $var wire 1 ! clk $end $var wire 8 ' in [7:0] $end $var wire 8 $ out [7:0] $end $upscope $end $upscope $end $scope module i_sub1 $end $var wire 1 ! clk $end $var wire 8 $ in [11:4] $end $var wire 8 % out [7:0] $end $upscope $end $scope module i_sub2 $end $var wire 1 ! clk $end $var wire 8 % in [7:0] $end $var wire 8 & out [7:0] $end $upscope $end $scope module i_sub3 $end $var parameter 8 3 P0 [7:0] $end $var parameter 32 4 UNPACKED_ARRAY[0] [31:0] $end $var parameter 32 5 UNPACKED_ARRAY[1] [31:0] $end $var parameter 16 6 UNUSED [15:0] $end $attrbegin misc 07 "" 1 $end $var parameter 2 7 ENUM [1:0] $end $var wire 1 ! clk $end $var wire 8 & in [7:0] $end $var wire 8 ' out [7:0] $end $var logic 8 8 ff [7:0] $end $var wire 8 ' out4 [7:0] $end $var wire 8 9 out4_2 [7:0] $end $scope module i_sub4_0 $end $var parameter 32 : P0 [31:0] $end $var real_parameter 64 ; P1 $end $var real_parameter 64 < P3 $end $var wire 1 ! clk $end $var wire 8 8 in [7:0] $end $var wire 8 ' out [7:0] $end $var logic 8 ' ff [7:0] $end $var logic 128 = sub5_in[0][0] [127:0] $end $var logic 128 > sub5_in[0][1] [127:0] $end $var logic 128 ? sub5_in[0][2] [127:0] $end $var logic 128 @ sub5_in[1][0] [127:0] $end $var logic 128 A sub5_in[1][1] [127:0] $end $var logic 128 B sub5_in[1][2] [127:0] $end $var wire 8 C sub5_out[0][0] [7:0] $end $var wire 8 D sub5_out[0][1] [7:0] $end $var wire 8 E sub5_out[0][2] [7:0] $end $var wire 8 F sub5_out[1][0] [7:0] $end $var wire 8 G sub5_out[1][1] [7:0] $end $var wire 8 H sub5_out[1][2] [7:0] $end $var int 32 I count [31:0] $end $scope module i_sub5 $end $var wire 1 ! clk $end $var wire 128 J in[0][0] [127:0] $end $var wire 128 K in[0][1] [127:0] $end $var wire 128 L in[0][2] [127:0] $end $var wire 128 M in[1][0] [127:0] $end $var wire 128 N in[1][1] [127:0] $end $var wire 128 O in[1][2] [127:0] $end $var wire 8 P out[0][0] [7:0] $end $var wire 8 Q out[0][1] [7:0] $end $var wire 8 R out[0][2] [7:0] $end $var wire 8 S out[1][0] [7:0] $end $var wire 8 T out[1][1] [7:0] $end $var wire 8 U out[1][2] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var int 32 V i [31:0] $end $scope module unnamedblk2 $end $var int 32 W j [31:0] $end $scope module unnamedblk3 $end $var byte 8 X exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module i_sub4_1 $end $var parameter 32 : P0 [31:0] $end $var real_parameter 64 ; P1 $end $var real_parameter 64 Y P3 $end $var wire 1 ! clk $end $var wire 8 8 in [7:0] $end $var wire 8 9 out [7:0] $end $var logic 8 9 ff [7:0] $end $var logic 128 Z sub5_in[0][0] [127:0] $end $var logic 128 [ sub5_in[0][1] [127:0] $end $var logic 128 \ sub5_in[0][2] [127:0] $end $var logic 128 ] sub5_in[1][0] [127:0] $end $var logic 128 ^ sub5_in[1][1] [127:0] $end $var logic 128 _ sub5_in[1][2] [127:0] $end $var wire 8 ` sub5_out[0][0] [7:0] $end $var wire 8 a sub5_out[0][1] [7:0] $end $var wire 8 b sub5_out[0][2] [7:0] $end $var wire 8 c sub5_out[1][0] [7:0] $end $var wire 8 d sub5_out[1][1] [7:0] $end $var wire 8 e sub5_out[1][2] [7:0] $end $var int 32 f count [31:0] $end $scope module i_sub5 $end $var wire 1 ! clk $end $var wire 128 g in[0][0] [127:0] $end $var wire 128 h in[0][1] [127:0] $end $var wire 128 i in[0][2] [127:0] $end $var wire 128 j in[1][0] [127:0] $end $var wire 128 k in[1][1] [127:0] $end $var wire 128 l in[1][2] [127:0] $end $var wire 8 m out[0][0] [7:0] $end $var wire 8 n out[0][1] [7:0] $end $var wire 8 o out[0][2] [7:0] $end $var wire 8 p out[1][0] [7:0] $end $var wire 8 q out[1][1] [7:0] $end $var wire 8 r out[1][2] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var int 32 s i [31:0] $end $scope module unnamedblk2 $end $var int 32 t j [31:0] $end $scope module unnamedblk3 $end $var byte 8 u exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module i_sub3_2 $end $var parameter 8 3 P0 [7:0] $end $var parameter 32 v UNPACKED_ARRAY[0] [31:0] $end $var parameter 32 w UNPACKED_ARRAY[1] [31:0] $end $var parameter 16 6 UNUSED [15:0] $end $attrbegin misc 07 "" 1 $end $var parameter 2 7 ENUM [1:0] $end $var wire 1 ! clk $end $var wire 8 & in [7:0] $end $var wire 8 ( out [7:0] $end $var logic 8 x ff [7:0] $end $var wire 8 ( out4 [7:0] $end $var wire 8 y out4_2 [7:0] $end $scope module i_sub4_0 $end $var parameter 32 : P0 [31:0] $end $var real_parameter 64 ; P1 $end $var real_parameter 64 < P3 $end $var wire 1 ! clk $end $var wire 8 x in [7:0] $end $var wire 8 ( out [7:0] $end $var logic 8 ( ff [7:0] $end $var logic 128 z sub5_in[0][0] [127:0] $end $var logic 128 { sub5_in[0][1] [127:0] $end $var logic 128 | sub5_in[0][2] [127:0] $end $var logic 128 } sub5_in[1][0] [127:0] $end $var logic 128 ~ sub5_in[1][1] [127:0] $end $var logic 128 !! sub5_in[1][2] [127:0] $end $var wire 8 "! sub5_out[0][0] [7:0] $end $var wire 8 #! sub5_out[0][1] [7:0] $end $var wire 8 $! sub5_out[0][2] [7:0] $end $var wire 8 %! sub5_out[1][0] [7:0] $end $var wire 8 &! sub5_out[1][1] [7:0] $end $var wire 8 '! sub5_out[1][2] [7:0] $end $var int 32 (! count [31:0] $end $scope module i_sub5 $end $var wire 1 ! clk $end $var wire 128 )! in[0][0] [127:0] $end $var wire 128 *! in[0][1] [127:0] $end $var wire 128 +! in[0][2] [127:0] $end $var wire 128 ,! in[1][0] [127:0] $end $var wire 128 -! in[1][1] [127:0] $end $var wire 128 .! in[1][2] [127:0] $end $var wire 8 /! out[0][0] [7:0] $end $var wire 8 0! out[0][1] [7:0] $end $var wire 8 1! out[0][2] [7:0] $end $var wire 8 2! out[1][0] [7:0] $end $var wire 8 3! out[1][1] [7:0] $end $var wire 8 4! out[1][2] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var int 32 5! i [31:0] $end $scope module unnamedblk2 $end $var int 32 6! j [31:0] $end $scope module unnamedblk3 $end $var byte 8 7! exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module i_sub4_1 $end $var parameter 32 : P0 [31:0] $end $var real_parameter 64 ; P1 $end $var real_parameter 64 Y P3 $end $var wire 1 ! clk $end $var wire 8 x in [7:0] $end $var wire 8 y out [7:0] $end $var logic 8 y ff [7:0] $end $var logic 128 8! sub5_in[0][0] [127:0] $end $var logic 128 9! sub5_in[0][1] [127:0] $end $var logic 128 :! sub5_in[0][2] [127:0] $end $var logic 128 ;! sub5_in[1][0] [127:0] $end $var logic 128 ! sub5_out[0][0] [7:0] $end $var wire 8 ?! sub5_out[0][1] [7:0] $end $var wire 8 @! sub5_out[0][2] [7:0] $end $var wire 8 A! sub5_out[1][0] [7:0] $end $var wire 8 B! sub5_out[1][1] [7:0] $end $var wire 8 C! sub5_out[1][2] [7:0] $end $var int 32 D! count [31:0] $end $scope module i_sub5 $end $var wire 1 ! clk $end $var wire 128 E! in[0][0] [127:0] $end $var wire 128 F! in[0][1] [127:0] $end $var wire 128 G! in[0][2] [127:0] $end $var wire 128 H! in[1][0] [127:0] $end $var wire 128 I! in[1][1] [127:0] $end $var wire 128 J! in[1][2] [127:0] $end $var wire 8 K! out[0][0] [7:0] $end $var wire 8 L! out[0][1] [7:0] $end $var wire 8 M! out[0][2] [7:0] $end $var wire 8 N! out[1][0] [7:0] $end $var wire 8 O! out[1][1] [7:0] $end $var wire 8 P! out[1][2] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var int 32 Q! i [31:0] $end $scope module unnamedblk2 $end $var int 32 R! j [31:0] $end $scope module unnamedblk3 $end $var byte 8 S! exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub0.i_sub0 $end $var wire 1 T! clk $end $var wire 8 U! in [7:0] $end $var wire 8 V! out [7:0] $end $scope module sub0 $end $var wire 1 T! clk $end $var wire 8 U! in [7:0] $end $var wire 8 V! out [7:0] $end $var logic 8 W! ff [7:0] $end $upscope $end $upscope $end $scope module top.t.i_sub1 $end $var wire 1 X! clk $end $var wire 8 Y! in [11:4] $end $var wire 8 Z! out [7:0] $end $scope module sub1 $end $var wire 1 X! clk $end $var wire 8 Y! in [11:4] $end $var wire 8 Z! out [7:0] $end $var logic 8 [! ff [7:0] $end $upscope $end $upscope $end $scope module top.t.i_sub2 $end $attrbegin misc 07 $unit::enum_t 4 enum_val_0 enum_val_1 enum_val_2 enum_val_3 00 01 10 11 2 $end $var wire 1 \! clk $end $var wire 8 ]! in [7:0] $end $var wire 8 ^! out [7:0] $end $scope module sub2 $end $var wire 1 \! clk $end $var wire 8 ]! in [7:0] $end $var wire 8 ^! out [7:0] $end $var logic 8 _! ff [7:0] $end $scope interface in_ifs $end $var wire 1 \! clk $end $var logic 8 _! data [7:0] $end $upscope $end $scope interface out_ifs $end $var wire 1 \! clk $end $var logic 8 `! data [7:0] $end $upscope $end $scope module i_sub3 $end $scope interface in $end $var wire 1 \! clk $end $var logic 8 _! data [7:0] $end $upscope $end $scope interface out $end $var wire 1 \! clk $end $var logic 8 `! data [7:0] $end $upscope $end $var wire 8 _! in_wire [7:0] $end $var wire 8 `! out_1 [7:0] $end $var wire 8 a! out_2 [7:0] $end $scope module i_sub3 $end $var parameter 8 b! P0 [7:0] $end $var parameter 32 c! UNPACKED_ARRAY[0] [31:0] $end $var parameter 32 d! UNPACKED_ARRAY[1] [31:0] $end $var parameter 16 e! UNUSED [15:0] $end $attrbegin misc 07 "" 2 $end $var parameter 2 f! ENUM [1:0] $end $var wire 1 \! clk $end $var wire 8 _! in [7:0] $end $var wire 8 `! out [7:0] $end $var logic 8 g! ff [7:0] $end $var wire 8 `! out4 [7:0] $end $var wire 8 h! out4_2 [7:0] $end $scope module i_sub4_0 $end $var parameter 32 i! P0 [31:0] $end $var real_parameter 64 j! P1 $end $var real_parameter 64 k! P3 $end $var wire 1 \! clk $end $var wire 8 g! in [7:0] $end $var wire 8 `! out [7:0] $end $var logic 8 `! ff [7:0] $end $var logic 128 l! sub5_in[0][0] [127:0] $end $var logic 128 m! sub5_in[0][1] [127:0] $end $var logic 128 n! sub5_in[0][2] [127:0] $end $var logic 128 o! sub5_in[1][0] [127:0] $end $var logic 128 p! sub5_in[1][1] [127:0] $end $var logic 128 q! sub5_in[1][2] [127:0] $end $var wire 8 r! sub5_out[0][0] [7:0] $end $var wire 8 s! sub5_out[0][1] [7:0] $end $var wire 8 t! sub5_out[0][2] [7:0] $end $var wire 8 u! sub5_out[1][0] [7:0] $end $var wire 8 v! sub5_out[1][1] [7:0] $end $var wire 8 w! sub5_out[1][2] [7:0] $end $var int 32 x! count [31:0] $end $scope module i_sub5 $end $var wire 1 \! clk $end $var wire 128 y! in[0][0] [127:0] $end $var wire 128 z! in[0][1] [127:0] $end $var wire 128 {! in[0][2] [127:0] $end $var wire 128 |! in[1][0] [127:0] $end $var wire 128 }! in[1][1] [127:0] $end $var wire 128 ~! in[1][2] [127:0] $end $var wire 8 !" out[0][0] [7:0] $end $var wire 8 "" out[0][1] [7:0] $end $var wire 8 #" out[0][2] [7:0] $end $var wire 8 $" out[1][0] [7:0] $end $var wire 8 %" out[1][1] [7:0] $end $var wire 8 &" out[1][2] [7:0] $end $var int 32 '" count [31:0] $end $var wire 8 (" val0[0] [7:0] $end $var wire 8 )" val0[1] [7:0] $end $var wire 8 *" val1[0] [7:0] $end $var wire 8 +" val1[1] [7:0] $end $var wire 8 ," val2[0] [7:0] $end $var wire 8 -" val2[1] [7:0] $end $var wire 8 ." val3[0] [7:0] $end $var wire 8 /" val3[1] [7:0] $end $scope module i_sub0 $end $var parameter 32 0" P0 [31:0] $end $var parameter 32 1" P1 [31:0] $end $var wire 8 2" out[0] [7:0] $end $var wire 8 3" out[1] [7:0] $end $upscope $end $scope module i_sub1 $end $var parameter 32 0" P0 [31:0] $end $var parameter 32 1" P1 [31:0] $end $var wire 8 4" out[0] [7:0] $end $var wire 8 5" out[1] [7:0] $end $upscope $end $scope module i_sub2 $end $var parameter 32 0" P0 [31:0] $end $var parameter 32 1" P1 [31:0] $end $var wire 8 6" out[0] [7:0] $end $var wire 8 7" out[1] [7:0] $end $upscope $end $scope module i_sub3 $end $var parameter 32 0" P0 [31:0] $end $var parameter 32 8" P1 [31:0] $end $var wire 8 9" out[0] [7:0] $end $var wire 8 :" out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var int 32 ;" i [31:0] $end $scope module unnamedblk2 $end $var int 32 <" j [31:0] $end $scope module unnamedblk3 $end $var bit 128 =" exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module unnamedblk1 $end $var int 32 >" i [31:0] $end $scope module unnamedblk2 $end $var int 32 ?" j [31:0] $end $scope module unnamedblk3 $end $var byte 8 @" exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module i_sub4_1 $end $var parameter 32 i! P0 [31:0] $end $var real_parameter 64 j! P1 $end $var real_parameter 64 A" P3 $end $var wire 1 \! clk $end $var wire 8 g! in [7:0] $end $var wire 8 h! out [7:0] $end $var logic 8 h! ff [7:0] $end $var logic 128 B" sub5_in[0][0] [127:0] $end $var logic 128 C" sub5_in[0][1] [127:0] $end $var logic 128 D" sub5_in[0][2] [127:0] $end $var logic 128 E" sub5_in[1][0] [127:0] $end $var logic 128 F" sub5_in[1][1] [127:0] $end $var logic 128 G" sub5_in[1][2] [127:0] $end $var wire 8 H" sub5_out[0][0] [7:0] $end $var wire 8 I" sub5_out[0][1] [7:0] $end $var wire 8 J" sub5_out[0][2] [7:0] $end $var wire 8 K" sub5_out[1][0] [7:0] $end $var wire 8 L" sub5_out[1][1] [7:0] $end $var wire 8 M" sub5_out[1][2] [7:0] $end $var int 32 N" count [31:0] $end $scope module i_sub5 $end $var wire 1 \! clk $end $var wire 128 O" in[0][0] [127:0] $end $var wire 128 P" in[0][1] [127:0] $end $var wire 128 Q" in[0][2] [127:0] $end $var wire 128 R" in[1][0] [127:0] $end $var wire 128 S" in[1][1] [127:0] $end $var wire 128 T" in[1][2] [127:0] $end $var wire 8 U" out[0][0] [7:0] $end $var wire 8 V" out[0][1] [7:0] $end $var wire 8 W" out[0][2] [7:0] $end $var wire 8 X" out[1][0] [7:0] $end $var wire 8 Y" out[1][1] [7:0] $end $var wire 8 Z" out[1][2] [7:0] $end $var int 32 [" count [31:0] $end $var wire 8 \" val0[0] [7:0] $end $var wire 8 ]" val0[1] [7:0] $end $var wire 8 ^" val1[0] [7:0] $end $var wire 8 _" val1[1] [7:0] $end $var wire 8 `" val2[0] [7:0] $end $var wire 8 a" val2[1] [7:0] $end $var wire 8 b" val3[0] [7:0] $end $var wire 8 c" val3[1] [7:0] $end $scope module i_sub0 $end $var parameter 32 0" P0 [31:0] $end $var parameter 32 1" P1 [31:0] $end $var wire 8 d" out[0] [7:0] $end $var wire 8 e" out[1] [7:0] $end $upscope $end $scope module i_sub1 $end $var parameter 32 0" P0 [31:0] $end $var parameter 32 1" P1 [31:0] $end $var wire 8 f" out[0] [7:0] $end $var wire 8 g" out[1] [7:0] $end $upscope $end $scope module i_sub2 $end $var parameter 32 0" P0 [31:0] $end $var parameter 32 1" P1 [31:0] $end $var wire 8 h" out[0] [7:0] $end $var wire 8 i" out[1] [7:0] $end $upscope $end $scope module i_sub3 $end $var parameter 32 0" P0 [31:0] $end $var parameter 32 8" P1 [31:0] $end $var wire 8 j" out[0] [7:0] $end $var wire 8 k" out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var int 32 l" i [31:0] $end $scope module unnamedblk2 $end $var int 32 m" j [31:0] $end $scope module unnamedblk3 $end $var bit 128 n" exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module unnamedblk1 $end $var int 32 o" i [31:0] $end $scope module unnamedblk2 $end $var int 32 p" j [31:0] $end $scope module unnamedblk3 $end $var byte 8 q" exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module i_sub3_2 $end $var parameter 8 b! P0 [7:0] $end $var parameter 32 r" UNPACKED_ARRAY[0] [31:0] $end $var parameter 32 s" UNPACKED_ARRAY[1] [31:0] $end $var parameter 16 e! UNUSED [15:0] $end $attrbegin misc 07 "" 2 $end $var parameter 2 f! ENUM [1:0] $end $var wire 1 \! clk $end $var wire 8 _! in [7:0] $end $var wire 8 a! out [7:0] $end $var logic 8 t" ff [7:0] $end $var wire 8 a! out4 [7:0] $end $var wire 8 u" out4_2 [7:0] $end $scope module i_sub4_0 $end $var parameter 32 i! P0 [31:0] $end $var real_parameter 64 j! P1 $end $var real_parameter 64 k! P3 $end $var wire 1 \! clk $end $var wire 8 t" in [7:0] $end $var wire 8 a! out [7:0] $end $var logic 8 a! ff [7:0] $end $var logic 128 v" sub5_in[0][0] [127:0] $end $var logic 128 w" sub5_in[0][1] [127:0] $end $var logic 128 x" sub5_in[0][2] [127:0] $end $var logic 128 y" sub5_in[1][0] [127:0] $end $var logic 128 z" sub5_in[1][1] [127:0] $end $var logic 128 {" sub5_in[1][2] [127:0] $end $var wire 8 |" sub5_out[0][0] [7:0] $end $var wire 8 }" sub5_out[0][1] [7:0] $end $var wire 8 ~" sub5_out[0][2] [7:0] $end $var wire 8 !# sub5_out[1][0] [7:0] $end $var wire 8 "# sub5_out[1][1] [7:0] $end $var wire 8 ## sub5_out[1][2] [7:0] $end $var int 32 $# count [31:0] $end $scope module i_sub5 $end $var wire 1 \! clk $end $var wire 128 %# in[0][0] [127:0] $end $var wire 128 &# in[0][1] [127:0] $end $var wire 128 '# in[0][2] [127:0] $end $var wire 128 (# in[1][0] [127:0] $end $var wire 128 )# in[1][1] [127:0] $end $var wire 128 *# in[1][2] [127:0] $end $var wire 8 +# out[0][0] [7:0] $end $var wire 8 ,# out[0][1] [7:0] $end $var wire 8 -# out[0][2] [7:0] $end $var wire 8 .# out[1][0] [7:0] $end $var wire 8 /# out[1][1] [7:0] $end $var wire 8 0# out[1][2] [7:0] $end $var int 32 1# count [31:0] $end $var wire 8 2# val0[0] [7:0] $end $var wire 8 3# val0[1] [7:0] $end $var wire 8 4# val1[0] [7:0] $end $var wire 8 5# val1[1] [7:0] $end $var wire 8 6# val2[0] [7:0] $end $var wire 8 7# val2[1] [7:0] $end $var wire 8 8# val3[0] [7:0] $end $var wire 8 9# val3[1] [7:0] $end $scope module i_sub0 $end $var parameter 32 0" P0 [31:0] $end $var parameter 32 1" P1 [31:0] $end $var wire 8 :# out[0] [7:0] $end $var wire 8 ;# out[1] [7:0] $end $upscope $end $scope module i_sub1 $end $var parameter 32 0" P0 [31:0] $end $var parameter 32 1" P1 [31:0] $end $var wire 8 <# out[0] [7:0] $end $var wire 8 =# out[1] [7:0] $end $upscope $end $scope module i_sub2 $end $var parameter 32 0" P0 [31:0] $end $var parameter 32 1" P1 [31:0] $end $var wire 8 ># out[0] [7:0] $end $var wire 8 ?# out[1] [7:0] $end $upscope $end $scope module i_sub3 $end $var parameter 32 0" P0 [31:0] $end $var parameter 32 8" P1 [31:0] $end $var wire 8 @# out[0] [7:0] $end $var wire 8 A# out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var int 32 B# i [31:0] $end $scope module unnamedblk2 $end $var int 32 C# j [31:0] $end $scope module unnamedblk3 $end $var bit 128 D# exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module unnamedblk1 $end $var int 32 E# i [31:0] $end $scope module unnamedblk2 $end $var int 32 F# j [31:0] $end $scope module unnamedblk3 $end $var byte 8 G# exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module i_sub4_1 $end $var parameter 32 i! P0 [31:0] $end $var real_parameter 64 j! P1 $end $var real_parameter 64 A" P3 $end $var wire 1 \! clk $end $var wire 8 t" in [7:0] $end $var wire 8 u" out [7:0] $end $var logic 8 u" ff [7:0] $end $var logic 128 H# sub5_in[0][0] [127:0] $end $var logic 128 I# sub5_in[0][1] [127:0] $end $var logic 128 J# sub5_in[0][2] [127:0] $end $var logic 128 K# sub5_in[1][0] [127:0] $end $var logic 128 L# sub5_in[1][1] [127:0] $end $var logic 128 M# sub5_in[1][2] [127:0] $end $var wire 8 N# sub5_out[0][0] [7:0] $end $var wire 8 O# sub5_out[0][1] [7:0] $end $var wire 8 P# sub5_out[0][2] [7:0] $end $var wire 8 Q# sub5_out[1][0] [7:0] $end $var wire 8 R# sub5_out[1][1] [7:0] $end $var wire 8 S# sub5_out[1][2] [7:0] $end $var int 32 T# count [31:0] $end $scope module i_sub5 $end $var wire 1 \! clk $end $var wire 128 U# in[0][0] [127:0] $end $var wire 128 V# in[0][1] [127:0] $end $var wire 128 W# in[0][2] [127:0] $end $var wire 128 X# in[1][0] [127:0] $end $var wire 128 Y# in[1][1] [127:0] $end $var wire 128 Z# in[1][2] [127:0] $end $var wire 8 [# out[0][0] [7:0] $end $var wire 8 \# out[0][1] [7:0] $end $var wire 8 ]# out[0][2] [7:0] $end $var wire 8 ^# out[1][0] [7:0] $end $var wire 8 _# out[1][1] [7:0] $end $var wire 8 `# out[1][2] [7:0] $end $var int 32 a# count [31:0] $end $var wire 8 b# val0[0] [7:0] $end $var wire 8 c# val0[1] [7:0] $end $var wire 8 d# val1[0] [7:0] $end $var wire 8 e# val1[1] [7:0] $end $var wire 8 f# val2[0] [7:0] $end $var wire 8 g# val2[1] [7:0] $end $var wire 8 h# val3[0] [7:0] $end $var wire 8 i# val3[1] [7:0] $end $scope module i_sub0 $end $var parameter 32 0" P0 [31:0] $end $var parameter 32 1" P1 [31:0] $end $var wire 8 j# out[0] [7:0] $end $var wire 8 k# out[1] [7:0] $end $upscope $end $scope module i_sub1 $end $var parameter 32 0" P0 [31:0] $end $var parameter 32 1" P1 [31:0] $end $var wire 8 l# out[0] [7:0] $end $var wire 8 m# out[1] [7:0] $end $upscope $end $scope module i_sub2 $end $var parameter 32 0" P0 [31:0] $end $var parameter 32 1" P1 [31:0] $end $var wire 8 n# out[0] [7:0] $end $var wire 8 o# out[1] [7:0] $end $upscope $end $scope module i_sub3 $end $var parameter 32 0" P0 [31:0] $end $var parameter 32 8" P1 [31:0] $end $var wire 8 p# out[0] [7:0] $end $var wire 8 q# out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var int 32 r# i [31:0] $end $scope module unnamedblk2 $end $var int 32 s# j [31:0] $end $scope module unnamedblk3 $end $var bit 128 t# exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module unnamedblk1 $end $var int 32 u# i [31:0] $end $scope module unnamedblk2 $end $var int 32 v# j [31:0] $end $scope module unnamedblk3 $end $var byte 8 w# exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3.i_sub4_0.i_sub5 $end $var wire 1 x# clk $end $var wire 128 y# in[0][0] [127:0] $end $var wire 128 z# in[0][1] [127:0] $end $var wire 128 {# in[0][2] [127:0] $end $var wire 128 |# in[1][0] [127:0] $end $var wire 128 }# in[1][1] [127:0] $end $var wire 128 ~# in[1][2] [127:0] $end $var wire 8 !$ out[0][0] [7:0] $end $var wire 8 "$ out[0][1] [7:0] $end $var wire 8 #$ out[0][2] [7:0] $end $var wire 8 $$ out[1][0] [7:0] $end $var wire 8 %$ out[1][1] [7:0] $end $var wire 8 &$ out[1][2] [7:0] $end $scope module sub5 $end $var wire 1 x# clk $end $var wire 128 '$ in[0][0] [127:0] $end $var wire 128 ($ in[0][1] [127:0] $end $var wire 128 )$ in[0][2] [127:0] $end $var wire 128 *$ in[1][0] [127:0] $end $var wire 128 +$ in[1][1] [127:0] $end $var wire 128 ,$ in[1][2] [127:0] $end $var wire 8 -$ out[0][0] [7:0] $end $var wire 8 .$ out[0][1] [7:0] $end $var wire 8 /$ out[0][2] [7:0] $end $var wire 8 0$ out[1][0] [7:0] $end $var wire 8 1$ out[1][1] [7:0] $end $var wire 8 2$ out[1][2] [7:0] $end $var int 32 3$ count [31:0] $end $var wire 8 4$ val0[0] [7:0] $end $var wire 8 5$ val0[1] [7:0] $end $var wire 8 6$ val1[0] [7:0] $end $var wire 8 7$ val1[1] [7:0] $end $var wire 8 8$ val2[0] [7:0] $end $var wire 8 9$ val2[1] [7:0] $end $var wire 8 :$ val3[0] [7:0] $end $var wire 8 ;$ val3[1] [7:0] $end $scope module i_sub0 $end $var parameter 32 <$ P0 [31:0] $end $var parameter 32 =$ P1 [31:0] $end $var wire 8 >$ out[0] [7:0] $end $var wire 8 ?$ out[1] [7:0] $end $upscope $end $scope module i_sub1 $end $var parameter 32 <$ P0 [31:0] $end $var parameter 32 =$ P1 [31:0] $end $var wire 8 @$ out[0] [7:0] $end $var wire 8 A$ out[1] [7:0] $end $upscope $end $scope module i_sub2 $end $var parameter 32 <$ P0 [31:0] $end $var parameter 32 =$ P1 [31:0] $end $var wire 8 B$ out[0] [7:0] $end $var wire 8 C$ out[1] [7:0] $end $upscope $end $scope module i_sub3 $end $var parameter 32 <$ P0 [31:0] $end $var parameter 32 D$ P1 [31:0] $end $var wire 8 E$ out[0] [7:0] $end $var wire 8 F$ out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var int 32 G$ i [31:0] $end $scope module unnamedblk2 $end $var int 32 H$ j [31:0] $end $scope module unnamedblk3 $end $var bit 128 I$ exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3.i_sub4_1.i_sub5 $end $var wire 1 J$ clk $end $var wire 128 K$ in[0][0] [127:0] $end $var wire 128 L$ in[0][1] [127:0] $end $var wire 128 M$ in[0][2] [127:0] $end $var wire 128 N$ in[1][0] [127:0] $end $var wire 128 O$ in[1][1] [127:0] $end $var wire 128 P$ in[1][2] [127:0] $end $var wire 8 Q$ out[0][0] [7:0] $end $var wire 8 R$ out[0][1] [7:0] $end $var wire 8 S$ out[0][2] [7:0] $end $var wire 8 T$ out[1][0] [7:0] $end $var wire 8 U$ out[1][1] [7:0] $end $var wire 8 V$ out[1][2] [7:0] $end $scope module sub5 $end $var wire 1 J$ clk $end $var wire 128 W$ in[0][0] [127:0] $end $var wire 128 X$ in[0][1] [127:0] $end $var wire 128 Y$ in[0][2] [127:0] $end $var wire 128 Z$ in[1][0] [127:0] $end $var wire 128 [$ in[1][1] [127:0] $end $var wire 128 \$ in[1][2] [127:0] $end $var wire 8 ]$ out[0][0] [7:0] $end $var wire 8 ^$ out[0][1] [7:0] $end $var wire 8 _$ out[0][2] [7:0] $end $var wire 8 `$ out[1][0] [7:0] $end $var wire 8 a$ out[1][1] [7:0] $end $var wire 8 b$ out[1][2] [7:0] $end $var int 32 c$ count [31:0] $end $var wire 8 d$ val0[0] [7:0] $end $var wire 8 e$ val0[1] [7:0] $end $var wire 8 f$ val1[0] [7:0] $end $var wire 8 g$ val1[1] [7:0] $end $var wire 8 h$ val2[0] [7:0] $end $var wire 8 i$ val2[1] [7:0] $end $var wire 8 j$ val3[0] [7:0] $end $var wire 8 k$ val3[1] [7:0] $end $scope module i_sub0 $end $var parameter 32 l$ P0 [31:0] $end $var parameter 32 m$ P1 [31:0] $end $var wire 8 n$ out[0] [7:0] $end $var wire 8 o$ out[1] [7:0] $end $upscope $end $scope module i_sub1 $end $var parameter 32 l$ P0 [31:0] $end $var parameter 32 m$ P1 [31:0] $end $var wire 8 p$ out[0] [7:0] $end $var wire 8 q$ out[1] [7:0] $end $upscope $end $scope module i_sub2 $end $var parameter 32 l$ P0 [31:0] $end $var parameter 32 m$ P1 [31:0] $end $var wire 8 r$ out[0] [7:0] $end $var wire 8 s$ out[1] [7:0] $end $upscope $end $scope module i_sub3 $end $var parameter 32 l$ P0 [31:0] $end $var parameter 32 t$ P1 [31:0] $end $var wire 8 u$ out[0] [7:0] $end $var wire 8 v$ out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var int 32 w$ i [31:0] $end $scope module unnamedblk2 $end $var int 32 x$ j [31:0] $end $scope module unnamedblk3 $end $var bit 128 y$ exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3_2.i_sub4_0.i_sub5 $end $var wire 1 z$ clk $end $var wire 128 {$ in[0][0] [127:0] $end $var wire 128 |$ in[0][1] [127:0] $end $var wire 128 }$ in[0][2] [127:0] $end $var wire 128 ~$ in[1][0] [127:0] $end $var wire 128 !% in[1][1] [127:0] $end $var wire 128 "% in[1][2] [127:0] $end $var wire 8 #% out[0][0] [7:0] $end $var wire 8 $% out[0][1] [7:0] $end $var wire 8 %% out[0][2] [7:0] $end $var wire 8 &% out[1][0] [7:0] $end $var wire 8 '% out[1][1] [7:0] $end $var wire 8 (% out[1][2] [7:0] $end $scope module sub5 $end $var wire 1 z$ clk $end $var wire 128 )% in[0][0] [127:0] $end $var wire 128 *% in[0][1] [127:0] $end $var wire 128 +% in[0][2] [127:0] $end $var wire 128 ,% in[1][0] [127:0] $end $var wire 128 -% in[1][1] [127:0] $end $var wire 128 .% in[1][2] [127:0] $end $var wire 8 /% out[0][0] [7:0] $end $var wire 8 0% out[0][1] [7:0] $end $var wire 8 1% out[0][2] [7:0] $end $var wire 8 2% out[1][0] [7:0] $end $var wire 8 3% out[1][1] [7:0] $end $var wire 8 4% out[1][2] [7:0] $end $var int 32 5% count [31:0] $end $var wire 8 6% val0[0] [7:0] $end $var wire 8 7% val0[1] [7:0] $end $var wire 8 8% val1[0] [7:0] $end $var wire 8 9% val1[1] [7:0] $end $var wire 8 :% val2[0] [7:0] $end $var wire 8 ;% val2[1] [7:0] $end $var wire 8 <% val3[0] [7:0] $end $var wire 8 =% val3[1] [7:0] $end $scope module i_sub0 $end $var parameter 32 >% P0 [31:0] $end $var parameter 32 ?% P1 [31:0] $end $var wire 8 @% out[0] [7:0] $end $var wire 8 A% out[1] [7:0] $end $upscope $end $scope module i_sub1 $end $var parameter 32 >% P0 [31:0] $end $var parameter 32 ?% P1 [31:0] $end $var wire 8 B% out[0] [7:0] $end $var wire 8 C% out[1] [7:0] $end $upscope $end $scope module i_sub2 $end $var parameter 32 >% P0 [31:0] $end $var parameter 32 ?% P1 [31:0] $end $var wire 8 D% out[0] [7:0] $end $var wire 8 E% out[1] [7:0] $end $upscope $end $scope module i_sub3 $end $var parameter 32 >% P0 [31:0] $end $var parameter 32 F% P1 [31:0] $end $var wire 8 G% out[0] [7:0] $end $var wire 8 H% out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var int 32 I% i [31:0] $end $scope module unnamedblk2 $end $var int 32 J% j [31:0] $end $scope module unnamedblk3 $end $var bit 128 K% exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3_2.i_sub4_1.i_sub5 $end $var wire 1 L% clk $end $var wire 128 M% in[0][0] [127:0] $end $var wire 128 N% in[0][1] [127:0] $end $var wire 128 O% in[0][2] [127:0] $end $var wire 128 P% in[1][0] [127:0] $end $var wire 128 Q% in[1][1] [127:0] $end $var wire 128 R% in[1][2] [127:0] $end $var wire 8 S% out[0][0] [7:0] $end $var wire 8 T% out[0][1] [7:0] $end $var wire 8 U% out[0][2] [7:0] $end $var wire 8 V% out[1][0] [7:0] $end $var wire 8 W% out[1][1] [7:0] $end $var wire 8 X% out[1][2] [7:0] $end $scope module sub5 $end $var wire 1 L% clk $end $var wire 128 Y% in[0][0] [127:0] $end $var wire 128 Z% in[0][1] [127:0] $end $var wire 128 [% in[0][2] [127:0] $end $var wire 128 \% in[1][0] [127:0] $end $var wire 128 ]% in[1][1] [127:0] $end $var wire 128 ^% in[1][2] [127:0] $end $var wire 8 _% out[0][0] [7:0] $end $var wire 8 `% out[0][1] [7:0] $end $var wire 8 a% out[0][2] [7:0] $end $var wire 8 b% out[1][0] [7:0] $end $var wire 8 c% out[1][1] [7:0] $end $var wire 8 d% out[1][2] [7:0] $end $var int 32 e% count [31:0] $end $var wire 8 f% val0[0] [7:0] $end $var wire 8 g% val0[1] [7:0] $end $var wire 8 h% val1[0] [7:0] $end $var wire 8 i% val1[1] [7:0] $end $var wire 8 j% val2[0] [7:0] $end $var wire 8 k% val2[1] [7:0] $end $var wire 8 l% val3[0] [7:0] $end $var wire 8 m% val3[1] [7:0] $end $scope module i_sub0 $end $var parameter 32 n% P0 [31:0] $end $var parameter 32 o% P1 [31:0] $end $var wire 8 p% out[0] [7:0] $end $var wire 8 q% out[1] [7:0] $end $upscope $end $scope module i_sub1 $end $var parameter 32 n% P0 [31:0] $end $var parameter 32 o% P1 [31:0] $end $var wire 8 r% out[0] [7:0] $end $var wire 8 s% out[1] [7:0] $end $upscope $end $scope module i_sub2 $end $var parameter 32 n% P0 [31:0] $end $var parameter 32 o% P1 [31:0] $end $var wire 8 t% out[0] [7:0] $end $var wire 8 u% out[1] [7:0] $end $upscope $end $scope module i_sub3 $end $var parameter 32 n% P0 [31:0] $end $var parameter 32 v% P1 [31:0] $end $var wire 8 w% out[0] [7:0] $end $var wire 8 x% out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var int 32 y% i [31:0] $end $scope module unnamedblk2 $end $var int 32 z% j [31:0] $end $scope module unnamedblk3 $end $var bit 128 {% exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 {% b00000000000000000000000000000000 z% b00000000000000000000000000000000 y% b00000011 x% b00000001 w% b00000000000000000000000000000011 v% b00000010 u% b00000001 t% b00000010 s% b00000001 r% b00000010 q% b00000001 p% b00000000000000000000000000000010 o% b00000000000000000000000000000001 n% b00000011 m% b00000001 l% b00000010 k% b00000001 j% b00000010 i% b00000001 h% b00000010 g% b00000001 f% b00000000000000000000000000000000 e% b00000000 d% b00000000 c% b00000000 b% b00000000 a% b00000000 `% b00000000 _% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ^% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 [% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Z% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Y% b00000000 X% b00000000 W% b00000000 V% b00000000 U% b00000000 T% b00000000 S% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Q% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 O% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 M% 0L% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 K% b00000000000000000000000000000000 J% b00000000000000000000000000000000 I% b00000011 H% b00000001 G% b00000000000000000000000000000011 F% b00000010 E% b00000001 D% b00000010 C% b00000001 B% b00000010 A% b00000001 @% b00000000000000000000000000000010 ?% b00000000000000000000000000000001 >% b00000011 =% b00000001 <% b00000010 ;% b00000001 :% b00000010 9% b00000001 8% b00000010 7% b00000001 6% b00000000000000000000000000000000 5% b00000000 4% b00000000 3% b00000000 2% b00000000 1% b00000000 0% b00000000 /% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 .% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ,% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 *% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 )% b00000000 (% b00000000 '% b00000000 &% b00000000 %% b00000000 $% b00000000 #% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 "% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 !% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 }$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 {$ 0z$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y$ b00000000000000000000000000000000 x$ b00000000000000000000000000000000 w$ b00000011 v$ b00000001 u$ b00000000000000000000000000000011 t$ b00000010 s$ b00000001 r$ b00000010 q$ b00000001 p$ b00000010 o$ b00000001 n$ b00000000000000000000000000000010 m$ b00000000000000000000000000000001 l$ b00000011 k$ b00000001 j$ b00000010 i$ b00000001 h$ b00000010 g$ b00000001 f$ b00000010 e$ b00000001 d$ b00000000000000000000000000000000 c$ b00000000 b$ b00000000 a$ b00000000 `$ b00000000 _$ b00000000 ^$ b00000000 ]$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 [$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Z$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Y$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 X$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W$ b00000000 V$ b00000000 U$ b00000000 T$ b00000000 S$ b00000000 R$ b00000000 Q$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 O$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 M$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 K$ 0J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 I$ b00000000000000000000000000000000 H$ b00000000000000000000000000000000 G$ b00000011 F$ b00000001 E$ b00000000000000000000000000000011 D$ b00000010 C$ b00000001 B$ b00000010 A$ b00000001 @$ b00000010 ?$ b00000001 >$ b00000000000000000000000000000010 =$ b00000000000000000000000000000001 <$ b00000011 ;$ b00000001 :$ b00000010 9$ b00000001 8$ b00000010 7$ b00000001 6$ b00000010 5$ b00000001 4$ b00000000000000000000000000000000 3$ b00000000 2$ b00000000 1$ b00000000 0$ b00000000 /$ b00000000 .$ b00000000 -$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ,$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 *$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 )$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ($ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '$ b00000000 &$ b00000000 %$ b00000000 $$ b00000000 #$ b00000000 "$ b00000000 !$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 }# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 {# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y# 0x# b00000000 w# b00000000000000000000000000000000 v# b00000000000000000000000000000000 u# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t# b00000000000000000000000000000000 s# b00000000000000000000000000000000 r# b00000011 q# b00000001 p# b00000010 o# b00000001 n# b00000010 m# b00000001 l# b00000010 k# b00000001 j# b00000011 i# b00000001 h# b00000010 g# b00000001 f# b00000010 e# b00000001 d# b00000010 c# b00000001 b# b00000000000000000000000000000000 a# b00000000 `# b00000000 _# b00000000 ^# b00000000 ]# b00000000 \# b00000000 [# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Z# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Y# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 X# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 U# b00000000000000000000000000000000 T# b00000000 S# b00000000 R# b00000000 Q# b00000000 P# b00000000 O# b00000000 N# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 M# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 K# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 I# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H# b00000000 G# b00000000000000000000000000000000 F# b00000000000000000000000000000000 E# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 D# b00000000000000000000000000000000 C# b00000000000000000000000000000000 B# b00000011 A# b00000001 @# b00000010 ?# b00000001 ># b00000010 =# b00000001 <# b00000010 ;# b00000001 :# b00000011 9# b00000001 8# b00000010 7# b00000001 6# b00000010 5# b00000001 4# b00000010 3# b00000001 2# b00000000000000000000000000000000 1# b00000000 0# b00000000 /# b00000000 .# b00000000 -# b00000000 ,# b00000000 +# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 *# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 )# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 (# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 &# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 %# b00000000000000000000000000000000 $# b00000000 ## b00000000 "# b00000000 !# b00000000 ~" b00000000 }" b00000000 |" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 {" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 w" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v" b00000000 u" b00000000 t" b00000000000000000000000000000001 s" b00000000000000000000000000000000 r" b00000000 q" b00000000000000000000000000000000 p" b00000000000000000000000000000000 o" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n" b00000000000000000000000000000000 m" b00000000000000000000000000000000 l" b00000011 k" b00000001 j" b00000010 i" b00000001 h" b00000010 g" b00000001 f" b00000010 e" b00000001 d" b00000011 c" b00000001 b" b00000010 a" b00000001 `" b00000010 _" b00000001 ^" b00000010 ]" b00000001 \" b00000000000000000000000000000000 [" b00000000 Z" b00000000 Y" b00000000 X" b00000000 W" b00000000 V" b00000000 U" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 T" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 S" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Q" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 O" b00000000000000000000000000000000 N" b00000000 M" b00000000 L" b00000000 K" b00000000 J" b00000000 I" b00000000 H" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 G" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 E" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 D" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 C" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B" r5 A" b00000000 @" b00000000000000000000000000000000 ?" b00000000000000000000000000000000 >" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 =" b00000000000000000000000000000000 <" b00000000000000000000000000000000 ;" b00000011 :" b00000001 9" b00000000000000000000000000000011 8" b00000010 7" b00000001 6" b00000010 5" b00000001 4" b00000010 3" b00000001 2" b00000000000000000000000000000010 1" b00000000000000000000000000000001 0" b00000011 /" b00000001 ." b00000010 -" b00000001 ," b00000010 +" b00000001 *" b00000010 )" b00000001 (" b00000000000000000000000000000000 '" b00000000 &" b00000000 %" b00000000 $" b00000000 #" b00000000 "" b00000000 !" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 {! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y! b00000000000000000000000000000000 x! b00000000 w! b00000000 v! b00000000 u! b00000000 t! b00000000 s! b00000000 r! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 o! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l! r4.1 k! r3.1 j! b00000000000000000000000000000010 i! b00000000 h! b00000000 g! b11 f! b1111111111111101 e! b00000000000000000000000000000001 d! b00000000000000000000000000000000 c! b00000011 b! b00000000 a! b00000000 `! b00000000 _! b00000000 ^! b00000000 ]! 0\! b00000000 [! b00000000 Z! b00000000 Y! 0X! b00000000 W! b00000000 V! b00000000 U! 0T! b00000000 S! b00000000000000000000000000000000 R! b00000000000000000000000000000000 Q! b00000000 P! b00000000 O! b00000000 N! b00000000 M! b00000000 L! b00000000 K! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 G! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 E! b00000000000000000000000000000000 D! b00000000 C! b00000000 B! b00000000 A! b00000000 @! b00000000 ?! b00000000 >! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 =! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 = r4.1 < r3.1 ; b00000000000000000000000000000010 : b00000000 9 b00000000 8 b00 7 b1111111111111101 6 b00000000000000000000000000000001 5 b00000000000000000000000000000000 4 b00000001 3 b00000000 2 b00000000 1 b00000000000000000000000000000011 0 b00000000000000000000000000000001 / b00000000 . b00000000000000000000000000001000 - b00000000000000000000000000000010 , b00000000000000000000000000000000 + b00000000 * b00000000 ) b00000000 ( b00000000 ' b00000000 & b00000000 % b00000000 $ b00000000000000000000000000101100 # b00000000000000000000000000100001 " 0! $end #10 1! b00000001 % b00000010 & b00000010 ' b00000010 ( b00000000000000000000000000000001 + b00000001 8 b00000010 9 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 > b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 ? b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 @ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 A b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 B b00000000000000000000000000000001 I b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 L b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 M b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 N b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 [ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 \ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ] b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ^ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _ b00000000000000000000000000000001 f b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 h b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 j b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 k b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 l b00000001 x b00000010 y b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 { b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 | b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 } b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 !! b00000000000000000000000000000001 (! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 *! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ,! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 -! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 .! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 9! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 :! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ;! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 b00000011 9 b00000011 8 b00000000000000000000000000000010 + b00000011 ( b00000011 ' b00000101 & b00000010 $ b00000010 . b00000110 C b00000101 D b00000100 E b00000011 F b00000010 G b00000001 H b00000110 P b00000101 Q b00000100 R b00000011 S b00000010 T b00000001 U b00000000000000000000000000000010 V b00000000000000000000000000000011 W b00000110 ` b00000101 a b00000100 b b00000011 c b00000010 d b00000001 e b00000110 m b00000101 n b00000100 o b00000011 p b00000010 q b00000001 r b00000000000000000000000000000010 s b00000000000000000000000000000011 t b00000110 "! b00000101 #! b00000100 $! b00000011 %! b00000010 &! b00000001 '! b00000110 /! b00000101 0! b00000100 1! b00000011 2! b00000010 3! b00000001 4! b00000000000000000000000000000010 5! b00000000000000000000000000000011 6! b00000110 >! b00000101 ?! b00000100 @! b00000011 A! b00000010 B! b00000001 C! b00000110 K! b00000101 L! b00000100 M! b00000011 N! b00000010 O! b00000001 P! b00000000000000000000000000000010 Q! b00000000000000000000000000000011 R! b00000010 V! b00000010 W! b00000010 Y! b00000110 r! b00000101 s! b00000100 t! b00000011 u! b00000010 v! b00000001 w! b00000110 !" b00000101 "" b00000100 #" b00000011 $" b00000010 %" b00000001 &" b00000000000000000000000000000010 ;" b00000000000000000000000000000011 <" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 =" b00000000000000000000000000000010 >" b00000000000000000000000000000011 ?" b00000110 H" b00000101 I" b00000100 J" b00000011 K" b00000010 L" b00000001 M" b00000110 U" b00000101 V" b00000100 W" b00000011 X" b00000010 Y" b00000001 Z" b00000000000000000000000000000010 l" b00000000000000000000000000000011 m" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 n" b00000000000000000000000000000010 o" b00000000000000000000000000000011 p" b00000110 |" b00000101 }" b00000100 ~" b00000011 !# b00000010 "# b00000001 ## b00000110 +# b00000101 ,# b00000100 -# b00000011 .# b00000010 /# b00000001 0# b00000000000000000000000000000010 B# b00000000000000000000000000000011 C# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 D# b00000000000000000000000000000010 E# b00000000000000000000000000000011 F# b00000110 N# b00000101 O# b00000100 P# b00000011 Q# b00000010 R# b00000001 S# b00000110 [# b00000101 \# b00000100 ]# b00000011 ^# b00000010 _# b00000001 `# b00000000000000000000000000000010 r# b00000000000000000000000000000011 s# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 t# b00000000000000000000000000000010 u# b00000000000000000000000000000011 v# b00000110 !$ b00000101 "$ b00000100 #$ b00000011 $$ b00000010 %$ b00000001 &$ b00000110 -$ b00000101 .$ b00000100 /$ b00000011 0$ b00000010 1$ b00000001 2$ b00000000000000000000000000000010 G$ b00000000000000000000000000000011 H$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 I$ b00000110 Q$ b00000101 R$ b00000100 S$ b00000011 T$ b00000010 U$ b00000001 V$ b00000110 ]$ b00000101 ^$ b00000100 _$ b00000011 `$ b00000010 a$ b00000001 b$ b00000000000000000000000000000010 w$ b00000000000000000000000000000011 x$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 y$ b00000110 #% b00000101 $% b00000100 %% b00000011 &% b00000010 '% b00000001 (% b00000110 /% b00000101 0% b00000100 1% b00000011 2% b00000010 3% b00000001 4% b00000000000000000000000000000010 I% b00000000000000000000000000000011 J% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 K% b00000110 S% b00000101 T% b00000100 U% b00000011 V% b00000010 W% b00000001 X% b00000110 _% b00000101 `% b00000100 a% b00000011 b% b00000010 c% b00000001 d% b00000000000000000000000000000010 y% b00000000000000000000000000000011 z% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 {% #25 0L% 0z$ 0J$ 0x# 0\! 0X! 0T! 0! #30 1! 1T! 1X! 1\! 1x# 1J$ 1z$ 1L% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 {% b00000000 d% b00000000 c% b00000000 b% b00000000 a% b00000000 `% b00000000 _% b00000000 X% b00000000 W% b00000000 V% b00000000 U% b00000000 T% b00000000 S% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 K% b00000000 4% b00000000 3% b00000000 2% b00000000 1% b00000000 0% b00000000 /% b00000000 (% b00000000 '% b00000000 &% b00000000 %% b00000000 $% b00000000 #% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y$ b00000000 b$ b00000000 a$ b00000000 `$ b00000000 _$ b00000000 ^$ b00000000 ]$ b00000000 V$ b00000000 U$ b00000000 T$ b00000000 S$ b00000000 R$ b00000000 Q$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 I$ b00000000 2$ b00000000 1$ b00000000 0$ b00000000 /$ b00000000 .$ b00000000 -$ b00000000 &$ b00000000 %$ b00000000 $$ b00000000 #$ b00000000 "$ b00000000 !$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t# b00000000 `# b00000000 _# b00000000 ^# b00000000 ]# b00000000 \# b00000000 [# b00000000 S# b00000000 R# b00000000 Q# b00000000 P# b00000000 O# b00000000 N# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 D# b00000000 0# b00000000 /# b00000000 .# b00000000 -# b00000000 ,# b00000000 +# b00000000 ## b00000000 "# b00000000 !# b00000000 ~" b00000000 }" b00000000 |" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n" b00000000 Z" b00000000 Y" b00000000 X" b00000000 W" b00000000 V" b00000000 U" b00000000 M" b00000000 L" b00000000 K" b00000000 J" b00000000 I" b00000000 H" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 =" b00000000 &" b00000000 %" b00000000 $" b00000000 #" b00000000 "" b00000000 !" b00000000 w! b00000000 v! b00000000 u! b00000000 t! b00000000 s! b00000000 r! b00000011 Y! b00000011 W! b00000011 V! b00000000 P! b00000000 O! b00000000 N! b00000000 M! b00000000 L! b00000000 K! b00000000 C! b00000000 B! b00000000 A! b00000000 @! b00000000 ?! b00000000 >! b00000000 4! b00000000 3! b00000000 2! b00000000 1! b00000000 0! b00000000 /! b00000000 '! b00000000 &! b00000000 %! b00000000 $! b00000000 #! b00000000 "! b00000000 r b00000000 q b00000000 p b00000000 o b00000000 n b00000000 m b00000000 e b00000000 d b00000000 c b00000000 b b00000000 a b00000000 ` b00000000 U b00000000 T b00000000 S b00000000 R b00000000 Q b00000000 P b00000000 H b00000000 G b00000000 F b00000000 E b00000000 D b00000000 C b00000011 . b00000011 $ b00000111 & b00000101 ' b00000101 ( b00000000000000000000000000000011 + b00000110 8 b00000101 9 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 > b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 ? b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 @ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 A b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 B b00000000000000000000000000000011 I b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 L b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 M b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 N b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 [ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 \ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ] b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ^ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _ b00000000000000000000000000000011 f b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 h b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 j b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 k b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 l b00000110 x b00000101 y b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 { b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 | b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 } b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 !! b00000000000000000000000000000011 (! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 *! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ,! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 -! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 .! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 9! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 :! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ;! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 b00001000 9 b00001000 8 b00000000000000000000000000000100 + b00001000 ( b00001000 ' b00001000 & b00000101 $ b00000101 . b00000110 C b00000101 D b00000100 E b00000011 F b00000010 G b00000001 H b00000110 P b00000101 Q b00000100 R b00000011 S b00000010 T b00000001 U b00000110 ` b00000101 a b00000100 b b00000011 c b00000010 d b00000001 e b00000110 m b00000101 n b00000100 o b00000011 p b00000010 q b00000001 r b00000110 "! b00000101 #! b00000100 $! b00000011 %! b00000010 &! b00000001 '! b00000110 /! b00000101 0! b00000100 1! b00000011 2! b00000010 3! b00000001 4! b00000110 >! b00000101 ?! b00000100 @! b00000011 A! b00000010 B! b00000001 C! b00000110 K! b00000101 L! b00000100 M! b00000011 N! b00000010 O! b00000001 P! b00000101 V! b00000101 W! b00000101 Y! b00000110 r! b00000101 s! b00000100 t! b00000011 u! b00000010 v! b00000001 w! b00000110 !" b00000101 "" b00000100 #" b00000011 $" b00000010 %" b00000001 &" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 =" b00000110 H" b00000101 I" b00000100 J" b00000011 K" b00000010 L" b00000001 M" b00000110 U" b00000101 V" b00000100 W" b00000011 X" b00000010 Y" b00000001 Z" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 n" b00000110 |" b00000101 }" b00000100 ~" b00000011 !# b00000010 "# b00000001 ## b00000110 +# b00000101 ,# b00000100 -# b00000011 .# b00000010 /# b00000001 0# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 D# b00000110 N# b00000101 O# b00000100 P# b00000011 Q# b00000010 R# b00000001 S# b00000110 [# b00000101 \# b00000100 ]# b00000011 ^# b00000010 _# b00000001 `# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 t# b00000110 !$ b00000101 "$ b00000100 #$ b00000011 $$ b00000010 %$ b00000001 &$ b00000110 -$ b00000101 .$ b00000100 /$ b00000011 0$ b00000010 1$ b00000001 2$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 I$ b00000110 Q$ b00000101 R$ b00000100 S$ b00000011 T$ b00000010 U$ b00000001 V$ b00000110 ]$ b00000101 ^$ b00000100 _$ b00000011 `$ b00000010 a$ b00000001 b$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 y$ b00000110 #% b00000101 $% b00000100 %% b00000011 &% b00000010 '% b00000001 (% b00000110 /% b00000101 0% b00000100 1% b00000011 2% b00000010 3% b00000001 4% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 K% b00000110 S% b00000101 T% b00000100 U% b00000011 V% b00000010 W% b00000001 X% b00000110 _% b00000101 `% b00000100 a% b00000011 b% b00000010 c% b00000001 d% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 {% b00000101 _! b00000010 1 #45 0L% 0z$ 0J$ 0x# 0\! 0X! 0T! 0! #50 1! 1T! 1X! 1\! 1x# 1J$ 1z$ 1L% b00000011 1 b00000110 _! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 {% b00000000 d% b00000000 c% b00000000 b% b00000000 a% b00000000 `% b00000000 _% b00000000 X% b00000000 W% b00000000 V% b00000000 U% b00000000 T% b00000000 S% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 K% b00000000 4% b00000000 3% b00000000 2% b00000000 1% b00000000 0% b00000000 /% b00000000 (% b00000000 '% b00000000 &% b00000000 %% b00000000 $% b00000000 #% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y$ b00000000 b$ b00000000 a$ b00000000 `$ b00000000 _$ b00000000 ^$ b00000000 ]$ b00000000 V$ b00000000 U$ b00000000 T$ b00000000 S$ b00000000 R$ b00000000 Q$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 I$ b00000000 2$ b00000000 1$ b00000000 0$ b00000000 /$ b00000000 .$ b00000000 -$ b00000000 &$ b00000000 %$ b00000000 $$ b00000000 #$ b00000000 "$ b00000000 !$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t# b00000000 `# b00000000 _# b00000000 ^# b00000000 ]# b00000000 \# b00000000 [# b00000000 S# b00000000 R# b00000000 Q# b00000000 P# b00000000 O# b00000000 N# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 D# b00000000 0# b00000000 /# b00000000 .# b00000000 -# b00000000 ,# b00000000 +# b00000000 ## b00000000 "# b00000000 !# b00000000 ~" b00000000 }" b00000000 |" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n" b00000000 Z" b00000000 Y" b00000000 X" b00000000 W" b00000000 V" b00000000 U" b00000000 M" b00000000 L" b00000000 K" b00000000 J" b00000000 I" b00000000 H" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 =" b00000000 &" b00000000 %" b00000000 $" b00000000 #" b00000000 "" b00000000 !" b00000000 w! b00000000 v! b00000000 u! b00000000 t! b00000000 s! b00000000 r! b00001000 Y! b00001000 W! b00001000 V! b00000000 P! b00000000 O! b00000000 N! b00000000 M! b00000000 L! b00000000 K! b00000000 C! b00000000 B! b00000000 A! b00000000 @! b00000000 ?! b00000000 >! b00000000 4! b00000000 3! b00000000 2! b00000000 1! b00000000 0! b00000000 /! b00000000 '! b00000000 &! b00000000 %! b00000000 $! b00000000 #! b00000000 "! b00000000 r b00000000 q b00000000 p b00000000 o b00000000 n b00000000 m b00000000 e b00000000 d b00000000 c b00000000 b b00000000 a b00000000 ` b00000000 U b00000000 T b00000000 S b00000000 R b00000000 Q b00000000 P b00000000 H b00000000 G b00000000 F b00000000 E b00000000 D b00000000 C b00001000 . b00001000 $ b00001010 ' b00001010 ( b00000000000000000000000000000101 + b00001001 8 b00001010 9 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 > b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 ? b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 @ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 A b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 B b00000000000000000000000000000101 I b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 L b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 M b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 N b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 [ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 \ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ] b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ^ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _ b00000000000000000000000000000101 f b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 h b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 j b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 k b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 l b00001001 x b00001010 y b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 { b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 | b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 } b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 !! b00000000000000000000000000000101 (! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 *! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ,! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 -! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 .! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 9! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 :! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ;! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 b00001011 9 b00000000000000000000000000000110 + b00001011 ( b00001011 ' b00001010 $ b00001010 . b00000110 C b00000101 D b00000100 E b00000011 F b00000010 G b00000001 H b00000110 P b00000101 Q b00000100 R b00000011 S b00000010 T b00000001 U b00000110 ` b00000101 a b00000100 b b00000011 c b00000010 d b00000001 e b00000110 m b00000101 n b00000100 o b00000011 p b00000010 q b00000001 r b00000110 "! b00000101 #! b00000100 $! b00000011 %! b00000010 &! b00000001 '! b00000110 /! b00000101 0! b00000100 1! b00000011 2! b00000010 3! b00000001 4! b00000110 >! b00000101 ?! b00000100 @! b00000011 A! b00000010 B! b00000001 C! b00000110 K! b00000101 L! b00000100 M! b00000011 N! b00000010 O! b00000001 P! b00001010 V! b00001010 W! b00001010 Y! b00000110 r! b00000101 s! b00000100 t! b00000011 u! b00000010 v! b00000001 w! b00000110 !" b00000101 "" b00000100 #" b00000011 $" b00000010 %" b00000001 &" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 =" b00000110 H" b00000101 I" b00000100 J" b00000011 K" b00000010 L" b00000001 M" b00000110 U" b00000101 V" b00000100 W" b00000011 X" b00000010 Y" b00000001 Z" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 n" b00000110 |" b00000101 }" b00000100 ~" b00000011 !# b00000010 "# b00000001 ## b00000110 +# b00000101 ,# b00000100 -# b00000011 .# b00000010 /# b00000001 0# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 D# b00000110 N# b00000101 O# b00000100 P# b00000011 Q# b00000010 R# b00000001 S# b00000110 [# b00000101 \# b00000100 ]# b00000011 ^# b00000010 _# b00000001 `# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 t# b00000110 !$ b00000101 "$ b00000100 #$ b00000011 $$ b00000010 %$ b00000001 &$ b00000110 -$ b00000101 .$ b00000100 /$ b00000011 0$ b00000010 1$ b00000001 2$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 I$ b00000110 Q$ b00000101 R$ b00000100 S$ b00000011 T$ b00000010 U$ b00000001 V$ b00000110 ]$ b00000101 ^$ b00000100 _$ b00000011 `$ b00000010 a$ b00000001 b$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 y$ b00000110 #% b00000101 $% b00000100 %% b00000011 &% b00000010 '% b00000001 (% b00000110 /% b00000101 0% b00000100 1% b00000011 2% b00000010 3% b00000001 4% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 K% b00000110 S% b00000101 T% b00000100 U% b00000011 V% b00000010 W% b00000001 X% b00000110 _% b00000101 `% b00000100 a% b00000011 b% b00000010 c% b00000001 d% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 {% b00001000 _! b00000101 1 b00001010 & b00001010 ^! b00001010 `! b00001010 a! b00001010 h! b00001010 u" b00000010 * #65 0L% 0z$ 0J$ 0x# 0\! 0X! 0T! 0! #70 1! 1T! 1X! 1\! 1x# 1J$ 1z$ 1L% b00000011 * b00001011 u" b00001011 h! b00001011 a! b00001011 `! b00001011 ^! b00001011 & b00001000 1 b00001011 _! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 {% b00000000 d% b00000000 c% b00000000 b% b00000000 a% b00000000 `% b00000000 _% b00000000 X% b00000000 W% b00000000 V% b00000000 U% b00000000 T% b00000000 S% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 K% b00000000 4% b00000000 3% b00000000 2% b00000000 1% b00000000 0% b00000000 /% b00000000 (% b00000000 '% b00000000 &% b00000000 %% b00000000 $% b00000000 #% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y$ b00000000 b$ b00000000 a$ b00000000 `$ b00000000 _$ b00000000 ^$ b00000000 ]$ b00000000 V$ b00000000 U$ b00000000 T$ b00000000 S$ b00000000 R$ b00000000 Q$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 I$ b00000000 2$ b00000000 1$ b00000000 0$ b00000000 /$ b00000000 .$ b00000000 -$ b00000000 &$ b00000000 %$ b00000000 $$ b00000000 #$ b00000000 "$ b00000000 !$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t# b00000000 `# b00000000 _# b00000000 ^# b00000000 ]# b00000000 \# b00000000 [# b00000000 S# b00000000 R# b00000000 Q# b00000000 P# b00000000 O# b00000000 N# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 D# b00000000 0# b00000000 /# b00000000 .# b00000000 -# b00000000 ,# b00000000 +# b00000000 ## b00000000 "# b00000000 !# b00000000 ~" b00000000 }" b00000000 |" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n" b00000000 Z" b00000000 Y" b00000000 X" b00000000 W" b00000000 V" b00000000 U" b00000000 M" b00000000 L" b00000000 K" b00000000 J" b00000000 I" b00000000 H" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 =" b00000000 &" b00000000 %" b00000000 $" b00000000 #" b00000000 "" b00000000 !" b00000000 w! b00000000 v! b00000000 u! b00000000 t! b00000000 s! b00000000 r! b00001011 Y! b00001011 W! b00001011 V! b00000000 P! b00000000 O! b00000000 N! b00000000 M! b00000000 L! b00000000 K! b00000000 C! b00000000 B! b00000000 A! b00000000 @! b00000000 ?! b00000000 >! b00000000 4! b00000000 3! b00000000 2! b00000000 1! b00000000 0! b00000000 /! b00000000 '! b00000000 &! b00000000 %! b00000000 $! b00000000 #! b00000000 "! b00000000 r b00000000 q b00000000 p b00000000 o b00000000 n b00000000 m b00000000 e b00000000 d b00000000 c b00000000 b b00000000 a b00000000 ` b00000000 U b00000000 T b00000000 S b00000000 R b00000000 Q b00000000 P b00000000 H b00000000 G b00000000 F b00000000 E b00000000 D b00000000 C b00001011 . b00001011 $ b00000000000000000000000000000111 + b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 > b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 ? b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 @ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 A b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 B b00000000000000000000000000000111 I b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 L b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 M b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 N b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 [ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 \ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ] b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ^ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _ b00000000000000000000000000000111 f b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 h b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 j b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 k b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 l b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 { b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 | b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 } b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 !! b00000000000000000000000000000111 (! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 *! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ,! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 -! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 .! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 9! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 :! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ;! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 b00000000000000000000000000001000 + b00000110 C b00000101 D b00000100 E b00000011 F b00000010 G b00000001 H b00000110 P b00000101 Q b00000100 R b00000011 S b00000010 T b00000001 U b00000110 ` b00000101 a b00000100 b b00000011 c b00000010 d b00000001 e b00000110 m b00000101 n b00000100 o b00000011 p b00000010 q b00000001 r b00000110 "! b00000101 #! b00000100 $! b00000011 %! b00000010 &! b00000001 '! b00000110 /! b00000101 0! b00000100 1! b00000011 2! b00000010 3! b00000001 4! b00000110 >! b00000101 ?! b00000100 @! b00000011 A! b00000010 B! b00000001 C! b00000110 K! b00000101 L! b00000100 M! b00000011 N! b00000010 O! b00000001 P! b00000110 r! b00000101 s! b00000100 t! b00000011 u! b00000010 v! b00000001 w! b00000110 !" b00000101 "" b00000100 #" b00000011 $" b00000010 %" b00000001 &" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 =" b00000110 H" b00000101 I" b00000100 J" b00000011 K" b00000010 L" b00000001 M" b00000110 U" b00000101 V" b00000100 W" b00000011 X" b00000010 Y" b00000001 Z" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 n" b00000110 |" b00000101 }" b00000100 ~" b00000011 !# b00000010 "# b00000001 ## b00000110 +# b00000101 ,# b00000100 -# b00000011 .# b00000010 /# b00000001 0# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 D# b00000110 N# b00000101 O# b00000100 P# b00000011 Q# b00000010 R# b00000001 S# b00000110 [# b00000101 \# b00000100 ]# b00000011 ^# b00000010 _# b00000001 `# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 t# b00000110 !$ b00000101 "$ b00000100 #$ b00000011 $$ b00000010 %$ b00000001 &$ b00000110 -$ b00000101 .$ b00000100 /$ b00000011 0$ b00000010 1$ b00000001 2$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 I$ b00000110 Q$ b00000101 R$ b00000100 S$ b00000011 T$ b00000010 U$ b00000001 V$ b00000110 ]$ b00000101 ^$ b00000100 _$ b00000011 `$ b00000010 a$ b00000001 b$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 y$ b00000110 #% b00000101 $% b00000100 %% b00000011 &% b00000010 '% b00000001 (% b00000110 /% b00000101 0% b00000100 1% b00000011 2% b00000010 3% b00000001 4% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 K% b00000110 S% b00000101 T% b00000100 U% b00000011 V% b00000010 W% b00000001 X% b00000110 _% b00000101 `% b00000100 a% b00000011 b% b00000010 c% b00000001 d% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 {% b00001101 _! b00001010 1 b00001101 & b00001101 ^! b00001101 `! b00001101 a! b00001101 h! b00001101 u" b00000101 * b00001101 ' b00001101 ( b00001101 9 b00001101 y b00001101 U! #85 0L% 0z$ 0J$ 0x# 0\! 0X! 0T! 0! #90 1! 1T! 1X! 1\! 1x# 1J$ 1z$ 1L% b00001110 U! b00001110 y b00001110 9 b00001110 ( b00001110 ' b00001000 * b00010000 u" b00010000 h! b00010000 a! b00010000 `! b00010000 ^! b00010000 & b00001011 1 b00001110 _! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 {% b00000000 d% b00000000 c% b00000000 b% b00000000 a% b00000000 `% b00000000 _% b00000000 X% b00000000 W% b00000000 V% b00000000 U% b00000000 T% b00000000 S% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 K% b00000000 4% b00000000 3% b00000000 2% b00000000 1% b00000000 0% b00000000 /% b00000000 (% b00000000 '% b00000000 &% b00000000 %% b00000000 $% b00000000 #% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y$ b00000000 b$ b00000000 a$ b00000000 `$ b00000000 _$ b00000000 ^$ b00000000 ]$ b00000000 V$ b00000000 U$ b00000000 T$ b00000000 S$ b00000000 R$ b00000000 Q$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 I$ b00000000 2$ b00000000 1$ b00000000 0$ b00000000 /$ b00000000 .$ b00000000 -$ b00000000 &$ b00000000 %$ b00000000 $$ b00000000 #$ b00000000 "$ b00000000 !$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t# b00000000 `# b00000000 _# b00000000 ^# b00000000 ]# b00000000 \# b00000000 [# b00000000 S# b00000000 R# b00000000 Q# b00000000 P# b00000000 O# b00000000 N# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 D# b00000000 0# b00000000 /# b00000000 .# b00000000 -# b00000000 ,# b00000000 +# b00000000 ## b00000000 "# b00000000 !# b00000000 ~" b00000000 }" b00000000 |" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n" b00000000 Z" b00000000 Y" b00000000 X" b00000000 W" b00000000 V" b00000000 U" b00000000 M" b00000000 L" b00000000 K" b00000000 J" b00000000 I" b00000000 H" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 =" b00000000 &" b00000000 %" b00000000 $" b00000000 #" b00000000 "" b00000000 !" b00000000 w! b00000000 v! b00000000 u! b00000000 t! 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b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 @ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 A b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 B b00000000000000000000000000001001 I b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 L b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 M b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 N b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 [ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 \ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ] b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ^ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _ b00000000000000000000000000001001 f b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 h b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 j b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 k b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 l b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 { b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 | b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 } b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 !! b00000000000000000000000000001001 (! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 *! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ,! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 -! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 .! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 9! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 :! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ;! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 b00000000000000000000000000001010 + b00000110 C b00000101 D b00000100 E b00000011 F b00000010 G b00000001 H b00000110 P b00000101 Q b00000100 R b00000011 S b00000010 T b00000001 U b00000110 ` b00000101 a b00000100 b b00000011 c b00000010 d b00000001 e b00000110 m b00000101 n b00000100 o b00000011 p b00000010 q b00000001 r b00000110 "! b00000101 #! b00000100 $! b00000011 %! b00000010 &! b00000001 '! b00000110 /! b00000101 0! b00000100 1! b00000011 2! b00000010 3! b00000001 4! b00000110 >! b00000101 ?! b00000100 @! b00000011 A! b00000010 B! b00000001 C! b00000110 K! b00000101 L! b00000100 M! b00000011 N! b00000010 O! b00000001 P! b00000110 r! b00000101 s! b00000100 t! b00000011 u! b00000010 v! b00000001 w! b00000110 !" b00000101 "" b00000100 #" b00000011 $" b00000010 %" b00000001 &" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 =" b00000110 H" b00000101 I" b00000100 J" b00000011 K" b00000010 L" b00000001 M" b00000110 U" b00000101 V" b00000100 W" b00000011 X" b00000010 Y" b00000001 Z" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 n" b00000110 |" b00000101 }" b00000100 ~" b00000011 !# b00000010 "# b00000001 ## b00000110 +# b00000101 ,# b00000100 -# b00000011 .# b00000010 /# b00000001 0# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 D# b00000110 N# b00000101 O# b00000100 P# b00000011 Q# b00000010 R# b00000001 S# b00000110 [# b00000101 \# b00000100 ]# b00000011 ^# b00000010 _# b00000001 `# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 t# b00000110 !$ b00000101 "$ b00000100 #$ b00000011 $$ b00000010 %$ b00000001 &$ b00000110 -$ b00000101 .$ b00000100 /$ b00000011 0$ b00000010 1$ b00000001 2$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 I$ b00000110 Q$ b00000101 R$ b00000100 S$ b00000011 T$ b00000010 U$ b00000001 V$ b00000110 ]$ b00000101 ^$ b00000100 _$ b00000011 `$ b00000010 a$ b00000001 b$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 y$ b00000110 #% b00000101 $% b00000100 %% b00000011 &% b00000010 '% b00000001 (% b00000110 /% b00000101 0% b00000100 1% b00000011 2% b00000010 3% b00000001 4% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 K% b00000110 S% b00000101 T% b00000100 U% b00000011 V% b00000010 W% b00000001 X% b00000110 _% b00000101 `% b00000100 a% b00000011 b% b00000010 c% b00000001 d% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 {% b00010010 & b00010010 ^! b00010010 `! b00010010 a! b00010010 h! b00010010 u" b00001010 * b00010000 ' b00010000 ( b00010000 9 b00010000 y b00010000 U! b00001110 ]! b00001110 [! b00001110 Z! b00001110 % b00001101 ) #105 0L% 0z$ 0J$ 0x# 0\! 0X! 0T! 0! #110 1! 1T! 1X! 1\! 1x# 1J$ 1z$ 1L% b00001110 ) b00001111 % b00001111 Z! b00001111 [! b00001111 ]! b00010011 U! b00010011 y b00010011 9 b00010011 ( b00010011 ' b00001011 * b00010011 u" b00010011 h! b00010011 a! b00010011 `! b00010011 ^! b00010011 & b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 {% b00000000 d% b00000000 c% b00000000 b% b00000000 a% b00000000 `% b00000000 _% b00000000 X% b00000000 W% b00000000 V% b00000000 U% b00000000 T% b00000000 S% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 K% b00000000 4% b00000000 3% b00000000 2% b00000000 1% b00000000 0% b00000000 /% b00000000 (% b00000000 '% b00000000 &% b00000000 %% b00000000 $% b00000000 #% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y$ b00000000 b$ b00000000 a$ b00000000 `$ b00000000 _$ b00000000 ^$ b00000000 ]$ b00000000 V$ b00000000 U$ b00000000 T$ b00000000 S$ b00000000 R$ b00000000 Q$ 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b00000000 F b00000000 E b00000000 D b00000000 C b00000000000000000000000000001011 + b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 > b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 ? b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 @ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 A b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 B b00000000000000000000000000001011 I b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 L b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 M b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 N b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 [ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 \ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ] b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ^ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _ b00000000000000000000000000001011 f b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 h b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 j b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 k b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 l b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 { b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 | b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 } b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 !! b00000000000000000000000000001011 (! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 *! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ,! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 -! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 .! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 9! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 :! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ;! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 b00000000000000000000000000001100 + b00000110 C b00000101 D b00000100 E b00000011 F b00000010 G b00000001 H b00000110 P b00000101 Q b00000100 R b00000011 S b00000010 T b00000001 U b00000110 ` b00000101 a b00000100 b b00000011 c b00000010 d b00000001 e b00000110 m b00000101 n b00000100 o b00000011 p b00000010 q b00000001 r b00000110 "! b00000101 #! b00000100 $! b00000011 %! b00000010 &! b00000001 '! b00000110 /! b00000101 0! b00000100 1! b00000011 2! b00000010 3! b00000001 4! b00000110 >! b00000101 ?! b00000100 @! b00000011 A! b00000010 B! b00000001 C! b00000110 K! b00000101 L! b00000100 M! b00000011 N! b00000010 O! b00000001 P! b00000110 r! b00000101 s! b00000100 t! b00000011 u! b00000010 v! b00000001 w! b00000110 !" b00000101 "" b00000100 #" b00000011 $" b00000010 %" b00000001 &" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 =" b00000110 H" b00000101 I" b00000100 J" b00000011 K" b00000010 L" b00000001 M" b00000110 U" b00000101 V" b00000100 W" b00000011 X" b00000010 Y" b00000001 Z" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 n" b00000110 |" b00000101 }" b00000100 ~" b00000011 !# b00000010 "# b00000001 ## b00000110 +# b00000101 ,# b00000100 -# b00000011 .# b00000010 /# b00000001 0# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 D# b00000110 N# b00000101 O# b00000100 P# b00000011 Q# b00000010 R# b00000001 S# b00000110 [# b00000101 \# b00000100 ]# b00000011 ^# b00000010 _# b00000001 `# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 t# b00000110 !$ b00000101 "$ b00000100 #$ b00000011 $$ b00000010 %$ b00000001 &$ b00000110 -$ b00000101 .$ b00000100 /$ b00000011 0$ b00000010 1$ b00000001 2$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 I$ b00000110 Q$ b00000101 R$ b00000100 S$ b00000011 T$ b00000010 U$ b00000001 V$ b00000110 ]$ b00000101 ^$ b00000100 _$ b00000011 `$ b00000010 a$ b00000001 b$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 y$ b00000110 #% b00000101 $% b00000100 %% b00000011 &% b00000010 '% b00000001 (% b00000110 /% b00000101 0% b00000100 1% b00000011 2% b00000010 3% b00000001 4% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 K% b00000110 S% b00000101 T% b00000100 U% b00000011 V% b00000010 W% b00000001 X% b00000110 _% b00000101 `% b00000100 a% b00000011 b% b00000010 c% b00000001 d% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 {% b00010101 ' b00010101 ( b00010101 9 b00010101 y b00010101 U! b00010001 ]! b00010001 [! b00010001 Z! b00010001 % b00010000 ) b00010011 t" b00010011 g! b00001101 2 #125 0L% 0z$ 0J$ 0x# 0\! 0X! 0T! 0! #130 1! 1T! 1X! 1\! 1x# 1J$ 1z$ 1L% b00001110 2 b00010100 g! b00010100 t" b00010011 ) b00010100 % b00010100 Z! b00010100 [! b00010100 ]! b00010110 U! b00010110 y b00010110 9 b00010110 ( b00010110 ' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 {% b00000000 d% b00000000 c% b00000000 b% b00000000 a% b00000000 `% b00000000 _% b00000000 X% b00000000 W% b00000000 V% b00000000 U% b00000000 T% b00000000 S% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 K% b00000000 4% b00000000 3% b00000000 2% b00000000 1% b00000000 0% b00000000 /% b00000000 (% b00000000 '% b00000000 &% b00000000 %% b00000000 $% b00000000 #% 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b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 B b00000000000000000000000000001101 I b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 L b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 M b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 N b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 [ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 \ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ] b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ^ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _ b00000000000000000000000000001101 f b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 h b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 j b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 k b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 l b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 { b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 | b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 } b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 !! b00000000000000000000000000001101 (! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 *! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ,! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 -! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 .! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 9! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 :! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ;! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 b00000000000000000000000000001110 + b00000110 C b00000101 D b00000100 E b00000011 F b00000010 G b00000001 H b00000110 P b00000101 Q b00000100 R b00000011 S b00000010 T b00000001 U b00000110 ` b00000101 a b00000100 b b00000011 c b00000010 d b00000001 e b00000110 m b00000101 n b00000100 o b00000011 p b00000010 q b00000001 r b00000110 "! b00000101 #! b00000100 $! b00000011 %! b00000010 &! b00000001 '! b00000110 /! b00000101 0! b00000100 1! b00000011 2! b00000010 3! b00000001 4! b00000110 >! b00000101 ?! b00000100 @! b00000011 A! b00000010 B! b00000001 C! b00000110 K! b00000101 L! b00000100 M! b00000011 N! b00000010 O! b00000001 P! b00000110 r! b00000101 s! b00000100 t! b00000011 u! b00000010 v! b00000001 w! b00000110 !" b00000101 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b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 @ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 A b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 B b00000000000000000000000000001111 I b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 L b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 M b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 N b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 [ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 \ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ] b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ^ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _ b00000000000000000000000000001111 f b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 h b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 j b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 k b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 l b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 { b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 | b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 } b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 !! b00000000000000000000000000001111 (! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 *! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ,! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 -! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 .! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 9! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 :! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ;! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 b00000000000000000000000000010000 + b00000110 C b00000101 D b00000100 E b00000011 F b00000010 G b00000001 H b00000110 P b00000101 Q b00000100 R b00000011 S b00000010 T b00000001 U b00000110 ` b00000101 a b00000100 b b00000011 c b00000010 d b00000001 e b00000110 m b00000101 n b00000100 o b00000011 p b00000010 q b00000001 r b00000110 "! b00000101 #! b00000100 $! b00000011 %! b00000010 &! b00000001 '! b00000110 /! b00000101 0! b00000100 1! b00000011 2! b00000010 3! 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b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 D# b00000110 N# b00000101 O# b00000100 P# b00000011 Q# b00000010 R# b00000001 S# b00000110 [# b00000101 \# b00000100 ]# b00000011 ^# b00000010 _# b00000001 `# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 t# b00000110 !$ b00000101 "$ b00000100 #$ b00000011 $$ b00000010 %$ b00000001 &$ b00000110 -$ b00000101 .$ b00000100 /$ b00000011 0$ b00000010 1$ b00000001 2$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 I$ b00000110 Q$ b00000101 R$ b00000100 S$ b00000011 T$ b00000010 U$ b00000001 V$ b00000110 ]$ b00000101 ^$ b00000100 _$ b00000011 `$ b00000010 a$ b00000001 b$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 y$ b00000110 #% b00000101 $% b00000100 %% b00000011 &% b00000010 '% b00000001 (% b00000110 /% b00000101 0% b00000100 1% b00000011 2% b00000010 3% b00000001 4% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 K% b00000110 S% b00000101 T% b00000100 U% b00000011 V% b00000010 W% b00000001 X% b00000110 _% b00000101 `% b00000100 a% b00000011 b% b00000010 c% b00000001 d% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 {% b00011011 t" b00011011 g! b00010101 2 b00011001 x b00011001 8 b00011000 $ b00011000 . b00011000 V! b00011000 W! b00011000 Y! #165 0L% 0z$ 0J$ 0x# 0\! 0X! 0T! 0! #170 1! 1T! 1X! 1\! 1x# 1J$ 1z$ 1L% b00011001 Y! b00011001 W! b00011001 V! b00011001 . b00011001 $ b00011100 8 b00011100 x b00010110 2 b00011100 g! b00011100 t" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 {% b00000000 d% b00000000 c% b00000000 b% b00000000 a% b00000000 `% b00000000 _% b00000000 X% b00000000 W% b00000000 V% b00000000 U% b00000000 T% b00000000 S% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 K% b00000000 4% b00000000 3% b00000000 2% b00000000 1% b00000000 0% b00000000 /% b00000000 (% b00000000 '% b00000000 &% b00000000 %% b00000000 $% b00000000 #% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y$ b00000000 b$ b00000000 a$ b00000000 `$ b00000000 _$ b00000000 ^$ b00000000 ]$ b00000000 V$ b00000000 U$ b00000000 T$ b00000000 S$ b00000000 R$ b00000000 Q$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 I$ 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b00000000 I" b00000000 H" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 =" b00000000 &" b00000000 %" b00000000 $" b00000000 #" b00000000 "" b00000000 !" b00000000 w! b00000000 v! b00000000 u! b00000000 t! b00000000 s! b00000000 r! b00000000 P! b00000000 O! b00000000 N! b00000000 M! b00000000 L! b00000000 K! b00000000 C! b00000000 B! b00000000 A! b00000000 @! b00000000 ?! b00000000 >! b00000000 4! b00000000 3! b00000000 2! b00000000 1! b00000000 0! b00000000 /! b00000000 '! b00000000 &! b00000000 %! b00000000 $! b00000000 #! b00000000 "! b00000000 r b00000000 q b00000000 p b00000000 o b00000000 n b00000000 m b00000000 e b00000000 d b00000000 c b00000000 b b00000000 a b00000000 ` b00000000 U b00000000 T b00000000 S b00000000 R b00000000 Q b00000000 P b00000000 H b00000000 G b00000000 F b00000000 E b00000000 D b00000000 C b00000000000000000000000000010001 + b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 > b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 ? b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 @ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 A b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 B b00000000000000000000000000010001 I b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 L b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 M b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 N b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 [ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 \ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ] b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ^ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _ b00000000000000000000000000010001 f b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 h b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 j b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 k b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 l b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 { b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 | b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 } b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 !! b00000000000000000000000000010001 (! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 *! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ,! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 -! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 .! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 9! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 :! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ;! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 " "struct{bit A;bit B;}t.AB_t" ==? "struct{bit A;bit B;}" "struct{bit A;bit B;}t.AB_t$[0:9]" ==? "struct{bit A;bit B;}top.AB_t$[0:9]" "union{bit A;bit B;}t.UAB_t" ==? "union{bit A;bit B;}" "class{}Cls" ==? "class{}t.Cls " *-* All Finished *-* verilator-5.042/test_regress/t/t_x_rand_mt_stability_trace.out0000644000542200017500000000105615101701376025361 0ustar mahmoudyfreeshelluninitialized = 0xf5bbcbc0 x_assigned (initial) = 0x00000000 uninitialized2 = 0xa979eb54 big = 0xa20c93ac50d8c57d4c80949aa68e82775da6af98ce08f75dc6ccfad97b059a33 random_init = 0x952aaa76 top.t.the_sub_yes_inline_1 no_init 0x4a544f7798b83fc8 top.t.the_sub_yes_inline_2 no_init 0x19b7000ee0472c9 top.t.the_sub_no_inline_1 no_init 0x38121a34978975dd top.t.the_sub_no_inline_2 no_init 0x9022c84ae0fa3cf6 rand = 0xb3cf9302 rand = 0xf0acf3e4 rand = 0xca0ac74c rand = 0x4eddfc2c rand = 0x1919db69 x_assigned = 0x486aeb2d Last rand = 0x2d118c9b *-* All Finished *-* verilator-5.042/test_regress/t/t_vams_wreal.v0000644000542200017500000000601715101701376021744 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `begin_keywords "VAMS-2.3" module t (/*autoarg*/ // Inputs clk, in ); input clk; input [15:0] in; wreal aout; integer cyc = 0; real vin; wreal vpass; through through (.vin, .vpass); real gnd; wire out; within_range within_range (/*AUTOINST*/ // Interfaces .vpass (vpass), .gnd (gnd), // Outputs .out (out)); // wreal bus declaration wreal vin_upper_bus[1:0]; // wreal nets declaration wreal vout_split_0; wreal vout_split_1; wreal_bus wreal_bus( .vin_bus(vin_upper_bus[1:0]), .vout_split_0(vout_split_0), .vout_split_1(vout_split_1)); // implicit declaration of wreal `ifdef VERILATOR wreal wreal_implicit_net; // implicit declaration of wreal not supported yet `endif // verilator lint_off IMPLICIT first_level first_level(.in(cyc[0]), .out(wreal_implicit_net)); // verilator lint_on IMPLICIT parameter real LSB = 1; // verilator lint_off WIDTH assign aout = $itor(in) * LSB; // verilator lint_on WIDTH always @ (posedge clk) begin cyc <= cyc + 1; `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d aout=%d (%f-%f=%f)\n", $time, cyc, out, vin, gnd, within_range.in_int); `endif if (cyc==0) begin // Setup gnd = 0.0; vin = 0.2; end else if (cyc==2) begin if (out != 0) $stop; end else if (cyc==3) begin gnd = 0.0; vin = 0.6; end else if (cyc==4) begin if (out != 1) $stop; end else if (cyc==5) begin gnd = 0.6; vin = 0.8; end else if (cyc==6) begin if (out != 0) $stop; end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module through (input wreal vin, output wreal vpass); assign vpass = vin; endmodule module within_range (input wreal vpass, input wreal gnd, output out); parameter real V_MIN = 0.5; parameter real V_MAX = 10; wreal in_int = vpass - gnd; assign out = (V_MIN <= in_int && in_int <= V_MAX); endmodule module wreal_bus (input wreal vin_bus [1:0], output wreal vout_split_0, output wreal vout_split_1); assign vout_split_0 = vin_bus[0]; assign vout_split_1 = vin_bus[1]; endmodule module first_level (input in, `ifdef VERILATOR output wreal out `else output out // Implicity becomes real `endif ); second_level second_level(.in(in), .out(out)); endmodule module second_level(in, out); input in; output out; wreal out; assign out = in ? 1.23456: 7.8910; endmodule verilator-5.042/test_regress/t/t_timing_long.py0000755000542200017500000000354215101701376022300 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = test.obj_dir + "/t_timing_long.v" # Look for O(n^2) problems in process handling def gen(filename): with open(filename, 'w', encoding="utf8") as fh: fh.write("// Generated by t_timing_long.py\n") fh.write("\n") fh.write("`ifdef TEST_VERBOSE\n") fh.write(" `define MSG(m) $display m\n") fh.write("`else\n") fh.write(" `define MSG(m)\n") fh.write("`endif\n") fh.write("\n") fh.write("module t;\n") fh.write("\n") fh.write(" int cnt;\n") fh.write("\n") fh.write(" initial begin\n") n = 100 for i in range(1, n): # If statement around the timing is important to make the code scheduling # mostly unpredictable fh.write(" if (cnt == " + str(i - 1) + ") begin\n") fh.write(" #1; ++cnt; `MSG((\"[%0t] cnt?=" + str(i) + "\", $time));" + " if (cnt != " + str(i) + ") $stop;\n") fh.write(" end\n") fh.write("\n") fh.write(' $write("*-* All Finished *-*\\n");' + "\n") fh.write(" $finish;\n") fh.write(" end\n") fh.write("endmodule\n") gen(test.top_filename) if test.have_coroutines: test.compile(verilator_flags2=["--binary"], make_top=1) test.execute() test.compile(verilator_flags2=["--binary --no-timing -Wno-STMTDLY"], make_top=1) test.execute() test.passes() verilator-5.042/test_regress/t/t_wrapper_clone.py0000755000542200017500000000125615101701376022632 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test module for prepareClone/atClone APIs # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename, "-cc"], threads=(2 if test.vltmt else 1)) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_scheduling_1.py0000755000542200017500000000073415101701376022337 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_ref_trace.out0000644000542200017500000004706615101701376024131 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $var wire 1 0 clk $end $scope module t $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $scope module intf_1 $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 $ value [31:0] $end $scope module the_struct $end $var wire 32 % val100 [31:0] $end $var wire 32 & val200 [31:0] $end $upscope $end $scope module inner $end $var wire 32 # cyc [31:0] $end $var wire 32 1 value [31:0] $end $upscope $end $upscope $end $scope module intf_2 $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 ' value [31:0] $end $scope module the_struct $end $var wire 32 ( val100 [31:0] $end $var wire 32 ) val200 [31:0] $end $upscope $end $scope module inner $end $var wire 32 # cyc [31:0] $end $var wire 32 2 value [31:0] $end $upscope $end $upscope $end $scope module c1 $end $scope module intf_for_check $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 $ value [31:0] $end $scope module the_struct $end $var wire 32 % val100 [31:0] $end $var wire 32 & val200 [31:0] $end $upscope $end $scope module inner $end $var wire 32 # cyc [31:0] $end $var wire 32 1 value [31:0] $end $upscope $end $upscope $end $upscope $end $scope module c2 $end $scope module intf_for_check $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 ' value [31:0] $end $scope module the_struct $end $var wire 32 ( val100 [31:0] $end $var wire 32 ) val200 [31:0] $end $upscope $end $scope module inner $end $var wire 32 # cyc [31:0] $end $var wire 32 2 value [31:0] $end $upscope $end $upscope $end $upscope $end $scope module a $end $scope module intf_one $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 $ value [31:0] $end $scope module the_struct $end $var wire 32 % val100 [31:0] $end $var wire 32 & val200 [31:0] $end $upscope $end $scope module inner $end $var wire 32 # cyc [31:0] $end $var wire 32 1 value [31:0] $end $upscope $end $upscope $end $scope module intf_two $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 ' value [31:0] $end $scope module the_struct $end $var wire 32 ( val100 [31:0] $end $var wire 32 ) val200 [31:0] $end $upscope $end $scope module inner $end $var wire 32 # cyc [31:0] $end $var wire 32 2 value [31:0] $end $upscope $end $upscope $end $scope module intf_in_sub_all $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 * value [31:0] $end $scope module the_struct $end $var wire 32 + val100 [31:0] $end $var wire 32 , val200 [31:0] $end $upscope $end $scope module inner $end $var wire 32 # cyc [31:0] $end $var wire 32 3 value [31:0] $end $upscope $end $upscope $end $scope module ac1 $end $scope module intf_for_check $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 $ value [31:0] $end $scope module the_struct $end $var wire 32 % val100 [31:0] $end $var wire 32 & val200 [31:0] $end $upscope $end $scope module inner $end $var wire 32 # cyc [31:0] $end $var wire 32 1 value [31:0] $end $upscope $end $upscope $end $upscope $end $scope module ac2 $end $scope module intf_for_check $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 ' value [31:0] $end $scope module the_struct $end $var wire 32 ( val100 [31:0] $end $var wire 32 ) val200 [31:0] $end $upscope $end $scope module inner $end $var wire 32 # cyc [31:0] $end $var wire 32 2 value [31:0] $end $upscope $end $upscope $end $upscope $end $scope module ac3 $end $scope module intf_for_check $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 * value [31:0] $end $scope module the_struct $end $var wire 32 + val100 [31:0] $end $var wire 32 , val200 [31:0] $end $upscope $end $scope module inner $end $var wire 32 # cyc [31:0] $end $var wire 32 3 value [31:0] $end $upscope $end $upscope $end $upscope $end $scope module as3 $end $scope module intf_for_struct $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 * value [31:0] $end $scope module the_struct $end $var wire 32 + val100 [31:0] $end $var wire 32 , val200 [31:0] $end $upscope $end $scope module inner $end $var wire 32 # cyc [31:0] $end $var wire 32 3 value [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module abcdefghijklmnopqrstuvwxyz $end $scope module intf_one $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 ' value [31:0] $end $scope module the_struct $end $var wire 32 ( val100 [31:0] $end $var wire 32 ) val200 [31:0] $end $upscope $end $scope module inner $end $var wire 32 # cyc [31:0] $end $var wire 32 2 value [31:0] $end $upscope $end $upscope $end $scope module intf_two $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 $ value [31:0] $end $scope module the_struct $end $var wire 32 % val100 [31:0] $end $var wire 32 & val200 [31:0] $end $upscope $end $scope module inner $end $var wire 32 # cyc [31:0] $end $var wire 32 1 value [31:0] $end $upscope $end $upscope $end $scope module intf_in_sub_all $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 - value [31:0] $end $scope module the_struct $end $var wire 32 . val100 [31:0] $end $var wire 32 / val200 [31:0] $end $upscope $end $scope module inner $end $var wire 32 # cyc [31:0] $end $var wire 32 4 value [31:0] $end $upscope $end $upscope $end $scope module ac1 $end $scope module intf_for_check $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 ' value [31:0] $end $scope module the_struct $end $var wire 32 ( val100 [31:0] $end $var wire 32 ) val200 [31:0] $end $upscope $end $scope module inner $end $var wire 32 # cyc [31:0] $end $var wire 32 2 value [31:0] $end $upscope $end $upscope $end $upscope $end $scope module ac2 $end $scope module intf_for_check $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 $ value [31:0] $end $scope module the_struct $end $var wire 32 % val100 [31:0] $end $var wire 32 & val200 [31:0] $end $upscope $end $scope module inner $end $var wire 32 # cyc [31:0] $end $var wire 32 1 value [31:0] $end $upscope $end $upscope $end $upscope $end $scope module ac3 $end $scope module intf_for_check $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 - value [31:0] $end $scope module the_struct $end $var wire 32 . val100 [31:0] $end $var wire 32 / val200 [31:0] $end $upscope $end $scope module inner $end $var wire 32 # cyc [31:0] $end $var wire 32 4 value [31:0] $end $upscope $end $upscope $end $upscope $end $scope module as3 $end $scope module intf_for_struct $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 - value [31:0] $end $scope module the_struct $end $var wire 32 . val100 [31:0] $end $var wire 32 / val200 [31:0] $end $upscope $end $scope module inner $end $var wire 32 # cyc [31:0] $end $var wire 32 4 value [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module s1 $end $scope module intf_for_struct $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 $ value [31:0] $end $scope module the_struct $end $var wire 32 % val100 [31:0] $end $var wire 32 & val200 [31:0] $end $upscope $end $scope module inner $end $var wire 32 # cyc [31:0] $end $var wire 32 1 value [31:0] $end $upscope $end $upscope $end $upscope $end $scope module s2 $end $scope module intf_for_struct $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 ' value [31:0] $end $scope module the_struct $end $var wire 32 ( val100 [31:0] $end $var wire 32 ) val200 [31:0] $end $upscope $end $scope module inner $end $var wire 32 # cyc [31:0] $end $var wire 32 2 value [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 b00000000000000000000000000000000 # b00000000000000000000000000000001 $ b00000000000000000000000001100101 % b00000000000000000000000011001001 & b00000000000000000000000000000010 ' b00000000000000000000000001100110 ( b00000000000000000000000011001010 ) b00000000000000000000001111101001 * b00000000000000000000010001001101 + b00000000000000000000010010110001 , b00000000000000000000001111101010 - b00000000000000000000010001001110 . b00000000000000000000010010110010 / 00 b00000000000000000000000000000000 1 b00000000000000000000000000000000 2 b00000000000000000000000000000000 3 b00000000000000000000000000000000 4 #10 b00000000000000000000000000000001 # b00000000000000000000000000000010 $ b00000000000000000000000001100110 % b00000000000000000000000011001010 & b00000000000000000000000000000011 ' b00000000000000000000000001100111 ( b00000000000000000000000011001011 ) b00000000000000000000001111101010 * b00000000000000000000010001001110 + b00000000000000000000010010110010 , b00000000000000000000001111101011 - b00000000000000000000010001001111 . b00000000000000000000010010110011 / 10 #15 00 #20 b00000000000000000000000000000010 # b00000000000000000000000000000011 $ b00000000000000000000000001100111 % b00000000000000000000000011001011 & b00000000000000000000000000000100 ' b00000000000000000000000001101000 ( b00000000000000000000000011001100 ) b00000000000000000000001111101011 * b00000000000000000000010001001111 + b00000000000000000000010010110011 , b00000000000000000000001111101100 - b00000000000000000000010001010000 . b00000000000000000000010010110100 / 10 #25 00 #30 b00000000000000000000000000000011 # b00000000000000000000000000000100 $ b00000000000000000000000001101000 % b00000000000000000000000011001100 & b00000000000000000000000000000101 ' b00000000000000000000000001101001 ( b00000000000000000000000011001101 ) b00000000000000000000001111101100 * b00000000000000000000010001010000 + b00000000000000000000010010110100 , b00000000000000000000001111101101 - b00000000000000000000010001010001 . b00000000000000000000010010110101 / 10 #35 00 #40 b00000000000000000000000000000100 # b00000000000000000000000000000101 $ b00000000000000000000000001101001 % b00000000000000000000000011001101 & b00000000000000000000000000000110 ' b00000000000000000000000001101010 ( b00000000000000000000000011001110 ) b00000000000000000000001111101101 * b00000000000000000000010001010001 + b00000000000000000000010010110101 , b00000000000000000000001111101110 - b00000000000000000000010001010010 . b00000000000000000000010010110110 / 10 #45 00 #50 b00000000000000000000000000000101 # b00000000000000000000000000000110 $ b00000000000000000000000001101010 % b00000000000000000000000011001110 & b00000000000000000000000000000111 ' b00000000000000000000000001101011 ( b00000000000000000000000011001111 ) b00000000000000000000001111101110 * b00000000000000000000010001010010 + b00000000000000000000010010110110 , b00000000000000000000001111101111 - b00000000000000000000010001010011 . b00000000000000000000010010110111 / 10 #55 00 #60 b00000000000000000000000000000110 # b00000000000000000000000000000111 $ b00000000000000000000000001101011 % b00000000000000000000000011001111 & b00000000000000000000000000001000 ' b00000000000000000000000001101100 ( b00000000000000000000000011010000 ) b00000000000000000000001111101111 * b00000000000000000000010001010011 + b00000000000000000000010010110111 , b00000000000000000000001111110000 - b00000000000000000000010001010100 . b00000000000000000000010010111000 / 10 #65 00 #70 b00000000000000000000000000000111 # b00000000000000000000000000001000 $ b00000000000000000000000001101100 % b00000000000000000000000011010000 & b00000000000000000000000000001001 ' b00000000000000000000000001101101 ( b00000000000000000000000011010001 ) b00000000000000000000001111110000 * b00000000000000000000010001010100 + b00000000000000000000010010111000 , b00000000000000000000001111110001 - b00000000000000000000010001010101 . b00000000000000000000010010111001 / 10 #75 00 #80 b00000000000000000000000000001000 # b00000000000000000000000000001001 $ b00000000000000000000000001101101 % b00000000000000000000000011010001 & b00000000000000000000000000001010 ' b00000000000000000000000001101110 ( b00000000000000000000000011010010 ) b00000000000000000000001111110001 * b00000000000000000000010001010101 + b00000000000000000000010010111001 , b00000000000000000000001111110010 - b00000000000000000000010001010110 . b00000000000000000000010010111010 / 10 #85 00 #90 b00000000000000000000000000001001 # b00000000000000000000000000001010 $ b00000000000000000000000001101110 % b00000000000000000000000011010010 & b00000000000000000000000000001011 ' b00000000000000000000000001101111 ( b00000000000000000000000011010011 ) b00000000000000000000001111110010 * b00000000000000000000010001010110 + b00000000000000000000010010111010 , b00000000000000000000001111110011 - b00000000000000000000010001010111 . b00000000000000000000010010111011 / 10 #95 00 #100 b00000000000000000000000000001010 # b00000000000000000000000000001011 $ b00000000000000000000000001101111 % b00000000000000000000000011010011 & b00000000000000000000000000001100 ' b00000000000000000000000001110000 ( b00000000000000000000000011010100 ) b00000000000000000000001111110011 * b00000000000000000000010001010111 + b00000000000000000000010010111011 , b00000000000000000000001111110100 - b00000000000000000000010001011000 . b00000000000000000000010010111100 / 10 #105 00 #110 b00000000000000000000000000001011 # b00000000000000000000000000001100 $ b00000000000000000000000001110000 % b00000000000000000000000011010100 & b00000000000000000000000000001101 ' b00000000000000000000000001110001 ( b00000000000000000000000011010101 ) b00000000000000000000001111110100 * b00000000000000000000010001011000 + b00000000000000000000010010111100 , b00000000000000000000001111110101 - b00000000000000000000010001011001 . b00000000000000000000010010111101 / 10 #115 00 #120 b00000000000000000000000000001100 # b00000000000000000000000000001101 $ b00000000000000000000000001110001 % b00000000000000000000000011010101 & b00000000000000000000000000001110 ' b00000000000000000000000001110010 ( b00000000000000000000000011010110 ) b00000000000000000000001111110101 * b00000000000000000000010001011001 + b00000000000000000000010010111101 , b00000000000000000000001111110110 - b00000000000000000000010001011010 . b00000000000000000000010010111110 / 10 #125 00 #130 b00000000000000000000000000001101 # b00000000000000000000000000001110 $ b00000000000000000000000001110010 % b00000000000000000000000011010110 & b00000000000000000000000000001111 ' b00000000000000000000000001110011 ( b00000000000000000000000011010111 ) b00000000000000000000001111110110 * b00000000000000000000010001011010 + b00000000000000000000010010111110 , b00000000000000000000001111110111 - b00000000000000000000010001011011 . b00000000000000000000010010111111 / 10 #135 00 #140 b00000000000000000000000000001110 # b00000000000000000000000000001111 $ b00000000000000000000000001110011 % b00000000000000000000000011010111 & b00000000000000000000000000010000 ' b00000000000000000000000001110100 ( b00000000000000000000000011011000 ) b00000000000000000000001111110111 * b00000000000000000000010001011011 + b00000000000000000000010010111111 , b00000000000000000000001111111000 - b00000000000000000000010001011100 . b00000000000000000000010011000000 / 10 #145 00 #150 b00000000000000000000000000001111 # b00000000000000000000000000010000 $ b00000000000000000000000001110100 % b00000000000000000000000011011000 & b00000000000000000000000000010001 ' b00000000000000000000000001110101 ( b00000000000000000000000011011001 ) b00000000000000000000001111111000 * b00000000000000000000010001011100 + b00000000000000000000010011000000 , b00000000000000000000001111111001 - b00000000000000000000010001011101 . b00000000000000000000010011000001 / 10 #155 00 #160 b00000000000000000000000000010000 # b00000000000000000000000000010001 $ b00000000000000000000000001110101 % b00000000000000000000000011011001 & b00000000000000000000000000010010 ' b00000000000000000000000001110110 ( b00000000000000000000000011011010 ) b00000000000000000000001111111001 * b00000000000000000000010001011101 + b00000000000000000000010011000001 , b00000000000000000000001111111010 - b00000000000000000000010001011110 . b00000000000000000000010011000010 / 10 #165 00 #170 b00000000000000000000000000010001 # b00000000000000000000000000010010 $ b00000000000000000000000001110110 % b00000000000000000000000011011010 & b00000000000000000000000000010011 ' b00000000000000000000000001110111 ( b00000000000000000000000011011011 ) b00000000000000000000001111111010 * b00000000000000000000010001011110 + b00000000000000000000010011000010 , b00000000000000000000001111111011 - b00000000000000000000010001011111 . b00000000000000000000010011000011 / 10 #175 00 #180 b00000000000000000000000000010010 # b00000000000000000000000000010011 $ b00000000000000000000000001110111 % b00000000000000000000000011011011 & b00000000000000000000000000010100 ' b00000000000000000000000001111000 ( b00000000000000000000000011011100 ) b00000000000000000000001111111011 * b00000000000000000000010001011111 + b00000000000000000000010011000011 , b00000000000000000000001111111100 - b00000000000000000000010001100000 . b00000000000000000000010011000100 / 10 #185 00 #190 b00000000000000000000000000010011 # b00000000000000000000000000010100 $ b00000000000000000000000001111000 % b00000000000000000000000011011100 & b00000000000000000000000000010101 ' b00000000000000000000000001111001 ( b00000000000000000000000011011101 ) b00000000000000000000001111111100 * b00000000000000000000010001100000 + b00000000000000000000010011000100 , b00000000000000000000001111111101 - b00000000000000000000010001100001 . b00000000000000000000010011000101 / 10 #195 00 #200 b00000000000000000000000000010100 # b00000000000000000000000000010101 $ b00000000000000000000000001111001 % b00000000000000000000000011011101 & b00000000000000000000000000010110 ' b00000000000000000000000001111010 ( b00000000000000000000000011011110 ) b00000000000000000000001111111101 * b00000000000000000000010001100001 + b00000000000000000000010011000101 , b00000000000000000000001111111110 - b00000000000000000000010001100010 . b00000000000000000000010011000110 / 10 #205 00 #210 b00000000000000000000000000010101 # b00000000000000000000000000010110 $ b00000000000000000000000001111010 % b00000000000000000000000011011110 & b00000000000000000000000000010111 ' b00000000000000000000000001111011 ( b00000000000000000000000011011111 ) b00000000000000000000001111111110 * b00000000000000000000010001100010 + b00000000000000000000010011000110 , b00000000000000000000001111111111 - b00000000000000000000010001100011 . b00000000000000000000010011000111 / 10 verilator-5.042/test_regress/t/t_queue_init.v0000644000542200017500000000153615101701376021754 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module t; int a1[$] = '{12, 13}; int a2[$] = {14, 15}; int a3[$] = '{16}; int a4[$] = {17}; initial begin `checkh(a1.size, 2); `checkh(a1[0], 12); `checkh(a1[1], 13); `checkh(a2.size, 2); `checkh(a2[0], 14); `checkh(a2[1], 15); `checkh(a3.size, 1); `checkh(a3[0], 16); `checkh(a4.size, 1); `checkh(a4[0], 17); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_interface_gen.py0000755000542200017500000000073415101701376022563 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_event_control_star_never.v0000644000542200017500000000047515101701376024717 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; int a; always @* a = 100; initial begin #1; if (a != 0) $stop; end endmodule verilator-5.042/test_regress/t/t_implements_contents_bad.out0000644000542200017500000000071715101701376025047 0ustar mahmoudyfreeshell%Error: t/t_implements_contents_bad.v:8:8: Interface class cannot contain non-parameter members (IEEE 1800-2023 8.26): 'badi' 8 | int badi; | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_implements_contents_bad.v:9:9: Interface class functions must be pure virtual (IEEE 1800-2023 8.26): 'badtask' 9 | task badtask; | ^~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_flag_x_initial_bad.py0000755000542200017500000000106115101701376023543 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--x-initial bad_one"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_implements_collision_bad.out0000644000542200017500000000163615101701376025206 0ustar mahmoudyfreeshell%Error: t/t_implements_collision_bad.v:15:11: Class 'IclsBoth' implements 'Icls2' but missing inheritance conflict resolution for 'icfboth' (IEEE 1800-2023 8.26.6.2) 15 | interface class IclsBoth extends Icls1, Icls2; | ^~~~~ t/t_implements_collision_bad.v:12:30: ... Location of interface class's function 12 | pure virtual function int icfboth; | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_implements_collision_bad.v:19:1: Class 'Cls' implements 'IclsBoth' but is missing implementation for 'icfboth' (IEEE 1800-2023 8.26) 19 | class Cls implements IclsBoth; | ^~~~~ t/t_implements_collision_bad.v:8:30: ... Location of interface class's function 8 | pure virtual function int icfboth; | ^~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_inst_nansi_dup_bad.v0000644000542200017500000000071715101701376023430 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef int T; module test ( /*AUTOARG*/ // Outputs bad4, bad5 ); output bad4; reg bad4; reg bad4; // <--- Error (duplicate) output bad5; output bad5; // <--- Error (duplicate) reg bad5; // <--- Error (duplicate) endmodule verilator-5.042/test_regress/t/t_event_control_expr.v0000644000542200017500000001210415101701376023515 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `ifdef TEST_VERBOSE `define WRITE_VERBOSE(args) $write args `else `define WRITE_VERBOSE(args) `endif `define STRINGIFY(text) `"text`" //======================================================================== // Various expression tests. The macro generates a module with the desired // input and tested expression. // `define EXPR_TEST(name, test_edges, inputs, expr) \ module t_``name inputs; \ logic[$bits(expr)-1:0] last = 0; \ always @(expr) begin \ if ($bits(expr) > 1) begin \ `WRITE_VERBOSE(("[%0t] %s [changed] %s=%0x, last=%0x\n", $time, `STRINGIFY(name), `STRINGIFY(expr), expr, last)); \ end \ if ($time > 0 && (expr) == last) $stop; \ last <= expr; \ end \ generate if (test_edges) begin \ always @(posedge expr) begin \ `WRITE_VERBOSE(("[%0t] %s [posedge] %s=%0x, last=%0x\n", $time, `STRINGIFY(name), `STRINGIFY(expr), expr, last)); \ if ($time > 0 && ({1'b0, ~(expr)}[0] || last[0])) $stop; \ end \ always @(negedge expr) begin \ `WRITE_VERBOSE(("[%0t] %s [negedge] %s=%0x, last=%0x\n", $time, `STRINGIFY(name), `STRINGIFY(expr), expr, last)); \ if ($time > 0 && ({1'b0, expr}[0] || ~last[0])) $stop; \ end \ end endgenerate \ endmodule `EXPR_TEST(xor, 1, (input a, b), b^a) `EXPR_TEST(nand, 1, (input a, b, c), ~(c&b&a)) `EXPR_TEST(concat1, 1, (input a, b, c), {{a, b},c,a,{2{a,b,c}}}) `EXPR_TEST(reduce, 1, (input[3:0] v), v[0]^v[1]^v[2]^v[3]) `EXPR_TEST(concat2, 1, (input[3:0] v), {{v[0]|v[1]},v[1]|v[2],{4{v[2]|v[3]}}}) `EXPR_TEST(add, 0, (input int i, j), i+j) `EXPR_TEST(lt, 1, (input int i, j), i 0 && expr == last) $stop; \ last <= expr; \ end \ endmodule `CLASS_TEST(class, obj.k) `CLASS_TEST(method, obj.get_k()) `endif //======================================================================== // $c test has to be written out explicitly as the STRINGIFY macro can't handle it // module t_cstmt; logic last = 0; always @($c("vlSymsp->TOP.clk")) begin if ($time > 0 && logic'($c("vlSymsp->TOP.clk")) == last) $stop; last <= logic'($c("vlSymsp->TOP.clk")); end always @(posedge $c("vlSymsp->TOP.clk")) begin `WRITE_VERBOSE(("[%0t] cstmt [posedge] $c(\"vlSymsp->TOP.clk\")=%0b, last=%b\n", $time, $c("vlSymsp->TOP.clk"), last)); if ($time > 0 && (~logic'($c("vlSymsp->TOP.clk")) || last)) $stop; end always @(negedge $c("vlSymsp->TOP.clk")) begin `WRITE_VERBOSE(("[%0t] cstmt [negedge] $c(\"vlSymsp->TOP.clk\")=%0b, last=%b\n", $time, $c("vlSymsp->TOP.clk"), last)); if ($time > 0 && (logic'($c("vlSymsp->TOP.clk")) || !last)) $stop; end endmodule module t(/*AUTOARG*/ // Inputs clk ); input clk; logic a = 0, b = 0, c = 0; t_xor u_xor(.*); t_nand u_nand(.*); t_concat1 u_concat1(.*); logic[3:0] v = '0; t_reduce u_reduce(.*); t_concat2 u_concat2(.*); int i = 0, j = 0; t_add u_add(.*); t_lt u_lt(.*); int t[5] = {0, 1, 2, 3, 4}; t_array u_array(.*); t_array_complex u_array_complex(.*); int q[$]; t_queue u_queue(.*); t_queue_mul u_queue_mul(.*); t_func u_func(.*); int k; assign k = i + j; `ifndef NO_CLASS t_class u_class(.*); t_method u_method(.*); `endif t_cstmt u_cstmt(); int cyc = 0; always @(posedge clk) begin cyc <= cyc + 1; // a, b, c a <= ~a; if (cyc % 2 == 0) b <= ~b; else c <= ~c; // v if (cyc % 3 == 0) v[0] <= 1; else v <= v << 1; // i, j i <= i + 2; if (cyc % 2 == 0) j <= j + 4; // t t[cyc % 5] <= t[cyc % 5] + cyc; // q q.push_front(cyc); `WRITE_VERBOSE(("[%0t] values: clk=%b, cyc=%0d, a=%b, b=%b, v=%b, i=%0x, j=%0x, t=[%0x, %0x, %0x, %0x, %0x], obj.k=%0x\n", $time, clk, cyc, a, b, v, i, j, t[0], t[1], t[2], t[3], t[4], k)); `WRITE_VERBOSE((" q=%p\n", q)); if (cyc == 20) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_constraint_pure_nonabs_bad.py0000755000542200017500000000076315101701376025361 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_trace_two_hdr_cc.out0000644000542200017500000000363515101701376023442 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module topa $end $var wire 1 # clk $end $scope module t $end $var wire 1 # clk $end $var wire 32 $ cyc [31:0] $end $var wire 32 % c_trace_on [31:0] $end $scope module sub $end $var wire 32 & inside_sub_a [31:0] $end $upscope $end $upscope $end $upscope $end $scope module topb $end $var wire 1 ( clk $end $scope module t $end $var wire 1 ( clk $end $var wire 32 + cyc [31:0] $end $var wire 32 , c_trace_on [31:0] $end $var real 64 ) r $end $scope module sub $end $var wire 32 - inside_sub_a [31:0] $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 0# b00000000000000000000000000000001 $ b00000000000000000000000000000000 % 0( r0 ) b00000000000000000000000000000001 & b00000000000000000000000000000001 + b00000000000000000000000000000000 , b00000000000000000000000000000010 - #10 1# b00000000000000000000000000000010 $ b00000000000000000000000000000011 % 1( r0.1 ) #15 0# 0( #20 1# b00000000000000000000000000000011 $ b00000000000000000000000000000100 % 1( r0.2 ) #25 0# 0( #30 1# b00000000000000000000000000000100 $ b00000000000000000000000000000101 % 1( r0.3 ) #35 0# 0( #40 1# b00000000000000000000000000000101 $ b00000000000000000000000000000110 % 1( r0.4 ) #45 0# 0( #50 1# b00000000000000000000000000000110 $ b00000000000000000000000000000111 % 1( r0.5 ) #55 0# 0( #60 1# b00000000000000000000000000000111 $ b00000000000000000000000000001000 % 1( r0.6 ) #65 0# 0( #70 1# b00000000000000000000000000001000 $ b00000000000000000000000000001001 % 1( r0.7 ) #75 0# 0( #80 1# b00000000000000000000000000001001 $ b00000000000000000000000000001010 % 1( r0.7999999999999999 ) #85 0# 0( #90 1# b00000000000000000000000000001010 $ b00000000000000000000000000001011 % 1( r0.8999999999999999 ) #95 0# 0( #100 1# b00000000000000000000000000001011 $ b00000000000000000000000000001100 % 1( r0.9999999999999999 ) verilator-5.042/test_regress/t/t_timing_dpi_unsup.out0000644000542200017500000000045015101701376023516 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_timing_dpi_unsup.v:28:19: Unsupported: Timing controls inside DPI-exported tasks 28 | repeat(n) @(negedge clk); | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_cpure.v0000644000542200017500000000076615101701376020727 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias' // // Simple bi-directional transitive alias test. // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 function int func(); static int someVar = 12; return $cpure(someVar, "+ 6"); endfunction module t; initial begin if (func() != 18) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_typedef_port.py0000755000542200017500000000073415101701376022476 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_virtual_sched_act.out0000644000542200017500000000013315101701376025642 0ustar mahmoudyfreeshell[0] data==0000 [20000] data==dead [30000] data==beef [40000] data==face [50000] data==cafe verilator-5.042/test_regress/t/t_inst_misarray_bad.out0000644000542200017500000000067315101701376023642 0ustar mahmoudyfreeshell%Error: t/t_inst_misarray_bad.v:17:23: Illegal input port connection 'foo', mismatch between port which is an array, and expression which is not an array. (IEEE 1800-2023 7.6) : ... note: In instance 't' 17 | .foo(foo)); | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_lint_dtype_compare_bad.v0000644000542200017500000000356415101701376024277 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // DESCRIPTION: Verilator: Invalid aggregate dtype comparisons // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Shou-Li Hsu. // SPDX-License-Identifier: CC0-1.0 module t; typedef int myint_t; typedef bit mybit_t; typedef string mystr_t; typedef int myval_t; typedef logic [31:0] mylogic_t; initial begin int queue_var[$] = '{1, 2, 3}; int q1[$] = '{1, 2}; bit q2[$] = '{1'b1, 1'b0}; int d1[] = new[2]; bit d2[] = new[2]; int u1[2] = '{1, 2}; int u2[2][1] = '{{1}, {2}}; int a1[2] = '{1, 2}; int a2[3] = '{1, 2, 3}; int aa1[string]; int aa2[int]; int aa3[string]; logic [3:0] aa4[string]; myint_t bad1[2] = '{1, 2}; mybit_t bad2[2] = '{1, 0}; myval_t val1[mystr_t] = '{"foo": 123}; mylogic_t val2[string] = '{"foo": 32'h12345678}; myint_t aa5[string]; myint_t aa6[int]; aa5["a"] = 1; aa6[1] = 1; // queue vs scalar if (queue_var == 1) begin end // scalar vs queue if (1 == queue_var) begin end // queue with diff type if (q1 == q2) begin end // dyn array with diff type if (d1 == d2) begin end // unpacked diff dim if (u1 == u2) begin end // unpacked diff size if (a1 == a2) begin end // assoc array diff key type if (aa1 == aa2) begin end // assoc array diff value type if (aa3 == aa4) begin end // typedef mismatch in unpacked array if (bad1 == bad2) begin end // typedef mismatch in assoc array value if (val1 == val2) begin end // typedef mismatch in assoc array key if (aa5 == aa6) begin end end endmodule verilator-5.042/test_regress/t/t_inside_queue_elem.py0000755000542200017500000000073415101701376023453 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_genfor_signed.py0000755000542200017500000000100015101701376022566 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface_find.v0000644000542200017500000000160215101701376022537 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Auto-resolved by t_interface_find_ifc.v // interface t_interface_find_ifc; module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=1; t_interface_find_ifc itop(); sub c1 (.isub(itop), .i_value(4'h4)); always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==20) begin if (c1.i_value != 4) $stop; // 'Normal' crossref just for comparison if (itop.value != 4) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module sub ( t_interface_find_ifc isub, input logic [3:0] i_value ); always @* begin isub.value = i_value; end endmodule : sub verilator-5.042/test_regress/t/t_module_class_static_method.v0000644000542200017500000000073315101701376025164 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // module t; class Cls; static function int static_task(); return 42; endfunction endclass : Cls initial begin if (Cls::static_task() != 42) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_sys_fmonitor.out0000644000542200017500000000043415101701376022676 0ustar mahmoudyfreeshell[110] cyc=11 also [120] cyc=12 also [130] cyc=13 also [140] cyc=14 also [150] cyc=15 also [160] cyc=16 also [170] cyc=17 also 00000000000000000000000000010010b 00000013h 00000000024o 00000000025o 00000000026o [230] cyc=23 new-monitor [240] cyc=24 new-monitor [270] cyc=27 new-monitor verilator-5.042/test_regress/t/t_alw_split_rst.v0000644000542200017500000000753615101701376022501 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [3:0] in = crc[3:0]; wire clken = crc[4]; wire rstn = !(cyc < 20 || (crc[11:8]==0)); /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [3:0] ff_out; // From test of Test.v wire [3:0] fg_out; // From test of Test.v wire [3:0] fh_out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .ff_out (ff_out[3:0]), .fg_out (fg_out[3:0]), .fh_out (fh_out[3:0]), // Inputs .clk (clk), .clken (clken), .rstn (rstn), .in (in[3:0])); // Aggregate outputs into a single result vector wire [63:0] result = {52'h0, ff_out, fg_out, fh_out}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x rstn=%x\n", $time, cyc, crc, result, rstn); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc == 0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc < 10) begin sum <= '0; end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h77979747fd86e9fd if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs ff_out, fg_out, fh_out, // Inputs clk, clken, rstn, in ); input clk; input clken; input rstn; input [3:0] in; output reg [3:0] ff_out; reg [3:0] ff_10; reg [3:0] ff_11; reg [3:0] ff_12; reg [3:0] ff_13; always @(posedge clk) begin if ((rstn == 0)) begin ff_10 <= 0; ff_11 <= 0; ff_12 <= 0; ff_13 <= 0; ff_out <= 0; end else begin ff_10 <= in; ff_11 <= ff_10; ff_12 <= ff_11; ff_13 <= ff_12; ff_out <= ff_13; end end output reg [3:0] fg_out; reg [3:0] fg_10; reg [3:0] fg_11; reg [3:0] fg_12; reg [3:0] fg_13; always @(posedge clk) begin if (clken) begin if ((rstn == 0)) begin fg_10 <= 0; fg_11 <= 0; fg_12 <= 0; fg_13 <= 0; fg_out <= 0; end else begin fg_10 <= in; fg_11 <= fg_10; fg_12 <= fg_11; fg_13 <= fg_12; fg_out <= fg_13; end end end output reg [3:0] fh_out; reg [3:0] fh_10; reg [3:0] fh_11; reg [3:0] fh_12; reg [3:0] fh_13; always @(posedge clk) begin if ((rstn == 0)) begin fh_10 <= 0; fh_11 <= 0; fh_12 <= 0; fh_13 <= 0; fh_out <= 0; end else begin if (clken) begin fh_10 <= in; fh_11 <= fh_10; fh_12 <= fh_11; fh_13[3:1] <= fh_12[3:1]; fh_13[0] <= fh_12[0]; fh_out <= fh_13; end end end endmodule verilator-5.042/test_regress/t/t_lint_always_comb_bad.v0000644000542200017500000000163015101701376023734 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs mid, o3, // Inputs clk, i3 ); input clk; output logic mid; input i3; output logic o3; wire [15:0] temp1; wire [15:0] temp1_d1r; logic setbefore; always_comb begin setbefore = 1'b1; if (setbefore) setbefore = 1'b0; // fine end always_comb begin if (mid) temp1 = 'h0; else temp1 = (temp1_d1r - 'h1); mid = (temp1_d1r == 'h0); // BAD end always_comb begin o3 = 'h0; case (i3) 1'b1: begin o3 = i3; end default: ; endcase end always_ff @ (posedge clk) begin temp1_d1r <= temp1; end endmodule verilator-5.042/test_regress/t/t_mem_multi_io2_sc.py0000755000542200017500000000126215101701376023215 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_mem_multi_io2.cpp" test.top_filename = "t/t_mem_multi_io2.v" test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename, "--sc -fno-inline"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_preproc_inc_fn_bad.v0000644000542200017500000000037215101701376023376 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `include `else module t; endmodule verilator-5.042/test_regress/t/t_wait_fork.py0000755000542200017500000000076615101701376021764 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_inside_wild.py0000755000542200017500000000073415101701376022264 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_array_pattern_bad3.v0000644000542200017500000000101715101701376023343 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // bug1364 module t (/*AUTOARG*/ // Inputs clk, res ); input clk; input res; int arr[3]; initial begin arr = '{default: '0, 1: '0, 1: '1}; // Bad arr = '{'0, '1, '0, '1}; // Bad, too many arr = '{'0, '1}; // Bad, too few end endmodule verilator-5.042/test_regress/t/t_interface_array_parameter_access.v0000644000542200017500000000165615101701376026327 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Get parameter from array of interfaces // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2024 by Todd Strader // SPDX-License-Identifier: CC0-1.0 interface intf #(parameter int FOO = 4) (input wire clk, input wire rst); modport modp (input clk, rst); endinterface module sub (intf.modp the_intf_port [4], intf.modp single_intf_port); localparam intf_foo = the_intf_port[0].FOO; localparam single_foo = single_intf_port.FOO; initial begin if (intf_foo != 4) $stop; if (single_foo != 4) $stop; end endmodule module t ( clk ); logic rst; input clk; intf the_intf [4] (.*); intf single_intf (.*); sub the_sub ( .the_intf_port (the_intf), .single_intf_port(single_intf) ); always @(posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_lint_implicit_func_bad.py0000755000542200017500000000110115101701376024440 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_case_huge.py0000755000542200017500000000163415101701376021715 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--stats"]) test.execute() if test.vlt: test.file_grep(test.stats, r'Optimizations, Cases parallelized\s+(\d+)', 11) test.file_grep(test.stats, r'Optimizations, Combined CFuncs\s+(\d+)', 8) test.file_grep(test.stats, r'Optimizations, Tables created\s+(\d+)', 10) elif test.vltmt: test.file_grep(test.stats, r'Optimizations, Combined CFuncs\s+(\d+)', 9) test.file_grep(test.stats, r'Optimizations, Tables created\s+(\d+)', 10) test.passes() verilator-5.042/test_regress/t/t_gen_inc.v0000644000542200017500000001347215101701376021211 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; genvar g; integer i; reg [31:0] v; reg [31:0] gen_pre_PLUSPLUS = 32'h0; reg [31:0] gen_pre_MINUSMINUS = 32'h0; reg [31:0] gen_post_PLUSPLUS = 32'h0; reg [31:0] gen_post_MINUSMINUS = 32'h0; reg [31:0] gen_PLUSEQ = 32'h0; reg [31:0] gen_MINUSEQ = 32'h0; reg [31:0] gen_TIMESEQ = 32'h0; reg [31:0] gen_DIVEQ = 32'h0; reg [31:0] gen_MODEQ = 32'h0; reg [31:0] gen_ANDEQ = 32'h0; reg [31:0] gen_OREQ = 32'h0; reg [31:0] gen_XOREQ = 32'h0; reg [31:0] gen_SLEFTEQ = 32'h0; reg [31:0] gen_SRIGHTEQ = 32'h0; reg [31:0] gen_SSRIGHTEQ = 32'h0; generate for (g=8; g<=16; ++g) always @(posedge clk) gen_pre_PLUSPLUS[g] = 1'b1; for (g=16; g>=8; --g) always @(posedge clk) gen_pre_MINUSMINUS[g] = 1'b1; for (g=8; g<=16; g++) always @(posedge clk) gen_post_PLUSPLUS[g] = 1'b1; for (g=16; g>=8; g--) always @(posedge clk) gen_post_MINUSMINUS[g] = 1'b1; for (g=8; g<=16; g+=2) always @(posedge clk) gen_PLUSEQ[g] = 1'b1; for (g=16; g>=8; g-=2) always @(posedge clk) gen_MINUSEQ[g] = 1'b1; for (g=8; g<=16; g*=2) always @(posedge clk) gen_TIMESEQ[g] = 1'b1; for (g=16; g>=8; g/=2) always @(posedge clk) gen_DIVEQ[g] = 1'b1; for (g=15; g>8; g%=8) always @(posedge clk) gen_MODEQ[g] = 1'b1; for (g=7; g>4; g&=4) always @(posedge clk) gen_ANDEQ[g] = 1'b1; for (g=1; g<=1; g|=2) always @(posedge clk) gen_OREQ[g] = 1'b1; for (g=7; g==7; g^=2) always @(posedge clk) gen_XOREQ[g] = 1'b1; for (g=8; g<=16; g<<=2) always @(posedge clk) gen_SLEFTEQ[g] = 1'b1; for (g=16; g>=8; g>>=2) always @(posedge clk) gen_SRIGHTEQ[g] = 1'b1; for (g=16; g>=8; g>>>=2) always @(posedge clk) gen_SSRIGHTEQ[g] = 1'b1; endgenerate always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 3) begin `ifdef TEST_VERBOSE $write("gen_pre_PLUSPLUS %b\n", gen_pre_PLUSPLUS); $write("gen_pre_MINUSMINUS %b\n", gen_pre_MINUSMINUS); $write("gen_post_PLUSPLUS %b\n", gen_post_PLUSPLUS); $write("gen_post_MINUSMINUS %b\n", gen_post_MINUSMINUS); $write("gen_PLUSEQ %b\n", gen_PLUSEQ); $write("gen_MINUSEQ %b\n", gen_MINUSEQ); $write("gen_TIMESEQ %b\n", gen_TIMESEQ); $write("gen_DIVEQ %b\n", gen_DIVEQ); $write("gen_MODEQ %b\n", gen_MODEQ); $write("gen_ANDEQ %b\n", gen_ANDEQ); $write("gen_OREQ %b\n", gen_OREQ); $write("gen_XOREQ %b\n", gen_XOREQ); $write("gen_SLEFTEQ %b\n", gen_SLEFTEQ); $write("gen_SRIGHTEQ %b\n", gen_SRIGHTEQ); $write("gen_SSRIGHTEQ %b\n", gen_SSRIGHTEQ); `endif if (gen_pre_PLUSPLUS !== 32'b00000000000000011111111100000000) $stop; if (gen_pre_MINUSMINUS !== 32'b00000000000000011111111100000000) $stop; if (gen_post_PLUSPLUS !== 32'b00000000000000011111111100000000) $stop; if (gen_post_MINUSMINUS!== 32'b00000000000000011111111100000000) $stop; if (gen_PLUSEQ !== 32'b00000000000000010101010100000000) $stop; if (gen_MINUSEQ !== 32'b00000000000000010101010100000000) $stop; if (gen_TIMESEQ !== 32'b00000000000000010000000100000000) $stop; if (gen_DIVEQ !== 32'b00000000000000010000000100000000) $stop; if (gen_MODEQ !== 32'b00000000000000001000000000000000) $stop; if (gen_ANDEQ !== 32'b00000000000000000000000010000000) $stop; if (gen_OREQ !== 32'b00000000000000000000000000000010) $stop; if (gen_XOREQ !== 32'b00000000000000000000000010000000) $stop; if (gen_SLEFTEQ !== 32'b00000000000000000000000100000000) $stop; if (gen_SRIGHTEQ !== 32'b00000000000000010000000000000000) $stop; if (gen_SSRIGHTEQ !== 32'b00000000000000010000000000000000) $stop; v=0; for (i=8; i<=16; ++i) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop; v=0; for (i=16; i>=8; --i) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop; v=0; for (i=8; i<=16; i++) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop; v=0; for (i=16; i>=8; i--) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop; v=0; for (i=8; i<=16; i+=2) v[i] = 1'b1; if (v !== 32'b00000000000000010101010100000000) $stop; v=0; for (i=16; i>=8; i-=2) v[i] = 1'b1; if (v !== 32'b00000000000000010101010100000000) $stop; v=0; for (i=8; i<=16; i*=2) v[i] = 1'b1; if (v !== 32'b00000000000000010000000100000000) $stop; v=0; for (i=16; i>=8; i/=2) v[i] = 1'b1; if (v !== 32'b00000000000000010000000100000000) $stop; v=0; for (i=15; i>8; i%=8) v[i] = 1'b1; if (v !== 32'b00000000000000001000000000000000) $stop; v=0; for (i=7; i>4; i&=4) v[i] = 1'b1; if (v !== 32'b00000000000000000000000010000000) $stop; v=0; for (i=1; i<=1; i|=2) v[i] = 1'b1; if (v !== 32'b00000000000000000000000000000010) $stop; v=0; for (i=7; i==7; i^=2) v[i] = 1'b1; if (v !== 32'b00000000000000000000000010000000) $stop; v=0; for (i=8; i<=16; i<<=2) v[i] =1'b1; if (v !== 32'b00000000000000000000000100000000) $stop; v=0; for (i=16; i>=8; i>>=2) v[i] =1'b1; if (v !== 32'b00000000000000010000000000000000) $stop; v=0; for (i=16; i>=8; i>>>=2) v[i]=1'b1; if (v !== 32'b00000000000000010000000000000000) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_inst_array_bad.py0000755000542200017500000000076615101701376022760 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_waiveroutput.v0000644000542200017500000000074415101701376022363 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t_waiveroutput; reg width_warn = 2'b11; // Width warning - must be line 8 // verilator lint_off UNUSEDSIGNAL // verilator lint_off WIDTHTRUNC reg width_warn2 = 2'b11; // verilator lint_on UNUSEDSIGNAL // verilator lint_on WIDTHTRUNC endmodule verilator-5.042/test_regress/t/t_package_ddecl.v0000644000542200017500000000146715101701376022336 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // See issue #474 package functions; localparam LP_PACK = 512; localparam LP_PACK_AND_MOD = 19; task check_param; $display("In %m\n"); // "In functions::check_param" if (LP_PACK_AND_MOD != 19) $stop; endtask endpackage module t (); // synthesis translate off import functions::*; // synthesis translate on localparam LP_PACK_AND_MOD = 20; initial begin // verilator lint_off STMTDLY #10; // verilator lint_on STMTDLY if (LP_PACK_AND_MOD != 20) $stop; check_param(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_dfg_3872.v0000644000542200017500000000046015101701376021023 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 module top( input wire [1:0] i, output wire [3:0] o ); assign o = 4'd2 ** i; endmodule verilator-5.042/test_regress/t/t_queue_struct.py0000755000542200017500000000073415101701376022522 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_force_release_net_trace.py0000755000542200017500000000115115101701376024606 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_force_release_net.v" test.compile(verilator_flags2=['--trace-vcd']) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_xml_output.py0000755000542200017500000000220115101701376022201 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') out_filename = test.obj_dir + "/renamed-" + test.name + ".xml" test.compile( verilator_flags2=["--no-std", "-Wno-DEPRECATED --xml-only --xml-output", out_filename], verilator_make_gmake=False, make_top_shell=False, make_main=False) test.files_identical(out_filename, test.golden_filename) for filename in test.glob_some(test.obj_dir + "/*"): if (re.search(r'\.log', filename) # Made by driver.py, not Verilator sources or re.search(r'\.status', filename) # Made by driver.py, not Verilator sources or re.search(r'renamed-', filename)): # Requested output continue test.error("%Error: Created '" + filename + "', but --xml-only shouldn't create files") test.passes() verilator-5.042/test_regress/t/t_dpi_openfirst.v0000644000542200017500000000234415101701376022450 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2017 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VERILATOR `define stop $stop `else `define stop `endif `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module t; int i_i [2:0]; int o_i [2:0]; import "DPI-C" function int dpii_failure(); import "DPI-C" function void dpii_open_i(input int i [], output int o []); reg [95:0] crc; initial begin crc = 96'h8a10a572_5aef0c8d_d70a4497; i_i[0] = crc[31:0]; i_i[1] = crc[63:32]; i_i[2] = crc[95:64]; dpii_open_i(i_i, o_i); `checkh(o_i[0], ~i_i[0]); `checkh(o_i[1], ~i_i[1]); `checkh(o_i[2], ~i_i[2]); if (dpii_failure()!=0) begin $write("%%Error: Failure in DPI tests\n"); $stop; end else begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_randomize_complex.v0000644000542200017500000000234715101701376023325 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class SubClass; rand bit [2:0] field; function new (); field = 0; endfunction endclass class MyClass; SubClass sc_inst2; function new (); sc_inst2 = new; endfunction endclass; class Deep; MyClass sc_inst1; function new (); sc_inst1 = new; endfunction endclass; class WeNeedToGoDeeper; Deep sc_inst; function new (); sc_inst = new; endfunction endclass; module t; initial begin WeNeedToGoDeeper cl_inst = new; MyClass cl_inst2 = new; repeat(10) begin if (cl_inst.sc_inst.sc_inst1.sc_inst2.randomize() with {field inside {1, 2, 3};} == 0) begin $stop; end if (cl_inst.sc_inst.sc_inst1.sc_inst2.field < 1 || cl_inst.sc_inst.sc_inst1.sc_inst2.field > 3) begin $stop; end if (cl_inst2.sc_inst2.randomize() with {field inside {1, 2, 3};} == 0) begin $stop; end if (cl_inst2.sc_inst2.field < 1 || cl_inst2.sc_inst2.field > 3) begin $stop; end end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_flag_instr_count_dpi_bad.py0000755000542200017500000000113115101701376024764 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--instr-count-dpi -1"], fails=True) test.file_grep(test.compile_log_filename, "%Error: --instr-count-dpi must be non-negative: -1") test.passes() verilator-5.042/test_regress/t/t_class_local_bad.out0000644000542200017500000001433115101701376023231 0ustar mahmoudyfreeshell%Error-ENCAPSULATED: t/t_class_local_bad.v:71:20: 'm_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18) : ... note: In instance 't' 71 | bad(); if (c.m_loc != 2) $stop; | ^~~~~ t/t_class_local_bad.v:71:20: ... Location of definition 15 | local int m_loc = 2; | ^~~~~ ... For error description see https://verilator.org/warn/ENCAPSULATED?v=latest %Error-ENCAPSULATED: t/t_class_local_bad.v:72:20: 'm_prot' is hidden as 'protected' within this context (IEEE 1800-2023 8.18) : ... note: In instance 't' 72 | bad(); if (c.m_prot != 20) $stop; | ^~~~~~ t/t_class_local_bad.v:72:20: ... Location of definition 16 | protected int m_prot = 3; | ^~~~~~ %Error-ENCAPSULATED: t/t_class_local_bad.v:74:20: 'm_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18) : ... note: In instance 't' 74 | bad(); if (e.m_loc != 2) $stop; | ^~~~~ t/t_class_local_bad.v:74:20: ... Location of definition 15 | local int m_loc = 2; | ^~~~~ %Error-ENCAPSULATED: t/t_class_local_bad.v:75:20: 'm_prot' is hidden as 'protected' within this context (IEEE 1800-2023 8.18) : ... note: In instance 't' 75 | bad(); if (e.m_prot != 20) $stop; | ^~~~~~ t/t_class_local_bad.v:75:20: ... Location of definition 16 | protected int m_prot = 3; | ^~~~~~ %Error-ENCAPSULATED: t/t_class_local_bad.v:77:16: 'f_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18) : ... note: In instance 't' 77 | bad(); c.f_loc(); | ^~~~~ t/t_class_local_bad.v:77:16: ... Location of definition 18 | local task f_loc; endtask | ^~~~~ %Error-ENCAPSULATED: t/t_class_local_bad.v:78:16: 'f_prot' is hidden as 'protected' within this context (IEEE 1800-2023 8.18) : ... note: In instance 't' 78 | bad(); c.f_prot(); | ^~~~~~ t/t_class_local_bad.v:78:16: ... Location of definition 19 | protected task f_prot; endtask | ^~~~~~ %Error-ENCAPSULATED: t/t_class_local_bad.v:80:16: 's_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18) : ... note: In instance 't' 80 | bad(); c.s_loc(); | ^~~~~ t/t_class_local_bad.v:80:16: ... Location of definition 21 | static local task s_loc; endtask | ^~~~~ %Error-ENCAPSULATED: t/t_class_local_bad.v:81:16: 's_prot' is hidden as 'protected' within this context (IEEE 1800-2023 8.18) : ... note: In instance 't' 81 | bad(); c.s_prot(); | ^~~~~~ t/t_class_local_bad.v:81:16: ... Location of definition 22 | static protected task s_prot; endtask | ^~~~~~ %Error-ENCAPSULATED: t/t_class_local_bad.v:83:19: 's_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18) : ... note: In instance 't' 83 | bad(); Cls::s_loc(); | ^~~~~ t/t_class_local_bad.v:83:19: ... Location of definition 21 | static local task s_loc; endtask | ^~~~~ %Error-ENCAPSULATED: t/t_class_local_bad.v:84:19: 's_prot' is hidden as 'protected' within this context (IEEE 1800-2023 8.18) : ... note: In instance 't' 84 | bad(); Cls::s_prot(); | ^~~~~~ t/t_class_local_bad.v:84:19: ... Location of definition 22 | static protected task s_prot; endtask | ^~~~~~ %Error-ENCAPSULATED: t/t_class_local_bad.v:47:18: 'm_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18) : ... note: In instance 't' 47 | bad(); if (m_loc != 10) $stop; | ^~~~~ t/t_class_local_bad.v:47:18: ... Location of definition 15 | local int m_loc = 2; | ^~~~~ %Error-ENCAPSULATED: t/t_class_local_bad.v:50:14: 'f_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18) : ... note: In instance 't' 50 | bad(); f_loc(); | ^~~~~ t/t_class_local_bad.v:50:14: ... Location of definition 18 | local task f_loc; endtask | ^~~~~ %Error-ENCAPSULATED: t/t_class_local_bad.v:53:16: 'f_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18) : ... note: In instance 't' 53 | bad(); o.f_loc(); | ^~~~~ t/t_class_local_bad.v:53:16: ... Location of definition 18 | local task f_loc; endtask | ^~~~~ %Error-ENCAPSULATED: t/t_class_local_bad.v:56:14: 's_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18) : ... note: In instance 't' 56 | bad(); s_loc(); | ^~~~~ t/t_class_local_bad.v:56:14: ... Location of definition 21 | static local task s_loc; endtask | ^~~~~ %Error-ENCAPSULATED: t/t_class_local_bad.v:59:19: 's_loc' is hidden as 'local' within this context (IEEE 1800-2023 8.18) : ... note: In instance 't' 59 | bad(); Cls::s_loc(); | ^~~~~ t/t_class_local_bad.v:59:19: ... Location of definition 21 | static local task s_loc; endtask | ^~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_func_ref_noinline.py0000755000542200017500000000100115101701376023440 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_func_ref.v" test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_struct_array.py0000755000542200017500000000073415101701376022514 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_reloop_offset.py0000755000542200017500000000151415101701376022635 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile( verilator_flags2=["-unroll-count 1024", test.wno_unopthreads_for_few_cores, "--stats"]) test.execute(expect_filename=test.golden_filename) if test.vlt: # Note, with vltmt this might be split differently, so only checking vlt test.file_grep(test.stats, r'Optimizations, Reloop iterations\s+(\d+)', 125) test.file_grep(test.stats, r'Optimizations, Reloops\s+(\d+)', 2) test.passes() verilator-5.042/test_regress/t/t_func_many_return.v0000644000542200017500000002426615101701376023170 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; function automatic string get_csr_name(input logic [11:0] csr_addr); // verilator no_inline_task unique case (csr_addr) 12'd0000: return "xx0000xxxxx"; 12'd0001: return "xx0001xxxx"; 12'd1952: return "xx1952xxxxx"; 12'd1953: return "xx1953xxx1"; 12'd1954: return "xx1954xxx2"; 12'd1955: return "xx1955xxx3"; 12'd1968: return "xx1968xx"; 12'd1969: return "xx1969x"; 12'd1970: return "xx1970xxxxxx"; 12'd0256: return "xx0256xxxxx"; 12'd0258: return "xx0258xxxxx"; 12'd0259: return "xx0259xxxxx"; 12'd0260: return "xx0260x"; 12'd0261: return "xx0261xxx"; 12'd0262: return "xx0262xxxxxxxx"; 12'd2816: return "xx2816xxxx"; 12'd2818: return "xx2818xxxxxx"; 12'd2819: return "xx2819xxxxxxxxx3"; 12'd2820: return "xx2820xxxxxxxxx4"; 12'd2821: return "xx2821xxxxxxxxx5"; 12'd2822: return "xx2822xxxxxxxxx6"; 12'd2823: return "xx2823xxxxxxxxx7"; 12'd2824: return "xx2824xxxxxxxxx8"; 12'd2825: return "xx2825xxxxxxxxx9"; 12'd2826: return "xx2826xxxxxxxxx10"; 12'd2827: return "xx2827xxxxxxxxx11"; 12'd2828: return "xx2828xxxxxxxxx12"; 12'd2829: return "xx2829xxxxxxxxx13"; 12'd2830: return "xx2830xxxxxxxxx14"; 12'd2831: return "xx2831xxxxxxxxx15"; 12'd2832: return "xx2832xxxxxxxxx16"; 12'd2833: return "xx2833xxxxxxxxx17"; 12'd2834: return "xx2834xxxxxxxxx18"; 12'd2835: return "xx2835xxxxxxxxx19"; 12'd2836: return "xx2836xxxxxxxxx20"; 12'd2837: return "xx2837xxxxxxxxx21"; 12'd2838: return "xx2838xxxxxxxxx22"; 12'd2839: return "xx2839xxxxxxxxx23"; 12'd2840: return "xx2840xxxxxxxxx24"; 12'd2841: return "xx2841xxxxxxxxx25"; 12'd2842: return "xx2842xxxxxxxxx26"; 12'd2843: return "xx2843xxxxxxxxx27"; 12'd2844: return "xx2844xxxxxxxxx28"; 12'd2845: return "xx2845xxxxxxxxx29"; 12'd2846: return "xx2846xxxxxxxxx30"; 12'd2847: return "xx2847xxxxxxxxx31"; 12'd2944: return "xx2944xxxxx"; 12'd2946: return "xx2946xxxxxxx"; 12'd2947: return "xx2947xxxxxxxxx3x"; 12'd2948: return "xx2948xxxxxxxxx4x"; 12'd2949: return "xx2949xxxxxxxxx5x"; 12'd2950: return "xx2950xxxxxxxxx6x"; 12'd2951: return "xx2951xxxxxxxxx7x"; 12'd2952: return "xx2952xxxxxxxxx8x"; 12'd2953: return "xx2953xxxxxxxxx9x"; 12'd2954: return "xx2954xxxxxxxxx10x"; 12'd2955: return "xx2955xxxxxxxxx11x"; 12'd2956: return "xx2956xxxxxxxxx12x"; 12'd2957: return "xx2957xxxxxxxxx13x"; 12'd2958: return "xx2958xxxxxxxxx14x"; 12'd2959: return "xx2959xxxxxxxxx15x"; 12'd2960: return "xx2960xxxxxxxxx16x"; 12'd2961: return "xx2961xxxxxxxxx17x"; 12'd2962: return "xx2962xxxxxxxxx18x"; 12'd2963: return "xx2963xxxxxxxxx19x"; 12'd2964: return "xx2964xxxxxxxxx20x"; 12'd2965: return "xx2965xxxxxxxxx21x"; 12'd2966: return "xx2966xxxxxxxxx22x"; 12'd2967: return "xx2967xxxxxxxxx23x"; 12'd2968: return "xx2968xxxxxxxxx24x"; 12'd2969: return "xx2969xxxxxxxxx25x"; 12'd2970: return "xx2970xxxxxxxxx26x"; 12'd2971: return "xx2971xxxxxxxxx27x"; 12'd2972: return "xx2972xxxxxxxxx28x"; 12'd2973: return "xx2973xxxxxxxxx29x"; 12'd2974: return "xx2974xxxxxxxxx30x"; 12'd2975: return "xx2975xxxxxxxxx31x"; 12'd0002: return "xx0002x"; 12'd3072: return "xx3072xxx"; 12'd3073: return "xx3073xx"; 12'd3074: return "xx3074xxxxx"; 12'd3075: return "xx3075xxxxxxxx3"; 12'd3076: return "xx3076xxxxxxxx4"; 12'd3077: return "xx3077xxxxxxxx5"; 12'd3078: return "xx3078xxxxxxxx6"; 12'd3079: return "xx3079xxxxxxxx7"; 12'd3080: return "xx3080xxxxxxxx8"; 12'd3081: return "xx3081xxxxxxxx9"; 12'd3082: return "xx3082xxxxxxxx10"; 12'd3083: return "xx3083xxxxxxxx11"; 12'd3084: return "xx3084xxxxxxxx12"; 12'd3085: return "xx3085xxxxxxxx13"; 12'd3086: return "xx3086xxxxxxxx14"; 12'd3087: return "xx3087xxxxxxxx15"; 12'd3088: return "xx3088xxxxxxxx16"; 12'd3089: return "xx3089xxxxxxxx17"; 12'd3090: return "xx3090xxxxxxxx18"; 12'd3091: return "xx3091xxxxxxxx19"; 12'd3092: return "xx3092xxxxxxxx20"; 12'd3093: return "xx3093xxxxxxxx21"; 12'd3094: return "xx3094xxxxxxxx22"; 12'd3095: return "xx3095xxxxxxxx23"; 12'd3096: return "xx3096xxxxxxxx24"; 12'd3097: return "xx3097xxxxxxxx25"; 12'd3098: return "xx3098xxxxxxxx26"; 12'd3099: return "xx3099xxxxxxxx27"; 12'd3100: return "xx3100xxxxxxxx28"; 12'd3101: return "xx3101xxxxxxxx29"; 12'd3102: return "xx3102xxxxxxxx30"; 12'd3103: return "xx3103xxxxxxxx31"; 12'd3200: return "xx3200xxxx"; 12'd3201: return "xx3201xxx"; 12'd3202: return "xx3202xxxxxx"; 12'd3203: return "xx3203xxxxxxxx3x"; 12'd3204: return "xx3204xxxxxxxx4x"; 12'd3205: return "xx3205xxxxxxxx5x"; 12'd3206: return "xx3206xxxxxxxx6x"; 12'd3207: return "xx3207xxxxxxxx7x"; 12'd3208: return "xx3208xxxxxxxx8x"; 12'd3209: return "xx3209xxxxxxxx9x"; 12'd0320: return "xx0320xxxxxx"; 12'd3210: return "xx3210xxxxxxxx10x"; 12'd3211: return "xx3211xxxxxxxx11x"; 12'd3212: return "xx3212xxxxxxxx12x"; 12'd3213: return "xx3213xxxxxxxx13x"; 12'd3214: return "xx3214xxxxxxxx14x"; 12'd3215: return "xx3215xxxxxxxx15x"; 12'd3216: return "xx3216xxxxxxxx16x"; 12'd3217: return "xx3217xxxxxxxx17x"; 12'd3218: return "xx3218xxxxxxxx18x"; 12'd3219: return "xx3219xxxxxxxx19x"; 12'd3220: return "xx3220xxxxxxxx20x"; 12'd3221: return "xx3221xxxxxxxx21x"; 12'd3222: return "xx3222xxxxxxxx22x"; 12'd3223: return "xx3223xxxxxxxx23x"; 12'd3224: return "xx3224xxxxxxxx24x"; 12'd3225: return "xx3225xxxxxxxx25x"; 12'd3226: return "xx3226xxxxxxxx26x"; 12'd3227: return "xx3227xxxxxxxx27x"; 12'd3228: return "xx3228xxxxxxxx28x"; 12'd3229: return "xx3229xxxxxxxx29x"; 12'd3230: return "xx3230xxxxxxxx30x"; 12'd3231: return "xx3231xxxxxxxx31x"; 12'd3857: return "xx3857xxxxxxx"; 12'd3858: return "xx3858xxxxx"; 12'd3859: return "xx3859xxxx"; 12'd3860: return "xx3860xxxxx"; 12'd0512: return "xx0512xxxxx"; 12'd0514: return "xx0514xxxxx"; 12'd0515: return "xx0515xxxxx"; 12'd0516: return "xx0516x"; 12'd0517: return "xx0517xxx"; 12'd0576: return "xx0576xxxxxx"; 12'd0577: return "xx0577xx"; 12'd0578: return "xx0578xxxx"; 12'd0579: return "xx0579xxxxxx"; 12'd0580: return "xx0580x"; 12'd0768: return "xx0768xxxxx"; 12'd0769: return "xx0769xx"; 12'd0770: return "xx0770xxxxx"; 12'd0771: return "xx0771xxxxx"; 12'd0772: return "xx0772x"; 12'd0773: return "xx0773xxx"; 12'd0774: return "xx0774xxxxxxxx"; 12'd0800: return "xx0800xxxxxxxxxxx"; 12'd0803: return "xx0803xxxxxxx3"; 12'd0804: return "xx0804xxxxxxx4"; 12'd0805: return "xx0805xxxxxxx5"; 12'd0806: return "xx0806xxxxxxx6"; 12'd0807: return "xx0807xxxxxxx7"; 12'd0808: return "xx0808xxxxxxx8"; 12'd0809: return "xx0809xxxxxxx9"; 12'd0810: return "xx0810xxxxxxx10"; 12'd0811: return "xx0811xxxxxxx11"; 12'd0812: return "xx0812xxxxxxx12"; 12'd0813: return "xx0813xxxxxxx13"; 12'd0814: return "xx0814xxxxxxx14"; 12'd0815: return "xx0815xxxxxxx15"; 12'd0816: return "xx0816xxxxxxx16"; 12'd0817: return "xx0817xxxxxxx17"; 12'd0818: return "xx0818xxxxxxx18"; 12'd0819: return "xx0819xxxxxxx19"; 12'd0820: return "xx0820xxxxxxx20"; 12'd0821: return "xx0821xxxxxxx21"; 12'd0822: return "xx0822xxxxxxx22"; 12'd0823: return "xx0823xxxxxxx23"; 12'd0824: return "xx0824xxxxxxx24"; 12'd0825: return "xx0825xxxxxxx25"; 12'd0826: return "xx0826xxxxxxx26"; 12'd0827: return "xx0827xxxxxxx27"; 12'd0828: return "xx0828xxxxxxx28"; 12'd0829: return "xx0829xxxxxxx29"; 12'd0830: return "xx0830xxxxxxx30"; 12'd0831: return "xx0831xxxxxxx31"; 12'd0832: return "xx0832xxxxxx"; 12'd0833: return "xx0833xx"; 12'd0834: return "xx0834xxxx"; 12'd0835: return "xx0835xxx"; 12'd0836: return "xx0836x"; 12'd0896: return "xx0896xxx"; 12'd0897: return "xx0897xxxx"; 12'd0898: return "xx0898xxxx"; 12'd0899: return "xx0899xxxxx"; 12'd0900: return "xx0900xxxx"; 12'd0901: return "xx0901xxxxx"; 12'd0928: return "xx0928xxxx0"; 12'd0929: return "xx0929xxxx1"; 12'd0930: return "xx0930xxxx2"; 12'd0931: return "xx0931xxxx3"; 12'd0944: return "xx0944xxxxx0"; 12'd0945: return "xx0945xxxxx1"; 12'd0946: return "xx0946xxxxx2"; 12'd0947: return "xx0947xxxxx3"; 12'd0948: return "xx0948xxxxx4"; 12'd0949: return "xx0949xxxxx5"; 12'd0950: return "xx0950xxxxx6"; 12'd0951: return "xx0951xxxxx7"; 12'd0952: return "xx0952xxxxx8"; 12'd0953: return "xx0953xxxxx9"; 12'd0954: return "xx0954xxxxx10"; 12'd0955: return "xx0955xxxxx11"; 12'd0956: return "xx0956xxxxx12"; 12'd0957: return "xx0957xxxxx13"; 12'd0958: return "xx0958xxxxx14"; 12'd0959: return "xx0959xxxxx15"; default: return $sformatf("0x%x", csr_addr); endcase endfunction int i; initial begin if (get_csr_name(12'd0957) != "xx0957xxxxx13") $stop; if (get_csr_name(12'd2830) != "xx2830xxxxxxxxx14") $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_interface_typo_bad.out0000644000542200017500000000151215101701376023762 0ustar mahmoudyfreeshell%Error: t/t_interface_typo_bad.v:14:4: Interface 'foo_intf' not connected as parent's interface not connected : ... Perhaps caused by another error on the parent interface that needs resolving : ... Or, perhaps intended an interface instantiation but are missing parenthesis (IEEE 1800-2023 25.3)? 14 | foo_intf foo | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_interface_typo_bad.v:22:4: Cannot find file containing interface: 'fo_intf' 22 | fo_intf the_foo(); | ^~~~~~~ %Error: t/t_interface_typo_bad.v:27:15: Found definition of 'the_foo' as a CELL but expected a variable 27 | .foo (the_foo) | ^~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_var_bad_hide_docs.v0000644000542200017500000000044215101701376023177 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; integer t; //<--- Warning ('t' hidden by module 't') endmodule verilator-5.042/test_regress/t/t_class_assign_cond.v0000644000542200017500000000402315101701376023253 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class Cls; int f; function new(int x); f = x; endfunction endclass class ExtendCls extends Cls; function new(int x); super.new(x); endfunction endclass class AnotherExtendCls extends Cls; function new(int x); super.new(x); endfunction endclass class ExtendExtendCls extends ExtendCls; function new(int x); super.new(x); endfunction endclass module t; typedef ExtendCls ExtendCls_t; initial begin Cls cls1 = null, cls2 = null; ExtendCls_t ext_cls = null; AnotherExtendCls an_ext_cls = null; ExtendExtendCls ext_ext_cls = null; int r; cls1 = (cls1 == null) ? cls2 : cls1; if (cls1 != null) $stop; cls1 = new(1); cls1 = (cls1 == null) ? cls2 : cls1; if (cls1.f != 1) $stop; cls1 = (cls1 != null) ? cls2 : cls1; if (cls1 != null) $stop; cls1 = new(1); cls2 = new(2); cls1 = (cls1 != null) ? cls2 : cls1; if (cls1.f != 2) $stop; cls1 = null; cls1 = (ext_cls != null) ? ext_cls : cls2; if (cls1.f != 2) $stop; ext_cls = new(3); cls1 = (ext_cls != null) ? ext_cls : cls2; if (cls1.f != 3) $stop; ext_ext_cls = new(4); an_ext_cls = new(5); cls1 = (ext_ext_cls.f != 4) ? ext_ext_cls : an_ext_cls; if (cls1.f != 5) $stop; ext_cls = new(3); r = $random; cls1 = r[0] ? ext_cls : null; if (cls1 != null && cls1.f != 3) $stop; ext_cls = new(3); r = $random; cls1 = r[0] ? null : ext_cls; if (cls1 != null && cls1.f != 3) $stop; ext_cls = new(3); r = $random; cls1 = r[0] ? null : null; if (cls1 != null) $stop; ext_cls = new(3); cls1 = (ext_cls == null) ? null : null; if (cls1 != null) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_assert_synth_full.py0000755000542200017500000000132715101701376023541 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_assert_synth.v" test.compile(v_flags2=['+define+FAILING_FULL +define+ATTRIBUTES'], verilator_flags2=['--assert'], nc_flags2=['+assert']) test.execute(check_finished=False, fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_stream_struct.v0000644000542200017500000000357615101701376022512 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [63:0] in = crc[63:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) logic [63:0] out; // From test of Test.v // End of automatics Test test(/*AUTOINST*/ // Outputs .out (out[63:0]), // Inputs .in (in[63:0])); // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x out=%x\n", $time, cyc, crc, out); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= out ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc == 0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc < 10) begin sum <= '0; end else if (cyc == 99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h29271cf844d6f90c if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test ( input wire [63:0] in, output logic [63:0] out); typedef struct packed { logic [63:0] dummy; } data_t; function automatic logic [63:0] reverse(data_t d); return {<<{d}}; endfunction assign out = reverse(in); endmodule verilator-5.042/test_regress/t/t_timescale_unit.py0000755000542200017500000000100015101701376022762 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_hier_block0_bad.v0000644000542200017500000000415115101701376022570 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020-2024 by Yutetsu TAKATSUKASA and Antmicro. // SPDX-License-Identifier: Unlicense `define HIER_BLOCK /*verilator hier_block*/ module t (/*AUTOARG*/ // Inputs clk ); input clk; wire [7:0] out0; wire [7:0] out1; int count = 0; // unpacked array cannot be passed to hierarchical block localparam logic UNPACKED[0:1] = '{1'b1, 1'b0}; sub0 #(UNPACKED) i_sub0(.clk(clk), .in(8'(count)), .out(out0)); sub1 #(.T(logic[7:0])) i_sub1(.in(out0), .out(out1)); always_ff @(posedge clk) begin // dotted access under hierarchical block is not allowed ... $display("%d i_sub0.ff: %d", count, i_sub0.ff); $display("%d i_sub0.i_sub.out: %d", count, i_sub0.i_sub.out); // ... Except for ports on a dierct hierarchical child $display("%d i_sub0.out: %d", count, i_sub0.out); $display("%d out1: %d", count, out1); if (count == 16) begin if (out1 == 15) begin $write("*-* All Finished *-*\n"); $finish; end else begin $write("Missmatch\n"); $stop; end end count <= count + 1; end endmodule module sub0 #( parameter logic UNPACKED[0:1] = '{1'b0, 1'b1} ) ( input wire clk, input wire [7:0] in, output wire [7:0] out); `HIER_BLOCK logic [7:0] ff; always_ff @(posedge clk) ff <= in; assign out = ff; logic [7:0] gg; sub0_sub0 i_sub(.in(ff), .out(gg)); always_ff @(posedge clk) begin // dotted access under hierarchical block is not allowed ... $display("%m: i_sub.x: %d", i_sub.x); // ... Except for ports on a direct hierarchical child $display("%m: i_sub.out: %d", i_sub.out); end endmodule module sub1 #( parameter type T = logic ) ( input wire T in, output wire T out); `HIER_BLOCK assign out = in; sub1_sub #(T) sub(in, out); endmodule module sub0_sub0 ( input wire [7:0] in, output wire [7:0] out ); `HIER_BLOCK wire [7:0] x = in + 1; assign out = x; endmodule verilator-5.042/test_regress/t/t_time_literals.py0000755000542200017500000000073415101701376022627 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_case_enum_incomplete_wildcard_bad.v0000644000542200017500000000154615101701376026443 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: SystemVerilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Anthony Donlon. // SPDX-License-Identifier: CC0-1.0 module t; t1 i_t1(); endmodule module t1; enum logic [1:0] { S00 = 'b00, S01 = 'b01, S10 = 'b10, SX0 = 2'b?0, S0X = 'b0? } state; int v = 0; initial begin state = S10; unique case (state) S00: $stop; 2'b01: $stop; endcase unique case (state) 2'd2: v++; 2'd1: $stop; endcase unique casez (state) S0X: $stop; 2'b11: $stop; endcase case (state) S00: $stop; S01: $stop; S10: v++; endcase end endmodule verilator-5.042/test_regress/t/t_case_enum_emptyish.v0000644000542200017500000000076615101701376023472 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; enum logic [2:0] { e0, e1, e2, e3 } EN; initial begin unique case (EN) e0 :; e1 :; e2 :; e3 :; endcase $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_json_only_flat.out0000644000542200017500000005676415101701376023204 0ustar mahmoudyfreeshell{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"(E)", "modulesp": [ {"type":"MODULE","name":"$root","addr":"(F)","loc":"d,7:8,7:9","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"$root","level":1,"modPublic":true,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"q","addr":"(G)","loc":"d,15:22,15:23","dtypep":"(H)","origName":"q","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"clk","addr":"(I)","loc":"d,13:10,13:13","dtypep":"(J)","origName":"clk","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"d","addr":"(K)","loc":"d,14:16,14:17","dtypep":"(H)","origName":"d","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"t.q","addr":"(L)","loc":"d,15:22,15:23","dtypep":"(H)","origName":"q","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"t.clk","addr":"(M)","loc":"d,13:10,13:13","dtypep":"(J)","origName":"clk","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"t.d","addr":"(N)","loc":"d,14:16,14:17","dtypep":"(H)","origName":"d","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"t.between","addr":"(O)","loc":"d,17:22,17:29","dtypep":"(H)","origName":"between","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"t.cell1.WIDTH","addr":"(P)","loc":"d,32:15,32:20","dtypep":"(Q)","origName":"WIDTH","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"GPARAM","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":true,"isParam":true,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [], "valuep": [ {"type":"CONST","name":"32'sh4","addr":"(R)","loc":"d,19:18,19:19","dtypep":"(Q)"} ],"attrsp": []}, {"type":"VAR","name":"t.cell1.clk","addr":"(S)","loc":"d,34:24,34:27","dtypep":"(J)","origName":"clk","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"t.cell1.d","addr":"(T)","loc":"d,35:30,35:31","dtypep":"(H)","origName":"d","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"t.cell1.q","addr":"(U)","loc":"d,36:30,36:31","dtypep":"(H)","origName":"q","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"t.cell1.IGNORED","addr":"(V)","loc":"d,39:15,39:22","dtypep":"(Q)","origName":"IGNORED","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"LPARAM","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":true,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [], "valuep": [ {"type":"CONST","name":"32'sh1","addr":"(W)","loc":"d,39:25,39:26","dtypep":"(Q)"} ],"attrsp": []}, {"type":"VAR","name":"t.cell2.clk","addr":"(X)","loc":"d,48:10,48:13","dtypep":"(J)","origName":"clk","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"t.cell2.d","addr":"(Y)","loc":"d,49:16,49:17","dtypep":"(H)","origName":"d","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"t.cell2.q","addr":"(Z)","loc":"d,50:22,50:23","dtypep":"(H)","origName":"q","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"TOPSCOPE","name":"","addr":"(E)","loc":"d,7:8,7:9","senTreesp": [], "scopep": [ {"type":"SCOPE","name":"TOP","addr":"(AB)","loc":"d,7:8,7:9","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(F)", "varsp": [ {"type":"VARSCOPE","name":"q","addr":"(BB)","loc":"d,15:22,15:23","dtypep":"(H)","isTrace":true,"scopep":"(AB)","varp":"(G)"}, {"type":"VARSCOPE","name":"clk","addr":"(CB)","loc":"d,13:10,13:13","dtypep":"(J)","isTrace":true,"scopep":"(AB)","varp":"(I)"}, {"type":"VARSCOPE","name":"d","addr":"(DB)","loc":"d,14:16,14:17","dtypep":"(H)","isTrace":true,"scopep":"(AB)","varp":"(K)"}, {"type":"VARSCOPE","name":"t.q","addr":"(EB)","loc":"d,15:22,15:23","dtypep":"(H)","isTrace":true,"scopep":"(AB)","varp":"(L)"}, {"type":"ALWAYS","name":"","addr":"(FB)","loc":"d,15:22,15:23","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(GB)","loc":"d,15:22,15:23","dtypep":"(H)", "rhsp": [ {"type":"VARREF","name":"q","addr":"(HB)","loc":"d,15:22,15:23","dtypep":"(H)","access":"RD","varp":"(G)","varScopep":"(BB)","classOrPackagep":"UNLINKED"} ], "lhsp": [ {"type":"VARREF","name":"t.q","addr":"(IB)","loc":"d,15:22,15:23","dtypep":"(H)","access":"WR","varp":"(L)","varScopep":"(EB)","classOrPackagep":"UNLINKED"} ],"timingControlp": [],"strengthSpecp": []} ]}, {"type":"VARSCOPE","name":"t.clk","addr":"(JB)","loc":"d,13:10,13:13","dtypep":"(J)","isTrace":true,"scopep":"(AB)","varp":"(M)"}, {"type":"ALWAYS","name":"","addr":"(KB)","loc":"d,13:10,13:13","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(LB)","loc":"d,13:10,13:13","dtypep":"(J)", "rhsp": [ {"type":"VARREF","name":"clk","addr":"(MB)","loc":"d,13:10,13:13","dtypep":"(J)","access":"RD","varp":"(I)","varScopep":"(CB)","classOrPackagep":"UNLINKED"} ], "lhsp": [ {"type":"VARREF","name":"t.clk","addr":"(NB)","loc":"d,13:10,13:13","dtypep":"(J)","access":"WR","varp":"(M)","varScopep":"(JB)","classOrPackagep":"UNLINKED"} ],"timingControlp": [],"strengthSpecp": []} ]}, {"type":"VARSCOPE","name":"t.d","addr":"(OB)","loc":"d,14:16,14:17","dtypep":"(H)","isTrace":true,"scopep":"(AB)","varp":"(N)"}, {"type":"ALWAYS","name":"","addr":"(PB)","loc":"d,14:16,14:17","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(QB)","loc":"d,14:16,14:17","dtypep":"(H)", "rhsp": [ {"type":"VARREF","name":"d","addr":"(RB)","loc":"d,14:16,14:17","dtypep":"(H)","access":"RD","varp":"(K)","varScopep":"(DB)","classOrPackagep":"UNLINKED"} ], "lhsp": [ {"type":"VARREF","name":"t.d","addr":"(SB)","loc":"d,14:16,14:17","dtypep":"(H)","access":"WR","varp":"(N)","varScopep":"(OB)","classOrPackagep":"UNLINKED"} ],"timingControlp": [],"strengthSpecp": []} ]}, {"type":"VARSCOPE","name":"t.between","addr":"(TB)","loc":"d,17:22,17:29","dtypep":"(H)","isTrace":true,"scopep":"(AB)","varp":"(O)"}, {"type":"VARSCOPE","name":"t.cell1.WIDTH","addr":"(UB)","loc":"d,32:15,32:20","dtypep":"(Q)","isTrace":true,"scopep":"(AB)","varp":"(P)"}, {"type":"VARSCOPE","name":"t.cell1.clk","addr":"(VB)","loc":"d,34:24,34:27","dtypep":"(J)","isTrace":true,"scopep":"(AB)","varp":"(S)"}, {"type":"ALWAYS","name":"","addr":"(WB)","loc":"d,34:24,34:27","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(XB)","loc":"d,34:24,34:27","dtypep":"(J)", "rhsp": [ {"type":"VARREF","name":"clk","addr":"(YB)","loc":"d,34:24,34:27","dtypep":"(J)","access":"RD","varp":"(I)","varScopep":"(CB)","classOrPackagep":"UNLINKED"} ], "lhsp": [ {"type":"VARREF","name":"t.cell1.clk","addr":"(ZB)","loc":"d,34:24,34:27","dtypep":"(J)","access":"WR","varp":"(S)","varScopep":"(VB)","classOrPackagep":"UNLINKED"} ],"timingControlp": [],"strengthSpecp": []} ]}, {"type":"VARSCOPE","name":"t.cell1.d","addr":"(AC)","loc":"d,35:30,35:31","dtypep":"(H)","isTrace":true,"scopep":"(AB)","varp":"(T)"}, {"type":"ALWAYS","name":"","addr":"(BC)","loc":"d,35:30,35:31","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(CC)","loc":"d,35:30,35:31","dtypep":"(H)", "rhsp": [ {"type":"VARREF","name":"d","addr":"(DC)","loc":"d,35:30,35:31","dtypep":"(H)","access":"RD","varp":"(K)","varScopep":"(DB)","classOrPackagep":"UNLINKED"} ], "lhsp": [ {"type":"VARREF","name":"t.cell1.d","addr":"(EC)","loc":"d,35:30,35:31","dtypep":"(H)","access":"WR","varp":"(T)","varScopep":"(AC)","classOrPackagep":"UNLINKED"} ],"timingControlp": [],"strengthSpecp": []} ]}, {"type":"VARSCOPE","name":"t.cell1.q","addr":"(FC)","loc":"d,36:30,36:31","dtypep":"(H)","isTrace":true,"scopep":"(AB)","varp":"(U)"}, {"type":"ALWAYS","name":"","addr":"(GC)","loc":"d,36:30,36:31","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(HC)","loc":"d,36:30,36:31","dtypep":"(H)", "rhsp": [ {"type":"VARREF","name":"t.between","addr":"(IC)","loc":"d,36:30,36:31","dtypep":"(H)","access":"RD","varp":"(O)","varScopep":"(TB)","classOrPackagep":"UNLINKED"} ], "lhsp": [ {"type":"VARREF","name":"t.cell1.q","addr":"(JC)","loc":"d,36:30,36:31","dtypep":"(H)","access":"WR","varp":"(U)","varScopep":"(FC)","classOrPackagep":"UNLINKED"} ],"timingControlp": [],"strengthSpecp": []} ]}, {"type":"VARSCOPE","name":"t.cell1.IGNORED","addr":"(KC)","loc":"d,39:15,39:22","dtypep":"(Q)","isTrace":true,"scopep":"(AB)","varp":"(V)"}, {"type":"VARSCOPE","name":"t.cell2.clk","addr":"(LC)","loc":"d,48:10,48:13","dtypep":"(J)","isTrace":true,"scopep":"(AB)","varp":"(X)"}, {"type":"ALWAYS","name":"","addr":"(MC)","loc":"d,48:10,48:13","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(NC)","loc":"d,48:10,48:13","dtypep":"(J)", "rhsp": [ {"type":"VARREF","name":"clk","addr":"(OC)","loc":"d,48:10,48:13","dtypep":"(J)","access":"RD","varp":"(I)","varScopep":"(CB)","classOrPackagep":"UNLINKED"} ], "lhsp": [ {"type":"VARREF","name":"t.cell2.clk","addr":"(PC)","loc":"d,48:10,48:13","dtypep":"(J)","access":"WR","varp":"(X)","varScopep":"(LC)","classOrPackagep":"UNLINKED"} ],"timingControlp": [],"strengthSpecp": []} ]}, {"type":"VARSCOPE","name":"t.cell2.d","addr":"(QC)","loc":"d,49:16,49:17","dtypep":"(H)","isTrace":true,"scopep":"(AB)","varp":"(Y)"}, {"type":"ALWAYS","name":"","addr":"(RC)","loc":"d,49:16,49:17","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(SC)","loc":"d,49:16,49:17","dtypep":"(H)", "rhsp": [ {"type":"VARREF","name":"t.between","addr":"(TC)","loc":"d,49:16,49:17","dtypep":"(H)","access":"RD","varp":"(O)","varScopep":"(TB)","classOrPackagep":"UNLINKED"} ], "lhsp": [ {"type":"VARREF","name":"t.cell2.d","addr":"(UC)","loc":"d,49:16,49:17","dtypep":"(H)","access":"WR","varp":"(Y)","varScopep":"(QC)","classOrPackagep":"UNLINKED"} ],"timingControlp": [],"strengthSpecp": []} ]}, {"type":"VARSCOPE","name":"t.cell2.q","addr":"(VC)","loc":"d,50:22,50:23","dtypep":"(H)","isTrace":true,"scopep":"(AB)","varp":"(Z)"}, {"type":"ALWAYS","name":"","addr":"(WC)","loc":"d,50:22,50:23","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(XC)","loc":"d,50:22,50:23","dtypep":"(H)", "rhsp": [ {"type":"VARREF","name":"q","addr":"(YC)","loc":"d,50:22,50:23","dtypep":"(H)","access":"RD","varp":"(G)","varScopep":"(BB)","classOrPackagep":"UNLINKED"} ], "lhsp": [ {"type":"VARREF","name":"t.cell2.q","addr":"(ZC)","loc":"d,50:22,50:23","dtypep":"(H)","access":"WR","varp":"(Z)","varScopep":"(VC)","classOrPackagep":"UNLINKED"} ],"timingControlp": [],"strengthSpecp": []} ]} ], "blocksp": [ {"type":"ALWAYS","name":"","addr":"(AD)","loc":"d,41:4,41:10","keyword":"always","isSuspendable":false,"needProcess":false, "sentreep": [ {"type":"SENTREE","name":"","addr":"(BD)","loc":"d,41:11,41:12","isMulti":false, "sensesp": [ {"type":"SENITEM","name":"","addr":"(CD)","loc":"d,41:13,41:20","edgeType":"POS", "sensp": [ {"type":"VARREF","name":"clk","addr":"(DD)","loc":"d,41:21,41:24","dtypep":"(J)","access":"RD","varp":"(I)","varScopep":"(CB)","classOrPackagep":"UNLINKED"} ],"condp": []} ]} ], "stmtsp": [ {"type":"ASSIGNDLY","name":"","addr":"(ED)","loc":"d,42:8,42:10","dtypep":"(H)", "rhsp": [ {"type":"VARREF","name":"d","addr":"(FD)","loc":"d,42:11,42:12","dtypep":"(H)","access":"RD","varp":"(K)","varScopep":"(DB)","classOrPackagep":"UNLINKED"} ], "lhsp": [ {"type":"VARREF","name":"t.between","addr":"(GD)","loc":"d,42:6,42:7","dtypep":"(H)","access":"WR","varp":"(O)","varScopep":"(TB)","classOrPackagep":"UNLINKED"} ],"timingControlp": []} ]}, {"type":"ALWAYS","name":"","addr":"(HD)","loc":"d,53:13,53:14","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(ID)","loc":"d,53:13,53:14","dtypep":"(H)", "rhsp": [ {"type":"VARREF","name":"t.between","addr":"(JD)","loc":"d,17:22,17:29","dtypep":"(H)","access":"RD","varp":"(O)","varScopep":"(TB)","classOrPackagep":"UNLINKED"} ], "lhsp": [ {"type":"VARREF","name":"q","addr":"(KD)","loc":"d,53:13,53:14","dtypep":"(H)","access":"WR","varp":"(G)","varScopep":"(BB)","classOrPackagep":"UNLINKED"} ],"timingControlp": [],"strengthSpecp": []} ]} ],"inlinesp": []} ]} ]} ],"filesp": [], "miscsp": [ {"type":"TYPETABLE","name":"","addr":"(C)","loc":"a,0:0,0:0","constraintRefp":"UNLINKED","emptyQueuep":"UNLINKED","queueIndexp":"UNLINKED","streamp":"UNLINKED","voidp":"(LD)", "typesp": [ {"type":"BASICDTYPE","name":"logic","addr":"(J)","loc":"d,34:24,34:27","dtypep":"(J)","keyword":"logic","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(H)","loc":"d,15:16,15:17","dtypep":"(H)","keyword":"logic","range":"3:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(Q)","loc":"d,19:18,19:19","dtypep":"(Q)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, {"type":"VOIDDTYPE","name":"","addr":"(LD)","loc":"a,0:0,0:0","dtypep":"(LD)","generic":false} ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ {"type":"MODULE","name":"@CONST-POOL@","addr":"(MD)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], "stmtsp": [ {"type":"SCOPE","name":"@CONST-POOL@","addr":"(ND)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(MD)","varsp": [],"blocksp": [],"inlinesp": []} ]} ]} ]} verilator-5.042/test_regress/t/t_sv_cpu_code/0000755000542200017500000000000015101701376021702 5ustar mahmoudyfreeshellverilator-5.042/test_regress/t/t_sv_cpu_code/cpu.sv0000644000542200017500000001342715101701376023052 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Large test for SystemVerilog // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. module cpu #( parameter // ... ID = 1 ) // Not used! ( // *************************************************************************** // Module Interface (interfaces, outputs, and inputs) // *************************************************************************** // **** Interfaces **** genbus_if.master dbus, // **** Outputs **** // N/A // **** Inputs **** input logic clk, input logic rst ); // *************************************************************************** // Regs and Wires // *************************************************************************** // **** Program Memory **** logic [15:0] rom_out; // **** Register File (RF) **** logic [7:0] rf[0:15]; // **** Fetch Stage **** logic [7:0] pc; // PC -> Program counter. logic [15:0] ir; // IR -> Instruction Register. // **** Decode **** logic [3:0] idec_rd; logic idec_rd_we; logic [7:0] idec_rd_data; logic [3:0] idec_rs; logic [7:0] idec_nextpc; // New PC if change of program flow. logic idec_coff; // Indicates a change of program flow. logic [7:0] idec_mem_adr; logic idec_mem_re; logic idec_mem_we; // **** Memory **** logic [7:0] mem_data; // Data from peripheral. logic mem_ws; // Waitstate. // *************************************************************************** // Program Memory (ROM) Interface // *************************************************************************** always_comb begin: ROM // - Local Variables - integer i; reg [15:0] irom [0:255]; // - Set default - for ( i = 0; i < 256; i++ ) begin if ( i < $size(rom) ) irom[i] = rom[i]; else irom[i] = 16'h0000; end rom_out = irom[pc[7:0]]; end // *************************************************************************** // Register File (RF) // *************************************************************************** always_ff @( posedge clk ) begin: RegFile // - Local Variables - integer i; // - Register File - for ( i = 0; i < 16; i++ ) begin if ( rst ) rf[i][7:0] <= 8'h00; else if ( idec_rd_we & (idec_rd == i[3:0]) ) rf[i] <= idec_rd_data; end end // *************************************************************************** // Fetch Stage // *************************************************************************** // **** Program Counter (PC) / Instruction Register (IR) **** always_ff @( posedge clk ) begin if ( rst ) begin pc <= 8'h00; ir <= 16'h0000; end else //if ( ~mem_ws ) begin if ( ~idec_coff ) begin pc <= pc + 1; ir <= rom_out; // Fetch Instruction. end else begin pc <= idec_nextpc; ir <= 16'h0000; // Insert no operation (NOP). end end end // *************************************************************************** // Decode/Execute Stage // *************************************************************************** always_comb begin // - Defaults - idec_rd = 4'h0; idec_rd_we = 1'b0; idec_rd_data = 8'h00; idec_rs = 4'h0; idec_nextpc = 8'h00; idec_coff = 1'b0; idec_mem_adr = 8'h00; idec_mem_re = 1'b0; idec_mem_we = 1'b0; // verilator lint_off CASEINCOMPLETE casez ( ir ) 16'h0000:; // NOP (<=> Default) 16'h1???: // JMP imm begin idec_nextpc = ir[7:0]; idec_coff = 1'b1; end 16'h4???: // LDI rd, imm begin idec_rd = ir[8+:4]; idec_rd_we = 1'b1; idec_rd_data = ir[0+:8]; end 16'h8???: begin // STS imm, rs idec_mem_adr = ir[0+:8]; idec_mem_we = 1'b1; idec_rs = ir[8+:4]; end 16'h9???: begin // LDS rd, imm idec_mem_adr = ir[0+:8]; idec_mem_we = 1'b1; idec_rd = ir[8+:4]; idec_rd_we = 1'b1; idec_rd_data = mem_data[0+:8]; end endcase end // *************************************************************************** // Memory Access ("Stage") // *************************************************************************** // **** Connect to "dbus" **** always_comb begin: Conntect reg [15:0] sdata16; dbus.mConnect ( ID, // ID sdata16, // sdata mem_ws, // ws {2{rf[idec_rs]}}, // mdata // adr {8'h00, idec_mem_adr[7:1], 1'b0}, // we {idec_mem_adr[0],~idec_mem_adr[0]} & {2{idec_mem_we}}, // re {idec_mem_adr[0],~idec_mem_adr[0]} & {2{idec_mem_re}} ); // - Connect 16-bit databus to 8-bit CPU - mem_data = ( idec_mem_adr[0] ) ? sdata16[15:8] : sdata16[7:0]; end mPreAdrDecode_resp busproperty; always_comb begin: PreAdrDecode // verilator lint_off WIDTH busproperty = dbus.mPreAdrDecode( 0, idec_mem_adr ); // verilator lint_on WIDTH end endmodule // cpu verilator-5.042/test_regress/t/t_sv_cpu_code/timescale.sv0000644000542200017500000000044415101701376024224 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Large test for SystemVerilog // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. // **** Set simulation time scale **** `timescale 1ns/1ps verilator-5.042/test_regress/t/t_sv_cpu_code/pads_h.sv0000644000542200017500000000541715101701376023521 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Large test for SystemVerilog // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. `ifndef _PADS_H_SV_ `define _PADS_H_SV_ // ***************************************************************************** // // ***************************************************************************** // **** Pin Identifiers **** typedef enum int { PINID_A0 = 32'd0, // MUST BE ZERO! // - Standard Ports - PINID_A1, PINID_A2, PINID_A3, PINID_A4, PINID_A5, PINID_A6, PINID_A7, PINID_B0, PINID_B1, PINID_B2, PINID_B3, PINID_B4, PINID_B5, PINID_B6, PINID_B7, PINID_C0, PINID_C1, PINID_C2, PINID_C3, PINID_C4, PINID_C5, PINID_C6, PINID_C7, PINID_D0, PINID_D1, PINID_D2, PINID_D3, PINID_D4, PINID_D5, PINID_D6, PINID_D7, PINID_E0, PINID_E1, PINID_E2, PINID_E3, PINID_E4, PINID_E5, PINID_E6, PINID_E7, PINID_F0, PINID_F1, PINID_F2, PINID_F3, PINID_F4, PINID_F5, PINID_F6, PINID_F7, PINID_G0, PINID_G1, PINID_G2, PINID_G3, PINID_G4, PINID_G5, PINID_G6, PINID_G7, PINID_H0, PINID_H1, PINID_H2, PINID_H3, PINID_H4, PINID_H5, PINID_H6, PINID_H7, // PINID_I0, PINID_I1, PINID_I2, PINID_I3, PINID_I4, PINID_I5, PINID_I6, PINID_I7,-> DO NOT USE!!!! I == 1 PINID_J0, PINID_J1, PINID_J2, PINID_J3, PINID_J4, PINID_J5, PINID_J6, PINID_J7, PINID_K0, PINID_K1, PINID_K2, PINID_K3, PINID_K4, PINID_K5, PINID_K6, PINID_K7, PINID_L0, PINID_L1, PINID_L2, PINID_L3, PINID_L4, PINID_L5, PINID_L6, PINID_L7, PINID_M0, PINID_M1, PINID_M2, PINID_M3, PINID_M4, PINID_M5, PINID_M6, PINID_M7, PINID_N0, PINID_N1, PINID_N2, PINID_N3, PINID_N4, PINID_N5, PINID_N6, PINID_N7, // PINID_O0, PINID_O1, PINID_O2, PINID_O3, PINID_O4, PINID_O5, PINID_O6, PINID_O7,-> DO NOT USE!!!! O == 0 PINID_P0, PINID_P1, PINID_P2, PINID_P3, PINID_P4, PINID_P5, PINID_P6, PINID_P7, PINID_Q0, PINID_Q1, PINID_Q2, PINID_Q3, PINID_Q4, PINID_Q5, PINID_Q6, PINID_Q7, PINID_R0, PINID_R1, PINID_R2, PINID_R3, PINID_R4, PINID_R5, PINID_R6, PINID_R7, // - AUX Port (Custom) - PINID_X0, PINID_X1, PINID_X2, PINID_X3, PINID_X4, PINID_X5, PINID_X6, PINID_X7, // - PDI Port - PINID_D2W_DAT, PINID_D2W_CLK, // - Power Pins - PINID_VDD0, PINID_VDD1, PINID_VDD2, PINID_VDD3, PINID_GND0, PINID_GND1, PINID_GND2, PINID_GND3, // - Maximum number of pins - PINID_MAX } t_pinid; // **** Pad types **** typedef enum int { PADTYPE_DEFAULT = 32'd0, PADTYPE_GPIO, // General Purpose I/O Pad (GPIO). PADTYPE_GPIO_ANA, // GPIO with Analog connection. Low noise GPIO. PADTYPE_GPIO_HDS, // GPIO with High Drive Strength. PADTYPE_VDD, // VDD Supply Pad PADTYPE_GND // Ground Pad } t_padtype; `endif // !`ifdef _PADS_H_SV_ verilator-5.042/test_regress/t/t_sv_cpu_code/ports_h.sv0000644000542200017500000000177315101701376023742 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Large test for SystemVerilog // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. `ifndef _PORTS_H_SV_ `define _PORTS_H_SV_ // ***************************************************************************** // // ***************************************************************************** // !!!! Incomplete! localparam int str_pinid [0:15] = '{ "DEF", "ERR", "ERR", "ERR", "ERR", "ERR", "ERR", "ERR", "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7" }; // **** Port Identifiers **** typedef enum int { PORTID_A = 32'd0, // MUST BE ZERO! PORTID_B, PORTID_C, PORTID_D, PORTID_E, PORTID_F, PORTID_G, PORTID_H, // PORTID_I, -> DO NOT USE! PORTID_J, PORTID_K, PORTID_L, PORTID_M, PORTID_N, // PORTID_O, -> DO NOT USE! PORTID_P, PORTID_Q, PORTID_R } t_portid; `endif // !`ifdef _PORTS_H_SV_ // **** End of File **** verilator-5.042/test_regress/t/t_sv_cpu_code/adrdec.sv0000644000542200017500000000221715101701376023500 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Large test for SystemVerilog // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. module adrdec #( parameter NSLAVES = 2 ) ( // *************************************************************************** // Module Interface (interfaces, outputs, and inputs) // *************************************************************************** // **** Interfaces **** genbus_if.adrdec dbus ); // *************************************************************************** // Address Decode // *************************************************************************** // const logic [15:0] adrmap[1:2] = '{} always_comb begin logic sel [1:NSLAVES]; sel[1] = (dbus.s_adr[1][7:4] == 4'h0); sel[2] = (dbus.s_adr[2][7:4] == 4'h1); // sel[3] = (dbus.s_adr[3][7:4] == 4'h2); dbus.s_sel = sel; // for ( i = 1; i <= dbus.aNumSlaves; i++ ) // begin // dbus.s_sel[i] = (dbus.s_adr[i] == adrmap[i]); // end end endmodule // adrdec verilator-5.042/test_regress/t/t_sv_cpu_code/pad_gnd.sv0000644000542200017500000000104215101701376023645 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Large test for SystemVerilog // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. //***************************************************************************** // PAD_GND - Ground Supply Pad (Dummy!!!!) //***************************************************************************** module pad_gnd #( parameter ID = 0 ) ( inout wire pad ); assign pad = 1'b0; endmodule // pad_gnd verilator-5.042/test_regress/t/t_sv_cpu_code/pad_gpio.sv0000644000542200017500000000215515101701376024041 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Large test for SystemVerilog // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. //***************************************************************************** // PAD_GPIO - General Purpose I/O Pad (Dummy!!!!) //***************************************************************************** module pad_gpio #( parameter ID = 0 ) ( input logic pullup_en, input logic pulldown_en, input logic output_en, input logic output_val, input logic slew_limit_en, input logic input_en, output logic input_val, inout wire ana, inout wire pad ); // **** Analog <-> pad connection **** `ifndef VERILATOR //TODO alias alias ana = pad; `endif // **** Digital driver <-> pad connection **** assign pad = (output_en) ? output_val : 1'bz; // **** Digital pull-up/pull-down <-> pad connection **** // TO BE ADDED!!!! // **** Digital input <-> pad connection **** assign input_val = (input_en) ? pad : 1'b0; endmodule // pad_gpio verilator-5.042/test_regress/t/t_sv_cpu_code/chip.sv0000644000542200017500000000660615101701376023207 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Large test for SystemVerilog // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. // ***************************************************************************** // Top level of System Verilog evalution (Full chip level) // ***************************************************************************** module chip #( parameter NUMPADS = $size( pinout ) ) ( // **** Pinout **** `ifdef VERILATOR // see t_tri_array inout wire [NUMPADS:1] pad, `else inout wire pad [1:NUMPADS], `endif // **** Inputs !!!! **** input logic clk, input logic rst ); // *************************************************************************** // Local Parameters // *************************************************************************** localparam NSLAVES = 2; // *************************************************************************** // PADS // *************************************************************************** // **** Interface **** pads_if padsif(); // **** Pad Instansiations **** pads // #( ) i_pads ( /*AUTOINST*/ // Interfaces .padsif (padsif.mp_pads), // Inouts .pad (pad), // Inputs .clk (clk), .rst (rst)); // *************************************************************************** // "dbus" Interface // *************************************************************************** genbus_if #( .NSLAVES(NSLAVES) ) dbus( .clk(clk), .rst(rst), .test_mode(1'b0) ); adrdec // #( ) i_adrdec ( /*AUTOINST*/ // Interfaces .dbus (dbus.adrdec)); // *************************************************************************** // CPU ("dbus" Master) // *************************************************************************** cpu #( .ID(1) ) i_cpu ( /*AUTOINST*/ // Interfaces .dbus (dbus.master), // Inputs .clk (clk), .rst (rst)); // *************************************************************************** // PORTS ("dbus" Slave #1) // *************************************************************************** ports #( .ID(1) ) i_ports ( /*AUTOINST*/ // Interfaces .dbus (dbus.slave), .padsif (padsif.mp_dig), // Inputs .clk (clk), .rst (rst)); // *************************************************************************** // Analog Comparator ("dbus" Slave #2) // *************************************************************************** ac #( .ID(2) ) i_ac ( /*AUTOINST*/ // Interfaces .dbus (dbus.slave), .padsif (padsif.mp_ana), // Inputs .clk (clk), .rst (rst)); endmodule // chip verilator-5.042/test_regress/t/t_sv_cpu_code/rom.sv0000644000542200017500000000153615101701376023056 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Large test for SystemVerilog // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. // ***************************************************************************** // Code ROM // // IMPORTANT! // Array size must be uppdated according to program size. // ***************************************************************************** const logic [15:0] rom[0:13] = '{ `LDI( R0, 11 ) `LDI( R1, 22 ) `LDI( R2, 33 ) `LDI( R3, 44 ) `STS( 0, R0 ) `STS( 1, R1 ) `STS( 2, R2 ) `STS( 3, R3 ) `LDS( R4, 0 ) `LDS( R5, 1 ) `LDS( R6, 0 ) `LDS( R7, 0 ) `JMP( 00 ) `EOP // End of Program (NOP) }; verilator-5.042/test_regress/t/t_sv_cpu_code/ac.sv0000644000542200017500000000423315101701376022641 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Large test for SystemVerilog // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. module ac #( parameter ID = 1 ) ( // *************************************************************************** // Module Interface (interfaces, outputs, and inputs) // *************************************************************************** // **** Interfaces **** genbus_if.slave dbus, pads_if.mp_ana padsif, // - System - input logic clk, input logic rst ); // *************************************************************************** // Regs and Wires, Automatics // *************************************************************************** /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) logic acenable; // From i_ac_dig of ac_dig.v logic acout; // From i_ac_ana of ac_ana.v // End of automatics // *************************************************************************** // Digital Control // *************************************************************************** ac_dig #( .ID(ID) ) i_ac_dig ( .dbus (dbus), /*AUTOINST*/ // Outputs .acenable (acenable), // Inputs .acout (acout), .clk (clk), .rst (rst)); // *************************************************************************** // Analog Model // *************************************************************************** ac_ana i_ac_ana ( .padsif (padsif), /*AUTOINST*/ // Outputs .acout (acout), // Inputs .acenable (acenable), .clk (clk), .rst (rst)); endmodule // ac verilator-5.042/test_regress/t/t_sv_cpu_code/pad_vdd.sv0000644000542200017500000000103715101701376023656 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Large test for SystemVerilog // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. //***************************************************************************** // PAD_VDD - VDD Supply Pad (Dummy!!!!) //***************************************************************************** module pad_vdd #( parameter ID = 0 ) ( inout wire pad ); assign pad = 1'b1; endmodule // pad_vdd verilator-5.042/test_regress/t/t_sv_cpu_code/pads.sv0000644000542200017500000000534215101701376023207 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Large test for SystemVerilog // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. module pads #( parameter NUMPADS = $size( pinout ) ) ( // *************************************************************************** // Module Interface // *************************************************************************** // **** Interfaces **** pads_if.mp_pads padsif, // **** Pinout **** `ifdef VERILATOR // see t_tri_array inout wire [NUMPADS:1] pad, `else inout wire pad [1:NUMPADS], `endif // **** Inputs **** input logic clk, input logic rst ); // *************************************************************************** // Code Section // *************************************************************************** `ifdef VERILATOR // see t_tri_array tri [NUMPADS:1] _anahack; `endif genvar i; for ( i = 1; i <= NUMPADS; i++ ) begin `ifdef VCS localparam t_padtype p_type = t_padtype'(pinout_wa[i][pinout_wa_padtype]); localparam t_pinid p_id = t_pinid'(pinout_wa[i][pinout_wa_id]); `else localparam t_padtype p_type = pinout[i].padtype; localparam t_pinid p_id = pinout[i].id; `endif case ( p_type ) PADTYPE_GPIO: pad_gpio #( .ID( i ) ) i_pad_gpio( .pad (pad [i]), // Outputs .input_val (padsif.input_val [i]), // Inouts `ifdef VERILATOR // see t_tri_array .ana (_anahack [i]), `else .ana (padsif.ana [i]), `endif // Inputs .pullup_en (padsif.pullup_en [i]), .pulldown_en (padsif.pulldown_en [i]), .output_en (padsif.output_en [i]), .output_val (padsif.output_val [i]), .slew_limit_en (padsif.slew_limit_en[i]), .input_en (padsif.input_en [i]) /*AUTOINST*/); PADTYPE_VDD: begin pad_vdd #( .ID( i ) ) i_pad_vdd( .pad (pad[i]) /*AUTOINST*/); // Not SV standard, yet... assign padsif.input_val[i] = (); end PADTYPE_GND: begin pad_gnd #( .ID( i ) ) i_pad_gnd(.pad (pad[i]) /*AUTOINST*/); end endcase end endmodule // pads verilator-5.042/test_regress/t/t_sv_cpu_code/pinout_h.sv0000644000542200017500000000327215101701376024105 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Large test for SystemVerilog // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. `ifndef _PINOUT_H_SV_ `define _PINOUT_H_SV_ // ***************************************************************************** // Structs/Unions // ***************************************************************************** // **** Pin Descriptor **** // - Pin Descriptor - typedef struct packed { t_pinid id; t_padtype padtype; int aux; } t_pin_descriptor; // ***************************************************************************** // Pinout // ***************************************************************************** // **** Preferred Solution !!!! **** localparam t_pin_descriptor pinout[ 1: 6] = '{ '{default:0, id:PINID_A0, padtype:PADTYPE_GPIO, aux:1}, '{default:0, id:PINID_A1, padtype:PADTYPE_GPIO}, '{default:0, id:PINID_A2, padtype:PADTYPE_GPIO}, '{default:0, id:PINID_D0, padtype:PADTYPE_GPIO}, '{default:0, id:PINID_VDD0, padtype:PADTYPE_VDD}, '{default:0, id:PINID_GND0, padtype:PADTYPE_GND} }; // **** Workaround !!!! **** typedef enum int { pinout_wa_id = 1, pinout_wa_padtype, pinout_wa_aux } t_pinout_wa; localparam int pinout_size = 6; localparam int pinout_wa[1:pinout_size][pinout_wa_id:pinout_wa_aux] = '{ '{PINID_A0, PADTYPE_GPIO, 0}, '{PINID_A1, PADTYPE_GPIO, 0}, '{PINID_A2, PADTYPE_GPIO, 0}, '{PINID_D0, PADTYPE_GPIO, 0}, '{PINID_VDD0, PADTYPE_VDD, 0}, '{PINID_GND0, PADTYPE_GND , 0} }; `endif // `ifndef _PINOUT_H_SV_ // **** End of File **** verilator-5.042/test_regress/t/t_sv_cpu_code/program_h.sv0000644000542200017500000000206015101701376024230 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Large test for SystemVerilog // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. `ifndef _PROGRAM_H_V_ `define _PROGRAM_H_V_ // ***************************************************************************** // Assembly Mnemonic Defines // ***************************************************************************** typedef enum reg [3:0] { R0,R1,R2,R3,R4,R5,R6,R7, R8,R9,R10,R11,R12,R13,R14,R15 } cpu_registers; `define NOP 16'h0000, `define JMP( k8 ) {4'h1, 4'h0, 8'h k8}, `define LDI( rd, k8 ) {4'h4, rd, 8'h k8}, `define STS( k8, rs ) {4'h8, rs, 8'h k8}, `define LDS( rd, k8 ) {4'h9, rd, 8'h k8}, `define EOP 16'h0000 // ***************************************************************************** // Include ROM // ***************************************************************************** `include "rom.sv" `endif // !`ifdef _PROGRAM_H_V_ verilator-5.042/test_regress/t/t_sv_cpu_code/pads_if.sv0000644000542200017500000000574715101701376023676 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Large test for SystemVerilog // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. interface pads_if(); // *************************************************************************** // Local Parameters // *************************************************************************** localparam NUMPADS = $size( pinout ); // *************************************************************************** // Interface Variables // *************************************************************************** // - PADS Digital Interface - logic pullup_en [1:NUMPADS];// Pull-up/down/bus-keeper enable. logic pulldown_en [1:NUMPADS];// Pull direction (0:Pull-up; 1:Pull-down). logic output_en [1:NUMPADS];// Digital output buffer enable. logic output_val [1:NUMPADS];// Digital output value. logic input_en [1:NUMPADS];// Digital input buffer enable. logic slew_limit_en [1:NUMPADS];// Slew rate limiter enable. logic input_val [1:NUMPADS];// Digital input value. // - PADS Analog Interface - logic ana_override [1:NUMPADS];// Disables digital output when driving analog output. wire ana [1:NUMPADS]; // *************************************************************************** // Modports // *************************************************************************** modport mp_pads( input pullup_en, input pulldown_en, input output_en, input output_val, input slew_limit_en, input input_en, output input_val, input ana_override, inout ana ); modport mp_dig( import IsPad, import IsPort, import Init, output pullup_en, output pulldown_en, output output_en, output output_val, output slew_limit_en, output input_en, input input_val ); modport mp_ana( import IsPad, output ana_override, inout ana ); // *************************************************************************** // Check for which pins exists // *************************************************************************** bit [PINID_D7:PINID_A0] exists; function automatic void Init( ); exists = {(PINID_D7+1){1'b0}}; for ( int i = 1; i <= $size( pinout ); i++ ) if ( PINID_D7 >= pinout[i].id ) exists[pinout[i].id] = 1'b1; endfunction // *************************************************************************** // Functions and Tasks // *************************************************************************** function automatic bit IsPad( integer i ); IsPad = exists[i]; endfunction function automatic bit IsPort( integer i ); IsPort = |exists[8*i+:8]; endfunction endinterface // pads_if verilator-5.042/test_regress/t/t_sv_cpu_code/ac_dig.sv0000644000542200017500000000651715101701376023473 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Large test for SystemVerilog // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. module ac_dig #( parameter ID = 1 ) ( // *************************************************************************** // Module Interface (interfaces, outputs, and inputs) // *************************************************************************** // **** Interfaces **** genbus_if.slave dbus, // **** Outputs **** output logic acenable, // **** Inputs **** input logic acout, // - System - input logic clk, input logic rst ); // *************************************************************************** // Regs and Wires // *************************************************************************** // **** Internal Data Bus **** logic [15:0] sdata; logic ws; logic [15:0] mdata; logic [15:0] adr; logic [1:0] we; logic [1:0] re; // **** User Registers **** struct packed { logic [7:1] reserved; logic enable; } control; struct packed { logic [7:1] reserved; logic acout; } status; // **** Internals **** logic [1:0] sync; // *************************************************************************** // Assignments // *************************************************************************** assign acenable = control.enable; // *************************************************************************** // "dbus" Connection // *************************************************************************** always_comb begin `ifdef VERILATOR //TODO dbus.sConnect( .id(ID), .rst(rst), .sdata(sdata), .ws(ws), .mdata(mdata), .adr(adr ), .we(we), .re(re) ); `else dbus.sConnect( .id(ID), .rst(rst), .sdata(sdata), .ws(ws), .mdata(mdata), .adr(adr[1:0]), .we(we), .re(re) ); `endif // dbus.sConnect( ID, rst, sdata, ws, mdata, adr, we, re ); end // *************************************************************************** // Register Access // *************************************************************************** // **** Register Write **** always_ff @( posedge clk ) begin if ( rst ) control <= 8'h00; else if ( (adr[1:0] == 2'b00) & we[0] ) control <= mdata[7:0]; end // **** Regiser Read **** always_comb begin: RegisterRead // - Local Variables - logic [7:0] data[0:3]; // Read access concatination. // - Setup read multiplexer - data = '{ control, status, 8'h00, 8'h00 }; // - Connect "genbusif" - sdata = { 8'h00, data[ adr[1:0] ] }; ws = 1'b0; end // *************************************************************************** // Status // *************************************************************************** // **** Synchronization **** always_ff @( posedge clk ) begin if ( rst ) sync <= 2'b00; else if ( control.enable ) sync <= {sync[0], acout}; end always_comb begin // - Defaults - status = {$size(status){1'b0}}; // - Set register values - status.acout = sync[1]; end endmodule // ac_dig verilator-5.042/test_regress/t/t_sv_cpu_code/genbus_if.sv0000644000542200017500000001511415101701376024217 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Large test for SystemVerilog // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. typedef struct packed { bit [1:0] size; } mPreAdrDecode_resp; interface genbus_if #( parameter DSIZE = 2, SSIZE = DSIZE, ASIZE = 16, NMASTERS = 1, NSLAVES = 1, DMSB = (DSIZE<<3) - 1, SMSB = SSIZE - 1, AMSB = ASIZE - 1 ) ( // **** Inputs **** // - System - input logic clk, // Device Clock. input logic rst, // Device Reset. input logic test_mode // Test mode. ); // *************************************************************************** // Interface Variables // *************************************************************************** // **** Master **** logic [DMSB:0] m_sdata[1:NMASTERS]; // Slave data. logic m_ws [1:NMASTERS]; // Slave wait state. logic [DMSB:0] m_mdata[1:NMASTERS]; // Master data. logic [AMSB:0] m_adr [1:NMASTERS]; // Address. logic [SMSB:0] m_we [1:NMASTERS]; // Write enable. logic [SMSB:0] m_re [1:NMASTERS]; // Read enable. // **** Slave **** logic [DMSB:0] s_sdata[1:NSLAVES]; // Slave data (from slave). logic s_ws [1:NSLAVES]; // Slave wait state (from slave). logic [DMSB:0] s_mdata[1:NSLAVES]; // Master data (to slave). logic [AMSB:0] s_adr [1:NSLAVES]; // Address (to slave). logic [SMSB:0] s_we [1:NSLAVES]; // Write enable (to slave). logic [SMSB:0] s_re [1:NSLAVES]; // Read enable (to slave). // **** Address Decoder **** logic s_sel [1:NSLAVES]; // Slave select (to slave). // *************************************************************************** // Modports // *************************************************************************** modport master( import mConnect, import mPreAdrDecode, input m_sdata, input m_ws, output m_mdata, output m_adr, output m_we, output m_re ); // - Slaves - modport slave( import sConnect, output s_sdata, output s_ws, input s_mdata, input s_adr, input s_we, input s_re, input s_sel ); // UNSUPPORTED // for (genvar i = 1; i <= NSLAVES; i++ ) // begin: mps // modport slave( // import sConnect, // output .s_sdata( s_sdata[i] ), // output .s_ws ( s_ws [i] ), // input .s_mdata( s_mdata[i] ), // input .s_adr ( s_adr [i] ), // input .s_we ( s_we [i] ), // input .s_re ( s_re [i] ), // input .s_sel ( s_sel [i] ) // ); // end // blocks modport adrdec( import aNumSlaves, input s_adr, output s_sel ); // *************************************************************************** // Bus Multiplexers // *************************************************************************** always_comb begin: busmux // - Local Variables - integer i; // - Defautls - m_sdata[1] = {(DSIZE<<3){1'b0}}; m_ws [1] = 1'b0; for ( i = 1; i <= NSLAVES; i++ ) begin m_sdata[1] |= s_sdata[i]; m_ws [1] |= s_ws [i]; s_mdata[i] = m_mdata[1]; s_adr [i] = m_adr [1]; s_we [i] = m_we [1]; s_re [i] = m_re [1]; end end // *************************************************************************** // Master Functions and Tasks // *************************************************************************** function automatic void mConnect( input integer id, output logic [DMSB:0] sdata, output logic ws, input logic [DMSB:0] mdata, input logic [AMSB:0] adr, input logic [SMSB:0] we, input logic [SMSB:0] re ); begin m_mdata[id] = mdata; m_adr [id] = adr; m_we [id] = we; m_re [id] = re; sdata = m_sdata[id]; ws = m_ws [id]; end endfunction function automatic mPreAdrDecode_resp mPreAdrDecode( input integer id, input logic [AMSB:0] adr ); begin // ToDo: Add parameterized address decoding!!!! // Example code: if ( adr[0] ) mPreAdrDecode.size = 2'b01; // Word (16-bit) memory. else mPreAdrDecode.size = 2'b10; // Double Word (32-bit) memory. end endfunction // *************************************************************************** // Slave Functions and Tasks // *************************************************************************** function automatic void sConnect( input integer id, input logic rst, input logic [DMSB:0] sdata, input logic ws, output logic [DMSB:0] mdata, output logic [AMSB:0] adr, output logic [SMSB:0] we, output logic [SMSB:0] re ); begin s_sdata[id] = sdata & {(DSIZE<<3){s_sel[id]}}; // verilator lint_off WIDTH s_ws [id] = ws & {SSIZE{s_sel[id]}}; // verilator lint_on WIDTH mdata = s_mdata[id] & {16{~rst}}; adr = s_adr [id]; we = (s_we [id] & {SSIZE{s_sel[id]}}) | {SSIZE{rst}}; re = s_re [id] & {SSIZE{s_sel[id]}}; end endfunction // *************************************************************************** // Address Decoder Functions and Tasks // *************************************************************************** function automatic integer aNumSlaves; aNumSlaves = NSLAVES; endfunction endinterface // genbus_if verilator-5.042/test_regress/t/t_sv_cpu_code/ports.sv0000644000542200017500000001024115101701376023421 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Large test for SystemVerilog // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. module ports #( parameter ID = 1 ) ( // *************************************************************************** // Module Interface (interfaces, outputs, and inputs) // *************************************************************************** genbus_if.slave dbus, pads_if.mp_dig padsif, // - System - input logic clk, input logic rst ); // *************************************************************************** // Regs and Wires // *************************************************************************** // **** Internal Data Bus **** logic [15:0] sdata; logic ws; logic [15:0] mdata; logic [15:0] adr; logic [1:0] we; logic [1:0] re; // **** Interal Registers **** struct { logic [7:0][1:0] in; logic [7:0] dir; logic [7:0] out; struct { logic [7:2] reserved; logic pullupen; logic slewlim; } cfg; } port [PORTID_A:PORTID_D]; // *************************************************************************** // "dbus" Connection // *************************************************************************** always_comb begin: dbus_Connect dbus.sConnect( .id(ID), .rst(rst), .sdata(sdata), .ws(ws), .mdata(mdata), .adr(adr), .we(we), .re(re) ); end // *************************************************************************** // Register Access // For PORTA...PORTD (Excluding I and O) // +0x00 DIR // +0x01 OUT // +0x02 IN // +0x03 CFG // *************************************************************************** always_comb begin padsif.Init(); end // **** Register Write **** always_ff @( posedge clk ) begin // - Local Variables - integer i, j; // **** Setup Port Registers **** for ( j = PORTID_A; j <= PORTID_D; j++ ) begin if ( padsif.IsPort( j ) ) begin if ( ((adr[3:2] == j[1:0]) && (adr[1] == 1'b0)) | rst ) begin if ( we[0] ) port[j].dir <= mdata[7:0]; if ( we[1] ) port[j].out <= mdata[15:8]; end end else begin port[j].dir <= 8'h00; port[j].out <= 8'h00; end end end // **** Regiser Read **** always_comb begin: RegisterRead // - Local Variables - integer i, j; logic [7:0] data [PORTID_D:PORTID_A][3:0]; // **** Output to "dbus" **** // - Setup read multiplexer - for ( j = PORTID_A; j <= PORTID_D; j++ ) begin // verilator lint_off SIDEEFFECT if ( padsif.IsPort( j ) ) data[j] = '{ port[j].dir, port[j].out, 8'h00, 8'h00 }; else data[j] = '{ 8'h00, 8'h00, 8'h00, 8'h00 }; // verilator lint_on SIDEEFFECT end // - Connect "genbusif" - sdata = { 8'h00, data[ adr[3:2] ][ adr[1:0] ] }; ws = 1'b0; end // *************************************************************************** // Output // *************************************************************************** always_comb begin // - Local Variables - integer i, j; // **** Defaults **** for ( i = 1; i <= $size( pinout ); i++ ) begin padsif.pullup_en [i] = 1'b0; padsif.pulldown_en [i] = 1'b0; padsif.output_en [i] = 1'b0; padsif.output_val [i] = 1'b0; padsif.slew_limit_en[i] = 1'b0; padsif.input_en [i] = 1'b0; end // **** Connect to Pads **** for ( i = 1; i <= $size( pinout ); i++ ) begin j = pinout[i].id; if ( PINID_D7 >= j ) begin padsif.output_en [i] = port[j[4:3]].dir[j[2:0]]; padsif.output_val[i] = port[j[4:3]].out[j[2:0]]; end end end endmodule // ports verilator-5.042/test_regress/t/t_sv_cpu_code/ac_ana.sv0000644000542200017500000000207215101701376023457 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Large test for SystemVerilog // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. module ac_ana // #( parameter // ID = 1 ) ( // *************************************************************************** // Module Interface (interfaces, outputs, and inputs) // *************************************************************************** // **** Interfaces **** pads_if.mp_ana padsif, // **** Outputs **** output logic acout, // **** Inputs **** input logic acenable, // - System - input logic clk, input logic rst ); // *************************************************************************** // Analog Model // *************************************************************************** assign acout = (padsif.ana[1] - padsif.ana[2]) & acenable; assign padsif.ana_override[1] = 1'b0; assign padsif.ana_override[2] = 1'b0; endmodule // ac_ana verilator-5.042/test_regress/t/t_dfg_true_cycle_bad.py0000755000542200017500000000076315101701376023560 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_vlt_warn_file_bad.vlt0000644000542200017500000000057015101701376023603 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `verilator_config // Test that this -file rule doesn't turn off warnings in t/t_vlt_warn_file_bad.v lint_off -rule WIDTHTRUNC -file "t/t_vlt_warn_file_bad_b.vh" verilator-5.042/test_regress/t/t_flag_build_dep_bin.v0000644000542200017500000000035215101701376023350 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; endmodule verilator-5.042/test_regress/t/t_trace_timescale.py0000755000542200017500000000106115101701376023110 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(v_flags2=["--trace-vcd"]) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_unbounded_bad.v0000644000542200017500000000042615101701376022373 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin if ($) $stop; end endmodule verilator-5.042/test_regress/t/t_gate_delref.v0000644000542200017500000000223415101701376022042 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // bug1475 module t (/*AUTOARG*/ // Outputs ID_45, IDa_f4c, // Inputs clk, ID_d9f, IDa_657, ID_477 ); input clk; output reg ID_45; input ID_d9f; input IDa_657; output reg IDa_f4c; reg ID_13; input ID_477; reg ID_489; reg ID_8d1; reg IDa_183; reg IDa_91c; reg IDa_a96; reg IDa_d6b; reg IDa_eb9; wire ID_fc8 = ID_d9f & ID_13; //<< wire ID_254 = ID_d9f & ID_13; wire ID_f40 = ID_fc8 ? ID_8d1 : 0; wire ID_f4c = ID_fc8 ? 0 : ID_477; wire ID_442 = IDa_91c; wire ID_825 = ID_489; always @(posedge clk) begin ID_13 <= ID_f40; ID_8d1 <= IDa_eb9; ID_489 <= ID_442; ID_45 <= ID_825; IDa_d6b <= IDa_a96; IDa_f4c <= ID_f4c; if (ID_254) begin IDa_91c <= IDa_d6b; IDa_183 <= IDa_657; IDa_a96 <= IDa_657; IDa_eb9 <= IDa_183; end end endmodule verilator-5.042/test_regress/t/t_math_concat0.v0000644000542200017500000000466015101701376022146 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [15:0] in = crc[15:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [15:0] outa; // From test of Test.v wire [15:0] outb; // From test of Test.v wire [15:0] outc; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .outa (outa[15:0]), .outb (outb[15:0]), .outc (outc[15:0]), // Inputs .clk (clk), .in (in[15:0])); // Aggregate outputs into a single result vector wire [63:0] result = {16'h0, outa, outb, outc}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h09be74b1b0f8c35d if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs outa, outb, outc, // Inputs clk, in ); input clk; input [15:0] in; output reg [15:0] outa; output reg [15:0] outb; output reg [15:0] outc; parameter WIDTH = 0; always @(posedge clk) begin outa <= {in}; outb <= {{WIDTH{1'b0}}, in}; outc <= {in, {WIDTH{1'b0}}}; end endmodule verilator-5.042/test_regress/t/t_class_extends_arg_super_bad.out0000644000542200017500000000104015101701376025651 0ustar mahmoudyfreeshell%Error: t/t_class_extends_arg_super_bad.v:17:13: Explicit super.new not allowed with class extends arguments (IEEE 1800-2023 8.17) : ... Suggest remove super.new 17 | super.new(33); | ^~~ t/t_class_extends_arg_super_bad.v:14:25: ... Location of extends argument(s) 14 | class Cls5 extends Base(5); | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_case_write1_tasks.v0000644000542200017500000041747415101701376023234 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t_case_write1_tasks (); // verilator lint_off WIDTH // verilator lint_off CASEINCOMPLETE parameter STRLEN = 78; task ozonerab; input [6:0] rab; inout [STRLEN*8:1] foobar; // verilator no_inline_task begin case (rab[6:0]) 7'h00 : foobar = {foobar, " 0"}; 7'h01 : foobar = {foobar, " 1"}; 7'h02 : foobar = {foobar, " 2"}; 7'h03 : foobar = {foobar, " 3"}; 7'h04 : foobar = {foobar, " 4"}; 7'h05 : foobar = {foobar, " 5"}; 7'h06 : foobar = {foobar, " 6"}; 7'h07 : foobar = {foobar, " 7"}; 7'h08 : foobar = {foobar, " 8"}; 7'h09 : foobar = {foobar, " 9"}; 7'h0a : foobar = {foobar, " 10"}; 7'h0b : foobar = {foobar, " 11"}; 7'h0c : foobar = {foobar, " 12"}; 7'h0d : foobar = {foobar, " 13"}; 7'h0e : foobar = {foobar, " 14"}; 7'h0f : foobar = {foobar, " 15"}; 7'h10 : foobar = {foobar, " 16"}; 7'h11 : foobar = {foobar, " 17"}; 7'h12 : foobar = {foobar, " 18"}; 7'h13 : foobar = {foobar, " 19"}; 7'h14 : foobar = {foobar, " 20"}; 7'h15 : foobar = {foobar, " 21"}; 7'h16 : foobar = {foobar, " 22"}; 7'h17 : foobar = {foobar, " 23"}; 7'h18 : foobar = {foobar, " 24"}; 7'h19 : foobar = {foobar, " 25"}; 7'h1a : foobar = {foobar, " 26"}; 7'h1b : foobar = {foobar, " 27"}; 7'h1c : foobar = {foobar, " 28"}; 7'h1d : foobar = {foobar, " 29"}; 7'h1e : foobar = {foobar, " 30"}; 7'h1f : foobar = {foobar, " 31"}; 7'h20 : foobar = {foobar, " 32"}; 7'h21 : foobar = {foobar, " 33"}; 7'h22 : foobar = {foobar, " 34"}; 7'h23 : foobar = {foobar, " 35"}; 7'h24 : foobar = {foobar, " 36"}; 7'h25 : foobar = {foobar, " 37"}; 7'h26 : foobar = {foobar, " 38"}; 7'h27 : foobar = {foobar, " 39"}; 7'h28 : foobar = {foobar, " 40"}; 7'h29 : foobar = {foobar, " 41"}; 7'h2a : foobar = {foobar, " 42"}; 7'h2b : foobar = {foobar, " 43"}; 7'h2c : foobar = {foobar, " 44"}; 7'h2d : foobar = {foobar, " 45"}; 7'h2e : foobar = {foobar, " 46"}; 7'h2f : foobar = {foobar, " 47"}; 7'h30 : foobar = {foobar, " 48"}; 7'h31 : foobar = {foobar, " 49"}; 7'h32 : foobar = {foobar, " 50"}; 7'h33 : foobar = {foobar, " 51"}; 7'h34 : foobar = {foobar, " 52"}; 7'h35 : foobar = {foobar, " 53"}; 7'h36 : foobar = {foobar, " 54"}; 7'h37 : foobar = {foobar, " 55"}; 7'h38 : foobar = {foobar, " 56"}; 7'h39 : foobar = {foobar, " 57"}; 7'h3a : foobar = {foobar, " 58"}; 7'h3b : foobar = {foobar, " 59"}; 7'h3c : foobar = {foobar, " 60"}; 7'h3d : foobar = {foobar, " 61"}; 7'h3e : foobar = {foobar, " 62"}; 7'h3f : foobar = {foobar, " 63"}; 7'h40 : foobar = {foobar, " 64"}; 7'h41 : foobar = {foobar, " 65"}; 7'h42 : foobar = {foobar, " 66"}; 7'h43 : foobar = {foobar, " 67"}; 7'h44 : foobar = {foobar, " 68"}; 7'h45 : foobar = {foobar, " 69"}; 7'h46 : foobar = {foobar, " 70"}; 7'h47 : foobar = {foobar, " 71"}; 7'h48 : foobar = {foobar, " 72"}; 7'h49 : foobar = {foobar, " 73"}; 7'h4a : foobar = {foobar, " 74"}; 7'h4b : foobar = {foobar, " 75"}; 7'h4c : foobar = {foobar, " 76"}; 7'h4d : foobar = {foobar, " 77"}; 7'h4e : foobar = {foobar, " 78"}; 7'h4f : foobar = {foobar, " 79"}; 7'h50 : foobar = {foobar, " 80"}; 7'h51 : foobar = {foobar, " 81"}; 7'h52 : foobar = {foobar, " 82"}; 7'h53 : foobar = {foobar, " 83"}; 7'h54 : foobar = {foobar, " 84"}; 7'h55 : foobar = {foobar, " 85"}; 7'h56 : foobar = {foobar, " 86"}; 7'h57 : foobar = {foobar, " 87"}; 7'h58 : foobar = {foobar, " 88"}; 7'h59 : foobar = {foobar, " 89"}; 7'h5a : foobar = {foobar, " 90"}; 7'h5b : foobar = {foobar, " 91"}; 7'h5c : foobar = {foobar, " 92"}; 7'h5d : foobar = {foobar, " 93"}; 7'h5e : foobar = {foobar, " 94"}; 7'h5f : foobar = {foobar, " 95"}; 7'h60 : foobar = {foobar, " 96"}; 7'h61 : foobar = {foobar, " 97"}; 7'h62 : foobar = {foobar, " 98"}; 7'h63 : foobar = {foobar, " 99"}; 7'h64 : foobar = {foobar, " 100"}; 7'h65 : foobar = {foobar, " 101"}; 7'h66 : foobar = {foobar, " 102"}; 7'h67 : foobar = {foobar, " 103"}; 7'h68 : foobar = {foobar, " 104"}; 7'h69 : foobar = {foobar, " 105"}; 7'h6a : foobar = {foobar, " 106"}; 7'h6b : foobar = {foobar, " 107"}; 7'h6c : foobar = {foobar, " 108"}; 7'h6d : foobar = {foobar, " 109"}; 7'h6e : foobar = {foobar, " 110"}; 7'h6f : foobar = {foobar, " 111"}; 7'h70 : foobar = {foobar, " 112"}; 7'h71 : foobar = {foobar, " 113"}; 7'h72 : foobar = {foobar, " 114"}; 7'h73 : foobar = {foobar, " 115"}; 7'h74 : foobar = {foobar, " 116"}; 7'h75 : foobar = {foobar, " 117"}; 7'h76 : foobar = {foobar, " 118"}; 7'h77 : foobar = {foobar, " 119"}; 7'h78 : foobar = {foobar, " 120"}; 7'h79 : foobar = {foobar, " 121"}; 7'h7a : foobar = {foobar, " 122"}; 7'h7b : foobar = {foobar, " 123"}; 7'h7c : foobar = {foobar, " 124"}; 7'h7d : foobar = {foobar, " 125"}; 7'h7e : foobar = {foobar, " 126"}; 7'h7f : foobar = {foobar, " 127"}; default:foobar = {foobar, " 128"}; endcase end endtask task ozonerb; input [5:0] rb; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (rb[5:0]) 6'h10, 6'h17, 6'h1e, 6'h1f: foobar = {foobar, " 129"}; default: ozonerab({1'b1, rb}, foobar); endcase end endtask task ozonef3f4_iext; input [1:0] foo; input [15:0] im16; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (foo) 2'h0 : begin skyway({4{im16[15]}}, foobar); skyway({4{im16[15]}}, foobar); skyway(im16[15:12], foobar); skyway(im16[11: 8], foobar); skyway(im16[ 7: 4], foobar); skyway(im16[ 3:0], foobar); foobar = {foobar, " 130"}; end 2'h1 : begin foobar = {foobar, " 131"}; skyway(im16[15:12], foobar); skyway(im16[11: 8], foobar); skyway(im16[ 7: 4], foobar); skyway(im16[ 3:0], foobar); end 2'h2 : begin skyway({4{im16[15]}}, foobar); skyway({4{im16[15]}}, foobar); skyway(im16[15:12], foobar); skyway(im16[11: 8], foobar); skyway(im16[ 7: 4], foobar); skyway(im16[ 3:0], foobar); foobar = {foobar, " 132"}; end 2'h3 : begin foobar = {foobar, " 133"}; skyway(im16[15:12], foobar); skyway(im16[11: 8], foobar); skyway(im16[ 7: 4], foobar); skyway(im16[ 3:0], foobar); end endcase end endtask task skyway; input [ 3:0] hex; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (hex) 4'h0 : foobar = {foobar, " 134"}; 4'h1 : foobar = {foobar, " 135"}; 4'h2 : foobar = {foobar, " 136"}; 4'h3 : foobar = {foobar, " 137"}; 4'h4 : foobar = {foobar, " 138"}; 4'h5 : foobar = {foobar, " 139"}; 4'h6 : foobar = {foobar, " 140"}; 4'h7 : foobar = {foobar, " 141"}; 4'h8 : foobar = {foobar, " 142"}; 4'h9 : foobar = {foobar, " 143"}; 4'ha : foobar = {foobar, " 144"}; 4'hb : foobar = {foobar, " 145"}; 4'hc : foobar = {foobar, " 146"}; 4'hd : foobar = {foobar, " 147"}; 4'he : foobar = {foobar, " 148"}; 4'hf : foobar = {foobar, " 149"}; endcase end endtask task ozonesr; input [ 15:0] foo; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (foo[11: 9]) 3'h0 : foobar = {foobar, " 158"}; 3'h1 : foobar = {foobar, " 159"}; 3'h2 : foobar = {foobar, " 160"}; 3'h3 : foobar = {foobar, " 161"}; 3'h4 : foobar = {foobar, " 162"}; 3'h5 : foobar = {foobar, " 163"}; 3'h6 : foobar = {foobar, " 164"}; 3'h7 : foobar = {foobar, " 165"}; endcase end endtask task ozonejk; input k; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin if (k) foobar = {foobar, " 166"}; else foobar = {foobar, " 167"}; end endtask task ozoneae; input [ 2:0] ae; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (ae) 3'b000 : foobar = {foobar, " 168"}; 3'b001 : foobar = {foobar, " 169"}; 3'b010 : foobar = {foobar, " 170"}; 3'b011 : foobar = {foobar, " 171"}; 3'b100 : foobar = {foobar, " 172"}; 3'b101 : foobar = {foobar, " 173"}; 3'b110 : foobar = {foobar, " 174"}; 3'b111 : foobar = {foobar, " 175"}; endcase end endtask task ozoneaee; input [ 2:0] aee; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (aee) 3'b001, 3'b011, 3'b101, 3'b111 : foobar = {foobar, " 176"}; 3'b000 : foobar = {foobar, " 177"}; 3'b010 : foobar = {foobar, " 178"}; 3'b100 : foobar = {foobar, " 179"}; 3'b110 : foobar = {foobar, " 180"}; endcase end endtask task ozoneape; input [ 2:0] ape; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (ape) 3'b001, 3'b011, 3'b101, 3'b111 : foobar = {foobar, " 181"}; 3'b000 : foobar = {foobar, " 182"}; 3'b010 : foobar = {foobar, " 183"}; 3'b100 : foobar = {foobar, " 184"}; 3'b110 : foobar = {foobar, " 185"}; endcase end endtask task ozonef1; input [ 31:0] foo; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (foo[24:21]) 4'h0 : if (foo[26]) foobar = {foobar, " 186"}; else foobar = {foobar, " 187"}; 4'h1 : case (foo[26:25]) 2'b00 : foobar = {foobar, " 188"}; 2'b01 : foobar = {foobar, " 189"}; 2'b10 : foobar = {foobar, " 190"}; 2'b11 : foobar = {foobar, " 191"}; endcase 4'h2 : foobar = {foobar, " 192"}; 4'h3 : case (foo[26:25]) 2'b00 : foobar = {foobar, " 193"}; 2'b01 : foobar = {foobar, " 194"}; 2'b10 : foobar = {foobar, " 195"}; 2'b11 : foobar = {foobar, " 196"}; endcase 4'h4 : if (foo[26]) foobar = {foobar, " 197"}; else foobar = {foobar, " 198"}; 4'h5 : case (foo[26:25]) 2'b00 : foobar = {foobar, " 199"}; 2'b01 : foobar = {foobar, " 200"}; 2'b10 : foobar = {foobar, " 201"}; 2'b11 : foobar = {foobar, " 202"}; endcase 4'h6 : foobar = {foobar, " 203"}; 4'h7 : case (foo[26:25]) 2'b00 : foobar = {foobar, " 204"}; 2'b01 : foobar = {foobar, " 205"}; 2'b10 : foobar = {foobar, " 206"}; 2'b11 : foobar = {foobar, " 207"}; endcase 4'h8 : case (foo[26:25]) 2'b00 : foobar = {foobar, " 208"}; 2'b01 : foobar = {foobar, " 209"}; 2'b10 : foobar = {foobar, " 210"}; 2'b11 : foobar = {foobar, " 211"}; endcase 4'h9 : case (foo[26:25]) 2'b00 : foobar = {foobar, " 212"}; 2'b01 : foobar = {foobar, " 213"}; 2'b10 : foobar = {foobar, " 214"}; 2'b11 : foobar = {foobar, " 215"}; endcase 4'ha : if (foo[25]) foobar = {foobar, " 216"}; else foobar = {foobar, " 217"}; 4'hb : if (foo[25]) foobar = {foobar, " 218"}; else foobar = {foobar, " 219"}; 4'hc : if (foo[26]) foobar = {foobar, " 220"}; else foobar = {foobar, " 221"}; 4'hd : case (foo[26:25]) 2'b00 : foobar = {foobar, " 222"}; 2'b01 : foobar = {foobar, " 223"}; 2'b10 : foobar = {foobar, " 224"}; 2'b11 : foobar = {foobar, " 225"}; endcase 4'he : case (foo[26:25]) 2'b00 : foobar = {foobar, " 226"}; 2'b01 : foobar = {foobar, " 227"}; 2'b10 : foobar = {foobar, " 228"}; 2'b11 : foobar = {foobar, " 229"}; endcase 4'hf : case (foo[26:25]) 2'b00 : foobar = {foobar, " 230"}; 2'b01 : foobar = {foobar, " 231"}; 2'b10 : foobar = {foobar, " 232"}; 2'b11 : foobar = {foobar, " 233"}; endcase endcase end endtask task ozonef1e; input [ 31:0] foo; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (foo[27:21]) 7'h00: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 234"}; foobar = {foobar, " 235"}; end 7'h01: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 236"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 237"}; foobar = {foobar, " 238"}; end 7'h02: foobar = {foobar, " 239"}; 7'h03: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 240"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 241"}; foobar = {foobar, " 242"}; end 7'h04: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 243"}; foobar = {foobar," 244"}; end 7'h05: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 245"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 246"}; end 7'h06: foobar = {foobar, " 247"}; 7'h07: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 248"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 249"}; end 7'h08: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 250"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 251"}; end 7'h09: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 252"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 253"}; end 7'h0a: begin ozoneae(foo[17:15], foobar); foobar = {foobar," 254"}; end 7'h0b: begin ozoneae(foo[17:15], foobar); foobar = {foobar," 255"}; end 7'h0c: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 256"}; end 7'h0d: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 257"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 258"}; end 7'h0e: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 259"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 260"}; end 7'h0f: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 261"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 262"}; end 7'h10: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 263"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 264"}; foobar = {foobar, " 265"}; foobar = {foobar, " 266"}; end 7'h11: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 267"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 268"}; foobar = {foobar, " 269"}; foobar = {foobar, " 270"}; end 7'h12: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 271"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 272"}; foobar = {foobar, " 273"}; foobar = {foobar, " 274"}; end 7'h13: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 275"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 276"}; foobar = {foobar, " 277"}; foobar = {foobar, " 278"}; end 7'h14: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 279"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 280"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 281"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 282"}; foobar = {foobar, " 283"}; foobar = {foobar, " 284"}; end 7'h15: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 285"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 286"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 287"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 288"}; foobar = {foobar, " 289"}; foobar = {foobar, " 290"}; end 7'h16: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 291"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 292"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 293"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 294"}; foobar = {foobar, " 295"}; foobar = {foobar, " 296"}; end 7'h17: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 297"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 298"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 299"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 300"}; foobar = {foobar, " 301"}; foobar = {foobar, " 302"}; end 7'h18: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 303"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 304"}; foobar = {foobar, " 305"}; foobar = {foobar, " 306"}; end 7'h19: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 307"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 308"}; foobar = {foobar, " 309"}; foobar = {foobar, " 310"}; end 7'h1a: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 311"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 312"}; foobar = {foobar, " 313"}; foobar = {foobar, " 314"}; end 7'h1b: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 315"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 316"}; foobar = {foobar, " 317"}; foobar = {foobar, " 318"}; end 7'h1c: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 319"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 320"}; foobar = {foobar, " 321"}; foobar = {foobar, " 322"}; end 7'h1d: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 323"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 324"}; foobar = {foobar, " 325"}; foobar = {foobar, " 326"}; end 7'h1e: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 327"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 328"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 329"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 330"}; foobar = {foobar, " 331"}; foobar = {foobar, " 332"}; end 7'h1f: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 333"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 334"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 335"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 336"}; foobar = {foobar, " 337"}; foobar = {foobar, " 338"}; end 7'h20: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 339"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 340"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 341"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 342"}; foobar = {foobar, " 343"}; foobar = {foobar, " 344"}; end 7'h21: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 345"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 346"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 347"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 348"}; foobar = {foobar, " 349"}; foobar = {foobar, " 350"}; end 7'h22: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 351"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 352"}; foobar = {foobar, " 353"}; foobar = {foobar, " 354"}; end 7'h23: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 355"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 356"}; foobar = {foobar, " 357"}; foobar = {foobar, " 358"}; end 7'h24: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 359"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 360"}; foobar = {foobar, " 361"}; foobar = {foobar, " 362"}; end 7'h25: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 363"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 364"}; foobar = {foobar, " 365"}; foobar = {foobar, " 366"}; end 7'h26: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 367"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 368"}; foobar = {foobar, " 369"}; foobar = {foobar, " 370"}; end 7'h27: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 371"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 372"}; foobar = {foobar, " 373"}; foobar = {foobar, " 374"}; end 7'h28: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 375"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 376"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 377"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 378"}; foobar = {foobar, " 379"}; foobar = {foobar, " 380"}; end 7'h29: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 381"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 382"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 383"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 384"}; foobar = {foobar, " 385"}; foobar = {foobar, " 386"}; end 7'h2a: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 387"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 388"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 389"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 390"}; foobar = {foobar, " 391"}; foobar = {foobar, " 392"}; end 7'h2b: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 393"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 394"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 395"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 396"}; foobar = {foobar, " 397"}; foobar = {foobar, " 398"}; end 7'h2c: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 399"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 400"}; foobar = {foobar, " 401"}; foobar = {foobar, " 402"}; end 7'h2d: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 403"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 404"}; foobar = {foobar, " 405"}; foobar = {foobar, " 406"}; end 7'h2e: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 407"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 408"}; foobar = {foobar, " 409"}; foobar = {foobar, " 410"}; end 7'h2f: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 411"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 412"}; foobar = {foobar, " 413"}; foobar = {foobar, " 414"}; end 7'h30: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 415"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 416"}; foobar = {foobar, " 417"}; foobar = {foobar, " 418"}; end 7'h31: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 419"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 420"}; foobar = {foobar, " 421"}; foobar = {foobar, " 422"}; end 7'h32: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 423"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 424"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 425"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 426"}; foobar = {foobar, " 427"}; foobar = {foobar, " 428"}; end 7'h33: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 429"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 430"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 431"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 432"}; foobar = {foobar, " 433"}; foobar = {foobar, " 434"}; end 7'h34: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 435"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 436"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 437"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 438"}; foobar = {foobar, " 439"}; foobar = {foobar, " 440"}; end 7'h35: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 441"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 442"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 443"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 444"}; foobar = {foobar, " 445"}; foobar = {foobar, " 446"}; end 7'h36: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 447"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 448"}; foobar = {foobar, " 449"}; foobar = {foobar, " 450"}; end 7'h37: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 451"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 452"}; foobar = {foobar, " 453"}; foobar = {foobar, " 454"}; end 7'h38: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 455"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 456"}; foobar = {foobar, " 457"}; end 7'h39: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 458"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 459"}; foobar = {foobar, " 460"}; end 7'h3a: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 461"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 462"}; foobar = {foobar, " 463"}; end 7'h3b: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 464"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 465"}; foobar = {foobar, " 466"}; end 7'h3c: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 467"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 468"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 469"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 470"}; foobar = {foobar, " 471"}; end 7'h3d: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 472"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 473"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 474"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 475"}; foobar = {foobar, " 476"}; end 7'h3e: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 477"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 478"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 479"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 480"}; foobar = {foobar, " 481"}; end 7'h3f: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 482"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 483"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 484"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 485"}; foobar = {foobar, " 486"}; end 7'h40: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 487"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 488"}; foobar = {foobar, " 489"}; foobar = {foobar, " 490"}; end 7'h41: begin foobar = {foobar, " 491"}; foobar = {foobar, " 492"}; end 7'h42: begin foobar = {foobar, " 493"}; foobar = {foobar, " 494"}; end 7'h43: begin foobar = {foobar, " 495"}; foobar = {foobar, " 496"}; end 7'h44: begin foobar = {foobar, " 497"}; foobar = {foobar, " 498"}; end 7'h45: foobar = {foobar, " 499"}; 7'h46: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 500"}; foobar = {foobar, " 501"}; foobar = {foobar, " 502"}; end 7'h47: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 503"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 504"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 505"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 506"}; foobar = {foobar, " 507"}; foobar = {foobar, " 508"}; end 7'h48: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 509"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 510"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 511"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 512"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 513"}; end 7'h49: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 514"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 515"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 516"}; end 7'h4a: foobar = {foobar," 517"}; 7'h4b: foobar = {foobar, " 518"}; 7'h4c: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 519"}; foobar = {foobar, " 520"}; foobar = {foobar, " 521"}; end 7'h4d: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 522"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 523"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 524"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 525"}; foobar = {foobar, " 526"}; foobar = {foobar, " 527"}; end 7'h4e: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 528"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 529"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 530"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 531"}; end 7'h4f: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 532"}; end 7'h50: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 533"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 534"}; ozoneaee(foo[20:18], foobar); foobar = {foobar," 535"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 536"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 537"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 538"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 539"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 540"}; end 7'h51: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 541"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 542"}; ozoneaee(foo[20:18], foobar); foobar = {foobar," 543"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 544"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 545"}; end 7'h52: foobar = {foobar, " 546"}; 7'h53: begin ozoneae(foo[20:18], foobar); foobar = {foobar, " 547"}; end 7'h54: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 548"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 549"}; end 7'h55: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 550"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 551"}; end 7'h56: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 552"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 553"}; foobar = {foobar, " 554"}; end 7'h57: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 555"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 556"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 557"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 558"}; end 7'h58: begin ozoneae(foo[20:18], foobar); foobar = {foobar, " 559"}; end 7'h59: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 560"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 561"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 562"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 563"}; end 7'h5a: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 564"}; ozoneae(foo[17:15], foobar); foobar = {foobar, " 565"}; end 7'h5b: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 566"}; ozoneae(foo[17:15], foobar); foobar = {foobar, " 567"}; end 7'h5c: begin foobar = {foobar," 568"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 569"}; foobar = {foobar," 570"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 571"}; ozoneae(foo[20:18], foobar); foobar = {foobar," 572"}; ozoneaee(foo[17:15], foobar); foobar = {foobar, " 573"}; end 7'h5d: begin foobar = {foobar," 574"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 575"}; foobar = {foobar," 576"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 577"}; ozoneae(foo[20:18], foobar); foobar = {foobar," 578"}; ozoneaee(foo[17:15], foobar); foobar = {foobar, " 579"}; end 7'h5e: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 580"}; ozoneae(foo[17:15], foobar); foobar = {foobar, " 581"}; end 7'h5f: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 582"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 583"}; ozoneaee(foo[20:18], foobar); foobar = {foobar," 584"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 585"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 586"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 587"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 588"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 589"}; end 7'h60: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 590"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 591"}; end 7'h61: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 592"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 593"}; end 7'h62: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 594"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 595"}; end 7'h63: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 596"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 597"}; end 7'h64: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 598"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 599"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 600"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 601"}; end 7'h65: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 602"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 603"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 604"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 605"}; end 7'h66: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 606"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 607"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 608"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 609"}; end 7'h67: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 610"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 611"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 612"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 613"}; end 7'h68: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 614"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 615"}; ozoneaee(foo[20:18], foobar); foobar = {foobar," 616"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 617"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 618"}; ozoneape(foo[17:15], foobar); end 7'h69: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 619"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 620"}; ozoneae(foo[20:18], foobar); foobar = {foobar," 621"}; end 7'h6a: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 622"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 623"}; ozoneaee(foo[20:18], foobar); foobar = {foobar," 624"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 625"}; ozoneaee(foo[20:18], foobar); foobar = {foobar," 626"}; ozoneae(foo[17:15], foobar); end 7'h6b: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 627"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 628"}; ozoneae(foo[20:18], foobar); foobar = {foobar," 629"}; end 7'h6c: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 630"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 631"}; ozoneaee(foo[20:18], foobar); foobar = {foobar," 632"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 633"}; ozoneaee(foo[20:18], foobar); foobar = {foobar," 634"}; ozoneae(foo[17:15], foobar); end 7'h6d: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 635"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 636"}; ozoneae(foo[20:18], foobar); foobar = {foobar," 637"}; end 7'h6e: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 638"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 639"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 640"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 641"}; end 7'h6f: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 642"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 643"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 644"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 645"}; end 7'h70: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 646"}; ozoneae(foo[20:18], foobar); foobar = {foobar," 647"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 648"}; ozoneae(foo[17:15], foobar); foobar = {foobar, " 649"}; end 7'h71: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 650"}; ozoneae(foo[17:15], foobar); foobar = {foobar, " 651"}; end 7'h72: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 652"}; ozoneae(foo[17:15], foobar); foobar = {foobar, " 653"}; end 7'h73: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 654"}; ozoneae(foo[20:18], foobar); foobar = {foobar," 655"}; ozoneae(foo[17:15], foobar); end 7'h74: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 656"}; ozoneae(foo[20:18], foobar); foobar = {foobar," 657"}; ozoneae(foo[17:15], foobar); end 7'h75: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 658"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 659"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 660"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 661"}; foobar = {foobar, " 662"}; foobar = {foobar, " 663"}; end 7'h76: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 664"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 665"}; ozoneaee(foo[20:18], foobar); foobar = {foobar," 666"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 667"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 668"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 669"}; end 7'h77: begin ozoneaee(foo[20:18], foobar); foobar = {foobar," 670"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 671"}; ozoneaee(foo[17:15], foobar); foobar = {foobar," 672"}; ozoneape(foo[20:18], foobar); foobar = {foobar," 673"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 674"}; ozoneape(foo[17:15], foobar); foobar = {foobar," 675"}; end 7'h78, 7'h79, 7'h7a, 7'h7b, 7'h7c, 7'h7d, 7'h7e, 7'h7f: foobar = {foobar," 676"}; endcase end endtask task ozonef2; input [ 31:0] foo; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (foo[24:21]) 4'h0 : case (foo[26:25]) 2'b00 : foobar = {foobar," 677"}; 2'b01 : foobar = {foobar," 678"}; 2'b10 : foobar = {foobar," 679"}; 2'b11 : foobar = {foobar," 680"}; endcase 4'h1 : case (foo[26:25]) 2'b00 : foobar = {foobar," 681"}; 2'b01 : foobar = {foobar," 682"}; 2'b10 : foobar = {foobar," 683"}; 2'b11 : foobar = {foobar," 684"}; endcase 4'h2 : case (foo[26:25]) 2'b00 : foobar = {foobar," 685"}; 2'b01 : foobar = {foobar," 686"}; 2'b10 : foobar = {foobar," 687"}; 2'b11 : foobar = {foobar," 688"}; endcase 4'h3 : case (foo[26:25]) 2'b00 : foobar = {foobar," 689"}; 2'b01 : foobar = {foobar," 690"}; 2'b10 : foobar = {foobar," 691"}; 2'b11 : foobar = {foobar," 692"}; endcase 4'h4 : case (foo[26:25]) 2'b00 : foobar = {foobar," 693"}; 2'b01 : foobar = {foobar," 694"}; 2'b10 : foobar = {foobar," 695"}; 2'b11 : foobar = {foobar," 696"}; endcase 4'h5 : case (foo[26:25]) 2'b00 : foobar = {foobar," 697"}; 2'b01 : foobar = {foobar," 698"}; 2'b10 : foobar = {foobar," 699"}; 2'b11 : foobar = {foobar," 700"}; endcase 4'h6 : case (foo[26:25]) 2'b00 : foobar = {foobar," 701"}; 2'b01 : foobar = {foobar," 702"}; 2'b10 : foobar = {foobar," 703"}; 2'b11 : foobar = {foobar," 704"}; endcase 4'h7 : case (foo[26:25]) 2'b00 : foobar = {foobar," 705"}; 2'b01 : foobar = {foobar," 706"}; 2'b10 : foobar = {foobar," 707"}; 2'b11 : foobar = {foobar," 708"}; endcase 4'h8 : if (foo[26]) foobar = {foobar," 709"}; else foobar = {foobar," 710"}; 4'h9 : case (foo[26:25]) 2'b00 : foobar = {foobar," 711"}; 2'b01 : foobar = {foobar," 712"}; 2'b10 : foobar = {foobar," 713"}; 2'b11 : foobar = {foobar," 714"}; endcase 4'ha : case (foo[26:25]) 2'b00 : foobar = {foobar," 715"}; 2'b01 : foobar = {foobar," 716"}; 2'b10 : foobar = {foobar," 717"}; 2'b11 : foobar = {foobar," 718"}; endcase 4'hb : case (foo[26:25]) 2'b00 : foobar = {foobar," 719"}; 2'b01 : foobar = {foobar," 720"}; 2'b10 : foobar = {foobar," 721"}; 2'b11 : foobar = {foobar," 722"}; endcase 4'hc : if (foo[26]) foobar = {foobar," 723"}; else foobar = {foobar," 724"}; 4'hd : case (foo[26:25]) 2'b00 : foobar = {foobar," 725"}; 2'b01 : foobar = {foobar," 726"}; 2'b10 : foobar = {foobar," 727"}; 2'b11 : foobar = {foobar," 728"}; endcase 4'he : case (foo[26:25]) 2'b00 : foobar = {foobar," 729"}; 2'b01 : foobar = {foobar," 730"}; 2'b10 : foobar = {foobar," 731"}; 2'b11 : foobar = {foobar," 732"}; endcase 4'hf : case (foo[26:25]) 2'b00 : foobar = {foobar," 733"}; 2'b01 : foobar = {foobar," 734"}; 2'b10 : foobar = {foobar," 735"}; 2'b11 : foobar = {foobar," 736"}; endcase endcase end endtask task ozonef2e; input [ 31:0] foo; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin casez (foo[25:21]) 5'h00 : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 737"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 738"}; end 5'h01 : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 739"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 740"}; end 5'h02 : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 741"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 742"}; end 5'h03 : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 743"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 744"}; end 5'h04 : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 745"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 746"}; end 5'h05 : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 747"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 748"}; end 5'h06 : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 749"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 750"}; end 5'h07 : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 751"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 752"}; end 5'h08 : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 753"}; if (foo[ 6]) foobar = {foobar," 754"}; else foobar = {foobar," 755"}; end 5'h09 : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 756"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 757"}; end 5'h0a : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 758"}; ozoneae(foo[17:15], foobar); end 5'h0b : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 759"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 760"}; end 5'h0c : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 761"}; end 5'h0d : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 762"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 763"}; end 5'h0e : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 764"}; ozoneae(foo[17:15], foobar); end 5'h0f : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 765"}; ozoneae(foo[17:15], foobar); end 5'h10 : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 766"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 767"}; end 5'h11 : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 768"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 769"}; end 5'h18 : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 770"}; if (foo[ 6]) foobar = {foobar," 771"}; else foobar = {foobar," 772"}; end 5'h1a : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 773"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 774"}; end 5'h1b : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 775"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 776"}; if (foo[ 6]) foobar = {foobar," 777"}; else foobar = {foobar," 778"}; foobar = {foobar," 779"}; end 5'h1c : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 780"}; end 5'h1d : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 781"}; if (foo[ 6]) foobar = {foobar," 782"}; else foobar = {foobar," 783"}; foobar = {foobar," 784"}; end 5'h1e : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 785"}; if (foo[ 6]) foobar = {foobar," 786"}; else foobar = {foobar," 787"}; foobar = {foobar," 788"}; end 5'h1f : begin ozoneae(foo[20:18], foobar); foobar = {foobar," 789"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 790"}; if (foo[ 6]) foobar = {foobar," 791"}; else foobar = {foobar," 792"}; foobar = {foobar," 793"}; end default : foobar = {foobar," 794"}; endcase end endtask task ozonef3e; input [ 31:0] foo; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (foo[25:21]) 5'h00, 5'h01, 5'h02: begin ozoneae(foo[20:18], foobar); case (foo[22:21]) 2'h0: foobar = {foobar," 795"}; 2'h1: foobar = {foobar," 796"}; 2'h2: foobar = {foobar," 797"}; endcase ozoneae(foo[17:15], foobar); foobar = {foobar," 798"}; if (foo[ 9]) ozoneae(foo[ 8: 6], foobar); else ozonef3e_te(foo[ 8: 6], foobar); foobar = {foobar," 799"}; end 5'h08, 5'h09, 5'h0d, 5'h0e, 5'h0f: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 800"}; ozoneae(foo[17:15], foobar); case (foo[23:21]) 3'h0: foobar = {foobar," 801"}; 3'h1: foobar = {foobar," 802"}; 3'h5: foobar = {foobar," 803"}; 3'h6: foobar = {foobar," 804"}; 3'h7: foobar = {foobar," 805"}; endcase if (foo[ 9]) ozoneae(foo[ 8: 6], foobar); else ozonef3e_te(foo[ 8: 6], foobar); end 5'h0a, 5'h0b: begin ozoneae(foo[17:15], foobar); if (foo[21]) foobar = {foobar," 806"}; else foobar = {foobar," 807"}; if (foo[ 9]) ozoneae(foo[ 8: 6], foobar); else ozonef3e_te(foo[ 8: 6], foobar); end 5'h0c: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 808"}; if (foo[ 9]) ozoneae(foo[ 8: 6], foobar); else ozonef3e_te(foo[ 8: 6], foobar); foobar = {foobar," 809"}; ozoneae(foo[17:15], foobar); end 5'h10, 5'h11, 5'h12, 5'h13: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 810"}; ozoneae(foo[17:15], foobar); case (foo[22:21]) 2'h0, 2'h2: foobar = {foobar," 811"}; 2'h1, 2'h3: foobar = {foobar," 812"}; endcase ozoneae(foo[ 8: 6], foobar); foobar = {foobar," 813"}; ozoneae((foo[20:18]+1), foobar); foobar = {foobar," 814"}; ozoneae((foo[17:15]+1), foobar); case (foo[22:21]) 2'h0, 2'h3: foobar = {foobar," 815"}; 2'h1, 2'h2: foobar = {foobar," 816"}; endcase ozoneae((foo[ 8: 6]+1), foobar); end 5'h18: begin ozoneae(foo[20:18], foobar); foobar = {foobar," 817"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 818"}; ozoneae(foo[ 8: 6], foobar); foobar = {foobar," 819"}; ozoneae(foo[20:18], foobar); foobar = {foobar," 820"}; ozoneae(foo[17:15], foobar); foobar = {foobar," 821"}; ozoneae(foo[ 8: 6], foobar); end default : foobar = {foobar," 822"}; endcase end endtask task ozonef3e_te; input [ 2:0] te; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (te) 3'b100 : foobar = {foobar, " 823"}; 3'b101 : foobar = {foobar, " 824"}; 3'b110 : foobar = {foobar, " 825"}; default: foobar = {foobar, " 826"}; endcase end endtask task ozonearm; input [ 2:0] ate; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (ate) 3'b000 : foobar = {foobar, " 827"}; 3'b001 : foobar = {foobar, " 828"}; 3'b010 : foobar = {foobar, " 829"}; 3'b011 : foobar = {foobar, " 830"}; 3'b100 : foobar = {foobar, " 831"}; 3'b101 : foobar = {foobar, " 832"}; 3'b110 : foobar = {foobar, " 833"}; 3'b111 : foobar = {foobar, " 834"}; endcase end endtask task ozonebmuop; input [ 4:0] f4; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (f4[ 4:0]) 5'h00, 5'h04 : foobar = {foobar, " 835"}; 5'h01, 5'h05 : foobar = {foobar, " 836"}; 5'h02, 5'h06 : foobar = {foobar, " 837"}; 5'h03, 5'h07 : foobar = {foobar, " 838"}; 5'h08, 5'h18 : foobar = {foobar, " 839"}; 5'h09, 5'h19 : foobar = {foobar, " 840"}; 5'h0a, 5'h1a : foobar = {foobar, " 841"}; 5'h0b : foobar = {foobar, " 842"}; 5'h1b : foobar = {foobar, " 843"}; 5'h0c, 5'h1c : foobar = {foobar, " 844"}; 5'h0d, 5'h1d : foobar = {foobar, " 845"}; 5'h1e : foobar = {foobar, " 846"}; endcase end endtask task automatic ozonef3; input [ 31:0] foo; inout [STRLEN*8: 1] foobar; reg nacho; // verilator no_inline_task begin : f3_body nacho = 1'b0; case (foo[24:21]) 4'h0: case (foo[26:25]) 2'b00 : foobar = {foobar, " 847"}; 2'b01 : foobar = {foobar, " 848"}; 2'b10 : foobar = {foobar, " 849"}; 2'b11 : foobar = {foobar, " 850"}; endcase 4'h1: case (foo[26:25]) 2'b00 : foobar = {foobar, " 851"}; 2'b01 : foobar = {foobar, " 852"}; 2'b10 : foobar = {foobar, " 853"}; 2'b11 : foobar = {foobar, " 854"}; endcase 4'h2: case (foo[26:25]) 2'b00 : foobar = {foobar, " 855"}; 2'b01 : foobar = {foobar, " 856"}; 2'b10 : foobar = {foobar, " 857"}; 2'b11 : foobar = {foobar, " 858"}; endcase 4'h8, 4'h9, 4'hd, 4'he, 4'hf : case (foo[26:25]) 2'b00 : foobar = {foobar, " 859"}; 2'b01 : foobar = {foobar, " 860"}; 2'b10 : foobar = {foobar, " 861"}; 2'b11 : foobar = {foobar, " 862"}; endcase 4'ha, 4'hb : if (foo[25]) foobar = {foobar, " 863"}; else foobar = {foobar, " 864"}; 4'hc : if (foo[26]) foobar = {foobar, " 865"}; else foobar = {foobar, " 866"}; default : begin foobar = {foobar, " 867"}; nacho = 1'b1; end endcase if (~nacho) begin case (foo[24:21]) 4'h8 : foobar = {foobar, " 868"}; 4'h9 : foobar = {foobar, " 869"}; 4'ha, 4'he : foobar = {foobar, " 870"}; 4'hb, 4'hf : foobar = {foobar, " 871"}; 4'hd : foobar = {foobar, " 872"}; endcase if (foo[20]) case (foo[18:16]) 3'b000 : foobar = {foobar, " 873"}; 3'b100 : foobar = {foobar, " 874"}; default: foobar = {foobar, " 875"}; endcase else ozoneae(foo[18:16], foobar); if (foo[24:21] === 4'hc) if (foo[25]) foobar = {foobar, " 876"}; else foobar = {foobar, " 877"}; case (foo[24:21]) 4'h0, 4'h1, 4'h2: foobar = {foobar, " 878"}; endcase end end endtask task ozonerx; input [ 31:0] foo; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (foo[19:18]) 2'h0 : foobar = {foobar, " 879"}; 2'h1 : foobar = {foobar, " 880"}; 2'h2 : foobar = {foobar, " 881"}; 2'h3 : foobar = {foobar, " 882"}; endcase case (foo[17:16]) 2'h1 : foobar = {foobar, " 883"}; 2'h2 : foobar = {foobar, " 884"}; 2'h3 : foobar = {foobar, " 885"}; endcase end endtask task ozonerme; input [ 2:0] rme; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (rme) 3'h0 : foobar = {foobar, " 886"}; 3'h1 : foobar = {foobar, " 887"}; 3'h2 : foobar = {foobar, " 888"}; 3'h3 : foobar = {foobar, " 889"}; 3'h4 : foobar = {foobar, " 890"}; 3'h5 : foobar = {foobar, " 891"}; 3'h6 : foobar = {foobar, " 892"}; 3'h7 : foobar = {foobar, " 893"}; endcase end endtask task ozoneye; input [5:0] ye; input l; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin foobar = {foobar, " 894"}; ozonerme(ye[5:3],foobar); case ({ye[ 2:0], l}) 4'h2, 4'ha: foobar = {foobar, " 895"}; 4'h4, 4'hb: foobar = {foobar, " 896"}; 4'h6, 4'he: foobar = {foobar, " 897"}; 4'h8, 4'hc: foobar = {foobar, " 898"}; endcase end endtask task ozonef1e_ye; input [5:0] ye; input l; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin foobar = {foobar, " 899"}; ozonerme(ye[5:3],foobar); ozonef1e_inc_dec(ye[5:0], l ,foobar); end endtask task ozonef1e_h; input [ 2:0] e; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin if (e[ 2:0] <= 3'h4) foobar = {foobar, " 900"}; end endtask task ozonef1e_inc_dec; input [5:0] ye; input l; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case ({ye[ 2:0], l}) 4'h2, 4'h3, 4'ha: foobar = {foobar, " 901"}; 4'h4, 4'h5, 4'hb: foobar = {foobar, " 902"}; 4'h6, 4'h7, 4'he: foobar = {foobar, " 903"}; 4'h8, 4'h9, 4'hc: foobar = {foobar, " 904"}; 4'hf: foobar = {foobar, " 905"}; endcase end endtask task ozonef1e_hl; input [ 2:0] e; input l; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case ({e[ 2:0], l}) 4'h0, 4'h2, 4'h4, 4'h6, 4'h8: foobar = {foobar, " 906"}; 4'h1, 4'h3, 4'h5, 4'h7, 4'h9: foobar = {foobar, " 907"}; endcase end endtask task ozonexe; input [ 3:0] xe; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (xe[3]) 1'b0 : foobar = {foobar, " 908"}; 1'b1 : foobar = {foobar, " 909"}; endcase case (xe[ 2:0]) 3'h1, 3'h5: foobar = {foobar, " 910"}; 3'h2, 3'h6: foobar = {foobar, " 911"}; 3'h3, 3'h7: foobar = {foobar, " 912"}; 3'h4: foobar = {foobar, " 913"}; endcase end endtask task ozonerp; input [ 2:0] rp; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (rp) 3'h0 : foobar = {foobar, " 914"}; 3'h1 : foobar = {foobar, " 915"}; 3'h2 : foobar = {foobar, " 916"}; 3'h3 : foobar = {foobar, " 917"}; 3'h4 : foobar = {foobar, " 918"}; 3'h5 : foobar = {foobar, " 919"}; 3'h6 : foobar = {foobar, " 920"}; 3'h7 : foobar = {foobar, " 921"}; endcase end endtask task ozonery; input [ 3:0] ry; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (ry) 4'h0 : foobar = {foobar, " 922"}; 4'h1 : foobar = {foobar, " 923"}; 4'h2 : foobar = {foobar, " 924"}; 4'h3 : foobar = {foobar, " 925"}; 4'h4 : foobar = {foobar, " 926"}; 4'h5 : foobar = {foobar, " 927"}; 4'h6 : foobar = {foobar, " 928"}; 4'h7 : foobar = {foobar, " 929"}; 4'h8 : foobar = {foobar, " 930"}; 4'h9 : foobar = {foobar, " 931"}; 4'ha : foobar = {foobar, " 932"}; 4'hb : foobar = {foobar, " 933"}; 4'hc : foobar = {foobar, " 934"}; 4'hd : foobar = {foobar, " 935"}; 4'he : foobar = {foobar, " 936"}; 4'hf : foobar = {foobar, " 937"}; endcase end endtask task ozonearx; input [ 15:0] foo; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (foo[1:0]) 2'h0 : foobar = {foobar, " 938"}; 2'h1 : foobar = {foobar, " 939"}; 2'h2 : foobar = {foobar, " 940"}; 2'h3 : foobar = {foobar, " 941"}; endcase end endtask task ozonef3f4imop; input [ 4:0] f3f4iml; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin casez (f3f4iml) 5'b000??: foobar = {foobar, " 942"}; 5'b001??: foobar = {foobar, " 943"}; 5'b?10??: foobar = {foobar, " 944"}; 5'b0110?: foobar = {foobar, " 945"}; 5'b01110: foobar = {foobar, " 946"}; 5'b01111: foobar = {foobar, " 947"}; 5'b10???: foobar = {foobar, " 948"}; 5'b11100: foobar = {foobar, " 949"}; 5'b11101: foobar = {foobar, " 950"}; 5'b11110: foobar = {foobar, " 951"}; 5'b11111: foobar = {foobar, " 952"}; endcase end endtask task ozonecon; input [ 4:0] con; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (con) 5'h00 : foobar = {foobar, " 953"}; 5'h01 : foobar = {foobar, " 954"}; 5'h02 : foobar = {foobar, " 955"}; 5'h03 : foobar = {foobar, " 956"}; 5'h04 : foobar = {foobar, " 957"}; 5'h05 : foobar = {foobar, " 958"}; 5'h06 : foobar = {foobar, " 959"}; 5'h07 : foobar = {foobar, " 960"}; 5'h08 : foobar = {foobar, " 961"}; 5'h09 : foobar = {foobar, " 962"}; 5'h0a : foobar = {foobar, " 963"}; 5'h0b : foobar = {foobar, " 964"}; 5'h0c : foobar = {foobar, " 965"}; 5'h0d : foobar = {foobar, " 966"}; 5'h0e : foobar = {foobar, " 967"}; 5'h0f : foobar = {foobar, " 968"}; 5'h10 : foobar = {foobar, " 969"}; 5'h11 : foobar = {foobar, " 970"}; 5'h12 : foobar = {foobar, " 971"}; 5'h13 : foobar = {foobar, " 972"}; 5'h14 : foobar = {foobar, " 973"}; 5'h15 : foobar = {foobar, " 974"}; 5'h16 : foobar = {foobar, " 975"}; 5'h17 : foobar = {foobar, " 976"}; 5'h18 : foobar = {foobar, " 977"}; 5'h19 : foobar = {foobar, " 978"}; 5'h1a : foobar = {foobar, " 979"}; 5'h1b : foobar = {foobar, " 980"}; 5'h1c : foobar = {foobar, " 981"}; 5'h1d : foobar = {foobar, " 982"}; 5'h1e : foobar = {foobar, " 983"}; 5'h1f : foobar = {foobar, " 984"}; endcase end endtask task ozonedr; input [ 15:0] foo; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (foo[ 9: 6]) 4'h0 : foobar = {foobar, " 985"}; 4'h1 : foobar = {foobar, " 986"}; 4'h2 : foobar = {foobar, " 987"}; 4'h3 : foobar = {foobar, " 988"}; 4'h4 : foobar = {foobar, " 989"}; 4'h5 : foobar = {foobar, " 990"}; 4'h6 : foobar = {foobar, " 991"}; 4'h7 : foobar = {foobar, " 992"}; 4'h8 : foobar = {foobar, " 993"}; 4'h9 : foobar = {foobar, " 994"}; 4'ha : foobar = {foobar, " 995"}; 4'hb : foobar = {foobar, " 996"}; 4'hc : foobar = {foobar, " 997"}; 4'hd : foobar = {foobar, " 998"}; 4'he : foobar = {foobar, " 999"}; 4'hf : foobar = {foobar, " 1000"}; endcase end endtask task ozoneshift; input [ 15:0] foo; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (foo[ 4: 3]) 2'h0 : foobar = {foobar, " 1001"}; 2'h1 : foobar = {foobar, " 1002"}; 2'h2 : foobar = {foobar, " 1003"}; 2'h3 : foobar = {foobar, " 1004"}; endcase end endtask task ozoneacc; input foo; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (foo) 2'h0 : foobar = {foobar, " 1005"}; 2'h1 : foobar = {foobar, " 1006"}; endcase end endtask task ozonehl; input foo; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin case (foo) 2'h0 : foobar = {foobar, " 1007"}; 2'h1 : foobar = {foobar, " 1008"}; endcase end endtask task automatic dude; inout [STRLEN*8: 1] foobar; reg [ 7:0] temp; integer i; reg nacho; // verilator no_inline_task begin : justify_block nacho = 1'b0; for (i=STRLEN-1; i>1; i=i-1) begin temp = foobar>>((STRLEN-1)*8); if (temp || nacho) nacho = 1'b1; else begin foobar = foobar<<8; foobar[8:1] = 32; end end end endtask task automatic big_case; input [ 31:0] fd; input [ 31:0] foo; reg [STRLEN*8: 1] foobar; // verilator no_inline_task begin foobar = " 1009"; if (&foo === 1'bx) $fwrite(fd, " 1010"); else casez ( {foo[31:26], foo[19:15], foo[5:0]} ) 17'b00_111?_?_????_??_???? : begin ozonef1(foo, foobar); foobar = {foobar, " 1011"}; ozoneacc(~foo[26], foobar); ozonehl(foo[20], foobar); foobar = {foobar, " 1012"}; ozonerx(foo, foobar); dude(foobar); $fwrite (fd, " 1013:%s", foobar); end 17'b01_001?_?_????_??_???? : begin ozonef1(foo, foobar); foobar = {foobar, " 1014"}; ozonerx(foo, foobar); foobar = {foobar, " 1015"}; foobar = {foobar, " 1016"}; ozonehl(foo[20], foobar); dude(foobar); $fwrite (fd, " 1017:%s", foobar); end 17'b10_100?_?_????_??_???? : begin ozonef1(foo, foobar); foobar = {foobar, " 1018"}; ozonerx(foo, foobar); foobar = {foobar, " 1019"}; foobar = {foobar, " 1020"}; ozonehl(foo[20], foobar); dude(foobar); $fwrite (fd, " 1021:%s", foobar); end 17'b10_101?_?_????_??_???? : begin ozonef1(foo, foobar); foobar = {foobar, " 1022"}; if (foo[20]) begin foobar = {foobar, " 1023"}; ozoneacc(foo[18], foobar); foobar = {foobar, " 1024"}; foobar = {foobar, " 1025"}; if (foo[19]) foobar = {foobar, " 1026"}; else foobar = {foobar, " 1027"}; end else ozonerx(foo, foobar); dude(foobar); $fwrite (fd, " 1028:%s", foobar); end 17'b10_110?_?_????_??_???? : begin ozonef1(foo, foobar); foobar = {foobar, " 1029"}; foobar = {foobar, " 1030"}; ozonehl(foo[20], foobar); foobar = {foobar, " 1031"}; ozonerx(foo, foobar); dude(foobar); $fwrite (fd, " 1032:%s", foobar); end 17'b10_111?_?_????_??_???? : begin ozonef1(foo, foobar); foobar = {foobar, " 1033"}; foobar = {foobar, " 1034"}; ozonehl(foo[20], foobar); foobar = {foobar, " 1035"}; ozonerx(foo, foobar); dude(foobar); $fwrite (fd, " 1036:%s", foobar); end 17'b11_001?_?_????_??_???? : begin ozonef1(foo, foobar); foobar = {foobar, " 1037"}; ozonerx(foo, foobar); foobar = {foobar, " 1038"}; foobar = {foobar, " 1039"}; ozonehl(foo[20], foobar); dude(foobar); $fwrite (fd, " 1040:%s", foobar); end 17'b11_111?_?_????_??_???? : begin ozonef1(foo, foobar); foobar = {foobar, " 1041"}; foobar = {foobar, " 1042"}; ozonerx(foo, foobar); foobar = {foobar, " 1043"}; if (foo[20]) foobar = {foobar, " 1044"}; else foobar = {foobar, " 1045"}; dude(foobar); $fwrite (fd, " 1046:%s", foobar); end 17'b00_10??_?_????_?1_1111 : casez (foo[11: 5]) 7'b??_0_010_0: begin foobar = " 1047"; ozonecon(foo[14:10], foobar); foobar = {foobar, " 1048"}; ozonef1e(foo, foobar); dude(foobar); $fwrite (fd, " 1049:%s", foobar); end 7'b00_?_110_?: begin ozonef1e(foo, foobar); foobar = {foobar, " 1050"}; case ({foo[ 9],foo[ 5]}) 2'b00: begin foobar = {foobar, " 1051"}; ozoneae(foo[14:12], foobar); ozonehl(foo[ 5], foobar); end 2'b01: begin foobar = {foobar, " 1052"}; ozoneae(foo[14:12], foobar); ozonehl(foo[ 5], foobar); end 2'b10: begin foobar = {foobar, " 1053"}; ozoneae(foo[14:12], foobar); end 2'b11: foobar = {foobar, " 1054"}; endcase dude(foobar); $fwrite (fd, " 1055:%s", foobar); end 7'b01_?_110_?: begin ozonef1e(foo, foobar); foobar = {foobar, " 1056"}; case ({foo[ 9],foo[ 5]}) 2'b00: begin ozoneae(foo[14:12], foobar); ozonehl(foo[ 5], foobar); foobar = {foobar, " 1057"}; end 2'b01: begin ozoneae(foo[14:12], foobar); ozonehl(foo[ 5], foobar); foobar = {foobar, " 1058"}; end 2'b10: begin ozoneae(foo[14:12], foobar); foobar = {foobar, " 1059"}; end 2'b11: foobar = {foobar, " 1060"}; endcase dude(foobar); $fwrite (fd, " 1061:%s", foobar); end 7'b10_0_110_0: begin ozonef1e(foo, foobar); foobar = {foobar, " 1062"}; foobar = {foobar, " 1063"}; if (foo[12]) foobar = {foobar, " 1064"}; else ozonerab({4'b1001, foo[14:12]}, foobar); dude(foobar); $fwrite (fd, " 1065:%s", foobar); end 7'b10_0_110_1: begin ozonef1e(foo, foobar); foobar = {foobar, " 1066"}; if (foo[12]) foobar = {foobar, " 1067"}; else ozonerab({4'b1001, foo[14:12]}, foobar); foobar = {foobar, " 1068"}; dude(foobar); $fwrite (fd, " 1069:%s", foobar); end 7'b??_?_000_?: begin ozonef1e(foo, foobar); foobar = {foobar, " 1070"}; foobar = {foobar, " 1071"}; ozonef1e_hl(foo[11:9],foo[ 5],foobar); foobar = {foobar, " 1072"}; ozonef1e_ye(foo[14:9],foo[ 5],foobar); dude(foobar); $fwrite (fd, " 1073:%s", foobar); end 7'b??_?_100_?: begin ozonef1e(foo, foobar); foobar = {foobar, " 1074"}; foobar = {foobar, " 1075"}; ozonef1e_hl(foo[11:9],foo[ 5],foobar); foobar = {foobar, " 1076"}; ozonef1e_ye(foo[14:9],foo[ 5],foobar); dude(foobar); $fwrite (fd, " 1077:%s", foobar); end 7'b??_?_001_?: begin ozonef1e(foo, foobar); foobar = {foobar, " 1078"}; ozonef1e_ye(foo[14:9],foo[ 5],foobar); foobar = {foobar, " 1079"}; foobar = {foobar, " 1080"}; ozonef1e_hl(foo[11:9],foo[ 5],foobar); dude(foobar); $fwrite (fd, " 1081:%s", foobar); end 7'b??_?_011_?: begin ozonef1e(foo, foobar); foobar = {foobar, " 1082"}; ozonef1e_ye(foo[14:9],foo[ 5],foobar); foobar = {foobar, " 1083"}; foobar = {foobar, " 1084"}; ozonef1e_hl(foo[11:9],foo[ 5],foobar); dude(foobar); $fwrite (fd, " 1085:%s", foobar); end 7'b??_?_101_?: begin ozonef1e(foo, foobar); foobar = {foobar, " 1086"}; ozonef1e_ye(foo[14:9],foo[ 5],foobar); dude(foobar); $fwrite (fd, " 1087:%s", foobar); end endcase 17'b00_10??_?_????_?0_0110 : begin ozonef1e(foo, foobar); foobar = {foobar, " 1088"}; ozoneae(foo[ 8: 6], foobar); ozonef1e_hl(foo[11:9],foo[ 5],foobar); foobar = {foobar, " 1089"}; ozonef1e_ye(foo[14:9],foo[ 5],foobar); dude(foobar); $fwrite (fd, " 1090:%s", foobar); end 17'b00_10??_?_????_00_0111 : begin ozonef1e(foo, foobar); foobar = {foobar, " 1091"}; if (foo[ 6]) foobar = {foobar, " 1092"}; else ozonerab({4'b1001, foo[ 8: 6]}, foobar); foobar = {foobar, " 1093"}; foobar = {foobar, " 1094"}; ozonerme(foo[14:12],foobar); case (foo[11: 9]) 3'h2, 3'h5, 3'h6, 3'h7: ozonef1e_inc_dec(foo[14:9],1'b0,foobar); 3'h1, 3'h3, 3'h4: foobar = {foobar, " 1095"}; endcase dude(foobar); $fwrite (fd, " 1096:%s", foobar); end 17'b00_10??_?_????_?0_0100 : begin ozonef1e(foo, foobar); foobar = {foobar, " 1097"}; ozonef1e_ye(foo[14:9],foo[ 5],foobar); foobar = {foobar, " 1098"}; ozoneae(foo[ 8: 6], foobar); ozonef1e_hl(foo[11:9],foo[ 5],foobar); dude(foobar); $fwrite (fd, " 1099:%s", foobar); end 17'b00_10??_?_????_10_0111 : begin ozonef1e(foo, foobar); foobar = {foobar, " 1100"}; foobar = {foobar, " 1101"}; ozonerme(foo[14:12],foobar); case (foo[11: 9]) 3'h2, 3'h5, 3'h6, 3'h7: ozonef1e_inc_dec(foo[14:9],1'b0,foobar); 3'h1, 3'h3, 3'h4: foobar = {foobar, " 1102"}; endcase foobar = {foobar, " 1103"}; if (foo[ 6]) foobar = {foobar, " 1104"}; else ozonerab({4'b1001, foo[ 8: 6]}, foobar); dude(foobar); $fwrite (fd, " 1105:%s", foobar); end 17'b00_10??_?_????_?0_1110 : begin ozonef1e(foo, foobar); foobar = {foobar, " 1106"}; case (foo[11:9]) 3'h2: begin foobar = {foobar, " 1107"}; if (foo[14:12] == 3'h0) foobar = {foobar, " 1108"}; else ozonerme(foo[14:12],foobar); foobar = {foobar, " 1109"}; end 3'h6: begin foobar = {foobar, " 1110"}; if (foo[14:12] == 3'h0) foobar = {foobar, " 1111"}; else ozonerme(foo[14:12],foobar); foobar = {foobar, " 1112"}; end 3'h0: begin foobar = {foobar, " 1113"}; if (foo[14:12] == 3'h0) foobar = {foobar, " 1114"}; else ozonerme(foo[14:12],foobar); foobar = {foobar, " 1115"}; if (foo[ 7: 5] >= 3'h5) foobar = {foobar, " 1116"}; else ozonexe(foo[ 8: 5], foobar); end 3'h1: begin foobar = {foobar, " 1117"}; if (foo[14:12] == 3'h0) foobar = {foobar, " 1118"}; else ozonerme(foo[14:12],foobar); foobar = {foobar, " 1119"}; if (foo[ 7: 5] >= 3'h5) foobar = {foobar, " 1120"}; else ozonexe(foo[ 8: 5], foobar); end 3'h4: begin foobar = {foobar, " 1121"}; if (foo[14:12] == 3'h0) foobar = {foobar, " 1122"}; else ozonerme(foo[14:12],foobar); foobar = {foobar, " 1123"}; if (foo[ 7: 5] >= 3'h5) foobar = {foobar, " 1124"}; else ozonexe(foo[ 8: 5], foobar); end 3'h5: begin foobar = {foobar, " 1125"}; if (foo[14:12] == 3'h0) foobar = {foobar, " 1126"}; else ozonerme(foo[14:12],foobar); foobar = {foobar, " 1127"}; if (foo[ 7: 5] >= 3'h5) foobar = {foobar, " 1128"}; else ozonexe(foo[ 8: 5], foobar); end endcase dude(foobar); $fwrite (fd, " 1129:%s", foobar); end 17'b00_10??_?_????_?0_1111 : casez (foo[14: 9]) 6'b001_10_?: begin ozonef1e(foo, foobar); foobar = {foobar, " 1130"}; foobar = {foobar, " 1131"}; ozonef1e_hl(foo[ 7: 5],foo[ 9],foobar); foobar = {foobar, " 1132"}; ozonexe(foo[ 8: 5], foobar); dude(foobar); $fwrite (fd, " 1133:%s", foobar); end 6'b???_11_?: begin ozonef1e(foo, foobar); foobar = {foobar, " 1134"}; ozoneae(foo[14:12], foobar); ozonef1e_hl(foo[ 7: 5],foo[ 9],foobar); foobar = {foobar, " 1135"}; ozonexe(foo[ 8: 5], foobar); dude(foobar); $fwrite (fd, " 1136:%s", foobar); end 6'b000_10_1, 6'b010_10_1, 6'b100_10_1, 6'b110_10_1: begin ozonef1e(foo, foobar); foobar = {foobar, " 1137"}; ozonerab({4'b1001, foo[14:12]}, foobar); foobar = {foobar, " 1138"}; if ((foo[ 7: 5] >= 3'h1) & (foo[ 7: 5] <= 3'h3)) foobar = {foobar, " 1139"}; else ozonexe(foo[ 8: 5], foobar); dude(foobar); $fwrite (fd, " 1140:%s", foobar); end 6'b000_10_0, 6'b010_10_0, 6'b100_10_0, 6'b110_10_0: begin ozonef1e(foo, foobar); foobar = {foobar, " 1141"}; foobar = {foobar, " 1142"}; ozonerab({4'b1001, foo[14:12]}, foobar); foobar = {foobar, " 1143"}; foobar = {foobar, " 1144"}; ozonef1e_h(foo[ 7: 5],foobar); foobar = {foobar, " 1145"}; ozonexe(foo[ 8: 5], foobar); dude(foobar); $fwrite (fd, " 1146:%s", foobar); end 6'b???_00_?: begin ozonef1e(foo, foobar); foobar = {foobar, " 1147"}; if (foo[ 9]) begin foobar = {foobar, " 1148"}; ozoneae(foo[14:12], foobar); end else begin foobar = {foobar, " 1149"}; ozoneae(foo[14:12], foobar); foobar = {foobar, " 1150"}; end foobar = {foobar, " 1151"}; foobar = {foobar, " 1152"}; ozonef1e_h(foo[ 7: 5],foobar); foobar = {foobar, " 1153"}; ozonexe(foo[ 8: 5], foobar); dude(foobar); $fwrite (fd, " 1154:%s", foobar); end 6'b???_01_?: begin ozonef1e(foo, foobar); foobar = {foobar, " 1155"}; ozoneae(foo[14:12], foobar); if (foo[ 9]) foobar = {foobar, " 1156"}; else foobar = {foobar, " 1157"}; foobar = {foobar, " 1158"}; foobar = {foobar, " 1159"}; ozonef1e_h(foo[ 7: 5],foobar); foobar = {foobar, " 1160"}; ozonexe(foo[ 8: 5], foobar); dude(foobar); $fwrite (fd, " 1161:%s", foobar); end 6'b011_10_0: begin ozonef1e(foo, foobar); foobar = {foobar, " 1162"}; case (foo[ 8: 5]) 4'h0: foobar = {foobar, " 1163"}; 4'h1: foobar = {foobar, " 1164"}; 4'h2: foobar = {foobar, " 1165"}; 4'h3: foobar = {foobar, " 1166"}; 4'h4: foobar = {foobar, " 1167"}; 4'h5: foobar = {foobar, " 1168"}; 4'h8: foobar = {foobar, " 1169"}; 4'h9: foobar = {foobar, " 1170"}; 4'ha: foobar = {foobar, " 1171"}; 4'hb: foobar = {foobar, " 1172"}; 4'hc: foobar = {foobar, " 1173"}; 4'hd: foobar = {foobar, " 1174"}; default: foobar = {foobar, " 1175"}; endcase dude(foobar); $fwrite (fd, " 1176:%s", foobar); end default: foobar = {foobar, " 1177"}; endcase 17'b00_10??_?_????_?0_110? : begin ozonef1e(foo, foobar); foobar = {foobar, " 1178"}; foobar = {foobar, " 1179"}; ozonef1e_hl(foo[11:9], foo[0], foobar); foobar = {foobar, " 1180"}; ozonef1e_ye(foo[14:9],1'b0,foobar); foobar = {foobar, " 1181"}; ozonef1e_h(foo[ 7: 5],foobar); foobar = {foobar, " 1182"}; ozonexe(foo[ 8: 5], foobar); dude(foobar); $fwrite (fd, " 1183:%s", foobar); end 17'b00_10??_?_????_?1_110? : begin ozonef1e(foo, foobar); foobar = {foobar, " 1184"}; foobar = {foobar, " 1185"}; ozonef1e_hl(foo[11:9],foo[0],foobar); foobar = {foobar, " 1186"}; ozonef1e_ye(foo[14:9],foo[ 0],foobar); foobar = {foobar, " 1187"}; foobar = {foobar, " 1188"}; ozonef1e_h(foo[ 7: 5],foobar); foobar = {foobar, " 1189"}; ozonexe(foo[ 8: 5], foobar); dude(foobar); $fwrite (fd, " 1190:%s", foobar); end 17'b00_10??_?_????_?0_101? : begin ozonef1e(foo, foobar); foobar = {foobar, " 1191"}; ozonef1e_ye(foo[14:9],foo[ 0],foobar); foobar = {foobar, " 1192"}; foobar = {foobar, " 1193"}; ozonef1e_hl(foo[11:9],foo[0],foobar); foobar = {foobar, " 1194"}; foobar = {foobar, " 1195"}; ozonef1e_h(foo[ 7: 5],foobar); foobar = {foobar, " 1196"}; ozonexe(foo[ 8: 5], foobar); dude(foobar); $fwrite (fd, " 1197:%s", foobar); end 17'b00_10??_?_????_?0_1001 : begin ozonef1e(foo, foobar); foobar = {foobar, " 1198"}; foobar = {foobar, " 1199"}; ozonef1e_h(foo[11:9],foobar); foobar = {foobar, " 1200"}; ozonef1e_ye(foo[14:9],1'b0,foobar); foobar = {foobar, " 1201"}; case (foo[ 7: 5]) 3'h1, 3'h2, 3'h3: foobar = {foobar, " 1202"}; default: begin foobar = {foobar, " 1203"}; foobar = {foobar, " 1204"}; ozonexe(foo[ 8: 5], foobar); end endcase dude(foobar); $fwrite (fd, " 1205:%s", foobar); end 17'b00_10??_?_????_?0_0101 : begin ozonef1e(foo, foobar); foobar = {foobar, " 1206"}; case (foo[11: 9]) 3'h1, 3'h3, 3'h4: foobar = {foobar, " 1207"}; default: begin ozonef1e_ye(foo[14:9],1'b0,foobar); foobar = {foobar, " 1208"}; foobar = {foobar, " 1209"}; end endcase foobar = {foobar, " 1210"}; foobar = {foobar, " 1211"}; ozonef1e_h(foo[ 7: 5],foobar); foobar = {foobar, " 1212"}; ozonexe(foo[ 8: 5], foobar); dude(foobar); $fwrite (fd, " 1213:%s", foobar); end 17'b00_10??_?_????_?1_1110 : begin ozonef1e(foo, foobar); foobar = {foobar, " 1214"}; ozonef1e_ye(foo[14:9],1'b0,foobar); foobar = {foobar, " 1215"}; foobar = {foobar, " 1216"}; ozonef1e_h(foo[11: 9],foobar); foobar = {foobar, " 1217"}; foobar = {foobar, " 1218"}; ozonef1e_h(foo[ 7: 5],foobar); foobar = {foobar, " 1219"}; ozonexe(foo[ 8: 5], foobar); dude(foobar); $fwrite (fd, " 1220:%s", foobar); end 17'b00_10??_?_????_?0_1000 : begin ozonef1e(foo, foobar); foobar = {foobar, " 1221"}; ozonef1e_ye(foo[14:9],1'b0,foobar); foobar = {foobar, " 1222"}; foobar = {foobar, " 1223"}; ozonef1e_h(foo[11: 9],foobar); foobar = {foobar, " 1224"}; foobar = {foobar, " 1225"}; ozonef1e_h(foo[ 7: 5],foobar); foobar = {foobar, " 1226"}; ozonexe(foo[ 8: 5], foobar); dude(foobar); $fwrite (fd, " 1227:%s", foobar); end 17'b10_01??_?_????_??_???? : begin if (foo[27]) foobar = " 1228"; else foobar = " 1229"; ozonecon(foo[20:16], foobar); foobar = {foobar, " 1230"}; ozonef2(foo[31:0], foobar); dude(foobar); $fwrite (fd, " 1231:%s", foobar); end 17'b00_1000_?_????_01_0011 : if (~|foo[ 9: 8]) begin if (foo[ 7]) foobar = " 1232"; else foobar = " 1233"; ozonecon(foo[14:10], foobar); foobar = {foobar, " 1234"}; ozonef2e(foo[31:0], foobar); dude(foobar); $fwrite (fd, " 1235:%s", foobar); end else begin foobar = " 1236"; ozonecon(foo[14:10], foobar); foobar = {foobar, " 1237"}; ozonef3e(foo[31:0], foobar); dude(foobar); $fwrite (fd, " 1238:%s", foobar); end 17'b11_110?_1_????_??_???? : begin ozonef3(foo[31:0], foobar); dude(foobar); $fwrite(fd, " 1239:%s", foobar); end 17'b11_110?_0_????_??_???? : begin : f4_body casez (foo[24:20]) 5'b0_1110, 5'b1_0???, 5'b1_1111: begin $fwrite (fd, " 1240"); end 5'b0_00??: begin ozoneacc(foo[26], foobar); foobar = {foobar, " 1241"}; ozoneacc(foo[25], foobar); ozonebmuop(foo[24:20], foobar); ozoneae(foo[18:16], foobar); foobar = {foobar, " 1242"}; dude(foobar); $fwrite(fd, " 1243:%s", foobar); end 5'b0_01??: begin ozoneacc(foo[26], foobar); foobar = {foobar, " 1244"}; ozoneacc(foo[25], foobar); ozonebmuop(foo[24:20], foobar); ozonearm(foo[18:16], foobar); dude(foobar); $fwrite(fd, " 1245:%s", foobar); end 5'b0_1011: begin ozoneacc(foo[26], foobar); foobar = {foobar, " 1246"}; ozonebmuop(foo[24:20], foobar); foobar = {foobar, " 1247"}; ozoneae(foo[18:16], foobar); foobar = {foobar, " 1248"}; dude(foobar); $fwrite(fd, " 1249:%s", foobar); end 5'b0_100?, 5'b0_1010, 5'b0_110? : begin ozoneacc(foo[26], foobar); foobar = {foobar, " 1250"}; ozonebmuop(foo[24:20], foobar); foobar = {foobar, " 1251"}; ozoneacc(foo[25], foobar); foobar = {foobar, " 1252"}; ozoneae(foo[18:16], foobar); foobar = {foobar, " 1253"}; dude(foobar); $fwrite(fd, " 1254:%s", foobar); end 5'b0_1111 : begin ozoneacc(foo[26], foobar); foobar = {foobar, " 1255"}; ozoneacc(foo[25], foobar); foobar = {foobar, " 1256"}; ozoneae(foo[18:16], foobar); dude(foobar); $fwrite(fd, " 1257:%s", foobar); end 5'b1_10??, 5'b1_110?, 5'b1_1110 : begin ozoneacc(foo[26], foobar); foobar = {foobar, " 1258"}; ozonebmuop(foo[24:20], foobar); foobar = {foobar, " 1259"}; ozoneacc(foo[25], foobar); foobar = {foobar, " 1260"}; ozonearm(foo[18:16], foobar); foobar = {foobar, " 1261"}; dude(foobar); $fwrite(fd, " 1262:%s", foobar); end endcase end 17'b11_100?_?_????_??_???? : casez (foo[23:19]) 5'b111??, 5'b0111?: begin ozoneae(foo[26:24], foobar); foobar = {foobar, " 1263"}; ozonef3f4imop(foo[23:19], foobar); foobar = {foobar, " 1264"}; ozoneae(foo[18:16], foobar); foobar = {foobar, " 1265"}; skyway(foo[15:12], foobar); skyway(foo[11: 8], foobar); skyway(foo[ 7: 4], foobar); skyway(foo[ 3:0], foobar); foobar = {foobar, " 1266"}; dude(foobar); $fwrite(fd, " 1267:%s", foobar); end 5'b?0???, 5'b110??: begin ozoneae(foo[26:24], foobar); foobar = {foobar, " 1268"}; if (foo[23:21] == 3'b100) foobar = {foobar, " 1269"}; ozoneae(foo[18:16], foobar); if (foo[19]) foobar = {foobar, " 1270"}; else foobar = {foobar, " 1271"}; ozonef3f4imop(foo[23:19], foobar); foobar = {foobar, " 1272"}; ozonef3f4_iext(foo[20:19], foo[15:0], foobar); dude(foobar); $fwrite(fd, " 1273:%s", foobar); end 5'b010??, 5'b0110?: begin ozoneae(foo[18:16], foobar); if (foo[19]) foobar = {foobar, " 1274"}; else foobar = {foobar, " 1275"}; ozonef3f4imop(foo[23:19], foobar); foobar = {foobar, " 1276"}; ozonef3f4_iext(foo[20:19], foo[15:0], foobar); dude(foobar); $fwrite(fd, " 1277:%s", foobar); end endcase 17'b00_1000_?_????_11_0011 : begin foobar = " 1278"; ozonecon(foo[14:10], foobar); foobar = {foobar, " 1279"}; casez (foo[25:21]) 5'b0_1110, 5'b1_0???, 5'b1_1111: begin $fwrite(fd, " 1280"); end 5'b0_00??: begin ozoneae(foo[20:18], foobar); foobar = {foobar, " 1281"}; ozoneae(foo[17:15], foobar); ozonebmuop(foo[25:21], foobar); ozoneae(foo[ 8: 6], foobar); foobar = {foobar, " 1282"}; dude(foobar); $fwrite(fd, " 1283:%s", foobar); end 5'b0_01??: begin ozoneae(foo[20:18], foobar); foobar = {foobar, " 1284"}; ozoneae(foo[17:15], foobar); ozonebmuop(foo[25:21], foobar); ozonearm(foo[ 8: 6], foobar); dude(foobar); $fwrite(fd, " 1285:%s", foobar); end 5'b0_1011: begin ozoneae(foo[20:18], foobar); foobar = {foobar, " 1286"}; ozonebmuop(foo[25:21], foobar); foobar = {foobar, " 1287"}; ozoneae(foo[ 8: 6], foobar); foobar = {foobar, " 1288"}; dude(foobar); $fwrite(fd, " 1289:%s", foobar); end 5'b0_100?, 5'b0_1010, 5'b0_110? : begin ozoneae(foo[20:18], foobar); foobar = {foobar, " 1290"}; ozonebmuop(foo[25:21], foobar); foobar = {foobar, " 1291"}; ozoneae(foo[17:15], foobar); foobar = {foobar, " 1292"}; ozoneae(foo[ 8: 6], foobar); foobar = {foobar, " 1293"}; dude(foobar); $fwrite(fd, " 1294:%s", foobar); end 5'b0_1111 : begin ozoneae(foo[20:18], foobar); foobar = {foobar, " 1295"}; ozoneae(foo[17:15], foobar); foobar = {foobar, " 1296"}; ozoneae(foo[ 8: 6], foobar); dude(foobar); $fwrite(fd, " 1297:%s", foobar); end 5'b1_10??, 5'b1_110?, 5'b1_1110 : begin ozoneae(foo[20:18], foobar); foobar = {foobar, " 1298"}; ozonebmuop(foo[25:21], foobar); foobar = {foobar, " 1299"}; ozoneae(foo[17:15], foobar); foobar = {foobar, " 1300"}; ozonearm(foo[ 8: 6], foobar); foobar = {foobar, " 1301"}; dude(foobar); $fwrite(fd, " 1302:%s", foobar); end endcase end 17'b00_0010_?_????_??_???? : begin $fwrite(fd, " 1304a:%x;%x", foobar, foo[25:20]); ozonerab({1'b0, foo[25:20]}, foobar); $fwrite(fd, " 1304b:%x", foobar); foobar = {foobar, " 1303"}; $fwrite(fd, " 1304c:%x;%x", foobar, foo[19:16]); skyway(foo[19:16], foobar); $fwrite(fd, " 1304d:%x", foobar); dude(foobar); $fwrite(fd, " 1304e:%x", foobar); $fwrite(fd, " 1304:%s", foobar); end 17'b00_01??_?_????_??_???? : begin if (foo[27]) begin foobar = {foobar, " 1305"}; if (foo[26]) foobar = {foobar, " 1306"}; else foobar = {foobar, " 1307"}; skyway(foo[19:16], foobar); foobar = {foobar, " 1308"}; ozonerab({1'b0, foo[25:20]}, foobar); end else begin ozonerab({1'b0, foo[25:20]}, foobar); foobar = {foobar, " 1309"}; if (foo[26]) foobar = {foobar, " 1310"}; else foobar = {foobar, " 1311"}; skyway(foo[19:16], foobar); foobar = {foobar, " 1312"}; end dude(foobar); $fwrite(fd, " 1313:%s", foobar); end 17'b01_000?_?_????_??_???? : begin if (foo[26]) begin ozonerb(foo[25:20], foobar); foobar = {foobar, " 1314"}; ozoneae(foo[18:16], foobar); ozonehl(foo[19], foobar); end else begin ozoneae(foo[18:16], foobar); ozonehl(foo[19], foobar); foobar = {foobar, " 1315"}; ozonerb(foo[25:20], foobar); end dude(foobar); $fwrite(fd, " 1316:%s", foobar); end 17'b01_10??_?_????_??_???? : begin if (foo[27]) begin ozonerab({1'b0, foo[25:20]}, foobar); foobar = {foobar, " 1317"}; ozonerx(foo, foobar); end else begin ozonerx(foo, foobar); foobar = {foobar, " 1318"}; ozonerab({1'b0, foo[25:20]}, foobar); end dude(foobar); $fwrite(fd, " 1319:%s", foobar); end 17'b11_101?_?_????_??_???? : begin ozonerab (foo[26:20], foobar); foobar = {foobar, " 1320"}; skyway(foo[19:16], foobar); skyway(foo[15:12], foobar); skyway(foo[11: 8], foobar); skyway(foo[ 7: 4], foobar); skyway(foo[ 3: 0], foobar); dude(foobar); $fwrite(fd, " 1321:%s", foobar); end 17'b11_0000_?_????_??_???? : begin casez (foo[25:23]) 3'b00?: begin ozonerab(foo[22:16], foobar); foobar = {foobar, " 1322"}; end 3'b01?: begin foobar = {foobar, " 1323"}; if (foo[22:16]>=7'h60) foobar = {foobar, " 1324"}; else ozonerab(foo[22:16], foobar); end 3'b110: foobar = {foobar, " 1325"}; 3'b10?: begin foobar = {foobar, " 1326"}; if (foo[22:16]>=7'h60) foobar = {foobar, " 1327"}; else ozonerab(foo[22:16], foobar); end 3'b111: begin foobar = {foobar, " 1328"}; ozonerab(foo[22:16], foobar); foobar = {foobar, " 1329"}; end endcase dude(foobar); $fwrite(fd, " 1330:%s", foobar); end 17'b00_10??_?_????_?1_0000 : begin if (foo[27]) begin foobar = {foobar, " 1331"}; ozonerp(foo[14:12], foobar); foobar = {foobar, " 1332"}; skyway(foo[19:16], foobar); skyway({foo[15],foo[11: 9]}, foobar); skyway(foo[ 8: 5], foobar); foobar = {foobar, " 1333"}; if (foo[26:20]>=7'h60) foobar = {foobar, " 1334"}; else ozonerab(foo[26:20], foobar); end else begin ozonerab(foo[26:20], foobar); foobar = {foobar, " 1335"}; foobar = {foobar, " 1336"}; ozonerp(foo[14:12], foobar); foobar = {foobar, " 1337"}; skyway(foo[19:16], foobar); skyway({foo[15],foo[11: 9]}, foobar); skyway(foo[ 8: 5], foobar); foobar = {foobar, " 1338"}; end dude(foobar); $fwrite(fd, " 1339:%s", foobar); end 17'b00_101?_1_0000_?1_0010 : if (~|foo[11: 7]) begin if (foo[ 6]) begin foobar = {foobar, " 1340"}; ozonerp(foo[14:12], foobar); foobar = {foobar, " 1341"}; ozonejk(foo[ 5], foobar); foobar = {foobar, " 1342"}; if (foo[26:20]>=7'h60) foobar = {foobar, " 1343"}; else ozonerab(foo[26:20], foobar); end else begin ozonerab(foo[26:20], foobar); foobar = {foobar, " 1344"}; foobar = {foobar, " 1345"}; ozonerp(foo[14:12], foobar); foobar = {foobar, " 1346"}; ozonejk(foo[ 5], foobar); foobar = {foobar, " 1347"}; end dude(foobar); $fwrite(fd, " 1348:%s", foobar); end else $fwrite(fd, " 1349"); 17'b00_100?_0_0011_?1_0101 : if (~|foo[ 8: 7]) begin if (foo[6]) begin ozonerab(foo[26:20], foobar); foobar = {foobar, " 1350"}; ozoneye(foo[14: 9],foo[ 5], foobar); end else begin ozoneye(foo[14: 9],foo[ 5], foobar); foobar = {foobar, " 1351"}; if (foo[26:20]>=7'h60) foobar = {foobar, " 1352"}; else ozonerab(foo[26:20], foobar); end dude(foobar); $fwrite(fd, " 1353:%s", foobar); end else $fwrite(fd, " 1354"); 17'b00_1001_0_0000_?1_0010 : if (~|foo[25:20]) begin ozoneye(foo[14: 9],1'b0, foobar); foobar = {foobar, " 1355"}; ozonef1e_h(foo[11: 9],foobar); foobar = {foobar, " 1356"}; ozonef1e_h(foo[ 7: 5],foobar); foobar = {foobar, " 1357"}; ozonexe(foo[ 8: 5], foobar); dude(foobar); $fwrite(fd, " 1358:%s", foobar); end else $fwrite(fd, " 1359"); 17'b00_101?_0_????_?1_0010 : if (~foo[13]) begin if (foo[12]) begin foobar = {foobar, " 1360"}; if (foo[26:20]>=7'h60) foobar = {foobar, " 1361"}; else ozonerab(foo[26:20], foobar); foobar = {foobar, " 1362"}; foobar = {foobar, " 1363"}; skyway({1'b0,foo[18:16]}, foobar); skyway({foo[15],foo[11: 9]}, foobar); skyway(foo[ 8: 5], foobar); dude(foobar); $fwrite(fd, " 1364:%s", foobar); end else begin ozonerab(foo[26:20], foobar); foobar = {foobar, " 1365"}; foobar = {foobar, " 1366"}; skyway({1'b0,foo[18:16]}, foobar); skyway({foo[15],foo[11: 9]}, foobar); skyway(foo[ 8: 5], foobar); dude(foobar); $fwrite(fd, " 1367:%s", foobar); end end else $fwrite(fd, " 1368"); 17'b01_01??_?_????_??_???? : begin ozonerab({1'b0,foo[27:26],foo[19:16]}, foobar); foobar = {foobar, " 1369"}; ozonerab({1'b0,foo[25:20]}, foobar); dude(foobar); $fwrite(fd, " 1370:%s", foobar); end 17'b00_100?_?_???0_11_0101 : if (~foo[6]) begin foobar = " 1371"; ozonecon(foo[14:10], foobar); foobar = {foobar, " 1372"}; ozonerab({foo[ 9: 7],foo[19:16]}, foobar); foobar = {foobar, " 1373"}; ozonerab({foo[26:20]}, foobar); dude(foobar); $fwrite(fd, " 1374:%s", foobar); end else $fwrite(fd, " 1375"); 17'b00_1000_?_????_?1_0010 : if (~|foo[25:24]) begin ozonery(foo[23:20], foobar); foobar = {foobar, " 1376"}; ozonerp(foo[14:12], foobar); foobar = {foobar, " 1377"}; skyway(foo[19:16], foobar); skyway({foo[15],foo[11: 9]}, foobar); skyway(foo[ 8: 5], foobar); dude(foobar); $fwrite(fd, " 1378:%s", foobar); end else if ((foo[25:24] == 2'b10) & ~|foo[19:15] & ~|foo[11: 6]) begin ozonery(foo[23:20], foobar); foobar = {foobar, " 1379"}; ozonerp(foo[14:12], foobar); foobar = {foobar, " 1380"}; ozonejk(foo[ 5], foobar); dude(foobar); $fwrite(fd, " 1381:%s", foobar); end else $fwrite(fd, " 1382"); 17'b11_01??_?_????_??_????, 17'b10_00??_?_????_??_???? : if (foo[30]) $fwrite(fd, " 1383:%s", foo[27:16]); else $fwrite(fd, " 1384:%s", foo[27:16]); 17'b00_10??_?_????_01_1000 : if (~foo[6]) begin if (foo[7]) $fwrite(fd, " 1385:%s", foo[27: 8]); else $fwrite(fd, " 1386:%s", foo[27: 8]); end else $fwrite(fd, " 1387"); 17'b00_10??_?_????_11_1000 : begin foobar = " 1388"; ozonecon(foo[14:10], foobar); foobar = {foobar, " 1389"}; if (foo[15]) foobar = {foobar, " 1390"}; else foobar = {foobar, " 1391"}; skyway(foo[27:24], foobar); skyway(foo[23:20], foobar); skyway(foo[19:16], foobar); skyway(foo[ 9: 6], foobar); dude(foobar); $fwrite(fd, " 1392:%s", foobar); end 17'b11_0001_?_????_??_???? : casez (foo[25:22]) 4'b01?? : begin foobar = " 1393"; ozonecon(foo[20:16], foobar); case (foo[23:21]) 3'h0 : foobar = {foobar, " 1394"}; 3'h1 : foobar = {foobar, " 1395"}; 3'h2 : foobar = {foobar, " 1396"}; 3'h3 : foobar = {foobar, " 1397"}; 3'h4 : foobar = {foobar, " 1398"}; 3'h5 : foobar = {foobar, " 1399"}; 3'h6 : foobar = {foobar, " 1400"}; 3'h7 : foobar = {foobar, " 1401"}; endcase dude(foobar); $fwrite(fd, " 1402:%s", foobar); end 4'b0000 : $fwrite(fd, " 1403:%s", foo[21:16]); 4'b0010 : if (~|foo[21:16]) $fwrite(fd, " 1404"); 4'b1010 : if (~|foo[21:17]) begin if (foo[16]) $fwrite(fd, " 1405"); else $fwrite(fd, " 1406"); end default : $fwrite(fd, " 1407"); endcase 17'b01_11??_?_????_??_???? : if (foo[27:23] === 5'h00) $fwrite(fd, " 1408:%s", foo[22:16]); else $fwrite(fd, " 1409:%s", foo[22:16]); default: $fwrite(fd, " 1410"); endcase end endtask //(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\",\",\\4,\");\");" nil nil nil) //(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\");\");" nil nil nil) endmodule verilator-5.042/test_regress/t/t_vlcov_flag_invalid_bad.out0000644000542200017500000000021415101701376024575 0ustar mahmoudyfreeshell%Error: Invalid option: --invalid-dash ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. verilator-5.042/test_regress/t/t_func_first.v0000644000542200017500000000142515101701376021744 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [7:0] cyc; initial cyc = 0; reg set_in_task; always @ (posedge clk) begin if (cyc == 8'd0) begin cyc <= 8'd1; set_in_task <= 0; end if (cyc == 8'd1) begin cyc <= 8'h2; ttask; end if (cyc == 8'd2) begin if (!set_in_task) $stop; cyc <= 8'hf; $write("*-* All Finished *-*\n"); $finish; end end task ttask; begin set_in_task <= 1'b1; end endtask endmodule verilator-5.042/test_regress/t/t_inst_dearray_slice.py0000755000542200017500000000073415101701376023635 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_struct_contents.v0000644000542200017500000000217715101701376023050 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; typedef enum logic [1:0] { ZERO, ONE } enum_t; typedef struct packed { bit a; } struct_packed_t; typedef union packed { bit a; } union_packed_t; //IEEE 1800-2023 7.2.1 // These are all legal typedef struct packed { enum_t e; shortint si; int it; longint li; byte by; bit bi; logic lo; reg rg; integer in; time tim; struct_packed_t sp; union_packed_t up; bit [1:0][2:0] bit_array; } legal_t; legal_t legal; initial begin legal.e = ONE; legal.si = 1; legal.it = 2; legal.li = 3; legal.by = 4; legal.bi = 1'b1; legal.lo = 1'b1; legal.rg = 1'b1; legal.in = 6; legal.tim = 7; legal.sp.a = 1'b1; legal.up.a = 1'b1; legal.bit_array[1][1] = 1'b1; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_param_type6.v0000644000542200017500000000217115101701376022030 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface intf #( parameter type the_type = bit ); the_type foo; endinterface interface no_param_intf; logic [13:0] bar; endinterface module t (/*AUTOARG*/ // Inputs clk ); input clk; intf #(.the_type (logic [7:0])) intf_eight(); no_param_intf the_no_param_intf(); sub #(.TYPE_BITS (8)) sub_eight ( .intf_pin (intf_eight), .no_param_intf_pin (the_no_param_intf) ); // finish report always @ (posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule module sub #( parameter int TYPE_BITS )( intf intf_pin, no_param_intf no_param_intf_pin ); localparam type intf_type = type(intf_pin.foo); localparam type no_param_intf_type = type(no_param_intf_pin.bar); initial begin if ($bits(intf_type) != TYPE_BITS) $stop(); if ($bits(no_param_intf_type) != 14) $stop(); end endmodule verilator-5.042/test_regress/t/t_sc_names.cpp0000644000542200017500000000146215101701376021710 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Edgar E. Iglesias. // SPDX-License-Identifier: CC0-1.0 #include VM_PREFIX_INCLUDE using namespace sc_core; VM_PREFIX* tb = nullptr; int sc_main(int argc, char* argv[]) { tb = new VM_PREFIX{"tb"}; std::vector ch = tb->get_child_objects(); bool found = false; // We expect to find clk in here for (int i = 0; i < ch.size(); ++i) { if (!std::strcmp(ch[i]->basename(), "clk")) found = true; } if (found) { VL_PRINTF("*-* All Finished *-*\n"); tb->final(); } else { vl_fatal(__FILE__, __LINE__, "tb", "Unexpected results\n"); } VL_DO_DANGLING(delete tb, tb); return 0; } verilator-5.042/test_regress/t/t_vams_kwd_bad.py0000755000542200017500000000106015101701376022404 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, verilator_flags2=["--error-limit 1000"], expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface_generic_array.v0000644000542200017500000000102315101701376024426 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 interface inf; int v; endinterface module GenericModule (interface a); initial begin #1; if (a.v != 7) $stop; end endmodule module t; inf inf_inst[3](); GenericModule genericModule (inf_inst[2]); initial begin inf_inst[2].v = 7; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_enum_bad_hide.v0000644000542200017500000000051215101701376022341 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef enum { HIDE_VALUE = 0 } hide_enum_t; module t; typedef enum { HIDE_VALUE = 0 } hide_enum_t; endmodule verilator-5.042/test_regress/t/t_class_copy_bad.v0000644000542200017500000000072515101701376022551 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Other; endclass class Cls; int imembera; function int inc_methoda; imembera += 1; return imembera; endfunction endclass module t; initial begin Cls c1; Other co; c1 = new co; // Bad, incompatible types end endmodule verilator-5.042/test_regress/t/t_wrapper_legacy.py0000755000542200017500000000120415101701376022767 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename], make_flags=['CPPFLAGS_ADD=-DVL_TIME_CONTEXT']) test.execute() test.passes() verilator-5.042/test_regress/t/t_func_ref_bad.v0000644000542200017500000000067715101701376022207 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class Cls; function logic get_x(ref logic x); return x; endfunction endclass module t; logic [10:0] a; logic b; Cls cls; initial begin cls = new; b = cls.get_x(a[1]); $stop; end endmodule verilator-5.042/test_regress/t/t_preproc_nodef_bad.out0000644000542200017500000000037315101701376023600 0ustar mahmoudyfreeshell%Error: t/t_preproc_nodef_bad.v:7:1: Define or directive not defined: '`not_defined' 7 | `not_defined | ^~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_opt_table_sparse.v0000644000542200017500000000147115101701376023131 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; int i; reg [2:0] cyc; initial cyc = 0; always @(posedge clk) cyc <= cyc + 1; /* verilator lint_off LATCH */ always @* begin case (cyc) 3'b000: i = 0; 3'b001: i = 1; 3'b010: ; // unset 3'b100: i = 4; 3'b101: i = 5; default: i = 99; endcase end /* verilator lint_on LATCH */ always @(posedge clk) begin $display("cyle %d = %d", cyc, i); if (cyc == 7) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_dpi_display_bad.v0000644000542200017500000000130215101701376022703 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2010 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (); `ifndef VERILATOR `error "Only Verilator supports PLI-ish DPI calls and sformat conversion." `endif import "DPI-C" context dpii_display_call = function void \$dpii_display (input string formatted /*verilator sformat*/, input string other_bad ); initial begin $dpii_display("hello", "huh"); $stop; end endmodule verilator-5.042/test_regress/t/t_lint_syncasyncnet_bad.out0000644000542200017500000000126515101701376024523 0ustar mahmoudyfreeshell%Warning-SYNCASYNCNET: t/t_lint_syncasyncnet_bad.v:14:10: Signal flopped as both synchronous and async: 'rst_both_l' t/t_lint_syncasyncnet_bad.v:52:15: ... Location of async usage 52 | q4 <= (~rst_both_l) ? 1'b0 : d; | ^~~~~~~~~~ t/t_lint_syncasyncnet_bad.v:34:14: ... Location of sync usage 34 | q2 <= (rst_both_l) ? d : 1'b0; | ^~~~~~~~~~ ... For warning description see https://verilator.org/warn/SYNCASYNCNET?v=latest ... Use "/* verilator lint_off SYNCASYNCNET */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_attr_parenstar.py0000755000542200017500000000073415101701376023023 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_x_rand_mt_stability_zeros.py0000755000542200017500000000121115101701376025242 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios("vltmt") test.top_filename = "t/t_x_rand_stability.v" test.compile(verilator_flags2=["--x-initial unique", "-DNOT_RAND"]) test.execute(all_run_flags=["+verilator+rand+reset+0"], expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_trace_two_hdr_sc.py0000755000542200017500000000252315101701376023301 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t_trace_two_a.v" test.pli_filename = "t/t_trace_two_sc.cpp" if not test.have_sc: test.skip("No SystemC installed") test.compile(make_main=False, verilator_make_gmake=False, top_filename='t_trace_two_b.v', vm_prefix='Vt_trace_two_b', verilator_flags2=['-sc -trace']) test.run(logfile=test.obj_dir + "/make_first_ALL.log", cmd=[ os.environ["MAKE"], "-C", test.obj_dir, "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp" ]) test.compile(make_main=False, top_filename='t_trace_two_a.v', make_flags=['CPPFLAGS_ADD=-DTEST_HDR_TRACE'], verilator_flags2=['-sc', '-exe', '-trace', test.pli_filename]) test.execute() if test.vlt_all: test.file_grep(test.trace_filename, r'\$enddefinitions') test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_declfilename.v0000644000542200017500000000046015101701376023236 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; t_lint_declfilename sub (); endmodule module t_lint_declfilename; endmodule verilator-5.042/test_regress/t/t_unroll_stmt.py0000755000542200017500000000274015101701376022353 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(verilator_flags2=["--binary", "--stats"]) test.execute(expect_filename=test.golden_filename) test.file_grep(test.stats, r'Optimizations, Loop unrolling, Failed - contains fork\s+(\d+)', 0) test.file_grep(test.stats, r'Optimizations, Loop unrolling, Failed - infinite loop\s+(\d+)', 0) test.file_grep(test.stats, r'Optimizations, Loop unrolling, Failed - loop test in sub-statement\s+(\d+)', 0) test.file_grep(test.stats, r'Optimizations, Loop unrolling, Failed - reached --unroll-count\s+(\d+)', 0) test.file_grep(test.stats, r'Optimizations, Loop unrolling, Failed - reached --unroll-stmts\s+(\d+)', 0) test.file_grep(test.stats, r'Optimizations, Loop unrolling, Failed - unknown loop condition\s+(\d+)', 0) test.file_grep(test.stats, r'Optimizations, Loop unrolling, Pragma unroll_disable\s+(\d+)', 0) test.file_grep(test.stats, r'Optimizations, Loop unrolling, Unrolled loops\s+(\d+)', 6) test.file_grep(test.stats, r'Optimizations, Loop unrolling, Unrolled iterations\s+(\d+)', 40) test.passes() verilator-5.042/test_regress/t/t_for_loop.py0000755000542200017500000000073415101701376021611 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_randsequence.py0000755000542200017500000000115715101701376022447 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--error-limit 999'], fails=test.vlt_all, expect_filename=test.golden_filename) if not test.vlt_all: test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_functimectl_bad.out0000644000542200017500000000174615101701376024323 0ustar mahmoudyfreeshell%Error-FUNCTIMECTL: t/t_lint_functimectl_bad.v:12:5: Functions cannot contain time-controlling statements (IEEE 1800-2023 13.4) : ... note: In instance 't' 12 | @e; | ^ : ... Suggest make caller 'function calls_timing_ctl' a task 11 | function void calls_timing_ctl; | ^~~~~~~~~~~~~~~~ ... For error description see https://verilator.org/warn/FUNCTIMECTL?v=latest %Error-FUNCTIMECTL: t/t_lint_functimectl_bad.v:17:5: Functions cannot contain time-controlling statements (IEEE 1800-2023 13.4) : ... note: In instance 't' 17 | wait (s); | ^~~~ : ... Suggest make caller 'function calls_timing_ctl' a task 11 | function void calls_timing_ctl; | ^~~~~~~~~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_opt_const_or.py0000755000542200017500000000073415101701376022502 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_struct_packed_init_bad.py0000755000542200017500000000101715101701376024451 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) #test.execute() test.passes() verilator-5.042/test_regress/t/t_comb_input_2.py0000755000542200017500000000110215101701376022340 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile( #make_top_shell = False, make_main=False, v_flags2=["--exe", test.pli_filename, "-fno-dfg"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_pragma_protected.py0000755000542200017500000000076515101701376024344 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=['--lint-only -Wno-PROTECTED']) test.passes() verilator-5.042/test_regress/t/t_event_copy.out0000644000542200017500000000305515101701376022320 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_event_copy.v:100:13: Assignment to and from event in statically scheduled context. : ... note: In instance 't' : Static event scheduling won't be able to handle this. : ... Suggest move the event into a completely dynamic context, eg. a class, and reference it only from such context. 100 | e4 = e3; | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_event_copy.v:101:13: Assignment to and from event in statically scheduled context. : ... note: In instance 't' : Static event scheduling won't be able to handle this. : ... Suggest move the event into a completely dynamic context, eg. a class, and reference it only from such context. 101 | e3 = e2; | ^ %Error-UNSUPPORTED: t/t_event_copy.v:128:13: Assignment to event in statically scheduled context. : ... note: In instance 't' : Static event scheduling won't be able to handle this. : ... Suggest move the event into a completely dynamic context, eg. a class, and reference it only from such context. 128 | e3 = null; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_interface_generic2.v0000644000542200017500000000134515101701376023321 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 interface inf; int v; endinterface interface inf2; int k; endinterface module GenericModule (logic[31:0] l1, interface a, logic[31:0] l2, interface b); initial begin #1; if (l1 != 87) $stop; if (a.v != 7) $stop; if (l2 != 73) $stop; if (b.k != 9) $stop; end endmodule module t; inf inf_inst(); inf2 inf_inst2(); GenericModule genericModule (87, inf_inst, 73, inf_inst2); initial begin inf_inst.v = 7; inf_inst2.k = 9; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_clk_dpulse.v0000644000542200017500000000213515101701376021726 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [7:0] cyc; initial cyc = 0; reg genclk; // verilator lint_off MULTIDRIVEN reg [7:0] set_both; // verilator lint_on MULTIDRIVEN wire genthiscyc = ( (cyc % 2) == 1 ); always @ (posedge clk) begin cyc <= cyc + 8'h1; genclk <= genthiscyc; set_both <= cyc; $write ("SB set_both %x <= cyc %x\n", set_both, cyc); if (genthiscyc) begin if (cyc>1 && set_both != (cyc - 8'h1)) $stop; end else begin if (cyc>1 && set_both != ~(cyc - 8'h1)) $stop; end if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end always @ (posedge genclk) begin set_both <= ~ set_both; $write ("SB set_both %x <= cyc %x\n", set_both, ~cyc); if (cyc>1 && set_both != (cyc - 8'h1)) $stop; end endmodule verilator-5.042/test_regress/t/t_dynarray_method_bad.out0000644000542200017500000000531215101701376024142 0ustar mahmoudyfreeshell%Warning-WIDTHTRUNC: t/t_dynarray_method_bad.v:19:9: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's CMETHODHARD 'r_sum' generates 64 bits. : ... note: In instance 't' 19 | i = s.sum with (item.len); | ^ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Warning-WIDTHTRUNC: t/t_dynarray_method_bad.v:21:9: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's CMETHODHARD 'r_product' generates 64 bits. : ... note: In instance 't' 21 | i = s.product with (item.len); | ^ %Warning-WIDTHTRUNC: t/t_dynarray_method_bad.v:23:9: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CMETHODHARD 'r_sum' generates 64 bits. : ... note: In instance 't' 23 | b = s.sum with (item == "hello"); | ^ %Warning-WIDTHTRUNC: t/t_dynarray_method_bad.v:25:9: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CMETHODHARD 'r_sum' generates 64 bits. : ... note: In instance 't' 25 | b = s.sum with (item == ""); | ^ %Warning-WIDTHTRUNC: t/t_dynarray_method_bad.v:27:9: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CMETHODHARD 'r_product' generates 64 bits. : ... note: In instance 't' 27 | b = s.product with (item inside {"hello", "sad"}); | ^ %Warning-WIDTHTRUNC: t/t_dynarray_method_bad.v:29:9: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CMETHODHARD 'r_product' generates 64 bits. : ... note: In instance 't' 29 | b = s.product with (item inside { "hello", "sad", "world" }); | ^ %Error-UNSUPPORTED: t/t_dynarray_method_bad.v:32:13: Unsupported/unknown built-in dynamic array method 'unknown_bad' : ... note: In instance 't' 32 | b = s.unknown_bad; | ^~~~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Warning-WIDTHTRUNC: t/t_dynarray_method_bad.v:32:9: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's METHODCALL 'unknown_bad' generates 64 bits. : ... note: In instance 't' 32 | b = s.unknown_bad; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_trace_sc_empty.v0000644000542200017500000000042515101701376022602 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilsn Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( output id0 ); assign id0 = 0; endmodule verilator-5.042/test_regress/t/t_case_write2_tasks.v0000644000542200017500000037153015101701376023225 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t_case_write2_tasks (); // verilator lint_off WIDTH // verilator lint_off CASEINCOMPLETE `define FD_BITS 31:0 parameter STRLEN = 78; task ozonerab; input [6:0] rab; input [`FD_BITS] fd; // verilator no_inline_task begin case (rab[6:0]) 7'h00 : $fwrite (fd, " 0"); 7'h01 : $fwrite (fd, " 1"); 7'h02 : $fwrite (fd, " 2"); 7'h03 : $fwrite (fd, " 3"); 7'h04 : $fwrite (fd, " 4"); 7'h05 : $fwrite (fd, " 5"); 7'h06 : $fwrite (fd, " 6"); 7'h07 : $fwrite (fd, " 7"); 7'h08 : $fwrite (fd, " 8"); 7'h09 : $fwrite (fd, " 9"); 7'h0a : $fwrite (fd, " 10"); 7'h0b : $fwrite (fd, " 11"); 7'h0c : $fwrite (fd, " 12"); 7'h0d : $fwrite (fd, " 13"); 7'h0e : $fwrite (fd, " 14"); 7'h0f : $fwrite (fd, " 15"); 7'h10 : $fwrite (fd, " 16"); 7'h11 : $fwrite (fd, " 17"); 7'h12 : $fwrite (fd, " 18"); 7'h13 : $fwrite (fd, " 19"); 7'h14 : $fwrite (fd, " 20"); 7'h15 : $fwrite (fd, " 21"); 7'h16 : $fwrite (fd, " 22"); 7'h17 : $fwrite (fd, " 23"); 7'h18 : $fwrite (fd, " 24"); 7'h19 : $fwrite (fd, " 25"); 7'h1a : $fwrite (fd, " 26"); 7'h1b : $fwrite (fd, " 27"); 7'h1c : $fwrite (fd, " 28"); 7'h1d : $fwrite (fd, " 29"); 7'h1e : $fwrite (fd, " 30"); 7'h1f : $fwrite (fd, " 31"); 7'h20 : $fwrite (fd, " 32"); 7'h21 : $fwrite (fd, " 33"); 7'h22 : $fwrite (fd, " 34"); 7'h23 : $fwrite (fd, " 35"); 7'h24 : $fwrite (fd, " 36"); 7'h25 : $fwrite (fd, " 37"); 7'h26 : $fwrite (fd, " 38"); 7'h27 : $fwrite (fd, " 39"); 7'h28 : $fwrite (fd, " 40"); 7'h29 : $fwrite (fd, " 41"); 7'h2a : $fwrite (fd, " 42"); 7'h2b : $fwrite (fd, " 43"); 7'h2c : $fwrite (fd, " 44"); 7'h2d : $fwrite (fd, " 45"); 7'h2e : $fwrite (fd, " 46"); 7'h2f : $fwrite (fd, " 47"); 7'h30 : $fwrite (fd, " 48"); 7'h31 : $fwrite (fd, " 49"); 7'h32 : $fwrite (fd, " 50"); 7'h33 : $fwrite (fd, " 51"); 7'h34 : $fwrite (fd, " 52"); 7'h35 : $fwrite (fd, " 53"); 7'h36 : $fwrite (fd, " 54"); 7'h37 : $fwrite (fd, " 55"); 7'h38 : $fwrite (fd, " 56"); 7'h39 : $fwrite (fd, " 57"); 7'h3a : $fwrite (fd, " 58"); 7'h3b : $fwrite (fd, " 59"); 7'h3c : $fwrite (fd, " 60"); 7'h3d : $fwrite (fd, " 61"); 7'h3e : $fwrite (fd, " 62"); 7'h3f : $fwrite (fd, " 63"); 7'h40 : $fwrite (fd, " 64"); 7'h41 : $fwrite (fd, " 65"); 7'h42 : $fwrite (fd, " 66"); 7'h43 : $fwrite (fd, " 67"); 7'h44 : $fwrite (fd, " 68"); 7'h45 : $fwrite (fd, " 69"); 7'h46 : $fwrite (fd, " 70"); 7'h47 : $fwrite (fd, " 71"); 7'h48 : $fwrite (fd, " 72"); 7'h49 : $fwrite (fd, " 73"); 7'h4a : $fwrite (fd, " 74"); 7'h4b : $fwrite (fd, " 75"); 7'h4c : $fwrite (fd, " 76"); 7'h4d : $fwrite (fd, " 77"); 7'h4e : $fwrite (fd, " 78"); 7'h4f : $fwrite (fd, " 79"); 7'h50 : $fwrite (fd, " 80"); 7'h51 : $fwrite (fd, " 81"); 7'h52 : $fwrite (fd, " 82"); 7'h53 : $fwrite (fd, " 83"); 7'h54 : $fwrite (fd, " 84"); 7'h55 : $fwrite (fd, " 85"); 7'h56 : $fwrite (fd, " 86"); 7'h57 : $fwrite (fd, " 87"); 7'h58 : $fwrite (fd, " 88"); 7'h59 : $fwrite (fd, " 89"); 7'h5a : $fwrite (fd, " 90"); 7'h5b : $fwrite (fd, " 91"); 7'h5c : $fwrite (fd, " 92"); 7'h5d : $fwrite (fd, " 93"); 7'h5e : $fwrite (fd, " 94"); 7'h5f : $fwrite (fd, " 95"); 7'h60 : $fwrite (fd, " 96"); 7'h61 : $fwrite (fd, " 97"); 7'h62 : $fwrite (fd, " 98"); 7'h63 : $fwrite (fd, " 99"); 7'h64 : $fwrite (fd, " 100"); 7'h65 : $fwrite (fd, " 101"); 7'h66 : $fwrite (fd, " 102"); 7'h67 : $fwrite (fd, " 103"); 7'h68 : $fwrite (fd, " 104"); 7'h69 : $fwrite (fd, " 105"); 7'h6a : $fwrite (fd, " 106"); 7'h6b : $fwrite (fd, " 107"); 7'h6c : $fwrite (fd, " 108"); 7'h6d : $fwrite (fd, " 109"); 7'h6e : $fwrite (fd, " 110"); 7'h6f : $fwrite (fd, " 111"); 7'h70 : $fwrite (fd, " 112"); 7'h71 : $fwrite (fd, " 113"); 7'h72 : $fwrite (fd, " 114"); 7'h73 : $fwrite (fd, " 115"); 7'h74 : $fwrite (fd, " 116"); 7'h75 : $fwrite (fd, " 117"); 7'h76 : $fwrite (fd, " 118"); 7'h77 : $fwrite (fd, " 119"); 7'h78 : $fwrite (fd, " 120"); 7'h79 : $fwrite (fd, " 121"); 7'h7a : $fwrite (fd, " 122"); 7'h7b : $fwrite (fd, " 123"); 7'h7c : $fwrite (fd, " 124"); 7'h7d : $fwrite (fd, " 125"); 7'h7e : $fwrite (fd, " 126"); 7'h7f : $fwrite (fd, " 127"); default:$fwrite (fd, " 128"); endcase end endtask task ozonerb; input [5:0] rb; input [`FD_BITS] fd; // verilator no_inline_task begin case (rb[5:0]) 6'h10, 6'h17, 6'h1e, 6'h1f: $fwrite (fd, " 129"); default: ozonerab({1'b1, rb}, fd); endcase end endtask task ozonef3f4_iext; input [1:0] foo; input [15:0] im16; input [`FD_BITS] fd; // verilator no_inline_task begin case (foo) 2'h0 : begin skyway({4{im16[15]}}, fd); skyway({4{im16[15]}}, fd); skyway(im16[15:12], fd); skyway(im16[11: 8], fd); skyway(im16[ 7: 4], fd); skyway(im16[ 3:0], fd); $fwrite (fd, " 130"); end 2'h1 : begin $fwrite (fd, " 131"); skyway(im16[15:12], fd); skyway(im16[11: 8], fd); skyway(im16[ 7: 4], fd); skyway(im16[ 3:0], fd); end 2'h2 : begin skyway({4{im16[15]}}, fd); skyway({4{im16[15]}}, fd); skyway(im16[15:12], fd); skyway(im16[11: 8], fd); skyway(im16[ 7: 4], fd); skyway(im16[ 3:0], fd); $fwrite (fd, " 132"); end 2'h3 : begin $fwrite (fd, " 133"); skyway(im16[15:12], fd); skyway(im16[11: 8], fd); skyway(im16[ 7: 4], fd); skyway(im16[ 3:0], fd); end endcase end endtask task skyway; input [ 3:0] hex; input [`FD_BITS] fd; // verilator no_inline_task begin case (hex) 4'h0 : $fwrite (fd, " 134"); 4'h1 : $fwrite (fd, " 135"); 4'h2 : $fwrite (fd, " 136"); 4'h3 : $fwrite (fd, " 137"); 4'h4 : $fwrite (fd, " 138"); 4'h5 : $fwrite (fd, " 139"); 4'h6 : $fwrite (fd, " 140"); 4'h7 : $fwrite (fd, " 141"); 4'h8 : $fwrite (fd, " 142"); 4'h9 : $fwrite (fd, " 143"); 4'ha : $fwrite (fd, " 144"); 4'hb : $fwrite (fd, " 145"); 4'hc : $fwrite (fd, " 146"); 4'hd : $fwrite (fd, " 147"); 4'he : $fwrite (fd, " 148"); 4'hf : $fwrite (fd, " 149"); endcase end endtask task ozonesr; input [ 15:0] foo; input [`FD_BITS] fd; // verilator no_inline_task begin case (foo[11: 9]) 3'h0 : $fwrite (fd, " 158"); 3'h1 : $fwrite (fd, " 159"); 3'h2 : $fwrite (fd, " 160"); 3'h3 : $fwrite (fd, " 161"); 3'h4 : $fwrite (fd, " 162"); 3'h5 : $fwrite (fd, " 163"); 3'h6 : $fwrite (fd, " 164"); 3'h7 : $fwrite (fd, " 165"); endcase end endtask task ozonejk; input k; input [`FD_BITS] fd; // verilator no_inline_task begin if (k) $fwrite (fd, " 166"); else $fwrite (fd, " 167"); end endtask task ozoneae; input [ 2:0] ae; input [`FD_BITS] fd; // verilator no_inline_task begin case (ae) 3'b000 : $fwrite (fd, " 168"); 3'b001 : $fwrite (fd, " 169"); 3'b010 : $fwrite (fd, " 170"); 3'b011 : $fwrite (fd, " 171"); 3'b100 : $fwrite (fd, " 172"); 3'b101 : $fwrite (fd, " 173"); 3'b110 : $fwrite (fd, " 174"); 3'b111 : $fwrite (fd, " 175"); endcase end endtask task ozoneaee; input [ 2:0] aee; input [`FD_BITS] fd; // verilator no_inline_task begin case (aee) 3'b001, 3'b011, 3'b101, 3'b111 : $fwrite (fd, " 176"); 3'b000 : $fwrite (fd, " 177"); 3'b010 : $fwrite (fd, " 178"); 3'b100 : $fwrite (fd, " 179"); 3'b110 : $fwrite (fd, " 180"); endcase end endtask task ozoneape; input [ 2:0] ape; input [`FD_BITS] fd; // verilator no_inline_task begin case (ape) 3'b001, 3'b011, 3'b101, 3'b111 : $fwrite (fd, " 181"); 3'b000 : $fwrite (fd, " 182"); 3'b010 : $fwrite (fd, " 183"); 3'b100 : $fwrite (fd, " 184"); 3'b110 : $fwrite (fd, " 185"); endcase end endtask task ozonef1; input [ 31:0] foo; input [`FD_BITS] fd; // verilator no_inline_task begin case (foo[24:21]) 4'h0 : if (foo[26]) $fwrite (fd, " 186"); else $fwrite (fd, " 187"); 4'h1 : case (foo[26:25]) 2'b00 : $fwrite (fd, " 188"); 2'b01 : $fwrite (fd, " 189"); 2'b10 : $fwrite (fd, " 190"); 2'b11 : $fwrite (fd, " 191"); endcase 4'h2 : $fwrite (fd, " 192"); 4'h3 : case (foo[26:25]) 2'b00 : $fwrite (fd, " 193"); 2'b01 : $fwrite (fd, " 194"); 2'b10 : $fwrite (fd, " 195"); 2'b11 : $fwrite (fd, " 196"); endcase 4'h4 : if (foo[26]) $fwrite (fd, " 197"); else $fwrite (fd, " 198"); 4'h5 : case (foo[26:25]) 2'b00 : $fwrite (fd, " 199"); 2'b01 : $fwrite (fd, " 200"); 2'b10 : $fwrite (fd, " 201"); 2'b11 : $fwrite (fd, " 202"); endcase 4'h6 : $fwrite (fd, " 203"); 4'h7 : case (foo[26:25]) 2'b00 : $fwrite (fd, " 204"); 2'b01 : $fwrite (fd, " 205"); 2'b10 : $fwrite (fd, " 206"); 2'b11 : $fwrite (fd, " 207"); endcase 4'h8 : case (foo[26:25]) 2'b00 : $fwrite (fd, " 208"); 2'b01 : $fwrite (fd, " 209"); 2'b10 : $fwrite (fd, " 210"); 2'b11 : $fwrite (fd, " 211"); endcase 4'h9 : case (foo[26:25]) 2'b00 : $fwrite (fd, " 212"); 2'b01 : $fwrite (fd, " 213"); 2'b10 : $fwrite (fd, " 214"); 2'b11 : $fwrite (fd, " 215"); endcase 4'ha : if (foo[25]) $fwrite (fd, " 216"); else $fwrite (fd, " 217"); 4'hb : if (foo[25]) $fwrite (fd, " 218"); else $fwrite (fd, " 219"); 4'hc : if (foo[26]) $fwrite (fd, " 220"); else $fwrite (fd, " 221"); 4'hd : case (foo[26:25]) 2'b00 : $fwrite (fd, " 222"); 2'b01 : $fwrite (fd, " 223"); 2'b10 : $fwrite (fd, " 224"); 2'b11 : $fwrite (fd, " 225"); endcase 4'he : case (foo[26:25]) 2'b00 : $fwrite (fd, " 226"); 2'b01 : $fwrite (fd, " 227"); 2'b10 : $fwrite (fd, " 228"); 2'b11 : $fwrite (fd, " 229"); endcase 4'hf : case (foo[26:25]) 2'b00 : $fwrite (fd, " 230"); 2'b01 : $fwrite (fd, " 231"); 2'b10 : $fwrite (fd, " 232"); 2'b11 : $fwrite (fd, " 233"); endcase endcase end endtask task ozonef1e; input [ 31:0] foo; input [`FD_BITS] fd; // verilator no_inline_task begin case (foo[27:21]) 7'h00: begin ozoneae(foo[20:18], fd); $fwrite (fd," 234"); $fwrite (fd, " 235"); end 7'h01: begin ozoneae(foo[20:18], fd); $fwrite (fd," 236"); ozoneae(foo[17:15], fd); $fwrite (fd," 237"); $fwrite (fd, " 238"); end 7'h02: $fwrite (fd, " 239"); 7'h03: begin ozoneae(foo[20:18], fd); $fwrite (fd," 240"); ozoneae(foo[17:15], fd); $fwrite (fd," 241"); $fwrite (fd, " 242"); end 7'h04: begin ozoneae(foo[20:18], fd); $fwrite (fd," 243"); $fwrite (fd," 244"); end 7'h05: begin ozoneae(foo[20:18], fd); $fwrite (fd," 245"); ozoneae(foo[17:15], fd); $fwrite (fd," 246"); end 7'h06: $fwrite (fd, " 247"); 7'h07: begin ozoneae(foo[20:18], fd); $fwrite (fd," 248"); ozoneae(foo[17:15], fd); $fwrite (fd," 249"); end 7'h08: begin ozoneae(foo[20:18], fd); $fwrite (fd," 250"); ozoneae(foo[17:15], fd); $fwrite (fd," 251"); end 7'h09: begin ozoneae(foo[20:18], fd); $fwrite (fd," 252"); ozoneae(foo[17:15], fd); $fwrite (fd," 253"); end 7'h0a: begin ozoneae(foo[17:15], fd); $fwrite (fd," 254"); end 7'h0b: begin ozoneae(foo[17:15], fd); $fwrite (fd," 255"); end 7'h0c: begin ozoneae(foo[20:18], fd); $fwrite (fd," 256"); end 7'h0d: begin ozoneae(foo[20:18], fd); $fwrite (fd," 257"); ozoneae(foo[17:15], fd); $fwrite (fd," 258"); end 7'h0e: begin ozoneae(foo[20:18], fd); $fwrite (fd," 259"); ozoneae(foo[17:15], fd); $fwrite (fd," 260"); end 7'h0f: begin ozoneae(foo[20:18], fd); $fwrite (fd," 261"); ozoneae(foo[17:15], fd); $fwrite (fd," 262"); end 7'h10: begin ozoneae(foo[20:18], fd); $fwrite (fd," 263"); ozoneae(foo[17:15], fd); $fwrite (fd," 264"); $fwrite (fd, " 265"); $fwrite (fd, " 266"); end 7'h11: begin ozoneae(foo[20:18], fd); $fwrite (fd," 267"); ozoneae(foo[17:15], fd); $fwrite (fd," 268"); $fwrite (fd, " 269"); $fwrite (fd, " 270"); end 7'h12: begin ozoneae(foo[20:18], fd); $fwrite (fd," 271"); ozoneae(foo[17:15], fd); $fwrite (fd," 272"); $fwrite (fd, " 273"); $fwrite (fd, " 274"); end 7'h13: begin ozoneae(foo[20:18], fd); $fwrite (fd," 275"); ozoneae(foo[17:15], fd); $fwrite (fd," 276"); $fwrite (fd, " 277"); $fwrite (fd, " 278"); end 7'h14: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 279"); ozoneaee(foo[17:15], fd); $fwrite (fd," 280"); ozoneape(foo[20:18], fd); $fwrite (fd," 281"); ozoneape(foo[17:15], fd); $fwrite (fd," 282"); $fwrite (fd, " 283"); $fwrite (fd, " 284"); end 7'h15: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 285"); ozoneaee(foo[17:15], fd); $fwrite (fd," 286"); ozoneape(foo[20:18], fd); $fwrite (fd," 287"); ozoneape(foo[17:15], fd); $fwrite (fd," 288"); $fwrite (fd, " 289"); $fwrite (fd, " 290"); end 7'h16: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 291"); ozoneaee(foo[17:15], fd); $fwrite (fd," 292"); ozoneape(foo[20:18], fd); $fwrite (fd," 293"); ozoneape(foo[17:15], fd); $fwrite (fd," 294"); $fwrite (fd, " 295"); $fwrite (fd, " 296"); end 7'h17: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 297"); ozoneaee(foo[17:15], fd); $fwrite (fd," 298"); ozoneape(foo[20:18], fd); $fwrite (fd," 299"); ozoneape(foo[17:15], fd); $fwrite (fd," 300"); $fwrite (fd, " 301"); $fwrite (fd, " 302"); end 7'h18: begin ozoneae(foo[20:18], fd); $fwrite (fd," 303"); ozoneae(foo[17:15], fd); $fwrite (fd," 304"); $fwrite (fd, " 305"); $fwrite (fd, " 306"); end 7'h19: begin ozoneae(foo[20:18], fd); $fwrite (fd," 307"); ozoneae(foo[17:15], fd); $fwrite (fd," 308"); $fwrite (fd, " 309"); $fwrite (fd, " 310"); end 7'h1a: begin ozoneae(foo[20:18], fd); $fwrite (fd," 311"); ozoneae(foo[17:15], fd); $fwrite (fd," 312"); $fwrite (fd, " 313"); $fwrite (fd, " 314"); end 7'h1b: begin ozoneae(foo[20:18], fd); $fwrite (fd," 315"); ozoneae(foo[17:15], fd); $fwrite (fd," 316"); $fwrite (fd, " 317"); $fwrite (fd, " 318"); end 7'h1c: begin ozoneae(foo[20:18], fd); $fwrite (fd," 319"); ozoneae(foo[17:15], fd); $fwrite (fd," 320"); $fwrite (fd, " 321"); $fwrite (fd, " 322"); end 7'h1d: begin ozoneae(foo[20:18], fd); $fwrite (fd," 323"); ozoneae(foo[17:15], fd); $fwrite (fd," 324"); $fwrite (fd, " 325"); $fwrite (fd, " 326"); end 7'h1e: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 327"); ozoneaee(foo[17:15], fd); $fwrite (fd," 328"); ozoneape(foo[20:18], fd); $fwrite (fd," 329"); ozoneape(foo[17:15], fd); $fwrite (fd," 330"); $fwrite (fd, " 331"); $fwrite (fd, " 332"); end 7'h1f: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 333"); ozoneaee(foo[17:15], fd); $fwrite (fd," 334"); ozoneape(foo[20:18], fd); $fwrite (fd," 335"); ozoneape(foo[17:15], fd); $fwrite (fd," 336"); $fwrite (fd, " 337"); $fwrite (fd, " 338"); end 7'h20: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 339"); ozoneaee(foo[17:15], fd); $fwrite (fd," 340"); ozoneape(foo[20:18], fd); $fwrite (fd," 341"); ozoneape(foo[17:15], fd); $fwrite (fd," 342"); $fwrite (fd, " 343"); $fwrite (fd, " 344"); end 7'h21: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 345"); ozoneaee(foo[17:15], fd); $fwrite (fd," 346"); ozoneape(foo[20:18], fd); $fwrite (fd," 347"); ozoneape(foo[17:15], fd); $fwrite (fd," 348"); $fwrite (fd, " 349"); $fwrite (fd, " 350"); end 7'h22: begin ozoneae(foo[20:18], fd); $fwrite (fd," 351"); ozoneae(foo[17:15], fd); $fwrite (fd," 352"); $fwrite (fd, " 353"); $fwrite (fd, " 354"); end 7'h23: begin ozoneae(foo[20:18], fd); $fwrite (fd," 355"); ozoneae(foo[17:15], fd); $fwrite (fd," 356"); $fwrite (fd, " 357"); $fwrite (fd, " 358"); end 7'h24: begin ozoneae(foo[20:18], fd); $fwrite (fd," 359"); ozoneae(foo[17:15], fd); $fwrite (fd," 360"); $fwrite (fd, " 361"); $fwrite (fd, " 362"); end 7'h25: begin ozoneae(foo[20:18], fd); $fwrite (fd," 363"); ozoneae(foo[17:15], fd); $fwrite (fd," 364"); $fwrite (fd, " 365"); $fwrite (fd, " 366"); end 7'h26: begin ozoneae(foo[20:18], fd); $fwrite (fd," 367"); ozoneae(foo[17:15], fd); $fwrite (fd," 368"); $fwrite (fd, " 369"); $fwrite (fd, " 370"); end 7'h27: begin ozoneae(foo[20:18], fd); $fwrite (fd," 371"); ozoneae(foo[17:15], fd); $fwrite (fd," 372"); $fwrite (fd, " 373"); $fwrite (fd, " 374"); end 7'h28: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 375"); ozoneaee(foo[17:15], fd); $fwrite (fd," 376"); ozoneape(foo[20:18], fd); $fwrite (fd," 377"); ozoneape(foo[17:15], fd); $fwrite (fd," 378"); $fwrite (fd, " 379"); $fwrite (fd, " 380"); end 7'h29: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 381"); ozoneaee(foo[17:15], fd); $fwrite (fd," 382"); ozoneape(foo[20:18], fd); $fwrite (fd," 383"); ozoneape(foo[17:15], fd); $fwrite (fd," 384"); $fwrite (fd, " 385"); $fwrite (fd, " 386"); end 7'h2a: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 387"); ozoneaee(foo[17:15], fd); $fwrite (fd," 388"); ozoneape(foo[20:18], fd); $fwrite (fd," 389"); ozoneape(foo[17:15], fd); $fwrite (fd," 390"); $fwrite (fd, " 391"); $fwrite (fd, " 392"); end 7'h2b: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 393"); ozoneaee(foo[17:15], fd); $fwrite (fd," 394"); ozoneape(foo[20:18], fd); $fwrite (fd," 395"); ozoneape(foo[17:15], fd); $fwrite (fd," 396"); $fwrite (fd, " 397"); $fwrite (fd, " 398"); end 7'h2c: begin ozoneae(foo[20:18], fd); $fwrite (fd," 399"); ozoneae(foo[17:15], fd); $fwrite (fd," 400"); $fwrite (fd, " 401"); $fwrite (fd, " 402"); end 7'h2d: begin ozoneae(foo[20:18], fd); $fwrite (fd," 403"); ozoneae(foo[17:15], fd); $fwrite (fd," 404"); $fwrite (fd, " 405"); $fwrite (fd, " 406"); end 7'h2e: begin ozoneae(foo[20:18], fd); $fwrite (fd," 407"); ozoneae(foo[17:15], fd); $fwrite (fd," 408"); $fwrite (fd, " 409"); $fwrite (fd, " 410"); end 7'h2f: begin ozoneae(foo[20:18], fd); $fwrite (fd," 411"); ozoneae(foo[17:15], fd); $fwrite (fd," 412"); $fwrite (fd, " 413"); $fwrite (fd, " 414"); end 7'h30: begin ozoneae(foo[20:18], fd); $fwrite (fd," 415"); ozoneae(foo[17:15], fd); $fwrite (fd," 416"); $fwrite (fd, " 417"); $fwrite (fd, " 418"); end 7'h31: begin ozoneae(foo[20:18], fd); $fwrite (fd," 419"); ozoneae(foo[17:15], fd); $fwrite (fd," 420"); $fwrite (fd, " 421"); $fwrite (fd, " 422"); end 7'h32: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 423"); ozoneaee(foo[17:15], fd); $fwrite (fd," 424"); ozoneape(foo[20:18], fd); $fwrite (fd," 425"); ozoneape(foo[17:15], fd); $fwrite (fd," 426"); $fwrite (fd, " 427"); $fwrite (fd, " 428"); end 7'h33: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 429"); ozoneaee(foo[17:15], fd); $fwrite (fd," 430"); ozoneape(foo[20:18], fd); $fwrite (fd," 431"); ozoneape(foo[17:15], fd); $fwrite (fd," 432"); $fwrite (fd, " 433"); $fwrite (fd, " 434"); end 7'h34: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 435"); ozoneaee(foo[17:15], fd); $fwrite (fd," 436"); ozoneape(foo[20:18], fd); $fwrite (fd," 437"); ozoneape(foo[17:15], fd); $fwrite (fd," 438"); $fwrite (fd, " 439"); $fwrite (fd, " 440"); end 7'h35: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 441"); ozoneaee(foo[17:15], fd); $fwrite (fd," 442"); ozoneape(foo[20:18], fd); $fwrite (fd," 443"); ozoneape(foo[17:15], fd); $fwrite (fd," 444"); $fwrite (fd, " 445"); $fwrite (fd, " 446"); end 7'h36: begin ozoneae(foo[20:18], fd); $fwrite (fd," 447"); ozoneae(foo[17:15], fd); $fwrite (fd," 448"); $fwrite (fd, " 449"); $fwrite (fd, " 450"); end 7'h37: begin ozoneae(foo[20:18], fd); $fwrite (fd," 451"); ozoneae(foo[17:15], fd); $fwrite (fd," 452"); $fwrite (fd, " 453"); $fwrite (fd, " 454"); end 7'h38: begin ozoneae(foo[20:18], fd); $fwrite (fd," 455"); ozoneae(foo[17:15], fd); $fwrite (fd," 456"); $fwrite (fd, " 457"); end 7'h39: begin ozoneae(foo[20:18], fd); $fwrite (fd," 458"); ozoneae(foo[17:15], fd); $fwrite (fd," 459"); $fwrite (fd, " 460"); end 7'h3a: begin ozoneae(foo[20:18], fd); $fwrite (fd," 461"); ozoneae(foo[17:15], fd); $fwrite (fd," 462"); $fwrite (fd, " 463"); end 7'h3b: begin ozoneae(foo[20:18], fd); $fwrite (fd," 464"); ozoneae(foo[17:15], fd); $fwrite (fd," 465"); $fwrite (fd, " 466"); end 7'h3c: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 467"); ozoneaee(foo[17:15], fd); $fwrite (fd," 468"); ozoneape(foo[20:18], fd); $fwrite (fd," 469"); ozoneape(foo[17:15], fd); $fwrite (fd," 470"); $fwrite (fd, " 471"); end 7'h3d: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 472"); ozoneaee(foo[17:15], fd); $fwrite (fd," 473"); ozoneape(foo[20:18], fd); $fwrite (fd," 474"); ozoneape(foo[17:15], fd); $fwrite (fd," 475"); $fwrite (fd, " 476"); end 7'h3e: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 477"); ozoneaee(foo[17:15], fd); $fwrite (fd," 478"); ozoneape(foo[20:18], fd); $fwrite (fd," 479"); ozoneape(foo[17:15], fd); $fwrite (fd," 480"); $fwrite (fd, " 481"); end 7'h3f: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 482"); ozoneaee(foo[17:15], fd); $fwrite (fd," 483"); ozoneape(foo[20:18], fd); $fwrite (fd," 484"); ozoneape(foo[17:15], fd); $fwrite (fd," 485"); $fwrite (fd, " 486"); end 7'h40: begin ozoneae(foo[20:18], fd); $fwrite (fd," 487"); ozoneae(foo[17:15], fd); $fwrite (fd," 488"); $fwrite (fd, " 489"); $fwrite (fd, " 490"); end 7'h41: begin $fwrite (fd, " 491"); $fwrite (fd, " 492"); end 7'h42: begin $fwrite (fd, " 493"); $fwrite (fd, " 494"); end 7'h43: begin $fwrite (fd, " 495"); $fwrite (fd, " 496"); end 7'h44: begin $fwrite (fd, " 497"); $fwrite (fd, " 498"); end 7'h45: $fwrite (fd, " 499"); 7'h46: begin ozoneae(foo[20:18], fd); $fwrite (fd," 500"); $fwrite (fd, " 501"); $fwrite (fd, " 502"); end 7'h47: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 503"); ozoneae(foo[17:15], fd); $fwrite (fd," 504"); ozoneape(foo[20:18], fd); $fwrite (fd," 505"); ozoneape(foo[20:18], fd); $fwrite (fd," 506"); $fwrite (fd, " 507"); $fwrite (fd, " 508"); end 7'h48: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 509"); ozoneape(foo[20:18], fd); $fwrite (fd," 510"); ozoneape(foo[20:18], fd); $fwrite (fd," 511"); ozoneaee(foo[17:15], fd); $fwrite (fd," 512"); ozoneape(foo[17:15], fd); $fwrite (fd," 513"); end 7'h49: begin ozoneae(foo[20:18], fd); $fwrite (fd," 514"); ozoneaee(foo[17:15], fd); $fwrite (fd," 515"); ozoneape(foo[17:15], fd); $fwrite (fd," 516"); end 7'h4a: $fwrite (fd," 517"); 7'h4b: $fwrite (fd, " 518"); 7'h4c: begin ozoneae(foo[20:18], fd); $fwrite (fd," 519"); $fwrite (fd, " 520"); $fwrite (fd, " 521"); end 7'h4d: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 522"); ozoneae(foo[17:15], fd); $fwrite (fd," 523"); ozoneape(foo[20:18], fd); $fwrite (fd," 524"); ozoneape(foo[20:18], fd); $fwrite (fd," 525"); $fwrite (fd, " 526"); $fwrite (fd, " 527"); end 7'h4e: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 528"); ozoneae(foo[17:15], fd); $fwrite (fd," 529"); ozoneape(foo[20:18], fd); $fwrite (fd," 530"); ozoneape(foo[20:18], fd); $fwrite (fd," 531"); end 7'h4f: begin ozoneae(foo[20:18], fd); $fwrite (fd," 532"); end 7'h50: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 533"); ozoneae(foo[17:15], fd); $fwrite (fd," 534"); ozoneaee(foo[20:18], fd); $fwrite (fd," 535"); ozoneae(foo[17:15], fd); $fwrite (fd," 536"); ozoneape(foo[20:18], fd); $fwrite (fd," 537"); ozoneae(foo[17:15], fd); $fwrite (fd," 538"); ozoneape(foo[20:18], fd); $fwrite (fd," 539"); ozoneae(foo[17:15], fd); $fwrite (fd," 540"); end 7'h51: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 541"); ozoneape(foo[20:18], fd); $fwrite (fd," 542"); ozoneaee(foo[20:18], fd); $fwrite (fd," 543"); ozoneape(foo[20:18], fd); $fwrite (fd," 544"); ozoneae(foo[17:15], fd); $fwrite (fd," 545"); end 7'h52: $fwrite (fd, " 546"); 7'h53: begin ozoneae(foo[20:18], fd); $fwrite (fd, " 547"); end 7'h54: begin ozoneae(foo[20:18], fd); $fwrite (fd," 548"); ozoneae(foo[17:15], fd); $fwrite (fd," 549"); end 7'h55: begin ozoneae(foo[20:18], fd); $fwrite (fd," 550"); ozoneae(foo[17:15], fd); $fwrite (fd," 551"); end 7'h56: begin ozoneae(foo[20:18], fd); $fwrite (fd," 552"); ozoneae(foo[17:15], fd); $fwrite (fd," 553"); $fwrite (fd, " 554"); end 7'h57: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 555"); ozoneae(foo[17:15], fd); $fwrite (fd," 556"); ozoneape(foo[20:18], fd); $fwrite (fd," 557"); ozoneape(foo[20:18], fd); $fwrite (fd," 558"); end 7'h58: begin ozoneae(foo[20:18], fd); $fwrite (fd, " 559"); end 7'h59: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 560"); ozoneae(foo[17:15], fd); $fwrite (fd," 561"); ozoneape(foo[20:18], fd); $fwrite (fd," 562"); ozoneape(foo[20:18], fd); $fwrite (fd," 563"); end 7'h5a: begin ozoneae(foo[20:18], fd); $fwrite (fd," 564"); ozoneae(foo[17:15], fd); $fwrite (fd, " 565"); end 7'h5b: begin ozoneae(foo[20:18], fd); $fwrite (fd," 566"); ozoneae(foo[17:15], fd); $fwrite (fd, " 567"); end 7'h5c: begin $fwrite (fd," 568"); ozoneape(foo[17:15], fd); $fwrite (fd," 569"); $fwrite (fd," 570"); ozoneape(foo[17:15], fd); $fwrite (fd," 571"); ozoneae(foo[20:18], fd); $fwrite (fd," 572"); ozoneaee(foo[17:15], fd); $fwrite (fd, " 573"); end 7'h5d: begin $fwrite (fd," 574"); ozoneape(foo[17:15], fd); $fwrite (fd," 575"); $fwrite (fd," 576"); ozoneape(foo[17:15], fd); $fwrite (fd," 577"); ozoneae(foo[20:18], fd); $fwrite (fd," 578"); ozoneaee(foo[17:15], fd); $fwrite (fd, " 579"); end 7'h5e: begin ozoneae(foo[20:18], fd); $fwrite (fd," 580"); ozoneae(foo[17:15], fd); $fwrite (fd, " 581"); end 7'h5f: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 582"); ozoneae(foo[17:15], fd); $fwrite (fd," 583"); ozoneaee(foo[20:18], fd); $fwrite (fd," 584"); ozoneae(foo[17:15], fd); $fwrite (fd," 585"); ozoneape(foo[20:18], fd); $fwrite (fd," 586"); ozoneae(foo[17:15], fd); $fwrite (fd," 587"); ozoneape(foo[20:18], fd); $fwrite (fd," 588"); ozoneae(foo[17:15], fd); $fwrite (fd," 589"); end 7'h60: begin ozoneae(foo[20:18], fd); $fwrite (fd," 590"); ozoneae(foo[17:15], fd); $fwrite (fd," 591"); end 7'h61: begin ozoneae(foo[20:18], fd); $fwrite (fd," 592"); ozoneae(foo[17:15], fd); $fwrite (fd," 593"); end 7'h62: begin ozoneae(foo[20:18], fd); $fwrite (fd," 594"); ozoneae(foo[17:15], fd); $fwrite (fd," 595"); end 7'h63: begin ozoneae(foo[20:18], fd); $fwrite (fd," 596"); ozoneae(foo[17:15], fd); $fwrite (fd," 597"); end 7'h64: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 598"); ozoneaee(foo[17:15], fd); $fwrite (fd," 599"); ozoneape(foo[20:18], fd); $fwrite (fd," 600"); ozoneape(foo[17:15], fd); $fwrite (fd," 601"); end 7'h65: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 602"); ozoneaee(foo[17:15], fd); $fwrite (fd," 603"); ozoneape(foo[20:18], fd); $fwrite (fd," 604"); ozoneape(foo[17:15], fd); $fwrite (fd," 605"); end 7'h66: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 606"); ozoneaee(foo[17:15], fd); $fwrite (fd," 607"); ozoneape(foo[20:18], fd); $fwrite (fd," 608"); ozoneape(foo[17:15], fd); $fwrite (fd," 609"); end 7'h67: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 610"); ozoneaee(foo[17:15], fd); $fwrite (fd," 611"); ozoneape(foo[20:18], fd); $fwrite (fd," 612"); ozoneape(foo[17:15], fd); $fwrite (fd," 613"); end 7'h68: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 614"); ozoneaee(foo[17:15], fd); $fwrite (fd," 615"); ozoneaee(foo[20:18], fd); $fwrite (fd," 616"); ozoneape(foo[20:18], fd); $fwrite (fd," 617"); ozoneape(foo[20:18], fd); $fwrite (fd," 618"); ozoneape(foo[17:15], fd); end 7'h69: begin ozoneae(foo[20:18], fd); $fwrite (fd," 619"); ozoneae(foo[17:15], fd); $fwrite (fd," 620"); ozoneae(foo[20:18], fd); $fwrite (fd," 621"); end 7'h6a: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 622"); ozoneae(foo[17:15], fd); $fwrite (fd," 623"); ozoneaee(foo[20:18], fd); $fwrite (fd," 624"); ozoneape(foo[20:18], fd); $fwrite (fd," 625"); ozoneaee(foo[20:18], fd); $fwrite (fd," 626"); ozoneae(foo[17:15], fd); end 7'h6b: begin ozoneae(foo[20:18], fd); $fwrite (fd," 627"); ozoneae(foo[17:15], fd); $fwrite (fd," 628"); ozoneae(foo[20:18], fd); $fwrite (fd," 629"); end 7'h6c: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 630"); ozoneae(foo[17:15], fd); $fwrite (fd," 631"); ozoneaee(foo[20:18], fd); $fwrite (fd," 632"); ozoneape(foo[20:18], fd); $fwrite (fd," 633"); ozoneaee(foo[20:18], fd); $fwrite (fd," 634"); ozoneae(foo[17:15], fd); end 7'h6d: begin ozoneae(foo[20:18], fd); $fwrite (fd," 635"); ozoneae(foo[17:15], fd); $fwrite (fd," 636"); ozoneae(foo[20:18], fd); $fwrite (fd," 637"); end 7'h6e: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 638"); ozoneaee(foo[17:15], fd); $fwrite (fd," 639"); ozoneape(foo[20:18], fd); $fwrite (fd," 640"); ozoneape(foo[17:15], fd); $fwrite (fd," 641"); end 7'h6f: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 642"); ozoneaee(foo[17:15], fd); $fwrite (fd," 643"); ozoneape(foo[20:18], fd); $fwrite (fd," 644"); ozoneape(foo[17:15], fd); $fwrite (fd," 645"); end 7'h70: begin ozoneae(foo[20:18], fd); $fwrite (fd," 646"); ozoneae(foo[20:18], fd); $fwrite (fd," 647"); ozoneae(foo[17:15], fd); $fwrite (fd," 648"); ozoneae(foo[17:15], fd); $fwrite (fd, " 649"); end 7'h71: begin ozoneae(foo[20:18], fd); $fwrite (fd," 650"); ozoneae(foo[17:15], fd); $fwrite (fd, " 651"); end 7'h72: begin ozoneae(foo[20:18], fd); $fwrite (fd," 652"); ozoneae(foo[17:15], fd); $fwrite (fd, " 653"); end 7'h73: begin ozoneae(foo[20:18], fd); $fwrite (fd," 654"); ozoneae(foo[20:18], fd); $fwrite (fd," 655"); ozoneae(foo[17:15], fd); end 7'h74: begin ozoneae(foo[20:18], fd); $fwrite (fd," 656"); ozoneae(foo[20:18], fd); $fwrite (fd," 657"); ozoneae(foo[17:15], fd); end 7'h75: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 658"); ozoneaee(foo[17:15], fd); $fwrite (fd," 659"); ozoneape(foo[20:18], fd); $fwrite (fd," 660"); ozoneape(foo[17:15], fd); $fwrite (fd," 661"); $fwrite (fd, " 662"); $fwrite (fd, " 663"); end 7'h76: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 664"); ozoneaee(foo[17:15], fd); $fwrite (fd," 665"); ozoneaee(foo[20:18], fd); $fwrite (fd," 666"); ozoneape(foo[20:18], fd); $fwrite (fd," 667"); ozoneape(foo[17:15], fd); $fwrite (fd," 668"); ozoneape(foo[20:18], fd); $fwrite (fd," 669"); end 7'h77: begin ozoneaee(foo[20:18], fd); $fwrite (fd," 670"); ozoneaee(foo[17:15], fd); $fwrite (fd," 671"); ozoneaee(foo[17:15], fd); $fwrite (fd," 672"); ozoneape(foo[20:18], fd); $fwrite (fd," 673"); ozoneape(foo[17:15], fd); $fwrite (fd," 674"); ozoneape(foo[17:15], fd); $fwrite (fd," 675"); end 7'h78, 7'h79, 7'h7a, 7'h7b, 7'h7c, 7'h7d, 7'h7e, 7'h7f: $fwrite (fd," 676"); endcase end endtask task ozonef2; input [ 31:0] foo; input [`FD_BITS] fd; // verilator no_inline_task begin case (foo[24:21]) 4'h0 : case (foo[26:25]) 2'b00 : $fwrite (fd," 677"); 2'b01 : $fwrite (fd," 678"); 2'b10 : $fwrite (fd," 679"); 2'b11 : $fwrite (fd," 680"); endcase 4'h1 : case (foo[26:25]) 2'b00 : $fwrite (fd," 681"); 2'b01 : $fwrite (fd," 682"); 2'b10 : $fwrite (fd," 683"); 2'b11 : $fwrite (fd," 684"); endcase 4'h2 : case (foo[26:25]) 2'b00 : $fwrite (fd," 685"); 2'b01 : $fwrite (fd," 686"); 2'b10 : $fwrite (fd," 687"); 2'b11 : $fwrite (fd," 688"); endcase 4'h3 : case (foo[26:25]) 2'b00 : $fwrite (fd," 689"); 2'b01 : $fwrite (fd," 690"); 2'b10 : $fwrite (fd," 691"); 2'b11 : $fwrite (fd," 692"); endcase 4'h4 : case (foo[26:25]) 2'b00 : $fwrite (fd," 693"); 2'b01 : $fwrite (fd," 694"); 2'b10 : $fwrite (fd," 695"); 2'b11 : $fwrite (fd," 696"); endcase 4'h5 : case (foo[26:25]) 2'b00 : $fwrite (fd," 697"); 2'b01 : $fwrite (fd," 698"); 2'b10 : $fwrite (fd," 699"); 2'b11 : $fwrite (fd," 700"); endcase 4'h6 : case (foo[26:25]) 2'b00 : $fwrite (fd," 701"); 2'b01 : $fwrite (fd," 702"); 2'b10 : $fwrite (fd," 703"); 2'b11 : $fwrite (fd," 704"); endcase 4'h7 : case (foo[26:25]) 2'b00 : $fwrite (fd," 705"); 2'b01 : $fwrite (fd," 706"); 2'b10 : $fwrite (fd," 707"); 2'b11 : $fwrite (fd," 708"); endcase 4'h8 : if (foo[26]) $fwrite (fd," 709"); else $fwrite (fd," 710"); 4'h9 : case (foo[26:25]) 2'b00 : $fwrite (fd," 711"); 2'b01 : $fwrite (fd," 712"); 2'b10 : $fwrite (fd," 713"); 2'b11 : $fwrite (fd," 714"); endcase 4'ha : case (foo[26:25]) 2'b00 : $fwrite (fd," 715"); 2'b01 : $fwrite (fd," 716"); 2'b10 : $fwrite (fd," 717"); 2'b11 : $fwrite (fd," 718"); endcase 4'hb : case (foo[26:25]) 2'b00 : $fwrite (fd," 719"); 2'b01 : $fwrite (fd," 720"); 2'b10 : $fwrite (fd," 721"); 2'b11 : $fwrite (fd," 722"); endcase 4'hc : if (foo[26]) $fwrite (fd," 723"); else $fwrite (fd," 724"); 4'hd : case (foo[26:25]) 2'b00 : $fwrite (fd," 725"); 2'b01 : $fwrite (fd," 726"); 2'b10 : $fwrite (fd," 727"); 2'b11 : $fwrite (fd," 728"); endcase 4'he : case (foo[26:25]) 2'b00 : $fwrite (fd," 729"); 2'b01 : $fwrite (fd," 730"); 2'b10 : $fwrite (fd," 731"); 2'b11 : $fwrite (fd," 732"); endcase 4'hf : case (foo[26:25]) 2'b00 : $fwrite (fd," 733"); 2'b01 : $fwrite (fd," 734"); 2'b10 : $fwrite (fd," 735"); 2'b11 : $fwrite (fd," 736"); endcase endcase end endtask task ozonef2e; input [ 31:0] foo; input [`FD_BITS] fd; // verilator no_inline_task begin casez (foo[25:21]) 5'h00 : begin ozoneae(foo[20:18], fd); $fwrite (fd," 737"); ozoneae(foo[17:15], fd); $fwrite (fd," 738"); end 5'h01 : begin ozoneae(foo[20:18], fd); $fwrite (fd," 739"); ozoneae(foo[17:15], fd); $fwrite (fd," 740"); end 5'h02 : begin ozoneae(foo[20:18], fd); $fwrite (fd," 741"); ozoneae(foo[17:15], fd); $fwrite (fd," 742"); end 5'h03 : begin ozoneae(foo[20:18], fd); $fwrite (fd," 743"); ozoneae(foo[17:15], fd); $fwrite (fd," 744"); end 5'h04 : begin ozoneae(foo[20:18], fd); $fwrite (fd," 745"); ozoneae(foo[17:15], fd); $fwrite (fd," 746"); end 5'h05 : begin ozoneae(foo[20:18], fd); $fwrite (fd," 747"); ozoneae(foo[17:15], fd); $fwrite (fd," 748"); end 5'h06 : begin ozoneae(foo[20:18], fd); $fwrite (fd," 749"); ozoneae(foo[17:15], fd); $fwrite (fd," 750"); end 5'h07 : begin ozoneae(foo[20:18], fd); $fwrite (fd," 751"); ozoneae(foo[17:15], fd); $fwrite (fd," 752"); end 5'h08 : begin ozoneae(foo[20:18], fd); $fwrite (fd," 753"); if (foo[ 6]) $fwrite (fd," 754"); else $fwrite (fd," 755"); end 5'h09 : begin ozoneae(foo[20:18], fd); $fwrite (fd," 756"); ozoneae(foo[17:15], fd); $fwrite (fd," 757"); end 5'h0a : begin ozoneae(foo[20:18], fd); $fwrite (fd," 758"); ozoneae(foo[17:15], fd); end 5'h0b : begin ozoneae(foo[20:18], fd); $fwrite (fd," 759"); ozoneae(foo[17:15], fd); $fwrite (fd," 760"); end 5'h0c : begin ozoneae(foo[20:18], fd); $fwrite (fd," 761"); end 5'h0d : begin ozoneae(foo[20:18], fd); $fwrite (fd," 762"); ozoneae(foo[17:15], fd); $fwrite (fd," 763"); end 5'h0e : begin ozoneae(foo[20:18], fd); $fwrite (fd," 764"); ozoneae(foo[17:15], fd); end 5'h0f : begin ozoneae(foo[20:18], fd); $fwrite (fd," 765"); ozoneae(foo[17:15], fd); end 5'h10 : begin ozoneae(foo[20:18], fd); $fwrite (fd," 766"); ozoneae(foo[17:15], fd); $fwrite (fd," 767"); end 5'h11 : begin ozoneae(foo[20:18], fd); $fwrite (fd," 768"); ozoneae(foo[17:15], fd); $fwrite (fd," 769"); end 5'h18 : begin ozoneae(foo[20:18], fd); $fwrite (fd," 770"); if (foo[ 6]) $fwrite (fd," 771"); else $fwrite (fd," 772"); end 5'h1a : begin ozoneae(foo[20:18], fd); $fwrite (fd," 773"); ozoneae(foo[17:15], fd); $fwrite (fd," 774"); end 5'h1b : begin ozoneae(foo[20:18], fd); $fwrite (fd," 775"); ozoneae(foo[17:15], fd); $fwrite (fd," 776"); if (foo[ 6]) $fwrite (fd," 777"); else $fwrite (fd," 778"); $fwrite (fd," 779"); end 5'h1c : begin ozoneae(foo[20:18], fd); $fwrite (fd," 780"); end 5'h1d : begin ozoneae(foo[20:18], fd); $fwrite (fd," 781"); if (foo[ 6]) $fwrite (fd," 782"); else $fwrite (fd," 783"); $fwrite (fd," 784"); end 5'h1e : begin ozoneae(foo[20:18], fd); $fwrite (fd," 785"); if (foo[ 6]) $fwrite (fd," 786"); else $fwrite (fd," 787"); $fwrite (fd," 788"); end 5'h1f : begin ozoneae(foo[20:18], fd); $fwrite (fd," 789"); ozoneae(foo[17:15], fd); $fwrite (fd," 790"); if (foo[ 6]) $fwrite (fd," 791"); else $fwrite (fd," 792"); $fwrite (fd," 793"); end default : $fwrite (fd," 794"); endcase end endtask task ozonef3e; input [ 31:0] foo; input [`FD_BITS] fd; // verilator no_inline_task begin case (foo[25:21]) 5'h00, 5'h01, 5'h02: begin ozoneae(foo[20:18], fd); case (foo[22:21]) 2'h0: $fwrite (fd," 795"); 2'h1: $fwrite (fd," 796"); 2'h2: $fwrite (fd," 797"); endcase ozoneae(foo[17:15], fd); $fwrite (fd," 798"); if (foo[ 9]) ozoneae(foo[ 8: 6], fd); else ozonef3e_te(foo[ 8: 6], fd); $fwrite (fd," 799"); end 5'h08, 5'h09, 5'h0d, 5'h0e, 5'h0f: begin ozoneae(foo[20:18], fd); $fwrite (fd," 800"); ozoneae(foo[17:15], fd); case (foo[23:21]) 3'h0: $fwrite (fd," 801"); 3'h1: $fwrite (fd," 802"); 3'h5: $fwrite (fd," 803"); 3'h6: $fwrite (fd," 804"); 3'h7: $fwrite (fd," 805"); endcase if (foo[ 9]) ozoneae(foo[ 8: 6], fd); else ozonef3e_te(foo[ 8: 6], fd); end 5'h0a, 5'h0b: begin ozoneae(foo[17:15], fd); if (foo[21]) $fwrite (fd," 806"); else $fwrite (fd," 807"); if (foo[ 9]) ozoneae(foo[ 8: 6], fd); else ozonef3e_te(foo[ 8: 6], fd); end 5'h0c: begin ozoneae(foo[20:18], fd); $fwrite (fd," 808"); if (foo[ 9]) ozoneae(foo[ 8: 6], fd); else ozonef3e_te(foo[ 8: 6], fd); $fwrite (fd," 809"); ozoneae(foo[17:15], fd); end 5'h10, 5'h11, 5'h12, 5'h13: begin ozoneae(foo[20:18], fd); $fwrite (fd," 810"); ozoneae(foo[17:15], fd); case (foo[22:21]) 2'h0, 2'h2: $fwrite (fd," 811"); 2'h1, 2'h3: $fwrite (fd," 812"); endcase ozoneae(foo[ 8: 6], fd); $fwrite (fd," 813"); ozoneae((foo[20:18]+1), fd); $fwrite (fd," 814"); ozoneae((foo[17:15]+1), fd); case (foo[22:21]) 2'h0, 2'h3: $fwrite (fd," 815"); 2'h1, 2'h2: $fwrite (fd," 816"); endcase ozoneae((foo[ 8: 6]+1), fd); end 5'h18: begin ozoneae(foo[20:18], fd); $fwrite (fd," 817"); ozoneae(foo[17:15], fd); $fwrite (fd," 818"); ozoneae(foo[ 8: 6], fd); $fwrite (fd," 819"); ozoneae(foo[20:18], fd); $fwrite (fd," 820"); ozoneae(foo[17:15], fd); $fwrite (fd," 821"); ozoneae(foo[ 8: 6], fd); end default : $fwrite (fd," 822"); endcase end endtask task ozonef3e_te; input [ 2:0] te; input [`FD_BITS] fd; // verilator no_inline_task begin case (te) 3'b100 : $fwrite (fd, " 823"); 3'b101 : $fwrite (fd, " 824"); 3'b110 : $fwrite (fd, " 825"); default: $fwrite (fd, " 826"); endcase end endtask task ozonearm; input [ 2:0] ate; input [`FD_BITS] fd; // verilator no_inline_task begin case (ate) 3'b000 : $fwrite (fd, " 827"); 3'b001 : $fwrite (fd, " 828"); 3'b010 : $fwrite (fd, " 829"); 3'b011 : $fwrite (fd, " 830"); 3'b100 : $fwrite (fd, " 831"); 3'b101 : $fwrite (fd, " 832"); 3'b110 : $fwrite (fd, " 833"); 3'b111 : $fwrite (fd, " 834"); endcase end endtask task ozonebmuop; input [ 4:0] f4; input [`FD_BITS] fd; // verilator no_inline_task begin case (f4[ 4:0]) 5'h00, 5'h04 : $fwrite (fd, " 835"); 5'h01, 5'h05 : $fwrite (fd, " 836"); 5'h02, 5'h06 : $fwrite (fd, " 837"); 5'h03, 5'h07 : $fwrite (fd, " 838"); 5'h08, 5'h18 : $fwrite (fd, " 839"); 5'h09, 5'h19 : $fwrite (fd, " 840"); 5'h0a, 5'h1a : $fwrite (fd, " 841"); 5'h0b : $fwrite (fd, " 842"); 5'h1b : $fwrite (fd, " 843"); 5'h0c, 5'h1c : $fwrite (fd, " 844"); 5'h0d, 5'h1d : $fwrite (fd, " 845"); 5'h1e : $fwrite (fd, " 846"); endcase end endtask task automatic ozonef3; input [ 31:0] foo; input [`FD_BITS] fd; reg nacho; // verilator no_inline_task begin : f3_body nacho = 1'b0; case (foo[24:21]) 4'h0: case (foo[26:25]) 2'b00 : $fwrite (fd, " 847"); 2'b01 : $fwrite (fd, " 848"); 2'b10 : $fwrite (fd, " 849"); 2'b11 : $fwrite (fd, " 850"); endcase 4'h1: case (foo[26:25]) 2'b00 : $fwrite (fd, " 851"); 2'b01 : $fwrite (fd, " 852"); 2'b10 : $fwrite (fd, " 853"); 2'b11 : $fwrite (fd, " 854"); endcase 4'h2: case (foo[26:25]) 2'b00 : $fwrite (fd, " 855"); 2'b01 : $fwrite (fd, " 856"); 2'b10 : $fwrite (fd, " 857"); 2'b11 : $fwrite (fd, " 858"); endcase 4'h8, 4'h9, 4'hd, 4'he, 4'hf : case (foo[26:25]) 2'b00 : $fwrite (fd, " 859"); 2'b01 : $fwrite (fd, " 860"); 2'b10 : $fwrite (fd, " 861"); 2'b11 : $fwrite (fd, " 862"); endcase 4'ha, 4'hb : if (foo[25]) $fwrite (fd, " 863"); else $fwrite (fd, " 864"); 4'hc : if (foo[26]) $fwrite (fd, " 865"); else $fwrite (fd, " 866"); default : begin $fwrite (fd, " 867"); nacho = 1'b1; end endcase if (~nacho) begin case (foo[24:21]) 4'h8 : $fwrite (fd, " 868"); 4'h9 : $fwrite (fd, " 869"); 4'ha, 4'he : $fwrite (fd, " 870"); 4'hb, 4'hf : $fwrite (fd, " 871"); 4'hd : $fwrite (fd, " 872"); endcase if (foo[20]) case (foo[18:16]) 3'b000 : $fwrite (fd, " 873"); 3'b100 : $fwrite (fd, " 874"); default: $fwrite (fd, " 875"); endcase else ozoneae(foo[18:16], fd); if (foo[24:21] === 4'hc) if (foo[25]) $fwrite (fd, " 876"); else $fwrite (fd, " 877"); case (foo[24:21]) 4'h0, 4'h1, 4'h2: $fwrite (fd, " 878"); endcase end end endtask task ozonerx; input [ 31:0] foo; input [`FD_BITS] fd; // verilator no_inline_task begin case (foo[19:18]) 2'h0 : $fwrite (fd, " 879"); 2'h1 : $fwrite (fd, " 880"); 2'h2 : $fwrite (fd, " 881"); 2'h3 : $fwrite (fd, " 882"); endcase case (foo[17:16]) 2'h1 : $fwrite (fd, " 883"); 2'h2 : $fwrite (fd, " 884"); 2'h3 : $fwrite (fd, " 885"); endcase end endtask task ozonerme; input [ 2:0] rme; input [`FD_BITS] fd; // verilator no_inline_task begin case (rme) 3'h0 : $fwrite (fd, " 886"); 3'h1 : $fwrite (fd, " 887"); 3'h2 : $fwrite (fd, " 888"); 3'h3 : $fwrite (fd, " 889"); 3'h4 : $fwrite (fd, " 890"); 3'h5 : $fwrite (fd, " 891"); 3'h6 : $fwrite (fd, " 892"); 3'h7 : $fwrite (fd, " 893"); endcase end endtask task ozoneye; input [5:0] ye; input l; input [`FD_BITS] fd; // verilator no_inline_task begin $fwrite (fd, " 894"); ozonerme(ye[5:3], fd); case ({ye[ 2:0], l}) 4'h2, 4'ha: $fwrite (fd, " 895"); 4'h4, 4'hb: $fwrite (fd, " 896"); 4'h6, 4'he: $fwrite (fd, " 897"); 4'h8, 4'hc: $fwrite (fd, " 898"); endcase end endtask task ozonef1e_ye; input [5:0] ye; input l; input [`FD_BITS] fd; // verilator no_inline_task begin $fwrite (fd, " 899"); ozonerme(ye[5:3], fd); ozonef1e_inc_dec(ye[5:0], l , fd); end endtask task ozonef1e_h; input [ 2:0] e; input [`FD_BITS] fd; // verilator no_inline_task begin if (e[ 2:0] <= 3'h4) $fwrite (fd, " 900"); end endtask task ozonef1e_inc_dec; input [5:0] ye; input l; input [`FD_BITS] fd; // verilator no_inline_task begin case ({ye[ 2:0], l}) 4'h2, 4'h3, 4'ha: $fwrite (fd, " 901"); 4'h4, 4'h5, 4'hb: $fwrite (fd, " 902"); 4'h6, 4'h7, 4'he: $fwrite (fd, " 903"); 4'h8, 4'h9, 4'hc: $fwrite (fd, " 904"); 4'hf: $fwrite (fd, " 905"); endcase end endtask task ozonef1e_hl; input [ 2:0] e; input l; input [`FD_BITS] fd; // verilator no_inline_task begin case ({e[ 2:0], l}) 4'h0, 4'h2, 4'h4, 4'h6, 4'h8: $fwrite (fd, " 906"); 4'h1, 4'h3, 4'h5, 4'h7, 4'h9: $fwrite (fd, " 907"); endcase end endtask task ozonexe; input [ 3:0] xe; input [`FD_BITS] fd; // verilator no_inline_task begin case (xe[3]) 1'b0 : $fwrite (fd, " 908"); 1'b1 : $fwrite (fd, " 909"); endcase case (xe[ 2:0]) 3'h1, 3'h5: $fwrite (fd, " 910"); 3'h2, 3'h6: $fwrite (fd, " 911"); 3'h3, 3'h7: $fwrite (fd, " 912"); 3'h4: $fwrite (fd, " 913"); endcase end endtask task ozonerp; input [ 2:0] rp; input [`FD_BITS] fd; // verilator no_inline_task begin case (rp) 3'h0 : $fwrite (fd, " 914"); 3'h1 : $fwrite (fd, " 915"); 3'h2 : $fwrite (fd, " 916"); 3'h3 : $fwrite (fd, " 917"); 3'h4 : $fwrite (fd, " 918"); 3'h5 : $fwrite (fd, " 919"); 3'h6 : $fwrite (fd, " 920"); 3'h7 : $fwrite (fd, " 921"); endcase end endtask task ozonery; input [ 3:0] ry; input [`FD_BITS] fd; // verilator no_inline_task begin case (ry) 4'h0 : $fwrite (fd, " 922"); 4'h1 : $fwrite (fd, " 923"); 4'h2 : $fwrite (fd, " 924"); 4'h3 : $fwrite (fd, " 925"); 4'h4 : $fwrite (fd, " 926"); 4'h5 : $fwrite (fd, " 927"); 4'h6 : $fwrite (fd, " 928"); 4'h7 : $fwrite (fd, " 929"); 4'h8 : $fwrite (fd, " 930"); 4'h9 : $fwrite (fd, " 931"); 4'ha : $fwrite (fd, " 932"); 4'hb : $fwrite (fd, " 933"); 4'hc : $fwrite (fd, " 934"); 4'hd : $fwrite (fd, " 935"); 4'he : $fwrite (fd, " 936"); 4'hf : $fwrite (fd, " 937"); endcase end endtask task ozonearx; input [ 15:0] foo; input [`FD_BITS] fd; // verilator no_inline_task begin case (foo[1:0]) 2'h0 : $fwrite (fd, " 938"); 2'h1 : $fwrite (fd, " 939"); 2'h2 : $fwrite (fd, " 940"); 2'h3 : $fwrite (fd, " 941"); endcase end endtask task ozonef3f4imop; input [ 4:0] f3f4iml; input [`FD_BITS] fd; // verilator no_inline_task begin casez (f3f4iml) 5'b000??: $fwrite (fd, " 942"); 5'b001??: $fwrite (fd, " 943"); 5'b?10??: $fwrite (fd, " 944"); 5'b0110?: $fwrite (fd, " 945"); 5'b01110: $fwrite (fd, " 946"); 5'b01111: $fwrite (fd, " 947"); 5'b10???: $fwrite (fd, " 948"); 5'b11100: $fwrite (fd, " 949"); 5'b11101: $fwrite (fd, " 950"); 5'b11110: $fwrite (fd, " 951"); 5'b11111: $fwrite (fd, " 952"); endcase end endtask task ozonecon; input [ 4:0] con; input [`FD_BITS] fd; // verilator no_inline_task begin case (con) 5'h00 : $fwrite (fd, " 953"); 5'h01 : $fwrite (fd, " 954"); 5'h02 : $fwrite (fd, " 955"); 5'h03 : $fwrite (fd, " 956"); 5'h04 : $fwrite (fd, " 957"); 5'h05 : $fwrite (fd, " 958"); 5'h06 : $fwrite (fd, " 959"); 5'h07 : $fwrite (fd, " 960"); 5'h08 : $fwrite (fd, " 961"); 5'h09 : $fwrite (fd, " 962"); 5'h0a : $fwrite (fd, " 963"); 5'h0b : $fwrite (fd, " 964"); 5'h0c : $fwrite (fd, " 965"); 5'h0d : $fwrite (fd, " 966"); 5'h0e : $fwrite (fd, " 967"); 5'h0f : $fwrite (fd, " 968"); 5'h10 : $fwrite (fd, " 969"); 5'h11 : $fwrite (fd, " 970"); 5'h12 : $fwrite (fd, " 971"); 5'h13 : $fwrite (fd, " 972"); 5'h14 : $fwrite (fd, " 973"); 5'h15 : $fwrite (fd, " 974"); 5'h16 : $fwrite (fd, " 975"); 5'h17 : $fwrite (fd, " 976"); 5'h18 : $fwrite (fd, " 977"); 5'h19 : $fwrite (fd, " 978"); 5'h1a : $fwrite (fd, " 979"); 5'h1b : $fwrite (fd, " 980"); 5'h1c : $fwrite (fd, " 981"); 5'h1d : $fwrite (fd, " 982"); 5'h1e : $fwrite (fd, " 983"); 5'h1f : $fwrite (fd, " 984"); endcase end endtask task ozonedr; input [ 15:0] foo; input [`FD_BITS] fd; // verilator no_inline_task begin case (foo[ 9: 6]) 4'h0 : $fwrite (fd, " 985"); 4'h1 : $fwrite (fd, " 986"); 4'h2 : $fwrite (fd, " 987"); 4'h3 : $fwrite (fd, " 988"); 4'h4 : $fwrite (fd, " 989"); 4'h5 : $fwrite (fd, " 990"); 4'h6 : $fwrite (fd, " 991"); 4'h7 : $fwrite (fd, " 992"); 4'h8 : $fwrite (fd, " 993"); 4'h9 : $fwrite (fd, " 994"); 4'ha : $fwrite (fd, " 995"); 4'hb : $fwrite (fd, " 996"); 4'hc : $fwrite (fd, " 997"); 4'hd : $fwrite (fd, " 998"); 4'he : $fwrite (fd, " 999"); 4'hf : $fwrite (fd, " 1000"); endcase end endtask task ozoneshift; input [ 15:0] foo; input [`FD_BITS] fd; // verilator no_inline_task begin case (foo[ 4: 3]) 2'h0 : $fwrite (fd, " 1001"); 2'h1 : $fwrite (fd, " 1002"); 2'h2 : $fwrite (fd, " 1003"); 2'h3 : $fwrite (fd, " 1004"); endcase end endtask task ozoneacc; input foo; input [`FD_BITS] fd; // verilator no_inline_task begin case (foo) 2'h0 : $fwrite (fd, " 1005"); 2'h1 : $fwrite (fd, " 1006"); endcase end endtask task ozonehl; input foo; input [`FD_BITS] fd; // verilator no_inline_task begin case (foo) 2'h0 : $fwrite (fd, " 1007"); 2'h1 : $fwrite (fd, " 1008"); endcase end endtask task dude; input [`FD_BITS] fd; // verilator no_inline_task $fwrite(fd," dude"); endtask task automatic big_case; input [ `FD_BITS] fd; input [ 31:0] foo; // verilator no_inline_task begin $fwrite(fd," 1009"); if (&foo === 1'bx) $fwrite(fd, " 1010"); else casez ( {foo[31:26], foo[19:15], foo[5:0]} ) 17'b00_111?_?_????_??_???? : begin ozonef1(foo, fd); $fwrite (fd, " 1011"); ozoneacc(~foo[26], fd); ozonehl(foo[20], fd); $fwrite (fd, " 1012"); ozonerx(foo, fd); dude(fd); $fwrite (fd, " 1013"); end 17'b01_001?_?_????_??_???? : begin ozonef1(foo, fd); $fwrite (fd, " 1014"); ozonerx(foo, fd); $fwrite (fd, " 1015"); $fwrite (fd, " 1016:%x", foo[20]); ozonehl(foo[20], fd); dude(fd); $fwrite (fd, " 1017"); end 17'b10_100?_?_????_??_???? : begin ozonef1(foo, fd); $fwrite (fd, " 1018"); ozonerx(foo, fd); $fwrite (fd, " 1019"); $fwrite (fd, " 1020"); ozonehl(foo[20], fd); dude(fd); $fwrite (fd, " 1021"); end 17'b10_101?_?_????_??_???? : begin ozonef1(foo, fd); $fwrite (fd, " 1022"); if (foo[20]) begin $fwrite (fd, " 1023"); ozoneacc(foo[18], fd); $fwrite (fd, " 1024"); $fwrite (fd, " 1025"); if (foo[19]) $fwrite (fd, " 1026"); else $fwrite (fd, " 1027"); end else ozonerx(foo, fd); dude(fd); $fwrite (fd, " 1028"); end 17'b10_110?_?_????_??_???? : begin ozonef1(foo, fd); $fwrite (fd, " 1029"); $fwrite (fd, " 1030"); ozonehl(foo[20], fd); $fwrite (fd, " 1031"); ozonerx(foo, fd); dude(fd); $fwrite (fd, " 1032"); end 17'b10_111?_?_????_??_???? : begin ozonef1(foo, fd); $fwrite (fd, " 1033"); $fwrite (fd, " 1034"); ozonehl(foo[20], fd); $fwrite (fd, " 1035"); ozonerx(foo, fd); dude(fd); $fwrite (fd, " 1036"); end 17'b11_001?_?_????_??_???? : begin ozonef1(foo, fd); $fwrite (fd, " 1037"); ozonerx(foo, fd); $fwrite (fd, " 1038"); $fwrite (fd, " 1039"); ozonehl(foo[20], fd); dude(fd); $fwrite (fd, " 1040"); end 17'b11_111?_?_????_??_???? : begin ozonef1(foo, fd); $fwrite (fd, " 1041"); $fwrite (fd, " 1042"); ozonerx(foo, fd); $fwrite (fd, " 1043"); if (foo[20]) $fwrite (fd, " 1044"); else $fwrite (fd, " 1045"); dude(fd); $fwrite (fd, " 1046"); end 17'b00_10??_?_????_?1_1111 : casez (foo[11: 5]) 7'b??_0_010_0: begin $fwrite (fd, " 1047"); ozonecon(foo[14:10], fd); $fwrite (fd, " 1048"); ozonef1e(foo, fd); dude(fd); $fwrite (fd, " 1049"); end 7'b00_?_110_?: begin ozonef1e(foo, fd); $fwrite (fd, " 1050"); case ({foo[ 9],foo[ 5]}) 2'b00: begin $fwrite (fd, " 1051"); ozoneae(foo[14:12], fd); ozonehl(foo[ 5], fd); end 2'b01: begin $fwrite (fd, " 1052"); ozoneae(foo[14:12], fd); ozonehl(foo[ 5], fd); end 2'b10: begin $fwrite (fd, " 1053"); ozoneae(foo[14:12], fd); end 2'b11: $fwrite (fd, " 1054"); endcase dude(fd); $fwrite (fd, " 1055"); end 7'b01_?_110_?: begin ozonef1e(foo, fd); $fwrite (fd, " 1056"); case ({foo[ 9],foo[ 5]}) 2'b00: begin ozoneae(foo[14:12], fd); ozonehl(foo[ 5], fd); $fwrite (fd, " 1057"); end 2'b01: begin ozoneae(foo[14:12], fd); ozonehl(foo[ 5], fd); $fwrite (fd, " 1058"); end 2'b10: begin ozoneae(foo[14:12], fd); $fwrite (fd, " 1059"); end 2'b11: $fwrite (fd, " 1060"); endcase dude(fd); $fwrite (fd, " 1061"); end 7'b10_0_110_0: begin ozonef1e(foo, fd); $fwrite (fd, " 1062"); $fwrite (fd, " 1063"); if (foo[12]) $fwrite (fd, " 1064"); else ozonerab({4'b1001, foo[14:12]}, fd); dude(fd); $fwrite (fd, " 1065"); end 7'b10_0_110_1: begin ozonef1e(foo, fd); $fwrite (fd, " 1066"); if (foo[12]) $fwrite (fd, " 1067"); else ozonerab({4'b1001, foo[14:12]}, fd); $fwrite (fd, " 1068"); dude(fd); $fwrite (fd, " 1069"); end 7'b??_?_000_?: begin ozonef1e(foo, fd); $fwrite (fd, " 1070"); $fwrite (fd, " 1071"); ozonef1e_hl(foo[11:9],foo[ 5], fd); $fwrite (fd, " 1072"); ozonef1e_ye(foo[14:9],foo[ 5], fd); dude(fd); $fwrite (fd, " 1073"); end 7'b??_?_100_?: begin ozonef1e(foo, fd); $fwrite (fd, " 1074"); $fwrite (fd, " 1075"); ozonef1e_hl(foo[11:9],foo[ 5], fd); $fwrite (fd, " 1076"); ozonef1e_ye(foo[14:9],foo[ 5], fd); dude(fd); $fwrite (fd, " 1077"); end 7'b??_?_001_?: begin ozonef1e(foo, fd); $fwrite (fd, " 1078"); ozonef1e_ye(foo[14:9],foo[ 5], fd); $fwrite (fd, " 1079"); $fwrite (fd, " 1080"); ozonef1e_hl(foo[11:9],foo[ 5], fd); dude(fd); $fwrite (fd, " 1081"); end 7'b??_?_011_?: begin ozonef1e(foo, fd); $fwrite (fd, " 1082"); ozonef1e_ye(foo[14:9],foo[ 5], fd); $fwrite (fd, " 1083"); $fwrite (fd, " 1084"); ozonef1e_hl(foo[11:9],foo[ 5], fd); dude(fd); $fwrite (fd, " 1085"); end 7'b??_?_101_?: begin ozonef1e(foo, fd); $fwrite (fd, " 1086"); ozonef1e_ye(foo[14:9],foo[ 5], fd); dude(fd); $fwrite (fd, " 1087"); end endcase 17'b00_10??_?_????_?0_0110 : begin ozonef1e(foo, fd); $fwrite (fd, " 1088"); ozoneae(foo[ 8: 6], fd); ozonef1e_hl(foo[11:9],foo[ 5], fd); $fwrite (fd, " 1089"); ozonef1e_ye(foo[14:9],foo[ 5], fd); dude(fd); $fwrite (fd, " 1090"); end 17'b00_10??_?_????_00_0111 : begin ozonef1e(foo, fd); $fwrite (fd, " 1091"); if (foo[ 6]) $fwrite (fd, " 1092"); else ozonerab({4'b1001, foo[ 8: 6]}, fd); $fwrite (fd, " 1093"); $fwrite (fd, " 1094"); ozonerme(foo[14:12], fd); case (foo[11: 9]) 3'h2, 3'h5, 3'h6, 3'h7: ozonef1e_inc_dec(foo[14:9],1'b0, fd); 3'h1, 3'h3, 3'h4: $fwrite (fd, " 1095"); endcase dude(fd); $fwrite (fd, " 1096"); end 17'b00_10??_?_????_?0_0100 : begin ozonef1e(foo, fd); $fwrite (fd, " 1097"); ozonef1e_ye(foo[14:9],foo[ 5], fd); $fwrite (fd, " 1098"); ozoneae(foo[ 8: 6], fd); ozonef1e_hl(foo[11:9],foo[ 5], fd); dude(fd); $fwrite (fd, " 1099"); end 17'b00_10??_?_????_10_0111 : begin ozonef1e(foo, fd); $fwrite (fd, " 1100"); $fwrite (fd, " 1101"); ozonerme(foo[14:12], fd); case (foo[11: 9]) 3'h2, 3'h5, 3'h6, 3'h7: ozonef1e_inc_dec(foo[14:9],1'b0, fd); 3'h1, 3'h3, 3'h4: $fwrite (fd, " 1102"); endcase $fwrite (fd, " 1103"); if (foo[ 6]) $fwrite (fd, " 1104"); else ozonerab({4'b1001, foo[ 8: 6]}, fd); dude(fd); $fwrite (fd, " 1105"); end 17'b00_10??_?_????_?0_1110 : begin ozonef1e(foo, fd); $fwrite (fd, " 1106"); case (foo[11:9]) 3'h2: begin $fwrite (fd, " 1107"); if (foo[14:12] == 3'h0) $fwrite (fd, " 1108"); else ozonerme(foo[14:12], fd); $fwrite (fd, " 1109"); end 3'h6: begin $fwrite (fd, " 1110"); if (foo[14:12] == 3'h0) $fwrite (fd, " 1111"); else ozonerme(foo[14:12], fd); $fwrite (fd, " 1112"); end 3'h0: begin $fwrite (fd, " 1113"); if (foo[14:12] == 3'h0) $fwrite (fd, " 1114"); else ozonerme(foo[14:12], fd); $fwrite (fd, " 1115"); if (foo[ 7: 5] >= 3'h5) $fwrite (fd, " 1116"); else ozonexe(foo[ 8: 5], fd); end 3'h1: begin $fwrite (fd, " 1117"); if (foo[14:12] == 3'h0) $fwrite (fd, " 1118"); else ozonerme(foo[14:12], fd); $fwrite (fd, " 1119"); if (foo[ 7: 5] >= 3'h5) $fwrite (fd, " 1120"); else ozonexe(foo[ 8: 5], fd); end 3'h4: begin $fwrite (fd, " 1121"); if (foo[14:12] == 3'h0) $fwrite (fd, " 1122"); else ozonerme(foo[14:12], fd); $fwrite (fd, " 1123"); if (foo[ 7: 5] >= 3'h5) $fwrite (fd, " 1124"); else ozonexe(foo[ 8: 5], fd); end 3'h5: begin $fwrite (fd, " 1125"); if (foo[14:12] == 3'h0) $fwrite (fd, " 1126"); else ozonerme(foo[14:12], fd); $fwrite (fd, " 1127"); if (foo[ 7: 5] >= 3'h5) $fwrite (fd, " 1128"); else ozonexe(foo[ 8: 5], fd); end endcase dude(fd); $fwrite (fd, " 1129"); end 17'b00_10??_?_????_?0_1111 : casez (foo[14: 9]) 6'b001_10_?: begin ozonef1e(foo, fd); $fwrite (fd, " 1130"); $fwrite (fd, " 1131"); ozonef1e_hl(foo[ 7: 5],foo[ 9], fd); $fwrite (fd, " 1132"); ozonexe(foo[ 8: 5], fd); dude(fd); $fwrite (fd, " 1133"); end 6'b???_11_?: begin ozonef1e(foo, fd); $fwrite (fd, " 1134"); ozoneae(foo[14:12], fd); ozonef1e_hl(foo[ 7: 5],foo[ 9], fd); $fwrite (fd, " 1135"); ozonexe(foo[ 8: 5], fd); dude(fd); $fwrite (fd, " 1136"); end 6'b000_10_1, 6'b010_10_1, 6'b100_10_1, 6'b110_10_1: begin ozonef1e(foo, fd); $fwrite (fd, " 1137"); ozonerab({4'b1001, foo[14:12]}, fd); $fwrite (fd, " 1138"); if ((foo[ 7: 5] >= 3'h1) & (foo[ 7: 5] <= 3'h3)) $fwrite (fd, " 1139"); else ozonexe(foo[ 8: 5], fd); dude(fd); $fwrite (fd, " 1140"); end 6'b000_10_0, 6'b010_10_0, 6'b100_10_0, 6'b110_10_0: begin ozonef1e(foo, fd); $fwrite (fd, " 1141"); $fwrite (fd, " 1142"); ozonerab({4'b1001, foo[14:12]}, fd); $fwrite (fd, " 1143"); $fwrite (fd, " 1144"); ozonef1e_h(foo[ 7: 5], fd); $fwrite (fd, " 1145"); ozonexe(foo[ 8: 5], fd); dude(fd); $fwrite (fd, " 1146"); end 6'b???_00_?: begin ozonef1e(foo, fd); $fwrite (fd, " 1147"); if (foo[ 9]) begin $fwrite (fd, " 1148"); ozoneae(foo[14:12], fd); end else begin $fwrite (fd, " 1149"); ozoneae(foo[14:12], fd); $fwrite (fd, " 1150"); end $fwrite (fd, " 1151"); $fwrite (fd, " 1152"); ozonef1e_h(foo[ 7: 5], fd); $fwrite (fd, " 1153"); ozonexe(foo[ 8: 5], fd); dude(fd); $fwrite (fd, " 1154"); end 6'b???_01_?: begin ozonef1e(foo, fd); $fwrite (fd, " 1155"); ozoneae(foo[14:12], fd); if (foo[ 9]) $fwrite (fd, " 1156"); else $fwrite (fd, " 1157"); $fwrite (fd, " 1158"); $fwrite (fd, " 1159"); ozonef1e_h(foo[ 7: 5], fd); $fwrite (fd, " 1160"); ozonexe(foo[ 8: 5], fd); dude(fd); $fwrite (fd, " 1161"); end 6'b011_10_0: begin ozonef1e(foo, fd); $fwrite (fd, " 1162"); case (foo[ 8: 5]) 4'h0: $fwrite (fd, " 1163"); 4'h1: $fwrite (fd, " 1164"); 4'h2: $fwrite (fd, " 1165"); 4'h3: $fwrite (fd, " 1166"); 4'h4: $fwrite (fd, " 1167"); 4'h5: $fwrite (fd, " 1168"); 4'h8: $fwrite (fd, " 1169"); 4'h9: $fwrite (fd, " 1170"); 4'ha: $fwrite (fd, " 1171"); 4'hb: $fwrite (fd, " 1172"); 4'hc: $fwrite (fd, " 1173"); 4'hd: $fwrite (fd, " 1174"); default: $fwrite (fd, " 1175"); endcase dude(fd); $fwrite (fd, " 1176"); end default: $fwrite (fd, " 1177"); endcase 17'b00_10??_?_????_?0_110? : begin ozonef1e(foo, fd); $fwrite (fd, " 1178"); $fwrite (fd, " 1179"); ozonef1e_hl(foo[11:9], foo[0], fd); $fwrite (fd, " 1180"); ozonef1e_ye(foo[14:9],1'b0, fd); $fwrite (fd, " 1181"); ozonef1e_h(foo[ 7: 5], fd); $fwrite (fd, " 1182"); ozonexe(foo[ 8: 5], fd); dude(fd); $fwrite (fd, " 1183"); end 17'b00_10??_?_????_?1_110? : begin ozonef1e(foo, fd); $fwrite (fd, " 1184"); $fwrite (fd, " 1185"); ozonef1e_hl(foo[11:9],foo[0], fd); $fwrite (fd, " 1186"); ozonef1e_ye(foo[14:9],foo[ 0], fd); $fwrite (fd, " 1187"); $fwrite (fd, " 1188"); ozonef1e_h(foo[ 7: 5], fd); $fwrite (fd, " 1189"); ozonexe(foo[ 8: 5], fd); dude(fd); $fwrite (fd, " 1190"); end 17'b00_10??_?_????_?0_101? : begin ozonef1e(foo, fd); $fwrite (fd, " 1191"); ozonef1e_ye(foo[14:9],foo[ 0], fd); $fwrite (fd, " 1192"); $fwrite (fd, " 1193"); ozonef1e_hl(foo[11:9],foo[0], fd); $fwrite (fd, " 1194"); $fwrite (fd, " 1195"); ozonef1e_h(foo[ 7: 5], fd); $fwrite (fd, " 1196"); ozonexe(foo[ 8: 5], fd); dude(fd); $fwrite (fd, " 1197"); end 17'b00_10??_?_????_?0_1001 : begin ozonef1e(foo, fd); $fwrite (fd, " 1198"); $fwrite (fd, " 1199"); ozonef1e_h(foo[11:9], fd); $fwrite (fd, " 1200"); ozonef1e_ye(foo[14:9],1'b0, fd); $fwrite (fd, " 1201"); case (foo[ 7: 5]) 3'h1, 3'h2, 3'h3: $fwrite (fd, " 1202"); default: begin $fwrite (fd, " 1203"); $fwrite (fd, " 1204"); ozonexe(foo[ 8: 5], fd); end endcase dude(fd); $fwrite (fd, " 1205"); end 17'b00_10??_?_????_?0_0101 : begin ozonef1e(foo, fd); $fwrite (fd, " 1206"); case (foo[11: 9]) 3'h1, 3'h3, 3'h4: $fwrite (fd, " 1207"); default: begin ozonef1e_ye(foo[14:9],1'b0, fd); $fwrite (fd, " 1208"); $fwrite (fd, " 1209"); end endcase $fwrite (fd, " 1210"); $fwrite (fd, " 1211"); ozonef1e_h(foo[ 7: 5], fd); $fwrite (fd, " 1212"); ozonexe(foo[ 8: 5], fd); dude(fd); $fwrite (fd, " 1213"); end 17'b00_10??_?_????_?1_1110 : begin ozonef1e(foo, fd); $fwrite (fd, " 1214"); ozonef1e_ye(foo[14:9],1'b0, fd); $fwrite (fd, " 1215"); $fwrite (fd, " 1216"); ozonef1e_h(foo[11: 9], fd); $fwrite (fd, " 1217"); $fwrite (fd, " 1218"); ozonef1e_h(foo[ 7: 5], fd); $fwrite (fd, " 1219"); ozonexe(foo[ 8: 5], fd); dude(fd); $fwrite (fd, " 1220"); end 17'b00_10??_?_????_?0_1000 : begin ozonef1e(foo, fd); $fwrite (fd, " 1221"); ozonef1e_ye(foo[14:9],1'b0, fd); $fwrite (fd, " 1222"); $fwrite (fd, " 1223"); ozonef1e_h(foo[11: 9], fd); $fwrite (fd, " 1224"); $fwrite (fd, " 1225"); ozonef1e_h(foo[ 7: 5], fd); $fwrite (fd, " 1226"); ozonexe(foo[ 8: 5], fd); dude(fd); $fwrite (fd, " 1227"); end 17'b10_01??_?_????_??_???? : begin if (foo[27]) $fwrite (fd," 1228"); else $fwrite (fd," 1229"); ozonecon(foo[20:16], fd); $fwrite (fd, " 1230"); ozonef2(foo[31:0], fd); dude(fd); $fwrite (fd, " 1231"); end 17'b00_1000_?_????_01_0011 : if (~|foo[ 9: 8]) begin if (foo[ 7]) $fwrite (fd," 1232"); else $fwrite (fd," 1233"); ozonecon(foo[14:10], fd); $fwrite (fd, " 1234"); ozonef2e(foo[31:0], fd); dude(fd); $fwrite (fd, " 1235"); end else begin $fwrite (fd, " 1236"); ozonecon(foo[14:10], fd); $fwrite (fd, " 1237"); ozonef3e(foo[31:0], fd); dude(fd); $fwrite (fd, " 1238"); end 17'b11_110?_1_????_??_???? : begin ozonef3(foo[31:0], fd); dude(fd); $fwrite(fd, " 1239"); end 17'b11_110?_0_????_??_???? : begin : f4_body casez (foo[24:20]) 5'b0_1110, 5'b1_0???, 5'b1_1111: begin $fwrite (fd, " 1240"); end 5'b0_00??: begin ozoneacc(foo[26], fd); $fwrite (fd, " 1241"); ozoneacc(foo[25], fd); ozonebmuop(foo[24:20], fd); ozoneae(foo[18:16], fd); $fwrite (fd, " 1242"); dude(fd); $fwrite(fd, " 1243"); end 5'b0_01??: begin ozoneacc(foo[26], fd); $fwrite (fd, " 1244"); ozoneacc(foo[25], fd); ozonebmuop(foo[24:20], fd); ozonearm(foo[18:16], fd); dude(fd); $fwrite(fd, " 1245"); end 5'b0_1011: begin ozoneacc(foo[26], fd); $fwrite (fd, " 1246"); ozonebmuop(foo[24:20], fd); $fwrite (fd, " 1247"); ozoneae(foo[18:16], fd); $fwrite (fd, " 1248"); dude(fd); $fwrite(fd, " 1249"); end 5'b0_100?, 5'b0_1010, 5'b0_110? : begin ozoneacc(foo[26], fd); $fwrite (fd, " 1250"); ozonebmuop(foo[24:20], fd); $fwrite (fd, " 1251"); ozoneacc(foo[25], fd); $fwrite (fd, " 1252"); ozoneae(foo[18:16], fd); $fwrite (fd, " 1253"); dude(fd); $fwrite(fd, " 1254"); end 5'b0_1111 : begin ozoneacc(foo[26], fd); $fwrite (fd, " 1255"); ozoneacc(foo[25], fd); $fwrite (fd, " 1256"); ozoneae(foo[18:16], fd); dude(fd); $fwrite(fd, " 1257"); end 5'b1_10??, 5'b1_110?, 5'b1_1110 : begin ozoneacc(foo[26], fd); $fwrite (fd, " 1258"); ozonebmuop(foo[24:20], fd); $fwrite (fd, " 1259"); ozoneacc(foo[25], fd); $fwrite (fd, " 1260"); ozonearm(foo[18:16], fd); $fwrite (fd, " 1261"); dude(fd); $fwrite(fd, " 1262"); end endcase end 17'b11_100?_?_????_??_???? : casez (foo[23:19]) 5'b111??, 5'b0111?: begin ozoneae(foo[26:24], fd); $fwrite (fd, " 1263"); ozonef3f4imop(foo[23:19], fd); $fwrite (fd, " 1264"); ozoneae(foo[18:16], fd); $fwrite (fd, " 1265"); skyway(foo[15:12], fd); skyway(foo[11: 8], fd); skyway(foo[ 7: 4], fd); skyway(foo[ 3:0], fd); $fwrite (fd, " 1266"); dude(fd); $fwrite(fd, " 1267"); end 5'b?0???, 5'b110??: begin ozoneae(foo[26:24], fd); $fwrite (fd, " 1268"); if (foo[23:21] == 3'b100) $fwrite (fd, " 1269"); ozoneae(foo[18:16], fd); if (foo[19]) $fwrite (fd, " 1270"); else $fwrite (fd, " 1271"); ozonef3f4imop(foo[23:19], fd); $fwrite (fd, " 1272"); ozonef3f4_iext(foo[20:19], foo[15:0], fd); dude(fd); $fwrite(fd, " 1273"); end 5'b010??, 5'b0110?: begin ozoneae(foo[18:16], fd); if (foo[19]) $fwrite (fd, " 1274"); else $fwrite (fd, " 1275"); ozonef3f4imop(foo[23:19], fd); $fwrite (fd, " 1276"); ozonef3f4_iext(foo[20:19], foo[15:0], fd); dude(fd); $fwrite(fd, " 1277"); end endcase 17'b00_1000_?_????_11_0011 : begin $fwrite (fd," 1278"); ozonecon(foo[14:10], fd); $fwrite (fd, " 1279"); casez (foo[25:21]) 5'b0_1110, 5'b1_0???, 5'b1_1111: begin $fwrite(fd, " 1280"); end 5'b0_00??: begin ozoneae(foo[20:18], fd); $fwrite (fd, " 1281"); ozoneae(foo[17:15], fd); ozonebmuop(foo[25:21], fd); ozoneae(foo[ 8: 6], fd); $fwrite (fd, " 1282"); dude(fd); $fwrite(fd, " 1283"); end 5'b0_01??: begin ozoneae(foo[20:18], fd); $fwrite (fd, " 1284"); ozoneae(foo[17:15], fd); ozonebmuop(foo[25:21], fd); ozonearm(foo[ 8: 6], fd); dude(fd); $fwrite(fd, " 1285"); end 5'b0_1011: begin ozoneae(foo[20:18], fd); $fwrite (fd, " 1286"); ozonebmuop(foo[25:21], fd); $fwrite (fd, " 1287"); ozoneae(foo[ 8: 6], fd); $fwrite (fd, " 1288"); dude(fd); $fwrite(fd, " 1289"); end 5'b0_100?, 5'b0_1010, 5'b0_110? : begin ozoneae(foo[20:18], fd); $fwrite (fd, " 1290"); ozonebmuop(foo[25:21], fd); $fwrite (fd, " 1291"); ozoneae(foo[17:15], fd); $fwrite (fd, " 1292"); ozoneae(foo[ 8: 6], fd); $fwrite (fd, " 1293"); dude(fd); $fwrite(fd, " 1294"); end 5'b0_1111 : begin ozoneae(foo[20:18], fd); $fwrite (fd, " 1295"); ozoneae(foo[17:15], fd); $fwrite (fd, " 1296"); ozoneae(foo[ 8: 6], fd); dude(fd); $fwrite(fd, " 1297"); end 5'b1_10??, 5'b1_110?, 5'b1_1110 : begin ozoneae(foo[20:18], fd); $fwrite (fd, " 1298"); ozonebmuop(foo[25:21], fd); $fwrite (fd, " 1299"); ozoneae(foo[17:15], fd); $fwrite (fd, " 1300"); ozonearm(foo[ 8: 6], fd); $fwrite (fd, " 1301"); dude(fd); $fwrite(fd, " 1302"); end endcase end 17'b00_0010_?_????_??_???? : begin ozonerab({1'b0, foo[25:20]}, fd); $fwrite (fd, " 1303"); skyway(foo[19:16], fd); dude(fd); $fwrite(fd, " 1304"); end 17'b00_01??_?_????_??_???? : begin if (foo[27]) begin $fwrite (fd, " 1305"); if (foo[26]) $fwrite (fd, " 1306"); else $fwrite (fd, " 1307"); skyway(foo[19:16], fd); $fwrite (fd, " 1308"); ozonerab({1'b0, foo[25:20]}, fd); end else begin ozonerab({1'b0, foo[25:20]}, fd); $fwrite (fd, " 1309"); if (foo[26]) $fwrite (fd, " 1310"); else $fwrite (fd, " 1311"); skyway(foo[19:16], fd); $fwrite (fd, " 1312"); end dude(fd); $fwrite(fd, " 1313"); end 17'b01_000?_?_????_??_???? : begin if (foo[26]) begin ozonerb(foo[25:20], fd); $fwrite (fd, " 1314"); ozoneae(foo[18:16], fd); ozonehl(foo[19], fd); end else begin ozoneae(foo[18:16], fd); ozonehl(foo[19], fd); $fwrite (fd, " 1315"); ozonerb(foo[25:20], fd); end dude(fd); $fwrite(fd, " 1316"); end 17'b01_10??_?_????_??_???? : begin if (foo[27]) begin ozonerab({1'b0, foo[25:20]}, fd); $fwrite (fd, " 1317"); ozonerx(foo, fd); end else begin ozonerx(foo, fd); $fwrite (fd, " 1318"); ozonerab({1'b0, foo[25:20]}, fd); end dude(fd); $fwrite(fd, " 1319"); end 17'b11_101?_?_????_??_???? : begin ozonerab (foo[26:20], fd); $fwrite (fd, " 1320"); skyway(foo[19:16], fd); skyway(foo[15:12], fd); skyway(foo[11: 8], fd); skyway(foo[ 7: 4], fd); skyway(foo[ 3: 0], fd); dude(fd); $fwrite(fd, " 1321"); end 17'b11_0000_?_????_??_???? : begin casez (foo[25:23]) 3'b00?: begin ozonerab(foo[22:16], fd); $fwrite (fd, " 1322"); end 3'b01?: begin $fwrite (fd, " 1323"); if (foo[22:16]>=7'h60) $fwrite (fd, " 1324"); else ozonerab(foo[22:16], fd); end 3'b110: $fwrite (fd, " 1325"); 3'b10?: begin $fwrite (fd, " 1326"); if (foo[22:16]>=7'h60) $fwrite (fd, " 1327"); else ozonerab(foo[22:16], fd); end 3'b111: begin $fwrite (fd, " 1328"); ozonerab(foo[22:16], fd); $fwrite (fd, " 1329"); end endcase dude(fd); $fwrite(fd, " 1330"); end 17'b00_10??_?_????_?1_0000 : begin if (foo[27]) begin $fwrite (fd, " 1331"); ozonerp(foo[14:12], fd); $fwrite (fd, " 1332"); skyway(foo[19:16], fd); skyway({foo[15],foo[11: 9]}, fd); skyway(foo[ 8: 5], fd); $fwrite (fd, " 1333"); if (foo[26:20]>=7'h60) $fwrite (fd, " 1334"); else ozonerab(foo[26:20], fd); end else begin ozonerab(foo[26:20], fd); $fwrite (fd, " 1335"); $fwrite (fd, " 1336"); ozonerp(foo[14:12], fd); $fwrite (fd, " 1337"); skyway(foo[19:16], fd); skyway({foo[15],foo[11: 9]}, fd); skyway(foo[ 8: 5], fd); $fwrite (fd, " 1338"); end dude(fd); $fwrite(fd, " 1339"); end 17'b00_101?_1_0000_?1_0010 : if (~|foo[11: 7]) begin if (foo[ 6]) begin $fwrite (fd, " 1340"); ozonerp(foo[14:12], fd); $fwrite (fd, " 1341"); ozonejk(foo[ 5], fd); $fwrite (fd, " 1342"); if (foo[26:20]>=7'h60) $fwrite (fd, " 1343"); else ozonerab(foo[26:20], fd); end else begin ozonerab(foo[26:20], fd); $fwrite (fd, " 1344"); $fwrite (fd, " 1345"); ozonerp(foo[14:12], fd); $fwrite (fd, " 1346"); ozonejk(foo[ 5], fd); $fwrite (fd, " 1347"); end dude(fd); $fwrite(fd, " 1348"); end else $fwrite(fd, " 1349"); 17'b00_100?_0_0011_?1_0101 : if (~|foo[ 8: 7]) begin if (foo[6]) begin ozonerab(foo[26:20], fd); $fwrite (fd, " 1350"); ozoneye(foo[14: 9],foo[ 5], fd); end else begin ozoneye(foo[14: 9],foo[ 5], fd); $fwrite (fd, " 1351"); if (foo[26:20]>=7'h60) $fwrite (fd, " 1352"); else ozonerab(foo[26:20], fd); end dude(fd); $fwrite(fd, " 1353"); end else $fwrite(fd, " 1354"); 17'b00_1001_0_0000_?1_0010 : if (~|foo[25:20]) begin ozoneye(foo[14: 9],1'b0, fd); $fwrite (fd, " 1355"); ozonef1e_h(foo[11: 9], fd); $fwrite (fd, " 1356"); ozonef1e_h(foo[ 7: 5], fd); $fwrite (fd, " 1357"); ozonexe(foo[ 8: 5], fd); dude(fd); $fwrite(fd, " 1358"); end else $fwrite(fd, " 1359"); 17'b00_101?_0_????_?1_0010 : if (~foo[13]) begin if (foo[12]) begin $fwrite (fd, " 1360"); if (foo[26:20]>=7'h60) $fwrite (fd, " 1361"); else ozonerab(foo[26:20], fd); $fwrite (fd, " 1362"); $fwrite (fd, " 1363"); skyway({1'b0,foo[18:16]}, fd); skyway({foo[15],foo[11: 9]}, fd); skyway(foo[ 8: 5], fd); dude(fd); $fwrite(fd, " 1364"); end else begin ozonerab(foo[26:20], fd); $fwrite (fd, " 1365"); $fwrite (fd, " 1366"); skyway({1'b0,foo[18:16]}, fd); skyway({foo[15],foo[11: 9]}, fd); skyway(foo[ 8: 5], fd); dude(fd); $fwrite(fd, " 1367"); end end else $fwrite(fd, " 1368"); 17'b01_01??_?_????_??_???? : begin ozonerab({1'b0,foo[27:26],foo[19:16]}, fd); $fwrite (fd, " 1369"); ozonerab({1'b0,foo[25:20]}, fd); dude(fd); $fwrite(fd, " 1370"); end 17'b00_100?_?_???0_11_0101 : if (~foo[6]) begin $fwrite (fd," 1371"); ozonecon(foo[14:10], fd); $fwrite (fd, " 1372"); ozonerab({foo[ 9: 7],foo[19:16]}, fd); $fwrite (fd, " 1373"); ozonerab({foo[26:20]}, fd); dude(fd); $fwrite(fd, " 1374"); end else $fwrite(fd, " 1375"); 17'b00_1000_?_????_?1_0010 : if (~|foo[25:24]) begin ozonery(foo[23:20], fd); $fwrite (fd, " 1376"); ozonerp(foo[14:12], fd); $fwrite (fd, " 1377"); skyway(foo[19:16], fd); skyway({foo[15],foo[11: 9]}, fd); skyway(foo[ 8: 5], fd); dude(fd); $fwrite(fd, " 1378"); end else if ((foo[25:24] == 2'b10) & ~|foo[19:15] & ~|foo[11: 6]) begin ozonery(foo[23:20], fd); $fwrite (fd, " 1379"); ozonerp(foo[14:12], fd); $fwrite (fd, " 1380"); ozonejk(foo[ 5], fd); dude(fd); $fwrite(fd, " 1381"); end else $fwrite(fd, " 1382"); 17'b11_01??_?_????_??_????, 17'b10_00??_?_????_??_???? : if (foo[30]) $fwrite(fd, " 1383:%x", foo[27:16]); else $fwrite(fd, " 1384:%x", foo[27:16]); 17'b00_10??_?_????_01_1000 : if (~foo[6]) begin if (foo[7]) $fwrite(fd, " 1385:%x", foo[27: 8]); else $fwrite(fd, " 1386:%x", foo[27: 8]); end else $fwrite(fd, " 1387"); 17'b00_10??_?_????_11_1000 : begin $fwrite (fd," 1388"); ozonecon(foo[14:10], fd); $fwrite (fd, " 1389"); if (foo[15]) $fwrite (fd, " 1390"); else $fwrite (fd, " 1391"); skyway(foo[27:24], fd); skyway(foo[23:20], fd); skyway(foo[19:16], fd); skyway(foo[ 9: 6], fd); dude(fd); $fwrite(fd, " 1392"); end 17'b11_0001_?_????_??_???? : casez (foo[25:22]) 4'b01?? : begin $fwrite (fd," 1393"); ozonecon(foo[20:16], fd); case (foo[23:21]) 3'h0 : $fwrite (fd, " 1394"); 3'h1 : $fwrite (fd, " 1395"); 3'h2 : $fwrite (fd, " 1396"); 3'h3 : $fwrite (fd, " 1397"); 3'h4 : $fwrite (fd, " 1398"); 3'h5 : $fwrite (fd, " 1399"); 3'h6 : $fwrite (fd, " 1400"); 3'h7 : $fwrite (fd, " 1401"); endcase dude(fd); $fwrite(fd, " 1402"); end 4'b0000 : $fwrite(fd, " 1403:%x", foo[21:16]); 4'b0010 : if (~|foo[21:16]) $fwrite(fd, " 1404"); 4'b1010 : if (~|foo[21:17]) begin if (foo[16]) $fwrite(fd, " 1405"); else $fwrite(fd, " 1406"); end default : $fwrite(fd, " 1407"); endcase 17'b01_11??_?_????_??_???? : if (foo[27:23] === 5'h00) $fwrite(fd, " 1408:%x", foo[22:16]); else $fwrite(fd, " 1409:%x", foo[22:16]); default: $fwrite(fd, " 1410"); endcase end endtask //(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\",\",\\4,\");\");" nil nil nil) //(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\");\");" nil nil nil) endmodule verilator-5.042/test_regress/t/t_tri_unconn.py0000755000542200017500000000073415101701376022150 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_colon_bad.out0000644000542200017500000000041415101701376024101 0ustar mahmoudyfreeshell%Error: t/t_interface_colon_bad.v:14:7: Package/class for ':: reference' not found: 'iface' 14 | iface::func(); | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_trace_public.v0000644000542200017500000000275015101701376022240 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( input wire CLK, output reg RESET ); neg neg (.clk(CLK)); little little (.clk(CLK)); glbl glbl (); // A vector logic [2:1] vec [4:3]; integer val = 0; always @ (posedge CLK) begin if (RESET) val <= 0; else val <= val + 1; vec[3] <= val[1:0]; vec[4] <= val[3:2]; end initial RESET = 1'b1; always @ (posedge CLK) RESET <= glbl.GSR; endmodule module glbl(); `ifdef PUB_FUNC reg GSR; task setGSR; `ifdef ATTRIBUTES /* verilator public */ `endif input value; GSR = value; endtask `else `ifdef ATTRIBUTES reg GSR /*verilator public*/; `else reg GSR; `endif `endif endmodule module neg ( input clk ); reg [0:-7] i8; initial i8 = '0; reg [-1:-48] i48; initial i48 = '0; reg [63:-64] i128; initial i128 = '0; always @ (posedge clk) begin i8 <= ~i8; i48 <= ~i48; i128 <= ~i128; end endmodule module little ( input clk ); // verilator lint_off ASCRANGE reg [0:7] i8; initial i8 = '0; reg [1:49] i48; initial i48 = '0; reg [63:190] i128; initial i128 = '0; // verilator lint_on ASCRANGE always @ (posedge clk) begin i8 <= ~i8; i48 <= ~i48; i128 <= ~i128; end endmodule verilator-5.042/test_regress/t/t_verilated_all.v0000644000542200017500000000202315101701376022404 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Rnd; rand bit x; endclass module t (/*AUTOARG*/ // Inputs clk ); Rnd c; input clk; int cyc; integer rand_result; integer seed = 123; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc != 0) begin if (cyc == 10) begin #5; $display("dist: %f ", $dist_poisson(seed, 12)); // Get verilated_probdist.cpp c = new; rand_result = c.randomize(); $display("rand: %x x: %x ", rand_result, c.x); // Get verilated_random.cpp $write("*-* All Finished *-*\n"); $finish; end end end cyc_eq_5: cover property (@(posedge clk) cyc==5) $display("*COVER: Cyc==5"); export "DPI-C" function dpix_f_int; function int dpix_f_int (); return cyc; endfunction endmodule verilator-5.042/test_regress/t/t_dpi_export_c.cpp0000644000542200017500000001615615101701376022605 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "svdpi.h" #include #include #include #include //====================================================================== #if defined(VERILATOR) #ifdef T_DPI_EXPORT_NOOPT #include "Vt_dpi_export_noopt__Dpi.h" #else #include "Vt_dpi_export__Dpi.h" #endif #elif defined(VCS) #include "../vc_hdrs.h" #elif defined(CADENCE) #define NEED_EXTERNS #else #error "Unknown simulator for DPI test" #endif // clang-format on #ifdef NEED_EXTERNS extern "C" { extern int dpix_run_tests(); extern int dpix_t_int(int i, int* o); extern int dpix_t_renamed(int i, int* o); extern int dpix_int123(); extern unsigned char dpix_f_bit(unsigned char i); extern svBitVecVal dpix_f_bit15(const svBitVecVal* i); extern svBitVecVal dpix_f_bit48(const svBitVecVal* i); extern int dpix_f_int(int i); extern char dpix_f_byte(char i); extern short int dpix_f_shortint(short int i); extern long long dpix_f_longint(long long i); extern void* dpix_f_chandle(void* i); extern int dpix_sub_inst(int i); extern void dpix_t_reg(svLogic i, svLogic* o); extern void dpix_t_reg15(const svLogicVecVal* i, svLogicVecVal* o); extern void dpix_t_reg95(const svLogicVecVal* i, svLogicVecVal* o); extern void dpix_t_integer(const svLogicVecVal* i, svLogicVecVal* o); extern void dpix_t_time(const svLogicVecVal* i, svLogicVecVal* o); extern int dpix__under___score(int i); } #endif //====================================================================== // clang-format off #define CHECK_RESULT(type, got, exp) \ if ((got) != (exp)) { \ printf("%%Error: %s:%d:", __FILE__, __LINE__); \ union { type a; uint64_t l; } u; \ u.l = 0; u.a = got; if (u.a) {/*used*/} \ printf(" GOT = %" PRIx64, u.l); \ u.l = 0; u.a = exp; if (u.a) {/*used*/} \ printf(" EXP = %" PRIx64 "\n", u.l); \ return __LINE__; \ } // clang-format on #define CHECK_RESULT_NNULL(got) \ if (!(got)) { \ printf("%%Error: %s:%d: GOT = %p EXP = !NULL\n", __FILE__, __LINE__, (got)); \ return __LINE__; \ } static int check_sub(const char* name, int i) { svScope scope = svGetScopeFromName(name); #ifdef TEST_VERBOSE printf("svGetScopeFromName(\"%s\") -> %p\n", name, scope); #endif CHECK_RESULT_NNULL(scope); svScope prev = svGetScope(); svScope sout = svSetScope(scope); CHECK_RESULT(svScope, sout, prev); CHECK_RESULT(svScope, svGetScope(), scope); #ifndef T_DPI_EXPORT_NOOPT int out = dpix_sub_inst(100 * i); CHECK_RESULT(int, out, 100 * i + i); #endif return 0; // OK } // Called from our Verilog code to run the tests int dpix_run_tests() { printf("dpix_run_tests:\n"); #ifdef VERILATOR static int didDump = 0; if (didDump++ == 0) { #ifdef TEST_VERBOSE Verilated::internalsDump(); #endif } #endif #ifndef CADENCE // Unimplemented; how hard is it? printf("svDpiVersion: %s\n", svDpiVersion()); CHECK_RESULT(bool, std::strcmp(svDpiVersion(), "1800-2005") == 0 || std::strcmp(svDpiVersion(), "P1800-2005") == 0, 1); #endif CHECK_RESULT(int, dpix_int123(), 0x123); #ifndef CADENCE // No export calls from an import int o; dpix_t_int(0x456, &o); CHECK_RESULT(unsigned long, o, ~0x456UL); dpix_t_renamed(0x456, &o); CHECK_RESULT(int, o, 0x458UL); #endif svBitVecVal vec10[1] = {0x10}; CHECK_RESULT(int, dpix_f_bit(1), 0x0); CHECK_RESULT(int, dpix_f_bit(0), 0x1); CHECK_RESULT(int, dpix_f_bit15(vec10) & 0x7fUL, 0x6f); // Simulators disagree over the next three's sign extension unless we mask the upper bits CHECK_RESULT(int, dpix_f_int(1) & 0xffffffffUL, 0xfffffffeUL); CHECK_RESULT(int, dpix_f_byte(1) & 0xffUL, 0xfe); CHECK_RESULT(int, dpix_f_shortint(1) & 0xffffUL, 0xfffeUL); CHECK_RESULT(unsigned long long, dpix_f_longint(1), 0xfffffffffffffffeULL); CHECK_RESULT(void*, dpix_f_chandle((void*)(12345)), (void*)(12345)); { svBitVecVal i_vec48[2] = {0xab782a12, 0x8a413bd9}; svBitVecVal o_vec48[2] = {0, 0}; dpix_t_bit48(i_vec48, o_vec48); CHECK_RESULT(int, o_vec48[0], ~i_vec48[0]); #ifdef VCS // VCS has bug where doesn't clean input CHECK_RESULT(int, o_vec48[1], (~i_vec48[1])); #else CHECK_RESULT(int, o_vec48[1], (~i_vec48[1]) & 0x0000ffffUL); #endif } { svBitVecVal i_vec95[3] = {0x72912312, 0xab782a12, 0x8a413bd9}; svBitVecVal o_vec95[3] = {0, 0, 0}; dpix_t_bit95(i_vec95, o_vec95); CHECK_RESULT(int, o_vec95[0], ~i_vec95[0]); CHECK_RESULT(int, o_vec95[1], ~i_vec95[1]); CHECK_RESULT(int, o_vec95[2], (~i_vec95[2]) & 0x7fffffffUL); } { svBitVecVal i_vec96[3] = {0xf2912312, 0xab782a12, 0x8a413bd9}; svBitVecVal o_vec96[3] = {0, 0, 0}; dpix_t_bit96(i_vec96, o_vec96); CHECK_RESULT(int, o_vec96[0], ~i_vec96[0]); CHECK_RESULT(int, o_vec96[1], ~i_vec96[1]); CHECK_RESULT(int, o_vec96[2], ~i_vec96[2]); } extern void dpix_t_reg(svLogic i, svLogic * o); { svLogic i = 0; svLogic o; dpix_t_reg(i, &o); CHECK_RESULT(svLogic, o, 1); i = 1; dpix_t_reg(i, &o); CHECK_RESULT(svLogic, o, 0); } { svLogicVecVal i[1]; i[0].aval = 0x12; i[0].bval = 0; svLogicVecVal o[1]; dpix_t_reg15(i, o); CHECK_RESULT(int, o[0].aval, (~i[0].aval) & 0x7fff); CHECK_RESULT(int, o[0].bval, 0); } { svLogicVecVal i[3]; i[0].aval = 0x72912312; i[0].bval = 0; i[1].aval = 0xab782a12; i[1].bval = 0; i[2].aval = 0x8a413bd9; i[2].bval = 0; svLogicVecVal o[3]; dpix_t_reg95(i, o); CHECK_RESULT(int, o[0].aval, ~i[0].aval); CHECK_RESULT(int, o[1].aval, ~i[1].aval); CHECK_RESULT(int, o[2].aval, (~i[2].aval) & 0x7fffffffUL); CHECK_RESULT(int, o[0].bval, 0); CHECK_RESULT(int, o[1].bval, 0); CHECK_RESULT(int, o[2].bval, 0); } #if !defined(VCS) && !defined(CADENCE) { svLogicVecVal i[2]; i[0].aval = 0x72912312; i[0].bval = 0; i[1].aval = 0xab782a12; i[1].bval = 0; svLogicVecVal o[2]; dpix_t_time(i, o); CHECK_RESULT(int, o[0].aval, ~i[0].aval); CHECK_RESULT(int, o[1].aval, ~i[1].aval); CHECK_RESULT(int, o[0].bval, 0); CHECK_RESULT(int, o[1].bval, 0); } #endif CHECK_RESULT(int, dpix__under___score(77), 78); if (int bad = check_sub("top.t.a", 1)) return bad; if (int bad = check_sub("top.t.b", 2)) return bad; return -1; // OK status } verilator-5.042/test_regress/t/t_func_no_paren.v0000644000542200017500000000154415101701376022420 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package pkg; class tb_cpu_seq_item; virtual function void uvm_report_error(string message); $display("%s", message); endfunction virtual function string get_type_name(); return "GTN"; endfunction virtual function bit do_compare(tb_cpu_seq_item rhs, int comparer); uvm_report_error( $sformatf( "this is of type %s, rhs is of type %s", this.get_type_name(), rhs.get_type_name())); uvm_report_error( $sformatf("this is of type %s, rhs is of type %s", this.get_type_name, rhs.get_type_name )); return 1'b0; endfunction endclass endpackage module t; endmodule verilator-5.042/test_regress/t/t_trace_packed_struct_fst.py0000755000542200017500000000114315101701376024652 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_packed_struct.v" test.compile(v_flags2=["--trace-fst"]) test.execute() test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_func_const_bad.out0000644000542200017500000000703315101701376023114 0ustar mahmoudyfreeshell%Error: t/t_func_const_bad.v:12:19: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_output' : ... note: In instance 't' t/t_func_const_bad.v:13:63: ... Location of non-constant VAR 'o': Language violation: Outputs/refs not allowed in constant functions 12 | localparam B1 = f_bad_output(1, 2); | ^~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_func_const_bad.v:21:19: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_dotted' : ... note: In instance 't' t/t_func_const_bad.v:23:22: ... Location of non-constant VARXREF 'EIGHT': Language violation: Dotted hierarchical references not allowed in constant functions t/t_func_const_bad.v:21:19: ... Called from 'f_bad_dotted()' with parameters: a = ?32?h2 21 | localparam B2 = f_bad_dotted(2); | ^~~~~~~~~~~~ %Error: t/t_func_const_bad.v:28:19: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_nonparam' : ... note: In instance 't' t/t_func_const_bad.v:30:22: ... Location of non-constant VARREF 'modvar': Language violation: reference to non-function-local variable t/t_func_const_bad.v:28:19: ... Called from 'f_bad_nonparam()' with parameters: a = ?32?h3 28 | localparam B3 = f_bad_nonparam(3); | ^~~~~~~~~~~~~~ %Error: t/t_func_const_bad.v:36:19: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_infinite' : ... note: In instance 't' t/t_func_const_bad.v:38:5: ... Location of non-constant LOOP: Loop unrolling took too long; probably this is aninfinite loop, or use /*verilator unroll_full*/, or set --unroll-count above 16386 t/t_func_const_bad.v:36:19: ... Called from 'f_bad_infinite()' with parameters: a = ?32?h3 36 | localparam B4 = f_bad_infinite(3); | ^~~~~~~~~~~~~~ %Error: t/t_func_const_bad.v:44:22: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_stop' : ... note: In instance 't' t/t_func_const_bad.v:46:5: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing t/t_func_const_bad.v:44:22: ... Called from 'f_bad_stop()' with parameters: a = ?32?h3 44 | localparam BSTOP = f_bad_stop(3); | ^~~~~~~~~~ -Info: "Printing in loop: 0" -Info: "Printing in loop: 1" -Info: "Printing in loop: 2" %Warning-USERFATAL: "Fatal Error" ... For warning description see https://verilator.org/warn/USERFATAL?v=latest ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. %Error: t/t_func_const_bad.v:51:23: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_fatal' : ... note: In instance 't' t/t_func_const_bad.v:56:5: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing t/t_func_const_bad.v:51:23: ... Called from 'f_bad_fatal()' with parameters: a = ?32?h3 51 | localparam BFATAL = f_bad_fatal(3); | ^~~~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_timing_zerodly_consecutive.v0000644000542200017500000000047615101701376025255 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t; initial begin #0; #0; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_param_ceil.py0000755000542200017500000000073415101701376022066 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_concat_sel.py0000755000542200017500000000073415101701376022104 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_strength_2_uneq_assign.v0000644000542200017500000000074715101701376024263 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; wire [5:0] a; assign (weak0, strong1) a = clk ? 'z : '0; assign (strong0, pull1) a = 6'b110001; initial begin if (a === 6'b110001) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_math_red_noexpand.py0000755000542200017500000000103315101701376023442 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_math_red.v" test.compile(verilator_flags2=['-fno-expand']) test.execute() test.passes() verilator-5.042/test_regress/t/t_dynarray.v0000644000542200017500000001015215101701376021430 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; integer i; // verilator lint_off UNUSED integer unused[]; // verilator lint_on UNUSED typedef bit [7:0] byte_t; byte_t a[]; byte_t b[]; // wide data array typedef struct packed { logic [15:0] header; logic [223:0] payload; logic [15:0] checksum; } pck256_t; pck256_t p256[]; string s[] = { "hello", "sad", "world" }; always @ (posedge clk) begin cyc <= cyc + 1; begin `checkh(a.size, 0); `checkp(a, "'{}"); `checkh(s.size, 3); `checks(s[0], "hello"); `checks(s[1], "sad"); `checks(s[2], "world"); a = new [3]; `checkh(a.size, 3); a[0] = 10; a[1] = 11; a[2] = 12; `checkh(a[0], 10); `checkh(a[1], 11); `checkh(a[2], 12); `checkp(a, "'{'ha, 'hb, 'hc}"); a.delete; `checkh(a.size, 0); a = '{15, 16}; `checkh(a.size, 2); `checkh(a[0], 15); `checkh(a[1], 16) a = {17, 18}; `checkh(a.size, 2); `checkh(a[0], 17); `checkh(a[1], 18) a = '{17}; `checkh(a.size, 1); // IEEE says resizes to smallest that fits pattern `checkh(a[0], 17); a = new[2]; a[0] = 5; a[1] = 6; `checkh(a[0], 5); `checkh(a[1], 6); a = new[2]; a[0] = 0; a[1] = 0; `checkh(a[0], 0); `checkh(a[1], 0); a[0] = 5; a[1] = 6; `checkh(a[0], 5); `checkh(a[1], 6); b = new [4](a); `checkh(b.size, 4); `checkh(b[0], 5); `checkh(b[1], 6); b[2] = 0; b[3] = 0; `checkh(b[2], 0); `checkh(b[3], 0); a = b; `checkh(a.size, 4); `checkh(a[0], 5); `checkh(a[1], 6); `checkh(a[2], 0); `checkh(a[3], 0); a = new [0]; `checkh(a.size, 0); b = new [4](a); `checkh(b.size, 4); b[0] = 0; b[1] = 0; b[2] = 0; b[3] = 0; `checkh(b[0], 0); `checkh(b[1], 0); `checkh(b[2], 0); `checkh(b[3], 0); a = new[4] ('{8'd1,8'd2,8'd3,8'd4}); `checkh(a.size, 4); `checkh(a[0], 1); `checkh(a[1], 2); `checkh(a[2], 3); `checkh(a[3], 4); i = 0; foreach (a[j]) i += int'(a[j]); `checkh(i, 1 + 2 + 3 + 4); // test wide dynamic array p256 = new [11]; `checkh(p256.size, 11); `checkh(p256.size(), 11); p256[1].header = 16'hcafe; p256[1].payload = {14{16'hbabe}}; p256[1].checksum = 16'hdead; `checkh(p256[1].header, 16'hcafe); `checkh(p256[1], {16'hcafe,{14{16'hbabe}},16'hdead}); //X's: `checkh(p256[0], 'x); p256[5] = '1; `checkh(p256[5], {32{8'hff}}); p256[5].header = 16'h2; `checkh(p256[5], {16'h2,{30{8'hff}}}); p256[2] = ( p256[5].header == 2 ) ? p256[1] : p256[5]; `checkh(p256[2], {16'hcafe,{14{16'hbabe}},16'hdead}); p256.delete(); `checkh(p256.size, 0); end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_opt_table_same.out0000644000542200017500000000043515101701376023122 0ustar mahmoudyfreeshellcyle 0 = 0 0 cyle 1 = 1 1 cyle 2 = 2 2 cyle 3 = 99 99 cyle 4 = 4 4 cyle 5 = 5 5 cyle 6 = 99 99 cyle 7 = 99 99 *-* All Finished *-* verilator-5.042/test_regress/t/t_preproc_resolve/0000755000542200017500000000000015101701376022622 5ustar mahmoudyfreeshellverilator-5.042/test_regress/t/t_preproc_resolve/submod.sv0000644000542200017500000000077715101701376024500 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `timescale 1ns/1ps module submod(/*AUTOARG*/ input logic clk, input logic rst, output logic out_signal ); always_ff @(posedge clk or posedge rst) begin if (rst) begin out_signal <= 1'b0; end else begin out_signal <= ~out_signal; end end endmodule verilator-5.042/test_regress/t/t_implements_notfound_bad.v0000644000542200017500000000044115101701376024476 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class ClsI implements Inotfound; endclass module t; ClsI ci; endmodule verilator-5.042/test_regress/t/t_param_type6.py0000755000542200017500000000073415101701376022221 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_dtype_compare_bad.out0000644000542200017500000001033415101701376024632 0ustar mahmoudyfreeshell%Error: t/t_lint_dtype_compare_bad.v:52:19: Comparison requires matching data types : ... note: In instance 't' : ... Left-hand data type: 'int$[$]' : ... Right-hand data type: 'logic[31:0]' 52 | if (queue_var == 1) begin end | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_lint_dtype_compare_bad.v:55:11: Comparison requires matching data types : ... note: In instance 't' : ... Left-hand data type: 'logic[31:0]' : ... Right-hand data type: 'int$[$]' 55 | if (1 == queue_var) begin end | ^~ %Error: t/t_lint_dtype_compare_bad.v:58:12: Comparison requires matching data types : ... note: In instance 't' : ... Left-hand data type: 'int$[$]' : ... Right-hand data type: 'bit$[$]' 58 | if (q1 == q2) begin end | ^~ %Error: t/t_lint_dtype_compare_bad.v:61:12: Comparison requires matching data types : ... note: In instance 't' : ... Left-hand data type: 'int$[]' : ... Right-hand data type: 'bit$[]' 61 | if (d1 == d2) begin end | ^~ %Error: t/t_lint_dtype_compare_bad.v:64:12: Comparison requires matching data types : ... note: In instance 't' : ... Left-hand data type: 'int$[0:1]' : ... Right-hand data type: 'int$[0:1][0:0]' 64 | if (u1 == u2) begin end | ^~ %Error: t/t_lint_dtype_compare_bad.v:67:12: Comparison requires matching data types : ... note: In instance 't' : ... Left-hand data type: 'int$[0:1]' : ... Right-hand data type: 'int$[0:2]' 67 | if (a1 == a2) begin end | ^~ %Error: t/t_lint_dtype_compare_bad.v:70:13: Comparison requires matching data types : ... note: In instance 't' : ... Left-hand data type: 'int$[string]' : ... Right-hand data type: 'int$[int]' 70 | if (aa1 == aa2) begin end | ^~ %Error: t/t_lint_dtype_compare_bad.v:73:13: Comparison requires matching data types : ... note: In instance 't' : ... Left-hand data type: 'int$[string]' : ... Right-hand data type: 'logic[3:0]$[string]' 73 | if (aa3 == aa4) begin end | ^~ %Error: t/t_lint_dtype_compare_bad.v:76:14: Comparison requires matching data types : ... note: In instance 't' : ... Left-hand data type: 'int$[0:1]' : ... Right-hand data type: 'bit$[0:1]' 76 | if (bad1 == bad2) begin end | ^~ %Error: t/t_lint_dtype_compare_bad.v:79:14: Comparison requires matching data types : ... note: In instance 't' : ... Left-hand data type: 'int$[string]' : ... Right-hand data type: 'logic[31:0]$[string]' 79 | if (val1 == val2) begin end | ^~ %Error: t/t_lint_dtype_compare_bad.v:82:13: Comparison requires matching data types : ... note: In instance 't' : ... Left-hand data type: 'int$[string]' : ... Right-hand data type: 'int$[int]' 82 | if (aa5 == aa6) begin end | ^~ %Error: Exiting due to verilator-5.042/test_regress/t/t_typedef_signed.v0000644000542200017500000000432615101701376022576 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 //bug456 typedef logic signed [34:0] rc_t; module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [34:0] rc = crc[34:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) logic o; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .o (o), // Inputs .rc (rc), .clk (clk)); // Aggregate outputs into a single result vector wire [63:0] result = {63'h0, o}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h7211d24a17b25ec9 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test( output logic o, input rc_t rc, input logic clk); localparam RATIO = 2; rc_t rc_d[RATIO:1]; always_ff @(posedge clk) begin integer k; rc_d[1] <= rc; for( k=2; k v_arr_real[1] $end $var wire 64 P v_chandle [63:0] $end $scope module v_str32x2[0] $end $var wire 32 @ data [31:0] $end $upscope $end $scope module v_str32x2[1] $end $var wire 32 A data [31:0] $end $upscope $end $var wire 32 B v_enumed [31:0] $end $var wire 32 C v_enumed2 [31:0] $end $var wire 3 D v_enumb [2:0] $end $scope module v_enumb2_str $end $var wire 3 E a [2:0] $end $var wire 3 F b [2:0] $end $upscope $end $var wire 8 R unpacked_array[-2] [7:0] $end $var wire 8 S unpacked_array[-1] [7:0] $end $var wire 8 T unpacked_array[0] [7:0] $end $var wire 1 U LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end $scope module unnamedblk1 $end $var wire 32 G b [31:0] $end $scope module unnamedblk2 $end $var wire 32 H a [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 1# b00000000000000000000000000000000 $ 0% 0& 0' 0( 0) 0* 0+ 0, b00 - b00 . b00 / 00 01 02 03 b00 4 b00 5 06 07 08 09 r0 : r0 < r0 > b00000000000000000000000011111111 @ b00000000000000000000000000000000 A b00000000000000000000000000000000 B b00000000000000000000000000000000 C b000 D b000 E b000 F b00000000000000000000000000000000 G b00000000000000000000000000000000 H 0I 0J 0K 0L 0M 0N 0O b0000000000000000000000000000000000000000000000000000000000000000 P b00000000 R b00000000 S b00000000 T 0U #10 b00000000000000000000000000000001 $ 1% 1& 1' 1( 1) 1* 1+ 1, b11 - b11 . b11 / 10 11 12 13 b11 4 b11 5 16 17 18 19 r0.1 : r0.2 < r0.3 > b00000000000000000000000011111110 @ b00000000000000000000000000000001 A b00000000000000000000000000000001 B b00000000000000000000000000000010 C b111 D b00000000000000000000000000000101 G b00000000000000000000000000000101 H 1I #15 0I #20 b00000000000000000000000000000010 $ 0% 0& 0' 0( 0) 0* 0+ 0, b00 - b00 . b00 / 00 01 02 03 b00 4 b00 5 06 07 08 09 r0.2 : r0.4 < r0.6 > b00000000000000000000000011111101 @ b00000000000000000000000000000010 A b00000000000000000000000000000010 B b00000000000000000000000000000100 C b110 D b111 E b111 F 1I #25 0I #30 b00000000000000000000000000000011 $ 1% 1& 1' 1( 1) 1* 1+ 1, b11 - b11 . b11 / 10 11 12 13 b11 4 b11 5 16 17 18 19 r0.3 : r0.6000000000000001 < r0.8999999999999999 > b00000000000000000000000011111100 @ b00000000000000000000000000000011 A b00000000000000000000000000000011 B b00000000000000000000000000000110 C b101 D b110 E b110 F 1I #35 0I #40 b00000000000000000000000000000100 $ 0% 0& 0' 0( 0) 0* 0+ 0, b00 - b00 . b00 / 00 01 02 03 b00 4 b00 5 06 07 08 09 r0.4 : r0.8 < r1.2 > b00000000000000000000000011111011 @ b00000000000000000000000000000100 A b00000000000000000000000000000100 B b00000000000000000000000000001000 C b100 D b101 E b101 F 1I #45 0I #50 b00000000000000000000000000000101 $ 1% 1& 1' 1( 1) 1* 1+ 1, b11 - b11 . b11 / 10 11 12 13 b11 4 b11 5 16 17 18 19 r0.5 : r1 < r1.5 > b00000000000000000000000011111010 @ b00000000000000000000000000000101 A b00000000000000000000000000000101 B b00000000000000000000000000001010 C b011 D b100 E b100 F 1I #55 0I #60 b00000000000000000000000000000110 $ 0% 0& 0' 0( 0) 0* 0+ 0, b00 - b00 . b00 / 00 01 02 03 b00 4 b00 5 06 07 08 09 r0.6 : r1.2 < r1.8 > b00000000000000000000000011111001 @ b00000000000000000000000000000110 A b00000000000000000000000000000110 B b00000000000000000000000000001100 C b010 D b011 E b011 F 1I verilator-5.042/test_regress/t/t_timing_reentry.v0000644000542200017500000000155615101701376022646 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; event a, b; int order = 0; initial begin order++; if (order != 1) $stop; #10; $display("[%0t]%0d -> a", $time, order); order++; if (order != 2) $stop; -> a; #10; $display("[%0t]%0d -> b", $time, order); order++; if (order != 4) $stop; -> b; #100; order++; if (order != 6) $stop; $write("*-* All Finished *-*\n"); $finish; end always @ (a or b) begin $display("[%0t]%0d entering", $time, order); order++; if (order != 3) $stop; #15; $display("[%0t]%0d 15 later", $time, order); order++; if (order != 5) $stop; end endmodule verilator-5.042/test_regress/t/t_inst_nansi_dup_bad.py0000755000542200017500000000076615101701376023622 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_mod_macromodule.v0000644000542200017500000000047015101701376022747 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 macromodule t; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_mod_interface_array1_noinl.py0000755000542200017500000000104515101701376025243 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_mod_interface_array1.v" test.compile(v_flags2=["-fno-inline"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_assert_ctl_type_bad.out0000644000542200017500000000070315101701376024154 0ustar mahmoudyfreeshell%Error: t/t_assert_ctl_type_bad.v:9:5: Bad $assertcontrol control_type '0' (IEEE 1800-2023 Table 20-5) 9 | $assertcontrol(0); | ^~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_assert_ctl_type_bad.v:10:5: Bad $assertcontrol control_type '100' (IEEE 1800-2023 Table 20-5) 10 | $assertcontrol(100); | ^~~~~~~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_alw_sen_compare.py0000755000542200017500000000075115101701376023127 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--timing"]) test.passes() verilator-5.042/test_regress/t/t_class_super_new_bad_nfirst.py0000755000542200017500000000076615101701376025366 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_string_type_methods_bad.out0000644000542200017500000000211615101701376025042 0ustar mahmoudyfreeshell%Error: t/t_string_type_methods_bad.v:15:13: The 1 arguments passed to .len method does not match its requiring 0 arguments : ... note: In instance 't' 15 | i = s.len(0); | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_string_type_methods_bad.v:16:9: The 0 arguments passed to .itoa method does not match its requiring 1 arguments : ... note: In instance 't' 16 | s.itoa; | ^~~~ %Error: t/t_string_type_methods_bad.v:17:9: The 3 arguments passed to .itoa method does not match its requiring 1 arguments : ... note: In instance 't' 17 | s.itoa(1,2,3); | ^~~~ %Error: t/t_string_type_methods_bad.v:18:9: Unknown built-in string method 'bad_no_such_method' : ... note: In instance 't' 18 | s.bad_no_such_method(); | ^~~~~~~~~~~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_gen_genblk.out0000644000542200017500000000340015101701376022232 0ustar mahmoudyfreeshell021: got=top.t.direct_ignored.show1 023: got=top.t.direct_ignored.genblk1.show2 exp=1 gennum=1 030: got=top.t.empty_DISAGREE.genblk1.show2 exp=0 gennum=1 037: got=top.t.empty_named_DISAGREE.genblk1.show2 exp=0 gennum=1 043: got=top.t.unnamed_counts.show1 046: got=top.t.unnamed_counts.genblk1.show2 exp=0 gennum=1 052: got=top.t.named_counts.named.show1 055: got=top.t.named_counts.genblk1.show2 exp=0 gennum=1 061: got=top.t.if_direct_counts.genblk1.show1 063: got=top.t.if_direct_counts.genblk2.show2 exp=2 gennum=2 069: got=top.t.if_begin_counts.genblk1.show1 071: got=top.t.if_begin_counts.genblk2.show2 exp=2 gennum=2 076: got=top.t.if_named_counts.named.show1 078: got=top.t.if_named_counts.named.subnamed.show1s 082: got=top.t.if_named_counts.genblk2.show2 exp=2 gennum=2 089: got=top.t.begin_if_counts.genblk1.show1 092: got=top.t.begin_if_counts.genblk2.show2 exp=2 gennum=2 099: got=top.t.for_empty_counts.genblk2.show2 exp=0 gennum=2 104: got=top.t.for_direct_counts.genblk1[0].show1 106: got=top.t.for_direct_counts.genblk2.show2 exp=2 gennum=2 111: got=top.t.for_named_counts.fornamed[0].show1 114: got=top.t.for_named_counts.genblk2.show2 exp=2 gennum=2 119: got=top.t.for_begin_counts.genblk1[0].show1 122: got=top.t.for_begin_counts.genblk2.show2 exp=2 gennum=2 132: got=top.t.if_if.genblk1.genblk1.show1 136: got=top.t.if_if.genblk2.show2 exp=2 gennum=2 142: got=top.t.case_direct.genblk1.show1 146: got=top.t.case_direct.genblk2.show2 exp=2 gennum=2 152: got=top.t.case_begin_counts.genblk1.show1 156: got=top.t.case_begin_counts.genblk2.show2 exp=2 gennum=2 162: got=top.t.case_named_counts.subnamed.show1 166: got=top.t.case_named_counts.genblk2.show2 exp=2 gennum=2 *-* All Finished *-* verilator-5.042/test_regress/t/t_flag_nofile_bad.py0000755000542200017500000000122015101701376023034 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.run(cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator --lint-only"], fails=True, logfile=test.obj_dir + "/sim.log", expect_filename=test.golden_filename, verilator_run=True) test.passes() verilator-5.042/test_regress/t/t_lint_eofnewline_bad.out0000644000542200017500000000077715101701376024144 0ustar mahmoudyfreeshell%Warning-EOFNEWLINE: obj_vlt/t_lint_eofnewline_bad/t_lint_eofnewline_bad.v:4:10: Missing newline at end of file (POSIX 3.206). : ... Suggest add newline. 4 | endmodule | ^ ... For warning description see https://verilator.org/warn/EOFNEWLINE?v=latest ... Use "/* verilator lint_off EOFNEWLINE */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_flag_values_deprecated.py0000755000542200017500000000112515101701376024435 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["-Werror-DEPRECATED", "--no-threads"], fails=True, threads=0, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_const_func_gen_bad.v0000644000542200017500000000077015101701376024432 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Donald Owen. // SPDX-License-Identifier: CC0-1.0 module t (); if (1) begin: GenConstFunc // IEEE 1800-2023 13.4.3, constant functions shall not be declared inside a //generate block function automatic bit constFunc(); constFunc = 1'b1; endfunction localparam PARAM = constFunc(); end endmodule verilator-5.042/test_regress/t/t_opt_const_or.v0000644000542200017500000000621615101701376022315 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [31:0] rd0; // From test of Test.v wire [31:0] rd1; // From test of Test.v // End of automatics wire rden0 = crc[0]; wire rden1 = crc[1]; wire [4:0] raddr0 = crc[20:16]; wire [4:0] raddr1 = crc[28:24]; Test test(/*AUTOINST*/ // Outputs .rd0 (rd0[31:0]), .rd1 (rd1[31:0]), // Inputs .clk (clk), .raddr0 (raddr0[4:0]), .raddr1 (raddr1[4:0]), .rden0 (rden0), .rden1 (rden1)); // Aggregate outputs into a single result vector wire [63:0] result = {rd1, rd0}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc == 0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc < 10) begin sum <= '0; end else if (cyc == 99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'hdc97b141ac5d6d7d if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test(/*AUTOARG*/ // Outputs rd0, rd1, // Inputs clk, raddr0, raddr1, rden0, rden1 ); input clk; input [4:0] raddr0; input [4:0] raddr1; input rden0; input rden1; output reg [31:0] rd0; output reg [31:0] rd1; reg [31:0] gpr [31:1]; initial begin for (int j=1; j<32; j++ ) begin gpr[j] = {8'(j), 8'(j), 8'(j), 8'(j)}; end end always_comb begin rd0[31:0] = 32'b0; rd1[31:0] = 32'b0; // Future optimization: // Multiple assignments to same variable with OR between them // ASSIGN(a, OR(a, aq)), ASSIGN(a, OR(a, bq)) -> ASSIGN(a, OR(a, OR(aq, bq)) // Skip if we're not const'ing an entire module (IE doing only one assign, etc) for (int j=1; j<32; j++ ) begin rd0[31:0] |= ({32{rden0 & (raddr0[4:0]== 5'(j))}} & gpr[j][31:0]); rd1[31:0] |= ({32{rden1 & (raddr1[4:0]== 5'(j))}} & gpr[j][31:0]); end end endmodule verilator-5.042/test_regress/t/t_mod_dot.v0000644000542200017500000000046515101701376021232 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by engr248. // SPDX-License-Identifier: CC0-1.0 module \foo.bar ; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_lint_numwidth.py0000755000542200017500000000076115101701376022657 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["--max-num-width 131072"]) test.passes() verilator-5.042/test_regress/t/t_mod_dup_bad.py0000755000542200017500000000076315101701376022231 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_var_rsvd.py0000755000542200017500000000073415101701376021620 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_flag_xinitial_0.v0000644000542200017500000000102715101701376022631 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs value ); output reg [63:0] value; initial begin `ifdef VERILATOR // Default is all ones, so we assume that here if (value != '0) $stop; `else if (value != {64{1'bx}}) $stop; `endif $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_assoc2.py0000755000542200017500000000073415101701376021164 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_param_noinit_bad.v0000644000542200017500000000073615101701376024261 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // No init value is legal with classes, as long as not used without the parameter class Cls #(int A, int B, type T); endclass module t; initial begin Cls #(1) c; // Bad: missing B $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_parse_sync_bad.v0000644000542200017500000000107015101701376022552 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Dan Petrisko. // SPDX-License-Identifier: CC0-1.0 package pkg; class cls; typedef unknown defu; typedef int defi; endclass endpackage module t; task tsk; begin valid1 = 5; // valid statement pkg::cls::defi invalid; // invalid statement end endtask endmodule typedef struct packed { logic clk /*verilator clocker*/; logic data; } ss_s; endmodule verilator-5.042/test_regress/t/t_assert_ctl_arg_unsup.py0000755000542200017500000000076315101701376024222 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_flag_suggest.py0000755000542200017500000000246415101701376022446 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') opts = [] # Typo opts += ["-ccc"] # Typo of an option that starts with "--" opts += ["--ccc"] # Typo of an option that starts with "-no-" opts += ["-no-asserT"] # Typo of an option that starts with "-no" opts += ["-noasserT"] # Typo of an option that allows "-no" opts += ["-asserT"] # Typo of an option that starts with '+' opts += ["+definE+A=B"] # Typo that takes arg opts += ["-CFLAGs -ggdb"] # Typo of an undocumented option opts += ["-debug-aborT"] # Typo of "-Wno" for partial match opts += ["-Won-SPLITVAR"] # Typo after -Wno- for partial match opts += ["-Wno-SPLITVER"] # Typo of -language opts += ["-language 1364-1997"] cmd = "" for var in opts: cmd += os.environ["VERILATOR_ROOT"] + "/bin/verilator " + var + "; " test.run(cmd=[cmd], verilator_run=True, logfile=test.obj_dir + "/sim.log", fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_flag_libcreate_bad.out0000644000542200017500000000030515101701376023671 0ustar mahmoudyfreeshell%Error: --lib-create argument must be a legal C++ identifier: 'bad/name' ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_var_dup_bad.v0000644000542200017500000000174215101701376022052 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ // Outputs o, oi, og, org, // Inputs i, oi ); reg a; reg a; integer l; integer l; bit b; bit b; output o; output o; input i; input i; output oi; input oi; output og; reg og; reg og; output reg org; output reg org; sub0 sub0(.*); sub1 sub1(.*); sub2 sub2(.*); sub3 sub3(.*); endmodule module sub0 ( bad_duport, bad_duport ); output bad_duport; endmodule module sub1 ( bad_mixport, output bad_mixport ); endmodule module sub2 ( output bad_reout_port ); output bad_reout_port; endmodule module sub3 (output wire bad_rewire, output reg bad_rereg ); wire bad_rewire; reg bad_rereg; endmodule verilator-5.042/test_regress/t/t_select_bad_range2.v0000644000542200017500000000241015101701376023120 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [1:0] in; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [1:0] out10; // From test of Test.v wire [1:0] out32; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out32 (out32[1:0]), .out10 (out10[1:0]), // Inputs .in (in[1:0])); // Test loop always @ (posedge clk) begin in <= in + 1; `ifdef TEST_VERBOSE $write("[%0t] in=%d out32=%d out10=%d\n", $time, in, out32, out10); `endif if (in==3) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs out32, out10, // Inputs in ); input [1:0] in; output [1:0] out32; output [1:0] out10; assign out32 = in[3:2]; assign out10 = in[1:0]; endmodule verilator-5.042/test_regress/t/t_func_sel.py0000755000542200017500000000073415101701376021570 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_warn_incfile2_bad.v0000644000542200017500000000066115101701376024161 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Check that lint_off doesn't propagate from include, for post-preprocessor warnings `include "t_lint_warn_incfile2_bad_b.vh" module t; sub sub(); int warn_t = 64'h1; // Not suppressed - should warn endmodule verilator-5.042/test_regress/t/t_hier_block_prot_lib.py0000755000542200017500000000327615101701376023771 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all', 'xsim') test.top_filename = "t/t_hier_block.v" secret_prefix = "secret" secret_dir = test.obj_dir + "/" + secret_prefix test.mkdir_ok(secret_dir) # Always compile the secret file with Verilator no matter what simulator # we are testing with test.run(logfile=secret_dir + "/vlt_compile.log", cmd=[ "perl", os.environ["VERILATOR_ROOT"] + "/bin/verilator", "-cc", "--hierarchical", "-Mdir", secret_dir, "--protect-lib", secret_prefix, "--protect-key", "PROTECT_KEY", "t/t_hier_block.v", "-DAS_PROT_LIB", '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"', (' --threads 1' if test.vltmt else ''), "--build" ], verilator_run=True) test.compile(v_flags2=['t/t_hier_block.cpp'], verilator_flags2=[ secret_dir + "/secret.sv", "-DPROTLIB_TOP", "--top-module t", "-LDFLAGS", "'" + secret_prefix + "/libsecret.a'" ]) test.execute() test.passes() test.file_grep(secret_dir + "/Vsub0/sub0.sv", r'^module\s+(\S+)\s+', "sub0") test.file_grep(secret_dir + "/Vsub1/sub1.sv", r'^module\s+(\S+)\s+', "sub1") test.file_grep(secret_dir + "/Vsub2/sub2.sv", r'^module\s+(\S+)\s+', "sub2") test.file_grep(test.run_log_filename, r'MACRO:(\S+) is defined', "cplusplus") test.passes() verilator-5.042/test_regress/t/t_verilated_all.py0000755000542200017500000000367215101701376022605 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vltmt') if not os.path.exists(test.root + "/.git"): test.skip("Not in a git repository") test.compile( # Can't use --coverage and --savable together, so cheat and compile inline verilator_flags2=[ "--cc", "--coverage-toggle --coverage-line --coverage-user", "--trace-vcd --vpi ", "--trace-threads 1", ("--timing" if test.have_coroutines else "--no-timing -Wno-STMTDLY"), "--prof-exec", "--prof-pgo", test.root + "/include/verilated_save.cpp" ], threads=2) test.execute( all_run_flags=[" +verilator+prof+exec+file+/dev/null", " +verilator+prof+vlt+file+/dev/null"]) hit = {} for filename in (test.glob_some(test.root + "/include/*.cpp") + test.glob_some(test.root + "/include/*.h")): filename = os.path.basename(filename) if test.verbose: print("NEED: " + filename) hit[filename] = False for dfile in test.glob_some(test.obj_dir + "/*.d"): wholefile = test.file_contents(dfile) for filename in wholefile.split(): filename = os.path.basename(filename) if test.verbose: print("USED: " + filename) hit[filename] = True for filename in sorted(hit.keys()): if (not hit[filename] and not re.search(r'_sc', filename) and not re.search(r'_fst', filename) and not re.search(r'_saif', filename) and not re.search(r'_thread', filename) and (not re.search(r'_timing', filename) or test.have_coroutines)): test.error("Include file not covered by t_verilated_all test: ", filename) test.passes() verilator-5.042/test_regress/t/t_cover_toggle_min.py0000755000542200017500000000177715101701376023324 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--binary', '--coverage-toggle']) test.execute(all_run_flags=[" +verilator+coverage+file+" + test.obj_dir + "/coverage.dat"]) if os.path.exists(test.obj_dir + "/coverage.dat"): # Don't try to write .info if test was skipped test.run(cmd=[ os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "-write-info", test.obj_dir + "/coverage.info", test.obj_dir + "/coverage.dat", ], verilator_run=True) test.files_identical(test.obj_dir + "/coverage.info", "t/" + test.name + ".info.out") test.passes() verilator-5.042/test_regress/t/t_std_pkg_bad.out0000644000542200017500000000036115101701376022403 0ustar mahmoudyfreeshell%Error: t/t_std_pkg_bad.v:7:9: Redeclaring the 'std' package is not allowed 7 | package std; | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_vlt_warn_ecode_bad.out0000644000542200017500000000064515101701376023750 0ustar mahmoudyfreeshell%Error: t/t_vlt_warn_ecode_bad.vlt:9:1: Unknown error code: 'BADRULENAME' 9 | lint_off -rule BADRULENAME -file "t/t_vlt_warn.v" | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_vlt_warn_ecode_bad.vlt:10:1: Unknown error code: 'BADRULENAME' 10 | lint_on -rule BADRULENAME -file "t/t_vlt_warn.v" | ^~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_randstate_seed_bad.out0000644000542200017500000000024315101701376023734 0ustar mahmoudyfreeshell%Warning: set_randstate ignored as state string not from get_randstate %Warning: set_randstate ignored as state string not from get_randstate *-* All Finished *-* verilator-5.042/test_regress/t/t_order_multidriven.v0000644000542200017500000001107615101701376023342 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Ted Campbell. // SPDX-License-Identifier: CC0-1.0 //With MULTI_CLK defined shows bug, without it is hidden `define MULTI_CLK //bug634 module t ( input i_clk_wr, input i_clk_rd ); wire wr$wen; wire [7:0] wr$addr; wire [7:0] wr$wdata; wire [7:0] wr$rdata; wire rd$wen; wire [7:0] rd$addr; wire [7:0] rd$wdata; wire [7:0] rd$rdata; wire clk_wr; wire clk_rd; `ifdef MULTI_CLK assign clk_wr = i_clk_wr; assign clk_rd = i_clk_rd; `else assign clk_wr = i_clk_wr; assign clk_rd = i_clk_wr; `endif FooWr u_wr ( .i_clk ( clk_wr ), .o_wen ( wr$wen ), .o_addr ( wr$addr ), .o_wdata ( wr$wdata ), .i_rdata ( wr$rdata ) ); FooRd u_rd ( .i_clk ( clk_rd ), .o_wen ( rd$wen ), .o_addr ( rd$addr ), .o_wdata ( rd$wdata ), .i_rdata ( rd$rdata ) ); FooMem u_mem ( .iv_clk ( {clk_wr, clk_rd } ), .iv_wen ( {wr$wen, rd$wen } ), .iv_addr ( {wr$addr, rd$addr } ), .iv_wdata ( {wr$wdata,rd$wdata} ), .ov_rdata ( {wr$rdata,rd$rdata} ) ); endmodule // Memory Writer module FooWr( input i_clk, output o_wen, output [7:0] o_addr, output [7:0] o_wdata, input [7:0] i_rdata ); reg [7:0] cnt = 0; // Count [0,200] always @( posedge i_clk ) if ( cnt < 8'd50 ) cnt <= cnt + 8'd1; // Write addr in (10,30) if even assign o_wen = ( cnt > 8'd10 ) && ( cnt < 8'd30 ) && ( cnt[0] == 1'b0 ); assign o_addr = cnt; assign o_wdata = cnt; endmodule // Memory Reader module FooRd( input i_clk, output o_wen, output [7:0] o_addr, output [7:0] o_wdata, input [7:0] i_rdata ); reg [7:0] cnt = 0; reg [7:0] addr_r; reg en_r; // Count [0,200] always @( posedge i_clk ) if ( cnt < 8'd200 ) cnt <= cnt + 8'd1; // Read data assign o_wen = 0; assign o_addr = cnt - 8'd100; // Track issued read always @( posedge i_clk ) begin addr_r <= o_addr; en_r <= ( cnt > 8'd110 ) && ( cnt < 8'd130 ) && ( cnt[0] == 1'b0 ); end // Display to console 100 cycles after writer always @( negedge i_clk ) if ( en_r ) begin `ifdef TEST_VERBOSE $display( "MEM[%x] == %x", addr_r, i_rdata ); `endif if (addr_r != i_rdata) $stop; end endmodule // Multi-port memory abstraction module FooMem( input [2 -1:0] iv_clk, input [2 -1:0] iv_wen, input [2*8-1:0] iv_addr, input [2*8-1:0] iv_wdata, output [2*8-1:0] ov_rdata ); FooMemImpl u_impl ( .a_clk ( iv_clk [0*1+:1] ), .a_wen ( iv_wen [0*1+:1] ), .a_addr ( iv_addr [0*8+:8] ), .a_wdata ( iv_wdata[0*8+:8] ), .a_rdata ( ov_rdata[0*8+:8] ), .b_clk ( iv_clk [1*1+:1] ), .b_wen ( iv_wen [1*1+:1] ), .b_addr ( iv_addr [1*8+:8] ), .b_wdata ( iv_wdata[1*8+:8] ), .b_rdata ( ov_rdata[1*8+:8] ) ); endmodule // Dual-Port L1 Memory Implementation module FooMemImpl( input a_clk, input a_wen, input [7:0] a_addr, input [7:0] a_wdata, output reg [7:0] a_rdata, input b_clk, input b_wen, input [7:0] b_addr, input [7:0] b_wdata, output reg [7:0] b_rdata ); /* verilator lint_off MULTIDRIVEN */ reg [7:0] mem[0:255]; /* verilator lint_on MULTIDRIVEN */ always @( posedge a_clk ) if ( a_wen ) mem[a_addr] <= a_wdata; always @( posedge b_clk ) if ( b_wen ) mem[b_addr] <= b_wdata; always @( posedge a_clk ) a_rdata <= mem[a_addr]; always @( posedge b_clk ) b_rdata <= mem[b_addr]; endmodule verilator-5.042/test_regress/t/t_alias_hier_ref_bad.v0000644000542200017500000000125515101701376023345 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias' // // Alias type check error test. // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ // Inputs clk ); input clk; reg [15:0] out; wire [15:0] a; alias a = sub_i.btw; sub sub_i ( .clk(clk), .out(out) ); endmodule module sub ( input clk, output wire [15:0] out ); reg [31:0] counter = 32'h0; wire [15:0] btw; assign btw = {counter[15:0]}; assign out = btw; always @(posedge clk) begin counter += 1; end endmodule verilator-5.042/test_regress/t/t_vpi_module_empty.cpp0000644000542200017500000000561715101701376023507 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2010-2023 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #ifdef IS_VPI #include "vpi_user.h" #include #else #include "verilated.h" #include "verilated_vcd_c.h" #include "verilated_vpi.h" #include "Vt_vpi_module_empty.h" #include "Vt_vpi_module_empty__Dpi.h" #include "svdpi.h" #endif #include #include #include extern "C" { #include } // These require the above. Comment prevents clang-format moving them #include "TestSimulator.h" #include "TestVpi.h" extern "C" { int mon_check() { #ifdef TEST_VERBOSE printf("-mon_check()\n"); #endif TestVpiHandle it = vpi_iterate(vpiModule, NULL); CHECK_RESULT_NZ(it); return 0; // Ok } } //====================================================================== #ifdef IS_VPI static int mon_check_vpi() { TestVpiHandle href = vpi_handle(vpiSysTfCall, 0); s_vpi_value vpi_value; vpi_value.format = vpiIntVal; vpi_value.value.integer = mon_check(); vpi_put_value(href, &vpi_value, NULL, vpiNoDelay); return 0; } static s_vpi_systf_data vpi_systf_data[] = {{vpiSysFunc, vpiIntFunc, (PLI_BYTE8*)"$mon_check", (PLI_INT32(*)(PLI_BYTE8*))mon_check_vpi, 0, 0, 0}, 0}; // cver entry void vpi_compat_bootstrap(void) { p_vpi_systf_data systf_data_p; systf_data_p = &(vpi_systf_data[0]); while (systf_data_p->type != 0) vpi_register_systf(systf_data_p++); } // icarus entry void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0}; #else int main(int argc, char** argv) { const std::unique_ptr contextp{new VerilatedContext}; uint64_t sim_time = 1100; contextp->debug(0); contextp->commandArgs(argc, argv); // we're going to be checking for these errors do don't crash out contextp->fatalOnVpiError(0); // Test second construction const std::unique_ptr topp{new VM_PREFIX{contextp.get(), // Note null name - we're flattening it out ""}}; #ifdef VERILATOR #ifdef TEST_VERBOSE contextp->scopesDump(); #endif #endif topp->eval(); VerilatedVpi::callValueCbs(); TestVpiHandle vh = vpi_handle_by_name((PLI_BYTE8*)"top.sv_if_i.a", NULL); CHECK_RESULT_NZ(vh); TestVpiHandle it = vpi_iterate(vpiModule, NULL); CHECK_RESULT_NZ(it); topp->final(); return 0; } #endif verilator-5.042/test_regress/t/t_enum_size.py0000755000542200017500000000073415101701376021770 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_contassreg_bad.v0000644000542200017500000000044515101701376023607 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(r); output r; reg r; assign r = 1'b0; // Bad endmodule verilator-5.042/test_regress/t/t_lint_latch_6.py0000755000542200017500000000070315101701376022334 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint() test.passes() verilator-5.042/test_regress/t/t_flag_aslr.py0000755000542200017500000000077215101701376021726 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = 't/t_EXAMPLE.v' test.lint(v_flags2=["--aslr"]) test.passes() verilator-5.042/test_regress/t/t_hier_trace_sub/0000755000542200017500000000000015101701376022367 5ustar mahmoudyfreeshellverilator-5.042/test_regress/t/t_hier_trace_sub/sub.F0000644000542200017500000000046215101701376023271 0ustar mahmoudyfreeshell# Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 t_hier_trace_sub.v verilator-5.042/test_regress/t/t_hier_trace_sub/t_hier_trace.vlt0000644000542200017500000000042415101701376025546 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `verilator_config hier_block -module "detail_code" hier_block -module "sub_top" verilator-5.042/test_regress/t/t_hier_trace_sub/top.F0000644000542200017500000000045015101701376023277 0ustar mahmoudyfreeshell# Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -F sub.F verilator-5.042/test_regress/t/t_hier_trace_sub/t_hier_trace_sub.v0000644000542200017500000000166615101701376026070 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module detail_code( input clk, input reset_l); endmodule module sub_top( input clk, input reset_l); detail_code u0( .clk(clk), .reset_l(reset_l) ); detail_code u1( .clk(clk), .reset_l(reset_l) ); detail_code u2( .clk(clk), .reset_l(reset_l) ); detail_code u3( .clk(clk), .reset_l(reset_l) ); detail_code u4( .clk(clk), .reset_l(reset_l) ); detail_code u5( .clk(clk), .reset_l(reset_l) ); detail_code u6( .clk(clk), .reset_l(reset_l) ); detail_code u7( .clk(clk), .reset_l(reset_l) ); endmodule verilator-5.042/test_regress/t/t_preproc_stringend_bad.v0000644000542200017500000000033415101701376024135 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 "Blah verilator-5.042/test_regress/t/t_interface_missing_bad.v0000644000542200017500000000102715101701376024077 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Missing interface test // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 // Interface intentionally not defined //interface foo_intf; // logic a; //endinterface module foo_mod ( foo_intf foo ); endmodule module t; foo_intf the_foo (); foo_mod foo_mod ( .foo (the_foo) ); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_tri_inout.cpp0000644000542200017500000000305715101701376022136 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2008 by Lane Brooks. // SPDX-License-Identifier: CC0-1.0 #include VM_PREFIX_INCLUDE VM_PREFIX* tb = nullptr; double sc_time_stamp() { return 0; } bool check() { bool pass; int Z; if (tb->SEL) { Z = tb->A; } else { Z = tb->B; } if (tb->Z == tb->Y1 && tb->Z == tb->Y2 && tb->Z == Z) { printf("PASS: "); pass = true; } else { printf("FAIL: "); pass = false; } #ifdef TEST_VERBOSE printf("SEL=%d A=%d B=%d Z=%d Y1=%d Y2=%d\n", tb->SEL, tb->A, tb->B, tb->Z, tb->Y1, tb->Y2); #endif return pass; } int main() { bool pass = true; Verilated::debug(0); tb = new VM_PREFIX{"tb"}; // loop through every possibility and check the result for (tb->SEL = 0; tb->SEL < 2; tb->SEL++) { for (tb->A = 0; tb->A < 2; tb->A++) { for (tb->B = 0; tb->B < 2; tb->B++) { tb->eval(); if (!check()) pass = false; } } } tb->SEL = tb->A = tb->B = 0; for (int i = 0; i < 256; ++i) { tb->clk = 0; tb->eval(); tb->clk = 1; tb->eval(); if (tb->done) break; if (i + 1 == 256) pass = false; } if (pass) { VL_PRINTF("*-* All Finished *-*\n"); tb->final(); } else { vl_fatal(__FILE__, __LINE__, "top", "Unexpected results from inout test\n"); } VL_DO_DANGLING(delete tb, tb); return 0; } verilator-5.042/test_regress/t/t_sys_rand.py0000755000542200017500000000073415101701376021614 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_param_type_fwd_bad.v0000644000542200017500000000147215101701376023413 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef int int_t; module sub; parameter type enum E_t; parameter type struct S_t; parameter type union U_t; parameter type class C_t; parameter type interface class IC_t; endmodule class Cls #(parameter type enum E_t, parameter type struct S_t, parameter type union U_t, parameter type class C_t, parameter type interface class IC_t); endclass module t; sub #(.E_t(int_t), .S_t(int_t), .U_t(int_t), .C_t(int_t), .IC_t(int_t)) sub(); Cls #(.E_t(int_t), .S_t(int_t), .U_t(int_t), .C_t(int_t), .IC_t(int_t)) c; initial begin c = new; end endmodule verilator-5.042/test_regress/t/t_opt_ifjumpgo.v0000644000542200017500000000276415101701376022313 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class uvm_object; endclass class uvm_callback; endclass class uvm_callbacks #(type T=uvm_object, type CB=uvm_callback); bit m_registered = 1; virtual function bit m_is_registered(uvm_object obj, uvm_callback cb); if (m_is_for_me(cb) && m_am_i_a(obj)) begin return m_registered; end endfunction virtual function bit m_is_for_me(uvm_callback cb); CB this_cb; // verilator lint_off WIDTHTRUNC return ($cast(this_cb, cb)); // verilator lint_on WIDTHTRUNC endfunction virtual function bit m_am_i_a(uvm_object obj); T this_t; // verilator lint_off WIDTHTRUNC return ($cast(this_t, obj)); // verilator lint_on WIDTHTRUNC endfunction endclass class my_object extends uvm_object; endclass class my_callback extends uvm_callback; endclass class other_object extends uvm_object; endclass module t; initial begin my_object obj; other_object oobj; my_callback cb; uvm_callbacks#(my_object, my_callback) ucs; bit i; obj = new; oobj = new; cb = new; ucs = new; i = ucs.m_is_registered(obj, cb); if (i !== 1) $stop; i = ucs.m_is_registered(oobj, cb); if (i !== 0) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_typedef_no_bad.out0000644000542200017500000000036315101701376023106 0ustar mahmoudyfreeshell%Error: t/t_typedef_no_bad.v:10:4: Can't find typedef/interface: 'sometype' 10 | sometype p; | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_force_immediate_release.v0000644000542200017500000000122415101701376024413 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module t; reg [2:0] a = 3'b000; initial begin a = 3'b001; `checkh(a, 1); force a = 3'b010; `checkh(a, 2); a = 3'b011; `checkh(a, 2); release a; `checkh(a, 2); a = 3'b100; `checkh(a, 4); $finish; end endmodule verilator-5.042/test_regress/t/t_vpi_package.v0000644000542200017500000000213015101701376022045 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2010 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import "DPI-C" context function int mon_check(); parameter int dollarUnitInt = 3; package somepackage; parameter int someInt = 5; parameter int anotherInt = 6; endpackage module t (/*AUTOARG*/ ); parameter int someOtherInt = 7; parameter int yetAnotherInt = 9; parameter int stillAnotherInt = 17; parameter int register = 0; parameter int n_str = 2; // Edge case with pvi code generation parameter string someString [n_str] = '{default: ""}; logic reference; integer status; initial begin status = mon_check(); if (status!=0) begin $write("%%Error: t_vpi_package.cpp:%0d: C Test failed\n", status); $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule : t verilator-5.042/test_regress/t/t_package_abs.v0000644000542200017500000000153215101701376022021 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // see bug491 package functions; function real abs (real num); abs = (num <0) ? -num : num; endfunction function real neg (real num); return -abs(num); // Check package funcs can call package funcs endfunction endpackage module t (); import functions::*; localparam P = 1; generate if (P == 1) begin initial begin if (abs(-2.1) != 2.1) $stop; if (abs(2.2) != 2.2) $stop; if (neg(-2.1) != -2.1) $stop; if (neg(2.2) != -2.2) $stop; $write("*-* All Finished *-*\n"); $finish; end end endgenerate endmodule verilator-5.042/test_regress/t/t_interface_virtual_param.py0000755000542200017500000000073415101701376024660 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_param_pattern_init_scope.py0000755000542200017500000000073415101701376025043 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_range_negative_bad.v0000644000542200017500000000076415101701376024421 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; int array_bad[0]; // <--- Error: Must be positive size int array2_bad[-1]; // <--- Error: Must be positive size localparam X = 32'bz; logic [X:0] x; // <--- Error: X range sub #(1) u_sub(); endmodule module sub #(parameter SIZE=0); int ignore[SIZE]; endmodule verilator-5.042/test_regress/t/t_flag_werror_bad3.py0000755000542200017500000000114215101701376023166 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_flag_werror.v" test.lint(fails=True, verilator_flags=["-cc -Werror-NOSUCHERRORASTHIS"], expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_preproc_eof2_bad.out0000644000542200017500000000031415101701376023333 0ustar mahmoudyfreeshell%Error: t/t_preproc_eof2_bad.v:10:1: Unterminated ( in define formal arguments. ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_semaphore.py0000755000542200017500000000077715101701376021764 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary -Wall"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_typedef_package.v0000644000542200017500000000073515101701376022720 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by Driss Hafdi. // SPDX-License-Identifier: CC0-1.0 package pkg1; typedef logic [7:0] uint8_t; endpackage package pkg2; typedef enum pkg1::uint8_t { a = 8'd1, b = 8'd2 } opts; endpackage module t; initial begin $display("%d", pkg2::a); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_assert_disable_bad.py0000755000542200017500000000102215101701376023553 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert'], fails=True) test.passes() verilator-5.042/test_regress/t/t_tri_gate_bufif0_pins_inout.py0000755000542200017500000000141215101701376025264 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_tri_gate.cpp" test.top_filename = "t/t_tri_gate.v" test.compile(make_top_shell=False, make_main=False, v_flags2=['+define+T_BUFIF0'], make_flags=['CPPFLAGS_ADD=-DT_BUFIF0'], verilator_flags2=["--exe --pins-inout-enables", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_cmpconst_bad.v0000644000542200017500000000051515101701376023263 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Test of select from constant // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; bit [2:0] uns; initial begin uns = 1; if (uns > 3'b111) $stop; end endmodule verilator-5.042/test_regress/t/t_interface_typo_bad.py0000755000542200017500000000123715101701376023612 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint( fails=True, # Used to be %Error: t/t_order_wireloop.v:\d+: Wire inputs its own output, creating circular logic .wire x=x. # However we no longer gate optimize this expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_unpacked_struct_eq.py0000755000542200017500000000077115101701376023656 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--binary']) test.execute() test.passes() verilator-5.042/test_regress/t/t_emit_accessors.cpp0000644000542200017500000000146515101701376023126 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include VM_PREFIX_INCLUDE int main(int argc, char* argv[]) { Verilated::debug(0); Verilated::commandArgs(argc, argv); VM_PREFIX* topp = new VM_PREFIX; CData small_in1 = 0; CData small_in2 = 1; IData big_in = 0xffffffff; topp->in1(small_in1); topp->in2(small_in2); topp->in3(big_in); topp->in4(big_in); topp->eval(); assert(topp->out1() == 0); assert(topp->out2() == 0xffffffff); assert(topp->out3().at(0) == 1); topp->final(); VL_DO_DANGLING(delete topp, topp); } verilator-5.042/test_regress/t/t_process_rand.py0000755000542200017500000000076115101701376022454 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_param_width_loc_bad.out0000644000542200017500000000107015101701376024102 0ustar mahmoudyfreeshell%Warning-WIDTHTRUNC: t/t_param_width_loc_bad.v:20:21: Operator VAR 'PARAM' expects 1 bits on the Initial value, but Initial value's CONST '32'h0' generates 32 bits. : ... note: In instance 't.test_i' 20 | parameter logic PARAM = 1'b0 | ^~~~~ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_gate_lvalue_const.v0000644000542200017500000000273015101701376023300 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Driss Hafdi. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk, rst ); input clk; input rst; logic [2:0] ctrl_inc_single; logic [2:0] ctrl_inc_double; logic [2:0] cnt_single; always_ff @(posedge clk) begin if (rst) begin cnt_single <= '0; end else if (ctrl_inc_single != '0 && cnt_single != '1) begin cnt_single <= cnt_single + 1'd1; end end logic [2:0] cnt_double; always_ff @(posedge clk) begin if (rst) begin cnt_double <= '0; end else if (ctrl_inc_double != '0 && cnt_double != '1) begin cnt_double <= cnt_double + 1'd1; end end always_comb ctrl_inc_single = '0; always_comb ctrl_inc_double = '0; testMod test_i (.data_i(cnt_single)); testMod test_j (.data_i(cnt_double)); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule module testMod (input wire [2:0] data_i); typedef logic [63:0] time_t; // verilator lint_off MULTIDRIVEN time_t [2:0] last_transition; // verilator lint_on MULTIDRIVEN genvar b; generate for (b = 0; b <= 2; b++) begin : gen_trans always_ff @(posedge data_i[b] or negedge data_i[b]) begin last_transition[b] <= $time; end end endgenerate endmodule verilator-5.042/test_regress/t/t_flag_lib.v0000644000542200017500000000037615101701376021345 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; liblib_a a (); endmodule verilator-5.042/test_regress/t/t_pp_lib.py0000755000542200017500000000077515101701376021244 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(v_flags2=['-v', 't/t_pp_lib_library.v']) test.execute() test.passes() verilator-5.042/test_regress/t/t_class_static_method.v0000644000542200017500000000202315101701376023611 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls; static task static_task(int x); $write("Called static task: %d\n", x); if (x != 16) $stop; endtask static function int static_function(int x); $write("Called static function: %d\n", x); if (x != 23) $stop; return 42; endfunction endclass : Cls class OCls; int i; static function OCls create(); OCls o = new; o.i = 42; return o; endfunction static task test_obj(OCls o); if (o.i != 42) $stop; endtask endclass module t; initial begin int x; OCls oc; Cls::static_task(16); x = Cls::static_function(23); $write("Static function result: %d\n", x); if (x != 42) $stop; oc = OCls::create(); OCls::test_obj(oc); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_nba_assign_on_rhs.py0000755000542200017500000000072615101701376023447 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_order_doubleloop.py0000755000542200017500000000077115101701376023332 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["-fno-dfg"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_gen_for.py0000755000542200017500000000073415101701376021411 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_sys_psprintf.v0000644000542200017500000000130115101701376022336 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; // Note $sformatf already tested elsewhere reg [3:0] n; reg [63:0] q; reg [16*8:1] wide; string str; initial begin n = 4'b1100; q = 64'h1234_5678_abcd_0123; wide = "hello-there12345"; str = $psprintf("n=%b q=%d w=%s", n, q, wide); `ifdef TEST_VERBOSE $display("str=%0s",str); `endif if (str !== "n=1100 q= 1311768467750060323 w=hello-there12345") $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_interface_wire_bad.v0000644000542200017500000000054015101701376023373 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface Ifc; endinterface module Sub; Ifc a(); endmodule module t; Sub sub(); // Issue #5649 wire wbad = sub.a; endmodule verilator-5.042/test_regress/t/t_func_call_order.v0000644000542200017500000000174515101701376022730 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t; int a; function int assign5; a = 5; return 5; endfunction function int assign3; a = 3; return 3; endfunction function int incr; a++; return a; endfunction function int assign5_return_arg(int x); a = 5; return x; endfunction int i; initial begin a = 1; i = assign5() + assign3() + incr(); `checkd(a, 4); `checkd(i, 12); a = 1; i = assign5_return_arg(assign3()+incr()); `checkd(a, 5); `checkd(i, 7); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_flag_values_deprecated.out0000644000542200017500000000062215101701376024612 0ustar mahmoudyfreeshell%Warning-DEPRECATED: Option --threads 0 is deprecated, use '--threads 1' instead ... For warning description see https://verilator.org/warn/DEPRECATED?v=latest ... Use "/* verilator lint_off DEPRECATED */" and lint_on around source to disable this message. %Error-DEPRECATED: Option --no-threads is deprecated, use '--threads 1' instead %Error: Exiting due to verilator-5.042/test_regress/t/t_dpi_display.out0000644000542200017500000000051015101701376022437 0ustar mahmoudyfreeshelldpii_display_call: '' dpii_display_call: 'c' dpii_display_call: 'co' dpii_display_call: 'cons' dpii_display_call: 'constant' dpii_display_call: 'constant_value' one10=0000000a dpii_display_call: 'one10=0000000a' Mod=top.t 16= 10 10=0000000a dpii_display_call: 'Mod=top.t 16= 10 10=0000000a' *-* All Finished *-* verilator-5.042/test_regress/t/t_scheduling_initial_event.py0000755000542200017500000000077115101701376025032 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_math_shiftls.py0000755000542200017500000000077115101701376022460 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--binary']) test.execute() test.passes() verilator-5.042/test_regress/t/t_udp_sequential_bad.py0000755000542200017500000000076615101701376023627 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_clocking_timing.v0000644000542200017500000000510315101701376022737 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `timescale 10ns/1ns `ifdef TEST_VERBOSE `define WRITE_VERBOSE(args) $write args `else `define WRITE_VERBOSE(args) `endif `ifndef TEST_WIDTH `define TEST_WIDTH 4 `endif `ifndef TEST_BITS `define TEST_BITS 4*`TEST_WIDTH `endif `ifndef TEST_CLK_PERIOD `define TEST_CLK_PERIOD 10 `endif `ifndef TEST_INPUT_SKEW `define TEST_INPUT_SKEW 2 `endif `ifndef TEST_OUTPUT_SKEW `define TEST_OUTPUT_SKEW 6 `endif `ifndef TEST_CYCLE_DELAY `define TEST_CYCLE_DELAY 4 `endif module t; typedef logic[`TEST_BITS-1:0] sig_t; sig_t D, Q; always @(posedge clk) Q <= D; logic clk = 0; always #(`TEST_CLK_PERIOD/2) clk = ~clk; always @(posedge clk) `WRITE_VERBOSE(("[%0t] posedge clk\n", $time)); default clocking cb @(posedge clk); default input #`TEST_INPUT_SKEW output #`TEST_OUTPUT_SKEW; input Q; output D; endclocking `ifdef TEST_VERBOSE initial $monitor("[%0t] --> D=%x\t\tQ=%x\t\tcb.Q=%x", $time, D, Q, cb.Q); `endif always begin sig_t val; val = '0; cb.D <= val; for (int i = 0; i < 5; i++) begin ##(`TEST_CYCLE_DELAY+`TEST_OUTPUT_SKEW/`TEST_CLK_PERIOD+1) val = {`TEST_WIDTH{(`TEST_BITS/`TEST_WIDTH)'('ha + i)}}; `WRITE_VERBOSE(("[%0t] cb.D <= ##%0d %x\n", $time, `TEST_CYCLE_DELAY, val)); cb.D <= ##(`TEST_CYCLE_DELAY) val; fork #(`TEST_CYCLE_DELAY*`TEST_CLK_PERIOD+`TEST_OUTPUT_SKEW-0.1) begin if (D == val) begin `WRITE_VERBOSE(("[%0t] D == %x == %x\n", $time, D, val)); $stop; end if (cb.Q != D) begin `WRITE_VERBOSE(("[%0t] cb.Q == %x != %x\n", $time, cb.Q, D)); $stop; end end #(`TEST_CYCLE_DELAY*`TEST_CLK_PERIOD+`TEST_OUTPUT_SKEW+0.1) begin if (D != val) begin `WRITE_VERBOSE(("[%0t] D == %x != %x\n", $time, D, val)); $stop; end if (cb.Q == D) begin `WRITE_VERBOSE(("[%0t] cb.Q == %x == %x\n", $time, cb.Q, D)); $stop; end end join_none end ##4 $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_package_import_bad2.v0000644000542200017500000000054315101701376023457 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package Pkg1; endpackage package Pkg10; // verilator lint_off PKGNODECL import Pkg1b::*; // BAD - typo in package name endpackage module t; endmodule verilator-5.042/test_regress/t/t_randomize_union_bad.py0000755000542200017500000000076615101701376024005 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_display_esc_bad.v0000644000542200017500000000046015101701376022705 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin $display("\x\y\z"); // Illegal escapes end endmodule verilator-5.042/test_regress/t/t_math_vliw.py0000755000542200017500000000073415101701376021764 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_assoc_wildcard_map.v0000644000542200017500000000127115101701376023417 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); module t; initial begin int res[]; int a [*] = '{1: 100, 2: 200, 3: 300}; // TODO results not known to be correct res = a.map(el) with (el == 2); `checkh(res.size, 3); `checkh(res[0], 0); `checkh(res[1], 1); `checkh(res[2], 0); end endmodule verilator-5.042/test_regress/t/t_type_expression_compare.py0000755000542200017500000000073415101701376024740 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_assigndly_deep_ref_array.v0000644000542200017500000000372415101701376024632 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 interface Iface; bit clk; int x[2:0]; clocking cb @(posedge clk); default input #0 output #0; inout x; endclocking endinterface class Foo; virtual Iface iface; int index = 0; function new(virtual Iface tmp); iface = tmp; endfunction task update(virtual Iface tmp); iface = tmp; endtask task update_index(int i); index = i; endtask endclass class Bar; Foo foo; function new(Foo tmp); foo = tmp; endfunction task update(Foo tmp); foo = tmp; endtask task assignment(); foo.iface.cb.x[foo.index] <= 8; endtask endclass module t; Iface iface(); Iface iface2(); task clockSome(); #2; iface.clk = ~iface.clk; iface2.clk = ~iface2.clk; #2; iface.clk = ~iface.clk; iface2.clk = ~iface2.clk; endtask initial begin Foo foo = new(iface); Foo foo2 = new(iface2); Bar bar = new(foo); clockSome(); if (iface.x[0] != 0) $stop; if (iface.x[1] != 0) $stop; if (iface2.x[0] != 0) $stop; if (iface2.x[1] != 0) $stop; bar.assignment(); clockSome(); if (iface.x[0] != 8) $stop; if (iface.x[1] != 0) $stop; if (iface2.x[0] != 0) $stop; if (iface2.x[1] != 0) $stop; foo.update_index(1); clockSome(); if (iface.x[0] != 8) $stop; if (iface.x[1] != 0) $stop; if (iface2.x[0] != 0) $stop; if (iface2.x[1] != 0) $stop; foo.update(iface2); clockSome(); if (iface.x[0] != 8) $stop; if (iface.x[1] != 0) $stop; if (iface2.x[0] != 0) $stop; if (iface2.x[1] != 0) $stop; bar.update(foo2); clockSome(); if (iface.x[0] != 8) $stop; if (iface.x[1] != 0) $stop; if (iface2.x[0] != 0) $stop; if (iface2.x[1] != 0) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_randomize_method_types_unsup.v0000644000542200017500000000155115101701376025610 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Foo; rand int x; endclass class Cls; rand int assocarr[string]; rand int dynarr[][]; rand int q[$]; rand Cls cls; rand int i; rand Foo foo; rand int y; int st; constraint dynsize { dynarr.size < 20; dynarr.size > 0; dynarr[1].size < 10; } constraint statedep { i < st + 2; } constraint q_size_elem { q.size < 5; q[i] < 10; } constraint global_constraint { foo.x < y; } endclass module t; Cls obj; int res; initial begin obj = new; obj.foo = new; res = obj.randomize(); res = obj.randomize() with { dynarr.size > 2; }; end endmodule verilator-5.042/test_regress/t/t_math_trig.v0000644000542200017500000001361015101701376021557 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; real r, r2; integer cyc = 0; task check(integer line, real got, real ex); if (got != ex) begin if ((got > ex ? got - ex : ex - got) > 0.000001) begin $display("%%Error: Line %0d: Bad result, got=%0.99g expect=%0.99g",line,got,ex); $stop; end end endtask initial begin // Check constant propagation // Note $abs is not defined in SystemVerilog (as of 2012) check(`__LINE__, $ceil(-1.2), -1); check(`__LINE__, $ceil(1.2), 2); check(`__LINE__, $exp(1.2), 3.3201169227365472380597566370852291584014892578125); check(`__LINE__, $exp(0.0), 1); check(`__LINE__, $exp(-1.2), 0.301194211912202136627314530414878390729427337646484375); check(`__LINE__, $floor(-1.2), -2); check(`__LINE__, $floor(1.2), 1); check(`__LINE__, $ln(1.2), 0.1823215567939545922460098381634452380239963531494140625); //check(`__LINE__, $ln(0), 0); // Bad value //check(`__LINE__, $ln(-1.2), 0); // Bad value check(`__LINE__, $log10(1.2), 0.07918124604762481755226843915806966833770275115966796875); //check(`__LINE__, $log10(0), 0); // Bad value //check(`__LINE__, $log10(-1.2), 0); check(`__LINE__, $pow(2.3,1.2), 2.71689843249914897427288451581262052059173583984375); check(`__LINE__, $pow(2.3,-1.2), 0.368066758785732861536388327294844202697277069091796875); //check(`__LINE__, $pow(-2.3,1.2),0); // Bad value check(`__LINE__, $sqrt(1.2), 1.095445115010332148841598609578795731067657470703125); //check(`__LINE__, $sqrt(-1.2), 0); // Bad value check(`__LINE__, ((1.5)**(1.25)), 1.660023); check(`__LINE__, $acos (0.2), 1.369438406); // Arg1 is -1..1 check(`__LINE__, $acosh(1.2), 0.622362503); check(`__LINE__, $asin (0.2), 0.201357920); // Arg1 is -1..1 check(`__LINE__, $asinh(1.2), 1.015973134); check(`__LINE__, $atan (0.2), 0.197395559); check(`__LINE__, $atan2(0.2,2.3), 0.086738338); // Arg1 is -1..1 check(`__LINE__, $atanh(0.2), 0.202732554); // Arg1 is -1..1 check(`__LINE__, $cos (1.2), 0.362357754); check(`__LINE__, $cosh (1.2), 1.810655567); check(`__LINE__, $hypot(1.2,2.3), 2.594224354); check(`__LINE__, $sin (1.2), 0.932039085); check(`__LINE__, $sinh (1.2), 1.509461355); check(`__LINE__, $tan (1.2), 2.572151622); check(`__LINE__, $tanh (1.2), 0.833654607); end real sum_ceil; real sum_exp; real sum_floor; real sum_ln; real sum_log10; real sum_pow1; real sum_pow2; real sum_sqrt; real sum_acos; real sum_acosh; real sum_asin; real sum_asinh; real sum_atan; real sum_atan2; real sum_atanh; real sum_cos ; real sum_cosh; real sum_hypot; real sum_sin; real sum_sinh; real sum_tan; real sum_tanh; // Test loop always @ (posedge clk) begin r = $itor(cyc)/10.0 - 5.0; // Crosses 0 `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d r=%g s_ln=%0.12g\n", $time, cyc, r, sum_ln); `endif cyc <= cyc + 1; if (cyc==0) begin end else if (cyc<90) begin // Setup sum_ceil += 1.0+$ceil(r); sum_exp += 1.0+$exp(r); sum_floor += 1.0+$floor(r); if (r > 0.0) sum_ln += 1.0+$ln(r); if (r > 0.0) sum_log10 += 1.0+$log10(r); // Pow requires if arg1<0 then arg1 integral sum_pow1 += 1.0+$pow(2.3,r); if (r >= 0.0) sum_pow2 += 1.0+$pow(r,2.3); if (r >= 0.0) sum_sqrt += 1.0+$sqrt(r); if (r>=-1.0 && r<=1.0) sum_acos += 1.0+$acos (r); if (r>=1.0) sum_acosh += 1.0+$acosh(r); if (r>=-1.0 && r<=1.0) sum_asin += 1.0+$asin (r); sum_asinh += 1.0+$asinh(r); sum_atan += 1.0+$atan (r); if (r>=-1.0 && r<=1.0) sum_atan2 += 1.0+$atan2(r,2.3); if (r>=-1.0 && r<=1.0) sum_atanh += 1.0+$atanh(r); sum_cos += 1.0+$cos (r); sum_cosh += 1.0+$cosh (r); sum_hypot += 1.0+$hypot(r,2.3); sum_sin += 1.0+$sin (r); sum_sinh += 1.0+$sinh (r); sum_tan += 1.0+$tan (r); sum_tanh += 1.0+$tanh (r); end else if (cyc==99) begin check (`__LINE__, sum_ceil, 85); check (`__LINE__, sum_exp, 608.06652950); check (`__LINE__, sum_floor, 4); check (`__LINE__, sum_ln, 55.830941633); check (`__LINE__, sum_log10, 46.309585076); check (`__LINE__, sum_pow1, 410.98798177); check (`__LINE__, sum_pow2, 321.94765689); check (`__LINE__, sum_sqrt, 92.269677253); check (`__LINE__, sum_acos, 53.986722862); check (`__LINE__, sum_acosh, 72.685208498); check (`__LINE__, sum_asin, 21); check (`__LINE__, sum_asinh, 67.034973416); check (`__LINE__, sum_atan, 75.511045389); check (`__LINE__, sum_atan2, 21); check (`__LINE__, sum_atanh, 0); check (`__LINE__, sum_cos, 72.042023124); check (`__LINE__, sum_cosh, 1054.0178222); check (`__LINE__, sum_hypot, 388.92858406); check (`__LINE__, sum_sin, 98.264184989); check (`__LINE__, sum_sinh, -356.9512927); check (`__LINE__, sum_tan, 1.7007946043); check (`__LINE__, sum_tanh, 79.003199681); $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_pp_recursedef_bad.v0000644000542200017500000000047315101701376023240 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; `define RECURSE `RECURSE `RECURSE initial $stop; // Should have failed endmodule verilator-5.042/test_regress/t/t_class_packed.py0000755000542200017500000000073415101701376022406 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_array_method_map.py0000755000542200017500000000105515101701376023302 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) if not test.vlt_all: test.execute() test.passes() verilator-5.042/test_regress/t/t_unpack_array_direct_assignment.py0000755000542200017500000000105715101701376026232 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_unpack_array_no_expand.v" test.compile(verilator_flags2=['-fno-expand']) test.execute() test.passes() verilator-5.042/test_regress/t/t_array_method_bad.v0000644000542200017500000000052715101701376023070 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; initial begin int q[5]; q.mex; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_gen_cond_bitrange_bad.out0000644000542200017500000000255215101701376024403 0ustar mahmoudyfreeshell%Warning-SELRANGE: t/t_gen_cond_bitrange_bad.v:58:38: Selection index out of range: 2:2 outside 1:0 : ... note: In instance 't.i_test_gen' 58 | if ((g < (SIZE + 1)) && MASK[g]) begin | ^ ... For warning description see https://verilator.org/warn/SELRANGE?v=latest ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Warning-SELRANGE: t/t_gen_cond_bitrange_bad.v:70:32: Selection index out of range: 2:2 outside 1:0 : ... note: In instance 't.i_test_gen' 70 | if ((g < SIZE) && MASK[g + 1]) begin | ^ %Warning-SELRANGE: t/t_gen_cond_bitrange_bad.v:83:33: Selection index out of range: 2:2 outside 1:0 : ... note: In instance 't.i_test_gen' 83 | if ((g < (SIZE)) & MASK[g]) begin | ^ %Warning-SELRANGE: t/t_gen_cond_bitrange_bad.v:96:35: Selection index out of range: 2:2 outside 1:0 : ... note: In instance 't.i_test_gen' 96 | if (!((g >= SIZE) | ~MASK[g])) begin | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_clocking_xref.py0000755000542200017500000000077115101701376022610 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_past_bad.v0000644000542200017500000000102515101701376021353 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs d, clk, num ); input d; input clk; input int num; always @ (posedge clk) begin if ($past(d, num)) $stop; // IEEE 16.9.3 must be const if ($past(d, 0)) $stop; // IEEE 16.9.3 must be >= 0 if ($past(d, 10000)) $stop; // TICKCOUNT end endmodule verilator-5.042/test_regress/t/t_nonsequential_udp.py0000755000542200017500000000073415101701376023527 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_null_struct.v0000644000542200017500000000145315101701376023346 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls; endclass : Cls typedef struct { Cls obj; int number; } str_t; module t; function automatic str_t func_null(); return '{null, 42}; endfunction function automatic str_t func_obj(); Cls c; c = new; return '{c, 43}; endfunction initial begin str_t result; result = func_null(); if (result.obj != null) $stop; if (result.number != 42) $stop; result = func_obj(); if (result.obj == null) $stop; if (result.number != 43) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_langext_1_bad.out0000644000542200017500000000070215101701376022631 0ustar mahmoudyfreeshell%Error: t/t_langext_1.v:44:7: syntax error, unexpected IDENTIFIER-for-type 44 | genvar i; | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_langext_1.v:51:1: syntax error, unexpected endmodule, expecting '(' 51 | endmodule | ^~~~~~~~~ %Error: Cannot continue ... This fatal error may be caused by the earlier error(s); resolve those first. verilator-5.042/test_regress/t/t_randstate_seed_bad.py0000755000542200017500000000077215101701376023567 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_implements_noinherit_bad.v0000644000542200017500000000064115101701376024643 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface class Icls; localparam IP = 1; typedef int i_t; endclass class Cls implements Icls; function void f; $display(IP); // Bad endfunction endclass module t; Cls c; endmodule verilator-5.042/test_regress/t/t_class_copy2.py0000755000542200017500000000073415101701376022213 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_dynarray_method_bad.v0000644000542200017500000000260115101701376023576 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); module t; string s[] = { "hello", "sad", "sad", "world" }; initial begin int i; bit b; i = s.sum with (item.len); `checkh(i, 10); i = s.product with (item.len); `checkh(i, 24); b = s.sum with (item == "hello"); `checkh(b, 1'b1); b = s.sum with (item == ""); `checkh(b, 1'b0); b = s.product with (item inside {"hello", "sad"}); `checkh(b, 1'b0); b = s.product with (item inside { "hello", "sad", "world" }); `checkh(b, 1'b1); b = s.unknown_bad; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_flag_define.py0000755000542200017500000000123115101701376022206 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') # We also test +librescan and +notimingchecks here, which are NOPs test.compile(v_flags2=[ "-f t/t_flag_define.vc -DCMD_DEF -DCMD_UNDEF -UCMD_UNDEF +define+CMD_DEF2", "+librescan", "+notimingchecks" ]) test.execute() test.passes() verilator-5.042/test_regress/t/t_with_suggest_bad.py0000755000542200017500000000107615101701376023314 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--lint-only --language 1800-2017"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_implicitstatic_bad.v0000644000542200017500000000120615101701376024455 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( input clk ); initial begin int static_ok = 1; // Obvious as is in initial end always @(posedge clk) begin int implicit_warn = 1; // <--- Warning: IMPLICITSTATIC end function int f_implicit_static(); int cnt = 0; // <--- Warning: IMPLICIT STATIC return ++cnt; endfunction task f_implicit_static(); int cnt = 0; // <--- Warning: IMPLICIT STATIC ++cnt; endtask endmodule verilator-5.042/test_regress/t/t_math_real_round.v0000644000542200017500000000557215101701376022754 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `define is_near_real(a,b) (( ((a)<(b)) ? (b)-(a) : (a)-(b)) < (((a)/(b))*0.0001)) `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; real r; reg [31:0] v32; reg [63:0] v64; reg [95:0] v96; initial begin // verilator lint_off REALCVT v32 = -1.5; v64 = -1.5; v96 = -1.5; // verilator lint_on REALCVT `checkh(v32, 32'hfffffffe); `checkh(v64, 64'hfffffffffffffffe); `checkh(v96, 96'hfffffffffffffffffffffffe); // verilator lint_off REALCVT v32 = 12456789012345678912345.5; v64 = 12456789012345678912345.5; v96 = 12456789012345678912345.5; // verilator lint_on REALCVT `checkh(v32, 32'he5400000); `checkh(v64, 64'h48acb7d4e5400000); `checkh(v96, 96'h000002a348acb7d4e5400000); // verilator lint_off REALCVT v32 = -12456789012345678912345.5; v64 = -12456789012345678912345.5; v96 = -12456789012345678912345.5; // verilator lint_on REALCVT `checkh(v32, 32'h1ac00000); `checkh(v64, 64'hb753482b1ac00000); `checkh(v96, 96'hfffffd5cb753482b1ac00000); end // Test loop always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 10) begin r <= 0; end else if (cyc == 11) begin // verilator lint_off REALCVT v32 = r; v64 = r; v96 = r; // verilator lint_on REALCVT `checkh(v32, '0); `checkh(v64, '0); `checkh(v96, '0); end else if (cyc == 20) begin r <= -5.24567; end else if (cyc == 21) begin // verilator lint_off REALCVT v32 = r; v64 = r; v96 = r; // verilator lint_on REALCVT `checkh(v32, 32'hfffffffb); `checkh(v64, 64'hfffffffffffffffb); `checkh(v96, 96'hfffffffffffffffffffffffb); end else if (cyc == 30) begin r <= 12456789012345678912345.5; end else if (cyc == 31) begin // verilator lint_off REALCVT v32 = r; v64 = r; v96 = r; // verilator lint_on REALCVT `checkh(v32, 32'he5400000); `checkh(v64, 64'h48acb7d4e5400000); `checkh(v96, 96'h000002a348acb7d4e5400000); end else if (cyc == 99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_trace_two_portfst_cc.out0000644000542200017500000000364715101701376024371 0ustar mahmoudyfreeshell$date Sat Mar 30 14:08:31 2024 $end $version fstWriter $end $timescale 1ps $end $scope module topa $end $var wire 1 ! clk $end $scope module t $end $var wire 1 ! clk $end $var integer 32 " cyc [31:0] $end $var integer 32 # c_trace_on [31:0] $end $scope module sub $end $var integer 32 $ inside_sub_a [31:0] $end $upscope $end $upscope $end $upscope $end $scope module topb $end $var wire 1 % clk $end $scope module t $end $var wire 1 % clk $end $var integer 32 & cyc [31:0] $end $var integer 32 ' c_trace_on [31:0] $end $var real 64 ( r $end $scope module sub $end $var integer 32 ) inside_sub_a [31:0] $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #10 $dumpvars b00000000000000000000000000000010 ) r0 ( b00000000000000000000000000000000 ' b00000000000000000000000000000001 & 1% b00000000000000000000000000000001 $ b00000000000000000000000000000000 # b00000000000000000000000000000001 " 1! $end #15 0! 0% #20 1% 1! b00000000000000000000000000000010 " b00000000000000000000000000000011 # r0.1 ( #25 0! 0% #30 1% 1! r0.2 ( b00000000000000000000000000000100 # b00000000000000000000000000000011 " #35 0! 0% #40 1% 1! b00000000000000000000000000000100 " b00000000000000000000000000000101 # r0.3 ( #45 0! 0% #50 1% 1! r0.4 ( b00000000000000000000000000000110 # b00000000000000000000000000000101 " #55 0! 0% #60 1% 1! b00000000000000000000000000000110 " b00000000000000000000000000000111 # r0.5 ( #65 0! 0% #70 1% 1! r0.6 ( b00000000000000000000000000001000 # b00000000000000000000000000000111 " #75 0! 0% #80 1% 1! b00000000000000000000000000001000 " b00000000000000000000000000001001 # r0.7 ( #85 0! 0% #90 1% 1! r0.7999999999999999 ( b00000000000000000000000000001010 # b00000000000000000000000000001001 " #95 0! 0% #100 1% 1! b00000000000000000000000000001010 " b00000000000000000000000000001011 # r0.8999999999999999 ( #105 0! 0% #110 1% 1! r0.9999999999999999 ( b00000000000000000000000000001100 # b00000000000000000000000000001011 " verilator-5.042/test_regress/t/t_func_real_abs.py0000755000542200017500000000073415101701376022555 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_mem_trace_split.py0000755000542200017500000000131115101701376023131 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--trace-vcd", "--trace-structs", "--output-split-ctrace", "32"]) if test.vlt_all: test.file_grep_count(test.obj_dir + "/V" + test.name + "__Trace__0.cpp", r'void Vt.*trace_chg_.*sub.*{', 3) test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_comb_bad.v0000644000542200017500000000051715101701376022357 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; always_comb @(*) begin $stop; end endmodule verilator-5.042/test_regress/t/t_select_bad_range.py0000755000542200017500000000077615101701376023241 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_inst_mnpipe.py0000755000542200017500000000073415101701376022317 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_queue_assignment.py0000755000542200017500000000073415101701376023346 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_sys_writemem.gold7.mem0000644000542200017500000000010015101701376023642 0ustar mahmoudyfreeshell000 000 000 000 654 000 000 000 000 000 65a 65b 65c 000 000 000 verilator-5.042/test_regress/t/t_vpi_public_depthn_3.out0000644000542200017500000000025315101701376024062 0ustar mahmoudyfreeshell scopesDump: SCOPE 0x#: top.TOP SCOPE 0x#: top.t SCOPE 0x#: top.t.s_axis_if SCOPE 0x#: top.t.u_dut SCOPE 0x#: top.t.u_dut.u_sub *-* All Finished *-* verilator-5.042/test_regress/t/t_vlcov_data_d.dat0000644000542200017500000000007715101701376022534 0ustar mahmoudyfreeshell# SystemC::Coverage-3 C 'CoverPoint6ffile1.sphl159' 12 verilator-5.042/test_regress/t/t_lint_unsigned_bad.v0000644000542200017500000000051015101701376023244 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Test of select from constant // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; bit [2:0] uns; initial begin uns = 1; if (uns < 0) $stop; end endmodule verilator-5.042/test_regress/t/t_flag_topmodule_inline.py0000755000542200017500000000104615101701376024326 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile( # This also tests --top as opposed to --top-module v_flags2=["--top b"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_dpi_display_bad.py0000755000542200017500000000076315101701376023103 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_mod_interface_array5.v0000644000542200017500000000620215101701376023662 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) interface intf (); integer value; endinterface module fanout #(parameter int N = 1) ( intf upstream, intf downstream[N-1:0] ); genvar i; for (i = 0; i < N; i = i + 1) assign downstream[i].value = upstream.value; endmodule module xbar ( input logic clk, input int cyc, intf Masters[1:0] ); localparam NUM_DEMUX_OUT = 2 * 4; localparam NUM_MUX_IN = 2 * 4; intf demuxOut[NUM_DEMUX_OUT-1:0](); intf muxIn[NUM_MUX_IN-1:0](); //fan out master connections to the crossbar matrix fanout #(.N(4)) fanout_inst0 (.upstream(Masters[0]), .downstream(demuxOut[3:0])); fanout #(.N(4)) fanout_inst1 (.upstream(Masters[1]), .downstream(demuxOut[7:4])); //the crossbar matrix assignments, done as 1D arrays because verilator doesn't currently support >1D arrays of interfaces genvar slv, mst; for (slv = 0; slv < 4; slv = slv + 1) begin for (mst = 0; mst < 2; mst = mst + 1) begin localparam int muxIdx = (slv*2)+mst; localparam int demuxIdx = slv+(mst*4); assign muxIn[muxIdx].value = demuxOut[demuxIdx].value; end end always @(posedge clk) begin if (cyc == 5) begin `checkh(Masters[0].value, 2); `checkh(Masters[1].value, 1); // The first 4 demuxOut values should have the value of the first Master `checkh(demuxOut[0].value, Masters[0].value); `checkh(demuxOut[1].value, Masters[0].value); `checkh(demuxOut[2].value, Masters[0].value); `checkh(demuxOut[3].value, Masters[0].value); // The next 4 demuxOut values should have the value of the second Master `checkh(demuxOut[4].value, Masters[1].value); `checkh(demuxOut[5].value, Masters[1].value); `checkh(demuxOut[6].value, Masters[1].value); `checkh(demuxOut[7].value, Masters[1].value); // Each 2 mux inputs should have one input from each master, in order from low to high `checkh(muxIn[0].value, Masters[0].value); `checkh(muxIn[1].value, Masters[1].value); `checkh(muxIn[2].value, Masters[0].value); `checkh(muxIn[3].value, Masters[1].value); `checkh(muxIn[4].value, Masters[0].value); `checkh(muxIn[5].value, Masters[1].value); `checkh(muxIn[6].value, Masters[0].value); `checkh(muxIn[7].value, Masters[1].value); $write("*-* All Finished *-*\n"); $finish; end end endmodule module t ( clk ); input clk; intf masters[1:0](); int cyc; xbar sub (.clk, .cyc, .Masters(masters)); always @(posedge clk) begin cyc <= cyc + 1; if (cyc == 1) begin masters[0].value <= 2; masters[1].value <= 1; end end endmodule verilator-5.042/test_regress/t/t_packed_concat_bad.out0000644000542200017500000000233315101701376023527 0ustar mahmoudyfreeshell%Warning-WIDTHCONCAT: t/t_packed_concat_bad.v:12:47: Unsized numbers/parameters not allowed in replications. : ... note: In instance 't' 12 | localparam bit_int_t [1:0] count_bits = {2{$bits(count_t)}}; | ^~~~~ ... For warning description see https://verilator.org/warn/WIDTHCONCAT?v=latest ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message. %Warning-WIDTHCONCAT: t/t_packed_concat_bad.v:13:46: Unsized numbers/parameters not allowed in concatenations. : ... note: In instance 't' 13 | localparam bit_int_t [1:0] count_bitsc = {$bits(count_t), $bits(count_t)}; | ^~~~~ %Warning-WIDTHCONCAT: t/t_packed_concat_bad.v:13:60: Unsized numbers/parameters not allowed in replications. : ... note: In instance 't' 13 | localparam bit_int_t [1:0] count_bitsc = {$bits(count_t), $bits(count_t)}; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_mem_multi_io2.cpp0000644000542200017500000000403715101701376022662 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2008 by Lane Brooks. // SPDX-License-Identifier: CC0-1.0 #include VM_PREFIX_INCLUDE VM_PREFIX* tb = nullptr; bool pass = true; double sc_time_stamp() { return 0; } void check(const char* bus, int got, int exp) { if (got != exp) { VL_PRINTF("%%Error: Data mismatch on '%s', got=%x, exp=%x\n", bus, got, exp); pass = false; } } #ifdef SYSTEMC_VERSION int sc_main(int, char**) #else int main() #endif { Verilated::debug(0); tb = new VM_PREFIX{"tb"}; #ifdef SYSTEMC_VERSION using namespace sc_core; sc_signal i3; sc_signal o3; sc_signal i34[4]; sc_signal o34[4]; sc_signal i345[4][5]; sc_signal o345[4][5]; tb->i3(i3); tb->o3(o3); for (int i = 0; i < 4; i++) { tb->i34[i](i34[i]); tb->o34[i](o34[i]); for (int j = 0; j < 5; j++) { tb->i345[i][j](i345[i][j]); tb->o345[i][j](o345[i][j]); } } #endif // loop through every possibility and check the result // clang-format off #ifdef SYSTEMC_VERSION sc_start(1, SC_NS); # define ASSIGN(s, v) s.write(v) # define READ(s) s.read() #else tb->eval(); # define ASSIGN(s, v) tb->s = (v) # define READ(s) tb->s #endif // clang-format on ASSIGN(i3, 13); for (int i = 0; i < 4; i++) { ASSIGN(i34[i], i); for (int j = 0; j < 5; j++) ASSIGN(i345[i][j], i * 8 + j); } #ifdef SYSTEMC_VERSION sc_start(1, SC_NS); #else tb->eval(); #endif check("o3", READ(o3), 13); for (int i = 0; i < 4; i++) { check("o34", READ(o34[i]), i); for (int j = 0; j < 5; j++) check("o345", READ(o345[i][j]), i * 8 + j); } tb->final(); VL_DO_DANGLING(delete tb, tb); if (pass) { VL_PRINTF("*-* All Finished *-*\n"); } else { vl_fatal(__FILE__, __LINE__, "top", "Unexpected results from test\n"); } return 0; } verilator-5.042/test_regress/t/t_event_control_scope_var.py0000755000542200017500000000101715101701376024707 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['-fno-inline', '-Wno-WIDTHTRUNC']) test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_contassreg_bad.out0000644000542200017500000000062515101701376024151 0ustar mahmoudyfreeshell%Error-CONTASSREG: t/t_lint_contassreg_bad.v:14:11: Continuous assignment to reg, perhaps intended wire (IEEE 1364-2005 6.1; Verilog only, legal in SV): 'r' : ... note: In instance 't' 14 | assign r = 1'b0; | ^ ... For error description see https://verilator.org/warn/CONTASSREG?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_string_type_methods_bad.v0000644000542200017500000000067715101701376024512 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; string s; integer i; // Check constification initial begin s="1234"; i = s.len(0); // BAD s.itoa; // BAD s.itoa(1,2,3); // BAD s.bad_no_such_method(); // BAD end endmodule verilator-5.042/test_regress/t/t_tri_gate.v0000644000542200017500000000220315101701376021373 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2008 by Lane Brooks. // SPDX-License-Identifier: CC0-1.0 module top (input SEL, input[1:0] A, output W, output X, output Y, output Z); mux mux2 (.A(A), .SEL(SEL), .Z(W)); pass mux1 (.A(A), .SEL(SEL), .Z(X)); tbuf mux0[1:0] (.A(A), .OE({SEL,!SEL}), .Z(Y)); assign Z = ( SEL) ? A[1] : 1'bz; tbuf tbuf (.A(A[0]), .OE(!SEL), .Z(Z)); endmodule module pass (input[1:0] A, input SEL, output Z); tbuf tbuf1 (.A(A[1]), .OE(SEL), .Z(Z)); tbuf tbuf0 (.A(A[0]), .OE(!SEL),.Z(Z)); endmodule module tbuf (input A, input OE, output Z); `ifdef T_BUFIF0 bufif0 (Z, A, !OE); `elsif T_BUFIF1 bufif1 (Z, A, OE); `elsif T_NOTIF0 notif0 (Z, !A, !OE); `elsif T_NOTIF1 notif1 (Z, !A, OE); `elsif T_PMOS pmos (Z, A, !OE); `elsif T_NMOS nmos (Z, A, OE); `elsif T_COND assign Z = (OE) ? A : 1'bz; `else `error "Unknown test name" `endif endmodule module mux (input[1:0] A, input SEL, output Z); assign Z = (SEL) ? A[1] : 1'bz; assign Z = (!SEL)? A[0] : 1'bz; assign Z = 1'bz; endmodule verilator-5.042/test_regress/t/t_sarif.sarif.out0000644000542200017500000002770015101701376022357 0ustar mahmoudyfreeshell{ "$schema": "https://json.schemastore.org/sarif-2.1.0-rtm.5.json", "version": "###", "runs": [ { "tool": { "driver": { "name": "Verilator", "version": "###", "informationUri": "https://verilator.org", "rules": [ { "id": "MODDUP", "helpUri": "https://verilator.org/warn/MODDUP?v=latest" }, { "id": "MULTIDRIVEN", "helpUri": "https://verilator.org/warn/MULTIDRIVEN?v=latest" }, { "id": "WIDTHTRUNC", "helpUri": "https://verilator.org/warn/WIDTHTRUNC?v=latest" } ] } }, "invocations": [ { "commandLine": "--prefix Vt_sarif -cc -Mdir obj_vlt/t_sarif --fdedup --debug-check --comp-limit-members 10 --x-assign unique -Wno-fatal --diagnostics-sarif --no-skip-identical -f input.vc +define+TEST_OBJ_DIR=obj_vlt/t_sarif +define+TEST_DUMPFILE=obj_vlt/t_sarif/simx.vcd t/t_sarif.v +librescan +notimingchecks +libext+.v -y t +incdir+t", "executionSuccessful": true } ], "results": [ { "level": "warning", "message": { "text": "Duplicate declaration of module: 't'\n... Location of original declaration\n... For warning description see https://verilator.org/warn/MODDUP?v=latest\n... Use \"/* verilator lint_off MODDUP */\" and lint_on around source to disable this message.", "markdown": "```\n%Warning-MODDUP: t/t_sarif.v:21:8: Duplicate declaration of module: 't'\n 21 | module t; \n | ^\n t/t_sarif.v:7:8: ... Location of original declaration\n 7 | module t(\n | ^\n ... For warning description see https://verilator.org/warn/MODDUP?v=latest\n ... Use \"/* verilator lint_off MODDUP */\" and lint_on around source to disable this message.\n\n```\n" }, "locations": [ { "physicalLocation": { "artifactLocation": { "uri": "file:///.../t_sarif.v" }, "region": { "sourceLanguage": "systemverilog", "startLine": 21, "startColumn": 8, "endColumn": 9, "snippit": { "text": "module t;", "markdown": "```\n 21 | module t; \n | ^\n\n```\n" } } } } ], "relatedLocations": [ { "message": { "text": "... Location of original declaration\n... For warning description see https://verilator.org/warn/MODDUP?v=latest\n... Use \"/* verilator lint_off MODDUP */\" and lint_on around source to disable this message.", "markdown": "```\n t/t_sarif.v:7:8: ... Location of original declaration\n 7 | module t(\n | ^\n ... For warning description see https://verilator.org/warn/MODDUP?v=latest\n ... Use \"/* verilator lint_off MODDUP */\" and lint_on around source to disable this message.\n\n```\n" }, "physicalLocation": { "artifactLocation": { "uri": "file:///.../t_sarif.v" }, "region": { "sourceLanguage": "systemverilog", "startLine": 7, "startColumn": 8, "endColumn": 9, "snippit": { "text": "module t(", "markdown": "```\n 7 | module t(\n | ^\n\n```\n" } } } } ], "ruleId": "MODDUP", "ruleIndex": 0 }, { "level": "warning", "message": { "text": "Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's CONST '5'h1f' generates 5 bits.\n... note: In instance 't'\n... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest\n... Use \"/* verilator lint_off WIDTHTRUNC */\" and lint_on around source to disable this message.", "markdown": "```\n%Warning-WIDTHTRUNC: t/t_sarif.v:12:23: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's CONST '5'h1f' generates 5 bits.\n : ... note: In instance 't'\n 12 | wire [1:0] trunced = 5'b11111; \n | ^\n ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest\n ... Use \"/* verilator lint_off WIDTHTRUNC */\" and lint_on around source to disable this message.\n\n```\n" }, "locations": [ { "physicalLocation": { "artifactLocation": { "uri": "file:///.../t_sarif.v" }, "region": { "sourceLanguage": "systemverilog", "startLine": 12, "startColumn": 23, "endColumn": 24, "snippit": { "text": " wire [1:0] trunced = 5'b11111;", "markdown": "```\n 12 | wire [1:0] trunced = 5'b11111; \n | ^\n\n```\n" } } } } ], "ruleId": "WIDTHTRUNC", "ruleIndex": 2 }, { "level": "warning", "message": { "text": "Signal has multiple driving blocks with different clocking: 'multidriven'\n... Location of first driving block\n... Location of other driving block\n... For warning description see https://verilator.org/warn/MULTIDRIVEN?v=latest\n... Use \"/* verilator lint_off MULTIDRIVEN */\" and lint_on around source to disable this message.", "markdown": "```\n%Warning-MULTIDRIVEN: t/t_sarif.v:10:18: Signal has multiple driving blocks with different clocking: 'multidriven'\n t/t_sarif.v:15:6: ... Location of first driving block\n 15 | multidriven <= '1;\n | ^~~~~~~~~~~\n t/t_sarif.v:17:6: ... Location of other driving block\n 17 | multidriven <= '0;\n | ^~~~~~~~~~~\n ... For warning description see https://verilator.org/warn/MULTIDRIVEN?v=latest\n ... Use \"/* verilator lint_off MULTIDRIVEN */\" and lint_on around source to disable this message.\n\n```\n" }, "locations": [ { "physicalLocation": { "artifactLocation": { "uri": "file:///.../t_sarif.v" }, "region": { "sourceLanguage": "systemverilog", "startLine": 10, "startColumn": 18, "endColumn": 29, "snippit": { "text": " output logic multidriven);", "markdown": "```\n 10 | output logic multidriven);\n | ^~~~~~~~~~~\n\n```\n" } } } } ], "relatedLocations": [ { "message": { "text": "... Location of first driving block", "markdown": "```\n t/t_sarif.v:15:6: ... Location of first driving block\n 15 | multidriven <= '1;\n | ^~~~~~~~~~~\n\n```\n" }, "physicalLocation": { "artifactLocation": { "uri": "file:///.../t_sarif.v" }, "region": { "sourceLanguage": "systemverilog", "startLine": 15, "startColumn": 6, "endColumn": 17, "snippit": { "text": " multidriven <= '1;", "markdown": "```\n 15 | multidriven <= '1;\n | ^~~~~~~~~~~\n\n```\n" } } } }, { "message": { "text": "... Location of other driving block\n... For warning description see https://verilator.org/warn/MULTIDRIVEN?v=latest\n... Use \"/* verilator lint_off MULTIDRIVEN */\" and lint_on around source to disable this message.", "markdown": "```\n t/t_sarif.v:17:6: ... Location of other driving block\n 17 | multidriven <= '0;\n | ^~~~~~~~~~~\n ... For warning description see https://verilator.org/warn/MULTIDRIVEN?v=latest\n ... Use \"/* verilator lint_off MULTIDRIVEN */\" and lint_on around source to disable this message.\n\n```\n" }, "physicalLocation": { "artifactLocation": { "uri": "file:///.../t_sarif.v" }, "region": { "sourceLanguage": "systemverilog", "startLine": 17, "startColumn": 6, "endColumn": 17, "snippit": { "text": " multidriven <= '0;", "markdown": "```\n 17 | multidriven <= '0;\n | ^~~~~~~~~~~\n\n```\n" } } } } ], "ruleId": "MULTIDRIVEN", "ruleIndex": 1 } ] } ] } verilator-5.042/test_regress/t/t_assoc_nokey_bad.v0000644000542200017500000000106215101701376022722 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias' // // Simple bi-directional alias test. // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin int dict[string] = '{1, 2}; int dict2[string] = '{3: 4}; // Legal due to value-to-string conversion $display("dict=%p", dict); $display("dict2=%p", dict2); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_param_real.v0000644000542200017500000000117015101701376021702 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Johan Bjork // SPDX-License-Identifier: CC0-1.0 module mod #( parameter real HZ = 0 ); //verilator no_inline_module initial begin if ((HZ-$floor(HZ)) - 0.45 > 0.01) $stop; if ((HZ-$floor(HZ)) - 0.45 < -0.01) $stop; end endmodule module t(); mod #(.HZ(123.45)) mod1(); mod #(.HZ(24.45)) mod2(); initial begin if (mod1.HZ != 123.45) $stop; if (mod2.HZ != 24.45) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_flag_topmodule.py0000755000542200017500000000076215101701376022774 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(v_flags2=["--top-module b "]) test.execute() test.passes() verilator-5.042/test_regress/t/t_queue_insert_at_end.py0000755000542200017500000000073415101701376024014 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_event_class_fire.out0000644000542200017500000000053315101701376023456 0ustar mahmoudyfreeshell%Error: Internal Error: t/t_event_class_fire.v:10:7: ../V3Delayed.cpp:#: No active to handle FireEvent : ... note: In instance '$unit::Cls' 10 | ->> e; | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. verilator-5.042/test_regress/t/t_fuzz_always_bad.v0000644000542200017500000000041215101701376022761 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 //bug1577 module t; always @ c.a c:h; endmodule verilator-5.042/test_regress/t/t_pp_resetall_bad.v0000644000542200017500000000043615101701376022723 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `resetall // Ok module t; `resetall // Bad endmodule `resetall // Ok verilator-5.042/test_regress/t/t_flag_decoration.v0000644000542200017500000000035215101701376022720 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; endmodule verilator-5.042/test_regress/t/t_trace_enum_saif.out0000644000542200017500000000135015101701376023265 0ustar mahmoudyfreeshell// Generated by verilated_saif (SAIFILE (SAIFVERSION "2.0") (DIRECTION "backward") (PROGRAM_NAME "Verilator") (DIVIDER / ) (TIMESCALE 1ps) (DURATION 10) (INSTANCE top (NET (clk (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) ) (INSTANCE t (NET (clk (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_enumed\[0\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[1\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_other_enumed\[0\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_other_enumed\[1\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE sink (NET (state\[0\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (state\[1\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) ) verilator-5.042/test_regress/t/t_flag_output_groups_bad.out0000644000542200017500000000024615101701376024702 0ustar mahmoudyfreeshell%Error: --output-groups must be >= -1: -2 ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_var_const_bad.py0000755000542200017500000000076615101701376022603 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_unpacked_concat_bad.py0000755000542200017500000000076315101701376023723 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lib_prot_comb.v0000644000542200017500000000272715101701376022422 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by Yutetsu TAKATSUKASA. // SPDX-License-Identifier: CC0-1.0 `ifdef PROCESS_TOP `define CHECK if (out0 != (in0 ^ in1) || out1 != (in0 | in1) || out2__under != (in0 & in1)) begin \ $display("Mismatch in0:%b in1:%b out0:%b out1:%b out2:%b", in0, in1, out0, out1, out2__under); \ $stop; \ end module t (/*AUTOARG*/ // Inputs clk ); input clk; logic in0, in1; logic out0, out1, out2__under; logic [31:0] count = 0; // actually XOR and OR and AND secret i_secret(.in0(in0), .in1(in1), .out0(out0), .out1(out1), .out2__under(out2__under)); always @(posedge clk) begin count <= count + 32'd1; if (count == 32'd1) begin in0 <= 1'b0; in1 <= 1'b0; end else if (count == 32'd2) begin `CHECK in0 <= 1'b1; in1 <= 1'b0; end else if (count == 32'd3) begin `CHECK in0 <= 1'b0; in1 <= 1'b1; end else if (count == 32'd4) begin `CHECK in0 <= 1'b1; in1 <= 1'b1; end else if (count == 32'd5) begin `CHECK $write("*-* All Finished *-*\n"); $finish; end end endmodule `else module secret(input in0, input in1, output out0, output out1, output out2__under); assign out0 = in0 ^ in1; assign out1 = in0 | in1; assign out2__under = in0 & in1; endmodule `endif verilator-5.042/test_regress/t/t_time_vpi_1us1ns.out0000644000542200017500000000170615101701376023174 0ustar mahmoudyfreeshell:: In top.t Time scale of t is 1us / 1ns [60000] time%0d=60 123%0t=123000 dig%0t=5432110000 dig%0d=5432110 rdig%0t=5432109877 rdig%0f=5432109.876543 acc%0t=12345678901234567890000 acc%0d=12345678901234567890 [60000.000000ns] time%0d=60 123%0t=123000.000000ns dig%0t=5432110000.000000ns dig%0d=5432110 rdig%0t=5432109876.543210ns rdig%0f=5432109.876543 acc%0t=12345678901234567890000.000000ns acc%0d=12345678901234567890 [60000.000000ns] stime%0t=60000.000000ns stime%0d=60 stime%0f=60.000000 [60000.000000ns] rtime%0t=60000.000000ns rtime%0d=60 rtime%0f=60.000000 global svGetTime = 0 0,60000 global svGetTimeUnit = 0 -6 svGetTmePrecision = 0 -9 global vpiSimTime = 0,60000 vpiScaledRealTime = 60000 global vpiTimeUnit = -6 vpiTimePrecision = -9 top.t svGetTime = 0 0,60000 top.t svGetTimeUnit = 0 -6 svGetTmePrecision = 0 -9 top.t vpiSimTime = 0,60000 vpiScaledRealTime = 60 top.t vpiTimeUnit = -6 vpiTimePrecision = -9 *-* All Finished *-* verilator-5.042/test_regress/t/t_cover_sys_unsup.py0000755000542200017500000000077315101701376023243 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_param_concat_bad.py0000755000542200017500000000103715101701376023224 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.top_filename = "t/t_param_concat.v" test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dpi_result_type.cpp0000644000542200017500000001764515101701376023345 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2020 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "svdpi.h" #include #include #include // clang-format off #if defined(VERILATOR) // Verilator # include "Vt_dpi_result_type__Dpi.h" typedef long long sv_longint_t; typedef unsigned long long sv_longint_unsigned_t; # define NO_SHORTREAL #elif defined(VCS) // VCS # include "../vc_hdrs.h" typedef long long sv_longint_t; typedef unsigned long long sv_longint_unsigned_t; # define NO_REAL_EXPORT #elif defined(NCSC) // NC # include "dpi-exp.h" # include "dpi-imp.h" typedef long long sv_longint_t; typedef unsigned long long sv_longint_unsigned_t; # define NO_STRUCT_OR_UNION # define NO_SHORTREAL #elif defined(MS) // ModelSim # include "dpi.h" typedef int64_t sv_longint_t; typedef uint64_t sv_longint_unsigned_t; # define NO_STRUCT_OR_UNION # define NO_ARRAY #else # error "Unknown simulator for DPI test" #endif // clang-format on //====================================================================== // Implementations of imported functions //====================================================================== // Basic types as per IEEE 1800-2023 35.5.5 void i_void() { static int n = 0; printf("i_void %d\n", n); n++; } char i_byte() { static int n = 0; return 10 - n++; } unsigned char i_byte_unsigned() { static int n = 0; return 20 - n++; } short i_shortint() { static int n = 0; return 30 - n++; } unsigned short i_shortint_unsigned() { static int n = 0; return 40 - n++; } int i_int() { static int n = 0; return 50 - n++; } unsigned i_int_unsigned() { static int n = 0; return 60 - n++; } sv_longint_t i_longint() { static int n = 0; return 70 - n++; } sv_longint_unsigned_t i_longint_unsigned() { static int n = 0; return 80 - n++; } double i_real() { static int n = 0; return (-2.0 * n++ - 1.0) / 2.0; } #ifndef NO_SHORTREAL float i_shortreal() { static int n = 0; return (-4.0f * n++ - 1.0f) / 4.0f; } #endif void* i_chandle() { static int n = 0; printf("i_chandle %d\n", n); return (n++ % 2) ? reinterpret_cast(&i_chandle) : NULL; } const char* i_string() { static int n = 0; printf("i_string %d\n", n); return (n++ % 2) ? "Hello" : "World"; } svBit i_bit() { static int n = 0; printf("i_bit %d\n", n); return !(n++ % 2); } svLogic i_logic() { static int n = 0; printf("i_logic %d\n", n); return n++ % 2; } // Basic types via typedefs char i_byte_t() { static int n = 0; const char r = 10 - n; n += 2; return r; } unsigned char i_byte_unsigned_t() { static int n = 0; const unsigned char r = 20 - n; n += 2; return r; } short i_shortint_t() { static int n = 0; const short r = 30 - n; n += 2; return r; } unsigned short i_shortint_unsigned_t() { static int n = 0; const unsigned short r = 40 - n; n += 2; return r; } int i_int_t() { static int n = 0; const int r = 50 - n; n += 2; return r; } unsigned i_int_unsigned_t() { static int n = 0; const unsigned r = 60 - n; n += 2; return r; } sv_longint_t i_longint_t() { static int n = 0; const sv_longint_t r = 70 - n; n += 2; return r; } sv_longint_unsigned_t i_longint_unsigned_t() { static int n = 0; const sv_longint_unsigned_t r = 80 - n; n += 2; return r; } double i_real_t() { static int n = 0; const double r = (-2.0 * n - 1.0) / 2.0; n += 2; return r; } #ifndef NO_SHORTREAL float i_shortreal_t() { static int n = 0; const float r = (-4.0f * n - 1.0f) / 4.0f; n += 2; return r; } #endif void* i_chandle_t() { static int n = 0; printf("i_chandle_t %d\n", n); return (n++ % 2) ? reinterpret_cast(&i_chandle) : NULL; } const char* i_string_t() { static int n = 0; printf("i_string_t %d\n", n); return (n++ % 2) ? "Hello" : "World"; } svBit i_bit_t() { static int n = 0; printf("i_bit_t %d\n", n); return !(n++ % 2); } svLogic i_logic_t() { static int n = 0; printf("i_logic_t %d\n", n); return n++ % 2; } #ifndef NO_ARRAY // 2-state packed arrays of width <= 32 svBitVecVal i_array_2_state_1() { static int n = 0; printf("i_array_2_state_1 %d\n", n); return !(n++ % 2); } svBitVecVal i_array_2_state_32() { static int n = 0; printf("i_array_2_state_32 %d\n", n); return 0xffffffffU << n++; } #endif #ifndef NO_STRUCT_OR_UNION // 2-state packed structures of width <= 32 svBitVecVal i_struct_2_state_1() { static int n = 0; printf("i_struct_2_state_1 %d\n", n); return !(n++ % 2); } svBitVecVal i_struct_2_state_32() { static int n = 0; printf("i_struct_2_state_32 %d\n", n); return 0xffffffffU << n++; } // 2-state packed unions of width <= 32 svBitVecVal i_union_2_state_1() { static int n = 0; printf("i_union_2_state_1 %d\n", n); return !(n++ % 2); } svBitVecVal i_union_2_state_32() { static int n = 0; printf("i_union_2_state_32 %d\n", n); return 0xffffffffU << n++; } #endif //====================================================================== // Check exported functions //====================================================================== #define stop() \ do { \ printf(__FILE__ ":%d Bad value\n", __LINE__); \ abort(); \ } while (0) void check_exports() { static int n = 0; e_void(); // Basic types as per IEEE 1800-2023 35.5.5 if (e_byte() != 10 + n) stop(); if (e_byte_unsigned() != 20 + n) stop(); if (e_shortint() != 30 + n) stop(); if (e_shortint_unsigned() != 40 + n) stop(); if (e_int() != 50 + n) stop(); if (e_int_unsigned() != 60 + n) stop(); if (e_longint() != 70 + n) stop(); if (e_longint_unsigned() != 80 + n) stop(); #ifndef NO_REAL_EXPORT if (e_real() != 1.0 * n + 0.5) stop(); #endif #ifndef NO_SHORTREAL if (e_shortreal() != 1.0f * n + 0.25f) stop(); #endif if (e_chandle()) stop(); if ((n % 2) == 0) { if (std::strcmp(e_string(), "Hello") != 0) stop(); } else { if (std::strcmp(e_string(), "World") != 0) stop(); } if (e_bit() != (n % 2)) stop(); if (e_logic() != !(n % 2)) stop(); // Basic types via tyepdef if (e_byte_t() != 10 + 2 * n) stop(); if (e_byte_unsigned_t() != 20 + 2 * n) stop(); if (e_shortint_t() != 30 + 2 * n) stop(); if (e_shortint_unsigned_t() != 40 + 2 * n) stop(); if (e_int_t() != 50 + 2 * n) stop(); if (e_int_unsigned_t() != 60 + 2 * n) stop(); if (e_longint_t() != 70 + 2 * n) stop(); if (e_longint_unsigned_t() != 80 + 2 * n) stop(); #ifndef NO_REAL_EXPORT if (e_real_t() != 1.0 * (2 * n) + 0.5) stop(); #endif #ifndef NO_SHORTREAL if (e_shortreal_t() != 1.0f * (2 * n) + 0.25f) stop(); #endif if (e_chandle_t()) stop(); if ((n % 2) == 0) { if (std::strcmp(e_string_t(), "Hello") != 0) stop(); } else { if (std::strcmp(e_string_t(), "World") != 0) stop(); } if (e_bit_t() != (n % 2)) stop(); if (e_logic_t() != !(n % 2)) stop(); #ifndef NO_ARRAY // 2-state packed arrays of width <= 32 if (e_array_2_state_1() != (n % 2)) stop(); if (e_array_2_state_32() != 0xffffffff >> n) stop(); #endif #ifndef NO_STRUCT_OR_UNION // 2-state packed structures of width <= 32 if (e_struct_2_state_1() != (n % 2)) stop(); if (e_struct_2_state_32() != 0xffffffff >> n) stop(); // 2-state packed unions of width <= 32 if (e_union_2_state_1() != (n % 2)) stop(); if (e_union_2_state_32() != 0xffffffff >> n) stop(); #endif n++; } verilator-5.042/test_regress/t/t_enum_type_methods.py0000755000542200017500000000073415101701376023522 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_slice_cond_side_effect.v0000644000542200017500000000145015101701376024222 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 typedef int arr_t[3]; class Cls; int cnt; int init_depth; function arr_t get_arr(int depth); arr_t arr = (depth > 1) ? get_arr(depth - 1) : '{init_depth, init_depth * 2, init_depth * 3}; cnt++; return arr; endfunction endclass module t; Cls c = new; initial begin arr_t arr; c.init_depth = 5; arr = (c.init_depth > 0) ? c.get_arr(5) : '{1, 2, 3}; if (arr[0] != 5) $stop; if (arr[1] != 10) $stop; if (arr[2] != 15) $stop; if (c.cnt != 5) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_initial.py0000755000542200017500000000073415101701376021423 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_math_signed5_timing.py0000755000542200017500000000104215101701376023701 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_math_signed5.v" test.compile(verilator_flags2=['--binary']) test.execute() test.passes() verilator-5.042/test_regress/t/t_func_virt_new.py0000755000542200017500000000072315101701376022640 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint() test.compile() test.passes() verilator-5.042/test_regress/t/t_lint_defparam.v0000644000542200017500000000054115101701376022405 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; sub sub (); defparam sub.P = 2; endmodule module sub; parameter P = 6; if (P != 0) ; // Prevent unused endmodule verilator-5.042/test_regress/t/t_opt_table_real_off.py0000755000542200017500000000134415101701376023576 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.top_filename = 't/t_opt_table_real.v' test.golden_filename = 't/t_opt_table_real.out' test.compile(verilator_flags2=["--stats -fno-table"]) if test.vlt_all: test.file_grep_not(test.stats, r'Optimizations, Tables created\s+(\d+)') test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_pp_circ_subst_bad2.out0000644000542200017500000000050215101701376023666 0ustar mahmoudyfreeshell%Error: t/t_pp_circ_subst_bad.v:8:40002: Too many preprocessor tokens on a line (>20000); perhaps recursive `define ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_pp_circ_subst_bad.v:8:5: syntax error, unexpected IDENTIFIER-for-type %Error: Exiting due to verilator-5.042/test_regress/t/t_const_hi.py0000755000542200017500000000073415101701376021600 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_hier_block_import.py0000755000542200017500000000234515101701376023465 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') # stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. test.clean_objs() test.setenv('TEST_ROOT', test.t_dir + "/t_hier_block_import") # CI environment offers 2 VCPUs, 2 thread setting causes the following warning. # %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. # So use 6 threads here though it's not optimal in performance, but ok. test.compile(verilator_flags2=[ '$TEST_ROOT/t_hier_block_import_def.vh', '-f $TEST_ROOT/t_hier_block_import_args.f', '-I$TEST_ROOT' ], threads=(6 if test.vltmt else 1)) test.execute() test.file_grep(test.obj_dir + "/VsubA/subA.sv", r'^module\s+(\S+)\s+', "subA") test.file_grep(test.stats, r'HierBlock,\s+Hierarchical blocks\s+(\d+)', 2) test.passes() verilator-5.042/test_regress/t/t_pp_dupdef_pragma_bad.out0000644000542200017500000000260115101701376024244 0ustar mahmoudyfreeshell%Warning-REDEFMACRO: t/t_pp_dupdef_pragma_bad.v:11:19: Redefining existing define: 'DUP', with different value: 'b_bad' t/t_pp_dupdef_pragma_bad.v:11:19: ... Location of previous definition, with value: 'a' ... For warning description see https://verilator.org/warn/REDEFMACRO?v=latest ... Use "/* verilator lint_off REDEFMACRO */" and lint_on around source to disable this message. %Warning-REDEFMACRO: t/t_pp_dupdef_pragma_bad.v:16:19: Redefining existing define: 'DUP', with different value: 'd_bad' t/t_pp_dupdef_pragma_bad.v:16:19: ... Location of previous definition, with value: 'c_nowarn' %Warning-REDEFMACRO: t/t_pp_dupdef_pragma_bad.v:21:19: Redefining existing define: 'DUP', with different value: 'f_bad' t/t_pp_dupdef_pragma_bad.v:21:19: ... Location of previous definition, with value: 'e_nowarn' %Warning-REDEFMACRO: t/t_pp_dupdef_pragma_bad.v:26:19: Redefining existing define: 'DUP', with different value: 'k_bad' t/t_pp_dupdef_pragma_bad.v:26:19: ... Location of previous definition, with value: 'j_nowarn' %Warning-REDEFMACRO: t/t_pp_dupdef_pragma_bad.v:31:19: Redefining existing define: 'DUP', with different value: 'm_bad' t/t_pp_dupdef_pragma_bad.v:31:19: ... Location of previous definition, with value: 'l_nowarn' %Error: Exiting due to verilator-5.042/test_regress/t/t_infinite_recursion.v0000644000542200017500000000062115101701376023475 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class cls; task t; t; endtask task pre_randomize; t; endtask endclass module t; cls obj; task static t; int _ = obj.randomize() with {1 == 1;}; endtask endmodule verilator-5.042/test_regress/t/t_force_release.out0000644000542200017500000000016115101701376022736 0ustar mahmoudyfreeshell 0 d=0,e=0 10 d=1,e=1 20 d=1,e=0 %Error: t/t_force_release.v:36: got='h1 exp='h00000000 verilator-5.042/test_regress/t/t_timing_debug2.py0000755000542200017500000000135715101701376022513 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_timing_class.v" test.compile(verilator_flags2=["--exe --main --timing"]) test.execute(all_run_flags=["+verilator+debug"]) if not test.vltmt: # vltmt output may vary between thread exec order test.files_identical(test.obj_dir + "/vlt_sim.log", test.golden_filename, "logfile") test.passes() verilator-5.042/test_regress/t/t_altera_lpm_shiftreg.py0000755000542200017500000000111115101701376023773 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) test.compile(verilator_flags2=["--top-module", module]) test.passes() verilator-5.042/test_regress/t/t_class_param_unused_default.v0000644000542200017500000000077115101701376025161 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class Bar#(type T = int); T t; function new; t = new; endfunction endclass class Baz; int x = 1; endclass module t; initial begin Bar#(Baz) bar_baz = new; if (bar_baz.t.x != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_math_signed_calc.py0000755000542200017500000000073415101701376023236 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_flag_werror_bad1.out0000644000542200017500000000101215101701376023334 0ustar mahmoudyfreeshell%Warning-WIDTHTRUNC: t/t_flag_werror.v:10:19: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits. : ... note: In instance 't' 10 | wire [3:0] foo = 6'h2e; | ^ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_cover_trace_always.out0000644000542200017500000000172015101701376024016 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module t $end $var wire 1 $ p $end $var wire 1 % q $end $var wire 1 & r $end $var wire 32 ' vlCoverageLineTrace_t_cover_trace_always__24_block [31:0] $end $scope module dut $end $var wire 1 $ p $end $var wire 1 % q $end $var wire 1 & r $end $var wire 32 # vlCoverageLineTrace_t_cover_trace_always__12_block [31:0] $end $var wire 32 ( vlCoverageLineTrace_t_cover_trace_always__13_expr_0 [31:0] $end $var wire 32 ) vlCoverageLineTrace_t_cover_trace_always__13_expr_1 [31:0] $end $var wire 32 * vlCoverageLineTrace_t_cover_trace_always__13_expr_2 [31:0] $end $upscope $end $upscope $end $enddefinitions $end #0 b00000000000000000000000000000001 # 1$ 0% 1& b00000000000000000000000000000000 ' b00000000000000000000000000000000 ( b00000000000000000000000000000001 ) b00000000000000000000000000000000 * #1 b00000000000000000000000000000001 ' b00000000000000000000000000000011 ) verilator-5.042/test_regress/t/t_class_local.py0000755000542200017500000000073415101701376022251 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_math_pow4.v0000644000542200017500000000303115101701376021477 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014 by Clifford Wolf. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; wire [31:0] y; reg a; test004 sub (/*AUTOINST*/ // Outputs .y (y[31:0]), // Inputs .a (a)); // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d a=%x y=%x\n", $time, cyc, a, y); `endif cyc <= cyc + 1; if (cyc==0) begin a <= 0; end else if (cyc==1) begin a <= 1; if (y != 32'h0) $stop; end else if (cyc==2) begin if (y != 32'h010000ff) $stop; end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module test004(a, y); input a; output [31:0] y; wire [7:0] y0; wire [7:0] y1; wire [7:0] y2; wire [7:0] y3; assign y = {y0,y1,y2,y3}; localparam [7:0] V0 = +8'sd1 ** -8'sd2; //'h01 localparam [7:0] V1 = +8'sd2 ** -8'sd2; //'h00 localparam [7:0] V2 = -8'sd2 ** -8'sd3; //'h00 localparam [7:0] V3 = -8'sd1 ** -8'sd3; //'hff localparam [7:0] ZERO = 0; initial $display("V0=%x V1=%x V2=%x V3=%x", V0,V1,V2,V3); assign y0 = a ? V0 : ZERO; assign y1 = a ? V1 : ZERO; assign y2 = a ? V2 : ZERO; assign y3 = a ? V3 : ZERO; endmodule verilator-5.042/test_regress/t/t_dynarray_bad.out0000644000542200017500000000145115101701376022602 0ustar mahmoudyfreeshell%Warning-WIDTHTRUNC: t/t_dynarray_bad.v:15:11: Operator NEWDYNAMIC expects 32 bits on the new() size, but new() size's VARREF 's' generates 64 bits. : ... note: In instance 't' 15 | a = new [s]; | ^~~ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: Internal Error: t/t_dynarray_bad.v:15:16: ../V3Number.cpp:#: Number operation called with non-logic (double or string) argument: '"str"" 15 | a = new [s]; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. verilator-5.042/test_regress/t/t_inside2.v0000644000542200017500000000117415101701376021140 0ustar mahmoudyfreeshell// DESCRIPTION::Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; typedef struct packed { logic signed [63:0] b; } a_t; a_t a_r; a_t a_n; logic signed [63:0] b; logic res; assign b = a_r.b; always_comb begin a_n = a_r; res = '0; if (b inside {1, 2}) begin res = 1'b1; end end always_ff @(posedge clk) begin a_r <= a_n; end endmodule verilator-5.042/test_regress/t/t_alw_split.py0000755000542200017500000000112415101701376021762 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--stats"]) if test.vlt_all: test.file_grep(test.stats, r'Optimizations, Split always\s+(\d+)', 4) test.execute() test.passes() verilator-5.042/test_regress/t/t_var_nonamebegin.py0000755000542200017500000000117115101701376023120 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['-trace']) test.execute(expect_filename="t/" + test.name + "__log.out") if test.vlt_all: test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_preproc_eof_qqq_bad.out0000644000542200017500000000030315101701376024131 0ustar mahmoudyfreeshell%Error: t/t_preproc_eof_qqq_bad.v:10:1: EOF in unterminated """ string ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_timing_dpi_unsup.v0000644000542200017500000000215715101701376023162 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Toru Niina. // SPDX-License-Identifier: CC0-1.0 `ifdef TEST_VERBOSE `define WRITE_VERBOSE(msg) $write(msg) `else `define WRITE_VERBOSE(msg) `endif `default_nettype none `timescale 1ns/1ps module t; localparam cycle = 1000.0 / 100.0; localparam halfcycle = 0.5 * cycle; logic clk = '0; import "DPI-C" context task tb_c_wait(); export "DPI-C" task tb_sv_wait; task automatic tb_sv_wait(input int n); `WRITE_VERBOSE("tb_sv_wait start...\n"); repeat(n) @(negedge clk); `WRITE_VERBOSE("tb_sv_wait done!\n"); endtask always #halfcycle clk = ~clk; initial begin `WRITE_VERBOSE("test start\n"); repeat(10) @(posedge clk); `WRITE_VERBOSE("calling tb_c_wait...\n"); tb_c_wait(); `WRITE_VERBOSE("tb_c_wait finish\n"); repeat(10) @(posedge clk); $write("*-* All Finished *-*\n"); $finish; end initial #(cycle*30) $stop; // timeout endmodule verilator-5.042/test_regress/t/t_preproc.py0000755000542200017500000000432315101701376021442 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap import collections test.scenarios('vlt') def preproc_check(filename1, filename2): # Read line comments. line_checks = collections.deque() with open(filename1, 'r', encoding="latin-1", newline='\n') as fh: lineno = 0 for line in fh: lineno += 1 if re.match(r'^Line_Preproc_Check', line): line_checks.append(lineno) # See if output file agrees. with open(filename2, 'r', encoding="latin-1", newline='\n') as fh: lineno = 0 for line in fh: lineno += 1 m = re.match(r'^\`line\s+(\d+)', line) if m: lineno = int(m.group(1)) - 1 m = re.match(r'^Line_Preproc_Check\s+(\d+)', line) if m: linecmt = m.group(1) check = line_checks.popleft() file2ln = filename2 + ":" + str(lineno) if not check: test.error(file2ln + ": Extra Line_Preproc_Check") if str(linecmt) != str(check): test.error(file2ln + ": __LINE__ inserted " + str(linecmt) + ", exp=" + str(check)) if str(lineno) != str(check): test.error(file2ln + ": __LINE__ on `line " + str(lineno) + ", exp=" + str(check)) if len(line_checks): test.error(filename2 + ": Missing a Line_Preproc_Check") stdout_filename = test.obj_dir + "/" + test.name + "__test.vpp" test.compile(verilator_flags2=['-DDEF_A0 -DPREDEF_COMMAND_LINE -E'], verilator_make_gmake=False, make_top_shell=False, make_main=False, stdout_filename=stdout_filename) preproc_check(test.top_filename, stdout_filename) test.files_identical(stdout_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_trace_enum_fst.py0000755000542200017500000000150315101701376022763 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_enum.v" test.compile(verilator_flags2=['--cc --trace-fst --output-split-ctrace 1']) test.execute() test.fst_identical(test.trace_filename, test.golden_filename) # Five $attrbegin expected: # - state_t declaration # - t.v_enumed # - t.sink.state # - other_state_t declaration # - t.v_other_enumed test.file_grep_count(test.golden_filename, r'attrbegin', 5) test.passes() verilator-5.042/test_regress/t/t_enum_enumvalue_struct_bad.v0000644000542200017500000000141115101701376025034 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // See issue #2855 package Pkg; typedef enum int unsigned { MODE10 = 10 } mode_t; typedef struct packed { bit u; mode_t a; bit b; } foo_t; localparam foo_t FOO0 = '{a: 0, b: 1'b1, u: 1'b1}; localparam foo_t FOO1 = '{a: MODE10, b: 1'b1, u: 1'b1}; endpackage module t; initial begin //if (sum !== `EXPECTED_SUM) $stop; if (Pkg::FOO0 != {1'b1, 32'd0, 1'b1}) $stop; if (Pkg::FOO1 != {1'b1, 32'd10, 1'b1}) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_opt_expand_keep_widths.v0000644000542200017500000000260015101701376024325 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module gymhnulbvj (in5, clock_10, clock_12, out18); input wire [23:22] in5; wire [29:1] wire_4; reg reg_35; output wire out18; input wire clock_10; input wire clock_12; // verilator lint_off WIDTH assign wire_4 = ~ in5[22]; assign out18 = reg_35 ? 0 : !(!(~(wire_4[6:5] | 8'hc6))); // verilator lint_on WIDTH always @(posedge clock_10 or posedge clock_12) begin if (clock_12) begin reg_35 <= 0; end else begin // verilator lint_off WIDTH reg_35 <= wire_4; // verilator lint_on WIDTH end end endmodule module t; reg [23:22] in5; reg clock_10 = 0; reg clock_12 = 0; wire out18; gymhnulbvj uut ( .in5(in5), .clock_10(clock_10), .clock_12(clock_12), .out18(out18) ); initial begin $monitor("[%0t] in5=%d clock_10=%d clock_12=%d out18=%d", $time, in5, clock_10, clock_12, out18); in5 = 2'b00; #5 clock_12 = 1; #5 clock_12 = 0; #5 clock_10 = 1; #5 clock_10 = 0; #10; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_opt_redor.v0000644000542200017500000000410215101701376021572 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [15:0] in = crc[15:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out (out), // Inputs .in (in[15:0])); // Aggregate outputs into a single result vector wire [63:0] result = {63'h0, out}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc<10) begin sum <= '0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h162c58b1635b8d6e if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs out, // Inputs in ); input [15:0] in; output reg out; // TODO this should flatten into a reduction OR always_comb begin out = 0; for (int i=0; i<16; i=i+1) begin if (in[i]) begin out = 1; end end end endmodule verilator-5.042/test_regress/t/t_gate_ormux.v0000644000542200017500000002672115101701376021762 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; logic [31:0] rdata; logic [31:0] rdata2; wire [31:0] wdata = crc[31:0]; wire [15:0] sel = {11'h0, crc[36:32]}; wire we = crc[48]; Test test (/*AUTOINST*/ // Outputs .rdata (rdata[31:0]), .rdata2 (rdata2[31:0]), // Inputs .clk (clk), .we (we), .sel (sel[15:0]), .wdata (wdata[31:0])); // 5.07 4.42 -> 13% wire [63:0] result = {rdata2, rdata}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (rdata2 != rdata) $stop; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc<10) begin sum <= '0; end else if (cyc == 99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; `define EXPECTED_SUM 64'h8977713eb467bc86 if (sum !== `EXPECTED_SUM) $stop; end else if (cyc == `SIM_CYCLES) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test(/*AUTOARG*/ // Outputs rdata, rdata2, // Inputs clk, we, sel, wdata ); input clk; input we; input [15:0] sel; input [31:0] wdata; output logic [31:0] rdata; output logic [31:0] rdata2; logic we_d1r; logic [15:0] sel_d1r; logic [31:0] wdata_d1r; always_ff @ (posedge clk) begin we_d1r <= we; sel_d1r <= sel; wdata_d1r <= wdata; end reg [31:0] csr0000; reg [31:0] csr0001; reg [31:0] csr0002; reg [31:0] csr0003; reg [31:0] csr0004; reg [31:0] csr0005; reg [31:0] csr0006; reg [31:0] csr0007; reg [31:0] csr0008; reg [31:0] csr0009; reg [31:0] csr000a; reg [31:0] csr000b; reg [31:0] csr000c; reg [31:0] csr000d; reg [31:0] csr000e; reg [31:0] csr000f; wire [31:0] csr0010 = 32'h33675230; wire [31:0] csr0011 = 32'h00fa2144; wire [31:0] csr0012 = 32'h6a5e8e10; wire [31:0] csr0013 = 32'h000a5b5e; wire [31:0] csr0014 = 32'h002fe51b; wire [31:0] csr0015 = 32'h00027e00; wire [31:0] csr0016 = 32'h0000e3c0; wire [31:0] csr0017 = 32'h00efcf16; wire [31:0] csr0018 = 32'h007a2600; wire [31:0] csr0019 = 32'h0a4a9f10; wire [31:0] csr001a = 32'h7d789de3; wire [31:0] csr001b = 32'h40f655f9; wire [31:0] csr001c = 32'hadad01f4; wire [31:0] csr001d = 32'h02e7b33c; wire [31:0] csr001e = 32'h12101533; wire [31:0] csr001f = 32'h2cc1cce5; initial begin csr0000 = 32'he172d365; csr0001 = 32'h35cc25e2; csr0002 = 32'haf48436e; csr0003 = 32'h135e55e4; csr0004 = 32'h5fd6e48a; csr0005 = 32'hb07d34ad; csr0006 = 32'h2aa05deb; csr0007 = 32'hfe97b680; csr0008 = 32'h960f20bb; csr0009 = 32'h251129f0; csr000a = 32'hef3d2f93; csr000b = 32'hef4bc127; csr000c = 32'h3dfecb10; csr000d = 32'h1b4690f5; csr000e = 32'ha07822ab; csr000f = 32'hf817cbf6; end always_ff @ (posedge clk) begin if (we_d1r && sel_d1r == 16'h0000) csr0000 <= wdata_d1r; if (we_d1r && sel_d1r == 16'h0001) csr0001 <= wdata_d1r; if (we_d1r && sel_d1r == 16'h0002) csr0002 <= wdata_d1r; if (we_d1r && sel_d1r == 16'h0003) csr0003 <= wdata_d1r; if (we_d1r && sel_d1r == 16'h0004) csr0004 <= wdata_d1r; if (we_d1r && sel_d1r == 16'h0005) csr0005 <= wdata_d1r; if (we_d1r && sel_d1r == 16'h0006) csr0006 <= wdata_d1r; if (we_d1r && sel_d1r == 16'h0007) csr0007 <= wdata_d1r; if (we_d1r && sel_d1r == 16'h0008) csr0008 <= wdata_d1r; if (we_d1r && sel_d1r == 16'h0009) csr0009 <= wdata_d1r; if (we_d1r && sel_d1r == 16'h000a) csr000a <= wdata_d1r; if (we_d1r && sel_d1r == 16'h000b) csr000b <= wdata_d1r; if (we_d1r && sel_d1r == 16'h000c) csr000c <= wdata_d1r; if (we_d1r && sel_d1r == 16'h000d) csr000d <= wdata_d1r; if (we_d1r && sel_d1r == 16'h000e) csr000e <= wdata_d1r; if (we_d1r && sel_d1r == 16'h000f) csr000f <= wdata_d1r; end wire dec0000 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; wire dec0001 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; wire dec0002 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; wire dec0003 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; wire dec0004 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; wire dec0005 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; wire dec0006 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; wire dec0007 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; wire dec0008 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; wire dec0009 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; wire dec000a = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; wire dec000b = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; wire dec000c = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; wire dec000d = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; wire dec000e = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; wire dec000f = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; wire dec0010 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; wire dec0011 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; wire dec0012 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; wire dec0013 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; wire dec0014 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; wire dec0015 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; wire dec0016 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; wire dec0017 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; wire dec0018 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; wire dec0019 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; wire dec001a = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; wire dec001b = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; wire dec001c = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; wire dec001d = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; wire dec001e = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; wire dec001f = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; assign rdata = (32'h0 | {32{dec0000}} & csr0000 | {32{dec0001}} & csr0001 | {32{dec0002}} & csr0002 | {32{dec0003}} & csr0003 | {32{dec0004}} & csr0004 | {32{dec0005}} & csr0005 | {32{dec0006}} & csr0006 | {32{dec0007}} & csr0007 | {32{dec0008}} & csr0008 | {32{dec0009}} & csr0009 | {32{dec000a}} & csr000a | {32{dec000b}} & csr000b | {32{dec000c}} & csr000c | {32{dec000d}} & csr000d | {32{dec000e}} & csr000e | {32{dec000f}} & csr000f | {32{dec0010}} & csr0010 | {32{dec0011}} & csr0011 | {32{dec0012}} & csr0012 | {32{dec0013}} & csr0013 | {32{dec0014}} & csr0014 | {32{dec0015}} & csr0015 | {32{dec0016}} & csr0016 | {32{dec0017}} & csr0017 | {32{dec0018}} & csr0018 | {32{dec0019}} & csr0019 | {32{dec001a}} & csr001a | {32{dec001b}} & csr001b | {32{dec001c}} & csr001c | {32{dec001d}} & csr001d | {32{dec001e}} & csr001e | {32{dec001f}} & csr001f ); always_comb begin case (sel_d1r) 16'h0000: rdata2 = csr0000; 16'h0001: rdata2 = csr0001; 16'h0002: rdata2 = csr0002; 16'h0003: rdata2 = csr0003; 16'h0004: rdata2 = csr0004; 16'h0005: rdata2 = csr0005; 16'h0006: rdata2 = csr0006; 16'h0007: rdata2 = csr0007; 16'h0008: rdata2 = csr0008; 16'h0009: rdata2 = csr0009; 16'h000a: rdata2 = csr000a; 16'h000b: rdata2 = csr000b; 16'h000c: rdata2 = csr000c; 16'h000d: rdata2 = csr000d; 16'h000e: rdata2 = csr000e; 16'h000f: rdata2 = csr000f; 16'h0010: rdata2 = csr0010; 16'h0011: rdata2 = csr0011; 16'h0012: rdata2 = csr0012; 16'h0013: rdata2 = csr0013; 16'h0014: rdata2 = csr0014; 16'h0015: rdata2 = csr0015; 16'h0016: rdata2 = csr0016; 16'h0017: rdata2 = csr0017; 16'h0018: rdata2 = csr0018; 16'h0019: rdata2 = csr0019; 16'h001a: rdata2 = csr001a; 16'h001b: rdata2 = csr001b; 16'h001c: rdata2 = csr001c; 16'h001d: rdata2 = csr001d; 16'h001e: rdata2 = csr001e; 16'h001f: rdata2 = csr001f; default: rdata2 = 0; endcase end endmodule verilator-5.042/test_regress/t/t_wire_beh1800_bad.v0000644000542200017500000000146015101701376022504 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs o, oa, ro, roa, wo, woa, vo, voa ); wire w; reg r; output o; output [1:0] oa; output reg ro; output reg [1:0] roa; output wire wo; output wire [1:0] woa; // 1800 only output var vo; output var [1:0] voa; initial begin w = '0; // Error o = '0; // Error oa = '0; // Error wo = '0; // Error woa = '0; // Error r = '0; // Not an error ro = '0; // Not an error roa = '0; // Not an error vo = '0; // Not an error voa = '0; // Not an error end endmodule verilator-5.042/test_regress/t/t_hier_parm_under.py0000755000542200017500000000130415101701376023127 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') # stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. test.clean_objs() test.compile(verilator_flags2=['--stats', '--hierarchical']) test.execute() test.file_grep(test.stats, r'HierBlock,\s+Hierarchical blocks\s+(\d+)', 1) test.passes() verilator-5.042/test_regress/t/t_order_dpi_export_2.py0000755000542200017500000000105615101701376023561 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_param_type3.v0000644000542200017500000000200115101701376022015 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Iztok Jeras. // SPDX-License-Identifier: CC0-1.0 typedef logic T_t; module t (/*AUTOARG*/ // Outputs o, ob, o2, o2b, // Inputs i ); input T_t i; output T_t o, ob, o2, o2b; sub1 #(.T_t(T_t), .CHECK(1)) sub1 (.i, .o(o)); sub2 #(.T_t(T_t), .CHECK(2)) sub2 (.i, .o(o2)); sub1 #(T_t, 1) sub1b (i, ob); sub2 #(T_t, 2) sub2b (i, o2b); endmodule module sub1 (i,o); parameter type T_t = real; localparam type T2_t = T_t; parameter int CHECK = 0; input T_t i; output T2_t o; assign o = i; if (CHECK != 1) $error; endmodule module sub2 #( parameter type T_t = real, localparam type T2_t = T_t, parameter int CHECK = 0 ) ( input T_t i, output T_t o ); assign o = i; if (CHECK != 2) $error; endmodule // Local Variables: // verilog-typedef-regexp: "_t$" // End: verilator-5.042/test_regress/t/t_sequence_first_match_unsup.v0000644000542200017500000000446315101701376025234 0ustar mahmoudyfreeshell// (C) 2001-2020, Daniel Kroening, Edmund Clarke, // Computer Science Department, University of Oxford // Computer Science Department, Carnegie Mellon University // // All rights reserved. Redistribution and use in source and binary forms, with // or without modification, are permitted provided that the following // conditions are met: // // 1. Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. // // 3. Neither the name of the University nor the names of its contributors // may be used to endorse or promote products derived from this software // without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // // You can contact the author at: // - homepage : https://www.cprover.org/ebmc/ // - source repository : https://github.com/diffblue/hw-cbmc module main(input clk); reg [31:0] x = 0; always @(posedge clk) x<=x+1; // Starting from a particular state, // first_match yields the sequence that _ends_ first. // fails initial p0: assert property ((##1 1) or (##2 1) |-> x==1); // passes initial p1: assert property (first_match((##1 1) or (##2 1)) |-> x==1); // fails initial p2: assert property (1 or ##1 1 |-> x==0); // passes initial p3: assert property (first_match(1 or ##1 1) |-> x==0); endmodule verilator-5.042/test_regress/t/t_randomize_method.v0000644000542200017500000001135115101701376023131 0ustar mahmoudyfreeshell// DESCRIPTION: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define check_rand(cl, field) \ begin \ longint prev_result; \ int ok = 0; \ void'(cl.randomize()); \ prev_result = longint'(field); \ repeat(9) begin \ longint result; \ void'(cl.randomize()); \ result = longint'(field); \ if (result != prev_result) ok = 1; \ prev_result = result; \ end \ if (ok != 1) $stop; \ end typedef enum bit[15:0] { ONE = 3, TWO = 5, THREE = 8, FOUR = 13 } Enum; typedef struct packed { int a; bit b; Enum c; } StructInner; typedef struct packed { bit x; StructInner s; Enum y; longint z; } StructOuter; typedef struct { int i; StructOuter j; Enum k; longint z; } StructUnpacked; class BaseCls1; endclass class Inner; rand logic[7:0] a; rand logic[15:0] b; rand logic[3:0] c; rand logic[11:0] d; int e; function new; a = 0; b = 0; c = 0; d = 0; e = 0; endfunction endclass class DerivedCls1 extends BaseCls1; rand Inner i; rand int j; int k; rand Enum l; function new; i = new; j = 0; k = 0; l = ONE; endfunction endclass class BaseCls2; rand int i; function new; i = 0; endfunction endclass class DerivedCls2 extends BaseCls2; rand int j; function new; super.new; j = 0; endfunction endclass class OtherCls; logic[63:0] v; rand logic[63:0] w; rand logic[47:0] x; rand logic[31:0] y; rand logic[23:0] z; rand StructUnpacked str; function new; v = 0; w = 0; x = 0; y = 0; z = 0; str.i = 0; str.j = '{x: 1'b0, y: ONE, z: 64'd0, s: '{a: 32'd0, b: 1'b0, c: ONE}}; str.k = ONE; endfunction endclass class ContainsNull; rand BaseCls1 b; endclass class ClsWithInt; rand int a; int b; endclass class DeriveClsWithInt extends ClsWithInt; endclass class DeriveAndContainClsWithInt extends ClsWithInt; rand ClsWithInt cls1; ClsWithInt cls2; function new; cls1 = new; cls2 = new; endfunction endclass class ClsUsedOnlyHere; rand int a; endclass typedef ClsUsedOnlyHere cls_used_only_here_t; class ClsContainUsedOnlyHere; rand cls_used_only_here_t c; function new; c = new; endfunction endclass module t; DerivedCls1 derived1; DerivedCls2 derived2; OtherCls other; BaseCls1 base; ContainsNull cont; DeriveClsWithInt der_int; DeriveAndContainClsWithInt der_contain; ClsContainUsedOnlyHere cls_cont_used; initial begin derived1 = new; derived2 = new; other = new; cont = new; der_int = new; der_contain = new; base = derived1; cls_cont_used = new; for (int i = 0; i < 10; i++) begin void'(base.randomize()); void'(derived2.randomize()); void'(other.randomize()); void'(cont.randomize()); void'(der_int.randomize()); void'(der_contain.randomize()); if (!(derived1.l inside {ONE, TWO, THREE, FOUR})) $stop; if (!(other.str.j.s.c inside {ONE, TWO, THREE, FOUR})) $stop; if (!(other.str.j.y inside {ONE, TWO, THREE, FOUR})) $stop; if (!(other.str.k inside {ONE, TWO, THREE, FOUR})) $stop; if (derived1.i.e != 0) $stop; if (derived1.k != 0) $stop; if (other.v != 0) $stop; if (cont.b != null) $stop; if (der_int.b != 0) $stop; if (der_contain.cls2.a != 0) $stop; if (der_contain.cls1.b != 0) $stop; if (der_contain.b != 0) $stop; end `check_rand(derived1, derived1.i.a); `check_rand(derived1, derived1.i.b); `check_rand(derived1, derived1.i.c); `check_rand(derived1, derived1.j); `check_rand(derived1, derived1.l); `check_rand(derived2, derived2.i); `check_rand(derived2, derived2.j); `check_rand(other, other.w); `check_rand(other, other.x); `check_rand(other, other.y); `check_rand(other, other.z); `check_rand(other, other.str.i); `check_rand(other, other.str.j.x); `check_rand(other, other.str.j.y); `check_rand(other, other.str.j.z); `check_rand(other, other.str.j.s.a); `check_rand(other, other.str.j.s.b); `check_rand(other, other.str.j.s.c); `check_rand(other, other.str.k); `check_rand(der_int, der_int.a); `check_rand(der_contain, der_contain.cls1.a); `check_rand(der_contain, der_contain.a); `check_rand(cls_cont_used, cls_cont_used.c.a); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_randc_oversize_bad.py0000755000542200017500000000076315101701376023617 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_param_sel_range.v0000644000542200017500000000176615101701376022731 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // bug477 module t ( input rst_n, input clk, output out ); submod #(.STAGES(5)) u2(.*); endmodule module submod (/*AUTOARG*/ // Outputs out, // Inputs rst_n, clk ); parameter STAGES = 4; input rst_n; input clk; output out; reg [STAGES-1:0] r_rst; generate // for i=0..5 (5+1-1) for (genvar i=0; i #include #include #include VM_PREFIX_INCLUDE //====================================================================== unsigned int main_time = 0; double sc_time_stamp() { return main_time; } int main(int argc, char* argv[]) { auto topp = new VM_PREFIX; // We aren't calling Verilated::commandArgs(argc, argv) topp->eval(); return 0; } verilator-5.042/test_regress/t/t_property_sexpr_cov.out0000644000542200017500000000207315101701376024120 0ustar mahmoudyfreeshell[4] cover property, fileline:45 [7] concurrent cover, fileline:51 [8] cover property, fileline:45 [12] not cover property, fileline:48 [15] concurrent cover, fileline:51 [18] not cover property, fileline:48 [20] not cover property, fileline:48 [23] concurrent cover, fileline:51 [31] concurrent cover, fileline:51 [39] concurrent cover, fileline:51 [47] concurrent cover, fileline:51 [55] concurrent cover, fileline:51 [63] concurrent cover, fileline:51 [71] concurrent cover, fileline:51 [79] concurrent cover, fileline:51 [87] concurrent cover, fileline:51 [95] concurrent cover, fileline:51 [103] concurrent cover, fileline:51 [111] concurrent cover, fileline:51 [119] concurrent cover, fileline:51 [127] concurrent cover, fileline:51 [135] concurrent cover, fileline:51 [143] concurrent cover, fileline:51 [151] concurrent cover, fileline:51 [159] concurrent cover, fileline:51 [167] concurrent cover, fileline:51 [175] concurrent cover, fileline:51 [183] concurrent cover, fileline:51 [191] concurrent cover, fileline:51 [199] concurrent cover, fileline:51 *-* All Finished *-* verilator-5.042/test_regress/t/t_vlcov_opt_expr.py0000755000542200017500000000133615101701376023042 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') test.run(cmd=[ os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--write-info", test.obj_dir + "/coverage.info", "--filter-type expr", "t/t_vlcov_data_e.dat" ], verilator_run=True) test.files_identical(test.obj_dir + "/coverage.info", "t/" + test.name + ".info.out") test.passes() verilator-5.042/test_regress/t/t_dist_pl.py0000755000542200017500000000133015101701376021421 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') for pl in sorted(glob.glob(test.root + "/test_regress/t/*.pl")): if 'bootstrap.pl' in pl: continue py = re.sub(r'\.pl', '.py', pl) test.error_keep_going(pl + ":1: Perl test needs conversion into a Python test '" + os.path.basename(py) + "'") test.passes() verilator-5.042/test_regress/t/t_class_ref_bad.out0000644000542200017500000000053315101701376022712 0ustar mahmoudyfreeshell%Error: t/t_class_ref_bad.v:15:11: Package/class for ':: reference' not found: 'ClsRigh' : ... Suggested alternative: 'ClsRight' 15 | s = ClsRigh::m_s; | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_slice_cond_2d_side_effect.v0000644000542200017500000000154215101701376024611 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 typedef int arr_t[5][3]; class Cls; int cnt; int init_depth; function arr_t get_arr(int depth); arr_t arr = (depth > 1) ? get_arr(depth - 1) : '{5{'{init_depth, init_depth * 2, init_depth * 3}}}; cnt++; return arr; endfunction endclass module t; Cls c = new; initial begin arr_t arr; c.init_depth = 5; arr = (c.init_depth > 0) ? c.get_arr(5) : '{5{'{1, 2, 3}}}; if (arr[0][0] != 5) $stop; if (arr[0][1] != 10) $stop; if (arr[0][2] != 15) $stop; if (arr[3][2] != 15) $stop; if (c.cnt != 5) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_pp_defnettype_bad.v0000644000542200017500000000044015101701376023252 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `default_nettype bad_none_such `default_trireg_strength this_is_optional verilator-5.042/test_regress/t/t_mod_macromodule.py0000755000542200017500000000070615101701376023137 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.042/test_regress/t/t_lint_latch_bad_3.out0000644000542200017500000000076515101701376023323 0ustar mahmoudyfreeshell%Warning-LATCH: t/t_lint_latch_bad_3.v:19:1: Latch inferred for signal 'o5' (not all control paths of combinational always assign a value) : ... Suggest use of always_latch for intentional latches 19 | always_comb | ^~~~~~~~~~~ ... For warning description see https://verilator.org/warn/LATCH?v=latest ... Use "/* verilator lint_off LATCH */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_func_lib.py0000755000542200017500000000100115101701376021537 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=['-v', 't/t_func_lib_sub.v']) test.execute() test.passes() verilator-5.042/test_regress/t/t_class_param_virtual_bad.v0000644000542200017500000000101715101701376024440 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 virtual class VBase; endclass class Cls#(parameter type T = VBase); T t; function new; t = new; endfunction endclass virtual class ClsVirt#(parameter type T); endclass module t; initial begin Cls c = new; // Error ClsVirt#(VBase) cv = new; // Error $stop; end endmodule verilator-5.042/test_regress/t/t_interface_gen3_collision.py0000755000542200017500000000105515101701376024716 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_gen3.v" test.compile(verilator_flags2=["--debug-collision"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_param_type.py0000755000542200017500000000073415101701376022133 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_multidriven_bad.v0000644000542200017500000000143215101701376023776 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ // Outputs out, out2, // Inputs clk, a0, d0, d1 ); input clk; input [1:0] a0; input [7:0] d0; input [7:0] d1; output reg [31:0] out; output reg [15:0] out2; reg [7:0] mem[4]; always @(posedge clk) begin mem[a0] <= d0; // <--- Warning end always @(negedge clk) begin mem[a0] <= d1; // <--- Warning end assign out = {mem[3], mem[2], mem[1], mem[0]}; always @(posedge clk) begin out2[7:0] <= d0; // <--- Warning end always @(negedge clk) begin out2[15:8] <= d0; // <--- Warning end endmodule verilator-5.042/test_regress/t/t_class_new_this.v0000644000542200017500000000205415101701376022606 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface class ICls; pure virtual function string get(); endclass class Cls; string name; ICls icls; function new(string name, ICls icls); this.name = name; this.icls = icls; endfunction endclass class Testcase implements ICls; Cls cls = new("test_class", this); virtual function string get(); return "In ICls"; endfunction function Testcase clone(); Testcase a = new this; return a; endfunction endclass module t; initial begin Testcase test; Testcase cloned; test = new; if (test.cls.name != "test_class") $stop; if (test.cls.icls.get() != "In ICls") $stop; cloned = test.clone(); if (cloned.cls.name != "test_class") $stop; test.cls.icls = null; // Prevent leak $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_inst_overwide.py0000755000542200017500000000115215101701376022646 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["-sc -Wno-WIDTH"], verilator_make_gmake=False, make_top_shell=False, make_main=False) #test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_caseincomplete_bad.out0000644000542200017500000000063715101701376024777 0ustar mahmoudyfreeshell%Warning-CASEINCOMPLETE: t/t_lint_caseincomplete_bad.v:15:7: Case values incompletely covered (example pattern 0x1) 15 | case (i) | ^~~~ ... For warning description see https://verilator.org/warn/CASEINCOMPLETE?v=latest ... Use "/* verilator lint_off CASEINCOMPLETE */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_unpacked_struct_sel.py0000755000542200017500000000073415101701376024033 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_const_overflow_bad.out0000644000542200017500000000242515101701376024024 0ustar mahmoudyfreeshell%Error: t/t_const_overflow_bad.v:9:34: Too many digits for 94 bit number: '94'd123456789012345678901234567890' 9 | parameter [200:0] TOO_SMALL = 94'd123456789012345678901234567890; | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_const_overflow_bad.v:11:31: Too many digits for 8 bit number: '8'habc' 11 | parameter [200:0] SMALLH = 8'habc; | ^~~~~~ %Error: t/t_const_overflow_bad.v:12:31: Too many digits for 6 bit number: '6'o1234' 12 | parameter [200:0] SMALLO = 6'o1234; | ^~~~~~~ %Error: t/t_const_overflow_bad.v:13:31: Too many digits for 3 bit number: '3'b1111' 13 | parameter [200:0] SMALLB = 3'b1111; | ^~~~~~~ %Error: t/t_const_overflow_bad.v:19:35: Too many digits for 129 bit number: '129'hdeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00d' 19 | parameter [128:0] ALSO_SMALL = 129'hdeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00d; | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_var_dotted_dup_bad.v0000644000542200017500000000065015101701376023412 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; generate begin eh2_ram dccm_bank (.*); end begin eh2_ram dccm_bank (.*); // Error: duplicate end endgenerate endmodule module eh2_ram (); endmodule verilator-5.042/test_regress/t/t_preproc_str_undef.py0000755000542200017500000000100015101701376023500 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_const.v0000644000542200017500000000121115101701376020721 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin // verilator lint_off WIDTH if (32'hxxxxxxxx !== 'hx) $stop; if (32'hzzzzzzzz !== 'hz) $stop; if (32'h???????? !== 'h?) $stop; if (68'hx_xxxxxxxx_xxxxxxxx !== 'dX) $stop; if (68'hz_zzzzzzzz_zzzzzzzz !== 'dZ) $stop; if (68'h?_????????_???????? !== 'd?) $stop; // verilator lint_on WIDTH $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_bitsel_struct3.v0000644000542200017500000000276515101701376022563 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // A test case for struct signal bit selection. // // This test is to check that bit selection of multi-dimensional signal inside // of a packed struct works. Currently +: and -: blow up with packed structs. // // This file ONLY is placed into the Public Domain, for any use, without // warranty, 2013 by Jie Xu. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t; typedef struct packed { logic [15:0] channel; logic [15:0] others; } buss_t; buss_t b; reg [7:0] a; reg [7:0] c; reg [7:0] d; union packed { logic [31:0] [7:0] idx; struct packed { logic [15:0] z, y, x; logic [25:0] [7:0] r; } nam; } gpr; reg [14:0] gpr_a; initial begin b = {16'h8765,16'h4321}; a = b[19:12]; // This works c = b[8+:8]; // This fails d = b[11-:8]; // This fails `checkh(a, 8'h54); `checkh(c, 8'h43); `checkh(d, 8'h32); gpr = 256'h12346789_abcdef12_3456789a_bcdef123_456789ab_cdef1234_56789abc_def12345; `checkh (gpr[255:255-14], 15'h091a); gpr_a = gpr.nam.z[15:1]; `checkh (gpr_a, 15'h091a); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_define_override_output.py0000755000542200017500000000121515101701376024536 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_define_override.v" test.compile(verilator_flags2=[ "-Wno-DEFOVERRIDE -Wno-REDEFMACRO +define+TEST_MACRO=20 +define+TEST_MACRO=50" ]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_trace_abort_fst.out0000644000542200017500000000065415101701376023310 0ustar mahmoudyfreeshell$date Wed Feb 23 00:00:18 2022 $end $version fstWriter $end $timescale 1ps $end $scope module top $end $var wire 1 ! clk $end $scope module t $end $var wire 1 ! clk $end $var logic 3 " cyc [2:0] $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b000 " 0! $end #10 1! b001 " #15 0! #20 1! b010 " #25 0! #30 1! b011 " #35 0! #40 1! b100 " #45 0! #50 1! b101 " #55 0! #60 1! b110 " #65 0! #70 1! b111 " #75 0! verilator-5.042/test_regress/t/t_inst_overwide_bad.py0000755000542200017500000000105015101701376023451 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.top_filename = "t/t_inst_overwide.v" test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_order_multialways.py0000755000542200017500000000073415101701376023540 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_constraint_dist.v0000644000542200017500000000246615101701376023017 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `define check_rand(cl, field, cond) \ begin \ longint prev_result; \ int ok = 0; \ if (!bit'(cl.randomize())) $stop; \ prev_result = longint'(field); \ if (!(cond)) $stop; \ repeat(9) begin \ longint result; \ if (!bit'(cl.randomize())) $stop; \ result = longint'(field); \ if (!(cond)) $stop; \ if (result != prev_result) ok = 1; \ prev_result = result; \ end \ if (ok != 1) $stop; \ end class C; rand int x, y, z, w; int que[$] = '{3, 4, 5}; int arr[3] = '{5, 6, 7}; constraint distrib { x dist { [1:3] := 0, [5:6], [9:15] :/ 0 }; y dist { [1:3] := 0, 5, 6 := 8, [9:15] :/0 }; // /0 intentional to check yP_COLONDIV x < 20; }; constraint distinside { z dist {que}; w dist {arr}; }; endclass module t; initial begin C c = new; `check_rand(c, c.x, 5 <= c.x && c.x <= 6); `check_rand(c, c.y, 5 <= c.y && c.y <= 6); `check_rand(c, c.z, 3 <= c.z && c.z <= 5); `check_rand(c, c.w, 5 <= c.w && c.w <= 7); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_flag_deprecated_bad.py0000755000542200017500000000113315101701376023663 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--trace-fst-thread --order-clock-delay --clk foo --no-clk bar"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_unroll_nested_param.py0000755000542200017500000000105715101701376024026 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.golden_filename = 't/t_unroll_nested.out' test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_trace_no_top_name2_saif.out0000644000542200017500000001505115101701376024704 0ustar mahmoudyfreeshell// Generated by verilated_saif (SAIFILE (SAIFVERSION "2.0") (DIRECTION "backward") (PROGRAM_NAME "Verilator") (DIVIDER / ) (TIMESCALE 1ps) (DURATION 20) (INSTANCE $rootio (NET (clk (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 20)) ) ) (INSTANCE foo_pkg (NET (foo_func__Vstatic__b_current\[0\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (foo_func__Vstatic__b_current\[1\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (foo_func__Vstatic__b_current\[2\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (foo_func__Vstatic__b_current\[3\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (foo_func__Vstatic__b_current\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (foo_func__Vstatic__b_current\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (foo_func__Vstatic__b_current\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (foo_func__Vstatic__b_current\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (foo_func__Vstatic__b_current\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (foo_func__Vstatic__b_current\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (foo_func__Vstatic__b_current\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (foo_func__Vstatic__b_current\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (foo_func__Vstatic__b_current\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (foo_func__Vstatic__b_current\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (foo_func__Vstatic__b_current\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (foo_func__Vstatic__b_current\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (foo_func__Vstatic__b_current\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (foo_func__Vstatic__b_current\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (foo_func__Vstatic__b_current\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (foo_func__Vstatic__b_current\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (foo_func__Vstatic__b_current\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (foo_func__Vstatic__b_current\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (foo_func__Vstatic__b_current\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (foo_func__Vstatic__b_current\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (foo_func__Vstatic__b_current\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (foo_func__Vstatic__b_current\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (foo_func__Vstatic__b_current\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (foo_func__Vstatic__b_current\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (foo_func__Vstatic__b_current\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (foo_func__Vstatic__b_current\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (foo_func__Vstatic__b_current\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (foo_func__Vstatic__b_current\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE t (NET (clk (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 20)) (cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE sub (NET (a\[0\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[1\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[2\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (a\[3\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (a\[4\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (a\[5\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (a\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[7\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (a\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[10\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (a\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) verilator-5.042/test_regress/t/t_var_port_bad.v0000644000542200017500000000057715101701376022253 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; subok subok (.a(1'b1), .b(1'b0)); sub sub (.a(1'b1), .b(1'b0)); endmodule module subok (input a,b); endmodule module sub (a); input a, b; endmodule verilator-5.042/test_regress/t/t_lint_pinnotfound.py0000755000542200017500000000070315101701376023357 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint() test.passes() verilator-5.042/test_regress/t/t_inst_noname_bad.out0000644000542200017500000000050415101701376023261 0ustar mahmoudyfreeshell%Error: t/t_inst_noname_bad.v:8:5: Instance of module must be named 8 | m (); | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_inst_noname_bad.v:9:5: Instance of module must be named 9 | m (); | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_flag_structs_packed.v0000644000542200017500000000076415101701376023616 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module x; typedef struct { int a; } notpacked_t; typedef struct packed { notpacked_t b; } ispacked_t; ispacked_t p; initial begin p.b = 1; if (p.b != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_lint_width_genfor_bad.v0000644000542200017500000000154115101701376024114 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs rc, rg, ri, rp, rw ); parameter P = 17; wire [4:0] w = 5'd1; output reg [3:0] rc; output reg [3:0] rg; output reg [3:0] ri; output reg [3:0] rp; output reg [3:0] rw; for (genvar g=16; g < 17; ++g) begin // Index 17 makes a width violation initial begin rg = g; // WidthMin mismatch rp = P; // WidthMin mismatch rw = w; // Always a mismatch rc = 64'h1; // Always a mismatch (as sized) end end initial begin for (integer i=16; i < 17; ++i) begin ri = i; // WidthMin mismatch end end endmodule verilator-5.042/test_regress/t/t_trace_complex_params.py0000755000542200017500000000127515101701376024163 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_complex.v" test.compile(verilator_flags2=['--cc --trace-vcd --no-trace-structs --trace-params']) test.execute() test.file_grep(test.trace_filename, r' PARAM ') test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_assign_inline.py0000755000542200017500000000077315101701376022617 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["-O0 -fgate"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_math_real.py0000755000542200017500000000073415101701376021726 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_dpi_open_vecval.v0000644000542200017500000001657215101701376022750 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2017 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module t; // Note that a packed array is required, otherwise some simulators will return bad // results using *ElemVecVal() routines instead of scalar *Elem() routines. bit [0:0] i_bit_p1_u1 [2:-2]; bit [0:0] o_bit_p1_u1 [2:-2]; bit [0:0] q_bit_p1_u1 [2:-2]; bit [60:0] i_bit61_p1_u1 [2:-2]; bit [60:0] o_bit61_p1_u1 [2:-2]; bit [60:0] q_bit61_p1_u1 [2:-2]; bit [91:0] i_bit92_p1_u1 [2:-2]; bit [91:0] o_bit92_p1_u1 [2:-2]; bit [91:0] q_bit92_p1_u1 [2:-2]; bit [11:0] i_bit12_p1_u2 [2:-2] [-3:3]; bit [11:0] o_bit12_p1_u2 [2:-2] [-3:3]; bit [11:0] q_bit12_p1_u2 [2:-2] [-3:3]; bit [29:1] i_bit29_p1_u3 [2:-2] [-3:3] [4:-4]; bit [29:1] o_bit29_p1_u3 [2:-2] [-3:3] [4:-4]; bit [29:1] q_bit29_p1_u3 [2:-2] [-3:3] [4:-4]; import "DPI-C" function void dpii_bit_vecval_p1_u1 (int bits, int p, int u, input bit [0:0] i [], output bit [0:0] o [], output bit [0:0] q []); import "DPI-C" function void dpii_bit61_vecval_p1_u1 (int bits, int p, int u, input bit [60:0] i [], output bit [60:0] o [], output bit [60:0] q []); import "DPI-C" function void dpii_bit92_vecval_p1_u1 (int bits, int p, int u, input bit [91:0] i [], output bit [91:0] o [], output bit [91:0] q []); import "DPI-C" function void dpii_bit12_vecval_p1_u2 (int bits, int p, int u, input bit [11:0] i [] [], output bit [11:0] o [] [], output bit [11:0] q [] []); import "DPI-C" function void dpii_bit29_vecval_p1_u3 (int bits, int p, int u, input bit [29:1] i [] [] [], output bit [29:1] o [] [] [], output bit [29:1] q [] [] []); logic [0:0] i_logic_p1_u1 [2:-2]; logic [0:0] o_logic_p1_u1 [2:-2]; logic [0:0] q_logic_p1_u1 [2:-2]; logic [60:0] i_logic61_p1_u1 [2:-2]; logic [60:0] o_logic61_p1_u1 [2:-2]; logic [60:0] q_logic61_p1_u1 [2:-2]; logic [91:0] i_logic92_p1_u1 [2:-2]; logic [91:0] o_logic92_p1_u1 [2:-2]; logic [91:0] q_logic92_p1_u1 [2:-2]; logic [11:0] i_logic12_p1_u2 [2:-2] [-3:3]; logic [11:0] o_logic12_p1_u2 [2:-2] [-3:3]; logic [11:0] q_logic12_p1_u2 [2:-2] [-3:3]; logic [29:1] i_logic29_p1_u3 [2:-2] [-3:3] [4:-4]; logic [29:1] o_logic29_p1_u3 [2:-2] [-3:3] [4:-4]; logic [29:1] q_logic29_p1_u3 [2:-2] [-3:3] [4:-4]; import "DPI-C" function void dpii_logic_vecval_p1_u1 (int logics, int p, int u, input logic [0:0] i [], output logic [0:0] o [], output logic [0:0] q []); import "DPI-C" function void dpii_logic61_vecval_p1_u1 (int logics, int p, int u, input logic [60:0] i [], output logic [60:0] o [], output logic [60:0] q []); import "DPI-C" function void dpii_logic92_vecval_p1_u1 (int logics, int p, int u, input logic [91:0] i [], output logic [91:0] o [], output logic [91:0] q []); import "DPI-C" function void dpii_logic12_vecval_p1_u2 (int logics, int p, int u, input logic [11:0] i [] [], output logic [11:0] o [] [], output logic [11:0] q [] []); import "DPI-C" function void dpii_logic29_vecval_p1_u3 (int logics, int p, int u, input logic [29:1] i [] [] [], output logic [29:1] o [] [] [], output logic [29:1] q [] [] []); import "DPI-C" function int dpii_failure(); reg [95:0] crc; initial begin crc = 96'h8a10a572_5aef0c8d_d70a4497; begin for (int a=-2; a<=2; a=a+1) begin i_bit_p1_u1[a] = crc[0]; i_bit61_p1_u1[a] = crc[60:0]; i_bit92_p1_u1[a] = crc[91:0]; for (int b=-3; b<=3; b=b+1) begin i_bit12_p1_u2[a][b] = crc[11:0]; for (int c=-4; c<=4; c=c+1) begin i_bit29_p1_u3[a][b][c] = crc[29:1]; crc = {crc[94:0], crc[95]^crc[2]^crc[0]}; end end end dpii_bit_vecval_p1_u1(1, 1, 1, i_bit_p1_u1, o_bit_p1_u1, q_bit_p1_u1); dpii_bit61_vecval_p1_u1(61, 1, 1, i_bit61_p1_u1, o_bit61_p1_u1, q_bit61_p1_u1); dpii_bit92_vecval_p1_u1(92, 1, 1, i_bit92_p1_u1, o_bit92_p1_u1, q_bit92_p1_u1); dpii_bit12_vecval_p1_u2(12, 1, 2, i_bit12_p1_u2, o_bit12_p1_u2, q_bit12_p1_u2); dpii_bit29_vecval_p1_u3(29, 1, 3, i_bit29_p1_u3, o_bit29_p1_u3, q_bit29_p1_u3); for (int a=-2; a<=2; a=a+1) begin `checkh(o_bit_p1_u1[a], ~i_bit_p1_u1[a]); `checkh(q_bit_p1_u1[a], ~i_bit_p1_u1[a]); `checkh(o_bit61_p1_u1[a], ~i_bit61_p1_u1[a]); `checkh(q_bit61_p1_u1[a], ~i_bit61_p1_u1[a]); `checkh(o_bit92_p1_u1[a], ~i_bit92_p1_u1[a]); `checkh(q_bit92_p1_u1[a], ~i_bit92_p1_u1[a]); for (int b=-3; b<=3; b=b+1) begin `checkh(o_bit12_p1_u2[a][b], ~i_bit12_p1_u2[a][b]); `checkh(q_bit12_p1_u2[a][b], ~i_bit12_p1_u2[a][b]); for (int c=-4; c<=4; c=c+1) begin `checkh(o_bit29_p1_u3[a][b][c], ~i_bit29_p1_u3[a][b][c]); `checkh(q_bit29_p1_u3[a][b][c], ~i_bit29_p1_u3[a][b][c]); end end end end begin for (int a=-2; a<=2; a=a+1) begin i_logic_p1_u1[a] = crc[0]; i_logic61_p1_u1[a] = crc[60:0]; i_logic92_p1_u1[a] = crc[91:0]; for (int b=-3; b<=3; b=b+1) begin i_logic12_p1_u2[a][b] = crc[11:0]; for (int c=-4; c<=4; c=c+1) begin i_logic29_p1_u3[a][b][c] = crc[29:1]; crc = {crc[94:0], crc[95]^crc[2]^crc[0]}; end end end dpii_logic_vecval_p1_u1(1, 1, 1, i_logic_p1_u1, o_logic_p1_u1, q_logic_p1_u1); dpii_logic61_vecval_p1_u1(61, 1, 1, i_logic61_p1_u1, o_logic61_p1_u1, q_logic61_p1_u1); dpii_logic92_vecval_p1_u1(92, 1, 1, i_logic92_p1_u1, o_logic92_p1_u1, q_logic92_p1_u1); dpii_logic12_vecval_p1_u2(12, 1, 2, i_logic12_p1_u2, o_logic12_p1_u2, q_logic12_p1_u2); dpii_logic29_vecval_p1_u3(29, 1, 3, i_logic29_p1_u3, o_logic29_p1_u3, q_logic29_p1_u3); for (int a=-2; a<=2; a=a+1) begin `checkh(o_logic_p1_u1[a], ~i_logic_p1_u1[a]); `checkh(q_logic_p1_u1[a], ~i_logic_p1_u1[a]); `checkh(o_logic61_p1_u1[a], ~i_logic61_p1_u1[a]); `checkh(q_logic61_p1_u1[a], ~i_logic61_p1_u1[a]); `checkh(o_logic92_p1_u1[a], ~i_logic92_p1_u1[a]); `checkh(q_logic92_p1_u1[a], ~i_logic92_p1_u1[a]); for (int b=-3; b<=3; b=b+1) begin `checkh(o_logic12_p1_u2[a][b], ~i_logic12_p1_u2[a][b]); `checkh(q_logic12_p1_u2[a][b], ~i_logic12_p1_u2[a][b]); for (int c=-4; c<=4; c=c+1) begin `checkh(o_logic29_p1_u3[a][b][c], ~i_logic29_p1_u3[a][b][c]); `checkh(q_logic29_p1_u3[a][b][c], ~i_logic29_p1_u3[a][b][c]); end end end end if (dpii_failure()!=0) begin $write("%%Error: Failure in DPI tests\n"); $stop; end else begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_trace_max_default.py0000755000542200017500000000135315101701376023437 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_trace_max.v" test.compile(verilator_flags2=["--cc --trace-vcd"]) test.execute() test.file_grep(test.trace_filename, r'wide1') test.file_grep(test.trace_filename, r'wide2') test.file_grep(test.trace_filename, r'deep1') test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_queue_method2_bad.py0000755000542200017500000000076315101701376023350 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_extends_aliased_real_bad.py0000755000542200017500000000076615101701376026131 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_type_match.v0000644000542200017500000000244115101701376021736 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // issue #5125 // type used for __Vtrigprevexpr signal do not match type used for i/o port // // Generated C++ code should compile. // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Pawel Jewstafjew (Pawel.Jewstafjew@gmail.com). // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; logic a; logic d; top i_top(.*); integer cnt; initial cnt=1; always @ (posedge clk) begin cnt <= cnt + 1; a <= cnt[0]; $display("%d %d %d", cnt, a, d); if (d != a) $stop; if (cnt == 10) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module top ( input a, output d ); logic b; logic c[1]; assign c[0] = b; unit i_unit ( .a (a), .b (b), .c (c), .d (d) ); endmodule module unit ( input a, input c[1], output logic b, output logic d ); // no_inline required to prevent optimising away the interesing part ... /*verilator no_inline_module*/ always_comb begin b = a; d = b && c[0]; end endmodule verilator-5.042/test_regress/t/t_param_first_b.v0000644000542200017500000000100015101701376022377 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t_param_first_b (/*AUTOARG*/ // Outputs par, varwidth ); parameter X = 1; parameter FIVE = 0; // Overridden parameter TWO = 2; output [4:0] par; output [X:0] varwidth; wire [4:0] par = X; wire [X:0] varwidth = (FIVE==5)?TWO:0; endmodule verilator-5.042/test_regress/t/t_func_modify_input.py0000755000542200017500000000070615101701376023512 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.passes() verilator-5.042/test_regress/t/t_vpi_public_off.py0000755000542200017500000000170715101701376022761 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.pli_filename = "t/t_vpi_public_depth.cpp" test.top_filename = "t/t_vpi_public_depth.v" test.compile(make_top_shell=False, make_main=False, make_pli=True, iv_flags2=["-g2005-sv"], verilator_flags2=[ "+define+USE_DOLLAR_C32 --exe --vpi --no-l2name", test.pli_filename, "--public-depth 1 --public-ignore", ], make_flags=['CPPFLAGS_ADD=-DTEST_VPI_PUBLIC_OFF']) test.execute(use_libvpi=True) test.passes() verilator-5.042/test_regress/t/t_class_virtual_chain_ctor.py0000755000542200017500000000070315101701376025032 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint() test.passes() verilator-5.042/test_regress/t/t_trace_cat_renew.py0000755000542200017500000000151315101701376023113 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_trace_cat.cpp" test.top_filename = "t/t_trace_cat.v" test.compile(make_top_shell=False, make_main=False, v_flags2=["--trace-vcd --exe", test.pli_filename]) test.execute() test.vcd_identical(test.obj_dir + "/simpart_0000.vcd", "t/" + test.name + "__0000.out") test.vcd_identical(test.obj_dir + "/simpart_0100.vcd", "t/" + test.name + "__0100.out") test.passes() verilator-5.042/test_regress/t/t_mem_trace_split.v0000644000542200017500000000114715101701376022752 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Demonstrate complex user typea problem with --x-assign // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; logic [31:0] mem_a [32]; logic [15:0] mem_b [32]; int cyc = 0; // finish report always @ (posedge clk) begin cyc <= cyc + 1; mem_a[cyc] <= cyc; mem_b[cyc] <= 16'(cyc); if (cyc == 10) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_class_override.v0000644000542200017500000001106315101701376022605 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Function names correspond to how the function is declared in the base class, // then the extend class, with letters: // Does-not-exist(x), Nothing(n), :initial(i), :extends(e), :final(f) class Base; // _X = non-existant // _n = None function int get_n; return 1; endfunction function int get_n_n; return 1; endfunction function int get_n_e; return 1; endfunction function int get_n_ef; return 1; endfunction function int get_n_i; return 1; endfunction function int get_n_if; return 1; endfunction function int get_n_f; return 1; endfunction // _e = :extends // function :extends int get_e; return 1; endfunction // Bad // _ef = :extends :final // function :extends :final int get_ef; return 1; endfunction // Bad // _i = :initial function :initial int get_i; return 1; endfunction function :initial int get_i_n; return 1; endfunction function :initial int get_i_e; return 1; endfunction function :initial int get_i_ef; return 1; endfunction function :initial int get_i_i; return 1; endfunction function :initial int get_i_if; return 1; endfunction function :initial int get_i_f; return 1; endfunction // _if = :initial :final function :initial :final int get_if; return 1; endfunction function :initial :final int get_if_n; return 1; endfunction function :initial :final int get_if_e; return 1; endfunction function :initial :final int get_if_ef; return 1; endfunction function :initial :final int get_if_i; return 1; endfunction function :initial :final int get_if_if; return 1; endfunction function :initial :final int get_if_f; return 1; endfunction // _f = :final function :final int get_f; return 1; endfunction function :final int get_f_n; return 1; endfunction function :final int get_f_e; return 1; endfunction function :final int get_f_ef; return 1; endfunction function :final int get_f_i; return 1; endfunction function :final int get_f_if; return 1; endfunction function :final int get_f_f; return 1; endfunction endclass class Cls extends Base; // _X = non-existant function int get_x_n; return 1; endfunction // function :extends int get_x_e; return 1; endfunction // Bad // function :extends :final int get_x_ef; return 1; endfunction // Bad function :initial int get_x_i; return 1; endfunction function :initial :final int get_x_if; return 1; endfunction function :final int get_x_f; return 1; endfunction // _n = None function int get_n_n; return 1; endfunction function :extends int get_n_e; return 1; endfunction function :extends :final int get_n_ef; return 1; endfunction // function :initial int get_n_i; return 1; endfunction // Bad // function :initial :final int get_n_if; return 1; endfunction // Bad function :final int get_n_f; return 1; endfunction // _e = :extends // _ef = :extends :final // _i = :initial function int get_i_n; return 1; endfunction function :extends int get_i_e; return 1; endfunction function :extends :final int get_i_ef; return 1; endfunction // function :initial int get_i_i; return 1; endfunction // Bad // function :initial :final int get_i_if; return 1; endfunction // Bad function :final int get_i_f; return 1; endfunction // _if = :initial :final // function int get_if_n; return 1; endfunction // Bad // function :extends int get_if_e; return 1; endfunction // Bad // function :extends :final int get_if_ef; return 1; endfunction // Bad // function :initial int get_if_i; return 1; endfunction // Bad // function :initial :final int get_if_if; return 1; endfunction // Bad // function :final int get_if_f; return 1; endfunction // Bad // _f = :final // function int get_f_n; return 1; endfunction // Bad // function :extends int get_f_e; return 1; endfunction // Bad // function :extends :final int get_f_ef; return 1; endfunction // Bad // function :initial int get_f_i; return 1; endfunction // Bad // function :initial :final int get_f_if; return 1; endfunction // Bad // function :final int get_f_f; return 1; endfunction // Bad endclass class CBase; endclass class CClsN extends CBase; endclass class :final CClsF extends CBase; endclass module t; initial begin Cls c; CClsF cc; if (c != null) $stop; c = new; cc = new; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_x_rand_mt_stability.out0000644000542200017500000000105615101701376024203 0ustar mahmoudyfreeshelluninitialized = 0xf5bbcbc0 x_assigned (initial) = 0x00000000 uninitialized2 = 0xa979eb54 big = 0xa20c93ac50d8c57d4c80949aa68e82775da6af98ce08f75dc6ccfad97b059a33 random_init = 0x952aaa76 top.t.the_sub_yes_inline_1 no_init 0x4a544f7798b83fc8 top.t.the_sub_yes_inline_2 no_init 0x19b7000ee0472c9 top.t.the_sub_no_inline_1 no_init 0x38121a34978975dd top.t.the_sub_no_inline_2 no_init 0x9022c84ae0fa3cf6 rand = 0xb3cf9302 rand = 0xf0acf3e4 rand = 0xca0ac74c rand = 0x4eddfc2c rand = 0x1919db69 x_assigned = 0x486aeb2d Last rand = 0x2d118c9b *-* All Finished *-* verilator-5.042/test_regress/t/t_param_circ_bad.out0000644000542200017500000000057315101701376023055 0ustar mahmoudyfreeshell%Error: t/t_param_circ_bad.v:11:43: Variable's initial value is circular: 'X' : ... note: In instance 't.sub' 11 | module sub #(parameter WIDTH=X, parameter X=WIDTH) | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_interface1_modport_noinl.py0000755000542200017500000000104315101701376024750 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface1_modport.v" test.compile(v_flags2=["-fno-inline"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_width_genfor.py0000755000542200017500000000070615101701376023476 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.042/test_regress/t/t_class_ref_bad.py0000755000542200017500000000076615101701376022546 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_process_parse.py0000755000542200017500000000136315101701376022641 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t_process.v" out_filename = test.obj_dir + "/V" + test.name + ".tree.json" test.compile(verilator_flags2=["--debug-exit-uvm", "--json-only"], make_main=False, make_top_shell=False, verilator_make_gmake=False) test.file_grep(out_filename, r'.') # Exists test.passes() verilator-5.042/test_regress/t/t_string_sel.v0000644000542200017500000000244115101701376021752 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 typedef struct { string str; } str_s; class c; string str; function new(); str = "foo"; endfunction function string get_str(); return str; endfunction endclass module t; string str = "bar"; function string get_str(); return str; endfunction initial begin c o = new; str_s st = '{"qux"}; string sc = {"foo", "bar"}; // read if (str[0] != "b") $stop; if (get_str()[1] != "a") $stop; if (str[3] != "\0") $stop; if (st.str[2] != "x") $stop; if (st.str[99] != "\0") $stop; if (o.str[0] != "f") $stop; if (o.get_str()[1] != "o") $stop; if (o.str[-1] != "\0") $stop; if (sc[2] != "o") $stop; if ($sformatf("foo%s", "bar")[3] != "b") $stop; if (sc[-1] != "\0") $stop; if (sc[6] != "\0") $stop; if (sc[99] != "\0") $stop; // write sc[5] = "z"; if (sc != "foobaz") $stop; o.str[0] = "b"; if (o.str != "boo") $stop; st.str[2] = "z"; if (st.str != "quz") $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_lint_implicit_type_bad.v0000644000542200017500000000073615101701376024315 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class imp_Cls_conflict; endclass module t; typedef int imp_typedef_conflict; localparam type imp_PARAM_conflict; `default_nettype wire assign imp_typedef_conflict = 1'b1; assign imp_Cls_conflict = 1'b1; assign imp_PARAM_conflict = 1'b1; endmodule verilator-5.042/test_regress/t/t_process_finished.py0000755000542200017500000000077115101701376023322 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--timing"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_protect_ids_c.cpp0000644000542200017500000000231615101701376022740 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "svdpi.h" #include #include //====================================================================== // clang-format off #if defined(VERILATOR) # ifdef T_PROTECT_IDS_KEY # include "Vt_protect_ids_key__Dpi.h" # else # include "Vt_protect_ids__Dpi.h" # endif #elif defined(VCS) # include "../vc_hdrs.h" #elif defined(CADENCE) # define NEED_EXTERNS #else # error "Unknown simulator for DPI test" #endif #ifdef NEED_EXTERNS # error "Not supported" #endif // clang-format on //====================================================================== int dpii_a_func(int i) { int o = dpix_a_func(i); return o; } int dpii_a_task(int i, int* op) { (void)dpix_a_task(i, op); return 0; } verilator-5.042/test_regress/t/t_union_hard_bad.v0000644000542200017500000000110415101701376022530 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ; union packed { bit [7 : 0] val1; bit [3 : 0] val2; } u; initial begin u.val1 = 8'h7c; if(u.val1 != 8'h7c) $stop; u.val2 = 4'h6; if(u.val2 != 4'h6) $stop; $display("%p", u); if(u.val1 != 8'h76) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_assoc_method_map.py0000755000542200017500000000076315101701376023301 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface_generic_bad2.py0000755000542200017500000000102515101701376024310 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=['--timing'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_timescale_udp.v0000644000542200017500000000143515101701376022421 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under The Creative Commons Public Domain, for // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `timescale 1ns/1ns module t; p p (); // Also check not-found modules localparam NOT = 0; if (NOT) begin NotFound not_found(.*); end initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule `timescale 1ns/1ns program p; endprogram `celldefine `timescale 1ns/1ns primitive a_udp(out, in); output out; input in; reg out; table 0 : 1; 1 : 0; ? : ?; x : x; endtable endprimitive `endcelldefine `celldefine module c_not(in, out); input in; output out; assign out = !in1; endmodule `endcelldefine verilator-5.042/test_regress/t/t_interface_modport_export.out0000644000542200017500000000075015101701376025251 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_interface_modport_export.v:12:4: Unsupported: extern function 12 | extern function myfunc (input logic val); | ^~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_interface_modport_export.v:51:31: Unsupported: Out of block function declaration 51 | function automatic logic ie.myfunc (input logic val); | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_uniqueif_fail4.out0000644000542200017500000000021715101701376023046 0ustar mahmoudyfreeshell[10] %Error: t_uniqueif.v:102: Assertion failed in top.t: 'unique if' statement violated %Error: t/t_uniqueif.v:102: Verilog $stop Aborting... verilator-5.042/test_regress/t/t_class_param.v0000644000542200017500000001466515101701376022101 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); // See also t_class_param_mod.v typedef class Cls; class Wrap #(parameter P = 13); function int get_p; return c1.get_p(); endfunction function new; c1 = new; endfunction Cls#(PMINUS1 + 1) c1; localparam PMINUS1 = P - 1; // Checking works when last endclass class Wrap2 #(parameter P = 35); function int get_p; return c1.get_p(); endfunction function new; c1 = new; endfunction Wrap#(PMINUS1 + 1) c1; localparam PMINUS1 = P - 1; // Checking works when last endclass class Cls #(parameter PBASE = 12); bit [PBASE-1:0] member; function bit [PBASE-1:0] get_member; return member; endfunction static function int get_p; return PBASE; endfunction typedef enum { E_PBASE = PBASE } enum_t; class ClsInner; bit [PBASE-1:0] member; endclass endclass typedef Cls#(8) Cls8_t; class SelfRefClassTypeParam #(type T=logic); typedef SelfRefClassTypeParam #(int) self_int_t; T field; endclass class SelfRefClassIntParam #(int P=1); typedef SelfRefClassIntParam #(10) self_int_t; endclass class Sum #(type T); static int sum; static function void add(T element); sum += int'(element); endfunction endclass class IntQueue; int q[$]; function int getSum(); foreach(q[i]) Sum#(int)::add(q[i]); return Sum#(int)::sum; endfunction endclass class ClsStatic; static int x = 1; static function int get_2; return 2; endfunction endclass class ClsParam #(type T); typedef T param_t; endclass class ClsWithParamField; int m_field = Sum#(int)::sum; int m_queue[$]; function int get(int index); return m_queue[index]; endfunction endclass class DictWrapper; int m_dict[string]; endclass class DictOperator #(type T) extends T; function void set(string s, int x); m_dict[s] = x; endfunction function int get(string s); return m_dict[s]; endfunction endclass class Getter1 #(int T=0); static function int get_1(); return Getter1#(1)::T; endfunction endclass class Getter2 #(int T=5); static function int get_T(); return T; endfunction static function int get_2(); return Getter2#(2)::get_T(); endfunction endclass class ClsParamString #(string S="abcde"); typedef ClsParamString#(S) this_type; static this_type m_inst; int x = 0; string name = S; endclass typedef ClsParamString#("abcde") cls_param_string_def_t; typedef ClsParamString#("xyz") cls_param_string_not_def_t; module t; Cls c12; Cls #(.PBASE(4)) c4; Cls8_t c8; Cls#()::ClsInner ci; Cls#(8)::ClsInner ci8; Wrap #(.P(16)) w16; Wrap2 #(.P(32)) w32; SelfRefClassTypeParam src_logic; SelfRefClassTypeParam#()::self_int_t src_int; SelfRefClassIntParam src1; SelfRefClassIntParam#()::self_int_t src10; IntQueue qi; ClsWithParamField cls_param_field; DictOperator #(DictWrapper) dict_op; Getter1 getter1; Getter1 #(1) getter1_param_1; Getter2 getter2; cls_param_string_def_t cps_def; cls_param_string_not_def_t cps_not_def; int arr [1:0] = '{1, 2}; initial begin c12 = new; c4 = new; c8 = new; ci = new; ci8 = new; w16 = new; w32 = new; src_int = new; src_logic = new; src1 = new; src10 = new; qi = new; cls_param_field = new; dict_op = new; getter1 = new; getter1_param_1 = new; getter2 = new; if (Cls#()::PBASE != 12) $stop; if (Cls#(4)::PBASE != 4) $stop; if (Cls8_t::PBASE != 8) $stop; if (Cls#()::E_PBASE != 12) $stop; if (Cls#(4)::E_PBASE != 4) $stop; if (Cls8_t::E_PBASE != 8) $stop; if (c12.PBASE != 12) $stop; if (c4.PBASE != 4) $stop; if (c8.PBASE != 8) $stop; if (Cls#()::get_p() != 12) $stop; if (Cls#(4)::get_p() != 4) $stop; if (Cls8_t::get_p() != 8) $stop; if (c12.get_p() != 12) $stop; if (c4.get_p() != 4) $stop; if (c8.get_p() != 8) $stop; if (w16.get_p() != 16) $stop; if (w32.get_p() != 32) $stop; // verilator lint_off WIDTH c12.member = 32'haaaaaaaa; c4.member = 32'haaaaaaaa; c8.member = 32'haaaaaaaa; // verilator lint_on WIDTH ci.member = 12'haaa; ci8.member = 8'hff; if (ci.member != 12'haaa) $stop; if (ci8.member != 8'hff) $stop; if (c12.member != 12'haaa) $stop; if (c4.member != 4'ha) $stop; if (c12.get_member() != 12'haaa) $stop; if (c4.get_member() != 4'ha) $stop; `checkp(c12, "'{member:'haaa}"); `checkp(c4, "'{member:'ha}"); if ($bits(src_logic.field) != 1) $stop; if ($bits(src_int.field) != 32) $stop; if (src1.P != 1) $stop; if (src10.P != 10) $stop; qi.q = '{2, 4, 6, 0, 2}; if (qi.getSum() != 14) $stop; Sum#(int)::add(arr[0]); if (Sum#(int)::sum != 16) $stop; if (Sum#(real)::sum != 0) $stop; Sum#(real)::add(1.9); // rounds if (Sum#(real)::sum != 2) $stop; if (ClsParam#(ClsStatic)::param_t::x != 1) $stop; if (ClsParam#(ClsStatic)::param_t::get_2() != 2) $stop; cls_param_field.m_queue = '{1, 5, 7}; if (cls_param_field.get(2) != 7) $stop; dict_op.set("abcd", 1); if (dict_op.get("abcd") != 1) $stop; if (getter1.get_1() != 1) $stop; if (Getter1#()::get_1() != 1) $stop; if (getter1_param_1.get_1() != 1) $stop; if (getter2.get_2() != 2) $stop; if (Getter2#()::get_2() != 2) $stop; if (Getter2#(2)::get_2() != 2) $stop; cls_param_string_def_t::m_inst = new; cls_param_string_def_t::m_inst.x = 1; cps_def = cls_param_string_def_t::m_inst; if (cps_def.x != 1) $stop; if (cps_def.name != "abcde") $stop; cls_param_string_not_def_t::m_inst = new; cls_param_string_not_def_t::m_inst.x = 2; cps_not_def = cls_param_string_not_def_t::m_inst; if (cps_not_def.x != 2) $stop; if (cps_not_def.name != "xyz") $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_inst_2star_bad.out0000644000542200017500000000114215101701376023036 0ustar mahmoudyfreeshell%Error: t/t_inst_2star_bad.v:12:17: Duplicate .* in an instance (IEEE 1800-2023 23.3.2) 12 | sub sub (.*, .*); | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_inst_2star_bad.v:14:13: Mixing positional and .*/named instantiation connection (IEEE 1800-2023 23.3.2) 14 | sub sub (foo, .*); | ^~~ %Error: t/t_inst_2star_bad.v:16:13: Mixing positional and .*/named instantiation connection (IEEE 1800-2023 23.3.2) 16 | sub sub (foo, .bar); | ^~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_tri_eqcase.py0000755000542200017500000000073415101701376022111 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_bitsel_concat.v0000644000542200017500000000444315101701376022416 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // A test case for struct signal bit selection. // // This test is to check that bit selection of multi-dimensional signal inside // of a packed struct works. Currently +: and -: blow up with packed structs. // // This file ONLY is placed into the Public Domain, for any use, without // warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); // Test IEEE 1800-2023 concat bit selects, function bit selects, method bit selects class Cls; static function logic [15:0] valf1ed(); return 16'hf1ed; endfunction endclass module t; Cls c; int q[$]; logic [7:0] aa; logic [7:0] bb; logic [7:0] s8; logic s1; function logic [15:0] valf0ed(); return 16'hf0ed; endfunction int i; typedef int arr_t[1:0][3:0]; function arr_t valarr(); return '{'{1,2,3,4}, '{5,6,7,8}}; endfunction initial begin aa = 8'haa; bb = 8'hbb; s1 = {aa,bb}[8]; `checkh(s1, 1'b0); s1 = {aa,bb}[9]; `checkh(s1, 1'b1); s8 = {aa,bb}[11:4]; `checkh(s8, 8'hab); s8 = {aa,bb}[4+:8]; `checkh(s8, 8'hab); s8 = {aa,bb}[11-:8]; `checkh(s8, 8'hab); s1 = valf0ed()[4]; `checkh(s1, 1'b0); s1 = valf0ed()[5]; `checkh(s1, 1'b1); s8 = valf0ed()[11:4]; `checkh(s8, 8'h0e); s8 = valf0ed()[4+:8]; `checkh(s8, 8'h0e); s8 = valf0ed()[11-:8]; `checkh(s8, 8'h0e); c = new; s1 = c.valf1ed()[4]; `checkh(s1, 1'b0); s1 = c.valf1ed()[5]; `checkh(s1, 1'b1); s8 = c.valf1ed()[11:4]; `checkh(s8, 8'h1e); s8 = c.valf1ed()[4+:8]; `checkh(s8, 8'h1e); s8 = c.valf1ed()[11-:8]; `checkh(s8, 8'h1e); q.push_front(32'h10ef); s1 = q.sum()[4]; `checkh(s1, 1'b0); s1 = q.sum()[5]; `checkh(s1, 1'b1); s8 = q.sum()[11:4]; `checkh(s8, 8'h0e); s8 = q.sum()[4+:8]; `checkh(s8, 8'h0e); s8 = q.sum()[11-:8]; `checkh(s8, 8'h0e); i = valarr()[1][2]; $display(i); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_fuzz_eof_bad.out0000644000542200017500000000103015101701376022571 0ustar mahmoudyfreeshell%Error: t/t_fuzz_eof_bad.v:3:31: Unterminated string ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_fuzz_eof_bad.v:2:21: EOF in (* 2 | initial $lay(*Hello!=nendmodule | ^ %Error: t/t_fuzz_eof_bad.v:2:21: syntax error, unexpected end of file 2 | initial $lay(*Hello!=nendmodule | ^ %Error: Cannot continue ... This fatal error may be caused by the earlier error(s); resolve those first. verilator-5.042/test_regress/t/t_flag_topmodule_bad2.py0000755000542200017500000000120615101701376023656 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_flag_topmodule.v" test.lint( fails=True, v_flags2=["--top-module notfound"], nc=False, # Need to get it not to give the prompt expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_fork_join_none_class_cap.v0000644000542200017500000000203515101701376024607 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 event evt1; typedef enum {ENUM_VALUE} enum_t; class Foo; int m_member; enum_t m_en; task do_something(); fork #20 begin m_member++; $display("this's m_member: %0d m_en: %s", m_member, m_en.name()); if (m_member != 3) $stop; ->evt1; end #10 begin m_member++; bar(this); end join_none endtask static task bar(Foo foo); fork begin foo.m_member++; $display("foo's m_member: %0d m_en: %s", foo.m_member, foo.m_en.name()); if (foo.m_member != 2) $stop; end join_none endtask endclass module t(); initial begin Foo foo; foo = new; foo.m_member = 0; foo.do_something(); end always @(evt1) begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_constraint_extern.v0000644000542200017500000000143215101701376023351 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Packet; rand int one; rand int two; extern function void f(); constraint cone; extern constraint ctwo; constraint cmissing; // Ok per IEEE 1800-2023 18.5.1 endclass constraint Packet::cone { one > 0 && one < 2; } constraint Packet::ctwo { two > 1 && two < 3; } function void Packet::f(); endfunction module t; Packet p; int v; initial begin p = new; v = p.randomize(); if (v != 1) $stop; if (p.one != 1) $stop; if (p.two != 2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_case_huge_sub4.v0000644000542200017500000000352715101701376022467 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilator lint_off LATCH module t_case_huge_sub4 (/*AUTOARG*/ // Outputs outq, // Inputs index ); input [7:0] index; output logic [9:0] outq; // ============================= always @* begin // verilog_format: off case (index) // default below: no change 8'h00: begin outq = 10'h001; end 8'he0: begin outq = 10'h05b; end 8'he1: begin outq = 10'h126; end 8'he2: begin outq = 10'h369; end 8'he3: begin outq = 10'h291; end 8'he4: begin outq = 10'h2ca; end 8'he5: begin outq = 10'h25b; end 8'he6: begin outq = 10'h106; end 8'he7: begin outq = 10'h172; end 8'he8: begin outq = 10'h2f7; end 8'he9: begin outq = 10'h2d3; end 8'hea: begin outq = 10'h182; end 8'heb: begin outq = 10'h327; end 8'hec: begin outq = 10'h1d0; end 8'hed: begin outq = 10'h204; end 8'hee: begin outq = 10'h11f; end 8'hef: begin outq = 10'h365; end 8'hf0: begin outq = 10'h2c2; end 8'hf1: begin outq = 10'h2b5; end 8'hf2: begin outq = 10'h1f8; end 8'hf3: begin outq = 10'h2a7; end 8'hf4: begin outq = 10'h1be; end 8'hf5: begin outq = 10'h25e; end 8'hf6: begin outq = 10'h032; end 8'hf7: begin outq = 10'h2ef; end 8'hf8: begin outq = 10'h02f; end 8'hf9: begin outq = 10'h201; end 8'hfa: begin outq = 10'h054; end 8'hfb: begin outq = 10'h013; end 8'hfc: begin outq = 10'h249; end 8'hfd: begin outq = 10'h09a; end 8'hfe: begin outq = 10'h012; end 8'hff: begin outq = 10'h114; end default: ; // No change endcase // verilog_format: on end endmodule verilator-5.042/test_regress/t/t_package_import_override.py0000755000542200017500000000074615101701376024661 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.compile(verilator_flags2=['--timing']) test.passes() verilator-5.042/test_regress/t/t_trace_complex_portable.py0000755000542200017500000000232215101701376024502 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Same test as t_trace_complex, but exercising the old VCD tracing API import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_trace_complex.v" test.golden_filename = "t/t_trace_complex.out" test.compile(verilator_flags2=['--cc --trace-vcd -CFLAGS -DVL_PORTABLE_ONLY']) test.execute() test.file_grep(test.trace_filename, r' v_strp ') test.file_grep(test.trace_filename, r' v_strp_strp ') test.file_grep(test.trace_filename, r' v_arrp ') test.file_grep(test.trace_filename, r' v_arrp_arrp ') test.file_grep(test.trace_filename, r' v_arrp_strp ') test.file_grep(test.trace_filename, r' v_arru\[') test.file_grep(test.trace_filename, r' v_arru_arru\[') test.file_grep(test.trace_filename, r' v_arru_arrp\[') test.file_grep(test.trace_filename, r' v_arru_strp\[') test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_var_static_assign_decl_bad.out0000644000542200017500000001045615101701376025450 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_var_static_assign_decl_bad.v:101:17: Static variable initializer : is dependent on function/task I/O variable 101 | logic tmp = in; | ^~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_var_static_assign_decl_bad.v:106:17: Static variable initializer : is dependent on function/task I/O variable 106 | logic tmp = in; | ^~ %Error-UNSUPPORTED: t/t_var_static_assign_decl_bad.v:111:24: Static variable initializer : is dependent on function/task I/O variable 111 | static logic tmp = in; | ^~ %Error-UNSUPPORTED: t/t_var_static_assign_decl_bad.v:116:17: Static variable initializer : is dependent on function/task I/O variable 116 | logic tmp = out; | ^~~ %Error-UNSUPPORTED: t/t_var_static_assign_decl_bad.v:121:20: Static variable initializer : is dependent on function/task I/O variable 121 | logic tmp = in + 1; | ^ %Error: t/t_var_static_assign_decl_bad.v:126:26: Static variable initializer : is dependent on automatic variable 126 | static int foo = tmp + 1; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_var_static_assign_decl_bad.v:132:26: Static variable initializer : is dependent on automatic variable 132 | static int foo = tmp + 1; | ^ %Error: t/t_var_static_assign_decl_bad.v:138:29: Static variable initializer : is dependent on automatic variable 138 | static logic func_var = loc; | ^~~ %Error-UNSUPPORTED: t/t_var_static_assign_decl_bad.v:9:15: Static variable initializer : is dependent on function/task I/O variable 9 | logic tmp = in; | ^~ %Error-UNSUPPORTED: t/t_var_static_assign_decl_bad.v:14:15: Static variable initializer : is dependent on function/task I/O variable 14 | logic tmp = in; | ^~ %Error-UNSUPPORTED: t/t_var_static_assign_decl_bad.v:20:17: Static variable initializer : is dependent on function/task I/O variable 20 | logic tmp = in; | ^~ %Error-UNSUPPORTED: t/t_var_static_assign_decl_bad.v:25:17: Static variable initializer : is dependent on function/task I/O variable 25 | logic tmp = in; | ^~ %Error-UNSUPPORTED: t/t_var_static_assign_decl_bad.v:32:17: Static variable initializer : is dependent on function/task I/O variable 32 | logic tmp = in; | ^~ %Error-UNSUPPORTED: t/t_var_static_assign_decl_bad.v:37:17: Static variable initializer : is dependent on function/task I/O variable 37 | logic tmp = in; | ^~ %Error-UNSUPPORTED: t/t_var_static_assign_decl_bad.v:44:17: Static variable initializer : is dependent on function/task I/O variable 44 | logic tmp = in; | ^~ %Error-UNSUPPORTED: t/t_var_static_assign_decl_bad.v:49:17: Static variable initializer : is dependent on function/task I/O variable 49 | logic tmp = in; | ^~ %Error-UNSUPPORTED: t/t_var_static_assign_decl_bad.v:72:17: Static variable initializer : is dependent on function/task I/O variable 72 | logic tmp = in; | ^~ %Error: Exiting due to verilator-5.042/test_regress/t/t_dpi_dup_bad.v0000644000542200017500000000113015101701376022025 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (); // Same name w/ different args import "DPI-C" dpii_fa_bit = function int oth_f_int1(input int i); import "DPI-C" pure dpii_fa_bit = function int oth_f_int2(input int i, input int bad); initial begin $stop; end endmodule verilator-5.042/test_regress/t/t_disable_empty.out0000644000542200017500000000041615101701376022764 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_disable_empty.v:12:7: disable isn't underneath a begin with name: 'block' 12 | disable block; | ^~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_prof.py0000755000542200017500000000351415101701376020737 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap import platform test.scenarios('vlt_all') if re.search(r'clang', test.cxx_version) and 'aarch64' in platform.processor(): test.skip("Known compiler profile issues on clang aarch64") if platform.libc_ver()[0] != "glibc": test.skip("The test depends on GMON_OUT_PREFIX which is glibc-specific") test.compile(verilator_flags2=["--stats --prof-cfuncs +define+T_PROF"]) # TODO below might no longer be required as configure checks for -pg if 'VERILATOR_TEST_NO_GPROF' in os.environ: test.skip("Skipping due to VERILATOR_TEST_NO_GPROF") for filename in glob.glob(test.obj_dir + "/gmon.out.*"): test.unlink_ok(filename) test.setenv('GMON_OUT_PREFIX', test.obj_dir + "/gmon.out") test.execute() gmon_path = None for filename in glob.glob(test.obj_dir + "/gmon.out.*"): gmon_path = filename if not gmon_path: test.error("Profiler did not create a gmon.out") gmon_base = re.sub(r'.*[/\\]', '', gmon_path) test.run( cmd=["cd " + test.obj_dir + " && gprof " + test.vm_prefix + " " + gmon_base + " > gprof.log"], check_finished=False) test.run(cmd=[ "cd " + test.obj_dir + " && " + os.environ["VERILATOR_ROOT"] + "/bin/verilator_profcfunc gprof.log > profcfuncs.log" ], check_finished=False) test.file_grep(test.obj_dir + "/profcfuncs.log", r'Overall summary by') test.file_grep(test.obj_dir + "/profcfuncs.log", r'VLib + VL_POWSS_QQQ') test.file_grep(test.obj_dir + "/profcfuncs.log", r'VBlock + t_prof:') test.passes() verilator-5.042/test_regress/t/t_scheduling_0.v0000644000542200017500000000310315101701376022141 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2022 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VERILATOR // The '$c1(1)' is there to prevent inlining of the signal by V3Gate `define IMPURE_ONE $c(1); `else // Use standard $random (chaces of getting 2 consecutive zeroes is zero). `define IMPURE_ONE |($random | $random); `endif module top( clk ); input clk; // Generate half speed 'clk_half', via non-blocking assignment reg clk_half = 0; always @(posedge clk) clk_half <= ~clk_half; // 'clk_half_also' is the same as 'clk_half'. wire clk_half_also = clk_half & `IMPURE_ONE; // Random data updated by full speed clock reg q = 0; always @(posedge clk) q <= ($random % 2 == 1) ? 1'b1 : 1'b0; // Flop `q` via `clk_half` reg a = 0; always @(posedge clk_half) a <= q; // Flop `q` via `clk_half_also` reg b = 0; always @(posedge clk_half_also) b <= q; // Cycle count reg [31:0] cyc = 0; // `a` should always equal `b`, no mater which value they actually capture always @(posedge clk) begin if (a !== b) begin $display("tick %d: a is %1d, b is %1d (q is %1d)", cyc, a, b, q); $stop; end end // Just stop condition always @(posedge clk) begin cyc <= cyc + 1; if (cyc == 100) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_gantt_io.vcd.out0000644000542200017500000000431515101701376022524 0ustar mahmoudyfreeshell$version Generated by verilator_gantt $end $timescale 1ns $end $scope module gantt $end $scope module measured $end $var wire 32 v5 cpu10_mtask [31:0] $end $var wire 32 v4 cpu10_thread [31:0] $end $var wire 32 v7 cpu10_waiting [31:0] $end $var wire 32 v2 cpu19_mtask [31:0] $end $var wire 32 v1 cpu19_thread [31:0] $end $var wire 32 v6 cpu19_waiting [31:0] $end $var wire 32 v0 t0_mtask [31:0] $end $var wire 32 v3 t1_mtask [31:0] $end $upscope $end $scope module predicted $end $var wire 32 v8 t0_mtask [31:0] $end $var wire 32 v9 t1_mtask [31:0] $end $upscope $end $scope module stats $end $var wire 32 va measured_parallelism [31:0] $end $var wire 32 vb predicted_parallelism [31:0] $end $upscope $end $upscope $end $enddefinitions $end #0 bz v0 bz v1 bz v2 bz v3 bz v4 bz v5 bz v6 bz v7 bz v8 bz v9 b0 va b0 vb #2695 b110 v0 b0 v1 b110 v2 b110 v8 b101 v9 b1 va b10 vb #3795 b1010 v0 b0 v1 b1010 v2 b10 va #3800 bz v8 b111 v9 b1 vb #4850 bz v0 bz v1 bz v2 b1 va #4906 b1000 v9 b1 vb #5495 b101 v3 b1 v4 b101 v5 b10 va #5905 bz v0 bz v1 bz v2 b1 va #6090 bz v3 bz v4 bz v5 b0 va #6300 b111 v3 b1 v4 b111 v5 b1 va #6895 bz v3 bz v4 bz v5 b0 va #7490 b1000 v3 b1 v4 b1000 v5 b1 va #8540 bz v3 bz v4 bz v5 b0 va #8848 b1001 v9 b1 vb #9135 b1001 v3 b1 v4 b1001 v5 b1 va #9695 b1010 v0 b0 v1 b1010 v2 b10 va #9730 bz v3 bz v4 bz v5 b1 va #9870 bz v0 bz v1 bz v2 b0 va #9917 b1010 v8 b11 vb #9954 b1011 v9 b11 vb #10255 b1011 v3 b1 v4 b1011 v5 b1 va #11023 bz v8 b1 vb #11060 bz v3 bz v4 bz v5 bz v9 b0 va b0 vb #15610 b110 v0 b0 v1 b110 v2 b110 v8 b101 v9 b1 va b10 vb #15820 bz v0 bz v1 bz v2 b0 va #16437 bz v8 b111 v9 b1 vb #17265 b1000 v9 b1 vb #18375 b101 v3 b1 v4 b101 v5 b1 va #18970 bz v3 bz v4 bz v5 b0 va #19145 b111 v3 b1 v4 b111 v5 b1 va #19320 bz v3 bz v4 bz v5 b0 va #19670 b1000 v3 b1 v4 b1000 v5 b1 va #19810 bz v3 bz v4 bz v5 b0 va #20000 bx v6 #20219 b1001 v9 b1 vb #20650 b1001 v3 b1 v4 b1001 v5 b1 va #20720 bz v3 bz v4 bz v5 b0 va #21000 bz v6 #21019 b1010 v8 b11 vb #21047 b1011 v9 b11 vb #21140 b1011 v3 b1 v4 b1011 v5 b1 va #21245 bz v3 bz v4 bz v5 b0 va #21700 b1010 v0 b0 v1 b1010 v2 b1 va #21847 bz v8 b1 vb #21875 bz v0 bz v1 bz v2 bz v9 b0 va b0 vb #22000 bx v7 #23000 bz v7 verilator-5.042/test_regress/t/t_class_super_bad.py0000755000542200017500000000076615101701376023130 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_case_orig.v0000644000542200017500000001153715101701376021542 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg _ranit; reg rnd; reg [2:0] a; reg [2:0] b; reg [31:0] wide; // surefire lint_off STMINI initial _ranit = 0; wire sigone1 = 1'b1; wire sigone2 = 1'b1; reg ok; parameter [1:0] TWOUNKN = 2'b?; // This gets extended to 2'b?? // Large case statements should be well optimizable. reg [2:0] anot; always @ (/*AS*/a) begin casez (a) default: anot = 3'b001; 3'd0: anot = 3'b111; 3'd1: anot = 3'b110; 3'd2: anot = 3'b101; 3'd3: anot = 3'b101; 3'd4: anot = 3'b011; 3'd5: anot = 3'b010; 3'd6: anot = 3'b001; // Same so folds with 7 endcase end always @ (posedge clk) begin if (!_ranit) begin _ranit <= 1; rnd <= 1; $write("[%0t] t_case: Running\n", $time); // a = 3'b101; b = 3'b111; // verilator lint_off CASEX casex (a) default: $stop; 3'bx1x: $stop; 3'b100: $stop; 3'bx01: ; endcase casez (a) default: $stop; 3'b?1?: $stop; 3'b100: $stop; 3'b?01: ; endcase casez (a) default: $stop; {1'b0, TWOUNKN}: $stop; {1'b1, TWOUNKN}: ; endcase casez (b) default: $stop; {1'b0, TWOUNKN}: $stop; {1'b1, TWOUNKN}: ; // {1'b0, 2'b??}: $stop; // {1'b1, 2'b??}: ; endcase case(a[0]) default: ; endcase casex(a) default: ; 3'b?0?: ; endcase // verilator lint_off CASEX //This is illegal, the default occurs before the statements. //case(a[0]) // default: $stop; // 1'b1: ; //endcase // wide = 32'h12345678; casez (wide) default: $stop; 32'h12345677, 32'h12345678, 32'h12345679: ; endcase // ok = 0; casez ({sigone1,sigone2}) //2'b10, 2'b01, 2'bXX: ; // verilator bails at this since in 2 state it can be true... 2'b10, 2'b01: ; 2'b00: ; default: ok=1'b1; endcase if (ok !== 1'b1) $stop; // if (rnd) begin $write(""); end // $write("*-* All Finished *-*\n"); $finish; end end // Check parameters in case statements parameter ALU_DO_REGISTER = 3'h1; // input selected by reg addr. parameter DSP_REGISTER_V = 6'h03; reg [2:0] alu_ctl_2s; // Delayed version of alu_ctl reg [5:0] reg_addr_2s; // Delayed version of reg_addr reg [7:0] ir_slave_2s; // Instruction Register delayed 2 phases reg [15:10] f_tmp_2s; // Delayed copy of F reg p00_2s; initial begin alu_ctl_2s = 3'h1; reg_addr_2s = 6'h3; ir_slave_2s= 0; f_tmp_2s= 0; casex ({alu_ctl_2s,reg_addr_2s, ir_slave_2s[7],ir_slave_2s[5:4],ir_slave_2s[1:0], f_tmp_2s[11:10]}) default: p00_2s = 1'b0; {ALU_DO_REGISTER,DSP_REGISTER_V,1'bx,2'bx,2'bx,2'bx}: p00_2s = 1'b1; endcase if (1'b0) $display ("%x %x %x %x", alu_ctl_2s, ir_slave_2s, f_tmp_2s, p00_2s); //Prevent unused // case ({1'b1, 1'b1}) default: $stop; {1'b1, p00_2s}: ; endcase end // Check wide overlapping cases // surefire lint_off CSEOVR parameter ANY_STATE = 7'h??; reg [19:0] foo; initial begin foo = {1'b0,1'b0,1'b0,1'b0,1'b0,7'h04,8'b0}; casez (foo) default: $stop; {1'b1,1'b?,1'b?,1'b?,1'b?,ANY_STATE,8'b?}: $stop; {1'b?,1'b1,1'b?,1'b?,1'b?,7'h00,8'b?}: $stop; {1'b?,1'b?,1'b1,1'b?,1'b?,7'h00,8'b?}: $stop; {1'b?,1'b?,1'b?,1'b1,1'b?,7'h00,8'b?}: $stop; {1'b?,1'b?,1'b?,1'b?,1'b?,7'h04,8'b?}: ; {1'b?,1'b?,1'b?,1'b?,1'b?,7'h06,8'hdf}: $stop; {1'b?,1'b?,1'b?,1'b?,1'b?,7'h06,8'h00}: $stop; endcase end initial begin foo = 20'b1010; casex (foo[3:0]) default: $stop; 4'b0xxx, 4'b100x, 4'b11xx: $stop; 4'b1010: ; endcase end initial begin foo = 20'b1010; ok = 1'b0; // Test of RANGE(CONCAT reductions... casex ({foo[3:2],foo[1:0],foo[3]}) 5'bxx10x: begin ok=1'b0; foo=20'd1; ok=1'b1; end // Check multiple expressions 5'bxx00x: $stop; 5'bxx01x: $stop; 5'bxx11x: $stop; endcase if (!ok) $stop; end endmodule verilator-5.042/test_regress/t/t_verilated_all_newest.py0000755000542200017500000000174115101701376024165 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_verilated_all.v" test.compile( # Can't use --coverage and --savable together, so cheat and compile inline verilator_flags2=[ "--cc --coverage-toggle --coverage-line --coverage-user --trace-vcd --prof-exec --prof-pgo --vpi " + test.root + "/include/verilated_save.cpp", ("--timing" if test.have_coroutines else "--no-timing -Wno-STMTDLY") ], make_flags=['DRIVER_STD=newest']) test.execute( all_run_flags=[" +verilator+prof+exec+file+/dev/null", " +verilator+prof+vlt+file+/dev/null"]) test.passes() verilator-5.042/test_regress/t/t_do_not_convert_to_comb.py0000755000542200017500000000116715101701376024517 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(verilator_flags2=["--stats"]) # We must not convert these blocks into combinational blocks test.file_grep(test.stats, r'Scheduling, size of class: combinational\s+(\d+)', 0) test.passes() verilator-5.042/test_regress/t/t_sys_readmem_bad_digit.v0000644000542200017500000000061515101701376024100 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg [175:0] hex [15:0]; initial begin $readmemb("t/t_sys_readmem_bad_digit.mem", hex); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_inst_nansi.v0000644000542200017500000000126715101701376021753 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(b, si, i, li, w3, w4); output b; // Output before type output si; byte b; shortint si; int i; longint li; output i; // Output after type output li; input [2:0] w3; wire [2:0] w3; wire [3:0] w4; input [3:0] w4; initial begin if ($bits(b) != 8) $stop; if ($bits(si) != 16) $stop; if ($bits(i) != 32) $stop; if ($bits(li) != 64) $stop; if ($bits(w3) != 3) $stop; if ($bits(w4) != 4) $stop; $finish; end endmodule verilator-5.042/test_regress/t/t_tri_various.py0000755000542200017500000000073415101701376022340 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_implicitstatic_bad.out0000644000542200017500000000427415101701376025027 0ustar mahmoudyfreeshell%Warning-IMPLICITSTATIC: t/t_lint_implicitstatic_bad.v:16:9: Variable's lifetime implicitly set to static : ... The initializer value will only be set once : ... Suggest use 'static' before variable declaration' 16 | int implicit_warn = 1; | ^~~~~~~~~~~~~ ... For warning description see https://verilator.org/warn/IMPLICITSTATIC?v=latest ... Use "/* verilator lint_off IMPLICITSTATIC */" and lint_on around source to disable this message. %Warning-IMPLICITSTATIC: t/t_lint_implicitstatic_bad.v:19:16: Function/task's lifetime implicitly set to static : ... Suggest use 'function automatic' or 'function static' 19 | function int f_implicit_static(); | ^~~~~~~~~~~~~~~~~ t/t_lint_implicitstatic_bad.v:20:9: ... Location of implicit static variable : ... The initializer value will only be set once 20 | int cnt = 0; | ^~~ %Warning-IMPLICITSTATIC: t/t_lint_implicitstatic_bad.v:24:8: Function/task's lifetime implicitly set to static : ... Suggest use 'task automatic' or 'task static' 24 | task f_implicit_static(); | ^~~~~~~~~~~~~~~~~ t/t_lint_implicitstatic_bad.v:25:9: ... Location of implicit static variable : ... The initializer value will only be set once 25 | int cnt = 0; | ^~~ %Error: t/t_lint_implicitstatic_bad.v:24:8: Unsupported in C: Task has the same name as function: 'f_implicit_static' 24 | task f_implicit_static(); | ^~~~~~~~~~~~~~~~~ t/t_lint_implicitstatic_bad.v:19:16: ... Location of original declaration 19 | function int f_implicit_static(); | ^~~~~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_stacktrace.v0000644000542200017500000000107215101701376021724 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under The Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; task automatic t; // verilator no_inline_task string trace; $display("== Trace Func"); trace = $stacktrace(); if (trace == "") $stop; $display("%s", trace); $display("== Trace Task"); $stacktrace; $write("*-* All Finished *-*\n"); $finish; endtask initial t(); endmodule verilator-5.042/test_regress/t/t_lib_prot_delay_bad.v0000644000542200017500000000041615101701376023377 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 module secret_impl; initial begin #10; $stop; end endmodule verilator-5.042/test_regress/t/t_x_rand_stability_add_trace.out0000644000542200017500000000105615101701376025471 0ustar mahmoudyfreeshelluninitialized = 0xf5bbcbc0 x_assigned (initial) = 0x00000000 uninitialized2 = 0xa979eb54 big = 0xa20c93ac50d8c57d4c80949aa68e82775da6af98ce08f75dc6ccfad97b059a33 random_init = 0x952aaa76 top.t.the_sub_yes_inline_1 no_init 0x4a544f7798b83fc8 top.t.the_sub_yes_inline_2 no_init 0x19b7000ee0472c9 top.t.the_sub_no_inline_1 no_init 0x38121a34978975dd top.t.the_sub_no_inline_2 no_init 0x9022c84ae0fa3cf6 rand = 0xe3e54aaa rand = 0xe85acf2d rand = 0x15e12c6a rand = 0x0f7f28c0 rand = 0xe189c52a x_assigned = 0x486aeb2d Last rand = 0xf0700dbf *-* All Finished *-* verilator-5.042/test_regress/t/t_gen_alw.v0000644000542200017500000000430615101701376021217 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [9:0] in = crc[9:0]; /*AUTOWIRE*/ Test test (// Outputs .a(), .b(), /*AUTOINST*/ // Inputs .clk (clk), .in (in[9:0])); // Aggregate outputs into a single result vector wire [63:0] result = {64'h0}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h0 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs a, b, // Inputs clk, in ); /*verilator hier_block*/ input clk; input [9:0] in; output reg a [9:0]; integer ai; always @* begin for (ai=0;ai<10;ai=ai+1) begin a[ai]=in[ai]; end end output reg [1:0] b [9:0]; integer j; generate genvar i; for (i=0; i<2; i=i+1) begin always @(posedge clk) begin for (j=0; j<10; j=j+1) begin if (a[j]) b[i][j] <= 1'b0; else b[i][j] <= 1'b1; end end end endgenerate endmodule verilator-5.042/test_regress/t/t_gate_lvalue_const.py0000755000542200017500000000073415101701376023470 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_extends_this.py0000755000542200017500000000073415101701376023660 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_var_escape.v0000644000542200017500000000422615101701376021714 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs \escaped_normal , double__underscore, \9num , \bra[ket]slash/dash-colon:9backslash\done , // Inputs clk ); input clk; integer cyc; initial cyc=1; output \escaped_normal ; wire \escaped_normal = cyc[0]; output double__underscore ; wire double__underscore = cyc[0]; wire underscore_at_the_end_ = cyc[0]; wire double__underscore_at_the_end__ = cyc[0]; // Only underscores, ignored in trace wire _ = cyc[0]; wire __ = cyc[0]; wire ___ = cyc[0]; wire ____ = cyc[0]; // C doesn't allow leading non-alpha, so must escape output \9num ; wire \9num = cyc[0]; output \bra[ket]slash/dash-colon:9backslash\done ; wire \bra[ket]slash/dash-colon:9backslash\done = cyc[0]; wire \wire = cyc[0]; wire \check_alias = cyc[0]; wire \check:alias = cyc[0]; wire \check;alias = !cyc[0]; // These are *different entities*, bug83 wire [31:0] \a0.cyc = ~a0.cyc; wire [31:0] \other.cyc = ~a0.cyc; sub a0 (.cyc(cyc)); sub \mod.with_dot (.cyc(cyc)); always @ (posedge clk) begin cyc <= cyc + 1; if (escaped_normal != cyc[0]) $stop; if (\escaped_normal != cyc[0]) $stop; if (underscore_at_the_end_ != cyc[0]) $stop; if (double__underscore_at_the_end__ != cyc[0]) $stop; if (_ != cyc[0]) $stop; if (__ != cyc[0]) $stop; if (___ != cyc[0]) $stop; if (____ != cyc[0]) $stop; if (\9num != cyc[0]) $stop; if (\bra[ket]slash/dash-colon:9backslash\done != cyc[0]) $stop; if (\wire != cyc[0]) $stop; if (\check_alias != cyc[0]) $stop; if (\check:alias != cyc[0]) $stop; if (\check;alias != !cyc[0]) $stop; if (\a0.cyc != ~cyc) $stop; if (\other.cyc != ~cyc) $stop; if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module sub ( input [31:0] cyc ); endmodule verilator-5.042/test_regress/t/t_mem_multi_io2.v0000644000542200017500000000153615101701376022346 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2008 by Lane Brooks. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs o3, o34, o345, // Inputs i3, i34, i345 ); input [15:0] i3; output wire [15:0] o3; input [15:0] i34 [3:0]; output wire [15:0] o34 [3:0]; input [15:0] i345 [3:0][4:0]; output wire [15:0] o345 [3:0][4:0]; sub sub (.*); endmodule module sub (/*AUTOARG*/ // Outputs o3, o34, o345, // Inputs i3, i34, i345 ); input [15:0] i3; output wire [15:0] o3; input [15:0] i34 [3:0]; output wire [15:0] o34 [3:0]; input [15:0] i345 [3:0][4:0]; output wire [15:0] o345 [3:0][4:0]; assign o3 = i3; assign o34 = i34; assign o345 = i345; endmodule verilator-5.042/test_regress/t/t_tri_gate_cond.py0000755000542200017500000000136115101701376022570 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_tri_gate.cpp" test.top_filename = "t/t_tri_gate.v" test.compile(make_top_shell=False, make_main=False, v_flags2=['+define+T_COND'], make_flags=['CPPFLAGS_ADD=-DT_COND'], verilator_flags2=["--exe", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_assigneqexpr.py0000755000542200017500000000103115101701376023520 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--binary', '--trace', '-Wno-ASSIGNEQEXPR']) test.execute() test.passes() verilator-5.042/test_regress/t/t_randomize_array.v0000755000542200017500000001726115101701376023000 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by PlanV GmbH. // SPDX-License-Identifier: CC0-1.0 `define check_rand(cl, field) \ begin \ longint prev_result; \ int ok = 0; \ void'(cl.randomize()); \ prev_result = longint'(field); \ repeat(9) begin \ longint result; \ void'(cl.randomize()); \ result = longint'(field); \ if (result != prev_result) ok = 1; \ prev_result = result; \ end \ if (ok != 1) $stop; \ end class unconstrained_packed_array_test; rand bit [3:0] [2:0] [15:0] packed_array; function new(); packed_array = '{default: '{default: '{default: 'h0}}}; endfunction function void check_randomization(); `check_rand(this, this.packed_array) endfunction endclass class unconstrained_unpacked_array_test; rand bit [2:0] [15:0] unpacked_array [3][5]; rand int unpacked_array1 [9:3][4:8]; rand int unpacked_array2 [3:9][8:4]; function new(); unpacked_array = '{ '{default: '{default: 'h0}}, '{default: '{default: 'h1}}, '{default: '{default: 'h2}}}; unpacked_array1 = '{default: '{default: 0}}; unpacked_array2 = '{default: '{default: 0}}; endfunction function void check_randomization(); foreach (unpacked_array[i]) begin foreach (unpacked_array[i][j]) begin // At the innermost packed level, invoke check_rand `check_rand(this, this.unpacked_array[i][j]) end end foreach (unpacked_array1[i, j]) begin `check_rand(this, this.unpacked_array1[i][j]) end foreach (unpacked_array2[i, j]) begin `check_rand(this, this.unpacked_array2[i][j]) end endfunction endclass class Cls; rand int x = 1; endclass class unconstrained_dynamic_array_test; rand int dynamic_array_1d[]; rand int dynamic_array_2d[][]; rand Cls class_dynamic_array[]; rand Cls class_dynamic_array_null[]; function new(); // Initialize 1D dynamic array dynamic_array_1d = new[5]; foreach(dynamic_array_1d[i]) begin dynamic_array_1d[i] = 'h0 + i; end // Initialize 2D dynamic array dynamic_array_2d = new[3]; foreach(dynamic_array_2d[i]) begin dynamic_array_2d[i] = new[3]; foreach(dynamic_array_2d[i][j]) begin dynamic_array_2d[i][j] = 'h0 + i + j; end end class_dynamic_array = new[5]; foreach(class_dynamic_array[i]) begin class_dynamic_array[i] = new; end class_dynamic_array_null = new[2]; endfunction function void check_randomization(); foreach (dynamic_array_1d[i]) begin `check_rand(this, dynamic_array_1d[i]) end foreach (dynamic_array_2d[i]) begin foreach (dynamic_array_2d[i][j]) begin `check_rand(this, dynamic_array_2d[i][j]) end end foreach (class_dynamic_array[i]) begin `check_rand(this, class_dynamic_array[i].x) end foreach (class_dynamic_array_null[i]) begin if (class_dynamic_array_null[i] != null) $stop; end endfunction endclass class unconstrained_struct_with_array_test; typedef struct { rand bit [7:0] byte_array[4]; } struct_with_array_t; rand struct_with_array_t struct_with_array; function new(); struct_with_array = '{'{default: 'h0}}; endfunction function void check_randomization(); foreach (struct_with_array.byte_array[i]) begin `check_rand(this, struct_with_array.byte_array[i]) end endfunction endclass class unconstrained_struct_array_test; typedef struct { rand int field_a; rand int field_b; } simple_struct_t; rand simple_struct_t struct_array_1[3]; // Unpacked array rand simple_struct_t struct_array_2[][]; // Dynamic array function new(); struct_array_1 = '{'{default: 0}, '{default: 1}, '{default: 2}}; struct_array_2 = new[3]; foreach (struct_array_2[i]) begin struct_array_2[i] = new[4]; end endfunction function void check_randomization(); foreach (struct_array_1[i]) begin `check_rand(this, struct_array_1[i].field_a) `check_rand(this, struct_array_1[i].field_b) end foreach (struct_array_2[i, j]) begin `check_rand(this, struct_array_2[i][j].field_a) `check_rand(this, struct_array_2[i][j].field_b) end endfunction endclass class unconstrained_associative_array_test; rand int associative_array_1d[string]; rand int associative_array_3d[string][string][string]; string key1, key2, key3; function new(); associative_array_1d["key1"] = 1; associative_array_1d["key2"] = 2; associative_array_3d["key1"]["subkey1"]["subsubkey1"] = 1; associative_array_3d["key1"]["subkey1"]["subsubkey2"] = 2; associative_array_3d["key1"]["subkey2"]["subsubkey1"] = 3; associative_array_3d["key1"]["subkey3"]["subsubkey1"] = 4; associative_array_3d["key1"]["subkey3"]["subsubkey2"] = 5; associative_array_3d["key1"]["subkey3"]["subsubkey3"] = 6; associative_array_3d["key2"]["subkey1"]["subsubkey1"] = 7; associative_array_3d["key2"]["subkey1"]["subsubkey2"] = 8; associative_array_3d["key2"]["subkey2"]["subsubkey1"] = 9; associative_array_3d["key2"]["subkey3"]["subsubkey1"] = 10; associative_array_3d["key2"]["subkey3"]["subsubkey2"] = 11; endfunction function void check_randomization(); `check_rand(this, associative_array_1d["key1"]); `check_rand(this, associative_array_1d["key2"]); foreach(associative_array_3d[key1, key2, key3]) begin `check_rand(this, associative_array_3d[key1][key2][key3]); end endfunction endclass class unconstrained_queue_test; rand int queue_array_1d[$]; rand int queue_array_2d[$][$]; function new(); queue_array_1d = {}; for (int i = 0; i < 8; i++) begin queue_array_1d.push_back('h0 + i); end queue_array_2d = {}; queue_array_2d[0] = '{1, 2, 3}; queue_array_2d[1] = '{4, 5, 6, 0, 10}; queue_array_2d[2] = '{6, 7, 8, 9}; endfunction function void check_randomization(); foreach (queue_array_1d[i]) begin `check_rand(this, queue_array_1d[i]); end foreach(queue_array_2d[i, j]) begin `check_rand(this, queue_array_2d[i][j]); end endfunction endclass module t_randomize_array; unconstrained_packed_array_test packed_class; unconstrained_unpacked_array_test unpacked_class; unconstrained_dynamic_array_test dynamic_class; unconstrained_struct_with_array_test struct_with_array_class; unconstrained_struct_array_test struct_array_class; unconstrained_associative_array_test associative_array_class; unconstrained_queue_test queue_class; initial begin // Test 1: Packed Array Unconstrained Constrained Test packed_class = new(); repeat(2) begin packed_class.check_randomization(); end // Test 2: Unpacked Array Unconstrained Constrained Test unpacked_class = new(); repeat(2) begin unpacked_class.check_randomization(); end // Test 3: Dynamic Array Unconstrained Constrained Test dynamic_class = new(); repeat(2) begin dynamic_class.check_randomization(); end // Test 4: Struct Containing Array Test struct_with_array_class = new(); repeat(2) begin struct_with_array_class.check_randomization(); end struct_array_class = new(); repeat(2) begin struct_array_class.check_randomization(); end // Test 5: Associative Array Unconstrained Test associative_array_class = new(); repeat(2) begin associative_array_class.check_randomization(); end // Test 6: Queue Unconstrained Test queue_class = new(); repeat(2) begin queue_class.check_randomization(); end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_struct_pat_width.py0000755000542200017500000000073415101701376023361 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_cover_const_compare.v0000644000542200017500000000151615101701376023635 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; wire a = cyc[0]; wire b = cyc[0]; always @ (posedge clk) begin cyc <= cyc + 1; // Before this was optimized, with --coverage-line // error: self-comparison always evaluates to true [-Werror=tautological-compare] // if (((1U & vlSelf->t__DOT__cyc) == (1U & vlSelf->t__DOT__cyc))) if (a != cyc[0]) $stop; // Becomes cyc == cyc after substitution if (b != cyc[0]) $stop; if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_select_bad_range5.py0000755000542200017500000000077615101701376023326 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dynarray_bits.v0000644000542200017500000000055515101701376022457 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; integer a[]; initial begin if ($bits(a) != 0) $stop; a = new [10]; if ($bits(a) != 10*32) $stop; end endmodule verilator-5.042/test_regress/t/t_lint_width_shift_bad.py0000755000542200017500000000076315101701376024144 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_property_unsup.py0000755000542200017500000000111615101701376023103 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert', '--timing', '--error-limit 1000'], fails=True) test.passes() verilator-5.042/test_regress/t/t_vlt_syntax_bad.py0000755000542200017500000000106415101701376023010 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["t/t_vlt_syntax_bad.vlt"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_order_dpi_export_5.v0000644000542200017500000000206315101701376023375 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2021 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module testbench( /*AUTOARG*/ // Inputs clk ); input clk; int cnt = 0; export "DPI-C" function set_cnt; function void set_cnt(int val); cnt = val; endfunction; export "DPI-C" function get_cnt; function int get_cnt(); return cnt; endfunction; always @(posedge clk) cnt += 1; // Downstream combinational signal dependent on both input clock and // DPI export. wire dependent_clk = cnt == 2; int n = 0; always @(posedge dependent_clk) begin $display("t=%t n=%d", $time, n); if ($time != (8*n+3) * 500) $stop; if (n == 20) begin $write("*-* All Finished *-*\n"); $finish; end n += 1; end endmodule verilator-5.042/test_regress/t/t_std_randomize.py0000755000542200017500000000074615101701376022637 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.lint(verilator_flags2=["--binary"]) test.passes() verilator-5.042/test_regress/t/t_fork_finish.py0000755000542200017500000000077115101701376022274 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--timing"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_math_divw.py0000755000542200017500000000073415101701376021754 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_comb_loop_through_unpacked_array.v0000644000542200017500000000132315101701376026360 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2022 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module top( input wire a, input wire b, output wire o ); logic [255:0] array [1:0]; logic [255:0] tmp [1:0]; // Nonsensical, but needs to compile. (In some real designs we can end up // with combinational loops via unpacked arrays) always_comb begin tmp[0] = array[a]; end always_comb begin array[b] = tmp[0]; end assign o = array[0][0]; endmodule verilator-5.042/test_regress/t/t_unpacked_str_init.v0000644000542200017500000000156315101701376023312 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package pkg; localparam string REGS [0:31] = '{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0/fp", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"}; function string disasm32(logic [4:0] op); return $sformatf("lui %s" , REGS[op]); endfunction endpackage module t(/*AUTOARG*/ // Inputs op ); import pkg::*; input [4:0] op; always_comb begin $display("OP: 0x%08x: %s", op, disasm32(op)); end endmodule verilator-5.042/test_regress/t/t_lint_infinite_bad.out0000644000542200017500000000131715101701376023605 0ustar mahmoudyfreeshell%Warning-INFINITELOOP: t/t_lint_infinite_bad.v:10:7: Infinite loop (condition always true) : ... note: In instance 't' 10 | forever begin end | ^~~~~~~ ... For warning description see https://verilator.org/warn/INFINITELOOP?v=latest ... Use "/* verilator lint_off INFINITELOOP */" and lint_on around source to disable this message. %Warning-INFINITELOOP: t/t_lint_infinite_bad.v:12:7: Infinite loop (condition always true) : ... note: In instance 't' 12 | for (reg [31:0] i=0; i>=0; i=i+1) begin end | ^~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_std_identifier.py0000755000542200017500000000075515101701376022771 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["-DTEST_DECLARE_STD"]) test.passes() verilator-5.042/test_regress/t/t_interface_param2.v0000644000542200017500000000214215101701376023001 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2016 by Adrian Wise. // SPDX-License-Identifier: CC0-1.0 //bug1104 module t (input clk); simple_bus sb_intf(clk); simple_bus #(.DWIDTH(16)) wide_intf(clk); mem mem(sb_intf.slave); cpu cpu(sb_intf.master); mem memW(wide_intf.slave); cpu cpuW(wide_intf.master); endmodule interface simple_bus #(AWIDTH = 8, DWIDTH = 8) (input logic clk); // Define the interface logic req, gnt; logic [AWIDTH-1:0] addr; logic [DWIDTH-1:0] data; modport slave( input req, addr, clk, output gnt, input data); modport master(input gnt, clk, output req, addr, output data); initial begin if (DWIDTH != 8 && DWIDTH != 16) $stop; end endinterface: simple_bus module mem(interface a); logic avail; always @(posedge a.clk) a.gnt <= a.req & avail; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule module cpu(interface b); endmodule verilator-5.042/test_regress/t/t_lint_syncasyncnet_bad.py0000755000542200017500000000112215101701376024337 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME --if-depth 10"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_member_bad2.v0000644000542200017500000000065215101701376023127 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class ClsDup; int vardup; int vardup; task memdup; endtask task memdup; endtask function void funcdup; endfunction function void funcdup; endfunction endclass module t; endmodule verilator-5.042/test_regress/t/t_implements.py0000755000542200017500000000071415101701376022145 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.passes() verilator-5.042/test_regress/t/t_math_div.v0000644000542200017500000000775315101701376021407 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [255:0] a; reg [60:0] divisor; reg [60:0] qq; reg [60:0] rq; reg [60:0] qq4; reg [60:0] rq4; reg [60:0] qq5; reg [60:0] rq5; reg signed [60:0] qqs; reg signed [60:0] rqs; always @* begin qq = a[60:0] / divisor; rq = a[60:0] % divisor; qq4 = a[60:0] / 4; // Check power-of-two constification rq4 = a[60:0] % 4; qq5 = a[60:0] / 5; // Non power-of-two rq5 = a[60:0] % 5; qqs = $signed(a[60:0]) / $signed(divisor); rqs = $signed(a[60:0]) % $signed(divisor); end integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; //$write("%d: %x %x %x %x\n", cyc, qq, rq, qqs, rqs); if (cyc==1) begin a <= 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26; divisor <= 61'h12371; a[60] <= 1'b0; divisor[60] <= 1'b0; // Unsigned end if (cyc > 1) begin if (qq4 != {2'b0, a[60:2]}) $stop; if (rq4 != {59'h0, a[1:0]}) $stop; end if (cyc==2) begin a <= 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8; divisor <= 61'h1238123771; a[60] <= 1'b0; divisor[60] <= 1'b0; // Unsigned if (qq!==61'h00000403ad81c0da) $stop; if (rq!==61'h00000000000090ec) $stop; if (qqs!==61'h00000403ad81c0da) $stop; if (rqs!==61'h00000000000090ec) $stop; if (qq4 != 61'h01247cf6851f9fc9) $stop; if (rq4 != 61'h0000000000000002) $stop; end if (cyc==3) begin a <= 256'h0e17c88f00d5fe51a982646c8002bd68c3e236ddfd00ddbdad20a48e00f395b8; divisor <= 61'hf1b; a[60] <= 1'b1; divisor[60] <= 1'b0; // Signed if (qq!==61'h000000000090832e) $stop; if (rq!==61'h0000000334becc6a) $stop; if (qqs!==61'h000000000090832e) $stop; if (rqs!==61'h0000000334becc6a) $stop; if (qq4 != 61'h0292380e727ce56e) $stop; if (rq4 != 61'h0000000000000000) $stop; end if (cyc==4) begin a[60] <= 1'b0; divisor[60] <= 1'b1; // Signed if (qq!==61'h0001eda37cca1be8) $stop; if (rq!==61'h0000000000000c40) $stop; if (qqs!==61'h1fffcf5187c76510) $stop; if (rqs!==61'h1ffffffffffffd08) $stop; if (qq4 != 61'h07482923803ce56e) $stop; if (rq4 != 61'h0000000000000000) $stop; end if (cyc==5) begin a[60] <= 1'b1; divisor[60] <= 1'b1; // Signed if (qq!==61'h0000000000000000) $stop; if (rq!==61'h0d20a48e00f395b8) $stop; if (qqs!==61'h0000000000000000) $stop; if (rqs!==61'h0d20a48e00f395b8) $stop; end if (cyc==6) begin if (qq!==61'h0000000000000001) $stop; if (rq!==61'h0d20a48e00f3869d) $stop; if (qqs!==61'h0000000000000000) $stop; if (rqs!==61'h1d20a48e00f395b8) $stop; end // Div by zero if (cyc==9) begin divisor <= 61'd0; end if (cyc==10) begin `ifdef verilator if (qq !== {61{1'b0}}) $stop; if (rq !== {61{1'b0}}) $stop; `else if (qq !== {61{1'bx}}) $stop; if (rq !== {61{1'bx}}) $stop; `endif if ({16{1'bx}} !== 16'd1/16'd0) $stop; // No div by zero errors if ({16{1'bx}} !== 16'd1%16'd0) $stop; // No div by zero errors end if (cyc==19) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.042/test_regress/t/t_vpi_stop_bad.py0000755000542200017500000000115115101701376022435 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=["t/t_vpi_stop_bad_c.cpp"], verilator_flags2=["--vpi"]) test.execute(fails=test.vlt_all, check_finished=False, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface_virtual_sched_act.v0000644000542200017500000000175615101701376025314 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 interface Bus; logic [15:0] data; endinterface module t_sched_act; logic clk = 0; integer cyc = 0; Bus intf(); virtual Bus vif = intf; logic [15:0] data; always @(posedge clk) begin cyc <= cyc + 1; end // Finish on negedge so that $finish is last always @(negedge clk) if (cyc >= 6) begin $write("*-* All Finished *-*\n"); $finish; end always @(posedge clk or data) begin if (cyc == 1) intf.data <= 'hdead; else if (cyc == 2) intf.data <= 'hbeef; else if (cyc == 3) intf.data <= 'hface; else if (cyc == 4) intf.data <= 'hcafe; end always @(negedge clk) begin data <= vif.data; end always @(data) begin $write("[%0t] data==%h\n", $time, data); end initial begin repeat (10) #5ns clk = ~clk; end endmodule verilator-5.042/test_regress/t/t_display_recurse.v0000644000542200017500000000257515101701376023006 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; integer i; integer count = 'd0; always @(posedge clk) begin count <= count + 1; if (count == 10) begin for(i=0; i<30; i=i+4) begin // See issue #4480, verilator may inline getb() which has another display inside it $display("%d: %02x%02x%02x%02x", i, getb(i+3), getb(i+2), getb(i+1), getb(i)); end end if (count == 11) begin $write("*-* All Finished *-*\n"); $finish; end end localparam SIZE = 64*1024; localparam ADDRW = $clog2(SIZE/4); reg [31: 0] ram [(SIZE/4)-1: 0]; function [7:0] getb; input [31:0] address; if (address[31:ADDRW+2] != 0) begin $display("Address out of range"); end case(address[1:0]) 0: getb = ram[address[ADDRW+1: 2]][8*0+7:8*0]; 1: getb = ram[address[ADDRW+1: 2]][8*1+7:8*1]; 2: getb = ram[address[ADDRW+1: 2]][8*2+7:8*2]; 3: getb = ram[address[ADDRW+1: 2]][8*3+7:8*3]; endcase endfunction initial begin for (i=0; i 0) begin cnt++; fork run(n - 1); join end endtask endclass module t; initial begin automatic RecFork rec = new; rec.run(7); if (rec.cnt != 7) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_package_export_bad.py0000755000542200017500000000114015101701376023564 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.top_filename = "t/t_package_export.v" test.lint(v_flags2=['+define+T_PACKAGE_EXPORT_BAD'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface_generic_modport.py0000755000542200017500000000077115101701376025173 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--timing']) test.execute() test.passes() verilator-5.042/test_regress/t/t_preproc_inc_inc_bad.vh0000644000542200017500000000041115101701376023706 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module xx; xx // intentional error endmodule verilator-5.042/test_regress/t/t_tri_select_pins_inout.py0000755000542200017500000000125515101701376024375 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_tri_select.cpp" test.top_filename = "t/t_tri_select.v" test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe --pins-inout-enables", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_split_var_auto.py0000755000542200017500000000112215101701376023015 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--stats"]) test.execute() test.file_grep(test.stats, r'SplitVar, packed variables split automatically\s+(\d+)', 1) test.passes() verilator-5.042/test_regress/t/t_dpi_display_bad.out0000644000542200017500000000063115101701376023251 0ustar mahmoudyfreeshell%Error: t/t_dpi_display_bad.v:17:69: /*verilator sformat*/ can only be applied to last argument of a function 17 | (input string formatted /*verilator sformat*/ , input string other_bad ); | ^~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_timing_timescale.v0000644000542200017500000000246715101701376023126 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Paul Wright. // SPDX-License-Identifier: CC0-1.0 module t; timeunit 1ns; timeprecision 1ps; logic clkb, clk; initial begin clkb = 0; end always @(clk) begin clkb <= ~clk; end bot bot (.clkb(clkb), .clk(clk)); final begin $display("[%g] final (%m)", $realtime()); end endmodule module bot (input logic clkb, output logic clk); timeunit 1s; timeprecision 1fs; integer count; real delay; initial begin count = 0; delay = 500e-9; clk = clkb; #(3.5 * delay) $display("[%g] Initial finishing, clkb = %b", $realtime(), clkb); end always @(clkb) begin $display("[%g] clkb is %b", $realtime(), clkb); count++; #(delay) clk = clkb; end always @(count) begin if (count > 20) begin $display("[%g] Finishing (%m)", $realtime()); if ($realtime() < (delay * 20)) begin $display("[%g] %%Error: That was too quick!", $realtime()); end $write("*-* All Finished *-*\n"); $finish; end end final begin $display("[%g] final (%m) count was %0d", $realtime(), count); end endmodule verilator-5.042/test_regress/t/t_inside2.py0000755000542200017500000000071415101701376021325 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.passes() verilator-5.042/test_regress/t/t_interface_wire_bad.out0000644000542200017500000000056015101701376023737 0ustar mahmoudyfreeshell%Error: t/t_interface_wire_bad.v:17:20: Operator ASSIGNW expected non-interface on Assign RHS but 'a' is an interface. : ... note: In instance 't' 17 | wire wbad = sub.a; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_dpi_result_type__Dpi.out0000644000542200017500000000534715101701376024321 0ustar mahmoudyfreeshell// Verilated -*- C++ -*- // DESCRIPTION: Verilator output: Prototypes for DPI import and export functions. // // Verilator includes this file in all generated .cpp files that use DPI functions. // Manually include this file where DPI .c import functions are declared to ensure // the C functions match the expectations of the DPI imports. #ifndef VERILATED_VT_DPI_RESULT_TYPE__DPI_H_ #define VERILATED_VT_DPI_RESULT_TYPE__DPI_H_ // guard #include "svdpi.h" #ifdef __cplusplus extern "C" { #endif // DPI EXPORTS extern svBitVecVal e_array_2_state_1(); extern svBitVecVal e_array_2_state_32(); extern svBit e_bit(); extern svBit e_bit_t(); extern char e_byte(); extern char e_byte_t(); extern unsigned char e_byte_unsigned(); extern unsigned char e_byte_unsigned_t(); extern void* e_chandle(); extern void* e_chandle_t(); extern int e_int(); extern int e_int_t(); extern unsigned int e_int_unsigned(); extern unsigned int e_int_unsigned_t(); extern svLogic e_logic(); extern svLogic e_logic_t(); extern long long e_longint(); extern long long e_longint_t(); extern unsigned long long e_longint_unsigned(); extern unsigned long long e_longint_unsigned_t(); extern double e_real(); extern double e_real_t(); extern short e_shortint(); extern short e_shortint_t(); extern unsigned short e_shortint_unsigned(); extern unsigned short e_shortint_unsigned_t(); extern const char* e_string(); extern const char* e_string_t(); extern svBitVecVal e_struct_2_state_1(); extern svBitVecVal e_struct_2_state_32(); extern svBitVecVal e_union_2_state_1(); extern svBitVecVal e_union_2_state_32(); extern void e_void(); // DPI IMPORTS extern void check_exports(); extern svBitVecVal i_array_2_state_1(); extern svBitVecVal i_array_2_state_32(); extern svBit i_bit(); extern svBit i_bit_t(); extern char i_byte(); extern char i_byte_t(); extern unsigned char i_byte_unsigned(); extern unsigned char i_byte_unsigned_t(); extern void* i_chandle(); extern void* i_chandle_t(); extern int i_int(); extern int i_int_t(); extern unsigned int i_int_unsigned(); extern unsigned int i_int_unsigned_t(); extern svLogic i_logic(); extern svLogic i_logic_t(); extern long long i_longint(); extern long long i_longint_t(); extern unsigned long long i_longint_unsigned(); extern unsigned long long i_longint_unsigned_t(); extern double i_real(); extern double i_real_t(); extern short i_shortint(); extern short i_shortint_t(); extern unsigned short i_shortint_unsigned(); extern unsigned short i_shortint_unsigned_t(); extern const char* i_string(); extern const char* i_string_t(); extern svBitVecVal i_struct_2_state_1(); extern svBitVecVal i_struct_2_state_32(); extern svBitVecVal i_union_2_state_1(); extern svBitVecVal i_union_2_state_32(); extern void i_void(); #ifdef __cplusplus } #endif #endif // guard verilator-5.042/test_regress/t/t_wrapper_reuse_context_bad.cpp0000644000542200017500000000113015101701376025345 0ustar mahmoudyfreeshell// // DESCRIPTION: Verilator: Verilog Multiple Model Test Module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include VM_PREFIX_INCLUDE int main(int argc, char** argv) { // Create contexts VerilatedContext* contextp{new VerilatedContext}; for (int i = 0; i < 2; ++i) { std::unique_ptr topp{new VM_PREFIX{contextp, "TOP"}}; topp->eval(); contextp->timeInc(1); topp->eval(); } return 0; } verilator-5.042/test_regress/t/t_continue_do_while_bad.out0000644000542200017500000000060015101701376024442 0ustar mahmoudyfreeshell%Warning-INFINITELOOP: t/t_continue_do_while_bad.v:14:7: Infinite loop (condition always true) 14 | do begin | ^~ ... For warning description see https://verilator.org/warn/INFINITELOOP?v=latest ... Use "/* verilator lint_off INFINITELOOP */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_timing_fork_join_forkproc.out0000644000542200017500000000116515101701376025401 0ustar mahmoudyfreeshell[0] fork..join process 4 [2] fork..join process 3 [4] fork..join process 2 [8] fork..join process 1 [16] fork in fork starts [16] fork..join process 8 [20] fork..join process 7 [24] fork..join process 6 [32] fork..join process 5 [32] fork..join in fork ends [64] main process fork..join_any process 2 back in main process fork..join_any process 1 fork..join_any process 1 back in main process fork..join_any process 2 in main process fork..join_none process 1 fork..join_none process 2 fork..join_none process 3 fork..join_none process 2 again fork..join_none process 1 again fork..join_none process 3 again *-* All Finished *-* verilator-5.042/test_regress/t/t_var_dup3.v0000644000542200017500000000105515101701376021324 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Legal with Verilog 1995 style ports module t (/*AUTOARG*/ // Outputs ok_o_w, ok_o_r, ok_o_ra, ok_or, ok_ow, ok_owa ); output ok_o_w; wire ok_o_w; output ok_o_r; reg ok_o_r; output [1:0] ok_o_ra; reg [1:0] ok_o_ra; output reg ok_or; output wire ok_ow; output wire [1:0] ok_owa; endmodule verilator-5.042/test_regress/t/t_class_assign_cond_bad.py0000755000542200017500000000076615101701376024261 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_unpacked_wide_unknown.py0000755000542200017500000000077115101701376024354 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--binary']) test.execute() test.passes() verilator-5.042/test_regress/t/t_vpi_repetitive_cbs.cpp0000644000542200017500000002612015101701376024003 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2020 by Wilson Snyder and Marlon James. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #ifdef IS_VPI #include "vpi_user.h" #include #else #include "verilated.h" #include "verilated_vpi.h" #include VM_PREFIX_INCLUDE #endif #include #include #include #include #include extern "C" { #include } // These require the above. Comment prevents clang-format moving them #include "TestSimulator.h" #include "TestVpi.h" const std::vector cbs_to_test{cbValueChange}; enum CallbackState { PRE_REGISTER, ACTIVE, ACTIVE_AGAIN, REM_REREG_ACTIVE, POST_REMOVE }; const std::vector cb_states{PRE_REGISTER, ACTIVE, ACTIVE_AGAIN, REM_REREG_ACTIVE, POST_REMOVE}; #define CB_COUNT cbAtEndOfSimTime + 1 TestVpiHandle vh_registered_cbs[CB_COUNT] = {0}; unsigned int callback_counts[CB_COUNT] = {0}; unsigned int callback_expected_counts[CB_COUNT] = {0}; bool callbacks_called[CB_COUNT] = {false}; bool callbacks_expected_called[CB_COUNT] = {false}; std::vector::const_iterator cb_iter; std::vector::const_iterator state_iter; bool got_error = false; #ifdef IS_VPI vpiHandle clk_h; #endif #ifdef TEST_VERBOSE bool verbose = true; #else bool verbose = false; #endif #ifdef IS_VPI #define END_TEST \ vpi_control(vpiStop); \ return 0; #else #define END_TEST return __LINE__; #endif #define STRINGIFY_CB_CASE(_cb) \ case _cb: return #_cb static const char* cb_reason_to_string(int cb_name) { switch (cb_name) { STRINGIFY_CB_CASE(cbValueChange); default: return "Unsupported callback"; } } #undef STRINGIFY_CB_CASE static int the_callback(p_cb_data cb_data) { vpi_printf(const_cast(" The callback\n")); callback_counts[cb_data->reason] = callback_counts[cb_data->reason] + 1; return 0; } static int register_cb(const int next_state) { int cb = *cb_iter; t_cb_data cb_data_testcase; s_vpi_value v; // Needed in this scope as is in cb_data bzero(&cb_data_testcase, sizeof(cb_data_testcase)); cb_data_testcase.cb_rtn = the_callback; cb_data_testcase.reason = cb; #ifdef IS_VPI TestVpiHandle count_h = vpi_handle_by_name(const_cast("t.count"), 0); // Needed in this scope as is in cb_data #else TestVpiHandle count_h = VPI_HANDLE("count"); // Needed in this scope as is in cb_data #endif CHECK_RESULT_NZ(count_h); if (cb == cbValueChange) { v.format = vpiSuppressVal; cb_data_testcase.obj = count_h; cb_data_testcase.value = &v; } // State of callback next time through loop if (verbose) vpi_printf(const_cast(" Updating callback for next loop:\n")); switch (next_state) { case ACTIVE: { if (verbose) { vpi_printf(const_cast(" - Registering callback %s\n"), cb_reason_to_string(cb)); } vh_registered_cbs[cb].release(); vh_registered_cbs[cb] = vpi_register_cb(&cb_data_testcase); break; } case REM_REREG_ACTIVE: { if (verbose) { vpi_printf(const_cast(" - Removing callback %s and re-registering\n"), cb_reason_to_string(cb)); } int ret = vpi_remove_cb(vh_registered_cbs[cb]); vh_registered_cbs[cb].freed(); CHECK_RESULT(ret, 1); vh_registered_cbs[cb] = vpi_register_cb(&cb_data_testcase); break; } case POST_REMOVE: { if (verbose) { vpi_printf(const_cast(" - Removing callback %s\n"), cb_reason_to_string(cb)); } int ret = vpi_remove_cb(vh_registered_cbs[cb]); vh_registered_cbs[cb].freed(); CHECK_RESULT(ret, 1); break; } default: if (verbose) vpi_printf(const_cast(" - No change\n")); break; } return 0; } void reset_expected() { for (int idx = 0; idx < CB_COUNT; idx++) callbacks_expected_called[idx] = false; } void cb_will_be_called(const int cb) { callback_expected_counts[cb] = callback_expected_counts[cb] + 1; callbacks_expected_called[cb] = true; } static int test_callbacks(p_cb_data cb_data) { t_cb_data cb_data_testcase; bzero(&cb_data_testcase, sizeof(cb_data_testcase)); if (verbose) vpi_printf(const_cast(" Checking callback results\n")); // Check results from previous loop int cb = *cb_iter; auto count = callback_counts[cb]; auto exp_count = callback_expected_counts[cb]; CHECK_RESULT(count, exp_count); #if !defined(IS_VPI) bool called = callbacks_called[cb]; bool exp_called = callbacks_expected_called[cb]; CHECK_RESULT(called, exp_called); #endif // Update expected values based on state of callback in next time through main loop reset_expected(); const int current_state = *state_iter; const int next_state = (current_state + 1) % cb_states.size(); switch (next_state) { case PRE_REGISTER: case ACTIVE: case ACTIVE_AGAIN: case REM_REREG_ACTIVE: { cb_will_be_called(*cb_iter); break; } default: break; } int ret = register_cb(next_state); if (ret) return ret; // Update iterators for next loop ++state_iter; if (state_iter == cb_states.cend()) { ++cb_iter; state_iter = cb_states.cbegin(); } // Re-register this cb for next time step if (cb_iter != cbs_to_test.cend()) { if (verbose) { vpi_printf(const_cast(" Re-registering test_callbacks for next loop\n")); } t_cb_data cb_data_n; bzero(&cb_data_n, sizeof(cb_data_n)); s_vpi_time t1; cb_data_n.reason = cbAfterDelay; t1.type = vpiSimTime; t1.high = 0; t1.low = 10; cb_data_n.time = &t1; cb_data_n.cb_rtn = test_callbacks; TestVpiHandle vh_test_cb = vpi_register_cb(&cb_data_n); CHECK_RESULT_NZ(vh_test_cb); } return ret; } #ifdef IS_VPI static int toggle_clock(p_cb_data data) { s_vpi_value val; s_vpi_time time = {vpiSimTime, 0, 0, 0}; val.format = vpiIntVal; vpi_get_value(clk_h, &val); val.value.integer = !val.value.integer; vpi_put_value(clk_h, &val, &time, vpiInertialDelay); s_vpi_time cur_time = {vpiSimTime, 0, 0, 0}; vpi_get_time(0, &cur_time); if (cur_time.low < 100 && !got_error) { t_cb_data cb_data; bzero(&cb_data, sizeof(cb_data)); time.low = 5; cb_data.reason = cbAfterDelay; cb_data.time = &time; cb_data.cb_rtn = toggle_clock; vpi_register_cb(&cb_data); } return 0; } #endif static int register_test_callback(p_cb_data data) { t_cb_data cb_data; bzero(&cb_data, sizeof(cb_data)); s_vpi_time t1; if (verbose) vpi_printf(const_cast(" Registering test_cbs Timed callback\n")); cb_data.reason = cbAfterDelay; t1.type = vpiSimTime; t1.high = 0; t1.low = 10; cb_data.time = &t1; cb_data.cb_rtn = test_callbacks; TestVpiHandle vh_test_cb = vpi_register_cb(&cb_data); CHECK_RESULT_NZ(vh_test_cb); cb_iter = cbs_to_test.cbegin(); state_iter = cb_states.cbegin(); #ifdef IS_VPI t1.low = 1; cb_data.cb_rtn = toggle_clock; TestVpiHandle vh_toggle_cb = vpi_register_cb(&cb_data); CHECK_RESULT_NZ(vh_toggle_cb); clk_h = vpi_handle_by_name(const_cast("t.clk"), 0); CHECK_RESULT_NZ(clk_h); #endif return 0; } #ifdef IS_VPI static int end_of_sim_cb(p_cb_data cb_data) { if (!got_error) fprintf(stdout, "*-* All Finished *-*\n"); return 0; } // cver entry void vpi_compat_bootstrap(void) { t_cb_data cb_data; bzero(&cb_data, sizeof(cb_data)); { vpi_printf(const_cast("register start-of-sim callback\n")); cb_data.reason = cbStartOfSimulation; cb_data.time = 0; cb_data.cb_rtn = register_test_callback; vpi_register_cb(&cb_data); } { cb_data.reason = cbEndOfSimulation; cb_data.time = 0; cb_data.cb_rtn = end_of_sim_cb; vpi_register_cb(&cb_data); } } // icarus entry void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0}; #else int main(int argc, char** argv) { const std::unique_ptr contextp{new VerilatedContext}; uint64_t sim_time = 100; bool cbs_called; contextp->commandArgs(argc, argv); const std::unique_ptr topp{new VM_PREFIX{contextp.get(), // Note null name - we're flattening it out ""}}; if (verbose) VL_PRINTF("-- { Sim Time %" PRId64 " } --\n", contextp->time()); register_test_callback(nullptr); topp->eval(); topp->clk = 0; contextp->timeInc(1); while (contextp->time() < sim_time && !contextp->gotFinish()) { if (verbose) { VL_PRINTF("-- { Sim Time %" PRId64 " , Callback %s (%d) , Testcase State %d } --\n", contextp->time(), cb_reason_to_string(*cb_iter), *cb_iter, *state_iter); } topp->eval(); for (const auto& i : cbs_to_test) { if (verbose) { VL_PRINTF(" Calling %s (%d) callbacks\n >>>>\n", cb_reason_to_string(i), i); } if (i == cbValueChange) { cbs_called = VerilatedVpi::callValueCbs(); } else { cbs_called = VerilatedVpi::callCbs(i); } if (verbose) VL_PRINTF(" <<<<\n Any callbacks called? %s\n", cbs_called ? "YES" : "NO"); callbacks_called[i] = cbs_called; } // Always calling this so we can get code coverage on the Verilator debug routine VerilatedVpi::dumpCbs(); VerilatedVpi::callTimedCbs(); int64_t next_time = VerilatedVpi::cbNextDeadline(); contextp->time(next_time); if (next_time == -1 && !contextp->gotFinish()) { if (verbose) VL_PRINTF("-- { Sim Time %" PRId64 " , No more testcases } --\n", contextp->time()); if (got_error) { vl_stop(__FILE__, __LINE__, "TOP-cpp"); } else { VL_PRINTF("*-* All Finished *-*\n"); contextp->gotFinish(true); } } // Count updates on rising edge, so cycle through falling edge as well topp->clk = !topp->clk; topp->eval(); topp->clk = !topp->clk; } if (!contextp->gotFinish()) { vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); } topp->final(); return 0; } #endif verilator-5.042/test_regress/t/t_math_concat64.v0000644000542200017500000001526115101701376022237 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc = 1; reg [127:0] i; wire [127:0] q1; wire [127:0] q32; wire [127:0] q64; wire [ 63:0] q64_low; // verilog_format: off assign q1 = { i[24*4], i[25*4], i[26*4], i[27*4], i[28*4], i[29*4], i[30*4], i[31*4], i[16*4], i[17*4], i[18*4], i[19*4], i[20*4], i[21*4], i[22*4], i[23*4], i[8*4], i[9*4], i[10*4], i[11*4], i[12*4], i[13*4], i[14*4], i[15*4], i[0*4], i[1*4], i[2*4], i[3*4], i[4*4], i[5*4], i[6*4], i[7*4], i[24*4+1], i[25*4+1], i[26*4+1], i[27*4+1], i[28*4+1], i[29*4+1], i[30*4+1], i[31*4+1], i[16*4+1], i[17*4+1], i[18*4+1], i[19*4+1], i[20*4+1], i[21*4+1], i[22*4+1], i[23*4+1], i[8*4+1], i[9*4+1], i[10*4+1], i[11*4+1], i[12*4+1], i[13*4+1], i[14*4+1], i[15*4+1], i[0*4+1], i[1*4+1], i[2*4+1], i[3*4+1], i[4*4+1], i[5*4+1], i[6*4+1], i[7*4+1], i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2], i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2], i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2], i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2], i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3], i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3], i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3], i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]}; assign q64[127:64] = { i[24*4], i[25*4], i[26*4], i[27*4], i[28*4], i[29*4], i[30*4], i[31*4], i[16*4], i[17*4], i[18*4], i[19*4], i[20*4], i[21*4], i[22*4], i[23*4], i[8*4], i[9*4], i[10*4], i[11*4], i[12*4], i[13*4], i[14*4], i[15*4], i[0*4], i[1*4], i[2*4], i[3*4], i[4*4], i[5*4], i[6*4], i[7*4], i[24*4+1], i[25*4+1], i[26*4+1], i[27*4+1], i[28*4+1], i[29*4+1], i[30*4+1], i[31*4+1], i[16*4+1], i[17*4+1], i[18*4+1], i[19*4+1], i[20*4+1], i[21*4+1], i[22*4+1], i[23*4+1], i[8*4+1], i[9*4+1], i[10*4+1], i[11*4+1], i[12*4+1], i[13*4+1], i[14*4+1], i[15*4+1], i[0*4+1], i[1*4+1], i[2*4+1], i[3*4+1], i[4*4+1], i[5*4+1], i[6*4+1], i[7*4+1]}; assign q64[63:0] = { i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2], i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2], i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2], i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2], i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3], i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3], i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3], i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]}; assign q64_low = { i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2], i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2], i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2], i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2], i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3], i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3], i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3], i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]}; assign q32[127:96] = { i[24*4], i[25*4], i[26*4], i[27*4], i[28*4], i[29*4], i[30*4], i[31*4], i[16*4], i[17*4], i[18*4], i[19*4], i[20*4], i[21*4], i[22*4], i[23*4], i[8*4], i[9*4], i[10*4], i[11*4], i[12*4], i[13*4], i[14*4], i[15*4], i[0*4], i[1*4], i[2*4], i[3*4], i[4*4], i[5*4], i[6*4], i[7*4]}; assign q32[95:64] = { i[24*4+1], i[25*4+1], i[26*4+1], i[27*4+1], i[28*4+1], i[29*4+1], i[30*4+1], i[31*4+1], i[16*4+1], i[17*4+1], i[18*4+1], i[19*4+1], i[20*4+1], i[21*4+1], i[22*4+1], i[23*4+1], i[8*4+1], i[9*4+1], i[10*4+1], i[11*4+1], i[12*4+1], i[13*4+1], i[14*4+1], i[15*4+1], i[0*4+1], i[1*4+1], i[2*4+1], i[3*4+1], i[4*4+1], i[5*4+1], i[6*4+1], i[7*4+1]}; assign q32[63:32] = { i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2], i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2], i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2], i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2]}; assign q32[31:0] = { i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3], i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3], i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3], i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]}; // verilog_format: on always @(posedge clk) begin if (cyc != 0) begin cyc <= cyc + 1; `ifdef TEST_VERBOSE $write("%x %x\n", q1, i); `endif if (cyc == 1) begin i <= 128'hed388e646c843d35de489bab2413d770; end if (cyc == 2) begin i <= 128'h0e17c88f3d5fe51a982646c8e2bd68c3; if (q1 != 128'h06f0b17c6551e269e3ab07723b26fb10) $stop; if (q1 != q32) $stop; if (q1 != q64) $stop; if (q1[63:0] != q64_low) $stop; end if (cyc == 3) begin i <= 128'he236ddfddddbdad20a48e039c9f395b8; if (q1 != 128'h8c6f018c8a992c979a3e7859f29ac36d) $stop; if (q1 != q32) $stop; if (q1 != q64) $stop; if (q1[63:0] != q64_low) $stop; end if (cyc == 4) begin i <= 128'h45e0eb7642b148537491f3da147e7f26; if (q1 != 128'hf45fc07e4fa8524cf9571425f17f9ad7) $stop; if (q1 != q32) $stop; if (q1 != q64) $stop; if (q1[63:0] != q64_low) $stop; end if (cyc == 9) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.042/test_regress/t/t_order_dpi_export_5.py0000755000542200017500000000105615101701376023564 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_module_input_default_value_2_bad.out0000644000542200017500000000056115101701376026577 0ustar mahmoudyfreeshell%Error-ASSIGNIN: t/t_module_input_default_value_2_bad.v:17:5: Assigning to input/const variable: 'i' : ... note: In instance 't.u_dut_should_fail_compile1' 17 | i = 1'b0; | ^ ... For error description see https://verilator.org/warn/ASSIGNIN?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_interface_param_dependency.v0000644000542200017500000002070115101701376025116 0ustar mahmoudyfreeshell// DESCRIPTION: Test interface parameter dependency resolution // // Test that interface/modport parameters can be accessed when the // interface/modport is an IO port of the module. // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2025 by Paul Swirhun // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkd(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); interface TEST_IF #( parameter int FOO = 1, parameter int BAR = FOO * 10 ); logic [31:0] data; modport mp(input data); endinterface module submod_iface ( output logic [31:0] result, TEST_IF iface ); assign result = iface.FOO + iface.BAR; endmodule module submod_modport ( output logic [31:0] result, TEST_IF.mp mp ); assign result = mp.FOO + mp.BAR; endmodule module submod_assert2 #( parameter int EXPECTED_FOO = 0, parameter int EXPECTED_BAR = 0 ) ( TEST_IF iface ); initial begin // Verify the dependent parameter BAR is correctly computed in the module if (iface.FOO != EXPECTED_FOO) begin $error("FOO mismatch in module: expected %0d, got %0d", EXPECTED_FOO, iface.FOO); end if (iface.BAR != EXPECTED_BAR) begin $error("BAR dependency failed in module: expected %0d, got %0d", EXPECTED_BAR, iface.BAR); end end endmodule // Test module that asserts interface parameter values - catches dependency bugs module submod_assert #( parameter int EXPECTED_FOO = 0, parameter int EXPECTED_BAR = 0 ) ( TEST_IF iface ); // Make a new interface with inherited parameters and pass it to a submodule // with inherited expectations. TEST_IF #( .FOO(iface.FOO), .BAR(iface.BAR) ) iface2 (); // Test mixed parameters: constant + interface port reference TEST_IF #( .FOO(7), // Constant parameter .BAR(iface.FOO) // References interface port ) iface_mixed (); // Test specifying only FOO parameter (BAR should use default calculation) TEST_IF #( .FOO(iface.FOO) // Only FOO specified, BAR = FOO * 10 ) iface_foo_only (); // Test specifying only BAR parameter (FOO should use default) TEST_IF #( .BAR(iface.BAR) // Only BAR specified, FOO = default (1) ) iface_bar_only (); // Test no parameters specified (both should use defaults) TEST_IF iface_defaults (); submod_assert2 #( .EXPECTED_FOO(EXPECTED_FOO), .EXPECTED_BAR(EXPECTED_BAR) ) u_submod_assert2 ( .iface(iface2) ); // Test the mixed parameter interface submod_assert2 #( .EXPECTED_FOO(7), .EXPECTED_BAR(EXPECTED_FOO) // BAR should get iface.FOO value ) u_mixed_assert ( .iface(iface_mixed) ); // Test FOO-only interface submod_assert2 #( .EXPECTED_FOO(EXPECTED_FOO), .EXPECTED_BAR(EXPECTED_FOO * 10) // BAR = FOO * 10 ) u_foo_only_assert ( .iface(iface_foo_only) ); // Test BAR-only interface submod_assert2 #( .EXPECTED_FOO(1), // FOO = default .EXPECTED_BAR(EXPECTED_BAR) // BAR = specified value ) u_bar_only_assert ( .iface(iface_bar_only) ); // Test defaults interface submod_assert2 #( .EXPECTED_FOO(1), // FOO = default .EXPECTED_BAR(10) // BAR = FOO * 10 = 1 * 10 ) u_defaults_assert ( .iface(iface_defaults) ); initial begin // Verify the dependent parameter BAR is correctly computed in the module if (iface.FOO != EXPECTED_FOO) begin $error("FOO mismatch in module: expected %0d, got %0d", EXPECTED_FOO, iface.FOO); end if (iface.BAR != EXPECTED_BAR) begin $error("BAR dependency failed in module: expected %0d, got %0d", EXPECTED_BAR, iface.BAR); end // Verify all interface instances have correct parameter values if (iface2.FOO != EXPECTED_FOO) begin $error("iface2.FOO mismatch: expected %0d, got %0d", EXPECTED_FOO, iface2.FOO); end if (iface2.BAR != EXPECTED_BAR) begin $error("iface2.BAR mismatch: expected %0d, got %0d", EXPECTED_BAR, iface2.BAR); end if (iface_mixed.FOO != 7) begin $error("iface_mixed.FOO mismatch: expected 7, got %0d", iface_mixed.FOO); end if (iface_mixed.BAR != EXPECTED_FOO) begin $error("iface_mixed.BAR mismatch: expected %0d, got %0d", EXPECTED_FOO, iface_mixed.BAR); end if (iface_foo_only.FOO != EXPECTED_FOO) begin $error("iface_foo_only.FOO mismatch: expected %0d, got %0d", EXPECTED_FOO, iface_foo_only.FOO); end if (iface_foo_only.BAR != EXPECTED_FOO * 10) begin $error("iface_foo_only.BAR mismatch: expected %0d, got %0d", EXPECTED_FOO * 10, iface_foo_only.BAR); end if (iface_bar_only.FOO != 1) begin $error("iface_bar_only.FOO mismatch: expected 1, got %0d", iface_bar_only.FOO); end if (iface_bar_only.BAR != EXPECTED_BAR) begin $error("iface_bar_only.BAR mismatch: expected %0d, got %0d", EXPECTED_BAR, iface_bar_only.BAR); end if (iface_defaults.FOO != 1) begin $error("iface_defaults.FOO mismatch: expected 1, got %0d", iface_defaults.FOO); end if (iface_defaults.BAR != 10) begin $error("iface_defaults.BAR mismatch: expected 10, got %0d", iface_defaults.BAR); end end endmodule // Test parameterized interface chain: module parameter -> interface parameter -> submodule module param_chain #( parameter int TOP_PARAM = 3 ) ( output logic [31:0] result ); // Interface gets parameter from module parameter TEST_IF #(.FOO(TOP_PARAM)) chain_iface (); // Submodule uses interface (FOO=3, BAR should be 30) submod_iface chain_sub ( .result(result), .iface (chain_iface) ); // Assert the chain works correctly submod_assert #( .EXPECTED_FOO(TOP_PARAM), .EXPECTED_BAR(TOP_PARAM * 10) ) chain_assert ( .iface(chain_iface) ); endmodule module t; // Test case 1: FOO specified, BAR should be FOO*10 TEST_IF #(.FOO(5)) tif_1 (); // Test case 2: Both FOO and BAR specified explicitly TEST_IF #( .FOO(6), .BAR(66) ) tif_2 (); // Test case 3: Only BAR specified, FOO should be default TEST_IF #(.BAR(77)) tif_3 (); // Test case 4: Default parameters TEST_IF tif_4 (); logic [8:0][31:0] result; // Test interface as port parameter submod_iface u0 ( .result(result[0]), .iface (tif_1) ); submod_iface u1 ( .result(result[1]), .iface (tif_2) ); submod_iface u2 ( .result(result[2]), .iface (tif_3) ); submod_iface u3 ( .result(result[3]), .iface (tif_4) ); // Test modport as port parameter submod_modport u4 ( .result(result[4]), .mp(tif_1) ); submod_modport u5 ( .result(result[5]), .mp(tif_2) ); submod_modport u6 ( .result(result[6]), .mp(tif_3) ); submod_modport u7 ( .result(result[7]), .mp(tif_4) ); // Test that interface parameter dependencies are correctly resolved in modules submod_assert #( .EXPECTED_FOO(5), .EXPECTED_BAR(50) ) assert1 ( .iface(tif_1) ); // Test parameterized interface chain: module param -> interface param -> submodule param_chain #(.TOP_PARAM(4)) chain_test (.result(result[8])); // Allow hierarchichal references to locally declared interfaces only when HIERPARAM is waived /* verilator lint_off HIERPARAM */ TEST_IF #(.FOO(3)) test_if_local (); logic [31:0] foo_local_1 = 32'(test_if_local.FOO); logic [31:0] bar_local_1 = 32'(test_if_local.BAR); localparam FOO_LOCAL = test_if_local.FOO; localparam BAR_LOCAL = test_if_local.BAR; logic [31:0] foo_local_2 = 32'(FOO_LOCAL); logic [31:0] bar_local_2 = 32'(BAR_LOCAL); /* verilator lint_on HIERPARAM */ initial begin // Verify modules can access interface parameters correctly `checkd(result[0], 55); // 5 + 50 `checkd(result[1], 72); // 6 + 66 `checkd(result[2], 78); // 1 + 77 (FOO default + BAR explicit) `checkd(result[3], 11); // 1 + 10 (both defaults, BAR = FOO*10) // Verify modport access gives same results `checkd(result[4], 55); // 5 + 50 `checkd(result[5], 72); // 6 + 66 `checkd(result[6], 78); // 1 + 77 `checkd(result[7], 11); // 1 + 10 // Verify parameterized chain works `checkd(result[8], 44); // 4 + 40 (TOP_PARAM=4, so FOO=4, BAR=40) `checkd(foo_local_1, 3); `checkd(bar_local_1, 30); `checkd(foo_local_2, 3); `checkd(bar_local_2, 30); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_enum_param_class.py0000755000542200017500000000073415101701376023303 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_param_sel.v0000644000542200017500000000443615101701376021552 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [31:0] out; // From test of Test.v // End of automatics Test #(16,2) test (/*AUTOINST*/ // Outputs .out (out[31:0]), // Inputs .clk (clk), .in (in[31:0])); // Aggregate outputs into a single result vector wire [63:0] result = {32'h0, out}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'hf9b3a5000165ed38 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs out, // Inputs clk, in ); input clk; input [31:0] in; output [31:0] out; parameter N = 0; parameter PASSDOWN = 1; add #(PASSDOWN) add (.in (in[(2*N)-1:(0*N)]), .out (out)); endmodule module add (/*AUTOARG*/ // Outputs out, // Inputs in ); parameter PASSDOWN = 9999; input [31:0] in; output [31:0] out; assign out = in + PASSDOWN; endmodule verilator-5.042/test_regress/t/t_math_signed5.py0000755000542200017500000000100515101701376022331 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--binary --no-timing']) test.execute() test.passes() verilator-5.042/test_regress/t/t_time_timeunit.py0000755000542200017500000000073415101701376022646 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_flag_noop_bad.py0000755000542200017500000000123115101701376022535 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.run(cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator", "t_flag_noop_bad.v"], fails=True, logfile=test.obj_dir + "/sim.log", expect_filename=test.golden_filename, verilator_run=True) test.passes() verilator-5.042/test_regress/t/t_structu_dataType_assignment_bad.out0000644000542200017500000000063315101701376026546 0ustar mahmoudyfreeshell%Error: t/t_structu_dataType_assignment_bad.v:19:26: Assignment pattern key not supported/understood: CONST '?32?sh1' : ... note: In instance 'top' 19 | DEF_struct DEF_bad = '{1: 5, default: 10}; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_case_inside_call_count.v0000644000542200017500000000226315101701376024254 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Cls; int callCount = 0; int callCount2 = 0; int value = 6; bit[5:0] value2 = 6; function int get(); callCount += 1; return value; endfunction function bit[5:0] get2(); callCount2 += 1; return value2; endfunction function int getPure(); return callCount2; endfunction endclass module t; Cls c; initial begin bit called = 0; c = new; case (c.get()) inside [0:5]: $stop; [6:6]: called = 1; [7:100]: $stop; default: $stop; endcase if (!called) $stop; if (c.callCount != 1) $stop; called = 0; case (c.get2()) inside [0:5]: $stop; [6:6]: called = 1; [7:100]: $stop; default: $stop; endcase if (!called) $stop; called = 0; case (c.getPure()) inside [0:1]: called = 1; [2:10]: $stop; default: $stop; endcase if (!called) $stop; if (c.callCount2 != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_inst_long.py0000755000542200017500000000250315101701376021762 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = os.path.join(test.obj_dir, "t_inst_long.v") length = 200 longname = "long_" * int((length + 4) / 5) def gen_top(filename): with open(filename, 'w', encoding="utf8") as fh: fh.write("// Generated by t_inst_long.py\n") fh.write("module t;\n") fh.write("\n") fh.write(" " + longname + " inst ();\n") fh.write("\n") fh.write("endmodule\n") def gen_sub(filename): with open(filename, 'w', encoding="utf8") as fh: fh.write("// Generated by t_inst_long.py\n") fh.write("module " + longname + ";\n") fh.write("\n") fh.write(" initial begin\n") fh.write(" $write(\"*-* All Finished *-*\\n\");\n") fh.write(" $finish;\n") fh.write(" end\n") fh.write("endmodule\n") gen_top(test.top_filename) gen_sub(os.path.join(test.obj_dir, longname + ".v")) test.compile() test.passes() verilator-5.042/test_regress/t/t_math_real_round.py0000755000542200017500000000073415101701376023135 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_dpi_2exp_bad.out0000644000542200017500000000054415101701376022465 0ustar mahmoudyfreeshell%Error: t/t_dpi_2exp_bad.v:12:45: Function was already DPI Exported, duplicate not allowed: 'dpix_twice' 12 | export "DPI-C" dpix_t_int_renamed = task dpix_twice; | ^~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_mod_interface_clocking.py0000755000542200017500000000077115101701376024443 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_force_func.py0000755000542200017500000000102715101701376022077 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["--binary"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_flag_structs_packed.py0000755000542200017500000000077615101701376024007 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.compile(verilator_flags2=['--structs-packed']) test.execute() test.passes() verilator-5.042/test_regress/t/t_assigndly_dynamic.py0000755000542200017500000000077115101701376023474 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_gen_for_interface.v0000644000542200017500000000122115101701376023233 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Johan Bjork. // SPDX-License-Identifier: CC0-1.0 parameter N = 5; interface intf; logic [N-1:0] data; endinterface module t ( input logic clk ); intf localinterface [N-1:0](); generate genvar i,j; for(i = 0; i < N; i++) begin logic [N-1:0] dummy; for(j = 0; j < N; j++) begin assign dummy[j] = localinterface[j].data[i]; end end endgenerate initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_debug_emitv.out0000644000542200017500000004417715101701376022451 0ustar mahmoudyfreeshellmodule Vt_debug_emitv_t; input logic clk; input logic in; typedef enum logic [2:0] { ZERO = 3'h0, ONE = 3'h1 } e_t; typedef struct packed { logic [2:0] a; } ps_t; typedef struct { logic signed [2:0] a; } us_t; typedef union { logic a; } union_t; const struct packed { logic [2:0] a; } ps[0:2]; struct { logic signed [2:0] a; } us; union { logic a; } unu; integer signed i1; int signed array[0:2]; initial begin array = '{0:32'sh1, 1:32'sh2, 2:32'sh3}; end logic [63:32] downto_32; downto_32 = 32'h0; function ident; input int signed value; begin : label0 ident = value; disable label0; end endfunction Iface the_ifaces[3:0] (); initial begin begin if ($test$plusargs("HELLO")) begin $display("Hello argument found."); end if ((Pkg::FOO == 'sh0)) begin $write(""); end if ((ZERO == 'sh0)) begin $write(""); end if ($value$plusargs("TEST=%d", i1)) begin $display("value was %~", i1); end else begin $display("+TEST= not found"); end if (downto_32[33]) begin $write(""); end if (downto_32[(ident('sh21) - 'h20)[5:0] + 32 +:1]) begin $write(""); end if ((| downto_32[48:40])) begin $write(""); end if ((| downto_32[57:55])) begin $write(""); end if ((| downto_32[60:54])) begin $write(""); end if (the_ifaces[2].ifsig) begin $write(""); end #1; $write("After #1 delay"); end end bit [6:5] [4:3] [2:1] arraymanyd[10:11][12:13][14:15]; logic [15:0] pubflat; logic [15:0] pubflat_r; logic [15:0] pubflat_w; assign pubflat_w = pubflat; int signed fd; int signed i; int signed q[$]; int signed qb[$:'sh3]; int signed assoc[string]; int signed assocassoc[string][real]; int signed dyn[]; typedef struct packed { logic nn1; } nested_named_t; typedef struct packed { struct packed { logic nn2; } nested_anonymous; struct packed { logic nn1; } nested_named; logic [11:10] nn3; } nibble_t; struct packed { struct packed { logic nn2; } nested_anonymous; struct packed { logic nn1; } nested_named; logic [11:10] nn3; } [5:4] nibblearray[3:2]; task t; $display("stmt"); endtask function f; input int signed v; begin : label1 $display("stmt"); f = ((v == 'sh0) ? 'sh63 : ((~ v) + 'sh1)); disable label1; end endfunction initial begin begin : unnamedblk1 int signed other; begin begin : unnamedblk2 int signed i; i = 'sh0; while ((i < 'sh3)) begin begin other = f(i); $display("stmt %~ %~", i, other); t(); end i = (i + 'h1); end end end begin : named $display("stmt"); end end end final begin begin $display("stmt"); end end always @( in) begin begin $display("stmt"); end end always @(posedge clk) begin begin $display("posedge clk"); pubflat_r <= pubflat_w; end end always @(negedge clk) begin begin $display("negedge clk, pfr = %x", pubflat_r); end end int signed cyc; int signed fo; int signed sum; real r; string str; int signed mod_val; int signed mod_res; always @(posedge clk) begin begin cyc <= (cyc + 'sh1); r <= (r + 0.01); fo = cyc; sub.inc(fosum); sum = sub.f(sum); $display("[%0t] sum = %~", $time, sum); $display("a?= %d", ($c('sh1) ? $c('sh14) : $c('sh1e))); $c(;); $display("%d", $c(0)); fd = $fopen("/dev/null"); ; $fclose(fd); fd = $fopen("/dev/null", "r"); ; $fgetc(fd); $fflush(fd); $fscanf(fd, "%d", sum); ; $fdisplay(32'h69203d20, "%~", sum); $fwrite(fd, "hello"); $readmemh(string'(fd), array); $readmemh(string'(fd), array, 'sh0); $readmemh(string'(fd), array, 'sh0, 'sh0); sum = 'sh0; begin : unnamedblk3 int signed i; i = 'sh0; begin : label2 while ((i < cyc)) begin begin sum = (sum + i); if ((sum > 'sha)) begin disable label2; end else begin sum = (sum + 'sh1); end end i = (i + 'h1); end end end if ((cyc == 'sh63)) begin $finish; end if ((cyc == 'sh64)) begin $stop; end case (in) // synopsys full_case parallel_case'sh1: begin $display("1"); end default: begin $display("default"); end endcase priority case (in) 'sh1: begin $display("1"); end default: begin $display("default"); end endcase unique case (in) 'sh1: begin $display("1"); end default: begin $display("default"); end endcase unique0 case (in) 'sh1: begin $display("1"); end default: begin $display("default"); end endcase if (in) begin $display("1"); end else begin $display("0"); end priority if (in) begin $display("1"); end else begin $display("0"); end unique if (in) begin $display("1"); end else begin $display("0"); end unique0 if (in) begin $display("1"); end else begin $display("0"); end $display("%~%~", $past(cyc), $past(cyc, 'sh1)); str = $sformatf("cyc=%~", cyc); ; $display("str = %@", str); $display("%% [%t] [%^] to=%o td=%d", $time, $realtime, $time, $time); $sscanf(40'h666f6f3d35, "foo=%d", i); ; $printtimescale; if ((i != 'sh5)) begin $stop; end sum = $random(); sum = $random('sha); sum = $urandom(); sum = $urandom('sha); if ((PKG_PARAM != 'sh1)) begin $stop; end sub.r = 62.0; mod_res = (mod_val % 'sh5); $display("%g", $log10(r)); $display("%g", $ln(r)); $display("%g", $exp(r)); $display("%g", $sqrt(r)); $display("%g", $floor(r)); $display("%g", $ceil(r)); $display("%g", $sin(r)); $display("%g", $cos(r)); $display("%g", $tan(r)); $display("%g", $asin(r)); $display("%g", $acos(r)); $display("%g", $atan(r)); $display("%g", $sinh(r)); $display("%g", $cosh(r)); $display("%g", $tanh(r)); $display("%g", $asinh(r)); $display("%g", $acosh(r)); $display("%g", $atanh(r)); if ($sampled(cyc[1])) begin $write(""); end if ($rose(cyc)) begin $write(""); end if ($fell(cyc)) begin $write(""); end if ($stable(cyc)) begin $write(""); end if ((! $stable(cyc))) begin $write(""); end if ($past(cyc[1])) begin $write(""); end if ($rose(cyc, @( clk))) begin $write(""); end if ($fell(cyc, @( clk))) begin $write(""); end if ($stable(cyc, @( clk))) begin $write(""); end if ((! $stable(cyc, @( clk)))) begin $write(""); end if ($past(cyc[1], 'sh5)) begin $write(""); end force sum = 'sha; begin : unnamedblk1_1 integer signed __Vrepeat0; __Vrepeat0 = 'sh2; while ((__Vrepeat0 > 32'h0)) begin if ((sum != 'sha)) begin $stop; end __Vrepeat0 = (__Vrepeat0 - 32'h1); end end release sum; end end property p; @(posedge clk) ##1 sum[0] endproperty property p1; @( clk) sum[0] endproperty property p2; @(posedge clk) disable iff (cyc == 'sh1) ##1 sum[0] endproperty assert property (@( clk) (! ##1 in) ) begin end else begin end initial begin begin begin : assert_simple_immediate_else assert ('sh0) begin end else begin $display("fail"); end end begin : assert_simple_immediate_stmt assert ('sh0) begin $display("pass"); end else begin end end begin : assert_simple_immediate_stmt_else assert ('sh0) begin $display("pass"); end else begin $display("fail"); end end begin : assume_simple_immediate assume ('sh0) begin end else begin end end begin : assume_simple_immediate_else assume ('sh0) begin end else begin $display("fail"); end end begin : assume_simple_immediate_stmt assume ('sh0) begin $display("pass"); end else begin end end begin : assume_simple_immediate_stmt_else assume ('sh0) begin $display("pass"); end else begin $display("fail"); end end end end always begin begin : assert_observed_deferred_immediate assert #0 ('sh0) begin end else begin end end end always begin begin : assert_observed_deferred_immediate_else assert #0 ('sh0) begin end else begin $display("fail"); end end end always begin begin : assert_observed_deferred_immediate_stmt assert #0 ('sh0) begin $display("pass"); end else begin end end end always begin begin : assert_observed_deferred_immediate_stmt_else assert #0 ('sh0) begin $display("pass"); end else begin $display("fail"); end end end always begin begin : assume_observed_deferred_immediate assume #0 ('sh0) begin end else begin end end end always begin begin : assume_observed_deferred_immediate_else assume #0 ('sh0) begin end else begin $display("fail"); end end end always begin begin : assume_observed_deferred_immediate_stmt assume #0 ('sh0) begin $display("pass"); end else begin end end end always begin begin : assume_observed_deferred_immediate_stmt_else assume #0 ('sh0) begin $display("pass"); end else begin $display("fail"); end end end always begin begin : assert_final_deferred_immediate assert final ('sh0) begin end else begin end end end always begin begin : assert_final_deferred_immediate_else assert final ('sh0) begin end else begin $display("fail"); end end end always begin begin : assert_final_deferred_immediate_stmt assert final ('sh0) begin $display("pass"); end else begin end end end always begin begin : assert_final_deferred_immediate_stmt_else assert final ('sh0) begin $display("pass"); end else begin $display("fail"); end end end always begin begin : assume_final_deferred_immediate assume final ('sh0) begin end else begin end end end always begin begin : assume_final_deferred_immediate_else assume final ('sh0) begin end else begin $display("fail"); end end end always begin begin : assume_final_deferred_immediate_stmt assume final ('sh0) begin $display("pass"); end else begin end end end always begin begin : assume_final_deferred_immediate_stmt_else assume final ('sh0) begin $display("pass"); end else begin $display("fail"); end end end property prop; @(posedge clk) 'sh0 endproperty begin : assert_concurrent assert property ( prop ) begin end else begin end end begin : assert_concurrent_else assert property ( prop ) begin end else begin $display("fail"); end end begin : assert_concurrent_stmt assert property ( prop ) begin $display("pass"); end else begin end end begin : assert_concurrent_stmt_else assert property ( prop ) begin $display("pass"); end else begin $display("fail"); end end begin : assume_concurrent assume property ( prop ) begin end else begin end end begin : assume_concurrent_else assume property ( prop ) begin end else begin $display("fail"); end end begin : assume_concurrent_stmt assume property ( prop ) begin $display("pass"); end else begin end end begin : assume_concurrent_stmt_else assume property ( prop ) begin $display("pass"); end else begin $display("fail"); end end begin : cover_concurrent cover property ( prop ) begin end end begin : cover_concurrent_stmt cover property ( prop ) begin $display("pass"); end end int signed a; int signed ao; initial begin begin : assert_intrinsic assert ((| $_EXPRSTMT( ao = (a); , ); )) begin end else begin end end end restrict (@(posedge clk) ##1 a[0] ); endmodule package Vt_debug_emitv___024unit; class Vt_debug_emitv_Cls; int signed member; member = 'sh1; task method; if ((this != this)) begin $stop; end endtask function new; endfunction endclass endpackage interface Vt_debug_emitv_Iface; input logic clk; logic ifsig; modport mp ( input logic ifsig ); endinterface module Vt_debug_emitv_sub; input logic clk; task inc; input int signed i; output int signed o; o = ({32'h1{{1'h0, i[31:1]}}} + 32'h1); endtask function f; input int signed v; begin : label3 if ((v == 'sh0)) begin f = 'sh21; disable label3; end f = ({32'h1{{31'h0, v[2]}}} + 32'h1); disable label3; end endfunction real r; endmodule package Vt_debug_emitv_p; logic pkgvar; endpackage package Vt_debug_emitv_Pkg; logic signed [31:0] PKG_PARAM; typedef enum int signed{ FOO = 32'h0, BAR = 32'h1, BAZ = 32'h2 } enum_t; endpackage verilator-5.042/test_regress/t/t_langext_2_bad.out0000644000542200017500000000072115101701376022633 0ustar mahmoudyfreeshell%Error: t/t_langext_2.v:46:7: syntax error, unexpected IDENTIFIER-for-type 46 | genvar i; | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_langext_2.v:49:21: syntax error, unexpected case 49 | unique0 case (i) | ^~~~ %Error: Cannot continue ... This fatal error may be caused by the earlier error(s); resolve those first. verilator-5.042/test_regress/t/t_interface_wire_bad.py0000755000542200017500000000076615101701376023573 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_constraint_struct.v0000755000542200017500000000501215101701376023371 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by PlanV GmbH. // SPDX-License-Identifier: CC0-1.0 typedef struct packed { bit [7:0] byte_value; int int_value; } PackedStruct; typedef struct { rand bit [7:0] byte_value; rand int int_value; int non_rand_value; // Non-randomized member } UnpackedStruct; class PackedStructTest; rand PackedStruct packed_struct; function new(); packed_struct.byte_value = 8'hA0; packed_struct.int_value = 0; endfunction // Constraint block for packed struct constraint packed_struct_constraint { packed_struct.byte_value == 8'hA0; packed_struct.int_value inside {[0:100]}; } // Self-check function for packed struct function void check(); if (packed_struct.byte_value != 8'hA0) $stop; if (!(packed_struct.int_value inside {[0:100]})) $stop; endfunction endclass class UnpackedStructTest; rand UnpackedStruct unpacked_struct; function new(); unpacked_struct.byte_value = 8'h00; unpacked_struct.int_value = 0; unpacked_struct.non_rand_value = 42; endfunction // Constraint block for unpacked struct constraint unpacked_struct_constraint { unpacked_struct.byte_value inside {8'hA0, 8'hB0, 8'hC0}; unpacked_struct.int_value inside {[50:150]}; } // Self-check function for unpacked struct function void check(); if (!(unpacked_struct.byte_value inside {8'hA0, 8'hB0, 8'hC0})) $stop; if (!(unpacked_struct.int_value inside {[50:150]})) $stop; if (unpacked_struct.non_rand_value != 42) $stop; // Check non-randomized member endfunction endclass module t_constraint_struct; PackedStructTest packed_struct_test; UnpackedStructTest unpacked_struct_test; int success; initial begin // Test packed struct packed_struct_test = new(); repeat(10) begin success = packed_struct_test.randomize(); if (success == 0) $stop; packed_struct_test.check(); // Self-check for packed struct end // Test unpacked struct unpacked_struct_test = new(); repeat(10) begin success = unpacked_struct_test.randomize(); if (success == 0) $stop; unpacked_struct_test.check(); // Self-check for unpacked struct end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_hier_block_threads_bad.py0000755000542200017500000000116415101701376024411 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vltmt') test.lint(fails=True, verilator_flags2=['t/t_hier_block_threads_bad.vlt', '-DWORKERS=8', '--hierarchical'], expect_filename=test.golden_filename, threads=4) test.passes() verilator-5.042/test_regress/t/t_class_param_bad2.v0000644000542200017500000000046015101701376022755 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class Cls #(type PARAMB); endclass module t; Cls c; // Missing type param endmodule verilator-5.042/test_regress/t/t_split_var_2_trace.py0000755000542200017500000000222615101701376023372 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_split_var_0.v" # CI environment offers 2 VCPUs, 2 thread setting causes the following warning. # %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. # So use 6 threads here though it's not optimal in performance, but ok. test.compile( verilator_flags2=['--cc', '--trace-vcd', '--stats', '+define+TEST_ATTRIBUTES', "-fno-dfg"], threads=(6 if test.vltmt else 1)) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.file_grep(test.stats, r'SplitVar,\s+packed variables split due to attribute\s+(\d+)', 12) test.file_grep(test.stats, r'SplitVar,\s+unpacked arrays split due to attribute\s+(\d+)', 27) test.passes() verilator-5.042/test_regress/t/t_flag_wpedantic_bad.out0000644000542200017500000000035715101701376023724 0ustar mahmoudyfreeshell%Error: t/t_flag_wpedantic_bad.v:8:8: syntax error, unexpected global 8 | reg global; | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_gen_assign.v0000644000542200017500000000265215101701376021722 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed into the Public Domain, for any use, // without warranty. // SPDX-License-Identifier: CC0-1.0 `timescale 1ns / 1ps module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc = 0; reg [63:0] crc; reg [31:0] sum; wire [8:0] Output; wire [8:0] Input = crc[8:0]; assigns assigns (/*AUTOINST*/ // Outputs .Output (Output[8:0]), // Inputs .Input (Input[8:0])); always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x q=%x\n", $time, cyc, crc, sum); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 32'h0; end else if (cyc>10 && cyc<90) begin sum <= {sum[30:0],sum[31]} ^ {23'h0, crc[8:0]}; end else if (cyc==99) begin if (sum !== 32'he8bbd130) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module assigns(Input, Output); input [8:0] Input; output [8:0] Output; genvar i; generate for (i = 0; i < 8; i = i + 1) begin : ap assign Output[(i>0) ? i-1 : 8] = Input[(i>0) ? i-1 : 8]; end endgenerate endmodule verilator-5.042/test_regress/t/t_hier_block1_bad.out0000644000542200017500000000236315101701376023136 0ustar mahmoudyfreeshell%Warning-HIERBLOCK: t/t_hier_block1_bad.v:16:8: Top module marked as hierarchical block, ignoring : ... note: In instance 't' : ... Suggest remove verilator hier_block on this module 16 | module t ( | ^ ... For warning description see https://verilator.org/warn/HIERBLOCK?v=latest ... Use "/* verilator lint_off HIERBLOCK */" and lint_on around source to disable this message. %Error: t/t_hier_block1_bad.v:45:32: Modport cannot be used at the hierarchical block boundary : ... note: In instance 't.i_sub1' 45 | module sub1 (byte_ifs.receiver in, byte_ifs.sender out); /*verilator hier_block*/ | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_hier_block1_bad.v:45:52: Modport cannot be used at the hierarchical block boundary : ... note: In instance 't.i_sub1' 45 | module sub1 (byte_ifs.receiver in, byte_ifs.sender out); /*verilator hier_block*/ | ^~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_inst_array_partial.py0000755000542200017500000000073415101701376023661 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_opt_const_cov.py0000755000542200017500000000121615101701376022645 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["-Wno-UNOPTTHREADS", "--stats", "--coverage", "--trace-vcd"]) test.execute() if test.vlt: test.file_grep(test.stats, r'Optimizations, Const bit op reduction\s+(\d+)', 478) test.passes() verilator-5.042/test_regress/t/t_lint_modmissing.v0000644000542200017500000000045115101701376022777 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(input i); // verilator lint_off MODMISSING foobar sub(i); endmodule verilator-5.042/test_regress/t/t_mem_packed.py0000755000542200017500000000073415101701376022057 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_timing_off.py0000755000542200017500000000077115101701376022114 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_func_grey.py0000755000542200017500000000073415101701376021753 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_detectarray_1.v0000644000542200017500000000127215101701376022331 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Simple test of unoptflat // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 localparam ID_MSB = 1; module t (/*AUTOARG*/ // Inputs clk ); input clk; typedef struct packed { logic [ID_MSB:0] id; } context_t; context_t tsb; assign tsb.id = {tsb.id[0], clk}; initial begin tsb.id = 0; end always @(posedge clk or negedge clk) begin `ifdef TEST_VERBOSE $write("tsb.id = %x\n", tsb.id); `endif if (tsb.id[1] != 0) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_var_pinsizes.v0000644000542200017500000000327115101701376022317 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Also check that SystemC is ordering properly module t (/*AUTOARG*/ // Outputs o1, o8, o16, o32, o64, o65, o128, o513, o1a2, o94a3, obv1, obv16, obv1_vlt, obv16_vlt, // Inputs clk, i1, i8, i16, i32, i64, i65, i128, i513, i1a2, i94a3, ibv1, ibv16, ibv1_vlt, ibv16_vlt ); input clk; input i1; input [7:0] i8; input [15:0] i16; input [31:0] i32; input [63:0] i64; input [64:0] i65; input [127:0] i128; input [512:0] i513; input i1a2 [1:0]; input [93:0] i94a3 [2:0]; output logic o1; output logic [7:0] o8; output logic [15:0] o16; output logic [31:0] o32; output logic [63:0] o64; output logic [64:0] o65; output logic [127:0] o128; output logic [512:0] o513; output logic o1a2 [1:0]; output logic [93:0] o94a3 [2:0]; input [0:0] ibv1 /*verilator sc_bv*/; input [15:0] ibv16 /*verilator sc_bv*/; input [0:0] ibv1_vlt; input [15:0] ibv16_vlt; output logic [0:0] obv1 /*verilator sc_bv*/; output logic [15:0] obv16 /*verilator sc_bv*/; output logic [0:0] obv1_vlt; output logic [15:0] obv16_vlt; always @ (posedge clk) begin o1 <= i1; o8 <= i8; o16 <= i16; o32 <= i32; o64 <= i64; o65 <= i65; o128 <= i128; o513 <= i513; obv1 <= ibv1; obv16 <= ibv16; obv1_vlt <= ibv1_vlt; obv16_vlt <= ibv16_vlt; o1a2 <= i1a2; o94a3 <= i94a3; end endmodule verilator-5.042/test_regress/t/t_trace_noflag_bad.out0000644000542200017500000000020715101701376023373 0ustar mahmoudyfreeshell%Error: Testbench C call to 'VerilatedContext::trace()' requires model(s) Verilated with --trace-fst or --trace-vcd option Aborting... verilator-5.042/test_regress/t/t_timing_unset1.out0000644000542200017500000000553115101701376022734 0ustar mahmoudyfreeshell%Error-NEEDTIMINGOPT: t/t_notiming.v:12:8: Use --timing or --no-timing to specify how delays should be handled : ... note: In instance 't' 12 | #1 | ^ ... For error description see https://verilator.org/warn/NEEDTIMINGOPT?v=latest %Error-NEEDTIMINGOPT: t/t_notiming.v:13:8: Use --timing or --no-timing to specify how forks should be handled : ... note: In instance 't' 13 | fork @e; @e; join; | ^~~~ %Error-NEEDTIMINGOPT: t/t_notiming.v:14:8: Use --timing or --no-timing to specify how event controls should be handled : ... note: In instance 't' 14 | @e | ^ %Error-NEEDTIMINGOPT: t/t_notiming.v:15:8: Use --timing or --no-timing to specify how wait statements should be handled : ... note: In instance 't' 15 | wait(x == 4) | ^~~~ %Error-NEEDTIMINGOPT: t/t_notiming.v:16:12: Use --timing or --no-timing to specify how timing controls should be handled : ... note: In instance 't' 16 | x = #1 8; | ^ %Error-NEEDTIMINGOPT: t/t_notiming.v:19:8: Use --timing or --no-timing to specify how event controls should be handled : ... note: In instance 't' 19 | @e | ^ %Error-NEEDTIMINGOPT: t/t_notiming.v:26:12: Use --timing or --no-timing to specify how delays should be handled : ... note: In instance 't' 26 | initial #1 ->e; | ^ %Error-NEEDTIMINGOPT: t/t_notiming.v:27:12: Use --timing or --no-timing to specify how delays should be handled : ... note: In instance 't' 27 | initial #2 $stop; | ^ %Error-NEEDTIMINGOPT: t/t_notiming.v:33:10: Use --timing or --no-timing to specify how mailbox::put() should be handled : ... note: In instance 't' 33 | m.put(i); | ^~~ %Error-NEEDTIMINGOPT: t/t_notiming.v:34:10: Use --timing or --no-timing to specify how mailbox::get() should be handled : ... note: In instance 't' 34 | m.get(i); | ^~~ %Error-NEEDTIMINGOPT: t/t_notiming.v:35:10: Use --timing or --no-timing to specify how mailbox::peek() should be handled : ... note: In instance 't' 35 | m.peek(i); | ^~~~ %Error-NEEDTIMINGOPT: t/t_notiming.v:36:10: Use --timing or --no-timing to specify how semaphore::get() should be handled : ... note: In instance 't' 36 | s.get(); | ^~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_interface_generic_modport_task.v0000644000542200017500000000114515101701376026023 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 interface inf; int v; task setup(); v = 3; endtask modport mp( input v, import setup ); endinterface module GenericModule (interface.mp a); initial begin a.setup(); end endmodule module t; inf inf_inst(); GenericModule genericModule (inf_inst); initial begin #1; if (inf_inst.v != 3) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_gate_elim.py0000755000542200017500000000073415101701376021720 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_func_lib_sub_timing.py0000755000542200017500000000106615101701376023772 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') # UNOPTTHREADS in vltmt test.top_filename = "t/t_func_lib_sub.v" test.compile(verilator_flags2=["--binary"]) #test.execute() test.passes() verilator-5.042/test_regress/t/t_param_in_func.v0000644000542200017500000001112315101701376022377 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Driss Hafdi. // SPDX-License-Identifier: CC0-1.0 module t; initial begin if (getUnpacked($c("0")) != "0") $stop; if (getUnpacked($c("1")) != "1") $stop; if (getUnpacked($c("2")) != "2") $stop; if (getUnpacked($c("3")) != "3") $stop; if (getUnpacked($c("4")) != "4") $stop; if (getUnpacked($c("5")) != "5") $stop; if (getUnpacked($c("6")) != "6") $stop; if (getUnpacked($c("7")) != "7") $stop; if (getUnpacked($c("8")) != "8") $stop; if (getUnpacked($c("9")) != "9") $stop; if (getPacked($c("0")) != "0") $stop; if (getPacked($c("1")) != "1") $stop; if (getPacked($c("2")) != "2") $stop; if (getPacked($c("3")) != "3") $stop; if (getPacked($c("4")) != "4") $stop; if (getPacked($c("5")) != "5") $stop; if (getPacked($c("6")) != "6") $stop; if (getPacked($c("7")) != "7") $stop; if (getPacked($c("8")) != "8") $stop; if (getPacked($c("9")) != "9") $stop; if (getString($c("0")) != "0") $stop; if (getString($c("1")) != "1") $stop; if (getString($c("2")) != "2") $stop; if (getString($c("3")) != "3") $stop; if (getString($c("4")) != "4") $stop; if (getString($c("5")) != "5") $stop; if (getString($c("6")) != "6") $stop; if (getString($c("7")) != "7") $stop; if (getString($c("8")) != "8") $stop; if (getString($c("9")) != "9") $stop; if (getStruct($c("0")) != "0") $stop; if (getStruct($c("1")) != "1") $stop; if (getStruct($c("2")) != "2") $stop; if (getStruct($c("3")) != "3") $stop; if (getStruct($c("4")) != "4") $stop; if (getStruct($c("5")) != "5") $stop; if (getStruct($c("6")) != "6") $stop; if (getStruct($c("7")) != "7") $stop; if (getStruct($c("8")) != "8") $stop; if (getStruct($c("9")) != "9") $stop; if (getType($c("0")) != "0") $stop; if (getType($c("1")) != "1") $stop; if (getType($c("2")) != "2") $stop; if (getType($c("3")) != "3") $stop; if (getType($c("4")) != "4") $stop; if (getType($c("5")) != "5") $stop; if (getType($c("6")) != "6") $stop; if (getType($c("7")) != "7") $stop; if (getType($c("8")) != "8") $stop; if (getType($c("9")) != "9") $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule function automatic logic [7:0] getUnpacked(logic[3:0] d); `ifdef NO_INLINE /* verilator no_inline_task */ `endif localparam logic [7:0] DIGITS [10] = '{"0", "1", "2", "3", "4", "5", "6", "7", "8", "9"}; return DIGITS[d]; endfunction function automatic logic [7:0] getPacked(logic[3:0] d); `ifdef NO_INLINE /* verilator no_inline_task */ `endif localparam logic [9:0][7:0] DIGITS = {"9", "8", "7", "6", "5", "4", "3", "2", "1", "0"}; return DIGITS[d]; endfunction function automatic string getString(logic[3:0] d); `ifdef NO_INLINE /* verilator no_inline_task */ `endif localparam string DIGITS [10] = '{"0", "1", "2", "3", "4", "5", "6", "7", "8", "9"}; return DIGITS[d]; endfunction function automatic logic [7:0] getStruct(logic[3:0] d); `ifdef NO_INLINE /* verilator no_inline_task */ `endif // Silly indirect lookup table because we want to use a struct typedef struct packed { logic [7:0] result; longint index; } lut_t; localparam lut_t DIGITS [10] = '{ '{result: "1", index: 9}, '{result: "2", index: 0}, '{result: "3", index: 1}, '{result: "4", index: 2}, '{result: "5", index: 3}, '{result: "6", index: 4}, '{result: "7", index: 5}, '{result: "8", index: 6}, '{result: "9", index: 7}, '{result: "0", index: 8} }; return DIGITS[4'(DIGITS[d].index)].result; endfunction function automatic logic [7:0] getType(logic[3:0] d); `ifdef NO_INLINE /* verilator no_inline_task */ `endif localparam type octet_t = logic [7:0]; localparam octet_t [9:0] DIGITS = {"9", "8", "7", "6", "5", "4", "3", "2", "1", "0"}; return DIGITS[d]; endfunction verilator-5.042/test_regress/t/t_force_subvar.py0000755000542200017500000000073415101701376022452 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_order_dpi_export_7.cpp0000644000542200017500000000213215101701376023711 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2022 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include #include #include int main(int argc, char* argv[]) { VM_PREFIX* const tb = new VM_PREFIX; tb->contextp()->commandArgs(argc, argv); bool clk = true; while (!tb->contextp()->gotFinish()) { // Timeout if (tb->contextp()->time() > 100000) break; // Toggle and set clock svSetScope(svGetScopeFromName("TOP.testbench")); clk = !clk; set_inputs(clk); // Eval tb->eval(); // Advance time tb->contextp()->timeInc(500); } delete tb; return 0; } verilator-5.042/test_regress/t/t_struct_initial_assign.py0000755000542200017500000000103215101701376024363 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--timing"]) test.execute(fails=test.vlt_all) # Issue #5381 test.passes() verilator-5.042/test_regress/t/t_lint_width.v0000644000542200017500000000135015101701376021744 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (); // This isn't a width violation, as +/- 1'b1 is a common idiom // that's fairly harmless wire [4:0] five = 5'd5; wire [4:0] suma = five + 1'b1; wire [4:0] sumb = 1'b1 + five; wire [4:0] sumc = five - 1'b1; wire [4:0] neg5 = - five; wire [5:0] neg6 = - five; // Relatively harmless < or <= compared with something less wide localparam [1:0] THREE = 3; int a; initial for (a = 0; a < THREE; ++a) $display(a); initial for (a = 0; a <= THREE; ++a) $display(a); endmodule verilator-5.042/test_regress/t/t_vpi_sc.v0000644000542200017500000000103515101701376021062 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2010 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; // bug1081 - We don't use VPI, just need SC with VPI initial begin $write("%0t: Hello\n", $time); $write("*-* All Finished *-*\n"); $finish; end endmodule : t verilator-5.042/test_regress/t/t_display_impure.v0000644000542200017500000000066715101701376022637 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 function integer f; static integer i = 0; return ++i; endfunction module t; initial begin $display("%d", f()); $display("%d", f()); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_lint_comb_use.v0000644000542200017500000000123715101701376022425 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs hval, // Inputs sel ); input logic [2:0] sel; output logic [3:0] hval; /*AUTOINPUT*/ /*AUTOOUTPUT*/ always_comb begin unique case (sel) 3'h0: hval = 4'hd; 3'h1: hval = 4'hc; 3'h7: hval = 4'hf; default: begin $ignore ("ERROR : %s [%m]", $sformatf ("Illegal sel = %x", sel)); hval = 4'bx; end endcase end endmodule verilator-5.042/test_regress/t/t_class1.out0000644000542200017500000000021515101701376021326 0ustar mahmoudyfreeshellDisplay: null = "null" Display: newed = "'{imembera:'h0, imemberb:'h0}" Display: set = "'{imembera:'ha, imemberb:'h14}" *-* All Finished *-* verilator-5.042/test_regress/t/t_class_this_super.py0000755000542200017500000000073415101701376023344 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_param1.py0000755000542200017500000000070615101701376023172 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.042/test_regress/t/t_func_ref.py0000755000542200017500000000073415101701376021561 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_covergroup_with_function_foo_bad.v0000644000542200017500000000052615101701376026407 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off COVERIGN */ module t; covergroup cg_bad with function foo(int x); endgroup cg_bad cov = new(); endmodule verilator-5.042/test_regress/t/t_lib_prot_delay_bad.py0000755000542200017500000000130515101701376023563 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=[ "--protect-lib", "secret", "--protect-key", "secret-key", "--timing", ], verilator_make_gcc=False, make_main=False, fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_string_repl.v0000644000542200017500000000232615101701376022133 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Use this file as a template for submitting bugs, etc. // This module takes a single clock input, and should either // $write("*-* All Finished *-*\n"); // $finish; // on success, or $stop. // // The code as shown applies a random vector to the Test // module, then calculates a CRC on the Test module's outputs. // // **If you do not wish for your code to be released to the public // please note it here, otherwise:** // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; string s, s2; // Test loop always @ (posedge clk) begin cyc <= cyc + 1; s = {s2, {cyc{"*"}}}; if (cyc != s.len()) $stop; if (cyc == 0 && s != "") $stop; if (cyc == 1 && s != "*") $stop; if (cyc == 2 && s != "**") $stop; if (cyc == 3 && s != "***") $stop; if (cyc == 4 && s != "****") $stop; if (cyc == 5 && s != "*****") $stop; if (cyc == 5) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_lib_prot.py0000755000542200017500000000357215101701376021607 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt', 'xsim') if test.benchmark: test.sim_time = test.benchmark * 100 secret_prefix = "secret" secret_dir = test.obj_dir + "/" + secret_prefix test.mkdir_ok(secret_dir) trace_opt = "" # Always compile the secret file with Verilator no matter what simulator # we are testing with test.run(logfile=secret_dir + "/vlt_compile.log", cmd=["perl", os.environ["VERILATOR_ROOT"] + "/bin/verilator", '--no-timing', trace_opt, "--prefix", "Vt_lib_prot_secret", "-cc", "-Mdir", secret_dir, "--protect-lib", secret_prefix, "--protect-key", "secret-key", "t/t_lib_prot_secret.v"], verilator_run=True) # yapf:disable test.run(logfile=secret_dir + "/secret_gcc.log", cmd=[os.environ["MAKE"], "-C", secret_dir, "-f", "Vt_lib_prot_secret.mk"]) test.compile(verilator_flags2=['--no-timing', trace_opt, "-LDFLAGS", secret_prefix + "/libsecret.a", secret_dir + "/secret.sv"], xsim_flags2=[secret_dir + "/secret.sv"]) # yapf:disable test.execute(xsim_run_flags2=["--sv_lib", secret_dir + "/libsecret", "--dpi_absolute"]) if test.vlt and test.trace: # We can see the ports of the secret module test.file_grep(test.trace_filename, r'accum_in') # but we can't see what's inside test.file_grep_not(test.trace_filename, r'secret_') test.passes() verilator-5.042/test_regress/t/t_interface_size_bad.py0000755000542200017500000000076615101701376023577 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_module_input_default_value_1_bad.out0000644000542200017500000000057515101701376026603 0ustar mahmoudyfreeshell%Error-ASSIGNIN: t/t_module_input_default_value_1_bad.v:16:10: Assigning to input/const variable: 'i' : ... note: In instance 't.u_dut_should_fail_compile1' 16 | assign i = 1'b0; | ^ ... For error description see https://verilator.org/warn/ASSIGNIN?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_disable_func_bad.out0000644000542200017500000000045115101701376023366 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_disable_func_bad.v:19:13: Node of type FUNCREF 'increment_x' referenced by disable 19 | #1 disable increment_x; | ^~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_dpi_if_cond.v0000644000542200017500000000163615101701376022043 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2024 by Antmicro. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer counter = 0; import "DPI-C" context function int dpii_increment(inout int counter); function void func(); endfunction : func always @(posedge clk) begin if(dpii_increment(counter) == 1) begin // unreachable func(); // add impure statement for splitting $write(""); end else if (counter == 1) begin $write("*-* All Finished *-*\n"); $finish; end else begin $write("DPI called too many times: %d\n", counter); $stop; end end endmodule verilator-5.042/test_regress/t/t_disable_iff_multi_bad.py0000755000542200017500000000102515101701376024233 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["--timing"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_vlcov_opt_expr.info.out0000644000542200017500000000046715101701376024154 0ustar mahmoudyfreeshellTN:verilator_coverage SF:t/t_cover_line.v DA:331,7 BRDA:331,0,0,7 BRDA:331,0,1,3 DA:347,1 BRDA:347,0,0,1 BRDA:347,0,1,0 DA:350,10 BRDA:350,0,0,10 BRDA:350,0,1,1 DA:353,11 BRDA:353,0,0,11 BRDA:353,0,1,0 DA:356,11 BRDA:356,0,0,0 BRDA:356,0,1,11 DA:360,11 BRDA:360,0,0,11 BRDA:360,0,1,0 BRF:12 BRH:4 end_of_record verilator-5.042/test_regress/t/t_struct_type_bad.py0000755000542200017500000000076615101701376023172 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_mod_bad.v0000644000542200017500000000075015101701376022354 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilator lint_off MULTITOP module M; class Cls; function string name; return $sformatf("m %m"); endfunction endclass endmodule module t; string s; initial begin M::Cls p; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_func_const_packed_struct_bad2.py0000755000542200017500000000076615101701376025743 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_struct_packed_value_list.py0000755000542200017500000000073415101701376025054 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_assert_imm_nz_bad.out0000644000542200017500000000045315101701376023624 0ustar mahmoudyfreeshell%Error: t/t_assert_imm_nz_bad.v:13:26: Deferred assertions must use '#0' (IEEE 1800-2023 16.4) 13 | labeled_imas: assert #1 (clk); | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_opt_const.cpp0000644000542200017500000000111215101701376022120 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2023 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // Fake dependency to avoid optimization extern "C" int c_fake_dependency() { return 0; } verilator-5.042/test_regress/t/t_var_set_link.v0000644000542200017500000000107015101701376022256 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs state, // Inputs clk ); input clk; // Gave "Internal Error: V3Broken.cpp:: Broken link in node" output [1:0] state; reg [1:0] state = 2'b11; always @ (posedge clk) begin state <= state; end initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_timing_trace_saif.py0000755000542200017500000000121615101701376023435 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_timing_trace.v" test.compile(verilator_flags2=["--exe --main --timing --trace-saif -Wno-MINTYPMAXDLY"]) test.execute() test.saif_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_tri_select_unsized.v0000644000542200017500000000146315101701376023502 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Test of selection with unsized Z. // // Test selecting Z when size is not explicit. Issue 510. // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; wire [1:0] b; wire [1:0] c; wire [0:0] d; // Explicit width due to issue #508 wire [0:0] e; // This works if we use 1'bz, or 1'bx, but not with just 'bz or 'bx. It // does require the tri-state Z. Since we get the same effect if b is // dimensioned [0:0], this may be connected to issue #508. assign b[1:0] = clk ? 2'bx : 'bz; assign c[1:0] = clk ? 2'bz : 'bx; assign d = clk ? 1'bx : 'bz; assign e = clk ? 1'bz : 'bx; endmodule // t verilator-5.042/test_regress/t/t_srandom_class_dep.v0000644000542200017500000000147715101701376023271 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 typedef class Cls; class A; extern function void method(); endclass class B; extern function void method(); endclass class C; extern function void method(); endclass class D; extern function void method(); endclass function void A::method(); B obj = new; obj.method(); endfunction function void B::method(); this.srandom(0); endfunction function void C::method(); this.srandom(0); endfunction function void D::method(); C obj = new; obj.method(); endfunction module t; A obj1 = new; D obj2 = new; initial begin obj1.method(); obj2.method(); end endmodule verilator-5.042/test_regress/t/t_randomize_complex_typedef.v0000644000542200017500000000264015101701376025041 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class SubClass; rand bit [2:0] field; function new (); field = 0; endfunction endclass typedef SubClass Sc_t; class MyClass; Sc_t sc_inst2[2]; function new (); sc_inst2[1] = new; endfunction endclass; typedef MyClass Mc_t; class Deep; Mc_t sc_inst1; function new (); sc_inst1 = new; endfunction endclass; typedef Deep D_t; class WeNeedToGoDeeper; D_t sc_inst; function new (); sc_inst = new; endfunction endclass; typedef WeNeedToGoDeeper WNTGDA_t[100]; typedef MyClass MCA_t[2]; module t; initial begin WNTGDA_t cl_inst; MCA_t cl_inst2; cl_inst[1] = new; cl_inst2[0] = new; repeat(10) begin if (cl_inst[1].sc_inst.sc_inst1.sc_inst2[1].randomize() with {field inside {1, 2, 3};} == 0) begin $stop; end if (cl_inst[1].sc_inst.sc_inst1.sc_inst2[1].field < 1 || cl_inst[1].sc_inst.sc_inst1.sc_inst2[1].field > 3) begin $stop; end if (cl_inst2[0].sc_inst2[1].randomize() with {field inside {1, 2, 3};} == 0) begin $stop; end if (cl_inst2[0].sc_inst2[1].field < 1 || cl_inst2[0].sc_inst2[1].field > 3) begin $stop; end end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_func_cond.v0000644000542200017500000000117315101701376021540 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t; function automatic logic func_with_cond(logic x); return x ? func_with_case(0) : 0; endfunction function automatic logic func_with_case(logic x); logic result = 1'b0; unique case (1'b0) 1'b0: result = x; 1'b1: result = x; endcase return result; endfunction initial begin if (func_with_cond(0)) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_lint_badvltpragma_bad.out0000644000542200017500000000064615101701376024450 0ustar mahmoudyfreeshell%Error-BADVLTPRAGMA: t/t_lint_badvltpragma_bad.v:7:3: Unknown verilator comment: '/*verilator lintt_off WIDTH <--- Warning (lint_off misspelled)*/' 7 | /*verilator lintt_off WIDTH <--- Warning (lint_off misspelled)*/ | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ... For error description see https://verilator.org/warn/BADVLTPRAGMA?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_covergroup_func_override_bad.v0000644000542200017500000000057715101701376025524 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off COVERIGN */ module t(); covergroup cg; function sample(); endfunction function get_coverage(); endfunction endgroup endmodule verilator-5.042/test_regress/t/t_gen_defparam.v0000644000542200017500000000156515101701376022217 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; parameter PAR = 3; wire [31:0] o1a,o1b; m1 #(0) m1a(.o(o1a)); m1 #(1) m1b(.o(o1b)); always @ (posedge clk) begin if (o1a != 8) $stop; if (o1b != 4) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module m1 (output wire [31:0] o); parameter W = 0; generate if (W == 0) begin m2 m2 (.o(o)); defparam m2.PAR2 = 8; end else begin m2 m2 (.o(o)); defparam m2.PAR2 = 4; end endgenerate endmodule module m2 (output wire [31:0] o); parameter PAR2 = 10; assign o = PAR2; endmodule verilator-5.042/test_regress/t/t_udp_sequential_bad.v0000755000542200017500000000104615101701376023434 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 primitive or_gate(dout, a, b, c); output dout; input a, b, c; reg dout; table x 0 1 : 1; 0 ? 1 : 1; 0 1 0 : 0; 1 1 ? : 1; 1 0 0 : 0; 0 0 0 : 1; endtable endprimitive module top (a, b, c, o); input a, b, c; output o; or_gate(o, a, b, c); endmodule verilator-5.042/test_regress/t/t_interface_generic_bad3.out0000644000542200017500000000106515101701376024471 0ustar mahmoudyfreeshell%Error: t/t_interface_generic_bad3.v:15:9: Can't find definition of scope/variable: 'b' 15 | if (b.k != 9) $stop; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error-PINNOTFOUND: t/t_interface_generic_bad3.v:21:42: Pin not found: '__pinNumber2' 21 | GenericModule genericModule (inf_inst, inf_inst); | ^~~~~~~~ ... For error description see https://verilator.org/warn/PINNOTFOUND?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_flag_verilate_threads_bad.out0000644000542200017500000000031115101701376025261 0ustar mahmoudyfreeshell%Error: --verilate-jobs requires a non-negative integer, but '-1' was passed ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_lint_sideeffect_bad.out0000644000542200017500000000105415101701376024077 0ustar mahmoudyfreeshell%Warning-SIDEEFFECT: t/t_lint_sideeffect_bad.v:17:31: Expression side effect may be mishandled : ... Suggest use a temporary variable in place of this expression 17 | arr[postincrement_i()][postincrement_i()]++; | ^ ... For warning description see https://verilator.org/warn/SIDEEFFECT?v=latest ... Use "/* verilator lint_off SIDEEFFECT */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_mailbox_class.v0000644000542200017500000000267515101701376022432 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class mailbox_cls #(type T=int); // Test an implementation similar to what Verilator will do internally int m_bound; T m_q[$]; function new(int bound = 0); m_bound = bound; endfunction function int num(); return m_q.size(); endfunction task put(T message); if (m_bound != 0) wait (m_q.size() < m_bound); m_q.push_back(message); endtask function int try_put(T message); if (m_bound != 0 && m_q.size() < m_bound) begin m_q.push_back(message); return 1; end else begin return 0; end endfunction task get(ref T message); wait (m_q.size() != 0); message = m_q.pop_front(); endtask function int try_get(ref T message); if (m_q.size() != 0) begin message = m_q.pop_front(); return 1; end else begin return 0; end endfunction task peek(ref T message); wait (m_q.size() != 0); message = m_q[0]; endtask function int try_peek(ref T message); if (m_q.size() != 0) begin message = m_q[0]; return 1; end else begin return 0; end endfunction endclass `define MAILBOX_T mailbox_cls `include "t_mailbox.v" verilator-5.042/test_regress/t/t_var_pins_cc.py0000755000542200017500000000210715101701376022254 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_var_pinsizes.v" test.compile(verilator_flags2=['-cc'], verilator_make_gmake=False, make_top_shell=False, make_main=False) def hgrep(re): test.file_grep(os.path.join(test.obj_dir, test.vm_prefix + ".h"), re) hgrep(r'VL_IN8\(&i1,0,0\);') hgrep(r'VL_IN8\(&i8,7,0\);') hgrep(r'VL_IN16\(&i16,15,0\);') hgrep(r'VL_IN\(&i32,31,0\);') hgrep(r'VL_IN64\(&i64,63,0\);') hgrep(r'VL_INW\(&i65,64,0,3\);') hgrep(r'VL_OUT8\(&o1,0,0\);') hgrep(r'VL_OUT8\(&o8,7,0\);') hgrep(r'VL_OUT16\(&o16,15,0\);') hgrep(r'VL_OUT\(&o32,31,0\);') hgrep(r'VL_OUT64\(&o64,63,0\);') hgrep(r'VL_OUTW\(&o65,64,0,3\);') test.passes() verilator-5.042/test_regress/t/t_preproc_defines.py0000755000542200017500000000151715101701376023141 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_preproc.v" stdout_filename = os.path.join(test.obj_dir, test.name + "__test.vpp") test.compile(verilator_flags2=['-DDEF_A0 -DPREDEF_COMMAND_LINE -E --preproc-defines'], verilator_make_gmake=False, make_top_shell=False, make_main=False, stdout_filename=stdout_filename) test.files_identical(stdout_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_type_array.v0000644000542200017500000000076715101701376021771 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; typedef int arr_t [5]; arr_t arr; localparam type arr_type = type(arr); arr_type arr_prime; initial begin arr[3] = 123; arr_prime = arr; if (arr_prime[3] != 123) $stop(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_select_little.v0000644000542200017500000000444315101701376022441 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // verilator lint_off LITENDIAN wire [10:41] sel2 = crc[31:0]; wire [10:100] sel3 = {crc[26:0],crc}; wire out20 = sel2[{1'b0,crc[3:0]} + 11]; wire [3:0] out21 = sel2[13 : 16]; wire [3:0] out22 = sel2[{1'b0,crc[3:0]} + 20 +: 4]; wire [3:0] out23 = sel2[{1'b0,crc[3:0]} + 20 -: 4]; wire out30 = sel3[{2'b0,crc[3:0]} + 11]; wire [3:0] out31 = sel3[13 : 16]; wire [3:0] out32 = sel3[crc[5:0] + 20 +: 4]; wire [3:0] out33 = sel3[crc[5:0] + 20 -: 4]; // Aggregate outputs into a single result vector wire [63:0] result = {38'h0, out20, out21, out22, out23, out30, out31, out32, out33}; reg [19:50] sel1; initial begin // Path clearing // 122333445 // 826048260 sel1 = 32'h12345678; if (sel1 != 32'h12345678) $stop; if (sel1[47 : 50] != 4'h8) $stop; if (sel1[31 : 34] != 4'h4) $stop; if (sel1[27 +: 4] != 4'h3) $stop; //==[27:30], in memory as [23:20] if (sel1[26 -: 4] != 4'h2) $stop; //==[23:26], in memory as [27:24] end // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] sels=%x,%x,%x,%x %x,%x,%x,%x\n", $time, out20,out21,out22,out23, out30,out31,out32,out33); $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; `define EXPECTED_SUM 64'h28bf65439eb12c00 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_var_tieout.v0000644000542200017500000000250015101701376021756 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // bug291 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer out18; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire out1; // From test of Test.v wire out19; // From test of Test.v wire out1b; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out1 (out1), .out18 (out18), .out1b (out1b), .out19 (out19)); // Test loop always @ (posedge clk) begin if (out1 !== 1'b1) $stop; if (out18 !== 32'h18) $stop; if (out1b !== 1'b1) $stop; if (out19 !== 1'b1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module Test ( output wire out1 = 1'b1, output integer out18 = 32'h18, output var out1b = 1'b1, output var logic out19 = 1'b1 ); endmodule verilator-5.042/test_regress/t/t_select_negative.py0000755000542200017500000000073415101701376023133 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_vpi_cb_iter.py0000755000542200017500000000111215101701376022246 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe --vpi", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_assert_ctl_unsup.py0000755000542200017500000000102515101701376023361 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=['--assert'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_package_local_bad.v0000644000542200017500000000043015101701376023150 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2024 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; initial begin $display(local::x); $finish; end endmodule verilator-5.042/test_regress/t/t_unpacked_struct_sel.v0000644000542200017500000000065615101701376023650 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 typedef struct { bit [3:0] byte_en; } my_struct; module t; initial begin my_struct ms; ms.byte_en[0] = 1; if (ms.byte_en[0] != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_randomize_prepost_alone.py0000755000542200017500000000070615101701376024713 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.042/test_regress/t/t_package_export_bad2.out0000644000542200017500000000040115101701376024021 0ustar mahmoudyfreeshell%Error: t/t_package_export_bad2.v:12:18: Export package not found: 'Pkg1b' 12 | export Pkg1b::*; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_hier_block_import/0000755000542200017500000000000015101701376023104 5ustar mahmoudyfreeshellverilator-5.042/test_regress/t/t_hier_block_import/t_hier_block_import_def.vh0000644000542200017500000000100415101701376030272 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // No include guards to validate if included once. `define VALUE_A 32'h12345678 `define VALUE_B 32'h87654321 typedef struct packed { bit [31:0] PARAM_VALUE; } param_t; verilator-5.042/test_regress/t/t_hier_block_import/t_hier_block_import_args.f0000644000542200017500000000065515101701376030313 0ustar mahmoudyfreeshell# Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 --stats --hierarchical $TEST_ROOT/t_hier_block_import_subA.v -v $TEST_ROOT/t_hier_block_import_subB.v $TEST_ROOT/t_hier_block_import_subsub.v verilator-5.042/test_regress/t/t_hier_block_import/t_hier_block_import_subB.v0000644000542200017500000000074315101701376030270 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2024 by Antmicro. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // Note: no hier_block pragma here to validate partial hier_block design module subB (output bit [31:0] out); assign out = `VALUE_B; endmodule verilator-5.042/test_regress/t/t_hier_block_import/t_hier_block_import.vh0000644000542200017500000000070015101701376027456 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // No include guards to validate if included once. parameter param_t pt = '{ PARAM_VALUE: `VALUE_A } verilator-5.042/test_regress/t/t_hier_block_import/t_hier_block_import_subsub.v0000644000542200017500000000074515101701376030702 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2024 by Antmicro. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module subsub #( `include "t_hier_block_import.vh" ) (output bit [31:0] out); /*verilator hier_block*/ assign out = pt.PARAM_VALUE; endmodule verilator-5.042/test_regress/t/t_hier_block_import/t_hier_block_import_subA.v0000644000542200017500000000066615101701376030273 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2024 by Antmicro. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module subA (output bit [31:0] out); /*verilator hier_block*/ subsub subsub(.out(out)); endmodule verilator-5.042/test_regress/t/t_altera_lpm_latch.py0000755000542200017500000000111115101701376023253 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) test.compile(verilator_flags2=["--top-module", module]) test.passes() verilator-5.042/test_regress/t/t_flag_fi.v0000644000542200017500000000072715101701376021175 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2017 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (); initial begin $c("myfunction();"); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_force_release_net.py0000755000542200017500000000073415101701376023436 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_hier_bynum.v0000644000542200017500000000116415101701376021743 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: Unlicense module flop (q, d, clk); // No AUTOARG; order of below is different from port order above input wire clk; output reg q; input wire d; // verilator hier_block always_ff @(posedge clk) begin q <= d; end endmodule module t ( output wire q, input wire d, input wire clk ); // This intentionally uses pin number ordering flop u_flop(q, d, clk); endmodule verilator-5.042/test_regress/t/t_force_mid.v0000644000542200017500000000257215101701376021535 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module t(/*AUTOARG*/ // Outputs topout, // Inputs clk, topin ); input clk; input [3:0] topin; output [3:0] topout; integer cyc = 0; assign topout = 4'b0101; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 0) begin if (topout != 4'b0101) $stop; if (topin != 4'b1001) $stop; end else if (cyc == 1) begin force topout = 4'b1010; end else if (cyc == 2) begin if (topout != 4'b1010) $stop; release topout; end else if (cyc == 3) begin if (topout != 4'b0101) $stop; end else if (cyc == 4) begin force topin = 4'b1100; end else if (cyc == 5) begin if (topin != 4'b1100) $stop; release topin; end else if (cyc == 6) begin if (topin != 4'b1001) $stop; end // else if (cyc == 99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_param_seg.py0000755000542200017500000000073415101701376021730 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_altera_lpm_clshift.py0000755000542200017500000000111115101701376023614 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) test.compile(verilator_flags2=["--top-module", module]) test.passes() verilator-5.042/test_regress/t/t_flag_f.vc0000644000542200017500000000047015101701376021162 0ustar mahmoudyfreeshell// Test that environment substitutions work # This is also a comment (in several simulators) -f $TEST_REGRESS/t/t_flag_f__2.vc // Env var with .v file, and parens // Double slash below is intentional, as allowed in other tools ${TEST_REGRESS}/t//t_flag_f__3.v // Test -f -F $TEST_REGRESS/t/tsub/t_flag_f_tsub.vc verilator-5.042/test_regress/t/t_event_copy.py0000755000542200017500000000107015101701376022137 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(fails=test.vlt_all, expect_filename=test.golden_filename, threads=1) if not test.vlt_all: test.execute() test.passes() verilator-5.042/test_regress/t/t_randomize_neasted_unsup.py0000755000542200017500000000076315101701376024721 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_vpi_stop_bad.out0000644000542200017500000000004215101701376022607 0ustar mahmoudyfreeshell%Error: Verilog $stop Aborting... verilator-5.042/test_regress/t/t_virtual_interface_param.py0000755000542200017500000000073415101701376024660 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_opt_if_array.py0000755000542200017500000000114215101701376022442 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() for filename in test.glob_some(test.obj_dir + "/" + test.vm_prefix + "___024root*.cpp"): test.file_grep_not(filename, r'rstn_r') test.passes() verilator-5.042/test_regress/t/t_param_type5.py0000755000542200017500000000073415101701376022220 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_struct_param_overflow.v0000644000542200017500000000336415101701376024235 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2023 by Varun Koyyalagunta. // SPDX-License-Identifier: CC0-1.0 package config_pkg; localparam int unsigned N = 10; typedef struct packed { logic [N-1:0][31:0] lo; logic [N-1:0][31:0] hi; logic [100-1:0][31:0] x; int unsigned n; } config_struct_t; function automatic logic subcheck(logic [31:0] lo, logic [31:0] hi, logic [31:0] val); return lo <= val && val < hi; endfunction function automatic logic check(config_struct_t cfg, logic [31:0] val); logic [N-1:0] good = '0; logic [N-1:0] bad = '0; for (int i = 0; i < cfg.n; i++) begin good[i] = subcheck(cfg.lo[i], cfg.hi[i], val); end for (int i = cfg.n; i < N; i++) begin bad[i] = !(cfg.lo[i] == '0 && cfg.hi[i] == '0); end return good != '0 && bad == '0; endfunction endpackage : config_pkg module t ( /*AUTOARG*/ // Inputs clk ); input clk; import config_pkg::*; parameter config_struct_t MY_CONFIG = '{ lo: {((N - 3) * 32)'('0), 32'h00, 32'h10, 32'h20}, hi: {((N - 3) * 32)'('0), 32'h10, 32'h20, 32'h30}, x : 3200'h0deadbeef, n : 3 }; struct_submodule #(.MY_CONFIG(MY_CONFIG)) a_submodule_I (.clk); endmodule module struct_submodule import config_pkg::*; #( parameter config_struct_t MY_CONFIG = '0 ) ( input clk ); logic [31:0] val; logic c; int count = 0; assign val = 3; assign c = check(MY_CONFIG, count); always @(posedge clk) begin count <= count + 1; if (c != '1) begin $error("c not 1"); $stop; end if (count >= 10) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_var_types_bad.py0000755000542200017500000000112415101701376022606 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.verilated_randReset = 1 # allow checking if we initialize vars to zero only when needed test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_extends_rec_bad.out0000644000542200017500000000051415101701376024440 0ustar mahmoudyfreeshell%Error: t/t_class_extends_rec_bad.v:7:31: Attempting to extend class 'RecursiveExtCls' from itself 7 | class RecursiveExtCls extends RecursiveExtCls; | ^~~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_vpi_get.py0000755000542200017500000000141615101701376021425 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(make_top_shell=False, make_main=False, make_pli=True, verilator_flags2=["--exe --vpi --no-l2name", test.pli_filename], iv_flags2=["-g2005-sv -D USE_VPI_NOT_DPI"], v_flags2=["+define+USE_VPI_NOT_DPI +define+VERILATOR_COMMENTS"]) test.execute(use_libvpi=True) test.passes() verilator-5.042/test_regress/t/t_exit.py0000755000542200017500000000073415101701376020743 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_cover_lib.v0000644000542200017500000000055215101701376021546 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2017 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; endmodule verilator-5.042/test_regress/t/t_flag_werror_bad3.out0000644000542200017500000000024215101701376023342 0ustar mahmoudyfreeshell%Error: Unknown warning specified: -Werror-NOSUCHERRORASTHIS ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. verilator-5.042/test_regress/t/t_flag_compiler_bad.out0000644000542200017500000000033415101701376023553 0ustar mahmoudyfreeshell%Error: Unknown setting for --compiler: 'bad_one' ... Suggest 'clang', 'gcc', or 'msvc' ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_queue_persistence_noinl.py0000755000542200017500000000121615101701376024715 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_queue_persistence.v" if not test.have_coroutines: test.skip("No coroutine support") test.compile(verilator_flags2=["--binary --fno-inline +define+TEST_NOINLINE"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_wait_const.py0000755000542200017500000000076315101701376022146 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_virtual_interface_param_bind.v0000644000542200017500000000111115101701376025454 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 interface b_if; int x = 1; endinterface module t; bind m b_if if_bind (); m #(.p(2)) m_i (); typedef virtual b_if vif_t; initial begin vif_t vif = t.m_i.if_bind; int y = t.m_i.if_bind.x; if (vif.x != 1) $stop; if (y != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module m #( parameter p = 1 ) (); endmodule verilator-5.042/test_regress/t/t_property_unsup.v0000644000542200017500000000754215101701376022726 0ustar mahmoudyfreeshell// (C) 2001-2020, Daniel Kroening, Edmund Clarke, // Computer Science Department, University of Oxford // Computer Science Department, Carnegie Mellon University // // All rights reserved. Redistribution and use in source and binary forms, with // or without modification, are permitted provided that the following // conditions are met: // // 1. Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. // // 3. Neither the name of the University nor the names of its contributors // may be used to endorse or promote products derived from this software // without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // // You can contact the author at: // - homepage : https://www.cprover.org/ebmc/ // - source repository : https://github.com/diffblue/hw-cbmc module t ( /*AUTOARG*/ // Inputs clk, reset ); input clk; input reset; eventually1 eventually1 (.*); eventually2 eventually2 (.*); sva_implies2 sva_implies2 (.*); sva_iff2 sva_iff2 (.*); endmodule module eventually1 ( input clk, input reset ); // count up from 0 to 10 reg [7:0] counter; initial counter = 0; always @(posedge clk) if (counter != 10) counter = counter + 1; // expected to pass p0 : assert property (counter == 1 implies eventually[1: 2] counter == 3); endmodule module eventually2 ( input clk, input reset ); reg [7:0] counter; initial counter = 0; always @(posedge clk) counter = 0; // expected to fail p0 : assert property (eventually[0: 2] counter == 3); endmodule module sva_implies2 ( input a, b ); p0 : assert property ((always a) implies (always a)); p1 : assert property ((a or(always b)) implies (a or(always b))); p2 : assert property ((eventually[0: 1] a) implies (eventually[0: 1] a)); p3 : assert property ((s_eventually a) implies (s_eventually a)); p4 : assert property ((a until b) implies (a until b)); p5 : assert property ((a s_until b) implies (a s_until b)); p6 : assert property ((a until_with b) implies (a until_with b)); p7 : assert property ((a s_until_with b) implies (a s_until_with b)); p8 : assert property ((a |-> b) implies (a |-> b)); p9 : assert property ((a #-# b) implies (a #-# b)); endmodule module sva_iff2 ( input a, b ); p0 : assert property ((always a) iff (always a)); p1 : assert property ((eventually[0: 1] a) iff (eventually[0: 1] a)); p2 : assert property ((s_eventually a) iff (s_eventually a)); p3 : assert property ((a until b) iff (a until b)); p4 : assert property ((a s_until b) iff (a s_until b)); p5 : assert property ((a until_with b) iff (a until_with b)); p6 : assert property ((a s_until_with b) iff (a s_until_with b)); p7 : assert property ((a |-> b) iff (a |-> b)); p8 : assert property ((a #-# b) iff (a #-# b)); endmodule verilator-5.042/test_regress/t/t_func_real_exprstmt.py0000755000542200017500000000121315101701376023667 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--stats"]) if test.vlt_all: # Check no EXPRSTMTs in final output - should get optimized away test.file_grep_not(test.stats, r'Node count, EXPRSTMT') test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_bind_public.py0000755000542200017500000000077015101701376024264 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['-public']) test.execute() test.passes() verilator-5.042/test_regress/t/t_enum_bad_value.py0000755000542200017500000000103015101701376022726 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["--Wno-fatal"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_param_circ_bad.out0000644000542200017500000000050715101701376024237 0ustar mahmoudyfreeshell%Error: t/t_class_param_circ_bad.v:14:4: Exceeded maximum --module-recursion-depth of 100 : ... note: In instance 't' 14 | ClsA #(PARAM+1) a; | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_module_input_default_value_2_bad.v0000644000542200017500000000223615101701376026236 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Andrew Ranck // SPDX-License-Identifier: CC0-1.0 // Test for Issue#5358: Support default value on module input. // This test *is* expected to not compile, and must match .out file. module dut_should_fail_compile2 ( input logic i = 1'b1, output logic o ); always_comb begin i = 1'b0; // bad, should fail post link in V3Width end assign o = i; endmodule module t (/*AUTOARG*/ // Inputs clk ); input clk; int cyc = 0; // 1800-2009, a few flavors to test: // We should have some DUT instances that fail to compile, // if you tried having a default value on port output. logic dut_should_fail_o; dut_should_fail_compile2 u_dut_should_fail_compile1 (.i(1'b0), .o(dut_should_fail_o) ); always @(posedge clk) begin : main cyc <= cyc + 1; if (cyc == 10) begin // done checking various DUTs and finish $display("%t %m: cyc=%0d", $time, cyc); $write("*-* All Finished *-*\n"); $finish(); end end endmodule : t verilator-5.042/test_regress/t/t_no_std_bad.out0000644000542200017500000000035315101701376022237 0ustar mahmoudyfreeshell%Error: t/t_no_std_bad.v:9:11: Import package not found: 'std' 9 | import std::*; | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_fork_bbox.v0000644000542200017500000000060715101701376021556 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin fork : fblk begin $write("*-* All Finished *-*\n"); $finish; end join : fblk end endmodule verilator-5.042/test_regress/t/t_wrapper_del_context_bad.py0000755000542200017500000000112715101701376024645 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Multiple Model Test Module # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) test.execute(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_const_bitoptree_bug3096.cpp0000644000542200017500000000155515101701376024505 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2021 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include VM_PREFIX_INCLUDE #include #include int main(int argc, char* argv[]) { VM_PREFIX* const tb = new VM_PREFIX; tb->instr_i = 0x08c0006f; tb->eval(); std::cout << "tb->illegal_instr_o: " << static_cast(tb->illegal_instr_o) << std::endl << std::flush; assert(tb->illegal_instr_o == 0); delete tb; return 0; } verilator-5.042/test_regress/t/t_lint_always_comb_automatic.py0000755000542200017500000000070615101701376025365 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.042/test_regress/t/t_flag_debug_noleak.v0000644000542200017500000000047115101701376023212 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_timing_clkgen_sc.py0000755000542200017500000000110415101701376023261 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_timing_clkgen2.v" test.compile(verilator_flags2=["--sc --exe --timing --timescale 10ps/1ps"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_forceable_var_vlt.py0000755000542200017500000000130515101701376023444 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.pli_filename = "t/t_forceable_var.cpp" test.top_filename = "t/t_forceable_var.v" test.compile(make_top_shell=False, make_main=False, verilator_flags2=['--exe', test.pli_filename, test.t_dir + "/t_forceable_var.vlt"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_modport_import.py0000755000542200017500000000073415101701376025070 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_randomize_queue_wide.py0000755000542200017500000000104615101701376024173 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_uvm_hello.v0000644000542200017500000000075415101701376021600 0ustar mahmoudyfreeshell// -*- Verilog -*- // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Test requires command line be passed uvm_pkg.sv before this filename // verilator lint_off DECLFILENAME module t; import uvm_pkg::*; initial begin // verilator lint_off WIDTHTRUNC `uvm_info("TOP", "Hello World!", UVM_MEDIUM); end endmodule verilator-5.042/test_regress/t/t_flag_threads_dpi_bad.py0000755000542200017500000000106315101701376024053 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--threads-dpi bad_one"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lib_prot_comb.py0000755000542200017500000000301515101701376022577 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all', 'xsim') if test.benchmark: test.sim_time = test.benchmark * 100 trace_opt = "" secret_prefix = "secret" secret_dir = test.obj_dir + "/" + secret_prefix test.mkdir_ok(secret_dir) # Always compile the secret file with Verilator no matter what simulator # we are testing with test.run( logfile=secret_dir + "/vlt_compile.log", cmd=["perl", os.environ["VERILATOR_ROOT"] + "/bin/verilator", "-cc", trace_opt, "--prefix", "Vt_lib_prot_secret", "-Mdir", secret_dir, "--protect-lib", secret_prefix, "--protect-key", "secret-key", "t/t_lib_prot_comb.v"], verilator_run=True) # yapf:disable test.run(logfile=secret_dir + "/secret_gcc.log", cmd=[os.environ["MAKE"], "-C", secret_dir, "-f", "Vt_lib_prot_secret.mk"]) test.compile( verilator_flags2=[ secret_dir + "/secret.sv", "+define+PROCESS_TOP", "-LDFLAGS",secret_prefix + "/libsecret.a"], xsim_flags2=[secret_dir + "/secret.sv"]) # yapf:disable test.execute(xsim_run_flags2=["--sv_lib", secret_dir + "/libsecret", "--dpi_absolute"]) test.passes() verilator-5.042/test_regress/t/t_alias_unsup.out0000644000542200017500000000063615101701376022472 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_alias_unsup.v:76:35: Unsupported: Operand of alias statement is not a variable reference : ... note: In instance 't.test2' 76 | alias {a[7:0], a[15:8], a[23:16], a[31:24]} = b; | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_mod_interface_array6.py0000755000542200017500000000073415101701376024055 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_package_enum.v0000644000542200017500000000142415101701376022220 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package pkg; typedef enum bit [1:0] { E__NOT = 2'b00, E__VAL = 2'b11 } E_t; endpackage module t; reg [1:0] ttype; reg m; enum bit [1:0] { LOCAL } l; always @ (m or 1'b0 or LOCAL) begin // Don't complain about constants in sensitivity lists end initial begin ttype = pkg::E__NOT; m = (ttype == pkg::E__VAL); if (m != 1'b0) $stop; ttype = pkg::E__VAL; m = (ttype == pkg::E__VAL); if (m != 1'b1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_tri_compass_bad.out0000644000542200017500000000053215101701376023273 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_tri_compass_bad.v:16:12: Unsupported: tristate in top-level IO: '__pinNumber1' : ... note: In instance 't' 16 | sub sub(i, o); | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_func_flip.py0000755000542200017500000000073415101701376021737 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_nullport_bad.py0000755000542200017500000000076615101701376023512 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_tri_struct_packed.v0000644000542200017500000000121615101701376023311 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 typedef struct packed { bit x; } p_struct_t; module p_mh (inout p_struct_t p_i, inout p_struct_t p_o); // OK: module p_mh (input p_struct_t p_i, output p_struct_t p_o); assign p_o.x = p_i.x; endmodule module t; p_struct_t p_i, p_o; p_mh p_mh(p_i, p_o); initial begin p_i.x = 1; #1; // issue #4925 if (p_o.x != 1'b1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_package_import_bad2.out0000644000542200017500000000037615101701376024025 0ustar mahmoudyfreeshell%Error: t/t_package_import_bad2.v:12:11: Import package not found: 'Pkg1b' 12 | import Pkg1b::*; | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_x_assign.cpp0000644000542200017500000000326215101701376021733 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2020 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "verilated.h" #include #include VM_PREFIX_INCLUDE double sc_time_stamp() { return 0; } // clang-format off #if defined(T_X_ASSIGN_0) # define EXPECTED 0 #elif defined(T_X_ASSIGN_1) # define EXPECTED 1 #endif // clang-format on int main(int argc, const char** argv) { #if defined(T_X_ASSIGN_UNIQUE_0) Verilated::randReset(0); #elif defined(T_X_ASSIGN_UNIQUE_1) Verilated::randReset(1); #endif VM_PREFIX* top = new VM_PREFIX{}; // Evaluate one clock posedge top->clk = 0; top->eval(); top->clk = 1; top->eval(); #if defined(T_X_ASSIGN_UNIQUE_0) || defined(T_X_ASSIGN_UNIQUE_1) if (top->o_int == 0 || top->o_int == -1) { vl_fatal(__FILE__, __LINE__, "TOP.t", "x assign was not unique"); exit(1); } #else if (top->o != EXPECTED) { vl_fatal(__FILE__, __LINE__, "TOP.t", "incorrect module output"); exit(1); } uint32_t o_int_expected = EXPECTED ? 0xffffffff : 0; if (top->o_int != o_int_expected) { vl_fatal(__FILE__, __LINE__, "TOP.t", "incorrect module output"); exit(1); } #endif VL_DO_DANGLING(delete top, top); std::cout << "*-* All Finished *-*" << std::endl; return 0; } verilator-5.042/test_regress/t/t_sys_file_basic_mcd_test5.dat0000644000542200017500000000002615101701376025026 0ustar mahmoudyfreeshellTo file and to stdout verilator-5.042/test_regress/t/t_case_zx_bad.out0000644000542200017500000000063215101701376022405 0ustar mahmoudyfreeshell%Warning-CASEWITHX: t/t_case_zx_bad.v:16:9: Use of x constant in casez statement, (perhaps intended ?/z in constant) 16 | 4'b1xxx: $stop; | ^~~~~~~ ... For warning description see https://verilator.org/warn/CASEWITHX?v=latest ... Use "/* verilator lint_off CASEWITHX */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_randcase.v0000644000542200017500000000477715101701376021377 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define check_range(gotv,minv,maxv) do if ((gotv) < (minv) || (gotv) > (maxv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d-%0d\n", `__FILE__,`__LINE__, (gotv), (minv), (maxv)); `stop; end while(0); `define check_within_30_percent(gotv,val) `check_range((gotv), (val) * 70 / 100, (val) * 130 / 100) module t; localparam int COUNT = 1000; int v; int counts[8]; function int randfunc(); int i; randcase 0 : i = 50; // Never 1 : i = 100; endcase return i; endfunction initial begin; if (randfunc() != 100) $stop; // for (int i = 0; i < 8; ++i) counts[i] = 0; for (int i = 0; i < COUNT; ++i) begin randcase 0 : ; // Never 0 : counts[0]++; // Never 1 : counts[1]++; endcase end `check_range(counts[0], 0, 0); `check_range(counts[1], COUNT, COUNT); // for (int i = 0; i < 8; ++i) counts[i] = 0; for (int i = 0; i < COUNT; ++i) begin randcase i - i : counts[0]++; // Never i + i + 1: counts[1]++; endcase end `check_range(counts[0], 0, 0); `check_range(counts[1], COUNT, COUNT); // for (int i = 0; i < 8; ++i) counts[i] = 0; for (int i = 0; i < COUNT; ++i) begin randcase 1 : counts[0]++; // Never 4 : counts[1]++; endcase end `check_within_30_percent(counts[0], (COUNT * 1 / 5)); `check_within_30_percent(counts[1], (COUNT * 4 / 5)); // for (int i = 0; i < 8; ++i) counts[i] = 0; for (int i = 0; i < COUNT; ++i) begin randcase 2 : counts[0]++; // Never 2 : counts[1]++; // Never 1 : counts[2]++; // Never 1 : counts[3]++; // Never 1 : counts[4]++; // Never 1 : counts[5]++; // Never 1 : counts[6]++; // Never 1 : counts[7]++; // Never endcase end `check_within_30_percent(counts[0], (COUNT * 2 / 10)); `check_within_30_percent(counts[1], (COUNT * 2 / 10)); `check_within_30_percent(counts[2], (COUNT * 1 / 10)); `check_within_30_percent(counts[7], (COUNT * 1 / 10)); // $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_interface_modportlist.v0000644000542200017500000000105015101701376024174 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2016 by Adrian Wise. // SPDX-License-Identifier: CC0-1.0 //bug1246 module t(input clk); my_interface iface(); my_module m(.clk(clk), .iface); endmodule module my_module(input clk, my_interface.my_port iface); always @(posedge clk) begin iface.b <= iface.a; iface.c <= iface.a; end endmodule interface my_interface; logic a, b, c; modport my_port(input a, output b, c); endinterface verilator-5.042/test_regress/t/t_func_defaults.v0000644000542200017500000000166015101701376022425 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Test for warning (not error) on improperly width'ed // default function argument // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 parameter logic BAR = 1'b1; function automatic logic calc_y; return 1'b1; endfunction function automatic logic [1:0] foo ( input logic x = BAR, input logic y = calc_y() ); return x + y; endfunction class Foo; static int x; static function int get_x; return x; endfunction endclass function int mult2(int x = Foo::get_x()); return 2 * x; endfunction module t; logic [1:0] foo_val; initial begin foo_val = foo(); if (foo_val != 2'b10) $stop; if (mult2(1) != 2) $stop; if (mult2() != 0) $stop; Foo::x = 30; if (mult2() != 60) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_var_port_bad.py0000755000542200017500000000076615101701376022441 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_link_delay.py0000755000542200017500000000101015101701376023256 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['-Wall -Wno-DECLFILENAME --coverage-line']) test.passes() verilator-5.042/test_regress/t/t_lint_warn_incfile2_bad_b.vh0000644000542200017500000000047015101701376024630 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module sub; // verilator lint_off WIDTHTRUNC int warn_sub = 64'h1; // Suppressed endmodule verilator-5.042/test_regress/t/t_trace_primitive_saif.out0000644000542200017500000000504415101701376024335 0ustar mahmoudyfreeshell// Generated by verilated_saif (SAIFILE (SAIFVERSION "2.0") (DIRECTION "backward") (PROGRAM_NAME "Verilator") (DIVIDER / ) (TIMESCALE 1ps) (DURATION 120) (INSTANCE top (NET (clk (T0 65) (T1 55) (TZ 0) (TX 0) (TB 0) (TC 23)) ) (INSTANCE t (NET (clk (T0 65) (T1 55) (TZ 0) (TX 0) (TB 0) (TC 23)) (cyc\[0\] (T0 60) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 12)) (cyc\[1\] (T0 60) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (cyc\[2\] (T0 80) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3)) (cyc\[3\] (T0 80) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[4\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[5\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a (T0 70) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 11)) (b (T0 70) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5)) (z (T0 100) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 5)) ) (INSTANCE sub_t_i (NET (x (T0 70) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 11)) (y (T0 70) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5)) (z (T0 100) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 5)) ) ) ) ) ) verilator-5.042/test_regress/t/t_tri_inz.py0000755000542200017500000000105615101701376021446 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_iface_array_topmodule2.v0000644000542200017500000000151215101701376025244 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Josh Redford. // SPDX-License-Identifier: CC0-1.0 interface my_if #( parameter DW = 8 ) (); logic valid; logic [DW-1:0] data ; modport slave_mp ( input valid, input data ); modport master_mp ( output valid, output data ); endinterface module t ( input wire clk, my_if.slave_mp in_if [2], my_if.master_mp out_if [2] ); assign out_if[0].valid = in_if[0].valid; assign out_if[0].data = in_if[0].data; assign out_if[1].valid = in_if[1].valid; assign out_if[1].data = in_if[1].data; endmodule verilator-5.042/test_regress/t/t_timing_finish.py0000755000542200017500000000077115101701376022622 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--binary']) test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_misindent_bad.py0000755000542200017500000000110115101701376023605 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME"], expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_time_vpi_10ms10ns.py0000755000542200017500000000137215101701376023147 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.pli_filename = "t/t_time_vpi_c.cpp" test.top_filename = "t/t_time_vpi.v" test.main_time_multiplier = 10e-3 / 10e-9 test.compile( v_flags2=['+define+time_scale_units=10ms +define+time_scale_prec=10ns', test.pli_filename], verilator_flags2=['--vpi']) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_unpacked_concat_bad.v0000644000542200017500000000122415101701376023526 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Driss Hafdi. // SPDX-License-Identifier: CC0-1.0 module t; typedef logic [15:0] count_t; typedef bit [31:0] bit_int_t; localparam bit_int_t count_bits [1:0] = {2{$bits(count_t)}}; localparam bit_int_t count_bitsc [1:0] = {$bits(count_t), $bits(count_t)}; initial begin if (count_bits[0] != 16) $stop; if (count_bits[1] != 16) $stop; if (count_bitsc[0] != 16) $stop; if (count_bitsc[1] != 16) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_opt_table_same.v0000644000542200017500000000174415101701376022564 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; int i; int j; reg [2:0] cyc; initial cyc = 0; always @(posedge clk) cyc <= cyc + 1; always @* begin case (cyc) 3'b000: i = 0; 3'b001: i = 1; 3'b010: i = 2; 3'b100: i = 4; 3'b101: i = 5; default: i = 99; endcase end // Equivalent to above always @* begin case (cyc) 3'b101: j = 5; 3'b100: j = 4; 3'b010: j = 2; 3'b001: j = 1; 3'b000: j = 0; default: j = 99; endcase end always @(posedge clk) begin $display("cyle %d = %d %d", cyc, i, j); if (cyc == 7) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_virtual_interface_gen_for_ref.v0000644000542200017500000000255315101701376025646 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 package uvm_pkg; class uvm_resource_db #( type T = int ); static T interf; static function void set(input T accessor); interf = accessor; endfunction endclass class uvm_config_db #( type T = int ) extends uvm_resource_db #(T); endclass endpackage interface iface (); int x = 1; endinterface module t; import uvm_pkg::*; bind bound iface if_bind (); dut i_dut (); initial begin uvm_config_db#(virtual iface)::set( t.i_dut.first_gen[0].i_fail.i_a.i_b.i_c.second_gen[0].i_d.i_bound.if_bind); if (uvm_config_db#(virtual iface)::interf.x != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module bound (); endmodule module dut (); genvar g_core; generate for (g_core = 0; g_core < 1; g_core++) begin : first_gen fail_mod i_fail (); end endgenerate endmodule module fail_mod (); a i_a (); endmodule module a (); b i_b (); endmodule ; module b (); c i_c (); endmodule module c (); genvar gi; generate for (gi = 0; gi < 1; gi++) begin : second_gen d i_d (); end endgenerate endmodule module d (); bound i_bound (); endmodule verilator-5.042/test_regress/t/t_struct_anon.v0000644000542200017500000000113015101701376022132 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Anonymous struct packed { logic [31:0] val1; logic [31:0] val2; } struct1; struct packed { logic [31:0] val3; logic [31:0] val4; } struct2; module t ( output logic [63:0] s1, output logic [63:0] s2 ); initial struct1 = 64'h123456789_abcdef0; always_comb s1 = struct1; initial struct2 = 64'h123456789_abcdef0; always_comb s2 = struct2; endmodule verilator-5.042/test_regress/t/t_pp_dupdef.v0000644000542200017500000000057015101701376021550 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; `define DUP fred `define DUP barney `define DUPP paramed(x) (x) `define DUPP paramed(x,z) (x*z) initial $stop; // Should have failed endmodule verilator-5.042/test_regress/t/t_sys_queue_unsup.v0000644000542200017500000001060515101701376023056 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias' // // Simple bi-directional alias test. // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Based on iverilog/ivtest/ivltests/queue.v // verilog_format: off `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); // verilog_format: on module top; reg pass; integer res, status, job, value; initial begin pass = 1'b1; $q_initialize(1, 1, 3, status); `checkd(status, 0); $q_initialize(2, 2, 2, status); `checkd(status, 0); $q_initialize(3, 0, 10, status); `checkd(status, 4); $q_initialize(3, 3, 10, status); `checkd(status, 4); $q_initialize(3, 1, 0, status); `checkd(status, 5); $q_initialize(3, 1, -1, status); `checkd(status, 5); $q_initialize(1, 2, 20, status); `checkd(status, 6); $q_add(3, 0, 0, status); `checkd(status, 2); $q_remove(3, job, value, status); `checkd(status, 2); res = $q_full(3, status); `checkd(status, 2); $q_exam(3, 1, value, status); `checkd(status, 2); $q_add(2, 1, 1, status); `checkd(status, 0); res = $q_full(2, status); `checkd(status, 0); `checkd(res, 0); $q_add(2, 1, 2, status); `checkd(status, 0); res = $q_full(2, status); `checkd(status, 0); `checkd(res, 1); $q_exam(2, 1, value, status); `checkd(status, 0); `checkd(value, 2); $q_exam(2, 3, value, status); `checkd(status, 0); `checkd(value, 2); $q_exam(2, 5, value, status); `checkd(status, 0); `checkd(value, 0); $q_add(2, 1, 3, status); `checkd(status, 1); $q_remove(2, job, value, status); `checkd(status, 0); `checkd(job, 1); `checkd(value, 2); res = $q_full(2, status); `checkd(status, 0); `checkd(res, 0); $q_remove(2, job, value, status); `checkd(status, 0); `checkd(job, 1); `checkd(value, 1); res = $q_full(2, status); `checkd(status, 0); `checkd(res, 0); $q_exam(2, 1, value, status); `checkd(status, 0); `checkd(value, 0); $q_exam(2, 3, value, status); `checkd(status, 0); `checkd(value, 2); $q_exam(2, 4, value, status); `checkd(status, 0); `checkd(value, 0); $q_remove(2, job, value, status); `checkd(status, 3); $q_add(1, 2, 1, status); `checkd(status, 0); res = $q_full(1, status); `checkd(status, 0); `checkd(res, 0); $q_add(1, 2, 2, status); `checkd(status, 0); res = $q_full(1, status); `checkd(status, 0); `checkd(res, 0); $q_add(1, 2, 3, status); `checkd(status, 0); res = $q_full(1, status); `checkd(status, 0); `checkd(res, 1); $q_exam(1, 1, value, status); `checkd(status, 0); `checkd(value, 3); $q_exam(1, 3, value, status); `checkd(status, 0); `checkd(value, 3); $q_exam(1, 5, value, status); `checkd(status, 0); `checkd(value, 0); $q_add(1, 2, 4, status); `checkd(status, 1); $q_remove(1, job, value, status); `checkd(status, 0); `checkd(job, 2); `checkd(value, 1); res = $q_full(1, status); `checkd(status, 0); `checkd(res, 0); $q_remove(1, job, value, status); `checkd(status, 0); `checkd(job, 2); `checkd(value, 2); res = $q_full(1, status); `checkd(status, 0); `checkd(res, 0); $q_add(1, 2, 4, status); `checkd(status, 0); res = $q_full(1, status); `checkd(status, 0); `checkd(res, 0); $q_remove(1, job, value, status); `checkd(status, 0); `checkd(job, 2); `checkd(value, 3); res = $q_full(1, status); `checkd(status, 0); `checkd(res, 0); $q_remove(1, job, value, status); `checkd(status, 0); `checkd(job, 2); `checkd(value, 4); res = $q_full(1, status); `checkd(status, 0); `checkd(res, 0); $q_exam(1, 1, value, status); `checkd(status, 0); `checkd(value, 0); $q_exam(1, 3, value, status); `checkd(status, 0); `checkd(value, 3); $q_exam(1, 4, value, status); `checkd(status, 0); `checkd(value, 0); $q_remove(1, job, value, status); `checkd(status, 3); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_gen_defparam_multi.py0000755000542200017500000000076315101701376023616 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_trace_ascendingrange_fst_sc.out0000644000542200017500000002671115101701376025640 0ustar mahmoudyfreeshell$date Sat Apr 5 13:56:21 2025 $end $version fstWriter $end $timescale 1ps $end $scope module top $end $scope module t $end $var parameter 8 ! P [0:7] $end $var wire 1 " clk $end $var int 32 # cyc [31:0] $end $var parameter 8 $ Q [0:7] $end $var logic 1 % v_a [0:0] $end $var logic 2 & v_b [0:1] $end $var logic 8 ' v_c [0:7] $end $var logic 9 ( v_d [0:8] $end $var logic 16 ) v_e [0:15] $end $var logic 17 * v_f [0:16] $end $var logic 32 + v_g [0:31] $end $var logic 33 , v_h [0:32] $end $var logic 64 - v_i [0:63] $end $var logic 65 . v_j [0:64] $end $var logic 128 / v_k [0:127] $end $var logic 129 0 v_l [0:128] $end $var logic 256 1 v_m [0:255] $end $var logic 257 2 v_n [0:256] $end $var logic 512 3 v_o [0:511] $end $var logic 3 4 v_p [-1:1] $end $var logic 15 5 v_q [-7:7] $end $var logic 31 6 v_r [-15:15] $end $var logic 63 7 v_s [-31:31] $end $var logic 127 8 v_t [-63:63] $end $var logic 255 9 v_u [-127:127] $end $var logic 511 : v_v [-255:255] $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 : b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 9 b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 8 b000000000000000000000000000000000000000000000000000000000000000 7 b0000000000000000000000000000000 6 b000000000000000 5 b000 4 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2 b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 1 b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 0 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 / b00000000000000000000000000000000000000000000000000000000000000000 . b0000000000000000000000000000000000000000000000000000000000000000 - b000000000000000000000000000000000 , b00000000000000000000000000000000 + b00000000000000000 * b0000000000000000 ) b000000000 ( b00000000 ' b00 & 0% b00010100 $ b00000000000000000000000000000000 # 0" b00001010 ! $end #10 1" b00000000000000000000000000000001 # 1% b11 & b11111111 ' b111111111 ( b1111111111111111 ) b11111111111111111 * b11111111111111111111111111111111 + b111111111111111111111111111111111 , b1111111111111111111111111111111111111111111111111111111111111111 - b11111111111111111111111111111111111111111111111111111111111111111 . b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 / b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 0 b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 1 b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 2 b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 3 b111 4 b111111111111111 5 b1111111111111111111111111111111 6 b111111111111111111111111111111111111111111111111111111111111111 7 b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 8 b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 9 b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 : #15 0" #20 1" b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 : b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 9 b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 8 b111111111111111111111111111111111111111111111111111111111111110 7 b1111111111111111111111111111110 6 b111111111111110 5 b110 4 b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 3 b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 2 b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 1 b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 0 b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 / b11111111111111111111111111111111111111111111111111111111111111110 . b1111111111111111111111111111111111111111111111111111111111111110 - b111111111111111111111111111111110 , b11111111111111111111111111111110 + b11111111111111110 * b1111111111111110 ) b111111110 ( b11111110 ' b10 & 0% b00000000000000000000000000000010 # #25 0" #30 1" b00000000000000000000000000000011 # b00 & b11111100 ' b111111100 ( b1111111111111100 ) b11111111111111100 * b11111111111111111111111111111100 + b111111111111111111111111111111100 , b1111111111111111111111111111111111111111111111111111111111111100 - b11111111111111111111111111111111111111111111111111111111111111100 . b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 / b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 0 b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 1 b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 2 b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 3 b100 4 b111111111111100 5 b1111111111111111111111111111100 6 b111111111111111111111111111111111111111111111111111111111111100 7 b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 8 b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 9 b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 : #34 verilator-5.042/test_regress/t/t_vpi_public_depth_off.py0000755000542200017500000000165315101701376024145 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.pli_filename = "t/t_vpi_public_depth.cpp" test.top_filename = "t/t_vpi_public_depth.v" test.compile(make_top_shell=False, make_main=False, make_pli=True, iv_flags2=["-g2005-sv"], verilator_flags2=[ "+define+USE_DOLLAR_C32 --exe --vpi --no-l2name", test.pli_filename, "--public-depth 2" ], make_flags=['CPPFLAGS_ADD=-DTEST_VPI_PUBLIC_DEPTH_OFF']) test.execute(use_libvpi=True) test.passes() verilator-5.042/test_regress/t/t_randomize_complex_queue.py0000755000542200017500000000104615101701376024712 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_threads_nondeterminism.py0000755000542200017500000000122015101701376024526 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vltmt') test.top_filename = "t/t_threads_counter.v" test.compile(verilator_flags2=['--cc --debug-nondeterminism --no-skip-identical'], threads=2) test.execute() test.file_grep(test.compile_log_filename, r'Hash of shape') test.passes() verilator-5.042/test_regress/t/t_cover_lib__2.out0000644000542200017500000000032415101701376022465 0ustar mahmoudyfreeshell# SystemC::Coverage-3 C 'f../../t/t_cover_lib_c.cppl48t_userpagesp_user/t_cover_lib_cokept_onehmain' 100 C 'f../../t/t_cover_lib_c.cppl49t_userpagesp_user/t_cover_lib_cokept_twohmain' 210 verilator-5.042/test_regress/t/t_mailbox_unbounded.py0000755000542200017500000000077715101701376023477 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary -Wall"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_covergroup_with_sample_args.py0000755000542200017500000000070615101701376025574 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.passes() verilator-5.042/test_regress/t/t_opt_balance_cats_nofunc.py0000755000542200017500000000137015101701376024620 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_opt_balance_cats.v" test.compile(verilator_flags2=[ "--stats", "-fno-func-opt", "-fno-func-opt-balance-cat", "-fno-func-opt-split-cat" ]) test.file_grep_not(test.stats, r'Optimizations, FuncOpt concat trees balances') test.file_grep_not(test.stats, r'Optimizations, FuncOpt concat splits') test.passes() verilator-5.042/test_regress/t/t_interface_virtual_unused2.v0000644000542200017500000000077415101701376024763 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 interface QBus(input logic k); logic data; endinterface class cls; virtual QBus vif1; function void foo(virtual QBus vif2); vif2.data = 1; endfunction endclass module t; cls bar; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_castdyn_castconst_bad.py0000755000542200017500000000076615101701376024333 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dpi_result_type_bad.v0000644000542200017500000004165015101701376023627 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2020 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t_dpi_result_type_bad; // Illegal result types for DPI functions //====================================================================== // Type definitions //====================================================================== // 2-state packed arrays of width > 32 typedef bit [ 32:0] array_2_state_33_t; typedef bit [ 63:0] array_2_state_64_t; typedef bit [ 64:0] array_2_state_65_t; typedef bit [127:0] array_2_state_128_t; // 2-state packed structures of width > 32 typedef struct packed { bit [15:0] x; bit [16:0] y; } struct_2_state_33; typedef struct packed { bit [31:0] x; bit [31:0] y; } struct_2_state_64; typedef struct packed { bit [31:0] x; bit [32:0] y; } struct_2_state_65; typedef struct packed { bit [63:0] x; bit [63:0] y; } struct_2_state_128; // 2-state packed unions of width > 32 typedef union packed { bit [ 32:0] x; bit [ 32:0] y; } union_2_state_33; typedef union packed { bit [ 63:0] x; bit [ 63:0] y; } union_2_state_64; typedef union packed { bit [ 64:0] x; bit [ 64:0] y; } union_2_state_65; typedef union packed { bit [127:0] x; bit [127:0] y; } union_2_state_128; // 4-state packed arrays of any size typedef logic [ 0:0] array_4_state_1_t; typedef logic [ 1:0] array_4_state_2_t; typedef logic [ 7:0] array_4_state_8_t; typedef logic [ 8:0] array_4_state_9_t; typedef logic [ 15:0] array_4_state_16_t; typedef logic [ 16:0] array_4_state_17_t; typedef logic [ 31:0] array_4_state_32_t; typedef logic [ 32:0] array_4_state_33_t; typedef logic [ 63:0] array_4_state_64_t; typedef logic [ 64:0] array_4_state_65_t; typedef logic [127:0] array_4_state_128_t; // 4-state packed structures of any size typedef struct packed { logic [ 0:0] x; } struct_4_state_1; typedef struct packed { logic [ 0:0] x; bit [ 0:0] y; } struct_4_state_2; typedef struct packed { logic [ 3:0] x; bit [ 3:0] y; } struct_4_state_8; typedef struct packed { logic [ 3:0] x; bit [ 4:0] y; } struct_4_state_9; typedef struct packed { logic [ 7:0] x; bit [ 7:0] y; } struct_4_state_16; typedef struct packed { logic [ 7:0] x; bit [ 8:0] y; } struct_4_state_17; typedef struct packed { logic [15:0] x; bit [15:0] y; } struct_4_state_32; typedef struct packed { logic [15:0] x; bit [16:0] y; } struct_4_state_33; typedef struct packed { logic [31:0] x; bit [31:0] y; } struct_4_state_64; typedef struct packed { logic [31:0] x; bit [32:0] y; } struct_4_state_65; typedef struct packed { logic [63:0] x; bit [63:0] y; } struct_4_state_128; // 4-state packed unions of any size typedef union packed { logic [ 0:0] x; bit [ 0:0] y; } union_4_state_1; typedef union packed { logic [ 1:0] x; bit [ 1:0] y; } union_4_state_2; typedef union packed { logic [ 7:0] x; bit [ 7:0] y; } union_4_state_8; typedef union packed { logic [ 8:0] x; bit [ 8:0] y; } union_4_state_9; typedef union packed { logic [ 15:0] x; bit [ 15:0] y; } union_4_state_16; typedef union packed { logic [ 16:0] x; bit [ 16:0] y; } union_4_state_17; typedef union packed { logic [ 31:0] x; bit [ 31:0] y; } union_4_state_32; typedef union packed { logic [ 32:0] x; bit [ 32:0] y; } union_4_state_33; typedef union packed { logic [ 63:0] x; bit [ 63:0] y; } union_4_state_64; typedef union packed { logic [ 64:0] x; bit [ 64:0] y; } union_4_state_65; typedef union packed { logic [127:0] x; bit [127:0] y; } union_4_state_128; //====================================================================== // Imports //====================================================================== // 2-state packed arrays of width > 32 import "DPI-C" function bit [ 32:0] i_array_2_state_33(); import "DPI-C" function bit [ 63:0] i_array_2_state_64(); import "DPI-C" function bit [ 64:0] i_array_2_state_65(); import "DPI-C" function bit [127:0] i_array_2_state_128(); // 2-state packed arrays of width > 32 via typedef import "DPI-C" function array_2_state_33_t i_array_2_state_33_t(); import "DPI-C" function array_2_state_64_t i_array_2_state_64_t(); import "DPI-C" function array_2_state_65_t i_array_2_state_65_t(); import "DPI-C" function array_2_state_128_t i_array_2_state_128_t(); // 2-state packed structures of width > 32 import "DPI-C" function struct_2_state_33 i_struct_2_state_33(); import "DPI-C" function struct_2_state_64 i_struct_2_state_64(); import "DPI-C" function struct_2_state_65 i_struct_2_state_65(); import "DPI-C" function struct_2_state_128 i_struct_2_state_128(); // 2-state packed unions of width > 32 import "DPI-C" function union_2_state_33 i_union_2_state_33(); import "DPI-C" function union_2_state_64 i_union_2_state_64(); import "DPI-C" function union_2_state_65 i_union_2_state_65(); import "DPI-C" function union_2_state_128 i_union_2_state_128(); // 4-state basic types import "DPI-C" function integer i_integer(); // 4-state packed arrays of any size import "DPI-C" function logic [ 0:0] i_array_4_state_1(); import "DPI-C" function logic [ 1:0] i_array_4_state_2(); import "DPI-C" function logic [ 7:0] i_array_4_state_8(); import "DPI-C" function logic [ 8:0] i_array_4_state_9(); import "DPI-C" function logic [ 15:0] i_array_4_state_16(); import "DPI-C" function logic [ 16:0] i_array_4_state_17(); import "DPI-C" function logic [ 31:0] i_array_4_state_32(); import "DPI-C" function logic [ 32:0] i_array_4_state_33(); import "DPI-C" function logic [ 63:0] i_array_4_state_64(); import "DPI-C" function logic [ 64:0] i_array_4_state_65(); import "DPI-C" function logic [127:0] i_array_4_state_128(); // 4-state packed arrays of any size via typedef import "DPI-C" function array_4_state_1_t i_array_4_state_1_t(); import "DPI-C" function array_4_state_2_t i_array_4_state_2_t(); import "DPI-C" function array_4_state_8_t i_array_4_state_8_t(); import "DPI-C" function array_4_state_9_t i_array_4_state_9_t(); import "DPI-C" function array_4_state_16_t i_array_4_state_16_t(); import "DPI-C" function array_4_state_17_t i_array_4_state_17_t(); import "DPI-C" function array_4_state_32_t i_array_4_state_32_t(); import "DPI-C" function array_4_state_33_t i_array_4_state_33_t(); import "DPI-C" function array_4_state_64_t i_array_4_state_64_t(); import "DPI-C" function array_4_state_65_t i_array_4_state_65_t(); import "DPI-C" function array_4_state_128_t i_array_4_state_128_t(); // 4-state packed structures of any size import "DPI-C" function struct_4_state_1 i_struct_4_state_1(); import "DPI-C" function struct_4_state_2 i_struct_4_state_2(); import "DPI-C" function struct_4_state_8 i_struct_4_state_8(); import "DPI-C" function struct_4_state_9 i_struct_4_state_9(); import "DPI-C" function struct_4_state_16 i_struct_4_state_16(); import "DPI-C" function struct_4_state_17 i_struct_4_state_17(); import "DPI-C" function struct_4_state_32 i_struct_4_state_32(); import "DPI-C" function struct_4_state_33 i_struct_4_state_33(); import "DPI-C" function struct_4_state_64 i_struct_4_state_64(); import "DPI-C" function struct_4_state_65 i_struct_4_state_65(); import "DPI-C" function struct_4_state_128 i_struct_4_state_128(); // 4-state packed unions of any size import "DPI-C" function union_4_state_1 i_union_4_state_1(); import "DPI-C" function union_4_state_2 i_union_4_state_2(); import "DPI-C" function union_4_state_8 i_union_4_state_8(); import "DPI-C" function union_4_state_9 i_union_4_state_9(); import "DPI-C" function union_4_state_16 i_union_4_state_16(); import "DPI-C" function union_4_state_17 i_union_4_state_17(); import "DPI-C" function union_4_state_32 i_union_4_state_32(); import "DPI-C" function union_4_state_33 i_union_4_state_33(); import "DPI-C" function union_4_state_64 i_union_4_state_64(); import "DPI-C" function union_4_state_65 i_union_4_state_65(); import "DPI-C" function union_4_state_128 i_union_4_state_128(); //====================================================================== // Exports //====================================================================== // 2-state packed arrays of width > 32 export "DPI-C" function e_array_2_state_33; export "DPI-C" function e_array_2_state_64; export "DPI-C" function e_array_2_state_65; export "DPI-C" function e_array_2_state_128; // 2-state packed arrays of width > 32 via typedef export "DPI-C" function e_array_2_state_33_t; export "DPI-C" function e_array_2_state_64_t; export "DPI-C" function e_array_2_state_65_t; export "DPI-C" function e_array_2_state_128_t; // 2-state packed structures of width > 32 export "DPI-C" function e_struct_2_state_33; export "DPI-C" function e_struct_2_state_64; export "DPI-C" function e_struct_2_state_65; export "DPI-C" function e_struct_2_state_128; // 2-state packed unions of width > 32 export "DPI-C" function e_union_2_state_33; export "DPI-C" function e_union_2_state_64; export "DPI-C" function e_union_2_state_65; export "DPI-C" function e_union_2_state_128; // 4-state basic types export "DPI-C" function e_integer; // 4-state packed arrays of any size export "DPI-C" function e_array_4_state_1; export "DPI-C" function e_array_4_state_2; export "DPI-C" function e_array_4_state_8; export "DPI-C" function e_array_4_state_9; export "DPI-C" function e_array_4_state_16; export "DPI-C" function e_array_4_state_17; export "DPI-C" function e_array_4_state_32; export "DPI-C" function e_array_4_state_33; export "DPI-C" function e_array_4_state_64; export "DPI-C" function e_array_4_state_65; export "DPI-C" function e_array_4_state_128; // 4-state packed arrays of any size via typedef export "DPI-C" function e_array_4_state_1_t; export "DPI-C" function e_array_4_state_2_t; export "DPI-C" function e_array_4_state_8_t; export "DPI-C" function e_array_4_state_9_t; export "DPI-C" function e_array_4_state_16_t; export "DPI-C" function e_array_4_state_17_t; export "DPI-C" function e_array_4_state_32_t; export "DPI-C" function e_array_4_state_33_t; export "DPI-C" function e_array_4_state_64_t; export "DPI-C" function e_array_4_state_65_t; export "DPI-C" function e_array_4_state_128_t; // 4-state packed structures of any size export "DPI-C" function e_struct_4_state_1; export "DPI-C" function e_struct_4_state_2; export "DPI-C" function e_struct_4_state_8; export "DPI-C" function e_struct_4_state_9; export "DPI-C" function e_struct_4_state_16; export "DPI-C" function e_struct_4_state_17; export "DPI-C" function e_struct_4_state_32; export "DPI-C" function e_struct_4_state_33; export "DPI-C" function e_struct_4_state_64; export "DPI-C" function e_struct_4_state_65; export "DPI-C" function e_struct_4_state_128; // 4-state packed unions of any size export "DPI-C" function e_union_4_state_1; export "DPI-C" function e_union_4_state_2; export "DPI-C" function e_union_4_state_8; export "DPI-C" function e_union_4_state_9; export "DPI-C" function e_union_4_state_16; export "DPI-C" function e_union_4_state_17; export "DPI-C" function e_union_4_state_32; export "DPI-C" function e_union_4_state_33; export "DPI-C" function e_union_4_state_64; export "DPI-C" function e_union_4_state_65; export "DPI-C" function e_union_4_state_128; //====================================================================== // Definitions of exported functions //====================================================================== // 2-state packed arrays of width > 32 function bit [ 32:0] e_array_2_state_33(); return 0; endfunction function bit [ 63:0] e_array_2_state_64(); return 0; endfunction function bit [ 64:0] e_array_2_state_65(); return 0; endfunction function bit [127:0] e_array_2_state_128(); return 0; endfunction // 2-state packed arrays of width > 32 via typedef function array_2_state_33_t e_array_2_state_33_t(); return 0; endfunction function array_2_state_64_t e_array_2_state_64_t(); return 0; endfunction function array_2_state_65_t e_array_2_state_65_t(); return 0; endfunction function array_2_state_128_t e_array_2_state_128_t(); return 0; endfunction // 2-state packed structures of width > 32 function struct_2_state_33 e_struct_2_state_33(); return 0; endfunction function struct_2_state_64 e_struct_2_state_64(); return 0; endfunction function struct_2_state_65 e_struct_2_state_65(); return 0; endfunction function struct_2_state_128 e_struct_2_state_128(); return 0; endfunction // 2-state packed unions of width > 32 function union_2_state_33 e_union_2_state_33(); return 0; endfunction function union_2_state_64 e_union_2_state_64(); return 0; endfunction function union_2_state_65 e_union_2_state_65(); return 0; endfunction function union_2_state_128 e_union_2_state_128(); return 0; endfunction // 4-state basic types function integer e_integer(); return 0; endfunction // 4-state packed arrays of any size function logic [ 0:0] e_array_4_state_1(); return 0; endfunction function logic [ 1:0] e_array_4_state_2(); return 0; endfunction function logic [ 7:0] e_array_4_state_8(); return 0; endfunction function logic [ 8:0] e_array_4_state_9(); return 0; endfunction function logic [ 15:0] e_array_4_state_16(); return 0; endfunction function logic [ 16:0] e_array_4_state_17(); return 0; endfunction function logic [ 31:0] e_array_4_state_32(); return 0; endfunction function logic [ 32:0] e_array_4_state_33(); return 0; endfunction function logic [ 63:0] e_array_4_state_64(); return 0; endfunction function logic [ 64:0] e_array_4_state_65(); return 0; endfunction function logic [127:0] e_array_4_state_128(); return 0; endfunction // 4-state packed arrays of any size via typedef function array_4_state_1_t e_array_4_state_1_t(); return 0; endfunction function array_4_state_2_t e_array_4_state_2_t(); return 0; endfunction function array_4_state_8_t e_array_4_state_8_t(); return 0; endfunction function array_4_state_9_t e_array_4_state_9_t(); return 0; endfunction function array_4_state_16_t e_array_4_state_16_t(); return 0; endfunction function array_4_state_17_t e_array_4_state_17_t(); return 0; endfunction function array_4_state_32_t e_array_4_state_32_t(); return 0; endfunction function array_4_state_33_t e_array_4_state_33_t(); return 0; endfunction function array_4_state_64_t e_array_4_state_64_t(); return 0; endfunction function array_4_state_65_t e_array_4_state_65_t(); return 0; endfunction function array_4_state_128_t e_array_4_state_128_t(); return 0; endfunction // 4-state packed structures of any size function struct_4_state_1 e_struct_4_state_1(); return 0; endfunction function struct_4_state_2 e_struct_4_state_2(); return 0; endfunction function struct_4_state_8 e_struct_4_state_8(); return 0; endfunction function struct_4_state_9 e_struct_4_state_9(); return 0; endfunction function struct_4_state_16 e_struct_4_state_16(); return 0; endfunction function struct_4_state_17 e_struct_4_state_17(); return 0; endfunction function struct_4_state_32 e_struct_4_state_32(); return 0; endfunction function struct_4_state_33 e_struct_4_state_33(); return 0; endfunction function struct_4_state_64 e_struct_4_state_64(); return 0; endfunction function struct_4_state_65 e_struct_4_state_65(); return 0; endfunction function struct_4_state_128 e_struct_4_state_128(); return 0; endfunction // 4-state packed unions of any size function union_4_state_1 e_union_4_state_1(); return 0; endfunction function union_4_state_2 e_union_4_state_2(); return 0; endfunction function union_4_state_8 e_union_4_state_8(); return 0; endfunction function union_4_state_9 e_union_4_state_9(); return 0; endfunction function union_4_state_16 e_union_4_state_16(); return 0; endfunction function union_4_state_17 e_union_4_state_17(); return 0; endfunction function union_4_state_32 e_union_4_state_32(); return 0; endfunction function union_4_state_33 e_union_4_state_33(); return 0; endfunction function union_4_state_64 e_union_4_state_64(); return 0; endfunction function union_4_state_65 e_union_4_state_65(); return 0; endfunction function union_4_state_128 e_union_4_state_128(); return 0; endfunction endmodule verilator-5.042/test_regress/t/t_class_super_bad2.out0000644000542200017500000000041615101701376023356 0ustar mahmoudyfreeshell%Error: t/t_class_super_bad2.v:10:12: 'super' used on non-extended class (IEEE 1800-2023 8.15) 10 | super.i = 1; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_flag_ldflags_c.cpp0000644000542200017500000000203415101701376023023 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "svdpi.h" #include //====================================================================== // clang-format off #if defined(VERILATOR) # include "Vt_flag_ldflags__Dpi.h" #else # error "Unknown simulator for DPI test" #endif //====================================================================== #ifndef CFLAGS_FROM_CMDLINE # error "CFLAGS_FROM_CMDLINE not set - not passed down?" #endif #ifndef CFLAGS2_FROM_CMDLINE # error "CFLAGS2_FROM_CMDLINE not set - not passed down?" #endif // clang-format on void dpii_c_library() {} verilator-5.042/test_regress/t/t_array_unpacked_public.py0000755000542200017500000000100115101701376024304 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--public-flat-rw"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_func_const_packed_struct_bad2.v0000644000542200017500000000225315101701376025546 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 module t; typedef struct packed { logic [ 31 : 0 ] b; logic [ 7 : 0 ] bar; } sub_params_t; typedef struct packed { logic [ 31 : 0 ] a; logic [ 5 : 0 ] foo; sub_params_t sub_params; } params_t; localparam P24 = f_add2(7, 8, 9); initial begin // Should never get here $write("*-* All Finished *-*\n"); $finish; end function integer f_add(input params_t [ 1 : 0 ] params); f_add = params[0].a+params[1].sub_params.b; if (f_add == 15) $fatal(2, "f_add = 15"); endfunction // Speced ok: function called from function function integer f_add2(input [31:0] a, input [31:0] b, input [31:0] c); params_t [ 1 : 0 ] params; sub_params_t sp0; sub_params_t sp1; sp0 = '{b:55, bar:111}; params[0] = '{a:a, foo:11, sub_params:sp0}; sp1 = '{b:b, bar:112}; params[1] = '{a:12345, foo:12, sub_params:sp1}; f_add2 = f_add(params)+c; endfunction endmodule verilator-5.042/test_regress/t/t_covergroup_func_override_bad.out0000644000542200017500000000040315101701376026052 0ustar mahmoudyfreeshell%Error: t/t_covergroup_func_override_bad.v:10:5: syntax error, unexpected function 10 | function sample(); | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_flag_quiet_stats.py0000755000542200017500000000117415101701376023327 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=['--quiet-stats'], verilator_make_gcc=False, logfile=test.run_log_filename) test.file_grep_not(test.compile_log_filename, r'V e r i l a t') test.passes() verilator-5.042/test_regress/t/t_altera_lpm_and.py0000755000542200017500000000111115101701376022722 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) test.compile(verilator_flags2=["--top-module", module]) test.passes() verilator-5.042/test_regress/t/t_class_assign_cond_bad.out0000644000542200017500000000272215101701376024427 0ustar mahmoudyfreeshell%Error: t/t_class_assign_cond_bad.v:22:25: Incompatible types of operands of condition operator: CLASSREFDTYPE 'Cls1' and CLASSREFDTYPE 'Cls2' : ... note: In instance 't' 22 | c1 = (c1 != null) ? c1 : c2; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_class_assign_cond_bad.v:23:10: Assign RHS expects a CLASSREFDTYPE 'Cls1', got CLASSREFDTYPE 'Cls2' : ... note: In instance 't' 23 | c1 = (c1 != null) ? c2 : c2; | ^ %Error: t/t_class_assign_cond_bad.v:24:25: Incompatible types of operands of condition operator: BASICDTYPE 'logic' and CLASSREFDTYPE 'Cls2' : ... note: In instance 't' 24 | c2 = (c1 == null) ? 1'b1 : c2; | ^ %Error: t/t_class_assign_cond_bad.v:24:10: Assign RHS expects a CLASSREFDTYPE 'Cls2', got BASICDTYPE 'logic' : ... note: In instance 't' 24 | c2 = (c1 == null) ? 1'b1 : c2; | ^ %Error: t/t_class_assign_cond_bad.v:25:29: Incompatible types of operands of condition operator: CLASSREFDTYPE 'ExtCls1' and CLASSREFDTYPE 'Cls1' : ... note: In instance 't' 25 | ext_c1 = (c1 == null) ? ext_c1 : c1; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_randomize_method_std.v0000644000542200017500000000072215101701376024003 0ustar mahmoudyfreeshell// DESCRIPTION: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 process p; // force importing std into top-level namespace class C; function new; if (randomize() != 1) $stop; endfunction endclass module t; initial begin C c = new; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_interface_wrong_bad.v0000644000542200017500000000131115101701376023556 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Using the wrong kind of interface in a portmap // should cause an error // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2018 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 interface foo_intf; logic [7:0] a; endinterface interface bar_intf; logic [7:0] a; endinterface module foo_mod (foo_intf foo_port); // initial begin // $display("a = %0d", foo_port.a); // end endmodule module t; foo_intf foo (); bar_intf bar (); // assign foo.a = 8'd1; // assign bar.a = 8'd2; foo_mod foo_mod ( .foo_port (bar) ); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_assoc_method_map.v0000644000542200017500000000127215101701376023107 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); module t; initial begin int res[]; int a[int] = '{1: 100, 2: 200, 3: 300}; // TODO results not known to be correct res = a.map(el) with (el == 2); `checkh(res.size, 3); `checkh(res[0], 0); `checkh(res[1], 1); `checkh(res[2], 0); end endmodule verilator-5.042/test_regress/t/t_savable_class_bad.py0000755000542200017500000000110415101701376023372 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(v_flags2=["--savable"], save_time=500, fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_type_param_circ_bad.v0000644000542200017500000000066115101701376023552 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package pkg; parameter [7:0] WIDTH = 8; typedef logic [WIDTH-1:0] SZ; endpackage // pkg module t import pkg::*; # (parameter type SZ = SZ) (input SZ i, output SZ o); always_comb o = i; endmodule verilator-5.042/test_regress/t/t_randomize_with_constraint.py0000755000542200017500000000076315101701376025263 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_param_enum_bad.py0000755000542200017500000000076615101701376024116 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dynarray.py0000755000542200017500000000073415101701376021623 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_two_dump_cc.out0000644000542200017500000000365115101701376023630 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module topa $end $var wire 1 # clk $end $scope module t $end $var wire 1 # clk $end $var wire 32 $ cyc [31:0] $end $var wire 32 % c_trace_on [31:0] $end $scope module sub $end $var wire 32 & inside_sub_a [31:0] $end $upscope $end $upscope $end $upscope $end $scope module topb $end $var wire 1 ( clk $end $scope module t $end $var wire 1 ( clk $end $var wire 32 + cyc [31:0] $end $var wire 32 , c_trace_on [31:0] $end $var real 64 ) r $end $scope module sub $end $var wire 32 - inside_sub_a [31:0] $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #10 1# b00000000000000000000000000000001 $ b00000000000000000000000000000000 % 1( r0 ) b00000000000000000000000000000001 & b00000000000000000000000000000001 + b00000000000000000000000000000000 , b00000000000000000000000000000010 - #15 0# 0( #20 1# b00000000000000000000000000000010 $ b00000000000000000000000000000011 % 1( r0.1 ) #25 0# 0( #30 1# b00000000000000000000000000000011 $ b00000000000000000000000000000100 % 1( r0.2 ) #35 0# 0( #40 1# b00000000000000000000000000000100 $ b00000000000000000000000000000101 % 1( r0.3 ) #45 0# 0( #50 1# b00000000000000000000000000000101 $ b00000000000000000000000000000110 % 1( r0.4 ) #55 0# 0( #60 1# b00000000000000000000000000000110 $ b00000000000000000000000000000111 % 1( r0.5 ) #65 0# 0( #70 1# b00000000000000000000000000000111 $ b00000000000000000000000000001000 % 1( r0.6 ) #75 0# 0( #80 1# b00000000000000000000000000001000 $ b00000000000000000000000000001001 % 1( r0.7 ) #85 0# 0( #90 1# b00000000000000000000000000001001 $ b00000000000000000000000000001010 % 1( r0.7999999999999999 ) #95 0# 0( #100 1# b00000000000000000000000000001010 $ b00000000000000000000000000001011 % 1( r0.8999999999999999 ) #105 0# 0( #110 1# b00000000000000000000000000001011 $ b00000000000000000000000000001100 % 1( r0.9999999999999999 ) verilator-5.042/test_regress/t/t_dpi_result_type_bad.out0000644000542200017500000010723615101701376024174 0ustar mahmoudyfreeshell%Error: t/t_dpi_result_type_bad.v:79:40: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? 79 | import "DPI-C" function bit [ 32:0] i_array_2_state_33(); | ^~~~~~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_dpi_result_type_bad.v:80:40: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? 80 | import "DPI-C" function bit [ 63:0] i_array_2_state_64(); | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:81:40: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? 81 | import "DPI-C" function bit [ 64:0] i_array_2_state_65(); | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:82:40: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? 82 | import "DPI-C" function bit [127:0] i_array_2_state_128(); | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:85:48: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? 85 | import "DPI-C" function array_2_state_33_t i_array_2_state_33_t(); | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:86:48: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? 86 | import "DPI-C" function array_2_state_64_t i_array_2_state_64_t(); | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:87:48: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? 87 | import "DPI-C" function array_2_state_65_t i_array_2_state_65_t(); | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:88:48: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? 88 | import "DPI-C" function array_2_state_128_t i_array_2_state_128_t(); | ^~~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:91:47: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? 91 | import "DPI-C" function struct_2_state_33 i_struct_2_state_33(); | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:92:47: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? 92 | import "DPI-C" function struct_2_state_64 i_struct_2_state_64(); | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:93:47: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? 93 | import "DPI-C" function struct_2_state_65 i_struct_2_state_65(); | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:94:47: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? 94 | import "DPI-C" function struct_2_state_128 i_struct_2_state_128(); | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:97:46: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? 97 | import "DPI-C" function union_2_state_33 i_union_2_state_33(); | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:98:46: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? 98 | import "DPI-C" function union_2_state_64 i_union_2_state_64(); | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:99:46: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? 99 | import "DPI-C" function union_2_state_65 i_union_2_state_65(); | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:100:46: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? 100 | import "DPI-C" function union_2_state_128 i_union_2_state_128(); | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:103:36: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 103 | import "DPI-C" function integer i_integer(); | ^~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:106:42: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 106 | import "DPI-C" function logic [ 0:0] i_array_4_state_1(); | ^~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:107:42: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 107 | import "DPI-C" function logic [ 1:0] i_array_4_state_2(); | ^~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:108:42: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 108 | import "DPI-C" function logic [ 7:0] i_array_4_state_8(); | ^~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:109:42: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 109 | import "DPI-C" function logic [ 8:0] i_array_4_state_9(); | ^~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:110:42: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 110 | import "DPI-C" function logic [ 15:0] i_array_4_state_16(); | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:111:42: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 111 | import "DPI-C" function logic [ 16:0] i_array_4_state_17(); | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:112:42: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 112 | import "DPI-C" function logic [ 31:0] i_array_4_state_32(); | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:113:42: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 113 | import "DPI-C" function logic [ 32:0] i_array_4_state_33(); | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:114:42: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 114 | import "DPI-C" function logic [ 63:0] i_array_4_state_64(); | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:115:42: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 115 | import "DPI-C" function logic [ 64:0] i_array_4_state_65(); | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:116:42: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 116 | import "DPI-C" function logic [127:0] i_array_4_state_128(); | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:119:48: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 119 | import "DPI-C" function array_4_state_1_t i_array_4_state_1_t(); | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:120:48: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 120 | import "DPI-C" function array_4_state_2_t i_array_4_state_2_t(); | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:121:48: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 121 | import "DPI-C" function array_4_state_8_t i_array_4_state_8_t(); | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:122:48: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 122 | import "DPI-C" function array_4_state_9_t i_array_4_state_9_t(); | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:123:48: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 123 | import "DPI-C" function array_4_state_16_t i_array_4_state_16_t(); | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:124:48: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 124 | import "DPI-C" function array_4_state_17_t i_array_4_state_17_t(); | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:125:48: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 125 | import "DPI-C" function array_4_state_32_t i_array_4_state_32_t(); | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:126:48: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 126 | import "DPI-C" function array_4_state_33_t i_array_4_state_33_t(); | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:127:48: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 127 | import "DPI-C" function array_4_state_64_t i_array_4_state_64_t(); | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:128:48: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 128 | import "DPI-C" function array_4_state_65_t i_array_4_state_65_t(); | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:129:48: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 129 | import "DPI-C" function array_4_state_128_t i_array_4_state_128_t(); | ^~~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:132:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 132 | import "DPI-C" function struct_4_state_1 i_struct_4_state_1(); | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:133:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 133 | import "DPI-C" function struct_4_state_2 i_struct_4_state_2(); | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:134:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 134 | import "DPI-C" function struct_4_state_8 i_struct_4_state_8(); | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:135:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 135 | import "DPI-C" function struct_4_state_9 i_struct_4_state_9(); | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:136:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 136 | import "DPI-C" function struct_4_state_16 i_struct_4_state_16(); | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:137:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 137 | import "DPI-C" function struct_4_state_17 i_struct_4_state_17(); | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:138:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 138 | import "DPI-C" function struct_4_state_32 i_struct_4_state_32(); | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:139:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 139 | import "DPI-C" function struct_4_state_33 i_struct_4_state_33(); | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:140:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 140 | import "DPI-C" function struct_4_state_64 i_struct_4_state_64(); | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:141:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 141 | import "DPI-C" function struct_4_state_65 i_struct_4_state_65(); | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:142:47: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 142 | import "DPI-C" function struct_4_state_128 i_struct_4_state_128(); | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:145:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 145 | import "DPI-C" function union_4_state_1 i_union_4_state_1(); | ^~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:146:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 146 | import "DPI-C" function union_4_state_2 i_union_4_state_2(); | ^~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:147:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 147 | import "DPI-C" function union_4_state_8 i_union_4_state_8(); | ^~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:148:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 148 | import "DPI-C" function union_4_state_9 i_union_4_state_9(); | ^~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:149:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 149 | import "DPI-C" function union_4_state_16 i_union_4_state_16(); | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:150:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 150 | import "DPI-C" function union_4_state_17 i_union_4_state_17(); | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:151:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 151 | import "DPI-C" function union_4_state_32 i_union_4_state_32(); | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:152:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 152 | import "DPI-C" function union_4_state_33 i_union_4_state_33(); | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:153:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 153 | import "DPI-C" function union_4_state_64 i_union_4_state_64(); | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:154:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 154 | import "DPI-C" function union_4_state_65 i_union_4_state_65(); | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:155:46: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 155 | import "DPI-C" function union_4_state_128 i_union_4_state_128(); | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:245:25: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? 245 | function bit [ 32:0] e_array_2_state_33(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:246:25: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? 246 | function bit [ 63:0] e_array_2_state_64(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:247:25: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? 247 | function bit [ 64:0] e_array_2_state_65(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:248:25: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? 248 | function bit [127:0] e_array_2_state_128(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:251:33: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? 251 | function array_2_state_33_t e_array_2_state_33_t(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:252:33: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? 252 | function array_2_state_64_t e_array_2_state_64_t(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:253:33: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? 253 | function array_2_state_65_t e_array_2_state_65_t(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:254:33: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? 254 | function array_2_state_128_t e_array_2_state_128_t(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:257:32: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? 257 | function struct_2_state_33 e_struct_2_state_33(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:258:32: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? 258 | function struct_2_state_64 e_struct_2_state_64(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:259:32: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? 259 | function struct_2_state_65 e_struct_2_state_65(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:260:32: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? 260 | function struct_2_state_128 e_struct_2_state_128(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:263:31: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? 263 | function union_2_state_33 e_union_2_state_33(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:264:31: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? 264 | function union_2_state_64 e_union_2_state_64(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:265:31: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? 265 | function union_2_state_65 e_union_2_state_65(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:266:31: DPI function may not return a > 32 bits wide type other than basic types. : ... Suggest make it an output argument instead? 266 | function union_2_state_128 e_union_2_state_128(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:269:21: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 269 | function integer e_integer(); return 0; endfunction | ^~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:272:27: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 272 | function logic [ 0:0] e_array_4_state_1(); return 0; endfunction | ^~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:273:27: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 273 | function logic [ 1:0] e_array_4_state_2(); return 0; endfunction | ^~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:274:27: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 274 | function logic [ 7:0] e_array_4_state_8(); return 0; endfunction | ^~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:275:27: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 275 | function logic [ 8:0] e_array_4_state_9(); return 0; endfunction | ^~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:276:27: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 276 | function logic [ 15:0] e_array_4_state_16(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:277:27: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 277 | function logic [ 16:0] e_array_4_state_17(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:278:27: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 278 | function logic [ 31:0] e_array_4_state_32(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:279:27: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 279 | function logic [ 32:0] e_array_4_state_33(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:280:27: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 280 | function logic [ 63:0] e_array_4_state_64(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:281:27: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 281 | function logic [ 64:0] e_array_4_state_65(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:282:27: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 282 | function logic [127:0] e_array_4_state_128(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:285:33: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 285 | function array_4_state_1_t e_array_4_state_1_t(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:286:33: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 286 | function array_4_state_2_t e_array_4_state_2_t(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:287:33: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 287 | function array_4_state_8_t e_array_4_state_8_t(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:288:33: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 288 | function array_4_state_9_t e_array_4_state_9_t(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:289:33: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 289 | function array_4_state_16_t e_array_4_state_16_t(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:290:33: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 290 | function array_4_state_17_t e_array_4_state_17_t(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:291:33: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 291 | function array_4_state_32_t e_array_4_state_32_t(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:292:33: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 292 | function array_4_state_33_t e_array_4_state_33_t(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:293:33: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 293 | function array_4_state_64_t e_array_4_state_64_t(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:294:33: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 294 | function array_4_state_65_t e_array_4_state_65_t(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:295:33: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 295 | function array_4_state_128_t e_array_4_state_128_t(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:298:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 298 | function struct_4_state_1 e_struct_4_state_1(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:299:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 299 | function struct_4_state_2 e_struct_4_state_2(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:300:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 300 | function struct_4_state_8 e_struct_4_state_8(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:301:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 301 | function struct_4_state_9 e_struct_4_state_9(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:302:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 302 | function struct_4_state_16 e_struct_4_state_16(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:303:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 303 | function struct_4_state_17 e_struct_4_state_17(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:304:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 304 | function struct_4_state_32 e_struct_4_state_32(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:305:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 305 | function struct_4_state_33 e_struct_4_state_33(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:306:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 306 | function struct_4_state_64 e_struct_4_state_64(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:307:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 307 | function struct_4_state_65 e_struct_4_state_65(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:308:32: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 308 | function struct_4_state_128 e_struct_4_state_128(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:311:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 311 | function union_4_state_1 e_union_4_state_1(); return 0; endfunction | ^~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:312:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 312 | function union_4_state_2 e_union_4_state_2(); return 0; endfunction | ^~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:313:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 313 | function union_4_state_8 e_union_4_state_8(); return 0; endfunction | ^~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:314:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 314 | function union_4_state_9 e_union_4_state_9(); return 0; endfunction | ^~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:315:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 315 | function union_4_state_16 e_union_4_state_16(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:316:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 316 | function union_4_state_17 e_union_4_state_17(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:317:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 317 | function union_4_state_32 e_union_4_state_32(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:318:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 318 | function union_4_state_33 e_union_4_state_33(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:319:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 319 | function union_4_state_64 e_union_4_state_64(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:320:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 320 | function union_4_state_65 e_union_4_state_65(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~ %Error: t/t_dpi_result_type_bad.v:321:31: DPI function may not return a 4-state type other than a single 'logic' (IEEE 1800-2023 35.5.5) 321 | function union_4_state_128 e_union_4_state_128(); return 0; endfunction | ^~~~~~~~~~~~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_vlt_legacy.vlt0000644000542200017500000000052415101701376022272 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `verilator_config clock_enable --module "t" --var "clk" clocker --module "t" --var "clk" no_clocker --module "t" --var "clk" verilator-5.042/test_regress/t/t_struct_type_bad.v0000644000542200017500000000050415101701376022772 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; int i; typedef struct packed { int i; i badi; // Bad } struct_t; endmodule verilator-5.042/test_regress/t/t_vpi_zero_time_cb.v0000644000542200017500000000145715101701376023126 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2010 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [31:0] count /*verilator public_flat_rd */; integer status; // Test loop initial begin count = 0; end always @(posedge clk) begin `ifdef TEST_VERBOSE $display("[%0t] clk", $time); `endif count <= count + 2; if (count == 1000) begin // See C++ code: $write("*-* All Finished *-*\n"); $finish; end end endmodule : t verilator-5.042/test_regress/t/t_flag_supported.py0000755000542200017500000000226515101701376023011 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') if test.have_coroutines: test.run(cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator --get-supported COROUTINES"], logfile=test.obj_dir + "/vlt_coroutines.log", expect_filename="t/t_flag_supported_1.out", verilator_run=True) if test.have_sc: test.run(cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator --get-supported SYSTEMC"], logfile=test.obj_dir + "/vlt_systemc.log", expect_filename="t/t_flag_supported_1.out", verilator_run=True) test.run(cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator --get-supported DOES_NOT_EXIST"], logfile=test.obj_dir + "/vlt_does_not_exist.log", expect_filename="t/t_flag_supported_empty.out", verilator_run=True) test.passes() verilator-5.042/test_regress/t/t_queue_compare.py0000755000542200017500000000073415101701376022624 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_var_bad_sameas.v0000644000542200017500000000121215101701376022523 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; integer varfirst; sub varfirst (); // Error: Cell hits var task varfirst; begin end endtask // Error: Task hits var sub cellfirst (); integer cellfirst; // Error: Var hits cell task cellfirst; begin end endtask // Error: Task hits cell task taskfirst; begin end endtask integer taskfirst; // Error: Var hits task sub taskfirst (); // Error: Cell hits task endmodule module sub; endmodule verilator-5.042/test_regress/t/t_trace_open_wrong_order_bad.out0000755000542200017500000000017015101701376025477 0ustar mahmoudyfreeshell%Error: Testbench C call to 'VerilatedContext::trace()' must not be called after 'VerilatedTrace*::open()' Aborting... verilator-5.042/test_regress/t/t_assert_ctl_unsup.out0000644000542200017500000001663215101701376023547 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:25:7: Unsupported: non-constant assert assertion-type expression : ... note: In instance 't.unsupported_ctl_type' 25 | $assertcontrol(Lock, a); | ^~~~~~~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:27:7: Unsupported: $assertcontrol control_type '2' 27 | $assertcontrol(Unlock); | ^~~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:29:7: Unsupported: $assertcontrol control_type '6' 29 | $assertcontrol(PassOn); | ^~~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:30:7: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' 30 | $assertpasson; | ^~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:31:7: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' 31 | $assertpasson(a); | ^~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:32:7: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' 32 | $assertpasson(a, t); | ^~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:34:7: Unsupported: $assertcontrol control_type '7' 34 | $assertcontrol(PassOff); | ^~~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:35:7: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' 35 | $assertpassoff; | ^~~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:36:7: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' 36 | $assertpassoff(a); | ^~~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:37:7: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' 37 | $assertpassoff(a, t); | ^~~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:39:7: Unsupported: $assertcontrol control_type '8' 39 | $assertcontrol(FailOn); | ^~~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:40:7: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' 40 | $assertfailon; | ^~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:41:7: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' 41 | $assertfailon(a); | ^~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:42:7: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' 42 | $assertfailon(a, t); | ^~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:44:7: Unsupported: $assertcontrol control_type '9' 44 | $assertcontrol(FailOff); | ^~~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:45:7: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' 45 | $assertfailoff; | ^~~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:46:7: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' 46 | $assertfailoff(a); | ^~~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:47:7: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' 47 | $assertfailoff(a, t); | ^~~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:49:7: Unsupported: $assertcontrol control_type '10' 49 | $assertcontrol(NonvacuousOn); | ^~~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:50:7: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' 50 | $assertnonvacuouson; | ^~~~~~~~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:51:7: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' 51 | $assertnonvacuouson(a); | ^~~~~~~~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:52:7: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' 52 | $assertnonvacuouson(a, t); | ^~~~~~~~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:54:7: Unsupported: $assertcontrol control_type '11' 54 | $assertcontrol(VacuousOff); | ^~~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:55:7: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' 55 | $assertvacuousoff; | ^~~~~~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:56:7: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' 56 | $assertvacuousoff(a); | ^~~~~~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:57:7: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' 57 | $assertvacuousoff(a, t); | ^~~~~~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:64:7: Unsupported: non-const assert control type expression : ... note: In instance 't.unsupported_ctl_type_expr' 64 | $assertcontrol(ctl_type); | ^~~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:93:10: Unsupported: assertcontrols in classes or interfaces : ... note: In instance 't.assert_class' 93 | $asserton; | ^~~~~~~~~ %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:99:10: Unsupported: assertcontrols in classes or interfaces : ... note: In instance 't.assert_class' 99 | $assertoff; | ^~~~~~~~~~ %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:172:7: Unsupported: assertcontrols in classes or interfaces : ... note: In instance 't.assert_iface' 172 | $assertoff; | ^~~~~~~~~~ %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:138:7: Unsupported: assertcontrols in classes or interfaces : ... note: In instance 't.assert_iface_class' 138 | $assertoff; | ^~~~~~~~~~ %Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:145:7: Unsupported: assertcontrols in classes or interfaces : ... note: In instance 't.assert_iface_class' 145 | $asserton; | ^~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_lint_implicitstatic_bad.py0000755000542200017500000000105515101701376024645 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) if not test.vlt_all: test.execute() test.passes() verilator-5.042/test_regress/t/t_timing_sched_if.v0000644000542200017500000000333315101701376022715 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; bit clk1 = 0; assign #3 clk1 = ~clk1; bit clk2 = 0; assign #11 clk2 = ~clk2; bit flag = 0; int a1 = 0; int b1 = 0; int c1 = 0; always @(posedge clk1) begin if (flag) #4 a1 = a1 + 1; else @(posedge clk2) b1 = b1 + 1; c1 = c1 + 1; flag = ~flag; end int a2 = 0; always_comb begin // verilator lint_off MULTIDRIVEN a2 = a1 << 1; // verilator lint_on MULTIDRIVEN `ifdef TEST_VERBOSE $display("[%0t] a2 = %0d", $time, a2); `endif end int b2 = 0; always_comb begin // verilator lint_off MULTIDRIVEN b2 = b1 << 2; // verilator lint_on MULTIDRIVEN `ifdef TEST_VERBOSE $display("[%0t] b2 = %0d", $time, b2); `endif end int c2 = 0; always_comb begin // verilator lint_off MULTIDRIVEN c2 = c1 << 3; // verilator lint_on MULTIDRIVEN `ifdef TEST_VERBOSE $display("[%0t] c2 = %0d", $time, c2); `endif end always @(posedge clk1) begin #1 if (c2 != c1 << 3) $stop; #5 if (a2 != a1 << 1) $stop; end always @(posedge clk2) #1 if (b2 != b1 << 2) $stop; initial #78 begin `ifdef TEST_VERBOSE $display("a1=%0d, b1=%0d, c1=%0d, a2=%0d, b2=%0d, c2=%0d", a1, b1, c1, a2, b2, c2); `endif if (a1 != 3) $stop; if (b1 != 4) $stop; if (c1 != a1 + b1) $stop; if (a2 != a1 << 1) $stop; if (b2 != b1 << 2) $stop; if (c2 != c1 << 3) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_trace_abort_saif.out0000644000542200017500000000076515101701376023441 0ustar mahmoudyfreeshell// Generated by verilated_saif (SAIFILE (SAIFVERSION "2.0") (DIRECTION "backward") (PROGRAM_NAME "Verilator") (DIVIDER / ) (TIMESCALE 1ps) (DURATION 75) (INSTANCE top (NET (clk (T0 40) (T1 35) (TZ 0) (TX 0) (TB 0) (TC 14)) ) (INSTANCE t (NET (clk (T0 40) (T1 35) (TZ 0) (TX 0) (TB 0) (TC 14)) (cyc\[0\] (T0 40) (T1 35) (TZ 0) (TX 0) (TB 0) (TC 7)) (cyc\[1\] (T0 40) (T1 35) (TZ 0) (TX 0) (TB 0) (TC 3)) (cyc\[2\] (T0 40) (T1 35) (TZ 0) (TX 0) (TB 0) (TC 1)) ) ) ) ) verilator-5.042/test_regress/t/t_std_randomize_no_args.v0000644000542200017500000000117615101701376024157 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by PlanV GmbH. // SPDX-License-Identifier: CC0-1.0 module t_no_args; bit [7:0] addr; bit [15:0] data; bit [7:0] old_addr; bit [15:0] old_data; int success; bit valid; initial begin old_addr = addr; old_data = data; success = std::randomize(); valid = (success == 1) && (addr == old_addr) && (data == old_data); if (!valid) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_class_mispure_bad.v0000644000542200017500000000071115101701376023256 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 virtual class Base; pure virtual function void pvfunc(); endclass class Bar extends Base; // Bad, no implementation of pvfunc endclass module t; initial begin Bar obj = new(); obj.pvfunc(); $stop; end endmodule verilator-5.042/test_regress/t/t_select_bound3.py0000755000542200017500000000073415101701376022523 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_flag_trace_threads_bad.py0000755000542200017500000000112415101701376024373 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = 't/t_EXAMPLE.v' test.lint(verilator_flags2=["--trace-threads -1"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_trace_complex_params_fst_sc.out0000644000542200017500000001134415101701376025676 0ustar mahmoudyfreeshell$date Sat Apr 5 13:56:23 2025 $end $version fstWriter $end $timescale 1ps $end $scope module top $end $attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end $attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end $scope module $unit $end $var bit 1 ! global_bit $end $upscope $end $scope module t $end $var wire 1 " clk $end $var integer 32 # cyc [31:0] $end $var bit 2 $ v_strp [1:0] $end $var bit 4 % v_strp_strp [3:0] $end $var bit 2 & v_unip_strp [1:0] $end $var bit 2 ' v_arrp [2:1] $end $var bit 4 ( v_arrp_arrp [3:0] $end $var bit 4 ) v_arrp_strp [3:0] $end $var bit 1 * v_arru[1] $end $var bit 1 + v_arru[2] $end $var bit 1 , v_arru_arru[3][1] $end $var bit 1 - v_arru_arru[3][2] $end $var bit 1 . v_arru_arru[4][1] $end $var bit 1 / v_arru_arru[4][2] $end $var bit 2 0 v_arru_arrp[3] [2:1] $end $var bit 2 1 v_arru_arrp[4] [2:1] $end $var bit 2 2 v_arru_strp[3] [1:0] $end $var bit 2 3 v_arru_strp[4] [1:0] $end $var real 64 4 v_real $end $var real 64 5 v_arr_real[0] $end $var real 64 6 v_arr_real[1] $end $var longint 64 7 v_chandle [63:0] $end $var logic 64 8 v_str32x2 [63:0] $end $attrbegin misc 07 "" 1 $end $var int 32 9 v_enumed [31:0] $end $attrbegin misc 07 "" 1 $end $var int 32 : v_enumed2 [31:0] $end $attrbegin misc 07 "" 2 $end $var logic 3 ; v_enumb [2:0] $end $var logic 6 < v_enumb2_str [5:0] $end $var logic 8 = unpacked_array[-2] [7:0] $end $var logic 8 > unpacked_array[-1] [7:0] $end $var logic 8 ? unpacked_array[0] [7:0] $end $var bit 1 @ LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end $scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end $var parameter 32 A PARAM [31:0] $end $upscope $end $scope module p2 $end $var parameter 32 B PARAM [31:0] $end $upscope $end $scope module p3 $end $var parameter 32 C PARAM [31:0] $end $upscope $end $scope module unnamedblk1 $end $var integer 32 D b [31:0] $end $scope module unnamedblk2 $end $var integer 32 E a [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b00000000000000000000000000000000 E b00000000000000000000000000000000 D b00000000000000000000000000000011 C b00000000000000000000000000000010 B b00000000000000000000000000000100 A 0@ b00000000 ? b00000000 > b00000000 = b000000 < b000 ; b00000000000000000000000000000000 : b00000000000000000000000000000000 9 b0000000000000000000000000000000000000000000000000000000011111111 8 b0000000000000000000000000000000000000000000000000000000000000000 7 r0 6 r0 5 r0 4 b00 3 b00 2 b00 1 b00 0 0/ 0. 0- 0, 0+ 0* b0000 ) b0000 ( b00 ' b00 & b0000 % b00 $ b00000000000000000000000000000000 # 0" 1! $end #10 1" b00000000000000000000000000000001 # b11 $ b1111 % b11 & b11 ' b1111 ( b1111 ) b11 0 b11 1 b11 2 b11 3 r0.1 4 r0.2 5 r0.3 6 b0000000000000000000000000000000100000000000000000000000011111110 8 b00000000000000000000000000000001 9 b00000000000000000000000000000010 : b111 ; b00000000000000000000000000000101 D b00000000000000000000000000000101 E #15 0" #20 1" b110 ; b00000000000000000000000000000100 : b00000000000000000000000000000010 9 b0000000000000000000000000000001000000000000000000000000011111101 8 r0.6 6 r0.4 5 r0.2 4 b00 3 b00 2 b00 1 b00 0 b0000 ) b0000 ( b00 ' b00 & b0000 % b00 $ b00000000000000000000000000000010 # b111111 < #25 0" #30 1" b110110 < b00000000000000000000000000000011 # b11 $ b1111 % b11 & b11 ' b1111 ( b1111 ) b11 0 b11 1 b11 2 b11 3 r0.3 4 r0.6000000000000001 5 r0.8999999999999999 6 b0000000000000000000000000000001100000000000000000000000011111100 8 b00000000000000000000000000000011 9 b00000000000000000000000000000110 : b101 ; #35 0" #40 1" b100 ; b00000000000000000000000000001000 : b00000000000000000000000000000100 9 b0000000000000000000000000000010000000000000000000000000011111011 8 r1.2 6 r0.8 5 r0.4 4 b00 3 b00 2 b00 1 b00 0 b0000 ) b0000 ( b00 ' b00 & b0000 % b00 $ b00000000000000000000000000000100 # b101101 < #45 0" #50 1" b100100 < b00000000000000000000000000000101 # b11 $ b1111 % b11 & b11 ' b1111 ( b1111 ) b11 0 b11 1 b11 2 b11 3 r0.5 4 r1 5 r1.5 6 b0000000000000000000000000000010100000000000000000000000011111010 8 b00000000000000000000000000000101 9 b00000000000000000000000000001010 : b011 ; #55 0" #60 1" b010 ; b00000000000000000000000000001100 : b00000000000000000000000000000110 9 b0000000000000000000000000000011000000000000000000000000011111001 8 r1.8 6 r1.2 5 r0.6 4 b00 3 b00 2 b00 1 b00 0 b0000 ) b0000 ( b00 ' b00 & b0000 % b00 $ b00000000000000000000000000000110 # b011011 < #64 verilator-5.042/test_regress/t/t_tri_gen.v0000644000542200017500000000143515101701376021232 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; tri z0; tri z1; updown #(0) updown0 (.z(z0)); updown #(1) updown1 (.z(z1)); always @ (posedge clk) begin if (z0 !== 0) $stop; if (z1 !== 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module updown #(parameter UP=0) (inout z); generate if (UP) begin t_up sub (.z); end else begin t_down sub (.z); end endgenerate endmodule module t_up (inout tri1 z); endmodule module t_down (inout tri0 z); endmodule verilator-5.042/test_regress/t/t_interface_dups.v0000644000542200017500000001166515101701376022604 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [4:0] din_data = crc[4:0]; wire [0:0] din_valid = crc[6]; wire [0:0] dout0_ready = crc[16]; wire [0:0] dout1_ready = crc[17]; wire [0:0] dout2_ready = crc[18]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) logic din_ready; // From test of Test.v logic [0:0] dout0_data; // From test of Test.v logic dout0_valid; // From test of Test.v logic [1:0] dout1_data; // From test of Test.v logic dout1_valid; // From test of Test.v logic [2:0] dout2_data; // From test of Test.v logic dout2_valid; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .din_ready (din_ready), .dout0_valid (dout0_valid), .dout0_data (dout0_data[0:0]), .dout1_valid (dout1_valid), .dout1_data (dout1_data[1:0]), .dout2_valid (dout2_valid), .dout2_data (dout2_data[2:0]), // Inputs .din_valid (din_valid), .din_data (din_data[4:0]), .dout0_ready (dout0_ready), .dout1_ready (dout1_ready), .dout2_ready (dout2_ready)); // Aggregate outputs into a single result vector wire [63:0] result = {48'h0, din_ready, 2'd0, dout2_valid, dout2_data, 2'd0, dout1_valid, dout1_data, 2'd0, dout0_valid, dout0_data}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc<10) begin sum <= '0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h6fd1bead9df31b07 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule interface dti #(W_DATA = 64 )(); logic [W_DATA-1:0] data; logic valid; logic ready; modport producer (output data, output valid, input ready); modport consumer (input data, input valid, output ready); endinterface : dti module Test ( output logic din_ready, input logic din_valid, input logic [4:0] din_data, input logic dout0_ready, output logic dout0_valid, output logic [0:0] dout0_data, input logic dout1_ready, output logic dout1_valid, output logic [1:0] dout1_data, input logic dout2_ready, output logic dout2_valid, output logic [2:0] dout2_data ); // Interface declarations dti #(.W_DATA(5)) din(); dti #(.W_DATA(1)) dout0(); dti #(.W_DATA(2)) dout1(); dti #(.W_DATA(3)) dout2(); // Interface wiring to top level ports assign din.valid = din_valid; assign din.data = din_data; assign din_ready = din.ready; assign dout0_valid = dout0.valid; assign dout0_data = dout0.data; assign dout0.ready = dout0_ready; assign dout1_valid = dout1.valid; assign dout1_data = dout1.data; assign dout1.ready = dout1_ready; assign dout2_valid = dout2.valid; assign dout2_data = dout2.data; assign dout2.ready = dout2_ready; assign din.ready = 0; assign dout0.data = 0; assign dout1.data = 0; assign dout2.data = 0; typedef struct packed { logic [1:0] ctrl; logic [2:0] data; } din_t; din_t din_s; assign din_s = din.data; always_comb begin dout0.valid = 0; dout1.valid = 0; dout2.valid = 0; case (din_s.ctrl) 0 : dout0.valid = din.valid; 1 : dout1.valid = din.valid; 2 : dout2.valid = din.valid; default: ; endcase end endmodule verilator-5.042/test_regress/t/t_pp_pragma_bad.v0000644000542200017500000000033615101701376022356 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `pragma verilator-5.042/test_regress/t/t_param_ceil.v0000644000542200017500000000213015101701376021670 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [31:0] O_out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .O_out (O_out[31:0])); initial begin if (O_out != 32'h4) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module Test ( output [31:0] O_out ); test #( .pFOO(5), .pBAR(2) ) U_test ( .O_out(O_out) ); endmodule module test #(parameter pFOO = 7, parameter pBAR = 3, parameter pBAZ = ceiling(pFOO, pBAR) ) ( output [31:0] O_out ); assign O_out = pBAZ; function integer ceiling; input [31:0] x, y; ceiling = ((x%y == 0) ? x/y : (x/y)+1) + 1; endfunction endmodule verilator-5.042/test_regress/t/t_time_timeunit.v0000644000542200017500000000135315101701376022456 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under The Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t; timeunit 1ns; timeprecision 1ps; initial begin `checkd($timeunit, -9); `checkd($timeunit(), -9); `checkd($timeunit(t), -9); `checkd($timeprecision, -12); `checkd($timeprecision(), -12); `checkd($timeprecision(t), -12); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_x_assign.v0000644000542200017500000000102415101701376021410 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2020 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t_x_assign( input wire clk, output reg o, output reg[31:0] o_int ); always @(posedge clk) begin if (1'bx) o <= 1'd1; else o <= 1'd0; o_int <= 'x; end endmodule verilator-5.042/test_regress/t/t_alw_split_cond.py0000755000542200017500000000071415101701376022771 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.passes() verilator-5.042/test_regress/t/t_unpacked_concat_bad3.py0000755000542200017500000000104015101701376023773 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') # Not lint, crashes in V3EmitCConstInit.h test.compile(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_bitsel_2d_slice.v0000644000542200017500000000131315101701376022624 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; localparam int WIDTH = 8; typedef logic [WIDTH-1:0] [15:0] two_dee_t; typedef logic[$clog2(WIDTH)-1:0] index_t; two_dee_t the_two_dee; initial begin the_two_dee[index_t'(5)][7:0] = 8'hab; the_two_dee[index_t'(5)][15:8] = 8'h12; end always @ (posedge clk) begin if (the_two_dee[5] != 16'h12ab) $stop(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_no_std_bad.py0000755000542200017500000000107315101701376022063 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, verilator_flags2=["--no-std", "--binary -Wall"], expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_tri_eqcase_input.v0000644000542200017500000000065115101701376023140 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; wire a = 1'bz === clk; always begin if (a) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_static_function_in_class_call_without_parentheses.py0000755000542200017500000000073415101701376032220 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_array_index_increment.py0000755000542200017500000000073415101701376024343 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_timescale_parse_bad.py0000755000542200017500000000076615101701376023745 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_concat_or.v0000644000542200017500000000451215101701376021551 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Outputs i299, // Inputs i190, i191, i192, i193, i194, i195, i196, i197, i198, i199, i200, i201, i202, i203, i204, i205, i182, i183, i184, i185, i186, i187, i188, i189, i206, i282, i284, i286, i287, i289, i290, i294, i34, i288, i31, i296, i37, i38 ); input [3:0] i190; input [3:0] i191; input [3:0] i192; input [3:0] i193; input [3:0] i194; input [3:0] i195; input [3:0] i196; input [3:0] i197; input [3:0] i198; input [3:0] i199; input [3:0] i200; input [3:0] i201; input [3:0] i202; input [3:0] i203; input [3:0] i204; input [3:0] i205; input [3:0] i182; input [3:0] i183; input [3:0] i184; input [3:0] i185; input [3:0] i186; input [3:0] i187; input [3:0] i188; input [3:0] i189; input [3:0] i206; input [3:0] i282; input [3:0] i284; input [3:0] i286; input [3:0] i287; input [3:0] i289; input [3:0] i290; input [3:0] i294; input [3:0] i34; input [3:0] i288; input [3:0] i31; input [3:0] i296; input [3:0] i37; input [3:0] i38; output [3:0] i299; assign i299 = { i296[2:0] | i31[3:1] | i282[3:1] | i284[3:1] | i34[3:1] | i286[3:1] | i287[3:1] | i37[3:1] | i38[3:1] | i288[3:1] | i289[3:1] | i290[3:1] | i182[3:1] | i183[3:1] | i184[3:1] | i185[3:1] | i186[3:1] | i187[3:1] | i188[3:1] | i189[3:1] | i190[3:1] | i191[3:1] | i192[3:1] | i193[3:1] | i194[3:1] | i195[3:1] | i196[3:1] | i197[3:1] | i198[3:1] | i199[3:1] | i200[3:1] | i201[3:1] | i202[3:1] | i203[3:1] | i204[3:1] | i205[3:1] | i206[3:1] , i294[0] | i289[0] | i290[0] | i182[0] | i183[0] | i184[0] | i185[0] | i186[0] | i187[0] | i188[0] | i189[0] | i190[0] | i191[0] | i192[0] | i193[0] | i194[0] | i195[0] | i196[0] | i197[0] | i198[0] | i199[0] | i200[0] | i201[0] | i202[0] | i203[0] | i204[0] | i205[0] | i206[0] }; endmodule verilator-5.042/test_regress/t/t_interface_star.py0000755000542200017500000000073415101701376022763 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_dpi_openfirst_c.cpp0000644000542200017500000000423415101701376023267 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2017 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "svdpi.h" #include #include #include // These require the above. Comment prevents clang-format moving them #include "TestCheck.h" //====================================================================== // clang-format off #if defined(VERILATOR) # include "Vt_dpi_openfirst__Dpi.h" #elif defined(VCS) # include "../vc_hdrs.h" #elif defined(NC) # define NEED_EXTERNS #else # error "Unknown simulator for DPI test" #endif // clang-format on #ifdef NEED_EXTERNS extern "C" { // If get ncsim: *F,NOFDPI: Function {foo} not found in default libdpi. // Then probably forgot to list a function here. extern int dpii_failure(); extern void dpii_open_i(const svOpenArrayHandle i, const svOpenArrayHandle o); } #endif //====================================================================== int errors = 0; int dpii_failure() { return errors; } //====================================================================== void dpii_open_i(const svOpenArrayHandle i, const svOpenArrayHandle o) { // Illegal in VCS: // TEST_CHECK_HEX_EQ(svLeft(i, 0), 2); // TEST_CHECK_HEX_EQ(svRight(i, 0), 0); // TEST_CHECK_HEX_EQ(svLow(i, 0), 0); // TEST_CHECK_HEX_EQ(svHigh(i, 0), 2); // TEST_CHECK_HEX_EQ(svDimensions(i), 1); TEST_CHECK_HEX_EQ(svLeft(i, 1), 2); TEST_CHECK_HEX_EQ(svRight(i, 1), 0); TEST_CHECK_HEX_EQ(svLow(i, 1), 0); TEST_CHECK_HEX_EQ(svHigh(i, 1), 2); // TEST_CHECK_HEX_EQ(svIncrement(i, 1), 0); TEST_CHECK_HEX_EQ(svSize(i, 1), 3); for (int a = 0; a < 3; ++a) { svBitVecVal vec[1]; svGetBitArrElemVecVal(vec, i, a); vec[0] = ~vec[0]; svPutBitArrElemVecVal(o, vec, a); } } verilator-5.042/test_regress/t/t_runflag_bad.v0000644000542200017500000000047115101701376022046 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_inside.v0000644000542200017500000000566515101701376021067 0ustar mahmoudyfreeshell// DESCRIPTION::Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t; typedef enum logic [1:0] { ZERO = 2'd0, ONE = 2'd1, TWO = 2'd2, THREE = 2'd3, XXX = 2'dx } num_t; function automatic logic is_odd; input en; input num_t number; case (en) 1'b1: begin unique if (number inside {ONE, THREE}) is_odd = 1'b1; else if (number inside {ZERO, TWO}) is_odd = 1'b0; else is_odd = 1'bx; end 1'b0: is_odd = 1'bx; default: is_odd = 1'bx; endcase endfunction function automatic bit is_00_to_04 (input byte value); return value inside { [ 8'h0 : 8'h04 ] }; endfunction function automatic bit is_fe_to_ff (input byte value); return value inside { [ 8'hfe : 8'hff ] }; endfunction initial begin `checkh ((4'd4 inside {4'd1,4'd5}), 1'b0); `checkh ((4'd4 inside {4'd1,4'd4}), 1'b1); // `checkh ((4'b1011 inside {4'b1001}), 1'b0); `checkh ((4'b1011 inside {4'b1xx1}), 1'b1); // Uses ==? `checkh ((4'b1001 inside {4'b1xx1}), 1'b1); // Uses ==? `checkh ((4'b1001 inside {4'b1??1}), 1'b1); `ifndef VERILATOR `checkh ((4'b1z11 inside {4'b11?1, 4'b1011}),1'bx); `endif // Range `checkh ((4'd4 inside {[4'd5:4'd3], [4'd10:4'd8]}), 1'b0); // If left of colon < never matches `checkh ((4'd3 inside {[4'd1:4'd2], [4'd3:4'd5]}), 1'b1); `checkh ((4'd4 inside {[4'd1:4'd2], [4'd3:4'd5]}), 1'b1); `checkh ((4'd5 inside {[4'd1:4'd2], [4'd3:4'd5]}), 1'b1); `checkh ((4.0 inside {[4'd1:4'd2], [4'd3:4'd5]}), 1'b1); // // Unsupported $ bound // // Unsupported if unpacked array, elements tranversed //int unpackedarray [$] = '{8,9}; //( expr inside {2, 3, unpackedarray}) // { 2,3,8,9} // `checkh (is_odd(1'b1, ZERO), 1'd0); `checkh (is_odd(1'b1, ONE), 1'd1); `checkh (is_odd(1'b1, TWO), 1'd0); `checkh (is_odd(1'b1, THREE),1'd1); `ifndef VERILATOR `checkh (is_odd(1'b1, XXX), 1'dx); `endif // // Should not give UNSIGNED/CMPCONST warnings // (Verilator converts to 8'h00 >= 8'h00 which is always true) `checkh(is_00_to_04(8'h00), 1'b1); `checkh(is_00_to_04(8'h04), 1'b1); `checkh(is_00_to_04(8'h05), 1'b0); `checkh(is_fe_to_ff(8'hfd), 1'b0); `checkh(is_fe_to_ff(8'hfe), 1'b1); `checkh(is_fe_to_ff(8'hff), 1'b1); // $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_class_unsup_bad.v0000644000542200017500000000211615101701376022745 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 virtual interface vi_t vi; virtual vi_t vi2; typedef class c; typedef interface class ic; class C #(parameter P=1); localparam LOCPAR = 10; int imember; static int istatic; local int loc; protected int prot; rand int irand; randc int icrand; rand typedef int irand_t; randc typedef int icrand_t; task classtask; endtask function int classfunc; endfunction virtual function void func_virtual; endfunction pure virtual function void func_pure_virtual; const function void func_const; endfunction extern task exttask; endclass virtual class VC; endclass module t; endmodule typedef class uvm_root; typedef class uvm_coreservice_t; class uvm_default_coreservice_t extends uvm_coreservice_t; virtual function uvm_root get_root(); uvm_root::m_forward_task_call(); return uvm_root::m_uvm_get_root(); endfunction endclass verilator-5.042/test_regress/t/t_vlt_syntax_bad.vlt0000644000542200017500000000130615101701376023161 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `verilator_config public -module "t" @(posedge clk) // only signals/functions/tasks isolate_assignments -module "t" // -match not supported tracing_off --file "*" -match "nothing" // -scope not supported lint_off --rule UNOPTFLAT -scope "top*" lint_off --rule UNOPTFLAT -scope "top*" -levels 0 lint_on --rule UNOPTFLAT -scope "top*" lint_on --rule UNOPTFLAT -scope "top*" -levels 0 // bad, --module missing forceable -module "" -var "net_*" // bad, --var missing forceable -module "top" -var "" verilator-5.042/test_regress/t/t_flag_hier0_bad.out0000644000542200017500000000116115101701376022747 0ustar mahmoudyfreeshell%Error: --hierarchical-block requires the number of entries to be even ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Module name 'param0' is duplicated in --hierarchical-block %Error: --hierarchical-block requires at least two comma-separated values %Error: --hierarchical-block must not end with \ %Error: --hierarchical-block does not allow 'a' after \ %Error: --hierarchical-block expects ',', but 'a' is passed %Error: --hierarchical-block must not end with ',' %Error: --hierarchical-block does not allow '"' in the middle of literal %Error: Exiting due to verilator-5.042/test_regress/t/t_vpi_time_cb.py0000755000542200017500000000134215101701376022246 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(make_top_shell=False, make_main=False, sim_time=2100, v_flags2=["t/t_vpi_time_cb_c.cpp"], iv_flags2=["-g2005-sv -DWAVES -DIVERILOG"], verilator_flags2=["--exe --vpi --no-l2name", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_assign_slice_overflow.v0000644000542200017500000001657515101701376024204 0ustar mahmoudyfreeshell// DESCRIPTION: Test that slice assignment overflows are handled correctly, // i.e. that if you assign to a slice such that some of the bits you assign to // do not actually exist, that those bits get correctly discarded. // Issue #2803 existed in a number number of different codepaths in // verilated.h and V3Expand.cpp. This test should cover all of these cases // when run both with and without the -Ox flag to verilator. // - Select offset constant, insert IData into CData // - Select offset constant, insert IData into SData // - Select offset constant, insert IData into IData // - Select offset constant, insert QData into QData // - Select offset constant, insert IData into WData within a word // - Select offset constant, insert IData into WData crossing a word boundary // - Select offset constant, insert IData into WData whole word insertion // - Select offset constant, insert QData into WData // - Select offset constant, insert WData into WData, several whole words // - Select offset constant, insert WData into WData, starting at word-offset // - Select offset constant, insert WData into WData, all other cases // - Select offset is non-constant, destination is wide, bit-select width == 1 // - Select offset is non-constant, destination is wide, bit-select width != 1 // - Select offset is non-constant, destination is narrow // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by David Turner. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; // Non-constant offsets reg varoffset1; reg [6:0] varoffset2; reg [6:0] varoffset3; // Destinations for variable-offset assignments reg [69:0] dstwide1; reg [69:0] dstwide2; reg [1:0] dstnarrow; // Constant offsets reg [6:0] constoffset; // Destinations for constant-offset assignments reg [2:0] dst_cdata; reg [11:0] dst_sdata; reg [29:0] dst_idata; reg [59:0] dst_qdata; reg [69:0] dst_wdata1; // assign idata within word reg [69:0] dst_wdata2; // assign idata crossing word boundary reg [69:0] dst_wdata3; // assign idata corresponding to whole word reg [69:0] dst_wdata4; // assign qdata reg [69:0] dst_wdata5; // assign wdata corresponding to several whole words reg [69:0] dst_wdata6; // assign wdata starting at word-offset reg [69:0] dst_wdata7; // assign wdata unaligned always @(*) begin // Non-constant select offset, destination narrow dstnarrow = 2'd0; dstnarrow[varoffset1 +: 2'd2] = 2'd2; // Non-constant select offset, destination wide, width == 1 dstwide1 = 70'd0; dstwide1[varoffset2 +: 1'd1] = 1'd1; // Non-constant select offset, destination wide, width != 1 dstwide2 = 70'd0; dstwide2[varoffset3 +: 2'd2] = 2'd2; // Constant offset, IData into CData constoffset = 7'd2; dst_cdata = 3'd0; dst_cdata[constoffset[0 +: 2] +: 3'd3] = 3'd6; // Constant offset, IData into SData constoffset = 7'd11; dst_sdata = 12'd0; dst_sdata[constoffset[0 +: 4] +: 2'd2] = 2'd2; // Constant offset, IData into IData constoffset = 7'd29; dst_idata = 30'd0; dst_idata[constoffset[0 +: 5] +: 2'd2] = 2'd2; // Constant offset, QData into QData constoffset = 7'd59; dst_qdata = 60'd0; dst_qdata[constoffset[0 +: 6] +: 2'd2] = 2'd2; // Constant offset, IData into WData within word constoffset = 7'd69; dst_wdata1 = 70'd0; dst_wdata1[constoffset +: 2'd2] = 2'd2; // Constant offset, IData into WData crossing word boundary constoffset = 7'd61; dst_wdata2 = 70'd0; dst_wdata2[constoffset +: 4'd10] = 10'd1 << 4'd9; // Constant offset, IData into WData replacing a whole word constoffset = 7'd64; dst_wdata3 = 70'd0; dst_wdata3[constoffset +: 6'd32] = 32'd1 << 3'd6; // Constant offset, QData into WData constoffset = 7'd31; dst_wdata4 = 70'd0; dst_wdata4[constoffset +: 7'd40] = 40'd1 << 7'd39; // Constant offset, WData into WData replacing whole words constoffset = 7'd32; dst_wdata5 = 70'd0; dst_wdata5[constoffset +: 7'd64] = 64'd1 << 7'd38; // Constant offset, WData into WData offset word aligned constoffset = 7'd32; dst_wdata6 = 70'd0; dst_wdata6[constoffset +: 7'd40] = 40'd1 << 7'd38; // Constant offset, WData into WData unaligned constoffset = 7'd1; dst_wdata7 = 70'd0; dst_wdata7[constoffset +: 7'd70] = 70'd1 << 7'd69; end // Test loop always @ (posedge clk) begin // State machine to avoid verilator constant-folding offset if (cyc == 0) begin // Initialisation varoffset1 <= 1'd0; varoffset2 <= 7'd0; varoffset3 <= 7'd0; end else if (cyc == 1) begin // Variable offsets set here to avoid verilator constant folding varoffset1 <= 1'd1; varoffset2 <= 7'd70; varoffset3 <= 7'd69; end else if (cyc == 2) begin // Check all destinations are 0 $write("dstwide1 = %23d, downshifted = %23d\n", dstwide1, dstwide1 >> 1); $write("dstwide2 = %23d, downshifted = %23d\n", dstwide2, dstwide2 >> 1); $write("dstnarrow = %23d, downshifted = %23d\n", dstnarrow, dstnarrow >> 1); $write("dst_cdata = %23d, downshifted = %23d\n", dst_cdata, dst_cdata >> 1); $write("dst_sdata = %23d, downshifted = %23d\n", dst_sdata, dst_sdata >> 1); $write("dst_idata = %23d, downshifted = %23d\n", dst_idata, dst_idata >> 1); $write("dst_qdata = %23d, downshifted = %23d\n", dst_qdata, dst_qdata >> 1); $write("dst_wdata1 = %23d, downshifted = %23d\n", dst_wdata1, dst_wdata1 >> 1); $write("dst_wdata2 = %23d, downshifted = %23d\n", dst_wdata2, dst_wdata2 >> 1); $write("dst_wdata3 = %23d, downshifted = %23d\n", dst_wdata3, dst_wdata3 >> 1); $write("dst_wdata4 = %23d, downshifted = %23d\n", dst_wdata4, dst_wdata4 >> 1); $write("dst_wdata5 = %23d, downshifted = %23d\n", dst_wdata5, dst_wdata5 >> 1); $write("dst_wdata6 = %23d, downshifted = %23d\n", dst_wdata6, dst_wdata6 >> 1); $write("dst_wdata7 = %23d, downshifted = %23d\n", dst_wdata7, dst_wdata7 >> 1); if (dstwide1 !== 70'd0 || (dstwide1 >> 1) !== 70'd0) $stop; if (dstwide2 !== 70'd0 || (dstwide2 >> 1) !== 70'd0) $stop; if (dstnarrow !== 2'd0 || (dstnarrow >> 1) !== 2'd0) $stop; if (dst_cdata !== 3'd0 || (dst_cdata >> 1) !== 3'd0) $stop; if (dst_sdata !== 12'd0 || (dst_sdata >> 1) !== 12'd0) $stop; if (dst_idata !== 30'd0 || (dst_idata >> 1) !== 30'd0) $stop; if (dst_qdata !== 60'd0 || (dst_qdata >> 1) !== 60'd0) $stop; if (dst_wdata1 !== 70'd0 || (dst_wdata1 >> 1) !== 70'd0) $stop; if (dst_wdata2 !== 70'd0 || (dst_wdata2 >> 1) !== 70'd0) $stop; if (dst_wdata3 !== 70'd0 || (dst_wdata3 >> 1) !== 70'd0) $stop; if (dst_wdata4 !== 70'd0 || (dst_wdata4 >> 1) !== 70'd0) $stop; if (dst_wdata5 !== 70'd0 || (dst_wdata5 >> 1) !== 70'd0) $stop; if (dst_wdata6 !== 70'd0 || (dst_wdata6 >> 1) !== 70'd0) $stop; if (dst_wdata7 !== 70'd0 || (dst_wdata7 >> 1) !== 70'd0) $stop; end else begin $write("*-* All Finished *-*\n"); $finish; end cyc <= cyc + 1; end endmodule verilator-5.042/test_regress/t/t_lint_declfilename_bad.py0000755000542200017500000000111115101701376024224 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_lint_declfilename.v" test.lint(verilator_flags2=["--lint-only -Wall"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_param_mintypmax.v0000644000542200017500000000141615101701376023010 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; parameter MTM = (1:2:3); sub sub (); //UNSUP sub #(.MTM(10:20:30)) sub20name (); //UNSUP sub #(.MTM(100:200)) sub200name (); //UNSUP sub #(10:20:30) sub20pos (); //UNSUP sub #(100:200) sub200pos (); initial begin if (MTM != 2) $stop; //UNSUP if (sub20pos.MTM != 20) $stop; //UNSUP if (sub200pos.MTM != 200) $stop; //UNSUP if (sub20name.MTM != 20) $stop; //UNSUP if (sub200name.MTM != 200) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module sub #(parameter MTM = (1:2:3)) (); endmodule verilator-5.042/test_regress/t/t_lint_blkseq_noedge.v0000644000542200017500000000070415101701376023431 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( lhs, o ); input wire [7:0] lhs; output reg [7:0] o; wire [7:0] shifted; always @(shifted or lhs) begin if (lhs[7]) o = shifted ^ 8'h1b; else o = shifted; end assign shifted = lhs << 1; endmodule verilator-5.042/test_regress/t/t_dpi_shortcircuit2.py0000755000542200017500000000105315101701376023425 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=["t/t_dpi_shortcircuit_c.cpp"], verilator_flags2=["-Wno-DECLFILENAME"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_disable_func_bad.v0000644000542200017500000000062615101701376023030 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 int x = 0; function int increment_x; x++; return x; endfunction module t; initial begin fork increment_x(); #1 disable increment_x; join end endmodule verilator-5.042/test_regress/t/t_sc_vl_assign_sbw.py0000755000542200017500000000114115101701376023310 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe --pins-sc-biguint --sc", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_param_array.py0000755000542200017500000000073415101701376022270 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_sys_file_eof.py0000755000542200017500000000073415101701376022440 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_opt_table_real.py0000755000542200017500000000130215101701376022736 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--stats"]) if test.vlt_all: test.file_grep(test.stats, r'Optimizations, Tables created\s+(\d+)', 1) test.file_grep(test.stats, r'ConstPool, Tables emitted\s+(\d+)', 1) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_class.py0000755000542200017500000000073415101701376022264 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_mispure_bad.py0000755000542200017500000000076615101701376023456 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_assert_synth_parallel.out0000644000542200017500000000062015101701376024542 0ustar mahmoudyfreeshell[0] -Info: t_assert_synth.v:115: top.t.test_info: Start of $info test [0] -Info: t_assert_synth.v:116: top.t.test_info: Middle of $info test [0] -Info: t_assert_synth.v:117: top.t.test_info: End of $info test [40] %Error: t_assert_synth.v:50: Assertion failed in top.t: synthesis full_case parallel_case, but multiple matches found for '1'h1' %Error: t/t_assert_synth.v:50: Verilog $stop Aborting... verilator-5.042/test_regress/t/t_queue_back.py0000755000542200017500000000073415101701376022076 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_assoc_nokey_bad.py0000755000542200017500000000076615101701376023122 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_clk_inp_init.v0000644000542200017500000000426615101701376022252 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Check initialisation of cloned clock variables // // This tests issue #1327 (Strange initialization behavior with // "VinpClk" cloned clock variables) // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2018 by Rupert Swarbrick (Argon Design). // SPDX-License-Identifier: CC0-1.0 // bug1327 // This models some device under test with an asynchronous reset pin // which counts to 15. module dut (input wire clk, input wire rst_n, output wire done); reg [3:0] counter; always @(posedge clk or negedge rst_n) begin if (rst_n & ! clk) begin $display("[%0t] %%Error: Oh dear! 'always @(posedge clk or negedge rst_n)' block triggered with clk=%0d, rst_n=%0d.", $time, clk, rst_n); $stop; end if (! rst_n) begin counter <= 4'd0; end else begin counter <= counter < 4'd15 ? counter + 4'd1 : counter; end end assign done = rst_n & (counter == 4'd15); endmodule module t(input wire clk, input wire rst_n); wire dut_done; // A small FSM for driving the test // // This is just designed to be enough to force Verilator to make a // "VinpClk" variant of dut_rst_n. // Possible states: // // 0: Device in reset // 1: Device running // 2: Device finished reg [1:0] state; always @(posedge clk or negedge rst_n) begin if (! rst_n) begin state <= 0; end else begin if (state == 2'd0) begin // One clock after resetting the device, we switch to running // it. state <= 2'd1; end else if (state == 2'd1) begin // If the device is running, we switch to finished when its // done signal goes high. state <= dut_done ? 2'd2 : 2'd1; end else begin // If the dut has finished, the test is done. $write("*-* All Finished *-*\n"); $finish; end end end wire dut_rst_n = rst_n & (state != 0); wire done; dut dut_i (.clk (clk), .rst_n (dut_rst_n), .done (dut_done)); endmodule verilator-5.042/test_regress/t/t_disable_outside.v0000644000542200017500000000111015101701376022730 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t; initial begin begin : blk int x = 0; fork : fork_blk begin x = 1; #2; x = 2; end join_none #1; disable fork_blk; #2; if (x != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_genfor_signed.v0000644000542200017500000000253615101701376022417 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Use this file as a template for submitting bugs, etc. // This module takes a single clock input, and should either // $write("*-* All Finished *-*\n"); // $finish; // on success, or $stop. // // The code as shown applies a random vector to the Test // module, then calculates a CRC on the Test module's outputs. // // **If you do not wish for your code to be released to the public // please note it here, otherwise:** // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by ____YOUR_NAME_HERE____. // SPDX-License-Identifier: CC0-1.0 module t # ( parameter PIPE = 4 )(/*AUTOARG*/ // Inputs clk ); input clk; // These are ok sub #( .P_STOP (1) ) u_sub1 (); sub #( .P_STOP (0) ) u_sub0 (); genvar i; for (i = -1; i < 1; i++) begin: SUB_PIPE sub #( .P_STOP (i) ) u_sub (); end always @ (posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule module sub # ( parameter P_START = 1, parameter P_STOP = 0 )( ); initial begin for (int i = P_START; i >= P_STOP; --i) begin $display("%m %0d..%0d i=%0d", P_START, P_STOP, i); end end endmodule verilator-5.042/test_regress/t/t_assoc_method_map.out0000644000542200017500000000060315101701376023446 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_assoc_method_map.v:17:15: Unsupported: Associative array 'map' method (IEEE 1800-2023 7.12.5) : ... note: In instance 't' 17 | res = a.map(el) with (el == 2); | ^~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_const_number_unsized.py0000755000542200017500000000073715101701376024234 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_assert_procedural_clk_bad.v0000644000542200017500000000131015101701376024753 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; wire [7:0] cyc_copy = cyc[7:0]; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==9) begin assume property (@(posedge clk) cyc == 9); assume property (@(negedge clk) cyc == 9); end if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.042/test_regress/t/t_case_enum_incomplete_bad.v0000644000542200017500000000062315101701376024565 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: SystemVerilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; enum logic [2:0] {S0, S1, S2} state; initial begin state = S1; unique case (state) S0: $stop; S2: $stop; endcase end endmodule verilator-5.042/test_regress/t/t_typedef.py0000755000542200017500000000073415101701376021432 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_multitop1.v0000644000542200017500000000066115101701376021541 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; t_multitop1s s (); initial $display("In '%m'"); always @(posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_dpi_open_query.v0000644000542200017500000002351115101701376022624 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2020 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `define stop $stop `define check(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) `define unless(cond,gotv,expv) do if (!(cond)) `check(gotv, expv); while(0) `ifdef VERILATOR `define NO_DYNAMIC `define NO_QUEUE `endif `ifdef VCS `define NO_QUEUE `endif `ifdef NC `define NO_DYNAMIC `define NO_QUEUE `endif `ifdef NC `define ONNC 1 `else `define ONNC 0 `endif `ifdef MS `define ONMS 1 `else `define ONMS 0 `endif module t; // 1 open dimension import "DPI-C" function int cSvLeft1( input bit h [], int d); import "DPI-C" function int cSvRight1( input bit h [], int d); import "DPI-C" function int cSvLow1( input bit h [], int d); import "DPI-C" function int cSvHigh1( input bit h [], int d); import "DPI-C" function int cSvIncrement1( input bit h [], int d); import "DPI-C" function int cSvSize1( input bit h [], int d); import "DPI-C" function int cSvDimensions1( input bit h []); // 2 open dimensions import "DPI-C" function int cSvLeft2( input bit h [][], int d); import "DPI-C" function int cSvRight2( input bit h [][], int d); import "DPI-C" function int cSvLow2( input bit h [][], int d); import "DPI-C" function int cSvHigh2( input bit h [][], int d); import "DPI-C" function int cSvIncrement2( input bit h [][], int d); import "DPI-C" function int cSvSize2( input bit h [][], int d); import "DPI-C" function int cSvDimensions2( input bit h [][]); // 3 open dimensions import "DPI-C" function int cSvLeft3( input bit h [][][], int d); import "DPI-C" function int cSvRight3( input bit h [][][], int d); import "DPI-C" function int cSvLow3( input bit h [][][], int d); import "DPI-C" function int cSvHigh3( input bit h [][][], int d); import "DPI-C" function int cSvIncrement3( input bit h [][][], int d); import "DPI-C" function int cSvSize3( input bit h [][][], int d); import "DPI-C" function int cSvDimensions3( input bit h [][][]); // 4 open dimensions import "DPI-C" function int cSvLeft4( input bit h [][][][], int d); import "DPI-C" function int cSvRight4( input bit h [][][][], int d); import "DPI-C" function int cSvLow4( input bit h [][][][], int d); import "DPI-C" function int cSvHigh4( input bit h [][][][], int d); import "DPI-C" function int cSvIncrement4( input bit h [][][][], int d); import "DPI-C" function int cSvSize4( input bit h [][][][], int d); import "DPI-C" function int cSvDimensions4( input bit h [][][][]); // verilator lint_off UNDRIVEN bit a1 [1:0]; bit a2 [1:0][2:0]; bit a3 [1:0][2:0][3:0]; bit a4 [1:0][2:0][3:0][4:0]; bit b1 [0:1]; bit b2 [0:1][0:2]; bit b3 [0:1][0:2][0:3]; bit b4 [0:1][0:2][0:3][0:4]; bit c1 [-1:1]; bit c2 [-1:1][-2:2]; bit c3 [-1:1][-2:2][-3:3]; bit c4 [-1:1][-2:2][-3:3][-4:4]; `ifndef NO_DYNAMIC bit d1 []; bit d2 [][-2:2]; bit d3 [][-2:2][-3:3]; bit d4 [][-2:2][-3:3][-4:4]; `endif `ifndef NO_QUEUE bit e1 [$]; `endif // verilator lint_on UNDRIVEN initial begin `ifndef NO_DYNAMIC d1 = new[3]; d2 = new[3]; d3 = new[3]; d4 = new[3]; `endif `ifndef NO_QUEUE e1.push_back(0); e1.push_back(0); e1.push_back(0); `endif // 1 open dimension `check(cSvDimensions1(a1), 1); `check(cSvDimensions1(b1), 1); `check(cSvDimensions1(c1), 1); `ifndef NO_DYNAMIC `check(cSvDimensions1(d1), 1); `endif `ifndef NO_QUEUE `check(cSvDimensions1(e1), 1); `endif for (int d = 0 ; d < 2 ; d++) begin if (`ONNC && d == 0) continue; `check(cSvLeft1(a1, d), d); `check(cSvRight1(a1, d), 0); `check(cSvLow1(a1, d), 0); `check(cSvHigh1(a1, d), d); `unless(`ONMS && d == 0, cSvIncrement1(a1, d), 1); `check(cSvSize1(a1, d), d+1); `check(cSvLeft1(b1, d), 0); `check(cSvRight1(b1, d), d); `check(cSvLow1(b1, d), 0); `check(cSvHigh1(b1, d), d); `ifndef NC `unless(`ONMS && d == 0, cSvIncrement1(b1, d), d == 0 ? 1 : -1); `endif `check(cSvSize1(b1, d), d+1); `check(cSvLeft1(c1, d), -d); `check(cSvRight1(c1, d), d); `check(cSvLow1(c1, d), -d); `check(cSvHigh1(c1, d), d); `ifndef NC `unless(`ONMS && d == 0, cSvIncrement1(c1, d), d == 0 ? 1 : -1); `endif `check(cSvSize1(c1, d), 2*d+1); `ifndef NO_DYNAMIC `check(cSvLeft1(d1, d), d == 1 ? 0 : -d); `check(cSvRight1(d1, d), d == 1 ? 2 : d); `check(cSvLow1(d1, d), d == 1 ? 0 : -d); `check(cSvHigh1(d1, d), d == 1 ? 2 : d); `unless(`ONMS && d == 0, cSvIncrement1(d1, d), d == 0 ? 1 : -1); `check(cSvSize1(d1, d), 2*d+1); `endif `ifndef NO_QUEUE `check(cSvLeft1(e1, d), d == 1 ? 0 : -d); `check(cSvRight1(e1, d), d == 1 ? 2 : d); `check(cSvLow1(e1, d), d == 1 ? 0 : -d); `check(cSvHigh1(e1, d), d == 1 ? 2 : d); `unless(`ONMS && d == 0, cSvIncrement1(e1, d), d == 0 ? 1 : -1); `check(cSvSize1(e1, d), 2*d+1); `endif end // 2 open dimensions `check(cSvDimensions2(a2), 2); `check(cSvDimensions2(b2), 2); `check(cSvDimensions2(c2), 2); `ifndef NO_DYNAMIC `check(cSvDimensions2(d2), 2); `endif for (int d = 0 ; d < 3 ; d++) begin if (`ONNC && d == 0) continue; `check(cSvLeft2(a2, d), d); `check(cSvRight2(a2, d), 0); `check(cSvLow2(a2, d), 0); `check(cSvHigh2(a2, d), d); `unless(`ONMS && d == 0, cSvIncrement2(a2, d), 1); `check(cSvSize2(a2, d), d+1); `check(cSvLeft2(b2, d), 0); `check(cSvRight2(b2, d), d); `check(cSvLow2(b2, d), 0); `check(cSvHigh2(b2, d), d); `ifndef NC `unless(`ONMS && d == 0, cSvIncrement2(b2, d), d == 0 ? 1 : -1); `endif `check(cSvSize2(b2, d), d+1); `check(cSvLeft2(c2, d), -d); `check(cSvRight2(c2, d), d); `check(cSvLow2(c2, d), -d); `check(cSvHigh2(c2, d), d); `ifndef NC `unless(`ONMS && d == 0, cSvIncrement2(c2, d), d == 0 ? 1 : -1); `endif `check(cSvSize2(c2, d), 2*d+1); `ifndef NO_DYNAMIC `check(cSvLeft2(d2, d), d == 1 ? 0 : -d); `check(cSvRight2(d2, d), d == 1 ? 2 : d); `check(cSvLow2(d2, d), d == 1 ? 0 : -d); `check(cSvHigh2(d2, d), d == 1 ? 2 : d); `unless(`ONMS && d == 0, cSvIncrement2(d2, d), d == 0 ? 1 : -1); `check(cSvSize2(d2, d), 2*d+1); `endif end // 3 open dimensions `check(cSvDimensions3(a3), 3); `check(cSvDimensions3(b3), 3); `check(cSvDimensions3(c3), 3); `ifndef NO_DYNAMIC `check(cSvDimensions3(d3), 3); `endif for (int d = 0 ; d < 4 ; d++) begin if (`ONNC && d == 0) continue; `check(cSvLeft3(a3, d), d); `check(cSvRight3(a3, d), 0); `check(cSvLow3(a3, d), 0); `check(cSvHigh3(a3, d), d); `unless(`ONMS && d == 0, cSvIncrement3(a3, d), 1); `check(cSvSize3(a3, d), d+1); `check(cSvLeft3(b3, d), 0); `check(cSvRight3(b3, d), d); `check(cSvLow3(b3, d), 0); `check(cSvHigh3(b3, d), d); `ifndef NC `unless(`ONMS && d == 0, cSvIncrement3(b3, d), d == 0 ? 1 : -1); `endif `check(cSvSize3(b3, d), d+1); `check(cSvLeft3(c3, d), -d); `check(cSvRight3(c3, d), d); `check(cSvLow3(c3, d), -d); `check(cSvHigh3(c3, d), d); `ifndef NC `unless(`ONMS && d == 0, cSvIncrement3(c3, d), d == 0 ? 1 : -1); `endif `check(cSvSize3(c3, d), 2*d+1); `ifndef NO_DYNAMIC `check(cSvLeft3(d3, d), d == 1 ? 0 : -d); `check(cSvRight3(d3, d), d == 1 ? 2 : d); `check(cSvLow3(d3, d), d == 1 ? 0 : -d); `check(cSvHigh3(d3, d), d == 1 ? 2 : d); `unless(`ONMS && d == 0, cSvIncrement3(d3, d), d == 0 ? 1 : -1); `check(cSvSize3(d3, d), 2*d+1); `endif end // 4 open dimension `check(cSvDimensions4(a4), 4); `check(cSvDimensions4(b4), 4); `check(cSvDimensions4(c4), 4); `ifndef NO_DYNAMIC `check(cSvDimensions4(d4), 4); `endif for (int d = 0 ; d < 5 ; d++) begin if (`ONNC && d == 0) continue; `check(cSvLeft4(a4, d), d); `check(cSvRight4(a4, d), 0); `check(cSvLow4(a4, d), 0); `check(cSvHigh4(a4, d), d); `unless(`ONMS && d == 0, cSvIncrement4(a4, d), 1); `check(cSvSize4(a4, d), d+1); `check(cSvLeft4(b4, d), 0); `check(cSvRight4(b4, d), d); `check(cSvLow4(b4, d), 0); `check(cSvHigh4(b4, d), d); `ifndef NC `unless(`ONMS && d == 0, cSvIncrement4(b4, d), d == 0 ? 1 : -1); `endif `check(cSvSize4(b4, d), d+1); `check(cSvLeft4(c4, d), -d); `check(cSvRight4(c4, d), d); `check(cSvLow4(c4, d), -d); `check(cSvHigh4(c4, d), d); `ifndef NC `unless(`ONMS && d == 0, cSvIncrement4(c4, d), d == 0 ? 1 : -1); `endif `check(cSvSize4(c4, d), 2*d+1); `ifndef NO_DYNAMIC `check(cSvLeft4(d4, d), d == 1 ? 0 : -d); `check(cSvRight4(d4, d), d == 1 ? 2 : d); `check(cSvLow4(d4, d), d == 1 ? 0 : -d); `check(cSvHigh4(d4, d), d == 1 ? 2 : d); `unless(`ONMS && d == 0, cSvIncrement4(d4, d), d == 0 ? 1 : -1); `check(cSvSize4(d4, d), 2*d+1); `endif end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_alw_splitord.py0000755000542200017500000000112415101701376022467 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--stats"]) if test.vlt_all: test.file_grep(test.stats, r'Optimizations, Split always\s+(\d+)', 5) test.execute() test.passes() verilator-5.042/test_regress/t/t_param_type_fwd.py0000755000542200017500000000070315101701376022767 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint() test.passes() verilator-5.042/test_regress/t/t_flag_timescale_override2.out0000644000542200017500000000011715101701376025061 0ustar mahmoudyfreeshellTime scale of t is 1s / 1us Time scale of sub is 1s / 1us *-* All Finished *-* verilator-5.042/test_regress/t/t_assigndly_dynamic_nofork.py0000755000542200017500000000134315101701376025046 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_assigndly_task.v" test.compile(verilator_flags2=["--timing"]) for filename in (test.glob_some(test.obj_dir + "/" + test.vm_prefix + "*.h") + test.glob_some(test.obj_dir + "/" + test.vm_prefix + "*.cpp")): test.file_grep_not(filename, r'__Vfork_') test.passes() verilator-5.042/test_regress/t/t_array_type_methods.py0000755000542200017500000000073415101701376023674 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_constraint_before_randc_bad.py0000755000542200017500000000077615101701376025463 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_gen_div0.py0000755000542200017500000000073415101701376021465 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_alias_hier_ref_bad.out0000644000542200017500000000054415101701376023707 0ustar mahmoudyfreeshell%Error: t/t_alias_hier_ref_bad.v:18:19: Hierarchical reference used for net alias (IEEE 1800-2023 10.11) : ... note: In instance 't' 18 | alias a = sub_i.btw; | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_vpi_public_depth.cpp0000644000542200017500000001421115101701376023434 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2010-2023 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #ifdef IS_VPI #include "vpi_user.h" #include #else #include "verilated.h" #include "verilated_vcd_c.h" #include "verilated_vpi.h" #include VM_PREFIX_INCLUDE #ifdef T_VPI_PUBLIC_DEPTH #include "Vt_vpi_public_depth__Dpi.h" #elif defined(T_VPI_PUBLIC_DEPTH_OFF) #include "Vt_vpi_public_depth_off__Dpi.h" #elif defined(T_VPI_PUBLIC_OFF) #include "Vt_vpi_public_off__Dpi.h" #else #error "Bad test" #endif #include "svdpi.h" #endif #include #include #include extern "C" { #include } // These require the above. Comment prevents clang-format moving them #include "TestSimulator.h" #include "TestVpi.h" void modDump(const TestVpiHandle& it, int n) { while (TestVpiHandle hndl = vpi_scan(it)) { const char* nm = vpi_get_str(vpiName, hndl); for (int i = 0; i < n; i++) printf(" "); printf("%s\n", nm); TestVpiHandle subIt = vpi_iterate(vpiModule, hndl); if (subIt) modDump(subIt, n + 1); } } extern "C" { int mon_check() { #ifdef TEST_VERBOSE printf("-mon_check()\n"); #endif TestVpiHandle it = vpi_iterate(vpiModule, NULL); CHECK_RESULT_NZ(it); // Uncomment to see what other simulators return // modDump(it, 0); // return 1; TestVpiHandle topmod; // both somepackage and t exist at the top level while ((topmod = vpi_scan(it))) { if (vpi_get(vpiType, topmod) == vpiModule) break; } CHECK_RESULT_NZ(topmod); const char* t_name = vpi_get_str(vpiName, topmod); CHECK_RESULT_NZ(t_name); // Icarus reports the top most module as "top" if (std::strcmp(t_name, "top") == 0) { it = vpi_iterate(vpiModule, topmod); CHECK_RESULT_NZ(it); CHECK_RESULT(vpi_get(vpiType, it), vpiModule); topmod = vpi_scan(it); t_name = vpi_get_str(vpiName, topmod); CHECK_RESULT_NZ(t_name); } CHECK_RESULT_CSTR(t_name, "t"); TestVpiHandle topmod_done_should_be_0 = (vpi_scan(it)); it.freed(); // IEEE 37.2.2 vpi_scan at end does a vpi_release_handle CHECK_RESULT_Z(topmod_done_should_be_0); TestVpiHandle mod_a = vpi_handle_by_name(const_cast("\\mod.a "), topmod); #if defined(T_VPI_PUBLIC_OFF) // metacomment from module A should be ignored CHECK_RESULT_Z(mod_a); return 0; #endif CHECK_RESULT_NZ(mod_a); TestVpiHandle it2 = vpi_iterate(vpiModule, topmod); CHECK_RESULT_NZ(it2); TestVpiHandle mod2 = vpi_scan(it2); CHECK_RESULT_NZ(mod2); const char* mod_a_name = vpi_get_str(vpiName, mod2); CHECK_RESULT_CSTR(mod_a_name, "\\mod.a "); TestVpiHandle it3 = vpi_iterate(vpiModule, mod2); #ifdef T_VPI_PUBLIC_DEPTH CHECK_RESULT_NZ(it3); TestVpiHandle mod3 = vpi_scan(it3); CHECK_RESULT_NZ(mod3); const char* mod_c_name = vpi_get_str(vpiName, mod3); if (std::strcmp(mod_c_name, "\\mod_b$ ") == 0) { // Full visibility in other simulators, skip mod_b TestVpiHandle mod4 = vpi_scan(it3); CHECK_RESULT_NZ(mod4); mod_c_name = vpi_get_str(vpiName, mod4); } CHECK_RESULT_CSTR(mod_c_name, "\\mod\\c$ "); #elif defined(T_VPI_PUBLIC_DEPTH_OFF) CHECK_RESULT_Z(it3); #endif return 0; // Ok } } //====================================================================== #ifdef IS_VPI static int mon_check_vpi() { TestVpiHandle href = vpi_handle(vpiSysTfCall, 0); s_vpi_value vpi_value; vpi_value.format = vpiIntVal; vpi_value.value.integer = mon_check(); vpi_put_value(href, &vpi_value, NULL, vpiNoDelay); return 0; } static s_vpi_systf_data vpi_systf_data[] = {{vpiSysFunc, vpiIntFunc, (PLI_BYTE8*)"$mon_check", (PLI_INT32(*)(PLI_BYTE8*))mon_check_vpi, 0, 0, 0}, 0}; // cver entry void vpi_compat_bootstrap(void) { p_vpi_systf_data systf_data_p; systf_data_p = &(vpi_systf_data[0]); while (systf_data_p->type != 0) vpi_register_systf(systf_data_p++); } // icarus entry void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0}; #else int main(int argc, char** argv) { const std::unique_ptr contextp{new VerilatedContext}; uint64_t sim_time = 1100; contextp->debug(0); contextp->commandArgs(argc, argv); // We're going to be checking for these errors so don't crash out contextp->fatalOnVpiError(0); { // Construct and destroy const std::unique_ptr topp{ new VM_PREFIX{contextp.get(), // Note null name - we're flattening it out ""}}; } // Test second construction const std::unique_ptr topp{new VM_PREFIX{contextp.get(), // Note null name - we're flattening it out ""}}; #ifdef VERILATOR #ifdef TEST_VERBOSE contextp->scopesDump(); #endif #endif #if VM_TRACE contextp->traceEverOn(true); VL_PRINTF("Enabling waves...\n"); VerilatedVcdC* tfp = new VerilatedVcdC; topp->trace(tfp, 99); tfp->open(STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); #endif topp->eval(); topp->clk = 0; contextp->timeInc(10); while (contextp->time() < sim_time && !contextp->gotFinish()) { contextp->timeInc(1); topp->eval(); VerilatedVpi::callValueCbs(); topp->clk = !topp->clk; // mon_do(); #if VM_TRACE if (tfp) tfp->dump(contextp->time()); #endif } if (!contextp->gotFinish()) { vl_fatal(FILENM, __LINE__, "main", "%Error: Timeout; never got a $finish"); } topp->final(); #if VM_TRACE if (tfp) tfp->close(); #endif return 0; } #endif verilator-5.042/test_regress/t/t_public_seq.cpp0000644000542200017500000000230415101701376022242 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 // Generated header #include "Vt_public_seq.h" #include "Vt_public_seq___024root.h" // General headers #include "verilated.h" std::unique_ptr topp; int main(int argc, char** argv) { vluint64_t sim_time = 1100; const std::unique_ptr contextp{new VerilatedContext}; contextp->debug(0); contextp->commandArgs(argc, argv); srand48(5); topp.reset(new VM_PREFIX{"top"}); topp->clk = 0; topp->eval(); { contextp->timeInc(10); } int cyc = 0; while ((contextp->time() < sim_time) && !contextp->gotFinish()) { if (cyc >= 5) ++topp->rootp->t__DOT__pub_byte; topp->eval(); topp->clk = !topp->clk; topp->eval(); contextp->timeInc(5); if (topp->clk) cyc++; } if (!contextp->gotFinish()) { vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); } topp->final(); topp.reset(); return 0; } verilator-5.042/test_regress/t/t_math_imm.py0000755000542200017500000000106515101701376021563 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile( # We have deep expressions we want to test) verilator_flags2=["--compiler msvc"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_udp_delay.py0000755000542200017500000000071115101701376021733 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.compile() test.passes() verilator-5.042/test_regress/t/t_lint_pragma_protected_bad.v0000644000542200017500000000723515101701376024763 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t_lint_pragma_protected_err; // This part should see some failures `pragma protect begin_protected `pragma protect version="xx" // should fail because value should be quoted `pragma protect encrypt_agent=123 // should fail because no value given at all `pragma protect encrypt_agent_info `pragma protect data_method="AES128-CBC" `pragma protect key_keyowner="BIG3#1" `pragma protect key_keyname="AAAAAA" `pragma protect key_method="RSA" // expect error in key_block below, 64 bytes but expecting 65 // also expect "multiple `pragma encoding sections` error because number of // bytes does not go down to 0 in the end of the section below due to the 64->65 change `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 65) `pragma protect key_block ICAgICAgICAgICAgICAgICAgIEdOVSBMRVNTRVIgR0VORVJBTCBQVUJMSUMgTElDRU5TRQogICAg KSAyMDA3IE== `pragma protect key_keyowner="BIG3#2" `pragma protect key_keyname="BBBBBB" `pragma protect key_method="RSA" `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `pragma protect key_block IEV2ZXJ5b25lIGlzIHBlcm1pdHRlZCB0byBjb3B5IGFuZCBkaXN0cmlidXRlIHZlcmJhdGltIGNv cGllcwogb2YgdGhpcyBsaWNlbnNlIGRvY3VtZW50LCBidXQgY2hhbmdpbmcgaXQgaXMgbm90IGFs bG93ZWQuCgoKICBUaGl= `pragma protect key_keyowner="BIG3#3" `pragma protect key_keyname="CCCCCCCC" `pragma protect key_method="RSA" `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `pragma protect key_block TGljZW5zZSBpbmNvcnBvcmF0ZXMKdGhlIHRlcm1zIGFuZCBjb25kaXRpb25zIG9mIHZlcnNpb24g MyBvZiB0aGUgR05VIEdlbmVyYWwgUHVibGljCkxpY2Vuc2UsIHN1cHBsZW1lbnRlZCBieSB0aGUg YWRkaXRpb25hbCBwZXJ= `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 295) `pragma protect data_block aW5pdGlvbnMuCgogIEFzIHVzZWQgaGVyZWluLCAidGhpcyBMaWNlbnNlIiByZWZlcnMgdG8gdmVy c2lvbiAzIG9mIHRoZSBHTlUgTGVzc2VyCkdlbmVyYWwgUHVibGljIExpY2Vuc2UsIGFuZCB0aGUg IkdOVSBHUEwiIHJlZmVycyB0byB2ZXJzaW9uIDMgb2YgdGhlIEdOVQpHZW5lcmFsIFB1YmxpYyBM aWNlbnNlLgoKICAiVGhlIExpYnJhcnkiIHJlZmVycyB0byBhIGNvdmVyZWQgd29yayBnb3Zlcm5l ZCBieSB0aGlzIExpY2Vuc2UsCm90aGVyIHRoYW4gYW4gQXBwbGljYXRpb24gb3IgYSBDb21iaW5l ZCBXb3JrIGFzIG== `pragma protect encoding = (enctype = "A-bad-not-BASE64", line_length = 1, bytes = 295) `pragma protect data_block aW5pdGlvbnMuCgogIEFzIHVzZWQgaGVyZWluLCAidGhpcyBMaWNlbnNlIiByZWZlcnMgdG8gdmVy c2lvbiAzIG9mIHRoZSBHTlUgTGVzc2VyCkdlbmVyYWwgUHVibGljIExpY2Vuc2UsIGFuZCB0aGUg IkdOVSBHUEwiIHJlZmVycyB0byB2ZXJzaW9uIDMgb2YgdGhlIEdOVQpHZW5lcmFsIFB1YmxpYyBM aWNlbnNlLgoKICAiVGhlIExpYnJhcnkiIHJlZmVycyB0byBhIGNvdmVyZWQgd29yayBnb3Zlcm5l ZCBieSB0aGlzIExpY2Vuc2UsCm90aGVyIHRoYW4gYW4gQXBwbGljYXRpb24gb3IgYSBDb21iaW5l ZCBXb3JrIGFzIG== `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 76) `pragma protect data_block aW5pdGlvbnMuCgogIEFzIHVzZWQgaGVyZWluLCAidGhpcyBMaWNlbnNlIiByZWZlcnMgdG8gdmVyTOOLONG `pragma protect encoding = (enctype = "BASE64", line_length = 1, bytes = 4) `pragma protect data_block aW5p `pragma protect encoding = (enctype = "UUENCODE", line_length = 1, bytes = 4) `pragma protect data_block aW5p `pragma protect encoding = (enctype = "QUOTED-PRINTABLE", line_length = 1, bytes = 4) `pragma protect data_block aW5p `pragma protect encoding = (enctype = "RAW", line_length = 1, bytes = 4) `pragma protect data_block aW5p `pragma protect end_protected // Should trigger unknown pragma warning, although in principle unknown pragmas should be safely ignored. `pragma XXXXX // Should trigger missing pragma warning `pragma endmodule verilator-5.042/test_regress/t/t_nettype.py0000755000542200017500000000076615101701376021467 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_wait.v0000644000542200017500000000132515101701376020545 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; int value; initial begin wait (value == 1); if (value != 1) $stop; wait (0); if (value != 1) $stop; // wait (value == 2); if (value != 2) $stop; // wait (value == 3) if (value != 3) $stop; if (value != 3) $stop; end initial begin #10; value = 1; #10; value = 2; #10; value = 3; #10; value = 4; #10; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_interface_dearray_bad.v0000644000542200017500000000124615101701376024060 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface A; endinterface typedef virtual A a_t; typedef a_t a_array_t[6]; class C; a_array_t vif; endclass module tb_top(); A a[6](), b[7](), f[6](); C c, d, e; a_array_t g; initial begin a = f; c = new(); c.vif = b; d = new(); for (int i = 0; i < 6; ++i) begin d.vif[i] = a[i]; end e = new(); e.vif = b[0:5]; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_flag_threads_bad.py0000755000542200017500000000127415101701376023223 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = 't/t_EXAMPLE.v' test.run(cmd=["perl", os.environ["VERILATOR_ROOT"] + "/bin/verilator", "--threads -1"], logfile=test.run_log_filename, fails=True, expect_filename=test.golden_filename, verilator_run=True) test.passes() verilator-5.042/test_regress/t/t_flag_parameter.py0000755000542200017500000000107315101701376022740 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile( # It is not possible to put them into the options file v_flags2=['-f t/t_flag_parameter.vc']) test.execute() test.passes() verilator-5.042/test_regress/t/t_string_add_bad.out0000644000542200017500000000136315101701376023071 0ustar mahmoudyfreeshell%Error: t/t_string_add_bad.v:13:9: Operator ADD is not legal on string data types (IEEE 1800-2023 6.16) : ... note: In instance 't' : ... Suggest to concatenate strings use '{LHS, RHS, ...}' 13 | s += $sformatf(" a%0d", a); | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_string_add_bad.v:14:13: Operator ADD is not legal on string data types (IEEE 1800-2023 6.16) : ... note: In instance 't' : ... Suggest to concatenate strings use '{LHS, RHS, ...}' 14 | s = s + s; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_fork_none_var.py0000755000542200017500000000077115101701376022623 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_param_default_override.py0000755000542200017500000000100715101701376024467 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--binary -Wno-MULTITOP']) test.execute() test.passes() verilator-5.042/test_regress/t/t_dpi_arg_inout_type.out0000644000542200017500000001206115101701376024026 0ustar mahmoudyfreeshelli_chandle 0 i_string 0 i_bit 0 i_logic 0 i_chandle_t 0 i_string_t 0 i_bit_t 0 i_logic_t 0 i_array_2_state_1 0 i_array_2_state_32 0 i_array_2_state_33 0 i_array_2_state_64 0 i_array_2_state_65 0 i_array_2_state_128 0 i_struct_2_state_1 0 i_struct_2_state_32 0 i_struct_2_state_33 0 i_struct_2_state_64 0 i_struct_2_state_65 0 i_struct_2_state_128 0 i_union_2_state_1 0 i_union_2_state_32 0 i_union_2_state_33 0 i_union_2_state_64 0 i_union_2_state_65 0 i_union_2_state_128 0 i_array_4_state_1 0 i_array_4_state_32 0 i_array_4_state_33 0 i_array_4_state_64 0 i_array_4_state_65 0 i_array_4_state_128 0 i_struct_4_state_1 0 i_struct_4_state_32 0 i_struct_4_state_33 0 i_struct_4_state_64 0 i_struct_4_state_65 0 i_struct_4_state_128 0 i_union_4_state_1 0 i_union_4_state_32 0 i_union_4_state_33 0 i_union_4_state_64 0 i_union_4_state_65 0 i_union_4_state_128 0 e_chandle 0 e_string 0 e_bit 0 e_logic 0 e_chandle_t 0 e_string_t 0 e_bit_t 0 e_logic_t 0 e_array_2_state_1 0 e_array_2_state_32 0 e_array_2_state_33 0 e_array_2_state_64 0 e_array_2_state_65 0 e_array_2_state_128 0 e_struct_2_state_1 0 e_struct_2_state_32 0 e_struct_2_state_33 0 e_struct_2_state_64 0 e_struct_2_state_65 0 e_struct_2_state_128 0 e_union_2_state_1 0 e_union_2_state_32 0 e_union_2_state_33 0 e_union_2_state_64 0 e_union_2_state_65 0 e_union_2_state_128 0 e_array_4_state_1 0 e_array_4_state_32 0 e_array_4_state_33 0 e_array_4_state_64 0 e_array_4_state_65 0 e_array_4_state_128 0 e_struct_4_state_1 0 e_struct_4_state_32 0 e_struct_4_state_33 0 e_struct_4_state_64 0 e_struct_4_state_65 0 e_struct_4_state_128 0 e_union_4_state_1 0 e_union_4_state_32 0 e_union_4_state_33 0 e_union_4_state_64 0 e_union_4_state_65 0 e_union_4_state_128 0 i_chandle 1 i_string 1 i_bit 1 i_logic 1 i_chandle_t 1 i_string_t 1 i_bit_t 1 i_logic_t 1 i_array_2_state_1 1 i_array_2_state_32 1 i_array_2_state_33 1 i_array_2_state_64 1 i_array_2_state_65 1 i_array_2_state_128 1 i_struct_2_state_1 1 i_struct_2_state_32 1 i_struct_2_state_33 1 i_struct_2_state_64 1 i_struct_2_state_65 1 i_struct_2_state_128 1 i_union_2_state_1 1 i_union_2_state_32 1 i_union_2_state_33 1 i_union_2_state_64 1 i_union_2_state_65 1 i_union_2_state_128 1 i_array_4_state_1 1 i_array_4_state_32 1 i_array_4_state_33 1 i_array_4_state_64 1 i_array_4_state_65 1 i_array_4_state_128 1 i_struct_4_state_1 1 i_struct_4_state_32 1 i_struct_4_state_33 1 i_struct_4_state_64 1 i_struct_4_state_65 1 i_struct_4_state_128 1 i_union_4_state_1 1 i_union_4_state_32 1 i_union_4_state_33 1 i_union_4_state_64 1 i_union_4_state_65 1 i_union_4_state_128 1 e_chandle 1 e_string 1 e_bit 1 e_logic 1 e_chandle_t 1 e_string_t 1 e_bit_t 1 e_logic_t 1 e_array_2_state_1 1 e_array_2_state_32 1 e_array_2_state_33 1 e_array_2_state_64 1 e_array_2_state_65 1 e_array_2_state_128 1 e_struct_2_state_1 1 e_struct_2_state_32 1 e_struct_2_state_33 1 e_struct_2_state_64 1 e_struct_2_state_65 1 e_struct_2_state_128 1 e_union_2_state_1 1 e_union_2_state_32 1 e_union_2_state_33 1 e_union_2_state_64 1 e_union_2_state_65 1 e_union_2_state_128 1 e_array_4_state_1 1 e_array_4_state_32 1 e_array_4_state_33 1 e_array_4_state_64 1 e_array_4_state_65 1 e_array_4_state_128 1 e_struct_4_state_1 1 e_struct_4_state_32 1 e_struct_4_state_33 1 e_struct_4_state_64 1 e_struct_4_state_65 1 e_struct_4_state_128 1 e_union_4_state_1 1 e_union_4_state_32 1 e_union_4_state_33 1 e_union_4_state_64 1 e_union_4_state_65 1 e_union_4_state_128 1 i_chandle 2 i_string 2 i_bit 2 i_logic 2 i_chandle_t 2 i_string_t 2 i_bit_t 2 i_logic_t 2 i_array_2_state_1 2 i_array_2_state_32 2 i_array_2_state_33 2 i_array_2_state_64 2 i_array_2_state_65 2 i_array_2_state_128 2 i_struct_2_state_1 2 i_struct_2_state_32 2 i_struct_2_state_33 2 i_struct_2_state_64 2 i_struct_2_state_65 2 i_struct_2_state_128 2 i_union_2_state_1 2 i_union_2_state_32 2 i_union_2_state_33 2 i_union_2_state_64 2 i_union_2_state_65 2 i_union_2_state_128 2 i_array_4_state_1 2 i_array_4_state_32 2 i_array_4_state_33 2 i_array_4_state_64 2 i_array_4_state_65 2 i_array_4_state_128 2 i_struct_4_state_1 2 i_struct_4_state_32 2 i_struct_4_state_33 2 i_struct_4_state_64 2 i_struct_4_state_65 2 i_struct_4_state_128 2 i_union_4_state_1 2 i_union_4_state_32 2 i_union_4_state_33 2 i_union_4_state_64 2 i_union_4_state_65 2 i_union_4_state_128 2 e_chandle 2 e_string 2 e_bit 2 e_logic 2 e_chandle_t 2 e_string_t 2 e_bit_t 2 e_logic_t 2 e_array_2_state_1 2 e_array_2_state_32 2 e_array_2_state_33 2 e_array_2_state_64 2 e_array_2_state_65 2 e_array_2_state_128 2 e_struct_2_state_1 2 e_struct_2_state_32 2 e_struct_2_state_33 2 e_struct_2_state_64 2 e_struct_2_state_65 2 e_struct_2_state_128 2 e_union_2_state_1 2 e_union_2_state_32 2 e_union_2_state_33 2 e_union_2_state_64 2 e_union_2_state_65 2 e_union_2_state_128 2 e_array_4_state_1 2 e_array_4_state_32 2 e_array_4_state_33 2 e_array_4_state_64 2 e_array_4_state_65 2 e_array_4_state_128 2 e_struct_4_state_1 2 e_struct_4_state_32 2 e_struct_4_state_33 2 e_struct_4_state_64 2 e_struct_4_state_65 2 e_struct_4_state_128 2 e_union_4_state_1 2 e_union_4_state_32 2 e_union_4_state_33 2 e_union_4_state_64 2 e_union_4_state_65 2 e_union_4_state_128 2 *-* All Finished *-* verilator-5.042/test_regress/t/t_enum_x_bad.py0000755000542200017500000000076615101701376022100 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_trace_ub_misaligned_address.out0000644000542200017500000000002515101701376025624 0ustar mahmoudyfreeshell*-* All Finished *-* verilator-5.042/test_regress/t/t_flag_help.py0000755000542200017500000000237415101701376021715 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') # See also t_flag_version.py def check(prog): logfile = test.obj_dir + "/t_help__" + os.path.basename(prog) + ".log" # Not using logfile=logfile as would invoke PAGER test.run(fails=False, cmd=[prog, "--help", ">", logfile, "2>&1"], tee=False, verilator_run=True) test.file_grep(logfile, r'(DISTRIBUTION|usage:)') check(os.environ["VERILATOR_ROOT"] + "/bin/verilator") check(os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage") check(os.environ["VERILATOR_ROOT"] + "/bin/verilator_ccache_report") check(os.environ["VERILATOR_ROOT"] + "/bin/verilator_gantt") check(os.environ["VERILATOR_ROOT"] + "/bin/verilator_profcfunc") if os.path.exists(os.environ["VERILATOR_ROOT"] + "/bin/verilator_difftree"): check(os.environ["VERILATOR_ROOT"] + "/bin/verilator_difftree") test.passes() verilator-5.042/test_regress/t/t_param_value.v0000644000542200017500000000337515101701376022104 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2012 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; `define ASSERT(x) initial if (!(x)) $stop // See IEEE 6.20.2 on value parameters localparam unsigned [63:0] UNSIGNED =64'h99934567_89abcdef; localparam signed [63:0] SIGNED =64'sh99934567_89abcdef; localparam real REAL=1.234; `ASSERT(UNSIGNED > 0); `ASSERT(SIGNED < 0); // bullet 1 localparam A1_WIDE = UNSIGNED; `ASSERT($bits(A1_WIDE)==64); localparam A2_REAL = REAL; `ASSERT(A2_REAL == 1.234); localparam A3_SIGNED = SIGNED; `ASSERT($bits(A3_SIGNED)==64 && A3_SIGNED < 0); localparam A4_EXPR = (2'b01 + 2'b10); `ASSERT($bits(A4_EXPR)==2 && A4_EXPR==2'b11); // bullet 2 localparam [63:0] B_UNSIGNED = SIGNED; `ASSERT($bits(B_UNSIGNED)==64 && B_UNSIGNED > 0); // bullet 3 localparam signed C_SIGNED = UNSIGNED; `ASSERT($bits(C_SIGNED)==64 && C_SIGNED < 0); localparam unsigned C_UNSIGNED = SIGNED; `ASSERT($bits(C_UNSIGNED)==64 && C_UNSIGNED > 0); // bullet 4 // verilator lint_off WIDTH localparam signed [59:0] D_SIGNED = UNSIGNED; `ASSERT($bits(D_SIGNED)==60 && D_SIGNED < 0); // verilator lint_on WIDTH // verilator lint_off WIDTH localparam unsigned [59:0] D_UNSIGNED = SIGNED; `ASSERT($bits(D_UNSIGNED)==60 && D_UNSIGNED > 0); // verilator lint_on WIDTH // bullet 6 localparam UNSIZED = 23; `ASSERT($bits(UNSIZED)>=32); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_if_swap.py0000755000542200017500000000071415101701376021420 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.passes() verilator-5.042/test_regress/t/t_randsequence_bad.v0000644000542200017500000000143515101701376023066 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2023 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; initial begin; randsequence(no_such_production) // Bad such_production: { }; endsequence randsequence(main) main: production_bad; // Bad production_baa: {}; endsequence randsequence() duplicated_bad: { $display("dup1"); }; duplicated_bad: { $display("dup2"); }; // Bad endsequence $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_hier_block_int.py0000755000542200017500000000124215101701376022740 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--stats', '--hierarchical']) test.execute() test.file_grep(test.obj_dir + "/Vsub/sub.sv", r'^module\s+(\S+)\s+', "sub") test.file_grep(test.stats, r'HierBlock,\s+Hierarchical blocks\s+(\d+)', 1) test.passes() verilator-5.042/test_regress/t/t_flag_threads_bad.out0000644000542200017500000000021015101701376023364 0ustar mahmoudyfreeshell%Error: --threads must be >= 0: -1 ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. verilator-5.042/test_regress/t/t_wrapper_legacy_timed.py0000755000542200017500000000133415101701376024155 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_wrapper_legacy.cpp" test.top_filename = "t/t_wrapper_legacy.v" test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename], make_flags=['CPPFLAGS_ADD=-UVL_TIME_CONTEXT']) test.execute() test.passes() verilator-5.042/test_regress/t/t_class_extern_args.py0000755000542200017500000000103315101701376023471 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = 't/t_class_extern_args_bad.v' test.lint(verilator_flags2=['-Wno-PROTOTYPEMIS']) test.passes() verilator-5.042/test_regress/t/t_clocking_inout.py0000755000542200017500000000101215101701376022767 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"], make_main=False) test.execute() test.passes() verilator-5.042/test_regress/t/t_for_count.v0000644000542200017500000000514015101701376021576 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; integer j; reg [63:0] cam_lookup_hit_vector; integer hit_count; always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin hit_count = 0; for (j=0; j < 64; j=j+1) begin hit_count = hit_count + {31'h0, cam_lookup_hit_vector[j]}; end end integer hit_count2; always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin hit_count2 = 0; for (j=63; j >= 0; j=j-1) begin hit_count2 = hit_count2 + {31'h0, cam_lookup_hit_vector[j]}; end end integer hit_count3; always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin hit_count3 = 0; for (j=63; j > 0; j=j-1) begin if (cam_lookup_hit_vector[j]) hit_count3 = hit_count3 + 32'd1; end end reg [127:0] wide_for_index; reg [31:0] wide_for_count; always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin wide_for_count = 0; for (wide_for_index = 128'hff_00000000_00000000; wide_for_index < 128'hff_00000000_00000100; wide_for_index = wide_for_index + 2) begin wide_for_count = wide_for_count+32'h1; end end // While loop int w; initial begin while (w<10) w=w+1; if (w!=10) $stop; while (w<20) begin w=w+2; end while (w<20) begin w=w+99999; end // NEVER if (w!=20) $stop; end // Do-While loop int dw; initial begin do dw=dw+1; while (dw<10); if (dw!=10) $stop; do dw=dw+2; while (dw<20); if (dw!=20) $stop; do dw=dw+5; while (dw<20); // Once if (dw!=25) $stop; end always @ (posedge clk) begin cam_lookup_hit_vector <= 0; if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin cam_lookup_hit_vector <= 64'h00010000_00010000; end if (cyc==2) begin if (hit_count != 32'd2) $stop; if (hit_count2 != 32'd2) $stop; if (hit_count3 != 32'd2) $stop; cam_lookup_hit_vector <= 64'h01010010_00010001; end if (cyc==3) begin if (hit_count != 32'd5) $stop; if (hit_count2 != 32'd5) $stop; if (hit_count3 != 32'd4) $stop; if (wide_for_count != 32'h80) $stop; end if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.042/test_regress/t/t_var_notfound_bad.v0000644000542200017500000000142115101701376023110 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; integer i; integer a_var; sub sub (); task nottask(); endtask function int notfunc(); return 0; endfunction initial begin nf = 0; // z not found sub.subsubz.inss = 0; // subsub not found i = nofunc(); // nofunc not found i = sub.nofuncs(); // nofuncs not found notask(); // notask not found a_var(); // Calling variable as task $finish; end endmodule module sub; subsub subsub (); function int notfuncs(); return 0; endfunction endmodule module subsub; integer inss; endmodule verilator-5.042/test_regress/t/t_lint_latch_3.v0000644000542200017500000000271715101701376022152 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module for issue #1609 // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by Julien Margetts. // SPDX-License-Identifier: Unlicense module t (/*AUTOARG*/ out, out2, in ); input [9:0] in; output reg [3:0] out; output reg [3:0] out2; // Should be no latch here since the input space is fully covered always @* begin casez (in) 10'b0000000000 : out = 4'h0; 10'b?????????1 : out = 4'h0; 10'b????????10 : out = 4'h1; 10'b???????100 : out = 4'h2; 10'b??????1000 : out = 4'h3; 10'b?????10000 : out = 4'h4; 10'b????100000 : out = 4'h5; 10'b???1000000 : out = 4'h6; 10'b??10000000 : out = 4'h7; 10'b?100000000 : out = 4'h8; 10'b1000000000 : out = 4'h9; endcase end // Should detect a latch here since not all paths assign // BUT we don't because warnOff(LATCH) is set for any always containing a // complex case statement always @* begin casez (in) 10'b0000000000 : out2 = 4'h0; 10'b?????????1 : out2 = 4'h0; 10'b????????10 : out2 = 4'h1; 10'b???????100 : out2 = 4'h2; 10'b??????1000 : out2 = 4'h3; 10'b?????10000 : /* No assignement */ ; 10'b????100000 : out2 = 4'h5; 10'b???1000000 : out2 = 4'h6; 10'b??10000000 : out2 = 4'h7; 10'b?100000000 : out2 = 4'h8; 10'b1000000000 : out2 = 4'h9; endcase end endmodule verilator-5.042/test_regress/t/t_dfg_stats_patterns.v0000644000542200017500000000133315101701376023476 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( input wire [3:0] a, input wire [3:0] b, input wire [3:0] c, output wire [10:0] o ); wire [ 3:0] x = ~a & ~b; wire [ 3:0] y = ~b & ~c; wire [ 3:0] z = ~c & ~a; wire [ 0:0] w1 = x[0]; wire [ 7:0] w8 = {8{x[1]}}; wire [15:0] w16 = {2{w8}}; wire [31:0] w32 = {2{w16}}; wire [63:0] w64a = {2{w32}}; wire [63:0] w64b = {2{~w32}}; wire [62:0] w63 = 63'({2{~w32}}); wire [95:0] w96 = 96'(w64a); assign o = {^x, ^y, ^z, ^w1, ^w8, ^w16, ^w32, ^w64a, ^w64b, ^w63, ^w96}; endmodule verilator-5.042/test_regress/t/t_json_only_flat_vlvbound.out0000644000542200017500000010560415101701376025107 0ustar mahmoudyfreeshell{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"(E)", "modulesp": [ {"type":"MODULE","name":"$root","addr":"(F)","loc":"d,7:8,7:21","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"$root","level":1,"modPublic":true,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"i_a","addr":"(G)","loc":"d,9:25,9:28","dtypep":"(H)","origName":"i_a","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"i_b","addr":"(I)","loc":"d,10:25,10:28","dtypep":"(H)","origName":"i_b","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"o_a","addr":"(J)","loc":"d,11:25,11:28","dtypep":"(K)","origName":"o_a","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"o_b","addr":"(L)","loc":"d,12:25,12:28","dtypep":"(K)","origName":"o_b","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"vlvbound_test.i_a","addr":"(M)","loc":"d,9:25,9:28","dtypep":"(H)","origName":"i_a","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"vlvbound_test.i_b","addr":"(N)","loc":"d,10:25,10:28","dtypep":"(H)","origName":"i_b","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"vlvbound_test.o_a","addr":"(O)","loc":"d,11:25,11:28","dtypep":"(K)","origName":"o_a","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"vlvbound_test.o_b","addr":"(P)","loc":"d,12:25,12:28","dtypep":"(K)","origName":"o_b","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"TOPSCOPE","name":"","addr":"(E)","loc":"d,7:8,7:21","senTreesp": [], "scopep": [ {"type":"SCOPE","name":"TOP","addr":"(Q)","loc":"d,7:8,7:21","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(F)", "varsp": [ {"type":"VARSCOPE","name":"i_a","addr":"(R)","loc":"d,9:25,9:28","dtypep":"(H)","isTrace":true,"scopep":"(Q)","varp":"(G)"}, {"type":"VARSCOPE","name":"i_b","addr":"(S)","loc":"d,10:25,10:28","dtypep":"(H)","isTrace":true,"scopep":"(Q)","varp":"(I)"}, {"type":"VARSCOPE","name":"o_a","addr":"(T)","loc":"d,11:25,11:28","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(J)"}, {"type":"VARSCOPE","name":"o_b","addr":"(U)","loc":"d,12:25,12:28","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(L)"}, {"type":"VARSCOPE","name":"vlvbound_test.i_a","addr":"(V)","loc":"d,9:25,9:28","dtypep":"(H)","isTrace":true,"scopep":"(Q)","varp":"(M)"}, {"type":"ALWAYS","name":"","addr":"(W)","loc":"d,9:25,9:28","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(X)","loc":"d,9:25,9:28","dtypep":"(H)", "rhsp": [ {"type":"VARREF","name":"i_a","addr":"(Y)","loc":"d,9:25,9:28","dtypep":"(H)","access":"RD","varp":"(G)","varScopep":"(R)","classOrPackagep":"UNLINKED"} ], "lhsp": [ {"type":"VARREF","name":"vlvbound_test.i_a","addr":"(Z)","loc":"d,9:25,9:28","dtypep":"(H)","access":"WR","varp":"(M)","varScopep":"(V)","classOrPackagep":"UNLINKED"} ],"timingControlp": [],"strengthSpecp": []} ]}, {"type":"VARSCOPE","name":"vlvbound_test.i_b","addr":"(AB)","loc":"d,10:25,10:28","dtypep":"(H)","isTrace":true,"scopep":"(Q)","varp":"(N)"}, {"type":"ALWAYS","name":"","addr":"(BB)","loc":"d,10:25,10:28","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(CB)","loc":"d,10:25,10:28","dtypep":"(H)", "rhsp": [ {"type":"VARREF","name":"i_b","addr":"(DB)","loc":"d,10:25,10:28","dtypep":"(H)","access":"RD","varp":"(I)","varScopep":"(S)","classOrPackagep":"UNLINKED"} ], "lhsp": [ {"type":"VARREF","name":"vlvbound_test.i_b","addr":"(EB)","loc":"d,10:25,10:28","dtypep":"(H)","access":"WR","varp":"(N)","varScopep":"(AB)","classOrPackagep":"UNLINKED"} ],"timingControlp": [],"strengthSpecp": []} ]}, {"type":"VARSCOPE","name":"vlvbound_test.o_a","addr":"(FB)","loc":"d,11:25,11:28","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(O)"}, {"type":"ALWAYS","name":"","addr":"(GB)","loc":"d,11:25,11:28","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(HB)","loc":"d,11:25,11:28","dtypep":"(K)", "rhsp": [ {"type":"VARREF","name":"o_a","addr":"(IB)","loc":"d,11:25,11:28","dtypep":"(K)","access":"RD","varp":"(J)","varScopep":"(T)","classOrPackagep":"UNLINKED"} ], "lhsp": [ {"type":"VARREF","name":"vlvbound_test.o_a","addr":"(JB)","loc":"d,11:25,11:28","dtypep":"(K)","access":"WR","varp":"(O)","varScopep":"(FB)","classOrPackagep":"UNLINKED"} ],"timingControlp": [],"strengthSpecp": []} ]}, {"type":"VARSCOPE","name":"vlvbound_test.o_b","addr":"(KB)","loc":"d,12:25,12:28","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(P)"}, {"type":"ALWAYS","name":"","addr":"(LB)","loc":"d,12:25,12:28","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(MB)","loc":"d,12:25,12:28","dtypep":"(K)", "rhsp": [ {"type":"VARREF","name":"o_b","addr":"(NB)","loc":"d,12:25,12:28","dtypep":"(K)","access":"RD","varp":"(L)","varScopep":"(U)","classOrPackagep":"UNLINKED"} ], "lhsp": [ {"type":"VARREF","name":"vlvbound_test.o_b","addr":"(OB)","loc":"d,12:25,12:28","dtypep":"(K)","access":"WR","varp":"(P)","varScopep":"(KB)","classOrPackagep":"UNLINKED"} ],"timingControlp": [],"strengthSpecp": []} ]}, {"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__0__Vfuncout","addr":"(PB)","loc":"d,15:34,15:37","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(QB)"}, {"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__0__val","addr":"(RB)","loc":"d,15:57,15:60","dtypep":"(H)","isTrace":true,"scopep":"(Q)","varp":"(SB)"}, {"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__0__ret","addr":"(TB)","loc":"d,16:17,16:20","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(UB)"}, {"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__0__i","addr":"(VB)","loc":"d,17:13,17:14","dtypep":"(WB)","isTrace":true,"scopep":"(Q)","varp":"(XB)"}, {"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__1__Vfuncout","addr":"(YB)","loc":"d,15:34,15:37","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(ZB)"}, {"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__1__val","addr":"(AC)","loc":"d,15:57,15:60","dtypep":"(H)","isTrace":true,"scopep":"(Q)","varp":"(BC)"}, {"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__1__ret","addr":"(CC)","loc":"d,16:17,16:20","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(DC)"}, {"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__1__i","addr":"(EC)","loc":"d,17:13,17:14","dtypep":"(WB)","isTrace":true,"scopep":"(Q)","varp":"(FC)"} ], "blocksp": [ {"type":"ALWAYS","name":"","addr":"(GC)","loc":"d,24:14,24:15","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"COMMENT","name":"Function: foo","addr":"(HC)","loc":"d,24:16,24:19"}, {"type":"ASSIGN","name":"","addr":"(IC)","loc":"d,24:20,24:23","dtypep":"(H)", "rhsp": [ {"type":"VARREF","name":"i_a","addr":"(JC)","loc":"d,24:20,24:23","dtypep":"(H)","access":"RD","varp":"(G)","varScopep":"(R)","classOrPackagep":"UNLINKED"} ], "lhsp": [ {"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__val","addr":"(KC)","loc":"d,15:57,15:60","dtypep":"(H)","access":"WR","varp":"(SB)","varScopep":"(RB)","classOrPackagep":"UNLINKED"} ],"timingControlp": []}, {"type":"CRESET","name":"","addr":"(LC)","loc":"d,16:17,16:20","constructing":false, "varrefp": [ {"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__ret","addr":"(MC)","loc":"d,16:17,16:20","dtypep":"(K)","access":"WR","varp":"(UB)","varScopep":"(TB)","classOrPackagep":"UNLINKED"} ]}, {"type":"CRESET","name":"","addr":"(NC)","loc":"d,17:13,17:14","constructing":false, "varrefp": [ {"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__i","addr":"(OC)","loc":"d,17:13,17:14","dtypep":"(WB)","access":"WR","varp":"(XB)","varScopep":"(VB)","classOrPackagep":"UNLINKED"} ]}, {"type":"ASSIGN","name":"","addr":"(PC)","loc":"d,18:11,18:12","dtypep":"(WB)", "rhsp": [ {"type":"CONST","name":"32'sh0","addr":"(QC)","loc":"d,18:12,18:13","dtypep":"(RC)"} ], "lhsp": [ {"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__i","addr":"(SC)","loc":"d,18:10,18:11","dtypep":"(WB)","access":"WR","varp":"(XB)","varScopep":"(VB)","classOrPackagep":"UNLINKED"} ],"timingControlp": []}, {"type":"LOOP","name":"","addr":"(TC)","loc":"d,18:5,18:8","unroll":"default", "stmtsp": [ {"type":"LOOPTEST","name":"","addr":"(UC)","loc":"d,18:16,18:17", "condp": [ {"type":"GTS","name":"","addr":"(VC)","loc":"d,18:18,18:19","dtypep":"(WC)", "lhsp": [ {"type":"CONST","name":"32'sh7","addr":"(XC)","loc":"d,18:20,18:21","dtypep":"(RC)"} ], "rhsp": [ {"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__i","addr":"(YC)","loc":"d,18:16,18:17","dtypep":"(WB)","access":"RD","varp":"(XB)","varScopep":"(VB)","classOrPackagep":"UNLINKED"} ]} ]}, {"type":"ASSIGN","name":"","addr":"(ZC)","loc":"d,19:14,19:15","dtypep":"(WC)", "rhsp": [ {"type":"EQ","name":"","addr":"(AD)","loc":"d,19:31,19:33","dtypep":"(WC)", "lhsp": [ {"type":"CONST","name":"2'h0","addr":"(BD)","loc":"d,19:34,19:39","dtypep":"(CD)"} ], "rhsp": [ {"type":"SEL","name":"","addr":"(DD)","loc":"d,19:20,19:21","dtypep":"(CD)","widthConst":2,"declRange":"[15:0]","declElWidth":1, "fromp": [ {"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__val","addr":"(ED)","loc":"d,19:17,19:20","dtypep":"(H)","access":"RD","varp":"(SB)","varScopep":"(RB)","classOrPackagep":"UNLINKED"} ], "lsbp": [ {"type":"SEL","name":"","addr":"(FD)","loc":"d,19:22,19:23","dtypep":"(GD)","widthConst":4, "fromp": [ {"type":"MULS","name":"","addr":"(HD)","loc":"d,19:22,19:23","dtypep":"(RC)", "lhsp": [ {"type":"CONST","name":"32'sh2","addr":"(ID)","loc":"d,19:23,19:24","dtypep":"(RC)"} ], "rhsp": [ {"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__i","addr":"(JD)","loc":"d,19:21,19:22","dtypep":"(WB)","access":"RD","varp":"(XB)","varScopep":"(VB)","classOrPackagep":"UNLINKED"} ]} ], "lsbp": [ {"type":"CONST","name":"32'h0","addr":"(KD)","loc":"d,19:22,19:23","dtypep":"(LD)"} ]} ]} ]} ], "lhsp": [ {"type":"SEL","name":"","addr":"(MD)","loc":"d,19:10,19:11","dtypep":"(WC)","widthConst":1,"declRange":"[6:0]","declElWidth":1, "fromp": [ {"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__ret","addr":"(ND)","loc":"d,19:7,19:10","dtypep":"(K)","access":"WR","varp":"(UB)","varScopep":"(TB)","classOrPackagep":"UNLINKED"} ], "lsbp": [ {"type":"SEL","name":"","addr":"(OD)","loc":"d,19:11,19:12","dtypep":"(PD)","widthConst":3, "fromp": [ {"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__i","addr":"(QD)","loc":"d,19:11,19:12","dtypep":"(WB)","access":"RD","varp":"(XB)","varScopep":"(VB)","classOrPackagep":"UNLINKED"} ], "lsbp": [ {"type":"CONST","name":"32'h0","addr":"(RD)","loc":"d,19:11,19:12","dtypep":"(LD)"} ]} ]} ],"timingControlp": []}, {"type":"ASSIGN","name":"","addr":"(SD)","loc":"d,18:24,18:26","dtypep":"(WB)", "rhsp": [ {"type":"ADD","name":"","addr":"(TD)","loc":"d,18:24,18:26","dtypep":"(LD)", "lhsp": [ {"type":"CONST","name":"32'h1","addr":"(UD)","loc":"d,18:24,18:26","dtypep":"(LD)"} ], "rhsp": [ {"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__i","addr":"(VD)","loc":"d,18:23,18:24","dtypep":"(WB)","access":"RD","varp":"(XB)","varScopep":"(VB)","classOrPackagep":"UNLINKED"} ]} ], "lhsp": [ {"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__i","addr":"(WD)","loc":"d,18:23,18:24","dtypep":"(WB)","access":"WR","varp":"(XB)","varScopep":"(VB)","classOrPackagep":"UNLINKED"} ],"timingControlp": []} ],"contsp": []}, {"type":"ASSIGN","name":"","addr":"(XD)","loc":"d,21:5,21:11","dtypep":"(K)", "rhsp": [ {"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__ret","addr":"(YD)","loc":"d,21:12,21:15","dtypep":"(K)","access":"RD","varp":"(UB)","varScopep":"(TB)","classOrPackagep":"UNLINKED"} ], "lhsp": [ {"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__Vfuncout","addr":"(ZD)","loc":"d,21:5,21:11","dtypep":"(K)","access":"WR","varp":"(QB)","varScopep":"(PB)","classOrPackagep":"UNLINKED"} ],"timingControlp": []}, {"type":"ASSIGNW","name":"","addr":"(AE)","loc":"d,24:14,24:15","dtypep":"(K)", "rhsp": [ {"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__Vfuncout","addr":"(BE)","loc":"d,24:16,24:19","dtypep":"(K)","access":"RD","varp":"(QB)","varScopep":"(PB)","classOrPackagep":"UNLINKED"} ], "lhsp": [ {"type":"VARREF","name":"o_a","addr":"(CE)","loc":"d,24:10,24:13","dtypep":"(K)","access":"WR","varp":"(J)","varScopep":"(T)","classOrPackagep":"UNLINKED"} ],"timingControlp": [],"strengthSpecp": []} ]}, {"type":"ALWAYS","name":"","addr":"(DE)","loc":"d,25:14,25:15","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"COMMENT","name":"Function: foo","addr":"(EE)","loc":"d,25:16,25:19"}, {"type":"ASSIGN","name":"","addr":"(FE)","loc":"d,25:20,25:23","dtypep":"(H)", "rhsp": [ {"type":"VARREF","name":"i_b","addr":"(GE)","loc":"d,25:20,25:23","dtypep":"(H)","access":"RD","varp":"(I)","varScopep":"(S)","classOrPackagep":"UNLINKED"} ], "lhsp": [ {"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__1__val","addr":"(HE)","loc":"d,15:57,15:60","dtypep":"(H)","access":"WR","varp":"(BC)","varScopep":"(AC)","classOrPackagep":"UNLINKED"} ],"timingControlp": []}, {"type":"CRESET","name":"","addr":"(IE)","loc":"d,16:17,16:20","constructing":false, "varrefp": [ {"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__1__ret","addr":"(JE)","loc":"d,16:17,16:20","dtypep":"(K)","access":"WR","varp":"(DC)","varScopep":"(CC)","classOrPackagep":"UNLINKED"} ]}, {"type":"CRESET","name":"","addr":"(KE)","loc":"d,17:13,17:14","constructing":false, "varrefp": [ {"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__1__i","addr":"(LE)","loc":"d,17:13,17:14","dtypep":"(WB)","access":"WR","varp":"(FC)","varScopep":"(EC)","classOrPackagep":"UNLINKED"} ]}, {"type":"ASSIGN","name":"","addr":"(ME)","loc":"d,18:11,18:12","dtypep":"(WB)", "rhsp": [ {"type":"CONST","name":"32'sh0","addr":"(NE)","loc":"d,18:12,18:13","dtypep":"(RC)"} ], "lhsp": [ {"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__1__i","addr":"(OE)","loc":"d,18:10,18:11","dtypep":"(WB)","access":"WR","varp":"(FC)","varScopep":"(EC)","classOrPackagep":"UNLINKED"} ],"timingControlp": []}, {"type":"LOOP","name":"","addr":"(PE)","loc":"d,18:5,18:8","unroll":"default", "stmtsp": [ {"type":"LOOPTEST","name":"","addr":"(QE)","loc":"d,18:16,18:17", "condp": [ {"type":"GTS","name":"","addr":"(RE)","loc":"d,18:18,18:19","dtypep":"(WC)", "lhsp": [ {"type":"CONST","name":"32'sh7","addr":"(SE)","loc":"d,18:20,18:21","dtypep":"(RC)"} ], "rhsp": [ {"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__1__i","addr":"(TE)","loc":"d,18:16,18:17","dtypep":"(WB)","access":"RD","varp":"(FC)","varScopep":"(EC)","classOrPackagep":"UNLINKED"} ]} ]}, {"type":"ASSIGN","name":"","addr":"(UE)","loc":"d,19:14,19:15","dtypep":"(WC)", "rhsp": [ {"type":"EQ","name":"","addr":"(VE)","loc":"d,19:31,19:33","dtypep":"(WC)", "lhsp": [ {"type":"CONST","name":"2'h0","addr":"(WE)","loc":"d,19:34,19:39","dtypep":"(CD)"} ], "rhsp": [ {"type":"SEL","name":"","addr":"(XE)","loc":"d,19:20,19:21","dtypep":"(CD)","widthConst":2,"declRange":"[15:0]","declElWidth":1, "fromp": [ {"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__1__val","addr":"(YE)","loc":"d,19:17,19:20","dtypep":"(H)","access":"RD","varp":"(BC)","varScopep":"(AC)","classOrPackagep":"UNLINKED"} ], "lsbp": [ {"type":"SEL","name":"","addr":"(ZE)","loc":"d,19:22,19:23","dtypep":"(GD)","widthConst":4, "fromp": [ {"type":"MULS","name":"","addr":"(AF)","loc":"d,19:22,19:23","dtypep":"(RC)", "lhsp": [ {"type":"CONST","name":"32'sh2","addr":"(BF)","loc":"d,19:23,19:24","dtypep":"(RC)"} ], "rhsp": [ {"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__1__i","addr":"(CF)","loc":"d,19:21,19:22","dtypep":"(WB)","access":"RD","varp":"(FC)","varScopep":"(EC)","classOrPackagep":"UNLINKED"} ]} ], "lsbp": [ {"type":"CONST","name":"32'h0","addr":"(DF)","loc":"d,19:22,19:23","dtypep":"(LD)"} ]} ]} ]} ], "lhsp": [ {"type":"SEL","name":"","addr":"(EF)","loc":"d,19:10,19:11","dtypep":"(WC)","widthConst":1,"declRange":"[6:0]","declElWidth":1, "fromp": [ {"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__1__ret","addr":"(FF)","loc":"d,19:7,19:10","dtypep":"(K)","access":"WR","varp":"(DC)","varScopep":"(CC)","classOrPackagep":"UNLINKED"} ], "lsbp": [ {"type":"SEL","name":"","addr":"(GF)","loc":"d,19:11,19:12","dtypep":"(PD)","widthConst":3, "fromp": [ {"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__1__i","addr":"(HF)","loc":"d,19:11,19:12","dtypep":"(WB)","access":"RD","varp":"(FC)","varScopep":"(EC)","classOrPackagep":"UNLINKED"} ], "lsbp": [ {"type":"CONST","name":"32'h0","addr":"(IF)","loc":"d,19:11,19:12","dtypep":"(LD)"} ]} ]} ],"timingControlp": []}, {"type":"ASSIGN","name":"","addr":"(JF)","loc":"d,18:24,18:26","dtypep":"(WB)", "rhsp": [ {"type":"ADD","name":"","addr":"(KF)","loc":"d,18:24,18:26","dtypep":"(LD)", "lhsp": [ {"type":"CONST","name":"32'h1","addr":"(LF)","loc":"d,18:24,18:26","dtypep":"(LD)"} ], "rhsp": [ {"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__1__i","addr":"(MF)","loc":"d,18:23,18:24","dtypep":"(WB)","access":"RD","varp":"(FC)","varScopep":"(EC)","classOrPackagep":"UNLINKED"} ]} ], "lhsp": [ {"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__1__i","addr":"(NF)","loc":"d,18:23,18:24","dtypep":"(WB)","access":"WR","varp":"(FC)","varScopep":"(EC)","classOrPackagep":"UNLINKED"} ],"timingControlp": []} ],"contsp": []}, {"type":"ASSIGN","name":"","addr":"(OF)","loc":"d,21:5,21:11","dtypep":"(K)", "rhsp": [ {"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__1__ret","addr":"(PF)","loc":"d,21:12,21:15","dtypep":"(K)","access":"RD","varp":"(DC)","varScopep":"(CC)","classOrPackagep":"UNLINKED"} ], "lhsp": [ {"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__1__Vfuncout","addr":"(QF)","loc":"d,21:5,21:11","dtypep":"(K)","access":"WR","varp":"(ZB)","varScopep":"(YB)","classOrPackagep":"UNLINKED"} ],"timingControlp": []}, {"type":"ASSIGNW","name":"","addr":"(RF)","loc":"d,25:14,25:15","dtypep":"(K)", "rhsp": [ {"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__1__Vfuncout","addr":"(SF)","loc":"d,25:16,25:19","dtypep":"(K)","access":"RD","varp":"(ZB)","varScopep":"(YB)","classOrPackagep":"UNLINKED"} ], "lhsp": [ {"type":"VARREF","name":"o_b","addr":"(TF)","loc":"d,25:10,25:13","dtypep":"(K)","access":"WR","varp":"(L)","varScopep":"(U)","classOrPackagep":"UNLINKED"} ],"timingControlp": [],"strengthSpecp": []} ]} ],"inlinesp": []} ]}, {"type":"VAR","name":"__Vfunc_vlvbound_test.foo__0__Vfuncout","addr":"(QB)","loc":"d,15:34,15:37","dtypep":"(K)","origName":"__Vfunc_vlvbound_test__DOT__foo__0__Vfuncout","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"__Vfunc_vlvbound_test.foo__0__val","addr":"(SB)","loc":"d,15:57,15:60","dtypep":"(H)","origName":"__Vfunc_vlvbound_test__DOT__foo__0__val","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"__Vfunc_vlvbound_test.foo__0__ret","addr":"(UB)","loc":"d,16:17,16:20","dtypep":"(K)","origName":"__Vfunc_vlvbound_test__DOT__foo__0__ret","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"__Vfunc_vlvbound_test.foo__0__i","addr":"(XB)","loc":"d,17:13,17:14","dtypep":"(WB)","origName":"__Vfunc_vlvbound_test__DOT__foo__0__i","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"integer","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"__Vfunc_vlvbound_test.foo__1__Vfuncout","addr":"(ZB)","loc":"d,15:34,15:37","dtypep":"(K)","origName":"__Vfunc_vlvbound_test__DOT__foo__1__Vfuncout","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"__Vfunc_vlvbound_test.foo__1__val","addr":"(BC)","loc":"d,15:57,15:60","dtypep":"(H)","origName":"__Vfunc_vlvbound_test__DOT__foo__1__val","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"__Vfunc_vlvbound_test.foo__1__ret","addr":"(DC)","loc":"d,16:17,16:20","dtypep":"(K)","origName":"__Vfunc_vlvbound_test__DOT__foo__1__ret","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"__Vfunc_vlvbound_test.foo__1__i","addr":"(FC)","loc":"d,17:13,17:14","dtypep":"(WB)","origName":"__Vfunc_vlvbound_test__DOT__foo__1__i","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"BLOCKTEMP","dtypeName":"integer","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ]} ],"filesp": [], "miscsp": [ {"type":"TYPETABLE","name":"","addr":"(C)","loc":"a,0:0,0:0","constraintRefp":"UNLINKED","emptyQueuep":"UNLINKED","queueIndexp":"UNLINKED","streamp":"UNLINKED","voidp":"(UF)", "typesp": [ {"type":"BASICDTYPE","name":"logic","addr":"(WC)","loc":"d,18:18,18:19","dtypep":"(WC)","keyword":"logic","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(CD)","loc":"d,19:34,19:39","dtypep":"(CD)","keyword":"logic","range":"1:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(H)","loc":"d,9:11,9:16","dtypep":"(H)","keyword":"logic","range":"15:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(K)","loc":"d,11:12,11:17","dtypep":"(K)","keyword":"logic","range":"6:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"integer","addr":"(WB)","loc":"d,17:5,17:12","dtypep":"(WB)","keyword":"integer","range":"31:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(PD)","loc":"d,19:10,19:11","dtypep":"(PD)","keyword":"logic","range":"2:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(LD)","loc":"d,19:11,19:12","dtypep":"(LD)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(GD)","loc":"d,19:20,19:21","dtypep":"(GD)","keyword":"logic","range":"3:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(RC)","loc":"d,18:12,18:13","dtypep":"(RC)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, {"type":"VOIDDTYPE","name":"","addr":"(UF)","loc":"a,0:0,0:0","dtypep":"(UF)","generic":false} ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ {"type":"MODULE","name":"@CONST-POOL@","addr":"(VF)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], "stmtsp": [ {"type":"SCOPE","name":"@CONST-POOL@","addr":"(WF)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(VF)","varsp": [],"blocksp": [],"inlinesp": []} ]} ]} ]} verilator-5.042/test_regress/t/t_dpi_open.py0000755000542200017500000000110615101701376021561 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=["t/t_dpi_open_c.cpp"], verilator_flags2=["-Wall -Wno-DECLFILENAME -unroll-count 1"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_class_param_override_local_bad.out0000644000542200017500000000156015101701376026310 0ustar mahmoudyfreeshell%Error-PINNOTFOUND: t/t_class_param_override_local_bad.v:23:30: Parameter not found: '__paramNumber1' 23 | class Cls3 implements Icls1#(2), Icls2#(0); | ^ ... For error description see https://verilator.org/warn/PINNOTFOUND?v=latest %Error-PINNOTFOUND: t/t_class_param_override_local_bad.v:23:41: Parameter not found: '__paramNumber1' 23 | class Cls3 implements Icls1#(2), Icls2#(0); | ^ %Error-PINNOTFOUND: t/t_class_param_override_local_bad.v:29:23: Parameter not found: '__paramNumber1' 29 | automatic Cls1#(bit) cls1 = new; | ^~~ %Error-PINNOTFOUND: t/t_class_param_override_local_bad.v:30:23: Parameter not found: '__paramNumber1' 30 | automatic Cls2#(1) cls2 = new; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_assert_future_bad.v0000644000542200017500000000147015101701376023303 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ // Inputs a, clk ); input a; input clk; global clocking @(posedge clk); endclocking assert property (@(posedge clk) 1 == 1) else $display("Future=%0d", $future_gclk(a)); assert property (@(posedge clk) 1 == 1) else $display("Future=%0d", $rising_gclk(a)); assert property (@(posedge clk) 1 == 1) else $display("Future=%0d", $falling_gclk(a)); assert property (@(posedge clk) 1 == 1) else $display("Future=%0d", $steady_gclk(a)); assert property (@(posedge clk) 1 == 1) else $display("Future=%0d", $changing_gclk(a)); initial $stop; endmodule verilator-5.042/test_regress/t/t_interface_gen8.v0000644000542200017500000000223315101701376022461 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty. // SPDX-License-Identifier: CC0-1.0 // bug998 interface intf #(parameter PARAM = 0) (); logic val; function integer func (); return 5; endfunction endinterface module t1(intf mod_intf); initial begin $display("%m %d", mod_intf.val); end endmodule module t(); //intf #(.PARAM(1)) my_intf [1:0] (); intf #(.PARAM(1)) my_intf (); generate genvar the_genvar; for (the_genvar = 0; the_genvar < 2; the_genvar++) begin : TestIf //assign my_intf[the_genvar].val = '1; //t1 t (.mod_intf(my_intf[the_genvar])); t1 t (.mod_intf(my_intf)); end endgenerate // t1 t (.mod_intf(my_intf[1])); // generate // begin : TestIf // assign my_intf[1].val = '1; // t1 t (.mod_intf(my_intf[1])); // end // endgenerate // generate // begin // assign my_intf[0].val = '1; // t1 t (.mod_intf(my_intf[0])); // end // endgenerate initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_sys_readmem_i.mem0000644000542200017500000000057715101701376022742 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test data file // // Copyright 2006 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 @4 6540004 @a 654000a 654000b 654000c verilator-5.042/test_regress/t/t_pp_defnettype_bad.out0000644000542200017500000000146615101701376023625 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_pp_defnettype_bad.v:7:1: Unsupported: `default_nettype of other than none or wire: '`default_nettype bad' 7 | `default_nettype bad_none_such | ^~~~~~~~~~~~~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_pp_defnettype_bad.v:9:1: Unsupported: Verilog optional directive not implemented: '`default_trireg_strength this_is_optional' 9 | `default_trireg_strength this_is_optional | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ %Error: t/t_pp_defnettype_bad.v:7:21: syntax error, unexpected IDENTIFIER 7 | `default_nettype bad_none_such | ^~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_dfg_peephole_off_each.py0000755000542200017500000000075315101701376024226 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap import runpy test.scenarios('vlt_all') runpy.run_path("t/t_dfg_peephole.py", globals()) verilator-5.042/test_regress/t/t_prof_timing.py0000755000542200017500000000416615101701376022312 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap import platform test.scenarios('vlt_all') test.top_filename = "t/t_prof.v" if re.search(r'clang', test.cxx_version) and 'aarch64' in platform.processor(): test.skip("Known compiler profile issues on clang aarch64") if platform.libc_ver()[0] != "glibc": test.skip("The test depends on GMON_OUT_PREFIX which is glibc-specific") # TODO below might no longer be required as configure checks for -pg if 'VERILATOR_TEST_NO_GPROF' in os.environ: test.skip("Skipping due to VERILATOR_TEST_NO_GPROF") if not test.have_coroutines: test.skip("No coroutine support") test.compile(verilator_flags2=["--stats --prof-cfuncs --binary"]) for filename in glob.glob(test.obj_dir + "/gmon.out.*"): test.unlink_ok(filename) test.setenv('GMON_OUT_PREFIX', test.obj_dir + "/gmon.out") test.execute() gmon_path = None for filename in glob.glob(test.obj_dir + "/gmon.out.*"): gmon_path = filename if not gmon_path: test.error("Profiler did not create a gmon.out") gmon_base = re.sub(r'.*[/\\]', '', gmon_path) test.run( cmd=["cd " + test.obj_dir + " && gprof " + test.vm_prefix + " " + gmon_base + " > gprof.log"], check_finished=False) test.run(cmd=[ "cd " + test.obj_dir + " && " + os.environ["VERILATOR_ROOT"] + "/bin/verilator_profcfunc gprof.log > profcfuncs.log" ], check_finished=False) test.file_grep(test.obj_dir + "/profcfuncs.log", r'Overall summary by') # Appears that GCC 11.4 has a bug whereby it doesn't trace function calls # within coroutines; CLang seems to work correctly. # test.file_grep(test.obj_dir + "/profcfuncs.log", r'VLib + VL_POWSS_QQQ') test.file_grep(test.obj_dir + "/profcfuncs.log", r'VLib + VL_WRITEF') test.file_grep(test.obj_dir + "/profcfuncs.log", r'VBlock + t_prof:') test.passes() verilator-5.042/test_regress/t/t_dpi_export_context2_bad.py0000755000542200017500000000110215101701376024571 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=["--exe", test.pli_filename], make_main=False) test.execute(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_assert_elab_p.v0000644000542200017500000000131215101701376022400 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilator lint_off WIDTH module pipe_id_match #( parameter type ID_T = logic [4:0], parameter ID_T STAGE_IDS[3:0][1:0] = '{default: 1} ); generate $info("%m %s:%0d: 4=%0d 2=%0d STAGE_IDS=%p", "test.sv", 25, 4, 2, STAGE_IDS); endgenerate endmodule module t #( parameter type ID_T = logic [4:0] ); localparam ID_T STAGE_IDS[3:0][1:0] = '{default: 5'b1}; pipe_id_match #( .ID_T(ID_T), .STAGE_IDS(STAGE_IDS) ) pipe ( .*); initial $finish; endmodule verilator-5.042/test_regress/t/t_param_type_id_bad.out0000644000542200017500000000042515101701376023566 0ustar mahmoudyfreeshell%Error: t/t_param_type_id_bad.v:9:34: Expecting a data type: 'i' 9 | class Cls #(parameter type P_T = i); | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_for_count.py0000755000542200017500000000073415101701376021770 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_ref_trace.v0000644000542200017500000000500215101701376023547 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 // Test for trace file interface aliasing typedef struct packed { integer val100; integer val200; } struct_t; // This interface is not connected to any cells interface ifc_inner(input integer cyc); integer value; endinterface interface ifc (input logic clk, input integer cyc); integer value; struct_t the_struct; ifc_inner inner (.*); endinterface module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; ifc intf_1(.*); ifc intf_2(.*); always @(*) begin intf_1.value = cyc + 1; intf_2.value = cyc + 2; end sub_struct s1 (.intf_for_struct(intf_1)); sub_struct s2 (.intf_for_struct(intf_2)); sub_check c1 (.intf_for_check(intf_1)); sub_check c2 (.intf_for_check(intf_2)); sub_all a (.intf_one(intf_1), .intf_two(intf_2)); // Intentionally longer scope name sub_all abcdefghijklmnopqrstuvwxyz (.intf_one(intf_2), .intf_two(intf_1)); always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==20) begin if (intf_1.value != 21) $stop; if (intf_2.value != 22) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module sub_struct ( ifc intf_for_struct ); always @(*) begin intf_for_struct.the_struct.val100 = intf_for_struct.value + 100; intf_for_struct.the_struct.val200 = intf_for_struct.value + 200; end endmodule module sub_check ( ifc intf_for_check ); `ifdef NO_INLINE_A //verilator no_inline_module `endif always @(posedge intf_for_check.clk) begin if (intf_for_check.the_struct.val100 != intf_for_check.value + 100) $stop; if (intf_for_check.the_struct.val200 != intf_for_check.value + 200) $stop; end endmodule module sub_all ( ifc intf_one, ifc intf_two ); `ifdef NO_INLINE_B //verilator no_inline_module `endif ifc intf_in_sub_all ( .clk(intf_one.clk), .cyc(intf_one.cyc) ); assign intf_in_sub_all.value = intf_one.value + 1000; sub_check ac1 (.intf_for_check(intf_one)); sub_check ac2 (.intf_for_check(intf_two)); sub_struct as3 (.intf_for_struct(intf_in_sub_all)); sub_check ac3 (.intf_for_check(intf_in_sub_all)); endmodule verilator-5.042/test_regress/t/t_parse_sync_bad.out0000644000542200017500000000111515101701376023114 0ustar mahmoudyfreeshell%Error: t/t_parse_sync_bad.v:19:22: syntax error, unexpected IDENTIFIER, expecting "'{" 19 | pkg::cls::defi invalid; | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_parse_sync_bad.v:25:14: syntax error, unexpected /*verilator clocker*/, expecting ',' or ';' 25 | logic clk /*verilator clocker*/ ; | ^~~~~~~~~~~~~~~~~~~~~ %Error: t/t_parse_sync_bad.v:29:1: syntax error, unexpected endmodule 29 | endmodule | ^~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_param_type5.v0000644000542200017500000000150315101701376022025 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class ParamClass #(string P = "ABC", R = "GDF"); endclass module t #(parameter int A = 0, B = 1, C = 2, type D = int, E = string); parameter bit F = 1'b0, G = 1'b1; parameter type H = int, I = string; E str1 = "abc"; I str2 = ""; initial begin automatic ParamClass param_class = new; if ($typename(B) != "int") $stop; if ($typename(C) != "int") $stop; if (str1.len() != 3) $stop; if ($typename(G) != "bit") $stop; if (str2.len() != 0) $stop; if ($typename(param_class.R) != "string") $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_flag_build_dep_bin.py0000755000542200017500000000110215101701376023530 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(v_flags2=['--build-dep-bin', 'path_to_exe']) test.file_grep(test.obj_dir + "/" + test.vm_prefix + "__ver.d", r'path_to_exe') test.passes() verilator-5.042/test_regress/t/t_display_merge.out0000644000542200017500000000216715101701376022774 0ustar mahmoudyfreeshellMerge: This should merge Merge: This should also merge f 1=1 a=top.t 1=1 1=1 b=top.t 1=1 pre t=0 t2=0 post t3=0 t4=0 t5=0 0 m t=0 t2=0 t3=0 t4=0 t5=0 t=0 t2=0 t3=0 t4=0 t5=0 mm f a=top.t b=top.t pre t=0 t2=0 post t3=0 t4=0 t5=0 0m t=0 t2=0 t3=0 t4=0 t5=0 t=0 t2=0 t3=0 t4=0 t5=0mm very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very very 11111 11111 11111 11111 *-* All Finished *-* verilator-5.042/test_regress/t/t_split_var_2_trace.out0000644000542200017500000011032215101701376023543 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $var wire 1 [" clk $end $scope module t $end $var wire 1 [" clk $end $var wire 32 \" DEPTH [31:0] $end $var wire 32 ]" WIDTH [31:0] $end $var wire 32 ^" NUMSUB [31:0] $end $var wire 8 _" in [7:0] $end $var wire 8 - out[0] [7:0] $end $var wire 8 . out[1] [7:0] $end $var wire 8 / out[2] [7:0] $end $var wire 8 0 out[3] [7:0] $end $var wire 8 1 out[4] [7:0] $end $var wire 8 2 out[5] [7:0] $end $var wire 8 3 out[6] [7:0] $end $var wire 8 4 out[7] [7:0] $end $var wire 8 5 out[8] [7:0] $end $var wire 8 6 through_tmp [7:0] $end $var wire 3 h shift [2:0] $end $var wire 31 i hash_input_d [31:1] $end $var wire 31 j hash_input_a [1:31] $end $var wire 9 k hash_output_dd [8:0] $end $var wire 9 l hash_output_da [8:0] $end $var wire 9 m hash_output_ad [8:0] $end $var wire 9 n hash_output_aa [8:0] $end $var wire 64 `" expc [63:0] $end $scope module always_block $end $var wire 1 o failed $end $var wire 9 p hash_expected [8:0] $end $scope module unnamedblk1 $end $var wire 32 q i [31:0] $end $upscope $end $upscope $end $scope module delay0 $end $var wire 1 [" clk $end $var wire 1 b" unpack_sig0(10) $end $var wire 1 c" unpack_sig0(11) $end $var wire 1 d" unpack_sig0(12) $end $var wire 1 r unpack_sig0(13) $end $var wire 1 s unpack_sig0(14) $end $var wire 1 t unpack_sig0(15) $end $var wire 1 u unpack_sig0(16) $end $var wire 1 v unpack_sig1(13) $end $var wire 1 w unpack_sig1(14) $end $var wire 1 x unpack_sig1(15) $end $var wire 1 y unpack_sig1(16) $end $var wire 1 e" unpack_sig2(10) $end $var wire 1 f" unpack_sig2(11) $end $var wire 1 g" unpack_sig2(12) $end $var wire 1 z unpack_sig2(13) $end $var wire 1 { unpack_sig2(14) $end $var wire 1 | unpack_sig2(15) $end $var wire 1 } unpack_sig2(16) $end $var wire 1 ~ unpack_sig3(13) $end $var wire 1 !! unpack_sig3(14) $end $var wire 1 "! unpack_sig3(15) $end $var wire 1 #! unpack_sig3(16) $end $var wire 32 $! c [31:0] $end $upscope $end $scope module i_hash_aa $end $var wire 31 j i [1:31] $end $var wire 9 n o [8:0] $end $upscope $end $scope module i_hash_ad $end $var wire 31 i i [1:31] $end $var wire 9 m o [8:0] $end $upscope $end $scope module i_hash_da $end $var wire 31 j i [31:1] $end $var wire 9 l o [8:0] $end $upscope $end $scope module i_hash_dd $end $var wire 31 i i [31:1] $end $var wire 9 k o [8:0] $end $upscope $end $scope module i_t_array_rev $end $var wire 1 [" clk $end $var wire 32 h" cyc [31:0] $end $var wire 1 # arrd(0) $end $var wire 1 $ arrd(1) $end $var wire 1 % y0 $end $var wire 1 & y1 $end $var wire 1 %! localbkw(0) $end $var wire 1 &! localbkw(1) $end $scope module arr_rev_u $end $var wire 1 ' arrbkw[0] $end $var wire 1 ( arrbkw[1] $end $var wire 1 % y0 $end $var wire 1 & y1 $end $upscope $end $upscope $end $scope module i_var_decl_with_init $end $var wire 32 ) var0 [-1:30] $end $var wire 32 * var2 [-1:30] $end $var wire 32 + var1 [30:-1] $end $var wire 32 , var3 [30:-1] $end $upscope $end $scope module shifter0 $end $var wire 32 \" DEPTH [31:0] $end $var wire 32 ]" WIDTH [31:0] $end $var wire 8 _" in [7:0] $end $var wire 3 h shift [2:0] $end $var wire 8 '! out [7:0] $end $var wire 32 i" OFFSET [31:0] $end $var wire 8 (! tmp(-1) [7:0] $end $var wire 8 )! tmp(-2) [7:0] $end $var wire 8 _" tmp(-3) [7:0] $end $var wire 8 '! tmp(0) [7:0] $end $upscope $end $scope module shifter1 $end $var wire 32 \" DEPTH [31:0] $end $var wire 32 ]" WIDTH [31:0] $end $var wire 8 _" in [7:0] $end $var wire 3 h shift [2:0] $end $var wire 8 *! out [7:0] $end $var wire 32 i" OFFSET [31:0] $end $var wire 8 +! tmp(-1) [7:0] $end $var wire 8 )! tmp(-2) [7:0] $end $var wire 8 _" tmp(-3) [7:0] $end $var wire 8 *! tmp(0) [7:0] $end $upscope $end $scope module shifter2 $end $var wire 32 \" DEPTH [31:0] $end $var wire 32 ]" WIDTH [31:0] $end $var wire 8 _" in [7:0] $end $var wire 3 h shift [2:0] $end $var wire 8 ,! out [7:0] $end $var wire 32 j" OFFSET [31:0] $end $var wire 8 _" tmp(1) [7:0] $end $var wire 8 -! tmp(2) [7:0] $end $var wire 8 .! tmp(3) [7:0] $end $var wire 8 ,! tmp(4) [7:0] $end $upscope $end $scope module shifter3 $end $var wire 32 \" DEPTH [31:0] $end $var wire 32 ]" WIDTH [31:0] $end $var wire 8 _" in [7:0] $end $var wire 3 h shift [2:0] $end $var wire 8 7 out [7:0] $end $var wire 32 j" OFFSET [31:0] $end $var wire 32 \" N [31:0] $end $var wire 8 _" tmp0(1)(1) [7:0] $end $var wire 8 _" tmp0(1)(2) [7:0] $end $var wire 8 _" tmp0(1)(3) [7:0] $end $var wire 8 )! tmp0(2)(1) [7:0] $end $var wire 8 )! tmp0(2)(2) [7:0] $end $var wire 8 )! tmp0(2)(3) [7:0] $end $var wire 8 /! tmp0(3)(1) [7:0] $end $var wire 8 0! tmp0(3)(2) [7:0] $end $var wire 8 1! tmp0(3)(3) [7:0] $end $var wire 8 2! tmp0(4)(1) [7:0] $end $var wire 8 3! tmp0(4)(2) [7:0] $end $var wire 8 4! tmp0(4)(3) [7:0] $end $var wire 8 5! tmp1(1)(1) [7:0] $end $var wire 8 6! tmp1(1)(2) [7:0] $end $var wire 8 7! tmp1(1)(3) [7:0] $end $var wire 8 8! tmp1(2)(1) [7:0] $end $var wire 8 9! tmp1(2)(2) [7:0] $end $var wire 8 :! tmp1(2)(3) [7:0] $end $var wire 8 ;! tmp1(3)(1) [7:0] $end $var wire 8 ! tmp1(4)(1) [7:0] $end $var wire 8 ?! tmp1(4)(2) [7:0] $end $var wire 8 @! tmp1(4)(3) [7:0] $end $var wire 8 A! tmp2[1][1] [7:0] $end $var wire 8 B! tmp2[1][2] [7:0] $end $var wire 8 C! tmp2[1][3] [7:0] $end $var wire 8 D! tmp2[2][1] [7:0] $end $var wire 8 E! tmp2[2][2] [7:0] $end $var wire 8 F! tmp2[2][3] [7:0] $end $var wire 8 G! tmp2[3][1] [7:0] $end $var wire 8 H! tmp2[3][2] [7:0] $end $var wire 8 I! tmp2[3][3] [7:0] $end $var wire 8 J! tmp2[4][1] [7:0] $end $var wire 8 K! tmp2[4][2] [7:0] $end $var wire 8 L! tmp2[4][3] [7:0] $end $var wire 8 M! tmp3(1)(1) [7:0] $end $var wire 8 N! tmp3(1)(2) [7:0] $end $var wire 8 O! tmp3(1)(3) [7:0] $end $var wire 8 P! tmp3(2)(1) [7:0] $end $var wire 8 Q! tmp3(2)(2) [7:0] $end $var wire 8 R! tmp3(2)(3) [7:0] $end $var wire 8 S! tmp3(3)(1) [7:0] $end $var wire 8 T! tmp3(3)(2) [7:0] $end $var wire 8 U! tmp3(3)(3) [7:0] $end $var wire 8 V! tmp3(4)(1) [7:0] $end $var wire 8 W! tmp3(4)(2) [7:0] $end $var wire 8 X! tmp3(4)(3) [7:0] $end $var wire 8 Y! tmp4(1)(1) [7:0] $end $var wire 8 Z! tmp4(1)(2) [7:0] $end $var wire 8 [! tmp4(1)(3) [7:0] $end $var wire 8 \! tmp4(2)(1) [7:0] $end $var wire 8 ]! tmp4(2)(2) [7:0] $end $var wire 8 ^! tmp4(2)(3) [7:0] $end $var wire 8 _! tmp4(3)(1) [7:0] $end $var wire 8 `! tmp4(3)(2) [7:0] $end $var wire 8 a! tmp4(3)(3) [7:0] $end $var wire 8 b! tmp4(4)(1) [7:0] $end $var wire 8 c! tmp4(4)(2) [7:0] $end $var wire 8 d! tmp4(4)(3) [7:0] $end $var wire 8 e! tmp5[1][1] [7:0] $end $var wire 8 f! tmp5[1][2] [7:0] $end $var wire 8 g! tmp5[1][3] [7:0] $end $var wire 8 h! tmp5[2][1] [7:0] $end $var wire 8 i! tmp5[2][2] [7:0] $end $var wire 8 j! tmp5[2][3] [7:0] $end $var wire 8 k! tmp5[3][1] [7:0] $end $var wire 8 l! tmp5[3][2] [7:0] $end $var wire 8 m! tmp5[3][3] [7:0] $end $var wire 8 n! tmp5[4][1] [7:0] $end $var wire 8 o! tmp5[4][2] [7:0] $end $var wire 8 p! tmp5[4][3] [7:0] $end $var wire 8 q! tmp6(1)(1) [7:0] $end $var wire 8 r! tmp6(1)(2) [7:0] $end $var wire 8 s! tmp6(1)(3) [7:0] $end $var wire 8 t! tmp6(2)(1) [7:0] $end $var wire 8 u! tmp6(2)(2) [7:0] $end $var wire 8 v! tmp6(2)(3) [7:0] $end $var wire 8 w! tmp6(3)(1) [7:0] $end $var wire 8 x! tmp6(3)(2) [7:0] $end $var wire 8 y! tmp6(3)(3) [7:0] $end $var wire 8 z! tmp6(4)(1) [7:0] $end $var wire 8 {! tmp6(4)(2) [7:0] $end $var wire 8 |! tmp6(4)(3) [7:0] $end $var wire 8 }! tmp7(2)(1) [7:0] $end $var wire 8 ~! tmp7(2)(2) [7:0] $end $var wire 8 !" tmp7(2)(3) [7:0] $end $var wire 8 "" tmp7(3)(1) [7:0] $end $var wire 8 #" tmp7(3)(2) [7:0] $end $var wire 8 $" tmp7(3)(3) [7:0] $end $var wire 8 %" tmp7(4)(1) [7:0] $end $var wire 8 &" tmp7(4)(2) [7:0] $end $var wire 8 '" tmp7(4)(3) [7:0] $end $var wire 8 (" tmp7(5)(1) [7:0] $end $var wire 8 )" tmp7(5)(2) [7:0] $end $var wire 8 *" tmp7(5)(3) [7:0] $end $var wire 8 k" tmp8(0)(1) [7:0] $end $var wire 8 l" tmp8(0)(2) [7:0] $end $var wire 8 m" tmp8(0)(3) [7:0] $end $var wire 8 n" tmp8(1)(1) [7:0] $end $var wire 8 o" tmp8(1)(2) [7:0] $end $var wire 8 p" tmp8(1)(3) [7:0] $end $var wire 8 +" tmp8(2)(1) [7:0] $end $var wire 8 ," tmp8(2)(2) [7:0] $end $var wire 8 -" tmp8(2)(3) [7:0] $end $var wire 8 ." tmp8(3)(1) [7:0] $end $var wire 8 /" tmp8(3)(2) [7:0] $end $var wire 8 0" tmp8(3)(3) [7:0] $end $var wire 8 1" tmp8(4)(1) [7:0] $end $var wire 8 2" tmp8(4)(2) [7:0] $end $var wire 8 3" tmp8(4)(3) [7:0] $end $var wire 8 4" tmp8(5)(1) [7:0] $end $var wire 8 5" tmp8(5)(2) [7:0] $end $var wire 8 6" tmp8(5)(3) [7:0] $end $var wire 8 q" tmp8(6)(1) [7:0] $end $var wire 8 r" tmp8(6)(2) [7:0] $end $var wire 8 s" tmp8(6)(3) [7:0] $end $var wire 8 t" tmp8(7)(1) [7:0] $end $var wire 8 u" tmp8(7)(2) [7:0] $end $var wire 8 v" tmp8(7)(3) [7:0] $end $var wire 8 7" tmp9(4)(1) [7:0] $end $var wire 8 8" tmp9(4)(2) [7:0] $end $var wire 8 9" tmp9(4)(3) [7:0] $end $var wire 8 :" tmp9(5)(1) [7:0] $end $var wire 8 ;" tmp9(5)(2) [7:0] $end $var wire 8 <" tmp9(5)(3) [7:0] $end $var wire 8 =" tmp9(6)(1) [7:0] $end $var wire 8 >" tmp9(6)(2) [7:0] $end $var wire 8 ?" tmp9(6)(3) [7:0] $end $var wire 8 @" tmp9(7)(1) [7:0] $end $var wire 8 A" tmp9(7)(2) [7:0] $end $var wire 8 B" tmp9(7)(3) [7:0] $end $var wire 8 C" tmp10(1)(1) [7:0] $end $var wire 8 D" tmp10(1)(2) [7:0] $end $var wire 8 E" tmp10(1)(3) [7:0] $end $var wire 8 F" tmp10(2)(1) [7:0] $end $var wire 8 G" tmp10(2)(2) [7:0] $end $var wire 8 H" tmp10(2)(3) [7:0] $end $var wire 8 I" tmp10(3)(1) [7:0] $end $var wire 8 J" tmp10(3)(2) [7:0] $end $var wire 8 K" tmp10(3)(3) [7:0] $end $var wire 8 L" tmp10(4)(1) [7:0] $end $var wire 8 M" tmp10(4)(2) [7:0] $end $var wire 8 N" tmp10(4)(3) [7:0] $end $var wire 8 8 tmp12(-1)(1)(1) [7:0] $end $var wire 8 9 tmp12(-1)(1)(2) [7:0] $end $var wire 8 : tmp12(-1)(1)(3) [7:0] $end $var wire 8 ; tmp12(-1)(2)(1) [7:0] $end $var wire 8 < tmp12(-1)(2)(2) [7:0] $end $var wire 8 = tmp12(-1)(2)(3) [7:0] $end $var wire 8 > tmp12(-1)(3)(1) [7:0] $end $var wire 8 ? tmp12(-1)(3)(2) [7:0] $end $var wire 8 @ tmp12(-1)(3)(3) [7:0] $end $var wire 8 7 tmp12(-1)(4)(1) [7:0] $end $var wire 8 A tmp12(-1)(4)(2) [7:0] $end $var wire 8 B tmp12(-1)(4)(3) [7:0] $end $var wire 8 C tmp12(0)(1)(1) [7:0] $end $var wire 8 D tmp12(0)(1)(2) [7:0] $end $var wire 8 E tmp12(0)(1)(3) [7:0] $end $var wire 8 F tmp12(0)(2)(1) [7:0] $end $var wire 8 G tmp12(0)(2)(2) [7:0] $end $var wire 8 H tmp12(0)(2)(3) [7:0] $end $var wire 8 I tmp12(0)(3)(1) [7:0] $end $var wire 8 J tmp12(0)(3)(2) [7:0] $end $var wire 8 K tmp12(0)(3)(3) [7:0] $end $var wire 8 L tmp12(0)(4)(1) [7:0] $end $var wire 8 M tmp12(0)(4)(2) [7:0] $end $var wire 8 N tmp12(0)(4)(3) [7:0] $end $var wire 8 w" tmp13(1)(1) [7:0] $end $var wire 8 x" tmp13(1)(2) [7:0] $end $var wire 8 y" tmp13(1)(3) [7:0] $end $var wire 8 z" tmp13(2)(1) [7:0] $end $var wire 8 {" tmp13(2)(2) [7:0] $end $var wire 8 |" tmp13(2)(3) [7:0] $end $var wire 8 }" tmp13(3)(1) [7:0] $end $var wire 8 ~" tmp13(3)(2) [7:0] $end $var wire 8 !# tmp13(3)(3) [7:0] $end $var wire 8 "# tmp13(4)(1) [7:0] $end $var wire 8 ## tmp13(4)(2) [7:0] $end $var wire 8 $# tmp13(4)(3) [7:0] $end $upscope $end $scope module shifter4 $end $var wire 32 \" DEPTH [31:0] $end $var wire 32 ]" WIDTH [31:0] $end $var wire 8 _" in [7:0] $end $var wire 3 h shift [2:0] $end $var wire 8 O" out [7:0] $end $var wire 32 %# OFFSET [31:0] $end $var wire 32 &# tmp(2) [31:0] $end $var wire 32 P" tmp(3) [31:0] $end $var wire 32 Q" tmp(4) [31:0] $end $var wire 32 R" tmp(5) [31:0] $end $var wire 24 '# PAD [23:0] $end $upscope $end $scope module shifter5 $end $var wire 32 \" DEPTH [31:0] $end $var wire 32 ]" WIDTH [31:0] $end $var wire 8 _" in [7:0] $end $var wire 3 h shift [2:0] $end $var wire 8 S" out [7:0] $end $var wire 32 (# OFFSET [31:0] $end $var wire 32 T" tmp [31:0] $end $upscope $end $scope module shifter6 $end $var wire 32 \" DEPTH [31:0] $end $var wire 32 ]" WIDTH [31:0] $end $var wire 8 _" in [7:0] $end $var wire 3 h shift [2:0] $end $var wire 8 U" out [7:0] $end $var wire 32 (# OFFSET [31:0] $end $var wire 32 V" tmp [31:0] $end $upscope $end $scope module shifter7 $end $var wire 32 \" DEPTH [31:0] $end $var wire 32 ]" WIDTH [31:0] $end $var wire 8 _" in [7:0] $end $var wire 3 h shift [2:0] $end $var wire 8 W" out [7:0] $end $var wire 32 X" tmp [31:0] $end $upscope $end $scope module shifter8 $end $var wire 32 \" DEPTH [31:0] $end $var wire 32 ]" WIDTH [31:0] $end $var wire 8 _" in [7:0] $end $var wire 3 h shift [2:0] $end $var wire 8 Y" out [7:0] $end $var wire 32 Z" tmp [0:31] $end $upscope $end $scope module though0 $end $var wire 32 ]" WIDTH [31:0] $end $var wire 8 O in [7:0] $end $var wire 8 6 out [7:0] $end $var wire 1 P unpack_tmp(0) $end $var wire 1 Q unpack_tmp(1) $end $var wire 1 R unpack_tmp(2) $end $var wire 1 S unpack_tmp(3) $end $var wire 1 T unpack_tmp(4) $end $var wire 1 U unpack_tmp(5) $end $var wire 1 V unpack_tmp(6) $end $var wire 1 W unpack_tmp(7) $end $scope module i_pack2unpack $end $var wire 32 ]" WIDTH [31:0] $end $var wire 8 O in [7:0] $end $var wire 1 X out[0] $end $var wire 1 Y out[1] $end $var wire 1 Z out[2] $end $var wire 1 [ out[3] $end $var wire 1 \ out[4] $end $var wire 1 ] out[5] $end $var wire 1 ^ out[6] $end $var wire 1 _ out[7] $end $upscope $end $scope module i_unpack2pack $end $var wire 32 ]" WIDTH [31:0] $end $var wire 1 ` in[0] $end $var wire 1 a in[1] $end $var wire 1 b in[2] $end $var wire 1 c in[3] $end $var wire 1 d in[4] $end $var wire 1 e in[5] $end $var wire 1 f in[6] $end $var wire 1 g in[7] $end $var wire 8 6 out [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 1# 0$ 0% 1& 0' 1( b00000001001000110100010101100111 ) b00100000000000000000000000000000 * b00000001001000110100000000100111 + b00000000000000000000000000000011 , b10001110 - b10001110 . b10001110 / b10001110 0 b10001110 1 b10001110 2 b10001110 3 b10001110 4 b10001110 5 b10001110 6 b10001110 7 b10001110 8 b10001110 9 b10001110 : b10001110 ; b10001110 < b10001110 = b10001110 > b10001110 ? b10001110 @ b10001110 A b10001110 B b10001110 C b10001110 D b10001110 E b10001110 F b10001110 G b10001110 H b10001110 I b10001110 J b10001110 K b10001110 L b10001110 M b10001110 N b10001110 O 1P 0Q 0R 0S 1T 1U 1V 0W 0X 1Y 1Z 1[ 0\ 0] 0^ 1_ 0` 1a 1b 1c 0d 0e 0f 1g b000 h b0110010000100001010101111001101 i b0110010000100001010101111001101 j b100011100 k b100011100 l b100011100 m b100011100 n 0o b000000000 p b00000000000000000000000000000000 q 0r 0s 0t 0u 0v 0w 0x 0y 0z 0{ 0| 0} 0~ 0!! 0"! 0#! b00000000000000000000000000000000 $! 0%! 0&! b10001110 '! b10001110 (! b10001110 )! b10001110 *! b10001110 +! b10001110 ,! b10001110 -! b10001110 .! b10001110 /! b10001110 0! b10001110 1! b10001110 2! b10001110 3! b10001110 4! b10001110 5! b10001110 6! b10001110 7! b10001110 8! b10001110 9! b10001110 :! b10001110 ;! b10001110 ! b10001110 ?! b10001110 @! b10001110 A! b10001110 B! b10001110 C! b10001110 D! b10001110 E! b10001110 F! b10001110 G! b10001110 H! b10001110 I! b10001110 J! b10001110 K! b10001110 L! b10001110 M! b10001110 N! b10001110 O! b10001110 P! b10001110 Q! b10001110 R! b10001110 S! b10001110 T! b10001110 U! b10001110 V! b10001110 W! b10001110 X! b10001110 Y! b10001110 Z! b10001110 [! b10001110 \! b10001110 ]! b10001110 ^! b10001110 _! b10001110 `! b10001110 a! b10001110 b! b10001110 c! b10001110 d! b10001110 e! b10001110 f! b10001110 g! b10001110 h! b10001110 i! b10001110 j! b10001110 k! b10001110 l! b10001110 m! b10001110 n! b10001110 o! b10001110 p! b10001110 q! b10001110 r! b10001110 s! b10001110 t! b10001110 u! b10001110 v! b10001110 w! b10001110 x! b10001110 y! b10001110 z! b10001110 {! b10001110 |! b10001110 }! b10001110 ~! b10001110 !" b10001110 "" b10001110 #" b10001110 $" b10001110 %" b10001110 &" b10001110 '" b10001110 (" b10001110 )" b10001110 *" b10001110 +" b10001110 ," b10001110 -" b10001110 ." b10001110 /" b10001110 0" b10001110 1" b10001110 2" b10001110 3" b10001110 4" b10001110 5" b10001110 6" b10001110 7" b10001110 8" b10001110 9" b10001110 :" b10001110 ;" b10001110 <" b10001110 =" b10001110 >" b10001110 ?" b10001110 @" b10001110 A" b10001110 B" b10001110 C" b10001110 D" b10001110 E" b10001110 F" b10001110 G" b10001110 H" b10001110 I" b10001110 J" b10001110 K" b10001110 L" b10001110 M" b10001110 N" b10001110 O" b00000000000000000000000010001110 P" b00000000000000000000000010001110 Q" b00000000000000000000000010001110 R" b10001110 S" b10001110100011101000111010001110 T" b10001110 U" b10001110100011101000111010001110 V" b10001110 W" b10001110100011101000111010001110 X" b10001110 Y" b10001110100011101000111010001110 Z" 0[" b00000000000000000000000000000011 \" b00000000000000000000000000001000 ]" b00000000000000000000000000001001 ^" b10001110 _" b1000111001000111101000111101000111101000011101000011101000011101 `" 0b" 0c" 0d" 0e" 0f" 0g" b00000000000000000000000000000000 h" b11111111111111111111111111111101 i" b00000000000000000000000000000001 j" b00000000 k" b00000000 l" b00000000 m" b00000000 n" b00000000 o" b00000000 p" b00000000 q" b00000000 r" b00000000 s" b00000000 t" b00000000 u" b00000000 v" b00000000 w" b00000000 x" b00000000 y" b00000000 z" b00000000 {" b00000000 |" b00000000 }" b00000000 ~" b00000000 !# b00000000 "# b00000000 ## b00000000 $# b00000000000000000000000000000010 %# b00000000000000000000000010001110 &# b000000000000000000000000 '# b11111111111111111111111111111110 (# #10 b01000111 - b01000111 . b01000111 / b01000111 0 b01000111 1 b01000111 2 b01000111 3 b01000111 4 b01000111 5 b01000111 6 b01000111 7 b01000111 ; b01000111 < b01000111 = b01000111 > b01000111 ? b01000111 @ b01000111 A b01000111 B b01000111 F b01000111 G b01000111 H b01000111 I b01000111 J b01000111 K b01000111 L b01000111 M b01000111 N b01000111 O 0P 1Q 0T 1W 1X 0[ 1^ 0_ 1` 0c 1f 0g b001 h b1011001000010000101010111100110 i b1011001000010000101010111100110 j b010001110 k b010001110 l b010001110 m b010001110 n b100011100 p b00000000000000000000000000001001 q 1r 1v 1z 1~ b00000000000000000000000000000001 $! 1&! b01000111 '! b01000111 (! b01000111 )! b01000111 *! b01000111 +! b01000111 ,! b01000111 -! b01000111 .! b01000111 /! b01000111 0! b01000111 1! b01000111 2! b01000111 3! b01000111 4! b01000111 8! b01000111 9! b01000111 :! b01000111 ;! b01000111 ! b01000111 ?! b01000111 @! b01000111 D! b01000111 E! b01000111 F! b01000111 G! b01000111 H! b01000111 I! b01000111 J! b01000111 K! b01000111 L! b01000111 P! b01000111 Q! b01000111 R! b01000111 S! b01000111 T! b01000111 U! b01000111 V! b01000111 W! b01000111 X! b01000111 \! b01000111 ]! b01000111 ^! b01000111 _! b01000111 `! b01000111 a! b01000111 b! b01000111 c! b01000111 d! b01000111 h! b01000111 i! b01000111 j! b01000111 k! b01000111 l! b01000111 m! b01000111 n! b01000111 o! b01000111 p! b01000111 t! b01000111 u! b01000111 v! b01000111 w! b01000111 x! b01000111 y! b01000111 z! b01000111 {! b01000111 |! b01000111 "" b01000111 #" b01000111 $" b01000111 %" b01000111 &" b01000111 '" b01000111 (" b01000111 )" b01000111 *" b01000111 ." b01000111 /" b01000111 0" b01000111 1" b01000111 2" b01000111 3" b01000111 4" b01000111 5" b01000111 6" b01000111 :" b01000111 ;" b01000111 <" b01000111 =" b01000111 >" b01000111 ?" b01000111 @" b01000111 A" b01000111 B" b01000111 F" b01000111 G" b01000111 H" b01000111 I" b01000111 J" b01000111 K" b01000111 L" b01000111 M" b01000111 N" b01000111 O" b00000000000000000000000001000111 P" b00000000000000000000000001000111 Q" b00000000000000000000000001000111 R" b01000111 S" b10001110010001110100011101000111 T" b01000111 U" b10001110010001110100011101000111 V" b01000111 W" b10001110010001110100011101000111 X" b01000111 Y" b10001110010001110100011101000111 Z" 1[" #15 0[" #20 b10100011 - b10100011 . b10100011 / b10100011 0 b10100011 1 b10100011 2 b10100011 3 b10100011 4 b10100011 5 b10100011 6 b10100011 7 b10001110 ; b10001110 < b10001110 = b10100011 > b10100011 ? b10100011 @ b10100011 A b10100011 B b10001110 F b10001110 G b10001110 H b10100011 I b10100011 J b10100011 K b10100011 L b10100011 M b10100011 N b10100011 O 1P 0Q 1R 0U 0Z 1] 0^ 1_ 0b 1e 0f 1g b010 h b0101100100001000010101011110011 i b0101100100001000010101011110011 j b101000111 k b101000111 l b101000111 m b101000111 n b010001110 p 1s 1w 1{ 1!! b00000000000000000000000000000010 $! b10100011 '! b10100011 (! b10001110 )! b10100011 *! b10100011 +! b10100011 ,! b10001110 -! b10100011 .! b10100011 /! b10100011 0! b10100011 1! b10100011 2! b10100011 3! b10100011 4! b10001110 8! b10001110 9! b10001110 :! b10100011 ;! b10100011 ! b10100011 ?! b10100011 @! b10001110 D! b10001110 E! b10001110 F! b10100011 G! b10100011 H! b10100011 I! b10100011 J! b10100011 K! b10100011 L! b10001110 P! b10001110 Q! b10001110 R! b10100011 S! b10100011 T! b10100011 U! b10100011 V! b10100011 W! b10100011 X! b10001110 \! b10001110 ]! b10001110 ^! b10100011 _! b10100011 `! b10100011 a! b10100011 b! b10100011 c! b10100011 d! b10001110 h! b10001110 i! b10001110 j! b10100011 k! b10100011 l! b10100011 m! b10100011 n! b10100011 o! b10100011 p! b10001110 t! b10001110 u! b10001110 v! b10100011 w! b10100011 x! b10100011 y! b10100011 z! b10100011 {! b10100011 |! b10001110 "" b10001110 #" b10001110 $" b10100011 %" b10100011 &" b10100011 '" b10100011 (" b10100011 )" b10100011 *" b10001110 ." b10001110 /" b10001110 0" b10100011 1" b10100011 2" b10100011 3" b10100011 4" b10100011 5" b10100011 6" b10001110 :" b10001110 ;" b10001110 <" b10100011 =" b10100011 >" b10100011 ?" b10100011 @" b10100011 A" b10100011 B" b10001110 F" b10001110 G" b10001110 H" b10100011 I" b10100011 J" b10100011 K" b10100011 L" b10100011 M" b10100011 N" b10100011 O" b00000000000000000000000010001110 P" b00000000000000000000000010100011 Q" b00000000000000000000000010100011 R" b10100011 S" b10001110100011101010001110100011 T" b10100011 U" b10001110100011101010001110100011 V" b10100011 W" b10001110100011101010001110100011 X" b10100011 Y" b10001110100011101010001110100011 Z" 1[" #25 0[" #30 b11010001 - b11010001 . b11010001 / b11010001 0 b11010001 1 b11010001 2 b11010001 3 b11010001 4 b11010001 5 b11010001 6 b11010001 7 b01000111 ; b01000111 < b01000111 = b11010001 > b11010001 ? b11010001 @ b11010001 A b11010001 B b01000111 F b01000111 G b01000111 H b11010001 I b11010001 J b11010001 K b11010001 L b11010001 M b11010001 N b11010001 O 1Q 0R 1S 0V 0Y 1\ 0] 1^ 0a 1d 0e 1f b011 h b1010110010000100001010101111001 i b1010110010000100001010101111001 j b110100011 k b110100011 l b110100011 m b110100011 n b101000111 p 1t 1x 1| 1"! b00000000000000000000000000000011 $! b11010001 '! b11010001 (! b01000111 )! b11010001 *! b11010001 +! b11010001 ,! b01000111 -! b11010001 .! b11010001 /! b11010001 0! b11010001 1! b11010001 2! b11010001 3! b11010001 4! b01000111 8! b01000111 9! b01000111 :! b11010001 ;! b11010001 ! b11010001 ?! b11010001 @! b01000111 D! b01000111 E! b01000111 F! b11010001 G! b11010001 H! b11010001 I! b11010001 J! b11010001 K! b11010001 L! b01000111 P! b01000111 Q! b01000111 R! b11010001 S! b11010001 T! b11010001 U! b11010001 V! b11010001 W! b11010001 X! b01000111 \! b01000111 ]! b01000111 ^! b11010001 _! b11010001 `! b11010001 a! b11010001 b! b11010001 c! b11010001 d! b01000111 h! b01000111 i! b01000111 j! b11010001 k! b11010001 l! b11010001 m! b11010001 n! b11010001 o! b11010001 p! b01000111 t! b01000111 u! b01000111 v! b11010001 w! b11010001 x! b11010001 y! b11010001 z! b11010001 {! b11010001 |! b01000111 "" b01000111 #" b01000111 $" b11010001 %" b11010001 &" b11010001 '" b11010001 (" b11010001 )" b11010001 *" b01000111 ." b01000111 /" b01000111 0" b11010001 1" b11010001 2" b11010001 3" b11010001 4" b11010001 5" b11010001 6" b01000111 :" b01000111 ;" b01000111 <" b11010001 =" b11010001 >" b11010001 ?" b11010001 @" b11010001 A" b11010001 B" b01000111 F" b01000111 G" b01000111 H" b11010001 I" b11010001 J" b11010001 K" b11010001 L" b11010001 M" b11010001 N" b11010001 O" b00000000000000000000000001000111 P" b00000000000000000000000011010001 Q" b00000000000000000000000011010001 R" b11010001 S" b10001110010001111101000111010001 T" b11010001 U" b10001110010001111101000111010001 V" b11010001 W" b10001110010001111101000111010001 X" b11010001 Y" b10001110010001111101000111010001 Z" 1[" #35 0[" #40 b11101000 - b11101000 . b11101000 / b11101000 0 b11101000 1 b11101000 2 b11101000 3 b11101000 4 b11101000 5 b11101000 6 b11101000 7 b10001110 ; b10001110 < b10001110 = b10001110 > b10001110 ? b10001110 @ b11101000 A b11101000 B b10001110 F b10001110 G b10001110 H b10001110 I b10001110 J b10001110 K b11101000 L b11101000 M b11101000 N b11101000 O 1R 0S 1T 0W 0X 1[ 0\ 1] 0` 1c 0d 1e b100 h b1101011001000010000101010111100 i b1101011001000010000101010111100 j b011010001 k b011010001 l b011010001 m b011010001 n b110100011 p 1u 1y 1} 1#! b00000000000000000000000000000100 $! b11101000 '! b10001110 (! b10001110 )! b11101000 *! b10001110 +! b11101000 ,! b10001110 -! b10001110 .! b10001110 /! b10001110 0! b10001110 1! b11101000 2! b11101000 3! b11101000 4! b10001110 8! b10001110 9! b10001110 :! b10001110 ;! b10001110 ! b11101000 ?! b11101000 @! b10001110 D! b10001110 E! b10001110 F! b10001110 G! b10001110 H! b10001110 I! b11101000 J! b11101000 K! b11101000 L! b10001110 P! b10001110 Q! b10001110 R! b10001110 S! b10001110 T! b10001110 U! b11101000 V! b11101000 W! b11101000 X! b10001110 \! b10001110 ]! b10001110 ^! b10001110 _! b10001110 `! b10001110 a! b11101000 b! b11101000 c! b11101000 d! b10001110 h! b10001110 i! b10001110 j! b10001110 k! b10001110 l! b10001110 m! b11101000 n! b11101000 o! b11101000 p! b10001110 t! b10001110 u! b10001110 v! b10001110 w! b10001110 x! b10001110 y! b11101000 z! b11101000 {! b11101000 |! b10001110 "" b10001110 #" b10001110 $" b10001110 %" b10001110 &" b10001110 '" b11101000 (" b11101000 )" b11101000 *" b10001110 ." b10001110 /" b10001110 0" b10001110 1" b10001110 2" b10001110 3" b11101000 4" b11101000 5" b11101000 6" b10001110 :" b10001110 ;" b10001110 <" b10001110 =" b10001110 >" b10001110 ?" b11101000 @" b11101000 A" b11101000 B" b10001110 F" b10001110 G" b10001110 H" b10001110 I" b10001110 J" b10001110 K" b11101000 L" b11101000 M" b11101000 N" b11101000 O" b00000000000000000000000010001110 P" b00000000000000000000000010001110 Q" b00000000000000000000000011101000 R" b11101000 S" b10001110100011101000111011101000 T" b11101000 U" b10001110100011101000111011101000 V" b11101000 W" b10001110100011101000111011101000 X" b11101000 Y" b10001110100011101000111011101000 Z" 1[" #45 0[" #50 b01110100 - b01110100 . b01110100 / b01110100 0 b01110100 1 b01110100 2 b01110100 3 b01110100 4 b01110100 5 b01110100 6 b01110100 7 b01000111 ; b01000111 < b01000111 = b01000111 > b01000111 ? b01000111 @ b01110100 A b01110100 B b01000111 F b01000111 G b01000111 H b01000111 I b01000111 J b01000111 K b01110100 L b01110100 M b01110100 N b01110100 O 0P 1S 0T 1U 1Z 0[ 1\ 0_ 1b 0c 1d 0g b101 h b0110101100100001000010101011110 i b0110101100100001000010101011110 j b001101000 k b001101000 l b001101000 m b001101000 n b011010001 p b00000000000000000000000000000101 $! b01110100 '! b01000111 (! b01000111 )! b01110100 *! b01000111 +! b01110100 ,! b01000111 -! b01000111 .! b01000111 /! b01000111 0! b01000111 1! b01110100 2! b01110100 3! b01110100 4! b01000111 8! b01000111 9! b01000111 :! b01000111 ;! b01000111 ! b01110100 ?! b01110100 @! b01000111 D! b01000111 E! b01000111 F! b01000111 G! b01000111 H! b01000111 I! b01110100 J! b01110100 K! b01110100 L! b01000111 P! b01000111 Q! b01000111 R! b01000111 S! b01000111 T! b01000111 U! b01110100 V! b01110100 W! b01110100 X! b01000111 \! b01000111 ]! b01000111 ^! b01000111 _! b01000111 `! b01000111 a! b01110100 b! b01110100 c! b01110100 d! b01000111 h! b01000111 i! b01000111 j! b01000111 k! b01000111 l! b01000111 m! b01110100 n! b01110100 o! b01110100 p! b01000111 t! b01000111 u! b01000111 v! b01000111 w! b01000111 x! b01000111 y! b01110100 z! b01110100 {! b01110100 |! b01000111 "" b01000111 #" b01000111 $" b01000111 %" b01000111 &" b01000111 '" b01110100 (" b01110100 )" b01110100 *" b01000111 ." b01000111 /" b01000111 0" b01000111 1" b01000111 2" b01000111 3" b01110100 4" b01110100 5" b01110100 6" b01000111 :" b01000111 ;" b01000111 <" b01000111 =" b01000111 >" b01000111 ?" b01110100 @" b01110100 A" b01110100 B" b01000111 F" b01000111 G" b01000111 H" b01000111 I" b01000111 J" b01000111 K" b01110100 L" b01110100 M" b01110100 N" b01110100 O" b00000000000000000000000001000111 P" b00000000000000000000000001000111 Q" b00000000000000000000000001110100 R" b01110100 S" b10001110010001110100011101110100 T" b01110100 U" b10001110010001110100011101110100 V" b01110100 W" b10001110010001110100011101110100 X" b01110100 Y" b10001110010001110100011101110100 Z" 1[" #55 0[" #60 b00111010 - b00111010 . b00111010 / b00111010 0 b00111010 1 b00111010 2 b00111010 3 b00111010 4 b00111010 5 b00111010 6 b00111010 7 b10001110 ; b10001110 < b10001110 = b10100011 > b10100011 ? b10100011 @ b00111010 A b00111010 B b10001110 F b10001110 G b10001110 H b10100011 I b10100011 J b10100011 K b00111010 L b00111010 M b00111010 N b00111010 O 0Q 1T 0U 1V 1Y 0Z 1[ 0^ 1a 0b 1c 0f b110 h b0011010110010000100001010101111 i b0011010110010000100001010101111 j b100110100 k b100110100 l b100110100 m b100110100 n b001101000 p b00000000000000000000000000000110 $! b00111010 '! b10100011 (! b10001110 )! b00111010 *! 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b10001110100011101000111010001110 X" b10001110 Y" b10001110100011101000111010001110 Z" 1[" verilator-5.042/test_regress/t/t_parse_sync_bad2.v0000644000542200017500000000110615101701376022634 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Dan Petrisko. // SPDX-License-Identifier: CC0-1.0 package pkg; class cls; typedef unknown defu; typedef int defi; endclass endpackage module t; task tsk; begin Invalid1 invalid1; // invalid declaration pkg::cls::defi valid1; // valid declaration pkg::cls::defu valid2; // valid declaration Invalid2 invalid2; // invalid declaration end endtask endmodule verilator-5.042/test_regress/t/t_prof.v0000644000542200017500000000325515101701376020553 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t( `ifdef T_PROF clk `endif ); `ifdef T_PROF input clk; `else bit clk; initial forever begin #5; clk = !clk; end `endif integer cyc = 0; wire [63:0] result; Test test(/*AUTOINST*/ // Outputs .result (result[63:0]), // Inputs .clk (clk), .cyc (cyc)); reg [63:0] sum; always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d result=%x\n", $time, cyc, result); `endif cyc <= cyc + 1; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc == 0) begin // Setup sum <= '0; end else if (cyc < 10) begin sum <= '0; end else if (cyc < 90) begin end else if (cyc == 99) begin $write("[%0t] cyc==%0d sum=%x\n", $time, cyc, sum); // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'hfefad16f06ba6b1f if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test(/*AUTOARG*/ // Outputs result, // Inputs clk, cyc ); input clk; input int cyc; output reg [63:0] result; logic [63:0] adder; always @(posedge clk) begin adder = 0; for (int i = 0; i < 1000; ++i) adder += {32'h0, (cyc+i)} ** 3; result <= adder; end endmodule verilator-5.042/test_regress/t/t_select_bad_range4.out0000644000542200017500000001334415101701376023474 0ustar mahmoudyfreeshell%Error: t/t_select_bad_range4.v:17:8: Width of bit range is huge; vector of over 1 billion bits: 0x20000001 : ... note: In instance 't' 17 | reg [1<<29 : 0] hugerange; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_select_bad_range4.v:20:16: Width of :+ or :- is < 0: 32'hffffffff : ... note: In instance 't' 20 | sel2 = mi[44 +: -1]; | ^ %Error: t/t_select_bad_range4.v:20:16: Width of bit extract must be positive (IEEE 1800-2023 11.5.1) : ... note: In instance 't' 20 | sel2 = mi[44 +: -1]; | ^ %Warning-WIDTHEXPAND: t/t_select_bad_range4.v:20:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits. : ... note: In instance 't' 20 | sel2 = mi[44 +: -1]; | ^ ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. %Error: t/t_select_bad_range4.v:21:16: Width of :+ or :- is huge; vector of over 1 billion bits: 32'h20000000 : ... note: In instance 't' 21 | sel2 = mi[44 +: 1<<29]; | ^ %Warning-SELRANGE: t/t_select_bad_range4.v:21:16: Extracting 536870912 bits from only 6 bit number : ... note: In instance 't' 21 | sel2 = mi[44 +: 1<<29]; | ^ ... For warning description see https://verilator.org/warn/SELRANGE?v=latest ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Warning-SELRANGE: t/t_select_bad_range4.v:21:16: Selection index out of range: 536870915:4 outside 45:40 : ... note: In instance 't' 21 | sel2 = mi[44 +: 1<<29]; | ^ %Warning-WIDTHTRUNC: t/t_select_bad_range4.v:21:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 536870912 bits. : ... note: In instance 't' 21 | sel2 = mi[44 +: 1<<29]; | ^ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: t/t_select_bad_range4.v:22:23: Expecting expression to be constant, but variable isn't const: 'nonconst' : ... note: In instance 't' 22 | sel2 = mi[44 +: nonconst]; | ^~~~~~~~ %Error: t/t_select_bad_range4.v:22:23: Width of :+ or :- bit slice range isn't a constant : ... note: In instance 't' 22 | sel2 = mi[44 +: nonconst]; | ^~~~~~~~ %Warning-WIDTHEXPAND: t/t_select_bad_range4.v:22:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits. : ... note: In instance 't' 22 | sel2 = mi[44 +: nonconst]; | ^ %Warning-WIDTHEXPAND: t/t_select_bad_range4.v:23:17: Operator SUB expects 32 or 6 bits on the LHS, but LHS's VARREF 'nonconst' generates 1 bits. : ... note: In instance 't' 23 | sel2 = mi[nonconst]; | ^~~~~~~~ %Warning-WIDTHEXPAND: t/t_select_bad_range4.v:23:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits. : ... note: In instance 't' 23 | sel2 = mi[nonconst]; | ^ %Error: t/t_select_bad_range4.v:24:17: First value of [a:b] isn't a constant, maybe you want +: or -: : ... note: In instance 't' 24 | sel2 = mi[nonconst : nonconst]; | ^~~~~~~~ %Error: t/t_select_bad_range4.v:24:28: Second value of [a:b] isn't a constant, maybe you want +: or -: : ... note: In instance 't' 24 | sel2 = mi[nonconst : nonconst]; | ^~~~~~~~ %Warning-WIDTHEXPAND: t/t_select_bad_range4.v:24:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits. : ... note: In instance 't' 24 | sel2 = mi[nonconst : nonconst]; | ^ %Warning-SELRANGE: t/t_select_bad_range4.v:25:16: Extracting 536870913 bits from only 6 bit number : ... note: In instance 't' 25 | sel2 = mi[1<<29 : 0]; | ^ %Warning-SELRANGE: t/t_select_bad_range4.v:25:16: Selection index out of range: 536870872:-40 outside 45:40 : ... note: In instance 't' 25 | sel2 = mi[1<<29 : 0]; | ^ %Warning-SELRANGE: t/t_select_bad_range4.v:25:16: Extracting 536870913 bits from only 536870873 bit number : ... note: In instance 't' 25 | sel2 = mi[1<<29 : 0]; | ^ %Warning-WIDTHTRUNC: t/t_select_bad_range4.v:25:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 536870913 bits. : ... note: In instance 't' 25 | sel2 = mi[1<<29 : 0]; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_opt_const_big_or_tree.py0000755000542200017500000000113515101701376024336 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') if test.have_dev_gcov: test.skip("Too slow with code coverage") test.timeout(10 if not test.have_dev_asan else 30) test.compile(verilator_make_gmake=False) test.passes() verilator-5.042/test_regress/t/t_randomize_method_nclass_bad.py0000755000542200017500000000077615101701376025501 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface_modport.py0000755000542200017500000000073415101701376023476 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_unconnected_bad.py0000755000542200017500000000076615101701376023112 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_comb_input_1.v0000644000542200017500000000174415101701376022165 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2022 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module top( clk, inc ); input clk; input [31:0] inc; // Cycle count reg [31:0] cyc = 0; /* verilator lint_off UNOPTFLAT */ // Circular combinational logic driven from primary input. 'msb' is the // narrowest, so it will be the cut vertex. wire [31:0] feedback; wire [31:0] sum = cyc + inc + feedback; wire msb = sum[31]; // Always 0, but Verilator cannot know that assign feedback = {32{msb}}; always @(posedge clk) begin $display("cyc: %d sum: %d", cyc, sum); if (sum != 2*cyc + 1) $stop; cyc <= cyc + 1; if (cyc == 100) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_inside_wild.v0000644000542200017500000000375015101701376022077 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; wire [4:0] in = crc[4:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) logic out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out (out), // Inputs .clk (clk), .in (in[4:0])); // Aggregate outputs into a single result vector wire [63:0] result = {63'h0, out}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h7a7bd4ee927e7cc3 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs out, // Inputs clk, in ); //bug718 input clk; input logic [4:0] in; output logic out; always @(posedge clk) begin out <= in inside {5'b1_1?1?}; end endmodule verilator-5.042/test_regress/t/t_covergroup_new_override_bad.py0000755000542200017500000000113715101701376025541 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if test.vlt_all: test.lint(fails=True, expect_filename=test.golden_filename) else: test.compile(nc_flags2=["-coverage", "functional"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_x_rand_mt_stability_add_trace.py0000755000542200017500000000122615101701376026014 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios("vltmt") test.top_filename = "t/t_x_rand_stability.v" test.compile(verilator_flags2=["--x-initial unique", "-DADD_SIGNAL", "--trace"]) test.execute(all_run_flags=["+verilator+rand+reset+2"], expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_flag_build_bad.py0000755000542200017500000000153115101701376022664 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["--build --make gmake"], fails=True, expect_filename=test.golden_filename) test.compile(verilator_flags2=["--build --make cmake -Wno-fatal"], fails=True, expect_filename="t/t_flag_build_bad_cmake.out") test.compile(verilator_flags2=["--build --make json"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_udp_bad_illegal_output.py0000755000542200017500000000076615101701376024506 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_array_pattern_unpacked.py0000755000542200017500000000073415101701376024517 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_split_var_1_bad.v0000644000542200017500000000541315101701376022634 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by Yutetsu TAKATSUKASA. // SPDX-License-Identifier: CC0-1.0 logic [7:0] should_show_warning_global0 /* verilator split_var */; logic [7:0] should_show_warning_global1 [1:0] /* verilator split_var */; interface ifs; logic [7:0] should_show_warning_ifs0 /* verilator split_var */; logic [7:0] should_show_warning_ifs1 [1:0] /* verilator split_var */; endinterface module t(); // The following variables can not be splitted. will see warnings. real should_show_warning0 /*verilator split_var*/; string should_show_warning1 /*verilator split_var*/; wire should_show_warning2 /*verilator split_var*/; logic [3:0] addr; logic [7:0] rd_data0, rd_data1, rd_data2; logic [1:0] public_signal /*verilator public*/ /*verilator split_var*/; sub0 i_sub0(.addr(addr), .rd_data(rd_data0)); sub1 i_sub1(.addr(addr), .rd_data(rd_data2)); sub2 i_sub2(); sub3 i_sub3(); ifs i_ifs(); function int bad_func(inout logic [3:0] inout_port /*verilator split_var*/, ref logic [7:0] ref_port /*verilator split_var*/); return 0; endfunction initial begin logic [7:0] loop_idx /*verilator split_var*/; addr = 0; addr = 1; i_sub0.cannot_split1[0] = 0; i_sub0.cannot_split1[1] = bad_func(addr, rd_data0); for (loop_idx = 0; loop_idx < 8'd4; loop_idx = loop_idx + 2) begin addr += 1; end $finish; end endmodule module sub0(input [3:0]addr, output logic [7:0] rd_data); logic [7:0] cannot_split0[0:15] /*verilator split_var*/; logic [7:0] cannot_split1[0:15] /*verilator split_var*/; always_comb rd_data = cannot_split0[addr]; endmodule module sub1(input [3:0]addr, output logic [7:0] rd_data); genvar cannot_split_genvar /*verilator split_var*/; logic [15:0] [8:0] cannot_split /*verilator split_var*/; always_comb begin static logic [8:0] rd_tmp /*verilator split_var*/ = cannot_split[addr]; rd_data = rd_tmp[{3'b0, addr[0]}+:8]; end endmodule module sub2; // from t_bitsel_wire_array_bad.v // a and b are arrays of length 1. wire a[0:0] /* verilator split_var */ ; // Array of nets wire b[0:0] /* verilator split_var */ ; assign a = 1'b0; // Only net assignment allowed assign b = a[0]; // Only net assignment allowed endmodule module sub3; // from t_select_bad_range3.v logic [7:0] inwires [12:10] /* verilator split_var */; wire [7:0] outwires [12:10] /* verilator split_var */; assign outwires[10] = inwires[11]; assign outwires[11] = inwires[12]; assign outwires[12] = inwires[13]; // must be an error here endmodule verilator-5.042/test_regress/t/t_time_sc_fs.py0000755000542200017500000000121315101701376022076 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_time_sc.v" test.sc_time_resolution = 'SC_FS' test.compile(verilator_flags2=['-sc', '-timescale 1fs/1fs', '+define+TEST_EXPECT=20fs']) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_public_unpacked_port.py0000755000542200017500000000072615101701376024167 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_param_type3.py0000755000542200017500000000073515101701376022217 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() #test.execute() test.passes() verilator-5.042/test_regress/t/t_case_unique_many.v0000644000542200017500000002233415101701376023131 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Varun Koyyalagunta, Tenstorrent. // SPDX-License-Identifier: CC0-1.0 module t; localparam W = 23; localparam [W-1:0] R0 = W'('h200000 + 0); localparam [W-1:0] R1 = W'('h200000 + 1); localparam [W-1:0] R2 = W'('h200000 + 2); localparam [W-1:0] R3 = W'('h200000 + 3); localparam [W-1:0] R4 = W'('h200000 + 4); localparam [W-1:0] R5 = W'('h200000 + 5); localparam [W-1:0] R6 = W'('h200000 + 6); localparam [W-1:0] R7 = W'('h200000 + 7); localparam [W-1:0] R8 = W'('h200000 + 8); localparam [W-1:0] R9 = W'('h200000 + 9); localparam [W-1:0] R10 = W'('h200000 + 10); localparam [W-1:0] R11 = W'('h200000 + 11); localparam [W-1:0] R12 = W'('h200000 + 12); localparam [W-1:0] R13 = W'('h200000 + 13); localparam [W-1:0] R14 = W'('h200000 + 14); localparam [W-1:0] R15 = W'('h200000 + 15); localparam [W-1:0] R16 = W'('h200000 + 16); localparam [W-1:0] R17 = W'('h200000 + 17); localparam [W-1:0] R18 = W'('h200000 + 18); localparam [W-1:0] R19 = W'('h200000 + 19); localparam [W-1:0] R20 = W'('h200000 + 20); localparam [W-1:0] R21 = W'('h200000 + 21); localparam [W-1:0] R22 = W'('h200000 + 22); localparam [W-1:0] R23 = W'('h200000 + 23); localparam [W-1:0] R24 = W'('h200000 + 24); localparam [W-1:0] R25 = W'('h200000 + 25); localparam [W-1:0] R26 = W'('h200000 + 26); localparam [W-1:0] R27 = W'('h200000 + 27); localparam [W-1:0] R28 = W'('h200000 + 28); localparam [W-1:0] R29 = W'('h200000 + 29); localparam [W-1:0] R30 = W'('h200000 + 30); localparam [W-1:0] R31 = W'('h200000 + 31); localparam [W-1:0] R32 = W'('h200000 + 32); localparam [W-1:0] R33 = W'('h200000 + 33); localparam [W-1:0] R34 = W'('h200000 + 34); localparam [W-1:0] R35 = W'('h200000 + 35); localparam [W-1:0] R36 = W'('h200000 + 36); localparam [W-1:0] R37 = W'('h200000 + 37); localparam [W-1:0] R38 = W'('h200000 + 38); localparam [W-1:0] R39 = W'('h200000 + 39); localparam [W-1:0] R40 = W'('h200000 + 40); localparam [W-1:0] R41 = W'('h200000 + 41); localparam [W-1:0] R42 = W'('h200000 + 42); localparam [W-1:0] R43 = W'('h200000 + 43); localparam [W-1:0] R44 = W'('h200000 + 44); localparam [W-1:0] R45 = W'('h200000 + 45); localparam [W-1:0] R46 = W'('h200000 + 46); localparam [W-1:0] R47 = W'('h200000 + 47); localparam [W-1:0] R48 = W'('h200000 + 48); localparam [W-1:0] R49 = W'('h200000 + 49); localparam [W-1:0] R50 = W'('h200000 + 50); localparam [W-1:0] R51 = W'('h200000 + 51); localparam [W-1:0] R52 = W'('h200000 + 52); localparam [W-1:0] R53 = W'('h200000 + 53); localparam [W-1:0] R54 = W'('h200000 + 54); localparam [W-1:0] R55 = W'('h200000 + 55); localparam [W-1:0] R56 = W'('h200000 + 56); localparam [W-1:0] R57 = W'('h200000 + 57); localparam [W-1:0] R58 = W'('h200000 + 58); localparam [W-1:0] R59 = W'('h200000 + 59); localparam [W-1:0] R60 = W'('h200000 + 60); localparam [W-1:0] R61 = W'('h200000 + 61); localparam [W-1:0] R62 = W'('h200000 + 62); localparam [W-1:0] R63 = W'('h200000 + 63); localparam [W-1:0] R64 = W'('h200000 + 64); localparam [W-1:0] R65 = W'('h200000 + 65); localparam [W-1:0] R66 = W'('h200000 + 66); localparam [W-1:0] R67 = W'('h200000 + 67); localparam [W-1:0] R68 = W'('h200000 + 68); localparam [W-1:0] R69 = W'('h200000 + 69); localparam [W-1:0] R70 = W'('h200000 + 70); localparam [W-1:0] R71 = W'('h200000 + 71); localparam [W-1:0] R72 = W'('h200000 + 72); localparam [W-1:0] R73 = W'('h200000 + 73); localparam [W-1:0] R74 = W'('h200000 + 74); localparam [W-1:0] R75 = W'('h200000 + 75); localparam [W-1:0] R76 = W'('h200000 + 76); localparam [W-1:0] R77 = W'('h200000 + 77); localparam [W-1:0] R78 = W'('h200000 + 78); localparam [W-1:0] R79 = W'('h200000 + 79); localparam [W-1:0] R80 = W'('h200000 + 80); localparam [W-1:0] R81 = W'('h200000 + 81); localparam [W-1:0] R82 = W'('h200000 + 82); localparam [W-1:0] R83 = W'('h200000 + 83); localparam [W-1:0] R84 = W'('h200000 + 84); localparam [W-1:0] R85 = W'('h200000 + 85); localparam [W-1:0] R86 = W'('h200000 + 86); localparam [W-1:0] R87 = W'('h200000 + 87); localparam [W-1:0] R88 = W'('h200000 + 88); localparam [W-1:0] R89 = W'('h200000 + 89); localparam [W-1:0] R90 = W'('h200000 + 90); localparam [W-1:0] R91 = W'('h200000 + 91); localparam [W-1:0] R92 = W'('h200000 + 92); localparam [W-1:0] R93 = W'('h200000 + 93); localparam [W-1:0] R94 = W'('h200000 + 94); localparam [W-1:0] R95 = W'('h200000 + 95); localparam [W-1:0] R96 = W'('h200000 + 96); localparam [W-1:0] R97 = W'('h200000 + 97); localparam [W-1:0] R98 = W'('h200000 + 98); localparam [W-1:0] R99 = W'('h200000 + 99); typedef struct packed { logic r0; logic r1; logic r2; logic r3; logic r4; logic r5; logic r6; logic r7; logic r8; logic r9; logic r10; logic r11; logic r12; logic r13; logic r14; logic r15; logic r16; logic r17; logic r18; logic r19; logic r20; logic r21; logic r22; logic r23; logic r24; logic r25; logic r26; logic r27; logic r28; logic r29; logic r30; logic r31; logic r32; logic r33; logic r34; logic r35; logic r36; logic r37; logic r38; logic r39; logic r40; logic r41; logic r42; logic r43; logic r44; logic r45; logic r46; logic r47; logic r48; logic r49; logic r50; logic r51; logic r52; logic r53; logic r54; logic r55; logic r56; logic r57; logic r58; logic r59; logic r60; logic r61; logic r62; logic r63; logic r64; logic r65; logic r66; logic r67; logic r68; logic r69; logic r70; logic r71; logic r72; logic r73; logic r74; logic r75; logic r76; logic r77; logic r78; logic r79; logic r80; logic r81; logic r82; logic r83; logic r84; logic r85; logic r86; logic r87; logic r88; logic r89; logic r90; logic r91; logic r92; logic r93; logic r94; logic r95; logic r96; logic r97; logic r98; logic r99; } hit_t; function automatic hit_t get_hit(input logic [22:0] a); hit_t hit = '0; unique case (a) R0: hit.r0 = 1'b1; R1: hit.r1 = 1'b1; R2: hit.r2 = 1'b1; R3: hit.r3 = 1'b1; R4: hit.r4 = 1'b1; R5: hit.r5 = 1'b1; R6: hit.r6 = 1'b1; R7: hit.r7 = 1'b1; R8: hit.r8 = 1'b1; R9: hit.r9 = 1'b1; R10: hit.r10 = 1'b1; R11: hit.r11 = 1'b1; R12: hit.r12 = 1'b1; R13: hit.r13 = 1'b1; R14: hit.r14 = 1'b1; R15: hit.r15 = 1'b1; R16: hit.r16 = 1'b1; R17: hit.r17 = 1'b1; R18: hit.r18 = 1'b1; R19: hit.r19 = 1'b1; R20: hit.r20 = 1'b1; R21: hit.r21 = 1'b1; R22: hit.r22 = 1'b1; R23: hit.r23 = 1'b1; R24: hit.r24 = 1'b1; R25: hit.r25 = 1'b1; R26: hit.r26 = 1'b1; R27: hit.r27 = 1'b1; R28: hit.r28 = 1'b1; R29: hit.r29 = 1'b1; R30: hit.r30 = 1'b1; R31: hit.r31 = 1'b1; R32: hit.r32 = 1'b1; R33: hit.r33 = 1'b1; R34: hit.r34 = 1'b1; R35: hit.r35 = 1'b1; R36: hit.r36 = 1'b1; R37: hit.r37 = 1'b1; R38: hit.r38 = 1'b1; R39: hit.r39 = 1'b1; R40: hit.r40 = 1'b1; R41: hit.r41 = 1'b1; R42: hit.r42 = 1'b1; R43: hit.r43 = 1'b1; R44: hit.r44 = 1'b1; R45: hit.r45 = 1'b1; R46: hit.r46 = 1'b1; R47: hit.r47 = 1'b1; R48: hit.r48 = 1'b1; R49: hit.r49 = 1'b1; R50: hit.r50 = 1'b1; R51: hit.r51 = 1'b1; R52: hit.r52 = 1'b1; R53: hit.r53 = 1'b1; R54: hit.r54 = 1'b1; R55: hit.r55 = 1'b1; R56: hit.r56 = 1'b1; R57: hit.r57 = 1'b1; R58: hit.r58 = 1'b1; R59: hit.r59 = 1'b1; R60: hit.r60 = 1'b1; R61: hit.r61 = 1'b1; R62: hit.r62 = 1'b1; R63: hit.r63 = 1'b1; R64: hit.r64 = 1'b1; R65: hit.r65 = 1'b1; R66: hit.r66 = 1'b1; R67: hit.r67 = 1'b1; R68: hit.r68 = 1'b1; R69: hit.r69 = 1'b1; R70: hit.r70 = 1'b1; R71: hit.r71 = 1'b1; R72: hit.r72 = 1'b1; R73: hit.r73 = 1'b1; R74: hit.r74 = 1'b1; R75: hit.r75 = 1'b1; R76: hit.r76 = 1'b1; R77: hit.r77 = 1'b1; R78: hit.r78 = 1'b1; R79: hit.r79 = 1'b1; R80: hit.r80 = 1'b1; R81: hit.r81 = 1'b1; R82: hit.r82 = 1'b1; R83: hit.r83 = 1'b1; R84: hit.r84 = 1'b1; R85: hit.r85 = 1'b1; R86: hit.r86 = 1'b1; R87: hit.r87 = 1'b1; R88: hit.r88 = 1'b1; R89: hit.r89 = 1'b1; R90: hit.r90 = 1'b1; R91: hit.r91 = 1'b1; R92: hit.r92 = 1'b1; R93: hit.r93 = 1'b1; R94: hit.r94 = 1'b1; R95: hit.r95 = 1'b1; R96: hit.r96 = 1'b1; R97: hit.r97 = 1'b1; R98: hit.r98 = 1'b1; R99: hit.r99 = 1'b1; default: hit = '0; endcase return hit; endfunction initial begin if (get_hit(R30) !== hit_t'{r30: 1'b1, default: '0}) $stop; if (get_hit('1) !== '0) $stop; if (get_hit('0) !== '0) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_dpi_export_context_bad.py0000755000542200017500000000110215101701376024507 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=["--exe", test.pli_filename], make_main=False) test.execute(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_mem_file.v0000644000542200017500000001300415101701376021353 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc = 0; reg [63:0] crc; reg [63:0] sum; wire r1_en /*verilator public*/ = crc[12]; wire [1:0] r1_ad /*verilator public*/ = crc[9:8]; wire r2_en /*verilator public*/ = 1'b1; wire [1:0] r2_ad /*verilator public*/ = crc[11:10]; wire w1_en /*verilator public*/ = crc[5]; wire [1:0] w1_a /*verilator public*/ = crc[1:0]; wire [63:0] w1_d /*verilator public*/ = {2{crc[63:32]}}; wire w2_en /*verilator public*/ = crc[4]; wire [1:0] w2_a /*verilator public*/ = crc[3:2]; wire [63:0] w2_d /*verilator public*/ = {2{~crc[63:32]}}; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [63:0] r1_d_d2r; // From file of file.v wire [63:0] r2_d_d2r; // From file of file.v // End of automatics file file (/*AUTOINST*/ // Outputs .r1_d_d2r (r1_d_d2r[63:0]), .r2_d_d2r (r2_d_d2r[63:0]), // Inputs .clk (clk), .r1_en (r1_en), .r1_ad (r1_ad[1:0]), .r2_en (r2_en), .r2_ad (r2_ad[1:0]), .w1_en (w1_en), .w1_a (w1_a[1:0]), .w1_d (w1_d[63:0]), .w2_en (w2_en), .w2_a (w2_a[1:0]), .w2_d (w2_d[63:0])); always @ (posedge clk) begin //$write("[%0t] cyc==%0d EN=%b%b%b%b R0=%x R1=%x\n", $time, cyc, r1_en,r2_en,w1_en,w2_en, r1_d_d2r, r2_d_d2r); cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= {r1_d_d2r ^ r2_d_d2r} ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin // We've manually verified all X's are out of the design by this point sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $write("[%0t] cyc==%0d crc=%x %x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; if (sum !== 64'h5e9ea8c33a97f81e) $stop; $finish; end end endmodule module file (/*AUTOARG*/ // Outputs r1_d_d2r, r2_d_d2r, // Inputs clk, r1_en, r1_ad, r2_en, r2_ad, w1_en, w1_a, w1_d, w2_en, w2_a, w2_d ); input clk; input r1_en; input [1:0] r1_ad; output [63:0] r1_d_d2r; input r2_en; input [1:0] r2_ad; output [63:0] r2_d_d2r; input w1_en; input [1:0] w1_a; input [63:0] w1_d; input w2_en; input [1:0] w2_a; input [63:0] w2_d; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) // End of automatics /*AUTOREG*/ // Beginning of automatic regs (for this module's undeclared outputs) reg [63:0] r1_d_d2r; reg [63:0] r2_d_d2r; // End of automatics // Writes wire [3:0] m_w1_onehotwe = ({4{w1_en}} & (4'b1 << w1_a)); wire [3:0] m_w2_onehotwe = ({4{w2_en}} & (4'b1 << w2_a)); wire [63:0] rg0_wrdat = m_w1_onehotwe[0] ? w1_d : w2_d; wire [63:0] rg1_wrdat = m_w1_onehotwe[1] ? w1_d : w2_d; wire [63:0] rg2_wrdat = m_w1_onehotwe[2] ? w1_d : w2_d; wire [63:0] rg3_wrdat = m_w1_onehotwe[3] ? w1_d : w2_d; wire [3:0] m_w_onehotwe = m_w1_onehotwe | m_w2_onehotwe; // Storage reg [63:0] m_rg0_r; reg [63:0] m_rg1_r; reg [63:0] m_rg2_r; reg [63:0] m_rg3_r; always @ (posedge clk) begin if (m_w_onehotwe[0]) m_rg0_r <= rg0_wrdat; if (m_w_onehotwe[1]) m_rg1_r <= rg1_wrdat; if (m_w_onehotwe[2]) m_rg2_r <= rg2_wrdat; if (m_w_onehotwe[3]) m_rg3_r <= rg3_wrdat; end // Reads reg [1:0] m_r1_ad_d1r; reg [1:0] m_r2_ad_d1r; reg [1:0] m_ren_d1r; always @ (posedge clk) begin if (r1_en) m_r1_ad_d1r <= r1_ad; if (r2_en) m_r2_ad_d1r <= r2_ad; m_ren_d1r <= {r2_en, r1_en}; end // Scheme1: shift... wire [3:0] m_r1_onehot_d1 = (4'b1 << m_r1_ad_d1r); // Scheme2: bit mask reg [3:0] m_r2_onehot_d1; always @* begin m_r2_onehot_d1 = 4'd0; m_r2_onehot_d1[m_r2_ad_d1r] = 1'b1; end wire [63:0] m_r1_d_d1 = (({64{m_r1_onehot_d1[0]}} & m_rg0_r) | ({64{m_r1_onehot_d1[1]}} & m_rg1_r) | ({64{m_r1_onehot_d1[2]}} & m_rg2_r) | ({64{m_r1_onehot_d1[3]}} & m_rg3_r)); wire [63:0] m_r2_d_d1 = (({64{m_r2_onehot_d1[0]}} & m_rg0_r) | ({64{m_r2_onehot_d1[1]}} & m_rg1_r) | ({64{m_r2_onehot_d1[2]}} & m_rg2_r) | ({64{m_r2_onehot_d1[3]}} & m_rg3_r)); always @ (posedge clk) begin if (m_ren_d1r[0]) r1_d_d2r <= m_r1_d_d1; if (m_ren_d1r[1]) r2_d_d2r <= m_r2_d_d1; end endmodule verilator-5.042/test_regress/t/t_detectarray_2.py0000755000542200017500000000101315101701376022511 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["-Wno-UNOPTFLAT", "-fno-dfg"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_ref_trace_fst_sc.out0000644000542200017500000004466715101701376025476 0ustar mahmoudyfreeshell$date Sat Apr 5 13:55:38 2025 $end $version fstWriter $end $timescale 1ps $end $scope module top $end $scope module t $end $var wire 1 ! clk $end $var integer 32 " cyc [31:0] $end $scope interface intf_1 $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 # value [31:0] $end $scope struct the_struct $end $var integer 32 $ val100 [31:0] $end $var integer 32 % val200 [31:0] $end $upscope $end $scope interface inner $end $var wire 32 " cyc [31:0] $end $var integer 32 & value [31:0] $end $upscope $end $upscope $end $scope interface intf_2 $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 ' value [31:0] $end $scope struct the_struct $end $var integer 32 ( val100 [31:0] $end $var integer 32 ) val200 [31:0] $end $upscope $end $scope interface inner $end $var wire 32 " cyc [31:0] $end $var integer 32 * value [31:0] $end $upscope $end $upscope $end $scope module a $end $scope interface intf_one $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 # value [31:0] $end $scope struct the_struct $end $var integer 32 $ val100 [31:0] $end $var integer 32 % val200 [31:0] $end $upscope $end $scope interface inner $end $var wire 32 " cyc [31:0] $end $var integer 32 & value [31:0] $end $upscope $end $upscope $end $scope interface intf_two $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 ' value [31:0] $end $scope struct the_struct $end $var integer 32 ( val100 [31:0] $end $var integer 32 ) val200 [31:0] $end $upscope $end $scope interface inner $end $var wire 32 " cyc [31:0] $end $var integer 32 * value [31:0] $end $upscope $end $upscope $end $scope interface intf_in_sub_all $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 + value [31:0] $end $scope struct the_struct $end $var integer 32 , val100 [31:0] $end $var integer 32 - val200 [31:0] $end $upscope $end $scope interface inner $end $var wire 32 " cyc [31:0] $end $var integer 32 . value [31:0] $end $upscope $end $upscope $end $scope module ac1 $end $scope interface intf_for_check $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 # value [31:0] $end $scope struct the_struct $end $var integer 32 $ val100 [31:0] $end $var integer 32 % val200 [31:0] $end $upscope $end $scope interface inner $end $var wire 32 " cyc [31:0] $end $var integer 32 & value [31:0] $end $upscope $end $upscope $end $upscope $end $scope module ac2 $end $scope interface intf_for_check $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 ' value [31:0] $end $scope struct the_struct $end $var integer 32 ( val100 [31:0] $end $var integer 32 ) val200 [31:0] $end $upscope $end $scope interface inner $end $var wire 32 " cyc [31:0] $end $var integer 32 * value [31:0] $end $upscope $end $upscope $end $upscope $end $scope module ac3 $end $scope interface intf_for_check $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 + value [31:0] $end $scope struct the_struct $end $var integer 32 , val100 [31:0] $end $var integer 32 - val200 [31:0] $end $upscope $end $scope interface inner $end $var wire 32 " cyc [31:0] $end $var integer 32 . value [31:0] $end $upscope $end $upscope $end $upscope $end $scope module as3 $end $scope interface intf_for_struct $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 + value [31:0] $end $scope struct the_struct $end $var integer 32 , val100 [31:0] $end $var integer 32 - val200 [31:0] $end $upscope $end $scope interface inner $end $var wire 32 " cyc [31:0] $end $var integer 32 . value [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module abcdefghijklmnopqrstuvwxyz $end $scope interface intf_one $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 ' value [31:0] $end $scope struct the_struct $end $var integer 32 ( val100 [31:0] $end $var integer 32 ) val200 [31:0] $end $upscope $end $scope interface inner $end $var wire 32 " cyc [31:0] $end $var integer 32 * value [31:0] $end $upscope $end $upscope $end $scope interface intf_two $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 # value [31:0] $end $scope struct the_struct $end $var integer 32 $ val100 [31:0] $end $var integer 32 % val200 [31:0] $end $upscope $end $scope interface inner $end $var wire 32 " cyc [31:0] $end $var integer 32 & value [31:0] $end $upscope $end $upscope $end $scope interface intf_in_sub_all $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 / value [31:0] $end $scope struct the_struct $end $var integer 32 0 val100 [31:0] $end $var integer 32 1 val200 [31:0] $end $upscope $end $scope interface inner $end $var wire 32 " cyc [31:0] $end $var integer 32 2 value [31:0] $end $upscope $end $upscope $end $scope module ac1 $end $scope interface intf_for_check $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 ' value [31:0] $end $scope struct the_struct $end $var integer 32 ( val100 [31:0] $end $var integer 32 ) val200 [31:0] $end $upscope $end $scope interface inner $end $var wire 32 " cyc [31:0] $end $var integer 32 * value [31:0] $end $upscope $end $upscope $end $upscope $end $scope module ac2 $end $scope interface intf_for_check $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 # value [31:0] $end $scope struct the_struct $end $var integer 32 $ val100 [31:0] $end $var integer 32 % val200 [31:0] $end $upscope $end $scope interface inner $end $var wire 32 " cyc [31:0] $end $var integer 32 & value [31:0] $end $upscope $end $upscope $end $upscope $end $scope module ac3 $end $scope interface intf_for_check $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 / value [31:0] $end $scope struct the_struct $end $var integer 32 0 val100 [31:0] $end $var integer 32 1 val200 [31:0] $end $upscope $end $scope interface inner $end $var wire 32 " cyc [31:0] $end $var integer 32 2 value [31:0] $end $upscope $end $upscope $end $upscope $end $scope module as3 $end $scope interface intf_for_struct $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 / value [31:0] $end $scope struct the_struct $end $var integer 32 0 val100 [31:0] $end $var integer 32 1 val200 [31:0] $end $upscope $end $scope interface inner $end $var wire 32 " cyc [31:0] $end $var integer 32 2 value [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module c1 $end $scope interface intf_for_check $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 # value [31:0] $end $scope struct the_struct $end $var integer 32 $ val100 [31:0] $end $var integer 32 % val200 [31:0] $end $upscope $end $scope interface inner $end $var wire 32 " cyc [31:0] $end $var integer 32 & value [31:0] $end $upscope $end $upscope $end $upscope $end $scope module c2 $end $scope interface intf_for_check $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 ' value [31:0] $end $scope struct the_struct $end $var integer 32 ( val100 [31:0] $end $var integer 32 ) val200 [31:0] $end $upscope $end $scope interface inner $end $var wire 32 " cyc [31:0] $end $var integer 32 * value [31:0] $end $upscope $end $upscope $end $upscope $end $scope module s1 $end $scope interface intf_for_struct $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 # value [31:0] $end $scope struct the_struct $end $var integer 32 $ val100 [31:0] $end $var integer 32 % val200 [31:0] $end $upscope $end $scope interface inner $end $var wire 32 " cyc [31:0] $end $var integer 32 & value [31:0] $end $upscope $end $upscope $end $upscope $end $scope module s2 $end $scope interface intf_for_struct $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 ' value [31:0] $end $scope struct the_struct $end $var integer 32 ( val100 [31:0] $end $var integer 32 ) val200 [31:0] $end $upscope $end $scope interface inner $end $var wire 32 " cyc [31:0] $end $var integer 32 * value [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b00000000000000000000000000000000 2 b00000000000000000000010010110010 1 b00000000000000000000010001001110 0 b00000000000000000000001111101010 / b00000000000000000000000000000000 . b00000000000000000000010010110001 - b00000000000000000000010001001101 , b00000000000000000000001111101001 + b00000000000000000000000000000000 * b00000000000000000000000011001010 ) b00000000000000000000000001100110 ( b00000000000000000000000000000010 ' b00000000000000000000000000000000 & b00000000000000000000000011001001 % b00000000000000000000000001100101 $ b00000000000000000000000000000001 # b00000000000000000000000000000000 " 0! $end #10 1! b00000000000000000000000000000001 " b00000000000000000000000000000010 # b00000000000000000000000001100110 $ b00000000000000000000000011001010 % b00000000000000000000000000000011 ' b00000000000000000000000001100111 ( b00000000000000000000000011001011 ) b00000000000000000000001111101010 + b00000000000000000000010001001110 , b00000000000000000000010010110010 - b00000000000000000000001111101011 / b00000000000000000000010001001111 0 b00000000000000000000010010110011 1 #15 0! #20 1! b00000000000000000000010010110100 1 b00000000000000000000010001010000 0 b00000000000000000000001111101100 / b00000000000000000000010010110011 - b00000000000000000000010001001111 , b00000000000000000000001111101011 + b00000000000000000000000011001100 ) b00000000000000000000000001101000 ( b00000000000000000000000000000100 ' b00000000000000000000000011001011 % b00000000000000000000000001100111 $ b00000000000000000000000000000011 # b00000000000000000000000000000010 " #25 0! #30 1! b00000000000000000000000000000011 " b00000000000000000000000000000100 # b00000000000000000000000001101000 $ b00000000000000000000000011001100 % b00000000000000000000000000000101 ' b00000000000000000000000001101001 ( b00000000000000000000000011001101 ) b00000000000000000000001111101100 + b00000000000000000000010001010000 , b00000000000000000000010010110100 - b00000000000000000000001111101101 / b00000000000000000000010001010001 0 b00000000000000000000010010110101 1 #35 0! #40 1! b00000000000000000000010010110110 1 b00000000000000000000010001010010 0 b00000000000000000000001111101110 / b00000000000000000000010010110101 - b00000000000000000000010001010001 , b00000000000000000000001111101101 + b00000000000000000000000011001110 ) b00000000000000000000000001101010 ( b00000000000000000000000000000110 ' b00000000000000000000000011001101 % b00000000000000000000000001101001 $ b00000000000000000000000000000101 # b00000000000000000000000000000100 " #45 0! #50 1! b00000000000000000000000000000101 " b00000000000000000000000000000110 # b00000000000000000000000001101010 $ b00000000000000000000000011001110 % b00000000000000000000000000000111 ' b00000000000000000000000001101011 ( b00000000000000000000000011001111 ) b00000000000000000000001111101110 + b00000000000000000000010001010010 , b00000000000000000000010010110110 - b00000000000000000000001111101111 / b00000000000000000000010001010011 0 b00000000000000000000010010110111 1 #55 0! #60 1! b00000000000000000000010010111000 1 b00000000000000000000010001010100 0 b00000000000000000000001111110000 / b00000000000000000000010010110111 - b00000000000000000000010001010011 , b00000000000000000000001111101111 + b00000000000000000000000011010000 ) b00000000000000000000000001101100 ( b00000000000000000000000000001000 ' b00000000000000000000000011001111 % b00000000000000000000000001101011 $ b00000000000000000000000000000111 # b00000000000000000000000000000110 " #65 0! #70 1! b00000000000000000000000000000111 " b00000000000000000000000000001000 # b00000000000000000000000001101100 $ b00000000000000000000000011010000 % b00000000000000000000000000001001 ' b00000000000000000000000001101101 ( b00000000000000000000000011010001 ) b00000000000000000000001111110000 + b00000000000000000000010001010100 , b00000000000000000000010010111000 - b00000000000000000000001111110001 / b00000000000000000000010001010101 0 b00000000000000000000010010111001 1 #75 0! #80 1! b00000000000000000000010010111010 1 b00000000000000000000010001010110 0 b00000000000000000000001111110010 / b00000000000000000000010010111001 - b00000000000000000000010001010101 , b00000000000000000000001111110001 + b00000000000000000000000011010010 ) b00000000000000000000000001101110 ( b00000000000000000000000000001010 ' b00000000000000000000000011010001 % b00000000000000000000000001101101 $ b00000000000000000000000000001001 # b00000000000000000000000000001000 " #85 0! #90 1! b00000000000000000000000000001001 " b00000000000000000000000000001010 # b00000000000000000000000001101110 $ b00000000000000000000000011010010 % b00000000000000000000000000001011 ' b00000000000000000000000001101111 ( b00000000000000000000000011010011 ) b00000000000000000000001111110010 + b00000000000000000000010001010110 , b00000000000000000000010010111010 - b00000000000000000000001111110011 / b00000000000000000000010001010111 0 b00000000000000000000010010111011 1 #95 0! #100 1! b00000000000000000000010010111100 1 b00000000000000000000010001011000 0 b00000000000000000000001111110100 / b00000000000000000000010010111011 - b00000000000000000000010001010111 , b00000000000000000000001111110011 + b00000000000000000000000011010100 ) b00000000000000000000000001110000 ( b00000000000000000000000000001100 ' b00000000000000000000000011010011 % b00000000000000000000000001101111 $ b00000000000000000000000000001011 # b00000000000000000000000000001010 " #105 0! #110 1! b00000000000000000000000000001011 " b00000000000000000000000000001100 # b00000000000000000000000001110000 $ b00000000000000000000000011010100 % b00000000000000000000000000001101 ' b00000000000000000000000001110001 ( b00000000000000000000000011010101 ) b00000000000000000000001111110100 + b00000000000000000000010001011000 , b00000000000000000000010010111100 - b00000000000000000000001111110101 / b00000000000000000000010001011001 0 b00000000000000000000010010111101 1 #115 0! #120 1! b00000000000000000000010010111110 1 b00000000000000000000010001011010 0 b00000000000000000000001111110110 / b00000000000000000000010010111101 - b00000000000000000000010001011001 , b00000000000000000000001111110101 + b00000000000000000000000011010110 ) b00000000000000000000000001110010 ( b00000000000000000000000000001110 ' b00000000000000000000000011010101 % b00000000000000000000000001110001 $ b00000000000000000000000000001101 # b00000000000000000000000000001100 " #125 0! #130 1! b00000000000000000000000000001101 " b00000000000000000000000000001110 # b00000000000000000000000001110010 $ b00000000000000000000000011010110 % b00000000000000000000000000001111 ' b00000000000000000000000001110011 ( b00000000000000000000000011010111 ) b00000000000000000000001111110110 + b00000000000000000000010001011010 , b00000000000000000000010010111110 - b00000000000000000000001111110111 / b00000000000000000000010001011011 0 b00000000000000000000010010111111 1 #135 0! #140 1! b00000000000000000000010011000000 1 b00000000000000000000010001011100 0 b00000000000000000000001111111000 / b00000000000000000000010010111111 - b00000000000000000000010001011011 , b00000000000000000000001111110111 + b00000000000000000000000011011000 ) b00000000000000000000000001110100 ( b00000000000000000000000000010000 ' b00000000000000000000000011010111 % b00000000000000000000000001110011 $ b00000000000000000000000000001111 # b00000000000000000000000000001110 " #145 0! #150 1! b00000000000000000000000000001111 " b00000000000000000000000000010000 # b00000000000000000000000001110100 $ b00000000000000000000000011011000 % b00000000000000000000000000010001 ' b00000000000000000000000001110101 ( b00000000000000000000000011011001 ) b00000000000000000000001111111000 + b00000000000000000000010001011100 , b00000000000000000000010011000000 - b00000000000000000000001111111001 / b00000000000000000000010001011101 0 b00000000000000000000010011000001 1 #155 0! #160 1! b00000000000000000000010011000010 1 b00000000000000000000010001011110 0 b00000000000000000000001111111010 / b00000000000000000000010011000001 - b00000000000000000000010001011101 , b00000000000000000000001111111001 + b00000000000000000000000011011010 ) b00000000000000000000000001110110 ( b00000000000000000000000000010010 ' b00000000000000000000000011011001 % b00000000000000000000000001110101 $ b00000000000000000000000000010001 # b00000000000000000000000000010000 " #165 0! #170 1! b00000000000000000000000000010001 " b00000000000000000000000000010010 # b00000000000000000000000001110110 $ b00000000000000000000000011011010 % b00000000000000000000000000010011 ' b00000000000000000000000001110111 ( b00000000000000000000000011011011 ) b00000000000000000000001111111010 + b00000000000000000000010001011110 , b00000000000000000000010011000010 - b00000000000000000000001111111011 / b00000000000000000000010001011111 0 b00000000000000000000010011000011 1 #175 0! #180 1! b00000000000000000000010011000100 1 b00000000000000000000010001100000 0 b00000000000000000000001111111100 / b00000000000000000000010011000011 - b00000000000000000000010001011111 , b00000000000000000000001111111011 + b00000000000000000000000011011100 ) b00000000000000000000000001111000 ( b00000000000000000000000000010100 ' b00000000000000000000000011011011 % b00000000000000000000000001110111 $ b00000000000000000000000000010011 # b00000000000000000000000000010010 " #185 0! #190 1! b00000000000000000000000000010011 " b00000000000000000000000000010100 # b00000000000000000000000001111000 $ b00000000000000000000000011011100 % b00000000000000000000000000010101 ' b00000000000000000000000001111001 ( b00000000000000000000000011011101 ) b00000000000000000000001111111100 + b00000000000000000000010001100000 , b00000000000000000000010011000100 - b00000000000000000000001111111101 / b00000000000000000000010001100001 0 b00000000000000000000010011000101 1 #195 0! #200 1! b00000000000000000000010011000110 1 b00000000000000000000010001100010 0 b00000000000000000000001111111110 / b00000000000000000000010011000101 - b00000000000000000000010001100001 , b00000000000000000000001111111101 + b00000000000000000000000011011110 ) b00000000000000000000000001111010 ( b00000000000000000000000000010110 ' b00000000000000000000000011011101 % b00000000000000000000000001111001 $ b00000000000000000000000000010101 # b00000000000000000000000000010100 " #205 0! #210 1! b00000000000000000000000000010101 " b00000000000000000000000000010110 # b00000000000000000000000001111010 $ b00000000000000000000000011011110 % b00000000000000000000000000010111 ' b00000000000000000000000001111011 ( b00000000000000000000000011011111 ) b00000000000000000000001111111110 + b00000000000000000000010001100010 , b00000000000000000000010011000110 - b00000000000000000000001111111111 / b00000000000000000000010001100011 0 b00000000000000000000010011000111 1 #214 verilator-5.042/test_regress/t/t_time_param.v0000644000542200017500000000131015101701376021711 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `timescale 1ns/1ps module vip_snitch_cluster #(parameter realtime ClkPeriod = 10ns) (output logic clk_o); initial begin forever begin clk_o = 1; #(ClkPeriod/2); clk_o = 0; #(ClkPeriod/2); end end initial begin #(ClkPeriod*100); $write("*-* All Finished *-*\n"); $finish; end endmodule module t; logic clk; vip_snitch_cluster #( .ClkPeriod(1ns) ) vip ( .clk_o(clk) ); endmodule verilator-5.042/test_regress/t/t_lint_noreturn_param_bad.py0000755000542200017500000000106515101701376024660 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=['-Wall -Wno-DECLFILENAME'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_assert_comp_bad.py0000755000542200017500000000357215101701376023122 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--assert'], nc_flags2=['+assert'], vcs_flags2=['-assert svaext'], fails=True, expect_filename=test.golden_filename) test.extract(in_filename=test.top_filename, out_filename=test.root + "/docs/gen/ex_USERWARN_faulty.rst", regexp=r'\$warn.*User') test.extract(in_filename=test.top_filename, out_filename=test.root + "/docs/gen/ex_USERERROR_faulty.rst", regexp=r'\$error.*User') test.extract(in_filename=test.top_filename, out_filename=test.root + "/docs/gen/ex_USERINFO_faulty.rst", regexp=r'\$info.*User') test.extract(in_filename=test.top_filename, out_filename=test.root + "/docs/gen/ex_USERFATAL_faulty.rst", regexp=r'\$fatal.*User') test.extract(in_filename=test.golden_filename, out_filename=test.root + "/docs/gen/ex_USERWARN_msg.rst", regexp=r'USERWARN:.* User') test.extract(in_filename=test.golden_filename, out_filename=test.root + "/docs/gen/ex_USERERROR_msg.rst", regexp=r'USERERROR:.* User') test.extract(in_filename=test.golden_filename, out_filename=test.root + "/docs/gen/ex_USERINFO_msg.rst", regexp=r'-Info:.* User') test.extract(in_filename=test.golden_filename, out_filename=test.root + "/docs/gen/ex_USERFATAL_msg.rst", regexp=r'USERFATAL:.* User') test.passes() verilator-5.042/test_regress/t/t_trace_flag_off.py0000755000542200017500000000107615101701376022713 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Test that without --trace we get a message when turning on traces import vltest_bootstrap test.scenarios('vlt') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_udp_bad.out0000644000542200017500000000232415101701376021541 0ustar mahmoudyfreeshell%Warning-PINMISSING: t/t_udp_bad.v:10:10: Instance has missing pin: 'c_bad' 10 | udp_x x (a, b); | ^ t/t_udp_bad.v:14:28: ... Location of port declaration 14 | primitive udp_x (a_bad, b, c_bad); | ^~~~~ ... For warning description see https://verilator.org/warn/PINMISSING?v=latest ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message. %Error: t/t_udp_bad.v:14:18: Pin is not an in/out/inout/interface: 'a_bad' 14 | primitive udp_x (a_bad, b, c_bad); | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error-PINNOTFOUND: t/t_udp_bad.v:10:13: Pin not found: '__pinNumber1' 10 | udp_x x (a, b); | ^ ... For error description see https://verilator.org/warn/PINNOTFOUND?v=latest %Error: t/t_udp_bad.v:17:11: Multiple outputs not allowed in udp modules 17 | output c_bad; | ^~~~~ %Error: t/t_udp_bad.v:15:9: Only inputs and outputs are allowed in udp modules 15 | tri a_bad; | ^~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_math_tri.py0000755000542200017500000000073415101701376021601 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_link_delay2.v0000644000542200017500000000171715101701376023170 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package pk1; typedef struct packed { int AddrBits; int DataBits; } cfg_t; endpackage virtual class a_class_t #( parameter pk1::cfg_t CFG = 0 ); // verilator lint_off ASCRANGE localparam type addr_t = logic [CFG.AddrBits-1:0]; localparam type data_t = logic [CFG.DataBits-1:0]; // verilator lint_on ASCRANGE typedef struct packed { addr_t addr; data_t data; } pkt_t; endclass interface ifc #( parameter pk1::cfg_t CFG = 0 ); a_class_t #(CFG)::pkt_t p; endinterface module a_to_b #( parameter pk1::cfg_t ACFG = 0 ) ( ifc bus ); // sturf endmodule module t; localparam pk1::cfg_t ACFG = '{AddrBits : 64, DataBits : 64}; ifc #(.CFG(ACFG)) the_bus (); a_to_b #(ACFG) a_to_b (.bus(the_bus)); endmodule verilator-5.042/test_regress/t/t_preproc_inc_bad.out0000644000542200017500000000052515101701376023255 0ustar mahmoudyfreeshell%Error: t/t_preproc_inc_inc_bad.vh:11:1: syntax error, unexpected endmodule, expecting '(' 11 | endmodule | ^~~~~~~~~ t/t_preproc_inc_bad.v:10:1: ... note: In file included from 't_preproc_inc_bad.v' ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_foreach_type_bad.out0000644000542200017500000000175015101701376023423 0ustar mahmoudyfreeshell%Error: t/t_foreach_type_bad.v:19:18: Illegal 'foreach' loop on CLASSREFDTYPE 'Cls' data type : ... note: In instance 't' 19 | foreach (c[i]); | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_foreach_type_bad.v:21:18: Illegal 'foreach' loop on BASICDTYPE 'real' data type : ... note: In instance 't' 21 | foreach (r[i]); | ^ %Error: t/t_foreach_type_bad.v:23:21: Illegal 'foreach' loop on BASICDTYPE 'bit' data type : ... note: In instance 't' 23 | foreach (b[i, j, k]); | ^ %Error: t/t_foreach_type_bad.v:25:18: Illegal 'foreach' loop on BASICDTYPE 'real' data type : ... note: In instance 't' 25 | foreach (r[, i]); | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_interface_notpublic.v0000644000542200017500000000122215101701376023614 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Iztok Jeras. // SPDX-License-Identifier: CC0-1.0 interface intf (input wire clk, input wire rst); modport intf_modp (input clk, rst); endinterface module sub // verilator public_on (intf.intf_modp intf_port); always @ (posedge intf_port.clk) begin $write("*-* All Finished *-*\n"); $finish; end // verilator public_off endmodule module t(clk); input clk /*verilator public*/ ; logic rst; intf the_intf (.clk, .rst); sub the_sub (.intf_port (the_intf)); endmodule verilator-5.042/test_regress/t/t_covergroup_with_sample_namedargs.py0000755000542200017500000000070615101701376026601 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.passes() verilator-5.042/test_regress/t/t_vpi_get_public_rw_switch.py0000755000542200017500000000164015101701376025053 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.vm_prefix = "Vt_vpi_get" test.top_filename = "t/t_vpi_get.v" test.pli_filename = "t/t_vpi_get.cpp" test.compile(make_top_shell=False, make_main=False, make_pli=True, verilator_flags2=[ "--exe --vpi --public-flat-rw --prefix Vt_vpi_get --no-l2name", test.pli_filename ], iv_flags2=["-g2005-sv -D USE_VPI_NOT_DPI"], v_flags2=["+define+USE_VPI_NOT_DPI"]) test.execute(use_libvpi=True) test.passes() verilator-5.042/test_regress/t/t_timing_strobe.out0000644000542200017500000000004715101701376023010 0ustar mahmoudyfreeshellv = 1 v = 2 v = 3 *-* All Finished *-* verilator-5.042/test_regress/t/t_verilated_all_oldest.py0000755000542200017500000000115415101701376024150 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') # This test now does nothing, because using DRIVER_STD=oldest tends to blow up glibc. # Support for DRIVER_STD=oldest was removed from makefiles. This file remains for commentary. test.passes() verilator-5.042/test_regress/t/t_tri_pullup.v0000644000542200017500000000121415101701376021775 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2008 by Lane Brooks. // SPDX-License-Identifier: CC0-1.0 module top (input A, input OE, output X, output Y, output Z); pullup p1(Z); assign Z = OE ? A : 1'bz; pulldown p2(Y); assign Y = OE ? A : 1'bz; pass pass(.A(A), .OE(OE), .X(X)); pullup_module p(X); endmodule module pass (input A, input OE, inout X); io io(.A(A), .OE(OE), .X(X)); endmodule module io (input A, input OE, inout X); assign X = (OE) ? A : 1'bz; endmodule module pullup_module (output X); pullup p1(X); endmodule verilator-5.042/test_regress/t/t_assert_iff_bad1.py0000755000542200017500000000110515101701376022777 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = 't_assert_iff.v' test.compile(verilator_flags2=['--assert --cc --coverage-user -DFAIL1']) test.execute(fails=True) test.passes() verilator-5.042/test_regress/t/t_assert_past.py0000755000542200017500000000077115101701376022323 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--assert']) test.execute() test.passes() verilator-5.042/test_regress/t/t_vpi_memory.cpp0000644000542200017500000002321515101701376022306 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #ifdef IS_VPI #include "vpi_user.h" #include #else #include "verilated.h" #include "verilated_vcd_c.h" #include "verilated_vpi.h" #include "Vt_vpi_memory.h" #include "Vt_vpi_memory__Dpi.h" #include "svdpi.h" #endif #include #include #include extern "C" { #include } // These require the above. Comment prevents clang-format moving them #include "TestCheck.h" #include "TestSimulator.h" #include "TestVpi.h" #define DEBUG \ if (0) printf int errors = 0; //====================================================================== void _mon_check_range(const TestVpiHandle& handle, int size, int left, int right) { s_vpi_value value; value.format = vpiIntVal; value.value.integer = 0; // check size of object { int vpisize = vpi_get(vpiSize, handle); TEST_CHECK_EQ(vpisize, size); } // check coherency int coherency = 1; { TestVpiHandle iter_h = vpi_iterate(vpiRange, handle); while (TestVpiHandle range_h = vpi_scan(iter_h)) { int rangeSize; TestVpiHandle left_h, right_h; // get left hand side of range left_h = vpi_handle(vpiLeftRange, range_h); TEST_CHECK_NZ(left_h); vpi_get_value(left_h, &value); rangeSize = value.value.integer; // get right hand side of range right_h = vpi_handle(vpiRightRange, range_h); TEST_CHECK_NZ(right_h); vpi_get_value(right_h, &value); rangeSize = abs(rangeSize - value.value.integer) + 1; coherency *= rangeSize; } iter_h.freed(); } TEST_CHECK_EQ(coherency, size); } void _mem_check(const char* name, int size, int left, int right, int words) { s_vpi_value value; s_vpi_error_info e; vpi_printf((PLI_BYTE8*)"Check memory vpi (%s) ...\n", name); TestVpiHandle mem_h = vpi_handle_by_name((PLI_BYTE8*)TestSimulator::rooted(name), NULL); TEST_CHECK_NZ(mem_h); // check type int vpitype = vpi_get(vpiType, mem_h); if (vpitype != vpiRegArray && vpitype != vpiReg) { printf("%%Error: %s:%d vpiType neither vpiRegArray or vpiReg: %d\n", FILENM, __LINE__, vpitype); errors++; } std::string binStr; for (int i = words; i >= 1; i--) { for (int pos = size - 1; pos >= 0; pos--) { int posValue = (i >> pos) & 0x1; binStr += posValue ? "1" : "0"; } } // iterate and store if (vpitype == vpiRegArray) { _mon_check_range(mem_h, words, words, 1); TestVpiHandle iter_h = vpi_iterate(vpiReg, mem_h); int cnt = 0; while (TestVpiHandle lcl_h = vpi_scan(iter_h)) { value.format = vpiIntVal; value.value.integer = ++cnt; vpi_put_value(lcl_h, &value, NULL, vpiNoDelay); TEST_CHECK_Z(vpi_chk_error(&e)); // check size and range _mon_check_range(lcl_h, size, left, right); } iter_h.freed(); // IEEE 37.2.2 vpi_scan at end does a vpi_release_handle TEST_CHECK_EQ(cnt, words); // should be words addresses } else { int expSize = size * words; _mon_check_range(mem_h, expSize, words, 1); value.format = vpiBinStrVal; value.value.str = const_cast(binStr.c_str()); vpi_put_value(mem_h, &value, NULL, vpiNoDelay); TEST_CHECK_Z(vpi_chk_error(&e)); } if (vpitype == vpiRegArray) { // iterate and accumulate TestVpiHandle iter_h = vpi_iterate(vpiReg, mem_h); int cnt = 0; while (TestVpiHandle lcl_h = vpi_scan(iter_h)) { ++cnt; value.format = vpiIntVal; vpi_get_value(lcl_h, &value); TEST_CHECK_Z(vpi_chk_error(&e)); TEST_CHECK_EQ(value.value.integer, cnt); } iter_h.freed(); // IEEE 37.2.2 vpi_scan at end does a vpi_release_handle TEST_CHECK_EQ(cnt, words); // should be words addresses } else { value.format = vpiBinStrVal; vpi_get_value(mem_h, &value); TEST_CHECK_Z(vpi_chk_error(&e)); TEST_CHECK_EQ(std::string{value.value.str}, binStr); } // don't care for non verilator // (crashes on Icarus) if (TestSimulator::is_icarus()) { vpi_printf((PLI_BYTE8*)"Skipping property checks for simulator %s\n", TestSimulator::get_info().product); return; // Ok } { // make sure trying to get properties that don't exist // doesn't crash TestVpiHandle iter_h = vpi_iterate(vpiReg, mem_h); int should_be_undefined = vpi_get(vpiSize, iter_h); TEST_CHECK_EQ(should_be_undefined, vpiUndefined); should_be_undefined = vpi_get(vpiIndex, iter_h); TEST_CHECK_EQ(should_be_undefined, vpiUndefined); vpiHandle should_be_NULL = vpi_handle(vpiLeftRange, iter_h); TEST_CHECK_EQ(should_be_NULL, 0); should_be_NULL = vpi_handle(vpiRightRange, iter_h); TEST_CHECK_EQ(should_be_NULL, 0); should_be_NULL = vpi_handle(vpiScope, iter_h); TEST_CHECK_EQ(should_be_NULL, 0); } if (vpitype == vpiRegArray) { // check vpiRange TestVpiHandle iter_h = vpi_iterate(vpiRange, mem_h); TEST_CHECK_NZ(iter_h); TEST_CHECK_EQ(vpi_get(vpiType, iter_h), vpiIterator); TestVpiHandle lcl_h = vpi_scan(iter_h); TEST_CHECK_NZ(lcl_h); TEST_CHECK_EQ(vpi_get(vpiType, lcl_h), vpiRange); { TestVpiHandle side_h = vpi_handle(vpiLeftRange, lcl_h); TEST_CHECK_NZ(side_h); vpi_get_value(side_h, &value); TEST_CHECK_EQ(value.value.integer, 16); } { TestVpiHandle side_h = vpi_handle(vpiRightRange, lcl_h); TEST_CHECK_NZ(side_h); vpi_get_value(side_h, &value); TEST_CHECK_EQ(value.value.integer, 1); // check writing to vpiConstant vpi_put_value(side_h, &value, NULL, vpiNoDelay); TEST_CHECK_NZ(vpi_chk_error(&e)); } { // iterator should exhaust after 1 dimension TestVpiHandle zero_h = vpi_scan(iter_h); iter_h.freed(); // IEEE 37.2.2 vpi_scan at end does a vpi_release_handle TEST_CHECK_EQ(zero_h, 0); } } } struct params { const char* name; int size; int left; int right; int words; }; void _mon_check_memory() { // See note in t_vpi_get.cpp about static static struct params values[] = {{"mem0", 32, 31, 0, 16}, {"memp32", 32, 31, 0, 16}, {"memp31", 31, 30, 0, 16}, {"memp33", 33, 32, 0, 15}, {"memw", 32, 31, 0, 16}, {NULL, 0, 0, 0, 0}}; struct params* value = values; while (value->name) { _mem_check(value->name, value->size, value->left, value->right, value->words); value++; } } extern "C" int mon_check() { // Callback from initial block in monitor _mon_check_memory(); return errors; } //====================================================================== #ifdef IS_VPI static int mon_check_vpi() { TestVpiHandle href = vpi_handle(vpiSysTfCall, 0); s_vpi_value vpi_value; vpi_value.format = vpiIntVal; vpi_value.value.integer = mon_check(); vpi_put_value(href, &vpi_value, NULL, vpiNoDelay); return 0; } static s_vpi_systf_data vpi_systf_data[] = {{vpiSysFunc, vpiIntFunc, (PLI_BYTE8*)"$mon_check", (PLI_INT32(*)(PLI_BYTE8*))mon_check_vpi, 0, 0, 0}, 0}; // cver entry void vpi_compat_bootstrap(void) { p_vpi_systf_data systf_data_p; systf_data_p = &(vpi_systf_data[0]); while (systf_data_p->type != 0) vpi_register_systf(systf_data_p++); } // icarus entry void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0}; #else int main(int argc, char** argv) { const std::unique_ptr contextp{new VerilatedContext}; uint64_t sim_time = 1100; contextp->debug(0); contextp->commandArgs(argc, argv); // We're going to be checking for these errors so don't crash out contextp->fatalOnVpiError(0); const std::unique_ptr topp{new VM_PREFIX{contextp.get(), // Note null name - we're flattening it out ""}}; #ifdef VERILATOR #ifdef TEST_VERBOSE contextp->scopesDump(); #endif #endif #if VM_TRACE contextp->traceEverOn(true); VL_PRINTF("Enabling waves...\n"); VerilatedVcdC* tfp = new VerilatedVcdC; topp->trace(tfp, 99); tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); #endif topp->eval(); topp->clk = 0; contextp->timeInc(10); while (contextp->time() < sim_time && !contextp->gotFinish()) { contextp->timeInc(1); topp->eval(); VerilatedVpi::callValueCbs(); topp->clk = !topp->clk; // mon_do(); #if VM_TRACE if (tfp) tfp->dump(contextp->time()); #endif } if (!contextp->gotFinish()) { vl_fatal(FILENM, __LINE__, "main", "%Error: Timeout; never got a $finish"); } topp->final(); #if VM_TRACE if (tfp) tfp->close(); #endif return 0; } #endif verilator-5.042/test_regress/t/t_checker_unsup.out0000644000542200017500000000176715101701376023013 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_checker_unsup.v:31:12: Unsupported: 'checker' below unit-level 31 | checker checker_in_module; | ^~~~~~~~~~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_checker_unsup.v:37:12: Unsupported: 'checker' below unit-level 37 | checker checker_in_pkg; | ^~~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_checker_unsup.v:41:29: Unsupported: checker port variable default value 41 | checker Chk(input defaulted = 1'b0); | ^ %Error-UNSUPPORTED: t/t_checker_unsup.v:45:4: Unsupported: checker rand 45 | rand bit randed; | ^~~~ %Error-UNSUPPORTED: t/t_checker_unsup.v:67:4: Unsupported: default clocking identifier 67 | default clocking clk; | ^~~~~~~ %Error-UNSUPPORTED: t/t_checker_unsup.v:70:12: Unsupported: recursive 'checker' 70 | checker ChkChk; | ^~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_timing_nested_assignment_on_lhs.py0000755000542200017500000000113215101701376026406 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_net_delay.v" test.compile(timing_loop=True, verilator_flags2=["--timing"]) test.execute(all_run_flags=["+verilator+rand+reset+0"]) test.passes() verilator-5.042/test_regress/t/t_class_this_constructor.py0000755000542200017500000000073415101701376024573 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_disable_task_simple.py0000755000542200017500000000101315101701376023757 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(timing_loop=True, verilator_flags2=["--timing"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_bitsel_struct2.v0000644000542200017500000000304215101701376022547 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkb(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='b%x exp='b%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t; typedef struct packed { logic [3:2] a; logic [5:4][3:2] b; } ab_t; typedef ab_t [7:6] c_t; // array of structs typedef struct packed { c_t [17:16] d; } e_t; initial begin e_t e; `checkh($bits(ab_t),6); `checkh($bits(c_t),12); `checkh($bits(e_t),24); `checkh($bits(e), 24); `checkh($bits(e.d[17]),12); `checkh($bits(e.d[16][6]),6); `checkh($bits(e.d[16][6].b[5]),2); `checkh($bits(e.d[16][6].b[5][2]), 1); // e = 24'b101101010111010110101010; `checkb(e, 24'b101101010111010110101010); e.d[17] = 12'b111110011011; `checkb(e, 24'b111110011011010110101010); e.d[16][6] = 6'b010101; `checkb(e, 24'b111110011011010110010101); e.d[16][6].b[5] = 2'b10; `checkb(e, 24'b111110011011010110011001); e.d[16][6].b[5][2] = 1'b1; // $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_flag_lib_dpi.mk0000644000542200017500000000052715101701376022341 0ustar mahmoudyfreeshell# DESCRIPTION: Verilator: Makefile for Verilog Test module # # This file ONLY is placed under the Creative Commons Public Domain, for # any use, without warranty, 2023 by Shupei Fan. # SPDX-License-Identifier: CC0-1.0 include Vt_flag_lib_dpi.mk t_flag_lib_dpi_test: libVt_flag_lib_dpi.a libverilated.a $(LINK) $(LDFLAGS) $^ $(LDLIBS) -o $@ verilator-5.042/test_regress/t/t_func_wide.v0000644000542200017500000000171715101701376021551 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; reg [43:0] mi; wire [31:0] mo; muxtop um ( mi, mo); integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin mi <= 44'h1234567890; end if (cyc==3) begin if (mo !== 32'h12345678) $stop; $write("*-* All Finished *-*\n"); $finish; end end end endmodule module muxtop ( input [ 43:0 ] i, output reg [ 31:0 ] o ); always @ ( i[43:0] ) // Verify we ignore ranges on always statement sense lists o = MUX( i[39:0] ); function [31:0] MUX; input [39:0] XX ; begin MUX = XX[39:8]; end endfunction endmodule verilator-5.042/test_regress/t/t_dpi_open_vecval_c.cpp0000644000542200017500000002172515101701376023563 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "svdpi.h" #include #include #include // These require the above. Comment prevents clang-format moving them #include "TestCheck.h" //====================================================================== // clang-format off #if defined(VERILATOR) # include "Vt_dpi_open_vecval__Dpi.h" #elif defined(VCS) # include "../vc_hdrs.h" #elif defined(NC) # define NEED_EXTERNS // #elif defined(MS) // # define NEED_EXTERNS #else # error "Unknown simulator for DPI test" #endif // clang-format on #ifdef NEED_EXTERNS extern "C" { // If get ncsim: *F,NOFDPI: Function {foo} not found in default libdpi. // Then probably forgot to list a function here. extern int dpii_failure(); } #endif int errors = 0; int dpii_failure() { return errors; } #define TEST_MAX_NELEMS 1024 static void _invert(int bits, svBitVecVal o[], const svBitVecVal i[]) { for (int w = 0; w < SV_PACKED_DATA_NELEMS(bits); ++w) o[w] = ~i[w]; o[SV_PACKED_DATA_NELEMS(bits) - 1] &= SV_MASK(bits & 31); } static void _invert(int bits, svLogicVecVal o[], const svLogicVecVal i[]) { for (int w = 0; w < SV_PACKED_DATA_NELEMS(bits); ++w) { o[w].aval = ~i[w].aval; o[w].bval = 0; } o[SV_PACKED_DATA_NELEMS(bits) - 1].aval &= SV_MASK(bits & 31); o[SV_PACKED_DATA_NELEMS(bits) - 1].bval &= SV_MASK(bits & 31); } static bool _same(int bits, const svBitVecVal o[], const svBitVecVal i[]) { for (int w = 0; w < SV_PACKED_DATA_NELEMS(bits); ++w) { svBitVecVal mask = 0xffffffff; if (w == SV_PACKED_DATA_NELEMS(bits) - 1) mask = SV_MASK(bits & 31); if ((o[w] & mask) != (i[w] & mask)) return false; } return true; } static bool _same(int bits, const svLogicVecVal o[], const svLogicVecVal i[]) { for (int w = 0; w < SV_PACKED_DATA_NELEMS(bits); ++w) { svBitVecVal mask = 0xffffffff; if (w == SV_PACKED_DATA_NELEMS(bits) - 1) mask = SV_MASK(bits & 31); if ((o[w].aval & mask) != (i[w].aval & mask)) return false; if ((o[w].bval & mask) != (i[w].bval & mask)) return false; } return true; } void dpii_unused(const svOpenArrayHandle u) {} //====================================================================== static void _dpii_bit_vecval_ux(int bits, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o, const svOpenArrayHandle q) { printf("%s: bits=%d p=%d u=%d\n", __func__, bits, p, u); int dim = svDimensions(i); #ifndef NC // NC always returns zero and warns TEST_CHECK_HEX_EQ(dim, u); #endif if (SV_PACKED_DATA_NELEMS(bits) > TEST_MAX_NELEMS) { fprintf(stderr, "%%Error: Increase TEST_MAX_NELEMS\n"); abort(); } svBitVecVal vv[TEST_MAX_NELEMS]; svBitVecVal vv2[TEST_MAX_NELEMS]; svBitVecVal vo[TEST_MAX_NELEMS]; for (int a = svLow(i, 1); a <= svHigh(i, 1); ++a) { fflush(stdout); if (dim == 1) { svGetBitArrElemVecVal(vv, i, a); svGetBitArrElem1VecVal(vv2, i, a); TEST_CHECK_HEX_EQ(_same(bits, vv, vv2), true); _invert(bits, vo, vv); svPutBitArrElemVecVal(o, vo, a); svPutBitArrElem1VecVal(q, vo, a); } else { for (int b = svLow(i, 2); b <= svHigh(i, 2); ++b) { if (dim == 2) { svGetBitArrElemVecVal(vv, i, a, b); svGetBitArrElem2VecVal(vv2, i, a, b); TEST_CHECK_HEX_EQ(_same(bits, vv, vv2), true); _invert(bits, vo, vv); svPutBitArrElemVecVal(o, vo, a, b); svPutBitArrElem2VecVal(q, vo, a, b); } else { for (int c = svLow(i, 3); c <= svHigh(i, 3); ++c) { if (dim == 3) { svGetBitArrElemVecVal(vv, i, a, b, c); svGetBitArrElem3VecVal(vv2, i, a, b, c); TEST_CHECK_HEX_EQ(_same(bits, vv, vv2), true); _invert(bits, vo, vv); svPutBitArrElemVecVal(o, vo, a, b, c); svPutBitArrElem3VecVal(q, vo, a, b, c); } } } } } } fflush(stdout); } void dpii_bit_vecval_p1_u1(int bits, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o, const svOpenArrayHandle q) { _dpii_bit_vecval_ux(bits, p, u, i, o, q); } void dpii_bit61_vecval_p1_u1(int bits, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o, const svOpenArrayHandle q) { _dpii_bit_vecval_ux(bits, p, u, i, o, q); } void dpii_bit92_vecval_p1_u1(int bits, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o, const svOpenArrayHandle q) { _dpii_bit_vecval_ux(bits, p, u, i, o, q); } void dpii_bit12_vecval_p1_u2(int bits, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o, const svOpenArrayHandle q) { _dpii_bit_vecval_ux(bits, p, u, i, o, q); } void dpii_bit29_vecval_p1_u3(int bits, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o, const svOpenArrayHandle q) { _dpii_bit_vecval_ux(bits, p, u, i, o, q); } //====================================================================== static void _dpii_logic_vecval_ux(int bits, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o, const svOpenArrayHandle q) { printf("%s: bits=%d p=%d u=%d\n", __func__, bits, p, u); int dim = svDimensions(i); #ifndef NC // NC always returns zero and warns TEST_CHECK_HEX_EQ(dim, u); #endif if (SV_PACKED_DATA_NELEMS(bits) > TEST_MAX_NELEMS) { fprintf(stderr, "%%Error: Increase TEST_MAX_NELEMS\n"); abort(); } svLogicVecVal vv[TEST_MAX_NELEMS]; svLogicVecVal vv2[TEST_MAX_NELEMS]; svLogicVecVal vo[TEST_MAX_NELEMS]; for (int a = svLow(i, 1); a <= svHigh(i, 1); ++a) { fflush(stdout); if (dim == 1) { svGetLogicArrElemVecVal(vv, i, a); svGetLogicArrElem1VecVal(vv2, i, a); TEST_CHECK_HEX_EQ(_same(bits, vv, vv2), true); _invert(bits, vo, vv); svPutLogicArrElemVecVal(o, vo, a); svPutLogicArrElem1VecVal(q, vo, a); } else { for (int b = svLow(i, 2); b <= svHigh(i, 2); ++b) { if (dim == 2) { svGetLogicArrElemVecVal(vv, i, a, b); svGetLogicArrElem2VecVal(vv2, i, a, b); TEST_CHECK_HEX_EQ(_same(bits, vv, vv2), true); _invert(bits, vo, vv); svPutLogicArrElemVecVal(o, vo, a, b); svPutLogicArrElem2VecVal(q, vo, a, b); } else { for (int c = svLow(i, 3); c <= svHigh(i, 3); ++c) { if (dim == 3) { svGetLogicArrElemVecVal(vv, i, a, b, c); svGetLogicArrElem3VecVal(vv2, i, a, b, c); TEST_CHECK_HEX_EQ(_same(bits, vv, vv2), true); _invert(bits, vo, vv); svPutLogicArrElemVecVal(o, vo, a, b, c); svPutLogicArrElem3VecVal(q, vo, a, b, c); } } } } } } fflush(stdout); } void dpii_logic_vecval_p1_u1(int bits, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o, const svOpenArrayHandle q) { _dpii_logic_vecval_ux(bits, p, u, i, o, q); } void dpii_logic61_vecval_p1_u1(int bits, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o, const svOpenArrayHandle q) { _dpii_logic_vecval_ux(bits, p, u, i, o, q); } void dpii_logic92_vecval_p1_u1(int bits, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o, const svOpenArrayHandle q) { _dpii_logic_vecval_ux(bits, p, u, i, o, q); } void dpii_logic12_vecval_p1_u2(int bits, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o, const svOpenArrayHandle q) { _dpii_logic_vecval_ux(bits, p, u, i, o, q); } void dpii_logic29_vecval_p1_u3(int bits, int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o, const svOpenArrayHandle q) { _dpii_logic_vecval_ux(bits, p, u, i, o, q); } verilator-5.042/test_regress/t/t_type_match.py0000755000542200017500000000077715101701376022136 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["-Wno-UNOPTFLAT"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_timing_intra_assign_func.v0000644000542200017500000000137715101701376024653 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg [3:0] ia = 4'd1; wire signed [3:0] iufunc; // verilator lint_off WIDTH assign #2 iufunc = int_func(ia); // verilator lint_on WIDTH function [31:0] int_func; input [31:0] in; int_func = in * 2; endfunction always @(iufunc) begin if ($time > 0) begin $display("time: %0t, iufunc: %0d", $time, iufunc); if (iufunc != 4'd4) $stop; if ($time != 3) $stop; end end initial begin #1; ia = 4'd2; #10; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_func_bad_width.out0000644000542200017500000000201515101701376023100 0ustar mahmoudyfreeshell%Warning-WIDTHEXPAND: t/t_func_bad_width.v:13:13: Operator FUNCREF 'MUX' expects 40 bits on the Function Argument, but Function Argument's VARREF 'in' generates 39 bits. : ... note: In instance 't' 13 | out = MUX (in); | ^~~ ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. %Warning-WIDTHTRUNC: t/t_func_bad_width.v:13:11: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's FUNCREF 'MUX' generates 32 bits. : ... note: In instance 't' 13 | out = MUX (in); | ^ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_unpacked_struct_redef.py0000755000542200017500000000073415101701376024335 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_chg_first.py0000755000542200017500000000073415101701376021742 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_latch_3.py0000755000542200017500000000070315101701376022331 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint() test.passes() verilator-5.042/test_regress/t/t_trace_event.v0000644000542200017500000000133415101701376022100 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" module t; event ev_test; int i; bit toggle = 1'b0; bit clk; always #10 clk = ~clk; initial begin @(posedge clk); @(ev_test); toggle = ~toggle; end initial begin $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); $dumpvars(0, top); for(i=0; i < 10; i++) begin @(posedge clk); if (i == 5) ->ev_test; end @(posedge clk); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_lint_importstar_bad.out0000644000542200017500000000061215101701376024201 0ustar mahmoudyfreeshell%Warning-IMPORTSTAR: t/t_lint_importstar_bad.v:11:8: 'import::*' in $unit scope may pollute global namespace 11 | import defs::*; | ^~~~ ... For warning description see https://verilator.org/warn/IMPORTSTAR?v=latest ... Use "/* verilator lint_off IMPORTSTAR */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_xml_deprecated_bad.out0000644000542200017500000000047315101701376023734 0ustar mahmoudyfreeshell%Warning-DEPRECATED: Option --xml-only is deprecated, move to --json-only ... For warning description see https://verilator.org/warn/DEPRECATED?v=latest ... Use "/* verilator lint_off DEPRECATED */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_dist_install.py0000755000542200017500000000310715101701376022460 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') if not os.path.exists(test.root + "/.git"): test.skip("Not in a git repository") cwd = os.getcwd() destdir = cwd + "/" + test.obj_dir # Start clean test.run(cmd=["rm -rf " + destdir + " && mkdir -p " + destdir], check_finished=False) # Install into temp area print("Install...") test.run( cmd=["cd " + test.root + " && " + os.environ["MAKE"] + " DESTDIR=" + destdir + " install-all"], check_finished=False) # Check we can run a test # Unfortunately the prefix was hardcoded in the exec at a different place, # so we can't do much here. #print("Check install...") # Uninstall print("Uninstall...\n") test.run( cmd=["cd " + test.root + " && " + os.environ["MAKE"] + " DESTDIR=" + destdir + " uninstall"], check_finished=False) # Check empty files = [] finds = test.run_capture("find " + destdir + " -type f -print") for filename in finds.split(): if re.search(r'\.status', filename): # Made by driver.py, not Verilator continue print("\tLEFT: " + filename) filename = re.sub(r'^' + re.escape(cwd), '.', filename) files.append(filename) if len(files) > 0: test.error("Uninstall missed files: " + ' '.join(files)) test.passes() verilator-5.042/test_regress/t/t_parse_sync_bad2.py0000755000542200017500000000076315101701376023032 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_enum.v0000644000542200017500000000064715101701376021740 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; class Cls; typedef enum {A = 10, B = 20, C = 30} en_t; endclass initial begin Cls c; if (c.A != 10) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_let.v0000644000542200017500000000173415101701376020371 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package Pkg; let P = 11; let PP(a) = 30 + a; endpackage module t; let A = 10; let B() = 20; let C(a) = 30 + a; let D(a, b) = 30 + a + b; let E(a=1, b=7) = 30 + a + b; let F(untyped a) = 30 + a; initial begin if (A != 10) $stop; if (A() != 10) $stop; if (B != 20) $stop; if (B() != 20) $stop; if (C(1) != (30 + 1)) $stop; if (C(.a(1)) != (30 + 1)) $stop; if (D(1, 2) != (30 + 1 + 2)) $stop; if (D(.a(1), .b(2)) != (30 + 1 + 2)) $stop; if (E(2) != (30 + 2 + 7)) $stop; if (E(.b(1)) != (30 + 1 + 1)) $stop; if (F(1) != (30 + 1)) $stop; if (Pkg::P != 11) $stop; if (Pkg::PP(6) != (30 + 6)) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_interface_virtual.out0000644000542200017500000000052215101701376023647 0ustar mahmoudyfreeshellva==vb? 1 va!=vb? 0 va==vb? 0 va!=vb? 1 va.addr=aa va.data=11 ia.addr=aa ia.data=11 vb.addr=bb vb.data=22 ib.addr=bb ib.data=22 ca.fa.addr=a0 ca.fa.data=11 ca.fa.addr=b0 ca.fb.data=22 cb.fa.addr=b0 cb.fa.data=22 cb.fa.addr=a0 cb.fb.data=11 gen.x[0].addr=a0 gen.x[1].addr=b0 gen='{x:'{top.t.ia, top.t.ib, null, null}} *-* All Finished *-* verilator-5.042/test_regress/t/t_process_compare.v0000644000542200017500000000164315101701376022770 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class A; local process proc2; task run; process proc1; proc1 = process::self(); if (proc2 == null) begin proc2 = proc1; end else if (proc1 == proc2) begin $display("process is equal %p %p", proc1, proc2); end else begin $display("process is not equal (using ! ==) %p %p", proc1, proc2); $stop; end if (proc2 != null && proc1 != proc2) begin $display("process is not equal (using !=) %p %p", proc1, proc2); $stop; end endtask endclass module t; initial begin A a; a = new(); a.run(); a.run(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_array_backw_index_bad.out0000644000542200017500000000367615101701376024440 0ustar mahmoudyfreeshell%Error: t/t_array_backw_index_bad.v:17:19: Slice selection '[1:3]' has reversed range order versus data type's '[3:0]' : ... note: In instance 't' 17 | array_assign[1:3] = '{32'd4, 32'd3, 32'd2}; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_array_backw_index_bad.v:18:20: Slice selection '[3:1]' has reversed range order versus data type's '[0:3]' : ... note: In instance 't' 18 | larray_assign[3:1] = '{32'd4, 32'd3, 32'd2}; | ^ %Error: t/t_array_backw_index_bad.v:19:20: Slice selection '[4:6]' has reversed range order versus data type's '[6:3]' : ... note: In instance 't' 19 | array_assign2[4:6] = '{32'd4, 32'd3, 32'd2}; | ^ %Error: t/t_array_backw_index_bad.v:20:21: Slice selection '[6:4]' has reversed range order versus data type's '[3:6]' : ... note: In instance 't' 20 | larray_assign2[6:4] = '{32'd4, 32'd3, 32'd2}; | ^ %Error: t/t_array_backw_index_bad.v:22:19: Slice selection index '[4:3]' outside data type's '[3:0]' : ... note: In instance 't' 22 | array_assign[4:3] = '{32'd4, 32'd3}; | ^ %Error: t/t_array_backw_index_bad.v:23:19: Slice selection index '[1:-1]' outside data type's '[3:0]' : ... note: In instance 't' 23 | array_assign[1:-1] = '{32'd4, 32'd3}; | ^ %Error: t/t_array_backw_index_bad.v:23:28: Assignment pattern missed initializing elements: -1 : ... note: In instance 't' 23 | array_assign[1:-1] = '{32'd4, 32'd3}; | ^~ %Error: Exiting due to verilator-5.042/test_regress/t/t_implements_typed.v0000644000542200017500000000164515101701376023170 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface class Icls; typedef int int_t; pure virtual function int ifunc(int_t val); endclass interface class IclsExt extends Icls; // Typedefs seen by extended, but not implements (need ::) pure virtual function int ifuncExt(int_t v1, int_t v2); endclass class IclsImp implements Icls; function int ifunc(Icls::int_t val); return val + 1; endfunction endclass // Bad, already have error for // class IclsImp2 implements Icls; // function int ifunc(int_t val); // Bad int_t not typedefed // endfunction // endclass module t; IclsImp i1; initial begin i1 = new; if (i1.ifunc(2) != 3) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_sys_file_eof.v0000644000542200017500000000151215101701376022245 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t; integer f; integer i; integer j; initial begin f = $fopen("/does-not-exist", "r"); `checkd(f, 0); i = $fscanf(f, "check %d", j); `checkd(i, -1); i = $fgetc(f); `checkd(i, -1); i = $ftell(f); `checkd(i, -1); i = $rewind(f); `checkd(i, -1); i = $fseek(f, 0, 0); `checkd(i, -1); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_array_pattern_enum.py0000755000542200017500000000077215101701376023673 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.skip('Needs clang fix') test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_gate_delay_unsup.py0000755000542200017500000000123115101701376023313 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.top_filename = "t/t_gate_basic.v" test.lint(verilator_flags2=[ "--lint-only --timing -Wall", "-Wno-DECLFILENAME -Wno-SPECIFYIGN -Wno-UNUSED" ], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_trace_enum.v0000644000542200017500000000114015101701376021716 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef enum logic [1:0] {VAL_A, VAL_B, VAL_C, VAL_D} state_t; interface MyIntf; state_t state; endinterface module t (clk); input clk; MyIntf #() sink (); state_t v_enumed; typedef enum logic [1:0] {VAL_X, VAL_Y, VAL_Z} other_state_t; other_state_t v_other_enumed; always @ (posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_inst_nansi_mism_bad.out0000644000542200017500000000233415101701376024144 0ustar mahmoudyfreeshell%Error: t/t_inst_nansi_mism_bad.v:13:10: Non-ANSI I/O declaration of signal conflicts with type declaration: 'bad1' 13 | output [15:0] bad1; | ^ t/t_inst_nansi_mism_bad.v:14:3: ... Location of other declaration 14 | shortint bad1; | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_inst_nansi_mism_bad.v:16:10: Non-ANSI I/O declaration of signal conflicts with type declaration: 'bad2' 16 | output [31:0] bad2; | ^ t/t_inst_nansi_mism_bad.v:17:3: ... Location of other declaration 17 | T bad2; | ^ %Error: t/t_inst_nansi_mism_bad.v:19:10: Non-ANSI I/O declaration of signal conflicts with type declaration: 'bad3' 19 | output [3:0] bad3; | ^ t/t_inst_nansi_mism_bad.v:20:3: ... Location of other declaration 20 | reg [7:0] bad3; | ^~~ %Error: t/t_inst_nansi_mism_bad.v:22:3: Non-ANSI I/O declaration of signal conflicts with type declaration: 'bad4' 22 | reg [7:0] bad4; | ^~~ t/t_inst_nansi_mism_bad.v:23:10: ... Location of other declaration 23 | output [3:0] bad4; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_foreach_noivar.py0000755000542200017500000000077615101701376022765 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['-Wno-NOEFFECT']) test.execute() test.passes() verilator-5.042/test_regress/t/t_dfg_peephole_off_all.py0000755000542200017500000000075315101701376024076 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap import runpy test.scenarios('vlt_all') runpy.run_path("t/t_dfg_peephole.py", globals()) verilator-5.042/test_regress/t/t_interface_generic_modport_bad.py0000755000542200017500000000102515101701376025772 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=['--timing'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_math_div0.v0000644000542200017500000000156315101701376021460 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Outputs y, d2, m2, d3, m3 ); output [3:0] y; output [31:0] d2; output [31:0] m2; output [63:0] d3; output [63:0] m3; // bug775 // verilator lint_off WIDTH assign y = ((0/0) ? 1 : 2) % 0; // bug2460 reg [31:0] b; assign d2 = $signed(32'h80000000) / $signed(b); assign m2 = $signed(32'h80000000) % $signed(b); reg [63:0] b3; assign d3 = $signed(64'h80000000_00000000) / $signed(b3); assign m3 = $signed(64'h80000000_00000000) % $signed(b3); initial begin b = 32'hffffffff; b3 = 64'hffffffff_ffffffff; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_verilated_header.py0000755000542200017500000000105015101701376023251 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.compile(verilator_flags2=["+incdir+" + os.environ["VERILATOR_ROOT"] + "/include"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_union_unpacked.py0000755000542200017500000000073415101701376022774 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_bitsel_concat.py0000755000542200017500000000073415101701376022603 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_stmtdly_bad.v0000644000542200017500000000044415101701376023136 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin #100 $finish; //<--- Warning end endmodule verilator-5.042/test_regress/t/t_interface_generic_modport_task2.py0000755000542200017500000000077115101701376026277 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--timing']) test.execute() test.passes() verilator-5.042/test_regress/t/t_gen_lsb.py0000755000542200017500000000073415101701376021403 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_sys_monitor.py0000755000542200017500000000100015101701376022342 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_continue_do_while_bad.v0000644000542200017500000000071415101701376024106 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ clk ); input clk; function void infinite_loop; do begin continue; end while (1); endfunction always @(posedge clk) begin infinite_loop(); $stop; end endmodule verilator-5.042/test_regress/t/t_clk_concat4.v0000644000542200017500000000405015101701376021763 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty. // SPDX-License-Identifier: CC0-1.0 module some_module ( input wrclk ); logic [ 1 : 0 ] some_state; logic [1:0] some_other_state; always @(posedge wrclk) begin case (some_state) 2'b11: if (some_other_state == 0) some_state <= 2'b00; default: $display ("This is a display statement"); endcase if (wrclk) some_other_state <= 0; end endmodule `define BROKEN module t1( input [3:0] i_clks, input i_clk0, input i_clk1 ); generate genvar i; for (i = 0; i < 2; i = i + 1) begin: a_generate_block some_module some_module ( `ifdef BROKEN .wrclk (i_clks[3]) `else .wrclk (i_clk1) `endif ); end endgenerate endmodule module t2( input [2:0] i_clks, input i_clk0, input i_clk1, input i_clk2, input i_data ); logic [3:0] the_clks; logic data_q; assign the_clks[3] = i_clk1; assign the_clks[2] = i_clk2; assign the_clks[1] = i_clk1; assign the_clks[0] = i_clk0; always @(posedge i_clk0) begin data_q <= i_data; end t1 t1 ( .i_clks (the_clks), .i_clk0 (i_clk0), .i_clk1 (i_clk1) ); endmodule module t( input clk0 /*verilator clocker*/, input clk1 /*verilator clocker*/, input clk2 /*verilator clocker*/, input data_in ); logic [2:0] clks; assign clks = {1'b0, clk1, clk0}; t2 t2 ( .i_clks (clks), .i_clk0 (clk0), .i_clk1 (clk1), .i_clk2 (clk2), .i_data (data_in) ); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_var_dup2_bad.v0000644000542200017500000000065415101701376022135 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Illegal with ANSI Verilog 2001 style ports module t ( output bad_o_w, output bad_o_r); wire bad_o_w; reg bad_o_r; wire bad_w_r; reg bad_w_r; wire bad_r_w; reg bad_r_w; endmodule verilator-5.042/test_regress/t/t_time_vpi_1ms10ns.out0000644000542200017500000000173415101701376023245 0ustar mahmoudyfreeshell:: In top.t Time scale of t is 1ms / 10ns [6000000] time%0d=60 123%0t=12300000 dig%0t=543200000 dig%0d=5432 rdig%0t=543210988 rdig%0f=5432.109877 acc%0t=1234567890123456789000000 acc%0d=12345678901234567890 [60000000.000000ns] time%0d=60 123%0t=123000000.000000ns dig%0t=5432000000.000000ns dig%0d=5432 rdig%0t=5432109876.543210ns rdig%0f=5432.109877 acc%0t=12345678901234567890000000.000000ns acc%0d=12345678901234567890 [60000000.000000ns] stime%0t=60000000.000000ns stime%0d=60 stime%0f=60.000000 [60000000.000000ns] rtime%0t=60000000.000000ns rtime%0d=60 rtime%0f=60.000000 global svGetTime = 0 0,6000000 global svGetTimeUnit = 0 -3 svGetTmePrecision = 0 -8 global vpiSimTime = 0,6000000 vpiScaledRealTime = 6e+06 global vpiTimeUnit = -3 vpiTimePrecision = -8 top.t svGetTime = 0 0,6000000 top.t svGetTimeUnit = 0 -3 svGetTmePrecision = 0 -8 top.t vpiSimTime = 0,6000000 vpiScaledRealTime = 60 top.t vpiTimeUnit = -3 vpiTimePrecision = -8 *-* All Finished *-* verilator-5.042/test_regress/t/t_vpi_dump.py0000755000542200017500000000202315101701376021606 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(make_top_shell=False, make_main=False, make_pli=True, iv_flags2=["-g2005-sv"], verilator_flags2=[ "--exe --vpi --public-flat-rw --no-l2name", test.pli_filename, "t/TestVpiMain.cpp" ], make_flags=['CPPFLAGS_ADD=-DVL_NO_LEGACY']) test.execute(use_libvpi=True, expect_filename=test.golden_filename, xrun_run_expect_filename=re.sub(r'\.out$', '.xrun.out', test.golden_filename), iv_run_expect_filename=re.sub(r'\.out$', '.iv.out', test.golden_filename)) test.passes() verilator-5.042/test_regress/t/t_forceable_net.cpp0000644000542200017500000000653215101701376022713 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 #include "verilatedos.h" #include "verilated.h" #include #if VM_TRACE #include "verilated_vcd_c.h" #endif #include VM_PREFIX_INCLUDE #include VM_PREFIX_ROOT_INCLUDE int main(int argc, char** argv) { const std::unique_ptr contextp{new VerilatedContext}; contextp->debug(0); contextp->commandArgs(argc, argv); srand48(5); const std::unique_ptr topp{new VM_PREFIX{"top"}}; topp->clk = false; topp->rst = true; topp->eval(); #if VM_TRACE contextp->traceEverOn(true); std::unique_ptr tfp{new VerilatedVcdC}; topp->trace(tfp.get(), 99); tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); tfp->dump(contextp->time()); #endif contextp->timeInc(5); topp->clk = true; topp->eval(); topp->rst = false; topp->eval(); #if VM_TRACE tfp->dump(contextp->time()); #endif contextp->timeInc(5); while (contextp->time() < 1000 && !contextp->gotFinish()) { topp->clk = !topp->clk; topp->eval(); if (topp->clk) { bool needsSecondEval = false; if (topp->cyc == 3) { topp->rootp->t__DOT__net_1__VforceEn = 1; topp->rootp->t__DOT__net_1__VforceVal = 0; needsSecondEval = true; } if (topp->cyc == 5) { topp->rootp->t__DOT__net_1__VforceVal = 1; needsSecondEval = true; } if (topp->cyc == 8) { topp->rootp->t__DOT__net_1__VforceEn = 0; needsSecondEval = true; } if (topp->cyc == 4) { topp->rootp->t__DOT__net_8__VforceEn = 0xff; topp->rootp->t__DOT__net_8__VforceVal = 0x5f; needsSecondEval = true; } if (topp->cyc == 6) { topp->rootp->t__DOT__net_8__VforceVal = 0xf5; needsSecondEval = true; } if (topp->cyc == 9) { topp->rootp->t__DOT__net_8__VforceEn = 0; needsSecondEval = true; } if (topp->cyc == 10) { topp->rootp->t__DOT__net_1__VforceEn = 1; topp->rootp->t__DOT__net_8__VforceEn = 0xff; topp->rootp->t__DOT__net_1__VforceVal = 1; topp->rootp->t__DOT__net_8__VforceVal = 0x5a; needsSecondEval = true; } if (topp->cyc == 12) { topp->rootp->t__DOT__net_1__VforceVal = 0; topp->rootp->t__DOT__net_8__VforceVal = 0xa5; needsSecondEval = true; } if (topp->cyc == 14) { topp->rootp->t__DOT__net_1__VforceEn = 0; topp->rootp->t__DOT__net_8__VforceEn = 0; needsSecondEval = true; } if (needsSecondEval) topp->eval(); } #if VM_TRACE tfp->dump(contextp->time()); #endif contextp->timeInc(5); } if (!contextp->gotFinish()) { vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); } topp->final(); #if VM_TRACE tfp->close(); #endif return 0; } verilator-5.042/test_regress/t/t_param_chain.v0000644000542200017500000000152615101701376022046 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; function integer max2; input integer x; input integer y; begin begin : blk automatic int temp; temp = x; end end max2 = ( x > y ) ? x : y; endfunction function integer max4; input integer x; input integer y; input integer z; input integer w; // MAX2 is used multiple times max4 = max2( max2( x, y ), max2( z, w ) ); endfunction localparam MAX4 = max4( 1, 1, 0, 0 ); initial begin if (MAX4 != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_queue_bounded.v0000644000542200017500000000176615101701376022436 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; localparam TWO = 2; int q[$ : TWO]; // Shall not go higher than [2], i.e. size 3 initial begin q.push_front(3); if (q.size() != 1) $stop; q.push_front(2); if (q.size() != 2) $stop; q.push_front(1); if (q.size() != 3) $stop; q.push_front(0); if (q.size() != 3) $stop; q[3] = -1; if (q.size() != 3) $stop; if (q[0] != 0) $stop; if (q[1] != 1) $stop; if (q[2] != 2) $stop; q.delete(); q.push_back(0); q.push_back(1); q.push_back(2); if (q.size() != 3) $stop; q.push_back(3); if (q.size() != 3) $stop; if (q[0] != 0) $stop; if (q[1] != 1) $stop; if (q[2] != 2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_preproc_elsif_bad.v0000644000542200017500000000045015101701376023241 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 //See bug289 `elsif A `endif `else `endif `error `include module t; endmodule verilator-5.042/test_regress/t/t_const_slicesel_bad.py0000755000542200017500000000076715101701376023617 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_mod_interface_clocking_bad.py0000755000542200017500000000077115101701376025251 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_real_param.py0000755000542200017500000000073415101701376022075 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_typedef_fwd_nested.v0000644000542200017500000000211515101701376023441 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 typedef class Bar; typedef Bar Baz; typedef class Quux; typedef Quux #(16, 32) Quux_t; typedef Quux_t Quuux_t; module t; initial begin Bar::Qux::boo(1); Baz::Qux::boo(1); Quux_t::Qux::boo(1); Quuux_t::Qux::boo(1); if (!Bar::Qux::finish) $stop; if (!Quux_t::Qux::finish) $stop; if (!Quuux_t::Qux::finish) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule class Foo #(type T); static logic finish = 0; static function void boo(input logic rec); if (rec) Bar::Qux::boo(0); finish = 1; endfunction endclass class Goo #(type T); function void goo(); T::Qux::boo(1); endfunction endclass class Bar; typedef Foo#(Bar) Qux; endclass class Quux #(PARA_A = 1, PARA_B = 2); typedef Quux #(PARA_A, PARA_B) this_t; typedef Foo#(this_t) Qux; endclass verilator-5.042/test_regress/t/t_split_var_xref.v0000644000542200017500000000111615101701376022626 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2025 by Antmicro // SPDX-License-Identifier: CC0-1.0 module child ( input logic test_out ); initial begin #1; if (test_out != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module parent; logic [1:0] test_out; child u0 (.test_out(test_out[0])); endmodule interface my_if; initial begin t.test_parent.test_out = 1; end endinterface module t; parent test_parent (); my_if intf (); endmodule verilator-5.042/test_regress/t/t_compiler_include.v0000644000542200017500000000065015101701376023116 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2024 by Antmicro. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (input logic[31:0] in, output logic[31:0] out); assign out = in; endmodule verilator-5.042/test_regress/t/t_interface_generic_function_bad.v0000644000542200017500000000101615101701376025745 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 interface inf; int v; endinterface module GenericModule (interface a); initial begin #1; if (a.get() != 4) $stop; end endmodule module t; inf inf_inst(); GenericModule genericModule (inf_inst); initial begin inf_inst.v = 4; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_waiveroutput_roundtrip.py0000755000542200017500000000144415101701376024655 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') out_filename = test.obj_dir + "/" + test.name + ".waiver_gen.out" waiver_filename = test.obj_dir + "/" + test.name + "_waiver.vlt" test.lint(v_flags2=['-Wall', '-Wno-fatal', '--waiver-output', out_filename]) test.file_sed(out_filename, waiver_filename, lambda line: re.sub(r'\/\/ lint_off', 'lint_off', line)) test.lint(v_flags2=[waiver_filename]) test.passes() verilator-5.042/test_regress/t/t_class_scope_import_bad.v0000644000542200017500000000047115101701376024300 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package pkg; endpackage class genericClass; import pkg::*; endclass module tb_top(); endmodule verilator-5.042/test_regress/t/t_class_copy_bad.out0000644000542200017500000000057315101701376023114 0ustar mahmoudyfreeshell%Error: t/t_class_copy_bad.v:19:16: New-as-copier passed different data type 'CLASSREFDTYPE 'Cls'' than expected 'CLASSREFDTYPE 'Other'' : ... note: In instance 't' 19 | c1 = new co; | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_udp_noname.py0000755000542200017500000000073415101701376022117 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_const_bitoptree_bug3096.py0000755000542200017500000000107215101701376024350 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(make_top_shell=False, make_main=False, v_flags2=["--exe", test.pli_filename]) test.execute(check_finished=False) test.passes() verilator-5.042/test_regress/t/t_property_fail_2_bad.py0000755000542200017500000000121415101701376023672 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_property.v" test.compile(v_flags2=['+define+FAIL_ASSERT_2'], verilator_flags2=['--assert --cc']) test.execute(fails=True) test.file_grep(test.run_log_filename, r"'assert' failed") test.passes() verilator-5.042/test_regress/t/t_flag_werror_bad1.py0000755000542200017500000000103315101701376023163 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_flag_werror.v" test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_trace_abort.py0000755000542200017500000000111015101701376022244 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(verilator_flags2=['--cc --trace-vcd']) test.execute(fails=True) test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_flag_prefix.py0000755000542200017500000000324315101701376022256 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile( verilator_flags2=[ "--prefix t_flag_prefix", # should be overridden "--prefix Vprefix", "--exe", "--main", "--stats", "--build" ], verilator_make_cmake=False, verilator_make_gmake=False) test.execute(executable=test.obj_dir + "/Vprefix") def check_files(): for path in test.glob_some(test.obj_dir + "/*"): filename = path[(len(test.obj_dir) + 1):] if re.search(r'\.log$', filename): continue if re.search(r't_flag_prefix', filename): test.error("bad filename '" + filename + "'") continue if re.search(r'^(.*\.(o|a)|Vprefix)$', filename): continue if re.search(r'\.gcda$', filename): continue if re.search(r'\.gcno$', filename): continue with open(path, 'r', encoding="utf8") as fh: for line in fh: line = re.sub(r'--prefix V?t_flag_prefix', '', line) line = re.sub(r'obj_vlt\/t_flag_prefix', '', line) line = re.sub(r't\/t_flag_prefix\.v', '', line) if re.search(r't_flag_prefix', line): test.error(filename + ": bad line: " + line) check_files() test.passes() verilator-5.042/test_regress/t/t_func_const_packed_array_bad.py0000755000542200017500000000076615101701376025453 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_force_rhs_ref_multiple.py0000755000542200017500000000076315101701376024515 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_waiveroutput_multiline.py0000755000542200017500000000140015101701376024621 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_waiveroutput.v" out_filename = test.obj_dir + "/" + test.name + ".waiver_gen.out" waiver_filename = "t/t_waiveroutput.vlt" test.lint(v_flags2=[ waiver_filename, '-Wall', '-Wno-fatal', '--waiver-multiline', '--waiver-output', out_filename ]) test.files_identical(out_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_assert_casez.py0000755000542200017500000000077115101701376022461 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--assert']) test.execute() test.passes() verilator-5.042/test_regress/t/t_vthread.py0000755000542200017500000000330615101701376021425 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = test.obj_dir + "/t_vthread.v" def gen(filename, n): with open(filename, 'w', encoding="utf8") as fh: fh.write("// Generated by t_vthread.py\n") fh.write("module genmod #(int val = 0)(clk, o);\n") fh.write(" input clk;\n") fh.write(" output int o;\n") fh.write(" always @ (posedge clk) begin\n") fh.write(" o <= val;\n") fh.write(" end\n") fh.write("endmodule\n") fh.write("module t (clk, o);\n") fh.write(" input clk;\n") fh.write(" output int o;\n") for i in range(0, n + 1): fh.write(" int r" + str(i) + ";\n") fh.write(" genmod #(.val(" + str(i) + ")) rm" + str(i) + " (.clk, .o(r" + str(i) + "));\n") fh.write(" always @ (posedge clk) begin\n") fh.write(" o <= r" + str(n) + ";\n") fh.write(' $write("*-* All Finished *-*\\n");' + "\n") fh.write(' $finish;' + "\n") fh.write(" end\n") fh.write("endmodule\n") gen(test.top_filename, 6000) test.compile( # use --trace-vcd to generate trace files that can be parallelized verilator_flags2=["--stats --trace-vcd --verilate-jobs 2"]) test.execute() test.file_grep(test.stats, r'Verilate jobs: 2') test.passes() verilator-5.042/test_regress/t/t_display_realtime.py0000755000542200017500000000073415101701376023321 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_force_subnet.v0000644000542200017500000000260315101701376022257 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module t(/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; logic [7:0] subnet; sub1 sub1(.*); // Test loop always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 10) begin `checkh(subnet, 8'h11); force sub1.subnet = 8'h01; // sub1.subnet *not* the same as subnet end else if (cyc == 11) begin `checkh(subnet, 8'h01); force subnet = 8'h10; // sub1.subnet *not* the same as subnet end else if (cyc == 12) begin `checkh(subnet, 8'h10); release subnet; // sub1.subnet *not* same as subnet end else if (cyc == 13) begin `checkh(subnet, 8'h01); release sub1.subnet; end else if (cyc == 13) begin `checkh(subnet, 8'h11); end // else if (cyc == 99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module sub1(output logic [7:0] subnet); assign subnet = 8'h11; endmodule verilator-5.042/test_regress/t/t_display_concat.out0000644000542200017500000000005115101701376023132 0ustar mahmoudyfreeshellabcd=abcd ab0d=ab0d *-* All Finished *-* verilator-5.042/test_regress/t/t_array_pattern_bad2.out0000644000542200017500000000050515101701376023705 0ustar mahmoudyfreeshell%Error: t/t_array_pattern_bad2.v:22:16: Multiple '{ default: } clauses : ... note: In instance 't' 22 | myinfo = '{default: '0, | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_cover_trace_always.v0000644000542200017500000000130415101701376023452 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // See bug5821 `define STRINGIFY(x) `"x`" module imply(input logic p, input logic q, output logic r); always_comb begin r = p | q; end endmodule module t(); logic p; logic q; logic r; imply dut(.p(p), .q(q), .r(r)); initial begin $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); $dumpvars(); // p = 1; q = 0; $strobe("[%0t] %d, %d, %d", $time, p, q, r); #1; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_var_dotted_dup_bad.out0000644000542200017500000000067315101701376023761 0ustar mahmoudyfreeshell%Error: t/t_var_dotted_dup_bad.v:14:18: Duplicate declaration of instance: 'dccm_bank' 14 | eh2_ram dccm_bank (.*); | ^~~~~~~~~ t/t_var_dotted_dup_bad.v:11:18: ... Location of original declaration 11 | eh2_ram dccm_bank (.*); | ^~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_module_input_default_value.py0000755000542200017500000000103315101701376025367 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') # Coverage for Issue #5920 test.compile(verilator_flags2=['--coverage-line']) test.execute() test.passes() verilator-5.042/test_regress/t/t_array_method_map.out0000644000542200017500000000126215101701376023456 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_array_method_map.v:17:15: Unsupported: Array 'map' method (IEEE 1800-2023 7.12.5) : ... note: In instance 't' 17 | res = a.map(el) with (el == 200); | ^~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: t/t_array_method_map.v:17:15: Unknown built-in array method 'map' : ... note: In instance 't' 17 | res = a.map(el) with (el == 200); | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_dpi_export_context_bad.cpp0000644000542200017500000000217115101701376024645 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include VM_PREFIX_INCLUDE //====================================================================== // clang-format off #if defined(VERILATOR) # include "Vt_dpi_export_context_bad__Dpi.h" #elif defined(VCS) # include "../vc_hdrs.h" #elif defined(CADENCE) # define NEED_EXTERNS #else # error "Unknown simulator for DPI test" #endif // clang-format on #ifdef NEED_EXTERNS extern "C" { extern void dpix_task(); } #endif //====================================================================== unsigned int main_time = 0; double sc_time_stamp() { return main_time; } VM_PREFIX* topp = nullptr; int main(int argc, char* argv[]) { Verilated::debug(0); Verilated::commandArgs(argc, argv); topp = new VM_PREFIX; topp->eval(); dpix_task(); // Missing svSetScope topp->final(); VL_DO_DANGLING(delete topp, topp); return 1; } verilator-5.042/test_regress/t/t_class_extends_int_param_bad.v0000644000542200017500000000052415101701376025300 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; class Bar #(type T=int) extends T; endclass initial begin Bar#() bar; $stop; end endmodule verilator-5.042/test_regress/t/t_interface_virtual_missing_bad.v0000644000542200017500000000051215101701376025643 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t; virtual foo vif; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_dfg_inline_forced.v0000644000542200017500000000075715101701376023231 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module top(input wire clk); logic [1:0][31:0] i; logic o; always @(posedge clk) begin force i = 64'hFFFFFFFF_FFFFFFFF; end sub sub_i(.i(i), .o(o)); endmodule module sub ( input logic [63:0] i, output logic o ); assign o = |i; endmodule verilator-5.042/test_regress/t/t_dpi_threads.v0000644000542200017500000000401715101701376022070 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2018 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import "DPI-C" dpii_sys_task = function void \$dpii_sys (); import "DPI-C" dpii_failure = function int \$dpii_failure (); module t (clk); input clk; integer cyc; integer failure; initial cyc = 0; `ifndef verilator `error "Only Verilator supports PLI-ish DPI calls." `endif always @ (posedge clk) begin if (cyc == 2) begin failure = $dpii_failure(); $write("* failure = %0d\n", failure); if (failure > 0) begin $stop; end $write("*-* All Finished *-*\n"); $finish; end cyc <= cyc + 1; end // The purpose of this test is to confirm that the DPI-call serialization // code in V3Partition does ensure that these DPI calls do not run // concurrently. // // Alternatively, the test may be run with "--threads-dpi all" in which case // it should confirm that the calls do run concurrently and do detect a // collision (they should, if the test is set up right.) This is // t_dpi_threads_collide.py. // // Q) Is it a risk that the partitioner will merge or serialize these always // blocks, just by luck, even if the DPI-call serialization code fails? // // A) Yes, that's why t_dpi_threads_collide.py also passes // --no-threads-do-coaren to disable MTask coarsening. This ensures that // the MTask graph at the end of FixDataHazards (where we resolve DPI // hazards) is basically the final MTasks graph, and that data hazards // which persist beyond FixDataHazards should persist in the final // generated C code. always @ (posedge clk) begin $dpii_sys(); end always @ (posedge clk) begin $dpii_sys(); end endmodule verilator-5.042/test_regress/t/t_interconnect.out0000644000542200017500000000120015101701376022626 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_interconnect.v:12:4: Unsupported: interconnect 12 | interconnect a; | ^~~~~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_interconnect.v:13:4: Unsupported: interconnect 13 | interconnect b; | ^~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_interconnect.v:22:11: Unsupported: interconnect 22 | output interconnect a, | ^~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_interconnect.v:23:11: Unsupported: interconnect 23 | output interconnect b); | ^~~~~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_trace_complex_structs_saif.out0000644000542200017500000010653615101701376025573 0ustar mahmoudyfreeshell// Generated by verilated_saif (SAIFILE (SAIFVERSION "2.0") (DIRECTION "backward") (PROGRAM_NAME "Verilator") (DIVIDER / ) (TIMESCALE 1ps) (DURATION 60) (INSTANCE top (NET (clk (T0 35) (T1 25) (TZ 0) (TX 0) (TB 0) (TC 11)) ) (INSTANCE $unit (NET (global_bit (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) ) ) (INSTANCE t (NET (clk (T0 35) (T1 25) (TZ 0) (TX 0) (TB 0) (TC 11)) (cyc\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (cyc\[1\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3)) (cyc\[2\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arrp\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arrp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arrp_arrp[3]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arrp_arrp[3]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arrp_arrp[4]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arrp_arrp[4]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arru[1] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arru[2] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arru_arru[3][1] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arru_arru[3][2] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arru_arru[4][1] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arru_arru[4][2] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arru_arrp[3]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arru_arrp[3]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arru_arrp[4]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_arru_arrp[4]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_real\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[32\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[33\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[34\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[35\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[36\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[37\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[38\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[39\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[40\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[41\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[42\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[43\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[44\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[45\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[46\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[47\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[48\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[49\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[50\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[51\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[52\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[53\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[54\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[55\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[56\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[57\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[58\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[59\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[60\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[61\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[62\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_real\[63\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[32\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[33\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[34\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[35\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[36\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[37\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[38\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[39\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[40\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[41\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[42\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[43\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[44\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[45\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[46\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[47\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[48\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[49\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[50\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[51\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[52\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[53\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[54\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[55\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[56\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[57\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[58\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[59\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[60\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[61\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[62\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[0]\[63\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[32\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[33\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[34\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[35\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[36\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[37\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[38\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[39\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[40\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[41\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[42\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[43\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[44\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[45\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[46\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[47\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[48\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[49\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[50\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[51\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[52\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[53\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[54\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[55\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[56\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[57\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[58\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[59\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[60\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[61\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[62\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_arr_real[1]\[63\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[32\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[33\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[34\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[35\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[36\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[37\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[38\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[39\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[40\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[41\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[42\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[43\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[44\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[45\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[46\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[47\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[48\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[49\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[50\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[51\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[52\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[53\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[54\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[55\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[56\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[57\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[58\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[59\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[60\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[61\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[62\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_chandle\[63\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_enumed\[1\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3)) (v_enumed\[2\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_enumed\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_enumed2\[2\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3)) (v_enumed2\[3\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_enumed2\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumed2\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_enumb\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (v_enumb\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 3)) (v_enumb\[2\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2)) (unpacked_array[-2]\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-2]\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-2]\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-2]\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-2]\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-2]\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-2]\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-2]\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-1]\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-1]\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-1]\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-1]\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-1]\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-1]\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-1]\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[-1]\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[0]\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[0]\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[0]\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[0]\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[0]\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[0]\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[0]\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (unpacked_array[0]\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE v_strp (NET (b1 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (b0 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) ) ) (INSTANCE v_strp_strp (INSTANCE x1 (NET (b1 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (b0 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) ) ) (INSTANCE x0 (NET (b1 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (b0 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) ) ) ) (INSTANCE v_unip_strp (INSTANCE x1 (NET (b1 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (b0 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) ) ) (INSTANCE x0 (NET (b1 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (b0 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) ) ) ) (INSTANCE v_arrp_strp[3] (NET (b1 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (b0 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) ) ) (INSTANCE v_arrp_strp[4] (NET (b1 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (b0 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) ) ) (INSTANCE v_arru_strp[3] (NET (b1 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (b0 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) ) ) (INSTANCE v_arru_strp[4] (NET (b1 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (b0 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) ) ) (INSTANCE v_str32x2[0] (NET (data\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 7)) (data\[1\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4)) (data\[2\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2)) (data\[3\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (data\[4\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (data\[5\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (data\[6\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (data\[7\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (data\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE v_str32x2[1] (NET (data\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (data\[1\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3)) (data\[2\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (data\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE v_enumb2_str (NET (a\[0\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 5)) (a\[1\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3)) (a\[2\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2)) (b\[0\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 5)) (b\[1\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3)) (b\[2\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2)) ) ) (INSTANCE unnamedblk1 (NET (b\[0\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (b\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[2\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (b\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (b\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE unnamedblk2 (NET (a\[0\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (a\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[2\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (a\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (a\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) ) ) verilator-5.042/test_regress/t/t_assert_iff.py0000755000542200017500000000101615101701376022111 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--assert --cc --coverage-user']) test.execute() test.passes() verilator-5.042/test_regress/t/t_order_wireloop.v0000644000542200017500000000055515101701376022640 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs bar ); wire foo; output bar; // Oh dear. assign foo = bar; assign bar = foo; endmodule verilator-5.042/test_regress/t/t_case_incrdecr.py0000755000542200017500000000102415101701376022547 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--trace-vcd --fno-split -x-assign 0"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_once_bad.v0000644000542200017500000000101515101701376022355 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Check that we report warnings only once on parameterized modules // Also check that we don't suppress warnings on the same line module t (); sub #(.A(1)) sub1(); sub #(.A(2)) sub2(); sub #(.A(3)) sub3(); endmodule module sub; parameter A = 0; reg [A:0] unus1; reg [A:0] unus2; endmodule verilator-5.042/test_regress/t/t_const_number_bad.py0000755000542200017500000000076615101701376023303 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_pp_circ_subst_bad.py0000755000542200017500000000076615101701376023444 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_x_rand_stability.out0000644000542200017500000000105615101701376023503 0ustar mahmoudyfreeshelluninitialized = 0xf5bbcbc0 x_assigned (initial) = 0x00000000 uninitialized2 = 0xa979eb54 big = 0xa20c93ac50d8c57d4c80949aa68e82775da6af98ce08f75dc6ccfad97b059a33 random_init = 0x952aaa76 top.t.the_sub_yes_inline_1 no_init 0x4a544f7798b83fc8 top.t.the_sub_yes_inline_2 no_init 0x19b7000ee0472c9 top.t.the_sub_no_inline_1 no_init 0x38121a34978975dd top.t.the_sub_no_inline_2 no_init 0x9022c84ae0fa3cf6 rand = 0xe3e54aaa rand = 0xe85acf2d rand = 0x15e12c6a rand = 0x0f7f28c0 rand = 0xe189c52a x_assigned = 0x486aeb2d Last rand = 0xf0700dbf *-* All Finished *-* verilator-5.042/test_regress/t/t_class_extends_nf_bad.out0000644000542200017500000000115415101701376024273 0ustar mahmoudyfreeshell%Error: t/t_class_extends_nf_bad.v:15:19: Class for 'extends' not found: 'IsNotFound' : ... Suggested alternative: 'IsFound' 15 | class Cls extends IsNotFound; | ^~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_class_extends_nf_bad.v:18:25: Class for 'extends' not found: 'NotFound2' : ... Suggested alternative: 'otFound2' 18 | class Cls2 extends Pkg::NotFound2; | ^~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_timing_write_expr.py0000755000542200017500000000101215101701376023517 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"], make_main=False) test.execute() test.passes() verilator-5.042/test_regress/t/t_string_repl.py0000755000542200017500000000073415101701376022322 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_opt_table_struct.out0000644000542200017500000000046515101701376023524 0ustar mahmoudyfreeshellcyle 0 = { 0, 1, 2 } cyle 1 = { 1, 2, 3 } cyle 2 = { 2, 3, 4 } cyle 3 = { 0, 0, 0 } cyle 4 = { 4, 5, 6 } cyle 5 = { 5, 6, 7 } cyle 6 = { 0, 0, 0 } cyle 7 = { 0, 0, 0 } *-* All Finished *-* verilator-5.042/test_regress/t/t_lint_cmpconst_bad.out0000644000542200017500000000072215101701376023625 0ustar mahmoudyfreeshell%Warning-CMPCONST: t/t_lint_cmpconst_bad.v:13:15: Comparison is constant due to limited range : ... note: In instance 't' 13 | if (uns > 3'b111) $stop; | ^ ... For warning description see https://verilator.org/warn/CMPCONST?v=latest ... Use "/* verilator lint_off CMPCONST */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_param_default_bad.out0000644000542200017500000000060615101701376023556 0ustar mahmoudyfreeshell%Error: t/t_param_default_bad.v:7:26: Parameter without default value is never given value (IEEE 1800-2023 6.20.1): 'Foo' : ... note: In instance 't.foo' 7 | module m #(parameter int Foo); | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_interface_asvar_bad.v0000644000542200017500000000110115101701376023533 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; counter_if iface(); source source ( .itf (iface) ); endmodule interface counter_if; logic [3:0] value; endinterface module source ( counter_if itf ); logic [3:0] getter; initial begin getter = itf; // Intended to write itf.value getter = 4'd3 + itf; // Intended to write itf.value end endmodule verilator-5.042/test_regress/t/t_vlcov_opt_toggle.py0000755000542200017500000000134015101701376023340 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') test.run(cmd=[ os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--write-info", test.obj_dir + "/coverage.info", "--filter-type toggle", "t/t_vlcov_data_e.dat" ], verilator_run=True) test.files_identical(test.obj_dir + "/coverage.info", "t/" + test.name + ".info.out") test.passes() verilator-5.042/test_regress/t/t_param_array6_noslice.py0000755000542200017500000000104415101701376024065 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_param_array6.v" test.compile(verilator_flags2=['-fno-slice']) test.execute() test.passes() verilator-5.042/test_regress/t/t_gantt_numa.py0000755000542200017500000000304015101701376022120 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Test for bin/verilator_gantt, import vltest_bootstrap test.scenarios('vltmt') test.top_filename = "t/t_gantt.v" test.pli_filename = "t/t_gantt_c.cpp" test.compile( verilator_flags2=["--prof-exec", test.pli_filename], # Checks below care about thread count threads=4) # We need several experiments to make sure that the algorithm is working trials = 4 for trial in range(0, trials): print("--------- Trial %d" % trial) test.execute( # Test fail: run_env='numactl -m 0 -C 0,0,0,0', all_run_flags=[ "+verilator+prof+exec+start+2", " +verilator+prof+exec+window+2", " +verilator+prof+exec+file+" + test.obj_dir + "/profile_exec.dat" ]) gantt_log = test.obj_dir + "/gantt.log" test.run(cmd=[ os.environ["VERILATOR_ROOT"] + "/bin/verilator_gantt", "--no-vcd", test.obj_dir + "/profile_exec.dat", "| tee " + gantt_log ]) test.file_grep(gantt_log, r'CPU info:') test.file_grep(gantt_log, r'NUMA status += (assigned|%Warning: no /proc/cpuinfo)') # False fails occasionally # test.file_grep_not(gantt_log, r'%Warning:') # e.g. There were fewer CPUs (1) than threads (3). test.passes() verilator-5.042/test_regress/t/t_format_wide_decimal.v0000644000542200017500000000236115101701376023560 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2020 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t_format_wide_decimal(/*AUTOARG*/ // Inputs clk ); input clk; int cycle; bit [1023:0] x; initial x = '1; always @(posedge clk) begin if (cycle == 0) begin // Format very wide constant number (which has more bits than can // be counted in exponent of a double precision float), with %d. $display("%d", 1024'hffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff); end else begin // Same, but for a variable with value only known at run-time $display("%d", x); end cycle <= cycle + 1; x <= x >> 1; if (cycle == 2) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_lint_import_name2_bad.v0000644000542200017500000000040015101701376024022 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 import missing::sigs; import missing::*; verilator-5.042/test_regress/t/t_lint_width_bad.v0000644000542200017500000000274715101701376022565 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (); // See also t_math_width // This shows the uglyness in width warnings across param modules // TODO: Would be nice to also show relevant parameter settings p #(.WIDTH(4)) p4 (.in(4'd0)); p #(.WIDTH(5)) p5 (.in(5'd0)); //==== localparam [3:0] XS = 'hx; // User presumably intended to use 'x //==== wire [4:0] c = 1'b1 << 2; // No width warning, as is common syntax wire [4:0] d = (1'b1 << 2) + 5'b1; // Has warning as not obvious what expression width is //==== localparam WIDTH = 6; wire one_bit; wire [2:0] shifter = 1; wire [WIDTH-1:0] masked = (({{(WIDTH){1'b0}}, one_bit}) << shifter); //==== // We presently warn here, in theory we could detect if the number of one bit additions could overflow the LHS wire one = 1; wire [2:0] cnt = (one + one + one + one); // Not harmless > or >= compared with something wider (as different results if "a" wider) localparam [40:0] THREE = 3; int a; initial for (a = 0; a > THREE; ++a) $display(a); initial for (a = 0; a >= THREE; ++a) $display(a); initial if (THREE) $stop; endmodule module p #(parameter WIDTH=64) (input [WIDTH-1:0] in); wire [4:0] out = in; endmodule verilator-5.042/test_regress/t/t_scope_map.v0000644000542200017500000000255715101701376021557 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Test symbol table scope map and general public // signal reflection // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 module t ( input wire CLK ); foo #(.WIDTH (1)) foo1 (.*); foo #(.WIDTH (7)) foo7 (.*); foo #(.WIDTH (8)) foo8 (.*); foo #(.WIDTH (32)) foo32 (.*); foo #(.WIDTH (33)) foo33 (.*); foo #(.WIDTH (40)) foo40 (.*); foo #(.WIDTH (41)) foo41 (.*); foo #(.WIDTH (64)) foo64 (.*); foo #(.WIDTH (65)) foo65 (.*); foo #(.WIDTH (96)) foo96 (.*); foo #(.WIDTH (97)) foo97 (.*); foo #(.WIDTH (128)) foo128 (.*); foo #(.WIDTH (256)) foo256 (.*); foo #(.WIDTH (1024)) foo1024 (.*); bar #(.WIDTH (1024)) bar1024 (.*); endmodule module foo #( parameter WIDTH = 32 ) ( input CLK ); logic [ ( ( WIDTH + 7 ) / 8 ) * 8 - 1 : 0 ] initial_value; logic [ WIDTH - 1 : 0 ] value_q /* verilator public */; integer i; initial begin initial_value = '1; for (i = 0; i < WIDTH / 8; i++) initial_value[ i * 8 +: 8 ] = i[ 7 : 0 ]; value_q = initial_value[ WIDTH - 1 : 0 ]; end always @(posedge CLK) value_q <= ~value_q; endmodule module bar #( parameter WIDTH = 32 ) ( input CLK ); foo #(.WIDTH (WIDTH)) foo (.*); endmodule verilator-5.042/test_regress/t/t_trace_ascendingrange.v0000644000542200017500000000434215101701376023731 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 module t #( parameter [0:7] P = 8'd10 )(/*AUTOARG*/ // Inputs clk ); input clk; int cyc = 0; localparam [0:7] Q = 8'd20; logic [ 0: 0] v_a = '0; logic [ 0: 1] v_b = '0; logic [ 0: 7] v_c = '0; logic [ 0: 8] v_d = '0; logic [ 0: 15] v_e = '0; logic [ 0: 16] v_f = '0; logic [ 0: 31] v_g = '0; logic [ 0: 32] v_h = '0; logic [ 0: 63] v_i = '0; logic [ 0: 64] v_j = '0; logic [ 0:127] v_k = '0; logic [ 0:128] v_l = '0; logic [ 0:255] v_m = '0; logic [ 0:256] v_n = '0; logic [ 0:511] v_o = '0; logic [ -1: 1] v_p = '0; logic [ -7: 7] v_q = '0; logic [ -15: 15] v_r = '0; logic [ -31: 31] v_s = '0; logic [ -63: 63] v_t = '0; logic [-127:127] v_u = '0; logic [-255:255] v_v = '0; always @(posedge clk) begin if (cyc == 0) begin v_a <= '1; v_b <= '1; v_c <= '1; v_d <= '1; v_e <= '1; v_f <= '1; v_g <= '1; v_h <= '1; v_i <= '1; v_j <= '1; v_k <= '1; v_l <= '1; v_m <= '1; v_n <= '1; v_o <= '1; v_p <= '1; v_q <= '1; v_r <= '1; v_s <= '1; v_t <= '1; v_u <= '1; v_v <= '1; end else begin v_a <= v_a << 1; v_b <= v_b << 1; v_c <= v_c << 1; v_d <= v_d << 1; v_e <= v_e << 1; v_f <= v_f << 1; v_g <= v_g << 1; v_h <= v_h << 1; v_i <= v_i << 1; v_j <= v_j << 1; v_k <= v_k << 1; v_l <= v_l << 1; v_m <= v_m << 1; v_n <= v_n << 1; v_o <= v_o << 1; v_p <= v_p << 1; v_q <= v_q << 1; v_r <= v_r << 1; v_s <= v_s << 1; v_t <= v_t << 1; v_u <= v_u << 1; v_v <= v_v << 1; end cyc <= cyc + 1; if (cyc == 2) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_mem_shift.py0000755000542200017500000000113115101701376021735 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--stats"]) if test.vlt_all: test.file_grep(test.stats, r'Optimizations, NBA flags shared\s+(\d+)', 14) test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_paramnodefault_bad.py0000755000542200017500000000152415101701376024626 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.top_filename = 't/t_lint_paramnodefault.v' test.lint(fails=True, expect_filename=test.golden_filename) test.extract(in_filename=test.top_filename, out_filename=test.root + "/docs/gen/ex_PARAMNODEFAULT_faulty.rst", lines="7-8") test.extract(in_filename=test.golden_filename, out_filename=test.root + "/docs/gen/ex_PARAMNODEFAULT_msg.rst", lines="1-3") test.passes() verilator-5.042/test_regress/t/t_vpi_dump_missing_scopes.py0000755000542200017500000000207215101701376024717 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.pli_filename = "t/t_vpi_dump.cpp" test.compile(make_top_shell=False, make_main=False, make_pli=True, iv_flags2=["-g2005-sv"], verilator_flags2=[ "--exe --vpi --public-flat-rw --no-l2name", test.pli_filename, "t/TestVpiMain.cpp" ], make_flags=['CPPFLAGS_ADD=-DVL_NO_LEGACY']) test.execute(use_libvpi=True, expect_filename=test.golden_filename, xrun_run_expect_filename=re.sub(r'\.out$', '.xrun.out', test.golden_filename), iv_run_expect_filename=re.sub(r'\.out$', '.iv.out', test.golden_filename)) test.passes() verilator-5.042/test_regress/t/t_bitsel_wire_array_bad.v0000644000542200017500000000074115101701376024116 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Test of select from constant // // This tests issue #509, bit select of constant fails // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 module t; // a and b are arrays of length 1. wire a[0:0]; // Array of nets wire b[0:0]; assign a = 1'b0; // Only net assignment allowed assign b = a[0]; // Only net assignment allowed endmodule verilator-5.042/test_regress/t/t_hier_block_perf.v0000644000542200017500000003034215101701376022717 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // based on t_gate_ormux `ifndef CORES `define CORES 4 `endif module t (/*AUTOARG*/ // Inputs clk ); input clk; generate for (genvar i = 0; i < `CORES; ++i) Core core(clk); for (genvar i = 0; i < `CORES; ++i) CoreHier hierCore(clk); endgenerate endmodule module Core(input clk); reg [63:0] crc; logic [31:0] rdata; logic [31:0] rdata2; wire [31:0] wdata = crc[31:0]; wire [15:0] sel = {11'h0, crc[36:32]}; wire we = crc[48]; Test test ( // Outputs .rdata (rdata[31:0]), .rdata2 (rdata2[31:0]), // Inputs .clk (clk), .we (we), .sel (sel[15:0]), .wdata (wdata[31:0])); wire [63:0] result = {rdata2, rdata}; Check check(.clk(clk), .crc(crc), .result(result), .rdata(rdata), .rdata2(rdata2)); endmodule module CoreHier(input clk); // Dummy logic to have two different hier blocks at the same level. integer cyc = 0; always @(posedge clk) begin cyc += 1; if (cyc == 1) $display("%d", clk); end endmodule module Check( input clk, output reg [63:0] crc, input wire [63:0] result, input logic [31:0] rdata, input logic [31:0] rdata2 ); /*verilator hier_block*/ integer cyc = 0; reg [63:0] sum; always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (rdata2 != rdata) $stop; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc<10) begin sum <= '0; end else if (cyc == 99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; `define EXPECTED_SUM 64'h8977713eb467bc86 if (sum !== `EXPECTED_SUM) $stop; end else if (cyc == `SIM_CYCLES) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test(/*AUTOARG*/ // Outputs rdata, rdata2, // Inputs clk, we, sel, wdata ); /*verilator hier_block*/ input clk; input we; input [15:0] sel; input [31:0] wdata; output logic [31:0] rdata; output logic [31:0] rdata2; logic we_d1r; logic [15:0] sel_d1r; logic [31:0] wdata_d1r; always_ff @ (posedge clk) begin we_d1r <= we; sel_d1r <= sel; wdata_d1r <= wdata; end reg [31:0] csr0000; reg [31:0] csr0001; reg [31:0] csr0002; reg [31:0] csr0003; reg [31:0] csr0004; reg [31:0] csr0005; reg [31:0] csr0006; reg [31:0] csr0007; reg [31:0] csr0008; reg [31:0] csr0009; reg [31:0] csr000a; reg [31:0] csr000b; reg [31:0] csr000c; reg [31:0] csr000d; reg [31:0] csr000e; reg [31:0] csr000f; wire [31:0] csr0010 = 32'h33675230; wire [31:0] csr0011 = 32'h00fa2144; wire [31:0] csr0012 = 32'h6a5e8e10; wire [31:0] csr0013 = 32'h000a5b5e; wire [31:0] csr0014 = 32'h002fe51b; wire [31:0] csr0015 = 32'h00027e00; wire [31:0] csr0016 = 32'h0000e3c0; wire [31:0] csr0017 = 32'h00efcf16; wire [31:0] csr0018 = 32'h007a2600; wire [31:0] csr0019 = 32'h0a4a9f10; wire [31:0] csr001a = 32'h7d789de3; wire [31:0] csr001b = 32'h40f655f9; wire [31:0] csr001c = 32'hadad01f4; wire [31:0] csr001d = 32'h02e7b33c; wire [31:0] csr001e = 32'h12101533; wire [31:0] csr001f = 32'h2cc1cce5; initial begin csr0000 = 32'he172d365; csr0001 = 32'h35cc25e2; csr0002 = 32'haf48436e; csr0003 = 32'h135e55e4; csr0004 = 32'h5fd6e48a; csr0005 = 32'hb07d34ad; csr0006 = 32'h2aa05deb; csr0007 = 32'hfe97b680; csr0008 = 32'h960f20bb; csr0009 = 32'h251129f0; csr000a = 32'hef3d2f93; csr000b = 32'hef4bc127; csr000c = 32'h3dfecb10; csr000d = 32'h1b4690f5; csr000e = 32'ha07822ab; csr000f = 32'hf817cbf6; end always_ff @ (posedge clk) begin if (we_d1r && sel_d1r == 16'h0000) csr0000 <= wdata_d1r; if (we_d1r && sel_d1r == 16'h0001) csr0001 <= wdata_d1r; if (we_d1r && sel_d1r == 16'h0002) csr0002 <= wdata_d1r; if (we_d1r && sel_d1r == 16'h0003) csr0003 <= wdata_d1r; if (we_d1r && sel_d1r == 16'h0004) csr0004 <= wdata_d1r; if (we_d1r && sel_d1r == 16'h0005) csr0005 <= wdata_d1r; if (we_d1r && sel_d1r == 16'h0006) csr0006 <= wdata_d1r; if (we_d1r && sel_d1r == 16'h0007) csr0007 <= wdata_d1r; if (we_d1r && sel_d1r == 16'h0008) csr0008 <= wdata_d1r; if (we_d1r && sel_d1r == 16'h0009) csr0009 <= wdata_d1r; if (we_d1r && sel_d1r == 16'h000a) csr000a <= wdata_d1r; if (we_d1r && sel_d1r == 16'h000b) csr000b <= wdata_d1r; if (we_d1r && sel_d1r == 16'h000c) csr000c <= wdata_d1r; if (we_d1r && sel_d1r == 16'h000d) csr000d <= wdata_d1r; if (we_d1r && sel_d1r == 16'h000e) csr000e <= wdata_d1r; if (we_d1r && sel_d1r == 16'h000f) csr000f <= wdata_d1r; end wire dec0000 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; wire dec0001 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; wire dec0002 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; wire dec0003 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; wire dec0004 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; wire dec0005 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; wire dec0006 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; wire dec0007 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; wire dec0008 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; wire dec0009 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; wire dec000a = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; wire dec000b = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; wire dec000c = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; wire dec000d = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; wire dec000e = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; wire dec000f = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; wire dec0010 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; wire dec0011 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; wire dec0012 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; wire dec0013 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; wire dec0014 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; wire dec0015 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; wire dec0016 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; wire dec0017 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; wire dec0018 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; wire dec0019 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; wire dec001a = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; wire dec001b = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; wire dec001c = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; wire dec001d = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; wire dec001e = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; wire dec001f = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; assign rdata = (32'h0 | {32{dec0000}} & csr0000 | {32{dec0001}} & csr0001 | {32{dec0002}} & csr0002 | {32{dec0003}} & csr0003 | {32{dec0004}} & csr0004 | {32{dec0005}} & csr0005 | {32{dec0006}} & csr0006 | {32{dec0007}} & csr0007 | {32{dec0008}} & csr0008 | {32{dec0009}} & csr0009 | {32{dec000a}} & csr000a | {32{dec000b}} & csr000b | {32{dec000c}} & csr000c | {32{dec000d}} & csr000d | {32{dec000e}} & csr000e | {32{dec000f}} & csr000f | {32{dec0010}} & csr0010 | {32{dec0011}} & csr0011 | {32{dec0012}} & csr0012 | {32{dec0013}} & csr0013 | {32{dec0014}} & csr0014 | {32{dec0015}} & csr0015 | {32{dec0016}} & csr0016 | {32{dec0017}} & csr0017 | {32{dec0018}} & csr0018 | {32{dec0019}} & csr0019 | {32{dec001a}} & csr001a | {32{dec001b}} & csr001b | {32{dec001c}} & csr001c | {32{dec001d}} & csr001d | {32{dec001e}} & csr001e | {32{dec001f}} & csr001f ); always_comb begin case (sel_d1r) 16'h0000: rdata2 = csr0000; 16'h0001: rdata2 = csr0001; 16'h0002: rdata2 = csr0002; 16'h0003: rdata2 = csr0003; 16'h0004: rdata2 = csr0004; 16'h0005: rdata2 = csr0005; 16'h0006: rdata2 = csr0006; 16'h0007: rdata2 = csr0007; 16'h0008: rdata2 = csr0008; 16'h0009: rdata2 = csr0009; 16'h000a: rdata2 = csr000a; 16'h000b: rdata2 = csr000b; 16'h000c: rdata2 = csr000c; 16'h000d: rdata2 = csr000d; 16'h000e: rdata2 = csr000e; 16'h000f: rdata2 = csr000f; 16'h0010: rdata2 = csr0010; 16'h0011: rdata2 = csr0011; 16'h0012: rdata2 = csr0012; 16'h0013: rdata2 = csr0013; 16'h0014: rdata2 = csr0014; 16'h0015: rdata2 = csr0015; 16'h0016: rdata2 = csr0016; 16'h0017: rdata2 = csr0017; 16'h0018: rdata2 = csr0018; 16'h0019: rdata2 = csr0019; 16'h001a: rdata2 = csr001a; 16'h001b: rdata2 = csr001b; 16'h001c: rdata2 = csr001c; 16'h001d: rdata2 = csr001d; 16'h001e: rdata2 = csr001e; 16'h001f: rdata2 = csr001f; default: rdata2 = 0; endcase end endmodule verilator-5.042/test_regress/t/t_randomize_unpacked_bad.py0000755000542200017500000000076615101701376024447 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_math_shiftrs2.v0000644000542200017500000000124515101701376022357 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkd(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__, `__LINE__, (gotv), (expv)); `stop; end while(0); module top(out35); output wire [2:0] out35; wire signed [2:0] wire_4; assign wire_4 = 3'b011; assign out35 = (wire_4 >>> 36'hffff_ffff_f); initial begin #10; `checkd(out35, '0); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_lint_nullport_bad.v0000644000542200017500000000202015101701376023305 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Udi Finkelstein. // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off MULTITOP */ // First, test we haven't broken normal ports module t1(); endmodule module t2; endmodule module t3(a); input a; endmodule module t4(a, b); input a, b; endmodule module t5(a,); input a; endmodule module t6(a,,); input a; endmodule module t7(a,b,); input a, b; endmodule module t8(a,b,,); input a, b; endmodule module t9(a,,b); input a, b; endmodule module t10(a,,b,); input a, b; endmodule module t11(a,,b,,); input a, b; endmodule module t12(,a,,b); input a, b; endmodule module t13(,a,,b,); input a, b; endmodule module t14(,a,,b,,); input a, b; endmodule module t15(,,a,,b); input a, b; endmodule module t16(,,a,,b,); input a, b; endmodule module t17(,,a,,b,,); input a, b; endmodule module t18(,); endmodule /* verilator lint_off NULLPORT */ module t19(,,); endmodule verilator-5.042/test_regress/t/t_interface_gen10.v0000644000542200017500000000121615101701376022532 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty. // SPDX-License-Identifier: CC0-1.0 // bug998 interface intf #(parameter PARAM = 0) (); logic val; function integer func (); return 5; endfunction endinterface module t1(intf mod_intf); initial begin $display("%m %d", mod_intf.val); end endmodule module t(); generate begin : TestIf intf #(.PARAM(1)) my_intf [0:0] (); t1 t (.mod_intf(my_intf[0])); end endgenerate initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_stream4.py0000755000542200017500000000073415101701376021351 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_param_scope_bad.py0000755000542200017500000000076615101701376023076 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_param_implicit_local_bad.out0000644000542200017500000000243315101701376025116 0ustar mahmoudyfreeshell%Error-PINNOTFOUND: t/t_param_implicit_local_bad.v:15:20: Parameter not found: '__paramNumber2' 15 | NestedCls #(1, 2) cls; | ^ ... For error description see https://verilator.org/warn/PINNOTFOUND?v=latest %Error-PINNOTFOUND: t/t_param_implicit_local_bad.v:17:21: Parameter not found: '__paramNumber3' 17 | mod1 # ( 3, 4, 5 ) i_mod1 (); | ^ %Error-PINNOTFOUND: t/t_param_implicit_local_bad.v:19:15: Parameter not found: '__paramNumber1' 19 | mod3 # ( 7, 24, 25 ) i_mod3 (); | ^ %Error-PINNOTFOUND: t/t_param_implicit_local_bad.v:19:18: Parameter not found: '__paramNumber2' 19 | mod3 # ( 7, 24, 25 ) i_mod3 (); | ^~ %Error-PINNOTFOUND: t/t_param_implicit_local_bad.v:19:22: Parameter not found: '__paramNumber3' 19 | mod3 # ( 7, 24, 25 ) i_mod3 (); | ^~ %Error-PINNOTFOUND: t/t_param_implicit_local_bad.v:20:22: Parameter not found: '__paramNumber3' 20 | intf1 # ( 8, 15, 17 ) i_intf1 (); | ^~ %Error-PINNOTFOUND: t/t_param_implicit_local_bad.v:21:22: Parameter not found: '__paramNumber3' 21 | prgm1 # ( 9, 40, 41 ) i_prgm1 (); | ^~ %Error: Exiting due to verilator-5.042/test_regress/t/t_select_set.py0000755000542200017500000000073415101701376022124 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_display_realtime.v0000644000542200017500000000105015101701376023123 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; always @ (posedge clk) begin cyc <= cyc + 1; $display("TestCase at %1t (%s)", $realtime, cyc[0] ? "Option1" : "Option2"); if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_math_shift.v0000644000542200017500000002053115101701376021727 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs ign, ign2, ign3, ign4, ign4s, // Inputs clk ); input clk; output [31:0] ign; output [3:0] ign2; output [11:0] ign3; parameter [95:0] P6 = 6; localparam P64 = (1 << P6); // verilator lint_off WIDTH localparam [4:0] PBIG23 = 1'b1 << ~73'b0; localparam [3:0] PBIG29 = 4'b1 << 33'h100000000; // verilator lint_on WIDTH reg [31:0] iright; reg signed [31:0] irights; reg [31:0] ileft; reg [P64-1:0] qright; reg signed [P64-1:0] qrights; reg [P64-1:0] qleft; reg [95:0] wright; reg signed [95:0] wrights; reg [95:0] wleft; reg [31:0] q_iright; reg signed [31:0] q_irights; reg [31:0] q_ileft; reg [P64-1:0] q_qright; reg signed [P64-1:0] q_qrights; reg [P64-1:0] q_qleft; reg [95:0] q_wright; reg signed [95:0] q_wrights; reg [95:0] q_wleft; reg [31:0] w_iright; reg signed [31:0] w_irights; reg [31:0] w_ileft; reg [P64-1:0] w_qright; reg signed [P64-1:0] w_qrights; reg [P64-1:0] w_qleft; reg [95:0] w_wright; reg signed [95:0] w_wrights; reg [95:0] w_wleft; reg [31:0] iamt; reg [63:0] qamt; reg [95:0] wamt; assign ign = {31'h0, clk} >>> 4'bx; // bug760 assign ign2 = {iamt[1:0] >> {22{iamt[5:2]}}, iamt[1:0] << (0 <<< iamt[5:2])}; // bug1174 assign ign3 = {iamt[1:0] >> {22{iamt[5:2]}}, iamt[1:0] >> {11{iamt[5:2]}}, $signed(iamt[1:0]) >>> {22{iamt[5:2]}}, $signed(iamt[1:0]) >>> {11{iamt[5:2]}}, iamt[1:0] << {22{iamt[5:2]}}, iamt[1:0] << {11{iamt[5:2]}}}; wire [95:0] wamtt = {iamt,iamt,iamt}; output wire [95:0] ign4; assign ign4 = wamtt >> {11{iamt[5:2]}}; output wire signed [95:0] ign4s; assign ign4s = $signed(wamtt) >>> {11{iamt[5:2]}}; always @* begin iright = 32'h819b018a >> iamt; irights = 32'sh819b018a >>> signed'(iamt); ileft = 32'h819b018a << iamt; qright = 64'hf784bf8f_12734089 >> iamt; qrights = 64'shf784bf8f_12734089 >>> signed'(iamt); qleft = 64'hf784bf8f_12734089 << iamt; wright = 96'hf784bf8f_12734089_190abe48 >> iamt; wrights = 96'shf784bf8f_12734089_190abe48 >>> signed'(iamt); wleft = 96'hf784bf8f_12734089_190abe48 << iamt; q_iright = 32'h819b018a >> qamt; q_irights = 32'sh819b018a >>> signed'(qamt); q_ileft = 32'h819b018a << qamt; q_qright = 64'hf784bf8f_12734089 >> qamt; q_qrights = 64'shf784bf8f_12734089 >>> signed'(qamt); q_qleft = 64'hf784bf8f_12734089 << qamt; q_wright = 96'hf784bf8f_12734089_190abe48 >> qamt; q_wrights = 96'shf784bf8f_12734089_190abe48 >>> signed'(qamt); q_wleft = 96'hf784bf8f_12734089_190abe48 << qamt; w_iright = 32'h819b018a >> wamt; w_irights = 32'sh819b018a >>> signed'(wamt); w_ileft = 32'h819b018a << wamt; w_qright = 64'hf784bf8f_12734089 >> wamt; w_qrights = 64'shf784bf8f_12734089 >>> signed'(wamt); w_qleft = 64'hf784bf8f_12734089 << wamt; w_wright = 96'hf784bf8f_12734089_190abe48 >> wamt; w_wrights = 96'shf784bf8f_12734089_190abe48 >>> signed'(wamt); w_wleft = 96'hf784bf8f_12734089_190abe48 << wamt; end integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; `ifdef TEST_VERBOSE $write("%d %x %x %x %x %x %x\n", cyc, ileft, iright, qleft, qright, wleft, wright); `endif if (cyc==1) begin iamt <= 0; qamt <= 0; wamt <= 0; if (P64 != 64) $stop; if (5'b10110>>2 != 5'b00101) $stop; if (5'b10110>>>2 != 5'b00101) $stop; // Note it cares about sign-ness if (5'b10110<<2 != 5'b11000) $stop; if (5'b10110<<<2 != 5'b11000) $stop; if (5'sb10110>>2 != 5'sb00101) $stop; if (5'sb10110>>>2 != 5'sb11101) $stop; if (5'sb10110<<2 != 5'sb11000) $stop; if (5'sb10110<<<2 != 5'sb11000) $stop; // Allow >64 bit shifts if the shift amount is a constant if ((64'sh458c2de282e30f8b >> 68'sh4) !== 64'sh0458c2de282e30f8) $stop; end if (cyc==2) begin iamt <= 28; qamt <= 28; wamt <= 28; if (ileft != 32'h819b018a) $stop; if (iright != 32'h819b018a) $stop; if (irights != 32'h819b018a) $stop; if (qleft != 64'hf784bf8f_12734089) $stop; if (qright != 64'hf784bf8f_12734089) $stop; if (qrights != 64'hf784bf8f_12734089) $stop; if (wleft != 96'hf784bf8f12734089190abe48) $stop; if (wright != 96'hf784bf8f12734089190abe48) $stop; if (wrights != 96'hf784bf8f12734089190abe48) $stop; end if (cyc==3) begin iamt <= 31; qamt <= 31; wamt <= 31; if (ileft != 32'ha0000000) $stop; if (iright != 32'h8) $stop; if (irights != 32'hfffffff8) $stop; if (qleft != 64'hf127340890000000) $stop; if (qright != 64'h0000000f784bf8f1) $stop; if (qrights != 64'hffffffff784bf8f1) $stop; if (wleft != 96'hf12734089190abe480000000) $stop; if (wright != 96'h0000000f784bf8f127340891) $stop; if (wrights != 96'hffffffff784bf8f127340891) $stop; end if (cyc==4) begin iamt <= 32; qamt <= 32; wamt <= 32; if (ileft != 32'h0) $stop; if (iright != 32'h1) $stop; if (qleft != 64'h8939a04480000000) $stop; if (qright != 64'h00000001ef097f1e) $stop; end if (cyc==5) begin iamt <= 33; qamt <= 33; wamt <= 33; if (ileft != 32'h0) $stop; if (iright != 32'h0) $stop; if (qleft != 64'h1273408900000000) $stop; if (qright != 64'h00000000f784bf8f) $stop; end if (cyc==6) begin iamt <= 64; qamt <= 64; wamt <= 64; if (ileft != 32'h0) $stop; if (iright != 32'h0) $stop; if (qleft != 64'h24e6811200000000) $stop; if (qright != 64'h000000007bc25fc7) $stop; end if (cyc==7) begin iamt <= 128; qamt <= 128; wamt <= 128; if (ileft != 32'h0) $stop; if (iright != 32'h0) $stop; if (qleft != 64'h0) $stop; if (qright != 64'h0) $stop; end if (cyc==8) begin iamt <= 100; qamt <= {32'h10, 32'h0}; wamt <= {32'h10, 64'h0}; if (ileft != '0) $stop; if (iright != '0) $stop; if (irights != '1) $stop; if (qleft != '0) $stop; if (qright != '0) $stop; if (qrights != '1) $stop; if (wleft != '0) $stop; if (wright != '0) $stop; if (wrights != '1) $stop; end if (cyc==19) begin $write("*-* All Finished *-*\n"); $finish; end // General rule to test all q's if (cyc != 0) begin if (ileft != q_ileft) $stop; if (iright != q_iright) $stop; if (irights != q_irights) $stop; if (qleft != q_qleft) $stop; if (qright != q_qright) $stop; if (qrights != q_qrights) $stop; if (wleft != q_wleft) $stop; if (wright != q_wright) $stop; if (wrights != q_wrights) $stop; if (ileft != w_ileft) $stop; if (iright != w_iright) $stop; if (irights != w_irights) $stop; if (qleft != w_qleft) $stop; if (qright != w_qright) $stop; if (qrights != w_qrights) $stop; if (wleft != w_wleft) $stop; if (wright != w_wright) $stop; if (wrights != w_wrights) $stop; end end end endmodule verilator-5.042/test_regress/t/t_unpacked_str_init2.v0000644000542200017500000000246515101701376023376 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // issue2895 module t; localparam string REG_X [0:31] = '{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0/fp", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6"}; function automatic string reg_x (logic [4:0] r, bit abi=1'b0); reg_x = abi ? REG_X[r] : $sformatf("x%0d", r); endfunction // the issue is triggered by a second function containing a case statement function automatic string f2 (logic [4:0] r, bit abi=0); case (r) 5'd0: f2 = $sformatf("nop"); 5'd1: f2 = $sformatf("reg %s", reg_x(r[4:0], abi)); default: f2 = $sformatf("ILLEGAL"); endcase endfunction initial begin for (int unsigned i = 0; i < 32; ++i) begin $display("REGX: %s", reg_x(i[4:0], 1'b1)); end $display("OP: %s", f2(5'd7)); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_param_local.py0000755000542200017500000000073415101701376022244 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_time_vpi_1ps1fs.out0000644000542200017500000000172315101701376023156 0ustar mahmoudyfreeshell:: In top.t Time scale of t is 1ps / 1fs [60000] time%0d=60 123%0t=123000 dig%0t=5432109876543000 dig%0d=5432109876543 rdig%0t=5432109876543210 rdig%0f=5432109876543.209961 acc%0t=12345678901234567890000 acc%0d=12345678901234567890 [0.060000ns] time%0d=60 123%0t=0.123000ns dig%0t=5432109876.543000ns dig%0d=5432109876543 rdig%0t=5432109876.543210ns rdig%0f=5432109876543.209961 acc%0t=12345678901234567.890000ns acc%0d=12345678901234567890 [0.060000ns] stime%0t=0.060000ns stime%0d=60 stime%0f=60.000000 [0.060000ns] rtime%0t=0.060000ns rtime%0d=60 rtime%0f=60.000000 global svGetTime = 0 0,60000 global svGetTimeUnit = 0 -12 svGetTmePrecision = 0 -15 global vpiSimTime = 0,60000 vpiScaledRealTime = 60000 global vpiTimeUnit = -12 vpiTimePrecision = -15 top.t svGetTime = 0 0,60000 top.t svGetTimeUnit = 0 -12 svGetTmePrecision = 0 -15 top.t vpiSimTime = 0,60000 vpiScaledRealTime = 60 top.t vpiTimeUnit = -12 vpiTimePrecision = -15 *-* All Finished *-* verilator-5.042/test_regress/t/t_lint_restore_bad.out0000644000542200017500000000102015101701376023452 0ustar mahmoudyfreeshell%Warning-WIDTHTRUNC: t/t_lint_restore_bad.v:19:17: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS's CONST '64'h1' generates 64 bits. : ... note: In instance 't' 19 | initial five = 64'h1; | ^ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_dpi_qw.v0000644000542200017500000000166515101701376021073 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; wire [39:0] out; sub a(.value(out)); import "DPI-C" context function void poke_value(input int i); initial begin poke_value(32'hdeadbeef); if (out !== 40'hdeadbeef) begin $display("[%0t] %%Error: t_dpi_qw: failed", $time); $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule module sub(value); parameter WIDTH = 40; output [WIDTH-1:0] value; reg [WIDTH-1:0] value; task set_value(input bit [WIDTH-1:0] v); value = v; endtask export "DPI-C" task set_value; endmodule verilator-5.042/test_regress/t/t_threads_crazy.py0000755000542200017500000000134515101701376022633 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vltmt') test.compile(verilator_flags2=['--cc'], threads=4, context_threads=2) test.execute(fails=True) test.file_grep( test.run_log_filename, r"%Error: .*\/verilated\.cpp:\d+: VerilatedContext has 2 threads but model 'Vt_threads_crazy' \(instantiated as 'top'\) was Verilated with --threads 4\." ) test.passes() verilator-5.042/test_regress/t/t_implements_new_bad.py0000755000542200017500000000076615101701376023633 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_randomize_rand_mode_unsup.v0000644000542200017500000000120215101701376025025 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Packet; rand int m_dyn_arr[]; rand int m_unp_arr[10]; rand struct { int y; } m_struct; static rand int m_static; endclass module t; initial begin Packet p = new; p.m_dyn_arr[0].rand_mode(0); p.m_unp_arr[0].rand_mode(0); p.m_struct.y.rand_mode(0); p.m_static.rand_mode(0); $display("p.m_static.rand_mode()=%0d", p.m_static.rand_mode()); p.rand_mode(0); end endmodule verilator-5.042/test_regress/t/t_trace_fst_sc_cmake.py0000755000542200017500000000131315101701376023563 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') if not test.have_sc: test.skip("No SystemC installed") test.compile(verilator_flags2=["--trace-fst --sc"], verilator_make_gmake=False, verilator_make_cmake=True) test.execute() test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_randstate_func.py0000755000542200017500000000073415101701376022772 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_generic.v0000644000542200017500000000121315101701376023231 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 interface inf; int v; endinterface interface inf2; int k; endinterface module GenericModule (interface a, interface b); initial begin #1; if (a.v != 7) $stop; if (b.k != 9) $stop; end endmodule module t; inf inf_inst(); inf2 inf_inst2(); GenericModule genericModule (inf_inst, inf_inst2); initial begin inf_inst.v = 7; inf_inst2.k = 9; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_randomize_method_bad.out0000644000542200017500000000135015101701376024277 0ustar mahmoudyfreeshell%Error: t/t_randomize_method_bad.v:8:17: 'randomize' is a predefined class method; redefinition not allowed (IEEE 1800-2023 18.6.3) 8 | function int randomize; | ^~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_randomize_method_bad.v:14:18: 'randomize' is a predefined class method; redefinition not allowed (IEEE 1800-2023 18.6.3) 14 | function void randomize(int x); | ^~~~~~~~~ %Error: t/t_randomize_method_bad.v:16:18: 'srandom' is a predefined class method; redefinition not allowed (IEEE 1800-2023 18.6.3) 16 | function void srandom(int seed); | ^~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_sys_monitor.v0000644000542200017500000000210715101701376022165 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; int cyc = 0; // Test loop always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 10) begin $monitor("[%0t] cyc=%0d", $time, cyc); end else if (cyc == 17) begin $monitorb(cyc, "b"); end else if (cyc == 18) begin $monitorh(cyc, "h"); end else if (cyc == 19) begin $monitoro(cyc, "o"); end else if (cyc == 22) begin $monitor("[%0t] cyc=%0d new-monitor", $time, cyc); end else if (cyc == 24) begin $monitoroff; end else if (cyc == 26) begin $monitoron; end else if (cyc == 30) begin $monitoroff; // To avoid inconsistent output between --vlt and --vltmt $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_gen_missing_bad2.out0000644000542200017500000000222015101701376023330 0ustar mahmoudyfreeshell%Error: t/t_gen_missing_bad2.v:8:8: Expecting expression to be constant, but can't convert a TESTPLUSARGS to constant. : ... note: In instance 't' 8 | if ($test$plusargs("BAD-non-constant")) begin | ^~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_gen_missing_bad2.v:8:8: Generate If condition must evaluate to constant : ... note: In instance 't' 8 | if ($test$plusargs("BAD-non-constant")) begin | ^~~~~~~~~~~~~~ %Error: t/t_gen_missing_bad2.v:12:7: Expecting expression to be constant, but can't convert a TESTPLUSARGS to constant. : ... note: In instance 't' 12 | $test$plusargs("BAD-non-constant"): initial $stop; | ^~~~~~~~~~~~~~ %Error: t/t_gen_missing_bad2.v:12:41: Generate Case item does not evaluate to constant : ... note: In instance 't' 12 | $test$plusargs("BAD-non-constant"): initial $stop; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_lint_infinite_bad.py0000755000542200017500000000076315101701376023435 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_display_esc_bad.py0000755000542200017500000000076315101701376023101 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_stop_winos_bad.out0000644000542200017500000000023715101701376023156 0ustar mahmoudyfreeshellIntentional stop Filename 'C:\some\windows\path\t_stop_winos_bad.v' Length = 39 %Error: C:\some\windows\path\t_stop_winos_bad.v:14: Verilog $stop Aborting... verilator-5.042/test_regress/t/t_bitsel_const_bad.out0000644000542200017500000000057615101701376023450 0ustar mahmoudyfreeshell%Error: t/t_bitsel_const_bad.v:16:16: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' : ... note: In instance 't' 16 | assign a = b[0]; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_implements_contents_bad.v0000644000542200017500000000046315101701376024503 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface class Icls; int badi; task badtask; endtask endclass module t; endmodule verilator-5.042/test_regress/t/t_interface_generic_function.py0000755000542200017500000000077115101701376025334 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--timing']) test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_mp_func.py0000755000542200017500000000073415101701376023441 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_constraint_mode_bad.py0000755000542200017500000000076315101701376023772 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_null_bad.v0000644000542200017500000000072215101701376022546 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls; int imembera; endclass : Cls module t; Cls c; initial begin c = null; // Not really required as null is default c.imembera = 10; // BAD IEEE 8.4 $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_randomize_inline_var_ctl.py0000755000542200017500000000104615101701376025027 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_ccache_report__ccache_report_initial.out0000644000542200017500000000046015101701376027474 0ustar mahmoudyfreeshell################################################################################ ccache report (from verilator_ccache_report) : Compiled object files: Vt_ccache_report__ALL.o : IGNORED Summary: IGNORED Longest: IGNORED ################################################################################ verilator-5.042/test_regress/t/t_flag_csplit_groups.py0000755000542200017500000001223215101701376023654 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_flag_csplit.v" def check_splits(): got1 = False gotSyms1 = False for filename in test.glob_some(test.obj_dir + "/*.cpp"): if re.search(r'Syms__1', filename): gotSyms1 = True elif re.search(r'__1', filename): got1 = True if not got1: test.error("No __1 split file found") if not gotSyms1: test.error("No Syms__1 split file found") def check_no_all_file(): for filename in test.glob_some(test.obj_dir + "/*.cpp"): if re.search(r'__ALL.cpp', filename): test.error("__ALL.cpp file found: " + filename) def check_cpp(filename): size = os.path.getsize(filename) if test.verbose: print(" File %6d %s\n" % (size, filename)) funcs = [] with open(filename, 'r', encoding="utf8") as fh: for line in fh: m = re.search(r'^(void|IData)\s+(.*::.*){', line) if not m: continue func = m.group(2) func = re.sub(r'\(.*$', '', func) if test.verbose: print("\tFunc " + func) if (re.search(r'(::_eval_initial_loop$', func) or re.search(r'::__Vconfigure$', func) or re.search(r'::trace$', func) or re.search(r'::traceInit$', func) or re.search(r'::traceFull$', func) or re.search(r'::final$', func) or re.search(r'::prepareClone$', func) or re.search(r'::atClone$', func)): continue funcs.append(func) if len(funcs) > 0: test.error("Split had multiple functions in $filename\n\t" + "\n\t".join(funcs)) def check_gcc_flags(filename): with open(filename, 'r', encoding="utf8") as fh: for line in fh: line = line.rstrip() if test.verbose: print(":log: " + line) if re.search(r'' + test.vm_prefix + r'\S*\.cpp', line): filetype = "slow" if re.search(r'(Slow|Syms)', line) else "fast" opt = "fast" if re.search(r'-O2', line) else "slow" if test.verbose: print(filetype + ", " + opt + ", " + line) if filetype != opt: test.error(filetype + " file compiled as if was " + opt + ": " + line) elif re.search(r'.cpp', line) and not re.search(r'-Os', line): test.error("library file not compiled with OPT_GLOBAL: " + line) # This rule requires GNU make > 4.1 (or so, known broken in 3.81) #%__Slow.o: %__Slow.cpp # $(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_SLOW) -c -o $@ $< if not test.make_version or float(test.make_version) < 4.1: test.skip("Test requires GNU Make version >= 4.1") test.compile(v_flags2=["--exe", "--trace-vcd", "--output-split 1", "--output-groups 2", "--output-split-cfuncs 1", "--stats", "--dumpi-V3EmitMk 9", # Dev coverage of the V3EmitMk debug printer "../" + test.main_filename], verilator_make_gmake=False) # yapf:disable # We don't use the standard test_regress rules, as want to test the rules # properly build test.run(logfile=test.obj_dir + "/vlt_gcc.log", tee=test.verbose, cmd=[os.environ["MAKE"], "-C " + test.obj_dir, "-f "+test.vm_prefix+".mk", "-j 4", "VM_PREFIX="+test.vm_prefix, "TEST_OBJ_DIR="+test.obj_dir, "CPPFLAGS_DRIVER=-D"+test.name.upper(), ("CPPFLAGS_DRIVER2=-DTEST_VERBOSE=1" if test.verbose else ""), "OPT_FAST=-O2", "OPT_SLOW=-O0", "OPT_GLOBAL=-Os", ]) # yapf:disable test.execute() # Splitting should set VM_PARALLEL_BUILDS to 1 by default test.file_grep(test.obj_dir + "/" + test.vm_prefix + "_classes.mk", r'VM_PARALLEL_BUILDS\s*=\s*1') check_splits() check_no_all_file() check_gcc_flags(test.obj_dir + "/vlt_gcc.log") # Check that only vm_classes_*.cpp are to be compiled test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + "_classes.mk", "sub") test.file_grep(test.obj_dir + "/" + test.vm_prefix + "_classes.mk", "vm_classes_Slow_1") test.file_grep(test.obj_dir + "/" + test.vm_prefix + "_classes.mk", "vm_classes_1") test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + "_classes.mk", "vm_classes_Slow_2") test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + "_classes.mk", "vm_classes_2") # Check combine count test.file_grep(test.stats, r'Node count, CFILE + (\d+)', (219 if test.vltmt else 205)) test.file_grep(test.stats, r'Makefile targets, VM_CLASSES_FAST + (\d+)', 2) test.file_grep(test.stats, r'Makefile targets, VM_CLASSES_SLOW + (\d+)', 2) test.passes() verilator-5.042/test_regress/t/t_alias_width_bad.v0000644000542200017500000000061115101701376022674 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias' // // Alias width check error test. // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ // Inputs clk ); input clk; wire [1:0] a; wire [2:0] b; alias a = b; endmodule verilator-5.042/test_regress/t/t_initial_dlyass.v0000644000542200017500000000115415101701376022611 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc = 0; integer a; integer b; initial begin a <= 22; b <= 33; end always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==99) begin if (a != 22) $stop; if (b != 33) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_lint_restore_prag_bad.out0000644000542200017500000000044415101701376024474 0ustar mahmoudyfreeshell%Error: t/t_lint_restore_prag_bad.v:10:4: /*verilator lint_restore*/ without matching save 10 | /*verilator lint_restore*/ | ^~~~~~~~~~~~~~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_sys_fscanf_bad.out0000644000542200017500000000061315101701376023106 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_sys_fscanf_bad.v:13:7: Unsupported: %l in $fscanf 13 | $fscanf(file, "%l", i); | ^~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_sys_fscanf_bad.v:14:7: Unsupported: %m in $fscanf 14 | $fscanf(file, "%m", i); | ^~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_class_name.v0000644000542200017500000001004215101701376021702 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `ifdef verilator `define stop $stop `else `define stop `endif `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); function string unit_name; return $sformatf("u %m"); endfunction class Cls; // We use the same name for all static_name's to check we resolve right static function string static_name; return $sformatf("c %m"); endfunction // Different for non_statis to make sure likewise function string c_auto_name; return $sformatf("c %m"); endfunction endclass package P; class Cls; static function string static_name; return $sformatf("p %m"); endfunction function string p_auto_name; return $sformatf("p %m"); endfunction endclass endpackage module M; class Cls; static function string static_name; return $sformatf("m %m"); endfunction function string m_auto_name; return $sformatf("m %m"); endfunction endclass S sub(); function string cls_static_name; return Cls::static_name(); endfunction function string cls_auto_name; Cls c; c = new; return c.m_auto_name(); endfunction endmodule module S; class Cls; static function string static_name; return $sformatf("ms %m"); endfunction function string ms_auto_name; return $sformatf("ms %m"); endfunction endclass function string cls_static_name; return Cls::static_name(); endfunction function string cls_auto_name; Cls c; c = new; return c.ms_auto_name(); endfunction endmodule module t; string s; M m(); function string mod_func_name; return $sformatf("tmf %m"); endfunction initial begin Cls c; P::Cls p; p = new; c = new; s = mod_func_name(); `checks(s, "tmf top.t.mod_func_name"); s = unit_name(); `checks(s, "u top.$unit.unit_name"); // Others: "u $unit_????::unit_name // Others: "u $unit::unit_name // Others: "u \\package UnitScopePackage_1\ .UnitScopePackage_1.unit_name // *** Below results vary with simulator. s = Cls::static_name(); `checks(s, "c top.$unit.Cls.static_name"); // Others: "c $unit_????.Cls.static_name // Others: "c $unit::\Cls::static_name // Others: "c Cls.static_name s = c.c_auto_name(); `checks(s, "c top.$unit.Cls.c_auto_name"); // Others: "c $unit_????.Cls.c_auto_name // Others: "c $unit::\Cls::c_auto_name // Others: "c Cls.c_auto_name //UNSUP s = P::Cls::static_name(); //UNSUP `checks(s, "p top.P.Cls"); // UNSUP `checks(s, "p top.P.Cls.static_name"); // Others: "p P.Cls.static_name // Others: "p P::Cls.static_name // Others: "p P::\Cls::static_name // Others: "p \\package P\ .Cls.static_name s = p.p_auto_name(); `checks(s, "p top.P.Cls.p_auto_name"); // Others: "p P.Cls.p_auto_name // Others: "p P::Cls.p_auto_name // Others: "p P::\Cls::p_auto_name // Others: "p \\package P\ .Cls.p_auto_name s = m.cls_static_name(); `checks(s, "m top.t.m.Cls.static_name"); // Others: "m top.t.m.Cls.static_name // Others: "m top.t.m.\Cls::static_name s = m.cls_auto_name(); `checks(s, "m top.t.m.Cls.m_auto_name"); // Others: "m top.t.m.Cls.m_auto_name // Others: "m top.t.m.\Cls::m_auto_name s = m.sub.cls_static_name(); `checks(s, "ms top.t.m.sub.Cls.static_name"); // Others: "ms top.t.m.sub.Cls.static_name // Others: "ms top.t.m.sub.\Cls::static_name s = m.sub.cls_auto_name(); `checks(s, "ms top.t.m.sub.Cls.ms_auto_name"); // Others: "ms top.t.m.sub.Cls.ms_auto_name // Others: "ms top.t.m.sub.\Cls::ms_auto_name $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_vlt_match_error_1.out0000644000542200017500000000036015101701376023553 0ustar mahmoudyfreeshell%Error: t/t_vlt_match_error.v:17:12: Import package not found: 'hi' 17 | import hi::*; | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_randsequence.v0000644000542200017500000001541415101701376022262 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2023 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define check_range(gotv,minv,maxv) do if ((gotv) < (minv) || (gotv) > (maxv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d-%0d\n", `__FILE__,`__LINE__, (gotv), (minv), (maxv)); `stop; end while(0); `define check_within_30_percent(gotv,val) `check_range((gotv), (val) * 70 / 100, (val) * 130 / 100) module t; localparam int COUNT = 1000; int seq; int counts[8]; function automatic int sfunc(); int o = 2; randsequence(main) main : one; one : { o = 1; }; endsequence return o; endfunction task prep(); for (int i = 0; i < COUNT; ++i) counts[i] = 0; endtask initial begin; if (sfunc() != 1) $stop; // simple prep(); seq = 0; randsequence(main) main: one two three; two: { `checkd(seq, 1); seq = 2; }; one: { `checkd(seq, 0); seq = 1; }; three: { `checkd(seq, 2); seq = 3; }; endsequence `checkd(seq, 3); // simple unnamed prep(); seq = 0; randsequence() unnamed: { seq = 2; }; endsequence `checkd(seq, 2); // empty block prep(); randsequence() unnamed: { }; endsequence // weight prep(); for (int i = 0; i < COUNT; ++i) begin randsequence(main) main: one | two | three := 2; one: { ++counts[0]; }; two: { ++counts[1]; }; three: { ++counts[2]; }; endsequence end `check_within_30_percent(counts[0], COUNT * 1 / 4); `check_within_30_percent(counts[1], COUNT * 1 / 4); `check_within_30_percent(counts[2], COUNT * 2 / 4); // case prep(); for (int i = 0; i < COUNT; ++i) begin randsequence(main) main: one_if; one_if: if (i % 10 == 0) count_1 else most; count_1: { ++counts[1]; }; count_2: { ++counts[2]; }; count_3: { ++counts[3]; }; count_4: { ++counts[4]; }; bad: { $stop; }; most: case (i % 10) 0: bad; 1, 2: count_2; 3, 4, 5: count_3; default: count_4; endcase; endsequence end `check_within_30_percent(counts[1], COUNT * 1 / 10); `check_within_30_percent(counts[2], COUNT * 2 / 10); `check_within_30_percent(counts[3], COUNT * 3 / 10); `check_within_30_percent(counts[4], COUNT * 4 / 10); // case - different default prep(); for (int i = 0; i < COUNT; ++i) begin randsequence(main) main: one_if; one_if: if (i % 10 == 0) count_1 else most; count_1: { ++counts[1]; }; count_2: { ++counts[2]; }; count_3: { ++counts[3]; }; count_4: { ++counts[4]; }; bad: { $stop; }; most: case (i % 10) 0: bad; 1, 2: count_2; 3, 4, 5: count_3; default count_4; // No : endcase; endsequence end `check_within_30_percent(counts[1], COUNT * 1 / 10); `check_within_30_percent(counts[2], COUNT * 2 / 10); `check_within_30_percent(counts[3], COUNT * 3 / 10); `check_within_30_percent(counts[4], COUNT * 4 / 10); // repeat prep(); randsequence(main) main: repeat(10) count_1; count_1: { ++counts[1]; }; endsequence `checkd(counts[1], 10); // rand join prep(); for (int i = 0; i < COUNT; ++i) begin randsequence(main) main: rand join count_1 count_2; count_1: { ++counts[1]; }; count_2: { ++counts[2]; }; endsequence end `check_within_30_percent(counts[1], COUNT * 1 / 1); `check_within_30_percent(counts[2], COUNT * 1 / 1); // rand join weight (TODO weight not tested yet) prep(); for (int i = 0; i < COUNT; ++i) begin randsequence(main) main: rand join (1.0) count_1 count_2; count_1: { ++counts[1]; }; count_2: { ++counts[2]; }; endsequence randsequence(main) main: rand join (0.0) count_3 count_4; count_3: { ++counts[3]; }; count_4: { ++counts[4]; }; endsequence end `check_within_30_percent(counts[1], COUNT * 1 / 1); `check_within_30_percent(counts[2], COUNT * 1 / 1); `check_within_30_percent(counts[3], COUNT * 1 / 1); `check_within_30_percent(counts[4], COUNT * 1 / 1); // break prep(); for (int i = 0; i < COUNT; ++i) begin automatic bit fiftyfifty = i[0]; randsequence(main) main: count_1 check count_2; check: count_3 { if (fiftyfifty) break; } count_4; count_1: { ++counts[1]; }; count_2: { ++counts[2]; }; count_3: { ++counts[3]; }; count_4: { ++counts[4]; }; endsequence end `checkd(counts[1], COUNT * 1 / 1); `checkd(counts[2], COUNT * 1 / 2); // break `checkd(counts[3], COUNT * 1 / 1); `checkd(counts[4], COUNT * 1 / 2); // break or return // return prep(); for (int i = 0; i < COUNT; ++i) begin automatic bit fiftyfifty = i[0]; randsequence(main) main: count_1 check count_2; check: count_3 { if (fiftyfifty) return; } count_4; count_1: { ++counts[1]; }; count_2: { ++counts[2]; }; count_3: { ++counts[3]; }; count_4: { ++counts[4]; }; endsequence end `checkd(counts[1], COUNT * 1 / 1); `checkd(counts[2], COUNT * 1 / 1); // return `checkd(counts[3], COUNT * 1 / 1); `checkd(counts[4], COUNT * 1 / 2); // break or return // functions prep(); for (int i = 0; i < COUNT; ++i) begin randsequence(main) main: f_1 f_2 f_3; f_1 : func(10); f_2 : func(20); f_3 : fnoarg; void func(int n) : { counts[1] += n; }; void fnoarg : { ++counts[2]; }; endsequence end `checkd(counts[1], COUNT * (10 + 20)); `checkd(counts[2], COUNT * 1 / 1); // return $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_inst_array_partial.v0000644000542200017500000000500215101701376023464 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2011 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; // verilator lint_off MULTIDRIVEN wire [19:10] bitout; // verilator lint_on MULTIDRIVEN wire [29:24] short_bitout; wire [7:0] allbits; wire [15:0] twobits; sub i_sub1 [7:4] (.allbits (allbits), .twobits (twobits[15:8]), .bitout (bitout[17:14])), i_sub2 [3:0] (.allbits (allbits), .twobits (twobits[7:0]), .bitout (bitout[13:10])); sub i_sub3 [7:4] (.allbits (allbits), .twobits (twobits[15:8]), .bitout (bitout[17:14])); sub i_sub4 [7:4] (.allbits (allbits), .twobits (twobits[15:8]), .bitout (short_bitout[27:24])); sub i_sub5 [7:0] (.allbits (allbits), .twobits (twobits), .bitout (bitout[17:10])); sub i_sub6 [7:4] (.allbits (allbits), .twobits (twobits[15:8]), .bitout ({bitout[18+:2],short_bitout[28+:2]})); integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Signals under test assign allbits = crc[7:0]; assign twobits = crc[15:0]; wire [63:0] result = {48'h0, short_bitout, bitout}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'ha1da9ff8082a4ff6 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule // t module sub ( input wire [7:0] allbits, input wire [1:0] twobits, output wire bitout); assign bitout = (^ twobits) ^ (^ allbits); endmodule // sub verilator-5.042/test_regress/t/t_gen_var_bad.py0000755000542200017500000000076615101701376022226 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_assert_comp_bad.out0000644000542200017500000000562315101701376023275 0ustar mahmoudyfreeshell-Info: t/t_assert_comp_bad.v:13:5: Elaboration system task message (IEEE 1800-2023 20.11) : ... note: In instance 't' 13 | $info; | ^~~~~ -Info: t/t_assert_comp_bad.v:14:5: User elaboration-time info : ... note: In instance 't' 14 | $info("User elaboration-time info"); | ^~~~~ -Info: t/t_assert_comp_bad.v:15:5: Percent=% PctPct=%% Ten=10 : ... note: In instance 't' 15 | $info("Percent=%% PctPct=%s Ten=%0d", PCTPCT, TEN); | ^~~~~ %Warning-USERWARN: t/t_assert_comp_bad.v:16:5: Elaboration system task message (IEEE 1800-2023 20.11) : ... note: In instance 't' 16 | $warning; | ^~~~~~~~ ... For warning description see https://verilator.org/warn/USERWARN?v=latest ... Use "/* verilator lint_off USERWARN */" and lint_on around source to disable this message. %Warning-USERWARN: t/t_assert_comp_bad.v:17:5: User elaboration-time warning : ... note: In instance 't' 17 | $warning("User elaboration-time warning"); | ^~~~~~~~ %Warning-USERWARN: t/t_assert_comp_bad.v:18:5: 1 : ... note: In instance 't' 18 | $warning(1); | ^~~~~~~~ %Warning-USERERROR: t/t_assert_comp_bad.v:19:5: Elaboration system task message (IEEE 1800-2023 20.11) : ... note: In instance 't' 19 | $error; | ^~~~~~ ... For warning description see https://verilator.org/warn/USERERROR?v=latest ... Use "/* verilator lint_off USERERROR */" and lint_on around source to disable this message. %Warning-USERERROR: t/t_assert_comp_bad.v:20:5: User elaboration-time error : ... note: In instance 't' 20 | $error("User elaboration-time error"); | ^~~~~~ %Warning-USERFATAL: t/t_assert_comp_bad.v:21:5: User elaboration-time fatal : ... note: In instance 't' 21 | $fatal(0, "User elaboration-time fatal"); | ^~~~~~ ... For warning description see https://verilator.org/warn/USERFATAL?v=latest ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. %Warning-USERFATAL: t/t_assert_comp_bad.v:22:5: Elaboration system task message (IEEE 1800-2023 20.11) : ... note: In instance 't' 22 | $fatal(0); | ^~~~~~ %Warning-USERFATAL: t/t_assert_comp_bad.v:23:5: Elaboration system task message (IEEE 1800-2023 20.11) : ... note: In instance 't' 23 | $fatal; | ^~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_flag_generate_key.py0000755000542200017500000000120115101701376023413 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(v_flags2=["--generate-key"], verilator_make_gmake=False, make_top_shell=False, make_main=False) test.file_grep(test.compile_log_filename, r'VL-KEY') test.passes() verilator-5.042/test_regress/t/t_probdist_bad.py0000755000542200017500000000073415101701376022426 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_json_only_flat_vlvbound.py0000755000542200017500000000137115101701376024727 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') out_filename = test.obj_dir + "/V" + test.name + ".tree.json" test.compile(verilator_flags2=['--no-std', '--json-only', '--no-json-edit-nums', '--flatten'], verilator_make_gmake=False, make_top_shell=False, make_main=False) test.files_identical(out_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_difftree.a.tree0000644000542200017500000000137515101701376022307 0ustar mahmoudyfreeshellVerilator Tree Dump (format 0x3900) from to NETLIST 0x555556bb6000 {a0aa} $root [1ps/1ps] 1: MODULE 0x555556bc0120 {d19ai} t L2 [1ps] 1:2: PORT 0x555556bc60d0 {d21ae} clk 1:2: VAR 0x555556bbe180 {d23ak} @dt=0@ clk INPUT PORT 1:2:1: BASICDTYPE 0x555556bc61a0 {d23ak} @dt=this@(nw0) LOGIC_IMPLICIT kwd=LOGIC_IMPLICIT 3: TYPETABLE 0x555556bbc000 {a0aa} logic -> BASICDTYPE 0x555556c71a00 {d55ap} @dt=this@(G/nw1) logic [GENERIC] kwd=logic 3: CONSTPOOL 0x555556bbe000 {a0aa} 3:1: MODULE 0x555556bc0000 {a0aa} @CONST-POOL@ L0 [NONE] 3:1:2: SCOPE 0x555556bb60f0 {a0aa} @CONST-POOL@ [abovep=0] [cellp=0] [modp=0x555556bc0000] verilator-5.042/test_regress/t/t_dpi_unpack_bad.out0000644000542200017500000000453415101701376023073 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_dpi_unpack_bad.v:21:20: Shape of the argument does not match the shape of the parameter ('logic[2:0]' v.s. 'logic[3:0]') : ... note: In instance 't' 21 | import_func0(sig0); | ^~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Warning-WIDTHEXPAND: t/t_dpi_unpack_bad.v:21:7: Operator TASKREF 'import_func0' expects 4 bits on the Function Argument, but Function Argument's VARREF 'sig0' generates 3 bits. : ... note: In instance 't' 21 | import_func0(sig0); | ^~~~~~~~~~~~ ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. %Error-UNSUPPORTED: t/t_dpi_unpack_bad.v:23:20: Shape of the argument does not match the shape of the parameter ('logic[2:0]$[0:2][0:1]' v.s. 'logic[2:0]$[0:2]') : ... note: In instance 't' 23 | import_func1(sig1); | ^~~~ %Error-UNSUPPORTED: t/t_dpi_unpack_bad.v:25:20: Shape of the argument does not match the shape of the parameter ('logic[2:0]$[0:2][0:1]' v.s. 'logic[2:0]$[0:2][0:2]') : ... note: In instance 't' 25 | import_func2(sig1); | ^~~~ %Error-UNSUPPORTED: t/t_dpi_unpack_bad.v:27:20: Shape of the argument does not match the shape of the parameter ('bit[2:0]' v.s. 'logic[2:0]') : ... note: In instance 't' 27 | import_func2(sig2); | ^~~~ %Error-UNSUPPORTED: t/t_dpi_unpack_bad.v:29:24: Argument is not an unpacked array while parameter 'in' is : ... note: In instance 't' 29 | import_func0(sig0[1]); | ^ %Warning-WIDTHEXPAND: t/t_dpi_unpack_bad.v:29:7: Operator TASKREF 'import_func0' expects 4 bits on the Function Argument, but Function Argument's ARRAYSEL generates 3 bits. : ... note: In instance 't' 29 | import_func0(sig0[1]); | ^~~~~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_sv_conditional.v0000644000542200017500000003623515101701376022624 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: System Verilog test of case and if // // This code instantiates and runs a simple CPU written in System Verilog. // // This file ONLY is placed into the Public Domain, for any use, without // warranty. // SPDX-License-Identifier: CC0-1.0 // Contributed 2012 by M W Lund, Atmel Corporation and Jeremy Bennett, Embecosm. module t (/*AUTOARG*/ // Inputs clk ); input clk; /*AUTOWIRE*/ // ************************************************************************** // Regs and Wires // ************************************************************************** reg rst; integer rst_count; st3_testbench st3_testbench_i (/*AUTOINST*/ // Inputs .clk (clk), .rst (rst)); // ************************************************************************** // Reset Generation // ************************************************************************** initial begin rst = 1'b1; rst_count = 0; end always @( posedge clk ) begin if (rst_count < 2) begin rst_count++; end else begin rst = 1'b0; end end // ************************************************************************** // Closing message // ************************************************************************** final begin $write("*-* All Finished *-*\n"); end endmodule module st3_testbench (/*AUTOARG*/ // Inputs clk, rst ); input clk; input rst; logic clk; logic rst; logic [8*16-1:0] wide_input_bus; logic decrementA; // 0=Up-counting, 1=down-counting logic dual_countA; // Advance counter by 2 steps at a time logic cntA_en; // Enable Counter A logic decrementB; // 0=Up-counting, 1=down-counting logic dual_countB; // Advance counter by 2 steps at a time logic cntB_en; // Enable counter B logic [47:0] selected_out; integer i; initial begin decrementA = 1'b0; dual_countA = 1'b0; cntA_en = 1'b1; decrementB = 1'b0; dual_countB = 1'b0; cntB_en = 1'b1; wide_input_bus = {8'hf5, 8'hef, 8'hd5, 8'hc5, 8'hb5, 8'ha5, 8'h95, 8'h85, 8'ha7, 8'ha6, 8'ha5, 8'ha4, 8'ha3, 8'ha2, 8'ha1, 8'ha0}; i = 0; end simple_test_3 simple_test_3_i (// Outputs .selected_out (selected_out[47:0]), // Inputs .wide_input_bus (wide_input_bus[8*16-1:0]), .rst (rst), .clk (clk), .decrementA (decrementA), .dual_countA (dual_countA), .cntA_en (cntA_en), .decrementB (decrementB), .dual_countB (dual_countB), .cntB_en (cntB_en)); // Logic to print outputs and then finish. always @(posedge clk) begin if (i < 50) begin `ifdef TEST_VERBOSE $display("%x", simple_test_3_i.cntA_reg ,"%x", simple_test_3_i.cntB_reg ," ", "%x", selected_out); `endif i <= i + 1; end else begin $finish(); end end // always @ (posedge clk) endmodule // Module testing: // - Unique case // - Priority case // - Unique if // - ++, --, =- and =+ operands. module simple_test_3 (input logic [8*16-1:0] wide_input_bus, input logic rst, input logic clk, // Counter A input logic decrementA, // 0=Up-counting, 1=down-counting input logic dual_countA, // Advance counter by 2 steps at a time input logic cntA_en, // Enable Counter A // Counter B input logic decrementB, // 0=Up-counting, 1=down-counting input logic dual_countB, // Advance counter by 2 steps at a time input logic cntB_en, // Enable counter B // Outputs output logic [47:0] selected_out); // Declarations logic [3:0] cntA_reg; // Registered version of cntA logic [3:0] cntB_reg; // Registered version of cntA counterA counterA_inst (/*AUTOINST*/ // Outputs .cntA_reg (cntA_reg[3:0]), // Inputs .decrementA (decrementA), .dual_countA (dual_countA), .cntA_en (cntA_en), .clk (clk), .rst (rst)); counterB counterB_inst (/*AUTOINST*/ // Outputs .cntB_reg (cntB_reg[3:0]), // Inputs .decrementB (decrementB), .dual_countB (dual_countB), .cntB_en (cntB_en), .clk (clk), .rst (rst)); simple_test_3a sta (.wide_input_bus (wide_input_bus), .selector (cntA_reg), .selected_out (selected_out[7:0])); simple_test_3b stb (.wide_input_bus (wide_input_bus), .selector (cntA_reg), .selected_out (selected_out[15:8])); simple_test_3c stc (.wide_input_bus (wide_input_bus), .selector (cntB_reg), .selected_out (selected_out[23:16])); simple_test_3d std (.wide_input_bus (wide_input_bus), .selector (cntB_reg), .selected_out (selected_out[31:24])); simple_test_3e ste (.wide_input_bus (wide_input_bus), .selector (cntB_reg), .selected_out (selected_out[39:32])); simple_test_3f stf (.wide_input_bus (wide_input_bus), .selector (cntB_reg), .selected_out (selected_out[47:40])); endmodule // simple_test_3 module counterA (output logic [3:0] cntA_reg, // Registered version of cntA input logic decrementA, // 0=Up-counting, 1=down-counting input logic dual_countA, // Advance counter by 2 steps at a time input logic cntA_en, // Enable Counter A input logic clk, // Clock input logic rst); // Synchronous reset logic [3:0] cntA; // combinational count variable. // Counter A // Sequential part of counter CntA always_ff @(posedge clk) begin cntA_reg <= cntA; end // Combinational part of counter // Had to be split up to test C-style update, as there are no // non-blocking version like -<= always_comb if (rst) cntA = 0; else begin cntA = cntA_reg; // Necessary to avoid latch if (cntA_en) begin if (decrementA) if (dual_countA) //cntA = cntA - 2; cntA -= 2; else //cntA = cntA - 1; cntA--; else if (dual_countA) //cntA = cntA + 2; cntA += 2; else //cntA = cntA + 1; cntA++; end // if (cntA_en) end endmodule // counterA module counterB (output logic [3:0] cntB_reg, // Registered version of cntA input logic decrementB, // 0=Up-counting, 1=down-counting input logic dual_countB, // Advance counter by 2 steps at a time input logic cntB_en, // Enable counter B input logic clk, // Clock input logic rst); // Synchronous reset // Counter B - tried to write sequential only, but ended up without // SystemVerilog. always_ff @(posedge clk) begin if (rst) cntB_reg <= 0; else if (cntB_en) begin if (decrementB) if (dual_countB) cntB_reg <= cntB_reg - 2; else cntB_reg <= cntB_reg - 1; // Attempts to write in SystemVerilog: else if (dual_countB) cntB_reg <= cntB_reg + 2; else cntB_reg <= cntB_reg + 1; // Attempts to write in SystemVerilog: end end // always_ff @ endmodule // A multiplexor in terms of look-up module simple_test_3a (input logic [8*16-1:0] wide_input_bus, input logic [3:0] selector, output logic [7:0] selected_out); always_comb selected_out = {wide_input_bus[selector*8+7], wide_input_bus[selector*8+6], wide_input_bus[selector*8+5], wide_input_bus[selector*8+4], wide_input_bus[selector*8+3], wide_input_bus[selector*8+2], wide_input_bus[selector*8+1], wide_input_bus[selector*8]}; endmodule // simple_test_3a // A multiplexer in terms of standard case module simple_test_3b (input logic [8*16-1:0] wide_input_bus, input logic [3:0] selector, output logic [7:0] selected_out); always_comb begin case (selector) 4'h0: selected_out = wide_input_bus[ 7: 0]; 4'h1: selected_out = wide_input_bus[ 15: 8]; 4'h2: selected_out = wide_input_bus[ 23: 16]; 4'h3: selected_out = wide_input_bus[ 31: 24]; 4'h4: selected_out = wide_input_bus[ 39: 32]; 4'h5: selected_out = wide_input_bus[ 47: 40]; 4'h6: selected_out = wide_input_bus[ 55: 48]; 4'h7: selected_out = wide_input_bus[ 63: 56]; 4'h8: selected_out = wide_input_bus[ 71: 64]; 4'h9: selected_out = wide_input_bus[ 79: 72]; 4'ha: selected_out = wide_input_bus[ 87: 80]; 4'hb: selected_out = wide_input_bus[ 95: 88]; 4'hc: selected_out = wide_input_bus[103: 96]; 4'hd: selected_out = wide_input_bus[111:104]; 4'he: selected_out = wide_input_bus[119:112]; 4'hf: selected_out = wide_input_bus[127:120]; endcase // case (selector) end endmodule // simple_test_3b // A multiplexer in terms of unique case module simple_test_3c (input logic [8*16-1:0] wide_input_bus, input logic [3:0] selector, output logic [7:0] selected_out); always_comb begin unique case (selector) 4'h0: selected_out = wide_input_bus[ 7: 0]; 4'h1: selected_out = wide_input_bus[ 15: 8]; 4'h2: selected_out = wide_input_bus[ 23: 16]; 4'h3: selected_out = wide_input_bus[ 31: 24]; 4'h4: selected_out = wide_input_bus[ 39: 32]; 4'h5: selected_out = wide_input_bus[ 47: 40]; 4'h6: selected_out = wide_input_bus[ 55: 48]; 4'h7: selected_out = wide_input_bus[ 63: 56]; 4'h8: selected_out = wide_input_bus[ 71: 64]; 4'h9: selected_out = wide_input_bus[ 79: 72]; 4'ha: selected_out = wide_input_bus[ 87: 80]; 4'hb: selected_out = wide_input_bus[ 95: 88]; 4'hc: selected_out = wide_input_bus[103: 96]; 4'hd: selected_out = wide_input_bus[111:104]; 4'he: selected_out = wide_input_bus[119:112]; 4'hf: selected_out = wide_input_bus[127:120]; endcase // case (selector) end endmodule // simple_test_3c // A multiplexer in terms of unique if module simple_test_3d (input logic [8*16-1:0] wide_input_bus, input logic [3:0] selector, output logic [7:0] selected_out); always_comb begin unique if (selector == 4'h0) selected_out = wide_input_bus[ 7: 0]; else if (selector == 4'h1) selected_out = wide_input_bus[ 15: 8]; else if (selector == 4'h2) selected_out = wide_input_bus[ 23: 16]; else if (selector == 4'h3) selected_out = wide_input_bus[ 31: 24]; else if (selector == 4'h4) selected_out = wide_input_bus[ 39: 32]; else if (selector == 4'h5) selected_out = wide_input_bus[ 47: 40]; else if (selector == 4'h6) selected_out = wide_input_bus[ 55: 48]; else if (selector == 4'h7) selected_out = wide_input_bus[ 63: 56]; else if (selector == 4'h8) selected_out = wide_input_bus[ 71: 64]; else if (selector == 4'h9) selected_out = wide_input_bus[ 79: 72]; else if (selector == 4'ha) selected_out = wide_input_bus[ 87: 80]; else if (selector == 4'hb) selected_out = wide_input_bus[ 95: 88]; else if (selector == 4'hc) selected_out = wide_input_bus[103: 96]; else if (selector == 4'hd) selected_out = wide_input_bus[111:104]; else if (selector == 4'he) selected_out = wide_input_bus[119:112]; else if (selector == 4'hf) selected_out = wide_input_bus[127:120]; end endmodule // simple_test_3d // Test of priority case // Note: This does NOT try to implement the same function as above. module simple_test_3e (input logic [8*16-1:0] wide_input_bus, input logic [3:0] selector, output logic [7:0] selected_out); always_comb begin priority case (1'b1) selector[0]: selected_out = wide_input_bus[ 7: 0]; // Bit 0 has highets priority selector[2]: selected_out = wide_input_bus[ 39: 32]; // Note 2 higher priority than 1 selector[1]: selected_out = wide_input_bus[ 23: 16]; // Note 1 lower priority than 2 selector[3]: selected_out = wide_input_bus[ 71: 64]; // Bit 3 has lowest priority default: selected_out = wide_input_bus[127:120]; // for selector = 0. endcase // case (selector) end endmodule // simple_test_3e // Test of "inside" // Note: This does NOT try to implement the same function as above. // Note: Support for "inside" is a separate Verilator feature request, so is // not used inside a this version of the test. module simple_test_3f (input logic [8*16-1:0] wide_input_bus, input logic [3:0] selector, output logic [7:0] selected_out); always_comb begin /* -----\/----- EXCLUDED -----\/----- if ( selector[3:0] inside { 4'b?00?, 4'b1100}) // Matching 0000, 0001, 1000, 1100, 1001 // if ( selector[3:2] inside { 2'b?0, selector[1:0]}) selected_out = wide_input_bus[ 7: 0]; else -----/\----- EXCLUDED -----/\----- */ /* verilator lint_off CASEOVERLAP */ priority casez (selector[3:0]) 4'b0?10: selected_out = wide_input_bus[ 15: 8]; // Matching 0010 and 0110 4'b0??0: selected_out = wide_input_bus[ 23: 16]; // Overlap: only 0100 remains (0000 in "if" above) 4'b0100: selected_out = wide_input_bus[ 31: 24]; // Overlap: Will never occur default: selected_out = wide_input_bus[127:120]; // Remaining 0011,0100,0101,0111,1010,1011,1101,1110,1111 endcase // case (selector) /* verilator lint_on CASEOVERLAP */ end endmodule // simple_test_3f verilator-5.042/test_regress/t/t_class_param_noinit_bad.py0000755000542200017500000000076615101701376024452 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface_paren_missing_bad.out0000644000542200017500000000105715101701376025631 0ustar mahmoudyfreeshell%Error: t/t_interface_paren_missing_bad.v:13:4: Interface 'intf' not connected as parent's interface not connected : ... Perhaps caused by another error on the parent interface that needs resolving : ... Or, perhaps intended an interface instantiation but are missing parenthesis (IEEE 1800-2023 25.3)? 13 | intf intf_i; | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_flag_wfatal.v0000644000542200017500000000043715101701376022053 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; // Width error below wire [3:0] foo = 6'h2e; endmodule verilator-5.042/test_regress/t/t_time_vpi_1fs1fs.out0000644000542200017500000000170415101701376023143 0ustar mahmoudyfreeshell:: In top.t Time scale of t is 1fs / 1fs [60] time%0d=60 123%0t=123 dig%0t=5432109876543210 dig%0d=5432109876543210 rdig%0t=5432109876543210 rdig%0f=5432109876543210.000000 acc%0t=12345678901234567890 acc%0d=12345678901234567890 [0.000060ns] time%0d=60 123%0t=0.000123ns dig%0t=5432109876.543210ns dig%0d=5432109876543210 rdig%0t=5432109876.543210ns rdig%0f=5432109876543210.000000 acc%0t=12345678901234.567890ns acc%0d=12345678901234567890 [0.000060ns] stime%0t=0.000060ns stime%0d=60 stime%0f=60.000000 [0.000060ns] rtime%0t=0.000060ns rtime%0d=60 rtime%0f=60.000000 global svGetTime = 0 0,60 global svGetTimeUnit = 0 -15 svGetTmePrecision = 0 -15 global vpiSimTime = 0,60 vpiScaledRealTime = 60 global vpiTimeUnit = -15 vpiTimePrecision = -15 top.t svGetTime = 0 0,60 top.t svGetTimeUnit = 0 -15 svGetTmePrecision = 0 -15 top.t vpiSimTime = 0,60 vpiScaledRealTime = 60 top.t vpiTimeUnit = -15 vpiTimePrecision = -15 *-* All Finished *-* verilator-5.042/test_regress/t/t_class_compare.v0000644000542200017500000000261415101701376022416 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Check == and != operations performed on class objects // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Ilya Barkov. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define check_comp(lhs, rhs, op, exp) if ((exp) != ((lhs) op (rhs))) begin $write("%%Error: %s:%0d: op comparison shall return 'b%x\n", `__FILE__, `__LINE__, (exp)); `stop; end // Two checks because == and != may not be derived from each other `define check_eq(lhs, rhs) `check_comp(lhs, rhs, ==, 1'b1) `check_comp(lhs, rhs, !=, 1'b0) `define check_ne(lhs, rhs) `check_comp(lhs, rhs, ==, 1'b0) `check_comp(lhs, rhs, !=, 1'b1) class Cls; class InnerCls; int j; endclass int i; endclass class ExtendCls extends Cls; endclass module t; initial begin Cls a = new; Cls b = new; ExtendCls ext = new; Cls::InnerCls ia = new; Cls::InnerCls ib = new; ExtendCls::InnerCls iext = new; `check_ne(a, b) `check_ne(a, ext) `check_ne(ext, a) `check_ne(ia, ib) `check_ne(ia, iext) `check_ne(iext, ia) a = b; ia = ib; `check_eq(a, b) `check_eq(ia, ib) a = ext; ia = iext; `check_eq(a, ext) `check_eq(ext, a) `check_eq(ia, iext) `check_eq(iext, ia) $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_gen_local.v0000644000542200017500000000133215101701376021522 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; localparam N = 31; wire [31:0] vec; generate genvar g; // bug461 begin : topgen for (g=0; g #define STRINGIFY_IMPL(str) #str #define STRINGIFY(str) STRINGIFY_IMPL(str) namespace { struct statically_initialized { statically_initialized() { std::cout << "MACRO:" << STRINGIFY(CPP_MACRO) << " is defined" << std::endl; } } g_statically_initialized; } `verilog `endif // PROTLIB_TOP endmodule module non_hier_sub0( input wire clk, input wire[7:0] in, output wire [7:0] out); sub0 i_sub0(.*); endmodule module sub0( input wire clk, input wire [7:0] in, output wire [7:0] out); `HIER_BLOCK logic [7:0] ff; always_ff @(posedge clk) ff <= in; assign out = ff; endmodule module sub1( input wire clk, input wire [11:4] in, // Uses higher LSB to cover bug3539 output wire [7:0] out); `HIER_BLOCK logic [7:0] ff; always_ff @(posedge clk) ff <= in + 1; assign out = ff; endmodule module sub2( input wire clk, input wire [7:0] in, output wire [7:0] out); `HIER_BLOCK logic [7:0] ff; // dpi_import_func returns (dpi_eport_func(v) -1) import "DPI-C" context function int dpi_import_func(int v); export "DPI-C" function dpi_export_func; function int dpi_export_func(int v); return v + 1; endfunction always_ff @(posedge clk) ff <= 8'(dpi_import_func({24'b0, in})) + 8'd2; byte_ifs in_ifs(.clk(clk)); byte_ifs out_ifs(.clk(clk)); assign in_ifs.data = ff; assign out = out_ifs.data; non_hier_sub3 i_sub3(.in(in_ifs), .out(out_ifs)); always @(posedge clk) // dotted access within a hierarchical block should be OK if (i_sub3.in_wire != ff) begin $display("Error mismatch in %m"); $stop; end endmodule module non_hier_sub3( byte_ifs.receiver in, byte_ifs.sender out); wire [7:0] in_wire, out_1, out_2; assign in_wire = in.data; localparam string sparam = "single quote escape comma:'\\,"; // Parameter appears in the different order from module declaration sub3 #(.STR(sparam), .UNUSED(-16'sd3), .P0(8'd3), .ENUM(enum_val_3)) i_sub3(.clk(in.clk), .in(in.data), .out(out_1)); // Instantiate again, should use the same wrapper sub3 #(.STR(sparam), .UNUSED(-16'sd3), .P0(8'd3), .ENUM(enum_val_3)) i_sub3_2(.clk(in.clk), .in(in.data), .out(out_2)); always @(posedge in.clk) if (out_1 != out_2) $stop; assign out.data = out_1; endmodule module sub3 #( parameter logic [7:0] P0 = 2 + 1, type TYPE = logic, parameter int UNPACKED_ARRAY[2] = '{0, 1}, parameter logic signed [15:0] UNUSED = -3, parameter string STR = "str", parameter enum_t ENUM = enum_val_0) ( input wire clk, input wire [7:0] in, output wire [7:0] out); `HIER_BLOCK initial $display("P0:%d UNUSED:%d %s %d", P0, UNUSED, STR, ENUM); TYPE [7:0] ff; always_ff @(posedge clk) ff <= in + P0; always_ff @(posedge clk) if (out4 != out4_2) $stop; wire [7:0] out4; wire [7:0] out4_2; assign out = out4; /* verilator lint_off REALCVT */ sub4 #(.P0(1.6), .P1(3.1), .P3(4.1)) i_sub4_0(.clk(clk), .in(ff), .out(out4)); // incr 2 sub4 #(.P0(2.4), .P1(3.1), .P3(5)) i_sub4_1(.clk(clk), .in(), .out(out4_2)); /* verilator lint_on REALCVT */ /* verilator lint_off ASSIGNIN */ assign i_sub4_1.in = ff; // Hierarchical reference to port of hier_block is OK /* verilator lint_off ASSIGNIN */ always @(posedge clk) begin $display("%d %m child input ports: %d %d", $time, i_sub4_0.in, i_sub4_1.in); $display("%d %m child output ports: %d %d", $time, i_sub4_0.out, i_sub4_1.out); end endmodule module sub4 #( parameter int P0 = 1.1, parameter P1 = 2, parameter real P3 = 3) ( input wire clk, input wire [7:0] in, output wire[7:0] out); `HIER_BLOCK initial begin if (P1 == 2) begin $display("P1(%f) is not properly set", P1); $stop; end end reg [7:0] ff; always_ff @(posedge clk) ff <= in + 8'(P0); assign out = ff; logic [127:0] sub5_in[2][3]; wire [7:0] sub5_out[2][3]; sub5 i_sub5(.clk(clk), .in(sub5_in), .out(sub5_out)); int count = 0; always @(posedge clk) begin if (!count[0]) begin sub5_in[0][0] <= 128'd0; sub5_in[0][1] <= 128'd1; sub5_in[0][2] <= 128'd2; sub5_in[1][0] <= 128'd3; sub5_in[1][1] <= 128'd4; sub5_in[1][2] <= 128'd5; end else begin sub5_in[0][0] <= 128'd0; sub5_in[0][1] <= 128'd0; sub5_in[0][2] <= 128'd0; sub5_in[1][0] <= 128'd0; sub5_in[1][1] <= 128'd0; sub5_in[1][2] <= 128'd0; end end always @(posedge clk) begin count <= count + 1; if (count > 0) begin for (int i = 0; i < 2; ++i) begin for (int j = 0; j < 3; ++j) begin automatic byte exp = !count[0] ? 8'(3 * (1 - i) + (2- j) + 1) : 8'b0; if (sub5_out[i][j] != exp) begin $display("in[%d][%d] act:%d exp:%d", i, j, sub5_out[i][j], exp); $stop; end if (i_sub5.out[i][j] != exp) begin $display("in[%d][%d] act:%d exp:%d", i, j, i_sub5.out[i][j], exp); $stop; end end end end end endmodule module sub5 (input wire clk, input wire [127:0] in[2][3], output logic [7:0] out[2][3]); `HIER_BLOCK int count = 0; always @(posedge clk) begin count <= count + 1; if (count > 0) begin for (int i = 0; i < 2; ++i) begin for (int j = 0; j < 3; ++j) begin automatic bit [127:0] exp = count[0] ? 128'(3 * i + 128'(j)) : 128'd0; if (in[i][j] != exp) begin $display("in[%d][%d] act:%d exp:%d", i, j, in[i][j], exp); $stop; end end end end end always @(posedge clk) begin if (count[0]) begin out[0][0] <= 8'd6; out[0][1] <= 8'd5; out[0][2] <= 8'd4; out[1][0] <= 8'd3; out[1][1] <= 8'd2; out[1][2] <= 8'd1; end else begin out[0][0] <= 8'd0; out[0][1] <= 8'd0; out[0][2] <= 8'd0; out[1][0] <= 8'd0; out[1][1] <= 8'd0; out[1][2] <= 8'd0; end end wire [7:0] val0[2]; wire [7:0] val1[2]; wire [7:0] val2[2]; wire [7:0] val3[2]; sub6 i_sub0(.out(val0)); sub6 #(.P0(1)) i_sub1(.out(val1)); // Setting the default value sub6 #(.P0(1), .P1(2)) i_sub2(.out(val2)); // Setting the default value sub6 #(.P0(1), .P1(3)) i_sub3(.out(val3)); always @(posedge clk) begin if (val0[0] != 1 || val0[1] != 2) $stop; if (val1[0] != 1 || val1[1] != 2) $stop; if (val2[0] != 1 || val2[1] != 2) $stop; if (val3[0] != 1 || val3[1] != 3) $stop; end endmodule module sub6 #(parameter P0 = 1, parameter P1 = 2) (output wire [7:0] out[2]); `HIER_BLOCK assign out[0] = 8'(P0); assign out[1] = 8'(P1); endmodule module delay #( parameter N = 1, parameter WIDTH = 8) ( input wire clk, input wire[WIDTH-1:0] in, output wire [WIDTH-1:0]out); `HIER_BLOCK reg [WIDTH-1:0] tmp; always_ff @(posedge clk) tmp <= in; if (N > 1) begin delay #(.N(N - 1), WIDTH) i_delay(clk, tmp, out); end else begin assign out = tmp; end endmodule verilator-5.042/test_regress/t/t_var_ref_bad3.v0000644000542200017500000000051515101701376022116 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Make sure type errors aren't suppressable // verilator lint_off WIDTH module t(ref int bad_primary_ref); endmodule verilator-5.042/test_regress/t/t_math_pow3.v0000644000542200017500000001012615101701376021501 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); fail=1; end while(0) module t; bit fail; // IEEE says for ** the size is L(i). Thus Icarus Verilog is wrong in sizing some of the below. initial begin // NC=67b6cfc1b29a21 VCS=c1b29a20(wrong) IV=67b6cfc1b29a21 Verilator=67b6cfc1b29a21 $display("15 ** 14 = %0x expect 67b6cfc1b29a21", 64'b1111 ** 64'b1110); // NC=1 VCS=0 IV=0 Verilator=1 (wrong,fixed) $display("15 **-4'sd2 = %0x expect 0 (per IEEE negative power)", ((-4'd1 ** -4'sd2))); // NC=1 VCS=0 IV=67b6cfc1b29a21(wrong) Verilator=1 $display("15 ** 14 = %0x expect 1 (LSB 4-bits of 67b6cfc1b29a21)", ((-4'd1 ** -4'd2))); // NC=1 VCS=0 IV=67b6cfc1b29a21(wrong) Verilator=1 $display("15 ** 14 = %0x expect 1 (LSB 4-bits of 67b6cfc1b29a21)", ((4'd15 ** 4'd14))); // NC=8765432187654321 VCS=8765432187654000(wrong) IV=8765432187654321 Verilator=8765432187654321 $display("64'big ** 1 = %0x expect %0x", 64'h8765432187654321 ** 1, 64'h8765432187654321); $display("\n"); `checkh( (64'b1111 ** 64'b1110), 64'h67b6cfc1b29a21); `checkh( (-4'd1 ** -4'sd2), 4'h0); //bug730 `checkh( (-4'd1 ** -4'd2), 4'h1); `checkh( (4'd15 ** 4'd14), 4'h1); `checkh( (64'h8765432187654321 ** 4'h1), 64'h8765432187654321); `checkh((-8'sh3 ** 8'h3) , 8'he5 ); // a**b (-27) `checkh((-8'sh1 ** 8'h2) , 8'h1 ); // -1^odd=-1, -1^even=1 `checkh((-8'sh1 ** 8'h3) , 8'hff ); // -1^odd=-1, -1^even=1 `checkh(( 8'h0 ** 8'h3) , 8'h0 ); // 0 `checkh(( 8'h1 ** 8'h3) , 8'h1 ); // 1 `checkh(( 8'h3 ** 8'h3) , 8'h1b ); // a**b (27) `checkh(( 8'sh3 ** 8'h3) , 8'h1b ); // a**b (27) `checkh(( 8'h6 ** 8'h3) , 8'hd8 ); // a**b (216) `checkh(( 8'sh6 ** 8'h3) , 8'hd8 ); // a**b (216) `checkh((-8'sh3 ** 8'sh3), 8'he5 ); // a**b `checkh((-8'sh1 ** 8'sh2), 8'h1 ); // -1^odd=-1, -1^even=1 `checkh((-8'sh1 ** 8'sh3), 8'hff ); // -1^odd=-1, -1^even=1 `checkh(( 8'h0 ** 8'sh3), 8'h0 ); // 0 `checkh(( 8'h1 ** 8'sh3), 8'h1 ); // 1 `checkh(( 8'h3 ** 8'sh3), 8'h1b ); // a**b (27) `checkh(( 8'sh3 ** 8'sh3), 8'h1b ); // a**b (27) `checkh(( 8'h6 ** 8'sh3), 8'hd8 ); // a**b (216) `checkh(( 8'sh6 ** 8'sh3), 8'hd8 ); // a**b (216) `checkh((-8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1 `checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1 `checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1 `checkh(( 8'h0 ** -8'sh0), 8'h1 ); // a**0 always 1 `checkh(( 8'h1 ** -8'sh0), 8'h1 ); // a**0 always 1 `checkh(( 8'h3 ** -8'sh0), 8'h1 ); // a**0 always 1 `checkh(( 8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1 `checkh((-8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1 `checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1 `checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1 `checkh(( 8'h0 ** -8'sh0), 8'h1 ); // a**0 always 1 `checkh(( 8'h1 ** -8'sh0), 8'h1 ); // a**0 always 1 `checkh(( 8'h3 ** -8'sh0), 8'h1 ); // a**0 always 1 `checkh(( 8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1 `checkh((-8'sh3 ** -8'sh3), 8'h0 ); // 0 (a<-1) // NCVERILOG bug `checkh((-8'sh1 ** -8'sh2), 8'h1 ); // -1^odd=-1, -1^even=1 `checkh((-8'sh1 ** -8'sh3), 8'hff); // -1^odd=-1, -1^even=1 // `checkh(( 8'h0 ** -8'sh3), 8'hx ); // x // NCVERILOG bug `checkh(( 8'h1 ** -8'sh3), 8'h1 ); // 1**b always 1 `checkh(( 8'h3 ** -8'sh3), 8'h0 ); // 0 // NCVERILOG bug `checkh(( 8'sh3 ** -8'sh3), 8'h0 ); // 0 // NCVERILOG bug if (fail) $stop; else $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_param_x_unique.v0000644000542200017500000000056415101701376022622 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module sub #(parameter P = 1'bx); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule module t; sub sub(); endmodule verilator-5.042/test_regress/t/t_tri_pull_unsup.out0000644000542200017500000000345115101701376023231 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_tri_pull_unsup.v:15:11: Unsupported: pullup strength 15 | pullup (supply1) pu1(a); | ^~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_tri_pull_unsup.v:16:11: Unsupported: pullup strength 16 | pullup (strong1) pu2(a); | ^~~~~~~ %Error-UNSUPPORTED: t/t_tri_pull_unsup.v:17:11: Unsupported: pullup strength 17 | pullup (pull1) pu3(a); | ^~~~~ %Error-UNSUPPORTED: t/t_tri_pull_unsup.v:18:11: Unsupported: pullup strength 18 | pullup (weak1) pu4(a); | ^~~~~ %Error-UNSUPPORTED: t/t_tri_pull_unsup.v:19:11: Unsupported: pullup strength 19 | pullup (supply1, supply0) pu5(a); | ^~~~~~~ %Error-UNSUPPORTED: t/t_tri_pull_unsup.v:20:11: Unsupported: pullup strength 20 | pullup (strong0, strong1) pu6(a); | ^~~~~~~ %Error-UNSUPPORTED: t/t_tri_pull_unsup.v:29:13: Unsupported: pulldown strength 29 | pulldown (supply0) pd1(a); | ^~~~~~~ %Error-UNSUPPORTED: t/t_tri_pull_unsup.v:30:13: Unsupported: pulldown strength 30 | pulldown (strong0) pd2(a); | ^~~~~~~ %Error-UNSUPPORTED: t/t_tri_pull_unsup.v:31:13: Unsupported: pulldown strength 31 | pulldown (pull0) pd3(a); | ^~~~~ %Error-UNSUPPORTED: t/t_tri_pull_unsup.v:32:13: Unsupported: pulldown strength 32 | pulldown (weak0) pd4(a); | ^~~~~ %Error-UNSUPPORTED: t/t_tri_pull_unsup.v:33:13: Unsupported: pulldown strength 33 | pulldown (supply0, supply1) pd5(a); | ^~~~~~~ %Error-UNSUPPORTED: t/t_tri_pull_unsup.v:34:13: Unsupported: pulldown strength 34 | pulldown (strong1, strong0) pd6(a); | ^~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_forceable_net_vlt.py0000755000542200017500000000130515101701376023442 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.pli_filename = "t/t_forceable_net.cpp" test.top_filename = "t/t_forceable_net.v" test.compile(make_top_shell=False, make_main=False, verilator_flags2=['--exe', test.pli_filename, test.t_dir + "/t_forceable_net.vlt"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_wrapper_del_context_bad.cpp0000644000542200017500000000125115101701376024772 0ustar mahmoudyfreeshell// // DESCRIPTION: Verilator: Verilog Multiple Model Test Module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include VM_PREFIX_INCLUDE int main(int argc, char** argv) { // Create contexts VerilatedContext* contextp{new VerilatedContext}; // Ideally we'd do this, but then address sanitizer blows up // delete contextp; // Test mistake - deleting contextp contextp->selfTestClearMagic(); // instantiate verilated design std::unique_ptr topp{new VM_PREFIX{contextp, "TOP"}}; return 0; } verilator-5.042/test_regress/t/t_select_lhs_oob2.v0000644000542200017500000000732015101701376022650 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [63:0] out; // From test of Test.v // End of automatics wire reset_l = ~(cyc<15); wire [63:0] d = crc[63:0]; wire [8:0] t_wa = crc[8:0]; wire [8:0] t_addr = {crc[18:17],3'b0,crc[13:10]}; Test test (/*AUTOINST*/ // Outputs .out (out[63:0]), // Inputs .clk (clk), .reset_l (reset_l), .t_wa (t_wa[8:0]), .d (d[63:0]), .t_addr (t_addr[8:0])); // Aggregate outputs into a single result vector wire [63:0] result = {out}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h421a41d1541ea652 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs out, // Inputs clk, reset_l, t_wa, d, t_addr ); input clk; input reset_l; reg [63:0] m_w0 [47:0]; reg [63:0] m_w1 [23:0]; reg [63:0] m_w2 [23:0]; reg [63:0] m_w3 [23:0]; reg [63:0] m_w4 [23:0]; reg [63:0] m_w5 [23:0]; input [8:0] t_wa; input [63:0] d; always @ (posedge clk) begin if (~reset_l) begin : blk integer i; for (i=0; i<48; i=i+1) begin m_w0[i] <= 64'h0; end for (i=0; i<24; i=i+1) begin m_w1[i] <= 64'h0; m_w2[i] <= 64'h0; m_w3[i] <= 64'h0; m_w4[i] <= 64'h0; m_w5[i] <= 64'h0; end end else begin casez (t_wa[8:6]) 3'd0: m_w0[t_wa[5:0]] <= d; 3'd1: m_w1[t_wa[4:0]] <= d; 3'd2: m_w2[t_wa[4:0]] <= d; 3'd3: m_w3[t_wa[4:0]] <= d; 3'd4: m_w4[t_wa[4:0]] <= d; default: m_w5[t_wa[4:0]] <= d; endcase end end input [8:0] t_addr; wire [63:0] t_w0 = m_w0[t_addr[5:0]]; wire [63:0] t_w1 = m_w1[t_addr[4:0]]; wire [63:0] t_w2 = m_w2[t_addr[4:0]]; wire [63:0] t_w3 = m_w3[t_addr[4:0]]; wire [63:0] t_w4 = m_w4[t_addr[4:0]]; wire [63:0] t_w5 = m_w5[t_addr[4:0]]; output reg [63:0] out; always @* begin casez (t_addr[8:6]) 3'd0: out = t_w0; 3'd1: out = t_w1; 3'd2: out = t_w2; 3'd3: out = t_w3; 3'd4: out = t_w4; default: out = t_w5; endcase end endmodule verilator-5.042/test_regress/t/t_class_vparam.v0000644000542200017500000000170015101701376022251 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias' // // Simple bi-directional alias test. // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef class paramed_class_t; typedef class arg_class_t; typedef paramed_class_t#(logic[3:0], 1) paramed_class_logic4_t; virtual class vclass #(type CTYPE_t = arg_class_t, int I = 0); pure virtual function void funcname(paramed_class_t #(CTYPE_t) v); endclass class paramed_class_t #(type TYPE, int I = 0); TYPE memb; endclass class arg_class_t; int ifield; endclass module t; vclass vir; paramed_class_t#(arg_class_t) argu; initial begin argu = new; argu.memb = new; argu.memb.ifield = 1234; // vir.funcname(argu); if (argu.memb.ifield != 1234) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_vpi_escape.cpp0000644000542200017500000002700315101701376022235 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2010-2023 by Wilson Snyder and Marlon James. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #ifdef IS_VPI #include "sv_vpi_user.h" #else #include "verilated.h" #include "verilated_vcd_c.h" #include "verilated_vpi.h" #include "Vt_vpi_escape.h" #include "Vt_vpi_escape__Dpi.h" #include "svdpi.h" #endif #include extern "C" { #include } // These require the above. Comment prevents clang-format moving them #include "TestCheck.h" #include "TestSimulator.h" #include "TestVpi.h" int errors = 0; unsigned int main_time = 0; //====================================================================== // We cannot replace those with VL_STRINGIFY, not available when PLI is build #define STRINGIFY(x) STRINGIFY2(x) #define STRINGIFY2(x) #x const char* _sim_top() { if (TestSimulator::is_verilator() || TestSimulator::is_icarus()) { return "\\t.has.dots "; } else { return "top.\\t.has.dots "; } } const char* _my_rooted(const char* obj) { static std::string buf; std::ostringstream os; os << _sim_top(); if (*obj) os << "." << obj; buf = os.str(); return buf.c_str(); } TestVpiHandle my_vpi_handle(const char* signal) { #ifdef TEST_VERBOSE printf("-my_vpi_handle(\"%s\")\n", _my_rooted(signal)); #endif TestVpiHandle vh = vpi_handle_by_name(const_cast(_my_rooted(signal)), NULL); return vh; } int _mon_check_var() { #ifdef TEST_VERBOSE printf("-mon_check_var()\n"); #endif TestVpiHandle vh1 = vpi_handle_by_name(const_cast(_sim_top()), NULL); TEST_CHECK_NZ(vh1); TestVpiHandle vh2 = my_vpi_handle("\\check;alias "); TEST_CHECK_NZ(vh2); // scope attributes const char* p; p = vpi_get_str(vpiName, vh1); TEST_CHECK_CSTR(p, "\\t.has.dots "); p = vpi_get_str(vpiFullName, vh1); TEST_CHECK_CSTR(p, _sim_top()); p = vpi_get_str(vpiType, vh1); TEST_CHECK_CSTR(p, "vpiModule"); TestVpiHandle vh3 = vpi_handle_by_name(const_cast("escaped_normal"), vh1); TEST_CHECK_NZ(vh3); // onebit attributes PLI_INT32 d; d = vpi_get(vpiType, vh3); if (TestSimulator::is_verilator()) { TEST_CHECK_EQ(d, vpiReg); } else { TEST_CHECK_EQ(d, vpiNet); } if (TestSimulator::has_get_scalar()) { d = vpi_get(vpiVector, vh3); TEST_CHECK_EQ(d, 0); } p = vpi_get_str(vpiName, vh3); TEST_CHECK_CSTR(p, "escaped_normal"); p = vpi_get_str(vpiFullName, vh3); // Toplevel port returns TOP.xxxxx TEST_CHECK_CSTR(p, "TOP.escaped_normal"); p = vpi_get_str(vpiType, vh3); if (TestSimulator::is_verilator()) { TEST_CHECK_CSTR(p, "vpiReg"); } else { TEST_CHECK_CSTR(p, "vpiNet"); } TestVpiHandle vh4 = my_vpi_handle("\\x.y "); TEST_CHECK_NZ(vh4); // Test that the toplevel TOP.xxxxx search is skipped // when the path to the scope has more than one level. { TestVpiHandle vh5 = my_vpi_handle("\\mod.with_dot .\\b.c "); TEST_CHECK_NZ(vh5); p = vpi_get_str(vpiFullName, vh5); TEST_CHECK_CSTR(p, "\\t.has.dots .\\mod.with_dot .\\b.c "); } { TestVpiHandle vh5 = my_vpi_handle("double__underscore"); TEST_CHECK_NZ(vh5); p = vpi_get_str(vpiFullName, vh5); TEST_CHECK_CSTR(p, "TOP.double__underscore"); } { TestVpiHandle vh5 = my_vpi_handle("double__underscore__vlt"); TEST_CHECK_NZ(vh5); p = vpi_get_str(vpiFullName, vh5); TEST_CHECK_CSTR(p, "TOP.double__underscore__vlt"); } return errors; } int _mon_check_iter() { #ifdef TEST_VERBOSE printf("-mon_check_iter()\n"); #endif const char* p; TestVpiHandle vh2 = my_vpi_handle("\\mod.with_dot "); TEST_CHECK_NZ(vh2); p = vpi_get_str(vpiName, vh2); TEST_CHECK_CSTR(p, "\\mod.with_dot "); if (TestSimulator::is_verilator()) { p = vpi_get_str(vpiDefName, vh2); TEST_CHECK_CSTR( p, "sub_with_very___05Fvery_____VhshsmH6BYHIAHq4mnPF8T3lXnhhONMT1I4ouBvkJk58"); } TestVpiHandle vh_null_name = my_vpi_handle("___0_"); TEST_CHECK_NZ(vh_null_name); p = vpi_get_str(vpiName, vh_null_name); TEST_CHECK_CSTR(p, "___0_"); TestVpiHandle vh_hex_name = my_vpi_handle("___0F_"); TEST_CHECK_NZ(vh_hex_name); p = vpi_get_str(vpiName, vh_hex_name); TEST_CHECK_CSTR(p, "___0F_"); TestVpiHandle vh10 = vpi_iterate(vpiReg, vh2); TEST_CHECK_NZ(vh10); TEST_CHECK_EQ(vpi_get(vpiType, vh10), vpiIterator); { TestVpiHandle vh11 = vpi_scan(vh10); TEST_CHECK_NZ(vh11); p = vpi_get_str(vpiFullName, vh11); #ifdef TEST_VERBOSE printf(" scanned %s\n", p); #endif TEST_CHECK_CSTR(p, _my_rooted("\\mod.with_dot .\\b.c ")); } { TestVpiHandle vh12 = vpi_scan(vh10); TEST_CHECK_NZ(vh12); p = vpi_get_str(vpiFullName, vh12); #ifdef TEST_VERBOSE printf(" scanned %s\n", p); #endif TEST_CHECK_CSTR(p, _my_rooted("\\mod.with_dot .cyc")); } { TestVpiHandle vh13 = vpi_scan(vh10); TEST_CHECK_NZ(vh13); p = vpi_get_str(vpiFullName, vh13); #ifdef TEST_VERBOSE printf(" scanned %s\n", p); #endif TEST_CHECK_CSTR(p, _my_rooted("\\mod.with_dot .subsig1")); } { TestVpiHandle vh14 = vpi_scan(vh10); TEST_CHECK_NZ(vh14); p = vpi_get_str(vpiFullName, vh14); #ifdef TEST_VERBOSE printf(" scanned %s\n", p); #endif TEST_CHECK_CSTR(p, _my_rooted("\\mod.with_dot .subsig2")); } { TestVpiHandle vh15 = vpi_scan(vh10); vh10.freed(); // IEEE 37.2.2 vpi_scan at end does a vpi_release_handle TEST_CHECK_EQ(vh15, 0); } return errors; } int _mon_check_ports() { #ifdef TEST_VERBOSE printf("-mon_check_ports()\n"); #endif // test writing to input port TestVpiHandle vh1 = my_vpi_handle("a"); TEST_CHECK_NZ(vh1); PLI_INT32 d; d = vpi_get(vpiType, vh1); if (TestSimulator::is_verilator()) { TEST_CHECK_EQ(d, vpiReg); } else { TEST_CHECK_EQ(d, vpiNet); } const char* portFullName; if (TestSimulator::is_verilator()) { portFullName = "TOP.a"; } else { portFullName = "t.a"; } const char* name = vpi_get_str(vpiFullName, vh1); TEST_CHECK_EQ(strcmp(name, portFullName), 0); std::string handleName1 = name; s_vpi_value v; v.format = vpiIntVal; vpi_get_value(vh1, &v); TEST_CHECK_EQ(v.value.integer, 0); s_vpi_time t; t.type = vpiSimTime; t.high = 0; t.low = 0; v.value.integer = 2; vpi_put_value(vh1, &v, &t, vpiNoDelay); v.value.integer = 100; vpi_get_value(vh1, &v); TEST_CHECK_EQ(v.value.integer, 2); // get handle of toplevel module TestVpiHandle vht = my_vpi_handle(""); TEST_CHECK_NZ(vht); d = vpi_get(vpiType, vht); TEST_CHECK_EQ(d, vpiModule); TestVpiHandle vhi = vpi_iterate(vpiReg, vht); TEST_CHECK_NZ(vhi); TestVpiHandle vh11; std::string handleName2; while ((vh11 = vpi_scan(vhi))) { const char* fn = vpi_get_str(vpiFullName, vh11); #ifdef TEST_VERBOSE printf(" scanned %s\n", fn); #endif if (0 == strcmp(fn, portFullName)) { handleName2 = fn; break; } } TEST_CHECK_NZ(vh11); // If get zero we never found the variable vhi.release(); TEST_CHECK_EQ(vpi_get(vpiType, vh11), vpiReg); TEST_CHECK_EQ(handleName1, handleName2); TestVpiHandle vh2 = my_vpi_handle("\\b.c "); TEST_CHECK_NZ(vh2); if (TestSimulator::is_verilator()) { portFullName = "TOP.\\b.c "; } else { portFullName = "t.\\b.c "; } name = vpi_get_str(vpiFullName, vh2); TEST_CHECK_EQ(strcmp(name, portFullName), 0); handleName1 = name; v.format = vpiIntVal; vpi_get_value(vh2, &v); TEST_CHECK_EQ(v.value.integer, 0); t.type = vpiSimTime; t.high = 0; t.low = 0; v.value.integer = 1; vpi_put_value(vh2, &v, &t, vpiNoDelay); v.value.integer = 0; vpi_get_value(vh2, &v); TEST_CHECK_EQ(v.value.integer, 1); vhi = vpi_iterate(vpiReg, vht); TEST_CHECK_NZ(vhi); while ((vh11 = vpi_scan(vhi))) { const char* fn = vpi_get_str(vpiFullName, vh11); #ifdef TEST_VERBOSE printf(" scanned %s\n", fn); #endif if (0 == strcmp(fn, portFullName)) { handleName2 = fn; break; } } TEST_CHECK_NZ(vh11); // If get zero we never found the variable vhi.release(); TEST_CHECK_EQ(vpi_get(vpiType, vh11), vpiReg); TEST_CHECK_EQ(handleName1, handleName2); return errors; } extern "C" int mon_check() { // Callback from initial block in monitor #ifdef TEST_VERBOSE printf("-mon_check()\n"); #endif if (int status = _mon_check_var()) return status; if (int status = _mon_check_iter()) return status; if (int status = _mon_check_ports()) return status; #ifndef IS_VPI VerilatedVpi::selfTest(); #endif return 0; // Ok } //====================================================================== #ifdef IS_VPI static int mon_check_vpi() { TestVpiHandle href = vpi_handle(vpiSysTfCall, 0); s_vpi_value vpi_value; vpi_value.format = vpiIntVal; vpi_value.value.integer = mon_check(); vpi_put_value(href, &vpi_value, NULL, vpiNoDelay); return 0; } static s_vpi_systf_data vpi_systf_data[] = {{vpiSysFunc, vpiIntFunc, (PLI_BYTE8*)"$mon_check", (PLI_INT32(*)(PLI_BYTE8*))mon_check_vpi, 0, 0, 0}, 0}; // cver entry void vpi_compat_bootstrap(void) { p_vpi_systf_data systf_data_p; systf_data_p = &(vpi_systf_data[0]); while (systf_data_p->type != 0) vpi_register_systf(systf_data_p++); } // icarus entry void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0}; #else double sc_time_stamp() { return main_time; } int main(int argc, char** argv) { const std::unique_ptr contextp{new VerilatedContext}; uint64_t sim_time = 1100; contextp->debug(0); contextp->commandArgs(argc, argv); const std::unique_ptr topp{new VM_PREFIX{contextp.get(), // Note null name - we're flattening it out ""}}; #ifdef VERILATOR #ifdef TEST_VERBOSE contextp->scopesDump(); #endif #endif #if VM_TRACE contextp->traceEverOn(true); VL_PRINTF("Enabling waves...\n"); VerilatedVcdC* tfp = new VerilatedVcdC; topp->trace(tfp, 99); tfp->open(STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); #endif topp->a = 0; topp->clk = 0; topp->b__02ec = 0; topp->eval(); main_time += 10; while (vl_time_stamp64() < sim_time && !contextp->gotFinish()) { main_time += 1; topp->eval(); VerilatedVpi::callValueCbs(); topp->clk = !topp->clk; // mon_do(); #if VM_TRACE if (tfp) tfp->dump(main_time); #endif } if (!contextp->gotFinish()) { vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); } topp->final(); #if VM_TRACE if (tfp) tfp->close(); #endif return 0; } #endif verilator-5.042/test_regress/t/t_tri_gate_cond_pins_inout.py0000755000542200017500000000140615101701376025037 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_tri_gate.cpp" test.top_filename = "t/t_tri_gate.v" test.compile(make_top_shell=False, make_main=False, v_flags2=['+define+T_COND'], make_flags=['CPPFLAGS_ADD=-DT_COND'], verilator_flags2=["--exe --pins-inout-enables", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_mod_automatic.v0000644000542200017500000000204615101701376022427 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module automatic t; task static accum_s(input integer value, output integer result); static int acc = 1; acc = acc + value; result = acc; endtask task accum_a(input integer value, output integer result); int acc = 1; // automatic acc = acc + value; result = acc; endtask integer value; reg failed = 0; // Static initial begin accum_s(2, value); $display("%d", value); if (value !== 3) failed = 1; accum_s(3, value); $display("%d", value); if (value !== 6) failed = 1; accum_a(2, value); $display("%d", value); if (value !== 3) failed = 1; accum_a(3, value); $display("%d", value); if (value !== 4) failed = 1; if (failed) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_gate_primitives_implicit_net.v0000755000542200017500000000764115101701376025546 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); // verilog_format: on module t( input clk ); int cyc=1; // Instantiate the primitive gates to be tested. and g_and(o_and, i_and1, i_and2, i_and3), g2_and(o2_and, i_and1, i_and2, i_and3); not g_not(o_not1, o_not2, i_not1), g2_not(o2_not1, o_not2, i_not1); nor g_nor(o_nor, i_nor1, i_nor2, i_nor3), g2_nor(o2_nor, i_nor1, i_nor2, i_nor3); or g_or(o_or, i_or1, i_or2, i_or3), g2_or(o2_or, i_or1, i_or2, i_or3); nand g_nand(o_nand, i_nand1, i_nand2, i_nand3), g2_nand(o2_nand, i_nand1, i_nand2, i_nand3); xor g_xor(o_xor, i_xor1, i_xor2, i_xor3), g2_xor(o2_xor, i_xor1, i_xor2, i_xor3); xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3), g2_xor(o2_xnor, i_xnor1, i_xnor2, i_xnor3); buf g_buf(o_buf1, o_buf2, i_buf1), g2_buf(o2_buf1, o_buf2, i_buf1); bufif0 g_bufif0(o_bufif0, i_bufif01, i_bufif02), g2_bufif0(o2_bufif0, i_bufif01, i_bufif02); bufif1 g_bufif1(o_bufif1, i_bufif11, i_bufif12), g2_bufif1(o2_bufif1, i_bufif11, i_bufif12); notif0 g_notif0(o_notif0, i_notif01, i_notif02), g2_notif0(o2_notif0, i_notif01, i_notif02); notif1 g_notif1(o_notif1, i_notif11, i_notif12), g2_notif1(o2_notif1, i_notif11, i_notif12); // Generate random data for inputs reg rd_data1, rd_data2, rd_data3; always @(posedge clk) begin rd_data1 = 1'($random); rd_data2 = 1'($random); rd_data3 = 1'($random); end // Assign the input of primitive gates. `default_nettype none assign i_and1 = rd_data1; assign i_and2 = rd_data2; assign i_and3 = rd_data3; assign i_not1 = rd_data1; assign i_nor1 = rd_data1; assign i_nor2 = rd_data2; assign i_nor3 = rd_data3; assign i_or1 = rd_data1; assign i_or2 = rd_data2; assign i_or3 = rd_data3; assign i_nand1 = rd_data1; assign i_nand2 = rd_data2; assign i_nand3 = rd_data3; assign i_xor1 = rd_data1; assign i_xor2 = rd_data2; assign i_xor3 = rd_data3; assign i_xnor1 = rd_data1; assign i_xnor2 = rd_data2; assign i_xnor3 = rd_data3; assign i_buf1 = rd_data1; assign i_bufif01 = rd_data1; assign i_bufif02 = rd_data2; assign i_bufif11 = rd_data1; assign i_bufif12 = rd_data2; assign i_notif01 = rd_data1; assign i_notif02 = rd_data2; assign i_notif11 = rd_data1; assign i_notif12 = rd_data2; // Check the outputs of the gate instances always @(negedge clk) begin if (o_and !== (i_and1 & i_and2 & i_and3)) $stop; if ((o_not1 !== ~i_not1) || (o_not2 != ~i_not1)) $stop; if (o_nor !== !(i_nor1 | i_nor2 | i_nor3)) $stop; if (o_or !== (i_or1 | i_or2 | i_or3)) $stop; if (o_nand !== !(i_nand1 & i_nand2 & i_nand3)) $stop; if (o_xor !== (i_xor1 ^ i_xor2 ^ i_xor3)) $stop; if (o_xnor !== !(i_xnor1 ^ i_xnor2 ^ i_xnor3)) $stop; if ((o_buf1 !== i_buf1) || (o_buf2 !== i_buf1)) $stop; if (!(o_bufif0 == (i_bufif01 & !i_bufif02))) $stop; if (!(o_bufif1 == (i_bufif11 & i_bufif12))) $stop; if (!(o_notif0 == (!i_notif01 & !i_notif02))) $stop; if (!(o_notif1 == (!i_notif11 & i_notif12))) $stop; `checkh(o2_and, o2_and); `checkh(o2_not1, o2_not1); `checkh(o2_nor, o2_nor); `checkh(o2_or, o2_or); `checkh(o2_nand, o2_nand); `checkh(o2_xor, o2_xor); `checkh(o2_xnor, o2_xnor); `checkh(o2_buf1, o2_buf1); `checkh(o2_bufif0, o2_bufif0); `checkh(o2_bufif1, o2_bufif1); `checkh(o2_notif0, o2_notif0); `checkh(o2_notif1, o2_notif1); end always @(posedge clk) begin cyc = cyc + 1; if (cyc == 100) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_display_time.out0000644000542200017500000000145715101701376022634 0ustar mahmoudyfreeshelldefault: [10] 0t time [ 10] No0 time p= 10 0p='ha -9,0,,0: [10] 0t time [10] No0 time p= 10 0p='ha -9,0,,10: [10] 0t time [ 10] No0 time p= 10 0p='ha -9,0,ns,5: [10ns] 0t time [ 10ns] No0 time p= 10 0p='ha -9,3,ns,8: [10.000ns] 0t time [10.000ns] No0 time p= 10 0p='ha -9,3,ns : [10.000ns] 0t time [10.000ns] No0 time p= 10 0p='ha -9,3: [10.000ns] 0t time [10.000ns] No0 time p= 10 0p='ha -9: [10.000ns] 0t time [10.000ns] No0 time p= 10 0p='ha : [10.000ns] 0t time [10.000ns] No0 time p= 10 0p='ha -9,,,: [10.000ns] 0t time [10.000ns] No0 time p= 10 0p='ha *-* All Finished *-* verilator-5.042/test_regress/t/t_property_untyped.v0000644000542200017500000000151315101701376023234 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ clk ); input clk; int cyc = 0; logic [4:0] val = 0; always @(posedge clk) begin cyc <= cyc + 1; val = ~val; end property check(cyc_mod_2, untyped expected); @(posedge clk) cyc % 2 == cyc_mod_2 |=> val == expected; endproperty assert property(check(0, 5'b11111)) else begin // Assertion should pass $display("[%0t] Assert failed, but shouldn't", $time); $stop; end always @(posedge clk) begin if (cyc == 10) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_preproc_inc_notfound_bad.out0000644000542200017500000000145515101701376025174 0ustar mahmoudyfreeshell%Error: t/t_preproc_inc_notfound_bad.v:7:10: Cannot find include file: 'this_file_is_not_found.vh' 7 | `include "this_file_is_not_found.vh" | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. ... Looked in: t/this_file_is_not_found.vh t/this_file_is_not_found.vh.v t/this_file_is_not_found.vh.sv this_file_is_not_found.vh this_file_is_not_found.vh.v this_file_is_not_found.vh.sv obj_vlt/t_preproc_inc_notfound_bad/this_file_is_not_found.vh obj_vlt/t_preproc_inc_notfound_bad/this_file_is_not_found.vh.v obj_vlt/t_preproc_inc_notfound_bad/this_file_is_not_found.vh.sv %Error: Exiting due to verilator-5.042/test_regress/t/t_var_top_struct.v0000644000542200017500000000120715101701376022656 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef struct { logic bist; logic [38:0] web; logic ceb; } mem_t; module sub (input bist_0, input bist_1, input bist_2, output y ); assign y = bist_0 | bist_1 | bist_2; endmodule module t (input mem_t i_ram_mbist [7:0], output y ); sub sub (.y, .bist_0(i_ram_mbist[0].bist), .bist_1(i_ram_mbist[1].bist), .bist_2(i_ram_mbist[2].bist) ); endmodule verilator-5.042/test_regress/t/t_var_xref_bad.out0000644000542200017500000000044315101701376022565 0ustar mahmoudyfreeshell%Error: t/t_var_xref_bad.v:11:12: Found definition of 'tsk' as a TASK but expected a scope/variable 11 | initial tsk.bad_missing_ref = 0; | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_scheduling_5.py0000755000542200017500000000100115101701376022327 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["-Wno-MULTIDRIVEN"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_notiming.py0000755000542200017500000000103315101701376021607 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.lint(verilator_flags2=["--no-timing"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_packed.v0000644000542200017500000000146115101701376022216 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; //TODO sub #(.WIDTH(1)) w1(); //TODO sub #(.WIDTH(2)) w2(); //TODO sub #(.WIDTH(3)) w3(); //TODO sub #(.WIDTH(4)) w4(); sub #(.WIDTH(5)) w5(); always @ (posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule module sub (); parameter WIDTH=5; // WIDTH >= 5 fails. WIDTH <= 4 passes typedef struct packed { logic [WIDTH-1:0] data; } [15:0] w_t; class WrReqQ; w_t w; endclass initial begin if ($bits(w_t) != WIDTH * 16) $stop; end endmodule verilator-5.042/test_regress/t/t_flag_f_bad.out0000644000542200017500000000027015101701376022165 0ustar mahmoudyfreeshell%Error: Cannot open -f command file: file_will_not_exist.vc ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_protect_ids.py0000755000542200017500000000263015101701376022306 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') # Use --debug-protect to assist debug # This test makes randomly named .cpp/.h files, which tend to collect, so remove them first for filename in (glob.glob(test.obj_dir + "/*_PS*.cpp") + glob.glob(test.obj_dir + "/*_PS*.h") + glob.glob(test.obj_dir + "/*.d")): test.unlink_ok(filename) test.compile(verilator_flags2=[ "--protect-ids", "--protect-key SECRET_KEY", "--trace-vcd", "--coverage", "-Wno-INSECURE", "t/t_protect_ids_c.cpp" ]) test.execute() # 'to="PS"' indicates means we probably mis-protected something already protected # Use --debug-protect to assist debugging these test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + "__idmap.xml", r'to="PS') if test.vlt_all: # Check for secret in any outputs for filename in test.glob_some(test.obj_dir + "/*.[ch]*"): if re.search(r'secret', filename, re.IGNORECASE): test.error("Secret found in a filename: " + filename) test.file_grep_not(filename, r'secret') test.passes() verilator-5.042/test_regress/t/t_sys_psprintf_warn_bad.py0000755000542200017500000000103415101701376024364 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_sys_psprintf.v" test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface_virtual_missing_bad.out0000644000542200017500000000041615101701376026210 0ustar mahmoudyfreeshell%Error: t/t_interface_virtual_missing_bad.v:9:12: Cannot find file containing interface: 'foo' 9 | virtual foo vif; | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_interconnect_bad.out0000644000542200017500000000036615101701376023450 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_interconnect_bad.v:9:4: Unsupported: interconnect 9 | interconnect a; | ^~~~~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_gate_inline_wide_noexclude_sel.v0000644000542200017500000000202715101701376026000 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t ( output reg [1020:0] res1, output reg [1020:0] res2, output reg [1022:0] res3, output reg [1022:0] res4 ); always_inline always_inline(res1, res2); dont_inline dont_inline(res3, res4); endmodule module always_inline( output reg [1020:0] res1, output reg [1020:0] res2 ); wire [1023:0] a; wire [478:0] b; assign b = a[510:32]; assign res1 = {542'b0, b}; assign res2 = {542'b1, b}; endmodule // SEL does not have proper offset so we do not have guarantee that it will be // emitted as '[' operator, thus we do not exclude it from inlining. module dont_inline( output reg [1022:0] res1, output reg [1022:0] res2 ); wire [1023:0] a; wire [480:0] b; // LSB % 32 != 0 assign b = a[510:30]; assign res1 = {542'b0, b}; assign res2 = {542'b1, b}; endmodule verilator-5.042/test_regress/t/t_enum_type_pins.py0000755000542200017500000000073415101701376023030 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_generic_bad4.out0000644000542200017500000000055115101701376024471 0ustar mahmoudyfreeshell%Error: t/t_interface_generic_bad4.v:26:32: Generic interfaces can only connect to an interface and 'inf_inst' is of type 'int' 26 | GenericModule genericModule (inf_inst, inf_inst2); | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_gen_defparam_multi.v0000644000542200017500000000236015101701376023423 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; parameter PAR = 3; defparam PAR = 5; wire [31:0] o2a, o2b, o3a, o3b; m1 #(0) m1a(.o2(o2a), .o3(o3a)); m1 #(1) m1b(.o2(o2b), .o3(o3b)); always @ (posedge clk) begin if (PAR != 5) $stop; if (o2a != 8) $stop; if (o2b != 4) $stop; if (o3a != 80) $stop; if (o3b != 40) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module m1 (output wire [31:0] o2, output wire [31:0] o3); parameter W = 0; generate if (W == 0) begin m2 m2 (.*); defparam m2.PAR2 = 8; defparam m2.m3.PAR3 = 80; end else begin m2 m2 (.*); defparam m2.PAR2 = 4; defparam m2.m3.PAR3 = 40; end endgenerate endmodule module m2 (output wire [31:0] o2, output wire [31:0] o3); parameter PAR2 = 20; assign o2 = PAR2; m3 m3 (.*); endmodule module m3 (output wire [31:0] o3); parameter PAR3 = 40; assign o3 = PAR3; endmodule verilator-5.042/test_regress/t/t_interface_gen4_noinl.py0000755000542200017500000000103715101701376024043 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_gen4.v" test.compile(v_flags2=["-fno-inline"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_process_fork.py0000755000542200017500000000103515101701376022464 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_std_identifier_bad.out0000644000542200017500000000066715101701376023755 0ustar mahmoudyfreeshell%Error: t/t_std_identifier.v:16:20: Package/class for ':: reference' not found: 'std' 16 | int baz = foo::std::bar; | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_std_identifier.v:16:25: Can't find definition of scope/variable/func: 'bar' 16 | int baz = foo::std::bar; | ^~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_enum_type_methods.v0000644000542200017500000000546115101701376023336 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t (/*AUTOARG*/ // Inputs clk ); input clk; typedef enum [3:0] { E01 = 1, E03 = 3, E04 = 4 } my_t; integer cyc = 0; my_t e; int arrayfits [e.num]; // Check can use as constant string all; // Check constification initial begin e = E03; `checkh(e.first, E01); `checkh(e.last, E04); `checkh(e.last(), E04); `checkh(e.next, E04); `checkh(e.next(), E04); `checkh(e.next(1), E04); `checkh(e.next(1).next(1), E01); `checkh(e.next(2), E01); `checkh(e.next(1).next(1).next(1), E03); `checkh(e.next(1).next(2), E03); `checkh(e.next(THREE), E03); `checkh(e.prev, E01); `checkh(e.prev(1), E01); `checkh(e.prev(1).prev(1), E04); `checkh(e.prev(2), E04); `checkh(e.num, 3); `checks(e.name, "E03"); // all = ""; for (my_t e = e.first; e != e.last; e = e.next) begin all = {all, e.name}; end e = e.last; all = {all, e.name}; `checks(all, "E01E03E04"); end localparam THREE = 3; // Check runtime always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==0) begin // Setup e <= E01; end else if (cyc==1) begin `checks(e.name, "E01"); `checkh(e.next, E03); `checkh(e.next(1), E03); `checkh(e.next(2), E04); `checkh(e.prev, E04); `checkh(e.prev(1), E04); `checkh(e.prev(2), E03); e <= E03; end else if (cyc==2) begin `checks(e.name, "E03"); `checkh(e.next, E04); `checkh(e.next(1), E04); `checkh(e.next(2), E01); `checkh(e.prev, E01); `checkh(e.prev(1), E01); `checkh(e.prev(2), E04); e <= E04; end else if (cyc==3) begin `checks(e.name, "E04"); `checkh(e.next, E01); `checkh(e.next(1), E01); `checkh(e.next(2), E03); `checkh(e.prev, E03); `checkh(e.prev(1), E03); `checkh(e.prev(2), E01); e <= E01; end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_interface_virtual_unsup.py0000755000542200017500000000105515101701376024727 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) if not test.vlt_all: test.execute() test.passes() verilator-5.042/test_regress/t/t_select_index2.py0000755000542200017500000000070615101701376022521 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.042/test_regress/t/t_mem_slice.v0000644000542200017500000000614615101701376021544 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; logic use_AnB; logic [1:0] active_command [8:0]; logic [1:0] command_A [8:0]; logic [1:0] command_B [8:0]; logic [1:0] active_command2 [8:0]; logic [1:0] command_A2 [8:0]; logic [1:0] command_B2 [8:0]; logic [1:0] active_command3 [1:0][2:0][3:0]; logic [1:0] command_A3 [1:0][2:0][3:0]; logic [1:0] command_B3 [1:0][2:0][3:0]; logic [2:0] use_A4nB4; logic [8:0][1:0] active_command4; logic [8:0][1:0] command_A4; logic [8:0][1:0] command_B4; logic [8:0] pipe1 [7:0]; logic [8:0] pipe1_input; integer cyc; assign active_command[8:0] = (use_AnB) ? command_A[8:0] : command_B[8:0]; assign active_command2 = (use_AnB) ? command_A2 : command_B2; // Illegal to have [1:0][x:y] here - IEEE only allows single dimension slicing assign active_command3[1:0] = (use_AnB) ? command_A3[1:0] : command_B3[1:0]; // Check we can cope with things other than packed arrays assign active_command4 = (use_A4nB4[0]) ? command_A4 : command_B4; always @ (posedge clk) begin pipe1_input <= pipe1_input + 1; pipe1[0] <= pipe1_input; pipe1[7:1] <= pipe1[6:0]; end logic [3:0][13:0] iq_read_data [15:0]; logic [3:0][13:0] iq_data; logic [3:0] sel; assign iq_data = iq_read_data[sel]; always @ (posedge clk) begin sel = sel + 1; end initial begin cyc = 0; use_AnB = 0; for (int i = 0; i < 7; ++i) begin command_A[i] = 2'b00; command_B[i] = 2'b11; command_A2[i] = 2'b00; command_B2[i] = 2'b11; pipe1_input = 9'b0; end for (int i = 0; i < 2; ++i) begin for (int j = 0; j < 3; ++j) begin for (int k = 0; k < 4; ++k) begin command_A3[i][j][k] = 2'b00; command_B3[i][j][k] = 2'b11; end end end end always @ (posedge clk) begin use_AnB <= ~use_AnB; cyc <= cyc + 1; if (use_AnB) begin if (active_command[3] != 2'b00) begin $stop; end if (active_command2[3] != 2'b00) begin $stop; end if (active_command3[0][1][2] != 2'b00) begin $stop; end end if (!use_AnB) begin if (active_command[3] != 2'b11) begin $stop; end if (active_command2[3] != 2'b11) begin $stop; end end end logic [8:0] last_pipe; always @(posedge clk) begin if (cyc < 3) begin last_pipe <= pipe1[0]; end else begin if (last_pipe + 1 != pipe1[0]) begin $stop; end else begin last_pipe <= pipe1[0]; end end if (cyc > 10) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule : t verilator-5.042/test_regress/t/t_param_hier_bad.v0000644000542200017500000000255215101701376022521 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilog_format: off `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); // verilog_format: on package pkg; function int pkg_func(); return 1; endfunction endpackage module sub #( parameter int X = 1 ) (); localparam int Y = X; localparam int Z = X; function int sub_func(); return 1; endfunction endmodule module t; localparam int MY_X = 2; sub #(.X(MY_X)) u_sub (); localparam int SUB_Y = u_sub.Y; // <--- BAD: IEEE 1800-2023 6.20.2 no hierarchical localparam int SUB_FUNC = u_sub.sub_func(); // <--- BAD: IEEE 1800-2023 6.20.2 no hierarchical localparam int OK_FUNC = local_func(); // ok localparam int OK_PKG_FUNC = pkg::pkg_func(); // ok sub #(.X(block.block_func())) u_sub2 (); // <--- BAD begin : block function int block_func(); return 2; endfunction end function int local_func(); return 2; endfunction initial begin `checkd(SUB_Y, 1); `checkd(u_sub.X, 2); `checkd(u_sub.Y, 1); `checkd(u_sub.Z, 2); $finish; end endmodule verilator-5.042/test_regress/t/t_math_countbits2_bad.v0000644000542200017500000000122415101701376023512 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; logic my_vec [4]; logic bool; int count; initial begin my_vec = '{1, 0, 1, 0}; count = $countones(my_vec); // Bad, must be bit vector count = $countbits(my_vec, '0); // Bad, must be bit vector bool = $onehot(my_vec); // Bad, must be bit vector bool = $onehot0(my_vec); // Bad, must be bit vector bool = $isunknown(my_vec); // Bad, must be bit vector $stop; end endmodule verilator-5.042/test_regress/t/t_alw_split_rst.py0000755000542200017500000000117115101701376022654 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--stats", test.wno_unopthreads_for_few_cores]) if test.vlt_all: test.file_grep(test.stats, r'Optimizations, Split always\s+(\d+)', 12) test.execute() test.passes() verilator-5.042/test_regress/t/t_alias_tristate_unsup.v0000644000542200017500000000100215101701376024033 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ // Inputs clk ); input clk; wire [31:0] a, b; integer cyc = 0; assign a = 'z; alias a = b; always @(posedge clk) begin cyc <= cyc + 1; if (a !== 'z) $stop; if (b !== 'z) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_timing_sched_if.py0000755000542200017500000000077115101701376023106 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_vlt_syntax_bad.v0000644000542200017500000000035215101701376022621 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; endmodule verilator-5.042/test_regress/t/t_vpi_var3.v0000644000542200017500000000732015101701376021333 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2010 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef USE_VPI_NOT_DPI //We call it via $c so we can verify DPI isn't required - see bug572 `else import "DPI-C" context function int mon_check(); `endif module t (/*AUTOARG*/ // Outputs x, // Inputs clk, a ); `ifdef VERILATOR `systemc_header extern "C" int mon_check(); `verilog `endif input clk; input [7:0] a; output reg [7:0] x; reg onebit; reg [2:1] twoone; reg [2:1] fourthreetwoone[4:3]; reg LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND; // verilator lint_off ASCRANGE reg [0:61] quads[2:3]; // verilator lint_on ASCRANGE reg [31:0] count; reg [31:0] half_count; reg [31:0] delayed; reg [31:0] delayed_mem [16]; reg [7:0] text_byte; reg [15:0] text_half; reg [31:0] text_word; reg [63:0] text_long; reg [511:0] text; reg [2047:0] too_big; integer status; real real1; string str1; localparam int nullptr = 123; logic [31:0] some_mem [4] = {0, 0, 0, 432}; sub sub(); // Test loop initial begin count = 0; delayed = 0; onebit = 1'b0; fourthreetwoone[3] = 0; // stop icarus optimizing away text_byte = "B"; text_half = "Hf"; text_word = "Word"; text_long = "Long64b"; text = "Verilog Test module"; too_big = "some text"; real1 = 1.0; str1 = "hello"; `ifdef VERILATOR status = $c32("mon_check()"); `endif `ifdef IVERILOG status = $mon_check(); `endif `ifndef USE_VPI_NOT_DPI status = mon_check(); `endif if (status!=0) begin $write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status); $stop; end $write("%%Info: Checking results\n"); if (onebit != 1'b1) $stop; if (quads[2] != 62'h12819213_abd31a1c) $stop; if (quads[3] != 62'h1c77bb9b_3784ea09) $stop; if (text_byte != "A") $stop; if (text_half != "T2") $stop; if (text_word != "Tree") $stop; if (text_long != "44Four44") $stop; if (text != "lorem ipsum") $stop; if (str1 != "something a lot longer than hello") $stop; if (real1 > 123456.7895 || real1 < 123456.7885 ) $stop; end always @(posedge clk) begin count <= count + 2; if (count[1]) half_count <= half_count + 2; if (count == 1000) begin if (delayed != 123) $stop; if (delayed_mem[7] != 456) $stop; $write("*-* All Finished *-*\n"); $finish; end end genvar i; generate for (i=1; i<=6; i=i+1) begin : arr arr #(.LENGTH(i)) arr(); end endgenerate genvar k; generate for (k=1; k<=6; k=k+1) begin : subs sub subsub(); end endgenerate endmodule : t module sub; reg subsig1; reg subsig2; `ifdef IVERILOG // stop icarus optimizing signals away wire redundant = subsig1 | subsig2; `endif endmodule : sub module arr; parameter LENGTH = 1; reg [LENGTH-1:0] sig; reg [LENGTH-1:0] rfr; reg check; reg verbose; initial begin sig = {LENGTH{1'b0}}; rfr = {LENGTH{1'b0}}; end always @(posedge check) begin if (verbose) $display("%m : %x %x", sig, rfr); if (check && sig != rfr) $stop; check <= 0; end endmodule : arr verilator-5.042/test_regress/t/t_interface_gen6.v0000644000542200017500000000222115101701376022454 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty. // SPDX-License-Identifier: CC0-1.0 // bug1001 interface intf #(parameter PARAM = 0) (); logic val; endinterface module t(); generate if (1) begin intf #(.PARAM(2)) my_intf (); assign my_intf.val = '1; end else begin intf #(.PARAM(3)) my_intf (); assign my_intf.val = '0; end endgenerate generate begin if (1) begin intf #(.PARAM(2)) my_intf (); assign my_intf.val = '1; end else begin intf #(.PARAM(3)) my_intf (); assign my_intf.val = '0; end end endgenerate generate begin begin if (1) begin intf #(.PARAM(2)) my_intf (); assign my_intf.val = '1; end else begin intf #(.PARAM(3)) my_intf (); assign my_intf.val = '0; end end end endgenerate initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_fork_func_bad.out0000644000542200017500000000041215101701376022721 0ustar mahmoudyfreeshell%Error: t/t_fork_func_bad.v:11:10: Return isn't legal under fork (IEEE 1800-2023 9.2.3) 11 | return 0; | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_preproc_undefineall.v0000644000542200017500000000102015101701376023611 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; `define UDALL `ifndef PREDEF_COMMAND_LINE `error "Test setup error, PREDEF_COMMAND_LINE pre-missing" `endif `undefineall `ifdef UDALL `error "undefineall failed" `endif `ifndef PREDEF_COMMAND_LINE `error "Deleted too much, no PREDEF_COMMAND_LINE" `endif initial begin $finish; end endmodule verilator-5.042/test_regress/t/t_priority_case.py0000755000542200017500000000076615101701376022653 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_mod_dup_bad.out0000644000542200017500000000204715101701376022402 0ustar mahmoudyfreeshell%Warning-MODDUP: t/t_mod_dup_bad.v:14:8: Duplicate declaration of module: 'a' 14 | module a(); | ^ t/t_mod_dup_bad.v:7:8: ... Location of original declaration 7 | module a(); | ^ ... For warning description see https://verilator.org/warn/MODDUP?v=latest ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message. %Warning-MULTITOP: t/t_mod_dup_bad.v:17:8: Multiple top level modules : ... Suggest see manual; fix the duplicates, or use --top-module to select top. ... For warning description see https://verilator.org/warn/MULTITOP?v=latest ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message. : ... Top module 'test' 10 | module test(); | ^~~~ : ... Top module 'b' 17 | module b(); | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_forceable_net_vlt_trace.py0000755000542200017500000000155415101701376024626 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.pli_filename = "t/t_forceable_net.cpp" test.top_filename = "t/t_forceable_net.v" test.golden_filename = "t/t_forceable_net_trace.vcd.out" test.compile(make_top_shell=False, make_main=False, verilator_flags2=[ '--exe', '--trace-vcd', test.pli_filename, test.t_dir + "/t_forceable_net.vlt" ]) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_inst_pin_place_bad.py0000755000542200017500000000076615101701376023574 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_stream_dynamic.py0000755000542200017500000000073415101701376022771 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_time_passed.out0000644000542200017500000000021615101701376022436 0ustar mahmoudyfreeshelltop.t.ps: Input time 5432109.877000ns 5432109877 top.t.ns: Input time 5432109877.000000ns 5432109877 *-* All Finished *-* verilator-5.042/test_regress/t/t_math_equal.v0000644000542200017500000000403615101701376021723 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer _mode; reg _guard1; reg [127:0] r_wide0; reg _guard2; wire [63:0] r_wide1; reg _guard3; reg _guard4; reg _guard5; reg _guard6; assign r_wide1 = r_wide0[127:64]; // surefire lint_off STMINI initial _mode = 0; always @ (posedge clk) begin if (_mode==0) begin $write("[%0t] t_equal: Running\n", $time); _guard1 <= 0; _guard2 <= 0; _guard3 <= 0; _guard4 <= 0; _guard5 <= 0; _guard6 <= 0; _mode<=1; r_wide0 <= {32'h aa111111,32'hbb222222,32'hcc333333,32'hdd444444}; end else if (_mode==1) begin _mode<=2; // if (5'd10 != 5'b1010) $stop; if (5'd10 != 5'd10) $stop; if (5'd10 != 5'd1_0) $stop; if (5'd10 != 5'ha) $stop; if (5'd10 != 5'o12) $stop; if (5'd10 != 5'o1_2) $stop; if (5'd10 != 5'B 1010) $stop; if (5'd10 != 5'B 10_10) $stop; if (5'd10 != 5'D10) $stop; if (5'd10 != 5'H a) $stop; if (5'd10 != 5 'O 12) $stop; if (24'h29cbb8 != 24'o12345670) $stop; if (24'h29__cbb8 != 24'o123456__70) $stop; if (6'b111xxx !== 6'o7x) $stop; if (6'b111??? !== 6'o7?) $stop; if (6'b111zzz !== 6'o7z) $stop; // if (r_wide0 !== {32'haa111111,32'hbb222222,32'hcc333333,32'hdd444444}) $stop; if (r_wide1 !== {32'haa111111,32'hbb222222}) $stop; if (|{_guard1,_guard2,_guard3,_guard4,_guard5,_guard6}) begin $write("Guard error %x %x %x %x %x\n",_guard1,_guard2,_guard3,_guard4,_guard5); $stop; end $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_continue_do_while_bad.py0000755000542200017500000000102215101701376024265 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert'], fails=True) test.passes() verilator-5.042/test_regress/t/t_class_uses_this.v0000644000542200017500000000301215101701376022767 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 Rafal Kapuscik // SPDX-License-Identifier: CC0-1.0 // class Cls; bit [3:0] addr; function void set(bit [3:0] addr); begin : body this.addr = addr; end : body endfunction function void set2(bit [3:0] addr); begin : body Cls c2 = this; c2.addr = addr; end : body endfunction extern function void setext(bit [3:0] addr); extern function void setext2(bit [3:0] addr); endclass function void Cls::setext(bit [3:0] addr); this.addr = addr; endfunction function void Cls::setext2(bit [3:0] addr); Cls c2 = this; c2.addr = addr; endfunction class wrapped_int; int x; static wrapped_int q[$]; function new(int a); this.x = a; endfunction function void push_this; q.push_back(this); endfunction endclass module t; Cls bar; Cls baz; wrapped_int i1, i2; initial begin bar = new(); baz = new(); bar.set(4); `ifdef TEST_VERBOSE $display(bar.addr); $display(baz.addr); `endif if (bar.addr != 4) $stop; bar.set2(1); if (bar.addr != 1) $stop; bar.setext(2); if (bar.addr != 2) $stop; bar.setext2(3); if (bar.addr != 3) $stop; i1 = new(1); i1.push_this(); i2 = new(2); i2.push_this(); if (wrapped_int::q.size() != 2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_checker.v0000644000542200017500000000224215101701376021204 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; bit failure; mutex check_bus(cyc, clk, failure); integer cyc_d1; always @ (posedge clk) cyc_d1 <= cyc; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d cyc_d1=0x%0x exp=%x failure=%x\n", $time, cyc, cyc_d1, $onehot0(cyc), failure); `endif cyc <= cyc + 1; if (cyc < 3) begin end else if (cyc < 90) begin if (failure !== !$onehot0(cyc)) $stop; end else if (cyc == 99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule checker mutex (input logic [31:0] sig, input bit clk, output bit failure); logic [31:0] last_sig; assert property (@(negedge clk) $onehot0(sig)) failure = 1'b0; else failure = 1'b1; assert property (@(negedge clk) sig == last_sig + 1); always_ff @(posedge clk) last_sig <= sig; endchecker verilator-5.042/test_regress/t/t_func_real_exprstmt.v0000644000542200017500000000123215101701376023502 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; function automatic real logWrapper(real x); return $ln(x); endfunction initial begin // See bug4543 $display("bad x=%f, y=%f", logWrapper(10.0), 1.0 * logWrapper(10.0)); $display("noc x=%f, y=%f", $ln(10.0), 1.0 * $ln(10.0)); if (logWrapper(10.0) != $ln(10.0)) $stop; if (logWrapper(10.0) != 1.0 * logWrapper(10.0)) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_covergroup_in_class_duplicate_bad.v0000644000542200017500000000053615101701376026512 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off COVERIGN */ class myClass; covergroup embeddedCg; endgroup covergroup embeddedCg; endgroup endclass verilator-5.042/test_regress/t/t_class_if_assign.v0000644000542200017500000000147715101701376022740 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class Cls; int x; function new; x = 1; endfunction endclass class ExtendCls extends Cls; function new; x = 2; endfunction endclass class AnotherExtendCls extends Cls; function new; x = 3; endfunction endclass module t; initial begin Cls cls = new; ExtendCls ext_cls = new; AnotherExtendCls an_ext_cls = new; if (cls.x == 1) cls = ext_cls; else cls = an_ext_cls; if (cls.x != 2) $stop; if (cls.x == 1) cls = ext_cls; else cls = an_ext_cls; if (cls.x != 3) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_cover_sva_notflat.v0000644000542200017500000000271415101701376023322 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg toggle; integer cyc; initial cyc=1; Test suba (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle), .cyc (cyc[31:0])); Test subb (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle), .cyc (cyc[31:0])); Test subc (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle), .cyc (cyc[31:0])); always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; toggle <= !cyc[0]; if (cyc==9) begin end if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module Test ( input clk, input toggle, input [31:0] cyc ); // Don't flatten out these modules please: // verilator no_inline_module // Labeled cover cyc_eq_5: cover property (@(posedge clk) cyc==5) $display("*COVER: Cyc==5"); endmodule verilator-5.042/test_regress/t/t_fallback_bad.out0000644000542200017500000000301015101701376022501 0ustar mahmoudyfreeshell%Error: t/t_fallback_bad.v:26:16: Can't find definition of task/function: 'tsk' 26 | super.tsk; | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_fallback_bad.v:27:15: Can't find definition of task/function: 'tsk' 27 | this.tsk; | ^~~ %Error: t/t_fallback_bad.v:28:16: Can't find definition of variable/method: 'f' 28 | super.f = 8; | ^ %Error: t/t_fallback_bad.v:29:15: Can't find definition of variable/method: 'f' 29 | this.f = 8; | ^ %Error: t/t_fallback_bad.v:30:20: Can't find definition of 'tsk' in dotted task/function: 'sub1.sub2.tsk' 30 | sub1.sub2.tsk; | ^~~ ... Known scopes under 'tsk': sub2 %Error: t/t_fallback_bad.v:31:15: Can't find definition of scope/variable/func: 'f' 31 | pkg::f = 8; | ^ %Error: t/t_fallback_bad.v:32:15: Can't find definition of task/function: 'tsk' 32 | pkg::tsk(); | ^~~ %Error: t/t_fallback_bad.v:33:20: Can't find definition of 'f' in dotted variable/method: 'sub1.sub2.f' 33 | sub1.sub2.f = 8; | ^ %Error: t/t_fallback_bad.v:34:20: Can't find definition of 'f' in dotted scope/variable: 'sub1.sub2.f' 34 | sub1.sub2.f.f = 8; | ^ ... Known scopes under 'sub1.sub2': %Error: Exiting due to verilator-5.042/test_regress/t/t_trace_array_fst_threads_1_sc.py0000755000542200017500000000141515101701376025556 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_trace_array.v" test.golden_filename = "t/t_trace_array_fst_sc.out" if not test.have_sc: test.skip("No SystemC installed") test.compile( verilator_flags2=['--sc --trace-fst --trace-threads 1 --trace-structs --trace-max-width 0']) test.execute() test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_unopt_combo.v0000644000542200017500000000673215101701376022134 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc = 0; reg [63:0] crc; reg [63:0] sum; `ifdef ALLOW_UNOPT /*verilator lint_off UNOPTFLAT*/ `endif /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [31:0] b; // From file of file.v wire [31:0] c; // From file of file.v wire [31:0] d; // From file of file.v // End of automatics file file (/*AUTOINST*/ // Outputs .b (b[31:0]), .c (c[31:0]), .d (d[31:0]), // Inputs .crc (crc[31:0])); always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc=%0d crc=%x sum=%x b=%x d=%x\n", $time, cyc, crc, sum, b, d); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= {b, d} ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $write("[%0t] cyc==%0d crc=%x %x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; if (sum !== 64'h649ee1713d624dd9) $stop; $finish; end end endmodule module file (/*AUTOARG*/ // Outputs b, c, d, // Inputs crc ); input [31:0] crc; `ifdef ISOLATE output reg [31:0] b /* verilator isolate_assignments*/; `else output reg [31:0] b; `endif output reg [31:0] c; output reg [31:0] d; always @* begin // Note that while c and b depend on crc, b doesn't depend on c. casez (crc[3:0]) 4'b??01: begin b = {crc[15:0],get_31_16(crc)}; d = c; end 4'b??00: begin b = {crc[15:0],~crc[31:16]}; d = {crc[15:0],~c[31:16]}; end default: begin set_b_d(crc, c); end endcase end `ifdef ISOLATE function [31:16] get_31_16 /* verilator isolate_assignments*/; input [31:0] t_crc /* verilator isolate_assignments*/; get_31_16 = t_crc[31:16]; endfunction `else function [31:16] get_31_16; input [31:0] t_crc; get_31_16 = t_crc[31:16]; endfunction `endif task set_b_d; `ifdef ISOLATE input [31:0] t_crc /* verilator isolate_assignments*/; input [31:0] t_c /* verilator isolate_assignments*/; `else input [31:0] t_crc; input [31:0] t_c; `endif begin b = {t_crc[31:16],~t_crc[23:8]}; d = {t_crc[31:16], ~t_c[23:8]}; end endtask always @* begin // Any complicated equation we can't optimize casez (crc[3:0]) 4'b00??: begin c = {b[29:0],2'b11}; end 4'b01??: begin c = {b[30:1],2'b01}; end 4'b10??: begin c = {b[31:2],2'b10}; end 4'b11??: begin c = {b[31:2],2'b00}; end endcase end endmodule verilator-5.042/test_regress/t/t_sys_sscanf.v0000644000542200017500000000147015101701376021755 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); // verilog_format: on module t; localparam int unsigned XLEN = 32; string pkt; int unsigned idx; logic [XLEN-1:0] val; int code; initial begin // All digits after % is to get line coverage in verilated.cpp code = $sscanf("P20=4cff0000", "P%h=%80123456789h", idx, val); `checkh(code, 2); `checkh(idx, 32'h20); `checkh(val, 32'h4cff0000); $finish; end endmodule verilator-5.042/test_regress/t/t_mem_bound_bad.py0000755000542200017500000000100115101701376022531 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint( # Should fail, but doesn't) fails=not test.vlt_all) test.passes() verilator-5.042/test_regress/t/t_clocking_virtual.v0000644000542200017500000000277015101701376023145 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 interface Iface; logic clk = 1'b0, inp = 1'b0, io = 1'b0, out = 1'b0, out2 = 1'b0; clocking cb @(posedge clk); input #7 inp; output out; inout io; endclocking always @(posedge clk) inp <= 1'b1; always #5 clk <= ~clk; assign out2 = out; endinterface module main; initial begin #6; t.mod1.cb.io <= 1'b1; t.mod1.cb.out <= 1'b1; if (t.mod0.io != 1'b0) $stop; if (t.mod1.cb.io != 1'b0) $stop; if (t.mod1.cb.inp != 1'b0) $stop; @(posedge t.mod0.io) if ($time != 15) $stop; if (t.mod0.io != 1'b1) $stop; if (t.mod1.cb.io != 1'b0) $stop; #1 if (t.mod0.cb.io != 1'b1) $stop; if (t.mod1.cb.io != 1'b1) $stop; if (t.mod1.cb.inp != 1'b1) $stop; #8; t.mod0.inp = 1'b0; if (t.mod0.cb.inp != 1'b1) $stop; @(t.mod1.cb) if ($time != 25) $stop; if (t.mod0.cb.inp != 1'b1) $stop; t.mod0.inp = 1'b0; @(t.mod0.cb) if ($time != 35) $stop; if (t.mod0.cb.inp != 1'b0) $stop; $write("*-* All Finished *-*\n"); $finish; end initial begin @(posedge t.mod0.out) if ($time != 15) $stop; if (t.mod1.out2 != 1'b1) $stop; end endmodule module t; main main1(); Iface mod0(); virtual Iface mod1 = mod0; endmodule verilator-5.042/test_regress/t/t_select_bad_range6.out0000644000542200017500000000126015101701376023470 0ustar mahmoudyfreeshell%Warning-SELRANGE: t/t_select_bad_range6.v:13:16: Extracting 31 bits from only 12 bit number : ... note: In instance 't' 13 | assign o = i[31:1]; | ^ ... For warning description see https://verilator.org/warn/SELRANGE?v=latest ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Warning-SELRANGE: t/t_select_bad_range6.v:13:16: Selection index out of range: 31:1 outside 11:0 : ... note: In instance 't' 13 | assign o = i[31:1]; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_flag_timescale.v0000644000542200017500000000076215101701376022544 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under The Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; sub sub(); initial begin $write("t: "); $printtimescale; sub.pts(); $write("*-* All Finished *-*\n"); $finish; end endmodule `timescale 1s/1s module sub; task pts; $write("sub: "); $printtimescale; endtask endmodule verilator-5.042/test_regress/t/t_enum.py0000755000542200017500000000073415101701376020736 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_membersel_int.v0000644000542200017500000000066215101701376023616 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls; int t; endclass module Sub; Cls c; initial begin int i; c = new; i = c.t; $write("*-* All Finished *-*\n"); $finish; end endmodule module t; Sub foo(); endmodule verilator-5.042/test_regress/t/t_flag_lib_dpi_main.cpp0000644000542200017500000000237315101701376023521 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Shupei Fan. // SPDX-License-Identifier: CC0-1.0 // //************************************************************************* // // DESCRIPTION: main() calling loop, created with Verilator --main #include "verilated.h" #include "Vt_flag_lib_dpi.h" //====================== int main(int argc, char** argv, char**) { // Setup context, defaults, and parse command line Verilated::debug(0); const std::unique_ptr contextp{new VerilatedContext}; contextp->commandArgs(argc, argv); // Construct the Verilated model, from Vtop.h generated from Verilating const std::unique_ptr topp{new Vt_flag_lib_dpi{contextp.get()}}; // Simulate until $finish while (!contextp->gotFinish()) { // Evaluate model topp->eval(); // Advance time contextp->timeInc(1); } if (!contextp->gotFinish()) { VL_DEBUG_IF(VL_PRINTF("+ Exiting without $finish; no events left\n");); } // Final model cleanup topp->final(); return 0; } verilator-5.042/test_regress/t/t_struct_init_bad.out0000644000542200017500000000062115101701376023316 0ustar mahmoudyfreeshell%Error: t/t_struct_init.v:55:40: Assignment pattern contains duplicate entry: b1 : ... note: In instance 't' 55 | const b4_t b4_const_c = '{b1: 1'b1, b1: 1'b0, b0:1'b0, b2: 1'b1, b3: 1'b1}; | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_dpi_export_bad.v0000644000542200017500000000062315101701376022564 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; export "DPI-C" task dpix_bad_missing; endmodule verilator-5.042/test_regress/t/t_order_first.py0000755000542200017500000000073415101701376022314 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_func_arg_unused.py0000755000542200017500000000073415101701376024326 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_func_automatic_clear.py0000755000542200017500000000073415101701376024141 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_package_dup_bad2.out0000644000542200017500000000212615101701376023276 0ustar mahmoudyfreeshell%Warning-MODDUP: t/t_package_dup_bad2.v:19:9: Duplicate declaration of package: 'Pkg' 19 | package Pkg; | ^~~ t/t_package_dup_bad2.v:7:9: ... Location of original declaration 7 | package Pkg; | ^~~ ... For warning description see https://verilator.org/warn/MODDUP?v=latest ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message. %Error-MODMISSING: t/t_package_dup_bad2.v:11:3: Cannot find file containing module: 'IOBUF' 11 | IOBUF iocell ( | ^~~~~ ... For error description see https://verilator.org/warn/MODMISSING?v=latest ... Looked in: t/IOBUF t/IOBUF.v t/IOBUF.sv IOBUF IOBUF.v IOBUF.sv obj_vlt/t_package_dup_bad2/IOBUF obj_vlt/t_package_dup_bad2/IOBUF.v obj_vlt/t_package_dup_bad2/IOBUF.sv %Error: Exiting due to verilator-5.042/test_regress/t/t_unopt_bound.py0000755000542200017500000000077115101701376022327 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["-fno-dfg"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_typedef.v0000644000542200017500000000314115101701376021237 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package pkg; typedef bit pkg_bit_t; endpackage program t; parameter SIZE = 5; typedef vec_t; // Forward typedef vec_t; // Multi-forward is ok typedef reg [SIZE-1:0] vec_t; vec_t a; initial a =0; typedef bit [SIZE-1:0] vec_bit_t; vec_bit_t b; initial b =0; typedef int array_t [3]; typedef array_t array2_t [2]; array2_t ar [1]; typedef pkg::pkg_bit_t lcl_pkg_bit_t; // Define before use // Not sure how well supported this is elsewhere //UNSUP typedef preuse; //UNSUP preuse p; //UNSUP typedef int preuse; //reg [SIZE-1:0] a; initial a =0; //reg [SIZE-1:0] b; initial b =0; initial begin typedef logic [3:0][7:0] instr_mem_t; instr_mem_t a; a[0] = 8'h12; if (a[0] != 8'h12) $stop; end integer j; initial begin for (j=0;j<=(1< 1 && iface_inst.q != cyc - 2) $stop; end always @(posedge clk) begin cyc <= cyc + 1; if (cyc == 100) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_force_release.v0000644000542200017500000000210315101701376022372 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); end while(0) // Example from IEEE 1800-2023 10.6.2 module t; logic a, b, c, d; wire e; and and1 (e, a, b, c); initial begin $monitor("%d d=%b,e=%b", $stime, d, e); assign d = a & b & c; a = 1; b = 0; c = 1; #10; force d = (a | b | c); force e = (a | b | c); `checkh(d, 1); `checkh(e, 1); #10; release d; release e; // TODO support procedural continuous assignments. // // As per IEEE 1800-2023 10.6.2, value of `d` should be updated // after release. However, Verilator treats `assign` inside an initial block // as procedural assign thus value update is not properly restored. #10; `checkh(d, 0); `checkh(e, 0); $finish; end endmodule verilator-5.042/test_regress/t/t_var_ref.py0000755000542200017500000000073415101701376021416 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_package.v0000644000542200017500000000205115101701376022356 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package pkga; int pvar; class MyClass; int member; function int getpvar(); return pvar; endfunction endclass endpackage package pkgb; int pvar; class MyClass; int member; function int getpvar(); return pvar; endfunction function int getavar(); return pkga::pvar; endfunction endclass endpackage module t; initial begin pkga::MyClass a; pkgb::MyClass b; pkga::pvar = 100; pkgb::pvar = 200; if (pkga::pvar != 100) $stop; if (pkgb::pvar != 200) $stop; a = new; b = new; a.member = 10; b.member = 20; if (a.member != 10) $stop; if (b.member != 20) $stop; if (a.getpvar() != 100) $stop; if (b.getpvar() != 200) $stop; if (b.getavar() != 100) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_clk_concat_vlt.py0000755000542200017500000000120015101701376022744 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_clk_concat.v" out_filename = test.obj_dir + "/V" + test.name + ".tree.json" test.compile(verilator_flags2=["--no-json-edit-nums", "t/t_clk_concat.vlt"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_class_null_struct.py0000755000542200017500000000073415101701376023535 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_hier_block_type_param_multiple_instances.py0000755000542200017500000000077715101701376030305 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--hierarchical']) test.execute() test.passes() verilator-5.042/test_regress/t/t_math_shift.py0000755000542200017500000000073415101701376022120 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_a3_selftest_thread.py0000755000542200017500000000104415101701376023530 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vltmt') test.top_filename = "t/t_EXAMPLE.v" test.lint(v_flags=["--lint-only --verilate-jobs 2 --debug-self-test"]) test.passes() verilator-5.042/test_regress/t/t_func_sum.py0000755000542200017500000000073415101701376021611 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_gate_inline_wide_noexclude_small_wide.py0000755000542200017500000000111415101701376027517 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=['--stats', '--expand-limit 5']) test.file_grep(test.stats, r'Optimizations, Gate excluded wide expressions\s+(\d+)', 0) test.passes() verilator-5.042/test_regress/t/t_math_shift_side.py0000755000542200017500000000073415101701376023124 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_array_saif_threads_1.py0000755000542200017500000000141015101701376025212 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_trace_array.v" test.golden_filename = "t/t_trace_array_saif.out" test.compile( verilator_flags2=['--cc --trace-saif --trace-threads 1 --trace-structs --trace-max-width 0']) test.execute() # saif_identical is very slow, so require exact match test.files_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_sys_writemem_b.gold6.mem0000644000542200017500000000066015101701376024155 0ustar mahmoudyfreeshell00000000000000000000000000 00000000000000000000000000 00000000000000000000000000 00000000000000000000000000 10010101000000000000000100 00000000000000000000000000 00000000000000000000000000 00000000000000000000000000 00000000000000000000000000 00000000000000000000000000 10010101000000000000001010 10010101000000000000001011 10010101000000000000001100 00000000000000000000000000 00000000000000000000000000 00000000000000000000000000 verilator-5.042/test_regress/t/t_udp_bad_line_outputs.v0000644000542200017500000000070415101701376024011 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 primitive udp_1(output reg o, input i); table ? : 0 0 : 0; // <--- BAD too many recirc endtable endprimitive primitive udp_2(output reg o, input i); table ? : 0 : 0 0; // <--- BAD too many outputs endtable endprimitive verilator-5.042/test_regress/t/t_param_type_bad2.py0000755000542200017500000000111515101701376023015 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint( # Bug1575 required trace to crash verilator_flags2=["--trace-vcd --cc"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_sys_time.v0000644000542200017500000000127315101701376021437 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] time64; // Test loop always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==0) begin end else if (cyc<10) begin end else if (cyc<90) begin time64 = $time; if ($stime != time64[31:0]) $stop; end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_trace_public_sig.cpp0000644000542200017500000000255515101701376023422 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include // clang-format off #include VM_PREFIX_INCLUDE #ifdef T_TRACE_PUBLIC_SIG_VLT # include "Vt_trace_public_sig_vlt_t.h" # include "Vt_trace_public_sig_vlt_glbl.h" #else # include "Vt_trace_public_sig_t.h" # include "Vt_trace_public_sig_glbl.h" #endif // clang-format on unsigned long long main_time = 0; double sc_time_stamp() { return (double)main_time; } const unsigned long long dt_2 = 3; int main(int argc, char** argv) { Verilated::debug(0); Verilated::traceEverOn(true); Verilated::commandArgs(argc, argv); VM_PREFIX* top = new VM_PREFIX{"top"}; VerilatedVcdC* tfp = new VerilatedVcdC; top->trace(tfp, 99); tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); while (main_time <= 20) { top->CLK = (main_time / dt_2) % 2; top->eval(); top->t->glbl->GSR = (main_time < 7); tfp->dump((unsigned int)(main_time)); ++main_time; } tfp->close(); top->final(); VL_DO_DANGLING(delete top, top); VL_DO_DANGLING(delete tfp, tfp); printf("*-* All Finished *-*\n"); return 0; } verilator-5.042/test_regress/t/t_array_pattern_unpacked.v0000644000542200017500000000471015101701376024327 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2009 by Iztok Jeras. // SPDX-License-Identifier: CC0-1.0 module t; logic [3:0] array_simp [1:0] [3:0]; // descending range array wire [2:0] array_wire [1:0] = '{3'd1, 3'd2}; int irep[1:2][1:6]; initial begin if (array_wire[0] !== 3'd2) $stop; if (array_wire[1] !== 3'd1) $stop; array_simp[0] = '{ 4'd3, 4'd2, 4'd1, 4'd0}; if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 16'h3210) $stop; // verilator lint_off WIDTH array_simp[0] = '{ 3 ,2 ,1, 0 }; // verilator lint_on WIDTH if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 16'h3210) $stop; // Doesn't seem to work for unpacked arrays in other simulators //array_simp[0] = '{ 1:4'd3, default:13 }; //if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 16'hDD3D) $stop; array_simp = '{ '{ 4'd3, 4'd2, 4'd1, 4'd0 }, '{ 4'd1, 4'd2, 4'd3, 4'd4 }}; if ({array_simp[1][3],array_simp[1][2],array_simp[1][1],array_simp[1][0], array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 32'h3210_1234) $stop; // Doesn't seem to work for unpacked arrays in other simulators array_simp = '{2{ '{4'd3, 4'd2, 4'd1, 4'd0 } }}; if ({array_simp[1][3],array_simp[1][2],array_simp[1][1],array_simp[1][0], array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 32'h3210_3210) $stop; array_simp = '{2{ '{4{ 4'd3 }} }}; if ({array_simp[1][3],array_simp[1][2],array_simp[1][1],array_simp[1][0], array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 32'h3333_3333) $stop; // Not legal in other simulators - replication doesn't match // However IEEE suggests this is legal. //array_simp = '{2{ '{2{ 4'd3, 4'd2 }} }}; // Note it's not '{3,2} // Replication irep = '{2{ '{3 {4, 5}}}}; if ({irep[1][1], irep[1][2], irep[1][3], irep[1][4], irep[1][5], irep[1][6]} != {32'h4, 32'h5, 32'h4, 32'h5, 32'h4, 32'h5}) $stop; if ({irep[2][1], irep[2][2], irep[2][3], irep[2][4], irep[2][5], irep[2][6]} != {32'h4, 32'h5, 32'h4, 32'h5, 32'h4, 32'h5}) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_interface_generic_modport_function_bad.v0000644000542200017500000000121115101701376027506 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 interface inf; int v; function int get(); return v; endfunction modport mp( input v ); endinterface interface inf2; int k; endinterface module GenericModule (interface.mp a); initial begin #1; if (a.get() != 4) $stop; end endmodule module t; inf inf_inst(); GenericModule genericModule (inf_inst); initial begin inf_inst.v = 4; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_assoc_ref_type.v0000644000542200017500000000342315101701376022607 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class Foo1; int x = 1; function int get_x; return x; endfunction endclass class Foo2; int x = 2; function int get_x; return x; endfunction endclass class Bar; typedef Foo1 foo_t; protected foo_t m_dict[int]; function void set(int key); foo_t default_value = new; m_dict[key] = default_value; endfunction function foo_t get(int key); return m_dict[key]; endfunction endclass class Baz #(type T=Foo1); protected T m_dict[int]; function void set(int key); T default_value = new; m_dict[key] = default_value; endfunction function T get(int key); return m_dict[key]; endfunction endclass class WBase; endclass class Wrapper#(type VAL_T=int); VAL_T value; endclass class Bum; typedef int map_t[string]; map_t m_value; function new(map_t value); m_value = value; endfunction endclass module t; typedef WBase wrap_map_t[string]; typedef WBase wrap_queue_t[$]; localparam string str_key = "the_key"; initial begin Bar bar_i = new; Baz baz_1_i = new; Baz #(Foo2) baz_2_i = new; Bum bum_i; Wrapper#(wrap_map_t) wrap_map = new(); Wrapper#(wrap_queue_t) wrap_queue = new(); bar_i.set(1); baz_1_i.set(2); baz_2_i.set(3); if (bar_i.get(1).get_x() != 1) $stop; if (baz_1_i.get(2).get_x() != 1) $stop; if (baz_2_i.get(3).get_x() != 2) $stop; bum_i = new('{str_key: 42}); if (bum_i.m_value["the_key"] != 42) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_trace_param_saif.py0000755000542200017500000000113315101701376023244 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_trace_param.v" test.compile(v_flags2=["--trace-saif"]) test.execute() test.saif_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_defaultparams.py0000755000542200017500000000070615101701376024006 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.passes() verilator-5.042/test_regress/t/t_math_clog2.v0000644000542200017500000000560115101701376021621 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `ifdef verilator `define CLOG2 $clog2 `else `define CLOG2 clog2_emulate `endif module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Need temp wires as function has different width rules than $clog2 wire [127:0] pows = 128'h1<> 1); end endfunction endmodule verilator-5.042/test_regress/t/t_preproc_eof4_bad.py0000755000542200017500000000076615101701376023174 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_flag_build_bad2.py0000755000542200017500000000150315101701376022745 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_flag_make_cmake.v" test.compile( # Need --no-print-directory so golden file doesn't compare directory names verilator_flags2=[ "--build --MAKEFLAGS --no-print-directory", " --MAKEFLAGS illegal-flag-to-fail-make" ], # Recursive make breaks the golden compare #expect_filename = test.golden_filename fails='any') # make returns exit code 2 test.passes() verilator-5.042/test_regress/t/t_wait_order.out0000644000542200017500000000160415101701376022302 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_wait_order.v:17:23: Unsupported: wait_order 17 | wait_order (a, b) wif[0] = '1; | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_wait_order.v:26:23: Unsupported: wait_order 26 | wait_order (a, b) else welse[1] = '1; | ^ %Error-UNSUPPORTED: t/t_wait_order.v:29:23: Unsupported: wait_order 29 | wait_order (b, a) else nelse[1] = '1; | ^ %Error-UNSUPPORTED: t/t_wait_order.v:33:23: Unsupported: wait_order 33 | wait_order (a, b) wif[2] = '1; else welse[2] = '1; | ^ %Error-UNSUPPORTED: t/t_wait_order.v:36:23: Unsupported: wait_order 36 | wait_order (b, a) nif[2] = '1; else nelse[2] = '1; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_vpi_var.py0000755000542200017500000000152315101701376021435 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(make_top_shell=False, make_main=False, make_pli=True, sim_time=2100, iv_flags2=["-g2005-sv -D USE_VPI_NOT_DPI -DWAVES"], v_flags2=["+define+USE_VPI_NOT_DPI"], verilator_flags2=["-Wno-SYMRSVDWORD --exe --vpi --no-l2name", test.pli_filename]) test.execute(use_libvpi=True, all_run_flags=['+PLUS +INT=1234 +STRSTR']) test.passes() verilator-5.042/test_regress/t/t_display_mcd.py0000755000542200017500000000100015101701376022245 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_param_array3.py0000755000542200017500000000073415101701376022353 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_enum_name2.v0000644000542200017500000000137015101701376021627 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014 by Jonathon Donaldson. // SPDX-License-Identifier: CC0-1.0 package our_pkg; typedef enum logic [8-1:0] { ADC_IN2IN = 8'h99, ADC_IMMED = 8'h88, ADC_INDIR = 8'h86, ADC_INIDX = 8'h97 } T_Opcode; endpackage : our_pkg module t (); our our (); endmodule module our import our_pkg::*; (); T_Opcode IR = ADC_IN2IN; initial begin $write ("%s (%t)\n", IR.name, $realtime); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_mod_interface_array2.v0000644000542200017500000000264215101701376023663 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Johan Bjork. // SPDX-License-Identifier: CC0-1.0 parameter N = 4; // verilator lint_off ASCRANGE interface a_if #(parameter PARAM = 0) (); logic long_name; modport source (output long_name); modport sink (input long_name); endinterface module intf_source ( input logic [0:N-1] intf_input, a_if.source i_intf_source[0:N-1] ); generate for (genvar i=0; i < N;i++) begin assign i_intf_source[i].long_name = intf_input[i]; end endgenerate endmodule module intf_sink ( output [0:N-1] a_out, a_if.sink i_intf_sink[0:N-1] ); generate for (genvar i=0; i < N;i++) begin assign a_out[i] = i_intf_sink[i].long_name; end endgenerate endmodule module t ( clk ); input clk; logic [0:N-1] a_in; logic [0:N-1] a_out; logic [0:N-1] ack_out; a_if #(.PARAM(1)) tl_intf [0:N-1] (); intf_source source(a_in, tl_intf); intf_sink sink(a_out, tl_intf); initial a_in = '0; initial ack_out = '0; always @(posedge clk) begin a_in <= a_in + { {N-1 {1'b0}}, 1'b1 }; ack_out <= ack_out + { {N-1 {1'b0}}, 1'b1 }; if (ack_out != a_out) begin $stop; end if (& a_in) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_timing_debug1.out0000644000542200017500000056314215101701376022673 0ustar mahmoudyfreeshell-V{t#,#}- Verilated::debug is on. Message prefix indicates {,}. -V{t#,#}+ Vt_timing_debug1___024root___ctor_var_reset -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Initial -V{t#,#}+ Vt_timing_debug1___024root___eval_static -V{t#,#}+ Vt_timing_debug1___024root___eval_static__TOP -V{t#,#}+ Vt_timing_debug1___024root___eval_initial -V{t#,#}+ Vt_timing_debug1___024root___eval_initial__TOP__Vtiming__0 -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:18 -V{t#,#}+ Vt_timing_debug1___024root___eval_initial__TOP__Vtiming__1 -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___eval_initial__TOP__Vtiming__2 -V{t#,#} Suspending process waiting for @(posedge t.clk2) at t/t_timing_sched.v:48 -V{t#,#}+ Vt_timing_debug1___024root___eval_initial__TOP__Vtiming__3 -V{t#,#}+ Vt_timing_debug1___024root___eval_settle -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__stl -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__stl -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__stl -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__stl -V{t#,#} 'stl' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#} 'stl' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'stl' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) -V{t#,#} 'stl' region trigger index 3 is active: @([hybrid] t.clk2) -V{t#,#} 'stl' region trigger index 4 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'stl' region trigger index 5 is active: @([hybrid] __VassignWgen_h########__0) -V{t#,#} 'stl' region trigger index 64 is active: Internal 'stl' trigger - first iteration -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__stl -V{t#,#}+ Vt_timing_debug1___024root___eval_stl -V{t#,#}+ Vt_timing_debug1___024root___stl_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1____Vfork_2__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__stl -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__stl -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__stl -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__stl -V{t#,#} 'stl' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'stl' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) -V{t#,#} 'stl' region trigger index 4 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'stl' region trigger index 5 is active: @([hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__stl -V{t#,#}+ Vt_timing_debug1___024root___eval_stl -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__stl -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__stl -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__stl -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__stl -V{t#,#} No 'stl' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__stl -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) -V{t#,#} 'act' region trigger index 3 is active: @([hybrid] t.clk2) -V{t#,#} 'act' region trigger index 4 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 5 is active: @([hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#} Committing processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:18 -V{t#,#} - Process waiting at t/t_timing_sched.v:17 -V{t#,#} Committing processes waiting for @(posedge t.clk2): -V{t#,#} - Process waiting at t/t_timing_sched.v:48 -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 3: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#} 'act' region trigger index 6 is active: @(posedge t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Ready processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:18 -V{t#,#} Ready processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:17 -V{t#,#} Resuming processes waiting for @(posedge t.clk1) -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:18 -V{t#,#} Suspending process waiting for @(posedge t.clk2) at t/t_timing_sched.v:18 -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#} Committing processes waiting for @(posedge t.clk2): -V{t#,#} - Process waiting at t/t_timing_sched.v:18 -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___nba_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 6: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 7: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 7: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 9: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#} Committing processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 9: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#} 'act' region trigger index 6 is active: @(posedge t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Ready processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:17 -V{t#,#} Resuming processes waiting for @(posedge t.clk1) -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___nba_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 12: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 13: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:13 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 3 is active: @([hybrid] t.clk2) -V{t#,#} 'act' region trigger index 8 is active: @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Ready processes waiting for @(posedge t.clk2): -V{t#,#} - Process waiting at t/t_timing_sched.v:48 -V{t#,#} Ready processes waiting for @(posedge t.clk2): -V{t#,#} - Process waiting at t/t_timing_sched.v:18 -V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:48 -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:18 -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:18 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1____Vfork_2__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 4 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 5 is active: @([hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#} Committing processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:18 -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 12: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 12: Process waiting at t/t_timing_sched.v:48 -V{t#,#} Awaiting time 13: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 22: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:48 -V{t#,#} Suspending process waiting for @(posedge t.clk2) at t/t_timing_sched.v:48 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#} Committing processes waiting for @(posedge t.clk2): -V{t#,#} - Process waiting at t/t_timing_sched.v:48 -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 13: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 15: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 22: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#} Committing processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 15: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 22: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#} 'act' region trigger index 6 is active: @(posedge t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Ready processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:18 -V{t#,#} Ready processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:17 -V{t#,#} Resuming processes waiting for @(posedge t.clk1) -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:18 -V{t#,#} Suspending process waiting for @(posedge t.clk2) at t/t_timing_sched.v:18 -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#} Committing processes waiting for @(posedge t.clk2): -V{t#,#} - Process waiting at t/t_timing_sched.v:18 -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___nba_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 18: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 19: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 22: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 19: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 21: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 22: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#} Committing processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 21: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 22: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#} 'act' region trigger index 6 is active: @(posedge t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Ready processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:17 -V{t#,#} Resuming processes waiting for @(posedge t.clk1) -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___nba_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 22: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 24: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 25: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:13 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 3 is active: @([hybrid] t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1____Vfork_2__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 4 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 5 is active: @([hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 24: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 25: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 33: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 25: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 27: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 33: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#} Committing processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 27: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 33: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#} 'act' region trigger index 6 is active: @(posedge t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Ready processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:17 -V{t#,#} Resuming processes waiting for @(posedge t.clk1) -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___nba_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 30: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 31: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 33: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 31: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 33: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 33: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#} Committing processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 33: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 33: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#} 'act' region trigger index 3 is active: @([hybrid] t.clk2) -V{t#,#} 'act' region trigger index 6 is active: @(posedge t.clk1) -V{t#,#} 'act' region trigger index 8 is active: @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Ready processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:17 -V{t#,#} Resuming processes waiting for @(posedge t.clk1) -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Ready processes waiting for @(posedge t.clk2): -V{t#,#} - Process waiting at t/t_timing_sched.v:48 -V{t#,#} Ready processes waiting for @(posedge t.clk2): -V{t#,#} - Process waiting at t/t_timing_sched.v:18 -V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:48 -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:18 -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:18 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1____Vfork_2__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) -V{t#,#} 'act' region trigger index 4 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 5 is active: @([hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#} Committing processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:18 -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___nba_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 34: Process waiting at t/t_timing_sched.v:48 -V{t#,#} Awaiting time 36: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 37: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 44: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:48 -V{t#,#} Suspending process waiting for @(posedge t.clk2) at t/t_timing_sched.v:48 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#} Committing processes waiting for @(posedge t.clk2): -V{t#,#} - Process waiting at t/t_timing_sched.v:48 -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 36: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 37: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 44: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 37: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 39: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 44: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#} Committing processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 39: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 44: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#} 'act' region trigger index 6 is active: @(posedge t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Ready processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:18 -V{t#,#} Ready processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:17 -V{t#,#} Resuming processes waiting for @(posedge t.clk1) -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:18 -V{t#,#} Suspending process waiting for @(posedge t.clk2) at t/t_timing_sched.v:18 -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#} Committing processes waiting for @(posedge t.clk2): -V{t#,#} - Process waiting at t/t_timing_sched.v:18 -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___nba_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 42: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 43: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 44: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 43: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 44: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 45: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#} Committing processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 44: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 45: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:13 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 3 is active: @([hybrid] t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1____Vfork_2__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 4 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 5 is active: @([hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 45: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 55: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#} 'act' region trigger index 6 is active: @(posedge t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Ready processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:17 -V{t#,#} Resuming processes waiting for @(posedge t.clk1) -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___nba_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 48: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 49: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 55: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 49: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 51: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 55: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#} Committing processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 51: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 55: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#} 'act' region trigger index 6 is active: @(posedge t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Ready processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:17 -V{t#,#} Resuming processes waiting for @(posedge t.clk1) -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___nba_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 54: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 55: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 55: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 55: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 55: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 57: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 3 is active: @([hybrid] t.clk2) -V{t#,#} 'act' region trigger index 8 is active: @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#} Committing processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Ready processes waiting for @(posedge t.clk2): -V{t#,#} - Process waiting at t/t_timing_sched.v:48 -V{t#,#} Ready processes waiting for @(posedge t.clk2): -V{t#,#} - Process waiting at t/t_timing_sched.v:18 -V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:48 -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:18 -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:18 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1____Vfork_2__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 4 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 5 is active: @([hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#} Committing processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:18 -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 56: Process waiting at t/t_timing_sched.v:48 -V{t#,#} Awaiting time 57: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 66: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:48 -V{t#,#} Suspending process waiting for @(posedge t.clk2) at t/t_timing_sched.v:48 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#} Committing processes waiting for @(posedge t.clk2): -V{t#,#} - Process waiting at t/t_timing_sched.v:48 -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 57: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 66: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#} 'act' region trigger index 6 is active: @(posedge t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Ready processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:17 -V{t#,#} Ready processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:18 -V{t#,#} Resuming processes waiting for @(posedge t.clk1) -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:18 -V{t#,#} Suspending process waiting for @(posedge t.clk2) at t/t_timing_sched.v:18 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#} Committing processes waiting for @(posedge t.clk2): -V{t#,#} - Process waiting at t/t_timing_sched.v:18 -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___nba_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 60: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 61: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 66: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 61: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 63: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 66: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#} Committing processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 63: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 66: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#} 'act' region trigger index 6 is active: @(posedge t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Ready processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:17 -V{t#,#} Resuming processes waiting for @(posedge t.clk1) -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___nba_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 66: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 66: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 67: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#} 'act' region trigger index 3 is active: @([hybrid] t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1____Vfork_2__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) -V{t#,#} 'act' region trigger index 4 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 5 is active: @([hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 67: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 69: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 77: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#} Committing processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 69: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 77: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#} 'act' region trigger index 6 is active: @(posedge t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Ready processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:17 -V{t#,#} Resuming processes waiting for @(posedge t.clk1) -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___nba_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 72: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 73: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 77: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 73: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 75: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 77: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#} Committing processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 75: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 77: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#} 'act' region trigger index 6 is active: @(posedge t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Ready processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:17 -V{t#,#} Resuming processes waiting for @(posedge t.clk1) -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___nba_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 77: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 79: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:13 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 3 is active: @([hybrid] t.clk2) -V{t#,#} 'act' region trigger index 8 is active: @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Ready processes waiting for @(posedge t.clk2): -V{t#,#} - Process waiting at t/t_timing_sched.v:48 -V{t#,#} Ready processes waiting for @(posedge t.clk2): -V{t#,#} - Process waiting at t/t_timing_sched.v:18 -V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:48 -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:18 -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:18 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1____Vfork_2__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 4 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 5 is active: @([hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#} Committing processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:18 -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step -V{t#,#}+ Vt_timing_debug1___024root___eval_debug_assertions -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:48 -V{t#,#} Awaiting time 79: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 88: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:50 *-* All Finished *-* -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:48 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup -V{t#,#}+ Vt_timing_debug1___024root___eval_final verilator-5.042/test_regress/t/t_debug_emitv_addrids.py0000755000542200017500000000123115101701376023747 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_debug_emitv.v" test.lint( # We also have dump-tree turned on, so hit a lot of AstNode*::dump() functions # Likewise XML v_flags=["--lint-only --dumpi-tree 9 --dump-tree-addrids --timing"]) test.passes() verilator-5.042/test_regress/t/t_class_static_member_sel.v0000644000542200017500000000307015101701376024446 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class Foo; static int x = 1; endclass class Bar; Foo f; function new; f = new; endfunction endclass class Baz; static function Bar get_bar; Bar b = new; return b; endfunction endclass class IntWrapper; int x; endclass class Cls; static IntWrapper iw; function new; if (iw == null) iw = new; endfunction endclass class ExtendCls extends Cls; endclass class Getter1; static function int get_1; return 1; endfunction endclass class uvm_root; int x; static uvm_root m_inst; static function uvm_root get_inst(); if (m_inst == null) m_inst = new; return m_inst; endfunction function int get_7(); return 7; endfunction endclass module t; initial begin Foo foo = new; Bar bar = new; Baz baz = new; ExtendCls ec = new; Getter1 getter1 = new; if (foo.x != 1) $stop; foo.x = 2; if (foo.x != 2) $stop; bar.f.x = 3; if (bar.f.x != 3) $stop; baz.get_bar().f.x = 4; if (baz.get_bar().f.x != 4) $stop; ec.iw.x = 5; if (ec.iw.x != 5) $stop; if (getter1.get_1 != 1) $stop; uvm_root::get_inst().x = 6; if (uvm_root::get_inst().x != 6) $stop; if (uvm_root::get_inst().get_7() != 7) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_dpi_arg_input_unpack__Dpi.out0000644000542200017500000003410215101701376025262 0ustar mahmoudyfreeshell// Verilated -*- C++ -*- // DESCRIPTION: Verilator output: Prototypes for DPI import and export functions. // // Verilator includes this file in all generated .cpp files that use DPI functions. // Manually include this file where DPI .c import functions are declared to ensure // the C functions match the expectations of the DPI imports. #ifndef VERILATED_VT_DPI_ARG_INPUT_UNPACK__DPI_H_ #define VERILATED_VT_DPI_ARG_INPUT_UNPACK__DPI_H_ // guard #include "svdpi.h" #ifdef __cplusplus extern "C" { #endif // DPI EXPORTS extern void e_bit121_0d(const svBitVecVal* val); extern void e_bit121_1d(const svBitVecVal* val); extern void e_bit121_1d1(const svBitVecVal* val); extern void e_bit121_2d(const svBitVecVal* val); extern void e_bit121_2d1(const svBitVecVal* val); extern void e_bit121_3d(const svBitVecVal* val); extern void e_bit121_3d1(const svBitVecVal* val); extern void e_bit1_0d(svBit val); extern void e_bit1_1d(const svBit* val); extern void e_bit1_1d1(const svBit* val); extern void e_bit1_2d(const svBit* val); extern void e_bit1_2d1(const svBit* val); extern void e_bit1_3d(const svBit* val); extern void e_bit1_3d1(const svBit* val); extern void e_bit7_0d(const svBitVecVal* val); extern void e_bit7_1d(const svBitVecVal* val); extern void e_bit7_1d1(const svBitVecVal* val); extern void e_bit7_2d(const svBitVecVal* val); extern void e_bit7_2d1(const svBitVecVal* val); extern void e_bit7_3d(const svBitVecVal* val); extern void e_bit7_3d1(const svBitVecVal* val); extern void e_byte_0d(char val); extern void e_byte_1d(const char* val); extern void e_byte_1d1(const char* val); extern void e_byte_2d(const char* val); extern void e_byte_2d1(const char* val); extern void e_byte_3d(const char* val); extern void e_byte_3d1(const char* val); extern void e_byte_unsigned_0d(unsigned char val); extern void e_byte_unsigned_1d(const unsigned char* val); extern void e_byte_unsigned_1d1(const unsigned char* val); extern void e_byte_unsigned_2d(const unsigned char* val); extern void e_byte_unsigned_2d1(const unsigned char* val); extern void e_byte_unsigned_3d(const unsigned char* val); extern void e_byte_unsigned_3d1(const unsigned char* val); extern void e_chandle_0d(void* val); extern void e_chandle_1d(const void** val); extern void e_chandle_1d1(const void** val); extern void e_chandle_2d(const void** val); extern void e_chandle_2d1(const void** val); extern void e_chandle_3d(const void** val); extern void e_chandle_3d1(const void** val); extern void e_int_0d(int val); extern void e_int_1d(const int* val); extern void e_int_1d1(const int* val); extern void e_int_2d(const int* val); extern void e_int_2d1(const int* val); extern void e_int_3d(const int* val); extern void e_int_3d1(const int* val); extern void e_int_unsigned_0d(unsigned int val); extern void e_int_unsigned_1d(const unsigned int* val); extern void e_int_unsigned_1d1(const unsigned int* val); extern void e_int_unsigned_2d(const unsigned int* val); extern void e_int_unsigned_2d1(const unsigned int* val); extern void e_int_unsigned_3d(const unsigned int* val); extern void e_int_unsigned_3d1(const unsigned int* val); extern void e_integer_0d(const svLogicVecVal* val); extern void e_integer_1d(const svLogicVecVal* val); extern void e_integer_1d1(const svLogicVecVal* val); extern void e_integer_2d(const svLogicVecVal* val); extern void e_integer_2d1(const svLogicVecVal* val); extern void e_integer_3d(const svLogicVecVal* val); extern void e_integer_3d1(const svLogicVecVal* val); extern void e_logic121_0d(const svLogicVecVal* val); extern void e_logic121_1d(const svLogicVecVal* val); extern void e_logic121_1d1(const svLogicVecVal* val); extern void e_logic121_2d(const svLogicVecVal* val); extern void e_logic121_2d1(const svLogicVecVal* val); extern void e_logic121_3d(const svLogicVecVal* val); extern void e_logic121_3d1(const svLogicVecVal* val); extern void e_logic1_0d(svLogic val); extern void e_logic1_1d(const svLogic* val); extern void e_logic1_1d1(const svLogic* val); extern void e_logic1_2d(const svLogic* val); extern void e_logic1_2d1(const svLogic* val); extern void e_logic1_3d(const svLogic* val); extern void e_logic1_3d1(const svLogic* val); extern void e_logic7_0d(const svLogicVecVal* val); extern void e_logic7_1d(const svLogicVecVal* val); extern void e_logic7_1d1(const svLogicVecVal* val); extern void e_logic7_2d(const svLogicVecVal* val); extern void e_logic7_2d1(const svLogicVecVal* val); extern void e_logic7_3d(const svLogicVecVal* val); extern void e_logic7_3d1(const svLogicVecVal* val); extern void e_longint_0d(long long val); extern void e_longint_1d(const long long* val); extern void e_longint_1d1(const long long* val); extern void e_longint_2d(const long long* val); extern void e_longint_2d1(const long long* val); extern void e_longint_3d(const long long* val); extern void e_longint_3d1(const long long* val); extern void e_longint_unsigned_0d(unsigned long long val); extern void e_longint_unsigned_1d(const unsigned long long* val); extern void e_longint_unsigned_1d1(const unsigned long long* val); extern void e_longint_unsigned_2d(const unsigned long long* val); extern void e_longint_unsigned_2d1(const unsigned long long* val); extern void e_longint_unsigned_3d(const unsigned long long* val); extern void e_longint_unsigned_3d1(const unsigned long long* val); extern void e_pack_struct_0d(const svLogicVecVal* val); extern void e_pack_struct_1d(const svLogicVecVal* val); extern void e_pack_struct_1d1(const svLogicVecVal* val); extern void e_pack_struct_2d(const svLogicVecVal* val); extern void e_pack_struct_2d1(const svLogicVecVal* val); extern void e_pack_struct_3d(const svLogicVecVal* val); extern void e_pack_struct_3d1(const svLogicVecVal* val); extern void e_real_0d(double val); extern void e_real_1d(const double* val); extern void e_real_1d1(const double* val); extern void e_real_2d(const double* val); extern void e_real_2d1(const double* val); extern void e_real_3d(const double* val); extern void e_real_3d1(const double* val); extern void e_shortint_0d(short val); extern void e_shortint_1d(const short* val); extern void e_shortint_1d1(const short* val); extern void e_shortint_2d(const short* val); extern void e_shortint_2d1(const short* val); extern void e_shortint_3d(const short* val); extern void e_shortint_3d1(const short* val); extern void e_shortint_unsigned_0d(unsigned short val); extern void e_shortint_unsigned_1d(const unsigned short* val); extern void e_shortint_unsigned_1d1(const unsigned short* val); extern void e_shortint_unsigned_2d(const unsigned short* val); extern void e_shortint_unsigned_2d1(const unsigned short* val); extern void e_shortint_unsigned_3d(const unsigned short* val); extern void e_shortint_unsigned_3d1(const unsigned short* val); extern void e_string_0d(const char* val); extern void e_string_1d(const char** val); extern void e_string_1d1(const char** val); extern void e_string_2d(const char** val); extern void e_string_2d1(const char** val); extern void e_string_3d(const char** val); extern void e_string_3d1(const char** val); extern void e_time_0d(const svLogicVecVal* val); extern void e_time_1d(const svLogicVecVal* val); extern void e_time_1d1(const svLogicVecVal* val); extern void e_time_2d(const svLogicVecVal* val); extern void e_time_2d1(const svLogicVecVal* val); extern void e_time_3d(const svLogicVecVal* val); extern void e_time_3d1(const svLogicVecVal* val); // DPI IMPORTS extern void check_exports(); extern void* get_non_null(); extern void i_bit121_0d(const svBitVecVal* val); extern void i_bit121_1d(const svBitVecVal* val); extern void i_bit121_1d1(const svBitVecVal* val); extern void i_bit121_2d(const svBitVecVal* val); extern void i_bit121_2d1(const svBitVecVal* val); extern void i_bit121_3d(const svBitVecVal* val); extern void i_bit121_3d1(const svBitVecVal* val); extern void i_bit1_0d(svBit val); extern void i_bit1_1d(const svBit* val); extern void i_bit1_1d1(const svBit* val); extern void i_bit1_2d(const svBit* val); extern void i_bit1_2d1(const svBit* val); extern void i_bit1_3d(const svBit* val); extern void i_bit1_3d1(const svBit* val); extern void i_bit7_0d(const svBitVecVal* val); extern void i_bit7_1d(const svBitVecVal* val); extern void i_bit7_1d1(const svBitVecVal* val); extern void i_bit7_2d(const svBitVecVal* val); extern void i_bit7_2d1(const svBitVecVal* val); extern void i_bit7_3d(const svBitVecVal* val); extern void i_bit7_3d1(const svBitVecVal* val); extern void i_byte_0d(char val); extern void i_byte_1d(const char* val); extern void i_byte_1d1(const char* val); extern void i_byte_2d(const char* val); extern void i_byte_2d1(const char* val); extern void i_byte_3d(const char* val); extern void i_byte_3d1(const char* val); extern void i_byte_unsigned_0d(unsigned char val); extern void i_byte_unsigned_1d(const unsigned char* val); extern void i_byte_unsigned_1d1(const unsigned char* val); extern void i_byte_unsigned_2d(const unsigned char* val); extern void i_byte_unsigned_2d1(const unsigned char* val); extern void i_byte_unsigned_3d(const unsigned char* val); extern void i_byte_unsigned_3d1(const unsigned char* val); extern void i_chandle_0d(void* val); extern void i_chandle_1d(const void** val); extern void i_chandle_1d1(const void** val); extern void i_chandle_2d(const void** val); extern void i_chandle_2d1(const void** val); extern void i_chandle_3d(const void** val); extern void i_chandle_3d1(const void** val); extern void i_int_0d(int val); extern void i_int_1d(const int* val); extern void i_int_1d1(const int* val); extern void i_int_2d(const int* val); extern void i_int_2d1(const int* val); extern void i_int_3d(const int* val); extern void i_int_3d1(const int* val); extern void i_int_unsigned_0d(unsigned int val); extern void i_int_unsigned_1d(const unsigned int* val); extern void i_int_unsigned_1d1(const unsigned int* val); extern void i_int_unsigned_2d(const unsigned int* val); extern void i_int_unsigned_2d1(const unsigned int* val); extern void i_int_unsigned_3d(const unsigned int* val); extern void i_int_unsigned_3d1(const unsigned int* val); extern void i_integer_0d(const svLogicVecVal* val); extern void i_integer_1d(const svLogicVecVal* val); extern void i_integer_1d1(const svLogicVecVal* val); extern void i_integer_2d(const svLogicVecVal* val); extern void i_integer_2d1(const svLogicVecVal* val); extern void i_integer_3d(const svLogicVecVal* val); extern void i_integer_3d1(const svLogicVecVal* val); extern void i_logic121_0d(const svLogicVecVal* val); extern void i_logic121_1d(const svLogicVecVal* val); extern void i_logic121_1d1(const svLogicVecVal* val); extern void i_logic121_2d(const svLogicVecVal* val); extern void i_logic121_2d1(const svLogicVecVal* val); extern void i_logic121_3d(const svLogicVecVal* val); extern void i_logic121_3d1(const svLogicVecVal* val); extern void i_logic1_0d(svLogic val); extern void i_logic1_1d(const svLogic* val); extern void i_logic1_1d1(const svLogic* val); extern void i_logic1_2d(const svLogic* val); extern void i_logic1_2d1(const svLogic* val); extern void i_logic1_3d(const svLogic* val); extern void i_logic1_3d1(const svLogic* val); extern void i_logic7_0d(const svLogicVecVal* val); extern void i_logic7_1d(const svLogicVecVal* val); extern void i_logic7_1d1(const svLogicVecVal* val); extern void i_logic7_2d(const svLogicVecVal* val); extern void i_logic7_2d1(const svLogicVecVal* val); extern void i_logic7_3d(const svLogicVecVal* val); extern void i_logic7_3d1(const svLogicVecVal* val); extern void i_longint_0d(long long val); extern void i_longint_1d(const long long* val); extern void i_longint_1d1(const long long* val); extern void i_longint_2d(const long long* val); extern void i_longint_2d1(const long long* val); extern void i_longint_3d(const long long* val); extern void i_longint_3d1(const long long* val); extern void i_longint_unsigned_0d(unsigned long long val); extern void i_longint_unsigned_1d(const unsigned long long* val); extern void i_longint_unsigned_1d1(const unsigned long long* val); extern void i_longint_unsigned_2d(const unsigned long long* val); extern void i_longint_unsigned_2d1(const unsigned long long* val); extern void i_longint_unsigned_3d(const unsigned long long* val); extern void i_longint_unsigned_3d1(const unsigned long long* val); extern void i_pack_struct_0d(const svLogicVecVal* val); extern void i_pack_struct_1d(const svLogicVecVal* val); extern void i_pack_struct_1d1(const svLogicVecVal* val); extern void i_pack_struct_2d(const svLogicVecVal* val); extern void i_pack_struct_2d1(const svLogicVecVal* val); extern void i_pack_struct_3d(const svLogicVecVal* val); extern void i_pack_struct_3d1(const svLogicVecVal* val); extern void i_real_0d(double val); extern void i_real_1d(const double* val); extern void i_real_1d1(const double* val); extern void i_real_2d(const double* val); extern void i_real_2d1(const double* val); extern void i_real_3d(const double* val); extern void i_real_3d1(const double* val); extern void i_shortint_0d(short val); extern void i_shortint_1d(const short* val); extern void i_shortint_1d1(const short* val); extern void i_shortint_2d(const short* val); extern void i_shortint_2d1(const short* val); extern void i_shortint_3d(const short* val); extern void i_shortint_3d1(const short* val); extern void i_shortint_unsigned_0d(unsigned short val); extern void i_shortint_unsigned_1d(const unsigned short* val); extern void i_shortint_unsigned_1d1(const unsigned short* val); extern void i_shortint_unsigned_2d(const unsigned short* val); extern void i_shortint_unsigned_2d1(const unsigned short* val); extern void i_shortint_unsigned_3d(const unsigned short* val); extern void i_shortint_unsigned_3d1(const unsigned short* val); extern void i_string_0d(const char* val); extern void i_string_1d(const char** val); extern void i_string_1d1(const char** val); extern void i_string_2d(const char** val); extern void i_string_2d1(const char** val); extern void i_string_3d(const char** val); extern void i_string_3d1(const char** val); extern void i_time_0d(const svLogicVecVal* val); extern void i_time_1d(const svLogicVecVal* val); extern void i_time_1d1(const svLogicVecVal* val); extern void i_time_2d(const svLogicVecVal* val); extern void i_time_2d1(const svLogicVecVal* val); extern void i_time_3d(const svLogicVecVal* val); extern void i_time_3d1(const svLogicVecVal* val); #ifdef __cplusplus } #endif #endif // guard verilator-5.042/test_regress/t/t_static_function_in_class_call_without_parentheses.v0000644000542200017500000000126715101701376032034 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class Foo; static int m_v; static function void set_v(int v); m_v = v; endfunction static function int get_v(); // Let's see if referring to the implicit variable does not resolve into a call get_v = m_v; endfunction endclass module t(); initial begin int v; Foo::set_v(3); // Check if a parenthesesless call to static method works v = Foo::get_v; if (v != 3) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_randcase_bad.out0000644000542200017500000000022715101701376022531 0ustar mahmoudyfreeshell[0] %Error: t_randcase_bad.v:12: Assertion failed in top.t.unnamedblk2_1: All randcase items had 0 weights (IEEE 1800-2023 18.16) *-* All Finished *-* verilator-5.042/test_regress/t/t_class_nested.v0000644000542200017500000000355315101701376022255 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class NodeList; class Node; string name; Node link; function new(); name = "node"; endfunction endclass Node head; endclass class NodeTree; class Node; int id; Node link; endclass Node root; endclass // Based on IEEE 1800-2017 section 8.23 Nested classes class Outer; int outerProp; local int outerLocalProp; static int outerStaticProp; static local int outerLocalStaticProp; class Inner; function void innerMethod(Outer h); outerStaticProp = 1; outerLocalStaticProp = 1; h.outerProp = 1; h.outerLocalProp = 1; endfunction endclass endclass module t; initial begin NodeList n = new; NodeList::Node n1 = new; NodeList::Node n2 = new; NodeTree tr = new; NodeTree::Node t1 = new; NodeTree::Node t2 = new; Outer o = new; Outer::Inner i = new; i.innerMethod(o); if(o.outerProp != 1) $stop; if(Outer::outerStaticProp != 1) $stop; if (n1.name != "node") $stop; n1.name = "n1"; if (n1.name != "n1") $stop; n2.name = "n2"; if (n2.name != "n2") $stop; n.head = n1; n1.link = n2; if (n.head.name != "n1") $stop; if (n.head.link.name != "n2") $stop; t1.id = 1; if (t1.id != 1) $stop; t2.id = 2; if (t2.id != 2) $stop; tr.root = t1; t1.link = t2; if (tr.root.id != 1) $stop; if (tr.root.link.id != 2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_multitop_sig.py0000755000542200017500000000161115101701376022504 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(make_top_shell=False, make_main=False, verilator_flags2=["-Wno-MULTITOP --exe", test.pli_filename]) test.execute() test.file_grep(test.run_log_filename, r"In 'a'") test.file_grep(test.run_log_filename, r"In 'a.sub'") test.file_grep(test.run_log_filename, r"In 'b'") test.file_grep(test.run_log_filename, r"In 'b.sub'") test.file_grep(test.run_log_filename, r"In 'c'") test.file_grep(test.run_log_filename, r"In 'c.sub'") test.passes() verilator-5.042/test_regress/t/t_interface_size_bad.v0000644000542200017500000000072415101701376023403 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Demonstrate deferred linking error messages // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Johan Bjork. // SPDX-License-Identifier: CC0-1.0 interface foo_intf; logic a; endinterface module t; localparam N = 4; foo_intf foo4 [N-1:0] (); foo_intf foo6 [5:0] (); baz baz4_inst (.foo(foo4)); baz baz6_inst (.foo(foo6)); endmodule module baz(foo_intf foo[4:0] ); endmodule verilator-5.042/test_regress/t/t_param_type_bad.py0000755000542200017500000000111015101701376022726 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint( # Bug1575 required trace to crash verilator_flags2=["--trace-vcd"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_udp_bad_input_num.v0000755000542200017500000000103015101701376023271 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 primitive t_gate(dout, a, b, c); output dout; input a, b, c; table x 0 1 : 1; 0 ? 1 : 1; 1 0 : 0; 1 1 ? : 1; 1 0 0 : 0; 0 0 0 : 1; endtable endprimitive module top (a, b, c, o); input a, b, c; output o; t_gate(o, a, b, c); endmodule verilator-5.042/test_regress/t/t_cast_types.v0000644000542200017500000000671615101701376021770 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define TRY_ASSIGN(a,b) a = b `define TRY_CAST(a,b) a = type(a)'(b) `ifdef VERILATOR `define TRY_DYNAMIC(a,b) // UNSUP $cast `define TRY_BAD(a,b) // UNSUP $cast `else `define TRY_DYNAMIC(a,b) if (1 != $cast(a, b)) $stop `define TRY_BAD(a,b) if (0 != $cast(a, b)) $stop `endif `define MATCHING(a,b) `TRY_ASSIGN(a,b) `define EQUIVALENT(a,b) `TRY_ASSIGN(a,b) `define COMPATIBLE(a,b) `TRY_ASSIGN(a,b) `define CAST_COMPATIBLE(a,b) `TRY_CAST(a,b) `define CAST_COMPATIBLE_ENUM(a,b) `TRY_CAST(a,b) `define CAST_COMPATIBLE_DYNAMIC(a,b) `TRY_DYNAMIC(a,b) `define INCOMPATIBLE(a,b) `TRY_BAD(a,b) `define STRING_LITERAL "literal" // IEEE 5.9 - to packed or unpacked per IEEE 6.24 class Base; endclass class BaseExtended extends Base; endclass class Other; endclass typedef enum { A_ZERO, A_ONE } Enum_A_t; typedef enum { B_ZERO, B_ONE } Enum_B_t; typedef int int_t; typedef struct packed { int a; int b; } stpack_t; typedef bit signed [7:0] simple_a_t; typedef bit signed [7:0] simple_a1_t; module t; real v_real; // IEEE 6.12.2 - by rounding string v_string; int v_int; int_t v_int_t; chandle v_chandle; Enum_A_t v_enum_a; Enum_A_t v_enum_a1; Enum_B_t v_enum_b; stpack_t v_stpack_a; stpack_t v_stpack_a1; simple_a_t v_simple_a; simple_a1_t v_simple_a1; int v_unpk_a[2][3]; int v_unpk_a1[2][3]; int v_assoc_a[string]; int v_assoc_a1[string]; int v_assoc_b[int]; int v_assoc_c[bit[31:0]]; int v_q_a[$]; int v_q_a1[$]; real v_q_b[$]; bit [3:0][7:0] v_2thirtytwo_a; bit [3:0][7:0] v_2thirtytwo_b; logic [3:0][7:0] v_4thirtytwo_a; logic [3:0][7:0] v_4thirtytwo_b; Base v_cls_a; Base v_cls_a1; BaseExtended v_cls_ab; Other v_cls_b; // verilator lint_off REALCVT initial begin // 6.22.1 `MATCHING(v_real, v_real); `MATCHING(v_string, v_string); `MATCHING(v_int, v_int); `MATCHING(v_chandle, v_chandle); `MATCHING(v_int, v_int_t); `MATCHING(v_stpack_a, v_stpack_a1); `MATCHING(v_simple_a, v_simple_a1); `MATCHING(v_unpk_a, v_unpk_a1); `MATCHING(v_assoc_a, v_assoc_a1); `MATCHING(v_q_a, v_q_a1); `MATCHING(v_int, v_2thirtytwo_a); `MATCHING(v_cls_a, v_cls_a1); `MATCHING(v_cls_a, v_cls_ab); // 6.22.2 `EQUIVALENT(v_int, v_2thirtytwo_a); `ifndef NC `ifndef VCS `EQUIVALENT(v_assoc_b, v_assoc_c); // Spec says equivalent, but simulators disagree `endif `endif // 6.22.3 `COMPATIBLE(v_string, `STRING_LITERAL); `COMPATIBLE(v_int, v_enum_a); `COMPATIBLE(v_int, v_real); `COMPATIBLE(v_real, v_int); // 6.22.4->5.9 `ifndef NC `CAST_COMPATIBLE(v_string, v_int); `endif // 6.22.4->6.19.3 `ifndef NC `CAST_COMPATIBLE_ENUM(v_enum_a, v_int); `CAST_COMPATIBLE_ENUM(v_enum_a, v_enum_b); `endif `CAST_COMPATIBLE_DYNAMIC(v_cls_ab, v_cls_a); // 6.22.5 incompatible `INCOMPATIBLE(v_cls_ab, v_int); `ifndef VCS `INCOMPATIBLE(v_real, v_assoc_a); `INCOMPATIBLE(v_real, v_q_a); `endif `ifndef VCS `ifndef VERILATOR `INCOMPATIBLE(v_chandle, v_int); `endif `endif `ifndef NC `INCOMPATIBLE(v_cls_a, v_cls_b); `endif $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_param_circ_bad.v0000644000542200017500000000047615101701376022515 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; sub sub (); endmodule module sub #(parameter WIDTH=X, parameter X=WIDTH) (); endmodule verilator-5.042/test_regress/t/t_type_non_type.py0000755000542200017500000000073415101701376022666 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_extern_bad.py0000755000542200017500000000076615101701376023277 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_param_public.v0000644000542200017500000000151615101701376022241 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 //bug505 module t; parameter TOP_PARAM /*verilator public*/ = 20; a #(1) a1 (); b #(2) b2 (); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule module a; parameter ONE /*verilator public*/ = 22; initial if (ONE != 1) $stop; `ifdef VERILATOR initial if ($c32("this->ONE") != 1) $stop; `endif endmodule module b #( parameter TWO /*verilator public*/ = 22 ); initial if (TWO != 2) $stop; `ifdef VERILATOR initial if ($c32("this->TWO") != 2) $stop; `endif endmodule //bug804 package p; localparam INPACK /*verilator public*/ = 6; endpackage verilator-5.042/test_regress/t/t_scheduling_1.v0000644000542200017500000000221015101701376022140 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2022 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module top( clk ); input clk; // Generate half speed 'clk_half', via blocking assignment reg clk_half = 0; always @(posedge clk) clk_half = ~clk_half; // Cycle count (+ stop condition) reg [31:0] cyc = 0; always @(posedge clk) begin cyc <= cyc + 1; if (cyc == 100) begin $write("*-* All Finished *-*\n"); $finish; end end // Flop cycle count via `clk` reg [31:0] a = 0; always @(posedge clk) a <= cyc; // Flop cycle count via `clk_half`, on both edges reg [31:0] b = 0; always @(posedge clk_half or negedge clk_half) b <= cyc; // `a` should always equal `b`, no mater which value they actually capture always @(posedge clk) begin if (a !== b) begin $display("tick %d: a is %x, b is %x", cyc, a, b); $stop; end end endmodule verilator-5.042/test_regress/t/t_struct_portsel.v0000644000542200017500000000462415101701376022702 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [19:0] in = crc[19:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [19:0] out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out (out[19:0]), // Inputs .in (in[19:0])); // Aggregate outputs into a single result vector wire [63:0] result = {44'h0, out}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'hdb7bc61592f31b99 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule typedef struct packed { logic [7:0] cn; logic vbfval; logic vabval; } rel_t; module Test (/*AUTOARG*/ // Outputs out, // Inputs in ); input [19:0] in; output [19:0] out; rel_t [1:0] i; // From ifb0 of ifb.v, ... rel_t [1:0] o; // From ifb0 of ifb.v, ... assign i = in; assign out = o; sub sub ( .i (i[1:0]), .o (o[1:0])); endmodule module sub (/*AUTOARG*/ // Outputs o, // Inputs i ); input rel_t [1:0] i; output rel_t [1:0] o; assign o = i; endmodule // Local Variables: // verilog-typedef-regexp: "_t$" // End: verilator-5.042/test_regress/t/t_interface_array2_coverage.py0000755000542200017500000000107315101701376025062 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_array2.v" test.compile(timing_loop=True, v_flags2=["--coverage --timing"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_select_sideeffect.v0000644000542200017500000000124715101701376023244 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Foo; bit [2:0] x = 0; function int get(); x += 1; return int'(x); endfunction function bit [2:0] get2(); x += 1; return x; endfunction endclass module t; Foo foo; int x[5] = {1, 2, 3, 4, 5}; initial begin foo = new; if (x[foo.get()] != 2) $stop; $write("*-* All Finished *-*\n"); $finish; end always begin if (x[foo.get2()] != 3) $stop; end final begin if (x[foo.get()] != 4) $stop; end endmodule verilator-5.042/test_regress/t/t_implements_notfound_bad.out0000644000542200017500000000044715101701376025046 0ustar mahmoudyfreeshell%Error: t/t_implements_notfound_bad.v:7:23: Class for 'implements' not found: 'Inotfound' 7 | class ClsI implements Inotfound; | ^~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_cover_toggle_min.v0000644000542200017500000000111315101701376023116 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2024 by Antmicro. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t(); logic[1:0] a; logic[1:0] b; logic[1:0] c; initial begin #1 a = 2'b01; #1 b = 2'b10; #1 c = 2'b11; #1 c = 2'b10; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_runflag_errorlimit_bad.v0000644000542200017500000000064615101701376024322 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin $error("One"); $error("Two"); $error("Three"); $error("Four"); $error("Five"); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_clocking_concat.py0000755000542200017500000000073415101701376023112 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_vams_basic.py0000755000542200017500000000073415101701376022101 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_dtype_compare_bad.py0000755000542200017500000000076615101701376024466 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_vpi_public_depth.py0000755000542200017500000000153015101701376023305 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(make_top_shell=False, make_main=False, make_pli=True, iv_flags2=["-g2005-sv"], verilator_flags2=[ "+define+USE_DOLLAR_C32 --exe --vpi --no-l2name", test.pli_filename, "--public-depth 3" ], make_flags=['CPPFLAGS_ADD=-DTEST_VPI_PUBLIC_DEPTH']) test.execute(use_libvpi=True, v_flags2=[]) test.passes() verilator-5.042/test_regress/t/t_timing_clkgen1.v0000644000542200017500000000162015101701376022472 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module clkgen(output bit clk); initial begin #(8.0:5:3) clk = 1; // Middle is default forever begin #5 clk = ~clk; end end endmodule module t; wire logic clk; clkgen clkgen (.clk); int cyc; always @ (posedge clk) begin cyc <= cyc + 1; `ifdef TEST_VERBOSE $display("[%0t] cyc=%0d", $time, cyc); `endif if (cyc == 0) begin if ($time != 5) $stop; end else if (cyc == 1) begin if ($time != 15) $stop; end else if (cyc == 2) begin if ($time != 25) $stop; end else if (cyc == 9) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_class_null_bad.out0000644000542200017500000000010715101701376023105 0ustar mahmoudyfreeshell%Error: t/t_class_null_bad.v:15: Null pointer dereferenced Aborting... verilator-5.042/test_regress/t/t_opt_const_cov.v0000644000542200017500000000502615101701376022462 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [32:0] in = crc[32:0]; logic bank_rd_vec_m3; always_ff @(posedge clk) bank_rd_vec_m3 <= crc[33]; logic [3:0][31:0] data_i; wire [3:0] out; for (genvar i = 0; i < 4; ++i) begin always_ff @(posedge clk) data_i[i] <= crc[63:32]; ecc_check_pipe u_bank_data_ecc_check( .clk (clk), .bank_rd_m3 (bank_rd_vec_m3), .data_i ({1'b0, data_i[i]}), .ecc_err_o (out[i]) ); end // Aggregate outputs into a single result vector wire [63:0] result = {60'b0, out}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc == 0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc < 10) begin sum <= '0; end else if (cyc == 99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'ha2601675a6ae4972 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module ecc_check_pipe ( input logic clk, input logic bank_rd_m3, input logic [32:0] data_i, output logic ecc_err_o ); logic [3:0] check_group_6_0; logic check_group_6_0_q; always_comb check_group_6_0 = {data_i[0], data_i[2], data_i[4], data_i[7] }; always_ff @(posedge clk) if (bank_rd_m3) check_group_6_0_q <=^check_group_6_0; assign ecc_err_o = check_group_6_0_q; endmodule verilator-5.042/test_regress/t/t_wide_temp_while_cond.py0000755000542200017500000000124015101701376024133 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary", "--stats", "t/t_wide_temp_while_cond.cpp"]) if test.vlt or test.vltmt: test.file_grep(test.stats, r'Optimizations, Prelim temporary variables created\s+(\d+)', 3) test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_input_eq_good.v0000644000542200017500000000047015101701376023463 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( input wire i, input wire i2 = i // Good under IEEE 1800-2009 ); endmodule verilator-5.042/test_regress/t/t_lint_iface_array_topmodule1.py0000755000542200017500000000070615101701376025435 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.042/test_regress/t/t_assert_sampled.v0000644000542200017500000000347215101701376022614 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [3:0] a, b; Test1 t1(clk, a, b); Test2 t2(clk, a, b); Test3 t3(clk, a, b); initial begin a = 0; b = 0; end always @(posedge clk) begin a <= a + 1; b = b + 1; $display("a = %0d, b = %0d, %0d == %0d", a, b, $sampled(a), $sampled(b)); if (b >= 10) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test1( clk, a, b ); input clk; input [3:0] a, b; assert property (@(posedge clk) $sampled(a) == $sampled(b)); endmodule module Test2( clk, a, b ); input clk; input [3:0] a, b; assert property (@(posedge clk) a == b); endmodule module Test3( clk, a, b ); input clk; input [3:0] a, b; int hits[10]; assert property (@(posedge clk) a == b) hits[1]=1; assert property (@(posedge clk) a == b) else hits[2]=1; assert property (@(posedge clk) a == b) hits[3]=1; else hits[4]=1; assert property (@(posedge clk) a != b) hits[5]=1; assert property (@(posedge clk) a != b) else hits[6]=1; assert property (@(posedge clk) a != b) hits[7]=1; else hits[8]=1; final begin `checkd(hits[1], 1); `checkd(hits[2], 0); `checkd(hits[3], 1); `checkd(hits[4], 0); `checkd(hits[5], 0); `checkd(hits[6], 1); `checkd(hits[7], 0); `checkd(hits[8], 1); end endmodule verilator-5.042/test_regress/t/t_struct_notfound_bad.out0000644000542200017500000000051015101701376024204 0ustar mahmoudyfreeshell%Error: t/t_struct_notfound_bad.v:13:9: Member 'nfmember' not found in structure : ... note: In instance 't' 13 | s.nfmember = 0; | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_assert_future_unsup.v0000644000542200017500000000073715101701376023734 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ // Inputs a, clk ); input a; input clk; function logic func(input logic i); return i; endfunction global clocking @(posedge clk); endclocking assert property (@(posedge clk) $future_gclk(a) == func(a)); endmodule verilator-5.042/test_regress/t/t_inside.py0000755000542200017500000000073415101701376021245 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_flag_f_bad.py0000755000542200017500000000110315101701376022005 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--lint-only -f file_will_not_exist.vc"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_param_bracket.py0000755000542200017500000000070615101701376022564 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.042/test_regress/t/t_unpack_array_no_expand.v0000644000542200017500000000177115101701376024320 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( output logic [255:0] data_out ); localparam int NUM_STAGES = 3; /* verilator lint_off ALWCOMBORDER */ /* verilator lint_off UNOPTFLAT */ `define INPUT 256'hbabecafe logic [255:0] stage_data [NUM_STAGES+1]; genvar stage; generate always_comb begin stage_data[0] = `INPUT; end for (stage = 0; stage < NUM_STAGES; ++stage) begin : stage_gen always_comb begin stage_data[stage+1] = stage_data[stage]; end end endgenerate /* verilator lint_on UNOPTFLAT */ /* verilator lint_on ALWCOMBORDER */ always_comb begin data_out = stage_data[NUM_STAGES]; if (data_out !== `INPUT) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_lint_restore_bad.v0000644000542200017500000000066415101701376023125 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (); reg [3:0] four; reg [4:0] five; // verilator lint_save // verilator lint_off WIDTH initial four = 64'h1; // verilator lint_restore initial five = 64'h1; initial $stop; endmodule verilator-5.042/test_regress/t/t_param_first_a.v0000644000542200017500000000147515101701376022416 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t_param_first_a (/*AUTOARG*/ // Outputs varwidth, par ); parameter X = 1; parameter FIVE = 0; // Overridden parameter TWO = 2; /*AUTOOUTPUT*/ // Beginning of automatic outputs (from unused autoinst outputs) output [4:0] par; // From b of t_param_first_b.v output [X:0] varwidth; // From b of t_param_first_b.v // End of automatics t_param_first_b #(X,FIVE,TWO) b (/*AUTOINST*/ // Outputs .par (par[4:0]), .varwidth (varwidth[X:0])); endmodule verilator-5.042/test_regress/t/t_dpi_var.vlt0000644000542200017500000000120515101701376021562 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. // SPDX-License-Identifier: CC0-1.0 `verilator_config sformat -task "mon_scope_name" -var "formatted" public_flat_rd -module "sub" -var "in" public_flat_rw -module "sub" -var "in_a" public_flat_rw -module "sub" -var "in_b" @(posedge t.monclk) public_flat_rw -module "sub" -var "fr_a" public_flat_rw -module "sub" -var "fr_b" @(posedge t.monclk) // Cover other edge declarations public_flat_rw -module "sub" -var "fr_chk" @(posedge t.monclk or negedge t.monclk or edge t.monclk) verilator-5.042/test_regress/t/t_tri_inout.py0000755000542200017500000000105615101701376022004 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_fst_cmake.py0000755000542200017500000000115015101701376023075 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(v_flags2=["--trace-fst"], verilator_make_gmake=False, verilator_make_cmake=True) test.execute() test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_typedef_param_class.py0000755000542200017500000000073415101701376023777 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_config_libmap.py0000755000542200017500000000111715101701376022557 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["--lint-only", "t/" + test.name + ".map"], fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_param_extra_bad.out0000644000542200017500000000133115101701376024436 0ustar mahmoudyfreeshell%Error-PINNOTFOUND: t/t_class_param_extra_bad.v:13:21: Parameter not found: '__paramNumber1' 13 | localparam Cls1#(123, integer, "text")::bool_t PARAM = 1; | ^~~ ... For error description see https://verilator.org/warn/PINNOTFOUND?v=latest %Error-PINNOTFOUND: t/t_class_param_extra_bad.v:13:26: Parameter not found: '__paramNumber2' 13 | localparam Cls1#(123, integer, "text")::bool_t PARAM = 1; | ^~~~~~~ %Error-PINNOTFOUND: t/t_class_param_extra_bad.v:13:35: Parameter not found: '__paramNumber3' 13 | localparam Cls1#(123, integer, "text")::bool_t PARAM = 1; | ^~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_flag_x_assign_bad.out0000644000542200017500000000034015101701376023551 0ustar mahmoudyfreeshell%Error: Unknown setting for --x-assign: 'bad_one' ... Suggest '0', '1', 'fast', or 'unique' ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_trace_max_default.out0000644000542200017500000000605015101701376023612 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $var wire 1 O clk $end $scope module t $end $var wire 1 O clk $end $var wire 32 # cyc [31:0] $end $var wire 96 $ wide1 [95:0] $end $var wire 16 ' wide2[0] [15:0] $end $var wire 16 ( wide2[1] [15:0] $end $var wire 16 ) wide2[2] [15:0] $end $var wire 16 * wide2[3] [15:0] $end $var wire 16 + wide2[4] [15:0] $end $var wire 16 , wide2[5] [15:0] $end $var wire 16 - wide2[6] [15:0] $end $var wire 16 . wide2[7] [15:0] $end $var wire 16 / wide2[8] [15:0] $end $var wire 16 0 wide2[9] [15:0] $end $var wire 16 1 wide2[10] [15:0] $end $var wire 16 2 wide2[11] [15:0] $end $var wire 16 3 wide2[12] [15:0] $end $var wire 16 4 wide2[13] [15:0] $end $var wire 16 5 wide2[14] [15:0] $end $var wire 16 6 wide2[15] [15:0] $end $var wire 1 7 deep1[0] $end $var wire 1 8 deep1[1] $end $var wire 1 9 deep1[2] $end $var wire 1 : deep1[3] $end $var wire 1 ; deep1[4] $end $var wire 1 < deep1[5] $end $var wire 1 = deep1[6] $end $var wire 1 > deep1[7] $end $var wire 1 ? deep1[8] $end $var wire 1 @ deep1[9] $end $var wire 1 A deep1[10] $end $var wire 1 B deep1[11] $end $var wire 1 C deep1[12] $end $var wire 1 D deep1[13] $end $var wire 1 E deep1[14] $end $var wire 1 F deep1[15] $end $var wire 1 G deep1[16] $end $var wire 1 H deep1[17] $end $var wire 1 I deep1[18] $end $var wire 1 J deep1[19] $end $var wire 1 K deep1[20] $end $var wire 1 L deep1[21] $end $var wire 1 M deep1[22] $end $var wire 1 N deep1[23] $end $upscope $end $upscope $end $enddefinitions $end #0 b00000000000000000000000000000000 # b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $ b0000000000000000 ' b0000000000000000 ( b0000000000000000 ) b0000000000000000 * b0000000000000000 + b0000000000000000 , b0000000000000000 - b0000000000000000 . b0000000000000000 / b0000000000000000 0 b0000000000000000 1 b0000000000000000 2 b0000000000000000 3 b0000000000000000 4 b0000000000000000 5 b0000000000000000 6 07 08 09 0: 0; 0< 0= 0> 0? 0@ 0A 0B 0C 0D 0E 0F 0G 0H 0I 0J 0K 0L 0M 0N 0O #10 b00000000000000000000000000000001 # 1O #15 0O #20 b00000000000000000000000000000010 # b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 $ b0000000000000001 ) 1: 1O #25 0O #30 b00000000000000000000000000000011 # b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 $ b0000000000000010 ) 0: 1O #35 0O #40 b00000000000000000000000000000100 # b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 $ b0000000000000011 ) 1: 1O #45 0O #50 b00000000000000000000000000000101 # b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 $ b0000000000000100 ) 0: 1O #55 0O #60 b00000000000000000000000000000110 # b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 $ b0000000000000101 ) 1: 1O verilator-5.042/test_regress/t/t_opt_merge_cond_motion_branch.py0000755000542200017500000000073415101701376025660 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_runflag.v0000644000542200017500000000047115101701376021240 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_enum_type_methods_bad.py0000755000542200017500000000076615101701376024335 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_package_param.v0000644000542200017500000000150315101701376022352 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // IEEE 1800-2009 requires that any local definitions take precedence over // definitions in wildcard imported packages (section 26.3). Thus the code // below is valid SystemVerilog. // // This file ONLY is placed into the Public Domain, for any use, without // warranty, 2013 by Jie Xu. // SPDX-License-Identifier: CC0-1.0 package defs; parameter NUMBER = 8; localparam NUM = NUMBER; endpackage module t(/*AUTOARG*/ // Inputs clk ); input clk; import defs::*; // This also fails if we use localparam parameter NUM = 32; // Check we have the right definition always @(posedge clk) begin if (NUM == 32) begin $write("*-* All Finished *-*\n"); $finish; end else begin $stop; end end endmodule verilator-5.042/test_regress/t/t_time_sc_fs.out0000644000542200017500000000013015101701376022247 0ustar mahmoudyfreeshellTime scale of t is 1fs / 1fs [20] In top.t: Hi - expect this is 20 *-* All Finished *-* verilator-5.042/test_regress/t/t_func_recurse_param_bad.v0000644000542200017500000000105415101701376024251 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; function automatic int recurse_self; input int i; if (i == 0) recurse_self = 0; else recurse_self = i + recurse_self(i - 1) * 2; endfunction localparam int HUGE = recurse_self(10000); // too much recursion initial begin $display(HUGE); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_dpi_display.py0000755000542200017500000000104215101701376022264 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=["t/t_dpi_display_c.cpp"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_func_static_bad.out0000644000542200017500000000130615101701376024437 0ustar mahmoudyfreeshell%Error: t/t_class_func_static_bad.v:10:17: Class function/task cannot be static lifetime ('task static') (IEEE 1800-2023 6.21) : ... May have intended 'static task' 10 | task static task_st(int x); | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_class_func_static_bad.v:14:25: Class function/task cannot be static lifetime ('function static') (IEEE 1800-2023 6.21) : ... May have intended 'static function' 14 | function static int func_st(int x); | ^~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_udp_tableend_bad.out0000644000542200017500000000037015101701376023376 0ustar mahmoudyfreeshell%Error: t/t_udp_tableend_bad.v:11:4: Syntax error: 'endtable' outside of 'table' 11 | endtable | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_module_input_default_value_1_bad.py0000755000542200017500000000076615101701376026431 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_param_type4_collision.py0000755000542200017500000000105215101701376024264 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_param_type4.v" test.compile(verilator_flags2=["--debug-collision"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_flag_f_bad_getenvend.out0000644000542200017500000000027015101701376024224 0ustar mahmoudyfreeshell%Error: Unmatched brackets in variable substitution in file: $(GETENV_NO_END_PAREN ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. verilator-5.042/test_regress/t/t_vpi_dump.v0000644000542200017500000000563315101701376021432 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2010 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 /* verilator public_on */ typedef struct packed { logic [3:0][7:0] adr; // address logic [3:0][7:0] dat; // data int sel; // select } t_bus; interface TestInterface(); logic [31:0] addr; modport source (input addr); endinterface module t ( /*AUTOARG*/ // Outputs x, // Inputs clk, a ); parameter int DO_GENERATE = 1; parameter longint LONG_INT = 64'h123456789abcdef; input clk; input [7:0] a; output reg [7:0] x; reg onebit; reg [2:1] twoone; reg [2:1] fourthreetwoone[4:3]; reg LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND ; // verilator lint_off ASCRANGE reg [0:61] quads[2:3]; // verilator lint_on ASCRANGE reg [31:0] count; reg [31:0] half_count; reg [7:0] text_byte; reg [15:0] text_half; reg [31:0] text_word; reg [63:0] text_long; reg [511:0] text; integer status; real real1; string str1; t_bus bus1; ModSub sub (); TestInterface intf_arr[2](); initial begin $write("*-* All Finished *-*\n"); $finish(); end genvar i; generate for (i = 1; i <= 2; i = i + 1) begin : arr ModArr #(.LENGTH(i)) arr (); end for (i = 1; i <= 3; i = i + 1) begin : outer_scope parameter int scoped_param = i * 2; genvar j; for (j = 1; j <= 3; j = j + 1) begin : inner_scope parameter int scoped_param_inner = scoped_param + 1; ModArr #(.LENGTH(scoped_param_inner)) arr (); end end endgenerate ModSubWrapper sub_wrap (); generate if (DO_GENERATE == 1) begin : cond_scope ModSub scoped_sub (); parameter int scoped_wire = 1; ModSubWrapper sub_wrap_gen (); end else begin : cond_scope_else ModSub scoped_sub_else (); end endgenerate endmodule : t module ModSub; reg subsig1; reg subsig2; `ifdef IVERILOG // stop icarus optimizing signals away wire redundant = subsig1 | subsig2; `endif endmodule : ModSub module ModArr; parameter LENGTH = 1; reg [LENGTH-1:0] sig; reg [LENGTH-1:0] rfr; reg check; reg verbose; initial begin sig = {LENGTH{1'b0}}; rfr = {LENGTH{1'b0}}; end always @(posedge check) begin if (verbose) $display("%m : %x %x", sig, rfr); if (check && sig != rfr) $stop; check <= 0; end endmodule : ModArr module ModSubWrapper; ModSub my_sub (); endmodule verilator-5.042/test_regress/t/t_enum_bad_circdecl.py0000755000542200017500000000107515101701376023373 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["--lint-only -Wwarn-VARHIDDEN"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_timescale_lint_bad.py0000755000542200017500000000110315101701376023563 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.top_filename = "t/t_timescale_lint.v" test.lint(verilator_flags2=["--lint-only"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_clocking_bad4.py0000755000542200017500000000102515101701376022447 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["--timing"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_savable_class_bad.out0000644000542200017500000000026515101701376023555 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: Unsupported: --savable with dynamic new ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_covergroup_unsup.v0000644000542200017500000001146115101701376023230 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; logic rst; int a; int b; logic c; int cyc = 0; always @(posedge clk) begin cyc <= cyc + 1; end function automatic void funca(); endfunction function automatic void funcb(); endfunction // NOTE this grammar hasn't been checked with other simulators, // is here just to avoid uncovered code lines in the grammar. covergroup cg_empty; endgroup covergroup cg_opt; type_option.weight = 1; // cg, cp, cross type_option.goal = 99; // cg, cp, cross type_option.comment = "type_option_comment"; // cg, cp, cross type_option.strobe = 0; // cg type_option.merge_instances = 1; // cg type_option.distribute_first = 1; // cg option.name = "the_name"; // cg option.weight = 1; // cg, cp, cross option.goal = 98; // cg, cp, cross option.comment = "option_comment"; // cg, cp, cross option.at_least = 20; // cg, cp, cross option.auto_bin_max = 10; // cg, cp option.cross_num_print_missing = 2; // cg, cross option.detect_overlap = 1; // cg, cp option.per_instance = 1; // cg option.get_inst_coverage = 1; // cg endgroup covergroup cg_clockingevent() @(posedge clk); endgroup covergroup cg_withfunction() with function sample (a); endgroup covergroup cg_atat() @@ (begin funca or end funcb); endgroup covergroup cg_bracket; {} endgroup covergroup cg_bracket2; { option.name = "option"; } endgroup covergroup cg_cp; coverpoint a; endgroup covergroup cg_cp_iff; coverpoint a iff (b); endgroup covergroup cg_id_cp_iff; id: coverpoint a iff (b); endgroup covergroup cg_id_cp_id1; int id: coverpoint a iff (b); endgroup covergroup cg_id_cp_id2; var int id: coverpoint a iff (b); endgroup covergroup cg_id_cp_id3; var [3:0] id: coverpoint a iff (b); endgroup covergroup cg_id_cp_id4; [3:0] id: coverpoint a iff (b); endgroup covergroup cg_id_cp_id5; signed id: coverpoint a iff (b); endgroup covergroup cg_cross; cross a, b iff (!rst); endgroup covergroup cg_cross2; cross a, b iff (!rst) {} endgroup covergroup cg_cross3; cross a, b { option.comment = "cross"; option.weight = 12; } endgroup covergroup cg_cross4; cross a, b { function void crossfunc; endfunction bins one = crossfunc(); } endgroup covergroup cg_cross_id; my_cg_id: cross a, b iff (!rst); endgroup covergroup cg_binsoroptions_bk1; // bins_keyword id/*bin_identifier*/ bins_orBraE '=' '{' open_range_list '}' iffE { bins ba = {a}; } { bins bar = {a} iff (!rst); } { illegal_bins ila = {a}; } { ignore_bins iga = {a}; } { bins ba[] = {a}; } { bins ba[2] = {a}; } { bins ba = {a} with { b }; } { wildcard bins bwa = {a}; } { wildcard bins bwaw = {a} with { b }; } { bins def = default; } { bins defs = default sequence; } { bins bts = ( 1, 2 ); } { wildcard bins wbts = ( 1, 2 ); } { bins bts2 = ( 2, 3 ), ( [5:6] ), ( [5 +/- 2] ), ( [ 5 +%- 20.0] ) ; } { bins bts2 = ( 1,5 => 6,7 ) ; } { bins bts2 = ( 3 [*5] ) ; } { bins bts2 = ( 3 [*5:6] ) ; } { bins bts2 = ( 3 [->5] ) ; } { bins bts2 = ( 3 [->5:6] ) ; } { bins bts2 = ( 3 [=5] ) ; } { bins bts2 = ( 3 [=5:6] ) ; } endgroup covergroup cg_cross_bins; cross a, b { bins bin_a = binsof(a); bins bin_ai = binsof(a) iff (!rst); bins bin_c = binsof(cp.x); bins bin_na = ! binsof(a); bins bin_d = binsof(a) intersect { b }; bins bin_nd = ! binsof(a) intersect { b }; bins bin_e = with (a); bins bin_not_e = ! with (a); bins bin_par = (binsof(a)); bins bin_and = binsof(a) && binsof(b); bins bin_or = binsof(a) || binsof(b); } endgroup covergroup cgArgs(int cg_lim); endgroup class CgCls; int m_x; int m_y; int m_z; covergroup cov1 @m_z; coverpoint m_x; coverpoint m_y; endgroup `ifndef T_COVERGROUP_UNSUP_IGN function new(); cov1 = new; endfunction `endif endclass class CgEmb; covergroup extends cg_empty; endgroup endclass initial begin cg_empty cov1 = new; `ifndef T_COVERGROUP_UNSUP_IGN cgArgs cov2 = new(2); `endif end always @(posedge clk) begin if (cyc == 10) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_interface_virtual_timing.py0000755000542200017500000000103515101701376025042 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_tri_pull01.v0000644000542200017500000000415115101701376021574 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Test: tri t; bufif1 (t, crc[1], cyc[1:0]==2'b00); bufif1 (t, crc[2], cyc[1:0]==2'b10); tri0 t0; bufif1 (t0, crc[1], cyc[1:0]==2'b00); bufif1 (t0, crc[2], cyc[1:0]==2'b10); tri1 t1; bufif1 (t1, crc[1], cyc[1:0]==2'b00); bufif1 (t1, crc[2], cyc[1:0]==2'b10); tri t2; t_tri2 t_tri2 (.t2, .d(crc[1]), .oe(cyc[1:0]==2'b00)); bufif1 (t2, crc[2], cyc[1:0]==2'b10); tri t3; t_tri3 t_tri3 (.t3, .d(crc[1]), .oe(cyc[1:0]==2'b00)); bufif1 (t3, crc[2], cyc[1:0]==2'b10); wire [63:0] result = {51'h0, t3, 3'h0,t2, 3'h0,t1, 3'h0,t0}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h04f91df71371e950 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module t_tri2 (/*AUTOARG*/ // Outputs t2, // Inputs d, oe ); output t2; input d; input oe; tri1 t2; bufif1 (t2, d, oe); endmodule module t_tri3 (/*AUTOARG*/ // Outputs t3, // Inputs d, oe ); output tri1 t3; input d; input oe; bufif1 (t3, d, oe); endmodule verilator-5.042/test_regress/t/t_dynarray_param.py0000755000542200017500000000073415101701376023003 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_uses_this_bad.out0000644000542200017500000000041015101701376024136 0ustar mahmoudyfreeshell%Error: t/t_class_uses_this_bad.v:11:12: 'this' used outside class (IEEE 1800-2023 8.11) 11 | this.addr = 2; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_math_signed_wire.v0000644000542200017500000000210715101701376023110 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // bug511 module t (/*AUTOARG*/ // Inputs clk ); input clk; wire [7:0] au; wire [7:0] as; Test1 test1 (.au); Test2 test2 (.as); // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] result=%x %x\n", $time, au, as); `endif if (au != 'h12) $stop; if (as != 'h02) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module Test1 (output [7:0] au); wire [7:0] b; wire signed [3:0] c; // verilator lint_off WIDTH assign c=-1; // 'hf assign b=3; // 'h3 assign au=b+c; // 'h12 // verilator lint_on WIDTH endmodule module Test2 (output [7:0] as); wire signed [7:0] b; wire signed [3:0] c; // verilator lint_off WIDTH assign c=-1; // 'hf assign b=3; // 'h3 assign as=b+c; // 'h12 // verilator lint_on WIDTH endmodule verilator-5.042/test_regress/t/t_initial_assign_sformatf.v0000644000542200017500000000114115101701376024473 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: SystemVerilog interface test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Iztok Jeras. // SPDX-License-Identifier: CC0-1.0 interface intf(); function automatic string get_scope; string the_scope = $sformatf("%m"); return the_scope; endfunction initial $display(get_scope()); endinterface module t (/*AUTOARG*/ // Inputs clk ); input clk; // finish report always @ (posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end intf the_intf(); endmodule verilator-5.042/test_regress/t/t_class_extends_alias_unsup.py0000755000542200017500000000076615101701376025241 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_unpacked_array_p_fmt.py0000755000542200017500000000100015101701376024132 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_bug6421.py0000755000542200017500000000074215101701376021063 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags=["--binary"]) test.passes() verilator-5.042/test_regress/t/t_var_overzero.py0000755000542200017500000000100115101701376022501 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--x-initial fast"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_class_virtual_pure_bad.v0000644000542200017500000000041415101701376024313 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class VBase; pure virtual task pure_task; endclass verilator-5.042/test_regress/t/t_param_public.cpp0000644000542200017500000000161515101701376022556 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include "Vt_param_public.h" #include "Vt_param_public_p.h" #include "Vt_param_public_t.h" double sc_time_stamp() { return 0; } int main(int argc, char* argv[]) { Verilated::debug(0); Verilated::commandArgs(argc, argv); VM_PREFIX* topp = new VM_PREFIX; // Make sure public tag worked if (static_cast(Vt_param_public_t::TOP_PARAM) != 30) { vl_fatal(__FILE__, __LINE__, "dut", "bad value"); } if (static_cast(Vt_param_public_p::INPACK) != 0) {} for (int i = 0; i < 10; i++) { // topp->eval(); } topp->final(); VL_DO_DANGLING(delete topp, topp); } verilator-5.042/test_regress/t/t_opt_inline_funcs.v0000644000542200017500000000063315101701376023140 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; function void allfin; $write("*-* All Finished *-*\n"); endfunction task done; $finish; endtask initial begin allfin(); done(); end endmodule verilator-5.042/test_regress/t/t_func_const2_bad.out0000644000542200017500000000205715101701376023177 0ustar mahmoudyfreeshell%Warning-USERFATAL: "f_add = 15" ... For warning description see https://verilator.org/warn/USERFATAL?v=latest ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. %Error: t/t_func_const2_bad.v:22:23: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2' : ... note: In instance 't.b8_a7.c9' t/t_func_const2_bad.v:10:6: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing t/t_func_const2_bad.v:15:13: ... Called from 'f_add()' with parameters: a = 32'h7 b = 32'h8 t/t_func_const2_bad.v:22:23: ... Called from 'f_add2()' with parameters: a = ?32?h7 b = ?32?h8 c = ?32?h9 22 | localparam SOMEP = f_add2(A, B, 9); | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_waiveroutput_multiline.out0000644000542200017500000000072415101701376025005 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator output: Waivers generated with --waiver-output `verilator_config // Below are suggested waivers. You have three options: // 1. Fix the reason for the linter warning in the Verilog sources // 2. Keep the waiver permanently if you are sure it is okay // 3. Keep the waiver temporarily to suppress the output // lint_off -rule UNUSEDSIGNAL -file "*t/t_waiveroutput.v" -match "Signal is not used: 'width_warn'*reg width_warn = 2'b11;*" verilator-5.042/test_regress/t/t_type_non_type.v0000644000542200017500000000225515101701376022500 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Use this file as a template for submitting bugs, etc. // This module takes a single clock input, and should either // $write("*-* All Finished *-*\n"); // $finish; // on success, or $stop. // // The code as shown applies a random vector to the Test // module, then calculates a CRC on the Test module's outputs. // // **If you do not wish for your code to be released to the public // please note it here, otherwise:** // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls; endclass package Pkg; // Issue #2956 typedef string STYPE; typedef string line; task automatic testf; inout STYPE line; endtask endpackage module t; localparam type T = Cls; // Issue #2412 typedef T this_thing; // this_thing now a type function T newer(); T this_thing; // this_thing now a class reference this_thing = new; return this_thing; endfunction initial begin Cls c; c = newer(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_bitsel_struct.v0000644000542200017500000000123115101701376022463 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // A test case for struct signal bit selection. // // This test is to check that bit selection of multi-dimensional signal inside // of a struct works. // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Jie Xu. // SPDX-License-Identifier: CC0-1.0 module t; typedef struct packed { logic [1:0][15:0] channel; logic others; } buss_t; buss_t b; reg [7:0] a; initial begin b = {16'h8765,16'h4321,1'b1}; a = b.channel[0][8+:8]; if (a != 8'h43) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_enum_type_methods_bad.out0000644000542200017500000000057015101701376024502 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_enum_type_methods_bad.v:24:14: Unsupported: enum next/prev with non-constant argument : ... note: In instance 't' 24 | e.next(increment); | ^~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_opt_table_packed_array.v0000644000542200017500000000164315101701376024262 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; logic [3:0][3:0] a; reg [2:0] cyc; initial cyc = 0; always @(posedge clk) cyc <= cyc + 1; always @* begin case (cyc) 3'b000: a = {4'd0, 4'd1, 4'd2, 4'd3}; 3'b001: a = {4'd1, 4'd2, 4'd3, 4'd4}; 3'b010: a = {4'd4, 4'd3, 4'd4, 4'd5}; 3'b100: a = {4'd4, 4'd5, 4'd6, 4'd7}; 3'b101: a = {4'd5, 4'd6, 4'd7, 4'd8}; default: a = {4{4'hf}}; endcase end always @(posedge clk) begin $display("cyle %d = { %d, %d, %d, %d }", cyc, a[0], a[1], a[2], a[3]); if (cyc == 7) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_urandom.py0000755000542200017500000000073415101701376021437 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_param_noval_bad.py0000755000542200017500000000076615101701376023104 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_gate_fdup.v0000644000542200017500000000124715101701376021542 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2005 by Thomas Dzetkulic. // SPDX-License-Identifier: CC0-1.0 module fnor2(f, a, b); parameter W = 1; output [W-1:0]f; input [W-1:0] a, b; supply0 gnd; supply1 vcc; generate genvar i; for (i = 0; i < W; i = i + 1) begin wire w; pmos(f[i], w, a[i]); pmos(w, vcc, b[i]); nmos(f[i], gnd, a[i]); nmos(f[i], gnd, b[i]); end endgenerate endmodule module t(f, a, b); output [1:0] f; input [1:0] a, b; fnor2 #(2) n(f, a, b); endmodule verilator-5.042/test_regress/t/t_string_octal.py0000755000542200017500000000073415101701376022462 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_link_delay2.py0000755000542200017500000000070615101701376023353 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.passes() verilator-5.042/test_regress/t/t_interface_typedef.v0000644000542200017500000000236215101701376023263 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) interface ifc #( parameter int unsigned WIDTH ) (); typedef struct { logic [WIDTH-1:0] data; } struct_t; endinterface module t (/*AUTOARG*/ // Inputs clk ); input clk; ifc #(10) i_ifc10(); ifc #(20) i_ifc20(); sub #(10) u_sub10 (.clk, .ifc_if(i_ifc10)); sub #(20) u_sub20 (.clk, .ifc_if(i_ifc20)); integer cyc = 1; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==20) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module sub #( parameter int EXP_WIDTH) ( input logic clk, ifc ifc_if); typedef ifc_if.struct_t struct_t; wire [EXP_WIDTH-1:0] expval = '1; initial begin struct_t substruct; substruct.data = '1; `checkh($bits(struct_t), EXP_WIDTH); `checkh(substruct.data, expval); end endmodule verilator-5.042/test_regress/t/t_fork_output_arg.v0000644000542200017500000000103415101701376023010 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class Cls; int x = 100; task get_x(output int arg); arg = x; endtask endclass task automatic test; int o; Cls c = new; fork c.get_x(o); join_any if (o != 100) $stop; endtask module t(); initial begin test(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_var_pins_sc2.py0000755000542200017500000000347415101701376022366 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.pli_filename = "t/t_var_pinsizes.cpp" test.top_filename = "t/t_var_pinsizes.v" test.compile(verilator_flags2=[ "-sc -pins-bv 2 --trace-vcd --exe", test.pli_filename, test.t_dir + "/t_var_pinsizes.vlt" ], make_main=False) def hgrep(re): test.file_grep(os.path.join(test.obj_dir, test.vm_prefix + ".h"), re) hgrep(r'sc_core::sc_in\s+&i1;') hgrep(r'sc_core::sc_in\s>\s+&i8;') hgrep(r'sc_core::sc_in\s>\s+&i16;') hgrep(r'sc_core::sc_in\s>\s+&i32;') hgrep(r'sc_core::sc_in\s>\s+&i64;') hgrep(r'sc_core::sc_in\s>\s+&i65;') hgrep(r'sc_core::sc_in\s>\s+&ibv1;') hgrep(r'sc_core::sc_in\s>\s+&ibv16;') hgrep(r'sc_core::sc_in\s>\s+&ibv1_vlt;') hgrep(r'sc_core::sc_in\s>\s+&ibv16_vlt;') hgrep(r'sc_core::sc_out\s+&o1;') hgrep(r'sc_core::sc_out\s>\s+&o8;') hgrep(r'sc_core::sc_out\s>\s+&o16;') hgrep(r'sc_core::sc_out\s>\s+&o32;') hgrep(r'sc_core::sc_out\s>\s+&o64;') hgrep(r'sc_core::sc_out\s>\s+&o65;') hgrep(r'sc_core::sc_out\s>\s+&obv1;') hgrep(r'sc_core::sc_out\s>\s+&obv16;') hgrep(r'sc_core::sc_out\s>\s+&obv1_vlt;') hgrep(r'sc_core::sc_out\s>\s+&obv16_vlt;') test.execute() test.passes() verilator-5.042/test_regress/t/t_case_overlap_bad.py0000755000542200017500000000076615101701376023250 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_flag_wwarn_bad.out0000644000542200017500000000024115101701376023074 0ustar mahmoudyfreeshell%Error: Unknown warning specified: -Wwarn-NOSUCHERRORASTHIS ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. verilator-5.042/test_regress/t/t_var_bad_hide.py0000755000542200017500000000107515101701376022360 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["--lint-only -Wwarn-VARHIDDEN"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_struct_clk.v0000644000542200017500000000222515101701376021756 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); typedef struct { logic clk1; logic clk2; logic rst; } clks_t; module t(/*AUTOARG*/ // Inputs clk, fastclk ); input clk; input fastclk; int cyc = 0; clks_t clks; always_comb begin clks.clk1 = clk; clks.clk2 = fastclk; end // verilator lint_off MULTIDRIVEN int cyc1 = 0; int cyc2 = 0; always @ (negedge clks.clk1) cyc1 <= cyc1 + 1; always @ (negedge clks.clk2) cyc2 <= cyc2 + 1; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc < 10) begin cyc1 <= '0; cyc2 <= '0; end else if (cyc == 99) begin `checkd(cyc1, 90); `checkd(cyc2, 90*5); $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_vpi_dump_missing_scopes.v0000644000542200017500000000172015101701376024530 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2010 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // using public_on causes one to be AstCellInline, and that one has correct scope // without this, both are AstCellInline, and both are wrong /* verilator public_on */ module t ( /*AUTOARG*/ ); initial begin $write("*-* All Finished *-*\n"); $finish(); end gen_wrapper top_wrap_1 (); gen_wrapper top_wrap_2 (); endmodule : t module sub; reg subsig1; endmodule : sub module gen_wrapper; genvar i; generate for (i = 0; i < 1; i++) begin : gen_loop // This fixes the scope // localparam int x = 2; sub after_gen_loop (); end endgenerate endmodule verilator-5.042/test_regress/t/t_debug_gate.py0000755000542200017500000000106615101701376022057 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile( # Check we can call dump() on graph, and other things v_flags=["--debug --debugi 0 --debugi-V3Graph 9"]) test.passes() verilator-5.042/test_regress/t/t_flag_timescale_override2.py0000755000542200017500000000113315101701376024704 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_flag_timescale_override.v" test.compile(verilator_flags2=["-timescale-override /1us"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_inc.v0000644000542200017500000000146715101701376021546 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Base #(type T = integer); T m_count; function void test1(); if (this.m_count != 0) $stop; if (this.m_count++ != 0) $stop; if (this.m_count != 1) $stop; if (m_count++ != 1) $stop; if (this.m_count != 2) $stop; endfunction endclass class Cls #(type T = integer) extends Base #(T); endclass module t; Cls #(int) c; initial begin c = new; c.test1(); c.m_count = 0; if (c.m_count != 0) $stop; if (c.m_count++ != 0) $stop; if (c.m_count != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_sys_readmem_4state.py0000755000542200017500000000144715101701376023570 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--x-initial unique"]) test.execute(all_run_flags=["+verilator+rand+reset+1"]) test.files_identical(test.obj_dir + "/t_sys_readmem_4state_b.mem", "t/t_sys_readmem_4state__b.mem.out") test.files_identical(test.obj_dir + "/t_sys_readmem_4state_h.mem", "t/t_sys_readmem_4state__h.mem.out") test.passes() verilator-5.042/test_regress/t/t_stream_bad.v0000644000542200017500000000066615101701376021711 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 module t; logic [31:0] packed_data_32; byte byte_in [4]; logic [ 3:0] x = 4'($random()); initial begin packed_data_32 = {<<$random{byte_in}}; packed_data_32 = {< 1) $display("[%0t] single delay with const implication stmt, fileline:%d", $time, 32); | ^~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:34:41: Unsupported: Implication with sequence expression 34 | assert property (@(posedge clk) ##1 1 |-> not (val)) $display("[%0t] single delay implication with negated var stmt, fileline:%d", $time, 34); | ^~~ %Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:36:37: Unsupported: Implication with sequence expression 36 | assert property (@(posedge clk) 1 |-> ##1 val) $display("[%0t] single delay implication with negated var stmt, fileline:%d", $time, 36); | ^~~ %Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:38:45: Unsupported: Implication with sequence expression 38 | assert property (@(posedge clk) (##1 val) |-> (not val)) $display("[%0t] single delay with negated implication stmt, fileline:%d", $time, 38); | ^~~ %Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:40:45: Unsupported: Implication with sequence expression 40 | assert property (@(posedge clk) ##1 (val) |-> not (val)) $display("[%0t] single delay with negated implication brackets stmt, fileline:%d", $time, 40); | ^~~ %Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:44:41: Unsupported: Implication with sequence expression 44 | assert property (@(posedge clk) ##1 1 |-> 0) $display("[%0t] disable iff with cond implication stmt, fileline:%d", $time, 44); | ^~~ %Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:46:45: Unsupported: Implication with sequence expression 46 | assert property (@(posedge clk) (##1 val) |-> (##1 val)) $display("[%0t] two delays implication stmt, fileline:%d", $time, 46); | ^~~ %Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:48:52: Unsupported: Disable iff with sequence expression : ... note: In instance 't' 48 | assert property (@(posedge clk) disable iff (cyc != 5) ##1 0) $display("[%0t] disable iff stmt, fileline:%d", $time, 48); | ^~ %Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:50:52: Unsupported: Disable iff with sequence expression : ... note: In instance 't' 50 | assume property (@(posedge clk) disable iff (cyc != 5) ##1 0) $display("[%0t] disable iff stmt, fileline:%d", $time, 50); | ^~ %Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:52:51: Unsupported: Disable iff with sequence expression : ... note: In instance 't' 52 | cover property (@(posedge clk) disable iff (cyc != 5) ##1 0) $display("[%0t] disable iff stmt, fileline:%d", $time, 52); | ^~ %Error: Exiting due to verilator-5.042/test_regress/t/t_param_package.v0000644000542200017500000000110615101701376022351 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; Test0 t0 (.val0('0)); Test1 t1 (.val1('0)); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule package params; parameter P = 7; endpackage module Test0 (val0); parameter Z = 1; input [Z : 0] val0; endmodule module Test1 (val1); input logic [params::P : 0] val1; // Fully qualified parameter endmodule verilator-5.042/test_regress/t/t_preproc_ifexpr.py0000755000542200017500000000137515101701376023023 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') stdout_filename = os.path.join(test.obj_dir, test.name + "__test.vpp") test.compile(verilator_flags2=['-E -P'], verilator_make_gmake=False, make_top_shell=False, make_main=False, stdout_filename=stdout_filename) test.files_identical(stdout_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_randomize_method_with_bad.py0000755000542200017500000000076615101701376025170 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_tri_eqcase_input.py0000755000542200017500000000073415101701376023330 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_foreach_type_bad.py0000755000542200017500000000076615101701376023255 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_foreach_array.py0000755000542200017500000000073415101701376022577 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_assert_ctl_immediate.v0000644000542200017500000000220715101701376023762 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; module_with_assert module_with_assert(clk); module_with_assertctl module_with_assertctl(clk); always @ (posedge clk) begin assert(0); end always @ (negedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule module module_with_assert(input clk); always @(posedge clk) assert(0); endmodule module module_with_assertctl(input clk); function void assert_off; begin $assertoff; end endfunction function void assert_on; begin $asserton; end endfunction function void f_assert; begin assert(0); end endfunction initial begin assert_on(); assert(0); assert_off(); assert_off(); assert(0); assert_on(); assert_on(); assert(0); f_assert(); f_assert(); assert_off(); f_assert(); f_assert(); end endmodule verilator-5.042/test_regress/t/t_no_std_bad.v0000644000542200017500000000043715101701376021700 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilator lint_off DECLFILENAME module t; import std::*; endmodule verilator-5.042/test_regress/t/t_process_std.out0000644000542200017500000000027115101701376022472 0ustar mahmoudyfreeshell[0] %Error: verilated_std.sv:154: Assertion failed in top.std.process.set_randstate: std::process::set_randstate() not supported %Error: verilated_std.sv:154: Verilog $stop Aborting... verilator-5.042/test_regress/t/t_enum_base_bad.v0000644000542200017500000000155515101701376022352 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; typedef struct {int a;} s_t; typedef enum s_t { // BAD EN_ZERO } bad_t; typedef int int_t; enum int_t [1:0] { // BAD enum type INTRANGE_VAL } intrange_e; typedef bit [1:0][1:0] d2_t; enum d2_t { // BAD enum type TD2_VAL } td2_e; enum logic [1:0][1:0] { // BAD enum type D2_VAL } d2_e; typedef struct packed {int x;} str_t; enum str_t { // BAD enum type STR_VAL } str_e; typedef enum {ENUM_VAL} enum_t; enum enum_t { // BAD enum type ENUMT_VAL } enumt_val; typedef logic array2_t[1:0]; enum array2_t { // BAD enum type ARRAY2_VAL } array2_e; initial $stop; endmodule verilator-5.042/test_regress/t/t_trace_max.py0000755000542200017500000000137315101701376021735 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["--cc --trace-vcd --trace-max-width 64 --trace-max-array 16"]) test.execute() test.file_grep_not(test.trace_filename, r'wide1') test.file_grep_not(test.trace_filename, r'wide2') test.file_grep_not(test.trace_filename, r'deep1') test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_vpi_param.v0000644000542200017500000000264215101701376021562 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2010 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef USE_VPI_NOT_DPI //We call it via $c so we can verify DPI isn't required - see bug572 `else import "DPI-C" context function int mon_check(); `endif module t #( parameter int WIDTH /* verilator public_flat_rd */ = 32 ) (/*AUTOARG*/ // Inputs clk ); `ifdef VERILATOR `systemc_header extern "C" int mon_check(); `verilog `endif input clk; localparam int DEPTH /* verilator public_flat_rd */ = 16; localparam longint PARAM_LONG /* verilator public_flat_rd */ = 64'hFEDCBA9876543210; localparam string PARAM_STR /* verilator public_flat_rd */ = "'some string value'"; reg [WIDTH-1:0] mem0 [DEPTH:1] /*verilator public_flat_rw @(posedge clk) */; integer i, status; // Test loop initial begin `ifdef VERILATOR status = $c32("mon_check()"); `endif `ifdef IVERILOG status = $mon_check(); `endif `ifndef USE_VPI_NOT_DPI status = mon_check(); `endif if (status!=0) begin $write("%%Error: t_vpi_param.cpp:%0d: C Test failed\n", status); $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule : t verilator-5.042/test_regress/t/t_interface_mismodport_bad.out0000644000542200017500000000053515101701376025170 0ustar mahmoudyfreeshell%Error: t/t_interface_mismodport_bad.v:32:12: Can't find definition of 'bad' in dotted signal: 'isub.bad' 32 | isub.bad = i_value; | ^~~ ... Known scopes under 'bad': ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_foreach_noivar_bad.py0000755000542200017500000000103615101701376023561 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = 't/t_foreach_noivar.v' test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_clk_concat6.py0000755000542200017500000000073415101701376022160 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_sys_readmem_bad_end.out0000644000542200017500000000021015101701376024077 0ustar mahmoudyfreeshell%Warning: t/t_sys_readmem_bad_end.mem:12: $readmem file ended before specified final address (IEEE 1800-2023 21.4) *-* All Finished *-* verilator-5.042/test_regress/t/t_class_dict.py0000755000542200017500000000073415101701376022102 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_virtual_sched_nba.v0000644000542200017500000000274115101701376025300 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 interface Bus1; logic [15:0] data; endinterface interface Bus2; logic [15:0] data; endinterface interface Bus3; logic [15:0] data; endinterface module t; logic clk = 0; integer cyc = 0; Bus1 intf1(); Bus2 intf2(); Bus3 intf3(); virtual Bus1 vif1 = intf1; virtual Bus2 vif2 = intf2; virtual Bus3 vif3 = intf3; logic [15:0] data; // assign vif2.data = data; always @(negedge clk) begin vif2.data <= data; end always @(posedge clk) begin cyc <= cyc + 1; if (cyc == 1) vif1.data = 'hdead; else if (cyc == 2) data = vif1.data; else if (cyc == 3) vif1.data = 'hbeef; else if (cyc == 4) data = vif1.data; else if (cyc == 5) intf3.data <= 'hface; else if (cyc == 6) intf3.data <= 'hcafe; end // Finish on negedge so that $finish is last always @(negedge clk) if (cyc >= 7) begin $write("*-* All Finished *-*\n"); $finish; end always @(intf1.data) begin $write("[%0t] intf1.data==%h\n", $time, intf1.data); end always @(intf2.data) begin $write("[%0t] intf2.data==%h\n", $time, intf2.data); end always @(vif3.data) begin $write("[%0t] vif3.data==%h\n", $time, vif3.data); end initial begin repeat (20) #5ns clk = ~clk; end endmodule verilator-5.042/test_regress/t/t_inst_2star_bad.py0000755000542200017500000000076615101701376022675 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_disable_outside2.py0000755000542200017500000000101315101701376023202 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(timing_loop=True, verilator_flags2=["--timing"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_var_ref_static.out0000644000542200017500000000067115101701376023141 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_var_ref_static.v:12:22: Unsupported: 'ref static' ports 12 | function void crs(const ref static i); | ^~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_var_ref_static.v:14:21: Unsupported: 'ref static' ports 14 | function void rs(ref static i); | ^~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_dpi_arg_output_type.v0000644000542200017500000011651115101701376023673 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2020 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VCS `define NO_TIME `endif `ifdef NC `define NO_TIME `define NO_INTEGER `define NO_SHORTREAL `endif `ifdef MS `endif `ifdef VERILATOR `define NO_SHORTREAL `define NULL 64'd0 `else `define NULL null `endif module t (/*AUTOARG*/ // Inputs clk ); input clk; `ifdef VERILATOR wire _unused = &{1'b0, clk}; `endif // Legal output argument types for DPI functions //====================================================================== // Type definitions //====================================================================== // Basic types as per IEEE 1800-2023 35.5.6 typedef byte byte_t; typedef byte unsigned byte_unsigned_t; typedef shortint shortint_t; typedef shortint unsigned shortint_unsigned_t; typedef int int_t; typedef int unsigned int_unsigned_t; typedef longint longint_t; typedef longint unsigned longint_unsigned_t; `ifndef NO_TIME typedef time time_t; `endif `ifndef NO_INTEGER typedef integer integer_t; `endif typedef real real_t; `ifndef NO_SHORTREAL typedef shortreal shortreal_t; `endif typedef chandle chandle_t; typedef string string_t; typedef bit bit_t; typedef logic logic_t; // 2-state packed structures typedef struct packed { bit x; } struct_2_state_1; typedef struct packed { bit [15:0] x; bit [15:0] y; } struct_2_state_32; typedef struct packed { bit [15:0] x; bit [16:0] y; } struct_2_state_33; typedef struct packed { bit [31:0] x; bit [31:0] y; } struct_2_state_64; typedef struct packed { bit [31:0] x; bit [32:0] y; } struct_2_state_65; typedef struct packed { bit [63:0] x; bit [63:0] y; } struct_2_state_128; // 2-state packed unions typedef union packed { bit x; bit y; } union_2_state_1; typedef union packed { bit [31:0] x; bit [31:0] y; } union_2_state_32; typedef union packed { bit [32:0] x; bit [32:0] y; } union_2_state_33; typedef union packed { bit [63:0] x; bit [63:0] y; } union_2_state_64; typedef union packed { bit [64:0] x; bit [64:0] y; } union_2_state_65; typedef union packed { bit [127:0] x; bit [127:0] y; } union_2_state_128; // 4-state packed structures typedef struct packed { logic x; } struct_4_state_1; typedef struct packed { logic [15:0] x; bit [15:0] y; } struct_4_state_32; typedef struct packed { logic [15:0] x; bit [16:0] y; } struct_4_state_33; typedef struct packed { logic [31:0] x; bit [31:0] y; } struct_4_state_64; typedef struct packed { logic [31:0] x; bit [32:0] y; } struct_4_state_65; typedef struct packed { logic [63:0] x; bit [63:0] y; } struct_4_state_128; // 4-state packed unions typedef union packed { logic x; bit y; } union_4_state_1; typedef union packed { logic [31:0] x; bit [31:0] y; } union_4_state_32; typedef union packed { logic [32:0] x; bit [32:0] y; } union_4_state_33; typedef union packed { logic [63:0] x; bit [63:0] y; } union_4_state_64; typedef union packed { logic [64:0] x; bit [64:0] y; } union_4_state_65; typedef union packed { logic [127:0] x; bit [127:0] y; } union_4_state_128; //====================================================================== // Imports //====================================================================== // Basic types as per IEEE 1800-2023 35.5.6 import "DPI-C" function void i_byte (output byte o); import "DPI-C" function void i_byte_unsigned (output byte unsigned o); import "DPI-C" function void i_shortint (output shortint o); import "DPI-C" function void i_shortint_unsigned (output shortint unsigned o); import "DPI-C" function void i_int (output int o); import "DPI-C" function void i_int_unsigned (output int unsigned o); import "DPI-C" function void i_longint (output longint o); import "DPI-C" function void i_longint_unsigned (output longint unsigned o); `ifndef NO_TIME import "DPI-C" function void i_time (output time o); `endif `ifndef NO_INTEGER import "DPI-C" function void i_integer (output integer o); `endif import "DPI-C" function void i_real (output real o); `ifndef NO_SHORTREAL import "DPI-C" function void i_shortreal (output shortreal o); `endif import "DPI-C" function void i_chandle (output chandle o); import "DPI-C" function void i_string (output string o); import "DPI-C" function void i_bit (output bit o); import "DPI-C" function void i_logic (output logic o); // Basic types via typedef import "DPI-C" function void i_byte_t (output byte_t o); import "DPI-C" function void i_byte_unsigned_t (output byte_unsigned_t o); import "DPI-C" function void i_shortint_t (output shortint_t o); import "DPI-C" function void i_shortint_unsigned_t (output shortint_unsigned_t o); import "DPI-C" function void i_int_t (output int_t o); import "DPI-C" function void i_int_unsigned_t (output int_unsigned_t o); import "DPI-C" function void i_longint_t (output longint_t o); import "DPI-C" function void i_longint_unsigned_t (output longint_unsigned_t o); `ifndef NO_TIME import "DPI-C" function void i_time_t (output time_t o); `endif `ifndef NO_INTEGER import "DPI-C" function void i_integer_t (output integer_t o); `endif import "DPI-C" function void i_real_t (output real_t o); `ifndef NO_SHORTREAL import "DPI-C" function void i_shortreal_t (output shortreal_t o); `endif import "DPI-C" function void i_chandle_t (output chandle_t o); import "DPI-C" function void i_string_t (output string_t o); import "DPI-C" function void i_bit_t (output bit_t o); import "DPI-C" function void i_logic_t (output logic_t o); // 2-state packed arrays import "DPI-C" function void i_array_2_state_1 (output bit [ 0:0] o); import "DPI-C" function void i_array_2_state_32 (output bit [ 31:0] o); import "DPI-C" function void i_array_2_state_33 (output bit [ 32:0] o); import "DPI-C" function void i_array_2_state_64 (output bit [ 63:0] o); import "DPI-C" function void i_array_2_state_65 (output bit [ 64:0] o); import "DPI-C" function void i_array_2_state_128(output bit [127:0] o); // 2-state packed structures import "DPI-C" function void i_struct_2_state_1 (output struct_2_state_1 o); import "DPI-C" function void i_struct_2_state_32 (output struct_2_state_32 o); import "DPI-C" function void i_struct_2_state_33 (output struct_2_state_33 o); import "DPI-C" function void i_struct_2_state_64 (output struct_2_state_64 o); import "DPI-C" function void i_struct_2_state_65 (output struct_2_state_65 o); import "DPI-C" function void i_struct_2_state_128 (output struct_2_state_128 o); // 2-state packed unions import "DPI-C" function void i_union_2_state_1 (output union_2_state_1 o); import "DPI-C" function void i_union_2_state_32 (output union_2_state_32 o); import "DPI-C" function void i_union_2_state_33 (output union_2_state_33 o); import "DPI-C" function void i_union_2_state_64 (output union_2_state_64 o); import "DPI-C" function void i_union_2_state_65 (output union_2_state_65 o); import "DPI-C" function void i_union_2_state_128 (output union_2_state_128 o); // 4-state packed arrays import "DPI-C" function void i_array_4_state_1 (output logic [ 0:0] o); import "DPI-C" function void i_array_4_state_32 (output logic [ 31:0] o); import "DPI-C" function void i_array_4_state_33 (output logic [ 32:0] o); import "DPI-C" function void i_array_4_state_64 (output logic [ 63:0] o); import "DPI-C" function void i_array_4_state_65 (output logic [ 64:0] o); import "DPI-C" function void i_array_4_state_128(output logic [127:0] o); // 4-state packed structures import "DPI-C" function void i_struct_4_state_1 (output struct_4_state_1 o); import "DPI-C" function void i_struct_4_state_32 (output struct_4_state_32 o); import "DPI-C" function void i_struct_4_state_33 (output struct_4_state_33 o); import "DPI-C" function void i_struct_4_state_64 (output struct_4_state_64 o); import "DPI-C" function void i_struct_4_state_65 (output struct_4_state_65 o); import "DPI-C" function void i_struct_4_state_128 (output struct_4_state_128 o); // 4-state packed unions import "DPI-C" function void i_union_4_state_1 (output union_4_state_1 o); import "DPI-C" function void i_union_4_state_32 (output union_4_state_32 o); import "DPI-C" function void i_union_4_state_33 (output union_4_state_33 o); import "DPI-C" function void i_union_4_state_64 (output union_4_state_64 o); import "DPI-C" function void i_union_4_state_65 (output union_4_state_65 o); import "DPI-C" function void i_union_4_state_128 (output union_4_state_128 o); //====================================================================== // Exports //====================================================================== // Basic types as per IEEE 1800-2023 35.5.6 export "DPI-C" function e_byte; export "DPI-C" function e_byte_unsigned; export "DPI-C" function e_shortint; export "DPI-C" function e_shortint_unsigned; export "DPI-C" function e_int; export "DPI-C" function e_int_unsigned; export "DPI-C" function e_longint; export "DPI-C" function e_longint_unsigned; `ifndef NO_TIME export "DPI-C" function e_time; `endif `ifndef NO_INTEGER export "DPI-C" function e_integer; `endif export "DPI-C" function e_real; `ifndef NO_SHORTREAL export "DPI-C" function e_shortreal; `endif export "DPI-C" function e_chandle; export "DPI-C" function e_string; export "DPI-C" function e_bit; export "DPI-C" function e_logic; // Basic types via typedef export "DPI-C" function e_byte_t; export "DPI-C" function e_byte_unsigned_t; export "DPI-C" function e_shortint_t; export "DPI-C" function e_shortint_unsigned_t; export "DPI-C" function e_int_t; export "DPI-C" function e_int_unsigned_t; export "DPI-C" function e_longint_t; export "DPI-C" function e_longint_unsigned_t; `ifndef NO_TIME export "DPI-C" function e_time_t; `endif `ifndef NO_INTEGER export "DPI-C" function e_integer_t; `endif export "DPI-C" function e_real_t; `ifndef NO_SHORTREAL export "DPI-C" function e_shortreal_t; `endif export "DPI-C" function e_chandle_t; export "DPI-C" function e_string_t; export "DPI-C" function e_bit_t; export "DPI-C" function e_logic_t; // 2-state packed arrays export "DPI-C" function e_array_2_state_1; export "DPI-C" function e_array_2_state_32; export "DPI-C" function e_array_2_state_33; export "DPI-C" function e_array_2_state_64; export "DPI-C" function e_array_2_state_65; export "DPI-C" function e_array_2_state_128; // 2-state packed structures export "DPI-C" function e_struct_2_state_1; export "DPI-C" function e_struct_2_state_32; export "DPI-C" function e_struct_2_state_33; export "DPI-C" function e_struct_2_state_64; export "DPI-C" function e_struct_2_state_65; export "DPI-C" function e_struct_2_state_128; // 2-state packed unions export "DPI-C" function e_union_2_state_1; export "DPI-C" function e_union_2_state_32; export "DPI-C" function e_union_2_state_33; export "DPI-C" function e_union_2_state_64; export "DPI-C" function e_union_2_state_65; export "DPI-C" function e_union_2_state_128; // 4-state packed arrays export "DPI-C" function e_array_4_state_1; export "DPI-C" function e_array_4_state_32; export "DPI-C" function e_array_4_state_33; export "DPI-C" function e_array_4_state_64; export "DPI-C" function e_array_4_state_65; export "DPI-C" function e_array_4_state_128; // 4-state packed structures export "DPI-C" function e_struct_4_state_1; export "DPI-C" function e_struct_4_state_32; export "DPI-C" function e_struct_4_state_33; export "DPI-C" function e_struct_4_state_64; export "DPI-C" function e_struct_4_state_65; export "DPI-C" function e_struct_4_state_128; // 4-state packed unions export "DPI-C" function e_union_4_state_1; export "DPI-C" function e_union_4_state_32; export "DPI-C" function e_union_4_state_33; export "DPI-C" function e_union_4_state_64; export "DPI-C" function e_union_4_state_65; export "DPI-C" function e_union_4_state_128; //====================================================================== // Definitions of exported functions //====================================================================== // Basic types as per IEEE 1800-2023 35.5.6 byte n_byte = 0; function void e_byte(output byte o); o = 8'd10 + n_byte; n_byte++; endfunction byte n_byte_unsigned = 0; function void e_byte_unsigned(output byte unsigned o); o = 8'd20 + n_byte_unsigned; n_byte_unsigned++; endfunction shortint n_shortint = 0; function void e_shortint(output shortint o); o = 16'd30 + n_shortint; n_shortint++; endfunction shortint n_shortint_unsigned = 0; function void e_shortint_unsigned(output shortint unsigned o); o = 16'd40 + n_shortint_unsigned; n_shortint_unsigned++; endfunction int n_int = 0; function void e_int(output int o); o = 32'd50 + n_int; n_int++; endfunction int n_int_unsigned = 0; function void e_int_unsigned(output int unsigned o); o = 32'd60 + n_int_unsigned; n_int_unsigned++; endfunction longint n_longint = 0; function void e_longint(output longint o); o = 64'd70 + n_longint; n_longint++; endfunction longint n_longint_unsigned = 0; function void e_longint_unsigned(output longint unsigned o); o = 64'd80 + n_longint_unsigned; n_longint_unsigned++; endfunction `ifndef NO_TIME longint n_time = 0; function void e_time(output time o); o = 64'd90 + n_time; n_time++; endfunction `endif `ifndef NO_INTEGER int n_integer = 0; function void e_integer(output integer o); o = 32'd100 + n_integer; n_integer++; endfunction `endif int n_real = 0; function void e_real(output real o); o = real'(2*n_real + 1) / 2.0; n_real++; endfunction `ifndef NO_SHORTREAL int n_shortreal = 0; function void e_shortreal(output shortreal o); o = shortreal'(4*n_shortreal + 1) / 4.0; n_shortreal++; endfunction `endif int n_chandle = 0; function void e_chandle(output chandle o); $display("e_chandle %1d", n_chandle); o = `NULL; n_chandle++; endfunction int n_string = 0; function void e_string(output string o); $display("e_string %1d", n_string); o = n_string[0] ? "World" : "Hello"; n_string++; endfunction int n_bit = 0; function void e_bit(output bit o); $display("e_bit %1d", n_bit); o = n_bit[0]; n_bit++; endfunction int n_logic = 0; function void e_logic(output logic o); $display("e_logic %1d", n_logic); o = ~n_logic[0]; n_logic++; endfunction // Basic types via typedefs byte_t n_byte_t = 0; function void e_byte_t(output byte_t o); o = 8'd10 + n_byte_t; n_byte_t += 2; endfunction byte n_byte_unsigned_t = 0; function void e_byte_unsigned_t(output byte_unsigned_t o); o = 8'd20 + n_byte_unsigned_t; n_byte_unsigned_t += 2; endfunction shortint_t n_shortint_t = 0; function void e_shortint_t(output shortint_t o); o = 16'd30 + n_shortint_t; n_shortint_t += 2; endfunction shortint n_shortint_unsigned_t = 0; function void e_shortint_unsigned_t(output shortint_unsigned_t o); o = 16'd40 + n_shortint_unsigned_t; n_shortint_unsigned_t += 2; endfunction int_t n_int_t = 0; function void e_int_t(output int_t o); o = 32'd50 + n_int_t; n_int_t += 2; endfunction int n_int_unsigned_t = 0; function void e_int_unsigned_t(output int_unsigned_t o); o = 32'd60 + n_int_unsigned_t; n_int_unsigned_t += 2; endfunction longint_t n_longint_t = 0; function void e_longint_t(output longint_t o); o = 64'd70 + n_longint_t; n_longint_t += 2; endfunction longint n_longint_unsigned_t = 0; function void e_longint_unsigned_t(output longint_unsigned_t o); o = 64'd80 + n_longint_unsigned_t; n_longint_unsigned_t += 2; endfunction `ifndef NO_TIME longint n_time_t = 0; function void e_time_t(output time_t o); o = 64'd90 + n_time_t; n_time_t += 2; endfunction `endif `ifndef NO_INTEGER int n_integer_t = 0; function void e_integer_t(output integer o); o = 32'd100 + n_integer_t; n_integer_t += 2; endfunction `endif int n_real_t = 0; function void e_real_t(output real_t o); o = real'(2*n_real_t + 1) / 2.0; n_real_t += 2; endfunction `ifndef NO_SHORTREAL int n_shortreal_t = 0; function void e_shortreal_t(output shortreal_t o); o = shortreal'(4*n_shortreal_t + 1) / 4.0; n_shortreal_t += 2; endfunction `endif int n_chandle_t = 0; function void e_chandle_t(output chandle_t o); $display("e_chandle_t %1d", n_chandle_t); o = `NULL; n_chandle_t++; endfunction int n_string_t = 0; function void e_string_t(output string_t o); $display("e_string_t %1d", n_string_t); o = n_string_t[0] ? "World" : "Hello"; n_string_t++; endfunction int n_bit_t = 0; function void e_bit_t(output bit_t o); $display("e_bit_t %1d", n_bit_t); o = n_bit_t[0]; n_bit_t++; endfunction int n_logic_t = 0; function void e_logic_t(output logic_t o); $display("e_logic_t %1d", n_logic_t); o = ~n_logic_t[0]; n_logic_t++; endfunction // 2-state packed arrays int n_array_2_state_1 = 0; function void e_array_2_state_1(output bit [ 0:0] o); $display("e_array_2_state_1 %1d", n_array_2_state_1); o = n_array_2_state_1[0]; n_array_2_state_1++; endfunction int n_array_2_state_32 = 0; function void e_array_2_state_32(output bit [31:0] o); $display("e_array_2_state_32 %1d", n_array_2_state_32); o = ~32'd0 >> n_array_2_state_32; n_array_2_state_32++; endfunction int n_array_2_state_33 = 0; function void e_array_2_state_33(output bit [32:0] o); $display("e_array_2_state_33 %1d", n_array_2_state_33); o = ~33'd0 >> n_array_2_state_33; n_array_2_state_33++; endfunction int n_array_2_state_64 = 0; function void e_array_2_state_64(output bit [63:0] o); $display("e_array_2_state_64 %1d", n_array_2_state_64); o = ~64'd0 >> n_array_2_state_64; n_array_2_state_64++; endfunction int n_array_2_state_65 = 0; function void e_array_2_state_65(output bit [64:0] o); $display("e_array_2_state_65 %1d", n_array_2_state_65); o = ~65'd0 >> n_array_2_state_65; n_array_2_state_65++; endfunction int n_array_2_state_128 = 0; function void e_array_2_state_128(output bit [127:0] o); $display("e_array_2_state_128 %1d", n_array_2_state_128); o = ~128'd0 >> n_array_2_state_128; n_array_2_state_128++; endfunction // 2-state packed structures int n_struct_2_state_1 = 0; function void e_struct_2_state_1(output struct_2_state_1 o); $display("e_struct_2_state_1 %1d", n_struct_2_state_1); o = n_struct_2_state_1[0]; n_struct_2_state_1++; endfunction int n_struct_2_state_32 = 0; function void e_struct_2_state_32(output struct_2_state_32 o); $display("e_struct_2_state_32 %1d", n_struct_2_state_32); o = ~32'd0 >> n_struct_2_state_32; n_struct_2_state_32++; endfunction int n_struct_2_state_33 = 0; function void e_struct_2_state_33(output struct_2_state_33 o); $display("e_struct_2_state_33 %1d", n_struct_2_state_33); o = ~33'd0 >> n_struct_2_state_33; n_struct_2_state_33++; endfunction int n_struct_2_state_64 = 0; function void e_struct_2_state_64(output struct_2_state_64 o); $display("e_struct_2_state_64 %1d", n_struct_2_state_64); o = ~64'd0 >> n_struct_2_state_64; n_struct_2_state_64++; endfunction int n_struct_2_state_65 = 0; function void e_struct_2_state_65(output struct_2_state_65 o); $display("e_struct_2_state_65 %1d", n_struct_2_state_65); o = ~65'd0 >> n_struct_2_state_65; n_struct_2_state_65++; endfunction int n_struct_2_state_128 = 0; function void e_struct_2_state_128(output struct_2_state_128 o); $display("e_struct_2_state_128 %1d", n_struct_2_state_128); o = ~128'd0 >> n_struct_2_state_128; n_struct_2_state_128++; endfunction // 2-state packed unions int n_union_2_state_1 = 0; function void e_union_2_state_1(output union_2_state_1 o); $display("e_union_2_state_1 %1d", n_union_2_state_1); o = n_union_2_state_1[0]; n_union_2_state_1++; endfunction int n_union_2_state_32 = 0; function void e_union_2_state_32(output union_2_state_32 o); $display("e_union_2_state_32 %1d", n_union_2_state_32); o = ~32'd0 >> n_union_2_state_32; n_union_2_state_32++; endfunction int n_union_2_state_33 = 0; function void e_union_2_state_33(output union_2_state_33 o); $display("e_union_2_state_33 %1d", n_union_2_state_33); o = ~33'd0 >> n_union_2_state_33; n_union_2_state_33++; endfunction int n_union_2_state_64 = 0; function void e_union_2_state_64(output union_2_state_64 o); $display("e_union_2_state_64 %1d", n_union_2_state_64); o = ~64'd0 >> n_union_2_state_64; n_union_2_state_64++; endfunction int n_union_2_state_65 = 0; function void e_union_2_state_65(output union_2_state_65 o); $display("e_union_2_state_65 %1d", n_union_2_state_65); o = ~65'd0 >> n_union_2_state_65; n_union_2_state_65++; endfunction int n_union_2_state_128 = 0; function void e_union_2_state_128(output union_2_state_128 o); $display("e_union_2_state_128 %1d", n_union_2_state_128); o = ~128'd0 >> n_union_2_state_128; n_union_2_state_128++; endfunction // 4-state packed arrays int n_array_4_state_1 = 0; function void e_array_4_state_1(output logic [ 0:0] o); $display("e_array_4_state_1 %1d", n_array_4_state_1); o = n_array_4_state_1[0]; n_array_4_state_1++; endfunction int n_array_4_state_32 = 0; function void e_array_4_state_32(output logic [31:0] o); $display("e_array_4_state_32 %1d", n_array_4_state_32); o = ~32'd0 >> n_array_4_state_32; n_array_4_state_32++; endfunction int n_array_4_state_33 = 0; function void e_array_4_state_33(output logic [32:0] o); $display("e_array_4_state_33 %1d", n_array_4_state_33); o = ~33'd0 >> n_array_4_state_33; n_array_4_state_33++; endfunction int n_array_4_state_64 = 0; function void e_array_4_state_64(output logic [63:0] o); $display("e_array_4_state_64 %1d", n_array_4_state_64); o = ~64'd0 >> n_array_4_state_64; n_array_4_state_64++; endfunction int n_array_4_state_65 = 0; function void e_array_4_state_65(output logic [64:0] o); $display("e_array_4_state_65 %1d", n_array_4_state_65); o = ~65'd0 >> n_array_4_state_65; n_array_4_state_65++; endfunction int n_array_4_state_128 = 0; function void e_array_4_state_128(output logic [127:0] o); $display("e_array_4_state_128 %1d", n_array_4_state_128); o = ~128'd0 >> n_array_4_state_128; n_array_4_state_128++; endfunction // 4-state packed structures int n_struct_4_state_1 = 0; function void e_struct_4_state_1(output struct_4_state_1 o); $display("e_struct_4_state_1 %1d", n_struct_4_state_1); o = n_struct_4_state_1[0]; n_struct_4_state_1++; endfunction int n_struct_4_state_32 = 0; function void e_struct_4_state_32(output struct_4_state_32 o); $display("e_struct_4_state_32 %1d", n_struct_4_state_32); o = ~32'd0 >> n_struct_4_state_32; n_struct_4_state_32++; endfunction int n_struct_4_state_33 = 0; function void e_struct_4_state_33(output struct_4_state_33 o); $display("e_struct_4_state_33 %1d", n_struct_4_state_33); o = ~33'd0 >> n_struct_4_state_33; n_struct_4_state_33++; endfunction int n_struct_4_state_64 = 0; function void e_struct_4_state_64(output struct_4_state_64 o); $display("e_struct_4_state_64 %1d", n_struct_4_state_64); o = ~64'd0 >> n_struct_4_state_64; n_struct_4_state_64++; endfunction int n_struct_4_state_65 = 0; function void e_struct_4_state_65(output struct_4_state_65 o); $display("e_struct_4_state_65 %1d", n_struct_4_state_65); o = ~65'd0 >> n_struct_4_state_65; n_struct_4_state_65++; endfunction int n_struct_4_state_128 = 0; function void e_struct_4_state_128(output struct_4_state_128 o); $display("e_struct_4_state_128 %1d", n_struct_4_state_128); o = ~128'd0 >> n_struct_4_state_128; n_struct_4_state_128++; endfunction // 4-state packed unions int n_union_4_state_1 = 0; function void e_union_4_state_1(output union_4_state_1 o); $display("e_union_4_state_1 %1d", n_union_4_state_1); o = n_union_4_state_1[0]; n_union_4_state_1++; endfunction int n_union_4_state_32 = 0; function void e_union_4_state_32(output union_4_state_32 o); $display("e_union_4_state_32 %1d", n_union_4_state_32); o = ~32'd0 >> n_union_4_state_32; n_union_4_state_32++; endfunction int n_union_4_state_33 = 0; function void e_union_4_state_33(output union_4_state_33 o); $display("e_union_4_state_33 %1d", n_union_4_state_33); o = ~33'd0 >> n_union_4_state_33; n_union_4_state_33++; endfunction int n_union_4_state_64 = 0; function void e_union_4_state_64(output union_4_state_64 o); $display("e_union_4_state_64 %1d", n_union_4_state_64); o = ~64'd0 >> n_union_4_state_64; n_union_4_state_64++; endfunction int n_union_4_state_65 = 0; function void e_union_4_state_65(output union_4_state_65 o); $display("e_union_4_state_65 %1d", n_union_4_state_65); o = ~65'd0 >> n_union_4_state_65; n_union_4_state_65++; endfunction int n_union_4_state_128 = 0; function void e_union_4_state_128(output union_4_state_128 o); $display("e_union_4_state_128 %1d", n_union_4_state_128); o = ~128'd0 >> n_union_4_state_128; n_union_4_state_128++; endfunction //====================================================================== // Invoke all functions 3 times (they have side effects) //====================================================================== import "DPI-C" context function void check_exports(); initial begin for (int i = 0 ; i < 3; i++) begin // Check the imports byte x_byte; byte unsigned x_byte_unsigned; shortint x_shortint; shortint unsigned x_shortint_unsigned; int x_int; int unsigned x_int_unsigned; longint x_longint; longint unsigned x_longint_unsigned; `ifndef NO_TIME time x_time; `endif `ifndef NO_INTEGER integer x_integer; `endif real x_real; `ifndef NO_SHORTREAL shortreal x_shortreal; `endif chandle x_chandle; string x_string; bit x_bit; logic x_logic; byte_t x_byte_t; byte_unsigned_t x_byte_unsigned_t; shortint_t x_shortint_t; shortint_unsigned_t x_shortint_unsigned_t; int_t x_int_t; int_unsigned_t x_int_unsigned_t; longint_t x_longint_t; longint_unsigned_t x_longint_unsigned_t; `ifndef NO_TIME time_t x_time_t; `endif `ifndef NO_INTEGER integer_t x_integer_t; `endif real_t x_real_t; `ifndef NO_SHORTREAL shortreal_t x_shortreal_t; `endif chandle_t x_chandle_t; string_t x_string_t; bit_t x_bit_t; logic_t x_logic_t; bit [ 0:0] x_bit_1; bit [ 31:0] x_bit_32; bit [ 32:0] x_bit_33; bit [ 63:0] x_bit_64; bit [ 64:0] x_bit_65; bit [127:0] x_bit_128; struct_2_state_1 x_struct_2_state_1; struct_2_state_32 x_struct_2_state_32; struct_2_state_33 x_struct_2_state_33; struct_2_state_64 x_struct_2_state_64; struct_2_state_65 x_struct_2_state_65; struct_2_state_128 x_struct_2_state_128; union_2_state_1 x_union_2_state_1; union_2_state_32 x_union_2_state_32; union_2_state_33 x_union_2_state_33; union_2_state_64 x_union_2_state_64; union_2_state_65 x_union_2_state_65; union_2_state_128 x_union_2_state_128; logic [ 0:0] x_logic_1; logic [ 31:0] x_logic_32; logic [ 32:0] x_logic_33; logic [ 63:0] x_logic_64; logic [ 64:0] x_logic_65; logic [127:0] x_logic_128; struct_4_state_1 x_struct_4_state_1; struct_4_state_32 x_struct_4_state_32; struct_4_state_33 x_struct_4_state_33; struct_4_state_64 x_struct_4_state_64; struct_4_state_65 x_struct_4_state_65; struct_4_state_128 x_struct_4_state_128; union_4_state_1 x_union_4_state_1; union_4_state_32 x_union_4_state_32; union_4_state_33 x_union_4_state_33; union_4_state_64 x_union_4_state_64; union_4_state_65 x_union_4_state_65; union_4_state_128 x_union_4_state_128; // Basic types as per IEEE 1800-2023 35.5.6 i_byte(x_byte); if (x_byte !== 8'd10 - 8'(i)) $stop; i_byte_unsigned(x_byte_unsigned); if (x_byte_unsigned !== 8'd20 - 8'(i)) $stop; i_shortint(x_shortint); if (x_shortint !== 16'd30 - 16'(i)) $stop; i_shortint_unsigned(x_shortint_unsigned); if (x_shortint_unsigned !== 16'd40 - 16'(i)) $stop; i_int(x_int); if (x_int !== 32'd50 - 32'(i)) $stop; i_int_unsigned(x_int_unsigned); if (x_int_unsigned !== 32'd60 - 32'(i)) $stop; i_longint(x_longint); if (x_longint !== 64'd70 - 64'(i)) $stop; i_longint_unsigned(x_longint_unsigned); if (x_longint_unsigned !== 64'd80 - 64'(i)) $stop; `ifndef NO_TIME i_time(x_time); if (x_time !== 64'd90 - 64'(i)) $stop; `endif `ifndef NO_INTEGER i_integer(x_integer); if (x_integer !== 32'd100- 32'(i)) $stop; `endif i_real(x_real); if (x_real != -1.0*i - 0.5 ) $stop; `ifndef NO_SHORTREAL i_shortreal(x_shortreal); if (x_shortreal != -1.0*i - 0.25) $stop; `endif if (~i[0]) begin i_chandle(x_chandle); if (x_chandle !== `NULL) $stop; i_string(x_string); if (x_string != "World") $stop; end else begin i_chandle(x_chandle); if (x_chandle === `NULL) $stop; i_string(x_string); if (x_string != "Hello") $stop; end i_bit(x_bit); if (x_bit !== ~i[0]) $stop; i_logic(x_logic); if (x_logic !== i[0]) $stop; // Basic types via typedefs i_byte_t(x_byte_t); if (x_byte_t !== 8'd10 - 8'(2*i)) $stop; i_byte_unsigned_t(x_byte_unsigned_t); if (x_byte_unsigned_t !== 8'd20 - 8'(2*i)) $stop; i_shortint_t(x_shortint_t); if (x_shortint_t !== 16'd30 - 16'(2*i)) $stop; i_shortint_unsigned_t(x_shortint_unsigned_t); if (x_shortint_unsigned_t !== 16'd40 - 16'(2*i)) $stop; i_int_t(x_int_t); if (x_int_t !== 32'd50 - 32'(2*i)) $stop; i_int_unsigned_t(x_int_unsigned_t); if (x_int_unsigned_t !== 32'd60 - 32'(2*i)) $stop; i_longint_t(x_longint_t); if (x_longint_t !== 64'd70 - 64'(2*i)) $stop; i_longint_unsigned_t(x_longint_unsigned_t); if (x_longint_unsigned_t !== 64'd80 - 64'(2*i)) $stop; `ifndef NO_TIME i_time_t(x_time_t); if (x_time_t !== 64'd90 - 64'(2*i)) $stop; `endif `ifndef NO_INTEGER i_integer_t(x_integer_t); if (x_integer_t !== 32'd100- 32'(2*i)) $stop; `endif i_real_t(x_real_t); if (x_real_t != -1.0*(2*i) - 0.5 ) $stop; `ifndef NO_SHORTREAL i_shortreal_t(x_shortreal_t); if (x_shortreal_t != -1.0*(2*i) - 0.25) $stop; `endif if (~i[0]) begin i_chandle_t(x_chandle_t); if (x_chandle_t !== `NULL) $stop; i_string_t(x_string_t); if (x_string_t != "World") $stop; end else begin i_chandle_t(x_chandle_t); if (x_chandle_t === `NULL) $stop; i_string_t(x_string_t); if (x_string_t != "Hello") $stop; end i_bit_t(x_bit_t); if (x_bit_t !== ~i[0]) $stop; i_logic_t(x_logic_t); if (x_logic_t !== i[0]) $stop; // 2-state packed arrays i_array_2_state_1(x_bit_1); if (x_bit_1 !== ~i[0] ) $stop; i_array_2_state_32(x_bit_32); if (x_bit_32 !== ~32'd0 << i) $stop; i_array_2_state_33(x_bit_33); if (x_bit_33 !== ~33'd0 << i) $stop; i_array_2_state_64(x_bit_64); if (x_bit_64 !== ~64'd0 << i) $stop; i_array_2_state_65(x_bit_65); if (x_bit_65 !== ~65'd0 << i) $stop; i_array_2_state_128(x_bit_128); if (x_bit_128 !== ~128'd0<< i) $stop; // 2-state packed structures i_struct_2_state_1(x_struct_2_state_1); if (x_struct_2_state_1 !== ~i[0] ) $stop; i_struct_2_state_32(x_struct_2_state_32); if (x_struct_2_state_32 !== ~32'd0 << i) $stop; i_struct_2_state_33(x_struct_2_state_33); if (x_struct_2_state_33 !== ~33'd0 << i) $stop; i_struct_2_state_64(x_struct_2_state_64); if (x_struct_2_state_64 !== ~64'd0 << i) $stop; i_struct_2_state_65(x_struct_2_state_65); if (x_struct_2_state_65 !== ~65'd0 << i) $stop; i_struct_2_state_128(x_struct_2_state_128); if (x_struct_2_state_128 !== ~128'd0<< i) $stop; // 2-state packed unions i_union_2_state_1(x_union_2_state_1); if (x_union_2_state_1 !== ~i[0] ) $stop; i_union_2_state_32(x_union_2_state_32); if (x_union_2_state_32 !== ~32'd0 << i) $stop; i_union_2_state_33(x_union_2_state_33); if (x_union_2_state_33 !== ~33'd0 << i) $stop; i_union_2_state_64(x_union_2_state_64); if (x_union_2_state_64 !== ~64'd0 << i) $stop; i_union_2_state_65(x_union_2_state_65); if (x_union_2_state_65 !== ~65'd0 << i) $stop; i_union_2_state_128(x_union_2_state_128); if (x_union_2_state_128 !== ~128'd0<< i) $stop; // 4-state packed arrays i_array_4_state_1(x_logic_1); if (x_logic_1 !== ~i[0] ) $stop; i_array_4_state_32(x_logic_32); if (x_logic_32 !== ~32'd0 << i) $stop; i_array_4_state_33(x_logic_33); if (x_logic_33 !== ~33'd0 << i) $stop; i_array_4_state_64(x_logic_64); if (x_logic_64 !== ~64'd0 << i) $stop; i_array_4_state_65(x_logic_65); if (x_logic_65 !== ~65'd0 << i) $stop; i_array_4_state_128(x_logic_128); if (x_logic_128 !== ~128'd0<< i) $stop; // 4-state packed structures i_struct_4_state_1(x_struct_4_state_1); if (x_struct_4_state_1 !== ~i[0] ) $stop; i_struct_4_state_32(x_struct_4_state_32); if (x_struct_4_state_32 !== ~32'd0 << i) $stop; i_struct_4_state_33(x_struct_4_state_33); if (x_struct_4_state_33 !== ~33'd0 << i) $stop; i_struct_4_state_64(x_struct_4_state_64); if (x_struct_4_state_64 !== ~64'd0 << i) $stop; i_struct_4_state_65(x_struct_4_state_65); if (x_struct_4_state_65 !== ~65'd0 << i) $stop; i_struct_4_state_128(x_struct_4_state_128); if (x_struct_4_state_128 !== ~128'd0<< i) $stop; // 4-state packed unions i_union_4_state_1(x_union_4_state_1); if (x_union_4_state_1 !== ~i[0] ) $stop; i_union_4_state_32(x_union_4_state_32); if (x_union_4_state_32 !== ~32'd0 << i) $stop; i_union_4_state_33(x_union_4_state_33); if (x_union_4_state_33 !== ~33'd0 << i) $stop; i_union_4_state_64(x_union_4_state_64); if (x_union_4_state_64 !== ~64'd0 << i) $stop; i_union_4_state_65(x_union_4_state_65); if (x_union_4_state_65 !== ~65'd0 << i) $stop; i_union_4_state_128(x_union_4_state_128); if (x_union_4_state_128 !== ~128'd0<< i) $stop; // Check the exports check_exports(); end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_fuzz_negwidth_bad.out0000644000542200017500000000174515101701376023646 0ustar mahmoudyfreeshell%Error: t/t_fuzz_negwidth_bad.v:9:9: Unsupported: Width of number exceeds implementation limit: 1231232312312312'd1 (IEEE 1800-2023 6.9.1) 9 | int c = 1231232312312312'd1; | ^~~~~~~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_fuzz_negwidth_bad.v:10:9: Syntax error: size cannot be provided with '0/'1/'x/'z: 12'1 (IEEE 1800-2023 5.7.1) 10 | int e = 12'1; | ^~~~ %Error: t/t_fuzz_negwidth_bad.v:11:9: Syntax error: size cannot be provided with '0/'1/'x/'z: 12'0 (IEEE 1800-2023 5.7.1) 11 | int f = 12'0; | ^~~~ %Error: t/t_fuzz_negwidth_bad.v:12:9: Syntax error: size cannot be provided with '0/'1/'x/'z: 12'z (IEEE 1800-2023 5.7.1) 12 | int g = 12'z; | ^~~~ %Error: t/t_fuzz_negwidth_bad.v:13:9: Syntax error: size cannot be provided with '0/'1/'x/'z: 12'x (IEEE 1800-2023 5.7.1) 13 | int h = 12'x; | ^~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_json_only_begin_hier.out0000644000542200017500000001470015101701376024331 0ustar mahmoudyfreeshell{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"UNLINKED", "modulesp": [ {"type":"MODULE","name":"test","addr":"(E)","loc":"d,22:8,22:12","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"test","level":2,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"N","addr":"(F)","loc":"d,24:12,24:13","dtypep":"(G)","origName":"N","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":true,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"GENVAR","dtypeName":"integer","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"GENBLOCK","name":"FOR_GENERATE","addr":"(H)","loc":"d,25:14,25:17","implied":true,"unnamed":false,"genforp": [],"itemsp": []}, {"type":"GENBLOCK","name":"FOR_GENERATE[0]","addr":"(I)","loc":"d,27:21,27:31","implied":false,"unnamed":false,"genforp": [], "itemsp": [ {"type":"CELL","name":"submod_for","addr":"(J)","loc":"d,27:21,27:31","origName":"submod_for","recursive":false,"modp":"(K)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []}, {"type":"GENBLOCK","name":"genblk1","addr":"(L)","loc":"d,28:19,28:24","implied":false,"unnamed":true,"genforp": [], "itemsp": [ {"type":"CELL","name":"submod_2","addr":"(M)","loc":"d,29:25,29:33","origName":"submod_2","recursive":false,"modp":"(K)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} ]}, {"type":"CELL","name":"submod_3","addr":"(N)","loc":"d,31:21,31:29","origName":"submod_3","recursive":false,"modp":"(K)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} ]}, {"type":"GENBLOCK","name":"FOR_GENERATE[1]","addr":"(O)","loc":"d,27:21,27:31","implied":false,"unnamed":false,"genforp": [], "itemsp": [ {"type":"CELL","name":"submod_for","addr":"(P)","loc":"d,27:21,27:31","origName":"submod_for","recursive":false,"modp":"(K)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []}, {"type":"GENBLOCK","name":"genblk1","addr":"(Q)","loc":"d,28:19,28:24","implied":false,"unnamed":true,"genforp": [], "itemsp": [ {"type":"CELL","name":"submod_2","addr":"(R)","loc":"d,29:25,29:33","origName":"submod_2","recursive":false,"modp":"(K)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} ]}, {"type":"CELL","name":"submod_3","addr":"(S)","loc":"d,31:21,31:29","origName":"submod_3","recursive":false,"modp":"(K)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} ]} ]}, {"type":"MODULE","name":"submod","addr":"(K)","loc":"d,10:8,10:14","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"submod","level":3,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"GENBLOCK","name":"submod_gen","addr":"(T)","loc":"d,12:19,12:29","implied":false,"unnamed":false,"genforp": [], "itemsp": [ {"type":"VAR","name":"l1_sig","addr":"(U)","loc":"d,13:14,13:20","dtypep":"(V)","origName":"l1_sig","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"GENBLOCK","name":"nested_gen","addr":"(W)","loc":"d,14:23,14:33","implied":false,"unnamed":false,"genforp": [], "itemsp": [ {"type":"CELL","name":"submod_nested","addr":"(X)","loc":"d,15:21,15:34","origName":"submod_nested","recursive":false,"modp":"(Y)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} ]}, {"type":"CELL","name":"submod_l1","addr":"(Z)","loc":"d,17:17,17:26","origName":"submod_l1","recursive":false,"modp":"(Y)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} ]}, {"type":"CELL","name":"submod_l0","addr":"(AB)","loc":"d,19:13,19:22","origName":"submod_l0","recursive":false,"modp":"(Y)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} ]}, {"type":"MODULE","name":"submod2","addr":"(Y)","loc":"d,7:8,7:15","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"submod2","level":4,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],"stmtsp": []} ],"filesp": [], "miscsp": [ {"type":"TYPETABLE","name":"","addr":"(C)","loc":"a,0:0,0:0","constraintRefp":"UNLINKED","emptyQueuep":"UNLINKED","queueIndexp":"UNLINKED","streamp":"UNLINKED","voidp":"UNLINKED", "typesp": [ {"type":"BASICDTYPE","name":"integer","addr":"(G)","loc":"d,24:12,24:13","dtypep":"(G)","keyword":"integer","range":"31:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(V)","loc":"d,13:14,13:20","dtypep":"(V)","keyword":"logic","generic":true,"rangep": []} ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ {"type":"MODULE","name":"@CONST-POOL@","addr":"(BB)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], "stmtsp": [ {"type":"SCOPE","name":"@CONST-POOL@","addr":"(CB)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(BB)","varsp": [],"blocksp": [],"inlinesp": []} ]} ]} ]} verilator-5.042/test_regress/t/t_class_virtual_chain_ctor.v0000644000542200017500000000150215101701376024642 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Check that an abstract class' contstructor // can be called indirectly from a constructor of a derived class. // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Ilya Barkov // SPDX-License-Identifier: CC0-1.0 // It's illegal to call // VBase b = new; // see t_class_virtual_bad virtual class VBase; function new(); endfunction endclass // Another constructor of an abstact class in the chain virtual class VChild1 extends VBase; function new(); super.new(); endfunction endclass // It shall be perfectly fine to create an instance of a // non-abstract VChild2 class VChild2 extends VChild1; function new(); super.new(); endfunction endclass module t; initial begin VChild2 c = new; end endmodule verilator-5.042/test_regress/t/t_fuzz_eqne_bad.out0000644000542200017500000000123615101701376022760 0ustar mahmoudyfreeshell%Error: t/t_fuzz_eqne_bad.v:9:9: Size of range is '[0]', must be positive integer (IEEE 1800-2023 7.4.2) : ... note: In instance 't' 9 | reg a[0]; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_fuzz_eqne_bad.v:12:19: Comparison requires matching data types : ... note: In instance 't' : ... Left-hand data type: 'logic$[0:-1]' : ... Right-hand data type: 'logic' 12 | initial c = (a != &b); | ^~ %Error: Exiting due to verilator-5.042/test_regress/t/t_udp_bad_input_num.out0000644000542200017500000000050615101701376023637 0ustar mahmoudyfreeshell%Error: t/t_udp_bad_input_num.v:14:9: Incorrect number of input values, expected 3, got 2 : ... note: In instance 'top' 14 | 1 0 : 0; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_func_redef.py0000755000542200017500000000071415101701376022070 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.passes() verilator-5.042/test_regress/t/t_display_l.py0000755000542200017500000000073415101701376021752 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_dtype_compare.v0000644000542200017500000000407015101701376023462 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; // Typedefs typedef int myint_t; typedef int myint2_t; typedef int myq_t[$]; typedef int myval_t; typedef string mykey_t; initial begin // Scalar int a = 1, b = 1; // Unpacked array int u1[2] = '{1, 2}; int u2[2] = '{1, 2}; int m1[2][2] = '{{1, 2}, {3, 4}}; int m2[2][2] = '{{1, 2}, {3, 4}}; // Dynamic array int d1[] = new[2]; int d2[] = new[2]; // Queue int q1[$] = '{10, 20}; int q2[$] = '{10, 20}; // Associative array int aa1[string]; int aa2[string]; // Typedef array myint_t t1[2] = '{1, 2}; myint2_t t2[2] = '{1, 2}; // Typedef queue myq_t tq1 = '{1, 2}; int tq2[$] = '{1, 2}; // Typedef associative array myval_t aa_typedef1[mykey_t]; int aa_typedef2[string]; // Typedef scalar bit signed [31:0] b1 = 1; int i1 = 1; d1[0] = 5; d1[1] = 6; d2[0] = 5; d2[1] = 6; aa1["a"] = 1; aa2["a"] = 1; aa1["b"] = 2; aa2["b"] = 2; aa_typedef1["foo"] = 123; aa_typedef2["foo"] = 123; if (a != b) $fatal(0, "Scalar comparison failed"); if (u1 != u2) $fatal(0, "Unpacked 1D array comparison failed"); if (m1 != m2) $fatal(0, "Unpacked multi-dimensional array comparison failed"); if (d1 != d2) $fatal(0, "Dynamic array comparison failed"); if (q1 != q2) $fatal(0, "Queue comparison failed"); if (aa1 != aa2) $fatal(0, "Associative array comparison failed"); if (t1 != t2) $fatal(0, "Typedef unpacked array comparison failed"); if (tq1 != tq2) $fatal(0, "Typedef queue comparison failed"); if (aa_typedef1 != aa_typedef2) $fatal(0, "Typedef associative array comparison failed"); if (b1 != i1) $fatal(0, "bit[31:0] vs int comparison failed"); $display("*-* All Finished *-*"); $finish; end endmodule verilator-5.042/test_regress/t/t_struct_portsel.py0000755000542200017500000000073415101701376023066 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_increment_bad.v0000644000542200017500000000120415101701376022367 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; int pos; int a; int b; int array[2][2] = '{ '{0, 1}, '{2, 3}}; string test_string = "abcd"; initial begin if (0 && test_string[pos++] != "e"); if (1 || pos-- != 1); if (a <-> --b); if (0 -> ++b); pos = (a > 0) ? a++ : --b; pos = array[0][0]++; end assert property (@(posedge clk) a++ >= 0); endmodule verilator-5.042/test_regress/t/t_lint_iface_topmodule1.py0000755000542200017500000000070615101701376024237 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.042/test_regress/t/t_no_sel_assign_merge_in_cpp.v0000644000542200017500000000065115101701376025134 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t_no_sel_assign_merge_in_cpp ( input wire [(8*39)-1:0] d_i, output wire [(8*32)-1:0] d_o ); for (genvar i = 0; i < 8; i = i + 1) begin assign d_o[i*32 +: 32] = d_i[i*39 +: 32]; end endmodule verilator-5.042/test_regress/t/t_func_const.py0000755000542200017500000000073415101701376022133 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_ub_misaligned_address.py0000755000542200017500000000143715101701376025460 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_ub_misaligned_address.v" test.compile(verilator_flags2=["--binary --trace-vcd", "--runtime-debug"]) test.execute(aslr_off=True) # Make sure that there are no additional messages (such as runtime messages # regarding undefined behavior).test.files_identical(test.obj_dir + "/vlt_sim.log", test.golden_filename, "logfile") test.passes() verilator-5.042/test_regress/t/t_gate_elim.v0000644000542200017500000000501415101701376021526 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg b; wire vconst1 = 1'b0; wire vconst2 = !(vconst1); wire vconst3 = !vconst2; wire vconst = vconst3; wire qa; wire qb; wire qc; wire qd; wire qe; ta ta (.b(b), .vconst(vconst), .q(qa)); tb tb (.clk(clk), .vconst(vconst), .q(qb)); tc tc (.b(b), .vconst(vconst), .q(qc)); td td (.b(b), .vconst(vconst), .q(qd)); te te (.clk(clk), .b(b), .vconst(vconst), .q(qe)); always @ (posedge clk) begin `ifdef TEST_VERBOSE $display("%b",{qa,qb,qc,qd,qe}); `endif if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin b <= 1'b1; end if (cyc==2) begin if (qa!=1'b1) $stop; if (qb!=1'b0) $stop; if (qd!=1'b0) $stop; b <= 1'b0; end if (cyc==3) begin if (qa!=1'b0) $stop; if (qb!=1'b0) $stop; if (qd!=1'b0) $stop; if (qe!=1'b0) $stop; b <= 1'b1; end if (cyc==4) begin if (qa!=1'b1) $stop; if (qb!=1'b0) $stop; if (qd!=1'b0) $stop; if (qe!=1'b1) $stop; b <= 1'b0; end if (cyc==5) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module ta ( input vconst, input b, output reg q); always @ (/*AS*/b or vconst) begin q = vconst | b; end endmodule module tb ( input vconst, input clk, output reg q); always @ (posedge clk) begin q <= vconst; end endmodule module tc ( input vconst, input b, output reg q); always @ (posedge vconst) begin q <= b; $stop; end endmodule module td ( input vconst, input b, output reg q); always @ (/*AS*/vconst) begin q = vconst; end endmodule module te ( input clk, input vconst, input b, output reg q); reg qmid; always @ (posedge vconst or posedge clk) begin qmid <= b; end always @ (posedge clk or posedge vconst) begin q <= qmid; end endmodule verilator-5.042/test_regress/t/t_class_misstatic_bad.out0000644000542200017500000000156015101701376024137 0ustar mahmoudyfreeshell%Error: t/t_class_misstatic_bad.v:31:5: Cannot call non-static member function 'nonstatic' without object (IEEE 1800-2023 8.10) : ... note: In instance 't' 31 | nonstatic(); | ^~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_class_misstatic_bad.v:38:10: Cannot call non-static member function 'nonstatic' without object (IEEE 1800-2023 8.10) : ... note: In instance 't' 38 | Cls::nonstatic(); | ^~~~~~~~~ %Error: t/t_class_misstatic_bad.v:44:10: Cannot call non-static member function 'nonstatic' without object (IEEE 1800-2023 8.10) : ... note: In instance 't' 44 | Cls::nonstatic(); | ^~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_flag_timescale_override.py0000755000542200017500000000105215101701376024622 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["-timescale-override 1ms/1us"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_timing_suspend_two_retrigger.py0000755000542200017500000000076315101701376025767 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_scope_no_inline.vlt0000644000542200017500000000057615101701376024471 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `verilator_config // Turn tracing off for all scopes by default tracing_off -scope "*" -levels 0 // Turn it back on only for *.mid_b.* and below tracing_on -scope "*.mid_b.*" -levels 0 verilator-5.042/test_regress/t/t_class_new_this.py0000755000542200017500000000073415101701376022777 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_defaultparams.v0000644000542200017500000000225015101701376023614 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 // verilator lint_off NORETURN class c0 #(type T= real); static function T f(); endfunction endclass class c2 #(type REQ=int, type RSP= int, type IMP=int); function new (IMP imp); endfunction endclass class c3 #(type REQ, type RSP, type IMP=RSP); function new (IMP imp); endfunction endclass class c1 #(type REQ= int, RSP=REQ); typedef c1 #( REQ , RSP) this_type; typedef c0 #(this_type) type_id; c2 #(REQ, RSP, this_type) c2inst; function new (string name, int parent); c2inst = new (this); endfunction c3 #(REQ, this_type) c3inst; endclass `define test \ c1 #(real) c1inst1;\ c1 #(real, real) c1inst2;\ c1 #(real, int) c1inst3;\ c1 #() c1inst4;\ c1 c1inst5; `test interface interf; // `test endinterface module t; // `test interf interf_inst(); endmodule class topc; // `test endclass class paramcl; endclass: paramcl class c5; c1 #(paramcl) seq; function void f(); seq = c1 #(paramcl)::type_id::f(); endfunction: f endclass c5 c5inst; verilator-5.042/test_regress/t/t_lint_badvltpragma_bad.py0000755000542200017500000000143315101701376024267 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.extract(in_filename=test.top_filename, out_filename=test.root + "/docs/gen/ex_BADVLTPRAGMA_faulty.rst", lines="7") test.extract(in_filename=test.golden_filename, out_filename=test.root + "/docs/gen/ex_BADVLTPRAGMA_msg.rst", lines="1-3") test.passes() verilator-5.042/test_regress/t/t_trace_ascendingrange_saif.out0000644000542200017500000046123315101701376025303 0ustar mahmoudyfreeshell// Generated by verilated_saif (SAIFILE (SAIFVERSION "2.0") (DIRECTION "backward") (PROGRAM_NAME "Verilator") (DIVIDER / ) (TIMESCALE 1ps) (DURATION 30) (INSTANCE top (NET (clk (T0 20) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 5)) ) (INSTANCE t (NET (P\[0\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P\[1\] (T0 0) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1)) (P\[2\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P\[3\] (T0 0) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1)) (P\[4\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P\[5\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P\[6\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P\[7\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (clk (T0 20) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[0\] (T0 20) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 3)) (cyc\[1\] (T0 20) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[2\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[3\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[4\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[5\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (Q\[0\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (Q\[1\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (Q\[2\] (T0 0) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1)) (Q\[3\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (Q\[4\] (T0 0) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1)) (Q\[5\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (Q\[6\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (Q\[7\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (v_a (T0 20) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_b\[0\] (T0 20) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_b\[1\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_c\[0\] (T0 20) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_c\[1\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_c\[2\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_c\[3\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_c\[4\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_c\[5\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_c\[6\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_c\[7\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_d\[0\] (T0 20) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_d\[1\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_d\[2\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_d\[3\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_d\[4\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_d\[5\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_d\[6\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_d\[7\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_d\[8\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_e\[0\] (T0 20) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_e\[1\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_e\[2\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_e\[3\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_e\[4\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_e\[5\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_e\[6\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_e\[7\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_e\[8\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_e\[9\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_e\[10\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_e\[11\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_e\[12\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_e\[13\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_e\[14\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_e\[15\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_f\[0\] (T0 20) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_f\[1\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_f\[2\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_f\[3\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_f\[4\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_f\[5\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_f\[6\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_f\[7\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_f\[8\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_f\[9\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_f\[10\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_f\[11\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_f\[12\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_f\[13\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_f\[14\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_f\[15\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_f\[16\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_g\[0\] (T0 20) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_g\[1\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_g\[2\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_g\[3\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_g\[4\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_g\[5\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_g\[6\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_g\[7\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_g\[8\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_g\[9\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_g\[10\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_g\[11\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_g\[12\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_g\[13\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_g\[14\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_g\[15\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_g\[16\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_g\[17\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_g\[18\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_g\[19\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_g\[20\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_g\[21\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_g\[22\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_g\[23\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_g\[24\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_g\[25\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_g\[26\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_g\[27\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_g\[28\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_g\[29\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_g\[30\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_g\[31\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_h\[0\] (T0 20) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_h\[1\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_h\[2\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_h\[3\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_h\[4\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_h\[5\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_h\[6\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_h\[7\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_h\[8\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_h\[9\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_h\[10\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_h\[11\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_h\[12\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_h\[13\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_h\[14\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_h\[15\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_h\[16\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_h\[17\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_h\[18\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_h\[19\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_h\[20\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_h\[21\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_h\[22\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_h\[23\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_h\[24\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_h\[25\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_h\[26\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_h\[27\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_h\[28\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_h\[29\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_h\[30\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_h\[31\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_h\[32\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[0\] (T0 20) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_i\[1\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_i\[2\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[3\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[4\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[5\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[6\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[7\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[8\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[9\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[10\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[11\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[12\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[13\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[14\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[15\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[16\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[17\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[18\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[19\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[20\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[21\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[22\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[23\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[24\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[25\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[26\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[27\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[28\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[29\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[30\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[31\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[32\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[33\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[34\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[35\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[36\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[37\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[38\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[39\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[40\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[41\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[42\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[43\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[44\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[45\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[46\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[47\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[48\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[49\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[50\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[51\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[52\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[53\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[54\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[55\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[56\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[57\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[58\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[59\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[60\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[61\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[62\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_i\[63\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[0\] (T0 20) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_j\[1\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_j\[2\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[3\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[4\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[5\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[6\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[7\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[8\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[9\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[10\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[11\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[12\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[13\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[14\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[15\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[16\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[17\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[18\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[19\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[20\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[21\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[22\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[23\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[24\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[25\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[26\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[27\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[28\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[29\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[30\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[31\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[32\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[33\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[34\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[35\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[36\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[37\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[38\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[39\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[40\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[41\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[42\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[43\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[44\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[45\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[46\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[47\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[48\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[49\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[50\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[51\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[52\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[53\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[54\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[55\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[56\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[57\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[58\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[59\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[60\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[61\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[62\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[63\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_j\[64\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[0\] (T0 20) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_k\[1\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_k\[2\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[3\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[4\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[5\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[6\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[7\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[8\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[9\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[10\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[11\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[12\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[13\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[14\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[15\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[16\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[17\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[18\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[19\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[20\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[21\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[22\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[23\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[24\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[25\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[26\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[27\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[28\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[29\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[30\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[31\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[32\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[33\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[34\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[35\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[36\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[37\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[38\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[39\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[40\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[41\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[42\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[43\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[44\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[45\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[46\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[47\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[48\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[49\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[50\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[51\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[52\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[53\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[54\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[55\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[56\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[57\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[58\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[59\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[60\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[61\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[62\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[63\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[64\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[65\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[66\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[67\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[68\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[69\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[70\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[71\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[72\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[73\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[74\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[75\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[76\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[77\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[78\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[79\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[80\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[81\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[82\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[83\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[84\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[85\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[86\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[87\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[88\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[89\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[90\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[91\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[92\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[93\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[94\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[95\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[96\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[97\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[98\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[99\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[100\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[101\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[102\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[103\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[104\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[105\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[106\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[107\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[108\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[109\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[110\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[111\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[112\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[113\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[114\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[115\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[116\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[117\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[118\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[119\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[120\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[121\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[122\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[123\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[124\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[125\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[126\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_k\[127\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[0\] (T0 20) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_l\[1\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_l\[2\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[3\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[4\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[5\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[6\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[7\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[8\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[9\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[10\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[11\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[12\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[13\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[14\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[15\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[16\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[17\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[18\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[19\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[20\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[21\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[22\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[23\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[24\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[25\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[26\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[27\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[28\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[29\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[30\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[31\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[32\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[33\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[34\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[35\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[36\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[37\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[38\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[39\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[40\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[41\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[42\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[43\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[44\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[45\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[46\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[47\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[48\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[49\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[50\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[51\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[52\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[53\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[54\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[55\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[56\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[57\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[58\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[59\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[60\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[61\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[62\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[63\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[64\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[65\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[66\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[67\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[68\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[69\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[70\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[71\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[72\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[73\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[74\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[75\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[76\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[77\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[78\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[79\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[80\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[81\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[82\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[83\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[84\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[85\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[86\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[87\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[88\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[89\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[90\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[91\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[92\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[93\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[94\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[95\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[96\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[97\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[98\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[99\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[100\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[101\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[102\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[103\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[104\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[105\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[106\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[107\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[108\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[109\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[110\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[111\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[112\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[113\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[114\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[115\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[116\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[117\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[118\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[119\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[120\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[121\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[122\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[123\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[124\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[125\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[126\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[127\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_l\[128\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[0\] (T0 20) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_m\[1\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_m\[2\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[3\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[4\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[5\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[6\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[7\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[8\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[9\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[10\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[11\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[12\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[13\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[14\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[15\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[16\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[17\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[18\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[19\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[20\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[21\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[22\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[23\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[24\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[25\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[26\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[27\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[28\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[29\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[30\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[31\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[32\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[33\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[34\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[35\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[36\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[37\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[38\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[39\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[40\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[41\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[42\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[43\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[44\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[45\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[46\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[47\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[48\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[49\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[50\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[51\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[52\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[53\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[54\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[55\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[56\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[57\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[58\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[59\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[60\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[61\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[62\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[63\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[64\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[65\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[66\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[67\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[68\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[69\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[70\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[71\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[72\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[73\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[74\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[75\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[76\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[77\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[78\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[79\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[80\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[81\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[82\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[83\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[84\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[85\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[86\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[87\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[88\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[89\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[90\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[91\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[92\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[93\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[94\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[95\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[96\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[97\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[98\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[99\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[100\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[101\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[102\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[103\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[104\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[105\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[106\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[107\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[108\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[109\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[110\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[111\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[112\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[113\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[114\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[115\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[116\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[117\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[118\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[119\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[120\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[121\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[122\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[123\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[124\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[125\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[126\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[127\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[128\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[129\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[130\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[131\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[132\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[133\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[134\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[135\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[136\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[137\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[138\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[139\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[140\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[141\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[142\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[143\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[144\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[145\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[146\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[147\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[148\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[149\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[150\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[151\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[152\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[153\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[154\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[155\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[156\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[157\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[158\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[159\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[160\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[161\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[162\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[163\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[164\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[165\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[166\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[167\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[168\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[169\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[170\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[171\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[172\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[173\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[174\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[175\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[176\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[177\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[178\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[179\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[180\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[181\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[182\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[183\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[184\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[185\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[186\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[187\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[188\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[189\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[190\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[191\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[192\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[193\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[194\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[195\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[196\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[197\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[198\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[199\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[200\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[201\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[202\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[203\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[204\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[205\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[206\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[207\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[208\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[209\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[210\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[211\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[212\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[213\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[214\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[215\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[216\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[217\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[218\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[219\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[220\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[221\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[222\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[223\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[224\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[225\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[226\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[227\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[228\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[229\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[230\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[231\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[232\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[233\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[234\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[235\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[236\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[237\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[238\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[239\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[240\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[241\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[242\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[243\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[244\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[245\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[246\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[247\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[248\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[249\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[250\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[251\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[252\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[253\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[254\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_m\[255\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[0\] (T0 20) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_n\[1\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_n\[2\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[3\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[4\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[5\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[6\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[7\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[8\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[9\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[10\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[11\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[12\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[13\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[14\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[15\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[16\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[17\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[18\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[19\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[20\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[21\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[22\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[23\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[24\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[25\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[26\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[27\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[28\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[29\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[30\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[31\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[32\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[33\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[34\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[35\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[36\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[37\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[38\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[39\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[40\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[41\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[42\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[43\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[44\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[45\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[46\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[47\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[48\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[49\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[50\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[51\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[52\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[53\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[54\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[55\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[56\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[57\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[58\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[59\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[60\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[61\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[62\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[63\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[64\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[65\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[66\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[67\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[68\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[69\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[70\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[71\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[72\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[73\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[74\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[75\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[76\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[77\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[78\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[79\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[80\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[81\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[82\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[83\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[84\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[85\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[86\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[87\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[88\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[89\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[90\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[91\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[92\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[93\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[94\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[95\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[96\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[97\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[98\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[99\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[100\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[101\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[102\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[103\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[104\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[105\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[106\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[107\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[108\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[109\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[110\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[111\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[112\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[113\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[114\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[115\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[116\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[117\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[118\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[119\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[120\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[121\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[122\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[123\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[124\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[125\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[126\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[127\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[128\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[129\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[130\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[131\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[132\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[133\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[134\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[135\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[136\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[137\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[138\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[139\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[140\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[141\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[142\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[143\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[144\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[145\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[146\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[147\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[148\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[149\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[150\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[151\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[152\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[153\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[154\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[155\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[156\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[157\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[158\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[159\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[160\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[161\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[162\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[163\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[164\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[165\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[166\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[167\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[168\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[169\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[170\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[171\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[172\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[173\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[174\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[175\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[176\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[177\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[178\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[179\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[180\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[181\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[182\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[183\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[184\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[185\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[186\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[187\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[188\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[189\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[190\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[191\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[192\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[193\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[194\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[195\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[196\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[197\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[198\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[199\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[200\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[201\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[202\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[203\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[204\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[205\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[206\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[207\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[208\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[209\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[210\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[211\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[212\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[213\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[214\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[215\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[216\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[217\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[218\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[219\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[220\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[221\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[222\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[223\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[224\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[225\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[226\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[227\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[228\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[229\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[230\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[231\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[232\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[233\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[234\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[235\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[236\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[237\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[238\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[239\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[240\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[241\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[242\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[243\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[244\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[245\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[246\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[247\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[248\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[249\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[250\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[251\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[252\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[253\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[254\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[255\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_n\[256\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[0\] (T0 20) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_o\[1\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_o\[2\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[3\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[4\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[5\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[6\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[7\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[8\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[9\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[10\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[11\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[12\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[13\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[14\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[15\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[16\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[17\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[18\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[19\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[20\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[21\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[22\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[23\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[24\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[25\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[26\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[27\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[28\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[29\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[30\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[31\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[32\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[33\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[34\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[35\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[36\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[37\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[38\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[39\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[40\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[41\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[42\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[43\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[44\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[45\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[46\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[47\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[48\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[49\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[50\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[51\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[52\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[53\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[54\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[55\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[56\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[57\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[58\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[59\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[60\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[61\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[62\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[63\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[64\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[65\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[66\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[67\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[68\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[69\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[70\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[71\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[72\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[73\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[74\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[75\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[76\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[77\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[78\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[79\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[80\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[81\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[82\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[83\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[84\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[85\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[86\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[87\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[88\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[89\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[90\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[91\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[92\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[93\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[94\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[95\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[96\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[97\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[98\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[99\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[100\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[101\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[102\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[103\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[104\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[105\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[106\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[107\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[108\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[109\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[110\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[111\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[112\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[113\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[114\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[115\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[116\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[117\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[118\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[119\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[120\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[121\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[122\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[123\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[124\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[125\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[126\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[127\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[128\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[129\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[130\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[131\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[132\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[133\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[134\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[135\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[136\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[137\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[138\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[139\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[140\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[141\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[142\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[143\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[144\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[145\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[146\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[147\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[148\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[149\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[150\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[151\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[152\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[153\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[154\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[155\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[156\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[157\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[158\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[159\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[160\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[161\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[162\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[163\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[164\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[165\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[166\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[167\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[168\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[169\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[170\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[171\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[172\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[173\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[174\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[175\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[176\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[177\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[178\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[179\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[180\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[181\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[182\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[183\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[184\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[185\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[186\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[187\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[188\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[189\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[190\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[191\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[192\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[193\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[194\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[195\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[196\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[197\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[198\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[199\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[200\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[201\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[202\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[203\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[204\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[205\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[206\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[207\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[208\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[209\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[210\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[211\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[212\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[213\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[214\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[215\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[216\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[217\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[218\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[219\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[220\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[221\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[222\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[223\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[224\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[225\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[226\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[227\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[228\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[229\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[230\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[231\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[232\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[233\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[234\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[235\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[236\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[237\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[238\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[239\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[240\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[241\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[242\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[243\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[244\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[245\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[246\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[247\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[248\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[249\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[250\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[251\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[252\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[253\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[254\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[255\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[256\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[257\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[258\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[259\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[260\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[261\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[262\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[263\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[264\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[265\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[266\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[267\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[268\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[269\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[270\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[271\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[272\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[273\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[274\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[275\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[276\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[277\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[278\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[279\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[280\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[281\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[282\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[283\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[284\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[285\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[286\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[287\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[288\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[289\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[290\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[291\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[292\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[293\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[294\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[295\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[296\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[297\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[298\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[299\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[300\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[301\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[302\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[303\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[304\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[305\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[306\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[307\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[308\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[309\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[310\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[311\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[312\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[313\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[314\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[315\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[316\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[317\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[318\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[319\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[320\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[321\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[322\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[323\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[324\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[325\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[326\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[327\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[328\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[329\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[330\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[331\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[332\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[333\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[334\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[335\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[336\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[337\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[338\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[339\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[340\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[341\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[342\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[343\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[344\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[345\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[346\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[347\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[348\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[349\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[350\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[351\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[352\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[353\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[354\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[355\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[356\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[357\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[358\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[359\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[360\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[361\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[362\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[363\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[364\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[365\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[366\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[367\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[368\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[369\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[370\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[371\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[372\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[373\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[374\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[375\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[376\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[377\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[378\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[379\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[380\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[381\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[382\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[383\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[384\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[385\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[386\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[387\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[388\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[389\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[390\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[391\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[392\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[393\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[394\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[395\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[396\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[397\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[398\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[399\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[400\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[401\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[402\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[403\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[404\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[405\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[406\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[407\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[408\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[409\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[410\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[411\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[412\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[413\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[414\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[415\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[416\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[417\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[418\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[419\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[420\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[421\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[422\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[423\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[424\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[425\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[426\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[427\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[428\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[429\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[430\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[431\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[432\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[433\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[434\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[435\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[436\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[437\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[438\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[439\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[440\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[441\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[442\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[443\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[444\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[445\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[446\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[447\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[448\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[449\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[450\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[451\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[452\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[453\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[454\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[455\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[456\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[457\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[458\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[459\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[460\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[461\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[462\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[463\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[464\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[465\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[466\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[467\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[468\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[469\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[470\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[471\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[472\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[473\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[474\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[475\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[476\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[477\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[478\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[479\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[480\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[481\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[482\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[483\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[484\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[485\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[486\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[487\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[488\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[489\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[490\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[491\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[492\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[493\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[494\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[495\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[496\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[497\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[498\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[499\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[500\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[501\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[502\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[503\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[504\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[505\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[506\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[507\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[508\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[509\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[510\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_o\[511\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_p\[0\] (T0 20) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_p\[1\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_p\[2\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_q\[0\] (T0 20) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_q\[1\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_q\[2\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_q\[3\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_q\[4\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_q\[5\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_q\[6\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_q\[7\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_q\[8\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_q\[9\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_q\[10\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_q\[11\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_q\[12\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_q\[13\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_q\[14\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_r\[0\] (T0 20) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_r\[1\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_r\[2\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_r\[3\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_r\[4\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_r\[5\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_r\[6\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_r\[7\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_r\[8\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_r\[9\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_r\[10\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_r\[11\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_r\[12\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_r\[13\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_r\[14\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_r\[15\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_r\[16\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_r\[17\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_r\[18\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_r\[19\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_r\[20\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_r\[21\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_r\[22\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_r\[23\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_r\[24\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_r\[25\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_r\[26\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_r\[27\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_r\[28\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_r\[29\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_r\[30\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[0\] (T0 20) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_s\[1\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_s\[2\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[3\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[4\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[5\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[6\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[7\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[8\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[9\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[10\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[11\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[12\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[13\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[14\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[15\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[16\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[17\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[18\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[19\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[20\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[21\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[22\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[23\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[24\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[25\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[26\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[27\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[28\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[29\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[30\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[31\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[32\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[33\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[34\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[35\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[36\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[37\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[38\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[39\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[40\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[41\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[42\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[43\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[44\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[45\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[46\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[47\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[48\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[49\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[50\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[51\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[52\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[53\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[54\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[55\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[56\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[57\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[58\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[59\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[60\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[61\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_s\[62\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[0\] (T0 20) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_t\[1\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_t\[2\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[3\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[4\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[5\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[6\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[7\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[8\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[9\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[10\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[11\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[12\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[13\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[14\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[15\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[16\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[17\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[18\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[19\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[20\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[21\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[22\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[23\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[24\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[25\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[26\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[27\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[28\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[29\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[30\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[31\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[32\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[33\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[34\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[35\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[36\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[37\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[38\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[39\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[40\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[41\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[42\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[43\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[44\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[45\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[46\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[47\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[48\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[49\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[50\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[51\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[52\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[53\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[54\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[55\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[56\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[57\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[58\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[59\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[60\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[61\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[62\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[63\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[64\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[65\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[66\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[67\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[68\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[69\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[70\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[71\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[72\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[73\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[74\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[75\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[76\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[77\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[78\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[79\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[80\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[81\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[82\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[83\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[84\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[85\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[86\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[87\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[88\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[89\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[90\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[91\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[92\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[93\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[94\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[95\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[96\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[97\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[98\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[99\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[100\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[101\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[102\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[103\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[104\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[105\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[106\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[107\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[108\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[109\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[110\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[111\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[112\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[113\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[114\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[115\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[116\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[117\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[118\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[119\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[120\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[121\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[122\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[123\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[124\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[125\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_t\[126\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[0\] (T0 20) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_u\[1\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_u\[2\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[3\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[4\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[5\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[6\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[7\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[8\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[9\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[10\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[11\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[12\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[13\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[14\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[15\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[16\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[17\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[18\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[19\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[20\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[21\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[22\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[23\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[24\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[25\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[26\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[27\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[28\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[29\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[30\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[31\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[32\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[33\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[34\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[35\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[36\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[37\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[38\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[39\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[40\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[41\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[42\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[43\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[44\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[45\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[46\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[47\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[48\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[49\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[50\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[51\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[52\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[53\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[54\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[55\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[56\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[57\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[58\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[59\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[60\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[61\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[62\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[63\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[64\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[65\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[66\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[67\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[68\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[69\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[70\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[71\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[72\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[73\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[74\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[75\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[76\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[77\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[78\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[79\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[80\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[81\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[82\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[83\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[84\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[85\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[86\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[87\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[88\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[89\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[90\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[91\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[92\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[93\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[94\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[95\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[96\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[97\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[98\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[99\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[100\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[101\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[102\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[103\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[104\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[105\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[106\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[107\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[108\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[109\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[110\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[111\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[112\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[113\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[114\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[115\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[116\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[117\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[118\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[119\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[120\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[121\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[122\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[123\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[124\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[125\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[126\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[127\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[128\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[129\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[130\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[131\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[132\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[133\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[134\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[135\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[136\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[137\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[138\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[139\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[140\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[141\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[142\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[143\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[144\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[145\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[146\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[147\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[148\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[149\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[150\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[151\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[152\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[153\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[154\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[155\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[156\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[157\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[158\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[159\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[160\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[161\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[162\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[163\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[164\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[165\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[166\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[167\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[168\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[169\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[170\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[171\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[172\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[173\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[174\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[175\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[176\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[177\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[178\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[179\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[180\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[181\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[182\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[183\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[184\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[185\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[186\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[187\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[188\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[189\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[190\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[191\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[192\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[193\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[194\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[195\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[196\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[197\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[198\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[199\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[200\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[201\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[202\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[203\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[204\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[205\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[206\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[207\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[208\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[209\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[210\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[211\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[212\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[213\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[214\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[215\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[216\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[217\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[218\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[219\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[220\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[221\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[222\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[223\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[224\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[225\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[226\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[227\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[228\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[229\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[230\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[231\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[232\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[233\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[234\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[235\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[236\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[237\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[238\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[239\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[240\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[241\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[242\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[243\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[244\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[245\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[246\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[247\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[248\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[249\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[250\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[251\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[252\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[253\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_u\[254\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[0\] (T0 20) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_v\[1\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2)) (v_v\[2\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[3\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[4\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[5\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[6\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[7\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[8\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[9\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[10\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[11\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[12\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[13\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[14\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[15\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[16\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[17\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[18\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[19\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[20\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[21\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[22\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[23\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[24\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[25\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[26\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[27\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[28\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[29\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[30\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[31\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[32\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[33\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[34\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[35\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[36\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[37\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[38\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[39\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[40\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[41\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[42\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[43\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[44\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[45\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[46\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[47\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[48\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[49\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[50\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[51\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[52\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[53\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[54\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[55\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[56\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[57\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[58\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[59\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[60\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[61\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[62\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[63\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[64\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[65\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[66\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[67\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[68\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[69\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[70\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[71\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[72\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[73\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[74\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[75\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[76\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[77\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[78\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[79\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[80\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[81\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[82\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[83\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[84\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[85\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[86\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[87\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[88\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[89\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[90\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[91\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[92\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[93\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[94\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[95\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[96\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[97\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[98\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[99\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[100\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[101\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[102\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[103\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[104\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[105\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[106\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[107\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[108\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[109\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[110\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[111\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[112\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[113\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[114\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[115\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[116\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[117\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[118\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[119\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[120\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[121\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[122\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[123\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[124\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[125\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[126\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[127\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[128\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[129\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[130\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[131\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[132\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[133\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[134\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[135\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[136\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[137\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[138\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[139\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[140\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[141\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[142\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[143\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[144\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[145\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[146\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[147\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[148\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[149\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[150\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[151\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[152\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[153\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[154\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[155\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[156\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[157\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[158\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[159\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[160\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[161\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[162\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[163\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[164\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[165\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[166\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[167\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[168\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[169\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[170\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[171\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[172\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[173\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[174\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[175\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[176\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[177\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[178\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[179\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[180\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[181\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[182\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[183\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[184\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[185\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[186\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[187\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[188\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[189\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[190\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[191\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[192\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[193\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[194\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[195\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[196\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[197\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[198\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[199\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[200\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[201\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[202\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[203\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[204\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[205\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[206\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[207\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[208\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[209\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[210\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[211\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[212\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[213\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[214\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[215\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[216\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[217\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[218\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[219\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[220\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[221\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[222\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[223\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[224\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[225\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[226\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[227\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[228\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[229\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[230\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[231\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[232\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[233\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[234\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[235\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[236\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[237\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[238\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[239\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[240\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[241\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[242\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[243\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[244\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[245\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[246\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[247\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[248\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[249\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[250\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[251\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[252\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[253\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[254\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[255\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[256\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[257\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[258\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[259\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[260\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[261\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[262\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[263\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[264\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[265\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[266\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[267\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[268\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[269\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[270\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[271\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[272\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[273\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[274\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[275\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[276\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[277\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[278\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[279\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[280\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[281\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[282\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[283\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[284\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[285\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[286\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[287\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[288\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[289\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[290\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[291\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[292\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[293\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[294\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[295\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[296\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[297\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[298\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[299\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[300\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[301\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[302\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[303\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[304\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[305\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[306\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[307\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[308\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[309\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[310\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[311\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[312\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[313\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[314\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[315\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[316\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[317\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[318\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[319\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[320\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[321\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[322\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[323\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[324\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[325\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[326\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[327\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[328\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[329\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[330\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[331\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[332\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[333\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[334\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[335\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[336\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[337\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[338\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[339\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[340\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[341\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[342\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[343\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[344\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[345\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[346\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[347\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[348\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[349\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[350\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[351\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[352\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[353\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[354\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[355\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[356\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[357\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[358\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[359\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[360\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[361\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[362\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[363\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[364\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[365\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[366\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[367\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[368\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[369\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[370\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[371\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[372\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[373\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[374\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[375\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[376\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[377\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[378\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[379\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[380\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[381\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[382\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[383\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[384\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[385\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[386\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[387\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[388\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[389\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[390\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[391\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[392\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[393\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[394\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[395\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[396\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[397\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[398\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[399\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[400\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[401\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[402\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[403\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[404\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[405\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[406\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[407\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[408\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[409\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[410\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[411\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[412\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[413\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[414\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[415\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[416\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[417\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[418\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[419\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[420\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[421\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[422\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[423\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[424\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[425\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[426\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[427\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[428\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[429\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[430\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[431\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[432\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[433\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[434\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[435\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[436\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[437\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[438\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[439\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[440\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[441\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[442\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[443\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[444\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[445\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[446\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[447\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[448\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[449\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[450\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[451\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[452\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[453\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[454\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[455\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[456\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[457\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[458\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[459\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[460\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[461\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[462\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[463\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[464\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[465\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[466\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[467\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[468\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[469\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[470\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[471\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[472\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[473\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[474\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[475\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[476\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[477\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[478\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[479\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[480\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[481\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[482\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[483\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[484\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[485\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[486\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[487\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[488\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[489\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[490\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[491\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[492\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[493\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[494\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[495\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[496\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[497\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[498\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[499\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[500\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[501\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[502\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[503\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[504\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[505\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[506\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[507\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[508\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[509\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (v_v\[510\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) ) ) ) ) verilator-5.042/test_regress/t/t_lint_ifdepth_bad.py0000755000542200017500000000111715101701376023245 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME --if-depth 10"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface_generic_modport_function_bad.out0000755000542200017500000000072215101701376030061 0ustar mahmoudyfreeshell%Error: t/t_interface_generic_modport_function_bad.v:24:11: Can't find definition of 'get' in dotted task/function: 'a.get' : ... note: In instance 't.genericModule' 24 | if (a.get() != 4) $stop; | ^~~ ... Known scopes under 'get': ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_inst_misarray2_bad.v0000644000542200017500000000100615101701376023351 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; wire signed [16:0] fft_oQ [6:0]; round round( .i_data(fft_oQ[6:0]) ); endmodule module round( input wire signed [16:0] i_data // Misdeclared, not a vector ); wire signed [15:0] w_convergent = {10'b0, {6{~i_data[7]}}}; endmodule verilator-5.042/test_regress/t/t_randc.py0000755000542200017500000000073415101701376021061 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_bug6421.v0000644000542200017500000000225215101701376020673 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 package uvm_pkg; class uvm_queue #(type T=int); endclass class m_uvm_waiter; endclass class uvm_config_db#(type T=int); static local uvm_queue#(m_uvm_waiter) m_waiters[string]; static function void set(int a, string b, string c, int d); endfunction endclass endpackage package sfr_agent_pkg; class sfr_monitor_abstract; endclass endpackage: sfr_agent_pkg module sfr_monitor_bfm #(ADDR_WIDTH = 8, DATA_WIDTH = 8) ( input [ADDR_WIDTH-1:0] address); import uvm_pkg::*; import sfr_agent_pkg::*; int SFR_MONITOR; initial begin uvm_config_db #(sfr_monitor_abstract)::set(null, "uvm_test_top", "SFR_MONITOR", SFR_MONITOR); end endmodule: sfr_monitor_bfm module hdl_top; parameter DATA_WIDTH = 32; parameter ADDR_WIDTH = 32; sfr_monitor_bfm #(.ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(DATA_WIDTH)) SFR_MONITOR( .address(42)); endmodule verilator-5.042/test_regress/t/t_gen_forif.py0000755000542200017500000000102515101701376021722 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(nc_flags2=['+access+r'], verilator_flags2=["--no-timing"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_mem_packed_noexpand.py0000755000542200017500000000103515101701376023746 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_mem_packed.v" test.compile(verilator_flags2=['-fno-expand']) test.execute() test.passes() verilator-5.042/test_regress/t/t_class_extern_args_bad.v0000644000542200017500000000255115101701376024117 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls; extern task func_bad(); //<--- Error (mismatch func) extern function int f1_bad(); //<--- Error (mismatch func type) extern function int f2_bad(); //<--- Error (mismatch func type) extern function void f3_bad(); //<--- Error (mismatch func type) extern function void f1bit_bad(int a); //<--- Error (mismatch arg type) extern function void f2args1_bad(bit a); //<--- Error (missing arg) extern function void f2args2(bit a); // ok extern function void f2args3_bad(bit a, bit b, bit c); //<--- Error (missing arg) extern function void farg_name_bad(bit declnamebad); //<--- Error (declname arg) endclass function bit Cls::func_bad(); return 1'b0; endfunction function bit Cls::f1_bad(); return 1'b0; endfunction function void Cls::f2_bad(); endfunction function bit Cls::f3_bad(); return 1'b0; endfunction function void Cls::f1bit_bad(bit a); endfunction function void Cls::f2args1_bad(bit a, bit b); endfunction function void Cls::f2args2(bit a, bit b); endfunction function void Cls::f2args3_bad(bit a, bit b); endfunction function void Cls::farg_name_bad(bit declname); endfunction module t; initial $stop; endmodule verilator-5.042/test_regress/t/t_forceable_net_cmt_trace.py0000755000542200017500000000146215101701376024602 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.pli_filename = "t/t_forceable_net.cpp" test.top_filename = "t/t_forceable_net.v" test.golden_filename = "t/t_forceable_net_trace.vcd.out" test.compile(make_top_shell=False, make_main=False, verilator_flags2=['-DCMT=1', '--exe', '--trace-vcd', test.pli_filename]) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_inst_paren_bad.v0000644000542200017500000000043415101701376022551 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module sub; endmodule module t; sub sub_inst; // No () endmodule verilator-5.042/test_regress/t/t_param_func2.py0000755000542200017500000000073415101701376022167 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_func_graphcirc.v0000644000542200017500000000220015101701376022547 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; integer cyc; initial cyc = 0; always @(posedge clk) begin cyc <= cyc + 1; if (cyc == 1) begin ReadContDisps; end else if (cyc == 5) begin $write("*-* All Finished *-*\n"); $finish; end `ifndef verilator DispContDisps; `endif end task ReadContDisps; begin $display("%m: Here: %d", cyc); end endtask integer dindex; task DispContDisps; /* verilator public */ begin if (cyc >= 2) begin if ( cyc >= 4 ) begin dindex = dindex + 2; //*** Error line $display("%m: DIndex increment %d", cyc); `ifdef VERILATOR $c("VL_PRINTF(\"Hello1?\\n\");"); `endif end `ifdef VERILATOR $c("VL_PRINTF(\"Hello2?\\n\");"); $c("VL_PRINTF(\"Hello3?\\n\");"); `endif end end endtask endmodule verilator-5.042/test_regress/t/t_recursive_method.py0000755000542200017500000000073415101701376023341 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_preproc_kwd_bad.v0000644000542200017500000000041715101701376022727 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `end_keywords `end_keywords // BAD module t; endmodule verilator-5.042/test_regress/t/t_assert_disabled.py0000755000542200017500000000104215101701376023113 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_assert_on.v" test.compile(verilator_flags2=['--no-assert']) test.execute() test.passes() verilator-5.042/test_regress/t/t_flag_decorations_node.py0000755000542200017500000000141415101701376024276 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_flag_decoration.v" test.compile(verilator_flags2=["--decorations node"]) test.file_grep_not(test.obj_dir + "/V" + test.name + ".h", "\n// CONSTRUCTORS") test.file_grep(test.obj_dir + "/V" + test.name + ".h", "\n // CONSTRUCTORS") test.file_grep(test.obj_dir + "/V" + test.name + ".h", r'/\*t/t_flag_decoration') test.passes() verilator-5.042/test_regress/t/t_x_assign_unique_0.py0000755000542200017500000000124615101701376023411 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_x_assign.cpp" test.top_filename = "t/t_x_assign.v" test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--x-assign unique --exe", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_langext_2.v0000644000542200017500000000253515101701376021470 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // A test of the +1364-1995ext+ and +systemverilogext+ flags. // // This source code contains constructs that are valid in SystemVerilog 2009 // but not in Verilog 1995. So it should fail if we set the language to be // Verilog 1995, but not SystemVerilog 2009. // // Compile only test, so no need for "All Finished" output. // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [1:0] res; // Instantiate the test test test_i (/*AUTOINST*/ // Outputs .res (res), // Inputs .clk (clk), .in (1'b1)); endmodule module test (// Outputs res, // Inputs clk, in ); output [1:0] res; input clk; input in; // This is a SystemVerilog 2009 only test generate genvar i; for (i=0; i<2; i=i+1) begin always @(posedge clk) begin unique0 case (i) 0: res[0:0] <= in; 1: res[1:1] <= in; endcase end end endgenerate endmodule verilator-5.042/test_regress/t/t_opt_const_no_expand.py0000755000542200017500000000131315101701376024027 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_opt_const.v" test.compile(verilator_flags2=[ "-Wno-UNOPTTHREADS", "-fno-dfg", "-fno-expand", "--stats", "t/t_opt_const.cpp" ]) test.execute() if test.vlt: test.file_grep(test.stats, r'Optimizations, Const bit op reduction\s+(\d+)', 1) test.passes() verilator-5.042/test_regress/t/t_interface_generic_task.py0000755000542200017500000000101315101701376024437 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(timing_loop=True, verilator_flags2=['--timing']) test.execute() test.passes() verilator-5.042/test_regress/t/t_math_svl2.py0000755000542200017500000000073415101701376021671 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_var_ref_bad1.out0000644000542200017500000000062615101701376022461 0ustar mahmoudyfreeshell%Error: t/t_var_ref_bad1.v:14:8: Ref connection 'bad_sub_ref' requires matching types; ref requires 'real' data type but connection is 'bit' data type. : ... note: In instance 't' 14 | (.bad_sub_ref(bad_parent)); | ^~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_sv_bus_mux_demux.py0000755000542200017500000000073415101701376023366 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_param_pattern.py0000755000542200017500000000077415101701376022633 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--dump-tree']) test.execute() test.passes() verilator-5.042/test_regress/t/t_std_waiver_no.py0000755000542200017500000000075115101701376022634 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=['-no-std-waiver']) test.passes() verilator-5.042/test_regress/t/t_math_pick.py0000755000542200017500000000073415101701376021731 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_case_x.py0000755000542200017500000000077515101701376021241 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--x-assign 0"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_assert_basic_off.py0000755000542200017500000000102015101701376023253 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_assert_basic.v" test.compile(v_flags2=[]) test.execute() test.passes() verilator-5.042/test_regress/t/t_slice_cond_2d_side_effect.py0000755000542200017500000000073415101701376025001 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_tri_pull_implicit.v0000644000542200017500000000066415101701376023332 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; // verilator lint_off IMPLICIT pulldown (pd); pullup (pu); initial begin if (pd != 0) $stop; if (pu != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_expr_incr_unsup.out0000644000542200017500000000156415101701376023373 0ustar mahmoudyfreeshell%Warning-SIDEEFFECT: t/t_expr_incr_unsup.v:17:34: Expression side effect may be mishandled : ... Suggest use a temporary variable in place of this expression 17 | $display("Value: %d", arr[postincrement_i()]++); | ^ ... For warning description see https://verilator.org/warn/SIDEEFFECT?v=latest ... Use "/* verilator lint_off SIDEEFFECT */" and lint_on around source to disable this message. %Warning-SIDEEFFECT: t/t_expr_incr_unsup.v:17:35: Expression side effect may be mishandled : ... Suggest use a temporary variable in place of this expression 17 | $display("Value: %d", arr[postincrement_i()]++); | ^~~~~~~~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_math_imm2.cpp0000644000542200017500000000335015101701376021773 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include VM_PREFIX_INCLUDE double sc_time_stamp() { return 0; } QData MaskVal(int lbit, int hbit) { QData val; for (val = 0; lbit <= hbit; lbit++) val |= (1ULL << lbit); return val; } int main(int argc, char* argv[]) { Verilated::debug(0); Verilated::commandArgs(argc, argv); VM_PREFIX* sim = new VM_PREFIX; int lbit, hbit; int errs = 0; for (lbit = 0; lbit < 32; lbit++) { for (hbit = lbit; hbit < 32; hbit++) { QData expected; sim->LowMaskSel_Bot = lbit; sim->LowMaskSel_Top = lbit; sim->HighMaskSel_Bot = hbit; sim->HighMaskSel_Top = hbit; sim->eval(); expected = ((MaskVal(sim->LowMaskSel_Top, sim->HighMaskSel_Top) << 32ULL) | MaskVal(sim->LowMaskSel_Bot, sim->HighMaskSel_Bot)); if (sim->LogicImm != expected) { printf("%%Error: %d.%d,%d.%d -> %016" PRIx64 "/%016" PRIx64 " -> %016" PRIx64 " (expected %016" PRIx64 ")\n", sim->LowMaskSel_Top, sim->HighMaskSel_Top, sim->LowMaskSel_Bot, sim->HighMaskSel_Bot, sim->LowLogicImm, sim->HighLogicImm, sim->LogicImm, expected); errs = 1; } } } sim->final(); VL_DO_DANGLING(delete sim, sim); if (errs) { vl_stop(__FILE__, __LINE__, "TOP-cpp"); exit(10); } else { printf("*-* All Finished *-*\n"); return 0; } } verilator-5.042/test_regress/t/t_cover_line_cc.info.out0000644000542200017500000000464315101701376023675 0ustar mahmoudyfreeshellTN:verilator_coverage SF:t/t_cover_line.v DA:15,1 DA:18,1 DA:55,10 DA:56,10 BRDA:56,0,0,10 BRDA:56,0,1,0 DA:57,10 DA:58,10 DA:60,9 BRDA:60,0,0,1 BRDA:60,0,1,9 DA:61,9 BRDA:61,0,0,1 BRDA:61,0,1,9 DA:62,1 DA:63,1 DA:66,9 BRDA:66,0,0,1 BRDA:66,0,1,9 DA:67,9 BRDA:67,0,0,1 BRDA:67,0,1,9 DA:69,9 DA:70,9 DA:73,9 BRDA:73,0,0,1 BRDA:73,0,1,9 DA:74,9 BRDA:74,0,0,1 BRDA:74,0,1,9 DA:75,1 DA:76,1 DA:79,9 DA:80,9 DA:83,1 DA:84,1 DA:85,1 DA:87,1 DA:88,1 DA:89,1 DA:91,7 BRDA:91,0,0,1 BRDA:91,0,1,7 DA:92,1 DA:93,1 DA:96,7 DA:97,7 DA:100,0 DA:101,0 DA:102,0 DA:104,0 DA:105,10 BRDA:105,0,0,0 BRDA:105,0,1,10 DA:106,10 DA:107,10 BRDA:107,0,0,0 BRDA:107,0,1,10 DA:110,1 DA:111,1 DA:113,1 DA:115,1 DA:120,7 BRDA:120,0,0,1 BRDA:120,0,1,7 DA:121,1 DA:122,1 DA:127,1 DA:129,1 DA:140,20 DA:141,18 BRDA:141,0,0,2 BRDA:141,0,1,18 DA:142,2 DA:145,18 DA:164,20 DA:165,20 DA:166,20 BRDA:166,0,0,0 BRDA:166,0,1,20 DA:168,0 DA:170,18 BRDA:170,0,0,2 BRDA:170,0,1,18 DA:172,2 DA:174,18 DA:188,11 DA:189,11 DA:190,11 BRDA:190,0,0,11 BRDA:190,0,1,0 DA:191,11 DA:194,11 DA:195,11 BRDA:195,0,0,11 BRDA:195,0,1,0 DA:196,11 DA:199,11 DA:200,11 BRDA:200,0,0,11 BRDA:200,0,1,0 DA:201,11 DA:215,10 DA:216,10 DA:219,11 DA:221,11 DA:222,10 BRDA:222,0,0,1 BRDA:222,0,1,10 DA:223,1 DA:225,10 BRDA:225,0,0,1 BRDA:225,0,1,10 DA:226,1 DA:229,11 DA:231,11 DA:232,11 DA:233,11 DA:253,10 DA:254,9 BRDA:254,0,0,1 BRDA:254,0,1,9 DA:256,1 DA:257,1 BRDA:257,0,0,0 BRDA:257,0,1,1 DA:266,10 DA:267,10 DA:268,1 DA:269,1 DA:270,1 DA:271,1 DA:272,1 DA:273,5 DA:277,10 DA:278,10 DA:288,0 DA:289,0 BRDA:289,0,0,0 BRDA:289,0,1,0 DA:290,0 DA:292,0 DA:293,0 DA:295,0 DA:301,1 DA:304,1 DA:305,20 DA:306,20 DA:315,1 DA:318,21 DA:319,21 DA:320,21 DA:323,10 DA:325,10 DA:328,31 BRDA:328,0,0,0 BRDA:328,0,1,31 DA:329,28 BRDA:329,0,0,3 BRDA:329,0,1,28 DA:330,21 BRDA:330,0,0,21 BRDA:330,0,1,0 DA:331,10 DA:332,10 BRDA:332,0,0,10 BRDA:332,0,1,3 BRDA:332,0,2,7 DA:333,10 BRDA:333,0,0,10 BRDA:333,0,1,0 BRDA:333,0,2,10 DA:335,19 BRDA:335,0,0,12 BRDA:335,0,1,19 BRDA:335,0,2,7 BRDA:335,0,3,5 DA:338,11 BRDA:338,0,0,11 BRDA:338,0,1,0 DA:344,11 BRDA:344,0,0,10 BRDA:344,0,1,11 DA:347,11 DA:348,10 BRDA:348,0,0,0 BRDA:348,0,1,1 BRDA:348,0,2,1 BRDA:348,0,3,10 DA:349,10 DA:351,11 BRDA:351,0,0,11 BRDA:351,0,1,1 BRDA:351,0,2,10 DA:354,55 BRDA:354,0,0,11 BRDA:354,0,1,55 DA:355,55 DA:357,44 BRDA:357,0,0,11 BRDA:357,0,1,11 BRDA:357,0,2,33 BRDA:357,0,3,44 DA:358,44 DA:361,11 BRDA:361,0,0,0 BRDA:361,0,1,11 DA:362,11 BRF:79 BRH:32 end_of_record verilator-5.042/test_regress/t/t_math_countbits_bad.py0000755000542200017500000000076615101701376023630 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_gen_missing.py0000755000542200017500000000077615101701376022302 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=['+define+T_GEN_MISSING']) test.execute() test.passes() verilator-5.042/test_regress/t/t_timescale_nobackwards.v0000644000542200017500000000122115101701376024120 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 `define checkf function void f(); $printtimescale; $display("%0t", $time); endfunction package pkg; `checkf; endpackage checker CHK(); `checkf; endchecker program PRG; `checkf; endprogram class CLS; static `checkf; endclass module mod; CHK chk(); PRG prg(); initial begin $printtimescale; $display("%0t", $time); pkg::f(); chk.f(); prg.f(); CLS::f(); $finish; end endmodule `timescale 1ns / 10ps verilator-5.042/test_regress/t/t_vpi_multidim.cpp0000644000542200017500000003773615101701376022637 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #ifdef IS_VPI #include "vpi_user.h" #include #else #include "verilated.h" #include "verilated_vcd_c.h" #include "verilated_vpi.h" #include "Vt_vpi_multidim.h" #include "Vt_vpi_multidim__Dpi.h" #include "svdpi.h" #endif #include #include #include #include #include #include #include extern "C" { #include } // These require the above. Comment prevents clang-format moving them #include "TestCheck.h" #include "TestSimulator.h" #include "TestVpi.h" int errors = 0; // TEST START void _arr_type_check(TestVpiHandle& arr_h, int expType, int expSize, int expRangeHigh, int expRangeLow) { const int vpitype = vpi_get(vpiType, arr_h); TEST_CHECK_EQ(vpitype, expType); const int vpisize = vpi_get(vpiSize, arr_h); TEST_CHECK_EQ(vpisize, expSize); s_vpi_value value; value.format = vpiIntVal; TestVpiHandle left_h = vpi_handle(vpiLeftRange, arr_h); TEST_CHECK_NZ(left_h); vpi_get_value(left_h, &value); TEST_CHECK_EQ(value.value.integer, expRangeHigh); TestVpiHandle right_h = vpi_handle(vpiRightRange, arr_h); TEST_CHECK_NZ(right_h); vpi_get_value(right_h, &value); TEST_CHECK_EQ(value.value.integer, expRangeLow); } void _arr_iter_check(const char* name, int wordSize, const int* lows) { TestVpiHandle arr_h = vpi_handle_by_name(const_cast(TestSimulator::rooted(name)), NULL); TEST_CHECK_NZ(arr_h); _arr_type_check(arr_h, vpiRegArray, 4, lows[0] + 1, lows[0]); { // can't iterate through RegArrays on a nested RegArray TestVpiHandle arr_iter_h = vpi_iterate(vpiRegArray, arr_h); TEST_CHECK_Z(vpi_scan(arr_iter_h)); arr_iter_h.freed(); } if (!TestSimulator::is_questa()) { // but we can access them by index (Questa can't) for (int idx = lows[0]; idx < lows[0] + 2; idx++) { TestVpiHandle arr_elem_h = vpi_handle_by_index(arr_h, idx); TEST_CHECK_NZ(arr_elem_h); // first indexing yields size-2 RegArrays _arr_type_check(arr_elem_h, vpiRegArray, 2, lows[1] + 1, lows[1]); for (int idx2 = lows[1]; idx2 < lows[1] + 2; idx2++) { TestVpiHandle arr_elem2_h = vpi_handle_by_index(arr_elem_h, idx2); TEST_CHECK_NZ(arr_elem2_h); // second indexing yields wordSize Regs _arr_type_check(arr_elem2_h, vpiReg, wordSize, lows[2] + 1, lows[2]); } } } { // it's also possible to directly iterate through all four Regs TestVpiHandle arr_iter_h = vpi_iterate(vpiReg, arr_h); for (int idx = 0; idx < 4; idx++) { TestVpiHandle arr_elem_h = vpi_scan(arr_iter_h); TEST_CHECK_NZ(arr_elem_h); // which gives us wordSize Regs _arr_type_check(arr_elem_h, vpiReg, wordSize, lows[2] + 1, lows[2]); { // can't iterate through Regs on a nested Reg TestVpiHandle arr_iter2_h = vpi_iterate(vpiReg, arr_elem_h); TEST_CHECK_Z(vpi_scan(arr_iter2_h)); arr_iter2_h.freed(); } // but we can access them by index for (int idx2 = lows[2]; idx2 < lows[2] + 2; idx2++) { TestVpiHandle arr_elem2_h = vpi_handle_by_index(arr_elem_h, idx2); TEST_CHECK_NZ(arr_elem2_h); // first indexing yields wordSize / 2 Regs _arr_type_check(arr_elem2_h, vpiReg, wordSize / 2, lows[3] + wordSize / 2 - 1, lows[3]); for (int idx3 = lows[3]; idx3 < lows[3] + wordSize / 2; idx3++) { TestVpiHandle arr_elem3_h = vpi_handle_by_index(arr_elem2_h, idx3); TEST_CHECK_NZ(arr_elem3_h); { // second indexing yields size-1 RegBits (no support for RegBit VPI type // yet) const int vpitype = vpi_get(vpiType, arr_elem3_h); if (TestSimulator::is_verilator()) { TEST_CHECK_EQ(vpitype, vpiReg); } else { TEST_CHECK_EQ(vpitype, vpiRegBit); } const int vpisize = vpi_get(vpiSize, arr_elem3_h); TEST_CHECK_EQ(vpisize, 1); } } } // iterating through packed ranges TestVpiHandle range_iter_h = vpi_iterate(vpiRange, arr_elem_h); for (int idx2 = 0; idx2 < 2; idx2++) { TestVpiHandle range_h = vpi_scan(range_iter_h); TEST_CHECK_NZ(range_h); { s_vpi_value value; value.format = vpiIntVal; TestVpiHandle side_h = vpi_handle(vpiLeftRange, range_h); TEST_CHECK_NZ(side_h); vpi_get_value(side_h, &value); if (idx2 == 0) { TEST_CHECK_EQ(value.value.integer, lows[2] + 1); } else { TEST_CHECK_EQ(value.value.integer, lows[3] + wordSize / 2 - 1); } side_h = vpi_handle(vpiRightRange, range_h); TEST_CHECK_NZ(side_h); vpi_get_value(side_h, &value); if (idx2 == 0) { TEST_CHECK_EQ(value.value.integer, lows[2]); } else { TEST_CHECK_EQ(value.value.integer, lows[3]); } } } TEST_CHECK_Z(vpi_scan(range_iter_h)); range_iter_h.freed(); } TEST_CHECK_Z(vpi_scan(arr_iter_h)); arr_iter_h.freed(); } { // iterating through unpacked ranges TestVpiHandle range_iter_h = vpi_iterate(vpiRange, arr_h); for (int idx = 0; idx < 2; idx++) { TestVpiHandle range_h = vpi_scan(range_iter_h); TEST_CHECK_NZ(range_h); { s_vpi_value value; value.format = vpiIntVal; TestVpiHandle side_h = vpi_handle(vpiLeftRange, range_h); TEST_CHECK_NZ(side_h); vpi_get_value(side_h, &value); if (idx == 0) { TEST_CHECK_EQ(value.value.integer, lows[0] + 1); } else { TEST_CHECK_EQ(value.value.integer, lows[1] + 1); } side_h = vpi_handle(vpiRightRange, range_h); TEST_CHECK_NZ(side_h); vpi_get_value(side_h, &value); if (idx == 0) { TEST_CHECK_EQ(value.value.integer, lows[0]); } else { TEST_CHECK_EQ(value.value.integer, lows[1]); } } } TEST_CHECK_Z(vpi_scan(range_iter_h)); range_iter_h.freed(); } } void _arr_access_format_check(TestVpiHandle& reg_h, int wordSize, const int* lows, const char* octVal_s, PLI_INT32 format) { constexpr int MAX_SPANSIZE = 1024; const int spanSize = wordSize / 2; assert(spanSize <= MAX_SPANSIZE); s_vpi_value value_in; s_vpi_value value_out; s_vpi_error_info e; char zero_s[2] = "0"; // zero out the vector value_in.format = vpiOctStrVal; value_in.value.str = zero_s; vpi_put_value(reg_h, &value_in, NULL, vpiNoDelay); TEST_CHECK_Z(vpi_chk_error(&e)); value_in.format = format; value_out.format = format; for (int i = 0; i < 2; i++) { TestVpiHandle subreg_h = vpi_handle_by_index(reg_h, lows[2] + i); TEST_CHECK_NZ(subreg_h); char octSpan_s[MAX_SPANSIZE / 3 + 1]; strncpy(octSpan_s, &octVal_s[spanSize / 3 * (1 - i)], spanSize / 3); octSpan_s[spanSize / 3] = '\0'; uint64_t intVal; t_vpi_vecval vecVal[2]; sscanf(octSpan_s, "%" SCNo64, &intVal); char strVal_s[MAX_SPANSIZE + 1]; // max length of the string happens for binary if (format == vpiIntVal) { value_in.value.integer = intVal; } else if (format == vpiVectorVal) { if (spanSize > 32) { vecVal[1].aval = intVal >> 32; vecVal[1].bval = 0; } vecVal[0].aval = intVal; vecVal[0].bval = 0; value_in.value.vector = vecVal; } else if (format == vpiBinStrVal) { for (int j = 0; j < spanSize; j++) strVal_s[j] = (intVal >> (spanSize - j - 1)) % 2 + '0'; strVal_s[spanSize] = '\0'; value_in.value.str = strVal_s; } else if (format == vpiDecStrVal) { sprintf(strVal_s, "%" PRIu64, intVal); value_in.value.str = strVal_s; } else if (format == vpiHexStrVal) { sprintf(strVal_s, "%0*" PRIx64, (spanSize + 3) / 4, intVal); value_in.value.str = strVal_s; } else if (format == vpiOctStrVal) { sprintf(strVal_s, "%0*" PRIo64, (spanSize + 2) / 3, intVal); value_in.value.str = strVal_s; } else if (format == vpiStringVal) { const int byteCount = (spanSize + 7) / 8; for (int j = 0; j < byteCount; j++) strVal_s[j] = (intVal >> (8 * (byteCount - j - 1))) & 0xff; strVal_s[byteCount] = '\0'; value_in.value.str = strVal_s; } vpi_put_value(subreg_h, &value_in, NULL, vpiNoDelay); TEST_CHECK_Z(vpi_chk_error(&e)); vpi_get_value(subreg_h, &value_out); switch (format) { case vpiIntVal: TEST_CHECK_EQ(value_out.value.integer, value_in.value.integer); break; case vpiVectorVal: if (spanSize > 32) TEST_CHECK_EQ(value_out.value.vector[1].aval, value_in.value.vector[1].aval); TEST_CHECK_EQ(value_out.value.vector[0].aval, value_in.value.vector[0].aval); break; case vpiStringVal: TEST_CHECK_EQ(value_out.value.str[0], value_in.value.str[0] ? value_in.value.str[0] : ' '); break; case vpiBinStrVal: case vpiDecStrVal: case vpiHexStrVal: case vpiOctStrVal: TEST_CHECK_CSTR(value_out.value.str, value_in.value.str); break; } } // validate the resulting flattened vector value_out.format = vpiOctStrVal; vpi_get_value(reg_h, &value_out); TEST_CHECK_CSTR(value_out.value.str, octVal_s); } std::default_random_engine rng; void _arr_access_check(const char* name, int wordSize, const int* lows) { TestVpiHandle arr_h = vpi_handle_by_name(const_cast(TestSimulator::rooted(name)), NULL); TEST_CHECK_NZ(arr_h); std::uniform_int_distribution rand64(std::numeric_limits::min(), std::numeric_limits::max()); constexpr int MAX_WORDSIZE = 128; assert(wordSize <= MAX_WORDSIZE); char octVal_s[MAX_WORDSIZE / 3 + 2]; octVal_s[0] = '0' + (rand64(rng) % (1ULL << ((((wordSize - 1) % 3) + 1)))); for (int i = 1; i < (wordSize + 2) / 3; ++i) octVal_s[i] = '0' + (rand64(rng) % 8); octVal_s[(wordSize + 2) / 3] = '\0'; // Assume that reading/writing to the "flattened" packed register is already tested, // check only reading/writing to sub-regs and validate the flattened result. { TestVpiHandle arr_iter_h = vpi_iterate(vpiReg, arr_h); while (TestVpiHandle reg_h = vpi_scan(arr_iter_h)) { s_vpi_value value_in; s_vpi_value value_out; s_vpi_error_info e; value_out.format = vpiOctStrVal; value_in.format = vpiOctStrVal; value_in.value.str = octVal_s; vpi_put_value(reg_h, &value_in, NULL, vpiNoDelay); TEST_CHECK_Z(vpi_chk_error(&e)); vpi_get_value(reg_h, &value_out); TEST_CHECK_CSTR(value_out.value.str, octVal_s); // test each I/O data format if (wordSize <= 64) { _arr_access_format_check(reg_h, wordSize, lows, octVal_s, vpiIntVal); _arr_access_format_check(reg_h, wordSize, lows, octVal_s, vpiDecStrVal); } _arr_access_format_check(reg_h, wordSize, lows, octVal_s, vpiVectorVal); _arr_access_format_check(reg_h, wordSize, lows, octVal_s, vpiBinStrVal); _arr_access_format_check(reg_h, wordSize, lows, octVal_s, vpiOctStrVal); _arr_access_format_check(reg_h, wordSize, lows, octVal_s, vpiHexStrVal); _arr_access_format_check(reg_h, wordSize, lows, octVal_s, vpiStringVal); } arr_iter_h.freed(); } } struct params { const char* name; int wordSize; const int lows[4]; }; void _multidim_check() { static struct params values[] = {{"arr_cdata", 6, {0, 1, 2, 3}}, {"arr_sdata", 12, {4, 5, 6, 7}}, {"arr_idata", 30, {8, 9, 10, 11}}, {"arr_qdata", 60, {12, 13, 14, 15}}, {"arr_wdata", 126, {16, 17, 18, 19}}, {nullptr, 0, {0, 0, 0, 0}}}; struct params* value = values; while (value->name) { _arr_iter_check(value->name, value->wordSize, value->lows); _arr_access_check(value->name, value->wordSize, value->lows); value++; } } // TEST END extern "C" int mon_check() { // Callback from initial block in monitor //if (int status = _mon_check_param()) return status; printf("-mon_check()\n"); _multidim_check(); return errors; } #ifdef IS_VPI static int mon_check_vpi() { TestVpiHandle href = vpi_handle(vpiSysTfCall, 0); s_vpi_value vpi_value; vpi_value.format = vpiIntVal; vpi_value.value.integer = mon_check(); vpi_put_value(href, &vpi_value, NULL, vpiNoDelay); return 0; } static s_vpi_systf_data vpi_systf_data[] = {{vpiSysFunc, vpiIntFunc, (PLI_BYTE8*)"$mon_check", (PLI_INT32(*)(PLI_BYTE8*))mon_check_vpi, 0, 0, 0}, 0}; void vpi_compat_bootstrap(void) { p_vpi_systf_data systf_data_p; systf_data_p = &(vpi_systf_data[0]); while (systf_data_p->type != 0) vpi_register_systf(systf_data_p++); } void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0}; #else int main(int argc, char** argv) { const std::unique_ptr contextp{new VerilatedContext}; uint64_t sim_time = 1100; // TODO contextp->debug(0); contextp->commandArgs(argc, argv); const std::unique_ptr topp{new VM_PREFIX{contextp.get(), // Note null name - we're flattening it out ""}}; #ifdef VERILATOR #ifdef TEST_VERBOSE contextp->scopesDump(); #endif #endif #if VM_TRACE contextp->traceEverOn(true); VL_PRINTF("Enabling waves...\n"); VerilatedVcdC* tfp = new VerilatedVcdC; topp->trace(tfp, 99); tfp->open(STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); #endif topp->eval(); topp->clk = 0; contextp->timeInc(10); while (contextp->time() < sim_time && !contextp->gotFinish()) { contextp->timeInc(1); topp->eval(); VerilatedVpi::callValueCbs(); topp->clk = !topp->clk; // mon_do(); #if VM_TRACE if (tfp) tfp->dump(main_time); #endif } if (!contextp->gotFinish()) { vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); } topp->final(); #if VM_TRACE if (tfp) tfp->close(); #endif return 0; } #endif verilator-5.042/test_regress/t/t_while_timing_control.v0000644000542200017500000000075315101701376024024 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t(); logic clk = 0; logic out = 1; always #5 clk = ~clk; initial begin while(1) begin if(out) begin break; end @(negedge clk); end $write("*-* All Finished *-*\n"); $finish(); end endmodule verilator-5.042/test_regress/t/t_func_sum.v0000644000542200017500000000423615101701376021424 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008-2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; wire [9:0] I1 = crc[9:0]; wire [9:0] I2 = crc[19:10]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [9:0] S; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .S (S[9:0]), // Inputs .I1 (I1[9:0]), .I2 (I2[9:0])); wire [63:0] result = {32'h0, 22'h0, S}; `define EXPECTED_SUM 64'h24c38b77b0fcc2e7 // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs S, // Inputs I1, I2 ); input [9:0] I1/*verilator public*/; input [9:0] I2/*verilator public*/; output reg [9:0] S/*verilator public*/; always @(I1 or I2) t2(I1,I2,S); task t1; input In1,In2; output Sum; Sum = In1 ^ In2; endtask task t2; input[9:0] In1,In2; output [9:0] Sum; integer I; begin for (I=0;I<10;I=I+1) t1(In1[I],In2[I],Sum[I]); end endtask endmodule verilator-5.042/test_regress/t/t_foreach_nindex_bad.out0000644000542200017500000000060115101701376023721 0ustar mahmoudyfreeshell%Error: t/t_foreach_nindex_bad.v:12:34: foreach loop variables exceed number of indices of array : ... note: In instance 't' 12 | foreach (array[i, j, badk, badl]); | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_wrapper_legacy.v0000644000542200017500000000074615101701376022613 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 Wilson Snyder and Marlon James. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; int count; always @(posedge clk) begin count <= count + 1; if (count == 10) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule : t verilator-5.042/test_regress/t/t_mem.v0000644000542200017500000000331715101701376020362 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; // [16] is SV syntax for [0:15] reg [7:0] memory8_16 [16]; reg m_we; reg [3:1] m_addr; reg [15:0] m_data; always @ (posedge clk) begin // Load instructions from cache memory8_16[{m_addr,1'd0}] <= 8'hfe; if (m_we) begin {memory8_16[{m_addr,1'd1}], memory8_16[{m_addr,1'd0}]} <= m_data; end end reg [7:0] memory8_16_4; reg [7:0] memory8_16_5; // Test complicated sensitivity lists always @ (memory8_16[4][7:1] or memory8_16[5]) begin memory8_16_4 = memory8_16[4]; memory8_16_5 = memory8_16[5]; end always @ (posedge clk) begin m_we <= 0; if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin m_we <= 1'b1; m_addr <= 3'd2; m_data <= 16'h55_44; end if (cyc==2) begin m_we <= 1'b1; m_addr <= 3'd3; m_data <= 16'h77_66; end if (cyc==3) begin m_we <= 0; // Check we really don't write this m_addr <= 3'd3; m_data <= 16'h0bad; end if (cyc==5) begin if (memory8_16_4 != 8'h44) $stop; if (memory8_16_5 != 8'h55) $stop; if (memory8_16[6] != 8'hfe) $stop; if (memory8_16[7] != 8'h77) $stop; $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.042/test_regress/t/t_sys_readmem_bad_end2.mem0000644000542200017500000000060015101701376024133 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test data file // // Copyright 2006 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 10 11 @2 01 // Missing additional data verilator-5.042/test_regress/t/t_gantt_io_noproc.dat0000644000542200017500000000356415101701376023277 0ustar mahmoudyfreeshellVLPROFVERSION 2.0 VLPROF arg +verilator+prof+exec+start+2 VLPROF arg +verilator+prof+exec+window+2 VLPROF stat threads 2 VLPROF stat yields 0 VLPROFTHREAD 0 VLPROFEXEC EXEC_GRAPH_BEGIN 945 VLPROFEXEC MTASK_BEGIN 2695 id 6 predictStart 0 cpu 19 VLPROFEXEC MTASK_END 2905 predictCost 30 VLPROFEXEC MTASK_BEGIN 9695 id 10 predictStart 196 cpu 19 VLPROFEXEC MTASK_END 9870 predictCost 30 VLPROFEXEC EXEC_GRAPH_END 12180 VLPROFEXEC EXEC_GRAPH_BEGIN 14000 VLPROFEXEC MTASK_BEGIN 15610 id 6 predictStart 0 cpu 19 VLPROFEXEC MTASK_END 15820 predictCost 30 VLPROFEXEC THREAD_SCHEDULE_WAIT_BEGIN 16000 cpu 19 VLPROFEXEC THREAD_SCHEDULE_WAIT_END 17000 cpu 19 VLPROFEXEC MTASK_BEGIN 21700 id 10 predictStart 196 cpu 19 VLPROFEXEC MTASK_END 21875 predictCost 30 VLPROFEXEC EXEC_GRAPH_END 22085 VLPROFTHREAD 1 VLPROFEXEC MTASK_BEGIN 5495 id 5 predictStart 0 cpu 10 VLPROFEXEC MTASK_END 6090 predictCost 30 VLPROFEXEC MTASK_BEGIN 6300 id 7 predictStart 30 cpu 10 VLPROFEXEC MTASK_END 6895 predictCost 30 VLPROFEXEC MTASK_BEGIN 7490 id 8 predictStart 60 cpu 10 VLPROFEXEC MTASK_END 8540 predictCost 107 VLPROFEXEC MTASK_BEGIN 9135 id 9 predictStart 167 cpu 10 VLPROFEXEC MTASK_END 9730 predictCost 30 VLPROFEXEC MTASK_BEGIN 10255 id 11 predictStart 197 cpu 10 VLPROFEXEC MTASK_END 11060 predictCost 30 VLPROFEXEC THREAD_SCHEDULE_WAIT_BEGIN 17000 cpu 10 VLPROFEXEC THREAD_SCHEDULE_WAIT_END 18000 cpu 10 VLPROFEXEC MTASK_BEGIN 18375 id 5 predictStart 0 cpu 10 VLPROFEXEC MTASK_END 18970 predictCost 30 VLPROFEXEC MTASK_BEGIN 19145 id 7 predictStart 30 cpu 10 VLPROFEXEC MTASK_END 19320 predictCost 30 VLPROFEXEC MTASK_BEGIN 19670 id 8 predictStart 60 cpu 10 VLPROFEXEC MTASK_END 19810 predictCost 107 VLPROFEXEC MTASK_BEGIN 20650 id 9 predictStart 167 cpu 10 VLPROFEXEC MTASK_END 20720 predictCost 30 VLPROFEXEC MTASK_BEGIN 21140 id 11 predictStart 197 cpu 10 VLPROFEXEC MTASK_END 21245 predictCost 30 VLPROF stat ticks 23415 verilator-5.042/test_regress/t/t_assert_unique_case_bad.out0000644000542200017500000000045415101701376024635 0ustar mahmoudyfreeshellmatch_item0 match_item0 match_item0 match_item0 match_item0 match_item0 match_item0 match_item0 match_item0 [90] %Error: t_assert_unique_case_bad.v:38: Assertion failed in top.t: unique case, but multiple matches found for '12'h388' %Error: t/t_assert_unique_case_bad.v:38: Verilog $stop Aborting... verilator-5.042/test_regress/t/t_lint_bsspace_bad.v0000644000542200017500000000055415101701376023060 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Fake binary character here '', so is treated as binary and // don't get whitespace violation. `define FOO blak \ blak module t; endmodule verilator-5.042/test_regress/t/t_interface_generic_task2.py0000755000542200017500000000077115101701376024533 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--timing']) test.execute() test.passes() verilator-5.042/test_regress/t/t_tri_dangle.v0000644000542200017500000000141115101701376021705 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inouts AVDD, AVSS ); inout AVDD; inout AVSS; sub sub (/*AUTOINST*/ // Inouts .AVDD (AVDD), .AVSS (AVSS)); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule module sub (/*AUTOARG*/ // Inouts AVDD, AVSS ); // verilator no_inline_module inout AVDD; inout AVSS; tri NON_IO; // +verilator+rand+reset+0 so z will read as zero initial if (NON_IO !== 'z) $stop; endmodule verilator-5.042/test_regress/t/t_cover_toggle.py0000755000542200017500000000350715101701376022452 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--cc --coverage-toggle --stats']) test.execute() # Read the input .v file and do any CHECK_COVER requests test.inline_checks() test.file_grep_not(test.obj_dir + "/coverage.dat", "largeish") if test.vlt_all: test.file_grep(test.stats, r'Coverage, Toggle points joined\s+(\d+)', 14) test.run(cmd=[ os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--annotate", test.obj_dir + "/annotated", test.obj_dir + "/coverage.dat", ], verilator_run=True) test.files_identical(test.obj_dir + "/annotated/" + test.name + ".v", test.golden_filename) test.file_grep_not(test.obj_dir + "/coverage.dat", "_under_toggle") test.run(cmd=[ os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--annotate-points", "--annotate", test.obj_dir + "/annotated-points", test.obj_dir + "/coverage.dat", ], verilator_run=True) test.files_identical(test.obj_dir + "/annotated-points/" + test.name + ".v", "t/" + test.name + "__points.out") test.run(cmd=[ os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--annotate-all", "--annotate-min 1", "--annotate", test.obj_dir + "/annotated-all", test.obj_dir + "/coverage.dat", ], verilator_run=True) test.files_identical(test.obj_dir + "/annotated-all/" + test.name + ".v", "t/" + test.name + "__all.out") test.passes() verilator-5.042/test_regress/t/t_fork_dynscope_unsup.out0000644000542200017500000000120415101701376024236 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_fork_dynscope_unsup.v:17:7: Unsupported: Writing to a captured inout variable in a fork after a timing control : ... note: In instance 't' 17 | p = #1 1; | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_fork_dynscope_unsup.v:22:5: Unsupported: Writing to a captured output variable in a non-blocking assignment after a timing control : ... note: In instance 't' 22 | q <= #1 1; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_scheduling_3.py0000755000542200017500000000073415101701376022341 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_gate_inline_wide_noexclude_sel.py0000755000542200017500000000140215101701376026162 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=['--stats', '--expand-limit 5', '-fno-var-split']) test.file_grep(test.stats, r'Optimizations, Gate excluded wide expressions\s+(\d+)', 1) test.file_grep(test.stats, r'Optimizations, Gate sigs deleted\s+(\d+)', 1) test.file_grep(test.stats, r'SplitVar, packed variables split automatically\s+(\d+)', 0) test.passes() verilator-5.042/test_regress/t/t_dynarray_unpacked.v0000644000542200017500000000154115101701376023304 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module t; byte dyn [][1:0]; initial begin begin dyn = new [3]; dyn[0] = '{101, 100}; dyn[1] = '{111, 110}; dyn[2] = '{121, 120}; `checkh(dyn[0][0], 100); `checkh(dyn[0][1], 101); `checkh(dyn[1][0], 110); `checkh(dyn[1][1], 111); `checkh(dyn[2][0], 120); `checkh(dyn[2][1], 121); end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_interface_wire_bad_param.out0000644000542200017500000000057415101701376025124 0ustar mahmoudyfreeshell%Error: t/t_interface_wire_bad_param.v:17:20: Operator ASSIGNW expected non-interface on Assign RHS but 'a' is an interface. : ... note: In instance 't' 17 | wire wbad = sub.a; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_interface_generic_task2.v0000644000542200017500000000113015101701376024333 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 interface inf; int v; task setup(); v = 3; endtask endinterface interface inf2; int k; endinterface module GenericModule (interface a); initial begin #1; if (a.v != 3) $stop; end endmodule module t; inf inf_inst(); GenericModule genericModule (inf_inst); initial begin inf_inst.setup(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_assoc_ref_type.py0000755000542200017500000000073415101701376022777 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_sys_plusargs_bad.py0000755000542200017500000000073415101701376023336 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_enum_huge_methods_bad.py0000755000542200017500000000076315101701376024301 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_param_long.py0000755000542200017500000000073415101701376022111 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_extends_default.v0000644000542200017500000000113715101701376024145 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Base1; int s = 2; function new(int def = 3); s = def; endfunction endclass class Cls1 extends Base1(default); // Gets new(int def) endclass module t; initial begin Cls1 c1; Cls1 c5; c1 = new(57); if (c1.s !== 57) $stop; c5 = new; if (c5.s !== 5) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_constraint_before_randc_bad.v0000644000542200017500000000056115101701376025265 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls1; rand bit b1; randc int b2; constraint raint2_bad { solve b1 before b2; } // BAD no randc vars here endclass module t; endmodule verilator-5.042/test_regress/t/t_unroll_delay.out0000644000542200017500000000026515101701376022636 0ustar mahmoudyfreeshell [0] A 1 6 [0] B 1 6 [1] C 1 6 [1] A 1 7 [1] B 1 7 [2] C 1 7 [2] B 1 8 [11] A 2 6 [11] B 2 6 [12] C 2 6 [12] A 2 7 [12] B 2 7 [13] C 2 7 [13] B 2 8 [22] B 3 8 *-* All Finished *-* verilator-5.042/test_regress/t/t_tri_cond_eqcase_with_1.py0000755000542200017500000000073415101701376024367 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_mem_slice_bad.out0000644000542200017500000000410415101701376022704 0ustar mahmoudyfreeshell%Error: t/t_mem_slice_bad.v:39:31: Slice selection index '[2:0]' outside data type's '[1:0]' : ... note: In instance 't' 39 | assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_mem_slice_bad.v:39:36: Slice selection index '[3:0]' outside data type's '[2:0]' : ... note: In instance 't' 39 | assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; | ^ %Error: t/t_mem_slice_bad.v:39:72: Slice selection index '[2:0]' outside data type's '[1:0]' : ... note: In instance 't' 39 | assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; | ^ %Error: t/t_mem_slice_bad.v:39:77: Slice selection index '[3:0]' outside data type's '[2:0]' : ... note: In instance 't' 39 | assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; | ^ %Error: t/t_mem_slice_bad.v:39:105: Slice selection index '[3:0]' outside data type's '[1:0]' : ... note: In instance 't' 39 | assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; | ^ %Error: t/t_mem_slice_bad.v:51:41: Slice selection index '[8:0]' outside data type's '[7:0]' : ... note: In instance 't' 51 | active_command4[7:0] <= command_A4[8:0]; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_math_signed4.v0000644000542200017500000001045215101701376022150 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0) `define checkf(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0) module t; bit fail; localparam signed [3:0] bug737_p1 = 4'b1000; wire [3:0] bug737_a = 4'b1010; reg [5:0] bug737_y; reg signed [3:0] w4_s; reg signed [4:0] w5_s; reg [3:0] w4_u; reg [4:0] w5_u; reg signed [8:0] w9_s; real r; initial begin // verilator lint_off WIDTH bug737_y = bug737_a + (bug737_p1 + 4'sb0); `checkh(bug737_y, 6'b010010); //bug737 // 6u +[6u] 4s +[6s] 6s bug737_y = 6'b001010 + (4'sb1000 + 6'sb0); `checkh(bug737_y, 6'b010010); //bug737, getx 000010 // 6u +[6u] 4s +[6s] 6s bug737_y = 6'b001010 + (4'b1000 + 6'sb0); `checkh(bug737_y, 6'b010010); //ok bug737_y = 6'b001010 + (6'sb111000 + 6'sb0); `checkh(bug737_y, 6'b000010); //ok // v--- sign extends to 6-bits bug737_y = 6'sb001010 + (4'sb1000 + 6'sb0); `checkh(bug737_y, 6'b000010); //ok // From t_math_signed_3 w4_s = 4'sb1111 - 1'b1; `checkh(w4_s,33'he); w4_s = 4'sb1111 - 5'b00001; `checkh(w4_s,33'he); w4_s = 4'sb1111 - 1'sb1; `checkh(w4_s,4'h0); w5_s = 4'sb1111 - 1'sb1; `checkh(w5_s,4'h0); w4_s = 4'sb1111 - 4'sb1111; `checkh(w4_s,4'h0); w5_s = 4'sb1111 - 4'sb1111; `checkh(w5_s,5'h0); // The assign LHS being signed or unsigned does not matter per IEEE // The upper add being signed DOES matter propagating to lower w4_s = 4'sb1111 - (1'sb1 + 4'b0); //1'sb1 not extended as unsigned add `checkh(w4_s,4'he); w4_s = 4'sb1111 - (1'sb1 + 4'sb0); //1'sb1 does sign extend `checkh(w4_s,4'h0); w4_s = 4'b1111 - (1'sb1 + 4'sb0); //1'sb1 does *NOT* sign extend `checkh(w4_s,4'he); // BUG, Verilator says 'h0 w5_u = 4'b1111 + 4'b0001; // Extends to 5 bits due to LHS `checkh(w5_u, 5'b10000); w4_u = 4'b1111 + 4'b0001; // Normal case `checkh(w4_u, 4'b0000); // Another example of promotion, the add is 4 bits wide w4_u = 3'b111 + 3'b010; `checkh(w4_u, 4'b1001); // w4_u = 3'sb111 * 3'sb001; // Signed output, LHS does not matter `checkh(w4_u, 4'sb1111); w4_s = 3'sb111 * 3'sb001; // Signed output `checkh(w4_s, 4'sb1111); w4_s = 3'b111 * 3'sb001; // Unsigned output `checkh(w4_s, 4'b0111); // Conditionals get width from parent; are assignment-like w4_u = 1'b0 ? 4'b0 : (2'b01+2'b11); `checkh(w4_u, 4'b0100); w4_u = 1'b0 ? 4'b0 : (6'b001000+6'b001000); `checkh(w4_u, 4'b0000); // If RHS is larger, that larger size is used w4_u = 5'b10000 / 5'b00100; `checkh(w4_u, 4'b0100); // bug754 w5_u = 4'sb0010 << -2'sd1; // << 3 `ifdef VCS `checkh(w5_u, 5'b00000); // VCS E-2014.03 bug `else `checkh(w5_u, 5'b10000); // VCS E-2014.03 bug `endif w5_u = 4'sb1000 << 0; // Sign extends `checkh(w5_u, 5'b11000); // Reals do not propagate to children r = 1.0 + ( 1 + (1 / 2)); `checkf(r, 2.0); // Self determined sign extension r = $itor(3'sb111); `checkf(r, -1.0); // If any part of case is real, all is real case (22) 22.0: ; 22.1: $stop; default: $stop; endcase // bug759 w5_u = { -4'sd7 }; `checkh(w5_u, 5'b01001); w5_u = {2{ -2'sd1 }}; `checkh(w5_u, 5'b01111); // Don't break concats.... w5_u = {{0{1'b1}}, -4'sd7 }; `checkh(w5_u, 5'b01001); w9_s = { -4'sd7, -4'sd7 }; `checkh(w9_s, 9'b010011001); {w5_u, {w4_u}} = 9'b10101_1100; `checkh(w5_u, 5'b10101); `checkh(w4_u, 4'b1100); {w4_u} = 4'b1011; `checkh(w4_u, 4'b1011); if (fail) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_func_nansi_mism_bad.v0000644000542200017500000000106515101701376023560 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef int T; module test; task t1; input [15:0] bad1; shortint bad1; // <--- Error (type doesn't match above) endtask task t2; input [31:0] bad2; T bad2; // <--- Error (type doesn't match above) endtask task t3; input [7:0] bad3; reg [3:0] bad3; // <--- Error (type doesn't match above) endtask endmodule verilator-5.042/test_regress/t/t_trace_dumpvars_dyn_saif_0.out0000644000542200017500000014053415101701376025263 0ustar mahmoudyfreeshell// Generated by verilated_saif (SAIFILE (SAIFVERSION "2.0") (DIRECTION "backward") (PROGRAM_NAME "Verilator") (DIVIDER / ) (TIMESCALE 1ps) (DURATION 20) (INSTANCE top (NET (clk (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 20)) ) (INSTANCE t (NET (clk (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 20)) (cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE sub1a (NET (ADD\[0\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[1\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (ADD\[2\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[3\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (ADD\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10)) (value\[1\] (T0 9) (T1 11) (TZ 0) (TX 0) (TB 0) (TC 6)) (value\[2\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 3)) (value\[3\] (T0 9) (T1 11) (TZ 0) (TX 0) (TB 0) (TC 2)) (value\[4\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE sub2a (NET (ADD\[0\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (ADD\[1\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (ADD\[2\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[3\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (ADD\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 11)) (value\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 6)) (value\[2\] (T0 9) (T1 11) (TZ 0) (TX 0) (TB 0) (TC 3)) (value\[3\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 2)) (value\[4\] (T0 9) (T1 11) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE sub2b (NET (ADD\[0\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[1\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[2\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (ADD\[3\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (ADD\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10)) (value\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5)) (value\[2\] (T0 8) (T1 12) (TZ 0) (TX 0) (TB 0) (TC 3)) (value\[3\] (T0 13) (T1 7) (TZ 0) (TX 0) (TB 0) (TC 2)) (value\[4\] (T0 7) (T1 13) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE sub2c (NET (ADD\[0\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (ADD\[1\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[2\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (ADD\[3\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (ADD\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 11)) (value\[1\] (T0 9) (T1 11) (TZ 0) (TX 0) (TB 0) (TC 5)) (value\[2\] (T0 8) (T1 12) (TZ 0) (TX 0) (TB 0) (TC 3)) (value\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 2)) (value\[4\] (T0 5) (T1 15) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) (INSTANCE sub1b (NET (ADD\[0\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[1\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[2\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (ADD\[3\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[4\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (ADD\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10)) (value\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5)) (value\[2\] (T0 8) (T1 12) (TZ 0) (TX 0) (TB 0) (TC 3)) (value\[3\] (T0 7) (T1 13) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[4\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE sub2a (NET (ADD\[0\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (ADD\[1\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[2\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (ADD\[3\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[4\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (ADD\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 11)) (value\[1\] (T0 9) (T1 11) (TZ 0) (TX 0) (TB 0) (TC 5)) (value\[2\] (T0 8) (T1 12) (TZ 0) (TX 0) (TB 0) (TC 3)) (value\[3\] (T0 5) (T1 15) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[4\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE sub2b (NET (ADD\[0\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[1\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (ADD\[2\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (ADD\[3\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[4\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (ADD\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10)) (value\[1\] (T0 9) (T1 11) (TZ 0) (TX 0) (TB 0) (TC 6)) (value\[2\] (T0 9) (T1 11) (TZ 0) (TX 0) (TB 0) (TC 4)) (value\[3\] (T0 4) (T1 16) (TZ 0) (TX 0) (TB 0) (TC 2)) (value\[4\] (T0 1) (T1 19) (TZ 0) (TX 0) (TB 0) (TC 2)) (value\[5\] (T0 19) (T1 1) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE sub2c (NET (ADD\[0\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (ADD\[1\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (ADD\[2\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (ADD\[3\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[4\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (ADD\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 11)) (value\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 6)) (value\[2\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 4)) (value\[3\] (T0 4) (T1 16) (TZ 0) (TX 0) (TB 0) (TC 2)) (value\[4\] (T0 3) (T1 17) (TZ 0) (TX 0) (TB 0) (TC 2)) (value\[5\] (T0 17) (T1 3) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) ) ) verilator-5.042/test_regress/t/t_interface1_modport.py0000755000542200017500000000073415101701376023557 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_enum_type_bad.py0000755000542200017500000000076315101701376022607 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dynarray_multid.py0000755000542200017500000000073415101701376023201 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_sys_system.py0000755000542200017500000000073415101701376022214 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_fork_dynscope_unsup.v0000644000542200017500000000063315101701376023701 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t; bit p = 0, q = 0; initial begin t1(p); t2(q); end task t1(inout p); fork p = #1 1; join_none endtask task t2(output q); q <= #1 1; endtask endmodule verilator-5.042/test_regress/t/t_tri_struct_pins_inout.py0000755000542200017500000000107015101701376024435 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.top_filename = "t/t_tri_struct.v" test.compile(verilator_flags2=['--binary --pins-inout-enables']) test.execute() test.passes() verilator-5.042/test_regress/t/t_param_ddeep_width.v0000644000542200017500000000122715101701376023242 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use. // SPDX-License-Identifier: CC0-1.0 // bug541 module t(clk,odata); input clk; output [7:0] odata; paramtest_DFFRE #(1) dffre0(clk,odata[7]); paramtest_WRAP #(7) dffe0(clk,odata[6:0]); endmodule module paramtest_WRAP(clk,q); parameter W=1; input clk; output [W-1:0] q; paramtest_DFFRE #(W) dffre0(clk,q); endmodule module paramtest_DFFRE(clk,q); parameter W=1; parameter [W-1:0] INIT={W{1'b0}}; input clk; output [W-1:0] q; reg [W-1:0] q; always @(posedge clk) begin q <= INIT; end endmodule verilator-5.042/test_regress/t/t_opt_life.py0000755000542200017500000000154715101701376021576 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--stats"]) if test.vlt_all: test.file_grep(test.stats, r'Optimizations, Lifetime assign deletions\s+(\d+)', 4) test.file_grep(test.stats, r'Optimizations, Lifetime creset deletions\s+(\d+)', 1) test.file_grep(test.stats, r'Optimizations, Lifetime constant prop\s+(\d+)', 5) test.file_grep(test.stats, r'Optimizations, Lifetime postassign deletions\s+(\d+)', 1) test.execute() test.passes() verilator-5.042/test_regress/t/t_user_type_xassign.v0000644000542200017500000000162215101701376023354 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Demonstrate complex user typea problem with --x-assign // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; typedef logic [31:0] int_t; typedef int_t [6:0] bar_t; bar_t the_bar; logic [31:0] thing_one; always_comb begin for (int sel = 0; sel < 1; sel++) thing_one = the_bar[sel]; end virtual class SomeClass; static function logic compare(int a, int b); return a > b; endfunction endclass logic [31:0] thing_two; always_comb begin for (int sel_a = 0; sel_a < 1; sel_a++) thing_two = the_bar[sel_a]; end // finish report always @ (posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_opt_merge_cond_bug_3409.v0000644000542200017500000000475415101701376024112 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Raynard Qiao. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [3:0] din = crc[3:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire row_found; // From test of Test.v wire [1:0] row_idx; // From test of Test.v // End of automatics Test test(/*AUTOINST*/ // Outputs .row_idx (row_idx[1:0]), .row_found (row_found), // Inputs .din (din)); // Aggregate outputs into a single result vector wire [63:0] result = {48'b0, din, 7'b0, row_found, 2'b0, row_idx}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc == 0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc < 10) begin sum <= '0; end else if (cyc == 99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h8b61595b704e511f if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test(/*AUTOARG*/ // Outputs row_idx, row_found, // Inputs din ); input din; output [1:0] row_idx; output row_found; reg [3:0] din; reg [3:0] wide_din; reg row_found; reg [1:0] row_idx; always_comb begin integer x; row_idx = {2{1'b0}}; row_found = 1'b0; // Issue #3409: After unrolling, these conditionals should not be merged // as row_found is assigned. for (x = 0; $unsigned(x) < 4; x = x + 1) begin row_idx = !row_found ? x[1:0] : row_idx; row_found = !row_found ? din[x] : row_found; end end endmodule verilator-5.042/test_regress/t/t_lint_blkseq_noedge.py0000755000542200017500000000076515101701376023626 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=['-Wall', '-Wno-DECLFILENAME']) test.passes() verilator-5.042/test_regress/t/t_package_dup_bad.v0000644000542200017500000000077715101701376022664 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package pkg; localparam PARAM = 10; endpackage package pkg; localparam PARAM = 10; endpackage module sub import pkg::*; #( ) (); endmodule package pkg; endpackage package pkg; endpackage module t; sub sub (); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_extract_static_const.out0000644000542200017500000000015515101701376024372 0ustar mahmoudyfreeshell0x88888888 0x77777777 0x66666666 0x55555555 0x44444444 0x33333333 0x22222222 0x11111111 *-* All Finished *-* verilator-5.042/test_regress/t/t_lint_incabspath_bad.py0000755000542200017500000000115515101701376023740 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_lint_incabspath.v" test.lint(verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_sys_file_scan.py0000755000542200017500000000115515101701376022611 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.unlink_ok(test.obj_dir + "/t_sys_file_scan_test.log") test.compile() test.execute() test.file_grep(test.obj_dir + "/t_sys_file_scan_test.log", r"""# a 1 """) test.passes() verilator-5.042/test_regress/t/t_order_blkandnblk_bad.out0000644000542200017500000000356115101701376024252 0ustar mahmoudyfreeshell%Warning-MULTIDRIVEN: t/t_order_blkandnblk_bad.v:33:6: Variable also written to in always_comb (IEEE 1800-2023 9.2.2.2): 'unpacked' : ... note: In instance 't' t/t_order_blkandnblk_bad.v:33:6: 33 | unpacked.b <= unpacked.a; | ^~~~~~~~ t/t_order_blkandnblk_bad.v:30:16: ... Location of always_comb write 30 | always_comb unpacked.a = i; | ^~~~~~~~ ... For warning description see https://verilator.org/warn/MULTIDRIVEN?v=latest ... Use "/* verilator lint_off MULTIDRIVEN */" and lint_on around source to disable this message. %Error-BLKANDNBLK: t/t_order_blkandnblk_bad.v:18:21: Unsupported: Blocking and non-blocking assignments to potentially overlapping bits of same packed variable: 't.array' 18 | logic [1:0][3:0] array; | ^~~~~ t/t_order_blkandnblk_bad.v:20:25: ... Location of blocking assignment (bits [3:0]) 20 | always_comb array[0] = i; | ^ t/t_order_blkandnblk_bad.v:23:6: ... Location of nonblocking assignment (bits [3:0]) 23 | array[0] <= array[0]; | ^~~~~ ... For error description see https://verilator.org/warn/BLKANDNBLK?v=latest %Error-BLKANDNBLK: t/t_order_blkandnblk_bad.v:28:6: Unsupported: Blocking and non-blocking assignments to same non-packed variable: 't.unpacked' 28 | } unpacked; | ^~~~~~~~ t/t_order_blkandnblk_bad.v:30:16: ... Location of blocking assignment 30 | always_comb unpacked.a = i; | ^~~~~~~~ t/t_order_blkandnblk_bad.v:33:6: ... Location of nonblocking assignment 33 | unpacked.b <= unpacked.a; | ^~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_gen_var_bad.v0000644000542200017500000000053215101701376022027 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; integer i; generate for (i=0; i<3; i=i+1) begin // Bad: i is not a genvar end endgenerate endmodule verilator-5.042/test_regress/t/t_param_pattern2.v0000644000542200017500000000072015101701376022516 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2021 by Ryszard Rozak. // SPDX-License-Identifier: CC0-1.0 module dut #(parameter int P [5]) (output int x); assign x = P[2]; endmodule module t(); int o; dut #(.P('{1, 2, 3, 4, 5})) u_dut(.x(o)); initial begin if (o !== 3) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_cast_class_incompat_bad.out0000644000542200017500000000135115101701376024761 0ustar mahmoudyfreeshell%Error: t/t_cast_class_incompat_bad.v:26:28: Dynamic, not static cast, required to cast 'class{}BaseExtended' from 'class{}Base' : ... note: In instance 't' : ... Suggest dynamic $cast 26 | cls_ab = BaseExtended'(cls_a); | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_cast_class_incompat_bad.v:27:20: Incompatible types to static cast to 'class{}Other' from 'class{}BaseExtended' : ... note: In instance 't' 27 | other = Other'(cls_ab); | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_dpi_lib.v0000644000542200017500000000130015101701376021174 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2017 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; import "DPI-C" function int dpii_failure(); import "DPI-C" function void dpii_check(); initial begin dpii_check(); if (dpii_failure()!=0) begin $write("%%Error: Failure in DPI tests\n"); $stop; end else begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_x_assign_1.py0000755000542200017500000000124115101701376022017 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_x_assign.cpp" test.top_filename = "t/t_x_assign.v" test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--x-assign 1 --exe", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_class_param_bad_paren.out0000644000542200017500000000056415101701376024427 0ustar mahmoudyfreeshell%Error: t/t_class_param_bad_paren.v:28:11: Reference to parameterized class without #() (IEEE 1800-2023 8.25.1) : ... Suggest use 'Cls#()' 28 | if (Cls::OTHER != 12) $stop; | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_math_cv_format.v0000644000542200017500000000331615101701376022574 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t; wire signed [21:10] out0; sub sub ( .out0(out0) ); sub2 sub2 (); string s; initial begin #20; // Bug with sformat, so can't just number-compare s = $sformatf("out0=%0d", out0); `checks(s, "out0=-12"); if (out0 > 0) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module sub (out0); reg signed [27:20] reg_4; output wire [21:10] out0; initial begin #1; reg_4 = 0; end wire [11:0] w55; wire [11:0] w23; // verilator lint_off WIDTHEXPAND assign w55 = ~reg_4[20]; // verilator lint_on WIDTHEXPAND assign { w23[3], w23[1:0] } = 3'h0; assign { w23[11:4], w23[2] } = { w55[11:4], w55[2] }; assign out0 = w23; endmodule module sub2; reg [27:5] in0; reg [26:11] in1; wire [24:14] wire_0; wire [26:5] out1; wire w085; wire w082; wire [10:0] w092; wire [9:0] w028; string s; initial begin in0 = 6902127; in1 = 10000; #10; s = $sformatf("out0=%0d", out1); `checks(s, "out0=0"); end assign w028 = ~ { 9'h000, in0[23] }; assign w092[1] = 1'h0; assign { w092[10:2], w092[0] } = w028; assign wire_0 = w092; assign w082 = | wire_0[18:17]; assign w085 = w082 ? in1[11] : 1'h0; assign out1 = { 21'h000000, w085 }; endmodule verilator-5.042/test_regress/t/t_interface1_modport_nansi.py0000755000542200017500000000104515101701376024743 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface1_modport.v" test.compile(v_flags2=['+define+NANSI']) test.execute() test.passes() verilator-5.042/test_regress/t/t_cover_assert.py0000755000542200017500000000110015101701376022455 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["-Wall -Wno-DECLFILENAME --coverage"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dpi_result_type.v0000644000542200017500000004216415101701376023022 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2020 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VCS `define NO_REAL_EXPORT `endif `ifdef NC `define NO_STRUCT_OR_UNION `define NO_SHORTREAL `endif `ifdef MS `define NO_STRUCT_OR_UNION `define NO_ARRAY `endif `ifdef VERILATOR `define NO_SHORTREAL `define NULL 64'd0 `else `define NULL null `endif module t (/*AUTOARG*/ // Inputs clk ); input clk; `ifdef VERILATOR wire _unused = &{1'b0, clk}; `endif // Legal result types for DPI functions //====================================================================== // Type definitions //====================================================================== // Basic types as per IEEE 1800-2023 35.5.5 typedef byte byte_t; typedef byte unsigned byte_unsigned_t; typedef shortint shortint_t; typedef shortint unsigned shortint_unsigned_t; typedef int int_t; typedef int unsigned int_unsigned_t; typedef longint longint_t; typedef longint unsigned longint_unsigned_t; typedef real real_t; `ifndef NO_SHORTREAL typedef shortreal shortreal_t; `endif typedef chandle chandle_t; typedef string string_t; typedef bit bit_t; typedef logic logic_t; // 2-state packed structures of width <= 32 typedef struct packed { bit x; } struct_2_state_1; typedef struct packed { bit [15:0] x; bit [15:0] y; } struct_2_state_32; // 2-state packed unions of width <= 32 typedef union packed { bit x; bit y; } union_2_state_1; typedef union packed { bit [31:0] x; bit [31:0] y; } union_2_state_32; //====================================================================== // Imports //====================================================================== // Basic types as per IEEE 1800-2023 35.5.5 import "DPI-C" function void i_void (); import "DPI-C" function byte i_byte (); import "DPI-C" function byte unsigned i_byte_unsigned (); import "DPI-C" function shortint i_shortint (); import "DPI-C" function shortint unsigned i_shortint_unsigned (); import "DPI-C" function int i_int (); import "DPI-C" function int unsigned i_int_unsigned (); import "DPI-C" function longint i_longint (); import "DPI-C" function longint unsigned i_longint_unsigned (); import "DPI-C" function real i_real (); `ifndef NO_SHORTREAL import "DPI-C" function shortreal i_shortreal (); `endif import "DPI-C" function chandle i_chandle (); import "DPI-C" function string i_string (); import "DPI-C" function bit i_bit (); import "DPI-C" function logic i_logic (); // Basic types via typedef import "DPI-C" function byte_t i_byte_t (); import "DPI-C" function byte_unsigned_t i_byte_unsigned_t (); import "DPI-C" function shortint_t i_shortint_t (); import "DPI-C" function shortint_unsigned_t i_shortint_unsigned_t (); import "DPI-C" function int_t i_int_t (); import "DPI-C" function int_unsigned_t i_int_unsigned_t (); import "DPI-C" function longint_t i_longint_t (); import "DPI-C" function longint_unsigned_t i_longint_unsigned_t (); import "DPI-C" function real_t i_real_t (); `ifndef NO_SHORTREAL import "DPI-C" function shortreal_t i_shortreal_t (); `endif import "DPI-C" function chandle_t i_chandle_t (); import "DPI-C" function string_t i_string_t (); import "DPI-C" function bit_t i_bit_t (); import "DPI-C" function logic_t i_logic_t (); `ifndef NO_ARRAY // 2-state packed arrays of width <= 32 import "DPI-C" function bit [ 0:0] i_array_2_state_1 (); import "DPI-C" function bit [31:0] i_array_2_state_32 (); `endif `ifndef NO_STRUCT_OR_UNION // 2-state packed structures of width <= 32 import "DPI-C" function struct_2_state_1 i_struct_2_state_1 (); import "DPI-C" function struct_2_state_32 i_struct_2_state_32(); // 2-state packed unions of width <= 32 import "DPI-C" function union_2_state_1 i_union_2_state_1 (); import "DPI-C" function union_2_state_32 i_union_2_state_32(); `endif //====================================================================== // Exports //====================================================================== // Basic types as per IEEE 1800-2023 35.5.5 export "DPI-C" function e_void; export "DPI-C" function e_byte; export "DPI-C" function e_byte_unsigned; export "DPI-C" function e_shortint; export "DPI-C" function e_shortint_unsigned; export "DPI-C" function e_int; export "DPI-C" function e_int_unsigned; export "DPI-C" function e_longint; export "DPI-C" function e_longint_unsigned; `ifndef NO_REAL_EXPORT export "DPI-C" function e_real; `endif `ifndef NO_SHORTREAL export "DPI-C" function e_shortreal; `endif export "DPI-C" function e_chandle; export "DPI-C" function e_string; export "DPI-C" function e_bit; export "DPI-C" function e_logic; // Basic types via typedef export "DPI-C" function e_byte_t; export "DPI-C" function e_byte_unsigned_t; export "DPI-C" function e_shortint_t; export "DPI-C" function e_shortint_unsigned_t; export "DPI-C" function e_int_t; export "DPI-C" function e_int_unsigned_t; export "DPI-C" function e_longint_t; export "DPI-C" function e_longint_unsigned_t; `ifndef NO_REAL_EXPORT export "DPI-C" function e_real_t; `endif `ifndef NO_SHORTREAL export "DPI-C" function e_shortreal_t; `endif export "DPI-C" function e_chandle_t; export "DPI-C" function e_string_t; export "DPI-C" function e_bit_t; export "DPI-C" function e_logic_t; `ifndef NO_ARRAY // 2-state packed arrays of width <= 32 export "DPI-C" function e_array_2_state_1; export "DPI-C" function e_array_2_state_32; `endif `ifndef NO_STRUCT_OR_UNION // 2-state packed structures of width <= 32 export "DPI-C" function e_struct_2_state_1; export "DPI-C" function e_struct_2_state_32; // 2-state packed unions of width <= 32 export "DPI-C" function e_union_2_state_1; export "DPI-C" function e_union_2_state_32; `endif //====================================================================== // Definitions of exported functions //====================================================================== // Static variables (Note: Verilator strangely assumes everything inside // a function is automatic, which is exactly the opposite of the standard // see IEEE 1800-2023 13.3.1 and 13.4.2 // Basic types as per IEEE 1800-2023 35.5.5 int n_void = 0; function void e_void(); $display("e_void %1d", n_void); n_void++; endfunction byte n_byte = 0; function byte e_byte(); e_byte = 8'd10 + n_byte; n_byte++; endfunction byte n_byte_unsigned = 0; function byte unsigned e_byte_unsigned(); e_byte_unsigned = 8'd20 + n_byte_unsigned; n_byte_unsigned++; endfunction shortint n_shortint = 0; function shortint e_shortint(); e_shortint = 16'd30 + n_shortint; n_shortint++; endfunction shortint n_shortint_unsigned = 0; function shortint unsigned e_shortint_unsigned(); e_shortint_unsigned = 16'd40 + n_shortint_unsigned; n_shortint_unsigned++; endfunction int n_int = 0; function int e_int(); e_int = 32'd50 + n_int; n_int++; endfunction int n_int_unsigned = 0; function int unsigned e_int_unsigned(); e_int_unsigned = 32'd60 + n_int_unsigned; n_int_unsigned++; endfunction longint n_longint = 0; function longint e_longint(); e_longint = 64'd70 + n_longint; n_longint++; endfunction longint n_longint_unsigned = 0; function longint unsigned e_longint_unsigned(); e_longint_unsigned = 64'd80 + n_longint_unsigned; n_longint_unsigned++; endfunction `ifndef NO_REAL_EXPORT int n_real = 0; function real e_real(); e_real = real'(2*n_real + 1) / 2.0; n_real++; endfunction `endif `ifndef NO_SHORTREAL int n_shortreal = 0; function shortreal e_shortreal(); e_shortreal = shortreal'(4*n_shortreal + 1)/ 4.0; n_shortreal++; endfunction `endif int n_chandle = 0; function chandle e_chandle(); $display("e_chandle %1d", n_chandle); e_chandle = `NULL; n_chandle++; endfunction int n_string = 0; function string e_string(); $display("e_string %1d", n_string); e_string = n_string[0] ? "World" : "Hello"; n_string++; endfunction int n_bit = 0; function bit e_bit(); $display("e_bit %1d", n_bit); e_bit = n_bit[0]; n_bit++; endfunction int n_logic = 0; function logic e_logic(); $display("e_logic %1d", n_logic); e_logic = ~n_logic[0]; n_logic++; endfunction // Basic types via typedefs byte_t n_byte_t = 0; function byte_t e_byte_t(); e_byte_t = 8'd10 + n_byte_t; n_byte_t += 2; endfunction byte n_byte_unsigned_t = 0; function byte_unsigned_t e_byte_unsigned_t(); e_byte_unsigned_t = 8'd20 + n_byte_unsigned_t; n_byte_unsigned_t += 2; endfunction shortint_t n_shortint_t = 0; function shortint_t e_shortint_t(); e_shortint_t = 16'd30 + n_shortint_t; n_shortint_t += 2; endfunction shortint n_shortint_unsigned_t = 0; function shortint_unsigned_t e_shortint_unsigned_t(); e_shortint_unsigned_t = 16'd40 + n_shortint_unsigned_t; n_shortint_unsigned_t += 2; endfunction int_t n_int_t = 0; function int_t e_int_t(); e_int_t = 32'd50 + n_int_t; n_int_t += 2; endfunction int n_int_unsigned_t = 0; function int_unsigned_t e_int_unsigned_t(); e_int_unsigned_t = 32'd60 + n_int_unsigned_t; n_int_unsigned_t += 2; endfunction longint_t n_longint_t = 0; function longint_t e_longint_t(); e_longint_t = 64'd70 + n_longint_t; n_longint_t += 2; endfunction longint n_longint_unsigned_t = 0; function longint_unsigned_t e_longint_unsigned_t(); e_longint_unsigned_t = 64'd80 + n_longint_unsigned_t; n_longint_unsigned_t += 2; endfunction `ifndef NO_REAL_EXPORT int n_real_t = 0; function real_t e_real_t(); e_real_t = real'(2*n_real_t + 1) / 2.0; n_real_t += 2; endfunction `endif `ifndef NO_SHORTREAL int n_shortreal_t = 0; function shortreal_t e_shortreal_t(); e_shortreal_t = shortreal'(4*n_shortreal_t + 1)/ 4.0; n_shortreal_t += 2; endfunction `endif int n_chandle_t = 0; function chandle_t e_chandle_t(); $display("e_chandle_t %1d", n_chandle_t); e_chandle_t = `NULL; n_chandle_t++; endfunction int n_string_t = 0; function string_t e_string_t(); $display("e_string_t %1d", n_string_t); e_string_t = n_string_t[0] ? "World" : "Hello"; n_string_t++; endfunction int n_bit_t = 0; function bit_t e_bit_t(); $display("e_bit_t %1d", n_bit_t); e_bit_t = n_bit_t[0]; n_bit_t++; endfunction int n_logic_t = 0; function logic_t e_logic_t(); $display("e_logic_t %1d", n_logic_t); e_logic_t = ~n_logic_t[0]; n_logic_t++; endfunction `ifndef NO_ARRAY // 2-state packed arrays of width <= 32 int n_array_2_state_1 = 0; function bit [ 0:0] e_array_2_state_1(); $display("e_array_2_state_1 %1d", n_array_2_state_1); e_array_2_state_1 = n_array_2_state_1[0]; n_array_2_state_1++; endfunction int n_array_2_state_32 = 0; function bit [31:0] e_array_2_state_32(); $display("e_array_2_state_32 %1d", n_array_2_state_32); e_array_2_state_32 = ~32'd0 >> n_array_2_state_32; n_array_2_state_32++; endfunction `endif `ifndef NO_STRUCT_OR_UNION // 2-state packed structures of width <= 32 int n_struct_2_state_1 = 0; function struct_2_state_1 e_struct_2_state_1(); $display("e_struct_2_state_1 %1d", n_struct_2_state_1); e_struct_2_state_1 = n_struct_2_state_1[0]; n_struct_2_state_1++; endfunction int n_struct_2_state_32 = 0; function struct_2_state_32 e_struct_2_state_32(); $display("e_struct_2_state_32 %1d", n_struct_2_state_32); e_struct_2_state_32 = ~32'd0 >> n_struct_2_state_32; n_struct_2_state_32++; endfunction // 2-state packed unions of width <= 32 int n_union_2_state_1 = 0; function union_2_state_1 e_union_2_state_1(); $display("e_union_2_state_1 %1d", n_union_2_state_1); e_union_2_state_1 = n_union_2_state_1[0]; n_union_2_state_1++; endfunction int n_union_2_state_32 = 0; function union_2_state_32 e_union_2_state_32(); $display("e_union_2_state_32 %1d", n_union_2_state_32); e_union_2_state_32 = ~32'd0 >> n_union_2_state_32; n_union_2_state_32++; endfunction `endif //====================================================================== // Invoke all functions 3 times (they have side effects) //====================================================================== import "DPI-C" context function void check_exports(); initial begin for (int i = 0 ; i < 3; i++) begin // Check the imports // Basic types as per IEEE 1800-2023 35.5.5 i_void(); if (i_byte() !== 8'd10 - 8'(i)) $stop; if (i_byte_unsigned() !== 8'd20 - 8'(i)) $stop; if (i_shortint() !== 16'd30 - 16'(i)) $stop; if (i_shortint_unsigned() !== 16'd40 - 16'(i)) $stop; if (i_int() !== 32'd50 - 32'(i)) $stop; if (i_int_unsigned() !== 32'd60 - 32'(i)) $stop; if (i_longint() !== 64'd70 - 64'(i)) $stop; if (i_longint_unsigned() !== 64'd80 - 64'(i)) $stop; if (i_real() != -1.0*i - 0.5 ) $stop; `ifndef NO_SHORTREAL if (i_shortreal() != -1.0*i - 0.25) $stop; `endif if (~i[0]) begin if (i_chandle() !== `NULL) $stop; if (i_string() != "World") $stop; end else begin if (i_chandle() === `NULL) $stop; if (i_string() != "Hello") $stop; end if (i_bit() !== ~i[0]) $stop; if (i_logic() !== i[0]) $stop; // Basic types via typedefs if (i_byte_t() !== 8'd10 - 8'(2*i)) $stop; if (i_byte_unsigned_t() !== 8'd20 - 8'(2*i)) $stop; if (i_shortint_t() !== 16'd30 - 16'(2*i)) $stop; if (i_shortint_unsigned_t() !== 16'd40 - 16'(2*i)) $stop; if (i_int_t() !== 32'd50 - 32'(2*i)) $stop; if (i_int_unsigned_t() !== 32'd60 - 32'(2*i)) $stop; if (i_longint_t() !== 64'd70 - 64'(2*i)) $stop; if (i_longint_unsigned_t() !== 64'd80 - 64'(2*i)) $stop; if (i_real_t() != -1.0*(2*i) - 0.5 ) $stop; `ifndef NO_SHORTREAL if (i_shortreal_t() != -1.0*(2*i) - 0.25) $stop; `endif if (~i[0]) begin if (i_chandle_t() !== `NULL) $stop; if (i_string_t() != "World") $stop; end else begin if (i_chandle_t() === `NULL) $stop; if (i_string_t() != "Hello") $stop; end if (i_bit_t() !== ~i[0]) $stop; if (i_logic_t() !== i[0]) $stop; `ifndef NO_ARRAY // 2-state packed arrays of width <= 32 if (i_array_2_state_1() !== ~i[0] ) $stop; if (i_array_2_state_32() !== ~32'd0 << i) $stop; `endif `ifndef NO_STRUCT_OR_UNION // 2-state packed structures of width <= 32 if (i_struct_2_state_1() !== ~i[0] ) $stop; if (i_struct_2_state_32() !== ~32'd0 << i) $stop; // 2-state packed unions of width <= 32 if (i_union_2_state_1() !== ~i[0] ) $stop; if (i_union_2_state_32() !== ~32'd0 << i) $stop; `endif // Check the exports check_exports(); end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_trace_jumps_do_while_saif.py0000755000542200017500000000114215101701376025154 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_jumps_do_while.v" test.compile(verilator_flags2=['--trace-saif']) test.execute() test.saif_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_force_chained.out0000644000542200017500000000034015101701376022710 0ustar mahmoudyfreeshell%Error: t/t_force_chained.v:27: got='h0 exp='h00000001 %Error: t/t_force_chained.v:33: got='h0 exp='h00000002 %Error: t/t_force_chained.v:40: got='h0 exp='h00000003 %Error: t/t_force_chained.v:46: got='h0 exp='h00000003 verilator-5.042/test_regress/t/t_var_suggest_bad.v0000644000542200017500000000052215101701376022736 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg foobar; task boobar; endtask initial begin if (foobat) $stop; boobat; end endmodule verilator-5.042/test_regress/t/t_implements_typed.py0000755000542200017500000000071415101701376023352 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.passes() verilator-5.042/test_regress/t/t_semaphore_class_nested.py0000755000542200017500000000075115101701376024503 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.passes() verilator-5.042/test_regress/t/t_class_assign_cond_bad.v0000644000542200017500000000101015101701376024052 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class Cls1; endclass class Cls2; endclass class ExtCls1; endclass module t; Cls1 c1; Cls2 c2; ExtCls1 ext_c1; initial begin c1 = (c1 != null) ? c1 : c2; c1 = (c1 != null) ? c2 : c2; c2 = (c1 == null) ? 1'b1 : c2; ext_c1 = (c1 == null) ? ext_c1 : c1; end endmodule verilator-5.042/test_regress/t/t_opt_inline_funcs_no.py0000755000542200017500000000121515101701376024017 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_opt_inline_funcs.v" test.compile(verilator_flags2=['--fno-inline-funcs', '--stats'], verilator_make_gmake=False) test.file_grep(test.stats, r'Optimizations, Functions inlined\s+(\d+)', 0) test.passes() verilator-5.042/test_regress/t/t_display_type_bad.out0000644000542200017500000000254615101701376023465 0ustar mahmoudyfreeshell%Error: t/t_display_type_bad.v:10:31: $display-line format of '%d' illegal with string argument : ... note: In instance 't' : ... Suggest use '%s' 10 | $display("%d %x %f %t", s, s, s, s); | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_display_type_bad.v:10:34: $display-line format of '%x' illegal with string argument : ... note: In instance 't' : ... Suggest use '%s' 10 | $display("%d %x %f %t", s, s, s, s); | ^ %Error: t/t_display_type_bad.v:10:37: $display-line format of '%f' illegal with string argument : ... note: In instance 't' : ... Suggest use '%s' 10 | $display("%d %x %f %t", s, s, s, s); | ^ %Error: t/t_display_type_bad.v:10:40: $display-line format of '%t' illegal with string argument : ... note: In instance 't' : ... Suggest use '%s' 10 | $display("%d %x %f %t", s, s, s, s); | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_select_out_of_range.v0000644000542200017500000000104415101701376023605 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module serial_adder( input cin, output cout ); localparam WIDTH = 8; wire [WIDTH:0] c; generate for (genvar i = 0; i < WIDTH; i++) full_adder fa(c[i+1]); endgenerate assign c[0] = cin; assign cout = c[WIDTH+1]; // intentional out-of-range endmodule module full_adder (output cout); endmodule verilator-5.042/test_regress/t/t_opt_table_sparse.py0000755000542200017500000000130215101701376023310 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--stats"]) if test.vlt_all: test.file_grep(test.stats, r'Optimizations, Tables created\s+(\d+)', 1) test.file_grep(test.stats, r'ConstPool, Tables emitted\s+(\d+)', 2) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_queue_struct.v0000644000542200017500000000175415101701376022337 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t; typedef struct { int b[$]; } st_t; typedef struct { int v; } st_in_t; function automatic st_t bar(); // verilator no_inline_task for (int i = 0; i < 4; ++i) begin bar.b.push_back(i); end endfunction // bar st_t res; st_in_t q[$]; initial begin res = bar(); `checkd(res.b[0], 0); `checkd(res.b[1], 1); `checkd(res.b[2], 2); `checkd(res.b[3], 3); q.push_back(st_in_t'{15}); q[0].v++; `checkd(q[0].v, 16); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_dpi_arg_output_unpack.cpp0000644000542200017500000010601415101701376024505 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2020 by Yutetsu TAKATSUKASA. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include #include #include #include #include // clang-format off #if defined(NCSC) // Used by NC's svdpi.h to pick up svLogicVecVal with _.aval and _.bval fields, // rather than the IEEE 1800-2005 version which has _.a and _.b fields. # define DPI_COMPATIBILITY_VERSION_1800v2012 #endif #include "svdpi.h" #if defined(VERILATOR) // Verilator # include "Vt_dpi_arg_output_unpack__Dpi.h" typedef long long sv_longint_t; typedef unsigned long long sv_longint_unsigned_t; # define NO_SHORTREAL # define NO_UNPACK_STRUCT # define CONSTARG const #elif defined(VCS) // VCS # include "../vc_hdrs.h" typedef long long sv_longint_t; typedef unsigned long long sv_longint_unsigned_t; # define NO_TIME # define CONSTARG const #elif defined(NCSC) // NC # include "dpi-exp.h" # include "dpi-imp.h" typedef long long sv_longint_t; typedef unsigned long long sv_longint_unsigned_t; # define NO_TIME # define NO_INTEGER # define NO_SHORTREAL // Sadly NC does not declare pass-by reference input arguments as const # define CONSTARG #elif defined(MS) // ModelSim # include "dpi.h" typedef int64_t sv_longint_t; typedef uint64_t sv_longint_unsigned_t; # define CONSTARG const #else # error "Unknown simulator for DPI test" #endif // clang-format on //====================================================================== // Implementations of imported functions //====================================================================== namespace { // unnamed namespace const bool VERBOSE_MESSAGE = false; #define stop() \ do { \ printf(__FILE__ ":%d Bad value\n", __LINE__); \ abort(); \ } while (0) void set_uint(svLogicVecVal* v0, sv_longint_unsigned_t val, int bitwidth) { for (int i = 0; i < bitwidth; ++i) { if (i < 64) svPutBitselLogic(v0, i, (val >> i) & 1); else svPutBitselLogic(v0, i, 0); } } void set_uint(svBitVecVal* v0, sv_longint_unsigned_t val, int bitwidth) { for (int i = 0; i < bitwidth; ++i) { if (i < 64) svPutBitselBit(v0, i, (val >> i) & 1); else svPutBitselBit(v0, i, 0); } } template void set_0d(T* v) { *v = 42; } template void set_1d(T* v) { v[0] = 43; v[1] = 44; } template void set_2d(T* v) { v[0 * 2 + 1] = 45; v[1 * 2 + 1] = 46; v[2 * 2 + 1] = 47; } template void set_3d(T* v) { v[(0 * 3 + 0) * 2 + 0] = 48; v[(1 * 3 + 0) * 2 + 0] = 49; v[(2 * 3 + 0) * 2 + 0] = 50; v[(3 * 3 + 0) * 2 + 0] = 51; } template void set_1d1(T* v) { v[0] = 52; } template void set_2d1(T* v) { v[0] = 53; } template void set_3d1(T* v) { v[0] = 54; } void set_0d(svLogicVecVal* v, int bitwidth) { set_uint(v, 42, bitwidth); } void set_1d(svLogicVecVal* v, int bitwidth) { const int unit = (bitwidth + 31) / 32; set_uint(v + 0 * unit, 43, bitwidth); set_uint(v + 1 * unit, 44, bitwidth); } void set_2d(svLogicVecVal* v, int bitwidth) { const int unit = (bitwidth + 31) / 32; set_uint(v + (0 * 2 + 1) * unit, 45, bitwidth); set_uint(v + (1 * 2 + 1) * unit, 46, bitwidth); set_uint(v + (2 * 2 + 1) * unit, 47, bitwidth); } void set_3d(svLogicVecVal* v, int bitwidth) { const int unit = (bitwidth + 31) / 32; set_uint(v + ((0 * 3 + 0) * 2 + 0) * unit, 48, bitwidth); set_uint(v + ((1 * 3 + 0) * 2 + 0) * unit, 49, bitwidth); set_uint(v + ((2 * 3 + 0) * 2 + 0) * unit, 50, bitwidth); set_uint(v + ((3 * 3 + 0) * 2 + 0) * unit, 51, bitwidth); } void set_1d1(svLogicVecVal* v, int bitwidth) { set_uint(v, 52, bitwidth); } void set_2d1(svLogicVecVal* v, int bitwidth) { set_uint(v, 53, bitwidth); } void set_3d1(svLogicVecVal* v, int bitwidth) { set_uint(v, 54, bitwidth); } void set_0d_scalar(svScalar* v) { *v = sv_0; } void set_1d_scalar(svScalar* v) { v[0] = sv_1; v[1] = sv_0; } void set_2d_scalar(svScalar* v) { v[0 * 2 + 1] = sv_1; v[1 * 2 + 1] = sv_0; v[2 * 2 + 1] = sv_1; } void set_3d_scalar(svScalar* v) { v[(0 * 3 + 0) * 2 + 0] = sv_0; v[(1 * 3 + 0) * 2 + 0] = sv_1; v[(2 * 3 + 0) * 2 + 0] = sv_0; v[(3 * 3 + 0) * 2 + 0] = sv_1; } void set_1d1_scalar(svScalar* v) { v[0] = sv_0; } void set_2d1_scalar(svScalar* v) { v[0] = sv_1; } void set_3d1_scalar(svScalar* v) { v[0] = sv_0; } void set_0d(svBitVecVal* v, int bitwidth) { set_uint(v, 42, bitwidth); } void set_1d(svBitVecVal* v, int bitwidth) { const int unit = (bitwidth + 31) / 32; set_uint(v + 0 * unit, 43, bitwidth); set_uint(v + 1 * unit, 44, bitwidth); } void set_2d(svBitVecVal* v, int bitwidth) { const int unit = (bitwidth + 31) / 32; set_uint(v + (0 * 2 + 1) * unit, 45, bitwidth); set_uint(v + (1 * 2 + 1) * unit, 46, bitwidth); set_uint(v + (2 * 2 + 1) * unit, 47, bitwidth); } void set_3d(svBitVecVal* v, int bitwidth) { const int unit = (bitwidth + 31) / 32; set_uint(v + ((0 * 3 + 0) * 2 + 0) * unit, 48, bitwidth); set_uint(v + ((1 * 3 + 0) * 2 + 0) * unit, 49, bitwidth); set_uint(v + ((2 * 3 + 0) * 2 + 0) * unit, 50, bitwidth); set_uint(v + ((3 * 3 + 0) * 2 + 0) * unit, 51, bitwidth); } void set_1d1(svBitVecVal* v, int bitwidth) { set_uint(v, 52, bitwidth); } void set_2d1(svBitVecVal* v, int bitwidth) { set_uint(v, 53, bitwidth); } void set_3d1(svBitVecVal* v, int bitwidth) { set_uint(v, 54, bitwidth); } template bool compare(const T& act, const T& exp) { if (exp == act) { if (VERBOSE_MESSAGE) std::cout << "OK Exp:" << exp << " actual:" << act << std::endl; return true; } else { std::cout << "NG Exp:" << exp << " actual:" << act << std::endl; return false; } } template bool check_0d(T v) { return compare(v, 42); } template bool check_1d(const T (&v)[2]) { return compare(v[0], 43) && compare(v[1], 44); } template bool check_2d(const T (&v)[3][2]) { return compare(v[0][1], 45) && compare(v[1][1], 46) && compare(v[2][1], 47); } template bool check_3d(const T (&v)[4][3][2]) { return compare(v[0][0][0], 48) && compare(v[1][0][0], 49) && compare(v[2][0][0], 50) && compare(v[3][0][0], 51); } template bool check_1d1(const T (&v)[1]) { return compare(v[0], 52); } template bool check_2d1(const T (&v)[1][1]) { return compare(v[0][0], 53); } template bool check_3d1(const T (&v)[1][1][1]) { return compare(v[0][0][0], 54); } bool compare(const svLogicVecVal* v0, sv_longint_unsigned_t val, int bitwidth) { for (int i = 0; i < bitwidth; ++i) { const bool act_bit = svGetBitselLogic(v0, i); const bool exp_bit = (i < 64) ? ((val >> i) & 1) : false; if (act_bit != exp_bit) { std::cout << "Mismatch at bit:" << i << " exp:" << exp_bit << " act:" << act_bit; return false; } } if (VERBOSE_MESSAGE) { std::cout << "OK " << val << " as expected (width:" << bitwidth << ")" << std::endl; } return true; } bool compare(const svBitVecVal* v0, sv_longint_unsigned_t val, int bitwidth) { for (int i = 0; i < bitwidth; ++i) { const bool act_bit = svGetBitselBit(v0, i); const bool exp_bit = (i < 64) ? ((val >> i) & 1) : false; if (act_bit != exp_bit) { std::cout << "Mismatch at bit:" << i << " exp:" << exp_bit << " act:" << act_bit; return false; } } if (VERBOSE_MESSAGE) { std::cout << "OK " << val << " as expected (width:" << bitwidth << ")" << std::endl; } return true; } template bool check_0d(const T (&v)[N], int bitwidth) { return compare(v, 42, bitwidth); } template bool check_1d(const T (&v)[2][N], int bitwidth) { return compare(v[0], 43, bitwidth) && compare(v[1], 44, bitwidth); } template bool check_2d(const T (&v)[3][2][N], int bitwidth) { return compare(v[0][1], 45, bitwidth) && compare(v[1][1], 46, bitwidth) && compare(v[2][1], 47, bitwidth); } template bool check_3d(const T (&v)[4][3][2][N], int bitwidth) { return compare(v[0][0][0], 48, bitwidth) && compare(v[1][0][0], 49, bitwidth) && compare(v[2][0][0], 50, bitwidth) && compare(v[3][0][0], 51, bitwidth); } template bool check_1d1(const T (&v)[1][N], int bitwidth) { return compare(v[0], 52, bitwidth); } template bool check_2d1(const T (&v)[1][1][N], int bitwidth) { return compare(v[0][0], 53, bitwidth); } template bool check_3d1(const T (&v)[1][1][1][N], int bitwidth) { return compare(v[0][0][0], 54, bitwidth); } } // unnamed namespace void* get_non_null() { static int v; return &v; } void i_byte_0d(char* v) { set_0d(v); } void i_byte_1d(char* v) { set_1d(v); } void i_byte_2d(char* v) { set_2d(v); } void i_byte_3d(char* v) { set_3d(v); } void i_byte_1d1(char* v) { set_1d1(v); } void i_byte_2d1(char* v) { set_2d1(v); } void i_byte_3d1(char* v) { set_3d1(v); } void i_byte_unsigned_0d(unsigned char* v) { set_0d(v); } void i_byte_unsigned_1d(unsigned char* v) { set_1d(v); } void i_byte_unsigned_2d(unsigned char* v) { set_2d(v); } void i_byte_unsigned_3d(unsigned char* v) { set_3d(v); } void i_byte_unsigned_1d1(unsigned char* v) { set_1d1(v); } void i_byte_unsigned_2d1(unsigned char* v) { set_2d1(v); } void i_byte_unsigned_3d1(unsigned char* v) { set_3d1(v); } void i_shortint_0d(short* v) { set_0d(v); } void i_shortint_1d(short* v) { set_1d(v); } void i_shortint_2d(short* v) { set_2d(v); } void i_shortint_3d(short* v) { set_3d(v); } void i_shortint_1d1(short* v) { set_1d1(v); } void i_shortint_2d1(short* v) { set_2d1(v); } void i_shortint_3d1(short* v) { set_3d1(v); } void i_shortint_unsigned_0d(unsigned short* v) { set_0d(v); } void i_shortint_unsigned_1d(unsigned short* v) { set_1d(v); } void i_shortint_unsigned_2d(unsigned short* v) { set_2d(v); } void i_shortint_unsigned_3d(unsigned short* v) { set_3d(v); } void i_shortint_unsigned_1d1(unsigned short* v) { set_1d1(v); } void i_shortint_unsigned_2d1(unsigned short* v) { set_2d1(v); } void i_shortint_unsigned_3d1(unsigned short* v) { set_3d1(v); } void i_int_0d(int* v) { set_0d(v); } void i_int_1d(int* v) { set_1d(v); } void i_int_2d(int* v) { set_2d(v); } void i_int_3d(int* v) { set_3d(v); } void i_int_1d1(int* v) { set_1d1(v); } void i_int_2d1(int* v) { set_2d1(v); } void i_int_3d1(int* v) { set_3d1(v); } void i_int_unsigned_0d(unsigned int* v) { set_0d(v); } void i_int_unsigned_1d(unsigned int* v) { set_1d(v); } void i_int_unsigned_2d(unsigned int* v) { set_2d(v); } void i_int_unsigned_3d(unsigned int* v) { set_3d(v); } void i_int_unsigned_1d1(unsigned int* v) { set_1d1(v); } void i_int_unsigned_2d1(unsigned int* v) { set_2d1(v); } void i_int_unsigned_3d1(unsigned int* v) { set_3d1(v); } void i_longint_0d(sv_longint_t* v) { set_0d(v); } void i_longint_1d(sv_longint_t* v) { set_1d(v); } void i_longint_2d(sv_longint_t* v) { set_2d(v); } void i_longint_3d(sv_longint_t* v) { set_3d(v); } void i_longint_1d1(sv_longint_t* v) { set_1d1(v); } void i_longint_2d1(sv_longint_t* v) { set_2d1(v); } void i_longint_3d1(sv_longint_t* v) { set_3d1(v); } void i_longint_unsigned_0d(sv_longint_unsigned_t* v) { set_0d(v); } void i_longint_unsigned_1d(sv_longint_unsigned_t* v) { set_1d(v); } void i_longint_unsigned_2d(sv_longint_unsigned_t* v) { set_2d(v); } void i_longint_unsigned_3d(sv_longint_unsigned_t* v) { set_3d(v); } void i_longint_unsigned_1d1(sv_longint_unsigned_t* v) { set_1d1(v); } void i_longint_unsigned_2d1(sv_longint_unsigned_t* v) { set_2d1(v); } void i_longint_unsigned_3d1(sv_longint_unsigned_t* v) { set_3d1(v); } #ifndef NO_TIME void i_time_0d(svLogicVecVal* v) { set_0d(v, 64); } void i_time_1d(svLogicVecVal* v) { set_1d(v, 64); } void i_time_2d(svLogicVecVal* v) { set_2d(v, 64); } void i_time_3d(svLogicVecVal* v) { set_3d(v, 64); } void i_time_1d1(svLogicVecVal* v) { set_1d1(v, 64); } void i_time_2d1(svLogicVecVal* v) { set_2d1(v, 64); } void i_time_3d1(svLogicVecVal* v) { set_3d1(v, 64); } #endif #ifndef NO_INTEGER void i_integer_0d(svLogicVecVal* v) { set_0d(v, 32); } void i_integer_1d(svLogicVecVal* v) { set_1d(v, 32); } void i_integer_2d(svLogicVecVal* v) { set_2d(v, 32); } void i_integer_3d(svLogicVecVal* v) { set_3d(v, 32); } void i_integer_1d1(svLogicVecVal* v) { set_1d1(v, 32); } void i_integer_2d1(svLogicVecVal* v) { set_2d1(v, 32); } void i_integer_3d1(svLogicVecVal* v) { set_3d1(v, 32); } #endif void i_real_0d(double* v) { set_0d(v); } void i_real_1d(double* v) { set_1d(v); } void i_real_2d(double* v) { set_2d(v); } void i_real_3d(double* v) { set_3d(v); } void i_real_1d1(double* v) { set_1d1(v); } void i_real_2d1(double* v) { set_2d1(v); } void i_real_3d1(double* v) { set_3d1(v); } #ifndef NO_SHORTREAL void i_shortreal_0d(float* v) { set_0d(v); } void i_shortreal_1d(float* v) { set_1d(v); } void i_shortreal_2d(float* v) { set_2d(v); } void i_shortreal_3d(float* v) { set_3d(v); } void i_shortreal_1d1(float* v) { set_1d1(v); } void i_shortreal_2d1(float* v) { set_2d1(v); } void i_shortreal_3d1(float* v) { set_3d1(v); } #endif void i_chandle_0d(void** v) { v[0] = get_non_null(); } void i_chandle_1d(void** v) { v[0] = get_non_null(); v[1] = get_non_null(); } void i_chandle_2d(void** v) { v[2 * 0 + 1] = get_non_null(); v[2 * 1 + 1] = get_non_null(); v[2 * 2 + 1] = get_non_null(); } void i_chandle_3d(void** v) { v[(0 * 3 + 0) * 2 + 0] = get_non_null(); v[(1 * 3 + 0) * 2 + 0] = get_non_null(); v[(2 * 3 + 0) * 2 + 0] = get_non_null(); v[(3 * 3 + 0) * 2 + 0] = get_non_null(); } void i_chandle_1d1(void** v) { v[0] = get_non_null(); } void i_chandle_2d1(void** v) { v[0] = get_non_null(); } void i_chandle_3d1(void** v) { v[0] = get_non_null(); } void i_string_0d(const char** v) { static const char s[] = "42"; v[0] = s; } void i_string_1d(const char** v) { static const char s0[] = "43"; static const char s1[] = "44"; v[0] = s0; v[1] = s1; } void i_string_2d(const char** v) { static const char empty[] = ""; static const char s0[] = "45"; static const char s1[] = "46"; static const char s2[] = "47"; for (int i = 0; i < 3 * 2; ++i) v[i] = empty; v[2 * 0 + 1] = s0; v[2 * 1 + 1] = s1; v[2 * 2 + 1] = s2; } void i_string_3d(const char** v) { static const char empty[] = ""; static const char s0[] = "48"; static const char s1[] = "49"; static const char s2[] = "50"; static const char s3[] = "51"; for (int i = 0; i < 4 * 3 * 2; ++i) v[i] = empty; v[(0 * 3 + 0) * 2 + 0] = s0; v[(1 * 3 + 0) * 2 + 0] = s1; v[(2 * 3 + 0) * 2 + 0] = s2; v[(3 * 3 + 0) * 2 + 0] = s3; } void i_string_1d1(const char** v) { v[0] = "52"; } void i_string_2d1(const char** v) { v[0] = "53"; } void i_string_3d1(const char** v) { v[0] = "54"; } void i_bit1_0d(svBit* v) { set_0d_scalar(v); } void i_bit1_1d(svBit* v) { set_1d_scalar(v); } void i_bit1_2d(svBit* v) { set_2d_scalar(v); } void i_bit1_3d(svBit* v) { set_3d_scalar(v); } void i_bit1_1d1(svBit* v) { set_1d1_scalar(v); } void i_bit1_2d1(svBit* v) { set_2d1_scalar(v); } void i_bit1_3d1(svBit* v) { set_3d1_scalar(v); } void i_bit7_0d(svBitVecVal* v) { set_0d(v, 7); } void i_bit7_1d(svBitVecVal* v) { set_1d(v, 7); } void i_bit7_2d(svBitVecVal* v) { set_2d(v, 7); } void i_bit7_3d(svBitVecVal* v) { set_3d(v, 7); } void i_bit7_1d1(svBitVecVal* v) { set_1d1(v, 7); } void i_bit7_2d1(svBitVecVal* v) { set_2d1(v, 7); } void i_bit7_3d1(svBitVecVal* v) { set_3d1(v, 7); } void i_bit121_0d(svBitVecVal* v) { set_0d(v, 121); } void i_bit121_1d(svBitVecVal* v) { set_1d(v, 121); } void i_bit121_2d(svBitVecVal* v) { set_2d(v, 121); } void i_bit121_3d(svBitVecVal* v) { set_3d(v, 121); } void i_bit121_1d1(svBitVecVal* v) { set_1d1(v, 121); } void i_bit121_2d1(svBitVecVal* v) { set_2d1(v, 121); } void i_bit121_3d1(svBitVecVal* v) { set_3d1(v, 121); } void i_logic1_0d(svLogic* v) { set_0d_scalar(v); } void i_logic1_1d(svLogic* v) { set_1d_scalar(v); } void i_logic1_2d(svLogic* v) { set_2d_scalar(v); } void i_logic1_3d(svLogic* v) { set_3d_scalar(v); } void i_logic1_1d1(svLogic* v) { set_1d1_scalar(v); } void i_logic1_2d1(svLogic* v) { set_2d1_scalar(v); } void i_logic1_3d1(svLogic* v) { set_3d1_scalar(v); } void i_logic7_0d(svLogicVecVal* v) { set_0d(v, 7); } void i_logic7_1d(svLogicVecVal* v) { set_1d(v, 7); } void i_logic7_2d(svLogicVecVal* v) { set_2d(v, 7); } void i_logic7_3d(svLogicVecVal* v) { set_3d(v, 7); } void i_logic7_1d1(svLogicVecVal* v) { set_1d1(v, 7); } void i_logic7_2d1(svLogicVecVal* v) { set_2d1(v, 7); } void i_logic7_3d1(svLogicVecVal* v) { set_3d1(v, 7); } void i_logic121_0d(svLogicVecVal* v) { set_0d(v, 121); } void i_logic121_1d(svLogicVecVal* v) { set_1d(v, 121); } void i_logic121_2d(svLogicVecVal* v) { set_2d(v, 121); } void i_logic121_3d(svLogicVecVal* v) { set_3d(v, 121); } void i_logic121_1d1(svLogicVecVal* v) { set_1d1(v, 121); } void i_logic121_2d1(svLogicVecVal* v) { set_2d1(v, 121); } void i_logic121_3d1(svLogicVecVal* v) { set_3d1(v, 121); } void i_pack_struct_0d(svLogicVecVal* v) { set_0d(v, 7); } void i_pack_struct_1d(svLogicVecVal* v) { set_1d(v, 7); } void i_pack_struct_2d(svLogicVecVal* v) { set_2d(v, 7); } void i_pack_struct_3d(svLogicVecVal* v) { set_3d(v, 7); } void i_pack_struct_1d1(svLogicVecVal* v) { set_1d1(v, 7); } void i_pack_struct_2d1(svLogicVecVal* v) { set_2d1(v, 7); } void i_pack_struct_3d1(svLogicVecVal* v) { set_3d1(v, 7); } #ifndef NO_UNPACK_STRUCT void i_unpack_struct_0d(unpack_struct_t* v) { set_uint(v->val, 42, 121); } void i_unpack_struct_1d(unpack_struct_t* v) { set_uint(v[0].val, 43, 121); set_uint(v[1].val, 44, 121); } void i_unpack_struct_2d(unpack_struct_t* v) { set_uint(v[0 * 2 + 1].val, 45, 121); set_uint(v[1 * 2 + 1].val, 46, 121); set_uint(v[2 * 2 + 1].val, 47, 121); } void i_unpack_struct_3d(unpack_struct_t* v) { set_uint(v[(0 * 3 + 0) * 2 + 0].val, 48, 121); set_uint(v[(1 * 3 + 0) * 2 + 0].val, 49, 121); set_uint(v[(2 * 3 + 0) * 2 + 0].val, 50, 121); set_uint(v[(3 * 3 + 0) * 2 + 0].val, 51, 121); } void i_unpack_struct_1d1(unpack_struct_t* v) { set_uint(v[0].val, 52, 121); } void i_unpack_struct_2d1(unpack_struct_t* v) { set_uint(v[0].val, 53, 121); } void i_unpack_struct_3d1(unpack_struct_t* v) { set_uint(v[0].val, 54, 121); } #endif void check_exports() { { char byte_array[4][3][2]; e_byte_0d(&byte_array[3][2][1]); if (!check_0d(byte_array[3][2][1])) stop(); e_byte_1d(&byte_array[2][1][0]); if (!check_1d(byte_array[2][1])) stop(); e_byte_2d(&byte_array[1][0][0]); if (!check_2d(byte_array[1])) stop(); e_byte_3d(&byte_array[0][0][0]); if (!check_3d(byte_array)) stop(); } { char array[1][1][1]; e_byte_1d1(&array[0][0][0]); if (!check_1d1(array[0][0])) stop(); e_byte_2d1(&array[0][0][0]); if (!check_2d1(array[0])) stop(); e_byte_3d1(&array[0][0][0]); if (!check_3d1(array)) stop(); } { unsigned char byte_unsigned_array[4][3][2]; e_byte_unsigned_0d(&byte_unsigned_array[3][2][1]); if (!check_0d(byte_unsigned_array[3][2][1])) stop(); e_byte_unsigned_1d(&byte_unsigned_array[2][1][0]); if (!check_1d(byte_unsigned_array[2][1])) stop(); e_byte_unsigned_2d(&byte_unsigned_array[1][0][0]); if (!check_2d(byte_unsigned_array[1])) stop(); e_byte_unsigned_3d(&byte_unsigned_array[0][0][0]); if (!check_3d(byte_unsigned_array)) stop(); } { unsigned char array[1][1][1]; e_byte_unsigned_1d1(&array[0][0][0]); if (!check_1d1(array[0][0])) stop(); e_byte_unsigned_2d1(&array[0][0][0]); if (!check_2d1(array[0])) stop(); e_byte_unsigned_3d1(&array[0][0][0]); if (!check_3d1(array)) stop(); } { short shortint_array[4][3][2]; e_shortint_0d(&shortint_array[3][2][1]); if (!check_0d(shortint_array[3][2][1])) stop(); e_shortint_1d(&shortint_array[2][1][0]); if (!check_1d(shortint_array[2][1])) stop(); e_shortint_2d(&shortint_array[1][0][0]); if (!check_2d(shortint_array[1])) stop(); e_shortint_3d(&shortint_array[0][0][0]); if (!check_3d(shortint_array)) stop(); } { short array[1][1][1]; e_shortint_1d1(&array[0][0][0]); if (!check_1d1(array[0][0])) stop(); e_shortint_2d1(&array[0][0][0]); if (!check_2d1(array[0])) stop(); e_shortint_3d1(&array[0][0][0]); if (!check_3d1(array)) stop(); } { unsigned short shortint_unsigned_array[4][3][2]; e_shortint_unsigned_0d(&shortint_unsigned_array[3][2][1]); if (!check_0d(shortint_unsigned_array[3][2][1])) stop(); e_shortint_unsigned_1d(&shortint_unsigned_array[2][1][0]); if (!check_1d(shortint_unsigned_array[2][1])) stop(); e_shortint_unsigned_2d(&shortint_unsigned_array[1][0][0]); if (!check_2d(shortint_unsigned_array[1])) stop(); e_shortint_unsigned_3d(&shortint_unsigned_array[0][0][0]); if (!check_3d(shortint_unsigned_array)) stop(); } { unsigned short array[1][1][1]; e_shortint_unsigned_1d1(&array[0][0][0]); if (!check_1d1(array[0][0])) stop(); e_shortint_unsigned_2d1(&array[0][0][0]); if (!check_2d1(array[0])) stop(); e_shortint_unsigned_3d1(&array[0][0][0]); if (!check_3d1(array)) stop(); } { int int_array[4][3][2]; e_int_0d(&int_array[3][2][1]); if (!check_0d(int_array[3][2][1])) stop(); e_int_1d(&int_array[2][1][0]); if (!check_1d(int_array[2][1])) stop(); e_int_2d(&int_array[1][0][0]); if (!check_2d(int_array[1])) stop(); e_int_3d(&int_array[0][0][0]); if (!check_3d(int_array)) stop(); } { int array[1][1][1]; e_int_1d1(&array[0][0][0]); if (!check_1d1(array[0][0])) stop(); e_int_2d1(&array[0][0][0]); if (!check_2d1(array[0])) stop(); e_int_3d1(&array[0][0][0]); if (!check_3d1(array)) stop(); } { unsigned int int_unsigned_array[4][3][2]; e_int_unsigned_0d(&int_unsigned_array[3][2][1]); if (!check_0d(int_unsigned_array[3][2][1])) stop(); e_int_unsigned_1d(&int_unsigned_array[2][1][0]); if (!check_1d(int_unsigned_array[2][1])) stop(); e_int_unsigned_2d(&int_unsigned_array[1][0][0]); if (!check_2d(int_unsigned_array[1])) stop(); e_int_unsigned_3d(&int_unsigned_array[0][0][0]); if (!check_3d(int_unsigned_array)) stop(); } { unsigned int array[1][1][1]; e_int_unsigned_1d1(&array[0][0][0]); if (!check_1d1(array[0][0])) stop(); e_int_unsigned_2d1(&array[0][0][0]); if (!check_2d1(array[0])) stop(); e_int_unsigned_3d1(&array[0][0][0]); if (!check_3d1(array)) stop(); } { sv_longint_t longint_array[4][3][2]; e_longint_0d(&longint_array[3][2][1]); if (!check_0d(longint_array[3][2][1])) stop(); e_longint_1d(&longint_array[2][1][0]); if (!check_1d(longint_array[2][1])) stop(); e_longint_2d(&longint_array[1][0][0]); if (!check_2d(longint_array[1])) stop(); e_longint_3d(&longint_array[0][0][0]); if (!check_3d(longint_array)) stop(); } { sv_longint_t array[1][1][1]; e_longint_1d1(&array[0][0][0]); if (!check_1d1(array[0][0])) stop(); e_longint_2d1(&array[0][0][0]); if (!check_2d1(array[0])) stop(); e_longint_3d1(&array[0][0][0]); if (!check_3d1(array)) stop(); } { sv_longint_unsigned_t longint_unsigned_array[4][3][2]; e_longint_unsigned_0d(&longint_unsigned_array[3][2][1]); if (!check_0d(longint_unsigned_array[3][2][1])) stop(); e_longint_unsigned_1d(&longint_unsigned_array[2][1][0]); if (!check_1d(longint_unsigned_array[2][1])) stop(); e_longint_unsigned_2d(&longint_unsigned_array[1][0][0]); if (!check_2d(longint_unsigned_array[1])) stop(); e_longint_unsigned_3d(&longint_unsigned_array[0][0][0]); if (!check_3d(longint_unsigned_array)) stop(); } { sv_longint_unsigned_t array[1][1][1]; e_longint_unsigned_1d1(&array[0][0][0]); if (!check_1d1(array[0][0])) stop(); e_longint_unsigned_2d1(&array[0][0][0]); if (!check_2d1(array[0])) stop(); e_longint_unsigned_3d1(&array[0][0][0]); if (!check_3d1(array)) stop(); } #ifndef NO_TIME { svLogicVecVal time_array[4][3][2][2]; e_time_0d(time_array[3][2][1]); if (!check_0d(time_array[3][2][1], 64)) stop(); e_time_1d(time_array[2][1][0]); if (!check_1d(time_array[2][1], 64)) stop(); e_time_2d(time_array[1][0][0]); if (!check_2d(time_array[1], 64)) stop(); e_time_3d(time_array[0][0][0]); if (!check_3d(time_array, 64)) stop(); } { svLogicVecVal array[1][1][1][2]; e_time_1d1(array[0][0][0]); if (!check_1d1(array[0][0], 64)) stop(); e_time_2d1(array[0][0][0]); if (!check_2d1(array[0], 64)) stop(); e_time_3d1(array[0][0][0]); if (!check_3d1(array, 64)) stop(); } #endif #ifndef NO_INTEGER { svLogicVecVal integer_array[4][3][2][1]; e_integer_0d(integer_array[3][2][1]); if (!check_0d(integer_array[3][2][1], 32)) stop(); e_integer_1d(integer_array[2][1][0]); if (!check_1d(integer_array[2][1], 32)) stop(); e_integer_2d(integer_array[1][0][0]); if (!check_2d(integer_array[1], 32)) stop(); e_integer_3d(integer_array[0][0][0]); if (!check_3d(integer_array, 32)) stop(); } { svLogicVecVal array[1][1][1][1]; e_integer_1d1(array[0][0][0]); if (!check_1d1(array[0][0], 32)) stop(); e_integer_2d1(array[0][0][0]); if (!check_2d1(array[0], 32)) stop(); e_integer_3d1(array[0][0][0]); if (!check_3d1(array, 32)) stop(); } #endif { double real_array[4][3][2]; e_real_0d(&real_array[3][2][1]); if (!check_0d(real_array[3][2][1])) stop(); e_real_1d(&real_array[2][1][0]); if (!check_1d(real_array[2][1])) stop(); e_real_2d(&real_array[1][0][0]); if (!check_2d(real_array[1])) stop(); e_real_3d(&real_array[0][0][0]); if (!check_3d(real_array)) stop(); } { double array[1][1][1]; e_real_1d1(&array[0][0][0]); if (!check_1d1(array[0][0])) stop(); e_real_2d1(&array[0][0][0]); if (!check_2d1(array[0])) stop(); e_real_3d1(&array[0][0][0]); if (!check_3d1(array)) stop(); } #ifndef NO_SHORTREAL { float shortreal_array[4][3][2]; e_shortreal_0d(&shortreal_array[3][2][1]); if (!check_0d(shortreal_array[3][2][1])) stop(); e_shortreal_1d(&shortreal_array[2][1][0]); if (!check_1d(shortreal_array[2][1])) stop(); e_shortreal_2d(&shortreal_array[1][0][0]); if (!check_2d(shortreal_array[1])) stop(); e_shortreal_3d(&shortreal_array[0][0][0]); if (!check_3d(shortreal_array)) stop(); } { float array[1][1][1]; e_shortreal_1d1(&array[0][0][0]); if (!check_1d1(array[0][0])) stop(); e_shortreal_2d1(&array[0][0][0]); if (!check_2d1(array[0])) stop(); e_shortreal_3d1(&array[0][0][0]); if (!check_3d1(array)) stop(); } #endif { void* chandle_array[4][3][2]; for (int i = 0; i < 4; ++i) for (int j = 0; j < 3; ++j) for (int k = 0; k < 2; ++k) chandle_array[i][j][k] = NULL; e_chandle_0d(&chandle_array[3][2][1]); if (!chandle_array[3][2][1]) stop(); e_chandle_1d(&chandle_array[2][1][0]); if (!chandle_array[2][1][0]) stop(); if (!chandle_array[2][1][1]) stop(); e_chandle_2d(&chandle_array[1][0][0]); if (!chandle_array[1][0][1]) stop(); if (!chandle_array[1][1][1]) stop(); if (!chandle_array[1][2][1]) stop(); e_chandle_3d(&chandle_array[0][0][0]); if (!chandle_array[0][0][0]) stop(); if (!chandle_array[1][0][0]) stop(); if (!chandle_array[2][0][0]) stop(); if (!chandle_array[3][0][0]) stop(); } { void* chandle_array[1][1][1]; e_chandle_1d1(&chandle_array[0][0][0]); if (!chandle_array[0][0][0]) stop(); e_chandle_2d1(&chandle_array[0][0][0]); if (!chandle_array[0][0][0]) stop(); e_chandle_3d1(&chandle_array[0][0][0]); if (!chandle_array[0][0][0]) stop(); } { const char* string_array[4][3][2]; for (int i = 0; i < 4; ++i) for (int j = 0; j < 3; ++j) for (int k = 0; k < 2; ++k) string_array[i][j][k] = NULL; e_string_0d(&string_array[3][2][1]); if (!compare(string_array[3][2][1], "42")) stop(); e_string_1d(&string_array[2][1][0]); if (!compare(string_array[2][1][0], "43")) stop(); if (!compare(string_array[2][1][1], "44")) stop(); e_string_2d(&string_array[1][0][0]); if (!compare(string_array[1][0][1], "45")) stop(); if (!compare(string_array[1][1][1], "46")) stop(); if (!compare(string_array[1][2][1], "47")) stop(); e_string_3d(&string_array[0][0][0]); if (!compare(string_array[0][0][0], "48")) stop(); if (!compare(string_array[1][0][0], "49")) stop(); if (!compare(string_array[2][0][0], "50")) stop(); if (!compare(string_array[3][0][0], "51")) stop(); } { const char* string_array[1][1][1]; e_string_1d1(&string_array[0][0][0]); if (!compare(string_array[0][0][0], "52")) stop(); e_string_2d1(&string_array[0][0][0]); if (!compare(string_array[0][0][0], "53")) stop(); e_string_3d1(&string_array[0][0][0]); if (!compare(string_array[0][0][0], "54")) stop(); } { svBitVecVal bit7_array[4][3][2][1]; e_bit7_0d(bit7_array[3][2][1]); if (!check_0d(bit7_array[3][2][1], 7)) stop(); e_bit7_1d(bit7_array[2][1][0]); if (!check_1d(bit7_array[2][1], 7)) stop(); e_bit7_2d(bit7_array[1][0][0]); if (!check_2d(bit7_array[1], 7)) stop(); e_bit7_3d(bit7_array[0][0][0]); if (!check_3d(bit7_array, 7)) stop(); } { svBitVecVal bit121_array[4][3][2][4]; e_bit121_0d(bit121_array[3][2][1]); if (!check_0d(bit121_array[3][2][1], 121)) stop(); e_bit121_1d(bit121_array[2][1][0]); if (!check_1d(bit121_array[2][1], 121)) stop(); e_bit121_2d(bit121_array[1][0][0]); if (!check_2d(bit121_array[1], 121)) stop(); e_bit121_3d(bit121_array[0][0][0]); if (!check_3d(bit121_array, 121)) stop(); } { svLogicVecVal logic7_array[4][3][2][1]; e_logic7_0d(logic7_array[3][2][1]); if (!check_0d(logic7_array[3][2][1], 7)) stop(); e_logic7_1d(logic7_array[2][1][0]); if (!check_1d(logic7_array[2][1], 7)) stop(); e_logic7_2d(logic7_array[1][0][0]); if (!check_2d(logic7_array[1], 7)) stop(); e_logic7_3d(logic7_array[0][0][0]); if (!check_3d(logic7_array, 7)) stop(); } { svLogicVecVal array[1][1][1][1]; e_logic7_1d1(array[0][0][0]); if (!check_1d1(array[0][0], 7)) stop(); e_logic7_2d1(array[0][0][0]); if (!check_2d1(array[0], 7)) stop(); e_logic7_3d1(array[0][0][0]); if (!check_3d1(array, 7)) stop(); } { svLogicVecVal logic121_array[4][3][2][4]; e_logic121_0d(logic121_array[3][2][1]); if (!check_0d(logic121_array[3][2][1], 121)) stop(); e_logic121_1d(logic121_array[2][1][0]); if (!check_1d(logic121_array[2][1], 121)) stop(); e_logic121_2d(logic121_array[1][0][0]); if (!check_2d(logic121_array[1], 121)) stop(); e_logic121_3d(logic121_array[0][0][0]); if (!check_3d(logic121_array, 121)) stop(); } { svLogicVecVal array[1][1][1][4]; e_logic121_1d1(array[0][0][0]); if (!check_1d1(array[0][0], 121)) stop(); e_logic121_2d1(array[0][0][0]); if (!check_2d1(array[0], 121)) stop(); e_logic121_3d1(array[0][0][0]); if (!check_3d1(array, 121)) stop(); } { svLogicVecVal pack_struct_array[4][3][2][1]; e_pack_struct_0d(pack_struct_array[3][2][1]); if (!check_0d(pack_struct_array[3][2][1], 7)) stop(); e_pack_struct_1d(pack_struct_array[2][1][0]); if (!check_1d(pack_struct_array[2][1], 7)) stop(); e_pack_struct_2d(pack_struct_array[1][0][0]); if (!check_2d(pack_struct_array[1], 7)) stop(); e_pack_struct_3d(pack_struct_array[0][0][0]); if (!check_3d(pack_struct_array, 7)) stop(); } { svLogicVecVal array[1][1][1][1]; e_pack_struct_1d1(array[0][0][0]); if (!check_1d1(array[0][0], 7)) stop(); e_pack_struct_2d1(array[0][0][0]); if (!check_2d1(array[0], 7)) stop(); e_pack_struct_3d1(array[0][0][0]); if (!check_3d1(array, 7)) stop(); } #ifndef NO_UNPACK_STRUCT { unpack_struct_t unpack_struct_array[4][3][2]; e_unpack_struct_0d(&unpack_struct_array[3][2][1]); if (!compare(unpack_struct_array[3][2][1].val, 42, 121)) stop(); e_unpack_struct_1d(&unpack_struct_array[2][1][0]); if (!compare(unpack_struct_array[2][1][0].val, 43, 121)) stop(); if (!compare(unpack_struct_array[2][1][1].val, 44, 121)) stop(); e_unpack_struct_2d(&unpack_struct_array[1][0][0]); if (!compare(unpack_struct_array[1][0][1].val, 45, 121)) stop(); if (!compare(unpack_struct_array[1][1][1].val, 46, 121)) stop(); if (!compare(unpack_struct_array[1][2][1].val, 47, 121)) stop(); e_unpack_struct_3d(&unpack_struct_array[0][0][0]); if (!compare(unpack_struct_array[0][0][0].val, 48, 121)) stop(); if (!compare(unpack_struct_array[1][0][0].val, 49, 121)) stop(); if (!compare(unpack_struct_array[2][0][0].val, 50, 121)) stop(); if (!compare(unpack_struct_array[3][0][0].val, 51, 121)) stop(); } { unpack_struct_t unpack_struct_array[1][1][1]; e_unpack_struct_1d1(&unpack_struct_array[0][0][0]); if (!compare(unpack_struct_array[0][0][0].val, 52, 121)) stop(); e_unpack_struct_2d1(&unpack_struct_array[0][0][0]); if (!compare(unpack_struct_array[0][0][0].val, 53, 121)) stop(); e_unpack_struct_3d1(&unpack_struct_array[0][0][0]); if (!compare(unpack_struct_array[0][0][0].val, 54, 121)) stop(); } #endif } verilator-5.042/test_regress/t/t_select_mul_extend.v0000644000542200017500000000533515101701376023311 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Varun Koyyalagunta. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [31:0] out; // From test of Test.v // End of automatics Test test(/*AUTOINST*/ // Outputs .out (out[31:0]), // Inputs .clk (clk), .in (in[31:0])); Test2 test2(/*AUTOINST*/ // Inputs .clk (clk)); // Aggregate outputs into a single result vector wire [63:0] result = {32'h0, out}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x sum=%x\n", $time, cyc, crc, result, sum); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc == 0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc < 10) begin sum <= '0; end else if (cyc < 90) begin end else if (cyc == 99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h4afe43fb79d7b71e if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test(/*AUTOARG*/ // Outputs out, // Inputs clk, in ); input clk; input [31:0] in; output reg [31:0] out; logic [31:0] cnt = 0; logic [7:0][30:0] q; logic cond = 0; always_comb begin for (int i = 0; i < 8; i++) begin if (i == (cond ? (2-cnt)%8 : 0)) begin q[i] = 31'(in); end else begin q[i] = '0; end end end always @(posedge clk) begin cnt <= cnt + 1; cond <= ~cond; out <= {in[31], q[cond ? (3'd2 - cnt[2:0]) : 3'd0]}; end endmodule module Test2(input wire clk); reg [127:1][7:0] arrayu; reg [6:0] index = 0; wire logic [7:0] selectedu = arrayu[index]; always @(posedge clk) begin index <= index + 1; if (index == 2) $display(selectedu); end endmodule verilator-5.042/test_regress/t/t_vpi_const_type.cpp0000644000542200017500000001414615101701376023170 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #ifdef IS_VPI #include "sv_vpi_user.h" #include #else #include "verilated.h" #include "verilated_vcd_c.h" #include "verilated_vpi.h" #include "Vt_vpi_const_type.h" #include "Vt_vpi_const_type__Dpi.h" #include "svdpi.h" #endif #include #include #include extern "C" { #include } // These require the above. Comment prevents clang-format moving them #include "TestSimulator.h" #include "TestVpi.h" extern "C" { int mon_check() { #ifdef TEST_VERBOSE printf("-mon_check()\n"); #endif TestVpiHandle intHandle = vpi_handle_by_name((PLI_BYTE8*)"t.intParam", NULL); CHECK_RESULT_NZ(intHandle) PLI_INT32 intConstType = vpi_get(vpiConstType, intHandle); CHECK_RESULT(intConstType, vpiDecConst) const char* intConstTypeStr = vpi_get_str(vpiConstType, intHandle); CHECK_RESULT_CSTR(intConstTypeStr, "vpiDecConst") TestVpiHandle realHandle = vpi_handle_by_name((PLI_BYTE8*)"t.realParam", NULL); CHECK_RESULT_NZ(realHandle) PLI_INT32 realConstType = vpi_get(vpiConstType, realHandle); CHECK_RESULT(realConstType, vpiRealConst) const char* realConstTypeStr = vpi_get_str(vpiConstType, realHandle); CHECK_RESULT_CSTR(realConstTypeStr, "vpiRealConst") TestVpiHandle strHandle = vpi_handle_by_name((PLI_BYTE8*)"t.strParam", NULL); CHECK_RESULT_NZ(strHandle) PLI_INT32 strConstType = vpi_get(vpiConstType, strHandle); CHECK_RESULT(strConstType, vpiStringConst) const char* strConstTypeStr = vpi_get_str(vpiConstType, strHandle); CHECK_RESULT_CSTR(strConstTypeStr, "vpiStringConst") // t.signal_rd is not constant, and should error on a write TestVpiHandle sigHandle = vpi_handle_by_name((PLI_BYTE8*)"t.signal_rd", NULL); CHECK_RESULT_NZ(sigHandle) PLI_INT32 sigConstType = vpi_get(vpiConstType, sigHandle); CHECK_RESULT(sigConstType, vpiUndefined) const char* sigConstTypeStr = vpi_get_str(vpiConstType, sigHandle); CHECK_RESULT_CSTR(sigConstTypeStr, "*undefined*") // and should error on a write s_vpi_value vpi_value; vpi_value.format = vpiIntVal; vpi_value.value.integer = 1; vpi_put_value(sigHandle, &vpi_value, NULL, vpiNoDelay); CHECK_RESULT(vpi_chk_error(nullptr), vpiError); // and an intertial write vpi_put_value(sigHandle, &vpi_value, NULL, vpiInertialDelay); CHECK_RESULT(vpi_chk_error(nullptr), vpiError); // t.signal_rw is not constant sigHandle = vpi_handle_by_name((PLI_BYTE8*)"t.signal_rw", NULL); CHECK_RESULT_NZ(sigHandle) sigConstType = vpi_get(vpiConstType, sigHandle); CHECK_RESULT(sigConstType, vpiUndefined) sigConstTypeStr = vpi_get_str(vpiConstType, sigHandle); CHECK_RESULT_CSTR(sigConstTypeStr, "*undefined*") // left range of t.signal_rw TestVpiHandle leftHandle = vpi_handle(vpiLeftRange, sigHandle); CHECK_RESULT_NZ(leftHandle) PLI_INT32 leftConstType = vpi_get(vpiConstType, leftHandle); CHECK_RESULT(leftConstType, vpiDecConst) TestVpiHandle timeHandle = vpi_handle_by_name((PLI_BYTE8*)"t.timeParam", NULL); CHECK_RESULT_NZ(timeHandle) PLI_INT32 timeConstType = vpi_get(vpiConstType, timeHandle); CHECK_RESULT(timeConstType, vpiDecConst) return 0; // Ok } } //====================================================================== #ifdef IS_VPI static int mon_check_vpi() { TestVpiHandle href = vpi_handle(vpiSysTfCall, 0); s_vpi_value vpi_value; vpi_value.format = vpiIntVal; vpi_value.value.integer = mon_check(); vpi_put_value(href, &vpi_value, NULL, vpiNoDelay); return 0; } static s_vpi_systf_data vpi_systf_data[] = {{vpiSysFunc, vpiIntFunc, (PLI_BYTE8*)"$mon_check", (PLI_INT32(*)(PLI_BYTE8*))mon_check_vpi, 0, 0, 0}, 0}; // cver entry void vpi_compat_bootstrap(void) { p_vpi_systf_data systf_data_p; systf_data_p = &(vpi_systf_data[0]); while (systf_data_p->type != 0) vpi_register_systf(systf_data_p++); } // icarus entry void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0}; #else int main(int argc, char** argv) { const std::unique_ptr contextp{new VerilatedContext}; uint64_t sim_time = 1100; contextp->debug(0); contextp->commandArgs(argc, argv); // We're going to be checking for these errors so don't crash out contextp->fatalOnVpiError(0); { // Construct and destroy const std::unique_ptr topp{ new VM_PREFIX{contextp.get(), // Note null name - we're flattening it out ""}}; } // Test second construction const std::unique_ptr topp{new VM_PREFIX{contextp.get(), // Note null name - we're flattening it out ""}}; #ifdef VERILATOR #ifdef TEST_VERBOSE contextp->scopesDump(); #endif #endif #if VM_TRACE contextp->traceEverOn(true); VL_PRINTF("Enabling waves...\n"); VerilatedVcdC* tfp = new VerilatedVcdC; topp->trace(tfp, 99); tfp->open(STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); #endif topp->eval(); contextp->timeInc(10); while (contextp->time() < sim_time && !contextp->gotFinish()) { contextp->timeInc(1); topp->eval(); VerilatedVpi::callValueCbs(); // mon_do(); #if VM_TRACE if (tfp) tfp->dump(contextp->time()); #endif } if (!contextp->gotFinish()) { vl_fatal(FILENM, __LINE__, "main", "%Error: Timeout; never got a $finish"); } topp->final(); #if VM_TRACE if (tfp) tfp->close(); #endif return 0; } #endif verilator-5.042/test_regress/t/t_debug_emitv.v0000644000542200017500000002243015101701376022073 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Dotted reference that uses another dotted reference // as the select expression // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package Pkg; localparam PKG_PARAM = 1; typedef enum int { FOO = 0, BAR, BAZ } enum_t; endpackage package PkgImp; import Pkg::*; export Pkg::*; endpackage class Cls; int member = 1; function void method; if (this != this) $stop; endfunction endclass interface Iface ( input clk ); logic ifsig; modport mp(input ifsig); endinterface module t (/*AUTOARG*/ // Inputs clk, in ); input clk; input in; // verilator lint_off UNPACKED typedef enum [2:0] { ZERO, ONE = 1 } e_t; typedef struct packed { e_t a; } ps_t; typedef struct { logic signed [2:0] a; } us_t; typedef union { logic a; } union_t; const ps_t ps[3]; us_t us; union_t unu; integer i1; int array[3]; initial array = '{1,2,3}; logic [63:32] downto_32 = '0; function automatic int ident(int value); return value; endfunction Iface the_ifaces [3:0] (.*); initial begin if ($test$plusargs("HELLO")) $display("Hello argument found."); if (Pkg::FOO == 0) $write(""); if (ZERO == 0) $write(""); if ($value$plusargs("TEST=%d", i1)) $display("value was %d", i1); else $display("+TEST= not found"); if (downto_32[33]) $write(""); if (downto_32[ident(33)]) $write(""); if (|downto_32[48:40]) $write(""); if (|downto_32[55+:3]) $write(""); if (|downto_32[60-:7]) $write(""); if (the_ifaces[2].ifsig) $write(""); #1 $write("After #1 delay"); end bit [6:5][4:3][2:1] arraymanyd[10:11][12:13][14:15]; reg [15:0] pubflat /*verilator public_flat_rw @(posedge clk) */; reg [15:0] pubflat_r; wire [15:0] pubflat_w = pubflat; int fd; int i; int q[$]; int qb[$ : 3]; int assoc[string]; int assocassoc[string][real]; int dyn[]; typedef struct packed { logic nn1; } nested_named_t; typedef struct packed { struct packed { logic nn2; } nested_anonymous; nested_named_t nested_named; logic [11:10] nn3; } nibble_t; nibble_t [5:4] nibblearray[3:2]; task t; $display("stmt"); endtask function int f(input int v); $display("stmt"); return v == 0 ? 99 : ~v + 1; endfunction sub sub(.*); initial begin int other; begin //unnamed for (int i = 0; i < 3; ++i) begin other = f(i); $display("stmt %d %d", i, other); t(); end end begin : named $display("stmt"); end : named end final begin $display("stmt"); end always @ (in) begin $display("stmt"); end always @ (posedge clk) begin $display("posedge clk"); pubflat_r <= pubflat_w; end always @ (negedge clk) begin $display("negedge clk, pfr = %x", pubflat_r); end int cyc; int fo; int sum; real r; string str; int mod_val; int mod_res; always_ff @ (posedge clk) begin cyc <= cyc + 1; r <= r + 0.01; fo = cyc; sub.inc(fo, sum); sum = sub.f(sum); $display("[%0t] sum = %d", $time, sum); $display("a?= %d", $c(1) ? $c32(20) : $c32(30)); $c(";"); $display("%d", $c("0")); fd = $fopen("/dev/null"); $fclose(fd); fd = $fopen("/dev/null", "r"); $fgetc(fd); // stmt $fflush(fd); $fscanf(fd, "%d", sum); $fdisplay("i = ", sum); $fwrite(fd, "hello"); $readmemh(fd, array); $readmemh(fd, array, 0); $readmemh(fd, array, 0, 0); sum = 0; for (int i = 0; i < cyc; ++i) begin sum += i; if (sum > 10) break; else sum += 1; end if (cyc == 99) $finish; if (cyc == 100) $stop; case (in) // synopsys full_case parallel_case 1: $display("1"); default: $display("default"); endcase priority case (in) 1: $display("1"); default: $display("default"); endcase unique case (in) 1: $display("1"); default: $display("default"); endcase unique0 case (in) 1: $display("1"); default: $display("default"); endcase if (in) $display("1"); else $display("0"); priority if (in) $display("1"); else $display("0"); unique if (in) $display("1"); else $display("0"); unique0 if (in) $display("1"); else $display("0"); $display($past(cyc), $past(cyc, 1)); str = $sformatf("cyc=%d", cyc); $display("str = %s", str); $display("%% [%t] [%t] to=%o td=%d", $time, $realtime, $time, $time); $sscanf("foo=5", "foo=%d", i); $printtimescale; if (i != 5) $stop; sum = $random; sum = $random(10); sum = $urandom; sum = $urandom(10); if (Pkg::PKG_PARAM != 1) $stop; sub.r = 62.0; mod_res = mod_val % 5; $display("%g", $log10(r)); $display("%g", $ln(r)); $display("%g", $exp(r)); $display("%g", $sqrt(r)); $display("%g", $floor(r)); $display("%g", $ceil(r)); $display("%g", $sin(r)); $display("%g", $cos(r)); $display("%g", $tan(r)); $display("%g", $asin(r)); $display("%g", $acos(r)); $display("%g", $atan(r)); $display("%g", $sinh(r)); $display("%g", $cosh(r)); $display("%g", $tanh(r)); $display("%g", $asinh(r)); $display("%g", $acosh(r)); $display("%g", $atanh(r)); if ($sampled(cyc[1])) $write(""); if ($rose(cyc)) $write(""); if ($fell(cyc)) $write(""); if ($stable(cyc)) $write(""); if ($changed(cyc)) $write(""); if ($past(cyc[1])) $write(""); if ($rose(cyc, clk)) $write(""); if ($fell(cyc, clk)) $write(""); if ($stable(cyc, clk)) $write(""); if ($changed(cyc, clk)) $write(""); if ($past(cyc[1], 5)) $write(""); force sum = 10; repeat (2) if (sum != 10) $stop; release sum; end property p; @(posedge clk) ##1 sum[0] endproperty property p1; @(clk) sum[0] endproperty property p2; @(posedge clk) disable iff (cyc == 1) ##1 sum[0] endproperty assert property (@(clk) not ##1 in); initial begin assert_simple_immediate_else: assert(0) else $display("fail"); assert_simple_immediate_stmt: assert(0) $display("pass"); assert_simple_immediate_stmt_else: assert(0) $display("pass"); else $display("fail"); assume_simple_immediate: assume(0); assume_simple_immediate_else: assume(0) else $display("fail"); assume_simple_immediate_stmt: assume(0) $display("pass"); assume_simple_immediate_stmt_else: assume(0) $display("pass"); else $display("fail"); end assert_observed_deferred_immediate: assert #0 (0); assert_observed_deferred_immediate_else: assert #0 (0) else $display("fail"); assert_observed_deferred_immediate_stmt: assert #0 (0) $display("pass"); assert_observed_deferred_immediate_stmt_else: assert #0 (0) $display("pass"); else $display("fail"); assume_observed_deferred_immediate: assume #0 (0); assume_observed_deferred_immediate_else: assume #0 (0) else $display("fail"); assume_observed_deferred_immediate_stmt: assume #0 (0) $display("pass"); assume_observed_deferred_immediate_stmt_else: assume #0 (0) $display("pass"); else $display("fail"); assert_final_deferred_immediate: assert final (0); assert_final_deferred_immediate_else: assert final (0) else $display("fail"); assert_final_deferred_immediate_stmt: assert final (0) $display("pass"); assert_final_deferred_immediate_stmt_else: assert final (0) $display("pass"); else $display("fail"); assume_final_deferred_immediate: assume final (0); assume_final_deferred_immediate_else: assume final (0) else $display("fail"); assume_final_deferred_immediate_stmt: assume final (0) $display("pass"); assume_final_deferred_immediate_stmt_else: assume final (0) $display("pass"); else $display("fail"); property prop(); @(posedge clk) 0 endproperty assert_concurrent: assert property (prop); assert_concurrent_else: assert property(prop) else $display("fail"); assert_concurrent_stmt: assert property(prop) $display("pass"); assert_concurrent_stmt_else: assert property(prop) $display("pass"); else $display("fail"); assume_concurrent: assume property(prop); assume_concurrent_else: assume property(prop) else $display("fail"); assume_concurrent_stmt: assume property(prop) $display("pass"); assume_concurrent_stmt_else: assume property(prop) $display("pass"); else $display("fail"); cover_concurrent: cover property(prop); cover_concurrent_stmt: cover property(prop) $display("pass"); int a; int ao; // verilator lint_off CASTCONST initial begin : assert_intrinsic $cast(ao, a); end restrict property (@(posedge clk) ##1 a[0]); endmodule module sub(input logic clk); task inc(input int i, output int o); o = {1'b0, i[31:1]} + 32'd1; endtask function int f(input int v); if (v == 0) return 33; return {31'd0, v[2]} + 32'd1; endfunction real r; endmodule package p; logic pkgvar; endpackage verilator-5.042/test_regress/t/t_func_real_param.v0000644000542200017500000000117015101701376022715 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // bug475 module t(); function real get_real_one; input ignored; get_real_one = 1.1; endfunction localparam R_PARAM = get_real_one(1'b0); localparam R_PARAM_2 = (R_PARAM > 0); generate initial begin if (R_PARAM != 1.1) $stop; if (R_PARAM_2 != 1'b1) $stop; $write("*-* All Finished *-*\n"); $finish; end endgenerate endmodule verilator-5.042/test_regress/t/t_altera_lpm_bustri.py0000755000542200017500000000111115101701376023470 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) test.compile(verilator_flags2=["--top-module", module]) test.passes() verilator-5.042/test_regress/t/t_select_plus_mul_pow2.v0000644000542200017500000000270615101701376023753 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Conor McCullough. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [63:0] from = 64'h0706050403020100; reg [7:0] to; reg [2:0] bitn; reg [7:0] cyc; initial cyc = 0; always @* begin to = from[bitn * 8 +: 8]; end always @ (posedge clk) begin cyc <= cyc + 8'd1; case (cyc) 8'd00: begin bitn<=3'd0; end 8'd01: begin bitn<=3'd1; end 8'd02: begin bitn<=3'd2; end 8'd03: begin bitn<=3'd3; end 8'd04: begin bitn<=3'd4; end 8'd05: begin bitn<=3'd5; end 8'd06: begin bitn<=3'd6; end 8'd07: begin bitn<=3'd7; end 8'd08: begin $write("*-* All Finished *-*\n"); $finish; end default: ; endcase case (cyc) 8'd00: ; 8'd01: begin if (to !== 8'h00) $stop; end 8'd02: begin if (to !== 8'h01) $stop; end 8'd03: begin if (to !== 8'h02) $stop; end 8'd04: begin if (to !== 8'h03) $stop; end 8'd05: begin if (to !== 8'h04) $stop; end 8'd06: begin if (to !== 8'h05) $stop; end 8'd07: begin if (to !== 8'h06) $stop; end 8'd08: begin if (to !== 8'h07) $stop; end default: $stop; endcase end endmodule verilator-5.042/test_regress/t/t_dpi_vams.py0000755000542200017500000000106015101701376021565 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_var_types_bad.out0000644000542200017500000000412415101701376022765 0ustar mahmoudyfreeshell%Error: t/t_var_types_bad.v:39:13: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'bit' : ... note: In instance 't' 39 | d_bitz[0] = 1'b1; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_var_types_bad.v:40:15: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' : ... note: In instance 't' 40 | d_logicz[0] = 1'b1; | ^ %Error: t/t_var_types_bad.v:41:13: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' : ... note: In instance 't' 41 | d_regz[0] = 1'b1; | ^ %Error: t/t_var_types_bad.v:46:13: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'real' : ... note: In instance 't' 46 | d_real[0] = 1'b1; | ^ %Warning-REALCVT: t/t_var_types_bad.v:46:7: Implicit conversion of real to integer; expected integral input to SEL : ... note: In instance 't' 46 | d_real[0] = 1'b1; | ^~~~~~ ... For warning description see https://verilator.org/warn/REALCVT?v=latest ... Use "/* verilator lint_off REALCVT */" and lint_on around source to disable this message. %Error: t/t_var_types_bad.v:47:17: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'real' : ... note: In instance 't' 47 | d_realtime[0] = 1'b1; | ^ %Warning-REALCVT: t/t_var_types_bad.v:47:7: Implicit conversion of real to integer; expected integral input to SEL : ... note: In instance 't' 47 | d_realtime[0] = 1'b1; | ^~~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_lint_edge_real_bad.out0000644000542200017500000000116315101701376023706 0ustar mahmoudyfreeshell%Error: t/t_lint_edge_real_bad.v:19:22: Edge event control not legal on real type (IEEE 1800-2023 6.12.1) : ... note: In instance 't' 19 | always @ (posedge rbad) $stop; | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_lint_edge_real_bad.v:20:22: Edge event control not legal on non-integral type (IEEE 1800-2023 9.4.2) : ... note: In instance 't' 20 | always @ (posedge ebad) $stop; | ^~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_unpacked_wide_unknown.v0000644000542200017500000000166215101701376024166 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef struct packed { logic [149:0] hdr; logic [1:0] vc; } packet_t; module t; logic clk; typedef struct {packet_t [1:0] pkt_i;} dut_if_t; dut_if_t dut[2]; initial begin clk = 0; forever #(0.5) clk = ~clk; end task automatic send_req_packets(int module_id, int channel); packet_t packet = '0; dut[module_id].pkt_i[channel] = packet; @(posedge clk); // If you comment out this line. It will build. endtask initial begin for (int m = 0; m < 2; m++) begin for (int i = 0; i < 2; i++) begin automatic int mod = m; automatic int ch = i; send_req_packets(mod, ch); end end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_opt_expand_keep_widths.out0000644000542200017500000000041115101701376024665 0ustar mahmoudyfreeshell[0] in5=0 clock_10=0 clock_12=0 out18=1 [5] in5=0 clock_10=0 clock_12=1 out18=1 [10] in5=0 clock_10=0 clock_12=0 out18=1 [15] in5=0 clock_10=1 clock_12=0 out18=1 [15] in5=0 clock_10=1 clock_12=0 out18=0 [20] in5=0 clock_10=0 clock_12=0 out18=0 *-* All Finished *-* verilator-5.042/test_regress/t/t_clk_2in_vec.py0000755000542200017500000000130515101701376022143 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_clk_2in.cpp" test.top_filename = "t/t_clk_2in.v" test.compile(make_top_shell=False, make_main=False, v_flags2=["+define+T_CLK_2IN_VEC=1"], verilator_flags2=["--exe", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_display_mcd.out0000644000542200017500000000005115101701376022426 0ustar mahmoudyfreeshellTo stdout To stderr *-* All Finished *-* verilator-5.042/test_regress/t/t_trace_no_top_name2_vcd.out0000644000542200017500000000200115101701376024525 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module $rootio $end $var wire 1 # clk $end $upscope $end $scope module foo_pkg $end $var wire 32 & foo_func__Vstatic__b_current [31:0] $end $upscope $end $scope module t $end $var wire 1 # clk $end $var wire 32 $ cyc [31:0] $end $scope module sub $end $var wire 32 % a [31:0] $end $upscope $end $upscope $end $enddefinitions $end #0 0# b00000000000000000000000000000000 $ b00000000000000000000010010111100 % b00000000000000000000000000000000 & #1 1# b00000000000000000000000000000001 $ #2 0# #3 1# b00000000000000000000000000000010 $ #4 0# #5 1# b00000000000000000000000000000011 $ #6 0# #7 1# b00000000000000000000000000000100 $ #8 0# #9 1# b00000000000000000000000000000101 $ #10 0# #11 1# b00000000000000000000000000000110 $ #12 0# #13 1# b00000000000000000000000000000111 $ #14 0# #15 1# b00000000000000000000000000001000 $ #16 0# #17 1# b00000000000000000000000000001001 $ #18 0# #19 1# b00000000000000000000000000001010 $ #20 0# verilator-5.042/test_regress/t/t_vpi_put_value_array.v0000644000542200017500000000377115101701376023670 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2024 by Diego Roux. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VERILATOR_COMMENTS `define PUBLIC_FLAT_RD /*verilator public_flat_rd*/ `define PUBLIC_FLAT_RW /*verilator public_flat_rw*/ `else `define PUBLIC_FLAT_RD `define PUBLIC_FLAT_RW `endif module test (); `ifdef VERILATOR `systemc_header extern "C" int mon_check(); `verilog `endif reg [7:0] write_bytes [0:3] `PUBLIC_FLAT_RW; reg [7:0] write_bytes_rl [3:0] `PUBLIC_FLAT_RW; reg [7:0] write_bytes_nonzero_index [1:4] `PUBLIC_FLAT_RW; reg [15:0] write_shorts [0:3] `PUBLIC_FLAT_RW; reg [31:0] write_words [0:3] `PUBLIC_FLAT_RW; reg [63:0] write_longs [0:3] `PUBLIC_FLAT_RW; reg [68:0] write_customs [0:3] `PUBLIC_FLAT_RW; reg [68:0] write_customs_nonzero_index_rl [4:1] `PUBLIC_FLAT_RW; integer write_integers [0:3] `PUBLIC_FLAT_RW; reg [7:0] write_scalar `PUBLIC_FLAT_RW; reg [7:0] write_bounds [1:3] `PUBLIC_FLAT_RW; reg [7:0] write_inaccessible [0:3] `PUBLIC_FLAT_RD; `ifdef IVERILOG // stop icarus optimizing signals away wire redundant = write_bytes[0][0] | write_bytes[0][0] | write_bytes_rl[0][0] | write_bytes_nonzero_index[1][0] | write_shorts[0][0] | write_words[0][0] | write_longs[0][0] | write_customs[0][0] | write_customs_nonzero_index_rl[1][0] | write_integers[0][0] | write_scalar[0] | write_bounds[1][0] | write_inaccessible[0][0]; `endif integer status; initial begin `ifdef IVERILOG status = $mon_check; `endif `ifdef VERILATOR status = $c32("mon_check()"); `endif if (status != 0) begin $write("%%Error: t_vpi_put_value_array.cpp:%0d: C Test failed\n", status); $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_mem_multi_io2_cc.py0000755000542200017500000000131715101701376023176 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_mem_multi_io2.cpp" test.top_filename = "t/t_mem_multi_io2.v" test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename, "-fno-inline"], verilator_flags3=[]) test.execute() test.passes() verilator-5.042/test_regress/t/t_nba_shared_flag_reuse.v0000644000542200017500000000275215101701376024070 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); module t; reg clk = 1'b1; reg reset = 1'b1; reg aw_valid = 1'b0; reg w_valid = 1'b0; reg r_valid; reg [31:0] addr [1:0]; reg [7:0] len [1:0]; always #5 clk = ~clk; initial begin #5; // Align with negedge clk #20; `checkh(addr[0], 32'h0000_0000); reset = 1'b0; #20; `checkh(addr[0], 32'h0000_0000); aw_valid = 1'b1; w_valid = 1'b1; #10; `checkh(addr[0], 32'h4444_4444); aw_valid = 1'b0; #10; `checkh(addr[0], 32'h2222_2222); w_valid = 1'b0; #10; `checkh(addr[0], 32'h2222_2222); $write("*-* All Finished *-*\n"); $finish; end always @(posedge clk) begin if (reset) begin r_valid <= 0; addr[0] <= '0; end else begin if (r_valid) begin addr[0] <= 32'h11111111; len[0] <= len[0] - 1; end if (w_valid) begin addr[0] <= 32'h22222222; end if (aw_valid) begin addr[0] <= 32'h33333333; len[0] <= 8'hff; if (w_valid) addr[0] <= 32'h44444444; end end end endmodule verilator-5.042/test_regress/t/t_assert_synth.py0000755000542200017500000000102015101701376022505 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--assert'], nc_flags2=['+assert']) test.execute() test.passes() verilator-5.042/test_regress/t/t_tri_and_eqcase.py0000755000542200017500000000077315101701376022736 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_pkg_colon_bad.out0000644000542200017500000000040115101701376023744 0ustar mahmoudyfreeshell%Error: t/t_lint_pkg_colon_bad.v:8:8: syntax error, unexpected IDENTIFIER-:: 8 | reg mispkgb::bar_t b; | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_math_imm.v0000644000542200017500000000704415101701376021400 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // // Example module to create problem. // // generate a 64 bit value with bits // [HighMaskSel_Bot : LowMaskSel_Bot ] = 1 // [HighMaskSel_Top+32: LowMaskSel_Top+32] = 1 // all other bits zero. module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc = 0; reg [7:0] crc; reg [63:0] sum; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [63:0] HighLogicImm; // From example of example.v wire [63:0] LogicImm; // From example of example.v wire [63:0] LowLogicImm; // From example of example.v // End of automatics wire [5:0] LowMaskSel_Top = crc[5:0]; wire [5:0] LowMaskSel_Bot = crc[5:0]; wire [5:0] HighMaskSel_Top = crc[5:0]+{4'b0,crc[7:6]}; wire [5:0] HighMaskSel_Bot = crc[5:0]+{4'b0,crc[7:6]}; example example (/*AUTOINST*/ // Outputs .LogicImm (LogicImm[63:0]), .LowLogicImm (LowLogicImm[63:0]), .HighLogicImm (HighLogicImm[63:0]), // Inputs .LowMaskSel_Top (LowMaskSel_Top[5:0]), .HighMaskSel_Top (HighMaskSel_Top[5:0]), .LowMaskSel_Bot (LowMaskSel_Bot[5:0]), .HighMaskSel_Bot (HighMaskSel_Bot[5:0])); always @ (posedge clk) begin cyc <= cyc + 1; crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%b %d.%d,%d.%d -> %x.%x -> %x\n", $time, cyc, crc, LowMaskSel_Top, HighMaskSel_Top, LowMaskSel_Bot, HighMaskSel_Bot, LowLogicImm, HighLogicImm, LogicImm); `endif if (cyc==0) begin // Single case crc <= 8'h0; sum <= 64'h0; end else if (cyc==1) begin // Setup crc <= 8'hed; sum <= 64'h0; end else if (cyc<90) begin sum <= {sum[62:0],sum[63]} ^ LogicImm; end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%b %x\n", $time, cyc, crc, sum); if (crc !== 8'b00111000) $stop; if (sum !== 64'h58743ffa61e41075) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module example (/*AUTOARG*/ // Outputs LogicImm, LowLogicImm, HighLogicImm, // Inputs LowMaskSel_Top, HighMaskSel_Top, LowMaskSel_Bot, HighMaskSel_Bot ); input [5:0] LowMaskSel_Top, HighMaskSel_Top; input [5:0] LowMaskSel_Bot, HighMaskSel_Bot; output [63:0] LogicImm; output [63:0] LowLogicImm, HighLogicImm; wire [63:0] LowLogicImm, HighLogicImm; /* verilator lint_off UNSIGNED */ /* verilator lint_off CMPCONST */ genvar i; generate for (i=0;i<64;i=i+1) begin : MaskVal if (i >= 32) begin assign LowLogicImm[i] = (LowMaskSel_Top <= i[5:0]); assign HighLogicImm[i] = (HighMaskSel_Top >= i[5:0]); end else begin assign LowLogicImm[i] = (LowMaskSel_Bot <= i[5:0]); assign HighLogicImm[i] = (HighMaskSel_Bot >= i[5:0]); end end endgenerate /* verilator lint_on UNSIGNED */ /* verilator lint_on CMPCONST */ assign LogicImm = LowLogicImm & HighLogicImm; endmodule verilator-5.042/test_regress/t/t_lint_range_negative_bad.out0000644000542200017500000000152015101701376024752 0ustar mahmoudyfreeshell%Error: t/t_lint_range_negative_bad.v:8:16: Size of range is '[0]', must be positive integer (IEEE 1800-2023 7.4.2) : ... note: In instance 't' 8 | int array_bad[0]; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_lint_range_negative_bad.v:9:17: Size of range is '[-1]', must be positive integer (IEEE 1800-2023 7.4.2) : ... note: In instance 't' 9 | int array2_bad[-1]; | ^ %Error: t/t_lint_range_negative_bad.v:11:10: left side of bit range isn't a two-state constant (IEEE 1800-2023 6.9.1) : ... note: In instance 't' 11 | logic [X:0] x; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_class_param_mailbox.py0000755000542200017500000000073415101701376023772 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_dfg_regularize_clk.v0000644000542200017500000000172015101701376023422 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkd(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module sub ( input clk, input b ); /*verilator hier_block*/ reg tmp_clk; assign tmp_clk = clk; always @(posedge tmp_clk) begin $display("[%0t] triggered by clk", $time); end int count = 0; always @(b) begin `ifdef TEST_VERBOSE $display("[%0t] triggered by b", $time); `endif ++count; end final `checkd(count, 2); endmodule module t ( /*AUTOARG*/ // Inputs clk ); input clk; logic b = 1; sub sub (.*); int cyc = 0; always @(posedge clk) begin cyc <= cyc + 1; if (cyc >= 2) begin $finish; end end endmodule verilator-5.042/test_regress/t/t_cover_const_compare.py0000755000542200017500000000100015101701376024007 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--coverage-line']) test.execute() test.passes() verilator-5.042/test_regress/t/t_math_vliw_noexpand.py0000755000542200017500000000103415101701376023652 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_math_vliw.v" test.compile(verilator_flags2=['-fno-expand']) test.execute() test.passes() verilator-5.042/test_regress/t/t_tri_pull2_bad.out0000644000542200017500000000071415101701376022666 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_tri_pull2_bad.v:12:11: Unsupported: Conflicting pull directions. : ... note: In instance 't' 12 | pullup p1(A); | ^~ t/t_tri_pull2_bad.v:22:13: ... Location of conflicting pull. 22 | pulldown p2(A); | ^~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_force_initial.py0000755000542200017500000000076315101701376022603 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_assert_basic.v0000644000542200017500000000310215101701376022236 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg toggle; integer cyc; initial cyc=1; wire [7:0] cyc_copy = cyc[7:0]; always @ (negedge clk) begin AssertionFalse1: assert (cyc<100); assert (!(cyc==5) || toggle); // FIX cover {cyc==3 || cyc==4}; // FIX cover {cyc==9} report "DefaultClock,expect=1"; // FIX cover {(cyc==5)->toggle} report "ToggleLogIf,expect=1"; end always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; toggle <= !cyc[0]; if (cyc==7) assert (cyc[0] == cyc[1]); // bug743 if (cyc==9) begin `ifdef FAILING_ASSERTIONS assert (0) else $info; assert (0) else $info("Info message"); assume (0) else $info("Info message from failing assumption"); assert (0) else $info("Info message, cyc=%d", cyc); InWarningBlock: assert (0) else $warning; InWarningMBlock: assert (0) else $warning("Warning.... 1.0=%f 2.0=%f", 1.0, 2.0); InErrorBlock: assert (0) else $error; InErrorMBlock: assert (0) else $error("Error...."); assert (0) else $fatal(1, "Fatal...."); assert (0) else $fatal; `endif end if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.042/test_regress/t/t_inst_misarray2_bad.py0000755000542200017500000000076615101701376023553 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_select_loop.py0000755000542200017500000000073415101701376022302 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_mem_multi_io3.v0000644000542200017500000000360315101701376022344 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013. // SPDX-License-Identifier: CC0-1.0 module t ( input logic clk, input logic daten, input logic [8:0] datval, output logic signed [3:0][3:0][35:0] datao ); logic signed [3:0][3:0][3:0][8:0] datat; genvar i; generate for (i=0; i<4; i++)begin testio dut(.clk(clk), .arr3d_in(datat[i]), .arr2d_out(datao[i])); end endgenerate genvar j; generate for (i=0; i<4; i++) begin for (j=0; j<4; j++) begin always_comb datat[i][j][0] = daten ? 9'h0 : datval; always_comb datat[i][j][1] = daten ? 9'h1 : datval; always_comb datat[i][j][2] = daten ? 9'h2 : datval; always_comb datat[i][j][3] = daten ? 9'h3 : datval; end end endgenerate endmodule module testio ( input clk, input logic signed [3:0] [3:0] [8:0] arr3d_in, output logic signed [3:0] [35:0] arr2d_out ); /* verilator lint_off MULTIDRIVEN */ logic signed [3:0] [35:0] ar2d_out_pre; /* verilator lint_on MULTIDRIVEN */ always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]}; always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]}; always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]}; always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]}; always_ff @(posedge clk) begin if (clk) arr2d_out <= ar2d_out_pre; end endmodule verilator-5.042/test_regress/t/t_sequence_sexpr_unsup.v0000644000542200017500000000540115101701376024063 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; int a; int b; int cyc = 0; int res0, res1; localparam DELAY = 1; always @(posedge clk) begin cyc <= cyc + 1; end // NOTE this grammar hasn't been checked with other simulators, // is here just to avoid uncovered code lines in the grammar. // NOTE using 'property weak' here as sequence/endsequence not supported sequence s_a; a; endsequence : s_a sequence s_var; logic l1, l2; a; endsequence sequence s_within; a within(b); endsequence sequence s_and; a and b; endsequence sequence s_or; a or b; endsequence sequence s_throughout; a throughout b; endsequence sequence s_intersect; a intersect b; endsequence sequence s_uni_cycdelay_id; ## DELAY b; endsequence sequence s_uni_cycdelay_pid; ## ( DELAY ) b; endsequence sequence s_uni_cycdelay_range; ## [1:2] b; endsequence sequence s_uni_cycdelay_star; ## [*] b; endsequence sequence s_uni_cycdelay_plus; ## [+] b; endsequence sequence s_cycdelay_int; a ## 1 b; endsequence sequence s_cycdelay_id; a ## DELAY b; endsequence sequence s_cycdelay_pid; a ## ( DELAY ) b; endsequence sequence s_cycdelay_range; a ## [1:2] b; endsequence sequence s_cycdelay_star; a ## [*] b; endsequence sequence s_cycdelay_plus; a ## [+] b; endsequence sequence s_booleanabbrev_brastar_int; a [* 1 ]; endsequence sequence s_booleanabbrev_brastar; a [*]; endsequence sequence s_booleanabbrev_plus; a [+]; endsequence sequence s_booleanabbrev_eq; a [= 1]; endsequence sequence s_booleanabbrev_eq_range; a [= 1:2]; endsequence sequence s_booleanabbrev_minusgt; a [-> 1]; endsequence sequence s_booleanabbrev_minusgt_range; a [-> 1:2]; endsequence sequence p_arg_seqence(sequence inseq); inseq; endsequence sequence s_firstmatch_a; first_match (a); endsequence sequence s_firstmatch_ab; first_match (a, res0 = 1); endsequence sequence s_firstmatch_abc; first_match (a, res0 = 1, res1 = 2); endsequence cover sequence (s_a) $display(""); cover sequence (@(posedge a) disable iff (b) s_a) $display(""); cover sequence (disable iff (b) s_a) $display(""); always @(posedge clk) begin if (cyc == 10) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_trace_string_fst.py0000755000542200017500000000105215101701376023324 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_string.v" test.compile(verilator_flags2=['--cc --trace-vcd']) test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_down.py0000755000542200017500000000073415101701376022761 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_concat_impure.v0000644000542200017500000000106615101701376022433 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 int global_variable = 0; function int side_effect; global_variable++; return 1; endfunction module t; reg [15:0] x; reg [15:0] y; initial begin {x, y} = side_effect() + 2; if (y != 3) $stop; if (x != 0) $stop; if (global_variable != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_vlt_match_error_2.py0000755000542200017500000000124515101701376023403 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_vlt_match_error.v" test.lint(verilator_flags2=[ "-DT_VLT_MATCH_ERROR_2 --lint-only -Wall t/t_vlt_match_error.v t/t_vlt_match_error.vlt" ], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_diamond.v0000644000542200017500000000241115101701376022376 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module class_tb (); interface class Ibase; pure virtual function int fn(); endclass interface class Ic1 extends Ibase; pure virtual function int fn1(); endclass interface class Ic2 extends Ibase; pure virtual function int fn2(); endclass interface class Ic3 extends Ic1, Ic2; endclass class Cls implements Ic3; virtual function int fn(); return 10; endfunction virtual function int fn1(); return 1; endfunction virtual function int fn2(); return 2; endfunction endclass initial begin Cls cls; Ibase ibase; Ic1 ic1; Ic2 ic2; Ic3 ic3; cls = new; if (cls.fn() != 10) $stop; if (cls.fn1() != 1) $stop; if (cls.fn2() != 2) $stop; ibase = cls; ic1 = cls; ic2 = cls; ic3 = cls; if (ibase.fn() != 10) $stop; if (ic1.fn() != 10) $stop; if (ic2.fn() != 10) $stop; if (ic3.fn() != 10) $stop; if (ic1.fn1() != 1) $stop; if (ic2.fn2() != 2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_initial_assign_sformatf.py0000755000542200017500000000073415101701376024670 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_math_cond_huge_noexpand.py0000755000542200017500000000104115101701376024622 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_math_cond_huge.v" test.compile(verilator_flags2=['-fno-expand']) test.execute() test.passes() verilator-5.042/test_regress/t/t_cast_param_type.v0000644000542200017500000000142315101701376022753 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef enum logic [1:0] {A, B, C } letters_t; module SubA #(parameter letters_t LETTER = A) (); endmodule module SubB #(parameter letters_t LETTER = letters_t'(0)) (); endmodule function automatic letters_t lfunc(int a); return letters_t'(1); endfunction module t (); localparam FMT = lfunc(1); SubA suba0 (); SubA #(.LETTER(letters_t'(1))) suba1 (); SubB #(.LETTER(letters_t'(1))) subb2 (); initial begin if (lfunc(1) != B) $stop; if (FMT != B) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_nba_mixed_update_clocked.v0000644000542200017500000000337515101701376024564 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define check(got ,exp) do if ((got) !== (exp)) begin $write("%%Error: %s:%0d: cyc=%0d got='h%x exp='h%x\n", `__FILE__,`__LINE__, cyc, (got), (exp)); `stop; end while(0) module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [31:0] cyc = 0; // 'x' has both blocking and non-blocking update, with the blocking // update in **clocked** logic reg [1:0] x = 2'b00; // '{y1, y0}' should have exactly the same value as 'x', at all times reg y0 = 1'b0; reg y1 = 1'b0; // 'z[0]' should equal '{8{x[0]}', 'z[1]' should equal '{8{x[1]}}' reg [1:0][7:0] z = '{default: 0}; // 'pair.a' should equal 'x[0]', 'pair.b' should equal 'x[1]' struct { logic a; logic b; } pair = '{a: 1'b0, b: 1'b0}; always @(posedge clk) begin $display("cyc = %d (%08x) x[1] = %0d, x[0] = %0d, y1 = %0d, y0 = %0d z[1] = %02x z[1] = %02x pair.a = %0d pair.b = %0d", cyc, cyc, x[1], x[0], y1, y0, z[1], z[0], pair.a, pair.b); `check(x[0], cyc[0]); `check(x[1], cyc[0]); `check(y0, cyc[0]); `check(y1, cyc[0]); `check(z[0], {8{cyc[0]}}); `check(z[1], {8{cyc[0]}}); `check(pair.a, cyc[0]); `check(pair.b, cyc[0]); x[1] <= ~x[1]; y1 <= ~y1; for (int i = 0; i < 8; ++i) z[1][i] <= ~z[1][i]; pair.b <= ~pair.b; cyc = cyc + 1; x[0] = cyc[0]; y0 = cyc[0]; for (int i = 0; i < 8; ++i) z[0][i] = cyc[0]; pair.a = cyc[0]; if (cyc == 99) begin $display(x); $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_var_in_assign.py0000755000542200017500000000073415101701376022614 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_dpi_qw.py0000755000542200017500000000107715101701376021256 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=["t/t_dpi_qw_c.cpp"], verilator_flags2=["-Wall -Wno-DECLFILENAME -no-l2name"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_mem_banks.v0000644000542200017500000000402215101701376021532 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg [5:0] addr; parameter BANKS = 6; parameter ROWS = 8; reg [2:0] bank; reg [2:0] row; integer a; integer used[BANKS][ROWS]; // Test loop initial begin for (a = 0; a < BANKS*ROWS; ++a) begin addr[5:0] = a[5:0]; hash (addr, bank, row); used [bank][row] ++; if (used [bank][row] > 1) begin $write ("Error: Hash failed addr=%x bank=%x row=%x\n", addr, bank, row); end end $write("*-* All Finished *-*\n"); $finish; end task hash (input [5:0] addr, output [2:0] bank, output [2:0] row); reg [1:0] third; reg [1:0] fourth; third = {addr[5], addr[4]}; fourth = {addr[3] ^ addr[1], addr[2] ^ addr[0]}; case (third) 2'h0: case (fourth) 2'h0: begin bank = 3'h0; row = {1'h0, addr[1:0]}; end 2'h1: begin bank = 3'h1; row = {1'h0, addr[1:0]}; end 2'h2: begin bank = 3'h2; row = {1'h0, addr[1:0]}; end 2'h3: begin bank = 3'h3; row = {1'h0, addr[1:0]}; end endcase 2'h1: case (fourth) 2'h0: begin bank = 3'h0; row = {1'h1, addr[1:0]}; end 2'h1: begin bank = 3'h1; row = {1'h1, addr[1:0]}; end 2'h2: begin bank = 3'h4; row = {1'h0, addr[1:0]}; end 2'h3: begin bank = 3'h5; row = {1'h0, addr[1:0]}; end endcase 2'h2: case (fourth) 2'h0: begin bank = 3'h2; row = {1'h1, addr[1:0]}; end 2'h1: begin bank = 3'h3; row = {1'h1, addr[1:0]}; end 2'h2: begin bank = 3'h4; row = {1'h1, addr[1:0]}; end 2'h3: begin bank = 3'h5; row = {1'h1, addr[1:0]}; end endcase 2'h3: $stop; endcase endtask endmodule verilator-5.042/test_regress/t/t_udp_bad_illegal_output.out0000644000542200017500000000320415101701376024650 0ustar mahmoudyfreeshell%Error: t/t_udp_bad_illegal_output.v:9:8: For sequential UDP, the output must be of 'reg' data type : ... note: In instance 'top' 9 | output dout; | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_udp_bad_illegal_output.v:16:22: Illegal value for sequential UDP line output : ... note: In instance 'top' 16 | 1 1 ? : ?: *; | ^ %Error: t/t_udp_bad_illegal_output.v:17:11: There can be only one edge tigger signal : ... note: In instance 'top' 17 | f r 0 : ?: 0; | ^ %Error: t/t_udp_bad_illegal_output.v:18:22: Illegal value for sequential UDP line output : ... note: In instance 'top' 18 | 0 0 0 : ?: *; | ^ %Error: t/t_udp_bad_illegal_output.v:29:9: There should not be a edge trigger for combinational UDP table line : ... note: In instance 'top' 29 | r ? 1 : 1; | ^ %Error: t/t_udp_bad_illegal_output.v:31:20: Illegal value for combinational UDP line output : ... note: In instance 'top' 31 | 1 1 ? : *; | ^ %Error: t/t_udp_bad_illegal_output.v:33:20: Illegal value for combinational UDP line output : ... note: In instance 'top' 33 | 0 0 0 : *; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_class_new_bad.py0000755000542200017500000000076615101701376022563 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_opt_dead_nocells.v0000644000542200017500000000056415101701376023103 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module Mod_Dead; endmodule module t; Mod_Dead cell_keptdead(); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_class_func_nvoid_bad.out0000644000542200017500000000275715101701376024302 0ustar mahmoudyfreeshell%Error: t/t_class_func_nvoid_bad.v:47:11: Cannot call a task/void-function as a function: 'mod_fv' : ... note: In instance 't' 47 | if (mod_fv() == 10) $stop; | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_class_func_nvoid_bad.v:50:11: Cannot call a task/void-function as a function: 'mod_t' : ... note: In instance 't' 50 | if (mod_t() == 10) $stop; | ^~~~~ %Error: t/t_class_func_nvoid_bad.v:58:13: Cannot call a task/void-function as a member function: 'fv' : ... note: In instance 't' 58 | if (c.fv() == 10) $stop; | ^~ %Error: t/t_class_func_nvoid_bad.v:61:13: Cannot call a task/void-function as a member function: 't' : ... note: In instance 't' 61 | if (c.t() == 10) $stop; | ^ %Error: t/t_class_func_nvoid_bad.v:69:13: Cannot call a task/void-function as a function: 'sfv' : ... note: In instance 't' 69 | if (c.sfv() == 10) $stop; | ^~~ %Error: t/t_class_func_nvoid_bad.v:72:13: Cannot call a task/void-function as a function: 'st' : ... note: In instance 't' 72 | if (c.st() == 10) $stop; | ^~ %Error: Exiting due to verilator-5.042/test_regress/t/t_x_rand_mt_stability_add_trace.out0000644000542200017500000000105615101701376026171 0ustar mahmoudyfreeshelluninitialized = 0xf5bbcbc0 x_assigned (initial) = 0x00000000 uninitialized2 = 0xa979eb54 big = 0xa20c93ac50d8c57d4c80949aa68e82775da6af98ce08f75dc6ccfad97b059a33 random_init = 0x952aaa76 top.t.the_sub_yes_inline_1 no_init 0x4a544f7798b83fc8 top.t.the_sub_yes_inline_2 no_init 0x19b7000ee0472c9 top.t.the_sub_no_inline_1 no_init 0x38121a34978975dd top.t.the_sub_no_inline_2 no_init 0x9022c84ae0fa3cf6 rand = 0xb3cf9302 rand = 0xf0acf3e4 rand = 0xca0ac74c rand = 0x4eddfc2c rand = 0x1919db69 x_assigned = 0x486aeb2d Last rand = 0x2d118c9b *-* All Finished *-* verilator-5.042/test_regress/t/t_blocking.py0000755000542200017500000000073415101701376021562 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_dpi_export_context_bad.out0000644000542200017500000000027015101701376024670 0ustar mahmoudyfreeshell%Error: unknown:0: Testbench C called 'dpix_task' but scope wasn't set, perhaps due to dpi import call without 'context', or missing svSetScope. See IEEE 1800-2023 35.5.3. Aborting... verilator-5.042/test_regress/t/t_var_init.py0000755000542200017500000000073415101701376021605 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_generic_normal.v0000644000542200017500000000124115101701376024602 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 interface inf; int v; endinterface module GenericModule (interface a, inf b, interface c); initial begin #1; if (a.v != 7) $stop; if (b.v != 8) $stop; if (c.v != 9) $stop; end endmodule module t; inf inf_inst[3](); GenericModule genericModule (inf_inst[0], inf_inst[1], inf_inst[2]); initial begin inf_inst[0].v = 7; inf_inst[1].v = 8; inf_inst[2].v = 9; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_trace_complex_fst_threads_2_sc.py0000755000542200017500000000135615101701376026114 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_complex.v" test.golden_filename = "t/t_trace_complex_fst_sc.out" if not test.have_sc: test.skip("No SystemC installed") test.compile(verilator_flags2=['--sc --trace-fst --trace-threads 2']) test.execute() test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_metacmt_onoff.py0000755000542200017500000000077315101701376022616 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_case_default_bad.out0000644000542200017500000000041015101701376023362 0ustar mahmoudyfreeshell%Error: t/t_case_default_bad.v:16:9: Multiple default statements in case statement. 16 | default: $stop; | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_func_cond.py0000755000542200017500000000073415101701376021730 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_repeat.v0000644000542200017500000000150015101701376021054 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg signed [2:0] negcnt; integer times; initial begin times = 0; repeat (1) begin repeat (0) $stop; repeat (-1) $stop; negcnt = 'sb111; // Not all commercial simulators agree on the below stopping or not // verilator lint_off WIDTH repeat (negcnt) $stop; // verilator lint_on WIDTH repeat (5) begin repeat (2) begin times = times + 1; end end end if (times != 10) $stop; // $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_class_virtual.py0000755000542200017500000000073415101701376022645 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_order_2d.py0000755000542200017500000000073415101701376021472 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_wire_beh1800_bad.out0000644000542200017500000000250415101701376023046 0ustar mahmoudyfreeshell%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:25:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'w' : ... note: In instance 't' 25 | w = '0; | ^ ... For error description see https://verilator.org/warn/PROCASSWIRE?v=latest %Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:26:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'o' : ... note: In instance 't' 26 | o = '0; | ^ %Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:27:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'oa' : ... note: In instance 't' 27 | oa = '0; | ^~ %Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:28:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'wo' : ... note: In instance 't' 28 | wo = '0; | ^~ %Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:29:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'woa' : ... note: In instance 't' 29 | woa = '0; | ^~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_vpi_public_depthn_1.out0000644000542200017500000000012015101701376024051 0ustar mahmoudyfreeshell scopesDump: SCOPE 0x#: top.TOP SCOPE 0x#: top.t *-* All Finished *-* verilator-5.042/test_regress/t/t_lint_pindup_bad.py0000755000542200017500000000076615101701376023132 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_pp_dupdef_bad.py0000755000542200017500000000103115101701376022535 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_pp_dupdef.v" test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_select_bad_width0.out0000644000542200017500000000256515101701376023516 0ustar mahmoudyfreeshell%Error: t/t_select_bad_width0.v:15:21: Width of bit extract must be positive (IEEE 1800-2023 11.5.1) : ... note: In instance 't' 15 | int part = val[left +: ZERO]; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Warning-WIDTHEXPAND: t/t_select_bad_width0.v:15:21: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits. : ... note: In instance 't' 15 | int part = val[left +: ZERO]; | ^ ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. %Error: t/t_select_bad_width0.v:17:17: Width of bit extract must be positive (IEEE 1800-2023 11.5.1) : ... note: In instance 't' 17 | part = val[left -: ZERO]; | ^ %Warning-WIDTHEXPAND: t/t_select_bad_width0.v:17:12: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits. : ... note: In instance 't' 17 | part = val[left -: ZERO]; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_opt_table_signed.out0000644000542200017500000000027515101701376023450 0ustar mahmoudyfreeshellcyle 0 = 0 cyle 1 = -1 cyle 2 = 2 cyle 3 = -2147483648 cyle 4 = -4 cyle 5 = 5 cyle 6 = -2147483648 cyle 7 = -2147483648 *-* All Finished *-* verilator-5.042/test_regress/t/t_net_delay_timing.py0000755000542200017500000000106115101701376023277 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_net_delay.v" test.compile(timing_loop=True, verilator_flags2=["--timing"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_always_comb_multidriven_compile_public_flat_bad.out0000644000542200017500000001334115101701376032776 0ustar mahmoudyfreeshell%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:26:16: Variable written to in always_comb also written by other process (IEEE 1800-2023 9.2.2.2): 'out1' : ... note: In instance 't' t/t_lint_always_comb_multidriven_bad.v:26:16: 26 | always_comb out1 = d; | ^~~~ t/t_lint_always_comb_multidriven_bad.v:25:11: ... Location of other write 25 | assign out1 = 1'b0; | ^~~~ ... For warning description see https://verilator.org/warn/MULTIDRIVEN?v=latest ... Use "/* verilator lint_off MULTIDRIVEN */" and lint_on around source to disable this message. %Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:29:16: Variable written to in always_comb also written by other process (IEEE 1800-2023 9.2.2.2): 'out2' : ... note: In instance 't' t/t_lint_always_comb_multidriven_bad.v:29:16: 29 | always_comb out2 = 1'b0; | ^~~~ t/t_lint_always_comb_multidriven_bad.v:28:11: ... Location of other write 28 | assign out2 = d; | ^~~~ %Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:32:11: Variable also written to in always_comb (IEEE 1800-2023 9.2.2.2): 'out3' : ... note: In instance 't' t/t_lint_always_comb_multidriven_bad.v:32:11: 32 | assign out3 = 1'b0; | ^~~~ t/t_lint_always_comb_multidriven_bad.v:31:16: ... Location of always_comb write 31 | always_comb out3 = d; | ^~~~ %Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:35:11: Variable also written to in always_comb (IEEE 1800-2023 9.2.2.2): 'out4' : ... note: In instance 't' t/t_lint_always_comb_multidriven_bad.v:35:11: 35 | assign out4 = d; | ^~~~ t/t_lint_always_comb_multidriven_bad.v:34:16: ... Location of always_comb write 34 | always_comb out4 = 1'b0; | ^~~~ %Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:38:16: Variable written to in always_comb also written by other process (IEEE 1800-2023 9.2.2.2): 'out5' : ... note: In instance 't' t/t_lint_always_comb_multidriven_bad.v:38:16: 38 | always_comb out5 = d; | ^~~~ t/t_lint_always_comb_multidriven_bad.v:37:16: ... Location of other write 37 | always_comb out5 = 1'b0; | ^~~~ %Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:41:16: Variable written to in always_comb also written by other process (IEEE 1800-2023 9.2.2.2): 'out6' : ... note: In instance 't' t/t_lint_always_comb_multidriven_bad.v:41:16: 41 | always_comb out6 = 1'b0; | ^~~~ t/t_lint_always_comb_multidriven_bad.v:40:16: ... Location of other write 40 | always_comb out6 = d; | ^~~~ %Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:17:15: Bit [0] of signal 'out2' have multiple combinational drivers. This can cause performance degradation. : ... note: In instance 't' t/t_lint_always_comb_multidriven_bad.v:28:16: ... Location of offending driver 28 | assign out2 = d; | ^ t/t_lint_always_comb_multidriven_bad.v:29:21: ... Location of offending driver 29 | always_comb out2 = 1'b0; | ^ %Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:19:15: Bit [0] of signal 'out4' have multiple combinational drivers. This can cause performance degradation. : ... note: In instance 't' t/t_lint_always_comb_multidriven_bad.v:34:21: ... Location of offending driver 34 | always_comb out4 = 1'b0; | ^ t/t_lint_always_comb_multidriven_bad.v:35:16: ... Location of offending driver 35 | assign out4 = d; | ^ %Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:20:15: Bit [0] of signal 'out5' have multiple combinational drivers. This can cause performance degradation. : ... note: In instance 't' t/t_lint_always_comb_multidriven_bad.v:37:21: ... Location of offending driver 37 | always_comb out5 = 1'b0; | ^ t/t_lint_always_comb_multidriven_bad.v:38:21: ... Location of offending driver 38 | always_comb out5 = d; | ^ %Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:21:15: Bit [0] of signal 'out6' have multiple combinational drivers. This can cause performance degradation. : ... note: In instance 't' t/t_lint_always_comb_multidriven_bad.v:40:21: ... Location of offending driver 40 | always_comb out6 = d; | ^ t/t_lint_always_comb_multidriven_bad.v:41:21: ... Location of offending driver 41 | always_comb out6 = 1'b0; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_type_compare_bad.py0000755000542200017500000000077615101701376023275 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_sys_file_basic_uz.out0000644000542200017500000004200015101701376023632 0ustar mahmoudyfreeshell00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 55 56 57 58 59 5a 5b 5c 5d 5e 5f 60 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f 70 71 72 73 74 75 76 77 78 79 7a 7b 7c 7d 7e 7f 80 81 82 83 84 85 86 87 88 89 8a 8b 8c 8d 8e 8f 90 91 92 93 94 95 96 97 98 99 9a 9b 9c 9d 9e 9f a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 aa ab ac ad ae af b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 ba bb bc bd be bf c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 ca cb cc cd ce cf d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 da db dc dd de df e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 ea eb ec ed ee ef f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd fe ff 0100 0201 0302 0403 0504 0605 0706 0807 0908 0a09 0b0a 0c0b 0d0c 0e0d 0f0e 100f 1110 1211 1312 1413 1514 1615 1716 1817 1918 1a19 1b1a 1c1b 1d1c 1e1d 1f1e 201f 2120 2221 2322 2423 2524 2625 2726 2827 2928 2a29 2b2a 2c2b 2d2c 2e2d 2f2e 302f 3130 3231 3332 3433 3534 3635 3736 3837 3938 3a39 3b3a 3c3b 3d3c 3e3d 3f3e 403f 4140 4241 4342 4443 4544 4645 4746 4847 4948 4a49 4b4a 4c4b 4d4c 4e4d 4f4e 504f 5150 5251 5352 5453 5554 5655 5756 5857 5958 5a59 5b5a 5c5b 5d5c 5e5d 5f5e 605f 6160 6261 6362 6463 6564 6665 6766 6867 6968 6a69 6b6a 6c6b 6d6c 6e6d 6f6e 706f 7170 7271 7372 7473 7574 7675 7776 7877 7978 7a79 7b7a 7c7b 7d7c 7e7d 7f7e 807f 8180 8281 8382 8483 8584 8685 8786 8887 8988 8a89 8b8a 8c8b 8d8c 8e8d 8f8e 908f 9190 9291 9392 9493 9594 9695 9796 9897 9998 9a99 9b9a 9c9b 9d9c 9e9d 9f9e a09f a1a0 a2a1 a3a2 a4a3 a5a4 a6a5 a7a6 a8a7 a9a8 aaa9 abaa acab adac aead afae b0af b1b0 b2b1 b3b2 b4b3 b5b4 b6b5 b7b6 b8b7 b9b8 bab9 bbba bcbb bdbc bebd bfbe c0bf c1c0 c2c1 c3c2 c4c3 c5c4 c6c5 c7c6 c8c7 c9c8 cac9 cbca cccb cdcc cecd cfce d0cf d1d0 d2d1 d3d2 d4d3 d5d4 d6d5 d7d6 d8d7 d9d8 dad9 dbda dcdb dddc dedd dfde e0df e1e0 e2e1 e3e2 e4e3 e5e4 e6e5 e7e6 e8e7 e9e8 eae9 ebea eceb edec eeed efee f0ef f1f0 f2f1 f3f2 f4f3 f5f4 f6f5 f7f6 f8f7 f9f8 faf9 fbfa fcfb fdfc fefd fffe 00ff 03020100 04030201 05040302 06050403 07060504 08070605 09080706 0a090807 0b0a0908 0c0b0a09 0d0c0b0a 0e0d0c0b 0f0e0d0c 100f0e0d 11100f0e 1211100f 13121110 14131211 15141312 16151413 17161514 18171615 19181716 1a191817 1b1a1918 1c1b1a19 1d1c1b1a 1e1d1c1b 1f1e1d1c 201f1e1d 21201f1e 2221201f 23222120 24232221 25242322 26252423 27262524 28272625 29282726 2a292827 2b2a2928 2c2b2a29 2d2c2b2a 2e2d2c2b 2f2e2d2c 302f2e2d 31302f2e 3231302f 33323130 34333231 35343332 36353433 37363534 38373635 39383736 3a393837 3b3a3938 3c3b3a39 3d3c3b3a 3e3d3c3b 3f3e3d3c 403f3e3d 41403f3e 4241403f 43424140 44434241 45444342 46454443 47464544 48474645 49484746 4a494847 4b4a4948 4c4b4a49 4d4c4b4a 4e4d4c4b 4f4e4d4c 504f4e4d 51504f4e 5251504f 53525150 54535251 55545352 56555453 57565554 58575655 59585756 5a595857 5b5a5958 5c5b5a59 5d5c5b5a 5e5d5c5b 5f5e5d5c 605f5e5d 61605f5e 6261605f 63626160 64636261 65646362 66656463 67666564 68676665 69686766 6a696867 6b6a6968 6c6b6a69 6d6c6b6a 6e6d6c6b 6f6e6d6c 706f6e6d 71706f6e 7271706f 73727170 74737271 75747372 76757473 77767574 78777675 79787776 7a797877 7b7a7978 7c7b7a79 7d7c7b7a 7e7d7c7b 7f7e7d7c 807f7e7d 81807f7e 8281807f 83828180 84838281 85848382 86858483 87868584 88878685 89888786 8a898887 8b8a8988 8c8b8a89 8d8c8b8a 8e8d8c8b 8f8e8d8c 908f8e8d 91908f8e 9291908f 93929190 94939291 95949392 96959493 97969594 98979695 99989796 9a999897 9b9a9998 9c9b9a99 9d9c9b9a 9e9d9c9b 9f9e9d9c a09f9e9d a1a09f9e a2a1a09f a3a2a1a0 a4a3a2a1 a5a4a3a2 a6a5a4a3 a7a6a5a4 a8a7a6a5 a9a8a7a6 aaa9a8a7 abaaa9a8 acabaaa9 adacabaa aeadacab afaeadac b0afaead b1b0afae b2b1b0af b3b2b1b0 b4b3b2b1 b5b4b3b2 b6b5b4b3 b7b6b5b4 b8b7b6b5 b9b8b7b6 bab9b8b7 bbbab9b8 bcbbbab9 bdbcbbba bebdbcbb bfbebdbc c0bfbebd c1c0bfbe c2c1c0bf c3c2c1c0 c4c3c2c1 c5c4c3c2 c6c5c4c3 c7c6c5c4 c8c7c6c5 c9c8c7c6 cac9c8c7 cbcac9c8 cccbcac9 cdcccbca cecdcccb cfcecdcc d0cfcecd d1d0cfce d2d1d0cf d3d2d1d0 d4d3d2d1 d5d4d3d2 d6d5d4d3 d7d6d5d4 d8d7d6d5 d9d8d7d6 dad9d8d7 dbdad9d8 dcdbdad9 dddcdbda dedddcdb dfdedddc e0dfdedd e1e0dfde e2e1e0df e3e2e1e0 e4e3e2e1 e5e4e3e2 e6e5e4e3 e7e6e5e4 e8e7e6e5 e9e8e7e6 eae9e8e7 ebeae9e8 ecebeae9 edecebea eeedeceb efeeedec f0efeeed f1f0efee f2f1f0ef f3f2f1f0 f4f3f2f1 f5f4f3f2 f6f5f4f3 f7f6f5f4 f8f7f6f5 f9f8f7f6 faf9f8f7 fbfaf9f8 fcfbfaf9 fdfcfbfa fefdfcfb fffefdfc 00fffefd 0100fffe 020100ff 0706050403020100 0807060504030201 0908070605040302 0a09080706050403 0b0a090807060504 0c0b0a0908070605 0d0c0b0a09080706 0e0d0c0b0a090807 0f0e0d0c0b0a0908 100f0e0d0c0b0a09 11100f0e0d0c0b0a 1211100f0e0d0c0b 131211100f0e0d0c 14131211100f0e0d 1514131211100f0e 161514131211100f 1716151413121110 1817161514131211 1918171615141312 1a19181716151413 1b1a191817161514 1c1b1a1918171615 1d1c1b1a19181716 1e1d1c1b1a191817 1f1e1d1c1b1a1918 201f1e1d1c1b1a19 21201f1e1d1c1b1a 2221201f1e1d1c1b 232221201f1e1d1c 24232221201f1e1d 2524232221201f1e 262524232221201f 2726252423222120 2827262524232221 2928272625242322 2a29282726252423 2b2a292827262524 2c2b2a2928272625 2d2c2b2a29282726 2e2d2c2b2a292827 2f2e2d2c2b2a2928 302f2e2d2c2b2a29 31302f2e2d2c2b2a 3231302f2e2d2c2b 333231302f2e2d2c 34333231302f2e2d 3534333231302f2e 363534333231302f 3736353433323130 3837363534333231 3938373635343332 3a39383736353433 3b3a393837363534 3c3b3a3938373635 3d3c3b3a39383736 3e3d3c3b3a393837 3f3e3d3c3b3a3938 403f3e3d3c3b3a39 41403f3e3d3c3b3a 4241403f3e3d3c3b 434241403f3e3d3c 44434241403f3e3d 4544434241403f3e 464544434241403f 4746454443424140 4847464544434241 4948474645444342 4a49484746454443 4b4a494847464544 4c4b4a4948474645 4d4c4b4a49484746 4e4d4c4b4a494847 4f4e4d4c4b4a4948 504f4e4d4c4b4a49 51504f4e4d4c4b4a 5251504f4e4d4c4b 535251504f4e4d4c 54535251504f4e4d 5554535251504f4e 565554535251504f 5756555453525150 5857565554535251 5958575655545352 5a59585756555453 5b5a595857565554 5c5b5a5958575655 5d5c5b5a59585756 5e5d5c5b5a595857 5f5e5d5c5b5a5958 605f5e5d5c5b5a59 61605f5e5d5c5b5a 6261605f5e5d5c5b 636261605f5e5d5c 64636261605f5e5d 6564636261605f5e 666564636261605f 6766656463626160 6867666564636261 6968676665646362 6a69686766656463 6b6a696867666564 6c6b6a6968676665 6d6c6b6a69686766 6e6d6c6b6a696867 6f6e6d6c6b6a6968 706f6e6d6c6b6a69 71706f6e6d6c6b6a 7271706f6e6d6c6b 737271706f6e6d6c 74737271706f6e6d 7574737271706f6e 767574737271706f 7776757473727170 7877767574737271 7978777675747372 7a79787776757473 7b7a797877767574 7c7b7a7978777675 7d7c7b7a79787776 7e7d7c7b7a797877 7f7e7d7c7b7a7978 807f7e7d7c7b7a79 81807f7e7d7c7b7a 8281807f7e7d7c7b 838281807f7e7d7c 84838281807f7e7d 8584838281807f7e 868584838281807f 8786858483828180 8887868584838281 8988878685848382 8a89888786858483 8b8a898887868584 8c8b8a8988878685 8d8c8b8a89888786 8e8d8c8b8a898887 8f8e8d8c8b8a8988 908f8e8d8c8b8a89 91908f8e8d8c8b8a 9291908f8e8d8c8b 939291908f8e8d8c 94939291908f8e8d 9594939291908f8e 969594939291908f 9796959493929190 9897969594939291 9998979695949392 9a99989796959493 9b9a999897969594 9c9b9a9998979695 9d9c9b9a99989796 9e9d9c9b9a999897 9f9e9d9c9b9a9998 a09f9e9d9c9b9a99 a1a09f9e9d9c9b9a a2a1a09f9e9d9c9b a3a2a1a09f9e9d9c a4a3a2a1a09f9e9d a5a4a3a2a1a09f9e a6a5a4a3a2a1a09f a7a6a5a4a3a2a1a0 a8a7a6a5a4a3a2a1 a9a8a7a6a5a4a3a2 aaa9a8a7a6a5a4a3 abaaa9a8a7a6a5a4 acabaaa9a8a7a6a5 adacabaaa9a8a7a6 aeadacabaaa9a8a7 afaeadacabaaa9a8 b0afaeadacabaaa9 b1b0afaeadacabaa b2b1b0afaeadacab b3b2b1b0afaeadac b4b3b2b1b0afaead b5b4b3b2b1b0afae b6b5b4b3b2b1b0af b7b6b5b4b3b2b1b0 b8b7b6b5b4b3b2b1 b9b8b7b6b5b4b3b2 bab9b8b7b6b5b4b3 bbbab9b8b7b6b5b4 bcbbbab9b8b7b6b5 bdbcbbbab9b8b7b6 bebdbcbbbab9b8b7 bfbebdbcbbbab9b8 c0bfbebdbcbbbab9 c1c0bfbebdbcbbba c2c1c0bfbebdbcbb c3c2c1c0bfbebdbc c4c3c2c1c0bfbebd c5c4c3c2c1c0bfbe c6c5c4c3c2c1c0bf c7c6c5c4c3c2c1c0 c8c7c6c5c4c3c2c1 c9c8c7c6c5c4c3c2 cac9c8c7c6c5c4c3 cbcac9c8c7c6c5c4 cccbcac9c8c7c6c5 cdcccbcac9c8c7c6 cecdcccbcac9c8c7 cfcecdcccbcac9c8 d0cfcecdcccbcac9 d1d0cfcecdcccbca d2d1d0cfcecdcccb d3d2d1d0cfcecdcc d4d3d2d1d0cfcecd d5d4d3d2d1d0cfce d6d5d4d3d2d1d0cf d7d6d5d4d3d2d1d0 d8d7d6d5d4d3d2d1 d9d8d7d6d5d4d3d2 dad9d8d7d6d5d4d3 dbdad9d8d7d6d5d4 dcdbdad9d8d7d6d5 dddcdbdad9d8d7d6 dedddcdbdad9d8d7 dfdedddcdbdad9d8 e0dfdedddcdbdad9 e1e0dfdedddcdbda e2e1e0dfdedddcdb e3e2e1e0dfdedddc e4e3e2e1e0dfdedd e5e4e3e2e1e0dfde e6e5e4e3e2e1e0df e7e6e5e4e3e2e1e0 e8e7e6e5e4e3e2e1 e9e8e7e6e5e4e3e2 eae9e8e7e6e5e4e3 ebeae9e8e7e6e5e4 ecebeae9e8e7e6e5 edecebeae9e8e7e6 eeedecebeae9e8e7 efeeedecebeae9e8 f0efeeedecebeae9 f1f0efeeedecebea f2f1f0efeeedeceb f3f2f1f0efeeedec f4f3f2f1f0efeeed f5f4f3f2f1f0efee f6f5f4f3f2f1f0ef f7f6f5f4f3f2f1f0 f8f7f6f5f4f3f2f1 f9f8f7f6f5f4f3f2 faf9f8f7f6f5f4f3 fbfaf9f8f7f6f5f4 fcfbfaf9f8f7f6f5 fdfcfbfaf9f8f7f6 fefdfcfbfaf9f8f7 fffefdfcfbfaf9f8 00fffefdfcfbfaf9 0100fffefdfcfbfa 020100fffefdfcfb 03020100fffefdfc 0403020100fffefd 050403020100fffe 06050403020100ff 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 55 56 57 58 59 5a 5b 5c 5d 5e 5f 60 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f 70 71 72 73 74 75 76 77 78 79 7a 7b 7c 7d 7e 7f 80 81 82 83 84 85 86 87 88 89 8a 8b 8c 8d 8e 8f 90 91 92 93 94 95 96 97 98 99 9a 9b 9c 9d 9e 9f a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 aa ab ac ad ae af b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 ba bb bc bd be bf c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 ca cb cc cd ce cf d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 da db dc dd de df e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 ea eb ec ed ee ef f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd fe ff 0100 0201 0302 0403 0504 0605 0706 0807 0908 0a09 0b0a 0c0b 0d0c 0e0d 0f0e 100f 1110 1211 1312 1413 1514 1615 1716 1817 1918 1a19 1b1a 1c1b 1d1c 1e1d 1f1e 201f 2120 2221 2322 2423 2524 2625 2726 2827 2928 2a29 2b2a 2c2b 2d2c 2e2d 2f2e 302f 3130 3231 3332 3433 3534 3635 3736 3837 3938 3a39 3b3a 3c3b 3d3c 3e3d 3f3e 403f 4140 4241 4342 4443 4544 4645 4746 4847 4948 4a49 4b4a 4c4b 4d4c 4e4d 4f4e 504f 5150 5251 5352 5453 5554 5655 5756 5857 5958 5a59 5b5a 5c5b 5d5c 5e5d 5f5e 605f 6160 6261 6362 6463 6564 6665 6766 6867 6968 6a69 6b6a 6c6b 6d6c 6e6d 6f6e 706f 7170 7271 7372 7473 7574 7675 7776 7877 7978 7a79 7b7a 7c7b 7d7c 7e7d 7f7e 807f 8180 8281 8382 8483 8584 8685 8786 8887 8988 8a89 8b8a 8c8b 8d8c 8e8d 8f8e 908f 9190 9291 9392 9493 9594 9695 9796 9897 9998 9a99 9b9a 9c9b 9d9c 9e9d 9f9e a09f a1a0 a2a1 a3a2 a4a3 a5a4 a6a5 a7a6 a8a7 a9a8 aaa9 abaa acab adac aead afae b0af b1b0 b2b1 b3b2 b4b3 b5b4 b6b5 b7b6 b8b7 b9b8 bab9 bbba bcbb bdbc bebd bfbe c0bf c1c0 c2c1 c3c2 c4c3 c5c4 c6c5 c7c6 c8c7 c9c8 cac9 cbca cccb cdcc cecd cfce d0cf d1d0 d2d1 d3d2 d4d3 d5d4 d6d5 d7d6 d8d7 d9d8 dad9 dbda dcdb dddc dedd dfde e0df e1e0 e2e1 e3e2 e4e3 e5e4 e6e5 e7e6 e8e7 e9e8 eae9 ebea eceb edec eeed efee f0ef f1f0 f2f1 f3f2 f4f3 f5f4 f6f5 f7f6 f8f7 f9f8 faf9 fbfa fcfb fdfc fefd fffe 00ff 03020100 04030201 05040302 06050403 07060504 08070605 09080706 0a090807 0b0a0908 0c0b0a09 0d0c0b0a 0e0d0c0b 0f0e0d0c 100f0e0d 11100f0e 1211100f 13121110 14131211 15141312 16151413 17161514 18171615 19181716 1a191817 1b1a1918 1c1b1a19 1d1c1b1a 1e1d1c1b 1f1e1d1c 201f1e1d 21201f1e 2221201f 23222120 24232221 25242322 26252423 27262524 28272625 29282726 2a292827 2b2a2928 2c2b2a29 2d2c2b2a 2e2d2c2b 2f2e2d2c 302f2e2d 31302f2e 3231302f 33323130 34333231 35343332 36353433 37363534 38373635 39383736 3a393837 3b3a3938 3c3b3a39 3d3c3b3a 3e3d3c3b 3f3e3d3c 403f3e3d 41403f3e 4241403f 43424140 44434241 45444342 46454443 47464544 48474645 49484746 4a494847 4b4a4948 4c4b4a49 4d4c4b4a 4e4d4c4b 4f4e4d4c 504f4e4d 51504f4e 5251504f 53525150 54535251 55545352 56555453 57565554 58575655 59585756 5a595857 5b5a5958 5c5b5a59 5d5c5b5a 5e5d5c5b 5f5e5d5c 605f5e5d 61605f5e 6261605f 63626160 64636261 65646362 66656463 67666564 68676665 69686766 6a696867 6b6a6968 6c6b6a69 6d6c6b6a 6e6d6c6b 6f6e6d6c 706f6e6d 71706f6e 7271706f 73727170 74737271 75747372 76757473 77767574 78777675 79787776 7a797877 7b7a7978 7c7b7a79 7d7c7b7a 7e7d7c7b 7f7e7d7c 807f7e7d 81807f7e 8281807f 83828180 84838281 85848382 86858483 87868584 88878685 89888786 8a898887 8b8a8988 8c8b8a89 8d8c8b8a 8e8d8c8b 8f8e8d8c 908f8e8d 91908f8e 9291908f 93929190 94939291 95949392 96959493 97969594 98979695 99989796 9a999897 9b9a9998 9c9b9a99 9d9c9b9a 9e9d9c9b 9f9e9d9c a09f9e9d a1a09f9e a2a1a09f a3a2a1a0 a4a3a2a1 a5a4a3a2 a6a5a4a3 a7a6a5a4 a8a7a6a5 a9a8a7a6 aaa9a8a7 abaaa9a8 acabaaa9 adacabaa aeadacab afaeadac b0afaead b1b0afae b2b1b0af b3b2b1b0 b4b3b2b1 b5b4b3b2 b6b5b4b3 b7b6b5b4 b8b7b6b5 b9b8b7b6 bab9b8b7 bbbab9b8 bcbbbab9 bdbcbbba bebdbcbb bfbebdbc c0bfbebd c1c0bfbe c2c1c0bf c3c2c1c0 c4c3c2c1 c5c4c3c2 c6c5c4c3 c7c6c5c4 c8c7c6c5 c9c8c7c6 cac9c8c7 cbcac9c8 cccbcac9 cdcccbca cecdcccb cfcecdcc d0cfcecd d1d0cfce d2d1d0cf d3d2d1d0 d4d3d2d1 d5d4d3d2 d6d5d4d3 d7d6d5d4 d8d7d6d5 d9d8d7d6 dad9d8d7 dbdad9d8 dcdbdad9 dddcdbda dedddcdb dfdedddc e0dfdedd e1e0dfde e2e1e0df e3e2e1e0 e4e3e2e1 e5e4e3e2 e6e5e4e3 e7e6e5e4 e8e7e6e5 e9e8e7e6 eae9e8e7 ebeae9e8 ecebeae9 edecebea eeedeceb efeeedec f0efeeed f1f0efee f2f1f0ef f3f2f1f0 f4f3f2f1 f5f4f3f2 f6f5f4f3 f7f6f5f4 f8f7f6f5 f9f8f7f6 faf9f8f7 fbfaf9f8 fcfbfaf9 fdfcfbfa fefdfcfb fffefdfc 00fffefd 0100fffe 020100ff 0706050403020100 0807060504030201 0908070605040302 0a09080706050403 0b0a090807060504 0c0b0a0908070605 0d0c0b0a09080706 0e0d0c0b0a090807 0f0e0d0c0b0a0908 100f0e0d0c0b0a09 11100f0e0d0c0b0a 1211100f0e0d0c0b 131211100f0e0d0c 14131211100f0e0d 1514131211100f0e 161514131211100f 1716151413121110 1817161514131211 1918171615141312 1a19181716151413 1b1a191817161514 1c1b1a1918171615 1d1c1b1a19181716 1e1d1c1b1a191817 1f1e1d1c1b1a1918 201f1e1d1c1b1a19 21201f1e1d1c1b1a 2221201f1e1d1c1b 232221201f1e1d1c 24232221201f1e1d 2524232221201f1e 262524232221201f 2726252423222120 2827262524232221 2928272625242322 2a29282726252423 2b2a292827262524 2c2b2a2928272625 2d2c2b2a29282726 2e2d2c2b2a292827 2f2e2d2c2b2a2928 302f2e2d2c2b2a29 31302f2e2d2c2b2a 3231302f2e2d2c2b 333231302f2e2d2c 34333231302f2e2d 3534333231302f2e 363534333231302f 3736353433323130 3837363534333231 3938373635343332 3a39383736353433 3b3a393837363534 3c3b3a3938373635 3d3c3b3a39383736 3e3d3c3b3a393837 3f3e3d3c3b3a3938 403f3e3d3c3b3a39 41403f3e3d3c3b3a 4241403f3e3d3c3b 434241403f3e3d3c 44434241403f3e3d 4544434241403f3e 464544434241403f 4746454443424140 4847464544434241 4948474645444342 4a49484746454443 4b4a494847464544 4c4b4a4948474645 4d4c4b4a49484746 4e4d4c4b4a494847 4f4e4d4c4b4a4948 504f4e4d4c4b4a49 51504f4e4d4c4b4a 5251504f4e4d4c4b 535251504f4e4d4c 54535251504f4e4d 5554535251504f4e 565554535251504f 5756555453525150 5857565554535251 5958575655545352 5a59585756555453 5b5a595857565554 5c5b5a5958575655 5d5c5b5a59585756 5e5d5c5b5a595857 5f5e5d5c5b5a5958 605f5e5d5c5b5a59 61605f5e5d5c5b5a 6261605f5e5d5c5b 636261605f5e5d5c 64636261605f5e5d 6564636261605f5e 666564636261605f 6766656463626160 6867666564636261 6968676665646362 6a69686766656463 6b6a696867666564 6c6b6a6968676665 6d6c6b6a69686766 6e6d6c6b6a696867 6f6e6d6c6b6a6968 706f6e6d6c6b6a69 71706f6e6d6c6b6a 7271706f6e6d6c6b 737271706f6e6d6c 74737271706f6e6d 7574737271706f6e 767574737271706f 7776757473727170 7877767574737271 7978777675747372 7a79787776757473 7b7a797877767574 7c7b7a7978777675 7d7c7b7a79787776 7e7d7c7b7a797877 7f7e7d7c7b7a7978 807f7e7d7c7b7a79 81807f7e7d7c7b7a 8281807f7e7d7c7b 838281807f7e7d7c 84838281807f7e7d 8584838281807f7e 868584838281807f 8786858483828180 8887868584838281 8988878685848382 8a89888786858483 8b8a898887868584 8c8b8a8988878685 8d8c8b8a89888786 8e8d8c8b8a898887 8f8e8d8c8b8a8988 908f8e8d8c8b8a89 91908f8e8d8c8b8a 9291908f8e8d8c8b 939291908f8e8d8c 94939291908f8e8d 9594939291908f8e 969594939291908f 9796959493929190 9897969594939291 9998979695949392 9a99989796959493 9b9a999897969594 9c9b9a9998979695 9d9c9b9a99989796 9e9d9c9b9a999897 9f9e9d9c9b9a9998 a09f9e9d9c9b9a99 a1a09f9e9d9c9b9a a2a1a09f9e9d9c9b a3a2a1a09f9e9d9c a4a3a2a1a09f9e9d a5a4a3a2a1a09f9e a6a5a4a3a2a1a09f a7a6a5a4a3a2a1a0 a8a7a6a5a4a3a2a1 a9a8a7a6a5a4a3a2 aaa9a8a7a6a5a4a3 abaaa9a8a7a6a5a4 acabaaa9a8a7a6a5 adacabaaa9a8a7a6 aeadacabaaa9a8a7 afaeadacabaaa9a8 b0afaeadacabaaa9 b1b0afaeadacabaa b2b1b0afaeadacab b3b2b1b0afaeadac b4b3b2b1b0afaead b5b4b3b2b1b0afae b6b5b4b3b2b1b0af b7b6b5b4b3b2b1b0 b8b7b6b5b4b3b2b1 b9b8b7b6b5b4b3b2 bab9b8b7b6b5b4b3 bbbab9b8b7b6b5b4 bcbbbab9b8b7b6b5 bdbcbbbab9b8b7b6 bebdbcbbbab9b8b7 bfbebdbcbbbab9b8 c0bfbebdbcbbbab9 c1c0bfbebdbcbbba c2c1c0bfbebdbcbb c3c2c1c0bfbebdbc c4c3c2c1c0bfbebd c5c4c3c2c1c0bfbe c6c5c4c3c2c1c0bf c7c6c5c4c3c2c1c0 c8c7c6c5c4c3c2c1 c9c8c7c6c5c4c3c2 cac9c8c7c6c5c4c3 cbcac9c8c7c6c5c4 cccbcac9c8c7c6c5 cdcccbcac9c8c7c6 cecdcccbcac9c8c7 cfcecdcccbcac9c8 d0cfcecdcccbcac9 d1d0cfcecdcccbca d2d1d0cfcecdcccb d3d2d1d0cfcecdcc d4d3d2d1d0cfcecd d5d4d3d2d1d0cfce d6d5d4d3d2d1d0cf d7d6d5d4d3d2d1d0 d8d7d6d5d4d3d2d1 d9d8d7d6d5d4d3d2 dad9d8d7d6d5d4d3 dbdad9d8d7d6d5d4 dcdbdad9d8d7d6d5 dddcdbdad9d8d7d6 dedddcdbdad9d8d7 dfdedddcdbdad9d8 e0dfdedddcdbdad9 e1e0dfdedddcdbda e2e1e0dfdedddcdb e3e2e1e0dfdedddc e4e3e2e1e0dfdedd e5e4e3e2e1e0dfde e6e5e4e3e2e1e0df e7e6e5e4e3e2e1e0 e8e7e6e5e4e3e2e1 e9e8e7e6e5e4e3e2 eae9e8e7e6e5e4e3 ebeae9e8e7e6e5e4 ecebeae9e8e7e6e5 edecebeae9e8e7e6 eeedecebeae9e8e7 efeeedecebeae9e8 f0efeeedecebeae9 f1f0efeeedecebea f2f1f0efeeedeceb f3f2f1f0efeeedec f4f3f2f1f0efeeed f5f4f3f2f1f0efee f6f5f4f3f2f1f0ef f7f6f5f4f3f2f1f0 f8f7f6f5f4f3f2f1 f9f8f7f6f5f4f3f2 faf9f8f7f6f5f4f3 fbfaf9f8f7f6f5f4 fcfbfaf9f8f7f6f5 fdfcfbfaf9f8f7f6 fefdfcfbfaf9f8f7 fffefdfcfbfaf9f8 00fffefdfcfbfaf9 0100fffefdfcfbfa 020100fffefdfcfb 03020100fffefdfc 0403020100fffefd 050403020100fffe 06050403020100ff verilator-5.042/test_regress/t/t_dpi_export_context2_bad.out0000644000542200017500000000054415101701376024756 0ustar mahmoudyfreeshell%Warning: DPI C Function called by Verilog DPI import with missing 'context' keyword. %Warning: DPI C Function called by Verilog DPI import with missing 'context' keyword. %Error: unknown:0: Testbench C called 'dpix_task' but scope wasn't set, perhaps due to dpi import call without 'context', or missing svSetScope. See IEEE 1800-2023 35.5.3. Aborting... verilator-5.042/test_regress/t/t_constraint_unsup.py0000755000542200017500000000077315101701376023413 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_flag_nofile_bad.out0000644000542200017500000000032315101701376023213 0ustar mahmoudyfreeshell%Error: verilator: No Input Verilog file specified on command line, see verilator --help for more information ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. verilator-5.042/test_regress/t/t_flag_xinitial_0.py0000755000542200017500000000114015101701376023013 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(verilator_flags2=["--x-initial 0"]) test.execute() test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + "___024root__Slow.cpp", r'VL_RAND_RESET') test.passes() verilator-5.042/test_regress/t/t_runflag_errorlimit_bad.py0000755000542200017500000000112015101701376024474 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile() test.execute(all_run_flags=["+verilator+error+limit+3"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_std_randomize_unsup_bad.py0000755000542200017500000000076615101701376024701 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_sys_readmem_assoc_bad.v0000644000542200017500000000071315101701376024107 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg [5:0] assoc_bad_key[real]; real assoc_bad_value[int]; initial begin $readmemb("not", assoc_bad_key); $readmemb("not", assoc_bad_value); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_interface_param_dependency.py0000755000542200017500000000075015101701376025306 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Test interface parameter dependency resolution # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios("simulator_st") test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_generic_mod_param.py0000755000542200017500000000077115101701376025446 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--timing']) test.execute() test.passes() verilator-5.042/test_regress/t/t_class_method_str_literal.v0000644000542200017500000000215615101701376024655 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; class uvm_reg; function int get_1; return 1; endfunction function bit get_true; return 1; endfunction function string get_string; if (get_1() == 1) begin return get_true() ? "user backdoor" : "DPI backdoor"; end else begin return ""; end endfunction endclass class T; function automatic string return_str(input string a_string); return a_string; endfunction static function automatic string static_return_str(input string a_string); return a_string; endfunction endclass initial begin T t_c = new; uvm_reg u_r = new; if (u_r.get_string() != "user backdoor") $stop; if (t_c.return_str("A") != "A") $stop; if (t_c.static_return_str("B") != "B") $stop; if (T::static_return_str("C") != "C") $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_mod_topmodule_nest.py0000755000542200017500000000100115101701376023656 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--top-module top"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_fork_output_arg.py0000755000542200017500000000077115101701376023205 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_sys_system.v0000644000542200017500000000154715101701376022031 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; integer i; string s; initial begin `ifndef VERILATOR `ifndef VCS `ifndef NC $system(); // Legal per spec, but not supported everywhere and nonsensical `endif `endif `endif $system("ls"); // IData $system("exit 0"); // QData $system("echo hello"); // WDATA `ifndef VCS i = $system("exit 0"); if (i!==0) $stop; i = $system("exit 10"); if (i!==10) $stop; i = $system("exit 20"); // Wide if (i!==20) $stop; s = "exit 10"; i = $system(s); // String if (i!==10) $stop; `endif $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_preproc_eof2_bad.v0000644000542200017500000000034515101701376022775 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define FOO(a, verilator-5.042/test_regress/t/t_var_nonamebegin.v0000644000542200017500000000321515101701376022733 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk, reset_l ); input clk; input reset_l; reg inmod; generate if (1) begin // Traces as genblk1.ingen integer ingen; initial $display("ingen: {mod}.genblk1 %m"); end endgenerate integer rawmod; initial begin begin integer upa; begin : d3nameda // %m='.d3nameda' var=_unnamed#.d3nameda.b1 integer d3a; $display("d3a: {mod}.d3nameda %m"); end end end initial begin integer b2; $display("b2: {mod} %m"); begin : b3named integer b3n; $display("b3n: {mod}.b3named: %m"); end if (1) begin integer b3; $display("b3: {mod} %m"); if (1) begin begin begin begin integer b4; $display("b4: {mod} %m"); end end end end else begin integer b4; $display("bb %m"); end end else begin integer b4; $display("b4 %m"); end tsk; $write("*-* All Finished *-*\n"); $finish; end task automatic tsk; integer t1; $display("t1 {mod}.tsk %m"); begin integer t2; $display("t2 {mod}.tsk %m"); end endtask endmodule verilator-5.042/test_regress/t/t_const_string_func.v0000644000542200017500000000113515101701376023327 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: constant string functions // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2023 by Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (); function automatic string foo_func(); foo_func = "FOO"; foo_func = $sformatf("%sBAR", foo_func); for (int i = 0; i < 4; i++) foo_func = $sformatf("%s%0d", foo_func, i); endfunction localparam string the_foo = foo_func(); initial begin if (the_foo != "FOOBAR0123") $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_waiveroutput.out0000644000542200017500000000067415101701376022727 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator output: Waivers generated with --waiver-output `verilator_config // Below are suggested waivers. You have three options: // 1. Fix the reason for the linter warning in the Verilog sources // 2. Keep the waiver permanently if you are sure it is okay // 3. Keep the waiver temporarily to suppress the output // lint_off -rule UNUSEDSIGNAL -file "*t/t_waiveroutput.v" -match "Signal is not used: 'width_warn'*" verilator-5.042/test_regress/t/t_class_module.v0000644000542200017500000000163715101701376022261 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; class Cls; class Inner; int imemberinnera; int imemberinnerb; endclass int imembera; int imemberb; Inner innermemberc; endclass : Cls class Dead; endclass initial begin Cls c; if (c != null) $stop; c = new; if (c.innermemberc != null) $stop; c.innermemberc = new; c.imembera = 10; c.imemberb = 20; c.innermemberc.imemberinnera = 30; c.innermemberc.imemberinnerb = 40; if (c.imembera != 10) $stop; if (c.imemberb != 20) $stop; if (c.innermemberc.imemberinnera != 30) $stop; if (c.innermemberc.imemberinnerb != 40) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_stacktrace.py0000755000542200017500000000073415101701376022116 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_enum_bad_cell.py0000755000542200017500000000107515101701376022542 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["--lint-only -Wwarn-VARHIDDEN"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_cmpconst_bad.py0000755000542200017500000000076615101701376023461 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_randomize_rand_mode_constr.py0000755000542200017500000000104615101701376025357 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_jumps_uninit_destructor_call.v0000644000542200017500000000250215101701376025574 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class Foo; string arra[2]; string arrb[string]; function new(); arra = '{"baz", "boo"}; arrb = '{"baz": "inga!", "boo": "..."}; endfunction task automatic return_before_fork(bit b); if (b) begin // This is going to translate to a `goto` statement. return; end // This will instantiate a `VlForkSync` object (local to the call, as we are under a class) fork #10 $display("forked process"); join // This is where we jump to from the aforementioned goto. If we don't wrap the `VlForkSync` // object in a scope that ends before that point, we will end up calling its destructor // without having it initialized first. endtask task automatic return_before_select(bit b, int idx); if (b) return; // goto // This will create two temporary strings used to select from `arrb` and assign to it. arrb[arra[idx]] = #10 "yah!"; // jump here endtask endclass module t(); initial begin Foo foo; foo = new; foo.return_before_fork(1'b1); foo.return_before_select(1'b1, 1); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_flag_quiet_stats2.py0000755000542200017500000000121115101701376023401 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_flag_quiet_stats.v" test.compile(verilator_flags2=['--quiet'], verilator_make_gcc=False, logfile=test.run_log_filename) test.file_grep_not(test.compile_log_filename, r'V e r i l a t') test.passes() verilator-5.042/test_regress/t/t_reloop_local.py0000755000542200017500000000077115101701376022445 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--assert']) test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_no_top_name.v0000644000542200017500000000072015101701376023253 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" module t; wire a = 0; initial begin $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); $dumpvars; $write("*-* All Finished *-*\n"); $finish; end endmodule module another_top; wire b = 0; endmodule verilator-5.042/test_regress/t/t_order_b.v0000644000542200017500000000071315101701376021215 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t_order_b (/*AUTOARG*/ // Outputs o_subfrom_clk_lev2, // Inputs m_from_clk_lev1_r ); input [7:0] m_from_clk_lev1_r; output [7:0] o_subfrom_clk_lev2; wire [7:0] o_subfrom_clk_lev2 = m_from_clk_lev1_r; endmodule verilator-5.042/test_regress/t/t_xml_begin_hier.v0000644000542200017500000000134415101701376022555 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Risto Pejasinovic. // SPDX-License-Identifier: CC0-1.0 module submod2 (); endmodule module submod #( )(); if(1) begin : submod_gen wire l1_sig; if(1) begin : nested_gen submod2 submod_nested(); end submod2 submod_l1(); end submod2 submod_l0(); endmodule module test( ); genvar N; generate for(N=0; N<2; N=N+1) begin : FOR_GENERATE submod submod_for(); if(1) begin submod submod_2(); end submod submod_3(); end endgenerate endmodule verilator-5.042/test_regress/t/t_class_null_bad.py0000755000542200017500000000101415101701376022727 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_inst_missing_dot_bad.out0000644000542200017500000000100015101701376024313 0ustar mahmoudyfreeshell%Error: t/t_inst_missing_dot_bad.v:9:22: Dotted reference to instance that refers to missing module/interface: 'missing' 9 | $display("a=", missing.a); | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_inst_missing_dot_bad.v:9:30: Can't find definition of 'a' in dotted variable/method: 'missing.a' 9 | $display("a=", missing.a); | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_param_default.v0000644000542200017500000000062215101701376022404 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module m #(parameter int Foo); endmodule module t; m #(10) foo(); initial begin if (foo.Foo != 10) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_const_bad.py0000755000542200017500000000076615101701376021733 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_trace_cat_reopen__0100.out0000644000542200017500000000503315101701376024237 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $var wire 1 # clk $end $scope module t $end $var wire 1 # clk $end $var wire 32 $ cyc [31:0] $end $upscope $end $upscope $end $enddefinitions $end #100 1# b00000000000000000000000000110010 $ #101 0# #102 1# b00000000000000000000000000110011 $ #103 0# #104 1# b00000000000000000000000000110100 $ #105 0# #106 1# b00000000000000000000000000110101 $ #107 0# #108 1# b00000000000000000000000000110110 $ #109 0# #110 1# b00000000000000000000000000110111 $ #111 0# #112 1# b00000000000000000000000000111000 $ #113 0# #114 1# b00000000000000000000000000111001 $ #115 0# #116 1# b00000000000000000000000000111010 $ #117 0# #118 1# b00000000000000000000000000111011 $ #119 0# #120 1# b00000000000000000000000000111100 $ #121 0# #122 1# b00000000000000000000000000111101 $ #123 0# #124 1# b00000000000000000000000000111110 $ #125 0# #126 1# b00000000000000000000000000111111 $ #127 0# #128 1# b00000000000000000000000001000000 $ #129 0# #130 1# b00000000000000000000000001000001 $ #131 0# #132 1# b00000000000000000000000001000010 $ #133 0# #134 1# b00000000000000000000000001000011 $ #135 0# #136 1# b00000000000000000000000001000100 $ #137 0# #138 1# b00000000000000000000000001000101 $ #139 0# #140 1# b00000000000000000000000001000110 $ #141 0# #142 1# b00000000000000000000000001000111 $ #143 0# #144 1# b00000000000000000000000001001000 $ #145 0# #146 1# b00000000000000000000000001001001 $ #147 0# #148 1# b00000000000000000000000001001010 $ #149 0# #150 1# b00000000000000000000000001001011 $ #151 0# #152 1# b00000000000000000000000001001100 $ #153 0# #154 1# b00000000000000000000000001001101 $ #155 0# #156 1# b00000000000000000000000001001110 $ #157 0# #158 1# b00000000000000000000000001001111 $ #159 0# #160 1# b00000000000000000000000001010000 $ #161 0# #162 1# b00000000000000000000000001010001 $ #163 0# #164 1# b00000000000000000000000001010010 $ #165 0# #166 1# b00000000000000000000000001010011 $ #167 0# #168 1# b00000000000000000000000001010100 $ #169 0# #170 1# b00000000000000000000000001010101 $ #171 0# #172 1# b00000000000000000000000001010110 $ #173 0# #174 1# b00000000000000000000000001010111 $ #175 0# #176 1# b00000000000000000000000001011000 $ #177 0# #178 1# b00000000000000000000000001011001 $ #179 0# #180 1# b00000000000000000000000001011010 $ #181 0# #182 1# b00000000000000000000000001011011 $ #183 0# #184 1# b00000000000000000000000001011100 $ #185 0# #186 1# b00000000000000000000000001011101 $ #187 0# #188 1# b00000000000000000000000001011110 $ #189 0# verilator-5.042/test_regress/t/t_implements_nested_bad.py0000755000542200017500000000076615101701376024324 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_gen_alw.py0000755000542200017500000000073415101701376021406 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_typedef_fwd.py0000755000542200017500000000070615101701376022271 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.042/test_regress/t/t_class_extends_colon.v0000644000542200017500000000117315101701376023633 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface class Icempty; endclass : Icempty package Pkg; class Icls1 #(parameter PARAM = 12); localparam LP1 = 1; function int getParam(); return PARAM; endfunction endclass endpackage class Cls12 extends Pkg::Icls1; endclass module t; Cls12 cp12; initial begin cp12 = new; if (cp12.getParam() != 12) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_mailbox_concurrent.py0000755000542200017500000000103515101701376023662 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_init_concat.py0000755000542200017500000000073415101701376022264 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_dpi_arg_inout_unpack__Dpi.out0000644000542200017500000003126015101701376025263 0ustar mahmoudyfreeshell// Verilated -*- C++ -*- // DESCRIPTION: Verilator output: Prototypes for DPI import and export functions. // // Verilator includes this file in all generated .cpp files that use DPI functions. // Manually include this file where DPI .c import functions are declared to ensure // the C functions match the expectations of the DPI imports. #ifndef VERILATED_VT_DPI_ARG_INOUT_UNPACK__DPI_H_ #define VERILATED_VT_DPI_ARG_INOUT_UNPACK__DPI_H_ // guard #include "svdpi.h" #ifdef __cplusplus extern "C" { #endif // DPI EXPORTS extern void e_bit121_0d(svBitVecVal* val); extern void e_bit121_1d(svBitVecVal* val); extern void e_bit121_1d1(svBitVecVal* val); extern void e_bit121_2d(svBitVecVal* val); extern void e_bit121_2d1(svBitVecVal* val); extern void e_bit121_3d(svBitVecVal* val); extern void e_bit121_3d1(svBitVecVal* val); extern void e_bit1_0d(svBit* val); extern void e_bit1_1d(svBit* val); extern void e_bit1_1d1(svBit* val); extern void e_bit1_2d(svBit* val); extern void e_bit1_2d1(svBit* val); extern void e_bit1_3d(svBit* val); extern void e_bit1_3d1(svBit* val); extern void e_bit7_0d(svBitVecVal* val); extern void e_bit7_1d(svBitVecVal* val); extern void e_bit7_1d1(svBitVecVal* val); extern void e_bit7_2d(svBitVecVal* val); extern void e_bit7_2d1(svBitVecVal* val); extern void e_bit7_3d(svBitVecVal* val); extern void e_bit7_3d1(svBitVecVal* val); extern void e_byte_0d(char* val); extern void e_byte_1d(char* val); extern void e_byte_1d1(char* val); extern void e_byte_2d(char* val); extern void e_byte_2d1(char* val); extern void e_byte_3d(char* val); extern void e_byte_3d1(char* val); extern void e_byte_unsigned_0d(unsigned char* val); extern void e_byte_unsigned_1d(unsigned char* val); extern void e_byte_unsigned_1d1(unsigned char* val); extern void e_byte_unsigned_2d(unsigned char* val); extern void e_byte_unsigned_2d1(unsigned char* val); extern void e_byte_unsigned_3d(unsigned char* val); extern void e_byte_unsigned_3d1(unsigned char* val); extern void e_chandle_0d(void** val); extern void e_chandle_1d(void** val); extern void e_chandle_1d1(void** val); extern void e_chandle_2d(void** val); extern void e_chandle_2d1(void** val); extern void e_chandle_3d(void** val); extern void e_chandle_3d1(void** val); extern void e_int_0d(int* val); extern void e_int_1d(int* val); extern void e_int_1d1(int* val); extern void e_int_2d(int* val); extern void e_int_2d1(int* val); extern void e_int_3d(int* val); extern void e_int_3d1(int* val); extern void e_int_unsigned_0d(unsigned int* val); extern void e_int_unsigned_1d(unsigned int* val); extern void e_int_unsigned_1d1(unsigned int* val); extern void e_int_unsigned_2d(unsigned int* val); extern void e_int_unsigned_2d1(unsigned int* val); extern void e_int_unsigned_3d(unsigned int* val); extern void e_int_unsigned_3d1(unsigned int* val); extern void e_integer_0d(svLogicVecVal* val); extern void e_integer_1d(svLogicVecVal* val); extern void e_integer_1d1(svLogicVecVal* val); extern void e_integer_2d(svLogicVecVal* val); extern void e_integer_2d1(svLogicVecVal* val); extern void e_integer_3d(svLogicVecVal* val); extern void e_integer_3d1(svLogicVecVal* val); extern void e_logic121_0d(svLogicVecVal* val); extern void e_logic121_1d(svLogicVecVal* val); extern void e_logic121_1d1(svLogicVecVal* val); extern void e_logic121_2d(svLogicVecVal* val); extern void e_logic121_2d1(svLogicVecVal* val); extern void e_logic121_3d(svLogicVecVal* val); extern void e_logic121_3d1(svLogicVecVal* val); extern void e_logic1_0d(svLogic* val); extern void e_logic1_1d(svLogic* val); extern void e_logic1_1d1(svLogic* val); extern void e_logic1_2d(svLogic* val); extern void e_logic1_2d1(svLogic* val); extern void e_logic1_3d(svLogic* val); extern void e_logic1_3d1(svLogic* val); extern void e_logic7_0d(svLogicVecVal* val); extern void e_logic7_1d(svLogicVecVal* val); extern void e_logic7_1d1(svLogicVecVal* val); extern void e_logic7_2d(svLogicVecVal* val); extern void e_logic7_2d1(svLogicVecVal* val); extern void e_logic7_3d(svLogicVecVal* val); extern void e_logic7_3d1(svLogicVecVal* val); extern void e_longint_0d(long long* val); extern void e_longint_1d(long long* val); extern void e_longint_1d1(long long* val); extern void e_longint_2d(long long* val); extern void e_longint_2d1(long long* val); extern void e_longint_3d(long long* val); extern void e_longint_3d1(long long* val); extern void e_longint_unsigned_0d(unsigned long long* val); extern void e_longint_unsigned_1d(unsigned long long* val); extern void e_longint_unsigned_1d1(unsigned long long* val); extern void e_longint_unsigned_2d(unsigned long long* val); extern void e_longint_unsigned_2d1(unsigned long long* val); extern void e_longint_unsigned_3d(unsigned long long* val); extern void e_longint_unsigned_3d1(unsigned long long* val); extern void e_pack_struct_0d(svLogicVecVal* val); extern void e_pack_struct_1d(svLogicVecVal* val); extern void e_pack_struct_1d1(svLogicVecVal* val); extern void e_pack_struct_2d(svLogicVecVal* val); extern void e_pack_struct_2d1(svLogicVecVal* val); extern void e_pack_struct_3d(svLogicVecVal* val); extern void e_pack_struct_3d1(svLogicVecVal* val); extern void e_real_0d(double* val); extern void e_real_1d(double* val); extern void e_real_1d1(double* val); extern void e_real_2d(double* val); extern void e_real_2d1(double* val); extern void e_real_3d(double* val); extern void e_real_3d1(double* val); extern void e_shortint_0d(short* val); extern void e_shortint_1d(short* val); extern void e_shortint_1d1(short* val); extern void e_shortint_2d(short* val); extern void e_shortint_2d1(short* val); extern void e_shortint_3d(short* val); extern void e_shortint_3d1(short* val); extern void e_shortint_unsigned_0d(unsigned short* val); extern void e_shortint_unsigned_1d(unsigned short* val); extern void e_shortint_unsigned_1d1(unsigned short* val); extern void e_shortint_unsigned_2d(unsigned short* val); extern void e_shortint_unsigned_2d1(unsigned short* val); extern void e_shortint_unsigned_3d(unsigned short* val); extern void e_shortint_unsigned_3d1(unsigned short* val); extern void e_string_0d(const char** val); extern void e_string_1d(const char** val); extern void e_string_1d1(const char** val); extern void e_string_2d(const char** val); extern void e_string_2d1(const char** val); extern void e_string_3d(const char** val); extern void e_string_3d1(const char** val); extern void e_time_0d(svLogicVecVal* val); extern void e_time_1d(svLogicVecVal* val); extern void e_time_1d1(svLogicVecVal* val); extern void e_time_2d(svLogicVecVal* val); extern void e_time_2d1(svLogicVecVal* val); extern void e_time_3d(svLogicVecVal* val); extern void e_time_3d1(svLogicVecVal* val); // DPI IMPORTS extern void check_exports(); extern void* get_non_null(); extern void i_bit121_0d(svBitVecVal* val); extern void i_bit121_1d(svBitVecVal* val); extern void i_bit121_1d1(svBitVecVal* val); extern void i_bit121_2d(svBitVecVal* val); extern void i_bit121_2d1(svBitVecVal* val); extern void i_bit121_3d(svBitVecVal* val); extern void i_bit121_3d1(svBitVecVal* val); extern void i_bit1_0d(svBit* val); extern void i_bit1_1d(svBit* val); extern void i_bit1_1d1(svBit* val); extern void i_bit1_2d(svBit* val); extern void i_bit1_2d1(svBit* val); extern void i_bit1_3d(svBit* val); extern void i_bit1_3d1(svBit* val); extern void i_bit7_0d(svBitVecVal* val); extern void i_bit7_1d(svBitVecVal* val); extern void i_bit7_1d1(svBitVecVal* val); extern void i_bit7_2d(svBitVecVal* val); extern void i_bit7_2d1(svBitVecVal* val); extern void i_bit7_3d(svBitVecVal* val); extern void i_bit7_3d1(svBitVecVal* val); extern void i_byte_0d(char* val); extern void i_byte_1d(char* val); extern void i_byte_1d1(char* val); extern void i_byte_2d(char* val); extern void i_byte_2d1(char* val); extern void i_byte_3d(char* val); extern void i_byte_3d1(char* val); extern void i_byte_unsigned_0d(unsigned char* val); extern void i_byte_unsigned_1d(unsigned char* val); extern void i_byte_unsigned_1d1(unsigned char* val); extern void i_byte_unsigned_2d(unsigned char* val); extern void i_byte_unsigned_2d1(unsigned char* val); extern void i_byte_unsigned_3d(unsigned char* val); extern void i_byte_unsigned_3d1(unsigned char* val); extern void i_chandle_0d(void** val); extern void i_chandle_1d(void** val); extern void i_chandle_1d1(void** val); extern void i_chandle_2d(void** val); extern void i_chandle_2d1(void** val); extern void i_chandle_3d(void** val); extern void i_chandle_3d1(void** val); extern void i_int_0d(int* val); extern void i_int_1d(int* val); extern void i_int_1d1(int* val); extern void i_int_2d(int* val); extern void i_int_2d1(int* val); extern void i_int_3d(int* val); extern void i_int_3d1(int* val); extern void i_int_unsigned_0d(unsigned int* val); extern void i_int_unsigned_1d(unsigned int* val); extern void i_int_unsigned_1d1(unsigned int* val); extern void i_int_unsigned_2d(unsigned int* val); extern void i_int_unsigned_2d1(unsigned int* val); extern void i_int_unsigned_3d(unsigned int* val); extern void i_int_unsigned_3d1(unsigned int* val); extern void i_integer_0d(svLogicVecVal* val); extern void i_integer_1d(svLogicVecVal* val); extern void i_integer_1d1(svLogicVecVal* val); extern void i_integer_2d(svLogicVecVal* val); extern void i_integer_2d1(svLogicVecVal* val); extern void i_integer_3d(svLogicVecVal* val); extern void i_integer_3d1(svLogicVecVal* val); extern void i_logic121_0d(svLogicVecVal* val); extern void i_logic121_1d(svLogicVecVal* val); extern void i_logic121_1d1(svLogicVecVal* val); extern void i_logic121_2d(svLogicVecVal* val); extern void i_logic121_2d1(svLogicVecVal* val); extern void i_logic121_3d(svLogicVecVal* val); extern void i_logic121_3d1(svLogicVecVal* val); extern void i_logic1_0d(svLogic* val); extern void i_logic1_1d(svLogic* val); extern void i_logic1_1d1(svLogic* val); extern void i_logic1_2d(svLogic* val); extern void i_logic1_2d1(svLogic* val); extern void i_logic1_3d(svLogic* val); extern void i_logic1_3d1(svLogic* val); extern void i_logic7_0d(svLogicVecVal* val); extern void i_logic7_1d(svLogicVecVal* val); extern void i_logic7_1d1(svLogicVecVal* val); extern void i_logic7_2d(svLogicVecVal* val); extern void i_logic7_2d1(svLogicVecVal* val); extern void i_logic7_3d(svLogicVecVal* val); extern void i_logic7_3d1(svLogicVecVal* val); extern void i_longint_0d(long long* val); extern void i_longint_1d(long long* val); extern void i_longint_1d1(long long* val); extern void i_longint_2d(long long* val); extern void i_longint_2d1(long long* val); extern void i_longint_3d(long long* val); extern void i_longint_3d1(long long* val); extern void i_longint_unsigned_0d(unsigned long long* val); extern void i_longint_unsigned_1d(unsigned long long* val); extern void i_longint_unsigned_1d1(unsigned long long* val); extern void i_longint_unsigned_2d(unsigned long long* val); extern void i_longint_unsigned_2d1(unsigned long long* val); extern void i_longint_unsigned_3d(unsigned long long* val); extern void i_longint_unsigned_3d1(unsigned long long* val); extern void i_pack_struct_0d(svLogicVecVal* val); extern void i_pack_struct_1d(svLogicVecVal* val); extern void i_pack_struct_1d1(svLogicVecVal* val); extern void i_pack_struct_2d(svLogicVecVal* val); extern void i_pack_struct_2d1(svLogicVecVal* val); extern void i_pack_struct_3d(svLogicVecVal* val); extern void i_pack_struct_3d1(svLogicVecVal* val); extern void i_real_0d(double* val); extern void i_real_1d(double* val); extern void i_real_1d1(double* val); extern void i_real_2d(double* val); extern void i_real_2d1(double* val); extern void i_real_3d(double* val); extern void i_real_3d1(double* val); extern void i_shortint_0d(short* val); extern void i_shortint_1d(short* val); extern void i_shortint_1d1(short* val); extern void i_shortint_2d(short* val); extern void i_shortint_2d1(short* val); extern void i_shortint_3d(short* val); extern void i_shortint_3d1(short* val); extern void i_shortint_unsigned_0d(unsigned short* val); extern void i_shortint_unsigned_1d(unsigned short* val); extern void i_shortint_unsigned_1d1(unsigned short* val); extern void i_shortint_unsigned_2d(unsigned short* val); extern void i_shortint_unsigned_2d1(unsigned short* val); extern void i_shortint_unsigned_3d(unsigned short* val); extern void i_shortint_unsigned_3d1(unsigned short* val); extern void i_string_0d(const char** val); extern void i_string_1d(const char** val); extern void i_string_1d1(const char** val); extern void i_string_2d(const char** val); extern void i_string_2d1(const char** val); extern void i_string_3d(const char** val); extern void i_string_3d1(const char** val); extern void i_time_0d(svLogicVecVal* val); extern void i_time_1d(svLogicVecVal* val); extern void i_time_1d1(svLogicVecVal* val); extern void i_time_2d(svLogicVecVal* val); extern void i_time_2d1(svLogicVecVal* val); extern void i_time_3d(svLogicVecVal* val); extern void i_time_3d1(svLogicVecVal* val); #ifdef __cplusplus } #endif #endif // guard verilator-5.042/test_regress/t/t_flag_invalid2_bad.out0000644000542200017500000000021315101701376023445 0ustar mahmoudyfreeshell%Error: Invalid option: +invalid-plus ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. verilator-5.042/test_regress/t/t_enum_bad_wrap.out0000644000542200017500000000053215101701376022745 0ustar mahmoudyfreeshell%Error: t/t_enum_bad_wrap.v:11:19: Enum value illegally wrapped around (IEEE 1800-2023 6.19) : ... note: In instance 't' 11 | WRAPPED | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_var_xref_gen.py0000755000542200017500000000075015101701376022435 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["--debug-check"]) test.passes() verilator-5.042/test_regress/t/t_class_super_new_bad_nfirst.out0000644000542200017500000000067015101701376025534 0ustar mahmoudyfreeshell%Error: t/t_class_super_new_bad_nfirst.v:18:13: 'super.new' not first statement in new function (IEEE 1800-2023 8.15) 18 | super.new(imemberc); | ^~~ t/t_class_super_new_bad_nfirst.v:17:16: ... Location of earlier statement 17 | imemberc = 10; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_param_slice.py0000755000542200017500000000101515101701376022242 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Test constant parameter slicing of unpacked arrays (issue #6257) # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_property_untyped_unsup.py0000755000542200017500000000102215101701376024647 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert'], fails=True) test.passes() verilator-5.042/test_regress/t/t_interface_array2.py0000755000542200017500000000100315101701376023200 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(timing_loop=True, v_flags2=["--timing"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_gen13.py0000755000542200017500000000073415101701376022727 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_randomize_queue_wide.v0000644000542200017500000000150315101701376024003 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Foo; rand bit [65:0] m_wideQueue[$]; function new; m_wideQueue = '{3{0}}; endfunction constraint int_queue_c { m_wideQueue[0] == 0; m_wideQueue[1] == 1; m_wideQueue[2] == 2; } function void self_check(); if (m_wideQueue[0] != 0) $stop; if (m_wideQueue[1] != 1) $stop; if (m_wideQueue[2] != 2) $stop; endfunction endclass module t; int success; initial begin Foo foo = new; success = foo.randomize(); if (success != 1) $stop; foo.self_check(); $display("Queue: %p", foo.m_wideQueue); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_compiler_include.h0000644000542200017500000000117315101701376023101 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2024 by Antmicro. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // no header guards to check if included once in pch file static inline int ext_equal(int actual, int expected) { return actual == expected; } verilator-5.042/test_regress/t/t_timescale_default.v0000644000542200017500000000071515101701376023255 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under The Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Intentionally no timescale here, nor in driver file module t; initial begin // Unspecified, but general consensus is 1s is default timeunit $printtimescale; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_func_bad_width.v0000644000542200017500000000074215101701376022543 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg [3:0] out; reg [38:0] in; initial begin in = 39'h0; out = MUX (in); $write("bad widths %x", out); end function [31:0] MUX; input [39:0] XX ; begin MUX = XX[39:8]; end endfunction endmodule verilator-5.042/test_regress/t/t_forceable_var_vlt_trace.py0000755000542200017500000000155415101701376024630 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.pli_filename = "t/t_forceable_var.cpp" test.top_filename = "t/t_forceable_var.v" test.golden_filename = "t/t_forceable_var_trace.vcd.out" test.compile(make_top_shell=False, make_main=False, verilator_flags2=[ '--exe', '--trace-vcd', test.pli_filename, test.t_dir + "/t_forceable_var.vlt" ]) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_timing_fork_join.py0000755000542200017500000000103515101701376023314 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_probdist.py0000755000542200017500000000073415101701376021620 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_randomize.py0000755000542200017500000000076315101701376021764 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dpi_name_bad.v0000644000542200017500000000105015101701376022156 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (); import "DPI-C" function int \badly.named (int i); export "DPI-C" function \badly.expt ; function int \badly.expt ; return 0; endfunction initial begin $stop; end endmodule verilator-5.042/test_regress/t/t_export_packed_struct.py0000755000542200017500000000113015101701376024215 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename, "-Wno-SYMRSVDWORD"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_hier_block1_bad.py0000755000542200017500000000103015101701376022750 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, verilator_flags2=['--hierarchical'], expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_flag_incdir.py0000755000542200017500000000076615101701376022240 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=['+incdir+ignore1+t/tsub+ignore2']) test.passes() verilator-5.042/test_regress/t/t_flag_csplit_eval.v0000644000542200017500000000153215101701376023077 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs cnt0, cnt1, // Inputs clk, clk1 ); input clk; input clk1; output int cnt0; output int cnt1; always @ (posedge clk) cnt0 <= cnt0 + 1; always @ (posedge clk1) cnt1 <= cnt1 + 1; final if (cnt0 == 0) $stop; final if (cnt1 != 0) $stop; // Some dummy statements to make the code larger generate genvar i; for (i = 0 ; i < 100; i = i + 1) begin always @(posedge clk) $c("/*", i, "*/"); end endgenerate always_comb begin if (cnt0==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_wrapper_clone.v0000644000542200017500000000146015101701376022441 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module for prepareClone/atClone APIs // // This model counts from 0 to 8. It forks a child process (in C++) at 6 // and waits for the child to simulate and exit for resumption (of the parent). // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2023 by Yinan Xu. // SPDX-License-Identifier: CC0-1.0 module top( input clock, input reset, input is_parent, output do_clone ); reg [3:0] counter; assign do_clone = counter == 4'h6; always @(posedge clock) begin if (reset) begin counter <= 4'h0; end else begin counter <= counter + 4'h1; $write("counter = %d\n", counter); end if (counter[3]) begin if (is_parent) begin $write("*-* All Finished *-*\n"); end $finish(0); end end endmodule verilator-5.042/test_regress/t/t_queue_method.v0000644000542200017500000001676415101701376022302 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); class Cls; int x; function new(int a); x = a; endfunction endclass module t; typedef struct packed { int x, y; } point; typedef struct packed { point p; int z; } point_3d; initial begin int q[$]; int qe[$]; // Empty int qv[$]; // Value returns int qvunused[$]; // Value returns (unused) int qi[$]; // Index returns int i; bit b; string string_q[$]; string string_qv[$]; point_3d points_q[$]; // Same as q and qv, but complex value type point_3d points_qv[$]; Cls cls; Cls cls_q[$]; Cls cls_qv[$]; points_q.push_back(point_3d'{point'{1, 2}, 3}); points_q.push_back(point_3d'{point'{2, 3}, 5}); points_q.push_back(point_3d'{point'{1, 4}, 5}); cls = new(1); cls_q.push_back(cls); cls = new(2); cls_q.push_back(cls); cls = new(1); cls_q.push_back(cls); string_q.push_back("a"); string_q.push_back("A"); string_q.push_back("b"); q = '{1, 2, 2, 4, 3}; `checkp(q, "'{'h1, 'h2, 'h2, 'h4, 'h3}"); // sort/rsort with clause is the field to use for the sorting q.sort; `checkp(q, "'{'h1, 'h2, 'h2, 'h3, 'h4}"); q.sort with (10 - item); `checkp(q, "'{'h4, 'h3, 'h2, 'h2, 'h1}"); q.sort(x) with (10 - x); `checkp(q, "'{'h4, 'h3, 'h2, 'h2, 'h1}"); qe.sort(x) with (10 - x); `checkp(qe, "'{}"); q.rsort; `checkp(q, "'{'h4, 'h3, 'h2, 'h2, 'h1}"); q.rsort with (10 - item); `checkp(q, "'{'h1, 'h2, 'h2, 'h3, 'h4}"); qe.rsort(x) with (10 - x); `checkp(q, "'{'h1, 'h2, 'h2, 'h3, 'h4}"); q = '{2, 2, 4, 1, 3}; qv = q.unique; `checkp(qv, "'{'h2, 'h4, 'h1, 'h3}"); qv = qe.unique; `checkh(qv.size(), 0); qv = q.unique(x) with (x % 2); `checkh(qv.size(), 2); string_qv = string_q.unique(s) with (s.toupper); `checkh(string_qv.size(), 2); qi = q.unique_index; qv.sort; // According to IEEE 1800-2023 7.12.1, it is not specified which index of duplicated value should be returned `checkh(qi.size(), 4); qi.delete(1); `checkp(qi, "'{'h0, 'h3, 'h4}"); qi = qe.unique_index; `checkh(qi.size(), 0); qi = q.unique_index(x) with (x % 3); qv.sort; `checkh(qi.size(), 3); cls_qv = cls_q.unique with (item.x); `checkh(cls_qv.size(), 2); cls_qv = cls_q.unique with (item.x < 10); `checkh(cls_qv.size(), 1); qi = cls_q.unique_index with (item.x % 2); qi.sort; `checkp(qi, "'{'h0, 'h1}"); q.reverse; `checkp(q, "'{'h3, 'h1, 'h4, 'h2, 'h2}"); qe.reverse; `checkh(qe.size(), 0); q.shuffle(); q.sort; `checkp(q, "'{'h1, 'h2, 'h2, 'h3, 'h4}"); qe.shuffle(); `checkh(qe.size(), 0); // These require an with clause or are illegal // TODO add a lint check that with clause is provided qv = q.find with (item == 2); `checkp(qv, "'{'h2, 'h2}"); qv = q.find with (item[0] == 1); `checkp(qv, "'{'h1, 'h3}"); qv = q.find_first with (item == 2); `checkp(qv, "'{'h2}"); points_qv = points_q.find_first with (item.z == 5); `checkh(points_qv[0].p.y, 3); points_qv = points_q.find_first with (item.p.x == 1); `checkh(points_qv[0].p.y, 2); qv = q.find_last with (item == 2); `checkp(qv, "'{'h2}"); string_qv = string_q.find_last(s) with (s.tolower() == "a"); `checks(string_qv[0], "A"); qv = q.find with (item == 20); `checkh(qv.size, 0); qv = q.find_first with (item == 20); `checkh(qv.size, 0); qv = q.find_last with (item == 20); `checkh(qv.size, 0); // Check gate eater with Lambda variable removal qvunused = q.find with (item == 20); qi = q.find_index with (item == 2); qi.sort; `checkp(qi, "'{'h1, 'h2}"); qi = q.find_first_index with (item == 2); `checkp(qi, "'{'h1}"); qi = q.find_last_index with (item == 2); `checkp(qi, "'{'h2}"); i = 2; qi = q.find_index with (item == i); qi.sort; `checkp(qi, "'{'h1, 'h2}"); qi = q.find_index with (item == 20); qi.sort; `checkh(qi.size, 0); qi = q.find_first_index with (item == 20); `checkh(qi.size, 0); qi = q.find_last_index with (item == 20); `checkh(qi.size, 0); qi = q.find_index with (item.index == 2); `checkp(qi, "'{'h2}"); qi = q.find_index with (item.index == item); `checkp(qi, "'{'h2, 'h3, 'h4}"); qv = q.min; `checkp(qv, "'{'h1}"); qv = q.min(x) with (x + 1); `checkp(qv, "'{'h1}"); qv = q.max; `checkp(qv, "'{'h4}"); qv = q.max(x) with ((x % 4) + 100); `checkp(qv, "'{'h3}"); qv = qe.min; `checkp(qv, "'{}"); qv = qe.max; `checkp(qv, "'{}"); // Reduction methods i = q.sum; `checkh(i, 32'hc); i = q.sum with (item + 1); `checkh(i, 32'h11); i = q.sum(myi) with (myi + 1); `checkh(i, 32'h11); i = q.sum with (1); // unused 'index' `checkh(i, 32'h5); i = q.sum(unused) with (1); // unused 'unused' `checkh(i, 32'h5); i = q.product; `checkh(i, 32'h30); i = q.product with (item + 1); `checkh(i, 32'h168); i = qe.sum; `checkh(i, 32'h0); i = qe.sum with (item + 1); `checkh(i, 32'h0); i = qe.product; `checkh(i, 32'h0); i = qe.product with (item + 1); `checkh(i, 32'h0); q = '{32'b1100, 32'b1010}; i = q.and; `checkh(i, 32'b1000); i = q.and with (item + 1); `checkh(i, 32'b1001); i = q.or; `checkh(i, 32'b1110); i = q.or with (item + 1); `checkh(i, 32'b1111); i = q.xor; `checkh(i, 32'b0110); i = q.xor with (item + 1); `checkh(i, 32'b0110); i = qe.and; `checkh(i, 32'b0); i = qe.and with (item + 1); `checkh(i, 32'b0); i = qe.or; `checkh(i, 32'b0); i = qe.or with (item + 1); `checkh(i, 32'b0); i = qe.xor; `checkh(i, 32'b0); i = qe.xor with (item + 1); `checkh(i, 32'b0); q = '{1, 2}; qe = '{1, 2}; `checkh(q == qe, 1'b1); `checkh(q != qe, 1'b0); string_q = {"a", "bc", "def", "ghij"}; i = string_q.sum with (item.len); `checkh(i, 10); i = string_q.product with (item.len); `checkh(i, 24); b = string_q.sum with (item == "bc"); `checkh(b, 1'b1); b = string_q.sum with (item == ""); `checkh(b, 1'b0); b = string_q.product with (item inside {"a", "bc", "def"}); `checkh(b, 1'b0); b = string_q.product with (item inside {"a", "bc", "def", "ghij"}); `checkh(b, 1'b1); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_constraint_extern_bad.py0000755000542200017500000000077615101701376024357 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_tri_array.v0000644000542200017500000000344015101701376021575 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; parameter NPAD = 4; tri pad [NPAD-1:0]; // Array wire [NPAD-1:0] data0 = crc[0 +: 4]; wire [NPAD-1:0] data1 = crc[8 +: 4]; wire [NPAD-1:0] en = crc[16 +: 4]; for (genvar g=0; g! exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub0.i_sub0 $end $var wire 1 .# clk $end $var wire 8 /# in [7:0] $end $var wire 8 0# out [7:0] $end $scope module sub0 $end $var wire 1 .# clk $end $var wire 8 /# in [7:0] $end $var wire 8 0# out [7:0] $end $var wire 8 1# ff [7:0] $end $upscope $end $upscope $end $scope module top.t.i_sub1 $end $var wire 1 3# clk $end $var wire 8 4# in [11:4] $end $var wire 8 5# out [7:0] $end $scope module sub1 $end $var wire 1 3# clk $end $var wire 8 4# in [11:4] $end $var wire 8 5# out [7:0] $end $var wire 8 6# ff [7:0] $end $upscope $end $upscope $end $scope module top.t.i_sub2 $end $var wire 1 #' clk $end $var wire 8 $' in [7:0] $end $var wire 8 %' out [7:0] $end $scope module sub2 $end $var wire 1 #' clk $end $var wire 8 $' in [7:0] $end $var wire 8 %' out [7:0] $end $var wire 8 x# ff [7:0] $end $scope module in_ifs $end $var wire 1 #' clk $end $var wire 8 x# data [7:0] $end $upscope $end $scope module out_ifs $end $var wire 1 #' clk $end $var wire 8 y# data [7:0] $end $upscope $end $scope module i_sub3 $end $scope module in $end $var wire 1 #' clk $end $var wire 8 x# data [7:0] $end $upscope $end $scope module out $end $var wire 1 #' clk $end $var wire 8 y# data [7:0] $end $upscope $end $var wire 8 x# in_wire [7:0] $end $var wire 8 y# out_1 [7:0] $end $var wire 8 z# out_2 [7:0] $end $scope module i_sub3 $end $var wire 8 &' P0 [7:0] $end $var wire 32 '' UNPACKED_ARRAY[0] [31:0] $end $var wire 32 (' UNPACKED_ARRAY[1] [31:0] $end $var wire 16 )' UNUSED [15:0] $end $var wire 2 *' ENUM [1:0] $end $var wire 1 #' clk $end $var wire 8 x# in [7:0] $end $var wire 8 y# out [7:0] $end $var wire 8 {# ff [7:0] $end $var wire 8 y# out4 [7:0] $end $var wire 8 |# out4_2 [7:0] $end $scope module i_sub4_0 $end $var wire 32 +' P0 [31:0] $end $var real 64 ,' P1 $end $var real 64 .' P3 $end $var wire 1 #' clk $end $var wire 8 {# in [7:0] $end $var wire 8 y# out [7:0] $end $var wire 8 y# ff [7:0] $end $var wire 128 }# sub5_in[0][0] [127:0] $end $var wire 128 #$ sub5_in[0][1] [127:0] $end $var wire 128 '$ sub5_in[0][2] [127:0] $end $var wire 128 +$ sub5_in[1][0] [127:0] $end $var wire 128 /$ sub5_in[1][1] [127:0] $end $var wire 128 3$ sub5_in[1][2] [127:0] $end $var wire 8 7$ sub5_out[0][0] [7:0] $end $var wire 8 8$ sub5_out[0][1] [7:0] $end $var wire 8 9$ sub5_out[0][2] [7:0] $end $var wire 8 :$ sub5_out[1][0] [7:0] $end $var wire 8 ;$ sub5_out[1][1] [7:0] $end $var wire 8 <$ sub5_out[1][2] [7:0] $end $var wire 32 =$ count [31:0] $end $scope module i_sub5 $end $var wire 1 #' clk $end $var wire 128 >$ in[0][0] [127:0] $end $var wire 128 B$ in[0][1] [127:0] $end $var wire 128 F$ in[0][2] [127:0] $end $var wire 128 J$ in[1][0] [127:0] $end $var wire 128 N$ in[1][1] [127:0] $end $var wire 128 R$ in[1][2] [127:0] $end $var wire 8 V$ out[0][0] [7:0] $end $var wire 8 W$ out[0][1] [7:0] $end $var wire 8 X$ out[0][2] [7:0] $end $var wire 8 Y$ out[1][0] [7:0] $end $var wire 8 Z$ out[1][1] [7:0] $end $var wire 8 [$ out[1][2] [7:0] $end $var wire 32 \$ count [31:0] $end $var wire 8 8# val0[0] [7:0] $end $var wire 8 9# val0[1] [7:0] $end $var wire 8 :# val1[0] [7:0] $end $var wire 8 ;# val1[1] [7:0] $end $var wire 8 <# val2[0] [7:0] $end $var wire 8 =# val2[1] [7:0] $end $var wire 8 ># val3[0] [7:0] $end $var wire 8 ?# val3[1] [7:0] $end $scope module i_sub0 $end $var wire 32 0' P0 [31:0] $end $var wire 32 1' P1 [31:0] $end $var wire 8 @# out[0] [7:0] $end $var wire 8 A# out[1] [7:0] $end $upscope $end $scope module i_sub1 $end $var wire 32 0' P0 [31:0] $end $var wire 32 1' P1 [31:0] $end $var wire 8 B# out[0] [7:0] $end $var wire 8 C# out[1] [7:0] $end $upscope $end $scope module i_sub2 $end $var wire 32 0' P0 [31:0] $end $var wire 32 1' P1 [31:0] $end $var wire 8 D# out[0] [7:0] $end $var wire 8 E# out[1] [7:0] $end $upscope $end $scope module i_sub3 $end $var wire 32 0' P0 [31:0] $end $var wire 32 2' P1 [31:0] $end $var wire 8 F# out[0] [7:0] $end $var wire 8 G# out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var wire 32 ]$ i [31:0] $end $scope module unnamedblk2 $end $var wire 32 ^$ j [31:0] $end $scope module unnamedblk3 $end $var wire 128 _$ exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module unnamedblk1 $end $var wire 32 c$ i [31:0] $end $scope module unnamedblk2 $end $var wire 32 d$ j [31:0] $end $scope module unnamedblk3 $end $var wire 8 e$ exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module i_sub4_1 $end $var wire 32 +' P0 [31:0] $end $var real 64 ,' P1 $end $var real 64 3' P3 $end $var wire 1 #' clk $end $var wire 8 {# in [7:0] $end $var wire 8 |# out [7:0] $end $var wire 8 |# ff [7:0] $end $var wire 128 f$ sub5_in[0][0] [127:0] $end $var wire 128 j$ sub5_in[0][1] [127:0] $end $var wire 128 n$ sub5_in[0][2] [127:0] $end $var wire 128 r$ sub5_in[1][0] [127:0] $end $var wire 128 v$ sub5_in[1][1] [127:0] $end $var wire 128 z$ sub5_in[1][2] [127:0] $end $var wire 8 ~$ sub5_out[0][0] [7:0] $end $var wire 8 !% sub5_out[0][1] [7:0] $end $var wire 8 "% sub5_out[0][2] [7:0] $end $var wire 8 #% sub5_out[1][0] [7:0] $end $var wire 8 $% sub5_out[1][1] [7:0] $end $var wire 8 %% sub5_out[1][2] [7:0] $end $var wire 32 &% count [31:0] $end $scope module i_sub5 $end $var wire 1 #' clk $end $var wire 128 '% in[0][0] [127:0] $end $var wire 128 +% in[0][1] [127:0] $end $var wire 128 /% in[0][2] [127:0] $end $var wire 128 3% in[1][0] [127:0] $end $var wire 128 7% in[1][1] [127:0] $end $var wire 128 ;% in[1][2] [127:0] $end $var wire 8 ?% out[0][0] [7:0] $end $var wire 8 @% out[0][1] [7:0] $end $var wire 8 A% out[0][2] [7:0] $end $var wire 8 B% out[1][0] [7:0] $end $var wire 8 C% out[1][1] [7:0] $end $var wire 8 D% out[1][2] [7:0] $end $var wire 32 E% count [31:0] $end $var wire 8 H# val0[0] [7:0] $end $var wire 8 I# val0[1] [7:0] $end $var wire 8 J# val1[0] [7:0] $end $var wire 8 K# val1[1] [7:0] $end $var wire 8 L# val2[0] [7:0] $end $var wire 8 M# val2[1] [7:0] $end $var wire 8 N# val3[0] [7:0] $end $var wire 8 O# val3[1] [7:0] $end $scope module i_sub0 $end $var wire 32 0' P0 [31:0] $end $var wire 32 1' P1 [31:0] $end $var wire 8 P# out[0] [7:0] $end $var wire 8 Q# out[1] [7:0] $end $upscope $end $scope module i_sub1 $end $var wire 32 0' P0 [31:0] $end $var wire 32 1' P1 [31:0] $end $var wire 8 R# out[0] [7:0] $end $var wire 8 S# out[1] [7:0] $end $upscope $end $scope module i_sub2 $end $var wire 32 0' P0 [31:0] $end $var wire 32 1' P1 [31:0] $end $var wire 8 T# out[0] [7:0] $end $var wire 8 U# out[1] [7:0] $end $upscope $end $scope module i_sub3 $end $var wire 32 0' P0 [31:0] $end $var wire 32 2' P1 [31:0] $end $var wire 8 V# out[0] [7:0] $end $var wire 8 W# out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var wire 32 F% i [31:0] $end $scope module unnamedblk2 $end $var wire 32 G% j [31:0] $end $scope module unnamedblk3 $end $var wire 128 H% exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module unnamedblk1 $end $var wire 32 L% i [31:0] $end $scope module unnamedblk2 $end $var wire 32 M% j [31:0] $end $scope module unnamedblk3 $end $var wire 8 N% exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module i_sub3_2 $end $var wire 8 &' P0 [7:0] $end $var wire 32 5' UNPACKED_ARRAY[0] [31:0] $end $var wire 32 6' UNPACKED_ARRAY[1] [31:0] $end $var wire 16 )' UNUSED [15:0] $end $var wire 2 *' ENUM [1:0] $end $var wire 1 #' clk $end $var wire 8 x# in [7:0] $end $var wire 8 z# out [7:0] $end $var wire 8 O% ff [7:0] $end $var wire 8 z# out4 [7:0] $end $var wire 8 P% out4_2 [7:0] $end $scope module i_sub4_0 $end $var wire 32 +' P0 [31:0] $end $var real 64 ,' P1 $end $var real 64 .' P3 $end $var wire 1 #' clk $end $var wire 8 O% in [7:0] $end $var wire 8 z# out [7:0] $end $var wire 8 z# ff [7:0] $end $var wire 128 Q% sub5_in[0][0] [127:0] $end $var wire 128 U% sub5_in[0][1] [127:0] $end $var wire 128 Y% sub5_in[0][2] [127:0] $end $var wire 128 ]% sub5_in[1][0] [127:0] $end $var wire 128 a% sub5_in[1][1] [127:0] $end $var wire 128 e% sub5_in[1][2] [127:0] $end $var wire 8 i% sub5_out[0][0] [7:0] $end $var wire 8 j% sub5_out[0][1] [7:0] $end $var wire 8 k% sub5_out[0][2] [7:0] $end $var wire 8 l% sub5_out[1][0] [7:0] $end $var wire 8 m% sub5_out[1][1] [7:0] $end $var wire 8 n% sub5_out[1][2] [7:0] $end $var wire 32 o% count [31:0] $end $scope module i_sub5 $end $var wire 1 #' clk $end $var wire 128 p% in[0][0] [127:0] $end $var wire 128 t% in[0][1] [127:0] $end $var wire 128 x% in[0][2] [127:0] $end $var wire 128 |% in[1][0] [127:0] $end $var wire 128 "& in[1][1] [127:0] $end $var wire 128 && in[1][2] [127:0] $end $var wire 8 *& out[0][0] [7:0] $end $var wire 8 +& out[0][1] [7:0] $end $var wire 8 ,& out[0][2] [7:0] $end $var wire 8 -& out[1][0] [7:0] $end $var wire 8 .& out[1][1] [7:0] $end $var wire 8 /& out[1][2] [7:0] $end $var wire 32 0& count [31:0] $end $var wire 8 X# val0[0] [7:0] $end $var wire 8 Y# val0[1] [7:0] $end $var wire 8 Z# val1[0] [7:0] $end $var wire 8 [# val1[1] [7:0] $end $var wire 8 \# val2[0] [7:0] $end $var wire 8 ]# val2[1] [7:0] $end $var wire 8 ^# val3[0] [7:0] $end $var wire 8 _# val3[1] [7:0] $end $scope module i_sub0 $end $var wire 32 0' P0 [31:0] $end $var wire 32 1' P1 [31:0] $end $var wire 8 `# out[0] [7:0] $end $var wire 8 a# out[1] [7:0] $end $upscope $end $scope module i_sub1 $end $var wire 32 0' P0 [31:0] $end $var wire 32 1' P1 [31:0] $end $var wire 8 b# out[0] [7:0] $end $var wire 8 c# out[1] [7:0] $end $upscope $end $scope module i_sub2 $end $var wire 32 0' P0 [31:0] $end $var wire 32 1' P1 [31:0] $end $var wire 8 d# out[0] [7:0] $end $var wire 8 e# out[1] [7:0] $end $upscope $end $scope module i_sub3 $end $var wire 32 0' P0 [31:0] $end $var wire 32 2' P1 [31:0] $end $var wire 8 f# out[0] [7:0] $end $var wire 8 g# out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var wire 32 1& i [31:0] $end $scope module unnamedblk2 $end $var wire 32 2& j [31:0] $end $scope module unnamedblk3 $end $var wire 128 3& exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module unnamedblk1 $end $var wire 32 7& i [31:0] $end $scope module unnamedblk2 $end $var wire 32 8& j [31:0] $end $scope module unnamedblk3 $end $var wire 8 9& exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module i_sub4_1 $end $var wire 32 +' P0 [31:0] $end $var real 64 ,' P1 $end $var real 64 3' P3 $end $var wire 1 #' clk $end $var wire 8 O% in [7:0] $end $var wire 8 P% out [7:0] $end $var wire 8 P% ff [7:0] $end $var wire 128 :& sub5_in[0][0] [127:0] $end $var wire 128 >& sub5_in[0][1] [127:0] $end $var wire 128 B& sub5_in[0][2] [127:0] $end $var wire 128 F& sub5_in[1][0] [127:0] $end $var wire 128 J& sub5_in[1][1] [127:0] $end $var wire 128 N& sub5_in[1][2] [127:0] $end $var wire 8 R& sub5_out[0][0] [7:0] $end $var wire 8 S& sub5_out[0][1] [7:0] $end $var wire 8 T& sub5_out[0][2] [7:0] $end $var wire 8 U& sub5_out[1][0] [7:0] $end $var wire 8 V& sub5_out[1][1] [7:0] $end $var wire 8 W& sub5_out[1][2] [7:0] $end $var wire 32 X& count [31:0] $end $scope module i_sub5 $end $var wire 1 #' clk $end $var wire 128 Y& in[0][0] [127:0] $end $var wire 128 ]& in[0][1] [127:0] $end $var wire 128 a& in[0][2] [127:0] $end $var wire 128 e& in[1][0] [127:0] $end $var wire 128 i& in[1][1] [127:0] $end $var wire 128 m& in[1][2] [127:0] $end $var wire 8 q& out[0][0] [7:0] $end $var wire 8 r& out[0][1] [7:0] $end $var wire 8 s& out[0][2] [7:0] $end $var wire 8 t& out[1][0] [7:0] $end $var wire 8 u& out[1][1] [7:0] $end $var wire 8 v& out[1][2] [7:0] $end $var wire 32 w& count [31:0] $end $var wire 8 h# val0[0] [7:0] $end $var wire 8 i# val0[1] [7:0] $end $var wire 8 j# val1[0] [7:0] $end $var wire 8 k# val1[1] [7:0] $end $var wire 8 l# val2[0] [7:0] $end $var wire 8 m# val2[1] [7:0] $end $var wire 8 n# val3[0] [7:0] $end $var wire 8 o# val3[1] [7:0] $end $scope module i_sub0 $end $var wire 32 0' P0 [31:0] $end $var wire 32 1' P1 [31:0] $end $var wire 8 p# out[0] [7:0] $end $var wire 8 q# out[1] [7:0] $end $upscope $end $scope module i_sub1 $end $var wire 32 0' P0 [31:0] $end $var wire 32 1' P1 [31:0] $end $var wire 8 r# out[0] [7:0] $end $var wire 8 s# out[1] [7:0] $end $upscope $end $scope module i_sub2 $end $var wire 32 0' P0 [31:0] $end $var wire 32 1' P1 [31:0] $end $var wire 8 t# out[0] [7:0] $end $var wire 8 u# out[1] [7:0] $end $upscope $end $scope module i_sub3 $end $var wire 32 0' P0 [31:0] $end $var wire 32 2' P1 [31:0] $end $var wire 8 v# out[0] [7:0] $end $var wire 8 w# out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var wire 32 x& i [31:0] $end $scope module unnamedblk2 $end $var wire 32 y& j [31:0] $end $scope module unnamedblk3 $end $var wire 128 z& exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module unnamedblk1 $end $var wire 32 ~& i [31:0] $end $scope module unnamedblk2 $end $var wire 32 !' j [31:0] $end $scope module unnamedblk3 $end $var wire 8 "' exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3.i_sub4_0.i_sub5 $end $var wire 1 m' clk $end $var wire 128 n' in[0][0] [127:0] $end $var wire 128 r' in[0][1] [127:0] $end $var wire 128 v' in[0][2] [127:0] $end $var wire 128 z' in[1][0] [127:0] $end $var wire 128 ~' in[1][1] [127:0] $end $var wire 128 $( in[1][2] [127:0] $end $var wire 8 (( out[0][0] [7:0] $end $var wire 8 )( out[0][1] [7:0] $end $var wire 8 *( out[0][2] [7:0] $end $var wire 8 +( out[1][0] [7:0] $end $var wire 8 ,( out[1][1] [7:0] $end $var wire 8 -( out[1][2] [7:0] $end $scope module sub5 $end $var wire 1 m' clk $end $var wire 128 H' in[0][0] [127:0] $end $var wire 128 L' in[0][1] [127:0] $end $var wire 128 P' in[0][2] [127:0] $end $var wire 128 T' in[1][0] [127:0] $end $var wire 128 X' in[1][1] [127:0] $end $var wire 128 \' in[1][2] [127:0] $end $var wire 8 `' out[0][0] [7:0] $end $var wire 8 a' out[0][1] [7:0] $end $var wire 8 b' out[0][2] [7:0] $end $var wire 8 c' out[1][0] [7:0] $end $var wire 8 d' out[1][1] [7:0] $end $var wire 8 e' out[1][2] [7:0] $end $var wire 32 f' count [31:0] $end $var wire 8 8' val0[0] [7:0] $end $var wire 8 9' val0[1] [7:0] $end $var wire 8 :' val1[0] [7:0] $end $var wire 8 ;' val1[1] [7:0] $end $var wire 8 <' val2[0] [7:0] $end $var wire 8 =' val2[1] [7:0] $end $var wire 8 >' val3[0] [7:0] $end $var wire 8 ?' val3[1] [7:0] $end $scope module i_sub0 $end $var wire 32 .( P0 [31:0] $end $var wire 32 /( P1 [31:0] $end $var wire 8 @' out[0] [7:0] $end $var wire 8 A' out[1] [7:0] $end $upscope $end $scope module i_sub1 $end $var wire 32 .( P0 [31:0] $end $var wire 32 /( P1 [31:0] $end $var wire 8 B' out[0] [7:0] $end $var wire 8 C' out[1] [7:0] $end $upscope $end $scope module i_sub2 $end $var wire 32 .( P0 [31:0] $end $var wire 32 /( P1 [31:0] $end $var wire 8 D' out[0] [7:0] $end $var wire 8 E' out[1] [7:0] $end $upscope $end $scope module i_sub3 $end $var wire 32 .( P0 [31:0] $end $var wire 32 0( P1 [31:0] $end $var wire 8 F' out[0] [7:0] $end $var wire 8 G' out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var wire 32 g' i [31:0] $end $scope module unnamedblk2 $end $var wire 32 h' j [31:0] $end $scope module unnamedblk3 $end $var wire 128 i' exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3.i_sub4_1.i_sub5 $end $var wire 1 g( clk $end $var wire 128 h( in[0][0] [127:0] $end $var wire 128 l( in[0][1] [127:0] $end $var wire 128 p( in[0][2] [127:0] $end $var wire 128 t( in[1][0] [127:0] $end $var wire 128 x( in[1][1] [127:0] $end $var wire 128 |( in[1][2] [127:0] $end $var wire 8 ") out[0][0] [7:0] $end $var wire 8 #) out[0][1] [7:0] $end $var wire 8 $) out[0][2] [7:0] $end $var wire 8 %) out[1][0] [7:0] $end $var wire 8 &) out[1][1] [7:0] $end $var wire 8 ') out[1][2] [7:0] $end $scope module sub5 $end $var wire 1 g( clk $end $var wire 128 B( in[0][0] [127:0] $end $var wire 128 F( in[0][1] [127:0] $end $var wire 128 J( in[0][2] [127:0] $end $var wire 128 N( in[1][0] [127:0] $end $var wire 128 R( in[1][1] [127:0] $end $var wire 128 V( in[1][2] [127:0] $end $var wire 8 Z( out[0][0] [7:0] $end $var wire 8 [( out[0][1] [7:0] $end $var wire 8 \( out[0][2] [7:0] $end $var wire 8 ]( out[1][0] [7:0] $end $var wire 8 ^( out[1][1] [7:0] $end $var wire 8 _( out[1][2] [7:0] $end $var wire 32 `( count [31:0] $end $var wire 8 2( val0[0] [7:0] $end $var wire 8 3( val0[1] [7:0] $end $var wire 8 4( val1[0] [7:0] $end $var wire 8 5( val1[1] [7:0] $end $var wire 8 6( val2[0] [7:0] $end $var wire 8 7( val2[1] [7:0] $end $var wire 8 8( val3[0] [7:0] $end $var wire 8 9( val3[1] [7:0] $end $scope module i_sub0 $end $var wire 32 () P0 [31:0] $end $var wire 32 )) P1 [31:0] $end $var wire 8 :( out[0] [7:0] $end $var wire 8 ;( out[1] [7:0] $end $upscope $end $scope module i_sub1 $end $var wire 32 () P0 [31:0] $end $var wire 32 )) P1 [31:0] $end $var wire 8 <( out[0] [7:0] $end $var wire 8 =( out[1] [7:0] $end $upscope $end $scope module i_sub2 $end $var wire 32 () P0 [31:0] $end $var wire 32 )) P1 [31:0] $end $var wire 8 >( out[0] [7:0] $end $var wire 8 ?( out[1] [7:0] $end $upscope $end $scope module i_sub3 $end $var wire 32 () P0 [31:0] $end $var wire 32 *) P1 [31:0] $end $var wire 8 @( out[0] [7:0] $end $var wire 8 A( out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var wire 32 a( i [31:0] $end $scope module unnamedblk2 $end $var wire 32 b( j [31:0] $end $scope module unnamedblk3 $end $var wire 128 c( exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3_2.i_sub4_0.i_sub5 $end $var wire 1 a) clk $end $var wire 128 b) in[0][0] [127:0] $end $var wire 128 f) in[0][1] [127:0] $end $var wire 128 j) in[0][2] [127:0] $end $var wire 128 n) in[1][0] [127:0] $end $var wire 128 r) in[1][1] [127:0] $end $var wire 128 v) in[1][2] [127:0] $end $var wire 8 z) out[0][0] [7:0] $end $var wire 8 {) out[0][1] [7:0] $end $var wire 8 |) out[0][2] [7:0] $end $var wire 8 }) out[1][0] [7:0] $end $var wire 8 ~) out[1][1] [7:0] $end $var wire 8 !* out[1][2] [7:0] $end $scope module sub5 $end $var wire 1 a) clk $end $var wire 128 <) in[0][0] [127:0] $end $var wire 128 @) in[0][1] [127:0] $end $var wire 128 D) in[0][2] [127:0] $end $var wire 128 H) in[1][0] [127:0] $end $var wire 128 L) in[1][1] [127:0] $end $var wire 128 P) in[1][2] [127:0] $end $var wire 8 T) out[0][0] [7:0] $end $var wire 8 U) out[0][1] [7:0] $end $var wire 8 V) out[0][2] [7:0] $end $var wire 8 W) out[1][0] [7:0] $end $var wire 8 X) out[1][1] [7:0] $end $var wire 8 Y) out[1][2] [7:0] $end $var wire 32 Z) count [31:0] $end $var wire 8 ,) val0[0] [7:0] $end $var wire 8 -) val0[1] [7:0] $end $var wire 8 .) val1[0] [7:0] $end $var wire 8 /) val1[1] [7:0] $end $var wire 8 0) val2[0] [7:0] $end $var wire 8 1) val2[1] [7:0] $end $var wire 8 2) val3[0] [7:0] $end $var wire 8 3) val3[1] [7:0] $end $scope module i_sub0 $end $var wire 32 "* P0 [31:0] $end $var wire 32 #* P1 [31:0] $end $var wire 8 4) out[0] [7:0] $end $var wire 8 5) out[1] [7:0] $end $upscope $end $scope module i_sub1 $end $var wire 32 "* P0 [31:0] $end $var wire 32 #* P1 [31:0] $end $var wire 8 6) out[0] [7:0] $end $var wire 8 7) out[1] [7:0] $end $upscope $end $scope module i_sub2 $end $var wire 32 "* P0 [31:0] $end $var wire 32 #* P1 [31:0] $end $var wire 8 8) out[0] [7:0] $end $var wire 8 9) out[1] [7:0] $end $upscope $end $scope module i_sub3 $end $var wire 32 "* P0 [31:0] $end $var wire 32 $* P1 [31:0] $end $var wire 8 :) out[0] [7:0] $end $var wire 8 ;) out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var wire 32 [) i [31:0] $end $scope module unnamedblk2 $end $var wire 32 \) j [31:0] $end $scope module unnamedblk3 $end $var wire 128 ]) exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3_2.i_sub4_1.i_sub5 $end $var wire 1 [* clk $end $var wire 128 \* in[0][0] [127:0] $end $var wire 128 `* in[0][1] [127:0] $end $var wire 128 d* in[0][2] [127:0] $end $var wire 128 h* in[1][0] [127:0] $end $var wire 128 l* in[1][1] [127:0] $end $var wire 128 p* in[1][2] [127:0] $end $var wire 8 t* out[0][0] [7:0] $end $var wire 8 u* out[0][1] [7:0] $end $var wire 8 v* out[0][2] [7:0] $end $var wire 8 w* out[1][0] [7:0] $end $var wire 8 x* out[1][1] [7:0] $end $var wire 8 y* out[1][2] [7:0] $end $scope module sub5 $end $var wire 1 [* clk $end $var wire 128 6* in[0][0] [127:0] $end $var wire 128 :* in[0][1] [127:0] $end $var wire 128 >* in[0][2] [127:0] $end $var wire 128 B* in[1][0] [127:0] $end $var wire 128 F* in[1][1] [127:0] $end $var wire 128 J* in[1][2] [127:0] $end $var wire 8 N* out[0][0] [7:0] $end $var wire 8 O* out[0][1] [7:0] $end $var wire 8 P* out[0][2] [7:0] $end $var wire 8 Q* out[1][0] [7:0] $end $var wire 8 R* out[1][1] [7:0] $end $var wire 8 S* out[1][2] [7:0] $end $var wire 32 T* count [31:0] $end $var wire 8 &* val0[0] [7:0] $end $var wire 8 '* val0[1] [7:0] $end $var wire 8 (* val1[0] [7:0] $end $var wire 8 )* val1[1] [7:0] $end $var wire 8 ** val2[0] [7:0] $end $var wire 8 +* val2[1] [7:0] $end $var wire 8 ,* val3[0] [7:0] $end $var wire 8 -* val3[1] [7:0] $end $scope module i_sub0 $end $var wire 32 z* P0 [31:0] $end $var wire 32 {* P1 [31:0] $end $var wire 8 .* out[0] [7:0] $end $var wire 8 /* out[1] [7:0] $end $upscope $end $scope module i_sub1 $end $var wire 32 z* P0 [31:0] $end $var wire 32 {* P1 [31:0] $end $var wire 8 0* out[0] [7:0] $end $var wire 8 1* out[1] [7:0] $end $upscope $end $scope module i_sub2 $end $var wire 32 z* P0 [31:0] $end $var wire 32 {* P1 [31:0] $end $var wire 8 2* out[0] [7:0] $end $var wire 8 3* out[1] [7:0] $end $upscope $end $scope module i_sub3 $end $var wire 32 z* P0 [31:0] $end $var wire 32 |* P1 [31:0] $end $var wire 8 4* out[0] [7:0] $end $var wire 8 5* out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end $var wire 32 U* i [31:0] $end $scope module unnamedblk2 $end $var wire 32 V* j [31:0] $end $scope module unnamedblk3 $end $var wire 128 W* exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 b00000000 # b00000000 $ b00000000 % b00000000000000000000000000000000 & b00000000 ' b00000000 ( b00000000 ) b00000000 * b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 / b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3 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b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 [ b00000000000000000000000000000000 _ b00000000000000000000000000000000 ` b00000000000000000000000000000000 a b00000000 b b00000000 c b00000000 d b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m 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b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ?" b00000000 C" b00000000 D" b00000000 E" b00000000 F" b00000000 G" b00000000 H" b00000000 I" b00000000 J" b00000000 K" b00000000 L" b00000000 M" b00000000 N" b00000000 O" b00000000 P" b00000000 Q" b00000000 R" b00000000 S" b00000000 T" b00000000 U" b00000000 V" b00000000 W" b00000000 X" b00000000 Y" b00000000 Z" b00000000 [" b00000000 \" b00000000 ]" b00000000 ^" b00000000 _" b00000000 `" b00000000 a" b00000000 b" b00000000 c" b00000000 d" b00000000 e" b00000000 f" b00000000 g" b00000000 h" b00000000 i" b00000000 j" b00000000 k" b00000000 l" b00000000 m" b00000000 n" b00000000 o" b00000000 p" b00000000 q" b00000000 r" b00000000 s" b00000000 t" b00000000 u" 0v" 0.# b00000000 /# b00000000 0# b00000000 1# 03# b00000000 4# b00000000 5# b00000000 6# b00000001 8# b00000010 9# b00000001 :# b00000010 ;# b00000001 <# b00000010 =# b00000001 ># b00000011 ?# b00000001 @# b00000010 A# b00000001 B# b00000010 C# b00000001 D# b00000010 E# b00000001 F# b00000011 G# b00000001 H# b00000010 I# b00000001 J# b00000010 K# b00000001 L# b00000010 M# b00000001 N# b00000011 O# b00000001 P# b00000010 Q# b00000001 R# b00000010 S# b00000001 T# b00000010 U# b00000001 V# b00000011 W# b00000001 X# b00000010 Y# b00000001 Z# b00000010 [# b00000001 \# b00000010 ]# b00000001 ^# b00000011 _# b00000001 `# b00000010 a# b00000001 b# b00000010 c# b00000001 d# b00000010 e# b00000001 f# b00000011 g# b00000001 h# b00000010 i# b00000001 j# b00000010 k# b00000001 l# b00000010 m# b00000001 n# b00000011 o# b00000001 p# b00000010 q# b00000001 r# b00000010 s# b00000001 t# b00000010 u# b00000001 v# b00000011 w# b00000000 x# b00000000 y# b00000000 z# b00000000 {# b00000000 |# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 }# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 #$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3$ b00000000 7$ b00000000 8$ b00000000 9$ b00000000 :$ b00000000 ;$ b00000000 <$ b00000000000000000000000000000000 =$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 >$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R$ b00000000 V$ b00000000 W$ b00000000 X$ b00000000 Y$ b00000000 Z$ b00000000 [$ b00000000000000000000000000000000 \$ b00000000000000000000000000000000 ]$ b00000000000000000000000000000000 ^$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 _$ b00000000000000000000000000000000 c$ b00000000000000000000000000000000 d$ b00000000 e$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 f$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 j$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z$ b00000000 ~$ b00000000 !% b00000000 "% b00000000 #% b00000000 $% b00000000 %% b00000000000000000000000000000000 &% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;% b00000000 ?% b00000000 @% b00000000 A% b00000000 B% b00000000 C% b00000000 D% b00000000000000000000000000000000 E% b00000000000000000000000000000000 F% b00000000000000000000000000000000 G% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H% b00000000000000000000000000000000 L% b00000000000000000000000000000000 M% b00000000 N% b00000000 O% b00000000 P% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Q% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 U% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Y% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e% b00000000 i% b00000000 j% b00000000 k% b00000000 l% b00000000 m% b00000000 n% b00000000000000000000000000000000 o% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 && b00000000 *& b00000000 +& b00000000 ,& b00000000 -& b00000000 .& b00000000 /& b00000000000000000000000000000000 0& b00000000000000000000000000000000 1& b00000000000000000000000000000000 2& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3& b00000000000000000000000000000000 7& b00000000000000000000000000000000 8& b00000000 9& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 :& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 >& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N& b00000000 R& b00000000 S& b00000000 T& b00000000 U& b00000000 V& b00000000 W& b00000000000000000000000000000000 X& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Y& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m& b00000000 q& b00000000 r& b00000000 s& b00000000 t& b00000000 u& b00000000 v& b00000000000000000000000000000000 w& b00000000000000000000000000000000 x& b00000000000000000000000000000000 y& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z& b00000000000000000000000000000000 ~& b00000000000000000000000000000000 !' b00000000 "' 0#' b00000000 $' b00000000 %' b00000001 8' b00000010 9' b00000001 :' b00000010 ;' b00000001 <' b00000010 =' b00000001 >' b00000011 ?' b00000001 @' b00000010 A' b00000001 B' b00000010 C' b00000001 D' b00000010 E' b00000001 F' b00000011 G' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \' b00000000 `' b00000000 a' b00000000 b' b00000000 c' b00000000 d' b00000000 e' b00000000000000000000000000000000 f' b00000000000000000000000000000000 g' b00000000000000000000000000000000 h' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i' 0m' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $( b00000000 (( b00000000 )( b00000000 *( b00000000 +( b00000000 ,( b00000000 -( b00000001 2( b00000010 3( b00000001 4( b00000010 5( b00000001 6( b00000010 7( b00000001 8( b00000011 9( b00000001 :( b00000010 ;( b00000001 <( b00000010 =( b00000001 >( b00000010 ?( b00000001 @( b00000011 A( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V( b00000000 Z( b00000000 [( b00000000 \( b00000000 ]( b00000000 ^( b00000000 _( b00000000000000000000000000000000 `( b00000000000000000000000000000000 a( b00000000000000000000000000000000 b( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 c( 0g( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 h( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |( b00000000 ") b00000000 #) b00000000 $) b00000000 %) b00000000 &) b00000000 ') b00000001 ,) b00000010 -) b00000001 .) b00000010 /) b00000001 0) b00000010 1) b00000001 2) b00000011 3) b00000001 4) b00000010 5) b00000001 6) b00000010 7) b00000001 8) b00000010 9) b00000001 :) b00000011 ;) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 <) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 @) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 D) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P) b00000000 T) b00000000 U) b00000000 V) b00000000 W) b00000000 X) b00000000 Y) b00000000000000000000000000000000 Z) b00000000000000000000000000000000 [) b00000000000000000000000000000000 \) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]) 0a) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 b) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 f) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 j) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v) b00000000 z) b00000000 {) b00000000 |) b00000000 }) b00000000 ~) b00000000 !* b00000001 &* b00000010 '* b00000001 (* b00000010 )* b00000001 ** b00000010 +* b00000001 ,* b00000011 -* b00000001 .* b00000010 /* b00000001 0* b00000010 1* b00000001 2* b00000010 3* b00000001 4* b00000011 5* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 6* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 :* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 >* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J* b00000000 N* b00000000 O* b00000000 P* b00000000 Q* b00000000 R* b00000000 S* b00000000000000000000000000000000 T* b00000000000000000000000000000000 U* b00000000000000000000000000000000 V* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W* 0[* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 `* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 d* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p* b00000000 t* b00000000 u* b00000000 v* b00000000 w* b00000000 x* b00000000 y* b00000000000000000000000000100001 w" b00000000000000000000000000101100 x" b00000000000000000000000000000010 y" b00000000000000000000000000001000 z" b00000000000000000000000000000001 {" b00000000000000000000000000000011 |" b00000001 }" b00000000000000000000000000000000 ~" b00000000000000000000000000000001 !# b1111111111111101 "# b00 ## b00000000000000000000000000000010 $# r3.1 %# r4.1 '# r5 )# b00000000000000000000000000000000 +# b00000000000000000000000000000001 ,# b00000011 &' b00000000000000000000000000000000 '' b00000000000000000000000000000001 (' b1111111111111101 )' b11 *' b00000000000000000000000000000010 +' r3.1 ,' r4.1 .' b00000000000000000000000000000001 0' b00000000000000000000000000000010 1' b00000000000000000000000000000011 2' r5 3' b00000000000000000000000000000000 5' b00000000000000000000000000000001 6' b00000000000000000000000000000001 .( b00000000000000000000000000000010 /( b00000000000000000000000000000011 0( b00000000000000000000000000000001 () b00000000000000000000000000000010 )) b00000000000000000000000000000011 *) b00000000000000000000000000000001 "* b00000000000000000000000000000010 #* b00000000000000000000000000000011 $* b00000000000000000000000000000001 z* b00000000000000000000000000000010 {* b00000000000000000000000000000011 |* #10 b00000010 # b00000000000000000000000000000001 & b00000010 * b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 / b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ? b00000000000000000000000000000001 C b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 [ b00000000000000000000000000000001 _ b00000001 c b00000010 d b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 y b00000000000000000000000000000001 } b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 '! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 7! b00000000000000000000000000000001 ;! b00000010 ?! b00000001 @! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 E! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 u! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 /" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ?" b00000001 D" b00000010 E" 1v" 1.# b00000010 /# 13# b00000001 5# b00000001 6# b00000010 x# b00000010 y# b00000010 z# b00000011 {# b00000010 |# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 #$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 '$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 3$ b00000000000000000000000000000001 =$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 B$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 F$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 R$ b00000000000000000000000000000001 \$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 j$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 n$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 z$ b00000000000000000000000000000001 &% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 +% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 /% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;% b00000000000000000000000000000001 E% b00000011 O% b00000010 P% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 U% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 Y% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 e% b00000000000000000000000000000001 o% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 t% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 x% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 && b00000000000000000000000000000001 0& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 >& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 B& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 N& b00000000000000000000000000000001 X& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m& b00000000000000000000000000000001 w& 1#' b00000001 $' b00000010 %' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 L' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 P' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 \' b00000000000000000000000000000001 f' 1m' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 r' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 v' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 $( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 F( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 J( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 V( b00000000000000000000000000000001 `( 1g( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 l( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 p( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 |( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 @) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 D) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 P) b00000000000000000000000000000001 Z) 1a) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 f) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 j) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 v) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 :* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 >* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 J* b00000000000000000000000000000001 T* 1[* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 `* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 d* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 p* #15 0v" 0.# 03# 0#' 0m' 0g( 0a) 0[* #20 b00000011 # b00000000000000000000000000000010 & b00000010 ' b00000011 * b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 / b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ? b00000000000000000000000000000010 C b00000000000000000000000000000010 D b00000000000000000000000000000011 E b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 [ b00000000000000000000000000000010 _ b00000000000000000000000000000010 ` b00000000000000000000000000000011 a b00000011 c b00000011 d b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y b00000000000000000000000000000010 } b00000000000000000000000000000010 ~ b00000000000000000000000000000011 !! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7! b00000000000000000000000000000010 ;! b00000000000000000000000000000010 & b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N& b00000110 R& b00000101 S& b00000100 T& b00000011 U& b00000010 V& b00000001 W& b00000000000000000000000000000010 X& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m& b00000110 q& b00000101 r& b00000100 s& b00000011 t& b00000010 u& b00000001 v& b00000000000000000000000000000010 w& b00000000000000000000000000000010 x& b00000000000000000000000000000011 y& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 z& b00000000000000000000000000000010 ~& b00000000000000000000000000000011 !' 1#' b00000101 %' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \' b00000110 `' b00000101 a' b00000100 b' b00000011 c' b00000010 d' b00000001 e' b00000000000000000000000000000010 f' b00000000000000000000000000000010 g' b00000000000000000000000000000011 h' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 i' 1m' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $( b00000110 (( b00000101 )( b00000100 *( b00000011 +( b00000010 ,( b00000001 -( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V( b00000110 Z( b00000101 [( b00000100 \( b00000011 ]( b00000010 ^( b00000001 _( b00000000000000000000000000000010 `( b00000000000000000000000000000010 a( b00000000000000000000000000000011 b( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 c( 1g( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |( b00000110 ") b00000101 #) b00000100 $) b00000011 %) b00000010 &) b00000001 ') b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 @) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 D) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P) b00000110 T) b00000101 U) b00000100 V) b00000011 W) b00000010 X) b00000001 Y) b00000000000000000000000000000010 Z) b00000000000000000000000000000010 [) b00000000000000000000000000000011 \) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ]) 1a) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 f) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 j) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v) b00000110 z) b00000101 {) b00000100 |) b00000011 }) b00000010 ~) b00000001 !* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 :* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 >* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J* b00000110 N* b00000101 O* b00000100 P* b00000011 Q* b00000010 R* b00000001 S* b00000000000000000000000000000010 T* b00000000000000000000000000000010 U* b00000000000000000000000000000011 V* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 W* 1[* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 `* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 d* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p* b00000110 t* b00000101 u* b00000100 v* b00000011 w* b00000010 x* b00000001 y* #25 0v" 0.# 03# 0#' 0m' 0g( 0a) 0[* #30 b00000101 # b00000010 $ b00000000000000000000000000000011 & b00000011 ' b00000101 * b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 / b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ? b00000000000000000000000000000011 C b00000001 F b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 [ b00000000000000000000000000000011 _ b00000001 b b00000110 c b00000101 d b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 y b00000000000000000000000000000011 } b00000001 "! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 '! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 7! b00000000000000000000000000000011 ;! b00000001 >! b00000101 ?! b00000110 @! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 E! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 u! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 /" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ?" b00000011 C" b00000011 D" b00000111 E" b00000000 F" b00000000 G" b00000000 H" b00000000 I" b00000000 J" b00000000 K" b00000000 L" b00000000 M" b00000000 N" b00000000 O" b00000000 P" b00000000 Q" b00000000 R" b00000000 S" b00000000 T" b00000000 U" b00000000 V" b00000000 W" b00000000 X" b00000000 Y" b00000000 Z" b00000000 [" b00000000 \" b00000000 ]" b00000000 ^" b00000000 _" b00000000 `" b00000000 a" b00000000 b" b00000000 c" b00000000 d" b00000000 e" b00000000 f" b00000000 g" b00000000 h" b00000000 i" b00000000 j" b00000000 k" b00000000 l" b00000000 m" b00000000 n" b00000000 o" b00000000 p" b00000000 q" b00000000 r" b00000000 s" b00000000 t" b00000000 u" 1v" 1.# b00000101 /# b00000011 0# b00000011 1# 13# b00000011 4# b00000011 5# b00000011 6# b00000111 y# b00000111 z# b00000110 {# b00000111 |# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 #$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 '$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 3$ b00000000 7$ b00000000 8$ b00000000 9$ b00000000 :$ b00000000 ;$ b00000000 <$ b00000000000000000000000000000011 =$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 B$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 F$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 R$ b00000000 V$ b00000000 W$ b00000000 X$ b00000000 Y$ b00000000 Z$ b00000000 [$ b00000000000000000000000000000011 \$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 _$ b00000001 e$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 j$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 n$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 z$ b00000000 ~$ b00000000 !% b00000000 "% b00000000 #% b00000000 $% b00000000 %% b00000000000000000000000000000011 &% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 +% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 /% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;% b00000000 ?% b00000000 @% b00000000 A% b00000000 B% b00000000 C% b00000000 D% b00000000000000000000000000000011 E% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H% b00000001 N% b00000110 O% b00000111 P% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 U% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 Y% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 e% b00000000 i% b00000000 j% b00000000 k% b00000000 l% b00000000 m% b00000000 n% b00000000000000000000000000000011 o% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 t% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 x% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 && b00000000 *& b00000000 +& b00000000 ,& b00000000 -& b00000000 .& b00000000 /& b00000000000000000000000000000011 0& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3& b00000001 9& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 >& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 B& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 N& b00000000 R& b00000000 S& b00000000 T& b00000000 U& b00000000 V& b00000000 W& b00000000000000000000000000000011 X& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m& b00000000 q& b00000000 r& b00000000 s& b00000000 t& b00000000 u& b00000000 v& b00000000000000000000000000000011 w& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z& b00000001 "' 1#' b00000011 $' b00000111 %' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 L' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 P' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 \' b00000000 `' b00000000 a' b00000000 b' b00000000 c' b00000000 d' b00000000 e' b00000000000000000000000000000011 f' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i' 1m' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 r' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 v' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 $( b00000000 (( b00000000 )( b00000000 *( b00000000 +( b00000000 ,( b00000000 -( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 F( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 J( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 V( b00000000 Z( b00000000 [( b00000000 \( b00000000 ]( b00000000 ^( b00000000 _( b00000000000000000000000000000011 `( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 c( 1g( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 l( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 p( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 |( b00000000 ") b00000000 #) b00000000 $) b00000000 %) b00000000 &) b00000000 ') b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 @) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 D) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 P) b00000000 T) b00000000 U) b00000000 V) b00000000 W) b00000000 X) b00000000 Y) b00000000000000000000000000000011 Z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]) 1a) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 f) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 j) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 v) b00000000 z) b00000000 {) b00000000 |) b00000000 }) b00000000 ~) b00000000 !* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 :* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 >* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 J* b00000000 N* b00000000 O* b00000000 P* b00000000 Q* b00000000 R* b00000000 S* b00000000000000000000000000000011 T* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W* 1[* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 `* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 d* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 p* b00000000 t* b00000000 u* b00000000 v* b00000000 w* b00000000 x* b00000000 y* #35 0v" 0.# 03# 0#' 0m' 0g( 0a) 0[* #40 b00001000 # b00000011 $ b00000000000000000000000000000100 & b00000101 ' b00000010 ( b00001000 * b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 / b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ? b00000000000000000000000000000100 C b00000000 F b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 [ b00000000000000000000000000000100 _ b00000000 b b00001000 c b00001000 d b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y b00000000000000000000000000000100 } b00000000 "! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7! b00000000000000000000000000000100 ;! b00000000 >! b00001000 ?! b00001000 @! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 E! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ?" b00000101 C" b00000100 D" b00001000 E" b00000110 F" b00000101 G" b00000100 H" b00000011 I" b00000010 J" b00000001 K" b00000110 L" b00000101 M" b00000100 N" b00000011 O" b00000010 P" b00000001 Q" b00000110 R" b00000101 S" b00000100 T" b00000011 U" b00000010 V" b00000001 W" b00000110 X" b00000101 Y" b00000100 Z" b00000011 [" b00000010 \" b00000001 ]" b00000110 ^" b00000101 _" b00000100 `" b00000011 a" b00000010 b" b00000001 c" b00000110 d" b00000101 e" b00000100 f" b00000011 g" b00000010 h" b00000001 i" b00000110 j" b00000101 k" b00000100 l" b00000011 m" b00000010 n" b00000001 o" b00000110 p" b00000101 q" b00000100 r" b00000011 s" b00000010 t" b00000001 u" 1v" 1.# b00001000 /# b00000101 0# b00000101 1# 13# b00000101 4# b00000100 5# b00000100 6# b00000101 x# b00001000 y# b00001000 z# b00001000 |# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 #$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3$ b00000110 7$ b00000101 8$ b00000100 9$ b00000011 :$ b00000010 ;$ b00000001 <$ b00000000000000000000000000000100 =$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R$ b00000110 V$ b00000101 W$ b00000100 X$ b00000011 Y$ b00000010 Z$ b00000001 [$ b00000000000000000000000000000100 \$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _$ b00000000 e$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 j$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z$ b00000110 ~$ b00000101 !% b00000100 "% b00000011 #% b00000010 $% b00000001 %% b00000000000000000000000000000100 &% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;% b00000110 ?% b00000101 @% b00000100 A% b00000011 B% b00000010 C% b00000001 D% b00000000000000000000000000000100 E% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 H% b00000000 N% b00001000 P% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 U% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Y% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e% b00000110 i% b00000101 j% b00000100 k% b00000011 l% b00000010 m% b00000001 n% b00000000000000000000000000000100 o% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 && b00000110 *& b00000101 +& b00000100 ,& b00000011 -& b00000010 .& b00000001 /& b00000000000000000000000000000100 0& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 3& b00000000 9& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 >& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N& b00000110 R& b00000101 S& b00000100 T& b00000011 U& b00000010 V& b00000001 W& b00000000000000000000000000000100 X& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m& b00000110 q& b00000101 r& b00000100 s& b00000011 t& b00000010 u& b00000001 v& b00000000000000000000000000000100 w& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 z& b00000000 "' 1#' b00000100 $' b00001000 %' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \' b00000110 `' b00000101 a' b00000100 b' b00000011 c' b00000010 d' b00000001 e' b00000000000000000000000000000100 f' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 i' 1m' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $( b00000110 (( b00000101 )( b00000100 *( b00000011 +( b00000010 ,( b00000001 -( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V( b00000110 Z( b00000101 [( b00000100 \( b00000011 ]( b00000010 ^( b00000001 _( b00000000000000000000000000000100 `( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 c( 1g( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |( b00000110 ") b00000101 #) b00000100 $) b00000011 %) b00000010 &) b00000001 ') b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 @) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 D) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P) b00000110 T) b00000101 U) b00000100 V) b00000011 W) b00000010 X) b00000001 Y) b00000000000000000000000000000100 Z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ]) 1a) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 f) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 j) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v) b00000110 z) b00000101 {) b00000100 |) b00000011 }) b00000010 ~) b00000001 !* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 :* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 >* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J* b00000110 N* b00000101 O* b00000100 P* b00000011 Q* b00000010 R* b00000001 S* b00000000000000000000000000000100 T* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 W* 1[* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 `* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 d* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p* b00000110 t* b00000101 u* b00000100 v* b00000011 w* b00000010 x* b00000001 y* #45 0v" 0.# 03# 0#' 0m' 0g( 0a) 0[* #50 b00001010 # b00000101 $ b00000000000000000000000000000101 & b00001000 ' b00000011 ( b00000010 ) b00001010 * b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 / b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ? b00000000000000000000000000000101 C b00000001 F b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 [ b00000000000000000000000000000101 _ b00000001 b b00001001 c b00001010 d b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 y b00000000000000000000000000000101 } b00000001 "! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 '! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 7! b00000000000000000000000000000101 ;! b00000001 >! b00001010 ?! b00001001 @! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 E! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 u! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 /" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ?" b00001000 C" b00000110 D" b00000000 F" b00000000 G" b00000000 H" b00000000 I" b00000000 J" b00000000 K" b00000000 L" b00000000 M" b00000000 N" b00000000 O" b00000000 P" b00000000 Q" b00000000 R" b00000000 S" b00000000 T" b00000000 U" b00000000 V" b00000000 W" b00000000 X" b00000000 Y" b00000000 Z" b00000000 [" b00000000 \" b00000000 ]" b00000000 ^" b00000000 _" b00000000 `" b00000000 a" b00000000 b" b00000000 c" b00000000 d" b00000000 e" b00000000 f" b00000000 g" b00000000 h" b00000000 i" b00000000 j" b00000000 k" b00000000 l" b00000000 m" b00000000 n" b00000000 o" b00000000 p" b00000000 q" b00000000 r" b00000000 s" b00000000 t" b00000000 u" 1v" 1.# b00001010 /# b00001000 0# b00001000 1# 13# b00001000 4# b00000110 5# b00000110 6# b00000110 x# b00001000 {# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 #$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 '$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 3$ b00000000 7$ b00000000 8$ b00000000 9$ b00000000 :$ b00000000 ;$ b00000000 <$ b00000000000000000000000000000101 =$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 B$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 F$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 R$ b00000000 V$ b00000000 W$ b00000000 X$ b00000000 Y$ b00000000 Z$ b00000000 [$ b00000000000000000000000000000101 \$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 _$ b00000001 e$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 j$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 n$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 z$ b00000000 ~$ b00000000 !% b00000000 "% b00000000 #% b00000000 $% b00000000 %% b00000000000000000000000000000101 &% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 +% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 /% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;% b00000000 ?% b00000000 @% b00000000 A% b00000000 B% b00000000 C% b00000000 D% b00000000000000000000000000000101 E% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H% b00000001 N% b00001000 O% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 U% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 Y% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 e% b00000000 i% b00000000 j% b00000000 k% b00000000 l% b00000000 m% b00000000 n% b00000000000000000000000000000101 o% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 t% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 x% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 && b00000000 *& b00000000 +& b00000000 ,& b00000000 -& b00000000 .& b00000000 /& b00000000000000000000000000000101 0& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3& b00000001 9& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 >& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 B& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 N& b00000000 R& b00000000 S& b00000000 T& b00000000 U& b00000000 V& b00000000 W& b00000000000000000000000000000101 X& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m& b00000000 q& b00000000 r& b00000000 s& b00000000 t& b00000000 u& b00000000 v& b00000000000000000000000000000101 w& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z& b00000001 "' 1#' b00000110 $' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 L' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 P' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 \' b00000000 `' b00000000 a' b00000000 b' b00000000 c' b00000000 d' b00000000 e' b00000000000000000000000000000101 f' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i' 1m' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 r' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 v' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 $( b00000000 (( b00000000 )( b00000000 *( b00000000 +( b00000000 ,( b00000000 -( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 F( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 J( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 V( b00000000 Z( b00000000 [( b00000000 \( b00000000 ]( b00000000 ^( b00000000 _( b00000000000000000000000000000101 `( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 c( 1g( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 l( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 p( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 |( b00000000 ") b00000000 #) b00000000 $) b00000000 %) b00000000 &) b00000000 ') b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 @) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 D) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 P) b00000000 T) b00000000 U) b00000000 V) b00000000 W) b00000000 X) b00000000 Y) b00000000000000000000000000000101 Z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]) 1a) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 f) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 j) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 v) b00000000 z) b00000000 {) b00000000 |) b00000000 }) b00000000 ~) b00000000 !* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 :* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 >* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 J* b00000000 N* b00000000 O* b00000000 P* b00000000 Q* b00000000 R* b00000000 S* b00000000000000000000000000000101 T* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W* 1[* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 `* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 d* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 p* b00000000 t* b00000000 u* b00000000 v* b00000000 w* b00000000 x* b00000000 y* #55 0v" 0.# 03# 0#' 0m' 0g( 0a) 0[* #60 b00001011 # b00001000 $ b00000010 % b00000000000000000000000000000110 & b00001010 ' b00000101 ( b00000011 ) b00001011 * b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 / b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ? b00000000000000000000000000000110 C b00000000 F b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 [ b00000000000000000000000000000110 _ b00000000 b b00001011 d b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y b00000000000000000000000000000110 } b00000000 "! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7! b00000000000000000000000000000110 ;! b00000000 >! b00001011 ?! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 E! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ?" b00001010 C" b00001001 D" b00001010 E" b00000110 F" b00000101 G" b00000100 H" b00000011 I" b00000010 J" b00000001 K" b00000110 L" b00000101 M" b00000100 N" b00000011 O" b00000010 P" b00000001 Q" b00000110 R" b00000101 S" b00000100 T" b00000011 U" b00000010 V" b00000001 W" b00000110 X" b00000101 Y" b00000100 Z" b00000011 [" b00000010 \" b00000001 ]" b00000110 ^" b00000101 _" b00000100 `" b00000011 a" b00000010 b" b00000001 c" b00000110 d" b00000101 e" b00000100 f" b00000011 g" b00000010 h" b00000001 i" b00000110 j" b00000101 k" b00000100 l" b00000011 m" b00000010 n" b00000001 o" b00000110 p" b00000101 q" b00000100 r" b00000011 s" b00000010 t" b00000001 u" 1v" 1.# b00001011 /# b00001010 0# b00001010 1# 13# b00001010 4# b00001001 5# b00001001 6# b00001000 x# b00001010 y# b00001010 z# b00001001 {# b00001010 |# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 #$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3$ b00000110 7$ b00000101 8$ b00000100 9$ b00000011 :$ b00000010 ;$ b00000001 <$ b00000000000000000000000000000110 =$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R$ b00000110 V$ b00000101 W$ b00000100 X$ b00000011 Y$ b00000010 Z$ b00000001 [$ b00000000000000000000000000000110 \$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _$ b00000000 e$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 j$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z$ b00000110 ~$ b00000101 !% b00000100 "% b00000011 #% b00000010 $% b00000001 %% b00000000000000000000000000000110 &% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;% b00000110 ?% b00000101 @% b00000100 A% b00000011 B% b00000010 C% b00000001 D% b00000000000000000000000000000110 E% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 H% b00000000 N% b00001001 O% b00001010 P% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 U% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Y% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e% b00000110 i% b00000101 j% b00000100 k% b00000011 l% b00000010 m% b00000001 n% b00000000000000000000000000000110 o% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 && b00000110 *& b00000101 +& b00000100 ,& b00000011 -& b00000010 .& b00000001 /& b00000000000000000000000000000110 0& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 3& b00000000 9& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 >& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N& b00000110 R& b00000101 S& b00000100 T& b00000011 U& b00000010 V& b00000001 W& b00000000000000000000000000000110 X& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m& b00000110 q& b00000101 r& b00000100 s& b00000011 t& b00000010 u& b00000001 v& b00000000000000000000000000000110 w& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 z& b00000000 "' 1#' b00001001 $' b00001010 %' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \' b00000110 `' b00000101 a' b00000100 b' b00000011 c' b00000010 d' b00000001 e' b00000000000000000000000000000110 f' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 i' 1m' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $( b00000110 (( b00000101 )( b00000100 *( b00000011 +( b00000010 ,( b00000001 -( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V( b00000110 Z( b00000101 [( b00000100 \( b00000011 ]( b00000010 ^( b00000001 _( b00000000000000000000000000000110 `( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 c( 1g( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |( b00000110 ") b00000101 #) b00000100 $) b00000011 %) b00000010 &) b00000001 ') b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 @) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 D) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P) b00000110 T) b00000101 U) b00000100 V) b00000011 W) b00000010 X) b00000001 Y) b00000000000000000000000000000110 Z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ]) 1a) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 f) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 j) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v) b00000110 z) b00000101 {) b00000100 |) b00000011 }) b00000010 ~) b00000001 !* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 :* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 >* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J* b00000110 N* b00000101 O* b00000100 P* b00000011 Q* b00000010 R* b00000001 S* b00000000000000000000000000000110 T* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 W* 1[* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 `* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 d* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p* b00000110 t* b00000101 u* b00000100 v* b00000011 w* b00000010 x* b00000001 y* #65 0v" 0.# 03# 0#' 0m' 0g( 0a) 0[* #70 b00001010 $ b00000011 % b00000000000000000000000000000111 & b00001011 ' b00001000 ( b00000101 ) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 / b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ? b00000000000000000000000000000111 C b00000001 F b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 [ b00000000000000000000000000000111 _ b00000001 b b00001011 c b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 y b00000000000000000000000000000111 } b00000001 "! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 '! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 7! b00000000000000000000000000000111 ;! b00000001 >! b00001011 @! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 E! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 u! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 /" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ?" b00001011 C" b00001011 D" b00001011 E" b00000000 F" b00000000 G" b00000000 H" b00000000 I" b00000000 J" b00000000 K" b00000000 L" b00000000 M" b00000000 N" b00000000 O" b00000000 P" b00000000 Q" b00000000 R" b00000000 S" b00000000 T" b00000000 U" b00000000 V" b00000000 W" b00000000 X" b00000000 Y" b00000000 Z" b00000000 [" b00000000 \" b00000000 ]" b00000000 ^" b00000000 _" b00000000 `" b00000000 a" b00000000 b" b00000000 c" b00000000 d" b00000000 e" b00000000 f" b00000000 g" b00000000 h" b00000000 i" b00000000 j" b00000000 k" b00000000 l" b00000000 m" b00000000 n" b00000000 o" b00000000 p" b00000000 q" b00000000 r" b00000000 s" b00000000 t" b00000000 u" 1v" 1.# b00001011 0# b00001011 1# 13# b00001011 4# b00001011 5# b00001011 6# b00001011 x# b00001011 y# b00001011 z# b00001011 {# b00001011 |# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 #$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 '$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 3$ b00000000 7$ b00000000 8$ b00000000 9$ b00000000 :$ b00000000 ;$ b00000000 <$ b00000000000000000000000000000111 =$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 B$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 F$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 R$ b00000000 V$ b00000000 W$ b00000000 X$ b00000000 Y$ b00000000 Z$ b00000000 [$ b00000000000000000000000000000111 \$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 _$ b00000001 e$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 j$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 n$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 z$ b00000000 ~$ b00000000 !% b00000000 "% b00000000 #% b00000000 $% b00000000 %% b00000000000000000000000000000111 &% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 +% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 /% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;% b00000000 ?% b00000000 @% b00000000 A% b00000000 B% b00000000 C% b00000000 D% b00000000000000000000000000000111 E% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H% b00000001 N% b00001011 O% b00001011 P% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 U% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 Y% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 e% b00000000 i% b00000000 j% b00000000 k% b00000000 l% b00000000 m% b00000000 n% b00000000000000000000000000000111 o% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 t% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 x% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 && b00000000 *& b00000000 +& b00000000 ,& b00000000 -& b00000000 .& b00000000 /& b00000000000000000000000000000111 0& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3& b00000001 9& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 >& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 B& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 N& b00000000 R& b00000000 S& b00000000 T& b00000000 U& b00000000 V& b00000000 W& b00000000000000000000000000000111 X& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m& b00000000 q& b00000000 r& b00000000 s& b00000000 t& b00000000 u& b00000000 v& b00000000000000000000000000000111 w& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z& b00000001 "' 1#' b00001011 $' b00001011 %' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 L' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 P' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 \' b00000000 `' b00000000 a' b00000000 b' b00000000 c' b00000000 d' b00000000 e' b00000000000000000000000000000111 f' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i' 1m' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 r' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 v' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 $( b00000000 (( b00000000 )( b00000000 *( b00000000 +( b00000000 ,( b00000000 -( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 F( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 J( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 V( b00000000 Z( b00000000 [( b00000000 \( b00000000 ]( b00000000 ^( b00000000 _( b00000000000000000000000000000111 `( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 c( 1g( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 l( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 p( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 |( b00000000 ") b00000000 #) b00000000 $) b00000000 %) b00000000 &) b00000000 ') b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 @) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 D) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 P) b00000000 T) b00000000 U) b00000000 V) b00000000 W) b00000000 X) b00000000 Y) b00000000000000000000000000000111 Z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]) 1a) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 f) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 j) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 v) b00000000 z) b00000000 {) b00000000 |) b00000000 }) b00000000 ~) b00000000 !* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 :* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 >* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 J* b00000000 N* b00000000 O* b00000000 P* b00000000 Q* b00000000 R* b00000000 S* b00000000000000000000000000000111 T* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W* 1[* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 `* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 d* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 p* b00000000 t* b00000000 u* b00000000 v* b00000000 w* b00000000 x* b00000000 y* #75 0v" 0.# 03# 0#' 0m' 0g( 0a) 0[* #80 b00001101 # b00001011 $ b00000101 % b00000000000000000000000000001000 & b00001010 ( b00001000 ) b00001101 * b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 / b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ? b00000000000000000000000000001000 C b00000000 F b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 [ b00000000000000000000000000001000 _ b00000000 b b00001100 c b00001101 d b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y b00000000000000000000000000001000 } b00000000 "! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7! b00000000000000000000000000001000 ;! b00000000 >! b00001101 ?! b00001100 @! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 E! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ?" b00001100 D" b00001101 E" b00000110 F" b00000101 G" b00000100 H" b00000011 I" b00000010 J" b00000001 K" b00000110 L" b00000101 M" b00000100 N" b00000011 O" b00000010 P" b00000001 Q" b00000110 R" b00000101 S" b00000100 T" b00000011 U" b00000010 V" b00000001 W" b00000110 X" b00000101 Y" b00000100 Z" b00000011 [" b00000010 \" b00000001 ]" b00000110 ^" b00000101 _" b00000100 `" b00000011 a" b00000010 b" b00000001 c" b00000110 d" b00000101 e" b00000100 f" b00000011 g" b00000010 h" b00000001 i" b00000110 j" b00000101 k" b00000100 l" b00000011 m" b00000010 n" b00000001 o" b00000110 p" b00000101 q" b00000100 r" b00000011 s" b00000010 t" b00000001 u" 1v" 1.# b00001101 /# 13# b00001100 5# b00001100 6# b00001101 x# b00001101 y# b00001101 z# b00001110 {# b00001101 |# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 #$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3$ b00000110 7$ b00000101 8$ b00000100 9$ b00000011 :$ b00000010 ;$ b00000001 <$ b00000000000000000000000000001000 =$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R$ b00000110 V$ b00000101 W$ b00000100 X$ b00000011 Y$ b00000010 Z$ b00000001 [$ b00000000000000000000000000001000 \$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _$ b00000000 e$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 j$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z$ b00000110 ~$ b00000101 !% b00000100 "% b00000011 #% b00000010 $% b00000001 %% b00000000000000000000000000001000 &% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;% b00000110 ?% b00000101 @% b00000100 A% b00000011 B% b00000010 C% b00000001 D% b00000000000000000000000000001000 E% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 H% b00000000 N% b00001110 O% b00001101 P% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 U% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Y% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e% b00000110 i% b00000101 j% b00000100 k% b00000011 l% b00000010 m% b00000001 n% b00000000000000000000000000001000 o% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 && b00000110 *& b00000101 +& b00000100 ,& b00000011 -& b00000010 .& b00000001 /& b00000000000000000000000000001000 0& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 3& b00000000 9& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 >& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N& b00000110 R& b00000101 S& b00000100 T& b00000011 U& b00000010 V& b00000001 W& b00000000000000000000000000001000 X& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m& b00000110 q& b00000101 r& b00000100 s& b00000011 t& b00000010 u& b00000001 v& b00000000000000000000000000001000 w& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 z& b00000000 "' 1#' b00001100 $' b00001101 %' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \' b00000110 `' b00000101 a' b00000100 b' b00000011 c' b00000010 d' b00000001 e' b00000000000000000000000000001000 f' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 i' 1m' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $( b00000110 (( b00000101 )( b00000100 *( b00000011 +( b00000010 ,( b00000001 -( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V( b00000110 Z( b00000101 [( b00000100 \( b00000011 ]( b00000010 ^( b00000001 _( b00000000000000000000000000001000 `( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 c( 1g( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |( b00000110 ") b00000101 #) b00000100 $) b00000011 %) b00000010 &) b00000001 ') b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 @) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 D) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P) b00000110 T) b00000101 U) b00000100 V) b00000011 W) b00000010 X) b00000001 Y) b00000000000000000000000000001000 Z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ]) 1a) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 f) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 j) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v) b00000110 z) b00000101 {) b00000100 |) b00000011 }) b00000010 ~) b00000001 !* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 :* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 >* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J* b00000110 N* b00000101 O* b00000100 P* b00000011 Q* b00000010 R* b00000001 S* b00000000000000000000000000001000 T* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 W* 1[* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 `* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 d* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p* b00000110 t* b00000101 u* b00000100 v* b00000011 w* b00000010 x* b00000001 y* #85 0v" 0.# 03# 0#' 0m' 0g( 0a) 0[* #90 b00001110 # b00001000 % b00000000000000000000000000001001 & b00001101 ' b00001011 ( b00001010 ) b00001110 * b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 / b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ? b00000000000000000000000000001001 C b00000001 F b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 [ b00000000000000000000000000001001 _ b00000001 b b00001110 c b00001110 d b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 y b00000000000000000000000000001001 } b00000001 "! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 '! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 7! b00000000000000000000000000001001 ;! b00000001 >! b00001110 ?! b00001110 @! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 E! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 u! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 /" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ?" b00001101 C" b00010000 E" b00000000 F" b00000000 G" b00000000 H" b00000000 I" b00000000 J" b00000000 K" b00000000 L" b00000000 M" b00000000 N" b00000000 O" b00000000 P" b00000000 Q" b00000000 R" b00000000 S" b00000000 T" b00000000 U" b00000000 V" b00000000 W" b00000000 X" b00000000 Y" b00000000 Z" b00000000 [" b00000000 \" b00000000 ]" b00000000 ^" b00000000 _" b00000000 `" b00000000 a" b00000000 b" b00000000 c" b00000000 d" b00000000 e" b00000000 f" b00000000 g" b00000000 h" b00000000 i" b00000000 j" b00000000 k" b00000000 l" b00000000 m" b00000000 n" b00000000 o" b00000000 p" b00000000 q" b00000000 r" b00000000 s" b00000000 t" b00000000 u" 1v" 1.# b00001110 /# b00001101 0# b00001101 1# 13# b00001101 4# b00001110 x# b00010000 y# b00010000 z# b00010000 {# b00010000 |# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 #$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 '$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 3$ b00000000 7$ b00000000 8$ b00000000 9$ b00000000 :$ b00000000 ;$ b00000000 <$ b00000000000000000000000000001001 =$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 B$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 F$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 R$ b00000000 V$ b00000000 W$ b00000000 X$ b00000000 Y$ b00000000 Z$ b00000000 [$ b00000000000000000000000000001001 \$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 _$ b00000001 e$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 j$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 n$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 z$ b00000000 ~$ b00000000 !% b00000000 "% b00000000 #% b00000000 $% b00000000 %% b00000000000000000000000000001001 &% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 +% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 /% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;% b00000000 ?% b00000000 @% b00000000 A% b00000000 B% b00000000 C% b00000000 D% b00000000000000000000000000001001 E% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H% b00000001 N% b00010000 O% b00010000 P% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 U% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 Y% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 e% b00000000 i% b00000000 j% b00000000 k% b00000000 l% b00000000 m% b00000000 n% b00000000000000000000000000001001 o% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 t% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 x% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 && b00000000 *& b00000000 +& b00000000 ,& b00000000 -& b00000000 .& b00000000 /& b00000000000000000000000000001001 0& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3& b00000001 9& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 >& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 B& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 N& b00000000 R& b00000000 S& b00000000 T& b00000000 U& b00000000 V& b00000000 W& b00000000000000000000000000001001 X& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m& b00000000 q& b00000000 r& b00000000 s& b00000000 t& b00000000 u& b00000000 v& b00000000000000000000000000001001 w& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z& b00000001 "' 1#' b00010000 %' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 L' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 P' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 \' b00000000 `' b00000000 a' b00000000 b' b00000000 c' b00000000 d' b00000000 e' b00000000000000000000000000001001 f' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i' 1m' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 r' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 v' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 $( b00000000 (( b00000000 )( b00000000 *( b00000000 +( b00000000 ,( b00000000 -( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 F( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 J( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 V( b00000000 Z( b00000000 [( b00000000 \( b00000000 ]( b00000000 ^( b00000000 _( b00000000000000000000000000001001 `( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 c( 1g( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 l( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 p( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 |( b00000000 ") b00000000 #) b00000000 $) b00000000 %) b00000000 &) b00000000 ') b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 @) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 D) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 P) b00000000 T) b00000000 U) b00000000 V) b00000000 W) b00000000 X) b00000000 Y) b00000000000000000000000000001001 Z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]) 1a) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 f) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 j) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 v) b00000000 z) b00000000 {) b00000000 |) b00000000 }) b00000000 ~) b00000000 !* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 :* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 >* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 J* b00000000 N* b00000000 O* b00000000 P* b00000000 Q* b00000000 R* b00000000 S* b00000000000000000000000000001001 T* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W* 1[* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 `* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 d* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 p* b00000000 t* b00000000 u* b00000000 v* b00000000 w* b00000000 x* b00000000 y* #95 0v" 0.# 03# 0#' 0m' 0g( 0a) 0[* #100 b00010000 # b00001101 $ b00001010 % b00000000000000000000000000001010 & b00001110 ' b00001011 ) b00010000 * b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 / b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ? b00000000000000000000000000001010 C b00000000 F b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 [ b00000000000000000000000000001010 _ b00000000 b b00010001 c b00010000 d b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y b00000000000000000000000000001010 } b00000000 "! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7! b00000000000000000000000000001010 ;! b00000000 >! b00010000 ?! b00010001 @! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 E! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ?" b00001110 C" b00001110 D" b00010010 E" b00000110 F" b00000101 G" b00000100 H" b00000011 I" b00000010 J" b00000001 K" b00000110 L" b00000101 M" b00000100 N" b00000011 O" b00000010 P" b00000001 Q" b00000110 R" b00000101 S" b00000100 T" b00000011 U" b00000010 V" b00000001 W" b00000110 X" b00000101 Y" b00000100 Z" b00000011 [" b00000010 \" b00000001 ]" b00000110 ^" b00000101 _" b00000100 `" b00000011 a" b00000010 b" b00000001 c" b00000110 d" b00000101 e" b00000100 f" b00000011 g" b00000010 h" b00000001 i" b00000110 j" b00000101 k" b00000100 l" b00000011 m" b00000010 n" b00000001 o" b00000110 p" b00000101 q" b00000100 r" b00000011 s" b00000010 t" b00000001 u" 1v" 1.# b00010000 /# b00001110 0# b00001110 1# 13# b00001110 4# b00001110 5# b00001110 6# b00010010 y# b00010010 z# b00010001 {# b00010010 |# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 #$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3$ b00000110 7$ b00000101 8$ b00000100 9$ b00000011 :$ b00000010 ;$ b00000001 <$ b00000000000000000000000000001010 =$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R$ b00000110 V$ b00000101 W$ b00000100 X$ b00000011 Y$ b00000010 Z$ b00000001 [$ b00000000000000000000000000001010 \$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _$ b00000000 e$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 j$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z$ b00000110 ~$ b00000101 !% b00000100 "% b00000011 #% b00000010 $% b00000001 %% b00000000000000000000000000001010 &% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;% b00000110 ?% b00000101 @% b00000100 A% b00000011 B% b00000010 C% b00000001 D% b00000000000000000000000000001010 E% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 H% b00000000 N% b00010001 O% b00010010 P% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 U% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Y% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e% b00000110 i% b00000101 j% b00000100 k% b00000011 l% b00000010 m% b00000001 n% b00000000000000000000000000001010 o% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 && b00000110 *& b00000101 +& b00000100 ,& b00000011 -& b00000010 .& b00000001 /& b00000000000000000000000000001010 0& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 3& b00000000 9& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 >& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N& b00000110 R& b00000101 S& b00000100 T& b00000011 U& b00000010 V& b00000001 W& b00000000000000000000000000001010 X& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m& b00000110 q& b00000101 r& b00000100 s& b00000011 t& b00000010 u& b00000001 v& b00000000000000000000000000001010 w& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 z& b00000000 "' 1#' b00001110 $' b00010010 %' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \' b00000110 `' b00000101 a' b00000100 b' b00000011 c' b00000010 d' b00000001 e' b00000000000000000000000000001010 f' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 i' 1m' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $( b00000110 (( b00000101 )( b00000100 *( b00000011 +( b00000010 ,( b00000001 -( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V( b00000110 Z( b00000101 [( b00000100 \( b00000011 ]( b00000010 ^( b00000001 _( b00000000000000000000000000001010 `( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 c( 1g( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |( b00000110 ") b00000101 #) b00000100 $) b00000011 %) b00000010 &) b00000001 ') b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 @) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 D) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P) b00000110 T) b00000101 U) b00000100 V) b00000011 W) b00000010 X) b00000001 Y) b00000000000000000000000000001010 Z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ]) 1a) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 f) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 j) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v) b00000110 z) b00000101 {) b00000100 |) b00000011 }) b00000010 ~) b00000001 !* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 :* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 >* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J* b00000110 N* b00000101 O* b00000100 P* b00000011 Q* b00000010 R* b00000001 S* b00000000000000000000000000001010 T* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 W* 1[* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 `* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 d* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p* b00000110 t* b00000101 u* b00000100 v* b00000011 w* b00000010 x* b00000001 y* #105 0v" 0.# 03# 0#' 0m' 0g( 0a) 0[* #110 b00010011 # b00001110 $ b00001011 % b00000000000000000000000000001011 & b00010000 ' b00001101 ( b00010011 * b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 / b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ? b00000000000000000000000000001011 C b00000001 F b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 [ b00000000000000000000000000001011 _ b00000001 b b00010011 c b00010011 d b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 y b00000000000000000000000000001011 } b00000001 "! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 '! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 7! b00000000000000000000000000001011 ;! b00000001 >! b00010011 ?! b00010011 @! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 E! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 u! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 /" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ?" b00010000 C" b00001111 D" b00010011 E" b00000000 F" b00000000 G" b00000000 H" b00000000 I" b00000000 J" b00000000 K" b00000000 L" b00000000 M" b00000000 N" b00000000 O" b00000000 P" b00000000 Q" b00000000 R" b00000000 S" b00000000 T" b00000000 U" b00000000 V" b00000000 W" b00000000 X" b00000000 Y" b00000000 Z" b00000000 [" b00000000 \" b00000000 ]" b00000000 ^" b00000000 _" b00000000 `" b00000000 a" b00000000 b" b00000000 c" b00000000 d" b00000000 e" b00000000 f" b00000000 g" b00000000 h" b00000000 i" b00000000 j" b00000000 k" b00000000 l" b00000000 m" b00000000 n" b00000000 o" b00000000 p" b00000000 q" b00000000 r" b00000000 s" b00000000 t" b00000000 u" 1v" 1.# b00010011 /# b00010000 0# b00010000 1# 13# b00010000 4# b00001111 5# b00001111 6# b00010000 x# b00010011 y# b00010011 z# b00010011 |# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 #$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 '$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 3$ b00000000 7$ b00000000 8$ b00000000 9$ b00000000 :$ b00000000 ;$ b00000000 <$ b00000000000000000000000000001011 =$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 B$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 F$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 R$ b00000000 V$ b00000000 W$ b00000000 X$ b00000000 Y$ b00000000 Z$ b00000000 [$ b00000000000000000000000000001011 \$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 _$ b00000001 e$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 j$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 n$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 z$ b00000000 ~$ b00000000 !% b00000000 "% b00000000 #% b00000000 $% b00000000 %% b00000000000000000000000000001011 &% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 +% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 /% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;% b00000000 ?% b00000000 @% b00000000 A% b00000000 B% b00000000 C% b00000000 D% b00000000000000000000000000001011 E% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H% b00000001 N% b00010011 P% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 U% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 Y% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 e% b00000000 i% b00000000 j% b00000000 k% b00000000 l% b00000000 m% b00000000 n% b00000000000000000000000000001011 o% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 t% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 x% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 && b00000000 *& b00000000 +& b00000000 ,& b00000000 -& b00000000 .& b00000000 /& b00000000000000000000000000001011 0& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3& b00000001 9& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 >& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 B& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 N& b00000000 R& b00000000 S& b00000000 T& b00000000 U& b00000000 V& b00000000 W& b00000000000000000000000000001011 X& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m& b00000000 q& b00000000 r& b00000000 s& b00000000 t& b00000000 u& b00000000 v& b00000000000000000000000000001011 w& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z& b00000001 "' 1#' b00001111 $' b00010011 %' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 L' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 P' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 \' b00000000 `' b00000000 a' b00000000 b' b00000000 c' b00000000 d' b00000000 e' b00000000000000000000000000001011 f' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i' 1m' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 r' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 v' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 $( b00000000 (( b00000000 )( b00000000 *( b00000000 +( b00000000 ,( b00000000 -( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 F( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 J( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 V( b00000000 Z( b00000000 [( b00000000 \( b00000000 ]( b00000000 ^( b00000000 _( b00000000000000000000000000001011 `( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 c( 1g( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 l( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 p( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 |( b00000000 ") b00000000 #) b00000000 $) b00000000 %) b00000000 &) b00000000 ') b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 @) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 D) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 P) b00000000 T) b00000000 U) b00000000 V) b00000000 W) b00000000 X) b00000000 Y) b00000000000000000000000000001011 Z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]) 1a) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 f) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 j) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 v) b00000000 z) b00000000 {) b00000000 |) b00000000 }) b00000000 ~) b00000000 !* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 :* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 >* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 J* b00000000 N* b00000000 O* b00000000 P* b00000000 Q* b00000000 R* b00000000 S* b00000000000000000000000000001011 T* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W* 1[* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 `* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 d* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 p* b00000000 t* b00000000 u* b00000000 v* b00000000 w* b00000000 x* b00000000 y* #115 0v" 0.# 03# 0#' 0m' 0g( 0a) 0[* #120 b00010101 # b00010000 $ b00000000000000000000000000001100 & b00010011 ' b00001110 ( b00001101 ) b00010101 * b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 / b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ? b00000000000000000000000000001100 C b00000000 F b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 [ b00000000000000000000000000001100 _ b00000000 b b00010100 c b00010101 d b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y b00000000000000000000000000001100 } b00000000 "! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7! b00000000000000000000000000001100 ;! b00000000 >! b00010101 ?! b00010100 @! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 E! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ?" b00010011 C" b00010001 D" b00000110 F" b00000101 G" b00000100 H" b00000011 I" b00000010 J" b00000001 K" b00000110 L" b00000101 M" b00000100 N" b00000011 O" b00000010 P" b00000001 Q" b00000110 R" b00000101 S" b00000100 T" b00000011 U" b00000010 V" b00000001 W" b00000110 X" b00000101 Y" b00000100 Z" b00000011 [" b00000010 \" b00000001 ]" b00000110 ^" b00000101 _" b00000100 `" b00000011 a" b00000010 b" b00000001 c" b00000110 d" b00000101 e" b00000100 f" b00000011 g" b00000010 h" b00000001 i" b00000110 j" b00000101 k" b00000100 l" b00000011 m" b00000010 n" b00000001 o" b00000110 p" b00000101 q" b00000100 r" b00000011 s" b00000010 t" b00000001 u" 1v" 1.# b00010101 /# b00010011 0# b00010011 1# 13# b00010011 4# b00010001 5# b00010001 6# b00010001 x# b00010011 {# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 #$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3$ b00000110 7$ b00000101 8$ b00000100 9$ b00000011 :$ b00000010 ;$ b00000001 <$ b00000000000000000000000000001100 =$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R$ b00000110 V$ b00000101 W$ b00000100 X$ b00000011 Y$ b00000010 Z$ b00000001 [$ b00000000000000000000000000001100 \$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _$ b00000000 e$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 j$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z$ b00000110 ~$ b00000101 !% b00000100 "% b00000011 #% b00000010 $% b00000001 %% b00000000000000000000000000001100 &% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;% b00000110 ?% b00000101 @% b00000100 A% b00000011 B% b00000010 C% b00000001 D% b00000000000000000000000000001100 E% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 H% b00000000 N% b00010011 O% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 U% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Y% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e% b00000110 i% b00000101 j% b00000100 k% b00000011 l% b00000010 m% b00000001 n% b00000000000000000000000000001100 o% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 && b00000110 *& b00000101 +& b00000100 ,& b00000011 -& b00000010 .& b00000001 /& b00000000000000000000000000001100 0& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 3& b00000000 9& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 >& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N& b00000110 R& b00000101 S& b00000100 T& b00000011 U& b00000010 V& b00000001 W& b00000000000000000000000000001100 X& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m& b00000110 q& b00000101 r& b00000100 s& b00000011 t& b00000010 u& b00000001 v& b00000000000000000000000000001100 w& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 z& b00000000 "' 1#' b00010001 $' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \' b00000110 `' b00000101 a' b00000100 b' b00000011 c' b00000010 d' b00000001 e' b00000000000000000000000000001100 f' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 i' 1m' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $( b00000110 (( b00000101 )( b00000100 *( b00000011 +( b00000010 ,( b00000001 -( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V( b00000110 Z( b00000101 [( b00000100 \( b00000011 ]( b00000010 ^( b00000001 _( b00000000000000000000000000001100 `( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 c( 1g( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |( b00000110 ") b00000101 #) b00000100 $) b00000011 %) b00000010 &) b00000001 ') b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 @) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 D) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P) b00000110 T) b00000101 U) b00000100 V) b00000011 W) b00000010 X) b00000001 Y) b00000000000000000000000000001100 Z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ]) 1a) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 f) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 j) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v) b00000110 z) b00000101 {) b00000100 |) b00000011 }) b00000010 ~) b00000001 !* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 :* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 >* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J* b00000110 N* b00000101 O* b00000100 P* b00000011 Q* b00000010 R* b00000001 S* b00000000000000000000000000001100 T* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 W* 1[* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 `* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 d* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p* b00000110 t* b00000101 u* b00000100 v* b00000011 w* b00000010 x* b00000001 y* #125 0v" 0.# 03# 0#' 0m' 0g( 0a) 0[* #130 b00010110 # b00010011 $ b00001101 % b00000000000000000000000000001101 & b00010101 ' b00010000 ( b00001110 ) b00010110 * b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 / b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ? b00000000000000000000000000001101 C b00000001 F b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 [ b00000000000000000000000000001101 _ b00000001 b b00010110 d b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 y b00000000000000000000000000001101 } b00000001 "! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 '! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 7! b00000000000000000000000000001101 ;! b00000001 >! b00010110 ?! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 E! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 u! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 /" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ?" b00010101 C" b00010100 D" b00010101 E" b00000000 F" b00000000 G" b00000000 H" b00000000 I" b00000000 J" b00000000 K" b00000000 L" b00000000 M" b00000000 N" b00000000 O" b00000000 P" b00000000 Q" b00000000 R" b00000000 S" b00000000 T" b00000000 U" b00000000 V" b00000000 W" b00000000 X" b00000000 Y" b00000000 Z" b00000000 [" b00000000 \" b00000000 ]" b00000000 ^" b00000000 _" b00000000 `" b00000000 a" b00000000 b" b00000000 c" b00000000 d" b00000000 e" b00000000 f" b00000000 g" b00000000 h" b00000000 i" b00000000 j" b00000000 k" b00000000 l" b00000000 m" b00000000 n" b00000000 o" b00000000 p" b00000000 q" b00000000 r" b00000000 s" b00000000 t" b00000000 u" 1v" 1.# b00010110 /# b00010101 0# b00010101 1# 13# b00010101 4# b00010100 5# b00010100 6# b00010011 x# b00010101 y# b00010101 z# b00010100 {# b00010101 |# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 #$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 '$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 3$ b00000000 7$ b00000000 8$ b00000000 9$ b00000000 :$ b00000000 ;$ b00000000 <$ b00000000000000000000000000001101 =$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 B$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 F$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 R$ b00000000 V$ b00000000 W$ b00000000 X$ b00000000 Y$ b00000000 Z$ b00000000 [$ b00000000000000000000000000001101 \$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 _$ b00000001 e$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 j$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 n$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 z$ b00000000 ~$ b00000000 !% b00000000 "% b00000000 #% b00000000 $% b00000000 %% b00000000000000000000000000001101 &% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 +% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 /% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;% b00000000 ?% b00000000 @% b00000000 A% b00000000 B% b00000000 C% b00000000 D% b00000000000000000000000000001101 E% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H% b00000001 N% b00010100 O% b00010101 P% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 U% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 Y% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 e% b00000000 i% b00000000 j% b00000000 k% b00000000 l% b00000000 m% b00000000 n% b00000000000000000000000000001101 o% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 t% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 x% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 && b00000000 *& b00000000 +& b00000000 ,& b00000000 -& b00000000 .& b00000000 /& b00000000000000000000000000001101 0& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3& b00000001 9& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 >& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 B& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 N& b00000000 R& b00000000 S& b00000000 T& b00000000 U& b00000000 V& b00000000 W& b00000000000000000000000000001101 X& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m& b00000000 q& b00000000 r& b00000000 s& b00000000 t& b00000000 u& b00000000 v& b00000000000000000000000000001101 w& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z& b00000001 "' 1#' b00010100 $' b00010101 %' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 L' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 P' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 \' b00000000 `' b00000000 a' b00000000 b' b00000000 c' b00000000 d' b00000000 e' b00000000000000000000000000001101 f' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i' 1m' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 r' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 v' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 $( b00000000 (( b00000000 )( b00000000 *( b00000000 +( b00000000 ,( b00000000 -( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 F( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 J( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 V( b00000000 Z( b00000000 [( b00000000 \( b00000000 ]( b00000000 ^( b00000000 _( b00000000000000000000000000001101 `( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 c( 1g( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 l( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 p( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 |( b00000000 ") b00000000 #) b00000000 $) b00000000 %) b00000000 &) b00000000 ') b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 @) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 D) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 P) b00000000 T) b00000000 U) b00000000 V) b00000000 W) b00000000 X) b00000000 Y) b00000000000000000000000000001101 Z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]) 1a) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 f) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 j) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 v) b00000000 z) b00000000 {) b00000000 |) b00000000 }) b00000000 ~) b00000000 !* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 :* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 >* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 J* b00000000 N* b00000000 O* b00000000 P* b00000000 Q* b00000000 R* b00000000 S* b00000000000000000000000000001101 T* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W* 1[* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 `* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 d* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 p* b00000000 t* b00000000 u* b00000000 v* b00000000 w* b00000000 x* b00000000 y* #135 0v" 0.# 03# 0#' 0m' 0g( 0a) 0[* #140 b00010101 $ b00001110 % b00000000000000000000000000001110 & b00010110 ' b00010011 ( b00010000 ) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 / b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ? b00000000000000000000000000001110 C b00000000 F b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 [ b00000000000000000000000000001110 _ b00000000 b b00010110 c b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y b00000000000000000000000000001110 } b00000000 "! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7! b00000000000000000000000000001110 ;! b00000000 >! b00010110 @! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 E! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ?" b00010110 C" b00010110 D" b00010110 E" b00000110 F" b00000101 G" b00000100 H" b00000011 I" b00000010 J" b00000001 K" b00000110 L" b00000101 M" b00000100 N" b00000011 O" b00000010 P" b00000001 Q" b00000110 R" b00000101 S" b00000100 T" b00000011 U" b00000010 V" b00000001 W" b00000110 X" b00000101 Y" b00000100 Z" b00000011 [" b00000010 \" b00000001 ]" b00000110 ^" b00000101 _" b00000100 `" b00000011 a" b00000010 b" b00000001 c" b00000110 d" b00000101 e" b00000100 f" b00000011 g" b00000010 h" b00000001 i" b00000110 j" b00000101 k" b00000100 l" b00000011 m" b00000010 n" b00000001 o" b00000110 p" b00000101 q" b00000100 r" b00000011 s" b00000010 t" b00000001 u" 1v" 1.# b00010110 0# b00010110 1# 13# b00010110 4# b00010110 5# b00010110 6# b00010110 x# b00010110 y# b00010110 z# b00010110 {# b00010110 |# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 #$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3$ b00000110 7$ b00000101 8$ b00000100 9$ b00000011 :$ b00000010 ;$ b00000001 <$ b00000000000000000000000000001110 =$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R$ b00000110 V$ b00000101 W$ b00000100 X$ b00000011 Y$ b00000010 Z$ b00000001 [$ b00000000000000000000000000001110 \$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _$ b00000000 e$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 j$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z$ b00000110 ~$ b00000101 !% b00000100 "% b00000011 #% b00000010 $% b00000001 %% b00000000000000000000000000001110 &% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;% b00000110 ?% b00000101 @% b00000100 A% b00000011 B% b00000010 C% b00000001 D% b00000000000000000000000000001110 E% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 H% b00000000 N% b00010110 O% b00010110 P% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 U% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Y% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e% b00000110 i% b00000101 j% b00000100 k% b00000011 l% b00000010 m% b00000001 n% b00000000000000000000000000001110 o% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 && b00000110 *& b00000101 +& b00000100 ,& b00000011 -& b00000010 .& b00000001 /& b00000000000000000000000000001110 0& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 3& b00000000 9& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 >& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N& b00000110 R& b00000101 S& b00000100 T& b00000011 U& b00000010 V& b00000001 W& b00000000000000000000000000001110 X& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m& b00000110 q& b00000101 r& b00000100 s& b00000011 t& b00000010 u& b00000001 v& b00000000000000000000000000001110 w& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 z& b00000000 "' 1#' b00010110 $' b00010110 %' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \' b00000110 `' b00000101 a' b00000100 b' b00000011 c' b00000010 d' b00000001 e' b00000000000000000000000000001110 f' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 i' 1m' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $( b00000110 (( b00000101 )( b00000100 *( b00000011 +( b00000010 ,( b00000001 -( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V( b00000110 Z( b00000101 [( b00000100 \( b00000011 ]( b00000010 ^( b00000001 _( b00000000000000000000000000001110 `( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 c( 1g( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |( b00000110 ") b00000101 #) b00000100 $) b00000011 %) b00000010 &) b00000001 ') b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 @) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 D) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P) b00000110 T) b00000101 U) b00000100 V) b00000011 W) b00000010 X) b00000001 Y) b00000000000000000000000000001110 Z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ]) 1a) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 f) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 j) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v) b00000110 z) b00000101 {) b00000100 |) b00000011 }) b00000010 ~) b00000001 !* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 :* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 >* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J* b00000110 N* b00000101 O* b00000100 P* b00000011 Q* b00000010 R* b00000001 S* b00000000000000000000000000001110 T* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 W* 1[* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 `* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 d* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p* b00000110 t* b00000101 u* b00000100 v* b00000011 w* b00000010 x* b00000001 y* #145 0v" 0.# 03# 0#' 0m' 0g( 0a) 0[* #150 b00011000 # b00010110 $ b00010000 % b00000000000000000000000000001111 & b00010101 ( b00010011 ) b00011000 * b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 / b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ? b00000000000000000000000000001111 C b00000001 F b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 [ b00000000000000000000000000001111 _ b00000001 b b00010111 c b00011000 d b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 y b00000000000000000000000000001111 } b00000001 "! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 '! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 7! b00000000000000000000000000001111 ;! b00000001 >! b00011000 ?! b00010111 @! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 E! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 u! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 /" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ?" b00010111 D" b00011000 E" b00000000 F" b00000000 G" b00000000 H" b00000000 I" b00000000 J" b00000000 K" b00000000 L" b00000000 M" b00000000 N" b00000000 O" b00000000 P" b00000000 Q" b00000000 R" b00000000 S" b00000000 T" b00000000 U" b00000000 V" b00000000 W" b00000000 X" b00000000 Y" b00000000 Z" b00000000 [" b00000000 \" b00000000 ]" b00000000 ^" b00000000 _" b00000000 `" b00000000 a" b00000000 b" b00000000 c" b00000000 d" b00000000 e" b00000000 f" b00000000 g" b00000000 h" b00000000 i" b00000000 j" b00000000 k" b00000000 l" b00000000 m" b00000000 n" b00000000 o" b00000000 p" b00000000 q" b00000000 r" b00000000 s" b00000000 t" b00000000 u" 1v" 1.# b00011000 /# 13# b00010111 5# b00010111 6# b00011000 x# b00011000 y# b00011000 z# b00011001 {# b00011000 |# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 #$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 '$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 3$ b00000000 7$ b00000000 8$ b00000000 9$ b00000000 :$ b00000000 ;$ b00000000 <$ b00000000000000000000000000001111 =$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 B$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 F$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 R$ b00000000 V$ b00000000 W$ b00000000 X$ b00000000 Y$ b00000000 Z$ b00000000 [$ b00000000000000000000000000001111 \$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 _$ b00000001 e$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 j$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 n$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 z$ b00000000 ~$ b00000000 !% b00000000 "% b00000000 #% b00000000 $% b00000000 %% b00000000000000000000000000001111 &% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 +% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 /% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;% b00000000 ?% b00000000 @% b00000000 A% b00000000 B% b00000000 C% b00000000 D% b00000000000000000000000000001111 E% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H% b00000001 N% b00011001 O% b00011000 P% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 U% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 Y% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 e% b00000000 i% b00000000 j% b00000000 k% b00000000 l% b00000000 m% b00000000 n% b00000000000000000000000000001111 o% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 t% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 x% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 && b00000000 *& b00000000 +& b00000000 ,& b00000000 -& b00000000 .& b00000000 /& b00000000000000000000000000001111 0& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3& b00000001 9& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 >& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 B& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 N& b00000000 R& b00000000 S& b00000000 T& b00000000 U& b00000000 V& b00000000 W& b00000000000000000000000000001111 X& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m& b00000000 q& b00000000 r& b00000000 s& b00000000 t& b00000000 u& b00000000 v& b00000000000000000000000000001111 w& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z& b00000001 "' 1#' b00010111 $' b00011000 %' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 L' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 P' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 \' b00000000 `' b00000000 a' b00000000 b' b00000000 c' b00000000 d' b00000000 e' b00000000000000000000000000001111 f' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i' 1m' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 r' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 v' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 $( b00000000 (( b00000000 )( b00000000 *( b00000000 +( b00000000 ,( b00000000 -( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 F( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 J( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 V( b00000000 Z( b00000000 [( b00000000 \( b00000000 ]( b00000000 ^( b00000000 _( b00000000000000000000000000001111 `( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 c( 1g( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 l( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 p( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 |( b00000000 ") b00000000 #) b00000000 $) b00000000 %) b00000000 &) b00000000 ') b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 @) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 D) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 P) b00000000 T) b00000000 U) b00000000 V) b00000000 W) b00000000 X) b00000000 Y) b00000000000000000000000000001111 Z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]) 1a) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 f) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 j) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 v) b00000000 z) b00000000 {) b00000000 |) b00000000 }) b00000000 ~) b00000000 !* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 :* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 >* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 J* b00000000 N* b00000000 O* b00000000 P* b00000000 Q* b00000000 R* b00000000 S* b00000000000000000000000000001111 T* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W* 1[* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 `* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 d* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 p* b00000000 t* b00000000 u* b00000000 v* b00000000 w* b00000000 x* b00000000 y* #155 0v" 0.# 03# 0#' 0m' 0g( 0a) 0[* #160 b00011001 # b00010011 % b00000000000000000000000000010000 & b00011000 ' b00010110 ( b00010101 ) b00011001 * b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 / b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ? b00000000000000000000000000010000 C b00000000 F b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 [ b00000000000000000000000000010000 _ b00000000 b b00011001 c b00011001 d b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y b00000000000000000000000000010000 } b00000000 "! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7! b00000000000000000000000000010000 ;! b00000000 >! b00011001 ?! b00011001 @! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 E! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 u! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ?" b00011000 C" b00011011 E" b00000110 F" b00000101 G" b00000100 H" b00000011 I" b00000010 J" b00000001 K" b00000110 L" b00000101 M" b00000100 N" b00000011 O" b00000010 P" b00000001 Q" b00000110 R" b00000101 S" b00000100 T" b00000011 U" b00000010 V" b00000001 W" b00000110 X" b00000101 Y" b00000100 Z" b00000011 [" b00000010 \" b00000001 ]" b00000110 ^" b00000101 _" b00000100 `" b00000011 a" b00000010 b" b00000001 c" b00000110 d" b00000101 e" b00000100 f" b00000011 g" b00000010 h" b00000001 i" b00000110 j" b00000101 k" b00000100 l" b00000011 m" b00000010 n" b00000001 o" b00000110 p" b00000101 q" b00000100 r" b00000011 s" b00000010 t" b00000001 u" 1v" 1.# b00011001 /# b00011000 0# b00011000 1# 13# b00011000 4# b00011001 x# b00011011 y# b00011011 z# b00011011 {# b00011011 |# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 #$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 '$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3$ b00000110 7$ b00000101 8$ b00000100 9$ b00000011 :$ b00000010 ;$ b00000001 <$ b00000000000000000000000000010000 =$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R$ b00000110 V$ b00000101 W$ b00000100 X$ b00000011 Y$ b00000010 Z$ b00000001 [$ b00000000000000000000000000010000 \$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 _$ b00000000 e$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 j$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z$ b00000110 ~$ b00000101 !% b00000100 "% b00000011 #% b00000010 $% b00000001 %% b00000000000000000000000000010000 &% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;% b00000110 ?% b00000101 @% b00000100 A% b00000011 B% b00000010 C% b00000001 D% b00000000000000000000000000010000 E% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 H% b00000000 N% b00011011 O% b00011011 P% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 U% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Y% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e% b00000110 i% b00000101 j% b00000100 k% b00000011 l% b00000010 m% b00000001 n% b00000000000000000000000000010000 o% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 && b00000110 *& b00000101 +& b00000100 ,& b00000011 -& b00000010 .& b00000001 /& b00000000000000000000000000010000 0& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 3& b00000000 9& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 >& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N& b00000110 R& b00000101 S& b00000100 T& b00000011 U& b00000010 V& b00000001 W& b00000000000000000000000000010000 X& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 a& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 m& b00000110 q& b00000101 r& b00000100 s& b00000011 t& b00000010 u& b00000001 v& b00000000000000000000000000010000 w& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 z& b00000000 "' 1#' b00011011 %' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 \' b00000110 `' b00000101 a' b00000100 b' b00000011 c' b00000010 d' b00000001 e' b00000000000000000000000000010000 f' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 i' 1m' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $( b00000110 (( b00000101 )( b00000100 *( b00000011 +( b00000010 ,( b00000001 -( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 V( b00000110 Z( b00000101 [( b00000100 \( b00000011 ]( b00000010 ^( b00000001 _( b00000000000000000000000000010000 `( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 c( 1g( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |( b00000110 ") b00000101 #) b00000100 $) b00000011 %) b00000010 &) b00000001 ') b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 @) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 D) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 P) b00000110 T) b00000101 U) b00000100 V) b00000011 W) b00000010 X) b00000001 Y) b00000000000000000000000000010000 Z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ]) 1a) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 f) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 j) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 v) b00000110 z) b00000101 {) b00000100 |) b00000011 }) b00000010 ~) b00000001 !* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 :* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 >* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 J* b00000110 N* b00000101 O* b00000100 P* b00000011 Q* b00000010 R* b00000001 S* b00000000000000000000000000010000 T* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 W* 1[* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 `* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 d* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 p* b00000110 t* b00000101 u* b00000100 v* b00000011 w* b00000010 x* b00000001 y* #165 0v" 0.# 03# 0#' 0m' 0g( 0a) 0[* #170 b00011011 # b00011000 $ b00010101 % b00000000000000000000000000010001 & b00011001 ' b00010110 ) b00011011 * b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 / b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ; b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ? b00000000000000000000000000010001 C b00000001 F b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 K b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 O b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 S b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 W b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 [ b00000000000000000000000000010001 _ b00000001 b b00011100 c b00011011 d b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 i b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 m b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 q b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 u b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 y b00000000000000000000000000010001 } b00000001 "! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 '! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 /! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 3! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 7! b00000000000000000000000000010001 ;! b00000001 >! b00011011 ?! b00011100 @! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 E! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 I! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 M! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 Q! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 U! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 u! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 y! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 }! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 #" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 '" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 /" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 3" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 7" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ;" b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ?" b00011001 C" b00011001 D" b00011101 E" b00000000 F" b00000000 G" b00000000 H" b00000000 I" b00000000 J" b00000000 K" b00000000 L" b00000000 M" b00000000 N" b00000000 O" b00000000 P" b00000000 Q" b00000000 R" b00000000 S" b00000000 T" b00000000 U" b00000000 V" b00000000 W" b00000000 X" b00000000 Y" b00000000 Z" b00000000 [" b00000000 \" b00000000 ]" b00000000 ^" b00000000 _" b00000000 `" b00000000 a" b00000000 b" b00000000 c" b00000000 d" b00000000 e" b00000000 f" b00000000 g" b00000000 h" b00000000 i" b00000000 j" b00000000 k" b00000000 l" b00000000 m" b00000000 n" b00000000 o" b00000000 p" b00000000 q" b00000000 r" b00000000 s" b00000000 t" b00000000 u" 1v" 1.# b00011011 /# b00011001 0# b00011001 1# 13# b00011001 4# b00011001 5# b00011001 6# b00011101 y# b00011101 z# b00011100 {# b00011101 |# b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 #$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 '$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 +$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 /$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 3$ b00000000 7$ b00000000 8$ b00000000 9$ b00000000 :$ b00000000 ;$ b00000000 <$ b00000000000000000000000000010001 =$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 B$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 F$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 J$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 N$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 R$ b00000000 V$ b00000000 W$ b00000000 X$ b00000000 Y$ b00000000 Z$ b00000000 [$ b00000000000000000000000000010001 \$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 _$ b00000001 e$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 j$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 n$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 r$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 v$ b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 z$ b00000000 ~$ b00000000 !% b00000000 "% b00000000 #% b00000000 $% b00000000 %% b00000000000000000000000000010001 &% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 +% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 /% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 3% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 7% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ;% b00000000 ?% b00000000 @% b00000000 A% b00000000 B% b00000000 C% b00000000 D% b00000000000000000000000000010001 E% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 H% b00000001 N% b00011100 O% b00011101 P% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 U% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 Y% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 ]% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 a% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 e% b00000000 i% b00000000 j% b00000000 k% b00000000 l% b00000000 m% b00000000 n% b00000000000000000000000000010001 o% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 t% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 x% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 |% b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 "& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 && b00000000 *& b00000000 +& b00000000 ,& b00000000 -& b00000000 .& b00000000 /& b00000000000000000000000000010001 0& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3& b00000001 9& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 >& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 B& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 F& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 J& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 N& b00000000 R& b00000000 S& b00000000 T& b00000000 U& b00000000 V& b00000000 W& b00000000000000000000000000010001 X& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ]& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 a& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 e& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 i& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 m& b00000000 q& b00000000 r& b00000000 s& b00000000 t& b00000000 u& b00000000 v& b00000000000000000000000000010001 w& b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z& b00000001 "' 1#' b00011001 $' b00011101 %' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 L' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 P' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 T' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 X' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 \' b00000000 `' b00000000 a' b00000000 b' b00000000 c' b00000000 d' b00000000 e' b00000000000000000000000000010001 f' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 i' 1m' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 r' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 v' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 z' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 ~' b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 $( b00000000 (( b00000000 )( b00000000 *( b00000000 +( b00000000 ,( b00000000 -( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 F( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 J( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 N( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 R( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 V( b00000000 Z( b00000000 [( b00000000 \( b00000000 ]( b00000000 ^( b00000000 _( b00000000000000000000000000010001 `( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 c( 1g( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 l( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 p( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 t( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 x( b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 |( b00000000 ") b00000000 #) b00000000 $) b00000000 %) b00000000 &) b00000000 ') b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 @) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 D) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 H) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 L) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 P) b00000000 T) b00000000 U) b00000000 V) b00000000 W) b00000000 X) b00000000 Y) b00000000000000000000000000010001 Z) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ]) 1a) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 f) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 j) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 n) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 r) b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 v) b00000000 z) b00000000 {) b00000000 |) b00000000 }) b00000000 ~) b00000000 !* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 :* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 >* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 B* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 F* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 J* b00000000 N* b00000000 O* b00000000 P* b00000000 Q* b00000000 R* b00000000 S* b00000000000000000000000000010001 T* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 W* 1[* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 `* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 d* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 h* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 l* b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 p* b00000000 t* b00000000 u* b00000000 v* b00000000 w* b00000000 x* b00000000 y* verilator-5.042/test_regress/t/t_var_overcmp.v0000644000542200017500000000605615101701376022132 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs dout, // Inputs clk, rstn, dval0, dval1, dbgsel_w ); input clk; input rstn; input [7:0] dval0; input [7:0] dval1; input [7:0] dbgsel_w; output [7:0] dout; wire [7:0] dout = dout0 | dout1; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [7:0] dout0; // From sub0 of sub0.v wire [7:0] dout1; // From sub1 of sub1.v // End of automatics initial begin $write("*-* All Finished *-*\n"); $finish; end reg [7:0] dbgsel_msk; always_comb begin reg [7:0] mask; mask = 8'hff; dbgsel_msk = (dbgsel_w & mask); end reg [7:0] dbgsel; always @(posedge clk) begin if ((rstn == 0)) begin dbgsel <= 0; end else begin dbgsel <= dbgsel_msk; end end sub0 sub0 (/*AUTOINST*/ // Outputs .dout0 (dout0[7:0]), // Inputs .rstn (rstn), .clk (clk), .dval1 (dval1[7:0]), .dbgsel (dbgsel[7:0])); sub1 sub1 (/*AUTOINST*/ // Outputs .dout1 (dout1[7:0]), // Inputs .rstn (rstn), .clk (clk), .dval1 (dval1[7:0]), .dbgsel (dbgsel[7:0])); endmodule module sub0 ( /*AUTOARG*/ // Outputs dout0, // Inputs rstn, clk, dval1, dbgsel ); input rstn; input clk; input [7:0] dval1; input [7:0] dbgsel; output reg [7:0] dout0; reg [7:0] dbgsel_d1r; always_comb begin // verilator lint_off WIDTH if (((dbgsel_d1r >= 34) && (dbgsel_d1r < 65))) begin // verilator lint_on WIDTH dout0 = dval1; end else begin dout0 = 0; end end always @(posedge clk) begin if ((rstn == 0)) begin dbgsel_d1r <= 0; end else begin dbgsel_d1r <= dbgsel; end end endmodule module sub1 ( /*AUTOARG*/ // Outputs dout1, // Inputs rstn, clk, dval1, dbgsel ); input rstn; input clk; input [7:0] dval1; input [7:0] dbgsel; output reg [7:0] dout1; reg [7:0] dbgsel_d1r; always_comb begin // verilator lint_off WIDTH if (((dbgsel_d1r >= 334) && (dbgsel_d1r < 365))) begin // verilator lint_on WIDTH dout1 = dval1; end else begin dout1 = 0; end end always @(posedge clk) begin if ((rstn == 0)) begin dbgsel_d1r <= 0; end else begin dbgsel_d1r <= dbgsel; end end endmodule verilator-5.042/test_regress/t/t_constraint_mode_unsup.out0000644000542200017500000000175315101701376024572 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_constraint_mode_unsup.v:17:55: Unsupported: 'constraint_mode()' on static constraint : ... note: In instance 't' 17 | $display("p.cons.constraint_mode()=%0d", p.cons.constraint_mode()); | ^~~~~~~~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_constraint_mode_unsup.v:18:14: Unsupported: 'constraint_mode()' on static constraint : ... note: In instance 't' 18 | p.cons.constraint_mode(0); | ^~~~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_constraint_mode_unsup.v:19:9: Unsupported: 'constraint_mode()' on static constraint: 'cons' : ... note: In instance 't' 19 | p.constraint_mode(0); | ^~~~~~~~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_func_no_lifetime_bad.py0000755000542200017500000000105515101701376024102 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) if not test.vlt_all: test.execute() test.passes() verilator-5.042/test_regress/t/t_dpi_export_context2_bad.v0000644000542200017500000000105015101701376024405 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; export "DPI-C" task dpix_task; sub sub (); task dpix_task(); $write("Hello in %m\n"); endtask endmodule module sub; import "DPI-C" task dpii_task; initial dpii_task; endmodule verilator-5.042/test_regress/t/t_initial_edge.v0000644000542200017500000000463015101701376022220 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: initial edge issue // // The module initial_edge drives the output "res" high when the reset signal, // rst, goes high. // // The module initial_edge_n drives the output "res_n" high when the reset // signal, rst_n, goes low. // // For 4-state simulators, that edge occurs when the initial value of rst_n, // X, goes to zero. However, by default for Verilator, being 2-state, the // initial value is zero, so no edge is seen. // // This is not a bug in verilator (it is bad design to rely on an edge // transition from an unitialized signal), but the problem is that there are // quite a few instances of code out there that seems to be dependent on this // behaviour to get out of reset. // // The Verilator --x-initial-edge flag causes these initial edges to trigger, // thus matching the behaviour of a 4-state simulator. This is reportedly also // the behaviour of commercial cycle accurate modelling tools as well. // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `timescale 1ns/1ns module t (/*AUTOARG*/ // Inputs clk ); input clk; wire res; wire res_n; reg rst; reg rst_n; integer count = 0; initial_edge i_edge (.res (res), .rst (rst)); initial_edge_n i_edge_n (.res_n (res_n), .rst_n (rst_n)); // run for 3 cycles, with one cycle of reset. always @(posedge clk) begin rst <= (count == 0) ? 1 : 0; rst_n <= (count == 0) ? 0 : 1; if (count == 3) begin if ((res == 1) && (res_n == 1)) begin $write ("*-* All Finished *-*\n"); $finish; end else begin `ifdef TEST_VERBOSE $write ("FAILED: res = %b, res_n = %b\n", res, res_n); `endif $stop; end end count = count + 1; end endmodule module initial_edge_n (res_n, rst_n); output res_n; input rst_n; reg res_n = 1'b0; always @(negedge rst_n) begin if (rst_n == 1'b0) begin res_n <= 1'b1; end end endmodule // initial_edge_n module initial_edge (res, rst); output res; input rst; reg res = 1'b0; always @(posedge rst) begin if (rst == 1'b1) begin res <= 1'b1; end end endmodule // initial_edge verilator-5.042/test_regress/t/t_process.py0000755000542200017500000000102515101701376021442 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=["--binary"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_inst_v2k.v0000644000542200017500000000341215101701376021337 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; supply0 [1:0] low; supply1 [1:0] high; reg [7:0] isizedwire; reg ionewire; `ifdef never_just_for_verilog_mode wire oonewire; // From sub of t_inst_v2k__sub.v `endif wire [7:0] osizedreg; // From sub of t_inst_v2k__sub.v wire [1:0] tied; wire [3:0] tied_also; hello hsub (.tied_also); // Double underscore tests bug631 t_inst_v2k__sub sub ( // Outputs .osizedreg (osizedreg[7:0]), // verilator lint_off IMPLICIT .oonewire (oonewire), // verilator lint_on IMPLICIT .tied (tied[1:0]), // Inputs .isizedwire (isizedwire[7:0]), .ionewire (ionewire)); always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin ionewire <= 1'b1; isizedwire <= 8'd8; end if (cyc==2) begin if (low != 2'b00) $stop; if (high != 2'b11) $stop; if (oonewire !== 1'b1) $stop; if (isizedwire !== 8'd8) $stop; if (tied != 2'b10) $stop; if (tied_also != 4'b1010) $stop; $write("*-* All Finished *-*\n"); $finish; end end end endmodule module hello(tied_also); initial $write ("Hello\n"); output reg [3:0] tied_also = 4'b1010; endmodule verilator-5.042/test_regress/t/t_dpi_arg_output_unpack.py0000755000542200017500000000237515101701376024363 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if test.nc: # For NC, compile twice, first just to generate DPI headers test.compile(nc_flags2=[ "+ncdpiheader+" + test.obj_dir + "/dpi-exp.h", "+ncdpiimpheader+" + test.obj_dir + "/dpi-imp.h" ]) test.compile( v_flags2=["t/" + test.name + ".cpp"], # --no-decoration so .out file doesn't comment on source lines verilator_flags2=["-Wall -Wno-DECLFILENAME --no-decoration"], # NC: Gdd the obj_dir to the C include path nc_flags2=["+ncscargs+-I" + test.obj_dir], # ModelSim: Generate DPI header, add obj_dir to the C include path ms_flags2=["-dpiheader " + test.obj_dir + "/dpi.h", "-ccflags -I" + test.obj_dir]) if test.vlt_all: test.files_identical(test.obj_dir + "/" + test.vm_prefix + "__Dpi.h", "t/" + test.name + "__Dpi.out") test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_comb_use.py0000755000542200017500000000075615101701376022620 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--lint-only --bbox-sys"]) test.passes() verilator-5.042/test_regress/t/t_dpi_threads_collide.py0000755000542200017500000000151415101701376023750 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vltmt') test.top_filename = "t/t_dpi_threads.v" test.skip_if_too_few_cores() test.compile(v_flags2=["t/t_dpi_threads_c.cpp --threads-dpi all --no-threads-coarsen"]) # Similar to t_dpi_threads, which confirms that Verilator can prevent a # race between DPI import calls, this test confirms that the race exists # and that the DPI C code can detect it under --threads-dpi all # mode. # test.execute(fails=True) test.passes() verilator-5.042/test_regress/t/t_flag_define.vc0000644000542200017500000000051315101701376022165 0ustar mahmoudyfreeshell+define+D1A +define+D2A=VALA +define+D3A+D3B +define+D4A=VALA+D4B +define+D5A=VALA+D5B=VALB // Quotes do NOT escape the plus //+define+D5A="VALA+D5B"+D5C +define+STRING1="\"New String\"" +define+STRING2='"New String"' +define+STRING3=\"New\ String\" +define+LIT1=32'h600D600D +define+LIT2=32\'h600D600D +define+LIT3="32'h600D600D" verilator-5.042/test_regress/t/t_time_sc_sec.out0000644000542200017500000000022415101701376022415 0ustar mahmoudyfreeshell Warning: (W516) default time unit changed to time resolution Time scale of t is 1s / 1s [20] In top.t: Hi - expect this is 20 *-* All Finished *-* verilator-5.042/test_regress/t/t_vpi_onetime_cbs.v0000644000542200017500000000074015101701376022746 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 Wilson Snyder and Marlon James. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs input clk ); reg [31:0] count /*verilator public_flat_rd */; // Test loop initial begin count = 0; end always @(posedge clk) begin count <= count + 2; end endmodule : t verilator-5.042/test_regress/t/t_math_signed3_noopt.py0000755000542200017500000000107315101701376023553 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_math_signed3.v" test.compile(make_main=False, verilator_flags2=["-O0", "--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_clocking_bad4.v0000644000542200017500000000152715101701376022270 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; logic in, out; clocking cb1 @(posedge clk); input in; output out; endclocking int cyc = 0; always @(posedge clk) cyc <= cyc + 1; clocking cb2 @(negedge clk); input #cyc in; input #(-1) out; endclocking task write(output x); x = 1; endtask always ##1; always cb1.out = clk; assign cb1.out = clk; always write(cb1.out); always cb1.out <= @(posedge clk) 1; always cb1.out <= #1 1; always out <= ##1 1; always @(posedge clk) begin cb1.in = 1; $display(cb1.out); end endmodule verilator-5.042/test_regress/t/t_lint_stmtdly_bad.out0000644000542200017500000000067415101701376023505 0ustar mahmoudyfreeshell%Warning-STMTDLY: t/t_lint_stmtdly_bad.v:10:5: Ignoring delay on this statement due to --no-timing : ... note: In instance 't' 10 | #100 $finish; | ^ ... For warning description see https://verilator.org/warn/STMTDLY?v=latest ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_gate_elim_cycle.v0000644000542200017500000000113515101701376022705 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module GND(output G); assign G = 0; endmodule module CARRY2( output [1:0] CO, input CI, input [1:0] DI, S ); assign CO[0] = S[0] ? CI : DI[0]; assign CO[1] = S[1] ? CO[0] : DI[1]; endmodule module A; wire const0; wire ci; GND GND ( .G(const0) ); CARRY2 CARRY2 ( .CO(), .CI(ci), .DI({const0,const0}), .S({const0,const0}) ); endmodule verilator-5.042/test_regress/t/t_cover_expr_associative_array_class.v0000644000542200017500000000110315101701376026724 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Class1; int value0 = 7; endclass module t; initial begin int i = 0; Class1 q[int] = '{}; for (int j = 0; j < 15; j = j + 1) begin Class1 x = new; q[j] = x; end while (i < 15) begin if ((q[i].value0 > 8) || (q[i].value0 < 5)) $stop; i += 1; end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_clk_2in.py0000755000542200017500000000115515101701376021311 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename], vcs_flags2=['-assert']) test.execute() test.passes() verilator-5.042/test_regress/t/t_timing_func_join.py0000755000542200017500000000077115101701376023314 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--binary']) test.execute() test.passes() verilator-5.042/test_regress/t/t_class_param_nconst_bad.out0000644000542200017500000000116415101701376024623 0ustar mahmoudyfreeshell%Error: t/t_class_param_nconst_bad.v:12:17: Expecting expression to be constant, but can't convert a RAND to constant. : ... note: In instance 't' 12 | Cls #(.PARAM($random)) c; | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_class_param_nconst_bad.v:12:11: Can't convert defparam value to constant: Param 'PARAM' of 'Cls' : ... note: In instance 't' 12 | Cls #(.PARAM($random)) c; | ^~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_interface_down_inlcd.py0000755000542200017500000000112215101701376024122 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_down.v" test.compile(v_flags2=['+define+INLINE_C +define+INLINE_D'], verilator_flags2=['-trace']) test.execute() test.passes() verilator-5.042/test_regress/t/t_clocking_sched.py0000755000542200017500000000077215101701376022733 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_unopt_converge_unopt_bad.out0000644000542200017500000000112515101701376025231 0ustar mahmoudyfreeshell%Warning-UNOPTFLAT: t/t_unopt_converge.v:19:11: Signal unoptimizable: Circular combinational logic: 'x' 19 | output x; | ^ ... For warning description see https://verilator.org/warn/UNOPTFLAT?v=latest ... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message. t/t_unopt_converge.v:19:11: Example path: x t/t_unopt_converge.v:22:4: Example path: ALWAYS t/t_unopt_converge.v:19:11: Example path: x %Error: Exiting due to verilator-5.042/test_regress/t/t_interface_dearray_bad.py0000755000542200017500000000076615101701376024254 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_gen_index.v0000644000542200017500000000300515101701376021536 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Test generate index usage. // // The code illustrates a problem in Verilator's handling of constant // expressions inside generate indexes. // // This is a regression test against issue #517. // // **If you do not wish for your code to be released to the public // please note it here, otherwise:** // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 `define START 8 `define SIZE 4 `define END (`START + `SIZE) module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [`END-1:0] y; wire [`END-1:0] x; foo foo_i (.y (y), .x (x), .clk (clk)); always @(posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule // t module foo(output wire [`END-1:0] y, input wire [`END-1:0] x, input wire clk); function peek_bar; peek_bar = bar_inst[`START].i_bar.r; // this is ok peek_bar = bar_inst[`START + 1].i_bar.r; // this fails, should not. endfunction genvar g; generate for (g = `START; g < `END; g = g + 1) begin: bar_inst bar i_bar(.x (x[g]), .y (y[g]), .clk (clk)); end endgenerate endmodule : foo module bar(output wire y, input wire x, input wire clk); reg r = 0; assign y = r; always @(posedge clk) begin r = x ? ~x : y; end endmodule : bar verilator-5.042/test_regress/t/t_flag_nomod_bad.py0000755000542200017500000000076315101701376022707 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_opt_const.v0000644000542200017500000004540215101701376021615 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 Yutetsu TAKATSUKASA. // SPDX-License-Identifier: CC0-1.0 // This function always returns 0, so safe to take bitwise OR with any value. // Calling this function stops constant folding as Verialtor does not know // what this function returns. import "DPI-C" context function int c_fake_dependency(); module t(/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) logic o; // From test of Test.v // End of automatics wire [31:0] i = crc[31:0]; Test test(/*AUTOINST*/ // Outputs .o (o), // Inputs .clk (clk), .i (i[31:0])); // Aggregate outputs into a single result vector wire [63:0] result = {63'b0, o}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); $display("o %b", o); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc == 0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc < 10) begin sum <= '0; end else if (cyc < 99) begin end else begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h4c5aa8d19cd13750 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test(/*AUTOARG*/ // Outputs o, // Inputs clk, i ); input clk; input [31:0] i; logic [31:0] d; logic d0, d1, d2, d3, d4, d5, d6, d7; logic bug3182_out; logic bug3197_out; logic bug3445_out; logic bug3470_out; logic bug3509_out; wire bug3399_out0; wire bug3399_out1; logic bug3786_out; logic bug3824_out; logic bug4059_out; logic bug4832_out; logic bug4837_out; logic bug4857_out; logic bug4864_out; logic bug5186_out; output logic o; logic [19:0] tmp; assign o = ^tmp; always_ff @(posedge clk) begin d <= i; d0 <= i[0]; d1 <= i[1]; d2 <= i[2]; d3 <= i[3]; d4 <= i[4]; d5 <= i[5]; d6 <= i[6]; d7 <= i[7]; end always_ff @(posedge clk) begin // Cover more lines in V3Const.cpp tmp[0] <= (d0 || (!d0 && d1)) ^ ((!d2 && d3) || d2); // maatchOrAndNot() tmp[1] <= ((32'd2 ** i) & 32'h10) == 32'b0; // replacePowShift tmp[2] <= ((d0 & d1) | (d0 & d2))^ ((d3 & d4) | (d5 & d4)); // replaceAndOr() tmp[3] <= d0 <-> d1; // replaceLogEq() tmp[4] <= i[0] & (i[1] & (i[2] & (i[3] | d[4]))); // ConstBitOpTreeVisitor::m_frozenNodes tmp[5] <= bug3182_out; tmp[6] <= bug3197_out; tmp[7] <= bug3445_out; tmp[8] <= bug3470_out; tmp[9] <= bug3509_out; tmp[10]<= bug3399_out0; tmp[11]<= bug3399_out1; tmp[12]<= bug3786_out; tmp[13]<= bug3824_out; tmp[14]<= bug4059_out; tmp[15]<= bug4832_out; tmp[16]<= bug4837_out; tmp[17]<= bug4857_out; tmp[18]<= bug4864_out; tmp[19]<= bug5186_out; end bug3182 i_bug3182(.in(d[4:0]), .out(bug3182_out)); bug3197 i_bug3197(.clk(clk), .in(d), .out(bug3197_out)); bug3445 i_bug3445(.clk(clk), .in(d), .out(bug3445_out)); bug3470 i_bug3470(.clk(clk), .in(d), .out(bug3470_out)); bug3509 i_bug3509(.clk(clk), .in(d), .out(bug3509_out)); bug3399 i_bug3399(.clk(clk), .in(d), .out0(bug3399_out0), .out1(bug3399_out1)); bug3786 i_bug3786(.clk(clk), .in(d), .out(bug3786_out)); bug3824 i_bug3824(.clk(clk), .in(d), .out(bug3824_out)); bug4059 i_bug4059(.clk(clk), .in(d), .out(bug4059_out)); bug4832 i_bug4832(.clk(clk), .in(d), .out(bug4832_out)); bug4837 i_bug4837(.clk(clk), .in(d), .out(bug4837_out)); bug4857 i_bug4857(.clk(clk), .in(d), .out(bug4857_out)); bug4864 i_bug4864(.clk(clk), .in(d), .out(bug4864_out)); bug5186 i_bug5186(.clk(clk), .in(d), .out(bug5186_out)); bug5993 i_bug5993(.clk(clk), .in(d[10])); bug6016 i_bug6016(.clk(clk), .in(d[10])); endmodule module bug3182(in, out); input wire [4:0] in; output wire out; logic [4:0] bit_source; /* verilator lint_off WIDTH */ always @(in) bit_source = c_fake_dependency() | in; wire [5:0] tmp = bit_source; // V3Gate should inline this assign out = ~(tmp >> 5) & (bit_source == 5'd10); /* verilator lint_on WIDTH */ endmodule module bug3197(input wire clk, input wire [31:0] in, output out); logic [63:0] d; always_ff @(posedge clk) d <= {d[31:0], in[0] ? in : 32'b0}; wire tmp0 = (|d[38:0]); assign out = (d[39] | tmp0); endmodule // See issue #3445 // An unoptimized node is kept as frozen node, but its LSB and polarity were not saved. // AST of RHS of result0 looks as below: // AND(SHIFTR(AND(WORDSEL(ARRAYSEL(VARREF)), WORDSEL(ARRAYSEL(VARREF)))), 32'd11) // ~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~ // Two of WORDSELs are frozen nodes. They are under SHIFTR of 11 bits. // // Fixing issue #3445 needs to // 1. Take AstShiftR and AstNot into op count when diciding optimizable or not // (result0 and result2 in the test) // 2. Insert AstShiftR if LSB of the frozen node is not 0 (result1 in the test) // 3. Insert AstNot if polarity of the frozen node is false (resutl3 in the // test) module bug3445(input wire clk, input wire [31:0] in, output wire out); logic [127:0] d; always_ff @(posedge clk) d <= {d[95:0], in}; typedef struct packed { logic a; logic [ 2:0] b; logic [ 2:0] c; logic [ 1:0] d; logic [ 7:0] e; logic [31:0] f; logic [ 3:0] g; logic [31:0] h; logic i; logic [41:0] j; } packed_struct; packed_struct st[4]; // This is always 1'b0, but Verilator cannot notice it. // This signal helps to reveal wrong optimization of result2 and result3. logic zero; always_ff @(posedge clk) begin st[0] <= d; st[1] <= st[0]; st[2] <= st[1]; st[3] <= st[2]; zero <= c_fake_dependency() > 0; end logic result0, result1, result2, result3; always_ff @(posedge clk) begin // Cannot optimize further. result0 <= (st[0].g[0] & st[0].h[0]) & (in[0] == 1'b0); // There are redundant !in[0] terms. They should be simplified. result1 <= (!in[0] & (st[1].g[0] & st[1].h[0])) & ((in[0] == 1'b0) & !in[0]); // Cannot optimize further. result2 <= !(st[2].g[0] & st[2].h[0]) & (zero == 1'b0); // There are redundant zero terms. They should be simplified. result3 <= (!zero & !(st[3].g[0] & st[3].h[0])) & ((zero == 1'b0) & !zero); end assign out = result0 ^ result1 ^ (result2 | result3); endmodule // Bug3470 // CCast had been ignored in bit op tree optimization // Assume the following HDL input: // (^d[38:32]) ^ (^d[31:0]) // where d is logic [38:0] // ^d[31:0] becomes REDXOR(CCast(uint32_t, d)), // but CCast was ignored and interpreted as ^d[38:0]. // Finally (^d[38:32]) ^ (^d31:0]) was wrongly transformed to // (^d[38:32]) ^ (^d[38:0]) // -> (^d[38:32]) ^ ((^d[38:32]) ^ (^d[31:0])) // -> ^d[31:0] // Of course the correct result is ^d[38:0] = ^d module bug3470(input wire clk, input wire [31:0] in, output wire out); logic [38:0] d; initial d = 0; initial tmp = 0; initial expected = 0; always_ff @(posedge clk) d <= {d[6:0], in}; logic tmp, expected; always_ff @(posedge clk) begin tmp <= ^(d >> 32) ^ (^d[31:0]); expected <= ^d; end always @(posedge clk) if (tmp != expected) $stop; assign out = tmp; endmodule // Bug3509 // Only bit range of "var" was considered in // "comp == (mask & var)" // and // "comp != (mask & var)" // // It caused wrong result if "comp" has wider bit width because // upper bit of "comp" was ignored. // // If "comp" has '1' in upper bit range than "var", // the result is constant after optimization. module bug3509(input wire clk, input wire [31:0] in, output reg out); reg [2:0] r0; always_ff @(posedge clk) r0 <= in[2:0]; wire [3:0] w1_0 = {1'b0, in[2:0]}; wire [3:0] w1_1 = {1'b0, r0}; wire tmp[4]; // tmp[0:1] is always 0 because w1[3] == 1'b0 // tmp[2:3] is always 1 because w1[3] == 1'b0 assign tmp[0] = w1_0[3:2] == 2'h2 && w1_0[1:0] != 2'd3; assign tmp[1] = w1_1[3:2] == 2'h2 && w1_1[1:0] != 2'd3; assign tmp[2] = w1_0[3:2] != 2'h2 || w1_0[1:0] == 2'd3; assign tmp[3] = w1_1[3:2] != 2'h2 || w1_1[1:0] == 2'd3; always_ff @(posedge clk) begin out <= tmp[0] | tmp[1] | !tmp[2] | !tmp[3]; end always @(posedge clk) begin if(tmp[0]) begin $display("tmp[0] != 0"); $stop; end if(tmp[1]) begin $display("tmp[1] != 0"); $stop; end if(!tmp[2]) begin $display("tmp[2] != 1"); $stop; end if(!tmp[3]) begin $display("tmp[3] != 1"); $stop; end end endmodule // Bug3399 // replaceShiftSame() in V3Const.cpp optimizes // Or(Shift(ll,CONSTlr),Shift(rl,CONSTrr==lr)) -> Shift(Or(ll,rl),CONSTlr) // (Or/And may also be reversed) // // dtype of Or after the transformation must be as same as ll and rl, but was dtype of Or BEFORE transformation. // When the result of Shift was 1 bit width, bit op tree optimization // optimized the tree even though the graph needs more width. // Remember that the target of bit op tree optimization is 1 bit width. module bug3399(input wire clk, input wire [31:0] in, inout wire out0, inout wire out1); logic [1:0] driver = '0; logic [1:0] d; always_ff @(posedge clk) begin driver <= 2'b11; d <= in[1:0]; end assign out0 = driver[0] ? d[0] : 1'bz; assign out1 = driver[1] ? d[1] : 1'bz; endmodule // Bug3786 // When V3Expand is skipped, wide number is not split by WORDSEL. // Bit op tree opt. expects that bit width is 64 bit at most. module bug3786(input wire clk, input wire [31:0] in, inout wire out); logic [127:0] d0, d1; always_ff @(posedge clk) begin d0 <= {d0[127:32], in}; d1 <= d1; end assign out = ^{d1, d0}; endmodule // Bug3824 // When a variable is shift-out, the term becomes 0. // Such behavior was not considered in Or-tree. module bug3824(input wire clk, input wire [31:0] in, output wire out); logic [5:0] a; always_ff @(posedge clk) a <= in[5:0]; logic [6:0] b; assign b = {1'b0, a}; logic c_and; assign c_and = (b[6]); // c_and is always 1'b0 always_comb if (c_and != 1'b0) $stop; logic d_and; always_ff @(posedge clk) d_and <= (&a) & c_and; logic c_or; assign c_or = ~(b[6]); // c_or is always 1'b1 as b[6] is 1'b0 always_comb if (c_or != 1'b1) $stop; logic d_or; always_ff @(posedge clk) d_or <= (|a) | c_or; logic c_xor; assign c_xor = ^(b[6]); // c_xor is always 1'b0 always_comb if (c_xor != 1'b0) $stop; logic d_xor; always_ff @(posedge clk) d_xor <= (^a) ^ c_xor; assign out = d_and ^ d_or ^ d_xor; endmodule /// See issue #4059 // Frozen node in an xor tree held unnecessary poloarity. // In an XOR tree, the entire result is flipped if necessary according to // total polarity. This bug was introduced when fixing issue #3445. module bug4059(input wire clk, input wire [31:0] in, output wire out); wire [127:0] words_i; for (genvar i = 0; i < $bits(in); ++i) begin always_ff @(posedge clk) words_i[4 * i +: 4] <= {4{in[i]}}; end wire _000_ = ~(words_i[104] ^ words_i[96]); wire _001_ = ~(words_i[88] ^ words_i[80]); wire _002_ = ~(_000_ ^ _001_); wire _003_ = words_i[72] ^ words_i[64]; wire _004_ = words_i[120] ^ words_i[112]; wire _005_ = ~(_003_ ^ _004_); wire _006_ = ~(_002_ ^ _005_); wire _007_ = words_i[40] ^ words_i[32]; wire _008_ = ~(words_i[24] ^ words_i[16]); wire _009_ = ~(_007_ ^ _008_); wire _010_ = words_i[8] ^ words_i[0]; wire _011_ = words_i[56] ^ words_i[48]; wire _012_ = ~(_010_ ^ _011_); wire _013_ = ~(_009_ ^ _012_); assign out = ~(_006_ ^ _013_); endmodule /// See issue #4832 // !(d[32 + 3] & in[3]) & d[32 + 22] // was wrongly transformed to // !d[32 + 3] & d[32 + 22] & !in[3] // A subtree under NOT should be untouched, but was not. // Testing OR subtree too. module bug4832(input wire clk, input wire [31:0] in, output out); logic [95:0] d; always_ff @(posedge clk) d <= {d[63:0], in}; logic [31:0] tmp_and; logic [31:0] tmp_or; logic result_and; logic result_or; assign tmp_and = (d[63:32] & in) >> 3; assign tmp_or = (d[63:32] | in) >> 8; always_ff @(posedge clk) begin result_and <= !tmp_and[0] & d[32 + 22]; result_or <= !tmp_or[0] | d[32 + 21]; end assign out = result_and ^ result_or; endmodule /// See issue #4837 and $4841 // replaceShiftOp() in V3Const did not update widthMin, then bit-op-tree opt. // was wrongly triggered for the subtree. // replaceShiftOp() transforms as below: // SHIFT(AND(a,b),CONST)->AND(SHIFT(a,CONST),SHIFT(b,CONST)) // AND after the transformation must have same minWidth as the original SHIFT // e.g. SHIFTL(AND(a, b), 1) => AND(SHIFTL(a, 1), SHIFTL(b, 1)) // AND in the result must have 1 bit larger widthMin than the original AND module bug4837(input wire clk, input wire [31:0] in, output out); logic [95:0] d; always_ff @(posedge clk) d <= {d[63:0], in}; wire celloutsig_0z; wire [1:0] celloutsig_1z; wire celloutsig_2z; wire [95:0] out_data; assign celloutsig_0z = d[83] < d[74]; assign celloutsig_1z = { d[54], celloutsig_0z } & { d[42], celloutsig_0z }; assign celloutsig_2z = d[65:64] < d[83:82]; assign { out_data[33:32], out_data[0] } = { celloutsig_1z, celloutsig_2z }; assign out = out_data[33] ^ out_data[32] ^ out_data[0]; endmodule // See issue #4857 // (1'b0 != (!a)) | b was wrongly optimized to // (a | b) & 1'b1 // polarity was not considered when traversing NEQ under AND/OR tree module bug4857(input wire clk, input wire [31:0] in, output out); logic [95:0] d; always_ff @(posedge clk) d <= {d[63:0], in}; wire celloutsig_12z; wire celloutsig_15z; wire celloutsig_17z; wire celloutsig_4z; wire celloutsig_67z; wire celloutsig_9z; logic [95:0] in_data; logic result; // verilator lint_off UNDRIVEN wire [95:0] out_data; // verilator lint_on UNDRIVEN assign celloutsig_4z = ~(in_data[72] & in_data[43]); // 1 assign celloutsig_67z = | { in_data[64], celloutsig_12z }; // 0 assign celloutsig_15z = in_data[43] & ~(celloutsig_4z); // 0 assign celloutsig_9z = celloutsig_17z & ~(in_data[43]); // 00000000 assign celloutsig_17z = celloutsig_15z & ~(in_data[43]);// 0 assign celloutsig_12z = celloutsig_4z != celloutsig_9z; // 1 assign out_data[32] = celloutsig_67z; // 1 assign in_data = d; always_ff @ (posedge clk) result <= out_data[32]; assign out = result; endmodule // See issue #4864 // (((in_data[32*1] & 32'h3000000 != 0) | (in_data[32*2 + 25])| (sig_b != 9'b0)) >> 4) | sig_b[2] // was wrongly optimized as below. // ((in_data[32] & 32'h30000000) != 0 >> 0) | (in_data[32*2 + 29])|((sig_b & 9'h1f4) != 0) // The result of EQ/NE is just 1 bit width, so EQ/NE under SHFITR cannot be treated as a multi-bit term // such as AND/OR. module bug4864(input wire clk, input wire [31:0] in, output wire out); logic [159:0] clkin_data = '0; logic [95:0] in_data = '0; int cycle = 0; always @(posedge clk) begin if (in[0]) begin cycle <= cycle + 1; if (cycle == 0) begin clkin_data <= 160'hFFFFFFFF_00000000_00000000_00000000_00000000; end else if (cycle == 1) begin in_data <= 96'h00000000_FFFFFFFF_00000000; end else begin clkin_data <= 160'hFFFFFFFF_00000000_00000000_00000000_FFFFFFFF; end end end wire moveme; wire sig_a; reg [8:0] sig_b; wire sig_c; wire [20:0] sig_d; reg sig_e; logic myfirst, mysecond; assign myfirst = 1'b0; assign mysecond = 1'b0; always_ff @(posedge clkin_data[0], posedge myfirst, posedge mysecond) if (myfirst) sig_e <= 1'b0; else if (mysecond) sig_e <= 1'b1; else if (clkin_data[128]) sig_e <= sig_d[7]; always_ff @(posedge clkin_data[128]) sig_b <= '0; assign sig_a = in_data[89]; // 1'b0; assign sig_c = | { in_data[61:60], sig_b, sig_a }; assign sig_d = ~ { moveme, 6'b0, sig_b, 1'b0, sig_c, 3'b0 }; assign moveme = 1'b1; assign out = sig_e; endmodule // See issue #5168 // BitOpTree removes d[38] ^ d[38] correctly, but adds a cleaning AND as // (d[31] & 32'b1) even though d is 64 bit width. // matchMaskedShift() thinks the cleaning AND is redundant because the mask // value is 32 bit width. module bug5186(input wire clk, input wire [31:0] in, output out); logic [63:0] d; always_ff @(posedge clk) d <= {d[31:0], in}; wire bad; assign bad = {d[38:32], d[38] ^ d[31] ^ d[38]} != d[38:31]; logic result; always_ff @ (posedge clk) result <= bad; assign out = result; endmodule // See issue #5993 // "in4[18]" is just one bit width, so " >> 8'd1" shifts out the bit. // BitOpTree ignored implicit "& 1". It caused the bug" module bug5993(input wire clk, input wire in); reg in3; reg [23:16] in4; task automatic checkd(logic gotv, logic expv); if ((gotv) !== (expv)) begin $write("%%Error: got=%0d exp=%0d\n", gotv, expv); $stop; end endtask // verilator lint_off WIDTH wire wire_2 = in3 ? {4{14'b010111101}} : (in4[18] >> 8'b1); // verilator lint_on WIDTH always @(posedge clk) begin in3 <= '0; in4 <= in ? 8'b00111__0__10 : 8'b00111__1__10; checkd(wire_2, 1'b0); end endmodule // See issue #6016 // When traversing a tree, a signal may be shifted out. // Then the polarity has to be cleared, but was not. // "(!in[18]) > 1" should be 0, but was not. module bug6016(input wire clk, input wire in); reg in0; reg signed [7:0] in4; wire [1:0] wire_0; wire out20; // verilator lint_off WIDTH assign wire_0 = in4[0:0] ? ({{7{in4[3:1]}}, 12'd201} & 2'h2) : (!(in0) >> 9'b1111); // verilator lint_on WIDTH assign out20 = wire_0[0:0]; logic in_s1 = 1'b0; always @(posedge clk) begin in_s1 <= in; if (in) begin in4 <= 8'b1111_1110; in0 <= 1'b0; end if (in_s1) begin if (out20 != 1'b0) $stop; end end endmodule verilator-5.042/test_regress/t/t_lint_warn_line_bad.py0000755000542200017500000000115615101701376023603 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint( # See also t/t_lint_warn_incfile1_bad # See also t/t_vlt_warn_file_bad verilator_flags2=["--no-std"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_preproc_stringend_bad.out0000644000542200017500000000027115101701376024477 0ustar mahmoudyfreeshell%Error: t/t_preproc_stringend_bad.v:8:1: Unterminated string ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_mem.py0000755000542200017500000000073415101701376020550 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_opt_merge_cond_no_extend.py0000755000542200017500000000106115101701376025013 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(verilator_flags2=["--stats"]) test.file_grep(test.stats, r'Optimizations, MergeCond merges\s+(\d+)', 0) test.passes() verilator-5.042/test_regress/t/t_func_void_bad.py0000755000542200017500000000076615101701376022561 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_clk_concat.v0000644000542200017500000000362315101701376021704 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty. // SPDX-License-Identifier: CC0-1.0 module some_module ( input wrclk ); logic [ 1 : 0 ] some_state; logic [1:0] some_other_state; always @(posedge wrclk) begin case (some_state) 2'b11: if (some_other_state == 0) some_state <= 2'b00; default: $display ("This is a display statement"); endcase if (wrclk) some_other_state <= 0; end endmodule `define BROKEN module t1( input [3:0] i_clks, input i_clk0, input i_clk1 ); some_module some_module ( `ifdef BROKEN .wrclk (i_clks[3]) `else .wrclk (i_clk1) `endif ); endmodule module t2( input [2:0] i_clks, input i_clk0, input i_clk1, input i_clk2, input i_data ); logic [3:0] the_clks; logic data_q; assign the_clks = {i_clk1, i_clk2, i_clk1, i_clk0}; always @(posedge i_clk0) begin data_q <= i_data; end t1 t1 ( .i_clks (the_clks), .i_clk0 (i_clk0), .i_clk1 (i_clk1) ); endmodule module t( `ifdef ATTRIBUTES input clk0 /*verilator clocker*/, input clk1 /*verilator clocker*/, input clk2 /*verilator clocker*/, `else input clk0, input clk1, input clk2, `endif input data_in ); logic [2:0] clks; assign clks = {1'b0, clk1, clk0}; t2 t2 ( .i_clks (clks), .i_clk0 (clk0), .i_clk1 (clk1), .i_clk2 (clk2), .i_data (data_in) ); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_timing_zerodly_consecutive.py0000755000542200017500000000077115101701376025441 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_randomize.v0000644000542200017500000000325215101701376021572 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Packet; rand int header; // 0..7 rand int length; // 0..15 rand int sublength; // 0..15 rand bit if_4; rand bit iff_5_6; /*rand*/ int array[2]; // 2,4,6 // TODO: add rand when supported constraint empty {} constraint size { header > 0 && header <= 7; length <= 15; length >= header; length dist { [0:1], [2:5] :/ 2, 6 := 6, 7 := 10, 1}; } constraint ifs { if (header > 4) { if_4 == '1; } if (header == 5 || header == 6) { iff_5_6 == '1; } else { iff_5_6 == '0; } } constraint arr_uniq { foreach (array[i]) { array[i] inside {2, 4, 6}; } unique { array[0], array[1] }; } constraint order { solve length before header; } constraint dis { soft sublength; disable soft sublength; sublength <= length; } endclass module t; Packet p; initial begin int v; bit if_4 = '0; // TODO not testing constrained values v = p.randomize(); if (v != 1) $stop; v = p.randomize() with {}; if (v != 1) $stop; v = p.randomize() with { if_4 == local::if_4; header == 2; }; if (v != 1) $stop; // verilator lint_off WIDTH assert(p.randomize && p.randomize); // No parens, math // verilator lint_on WIDTH // TODO not testing other randomize forms as unused in UVM $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_cast_class.py0000755000542200017500000000073415101701376022111 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_math_pow4.py0000755000542200017500000000073415101701376021674 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_func_lib.v0000644000542200017500000000047615101701376021370 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_lint_comb_bad.py0000755000542200017500000000076315101701376022550 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dynarray_bad.v0000644000542200017500000000052015101701376022234 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; integer a[]; string s; initial begin s = "str"; a = new [s]; // Bad end endmodule verilator-5.042/test_regress/t/t_func_inconly.py0000755000542200017500000000073415101701376022460 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_queue_back.v0000644000542200017500000000155415101701376021711 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; int q[$]; int r; function void set_val(ref int lhs, input int rhs); lhs = rhs; endfunction initial begin q = { 60, 50, 40 }; set_val(q[$-1], 30); q[$-2] = 20; r = q[$]; if (r != 40) $stop; r = q[$-1]; if (r != 30) $stop; q = q[0:$-1]; // void'(q.pop_back()) or q.delete(q.size-1) if (q.size != 2) $stop; if (q[0] != 20) $stop; if (q[1] != 30) $stop; q = { 20, 30, 40 }; q = q[$-1:$]; if (q.size != 2) $stop; if (q[0] != 30) $stop; if (q[1] != 40) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_property_recursive_unsup.py0000755000542200017500000000102215101701376025166 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert'], fails=True) test.passes() verilator-5.042/test_regress/t/t_interface_asvar_bad.out0000644000542200017500000000117215101701376024105 0ustar mahmoudyfreeshell%Error: t/t_interface_asvar_bad.v:29:16: Operator ASSIGN expected non-interface on Assign RHS but 'itf' is an interface. : ... note: In instance 't.source' 29 | getter = itf; | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_interface_asvar_bad.v:30:23: Operator ADD expected non-interface on RHS but 'itf' is an interface. : ... note: In instance 't.source' 30 | getter = 4'd3 + itf; | ^~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_math_repl3_bad.out0000644000542200017500000000442615101701376023014 0ustar mahmoudyfreeshell%Error: t/t_math_repl3_bad.v:14:50: Replication value of < 0 or X/Z not legal (IEEE 1800-2023 11.4.12.1): '32'hfffffff8' : ... note: In instance 't' 14 | link_data_reg_in = {{((NUM_LANES - 2) * 8) {1'b0}}, link_data_reg[15:8]}; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Warning-SELRANGE: t/t_math_repl3_bad.v:14:72: Selection index out of range: 15:8 outside 7:0 : ... note: In instance 't' 14 | link_data_reg_in = {{((NUM_LANES - 2) * 8) {1'b0}}, link_data_reg[15:8]}; | ^ ... For warning description see https://verilator.org/warn/SELRANGE?v=latest ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Warning-WIDTHTRUNC: t/t_math_repl3_bad.v:14:24: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's REPLICATE generates 9 bits. : ... note: In instance 't' 14 | link_data_reg_in = {{((NUM_LANES - 2) * 8) {1'b0}}, link_data_reg[15:8]}; | ^ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: t/t_math_repl3_bad.v:16:19: Replication value of < 0 or X/Z not legal (IEEE 1800-2023 11.4.12.1): '32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz' : ... note: In instance 't' 16 | other = {32'bz{1'b1}}; | ^ %Warning-WIDTHEXPAND: t/t_math_repl3_bad.v:16:11: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS's REPLICATE generates 1 bits. : ... note: In instance 't' 16 | other = {32'bz{1'b1}}; | ^ ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_trace_timescale.out0000644000542200017500000000150315101701376023265 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ms $end $scope module top $end $var wire 1 # clk $end $scope module t $end $var wire 1 # clk $end $var wire 32 $ cyc [31:0] $end $upscope $end $upscope $end $enddefinitions $end #0 0# b00000000000000000000000000000000 $ #10 1# b00000000000000000000000000000001 $ #15 0# #20 1# b00000000000000000000000000000010 $ #25 0# #30 1# b00000000000000000000000000000011 $ #35 0# #40 1# b00000000000000000000000000000100 $ #45 0# #50 1# b00000000000000000000000000000101 $ #55 0# #60 1# b00000000000000000000000000000110 $ #65 0# #70 1# b00000000000000000000000000000111 $ #75 0# #80 1# b00000000000000000000000000001000 $ #85 0# #90 1# b00000000000000000000000000001001 $ #95 0# #100 1# b00000000000000000000000000001010 $ #105 0# #110 1# b00000000000000000000000000001011 $ verilator-5.042/test_regress/t/t_display_mcd.v0000644000542200017500000000066115101701376022073 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2015 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin $fwrite(32'h8000_0001, "To stdout\n"); $fflush(32'h8000_0001); $fwrite(32'h8000_0002, "To stderr\n"); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_lint_eofnewline.py0000755000542200017500000000142215101701376023146 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = test.obj_dir + "/t_lint_eofnewline_bad.v" def gen(filename): with open(filename, 'w', encoding="utf8") as fh: # pylint: disable=unused-variable pass # Empty file should not EOFLINE warn gen(test.top_filename) test.lint(verilator_flags2=["-E -Wall -Wno-DECLFILENAME"], expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_clocking_timing1.py0000755000542200017500000000104515101701376023207 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_clocking_timing.v" test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_nullport_bad.out0000644000542200017500000001246115101701376023661 0ustar mahmoudyfreeshell%Warning-NULLPORT: t/t_lint_nullport_bad.v:23:13: Null port on module (perhaps extraneous comma) 23 | module t5(a,); | ^ ... For warning description see https://verilator.org/warn/NULLPORT?v=latest ... Use "/* verilator lint_off NULLPORT */" and lint_on around source to disable this message. %Warning-NULLPORT: t/t_lint_nullport_bad.v:27:13: Null port on module (perhaps extraneous comma) 27 | module t6(a,,); | ^ %Warning-NULLPORT: t/t_lint_nullport_bad.v:27:14: Null port on module (perhaps extraneous comma) 27 | module t6(a,,); | ^ %Warning-NULLPORT: t/t_lint_nullport_bad.v:31:15: Null port on module (perhaps extraneous comma) 31 | module t7(a,b,); | ^ %Warning-NULLPORT: t/t_lint_nullport_bad.v:35:15: Null port on module (perhaps extraneous comma) 35 | module t8(a,b,,); | ^ %Warning-NULLPORT: t/t_lint_nullport_bad.v:35:16: Null port on module (perhaps extraneous comma) 35 | module t8(a,b,,); | ^ %Warning-NULLPORT: t/t_lint_nullport_bad.v:39:13: Null port on module (perhaps extraneous comma) 39 | module t9(a,,b); | ^ %Warning-NULLPORT: t/t_lint_nullport_bad.v:43:14: Null port on module (perhaps extraneous comma) 43 | module t10(a,,b,); | ^ %Warning-NULLPORT: t/t_lint_nullport_bad.v:43:17: Null port on module (perhaps extraneous comma) 43 | module t10(a,,b,); | ^ %Warning-NULLPORT: t/t_lint_nullport_bad.v:47:14: Null port on module (perhaps extraneous comma) 47 | module t11(a,,b,,); | ^ %Warning-NULLPORT: t/t_lint_nullport_bad.v:47:17: Null port on module (perhaps extraneous comma) 47 | module t11(a,,b,,); | ^ %Warning-NULLPORT: t/t_lint_nullport_bad.v:47:18: Null port on module (perhaps extraneous comma) 47 | module t11(a,,b,,); | ^ %Warning-NULLPORT: t/t_lint_nullport_bad.v:51:12: Null port on module (perhaps extraneous comma) 51 | module t12(,a,,b); | ^ %Warning-NULLPORT: t/t_lint_nullport_bad.v:51:15: Null port on module (perhaps extraneous comma) 51 | module t12(,a,,b); | ^ %Warning-NULLPORT: t/t_lint_nullport_bad.v:55:12: Null port on module (perhaps extraneous comma) 55 | module t13(,a,,b,); | ^ %Warning-NULLPORT: t/t_lint_nullport_bad.v:55:15: Null port on module (perhaps extraneous comma) 55 | module t13(,a,,b,); | ^ %Warning-NULLPORT: t/t_lint_nullport_bad.v:55:18: Null port on module (perhaps extraneous comma) 55 | module t13(,a,,b,); | ^ %Warning-NULLPORT: t/t_lint_nullport_bad.v:59:12: Null port on module (perhaps extraneous comma) 59 | module t14(,a,,b,,); | ^ %Warning-NULLPORT: t/t_lint_nullport_bad.v:59:15: Null port on module (perhaps extraneous comma) 59 | module t14(,a,,b,,); | ^ %Warning-NULLPORT: t/t_lint_nullport_bad.v:59:18: Null port on module (perhaps extraneous comma) 59 | module t14(,a,,b,,); | ^ %Warning-NULLPORT: t/t_lint_nullport_bad.v:59:19: Null port on module (perhaps extraneous comma) 59 | module t14(,a,,b,,); | ^ %Warning-NULLPORT: t/t_lint_nullport_bad.v:63:12: Null port on module (perhaps extraneous comma) 63 | module t15(,,a,,b); | ^ %Warning-NULLPORT: t/t_lint_nullport_bad.v:63:13: Null port on module (perhaps extraneous comma) 63 | module t15(,,a,,b); | ^ %Warning-NULLPORT: t/t_lint_nullport_bad.v:63:16: Null port on module (perhaps extraneous comma) 63 | module t15(,,a,,b); | ^ %Warning-NULLPORT: t/t_lint_nullport_bad.v:67:12: Null port on module (perhaps extraneous comma) 67 | module t16(,,a,,b,); | ^ %Warning-NULLPORT: t/t_lint_nullport_bad.v:67:13: Null port on module (perhaps extraneous comma) 67 | module t16(,,a,,b,); | ^ %Warning-NULLPORT: t/t_lint_nullport_bad.v:67:16: Null port on module (perhaps extraneous comma) 67 | module t16(,,a,,b,); | ^ %Warning-NULLPORT: t/t_lint_nullport_bad.v:67:19: Null port on module (perhaps extraneous comma) 67 | module t16(,,a,,b,); | ^ %Warning-NULLPORT: t/t_lint_nullport_bad.v:71:12: Null port on module (perhaps extraneous comma) 71 | module t17(,,a,,b,,); | ^ %Warning-NULLPORT: t/t_lint_nullport_bad.v:71:13: Null port on module (perhaps extraneous comma) 71 | module t17(,,a,,b,,); | ^ %Warning-NULLPORT: t/t_lint_nullport_bad.v:71:16: Null port on module (perhaps extraneous comma) 71 | module t17(,,a,,b,,); | ^ %Warning-NULLPORT: t/t_lint_nullport_bad.v:71:19: Null port on module (perhaps extraneous comma) 71 | module t17(,,a,,b,,); | ^ %Warning-NULLPORT: t/t_lint_nullport_bad.v:71:20: Null port on module (perhaps extraneous comma) 71 | module t17(,,a,,b,,); | ^ %Warning-NULLPORT: t/t_lint_nullport_bad.v:75:12: Null port on module (perhaps extraneous comma) 75 | module t18(,); | ^ %Warning-NULLPORT: t/t_lint_nullport_bad.v:75:13: Null port on module (perhaps extraneous comma) 75 | module t18(,); | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_gen_cond_const.py0000755000542200017500000000100515101701376022744 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--language 1364-2001"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_array_in_struct.v0000644000542200017500000000322015101701376023005 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 //bug991 module t; typedef struct { logic [31:0] arr [3:0]; } a_t; typedef struct { logic [31:0] arr [0:3]; } b_t; a_t array_assign; a_t array_other; b_t larray_assign; b_t larray_other; initial begin array_assign.arr[0] = 32'd1; array_assign.arr[3:1] = '{32'd4, 32'd3, 32'd2}; array_other.arr[0] = array_assign.arr[0]+10; array_other.arr[3:1] = array_assign.arr[3:1]; if (array_other.arr[0] != 11) $stop; if (array_other.arr[1] != 2) $stop; if (array_other.arr[2] != 3) $stop; if (array_other.arr[3] != 4) $stop; larray_assign.arr[0] = 32'd1; larray_assign.arr[1:3] = '{32'd4, 32'd3, 32'd2}; larray_other.arr[0] = larray_assign.arr[0]+10; larray_other.arr[1:3] = larray_assign.arr[1:3]; if (larray_other.arr[0] != 11) $stop; if (larray_other.arr[1] != 4) $stop; if (larray_other.arr[2] != 3) $stop; if (larray_other.arr[3] != 2) $stop; larray_other.arr = '{5, 6, 7, 8}; if (larray_other.arr[0] != 5) $stop; if (larray_other.arr[1] != 6) $stop; if (larray_other.arr[2] != 7) $stop; if (larray_other.arr[3] != 8) $stop; larray_other.arr = larray_assign.arr; if (larray_other.arr[0] != 1) $stop; if (larray_other.arr[1] != 4) $stop; if (larray_other.arr[2] != 3) $stop; if (larray_other.arr[3] != 2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_display_bad.v0000644000542200017500000000077515101701376022064 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg [40:0] disp; initial disp = 41'ha_bbbb_cccc; initial begin // Display formatting $display("%x"); // Too few $display("%x",disp,disp); // Too many $display("%q"); // Bad escape $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_event_control.out0000644000542200017500000000147715101701376023034 0ustar mahmoudyfreeshell%Error-NOTIMING: t/t_event_control.v:14:7: Event control statement in this location requires --timing : ... note: In instance 't' : ... With --no-timing, suggest have one event control statement per procedure, at the top of the procedure 14 | @(clk); | ^ ... For error description see https://verilator.org/warn/NOTIMING?v=latest %Error-NOTIMING: t/t_event_control.v:16:7: Event control statement in this location requires --timing : ... note: In instance 't' : ... With --no-timing, suggest have one event control statement per procedure, at the top of the procedure 16 | @(clk); | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_var_escape.out0000644000542200017500000000414115101701376022252 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $var wire 1 # clk $end $var wire 1 $ escaped_normal $end $var wire 1 % double__underscore $end $var wire 1 & 9num $end $var wire 1 ' bra[ket]slash/dash-colon:9backslash\done $end $scope module t $end $var wire 1 # clk $end $var wire 32 ( cyc [31:0] $end $var wire 1 $ escaped_normal $end $var wire 1 % double__underscore $end $var wire 1 $ underscore_at_the_end_ $end $var wire 1 $ double__underscore_at_the_end__ $end $var wire 1 & 9num $end $var wire 1 ' bra[ket]slash/dash-colon:9backslash\done $end $var wire 1 $ wire $end $var wire 1 $ check_alias $end $var wire 1 $ check:alias $end $var wire 1 ) check;alias $end $var wire 32 * a0.cyc [31:0] $end $var wire 32 * other.cyc [31:0] $end $scope module a0 $end $var wire 32 ( cyc [31:0] $end $upscope $end $scope module mod.with_dot $end $var wire 32 ( cyc [31:0] $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 0# 1$ 1% 1& 1' b00000000000000000000000000000001 ( 0) b11111111111111111111111111111110 * #10 1# 0$ 0% 0& 0' b00000000000000000000000000000010 ( 1) b11111111111111111111111111111101 * #15 0# #20 1# 1$ 1% 1& 1' b00000000000000000000000000000011 ( 0) b11111111111111111111111111111100 * #25 0# #30 1# 0$ 0% 0& 0' b00000000000000000000000000000100 ( 1) b11111111111111111111111111111011 * #35 0# #40 1# 1$ 1% 1& 1' b00000000000000000000000000000101 ( 0) b11111111111111111111111111111010 * #45 0# #50 1# 0$ 0% 0& 0' b00000000000000000000000000000110 ( 1) b11111111111111111111111111111001 * #55 0# #60 1# 1$ 1% 1& 1' b00000000000000000000000000000111 ( 0) b11111111111111111111111111111000 * #65 0# #70 1# 0$ 0% 0& 0' b00000000000000000000000000001000 ( 1) b11111111111111111111111111110111 * #75 0# #80 1# 1$ 1% 1& 1' b00000000000000000000000000001001 ( 0) b11111111111111111111111111110110 * #85 0# #90 1# 0$ 0% 0& 0' b00000000000000000000000000001010 ( 1) b11111111111111111111111111110101 * #95 0# #100 1# 1$ 1% 1& 1' b00000000000000000000000000001011 ( 0) b11111111111111111111111111110100 * verilator-5.042/test_regress/t/t_sys_file_basic.v0000644000542200017500000002604515101701376022565 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" `define ratio_error(a,b) (((a)>(b) ? ((a)-(b)) : ((b)-(a))) /(a)) `define stop $stop `define checkr(gotv,expv) do if (`ratio_error((gotv),(expv))>0.0001) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t; integer file; integer file_a[1]; integer chars; reg [1*8:1] letterl; reg [8*8:1] letterq; reg signed [8*8:1] letterqs; reg [16*8:1] letterw; reg [16*8:1] letterz; real r; string s; reg [16*8:1] si; integer i; reg [7:0] v_a,v_b,v_c,v_d; reg [31:0] v_worda; reg [31:0] v_wordb; integer v_length, v_off; wire signed [16:0] wire17 = 17'h1ffff; logic signed [16:0] scan17; `ifdef TEST_VERBOSE `define verbose 1'b1 `else `define verbose 1'b0 `endif initial begin // Display formatting `ifdef verilator if (file != 0) $stop; $fwrite(file, "Never printed, file closed\n"); if (!$feof(file)) $stop; `endif `ifdef AUTOFLUSH // The "w" is required so we get a FD not a MFD file = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_file_autoflush.log"},"w"); `else // The "w" is required so we get a FD not a MFD file = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_file_basic_test.log"},"w"); `endif if ($feof(file)) $stop; $fdisplay(file, "[%0t] hello v=%x", $time, 32'h12345667); $fwrite(file, "[%0t] %s\n", $time, "Hello2"); i = 12; $fwrite(file, "d: "); $fwrite(file, i); $fwrite(file, " "); $fdisplay(file, i); $fdisplay(file); $fwriteh(file, "h: "); $fwriteh(file, i); $fwriteh(file, " "); $fdisplayh(file, i); $fdisplayh(file); $fwriteo(file, "o: "); $fwriteo(file, i); $fwriteo(file, " "); $fdisplayo(file, i); $fdisplayo(file); $fwriteb(file, "b: "); $fwriteb(file, i); $fwriteb(file, " "); $fdisplayb(file, i); $fdisplayb(file); $fflush(file); $fflush(); $fflush; $fclose(file); $fwrite(file, "Never printed, file closed\n"); begin // Check for opening errors // The "r" is required so we get a FD not a MFD file = $fopen("DOES_NOT_EXIST","r"); if (|file) $stop; // Should not exist, IE must return 0 // Check error function s = ""; i = $ferror(file, s); `checkh(i, 2); `checks(s, "No such file or directory"); si = "xx"; i = $ferror(file, si); `checkh(i, 2); end begin // Check quadword access; a little strange, but it's legal to open "." // Also checks using array reference file_a[0] = $fopen(".","r"); if (file_a[0] == 0) $stop; $fclose(file_a[0]); end begin // Check read functions w/string s = "t/t_sys_file_basic_input.dat"; file = $fopen(s,"r"); if ($feof(file)) $stop; $fclose(file); end begin // Check read functions file = $fopen("t/t_sys_file_basic_input.dat","r"); if ($feof(file)) $stop; // $fgetc if ($fgetc(file) != "h") $stop; if ($fgetc(file) != "i") $stop; if ($fgetc(file) != "\n") $stop; // $ungetc if ($ungetc("x", file) != 0) $stop; if ($fgetc(file) != "x") $stop; // $fgets chars = $fgets(letterl, file); if (`verbose) $write("c=%0d l=%s\n", chars, letterl); if (chars != 1) $stop; if (letterl != "l") $stop; chars = $fgets(letterq, file); if (`verbose) $write("c=%0d q=%x=%s", chars, letterq, letterq); // Output includes newline if (chars != 5) $stop; if (letterq != "\0\0\0quad\n") $stop; letterw = "5432109876543210"; chars = $fgets(letterw, file); if (`verbose) $write("c=%0d w=%s", chars, letterw); // Output includes newline if (chars != 10) $stop; if (letterw != "\0\0\0\0\0\0widestuff\n") $stop; s = ""; chars = $fgets(s, file); if (`verbose) $write("c=%0d w=%s", chars, s); // Output includes newline if (chars != 7) $stop; if (s != "string\n") $stop; // $sscanf if ($sscanf("x","")!=0) $stop; if ($sscanf("z","z")!=0) $stop; chars = $sscanf("blabcdefghijklmnop", "%s", letterq); if (`verbose) $write("c=%0d sa=%s\n", chars, letterq); if (chars != 1) $stop; if (letterq != "ijklmnop") $stop; chars = $sscanf("xa=1f ign=22 xb=12898971238912389712783490823_abcdef689_02348923", "xa=%x ign=%*d xb=%x", letterq, letterw); if (`verbose) $write("c=%0d xa=%x xb=%x\n", chars, letterq, letterw); if (chars != 2) $stop; if (letterq != 64'h1f) $stop; if (letterw != 128'h389712783490823_abcdef689_02348923) $stop; chars = $sscanf("ba=10 bb=110100101010010101012 note_the_two ", "ba=%b bb=%b%s", letterq, letterw, letterz); if (`verbose) $write("c=%0d xa=%x xb=%x z=%0s\n", chars, letterq, letterw, letterz); if (chars != 3) $stop; if (letterq != 64'h2) $stop; if (letterw != 128'hd2a55) $stop; if (letterz != {"\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0","2"}) $stop; chars = $sscanf("oa=23 oi=11 ob=125634123615234123681236", "oa=%o oi=%*o ob=%o", letterq, letterw); if (`verbose) $write("c=%0d oa=%x ob=%x\n", chars, letterq, letterw); if (chars != 2) $stop; if (letterq != 64'h13) $stop; if (letterw != 128'h55ce14f1a9c29e) $stop; chars = $sscanf("r=0.1 d=-236123", "r=%g d=%d", r, letterq); if (`verbose) $write("c=%0d d=%d\n", chars, letterq); if (chars != 2) $stop; `checkr(r, 0.1); if (letterq != 64'hfffffffffffc65a5) $stop; chars = $sscanf("scan from string", "scan %s string", s); if (`verbose) $write("c=%0d s=%s\n", chars, s); if (chars != 1) $stop; if (s != "from") $stop; // Cover quad and %e/%f chars = $sscanf("r=0.2", "r=%e", r); if (`verbose) $write("c=%0d r=%e\n", chars, r); `checkr(r, 0.2); chars = $sscanf("r=0.3", "r=%f", r); if (`verbose) $write("c=%0d r=%f\n", chars, r); `checkr(r, 0.3); s = "r=0.2 d=-236124"; chars = $sscanf(s, "r=%g d=%d", r, letterq); if (`verbose) $write("c=%0d d=%d\n", chars, letterq); if (chars != 2) $stop; `checkr(r, 0.2); if (letterq != 64'hfffffffffffc65a4) $stop; // $fscanf if ($fscanf(file,"")!=0) $stop; if (!sync("*")) $stop; chars = $fscanf(file, "xa=%x xb=%x", letterq, letterw); if (`verbose) $write("c=%0d xa=%0x xb=%0x\n", chars, letterq, letterw); if (chars != 2) $stop; if (letterq != 64'h1f) $stop; if (letterw != 128'h23790468902348923) $stop; if (!sync("\n")) $stop; if (!sync("*")) $stop; chars = $fscanf(file, "ba=%b bb=%b %s", letterq, letterw, letterz); if (`verbose) $write("c=%0d ba=%0x bb=%0x z=%0s\n", chars, letterq, letterw, letterz); if (chars != 3) $stop; if (letterq != 64'h2) $stop; if (letterw != 128'hd2a55) $stop; if (letterz != "\0\0\0\0note_the_two") $stop; if (!sync("\n")) $stop; if (!sync("*")) $stop; chars = $fscanf(file, "oa=%o ob=%o", letterq, letterw); if (`verbose) $write("c=%0d oa=%0x ob=%0x\n", chars, letterq, letterw); if (chars != 2) $stop; if (letterq != 64'h13) $stop; if (letterw != 128'h1573) $stop; if (!sync("\n")) $stop; if (!sync("*")) $stop; chars = $fscanf(file, "d=%d", letterq); if (`verbose) $write("c=%0d d=%0x\n", chars, letterq); if (chars != 1) $stop; if (letterq != 64'hfffffffffffc65a5) $stop; if (!sync("\n")) $stop; if (!sync("*")) $stop; chars = $fscanf(file, "u=%d", letterqs); if (`verbose) $write("c=%0d u=%0x\n", chars, letterqs); if (chars != 1) $stop; if (letterqs != -236124) $stop; if (!sync("\n")) $stop; if (!sync("*")) $stop; chars = $fscanf(file, "%c%s", letterl, letterw); if (`verbose) $write("c=%0d q=%c s=%s\n", chars, letterl, letterw); if (chars != 2) $stop; if (letterl != "f") $stop; if (letterw != "\0\0\0\0\0redfishblah") $stop; chars = $fscanf(file, "%c", letterl); if (`verbose) $write("c=%0d l=%x\n", chars, letterl); if (chars != 1) $stop; if (letterl != "\n") $stop; chars = $fscanf(file, "%c%s not_included\n", letterl, s); if (`verbose) $write("c=%0d l=%s\n", chars, s); if (chars != 2) $stop; if (s != "BCD") $stop; // msg1229 v_a = $fgetc(file); v_b = $fgetc(file); v_c = $fgetc(file); v_d = $fgetc(file); v_worda = { v_d, v_c, v_b, v_a }; if (v_worda != "4321") $stop; v_wordb[7:0] = $fgetc(file); v_wordb[15:8] = $fgetc(file); v_wordb[23:16] = $fgetc(file); v_wordb[31:24] = $fgetc(file); if (v_wordb != "9876") $stop; if ($fgetc(file) != "\n") $stop; v_length = $ftell(file); $frewind(file); v_off = $ftell(file); if (v_off != 0) $stop; $fseek(file, 10, 0); v_off = $ftell(file); if (v_off != 10) $stop; $fseek(file, 1, 1); v_off = $ftell(file); if (v_off != 11) $stop; $fseek(file, -1, 1); v_off = $ftell(file); if (v_off != 10) $stop; $fseek(file, v_length, 0); v_off = $ftell(file); if (v_off != v_length) $stop; if ($fseek(file, 0, 2) != 0) $stop; v_off = $ftell(file); if (v_off < v_length) $stop; if ($rewind(file) != 0) $stop; v_off = $ftell(file); if (v_off != 0) $stop; $fclose(file); end begin $sscanf("-1", "%d", scan17); if (scan17 !== wire17) $stop; end $write("*-* All Finished *-*\n"); $finish(0); // Test arguments to finish end function sync; input [7:0] cexp; reg [7:0] cgot; begin cgot = $fgetc(file); if (`verbose) $write("sync=%x='%c'\n", cgot,cgot); sync = (cgot == cexp); end endfunction endmodule verilator-5.042/test_regress/t/t_math_wallace_mul.v0000644000542200017500000010073115101701376023100 0ustar mahmoudyfreeshell// -*- Verilog -*- // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t_math_wallace_mul ( /*AUTOARG*/ // Outputs product_d3, // Inputs clk, enable, negate, datA, datB ); input clk; input enable; input negate; input [31:0] datA; input [31:0] datB; output reg [64:0] product_d3; wire [129:0] l1ppin00; wire [129:0] l1ppin01; wire [129:0] l1ppin02; wire [129:0] l1ppin03; wire [129:0] l1ppin04; wire [129:0] l1ppin05; wire [129:0] l1ppin06; wire [129:0] l1ppin07; wire [129:0] l1ppin08; wire [129:0] l1ppin09; wire [129:0] l1ppin10; wire [129:0] l1ppin11; wire [129:0] l1ppin12; wire [129:0] l1ppin13; wire [129:0] l1ppin14; wire [129:0] l1ppin15; wire [129:0] l1ppin16; wire [129:0] l1ppin17; wire [129:0] l1ppin18; wire [129:0] l1ppin19; wire [129:0] l1ppin20; wire [129:0] l1ppin21; wire [129:0] l1ppin22; wire [129:0] l1ppin23; wire [129:0] l1ppin24; wire [129:0] l1ppin25; wire [129:0] l1ppin26; wire [129:0] l1ppin27; wire [129:0] l1ppin28; wire [129:0] l1ppin29; wire [129:0] l1ppin30; wire [129:0] l1ppin31; wire [129:0] l1ppin32; wire [129:0] l1ppin33; wire [63:0] l1sumg0; wire [63:0] l1sumg1; wire [63:0] l1sumg2; wire [63:0] l1sumg3; wire [63:0] l1carryg0; wire [63:0] l1carryg1; wire [63:0] l1carryg2; wire [63:0] l1carryg3; wire [63:0] l2sumg0; wire [63:0] l2carryg0; wire [64:0] l1cin0g0; wire [64:0] l1cin0g1; wire [64:0] l1cin0g2; wire [64:0] l1cin0g3; wire [64:0] l1cin1g0; wire [64:0] l1cin1g1; wire [64:0] l1cin1g2; wire [64:0] l1cin1g3; wire [64:0] l1cin2g0; wire [64:0] l1cin2g1; wire [64:0] l1cin2g2; wire [64:0] l1cin2g3; wire [64:0] l1cin3g0; wire [64:0] l1cin3g1; wire [64:0] l1cin3g2; wire [64:0] l1cin4g0; wire [64:0] l1cin4g1; wire [64:0] l1cin4g2; wire [64:0] l1cin5g0; wire [64:0] l1cin5g1; wire [64:0] l1cin5g2; wire [64:0] l2cin0g0; wire [64:0] l2cin1g0; wire [64:0] l2cin2g0; wire [64:0] l2cin3g0; wire [64:0] l2cin4g0; wire [64:0] l2cin5g0; reg enable_d1; reg enable_d2; reg enable_d3; reg negate_d1; reg [31:0] datA_d1; reg [31:0] datB_d1; always @(posedge clk) begin // Initial input gater enable_d1 <= enable; if (enable) begin negate_d1 <= negate; datA_d1 <= datA; datB_d1 <= datB; end end function [4:0] booth; input negatef; input [2:0] in; case (({3{negatef}} ^ in)) 3'b000: booth = 5'b0_0001; // 0 3'b001: booth = 5'b0_0100; // +1x 3'b010: booth = 5'b0_0100; // +1x 3'b011: booth = 5'b1_0000; // +2x 3'b100: booth = 5'b0_1000; // -2x 3'b101: booth = 5'b0_0010; // -1x 3'b110: booth = 5'b0_0010; // -1x default: booth = 5'b0_0001; // 0 endcase endfunction wire [66:0] lcl_mier = {2'b0, 32'h0, datB_d1, 1'b0}; integer j; reg [4:0] ppsel[32:0]; always @* begin for (j = 0; j < 65; j = j + 2) begin ppsel[j/2] = booth(negate_d1, {lcl_mier[j+2], lcl_mier[j+1], lcl_mier[j]}); end end TmpPpg ppgen ( // Inputs .datA_d1(datA_d1), // Outputs .pp00(l1ppin00[129:0]), .pp01(l1ppin01[129:0]), .pp02(l1ppin02[129:0]), .pp03(l1ppin03[129:0]), .pp04(l1ppin04[129:0]), .pp05(l1ppin05[129:0]), .pp06(l1ppin06[129:0]), .pp07(l1ppin07[129:0]), .pp08(l1ppin08[129:0]), .pp09(l1ppin09[129:0]), .pp10(l1ppin10[129:0]), .pp11(l1ppin11[129:0]), .pp12(l1ppin12[129:0]), .pp13(l1ppin13[129:0]), .pp14(l1ppin14[129:0]), .pp15(l1ppin15[129:0]), .pp16(l1ppin16[129:0]), .pp17(l1ppin17[129:0]), .pp18(l1ppin18[129:0]), .pp19(l1ppin19[129:0]), .pp20(l1ppin20[129:0]), .pp21(l1ppin21[129:0]), .pp22(l1ppin22[129:0]), .pp23(l1ppin23[129:0]), .pp24(l1ppin24[129:0]), .pp25(l1ppin25[129:0]), .pp26(l1ppin26[129:0]), .pp27(l1ppin27[129:0]), .pp28(l1ppin28[129:0]), .pp29(l1ppin29[129:0]), .pp30(l1ppin30[129:0]), .pp31(l1ppin31[129:0]), .pp32(l1ppin32[129:0]), .pp33(l1ppin33[129:0]), // Inputs .pp00sel(ppsel[00][4:0]), .pp01sel(ppsel[01][4:0]), .pp02sel(ppsel[02][4:0]), .pp03sel(ppsel[03][4:0]), .pp04sel(ppsel[04][4:0]), .pp05sel(ppsel[05][4:0]), .pp06sel(ppsel[06][4:0]), .pp07sel(ppsel[07][4:0]), .pp08sel(ppsel[08][4:0]), .pp09sel(ppsel[09][4:0]), .pp10sel(ppsel[10][4:0]), .pp11sel(ppsel[11][4:0]), .pp12sel(ppsel[12][4:0]), .pp13sel(ppsel[13][4:0]), .pp14sel(ppsel[14][4:0]), .pp15sel(ppsel[15][4:0]), .pp16sel(ppsel[16][4:0]), .pp17sel(ppsel[17][4:0]), .pp18sel(ppsel[18][4:0]), .pp19sel(ppsel[19][4:0]), .pp20sel(ppsel[20][4:0]), .pp21sel(ppsel[21][4:0]), .pp22sel(ppsel[22][4:0]), .pp23sel(ppsel[23][4:0]), .pp24sel(ppsel[24][4:0]), .pp25sel(ppsel[25][4:0]), .pp26sel(ppsel[26][4:0]), .pp27sel(ppsel[27][4:0]), .pp28sel(ppsel[28][4:0]), .pp29sel(ppsel[29][4:0]), .pp30sel(ppsel[30][4:0]), .pp31sel(ppsel[31][4:0]), .pp32sel(ppsel[32][4:0]) ); assign l1cin0g0[0] = 1'b0; assign l1cin0g1[0] = 1'b0; assign l1cin0g2[0] = 1'b0; assign l1cin0g3[0] = 1'b0; assign l1cin1g0[0] = 1'b0; assign l1cin1g1[0] = 1'b0; assign l1cin1g2[0] = 1'b0; assign l1cin1g3[0] = 1'b0; assign l1cin2g0[0] = 1'b0; assign l1cin2g1[0] = 1'b0; assign l1cin2g2[0] = 1'b0; assign l1cin2g3[0] = 1'b0; assign l1cin3g0[0] = 1'b0; assign l1cin3g1[0] = 1'b0; assign l1cin3g2[0] = 1'b0; assign l1cin4g0[0] = 1'b0; assign l1cin4g1[0] = 1'b0; assign l1cin4g2[0] = 1'b0; assign l1cin5g0[0] = 1'b0; assign l1cin5g1[0] = 1'b0; assign l1cin5g2[0] = 1'b0; assign l2cin0g0[0] = 1'b0; assign l2cin1g0[0] = 1'b0; assign l2cin2g0[0] = 1'b0; assign l2cin3g0[0] = 1'b0; assign l2cin4g0[0] = 1'b0; assign l2cin5g0[0] = 1'b0; genvar i; generate for (i = 0; i < 64; i = i + 1) begin TmpCsa9to2 l1csag0 ( // Outputs .cout0(l1cin0g0[i+1]), .cout1(l1cin1g0[i+1]), .cout2(l1cin2g0[i+1]), .cout3(l1cin3g0[i+1]), .cout4(l1cin4g0[i+1]), .cout5(l1cin5g0[i+1]), .carry(l1carryg0[i]), .sum(l1sumg0[i]), // Inputs .in0(l1ppin00[i]), .in1(l1ppin01[i]), .in2(l1ppin02[i]), .in3(l1ppin03[i]), .in4(l1ppin04[i]), .in5(l1ppin05[i]), .in6(l1ppin06[i]), .in7(l1ppin07[i]), .in8(l1ppin08[i]), .cin0(l1cin0g0[i]), .cin1(l1cin1g0[i]), .cin2(l1cin2g0[i]), .cin3(l1cin3g0[i]), .cin4(l1cin4g0[i]), .cin5(l1cin5g0[i]) ); TmpCsa9to2 l1csag1 ( // Outputs .cout0(l1cin0g1[i+1]), .cout1(l1cin1g1[i+1]), .cout2(l1cin2g1[i+1]), .cout3(l1cin3g1[i+1]), .cout4(l1cin4g1[i+1]), .cout5(l1cin5g1[i+1]), .carry(l1carryg1[i]), .sum(l1sumg1[i]), // Inputs .in0(l1ppin09[i]), .in1(l1ppin10[i]), .in2(l1ppin11[i]), .in3(l1ppin12[i]), .in4(l1ppin13[i]), .in5(l1ppin14[i]), .in6(l1ppin15[i]), .in7(l1ppin16[i]), .in8(l1ppin17[i]), .cin0(l1cin0g1[i]), .cin1(l1cin1g1[i]), .cin2(l1cin2g1[i]), .cin3(l1cin3g1[i]), .cin4(l1cin4g1[i]), .cin5(l1cin5g1[i]) ); TmpCsa9to2 l1csag2 ( // Outputs .cout0(l1cin0g2[i+1]), .cout1(l1cin1g2[i+1]), .cout2(l1cin2g2[i+1]), .cout3(l1cin3g2[i+1]), .cout4(l1cin4g2[i+1]), .cout5(l1cin5g2[i+1]), .carry(l1carryg2[i]), .sum(l1sumg2[i]), // Inputs .in0(l1ppin18[i]), .in1(l1ppin19[i]), .in2(l1ppin20[i]), .in3(l1ppin21[i]), .in4(l1ppin22[i]), .in5(l1ppin23[i]), .in6(l1ppin24[i]), .in7(l1ppin25[i]), .in8(l1ppin26[i]), .cin0(l1cin0g2[i]), .cin1(l1cin1g2[i]), .cin2(l1cin2g2[i]), .cin3(l1cin3g2[i]), .cin4(l1cin4g2[i]), .cin5(l1cin5g2[i]) ); TmpCsa6to2 l1csag3 ( // Outputs .cout0(l1cin0g3[i+1]), .cout1(l1cin1g3[i+1]), .cout2(l1cin2g3[i+1]), .carry(l1carryg3[i]), .sum(l1sumg3[i]), // Inputs .in0(l1ppin27[i]), .in1(l1ppin28[i]), .in2(l1ppin29[i]), .in3(l1ppin30[i]), .in4(l1ppin31[i]), .in5(l1ppin32[i]), .cin0(l1cin0g3[i]), .cin1(l1cin1g3[i]), .cin2(l1cin2g3[i]) ); end endgenerate wire [63:0] l2ppin00 = l1sumg0[63:0]; wire [63:0] l2ppin01 = {l1carryg0[62:0], 1'b0}; wire [63:0] l2ppin02 = l1sumg1[63:0]; wire [63:0] l2ppin03 = {l1carryg1[62:0], 1'b0}; wire [63:0] l2ppin04 = l1sumg2[63:0]; wire [63:0] l2ppin05 = {l1carryg2[62:0], 1'b0}; wire [63:0] l2ppin06 = l1sumg3[63:0]; wire [63:0] l2ppin07 = {l1carryg3[62:0], 1'b0}; wire [63:0] l2ppin08 = l1ppin33[63:0]; generate for (i = 0; i < 64; i = i + 1) begin TmpCsa9to2 l2csag0 ( // Outputs .cout0(l2cin0g0[i+1]), .cout1(l2cin1g0[i+1]), .cout2(l2cin2g0[i+1]), .cout3(l2cin3g0[i+1]), .cout4(l2cin4g0[i+1]), .cout5(l2cin5g0[i+1]), .carry(l2carryg0[i]), .sum(l2sumg0[i]), // Inputs .in0(l2ppin00[i]), .in1(l2ppin01[i]), .in2(l2ppin02[i]), .in3(l2ppin03[i]), .in4(l2ppin04[i]), .in5(l2ppin05[i]), .in6(l2ppin06[i]), .in7(l2ppin07[i]), .in8(l2ppin08[i]), .cin0(l2cin0g0[i]), .cin1(l2cin1g0[i]), .cin2(l2cin2g0[i]), .cin3(l2cin3g0[i]), .cin4(l2cin4g0[i]), .cin5(l2cin5g0[i]) ); end endgenerate reg [63:0] l3ppin00_d2; reg [63:0] l3ppin01_d2; always @(posedge clk) begin enable_d2 <= enable_d1; if (enable_d1) begin l3ppin00_d2 <= l2sumg0[63:0]; l3ppin01_d2 <= {l2carryg0[62:0], 1'b0}; end end wire [63:0] l3carryg0_d2; wire [63:0] l3sumg0_d2; generate for (i = 0; i < 64; i = i + 1) begin TmpCsa3 l3csag0 ( // Outputs .out({l3carryg0_d2[i], l3sumg0_d2[i]}), // Inputs .in0(l3ppin00_d2[i]), .in1(l3ppin01_d2[i]), .in2(1'b0) ); end endgenerate wire [64:0] temp_lo_d2 = {l3sumg0_d2[63:0]} + {l3carryg0_d2[62:0], 1'b0}; always @(posedge clk) begin if (enable_d2) begin product_d3 <= temp_lo_d2; end end // lint_checking URDWIR OFF wire _unused_ok = |{1'b0, l1carryg0, l1carryg1, l1carryg2, l1carryg3, l1cin0g0, l1cin0g1, l1cin0g2, l1cin0g3, l1cin1g0, l1cin1g1, l1cin1g2, l1cin1g3, l1cin2g0, l1cin2g1, l1cin2g2, l1cin2g3, l1cin3g0, l1cin3g1, l1cin3g2, l1cin4g0, l1cin4g1, l1cin4g2, l1cin5g0, l1cin5g1, l1cin5g2, l1ppin00, l1ppin01, l1ppin02, l1ppin03, l1ppin04, l1ppin05, l1ppin06, l1ppin07, l1ppin08, l1ppin09, l1ppin10, l1ppin11, l1ppin12, l1ppin13, l1ppin14, l1ppin15, l1ppin16, l1ppin17, l1ppin18, l1ppin19, l1ppin20, l1ppin21, l1ppin22, l1ppin23, l1ppin24, l1ppin25, l1ppin26, l1ppin27, l1ppin28, l1ppin29, l1ppin30, l1ppin31, l1ppin32, l1ppin33, l1sumg0, l1sumg1, l1sumg2, l1sumg3, l2carryg0, l2cin0g0, l2cin1g0, l2cin2g0, l2cin3g0, l2cin4g0, l2cin5g0, l2sumg0, l3carryg0_d2[63], 1'b0}; // lint_checking URDWIR ON endmodule // lint_checking MULTMF OFF module TmpPpg ( /*AUTOARG*/ // Outputs pp00, pp01, pp02, pp03, pp04, pp05, pp06, pp07, pp08, pp09, pp10, pp11, pp12, pp13, pp14, pp15, pp16, pp17, pp18, pp19, pp20, pp21, pp22, pp23, pp24, pp25, pp26, pp27, pp28, pp29, pp30, pp31, pp32, pp33, // Inputs datA_d1, pp00sel, pp01sel, pp02sel, pp03sel, pp04sel, pp05sel, pp06sel, pp07sel, pp08sel, pp09sel, pp10sel, pp11sel, pp12sel, pp13sel, pp14sel, pp15sel, pp16sel, pp17sel, pp18sel, pp19sel, pp20sel, pp21sel, pp22sel, pp23sel, pp24sel, pp25sel, pp26sel, pp27sel, pp28sel, pp29sel, pp30sel, pp31sel, pp32sel ); input [31:0] datA_d1; input [4:0] pp00sel; input [4:0] pp01sel; input [4:0] pp02sel; input [4:0] pp03sel; input [4:0] pp04sel; input [4:0] pp05sel; input [4:0] pp06sel; input [4:0] pp07sel; input [4:0] pp08sel; input [4:0] pp09sel; input [4:0] pp10sel; input [4:0] pp11sel; input [4:0] pp12sel; input [4:0] pp13sel; input [4:0] pp14sel; input [4:0] pp15sel; input [4:0] pp16sel; input [4:0] pp17sel; input [4:0] pp18sel; input [4:0] pp19sel; input [4:0] pp20sel; input [4:0] pp21sel; input [4:0] pp22sel; input [4:0] pp23sel; input [4:0] pp24sel; input [4:0] pp25sel; input [4:0] pp26sel; input [4:0] pp27sel; input [4:0] pp28sel; input [4:0] pp29sel; input [4:0] pp30sel; input [4:0] pp31sel; input [4:0] pp32sel; output [129:0] pp00; output [129:0] pp01; output [129:0] pp02; output [129:0] pp03; output [129:0] pp04; output [129:0] pp05; output [129:0] pp06; output [129:0] pp07; output [129:0] pp08; output [129:0] pp09; output [129:0] pp10; output [129:0] pp11; output [129:0] pp12; output [129:0] pp13; output [129:0] pp14; output [129:0] pp15; output [129:0] pp16; output [129:0] pp17; output [129:0] pp18; output [129:0] pp19; output [129:0] pp20; output [129:0] pp21; output [129:0] pp22; output [129:0] pp23; output [129:0] pp24; output [129:0] pp25; output [129:0] pp26; output [129:0] pp27; output [129:0] pp28; output [129:0] pp29; output [129:0] pp30; output [129:0] pp31; output [129:0] pp32; output [129:0] pp33; function [65:0] boothmux; input [4:0] mxsel; input [65:0] mpcnd; case (mxsel) 5'b0_0001: boothmux = 66'h0; 5'b0_0010: boothmux = ~mpcnd; // -1x 5'b0_0100: boothmux = mpcnd; // +1x 5'b0_1000: boothmux = ~{mpcnd[64:0], 1'b0}; // -2x 5'b1_0000: boothmux = {mpcnd[64:0], 1'b0}; // +2x default: boothmux = 66'h0; // CANNOT_HIT endcase endfunction function rowcin; input [4:0] mxsel; case (mxsel) 5'b0_0001: rowcin = 1'b0; 5'b0_0010: rowcin = 1'b1; // -1x 5'b0_0100: rowcin = 1'b0; // +1x 5'b0_1000: rowcin = 1'b1; // -2x 5'b1_0000: rowcin = 1'b0; // +2x default: rowcin = 1'b0; // CANNOT_HIT endcase endfunction wire [65:0] lcl_mand = {2'b0, 32'h0, datA_d1}; wire [2*32+1:2*00] temp_pp00; wire [2*33+1:2*01] temp_pp01; wire [2*34+1:2*02] temp_pp02; wire [2*35+1:2*03] temp_pp03; wire [2*36+1:2*04] temp_pp04; wire [2*37+1:2*05] temp_pp05; wire [2*38+1:2*06] temp_pp06; wire [2*39+1:2*07] temp_pp07; wire [2*40+1:2*08] temp_pp08; wire [2*41+1:2*09] temp_pp09; wire [2*42+1:2*10] temp_pp10; wire [2*43+1:2*11] temp_pp11; wire [2*44+1:2*12] temp_pp12; wire [2*45+1:2*13] temp_pp13; wire [2*46+1:2*14] temp_pp14; wire [2*47+1:2*15] temp_pp15; wire [2*48+1:2*16] temp_pp16; wire [2*49+1:2*17] temp_pp17; wire [2*50+1:2*18] temp_pp18; wire [2*51+1:2*19] temp_pp19; wire [2*52+1:2*20] temp_pp20; wire [2*53+1:2*21] temp_pp21; wire [2*54+1:2*22] temp_pp22; wire [2*55+1:2*23] temp_pp23; wire [2*56+1:2*24] temp_pp24; wire [2*57+1:2*25] temp_pp25; wire [2*58+1:2*26] temp_pp26; wire [2*59+1:2*27] temp_pp27; wire [2*60+1:2*28] temp_pp28; wire [2*61+1:2*29] temp_pp29; wire [2*62+1:2*30] temp_pp30; wire [2*63+1:2*31] temp_pp31; wire [2*64+1:2*32] temp_pp32; assign temp_pp00 = boothmux(pp00sel, lcl_mand); assign temp_pp01 = boothmux(pp01sel, lcl_mand); assign temp_pp02 = boothmux(pp02sel, lcl_mand); assign temp_pp03 = boothmux(pp03sel, lcl_mand); assign temp_pp04 = boothmux(pp04sel, lcl_mand); assign temp_pp05 = boothmux(pp05sel, lcl_mand); assign temp_pp06 = boothmux(pp06sel, lcl_mand); assign temp_pp07 = boothmux(pp07sel, lcl_mand); assign temp_pp08 = boothmux(pp08sel, lcl_mand); assign temp_pp09 = boothmux(pp09sel, lcl_mand); assign temp_pp10 = boothmux(pp10sel, lcl_mand); assign temp_pp11 = boothmux(pp11sel, lcl_mand); assign temp_pp12 = boothmux(pp12sel, lcl_mand); assign temp_pp13 = boothmux(pp13sel, lcl_mand); assign temp_pp14 = boothmux(pp14sel, lcl_mand); assign temp_pp15 = boothmux(pp15sel, lcl_mand); assign temp_pp16 = boothmux(pp16sel, lcl_mand); assign temp_pp17 = boothmux(pp17sel, lcl_mand); assign temp_pp18 = boothmux(pp18sel, lcl_mand); assign temp_pp19 = boothmux(pp19sel, lcl_mand); assign temp_pp20 = boothmux(pp20sel, lcl_mand); assign temp_pp21 = boothmux(pp21sel, lcl_mand); assign temp_pp22 = boothmux(pp22sel, lcl_mand); assign temp_pp23 = boothmux(pp23sel, lcl_mand); assign temp_pp24 = boothmux(pp24sel, lcl_mand); assign temp_pp25 = boothmux(pp25sel, lcl_mand); assign temp_pp26 = boothmux(pp26sel, lcl_mand); assign temp_pp27 = boothmux(pp27sel, lcl_mand); assign temp_pp28 = boothmux(pp28sel, lcl_mand); assign temp_pp29 = boothmux(pp29sel, lcl_mand); assign temp_pp30 = boothmux(pp30sel, lcl_mand); assign temp_pp31 = boothmux(pp31sel, lcl_mand); assign temp_pp32 = boothmux(pp32sel, lcl_mand); assign pp00[2*32+1+3:2*00] = { ~temp_pp00[2*32+1], temp_pp00[2*32+1], temp_pp00[2*32+1], temp_pp00[2*32+1:2*00] }; assign pp01[2*33+1+2:2*01] = {1'b1, ~temp_pp01[2*33+1], temp_pp01[2*33+1:2*01]}; assign pp02[2*34+1+2:2*02] = {1'b1, ~temp_pp02[2*34+1], temp_pp02[2*34+1:2*02]}; assign pp03[2*35+1+2:2*03] = {1'b1, ~temp_pp03[2*35+1], temp_pp03[2*35+1:2*03]}; assign pp04[2*36+1+2:2*04] = {1'b1, ~temp_pp04[2*36+1], temp_pp04[2*36+1:2*04]}; assign pp05[2*37+1+2:2*05] = {1'b1, ~temp_pp05[2*37+1], temp_pp05[2*37+1:2*05]}; assign pp06[2*38+1+2:2*06] = {1'b1, ~temp_pp06[2*38+1], temp_pp06[2*38+1:2*06]}; assign pp07[2*39+1+2:2*07] = {1'b1, ~temp_pp07[2*39+1], temp_pp07[2*39+1:2*07]}; assign pp08[2*40+1+2:2*08] = {1'b1, ~temp_pp08[2*40+1], temp_pp08[2*40+1:2*08]}; assign pp09[2*41+1+2:2*09] = {1'b1, ~temp_pp09[2*41+1], temp_pp09[2*41+1:2*09]}; assign pp10[2*42+1+2:2*10] = {1'b1, ~temp_pp10[2*42+1], temp_pp10[2*42+1:2*10]}; assign pp11[2*43+1+2:2*11] = {1'b1, ~temp_pp11[2*43+1], temp_pp11[2*43+1:2*11]}; assign pp12[2*44+1+2:2*12] = {1'b1, ~temp_pp12[2*44+1], temp_pp12[2*44+1:2*12]}; assign pp13[2*45+1+2:2*13] = {1'b1, ~temp_pp13[2*45+1], temp_pp13[2*45+1:2*13]}; assign pp14[2*46+1+2:2*14] = {1'b1, ~temp_pp14[2*46+1], temp_pp14[2*46+1:2*14]}; assign pp15[2*47+1+2:2*15] = {1'b1, ~temp_pp15[2*47+1], temp_pp15[2*47+1:2*15]}; assign pp16[2*48+1+2:2*16] = {1'b1, ~temp_pp16[2*48+1], temp_pp16[2*48+1:2*16]}; assign pp17[2*49+1+2:2*17] = {1'b1, ~temp_pp17[2*49+1], temp_pp17[2*49+1:2*17]}; assign pp18[2*50+1+2:2*18] = {1'b1, ~temp_pp18[2*50+1], temp_pp18[2*50+1:2*18]}; assign pp19[2*51+1+2:2*19] = {1'b1, ~temp_pp19[2*51+1], temp_pp19[2*51+1:2*19]}; assign pp20[2*52+1+2:2*20] = {1'b1, ~temp_pp20[2*52+1], temp_pp20[2*52+1:2*20]}; assign pp21[2*53+1+2:2*21] = {1'b1, ~temp_pp21[2*53+1], temp_pp21[2*53+1:2*21]}; assign pp22[2*54+1+2:2*22] = {1'b1, ~temp_pp22[2*54+1], temp_pp22[2*54+1:2*22]}; assign pp23[2*55+1+2:2*23] = {1'b1, ~temp_pp23[2*55+1], temp_pp23[2*55+1:2*23]}; assign pp24[2*56+1+2:2*24] = {1'b1, ~temp_pp24[2*56+1], temp_pp24[2*56+1:2*24]}; assign pp25[2*57+1+2:2*25] = {1'b1, ~temp_pp25[2*57+1], temp_pp25[2*57+1:2*25]}; assign pp26[2*58+1+2:2*26] = {1'b1, ~temp_pp26[2*58+1], temp_pp26[2*58+1:2*26]}; assign pp27[2*59+1+2:2*27] = {1'b1, ~temp_pp27[2*59+1], temp_pp27[2*59+1:2*27]}; assign pp28[2*60+1+2:2*28] = {1'b1, ~temp_pp28[2*60+1], temp_pp28[2*60+1:2*28]}; assign pp29[2*61+1+2:2*29] = {1'b1, ~temp_pp29[2*61+1], temp_pp29[2*61+1:2*29]}; assign pp30[2*62+1+2:2*30] = {1'b1, ~temp_pp30[2*62+1], temp_pp30[2*62+1:2*30]}; assign pp31[2*63+1+2:2*31] = {1'b1, ~temp_pp31[2*63+1], temp_pp31[2*63+1:2*31]}; assign pp32[2*63+1+2:2*32] = temp_pp32[2*64+1:2*32]; assign pp33[2*63+1+2:2*33] = 64'b0; assign pp00[2*64+1:2*32+1+4] = {((2 * 64 + 1) - (2 * 32 + 1 + 4) + 1) {1'b0}}; assign pp01[2*64+1:2*33+1+3] = {((2 * 64 + 1) - (2 * 33 + 1 + 3) + 1) {1'b0}}; assign pp02[2*64+1:2*34+1+3] = {((2 * 64 + 1) - (2 * 34 + 1 + 3) + 1) {1'b0}}; assign pp03[2*64+1:2*35+1+3] = {((2 * 64 + 1) - (2 * 35 + 1 + 3) + 1) {1'b0}}; assign pp04[2*64+1:2*36+1+3] = {((2 * 64 + 1) - (2 * 36 + 1 + 3) + 1) {1'b0}}; assign pp05[2*64+1:2*37+1+3] = {((2 * 64 + 1) - (2 * 37 + 1 + 3) + 1) {1'b0}}; assign pp06[2*64+1:2*38+1+3] = {((2 * 64 + 1) - (2 * 38 + 1 + 3) + 1) {1'b0}}; assign pp07[2*64+1:2*39+1+3] = {((2 * 64 + 1) - (2 * 39 + 1 + 3) + 1) {1'b0}}; assign pp08[2*64+1:2*40+1+3] = {((2 * 64 + 1) - (2 * 40 + 1 + 3) + 1) {1'b0}}; assign pp09[2*64+1:2*41+1+3] = {((2 * 64 + 1) - (2 * 41 + 1 + 3) + 1) {1'b0}}; assign pp10[2*64+1:2*42+1+3] = {((2 * 64 + 1) - (2 * 42 + 1 + 3) + 1) {1'b0}}; assign pp11[2*64+1:2*43+1+3] = {((2 * 64 + 1) - (2 * 43 + 1 + 3) + 1) {1'b0}}; assign pp12[2*64+1:2*44+1+3] = {((2 * 64 + 1) - (2 * 44 + 1 + 3) + 1) {1'b0}}; assign pp13[2*64+1:2*45+1+3] = {((2 * 64 + 1) - (2 * 45 + 1 + 3) + 1) {1'b0}}; assign pp14[2*64+1:2*46+1+3] = {((2 * 64 + 1) - (2 * 46 + 1 + 3) + 1) {1'b0}}; assign pp15[2*64+1:2*47+1+3] = {((2 * 64 + 1) - (2 * 47 + 1 + 3) + 1) {1'b0}}; assign pp16[2*64+1:2*48+1+3] = {((2 * 64 + 1) - (2 * 48 + 1 + 3) + 1) {1'b0}}; assign pp17[2*64+1:2*49+1+3] = {((2 * 64 + 1) - (2 * 49 + 1 + 3) + 1) {1'b0}}; assign pp18[2*64+1:2*50+1+3] = {((2 * 64 + 1) - (2 * 50 + 1 + 3) + 1) {1'b0}}; assign pp19[2*64+1:2*51+1+3] = {((2 * 64 + 1) - (2 * 51 + 1 + 3) + 1) {1'b0}}; assign pp20[2*64+1:2*52+1+3] = {((2 * 64 + 1) - (2 * 52 + 1 + 3) + 1) {1'b0}}; assign pp21[2*64+1:2*53+1+3] = {((2 * 64 + 1) - (2 * 53 + 1 + 3) + 1) {1'b0}}; assign pp22[2*64+1:2*54+1+3] = {((2 * 64 + 1) - (2 * 54 + 1 + 3) + 1) {1'b0}}; assign pp23[2*64+1:2*55+1+3] = {((2 * 64 + 1) - (2 * 55 + 1 + 3) + 1) {1'b0}}; assign pp24[2*64+1:2*56+1+3] = {((2 * 64 + 1) - (2 * 56 + 1 + 3) + 1) {1'b0}}; assign pp25[2*64+1:2*57+1+3] = {((2 * 64 + 1) - (2 * 57 + 1 + 3) + 1) {1'b0}}; assign pp26[2*64+1:2*58+1+3] = {((2 * 64 + 1) - (2 * 58 + 1 + 3) + 1) {1'b0}}; assign pp27[2*64+1:2*59+1+3] = {((2 * 64 + 1) - (2 * 59 + 1 + 3) + 1) {1'b0}}; assign pp28[2*64+1:2*60+1+3] = {((2 * 64 + 1) - (2 * 60 + 1 + 3) + 1) {1'b0}}; assign pp29[2*64+1:2*61+1+3] = {((2 * 64 + 1) - (2 * 61 + 1 + 3) + 1) {1'b0}}; assign pp30[2*64+1:2*62+1+3] = {((2 * 64 + 1) - (2 * 62 + 1 + 3) + 1) {1'b0}}; assign pp01[2*00+1:2*00] = {1'b0, rowcin(pp00sel)}; assign pp02[2*01+1:2*01] = {1'b0, rowcin(pp01sel)}; assign pp03[2*02+1:2*02] = {1'b0, rowcin(pp02sel)}; assign pp04[2*03+1:2*03] = {1'b0, rowcin(pp03sel)}; assign pp05[2*04+1:2*04] = {1'b0, rowcin(pp04sel)}; assign pp06[2*05+1:2*05] = {1'b0, rowcin(pp05sel)}; assign pp07[2*06+1:2*06] = {1'b0, rowcin(pp06sel)}; assign pp08[2*07+1:2*07] = {1'b0, rowcin(pp07sel)}; assign pp09[2*08+1:2*08] = {1'b0, rowcin(pp08sel)}; assign pp10[2*09+1:2*09] = {1'b0, rowcin(pp09sel)}; assign pp11[2*10+1:2*10] = {1'b0, rowcin(pp10sel)}; assign pp12[2*11+1:2*11] = {1'b0, rowcin(pp11sel)}; assign pp13[2*12+1:2*12] = {1'b0, rowcin(pp12sel)}; assign pp14[2*13+1:2*13] = {1'b0, rowcin(pp13sel)}; assign pp15[2*14+1:2*14] = {1'b0, rowcin(pp14sel)}; assign pp16[2*15+1:2*15] = {1'b0, rowcin(pp15sel)}; assign pp17[2*16+1:2*16] = {1'b0, rowcin(pp16sel)}; assign pp18[2*17+1:2*17] = {1'b0, rowcin(pp17sel)}; assign pp19[2*18+1:2*18] = {1'b0, rowcin(pp18sel)}; assign pp20[2*19+1:2*19] = {1'b0, rowcin(pp19sel)}; assign pp21[2*20+1:2*20] = {1'b0, rowcin(pp20sel)}; assign pp22[2*21+1:2*21] = {1'b0, rowcin(pp21sel)}; assign pp23[2*22+1:2*22] = {1'b0, rowcin(pp22sel)}; assign pp24[2*23+1:2*23] = {1'b0, rowcin(pp23sel)}; assign pp25[2*24+1:2*24] = {1'b0, rowcin(pp24sel)}; assign pp26[2*25+1:2*25] = {1'b0, rowcin(pp25sel)}; assign pp27[2*26+1:2*26] = {1'b0, rowcin(pp26sel)}; assign pp28[2*27+1:2*27] = {1'b0, rowcin(pp27sel)}; assign pp29[2*28+1:2*28] = {1'b0, rowcin(pp28sel)}; assign pp30[2*29+1:2*29] = {1'b0, rowcin(pp29sel)}; assign pp31[2*30+1:2*30] = {1'b0, rowcin(pp30sel)}; assign pp32[2*31+1:2*31] = {1'b0, rowcin(pp31sel)}; assign pp33[2*32+1:2*32] = {1'b0, rowcin(pp32sel)}; assign pp02[2*01-1:0] = {(2 * 01 - 1 - 0 + 1) {1'b0}}; assign pp03[2*02-1:0] = {(2 * 02 - 1 - 0 + 1) {1'b0}}; assign pp04[2*03-1:0] = {(2 * 03 - 1 - 0 + 1) {1'b0}}; assign pp05[2*04-1:0] = {(2 * 04 - 1 - 0 + 1) {1'b0}}; assign pp06[2*05-1:0] = {(2 * 05 - 1 - 0 + 1) {1'b0}}; assign pp07[2*06-1:0] = {(2 * 06 - 1 - 0 + 1) {1'b0}}; assign pp08[2*07-1:0] = {(2 * 07 - 1 - 0 + 1) {1'b0}}; assign pp09[2*08-1:0] = {(2 * 08 - 1 - 0 + 1) {1'b0}}; assign pp10[2*09-1:0] = {(2 * 09 - 1 - 0 + 1) {1'b0}}; assign pp11[2*10-1:0] = {(2 * 10 - 1 - 0 + 1) {1'b0}}; assign pp12[2*11-1:0] = {(2 * 11 - 1 - 0 + 1) {1'b0}}; assign pp13[2*12-1:0] = {(2 * 12 - 1 - 0 + 1) {1'b0}}; assign pp14[2*13-1:0] = {(2 * 13 - 1 - 0 + 1) {1'b0}}; assign pp15[2*14-1:0] = {(2 * 14 - 1 - 0 + 1) {1'b0}}; assign pp16[2*15-1:0] = {(2 * 15 - 1 - 0 + 1) {1'b0}}; assign pp17[2*16-1:0] = {(2 * 16 - 1 - 0 + 1) {1'b0}}; assign pp18[2*17-1:0] = {(2 * 17 - 1 - 0 + 1) {1'b0}}; assign pp19[2*18-1:0] = {(2 * 18 - 1 - 0 + 1) {1'b0}}; assign pp20[2*19-1:0] = {(2 * 19 - 1 - 0 + 1) {1'b0}}; assign pp21[2*20-1:0] = {(2 * 20 - 1 - 0 + 1) {1'b0}}; assign pp22[2*21-1:0] = {(2 * 21 - 1 - 0 + 1) {1'b0}}; assign pp23[2*22-1:0] = {(2 * 22 - 1 - 0 + 1) {1'b0}}; assign pp24[2*23-1:0] = {(2 * 23 - 1 - 0 + 1) {1'b0}}; assign pp25[2*24-1:0] = {(2 * 24 - 1 - 0 + 1) {1'b0}}; assign pp26[2*25-1:0] = {(2 * 25 - 1 - 0 + 1) {1'b0}}; assign pp27[2*26-1:0] = {(2 * 26 - 1 - 0 + 1) {1'b0}}; assign pp28[2*27-1:0] = {(2 * 27 - 1 - 0 + 1) {1'b0}}; assign pp29[2*28-1:0] = {(2 * 28 - 1 - 0 + 1) {1'b0}}; assign pp30[2*29-1:0] = {(2 * 29 - 1 - 0 + 1) {1'b0}}; assign pp31[2*30-1:0] = {(2 * 30 - 1 - 0 + 1) {1'b0}}; assign pp32[2*31-1:0] = {(2 * 31 - 1 - 0 + 1) {1'b0}}; assign pp33[2*32-1:0] = {(2 * 32 - 1 - 0 + 1) {1'b0}}; endmodule module TmpCsa9to2 ( /*AUTOARG*/ // Outputs cout0, cout1, cout2, cout3, cout4, cout5, carry, sum, // Inputs in0, in1, in2, in3, in4, in5, in6, in7, in8, cin0, cin1, cin2, cin3, cin4, cin5 ); input in0; input in1; input in2; input in3; input in4; input in5; input in6; input in7; input in8; input cin0; input cin1; input cin2; input cin3; input cin4; input cin5; output cout0; output cout1; output cout2; output cout3; output cout4; output cout5; output carry; output sum; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire sumi0; // From csa0 of TmpCsa3.v wire sumi1; // From csa1 of TmpCsa3.v wire sumi2; // From csa3 of TmpCsa3.v // End of automatics TmpCsa3 csa0 ( // Outputs .out({cout0, sumi0}), /*AUTOINST*/ // Inputs .in0 (in0), .in1 (in1), .in2 (in2)); TmpCsa3 csa1 ( // Outputs .out({cout1, sumi1}), // Inputs .in0(in3), .in1(in4), .in2(in5) /*AUTOINST*/); TmpCsa3 csa3 ( // Outputs .out({cout2, sumi2}), // Inputs .in0(in6), .in1(in7), .in2(in8) /*AUTOINST*/); TmpCsa6to2 csa4 ( // Inputs .in0(sumi0), .in1(sumi1), .in2(sumi2), .in3(cin0), .in4(cin1), .in5(cin2), .cin0(cin3), .cin1(cin4), .cin2(cin5), // Outputs .cout0(cout3), .cout1(cout4), .cout2(cout5), /*AUTOINST*/ // Outputs .carry (carry), .sum (sum)); endmodule module TmpCsa6to2 ( /*AUTOARG*/ // Outputs cout0, cout1, cout2, carry, sum, // Inputs in0, in1, in2, in3, in4, in5, cin0, cin1, cin2 ); input in0; input in1; input in2; input in3; input in4; input in5; input cin0; input cin1; input cin2; output cout0; output cout1; output cout2; output carry; output sum; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire sumi0; // From csa0 of TmpCsa3.v wire sumi1; // From csa1 of TmpCsa3.v // End of automatics TmpCsa3 csa0 (// Outputs .out({cout0, sumi0}), /*AUTOINST*/ // Inputs .in0 (in0), .in1 (in1), .in2 (in2)); TmpCsa3 csa1 (// Outputs .out({cout1, sumi1}), // Inputs .in0(in3), .in1(in4), .in2(in5) /*AUTOINST*/); TmpCsa4to2 csa3 (// Inputs .in0(sumi0), .in1(sumi1), .in2(cin0), .in3(cin1), .cin(cin2), // Outputs .cout(cout2), /*AUTOINST*/ // Outputs .carry (carry), .sum (sum)); endmodule module TmpCsa4to2 ( /*AUTOARG*/ // Outputs cout, carry, sum, // Inputs in0, in1, in2, in3, cin ); input in0; input in1; input in2; input in3; input cin; output cout; output carry; output wire sum; wire sumi; TmpCsa3 csa0 ( // Outputs .out({cout, sumi}), // Inputs .in0(in0), .in1(in1), .in2(in2) ); TmpCsa3 csa1 ( // Outputs .out({carry, sum}), // Inputs .in0(in3), .in1(sumi), .in2(cin) ); endmodule module TmpCsa3 ( /*AUTOARG*/ // Outputs out, // Inputs in0, in1, in2 ); input in0; input in1; input in2; output [1:0] out; assign out[0] = in0 ^ in1 ^ in2; assign out[1] = (in0 & in1) | (in1 & in2) | (in0 & in2); endmodule // Local Variables: // compile-command: "vlint --brief --nowarn=MULTMF,MODLNM t_math_wallace_mul.v" // End: verilator-5.042/test_regress/t/t_force_release_net.v0000644000542200017500000000651515101701376023253 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module t (/*AUTOARG*/ // Inputs clk ); input clk; int cyc = 0; always @(posedge clk) cyc <= cyc + 1; wire net_1; wire [7:0] net_8, alias_net_8; assign net_1 = ~cyc[0]; assign net_8 = ~cyc[1 +: 8]; alias net_8 = alias_net_8; always @ (posedge clk) begin $display("%d pre : %x %x", cyc, net_8, net_1); case (cyc) 4: begin `checkh (net_1, 0); `checkh (net_8, ~cyc[1 +: 8]); end 5: begin `checkh (net_1, 0); `checkh (net_8, 8'h5f); end 6: begin `checkh (net_1, 1); `checkh (net_8, 8'h5f); end 7, 8: begin `checkh (net_1, 1); `checkh (net_8, 8'hf5); end 9: begin `checkh (net_1, ~cyc[0]); `checkh (net_8, 8'hf5); end 11, 12: begin `checkh (net_1, 1); `checkh (net_8, 8'h5a); end 13, 14: begin `checkh (net_1, 0); `checkh (net_8, 8'ha5); end default: begin `checkh ({net_8, net_1}, ~cyc[0 +: 9]); end endcase `ifndef REVERSE if (cyc == 3) force net_1 = 0; if (cyc == 5) force net_1 = 1; if (cyc == 8) release net_1; if (cyc == 4) force net_8 = 8'h5f; if (cyc == 6) force net_8 = 8'hf5; if (cyc == 9) release net_8; if (cyc == 10) force {net_1, net_8} = 9'b1_0101_1010; if (cyc == 12) force {net_8, net_1} = 9'b1010_0101_0; if (cyc == 14) release {net_1, net_8}; `else if (cyc == 8) release net_1; if (cyc == 5) force net_1 = 1; if (cyc == 3) force net_1 = 0; if (cyc == 9) release net_8; if (cyc == 6) force net_8 = 8'hf5; if (cyc == 4) force net_8 = 8'h5f; if (cyc == 14) release {net_1, net_8}; if (cyc == 12) force {net_8, net_1} = 9'b1010_0101_0; if (cyc == 10) force {net_1, net_8} = 9'b1_0101_1010; `endif $display("%d post: %x %x", cyc, net_8, net_1); case (cyc) 3: begin `checkh (net_1, 0); `checkh (net_8, ~cyc[1 +: 8]); end 4: begin `checkh (net_1, 0); `checkh (net_8, 8'h5f); end 5: begin `checkh (net_1, 1); `checkh (net_8, 8'h5f); end 6, 7: begin `checkh (net_1, 1); `checkh (net_8, 8'hf5); end 8: begin `checkh (net_1, ~cyc[0]); `checkh (net_8, 8'hf5); end 10, 11: begin `checkh (net_1, 1); `checkh (net_8, 8'h5a); end 12, 13: begin `checkh (net_1, 0); `checkh (net_8, 8'ha5); end default: begin `checkh ({net_8, net_1}, ~cyc[0 +: 9]); `checkh ({alias_net_8, net_1}, ~cyc[0 +: 9]); end endcase if (cyc == 30) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_struct_clk.py0000755000542200017500000000073415101701376022147 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_timing_osc.out0000644000542200017500000000214715101701376022301 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1fs $end $scope module tb_osc $end $var wire 1 # dco_out $end $scope module dco $end $var real 64 ' coarse_cw $end $var real 64 ' medium_cw $end $var real 64 ) fine_cw $end $var wire 1 # rf_out $end $var real 64 + coarse_ofst $end $var real 64 - coarse_res $end $var real 64 / medium_ofst $end $var real 64 1 medium_res $end $var real 64 3 fine_ofst $end $var real 64 5 fine_res $end $var real 64 7 coarse_delay $end $var real 64 9 medium_delay $end $var real 64 ; fine_delay $end $var real 64 = jitter $end $var wire 1 $ coarse_out $end $var wire 1 % medium_out $end $var wire 1 & fine_out $end $upscope $end $upscope $end $enddefinitions $end #0 0# 0$ 0% 0& r8 ' r32 ) r6e-10 + r6e-11 - r1.3e-10 / r6e-12 1 r7e-11 3 r2e-13 5 r5.4e-10 7 r8.9e-11 9 r3.82e-11 ; r0 = #38200 1& #88200 1# #89000 1% #127200 0& #177200 0# #578200 1$ #667200 0% #705400 1& #755400 1# #1245400 0$ #1334400 1% #1372600 0& #1422600 0# #1912600 1$ #2001600 0% #2039800 1& #2089800 1# #2579800 0$ #2668800 1% #2707000 0& #2757000 0# #3000000 verilator-5.042/test_regress/t/t_sys_readmem_assoc_bad.py0000755000542200017500000000077615101701376024306 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_assoc_wildcard_bad.out0000644000542200017500000001052015101701376023727 0ustar mahmoudyfreeshell%Error: t/t_assoc_wildcard_bad.v:23:13: The 1 arguments passed to .num method does not match its requiring 0 arguments : ... note: In instance 't' 23 | v = a.num("badarg"); | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_assoc_wildcard_bad.v:24:13: The 1 arguments passed to .size method does not match its requiring 0 arguments : ... note: In instance 't' 24 | v = a.size("badarg"); | ^~~~ %Error: t/t_assoc_wildcard_bad.v:25:13: The 0 arguments passed to .exists method does not match its requiring 1 arguments : ... note: In instance 't' 25 | v = a.exists(); | ^~~~~~ %Error: t/t_assoc_wildcard_bad.v:26:13: The 2 arguments passed to .exists method does not match its requiring 1 arguments : ... note: In instance 't' 26 | v = a.exists(k, "bad2"); | ^~~~~~ %Error: t/t_assoc_wildcard_bad.v:27:9: The 2 arguments passed to .delete method does not match its requiring 0 to 1 arguments : ... note: In instance 't' 27 | a.delete(k, "bad2"); | ^~~~~~ %Error: t/t_assoc_wildcard_bad.v:29:9: Array method 'sort' not legal on associative arrays : ... note: In instance 't' 29 | a.sort; | ^~~~ %Error: t/t_assoc_wildcard_bad.v:30:9: Array method 'rsort' not legal on associative arrays : ... note: In instance 't' 30 | a.rsort; | ^~~~~ %Error: t/t_assoc_wildcard_bad.v:31:9: Array method 'reverse' not legal on associative arrays : ... note: In instance 't' 31 | a.reverse; | ^~~~~~~ %Error: t/t_assoc_wildcard_bad.v:32:9: Array method 'shuffle' not legal on associative arrays : ... note: In instance 't' 32 | a.shuffle; | ^~~~~~~ %Error: t/t_assoc_wildcard_bad.v:34:9: Array method 'first' not legal on wildcard associative arrays : ... note: In instance 't' 34 | a.first; | ^~~~~ %Error: t/t_assoc_wildcard_bad.v:35:9: Array method 'last' not legal on wildcard associative arrays : ... note: In instance 't' 35 | a.last; | ^~~~ %Error: t/t_assoc_wildcard_bad.v:36:9: Array method 'next' not legal on wildcard associative arrays : ... note: In instance 't' 36 | a.next; | ^~~~ %Error: t/t_assoc_wildcard_bad.v:37:9: Array method 'prev' not legal on wildcard associative arrays : ... note: In instance 't' 37 | a.prev; | ^~~~ %Error: t/t_assoc_wildcard_bad.v:38:9: Array method 'unique_index' not legal on wildcard associative arrays : ... note: In instance 't' 38 | a.unique_index; | ^~~~~~~~~~~~ %Error: t/t_assoc_wildcard_bad.v:39:9: Array method 'find_index' not legal on wildcard associative arrays : ... note: In instance 't' 39 | a.find_index; | ^~~~~~~~~~ %Error: t/t_assoc_wildcard_bad.v:40:9: Array method 'find_first_index' not legal on wildcard associative arrays : ... note: In instance 't' 40 | a.find_first_index; | ^~~~~~~~~~~~~~~~ %Error: t/t_assoc_wildcard_bad.v:41:9: Array method 'find_last_index' not legal on wildcard associative arrays : ... note: In instance 't' 41 | a.find_last_index; | ^~~~~~~~~~~~~~~ %Error: t/t_assoc_wildcard_bad.v:43:8: Wildcard index must be integral (IEEE 1800-2023 7.8.1) : ... note: In instance 't' 43 | a[x] = "bad"; | ^ %Error: t/t_assoc_wildcard_bad.v:45:9: Unknown wildcard associative array method 'bad_not_defined' : ... note: In instance 't' 45 | a.bad_not_defined(); | ^~~~~~~~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_interface_generic_bad.py0000755000542200017500000000102515101701376024226 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=['--timing'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_mod_recurse.v0000644000542200017500000000576515101701376022124 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Sean Moore. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [7:0] tripline = crc[7:0]; /*AUTOWIRE*/ wire valid; wire [3-1:0] value; PriorityChoice #(.OCODEWIDTH(3)) pe (.out(valid), .outN(value[2:0]), .tripline(tripline)); // Aggregate outputs into a single result vector wire [63:0] result = {60'h0, valid, value}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'hc5fc632f816568fb if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module PriorityChoice (out, outN, tripline); parameter OCODEWIDTH = 1; localparam CODEWIDTH=OCODEWIDTH-1; localparam SCODEWIDTH= (CODEWIDTH<1) ? 1 : CODEWIDTH; output reg out; output reg [OCODEWIDTH-1:0] outN; input wire [(1<final(); VL_DO_DANGLING(delete tb, tb); return 0; } int sc_main(int argc, char* argv[]) { tb = new VM_PREFIX{"tb"}; VL_PRINTF("*-* All Finished *-*\n"); tb->final(); VL_DO_DANGLING(delete tb, tb); return 0; } verilator-5.042/test_regress/t/t_order_multidriven.cpp0000644000542200017500000000243415101701376023655 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Ted Campbell. // SPDX-License-Identifier: CC0-1.0 #include "verilated.h" #include "verilated_vcd_c.h" #include VM_PREFIX_INCLUDE double sc_time_stamp() { return 0; } Vt_order_multidriven* vcore; VerilatedVcdC* vcd; uint64_t vtime; #define PHASE_90 static void half_cycle(int clk) { if (clk & 1) vcore->i_clk_wr = !vcore->i_clk_wr; if (clk & 2) vcore->i_clk_rd = !vcore->i_clk_rd; vtime += 10 / 2; vcore->eval(); vcore->eval(); vcd->dump(vtime); } static void cycle() { #ifdef PHASE_90 half_cycle(1); half_cycle(2); half_cycle(1); half_cycle(2); #else half_cycle(3); half_cycle(3); #endif } int main() { const std::unique_ptr contextp{new VerilatedContext}; contextp->traceEverOn(true); vcore = new VM_PREFIX{contextp.get()}; vcd = new VerilatedVcdC; vcore->trace(vcd, 99); vcd->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); vcore->i_clk_wr = 0; vcore->i_clk_rd = 0; for (int i = 0; i < 256; ++i) { // cycle(); } vcd->close(); vcore->final(); VL_DO_DANGLING(delete vcore, vcore); printf("*-* All Finished *-*\n"); } verilator-5.042/test_regress/t/t_dynarray_concat.v0000644000542200017500000000303115101701376022755 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `ifdef VERILATOR `define stop $stop `else `define stop `endif `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); module t; int da[][2] = '{}; int da2[][2] = '{'{1, 2}}; int dd[][] = '{}; int dd1[][] = '{'{1}}; int dd2[][] = '{'{1, 2}}; int dq[][$] = '{}; int dq1[][$] = '{'{1}}; int dq2[][$] = '{'{1, 2}}; int qa[$][2] = '{}; int qa2[$][2] = '{'{1, 2}}; int qd[$][] = '{}; int qd1[$][] = '{'{1}}; int qd2[$][] = '{'{1, 2}}; int qq[$][$] = '{}; int qq1[$][$] = '{'{1}}; int qq2[$][$] = '{'{1, 2}}; initial begin `checkp(da, "'{}"); `checkp(da2, "'{'{'h1, 'h2}}"); `checkp(dd, "'{}"); `checkp(dd1, "'{'{'h1}}"); `checkp(dd2, "'{'{'h1, 'h2}}"); `checkp(dq, "'{}"); `checkp(dq1, "'{'{'h1}}"); `checkp(dq2, "'{'{'h1, 'h2}}"); `checkp(qa, "'{}"); `checkp(qa2, "'{'{'h1, 'h2}}"); `checkp(qd, "'{}"); `checkp(qd1, "'{'{'h1}}"); `checkp(qd2, "'{'{'h1, 'h2}}"); `checkp(qq, "'{}"); `checkp(qq1, "'{'{'h1}}"); `checkp(qq2, "'{'{'h1, 'h2}}"); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_math_shiftrs.v0000644000542200017500000000276515101701376022305 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg signed [64+15:0] data; integer i; integer b; reg signed [64+15:0] srs; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==2) begin data <= 80'h0; data[75] <= 1'b1; data[10] <= 1'b1; end if (cyc==3) begin for (i=0; i<85; i=i+1) begin srs = data>>>i; //$write (" %x >>> %d == %x\n",data,i,srs); for (b=0; b<80; b=b+1) begin if (srs[b] != (b==(75-i) || b==(10-i))) $stop; end end end if (cyc==10) begin data <= 80'h0; data[79] <= 1'b1; data[10] <= 1'b1; end if (cyc==12) begin for (i=0; i<85; i=i+1) begin srs = data>>>i; //$write (" %x >>> %d == %x\n",data,i,srs); for (b=0; b<80; b=b+1) begin if (srs[b] != (b>=(79-i) || b==(10-i))) $stop; end end end if (cyc==20) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.042/test_regress/t/t_disable_task_unsup.out0000644000542200017500000000042615101701376024023 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_disable_task_unsup.v:20:13: Unsupported: disabling task by name 20 | #1 disable increment_x; | ^~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_tri_graph.py0000755000542200017500000000071415101701376021747 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.passes() verilator-5.042/test_regress/t/t_func_void_bad.v0000644000542200017500000000124315101701376022362 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls; function int fi(); return 10; endfunction static function int sfi(); return 10; endfunction endclass module t; function int f1; return 20; endfunction initial begin Cls c; // f1(); // Bad - ignored result // c = new; c.fi(); // Bad - ignored result c.sfi(); // Bad - ignored result // $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_let_recurse_bad.out0000644000542200017500000000046615101701376023272 0ustar mahmoudyfreeshell%Error: t/t_let_recurse_bad.v:9:36: Recursive let substitution 'RECURSE' 9 | let RECURSE(a) = (a == 1) ? 1 : RECURSE(a - 1); | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_class_builtin_bad.out0000644000542200017500000000124015101701376023600 0ustar mahmoudyfreeshell%Error: t/t_class_builtin_bad.v:8:17: The 'rand_mode' method is built-in and cannot be overridden (IEEE 1800-2023 18.8) : ... note: In instance 't' 8 | function int rand_mode(bit onoff); | ^~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_class_builtin_bad.v:11:17: The 'constraint_mode' method is built-in and cannot be overridden (IEEE 1800-2023 18.9) : ... note: In instance 't' 11 | function int constraint_mode(bit onoff); | ^~~~~~~~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_var_init.v0000644000542200017500000000133415101701376021414 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; parameter [31:0] P2=2, P3=3; integer i2=2, i3=3; reg [31:0] r2=2, r3=3; wire [31:0] w2=2, w3=3; always @ (posedge clk) begin if (P2 !== 2) $stop; if (P3 !== 3) $stop; if (i2 !== 2) $stop; if (i3 !== 3) $stop; if (r2 !== 2) $stop; if (r3 !== 3) $stop; if (w2 !== 2) $stop; if (w3 !== 3) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_udp_bad_first_input.py0000755000542200017500000000076615101701376024023 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface_parent_scope.v0000644000542200017500000000074015101701376024303 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Driss Hafdi. // SPDX-License-Identifier: CC0-1.0 interface Foo; logic quux; endinterface module Bar; // Issue# 1623 - seems legal always_comb foo.quux = '0; endmodule module Baz; Foo foo (); Bar bar (); endmodule module t; Baz baz (); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_assert_ctl_arg.v0000644000542200017500000001716215101701376022603 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 `define DISPLAY_PASS(file, line) \ $display("Passed '%m' at %s:%g", file, line) `define DISPLAY_FAIL(file, line) \ $display("Failed '%m' at %s:%g", file, line) `define RUN_ALL_ASSERTS \ $display("==========\nRunning all asserts at: %s:%g\n==========", `__FILE__, `__LINE__); \ run_all_asserts(`__FILE__, `__LINE__); \ cover_simple_immediate_`__LINE__: cover(1); \ cover_simple_immediate_stmt_`__LINE__: cover(1) `DISPLAY_PASS(`__FILE__, `__LINE__); \ cover_observed_deferred_immediate_`__LINE__: cover #0 (1); \ cover_observed_deferred_immediate_stmt_`__LINE__: cover #0 (1) `DISPLAY_PASS(`__FILE__, `__LINE__); \ cover_final_deferred_immediate_`__LINE__: cover final (1); \ cover_final_deferred_immediate_stmt_`__LINE__: cover final (1) `DISPLAY_PASS(`__FILE__, `__LINE__); \ module t (/*AUTOARG*/ clk ); input clk; let On = 3; let Off = 4; let Kill = 5; let CONCURRENT = 1; let SIMPLE_IMMEDIATE = 2; let OBSERVED_DEFERRED_IMMEDIATE = 4; let FINAL_DEFERRED_IMMEDIATE = 8; let ALL_TYPES = CONCURRENT|SIMPLE_IMMEDIATE|OBSERVED_DEFERRED_IMMEDIATE|FINAL_DEFERRED_IMMEDIATE; let ASSERT = 1; let COVER = 2; let ASSUME = 4; concurrent concurrent(.clk(clk)); initial begin // simple immediate $assertcontrol(Off, ALL_TYPES); $assertcontrol(On, SIMPLE_IMMEDIATE); `RUN_ALL_ASSERTS $assertcontrol(Off, SIMPLE_IMMEDIATE); `RUN_ALL_ASSERTS // observed deferred immediate $assertcontrol(Off, ALL_TYPES); $assertcontrol(On, OBSERVED_DEFERRED_IMMEDIATE); `RUN_ALL_ASSERTS $assertcontrol(Off, OBSERVED_DEFERRED_IMMEDIATE); `RUN_ALL_ASSERTS // final deferred immediate $assertcontrol(Off, ALL_TYPES); $assertcontrol(On, FINAL_DEFERRED_IMMEDIATE); `RUN_ALL_ASSERTS $assertcontrol(Off, FINAL_DEFERRED_IMMEDIATE); `RUN_ALL_ASSERTS // on, off, kill test $assertoff; `RUN_ALL_ASSERTS; $asserton; `RUN_ALL_ASSERTS; $assertkill; `RUN_ALL_ASSERTS; $assertcontrol(On, SIMPLE_IMMEDIATE|OBSERVED_DEFERRED_IMMEDIATE); `RUN_ALL_ASSERTS; $assertcontrol(On, FINAL_DEFERRED_IMMEDIATE); `RUN_ALL_ASSERTS; $assertcontrol(Off, OBSERVED_DEFERRED_IMMEDIATE|FINAL_DEFERRED_IMMEDIATE); `RUN_ALL_ASSERTS; $assertcontrol(Off, FINAL_DEFERRED_IMMEDIATE); `RUN_ALL_ASSERTS; $assertcontrol(Off, SIMPLE_IMMEDIATE); `RUN_ALL_ASSERTS; $assertcontrol(On, SIMPLE_IMMEDIATE); `RUN_ALL_ASSERTS; $assertcontrol(Off, ALL_TYPES); `RUN_ALL_ASSERTS; $assertcontrol(On, ALL_TYPES); `RUN_ALL_ASSERTS; $assertcontrol(Kill, ALL_TYPES); `RUN_ALL_ASSERTS; // directive_type test $assertoff; $assertcontrol(On, ALL_TYPES, ASSERT); `RUN_ALL_ASSERTS; $assertcontrol(Off, ALL_TYPES, ASSERT); $assertcontrol(On, ALL_TYPES, COVER); `RUN_ALL_ASSERTS; $assertcontrol(Off, ALL_TYPES, COVER); $assertcontrol(On, ALL_TYPES, ASSUME); `RUN_ALL_ASSERTS; $assertcontrol(Off, ALL_TYPES, ASSUME); $assertcontrol(On, ALL_TYPES, ASSERT|COVER); `RUN_ALL_ASSERTS; $assertcontrol(On, ALL_TYPES, ASSUME); `RUN_ALL_ASSERTS; $assertoff; `RUN_ALL_ASSERTS; $assertcontrol(On, SIMPLE_IMMEDIATE|FINAL_DEFERRED_IMMEDIATE, COVER|ASSUME); `RUN_ALL_ASSERTS; $assertoff; // concurrent test #10; $display("Disabling concurrent asserts, time: %g", $time); $assertcontrol(On, ALL_TYPES); $assertcontrol(Off, CONCURRENT); #10; $display("Enabling concurrent asserts, time: %g", $time); $assertcontrol(On, CONCURRENT); $write("*-* All Finished *-*\n"); $finish; end endmodule task run_all_asserts(string file, integer line); run_simple_immediate(file, line); run_observed_deferred_immediate(file, line); run_final_deferred_immediate(file, line); endtask task run_simple_immediate(string file, integer line); $display("Testing assert_simple_immediate at %s:%g", file, line); assert_simple_immediate: assert(0); assert_simple_immediate_else: assert(0) else `DISPLAY_FAIL(file, line); assert_simple_immediate_stmt: assert(0) `DISPLAY_PASS(file, line); assert_simple_immediate_stmt_else: assert(0) `DISPLAY_PASS(file, line); else `DISPLAY_FAIL(file, line); $display("Testing assume_simple_immediate at %s:%g", file, line); assume_simple_immediate: assume(0); assume_simple_immediate_else: assume(0) else `DISPLAY_FAIL(file, line); assume_simple_immediate_stmt: assume(0) `DISPLAY_PASS(file, line); assume_simple_immediate_stmt_else: assume(0) `DISPLAY_PASS(file, line); else `DISPLAY_FAIL(file, line); endtask task run_observed_deferred_immediate(string file, integer line); $display("Testing assert_observed_deferred_immediate at %s:%g", file, line); assert_observed_deferred_immediate: assert #0 (0); assert_observed_deferred_immediate_else: assert #0 (0) else `DISPLAY_FAIL(file, line); assert_observed_deferred_immediate_stmt: assert #0 (0) `DISPLAY_PASS(file, line); assert_observed_deferred_immediate_stmt_else: assert #0 (0) `DISPLAY_PASS(file, line); else `DISPLAY_FAIL(file, line); $display("Testing assume_observed_deferred_immediate at %s:%g", file, line); assume_observed_deferred_immediate: assume #0 (0); assume_observed_deferred_immediate_else: assume #0 (0) else `DISPLAY_FAIL(file, line); assume_observed_deferred_immediate_stmt: assume #0 (0) `DISPLAY_PASS(file, line); assume_observed_deferred_immediate_stmt_else: assume #0 (0) `DISPLAY_PASS(file, line); else `DISPLAY_FAIL(file, line); endtask task run_final_deferred_immediate(string file, integer line); $display("Testing assert_final_deferred_immediate at %s:%g", file, line); assert_final_deferred_immediate: assert final (0); assert_final_deferred_immediate_else: assert final (0) else `DISPLAY_FAIL(file, line); assert_final_deferred_immediate_stmt: assert final (0) `DISPLAY_PASS(file, line); assert_final_deferred_immediate_stmt_else: assert final (0) `DISPLAY_PASS(file, line); else `DISPLAY_FAIL(file, line); $display("Testing assume_final_deferred_immediate at %s:%g", file, line); assume_final_deferred_immediate: assume final (0); assume_final_deferred_immediate_else: assume final (0) else `DISPLAY_FAIL(file, line); assume_final_deferred_immediate_stmt: assume final (0) `DISPLAY_PASS(file, line); assume_final_deferred_immediate_stmt_else: assume final (0) `DISPLAY_PASS(file, line); else `DISPLAY_FAIL(file, line); endtask module concurrent(input clk); property prop(); @(posedge clk) 0 endproperty assert_concurrent: assert property (prop); assert_concurrent_else: assert property(prop) else `DISPLAY_FAIL(`__FILE__, `__LINE__); assert_concurrent_stmt: assert property(prop) `DISPLAY_PASS(`__FILE__, `__LINE__); assert_concurrent_stmt_else: assert property(prop) `DISPLAY_PASS(`__FILE__, `__LINE__); else `DISPLAY_FAIL(`__FILE__, `__LINE__); assume_concurrent: assume property(prop); assume_concurrent_else: assume property(prop) else `DISPLAY_FAIL(`__FILE__, `__LINE__); assume_concurrent_stmt: assume property(prop) `DISPLAY_PASS(`__FILE__, `__LINE__); assume_concurrent_stmt_else: assume property(prop) `DISPLAY_PASS(`__FILE__, `__LINE__); else `DISPLAY_FAIL(`__FILE__, `__LINE__); cover_concurrent: cover property(prop); cover_concurrent_stmt: cover property(prop) `DISPLAY_PASS(`__FILE__, `__LINE__); endmodule verilator-5.042/test_regress/t/t_lint_latch_bad_2.out0000644000542200017500000000077215101701376023320 0ustar mahmoudyfreeshell%Warning-LATCH: t/t_lint_latch_bad_2.v:12:4: Latch inferred for signal 'o' (not all control paths of combinational always assign a value) : ... Suggest use of always_latch for intentional latches 12 | always_comb | ^~~~~~~~~~~ ... For warning description see https://verilator.org/warn/LATCH?v=latest ... Use "/* verilator lint_off LATCH */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_dpi_vams.cpp0000644000542200017500000000254515101701376021725 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include VM_PREFIX_INCLUDE //====================================================================== // clang-format off #if defined(VERILATOR) # include "Vt_dpi_vams__Dpi.h" #elif defined(VCS) # include "../vc_hdrs.h" #elif defined(CADENCE) # define NEED_EXTERNS #else # error "Unknown simulator for DPI test" #endif // clang-format on #ifdef NEED_EXTERNS extern "C" { extern void dpii_call(double in, double* outp); } #endif void dpii_call(double in, double* outp) { *outp = in + 0.1; } //====================================================================== unsigned int main_time = 0; double sc_time_stamp() { return main_time; } VM_PREFIX* topp = nullptr; int main(int argc, char* argv[]) { Verilated::debug(0); Verilated::commandArgs(argc, argv); topp = new VM_PREFIX; topp->in = 1.1; topp->eval(); if (topp->out != 1.2) { VL_PRINTF("*-* All Finished *-*\n"); topp->final(); } else { vl_fatal(__FILE__, __LINE__, "top", "Unexpected results\n"); } topp->final(); VL_DO_DANGLING(delete topp, topp); return 0; } verilator-5.042/test_regress/t/t_infinite_recursion.py0000755000542200017500000000076215101701376023671 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.lint(verilator_flags2=["--no-unlimited-stack"]) test.passes() verilator-5.042/test_regress/t/t_inst_missing_bad.v0000644000542200017500000000076715101701376023126 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; wire ok = 1'b0; // verilator lint_off UNDRIVEN wire nc; // verilator lint_on UNDRIVEN sub sub (ok, , nc); endmodule module sub (input ok, input none, input nc, input missing); initial if (ok && none && nc && missing) begin end // No unused warning endmodule verilator-5.042/test_regress/t/t_wire_trireg_unsup.out0000644000542200017500000000222415101701376023716 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_wire_trireg_unsup.v:11:4: Unsupported: trireg 11 | trireg unsup; | ^~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_wire_trireg_unsup.v:12:4: Unsupported: trireg 12 | trireg (small) unsup_s; | ^~~~~~ %Error: t/t_wire_trireg_unsup.v:12:12: syntax error, unexpected STRENGTH keyword (strong1/etc) 12 | trireg (small) unsup_s; | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error-UNSUPPORTED: t/t_wire_trireg_unsup.v:13:4: Unsupported: trireg 13 | trireg (medium) unsup_m; | ^~~~~~ %Error: t/t_wire_trireg_unsup.v:13:12: syntax error, unexpected STRENGTH keyword (strong1/etc) 13 | trireg (medium) unsup_m; | ^~~~~~ %Error-UNSUPPORTED: t/t_wire_trireg_unsup.v:14:4: Unsupported: trireg 14 | trireg (large) unsup_l; | ^~~~~~ %Error: t/t_wire_trireg_unsup.v:14:12: syntax error, unexpected STRENGTH keyword (strong1/etc) 14 | trireg (large) unsup_l; | ^~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_interface_ref_trace_fst.out0000644000542200017500000004471115101701376024777 0ustar mahmoudyfreeshell$date Tue Oct 24 11:00:16 2023 $end $version fstWriter $end $timescale 1ps $end $scope module top $end $var wire 1 ! clk $end $scope module t $end $var wire 1 ! clk $end $var integer 32 " cyc [31:0] $end $scope interface intf_1 $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 # value [31:0] $end $scope struct the_struct $end $var integer 32 $ val100 [31:0] $end $var integer 32 % val200 [31:0] $end $upscope $end $scope interface inner $end $var wire 32 " cyc [31:0] $end $var integer 32 & value [31:0] $end $upscope $end $upscope $end $scope interface intf_2 $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 ' value [31:0] $end $scope struct the_struct $end $var integer 32 ( val100 [31:0] $end $var integer 32 ) val200 [31:0] $end $upscope $end $scope interface inner $end $var wire 32 " cyc [31:0] $end $var integer 32 * value [31:0] $end $upscope $end $upscope $end $scope module a $end $scope interface intf_one $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 # value [31:0] $end $scope struct the_struct $end $var integer 32 $ val100 [31:0] $end $var integer 32 % val200 [31:0] $end $upscope $end $scope interface inner $end $var wire 32 " cyc [31:0] $end $var integer 32 & value [31:0] $end $upscope $end $upscope $end $scope interface intf_two $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 ' value [31:0] $end $scope struct the_struct $end $var integer 32 ( val100 [31:0] $end $var integer 32 ) val200 [31:0] $end $upscope $end $scope interface inner $end $var wire 32 " cyc [31:0] $end $var integer 32 * value [31:0] $end $upscope $end $upscope $end $scope interface intf_in_sub_all $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 + value [31:0] $end $scope struct the_struct $end $var integer 32 , val100 [31:0] $end $var integer 32 - val200 [31:0] $end $upscope $end $scope interface inner $end $var wire 32 " cyc [31:0] $end $var integer 32 . value [31:0] $end $upscope $end $upscope $end $scope module ac1 $end $scope interface intf_for_check $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 # value [31:0] $end $scope struct the_struct $end $var integer 32 $ val100 [31:0] $end $var integer 32 % val200 [31:0] $end $upscope $end $scope interface inner $end $var wire 32 " cyc [31:0] $end $var integer 32 & value [31:0] $end $upscope $end $upscope $end $upscope $end $scope module ac2 $end $scope interface intf_for_check $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 ' value [31:0] $end $scope struct the_struct $end $var integer 32 ( val100 [31:0] $end $var integer 32 ) val200 [31:0] $end $upscope $end $scope interface inner $end $var wire 32 " cyc [31:0] $end $var integer 32 * value [31:0] $end $upscope $end $upscope $end $upscope $end $scope module ac3 $end $scope interface intf_for_check $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 + value [31:0] $end $scope struct the_struct $end $var integer 32 , val100 [31:0] $end $var integer 32 - val200 [31:0] $end $upscope $end $scope interface inner $end $var wire 32 " cyc [31:0] $end $var integer 32 . value [31:0] $end $upscope $end $upscope $end $upscope $end $scope module as3 $end $scope interface intf_for_struct $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 + value [31:0] $end $scope struct the_struct $end $var integer 32 , val100 [31:0] $end $var integer 32 - val200 [31:0] $end $upscope $end $scope interface inner $end $var wire 32 " cyc [31:0] $end $var integer 32 . value [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module abcdefghijklmnopqrstuvwxyz $end $scope interface intf_one $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 ' value [31:0] $end $scope struct the_struct $end $var integer 32 ( val100 [31:0] $end $var integer 32 ) val200 [31:0] $end $upscope $end $scope interface inner $end $var wire 32 " cyc [31:0] $end $var integer 32 * value [31:0] $end $upscope $end $upscope $end $scope interface intf_two $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 # value [31:0] $end $scope struct the_struct $end $var integer 32 $ val100 [31:0] $end $var integer 32 % val200 [31:0] $end $upscope $end $scope interface inner $end $var wire 32 " cyc [31:0] $end $var integer 32 & value [31:0] $end $upscope $end $upscope $end $scope interface intf_in_sub_all $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 / value [31:0] $end $scope struct the_struct $end $var integer 32 0 val100 [31:0] $end $var integer 32 1 val200 [31:0] $end $upscope $end $scope interface inner $end $var wire 32 " cyc [31:0] $end $var integer 32 2 value [31:0] $end $upscope $end $upscope $end $scope module ac1 $end $scope interface intf_for_check $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 ' value [31:0] $end $scope struct the_struct $end $var integer 32 ( val100 [31:0] $end $var integer 32 ) val200 [31:0] $end $upscope $end $scope interface inner $end $var wire 32 " cyc [31:0] $end $var integer 32 * value [31:0] $end $upscope $end $upscope $end $upscope $end $scope module ac2 $end $scope interface intf_for_check $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 # value [31:0] $end $scope struct the_struct $end $var integer 32 $ val100 [31:0] $end $var integer 32 % val200 [31:0] $end $upscope $end $scope interface inner $end $var wire 32 " cyc [31:0] $end $var integer 32 & value [31:0] $end $upscope $end $upscope $end $upscope $end $scope module ac3 $end $scope interface intf_for_check $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 / value [31:0] $end $scope struct the_struct $end $var integer 32 0 val100 [31:0] $end $var integer 32 1 val200 [31:0] $end $upscope $end $scope interface inner $end $var wire 32 " cyc [31:0] $end $var integer 32 2 value [31:0] $end $upscope $end $upscope $end $upscope $end $scope module as3 $end $scope interface intf_for_struct $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 / value [31:0] $end $scope struct the_struct $end $var integer 32 0 val100 [31:0] $end $var integer 32 1 val200 [31:0] $end $upscope $end $scope interface inner $end $var wire 32 " cyc [31:0] $end $var integer 32 2 value [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module c1 $end $scope interface intf_for_check $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 # value [31:0] $end $scope struct the_struct $end $var integer 32 $ val100 [31:0] $end $var integer 32 % val200 [31:0] $end $upscope $end $scope interface inner $end $var wire 32 " cyc [31:0] $end $var integer 32 & value [31:0] $end $upscope $end $upscope $end $upscope $end $scope module c2 $end $scope interface intf_for_check $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 ' value [31:0] $end $scope struct the_struct $end $var integer 32 ( val100 [31:0] $end $var integer 32 ) val200 [31:0] $end $upscope $end $scope interface inner $end $var wire 32 " cyc [31:0] $end $var integer 32 * value [31:0] $end $upscope $end $upscope $end $upscope $end $scope module s1 $end $scope interface intf_for_struct $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 # value [31:0] $end $scope struct the_struct $end $var integer 32 $ val100 [31:0] $end $var integer 32 % val200 [31:0] $end $upscope $end $scope interface inner $end $var wire 32 " cyc [31:0] $end $var integer 32 & value [31:0] $end $upscope $end $upscope $end $upscope $end $scope module s2 $end $scope interface intf_for_struct $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 ' value [31:0] $end $scope struct the_struct $end $var integer 32 ( val100 [31:0] $end $var integer 32 ) val200 [31:0] $end $upscope $end $scope interface inner $end $var wire 32 " cyc [31:0] $end $var integer 32 * value [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b00000000000000000000000000000000 2 b00000000000000000000010010110010 1 b00000000000000000000010001001110 0 b00000000000000000000001111101010 / b00000000000000000000000000000000 . b00000000000000000000010010110001 - b00000000000000000000010001001101 , b00000000000000000000001111101001 + b00000000000000000000000000000000 * b00000000000000000000000011001010 ) b00000000000000000000000001100110 ( b00000000000000000000000000000010 ' b00000000000000000000000000000000 & b00000000000000000000000011001001 % b00000000000000000000000001100101 $ b00000000000000000000000000000001 # b00000000000000000000000000000000 " 0! $end #10 1! b00000000000000000000000000000001 " b00000000000000000000000000000010 # b00000000000000000000000001100110 $ b00000000000000000000000011001010 % b00000000000000000000000000000011 ' b00000000000000000000000001100111 ( b00000000000000000000000011001011 ) b00000000000000000000001111101010 + b00000000000000000000010001001110 , b00000000000000000000010010110010 - b00000000000000000000001111101011 / b00000000000000000000010001001111 0 b00000000000000000000010010110011 1 #15 0! #20 1! b00000000000000000000010010110100 1 b00000000000000000000010001010000 0 b00000000000000000000001111101100 / b00000000000000000000010010110011 - b00000000000000000000010001001111 , b00000000000000000000001111101011 + b00000000000000000000000011001100 ) b00000000000000000000000001101000 ( b00000000000000000000000000000100 ' b00000000000000000000000011001011 % b00000000000000000000000001100111 $ b00000000000000000000000000000011 # b00000000000000000000000000000010 " #25 0! #30 1! b00000000000000000000000000000011 " b00000000000000000000000000000100 # b00000000000000000000000001101000 $ b00000000000000000000000011001100 % b00000000000000000000000000000101 ' b00000000000000000000000001101001 ( b00000000000000000000000011001101 ) b00000000000000000000001111101100 + b00000000000000000000010001010000 , b00000000000000000000010010110100 - b00000000000000000000001111101101 / b00000000000000000000010001010001 0 b00000000000000000000010010110101 1 #35 0! #40 1! b00000000000000000000010010110110 1 b00000000000000000000010001010010 0 b00000000000000000000001111101110 / b00000000000000000000010010110101 - b00000000000000000000010001010001 , b00000000000000000000001111101101 + b00000000000000000000000011001110 ) b00000000000000000000000001101010 ( b00000000000000000000000000000110 ' b00000000000000000000000011001101 % b00000000000000000000000001101001 $ b00000000000000000000000000000101 # b00000000000000000000000000000100 " #45 0! #50 1! b00000000000000000000000000000101 " b00000000000000000000000000000110 # b00000000000000000000000001101010 $ b00000000000000000000000011001110 % b00000000000000000000000000000111 ' b00000000000000000000000001101011 ( b00000000000000000000000011001111 ) b00000000000000000000001111101110 + b00000000000000000000010001010010 , b00000000000000000000010010110110 - b00000000000000000000001111101111 / b00000000000000000000010001010011 0 b00000000000000000000010010110111 1 #55 0! #60 1! b00000000000000000000010010111000 1 b00000000000000000000010001010100 0 b00000000000000000000001111110000 / b00000000000000000000010010110111 - b00000000000000000000010001010011 , b00000000000000000000001111101111 + b00000000000000000000000011010000 ) b00000000000000000000000001101100 ( b00000000000000000000000000001000 ' b00000000000000000000000011001111 % b00000000000000000000000001101011 $ b00000000000000000000000000000111 # b00000000000000000000000000000110 " #65 0! #70 1! b00000000000000000000000000000111 " b00000000000000000000000000001000 # b00000000000000000000000001101100 $ b00000000000000000000000011010000 % b00000000000000000000000000001001 ' b00000000000000000000000001101101 ( b00000000000000000000000011010001 ) b00000000000000000000001111110000 + b00000000000000000000010001010100 , b00000000000000000000010010111000 - b00000000000000000000001111110001 / b00000000000000000000010001010101 0 b00000000000000000000010010111001 1 #75 0! #80 1! b00000000000000000000010010111010 1 b00000000000000000000010001010110 0 b00000000000000000000001111110010 / b00000000000000000000010010111001 - b00000000000000000000010001010101 , b00000000000000000000001111110001 + b00000000000000000000000011010010 ) b00000000000000000000000001101110 ( b00000000000000000000000000001010 ' b00000000000000000000000011010001 % b00000000000000000000000001101101 $ b00000000000000000000000000001001 # b00000000000000000000000000001000 " #85 0! #90 1! b00000000000000000000000000001001 " b00000000000000000000000000001010 # b00000000000000000000000001101110 $ b00000000000000000000000011010010 % b00000000000000000000000000001011 ' b00000000000000000000000001101111 ( b00000000000000000000000011010011 ) b00000000000000000000001111110010 + b00000000000000000000010001010110 , b00000000000000000000010010111010 - b00000000000000000000001111110011 / b00000000000000000000010001010111 0 b00000000000000000000010010111011 1 #95 0! #100 1! b00000000000000000000010010111100 1 b00000000000000000000010001011000 0 b00000000000000000000001111110100 / b00000000000000000000010010111011 - b00000000000000000000010001010111 , b00000000000000000000001111110011 + b00000000000000000000000011010100 ) b00000000000000000000000001110000 ( b00000000000000000000000000001100 ' b00000000000000000000000011010011 % b00000000000000000000000001101111 $ b00000000000000000000000000001011 # b00000000000000000000000000001010 " #105 0! #110 1! b00000000000000000000000000001011 " b00000000000000000000000000001100 # b00000000000000000000000001110000 $ b00000000000000000000000011010100 % b00000000000000000000000000001101 ' b00000000000000000000000001110001 ( b00000000000000000000000011010101 ) b00000000000000000000001111110100 + b00000000000000000000010001011000 , b00000000000000000000010010111100 - b00000000000000000000001111110101 / b00000000000000000000010001011001 0 b00000000000000000000010010111101 1 #115 0! #120 1! b00000000000000000000010010111110 1 b00000000000000000000010001011010 0 b00000000000000000000001111110110 / b00000000000000000000010010111101 - b00000000000000000000010001011001 , b00000000000000000000001111110101 + b00000000000000000000000011010110 ) b00000000000000000000000001110010 ( b00000000000000000000000000001110 ' b00000000000000000000000011010101 % b00000000000000000000000001110001 $ b00000000000000000000000000001101 # b00000000000000000000000000001100 " #125 0! #130 1! b00000000000000000000000000001101 " b00000000000000000000000000001110 # b00000000000000000000000001110010 $ b00000000000000000000000011010110 % b00000000000000000000000000001111 ' b00000000000000000000000001110011 ( b00000000000000000000000011010111 ) b00000000000000000000001111110110 + b00000000000000000000010001011010 , b00000000000000000000010010111110 - b00000000000000000000001111110111 / b00000000000000000000010001011011 0 b00000000000000000000010010111111 1 #135 0! #140 1! b00000000000000000000010011000000 1 b00000000000000000000010001011100 0 b00000000000000000000001111111000 / b00000000000000000000010010111111 - b00000000000000000000010001011011 , b00000000000000000000001111110111 + b00000000000000000000000011011000 ) b00000000000000000000000001110100 ( b00000000000000000000000000010000 ' b00000000000000000000000011010111 % b00000000000000000000000001110011 $ b00000000000000000000000000001111 # b00000000000000000000000000001110 " #145 0! #150 1! b00000000000000000000000000001111 " b00000000000000000000000000010000 # b00000000000000000000000001110100 $ b00000000000000000000000011011000 % b00000000000000000000000000010001 ' b00000000000000000000000001110101 ( b00000000000000000000000011011001 ) b00000000000000000000001111111000 + b00000000000000000000010001011100 , b00000000000000000000010011000000 - b00000000000000000000001111111001 / b00000000000000000000010001011101 0 b00000000000000000000010011000001 1 #155 0! #160 1! b00000000000000000000010011000010 1 b00000000000000000000010001011110 0 b00000000000000000000001111111010 / b00000000000000000000010011000001 - b00000000000000000000010001011101 , b00000000000000000000001111111001 + b00000000000000000000000011011010 ) b00000000000000000000000001110110 ( b00000000000000000000000000010010 ' b00000000000000000000000011011001 % b00000000000000000000000001110101 $ b00000000000000000000000000010001 # b00000000000000000000000000010000 " #165 0! #170 1! b00000000000000000000000000010001 " b00000000000000000000000000010010 # b00000000000000000000000001110110 $ b00000000000000000000000011011010 % b00000000000000000000000000010011 ' b00000000000000000000000001110111 ( b00000000000000000000000011011011 ) b00000000000000000000001111111010 + b00000000000000000000010001011110 , b00000000000000000000010011000010 - b00000000000000000000001111111011 / b00000000000000000000010001011111 0 b00000000000000000000010011000011 1 #175 0! #180 1! b00000000000000000000010011000100 1 b00000000000000000000010001100000 0 b00000000000000000000001111111100 / b00000000000000000000010011000011 - b00000000000000000000010001011111 , b00000000000000000000001111111011 + b00000000000000000000000011011100 ) b00000000000000000000000001111000 ( b00000000000000000000000000010100 ' b00000000000000000000000011011011 % b00000000000000000000000001110111 $ b00000000000000000000000000010011 # b00000000000000000000000000010010 " #185 0! #190 1! b00000000000000000000000000010011 " b00000000000000000000000000010100 # b00000000000000000000000001111000 $ b00000000000000000000000011011100 % b00000000000000000000000000010101 ' b00000000000000000000000001111001 ( b00000000000000000000000011011101 ) b00000000000000000000001111111100 + b00000000000000000000010001100000 , b00000000000000000000010011000100 - b00000000000000000000001111111101 / b00000000000000000000010001100001 0 b00000000000000000000010011000101 1 #195 0! #200 1! b00000000000000000000010011000110 1 b00000000000000000000010001100010 0 b00000000000000000000001111111110 / b00000000000000000000010011000101 - b00000000000000000000010001100001 , b00000000000000000000001111111101 + b00000000000000000000000011011110 ) b00000000000000000000000001111010 ( b00000000000000000000000000010110 ' b00000000000000000000000011011101 % b00000000000000000000000001111001 $ b00000000000000000000000000010101 # b00000000000000000000000000010100 " #205 0! #210 1! b00000000000000000000000000010101 " b00000000000000000000000000010110 # b00000000000000000000000001111010 $ b00000000000000000000000011011110 % b00000000000000000000000000010111 ' b00000000000000000000000001111011 ( b00000000000000000000000011011111 ) b00000000000000000000001111111110 + b00000000000000000000010001100010 , b00000000000000000000010011000110 - b00000000000000000000001111111111 / b00000000000000000000010001100011 0 b00000000000000000000010011000111 1 verilator-5.042/test_regress/t/t_math_shift_sel.v0000644000542200017500000000467115101701376022601 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [106:0] in = {~crc[42:0], crc[63:0]}; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [7:0] out1; // From test of Test.v wire [7:0] out2; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out1 (out1[7:0]), .out2 (out2[7:0]), // Inputs .in (in[106:0])); // Aggregate outputs into a single result vector wire [63:0] result = {48'h0, out1, out1}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc<10) begin sum <= '0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'hc746017202a24ecc if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs out1, out2, // Inputs in ); // Replace this module with the device under test. // // Change the code in the t module to apply values to the inputs and // merge the output values into the result vector. input [106:0] in; output [7:0] out1, out2; // verilator lint_off WIDTH // Better written as onibble[99 +: 8]. Verilator will convert it. wire [7:0] out1 = (in >>> 99) & 255; // verilator lint_on WIDTH wire [7:0] out2 = in[106:99]; endmodule verilator-5.042/test_regress/t/t_inst_slice_noinl.py0000755000542200017500000000103315101701376023316 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_inst_slice.v" test.compile(v_flags2=["-fno-inline"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_timing_intra_assign_func.py0000755000542200017500000000077115101701376025036 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_timing_finish.v0000644000542200017500000000050015101701376022422 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 program t; initial begin $write("*-* All Finished *-*\n"); // No $finish end endprogram verilator-5.042/test_regress/t/t_stream_struct.py0000755000542200017500000000073415101701376022671 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_clk_vecgen1.v0000644000542200017500000000611015101701376021757 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; wire [1:0] clkvec = crc[1:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [1:0] count; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .count (count[1:0]), // Inputs .clkvec (clkvec[1:0])); // Aggregate outputs into a single result vector wire [63:0] result = {62'h0, count}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; `define EXPECTED_SUM 64'hfe8bac0bb1a0e53b if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule `ifdef T_TEST1 module Test ( input wire [1:0] clkvec, // verilator lint_off MULTIDRIVEN output reg [1:0] count // verilator lint_on MULTIDRIVEN ); genvar igen; generate for (igen=0; igen<2; igen=igen+1) begin : code_gen initial count[igen] = 1'b0; always @ (posedge clkvec[igen]) count[igen] <= count[igen] + 1; end endgenerate always @ (count) begin $write("hi\n"); end endmodule `endif `ifdef T_TEST2 module Test ( input wire [1:0] clkvec, // verilator lint_off MULTIDRIVEN output reg [1:0] count // verilator lint_on MULTIDRIVEN ); genvar igen; generate for (igen=0; igen<2; igen=igen+1) begin : code_gen wire clk_tmp = clkvec[igen]; // Unsupported: Count is multidriven, though if we did better analysis it wouldn't // need to be. initial count[igen] = 1'b0; always @ (posedge clk_tmp) count[igen] <= count[igen] + 1; end endgenerate endmodule `endif `ifdef T_TEST3 module Test ( input wire [1:0] clkvec, output wire [1:0] count ); genvar igen; generate for (igen=0; igen<2; igen=igen+1) begin : code_gen wire clk_tmp = clkvec[igen]; reg tmp_count = 1'b0; always @ (posedge clk_tmp) begin tmp_count <= tmp_count + 1; end assign count[igen] = tmp_count; end endgenerate endmodule `endif verilator-5.042/test_regress/t/t_var_bad_sameas.out0000644000542200017500000000314515101701376023074 0ustar mahmoudyfreeshell%Error: t/t_var_bad_sameas.v:10:8: Unsupported in C: Instance has the same name as variable: 'varfirst' 10 | sub varfirst (); | ^~~~~~~~ t/t_var_bad_sameas.v:9:12: ... Location of original declaration 9 | integer varfirst; | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_var_bad_sameas.v:11:9: Unsupported in C: Task has the same name as instance: 'varfirst' 11 | task varfirst; begin end endtask | ^~~~~~~~ t/t_var_bad_sameas.v:10:8: ... Location of original declaration 10 | sub varfirst (); | ^~~~~~~~ %Error: t/t_var_bad_sameas.v:14:12: Unsupported in C: Variable has same name as instance: 'cellfirst' 14 | integer cellfirst; | ^~~~~~~~~ %Error: t/t_var_bad_sameas.v:15:9: Unsupported in C: Task has the same name as instance: 'cellfirst' 15 | task cellfirst; begin end endtask | ^~~~~~~~~ t/t_var_bad_sameas.v:13:8: ... Location of original declaration 13 | sub cellfirst (); | ^~~~~~~~~ %Error: t/t_var_bad_sameas.v:18:12: Unsupported in C: Variable has same name as task: 'taskfirst' 18 | integer taskfirst; | ^~~~~~~~~ %Error: t/t_var_bad_sameas.v:19:8: Unsupported in C: Instance has the same name as task: 'taskfirst' 19 | sub taskfirst (); | ^~~~~~~~~ t/t_var_bad_sameas.v:17:9: ... Location of original declaration 17 | task taskfirst; begin end endtask | ^~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_assert_synth_parallel_vlt.py0000755000542200017500000000135115101701376025255 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_assert_synth.v" test.compile(v_flags2=['+define+FAILING_PARALLEL', "t/t_assert_synth_parallel.vlt"], verilator_flags2=['--assert'], nc_flags2=['+assert']) test.execute(check_finished=False, fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_unconnected.py0000755000542200017500000000073415101701376022277 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_sys_strobe.v0000644000542200017500000000204415101701376021774 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; int cyc = 0; // Test loop always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 10) begin $strobe("[%0t] cyc=%0d", $time, cyc); $strobe("[%0t] cyc=%0d also", $time, cyc); end else if (cyc == 17) begin $strobeb(cyc, "b"); end else if (cyc == 18) begin $strobeh(cyc, "h"); end else if (cyc == 19) begin $strobeo(cyc, "o"); end else if (cyc == 22) begin $strobe("[%0t] cyc=%0d new-strobe", $time, cyc); end else if (cyc == 24) begin $monitoroff; end else if (cyc == 26) begin $monitoron; end else if (cyc == 30) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_var_dup3.py0000755000542200017500000000070615101701376021514 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.042/test_regress/t/t_select_param.v0000644000542200017500000000075315101701376022244 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; parameter [ BMSB : BLSB ] B = A[23:20]; // 3 parameter A = 32'h12345678; parameter BLSB = A[16+:4]; // 4 parameter BMSB = A[7:4]; // 7 initial begin if (B !== 4'h3) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_trace_complex_params_fst.out0000644000542200017500000001136715101701376025216 0ustar mahmoudyfreeshell$date Tue Jun 10 19:02:39 2025 $end $version fstWriter $end $timescale 1ps $end $scope module top $end $attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end $attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end $var wire 1 ! clk $end $scope module $unit $end $var bit 1 " global_bit $end $upscope $end $scope module t $end $var wire 1 ! clk $end $var integer 32 # cyc [31:0] $end $var bit 2 $ v_strp [1:0] $end $var bit 4 % v_strp_strp [3:0] $end $var bit 2 & v_unip_strp [1:0] $end $var bit 2 ' v_arrp [2:1] $end $var bit 4 ( v_arrp_arrp [3:0] $end $var bit 4 ) v_arrp_strp [3:0] $end $var bit 1 * v_arru[1] $end $var bit 1 + v_arru[2] $end $var bit 1 , v_arru_arru[3][1] $end $var bit 1 - v_arru_arru[3][2] $end $var bit 1 . v_arru_arru[4][1] $end $var bit 1 / v_arru_arru[4][2] $end $var bit 2 0 v_arru_arrp[3] [2:1] $end $var bit 2 1 v_arru_arrp[4] [2:1] $end $var bit 2 2 v_arru_strp[3] [1:0] $end $var bit 2 3 v_arru_strp[4] [1:0] $end $var real 64 4 v_real $end $var real 64 5 v_arr_real[0] $end $var real 64 6 v_arr_real[1] $end $var longint 64 7 v_chandle [63:0] $end $var logic 64 8 v_str32x2 [63:0] $end $attrbegin misc 07 "" 1 $end $var int 32 9 v_enumed [31:0] $end $attrbegin misc 07 "" 1 $end $var int 32 : v_enumed2 [31:0] $end $attrbegin misc 07 "" 2 $end $var logic 3 ; v_enumb [2:0] $end $var logic 6 < v_enumb2_str [5:0] $end $var logic 8 = unpacked_array[-2] [7:0] $end $var logic 8 > unpacked_array[-1] [7:0] $end $var logic 8 ? unpacked_array[0] [7:0] $end $var bit 1 @ LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end $scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end $var parameter 32 A PARAM [31:0] $end $upscope $end $scope module p2 $end $var parameter 32 B PARAM [31:0] $end $upscope $end $scope module p3 $end $var parameter 32 C PARAM [31:0] $end $upscope $end $scope module unnamedblk1 $end $var integer 32 D b [31:0] $end $scope module unnamedblk2 $end $var integer 32 E a [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b00000000000000000000000000000000 E b00000000000000000000000000000000 D b00000000000000000000000000000011 C b00000000000000000000000000000010 B b00000000000000000000000000000100 A 0@ b00000000 ? b00000000 > b00000000 = b000000 < b000 ; b00000000000000000000000000000000 : b00000000000000000000000000000000 9 b0000000000000000000000000000000000000000000000000000000011111111 8 b0000000000000000000000000000000000000000000000000000000000000000 7 r0 6 r0 5 r0 4 b00 3 b00 2 b00 1 b00 0 0/ 0. 0- 0, 0+ 0* b0000 ) b0000 ( b00 ' b00 & b0000 % b00 $ b00000000000000000000000000000000 # 1" 0! $end #10 1! b00000000000000000000000000000001 # b11 $ b1111 % b11 & b11 ' b1111 ( b1111 ) b11 0 b11 1 b11 2 b11 3 r0.1 4 r0.2 5 r0.3 6 b0000000000000000000000000000000100000000000000000000000011111110 8 b00000000000000000000000000000001 9 b00000000000000000000000000000010 : b111 ; b00000000000000000000000000000101 D b00000000000000000000000000000101 E #15 0! #20 1! b110 ; b00000000000000000000000000000100 : b00000000000000000000000000000010 9 b0000000000000000000000000000001000000000000000000000000011111101 8 r0.6 6 r0.4 5 r0.2 4 b00 3 b00 2 b00 1 b00 0 b0000 ) b0000 ( b00 ' b00 & b0000 % b00 $ b00000000000000000000000000000010 # b111111 < #25 0! #30 1! b110110 < b00000000000000000000000000000011 # b11 $ b1111 % b11 & b11 ' b1111 ( b1111 ) b11 0 b11 1 b11 2 b11 3 r0.3 4 r0.6000000000000001 5 r0.8999999999999999 6 b0000000000000000000000000000001100000000000000000000000011111100 8 b00000000000000000000000000000011 9 b00000000000000000000000000000110 : b101 ; #35 0! #40 1! b100 ; b00000000000000000000000000001000 : b00000000000000000000000000000100 9 b0000000000000000000000000000010000000000000000000000000011111011 8 r1.2 6 r0.8 5 r0.4 4 b00 3 b00 2 b00 1 b00 0 b0000 ) b0000 ( b00 ' b00 & b0000 % b00 $ b00000000000000000000000000000100 # b101101 < #45 0! #50 1! b100100 < b00000000000000000000000000000101 # b11 $ b1111 % b11 & b11 ' b1111 ( b1111 ) b11 0 b11 1 b11 2 b11 3 r0.5 4 r1 5 r1.5 6 b0000000000000000000000000000010100000000000000000000000011111010 8 b00000000000000000000000000000101 9 b00000000000000000000000000001010 : b011 ; #55 0! #60 1! b010 ; b00000000000000000000000000001100 : b00000000000000000000000000000110 9 b0000000000000000000000000000011000000000000000000000000011111001 8 r1.8 6 r1.2 5 r0.6 4 b00 3 b00 2 b00 1 b00 0 b0000 ) b0000 ( b00 ' b00 & b0000 % b00 $ b00000000000000000000000000000110 # b011011 < verilator-5.042/test_regress/t/t_force_release_var_trace.out0000644000542200017500000000422515101701376024771 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $var wire 1 # clk $end $scope module t $end $var wire 1 # clk $end $var wire 32 $ cyc [31:0] $end $var wire 1 % var_1 $end $var wire 8 & var_8 [7:0] $end $upscope $end $upscope $end $enddefinitions $end #0 0# b00000000000000000000000000000000 $ 0% b00000000 & #10 1# b00000000000000000000000000000001 $ #15 0# #20 1# b00000000000000000000000000000010 $ 1% #25 0# #30 1# b00000000000000000000000000000011 $ 0% b00000001 & #35 0# #40 1# b00000000000000000000000000000100 $ 1% #45 0# #50 1# b00000000000000000000000000000101 $ 0% b00000010 & #55 0# #60 1# b00000000000000000000000000000110 $ 1% #65 0# #70 1# b00000000000000000000000000000111 $ 0% b00000011 & #75 0# #80 1# b00000000000000000000000000001000 $ 1% #85 0# #90 1# b00000000000000000000000000001001 $ 0% b00000100 & #95 0# #100 1# b00000000000000000000000000001010 $ 1% #105 0# #110 1# b00000000000000000000000000001011 $ 0% b00000101 & #115 0# #120 1# b00000000000000000000000000001100 $ 1% #125 0# #130 1# b00000000000000000000000000001101 $ 0% b00000110 & #135 0# #140 1# b00000000000000000000000000001110 $ 1% #145 0# #150 1# b00000000000000000000000000001111 $ b11110101 & #155 0# #160 1# b00000000000000000000000000010000 $ 0% #165 0# #170 1# b00000000000000000000000000010001 $ b01011111 & #175 0# #180 1# b00000000000000000000000000010010 $ #185 0# #190 1# b00000000000000000000000000010011 $ #195 0# #200 1# b00000000000000000000000000010100 $ 1% b00001001 & #205 0# #210 1# b00000000000000000000000000010101 $ b01011010 & #215 0# #220 1# b00000000000000000000000000010110 $ #225 0# #230 1# b00000000000000000000000000010111 $ 0% b10100101 & #235 0# #240 1# b00000000000000000000000000011000 $ #245 0# #250 1# b00000000000000000000000000011001 $ b00001100 & #255 0# #260 1# b00000000000000000000000000011010 $ 1% #265 0# #270 1# b00000000000000000000000000011011 $ 0% b00001101 & #275 0# #280 1# b00000000000000000000000000011100 $ 1% #285 0# #290 1# b00000000000000000000000000011101 $ 0% b00001110 & #295 0# #300 1# b00000000000000000000000000011110 $ 1% #305 0# #310 1# b00000000000000000000000000011111 $ 0% b00001111 & verilator-5.042/test_regress/t/t_math_const.v0000644000542200017500000001266315101701376021747 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [39:0] con1,con2, con3; reg [31:0] w32; reg [31:0] v32 [2]; // surefire lint_off UDDSCN reg [200:0] conw3, conw4; // surefire lint_on UDDSCN reg [16*8-1:0] con__ascii; reg [31:0] win; // Test casting is proper on narrow->wide->narrow conversions // verilator lint_off WIDTH wire [49:0] wider = ({18'h0, win} | (1'b1<<32)) - 50'h111; wire [31:0] wider2 = ({win} | (1'b1<<32)) - 50'd111; // verilator lint_on WIDTH wire [31:0] narrow = wider[31:0]; wire [31:0] narrow2 = wider2[31:0]; // surefire lint_off ASWEMB // surefire lint_off ASWCMB // surefire lint_off CWECBB // surefire lint_off CWECSB // surefire lint_off STMINI integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin $write("[%0t] t_const: Running\n", $time); con1 = 4_0'h1000_0010; // Odd but legal _ in width con2 = 40'h10_0000_0010; con3 = con1 + 40'h10_1100_0101; if (con1[31:0]!== 32'h1000_0010 || con1[39:32]!==0) $stop; $display("%x %x %x\n", con2, con2[31:0], con2[39:32]); if (con2[31:0]!== 32'h10 || con2[39:32]!==8'h10) $stop; if (con3[31:0]!==32'h2100_0111 || con3[39:32]!==8'h10) $stop; // verilator lint_off WIDTH con1 = 10'h10 + 40'h80_1100_0131; // verilator lint_on WIDTH con2 = 40'h80_0000_0000 + 40'h13_7543_0107; if (con1[31:0]!== 32'h1100_0141 || con1[39:32]!==8'h80) $stop; if (con2[31:0]!== 32'h7543_0107 || con2[39:32]!==8'h93) $stop; // verilator lint_off WIDTH conw3 = 94'h000a_5010_4020_3030_2040_1050; // verilator lint_on WIDTH if (conw3[31:00]!== 32'h2040_1050 || conw3[63:32]!== 32'h4020_3030 || conw3[95:64]!== 32'h000a_5010 || conw3[128:96]!==33'h0) $stop; $display("%x... %x\n", conw3[15:0], ~| conw3[15:0]); if ((~| conw3[15:0]) !== 1'h0) $stop; if ((~& conw3[15:0]) !== 1'h1) $stop; // verilator lint_off WIDTH conw4 = 112'h7010_602a_5030_4040_3050_2060_1070; // verilator lint_on WIDTH if (conw4[31:00]!== 32'h2060_1070 || conw4[63:32]!== 32'h4040_3050 || conw4[95:64]!== 32'h602a_5030 || conw4[127:96]!==32'h7010) $stop; // conw4 = 144'h7000_7000_7010_602a_5030_4040_3050_2060_1070; w32 = 12; win <= 12; if ((32'hffff0000 >> w32) != 32'h 000ffff0) $stop; con__ascii = "abcdefghijklmnop"; if ( con__ascii !== {"abcd","efgh","ijkl","mnop"}) $stop; con__ascii = "abcdefghijklm"; if ( con__ascii !== {24'h0,"a","bcde","fghi","jklm"}) $stop; if ( 3'dx !== 3'hx) $stop; // Wide decimal if ( 94'd12345678901234567890123456789 != 94'h27e41b3246bec9b16e398115) $stop; if (-94'sd123456789012345678901234567 != 94'h3f99e1020ea70d57d360b479) $stop; // Increments w32 = 12; w32++; if (w32 != 13) $stop; w32 = 12; ++w32; if (w32 != 13) $stop; w32 = 12; w32--; if (w32 != 11) $stop; w32 = 12; --w32; if (w32 != 11) $stop; w32 = 12; w32 += 2; if (w32 != 14) $stop; w32 = 12; w32 -= 2; if (w32 != 10) $stop; w32 = 12; w32 *= 2; if (w32 != 24) $stop; w32 = 12; w32 /= 2; if (w32 != 6) $stop; w32 = 12; w32 &= 6; if (w32 != 4) $stop; w32 = 12; w32 |= 15; if (w32 != 15) $stop; w32 = 12; w32 ^= 15; if (w32 != 3) $stop; w32 = 12; w32 >>= 1; if (w32 != 6) $stop; w32 = 12; w32 >>>= 1; if (w32 != 6) $stop; w32 = 12; w32 <<= 1; if (w32 != 24) $stop; w32 = 12; w32 %= 5; if (w32 != 2) $stop; // Increments v32[1] = 12; v32[1]++; if (v32[1] != 13) $stop; v32[1] = 12; ++v32[1]; if (v32[1] != 13) $stop; v32[1] = 12; v32[1]--; if (v32[1] != 11) $stop; v32[1] = 12; --v32[1]; if (v32[1] != 11) $stop; v32[1] = 12; v32[1] += 2; if (v32[1] != 14) $stop; v32[1] = 12; v32[1] -= 2; if (v32[1] != 10) $stop; v32[1] = 12; v32[1] *= 2; if (v32[1] != 24) $stop; v32[1] = 12; v32[1] /= 2; if (v32[1] != 6) $stop; v32[1] = 12; v32[1] &= 6; if (v32[1] != 4) $stop; v32[1] = 12; v32[1] |= 15; if (v32[1] != 15) $stop; v32[1] = 12; v32[1] ^= 15; if (v32[1] != 3) $stop; v32[1] = 12; v32[1] >>= 1; if (v32[1] != 6) $stop; v32[1] = 12; v32[1] <<= 1; if (v32[1] != 24) $stop; end if (cyc==2) begin win <= 32'h123123; if (narrow !== 32'hfffffefb) $stop; if (narrow2 !== 32'hffffff9d) $stop; end if (cyc==3) begin if (narrow !== 32'h00123012) $stop; if (narrow2 !== 32'h001230b4) $stop; end if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.042/test_regress/t/t_lint_ifdepth_bad.v0000644000542200017500000000226115101701376023060 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; integer value = 19; initial begin if (value==1) begin end else if (value==2) begin end else if (value==3) begin end else if (value==4) begin end else if (value==5) begin end else if (value==6) begin end else if (value==7) begin end else if (value==8) begin end else if (value==9) begin end else if (value==10) begin end else if (value==11) begin end // Warn about this one else if (value==12) begin end end initial begin unique0 if (value==1) begin end else if (value==2) begin end else if (value==3) begin end else if (value==4) begin end else if (value==5) begin end else if (value==6) begin end else if (value==7) begin end else if (value==8) begin end else if (value==9) begin end else if (value==10) begin end else if (value==11) begin end // Warn about this one else if (value==12) begin end end endmodule verilator-5.042/test_regress/t/t_virtual_interface_gen_for_ref.py0000755000542200017500000000073415101701376026033 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_extend_class.v0000644000542200017500000000270215101701376022255 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Although strange, Verilog defines are expanded inside the C blocks // (as the `systemc_* directives are opaque to the preprocessor) `define finished "*-* All Finished *-*\n" class Cls; `ifdef verilator `systemc_header #define DID_INT_HEADER 1 `systemc_header_post inline void `systemc_class_name::my_inline_function() {} `systemc_interface #ifndef DID_INT_HEADER #error "`systemc_header didn't work" #endif bool m_did_ctor; uint32_t my_function() { if (!m_did_ctor) vl_fatal(__FILE__, __LINE__, __FILE__, "`systemc_ctor didn't work"); return 1; } static void my_imp_function(); static void my_inline_function(); `systemc_imp_header #define DID_IMP_HEADER 1 `systemc_implementation void `systemc_class_name::my_imp_function() { } `systemc_ctor // Works, but using a $c inside a `function new` might be cleaner m_did_ctor = 1; `systemc_dtor printf("In systemc_dtor\n"); printf(`finished); `verilog `endif // verilator endclass module t; int i; initial begin Cls c; c = new; i = $c(c, "->my_function()"); $c(c, "->my_imp_function();"); $c(c, "->my_inline_function();"); c = null; // Causes destruction and All Finished $finish; end endmodule verilator-5.042/test_regress/t/t_fork_dynscope_interface.v0000644000542200017500000000135715101701376024473 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; Iface ifc(); rvlab_tests uut (.ifc); always begin uut.test_idcode(); end initial begin #1; $write("*-* All Finished *-*\n"); $finish; end endmodule interface Iface; logic tck; logic tdo; task tsk(output logic [31:0] data_o, input logic [31:0] data_i); @(posedge tck); data_o[$size(data_i)-1] <= tdo; endtask endinterface module rvlab_tests ( Iface ifc); task test_idcode(); bit [31:0] idcode_read; ifc.tsk(idcode_read, '0); endtask endmodule verilator-5.042/test_regress/t/t_lint_unused_tri.v0000644000542200017500000000104315101701376023005 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module Receiver(in); inout [31:0] in; always @(in) $display(in); endmodule module Sender(out); inout [31:0] out; assign out = 12; endmodule module t; // ports of submodule recv tri [31 : 0] recvIn; // submodule recv Receiver recv(.in(recvIn)); // submodule send Sender send(.out(recvIn)); endmodule verilator-5.042/test_regress/t/t_scope_map.cpp0000644000542200017500000001256315101701376022072 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include #include #include VM_PREFIX_INCLUDE #include #include const unsigned long long dt_2 = 3; int main(int argc, char** argv) { const std::unique_ptr contextp{new VerilatedContext}; VM_PREFIX* top = new VM_PREFIX{contextp.get(), "top"}; contextp->debug(0); contextp->traceEverOn(true); VerilatedVcdC* tfp = new VerilatedVcdC; top->trace(tfp, 99); tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); top->CLK = 0; top->eval(); tfp->dump(contextp->time()); contextp->timeInc(1); const VerilatedScopeNameMap* scopeMapp = contextp->scopeNameMap(); for (VerilatedScopeNameMap::const_iterator it = scopeMapp->begin(); it != scopeMapp->end(); ++it) { #ifdef TEST_VERBOSE VL_PRINTF("---------------------------------------------\n"); VL_PRINTF("Scope = %s\n", it->first); it->second->scopeDump(); #endif VerilatedVarNameMap* varNameMap = it->second->varsp(); if (!varNameMap) { VL_PRINTF("%%Error: Bad varsp()\n"); return -1; } for (const auto& varname : *varNameMap) { const VerilatedVar* varp = &(varname.second); int varLeft = varp->range(0)->left(); int varRight = varp->range(0)->right(); #ifdef TEST_VERBOSE VL_PRINTF("\tVar = %s\n", varname.first); VL_PRINTF("\t Type = %d\n", varp->vltype()); VL_PRINTF("\t EntSize = %d\n", varp->entSize()); VL_PRINTF("\t Dims = %d\n", varp->dims()); VL_PRINTF("\t Range = %d:%d\n", varLeft, varRight); VL_PRINTF("\t Is RW = %d\n", varp->isPublicRW()); #endif if (varRight != 0) { VL_PRINTF("%%Error: Was expecting right range value = 0\n"); return -1; } int varBits = varLeft + 1; // First expect an incrementing byte pattern uint8_t* varData = reinterpret_cast(varp->datap()); for (int i = 0; i < varBits / 8; i++) { #ifdef TEST_VERBOSE VL_PRINTF("%02x ", varData[i]); #endif const uint8_t expected = i % 0xff; if (varData[i] != expected) { VL_PRINTF("%%Error: Data mismatch, got 0x%02x, expected 0x%02x\n", varData[i], expected); return -1; } } // Extra bits all set high initially if (varBits % 8 != 0) { const uint8_t got = varData[varBits / 8]; const uint8_t expected = ~(0xff << (varBits % 8)); if (got != expected) { VL_PRINTF("%%Error: Data mismatch, got 0x%02x, expected 0x%02x\n", got, expected); return -1; } } #ifdef TEST_VERBOSE VL_PRINTF("\n"); #endif // Clear out the data std::memset(varData, 0, (varBits + 7) / 8); } } top->CLK = 0; top->eval(); tfp->dump(contextp->time()); contextp->timeInc(1); // Posedge on clock, expect all the public bits to flip top->CLK = 1; top->eval(); tfp->dump(contextp->time()); contextp->timeInc(1); for (VerilatedScopeNameMap::const_iterator it = scopeMapp->begin(); it != scopeMapp->end(); ++it) { VerilatedVarNameMap* varNameMap = it->second->varsp(); if (!varNameMap) { VL_PRINTF("%%Error: Bad varsp()\n"); return -1; } for (const auto& varname : *varNameMap) { const VerilatedVar* varp = &(varname.second); int varLeft = varp->range(0)->left(); int varBits = varLeft + 1; uint8_t* varData = reinterpret_cast(varp->datap()); // Cover illegal access if (varp->range(1000) != nullptr) { VL_PRINTF("%%Error: Range null mismatch\n"); return -1; } // Check that all bits are high now for (int i = 0; i < varBits / 8; i++) { const uint8_t expected = 0xff; if (varData[i] != expected) { VL_PRINTF("%%Error: Data mismatch (%s), got 0x%02x, expected 0x%02x\n", varname.first, varData[i], expected); return -1; } } if (varBits % 8 != 0) { const uint8_t got = varData[varBits / 8]; const uint8_t expected = ~(0xff << (varBits % 8)); if (got != expected) { VL_PRINTF("%%Error: Data mismatch (%s), got 0x%02x, expected 0x%02x\n", varname.first, got, expected); return -1; } } } } top->CLK = 0; top->eval(); tfp->dump(contextp->time()); contextp->timeInc(1); tfp->close(); top->final(); VL_DO_DANGLING(delete tfp, tfp); VL_DO_DANGLING(delete top, top); VL_PRINTF("*-* All Finished *-*\n"); return 0; } verilator-5.042/test_regress/t/TestVpiMain.cpp0000644000542200017500000001273415101701376022004 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2024-2025 by Andrew Nolte. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // Copyright cocotb contributors // Licensed under the Revised BSD License, see LICENSE for details. // SPDX-License-Identifier: BSD-3-Clause #include "verilated.h" #include "verilated_vpi.h" #include VM_PREFIX_INCLUDE #include #include extern "C" { #include } #ifndef VM_TRACE_FST // emulate new verilator behavior for legacy versions #define VM_TRACE_FST 0 #endif #if VM_TRACE #if VM_TRACE_FST #include #else #include #endif #endif extern void (*vlog_startup_routines[])(); static bool settle_value_callbacks() { bool cbs_called; bool again; // Call Value Change callbacks // These can modify signal values so we loop // until there are no more changes cbs_called = again = VerilatedVpi::callValueCbs(); while (again) { again = VerilatedVpi::callValueCbs(); } return cbs_called; } int main(int argc, char** argv) { const std::unique_ptr contextp{new VerilatedContext}; bool traceOn = false; for (int i = 1; i < argc; ++i) { const std::string arg = std::string(argv[i]); if (arg == "--trace") { traceOn = true; } else if (arg == "--help") { fprintf(stderr, "usage: %s [--trace]\n" "\n" "Cocotb + Verilator sim\n" "\n" "options:\n" " --trace Enables tracing (VCD or FST)\n", basename(argv[0])); return 0; } } (void)traceOn; // Prevent unused if VM_TRACE not defined contextp->commandArgs(argc, argv); #ifdef VERILATOR_SIM_DEBUG contextp->debug(99); #endif const std::unique_ptr top{new VM_PREFIX{contextp.get(), // Note null name - we're flattening it out ""}}; contextp->fatalOnVpiError(false); // otherwise it will fail on systemtf #ifdef VERILATOR_SIM_DEBUG contextp->internalsDump(); #endif for (auto it = &vlog_startup_routines[0]; *it != nullptr; it++) { auto routine = *it; routine(); } VerilatedVpi::callCbs(cbStartOfSimulation); #if VM_TRACE #if VM_TRACE_FST std::unique_ptr tfp(new VerilatedFstC); const char* traceFile = "dump.fst"; #else std::unique_ptr tfp(new VerilatedVcdC); const char* traceFile = "dump.vcd"; #endif if (traceOn) { contextp->traceEverOn(true); top->trace(tfp.get(), 99); tfp->open(traceFile); } #endif while (!contextp->gotFinish()) { do { // We must evaluate whole design until we process all 'events' for // this time step do { top->eval_step(); VerilatedVpi::clearEvalNeeded(); VerilatedVpi::doInertialPuts(); settle_value_callbacks(); } while (VerilatedVpi::evalNeeded()); // Run ReadWrite callback as we are done processing this eval step VerilatedVpi::callCbs(cbReadWriteSynch); VerilatedVpi::doInertialPuts(); settle_value_callbacks(); } while (VerilatedVpi::evalNeeded() || VerilatedVpi::hasCbs(cbReadWriteSynch)); top->eval_end_step(); // Call ReadOnly callbacks VerilatedVpi::callCbs(cbReadOnlySynch); #if VM_TRACE if (traceOn) tfp->dump(contextp->time()); #endif // cocotb controls the clock inputs using cbAfterDelay so // skip ahead to the next registered callback const uint64_t NO_TOP_EVENTS_PENDING = static_cast(~0ULL); const uint64_t next_time_cocotb = VerilatedVpi::cbNextDeadline(); const uint64_t next_time_timing = top->eventsPending() ? top->nextTimeSlot() : NO_TOP_EVENTS_PENDING; const uint64_t next_time = std::min(next_time_cocotb, next_time_timing); // If there are no more cbAfterDelay callbacks, // the next deadline is max value, so end the simulation now if (next_time == NO_TOP_EVENTS_PENDING) { break; } else { contextp->time(next_time); } // Call registered NextSimTime // It should be called in simulation cycle before everything else // but not on first cycle VerilatedVpi::callCbs(cbNextSimTime); settle_value_callbacks(); // Call registered timed callbacks (e.g. clock timer) // These are called at the beginning of the time step // before the iterative regions (IEEE 1800-2012 4.4.1) VerilatedVpi::callTimedCbs(); settle_value_callbacks(); } VerilatedVpi::callCbs(cbEndOfSimulation); top->final(); #if VM_TRACE if (traceOn) tfp->close(); #endif // VM_COVERAGE is a define which is set if Verilator is // instructed to collect coverage (when compiling the simulation) #if VM_COVERAGE VerilatedCov::write("coverage.dat"); #endif return 0; }; verilator-5.042/test_regress/t/t_inside_unpacked_param.py0000755000542200017500000000105515101701376024274 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) if not test.vlt_all: test.execute() test.passes() verilator-5.042/test_regress/t/t_dynarray_cast_write.v0000644000542200017500000000142215101701376023654 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Foo; int x = 1; endclass class Bar extends Foo; function new; x = 2; endfunction endclass module t; initial begin int sel_bit = 3; Bar bar = new; Foo foo = bar; Bar bars[] = new[4]; $cast(bars[0], foo); if (bars[0].x != 2) $stop; $cast(bars[sel_bit[0]], foo); if (bars[1].x != 2) $stop; $cast(bars[bars[0].x], foo); if (bars[2].x != 2) $stop; $cast(bars[sel_bit[1:0]], foo); if (bars[3].x != 2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_vpi_dump_no_inline.py0000755000542200017500000000224715101701376023650 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.pli_filename = "t/t_vpi_dump.cpp" test.golden_filename = "t/t_vpi_dump.out" test.top_filename = "t/t_vpi_dump.v" test.compile(make_top_shell=False, make_main=False, make_pli=True, iv_flags2=["-g2005-sv"], verilator_flags2=[ "--exe --vpi --public-flat-rw --no-l2name --fno-inline", test.pli_filename, "t/TestVpiMain.cpp" ], make_flags=['CPPFLAGS_ADD=-DVL_NO_LEGACY']) test.execute(use_libvpi=True, expect_filename=test.golden_filename, xrun_run_expect_filename=re.sub(r'\.out$', '.xrun.out', test.golden_filename), iv_run_expect_filename=re.sub(r'\.out$', '.iv.out', test.golden_filename)) test.passes() verilator-5.042/test_regress/t/t_param_array9.py0000755000542200017500000000071415101701376022357 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.passes() verilator-5.042/test_regress/t/t_flag_topmodule_bad2.out0000644000542200017500000000027715101701376024041 0ustar mahmoudyfreeshell%Error: Specified --top-module 'notfound' was not found in design. ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_clocking_bad2.py0000755000542200017500000000102515101701376022445 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["--timing"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_constraint_extern_bad.out0000644000542200017500000000112515101701376024520 0ustar mahmoudyfreeshell%Error-PROTOTYPEMIS: t/t_constraint_extern_bad.v:8:22: Definition not found for extern prototype 'missing_bad' 8 | extern constraint missing_bad; | ^~~~~~~~~~~ ... For error description see https://verilator.org/warn/PROTOTYPEMIS?v=latest %Error: t/t_constraint_extern_bad.v:11:20: extern not found that declares 'missing_extern' 11 | constraint Packet::missing_extern { } | ^~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_uniqueif.v0000644000542200017500000000473315101701376021434 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=1; integer a, b, c, d, e, f, g, h, i, j, k, l; always @ (posedge clk) begin cyc <= cyc + 1; //==================== // Positive test cases //==================== // Single if, which is untrue sometimes unique0 if (cyc > 5) a <= 17; // single if with else unique0 if (cyc < 3) b <= 17; else b <= 19; // multi if, some cases may not be true unique0 if (cyc < 3) c <= 17; else if (cyc > 3) c <= 19; // multi if with else, else clause hit in some cases unique0 if (cyc < 3) d <= 17; else if (cyc > 3) d <= 19; else d <= 21; // single if with else unique if (cyc < 3) f <= 17; else f <= 19; // multi if unique if (cyc < 3) g <= 17; else if (cyc >= 3) g <= 19; // multi if with else, else clause hit in some cases unique if (cyc < 3) h <= 17; else if (cyc > 3) h <= 19; else h <= 21; //==================== // Negative test cases //==================== `ifdef FAILING_ASSERTION1 $display("testing fail 1: %d", cyc); // multi if, multiple cases true unique0 if (cyc < 3) i <= 17; else if (cyc < 5) i <= 19; `endif `ifdef FAILING_ASSERTION2 // multi if, multiple cases true unique if (cyc < 3) j <= 17; else if (cyc < 5) j <= 19; `endif `ifdef FAILING_ASSERTION3 // multi if, no cases true unique if (cyc > 1000) k <= 17; else if (cyc > 2000) k <= 19; `endif `ifdef FAILING_ASSERTION4 // Single if, which is untrue sometimes. // The LRM states: "A software tool shall also issue an error if it determines that no condition' // is true, or it is possible that no condition is true, and the final if does not have a // corresponding else." In this case, the final if is the only if, but I think the clause // still applies. unique if (cyc > 5) l <= 17; `endif if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_lint_style_no.py0000755000542200017500000000105115101701376022645 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.top_filename = 't/t_lint_style_bad.v' test.lint(verilator_flags2=["--lint-only -Wwarn-style -Wno-style"]) test.passes() verilator-5.042/test_regress/t/t_opt_localize_max_size_1.py0000755000542200017500000000127715101701376024600 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_opt_localize_max_size.v" test.compile(verilator_flags2=["--stats --localize-max-size 1"]) test.execute() # Value must differ from that in t_opt_localize_max_size.py test.file_grep(test.stats, r'Optimizations, Vars localized\s+(\d+)', 0) test.passes() verilator-5.042/test_regress/t/t_class_virtual.v0000644000542200017500000000416115101701376022455 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 virtual class VBase; virtual function int hello; return 1; endfunction virtual class VNested; virtual function int hello; return 10; endfunction endclass endclass class VA extends VBase; virtual function int hello; return 2; endfunction class VNested extends VBase::VNested; virtual function int hello; return 20; endfunction endclass endclass class VB extends VBase; virtual function int hello; return 3; endfunction class VNested extends VBase::VNested; virtual function int hello; return 30; endfunction endclass endclass virtual class uvm_phase; virtual function int exec_func; return 0; endfunction endclass class uvm_topdown_phase extends uvm_phase; function int get1; return exec_func(); endfunction endclass class uvm_build_phase extends uvm_topdown_phase; virtual function int exec_func; return 1; endfunction endclass virtual class Cls; uvm_phase ph; endclass class ExtendsCls extends Cls; function new; uvm_build_phase bp = new; ph = bp; endfunction function int get1; return super.ph.exec_func(); endfunction endclass module t; initial begin VA va = new; VB vb = new; VA::VNested vna = new; VB::VNested vnb = new; VBase b; VBase::VNested bn; uvm_build_phase ph; ExtendsCls ec; if (va.hello() != 2) $stop; if (vb.hello() != 3) $stop; if (vna.hello() != 20) $stop; if (vnb.hello() != 30) $stop; b = va; bn = vna; if (b.hello() != 2) $stop; if (bn.hello() != 20) $stop; b = vb; bn = vnb; if (b.hello() != 3) $stop; if (bn.hello() != 30) $stop; ph = new; if (ph.get1() != 1) $stop; ec = new; if (ec.get1() != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_var_rsvd_port.v0000644000542200017500000000071615101701376022476 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs bool ); input bool; // BAD reg vector; // OK, as not public reg switch /*verilator public*/; // Bad initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_checker.py0000755000542200017500000000077115101701376021377 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--assert"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_randomize_srandom.v0000644000542200017500000000707615101701376023325 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkeq(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) `define checkne(gotv,expv) do if ((gotv) === (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) class Cls; bit [63:0] m_sum; rand int m_r; function void hash_init(); m_sum = 64'h5aef0c8d_d70a4497; endfunction function void hash(int res); $display(" res %x", res); m_sum = {32'h0, res} ^ {m_sum[62:0], m_sum[63] ^ m_sum[2] ^ m_sum[0]}; endfunction function bit [63:0] test1(); Cls o; // Affected by srandom $display(" init for randomize"); hash_init; // TODO: Support this.randomize() o = this; void'(o.randomize()); hash(m_r); void'(o.randomize()); hash(m_r); return m_sum; endfunction function bit [63:0] test2(int seed); $display(" init for seeded randomize"); hash_init; this.srandom(seed); void'(this.randomize()); hash(m_r); return m_sum; endfunction function bit [63:0] test3(int seed); $display(" init for seeded randomize"); hash_init; srandom(seed); void'(randomize()); hash(m_r); return m_sum; endfunction endclass class Foo; endclass class Bar extends Foo; bit [63:0] m_sum; rand int m_r; function void hash_init(); m_sum = 64'h5aef0c8d_d70a4497; endfunction function void hash(int res); $display(" res %x", res); m_sum = {32'h0, res} ^ {m_sum[62:0], m_sum[63] ^ m_sum[2] ^ m_sum[0]}; endfunction function void this_srandom(int seed); this.srandom(seed); endfunction function bit [63:0] test2; $display(" init for seeded randomize"); hash_init; $display("%d", m_r); hash(m_r); return m_sum; endfunction endclass module t; Cls ca; Cls cb; Bar b1; Bar b2; bit [63:0] sa; bit [63:0] sb; initial begin // Each class gets different seed from same thread, // so the randomization should be different $display("New"); ca = new; cb = new; b1 = new; b2 = new; sa = ca.test1(); sb = cb.test1(); `checkne(sa, sb); // Could false-fail 2^-32 // Seed the classes to be synced $display("Seed"); ca.srandom(123); cb.srandom(123); sa = ca.test1(); sb = cb.test1(); `checkeq(sa, sb); // Check using this $display("this.srandom"); sa = ca.test2(1); sb = cb.test2(2); `checkne(sa, sb); sa = ca.test2(3); sb = cb.test2(3); `checkeq(sa, sb); $display("this.srandom - Bar class"); b1.this_srandom(1); b2.this_srandom(2); void'(b1.randomize()); void'(b2.randomize()); sa = b1.test2; sb = b2.test2; `checkne(sa, sb); b1.this_srandom(3); b2.this_srandom(3); void'(b1.randomize()); void'(b2.randomize()); sa = b1.test2; sb = b2.test2; `checkeq(sa, sb); // Check using direct call $display("srandom"); sa = ca.test3(1); sb = cb.test3(2); `checkne(sa, sb); sa = ca.test3(3); sb = cb.test3(3); `checkeq(sa, sb); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_enum_enumvalue_struct_bad.out0000644000542200017500000000106015101701376025376 0ustar mahmoudyfreeshell%Error-ENUMVALUE: t/t_enum_enumvalue_struct_bad.v:21:33: Implicit conversion to enum 'MEMBERDTYPE 'a'' from 'logic[31:0]' (IEEE 1800-2023 6.19.3) : ... note: In instance 't' : ... Suggest use enum's mnemonic, or static cast 21 | localparam foo_t FOO0 = '{a: 0, b: 1'b1, u: 1'b1}; | ^ ... For error description see https://verilator.org/warn/ENUMVALUE?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_vpi_multidim.v0000644000542200017500000000225215101701376022303 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (/*AUTOARG*/ // Inputs clk ); /*verilator public_module*/ `ifdef VERILATOR `systemc_header extern "C" int mon_check(); `verilog `endif input clk; logic [3:2][5:3] arr_cdata [1:0][2:1]; // 2x3 (6) bit words logic [7:6][12:7] arr_sdata [5:4][6:5]; // 2x6 (12) bit words logic [11:10][25:11] arr_idata [9:8][10:9]; // 2x15 (30) bit words logic [15:14][44:15] arr_qdata [13:12][14:13]; // 2x30 (60) bit words logic [19:18][81:19] arr_wdata [17:16][18:17]; // 2x63 (126) bit words int status; initial begin `ifdef VERILATOR status = $c32("mon_check()"); `else status = $mon_check(); `endif if (status!=0) begin $write("%%Error: t_vpi_multidim.cpp:%0d: C Test failed\n", status); $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule : t verilator-5.042/test_regress/t/t_randomize_param_with.py0000755000542200017500000000104615101701376024172 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_dynarray_method_bad.py0000755000542200017500000000076615101701376023776 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_disable_outside3.py0000755000542200017500000000101315101701376023203 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(timing_loop=True, verilator_flags2=["--timing"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_inst_nansi_mism_bad.py0000755000542200017500000000076615101701376023777 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_noreturn_param.py0000755000542200017500000000103115101701376024043 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.compile(verilator_flags2=['-Wall -Wno-DECLFILENAME -Wno-NORETURN']) test.execute() test.passes() verilator-5.042/test_regress/t/t_var_pins_sc64.py0000755000542200017500000000335315101701376022452 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.pli_filename = "t/t_var_pinsizes.cpp" test.top_filename = "t/t_var_pinsizes.v" test.compile(verilator_flags2=[ "-sc -pins64 --trace-vcd --exe", test.pli_filename, test.t_dir + "/t_var_pinsizes.vlt" ], make_main=False) def hgrep(re): test.file_grep(os.path.join(test.obj_dir, test.vm_prefix + ".h"), re) hgrep(r'sc_core::sc_in\s+&i1;') hgrep(r'sc_core::sc_in\s+&i8;') hgrep(r'sc_core::sc_in\s+&i16;') hgrep(r'sc_core::sc_in\s+&i32;') hgrep(r'sc_core::sc_in\s+&i64;') hgrep(r'sc_core::sc_in\s>\s+&i65;') hgrep(r'sc_core::sc_in\s>\s+&ibv1;') hgrep(r'sc_core::sc_in\s>\s+&ibv16;') hgrep(r'sc_core::sc_in\s>\s+&ibv1_vlt;') hgrep(r'sc_core::sc_in\s>\s+&ibv16_vlt;') hgrep(r'sc_core::sc_out\s+&o1;') hgrep(r'sc_core::sc_out\s+&o8;') hgrep(r'sc_core::sc_out\s+&o16;') hgrep(r'sc_core::sc_out\s+&o32;') hgrep(r'sc_core::sc_out\s+&o64;') hgrep(r'sc_core::sc_out\s>\s+&o65;') hgrep(r'sc_core::sc_out\s>\s+&obv1;') hgrep(r'sc_core::sc_out\s>\s+&obv16;') hgrep(r'sc_core::sc_out\s>\s+&obv1_vlt;') hgrep(r'sc_core::sc_out\s>\s+&obv16_vlt;') test.execute() test.passes() verilator-5.042/test_regress/t/t_param_type_bad.v0000644000542200017500000000046615101701376022555 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; localparam type t = logic; // Fine localparam type bad2 = 2; // Bad endmodule verilator-5.042/test_regress/t/t_dfg_circular.py0000755000542200017500000000075015101701376022414 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["--dumpi-dfg 9"]) test.passes() verilator-5.042/test_regress/t/t_uvm_hello_all_v2017_1_0_nodpi.py0000755000542200017500000000132315101701376025276 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = 't/t_uvm_hello.v' if test.have_dev_gcov: test.skip("Test suite intended for full dev coverage without needing this test") test.compile(v_flags2=[ "--binary", "-j 0", "-Wall", "+incdir+t/uvm", # "t/uvm/uvm_pkg_all_v2017_1_0_nodpi.svh", ]) test.passes() verilator-5.042/test_regress/t/t_assert_inside_cond.py0000755000542200017500000000104215101701376023622 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["-x-assign 0 --assert +define+T_ASSERT_INSIDE_COND"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_inst_missing.py0000755000542200017500000000077715101701376022507 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["--lint-only --Wall -Wno-DECLFILENAME"]) test.passes() verilator-5.042/test_regress/t/t_class_param_pkg.v0000644000542200017500000000534715101701376022737 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); // See also t_class_param_mod.v package Pkg; typedef class Cls; class Wrap #(parameter P = 13); function int get_p; return c1.get_p(); endfunction function new; c1 = new; endfunction Cls#(PMINUS1 + 1) c1; localparam PMINUS1 = P - 1; // Checking works when last endclass class Wrap2 #(parameter P = 35); function int get_p; return c1.get_p(); endfunction function new; c1 = new; endfunction Wrap#(PMINUS1 + 1) c1; localparam PMINUS1 = P - 1; // Checking works when last endclass class Cls #(parameter PBASE = 12); bit [PBASE-1:0] member; function bit [PBASE-1:0] get_member; return member; endfunction static function int get_p; return PBASE; endfunction typedef enum { E_PBASE = PBASE } enum_t; endclass typedef Pkg::Cls#(8) Cls8_t; endpackage module t; Pkg::Cls c12; Pkg::Cls #(.PBASE(4)) c4; Pkg::Cls8_t c8; Pkg::Wrap #(.P(16)) w16; Pkg::Wrap2 #(.P(32)) w32; initial begin c12 = new; c4 = new; c8 = new; w16 = new; w32 = new; if (Pkg::Cls#()::PBASE != 12) $stop; if (Pkg::Cls#(4)::PBASE != 4) $stop; if (Pkg::Cls8_t::PBASE != 8) $stop; if (Pkg::Cls#()::E_PBASE != 12) $stop; if (Pkg::Cls#(4)::E_PBASE != 4) $stop; if (Pkg::Cls8_t::E_PBASE != 8) $stop; if (c12.PBASE != 12) $stop; if (c4.PBASE != 4) $stop; if (c8.PBASE != 8) $stop; if (Pkg::Cls#()::get_p() != 12) $stop; if (Pkg::Cls#(4)::get_p() != 4) $stop; if (Pkg::Cls8_t::get_p() != 8) $stop; if (c12.get_p() != 12) $stop; if (c4.get_p() != 4) $stop; if (c8.get_p() != 8) $stop; if (w16.get_p() != 16) $stop; if (w32.get_p() != 32) $stop; // verilator lint_off WIDTH c12.member = 32'haaaaaaaa; c4.member = 32'haaaaaaaa; c8.member = 32'haaaaaaaa; // verilator lint_on WIDTH if (c12.member != 12'haaa) $stop; if (c4.member != 4'ha) $stop; if (c12.get_member() != 12'haaa) $stop; if (c4.get_member() != 4'ha) $stop; `checkp(c12, "'{member:'haaa}"); `checkp(c4, "'{member:'ha}"); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_let_unsup.v0000644000542200017500000000077215101701376021624 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; let F(untyped a) = 30 + a; let G(int a) = 30 + a; let H(signed a) = 30 + a; initial begin if (F(1) != (30 + 1)) $stop; if (G(1) != (30 + 1)) $stop; if (H(1) != (30 + 1)) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_class_method.py0000755000542200017500000000073415101701376022437 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_vlcov_nfound_bad.out0000644000542200017500000000022515101701376023451 0ustar mahmoudyfreeshell%Error: Can't read coverage file: t/t_NOT_FOUND ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. verilator-5.042/test_regress/t/t_inst_ccall.v0000644000542200017500000000272415101701376021720 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg [31:0] long; reg [63:0] quad; wire [31:0] longout; wire [63:0] quadout; wire [7:0] narrow = long[7:0]; sub sub (/*AUTOINST*/ // Outputs .longout (longout[31:0]), .quadout (quadout[63:0]), // Inputs .narrow (narrow[7:0]), .quad (quad[63:0])); always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin long <= 32'h12345678; quad <= 64'h12345678_abcdef12; end if (cyc==2) begin if (longout !== 32'h79) $stop; if (quadout !== 64'h12345678_abcdef13) $stop; $write("*-* All Finished *-*\n"); $finish; end end end endmodule module sub (input [7:0] narrow, input [63:0] quad, output [31:0] longout, output [63:0] quadout); // verilator public_module `ifdef verilator assign longout = $c32("(", narrow, "+1)"); assign quadout = $c64("(", quad, "+1)"); `else assign longout = narrow + 8'd1; assign quadout = quad + 64'd1; `endif endmodule verilator-5.042/test_regress/t/t_trace_scope_no_inline.v0000644000542200017500000000133515101701376024123 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; integer cyc = 0; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 5) begin $write("*-* All Finished *-*\n"); $finish; end end mid mid_a(clk); mid mid_b(clk); mid mid_c(clk); endmodule module mid(input wire clk); int cnt = 0; always @(posedge clk) cnt += 1; sub sub_a(clk); sub sub_b(clk); sub sub_c(clk); endmodule module sub(input wire clk); int cnt = 0; always @(posedge clk) cnt += 2; endmodule verilator-5.042/test_regress/t/t_var_in_assign_bad.out0000644000542200017500000000111615101701376023571 0ustar mahmoudyfreeshell%Error-ASSIGNIN: t/t_var_in_assign_bad.v:21:16: Assigning to input/const variable: 'valueSub' : ... note: In instance 't.sub' 21 | assign valueSub = 4'h0; | ^~~~~~~~ ... For error description see https://verilator.org/warn/ASSIGNIN?v=latest %Error-ASSIGNIN: t/t_var_in_assign_bad.v:12:16: Assigning to input/const variable: 'value' : ... note: In instance 't' 12 | assign value = 4'h0; | ^~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_cover_unused_bad.py0000755000542200017500000000110315101701376023270 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["-Wall -Wno-DECLFILENAME --coverage"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_unbounded.py0000755000542200017500000000073415101701376021755 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_inside_nonint.py0000755000542200017500000000073415101701376022632 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_multi_bad.out0000644000542200017500000000030615101701376023257 0ustar mahmoudyfreeshell%Error: Only one of --trace-fst, --trace-saif or --trace--vcd may be used ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_cover_sys_unsup.out0000644000542200017500000000334215101701376023412 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_cover_sys_unsup.v:18:9: Unsupported: IEEE 1800-2005 reserved word not implemented: '$coverage_control' 18 | i = $coverage_control(0, 23, 10, t); | ^~~~~~~~~~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_cover_sys_unsup.v:21:9: Unsupported: IEEE 1800-2005 reserved word not implemented: '$coverage_get' 21 | i = $coverage_get(23, 10, t); | ^~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_cover_sys_unsup.v:24:9: Unsupported: IEEE 1800-2005 reserved word not implemented: '$coverage_get_max' 24 | i = $coverage_get_max(23, 10, t); | ^~~~~~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_cover_sys_unsup.v:27:9: Unsupported: IEEE 1800-2005 reserved word not implemented: '$get_coverage' 27 | r = $get_coverage(); | ^~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_cover_sys_unsup.v:29:5: Unsupported: IEEE 1800-2005 reserved word not implemented: '$set_coverage_db_name' 29 | $set_coverage_db_name("filename"); | ^~~~~~~~~~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_cover_sys_unsup.v:31:9: Unsupported: IEEE 1800-2005 reserved word not implemented: '$coverage_save' 31 | i = $coverage_save(coverage_type, "filename"); | ^~~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_cover_sys_unsup.v:34:5: Unsupported: IEEE 1800-2005 reserved word not implemented: '$load_coverage_db' 34 | $load_coverage_db("filename"); | ^~~~~~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_cover_sys_unsup.v:36:9: Unsupported: IEEE 1800-2005 reserved word not implemented: '$coverage_merge' 36 | i = $coverage_merge(coverage_type, "filename"); | ^~~~~~~~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_lint_latch_5.out0000644000542200017500000000157315101701376022515 0ustar mahmoudyfreeshell%Warning-COMBDLY: t/t_lint_latch_5.v:13:13: Non-blocking assignment '<=' in combinational logic process : ... This will be executed as a blocking assignment '='! 13 | z[0] <= a[0]; | ^~ ... For warning description see https://verilator.org/warn/COMBDLY?v=latest ... Use "/* verilator lint_off COMBDLY */" and lint_on around source to disable this message. *** See https://verilator.org/warn/COMBDLY before disabling this, else you may end up with different sim results. %Warning-COMBDLY: t/t_lint_latch_5.v:17:13: Non-blocking assignment '<=' in combinational logic process : ... This will be executed as a blocking assignment '='! 17 | z[1] <= a[1]; | ^~ %Error: Exiting due to verilator-5.042/test_regress/t/t_trace_event.out0000644000542200017500000000144415101701376022444 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module t $end $var event 1 # ev_test $end $var wire 32 $ i [31:0] $end $var wire 1 % toggle $end $var wire 1 & clk $end $upscope $end $enddefinitions $end #0 b00000000000000000000000000000000 $ 0% 0& #10 b00000000000000000000000000000001 $ 1& #20 0& #30 b00000000000000000000000000000010 $ 1& #40 0& #50 b00000000000000000000000000000011 $ 1& #60 0& #70 b00000000000000000000000000000100 $ 1& #80 0& #90 b00000000000000000000000000000101 $ 1& #100 0& #110 1# b00000000000000000000000000000110 $ 1% 1& #120 0& #130 b00000000000000000000000000000111 $ 1& #140 0& #150 b00000000000000000000000000001000 $ 1& #160 0& #170 b00000000000000000000000000001001 $ 1& #180 0& #190 b00000000000000000000000000001010 $ 1& #200 0& #210 1& verilator-5.042/test_regress/t/t_enum_const_methods.v0000644000542200017500000000235015101701376023475 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: constant enum methods // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2022 by Todd Strader // SPDX-License-Identifier: CC0-1.0 module t (); typedef enum [1:0] {E0, E1, E2} enm_t; function automatic enm_t get_first(); enm_t enm; return enm.first; endfunction localparam enm_t enum_first = get_first(); function automatic enm_t get_last(); enm_t enm; return enm.last; endfunction localparam enm_t enum_last = get_last(); function automatic enm_t get_second(); enm_t enm; enm = enm.first; return enm.next; endfunction localparam enm_t enum_second = get_second(); function automatic string get_name(enm_t enm); return enm.name; endfunction localparam string e0_name = get_name(E0); function automatic enm_t get_2(); enm_t enm; enm = E0; return enm.next.next; endfunction localparam enm_t enum_2 = get_2(); initial begin if (enum_first != E0) $stop; if (enum_last != E2) $stop; if (enum_second != E1) $stop; if (e0_name != "E0") $stop; if (enum_2 != E2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_time_vpi_1fs1fs.py0000755000542200017500000000137015101701376022766 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.pli_filename = "t/t_time_vpi_c.cpp" test.top_filename = "t/t_time_vpi.v" test.main_time_multiplier = 1e-15 / 1e-15 test.compile( v_flags2=['+define+time_scale_units=1fs +define+time_scale_prec=1fs', test.pli_filename], verilator_flags2=['--vpi']) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_randomize_method_std.py0000755000542200017500000000073415101701376024174 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_math_eq.v0000644000542200017500000000627215101701376021225 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [3:0] out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .out (out[3:0]), // Inputs .clk (clk), .in (in[31:0])); // Aggregate outputs into a single result vector wire [63:0] result = {60'h0, out}; // What checksum will we end up with `define EXPECTED_SUM 64'h1a0d07009b6a30d2 initial begin `checkh(3'b101 ==? 3'b100, 1'b0); `checkh(3'b101 ==? 3'b101, 1'b1); `checkh(3'b100 ==? 3'b10x, 1'b1); `checkh(3'b101 ==? 3'b10x, 1'b1); `checkh(3'b10x ==? 3'b10?, 1'b1); `checkh(3'b110 ==? 3'b10?, 1'b0); `checkh(3'b111 ==? 3'b10?, 1'b0); `checkh(3'b11x ==? 3'b10?, 1'b0); `checkh(3'b101 !=? 3'b100, !1'b0); `checkh(3'b101 !=? 3'b101, !1'b1); `checkh(3'b100 !=? 3'b10x, !1'b1); `checkh(3'b101 !=? 3'b10x, !1'b1); `checkh(3'b10x !=? 3'b10?, !1'b1); `checkh(3'b110 !=? 3'b10?, !1'b0); `checkh(3'b111 !=? 3'b10?, !1'b0); `checkh(3'b11x !=? 3'b10?, !1'b0); end // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs out, // Inputs clk, in ); input clk; input [31:0] in; output [3:0] out; assign out[0] = in[3:0] ==? 4'b1001; assign out[1] = in[3:0] !=? 4'b1001; assign out[2] = in[3:0] ==? 4'bx01x; assign out[3] = in[3:0] !=? 4'bx01x; wire signed [3:0] ins = in[3:0]; wire signed [3:0] outs; assign outs[0] = ins ==? 4'sb1001; assign outs[1] = ins !=? 4'sb1001; assign outs[2] = ins ==? 4'sbx01x; assign outs[3] = ins !=? 4'sbx01x; always_comb if (out != outs) $stop; endmodule verilator-5.042/test_regress/t/t_timing_localevent.py0000755000542200017500000000077115101701376023476 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_virtual_interface_pkg.py0000755000542200017500000000077115101701376024342 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--binary']) test.execute() test.passes() verilator-5.042/test_regress/t/t_sys_readmem_4state__b.mem.out0000644000542200017500000000001415101701376025146 0ustar mahmoudyfreeshell0 1 1 1 1 1 verilator-5.042/test_regress/t/t_flag_structs_packed_bad.out0000644000542200017500000000057215101701376024763 0ustar mahmoudyfreeshell%Error: t/t_flag_structs_packed.v:14:19: Unpacked data type 'struct{}x.notpacked_t' in packed struct/union (IEEE 1800-2023 7.2.1) : ... note: In instance 'x' 14 | notpacked_t b; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_assert_unique_case_bad.py0000755000542200017500000000106515101701376024460 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["-x-assign 0 --assert"]) test.execute(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_vlt_match_error_3.py0000755000542200017500000000124515101701376023404 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_vlt_match_error.v" test.lint(verilator_flags2=[ "-DT_VLT_MATCH_ERROR_3 --lint-only -Wall t/t_vlt_match_error.v t/t_vlt_match_error.vlt" ], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_jumps_do_while.v0000644000542200017500000000631115101701376022611 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ clk ); input clk; function automatic bit test_1; int iterations = 0; do begin iterations++; break; end while (1); return iterations == 1; endfunction function automatic bit test_2; int iterations = 0; do begin break; iterations++; end while (1); return iterations == 0; endfunction function bit test_3; do break; while (1); return 1'b1; endfunction function automatic bit test_4; int incr = 0; do begin incr++; break; incr++; end while (1); return incr == 1; endfunction function automatic bit test_5; int incr = 0; do begin do incr++; while (incr < 9); incr++; break; incr++; end while (1); return incr == 10; endfunction function automatic bit test_6; int incr = 0; do begin do begin incr += 1; incr += 2; end while (incr < 9); incr++; break; incr++; end while (1); return incr == 10; endfunction function automatic bit test_7; int incr = 0; do begin do begin incr += 1; break; incr += 2; end while (incr < 9); incr++; break; incr++; end while (1); return incr == 2; endfunction function automatic bit test_8; int incr = 0; do begin incr++; continue; incr++; end while (0); return incr == 1; endfunction function automatic bit test_9; int incr = 0; do begin incr++; continue; incr++; end while (incr < 5); return incr == 5; endfunction function automatic bit test_10; do begin continue; end while (0); return 1'b1; endfunction function automatic bit test_11; int incr = 0; do begin do incr++; while (0); incr++; continue; incr++; end while (incr < 11); return incr == 12; endfunction function automatic bit test_12; int incr = 0; do begin do begin incr++; continue; incr++; end while (0); incr++; continue; incr++; end while (incr < 11); return incr == 12; endfunction always @(posedge clk) begin bit [11:0] results; results = {test_1(), test_2(), test_3(), test_4(), test_5(), test_6(), test_7(), test_8(), test_9(), test_10(), test_11(), test_12()}; if (results == '1) begin $write("*-* All Finished *-*\n"); $finish; end else begin $write("Results: %b\n", results); $stop; end end endmodule verilator-5.042/test_regress/t/t_clocking_sched.v0000644000542200017500000000347215101701376022545 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; int cyc = 0; always @(negedge clk) begin // negedge so there is nothing after $finish cyc <= cyc + 1; if (cyc == 2) begin $write("*-* All Finished *-*\n"); $finish; end end logic genclk = 0, a = 0, b = 1, c = 0, x = 0, y, z = 0; always @(edge clk) genclk = clk; always @(posedge genclk) $display("%0t | posedge", $time); // Clocking block clocking cb @(posedge genclk); input #0 a, y; input #1step b; output #0 x; `ifdef VERILATOR_TIMING output #2 z; `endif endclocking // Print after Observed always @(posedge genclk) a = ~a; always @cb $display("%0t | cb.a=%b", $time, cb.a); always @cb $display("%0t | cb.b=%b", $time, cb.b); always @cb.y $display("%0t | cb.y=%b", $time, cb.y); // Retrigger everything after Observed always @cb.a b = x; always @b begin $display("%0t | b=%b", $time, b); if (b == 0) genclk = ~genclk; end // Do an NBA always @(posedge genclk) c <= ~c; always @c begin $display("%0t | c<=%b", $time, c); end // Print after Re-NBA always @(posedge genclk) cb.x <= ~x; always @x $display("%0t | x<=%b", $time, x); // Retrigger everything after Re-NBA always @x y = x; always @y begin $display("%0t | y=%b", $time, y); if (y == 1) genclk = ~genclk; end `ifdef VERILATOR_TIMING // Print after delay and Re-NBA always @(posedge genclk) cb.z <= ~z; always @z $display("%0t | z<=%b", $time, z); `endif // Print in Postponed always @(posedge genclk) $strobe("%0t | %b %b %b %b %b %b", $time, a, b, c, x, y, z); endmodule; verilator-5.042/test_regress/t/t_vpi_var.cpp0000644000542200017500000010020415101701376021560 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #ifdef IS_VPI #include "sv_vpi_user.h" #else #include "verilated.h" #include "verilated_vcd_c.h" #include "verilated_vpi.h" #ifdef T_VPI_VAR2 #include "Vt_vpi_var2.h" #include "Vt_vpi_var2__Dpi.h" #elif defined(T_VPI_VAR3) #include "Vt_vpi_var3.h" #include "Vt_vpi_var3__Dpi.h" #else #include "Vt_vpi_var.h" #include "Vt_vpi_var__Dpi.h" #endif #include "svdpi.h" #endif #ifdef VERILATOR #include "verilated.h" #endif #include #include #include #include #include extern "C" { #include } // These require the above. Comment prevents clang-format moving them #include "TestCheck.h" #include "TestSimulator.h" #include "TestVpi.h" int errors = 0; #define TEST_MSG \ if (0) printf unsigned int main_time = 0; unsigned int callback_count = 0; unsigned int callback_count_half = 0; unsigned int callback_count_quad = 0; unsigned int callback_count_strs = 0; unsigned int callback_count_strs_max = 500; //====================================================================== // We cannot replace those with VL_STRINGIFY, not available when PLI is build #define STRINGIFY(x) STRINGIFY2(x) #define STRINGIFY2(x) #x int _mon_check_mcd() { PLI_INT32 status; PLI_UINT32 mcd; PLI_BYTE8* filename = (PLI_BYTE8*)(STRINGIFY(TEST_OBJ_DIR) "/mcd_open.tmp"); mcd = vpi_mcd_open(filename); CHECK_RESULT_NZ(mcd); { // Check it got written FILE* fp = fopen(filename, "r"); CHECK_RESULT_NZ(fp); fclose(fp); } status = vpi_mcd_printf(mcd, (PLI_BYTE8*)"hello %s", "vpi_mcd_printf"); CHECK_RESULT(status, std::strlen("hello vpi_mcd_printf")); status = vpi_mcd_printf(0, (PLI_BYTE8*)"empty"); CHECK_RESULT(status, 0); status = vpi_mcd_flush(mcd); CHECK_RESULT(status, 0); status = vpi_mcd_flush(0); CHECK_RESULT(status, 1); status = vpi_mcd_close(mcd); // Icarus says 'error' on ones we're not using, so check only used ones return 0. CHECK_RESULT(status & mcd, 0); status = vpi_flush(); CHECK_RESULT(status, 0); return 0; } int _mon_check_callbacks_error(p_cb_data cb_data) { vpi_printf((PLI_BYTE8*)"%%Error: callback should not be executed\n"); return 1; } int _mon_check_callbacks() { t_cb_data cb_data; cb_data.reason = cbEndOfSimulation; cb_data.cb_rtn = _mon_check_callbacks_error; cb_data.user_data = 0; cb_data.value = NULL; cb_data.time = NULL; TestVpiHandle vh = vpi_register_cb(&cb_data); CHECK_RESULT_NZ(vh); PLI_INT32 status = vpi_remove_cb(vh); vh.freed(); CHECK_RESULT_NZ(status); return 0; } int _value_callback(p_cb_data cb_data) { if (verbose) vpi_printf(const_cast(" _value_callback:\n")); if (TestSimulator::is_verilator()) { // this check only makes sense in Verilator CHECK_RESULT(cb_data->value->value.integer + 10, main_time); } callback_count++; return 0; } int _value_callback_half(p_cb_data cb_data) { if (TestSimulator::is_verilator()) { // this check only makes sense in Verilator CHECK_RESULT(cb_data->value->value.integer * 2 + 10, main_time); } callback_count_half++; return 0; } int _value_callback_quad(p_cb_data cb_data) { for (int index = 0; index < 2; index++) { CHECK_RESULT_HEX(cb_data->value->value.vector[1].aval, (unsigned long)((index == 2) ? 0x1c77bb9bUL : 0x12819213UL)); CHECK_RESULT_HEX(cb_data->value->value.vector[0].aval, (unsigned long)((index == 2) ? 0x3784ea09UL : 0xabd31a1cUL)); } callback_count_quad++; return 0; } int _value_callback_never(p_cb_data cb_data) { printf("%%Error: callback should never be called\n"); exit(-1); return 0; } int _mon_check_value_callbacks() { s_vpi_value v; v.format = vpiIntVal; t_cb_data cb_data; cb_data.reason = cbValueChange; cb_data.time = NULL; { TestVpiHandle vh1 = VPI_HANDLE("count"); CHECK_RESULT_NZ(vh1); vpi_get_value(vh1, &v); cb_data.value = &v; cb_data.obj = vh1; cb_data.cb_rtn = _value_callback; if (verbose) vpi_printf(const_cast(" vpi_register_cb(_value_callback):\n")); TestVpiHandle callback_h = vpi_register_cb(&cb_data); CHECK_RESULT_NZ(callback_h); } { TestVpiHandle vh1 = VPI_HANDLE("half_count"); CHECK_RESULT_NZ(vh1); cb_data.obj = vh1; cb_data.cb_rtn = _value_callback_half; TestVpiHandle callback_h = vpi_register_cb(&cb_data); CHECK_RESULT_NZ(callback_h); } { TestVpiHandle vh1 = VPI_HANDLE("quads"); CHECK_RESULT_NZ(vh1); v.format = vpiVectorVal; cb_data.obj = vh1; cb_data.cb_rtn = _value_callback_quad; TestVpiHandle callback_h = vpi_register_cb(&cb_data); CHECK_RESULT_NZ(callback_h); } { TestVpiHandle vh1 = VPI_HANDLE("quads"); CHECK_RESULT_NZ(vh1); TestVpiHandle vh2 = vpi_handle_by_index(vh1, 2); CHECK_RESULT_NZ(vh2); cb_data.obj = vh2; cb_data.cb_rtn = _value_callback_quad; TestVpiHandle callback_h = vpi_register_cb(&cb_data); CHECK_RESULT_NZ(callback_h); } { TestVpiHandle vh1 = VPI_HANDLE("some_mem"); CHECK_RESULT_NZ(vh1); TestVpiHandle vh2 = vpi_handle_by_index(vh1, 3); CHECK_RESULT_NZ(vh2); cb_data.obj = vh2; cb_data.cb_rtn = _value_callback_never; TestVpiHandle callback_h = vpi_register_cb(&cb_data); CHECK_RESULT_NZ(callback_h); } return 0; } int _mon_check_too_big() { #ifdef VERILATOR s_vpi_value v; v.format = vpiVectorVal; TestVpiHandle h = VPI_HANDLE("too_big"); CHECK_RESULT_NZ(h); Verilated::fatalOnVpiError(false); vpi_get_value(h, &v); Verilated::fatalOnVpiError(true); s_vpi_error_info info; CHECK_RESULT_NZ(vpi_chk_error(&info)); v.format = vpiStringVal; vpi_get_value(h, &v); CHECK_RESULT_Z(vpi_chk_error(nullptr)); CHECK_RESULT_CSTR_STRIP(v.value.str, "some text"); #endif return 0; } int _mon_check_var() { TestVpiHandle vh1 = VPI_HANDLE("onebit"); CHECK_RESULT_NZ(vh1); TestVpiHandle vh2 = vpi_handle_by_name((PLI_BYTE8*)TestSimulator::top(), NULL); CHECK_RESULT_NZ(vh2); // scope attributes const char* p; p = vpi_get_str(vpiName, vh2); CHECK_RESULT_CSTR(p, "t"); p = vpi_get_str(vpiFullName, vh2); CHECK_RESULT_CSTR(p, TestSimulator::top()); p = vpi_get_str(vpiType, vh2); CHECK_RESULT_CSTR(p, "vpiModule"); TestVpiHandle vh3 = vpi_handle_by_name((PLI_BYTE8*)"onebit", vh2); CHECK_RESULT_NZ(vh3); #ifdef T_VPI_VAR2 // test scoped attributes TestVpiHandle vh_invisible1 = vpi_handle_by_name((PLI_BYTE8*)"invisible1", vh2); CHECK_RESULT_Z(vh_invisible1); TestVpiHandle vh_invisible2 = vpi_handle_by_name((PLI_BYTE8*)"invisible2", vh2); CHECK_RESULT_Z(vh_invisible2); TestVpiHandle vh_visibleParam1 = vpi_handle_by_name((PLI_BYTE8*)"visibleParam1", vh2); CHECK_RESULT_NZ(vh_visibleParam1); TestVpiHandle vh_invisibleParam1 = vpi_handle_by_name((PLI_BYTE8*)"invisibleParam1", vh2); CHECK_RESULT_Z(vh_invisibleParam1); TestVpiHandle vh_visibleParam2 = vpi_handle_by_name((PLI_BYTE8*)"visibleParam2", vh2); CHECK_RESULT_NZ(vh_visibleParam2); #endif // onebit attributes PLI_INT32 d; d = vpi_get(vpiType, vh3); CHECK_RESULT(d, vpiReg); if (TestSimulator::has_get_scalar()) { d = vpi_get(vpiVector, vh3); CHECK_RESULT(d, 0); } p = vpi_get_str(vpiName, vh3); CHECK_RESULT_CSTR(p, "onebit"); p = vpi_get_str(vpiFullName, vh3); CHECK_RESULT_CSTR(p, TestSimulator::rooted("onebit")); p = vpi_get_str(vpiType, vh3); CHECK_RESULT_CSTR(p, "vpiReg"); // array attributes TestVpiHandle vh4 = VPI_HANDLE("fourthreetwoone"); CHECK_RESULT_NZ(vh4); if (TestSimulator::has_get_scalar()) { d = vpi_get(vpiVector, vh4); CHECK_RESULT(d, 1); p = vpi_get_str(vpiType, vh4); CHECK_RESULT_CSTR(p, "vpiRegArray"); } t_vpi_value tmpValue; tmpValue.format = vpiIntVal; { TestVpiHandle vh10 = vpi_handle(vpiLeftRange, vh4); CHECK_RESULT_NZ(vh10); vpi_get_value(vh10, &tmpValue); CHECK_RESULT(tmpValue.value.integer, 4); CHECK_RESULT(vpi_get(vpiType, vh10), vpiConstant); p = vpi_get_str(vpiType, vh10); CHECK_RESULT_CSTR(p, "vpiConstant"); } { TestVpiHandle vh10 = vpi_handle(vpiRightRange, vh4); CHECK_RESULT_NZ(vh10); vpi_get_value(vh10, &tmpValue); CHECK_RESULT(tmpValue.value.integer, 3); p = vpi_get_str(vpiType, vh10); CHECK_RESULT_CSTR(p, "vpiConstant"); } { TestVpiHandle vh10 = vpi_iterate(vpiReg, vh4); CHECK_RESULT_NZ(vh10); p = vpi_get_str(vpiType, vh10); CHECK_RESULT_CSTR(p, "vpiIterator"); TestVpiHandle vh11 = vpi_scan(vh10); CHECK_RESULT_NZ(vh11); p = vpi_get_str(vpiType, vh11); CHECK_RESULT_CSTR(p, "vpiReg"); TestVpiHandle vh12 = vpi_handle(vpiLeftRange, vh11); CHECK_RESULT_NZ(vh12); vpi_get_value(vh12, &tmpValue); CHECK_RESULT(tmpValue.value.integer, 2); p = vpi_get_str(vpiType, vh12); CHECK_RESULT_CSTR(p, "vpiConstant"); TestVpiHandle vh13 = vpi_handle(vpiRightRange, vh11); CHECK_RESULT_NZ(vh13); vpi_get_value(vh13, &tmpValue); CHECK_RESULT(tmpValue.value.integer, 1); p = vpi_get_str(vpiType, vh13); CHECK_RESULT_CSTR(p, "vpiConstant"); } TestVpiHandle vh5 = VPI_HANDLE("quads"); CHECK_RESULT_NZ(vh5); { TestVpiHandle vh10 = vpi_handle(vpiLeftRange, vh5); CHECK_RESULT_NZ(vh10); vpi_get_value(vh10, &tmpValue); CHECK_RESULT(tmpValue.value.integer, 2); p = vpi_get_str(vpiType, vh10); CHECK_RESULT_CSTR(p, "vpiConstant"); } { TestVpiHandle vh10 = vpi_handle(vpiRightRange, vh5); CHECK_RESULT_NZ(vh10); vpi_get_value(vh10, &tmpValue); CHECK_RESULT(tmpValue.value.integer, 3); p = vpi_get_str(vpiType, vh10); CHECK_RESULT_CSTR(p, "vpiConstant"); } TestVpiHandle vh6 = vpi_handle_by_index(vh5, 2); CHECK_RESULT_NZ(vh6); { TestVpiHandle vh10 = vpi_handle(vpiLeftRange, vh6); CHECK_RESULT_NZ(vh10); vpi_get_value(vh10, &tmpValue); CHECK_RESULT(tmpValue.value.integer, 0); p = vpi_get_str(vpiType, vh10); CHECK_RESULT_CSTR(p, "vpiConstant"); } { TestVpiHandle vh10 = vpi_handle(vpiRightRange, vh6); CHECK_RESULT_NZ(vh10); vpi_get_value(vh10, &tmpValue); CHECK_RESULT(tmpValue.value.integer, 61); p = vpi_get_str(vpiType, vh10); CHECK_RESULT_CSTR(p, "vpiConstant"); } // C++ keyword collision { TestVpiHandle vh10 = VPI_HANDLE("nullptr"); CHECK_RESULT_NZ(vh10); vpi_get_value(vh10, &tmpValue); CHECK_RESULT(tmpValue.value.integer, 123); p = vpi_get_str(vpiType, vh10); CHECK_RESULT_CSTR(p, "vpiParameter"); } // non-integer variables tmpValue.format = vpiRealVal; { TestVpiHandle vh101 = VPI_HANDLE("real1"); CHECK_RESULT_NZ(vh101); d = vpi_get(vpiType, vh101); CHECK_RESULT(d, vpiRealVar); vpi_get_value(vh101, &tmpValue); TEST_CHECK_REAL_EQ(tmpValue.value.real, 1.0, 0.0005); p = vpi_get_str(vpiType, vh101); CHECK_RESULT_CSTR(p, "vpiRealVar"); } // string variable tmpValue.format = vpiStringVal; { TestVpiHandle vh101 = VPI_HANDLE("str1"); CHECK_RESULT_NZ(vh101); d = vpi_get(vpiType, vh101); CHECK_RESULT(d, vpiStringVar); vpi_get_value(vh101, &tmpValue); CHECK_RESULT_CSTR(tmpValue.value.str, "hello"); p = vpi_get_str(vpiType, vh101); CHECK_RESULT_CSTR(p, "vpiStringVar"); } return errors; } int _mon_check_varlist() { const char* p; TestVpiHandle vh2 = VPI_HANDLE("sub"); CHECK_RESULT_NZ(vh2); p = vpi_get_str(vpiName, vh2); CHECK_RESULT_CSTR(p, "sub"); if (TestSimulator::is_verilator()) { p = vpi_get_str(vpiDefName, vh2); CHECK_RESULT_CSTR(p, "sub"); } TestVpiHandle vh10 = vpi_iterate(vpiReg, vh2); CHECK_RESULT_NZ(vh10); CHECK_RESULT(vpi_get(vpiType, vh10), vpiIterator); { TestVpiHandle vh11 = vpi_scan(vh10); CHECK_RESULT_NZ(vh11); p = vpi_get_str(vpiFullName, vh11); CHECK_RESULT_CSTR(p, TestSimulator::rooted("sub.subsig1")); } { TestVpiHandle vh12 = vpi_scan(vh10); CHECK_RESULT_NZ(vh12); p = vpi_get_str(vpiFullName, vh12); CHECK_RESULT_CSTR(p, TestSimulator::rooted("sub.subsig2")); } { TestVpiHandle vh13 = vpi_scan(vh10); vh10.freed(); // IEEE 37.2.2 vpi_scan at end does a vpi_release_handle CHECK_RESULT(vh13, 0); } return 0; } void touch_signal() { TestVpiHandle vh1 = VPI_HANDLE("count"); TEST_CHECK_NZ(vh1); s_vpi_value v; v.format = vpiIntVal; s_vpi_time t; t.type = vpiSimTime; t.high = 0; t.low = 0; v.value.integer = 0; vpi_put_value(vh1, &v, &t, vpiNoDelay); } int _mon_check_ports() { #ifdef TEST_VERBOSE printf("-mon_check_ports()\n"); #endif // test writing to input port TestVpiHandle vh1 = VPI_HANDLE("a"); TEST_CHECK_NZ(vh1); PLI_INT32 d; d = vpi_get(vpiType, vh1); if (TestSimulator::is_verilator()) { TEST_CHECK_EQ(d, vpiReg); } else { TEST_CHECK_EQ(d, vpiNet); } const char* portFullName; if (TestSimulator::is_verilator()) { portFullName = "TOP.a"; } else { portFullName = "t.a"; } const char* name = vpi_get_str(vpiFullName, vh1); TEST_CHECK_EQ(strcmp(name, portFullName), 0); std::string handleName1 = name; s_vpi_value v; v.format = vpiIntVal; vpi_get_value(vh1, &v); TEST_CHECK_EQ(v.value.integer, 0); s_vpi_time t; t.type = vpiSimTime; t.high = 0; t.low = 0; v.value.integer = 2; vpi_put_value(vh1, &v, &t, vpiNoDelay); v.value.integer = 100; vpi_get_value(vh1, &v); TEST_CHECK_EQ(v.value.integer, 2); // get handle of toplevel module TestVpiHandle vht = VPI_HANDLE(""); TEST_CHECK_NZ(vht); d = vpi_get(vpiType, vht); TEST_CHECK_EQ(d, vpiModule); TestVpiHandle vhi = vpi_iterate(vpiReg, vht); TEST_CHECK_NZ(vhi); TestVpiHandle vh11; std::string handleName2; while ((vh11 = vpi_scan(vhi))) { const char* fn = vpi_get_str(vpiFullName, vh11); #ifdef TEST_VERBOSE printf(" scanned %s\n", fn); #endif if (0 == strcmp(fn, portFullName)) { handleName2 = fn; break; } } TEST_CHECK_NZ(vh11); // If get zero we never found the variable vhi.release(); TEST_CHECK_EQ(vpi_get(vpiType, vh11), vpiReg); TEST_CHECK_EQ(handleName1, handleName2); return errors; } int _mon_check_getput() { TestVpiHandle vh2 = VPI_HANDLE("onebit"); CHECK_RESULT_NZ(vh2); const char* p = vpi_get_str(vpiFullName, vh2); CHECK_RESULT_CSTR(p, "t.onebit"); s_vpi_value v; v.format = vpiIntVal; vpi_get_value(vh2, &v); CHECK_RESULT(v.value.integer, 0); s_vpi_time t; t.type = vpiSimTime; t.high = 0; t.low = 0; v.value.integer = 0; vpi_put_value(vh2, &v, &t, vpiNoDelay); vpi_get_value(vh2, &v); CHECK_RESULT(v.value.integer, 0); v.value.integer = 1; vpi_put_value(vh2, &v, &t, vpiNoDelay); vpi_get_value(vh2, &v); CHECK_RESULT(v.value.integer, 1); // real TestVpiHandle vh3 = VPI_HANDLE("real1"); CHECK_RESULT_NZ(vh3); v.format = vpiRealVal; vpi_get_value(vh3, &v); TEST_CHECK_REAL_EQ(v.value.real, 1.0, 0.0005); v.value.real = 123456.789; vpi_put_value(vh3, &v, &t, vpiNoDelay); v.value.real = 0.0f; vpi_get_value(vh3, &v); TEST_CHECK_REAL_EQ(v.value.real, 123456.789, 0.0005); // string TestVpiHandle vh4 = VPI_HANDLE("str1"); CHECK_RESULT_NZ(vh4); v.format = vpiStringVal; vpi_get_value(vh4, &v); CHECK_RESULT_CSTR(v.value.str, "hello"); v.value.str = const_cast("something a lot longer than hello"); vpi_put_value(vh4, &v, &t, vpiNoDelay); v.value.str = 0; vpi_get_value(vh4, &v); TEST_CHECK_CSTR(v.value.str, "something a lot longer than hello"); return errors; } int _mon_check_var_long_name() { TestVpiHandle vh2 = VPI_HANDLE( "LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_" "a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND"); CHECK_RESULT_NZ(vh2); const char* p = vpi_get_str(vpiFullName, vh2); CHECK_RESULT_CSTR(p, "t.LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_" "which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_" "long_name_which_will_get_hashed_LONGEND"); return 0; } int _mon_check_getput_iter() { TestVpiHandle vh2 = VPI_HANDLE("sub"); CHECK_RESULT_NZ(vh2); TestVpiHandle vh10 = vpi_iterate(vpiReg, vh2); CHECK_RESULT_NZ(vh10); CHECK_RESULT(vpi_get(vpiType, vh10), vpiIterator); TestVpiHandle vh11; while (1) { vh11 = vpi_scan(vh10); CHECK_RESULT_NZ(vh11); // If get zero we never found the variable const char* p = vpi_get_str(vpiFullName, vh11); #ifdef TEST_VERBOSE printf(" scanned %s\n", p); #endif if (0 == strcmp(p, "t.sub.subsig1")) break; } CHECK_RESULT(vpi_get(vpiType, vh11), vpiReg); s_vpi_time t; t.type = vpiSimTime; t.high = 0; t.low = 0; s_vpi_value v; v.format = vpiIntVal; v.value.integer = 0; vpi_put_value(vh11, &v, &t, vpiNoDelay); vpi_get_value(vh11, &v); CHECK_RESULT(v.value.integer, 0); v.value.integer = 1; vpi_put_value(vh11, &v, &t, vpiNoDelay); vpi_get_value(vh11, &v); CHECK_RESULT(v.value.integer, 1); return 0; } int _mon_check_quad() { TestVpiHandle vh2 = VPI_HANDLE("quads"); CHECK_RESULT_NZ(vh2); s_vpi_value v; t_vpi_vecval vv[2]; bzero(&vv, sizeof(vv)); s_vpi_time t; t.type = vpiSimTime; t.high = 0; t.low = 0; TestVpiHandle vhidx2 = vpi_handle_by_index(vh2, 2); CHECK_RESULT_NZ(vhidx2); TestVpiHandle vhidx3 = vpi_handle_by_index(vh2, 3); CHECK_RESULT_NZ(vhidx3); // Packed words should be indexable TestVpiHandle vhidx3idx0 = vpi_handle_by_index(vhidx3, 0); CHECK_RESULT_NZ(vhidx3idx0); TestVpiHandle vhidx2idx2 = vpi_handle_by_index(vhidx2, 2); CHECK_RESULT_NZ(vhidx2idx2); TestVpiHandle vhidx3idx3 = vpi_handle_by_index(vhidx3, 3); CHECK_RESULT_NZ(vhidx3idx3); TestVpiHandle vhidx2idx61 = vpi_handle_by_index(vhidx2, 61); CHECK_RESULT_NZ(vhidx2idx61); v.format = vpiVectorVal; v.value.vector = vv; v.value.vector[1].aval = 0x12819213UL; v.value.vector[0].aval = 0xabd31a1cUL; vpi_put_value(vhidx2, &v, &t, vpiNoDelay); v.format = vpiVectorVal; v.value.vector = vv; v.value.vector[1].aval = 0x1c77bb9bUL; v.value.vector[0].aval = 0x3784ea09UL; vpi_put_value(vhidx3, &v, &t, vpiNoDelay); vpi_get_value(vhidx2, &v); CHECK_RESULT(v.value.vector[1].aval, 0x12819213UL); CHECK_RESULT(v.value.vector[1].bval, 0); vpi_get_value(vhidx3, &v); CHECK_RESULT(v.value.vector[1].aval, 0x1c77bb9bUL); CHECK_RESULT(v.value.vector[1].bval, 0); return 0; } int _mon_check_delayed() { TestVpiHandle vh = VPI_HANDLE("delayed"); CHECK_RESULT_NZ(vh); s_vpi_time t; t.type = vpiSimTime; t.high = 0; t.low = 0; s_vpi_value v; v.format = vpiIntVal; v.value.integer = 123; vpi_put_value(vh, &v, &t, vpiInertialDelay); CHECK_RESULT_Z(vpi_chk_error(nullptr)); vpi_get_value(vh, &v); CHECK_RESULT(v.value.integer, 0); TestVpiHandle vhMem = VPI_HANDLE("delayed_mem"); CHECK_RESULT_NZ(vhMem); TestVpiHandle vhMemWord = vpi_handle_by_index(vhMem, 7); CHECK_RESULT_NZ(vhMemWord); v.value.integer = 456; vpi_put_value(vhMemWord, &v, &t, vpiInertialDelay); CHECK_RESULT_Z(vpi_chk_error(nullptr)); // test unsupported vpiInertialDelay cases // - should these also throw vpi errors? v.format = vpiStringVal; v.value.str = nullptr; vpi_put_value(vh, &v, &t, vpiInertialDelay); CHECK_RESULT_NZ(vpi_chk_error(nullptr)); v.format = vpiVectorVal; v.value.vector = nullptr; vpi_put_value(vh, &v, &t, vpiInertialDelay); CHECK_RESULT_NZ(vpi_chk_error(nullptr)); // This format throws an error now Verilated::fatalOnVpiError(false); v.format = vpiObjTypeVal; vpi_put_value(vh, &v, &t, vpiInertialDelay); Verilated::fatalOnVpiError(true); return 0; } int _mon_check_string() { static struct { const char* name; const char* initial; const char* value; } text_test_obs[] = { {"text_byte", "B", "xxA"}, // x's dropped {"text_half", "Hf", "xxT2"}, // x's dropped {"text_word", "Word", "Tree"}, {"text_long", "Long64b", "44Four44"}, {"text", "Verilog Test module", "lorem ipsum"}, }; for (int i = 0; i < 5; i++) { TestVpiHandle vh1 = VPI_HANDLE(text_test_obs[i].name); CHECK_RESULT_NZ(vh1); s_vpi_value v; s_vpi_time t = {vpiSimTime, 0, 0, 0.0}; s_vpi_error_info e; v.format = vpiStringVal; vpi_get_value(vh1, &v); if (vpi_chk_error(&e)) printf("%%vpi_chk_error : %s\n", e.message); (void)vpi_chk_error(NULL); CHECK_RESULT_CSTR_STRIP(v.value.str, text_test_obs[i].initial); v.value.str = (PLI_BYTE8*)text_test_obs[i].value; vpi_put_value(vh1, &v, &t, vpiNoDelay); } return 0; } int _mon_check_putget_str(p_cb_data cb_data) { static TestVpiHandle cb; static struct { TestVpiHandle scope, sig, rfr, check, verbose; std::string str; int type; // value type in .str union { PLI_INT32 integer; s_vpi_vecval vector[4]; } value; // reference } data[129]; if (cb_data) { if (verbose) vpi_printf(const_cast(" _mon_check_putget_str callback:\n")); // this is the callback static unsigned int seed = 1; s_vpi_time t; t.type = vpiSimTime; t.high = 0; t.low = 0; for (int i = 2; i <= 6; i++) { static s_vpi_value v; int words = (i + 31) >> 5; TEST_MSG("========== %d ==========\n", i); if (callback_count_strs) { // check persistence if (data[i].type) { v.format = data[i].type; } else { static PLI_INT32 vals[] = {vpiBinStrVal, vpiOctStrVal, vpiHexStrVal, vpiDecStrVal}; v.format = vals[rand_r(&seed) % ((words > 2) ? 3 : 4)]; TEST_MSG("new format %d\n", v.format); } vpi_get_value(data[i].sig, &v); TEST_MSG("%s\n", v.value.str); if (data[i].type) { CHECK_RESULT_CSTR(v.value.str, data[i].str.c_str()); } else { data[i].type = v.format; data[i].str = std::string{v.value.str}; } } // check for corruption v.format = (words == 1) ? vpiIntVal : vpiVectorVal; vpi_get_value(data[i].sig, &v); if (v.format == vpiIntVal) { TEST_MSG("%08x %08x\n", v.value.integer, data[i].value.integer); CHECK_RESULT(v.value.integer, data[i].value.integer); } else { for (int k = 0; k < words; k++) { TEST_MSG("%d %08x %08x\n", k, v.value.vector[k].aval, data[i].value.vector[k].aval); CHECK_RESULT_HEX(v.value.vector[k].aval, data[i].value.vector[k].aval); } } if (callback_count_strs & 7) { // put same value back - checking encoding/decoding equivalent v.format = data[i].type; v.value.str = (PLI_BYTE8*)(data[i].str.c_str()); // Can't reinterpret_cast vpi_put_value(data[i].sig, &v, &t, vpiNoDelay); v.format = vpiIntVal; v.value.integer = 1; // vpi_put_value(data[i].verbose, &v, &t, vpiNoDelay); vpi_put_value(data[i].check, &v, &t, vpiNoDelay); } else { // stick a new random value in unsigned int mask = ((i & 31) ? (1 << (i & 31)) : 0) - 1; if (words == 1) { v.value.integer = rand_r(&seed); data[i].value.integer = v.value.integer &= mask; v.format = vpiIntVal; TEST_MSG("new value %08x\n", data[i].value.integer); } else { TEST_MSG("new value\n"); for (int j = 0; j < 4; j++) { data[i].value.vector[j].aval = rand_r(&seed); if (j == (words - 1)) data[i].value.vector[j].aval &= mask; TEST_MSG(" %08x\n", data[i].value.vector[j].aval); } v.value.vector = data[i].value.vector; v.format = vpiVectorVal; } vpi_put_value(data[i].sig, &v, &t, vpiNoDelay); vpi_put_value(data[i].rfr, &v, &t, vpiNoDelay); } if ((callback_count_strs & 1) == 0) data[i].type = 0; } if (++callback_count_strs == callback_count_strs_max) { int success = vpi_remove_cb(cb); cb.freed(); CHECK_RESULT_NZ(success); }; } else { // setup and install for (int i = 1; i <= 6; i++) { char buf[32]; VL_SNPRINTF(buf, sizeof(buf), TestSimulator::rooted("arr[%d].arr"), i); CHECK_RESULT_NZ(data[i].scope = vpi_handle_by_name((PLI_BYTE8*)buf, NULL)); CHECK_RESULT_NZ(data[i].sig = vpi_handle_by_name((PLI_BYTE8*)"sig", data[i].scope)); CHECK_RESULT_NZ(data[i].rfr = vpi_handle_by_name((PLI_BYTE8*)"rfr", data[i].scope)); CHECK_RESULT_NZ(data[i].check = vpi_handle_by_name((PLI_BYTE8*)"check", data[i].scope)); CHECK_RESULT_NZ(data[i].verbose = vpi_handle_by_name((PLI_BYTE8*)"verbose", data[i].scope)); } for (int i = 1; i <= 6; i++) { char buf[32]; VL_SNPRINTF(buf, sizeof(buf), TestSimulator::rooted("subs[%d].subsub"), i); CHECK_RESULT_NZ(data[i].scope = vpi_handle_by_name((PLI_BYTE8*)buf, NULL)); } static t_cb_data cb_data; static s_vpi_value v; TestVpiHandle count_h = VPI_HANDLE("count"); cb_data.reason = cbValueChange; cb_data.cb_rtn = _mon_check_putget_str; // this function cb_data.obj = count_h; cb_data.value = &v; cb_data.time = NULL; v.format = vpiIntVal; cb = vpi_register_cb(&cb_data); // It is legal to free the callback handle immediately if not otherwise needed CHECK_RESULT_NZ(cb); } return 0; } int _mon_check_vlog_info() { s_vpi_vlog_info vlog_info; PLI_INT32 rtn = vpi_get_vlog_info(&vlog_info); CHECK_RESULT(rtn, 1); CHECK_RESULT(vlog_info.argc, 4); CHECK_RESULT_CSTR(vlog_info.argv[1], "+PLUS"); CHECK_RESULT_CSTR(vlog_info.argv[2], "+INT=1234"); CHECK_RESULT_CSTR(vlog_info.argv[3], "+STRSTR"); CHECK_RESULT_Z(vlog_info.argv[4]); if (TestSimulator::is_verilator()) { CHECK_RESULT_CSTR(vlog_info.product, "Verilator"); CHECK_RESULT(std::strlen(vlog_info.version) > 0, 1); } return 0; } extern "C" int mon_check() { // Callback from initial block in monitor #ifdef TEST_VERBOSE printf("-mon_check()\n"); #endif if (int status = _mon_check_mcd()) return status; if (int status = _mon_check_callbacks()) return status; if (int status = _mon_check_value_callbacks()) return status; if (int status = _mon_check_var()) return status; if (int status = _mon_check_varlist()) return status; if (int status = _mon_check_var_long_name()) return status; // Ports are not public_flat_rw in t_vpi_var #if defined(T_VPI_VAR2) || defined(T_VPI_VAR3) if (int status = _mon_check_ports()) return status; #endif if (int status = _mon_check_getput()) return status; if (int status = _mon_check_getput_iter()) return status; if (int status = _mon_check_quad()) return status; if (int status = _mon_check_string()) return status; if (int status = _mon_check_putget_str(NULL)) return status; if (int status = _mon_check_vlog_info()) return status; if (int status = _mon_check_delayed()) return status; if (int status = _mon_check_too_big()) return status; #ifndef IS_VPI VerilatedVpi::selfTest(); #endif return 0; // Ok } //====================================================================== #ifdef IS_VPI static int mon_check_vpi() { TestVpiHandle href = vpi_handle(vpiSysTfCall, 0); s_vpi_value vpi_value; vpi_value.format = vpiIntVal; vpi_value.value.integer = mon_check(); vpi_put_value(href, &vpi_value, NULL, vpiNoDelay); return 0; } static s_vpi_systf_data vpi_systf_data[] = {{vpiSysFunc, vpiIntFunc, (PLI_BYTE8*)"$mon_check", (PLI_INT32(*)(PLI_BYTE8*))mon_check_vpi, 0, 0, 0}, 0}; // cver entry void vpi_compat_bootstrap(void) { p_vpi_systf_data systf_data_p; systf_data_p = &(vpi_systf_data[0]); while (systf_data_p->type != 0) vpi_register_systf(systf_data_p++); } // icarus entry void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0}; #else double sc_time_stamp() { return main_time; } int main(int argc, char** argv) { const std::unique_ptr contextp{new VerilatedContext}; uint64_t sim_time = 1100; contextp->debug(0); contextp->commandArgs(argc, argv); const std::unique_ptr topp{new VM_PREFIX{contextp.get(), // Note null name - we're flattening it out ""}}; #ifdef VERILATOR #ifdef TEST_VERBOSE contextp->scopesDump(); #endif #endif #if VM_TRACE contextp->traceEverOn(true); VL_PRINTF("Enabling waves...\n"); VerilatedVcdC* tfp = new VerilatedVcdC; topp->trace(tfp, 99); tfp->open(STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); #endif topp->clk = 0; topp->a = 0; topp->eval(); main_time += 10; while (vl_time_stamp64() < sim_time && !contextp->gotFinish()) { main_time += 1; VerilatedVpi::doInertialPuts(); topp->eval(); VerilatedVpi::callValueCbs(); topp->clk = !topp->clk; // mon_do(); #if VM_TRACE if (tfp) tfp->dump(main_time); #endif } CHECK_RESULT(callback_count, 501); CHECK_RESULT(callback_count_half, 250); CHECK_RESULT(callback_count_quad, 2); CHECK_RESULT(callback_count_strs, callback_count_strs_max); VerilatedVpi::clearEvalNeeded(); if (VerilatedVpi::evalNeeded()) { vl_fatal(FILENM, __LINE__, "main", "%Error: Unexpected VPI dirty state"); } touch_signal(); if (!VerilatedVpi::evalNeeded()) { vl_fatal(FILENM, __LINE__, "main", "%Error: Unexpected VPI clean state"); } if (!contextp->gotFinish()) { vl_fatal(FILENM, __LINE__, "main", "%Error: Timeout; never got a $finish"); } topp->final(); #if VM_TRACE if (tfp) tfp->close(); #endif return 0; } #endif verilator-5.042/test_regress/t/t_concat_unpack.v0000644000542200017500000000172015101701376022410 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; wire [31:0] arr [0:7]; assign arr[0:7] = { {16'hffff, 16'h0000}, {16'h0000, 16'h0000}, {16'h0a0a, 16'h0000}, {16'ha0a0, 16'h0000}, {16'hffff, 16'h0000}, {16'h0000, 16'h0000}, {16'h0a0a, 16'h0000}, {16'ha0a0, 16'h0000} }; int cyc = 0; always @(posedge clk) begin cyc <= cyc + 1; if (cyc == 9) begin if (arr[0] !== 32'hffff0000) $stop; if (arr[7] !== 32'ha0a00000) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_flag_no_unlimited_stack.py0000755000542200017500000000103115101701376024625 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') # Just check whether the flag is recognized. test.lint(verilator_flags2=["--no-unlimited-stack"]) test.passes() verilator-5.042/test_regress/t/t_param_default.py0000755000542200017500000000073415101701376022576 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_timing_unset2.py0000755000542200017500000000112515101701376022554 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_timing_off.v" test.compile( # --timing/--no-timing not specified fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_lint_bad.v0000644000542200017500000000042015101701376022376 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; wire i = 0; not(implicit_out, i); endmodule verilator-5.042/test_regress/t/t_interface_parameter_access.py0000755000542200017500000000073715101701376025316 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_timing_debug1.py0000755000542200017500000000135715101701376022512 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_timing_sched.v" test.compile(verilator_flags2=["--exe --main --timing"]) test.execute(all_run_flags=["+verilator+debug"]) if not test.vltmt: # vltmt output may vary between thread exec order test.files_identical(test.obj_dir + "/vlt_sim.log", test.golden_filename, "logfile") test.passes() verilator-5.042/test_regress/t/t_dist_warn_coverage.py0000755000542200017500000002232415101701376023636 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') Messages = {} Outputs = {} Suppressed = {} for s in [ # Cannot hit, and comment as to why # Instead of adding here, consider adding a LCOV_EXCL_LINE/START/STOP to the sources on the message ' exited with ', # Is hit; driver.py filters out ' loading non-variable', # Instead 'storing to parameter' or syntax error 'Assigned pin is neither input nor output', # Instead earlier error 'Define missing argument \'', # Instead get Define passed too many arguments 'Define or directive not defined: `', # Instead V3ParseImp will warn 'Expecting define formal arguments. Found: ', # Instead define syntax error 'Syntax error: Range \':\', \'+:\' etc are not allowed in the instance ', # Instead get syntax error 'dynamic new() not expected in this context (expected under an assign)', # Instead get syntax error # Not yet analyzed '--pipe-filter protocol error, unexpected: ', '--pipe-filter returned bad status', 'Array initialization has too few elements, need element ', 'Assignment pattern with no members', 'Can\'t find varpin scope of ', 'Can\'t read annotation file: ', 'Can\'t resolve module reference: \'', 'Can\'t write file: ', 'Expected data type, not a ', 'Extern declaration\'s scope is not a defined class', 'File not found: ', 'Format to $display-like function must have constant format string', 'Forward typedef used as class/package does not resolve to class/package: ', 'Illegal +: or -: select; type already selected, or bad dimension: ', 'Illegal bit or array select; type already selected, or bad dimension: ', 'Illegal range select; type already selected, or bad dimension: ', 'Interface port declaration ', 'Modport item is not a function/task: ', 'Modport item is not a variable: ', 'Modport not referenced as .', 'Modport not referenced from underneath an interface: ', 'Non-interface used as an interface: ', 'Parameter type pin value isn\'t a type: Param ', 'Parameter type variable isn\'t a type: Param ', 'Pattern replication value of 0 is not legal.', 'Signals inside functions/tasks cannot be marked forceable', 'Slice size cannot be zero.', 'Slices of arrays in assignments have different unpacked dimensions, ', 'String of ', 'Symbol matching ', 'Unexpected connection to arrayed port', 'Unsized numbers/parameters not allowed in streams.', 'Unsupported RHS tristate construct: ', 'Unsupported or syntax error: Unsized range in instance or other declaration', 'Unsupported pullup/down (weak driver) construct.', 'Unsupported tristate port expression: ', 'Unsupported: $bits for queue', 'Unsupported: &&& expression', 'Unsupported: 4-state numbers in this context', 'Unsupported: Bind with instance list', 'Unsupported: Concatenation to form ', 'Unsupported: Modport dotted port name', 'Unsupported: Modport export with prototype', 'Unsupported: Modport import with prototype', 'Unsupported: Only one PSL clock allowed per assertion', 'Unsupported: Per-bit array instantiations ', 'Unsupported: Public functions with >64 bit outputs; ', 'Unsupported: Replication to form ', 'Unsupported: Size-changing cast on non-basic data type', 'Unsupported: Slice of non-constant bounds', 'Unsupported: Unclocked assertion', 'Unsupported: Verilog 1995 deassign', 'Unsupported: Verilog 1995 gate primitive: ', 'Unsupported: [] dimensions', 'Unsupported: \'default :/\' constraint', 'Unsupported: \'{} .* patterns', 'Unsupported: assertion items in clocking blocks', 'Unsupported: don\'t know how to deal with ', 'Unsupported: extern forkjoin', 'Unsupported: extern task', 'Unsupported: modport export', 'Unsupported: no_inline for tasks', 'Unsupported: property port \'local\'', 'Unsupported: repeat event control', 'Unsupported: static cast to ', 'Unsupported: super', 'Unsupported: with[] stream expression', ]: Suppressed[s] = True def read_messages(): for filename in test.glob_some(test.root + "/src/*"): if not os.path.isfile(filename): continue if '#' in filename: continue with open(filename, 'r', encoding="utf8") as fh: lineno = 0 read_next = None excl = False excl_next = False for origline in fh: line = origline lineno += 1 if re.match(r'^\s*//', line): continue if re.match(r'^\s*/\*', line): continue excl = excl_next if 'LCOV_EXCL_START' in line: excl = True excl_next = True if 'LCOV_EXCL_STOP' in line: excl_next = False # Reenables coverage on next line, not this one if re.search(r'\b(v3error|v3warn|v3fatal|BBUNSUP)\b\($', line): if 'LCOV_EXCL_LINE' not in line: read_next = True continue m = re.search(r'.*\b(v3error|v3warn|v3fatal|BBUNSUP)\b(.*)', line) if m: line = m.group(2) if 'LCOV_EXCL_LINE' not in line: read_next = True if read_next: read_next = False if 'LCOV_EXCL_LINE' in line: continue if excl: continue if "\\" in line: # \" messes up next part continue m = re.search(r'"([^"]*)"', line) if m: msg = m.group(1) fileline = filename + ":" + str(lineno) # print("FFFF " + fileline + ": " + msg + " LL " + line) Messages[msg] = {} Messages[msg]['fileline'] = fileline Messages[msg]['line'] = origline print("Number of messages = " + str(len(Messages))) def read_outputs(): for filename in (test.glob_some(test.root + "/test_regress/t/*.py") + test.glob_some(test.root + "/test_regress/t/*.out") + test.glob_some(test.root + "/docs/gen/*.rst")): if "t_dist_warn_coverage" in filename: # Avoid our own suppressions continue with open(filename, 'r', encoding="latin-1") as fh: for line in fh: if re.match(r'^\$date', line): # Assume it is a VCD file break line = line.lstrip().rstrip() Outputs[line] = True print("Number of outputs = " + str(len(Outputs))) def check(): read_messages() read_outputs() print("Number of suppressions = " + str(len(Suppressed))) print("Coverage = %3.1f%%" % (100 - (100 * len(Suppressed) / len(Messages)))) print() print("Checking for v3error/v3warn messages in sources without") print("coverage in test_regress/t/*.out:") print("(Developers: If a message is impossible to test, consider using") print("UASSERT or v3fatalSrc instead of v3error)") print() used_suppressed = {} for msg in sorted(Messages.keys()): fileline = Messages[msg]['fileline'] next_msg = False for output in Outputs: if msg in output: # print(fileline+": M '" + msg + "' HIT '" + output) next_msg = True break if next_msg: continue # Some exceptions if re.match(r'internal:', msg, re.IGNORECASE): continue line = Messages[msg]['line'] line = line.lstrip().rstrip() if msg in Suppressed: used_suppressed[msg] = True if test.verbose: print(fileline + ": Suppressed check for message in source: '" + msg + "'") else: test.error_keep_going(fileline + ": Missing test_regress/t/*.out test for message in source: '" + msg + "'") if test.verbose: print(" Line is: " + line) print() for msg in sorted(Suppressed.keys()): if msg not in used_suppressed: print("Suppression not used: '" + msg + "'") print() if not os.path.exists(test.root + "/.git"): test.skip("Not in a git repository") check() test.passes() # Local Variables: # compile-command:"./t_dist_warn_coverage.py" # End: verilator-5.042/test_regress/t/t_trace_packed_struct.py0000755000542200017500000000076415101701376024006 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=["--trace-vcd"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_assert_dup_bad.py0000755000542200017500000000076615101701376022756 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_unused_tri.py0000755000542200017500000000077315101701376023204 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME"]) test.passes() verilator-5.042/test_regress/t/t_case_enum_complete_wildcard.v0000644000542200017500000000311515101701376025300 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: SystemVerilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Anthony Donlon. // SPDX-License-Identifier: CC0-1.0 // Fix bug4464 module t; enum logic [1:0] { S00 = 'b00, S01 = 'b01, S10 = 'b10, S0X = 2'b0?, SX0 = 2'b?0 } state; int v = 0; initial begin state = S01; unique case (state) S00: $stop; S01: v++; S10: $stop; endcase unique case (state) S00: $stop; default: v++; // default endcase unique case (state) 2'd0: $stop; 2'd1: v++; 2'd2: $stop; endcase unique case (state) 2'd0: $stop; 2'd1: v++; 2'd2: $stop; 2'd3: $stop; // extra case endcase unique case (state) inside 2'd0: $stop; 2'd1: v++; [2'd2:2'd3]: $stop; endcase unique case (state) inside [S00:S10]: v++; endcase unique casez (state) S10: $stop; S0X: v++; // fully covered endcase unique casez (state) S10: $stop; S0X: v++; 2'b11: $stop; // extra case endcase unique casez (state) S0X: v++; default: $stop; endcase case (state) S00: $stop; S01: v++; S10, 2'b11: $stop; endcase end endmodule verilator-5.042/test_regress/t/t_array_pattern_bad3.py0000755000542200017500000000076615101701376023543 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_vlcov_opt_branch.py0000755000542200017500000000134015101701376023314 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') test.run(cmd=[ os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--write-info", test.obj_dir + "/coverage.info", "--filter-type branch", "t/t_vlcov_data_e.dat" ], verilator_run=True) test.files_identical(test.obj_dir + "/coverage.info", "t/" + test.name + ".info.out") test.passes() verilator-5.042/test_regress/t/t_castdyn_unsup_bad.v0000644000542200017500000000050415101701376023304 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; string q[$]; int aarray[string]; initial begin $cast(q, aarray); end endmodule verilator-5.042/test_regress/t/t_wire_types.v0000644000542200017500000000204415101701376021772 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t (/*AUTOARG*/ // Inputs clk ); input clk; // IEEE: integer_atom_type wire integer w_integer; // IEEE: integer_atom_type wire logic w_logic; wire logic [1:0] w_logic2; assign w_integer = -123456; assign w_logic = 1'b1; assign w_logic2 = 2'b10; always @ (posedge clk) begin `checkh(w_integer, -123456); `checkh(w_logic, 1'b1); `checkh(w_logic2, 2'b10); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_enumeration.v0000644000542200017500000003000515101701376022124 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Iztok Jeras. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cnt = 0; integer mod = 0; // event counter always @ (posedge clk) if (cnt==20) begin cnt <= 0; mod <= mod + 1; end else begin cnt <= cnt + 1; end // finish report always @ (posedge clk) if (mod==3) begin $write("*-* All Finished *-*\n"); $finish; end // anonymous type variable declaration enum logic [2:0] {red=1, orange, yellow, green, blue, indigo, violet} rainbow7; // named type typedef enum logic {OFF, ON} t_switch; t_switch switch; // numbering examples enum integer {father, mother, son[2], daughter, gerbil, dog[3]=10, cat[3:5]=20, car[3:1]=30} family; // test of raibow7 type always @ (posedge clk) if (mod==0) begin // write value to array if (cnt== 0) begin rainbow7 <= rainbow7.first(); // check number if (rainbow7.num() !== 7 ) begin $display("%d", rainbow7.num() ); $stop(); end // if (rainbow7 !== 3'bxxx ) begin $display("%b", rainbow7 ); $stop(); end end else if (cnt== 1) begin if (rainbow7 !== 3'd1 ) begin $display("%b", rainbow7 ); $stop(); end if (rainbow7 !== red ) begin $display("%b", rainbow7 ); $stop(); end rainbow7 <= rainbow7.next(); end else if (cnt== 2) begin if (rainbow7 !== 3'd2 ) begin $display("%b", rainbow7 ); $stop(); end if (rainbow7 !== orange ) begin $display("%b", rainbow7 ); $stop(); end rainbow7 <= rainbow7.next(); end else if (cnt== 3) begin if (rainbow7 !== 3'd3 ) begin $display("%b", rainbow7 ); $stop(); end if (rainbow7 !== yellow ) begin $display("%b", rainbow7 ); $stop(); end rainbow7 <= rainbow7.next(); end else if (cnt== 4) begin if (rainbow7 !== 3'd4 ) begin $display("%b", rainbow7 ); $stop(); end if (rainbow7 !== green ) begin $display("%b", rainbow7 ); $stop(); end rainbow7 <= rainbow7.next(); end else if (cnt== 5) begin if (rainbow7 !== 3'd5 ) begin $display("%b", rainbow7 ); $stop(); end if (rainbow7 !== blue ) begin $display("%b", rainbow7 ); $stop(); end rainbow7 <= rainbow7.next(); end else if (cnt== 6) begin if (rainbow7 !== 3'd6 ) begin $display("%b", rainbow7 ); $stop(); end if (rainbow7 !== indigo ) begin $display("%b", rainbow7 ); $stop(); end rainbow7 <= rainbow7.next(); end else if (cnt== 7) begin if (rainbow7 !== 3'd7 ) begin $display("%b", rainbow7 ); $stop(); end if (rainbow7 !== violet ) begin $display("%b", rainbow7 ); $stop(); end rainbow7 <= rainbow7.next(); end else if (cnt== 8) begin if (rainbow7 !== 3'd1 ) begin $display("%b", rainbow7 ); $stop(); end if (rainbow7 !== red ) begin $display("%b", rainbow7 ); $stop(); end rainbow7 <= rainbow7.next(); end end else if (mod==1) begin // write value to array if (cnt== 0) begin rainbow7 <= rainbow7.last(); // check number if (rainbow7.num() !== 7 ) begin $display("%d", rainbow7.num() ); $stop(); end end else if (cnt== 1) begin if (rainbow7 !== 3'd7 ) begin $display("%b", rainbow7 ); $stop(); end if (rainbow7 !== violet ) begin $display("%b", rainbow7 ); $stop(); end rainbow7 <= rainbow7.prev(); end else if (cnt== 2) begin if (rainbow7 !== 3'd6 ) begin $display("%b", rainbow7 ); $stop(); end if (rainbow7 !== indigo ) begin $display("%b", rainbow7 ); $stop(); end rainbow7 <= rainbow7.prev(); end else if (cnt== 3) begin if (rainbow7 !== 3'd5 ) begin $display("%b", rainbow7 ); $stop(); end if (rainbow7 !== blue ) begin $display("%b", rainbow7 ); $stop(); end rainbow7 <= rainbow7.prev(); end else if (cnt== 4) begin if (rainbow7 !== 3'd4 ) begin $display("%b", rainbow7 ); $stop(); end if (rainbow7 !== green ) begin $display("%b", rainbow7 ); $stop(); end rainbow7 <= rainbow7.prev(); end else if (cnt== 5) begin if (rainbow7 !== 3'd3 ) begin $display("%b", rainbow7 ); $stop(); end if (rainbow7 !== yellow ) begin $display("%b", rainbow7 ); $stop(); end rainbow7 <= rainbow7.prev(); end else if (cnt== 6) begin if (rainbow7 !== 3'd2 ) begin $display("%b", rainbow7 ); $stop(); end if (rainbow7 !== orange ) begin $display("%b", rainbow7 ); $stop(); end rainbow7 <= rainbow7.prev(); end else if (cnt== 7) begin if (rainbow7 !== 3'd1 ) begin $display("%b", rainbow7 ); $stop(); end if (rainbow7 !== red ) begin $display("%b", rainbow7 ); $stop(); end rainbow7 <= rainbow7.prev(); end else if (cnt== 8) begin if (rainbow7 !== 3'd7 ) begin $display("%b", rainbow7 ); $stop(); end if (rainbow7 !== violet ) begin $display("%b", rainbow7 ); $stop(); end rainbow7 <= rainbow7.prev(); end end // test of t_switch type always @ (posedge clk) if (mod==0) begin // write value to array if (cnt== 0) begin switch <= switch.first(); // check number if (switch.num() !== 2 ) begin $display("%d", switch.num() ); $stop(); end // if (switch !== 1'bx) begin $display("%b", switch ); $stop(); end end else if (cnt== 1) begin if (switch !== 1'b0) begin $display("%b", switch ); $stop(); end if (switch !== OFF ) begin $display("%b", switch ); $stop(); end switch <= switch.next(); end else if (cnt== 2) begin if (switch !== 1'b1) begin $display("%b", switch ); $stop(); end if (switch !== ON ) begin $display("%b", switch ); $stop(); end switch <= switch.next(); end else if (cnt== 3) begin if (switch !== 1'b0) begin $display("%b", switch ); $stop(); end if (switch !== OFF ) begin $display("%b", switch ); $stop(); end switch <= switch.next(); end end else if (mod==1) begin // write value to array if (cnt== 0) begin rainbow7 <= rainbow7.last(); // check number if (switch.num() !== 2 ) begin $display("%d", switch.num() ); $stop(); end end else if (cnt== 1) begin if (switch !== 1'b1) begin $display("%b", switch ); $stop(); end if (switch !== ON ) begin $display("%b", switch ); $stop(); end switch <= switch.prev(); end else if (cnt== 2) begin if (switch !== 1'b0) begin $display("%b", switch ); $stop(); end if (switch !== OFF ) begin $display("%b", switch ); $stop(); end switch <= switch.prev(); end else if (cnt== 3) begin if (switch !== 1'b1) begin $display("%b", switch ); $stop(); end if (switch !== ON ) begin $display("%b", switch ); $stop(); end switch <= switch.prev(); end end // test of raibow7 type always @ (posedge clk) if (mod==0) begin // write value to array if (cnt== 0) begin family <= family.first(); // check number if (family.num() !== 15 ) begin $display("%d", family.num() ); $stop(); end // if (family !== 32'dx ) begin $display("%b", family ); $stop(); end end else if (cnt== 1) begin if (family !== 0 ) begin $display("%b", family ); $stop(); end if (family !== father ) begin $display("%b", family ); $stop(); end family <= family.next(); end else if (cnt== 2) begin if (family !== 1 ) begin $display("%b", family ); $stop(); end if (family !== mother ) begin $display("%b", family ); $stop(); end family <= family.next(); end else if (cnt== 3) begin if (family !== 2 ) begin $display("%b", family ); $stop(); end if (family !== son0 ) begin $display("%b", family ); $stop(); end family <= family.next(); end else if (cnt== 4) begin if (family !== 3 ) begin $display("%b", family ); $stop(); end if (family !== son1 ) begin $display("%b", family ); $stop(); end family <= family.next(); end else if (cnt== 5) begin if (family !== 4 ) begin $display("%b", family ); $stop(); end if (family !== daughter ) begin $display("%b", family ); $stop(); end family <= family.next(); end else if (cnt== 6) begin if (family !== 5 ) begin $display("%b", family ); $stop(); end if (family !== gerbil ) begin $display("%b", family ); $stop(); end family <= family.next(); end else if (cnt== 7) begin if (family !== 10 ) begin $display("%b", family ); $stop(); end if (family !== dog0 ) begin $display("%b", family ); $stop(); end family <= family.next(); end else if (cnt== 8) begin if (family !== 11 ) begin $display("%b", family ); $stop(); end if (family !== dog1 ) begin $display("%b", family ); $stop(); end family <= family.next(); end else if (cnt== 9) begin if (family !== 12 ) begin $display("%b", family ); $stop(); end if (family !== dog2 ) begin $display("%b", family ); $stop(); end family <= family.next(); end else if (cnt== 10) begin if (family !== 20 ) begin $display("%b", family ); $stop(); end if (family !== cat3 ) begin $display("%b", family ); $stop(); end family <= family.next(); end else if (cnt== 11) begin if (family !== 21 ) begin $display("%b", family ); $stop(); end if (family !== cat4 ) begin $display("%b", family ); $stop(); end family <= family.next(); end else if (cnt== 12) begin if (family !== 22 ) begin $display("%b", family ); $stop(); end if (family !== cat5 ) begin $display("%b", family ); $stop(); end family <= family.next(); end else if (cnt== 13) begin if (family !== 30 ) begin $display("%b", family ); $stop(); end if (family !== car3 ) begin $display("%b", family ); $stop(); end family <= family.next(); end else if (cnt== 14) begin if (family !== 31 ) begin $display("%b", family ); $stop(); end if (family !== car2 ) begin $display("%b", family ); $stop(); end family <= family.next(); end else if (cnt== 15) begin if (family !== 32 ) begin $display("%b", family ); $stop(); end if (family !== car1 ) begin $display("%b", family ); $stop(); end family <= family.next(); end end endmodule verilator-5.042/test_regress/t/t_pp_line.py0000755000542200017500000000075215101701376021420 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_define_override.v0000644000542200017500000000071215101701376022731 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Multiple `defines while using +define+ // as a command-line argument as well // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define TEST_MACRO 10 `define TEST_MACRO 100 `define STRINGIFY(x) `"x`" module test ( ); initial begin $display("TEST_MACRO %s", `STRINGIFY(`TEST_MACRO)); $finish; end endmodule verilator-5.042/test_regress/t/t_lint_in_inc_bad.out0000644000542200017500000000065315101701376023241 0ustar mahmoudyfreeshell%Error: t/t_lint_in_inc_bad_2.vh:9:7: syntax error, unexpected if, expecting '(' 9 | if if if; | ^~ t/t_lint_in_inc_bad_1.vh:8:1: ... note: In file included from 't_lint_in_inc_bad_1.vh' t/t_lint_in_inc_bad.v:8:1: ... note: In file included from 't_lint_in_inc_bad.v' ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_sys_readmem_bad_digit.py0000755000542200017500000000102415101701376024261 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_sc_names.v0000644000542200017500000000041215101701376021365 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Edgar E. Iglesias. // SPDX-License-Identifier: CC0-1.0 module t ( clk ); input clk; endmodule verilator-5.042/test_regress/t/t_trace_cat_fst.v0000644000542200017500000000063115101701376022401 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( input wire clk ); integer cyc; initial cyc = 0; integer unchanged; initial unchanged = 42; always @ (posedge clk) begin cyc <= cyc + 1; end endmodule verilator-5.042/test_regress/t/t_savable_format3_bad.out0000644000542200017500000000036615101701376024025 0ustar mahmoudyfreeshellModel width = 10 Restoring model from 'obj_vlt/t_savable_format3_bad/saved.vltsv' %Error: obj_vlt/t_savable_format3_bad/saved.vltsv:0: Can't deserialize; file has wrong end-of-file signature: obj_vlt/t_savable_format3_bad/saved.vltsv Aborting... verilator-5.042/test_regress/t/t_typename_min.py0000755000542200017500000000073415101701376022457 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_tri_pull_bad.out0000644000542200017500000000071115101701376022601 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_tri_pull_bad.v:13:13: Unsupported: Conflicting pull directions. : ... note: In instance 't' 13 | pulldown p2(A); | ^~ t/t_tri_pull_bad.v:12:11: ... Location of conflicting pull. 12 | pullup p1(A); | ^~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_struct_unaligned.v0000644000542200017500000000153515101701376023156 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: // Test an error where a shift amount was out of bounds and the compiler treats the // value as undefined (issue #803) // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014 by Jeff Bush. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; struct packed { logic flag; logic [130:0] data; } foo[1]; integer cyc = 0; // Test loop always @ (posedge clk) begin cyc <= cyc + 1; foo[0].data <= 0; foo[0].flag <= !foo[0].flag; if (cyc==10) begin if (foo[0].data != 0) begin $display("bad data value %x", foo[0].data); $stop; end $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_math_eq_noexpand.py0000755000542200017500000000103215101701376023274 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_math_eq.v" test.compile(verilator_flags2=['-fno-expand']) test.execute() test.passes() verilator-5.042/test_regress/t/t_timing_trace.py0000755000542200017500000000112615101701376022433 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary --trace-vcd -Wno-MINTYPMAXDLY"]) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_lint_bad.out0000644000542200017500000000062115101701376022743 0ustar mahmoudyfreeshell%Warning-IMPLICIT: t/t_lint_lint_bad.v:9:7: Signal definition not found, creating implicitly: 'implicit_out' 9 | not(implicit_out, i); | ^~~~~~~~~~~~ ... For warning description see https://verilator.org/warn/IMPLICIT?v=latest ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_dpi_open_vecval.py0000755000542200017500000000111515101701376023121 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=["t/t_dpi_open_vecval_c.cpp"], verilator_flags2=["-Wall -Wno-DECLFILENAME -unroll-count 1"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_gen_genblk_noinl.py0000755000542200017500000000117715101701376023266 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t_gen_genblk.v" test.golden_filename = "t/t_gen_genblk.out" test.sim_time = 11000 test.compile(v_flags2=["-fno-inline"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_vpi_package.py0000755000542200017500000000123015101701376022233 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(make_top_shell=False, make_main=False, make_pli=True, verilator_flags2=["--exe --vpi --no-l2name --public-depth 1", test.pli_filename]) test.execute(use_libvpi=True) test.passes() verilator-5.042/test_regress/t/t_structu_dataType_assignment_bad.v0000644000542200017500000000073015101701376026202 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module for specialized type default values // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Mostafa Gamal. // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off UNPACKED */ module top(); typedef struct { // IEEE 1800-2023 10.9.2 int A; struct { int B, C; } BC1, BC2; } DEF_struct; DEF_struct DEF_bad = '{1: 5, default: 10}; endmodule verilator-5.042/test_regress/t/t_metacmt_onoff.v0000644000542200017500000000100415101701376022414 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; // Test turning on and off a message on the same line; only middle reg shouldn't warn reg [0:1] show1; /*verilator lint_off ASCRANGE*/ reg [0:2] ign2; /*verilator lint_on ASCRANGE*/ reg [0:3] show3; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_dfg_circular_merged_scc.v0000644000542200017500000000117315101701376024401 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 module mul (input [8:0] A, input [16:0] B, output [25:0] Y); assign Y = $signed(A) * $signed(B); endmodule module A; wire [26:0] C; wire [26:0] D; wire [8:0] E; // This yields a circular DFG with a fairly special form that used to trip // decomposition. mul mul ( .A(9'd10), .B(17'h0cccd), .Y({ C[26], C[9:0], D[15:1] }) ); assign E = { C[8:0] }; assign C[25:10] = {16{C[26]}}; endmodule verilator-5.042/test_regress/t/t_extend_c_class.v0000644000542200017500000000245615101701376022565 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [7:0] cyc; initial cyc = 0; reg [31:0] in; wire [31:0] out; t_extend_c_class_v sub (.in(in), .out(out)); always @ (posedge clk) begin cyc <= cyc + 8'd1; if (cyc == 8'd1) begin in <= 32'h10; end if (cyc == 8'd2) begin if (out != 32'h11) $stop; end if (cyc == 8'd9) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module t_extend_c_class_v (/*AUTOARG*/ // Outputs out, // Inputs in ); input [31:0] in; output logic [31:0] out; always @* begin // When "in" changes, call my method out = $c("this->m_myobjp->my_math(", in, ")"); end `systemc_header #include "t_extend_c_class_c.h" // Header for contained object `systemc_interface t_extend_c_class_c* m_myobjp; // Pointer to object we are embedding `systemc_ctor m_myobjp = new t_extend_c_class_c(); // Construct contained object `systemc_dtor delete m_myobjp; // Destruct contained object `verilog endmodule verilator-5.042/test_regress/t/t_trace_complex_saif.py0000755000542200017500000000124015101701376023612 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_complex.v" test.golden_filename = "t/t_trace_complex_saif.out" test.compile(verilator_flags2=['--cc --trace-saif']) test.execute() test.saif_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_program_extern.out0000644000542200017500000000074315101701376023202 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_program_extern.v:7:1: Unsupported: extern program 7 | extern program ex_pgm; | ^~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_program_extern.v:8:1: Unsupported: extern interface 8 | extern interface ex_ifc; | ^~~~~~ %Error-UNSUPPORTED: t/t_program_extern.v:9:1: Unsupported: extern module 9 | extern module ex_mod; | ^~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_preproc_comments.out0000644000542200017500000005540015101701376023525 0ustar mahmoudyfreeshell`line 1 "t/t_preproc.v" 1 // DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2000-2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `line 6 "t/t_preproc.v" 0 // This file intentionally includes some tabs `line 8 "t/t_preproc.v" 0 //=========================================================================== // Includes `line 10 "t/t_preproc.v" 0 `line 1 "t/t_preproc_inc2.vh" 1 // DESCRIPTION: Verilog::Preproc: Example source code `line 2 "t/t_preproc_inc2.vh" 0 // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2000-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 At file "t/t_preproc_inc2.vh" line 5 `line 7 "t/t_preproc_inc2.vh" 0 `line 1 "t/t_preproc_inc3.vh" 1 // DESCRIPTION: Verilog::Preproc: Example source code `line 2 "t/t_preproc_inc3.vh" 0 // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2000-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `line 6 "t/t_preproc_inc3.vh" 0 // FOO At file "t/t_preproc_inc3.vh" line 10 `line 12 "inc3_a_filename_from_line_directive_with_LINE" 0 At file "inc3_a_filename_from_line_directive_with_LINE" line 12 `line 100 "inc3_a_filename_from_line_directive" 0 At file "inc3_a_filename_from_line_directive" line 100 `line 103 "inc3_a_filename_from_line_directive" 0 // guard `line 106 "inc3_a_filename_from_line_directive" 0 `line 110 "inc3_a_filename_from_line_directive" 0 `line 7 "t/t_preproc_inc2.vh" 2 `line 9 "t/t_preproc_inc2.vh" 0 `line 10 "t/t_preproc.v" 2 `line 12 "t/t_preproc.v" 0 //=========================================================================== // Comments `line 15 "t/t_preproc.v" 0 /* verilator pass_thru comment */ `line 17 "t/t_preproc.v" 0 // verilator pass_thru_comment2 `line 19 "t/t_preproc.v" 0 //=========================================================================== // Defines `line 22 "t/t_preproc.v" 0 // DEF_A0 set by command line wire [3:0] q = { 1'b1 , 1'b0 , 1'b1 , 1'b1 }; `line 32 "t/t_preproc.v" 0 text. `line 34 "t/t_preproc.v" 0 foo /*this */ bar /* this too */ foobar2 // but not `line 39 "t/t_preproc.v" 0 `line 43 "t/t_preproc.v" 0 `line 48 "t/t_preproc.v" 0 /*******COMMENT*****/ first part `line 49 "t/t_preproc.v" 0 second part `line 49 "t/t_preproc.v" 0 third part { `line 50 "t/t_preproc.v" 0 a, `line 50 "t/t_preproc.v" 0 b, `line 50 "t/t_preproc.v" 0 c} Line_Preproc_Check 51 `line 53 "t/t_preproc.v" 0 //=========================================================================== `line 55 "t/t_preproc.v" 0 `line 57 "t/t_preproc.v" 0 deep deep `line 61 "t/t_preproc.v" 0 "Inside: `nosubst" "`nosubst" `line 66 "t/t_preproc.v" 0 x y LLZZ x y p q LLZZ p q r s LLZZ r s LLZZ p q LLZZ p q r s LLZZ r s `line 72 "t/t_preproc.v" 0 firstline comma","line LLZZ firstline comma","line `line 74 "t/t_preproc.v" 0 x y LLZZ "a" y // IEEE 1800-2023 clarified that "a" not to substitute `line 77 "t/t_preproc.v" 0 (a,b)(a,b) `line 80 "t/t_preproc.v" 0 $display("left side: \"right side\"") `line 83 "t/t_preproc.v" 0 bar_suffix more `line 86 "t/t_preproc.v" 0 arg suffix_after_space `line 89 "t/t_preproc.v" 0 `line 91 "t/t_preproc.v" 0 $c("Zap(\"",bug1,"\");");; `line 92 "t/t_preproc.v" 0 $c("Zap(\"","bug2","\");");; `line 94 "t/t_preproc.v" 0 /* Define inside comment: `DEEPER and `WITHTICK */ // More commentary: `zap(bug1); `zap("bug2"); `line 97 "t/t_preproc.v" 0 //====================================================================== // display passthru `line 100 "t/t_preproc.v" 0 initial begin //$display(`msg( \`, \`)); // Illegal $display("pre thrupre thrumid thrupost post: \"right side\""); $display("left side: \"right side\""); $display("left side: \"right side\""); $display("left_side: \"right_side\""); $display("na: \"right_side\""); $display("prep ( midp1 left_side midp2 ( outp ) ): \"right_side\""); $display("na: \"nana\""); $display("left_side right_side // Doesn't expand: \"left_side right_side // Doesn't expand\""); // Results vary between simulators $display(": \"\""); // Empty $display("left side: \"right side\""); $display("left side: \"right side\""); $display("standalone"); `line 121 "t/t_preproc.v" 0 // Unspecified when the stringification has multiple lines $display("twoline: \"first second\""); //$display(`msg(left side, \ right side \ )); // Not sure \{space} is legal. $write("*-* All Finished *-*\n"); $finish; end endmodule `line 131 "t/t_preproc.v" 0 //====================================================================== // rt.cpan.org bug34429 `line 134 "t/t_preproc.v" 0 `line 139 "t/t_preproc.v" 0 module add1 ( input wire d1, output wire o1); `line 140 "t/t_preproc.v" 0 wire tmp_d1 = d1; `line 140 "t/t_preproc.v" 0 wire tmp_o1 = tmp_d1 + 1; `line 140 "t/t_preproc.v" 0 assign o1 = tmp_o1 ; // expansion is OK endmodule module add2 ( input wire d2, output wire o2); `line 143 "t/t_preproc.v" 0 wire tmp_d2 = d2; `line 143 "t/t_preproc.v" 0 wire tmp_o2 = tmp_d2 + 1; `line 143 "t/t_preproc.v" 0 assign o2 = tmp_o2 ; // expansion is bad endmodule `line 146 "t/t_preproc.v" 0 `line 152 "t/t_preproc.v" 0 // parameterized macro with arguments that are macros `line 157 "t/t_preproc.v" 0 `line 157 "t/t_preproc.v" 0 generate for (i=0; i<(3); i=i+1) begin `line 157 "t/t_preproc.v" 0 psl cover { m5k.f .ctl._ctl_mvldx_m1.d[i] & ~m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoRise: m5kc_fcl._ctl_mvldx_m1"; `line 157 "t/t_preproc.v" 0 psl cover { ~m5k.f .ctl._ctl_mvldx_m1.d[i] & m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoFall: m5kc_fcl._ctl_mvldx_m1"; `line 157 "t/t_preproc.v" 0 end endgenerate // ignorecmt `line 159 "t/t_preproc.v" 0 //====================================================================== // Quotes are legal in protected blocks. Grr. module prot(); `protected I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl) #nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk] `line 165 "t/t_preproc.v" 0 `endprotected endmodule //" `line 169 "t/t_preproc.v" 0 //====================================================================== // Check IEEE 1800-2017 `pragma protect encrypted modules module t_lint_pragma_protected; `line 173 "t/t_preproc.v" 0 `pragma protect begin_protected `pragma protect version=1 `pragma protect encrypt_agent="XXXXX" `pragma protect encrypt_agent_info="YYYYY" `pragma protect data_method="AES128-CBC" `pragma protect key_keyowner="BIG3#1" `pragma protect key_keyname="AAAAAA" `pragma protect key_method="RSA" `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `pragma protect key_block ICAgICAgICAgICAgICAgICAgIEdOVSBMRVNTRVIgR0VORVJBTCBQVUJMSUMgTElDRU5TRQogICAg KSAyMDA3IE== `line 186 "t/t_preproc.v" 0 `pragma protect key_keyowner="BIG3#2" `pragma protect key_keyname="BBBBBB" `pragma protect key_method="RSA" `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `pragma protect key_block IEV2ZXJ5b25lIGlzIHBlcm1pdHRlZCB0byBjb3B5IGFuZCBkaXN0cmlidXRlIHZlcmJhdGltIGNv cGllcwogb2YgdGhpcyBsaWNlbnNlIGRvY3VtZW50LCBidXQgY2hhbmdpbmcgaXQgaXMgbm90IGFs bG93ZWQuCgoKICBUaGl= `line 195 "t/t_preproc.v" 0 `pragma protect key_keyowner="BIG3#3" `pragma protect key_keyname="CCCCCCCC" `pragma protect key_method="RSA" `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `pragma protect key_block TGljZW5zZSBpbmNvcnBvcmF0ZXMKdGhlIHRlcm1zIGFuZCBjb25kaXRpb25zIG9mIHZlcnNpb24g MyBvZiB0aGUgR05VIEdlbmVyYWwgUHVibGljCkxpY2Vuc2UsIHN1cHBsZW1lbnRlZCBieSB0aGUg YWRkaXRpb25hbCBwZXJ= `line 204 "t/t_preproc.v" 0 `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 295) `pragma protect data_block aW5pdGlvbnMuCgogIEFzIHVzZWQgaGVyZWluLCAidGhpcyBMaWNlbnNlIiByZWZlcnMgdG8gdmVy c2lvbiAzIG9mIHRoZSBHTlUgTGVzc2VyCkdlbmVyYWwgUHVibGljIExpY2Vuc2UsIGFuZCB0aGUg IkdOVSBHUEwiIHJlZmVycyB0byB2ZXJzaW9uIDMgb2YgdGhlIEdOVQpHZW5lcmFsIFB1YmxpYyBM aWNlbnNlLgoKICAiVGhlIExpYnJhcnkiIHJlZmVycyB0byBhIGNvdmVyZWQgd29yayBnb3Zlcm5l ZCBieSB0aGlzIExpY2Vuc2UsCm90aGVyIHRoYW4gYW4gQXBwbGljYXRpb24gb3IgYSBDb21iaW5l ZCBXb3JrIGFzIG== `line 214 "t/t_preproc.v" 0 `pragma protect end_protected `line 216 "t/t_preproc.v" 0 // encoding envelope `pragma protect `pragma protect end `line 220 "t/t_preproc.v" 0 endmodule `line 222 "t/t_preproc.v" 0 //====================================================================== // macro call with define that has comma `line 232 "t/t_preproc.v" 0 begin addr <= (({regs[6], regs[7]} + 1)); rd <= 1; end and begin addr <= (({regs[6], regs[7]})); wdata <= (rdata); wr <= 1; end begin addr <= ({regs[6], regs[7]} + 1); rd <= 1; end begin addr <= ({regs[6], regs[7]}); wdata <= (rdata); wr <= 1; end more `line 236 "t/t_preproc.v" 0 //====================================================================== // include of parameterized file `line 239 "t/t_preproc.v" 0 `line 1 "t/t_preproc_inc4.vh" 1 // DESCRIPTION: Verilog::Preproc: Example source code `line 2 "t/t_preproc_inc4.vh" 0 // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2000-2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `line 6 "t/t_preproc_inc4.vh" 0 `line 8 "t/t_preproc_inc4.vh" 0 `line 239 "t/t_preproc.v" 2 `line 240 "t/t_preproc.v" 0 `line 243 "t/t_preproc.v" 0 `line 245 "t/t_preproc.v" 0 `line 249 "t/t_preproc.v" 0 //====================================================================== // macro call with , in {} `line 252 "t/t_preproc.v" 0 $blah("ab,cd","e,f"); $blah(this.logfile,vec); $blah(this.logfile,vec[1,2,3]); $blah(this.logfile,{blah.name(), " is not foo"}); `line 258 "t/t_preproc.v" 0 //====================================================================== // pragma/default net type `line 261 "t/t_preproc.v" 0 `pragma foo = 1 `default_nettype none `default_nettype uwire `line 265 "t/t_preproc.v" 0 //====================================================================== // Ifdef `line 268 "t/t_preproc.v" 0 `line 272 "t/t_preproc.v" 0 Line_Preproc_Check 272 `line 274 "t/t_preproc.v" 0 //====================================================================== // bug84 `line 277 "t/t_preproc.v" 0 // Hello, comments MIGHT not be legal /*more,,)cmts*/ // But newlines ARE legal... who speced THAT? (p,q) `line 284 "t/t_preproc.v" 0 (//Here x,y //Too) Line_Preproc_Check 285 `line 287 "t/t_preproc.v" 0 //====================================================================== // defines split arguments `line 290 "t/t_preproc.v" 0 beginend // 2001 spec doesn't require two tokens, so "beginend" ok beginend // 2001 spec doesn't require two tokens, so "beginend" ok "beginend" // No space "beginend" `line 298 "t/t_preproc.v" 0 //====================================================================== // bug106 `\esc`def `line 304 "t/t_preproc.v" 0 Not a \`define `line 306 "t/t_preproc.v" 0 //====================================================================== // misparsed comma in submacro x,y)--bee submacro has comma paren `line 314 "t/t_preproc.v" 0 //====================================================================== // bug191 $display("bits %d %d", $bits(foo), 10); `line 319 "t/t_preproc.v" 0 //====================================================================== // 1800-2009 `line 324 "t/t_preproc.v" 0 `line 327 "t/t_preproc.v" 0 //====================================================================== // bug202 `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 assign a3 = ~b3 ; `line 341 "t/t_preproc.v" 0 `line 343 "t/t_preproc.v" 0 /* multi \ line1*/ \ `line 345 "t/t_preproc.v" 0 /*multi \ line2*/ `line 352 "t/t_preproc.v" 0 `line 352 "t/t_preproc.v" 0 `line 352 "t/t_preproc.v" 0 /* multi line 3*/ `line 352 "t/t_preproc.v" 0 def i `line 354 "t/t_preproc.v" 0 //====================================================================== `line 356 "t/t_preproc.v" 0 `line 360 "t/t_preproc.v" 0 `line 366 "t/t_preproc.v" 0 1 // verilator NOT IN DEFINE (nodef) 2 /* verilator PART OF DEFINE */ (hasdef) 3 `line 368 "t/t_preproc.v" 0 /* verilator NOT PART OF DEFINE */ (nodef) `line 369 "t/t_preproc.v" 0 4 `line 369 "t/t_preproc.v" 0 /* verilator PART OF DEFINE */ (nodef) `line 370 "t/t_preproc.v" 0 5 also in `line 370 "t/t_preproc.v" 0 also3 // CMT NOT (nodef) HAS a NEW `line 373 "t/t_preproc.v" 0 LINE `line 375 "t/t_preproc.v" 0 //====================================================================== `line 377 "t/t_preproc.v" 0 `line 390 "t/t_preproc.v" 0 `line 393 "t/t_preproc.v" 0 EXP: clxx_scen clxx_scen EXP: clxx_scen "clxx_scen" EXP: do if (start("verilog/inc1.v", 25)) begin message({"Blah-", "clx_scen", " end"}); end while(0); `line 399 "t/t_preproc.v" 0 do `line 399 "t/t_preproc.v" 0 /* synopsys translate_off */ `line 399 "t/t_preproc.v" 0 `line 399 "t/t_preproc.v" 0 `line 399 "t/t_preproc.v" 0 `line 399 "t/t_preproc.v" 0 if (start("t/t_preproc.v", 399)) begin `line 399 "t/t_preproc.v" 0 `line 399 "t/t_preproc.v" 0 message({"Blah-", "clx_scen", " end"}); `line 399 "t/t_preproc.v" 0 end `line 399 "t/t_preproc.v" 0 /* synopsys translate_on */ `line 399 "t/t_preproc.v" 0 while(0); `line 401 "t/t_preproc.v" 0 //====================================================================== `line 403 "t/t_preproc.v" 0 `line 407 "t/t_preproc.v" 0 `line 407 "t/t_preproc.v" 0 `line 408 "t/t_preproc.v" 0 //`ifndef def_fooed_2 `error "No def_fooed_2" `endif EXP: This is fooed This is fooed EXP: This is fooed_2 This is fooed_2 `line 415 "t/t_preproc.v" 0 //====================================================================== np np //====================================================================== // It's unclear if the spec allows this; is text_macro_idenitfier before or after substitution? `line 426 "t/t_preproc.v" 0 `line 429 "t/t_preproc.v" 0 //====================================================================== // Metaprogramming `line 437 "t/t_preproc.v" 0 `line 441 "t/t_preproc.v" 0 hello3hello3hello3 hello4hello4hello4hello4 //====================================================================== // Include from stringification `line 447 "t/t_preproc.v" 0 `line 1 "t/t_preproc_inc4.vh" 1 // DESCRIPTION: Verilog::Preproc: Example source code `line 2 "t/t_preproc_inc4.vh" 0 // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2000-2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `line 6 "t/t_preproc_inc4.vh" 0 `line 8 "t/t_preproc_inc4.vh" 0 `line 447 "t/t_preproc.v" 2 `line 448 "t/t_preproc.v" 0 //====================================================================== // Defines doing defines // Note the newline on the end - required to form the end of a define `line 456 "t/t_preproc.v" 0 Line_Preproc_Check 460 //====================================================================== // Quoted multiline - track line numbers, and ensure \\n gets propagated Line_Preproc_Check 466 "FOO \ BAR " "arg_line1 \ arg_line2" "FOO \ BAR " `line 469 "t/t_preproc.v" 0 Line_Preproc_Check 469 //====================================================================== // bug283 `line 473 "t/t_preproc.v" 0 // EXP: abc abc `line 483 "t/t_preproc.v" 0 EXP: sonet_frame sonet_frame `line 489 "t/t_preproc.v" 0 EXP: sonet_frame sonet_frame // This result varies between simulators EXP: sonet_frame sonet_frame `line 499 "t/t_preproc.v" 0 // The existance of non-existance of a base define can make a difference EXP: module zzz ; endmodule module zzz ; endmodule module zzz ; endmodule `line 506 "t/t_preproc.v" 0 EXP: module a_b ; endmodule module a_b ; endmodule module a_b ; endmodule `line 511 "t/t_preproc.v" 0 //====================================================================== // bug311 integer/*NEED_SPACE*/ foo; //====================================================================== // bug441 module t; //----- // case provided // note this does NOT escape as suggested in the mail initial begin : \`LEX_CAT(a[0],_assignment) `line 523 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\`LEX_CAT(a[0],_assignment) "); end //----- // SHOULD(simulator-dependant): Backslash doesn't prevent arguments from // substituting and the \ staying in the expansion // Note space after name is important so when substitute it has ending whitespace initial begin : \a[0]_assignment_a[1] `line 530 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\a[0]_assignment_a[1] "); end //----- // RULE: Ignoring backslash does NOT allow an additional expansion level // (Because ESC gets expanded then the \ has it's normal escape meaning) initial begin : \`CAT(pp,suffix) $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(pp,suffix) "); end //----- // Similar to above; \ does not allow expansion after substitution initial begin : \`CAT(ff,bb) `line 544 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(ff,bb) "); end //----- // MUST: Unknown macro with backslash escape stays as escaped symbol name initial begin : \`zzz `line 550 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\`zzz "); end //----- // SHOULD(simulator-dependant): Known macro with backslash escape expands initial begin : \`FOO `line 557 "t/t_preproc.v" 0 $write("GOT%%m='%m' OTHER_EXP='%s'\n OUR_EXP='%s'", "t.bar ","t.\\`FOO "); end // SHOULD(simulator-dependant): Prefix breaks the above initial begin : \xx`FOO `line 559 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\xx`FOO "); end //----- // MUST: Unknown macro not under call with backslash escape doesn't expand initial begin : \`UNKNOWN $write("GOT%%m='%m' EXP='%s'\n", "t.\\`UNKNOWN "); end //----- // MUST: Unknown macro not under call doesn't expand initial begin : \`DEF_NO_EXPAND $write("GOT%%m='%m' EXP='%s'\n", "t.\\`DEF_NO_EXPAND "); end //----- // bug441 derivative // Clarified in IEEE 1800-2023: Quotes prevent arguments from expanding initial $write("GOT='%s' EXP='%s'\n", "foo name baz", "foo bar baz"); //----- // RULE: Because there are quotes after substituting STR, the `A does NOT expand initial $write("GOT='%s' EXP='%s'\n", "foo name baz", "foo `A(bar) baz"); //---- // bug845 initial $write("Slashed=`%s'\n", "1//2.3"); //---- // bug915 initial `line 590 "t/t_preproc.v" 0 $display("%s%s","a1","b2c3\n"); endmodule `line 593 "t/t_preproc.v" 0 //====================================================================== //bug1225 `line 596 "t/t_preproc.v" 0 $display("RAM0"); $display("CPU"); `line 601 "t/t_preproc.v" 0 `line 606 "t/t_preproc.v" 0 XXE_FAMILY = XXE_ $display("XXE_ is defined"); `line 613 "t/t_preproc.v" 0 XYE_FAMILY = XYE_ $display("XYE_ is defined"); `line 620 "t/t_preproc.v" 0 XXS_FAMILY = XXS_some $display("XXS_some is defined"); `line 627 "t/t_preproc.v" 0 XYS_FAMILY = XYS_foo $display("XYS_foo is defined"); `line 634 "t/t_preproc.v" 0 //==== `line 636 "t/t_preproc.v" 0 `line 644 "t/t_preproc.v" 0 `line 651 "t/t_preproc.v" 0 `line 658 "t/t_preproc.v" 0 `line 665 "t/t_preproc.v" 0 `line 667 "t/t_preproc.v" 0 // NEVER `line 669 "t/t_preproc.v" 0 //bug1227 (.mySig (myInterface.pa5), `line 673 "t/t_preproc.v" 0 //====================================================================== // Stringify bug `line 676 "t/t_preproc.v" 0 `dbg_hdl(UVM_LOW, ("Functional coverage enabled: paramgrp")); `line 679 "t/t_preproc.v" 0 `line 687 "t/t_preproc.v" 0 module pcc2_cfg; generate `line 689 "t/t_preproc.v" 0 covergroup a @(posedge b); `line 689 "t/t_preproc.v" 0 c: coverpoint d iff ((c) === 1'b1); endgroup `line 689 "t/t_preproc.v" 0 a u_a; `line 689 "t/t_preproc.v" 0 initial do begin $display ("DEBUG : %s [%m]", $sformatf ("Functional coverage enabled: u_a")); end while(0); endgenerate endmodule `line 693 "t/t_preproc.v" 0 //====================================================================== // Verilog-Perl bug1668 "`NOT_DEFINED_STR" `line 698 "t/t_preproc.v" 0 //====================================================================== """First line with "quoted"\nSecond line\ Third line""" """First line Second line""" `line 705 "t/t_preproc.v" 0 """QQQ defform""" """QQQ defval""" `line 710 "t/t_preproc.v" 0 // string concat bug "string argument" `line 714 "t/t_preproc.v" 0 //====================================================================== // See issue #5094 - IEEE 1800-2023 clarified proper behavior `line 717 "t/t_preproc.v" 0 bar "foo foo foo" bar bar """foo foo foo""" bar `line 722 "t/t_preproc.v" 0 //====================================================================== // IEEE mandated predefines // undefineall should have no effect on these predef 0 0 predef 1 1 predef 2 2 predef 3 3 predef 10 10 predef 11 11 predef 20 20 predef 21 21 predef 22 22 predef 23 23 predef -2 -2 predef -1 -1 predef 0 0 predef 1 1 predef 2 2 //====================================================================== // After `undefineall above, for testing --dump-defines `line 744 "t/t_preproc.v" 0 //====================================================================== // Stringify in nested macro string boo = "test"; string boo = "test x,y x,y"; string boo = "testx,ytest x x,y"; string boo = "testtest x,y xquux(test)"; `line 757 "t/t_preproc.v" 0 //====================================================================== // Define with --preproc-defines needs to keep backslashes `line 760 "t/t_preproc.v" 0 `line 769 "t/t_preproc.v" 0 verilator-5.042/test_regress/t/t_mem_multi_io.v0000644000542200017500000000250715101701376022263 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; logic [7:0] arr [7:0]; logic [7:0] arri [7:0]; has_array am1 (.clk(clk), .arri(arr), .arro(arri)); integer cyc; initial cyc = 0; initial begin for (int i = 0; i < 8; i++) begin arr[i] = 0; arri[i] = 0; end end always @(posedge clk) begin cyc <= cyc + 1; if (cyc == 5 && arri[1] != 8) begin $stop; end if (cyc >= 2) begin for (int i = 0; i < 7; ++i) begin arr[i+1] <= arr[i]; end arr[0] <= arr[0] + 1; end end endmodule : t module has_array ( input clk, input logic [7:0] arri [7:0], output logic [7:0] arro [7:0] ); integer cyc; initial cyc = 0; always @(posedge clk) begin cyc <= cyc + 1; if (cyc == 10) begin if (arri[0] != 8) $stop; $write("*-* All Finished *-*\n"); $finish; end end always @(posedge clk) begin for (integer i = 0; i < 7; ++i) begin arro[i+1] <= arro[i]; end arro[0] = arro[0] + 2; end endmodule : has_array verilator-5.042/test_regress/t/t_mod_dup_ign.v0000644000542200017500000000074215101701376022067 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; sub sub (); endmodule module sub; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule // verilator lint_off MODDUP module sub; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_force_port_inline.v0000644000542200017500000000357315101701376023310 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module sub( input wire [7:0] i, output wire [7:0] o ); // Must inline this module // verilator inline_module wire [7:0] m; assign m = i; assign o = m; endmodule module top; // Variable input reg [7:0] i = 8'h01; reg [7:0] o_v; sub sub_v(i, o_v); // Constant input reg [7:0] o_c; sub sub_c(8'h10, o_c); logic clk = 1'b0; always #1 clk = ~clk; int cyc = 0; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 1) begin `checkh(i, 8'h01); `checkh(sub_v.i, 8'h01); `checkh(sub_v.m, 8'h01); `checkh(sub_v.o, 8'h01); `checkh(o_v, 8'h01); `checkh(sub_c.i, 8'h10); `checkh(sub_c.m, 8'h10); `checkh(sub_c.o, 8'h10); `checkh(o_c, 8'h10); end else if (cyc == 2) begin force sub_v.i = 8'h02; force sub_v.m = 8'h03; force sub_v.o = 8'h04; force sub_c.i = 8'h20; force sub_c.m = 8'h30; force sub_c.o = 8'h40; end else if (cyc == 3) begin `checkh(i, 8'h01); `checkh(sub_v.i, 8'h02); `checkh(sub_v.m, 8'h03); `checkh(sub_v.o, 8'h04); `checkh(o_v, 8'h04); `checkh(sub_c.i, 8'h20); `checkh(sub_c.m, 8'h30); `checkh(sub_c.o, 8'h40); `checkh(o_c, 8'h40); end // else if (cyc == 99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_stream_queue.py0000755000542200017500000000073415101701376022471 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_preproc_resolve.py0000755000542200017500000000162215101701376023200 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') stdout_filename = os.path.join(test.obj_dir, test.name + ".out") test.compile( # Override default flags v_flags=[''], verilator_flags=[ "-E -P --preproc-resolve t/t_preproc_resolve_config.vlt -y t/t_preproc_resolve" ], verilator_flags2=[''], verilator_flags3=[''], verilator_make_gmake=False, make_top_shell=False, make_main=False, stdout_filename=stdout_filename) test.files_identical(stdout_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_infinite.v0000644000542200017500000000126715101701376022441 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; mailbox #(int) mbox; task main(); // See issue #4323; not an INFINITELOOP due to delay inside get() forever begin int i; mbox.get(i); $display("[%0t] Got %0d", $time, i); end endtask initial begin mbox = new (1); #10; fork main(); join_none #10; mbox.put(10); mbox.put(11); #10; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_timing_func_fork_bad.out0000644000542200017500000000460415101701376024277 0ustar mahmoudyfreeshell%Error: t/t_timing_func_fork_bad.v:12:7: Writing to an output variable of a function after a timing control is not allowed : ... note: In instance 't' 12 | f1 = 0; | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_timing_func_fork_bad.v:13:7: Writing to an output variable of a function after a timing control is not allowed : ... note: In instance 't' 13 | o1 = 0; | ^~ %Error: t/t_timing_func_fork_bad.v:19:7: Writing to an output variable of a function after a timing control is not allowed : ... note: In instance 't' 19 | f2 = #5 0; $stop; | ^~ %Error: t/t_timing_func_fork_bad.v:20:7: Writing to an inout variable of a function after a timing control is not allowed : ... note: In instance 't' 20 | io2 = 0; | ^~~ %Error: t/t_timing_func_fork_bad.v:28:7: Writing to an output variable of a function after a timing control is not allowed : ... note: In instance 't' 28 | f3 = 0; | ^~ %Error: t/t_timing_func_fork_bad.v:29:7: Writing to an output variable of a function after a timing control is not allowed : ... note: In instance 't' 29 | o3 = 0; | ^~ %Error: t/t_timing_func_fork_bad.v:35:7: Writing to an output variable of a function after a timing control is not allowed : ... note: In instance 't' 35 | f4 = @e 0; $stop; | ^~ %Error: t/t_timing_func_fork_bad.v:36:7: Writing to an inout variable of a function after a timing control is not allowed : ... note: In instance 't' 36 | io4 = 0; | ^~~ %Error: t/t_timing_func_fork_bad.v:45:7: Writing to an output variable of a function after a timing control is not allowed : ... note: In instance 't' 45 | f5 = 0; | ^~ %Error: t/t_timing_func_fork_bad.v:46:7: Writing to an output variable of a function after a timing control is not allowed : ... note: In instance 't' 46 | o5 = 0; | ^~ %Error: Exiting due to verilator-5.042/test_regress/t/t_math_swap.v0000644000542200017500000001135515101701376021570 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] Operand1 = crc[31:0]; wire [15:0] Operand2 = crc[47:32]; wire Unsigned = crc[48]; reg rst; parameter WL = 16; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [WL-1:0] Quotient; // From test of Test.v wire [WL-1:0] Remainder; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .Quotient (Quotient[WL-1:0]), .Remainder (Remainder[WL-1:0]), // Inputs .Operand1 (Operand1[WL*2-1:0]), .Operand2 (Operand2[WL-1:0]), .clk (clk), .rst (rst), .Unsigned (Unsigned)); // Aggregate outputs into a single result vector wire [63:0] result = {32'h0, Quotient, Remainder}; // What checksum will we end up with `define EXPECTED_SUM 64'h98d41f89a8be5693 // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x it=%x\n", $time, cyc, crc, result, test.Iteration); `endif cyc <= cyc + 1; if (cyc < 20 || test.Iteration==4'd15) begin crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; end sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; rst <= 1'b1; end else if (cyc<20) begin sum <= 64'h0; rst <= 1'b0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'h8dd70a44972ad809) $stop; if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test(clk, rst, Operand1, Operand2, Unsigned, Quotient, Remainder); parameter WL = 16; input [WL*2-1:0] Operand1; input [WL-1:0] Operand2; input clk, rst, Unsigned; output [WL-1:0] Quotient, Remainder; reg Cy, Overflow, Sign1, Sign2, Zero, Negative; reg [WL-1:0] ah,al,Quotient, Remainder; reg [3:0] Iteration; reg [WL-1:0] sub_quot,op; reg ah_ext; reg [1:0] a,b,c,d,e; always @(posedge clk) begin if (!rst) begin {a,b,c,d,e} = Operand1[9:0]; {a,b,c,d,e} = {e,d,c,b,a}; if (a != Operand1[1:0]) $stop; if (b != Operand1[3:2]) $stop; if (c != Operand1[5:4]) $stop; if (d != Operand1[7:6]) $stop; if (e != Operand1[9:8]) $stop; end end always @(posedge clk) begin if (rst) begin Iteration <= 0; Quotient <= 0; Remainder <= 0; end else begin if (Iteration == 0) begin {ah,al} = Operand1; op = Operand2; Cy = 0; Overflow = 0; Sign1 = (~Unsigned)&ah[WL-1]; Sign2 = (~Unsigned)&(ah[WL-1]^op[WL-1]); if (Sign1) {ah,al} = -{ah,al}; end `define BUG1 `ifdef BUG1 {ah_ext,ah,al} = {ah,al,Cy}; `else ah_ext = ah[15]; ah[15:1] = ah[14:0]; ah[0] = al[15]; al[15:1] = al[14:0]; al[0] = Cy; `endif `ifdef TEST_VERBOSE $display("%x %x %x %x %x %x %x %x %x", Iteration, ah, al, Quotient, Remainder, Overflow, ah_ext, sub_quot, Cy); `endif {Cy,sub_quot} = (~Unsigned)&op[WL-1]? {ah_ext,ah}+op : {ah_ext,ah} - {1'b1,op}; if (Cy) begin {ah_ext,ah} = {1'b0,sub_quot}; end if (Iteration != 15 ) begin if (ah_ext) Overflow = 1; end else begin if (al[14] && ~Unsigned) Overflow = 1; Quotient <= Sign2 ? -{al[14:0],Cy} : {al[14:0],Cy}; Remainder <= Sign1 ? -ah : ah; if (Overflow) begin Quotient <= Sign2 ? 16'h8001 : {Unsigned,{15{1'b1}}}; Remainder <= Unsigned ? 16'hffff : 16'h8000; Zero = 1; Negative = 1; end end Iteration <= Iteration + 1; // Count number of times this instruction is repeated end end endmodule verilator-5.042/test_regress/t/t_var_const2.v0000644000542200017500000000136315101701376021663 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; const static int a1; const static int a2 = 0; initial begin const static int c1; const static int c2 = 0; const automatic int d1; const automatic int d2 = 0; end function static void tb_func1(); const static int e1; const static int e2 = 0; const automatic int f1; const automatic int f2 = 0; endfunction function automatic void tb_func2(); const static int g1; const static int g2 = 0; const automatic int h1; const automatic int h2 = 0; endfunction endmodule verilator-5.042/test_regress/t/t_unpacked_to_packed_param.v0000644000542200017500000000157015101701376024566 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Confirm x randomization stability // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; always @(posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end localparam logic [1:0][7:0] foo_unpacked [2:0] = '{"12", "34", "56"}; localparam logic [2:0][1:0][7:0] foo_packed = '{"12", "34", "56"}; sub #( .foos ({foo_unpacked[0], foo_unpacked[1], foo_unpacked[2]}) ) the_unpacked_sub(); sub #( .foos ({foo_packed[0], foo_packed[1], foo_packed[2]}) ) the_packed_sub(); endmodule module sub #( parameter logic [2:0][1:0][7:0] foos ); initial begin if (foos != "563412") $stop; end endmodule verilator-5.042/test_regress/t/t_gen_defparam_bad.py0000755000542200017500000000076315101701376023212 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_hierarchy_identifier.py0000755000542200017500000000073415101701376024152 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_cover_line_cc.py0000755000542200017500000000341115101701376022557 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_cover_line.v" test.golden_filename = "t/t_cover_line.out" test.compile(verilator_flags2=['--cc --coverage-line +define+ATTRIBUTE']) test.execute() test.run(cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--annotate-points", "--annotate", test.obj_dir + "/annotated", test.obj_dir + "/coverage.dat"], verilator_run=True) # yapf:disable test.files_identical(test.obj_dir + "/annotated/t_cover_line.v", test.golden_filename) # Also try lcov test.run(cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--write-info", test.obj_dir + "/coverage.info", test.obj_dir + "/coverage.dat"], verilator_run=True) # yapf:disable test.files_identical(test.obj_dir + "/coverage.info", "t/" + test.name + ".info.out") # If installed nout = test.run_capture("lcov --version", check=False) version_match = re.search(r'version ([0-9.]+)', nout, re.IGNORECASE) if not version_match: test.skip("lcov or genhtml not installed") if float(version_match.group(1)) < 1.14: test.skip("lcov or genhtml too old (version " + version_match.group(1) + ", need version >= 1.14") test.run(cmd=[ "genhtml", test.obj_dir + "/coverage.info", "--branch-coverage", "--output-directory " + test.obj_dir + "/html" ]) test.passes() verilator-5.042/test_regress/t/t_preproc_eof4_bad.v0000644000542200017500000000033415101701376022775 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 "blah verilator-5.042/test_regress/t/t_strength_strongest_non_tristate.py0000755000542200017500000000073415101701376026531 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_enum_name_sformatf.py0000755000542200017500000000073415101701376023637 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_sdf_annotate_unsup.out0000644000542200017500000000162315101701376024043 0ustar mahmoudyfreeshell%Warning-SPECIFYIGN: t/t_sdf_annotate_unsup.v:10:5: Ignoring unsupported: $sdf_annotate 10 | $sdf_annotate("file.sdf"); | ^~~~~~~~~~~~~ ... For warning description see https://verilator.org/warn/SPECIFYIGN?v=latest ... Use "/* verilator lint_off SPECIFYIGN */" and lint_on around source to disable this message. %Warning-SPECIFYIGN: t/t_sdf_annotate_unsup.v:11:5: Ignoring unsupported: $sdf_annotate 11 | $sdf_annotate("file.sdf",); | ^~~~~~~~~~~~~ %Warning-SPECIFYIGN: t/t_sdf_annotate_unsup.v:12:5: Ignoring unsupported: $sdf_annotate 12 | $sdf_annotate("file.sdf", t); | ^~~~~~~~~~~~~ %Warning-SPECIFYIGN: t/t_sdf_annotate_unsup.v:14:5: Ignoring unsupported: $sdf_annotate 14 | $sdf_annotate("file.sdf", t, "config_file", "log_file", "mtm_spec", "scale_factors", | ^~~~~~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_package_verb.v0000644000542200017500000000101215101701376022203 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // bug474 package verb_pkg; typedef enum int {VERB_I, VERB_W} Verb_t; Verb_t verb = VERB_I; string message = " "; endpackage module t; import verb_pkg::*; string message = "*x*"; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_interface_generic_modport_bad.v0000644000542200017500000000101515101701376025603 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 interface inf; int v; endinterface module GenericModule (interface.mp a); initial begin #1; if (a.v != 7) $stop; end endmodule module t; inf inf_inst(); GenericModule genericModule (inf_inst); initial begin inf_inst.v = 7; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_bigmem_bad.py0000755000542200017500000000076615101701376022045 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_param_nested_bad.py0000755000542200017500000000076615101701376024434 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_hier_block_binary.py0000755000542200017500000000236115101701376023435 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_hier_block.v" # stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. test.clean_objs() test.compile(verilator_flags2=[ 't/t_hier_block.cpp', '--stats', '--hierarchical', '--Wno-TIMESCALEMOD', '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"', '--binary' ]) test.execute() test.file_grep(test.obj_dir + "/Vsub0/sub0.sv", r'^\s+\/\/\s+timeprecision\s+(\d+)ps;', 1) test.file_grep(test.obj_dir + "/Vsub0/sub0.sv", r'^module\s+(\S+)\s+', "sub0") test.file_grep(test.obj_dir + "/Vsub1/sub1.sv", r'^module\s+(\S+)\s+', "sub1") test.file_grep(test.obj_dir + "/Vsub2/sub2.sv", r'^module\s+(\S+)\s+', "sub2") test.file_grep(test.stats, r'HierBlock,\s+Hierarchical blocks\s+(\d+)', 14) test.file_grep(test.run_log_filename, r'MACRO:(\S+) is defined', "cplusplus") test.passes() verilator-5.042/test_regress/t/t_flag_invalid_bad.py0000755000542200017500000000103015101701376023205 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, verilator_flags2=['--invalid-dash'], expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_assert_always_unsup.v0000644000542200017500000000151215101701376023712 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022-2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ clk ); input clk; int cyc = 0; logic val = 0; always @(posedge clk) begin cyc <= cyc + 1; val = ~val; end property p_alw; always [2:5] a; endproperty property p_s_alw; s_always [2:5] a; endproperty property p_ev; eventually [2:5] a; endproperty property p_evc; eventually [2] a; endproperty property p_s_ev; s_eventually [2:5] a; endproperty property p_s_alw_ev; always s_eventually [2:5] a; endproperty property p_s_ev_alw; s_eventually always [2:5] a; endproperty endmodule verilator-5.042/test_regress/t/t_sys_queue_unsup.py0000755000542200017500000000077315101701376023251 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_func_modify_input.v0000644000542200017500000000053515101701376023324 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class foo; function void g(input integer x); f(x); endfunction function void f(inout integer x); endfunction endclass verilator-5.042/test_regress/t/t_timescale_default.py0000755000542200017500000000100015101701376023427 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_const_func_gen_bad.py0000755000542200017500000000076315101701376024622 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_event.py0000755000542200017500000000073415101701376021113 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_implements_contents_bad.py0000755000542200017500000000076615101701376024677 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_delay_incr.v0000644000542200017500000000077215101701376021717 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `timescale 100ns/1ns module t; int ia; int ib; initial begin ia = 0; #1 ib = ++ia; #1 if (ia !== ib) $stop; #1 ib = ia++; #1 if (ia == ib) $stop; #10; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_unconnected.v0000644000542200017500000000166215101701376022112 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; wire o_n; wire o_0; wire o_1; // verilator lint_off PINMISSING sub_0 sub_0(.o_0); sub_1 sub_1(.o_1); sub_n sub_n(.o_n); // verilator lint_on PINMISSING always @ (posedge clk) begin if (o_0 !== 1'b0) $stop; if (o_1 !== 1'b1) $stop; //4-state if (o_n !== 1'bz) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule `unconnected_drive pull0 module sub_0 (input i, output wire o_0); assign o_0 = i; endmodule `unconnected_drive pull1 module sub_1 (input i, output wire o_1); assign o_1 = i; endmodule `nounconnected_drive module sub_n (input i, output wire o_n); assign o_n = i; endmodule verilator-5.042/test_regress/t/t_wire_beh1364_bad.out0000644000542200017500000000246015101701376023054 0ustar mahmoudyfreeshell%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:26:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'w' : ... note: In instance 't' 26 | w = 0; | ^ ... For error description see https://verilator.org/warn/PROCASSWIRE?v=latest %Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:27:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'o' : ... note: In instance 't' 27 | o = 0; | ^ %Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:28:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'oa' : ... note: In instance 't' 28 | oa = 0; | ^~ %Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:29:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'wo' : ... note: In instance 't' 29 | wo = 0; | ^~ %Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:30:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'woa' : ... note: In instance 't' 30 | woa = 0; | ^~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_preproc_resolve.v0000644000542200017500000000066215101701376023015 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `timescale 1ns/1ps module top(/*AUTOARG*/ input logic clk, input logic rst, output logic top_out ); submod u_submod (/*AUTOINST*/ .clk (clk), .rst (rst), .out_signal(top_out) ); endmodule verilator-5.042/test_regress/t/t_interface_arraymux.py0000755000542200017500000000070615101701376023661 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.042/test_regress/t/t_class_param_type.py0000755000542200017500000000073415101701376023320 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_assert_cover.v0000644000542200017500000001026315101701376022301 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg toggle; integer cyc; initial cyc=1; Test test (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle), .cyc (cyc[31:0])); Sub sub1 (.*); Sub sub2 (.*); always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; toggle <= !cyc[0]; if (cyc==9) begin end if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module Test ( input clk, input toggle, input [31:0] cyc ); // Simple cover cover property (@(posedge clk) cyc==3); // With statement, in generate generate if (1) begin cover property (@(posedge clk) cyc==4) $display("*COVER: Cyc==4"); end endgenerate // Labeled cover cyc_eq_5: cover property (@(posedge clk) cyc==5) $display("*COVER: Cyc==5"); // Using default clock default clocking @(posedge clk); endclocking cover property (cyc==6) $display("*COVER: Cyc==6"); // Disable statement // Note () after disable are required cover property (@(posedge clk) disable iff (toggle) cyc==8) $display("*COVER: Cyc==8"); cover property (@(posedge clk) disable iff (!toggle) cyc==8) $stop; always_ff @ (posedge clk) begin labeled_icov: cover (cyc==3 || cyc==4); end // Immediate cover labeled_imm0: cover #0 (cyc == 0); labeled_immf: cover final (cyc == 0); // Immediate assert labeled_imas: assert #0 (1); assert final (1); //============================================================ // Using a macro and generate wire reset = (cyc < 2); `define covclk(eqn) cover property (@(posedge clk) disable iff (reset) (eqn)) genvar i; generate for (i=0; i<32; i=i+1) begin: cycval CycCover_i: `covclk( cyc[i] ); end endgenerate //============================================================ // Using a more complicated property property C1; @(posedge clk) disable iff (!toggle) cyc==5; endproperty cover property (C1) $display("*COVER: Cyc==5"); `ifndef verilator // Unsupported //============================================================ // Using covergroup // Note a covergroup is really inheritance of a special system "covergroup" class. covergroup counter1 @ (posedge cyc); // Automatic methods: stop(), start(), sample(), set_inst_name() // Each bin value must be <= 32 bits. Strange. cyc_value : coverpoint cyc { } cyc_bined : coverpoint cyc { bins zero = {0}; bins low = {1,5}; // Note 5 is also in the bin above. Only the first bin matching is counted. bins mid = {[5:$]}; // illegal_bins // Has precidence over "first matching bin", creates assertion // ignore_bins // Not counted, and not part of total } toggle : coverpoint (toggle) { bins off = {0}; bins on = {1}; } cyc5 : coverpoint (cyc==5) { bins five = {1}; } // option.at_least = {number}; // Default 1 - Hits to be considered covered // option.auto_bin_max = {number}; // Default 64 // option.comment = {string}; // Default "" // option.goal = {number}; // Default 90% // option.name = {string}; // Default "" // option.per_instance = 1; // Default 0 - each instance separately counted (cadence default is 1) // option.weight = {number}; // Default 1 // CROSS value_and_toggle: // else default is ___X__ cross cyc_value, toggle; endgroup counter1 c1 = new(); `endif endmodule module Sub ( input clk, input integer cyc ); // Simple cover, per-instance pi_sub: cover property (@(posedge clk) cyc == 3); endmodule verilator-5.042/test_regress/t/t_wire_behp1364_bad.py0000755000542200017500000000107615101701376023062 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--lint-only --language 1364-2001"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_constraint_pure_missing_bad.v0000644000542200017500000000055315101701376025361 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 virtual class Base; pure constraint raint; endclass class Cls extends Base; // Bad: Missing 'constraint raint' endclass module t; endmodule verilator-5.042/test_regress/t/t_enum_type_nomethod_bad.out0000644000542200017500000000054715101701376024660 0ustar mahmoudyfreeshell%Error: t/t_enum_type_nomethod_bad.v:15:9: Unknown built-in enum method 'bad_no_such_method' : ... note: In instance 't' 15 | e.bad_no_such_method(); | ^~~~~~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_math_pow3.py0000755000542200017500000000073415101701376021673 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_foreach_class.py0000755000542200017500000000073415101701376022566 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_assigndly_task.py0000755000542200017500000000071415101701376023007 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.passes() verilator-5.042/test_regress/t/t_display_merge.py0000755000542200017500000000124615101701376022615 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.compile(verilator_flags2=["--stats"]) test.execute(expect_filename=test.golden_filename) test.file_grep(test.obj_dir + "/" + test.vm_prefix + "__stats.txt", r'Node count, DISPLAY \s+ 44 \s+ 27 \s+ 27 \s+ 6') test.passes() verilator-5.042/test_regress/t/t_langext_2023ext.py0000755000542200017500000000105515101701376022620 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_langext_2.v" # This is a compile only test. test.compile(v_flags2=["+1800-2023ext+v"]) test.passes() verilator-5.042/test_regress/t/t_func_ref_noparen.py0000755000542200017500000000070615101701376023302 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.passes() verilator-5.042/test_regress/t/t_bitsel_lvalue.v0000644000542200017500000000104115101701376022426 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( input wire [ 31:0] foo, output reg [144:0] bar, output reg [144:0] bar2, output reg [144:0] bar3, output reg [144:0] bar4 ); // verilator lint_off SELRANGE assign bar[159:128] = foo; assign bar2[159] = foo[1]; assign bar3[159 -: 32] = foo; assign bar4[128 +: 32] = foo; endmodule verilator-5.042/test_regress/t/t_order_dpi_export_6.py0000755000542200017500000000105615101701376023565 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_langext_order.v0000644000542200017500000000057615101701376022445 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // A test of the +verilog2001ext+ and +verilog2005ext+ flags. // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilator lint_off SYMRSVDWORD module t(input do); t_langext_order_sub sub (.do(do)); endmodule verilator-5.042/test_regress/t/t_trace_empty.v0000644000542200017500000000076415101701376022123 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); /* verilator tracing_off */ input clk; reg [7:0] cyc = 8'd0; always @(posedge clk) begin cyc <= cyc + 1; if (cyc == 20) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_var_ref_bad2.out0000644000542200017500000000113115101701376022452 0ustar mahmoudyfreeshell%Error: t/t_var_ref_bad2.v:13:7: Assigning to const ref variable: 'bad_const_set' : ... note: In instance 't' 13 | bad_const_set = 32'h4567; | ^~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_var_ref_bad2.v:23:17: Ref argument requires matching types; port 'int_ref' requires 'int' but connection is 'byte'. : ... note: In instance 't' 23 | checkset2(bad_non_int); | ^~~~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_tri_pullvec_bad.py0000755000542200017500000000077315101701376023133 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_latch_casei_bad.out0000644000542200017500000000100615101701376024232 0ustar mahmoudyfreeshell%Warning-LATCH: t/t_lint_latch_casei_bad.v:12:3: Latch inferred for signal 'o' (not all control paths of combinational always assign a value) : ... Suggest use of always_latch for intentional latches 12 | always_comb begin | ^~~~~~~~~~~ ... For warning description see https://verilator.org/warn/LATCH?v=latest ... Use "/* verilator lint_off LATCH */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_tri_inout2.v0000644000542200017500000000274215101701376021703 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [2:0] in; wire a,y,y_fixed; wire b = in[0]; wire en = in[1]; pullup(a); ChildA childa ( .A(a), .B(b), .en(en), .Y(y),.Yfix(y_fixed) ); initial in=0; // Test loop always @ (posedge clk) begin in <= in + 1; $display ( "a %d b %d en %d y %d yfix: %d)" , a, b, en, y, y_fixed); if (en) begin // driving b // a should be b // y and yfix should also be b if (a!=b || y != b || y_fixed != b) begin $display ( "Expected a %d y %b yfix %b" , a, y, y_fixed); $stop; end end else begin // not driving b // a should be 1 (pullup) // y and yfix shold be 1 if (a!=1 || y != 1 || y_fixed != 1) begin $display( "Expected a,y,yfix == 1"); $stop; end end if (in==3) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module ChildA(inout A, input B, input en, output Y, output Yfix); // workaround wire a_in = A; ChildB childB(.A(A), .Y(Y)); assign A = en ? B : 1'bz; ChildB childBfix(.A(a_in),.Y(Yfix)); endmodule module ChildB(input A, output Y); assign Y = A; endmodule verilator-5.042/test_regress/t/t_lint_latch_7.v0000644000542200017500000000074215101701376022152 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module for Issue#xxxx // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2021 by Julien Margetts // SPDX-License-Identifier: Unlicense module test #(parameter W = 65) (input logic [W-1:0] a, input logic e, output logic [W-1:0] z); integer i; always @(*) if (e) for (i=0;iclk = 0; topp->eval(); main_time += 10; topp->clk = 0x2; // ILLEGAL topp->eval(); topp->final(); VL_DO_DANGLING(delete topp, topp); return 0; } verilator-5.042/test_regress/t/t_class_static_member.py0000755000542200017500000000073415101701376023775 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_sys_delta_monitor.out0000644000542200017500000000046615101701376023706 0ustar mahmoudyfreeshell[0] monitor0 00000004 [1] monitor0 00000005 [2] monitor0 00000009 [3] monitor0 0000000a [4] monitor0 0000000e [5] monitor0 0000000f [6] monitor0 00000013 [7] monitor0 00000014 [8] monitor0 00000018 [9] monitor0 00000019 [10] monitor0 0000001d [11] monitor0 0000001e [12] monitor0 00000022 *-* All Finished *-* verilator-5.042/test_regress/t/t_class_virtual_protect_ids.py0000755000542200017500000000151515101701376025242 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_class_virtual.v" # This test makes randomly named .cpp/.h files, which tend to collect, so remove them first for filename in (glob.glob(test.obj_dir + "/*_PS*.cpp") + glob.glob(test.obj_dir + "/*_PS*.h") + glob.glob(test.obj_dir + "/*.d")): test.unlink_ok(filename) test.compile(verilator_flags2=["--protect-ids", "--protect-key SECRET_KEY"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_flag_ldflags_a.cpp0000644000542200017500000000103615101701376023022 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* extern "C" { void dpii_a_library() {} }; verilator-5.042/test_regress/t/t_param_type_bad3.v0000644000542200017500000000045115101701376022632 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; localparam int PI = 6; localparam type P_T = PI; // Bad endmodule verilator-5.042/test_regress/t/t_randc.v0000644000542200017500000000623515101701376020675 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class ClsNarrow #(parameter int WIDTH); randc bit [WIDTH-1:0] m_var; function void test; automatic int i; automatic int count[2**WIDTH]; automatic int maxcount; automatic bit bad; automatic int randomize_result; $display("Test %m"); for (int trial = 0; trial < 10; ++trial) begin for (i = 0; i < (2 ** WIDTH); ++i) begin randomize_result = randomize(); if (randomize_result !== 1) $stop; `ifdef TEST_VERBOSE $display("w%0d i=%0d m_var=%x", WIDTH, i, m_var); `endif ++count[m_var]; end end maxcount = count[0]; bad = '0; `ifndef TEST_IGNORE_RANDC for (i = 0; i < (2 ** WIDTH); ++i) begin if (maxcount != count[i]) bad = '1; end `endif if (bad) begin $display("%%Error: count mismatch"); for (i = 0; i < (2 ** WIDTH); ++i) begin $display("w%0d entry[%0d]=%0d", WIDTH, i, count[i]); end $stop; end endfunction endclass class ClsWide #(parameter int WIDTH); randc bit [WIDTH-1:0] m_var; function void test; automatic bit [WIDTH-1:0] last; automatic int randomize_result; $display("Test %m"); for (int i = 0; i < 100; ++i) begin randomize_result = randomize(); if (randomize_result !== 1) $stop; `ifdef TEST_VERBOSE $display("ww%0d i=%0d m_var=%x", WIDTH, i, m_var); `endif if (i != 0) begin `ifndef TEST_IGNORE_RANDC if (m_var == last) $stop; `endif end last = m_var; end endfunction endclass class ClsEnum; typedef enum bit [3:0] { TWO = 2, FIVE = 5, SIX = 6 } enum_t; randc enum_t m_var; function void test; automatic enum_t last; automatic int randomize_result; $display("Test %m"); for (int trial = 0; trial < 10; ++trial) begin for (int i = 0; i < 3; ++i) begin randomize_result = randomize(); if (randomize_result !== 1) $stop; `ifdef TEST_VERBOSE $display("we i=%0d m_var=%x", i, m_var); `endif if (m_var != TWO && m_var != FIVE && m_var != SIX) $stop; if (i != 0) begin `ifndef TEST_IGNORE_RANDC if (m_var == last) $stop; `endif end last = m_var; end end endfunction endclass module t; ClsNarrow #(1) c1; // Degenerate case ClsNarrow #(2) c2; ClsNarrow #(3) c3; ClsNarrow #(3) c3b; // Need to have two of same size to cover dtype dedup code ClsNarrow #(9) c9; ClsWide #(31) c31; ClsWide #(32) c32; ClsEnum ce; initial begin c1 = new; c1.test(); c2 = new; c2.test(); c3 = new; c3.test(); c3b = new; c3b.test(); c9 = new; c9.test(); c31 = new; c31.test(); c32 = new; c32.test(); ce = new; ce.test(); $write("*-* All Finished *-*\n"); $finish(); end endmodule verilator-5.042/test_regress/t/t_constraint_soft_randc_bad.out0000644000542200017500000000076615101701376025347 0ustar mahmoudyfreeshell%Error: t/t_constraint_soft_randc_bad.v:10:28: Randc variables not allowed in 'constraint soft' (IEEE 1800-2023 18.5.13.1) 10 | constraint c_bad { soft rc > 4; } | ^~ t/t_constraint_soft_randc_bad.v:10:23: ... Location of restricting expression 10 | constraint c_bad { soft rc > 4; } | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_class_super_bad.out0000644000542200017500000000040515101701376023272 0ustar mahmoudyfreeshell%Error: t/t_class_super_bad.v:12:12: 'super' used outside class (IEEE 1800-2023 8.15) 12 | super.addr = 2; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_clk_latch.v0000644000542200017500000000650215101701376021527 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs fastclk, clk ); `ifdef EDGE_DETECT_STYLE // Two 'common' forms of latching, with full combo, and with pos/negedge `define posstyle posedge `define negstyle negedge `else `define posstyle `define negstyle `endif input fastclk; input clk; reg [7:0] data; reg [7:0] data_a; reg [7:0] data_a_a; reg [7:0] data_a_b; reg [7:0] data_b; reg [7:0] data_b_a; reg [7:0] data_b_b; reg [8*6-1:0] check [100:0]; wire [8*6-1:0] compare = {data_a,data_a_a,data_b_a,data_b,data_a_b,data_b_b}; initial begin check[7'd19] = {8'h0d, 8'h0e, 8'h0e, 8'h0d, 8'h0e, 8'h0e}; check[7'd20] = {8'h0d, 8'h0e, 8'h0e, 8'h0d, 8'h0e, 8'h0e}; check[7'd21] = {8'h15, 8'h16, 8'h0e, 8'h0d, 8'h0e, 8'h0e}; check[7'd22] = {8'h15, 8'h16, 8'h0e, 8'h0d, 8'h0e, 8'h0e}; check[7'd23] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e}; check[7'd24] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e}; check[7'd25] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e}; check[7'd26] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h0e}; check[7'd27] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h0e}; check[7'd28] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16}; check[7'd29] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16}; check[7'd30] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16}; check[7'd31] = {8'h1f, 8'h20, 8'h16, 8'h15, 8'h16, 8'h16}; check[7'd32] = {8'h1f, 8'h20, 8'h16, 8'h15, 8'h16, 8'h16}; check[7'd33] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16}; check[7'd34] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16}; check[7'd35] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16}; check[7'd36] = {8'h1f, 8'h20, 8'h20, 8'h1f, 8'h20, 8'h16}; check[7'd37] = {8'h1f, 8'h20, 8'h20, 8'h1f, 8'h20, 8'h16}; end // verilator lint_off COMBDLY // verilator lint_off LATCH always @ (`posstyle clk /*AS*/ or data) begin if (clk) begin data_a <= data + 8'd1; end end always @ (`posstyle clk /*AS*/ or data_a) begin if (clk) begin data_a_a <= data_a + 8'd1; end end always @ (`posstyle clk /*AS*/ or data_b) begin if (clk) begin data_b_a <= data_b + 8'd1; end end always @ (`negstyle clk /*AS*/ or data or data_a) begin if (~clk) begin data_b <= data + 8'd1; data_a_b <= data_a + 8'd1; data_b_b <= data_b + 8'd1; end end integer cyc; initial cyc = 0; always @ (posedge fastclk) begin cyc <= cyc+1; `ifdef TEST_VERBOSE $write("%d %x %x %x %x %x %x\n",cyc,data_a,data_a_a,data_b_a,data_b,data_a_b,data_b_b); `endif if (cyc>=19 && cyc<36) begin if (compare !== check[cyc]) begin $write("[%0t] Mismatch, got=%x, exp=%x\n", $time, compare, check[cyc]); $stop; end end if (cyc == 10) begin data <= 8'd12; end if (cyc == 20) begin data <= 8'd20; end if (cyc == 30) begin data <= 8'd30; end if (cyc == 40) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_class_static.v0000644000542200017500000000347315101701376022263 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); class Cls; int c_no = 2; //automatic int c_au = 2; // automatic not a legal keyword here static int c_st = 2; function int f_c_no (); ++c_no; return c_no; endfunction function int f_c_st (); ++c_st; return c_st; endfunction function int f_no_no (); int au = 2; au++; return au; endfunction function int f_no_st (); static int st = 2; st++; return st; endfunction function int f_no_au (); automatic int au = 2; au++; return au; endfunction endclass module t; Cls a = new; Cls b = new; int v; initial begin v = a.f_c_no(); `checkh(v,3); v = a.f_c_no(); `checkh(v, 4); v = b.f_c_no(); `checkh(v, 3); v = b.f_c_no(); `checkh(v, 4); v = a.f_c_st(); `checkh(v,3); v = a.f_c_st(); `checkh(v, 4); v = b.f_c_st(); `checkh(v, 5); v = b.f_c_st(); `checkh(v, 6); // v = a.f_no_no(); `checkh(v, 3); v = a.f_no_no(); `checkh(v, 3); v = b.f_no_no(); `checkh(v, 3); v = b.f_no_no(); `checkh(v, 3); v = a.f_no_st(); `checkh(v, 3); v = a.f_no_st(); `checkh(v, 4); v = b.f_no_st(); `checkh(v, 5); v = b.f_no_st(); `checkh(v, 6); v = a.f_no_au(); `checkh(v, 3); v = a.f_no_au(); `checkh(v, 3); v = b.f_no_au(); `checkh(v, 3); v = b.f_no_au(); `checkh(v, 3); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_interface_virtual_bad.out0000644000542200017500000000437115101701376024463 0ustar mahmoudyfreeshell%Error: t/t_interface_virtual_bad.v:31:12: Operator ASSIGN expected 'PBus' interface on Assign RHS but 'q8' is a different interface ('QBus'). : ... note: In instance 't' 31 | v8 = q8; | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_interface_virtual_bad.v:35:12: Operator ASSIGN expected no interface modport on Assign RHS but got 'phy' modport. : ... note: In instance 't' 35 | v8 = v8_phy; | ^~~~~~ %Error: t/t_interface_virtual_bad.v:37:17: Operator ASSIGN expected non-interface on Assign RHS but 'p8' is an interface. : ... note: In instance 't' 37 | data = p8.phy; | ^~~ %Error: t/t_interface_virtual_bad.v:38:14: Operator ASSIGN expected non-interface on Assign RHS but 'v8_phy' is an interface. : ... note: In instance 't' 38 | data = v8_phy; | ^~~~~~ %Error: t/t_interface_virtual_bad.v:39:14: Operator ASSIGN expected non-interface on Assign RHS but 'v8' is an interface. : ... note: In instance 't' 39 | data = v8; | ^~ %Error: t/t_interface_virtual_bad.v:40:14: Operator ASSIGN expected non-interface on Assign RHS but 'p8' is an interface. : ... note: In instance 't' 40 | data = p8; | ^~ %Error: t/t_interface_virtual_bad.v:41:12: Operator ASSIGN expected 'PBus' interface on Assign RHS but 'data' is not an interface. : ... note: In instance 't' 41 | v8 = data; | ^~~~ %Error: t/t_interface_virtual_bad.v:44:79: Member 'gran' not found in interface 'PBus' : ... note: In instance 't' : ... Suggested alternative: 'grant' 44 | $display("q8.grant=", p8.grant, " v8.grant=", v8.grant, v8_phy.addr, v8.gran); | ^~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_event_control.py0000755000542200017500000000110015101701376022637 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--no-timing'], fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_timescale_parse.py0000755000542200017500000000105215101701376023124 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_class_param_upcast.v0000644000542200017500000000113515101701376023444 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class factory #(type T); static function T create; T obj = new; return obj; endfunction endclass class foo; endclass class bar extends foo; static function bar create; bar b = new; return b; endfunction endclass module t; initial begin foo f; if (bit'($random)) f = bar::create; else f = factory#(foo)::create(); $finish; end endmodule; verilator-5.042/test_regress/t/t_flag_expand_limit.py0000755000542200017500000000110515101701376023431 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=['--expand-limit 1 --stats -fno-dfg']) test.file_grep(test.stats, r'Optimizations, expand limited\s+(\d+)', 3) test.passes() verilator-5.042/test_regress/t/t_nba_hier.py0000755000542200017500000000171315101701376021537 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--binary', '--stats', '-fno-inline', '--unroll-count', '0']) test.file_grep(test.stats, r'NBA, variables using ShadowVar scheme\s+(\d+)', 2) test.file_grep(test.stats, r'NBA, variables using ShadowVarMasked scheme\s+(\d+)', 2) test.file_grep(test.stats, r'NBA, variables using FlagShared scheme\s+(\d+)', 2) test.file_grep(test.stats, r'NBA, variables using FlagUnique scheme\s+(\d+)', 2) test.file_grep(test.stats, r'NBA, variables using ValueQueuePartial scheme\s+(\d+)', 2) test.execute() test.passes() verilator-5.042/test_regress/t/t_flag_lib_dpi.cpp0000644000542200017500000000100715101701376022506 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Shupei Fan. // SPDX-License-Identifier: CC0-1.0 // //************************************************************************* #include "Vt_flag_lib_dpi__Dpi.h" #include "svdpi.h" #include void write_all_finished() { std::cout << "*-* All Finished *-*" << std::endl; } verilator-5.042/test_regress/t/t_trace_abort_fst.py0000755000542200017500000000116015101701376023125 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_trace_abort.v" test.compile(verilator_flags2=['--cc --trace-fst']) test.execute(fails=True) test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dpi_arg_inout_type.cpp0000644000542200017500000010673715101701376024017 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2020 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include #include #include // clang-format off #if defined(NCSC) // Used by NC's svdpi.h to pick up svLogicVecVal with _.aval and _.bval fields, // rather than the IEEE 1800-2005 version which has _.a and _.b fields. # define DPI_COMPATIBILITY_VERSION_1800v2012 #endif #include "svdpi.h" #if defined(VERILATOR) // Verilator # include "Vt_dpi_arg_inout_type__Dpi.h" typedef long long sv_longint_t; typedef unsigned long long sv_longint_unsigned_t; # define NO_SHORTREAL #elif defined(VCS) // VCS # include "../vc_hdrs.h" typedef long long sv_longint_t; typedef unsigned long long sv_longint_unsigned_t; # define NO_TIME #elif defined(NCSC) // NC # include "dpi-exp.h" # include "dpi-imp.h" typedef long long sv_longint_t; typedef unsigned long long sv_longint_unsigned_t; # define NO_TIME # define NO_INTEGER # define NO_SHORTREAL #elif defined(MS) // ModelSim # include "dpi.h" typedef int64_t sv_longint_t; typedef uint64_t sv_longint_unsigned_t; #else # error "Unknown simulator for DPI test" #endif // clang-format on //====================================================================== // Implementations of imported functions //====================================================================== #define stop() \ do { \ printf(__FILE__ ":%d Bad value\n", __LINE__); \ abort(); \ } while (0) void check_bvals(const svLogicVecVal* v, unsigned n); void check_bvals(const svLogicVecVal* v, unsigned n) { for (unsigned i = 0; i < n; i++) { if (v[i].bval != 0) { printf(__FILE__ ":%d Bad svLogicVecVal bval\n", __LINE__); abort(); } } } void set_bvals(svLogicVecVal* v, unsigned n); void set_bvals(svLogicVecVal* v, unsigned n) { for (unsigned i = 0; i < n; i++) v[i].bval = 0; } // Basic types as per IEEE 1800-2023 35.5.6 void i_byte(char* x) { static int n = 0; if (*x != 10 - n++) stop(); *x += 100; } void i_byte_unsigned(unsigned char* x) { static int n = 0; if (*x != 20 - n++) stop(); *x += 200; } void i_shortint(short* x) { static int n = 0; if (*x != 30 - n++) stop(); *x += 300; } void i_shortint_unsigned(unsigned short* x) { static int n = 0; if (*x != 40 - n++) stop(); *x += 400; } void i_int(int* x) { static int n = 0; if (*x != 50 - n++) stop(); *x += 500; } void i_int_unsigned(unsigned* x) { static int n = 0; if (*x != 60 - n++) stop(); *x += 600; } void i_longint(sv_longint_t* x) { static int n = 0; if (*x != 70 - n++) stop(); *x += 700; } void i_longint_unsigned(sv_longint_unsigned_t* x) { static int n = 0; if (*x != 80 - n++) stop(); *x += 800; } #ifndef NO_TIME void i_time(svLogicVecVal* x) { static int n = 0; if (x[0].aval != 90 - n++) stop(); if (x[1].aval != 0) stop(); check_bvals(x, 2); x[0].aval += 900; } #endif #ifndef NO_INTEGER void i_integer(svLogicVecVal* x) { static int n = 0; if (x[0].aval != 100 - n++) stop(); check_bvals(x, 1); x[0].aval += 1000; } #endif void i_real(double* x) { static int n = 0; if (*x != (-2.0 * n++ - 1.0) / 2.0) stop(); *x += -100.0; } #ifndef NO_SHORTREAL void i_shortreal(float* x) { static int n = 0; if (*x != (-4.0f * n++ - 1.0f) / 4.0f) stop(); *x += -200.0f; } #endif void i_chandle(void** x) { static int n = 0; printf("i_chandle %d\n", n); if (*x) stop(); *x = (n % 2) ? reinterpret_cast(&i_chandle) : 0; n++; } void i_string(const char** x) { static int n = 0; printf("i_string %d\n", n); if (n++ % 2 == 0) { if (std::strcmp(*x, "Hello") != 0) stop(); *x = "Good"; } else { if (std::strcmp(*x, "World") != 0) stop(); *x = "Bye"; } } void i_bit(svBit* x) { static int n = 0; printf("i_bit %d\n", n); if (*x != !(n++ % 2)) stop(); *x ^= 1; } void i_logic(svLogic* x) { static int n = 0; printf("i_logic %d\n", n); if (*x != n++ % 2) stop(); *x ^= 1; } // Basic types via typedefs void i_byte_t(char* x) { static int n = 0; if (*x != 10 - n) stop(); *x += 101; n += 2; } void i_byte_unsigned_t(unsigned char* x) { static int n = 0; if (*x != 20 - n) stop(); *x += 202; n += 2; } void i_shortint_t(short* x) { static int n = 0; if (*x != 30 - n) stop(); *x += 303; n += 2; } void i_shortint_unsigned_t(unsigned short* x) { static int n = 0; if (*x != 40 - n) stop(); *x += 404; n += 2; } void i_int_t(int* x) { static int n = 0; if (*x != 50 - n) stop(); *x += 505; n += 2; } void i_int_unsigned_t(unsigned* x) { static int n = 0; if (*x != 60 - n) stop(); *x += 606; n += 2; } void i_longint_t(sv_longint_t* x) { static int n = 0; if (*x != 70 - n) stop(); *x += 707; n += 2; } void i_longint_unsigned_t(sv_longint_unsigned_t* x) { static int n = 0; if (*x != 80 - n) stop(); *x += 808; n += 2; } #ifndef NO_TIME void i_time_t(svLogicVecVal* x) { static int n = 0; if (x[0].aval != 90 - n) stop(); if (x[1].aval != 0) stop(); check_bvals(x, 2); x[0].aval += 909; n += 2; } #endif #ifndef NO_INTEGER void i_integer_t(svLogicVecVal* x) { static int n = 0; if (x[0].aval != 100 - n) stop(); check_bvals(x, 1); x[0].aval += 1001; n += 2; } #endif void i_real_t(double* x) { static int n = 0; if (*x != (-2.0 * n - 1.0) / 2.0) stop(); *x += -111.0; n += 2; } #ifndef NO_SHORTREAL void i_shortreal_t(float* x) { static int n = 0; if (*x != (-4.0f * n - 1.0f) / 4.0f) stop(); *x += -222.0f; n += 2; } #endif void i_chandle_t(void** x) { static int n = 0; printf("i_chandle_t %d\n", n); if (*x) stop(); *x = (n % 2) ? 0 : reinterpret_cast(&i_chandle_t); n++; } void i_string_t(const char** x) { static int n = 0; printf("i_string_t %d\n", n); if (n++ % 2 == 0) { if (std::strcmp(*x, "World") != 0) stop(); *x = "Bye"; } else { if (std::strcmp(*x, "Hello") != 0) stop(); *x = "Good"; } } void i_bit_t(svBit* x) { static int n = 0; printf("i_bit_t %d\n", n); if (*x != !(n++ % 2)) stop(); *x ^= 1; } void i_logic_t(svLogic* x) { static int n = 0; printf("i_logic_t %d\n", n); if (*x != n++ % 2) stop(); *x ^= 1; } // 2-state packed arrays void i_array_2_state_1(svBitVecVal* x) { static int n = 0; printf("i_array_2_state_1 %d\n", n); *x &= 1; if (*x != !(n++ % 2)) stop(); *x ^= 1; } void i_array_2_state_32(svBitVecVal* x) { static int n = 0; printf("i_array_2_state_32 %d\n", n); if (*x != 0xffffffffU << n) stop(); *x >>= n; n++; } void i_array_2_state_33(svBitVecVal* x) { static int n = 0; printf("i_array_2_state_33 %d\n", n); x[1] &= 1; if (x[0] != 0xffffffffU << n) stop(); if (x[1] != 1) stop(); if (n > 0) { x[0] = x[1] << (32 - n) | x[0] >> n; x[1] = x[1] >> n; } n++; } void i_array_2_state_64(svBitVecVal* x) { static int n = 0; printf("i_array_2_state_64 %d\n", n); if (x[0] != 0xffffffffU << n) stop(); if (x[1] != -1) stop(); if (n > 0) { x[0] = x[1] << (32 - n) | x[0] >> n; x[1] = x[1] >> n; } n++; } void i_array_2_state_65(svBitVecVal* x) { static int n = 0; printf("i_array_2_state_65 %d\n", n); x[2] &= 1; if (x[0] != 0xffffffffU << n) stop(); if (x[1] != -1) stop(); if (x[2] != 1) stop(); if (n > 0) { x[0] = -1; x[1] = x[2] << (32 - n) | x[1] >> n; x[2] = x[2] >> n; } n++; } void i_array_2_state_128(svBitVecVal* x) { static int n = 0; printf("i_array_2_state_128 %d\n", n); if (x[0] != 0xffffffffU << n) stop(); if (x[1] != -1) stop(); if (x[2] != -1) stop(); if (x[3] != -1) stop(); if (n > 0) { x[0] = -1; x[2] = x[3] << (32 - n) | x[2] >> n; x[3] = x[3] >> n; } n++; } // 2-state packed structures void i_struct_2_state_1(svBitVecVal* x) { static int n = 0; printf("i_struct_2_state_1 %d\n", n); *x &= 1; if (*x != !(n++ % 2)) stop(); *x ^= 1; } void i_struct_2_state_32(svBitVecVal* x) { static int n = 0; printf("i_struct_2_state_32 %d\n", n); if (*x != 0xffffffffU << n) stop(); *x >>= n; n++; } void i_struct_2_state_33(svBitVecVal* x) { static int n = 0; printf("i_struct_2_state_33 %d\n", n); x[1] &= 1; if (x[0] != 0xffffffffU << n) stop(); if (x[1] != 1) stop(); if (n > 0) { x[0] = x[1] << (32 - n) | x[0] >> n; x[1] = x[1] >> n; } n++; } void i_struct_2_state_64(svBitVecVal* x) { static int n = 0; printf("i_struct_2_state_64 %d\n", n); if (x[0] != 0xffffffffU << n) stop(); if (x[1] != -1) stop(); if (n > 0) { x[0] = x[1] << (32 - n) | x[0] >> n; x[1] = x[1] >> n; } n++; } void i_struct_2_state_65(svBitVecVal* x) { static int n = 0; printf("i_struct_2_state_65 %d\n", n); x[2] &= 1; if (x[0] != 0xffffffffU << n) stop(); if (x[1] != -1) stop(); if (x[2] != 1) stop(); if (n > 0) { x[0] = -1; x[1] = x[2] << (32 - n) | x[1] >> n; x[2] = x[2] >> n; } n++; } void i_struct_2_state_128(svBitVecVal* x) { static int n = 0; printf("i_struct_2_state_128 %d\n", n); if (x[0] != 0xffffffffU << n) stop(); if (x[1] != -1) stop(); if (x[2] != -1) stop(); if (x[3] != -1) stop(); if (n > 0) { x[0] = -1; x[2] = x[3] << (32 - n) | x[2] >> n; x[3] = x[3] >> n; } n++; } // 2-state packed unions void i_union_2_state_1(svBitVecVal* x) { static int n = 0; printf("i_union_2_state_1 %d\n", n); *x &= 1; if (*x != !(n++ % 2)) stop(); *x ^= 1; } void i_union_2_state_32(svBitVecVal* x) { static int n = 0; printf("i_union_2_state_32 %d\n", n); if (*x != 0xffffffffU << n) stop(); *x >>= n; n++; } void i_union_2_state_33(svBitVecVal* x) { static int n = 0; printf("i_union_2_state_33 %d\n", n); x[1] &= 1; if (x[0] != 0xffffffffU << n) stop(); if (x[1] != 1) stop(); if (n > 0) { x[0] = x[1] << (32 - n) | x[0] >> n; x[1] = x[1] >> n; } n++; } void i_union_2_state_64(svBitVecVal* x) { static int n = 0; printf("i_union_2_state_64 %d\n", n); if (x[0] != 0xffffffffU << n) stop(); if (x[1] != -1) stop(); if (n > 0) { x[0] = x[1] << (32 - n) | x[0] >> n; x[1] = x[1] >> n; } n++; } void i_union_2_state_65(svBitVecVal* x) { static int n = 0; printf("i_union_2_state_65 %d\n", n); x[2] &= 1; if (x[0] != 0xffffffffU << n) stop(); if (x[1] != -1) stop(); if (x[2] != 1) stop(); if (n > 0) { x[0] = -1; x[1] = x[2] << (32 - n) | x[1] >> n; x[2] = x[2] >> n; } n++; } void i_union_2_state_128(svBitVecVal* x) { static int n = 0; printf("i_union_2_state_128 %d\n", n); if (x[0] != 0xffffffffU << n) stop(); if (x[1] != -1) stop(); if (x[2] != -1) stop(); if (x[3] != -1) stop(); if (n > 0) { x[0] = -1; x[2] = x[3] << (32 - n) | x[2] >> n; x[3] = x[3] >> n; } n++; } // 4-state packed arrays void i_array_4_state_1(svLogicVecVal* x) { static int n = 0; printf("i_array_4_state_1 %d\n", n); x[0].aval &= 1; if (x[0].aval != !(n++ % 2)) stop(); check_bvals(x, 1); x[0].aval ^= 1; } void i_array_4_state_32(svLogicVecVal* x) { static int n = 0; printf("i_array_4_state_32 %d\n", n); if (x[0].aval != 0xffffffffU << n) stop(); check_bvals(x, 1); x[0].aval >>= n; n++; } void i_array_4_state_33(svLogicVecVal* x) { static int n = 0; printf("i_array_4_state_33 %d\n", n); x[1].aval &= 1; if (x[0].aval != 0xffffffffU << n) stop(); if (x[1].aval != 1) stop(); check_bvals(x, 2); if (n > 0) { x[0].aval = x[1].aval << (32 - n) | x[0].aval >> n; x[1].aval = x[1].aval >> n; } n++; } void i_array_4_state_64(svLogicVecVal* x) { static int n = 0; printf("i_array_4_state_64 %d\n", n); if (x[0].aval != 0xffffffffU << n) stop(); if (x[1].aval != -1) stop(); check_bvals(x, 2); if (n > 0) { x[0].aval = x[1].aval << (32 - n) | x[0].aval >> n; x[1].aval = x[1].aval >> n; } n++; } void i_array_4_state_65(svLogicVecVal* x) { static int n = 0; printf("i_array_4_state_65 %d\n", n); x[2].aval &= 1; if (x[0].aval != 0xffffffffU << n) stop(); if (x[1].aval != -1) stop(); if (x[2].aval != 1) stop(); check_bvals(x, 3); if (n > 0) { x[0].aval = -1; x[1].aval = x[2].aval << (32 - n) | x[1].aval >> n; x[2].aval = x[2].aval >> n; } n++; } void i_array_4_state_128(svLogicVecVal* x) { static int n = 0; printf("i_array_4_state_128 %d\n", n); if (x[0].aval != 0xffffffffU << n) stop(); if (x[1].aval != -1) stop(); if (x[2].aval != -1) stop(); if (x[3].aval != -1) stop(); check_bvals(x, 4); if (n > 0) { x[0].aval = -1; x[2].aval = x[3].aval << (32 - n) | x[2].aval >> n; x[3].aval = x[3].aval >> n; } n++; } // 4-state packed structures void i_struct_4_state_1(svLogicVecVal* x) { static int n = 0; printf("i_struct_4_state_1 %d\n", n); x[0].aval &= 1; if (x[0].aval != !(n++ % 2)) stop(); check_bvals(x, 1); x[0].aval ^= 1; } void i_struct_4_state_32(svLogicVecVal* x) { static int n = 0; printf("i_struct_4_state_32 %d\n", n); if (x[0].aval != 0xffffffffU << n) stop(); check_bvals(x, 1); x[0].aval >>= n; n++; } void i_struct_4_state_33(svLogicVecVal* x) { static int n = 0; printf("i_struct_4_state_33 %d\n", n); x[1].aval &= 1; if (x[0].aval != 0xffffffffU << n) stop(); if (x[1].aval != 1) stop(); check_bvals(x, 2); if (n > 0) { x[0].aval = x[1].aval << (32 - n) | x[0].aval >> n; x[1].aval = x[1].aval >> n; } n++; } void i_struct_4_state_64(svLogicVecVal* x) { static int n = 0; printf("i_struct_4_state_64 %d\n", n); if (x[0].aval != 0xffffffffU << n) stop(); if (x[1].aval != -1) stop(); check_bvals(x, 2); if (n > 0) { x[0].aval = x[1].aval << (32 - n) | x[0].aval >> n; x[1].aval = x[1].aval >> n; } n++; } void i_struct_4_state_65(svLogicVecVal* x) { static int n = 0; printf("i_struct_4_state_65 %d\n", n); x[2].aval &= 1; if (x[0].aval != 0xffffffffU << n) stop(); if (x[1].aval != -1) stop(); if (x[2].aval != 1) stop(); check_bvals(x, 3); if (n > 0) { x[0].aval = -1; x[1].aval = x[2].aval << (32 - n) | x[1].aval >> n; x[2].aval = x[2].aval >> n; } n++; } void i_struct_4_state_128(svLogicVecVal* x) { static int n = 0; printf("i_struct_4_state_128 %d\n", n); if (x[0].aval != 0xffffffffU << n) stop(); if (x[1].aval != -1) stop(); if (x[2].aval != -1) stop(); if (x[3].aval != -1) stop(); check_bvals(x, 4); if (n > 0) { x[0].aval = -1; x[2].aval = x[3].aval << (32 - n) | x[2].aval >> n; x[3].aval = x[3].aval >> n; } n++; } // 4-state packed unions void i_union_4_state_1(svLogicVecVal* x) { static int n = 0; printf("i_union_4_state_1 %d\n", n); x[0].aval &= 1; if (x[0].aval != !(n++ % 2)) stop(); check_bvals(x, 1); x[0].aval ^= 1; } void i_union_4_state_32(svLogicVecVal* x) { static int n = 0; printf("i_union_4_state_32 %d\n", n); if (x[0].aval != 0xffffffffU << n) stop(); check_bvals(x, 1); x[0].aval >>= n; n++; } void i_union_4_state_33(svLogicVecVal* x) { static int n = 0; printf("i_union_4_state_33 %d\n", n); x[1].aval &= 1; if (x[0].aval != 0xffffffffU << n) stop(); if (x[1].aval != 1) stop(); check_bvals(x, 2); if (n > 0) { x[0].aval = x[1].aval << (32 - n) | x[0].aval >> n; x[1].aval = x[1].aval >> n; } n++; } void i_union_4_state_64(svLogicVecVal* x) { static int n = 0; printf("i_union_4_state_64 %d\n", n); if (x[0].aval != 0xffffffffU << n) stop(); if (x[1].aval != -1) stop(); check_bvals(x, 2); if (n > 0) { x[0].aval = x[1].aval << (32 - n) | x[0].aval >> n; x[1].aval = x[1].aval >> n; } n++; } void i_union_4_state_65(svLogicVecVal* x) { static int n = 0; printf("i_union_4_state_65 %d\n", n); x[2].aval &= 1; if (x[0].aval != 0xffffffffU << n) stop(); if (x[1].aval != -1) stop(); if (x[2].aval != 1) stop(); check_bvals(x, 3); if (n > 0) { x[0].aval = -1; x[1].aval = x[2].aval << (32 - n) | x[1].aval >> n; x[2].aval = x[2].aval >> n; } n++; } void i_union_4_state_128(svLogicVecVal* x) { static int n = 0; printf("i_union_4_state_128 %d\n", n); if (x[0].aval != 0xffffffffU << n) stop(); if (x[1].aval != -1) stop(); if (x[2].aval != -1) stop(); if (x[3].aval != -1) stop(); check_bvals(x, 4); if (n > 0) { x[0].aval = -1; x[2].aval = x[3].aval << (32 - n) | x[2].aval >> n; x[3].aval = x[3].aval >> n; } n++; } //====================================================================== // Check exported functions //====================================================================== void check_exports() { static int n = 0; char x_byte; unsigned char x_byte_unsigned; short x_shortint; unsigned short x_shortint_unsigned; int x_int; unsigned x_int_unsigned; sv_longint_t x_longint; sv_longint_unsigned_t x_longint_unsigned; #ifndef NO_TIME svLogicVecVal x_time[2]; #endif #ifndef NO_INTEGER svLogicVecVal x_integer[1]; #endif double x_real; #ifndef NO_SHORTREAL float x_shortreal; #endif void* x_chandle; const char* x_string; svBit x_bit; svLogic x_logic; char x_byte_t; unsigned char x_byte_unsigned_t; short x_shortint_t; unsigned short x_shortint_unsigned_t; int x_int_t; unsigned x_int_unsigned_t; sv_longint_t x_longint_t; sv_longint_unsigned_t x_longint_unsigned_t; #ifndef NO_TIME svLogicVecVal x_time_t[2]; #endif #ifndef NO_INTEGER svLogicVecVal x_integer_t[1]; #endif double x_real_t; #ifndef NO_SHORTREAL float x_shortreal_t; #endif void* x_chandle_t; const char* x_string_t; svBit x_bit_t; svLogic x_logic_t; svBitVecVal x_array_2_state_1[1]; svBitVecVal x_array_2_state_32[1]; svBitVecVal x_array_2_state_33[2]; svBitVecVal x_array_2_state_64[2]; svBitVecVal x_array_2_state_65[3]; svBitVecVal x_array_2_state_128[4]; svBitVecVal x_struct_2_state_1[1]; svBitVecVal x_struct_2_state_32[1]; svBitVecVal x_struct_2_state_33[2]; svBitVecVal x_struct_2_state_64[2]; svBitVecVal x_struct_2_state_65[3]; svBitVecVal x_struct_2_state_128[4]; svBitVecVal x_union_2_state_1[1]; svBitVecVal x_union_2_state_32[1]; svBitVecVal x_union_2_state_33[2]; svBitVecVal x_union_2_state_64[2]; svBitVecVal x_union_2_state_65[3]; svBitVecVal x_union_2_state_128[4]; svLogicVecVal x_array_4_state_1[1]; svLogicVecVal x_array_4_state_32[1]; svLogicVecVal x_array_4_state_33[2]; svLogicVecVal x_array_4_state_64[2]; svLogicVecVal x_array_4_state_65[3]; svLogicVecVal x_array_4_state_128[4]; svLogicVecVal x_struct_4_state_1[1]; svLogicVecVal x_struct_4_state_32[1]; svLogicVecVal x_struct_4_state_33[2]; svLogicVecVal x_struct_4_state_64[2]; svLogicVecVal x_struct_4_state_65[3]; svLogicVecVal x_struct_4_state_128[4]; svLogicVecVal x_union_4_state_1[1]; svLogicVecVal x_union_4_state_32[1]; svLogicVecVal x_union_4_state_33[2]; svLogicVecVal x_union_4_state_64[2]; svLogicVecVal x_union_4_state_65[3]; svLogicVecVal x_union_4_state_128[4]; #ifndef NO_TIME set_bvals(x_time, 2); set_bvals(x_time_t, 2); #endif #ifndef NO_INTEGER set_bvals(x_integer, 1); set_bvals(x_integer_t, 1); #endif set_bvals(x_array_4_state_1, 1); set_bvals(x_array_4_state_32, 1); set_bvals(x_array_4_state_33, 2); set_bvals(x_array_4_state_64, 2); set_bvals(x_array_4_state_65, 3); set_bvals(x_array_4_state_128, 4); set_bvals(x_struct_4_state_1, 1); set_bvals(x_struct_4_state_32, 1); set_bvals(x_struct_4_state_33, 2); set_bvals(x_struct_4_state_64, 2); set_bvals(x_struct_4_state_65, 3); set_bvals(x_struct_4_state_128, 4); set_bvals(x_union_4_state_1, 1); set_bvals(x_union_4_state_32, 1); set_bvals(x_union_4_state_33, 2); set_bvals(x_union_4_state_64, 2); set_bvals(x_union_4_state_65, 3); set_bvals(x_union_4_state_128, 4); // Basic types as per IEEE 1800-2023 35.5.6 x_byte = 10 + n; e_byte(&x_byte); if (x_byte != 110 + n) stop(); x_byte_unsigned = 20 + n; e_byte_unsigned(&x_byte_unsigned); if (x_byte_unsigned != 220 + n) stop(); x_shortint = 30 + n; e_shortint(&x_shortint); if (x_shortint != 330 + n) stop(); x_shortint_unsigned = 40 + n; e_shortint_unsigned(&x_shortint_unsigned); if (x_shortint_unsigned != 440 + n) stop(); x_int = 50 + n; e_int(&x_int); if (x_int != 550 + n) stop(); x_int_unsigned = 60 + n; e_int_unsigned(&x_int_unsigned); if (x_int_unsigned != 660 + n) stop(); x_longint = 70 + n; e_longint(&x_longint); if (x_longint != 770 + n) stop(); x_longint_unsigned = 80 + n; e_longint_unsigned(&x_longint_unsigned); if (x_longint_unsigned != 880 + n) stop(); #ifndef NO_TIME x_time[0].aval = 90 + n; x_time[1].aval = 0; e_time(x_time); if (x_time[0].aval != 990 + n || x_time[1].aval != 0) stop(); check_bvals(x_time, 2); #endif #ifndef NO_INTEGER x_integer[0].aval = 100 + n; e_integer(x_integer); if (x_integer[0].aval != 1100 + n) stop(); check_bvals(x_integer, 1); #endif x_real = 1.0 * n + 0.50; e_real(&x_real); if (x_real != 100.0 + 1.0 * n + 0.5) stop(); #ifndef NO_SHORTREAL x_shortreal = 1.0f * n + 0.25f; e_shortreal(&x_shortreal); if (x_shortreal != 200.0f + 1.0f * n + 0.25f) stop(); #endif if ((n % 2) == 0) { x_chandle = reinterpret_cast(&e_chandle); x_string = "Good"; } else { x_chandle = NULL; x_string = "Bye"; } e_chandle(&x_chandle); e_string(&x_string); if ((n % 2) == 0) { if (x_chandle) stop(); if (std::strcmp(x_string, "Hello") != 0) stop(); } else { if (x_chandle) stop(); if (std::strcmp(x_string, "World") != 0) stop(); } x_bit = n % 2; e_bit(&x_bit); if (x_bit != !(n % 2)) stop(); x_logic = !(n % 2); e_logic(&x_logic); if (x_logic != n % 2) stop(); // Basic types via tyepdef x_byte_t = 10 + 2 * n; e_byte_t(&x_byte_t); if (x_byte_t != 111 + 2 * n) stop(); x_byte_unsigned_t = 20 + 2 * n; e_byte_unsigned_t(&x_byte_unsigned_t); if (x_byte_unsigned_t != 222 + 2 * n) stop(); x_shortint_t = 30 + 2 * n; e_shortint_t(&x_shortint_t); if (x_shortint_t != 333 + 2 * n) stop(); x_shortint_unsigned_t = 40 + 2 * n; e_shortint_unsigned_t(&x_shortint_unsigned_t); if (x_shortint_unsigned_t != 444 + 2 * n) stop(); x_int_t = 50 + 2 * n; e_int_t(&x_int_t); if (x_int_t != 555 + 2 * n) stop(); x_int_unsigned_t = 60 + 2 * n; e_int_unsigned_t(&x_int_unsigned_t); if (x_int_unsigned_t != 666 + 2 * n) stop(); x_longint_t = 70 + 2 * n; e_longint_t(&x_longint_t); if (x_longint_t != 777 + 2 * n) stop(); x_longint_unsigned_t = 80 + 2 * n; e_longint_unsigned_t(&x_longint_unsigned_t); if (x_longint_unsigned_t != 888 + 2 * n) stop(); #ifndef NO_TIME x_time_t[0].aval = 90 + 2 * n; x_time_t[1].aval = 0; e_time_t(x_time_t); if (x_time_t[0].aval != 999 + 2 * n || x_time_t[1].aval != 0) stop(); check_bvals(x_time_t, 2); #endif #ifndef NO_INTEGER x_integer_t[0].aval = 100 + 2 * n; e_integer_t(x_integer_t); if (x_integer_t[0].aval != 1101 + 2 * n) stop(); check_bvals(x_integer_t, 1); #endif x_real_t = 1.0 * (2 * n) + 0.50; e_real_t(&x_real_t); if (x_real_t != 111.0 + 1.0 * (2 * n) + 0.5) stop(); #ifndef NO_SHORTREAL x_shortreal_t = 1.0f * (2 * n) + 0.25f; e_shortreal_t(&x_shortreal_t); if (x_shortreal_t != 222.0f + 1.0f * (2 * n) + 0.25f) stop(); #endif if ((n % 2) == 0) { x_chandle_t = NULL; x_string_t = "Bye"; } else { x_chandle_t = reinterpret_cast(&e_chandle_t); x_string_t = "Good"; } e_chandle_t(&x_chandle_t); e_string_t(&x_string_t); if ((n % 2) == 0) { if (x_chandle_t != NULL) stop(); if (std::strcmp(x_string_t, "World") != 0) stop(); } else { if (x_chandle_t != NULL) stop(); if (std::strcmp(x_string_t, "Hello") != 0) stop(); } x_bit_t = n % 2; e_bit_t(&x_bit_t); if (x_bit_t != !(n % 2)) stop(); x_logic_t = !(n % 2); e_logic_t(&x_logic_t); if (x_logic_t != n % 2) stop(); const int m = n == 0 ? 0 : n - 1; // 2-state packed arrays x_array_2_state_1[0] = n % 2; x_array_2_state_32[0] = 0xffffffff >> n; x_array_2_state_33[1] = 1 >> n; x_array_2_state_33[0] = 0xffffffff >> m; x_array_2_state_64[1] = 0xffffffff >> n; x_array_2_state_64[0] = 0xffffffff; x_array_2_state_65[2] = 1 >> n; x_array_2_state_65[1] = 0xffffffff >> m; x_array_2_state_65[0] = 0xffffffff; x_array_2_state_128[3] = 0xffffffff >> n; x_array_2_state_128[2] = x_array_2_state_128[1] = x_array_2_state_128[0] = 0xffffffff; e_array_2_state_1(x_array_2_state_1); if ((x_array_2_state_1[0] & 1) != !(n % 2)) stop(); e_array_2_state_32(x_array_2_state_32); if (x_array_2_state_32[0] != 0xffffffff << n) stop(); e_array_2_state_33(x_array_2_state_33); if ((x_array_2_state_33[1] & 1) != 1) stop(); if (x_array_2_state_33[0] != 0xffffffff << n) stop(); e_array_2_state_64(x_array_2_state_64); if (x_array_2_state_64[1] != 0xffffffff) stop(); if (x_array_2_state_64[0] != 0xffffffff << n) stop(); e_array_2_state_65(x_array_2_state_65); if ((x_array_2_state_65[2] & 1) != 1) stop(); if (x_array_2_state_65[1] != 0xffffffff) stop(); if (x_array_2_state_65[0] != 0xffffffff << n) stop(); e_array_2_state_128(x_array_2_state_128); if (x_array_2_state_128[3] != 0xffffffff) stop(); if (x_array_2_state_128[2] != 0xffffffff) stop(); if (x_array_2_state_128[1] != 0xffffffff) stop(); if (x_array_2_state_128[0] != 0xffffffff << n) stop(); // 2-state packed structures x_struct_2_state_1[0] = n % 2; x_struct_2_state_32[0] = 0xffffffff >> n; x_struct_2_state_33[1] = 1 >> n; x_struct_2_state_33[0] = 0xffffffff >> m; x_struct_2_state_64[1] = 0xffffffff >> n; x_struct_2_state_64[0] = 0xffffffff; x_struct_2_state_65[2] = 1 >> n; x_struct_2_state_65[1] = 0xffffffff >> m; x_struct_2_state_65[0] = 0xffffffff; x_struct_2_state_128[3] = 0xffffffff >> n; x_struct_2_state_128[2] = x_struct_2_state_128[1] = x_struct_2_state_128[0] = 0xffffffff; e_struct_2_state_1(x_struct_2_state_1); if ((x_struct_2_state_1[0] & 1) != !(n % 2)) stop(); e_struct_2_state_32(x_struct_2_state_32); if (x_struct_2_state_32[0] != 0xffffffff << n) stop(); e_struct_2_state_33(x_struct_2_state_33); if ((x_struct_2_state_33[1] & 1) != 1) stop(); if (x_struct_2_state_33[0] != 0xffffffff << n) stop(); e_struct_2_state_64(x_struct_2_state_64); if (x_struct_2_state_64[1] != 0xffffffff) stop(); if (x_struct_2_state_64[0] != 0xffffffff << n) stop(); e_struct_2_state_65(x_struct_2_state_65); if ((x_struct_2_state_65[2] & 1) != 1) stop(); if (x_struct_2_state_65[1] != 0xffffffff) stop(); if (x_struct_2_state_65[0] != 0xffffffff << n) stop(); e_struct_2_state_128(x_struct_2_state_128); if (x_struct_2_state_128[3] != 0xffffffff) stop(); if (x_struct_2_state_128[2] != 0xffffffff) stop(); if (x_struct_2_state_128[1] != 0xffffffff) stop(); if (x_struct_2_state_128[0] != 0xffffffff << n) stop(); // 2-state packed unions x_union_2_state_1[0] = n % 2; x_union_2_state_32[0] = 0xffffffff >> n; x_union_2_state_33[1] = 1 >> n; x_union_2_state_33[0] = 0xffffffff >> m; x_union_2_state_64[1] = 0xffffffff >> n; x_union_2_state_64[0] = 0xffffffff; x_union_2_state_65[2] = 1 >> n; x_union_2_state_65[1] = 0xffffffff >> m; x_union_2_state_65[0] = 0xffffffff; x_union_2_state_128[3] = 0xffffffff >> n; x_union_2_state_128[2] = x_union_2_state_128[1] = x_union_2_state_128[0] = 0xffffffff; e_union_2_state_1(x_union_2_state_1); if ((x_union_2_state_1[0] & 1) != !(n % 2)) stop(); e_union_2_state_32(x_union_2_state_32); if (x_union_2_state_32[0] != 0xffffffff << n) stop(); e_union_2_state_33(x_union_2_state_33); if ((x_union_2_state_33[1] & 1) != 1) stop(); if (x_union_2_state_33[0] != 0xffffffff << n) stop(); e_union_2_state_64(x_union_2_state_64); if (x_union_2_state_64[1] != 0xffffffff) stop(); if (x_union_2_state_64[0] != 0xffffffff << n) stop(); e_union_2_state_65(x_union_2_state_65); if ((x_union_2_state_65[2] & 1) != 1) stop(); if (x_union_2_state_65[1] != 0xffffffff) stop(); if (x_union_2_state_65[0] != 0xffffffff << n) stop(); e_union_2_state_128(x_union_2_state_128); if (x_union_2_state_128[3] != 0xffffffff) stop(); if (x_union_2_state_128[2] != 0xffffffff) stop(); if (x_union_2_state_128[1] != 0xffffffff) stop(); if (x_union_2_state_128[0] != 0xffffffff << n) stop(); // 4-state packed arrays x_array_4_state_1[0].aval = n % 2; x_array_4_state_32[0].aval = 0xffffffff >> n; x_array_4_state_33[1].aval = 1 >> n; x_array_4_state_33[0].aval = 0xffffffff >> m; x_array_4_state_64[1].aval = 0xffffffff >> n; x_array_4_state_64[0].aval = 0xffffffff; x_array_4_state_65[2].aval = 1 >> n; x_array_4_state_65[1].aval = 0xffffffff >> m; x_array_4_state_65[0].aval = 0xffffffff; x_array_4_state_128[3].aval = 0xffffffff >> n; x_array_4_state_128[2].aval = 0xffffffff; x_array_4_state_128[1].aval = 0xffffffff; x_array_4_state_128[0].aval = 0xffffffff; e_array_4_state_1(x_array_4_state_1); if ((x_array_4_state_1[0].aval & 1) != !(n % 2)) stop(); e_array_4_state_32(x_array_4_state_32); if (x_array_4_state_32[0].aval != 0xffffffff << n) stop(); e_array_4_state_33(x_array_4_state_33); if ((x_array_4_state_33[1].aval & 1) != 1) stop(); if (x_array_4_state_33[0].aval != 0xffffffff << n) stop(); e_array_4_state_64(x_array_4_state_64); if (x_array_4_state_64[1].aval != 0xffffffff) stop(); if (x_array_4_state_64[0].aval != 0xffffffff << n) stop(); e_array_4_state_65(x_array_4_state_65); if ((x_array_4_state_65[2].aval & 1) != 1) stop(); if (x_array_4_state_65[1].aval != 0xffffffff) stop(); if (x_array_4_state_65[0].aval != 0xffffffff << n) stop(); e_array_4_state_128(x_array_4_state_128); if (x_array_4_state_128[3].aval != 0xffffffff) stop(); if (x_array_4_state_128[2].aval != 0xffffffff) stop(); if (x_array_4_state_128[1].aval != 0xffffffff) stop(); if (x_array_4_state_128[0].aval != 0xffffffff << n) stop(); check_bvals(x_array_4_state_1, 1); check_bvals(x_array_4_state_32, 1); check_bvals(x_array_4_state_33, 2); check_bvals(x_array_4_state_64, 2); check_bvals(x_array_4_state_65, 3); check_bvals(x_array_4_state_128, 4); // 4-state packed structures x_struct_4_state_1[0].aval = n % 2; x_struct_4_state_32[0].aval = 0xffffffff >> n; x_struct_4_state_33[1].aval = 1 >> n; x_struct_4_state_33[0].aval = 0xffffffff >> m; x_struct_4_state_64[1].aval = 0xffffffff >> n; x_struct_4_state_64[0].aval = 0xffffffff; x_struct_4_state_65[2].aval = 1 >> n; x_struct_4_state_65[1].aval = 0xffffffff >> m; x_struct_4_state_65[0].aval = 0xffffffff; x_struct_4_state_128[3].aval = 0xffffffff >> n; x_struct_4_state_128[2].aval = 0xffffffff; x_struct_4_state_128[1].aval = 0xffffffff; x_struct_4_state_128[0].aval = 0xffffffff; e_struct_4_state_1(x_struct_4_state_1); if ((x_struct_4_state_1[0].aval & 1) != !(n % 2)) stop(); e_struct_4_state_32(x_struct_4_state_32); if (x_struct_4_state_32[0].aval != 0xffffffff << n) stop(); e_struct_4_state_33(x_struct_4_state_33); if ((x_struct_4_state_33[1].aval & 1) != 1) stop(); if (x_struct_4_state_33[0].aval != 0xffffffff << n) stop(); e_struct_4_state_64(x_struct_4_state_64); if (x_struct_4_state_64[1].aval != 0xffffffff) stop(); if (x_struct_4_state_64[0].aval != 0xffffffff << n) stop(); e_struct_4_state_65(x_struct_4_state_65); if ((x_struct_4_state_65[2].aval & 1) != 1) stop(); if (x_struct_4_state_65[1].aval != 0xffffffff) stop(); if (x_struct_4_state_65[0].aval != 0xffffffff << n) stop(); e_struct_4_state_128(x_struct_4_state_128); if (x_struct_4_state_128[3].aval != 0xffffffff) stop(); if (x_struct_4_state_128[2].aval != 0xffffffff) stop(); if (x_struct_4_state_128[1].aval != 0xffffffff) stop(); if (x_struct_4_state_128[0].aval != 0xffffffff << n) stop(); check_bvals(x_struct_4_state_1, 1); check_bvals(x_struct_4_state_32, 1); check_bvals(x_struct_4_state_33, 2); check_bvals(x_struct_4_state_64, 2); check_bvals(x_struct_4_state_65, 3); check_bvals(x_struct_4_state_128, 4); // 4-state packed unions x_union_4_state_1[0].aval = n % 2; x_union_4_state_32[0].aval = 0xffffffff >> n; x_union_4_state_33[1].aval = 1 >> n; x_union_4_state_33[0].aval = 0xffffffff >> m; x_union_4_state_64[1].aval = 0xffffffff >> n; x_union_4_state_64[0].aval = 0xffffffff; x_union_4_state_65[2].aval = 1 >> n; x_union_4_state_65[1].aval = 0xffffffff >> m; x_union_4_state_65[0].aval = 0xffffffff; x_union_4_state_128[3].aval = 0xffffffff >> n; x_union_4_state_128[2].aval = 0xffffffff; x_union_4_state_128[1].aval = 0xffffffff; x_union_4_state_128[0].aval = 0xffffffff; e_union_4_state_1(x_union_4_state_1); if ((x_union_4_state_1[0].aval & 1) != !(n % 2)) stop(); e_union_4_state_32(x_union_4_state_32); if (x_union_4_state_32[0].aval != 0xffffffff << n) stop(); e_union_4_state_33(x_union_4_state_33); if ((x_union_4_state_33[1].aval & 1) != 1) stop(); if (x_union_4_state_33[0].aval != 0xffffffff << n) stop(); e_union_4_state_64(x_union_4_state_64); if (x_union_4_state_64[1].aval != 0xffffffff) stop(); if (x_union_4_state_64[0].aval != 0xffffffff << n) stop(); e_union_4_state_65(x_union_4_state_65); if ((x_union_4_state_65[2].aval & 1) != 1) stop(); if (x_union_4_state_65[1].aval != 0xffffffff) stop(); if (x_union_4_state_65[0].aval != 0xffffffff << n) stop(); e_union_4_state_128(x_union_4_state_128); if (x_union_4_state_128[3].aval != 0xffffffff) stop(); if (x_union_4_state_128[2].aval != 0xffffffff) stop(); if (x_union_4_state_128[1].aval != 0xffffffff) stop(); if (x_union_4_state_128[0].aval != 0xffffffff << n) stop(); check_bvals(x_union_4_state_1, 1); check_bvals(x_union_4_state_32, 1); check_bvals(x_union_4_state_33, 2); check_bvals(x_union_4_state_64, 2); check_bvals(x_union_4_state_65, 3); check_bvals(x_union_4_state_128, 4); n++; } verilator-5.042/test_regress/t/t_sys_writemem.gold4.mem0000644000542200017500000000142015101701376023645 0ustar mahmoudyfreeshell000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000 7755400437654321276543211765432107654321abcdef10 000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000 7755400a37654321276543211765432107654321abcdef11 7755400b37654321276543211765432107654321abcdef12 7755400c37654321276543211765432107654321abcdef13 000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000 verilator-5.042/test_regress/t/t_eq_wild.v0000644000542200017500000000075615101701376021234 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 function bit get_1_or_0(bit get_1); return get_1 ? 1'b1 : 1'b0; endfunction module t; initial begin if (get_1_or_0(0) ==? get_1_or_0(1)) $stop; if (!(get_1_or_0(0) !=? get_1_or_0(1))) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_for_comma.v0000644000542200017500000000443715101701376021552 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define checkc(expc) \ do begin \ if (c !== expc) begin \ $write("%%Error: %s:%0d: a=%0d b=%0d c=%0d expc=%0d\n", `__FILE__,`__LINE__, a, b, c, (expc)); \ $stop; \ end \ a=0; b=0; c=0; \ end while(0); module t; int a, b, c; initial begin for (; ; ) begin c = c + 1 + a + b; break; end `checkc(1); for (; ; a = a + 1) begin c = c + 1 + a + b; break; end `checkc(1); for (; ; a = a + 1, b = b + 1) begin c = c + 1 + a + b; break; end `checkc(1); for (; a < 3; ) begin c = c + 1 + a + b; break; end `checkc(1); for (; a < 3; a = a + 1) begin c = c + 1 + a + b; break; end `checkc(1); for (; a < 3; a = a + 1, b = b + 1) begin c = c + 1 + a + b; break; end `checkc(1); for (a = 1; a < 3; ) begin c = c + 1 + a + b; a = a + 10; end `checkc(2); for (a = 1; a < 3; a = a + 1) begin c = c + 1 + a + b; end `checkc(5); for (a = 1; a < 3; a = a + 1, b = b + 1) begin c = c + 1 + a + b; end `checkc(6); for (int a = 1; a < 3; ) begin c = c + 1 + a + b; a = a + 10; end `checkc(2); for (int a = 1; a < 3; a = a + 1) begin c = c + 1 + a + b; end `checkc(5); for (int a = 1; a < 3; a = a + 1, b = b + 1) begin c = c + 1 + a + b; end `checkc(6); for (var int a = 1; a < 3; ) begin c = c + 1 + a + b; a = a + 10; end `checkc(2); for (var int a = 1; a < 3; a = a + 1) begin c = c + 1 + a + b; end `checkc(5); for (var int a = 1; a < 3; a = a + 1, b = b + 1) begin c = c + 1 + a + b; end `checkc(6); for (int a = 1, int b = 1; a < 3; ) begin c = c + 1 + a + b; a = a + 10; end `checkc(3); for (int a = 1, int b = 1; a < 3; a = a + 1) begin c = c + 1 + a + b; end `checkc(7); for (int a = 1, int b = 1; a < 3; a = a + 1, b = b + 1) begin c = c + 1 + a + b; end `checkc(8); for (int a = 1, x = 1; a < 3; a = a + 1, x = x + 1) begin c = c + 1 + a + x; end `checkc(8); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_timing_cmake.py0000755000542200017500000000144015101701376022414 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_timing_events.v" if not test.have_coroutines: test.skip("No coroutine support") if re.search(r'clang', test.cxx_version): test.skip("Known clang bug on ubuntu-24.04") test.compile(verilator_flags2=["--timescale 10ns/1ns --main --timing"], verilator_make_gmake=False, verilator_make_cmake=True) test.passes() verilator-5.042/test_regress/t/t_lint_pragma_protected_bad.out0000644000542200017500000001726415101701376025330 0ustar mahmoudyfreeshell%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:14:17: Unknown '`pragma protect' error 14 | `pragma protect encrypt_agent=123 | ^~~~~~~~~~~~~~~~~ ... For error description see https://verilator.org/warn/BADSTDPRAGMA?v=latest %Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:16:17: Unknown '`pragma protect' error 16 | `pragma protect encrypt_agent_info | ^~~~~~~~~~~~~~~~~~ %Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:29:1: BASE64 encoding length mismatch in `pragma protect key_block/data_block %Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:33:17: Multiple `pragma protected encoding sections 33 | `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ %Warning-PROTECTED: t/t_lint_pragma_protected_bad.v:50:17: A '`pragma protected data_block' encrypted section was detected and will be skipped. ... For warning description see https://verilator.org/warn/PROTECTED?v=latest ... Use "/* verilator lint_off PROTECTED */" and lint_on around source to disable this message. %Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:57:17: Illegal encoding type for `pragma protected encoding 57 | `pragma protect encoding = (enctype = "A-bad-not-BASE64", line_length = 1, bytes = 295) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_lint_pragma_protected_bad.v:57:17: Unsupported: only BASE64 is recognized for `pragma protected encoding 57 | `pragma protect encoding = (enctype = "A-bad-not-BASE64", line_length = 1, bytes = 295) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Warning-PROTECTED: t/t_lint_pragma_protected_bad.v:59:17: A '`pragma protected data_block' encrypted section was detected and will be skipped. %Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:60:1: BASE64 encoding (too short) in `pragma protect key_block/data_block 60 | c2lvbiAzIG9mIHRoZSBHTlUgTGVzc2VyCkdlbmVyYWwgUHVibGljIExpY2Vuc2UsIGFuZCB0aGUg | ^ %Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:61:1: BASE64 encoding (too short) in `pragma protect key_block/data_block 61 | IkdOVSBHUEwiIHJlZmVycyB0byB2ZXJzaW9uIDMgb2YgdGhlIEdOVQpHZW5lcmFsIFB1YmxpYyBM | ^ %Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:62:1: BASE64 encoding (too short) in `pragma protect key_block/data_block 62 | aWNlbnNlLgoKICAiVGhlIExpYnJhcnkiIHJlZmVycyB0byBhIGNvdmVyZWQgd29yayBnb3Zlcm5l | ^ %Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:63:1: BASE64 encoding (too short) in `pragma protect key_block/data_block 63 | ZCBieSB0aGlzIExpY2Vuc2UsCm90aGVyIHRoYW4gYW4gQXBwbGljYXRpb24gb3IgYSBDb21iaW5l | ^ %Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:64:1: BASE64 encoding (too short) in `pragma protect key_block/data_block 64 | ZCBXb3JrIGFzIG== | ^ %Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:65:1: BASE64 encoding (too short) in `pragma protect key_block/data_block %Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:65:1: BASE64 encoding length mismatch in `pragma protect key_block/data_block %Warning-PROTECTED: t/t_lint_pragma_protected_bad.v:69:17: A '`pragma protected data_block' encrypted section was detected and will be skipped. %Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:70:1: BASE64 line too long in `pragma protect key_block/data_block %Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:70:1: BASE64 encoding length mismatch in `pragma protect key_block/data_block %Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:72:17: Multiple `pragma protected encoding sections 72 | `pragma protect encoding = (enctype = "BASE64", line_length = 1, bytes = 4) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ %Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:72:17: line_length must be multiple of 4 for BASE64 72 | `pragma protect encoding = (enctype = "BASE64", line_length = 1, bytes = 4) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ %Warning-PROTECTED: t/t_lint_pragma_protected_bad.v:74:17: A '`pragma protected data_block' encrypted section was detected and will be skipped. %Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:75:1: BASE64 line too long in `pragma protect key_block/data_block %Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:75:1: BASE64 encoding length mismatch in `pragma protect key_block/data_block %Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:77:17: Multiple `pragma protected encoding sections 77 | `pragma protect encoding = (enctype = "UUENCODE", line_length = 1, bytes = 4) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_lint_pragma_protected_bad.v:77:17: Unsupported: only BASE64 is recognized for `pragma protected encoding 77 | `pragma protect encoding = (enctype = "UUENCODE", line_length = 1, bytes = 4) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ %Warning-PROTECTED: t/t_lint_pragma_protected_bad.v:79:17: A '`pragma protected data_block' encrypted section was detected and will be skipped. %Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:80:1: BASE64 line too long in `pragma protect key_block/data_block %Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:80:1: BASE64 encoding length mismatch in `pragma protect key_block/data_block %Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:81:17: Multiple `pragma protected encoding sections 81 | `pragma protect encoding = (enctype = "QUOTED-PRINTABLE", line_length = 1, bytes = 4) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ %Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:81:17: Illegal encoding type for `pragma protected encoding 81 | `pragma protect encoding = (enctype = "QUOTED-PRINTABLE", line_length = 1, bytes = 4) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_lint_pragma_protected_bad.v:81:17: Unsupported: only BASE64 is recognized for `pragma protected encoding 81 | `pragma protect encoding = (enctype = "QUOTED-PRINTABLE", line_length = 1, bytes = 4) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ %Warning-PROTECTED: t/t_lint_pragma_protected_bad.v:83:17: A '`pragma protected data_block' encrypted section was detected and will be skipped. %Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:84:1: BASE64 encoding (too short) in `pragma protect key_block/data_block %Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:84:1: BASE64 encoding length mismatch in `pragma protect key_block/data_block %Error-UNSUPPORTED: t/t_lint_pragma_protected_bad.v:85:17: Unsupported: only BASE64 is recognized for `pragma protected encoding 85 | `pragma protect encoding = (enctype = "RAW", line_length = 1, bytes = 4) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ %Warning-PROTECTED: t/t_lint_pragma_protected_bad.v:87:17: A '`pragma protected data_block' encrypted section was detected and will be skipped. %Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:88:1: BASE64 line too long in `pragma protect key_block/data_block %Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:88:1: BASE64 encoding length mismatch in `pragma protect key_block/data_block %Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:96:1: `pragma is missing a pragma_expression. 96 | `pragma | ^~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_string_byte.py0000755000542200017500000000073415101701376022323 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_dpi_export_scope_bad.cpp0000644000542200017500000000113515101701376024271 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include //====================================================================== #include "Vt_dpi_export_scope_bad__Dpi.h" #ifdef NEED_EXTERNS extern "C" { extern void dpix_task(); } #endif //====================================================================== void dpix_run_tests() { dpix_task(); // Wrong scope } verilator-5.042/test_regress/t/t_clk_gater.py0000755000542200017500000000120215101701376021714 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--stats", test.wno_unopthreads_for_few_cores]) test.execute() #Optimization is disabled #test.file_grep(test.stats, r'Optimizations, Gaters inserted\s+(\d+)'i, 3) test.passes() verilator-5.042/test_regress/t/t_covergroup_with_sample_args.v0000644000542200017500000000071515101701376025406 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off COVERIGN */ module t; covergroup cg_with_sample(int init_val) with function sample (int addr, bit is_read); endgroup cg_with_sample cov1 = new(42); function void run(); cov1.sample(16, 1'b1); endfunction endmodule verilator-5.042/test_regress/t/t_lint_lint_bad.py0000755000542200017500000000107015101701376022566 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["--lint-only -Wwarn-lint"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_vlcov_opt_wild.info.out0000644000542200017500000001020315101701376024122 0ustar mahmoudyfreeshellTN:verilator_coverage SF:t/t_cover_line.v DA:12,19 DA:14,2 DA:15,1 DA:18,1 DA:20,11 BRDA:20,0,0,11 BRDA:20,0,1,5 BRDA:20,0,2,2 BRDA:20,0,3,1 BRDA:20,0,4,0 BRDA:20,0,5,0 BRDA:20,0,6,0 BRDA:20,0,7,0 DA:55,10 DA:56,10 BRDA:56,0,0,10 BRDA:56,0,1,0 DA:57,10 DA:58,10 DA:60,9 BRDA:60,0,0,1 BRDA:60,0,1,9 DA:61,9 BRDA:61,0,0,1 BRDA:61,0,1,9 DA:62,1 DA:63,1 DA:66,9 BRDA:66,0,0,1 BRDA:66,0,1,9 DA:67,9 BRDA:67,0,0,1 BRDA:67,0,1,9 DA:69,9 DA:70,9 DA:73,9 BRDA:73,0,0,1 BRDA:73,0,1,9 DA:74,9 BRDA:74,0,0,1 BRDA:74,0,1,9 DA:75,1 DA:76,1 DA:79,9 DA:80,9 DA:83,1 DA:84,1 DA:85,1 DA:87,1 DA:88,1 DA:89,1 DA:91,7 BRDA:91,0,0,1 BRDA:91,0,1,7 DA:92,1 DA:93,1 DA:96,7 DA:97,7 DA:100,0 DA:101,0 DA:102,0 DA:104,0 DA:105,10 BRDA:105,0,0,0 BRDA:105,0,1,10 DA:106,10 BRDA:106,0,0,0 BRDA:106,0,1,10 DA:107,0 DA:110,1 DA:111,1 DA:113,1 DA:115,1 DA:120,7 BRDA:120,0,0,1 BRDA:120,0,1,7 DA:121,1 DA:122,1 DA:127,1 DA:129,1 DA:138,38 DA:139,4 DA:140,20 DA:141,18 BRDA:141,0,0,2 BRDA:141,0,1,18 DA:142,2 DA:145,18 DA:159,38 DA:160,4 DA:164,20 DA:165,20 DA:166,20 BRDA:166,0,0,0 BRDA:166,0,1,20 DA:168,0 DA:170,18 BRDA:170,0,0,2 BRDA:170,0,1,18 DA:172,2 DA:174,18 DA:188,1 DA:189,1 DA:190,1 BRDA:190,0,0,1 BRDA:190,0,1,0 DA:191,1 DA:194,11 DA:195,11 BRDA:195,0,0,11 BRDA:195,0,1,0 DA:196,11 DA:199,11 DA:200,11 BRDA:200,0,0,11 BRDA:200,0,1,0 DA:201,11 DA:210,19 DA:211,2 DA:215,10 DA:216,10 DA:219,11 DA:221,11 DA:222,10 BRDA:222,0,0,1 BRDA:222,0,1,10 DA:223,1 DA:225,10 BRDA:225,0,0,1 BRDA:225,0,1,10 DA:226,1 DA:229,11 DA:230,1 DA:231,11 DA:232,11 DA:241,19 DA:242,2 DA:252,10 DA:253,9 BRDA:253,0,0,1 BRDA:253,0,1,9 DA:255,1 DA:256,1 BRDA:256,0,0,0 BRDA:256,0,1,1 DA:261,19 DA:262,10 BRDA:262,0,0,10 BRDA:262,0,1,5 BRDA:262,0,2,2 BRDA:262,0,3,1 DA:265,10 DA:266,10 DA:267,1 DA:268,1 DA:269,1 DA:270,1 DA:271,1 DA:272,5 DA:276,10 DA:277,10 DA:287,0 DA:288,0 BRDA:288,0,0,0 BRDA:288,0,1,0 DA:289,0 DA:291,0 DA:292,0 DA:294,0 DA:300,1 DA:303,1 DA:304,20 DA:305,20 DA:309,19 BRDA:309,0,0,19 BRDA:309,0,1,11 BRDA:309,0,2,0 BRDA:309,0,3,0 BRDA:309,0,4,0 BRDA:309,0,5,0 BRDA:309,0,6,0 BRDA:309,0,7,0 BRDA:309,0,8,0 BRDA:309,0,9,0 BRDA:309,0,10,0 BRDA:309,0,11,0 BRDA:309,0,12,5 BRDA:309,0,13,0 BRDA:309,0,14,0 BRDA:309,0,15,0 BRDA:309,0,16,0 BRDA:309,0,17,0 BRDA:309,0,18,0 BRDA:309,0,19,0 BRDA:309,0,20,0 BRDA:309,0,21,0 BRDA:309,0,22,0 BRDA:309,0,23,2 BRDA:309,0,24,0 BRDA:309,0,25,0 BRDA:309,0,26,1 BRDA:309,0,27,0 BRDA:309,0,28,0 BRDA:309,0,29,0 BRDA:309,0,30,0 BRDA:309,0,31,0 BRDA:309,0,32,0 DA:310,19 BRDA:310,0,0,0 BRDA:310,0,1,2 BRDA:310,0,2,19 BRDA:310,0,3,6 BRDA:310,0,4,7 BRDA:310,0,5,1 BRDA:310,0,6,19 BRDA:310,0,7,3 BRDA:310,0,8,0 BRDA:310,0,9,0 BRDA:310,0,10,0 DA:311,1 BRDA:311,0,0,1 BRDA:311,0,1,1 BRDA:311,0,2,0 BRDA:311,0,3,0 BRDA:311,0,4,0 BRDA:311,0,5,0 DA:313,2 BRDA:313,0,0,0 BRDA:313,0,1,2 BRDA:313,0,2,0 BRDA:313,0,3,0 BRDA:313,0,4,0 BRDA:313,0,5,0 BRDA:313,0,6,0 BRDA:313,0,7,0 BRDA:313,0,8,2 BRDA:313,0,9,0 BRDA:313,0,10,0 BRDA:313,0,11,0 BRDA:313,0,12,0 BRDA:313,0,13,0 BRDA:313,0,14,0 BRDA:313,0,15,0 BRDA:313,0,16,0 BRDA:313,0,17,0 BRDA:313,0,18,0 BRDA:313,0,19,0 BRDA:313,0,20,0 BRDA:313,0,21,0 BRDA:313,0,22,0 BRDA:313,0,23,0 BRDA:313,0,24,0 BRDA:313,0,25,0 BRDA:313,0,26,0 BRDA:313,0,27,0 BRDA:313,0,28,0 BRDA:313,0,29,0 BRDA:313,0,30,0 BRDA:313,0,31,0 DA:314,1 DA:317,21 DA:318,21 DA:319,21 DA:322,10 DA:324,10 DA:327,31 BRDA:327,0,0,0 BRDA:327,0,1,31 DA:328,28 BRDA:328,0,0,3 BRDA:328,0,1,28 DA:329,21 BRDA:329,0,0,21 BRDA:329,0,1,0 DA:330,10 DA:331,10 BRDA:331,0,0,10 BRDA:331,0,1,7 BRDA:331,0,2,3 BRDA:331,0,3,3 BRDA:331,0,4,7 DA:332,10 BRDA:332,0,0,10 BRDA:332,0,1,0 BRDA:332,0,2,10 DA:334,19 BRDA:334,0,0,12 BRDA:334,0,1,19 BRDA:334,0,2,7 BRDA:334,0,3,5 DA:337,11 BRDA:337,0,0,11 BRDA:337,0,1,0 DA:343,11 BRDA:343,0,0,10 BRDA:343,0,1,11 DA:346,11 DA:347,10 BRDA:347,0,0,1 BRDA:347,0,1,0 BRDA:347,0,2,0 BRDA:347,0,3,1 BRDA:347,0,4,1 BRDA:347,0,5,10 DA:348,10 DA:350,11 BRDA:350,0,0,11 BRDA:350,0,1,10 BRDA:350,0,2,1 BRDA:350,0,3,1 BRDA:350,0,4,10 DA:353,55 BRDA:353,0,0,11 BRDA:353,0,1,11 BRDA:353,0,2,0 BRDA:353,0,3,55 DA:354,55 DA:356,44 BRDA:356,0,0,11 BRDA:356,0,1,0 BRDA:356,0,2,11 BRDA:356,0,3,44 DA:357,44 DA:360,11 BRDA:360,0,0,11 BRDA:360,0,1,0 BRDA:360,0,2,0 BRDA:360,0,3,11 DA:361,11 BRF:183 BRH:39 end_of_record verilator-5.042/test_regress/t/t_covergroup_in_class_colliding.py0000755000542200017500000000070615101701376026063 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.passes() verilator-5.042/test_regress/t/t_constraint_mode_bad.v0000644000542200017500000000115415101701376023577 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Packet; int m_one; constraint cons { m_one > 0 && m_one < 2; } function int get_constraint_mode; return constraint_mode(); endfunction endclass module t; Packet p; initial begin p = new; p.m_one.constraint_mode(0); $display("p.constraint_mode()=%0d", p.constraint_mode()); $display(p.constraint_mode(0)); p.cons.constraint_mode(); end endmodule verilator-5.042/test_regress/t/t_class_extends_arg_super_bad.py0000755000542200017500000000076615101701376025513 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dynarray_cast_write.py0000755000542200017500000000073415101701376024047 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_select_mul_extend.py0000755000542200017500000000073415101701376023475 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_fork_func2_bad.v0000644000542200017500000000057115101701376022447 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; function int f; fork ; join_any // Illegal 13.4.4 return 0; endfunction int i; initial begin i = f(); end endmodule verilator-5.042/test_regress/t/t_case_genx_bad.out0000644000542200017500000000056315101701376022710 0ustar mahmoudyfreeshell%Error: t/t_case_genx_bad.v:14:9: Use of x/? constant in generate case statement, (no such thing as 'generate casez') : ... note: In instance 't' 14 | 32'b1xxx: initial begin end | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_interface_down_inlb.py0000755000542200017500000000110115101701376023752 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_down.v" test.compile(v_flags2=['+define+INLINE_B'], verilator_flags2=['-trace']) test.execute() test.passes() verilator-5.042/test_regress/t/t_case_enum_complete.v0000644000542200017500000000076515101701376023437 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: SystemVerilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; enum logic [2:0] {S0, S1, S2} state; int v = 0; initial begin state = S1; unique case (state) S0, S2: $stop; S1: v++; endcase unique case (state) S2: $stop; default: v++; endcase end endmodule verilator-5.042/test_regress/t/t_wrapper_context_seq.py0000755000542200017500000000150015101701376024056 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Multiple Model Test Module # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_wrapper_context.cpp" test.top_filename = "t/t_wrapper_context.v" test.compile( make_top_shell=False, make_main=False, # link threads library, add custom .cpp code, add tracing & coverage support verilator_flags2=["--exe", test.pli_filename, "--trace-vcd --coverage -cc"], threads=1, make_flags=['CPPFLAGS_ADD=-DVL_NO_LEGACY']) test.execute() test.passes() verilator-5.042/test_regress/t/t_with.v0000644000542200017500000000505415101701376020557 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias' // // Simple bi-directional alias test. // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilog_format: off `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkh(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); // verilog_format: on module t; initial begin int tofind; int aliases[$]; int found[$]; int i; byte byteq[$] = {2, -1, 127}; byte b[]; logic [7:0] m[2][2]; logic bit_arr[1024]; aliases = '{1, 4, 6, 8}; tofind = 6; found = aliases.find with (item == 1); `checkh(found.size, 1); found = aliases.find(j) with (j == tofind); `checkh(found.size, 1); // And as function aliases.find(i) with (i == tofind); // No parenthesis tofind = 0; found = aliases.find with (item == tofind); `checkh(found.size, 0); aliases.find with (item == tofind); // bug3387 i = aliases.sum(); `checkh(i, 'h13); i = byteq.sum() with (int'(item)); `checkh(i, 128); // Unique (array method) tofind = 4; found = aliases.find with (tofind); // "true" match `checkh(found.size, 4); found = aliases.find() with (item == tofind); `checkh(found.size, 1); found = aliases.find(i) with (i == tofind); `checkh(found.size, 1); i = aliases.or(v) with (v); `checkh(i, 'hf); i = aliases.and(v) with (v); `checkh(i, 0); i = aliases.xor(v) with (v); `checkh(i, 'hb); // Based roughly on IEEE 1800-2023 7.12.3 // verilator lint_off WIDTHEXPAND b = {1, 2, 3, 4}; i = b.sum; // = 10 <= 1 + 2 + 3 + 4 `checkd(i, 10); i = b.product; // = 24 <= 1 * 2 * 3 * 4 `checkd(i, 24); i = b.xor with (item + 4); // = 12 <= 5 ^ 6 ^ 7 ^ 8 `checkd(i, 12); m = '{'{5, 10}, '{15, 20}}; i = m.sum with (item.sum with (item)); // = 50 <= 5+10+15+20 `checkd(i, 50); // Width of the reduction method's result is the dtype of the with's expression // verilator lint_on WIDTHEXPAND for (i = 0; i < 1024; ++i) bit_arr[i] = 1'b1; i = bit_arr.sum with (int'(item)); // forces result to be 32-bit `checkd(i, 1024); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_lint_implicit.py0000755000542200017500000000075015101701376022630 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["-Wno-IMPLICIT"]) test.passes() verilator-5.042/test_regress/t/t_disable_fork3.py0000755000542200017500000000077115101701376022502 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_class_extern.py0000755000542200017500000000073415101701376022464 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_timing_wait_long.py0000755000542200017500000000103515101701376023317 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_func_recurse2.py0000755000542200017500000000073415101701376022537 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_foreach_blkname.py0000755000542200017500000000070615101701376023071 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.042/test_regress/t/t_order_first.v0000644000542200017500000000250315101701376022122 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs fastclk ); input fastclk; t_netlist tnetlist (.also_fastclk (fastclk), /*AUTOINST*/ // Inputs .fastclk (fastclk)); endmodule module t_netlist (/*AUTOARG*/ // Inputs fastclk, also_fastclk ); // surefire lint_off ASWEMB input fastclk; input also_fastclk; integer _mode; initial _mode = 0; // This entire module should optimize to nearly nothing... reg [4:0] a,a2,b,c,d,e; initial a=5'd1; always @ (posedge fastclk) begin b <= a+5'd1; c <= b+5'd1; // Better for ordering if this moves before previous statement end always @ (d or /*AS*/a or c) begin e = d+5'd1; a2 = a+5'd1; // This can be pulled out of the middle of the always d = c+5'd1; // Better for ordering if this moves before previous statement end always @ (posedge also_fastclk) begin if (_mode==5) begin if (a2 != 5'd2) $stop; if (e != 5'd5) $stop; $write("*-* All Finished *-*\n"); $finish; end _mode <= _mode + 1; end endmodule verilator-5.042/test_regress/t/t_string_dyn_num.v0000644000542200017500000000370115101701376022640 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Use this file as a template for submitting bugs, etc. // This module takes a single clock input, and should either // $write("*-* All Finished *-*\n"); // $finish; // on success, or $stop. // // The code as shown applies a random vector to the Test // module, then calculates a CRC on the Test module's outputs. // // **If you do not wish for your code to be released to the public // please note it here, otherwise:** // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [31:0] istr; string sstr; string v; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d istr='%s' sstr='%s'\n", $time, cyc, istr, sstr); `endif cyc <= cyc + 1; sstr <= string'(istr); // Note takes another cycle if (cyc < 10) begin istr <= 32'h00_00_00_00; end else if (cyc == 13) begin // These displays are needed to check padding of %s $display("istr='%s' istr%%0='%0s' sstr='%s'", istr, istr, sstr); if (sstr.len() != 0) $stop; if (sstr != "") $stop; end else if (cyc == 20) begin istr <= 32'h00_00_41_00; end else if (cyc == 23) begin $display("istr='%s' istr%%0='%0s' sstr='%s'", istr, istr, sstr); if (sstr.len() != 1) $stop; if (sstr != "A") $stop; end else if (cyc == 30) begin istr <= 32'h42_00_41_00; end else if (cyc == 33) begin $display("istr='%s' istr%%0='%0s' sstr='%s'", istr, istr, sstr); if (sstr.len() != 2) $stop; if (sstr != "BA") $stop; end else if (cyc == 99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_array_compare.py0000755000542200017500000000073415101701376022616 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_real_cast.v0000644000542200017500000000157415101701376021544 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Confirm x randomization stability // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; typedef logic [85:0] big_t; localparam big_t foo = big_t'(8.531630271583128e+16); big_t bar; int cyc; real some_real; initial begin cyc = 0; some_real = 5.123; end always_comb bar = big_t'(some_real); always @(posedge clk) begin cyc <= cyc + 1; some_real <= some_real * 1.234e4; if (cyc == 6) begin if (foo != 86'd85316302715831280) $stop(); if (bar != 86'd18089031459271914704338944) $stop(); $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_param_no_parentheses.py0000755000542200017500000000073415101701376024167 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_preproc_undefineall.py0000755000542200017500000000075615101701376024016 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(v_flags2=['+define+PREDEF_COMMAND_LINE']) test.passes() verilator-5.042/test_regress/t/t_trace_string.v0000644000542200017500000000311415101701376022263 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; localparam string SVEC [0:7] = '{"zero", "one", "two", "three", "four", "five", "six", "seven"}; initial begin $display("%s", SVEC[3'd1]); $write("*-* All Finished *-*\n"); $finish; end localparam string REGX [0:31] = '{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0/fp", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6"}; function automatic string regx (logic [5-1:0] r, bit abi=1'b0); regx = abi ? REGX[r] : $sformatf("x%0d", r); endfunction: regx function string dis32 (logic [32-1:0] op); casez (op) 32'b0000_0000_0000_0000_0000_0000_0001_0011: dis32 = $sformatf("nop"); 32'b0000_0000_0000_0000_0100_0000_0011_0011: dis32 = $sformatf("-"); 32'b????_????_????_????_?000_????_?110_0111: dis32 = $sformatf("jalr %s, 0x%03x (%s)", regx(op[5-1:0]), op[16-1:0], regx(op[5-1:0])); default: dis32 = "illegal"; endcase endfunction: dis32 always @(posedge clk) begin for (int unsigned i=0; i<32; i++) $display("REGX: %s", regx(i[4:0])); $display("OP: %s", dis32(32'h00000000)); $finish(); end endmodule verilator-5.042/test_regress/t/t_mod_dup_bad.v0000644000542200017500000000047615101701376022044 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module a(); endmodule module test(); a a(); endmodule module a(); endmodule module b(); endmodule verilator-5.042/test_regress/t/t_case_enum_complete_wildcard.py0000755000542200017500000000077415101701376025476 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["--lint-only -Wwarn-CASEINCOMPLETE"]) test.passes() verilator-5.042/test_regress/t/t_interface_generic_modport_bad3.py0000755000542200017500000000102515101701376026055 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=['--timing'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface_generic_modport_param.v0000644000542200017500000000114715101701376026163 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 interface inf; localparam LPARAM = 12; int v; modport mp ( input v ); endinterface module GenericModule (interface.mp a); initial begin #1; if (a.LPARAM != 12) $stop; if (a.v != 7) $stop; end endmodule module t; inf inf_inst(); GenericModule genericModule (inf_inst); initial begin inf_inst.v = 7; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_randomize_method_types_unsup.py0000755000542200017500000000100415101701376025767 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_implicit_func_bad.out0000644000542200017500000000060215101701376024621 0ustar mahmoudyfreeshell%Error: t/t_lint_implicit_func_bad.v:12:11: Cannot call a task/void-function as a function: 'imp_func_conflict' : ... note: In instance 't' 12 | assign imp_func_conflict = 1'b1; | ^~~~~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_randomize_method.py0000755000542200017500000000073415101701376023322 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_vpi_memory.v0000644000542200017500000000363315101701376021773 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2010 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef USE_VPI_NOT_DPI //We call it via $c so we can verify DPI isn't required - see bug572 `else import "DPI-C" context function int mon_check(); `endif module t (/*AUTOARG*/ // Inputs clk ); `ifdef VERILATOR `systemc_header extern "C" int mon_check(); `verilog `endif input clk; typedef logic [31:0] word_t; reg [31:0] mem0 [16:1] /*verilator public_flat_rw @(posedge clk) */; reg [16:1] [31:0] memp32 /*verilator public_flat_rw @(posedge clk) */; reg [16:1] [30:0] memp31 /*verilator public_flat_rw @(posedge clk) */; reg [15:1] [32:0] memp33 /*verilator public_flat_rw @(posedge clk) */; word_t [16:1] memw /*verilator public_flat_rw @(posedge clk) */; integer i, status; `define CHECK_MEM(mem, words) \ for (i = words; i > 0; i--) \ if (integer'(mem[i]) !== i) begin \ $write("%%Error: %s[%d] : GOT = %d EXP = %d\n", `"mem`", i, mem[i], i); \ status = -1; \ end // Test loop initial begin `ifdef VERILATOR status = $c32("mon_check()"); `else status = $mon_check(); `endif `ifndef USE_VPI_NOT_DPI status = mon_check(); `endif if (status!=0) begin $write("%%Error: t_vpi_memory.cpp: C Test failed (rc=%0d)\n", status); $stop; end `CHECK_MEM(mem0, 16) `CHECK_MEM(memp32, 16) `CHECK_MEM(memp31, 16) `CHECK_MEM(memp33, 15) `CHECK_MEM(memw, 16) if (status!=0) begin $write("%%Error: Verilog memory checks failed\n"); $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule : t verilator-5.042/test_regress/t/t_func_tie_bad.out0000644000542200017500000000043215101701376022543 0ustar mahmoudyfreeshell%Error: t/t_func_tie_bad.v:11:15: Function/task output connected to constant instead of variable: 'b' 11 | func(0, 1'b1); | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_typedef_fwd.v0000644000542200017500000000211015101701376022072 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package P; `ifndef TEST_NO_TYPEDEFS typedef enum enum_t; typedef struct struct_t; typedef union union_t; typedef class ClsB; typedef interface class IfC; typedef generic_t; `endif class ClsA; enum_t m_e; // <--- Error need forward decl (if TEST_NO_TYPEDEFS) struct_t m_s; // <--- Error need forward decl (if TEST_NO_TYPEDEFS) union_t m_u; // <--- Error need forward decl (if TEST_NO_TYPEDEFS) ClsB m_b; // <--- Error need forward decl (if TEST_NO_TYPEDEFS) IfC m_i; // <--- Error need forward decl (if TEST_NO_TYPEDEFS) generic_t m_g; // <--- Error need forward decl (if TEST_NO_TYPEDEFS) endclass typedef enum {N = 0} enum_t; typedef struct packed {int s;} struct_t; typedef union packed {int s;} union_t; class ClsB; endclass interface class IfC; endclass typedef int generic_t; endpackage module t; endmodule verilator-5.042/test_regress/t/t_interface_generic_positional.py0000755000542200017500000000077115101701376025670 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--timing']) test.execute() test.passes() verilator-5.042/test_regress/t/t_inst_tree_inl1_pub0.vlt0000644000542200017500000000036115101701376024005 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. // SPDX-License-Identifier: CC0-1.0 `verilator_config inline -module "l*" verilator-5.042/test_regress/t/t_class_extern.v0000644000542200017500000000446215101701376022300 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls; int value; extern function int ext_f_np; extern function int ext_f_p(); extern function int ext_f_i(int in); extern function ext_f_imp(in); extern static function int get_1(); extern task ext_t_np; extern task ext_t_p(); extern task ext_t_i(int in); class SubCls; int value; extern function int ext_f_np; extern function int ext_f_p(); extern function int ext_f_i(int in); extern static function int get_10(); extern task ext_t_np; extern task ext_t_p(); extern task ext_t_i(int in); endclass endclass function int Cls::ext_f_np; return 1; endfunction function int Cls::ext_f_p(); return value; endfunction function int Cls::ext_f_i(int in); return in+1; endfunction function Cls::ext_f_imp(in); return ~in; endfunction function int Cls::get_1(); return 1; endfunction task Cls::ext_t_np(); $write("*-* All Finished *-*\n"); endtask task Cls::ext_t_p(); $finish; endtask task Cls::ext_t_i(int in); if (in != 2) $stop; value = in; endtask function int Cls::SubCls::ext_f_np; return 10; endfunction function int Cls::SubCls::ext_f_p(); return value; endfunction function int Cls::SubCls::ext_f_i(int in); return in+10; endfunction function int Cls::SubCls::get_10(); return 10; endfunction task Cls::SubCls::ext_t_np(); $write("Cls::SubCls::ext_t_np\n"); endtask task Cls::SubCls::ext_t_p(); $write("Cls::SubCls::ext_t_p\n"); endtask task Cls::SubCls::ext_t_i(int in); if (in != 20) $stop; value = in; endtask module t; initial begin Cls c = new; Cls::SubCls subc = new; c.ext_t_i(2); if (c.ext_f_np() != 1) $stop; if (c.ext_f_p() != 2) $stop; if (c.ext_f_i(10) != 11) $stop; if (c.ext_f_imp(1'b1) != 1'b0) $stop; if (Cls::get_1() != 1) $stop; subc.ext_t_i(20); if (subc.ext_f_np() != 10) $stop; if (subc.ext_f_p() != 20) $stop; if (subc.ext_f_i(11) != 21) $stop; if (Cls::SubCls::get_10() != 10) $stop; subc.ext_t_np(); subc.ext_t_p(); c.ext_t_np(); c.ext_t_p(); end endmodule verilator-5.042/test_regress/t/t_class_param_rewrite.py0000755000542200017500000000073415101701376024020 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_array_fst.py0000755000542200017500000000120615101701376023135 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_trace_array.v" test.compile(verilator_flags2=['--cc --trace-fst --trace-structs --trace-max-width 0']) test.execute() test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_covergroup_unsup.out0000644000542200017500000005405715101701376023602 0ustar mahmoudyfreeshell%Warning-COVERIGN: t/t_covergroup_unsup.v:32:4: Ignoring unsupported: covergroup 32 | covergroup cg_empty; | ^~~~~~~~~~ ... For warning description see https://verilator.org/warn/COVERIGN?v=latest ... Use "/* verilator lint_off COVERIGN */" and lint_on around source to disable this message. %Warning-COVERIGN: t/t_covergroup_unsup.v:36:7: Ignoring unsupported: coverage option 36 | type_option.weight = 1; | ^~~~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:37:7: Ignoring unsupported: coverage option 37 | type_option.goal = 99; | ^~~~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:38:7: Ignoring unsupported: coverage option 38 | type_option.comment = "type_option_comment"; | ^~~~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:39:7: Ignoring unsupported: coverage option 39 | type_option.strobe = 0; | ^~~~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:40:7: Ignoring unsupported: coverage option 40 | type_option.merge_instances = 1; | ^~~~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:41:7: Ignoring unsupported: coverage option 41 | type_option.distribute_first = 1; | ^~~~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:42:7: Ignoring unsupported: coverage option 42 | option.name = "the_name"; | ^~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:43:7: Ignoring unsupported: coverage option 43 | option.weight = 1; | ^~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:44:7: Ignoring unsupported: coverage option 44 | option.goal = 98; | ^~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:45:7: Ignoring unsupported: coverage option 45 | option.comment = "option_comment"; | ^~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:46:7: Ignoring unsupported: coverage option 46 | option.at_least = 20; | ^~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:47:7: Ignoring unsupported: coverage option 47 | option.auto_bin_max = 10; | ^~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:48:7: Ignoring unsupported: coverage option 48 | option.cross_num_print_missing = 2; | ^~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:49:7: Ignoring unsupported: coverage option 49 | option.detect_overlap = 1; | ^~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:50:7: Ignoring unsupported: coverage option 50 | option.per_instance = 1; | ^~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:51:7: Ignoring unsupported: coverage option 51 | option.get_inst_coverage = 1; | ^~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:35:4: Ignoring unsupported: covergroup 35 | covergroup cg_opt; | ^~~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:54:34: Ignoring unsupported: coverage clocking event 54 | covergroup cg_clockingevent() @(posedge clk); | ^ %Warning-COVERIGN: t/t_covergroup_unsup.v:54:4: Ignoring unsupported: covergroup 54 | covergroup cg_clockingevent() @(posedge clk); | ^~~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:56:4: Ignoring unsupported: covergroup 56 | covergroup cg_withfunction() with function sample (a); | ^~~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:58:25: Ignoring unsupported: coverage '@@' events 58 | covergroup cg_atat() @@ (begin funca or end funcb); | ^~ %Warning-COVERIGN: t/t_covergroup_unsup.v:58:4: Ignoring unsupported: covergroup 58 | covergroup cg_atat() @@ (begin funca or end funcb); | ^~~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:60:4: Ignoring unsupported: covergroup 60 | covergroup cg_bracket; | ^~~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:64:9: Ignoring unsupported: coverage option 64 | { option.name = "option"; } | ^~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:63:4: Ignoring unsupported: covergroup 63 | covergroup cg_bracket2; | ^~~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:67:7: Ignoring unsupported: coverpoint 67 | coverpoint a; | ^~~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:66:4: Ignoring unsupported: covergroup 66 | covergroup cg_cp; | ^~~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:70:20: Ignoring unsupported: cover 'iff' 70 | coverpoint a iff (b); | ^~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:70:7: Ignoring unsupported: coverpoint 70 | coverpoint a iff (b); | ^~~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:69:4: Ignoring unsupported: covergroup 69 | covergroup cg_cp_iff; | ^~~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:73:24: Ignoring unsupported: cover 'iff' 73 | id: coverpoint a iff (b); | ^~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:73:11: Ignoring unsupported: coverpoint 73 | id: coverpoint a iff (b); | ^~~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:72:4: Ignoring unsupported: covergroup 72 | covergroup cg_id_cp_iff; | ^~~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:76:28: Ignoring unsupported: cover 'iff' 76 | int id: coverpoint a iff (b); | ^~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:76:15: Ignoring unsupported: coverpoint 76 | int id: coverpoint a iff (b); | ^~~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:75:4: Ignoring unsupported: covergroup 75 | covergroup cg_id_cp_id1; | ^~~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:79:32: Ignoring unsupported: cover 'iff' 79 | var int id: coverpoint a iff (b); | ^~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:79:19: Ignoring unsupported: coverpoint 79 | var int id: coverpoint a iff (b); | ^~~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:78:4: Ignoring unsupported: covergroup 78 | covergroup cg_id_cp_id2; | ^~~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:82:34: Ignoring unsupported: cover 'iff' 82 | var [3:0] id: coverpoint a iff (b); | ^~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:82:21: Ignoring unsupported: coverpoint 82 | var [3:0] id: coverpoint a iff (b); | ^~~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:81:4: Ignoring unsupported: covergroup 81 | covergroup cg_id_cp_id3; | ^~~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:85:30: Ignoring unsupported: cover 'iff' 85 | [3:0] id: coverpoint a iff (b); | ^~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:85:17: Ignoring unsupported: coverpoint 85 | [3:0] id: coverpoint a iff (b); | ^~~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:84:4: Ignoring unsupported: covergroup 84 | covergroup cg_id_cp_id4; | ^~~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:88:31: Ignoring unsupported: cover 'iff' 88 | signed id: coverpoint a iff (b); | ^~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:88:18: Ignoring unsupported: coverpoint 88 | signed id: coverpoint a iff (b); | ^~~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:87:4: Ignoring unsupported: covergroup 87 | covergroup cg_id_cp_id5; | ^~~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:92:18: Ignoring unsupported: cover 'iff' 92 | cross a, b iff (!rst); | ^~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:92:7: Ignoring unsupported: cover cross 92 | cross a, b iff (!rst); | ^~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:91:4: Ignoring unsupported: covergroup 91 | covergroup cg_cross; | ^~~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:95:18: Ignoring unsupported: cover 'iff' 95 | cross a, b iff (!rst) {} | ^~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:95:7: Ignoring unsupported: cover cross 95 | cross a, b iff (!rst) {} | ^~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:94:4: Ignoring unsupported: covergroup 94 | covergroup cg_cross2; | ^~~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:98:20: Ignoring unsupported: coverage option 98 | cross a, b { option.comment = "cross"; option.weight = 12; } | ^~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:98:46: Ignoring unsupported: coverage option 98 | cross a, b { option.comment = "cross"; option.weight = 12; } | ^~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:98:7: Ignoring unsupported: cover cross 98 | cross a, b { option.comment = "cross"; option.weight = 12; } | ^~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:97:4: Ignoring unsupported: covergroup 97 | covergroup cg_cross3; | ^~~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:102:24: Ignoring unsupported: coverage cross 'function' declaration 102 | function void crossfunc; endfunction | ^~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:103:21: Ignoring unsupported: coverage select function call 103 | bins one = crossfunc(); | ^~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:103:10: Ignoring unsupported: coverage cross bin 103 | bins one = crossfunc(); | ^~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:101:7: Ignoring unsupported: cover cross 101 | cross a, b { | ^~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:100:4: Ignoring unsupported: covergroup 100 | covergroup cg_cross4; | ^~~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:107:28: Ignoring unsupported: cover 'iff' 107 | my_cg_id: cross a, b iff (!rst); | ^~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:107:17: Ignoring unsupported: cover cross 107 | my_cg_id: cross a, b iff (!rst); | ^~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:106:4: Ignoring unsupported: covergroup 106 | covergroup cg_cross_id; | ^~~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:112:17: Ignoring unsupported: cover bin specification 112 | { bins ba = {a}; } | ^ %Warning-COVERIGN: t/t_covergroup_unsup.v:113:24: Ignoring unsupported: cover 'iff' 113 | { bins bar = {a} iff (!rst); } | ^~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:113:18: Ignoring unsupported: cover bin specification 113 | { bins bar = {a} iff (!rst); } | ^ %Warning-COVERIGN: t/t_covergroup_unsup.v:114:26: Ignoring unsupported: cover bin specification 114 | { illegal_bins ila = {a}; } | ^ %Warning-COVERIGN: t/t_covergroup_unsup.v:115:25: Ignoring unsupported: cover bin specification 115 | { ignore_bins iga = {a}; } | ^ %Warning-COVERIGN: t/t_covergroup_unsup.v:117:19: Ignoring unsupported: cover bin specification 117 | { bins ba[] = {a}; } | ^ %Warning-COVERIGN: t/t_covergroup_unsup.v:118:20: Ignoring unsupported: cover bin specification 118 | { bins ba[2] = {a}; } | ^ %Warning-COVERIGN: t/t_covergroup_unsup.v:120:23: Ignoring unsupported: cover bin 'with' specification 120 | { bins ba = {a} with { b }; } | ^~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:122:27: Ignoring unsupported: cover bin 'wildcard' specification 122 | { wildcard bins bwa = {a}; } | ^ %Warning-COVERIGN: t/t_covergroup_unsup.v:123:34: Ignoring unsupported: cover bin 'wildcard' 'with' specification 123 | { wildcard bins bwaw = {a} with { b }; } | ^~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:125:20: Ignoring unsupported: cover bin 'default' 125 | { bins def = default; } | ^~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:126:29: Ignoring unsupported: cover bin 'default' 'sequence' 126 | { bins defs = default sequence; } | ^~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:128:18: Ignoring unsupported: cover bin trans list 128 | { bins bts = ( 1, 2 ); } | ^ %Warning-COVERIGN: t/t_covergroup_unsup.v:129:9: Ignoring unsupported: cover bin 'wildcard' trans list 129 | { wildcard bins wbts = ( 1, 2 ); } | ^~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:130:33: Ignoring unsupported: covergroup value range 130 | { bins bts2 = ( 2, 3 ), ( [5:6] ), ( [5 +/- 2] ), ( [ 5 +%- 20.0] ) ; } | ^ %Warning-COVERIGN: t/t_covergroup_unsup.v:130:44: Ignoring unsupported: covergroup value range 130 | { bins bts2 = ( 2, 3 ), ( [5:6] ), ( [5 +/- 2] ), ( [ 5 +%- 20.0] ) ; } | ^ %Warning-COVERIGN: t/t_covergroup_unsup.v:130:59: Ignoring unsupported: covergroup value range 130 | { bins bts2 = ( 2, 3 ), ( [5:6] ), ( [5 +/- 2] ), ( [ 5 +%- 20.0] ) ; } | ^ %Warning-COVERIGN: t/t_covergroup_unsup.v:130:19: Ignoring unsupported: cover bin trans list 130 | { bins bts2 = ( 2, 3 ), ( [5:6] ), ( [5 +/- 2] ), ( [ 5 +%- 20.0] ) ; } | ^ %Warning-COVERIGN: t/t_covergroup_unsup.v:132:27: Ignoring unsupported: cover trans set '=>' 132 | { bins bts2 = ( 1,5 => 6,7 ) ; } | ^~ %Warning-COVERIGN: t/t_covergroup_unsup.v:132:19: Ignoring unsupported: cover bin trans list 132 | { bins bts2 = ( 1,5 => 6,7 ) ; } | ^ %Warning-COVERIGN: t/t_covergroup_unsup.v:133:25: Ignoring unsupported: cover '[*' 133 | { bins bts2 = ( 3 [*5] ) ; } | ^~ %Warning-COVERIGN: t/t_covergroup_unsup.v:133:19: Ignoring unsupported: cover bin trans list 133 | { bins bts2 = ( 3 [*5] ) ; } | ^ %Warning-COVERIGN: t/t_covergroup_unsup.v:134:25: Ignoring unsupported: cover '[*' 134 | { bins bts2 = ( 3 [*5:6] ) ; } | ^~ %Warning-COVERIGN: t/t_covergroup_unsup.v:134:19: Ignoring unsupported: cover bin trans list 134 | { bins bts2 = ( 3 [*5:6] ) ; } | ^ %Warning-COVERIGN: t/t_covergroup_unsup.v:135:25: Ignoring unsupported: cover '[->' 135 | { bins bts2 = ( 3 [->5] ) ; } | ^~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:135:19: Ignoring unsupported: cover bin trans list 135 | { bins bts2 = ( 3 [->5] ) ; } | ^ %Warning-COVERIGN: t/t_covergroup_unsup.v:136:25: Ignoring unsupported: cover '[->' 136 | { bins bts2 = ( 3 [->5:6] ) ; } | ^~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:136:19: Ignoring unsupported: cover bin trans list 136 | { bins bts2 = ( 3 [->5:6] ) ; } | ^ %Warning-COVERIGN: t/t_covergroup_unsup.v:137:25: Ignoring unsupported: cover '[=' 137 | { bins bts2 = ( 3 [=5] ) ; } | ^~ %Warning-COVERIGN: t/t_covergroup_unsup.v:137:19: Ignoring unsupported: cover bin trans list 137 | { bins bts2 = ( 3 [=5] ) ; } | ^ %Warning-COVERIGN: t/t_covergroup_unsup.v:138:25: Ignoring unsupported: cover '[=' 138 | { bins bts2 = ( 3 [=5:6] ) ; } | ^~ %Warning-COVERIGN: t/t_covergroup_unsup.v:138:19: Ignoring unsupported: cover bin trans list 138 | { bins bts2 = ( 3 [=5:6] ) ; } | ^ %Warning-COVERIGN: t/t_covergroup_unsup.v:110:4: Ignoring unsupported: covergroup 110 | covergroup cg_binsoroptions_bk1; | ^~~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:144:23: Ignoring unsupported: coverage select expression 'binsof' 144 | bins bin_a = binsof(a); | ^~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:144:10: Ignoring unsupported: coverage cross bin 144 | bins bin_a = binsof(a); | ^~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:145:24: Ignoring unsupported: coverage select expression 'binsof' 145 | bins bin_ai = binsof(a) iff (!rst); | ^~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:145:34: Ignoring unsupported: cover 'iff' 145 | bins bin_ai = binsof(a) iff (!rst); | ^~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:145:10: Ignoring unsupported: coverage cross bin 145 | bins bin_ai = binsof(a) iff (!rst); | ^~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:146:23: Ignoring unsupported: coverage select expression 'binsof' 146 | bins bin_c = binsof(cp.x); | ^~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:146:10: Ignoring unsupported: coverage cross bin 146 | bins bin_c = binsof(cp.x); | ^~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:147:24: Ignoring unsupported: coverage select expression 'binsof' 147 | bins bin_na = ! binsof(a); | ^ %Warning-COVERIGN: t/t_covergroup_unsup.v:147:10: Ignoring unsupported: coverage cross bin 147 | bins bin_na = ! binsof(a); | ^~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:149:33: Ignoring unsupported: coverage select expression 'intersect' 149 | bins bin_d = binsof(a) intersect { b }; | ^~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:149:10: Ignoring unsupported: coverage cross bin 149 | bins bin_d = binsof(a) intersect { b }; | ^~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:150:34: Ignoring unsupported: coverage select expression 'intersect' 150 | bins bin_nd = ! binsof(a) intersect { b }; | ^ %Warning-COVERIGN: t/t_covergroup_unsup.v:150:10: Ignoring unsupported: coverage cross bin 150 | bins bin_nd = ! binsof(a) intersect { b }; | ^~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:152:23: Ignoring unsupported: coverage select expression with 152 | bins bin_e = with (a); | ^~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:152:10: Ignoring unsupported: coverage cross bin 152 | bins bin_e = with (a); | ^~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:153:27: Ignoring unsupported: coverage select expression with 153 | bins bin_not_e = ! with (a); | ^ %Warning-COVERIGN: t/t_covergroup_unsup.v:153:10: Ignoring unsupported: coverage cross bin 153 | bins bin_not_e = ! with (a); | ^~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:155:26: Ignoring unsupported: coverage select expression 'binsof' 155 | bins bin_par = (binsof(a)); | ^~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:155:10: Ignoring unsupported: coverage cross bin 155 | bins bin_par = (binsof(a)); | ^~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:156:25: Ignoring unsupported: coverage select expression 'binsof' 156 | bins bin_and = binsof(a) && binsof(b); | ^~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:156:38: Ignoring unsupported: coverage select expression 'binsof' 156 | bins bin_and = binsof(a) && binsof(b); | ^~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:156:35: Ignoring unsupported: coverage select expression '&&' 156 | bins bin_and = binsof(a) && binsof(b); | ^~ %Warning-COVERIGN: t/t_covergroup_unsup.v:156:10: Ignoring unsupported: coverage cross bin 156 | bins bin_and = binsof(a) && binsof(b); | ^~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:157:24: Ignoring unsupported: coverage select expression 'binsof' 157 | bins bin_or = binsof(a) || binsof(b); | ^~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:157:37: Ignoring unsupported: coverage select expression 'binsof' 157 | bins bin_or = binsof(a) || binsof(b); | ^~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:157:34: Ignoring unsupported: coverage select expression '||' 157 | bins bin_or = binsof(a) || binsof(b); | ^~ %Warning-COVERIGN: t/t_covergroup_unsup.v:157:10: Ignoring unsupported: coverage cross bin 157 | bins bin_or = binsof(a) || binsof(b); | ^~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:143:7: Ignoring unsupported: cover cross 143 | cross a, b { | ^~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:142:4: Ignoring unsupported: covergroup 142 | covergroup cg_cross_bins; | ^~~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:161:4: Ignoring unsupported: covergroup 161 | covergroup cgArgs(int cg_lim); | ^~~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:168:23: Ignoring unsupported: coverage clocking event 168 | covergroup cov1 @m_z; | ^ %Warning-COVERIGN: t/t_covergroup_unsup.v:169:10: Ignoring unsupported: coverpoint 169 | coverpoint m_x; | ^~~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:170:10: Ignoring unsupported: coverpoint 170 | coverpoint m_y; | ^~~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:168:7: Ignoring unsupported: covergroup 168 | covergroup cov1 @m_z; | ^~~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:178:7: Ignoring unsupported: covergroup 178 | covergroup extends cg_empty; | ^~~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_string.py0000755000542200017500000000073415101701376021300 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_eofnewline_bad.py0000755000542200017500000000165515101701376023764 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = test.obj_dir + "/t_lint_eofnewline_bad.v" def gen(filename): with open(filename, 'w', encoding="utf8") as fh: fh.write("// Generated by t_lint_eofnewline_bad.py\n") fh.write("module t;\n") fh.write("// No newline below:\n") fh.write("endmodule") # Intentionally no newline gen(test.top_filename) test.lint(verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_pp_defkwd_bad.py0000755000542200017500000000076615101701376022550 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_gen_intdot.py0000755000542200017500000000077415101701376022130 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--no-timing"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_altera_lpm_constant.py0000755000542200017500000000111115101701376024011 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) test.compile(verilator_flags2=["--top-module", module]) test.passes() verilator-5.042/test_regress/t/t_implements_new_bad.v0000644000542200017500000000057315101701376023441 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface class Icls; endclass module t; Icls c; initial begin c = new; // Bad $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_flag_timescale_override.out0000644000542200017500000000012115101701376024772 0ustar mahmoudyfreeshellTime scale of t is 1ms / 1us Time scale of sub is 1ms / 1us *-* All Finished *-* verilator-5.042/test_regress/t/t_dfg_regularize_driver_of_sc_var.v0000644000542200017500000000057215101701376026171 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module sub(input in, output out); assign out = in; endmodule module top(input clk, output out); logic one = '1; sub sub_inst(.in(one), .out(out)); endmodule verilator-5.042/test_regress/t/t_trace_dumpvars_dyn_vcd_1.py0000755000542200017500000000134615101701376024737 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_trace_dumpvars_dyn.cpp" test.top_filename = "t/t_trace_dumpvars_dyn.v" test.compile(make_main=False, verilator_flags2=["--trace-vcd --exe", test.pli_filename, "-CFLAGS -DVL_DEBUG"]) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_func_ref_arg.v0000644000542200017500000000234315101701376022222 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); class MyInt; int x; function new(int a); x = a; endfunction endclass function int get_val_set_5(ref int x); automatic int y = x; x = 5; return y; endfunction class Cls; function int get_val_set_2(ref int x); automatic int y = x; x = 2; return y; endfunction endclass module t; int a, b; int arr[1]; Cls cls; MyInt mi; initial begin a = 10; b = get_val_set_5(a); `checkh(a, 5); `checkh(b, 10); cls = new; b = cls.get_val_set_2(a); `checkh(a, 2); `checkh(b, 5); mi = new(1); b = cls.get_val_set_2(mi.x); `checkh(mi.x, 2); `checkh(b, 1); arr[0] = 10; b = cls.get_val_set_2(arr[0]); `checkh(arr[0], 2); `checkh(b, 10); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_uniqueif_else.v0000644000542200017500000000223015101701376022432 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilog_format: off `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); // verilog_format: on module t; logic clk; logic A, B, C; logic reset; logic x; always #1 clk = ~clk; initial begin clk = 0; reset = 0; A = 0; B = 0; C = 0; #10; reset = 1; #2; A = 1; #2; `checkd(x, 1'b0); #2; B = 1; #2; `checkd(x, 1'b0); #2; B = 0; C = 1; #2; `checkd(x, 1'b1); #10; $finish; end always_ff @(posedge clk or negedge reset) begin if (!reset) begin x <= '0; end else if (A) begin unique if (B) begin x <= '0; end else if (C) begin x <= '1; end // This passes: // else begin end else; // For unique if to not have a false positive end end endmodule verilator-5.042/test_regress/t/t_emit_memb_limit.py0000755000542200017500000000337315101701376023130 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap # Very slow on vltmt, and doesn't test much of value there, so disabled test.scenarios('vlt') test.top_filename = test.obj_dir + "/t_emit_memb_limit.v" def gen(filename, n): with open(filename, 'w', encoding="utf8") as fh: fh.write("// Generated by t_emit_memb_limit.py\n") fh.write("module t (i, clk, o);\n") fh.write(" input clk;\n") fh.write(" input i;\n") fh.write(" output logic o;\n") for i in range(0, n + 1): fh.write(" logic r" + str(i) + ";\n") fh.write(" always @ (posedge clk) begin\n") fh.write(" r0 <= i;\n") for i in range(1, n): fh.write(" r" + str(i + 1) + " <= r" + str(i) + ";\n") fh.write(" o <= r" + str(n) + ";\n") fh.write(' $write("*-* All Finished *-*\\n");' + "\n") fh.write(' $finish;' + "\n") fh.write(" end\n") fh.write("endmodule\n") # Current limit is 50, so want to test at least 50*50 cases gen(test.top_filename, 6000) test.compile(verilator_flags2=[ "-x-assign fast --x-initial fast", "-Wno-UNOPTTHREADS", # The slow V3Partition asserts are just too slow # in this test. They're disabled just for performance # reasons: "--no-debug-partition" ]) test.execute() test.file_grep(test.obj_dir + "/" + test.vm_prefix + "___024root.h", r'struct \{') test.passes() verilator-5.042/test_regress/t/t_assert_imm_nz_bad.v0000644000542200017500000000050415101701376023257 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ clk ); input clk; labeled_imas: assert #1 (clk); // BAD: #1 endmodule verilator-5.042/test_regress/t/t_gated_clk_1.py0000755000542200017500000000073415101701376022127 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_config_unsup.py0000755000542200017500000000077315101701376022474 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_implicit_func_bad.v0000644000542200017500000000053215101701376024261 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; function void imp_func_conflict(); endfunction `default_nettype wire assign imp_func_conflict = 1'b1; endmodule verilator-5.042/test_regress/t/t_constraint_dist.py0000755000542200017500000000111515101701376023173 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile(verilator_flags2=['-Wno-CONSTRAINTIGN']) test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_binary.out0000644000542200017500000000035015101701376022602 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module t $end $var wire 32 # sig [31:0] $end $upscope $end $enddefinitions $end #0 b00000000000000000000000000001010 # #20 b00000000000000000000000000010100 # verilator-5.042/test_regress/t/t_stop_bad.out0000644000542200017500000000010615101701376021732 0ustar mahmoudyfreeshellIntentional stop %Error: t/t_stop_bad.v:10: Verilog $stop Aborting... verilator-5.042/test_regress/t/t_queue_empty_pin.py0000755000542200017500000000073415101701376023202 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_local.v0000644000542200017500000000566515101701376022073 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls; typedef enum {A = 10, B = 20, C = 30} en_t; int m_pub = 1; local int m_loc = 2; protected int m_prot = B; task f_pub; endtask local task f_loc; endtask protected task f_prot; endtask static task s_pub; endtask static local task s_loc; endtask static protected task s_prot; endtask task check; Cls o; if (m_pub != 1) $stop; if (m_loc != 2) $stop; if (m_prot != 20) $stop; f_pub(); // Ok f_loc(); // Ok f_prot(); // Ok s_pub(); // Ok s_loc(); // Ok s_prot(); // Ok Cls::s_pub(); // Ok Cls::s_loc(); // Ok Cls::s_prot(); // Ok endtask class InnerCls; typedef enum {A = 10, B = 20, C = 30} en_t; int m_pub = 1; local int m_loc = 2; protected int m_prot = B; task f_pub; endtask local task f_loc; endtask protected task f_prot; endtask static task s_pub; endtask static local task s_loc; endtask static protected task s_prot; endtask task check; Cls o; if (m_pub != 1) $stop; if (m_loc != 2) $stop; if (m_prot != 20) $stop; f_pub(); // Ok f_loc(); // Ok f_prot(); // Ok s_pub(); // Ok s_loc(); // Ok s_prot(); // Ok Cls::s_pub(); // Ok Cls::s_loc(); // Ok Cls::s_prot(); // Ok endtask endclass endclass class Ext extends Cls; task check; if (m_pub != 1) $stop; if (m_prot != 20) $stop; f_pub(); // Ok f_prot(); // Ok s_pub(); // Ok s_prot(); // Ok Cls::s_pub(); // Ok Cls::s_prot(); // Ok endtask class ExtInner extends Cls::InnerCls; task check; if (m_pub != 1) $stop; if (m_prot != 20) $stop; f_pub(); // Ok f_prot(); // Ok s_pub(); // Ok s_prot(); // Ok Cls::InnerCls::s_pub(); // Ok Cls::InnerCls::s_prot(); // Ok endtask endclass endclass module t; const Cls mod_c = new; const Cls::InnerCls imod_c = new; initial begin Cls c; Cls::InnerCls i; Ext e; Ext::ExtInner ei; if (c.A != 10) $stop; if (i.A != 10) $stop; c = new; i = new; e = new; ei = new; if (c.m_pub != 1) $stop; if (i.m_pub != 1) $stop; // if (mod_c.A != 10) $stop; if (imod_c.A != 10) $stop; // c.check(); i.check(); e.check(); ei.check(); // Cls::s_pub(); // Ok Cls::InnerCls::s_pub(); // Ok c.s_pub(); // Ok i.s_pub(); // Ok e.s_pub(); // Ok ei.s_pub(); // Ok // $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_array_method_map.v0000644000542200017500000000126115101701376023113 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); module t; initial begin int res[]; int a[3] = '{100, 200, 300}; // TODO results not known to be correct res = a.map(el) with (el == 200); `checkh(res.size, 3); `checkh(res[0], 0); `checkh(res[1], 1); `checkh(res[2], 0); end endmodule verilator-5.042/test_regress/t/t_json_only_output.v0000644000542200017500000000042215101701376023230 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module m (input clk); // verilator tag foo_op endmodule verilator-5.042/test_regress/t/t_math_real.v0000644000542200017500000002264215101701376021542 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `define stop $stop `define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define is_near_real(a,b) (( ((a)<(b)) ? (b)-(a) : (a)-(b)) < (((a)/(b))*0.0001)) module t (/*AUTOARG*/ // Inputs clk ); input clk; integer i; reg [63:0] b; reg [47:0] i48; reg signed [47:0] is48; reg [31:0] ci32; reg signed [31:0] cis32; reg [47:0] ci48; reg signed [47:0] cis48; reg [63:0] ci64; reg signed [63:0] cis64; reg [95:0] ci96; reg signed [95:0] cis96; real r, r2; integer cyc = 0; string s; realtime uninit; initial if (uninit != 0.0) $stop; localparam int TWENTY = 20; localparam real TWENDIV = $ceil((real'(TWENTY)-14.0)/2.0); sub_cast_bug374 sub (.cyc5(cyc[4:0]), .*); initial begin if (1_00_0.0_1 != 1000.01) $stop; // rtoi truncates if ($rtoi(36.7) != 36) $stop; if ($rtoi(36.5) != 36) $stop; if ($rtoi(36.4) != 36) $stop; // casting rounds if ((integer '(36.7)) != 37) $stop; if ((integer '(36.5)) != 37) $stop; if ((integer '(36.4)) != 36) $stop; // assignment rounds // verilator lint_off REALCVT i = 36.7; if (i != 37) $stop; i = 36.5; if (i != 37) $stop; i = 36.4; if (i != 36) $stop; r = 10'd38; if (r!=38.0) $stop; // verilator lint_on REALCVT // operators if ((-(1.5)) != -1.5) $stop; if ((+(1.5)) != 1.5) $stop; if (((1.5)+(1.25)) != 2.75) $stop; if (((1.5)-(1.25)) != 0.25) $stop; if (((1.5)*(1.25)) != 1.875) $stop; if (((1.5)/(1.25)) != 1.2) $stop; // if (((1.5)==(2)) != 1'b0) $stop; // note 2 becomes real 2.0 if (((1.5)!=(2)) != 1'b1) $stop; if (((1.5)> (2)) != 1'b0) $stop; if (((1.5)>=(2)) != 1'b0) $stop; if (((1.5)< (2)) != 1'b1) $stop; if (((1.5)<=(2)) != 1'b1) $stop; if (((1.5)==(1.5)) != 1'b1) $stop; if (((1.5)!=(1.5)) != 1'b0) $stop; if (((1.5)> (1.5)) != 1'b0) $stop; if (((1.5)>=(1.5)) != 1'b1) $stop; if (((1.5)< (1.5)) != 1'b0) $stop; if (((1.5)<=(1.5)) != 1'b1) $stop; if (((1.6)==(1.5)) != 1'b0) $stop; if (((1.6)!=(1.5)) != 1'b1) $stop; if (((1.6)> (1.5)) != 1'b1) $stop; if (((1.6)>=(1.5)) != 1'b1) $stop; if (((1.6)< (1.5)) != 1'b0) $stop; if (((1.6)<=(1.5)) != 1'b0) $stop; // if (((0.0)?(2.0):(1.1)) != 1.1) $stop; if (((1.5)?(2.0):(1.1)) != 2.0) $stop; // if (!1.7) $stop; if (!(!0.0)) $stop; if (1.8 && 0.0) $stop; if (!(1.8 || 0.0)) $stop; // i=0; for (r=1.0; r<2.0; r=r+0.1) i++; if (i!=10) $stop; // bug ci64 = $realtobits(1.444); if (ci64 != 64'h3ff71a9fbe76c8b4) $stop; r = $bitstoreal(64'h3ff71a9fbe76c8b4); if (r != 1.444) $stop; r = $bitstoreal($realtobits(1.414)); if (r != 1.414) $stop; // bug r = 32'bxz000_111; // 7 accoding to IEEE if (r != 7) $stop; // bug b = 64'h7fe8000000000000; $display("%6.3f", $bitstoreal(b)); // bug i48 = 48'hff00_00000000; r = real'(i48); if (r != 280375465082880.0) $stop; r = $itor(i48); if (r != 280375465082880.0) $stop; is48 = 48'shff00_00000000; r = real'(is48); if (r != -1099511627776.0) $stop; r = $itor(is48); if (r != -1099511627776.0) $stop; r = 0; r = i48; if (r != 280375465082880.0) $stop; r = 0; r = $itor(-10); if (r != -10.0) $stop; r = real'(4'sb1111); if (r != -1) $stop; r = $itor(4'sb1111); if (r != -1) $stop; r = real'(4'b1111); if (r != 15) $stop; r = $itor(4'b1111); if (r != 15) $stop; r = real'(96'hf0000000_00000000_00000000); if (r != 74276402357122816493947453440.0) $stop; r = real'(96'shf0000000_00000000_00000000); if (r != -4951760157141521099596496896.0) $stop; r = 1.5; if (r++ != 1.5) $stop; if (r != 2.5) $stop; if (r-- != 2.5) $stop; if (r != 1.5) $stop; if (++r != 2.5) $stop; if (r != 2.5) $stop; if (--r != 1.5) $stop; if (r != 1.5) $stop; r = 1.23456; s = $sformatf("%g", r); `checks(s, "1.23456"); r = 1.0/0; // inf s = $sformatf("%g", r); `checks(s, "inf"); r = -1.0/0; // -inf s = $sformatf("%g", r); `checks(s, "-inf"); r = $sqrt(-1.0); // NaN s = $sformatf("%g", r); if (s == "-nan") s = "nan"; `checks(s, "nan"); r = -$sqrt(-1.0); // NaN s = $sformatf("%g", r); if (s == "-nan") s = "nan"; `checks(s, "nan"); if (real'(TWENTY) != 20.0) $stop; if (TWENDIV != 3.0) $stop; end // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d\n", $time, cyc); `endif cyc <= cyc + 1; if (cyc==0) begin // Setup ci48 <= '0; cis48 <= '0; ci96 <= '0; cis96 <= '0; end else if (cyc == 1) begin ci48 <= 48'hff00_00000000; cis48 <= 48'shff00_00000000; ci96 <= 96'hf0000000_00000000_00000000; cis96 <= 96'shf0000000_00000000_00000000; end else if (cyc<80) begin if ($time != {32'h0, $rtoi($realtime)}) $stop; if ($itor(cyc) != cyc) $stop; //Unsup: if ((real `($time)) != $realtime) $stop; r = $itor(cyc*2); i = $rtoi(r); if (i!=cyc*2) $stop; // r = $itor(cyc)/1.5; b = $realtobits(r); r2 = $bitstoreal(b); if (r != r2) $stop; // // Trust the integer math as a comparison r = $itor(cyc); if ($rtoi(-r) != -cyc) $stop; if ($rtoi(+r) != cyc) $stop; if ($rtoi(r+2.0) != (cyc+2)) $stop; if ($rtoi(r-2.0) != (cyc-2)) $stop; if ($rtoi(r*2.0) != (cyc*2)) $stop; if ($rtoi(r/2.0) != (cyc/2)) $stop; r2 = (2.0/(r-60)); // When zero, result indeterminate, but no crash // r2 = $itor(cyc); case (r) (r2-1.0): $stop; r2: ; default: $stop; endcase // r = $itor(cyc); if ((r==50.0) != (cyc==50)) $stop; if ((r!=50.0) != (cyc!=50)) $stop; if ((r> 50.0) != (cyc> 50)) $stop; if ((r>=50.0) != (cyc>=50)) $stop; if ((r< 50.0) != (cyc< 50)) $stop; if ((r<=50.0) != (cyc<=50)) $stop; // if ($rtoi((r-50.0) ? 10.0 : 20.0) != (((cyc-50)!=0) ? 10 : 20)) $stop; // if ((!(r-50.0)) != (!((cyc-50) != 0))) $stop; // r = real'(ci48); `checkr(r, 280375465082880.0); r = real'(cis48); `checkr(r, -1099511627776.0); // r = real'(ci96); `checkr(r, 74276402357122816493947453440.0); r = real'(cis96); `checkr(r, -4951760157141521099596496896.0); end else if (cyc==90) begin ci32 <= '0; cis32 <= '0; ci48 <= '0; cis48 <= '0; ci64 <= '0; cis64 <= '0; ci96 <= '0; cis96 <= '0; end else if (cyc==91) begin `checkr(real'(ci32), 0.0); `checkr(real'(cis32), 0.0); `checkr(real'(ci48), 0.0); `checkr(real'(cis48), 0.0); `checkr(real'(ci64), 0.0); `checkr(real'(cis64), 0.0); `checkr(real'(ci96), 0.0); `checkr(real'(cis96), 0.0); end else if (cyc==92) begin ci32 <= 32'b1; cis32 <= 32'b1; ci48 <= 48'b1; cis48 <= 48'b1; ci64 <= 64'b1; cis64 <= 64'b1; ci96 <= 96'b1; cis96 <= 96'b1; end else if (cyc==93) begin `checkr(real'(ci32), 1.0); `checkr(real'(cis32), 1.0); `checkr(real'(ci48), 1.0); `checkr(real'(cis48), 1.0); `checkr(real'(ci64), 1.0); `checkr(real'(cis64), 1.0); `checkr(real'(ci96), 1.0); `checkr(real'(cis96), 1.0); end else if (cyc==94) begin ci32 <= ~ '0; cis32 <= ~ '0; ci48 <= ~ '0; cis48 <= ~ '0; ci64 <= ~ '0; cis64 <= ~ '0; ci96 <= ~ '0; cis96 <= ~ '0; end else if (cyc==95) begin `checkr(real'(ci32), 4294967295.0); `checkr(real'(cis32), -1.0); `checkr(real'(ci48), 281474976710655.0); `checkr(real'(cis48), -1.0); `checkr(real'(ci64), 18446744073709551616.0); `checkr(real'(cis64), -1.0); `checkr(real'(ci96), 79228162514264337593543950336.0); `checkr(real'(cis96), -1.0); end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module sub_cast_bug374(input clk, input [4:0] cyc5); integer i; always @(posedge clk) begin i <= integer'(cyc5); end endmodule verilator-5.042/test_regress/t/t_package_param.py0000755000542200017500000000073415101701376022545 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_select_bad_width0.v0000644000542200017500000000077015101701376023150 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; parameter int ZERO = 0; initial begin bit [31:0] val = '1; int left = 4; int part = val[left +: ZERO]; $display(part); part = val[left -: ZERO]; $display(part); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_trace_split_cfuncs.py0000755000542200017500000000100215101701376023631 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=["--trace-vcd", "--output-split-cfuncs", "1"]) test.passes() verilator-5.042/test_regress/t/t_randomize_complex_associative_arrays.py0000755000542200017500000000104615101701376027461 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_assert_inside_cond.v0000644000542200017500000000155415101701376023444 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs hit, // Inputs clk ); input clk; output logic hit; logic [31:0] addr; int cyc; initial addr = 32'h380; always @ (posedge clk) begin cyc <= cyc + 1; `ifdef T_ASSERT_INSIDE_COND addr <= 32'h380; `elsif T_ASSERT_INSIDE_COND_BAD addr <= 32'h389; `else `error "Bad test define" `endif if (cyc == 9) begin $write("*-* All Finished *-*\n"); $finish; end end always_comb begin hit = 0; unique case (addr[11:0]) inside [12'h380 : 12'h388]: begin hit = 1; end endcase end endmodule verilator-5.042/test_regress/t/t_gen_if.v0000644000542200017500000000243715101701376021035 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // simplistic example, should choose 1st conditional generate and assign straight through // the tool also compiles the special case and determines an error (replication value is 0) // // This file ONLY is placed into the Public Domain, for any use, // without warranty. // SPDX-License-Identifier: CC0-1.0 `timescale 1ns / 1ps module t(data_i, data_o, single); parameter OP_BITS = 32; input [OP_BITS -1:0] data_i; output [31:0] data_o; input single; // Bare begin/end extension of IEEE allowed by most all tools begin end begin : named end : named //simplistic example, should choose 1st conditional generate and assign straight through //the tool also compiles the special case and determines an error (replication value is 0 generate if (OP_BITS == 32) begin : general_case assign data_o = data_i; // Test implicit signals /* verilator lint_off IMPLICIT */ assign imp = single; /* verilator lint_on IMPLICIT */ end else begin : special_case assign data_o = {{(32 -OP_BITS){1'b0}},data_i}; /* verilator lint_off IMPLICIT */ assign imp = single; /* verilator lint_on IMPLICIT */ end endgenerate endmodule verilator-5.042/test_regress/t/t_inst_dtree_inla.py0000755000542200017500000000107515101701376023134 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_inst_dtree.v" test.compile(v_flags2=['+define+INLINE_A'], verilator_flags2=['-trace']) test.execute() test.passes() verilator-5.042/test_regress/t/t_EXAMPLE.v0000644000542200017500000000542115101701376020675 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Use this file as a template for submitting bugs, etc. // This module takes a single clock input, and should either // $write("*-* All Finished *-*\n"); // $finish; // on success, or $stop. // // The code as shown applies a random vector to the Test // module, then calculates a CRC on the Test module's outputs. // // **If you do not wish for your code to be released to the public // please note it here, otherwise:** // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); // verilog_format: on module t ( input clk ); int cyc; logic [63:0] crc; logic [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) logic [31:0] out; // From test of Test.v // End of automatics Test test ( /*AUTOINST*/ // Outputs .out (out[31:0]), // Inputs .clk (clk), .in (in[31:0])); // Aggregate outputs into a single result vector wire [63:0] result = {32'h0, out}; // Test loop always @(posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc == 0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc < 10) begin sum <= '0; end else if (cyc == 99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); `checkh(crc, 64'hc77bb9b3784ea091); // What checksum will we end up with (above print should match) `checkh(sum, 64'h4afe43fb79d7b71e); $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test ( input clk, input [31:0] in, output logic [31:0] out ); // Replace this module with the device under test. // // Change the code in the t module to apply values to the inputs and // merge the output values into the result vector. always @(posedge clk) begin out <= in; end endmodule verilator-5.042/test_regress/t/t_savable_format3_bad.py0000755000542200017500000000167315101701376023653 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_savable.v" test.compile(v_flags2=["--savable"], save_time=500) test.execute(check_finished=False, all_run_flags=['+save_time=500']) if not os.path.exists(test.obj_dir + "/saved.vltsv"): test.error("saved.vltsv not created") # Break the header test.file_sed(test.obj_dir + "/saved.vltsv", test.obj_dir + "/saved.vltsv", lambda line: re.sub(r'vltsaved', 'vltNOTed', line)) test.execute(all_run_flags=['+save_restore=1'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_debug_inputs.v0000644000542200017500000000050215101701376022265 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Dotted reference that uses another dotted reference // as the select expression // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `include "t/t_debug_inputs_a.v" module t_debug_inputs; endmodule verilator-5.042/test_regress/t/t_gate_inline_wide_noexclude_const.v0000644000542200017500000000073715101701376026351 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t; logic [255:0] arrd = 256'b0; logic [255:0] y0; // Do not exclude from inlining wide variables with const assignments. always_comb y0 = 256'(arrd[0]); always_comb begin if (y0 != 1 && y0 != 0) begin $stop; end end endmodule verilator-5.042/test_regress/t/t_case_66bits_noexpand.py0000755000542200017500000000103615101701376023772 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_case_66bits.v" test.compile(verilator_flags2=['-fno-expand']) test.execute() test.passes() verilator-5.042/test_regress/t/t_fuzz_genintf_bad.py0000755000542200017500000000076615101701376023315 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_mod_paren_bad.out0000644000542200017500000000035515101701376023745 0ustar mahmoudyfreeshell%Error: t/t_lint_mod_paren_bad.v:13:6: syntax error, unexpected '(', expecting ';' 13 | ) ( | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_func_recurse_param_bad.py0000755000542200017500000000076315101701376024445 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_wire_beh1800_bad.py0000755000542200017500000000107615101701376022675 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--lint-only --language 1800-2017"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_assert_iff_clk_unsup.out0000644000542200017500000000067615101701376024363 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_assert_iff_clk_unsup.v:20:21: Unsupported: property '(disable iff (...) @ (...)' : ... Suggest use property '(@(...) disable iff (...))' 20 | assert property (disable iff (cyc < 5) @(posedge clk) cyc >= 5); | ^~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_cover_line_wide_ternary.py0000755000542200017500000000156215101701376024673 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap from pathlib import Path test.scenarios('simulator') test.compile(verilator_flags2=['--cc', '--coverage-line']) test.execute() test.run(cmd=[ os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--annotate-points", "--annotate", test.obj_dir + "/annotated", test.obj_dir + "/coverage.dat", ], verilator_run=True) top = Path(test.top_filename) test.files_identical(test.obj_dir + f"/annotated/{top.name}", test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_trace_open_wrong_order_bad.cpp0000644000542200017500000000144215101701376025452 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Yu-Sheng Lin. // SPDX-License-Identifier: CC0-1.0 #include #include #include VM_PREFIX_INCLUDE int main(int argc, char** argv) { std::unique_ptr contextp{new VerilatedContext}; std::unique_ptr tfp{new VerilatedVcdC}; std::unique_ptr top{new VM_PREFIX{contextp.get(), "top"}}; contextp->traceEverOn(true); tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/dump.vcd"); // Error! shall put to the next line! top->trace(tfp.get(), 99); // Error! tfp->dump(0); tfp->close(); return 0; } verilator-5.042/test_regress/t/t_depth_flop.py0000755000542200017500000000106015101701376022107 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vltmt') # Note issue shows up with --threads test.compile(verilator_flags2=['--compiler clang -Wno-UNOPTTHREADS'], threads=2) test.passes() verilator-5.042/test_regress/t/t_param_typedef2.py0000755000542200017500000000073415101701376022674 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_iff.v0000644000542200017500000000430515101701376020346 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [63:0] result; // From test of Test.v // End of automatics Test test (.*); // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc<10) begin sum <= '0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'hd55eb7da9ba3354a if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test ( input clk, input [63:0] crc, input [31:0] cyc, output wire [63:0] result); wire enable = crc[32]; wire [7:0] d = crc[7:0]; logic [7:0] d0_r; always @(d iff enable) begin d0_r <= d; end logic [7:0] d1_r; always @(posedge d iff enable) begin d1_r <= d; end logic [7:0] d2_r; always @(negedge d iff enable) begin d2_r <= d; end logic [7:0] d3_r; always @(edge d iff enable) begin d3_r <= d; end wire reset = (cyc < 10); assert property (@(posedge clk iff enable) disable iff (reset) (crc != '0)); // Aggregate outputs into a single result vector assign result = {32'h0, d3_r, d2_r, d1_r, d0_r}; endmodule verilator-5.042/test_regress/t/t_flag_decorations_bad.py0000755000542200017500000000110615101701376024075 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_flag_decoration.v" test.lint(verilator_flags2=["-decorations BAD"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface1.py0000755000542200017500000000073415101701376022013 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_preproc_debugi.py0000755000542200017500000000137315101701376022763 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') # Hit the debug statements in the preprocessor for internal coverage test.run(cmd=[ os.environ["VERILATOR_ROOT"] + "/bin/verilator", "-E", "t/t_preproc_debugi.v", "--debug", "--debugi-V3PreShell 10", ], tee=test.verbose, logfile=test.obj_dir + "/sim.log", verilator_run=True) test.passes() verilator-5.042/test_regress/t/t_pp_display.py0000755000542200017500000000077215101701376022140 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_forward.py0000755000542200017500000000073415101701376022623 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_math_cv_bitop.out0000644000542200017500000000024715101701376022763 0ustar mahmoudyfreeshellone 'd=-1 'b=1 ort 'd=-1 'b=1 tmp 'd= -1 'b=11111111 out63 'd= 1 'b=000000000000000000000001 out63 'd= 1 'b=000000000000000000000001 *-* All Finished *-* verilator-5.042/test_regress/t/t_pp_line_bad.py0000755000542200017500000000102415101701376022217 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=['-no-std'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_disable_func_bad.py0000755000542200017500000000106515101701376023214 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=['--lint-only --timing'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_param_sel.py0000755000542200017500000000073415101701376021735 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_timing_wait2.out0000644000542200017500000000003315101701376022533 0ustar mahmoudyfreeshell2 1 0 *-* All Finished *-* verilator-5.042/test_regress/t/t_gen_assign.py0000755000542200017500000000071215101701376022103 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile() test.passes() verilator-5.042/test_regress/t/t_flag_compiler_msvc.py0000755000542200017500000000110715101701376023620 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_flag_compiler.v" test.compile( # Bug requires msvc verilator_flags2=["--compiler msvc"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_sys_readmem_c.mem0000644000542200017500000000055315101701376022726 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test data file // // Copyright 2006 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 @4 14 @a 1a 1b 1c verilator-5.042/test_regress/t/t_hier_block_threads_bad.v0000644000542200017500000000136415101701376024225 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; generate for (genvar i = 0; i < 2; ++i) Core hierCore(clk); endgenerate always @(negedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule module Core(input clk); /* verilator hier_block */ generate for (genvar i = 0; i < 2; ++i) SubCore sub(clk); endgenerate always @(posedge clk) $display("%m"); endmodule module SubCore(input clk); /* verilator hier_block */ always @(posedge clk) $display("%m"); endmodule verilator-5.042/test_regress/t/t_flag_errorlimit_bad.out0000644000542200017500000000110415101701376024125 0ustar mahmoudyfreeshell%Error: t/t_flag_errorlimit_bad.v:10:8: Duplicate declaration of signal: 'u1' 10 | int u1; | ^~ t/t_flag_errorlimit_bad.v:9:8: ... Location of original declaration 9 | int u1; | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_flag_errorlimit_bad.v:11:8: Duplicate declaration of signal: 'u1' 11 | int u1; | ^~ t/t_flag_errorlimit_bad.v:9:8: ... Location of original declaration 9 | int u1; | ^~ %Error: Exiting due to verilator-5.042/test_regress/t/t_profcfunc.gprof0000644000542200017500000001026115101701376022435 0ustar mahmoudyfreeshellFlat profile: Note all numbers below were faked for this test, so might not be consistent. % cumulative self self total time seconds seconds calls Ts/call Ts/call name 1.99 1.99 0.99 200578 0.00 0.00 VL_EXTENDS_QQ(int, int, unsigned long) 1.98 0.00 0.98 100000 0.00 0.00 VL_POWSS_QQQ(int, int, int, unsigned long, unsigned long, bool, bool) 1.89 0.00 0.89 1407 0.00 0.00 Verilated::debug() 1.88 0.00 0.88 202 0.00 0.00 VerilatedContext::gotFinish() const 1.87 0.00 0.87 6 0.00 0.00 VerilatedContext::randReset() 1.86 0.00 0.86 9 0.00 0.00 VlWide<2ul>::operator unsigned int*() 1.79 0.00 0.79 600 0.00 0.00 Vt_prof* const& std::__get_helper<0ul, Vt_prof*, std::default_delete >(std::_Tuple_impl<0ul, Vt_prof*, std::default_delete > const&) 1.78 0.00 0.78 3 0.00 0.00 Vt_prof*& std::__get_helper<0ul, Vt_prof*, std::default_delete >(std::_Tuple_impl<0ul, Vt_prof*, std::default_delete >&) 1.77 0.00 0.77 1 0.00 0.00 Vt_prof::Vt_prof(VerilatedContext*, char const*) 1.76 0.00 0.76 1 0.00 0.00 Vt_prof::Vt_prof(char const*) 1.75 0.00 0.75 200 0.00 0.00 Vt_prof::eval() 1.74 0.00 0.74 200 0.00 0.00 Vt_prof::eval_step() 1.73 0.00 0.73 1 0.00 0.00 Vt_prof::final() 1.72 0.00 0.72 1 0.00 0.00 Vt_prof::~Vt_prof() 1.71 0.00 0.71 1 0.00 0.00 Vt_prof__Syms::Vt_prof__Syms(VerilatedContext*, char const*, Vt_prof*) 1.70 0.00 0.70 1 0.00 0.00 Vt_prof__Syms::~Vt_prof__Syms() 1.69 0.00 0.69 1 0.00 0.00 Vt_prof___024root::__Vconfigure(Vt_prof__Syms*, bool) 1.68 0.00 0.68 1 0.00 0.00 Vt_prof___024root::Vt_prof___024root(char const*) 1.67 0.00 0.67 1 0.00 0.00 Vt_prof___024root::~Vt_prof___024root() 1.66 0.00 0.66 201 0.00 0.00 Vt_prof___024root___eval(Vt_prof___024root*) 1.65 0.00 0.65 200 0.00 0.00 Vt_prof___024root___eval_debug_assertions(Vt_prof___024root*) 1.64 0.00 0.64 100 0.00 0.00 Vt_prof___024root___sequent__TOP__5__PROF__t_prof__l31(Vt_prof___024root*) 1.63 0.00 0.63 100 0.00 0.00 Vt_prof___024root___sequent__TOP__50__PROF__t_prof__l31(Vt_prof___024root*) 1.62 0.00 0.62 100 0.00 0.00 Vt_prof___024root___sequent__TOP__6__PROF__t_prof__l30(Vt_prof___024root*) 1.61 0.00 0.61 1 0.00 0.00 Vt_prof___024root___final(Vt_prof___024root*) 1.60 0.00 0.60 1 0.00 0.00 Vt_prof___024root___eval_settle(Vt_prof___024root*) 1.59 0.00 0.59 1 0.00 0.00 Vt_prof___024root___eval_initial(Vt_prof___024root*) 1.58 0.00 0.58 1 0.00 0.00 Vt_prof___024root___ctor_var_reset(Vt_prof___024root*) 1.57 0.00 0.57 1 0.00 0.00 Vt_prof___024root___initial__TOP__13__PROF__t_prof__l13(Vt_prof___024root*) 1.30 0.00 0.30 1 0.00 0.00 _eval_initial_loop(Vt_prof__Syms*) 1.29 0.00 0.29 1 0.00 0.00 _vl_cmp_w(int, unsigned int const*, unsigned int const*) 1.28 0.00 0.28 2 0.00 0.00 _vl_moddiv_w(int, unsigned int*, unsigned int const*, unsigned int const*, bool) 1.27 0.00 0.27 2 0.00 0.00 _vl_vsformat(std::__cxx11::basic_string, std::allocator >&, char const*, __va_list_tag*) 1.26 0.00 0.26 1399 0.00 0.00 std::unique_ptr >::get() const 1.25 0.00 0.25 3 0.00 0.00 unsigned long const& std::max(unsigned long const&, unsigned long const&) 1.19 0.00 0.19 1 0.00 0.00 vl_finish(char const*, int, char const*) 1.18 0.00 0.18 2 0.00 0.00 vl_time_pow10(int) verilator-5.042/test_regress/t/t_sys_fscanf_bad.v0000644000542200017500000000064615101701376022552 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; integer file; integer i; initial begin $fscanf(file, "%l", i); // Bad $fscanf(file, "%m", i); // Bad $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_runflag_seed.py0000755000542200017500000000111615101701376022423 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile() test.execute(all_run_flags=["+verilator+seed+5 +SEED=fffffff4"]) test.execute(all_run_flags=["+verilator+seed+6 +SEED=fffffff2"]) test.passes() verilator-5.042/test_regress/t/t_class_param_rewrite.v0000644000542200017500000000143015101701376023624 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module test; typedef enum { FOO_0 } foo_e; typedef enum { BAR_0 } bar_e; class baz #(parameter type E = foo_e); static function void print(); E enum_item; if (enum_item.first().name() != "BAR_0") $stop; endfunction class Inner1; static function void print(); E enum_item; if (enum_item.first().name() != "BAR_0") $stop; endfunction endclass endclass initial begin baz#(bar_e)::print(); baz#(bar_e)::Inner1::print(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_wire_behp1364_bad.v0000644000542200017500000000121615101701376022670 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( output o, output [1:0] oa, output reg ro, output reg [1:0] roa, output wire wo, output wire [1:0] woa //1800 only: //output var vo; //output var [1:0] voa; ); wire w; reg r; initial begin // Error w = 0; o = 0; oa = 0; wo = 0; woa = 0; // Not an error r = 0; ro = 0; roa = 0; //vo = 0; //voa = 0; end endmodule verilator-5.042/test_regress/t/t_timing_localevent.v0000644000542200017500000000166615101701376023314 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t; class Foo; task sleep; event e; fork @e; #1 ->e; join endtask task trigger_later1(event e); fork #2 ->e; join_none endtask task trigger_later2(ref event e); fork #3 ->e; join_none endtask task test; for (int i = 0; i < 10; i++) begin event e1, e2; trigger_later1(e1); trigger_later2(e2); sleep; @e1; @e2; end endtask endclass initial begin Foo foo = new; foo.test; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_interface_virtual_sched_nba.out0000644000542200017500000000034715101701376025642 0ustar mahmoudyfreeshell[0] intf1.data==0000 [0] intf2.data==0000 [0] vif3.data==0000 [15000] intf1.data==dead [30000] intf2.data==dead [35000] intf1.data==beef [50000] intf2.data==beef [55000] vif3.data==face [65000] vif3.data==cafe *-* All Finished *-* verilator-5.042/test_regress/t/t_concat_link_bad.out0000644000542200017500000000300015101701376023225 0ustar mahmoudyfreeshell%Error: t/t_concat_link_bad.v:13:20: Syntax error: Not expecting REPLICATE under a DOT in dotted expression 13 | assign bar_s = {foo_s, foo_s}.f1; | ^ t/t_concat_link_bad.v:13:34: ... Resolving this reference 13 | assign bar_s = {foo_s, foo_s}.f1; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_concat_link_bad.v:13:26: Syntax error: Not expecting CONCAT under a REPLICATE in dotted expression 13 | assign bar_s = {foo_s, foo_s}.f1; | ^ t/t_concat_link_bad.v:13:34: ... Resolving this reference 13 | assign bar_s = {foo_s, foo_s}.f1; | ^ %Error: t/t_concat_link_bad.v:13:20: Syntax error: Not expecting CONST under a REPLICATE in dotted expression 13 | assign bar_s = {foo_s, foo_s}.f1; | ^ t/t_concat_link_bad.v:13:34: ... Resolving this reference 13 | assign bar_s = {foo_s, foo_s}.f1; | ^ %Warning-IMPLICIT: t/t_concat_link_bad.v:13:12: Signal definition not found, creating implicitly: 'bar_s' 13 | assign bar_s = {foo_s, foo_s}.f1; | ^~~~~ ... For warning description see https://verilator.org/warn/IMPLICIT?v=latest ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_math_shiftrs2.py0000755000542200017500000000077115101701376022550 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--binary']) test.execute() test.passes() verilator-5.042/test_regress/t/t_clk_concat.py0000755000542200017500000000112615101701376022066 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') out_filename = test.obj_dir + "/V" + test.name + ".tree.json" test.compile(verilator_flags2=["+define+ATTRIBUTES --no-json-edit-nums"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_math_real_random.v0000644000542200017500000000523215101701376023076 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t(/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; reg [127:0] in; check #(48) check48 (.*); check #(31) check31 (.*); check #(32) check32 (.*); check #(63) check63 (.*); check #(64) check64 (.*); check #(96) check96 (.*); check #(128) check128 (.*); always_comb begin if (crc[2:0] == 0) in = '0; else if (crc[2:0] == 1) in = ~'0; else if (crc[2:0] == 2) in = 128'b1; else if (crc[2:0] == 3) in = ~ 128'b1; else begin in = {crc, crc}; if (crc[3]) in[31:0] = '0; if (crc[4]) in[63:32] = '0; if (crc[5]) in[95:64] = '0; if (crc[6]) in[127:96] = '0; if (crc[7]) in[31:0] = ~'0; if (crc[8]) in[63:32] = ~'0; if (crc[9]) in[95:64] = ~'0; if (crc[10]) in[127:96] = ~'0; end end // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d in=%x\n", $time, cyc, in); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; if (cyc == 0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc == 99) begin `checkr(check48.sum, 14574057015683440.000000); `checkr(check31.sum, 114141374814.000000); `checkr(check32.sum, 236547942750.000000); `checkr(check63.sum, 513694866079917670400.000000); `checkr(check64.sum, 1002533584033221181440.000000); `checkr(check96.sum, 4377373669974269260279175970816.000000); `checkr(check128.sum, 18358899571808044815012294240949812330496.000000); $write("*-* All Finished *-*\n"); $finish; end end endmodule module check(/*AUTOARG*/ // Inputs in, clk, cyc ); parameter WIDTH = 128; input [127:0] in; wire [WIDTH-1:0] ci = in[WIDTH-1:0]; wire signed [WIDTH-1:0] cis = in[WIDTH-1:0]; real r; real rs; always_comb r = ci; always_comb rs = cis; input clk; input integer cyc; real sum; always_ff @ (negedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] w%0d in=%h r=%f rs=%f sum=%f\n", $time, WIDTH, ci, r, rs, sum); `endif if (cyc < 10) sum <= 0; else sum <= sum + r + rs; end endmodule verilator-5.042/test_regress/t/t_fuzz_triand_bad.py0000755000542200017500000000076615101701376023144 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_case_inside_bad.v0000644000542200017500000000050215101701376022651 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin casex (1'bx) inside default: $stop; endcase end endmodule verilator-5.042/test_regress/t/t_force_rhs_ref_multiple.v0000644000542200017500000000157515101701376024331 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module t; logic [7:0] a = 1; logic [7:0] b = 2; logic [7:0] c = 3; logic [7:0] d = 4; logic [7:0] e = 5; initial begin force e = a + b + c + d; `checkh(e, 10); #1; a = 0; #1; `checkh(e, 9); b = 0; #1; `checkh(e, 7); c = 0; #1; `checkh(e, 4); d = 0; #1; `checkh(e, 0); release e; // Not driven, change value after procedural assignment. `checkh(e, 0); e = 5; `checkh(e, 5); $finish; end endmodule verilator-5.042/test_regress/t/t_for_comma.py0000755000542200017500000000073415101701376021734 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_param_implicit_string.py0000755000542200017500000000073415101701376024352 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_stream_unpack_narrower.out0000644000542200017500000000324615101701376024722 0ustar mahmoudyfreeshell%Warning-WIDTHEXPAND: t/t_stream_unpack_narrower.v:15:18: Stream target requires 32 bits, but source expression only provides 31 bits (IEEE 1800-2023 11.4.14.3) : ... note: In instance 't' 15 | {>>{stream}} = packed_data; | ^ ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. %Warning-WIDTHTRUNC: t/t_stream_unpack_narrower.v:16:17: Target fixed size variable (31 bits) is narrower than the stream (32 bits) (IEEE 1800-2023 11.4.14) : ... note: In instance 't' 16 | packed_data = {>>{stream}}; | ^ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Warning-WIDTHTRUNC: t/t_stream_unpack_narrower.v:17:12: Target fixed size variable (32 bits) is narrower than the stream (61 bits) (IEEE 1800-2023 11.4.14) : ... note: In instance 't' 17 | stream = {>>{packed_data2}}; | ^ %Warning-WIDTHEXPAND: t/t_stream_unpack_narrower.v:18:24: Stream target requires 61 bits, but source expression only provides 32 bits (IEEE 1800-2023 11.4.14.3) : ... note: In instance 't' 18 | {>>{packed_data2}} = stream; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_sys_monitor.out0000644000542200017500000000053115101701376022526 0ustar mahmoudyfreeshell[110] cyc=11 [120] cyc=12 [130] cyc=13 [140] cyc=14 [150] cyc=15 [160] cyc=16 [170] cyc=17 00000000000000000000000000010010b 00000013h 00000000024o 00000000025o 00000000026o [230] cyc=23 new-monitor [240] cyc=24 new-monitor [270] cyc=27 new-monitor [280] cyc=28 new-monitor [290] cyc=29 new-monitor [300] cyc=30 new-monitor *-* All Finished *-* verilator-5.042/test_regress/t/t_constraint_assoc_arr_bad.out0000644000542200017500000000250115101701376025166 0ustar mahmoudyfreeshell%Warning-CONSTRAINTIGN: t/t_constraint_assoc_arr_bad.v:12:20: Unsupported: Constrained randomization of associative array keys of 144bits, limit is 128 bits 12 | string_arr["a_very_long_string"] == 65; | ^~~~~~~~~~~~~~~~~~~~ ... For warning description see https://verilator.org/warn/CONSTRAINTIGN?v=latest ... Use "/* verilator lint_off CONSTRAINTIGN */" and lint_on around source to disable this message. %Error: t/t_constraint_assoc_arr_bad.v:30:26: Illegal non-integral expression or subexpression in random constraint. (IEEE 1800-2023 18.3) 30 | constraint c1 { data[cl] > 0;} | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_constraint_assoc_arr_bad.v:44:44: Illegal non-integral expression or subexpression in random constraint. (IEEE 1800-2023 18.3) 44 | constraint c2 { foreach (data[i]) data[i] < 100; } | ^ %Error: t/t_constraint_assoc_arr_bad.v:58:44: Illegal non-integral expression or subexpression in random constraint. (IEEE 1800-2023 18.3) 58 | constraint c3 { foreach (data[i]) data[i] > 0; } | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_sys_readmem_4state__h.mem.out0000644000542200017500000000001415101701376025154 0ustar mahmoudyfreeshell0 1 f f f f verilator-5.042/test_regress/t/t_preproc_noline.py0000755000542200017500000000145015101701376023004 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_preproc_noline.v" stdout_filename = os.path.join(test.obj_dir, test.name + "__test.vpp") test.compile(verilator_flags2=['-E -P'], verilator_make_gmake=False, make_top_shell=False, make_main=False, stdout_filename=stdout_filename) test.files_identical(stdout_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_x_rand_stability.py0000755000542200017500000000140615101701376023326 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap import glob test.scenarios("vlt") test.compile(verilator_flags2=["--x-initial unique"]) test.execute(all_run_flags=["+verilator+rand+reset+2"], expect_filename=test.golden_filename) test.passes() other_logs = [x for x in glob.glob("t/t_x_rand_stability_*.out") if "_zero" not in x] for other_log in other_logs: test.files_identical(test.golden_filename, other_log) verilator-5.042/test_regress/t/t_lint_multiple_msgs.py0000755000542200017500000000070315101701376023700 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint() test.passes() verilator-5.042/test_regress/t/t_unpacked_concat_bad2.py0000755000542200017500000000076315101701376024005 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_trace_public_func.cpp0000644000542200017500000000260115101701376023563 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include #include // clang-format off #include VM_PREFIX_INCLUDE #ifdef T_TRACE_PUBLIC_FUNC_VLT # include "Vt_trace_public_func_vlt_t.h" # include "Vt_trace_public_func_vlt_glbl.h" #else # include "Vt_trace_public_func_t.h" # include "Vt_trace_public_func_glbl.h" #endif // clang-format on unsigned long long main_time = 0; double sc_time_stamp() { return (double)main_time; } const unsigned long long dt_2 = 3; int main(int argc, char** argv) { Verilated::debug(0); Verilated::traceEverOn(true); Verilated::commandArgs(argc, argv); std::unique_ptr top{new VM_PREFIX{"top"}}; std::unique_ptr tfp{new VerilatedVcdC}; top->trace(tfp.get(), 99); tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); while (main_time <= 20) { top->CLK = (main_time / dt_2) % 2; top->eval(); top->t->glbl->setGSR(main_time < 7); tfp->dump((unsigned int)(main_time)); ++main_time; } tfp->close(); top->final(); tfp.reset(); top.reset(); printf("*-* All Finished *-*\n"); return 0; } verilator-5.042/test_regress/t/t_class_param_type.v0000644000542200017500000000756515101701376023143 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 // See also t_class_param.v class Parcls #(type T); static function int get_p; return T::get_p(); endfunction endclass class Cls; static function int get_p; return 20; endfunction endclass class ParclsDefaultType #(type T=Cls); static function int get_p; return T::get_p(); endfunction endclass typedef Cls cls_t; typedef cls_t cls2_t; class Singleton #(type T=int); static function Singleton#(T) self; static Singleton#(T) c = new; return c; endfunction function int get_size; return $bits(T); endfunction endclass class SingletonUnusedDefault #(type T=int); static function SingletonUnusedDefault#(T) self; static SingletonUnusedDefault#(T) c = new; return c; endfunction endclass class Empty; endclass class Foo #(type IF=Empty) extends IF; typedef Foo foo_t; int a = 1; endclass class Bar #(type A=int, type B=A) extends Foo#(); function int get_size_A; return $bits(A); endfunction function int get_size_B; return $bits(B); endfunction endclass class Empty2; endclass class Baz #(type T=Empty2) extends Foo#(); endclass class Getter1 extends Baz#(); function int get_1; foo_t f = new; return f.a; endfunction endclass class MyInt1; int x = 1; endclass class MyInt2; int x = 2; endclass class ExtendsMyInt #(type T=MyInt1) extends T; typedef ExtendsMyInt#(T) this_type; function int get_this_type_x; this_type t = new; return t.x; endfunction endclass class StaticX; static int val = 1; endclass class GetStaticXVal #(type T = int); static function int get; return T::val; endfunction endclass module t; initial begin automatic ParclsDefaultType#(Cls) pdt1 = new; automatic ParclsDefaultType#(cls_t) pdt2 = pdt1; automatic ParclsDefaultType#(cls2_t) pdt3 = pdt2; automatic Parcls#(Cls) p1 = new; automatic Parcls#(cls_t) p2 = p1; automatic Parcls#(cls2_t) p3 = p2; automatic Singleton #(int) s_int1 = Singleton#(int)::self(); automatic Singleton #(int) s_int2 = Singleton#(int)::self(); automatic Singleton #(bit) s_bit1 = Singleton#(bit)::self(); automatic Singleton #(bit) s_bit2 = Singleton#(bit)::self(); automatic SingletonUnusedDefault #(bit) sud1 = SingletonUnusedDefault#(bit)::self(); automatic SingletonUnusedDefault #(bit) sud2 = SingletonUnusedDefault#(bit)::self(); automatic Getter1 getter1 = new; automatic ExtendsMyInt#() ext1 = new; automatic ExtendsMyInt#(MyInt2) ext2 = new; automatic GetStaticXVal#(StaticX) get_statix_x_val = new; typedef bit my_bit_t; Bar#(.A(my_bit_t)) bar_a_bit = new; Bar#(.B(my_bit_t)) bar_b_bit = new; Bar#() bar_default = new; if (bar_a_bit.get_size_A != 1) $stop; if (bar_a_bit.get_size_B != 1) $stop; if (bar_b_bit.get_size_A != 32) $stop; if (bar_b_bit.get_size_B != 1) $stop; if (bar_default.get_size_A != 32) $stop; if (bar_default.get_size_B != 32) $stop; if (pdt1 != pdt2) $stop; if (pdt2 != pdt3) $stop; if (p1 != p2) $stop; if (p2 != p3) $stop; if (s_int1 != s_int2) $stop; if (s_bit1 != s_bit2) $stop; if (sud1 != sud2) $stop; if (s_int1.get_size() != 32) $stop; if (s_bit1.get_size() != 1) $stop; if (p1.get_p() != 20) $stop; if (pdt1.get_p() != 20) $stop; if (Parcls#(cls2_t)::get_p() != 20) $stop; if (getter1.get_1() != 1) $stop; if (ext1.get_this_type_x() != 1) $stop; if (ext2.get_this_type_x() != 2) $stop; if (get_statix_x_val.get() != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_class_new_default.py0000755000542200017500000000076315101701376023456 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_gen_lsb.v0000644000542200017500000000444515101701376021220 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [3:0] datai = crc[3:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) logic [3:0] datao; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .datao (datao[3:0]), // Inputs .clk (clk), .datai (datai[3:0])); // Aggregate outputs into a single result vector wire [63:0] result = {60'h0, datao}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h3db7bc8bfe61f983 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test ( input logic clk, input logic [3:0] datai, output logic [3:0] datao ); genvar i; parameter SIZE = 4; logic [SIZE:1][3:0] delay; always_ff @(posedge clk) begin delay[1][3:0] <= datai; end generate for (i = 2; i < (SIZE+1); i++) begin always_ff @(posedge clk) begin delay[i][3:0] <= delay[i-1][3:0]; end end endgenerate always_comb datao = delay[SIZE][3:0]; endmodule verilator-5.042/test_regress/t/t_threads_counter_2.py0000755000542200017500000000105015101701376023374 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vltmt') test.top_filename = "t/t_threads_counter.v" test.compile(verilator_flags2=['--cc'], threads=2) test.execute() test.passes() verilator-5.042/test_regress/t/t_typedef_fwd_nested.py0000755000542200017500000000073715101701376023637 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_interconnect_bad.py0000755000542200017500000000076615101701376023300 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_slice_init.v0000644000542200017500000000373215101701376021727 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk, d0, d1 ); input clk; input [7:0] d0, d1; logic [7:0] inia [1:0][3:0] = '{ '{ '0, '1, 8'hfe, 8'hed }, '{ '1, '1, 8'h11, 8'h22 }}; logic [7:0] inil [0:1][0:3] = '{ '{ '0, '1, 8'hfe, 8'hed }, '{ '1, '1, 8'h11, 8'h22 }}; logic [7:0] data [1:0][3:0]; logic [7:0] datl [0:1][0:3]; initial begin data = '{ '{ d0, d1, 8'hfe, 8'hed }, '{ d1, d1, 8'h11, 8'h22 }}; data[0] = '{ d0, d1, 8'h19, 8'h39 }; datl = '{ '{ d0, d1, 8'hfe, 8'hed }, '{ d1, d1, 8'h11, 8'h22 }}; datl[0] = '{ d0, d1, 8'h19, 8'h39 }; `ifdef TEST_VERBOSE $display("D=%x %x %x %x -> 39 19 x x", data[0][0], data[0][1], data[0][2], data[0][3]); $display("D=%x %x %x %x -> ed fe x x", data[1][0], data[1][1], data[1][2], data[1][3]); $display("L=%x %x %x %x -> x x 19 39", datl[0][0], datl[0][1], datl[0][2], datl[0][3]); $display("L=%x %x %x %x -> x x 11 12", datl[1][0], datl[1][1], datl[1][2], datl[1][3]); `endif if (inia[0][0] !== 8'h22) $stop; if (inia[0][1] !== 8'h11) $stop; if (inia[1][0] !== 8'hed) $stop; if (inia[1][1] !== 8'hfe) $stop; if (inil[0][2] !== 8'hfe) $stop; if (inil[0][3] !== 8'hed) $stop; if (inil[1][2] !== 8'h11) $stop; if (inil[1][3] !== 8'h22) $stop; if (data[0][0] !== 8'h39) $stop; if (data[0][1] !== 8'h19) $stop; if (data[1][0] !== 8'hed) $stop; if (data[1][1] !== 8'hfe) $stop; if (datl[0][2] !== 8'h19) $stop; if (datl[0][3] !== 8'h39) $stop; if (datl[1][2] !== 8'h11) $stop; if (datl[1][3] !== 8'h22) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_event_control_pass.py0000755000542200017500000000100415101701376023670 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"], threads=1) test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_split_cfuncs_dpi_export.v0000644000542200017500000000062015101701376025705 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Varun Koyyalagunta. // SPDX-License-Identifier: CC0-1.0 module t (); function automatic void func(); endfunction export "DPI-C" function func; initial begin $dumpfile("dump.vcd"); $dumpvars(); end endmodule verilator-5.042/test_regress/t/t_gate_basic_timing.py0000755000542200017500000000123715101701376023421 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_gate_basic.v" test.main_time_multiplier = 10e-7 / 10e-9 test.compile(timing_loop=True, verilator_flags2=["--timing --timescale 10ns/1ns -Wno-RISEFALLDLY -Wno-SPECIFYIGN"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_queue_persistence.v0000644000542200017500000000243315101701376023332 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t; int qdel[$]; int qkept[$]; task automatic func(ref int vrefed); `ifdef TEST_NOINLINE // verilator no_inline_task `endif `checkd(vrefed, 2); #100; vrefed = 10; #10; `checkd(vrefed, 10); endtask initial begin qkept.push_back(1); qkept.push_back(2); qkept.push_back(3); qdel = qkept; $display("qkept=%p qdel=%p", qkept, qdel); `checkd(qkept[0], 1); `checkd(qkept[1], 2); `checkd(qkept[2], 3); func(qdel[1]); func(qkept[1]); $display("qkept=%p qdel=%p", qkept, qdel); `checkd(qdel.size, 0); `checkd(qkept[0], 1); `checkd(qkept[1], 10); `checkd(qkept[2], 3); end initial begin #50; `checkd(qdel[1], 2); `checkd(qkept[1], 2); qdel.delete(); #100; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_math_repl.py0000755000542200017500000000073415101701376021745 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_genunnamed_bad.py0000755000542200017500000000110115101701376023734 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME"], expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_bind_nfound.v0000644000542200017500000000073115101701376022066 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface bound_if; endinterface module t; sub sub(); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule module sub_ext; bind sub_inst bound_if i_bound(); endmodule module sub; sub_ext sub_ext(); endmodule verilator-5.042/test_regress/t/t_array_list_bad.out0000644000542200017500000000156415101701376023127 0ustar mahmoudyfreeshell%Error: t/t_array_list_bad.v:38:25: Assignment pattern missed initializing elements: 'logic' 't3' : ... note: In instance 't' 38 | test_out <= '{'0, '0}; | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Warning-WIDTHEXPAND: t/t_array_list_bad.v:38:22: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS's CONCAT generates 2 bits. : ... note: In instance 't' 38 | test_out <= '{'0, '0}; | ^~ ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_dpi_arg_inout_unpack.cpp0000644000542200017500000014024515101701376024307 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2020 by Yutetsu TAKATSUKASA. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include #include #include #include #include // clang-format off #if defined(NCSC) // Used by NC's svdpi.h to pick up svLogicVecVal with _.aval and _.bval fields, // rather than the IEEE 1800-2005 version which has _.a and _.b fields. # define DPI_COMPATIBILITY_VERSION_1800v2012 #endif #include "svdpi.h" #if defined(VERILATOR) // Verilator # include "Vt_dpi_arg_inout_unpack__Dpi.h" typedef long long sv_longint_t; typedef unsigned long long sv_longint_unsigned_t; # define NO_SHORTREAL # define NO_UNPACK_STRUCT # define CONSTARG const #elif defined(VCS) // VCS # include "../vc_hdrs.h" typedef long long sv_longint_t; typedef unsigned long long sv_longint_unsigned_t; # define NO_TIME # define CONSTARG const #elif defined(NCSC) // NC # include "dpi-exp.h" # include "dpi-imp.h" typedef long long sv_longint_t; typedef unsigned long long sv_longint_unsigned_t; # define NO_TIME # define NO_INTEGER # define NO_SHORTREAL // Sadly NC does not declare pass-by reference input arguments as const # define CONSTARG #elif defined(MS) // ModelSim # include "dpi.h" typedef int64_t sv_longint_t; typedef uint64_t sv_longint_unsigned_t; # define CONSTARG const #else # error "Unknown simulator for DPI test" #endif // clang-format on //====================================================================== // Implementations of imported functions //====================================================================== namespace { // unnamed namespace const bool VERBOSE_MESSAGE = false; #define stop() \ do { \ printf(__FILE__ ":%d Bad value\n", __LINE__); \ abort(); \ } while (0) void set_uint(svLogicVecVal* v0, sv_longint_unsigned_t val, int bitwidth) { for (int i = 0; i < bitwidth; ++i) { if (i < 64) svPutBitselLogic(v0, i, (val >> i) & 1); else svPutBitselLogic(v0, i, 0); } } void set_uint(svBitVecVal* v0, sv_longint_unsigned_t val, int bitwidth) { for (int i = 0; i < bitwidth; ++i) { if (i < 64) svPutBitselBit(v0, i, (val >> i) & 1); else svPutBitselBit(v0, i, 0); } } template bool compare(const T& act, const T& exp) { if (exp == act) { if (VERBOSE_MESSAGE) std::cout << "OK Exp:" << exp << " actual:" << act << std::endl; return true; } else { std::cout << "NG Exp:" << exp << " actual:" << act << std::endl; return false; } } bool compare_scalar(const svScalar v0, sv_longint_unsigned_t val) { const bool act_bit = v0 == sv_1; const bool exp_bit = val & 1; if (act_bit != exp_bit) { std::cout << "Mismatch at bit:" << 0 << " exp:" << exp_bit << " act:" << act_bit; return false; } if (VERBOSE_MESSAGE) std::cout << "OK " << val << " as expected " << std::endl; return true; } bool compare(const svLogicVecVal* v0, sv_longint_unsigned_t val, int bitwidth) { for (int i = 0; i < bitwidth; ++i) { const bool act_bit = svGetBitselLogic(v0, i); const bool exp_bit = (i < 64) ? ((val >> i) & 1) : false; if (act_bit != exp_bit) { std::cout << "Mismatch at bit:" << i << " exp:" << exp_bit << " act:" << act_bit; return false; } } if (VERBOSE_MESSAGE) { std::cout << "OK " << val << " as expected (width:" << bitwidth << ")" << std::endl; } return true; } bool compare(const svBitVecVal* v0, sv_longint_unsigned_t val, int bitwidth) { for (int i = 0; i < bitwidth; ++i) { const bool act_bit = svGetBitselBit(v0, i); const bool exp_bit = (i < 64) ? ((val >> i) & 1) : false; if (act_bit != exp_bit) { std::cout << "Mismatch at bit:" << i << " exp:" << exp_bit << " act:" << act_bit; return false; } } if (VERBOSE_MESSAGE) { std::cout << "OK " << val << " as expected (width:" << bitwidth << ")" << std::endl; } return true; } template bool update_0d(T* v) { if (!compare(*v, 42)) return false; ++(*v); return true; } template bool update_1d(T* v) { if (!compare(v[0], 43)) return false; if (!compare(v[1], 44)) return false; ++v[0]; ++v[1]; return true; } template bool update_2d(T* v) { if (!compare(v[0 * 2 + 1], 45)) return false; if (!compare(v[1 * 2 + 1], 46)) return false; if (!compare(v[2 * 2 + 1], 47)) return false; ++v[0 * 2 + 1]; ++v[1 * 2 + 1]; ++v[2 * 2 + 1]; return true; } template bool update_3d(T* v) { if (!compare(v[(0 * 3 + 0) * 2 + 0], 48)) return false; if (!compare(v[(1 * 3 + 0) * 2 + 0], 49)) return false; if (!compare(v[(2 * 3 + 0) * 2 + 0], 50)) return false; if (!compare(v[(3 * 3 + 0) * 2 + 0], 51)) return false; ++v[(0 * 3 + 0) * 2 + 0]; ++v[(1 * 3 + 0) * 2 + 0]; ++v[(2 * 3 + 0) * 2 + 0]; ++v[(3 * 3 + 0) * 2 + 0]; return true; } template bool update_1d1(T* v) { if (!compare(v[0], 52)) return false; ++v[0]; return true; } template bool update_2d1(T* v) { if (!compare(v[0], 53)) return false; ++v[0]; return true; } template bool update_3d1(T* v) { if (!compare(v[0], 54)) return false; ++v[0]; return true; } bool update_0d_scalar(svScalar* v) { if (!compare_scalar(v[0], sv_0)) return false; v[0] = sv_1; return true; } bool update_1d_scalar(svScalar* v) { if (!compare_scalar(v[0], sv_1)) return false; v[0] = sv_0; if (!compare_scalar(v[1], sv_0)) return false; v[1] = sv_1; return true; } bool update_2d_scalar(svScalar* v) { if (!compare_scalar(v[(0 * 2) + 1], sv_1)) return false; v[(0 * 2) + 1] = sv_0; if (!compare_scalar(v[(1 * 2) + 1], sv_0)) return false; v[(1 * 2) + 1] = sv_1; if (!compare_scalar(v[(2 * 2) + 1], sv_1)) return false; v[(2 * 2) + 1] = sv_0; return true; } bool update_3d_scalar(svScalar* v) { if (!compare_scalar(v[((0 * 3) + 0) * 2 + 0], sv_0)) return false; v[(0 * 3 + 0) * 2 + 0] = sv_1; if (!compare_scalar(v[((1 * 3) + 0) * 2 + 0], sv_1)) return false; v[(1 * 3 + 0) * 2 + 0] = sv_0; if (!compare_scalar(v[((2 * 3) + 0) * 2 + 0], sv_0)) return false; v[(2 * 3 + 0) * 2 + 0] = sv_1; if (!compare_scalar(v[((3 * 3) + 0) * 2 + 0], sv_1)) return false; v[(3 * 3 + 0) * 2 + 0] = sv_0; return true; } bool update_1d1_scalar(svScalar* v) { if (!compare_scalar(v[0], sv_0)) return false; v[0] = sv_1; return true; } bool update_2d1_scalar(svScalar* v) { if (!compare_scalar(v[0], sv_1)) return false; v[0] = sv_0; return true; } bool update_3d1_scalar(svScalar* v) { if (!compare_scalar(v[0], sv_0)) return false; v[0] = sv_1; return true; } template bool update_0d(T* v, int bitwidth) { if (!compare(v, 42, bitwidth)) return false; set_uint(v, 43, bitwidth); return true; } template bool update_1d(T* v, int bitwidth) { const int unit = (bitwidth + 31) / 32; if (!compare(v + unit * 0, 43, bitwidth)) return false; if (!compare(v + unit * 1, 44, bitwidth)) return false; set_uint(v + unit * 0, 44, bitwidth); set_uint(v + unit * 1, 45, bitwidth); return true; } template bool update_2d(T* v, int bitwidth) { const int unit = (bitwidth + 31) / 32; if (!compare(v + unit * (0 * 2 + 1), 45, bitwidth)) return false; if (!compare(v + unit * (1 * 2 + 1), 46, bitwidth)) return false; if (!compare(v + unit * (2 * 2 + 1), 47, bitwidth)) return false; set_uint(v + unit * (0 * 2 + 1), 46, bitwidth); set_uint(v + unit * (1 * 2 + 1), 47, bitwidth); set_uint(v + unit * (2 * 2 + 1), 48, bitwidth); return true; } template bool update_3d(T* v, int bitwidth) { const int unit = (bitwidth + 31) / 32; if (!compare(v + unit * ((0 * 3 + 0) * 2 + 0), 48, bitwidth)) return false; if (!compare(v + unit * ((1 * 3 + 0) * 2 + 0), 49, bitwidth)) return false; if (!compare(v + unit * ((2 * 3 + 0) * 2 + 0), 50, bitwidth)) return false; if (!compare(v + unit * ((3 * 3 + 0) * 2 + 0), 51, bitwidth)) return false; set_uint(v + unit * ((0 * 3 + 0) * 2 + 0), 49, bitwidth); set_uint(v + unit * ((1 * 3 + 0) * 2 + 0), 50, bitwidth); set_uint(v + unit * ((2 * 3 + 0) * 2 + 0), 51, bitwidth); set_uint(v + unit * ((3 * 3 + 0) * 2 + 0), 52, bitwidth); return true; } template bool update_1d1(T* v, int bitwidth) { const int unit = (bitwidth + 31) / 32; if (!compare(v, 52, bitwidth)) return false; set_uint(v, 53, bitwidth); return true; } template bool update_2d1(T* v, int bitwidth) { const int unit = (bitwidth + 31) / 32; if (!compare(v, 53, bitwidth)) return false; set_uint(v, 54, bitwidth); return true; } template bool update_3d1(T* v, int bitwidth) { const int unit = (bitwidth + 31) / 32; if (!compare(v, 54, bitwidth)) return false; set_uint(v, 55, bitwidth); return true; } template void set_values(T (&v)[4][3][2]) { for (int i = 0; i < 4; ++i) for (int j = 0; j < 3; ++j) for (int k = 0; k < 2; ++k) v[i][j][k] = 0; v[3][2][1] = 42; v[2][1][0] = 43; v[2][1][1] = 44; v[1][0][1] = 45; v[1][1][1] = 46; v[1][2][1] = 47; v[0][0][0] = 48; v[1][0][0] = 49; v[2][0][0] = 50; v[3][0][0] = 51; } template void set_values(T (&v)[4][3][2][N], int bitwidth) { for (int i = 0; i < 4; ++i) for (int j = 0; j < 3; ++j) for (int k = 0; k < 2; ++k) set_uint(v[i][j][k], 0, bitwidth); set_uint(v[3][2][1], 42, bitwidth); set_uint(v[2][1][0], 43, bitwidth); set_uint(v[2][1][1], 44, bitwidth); set_uint(v[1][0][1], 45, bitwidth); set_uint(v[1][1][1], 46, bitwidth); set_uint(v[1][2][1], 47, bitwidth); set_uint(v[0][0][0], 48, bitwidth); set_uint(v[1][0][0], 49, bitwidth); set_uint(v[2][0][0], 50, bitwidth); set_uint(v[3][0][0], 51, bitwidth); } template bool check_0d(T v) { return compare(v, 43); } template bool check_1d(const T (&v)[2]) { return compare(v[0], 44) && compare(v[1], 45); } template bool check_2d(const T (&v)[3][2]) { return compare(v[0][1], 46) && compare(v[1][1], 47) && compare(v[2][1], 48); } template bool check_3d(const T (&v)[4][3][2]) { return compare(v[0][0][0], 49) && compare(v[1][0][0], 50) && compare(v[2][0][0], 51) && compare(v[3][0][0], 52); } template bool check_1d1(const T (&v)[1]) { return compare(v[0], 53); } template bool check_2d1(const T (&v)[1][1]) { return compare(v[0][0], 54); } template bool check_3d1(const T (&v)[1][1][1]) { return compare(v[0][0][0], 55); } template bool check_0d(const T (&v)[N], unsigned int bitwidth) { return compare(v, 43, bitwidth); } template bool check_1d(const T (&v)[2][N], unsigned int bitwidth) { return compare(v[0], 44, bitwidth) && compare(v[1], 45, bitwidth); } template bool check_2d(const T (&v)[3][2][N], unsigned int bitwidth) { return compare(v[0][1], 46, bitwidth) && compare(v[1][1], 47, bitwidth) && compare(v[2][1], 48, bitwidth); } template bool check_3d(const T (&v)[4][3][2][N], unsigned int bitwidth) { return compare(v[0][0][0], 49, bitwidth) && compare(v[1][0][0], 50, bitwidth) && compare(v[2][0][0], 51, bitwidth) && compare(v[3][0][0], 52, bitwidth); } template bool check_1d1(const T (&v)[1][N], unsigned int bitwidth) { return compare(v[0], 53, bitwidth); } template bool check_2d1(const T (&v)[1][1][N], unsigned int bitwidth) { return compare(v[0][0], 54, bitwidth); } template bool check_3d1(const T (&v)[1][1][1][N], unsigned int bitwidth) { return compare(v[0][0][0], 55, bitwidth); } } // unnamed namespace void* get_non_null() { static int v; return &v; } void i_byte_0d(char* v) { if (!update_0d(v)) stop(); } void i_byte_1d(char* v) { if (!update_1d(v)) stop(); } void i_byte_2d(char* v) { if (!update_2d(v)) stop(); } void i_byte_3d(char* v) { if (!update_3d(v)) stop(); } void i_byte_1d1(char* v) { if (!update_1d1(v)) stop(); } void i_byte_2d1(char* v) { if (!update_2d1(v)) stop(); } void i_byte_3d1(char* v) { if (!update_3d1(v)) stop(); } void i_byte_unsigned_0d(unsigned char* v) { if (!update_0d(v)) stop(); } void i_byte_unsigned_1d(unsigned char* v) { if (!update_1d(v)) stop(); } void i_byte_unsigned_2d(unsigned char* v) { if (!update_2d(v)) stop(); } void i_byte_unsigned_3d(unsigned char* v) { if (!update_3d(v)) stop(); } void i_byte_unsigned_1d1(unsigned char* v) { if (!update_1d1(v)) stop(); } void i_byte_unsigned_2d1(unsigned char* v) { if (!update_2d1(v)) stop(); } void i_byte_unsigned_3d1(unsigned char* v) { if (!update_3d1(v)) stop(); } void i_shortint_0d(short* v) { if (!update_0d(v)) stop(); } void i_shortint_1d(short* v) { if (!update_1d(v)) stop(); } void i_shortint_2d(short* v) { if (!update_2d(v)) stop(); } void i_shortint_3d(short* v) { if (!update_3d(v)) stop(); } void i_shortint_1d1(short* v) { if (!update_1d1(v)) stop(); } void i_shortint_2d1(short* v) { if (!update_2d1(v)) stop(); } void i_shortint_3d1(short* v) { if (!update_3d1(v)) stop(); } void i_shortint_unsigned_0d(unsigned short* v) { if (!update_0d(v)) stop(); } void i_shortint_unsigned_1d(unsigned short* v) { if (!update_1d(v)) stop(); } void i_shortint_unsigned_2d(unsigned short* v) { if (!update_2d(v)) stop(); } void i_shortint_unsigned_3d(unsigned short* v) { if (!update_3d(v)) stop(); } void i_shortint_unsigned_1d1(unsigned short* v) { if (!update_1d1(v)) stop(); } void i_shortint_unsigned_2d1(unsigned short* v) { if (!update_2d1(v)) stop(); } void i_shortint_unsigned_3d1(unsigned short* v) { if (!update_3d1(v)) stop(); } void i_int_0d(int* v) { if (!update_0d(v)) stop(); } void i_int_1d(int* v) { if (!update_1d(v)) stop(); } void i_int_2d(int* v) { if (!update_2d(v)) stop(); } void i_int_3d(int* v) { if (!update_3d(v)) stop(); } void i_int_1d1(int* v) { if (!update_1d1(v)) stop(); } void i_int_2d1(int* v) { if (!update_2d1(v)) stop(); } void i_int_3d1(int* v) { if (!update_3d1(v)) stop(); } void i_int_unsigned_0d(unsigned int* v) { if (!update_0d(v)) stop(); } void i_int_unsigned_1d(unsigned int* v) { if (!update_1d(v)) stop(); } void i_int_unsigned_2d(unsigned int* v) { if (!update_2d(v)) stop(); } void i_int_unsigned_3d(unsigned int* v) { if (!update_3d(v)) stop(); } void i_int_unsigned_1d1(unsigned int* v) { if (!update_1d1(v)) stop(); } void i_int_unsigned_2d1(unsigned int* v) { if (!update_2d1(v)) stop(); } void i_int_unsigned_3d1(unsigned int* v) { if (!update_3d1(v)) stop(); } void i_longint_0d(sv_longint_t* v) { if (!update_0d(v)) stop(); } void i_longint_1d(sv_longint_t* v) { if (!update_1d(v)) stop(); } void i_longint_2d(sv_longint_t* v) { if (!update_2d(v)) stop(); } void i_longint_3d(sv_longint_t* v) { if (!update_3d(v)) stop(); } void i_longint_1d1(sv_longint_t* v) { if (!update_1d1(v)) stop(); } void i_longint_2d1(sv_longint_t* v) { if (!update_2d1(v)) stop(); } void i_longint_3d1(sv_longint_t* v) { if (!update_3d1(v)) stop(); } void i_longint_unsigned_0d(sv_longint_unsigned_t* v) { if (!update_0d(v)) stop(); } void i_longint_unsigned_1d(sv_longint_unsigned_t* v) { if (!update_1d(v)) stop(); } void i_longint_unsigned_2d(sv_longint_unsigned_t* v) { if (!update_2d(v)) stop(); } void i_longint_unsigned_3d(sv_longint_unsigned_t* v) { if (!update_3d(v)) stop(); } void i_longint_unsigned_1d1(sv_longint_unsigned_t* v) { if (!update_1d1(v)) stop(); } void i_longint_unsigned_2d1(sv_longint_unsigned_t* v) { if (!update_2d1(v)) stop(); } void i_longint_unsigned_3d1(sv_longint_unsigned_t* v) { if (!update_3d1(v)) stop(); } #ifndef NO_TIME void i_time_0d(svLogicVecVal* v) { if (!update_0d(v, 64)) stop(); } void i_time_1d(svLogicVecVal* v) { if (!update_1d(v, 64)) stop(); } void i_time_2d(svLogicVecVal* v) { if (!update_2d(v, 64)) stop(); } void i_time_3d(svLogicVecVal* v) { if (!update_3d(v, 64)) stop(); } void i_time_1d1(svLogicVecVal* v) { if (!update_1d1(v, 64)) stop(); } void i_time_2d1(svLogicVecVal* v) { if (!update_2d1(v, 64)) stop(); } void i_time_3d1(svLogicVecVal* v) { if (!update_3d1(v, 64)) stop(); } #endif #ifndef NO_INTEGER void i_integer_0d(svLogicVecVal* v) { if (!update_0d(v, 32)) stop(); } void i_integer_1d(svLogicVecVal* v) { if (!update_1d(v, 32)) stop(); } void i_integer_2d(svLogicVecVal* v) { if (!update_2d(v, 32)) stop(); } void i_integer_3d(svLogicVecVal* v) { if (!update_3d(v, 32)) stop(); } void i_integer_1d1(svLogicVecVal* v) { if (!update_1d1(v, 32)) stop(); } void i_integer_2d1(svLogicVecVal* v) { if (!update_2d1(v, 32)) stop(); } void i_integer_3d1(svLogicVecVal* v) { if (!update_3d1(v, 32)) stop(); } #endif void i_real_0d(double* v) { update_0d(v); } void i_real_1d(double* v) { update_1d(v); } void i_real_2d(double* v) { update_2d(v); } void i_real_3d(double* v) { update_3d(v); } void i_real_1d1(double* v) { update_1d1(v); } void i_real_2d1(double* v) { update_2d1(v); } void i_real_3d1(double* v) { update_3d1(v); } #ifndef NO_SHORTREAL void i_shortreal_0d(float* v) { update_0d(v); } void i_shortreal_1d(float* v) { update_1d(v); } void i_shortreal_2d(float* v) { update_2d(v); } void i_shortreal_3d(float* v) { update_3d(v); } void i_shortreal_1d1(float* v) { update_1d1(v); } void i_shortreal_2d1(float* v) { update_2d1(v); } void i_shortreal_3d1(float* v) { update_3d1(v); } #endif void i_chandle_0d(void** v) { if (v[0]) stop(); v[0] = get_non_null(); } void i_chandle_1d(void** v) { if (v[0]) stop(); if (v[1]) stop(); v[0] = get_non_null(); v[1] = get_non_null(); } void i_chandle_2d(void** v) { if (v[2 * 0 + 1]) stop(); if (v[2 * 1 + 1]) stop(); if (v[2 * 2 + 1]) stop(); v[2 * 0 + 1] = get_non_null(); v[2 * 1 + 1] = get_non_null(); v[2 * 2 + 1] = get_non_null(); } void i_chandle_3d(void** v) { if (v[(0 * 3 + 0) * 2 + 0]) stop(); if (v[(1 * 3 + 0) * 2 + 0]) stop(); if (v[(2 * 3 + 0) * 2 + 0]) stop(); if (v[(3 * 3 + 0) * 2 + 0]) stop(); v[(0 * 3 + 0) * 2 + 0] = get_non_null(); v[(1 * 3 + 0) * 2 + 0] = get_non_null(); v[(2 * 3 + 0) * 2 + 0] = get_non_null(); v[(3 * 3 + 0) * 2 + 0] = get_non_null(); } void i_chandle_1d1(void** v) { if (v[0]) stop(); v[0] = get_non_null(); } void i_chandle_2d1(void** v) { if (v[0]) stop(); v[0] = get_non_null(); } void i_chandle_3d1(void** v) { if (v[0]) stop(); v[0] = get_non_null(); } void i_string_0d(const char** v) { static const char s[] = "43"; if (!compare(v[0], "42")) stop(); v[0] = s; } void i_string_1d(const char** v) { static const char s0[] = "44"; static const char s1[] = "45"; if (!compare(v[0], "43")) stop(); if (!compare(v[1], "44")) stop(); v[0] = s0; v[1] = s1; } void i_string_2d(const char** v) { static const char s0[] = "46"; static const char s1[] = "47"; static const char s2[] = "48"; if (!compare(v[2 * 0 + 1], "45")) stop(); if (!compare(v[2 * 1 + 1], "46")) stop(); if (!compare(v[2 * 2 + 1], "47")) stop(); v[2 * 0 + 1] = s0; v[2 * 1 + 1] = s1; v[2 * 2 + 1] = s2; } void i_string_3d(const char** v) { static const char s0[] = "49"; static const char s1[] = "50"; static const char s2[] = "51"; static const char s3[] = "52"; if (!compare(v[(0 * 3 + 0) * 2 + 0], "48")) stop(); if (!compare(v[(1 * 3 + 0) * 2 + 0], "49")) stop(); if (!compare(v[(2 * 3 + 0) * 2 + 0], "50")) stop(); if (!compare(v[(3 * 3 + 0) * 2 + 0], "51")) stop(); v[(0 * 3 + 0) * 2 + 0] = s0; v[(1 * 3 + 0) * 2 + 0] = s1; v[(2 * 3 + 0) * 2 + 0] = s2; v[(3 * 3 + 0) * 2 + 0] = s3; } void i_string_1d1(const char** v) { static const char s0[] = "53"; if (!compare(v[0], "52")) stop(); v[0] = s0; } void i_string_2d1(const char** v) { static const char s0[] = "54"; if (!compare(v[0], "53")) stop(); v[0] = s0; } void i_string_3d1(const char** v) { static const char s0[] = "55"; if (!compare(v[0], "54")) stop(); v[0] = s0; } void i_bit1_0d(svBit* v) { update_0d_scalar(v); } void i_bit1_1d(svBit* v) { update_1d_scalar(v); } void i_bit1_2d(svBit* v) { update_2d_scalar(v); } void i_bit1_3d(svBit* v) { update_3d_scalar(v); } void i_bit1_1d1(svBit* v) { update_1d1_scalar(v); } void i_bit1_2d1(svBit* v) { update_2d1_scalar(v); } void i_bit1_3d1(svBit* v) { update_3d1_scalar(v); } void i_bit7_0d(svBitVecVal* v) { update_0d(v, 7); } void i_bit7_1d(svBitVecVal* v) { update_1d(v, 7); } void i_bit7_2d(svBitVecVal* v) { update_2d(v, 7); } void i_bit7_3d(svBitVecVal* v) { update_3d(v, 7); } void i_bit7_1d1(svBitVecVal* v) { update_1d1(v, 7); } void i_bit7_2d1(svBitVecVal* v) { update_2d1(v, 7); } void i_bit7_3d1(svBitVecVal* v) { update_3d1(v, 7); } void i_bit121_0d(svBitVecVal* v) { update_0d(v, 121); } void i_bit121_1d(svBitVecVal* v) { update_1d(v, 121); } void i_bit121_2d(svBitVecVal* v) { update_2d(v, 121); } void i_bit121_3d(svBitVecVal* v) { update_3d(v, 121); } void i_bit121_1d1(svBitVecVal* v) { update_1d1(v, 121); } void i_bit121_2d1(svBitVecVal* v) { update_2d1(v, 121); } void i_bit121_3d1(svBitVecVal* v) { update_3d1(v, 121); } void i_logic1_0d(svLogic* v) { update_0d_scalar(v); } void i_logic1_1d(svLogic* v) { update_1d_scalar(v); } void i_logic1_2d(svLogic* v) { update_2d_scalar(v); } void i_logic1_3d(svLogic* v) { update_3d_scalar(v); } void i_logic1_1d1(svLogic* v) { update_1d1_scalar(v); } void i_logic1_2d1(svLogic* v) { update_2d1_scalar(v); } void i_logic1_3d1(svLogic* v) { update_3d1_scalar(v); } void i_logic7_0d(svLogicVecVal* v) { update_0d(v, 7); } void i_logic7_1d(svLogicVecVal* v) { update_1d(v, 7); } void i_logic7_2d(svLogicVecVal* v) { update_2d(v, 7); } void i_logic7_3d(svLogicVecVal* v) { update_3d(v, 7); } void i_logic7_1d1(svLogicVecVal* v) { update_1d1(v, 7); } void i_logic7_2d1(svLogicVecVal* v) { update_2d1(v, 7); } void i_logic7_3d1(svLogicVecVal* v) { update_3d1(v, 7); } void i_logic121_0d(svLogicVecVal* v) { update_0d(v, 121); } void i_logic121_1d(svLogicVecVal* v) { update_1d(v, 121); } void i_logic121_2d(svLogicVecVal* v) { update_2d(v, 121); } void i_logic121_3d(svLogicVecVal* v) { update_3d(v, 121); } void i_logic121_1d1(svLogicVecVal* v) { update_1d1(v, 121); } void i_logic121_2d1(svLogicVecVal* v) { update_2d1(v, 121); } void i_logic121_3d1(svLogicVecVal* v) { update_3d1(v, 121); } void i_pack_struct_0d(svLogicVecVal* v) { update_0d(v, 7); } void i_pack_struct_1d(svLogicVecVal* v) { update_1d(v, 7); } void i_pack_struct_2d(svLogicVecVal* v) { update_2d(v, 7); } void i_pack_struct_3d(svLogicVecVal* v) { update_3d(v, 7); } void i_pack_struct_1d1(svLogicVecVal* v) { update_1d1(v, 7); } void i_pack_struct_2d1(svLogicVecVal* v) { update_2d1(v, 7); } void i_pack_struct_3d1(svLogicVecVal* v) { update_3d1(v, 7); } #ifndef NO_UNPACK_STRUCT void i_unpack_struct_0d(unpack_struct_t* v) { if (!compare(v->val, 42, 121)) stop(); set_uint(v->val, 43, 121); } void i_unpack_struct_1d(unpack_struct_t* v) { if (!compare(v[0].val, 43, 121)) stop(); if (!compare(v[1].val, 44, 121)) stop(); set_uint(v[0].val, 44, 121); set_uint(v[1].val, 45, 121); } void i_unpack_struct_2d(unpack_struct_t* v) { if (!compare(v[0 * 2 + 1].val, 45, 121)) stop(); if (!compare(v[1 * 2 + 1].val, 46, 121)) stop(); if (!compare(v[2 * 2 + 1].val, 47, 121)) stop(); set_uint(v[0 * 2 + 1].val, 46, 121); set_uint(v[1 * 2 + 1].val, 47, 121); set_uint(v[2 * 2 + 1].val, 48, 121); } void i_unpack_struct_3d(unpack_struct_t* v) { if (!compare(v[(0 * 3 + 0) * 2 + 0].val, 48, 121)) stop(); if (!compare(v[(1 * 3 + 0) * 2 + 0].val, 49, 121)) stop(); if (!compare(v[(2 * 3 + 0) * 2 + 0].val, 50, 121)) stop(); if (!compare(v[(3 * 3 + 0) * 2 + 0].val, 51, 121)) stop(); set_uint(v[(0 * 3 + 0) * 2 + 0].val, 49, 121); set_uint(v[(1 * 3 + 0) * 2 + 0].val, 50, 121); set_uint(v[(2 * 3 + 0) * 2 + 0].val, 51, 121); set_uint(v[(3 * 3 + 0) * 2 + 0].val, 52, 121); } void i_unpack_struct_1d1(unpack_struct_t* v) { if (!compare(v[0].val, 52, 121)) stop(); set_uint(v[0].val, 53, 121); } void i_unpack_struct_2d(unpack_struct_t* v) { if (!compare(v[0].val, 53, 121)) stop(); set_uint(v[0].val, 54, 121); } void i_unpack_struct_3d(unpack_struct_t* v) { if (!compare(v[0].val, 54, 121)) stop(); set_uint(v[0].val, 55, 121); #endif void check_exports() { { char byte_array[4][3][2]; set_values(byte_array); e_byte_0d(&byte_array[3][2][1]); if (!check_0d(byte_array[3][2][1])) stop(); e_byte_1d(&byte_array[2][1][0]); if (!check_1d(byte_array[2][1])) stop(); e_byte_2d(&byte_array[1][0][0]); if (!check_2d(byte_array[1])) stop(); e_byte_3d(&byte_array[0][0][0]); if (!check_3d(byte_array)) stop(); } { char array[1][1][1]; array[0][0][0] = 52; e_byte_1d1(&array[0][0][0]); if (!check_1d1(array[0][0])) stop(); array[0][0][0] = 53; e_byte_2d1(&array[0][0][0]); if (!check_2d1(array[0])) stop(); array[0][0][0] = 54; e_byte_3d1(&array[0][0][0]); if (!check_3d1(array)) stop(); } { unsigned char byte_unsigned_array[4][3][2]; set_values(byte_unsigned_array); e_byte_unsigned_0d(&byte_unsigned_array[3][2][1]); if (!check_0d(byte_unsigned_array[3][2][1])) stop(); e_byte_unsigned_1d(&byte_unsigned_array[2][1][0]); if (!check_1d(byte_unsigned_array[2][1])) stop(); e_byte_unsigned_2d(&byte_unsigned_array[1][0][0]); if (!check_2d(byte_unsigned_array[1])) stop(); e_byte_unsigned_3d(&byte_unsigned_array[0][0][0]); if (!check_3d(byte_unsigned_array)) stop(); } { unsigned char array[1][1][1]; array[0][0][0] = 52; e_byte_unsigned_1d1(&array[0][0][0]); if (!check_1d1(array[0][0])) stop(); array[0][0][0] = 53; e_byte_unsigned_2d1(&array[0][0][0]); if (!check_2d1(array[0])) stop(); array[0][0][0] = 54; e_byte_unsigned_3d1(&array[0][0][0]); if (!check_3d1(array)) stop(); } { short shortint_array[4][3][2]; set_values(shortint_array); e_shortint_0d(&shortint_array[3][2][1]); if (!check_0d(shortint_array[3][2][1])) stop(); e_shortint_1d(&shortint_array[2][1][0]); if (!check_1d(shortint_array[2][1])) stop(); e_shortint_2d(&shortint_array[1][0][0]); if (!check_2d(shortint_array[1])) stop(); e_shortint_3d(&shortint_array[0][0][0]); if (!check_3d(shortint_array)) stop(); } { short array[1][1][1]; array[0][0][0] = 52; e_shortint_1d1(&array[0][0][0]); if (!check_1d1(array[0][0])) stop(); array[0][0][0] = 53; e_shortint_2d1(&array[0][0][0]); if (!check_2d1(array[0])) stop(); array[0][0][0] = 54; e_shortint_3d1(&array[0][0][0]); if (!check_3d1(array)) stop(); } { unsigned short shortint_unsigned_array[4][3][2]; set_values(shortint_unsigned_array); e_shortint_unsigned_0d(&shortint_unsigned_array[3][2][1]); if (!check_0d(shortint_unsigned_array[3][2][1])) stop(); e_shortint_unsigned_1d(&shortint_unsigned_array[2][1][0]); if (!check_1d(shortint_unsigned_array[2][1])) stop(); e_shortint_unsigned_2d(&shortint_unsigned_array[1][0][0]); if (!check_2d(shortint_unsigned_array[1])) stop(); e_shortint_unsigned_3d(&shortint_unsigned_array[0][0][0]); if (!check_3d(shortint_unsigned_array)) stop(); } { unsigned short array[1][1][1]; array[0][0][0] = 52; e_shortint_unsigned_1d1(&array[0][0][0]); if (!check_1d1(array[0][0])) stop(); array[0][0][0] = 53; e_shortint_unsigned_2d1(&array[0][0][0]); if (!check_2d1(array[0])) stop(); array[0][0][0] = 54; e_shortint_unsigned_3d1(&array[0][0][0]); if (!check_3d1(array)) stop(); } { int int_array[4][3][2]; set_values(int_array); e_int_0d(&int_array[3][2][1]); if (!check_0d(int_array[3][2][1])) stop(); e_int_1d(&int_array[2][1][0]); if (!check_1d(int_array[2][1])) stop(); e_int_2d(&int_array[1][0][0]); if (!check_2d(int_array[1])) stop(); e_int_3d(&int_array[0][0][0]); if (!check_3d(int_array)) stop(); } { int array[1][1][1]; array[0][0][0] = 52; e_int_1d1(&array[0][0][0]); if (!check_1d1(array[0][0])) stop(); array[0][0][0] = 53; e_int_2d1(&array[0][0][0]); if (!check_2d1(array[0])) stop(); array[0][0][0] = 54; e_int_3d1(&array[0][0][0]); if (!check_3d1(array)) stop(); } { unsigned int int_unsigned_array[4][3][2]; set_values(int_unsigned_array); e_int_unsigned_0d(&int_unsigned_array[3][2][1]); if (!check_0d(int_unsigned_array[3][2][1])) stop(); e_int_unsigned_1d(&int_unsigned_array[2][1][0]); if (!check_1d(int_unsigned_array[2][1])) stop(); e_int_unsigned_2d(&int_unsigned_array[1][0][0]); if (!check_2d(int_unsigned_array[1])) stop(); e_int_unsigned_3d(&int_unsigned_array[0][0][0]); if (!check_3d(int_unsigned_array)) stop(); } { unsigned int array[1][1][1]; array[0][0][0] = 52; e_int_unsigned_1d1(&array[0][0][0]); if (!check_1d1(array[0][0])) stop(); array[0][0][0] = 53; e_int_unsigned_2d1(&array[0][0][0]); if (!check_2d1(array[0])) stop(); array[0][0][0] = 54; e_int_unsigned_3d1(&array[0][0][0]); if (!check_3d1(array)) stop(); } { sv_longint_t longint_array[4][3][2]; set_values(longint_array); e_longint_0d(&longint_array[3][2][1]); if (!check_0d(longint_array[3][2][1])) stop(); e_longint_1d(&longint_array[2][1][0]); if (!check_1d(longint_array[2][1])) stop(); e_longint_2d(&longint_array[1][0][0]); if (!check_2d(longint_array[1])) stop(); e_longint_3d(&longint_array[0][0][0]); if (!check_3d(longint_array)) stop(); } { sv_longint_t array[1][1][1]; array[0][0][0] = 52; e_longint_1d1(&array[0][0][0]); if (!check_1d1(array[0][0])) stop(); array[0][0][0] = 53; e_longint_2d1(&array[0][0][0]); if (!check_2d1(array[0])) stop(); array[0][0][0] = 54; e_longint_3d1(&array[0][0][0]); if (!check_3d1(array)) stop(); } { sv_longint_unsigned_t longint_unsigned_array[4][3][2]; set_values(longint_unsigned_array); e_longint_unsigned_0d(&longint_unsigned_array[3][2][1]); if (!check_0d(longint_unsigned_array[3][2][1])) stop(); e_longint_unsigned_1d(&longint_unsigned_array[2][1][0]); if (!check_1d(longint_unsigned_array[2][1])) stop(); e_longint_unsigned_2d(&longint_unsigned_array[1][0][0]); if (!check_2d(longint_unsigned_array[1])) stop(); e_longint_unsigned_3d(&longint_unsigned_array[0][0][0]); if (!check_3d(longint_unsigned_array)) stop(); } { sv_longint_unsigned_t array[1][1][1]; array[0][0][0] = 52; e_longint_unsigned_1d1(&array[0][0][0]); if (!check_1d1(array[0][0])) stop(); array[0][0][0] = 53; e_longint_unsigned_2d1(&array[0][0][0]); if (!check_2d1(array[0])) stop(); array[0][0][0] = 54; e_longint_unsigned_3d1(&array[0][0][0]); if (!check_3d1(array)) stop(); } #ifndef NO_TIME { svLogicVecVal time_array[4][3][2][2]; set_values(time_array, 64); e_time_0d(time_array[3][2][1]); if (!check_0d(time_array[3][2][1], 64)) stop(); e_time_1d(time_array[2][1][0]); if (!check_1d(time_array[2][1], 64)) stop(); e_time_2d(time_array[1][0][0]); if (!check_2d(time_array[1], 64)) stop(); e_time_3d(time_array[0][0][0]); if (!check_3d(time_array, 64)) stop(); } { svLogicVecVal array[1][1][1][2]; set_uint(array[0][0][0], 52, 64); e_time_1d1(array[0][0][0]); if (!check_1d1(array[0][0], 64)) stop(); set_uint(array[0][0][0], 53, 64); e_time_2d1(array[0][0][0]); if (!check_2d1(array[0], 64)) stop(); set_uint(array[0][0][0], 54, 64); e_time_3d1(array[0][0][0]); if (!check_3d1(array, 64)) stop(); } #endif #ifndef NO_INTEGER { svLogicVecVal integer_array[4][3][2][1]; set_values(integer_array, 32); e_integer_0d(integer_array[3][2][1]); if (!check_0d(integer_array[3][2][1], 32)) stop(); e_integer_1d(integer_array[2][1][0]); if (!check_1d(integer_array[2][1], 32)) stop(); e_integer_2d(integer_array[1][0][0]); if (!check_2d(integer_array[1], 32)) stop(); e_integer_3d(integer_array[0][0][0]); if (!check_3d(integer_array, 32)) stop(); } { svLogicVecVal array[1][1][1][1]; set_uint(array[0][0][0], 52, 22); e_integer_1d1(array[0][0][0]); if (!check_1d1(array[0][0], 32)) stop(); set_uint(array[0][0][0], 53, 32); e_integer_2d1(array[0][0][0]); if (!check_2d1(array[0], 32)) stop(); set_uint(array[0][0][0], 54, 32); e_integer_3d1(array[0][0][0]); if (!check_3d1(array, 32)) stop(); } #endif { double real_array[4][3][2]; set_values(real_array); e_real_0d(&real_array[3][2][1]); if (!check_0d(real_array[3][2][1])) stop(); e_real_1d(&real_array[2][1][0]); if (!check_1d(real_array[2][1])) stop(); e_real_2d(&real_array[1][0][0]); if (!check_2d(real_array[1])) stop(); e_real_3d(&real_array[0][0][0]); if (!check_3d(real_array)) stop(); } { double array[1][1][1]; array[0][0][0] = 52; e_real_1d1(&array[0][0][0]); if (!check_1d1(array[0][0])) stop(); array[0][0][0] = 53; e_real_2d1(&array[0][0][0]); if (!check_2d1(array[0])) stop(); array[0][0][0] = 54; e_real_3d1(&array[0][0][0]); if (!check_3d1(array)) stop(); } #ifndef NO_SHORTREAL { float shortreal_array[4][3][2]; set_values(shortreal_array); e_shortreal_0d(&shortreal_array[3][2][1]); if (!check_0d(shortreal_array[3][2][1])) stop(); e_shortreal_1d(&shortreal_array[2][1][0]); if (!check_1d(shortreal_array[2][1])) stop(); e_shortreal_2d(&shortreal_array[1][0][0]); if (!check_2d(shortreal_array[1])) stop(); e_shortreal_3d(&shortreal_array[0][0][0]); if (!check_3d(shortreal_array)) stop(); } { float array[1][1][1]; array[0][0][0] = 52; e_shortreal_1d1(&array[0][0][0]); if (!check_1d1(array[0][0])) stop(); array[0][0][0] = 53; e_shortreal_2d1(&array[0][0][0]); if (!check_2d1(array[0])) stop(); array[0][0][0] = 54; e_shortreal_3d1(&array[0][0][0]); if (!check_3d1(array)) stop(); } #endif { void* chandle_array[4][3][2]; for (int i = 0; i < 4; ++i) for (int j = 0; j < 3; ++j) for (int k = 0; k < 2; ++k) chandle_array[i][j][k] = NULL; chandle_array[3][2][1] = get_non_null(); e_chandle_0d(&chandle_array[3][2][1]); if (chandle_array[3][2][1]) stop(); chandle_array[2][1][0] = get_non_null(); chandle_array[2][1][1] = get_non_null(); e_chandle_1d(&chandle_array[2][1][0]); if (chandle_array[2][1][0]) stop(); if (chandle_array[2][1][1]) stop(); chandle_array[1][0][1] = get_non_null(); chandle_array[1][1][1] = get_non_null(); chandle_array[1][2][1] = get_non_null(); e_chandle_2d(&chandle_array[1][0][0]); if (chandle_array[1][0][1]) stop(); if (chandle_array[1][1][1]) stop(); if (chandle_array[1][2][1]) stop(); chandle_array[0][0][0] = get_non_null(); chandle_array[1][0][0] = get_non_null(); chandle_array[2][0][0] = get_non_null(); chandle_array[3][0][0] = get_non_null(); e_chandle_3d(&chandle_array[0][0][0]); if (chandle_array[0][0][0]) stop(); if (chandle_array[1][0][0]) stop(); if (chandle_array[2][0][0]) stop(); if (chandle_array[3][0][0]) stop(); } { void* array[1][1][1]; array[0][0][0] = get_non_null(); e_chandle_1d1(&array[0][0][0]); if (array[0][0][0]) stop(); array[0][0][0] = get_non_null(); e_chandle_2d1(&array[0][0][0]); if (array[0][0][0]) stop(); array[0][0][0] = get_non_null(); e_chandle_3d1(&array[0][0][0]); if (array[0][0][0]) stop(); } { const char* string_array[4][3][2]; for (int i = 0; i < 4; ++i) for (int j = 0; j < 3; ++j) for (int k = 0; k < 2; ++k) string_array[i][j][k] = ""; string_array[3][2][1] = "42"; e_string_0d(&string_array[3][2][1]); if (!compare(string_array[3][2][1], "43")) stop(); string_array[2][1][0] = "43"; string_array[2][1][1] = "44"; e_string_1d(&string_array[2][1][0]); if (!compare(string_array[2][1][0], "44")) stop(); if (!compare(string_array[2][1][1], "45")) stop(); string_array[1][0][1] = "45"; string_array[1][1][1] = "46"; string_array[1][2][1] = "47"; e_string_2d(&string_array[1][0][0]); if (!compare(string_array[1][0][1], "46")) stop(); if (!compare(string_array[1][1][1], "47")) stop(); if (!compare(string_array[1][2][1], "48")) stop(); string_array[0][0][0] = "48"; string_array[1][0][0] = "49"; string_array[2][0][0] = "50"; string_array[3][0][0] = "51"; e_string_3d(&string_array[0][0][0]); if (!compare(string_array[0][0][0], "49")) stop(); if (!compare(string_array[1][0][0], "50")) stop(); if (!compare(string_array[2][0][0], "51")) stop(); if (!compare(string_array[3][0][0], "52")) stop(); } { const char* array[1][1][1]; array[0][0][0] = "52"; e_string_1d1(&array[0][0][0]); if (!compare(array[0][0][0], "53")) stop(); array[0][0][0] = "53"; e_string_2d1(&array[0][0][0]); if (!compare(array[0][0][0], "54")) stop(); array[0][0][0] = "54"; e_string_3d1(&array[0][0][0]); if (!compare(array[0][0][0], "55")) stop(); } { svBitVecVal bit7_array[4][3][2][1]; set_values(bit7_array, 7); e_bit7_0d(bit7_array[3][2][1]); if (!check_0d(bit7_array[3][2][1], 7)) stop(); e_bit7_1d(bit7_array[2][1][0]); if (!check_1d(bit7_array[2][1], 7)) stop(); e_bit7_2d(bit7_array[1][0][0]); if (!check_2d(bit7_array[1], 7)) stop(); e_bit7_3d(bit7_array[0][0][0]); if (!check_3d(bit7_array, 7)) stop(); } { svBitVecVal array[1][1][1][1]; set_uint(array[0][0][0], 52, 7); e_bit7_1d1(array[0][0][0]); if (!check_1d1(array[0][0], 7)) stop(); set_uint(array[0][0][0], 53, 7); e_bit7_2d1(array[0][0][0]); if (!check_2d1(array[0], 7)) stop(); set_uint(array[0][0][0], 54, 7); e_bit7_3d1(array[0][0][0]); if (!check_3d1(array, 7)) stop(); } { svBitVecVal bit121_array[4][3][2][4]; set_values(bit121_array, 121); e_bit121_0d(bit121_array[3][2][1]); if (!check_0d(bit121_array[3][2][1], 121)) stop(); e_bit121_1d(bit121_array[2][1][0]); if (!check_1d(bit121_array[2][1], 121)) stop(); e_bit121_2d(bit121_array[1][0][0]); if (!check_2d(bit121_array[1], 121)) stop(); e_bit121_3d(bit121_array[0][0][0]); if (!check_3d(bit121_array, 121)) stop(); } { svBitVecVal array[1][1][1][4]; set_uint(array[0][0][0], 52, 121); e_bit121_1d1(array[0][0][0]); if (!check_1d1(array[0][0], 121)) stop(); set_uint(array[0][0][0], 53, 121); e_bit121_2d1(array[0][0][0]); if (!check_2d1(array[0], 121)) stop(); set_uint(array[0][0][0], 54, 121); e_bit121_3d1(array[0][0][0]); if (!check_3d1(array, 121)) stop(); } { svLogicVecVal logic7_array[4][3][2][1]; set_values(logic7_array, 7); e_logic7_0d(logic7_array[3][2][1]); if (!check_0d(logic7_array[3][2][1], 7)) stop(); e_logic7_1d(logic7_array[2][1][0]); if (!check_1d(logic7_array[2][1], 7)) stop(); e_logic7_2d(logic7_array[1][0][0]); if (!check_2d(logic7_array[1], 7)) stop(); e_logic7_3d(logic7_array[0][0][0]); if (!check_3d(logic7_array, 7)) stop(); } { svLogicVecVal array[1][1][1][1]; set_uint(array[0][0][0], 52, 7); e_logic7_1d1(array[0][0][0]); if (!check_1d1(array[0][0], 7)) stop(); set_uint(array[0][0][0], 53, 7); e_logic7_2d1(array[0][0][0]); if (!check_2d1(array[0], 7)) stop(); set_uint(array[0][0][0], 54, 7); e_logic7_3d1(array[0][0][0]); if (!check_3d1(array, 7)) stop(); } { svLogicVecVal logic121_array[4][3][2][4]; set_values(logic121_array, 121); e_logic121_0d(logic121_array[3][2][1]); if (!check_0d(logic121_array[3][2][1], 121)) stop(); e_logic121_1d(logic121_array[2][1][0]); if (!check_1d(logic121_array[2][1], 121)) stop(); e_logic121_2d(logic121_array[1][0][0]); if (!check_2d(logic121_array[1], 121)) stop(); e_logic121_3d(logic121_array[0][0][0]); if (!check_3d(logic121_array, 121)) stop(); } { svLogicVecVal array[1][1][1][4]; set_uint(array[0][0][0], 52, 121); e_logic121_1d1(array[0][0][0]); if (!check_1d1(array[0][0], 121)) stop(); set_uint(array[0][0][0], 53, 121); e_logic121_2d1(array[0][0][0]); if (!check_2d1(array[0], 121)) stop(); set_uint(array[0][0][0], 54, 121); e_logic121_3d1(array[0][0][0]); if (!check_3d1(array, 121)) stop(); } { svLogicVecVal pack_struct_array[4][3][2][1]; set_values(pack_struct_array, 7); e_pack_struct_0d(pack_struct_array[3][2][1]); if (!check_0d(pack_struct_array[3][2][1], 7)) stop(); e_pack_struct_1d(pack_struct_array[2][1][0]); if (!check_1d(pack_struct_array[2][1], 7)) stop(); e_pack_struct_2d(pack_struct_array[1][0][0]); if (!check_2d(pack_struct_array[1], 7)) stop(); e_pack_struct_3d(pack_struct_array[0][0][0]); if (!check_3d(pack_struct_array, 7)) stop(); } { svLogicVecVal array[1][1][1][1]; set_uint(array[0][0][0], 52, 7); e_pack_struct_1d1(array[0][0][0]); if (!check_1d1(array[0][0], 7)) stop(); set_uint(array[0][0][0], 53, 7); e_pack_struct_2d1(array[0][0][0]); if (!check_2d1(array[0], 7)) stop(); set_uint(array[0][0][0], 54, 7); e_pack_struct_3d1(array[0][0][0]); if (!check_3d1(array, 7)) stop(); } #ifndef NO_UNPACK_STRUCT { unpack_struct_t unpack_struct_array[4][3][2]; set_uint(unpack_struct_array[3][2][1].val, 42, 121); e_unpack_struct_0d(&unpack_struct_array[3][2][1]); if (!compare(unpack_struct_array[3][2][1].val, 43, 121)) stop(); set_uint(unpack_struct_array[2][1][0].val, 43, 121); set_uint(unpack_struct_array[2][1][1].val, 44, 121); e_unpack_struct_1d(&unpack_struct_array[2][1][0]); if (!compare(unpack_struct_array[2][1][0].val, 44, 121)) stop(); if (!compare(unpack_struct_array[2][1][1].val, 45, 121)) stop(); set_uint(unpack_struct_array[1][0][1].val, 45, 121); set_uint(unpack_struct_array[1][1][1].val, 46, 121); set_uint(unpack_struct_array[1][2][1].val, 47, 121); e_unpack_struct_2d(&unpack_struct_array[1][0][0]); if (!compare(unpack_struct_array[1][0][1].val, 46, 121)) stop(); if (!compare(unpack_struct_array[1][1][1].val, 47, 121)) stop(); if (!compare(unpack_struct_array[1][2][1].val, 48, 121)) stop(); set_uint(unpack_struct_array[0][0][0].val, 48, 121); set_uint(unpack_struct_array[1][0][0].val, 49, 121); set_uint(unpack_struct_array[2][0][0].val, 50, 121); set_uint(unpack_struct_array[3][0][0].val, 51, 121); e_unpack_struct_3d(&unpack_struct_array[0][0][0]); if (!compare(unpack_struct_array[0][0][0].val, 49, 121)) stop(); if (!compare(unpack_struct_array[1][0][0].val, 50, 121)) stop(); if (!compare(unpack_struct_array[2][0][0].val, 51, 121)) stop(); if (!compare(unpack_struct_array[3][0][0].val, 52, 121)) stop(); } { unpack_struct_t array[1][1][1]; set_uint(array[0][0][0].val, 52, 121); e_unpack_struct_1d1(&array[0][0][0]); if (!compare(array[0][0][0].val, 53, 121)) stop(); set_uint(array[0][0][0].val, 53, 121); e_unpack_struct_2d1(&array[0][0][0]); if (!compare(array[0][0][0].val, 53, 121)) stop(); set_uint(array[0][0][0].val, 53, 121); e_unpack_struct_3d1(&array[0][0][0]); if (!compare(array[0][0][0].val, 53, 121)) stop(); } #endif } verilator-5.042/test_regress/t/t_interface_param2.py0000755000542200017500000000073415101701376023174 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_gate_inline_wide_noexclude_const.py0000755000542200017500000000122715101701376026532 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=['--stats', '--expand-limit 5']) test.file_grep(test.stats, r'Optimizations, Gate excluded wide expressions\s+(\d+)', 0) test.file_grep(test.stats, r'Optimizations, Gate sigs deleted\s+(\d+)', 2) test.passes() verilator-5.042/test_regress/t/t_lint_block_redecl_bad.v0000644000542200017500000000065715101701376024054 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 //bug485, but see t_gen_forif.v for an OK example. module t; always_comb begin integer i; for(i=0; i<10; i++ ) begin: COMB end for(i=0; i<9; i++ ) begin: COMB end end endmodule verilator-5.042/test_regress/t/t_math_repl_bad.out0000644000542200017500000000274315101701376022731 0ustar mahmoudyfreeshell%Error-ZEROREPL: t/t_math_repl_bad.v:12:14: Replication value of 0 is only legal under a concatenation (IEEE 1800-2023 11.4.12.1) : ... note: In instance 't' 12 | o = {0 {1'b1}}; | ^ ... For error description see https://verilator.org/warn/ZEROREPL?v=latest %Warning-WIDTHEXPAND: t/t_math_repl_bad.v:12:9: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's REPLICATE generates 1 bits. : ... note: In instance 't' 12 | o = {0 {1'b1}}; | ^ ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. %Error: t/t_math_repl_bad.v:13:43: Replication value isn't a constant. : ... note: In instance 't' 13 | o = {$test$plusargs("NON-CONSTANT") {1'b1}}; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Warning-WIDTHEXPAND: t/t_math_repl_bad.v:13:9: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's REPLICATE generates 1 bits. : ... note: In instance 't' 13 | o = {$test$plusargs("NON-CONSTANT") {1'b1}}; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_dpi_open_query.cpp0000644000542200017500000000646715101701376023154 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2020 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "svdpi.h" // clang-format off #if defined(VERILATOR) // Verilator # include "Vt_dpi_open_query__Dpi.h" #elif defined(VCS) // VCS # include "../vc_hdrs.h" #elif defined(NCSC) // NC # include "dpi-imp.h" #elif defined(MS) // ModelSim # include "dpi.h" #else # error "Unknown simulator for DPI test" #endif // clang-format on //====================================================================== // Implementations of imported functions //====================================================================== // These are simple wrappers for the array querying functions themselves, // see IEEE 1800-2023 H.12.2. Sadly on the SV side these have different // signatures, and hence need to have different names here as well. // 1 open dimension int cSvLeft1(const svOpenArrayHandle h, int d) { return svLeft(h, d); } int cSvRight1(const svOpenArrayHandle h, int d) { return svRight(h, d); } int cSvLow1(const svOpenArrayHandle h, int d) { return svLow(h, d); } int cSvHigh1(const svOpenArrayHandle h, int d) { return svHigh(h, d); } int cSvIncrement1(const svOpenArrayHandle h, int d) { return svIncrement(h, d); } int cSvSize1(const svOpenArrayHandle h, int d) { return svSize(h, d); } int cSvDimensions1(const svOpenArrayHandle h) { return svDimensions(h); } // 2 open dimensions int cSvLeft2(const svOpenArrayHandle h, int d) { return svLeft(h, d); } int cSvRight2(const svOpenArrayHandle h, int d) { return svRight(h, d); } int cSvLow2(const svOpenArrayHandle h, int d) { return svLow(h, d); } int cSvHigh2(const svOpenArrayHandle h, int d) { return svHigh(h, d); } int cSvIncrement2(const svOpenArrayHandle h, int d) { return svIncrement(h, d); } int cSvSize2(const svOpenArrayHandle h, int d) { return svSize(h, d); } int cSvDimensions2(const svOpenArrayHandle h) { return svDimensions(h); } // 3 open dimensions int cSvLeft3(const svOpenArrayHandle h, int d) { return svLeft(h, d); } int cSvRight3(const svOpenArrayHandle h, int d) { return svRight(h, d); } int cSvLow3(const svOpenArrayHandle h, int d) { return svLow(h, d); } int cSvHigh3(const svOpenArrayHandle h, int d) { return svHigh(h, d); } int cSvIncrement3(const svOpenArrayHandle h, int d) { return svIncrement(h, d); } int cSvSize3(const svOpenArrayHandle h, int d) { return svSize(h, d); } int cSvDimensions3(const svOpenArrayHandle h) { return svDimensions(h); } // 4 open dimensions int cSvLeft4(const svOpenArrayHandle h, int d) { return svLeft(h, d); } int cSvRight4(const svOpenArrayHandle h, int d) { return svRight(h, d); } int cSvLow4(const svOpenArrayHandle h, int d) { return svLow(h, d); } int cSvHigh4(const svOpenArrayHandle h, int d) { return svHigh(h, d); } int cSvIncrement4(const svOpenArrayHandle h, int d) { return svIncrement(h, d); } int cSvSize4(const svOpenArrayHandle h, int d) { return svSize(h, d); } int cSvDimensions4(const svOpenArrayHandle h) { return svDimensions(h); } verilator-5.042/test_regress/t/t_math_reverse.py0000755000542200017500000000073415101701376022456 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_array_fst_sc.py0000755000542200017500000000130215101701376023617 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_trace_array.v" if not test.have_sc: test.skip("No SystemC installed") test.compile(verilator_flags2=['--sc --trace-fst --trace-structs --trace-max-width 0']) test.execute() test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_unpacked_to_packed_param.py0000755000542200017500000000072615101701376024756 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios("vlt") test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_hidden.v0000644000542200017500000000270115101701376023053 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=1; ifc ifc(); // Cell name hides interface's name assign ifc.ifi = 55; sub sub (.isub(ifc)); // Cell name hides module's name int om; mod_or_type mot (.*); hides_with_type hides_type(); hides_with_decl hides_decl(); always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 20) begin if (om != 22) $stop; if (mot.LOCAL != 22) $stop; if (ifc.ifo != 55) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module sub ( ifc isub ); always @* begin isub.ifo = isub.ifi; end endmodule module mod_or_type(output int om); localparam LOCAL = 22; initial om = 22; endmodule module hides_with_type(); typedef int ifc; // Hides interface typedef int mod_or_type; // Hides module ifc /*=int*/ hides_ifc; mod_or_type /*=int*/ hides_mod; initial hides_ifc = 33; initial hides_mod = 44; endmodule module hides_with_decl(); int ifc; // Hides interface int mod_or_type; // Hides module initial ifc = 66; initial mod_or_type = 77; endmodule interface ifc; localparam LOCAL = 12; int ifi; int ifo; endinterface verilator-5.042/test_regress/t/t_select_bound1.py0000755000542200017500000000073415101701376022521 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_display_bad.out0000644000542200017500000000057715101701376022426 0ustar mahmoudyfreeshell%Error: t/t_display_bad.v:11:7: Missing arguments for $display-like format 11 | $display("%x"); | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_display_bad.v:13:7: Unknown $display-like format code: '%q' 13 | $display("%q"); | ^~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_class_unsup_bad.py0000755000542200017500000000076315101701376023141 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_sv_cpu.py0000755000542200017500000000276315101701376021275 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') # 22-Mar-2012: Modifications for this test contributed by Jeremy Bennett, # Embecosm. test.compile( # Taken from the original VCS command line. v_flags2=[ "t/t_sv_cpu_code/timescale.sv", "t/t_sv_cpu_code/program_h.sv", "t/t_sv_cpu_code/pads_h.sv", "t/t_sv_cpu_code/ports_h.sv", "t/t_sv_cpu_code/pinout_h.sv", "t/t_sv_cpu_code/genbus_if.sv", "t/t_sv_cpu_code/pads_if.sv", "t/t_sv_cpu_code/adrdec.sv", "t/t_sv_cpu_code/pad_gpio.sv", "t/t_sv_cpu_code/pad_vdd.sv", "t/t_sv_cpu_code/pad_gnd.sv", "t/t_sv_cpu_code/pads.sv", "t/t_sv_cpu_code/ports.sv", "t/t_sv_cpu_code/ac_dig.sv", "t/t_sv_cpu_code/ac_ana.sv", "t/t_sv_cpu_code/ac.sv", "t/t_sv_cpu_code/cpu.sv", "t/t_sv_cpu_code/chip.sv" ], vcs_flags2=["-R -sverilog +memcbk -y t/t_sv_cpu_code +libext+.sv+ +incdir+t/t_sv_cpu_code"], verilator_flags2=[ "-y t/t_sv_cpu_code +libext+.sv+ +incdir+t/t_sv_cpu_code --top-module t", "--timescale-override 1ns/1ps" ], iv_flags2=["-yt/t_sv_cpu_code -It/t_sv_cpu_code -Y.sv"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_clocking_bad1.out0000644000542200017500000000055615101701376022630 0ustar mahmoudyfreeshell%Error: t/t_clocking_bad1.v:16:12: Only one default clocking block allowed per module (IEEE 1800-2023 14.12) : ... note: In instance 't' 16 | default clocking @(posedge clk); | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_assert_iff_clk_unsup.v0000644000542200017500000000071315101701376024011 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ clk ); input clk; int cyc = 0; logic val = 0; always @(posedge clk) begin cyc <= cyc + 1; val = ~val; end assert property (disable iff (cyc < 5) @(posedge clk) cyc >= 5); endmodule verilator-5.042/test_regress/t/t_case_inside_bad.py0000755000542200017500000000076615101701376023053 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_latch_bad_2.py0000755000542200017500000000076615101701376023147 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_var_const.v0000644000542200017500000000114315101701376021575 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; const logic [2:0] five = 3'd5; const logic unsigned [31:0] var_const = 22; logic [7:0] res_const; assign res_const = var_const[7:0]; // bug693 always @ (posedge clk) begin if (five !== 3'd5) $stop; if (res_const !== 8'd22) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_struct_nest.py0000755000542200017500000000070615101701376022346 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.042/test_regress/t/t_sv_cpu.v0000644000542200017500000000705515101701376021106 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: System Verilog test of a complete CPU // // This code instantiates and runs a simple CPU written in System Verilog. // // This file ONLY is placed into the Public Domain, for any use, without // warranty. // SPDX-License-Identifier: CC0-1.0 // Contributed 2012 by M W Lund, Atmel Corporation and Jeremy Bennett, Embecosm. module t (/*AUTOARG*/ // Inputs clk ); input clk; /*AUTOWIRE*/ // ************************************************************************** // Regs and Wires // ************************************************************************** reg rst; integer rst_count; integer clk_count; testbench testbench_i (/*AUTOINST*/ // Inputs .clk (clk), .rst (rst)); // ************************************************************************** // Reset Generation // ************************************************************************** initial begin rst = 1'b1; rst_count = 0; end always @( posedge clk ) begin if (rst_count < 2) begin rst_count++; end else begin rst = 1'b0; end end // ************************************************************************** // Drive simulation for 500 clock cycles // ************************************************************************** initial begin `ifdef TEST_VERBOSE $display( "[testbench] - Start of simulation ----------------------- " ); `endif clk_count = 0; end always @( posedge clk ) begin if (90 == clk_count) begin $finish (); end else begin clk_count++; end end final begin `ifdef TEST_VERBOSE $display( "[testbench] - End of simulation ------------------------- " ); `endif $write("*-* All Finished *-*\n"); end endmodule module testbench (/*AUTOARG*/ // Inputs clk, rst ); input clk; input rst; // ************************************************************************** // Local parameters // ************************************************************************** localparam NUMPADS = $size( pinout ); // ************************************************************************** // Regs and Wires // ************************************************************************** // **** Pinout **** `ifdef VERILATOR // see t_tri_array wire [NUMPADS:1] pad; // GPIO Pads (PORT{A,...,R}). `else wire pad [1:NUMPADS]; // GPIO Pads (PORT{A,...,R}). `endif // ************************************************************************** // Regs and Wires, Automatics // ************************************************************************** /*AUTOWIRE*/ // ************************************************************************** // Includes (Testbench extensions) // ************************************************************************** // N/A // ************************************************************************** // Chip Instance // ************************************************************************** chip i_chip ( /*AUTOINST*/ // Inouts .pad (pad[NUMPADS:1]), // Inputs .clk (clk), .rst (rst)); endmodule // test // Local Variables: // verilog-library-directories:("." "t_sv_cpu_code") // End: verilator-5.042/test_regress/t/t_class_field_name.py0000755000542200017500000000073415101701376023242 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_cast_signed.v0000644000542200017500000000104115101701376022057 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; logic [7:0] smaller; logic [15:0] bigger; typedef logic [15:0] bigger_t; initial begin smaller = 8'hfa; bigger = bigger_t'(signed'(smaller)); $display("%x", bigger); // NOCOMMIT if (bigger != 16'hfffa) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_implements_collision.py0000755000542200017500000000073415101701376024222 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_func_link.py0000755000542200017500000000073415101701376021742 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_param_named_2.v0000644000542200017500000000215115101701376022264 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); parameter PAR = 3; input clk; m3 m3_inst (.clk(clk)); defparam m3_inst.FROMDEFP = 19; defparam m3_inst.P2 = 2; //defparam m3_inst.P3 = PAR; defparam m3_inst.P3 = 3; integer cyc=1; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==1) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module m3 (/*AUTOARG*/ // Inputs clk ); input clk; localparam LOC = 13; parameter UNCH = 99; parameter P1 = 10; parameter P2 = 20; parameter P3 = 30; parameter FROMDEFP = 11; initial begin $display("%x %x %x",P1,P2,P3); end always @ (posedge clk) begin if (UNCH !== 99) $stop; if (P1 !== 10) $stop; if (P2 !== 2) $stop; if (P3 !== 3) $stop; if (FROMDEFP !== 19) $stop; end endmodule verilator-5.042/test_regress/t/t_trace_ena_cc.out0000644000542200017500000000246015101701376022532 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $var wire 1 # clk $end $scope module t $end $var wire 1 # clk $end $var wire 32 $ cyc [31:0] $end $var wire 32 % c_trace_on [31:0] $end $var real 64 & r $end $upscope $end $upscope $end $enddefinitions $end #0 0# b00000000000000000000000000000001 $ b00000000000000000000000000000000 % r0 & #10 1# b00000000000000000000000000000010 $ r0.1 & #15 0# #20 1# b00000000000000000000000000000011 $ b00000000000000000000000000000001 % r0.2 & #25 0# #30 1# b00000000000000000000000000000100 $ b00000000000000000000000000000010 % r0.3 & #35 0# #40 1# b00000000000000000000000000000101 $ b00000000000000000000000000000011 % r0.4 & #45 0# #50 1# b00000000000000000000000000000110 $ b00000000000000000000000000000100 % r0.5 & #55 0# #60 1# b00000000000000000000000000000111 $ b00000000000000000000000000000101 % r0.6 & #65 0# #70 1# b00000000000000000000000000001000 $ b00000000000000000000000000000110 % r0.7 & #75 0# #80 1# b00000000000000000000000000001001 $ b00000000000000000000000000000111 % r0.7999999999999999 & #85 0# #90 1# b00000000000000000000000000001010 $ b00000000000000000000000000001000 % r0.8999999999999999 & #95 0# #100 1# b00000000000000000000000000001011 $ b00000000000000000000000000001001 % r0.9999999999999999 & verilator-5.042/test_regress/t/t_interface_array4.py0000755000542200017500000000077115101701376023215 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--binary']) test.execute() test.passes() verilator-5.042/test_regress/t/t_param_array5.v0000644000542200017500000000165415101701376022171 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 //bug1578 module t; parameter N = 4; typedef logic array_t[N]; parameter array_t MASK = mask_array(); //TODO bug1578: parameter MASK = mask_array(); function array_t mask_array(); for(int i = 0; i < N; i++) begin mask_array[i] = i[0]; end endfunction array_t norm; initial begin if (N != 4) $stop; norm = mask_array(); if (norm[0] != 1'b0) $stop; if (norm[1] != 1'b1) $stop; if (norm[2] != 1'b0) $stop; if (norm[3] != 1'b1) $stop; if (MASK[0] != 1'b0) $stop; if (MASK[1] != 1'b1) $stop; if (MASK[2] != 1'b0) $stop; if (MASK[3] != 1'b1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_inst_param_comma_bad.v0000644000542200017500000000215215101701376023717 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module M #( parameter int P = 12, parameter int Q = 13 ) ( input wire i, output wire o ); assign o = i; endmodule module N #( parameter int P = 12 ) ( input wire i, output wire o ); assign o = i; endmodule module t; wire i1, o1, i2, o2, i3, o3, i4, o4, i5, o5, i6, o6; // All of these have superfluous commas after the first parameter. // All of the N instances produced a PINNOTFOUND error, however as reported in issue #4979, // none of the M instances do when they should. The copmma after the first parameter is not // allowed in verilog. M #(.P(13),) m1( .i(i1), .o(o1) ); M #(14,) m2 ( .i(i2), .o(o2) ); M #(14,) m3 ( .i(i3), .o(o3) ); N #(.P(13),) n1( .i(i4), .o(o4) ); N #(14,) n2 ( .i(i5), .o(o5) ); N #(14,) n3 ( .i(i6), .o(o6) ); endmodule verilator-5.042/test_regress/t/t_trace_fst_sc.out0000644000542200017500000002546615101701376022616 0ustar mahmoudyfreeshell$date Sat Apr 5 13:52:51 2025 $end $version fstWriter $end $timescale 1ps $end $scope module top $end $scope module t $end $var wire 1 ! clk $end $var int 32 " cyc [31:0] $end $var logic 1 # rstn $end $var real_parameter 64 $ fst_gparam_real $end $var real_parameter 64 % fst_lparam_real $end $var real 64 $ fst_real $end $var integer 32 & fst_integer [31:0] $end $var bit 1 ' fst_bit $end $var logic 1 ( fst_logic $end $var int 32 ) fst_int [31:0] $end $var shortint 16 * fst_shortint [15:0] $end $var longint 64 + fst_longint [63:0] $end $var byte 8 , fst_byte [7:0] $end $var parameter 32 - fst_parameter [31:0] $end $var parameter 32 . fst_lparam [31:0] $end $var supply0 1 / fst_supply0 $end $var supply1 1 0 fst_supply1 $end $var tri0 1 / fst_tri0 $end $var tri1 1 0 fst_tri1 $end $var tri 1 1 fst_tri $end $var wire 1 2 fst_wire $end $var logic 5 3 state [4:0] $end $scope module test $end $var wire 1 ! clk $end $var wire 1 # rstn $end $var wire 5 3 state [4:0] $end $var logic 5 4 state_w [4:0] $end $var logic 5 5 state_array[0] [4:0] $end $var logic 5 6 state_array[1] [4:0] $end $var logic 5 7 state_array[2] [4:0] $end $scope module unnamedblk1 $end $var int 32 8 i [31:0] $end $upscope $end $scope module unnamedblk2 $end $var int 32 9 i [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b00000000000000000000000000000000 9 b00000000000000000000000000000000 8 b00000 7 b00000 6 b00000 5 b00000 4 b00000 3 02 01 10 0/ b00000000000000000000000111001000 . b00000000000000000000000001111011 - b00000000 , b0000000000000000000000000000000000000000000000000000000000000000 + b0000000000000000 * b00000000000000000000000000000000 ) 0( 0' b00000000000000000000000000000000 & r4.56 % r1.23 $ 0# b00000000000000000000000000000000 " 0! $end #10 1! b00000000000000000000000000000001 " b00001 3 b10100 4 b00001 5 b00001 6 b00001 7 b00000000000000000000000000000011 8 #15 0! #20 1! b00000000000000000000000000000010 " #25 0! #30 1! b00000000000000000000000000000011 " #35 0! #40 1! b00000000000000000000000000000100 " #45 0! #50 1! b00000000000000000000000000000101 " #55 0! #60 1! b00000000000000000000000000000110 " #65 0! #70 1! b00000000000000000000000000000111 " #75 0! #80 1! b00000000000000000000000000001000 " #85 0! #90 1! b00000000000000000000000000001001 " #95 0! #100 1! b00000000000000000000000000001010 " #105 0! #110 1! b00000000000000000000000000001011 " 1# #115 0! #120 1! b00000000000000000000000000001100 " b10100 7 b01010 4 b00000000000000000000000000000010 9 #125 0! #130 1! b00101 4 b01010 7 b00000000000000000000000000001101 " b10100 6 #135 0! #140 1! b01010 6 b00000000000000000000000000001110 " b00101 7 b10110 4 b10100 5 b10100 3 #145 0! #150 1! b01010 3 b01010 5 b01011 4 b10110 7 b00000000000000000000000000001111 " b00101 6 #155 0! #160 1! b10110 6 b00000000000000000000000000010000 " b01011 7 b10001 4 b00101 5 b00101 3 #165 0! #170 1! b10110 3 b10110 5 b11100 4 b10001 7 b00000000000000000000000000010001 " b01011 6 #175 0! #180 1! b10001 6 b00000000000000000000000000010010 " b11100 7 b01110 4 b01011 5 b01011 3 #185 0! #190 1! b10001 3 b10001 5 b00111 4 b01110 7 b00000000000000000000000000010011 " b11100 6 #195 0! #200 1! b01110 6 b00000000000000000000000000010100 " b00111 7 b10111 4 b11100 5 b11100 3 #205 0! #210 1! b01110 3 b01110 5 b11111 4 b10111 7 b00000000000000000000000000010101 " b00111 6 #215 0! #220 1! b10111 6 b00000000000000000000000000010110 " b11111 7 b11011 4 b00111 5 b00111 3 #225 0! #230 1! b10111 3 b10111 5 b11001 4 b11011 7 b00000000000000000000000000010111 " b11111 6 #235 0! #240 1! b11011 6 b00000000000000000000000000011000 " b11001 7 b11000 4 b11111 5 b11111 3 #245 0! #250 1! b11011 3 b11011 5 b01100 4 b11000 7 b00000000000000000000000000011001 " b11001 6 #255 0! #260 1! b11000 6 b00000000000000000000000000011010 " b01100 7 b00110 4 b11001 5 b11001 3 #265 0! #270 1! b11000 3 b11000 5 b00011 4 b00110 7 b00000000000000000000000000011011 " b01100 6 #275 0! #280 1! b00110 6 b00000000000000000000000000011100 " b00011 7 b10101 4 b01100 5 b01100 3 #285 0! #290 1! b00110 3 b00110 5 b11110 4 b10101 7 b00000000000000000000000000011101 " b00011 6 #295 0! #300 1! b10101 6 b00000000000000000000000000011110 " b11110 7 b01111 4 b00011 5 b00011 3 #305 0! #310 1! b10101 3 b10101 5 b10011 4 b01111 7 b00000000000000000000000000011111 " b11110 6 #315 0! #320 1! b01111 6 b00000000000000000000000000100000 " b10011 7 b11101 4 b11110 5 b11110 3 #325 0! #330 1! b01111 3 b01111 5 b11010 4 b11101 7 b00000000000000000000000000100001 " b10011 6 #335 0! #340 1! b11101 6 b00000000000000000000000000100010 " b11010 7 b01101 4 b10011 5 b10011 3 #345 0! #350 1! b11101 3 b11101 5 b10010 4 b01101 7 b00000000000000000000000000100011 " b11010 6 #355 0! #360 1! b01101 6 b00000000000000000000000000100100 " b10010 7 b01001 4 b11010 5 b11010 3 #365 0! #370 1! b01101 3 b01101 5 b10000 4 b01001 7 b00000000000000000000000000100101 " b10010 6 #375 0! #380 1! b01001 6 b00000000000000000000000000100110 " b10000 7 b01000 4 b10010 5 b10010 3 #385 0! #390 1! b01001 3 b01001 5 b00100 4 b01000 7 b00000000000000000000000000100111 " b10000 6 #395 0! #400 1! b01000 6 b00000000000000000000000000101000 " b00100 7 b00010 4 b10000 5 b10000 3 #405 0! #410 1! b01000 3 b01000 5 b00001 4 b00010 7 b00000000000000000000000000101001 " b00100 6 #415 0! #420 1! b00010 6 b00000000000000000000000000101010 " b00001 7 b10100 4 b00100 5 b00100 3 #425 0! #430 1! b00010 3 b00010 5 b01010 4 b10100 7 b00000000000000000000000000101011 " b00001 6 #435 0! #440 1! b10100 6 b00000000000000000000000000101100 " b01010 7 b00101 4 b00001 5 b00001 3 #445 0! #450 1! b10100 3 b10100 5 b10110 4 b00101 7 b00000000000000000000000000101101 " b01010 6 #455 0! #460 1! b00101 6 b00000000000000000000000000101110 " b10110 7 b01011 4 b01010 5 b01010 3 #465 0! #470 1! b00101 3 b00101 5 b10001 4 b01011 7 b00000000000000000000000000101111 " b10110 6 #475 0! #480 1! b01011 6 b00000000000000000000000000110000 " b10001 7 b11100 4 b10110 5 b10110 3 #485 0! #490 1! b01011 3 b01011 5 b01110 4 b11100 7 b00000000000000000000000000110001 " b10001 6 #495 0! #500 1! b11100 6 b00000000000000000000000000110010 " b01110 7 b00111 4 b10001 5 b10001 3 #505 0! #510 1! b11100 3 b11100 5 b10111 4 b00111 7 b00000000000000000000000000110011 " b01110 6 #515 0! #520 1! b00111 6 b00000000000000000000000000110100 " b10111 7 b11111 4 b01110 5 b01110 3 #525 0! #530 1! b00111 3 b00111 5 b11011 4 b11111 7 b00000000000000000000000000110101 " b10111 6 #535 0! #540 1! b11111 6 b00000000000000000000000000110110 " b11011 7 b11001 4 b10111 5 b10111 3 #545 0! #550 1! b11111 3 b11111 5 b11000 4 b11001 7 b00000000000000000000000000110111 " b11011 6 #555 0! #560 1! b11001 6 b00000000000000000000000000111000 " b11000 7 b01100 4 b11011 5 b11011 3 #565 0! #570 1! b11001 3 b11001 5 b00110 4 b01100 7 b00000000000000000000000000111001 " b11000 6 #575 0! #580 1! b01100 6 b00000000000000000000000000111010 " b00110 7 b00011 4 b11000 5 b11000 3 #585 0! #590 1! b01100 3 b01100 5 b10101 4 b00011 7 b00000000000000000000000000111011 " b00110 6 #595 0! #600 1! b00011 6 b00000000000000000000000000111100 " b10101 7 b11110 4 b00110 5 b00110 3 #605 0! #610 1! b00011 3 b00011 5 b01111 4 b11110 7 b00000000000000000000000000111101 " b10101 6 #615 0! #620 1! b11110 6 b00000000000000000000000000111110 " b01111 7 b10011 4 b10101 5 b10101 3 #625 0! #630 1! b11110 3 b11110 5 b11101 4 b10011 7 b00000000000000000000000000111111 " b01111 6 #635 0! #640 1! b10011 6 b00000000000000000000000001000000 " b11101 7 b11010 4 b01111 5 b01111 3 #645 0! #650 1! b10011 3 b10011 5 b01101 4 b11010 7 b00000000000000000000000001000001 " b11101 6 #655 0! #660 1! b11010 6 b00000000000000000000000001000010 " b01101 7 b10010 4 b11101 5 b11101 3 #665 0! #670 1! b11010 3 b11010 5 b01001 4 b10010 7 b00000000000000000000000001000011 " b01101 6 #675 0! #680 1! b10010 6 b00000000000000000000000001000100 " b01001 7 b10000 4 b01101 5 b01101 3 #685 0! #690 1! b10010 3 b10010 5 b01000 4 b10000 7 b00000000000000000000000001000101 " b01001 6 #695 0! #700 1! b10000 6 b00000000000000000000000001000110 " b01000 7 b00100 4 b01001 5 b01001 3 #705 0! #710 1! b10000 3 b10000 5 b00010 4 b00100 7 b00000000000000000000000001000111 " b01000 6 #715 0! #720 1! b00100 6 b00000000000000000000000001001000 " b00010 7 b00001 4 b01000 5 b01000 3 #725 0! #730 1! b00100 3 b00100 5 b10100 4 b00001 7 b00000000000000000000000001001001 " b00010 6 #735 0! #740 1! b00001 6 b00000000000000000000000001001010 " b10100 7 b01010 4 b00010 5 b00010 3 #745 0! #750 1! b00001 3 b00001 5 b00101 4 b01010 7 b00000000000000000000000001001011 " b10100 6 #755 0! #760 1! b01010 6 b00000000000000000000000001001100 " b00101 7 b10110 4 b10100 5 b10100 3 #765 0! #770 1! b01010 3 b01010 5 b01011 4 b10110 7 b00000000000000000000000001001101 " b00101 6 #775 0! #780 1! b10110 6 b00000000000000000000000001001110 " b01011 7 b10001 4 b00101 5 b00101 3 #785 0! #790 1! b10110 3 b10110 5 b11100 4 b10001 7 b00000000000000000000000001001111 " b01011 6 #795 0! #800 1! b10001 6 b00000000000000000000000001010000 " b11100 7 b01110 4 b01011 5 b01011 3 #805 0! #810 1! b10001 3 b10001 5 b00111 4 b01110 7 b00000000000000000000000001010001 " b11100 6 #815 0! #820 1! b01110 6 b00000000000000000000000001010010 " b00111 7 b10111 4 b11100 5 b11100 3 #825 0! #830 1! b01110 3 b01110 5 b11111 4 b10111 7 b00000000000000000000000001010011 " b00111 6 #835 0! #840 1! b10111 6 b00000000000000000000000001010100 " b11111 7 b11011 4 b00111 5 b00111 3 #845 0! #850 1! b10111 3 b10111 5 b11001 4 b11011 7 b00000000000000000000000001010101 " b11111 6 #855 0! #860 1! b11011 6 b00000000000000000000000001010110 " b11001 7 b11000 4 b11111 5 b11111 3 #865 0! #870 1! b11011 3 b11011 5 b01100 4 b11000 7 b00000000000000000000000001010111 " b11001 6 #875 0! #880 1! b11000 6 b00000000000000000000000001011000 " b01100 7 b00110 4 b11001 5 b11001 3 #885 0! #890 1! b11000 3 b11000 5 b00011 4 b00110 7 b00000000000000000000000001011001 " b01100 6 #895 0! #900 1! b00110 6 b00000000000000000000000001011010 " b00011 7 b10101 4 b01100 5 b01100 3 #905 0! #910 1! b00110 3 b00110 5 b11110 4 b10101 7 b00000000000000000000000001011011 " b00011 6 #915 0! #920 1! b10101 6 b00000000000000000000000001011100 " b11110 7 b01111 4 b00011 5 b00011 3 #925 0! #930 1! b10101 3 b10101 5 b10011 4 b01111 7 b00000000000000000000000001011101 " b11110 6 #935 0! #940 1! b01111 6 b00000000000000000000000001011110 " b10011 7 b11101 4 b11110 5 b11110 3 #945 0! #950 1! b01111 3 b01111 5 b11010 4 b11101 7 b00000000000000000000000001011111 " b10011 6 #955 0! #960 1! b11101 6 b00000000000000000000000001100000 " b11010 7 b01101 4 b10011 5 b10011 3 #965 0! #970 1! b11101 3 b11101 5 b10010 4 b01101 7 b00000000000000000000000001100001 " b11010 6 #975 0! #980 1! b01101 6 b00000000000000000000000001100010 " b10010 7 b01001 4 b11010 5 b11010 3 #985 0! #990 1! b01101 3 b01101 5 b10000 4 b01001 7 b00000000000000000000000001100011 " b10010 6 #995 0! #1000 1! b01001 6 b00000000000000000000000001100100 " b10000 7 b01000 4 b10010 5 b10010 3 #1004 verilator-5.042/test_regress/t/t_struct_nest.v0000644000542200017500000000203115101701376022151 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef struct packed { logic [1:0] b1; logic [1:0] b2; logic [1:0] b3; logic [1:0] b4; } t__aa_bbbbbbb_ccccc_dddddd_eee; typedef struct packed { logic [31:0] a; union packed { logic [7:0] fbyte; t__aa_bbbbbbb_ccccc_dddddd_eee pairs; } b1; logic [23:0] b2; logic [7:0] c1; logic [23:0] c2; logic [31:0] d; } t__aa_bbbbbbb_ccccc_dddddd; typedef struct packed { logic [31:0] a; logic [31:0] b; logic [31:0] c; logic [31:0] d; } t__aa_bbbbbbb_ccccc_eee; typedef union packed { t__aa_bbbbbbb_ccccc_dddddd dddddd; t__aa_bbbbbbb_ccccc_eee eee; } t__aa_bbbbbbb_ccccc; module t ( input t__aa_bbbbbbb_ccccc xxxxxxx_yyyyy_zzzz, output logic [15:0] datao_pre ); always_comb datao_pre = { xxxxxxx_yyyyy_zzzz.dddddd.b1.fbyte, xxxxxxx_yyyyy_zzzz.dddddd.c1 }; endmodule verilator-5.042/test_regress/t/t_unopt_converge_ndbg_bad.py0000755000542200017500000000124015101701376024620 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_unopt_converge.v" test.compile(v_flags2=['+define+ALLOW_UNOPT', "-fno-dfg"], make_flags=['CPPFLAGS_ADD=-UVL_DEBUG']) if test.vlt_all: test.execute(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_timescale_lint_bad.out0000644000542200017500000000105415101701376023744 0ustar mahmoudyfreeshell%Warning-TIMESCALEMOD: t/t_timescale_lint.v:7:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) 7 | module pre_no_ts; | ^~~~~~~~~ t/t_timescale_lint.v:12:8: ... Location of module with timescale 12 | module t; | ^ ... For warning description see https://verilator.org/warn/TIMESCALEMOD?v=latest ... Use "/* verilator lint_off TIMESCALEMOD */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_while_finish.v0000644000542200017500000000073415101701376022254 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; int loops; initial begin #1; // verilator lint_off INFINITELOOP while (1'b1) begin $write("*-* All Finished *-*\n"); $finish; // Infinite loop, but for this finish if (++loops > 100) $stop; end end endmodule verilator-5.042/test_regress/t/t_preproc_persist.v0000644000542200017500000000041415101701376023022 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 Inside `__FILE__. `include "t_preproc_persist_inc.v" verilator-5.042/test_regress/t/t_runflag_bad__e.out0000644000542200017500000000023015101701376023044 0ustar mahmoudyfreeshell%Error: COMMAND_LINE:0: Argument '+verilator+prof+exec+window+' must be an unsigned integer, greater than 0. Value out of range of uint64_t Aborting... verilator-5.042/test_regress/t/t_trace_event.py0000755000542200017500000000122215101701376022262 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=[ '--trace-vcd --binary', '--dumpi-V3Trace 9' # Dev coverage of the V3DumpFinder debug code ]) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_param_sel_range_bad.py0000755000542200017500000000104215101701376023710 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.top_filename = "t/t_param_sel_range.v" test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_force_rhs_ref.v0000644000542200017500000000142215101701376022405 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module t; reg [1:0] a; wire [1:0] b = 1; initial begin #1 a = 0; force b = a; `checkh(a, 0); `checkh(b, 0); a = 1; #1; `checkh(a, 1); `checkh(b, 1); a = 2; #1; `checkh(a, 2); `checkh(b, 2); a = 3; #1; `checkh(a, 3); `checkh(b, 3); release b; `checkh(a, 3); `checkh(b, 1); #1 $finish; end endmodule verilator-5.042/test_regress/t/t_mem_multidim_Ox.py0000755000542200017500000000104615101701376023117 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_mem_multidim.v" test.compile(verilator_flags2=['--fno-expand']) test.execute() test.passes() verilator-5.042/test_regress/t/t_array_pattern_scalar_bad.out0000644000542200017500000000061615101701376025153 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_array_pattern_scalar_bad.v:9:13: Unsupported: Assignment pattern applies against non struct/union data type: 'bit' : ... note: In instance 't' 9 | bit bad = '{1'b1}; | ^~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_vlcov_data_e.dat0000644000542200017500000004741715101701376022546 0ustar mahmoudyfreeshell# SystemC::Coverage-3 C 'ft/t_cover_line.vl100n10tlinepagev_line/toblockS100htop.t' 0 C 'ft/t_cover_line.vl101n10tlinepagev_line/toblockS101-102htop.t' 0 C 'ft/t_cover_line.vl104n10tlinepagev_line/toblockS104htop.t' 0 C 'ft/t_cover_line.vl105n10tlinepagev_line/toblockS105-107htop.t' 0 C 'ft/t_cover_line.vl110n10tlinepagev_line/toelsifS110-111htop.t' 1 C 'ft/t_cover_line.vl113n15tlinepagev_line/toelsifS113,115htop.t' 1 C 'ft/t_cover_line.vl12n10ttogglepagev_toggle/toclkhtop.t' 19 C 'ft/t_cover_line.vl120n15tbranchpagev_branch/toifS120-122htop.t' 1 C 'ft/t_cover_line.vl120n16tbranchpagev_branch/toelsehtop.t' 7 C 'ft/t_cover_line.vl127n9tlinepagev_line/toblockS127,129htop.t' 1 C 'ft/t_cover_line.vl138n10ttogglepagev_toggle/alphaoclkhtop.t.a*' 38 C 'ft/t_cover_line.vl139n10ttogglepagev_toggle/alphaotogglehtop.t.a*' 4 C 'ft/t_cover_line.vl14n10ttogglepagev_toggle/totogglehtop.t' 2 C 'ft/t_cover_line.vl140n4tlinepagev_line/alphaoblockS140htop.t.a*' 20 C 'ft/t_cover_line.vl141n7tbranchpagev_branch/alphaoifS141-142htop.t.a*' 2 C 'ft/t_cover_line.vl141n8tbranchpagev_branch/alphaoelsehtop.t.a*' 18 C 'ft/t_cover_line.vl145n8tlinepagev_line/alphaoelsehtop.t.a*' 18 C 'ft/t_cover_line.vl15n4tlinepagev_line/toblockS15htop.t' 1 C 'ft/t_cover_line.vl159n10ttogglepagev_toggle/betaoclkhtop.t.b*' 38 C 'ft/t_cover_line.vl160n10ttogglepagev_toggle/betaotogglehtop.t.b*' 4 C 'ft/t_cover_line.vl164n4tlinepagev_line/betaoblockS164-165htop.t.b*' 20 C 'ft/t_cover_line.vl166n7tbranchpagev_branch/betaoifS166,168htop.t.b*' 0 C 'ft/t_cover_line.vl166n8tbranchpagev_branch/betaoelsehtop.t.b*' 20 C 'ft/t_cover_line.vl170n7tbranchpagev_branch/betaoifS170,172htop.t.b*' 2 C 'ft/t_cover_line.vl170n8tbranchpagev_branch/betaoelsehtop.t.b*' 18 C 'ft/t_cover_line.vl174n8tlinepagev_line/betaoelsehtop.t.b*' 18 C 'ft/t_cover_line.vl18n4tlinepagev_line/toblockS18htop.t' 1 C 'ft/t_cover_line.vl188n13tlinepagev_line/ClsoblockS188-189htop.$unit::Cls__Vclpkg' 1 C 'ft/t_cover_line.vl190n7tbranchpagev_branch/ClsoifS190-191htop.$unit::Cls__Vclpkg' 1 C 'ft/t_cover_line.vl190n8tbranchpagev_branch/Clsoelsehtop.$unit::Cls__Vclpkg' 0 C 'ft/t_cover_line.vl194n25tlinepagev_line/ClsoblockS194htop.$unit::Cls__Vclpkg' 11 C 'ft/t_cover_line.vl195n7tbranchpagev_branch/ClsoifS195-196htop.$unit::Cls__Vclpkg' 11 C 'ft/t_cover_line.vl195n8tbranchpagev_branch/Clsoelsehtop.$unit::Cls__Vclpkg' 0 C 'ft/t_cover_line.vl199n18tlinepagev_line/ClsoblockS199htop.$unit::Cls__Vclpkg' 11 C 'ft/t_cover_line.vl20n15ttogglepagev_toggle/tocyc_copy[0]htop.t' 11 C 'ft/t_cover_line.vl20n15ttogglepagev_toggle/tocyc_copy[1]htop.t' 5 C 'ft/t_cover_line.vl20n15ttogglepagev_toggle/tocyc_copy[2]htop.t' 2 C 'ft/t_cover_line.vl20n15ttogglepagev_toggle/tocyc_copy[3]htop.t' 1 C 'ft/t_cover_line.vl20n15ttogglepagev_toggle/tocyc_copy[4]htop.t' 0 C 'ft/t_cover_line.vl20n15ttogglepagev_toggle/tocyc_copy[5]htop.t' 0 C 'ft/t_cover_line.vl20n15ttogglepagev_toggle/tocyc_copy[6]htop.t' 0 C 'ft/t_cover_line.vl20n15ttogglepagev_toggle/tocyc_copy[7]htop.t' 0 C 'ft/t_cover_line.vl200n7tbranchpagev_branch/ClsoifS200-201htop.$unit::Cls__Vclpkg' 11 C 'ft/t_cover_line.vl200n8tbranchpagev_branch/Clsoelsehtop.$unit::Cls__Vclpkg' 0 C 'ft/t_cover_line.vl210n10ttogglepagev_toggle/tskoclkhtop.t.t1' 19 C 'ft/t_cover_line.vl211n10ttogglepagev_toggle/tskotogglehtop.t.t1' 2 C 'ft/t_cover_line.vl215n4tlinepagev_line/tskoblockS215-216htop.t.t1' 10 C 'ft/t_cover_line.vl219n9tlinepagev_line/tskoblockS219,221,229,231-232htop.t.t1' 11 C 'ft/t_cover_line.vl222n10tbranchpagev_branch/tskoifS222-223htop.t.t1' 1 C 'ft/t_cover_line.vl222n11tbranchpagev_branch/tskoelsehtop.t.t1' 10 C 'ft/t_cover_line.vl225n10tbranchpagev_branch/tskoifS225-226htop.t.t1' 1 C 'ft/t_cover_line.vl225n11tbranchpagev_branch/tskoelsehtop.t.t1' 10 C 'ft/t_cover_line.vl230n18tlinepagev_line/tskoblockS230htop.t.t1' 1 C 'ft/t_cover_line.vl241n10ttogglepagev_toggle/offoclkhtop.t.o1' 19 C 'ft/t_cover_line.vl242n10ttogglepagev_toggle/offotogglehtop.t.o1' 2 C 'ft/t_cover_line.vl252n4tlinepagev_line/offoblockS252htop.t.o1' 10 C 'ft/t_cover_line.vl253n7tbranchpagev_branch/offoifS253,255htop.t.o1' 1 C 'ft/t_cover_line.vl253n8tbranchpagev_branch/offoelsehtop.t.o1' 9 C 'ft/t_cover_line.vl256n10tbranchpagev_branch/offoifS256htop.t.o1' 0 C 'ft/t_cover_line.vl256n11tbranchpagev_branch/offoelsehtop.t.o1' 1 C 'ft/t_cover_line.vl261n19ttogglepagev_toggle/taboclkhtop.t.tab1' 19 C 'ft/t_cover_line.vl262n14ttogglepagev_toggle/tabocyc4[0]htop.t.tab1' 10 C 'ft/t_cover_line.vl262n14ttogglepagev_toggle/tabocyc4[1]htop.t.tab1' 5 C 'ft/t_cover_line.vl262n14ttogglepagev_toggle/tabocyc4[2]htop.t.tab1' 2 C 'ft/t_cover_line.vl262n14ttogglepagev_toggle/tabocyc4[3]htop.t.tab1' 1 C 'ft/t_cover_line.vl265n4tlinepagev_line/taboblockS265-266htop.t.tab1' 10 C 'ft/t_cover_line.vl267n10tlinepagev_line/tabocaseS267htop.t.tab1' 1 C 'ft/t_cover_line.vl268n10tlinepagev_line/tabocaseS268htop.t.tab1' 1 C 'ft/t_cover_line.vl269n10tlinepagev_line/tabocaseS269htop.t.tab1' 1 C 'ft/t_cover_line.vl270n10tlinepagev_line/tabocaseS270htop.t.tab1' 1 C 'ft/t_cover_line.vl271n10tlinepagev_line/tabocaseS271htop.t.tab1' 1 C 'ft/t_cover_line.vl272n9tlinepagev_line/tabocaseS272htop.t.tab1' 5 C 'ft/t_cover_line.vl276n4tlinepagev_line/taboblockS276-277htop.t.tab1' 10 C 'ft/t_cover_line.vl287n27tlinepagev_line/paroblockS287,294htop.t.par1' 0 C 'ft/t_cover_line.vl288n7tbranchpagev_branch/paroifS288-289htop.t.par1' 0 C 'ft/t_cover_line.vl288n8tbranchpagev_branch/paroelseS291-292htop.t.par1' 0 C 'ft/t_cover_line.vl300n14tlinepagev_line/my_pkgoblockS300htop.my_pkg' 1 C 'ft/t_cover_line.vl303n1tlinepagev_line/Getter1oblockS303htop.$unit::Getter1__Vclpkg' 1 C 'ft/t_cover_line.vl304n17tlinepagev_line/Getter1oblockS304-305htop.$unit::Getter1__Vclpkg' 20 C 'ft/t_cover_line.vl309n25ttogglepagev_toggle/condoclkhtop.t.cond1' 19 C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[0]htop.t.cond1' 11 C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[10]htop.t.cond1' 0 C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[11]htop.t.cond1' 0 C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[12]htop.t.cond1' 0 C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[13]htop.t.cond1' 0 C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[14]htop.t.cond1' 0 C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[15]htop.t.cond1' 0 C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[16]htop.t.cond1' 0 C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[17]htop.t.cond1' 0 C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[18]htop.t.cond1' 0 C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[19]htop.t.cond1' 0 C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[1]htop.t.cond1' 5 C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[20]htop.t.cond1' 0 C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[21]htop.t.cond1' 0 C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[22]htop.t.cond1' 0 C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[23]htop.t.cond1' 0 C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[24]htop.t.cond1' 0 C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[25]htop.t.cond1' 0 C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[26]htop.t.cond1' 0 C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[27]htop.t.cond1' 0 C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[28]htop.t.cond1' 0 C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[29]htop.t.cond1' 0 C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[2]htop.t.cond1' 2 C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[30]htop.t.cond1' 0 C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[31]htop.t.cond1' 0 C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[3]htop.t.cond1' 1 C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[4]htop.t.cond1' 0 C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[5]htop.t.cond1' 0 C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[6]htop.t.cond1' 0 C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[7]htop.t.cond1' 0 C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[8]htop.t.cond1' 0 C 'ft/t_cover_line.vl309n40ttogglepagev_toggle/condocyc[9]htop.t.cond1' 0 C 'ft/t_cover_line.vl310n10ttogglepagev_toggle/condoahtop.t.cond1' 0 C 'ft/t_cover_line.vl310n13ttogglepagev_toggle/condobhtop.t.cond1' 2 C 'ft/t_cover_line.vl310n16ttogglepagev_toggle/condochtop.t.cond1' 19 C 'ft/t_cover_line.vl310n19ttogglepagev_toggle/condodhtop.t.cond1' 6 C 'ft/t_cover_line.vl310n22ttogglepagev_toggle/condoehtop.t.cond1' 7 C 'ft/t_cover_line.vl310n25ttogglepagev_toggle/condofhtop.t.cond1' 1 C 'ft/t_cover_line.vl310n28ttogglepagev_toggle/condoghtop.t.cond1' 19 C 'ft/t_cover_line.vl310n31ttogglepagev_toggle/condohhtop.t.cond1' 3 C 'ft/t_cover_line.vl310n34ttogglepagev_toggle/condokhtop.t.cond1' 0 C 'ft/t_cover_line.vl310n37ttogglepagev_toggle/condolhtop.t.cond1' 0 C 'ft/t_cover_line.vl310n40ttogglepagev_toggle/condomhtop.t.cond1' 0 C 'ft/t_cover_line.vl311n16ttogglepagev_toggle/condotab[0]htop.t.cond1' 1 C 'ft/t_cover_line.vl311n16ttogglepagev_toggle/condotab[1]htop.t.cond1' 1 C 'ft/t_cover_line.vl311n16ttogglepagev_toggle/condotab[2]htop.t.cond1' 0 C 'ft/t_cover_line.vl311n16ttogglepagev_toggle/condotab[3]htop.t.cond1' 0 C 'ft/t_cover_line.vl311n16ttogglepagev_toggle/condotab[4]htop.t.cond1' 0 C 'ft/t_cover_line.vl311n16ttogglepagev_toggle/condotab[5]htop.t.cond1' 0 C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[0][0][0]htop.t.cond1' 0 C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[0][0][1]htop.t.cond1' 2 C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[0][0][2]htop.t.cond1' 0 C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[0][0][3]htop.t.cond1' 0 C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[0][0][4]htop.t.cond1' 0 C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[0][0][5]htop.t.cond1' 0 C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[0][0][6]htop.t.cond1' 0 C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[0][0][7]htop.t.cond1' 0 C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[0][1][0]htop.t.cond1' 2 C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[0][1][1]htop.t.cond1' 0 C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[0][1][2]htop.t.cond1' 0 C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[0][1][3]htop.t.cond1' 0 C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[0][1][4]htop.t.cond1' 0 C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[0][1][5]htop.t.cond1' 0 C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[0][1][6]htop.t.cond1' 0 C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[0][1][7]htop.t.cond1' 0 C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[1][0][0]htop.t.cond1' 0 C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[1][0][1]htop.t.cond1' 0 C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[1][0][2]htop.t.cond1' 0 C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[1][0][3]htop.t.cond1' 0 C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[1][0][4]htop.t.cond1' 0 C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[1][0][5]htop.t.cond1' 0 C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[1][0][6]htop.t.cond1' 0 C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[1][0][7]htop.t.cond1' 0 C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[1][1][0]htop.t.cond1' 0 C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[1][1][1]htop.t.cond1' 0 C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[1][1][2]htop.t.cond1' 0 C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[1][1][3]htop.t.cond1' 0 C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[1][1][4]htop.t.cond1' 0 C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[1][1][5]htop.t.cond1' 0 C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[1][1][6]htop.t.cond1' 0 C 'ft/t_cover_line.vl313n10ttogglepagev_toggle/condodata[1][1][7]htop.t.cond1' 0 C 'ft/t_cover_line.vl314n22tlinepagev_line/condoblockS314htop.t.cond1' 1 C 'ft/t_cover_line.vl317n19tlinepagev_line/condoblockS317-319htop.t.cond1' 21 C 'ft/t_cover_line.vl322n19tlinepagev_line/condoblockS322,324htop.t.cond1' 10 C 'ft/t_cover_line.vl327n26tbranchpagev_branch/condocond_thenS327htop.t.cond1' 0 C 'ft/t_cover_line.vl327n27tbranchpagev_branch/condocond_elseS327htop.t.cond1' 31 C 'ft/t_cover_line.vl328n26tbranchpagev_branch/condocond_thenS328htop.t.cond1' 3 C 'ft/t_cover_line.vl328n27tbranchpagev_branch/condocond_elseS328htop.t.cond1' 28 C 'ft/t_cover_line.vl329n34tbranchpagev_branch/condocond_thenS329htop.t.cond1' 21 C 'ft/t_cover_line.vl329n35tbranchpagev_branch/condocond_elseS329htop.t.cond1' 0 C 'ft/t_cover_line.vl330n4tlinepagev_line/condoblockS330-332htop.t.cond1' 10 C 'ft/t_cover_line.vl331n20texprpagev_expr/condo(((cyc %25 32'sh3) == 32'sh0)==0) => 0htop.t.cond1' 7 C 'ft/t_cover_line.vl331n20texprpagev_expr/condo(((cyc %25 32'sh3) == 32'sh0)==1) => 1htop.t.cond1' 3 C 'ft/t_cover_line.vl331n26tbranchpagev_branch/condocond_thenS331htop.t.cond1' 3 C 'ft/t_cover_line.vl331n27tbranchpagev_branch/condocond_elseS331htop.t.cond1' 7 C 'ft/t_cover_line.vl332n34tbranchpagev_branch/condocond_thenS332htop.t.cond1' 0 C 'ft/t_cover_line.vl332n35tbranchpagev_branch/condocond_elseS332htop.t.cond1' 10 C 'ft/t_cover_line.vl334n30tbranchpagev_branch/condocond_thenS334htop.t.cond1' 12 C 'ft/t_cover_line.vl334n31tbranchpagev_branch/condocond_elseS334htop.t.cond1' 19 C 'ft/t_cover_line.vl334n37tbranchpagev_branch/condocond_thenS334htop.t.cond1' 7 C 'ft/t_cover_line.vl334n38tbranchpagev_branch/condocond_elseS334htop.t.cond1' 5 C 'ft/t_cover_line.vl337n34tbranchpagev_branch/condocond_thenS337htop.t.cond1' 11 C 'ft/t_cover_line.vl337n35tbranchpagev_branch/condocond_elseS337htop.t.cond1' 0 C 'ft/t_cover_line.vl343n22tbranchpagev_branch/condocond_thenS343htop.t.cond1' 10 C 'ft/t_cover_line.vl343n23tbranchpagev_branch/condocond_elseS343htop.t.cond1' 11 C 'ft/t_cover_line.vl346n4tlinepagev_line/condoblockS346,350,353,356htop.t.cond1' 11 C 'ft/t_cover_line.vl347n29texprpagev_expr/condo((cyc > 32'sh5)==0) => 0htop.t.cond1' 1 C 'ft/t_cover_line.vl347n29texprpagev_expr/condo((cyc > 32'sh5)==1) => 1htop.t.cond1' 0 C 'ft/t_cover_line.vl347n33tbranchpagev_branch/condocond_thenS347htop.t.cond1' 0 C 'ft/t_cover_line.vl347n34tbranchpagev_branch/condocond_elseS347htop.t.cond1' 1 C 'ft/t_cover_line.vl347n7tbranchpagev_branch/condoifS347htop.t.cond1' 1 C 'ft/t_cover_line.vl347n8tbranchpagev_branch/condoelseS348htop.t.cond1' 10 C 'ft/t_cover_line.vl350n22texprpagev_expr/condo((cyc == 32'sh2)==0) => 0htop.t.cond1' 10 C 'ft/t_cover_line.vl350n22texprpagev_expr/condo((cyc == 32'sh2)==1) => 1htop.t.cond1' 1 C 'ft/t_cover_line.vl350n28tbranchpagev_branch/condocond_thenS350htop.t.cond1' 1 C 'ft/t_cover_line.vl350n29tbranchpagev_branch/condocond_elseS350htop.t.cond1' 10 C 'ft/t_cover_line.vl353n26texprpagev_expr/condo((i < 32'sh5)==0) => 0htop.t.cond1' 11 C 'ft/t_cover_line.vl353n26texprpagev_expr/condo((i < 32'sh5)==1) => 1htop.t.cond1' 0 C 'ft/t_cover_line.vl353n7tlinepagev_line/condoblockS353-354htop.t.cond1' 55 C 'ft/t_cover_line.vl356n37texprpagev_expr/condo((i > 32'sh4)==0) => 0htop.t.cond1' 0 C 'ft/t_cover_line.vl356n37texprpagev_expr/condo((i > 32'sh4)==1) => 1htop.t.cond1' 11 C 'ft/t_cover_line.vl356n7tlinepagev_line/condoblockS356-357htop.t.cond1' 44 C 'ft/t_cover_line.vl360n11texprpagev_expr/condo(k==0) => 0htop.t.cond1' 11 C 'ft/t_cover_line.vl360n11texprpagev_expr/condo(k==1) => 1htop.t.cond1' 0 C 'ft/t_cover_line.vl360n7tbranchpagev_branch/condoifS360htop.t.cond1' 0 C 'ft/t_cover_line.vl360n8tbranchpagev_branch/condoelseS361htop.t.cond1' 11 C 'ft/t_cover_line.vl55n4tlinepagev_line/toblockS55htop.t' 10 C 'ft/t_cover_line.vl56n7tbranchpagev_branch/toifS56-58,105-106htop.t' 10 C 'ft/t_cover_line.vl56n8tbranchpagev_branch/toelsehtop.t' 0 C 'ft/t_cover_line.vl60n10tbranchpagev_branch/toifS60htop.t' 1 C 'ft/t_cover_line.vl60n11tbranchpagev_branch/toelsehtop.t' 9 C 'ft/t_cover_line.vl61n10tbranchpagev_branch/toifS61-63htop.t' 1 C 'ft/t_cover_line.vl61n11tbranchpagev_branch/toelsehtop.t' 9 C 'ft/t_cover_line.vl66n10tbranchpagev_branch/toifS66htop.t' 1 C 'ft/t_cover_line.vl66n11tbranchpagev_branch/toelseS66htop.t' 9 C 'ft/t_cover_line.vl67n10tbranchpagev_branch/toifS67htop.t' 1 C 'ft/t_cover_line.vl67n11tbranchpagev_branch/toelseS69-70htop.t' 9 C 'ft/t_cover_line.vl73n10tbranchpagev_branch/toifS73htop.t' 1 C 'ft/t_cover_line.vl73n11tbranchpagev_branch/toelseS73htop.t' 9 C 'ft/t_cover_line.vl74n10tbranchpagev_branch/toifS74-76htop.t' 1 C 'ft/t_cover_line.vl74n11tbranchpagev_branch/toelseS79-80htop.t' 9 C 'ft/t_cover_line.vl83n10tlinepagev_line/toelsifS83-85htop.t' 1 C 'ft/t_cover_line.vl87n15tlinepagev_line/toelsifS87-89htop.t' 1 C 'ft/t_cover_line.vl91n15tlinepagev_line/toifS91-93htop.t' 1 C 'ft/t_cover_line.vl91n16tlinepagev_line/toelseS96-97htop.t' 7 verilator-5.042/test_regress/t/t_initarray_nonarray.py0000755000542200017500000000071415101701376023703 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.passes() verilator-5.042/test_regress/t/t_func_virt_new.v0000644000542200017500000000060415101701376022450 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class cl #(type T= int); function void f(); T obj = new; endfunction endclass virtual class vcl; endclass; module t; cl #(vcl) c = new; initial begin end endmodule verilator-5.042/test_regress/t/t_timing_events.v0000644000542200017500000000167115101701376022460 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; event e1; event e2; event e3; initial forever begin #2 ->e1; #2 ->e2; #2 ->e3; end initial begin for (int i = 0; i < 10; i++) begin @(e1, e2, e3) if (!e1.triggered && !e2.triggered && !e3.triggered) $stop; `ifdef TEST_VERBOSE $write("got event %0d\n", i); `endif end $write("*-* All Finished *-*\n"); $finish; end int x; initial begin x = # 1_1 'd 12_34; // Checks we parse _ correctly if (x != 1234) $stop; if ($time != 11) $stop; end initial #21 $stop; // timeout endmodule `ifndef VERILATOR_TIMING `error "VERILATOR_TIMING should have been defined as have --timing" `endif verilator-5.042/test_regress/t/t_class_super_new.py0000755000542200017500000000073415101701376023166 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_member_var_virt_bad.py0000755000542200017500000000076615101701376025155 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_flag_woff.py0000755000542200017500000000075615101701376021730 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--lint-only -Wno-WIDTH"]) test.passes() verilator-5.042/test_regress/t/t_altera_lpm_ram_io.py0000755000542200017500000000111115101701376023426 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) test.compile(verilator_flags2=["--top-module", module]) test.passes() verilator-5.042/test_regress/t/t_package_verb.py0000755000542200017500000000073415101701376022403 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_assert_unique_case.py0000755000542200017500000000120515101701376023646 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_assert_unique_case_bad.v" test.compile(verilator_flags2=["-x-assign 0 --assert-case --no-stop-fail +define+NO_STOP_FAIL"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_strength_assignments_constants.py0000755000542200017500000000100515101701376026327 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--language 1364-2005"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_assert_implication_bad.py0000755000542200017500000000130315101701376024462 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_assert_implication.v" test.compile(v_flags2=['+define+FAIL_ASSERT_1'], verilator_flags2=['--assert --cc']) test.execute() # We expect to get a message when this assert fires: test.file_grep(test.run_log_filename, r'wrong implication') test.passes() verilator-5.042/test_regress/t/t_vlcov_data_c.dat0000644000542200017500000000007715101701376022533 0ustar mahmoudyfreeshell# SystemC::Coverage-3 C 'CoverPoint6ffile1.sphl159' 10 verilator-5.042/test_regress/t/t_func_dotted_inl0_vlt.py0000755000542200017500000000234615101701376024100 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_func_dotted.v" out_filename = test.obj_dir + "/V" + test.name + ".tree.json" test.compile(v_flags2=["--no-json-edit-nums", test.t_dir + "/t_func_dotted_inl0.vlt"]) if test.vlt_all: test.file_grep( out_filename, r'{"type":"MODULE","name":"ma",.*"loc":"\w,84:[^"]*",.*"origName":"ma",.*"modPublic":true') test.file_grep( out_filename, r'{"type":"MODULE","name":"mb",.*"loc":"\w,99:[^"]*",.*"origName":"mb",.*"modPublic":true') test.file_grep( out_filename, r'{"type":"MODULE","name":"mc",.*"loc":"\w,127:[^"]*",.*"origName":"mc",.*"modPublic":true' ) test.file_grep( out_filename, r'{"type":"MODULE","name":"mc__PB1",.*"loc":"\w,127:[^"]*",.*"origName":"mc",.*"modPublic":true' ) test.execute() test.passes() verilator-5.042/test_regress/t/t_scheduling_5.v0000644000542200017500000000176515101701376022162 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg start = 0; reg [31:0] count; reg [31:0] runner = 0; always @ (posedge start) count = 0; always @ (posedge start) runner = 3; always @ (runner) begin if (runner > 0) begin $display("count=%d runner=%d",count, runner); count = count + 1; runner = runner - 1;; end end reg [7:0] cyc = 0; always @ (posedge clk) begin cyc <= cyc + 8'd1; case (cyc) 8'd00: start <= 1'b0; 8'd01: start <= 1'b1; 8'd02: begin $display("Final count=%d", count); if (count!=32'h3) $stop; end default: begin $write("*-* All Finished *-*\n"); $finish; end endcase end endmodule verilator-5.042/test_regress/t/t_func_mlog2.v0000644000542200017500000000266615101701376021645 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003-2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; integer cyc; initial cyc=1; integer sum; integer cpre; always @ (posedge clk) begin if (cyc!=0) begin cpre = cyc; cyc <= cyc + 1; if (cyc==1) begin if (mlog2(32'd0) != 32'd0) $stop; if (mlog2(32'd1) != 32'd0) $stop; if (mlog2(32'd3) != 32'd2) $stop; sum <= 32'd0; end else if (cyc<90) begin // (cyc) so if we trash the variable things will get upset. sum <= mlog2(cyc) + sum * 32'd42; if (cpre != cyc) $stop; end else if (cyc==90) begin if (sum !== 32'h0f12bb51) $stop; $write("*-* All Finished *-*\n"); $finish; end end end function integer mlog2; input [31:0] value; integer i; begin if(value < 32'd1) begin mlog2 = 0; end else begin value = value - 32'd1; mlog2 = 0; for(i=0;i<32;i=i+1) begin if(value > 32'd0) begin mlog2 = mlog2 + 1; end value = value >> 1; end end end endfunction endmodule verilator-5.042/test_regress/t/t_opt_merge_cond_blowup.v0000644000542200017500000000275515101701376024165 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; localparam int N = 4096; integer cyc = 0; reg [63:0] crc= 64'h5aef0c8d_d70a4497; always @ (posedge clk) begin cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end reg a [N-1:0]; reg b [N-1:0]; // This yields pathological complexity for the current conditional merging // algorithm. Note in practice, other parts of the compiler blow up on this // code far earlier than the conditional merging, but here we go anyway. generate genvar i; for (i = 0 ; i < N ; i = i + 1) begin always @(posedge clk) a[i] <= (crc + 64'(i)) == 0 ? crc[(i+16)%64] : crc[(i+32)%64]; end for (i = 0 ; i < N ; i = i + 1) begin always @(posedge clk) b[i] <= (crc + 64'(i)) == 0 ? crc[(i+16)%64] : crc[(i+32)%64]; end endgenerate always @(posedge clk) begin if (cyc >= 2) begin for (int i = 0 ; i < N ; i = i + 1) begin if (a[i] !== b[i]) begin $write("%%Error: %s:%0d: cyc=%0d i=%0d a[i]='h%x b[i]='h%x\n", `__FILE__,`__LINE__, cyc, i, a[i], b[i]); $stop; end end end end endmodule verilator-5.042/test_regress/t/t_json_only_first.py0000755000542200017500000000135415101701376023212 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') out_filename = test.obj_dir + "/V" + test.name + ".tree.json" test.compile(verilator_flags2=['--no-std', '--json-only', '--no-json-edit-nums'], verilator_make_gmake=False, make_top_shell=False, make_main=False) test.files_identical(out_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_inst_v2k__sub.vi0000644000542200017500000000110115101701376022511 0ustar mahmoudyfreeshell// -*- Verilog -*- // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // This file is named .vi to test +libext+ flags. module t_inst_v2k__sub ( output reg [7:0] osizedreg, output wire oonewire /*verilator public*/, input [7:0] isizedwire, input wire ionewire, output reg [1:0] tied = 2'b10 ); assign oonewire = ionewire; always @* begin osizedreg = isizedwire; end endmodule verilator-5.042/test_regress/t/t_mem_slice_bad.v0000644000542200017500000000320015101701376022336 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; logic use_AnB; logic [1:0] active_command [8:0]; logic [1:0] command_A [8:0]; logic [1:0] command_B [8:0]; logic [1:0] active_command2 [8:0]; logic [1:0] command_A2 [7:0]; logic [1:0] command_B2 [8:0]; logic [1:0] active_command3 [1:0][2:0][3:0]; logic [1:0] command_A3 [1:0][2:0][3:0]; logic [1:0] command_B3 [1:0][2:0][3:0]; logic [1:0] active_command4 [8:0]; logic [1:0] command_A4 [7:0]; logic [1:0] active_command5 [8:0]; logic [1:0] command_A5 [7:0]; // Single dimension assign assign active_command[3:0] = (use_AnB) ? command_A[7:0] : command_B[7:0]; // Assignment of entire arrays assign active_command2 = (use_AnB) ? command_A2 : command_B2; // Multi-dimension assign assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; // Supported: Delayed assigment with RHS Var == LHS Var logic [7:0] arrd [7:0]; always_ff @(posedge clk) arrd[7:4] <= arrd[3:0]; // Unsupported: Non-delayed assigment with RHS Var == LHS Var logic [7:0] arr [7:0]; assign arr[7:4] = arr[3:0]; // Delayed assign always @(posedge clk) begin active_command4[7:0] <= command_A4[8:0]; end // Combinational assign always_comb begin active_command5[8:0] = command_A5[7:0]; end endmodule : t verilator-5.042/test_regress/t/t_stream_type.v0000644000542200017500000000174515101701376022143 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); // verilog_format: on module t; initial begin bit b; automatic reg [2:0] foo0 [1:0] = '{0, 0}; automatic reg [2:0] foo2 [1:0] = '{0, 2}; automatic reg [2:0] foo4 [1:0] = '{1, 0}; b = |type(logic [$bits(foo0)-1:0])'({>>{foo0}}); $display("foo0 %p -> %b", foo0, b); `checkh(b, 1'b0); b = |type(logic [$bits(foo2)-1:0])'({>>{foo2}}); $display("foo0 %p -> %b", foo2, b); `checkh(b, 1'b1); b = |type(logic [$bits(foo4)-1:0])'({>>{foo4}}); $display("foo0 %p -> %b", foo4, b); `checkh(b, 1'b1); $finish; end endmodule verilator-5.042/test_regress/t/t_preproc_ifdefend_bad.v0000644000542200017500000000034115101701376023702 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `ifdef FOO verilator-5.042/test_regress/t/t_table_fsm.py0000755000542200017500000000073415101701376021726 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_exit.v0000644000542200017500000000052315101701376020551 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 program t; initial begin $write("*-* All Finished *-*\n"); $exit; // Must be in program block end endprogram verilator-5.042/test_regress/t/t_c_this.py0000755000542200017500000000251515101701376021242 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() if test.vlt_all: # The word 'this' (but only the whole word 'this' should have been replaced # in the contents. has_this = False has_xthis = False has_thisx = False has_xthisx = False for filename in test.glob_some(test.obj_dir + "/" + test.vm_prefix + "___024root__0.cpp"): text = test.file_contents(filename) if re.search(r'\bthis->clk\b', text): has_this = True if re.search(r'\bxthis\b', text): has_xthis = True if re.search(r'\bthisx\b', text): has_thisx = True if re.search(r'\bxthisx\b', text): has_xthisx = True if has_this: test.error("Some file has 'this->clk'") if not has_xthis: test.error("No file has 'xthis'") if not has_thisx: test.error("No file has 'thisx'") if not has_xthisx: test.error("No file has 'xthisx'") test.passes() verilator-5.042/test_regress/t/t_interface_param_another_bad.out0000644000542200017500000000215415101701376025612 0ustar mahmoudyfreeshell%Error-HIERPARAM: t/t_interface_param_another_bad.v:9:35: Parameter values cannot use hierarchical values (IEEE 1800-2023 6.20.2) : ... note: In instance 't' 9 | simple_bus #(.PARAMETER(sb_intf.dummy)) simple (); | ^~~~~ ... For error description see https://verilator.org/warn/HIERPARAM?v=latest %Error: t/t_interface_param_another_bad.v:9:35: Expecting expression to be constant, but variable isn't const: 'dummy' : ... note: In instance 't' 9 | simple_bus #(.PARAMETER(sb_intf.dummy)) simple (); | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_interface_param_another_bad.v:9:17: Can't convert defparam value to constant: Param 'PARAMETER' of 'simple' : ... note: In instance 't' 9 | simple_bus #(.PARAMETER(sb_intf.dummy)) simple (); | ^~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_inst_recurse_bad.v0000644000542200017500000000054215101701376023114 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; looped looped (); endmodule module looped; looped2 looped2 (); endmodule module looped2; looped looped (); endmodule verilator-5.042/test_regress/t/t_const_dec_mixed_bad.v0000644000542200017500000000042715101701376023540 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; parameter [200:0] MIXED = 32'dx_1; endmodule verilator-5.042/test_regress/t/t_runflag_seed.v0000644000542200017500000000115415101701376022237 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t; initial begin integer r = $random; integer ex; if ($value$plusargs("SEED=%x", ex) !== 1) $stop; `checkh(r, ex); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_lint_eofnewline_vlt.py0000755000542200017500000000160315101701376024034 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = test.obj_dir + "/t_lint_eofnewline_bad.v" def gen(filename): with open(filename, 'w', encoding="utf8") as fh: fh.write("// Generated by t_lint_eofnewline_bad.py\n") fh.write("module t;\n") fh.write("// No newline below:\n") fh.write("endmodule") # Intentionally no newline gen(test.top_filename) test.lint(verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME t/t_lint_eofnewline_vlt.vlt"]) test.passes() verilator-5.042/test_regress/t/t_dynarray_init.py0000755000542200017500000000073415101701376022646 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_param_real2.v0000644000542200017500000000157315101701376021773 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module foo #( parameter real BAR = 2.0) (); endmodule module t(); genvar m, r; generate for (m = 10; m <= 20; m+=10) begin : gen_m for (r = 0; r <= 1; r++) begin : gen_r localparam real LPARAM = m + (r + 0.5); initial begin if (LPARAM != foo_inst.BAR) begin $display("%m: LPARAM != foo_inst.BAR (%f, %f)", LPARAM, foo_inst.BAR); $stop(); end end foo #(.BAR (LPARAM)) foo_inst (); end end endgenerate initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_assoc_enum.py0000755000542200017500000000073415101701376022126 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_dist_docs_warnings.py0000755000542200017500000000647015101701376023660 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Primitive C++ style checker # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') Waivers = [ 'Internal', 'Unsupported', 'DIDNOTCONVERGE', # Runtime ] src_filename = "src/V3Error.h" doc_filename = "docs/guide/warnings.rst" def get_src_warns(): args = {} for filename in test.glob_some(test.root + "/" + src_filename): with open(filename, "r", encoding="latin-1") as fh: state = 0 lineno = 0 for line in fh: lineno += 1 line = line.rstrip() line = re.sub(r'\s*//.*', '', line) # print("S: %s" % line) if state == 0 and re.search(r'class V3ErrorCode', line): state = 1 elif state == 1 and re.search(r'const names', line): state = 2 elif state == 2 and re.search(r' return ', line): state = 3 elif state == 2: for opt in re.findall(r'"([A-Z0-9]+)"', line): opt = opt_clean(opt) if test.verbose: print("S '" + opt + "' " + line) args[opt] = filename + ":" + str(lineno) return args def get_docs_warns(): args = {} for filename in test.glob_some(test.root + "/" + doc_filename): with open(filename, "r", encoding="latin-1") as fh: lineno = 0 last_opt = None for line in fh: lineno += 1 line = line.rstrip() m = re.search(r' option:: ([A-Za-z0-9]+)', line) if m: opt = opt_clean(m.group(1)) if test.verbose: print("D '" + opt + "' " + line) args[opt] = filename + ":" + str(lineno) last_opt = opt if last_opt and re.search(r'Historical', line): Waivers.append(last_opt) return args def opt_clean(opt): return opt if not os.path.exists(test.root + "/.git"): test.skip("Not in a git repository") srcs = get_src_warns() docs = get_docs_warns() if len(srcs) < 10: test.error(src_filename + ": Too few warnings found; parse error?") if len(docs) < 10: test.error(doc_filename + ": Too few warnings found; parse error?") both = {} both.update(srcs) both.update(docs) waiver = {k: 1 for k in Waivers} for opt in sorted(both.keys()): if opt in waiver: continue src_ok = opt in srcs docs_ok = opt in docs if not src_ok: test.error_keep_going(docs[opt] + ": Warn code documented in " + doc_filename + " '" + opt + "' not found in " + src_filename + " sources") elif not docs_ok: test.error_keep_going(srcs[opt] + ": Warn code documented in " + src_filename + " '" + opt + "' not found in " + doc_filename + " documentation") elif test.verbose: print(": ok '" + opt) test.passes() verilator-5.042/test_regress/t/t_tri_select.py0000755000542200017500000000105615101701376022125 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_randomize_method_complex_bad.py0000755000542200017500000000077615101701376025665 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_pp_circ_subst_bad.out0000644000542200017500000000050215101701376023604 0ustar mahmoudyfreeshell%Error: t/t_pp_circ_subst_bad.v:8:80001: Too many preprocessor tokens on a line (>40000); perhaps recursive `define ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_pp_circ_subst_bad.v:8:5: syntax error, unexpected IDENTIFIER-for-type %Error: Exiting due to verilator-5.042/test_regress/t/t_interface_twod.v0000644000542200017500000000173615101701376022604 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface ifc; integer value; modport i (output value); modport o (input value); endinterface module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=1; ifc itop1a(), itop1b(); wrapper c1 (.isuba(itop1a), .isubb(itop1b), .i_valuea(14), .i_valueb(15)); always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==20) begin if (itop1a.value != 14) $stop; if (itop1b.value != 15) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module wrapper ( ifc.i isuba, isubb, input integer i_valuea, i_valueb ); always @* begin isuba.value = i_valuea; isubb.value = i_valueb; end endmodule verilator-5.042/test_regress/t/t_randcase_bad.py0000755000542200017500000000077215101701376022362 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_udp_bad_line_outputs.py0000755000542200017500000000102115101701376024170 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.leak_check_disable() test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_preproc_preproczero_bad.py0000755000542200017500000000141415101701376024700 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') stdout_filename = os.path.join(test.obj_dir, test.name + "__test.vpp") test.compile(verilator_flags2=['-E -P'], verilator_make_gmake=False, make_top_shell=False, make_main=False, stdout_filename=stdout_filename, fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_param_seg.v0000644000542200017500000000113315101701376021534 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2016 by Mandy Xu. // SPDX-License-Identifier: CC0-1.0 // verilator lint_off WIDTH //bug1088 module t (/*AUTOARG*/ // Outputs err_count, // Inputs clk, syndromes ); input clk; input [7:0] syndromes; output reg [1:0] err_count = 0; localparam [95:0] M = 96'h4; wire [3:0] syn1 = syndromes[0+:M]; always @(posedge clk) begin err_count <= {1'b0, |syn1}; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_class_member_var_virt_bad.out0000644000542200017500000000044215101701376025320 0ustar mahmoudyfreeshell%Error: t/t_class_member_var_virt_bad.v:8:16: Syntax error: 'virtual' not allowed before var declaration 8 | virtual int member; | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_mod_interface_array5.py0000755000542200017500000000073415101701376024054 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_param_mailbox.v0000644000542200017500000000077015101701376023604 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module sub #( parameter type T = logic ); mailbox #(T) mbox; endmodule module try #( parameter I = 1 ); endmodule module t; typedef struct packed { logic a; logic b; } my_struct_t; sub #(my_struct_t) u_sub (); try #(2) u_try2 (); initial $finish; endmodule verilator-5.042/test_regress/t/t_timing_fork_no_timing_ctrl.v0000644000542200017500000000055615101701376025205 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; initial fork begin $write("*-* All Finished *-*\n"); $finish; end join_none endmodule verilator-5.042/test_regress/t/t_pp_dupdef_bad.out0000644000542200017500000000125415101701376022720 0ustar mahmoudyfreeshell%Warning-REDEFMACRO: t/t_pp_dupdef.v:11:20: Redefining existing define: 'DUP', with different value: 'barney' t/t_pp_dupdef.v:11:20: ... Location of previous definition, with value: 'fred' ... For warning description see https://verilator.org/warn/REDEFMACRO?v=latest ... Use "/* verilator lint_off REDEFMACRO */" and lint_on around source to disable this message. %Warning-REDEFMACRO: t/t_pp_dupdef.v:14:33: Redefining existing define: 'DUPP', with different value: 'paramed(x,z) (x*z)' t/t_pp_dupdef.v:14:33: ... Location of previous definition, with value: 'paramed(x) (x)' %Error: Exiting due to verilator-5.042/test_regress/t/t_assert_future_unsup.out0000644000542200017500000000074315101701376024273 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_assert_future_unsup.v:21:54: Unsupported/illegal: Future value function used with expression with operator FUNCREF 'func' : ... note: In instance 't' 21 | assert property (@(posedge clk) $future_gclk(a) == func(a)); | ^~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_class_param_bad2.py0000755000542200017500000000076615101701376023154 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dfg_stats_patterns_post_inline.py0000755000542200017500000000131315101701376026265 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_dfg_stats_patterns.v" test.compile(verilator_flags2=["--stats --no-skip-identical -fno-dfg-pre-inline -fno-dfg-scoped"]) fn = test.glob_one(test.obj_dir + "/" + test.vm_prefix + "__stats_dfg_patterns*") test.files_identical(fn, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_trace_binary_flag_off.out0000644000542200017500000000014215101701376024424 0ustar mahmoudyfreeshell-Info: t/t_trace_binary.v:14: $dumpvar ignored, as Verilated without --trace *-* All Finished *-* verilator-5.042/test_regress/t/t_dpi_shortcircuit.py0000755000542200017500000000104515101701376023344 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(v_flags2=["t/t_dpi_shortcircuit_c.cpp"], verilator_flags2=["-Wno-DECLFILENAME"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_mem_packed_bad.v0000644000542200017500000000206115101701376022472 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc = 0; logic [1:0][27:0] ch01; logic [1:0][27:0] ch02; logic [1:0][27:0] ch03; logic [27:0] ch04[1:0]; /* verilator lint_off WIDTH */ always @ (posedge clk) begin // LHS is a 2D packed array, RHS is 1D packed or Const. Allowed now. ch01 <= {{2{28'd4}}}; ch02 <= {{2{cyc}}}; ch03 <= 56'd0; // LHS is 1D packed, 1D unpacked, this should never work. ch04 <= 56'd0; $display("ch01: %0x %0x", ch01[0], ch01[1]); $display("ch01: %0x %0x", ch02[0], ch02[1]); $display("ch01: %0x %0x", ch03[0], ch03[1]); $display("ch01: %0x %0x", ch04[0], ch04[1]); end /* verilator lint_on WIDTH */ endmodule verilator-5.042/test_regress/t/t_func_wide_out_c.cpp0000644000542200017500000000262715101701376023260 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "svdpi.h" #include #include //====================================================================== // clang-format off #if defined(VERILATOR) # ifdef T_FUNC_WIDE_OUT # include "Vt_func_wide_out__Dpi.h" # elif defined(T_FUNC_WIDE_OUT_NOINL) # include "Vt_func_wide_out_noinl__Dpi.h" # else # error "Unknown test" # endif #elif defined(VCS) # include "../vc_hdrs.h" #else # error "Unknown simulator for DPI test" #endif // clang-format on //====================================================================== void dpii_inv_s12(const svBitVecVal* in, svBitVecVal* out) { out[0] = ~in[0]; } void dpii_inv_u12(const svBitVecVal* in, svBitVecVal* out) { out[0] = ~in[0]; } void dpii_inv_s70(const svBitVecVal* in, svBitVecVal* out) { out[0] = ~in[0]; out[1] = ~in[1] & 0xf; } void dpii_inv_u70(const svBitVecVal* in, svBitVecVal* out) { out[0] = ~in[0]; out[1] = ~in[1] & 0xf; } verilator-5.042/test_regress/t/t_name_collision.v0000644000542200017500000000064415101701376022577 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module HasNameParam #(parameter name /*verilator public*/ = 0) (); endmodule module t (); HasNameParam a(); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_lint_lint_no.py0000755000542200017500000000104615101701376022457 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.top_filename = 't/t_lint_lint_bad.v' test.lint(verilator_flags2=["--lint-only -Wwarn-lint -Wno-lint"]) test.passes() verilator-5.042/test_regress/t/t_hier_block_trace_saif.out0000644000542200017500000715423715101701376024446 0ustar mahmoudyfreeshell// Generated by verilated_saif (SAIFILE (SAIFVERSION "2.0") (DIRECTION "backward") (PROGRAM_NAME "Verilator") (DIVIDER / ) (TIMESCALE 1ps) (DURATION 170) (INSTANCE top (NET (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) ) (INSTANCE t (NET (PARAM_A\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (PARAM_A\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_A\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_A\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_A\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_A\[5\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (PARAM_A\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_A\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_A\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_A\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_A\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_A\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_A\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_A\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_A\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_A\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_A\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_A\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_A\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_A\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_A\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_A\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_A\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_A\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_A\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_A\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_A\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_A\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_A\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_A\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_A\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_A\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_B\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_B\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_B\[2\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (PARAM_B\[3\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (PARAM_B\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_B\[5\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (PARAM_B\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_B\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_B\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_B\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_B\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_B\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_B\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_B\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_B\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_B\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_B\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_B\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_B\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_B\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_B\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_B\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_B\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_B\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_B\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_B\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_B\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_B\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_B\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_B\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_B\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (PARAM_B\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (out0\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 7)) (out0\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10)) (out0\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (out0\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (out0\[4\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (out0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out1\[0\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 7)) (out1\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 10)) (out1\[2\] (T0 70) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 6)) (out1\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3)) (out1\[4\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (out1\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out1\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out1\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out2\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (out2\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12)) (out2\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7)) (out2\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (out2\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1)) (out2\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out2\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out2\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out3\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (out3\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11)) (out3\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (out3\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3)) (out3\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1)) (out3\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out3\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out3\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out3_2\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (out3_2\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11)) (out3_2\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (out3_2\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3)) (out3_2\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1)) (out3_2\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out3_2\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out3_2\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out5\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 6)) (out5\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10)) (out5\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (out5\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3)) (out5\[4\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (out5\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out5\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out5\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out6\[0\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 5)) (out6\[1\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 8)) (out6\[2\] (T0 140) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 5)) (out6\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 2)) (out6\[4\] (T0 150) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (out6\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out6\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out6\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (count\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8)) (count\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4)) (count\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (count\[4\] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1)) (count\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE i_delay0 (NET (N\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (N\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[3\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (WIDTH\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (in\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (in\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11)) (in\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (in\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3)) (in\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1)) (in\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 6)) (out\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10)) (out\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (out\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3)) (out\[4\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (out\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (tmp\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 7)) (tmp\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10)) (tmp\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (tmp\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (tmp\[4\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (tmp\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (tmp\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (tmp\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE genblk1 (INSTANCE i_delay (NET (N\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (N\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[3\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (WIDTH\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (in\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 7)) (in\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10)) (in\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (in\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (in\[4\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (in\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 6)) (out\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10)) (out\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (out\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3)) (out\[4\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (out\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (tmp\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 6)) (tmp\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10)) (tmp\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (tmp\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3)) (tmp\[4\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (tmp\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (tmp\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (tmp\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) (INSTANCE i_delay1 (NET (N\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (N\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (N\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[3\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (WIDTH\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (in\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 6)) (in\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10)) (in\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (in\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3)) (in\[4\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (in\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[0\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 5)) (out\[1\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 8)) (out\[2\] (T0 140) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 5)) (out\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 2)) (out\[4\] (T0 150) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (out\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (tmp\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 6)) (tmp\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 9)) (tmp\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5)) (tmp\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 2)) (tmp\[4\] (T0 130) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) (tmp\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (tmp\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (tmp\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE genblk1 (INSTANCE i_delay (NET (N\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (N\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[3\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (WIDTH\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (in\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 6)) (in\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 9)) (in\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5)) (in\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 2)) (in\[4\] (T0 130) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) (in\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[0\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 5)) (out\[1\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 8)) (out\[2\] (T0 140) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 5)) (out\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 2)) (out\[4\] (T0 150) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (out\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (tmp\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 6)) (tmp\[1\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 9)) (tmp\[2\] (T0 130) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5)) (tmp\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 2)) (tmp\[4\] (T0 140) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1)) (tmp\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (tmp\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (tmp\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE genblk1 (INSTANCE i_delay (NET (N\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (N\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (N\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[3\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (WIDTH\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (WIDTH\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (in\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 6)) (in\[1\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 9)) (in\[2\] (T0 130) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5)) (in\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 2)) (in\[4\] (T0 140) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1)) (in\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[0\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 5)) (out\[1\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 8)) (out\[2\] (T0 140) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 5)) (out\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 2)) (out\[4\] (T0 150) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (out\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (tmp\[0\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 5)) (tmp\[1\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 8)) (tmp\[2\] (T0 140) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 5)) (tmp\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 2)) (tmp\[4\] (T0 150) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (tmp\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (tmp\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (tmp\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) ) ) (INSTANCE i_sub0 (NET (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (in\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (in\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11)) (in\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (in\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3)) (in\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1)) (in\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 7)) (out\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10)) (out\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (out\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (out\[4\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (out\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE i_sub0 (NET (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (in\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (in\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11)) (in\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (in\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3)) (in\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1)) (in\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 7)) (out\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10)) (out\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (out\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (out\[4\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (out\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) (INSTANCE i_sub1 (NET (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (in\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 7)) (in\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10)) (in\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (in\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (in\[4\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (in\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[0\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 7)) (out\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 10)) (out\[2\] (T0 70) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 6)) (out\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3)) (out\[4\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (out\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE i_sub2 (NET (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (in\[0\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 7)) (in\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 10)) (in\[2\] (T0 70) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 6)) (in\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3)) (in\[4\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (in\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (out\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12)) (out\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7)) (out\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (out\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1)) (out\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE i_sub3 (NET (P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNPACKED_ARRAY[1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNUSED\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNUSED\[2\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[3\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[4\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[5\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[6\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[7\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[8\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[9\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[10\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[11\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[12\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[13\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[14\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[15\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (ENUM\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ENUM\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (in\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (in\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12)) (in\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7)) (in\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (in\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1)) (in\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (out\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11)) (out\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (out\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3)) (out\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1)) (out\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[0\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 8)) (ff\[1\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 10)) (ff\[2\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 7)) (ff\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (ff\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1)) (ff\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out4\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (out4\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11)) (out4\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (out4\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3)) (out4\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1)) (out4\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out4\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out4\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out4_2\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (out4_2\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11)) (out4_2\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (out4_2\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3)) (out4_2\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1)) (out4_2\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out4_2\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out4_2\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE i_sub4_0 (NET (P0\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (in\[0\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 8)) (in\[1\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 10)) (in\[2\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 7)) (in\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (in\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1)) (in\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (out\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11)) (out\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (out\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3)) (out\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1)) (out\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (ff\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11)) (ff\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (ff\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3)) (ff\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1)) (ff\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[0][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[1][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (count\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8)) (count\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4)) (count\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (count\[4\] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1)) (count\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE i_sub5 (NET (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (in[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[0][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE unnamedblk1 (NET (i\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (i\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE unnamedblk2 (NET (j\[0\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (j\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (j\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE unnamedblk3 (NET (exp\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 15)) (exp\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) ) (INSTANCE i_sub4_1 (NET (P0\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (in\[0\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 8)) (in\[1\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 10)) (in\[2\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 7)) (in\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (in\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1)) (in\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (out\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11)) (out\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (out\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3)) (out\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1)) (out\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (ff\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11)) (ff\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (ff\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3)) (ff\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1)) (ff\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[0][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[1][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (count\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8)) (count\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4)) (count\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (count\[4\] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1)) (count\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE i_sub5 (NET (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (in[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[0][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE unnamedblk1 (NET (i\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (i\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE unnamedblk2 (NET (j\[0\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (j\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (j\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE unnamedblk3 (NET (exp\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 15)) (exp\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) ) ) (INSTANCE i_sub3_2 (NET (P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNPACKED_ARRAY[1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNUSED\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNUSED\[2\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[3\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[4\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[5\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[6\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[7\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[8\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[9\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[10\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[11\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[12\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[13\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[14\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[15\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (ENUM\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ENUM\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (in\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (in\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12)) (in\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7)) (in\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (in\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1)) (in\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (out\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11)) (out\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (out\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3)) (out\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1)) (out\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[0\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 8)) (ff\[1\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 10)) (ff\[2\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 7)) (ff\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (ff\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1)) (ff\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out4\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (out4\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11)) (out4\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (out4\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3)) (out4\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1)) (out4\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out4\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out4\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out4_2\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (out4_2\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11)) (out4_2\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (out4_2\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3)) (out4_2\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1)) (out4_2\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out4_2\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out4_2\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE i_sub4_0 (NET (P0\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (in\[0\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 8)) (in\[1\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 10)) (in\[2\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 7)) (in\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (in\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1)) (in\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (out\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11)) (out\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (out\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3)) (out\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1)) (out\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (ff\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11)) (ff\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (ff\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3)) (ff\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1)) (ff\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[0][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[1][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (count\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8)) (count\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4)) (count\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (count\[4\] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1)) (count\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE i_sub5 (NET (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (in[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[0][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE unnamedblk1 (NET (i\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (i\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE unnamedblk2 (NET (j\[0\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (j\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (j\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE unnamedblk3 (NET (exp\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 15)) (exp\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) ) (INSTANCE i_sub4_1 (NET (P0\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (in\[0\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 8)) (in\[1\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 10)) (in\[2\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 7)) (in\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (in\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1)) (in\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (out\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11)) (out\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (out\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3)) (out\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1)) (out\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (ff\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11)) (ff\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (ff\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3)) (ff\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1)) (ff\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[0][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[1][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (count\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8)) (count\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4)) (count\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (count\[4\] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1)) (count\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE i_sub5 (NET (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (in[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[0][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE unnamedblk1 (NET (i\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (i\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE unnamedblk2 (NET (j\[0\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (j\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (j\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE unnamedblk3 (NET (exp\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 15)) (exp\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) ) ) ) ) (INSTANCE top.t.i_sub0.i_sub0 (NET (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (in\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (in\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11)) (in\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (in\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3)) (in\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1)) (in\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 7)) (out\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10)) (out\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (out\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (out\[4\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (out\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE sub0 (NET (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (in\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (in\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11)) (in\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (in\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3)) (in\[4\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1)) (in\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 7)) (out\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10)) (out\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (out\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (out\[4\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (out\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 7)) (ff\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10)) (ff\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (ff\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (ff\[4\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (ff\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) (INSTANCE top.t.i_sub1 (NET (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (in\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 7)) (in\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10)) (in\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (in\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (in\[4\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (in\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[0\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 7)) (out\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 10)) (out\[2\] (T0 70) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 6)) (out\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3)) (out\[4\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (out\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE sub1 (NET (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (in\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 7)) (in\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10)) (in\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (in\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (in\[4\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (in\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[0\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 7)) (out\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 10)) (out\[2\] (T0 70) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 6)) (out\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3)) (out\[4\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (out\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[0\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 7)) (ff\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 10)) (ff\[2\] (T0 70) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 6)) (ff\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3)) (ff\[4\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (ff\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) (INSTANCE top.t.i_sub2 (NET (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (in\[0\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 7)) (in\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 10)) (in\[2\] (T0 70) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 6)) (in\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3)) (in\[4\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (in\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (out\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12)) (out\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7)) (out\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (out\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1)) (out\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE sub2 (NET (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (in\[0\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 7)) (in\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 10)) (in\[2\] (T0 70) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 6)) (in\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3)) (in\[4\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (in\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (out\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12)) (out\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7)) (out\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (out\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1)) (out\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (ff\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10)) (ff\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (ff\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (ff\[4\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (ff\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE in_ifs (NET (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (data\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (data\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10)) (data\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (data\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (data\[4\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (data\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE out_ifs (NET (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (data\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (data\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12)) (data\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7)) (data\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (data\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1)) (data\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE i_sub3 (NET (in_wire\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (in_wire\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10)) (in_wire\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (in_wire\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (in_wire\[4\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (in_wire\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in_wire\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in_wire\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out_1\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (out_1\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12)) (out_1\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7)) (out_1\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (out_1\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1)) (out_1\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out_1\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out_1\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out_2\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (out_2\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12)) (out_2\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7)) (out_2\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (out_2\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1)) (out_2\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out_2\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out_2\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE in (NET (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (data\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (data\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10)) (data\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (data\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (data\[4\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (data\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE out (NET (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (data\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (data\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12)) (data\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7)) (data\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (data\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1)) (data\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (data\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE i_sub3 (NET (P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNPACKED_ARRAY[1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNUSED\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNUSED\[2\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[3\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[4\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[5\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[6\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[7\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[8\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[9\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[10\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[11\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[12\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[13\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[14\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[15\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (ENUM\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (ENUM\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (in\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (in\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10)) (in\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (in\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (in\[4\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (in\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (out\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12)) (out\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7)) (out\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (out\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1)) (out\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[0\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 8)) (ff\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 12)) (ff\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 7)) (ff\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3)) (ff\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1)) (ff\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out4\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (out4\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12)) (out4\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7)) (out4\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (out4\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1)) (out4\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out4\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out4\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out4_2\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (out4_2\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12)) (out4_2\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7)) (out4_2\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (out4_2\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1)) (out4_2\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out4_2\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out4_2\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE i_sub4_0 (NET (P0\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (in\[0\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 8)) (in\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 12)) (in\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 7)) (in\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3)) (in\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1)) (in\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (out\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12)) (out\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7)) (out\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (out\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1)) (out\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (ff\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12)) (ff\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7)) (ff\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (ff\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1)) (ff\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[0][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[1][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (count\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8)) (count\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4)) (count\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (count\[4\] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1)) (count\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE i_sub5 (NET (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (in[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[0][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (count\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8)) (count\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4)) (count\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (count\[4\] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1)) (count\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val0[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val0[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val1[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val1[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val2[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val2[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val3[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val3[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val3[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE i_sub0 (NET (P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P1\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE i_sub1 (NET (P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P1\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE i_sub2 (NET (P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P1\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE i_sub3 (NET (P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P1\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE unnamedblk1 (NET (i\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (i\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE unnamedblk2 (NET (j\[0\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (j\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (j\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE unnamedblk3 (NET (exp\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (exp\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (exp\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) ) (INSTANCE unnamedblk1 (NET (i\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (i\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE unnamedblk2 (NET (j\[0\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (j\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (j\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE unnamedblk3 (NET (exp\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 15)) (exp\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) ) (INSTANCE i_sub4_1 (NET (P0\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (in\[0\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 8)) (in\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 12)) (in\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 7)) (in\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3)) (in\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1)) (in\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (out\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12)) (out\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7)) (out\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (out\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1)) (out\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (ff\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12)) (ff\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7)) (ff\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (ff\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1)) (ff\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[0][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[1][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (count\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8)) (count\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4)) (count\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (count\[4\] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1)) (count\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE i_sub5 (NET (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (in[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[0][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (count\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8)) (count\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4)) (count\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (count\[4\] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1)) (count\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val0[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val0[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val1[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val1[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val2[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val2[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val3[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val3[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val3[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE i_sub0 (NET (P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P1\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE i_sub1 (NET (P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P1\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE i_sub2 (NET (P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P1\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE i_sub3 (NET (P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P1\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE unnamedblk1 (NET (i\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (i\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE unnamedblk2 (NET (j\[0\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (j\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (j\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE unnamedblk3 (NET (exp\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (exp\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (exp\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) ) (INSTANCE unnamedblk1 (NET (i\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (i\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE unnamedblk2 (NET (j\[0\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (j\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (j\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE unnamedblk3 (NET (exp\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 15)) (exp\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) ) ) (INSTANCE i_sub3_2 (NET (P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNPACKED_ARRAY[1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNPACKED_ARRAY[1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNUSED\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (UNUSED\[2\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[3\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[4\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[5\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[6\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[7\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[8\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[9\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[10\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[11\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[12\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[13\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[14\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (UNUSED\[15\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (ENUM\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (ENUM\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (in\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (in\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10)) (in\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6)) (in\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (in\[4\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1)) (in\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (out\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12)) (out\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7)) (out\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (out\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1)) (out\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[0\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 8)) (ff\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 12)) (ff\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 7)) (ff\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3)) (ff\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1)) (ff\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out4\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (out4\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12)) (out4\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7)) (out4\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (out4\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1)) (out4\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out4\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out4\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out4_2\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (out4_2\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12)) (out4_2\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7)) (out4_2\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (out4_2\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1)) (out4_2\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out4_2\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out4_2\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE i_sub4_0 (NET (P0\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (in\[0\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 8)) (in\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 12)) (in\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 7)) (in\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3)) (in\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1)) (in\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (out\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12)) (out\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7)) (out\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (out\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1)) (out\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (ff\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12)) (ff\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7)) (ff\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (ff\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1)) (ff\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[0][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[1][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (count\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8)) (count\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4)) (count\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (count\[4\] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1)) (count\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE i_sub5 (NET (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (in[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[0][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (count\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8)) (count\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4)) (count\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (count\[4\] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1)) (count\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val0[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val0[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val1[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val1[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val2[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val2[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val3[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val3[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val3[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE i_sub0 (NET (P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P1\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE i_sub1 (NET (P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P1\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE i_sub2 (NET (P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P1\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE i_sub3 (NET (P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P1\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE unnamedblk1 (NET (i\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (i\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE unnamedblk2 (NET (j\[0\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (j\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (j\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE unnamedblk3 (NET (exp\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (exp\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (exp\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) ) (INSTANCE unnamedblk1 (NET (i\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (i\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE unnamedblk2 (NET (j\[0\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (j\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (j\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE unnamedblk3 (NET (exp\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 15)) (exp\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) ) (INSTANCE i_sub4_1 (NET (P0\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P3\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (in\[0\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 8)) (in\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 12)) (in\[2\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 7)) (in\[3\] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3)) (in\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1)) (in\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (out\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12)) (out\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7)) (out\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (out\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1)) (out\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7)) (ff\[1\] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12)) (ff\[2\] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7)) (ff\[3\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3)) (ff\[4\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1)) (ff\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ff\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[0][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[0][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (sub5_in[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_in[1][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[1][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (sub5_out[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (sub5_out[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (count\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8)) (count\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4)) (count\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (count\[4\] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1)) (count\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE i_sub5 (NET (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (in[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[0][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (count\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8)) (count\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4)) (count\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (count\[4\] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1)) (count\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val0[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val0[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val1[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val1[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val2[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val2[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val3[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val3[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val3[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE i_sub0 (NET (P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P1\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE i_sub1 (NET (P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P1\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE i_sub2 (NET (P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P1\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE i_sub3 (NET (P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P1\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE unnamedblk1 (NET (i\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (i\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE unnamedblk2 (NET (j\[0\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (j\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (j\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE unnamedblk3 (NET (exp\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (exp\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (exp\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) ) (INSTANCE unnamedblk1 (NET (i\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (i\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE unnamedblk2 (NET (j\[0\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (j\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (j\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE unnamedblk3 (NET (exp\[0\] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 15)) (exp\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) ) ) ) ) ) (INSTANCE top.t.i_sub3.i_sub4_0.i_sub5 (NET (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (in[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[0][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE sub5 (NET (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (in[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[0][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (count\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8)) (count\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4)) (count\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (count\[4\] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1)) (count\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val0[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val0[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val1[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val1[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val2[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val2[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val3[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val3[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val3[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE i_sub0 (NET (P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P1\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE i_sub1 (NET (P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P1\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE i_sub2 (NET (P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P1\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE i_sub3 (NET (P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P1\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE unnamedblk1 (NET (i\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (i\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE unnamedblk2 (NET (j\[0\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (j\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (j\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE unnamedblk3 (NET (exp\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (exp\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (exp\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) ) ) (INSTANCE top.t.i_sub3.i_sub4_1.i_sub5 (NET (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (in[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[0][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE sub5 (NET (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (in[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[0][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (count\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8)) (count\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4)) (count\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (count\[4\] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1)) (count\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val0[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val0[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val1[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val1[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val2[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val2[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val3[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val3[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val3[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE i_sub0 (NET (P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P1\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE i_sub1 (NET (P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P1\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE i_sub2 (NET (P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P1\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE i_sub3 (NET (P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P1\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE unnamedblk1 (NET (i\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (i\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE unnamedblk2 (NET (j\[0\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (j\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (j\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE unnamedblk3 (NET (exp\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (exp\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (exp\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) ) ) (INSTANCE top.t.i_sub3_2.i_sub4_0.i_sub5 (NET (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (in[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[0][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE sub5 (NET (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (in[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[0][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (count\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8)) (count\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4)) (count\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (count\[4\] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1)) (count\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val0[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val0[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val1[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val1[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val2[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val2[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val3[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val3[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val3[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE i_sub0 (NET (P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P1\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE i_sub1 (NET (P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P1\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE i_sub2 (NET (P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P1\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE i_sub3 (NET (P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P1\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE unnamedblk1 (NET (i\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (i\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE unnamedblk2 (NET (j\[0\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (j\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (j\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE unnamedblk3 (NET (exp\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (exp\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (exp\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) ) ) (INSTANCE top.t.i_sub3_2.i_sub4_1.i_sub5 (NET (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (in[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[0][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE sub5 (NET (clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33)) (in[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[0][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[0][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][0]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][1]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (in[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (in[1][2]\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][0]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][1]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[0][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][0]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (out[1][2]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1][2]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17)) (count\[1\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8)) (count\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4)) (count\[3\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2)) (count\[4\] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1)) (count\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (count\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val0[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val0[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val0[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val1[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val1[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val1[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val2[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val2[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val2[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val3[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val3[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (val3[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (val3[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE i_sub0 (NET (P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P1\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE i_sub1 (NET (P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P1\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE i_sub2 (NET (P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P1\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE i_sub3 (NET (P0\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P0\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P0\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P1\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (P1\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (P1\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[0]\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[0]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[0\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[1]\[1\] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1)) (out[1]\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (out[1]\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE unnamedblk1 (NET (i\[0\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (i\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE unnamedblk2 (NET (j\[0\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (j\[1\] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1)) (j\[2\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (j\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE unnamedblk3 (NET (exp\[0\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (exp\[1\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[2\] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16)) (exp\[3\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[4\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[5\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[6\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[7\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[8\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[9\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[10\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[11\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[12\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[13\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[14\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[15\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[16\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[17\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[18\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[19\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[20\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[21\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[22\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[23\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[24\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[25\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[26\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[27\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[28\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[29\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[30\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[31\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[32\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[33\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[34\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[35\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[36\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[37\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[38\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[39\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[40\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[41\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[42\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[43\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[44\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[45\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[46\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[47\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[48\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[49\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[50\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[51\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[52\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[53\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[54\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[55\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[56\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[57\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[58\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[59\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[60\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[61\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[62\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[63\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[64\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[65\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[66\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[67\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[68\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[69\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[70\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[71\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[72\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[73\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[74\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[75\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[76\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[77\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[78\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[79\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[80\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[81\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[82\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[83\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[84\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[85\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[86\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[87\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[88\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[89\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[90\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[91\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[92\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[93\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[94\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[95\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[96\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[97\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[98\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[99\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[100\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[101\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[102\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[103\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[104\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[105\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[106\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[107\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[108\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[109\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[110\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[111\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[112\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[113\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[114\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[115\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[116\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[117\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[118\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[119\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[120\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[121\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[122\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[123\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[124\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[125\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[126\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (exp\[127\] (T0 170) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) ) ) ) verilator-5.042/test_regress/t/t_display_impure.py0000755000542200017500000000103215101701376023010 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.compile(verilator_flags2=["--binary"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_fork_func_bad.v0000644000542200017500000000060115101701376022357 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; function int f; fork return 0; // Illegal 9.3.2 join_none endfunction int i; initial begin i = f(); end endmodule verilator-5.042/test_regress/t/t_math_shortreal_unsup_bad.v0000644000542200017500000000042415101701376024654 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2016 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; shortreal s; initial s = 1.2345; endmodule verilator-5.042/test_regress/t/t_func_const_struct_bad.v0000644000542200017500000000175415101701376024162 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 module t; typedef struct packed { logic [ 31 : 0 ] a; logic [ 31 : 0 ] b; } params_t; localparam params_t P = '{a:5, b:1}; localparam P6 = f_add(P); localparam P14 = f_add2(2, 3, f_add(P)); localparam P24 = f_add2(7, 8, 9); initial begin // Should never get here $write("*-* All Finished *-*\n"); $finish; end function integer f_add(input params_t params); f_add = params.a+params.b; if (f_add == 15) $fatal(2, "f_add = 15"); endfunction // Speced ok: function called from function function integer f_add2(input [31:0] a, input [31:0] b, input [31:0] c); params_t params; params = '{ a: a, b: b }; f_add2 = f_add(params)+c; endfunction endmodule verilator-5.042/test_regress/t/t_array_pattern_bad2.py0000755000542200017500000000076615101701376023542 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface_virtual.py0000755000542200017500000000100015101701376023463 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_restore_prag_bad.v0000644000542200017500000000044315101701376024131 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (); // No matching save // verilator lint_restore endmodule verilator-5.042/test_regress/t/t_property_sexpr.v0000644000542200017500000001141715101701376022711 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ // Inputs clk ); input clk; bit [3:0] val = 0; event e1; event e2; event e3; event e4; event e5; event e6; event e7; event e8; event e9; event e10; event e11; event e12; integer cyc = 1; always @(negedge clk) begin val <= 4'(cyc % 4); if (cyc >= 0 && cyc <= 4) begin ->e1; `ifdef TEST_VERBOSE $display("[%0t] triggered e1", $time); `endif end if (cyc >= 5 && cyc <= 10) begin ->e2; `ifdef TEST_VERBOSE $display("[%0t] triggered e2", $time); `endif end if (cyc >= 11 && cyc <= 15) begin ->e3; `ifdef TEST_VERBOSE $display("[%0t] triggered e3", $time); `endif end if (cyc >= 16 && cyc <= 20) begin ->e4; `ifdef TEST_VERBOSE $display("[%0t] triggered e4", $time); `endif end if (cyc >= 21 && cyc <= 25) begin ->e5; `ifdef TEST_VERBOSE $display("[%0t] triggered e5", $time); `endif end if (cyc >= 26 && cyc <= 30) begin ->e6; `ifdef TEST_VERBOSE $display("[%0t] triggered e6", $time); `endif end if (cyc >= 31 && cyc <= 35) begin ->e7; `ifdef TEST_VERBOSE $display("[%0t] triggered e7", $time); `endif end if (cyc >= 36 && cyc <= 40) begin ->e8; `ifdef TEST_VERBOSE $display("[%0t] triggered e8", $time); `endif end if (cyc >= 41 && cyc <= 45) begin ->e9; `ifdef TEST_VERBOSE $display("[%0t] triggered e9", $time); `endif end if (cyc >= 46 && cyc <= 50) begin ->e10; `ifdef TEST_VERBOSE $display("[%0t] triggered e10", $time); `endif end if (cyc >= 51 && cyc <= 55) begin ->e11; `ifdef TEST_VERBOSE $display("[%0t] triggered e11", $time); `endif end if (cyc >= 56 && cyc <= 60) begin ->e12; `ifdef TEST_VERBOSE $display("[%0t] triggered e12", $time); `endif end `ifdef TEST_VERBOSE $display("cyc=%0d val=%0d", cyc, val); `endif cyc <= cyc + 1; if (cyc == 100) begin $write("*-* All Finished *-*\n"); $finish; end end assert property (@(e1) ##1 1) $display("[%0t] single delay with const stmt, fileline:%0d", $time, `__LINE__); assert property (@(e2) ##1 val[0]) $display("[%0t] single delay with var stmt, fileline:%0d", $time, `__LINE__); else $display("[%0t] single delay with var else, fileline:%0d", $time, `__LINE__); assert property (@(e3) ##2 val[0]) $display("[%0t] single multi-cycle delay with var stmt, fileline:%0d", $time, `__LINE__); else $display("[%0t] single multi-cycle delay with var else, fileline:%0d", $time, `__LINE__); assert property (@(e4) ##1 (val[0])) $display("[%0t] single delay with var brackets 1 stmt, fileline:%0d", $time, `__LINE__); else $display("[%0t] single delay with var brackets 1 else, fileline:%0d", $time, `__LINE__); assert property (@(e5) (##1 (val[0]))) $display("[%0t] single delay with var brackets 2 stmt, fileline:%0d", $time, `__LINE__); else $display("[%0t] single delay with var brackets 2 else, fileline:%0d", $time, `__LINE__); assert property (@(e6) (##1 val[0] && val[1])) $display("[%0t] single delay with negated var stmt, fileline:%0d", $time, `__LINE__); else $display("[%0t] single delay with negated var else, fileline:%0d", $time, `__LINE__); assert property (@(e7) not ##1 val[0]) $display("[%0t] single delay with negated var stmt, fileline:%0d", $time, `__LINE__); else $display("[%0t] single delay with negated var else, fileline:%0d", $time, `__LINE__); assume property (@(e8) not (##1 val[0])) $display("[%0t] single delay with negated var brackets stmt, fileline:%0d", $time, `__LINE__); else $display("[%0t] single delay with negated var brackets else, fileline:%0d", $time, `__LINE__); assume property (@(e9) not (##1 val[0])) else $display("[%0t] single delay with negated var brackets else, fileline:%0d", $time, `__LINE__); assert property (@(e10) not (not ##1 val[0])) $display("[%0t] single delay with nested not stmt, fileline:%0d", $time, `__LINE__); else $display("[%0t] single delay with nested not else, fileline:%0d", $time, `__LINE__); restrict property (@(e11) ##1 val[0]); restrict property (@(e11) not ##1 val[0]); property prop; @(e12) not ##1 val[0] endproperty assert property (prop) $display("[%0t] property, fileline:%0d", $time, `__LINE__); else $display("[%0t] property, fileline:%0d", $time, `__LINE__); assert property (@(posedge clk) not (not ##2 val[0] && val[1])) $display("[%0t] concurrent assert stmt, fileline:%0d", $time, `__LINE__); else $display("[%0t] concurrent assert else, fileline:%0d", $time, `__LINE__); endmodule verilator-5.042/test_regress/t/t_gen_self_return.py0000755000542200017500000000073415101701376023153 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_func_link.v0000644000542200017500000000204215101701376021546 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module Test(/*AUTOARG*/ // Outputs out, // Inputs clk, in ); // Replace this module with the device under test. // // Change the code in the t module to apply values to the inputs and // merge the output values into the result vector. input clk; input [31:0] in; output reg [31:0] out; integer cyc = 0; SubTest subtest(.out); always @(posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d\n", $time, cyc); `endif cyc <= cyc + 1; if (cyc < 99) begin subtest.block.set(in); end else begin $write("[%0t] cyc==%0d\n", $time, cyc); $write("*-* All Finished *-*\n"); $finish; end end endmodule module SubTest( output logic[31:0] out ); if (1) begin : block function void set(logic[31:0] in); out <= in; endfunction end : block endmodule verilator-5.042/test_regress/t/t_gantt_io_arm.py0000755000542200017500000000131215101701376022426 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') test.run(cmd=[ "cd " + test.obj_dir + " && " + os.environ["VERILATOR_ROOT"] + "/bin/verilator_gantt" + " " + test.t_dir + "/" + test.name + ".dat > gantt.log" ], check_finished=False) test.files_identical(test.obj_dir + "/gantt.log", test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_gate_loop.py0000755000542200017500000000075715101701376021750 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["-Wno-UNOPTFLAT"]) test.passes() verilator-5.042/test_regress/t/t_randsequence_recurse.v0000644000542200017500000000162015101701376024004 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2023 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); module t(/*AUTOARG*/); initial begin int o; int i; o = 0; i = 0; randsequence(main) main : recurse recurse; recurse: { i++; if ((i % 4) == 0) break; } add recurse; add: { o++; } ; endsequence `checkd(o, 3); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_opt_table_packed_array.py0000755000542200017500000000130215101701376024440 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--stats"]) if test.vlt_all: test.file_grep(test.stats, r'Optimizations, Tables created\s+(\d+)', 1) test.file_grep(test.stats, r'ConstPool, Tables emitted\s+(\d+)', 1) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_unopt_combo_waive.py0000755000542200017500000000114715101701376023510 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_unopt_combo.v" test.compile(v_flags2=['+define+ATTRIBUTES', "t/t_unopt_combo.vlt", "-fno-dfg"], # Passes, as we waived ) test.passes() verilator-5.042/test_regress/t/t_reloop_offset.out0000644000542200017500000000043315101701376023010 0ustar mahmoudyfreeshellshift down 1 oarray[63] is 0 oarray[62] is 63 oarray[61] is 62 oarray[32] is 33 oarray[ 2] is 3 oarray[ 1] is 2 oarray[ 0] is 1 shift up 2 oarray[63] is 61 oarray[62] is 60 oarray[61] is 59 oarray[32] is 30 oarray[ 2] is 0 oarray[ 1] is 2 oarray[ 0] is 1 *-* All Finished *-* verilator-5.042/test_regress/t/t_disable_task_unsup.py0000755000542200017500000000103015101701376023637 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.lint(verilator_flags2=['--timing'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_inside_unpacked.out0000644000542200017500000000110515101701376023264 0ustar mahmoudyfreeshell%Error: t/t_inside_unpacked.v:17:35: Unsupported: inside (set membership operator) on unpacked array : ... note: In instance 't' 17 | localparam HIT_INSIDE = HIT_LP inside {CHECKLIST_P}; | ^~~~~~ %Error: t/t_inside_unpacked.v:18:37: Unsupported: inside (set membership operator) on unpacked array : ... note: In instance 't' 18 | localparam MISS_INSIDE = MISS_LP inside {CHECKLIST_P}; | ^~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_lint_width.py0000755000542200017500000000070615101701376022136 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.042/test_regress/t/t_display_wide.out0000644000542200017500000000753315101701376022627 0ustar mahmoudyfreeshell[1000] cyc==99 crc=2961926edde3e5c6018be970cdbf327b72b5f3c5eab42995891005eec8767e5fdf03051edbe9d222ee756ee34d8d6c83ee877aad65c487140ac87d26c636a66214b4a69acad924c568cc8e8c79f97d07a6eedf91011919d0e3cdda5215ee58c942f6c4dea48b3f38abc77bf47e4f6d6a859fcc5b5d46ec9d2f6a5bf7b978b1ba7ca15d0713a2eb06ade1570c4e3a12db687625eef8dfebcb4095ab4bdffe79c1298f609307a5ef773a6432b855e3e54deb88ca342bf5a7fecc5f2f3e165a59cdb9179718a2d11c9d55f14d69f40b01e41fcb7335a8872a6ba7876ec684d6a3af0b82aa31cca6e26340a2589cf7bf886faa8d23844596dc71233c7025c5250a968b770ab72db90b03d8c045fb8848159df544a3a3bf063269be0aa11d5507f5c8b328b760a6df9e3fbe276faad8eadee126443ad3f99d595b12d0ae514b20693298a58642a07718f9ab7ea8c66575f7f8d0e3ba77d992235b3d5a4e015a7ff9b97a8c4f48ebdbfc2365e6bca4dd3ba6bfc7e850f7c8e2842c717a1d85a977a033f564fc [1000] cyc==99 crc=001010010110000110010010011011101101110111100011111001011100011000000001100010111110100101110000110011011011111100110010011110110111001010110101111100111100010111101010101101000010100110010101100010010001000000000101111011101100100001110110011111100101111111011111000000110000010100011110110110111110100111010010001000101110111001110101011011101110001101001101100011010110110010000011111011101000011101111010101011010110010111000100100001110001010000001010110010000111110100100110110001100011011010100110011000100001010010110100101001101001101011001010110110010010010011000101011010001100110010001110100011000111100111111001011111010000011110100110111011101101111110010001000000010001100100011001110100001110001111001101110110100101001000010101111011100101100011001001010000101111011011000100110111101010010010001011001111110011100010101011110001110111101111110100011111100100111101101101011010101000010110011111110011000101101101011101010001101110110010011101001011110110101001011011111101111011100101111000101100011011101001111100101000010101110100000111000100111010001011101011000001101010110111100001010101110000110001001110001110100001001011011011011010000111011000100101111011101111100011011111111010111100101101000000100101011010101101001011110111111111111001111001110000010010100110001111011000001001001100000111101001011110111101110111001110100110010000110010101110000101010111100011111001010100110111101011100010001100101000110100001010111111010110100111111111101100110001011111001011110011111000010110010110100101100111001101101110010001011110010111000110001010001011010001000111001001110101010101111100010100110101101001111101000000101100000001111001000001111111001011011100110011010110101000100001110010101001101011101001111000011101101110110001101000010011010110101000111010111100001011100000101010101000110001110011001010011011100010011000110100000010100010010110001001110011110111101111111000100001101111101010101000110100100011100001000100010110010110110111000111000100100011001111000111000000100101110001010010010100001010100101101000101101110111000010101011011100101101101110010000101100000011110110001100000001000101111110111000100001001000000101011001110111110101010001001010001110100011101111110000011000110010011010011011111000001010101000010001110101010101000001111111010111001000101100110010100010110111011000001010011011011111100111100011111110111110001001110110111110101010110110001110101011011110111000010010011001000100001110101101001111111001100111010101100101011011000100101101000010101110010100010100101100100000011010010011001010011000101001011000011001000010101000000111011100011000111110011010101101111110101010001100011001100101011101011111011111111000110100001110001110111010011101111101100110010010001000110101101100111101010110100100111000000001010110100111111111111001101110010111101010001100010011110100100011101011110110111111110000100011011001011110011010111100101001001101110100111011101001101011111111000111111010000101000011110111110010001110001010000100001011000111000101111010000111011000010110101001011101111010000000110011111101010110010011111100 *-* All Finished *-* verilator-5.042/test_regress/t/t_class_ref_ref.py0000755000542200017500000000070615101701376022566 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.042/test_regress/t/t_interface_gen6_noinl.py0000755000542200017500000000103715101701376024045 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_gen6.v" test.compile(v_flags2=["-fno-inline"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_opt_const_cond_redundant.py0000755000542200017500000000124415101701376025046 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--stats']) test.execute() test.file_grep(test.stats, r'Optimizations, Cond redundant expressions\s+(\d+)', 1) test.file_grep(test.stats, r'Optimizations, If cond redundant expressions\s+(\d+)', 1) test.passes() verilator-5.042/test_regress/t/t_interface_gen7.py0000755000542200017500000000073415101701376022652 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_display_cwide_bad.out0000644000542200017500000000063115101701376023570 0ustar mahmoudyfreeshell%Warning-WIDTHTRUNC: t/t_display_cwide_bad.v:10:7: $display-like format of %c format of > 8 bit value 10 | $display("%c", 32'h1234); | ^~~~~~~~ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_select_2d.py0000755000542200017500000000073415101701376021636 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_stream_integer_type.py0000755000542200017500000000073415101701376024043 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_gen9.py0000755000542200017500000000073415101701376022654 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_json_only_flat_pub_mod.out0000644000542200017500000001354615101701376024700 0ustar mahmoudyfreeshell{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"(E)", "modulesp": [ {"type":"MODULE","name":"$root","addr":"(F)","loc":"d,11:8,11:11","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"$root","level":1,"modPublic":true,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"i_clk","addr":"(G)","loc":"d,11:24,11:29","dtypep":"(H)","origName":"i_clk","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"top.i_clk","addr":"(I)","loc":"d,11:24,11:29","dtypep":"(H)","origName":"i_clk","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"top.f.i_clk","addr":"(J)","loc":"d,7:24,7:29","dtypep":"(H)","origName":"i_clk","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"TOPSCOPE","name":"","addr":"(E)","loc":"d,11:8,11:11","senTreesp": [], "scopep": [ {"type":"SCOPE","name":"TOP","addr":"(K)","loc":"d,11:8,11:11","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(F)", "varsp": [ {"type":"VARSCOPE","name":"i_clk","addr":"(L)","loc":"d,11:24,11:29","dtypep":"(H)","isTrace":true,"scopep":"(K)","varp":"(G)"}, {"type":"VARSCOPE","name":"top.i_clk","addr":"(M)","loc":"d,11:24,11:29","dtypep":"(H)","isTrace":true,"scopep":"(K)","varp":"(I)"}, {"type":"ALWAYS","name":"","addr":"(N)","loc":"d,11:24,11:29","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(O)","loc":"d,11:24,11:29","dtypep":"(H)", "rhsp": [ {"type":"VARREF","name":"i_clk","addr":"(P)","loc":"d,11:24,11:29","dtypep":"(H)","access":"RD","varp":"(G)","varScopep":"(L)","classOrPackagep":"UNLINKED"} ], "lhsp": [ {"type":"VARREF","name":"top.i_clk","addr":"(Q)","loc":"d,11:24,11:29","dtypep":"(H)","access":"WR","varp":"(I)","varScopep":"(M)","classOrPackagep":"UNLINKED"} ],"timingControlp": [],"strengthSpecp": []} ]}, {"type":"VARSCOPE","name":"top.f.i_clk","addr":"(R)","loc":"d,7:24,7:29","dtypep":"(H)","isTrace":true,"scopep":"(K)","varp":"(J)"}, {"type":"ALWAYS","name":"","addr":"(S)","loc":"d,7:24,7:29","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(T)","loc":"d,7:24,7:29","dtypep":"(H)", "rhsp": [ {"type":"VARREF","name":"i_clk","addr":"(U)","loc":"d,7:24,7:29","dtypep":"(H)","access":"RD","varp":"(G)","varScopep":"(L)","classOrPackagep":"UNLINKED"} ], "lhsp": [ {"type":"VARREF","name":"top.f.i_clk","addr":"(V)","loc":"d,7:24,7:29","dtypep":"(H)","access":"WR","varp":"(J)","varScopep":"(R)","classOrPackagep":"UNLINKED"} ],"timingControlp": [],"strengthSpecp": []} ]} ],"blocksp": [],"inlinesp": []} ]} ]} ],"filesp": [], "miscsp": [ {"type":"TYPETABLE","name":"","addr":"(C)","loc":"a,0:0,0:0","constraintRefp":"UNLINKED","emptyQueuep":"UNLINKED","queueIndexp":"UNLINKED","streamp":"UNLINKED","voidp":"UNLINKED", "typesp": [ {"type":"BASICDTYPE","name":"logic","addr":"(H)","loc":"d,11:18,11:23","dtypep":"(H)","keyword":"logic","generic":true,"rangep": []} ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ {"type":"MODULE","name":"@CONST-POOL@","addr":"(W)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], "stmtsp": [ {"type":"SCOPE","name":"@CONST-POOL@","addr":"(X)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(W)","varsp": [],"blocksp": [],"inlinesp": []} ]} ]} ]} verilator-5.042/test_regress/t/t_enum_bad_value.out0000644000542200017500000000270615101701376023115 0ustar mahmoudyfreeshell%Error-ENUMITEMWIDTH: t/t_enum_bad_value.v:12:37: Enum value exceeds width of enum type (IEEE 1800-2023 6.19) : ... note: In instance 't' 12 | typedef enum [2:0] { VALUE_BAD1 = 8 } enum_t; | ^ ... For error description see https://verilator.org/warn/ENUMITEMWIDTH?v=latest %Error-ENUMITEMWIDTH: t/t_enum_bad_value.v:14:29: Enum value exceeds width of enum type (IEEE 1800-2023 6.19) : ... note: In instance 't' 14 | enum bit [4:0] {BAD2[4] = 100} bad2; | ^~~ %Warning-WIDTHTRUNC: t/t_enum_bad_value.v:14:19: Operator ADD expects 5 bits on the LHS, but LHS's CONST '?32?sh64' generates 32 or 7 bits. : ... note: In instance 't' 14 | enum bit [4:0] {BAD2[4] = 100} bad2; | ^~~~ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error-ENUMITEMWIDTH: t/t_enum_bad_value.v:16:28: Enum value exceeds width of enum type (IEEE 1800-2023 6.19) : ... note: In instance 't' 16 | enum logic [3:0] {BAD3 = 5'bxxxxx} bad3; | ^~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_class_extends_param.v0000644000542200017500000000722215101701376023622 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ ); class Foo; class InnerFoo; int y = 10; function int get_y; return y; endfunction function int get_30; return 30; endfunction endclass int x = 1; InnerFoo foo = new; function int get_x; return x; endfunction function int get_3; return 3; endfunction function InnerFoo get_foo; return foo; endfunction endclass class Bar #(type T=Foo) extends T; endclass class Baz; class InnerFoo; int y = 20; function int get_y; return y; endfunction function int get_40; return 40; endfunction endclass int x = 2; InnerFoo foo = new; function int get_x; return x; endfunction function int get_4; return 4; endfunction function InnerFoo get_foo; return foo; endfunction endclass class ExtendBar extends Bar#(); function int get_x; return super.get_x(); endfunction function int get_6; return 2 * get_3(); endfunction endclass class ExtendBar1 extends Bar #(Foo); function int get_x; return super.get_x(); endfunction function int get_6; return 2 * get_3(); endfunction endclass class ExtendBarBaz extends Bar #(Baz); function int get_x; return super.get_x(); endfunction function int get_8; return 2 * get_4(); endfunction endclass class ExtendExtendBar extends ExtendBar; function int get_12; return 4 * get_3(); endfunction endclass class FooDict; Foo q[int]; endclass class ExtendFooDict#(type BASE=FooDict) extends BASE; function int get_x_of_item(int i); return q[i].x; endfunction function int get_y_of_item(int i); return q[i].get_foo().get_y(); endfunction endclass Bar #() bar_foo_i; Bar #(Baz) bar_baz_i; ExtendBar extend_bar_i; ExtendBar1 extend_bar1_i; ExtendBarBaz extend_bar_baz_i; ExtendExtendBar extend_extend_bar_i; ExtendFooDict extend_foo_dict_i; initial begin bar_foo_i = new; bar_baz_i = new; extend_bar_i = new; extend_bar1_i = new; extend_bar_baz_i = new; extend_extend_bar_i = new; extend_foo_dict_i = new; extend_foo_dict_i.q[1] = new; if (bar_foo_i.get_x() != 1) $stop; if (bar_foo_i.get_3() != 3) $stop; if (bar_foo_i.get_foo().get_y() != 10) $stop; if (bar_foo_i.get_foo().get_30() != 30) $stop; if (bar_baz_i.get_x() != 2) $stop; if (bar_baz_i.get_4() != 4) $stop; if (bar_baz_i.get_foo().get_y() != 20) $stop; if (bar_baz_i.get_foo().get_40() != 40) $stop; if (extend_bar_i.get_x() != 1) $stop; if (extend_bar_i.get_6() != 6) $stop; if (extend_bar_i.get_x() != 1) $stop; if (extend_bar_i.get_6() != 6) $stop; if (extend_bar1_i.get_x() != 1) $stop; if (extend_bar1_i.get_6() != 6) $stop; if (extend_bar_baz_i.get_x() != 2) $stop; if (extend_bar_baz_i.get_8() != 8) $stop; if (extend_extend_bar_i.get_x() != 1) $stop; if (extend_extend_bar_i.get_12() != 12) $stop; if (extend_foo_dict_i.get_x_of_item(1) != 1) $stop; if (extend_foo_dict_i.get_y_of_item(1) != 10) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_lint_unsigned_bad.out0000644000542200017500000000072315101701376023614 0ustar mahmoudyfreeshell%Warning-UNSIGNED: t/t_lint_unsigned_bad.v:13:15: Comparison is constant due to unsigned arithmetic : ... note: In instance 't' 13 | if (uns < 0) $stop; | ^ ... For warning description see https://verilator.org/warn/UNSIGNED?v=latest ... Use "/* verilator lint_off UNSIGNED */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_class_param_typedef2.py0000755000542200017500000000073415101701376024061 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_incabspath.py0000755000542200017500000000070315101701376023130 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint() test.passes() verilator-5.042/test_regress/t/t_trace_empty.py0000755000542200017500000000105515101701376022303 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--trace-vcd']) test.execute() test.file_grep_not(test.trace_filename, r'var') test.passes() verilator-5.042/test_regress/t/t_uniqueif_fail4.py0000755000542200017500000000131415101701376022671 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_uniqueif.v" test.compile(v_flags2=['+define+FAILING_ASSERTION4'], verilator_flags2=['--assert'], nc_flags2=['+assert'], fails=test.nc) test.execute(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_var_assign_landr.v0000644000542200017500000000443015101701376023115 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [255:0] sum; // Take CRC data and apply to testblock inputs wire [127:0] in = {~crc[63:0], crc[63:0]}; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [127:0] o1; // From test of Test.v wire [127:0] o2; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .o1 (o1[127:0]), .o2 (o2[127:0]), // Inputs .in (in[127:0])); // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x %x\n", $time, cyc, crc, o1, o2); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= {o1,o2} ^ {sum[254:0],sum[255]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc<10) begin sum <= '0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 256'h008a080aaa000000140550404115dc7b008a080aaae7c8cd897bc1ca49c9350a if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs o1, o2, // Inputs in ); input [127:0] in; output logic [127:0] o1; output logic [127:0] o2; always_comb begin: b_test logic [127:0] tmpp; logic [127:0] tmp; tmp = '0; tmpp = '0; tmp[63:0] = in[63:0]; tmpp[63:0] = in[63:0]; tmpp[63:0] = {tmp[0+:32], tmp[32+:32]}; tmp[63:0] = {tmp[0+:32], tmp[32+:32]}; o1 = tmp; o2 = tmpp; end endmodule verilator-5.042/test_regress/t/t_vlt_timing.vlt0000644000542200017500000000057015101701376022316 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `verilator_config timing_on --file "t/t_timing_off.v" --lines 23 timing_off -file "t/t_timing_off.v" -lines 26-34 timing_on -file "t/t_timing_off.v" -lines 35-38 verilator-5.042/test_regress/t/t_disable_fork2.v0000644000542200017500000000347115101701376022313 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 // USING THIS FOR DEBUGGING PROCESS PROPAGATION: // // The example contains most cases that were problematic during the // works on support of 'disable fork' statement, including: // // - indirect use of disable fork (through a task), // - indirect use of forks that are to be disabled, // - forks in forks, // - a function taking VlProcess argument shared between a process that // allocates VlProcess, and one that doesnt, // - a function that has a delay and obtains VlProcess argument, // - a function that has a delay and doesn't obtain it, // - an empty fork with disable fork. // // Blocks below contain info on whether they should (YES) or shouldn't (NO) // be emitted as functions with a VlProcess argument. // // To check if that corresponds to reality, see blue nodes in proc_deps.dot class Cls; task print; /*NO*/ $write("*-* All "); endtask task disable_fork_func; /*YES*/ disable fork; endtask task common_func; /*YES*/ fork /*YES*/ #1; join_none endtask task fork_func; /*YES*/ fork /*YES*/ #1 $stop; join_none endtask task delay_func; /*NO*/ fork /*NO*/ #1 $write("Finished *-*\n"); join_none endtask task empty_fork; fork begin end join_none disable fork; endtask endclass module t; Cls cls = new; initial begin /*YES*/ fork /*YES*/ cls.common_func(); join_none cls.fork_func(); cls.disable_fork_func(); cls.empty_fork(); cls.print(); end initial begin /*NO*/ cls.delay_func(); cls.common_func(); fork /*YES*/ disable fork; join_none end endmodule verilator-5.042/test_regress/t/t_assert_enabled_on_bad.py0000755000542200017500000000104315101701376024241 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_assert_on.v" test.compile(verilator_flags2=["--assert"]) test.execute(fails=True) test.passes() verilator-5.042/test_regress/t/t_vpi_onetime_cbs.py0000755000542200017500000000136215101701376023135 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(make_top_shell=False, make_main=False, make_pli=True, verilator_flags2=["--exe --vpi", test.pli_filename], iv_flags2=["-g2005-sv -D USE_VPI_NOT_DPI -DIVERILOG"], v_flags2=["+define+USE_VPI_NOT_DPI"]) test.execute(use_libvpi=True) test.passes() verilator-5.042/test_regress/t/t_covergroup_coverpoints_unsup.py0000755000542200017500000000113715101701376026050 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if test.vlt_all: test.lint(fails=True, expect_filename=test.golden_filename) else: test.compile(nc_flags2=["-coverage", "functional"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_randomize_method_with_scoping.py0000755000542200017500000000104615101701376026074 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_param_circ_bad.v0000644000542200017500000000066515101701376023702 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef class ClsB; class ClsA #(parameter PARAM = 12); ClsB #(PARAM+1) b; endclass class ClsB #(parameter PARAM = 12); ClsA #(PARAM+1) a; endclass module t; ClsA #(.PARAM(15)) c; // Bad param name endmodule verilator-5.042/test_regress/t/t_tri_gate_bufif1_pins_inout.py0000755000542200017500000000141215101701376025265 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_tri_gate.cpp" test.top_filename = "t/t_tri_gate.v" test.compile(make_top_shell=False, make_main=False, v_flags2=['+define+T_BUFIF1'], make_flags=['CPPFLAGS_ADD=-DT_BUFIF1'], verilator_flags2=["--exe --pins-inout-enables", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_ar3.out0000644000542200017500000000132415101701376022647 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_interface_ar3.v:16:36: Unsupported: interface slices : ... note: In instance 't' 16 | sub sub01 [2] (.clk, .infc(iinst[0:1])); | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Internal Error: t/t_interface_ar3.v:16:36: ../V3Inst.cpp:#: No interface varref under array : ... note: In instance 't' 16 | sub sub01 [2] (.clk, .infc(iinst[0:1])); | ^ ... This fatal error may be caused by the earlier error(s); resolve those first. verilator-5.042/test_regress/t/t_mailbox_class.py0000755000542200017500000000075115101701376022611 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.passes() verilator-5.042/test_regress/t/t_vlt_match_contents.out0000644000542200017500000000102715101701376024040 0ustar mahmoudyfreeshell%Warning-UNUSEDSIGNAL: t/t_vlt_match_contents.v:11:10: Signal is not driven, nor used: 'usignal_contents_mismatch' : ... note: In instance 't' 11 | logic usignal_contents_mismatch; | ^~~~~~~~~~~~~~~~~~~~~~~~~ ... For warning description see https://verilator.org/warn/UNUSEDSIGNAL?v=latest ... Use "/* verilator lint_off UNUSEDSIGNAL */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_constraint_dist_randc_bad.py0000755000542200017500000000077615101701376025164 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_unopt_combo.vlt0000644000542200017500000000053215101701376022464 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `verilator_config lint_off -rule UNOPTFLAT -file "*t_unopt_combo.v" -match "Signal unoptimizable: Circular combinational logic: *" verilator-5.042/test_regress/t/t_threads_counter.v0000644000542200017500000000077015101701376022775 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; int cyc; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc!=0) begin if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.042/test_regress/t/t_dist_whitespace.py0000755000542200017500000001031715101701376023147 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') Tabs_Exempt_Re = r'(\.out$)|(/gtkwave)|(Makefile)|(\.mk$)|(\.mk\.in$)|test_regress/t/t_preproc\.v|install-sh' def get_source_files(): git_files = test.run_capture("cd " + test.root + " && git ls-files") if test.verbose: print("MF " + git_files) files = {} for filename in git_files.split(): if filename == '': continue files[filename] = True return files if not os.path.exists(test.root + "/.git"): test.skip("Not in a git repository") files = get_source_files() warns = {} fcount = 0 for filename in sorted(files.keys()): filename = os.path.join(test.root, filename) if not os.path.exists(filename): # git file might be deleted but not yet staged continue contents = test.file_contents(filename) if re.search(r'(\.out|\.dat)$', filename): continue # Ignore golden files if re.search(r'[\001\002\003\004\005\006]', contents): continue # Ignore binary files if contents != "" and contents[-1] != "\n": contents += "\n" warns[filename] = "Missing trailing newline (add one) in " + filename if "\r" in contents: contents = re.sub(r'\r', '', contents) warns[filename] = "Carriage returns (remove them) in: " + filename if "\f" in contents: contents = re.sub(r'\f', '', contents) warns[filename] = "Form-feeds (remove them) in: " + filename if "\t" in contents and not re.search(Tabs_Exempt_Re, filename): warns[filename] = "Tabs (cannot --gold fix) in " + filename if (re.search(r'[ \t]\n', contents) or re.search(r'\n\n+$', contents)): # Regexp repeated below eol_ws_exempt = ('spelling.txt' in filename or '/gtkwave/' in filename) if eol_ws_exempt: continue if 'HARNESS_UPDATE_GOLDEN' in os.environ: changes = False (contents, n) = re.subn(r'[ \t]+\n', '\n', contents) if n: changes = True if not eol_ws_exempt: (contents, n) = re.subn(r'\n\n+$', '\n', contents) if n: changes = True if not changes: continue warns[filename] = "Updated whitespace at " + filename test.write_wholefile(filename, contents) continue lineno = 0 for line in contents.splitlines(): lineno += 1 if re.search(r'\s$', line): warns[filename] = "Trailing whitespace at " + filename + ":" + str(lineno) warns[filename] += " (last character is ASCII " + str(ord(line[-1])) + ")" if not eol_ws_exempt and re.search(r'\n\n+$', contents): # Regexp repeated above warns[filename] = "Trailing newlines at EOF in " + filename # Unicode checker; should this be done in another file? # No way to auto-fix. unicode_exempt = (re.search(r'Changes$', filename) or re.search(r'CONTRIBUTORS$', filename) or re.search(r'contributors.rst$', filename) or re.search(r'spelling.txt$', filename)) if not unicode_exempt and re.search(r'[^ \t\r\n\x20-\x7e]', contents): warns[filename] = "Warning: non-ASCII contents in " + filename fcount += 1 if fcount < 50: test.error("Too few source files found") if len(warns): # First warning lists everything as that's shown in the driver summary msg = "" if 'HARNESS_UPDATE_GOLDEN' in os.environ: msg += "Updated files with whitespace errors: " + ' '.join(sorted(warns.keys())) + "\n" else: msg += "Files have whitespace errors: " + ' '.join(sorted(warns.keys())) + "\n" msg += "To auto-fix: HARNESS_UPDATE_GOLDEN=1 {command} or --golden\n" for filename in sorted(warns.keys()): msg += warns[filename] + "\n" test.error(msg) test.passes() verilator-5.042/test_regress/t/t_x_rand_stability.v0000644000542200017500000000421115101701376023135 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Confirm x randomization stability // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; int cyc = 0; logic [31:0] uninitialized; logic [31:0] x_assigned = '0; `ifdef ADD_SIGNAL logic [31:0] added; logic [31:0] x_assigned_added = '0; `endif logic [31:0] unused; logic [31:0] x_assigned_unused = '0; logic [31:0] uninitialized2; logic [255:0] big; int random_init = $random(); sub_no_inline the_sub_no_inline_1(); sub_no_inline the_sub_no_inline_2(); sub_yes_inline the_sub_yes_inline_1(); sub_yes_inline the_sub_yes_inline_2(); initial begin $display("uninitialized = 0x%x", uninitialized); $display("x_assigned (initial) = 0x%x", x_assigned); $display("uninitialized2 = 0x%x", uninitialized2); $display("big = 0x%x", big); $display("random_init = 0x%x", random_init); end always @(posedge clk) begin x_assigned_unused = 'x; x_assigned <= 'x; `ifdef ADD_SIGNAL x_assigned_added <= 'x; `endif cyc <= cyc + 1; $display("rand = 0x%x", $random()); if (cyc == 4) begin $display("x_assigned = 0x%x", x_assigned); `ifndef NOT_RAND if (uninitialized == uninitialized2) $stop(); if (the_sub_yes_inline_1.no_init == the_sub_yes_inline_2.no_init) $stop(); if (the_sub_no_inline_1.no_init == the_sub_no_inline_2.no_init) $stop(); `endif `ifdef ADD_SIGNAL if (added == 0) $stop(); if (x_assigned_added == 0) $stop(); `endif $display("Last rand = 0x%x", $random()); $write("*-* All Finished *-*\n"); $finish; end end endmodule module sub_no_inline; /* verilator no_inline_module */ logic [63:0] no_init; initial $display("%m no_init 0x%0x", no_init); endmodule module sub_yes_inline; /* verilator inline_module */ logic [63:0] no_init; initial $display("%m no_init 0x%0x", no_init); endmodule verilator-5.042/test_regress/t/t_randomize_rand_mode_unsup.out0000644000542200017500000000343015101701376025374 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_randomize_rand_mode_unsup.v:17:22: Unsupported: 'rand_mode()' on dynamic array element : ... note: In instance 't' 17 | p.m_dyn_arr[0].rand_mode(0); | ^~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_randomize_rand_mode_unsup.v:18:22: Unsupported: 'rand_mode()' on unpacked array element : ... note: In instance 't' 18 | p.m_unp_arr[0].rand_mode(0); | ^~~~~~~~~ %Error-UNSUPPORTED: t/t_randomize_rand_mode_unsup.v:19:20: Unsupported: 'rand_mode()' on unpacked struct element : ... note: In instance 't' 19 | p.m_struct.y.rand_mode(0); | ^~~~~~~~~ %Error-UNSUPPORTED: t/t_randomize_rand_mode_unsup.v:20:18: Unsupported: 'rand_mode()' on static variable : ... note: In instance 't' 20 | p.m_static.rand_mode(0); | ^~~~~~~~~ %Error-UNSUPPORTED: t/t_randomize_rand_mode_unsup.v:21:57: Unsupported: 'rand_mode()' on static variable : ... note: In instance 't' 21 | $display("p.m_static.rand_mode()=%0d", p.m_static.rand_mode()); | ^~~~~~~~~ %Error-UNSUPPORTED: t/t_randomize_rand_mode_unsup.v:22:9: Unsupported: 'rand_mode()' on static variable: 'm_static' : ... note: In instance 't' 22 | p.rand_mode(0); | ^~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_dpi_arg_input_unpack.v0000644000542200017500000015357215101701376024002 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2020 by Yutetsu TAKATSUKASA. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VCS `define NO_TIME `endif `ifdef NC `define NO_TIME `define NO_INTEGER `define NO_SHORTREAL `endif `ifdef MS `define NO_BITS_TO_SCALAR `endif `ifdef VERILATOR `define NO_SHORTREAL `define NO_UNPACK_STRUCT `else `endif `ifdef NO_BITS_TO_SCALAR `define ARE_SAME(act, exp) ((act) == (exp)) `else `define ARE_SAME(act, exp) ((act) == (($bits(act))'(exp))) `endif `define CHECK_VAL(act, exp) if (`ARE_SAME(act, exp)) begin \ if (ENABLE_VERBOSE_MESSAGE)$display(`"act`", ":", (act), " as expected"); \ end else begin \ $display("Mismatch %s expected:%d actual:%d at %d", `"act`", \ int'(exp), int'(act), `__LINE__); \ $stop; \ end `define CHECK_0D(val) \ `CHECK_VAL((val), 42) `define CHECK_1D(val) \ `CHECK_VAL(val[0], 43); \ `CHECK_VAL(val[1], 44) `define CHECK_2D(val) \ `CHECK_VAL(val[0][1], 45); \ `CHECK_VAL(val[1][1], 46); \ `CHECK_VAL(val[2][1], 47) `define CHECK_3D(val) \ `CHECK_VAL(val[0][0][0], 48); \ `CHECK_VAL(val[1][0][0], 49); \ `CHECK_VAL(val[2][0][0], 50); \ `CHECK_VAL(val[3][0][0], 51) `define CHECK_1D1(val) \ `CHECK_VAL(val[0], 52) `define CHECK_2D1(val) \ `CHECK_VAL(val[0][0], 53) `define CHECK_3D1(val) \ `CHECK_VAL(val[0][0][0], 54) `define SET_VALUES(val) \ /* verilator lint_off WIDTH */ \ val[3][2][1] = 42; \ val[2][1][0] = 43; val[2][1][1] = 44; \ val[1][0][1] = 45; val[1][1][1] = 46; val[1][2][1] = 47; \ val[0][0][0] = 48; val[1][0][0] = 49; val[2][0][0] = 50; val[3][0][0] = 51 \ /* verilator lint_on WIDTH */ module t; localparam ENABLE_VERBOSE_MESSAGE = 0; // Legal input argument types for DPI functions //====================================================================== // Type definitions //====================================================================== typedef byte byte_array_t[4][3][2]; typedef byte byte_array1_t[1][1][1]; typedef byte unsigned byte_unsigned_array_t[4][3][2]; typedef byte unsigned byte_unsigned_array1_t[1][1][1]; typedef shortint shortint_array_t[4][3][2]; typedef shortint shortint_array1_t[1][1][1]; typedef shortint unsigned shortint_unsigned_array_t[4][3][2]; typedef shortint unsigned shortint_unsigned_array1_t[1][1][1]; typedef int int_array_t[4][3][2]; typedef int int_array1_t[1][1][1]; typedef int unsigned int_unsigned_array_t[4][3][2]; typedef int unsigned int_unsigned_array1_t[1][1][1]; typedef longint longint_array_t[4][3][2]; typedef longint longint_array1_t[1][1][1]; typedef longint unsigned longint_unsigned_array_t[4][3][2]; typedef longint unsigned longint_unsigned_array1_t[1][1][1]; `ifndef NO_TIME typedef time time_array_t[4][3][2]; typedef time time_array1_t[1][1][1]; `endif `ifndef NO_INTEGER typedef integer integer_array_t[4][3][2]; typedef integer integer_array1_t[1][1][1]; `endif typedef real real_array_t[4][3][2]; typedef real real_array1_t[1][1][1]; `ifndef NO_SHORTREAL typedef shortreal shortreal_array_t[4][3][2]; typedef shortreal shortreal_array1_t[1][1][1]; `endif typedef chandle chandle_array_t[4][3][2]; typedef chandle chandle_array1_t[1][1][1]; typedef string string_array_t[4][3][2]; typedef string string_array1_t[1][1][1]; typedef bit bit1_array_t[4][3][2]; typedef bit bit1_array1_t[1][1][1]; typedef bit [6:0] bit7_array_t[4][3][2]; typedef bit [6:0] bit7_array1_t[1][1][1]; typedef bit [120:0] bit121_array_t[4][3][2]; typedef bit [120:0] bit121_array1_t[1][1][1]; typedef logic logic1_array_t[4][3][2]; typedef logic logic1_array1_t[1][1][1]; typedef logic [6:0] logic7_array_t[4][3][2]; typedef logic [6:0] logic7_array1_t[1][1][1]; typedef logic [120:0] logic121_array_t[4][3][2]; typedef logic [120:0] logic121_array1_t[1][1][1]; typedef struct packed { logic [6:0] val; } pack_struct_t; typedef pack_struct_t pack_struct_array_t[4][3][2]; typedef pack_struct_t pack_struct_array1_t[1][1][1]; `ifndef NO_UNPACK_STRUCT typedef struct { logic [120:0] val; } unpack_struct_t; typedef unpack_struct_t unpack_struct_array_t[4][3][2]; typedef unpack_struct_t unpack_struct_array1_t[1][1][1]; `endif //====================================================================== // Imports //====================================================================== // Returns non-null pointer import "DPI-C" function chandle get_non_null(); import "DPI-C" function void i_byte_0d(input byte val); import "DPI-C" function void i_byte_1d(input byte val[2]); import "DPI-C" function void i_byte_2d(input byte val[3][2]); import "DPI-C" function void i_byte_3d(input byte_array_t val); import "DPI-C" function void i_byte_1d1(input byte val[1]); import "DPI-C" function void i_byte_2d1(input byte val[1][1]); import "DPI-C" function void i_byte_3d1(input byte_array1_t val); import "DPI-C" function void i_byte_unsigned_0d(input byte unsigned val); import "DPI-C" function void i_byte_unsigned_1d(input byte unsigned val[2]); import "DPI-C" function void i_byte_unsigned_2d(input byte unsigned val[3][2]); import "DPI-C" function void i_byte_unsigned_3d(input byte_unsigned_array_t val); import "DPI-C" function void i_byte_unsigned_1d1(input byte unsigned val[1]); import "DPI-C" function void i_byte_unsigned_2d1(input byte unsigned val[1][1]); import "DPI-C" function void i_byte_unsigned_3d1(input byte_unsigned_array1_t val); import "DPI-C" function void i_shortint_0d(input shortint val); import "DPI-C" function void i_shortint_1d(input shortint val[2]); import "DPI-C" function void i_shortint_2d(input shortint val[3][2]); import "DPI-C" function void i_shortint_3d(input shortint_array_t val); import "DPI-C" function void i_shortint_1d1(input shortint val[1]); import "DPI-C" function void i_shortint_2d1(input shortint val[1][1]); import "DPI-C" function void i_shortint_3d1(input shortint_array1_t val); import "DPI-C" function void i_shortint_unsigned_0d(input shortint unsigned val); import "DPI-C" function void i_shortint_unsigned_1d(input shortint unsigned val[2]); import "DPI-C" function void i_shortint_unsigned_2d(input shortint unsigned val[3][2]); import "DPI-C" function void i_shortint_unsigned_3d(input shortint_unsigned_array_t val); import "DPI-C" function void i_shortint_unsigned_1d1(input shortint unsigned val[1]); import "DPI-C" function void i_shortint_unsigned_2d1(input shortint unsigned val[1][1]); import "DPI-C" function void i_shortint_unsigned_3d1(input shortint_unsigned_array1_t val); import "DPI-C" function void i_int_0d(input int val); import "DPI-C" function void i_int_1d(input int val[2]); import "DPI-C" function void i_int_2d(input int val[3][2]); import "DPI-C" function void i_int_3d(input int_array_t val); import "DPI-C" function void i_int_1d1(input int val[1]); import "DPI-C" function void i_int_2d1(input int val[1][1]); import "DPI-C" function void i_int_3d1(input int_array1_t val); import "DPI-C" function void i_int_unsigned_0d(input int unsigned val); import "DPI-C" function void i_int_unsigned_1d(input int unsigned val[2]); import "DPI-C" function void i_int_unsigned_2d(input int unsigned val[3][2]); import "DPI-C" function void i_int_unsigned_3d(input int_unsigned_array_t val); import "DPI-C" function void i_int_unsigned_1d1(input int unsigned val[1]); import "DPI-C" function void i_int_unsigned_2d1(input int unsigned val[1][1]); import "DPI-C" function void i_int_unsigned_3d1(input int_unsigned_array1_t val); import "DPI-C" function void i_longint_0d(input longint val); import "DPI-C" function void i_longint_1d(input longint val[2]); import "DPI-C" function void i_longint_2d(input longint val[3][2]); import "DPI-C" function void i_longint_3d(input longint_array_t val); import "DPI-C" function void i_longint_1d1(input longint val[1]); import "DPI-C" function void i_longint_2d1(input longint val[1][1]); import "DPI-C" function void i_longint_3d1(input longint_array1_t val); import "DPI-C" function void i_longint_unsigned_0d(input longint unsigned val); import "DPI-C" function void i_longint_unsigned_1d(input longint unsigned val[2]); import "DPI-C" function void i_longint_unsigned_2d(input longint unsigned val[3][2]); import "DPI-C" function void i_longint_unsigned_3d(input longint_unsigned_array_t val); import "DPI-C" function void i_longint_unsigned_1d1(input longint unsigned val[1]); import "DPI-C" function void i_longint_unsigned_2d1(input longint unsigned val[1][1]); import "DPI-C" function void i_longint_unsigned_3d1(input longint_unsigned_array1_t val); `ifndef NO_TIME import "DPI-C" function void i_time_0d(input time val); import "DPI-C" function void i_time_1d(input time val[2]); import "DPI-C" function void i_time_2d(input time val[3][2]); import "DPI-C" function void i_time_3d(input time_array_t val); import "DPI-C" function void i_time_1d1(input time val[1]); import "DPI-C" function void i_time_2d1(input time val[1][1]); import "DPI-C" function void i_time_3d1(input time_array1_t val); `endif `ifndef NO_INTEGER import "DPI-C" function void i_integer_0d(input integer val); import "DPI-C" function void i_integer_1d(input integer val[2]); import "DPI-C" function void i_integer_2d(input integer val[3][2]); import "DPI-C" function void i_integer_3d(input integer_array_t val); import "DPI-C" function void i_integer_1d1(input integer val[1]); import "DPI-C" function void i_integer_2d1(input integer val[1][1]); import "DPI-C" function void i_integer_3d1(input integer_array1_t val); `endif import "DPI-C" function void i_real_0d(input real val); import "DPI-C" function void i_real_1d(input real val[2]); import "DPI-C" function void i_real_2d(input real val[3][2]); import "DPI-C" function void i_real_3d(input real_array_t val); import "DPI-C" function void i_real_1d1(input real val[1]); import "DPI-C" function void i_real_2d1(input real val[1][1]); import "DPI-C" function void i_real_3d1(input real_array1_t val); `ifndef NO_SHORTREAL import "DPI-C" function void i_shortreal_0d(input shortreal val); import "DPI-C" function void i_shortreal_1d(input shortreal val[2]); import "DPI-C" function void i_shortreal_2d(input shortreal val[3][2]); import "DPI-C" function void i_shortreal_3d(input shortreal_array_t val); import "DPI-C" function void i_shortreal_1d1(input shortreal val[1]); import "DPI-C" function void i_shortreal_2d1(input shortreal val[1][1]); import "DPI-C" function void i_shortreal_3d1(input shortreal_array1_t val); `endif import "DPI-C" function void i_chandle_0d(input chandle val); import "DPI-C" function void i_chandle_1d(input chandle val[2]); import "DPI-C" function void i_chandle_2d(input chandle val[3][2]); import "DPI-C" function void i_chandle_3d(input chandle_array_t val); import "DPI-C" function void i_chandle_1d1(input chandle val[1]); import "DPI-C" function void i_chandle_2d1(input chandle val[1][1]); import "DPI-C" function void i_chandle_3d1(input chandle_array1_t val); import "DPI-C" function void i_string_0d(input string val); import "DPI-C" function void i_string_1d(input string val[2]); import "DPI-C" function void i_string_2d(input string val[3][2]); import "DPI-C" function void i_string_3d(input string_array_t val); import "DPI-C" function void i_string_1d1(input string val[1]); import "DPI-C" function void i_string_2d1(input string val[1][1]); import "DPI-C" function void i_string_3d1(input string_array1_t val); import "DPI-C" function void i_bit1_0d(input bit val); import "DPI-C" function void i_bit1_1d(input bit val[2]); import "DPI-C" function void i_bit1_2d(input bit val[3][2]); import "DPI-C" function void i_bit1_3d(input bit1_array_t val); import "DPI-C" function void i_bit1_1d1(input bit val[1]); import "DPI-C" function void i_bit1_2d1(input bit val[1][1]); import "DPI-C" function void i_bit1_3d1(input bit1_array1_t val); import "DPI-C" function void i_bit7_0d(input bit[6:0] val); import "DPI-C" function void i_bit7_1d(input bit[6:0] val[2]); import "DPI-C" function void i_bit7_2d(input bit[6:0] val[3][2]); import "DPI-C" function void i_bit7_3d(input bit7_array_t val); import "DPI-C" function void i_bit7_1d1(input bit[6:0] val[1]); import "DPI-C" function void i_bit7_2d1(input bit[6:0] val[1][1]); import "DPI-C" function void i_bit7_3d1(input bit7_array1_t val); import "DPI-C" function void i_bit121_0d(input bit[120:0] val); import "DPI-C" function void i_bit121_1d(input bit[120:0] val[2]); import "DPI-C" function void i_bit121_2d(input bit[120:0] val[3][2]); import "DPI-C" function void i_bit121_3d(input bit121_array_t val); import "DPI-C" function void i_bit121_1d1(input bit[120:0] val[1]); import "DPI-C" function void i_bit121_2d1(input bit[120:0] val[1][1]); import "DPI-C" function void i_bit121_3d1(input bit121_array1_t val); import "DPI-C" function void i_logic1_0d(input logic val); import "DPI-C" function void i_logic1_1d(input logic val[2]); import "DPI-C" function void i_logic1_2d(input logic val[3][2]); import "DPI-C" function void i_logic1_3d(input logic1_array_t val); import "DPI-C" function void i_logic1_1d1(input logic val[1]); import "DPI-C" function void i_logic1_2d1(input logic val[1][1]); import "DPI-C" function void i_logic1_3d1(input logic1_array1_t val); import "DPI-C" function void i_logic7_0d(input logic[6:0] val); import "DPI-C" function void i_logic7_1d(input logic[6:0] val[2]); import "DPI-C" function void i_logic7_2d(input logic[6:0] val[3][2]); import "DPI-C" function void i_logic7_3d(input logic7_array_t val); import "DPI-C" function void i_logic7_1d1(input logic[6:0] val[1]); import "DPI-C" function void i_logic7_2d1(input logic[6:0] val[1][1]); import "DPI-C" function void i_logic7_3d1(input logic7_array1_t val); import "DPI-C" function void i_logic121_0d(input logic[120:0] val); import "DPI-C" function void i_logic121_1d(input logic[120:0] val[2]); import "DPI-C" function void i_logic121_2d(input logic[120:0] val[3][2]); import "DPI-C" function void i_logic121_3d(input logic121_array_t val); import "DPI-C" function void i_logic121_1d1(input logic[120:0] val[1]); import "DPI-C" function void i_logic121_2d1(input logic[120:0] val[1][1]); import "DPI-C" function void i_logic121_3d1(input logic121_array1_t val); import "DPI-C" function void i_pack_struct_0d(input pack_struct_t val); import "DPI-C" function void i_pack_struct_1d(input pack_struct_t val[2]); import "DPI-C" function void i_pack_struct_2d(input pack_struct_t val[3][2]); import "DPI-C" function void i_pack_struct_3d(input pack_struct_array_t val); import "DPI-C" function void i_pack_struct_1d1(input pack_struct_t val[1]); import "DPI-C" function void i_pack_struct_2d1(input pack_struct_t val[1][1]); import "DPI-C" function void i_pack_struct_3d1(input pack_struct_array1_t val); `ifndef NO_UNPACK_STRUCT import "DPI-C" function void i_unpack_struct_0d(input unpack_struct_t val); import "DPI-C" function void i_unpack_struct_1d(input unpack_struct_t val[2]); import "DPI-C" function void i_unpack_struct_2d(input unpack_struct_t val[3][2]); import "DPI-C" function void i_unpack_struct_3d(input unpack_struct_array_t val); import "DPI-C" function void i_unpack_struct_1d1(input unpack_struct_t val[1]); import "DPI-C" function void i_unpack_struct_2d1(input unpack_struct_t val[1][1]); import "DPI-C" function void i_unpack_struct_3d1(input unpack_struct_array1_t val); `endif //====================================================================== // Exports //====================================================================== export "DPI-C" function e_byte_0d; export "DPI-C" function e_byte_1d; export "DPI-C" function e_byte_2d; export "DPI-C" function e_byte_3d; export "DPI-C" function e_byte_1d1; export "DPI-C" function e_byte_2d1; export "DPI-C" function e_byte_3d1; export "DPI-C" function e_byte_unsigned_0d; export "DPI-C" function e_byte_unsigned_1d; export "DPI-C" function e_byte_unsigned_2d; export "DPI-C" function e_byte_unsigned_3d; export "DPI-C" function e_byte_unsigned_1d1; export "DPI-C" function e_byte_unsigned_2d1; export "DPI-C" function e_byte_unsigned_3d1; export "DPI-C" function e_shortint_0d; export "DPI-C" function e_shortint_1d; export "DPI-C" function e_shortint_2d; export "DPI-C" function e_shortint_3d; export "DPI-C" function e_shortint_1d1; export "DPI-C" function e_shortint_2d1; export "DPI-C" function e_shortint_3d1; export "DPI-C" function e_shortint_unsigned_0d; export "DPI-C" function e_shortint_unsigned_1d; export "DPI-C" function e_shortint_unsigned_2d; export "DPI-C" function e_shortint_unsigned_3d; export "DPI-C" function e_shortint_unsigned_1d1; export "DPI-C" function e_shortint_unsigned_2d1; export "DPI-C" function e_shortint_unsigned_3d1; export "DPI-C" function e_int_0d; export "DPI-C" function e_int_1d; export "DPI-C" function e_int_2d; export "DPI-C" function e_int_3d; export "DPI-C" function e_int_1d1; export "DPI-C" function e_int_2d1; export "DPI-C" function e_int_3d1; export "DPI-C" function e_int_unsigned_0d; export "DPI-C" function e_int_unsigned_1d; export "DPI-C" function e_int_unsigned_2d; export "DPI-C" function e_int_unsigned_3d; export "DPI-C" function e_int_unsigned_1d1; export "DPI-C" function e_int_unsigned_2d1; export "DPI-C" function e_int_unsigned_3d1; export "DPI-C" function e_longint_0d; export "DPI-C" function e_longint_1d; export "DPI-C" function e_longint_2d; export "DPI-C" function e_longint_3d; export "DPI-C" function e_longint_1d1; export "DPI-C" function e_longint_2d1; export "DPI-C" function e_longint_3d1; export "DPI-C" function e_longint_unsigned_0d; export "DPI-C" function e_longint_unsigned_1d; export "DPI-C" function e_longint_unsigned_2d; export "DPI-C" function e_longint_unsigned_3d; export "DPI-C" function e_longint_unsigned_1d1; export "DPI-C" function e_longint_unsigned_2d1; export "DPI-C" function e_longint_unsigned_3d1; `ifndef NO_TIME export "DPI-C" function e_time_0d; export "DPI-C" function e_time_1d; export "DPI-C" function e_time_2d; export "DPI-C" function e_time_3d; export "DPI-C" function e_time_1d1; export "DPI-C" function e_time_2d1; export "DPI-C" function e_time_3d1; `endif `ifndef NO_INTEGER export "DPI-C" function e_integer_0d; export "DPI-C" function e_integer_1d; export "DPI-C" function e_integer_2d; export "DPI-C" function e_integer_3d; export "DPI-C" function e_integer_1d1; export "DPI-C" function e_integer_2d1; export "DPI-C" function e_integer_3d1; `endif export "DPI-C" function e_real_0d; export "DPI-C" function e_real_1d; export "DPI-C" function e_real_2d; export "DPI-C" function e_real_3d; export "DPI-C" function e_real_1d1; export "DPI-C" function e_real_2d1; export "DPI-C" function e_real_3d1; `ifndef NO_SHORTREAL export "DPI-C" function e_shortreal_0d; export "DPI-C" function e_shortreal_1d; export "DPI-C" function e_shortreal_2d; export "DPI-C" function e_shortreal_3d; export "DPI-C" function e_shortreal_1d1; export "DPI-C" function e_shortreal_2d1; export "DPI-C" function e_shortreal_3d1; `endif export "DPI-C" function e_chandle_0d; export "DPI-C" function e_chandle_1d; export "DPI-C" function e_chandle_2d; export "DPI-C" function e_chandle_3d; export "DPI-C" function e_chandle_1d1; export "DPI-C" function e_chandle_2d1; export "DPI-C" function e_chandle_3d1; export "DPI-C" function e_string_0d; export "DPI-C" function e_string_1d; export "DPI-C" function e_string_2d; export "DPI-C" function e_string_3d; export "DPI-C" function e_string_1d1; export "DPI-C" function e_string_2d1; export "DPI-C" function e_string_3d1; export "DPI-C" function e_bit1_0d; export "DPI-C" function e_bit1_1d; export "DPI-C" function e_bit1_2d; export "DPI-C" function e_bit1_3d; export "DPI-C" function e_bit1_1d1; export "DPI-C" function e_bit1_2d1; export "DPI-C" function e_bit1_3d1; export "DPI-C" function e_bit7_0d; export "DPI-C" function e_bit7_1d; export "DPI-C" function e_bit7_2d; export "DPI-C" function e_bit7_3d; export "DPI-C" function e_bit7_1d1; export "DPI-C" function e_bit7_2d1; export "DPI-C" function e_bit7_3d1; export "DPI-C" function e_bit121_0d; export "DPI-C" function e_bit121_1d; export "DPI-C" function e_bit121_2d; export "DPI-C" function e_bit121_3d; export "DPI-C" function e_bit121_1d1; export "DPI-C" function e_bit121_2d1; export "DPI-C" function e_bit121_3d1; export "DPI-C" function e_logic1_0d; export "DPI-C" function e_logic1_1d; export "DPI-C" function e_logic1_2d; export "DPI-C" function e_logic1_3d; export "DPI-C" function e_logic1_1d1; export "DPI-C" function e_logic1_2d1; export "DPI-C" function e_logic1_3d1; export "DPI-C" function e_logic7_0d; export "DPI-C" function e_logic7_1d; export "DPI-C" function e_logic7_2d; export "DPI-C" function e_logic7_3d; export "DPI-C" function e_logic7_1d1; export "DPI-C" function e_logic7_2d1; export "DPI-C" function e_logic7_3d1; export "DPI-C" function e_logic121_0d; export "DPI-C" function e_logic121_1d; export "DPI-C" function e_logic121_2d; export "DPI-C" function e_logic121_3d; export "DPI-C" function e_logic121_1d1; export "DPI-C" function e_logic121_2d1; export "DPI-C" function e_logic121_3d1; export "DPI-C" function e_pack_struct_0d; export "DPI-C" function e_pack_struct_1d; export "DPI-C" function e_pack_struct_2d; export "DPI-C" function e_pack_struct_3d; export "DPI-C" function e_pack_struct_1d1; export "DPI-C" function e_pack_struct_2d1; export "DPI-C" function e_pack_struct_3d1; `ifndef NO_UNPACK_STRUCT export "DPI-C" function e_unpack_struct_0d; export "DPI-C" function e_unpack_struct_1d; export "DPI-C" function e_unpack_struct_2d; export "DPI-C" function e_unpack_struct_3d; export "DPI-C" function e_unpack_struct_1d1; export "DPI-C" function e_unpack_struct_2d1; export "DPI-C" function e_unpack_struct_3d1; `endif //====================================================================== // Definitions of exported functions //====================================================================== function void e_byte_0d(input byte val); `CHECK_0D(val); endfunction function void e_byte_1d(input byte val[2]); `CHECK_1D(val); endfunction function void e_byte_2d(input byte val[3][2]); `CHECK_2D(val); endfunction function void e_byte_3d(input byte_array_t val); `CHECK_3D(val); endfunction function void e_byte_1d1(input byte val[1]); `CHECK_1D1(val); endfunction function void e_byte_2d1(input byte val[1][1]); `CHECK_2D1(val); endfunction function void e_byte_3d1(input byte_array1_t val); `CHECK_3D1(val); endfunction function void e_byte_unsigned_0d(input byte unsigned val); `CHECK_0D(val); endfunction function void e_byte_unsigned_1d(input byte unsigned val[2]); `CHECK_1D(val); endfunction function void e_byte_unsigned_2d(input byte unsigned val[3][2]); `CHECK_2D(val); endfunction function void e_byte_unsigned_3d(input byte_unsigned_array_t val); `CHECK_3D(val); endfunction function void e_byte_unsigned_1d1(input byte unsigned val[1]); `CHECK_1D1(val); endfunction function void e_byte_unsigned_2d1(input byte unsigned val[1][1]); `CHECK_2D1(val); endfunction function void e_byte_unsigned_3d1(input byte_unsigned_array1_t val); `CHECK_3D1(val); endfunction function void e_shortint_0d(input shortint val); `CHECK_0D(val); endfunction function void e_shortint_1d(input shortint val[2]); `CHECK_1D(val); endfunction function void e_shortint_2d(input shortint val[3][2]); `CHECK_2D(val); endfunction function void e_shortint_3d(input shortint_array_t val); `CHECK_3D(val); endfunction function void e_shortint_1d1(input shortint val[1]); `CHECK_1D1(val); endfunction function void e_shortint_2d1(input shortint val[1][1]); `CHECK_2D1(val); endfunction function void e_shortint_3d1(input shortint_array1_t val); `CHECK_3D1(val); endfunction function void e_shortint_unsigned_0d(input shortint unsigned val); `CHECK_0D(val); endfunction function void e_shortint_unsigned_1d(input shortint unsigned val[2]); `CHECK_1D(val); endfunction function void e_shortint_unsigned_2d(input shortint unsigned val[3][2]); `CHECK_2D(val); endfunction function void e_shortint_unsigned_3d(input shortint_unsigned_array_t val); `CHECK_3D(val); endfunction function void e_shortint_unsigned_1d1(input shortint unsigned val[1]); `CHECK_1D1(val); endfunction function void e_shortint_unsigned_2d1(input shortint unsigned val[1][1]); `CHECK_2D1(val); endfunction function void e_shortint_unsigned_3d1(input shortint_unsigned_array1_t val); `CHECK_3D1(val); endfunction function void e_int_0d(input int val); `CHECK_0D(val); endfunction function void e_int_1d(input int val[2]); `CHECK_1D(val); endfunction function void e_int_2d(input int val[3][2]); `CHECK_2D(val); endfunction function void e_int_3d(input int_array_t val); `CHECK_3D(val); endfunction function void e_int_1d1(input int val[1]); `CHECK_1D1(val); endfunction function void e_int_2d1(input int val[1][1]); `CHECK_2D1(val); endfunction function void e_int_3d1(input int_array1_t val); `CHECK_3D1(val); endfunction function void e_int_unsigned_0d(input int unsigned val); `CHECK_0D(val); endfunction function void e_int_unsigned_1d(input int unsigned val[2]); `CHECK_1D(val); endfunction function void e_int_unsigned_2d(input int unsigned val[3][2]); `CHECK_2D(val); endfunction function void e_int_unsigned_3d(input int_unsigned_array_t val); `CHECK_3D(val); endfunction function void e_int_unsigned_1d1(input int unsigned val[1]); `CHECK_1D1(val); endfunction function void e_int_unsigned_2d1(input int unsigned val[1][1]); `CHECK_2D1(val); endfunction function void e_int_unsigned_3d1(input int_unsigned_array1_t val); `CHECK_3D1(val); endfunction function void e_longint_0d(input longint val); `CHECK_0D(val); endfunction function void e_longint_1d(input longint val[2]); `CHECK_1D(val); endfunction function void e_longint_2d(input longint val[3][2]); `CHECK_2D(val); endfunction function void e_longint_3d(input longint_array_t val); `CHECK_3D(val); endfunction function void e_longint_1d1(input longint val[1]); `CHECK_1D1(val); endfunction function void e_longint_2d1(input longint val[1][1]); `CHECK_2D1(val); endfunction function void e_longint_3d1(input longint_array1_t val); `CHECK_3D1(val); endfunction function void e_longint_unsigned_0d(input longint unsigned val); `CHECK_0D(val); endfunction function void e_longint_unsigned_1d(input longint unsigned val[2]); `CHECK_1D(val); endfunction function void e_longint_unsigned_2d(input longint unsigned val[3][2]); `CHECK_2D(val); endfunction function void e_longint_unsigned_3d(input longint_unsigned_array_t val); `CHECK_3D(val); endfunction function void e_longint_unsigned_1d1(input longint unsigned val[1]); `CHECK_1D1(val); endfunction function void e_longint_unsigned_2d1(input longint unsigned val[1][1]); `CHECK_2D1(val); endfunction function void e_longint_unsigned_3d1(input longint_unsigned_array1_t val); `CHECK_3D1(val); endfunction `ifndef NO_TIME function void e_time_0d(input time val); `CHECK_0D(val); endfunction function void e_time_1d(input time val[2]); `CHECK_1D(val); endfunction function void e_time_2d(input time val[3][2]); `CHECK_2D(val); endfunction function void e_time_3d(input time_array_t val); `CHECK_3D(val); endfunction function void e_time_1d1(input time val[1]); `CHECK_1D1(val); endfunction function void e_time_2d1(input time val[1][1]); `CHECK_2D1(val); endfunction function void e_time_3d1(input time_array1_t val); `CHECK_3D1(val); endfunction `endif `ifndef NO_INTEGER function void e_integer_0d(input integer val); `CHECK_0D(val); endfunction function void e_integer_1d(input integer val[2]); `CHECK_1D(val); endfunction function void e_integer_2d(input integer val[3][2]); `CHECK_2D(val); endfunction function void e_integer_3d(input integer_array_t val); `CHECK_3D(val); endfunction function void e_integer_1d1(input integer val[1]); `CHECK_1D1(val); endfunction function void e_integer_2d1(input integer val[1][1]); `CHECK_2D1(val); endfunction function void e_integer_3d1(input integer_array1_t val); `CHECK_3D1(val); endfunction `endif function void e_real_0d(input real val); `CHECK_0D(val); endfunction function void e_real_1d(input real val[2]); `CHECK_1D(val); endfunction function void e_real_2d(input real val[3][2]); `CHECK_2D(val); endfunction function void e_real_3d(input real_array_t val); `CHECK_3D(val); endfunction function void e_real_1d1(input real val[1]); `CHECK_1D1(val); endfunction function void e_real_2d1(input real val[1][1]); `CHECK_2D1(val); endfunction function void e_real_3d1(input real_array1_t val); `CHECK_3D1(val); endfunction `ifndef NO_SHORTREAL function void e_shortreal_0d(input shortreal val); `CHECK_0D(val); endfunction function void e_shortreal_1d(input shortreal val[2]); `CHECK_1D(val); endfunction function void e_shortreal_2d(input shortreal val[3][2]); `CHECK_2D(val); endfunction function void e_shortreal_3d(input shortreal_array_t val); `CHECK_3D(val); endfunction function void e_shortreal_1d1(input shortreal val[1]); `CHECK_1D1(val); endfunction function void e_shortreal_2d1(input shortreal val[1][1]); `CHECK_2D1(val); endfunction function void e_shortreal_3d1(input shortreal_array1_t val); `CHECK_3D1(val); endfunction `endif function void e_chandle_0d(input chandle val); if (val == null) begin $display("Mismatch non null is expected, but not."); $stop; end endfunction function void e_chandle_1d(input chandle val[2]); if (val[0] == null) begin $display("Mismatch non null is expected, but not."); $stop; end if (val[1] == null) begin $display("Mismatch non null is expected, but not."); $stop; end endfunction function void e_chandle_2d(input chandle val[3][2]); if (val[0][1] == null) begin $display("Mismatch non null is expected, but not."); $stop; end if (val[1][1] == null) begin $display("Mismatch non null is expected, but not."); $stop; end if (val[2][1] == null) begin $display("Mismatch non null is expected, but not."); $stop; end endfunction function void e_chandle_3d(input chandle_array_t val); if (val[0][0][0] == null) begin $display("Mismatch non null is expected, but not."); $stop; end if (val[1][0][0] == null) begin $display("Mismatch non null is expected, but not."); $stop; end if (val[2][0][0] == null) begin $display("Mismatch non null is expected, but not."); $stop; end if (val[3][0][0] == null) begin $display("Mismatch non null is expected, but not."); $stop; end endfunction function void e_chandle_1d1(input chandle val[1]); if (val[0] == null) begin $display("Mismatch non null is expected, but not."); $stop; end endfunction function void e_chandle_2d1(input chandle val[1][1]); if (val[0][0] == null) begin $display("Mismatch non null is expected, but not."); $stop; end endfunction function void e_chandle_3d1(input chandle_array1_t val); if (val[0][0][0] == null) begin $display("Mismatch non null is expected, but not."); $stop; end endfunction function void e_string_0d(input string val); if (val != "42") begin $display("Mismatch expected:%s actual:%s", "42", val); $stop; end endfunction function void e_string_1d(input string val[2]); if (val[0] != "43") begin $display("Mismatch expected:%s actual:%s", "43", val[0]); $stop; end if (val[1] != "44") begin $display("Mismatch expected:%s actual:%s", "44", val[1]); $stop; end endfunction function void e_string_2d(input string val[3][2]); if (val[0][1] != "45") begin $display("Mismatch expected:%s actual:%s", "45", val[0][1]); $stop; end if (val[1][1] != "46") begin $display("Mismatch expected:%s actual:%s", "46", val[1][1]); $stop; end if (val[2][1] != "47") begin $display("Mismatch expected:%s actual:%s", "47", val[2][1]); $stop; end endfunction function void e_string_3d(input string_array_t val); if (val[0][0][0] != "48") begin $display("Mismatch expected:%s actual:%s", "48", val[0][0][0]); $stop; end if (val[1][0][0] != "49") begin $display("Mismatch expected:%s actual:%s", "49", val[1][0][0]); $stop; end if (val[2][0][0] != "50") begin $display("Mismatch expected:%s actual:%s", "50", val[2][0][0]); $stop; end if (val[3][0][0] != "51") begin $display("Mismatch expected:%s actual:%s", "51", val[3][0][0]); $stop; end endfunction function void e_string_1d1(input string val[1]); if (val[0] != "52") begin $display("Mismatch expected:%s actual:%s", "52", val[0]); $stop; end endfunction function void e_string_2d1(input string val[1][1]); if (val[0][0] != "53") begin $display("Mismatch expected:%s actual:%s", "53", val[0][0]); $stop; end endfunction function void e_string_3d1(input string_array1_t val); if (val[0][0][0] != "54") begin $display("Mismatch expected:%s actual:%s", "54", val[0][0][0]); $stop; end endfunction function void e_bit1_0d(input bit val); `CHECK_0D(val); endfunction function void e_bit1_1d(input bit val[2]); `CHECK_1D(val); endfunction function void e_bit1_2d(input bit val[3][2]); `CHECK_2D(val); endfunction function void e_bit1_3d(input bit1_array_t val); `CHECK_3D(val); endfunction function void e_bit1_1d1(input bit val[1]); `CHECK_1D1(val); endfunction function void e_bit1_2d1(input bit val[1][1]); `CHECK_2D1(val); endfunction function void e_bit1_3d1(input bit1_array1_t val); `CHECK_3D1(val); endfunction function void e_bit7_0d(input bit[6:0] val); `CHECK_0D(val); endfunction function void e_bit7_1d(input bit[6:0] val[2]); `CHECK_1D(val); endfunction function void e_bit7_2d(input bit[6:0] val[3][2]); `CHECK_2D(val); endfunction function void e_bit7_3d(input bit7_array_t val); `CHECK_3D(val); endfunction function void e_bit7_1d1(input bit[6:0] val[1]); `CHECK_1D1(val); endfunction function void e_bit7_2d1(input bit[6:0] val[1][1]); `CHECK_2D1(val); endfunction function void e_bit7_3d1(input bit7_array1_t val); `CHECK_3D1(val); endfunction function void e_bit121_0d(input bit[120:0] val); `CHECK_0D(val); endfunction function void e_bit121_1d(input bit[120:0] val[2]); `CHECK_1D(val); endfunction function void e_bit121_2d(input bit[120:0] val[3][2]); `CHECK_2D(val); endfunction function void e_bit121_3d(input bit121_array_t val); `CHECK_3D(val); endfunction function void e_bit121_1d1(input bit[120:0] val[1]); `CHECK_1D1(val); endfunction function void e_bit121_2d1(input bit[120:0] val[1][1]); `CHECK_2D1(val); endfunction function void e_bit121_3d1(input bit121_array1_t val); `CHECK_3D1(val); endfunction function void e_logic1_0d(input logic val); `CHECK_0D(val); endfunction function void e_logic1_1d(input logic val[2]); `CHECK_1D(val); endfunction function void e_logic1_2d(input logic val[3][2]); `CHECK_2D(val); endfunction function void e_logic1_3d(input logic1_array_t val); `CHECK_3D(val); endfunction function void e_logic1_1d1(input logic val[1]); `CHECK_1D1(val); endfunction function void e_logic1_2d1(input logic val[1][1]); `CHECK_2D1(val); endfunction function void e_logic1_3d1(input logic1_array1_t val); `CHECK_3D1(val); endfunction function void e_logic7_0d(input logic[6:0] val); `CHECK_0D(val); endfunction function void e_logic7_1d(input logic[6:0] val[2]); `CHECK_1D(val); endfunction function void e_logic7_2d(input logic[6:0] val[3][2]); `CHECK_2D(val); endfunction function void e_logic7_3d(input logic7_array_t val); `CHECK_3D(val); endfunction function void e_logic7_1d1(input logic[6:0] val[1]); `CHECK_1D1(val); endfunction function void e_logic7_2d1(input logic[6:0] val[1][1]); `CHECK_2D1(val); endfunction function void e_logic7_3d1(input logic7_array1_t val); `CHECK_3D1(val); endfunction function void e_logic121_0d(input logic[120:0] val); `CHECK_0D(val); endfunction function void e_logic121_1d(input logic[120:0] val[2]); `CHECK_1D(val); endfunction function void e_logic121_2d(input logic[120:0] val[3][2]); `CHECK_2D(val); endfunction function void e_logic121_3d(input logic121_array_t val); `CHECK_3D(val); endfunction function void e_logic121_1d1(input logic[120:0] val[1]); `CHECK_1D1(val); endfunction function void e_logic121_2d1(input logic[120:0] val[1][1]); `CHECK_2D1(val); endfunction function void e_logic121_3d1(input logic121_array1_t val); `CHECK_3D1(val); endfunction function void e_pack_struct_0d(input pack_struct_t val); `CHECK_0D(val); endfunction function void e_pack_struct_1d(input pack_struct_t val[2]); `CHECK_1D(val); endfunction function void e_pack_struct_2d(input pack_struct_t val[3][2]); `CHECK_2D(val); endfunction function void e_pack_struct_3d(input pack_struct_array_t val); `CHECK_3D(val); endfunction function void e_pack_struct_1d1(input pack_struct_t val[1]); `CHECK_1D1(val); endfunction function void e_pack_struct_2d1(input pack_struct_t val[1][1]); `CHECK_2D1(val); endfunction function void e_pack_struct_3d1(input pack_struct_array1_t val); `CHECK_3D1(val); endfunction `ifndef NO_UNPACK_STRUCT function void e_unpack_struct_0d(input unpack_struct_t val); if (val.val != 42) begin $display("Mismatch expected:%s actual:%s", "42", val.val); $stop; end endfunction function void e_unpack_struct_1d(input unpack_struct_t val[2]); if (val[0].val != 43) begin $display("Mismatch expected:%s actual:%s", "43", val[0].val); $stop; end if (val[1].val != 44) begin $display("Mismatch expected:%s actual:%s", "44", val[1].val); $stop; end endfunction function void e_unpack_struct_2d(input unpack_struct_t val[3][2]); if (val[0][1].val != 45) begin $display("Mismatch expected:%s actual:%s", "45", val[0][1].val); $stop; end if (val[1][1].val != 46) begin $display("Mismatch expected:%s actual:%s", "46", val[1][1].val); $stop; end if (val[2][1].val != 47) begin $display("Mismatch expected:%s actual:%s", "47", val[2][1].val); $stop; end endfunction function void e_unpack_struct_3d(input unpack_struct_array_t val); if (val[0][0][0].val != 48) begin $display("Mismatch expected:%s actual:%s", "48", val[0][0][0].val); $stop; end if (val[1][0][0].val != 49) begin $display("Mismatch expected:%s actual:%s", "49", val[1][0][0].val); $stop; end if (val[2][0][0].val != 50) begin $display("Mismatch expected:%s actual:%s", "50", val[2][0][0].val); $stop; end if (val[3][0][0].val != 51) begin $display("Mismatch expected:%s actual:%s", "51", val[3][0][0].val); $stop; end endfunction function void e_unpack_struct_1d1(input unpack_struct_t val[1]); if (val[0].val != 52) begin $display("Mismatch expected:%s actual:%s", "52", val[0].val); $stop; end endfunction function void e_unpack_struct_2d1(input unpack_struct_t val[1][1]); if (val[0][0].val != 53) begin $display("Mismatch expected:%s actual:%s", "53", val[0][0].val); $stop; end endfunction function void e_unpack_struct_3d1(input unpack_struct_array1_t val); if (val[0][0][0].val != 54) begin $display("Mismatch expected:%s actual:%s", "54", val[0][0][0].val); $stop; end endfunction `endif //====================================================================== // Invoke all imported functions //====================================================================== import "DPI-C" context function void check_exports(); initial begin byte_array_t byte_array; byte_array1_t byte_array1; byte_unsigned_array_t byte_unsigned_array; byte_unsigned_array1_t byte_unsigned_array1; shortint_array_t shortint_array; shortint_array1_t shortint_array1; shortint_unsigned_array_t shortint_unsigned_array; shortint_unsigned_array1_t shortint_unsigned_array1; int_array_t int_array; int_array1_t int_array1; int_unsigned_array_t int_unsigned_array; int_unsigned_array1_t int_unsigned_array1; longint_array_t longint_array; longint_array1_t longint_array1; longint_unsigned_array_t longint_unsigned_array; longint_unsigned_array1_t longint_unsigned_array1; `ifndef NO_TIME time_array_t time_array; time_array1_t time_array1; `endif `ifndef NO_INTEGER integer_array_t integer_array; integer_array1_t integer_array1; `endif real_array_t real_array; real_array1_t real_array1; `ifndef NO_SHORTREAL shortreal_array_t shortreal_array; shortreal_array1_t shortreal_array1; `endif chandle_array_t chandle_array; chandle_array1_t chandle_array1; string_array_t string_array; string_array1_t string_array1; bit1_array_t bit1_array; bit1_array1_t bit1_array1; bit7_array_t bit7_array; bit7_array1_t bit7_array1; bit121_array_t bit121_array; bit121_array1_t bit121_array1; logic1_array_t logic1_array; logic1_array1_t logic1_array1; logic7_array_t logic7_array; logic7_array1_t logic7_array1; logic121_array_t logic121_array; logic121_array1_t logic121_array1; pack_struct_array_t pack_struct_array; pack_struct_array1_t pack_struct_array1; `ifndef NO_UNPACK_STRUCT unpack_struct_array_t unpack_struct_array; unpack_struct_array1_t unpack_struct_array1; `endif `SET_VALUES(byte_array); i_byte_0d(byte_array[3][2][1]); i_byte_1d(byte_array[2][1]); i_byte_2d(byte_array[1]); i_byte_3d(byte_array); byte_array1[0][0][0] = 52; i_byte_1d1(byte_array1[0][0]); byte_array1[0][0][0] = 53; i_byte_2d1(byte_array1[0]); byte_array1[0][0][0] = 54; i_byte_3d1(byte_array1); `SET_VALUES(byte_unsigned_array); i_byte_unsigned_0d(byte_unsigned_array[3][2][1]); i_byte_unsigned_1d(byte_unsigned_array[2][1]); i_byte_unsigned_2d(byte_unsigned_array[1]); i_byte_unsigned_3d(byte_unsigned_array); byte_unsigned_array1[0][0][0] = 52; i_byte_unsigned_1d1(byte_unsigned_array1[0][0]); byte_unsigned_array1[0][0][0] = 53; i_byte_unsigned_2d1(byte_unsigned_array1[0]); byte_unsigned_array1[0][0][0] = 54; i_byte_unsigned_3d1(byte_unsigned_array1); `SET_VALUES(shortint_array); i_shortint_0d(shortint_array[3][2][1]); i_shortint_1d(shortint_array[2][1]); i_shortint_2d(shortint_array[1]); i_shortint_3d(shortint_array); shortint_array1[0][0][0] = 52; i_shortint_1d1(shortint_array1[0][0]); shortint_array1[0][0][0] = 53; i_shortint_2d1(shortint_array1[0]); shortint_array1[0][0][0] = 54; i_shortint_3d1(shortint_array1); `SET_VALUES(shortint_unsigned_array); i_shortint_unsigned_0d(shortint_unsigned_array[3][2][1]); i_shortint_unsigned_1d(shortint_unsigned_array[2][1]); i_shortint_unsigned_2d(shortint_unsigned_array[1]); i_shortint_unsigned_3d(shortint_unsigned_array); shortint_unsigned_array1[0][0][0] = 52; i_shortint_unsigned_1d1(shortint_unsigned_array1[0][0]); shortint_unsigned_array1[0][0][0] = 53; i_shortint_unsigned_2d1(shortint_unsigned_array1[0]); shortint_unsigned_array1[0][0][0] = 54; i_shortint_unsigned_3d1(shortint_unsigned_array1); `SET_VALUES(int_array); i_int_0d(int_array[3][2][1]); i_int_1d(int_array[2][1]); i_int_2d(int_array[1]); i_int_3d(int_array); int_array1[0][0][0] = 52; i_int_1d1(int_array1[0][0]); int_array1[0][0][0] = 53; i_int_2d1(int_array1[0]); int_array1[0][0][0] = 54; i_int_3d1(int_array1); `SET_VALUES(int_unsigned_array); i_int_unsigned_0d(int_unsigned_array[3][2][1]); i_int_unsigned_1d(int_unsigned_array[2][1]); i_int_unsigned_2d(int_unsigned_array[1]); i_int_unsigned_3d(int_unsigned_array); int_unsigned_array1[0][0][0] = 52; i_int_unsigned_1d1(int_unsigned_array1[0][0]); int_unsigned_array1[0][0][0] = 53; i_int_unsigned_2d1(int_unsigned_array1[0]); int_unsigned_array1[0][0][0] = 54; i_int_unsigned_3d1(int_unsigned_array1); `SET_VALUES(longint_array); i_longint_0d(longint_array[3][2][1]); i_longint_1d(longint_array[2][1]); i_longint_2d(longint_array[1]); i_longint_3d(longint_array); longint_array1[0][0][0] = 52; i_longint_1d1(longint_array1[0][0]); longint_array1[0][0][0] = 53; i_longint_2d1(longint_array1[0]); longint_array1[0][0][0] = 54; i_longint_3d1(longint_array1); `SET_VALUES(longint_unsigned_array); i_longint_unsigned_0d(longint_unsigned_array[3][2][1]); i_longint_unsigned_1d(longint_unsigned_array[2][1]); i_longint_unsigned_2d(longint_unsigned_array[1]); i_longint_unsigned_3d(longint_unsigned_array); longint_unsigned_array1[0][0][0] = 52; i_longint_unsigned_1d1(longint_unsigned_array1[0][0]); longint_unsigned_array1[0][0][0] = 53; i_longint_unsigned_2d1(longint_unsigned_array1[0]); longint_unsigned_array1[0][0][0] = 54; i_longint_unsigned_3d1(longint_unsigned_array1); `ifndef NO_TIME `SET_VALUES(time_array); i_time_0d(time_array[3][2][1]); i_time_1d(time_array[2][1]); i_time_2d(time_array[1]); i_time_3d(time_array); time_array1[0][0][0] = 52; i_time_1d1(time_array1[0][0]); time_array1[0][0][0] = 53; i_time_2d1(time_array1[0]); time_array1[0][0][0] = 54; i_time_3d1(time_array1); `endif `ifndef NO_INTEGER `SET_VALUES(integer_array); i_integer_0d(integer_array[3][2][1]); i_integer_1d(integer_array[2][1]); i_integer_2d(integer_array[1]); i_integer_3d(integer_array); integer_array1[0][0][0] = 52; i_integer_1d1(integer_array1[0][0]); integer_array1[0][0][0] = 53; i_integer_2d1(integer_array1[0]); integer_array1[0][0][0] = 54; i_integer_3d1(integer_array1); `endif `SET_VALUES(real_array); i_real_0d(real_array[3][2][1]); i_real_1d(real_array[2][1]); i_real_2d(real_array[1]); i_real_3d(real_array); real_array1[0][0][0] = 52; i_real_1d1(real_array1[0][0]); real_array1[0][0][0] = 53; i_real_2d1(real_array1[0]); real_array1[0][0][0] = 54; i_real_3d1(real_array1); `ifndef NO_SHORTREAL `SET_VALUES(shortreal_array); i_shortreal_0d(shortreal_array[3][2][1]); i_shortreal_1d(shortreal_array[2][1]); i_shortreal_2d(shortreal_array[1]); i_shortreal_3d(shortreal_array); shortreal_array1[0][0][0] = 52; i_shortreal_1d1(shotreal_array1[0][0]); shortreal_array1[0][0][0] = 53; i_shortreal_2d1(shotreal_array1[0]); shortreal_array1[0][0][0] = 54; i_shortreal_3d1(shotreal_array1); `endif for (int i = 0; i < 4; ++i) for (int j = 0; j < 3; ++j) for (int k = 0; k < 2; ++k) chandle_array[i][j][k] = null; chandle_array[3][2][1] = get_non_null(); i_chandle_0d(chandle_array[3][2][1]); chandle_array[2][1][0] = get_non_null(); chandle_array[2][1][1] = get_non_null(); i_chandle_1d(chandle_array[2][1]); chandle_array[1][0][1] = get_non_null(); chandle_array[1][1][1] = get_non_null(); chandle_array[1][2][1] = get_non_null(); i_chandle_2d(chandle_array[1]); chandle_array[0][0][0] = get_non_null(); chandle_array[1][0][0] = get_non_null(); chandle_array[2][0][0] = get_non_null(); chandle_array[3][0][0] = get_non_null(); i_chandle_3d(chandle_array); chandle_array1[0][0][0] = get_non_null(); i_chandle_1d1(chandle_array1[0][0]); chandle_array1[0][0][0] = get_non_null(); i_chandle_2d1(chandle_array1[0]); chandle_array1[0][0][0] = get_non_null(); i_chandle_3d1(chandle_array1); string_array[3][2][1] = "42"; string_array[2][1][0] = "43"; string_array[2][1][1] = "44"; string_array[1][0][1] = "45"; string_array[1][1][1] = "46"; string_array[1][2][1] = "47"; string_array[0][0][0] = "48"; string_array[1][0][0] = "49"; string_array[2][0][0] = "50"; string_array[3][0][0] = "51"; i_string_0d(string_array[3][2][1]); i_string_1d(string_array[2][1]); i_string_2d(string_array[1]); i_string_3d(string_array); string_array1[0][0][0] = "52"; i_string_1d1(string_array1[0][0]); string_array1[0][0][0] = "53"; i_string_2d1(string_array1[0]); string_array1[0][0][0] = "54"; i_string_3d1(string_array1); `SET_VALUES(bit1_array); i_bit1_0d(bit1_array[3][2][1]); i_bit1_1d(bit1_array[2][1]); i_bit1_2d(bit1_array[1]); i_bit1_3d(bit1_array); bit1_array1[0][0][0] = 1'(52); i_bit1_1d1(bit1_array1[0][0]); bit1_array1[0][0][0] = 1'(53); i_bit1_2d1(bit1_array1[0]); bit1_array1[0][0][0] = 1'(54); i_bit1_3d1(bit1_array1); `SET_VALUES(bit7_array); i_bit7_0d(bit7_array[3][2][1]); i_bit7_1d(bit7_array[2][1]); i_bit7_2d(bit7_array[1]); i_bit7_3d(bit7_array); bit7_array1[0][0][0] = 52; i_bit7_1d1(bit7_array1[0][0]); bit7_array1[0][0][0] = 53; i_bit7_2d1(bit7_array1[0]); bit7_array1[0][0][0] = 54; i_bit7_3d1(bit7_array1); `SET_VALUES(bit121_array); i_bit121_0d(bit121_array[3][2][1]); i_bit121_1d(bit121_array[2][1]); i_bit121_2d(bit121_array[1]); i_bit121_3d(bit121_array); bit121_array1[0][0][0] = 52; i_bit121_1d1(bit121_array1[0][0]); bit121_array1[0][0][0] = 53; i_bit121_2d1(bit121_array1[0]); bit121_array1[0][0][0] = 54; i_bit121_3d1(bit121_array1); `SET_VALUES(logic1_array); i_logic1_0d(logic1_array[3][2][1]); i_logic1_1d(logic1_array[2][1]); i_logic1_2d(logic1_array[1]); i_logic1_3d(logic1_array); logic1_array1[0][0][0] = 1'(52); i_logic1_1d1(logic1_array1[0][0]); logic1_array1[0][0][0] = 1'(53); i_logic1_2d1(logic1_array1[0]); logic1_array1[0][0][0] = 1'(54); i_logic1_3d1(logic1_array1); `SET_VALUES(logic7_array); i_logic7_0d(logic7_array[3][2][1]); i_logic7_1d(logic7_array[2][1]); i_logic7_2d(logic7_array[1]); i_logic7_3d(logic7_array); logic7_array1[0][0][0] = 52; i_logic7_1d1(logic7_array1[0][0]); logic7_array1[0][0][0] = 53; i_logic7_2d1(logic7_array1[0]); logic7_array1[0][0][0] = 54; i_logic7_3d1(logic7_array1); `SET_VALUES(logic121_array); i_logic121_0d(logic121_array[3][2][1]); i_logic121_1d(logic121_array[2][1]); i_logic121_2d(logic121_array[1]); i_logic121_3d(logic121_array); logic121_array1[0][0][0] = 52; i_logic121_1d1(logic121_array1[0][0]); logic121_array1[0][0][0] = 53; i_logic121_2d1(logic121_array1[0]); logic121_array1[0][0][0] = 54; i_logic121_3d1(logic121_array1); `SET_VALUES(pack_struct_array); i_pack_struct_0d(pack_struct_array[3][2][1]); i_pack_struct_1d(pack_struct_array[2][1]); i_pack_struct_2d(pack_struct_array[1]); i_pack_struct_3d(pack_struct_array); pack_struct_array1[0][0][0] = 52; i_pack_struct_1d1(pack_struct_array1[0][0]); pack_struct_array1[0][0][0] = 53; i_pack_struct_2d1(pack_struct_array1[0]); pack_struct_array1[0][0][0] = 54; i_pack_struct_3d1(pack_struct_array1); `ifndef NO_UNPACK_STRUCT unpack_struct_array[3][2][1].val = 42; unpack_struct_array[2][1][0].val = 43; unpack_struct_array[2][1][1].val = 44; unpack_struct_array[1][0][1].val = 45; unpack_struct_array[1][1][1].val = 46; unpack_struct_array[1][2][1].val = 47; unpack_struct_array[0][0][0].val = 48; unpack_struct_array[1][0][0].val = 49; unpack_struct_array[2][0][0].val = 50; unpack_struct_array[3][0][0].val = 51; i_unpack_struct_0d(unpack_struct_array[3][2][1]); i_unpack_struct_1d(unpack_struct_array[2][1]); i_unpack_struct_2d(unpack_struct_array[1]); i_unpack_struct_3d(unpack_struct_array); unpack_struct_array1[0][0][0].val = 52; i_unpack_struct_1d1(unpack_struct_array1[0][0]); unpack_struct_array1[0][0][0].val = 53; i_unpack_struct_2d1(unpack_struct_array1[0]); unpack_struct_array1[0][0][0].val = 54; i_unpack_struct_3d1(unpack_struct_array1); `endif check_exports(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_process_copy_constr.v0000644000542200017500000000101015101701376023670 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Cls; int x = 1; function new(); process p = process::self(); endfunction endclass module t (/*AUTOARG*/ ); initial begin Cls c, d; c = new; c.x = 2; d = new c; if (d.x != 2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_flag_only_bad2.py0000755000542200017500000000124115101701376022626 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_flag_main.v" test.lint(verilator_flags2=[ "-Wno-DEPRECATED --build -E -Wno-fatal --dpi-hdr-only --lint-only --xml-only --json-only" ], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_strength_strong1_strong1_bad.v0000644000542200017500000000046115101701376025377 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; wire (strong1, strong1) a = 1; initial begin $stop; end endmodule verilator-5.042/test_regress/t/t_class_param_super.v0000644000542200017500000000060315101701376023302 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class base #( type T = int ); function void fbase(); endfunction endclass class ext extends base; function void fext(); super.fbase(); endfunction endclass verilator-5.042/test_regress/t/t_class_uses_this_bad.py0000755000542200017500000000076615101701376024000 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_delay_incr.py0000755000542200017500000000104115101701376022073 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--binary --no-timing -Wno-STMTDLY -Wno-ASSIGNDLY']) test.execute() test.passes() verilator-5.042/test_regress/t/t_var_escape.py0000755000542200017500000000165515101701376022105 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile( # Access is so we can dump waves v_flags2=['-trace' if test.vlt_all else ' +access+rwc']) test.execute() if test.vlt_all: test.file_grep(test.trace_filename, r'\$enddefinitions') sigre = re.escape("bra[ket]slash/dash-colon:9") test.file_grep(test.trace_filename, sigre) test.file_grep(test.trace_filename, r' other\.cyc ') test.file_grep(test.trace_filename, r' module mod\.with_dot ') test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_tri_ifbegin.py0000755000542200017500000000073515101701376022254 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() #test.execute() test.passes() verilator-5.042/test_regress/t/t_func_void_bad.out0000644000542200017500000000133615101701376022727 0ustar mahmoudyfreeshell%Warning-IGNOREDRETURN: t/t_func_void_bad.v:24:7: Ignoring return value of non-void function (IEEE 1800-2023 13.4.1) 24 | f1(); | ^~ ... For warning description see https://verilator.org/warn/IGNOREDRETURN?v=latest ... Use "/* verilator lint_off IGNOREDRETURN */" and lint_on around source to disable this message. %Warning-IGNOREDRETURN: t/t_func_void_bad.v:27:9: Ignoring return value of non-void function (IEEE 1800-2023 13.4.1) 27 | c.fi(); | ^~ %Warning-IGNOREDRETURN: t/t_func_void_bad.v:28:9: Ignoring return value of non-void function (IEEE 1800-2023 13.4.1) 28 | c.sfi(); | ^~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_timing_intra_assign.out0000644000542200017500000000232615101701376024175 0ustar mahmoudyfreeshell[0] val[0]=0 val[1]=0 val[2]=0 net[0]=0 net[1]=0 [10] val[0]=1 val[1]=0 val[2]=0 net[0]=0 net[1]=15 [14] val[0]=1 val[1]=1 val[2]=0 net[0]=0 net[1]=15 [16] val[0]=1 val[1]=1 val[2]=1 net[0]=0 net[1]=15 [20] val[0]=2 val[1]=1 val[2]=1 net[0]=1 net[1]=14 [24] val[0]=2 val[1]=2 val[2]=1 net[0]=1 net[1]=14 [25] val[0]=3 val[1]=2 val[2]=1 net[0]=1 net[1]=14 [29] val[0]=3 val[1]=3 val[2]=1 net[0]=2 net[1]=13 [30] val[0]=4 val[1]=3 val[2]=1 net[0]=2 net[1]=13 [34] val[0]=4 val[1]=4 val[2]=1 net[0]=3 net[1]=12 [35] val[0]=5 val[1]=4 val[2]=1 net[0]=3 net[1]=12 [39] val[0]=5 val[1]=5 val[2]=1 net[0]=4 net[1]=11 [40] val[0]=6 val[1]=5 val[2]=1 net[0]=4 net[1]=11 [44] val[0]=6 val[1]=6 val[2]=1 net[0]=5 net[1]=10 [46] val[0]=6 val[1]=6 val[2]=6 net[0]=5 net[1]=10 [50] val[0]=7 val[1]=6 val[2]=6 net[0]=6 net[1]=9 [54] val[0]=7 val[1]=7 val[2]=6 net[0]=6 net[1]=9 [56] val[0]=7 val[1]=7 val[2]=7 net[0]=6 net[1]=9 [75] val[0]=8 val[1]=7 val[2]=7 net[0]=7 net[1]=8 [76] val[0]=9 val[1]=7 val[2]=7 net[0]=7 net[1]=8 [78] val[0]=10 val[1]=7 val[2]=7 net[0]=7 net[1]=8 [79] val[0]=11 val[1]=7 val[2]=7 net[0]=7 net[1]=8 [80] val[0]=12 val[1]=7 val[2]=7 net[0]=7 net[1]=8 [82] val[0]=13 val[1]=7 val[2]=7 net[0]=7 net[1]=8 *-* All Finished *-* verilator-5.042/test_regress/t/t_fork_label.py0000755000542200017500000000100515101701376022062 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--binary --no-timing']) test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_derived_type.py0000755000542200017500000000073415101701376024475 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_math_wide_bad.v0000644000542200017500000000145415101701376022353 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs z, z2, z3, z4, z5, z6, r, // Inputs a, b, ua, ub ); input signed [170*32 : 0] a; input signed [170*32 : 0] b; input [170*32 : 0] ua; input [170*32 : 0] ub; output signed [170*32 : 0] z; output signed [170*32 : 0] z2; output signed [170*32 : 0] z3; output signed [170*32 : 0] z4; output [170*32 : 0] z5; output [170*32 : 0] z6; output real r; assign z = a * b; assign z2 = a ** 3; assign z3 = a / b; assign z4 = a % b; assign z5 = ua / ub; assign z6 = ua % ub; assign r = real'(a); endmodule verilator-5.042/test_regress/t/t_class_extends_param_unused.v0000644000542200017500000000055015101701376025202 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class Foo#(type T = logic) extends T; endclass module t; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_fork_initial.py0000755000542200017500000000114515101701376022441 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile( verilator_flags2=["--exe --main --timing"], # issue #4471 - remove this verilator_make_gmake=False) # issue #4471 - add this #test.execute() test.passes() verilator-5.042/test_regress/t/t_flag_only_bad3.out0000755000542200017500000000036415101701376023013 0ustar mahmoudyfreeshell%Error: The following cannot be used together: --dpi-hdr-only, --lint-only, --xml-only, --json-only. Suggest see manual ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_interface2.py0000755000542200017500000000077715101701376022023 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--top-module t"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_assert_elab.v0000644000542200017500000000134515101701376022067 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Johan Bjork. // SPDX-License-Identifier: CC0-1.0 module t; localparam STR = "string"; function logic checkParameter(input logic [8:0] N); $info("For %m, x is %d.", N); if (N == 1) return 0; $fatal(1, "Parameter %d is invalid...%s and %s", N, STR, "constant both work"); endfunction `ifdef FAILING_ASSERTIONS localparam X = checkParameter(5); `else localparam X = checkParameter(1); `endif generate $info("%m: In generate"); // Issue 6445 endgenerate initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_property_recursive_unsup.v0000644000542200017500000000134215101701376025005 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ clk ); input clk; int cyc = 0; logic val = 0; always @(posedge clk) begin cyc <= cyc + 1; val = ~val; end property check(int n); disable iff (n == 0) check(n - 1); endproperty assert property(@(posedge clk) check(1)) else begin // Assertion should pass $write("*-* Assertion failed *-*\n"); $stop; end always @(posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_sys_rand_seed.py0000755000542200017500000000073415101701376022614 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_pp_dupdef_pragma_bad.v0000644000542200017500000000133715101701376023707 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; `define DUP a `define DUP b_bad // verilator lint_off REDEFMACRO `define DUP c_nowarn // verilator lint_on REDEFMACRO `define DUP d_bad // verilator lint_save // verilator lint_off REDEFMACRO `define DUP e_nowarn // verilator lint_restore `define DUP f_bad /* verilator lint_off REDEFMACRO */ `define DUP j_nowarn /* verilator lint_on REDEFMACRO */ `define DUP k_bad /* verilator lint_save */ /* verilator lint_off REDEFMACRO */ `define DUP l_nowarn /* verilator lint_restore */ `define DUP m_bad endmodule verilator-5.042/test_regress/t/t_const_overflow_bad.v0000644000542200017500000000133615101701376023462 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; parameter [200:0] TOO_SMALL = 94'd123456789012345678901234567890; // One to many digits parameter [200:0] SMALLH = 8'habc; // One to many digits parameter [200:0] SMALLO = 6'o1234; // One to many digits parameter [200:0] SMALLB = 3'b1111; // One to many digits // We'll allow this though; no reason to be cruel parameter [200:0] OKH = 8'h000000001; // bug1380 parameter [128:0] ALSO_SMALL = 129'hdeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00d; endmodule verilator-5.042/test_regress/t/t_timing_trace.v0000644000542200017500000000166515101701376022255 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" module t; localparam CLK_PERIOD = 10; localparam CLK_HALF_PERIOD = CLK_PERIOD / 2; logic rst; logic clk; logic a; logic b; logic c; logic d; event ev; initial begin $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); $dumpvars; forever clk = #CLK_HALF_PERIOD ~clk; end always begin rst = 1; clk = 0; a = 0; c = 0; b = ~b; d = 0; fork #(10 * CLK_PERIOD) b = 0; join_none while (b) begin c = ~c; -> ev; #CLK_PERIOD; end $write("[%0t] Done\n", $time); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_runflag_errorlimit_fatal_bad.py0000755000542200017500000000112015101701376025643 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile() test.execute(all_run_flags=["+verilator+error+limit+3"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_fuzz_genintf_bad.v0000644000542200017500000000072715101701376023124 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 //bug1588 interface intf; logic a; modport source(output a); endinterface module m1 ( input logic value, intf.source b ); endmodule module t; intf ifs(); m1 m0( j.e(0), .b(ifs) ); genvar j; endmodule verilator-5.042/test_regress/t/t_flag_relinc.py0000755000542200017500000000107015101701376022231 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(v_flags2=[ "--relative-includes", "--lint-only", test.t_dir + "/t_flag_relinc_dir/chip/t_flag_relinc_sub.v" ]) test.passes() verilator-5.042/test_regress/t/t_process_finished.v0000644000542200017500000000077015101701376023133 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; process p; initial begin p = process::self(); end always @(posedge clk) begin if (p.status() != process::FINISHED) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_mem_packed_bad.py0000755000542200017500000000076615101701376022672 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_var_types.v0000644000542200017500000002231615101701376021620 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; // IEEE: integer_atom_type byte d_byte; shortint d_shortint; int d_int; longint d_longint; integer d_integer; time d_time; chandle d_chandle; // IEEE: integer_atom_type bit d_bit; logic d_logic; reg d_reg; bit [1:0] d_bit2; logic [1:0] d_logic2; reg [1:0] d_reg2; // IEEE: non_integer_type //UNSUP shortreal d_shortreal; real d_real; realtime d_realtime; // Declarations using var var byte v_b; `ifndef VCS var [2:0] v_b3; var signed [2:0] v_bs; `endif // verilator lint_off WIDTH localparam p_implicit = {96{1'b1}}; localparam [89:0] p_explicit = {96{1'b1}}; localparam byte p_byte = {96{1'b1}}; localparam shortint p_shortint = {96{1'b1}}; localparam int p_int = {96{1'b1}}; localparam longint p_longint = {96{1'b1}}; localparam integer p_integer = {96{1'b1}}; localparam reg p_reg = {96{1'b1}}; localparam bit p_bit = {96{1'b1}}; localparam logic p_logic = {96{1'b1}}; localparam reg [0:0] p_reg1 = {96{1'b1}}; localparam bit [0:0] p_bit1 = {96{1'b1}}; localparam logic [0:0] p_logic1= {96{1'b1}}; localparam reg [1:0] p_reg2 = {96{1'b1}}; localparam bit [1:0] p_bit2 = {96{1'b1}}; localparam logic [1:0] p_logic2= {96{1'b1}}; // verilator lint_on WIDTH byte v_byte[2]; shortint v_shortint[2]; int v_int[2]; longint v_longint[2]; integer v_integer[2]; time v_time[2]; chandle v_chandle[2]; bit v_bit[2]; logic v_logic[2]; reg v_reg[2]; real v_real[2]; realtime v_realtime[2]; // We do this in two steps so we can check that initialization inside functions works properly // verilator lint_off WIDTH function f_implicit; reg lv_implicit; f_implicit = lv_implicit; endfunction function [89:0] f_explicit; reg [89:0] lv_explicit; f_explicit = lv_explicit; endfunction function byte f_byte; byte lv_byte; f_byte = lv_byte; endfunction function shortint f_shortint; shortint lv_shortint; f_shortint = lv_shortint; endfunction function int f_int; int lv_int; f_int = lv_int; endfunction function longint f_longint; longint lv_longint; f_longint = lv_longint; endfunction function integer f_integer; integer lv_integer; f_integer = lv_integer; endfunction function reg f_reg; reg lv_reg; f_reg = lv_reg; endfunction function bit f_bit; bit lv_bit; f_bit = lv_bit; endfunction function logic f_logic; logic lv_logic; f_logic = lv_logic; endfunction function reg [0:0] f_reg1; reg [0:0] lv_reg1; f_reg1 = lv_reg1; endfunction function bit [0:0] f_bit1; bit [0:0] lv_bit1; f_bit1 = lv_bit1; endfunction function logic [0:0] f_logic1; logic [0:0] lv_logic1; f_logic1 = lv_logic1; endfunction function reg [1:0] f_reg2; reg [1:0] lv_reg2; f_reg2 = lv_reg2; endfunction function bit [1:0] f_bit2; bit [1:0] lv_bit2; f_bit2 = lv_bit2; endfunction function logic [1:0] f_logic2; logic [1:0] lv_logic2; f_logic2 = lv_logic2; endfunction function time f_time; time lv_time; f_time = lv_time; endfunction function chandle f_chandle; chandle lv_chandle; f_chandle = lv_chandle; endfunction // verilator lint_on WIDTH `ifdef verilator // For verilator zeroinit detection to work properly, we need to x-rand-reset to all 1s. This is the default! `define XINIT 1'b1 `define ALL_TWOSTATE 1'b1 `else `define XINIT 1'bx `define ALL_TWOSTATE 1'b0 `endif `define CHECK_ALL(name,nbits,issigned,twostate,zeroinit) \ if (zeroinit ? ((name & 1'b1)!==1'b0) : ((name & 1'b1)!==`XINIT)) \ begin $display("%%Error: Bad zero/X init for %s: %b",`"name`",name); $stop; end \ name = {96{1'b1}}; \ if (name !== {(nbits){1'b1}}) begin $display("%%Error: Bad size for %s",`"name`"); $stop; end \ if (issigned ? (name > 0) : (name < 0)) begin $display("%%Error: Bad signed for %s",`"name`"); $stop; end \ name = {96{1'bx}}; \ if (name !== {(nbits){`ALL_TWOSTATE ? `XINIT : (twostate ? 1'b0 : `XINIT)}}) \ begin $display("%%Error: Bad twostate for %s: %b",`"name`",name); $stop; end \ initial begin // verilator lint_off WIDTH // verilator lint_off UNSIGNED // name b sign twost 0init `CHECK_ALL(d_byte ,8 ,1'b1,1'b1,1'b1); `CHECK_ALL(d_shortint ,16,1'b1,1'b1,1'b1); `CHECK_ALL(d_int ,32,1'b1,1'b1,1'b1); `CHECK_ALL(d_longint ,64,1'b1,1'b1,1'b1); `CHECK_ALL(d_integer ,32,1'b1,1'b0,1'b0); `CHECK_ALL(d_time ,64,1'b0,1'b0,1'b0); `CHECK_ALL(d_bit ,1 ,1'b0,1'b1,1'b1); `CHECK_ALL(d_logic ,1 ,1'b0,1'b0,1'b0); `CHECK_ALL(d_reg ,1 ,1'b0,1'b0,1'b0); `CHECK_ALL(d_bit2 ,2 ,1'b0,1'b1,1'b1); `CHECK_ALL(d_logic2 ,2 ,1'b0,1'b0,1'b0); `CHECK_ALL(d_reg2 ,2 ,1'b0,1'b0,1'b0); // verilator lint_on WIDTH // verilator lint_on UNSIGNED // Can't CHECK_ALL(d_chandle), as many operations not legal on chandles `ifdef VERILATOR // else indeterminate if ($bits(d_chandle) !== 64) $stop; `endif `define CHECK_P(name,nbits) \ if (name !== {(nbits){1'b1}}) begin $display("%%Error: Bad size for %s",`"name`"); $stop; end \ // name b `CHECK_P(p_implicit ,96); `CHECK_P(p_implicit[0] ,1 ); `CHECK_P(p_explicit ,90); `CHECK_P(p_explicit[0] ,1 ); `CHECK_P(p_byte ,8 ); `CHECK_P(p_byte[0] ,1 ); `CHECK_P(p_shortint ,16); `CHECK_P(p_shortint[0] ,1 ); `CHECK_P(p_int ,32); `CHECK_P(p_int[0] ,1 ); `CHECK_P(p_longint ,64); `CHECK_P(p_longint[0] ,1 ); `CHECK_P(p_integer ,32); `CHECK_P(p_integer[0] ,1 ); `CHECK_P(p_bit ,1 ); `CHECK_P(p_logic ,1 ); `CHECK_P(p_reg ,1 ); `CHECK_P(p_bit1 ,1 ); `CHECK_P(p_logic1 ,1 ); `CHECK_P(p_reg1 ,1 ); `CHECK_P(p_bit1[0] ,1 ); `CHECK_P(p_logic1[0] ,1 ); `CHECK_P(p_reg1[0] ,1 ); `CHECK_P(p_bit2 ,2 ); `CHECK_P(p_logic2 ,2 ); `CHECK_P(p_reg2 ,2 ); `define CHECK_B(varname,nbits) \ if ($bits(varname) !== nbits) begin $display("%%Error: Bad size for %s",`"varname`"); $stop; end \ `CHECK_B(v_byte[1] ,8 ); `CHECK_B(v_shortint[1] ,16); `CHECK_B(v_int[1] ,32); `CHECK_B(v_longint[1] ,64); `CHECK_B(v_integer[1] ,32); `CHECK_B(v_time[1] ,64); //`CHECK_B(v_chandle[1] `CHECK_B(v_bit[1] ,1 ); `CHECK_B(v_logic[1] ,1 ); `CHECK_B(v_reg[1] ,1 ); //`CHECK_B(v_real[1] ,64); // $bits not allowed //`CHECK_B(v_realtime[1] ,64); // $bits not allowed `define CHECK_F(fname,nbits,zeroinit) \ if ($bits(fname()) !== nbits) begin $display("%%Error: Bad size for %s",`"fname`"); $stop; end \ // name b 0init `CHECK_F(f_implicit ,1 ,1'b0); // Note 1 bit, not 96 `CHECK_F(f_explicit ,90,1'b0); `CHECK_F(f_byte ,8 ,1'b1); `CHECK_F(f_shortint ,16,1'b1); `CHECK_F(f_int ,32,1'b1); `CHECK_F(f_longint ,64,1'b1); `CHECK_F(f_integer ,32,1'b0); `CHECK_F(f_time ,64,1'b0); `ifdef VERILATOR // else indeterminate `CHECK_F(f_chandle ,64,1'b0); `endif `CHECK_F(f_bit ,1 ,1'b1); `CHECK_F(f_logic ,1 ,1'b0); `CHECK_F(f_reg ,1 ,1'b0); `CHECK_F(f_bit1 ,1 ,1'b1); `CHECK_F(f_logic1 ,1 ,1'b0); `CHECK_F(f_reg1 ,1 ,1'b0); `CHECK_F(f_bit2 ,2 ,1'b1); `CHECK_F(f_logic2 ,2 ,1'b0); `CHECK_F(f_reg2 ,2 ,1'b0); // For unpacked types we don't want width warnings for unsized numbers that fit d_byte = 2; d_shortint= 2; d_int = 2; d_longint = 2; d_integer = 2; // Special check d_time = $time; if ($time !== d_time) $stop; // Null checks d_chandle = null; if (d_chandle != null) $stop; if (d_chandle) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_stop_bad.py0000755000542200017500000000101415101701376021555 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_gen_upscope.py0000755000542200017500000000100015101701376022264 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dpi_sys.py0000755000542200017500000000077215101701376021446 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=["t/t_dpi_sys_c.cpp"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_dpi_export_context2_bad.cpp0000644000542200017500000000216015101701376024725 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include VM_PREFIX_INCLUDE //====================================================================== #include "Vt_dpi_export_context2_bad__Dpi.h" //====================================================================== unsigned int main_time = 0; double sc_time_stamp() { return main_time; } VM_PREFIX* topp = nullptr; int main(int argc, char* argv[]) { Verilated::debug(0); Verilated::commandArgs(argc, argv); topp = new VM_PREFIX; topp->eval(); VL_DO_DANGLING(delete topp, topp); return 1; } int dpii_task() { // Check DPI warnings svScope scope = svGetScope(); // Will warn (void)scope; // Unused const char* filenamep = ""; int lineno = 0; svGetCallerInfo(&filenamep, &lineno); // Will warn (void)filenamep; // Unused (void)lineno; // Unused dpix_task(); return 0; } verilator-5.042/test_regress/t/t_time_vpi_10ms10ns.out0000644000542200017500000000174715101701376023331 0ustar mahmoudyfreeshell:: In top.t Time scale of t is 10ms / 10ns [60000000] time%0d=60 123%0t=123000000 dig%0t=543000000 dig%0d=543 rdig%0t=543210988 rdig%0f=543.210988 acc%0t=12345678901234567890000000 acc%0d=12345678901234567890 [600000000.000000ns] time%0d=60 123%0t=1230000000.000000ns dig%0t=5430000000.000000ns dig%0d=543 rdig%0t=5432109876.543210ns rdig%0f=543.210988 acc%0t=123456789012345678900000000.000000ns acc%0d=12345678901234567890 [600000000.000000ns] stime%0t=600000000.000000ns stime%0d=60 stime%0f=60.000000 [600000000.000000ns] rtime%0t=600000000.000000ns rtime%0d=60 rtime%0f=60.000000 global svGetTime = 0 0,60000000 global svGetTimeUnit = 0 -2 svGetTmePrecision = 0 -8 global vpiSimTime = 0,60000000 vpiScaledRealTime = 6e+07 global vpiTimeUnit = -2 vpiTimePrecision = -8 top.t svGetTime = 0 0,60000000 top.t svGetTimeUnit = 0 -2 svGetTmePrecision = 0 -8 top.t vpiSimTime = 0,60000000 vpiScaledRealTime = 60 top.t vpiTimeUnit = -2 vpiTimePrecision = -8 *-* All Finished *-* verilator-5.042/test_regress/t/t_vlt_timing.py0000755000542200017500000000106315101701376022142 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_timing_off.v" test.compile(verilator_flags2=["--binary t/t_vlt_timing.vlt"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_class_super_bad2.py0000755000542200017500000000076615101701376023212 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_event_control_star_never_bad.py0000755000542200017500000000155415101701376025712 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.top_filename = 't/t_event_control_star_never.v' test.lint(verilator_flags2=['--timing'], fails=True, expect_filename=test.golden_filename) test.extract(in_filename=test.top_filename, out_filename=test.root + "/docs/gen/ex_ALWNEVER_faulty.rst", lines="9-9") test.extract(in_filename=test.golden_filename, out_filename=test.root + "/docs/gen/ex_ALWNEVER_msg.rst", lines="1-1") test.passes() verilator-5.042/test_regress/t/t_fork_dynscope_out.py0000755000542200017500000000101115101701376023513 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary -Wno-INITIALDLY"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_assert_disable_iff.py0000755000542200017500000000101615101701376023574 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--assert --cc --coverage-user']) test.execute() test.passes() verilator-5.042/test_regress/t/t_class_extends_vsyment.v0000644000542200017500000000054115101701376024224 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class Foo; endclass class Bar extends Foo; int m_field = get_1(); function int get_1(); return 1; endfunction endclass verilator-5.042/test_regress/t/t_while_timing_control.py0000755000542200017500000000100615101701376024202 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--binary -Wno-ZERODLY']) test.execute() test.passes() verilator-5.042/test_regress/t/t_param_pattern_init_scope.v0000644000542200017500000000246315101701376024656 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilog_format: off `define stop $stop `define checkh(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); // verilog_format: on package some_pkg; localparam FOO = 5; localparam BAR = 6; typedef enum int {QUX = 7} pkg_enum_t; endpackage module t ( input clk ); int cyc = 0; logic [31:0] package_array[8]; always_comb package_array = '{ 1: 32'h1111, some_pkg::FOO: 32'h9876, some_pkg::BAR: 32'h1212, some_pkg::QUX: 32'h5432, default: 0 }; always @(posedge clk) begin `checkh(package_array[0], 32'h0); `checkh(package_array[1], 32'h1111); `checkh(package_array[2], 32'h0); `checkh(package_array[3], 32'h0); `checkh(package_array[4], 32'h0); `checkh(package_array[5], 32'h9876); `checkh(package_array[6], 32'h1212); `checkh(package_array[7], 32'h5432); end always @(posedge clk) begin cyc <= cyc + 1; if (cyc == 2) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_math_signed.v0000644000542200017500000001425115101701376022065 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; by_width #(1) w1 (.clk(clk)); by_width #(31) w31 (.clk(clk)); by_width #(32) w32 (.clk(clk)); by_width #(33) w33 (.clk(clk)); by_width #(63) w63 (.clk(clk)); by_width #(64) w64 (.clk(clk)); by_width #(65) w65 (.clk(clk)); by_width #(95) w95 (.clk(clk)); by_width #(96) w96 (.clk(clk)); by_width #(97) w97 (.clk(clk)); reg signed [15:0] a; reg signed [4:0] b; reg signed [15:0] sr,srs,sl,sls; reg [15:0] b_s; reg [15:0] b_us; task check_s(input signed [7:0] i, input [7:0] expval); //$display("check_s %x\n", i); if (i !== expval) $stop; endtask task check_us(input signed [7:0] i, input [7:0] expval); //$display("check_us %x\n", i); if (i !== expval) $stop; endtask always @* begin sr = a>>b; srs = copy_signed(a)>>>b; sl = a<>>4; // Signed b_us = b[4:0]>>>4; // Unsigned, due to extract check_s ( 3'b111, 8'h07); check_s (3'sb111, 8'hff); check_us( 3'b111, 8'h07); check_us(3'sb111, 8'hff); // Note we sign extend ignoring function's input requirements // verilator lint_on WIDTH end reg signed [32:0] bug349; initial begin end integer i; initial begin if ((-1 >>> 3) != -1) $stop; // Decimals are signed // verilator lint_off WIDTH if ((3'b111 >>> 3) != 0) $stop; // Based numbers are unsigned if ((3'sb111 >>> 3) != -1) $stop; // Signed based numbers // verilator lint_on WIDTH if ( (3'sb000 > 3'sb000)) $stop; if (!(3'sb000 > 3'sb111)) $stop; if ( (3'sb111 > 3'sb000)) $stop; if ( (3'sb000 < 3'sb000)) $stop; if ( (3'sb000 < 3'sb111)) $stop; if (!(3'sb111 < 3'sb000)) $stop; if (!(3'sb000 >= 3'sb000)) $stop; if (!(3'sb000 >= 3'sb111)) $stop; if ( (3'sb111 >= 3'sb000)) $stop; if (!(3'sb000 <= 3'sb000)) $stop; if ( (3'sb000 <= 3'sb111)) $stop; if (!(3'sb111 <= 3'sb000)) $stop; // When we multiply overflow, the sign bit stays correct. if ( (4'sd2*4'sd8) != 4'd0) $stop; // From the spec: // verilator lint_off WIDTH i = -12 /3; if (i !== 32'hfffffffc) $stop; i = -'d12 /3; if (i !== 32'h55555551) $stop; i = -'sd12 /3; if (i !== 32'hfffffffc) $stop; i = -4'sd12 /3; if (i !== 32'h00000001) $stop; // verilator lint_on WIDTH // verilator lint_off WIDTH bug349 = 4'sb1111 - 1'b1; if (bug349 != 32'he) $stop; end function signed [15:0] copy_signed; input [15:0] ai; copy_signed = ai; endfunction integer cyc; initial cyc = 0; wire [31:0] ucyc = cyc; always @ (posedge clk) begin cyc <= cyc + 1; `ifdef TEST_VERBOSE $write("%x %x %x %x %x %x %x\n", cyc, sr,srs,sl,sls, b_s,b_us); `endif case (cyc) 0: begin a <= 16'sh8b1b; b <= 5'sh1f; // -1 end 1: begin // Check spaces in constants a <= 16 'sh 8b1b; b <= 5'sh01; // -1 end 2: begin a <= 16'sh8b1b; b <= 5'sh1e; // shift AMOUNT is really unsigned if (ucyc / 1 != 32'd2) $stop; if (ucyc / 2 != 32'd1) $stop; if (ucyc * 1 != 32'd2) $stop; if (ucyc * 2 != 32'd4) $stop; if (ucyc * 3 != 32'd6) $stop; if (cyc * 32'sd1 != 32'sd2) $stop; if (cyc * 32'sd2 != 32'sd4) $stop; if (cyc * 32'sd3 != 32'sd6) $stop; end 3: begin a <= 16'sh0048; b <= 5'sh1f; if (ucyc * 1 != 32'd3) $stop; if (ucyc * 2 != 32'd6) $stop; if (ucyc * 3 != 32'd9) $stop; if (ucyc * 4 != 32'd12) $stop; if (cyc * 32'sd1 != 32'sd3) $stop; if (cyc * 32'sd2 != 32'sd6) $stop; if (cyc * 32'sd3 != 32'sd9) $stop; end 4: begin a <= 16'sh4154; b <= 5'sh02; end 5: begin a <= 16'shc3e8; b <= 5'sh12; end 6: begin a <= 16'sh488b; b <= 5'sh02; end 9: begin $write("*-* All Finished *-*\n"); $finish; end default: ; endcase case (cyc) 0: ; 1: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh0000_ffff_0000_0000_ffff_0001) $stop; 2: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh458d_c58d_1636_1636_0000_0000) $stop; 3: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh0000_ffff_0000_0000_ffff_0001) $stop; 4: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh0000_0000_0000_0000_ffff_0001) $stop; 5: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh1055_1055_0550_0550_0000_0000) $stop; 6: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh0000_ffff_0000_0000_ffff_0001) $stop; 7: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh1222_1222_222c_222c_0000_0000) $stop; 8: ; 9: ; endcase end endmodule module by_width ( input clk ); parameter WIDTH=1; reg signed i1; reg signed [62:0] i63; reg signed [64:0] i65; // verilator lint_off WIDTH wire signed [WIDTH-1:0] i1extp /*verilator public*/ = i1; wire signed [WIDTH-1:0] i1ext = i1; wire signed [WIDTH-1:0] i63ext = i63; wire signed [WIDTH-1:0] i65ext = i65; // verilator lint_on WIDTH integer cyc; initial cyc = 0; always @ (posedge clk) begin cyc <= cyc + 1; i1 <= cyc[0]; i63 <= {63{cyc[0]}}; i65 <= {65{cyc[0]}}; case (cyc) 1: begin if (i1extp != {WIDTH{1'b0}}) $stop; if (i1ext != {WIDTH{1'b0}}) $stop; if (i63ext != {WIDTH{1'b0}}) $stop; if (i65ext != {WIDTH{1'b0}}) $stop; end 2: begin if (i1extp != {WIDTH{1'b1}}) $stop; if (i1ext != {WIDTH{1'b1}}) $stop; if (i63ext != {WIDTH{1'b1}}) $stop; if (i65ext != {WIDTH{1'b1}}) $stop; end default: ; endcase end endmodule verilator-5.042/test_regress/t/t_config_libmap_inc.map0000644000542200017500000000067615101701376023543 0ustar mahmoudyfreeshell// -*- Verilog -*- // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // lib.map file: include ./t_config_libmap_inc.map library rtllib *.v; library rtllib2 *.v, *.sv; library rtllib3 *.v -incdir *.vh; library rtllib4 *.v -incdir *.vh, *.svh; config cfg; design t; endconfig verilator-5.042/test_regress/t/t_flag_hierarchical_threads_bad.py0000755000542200017500000000106715101701376025721 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, verilator_flags2=['--hierarchical-threads -2'], expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_reloop_local.v0000644000542200017500000000304615101701376022255 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Justin Yao Du. // SPDX-License-Identifier: CC0-1.0 typedef logic [7:0] Word; typedef logic [255:0] BigItem; module shuffler ( input logic clk, input logic reset_l, output logic odd, output logic [255:0][7:0] shuffle ); Word ctr; assign odd = ctr[0]; always_ff @(posedge clk) begin if (!reset_l) begin ctr <= 0; end else begin ctr <= ctr + 1; end end for (genvar i = 0; i < 256; i++) always_comb begin shuffle[i] = Word'(i) - ctr; end for (genvar i = 0; i < 256; i++) begin assert property (@(posedge clk) shuffle[ctr + Word'(i)] == i); end endmodule interface big_port(); BigItem big; function automatic BigItem get_big(); return big; endfunction modport reader(import get_big); endinterface module foo ( input clk, input reset_l, big_port.reader big); logic odd; Word[255 : 0] shuffle; shuffler fifo ( .clk, .reset_l, .odd, .shuffle ); BigItem bigs[256]; for (genvar i = 0; i < 256; i++) always_comb begin bigs[i] = odd ? big.get_big() : 0; end endmodule module t (/*AUTOARG*/ // Inputs clk, reset_l ); input clk; input reset_l; big_port big(); foo foo ( .clk, .reset_l, .big); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_force_chained.py0000755000542200017500000000102715101701376022537 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["--binary"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_split_var_xref.py0000755000542200017500000000101315101701376023010 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(timing_loop=True, verilator_flags2=["--timing"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_flag_f.py0000755000542200017500000000076315101701376021212 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(v_flags2=["-f t/t_flag_f.vc"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_import_name_bad.v0000644000542200017500000000044415101701376023750 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package defs; int sig; endpackage import defs::sigs; module t; endmodule verilator-5.042/test_regress/t/t_covergroup_coverpoints_unsup.out0000644000542200017500000000744715101701376026236 0ustar mahmoudyfreeshell%Warning-COVERIGN: t/t_covergroup_coverpoints_unsup.v:21:19: Ignoring unsupported: coverage clocking event 21 | covergroup cg @(posedge clk); | ^ ... For warning description see https://verilator.org/warn/COVERIGN?v=latest ... Use "/* verilator lint_off COVERIGN */" and lint_on around source to disable this message. %Warning-COVERIGN: t/t_covergroup_coverpoints_unsup.v:22:9: Ignoring unsupported: coverpoint 22 | coverpoint a; | ^~~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_coverpoints_unsup.v:24:31: Ignoring unsupported: cover bin specification 24 | bins the_bins [5] = { [0:20] }; | ^ %Warning-COVERIGN: t/t_covergroup_coverpoints_unsup.v:23:9: Ignoring unsupported: coverpoint 23 | coverpoint b { | ^~~~~~~~~~ %Warning-COVERIGN: t/t_covergroup_coverpoints_unsup.v:21:5: Ignoring unsupported: covergroup 21 | covergroup cg @(posedge clk); | ^~~~~~~~~~ %Error: t/t_covergroup_coverpoints_unsup.v:35:48: Member 'a' not found in class 'cg' : ... note: In instance 't' 35 | $display("coverage a = %f", the_cg.a.get_inst_coverage()); | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error-UNSUPPORTED: t/t_covergroup_coverpoints_unsup.v:35:50: Unsupported: Member call on object 'CONST '1'h0'' which is a 'BASICDTYPE 'logic'' : ... note: In instance 't' 35 | $display("coverage a = %f", the_cg.a.get_inst_coverage()); | ^~~~~~~~~~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: t/t_covergroup_coverpoints_unsup.v:36:48: Member 'b' not found in class 'cg' : ... note: In instance 't' 36 | $display("coverage b = %f", the_cg.b.get_inst_coverage()); | ^ %Error-UNSUPPORTED: t/t_covergroup_coverpoints_unsup.v:36:50: Unsupported: Member call on object 'CONST '1'h0'' which is a 'BASICDTYPE 'logic'' : ... note: In instance 't' 36 | $display("coverage b = %f", the_cg.b.get_inst_coverage()); | ^~~~~~~~~~~~~~~~~ %Error: t/t_covergroup_coverpoints_unsup.v:37:24: Member 'a' not found in class 'cg' : ... note: In instance 't' 37 | if (the_cg.a.get_inst_coverage() != 15/16.0) $stop(); | ^ %Error-UNSUPPORTED: t/t_covergroup_coverpoints_unsup.v:37:26: Unsupported: Member call on object 'CONST '1'h0'' which is a 'BASICDTYPE 'logic'' : ... note: In instance 't' 37 | if (the_cg.a.get_inst_coverage() != 15/16.0) $stop(); | ^~~~~~~~~~~~~~~~~ %Error: t/t_covergroup_coverpoints_unsup.v:38:24: Member 'b' not found in class 'cg' : ... note: In instance 't' 38 | if (the_cg.b.get_inst_coverage() != 4/5.0) $stop(); | ^ %Error-UNSUPPORTED: t/t_covergroup_coverpoints_unsup.v:38:26: Unsupported: Member call on object 'CONST '1'h0'' which is a 'BASICDTYPE 'logic'' : ... note: In instance 't' 38 | if (the_cg.b.get_inst_coverage() != 4/5.0) $stop(); | ^~~~~~~~~~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_preproc_inc_notfound_bad.py0000755000542200017500000000076615101701376025024 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_preproc_ttempty.out0000644000542200017500000000000015101701376023370 0ustar mahmoudyfreeshellverilator-5.042/test_regress/t/t_dpi_arg_inout_type__Dpi.out0000644000542200017500000001454715101701376024774 0ustar mahmoudyfreeshell// Verilated -*- C++ -*- // DESCRIPTION: Verilator output: Prototypes for DPI import and export functions. // // Verilator includes this file in all generated .cpp files that use DPI functions. // Manually include this file where DPI .c import functions are declared to ensure // the C functions match the expectations of the DPI imports. #ifndef VERILATED_VT_DPI_ARG_INOUT_TYPE__DPI_H_ #define VERILATED_VT_DPI_ARG_INOUT_TYPE__DPI_H_ // guard #include "svdpi.h" #ifdef __cplusplus extern "C" { #endif // DPI EXPORTS extern void e_array_2_state_1(svBitVecVal* x); extern void e_array_2_state_128(svBitVecVal* x); extern void e_array_2_state_32(svBitVecVal* x); extern void e_array_2_state_33(svBitVecVal* x); extern void e_array_2_state_64(svBitVecVal* x); extern void e_array_2_state_65(svBitVecVal* x); extern void e_array_4_state_1(svLogicVecVal* x); extern void e_array_4_state_128(svLogicVecVal* x); extern void e_array_4_state_32(svLogicVecVal* x); extern void e_array_4_state_33(svLogicVecVal* x); extern void e_array_4_state_64(svLogicVecVal* x); extern void e_array_4_state_65(svLogicVecVal* x); extern void e_bit(svBit* x); extern void e_bit_t(svBit* x); extern void e_byte(char* x); extern void e_byte_t(char* x); extern void e_byte_unsigned(unsigned char* x); extern void e_byte_unsigned_t(unsigned char* x); extern void e_chandle(void** x); extern void e_chandle_t(void** x); extern void e_int(int* x); extern void e_int_t(int* x); extern void e_int_unsigned(unsigned int* x); extern void e_int_unsigned_t(unsigned int* x); extern void e_integer(svLogicVecVal* x); extern void e_integer_t(svLogicVecVal* x); extern void e_logic(svLogic* x); extern void e_logic_t(svLogic* x); extern void e_longint(long long* x); extern void e_longint_t(long long* x); extern void e_longint_unsigned(unsigned long long* x); extern void e_longint_unsigned_t(unsigned long long* x); extern void e_real(double* x); extern void e_real_t(double* x); extern void e_shortint(short* x); extern void e_shortint_t(short* x); extern void e_shortint_unsigned(unsigned short* x); extern void e_shortint_unsigned_t(unsigned short* x); extern void e_string(const char** x); extern void e_string_t(const char** x); extern void e_struct_2_state_1(svBitVecVal* x); extern void e_struct_2_state_128(svBitVecVal* x); extern void e_struct_2_state_32(svBitVecVal* x); extern void e_struct_2_state_33(svBitVecVal* x); extern void e_struct_2_state_64(svBitVecVal* x); extern void e_struct_2_state_65(svBitVecVal* x); extern void e_struct_4_state_1(svLogicVecVal* x); extern void e_struct_4_state_128(svLogicVecVal* x); extern void e_struct_4_state_32(svLogicVecVal* x); extern void e_struct_4_state_33(svLogicVecVal* x); extern void e_struct_4_state_64(svLogicVecVal* x); extern void e_struct_4_state_65(svLogicVecVal* x); extern void e_time(svLogicVecVal* x); extern void e_time_t(svLogicVecVal* x); extern void e_union_2_state_1(svBitVecVal* x); extern void e_union_2_state_128(svBitVecVal* x); extern void e_union_2_state_32(svBitVecVal* x); extern void e_union_2_state_33(svBitVecVal* x); extern void e_union_2_state_64(svBitVecVal* x); extern void e_union_2_state_65(svBitVecVal* x); extern void e_union_4_state_1(svLogicVecVal* x); extern void e_union_4_state_128(svLogicVecVal* x); extern void e_union_4_state_32(svLogicVecVal* x); extern void e_union_4_state_33(svLogicVecVal* x); extern void e_union_4_state_64(svLogicVecVal* x); extern void e_union_4_state_65(svLogicVecVal* x); // DPI IMPORTS extern void check_exports(); extern void i_array_2_state_1(svBitVecVal* x); extern void i_array_2_state_128(svBitVecVal* x); extern void i_array_2_state_32(svBitVecVal* x); extern void i_array_2_state_33(svBitVecVal* x); extern void i_array_2_state_64(svBitVecVal* x); extern void i_array_2_state_65(svBitVecVal* x); extern void i_array_4_state_1(svLogicVecVal* x); extern void i_array_4_state_128(svLogicVecVal* x); extern void i_array_4_state_32(svLogicVecVal* x); extern void i_array_4_state_33(svLogicVecVal* x); extern void i_array_4_state_64(svLogicVecVal* x); extern void i_array_4_state_65(svLogicVecVal* x); extern void i_bit(svBit* x); extern void i_bit_t(svBit* x); extern void i_byte(char* x); extern void i_byte_t(char* x); extern void i_byte_unsigned(unsigned char* x); extern void i_byte_unsigned_t(unsigned char* x); extern void i_chandle(void** x); extern void i_chandle_t(void** x); extern void i_int(int* x); extern void i_int_t(int* x); extern void i_int_unsigned(unsigned int* x); extern void i_int_unsigned_t(unsigned int* x); extern void i_integer(svLogicVecVal* x); extern void i_integer_t(svLogicVecVal* x); extern void i_logic(svLogic* x); extern void i_logic_t(svLogic* x); extern void i_longint(long long* x); extern void i_longint_t(long long* x); extern void i_longint_unsigned(unsigned long long* x); extern void i_longint_unsigned_t(unsigned long long* x); extern void i_real(double* x); extern void i_real_t(double* x); extern void i_shortint(short* x); extern void i_shortint_t(short* x); extern void i_shortint_unsigned(unsigned short* x); extern void i_shortint_unsigned_t(unsigned short* x); extern void i_string(const char** x); extern void i_string_t(const char** x); extern void i_struct_2_state_1(svBitVecVal* x); extern void i_struct_2_state_128(svBitVecVal* x); extern void i_struct_2_state_32(svBitVecVal* x); extern void i_struct_2_state_33(svBitVecVal* x); extern void i_struct_2_state_64(svBitVecVal* x); extern void i_struct_2_state_65(svBitVecVal* x); extern void i_struct_4_state_1(svLogicVecVal* x); extern void i_struct_4_state_128(svLogicVecVal* x); extern void i_struct_4_state_32(svLogicVecVal* x); extern void i_struct_4_state_33(svLogicVecVal* x); extern void i_struct_4_state_64(svLogicVecVal* x); extern void i_struct_4_state_65(svLogicVecVal* x); extern void i_time(svLogicVecVal* x); extern void i_time_t(svLogicVecVal* x); extern void i_union_2_state_1(svBitVecVal* x); extern void i_union_2_state_128(svBitVecVal* x); extern void i_union_2_state_32(svBitVecVal* x); extern void i_union_2_state_33(svBitVecVal* x); extern void i_union_2_state_64(svBitVecVal* x); extern void i_union_2_state_65(svBitVecVal* x); extern void i_union_4_state_1(svLogicVecVal* x); extern void i_union_4_state_128(svLogicVecVal* x); extern void i_union_4_state_32(svLogicVecVal* x); extern void i_union_4_state_33(svLogicVecVal* x); extern void i_union_4_state_64(svLogicVecVal* x); extern void i_union_4_state_65(svLogicVecVal* x); #ifdef __cplusplus } #endif #endif // guard verilator-5.042/test_regress/t/t_trace_no_top_name.out0000644000542200017500000000033315101701376023615 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module another_top $end $var wire 1 # b $end $upscope $end $scope module t $end $var wire 1 # a $end $upscope $end $enddefinitions $end #0 0# verilator-5.042/test_regress/t/t_clocking_bad5.py0000755000542200017500000000102515101701376022450 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["--timing"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_opt_localize_deep.py0000755000542200017500000000106515101701376023451 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile( # We have deep expressions we want to test) verilator_flags2=["--compiler msvc"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_preproc_dump_defines.py0000755000542200017500000000151415101701376024163 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_preproc.v" stdout_filename = os.path.join(test.obj_dir, test.name + "__test.vpp") test.compile(verilator_flags2=['-DDEF_A0 -DPREDEF_COMMAND_LINE -E --dump-defines'], verilator_make_gmake=False, make_top_shell=False, make_main=False, stdout_filename=stdout_filename) test.files_identical(stdout_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_gen_intdot2.v0000644000542200017500000001061015101701376022012 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg check; initial check = 1'b0; Genit g (.clk(clk), .check(check)); always @ (posedge clk) begin //$write("[%0t] cyc==%0d %x %x\n", $time, cyc, check, out); cyc <= cyc + 1; if (cyc==0) begin // Setup check <= 1'b0; end else if (cyc==1) begin check <= 1'b1; end else if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end //`define WAVES `ifdef WAVES initial begin $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); $dumpvars(12, t); end `endif endmodule module One; wire one = 1'b1; endmodule module Genit ( input clk, input check); // ARRAY One cellarray1[1:0] (); //cellarray[0..1][0..1] always @ (posedge clk) if (cellarray1[0].one !== 1'b1) $stop; always @ (posedge clk) if (cellarray1[1].one !== 1'b1) $stop; // IF generate // genblk1 refers to the if's name, not the "generate" itself. if (1'b1) // IMPLIED begin: genblk1 One ifcell1(); // genblk1.ifcell1 else One ifcell1(); // genblk1.ifcell1 endgenerate // DISAGREEMENT on this naming always @ (posedge clk) if (genblk1.ifcell1.one !== 1'b1) $stop; generate begin : namedif2 if (1'b1) One ifcell2(); // namedif2.genblk1.ifcell2 end endgenerate // DISAGREEMENT on this naming always @ (posedge clk) if (namedif2.genblk1.ifcell2.one !== 1'b1) $stop; generate if (1'b1) begin : namedif3 One ifcell3(); // namedif3.ifcell3 end endgenerate always @ (posedge clk) if (namedif3.ifcell3.one !== 1'b1) $stop; // CASE generate begin : casecheck case (1'b1) 1'b1 : One casecell10(); // genblk4.casecell10 endcase end endgenerate // DISAGREEMENT on this naming always @ (posedge clk) if (casecheck.genblk1.casecell10.one !== 1'b1) $stop; generate case (1'b1) 1'b1 : begin : namedcase11 One casecell11(); end endcase endgenerate always @ (posedge clk) if (namedcase11.casecell11.one !== 1'b1) $stop; genvar i; genvar j; generate begin : genfor for (i = 0; i < 2; i = i + 1) One cellfor20 (); // genfor.genblk1[0..1].cellfor20 end endgenerate // DISAGREEMENT on this naming always @ (posedge clk) if (genfor.genblk1[0].cellfor20.one !== 1'b1) $stop; always @ (posedge clk) if (genfor.genblk1[1].cellfor20.one !== 1'b1) $stop; // COMBO generate for (i = 0; i < 2; i = i + 1) begin : namedfor21 One cellfor21 (); // namedfor21[0..1].cellfor21 end endgenerate always @ (posedge clk) if (namedfor21[0].cellfor21.one !== 1'b1) $stop; always @ (posedge clk) if (namedfor21[1].cellfor21.one !== 1'b1) $stop; generate for (i = 0; i < 2; i = i + 1) begin : namedfor30 for (j = 0; j < 2; j = j + 1) begin : forb30 if (j == 0) begin : forif30 One cellfor30a (); // namedfor30[0..1].forb30[0].forif30.cellfor30a end else `ifdef verilator begin : forif30b `else begin : forif30 // forif30 seems to work on some simulators, not verilator yet `endif One cellfor30b (); // namedfor30[0..1].forb30[1].forif30.cellfor30b end end end endgenerate always @ (posedge clk) if (namedfor30[0].forb30[0].forif30.cellfor30a.one !== 1'b1) $stop; always @ (posedge clk) if (namedfor30[1].forb30[0].forif30.cellfor30a.one !== 1'b1) $stop; `ifdef verilator always @ (posedge clk) if (namedfor30[0].forb30[1].forif30b.cellfor30b.one !== 1'b1) $stop; always @ (posedge clk) if (namedfor30[1].forb30[1].forif30b.cellfor30b.one !== 1'b1) $stop; `else always @ (posedge clk) if (namedfor30[0].forb30[1].forif30.cellfor30b.one !== 1'b1) $stop; always @ (posedge clk) if (namedfor30[1].forb30[1].forif30.cellfor30b.one !== 1'b1) $stop; `endif endmodule verilator-5.042/test_regress/t/t_class_new.py0000755000542200017500000000073415101701376021750 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_inst_pin_realnreal.py0000755000542200017500000000105515101701376023637 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) if not test.vlt_all: test.execute() test.passes() verilator-5.042/test_regress/t/t_inst_array_bad.v0000644000542200017500000000112415101701376022557 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; wire [7:0] bitout; reg [7:0] allbits; reg [7:0] onebit; reg [8:0] onebitbad; // Wrongly sized sub sub [7:0] (allbits, onebitbad, bitout); // This is ok. wire [9:8] b; wire [1:0] c; sub sub2 [9:8] (allbits,b,c); endmodule module sub (input [7:0] allbits, input onebit, output bitout); assign bitout = onebit ^ (^ allbits); endmodule verilator-5.042/test_regress/t/t_wide_temp_while_cond.v0000644000542200017500000000134315101701376023751 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 import "DPI-C" pure function int identity(input int value); module t; initial begin int n = 0; logic [127:0] val = 128'b1; logic [15:0] one = 16'b1; // This condition involves multiple wide temporaries, and an over-width // shift, all of which requires V3Premit to fix up. while (|((val[ 7'(one >> identity(32)) +: 96] << n) >> n)) begin ++n; end $display("n=%0d", n); if (n != 96) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_savable_coverage_bad.v0000644000542200017500000000035215101701376023676 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; endmodule verilator-5.042/test_regress/t/t_sarif_output.py0000755000542200017500000000117415101701376022515 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_sarif.v" test.lint( verilator_flags2=['-Wno-fatal', '--diagnostics-sarif-output', test.obj_dir + "/my.sarif"]) test.file_grep(test.obj_dir + "/my.sarif", "t_sarif.v") test.passes() verilator-5.042/test_regress/t/t_clocking_timing2.py0000755000542200017500000000112015101701376023202 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_clocking_timing.v" test.compile(verilator_flags2=["--binary -DTEST_INPUT_SKEW=12 -DTEST_OUTPUT_SKEW=16"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_struct_anon.py0000755000542200017500000000070615101701376022330 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.042/test_regress/t/t_reloop_offset_lim_63.py0000755000542200017500000000167215101701376024013 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_reloop_offset.v" test.golden_filename = "t/t_reloop_offset.out" test.compile(verilator_flags2=[ "-unroll-count 1024", test.wno_unopthreads_for_few_cores, "--reloop-limit 63", "--stats" ]) test.execute(expect_filename=test.golden_filename) if test.vlt: # Note, with vltmt this might be split differently, so only checking vlt test.file_grep(test.stats, r'Optimizations, Reloop iterations\s+(\d+)', 63) test.file_grep(test.stats, r'Optimizations, Reloops\s+(\d+)', 1) test.passes() verilator-5.042/test_regress/t/t_altera_lpm_decode.py0000755000542200017500000000111115101701376023403 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) test.compile(verilator_flags2=["--top-module", module]) test.passes() verilator-5.042/test_regress/t/t_assert_comp.py0000755000542200017500000000106415101701376022306 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--assert'], nc_flags2=['+assert']) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_hier_trace.py0000755000542200017500000000131515101701376022073 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=[ '--trace-vcd', '-j 4', 't/t_hier_trace_sub/t_hier_trace.vlt', '--top-module t', '--hierarchical', '-F t/t_hier_trace_sub/top.F' ]) test.execute(all_run_flags=['-j 4']) test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_flag_topmodule_inline.v0000644000542200017500000000110315101701376024132 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module a; a2 a2 (.tmp(1'b0)); initial begin $write("Bad top modules\n"); $stop; end endmodule module a2 (input tmp); l3 l3 (.tmp(tmp)); endmodule module b; l3 l3 (.tmp(1'b1)); endmodule module l3 (input tmp); initial begin if (tmp) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_force_readwrite.v0000644000542200017500000000071315101701376022745 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Cls; task take_ref(ref logic s); endtask endclass module t; logic a; logic b = 1; logic c; Cls cls = new; initial begin force a = b; cls.take_ref(c); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_class_extends_this.v0000644000542200017500000000343215101701376023470 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef class Cls; class Base; class BaseInner; int value = 10; function void test; if (value != 10) $stop; if (this.value != 10) $stop; value = 20; if (value != 20) $stop; this.value = 30; if (value != 30) $stop; endfunction endclass int value = 1; BaseInner inner = new; function void test; if (value != 1) $stop; if (this.value != 1) $stop; value = 2; if (value != 2) $stop; this.value = 3; if (value != 3) $stop; endfunction endclass class Cls extends Base; class BaseInner extends Base::BaseInner; int value = 100; function void test; if (value != 100) $stop; if (this.value != 100) $stop; if (super.value != 10) $stop; super.test(); if (value != 100) $stop; if (this.value != 100) $stop; if (super.value != 30) $stop; value = 200; if (value != 200) $stop; this.value = 300; if (value != 300) $stop; endfunction endclass int value = 20; BaseInner inner = new; function void test; if (value != 20) $stop; if (this.value != 20) $stop; if (super.value != 1) $stop; super.test(); if (this.value != 20) $stop; super.value = 9; this.value = 29; if (super.value != 9) $stop; if (value != 29) $stop; inner.test(); endfunction endclass module t; initial begin Cls c; c = new; c.test(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_class_new_bad.out0000644000542200017500000000357215101701376022735 0ustar mahmoudyfreeshell%Error: t/t_class_new_bad.v:27:19: class 'new()' cannot be static (IEEE 1800-2023 18.3) : ... note: In instance 't' 27 | static function new(); | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_class_new_bad.v:32:20: class 'new()' cannot be virual (IEEE 1800-2023 18.3) : ... note: In instance 't' 32 | virtual function new(); | ^~~ %Error: t/t_class_new_bad.v:39:19: class 'new()' cannot be virual (IEEE 1800-2023 18.3) : ... note: In instance 't' 39 | function ClsNew3::new(); | ^~~ %Error: t/t_class_new_bad.v:47:16: Too many arguments in function call to FUNC 'new' : ... note: In instance 't' 47 | c1 = new(3); | ^ %Error: t/t_class_new_bad.v:48:16: Too many arguments in function call to FUNC 'new' : ... note: In instance 't' 48 | c2 = new(3); | ^ %Error: t/t_class_new_bad.v:49:12: Missing argument on non-defaulted argument 'i' in function call to FUNC 'new' : ... note: In instance 't' 49 | c3 = new(); | ^~~ %Error: t/t_class_new_bad.v:50:12: dynamic new() not expected in this context (data type must be dynamic array) : ... note: In instance 't' 50 | c1 = new[2]; | ^~~ %Error: Internal Error: t/t_class_new_bad.v:50:12: ../V3Width.cpp:#: Node has no type : ... note: In instance 't' 50 | c1 = new[2]; | ^~~ ... This fatal error may be caused by the earlier error(s); resolve those first. verilator-5.042/test_regress/t/t_langext_1d_bad.out0000644000542200017500000000070215101701376022775 0ustar mahmoudyfreeshell%Error: t/t_langext_1.v:44:7: syntax error, unexpected IDENTIFIER-for-type 44 | genvar i; | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_langext_1.v:51:1: syntax error, unexpected endmodule, expecting '(' 51 | endmodule | ^~~~~~~~~ %Error: Cannot continue ... This fatal error may be caused by the earlier error(s); resolve those first. verilator-5.042/test_regress/t/t_mem_slot.v0000644000542200017500000000121015101701376021411 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define RegDel 1 module t_mem_slot (Clk, SlotIdx, BitToChange, BitVal, SlotToReturn, OutputVal); input Clk; input [1:0] SlotIdx; input BitToChange; input BitVal; input [1:0] SlotToReturn; output bit [1:0] OutputVal; bit [1:0] Array[2:0]; always @(posedge Clk) begin Array[SlotIdx][BitToChange] <= #`RegDel BitVal; OutputVal = Array[SlotToReturn]; end endmodule verilator-5.042/test_regress/t/t_jumps_uninit_destructor_call.py0000755000542200017500000000077115101701376025770 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_tri_cond_eqcase_with_1.v0000644000542200017500000000070215101701376024174 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; wire a; assign a = 1 === (clk ? 1 : 1'bz); always begin if (!a) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_class_param_mod.v0000644000542200017500000000616115101701376022730 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); // See also t_class_param.v module t; class Cls #(parameter PBASE = 12); bit [PBASE-1:0] member; function bit [PBASE-1:0] get_member; return member; endfunction static function int get_p; return PBASE; endfunction typedef enum { E_PBASE = PBASE } enum_t; endclass class Wrap #(parameter P = 13); function int get_p; return c1.get_p(); endfunction function new; c1 = new; endfunction Cls#(PMINUS1 + 1) c1; localparam PMINUS1 = P - 1; // Checking works when last endclass class Wrap2 #(parameter P = 35); function int get_p; return c1.get_p(); endfunction function new; c1 = new; endfunction Wrap#(PMINUS1 + 1) c1; localparam PMINUS1 = P - 1; // Checking works when last endclass typedef Cls#(8) Cls8_t; class SelfRefClassTypeParam #(type T=logic); typedef SelfRefClassTypeParam #(int) self_int_t; T field; endclass class SelfRefClassIntParam #(int P=1); typedef SelfRefClassIntParam #(10) self_int_t; endclass Cls c12; Cls #(.PBASE(4)) c4; Cls8_t c8; Wrap #(.P(16)) w16; Wrap2 #(.P(32)) w32; SelfRefClassTypeParam src_logic; SelfRefClassTypeParam#()::self_int_t src_int; SelfRefClassIntParam src1; SelfRefClassIntParam#()::self_int_t src10; initial begin c12 = new; c4 = new; c8 = new; w16 = new; w32 = new; src_int = new; src_logic = new; src1 = new; src10 = new; if (Cls#()::PBASE != 12) $stop; if (Cls#(4)::PBASE != 4) $stop; if (Cls8_t::PBASE != 8) $stop; if (Cls#()::E_PBASE != 12) $stop; if (Cls#(4)::E_PBASE != 4) $stop; if (Cls8_t::E_PBASE != 8) $stop; if (c12.PBASE != 12) $stop; if (c4.PBASE != 4) $stop; if (c8.PBASE != 8) $stop; if (Cls#()::get_p() != 12) $stop; if (Cls#(4)::get_p() != 4) $stop; if (Cls8_t::get_p() != 8) $stop; if (c12.get_p() != 12) $stop; if (c4.get_p() != 4) $stop; if (c8.get_p() != 8) $stop; if (w16.get_p() != 16) $stop; if (w32.get_p() != 32) $stop; // verilator lint_off WIDTH c12.member = 32'haaaaaaaa; c4.member = 32'haaaaaaaa; c8.member = 32'haaaaaaaa; // verilator lint_on WIDTH if (c12.member != 12'haaa) $stop; if (c4.member != 4'ha) $stop; if (c12.get_member() != 12'haaa) $stop; if (c4.get_member() != 4'ha) $stop; `checkp(c12, "'{member:'haaa}"); `checkp(c4, "'{member:'ha}"); if ($bits(src_logic.field) != 1) $stop; if ($bits(src_int.field) != 32) $stop; if (src1.P != 1) $stop; if (src10.P != 10) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_var_pins_sc_uint_biguint.py0000755000542200017500000000347415101701376025064 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.pli_filename = "t/t_var_pinsizes.cpp" test.top_filename = "t/t_var_pinsizes.v" test.compile( verilator_flags2=["-sc --pins-sc-uint --pins-sc-biguint --trace-vcd --exe", test.pli_filename], make_main=False) def hgrep(re): test.file_grep(os.path.join(test.obj_dir, test.vm_prefix + ".h"), re) hgrep(r'sc_core::sc_in\s+&i1;') hgrep(r'sc_core::sc_in\s>\s+&i8;') hgrep(r'sc_core::sc_in\s>\s+&i16;') hgrep(r'sc_core::sc_in\s>\s+&i32;') hgrep(r'sc_core::sc_in\s>\s+&i64;') hgrep(r'sc_core::sc_in\s>\s+&i65;') hgrep(r'sc_core::sc_in\s>\s+&i128;') hgrep(r'sc_core::sc_in\s>\s+&i513;') hgrep(r'sc_core::sc_in\s>\s+&ibv1;') hgrep(r'sc_core::sc_in\s>\s+&ibv16;') hgrep(r'sc_core::sc_out\s+&o1;') hgrep(r'sc_core::sc_out\s>\s+&o8;') hgrep(r'sc_core::sc_out\s>\s+&o16;') hgrep(r'sc_core::sc_out\s>\s+&o32;') hgrep(r'sc_core::sc_out\s>\s+&o64;') hgrep(r'sc_core::sc_out\s>\s+&o65;') hgrep(r'sc_core::sc_out\s>\s+&o128;') hgrep(r'sc_core::sc_out\s>\s+&o513;') hgrep(r'sc_core::sc_out\s>\s+&obv1;') hgrep(r'sc_core::sc_out\s>\s+&obv16;') test.execute() test.passes() verilator-5.042/test_regress/t/t_dist_portability.py0000755000542200017500000000713515101701376023361 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') def line_filename(line): m = re.search(r'^([^:]+)', line) return m.group(1) if m else 'UNKNOWN' def printfll(): files = "src/*.c* src/*.h include/*.c* include/*.h examples/*/*.c* test_regress/t/*.c* test_regress/t/*.h" cmd = "cd " + test.root + " && fgrep -n ll " + files + " | sort" grep = test.run_capture(cmd, check=False) names = {} for line in grep.splitlines(): if not re.search(r'%[a-z0-9]*ll', line): continue if re.search(r'lintok-format-ll', line): continue print(line) names[line_filename(line)] = True if len(names): test.error("Files with %ll instead of PRIx64: " + ' '.join(sorted(names.keys()))) def cstr(): files = "src/*.c* src/*.h include/*.c* include/*.h examples/*/*.c* test_regress/t/*.c* test_regress/t/*.h" cmd = "cd " + test.root + " && grep -n -P 'c_str|begin|end' " + files + " | sort" grep = test.run_capture(cmd, check=False) names = {} for line in grep.splitlines(): if re.search(r'^([^:]+)[^"]*\(\)[a-z0-9_().->]*[.->]+(c_str|r?begin|r?end)\(\)', line): if re.search(r'lintok-begin-on-ref', line): continue print(line) names[line_filename(line)] = True if len(names): test.error("Files with potential c_str() lifetime issue: " + ' '.join(sorted(names.keys()))) def vsnprintf(): # Note do not do test_regress, as VPI files need to compile without verilatedos.h files = "src/*.c* src/*.h include/*.c* include/*.h examples/*/*.c*" cmd = "cd " + test.root + " && grep -n -P '(snprintf|vsnprintf)' " + files + " | sort" grep = test.run_capture(cmd, check=False) names = {} for line in grep.splitlines(): if re.search(r'\b(snprintf|vsnprintf)\b', line): if re.search(r'# *define\s*VL_V?SNPRINTF', line): continue print(line) names[line_filename(line)] = True if len(names): test.error("Files with vsnprintf, use VL_VSNPRINTF: " + ' '.join(sorted(names.keys()))) def final(): # Note do not do test_regress, as VPI files need to compile without verilatedos.h files = "src/*.c* src/*.h include/*.c* include/*.h" cmd = "cd " + test.root + " && grep -n -P '(class|struct)' " + files + " | sort" grep = test.run_capture(cmd, check=False) names = {} for line in grep.splitlines(): if re.search(r':\s*(class|struct) ', line): if (re.search(r'final|VL_NOT_FINAL', line) # or re.search(r'{}', line) # e.g. 'class Foo {};' or re.search(r';', line) # e.g. 'class Foo;' or re.search(r'(class|struct)\s+{', line) # e.g. anon 'class {' or re.search(r'struct std::', line) # or not re.search(r'{', line)): continue print(line) names[line_filename(line)] = True if len(names): test.error("Files with classes without final/VL_NOT_FINAL: " + ' '.join(sorted(names.keys()))) if not os.path.exists(test.root + "/.git"): test.skip("Not in a git repository") printfll() cstr() vsnprintf() final() test.passes() verilator-5.042/test_regress/t/t_preproc_eof_qqq_bad.v0000644000542200017500000000033515101701376023574 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 """str verilator-5.042/test_regress/t/t_lint_modport_dir_bad.out0000644000542200017500000000055415101701376024324 0ustar mahmoudyfreeshell%Error: t/t_lint_modport_dir_bad.v:26:20: Attempt to drive input-only modport: 'signal' : ... note: In instance 't.sub' 26 | assign dummy_in.signal = signal_i; | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_flag_parameter.vc0000644000542200017500000000150215101701376022712 0ustar mahmoudyfreeshell-Gstring1="\"New String\"" -pvalue+string2="\"New String\"" -Gstring11='"New String"' -pvalue+string12='"New String"' -Gstring21=\"New\ String\" -pvalue+string22=\"New\ String\" -Greal11=0.2 -pvalue+real12=0.2 -Greal21=4E2 -pvalue+real22=4e2 -Greal31=0.2e2 -pvalue+real32=0.2e2 -Greal41=0x123.4p1 -pvalue+real42=0X123.4P1 -Greal51=0x123p-1 -pvalue+real52=0X123P-1 -Gint11=0x10 -pvalue+int12=0x10 -Gint21=020 -pvalue+int22=020 -Gint31=123 -pvalue+int32=123 -Gint41=32'hdead_beef -pvalue+int42=32'hdead_beef -Gint51=32\'hdead_beef -pvalue+int52=32\'hdead_beef -Gint61="32'hdead_beef" -pvalue+int62="32'hdead_beef" -Gint71=-1000 -pvalue+int72=-1000 -Gbit0to0=0 -pvalue+bit0to0=0 -Gbit1to1=1 -pvalue+bit1to1=1 -Gbit0to1=1 -pvalue+bit0to1=1 -Gbit1to0=0 -pvalue+bit1to0=0 -Genum11=2'd2 -pvalue+enum12=2'd2 -Genum21=2'd3 -pvalue+enum22=2'd3 verilator-5.042/test_regress/t/t_varref_scope_in_interface.py0000755000542200017500000000075715101701376025163 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--lint-only", "--timing"]) test.passes() verilator-5.042/test_regress/t/t_class_to_basic_assignment_bad.v0000644000542200017500000000123515101701376025607 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Foo; int phase_done; static function Foo get(); Foo ans = new; return ans; endfunction static function int create (); return 3; endfunction function string get_name (); return "bar"; endfunction function void add(Foo phase); Foo new_node; if (new_node.get_name() == "run") begin new_node.phase_done = get(); end else begin new_node.phase_done = create(); end endfunction endclass verilator-5.042/test_regress/t/t_mem_cond.v0000644000542200017500000000103615101701376021361 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs b, // Inputs clk, en, a ); // bug1017 input clk; input en; input a[1]; output logic b[1]; always_ff @ (posedge clk) begin b <= en ? a : b; end always @ (posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_func_dotted_inl2.py0000755000542200017500000000177515101701376023222 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_func_dotted.v" out_filename = test.obj_dir + "/V" + test.name + ".tree.json" test.compile(v_flags2=["--no-json-edit-nums", '+define+ATTRIBUTES', '+define+USE_INLINE_MID']) if test.vlt_all: modps = test.file_grep( out_filename, r'{"type":"MODULE","name":"mb","addr":"([^"]*)","loc":"\w,99:[^"]*",.*"origName":"mb"') modp = modps[0][0] test.file_grep( out_filename, r'{"type":"CELL","name":"t.ma0.mb0","addr":"[^"]*","loc":"\w,87:[^"]*",.*"origName":"mb0",.*"modp":"([^"]*)"', modp) test.execute() test.passes() verilator-5.042/test_regress/t/t_incr_void.py0000755000542200017500000000101015101701376021732 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--fno-split -x-assign 0"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_nba_struct_array.v0000644000542200017500000000420115101701376023137 0ustar mahmoudyfreeshell // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module t(clk); input clk; logic [31:0] cyc = 0; always @(posedge clk) begin cyc <= cyc + 1; if (cyc == 99) begin $write("*-* All Finished *-*\n"); $finish; end end `define at_posedge_clk_on_cycle(n) always @(posedge clk) if (cyc == n) struct { int foo; int bar; } arr [2]; initial begin arr[0].foo = 0; arr[0].bar = 100; arr[1].foo = 0; arr[1].bar = 100; end `at_posedge_clk_on_cycle(0) begin for (int i = 0; i < 2; ++i) begin `checkh(arr[i].foo, 0); `checkh(arr[i].bar, 100); end end `at_posedge_clk_on_cycle(1) begin for (int i = 0; i < 2; ++i) begin `checkh(arr[i].foo, 0); `checkh(arr[i].bar, 100); end arr[0].foo <= 0; arr[0].bar <= -0; arr[1].foo <= 1; arr[1].bar <= -1; for (int i = 0; i < 2; ++i) begin `checkh(arr[i].foo, 0); `checkh(arr[i].bar, 100); end end `at_posedge_clk_on_cycle(2) begin for (int i = 0; i < 2; ++i) begin `checkh(arr[i].foo, i); `checkh(arr[i].bar, -i); end arr[0].foo <= ~0; arr[0].bar <= 0; arr[1].foo <= ~1; arr[1].bar <= 1; for (int i = 0; i < 2; ++i) begin `checkh(arr[i].foo, i); `checkh(arr[i].bar, -i); end end `at_posedge_clk_on_cycle(3) begin for (int i = 0; i < 2; ++i) begin `checkh(arr[i].foo, ~i); `checkh(arr[i].bar, i); end arr[0].foo <= -1; arr[0].bar <= -2; arr[1].foo <= -1; arr[1].bar <= -2; for (int i = 0; i < 2; ++i) begin `checkh(arr[i].foo, ~i); `checkh(arr[i].bar, i); end end `at_posedge_clk_on_cycle(4) begin for (int i = 0; i < 2; ++i) begin `checkh(arr[i].foo, -1); `checkh(arr[i].bar, -2); end end endmodule verilator-5.042/test_regress/t/t_foreach_class.v0000644000542200017500000000223215101701376022373 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2016 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); class Cls; int q[$]; function new(); q.push_back(1); q.push_back(2); q.push_back(3); endfunction endclass module t; int two[5:6]; if (1) begin : named Cls c; end function [63:0] crc(input [63:0] sum, input [31:0] a, input [31:0] b, input [31:0] c, input [31:0] d); crc = {sum[62:0],sum[63]} ^ {20'b0,a[7:0], 4'h0,b[7:0], 4'h0,c[7:0], 4'h0,d[7:0]}; endfunction bit [63:0] sum; initial begin named.c = new; sum = 0; foreach (named.c.q[i]) begin foreach (two[j]) begin // $display(i, j); sum = crc(sum, i, named.c.q[i], j, 0); end end `checkh(sum, 64'h000000a02d0fc000); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_func_redef.v0000644000542200017500000000113315101701376021676 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 function automatic integer min(input integer a, input integer b); return (a < b) ? a : b; endfunction module t #(parameter A=16, parameter B=8) (/*AUTOARG*/ // Outputs c, // Inputs a, b ); input [A-1:0] a; input [B-1:0] b; output logic [min(A,B)-1:0] c; always_comb for (int i = 0; i < min(A,B); i++) assign c[i] = a[i] | b[i]; endmodule verilator-5.042/test_regress/t/t_func_const2_bad.py0000755000542200017500000000076615101701376023030 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_const_number_unsized.v0000644000542200017500000000373315101701376024045 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0h exp=%0h\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t; int s; logic [255:0] n; initial begin s = $bits('d123); `checkd(s, 32); s = $bits('h123); `checkd(s, 32); s = $bits('o123); `checkd(s, 32); s = $bits('b101); `checkd(s, 32); // verilator lint_off WIDTHEXPAND // Used to warn "Too many digits for 32 bit number" // ... As that number was unsized ('...) it is limited to 32 bits // But other simulators don't warn, and language of (IEEE 1800-2023 5.7.1) // has been updated to accepting this legal n = 'd123456789123456789123456789; s = $bits('d123456789123456789123456789); `checkh(n, 256'h661efdf2e3b19f7c045f15); `checkd(s, 87); n = 'h123456789123456789123456789; s = $bits('h123456789123456789123456789); `checkh(n, 256'h123456789123456789123456789); `checkd(s, 108); //FIX octal digits in master test, if don't merge this n = 'o123456777123456777123456777; s = $bits('o123456777123456777123456777); `checkh(n, 256'h53977fca72eff94e5dff); `checkd(s, 81); n = 'b10101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010; s = $bits('b10101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010); `checkh(n, 256'haaaaaaaaaaaaaaaaaaaaaaa); `checkd(s, 92); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_bench_mux4k.py0000755000542200017500000000102415101701376022172 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=["--stats", test.wno_unopthreads_for_few_cores]) test.execute() test.passes() verilator-5.042/test_regress/t/t_order_clkinst.out0000644000542200017500000000304415101701376023005 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $var wire 1 # clk $end $scope module t $end $var wire 1 # clk $end $var wire 1 $ c1_start $end $var wire 32 % c1_count [31:0] $end $var wire 1 $ s2_start $end $var wire 32 & s2_count [31:0] $end $var wire 1 ' c3_start $end $var wire 32 ( c3_count [31:0] $end $var wire 8 ) cyc [7:0] $end $scope module c1 $end $var wire 1 $ start $end $var wire 32 % count [31:0] $end $var wire 32 * runnerm1 [31:0] $end $var wire 32 + runner [31:0] $end $upscope $end $scope module c3 $end $var wire 1 ' start $end $var wire 32 ( count [31:0] $end $var wire 32 , runnerm1 [31:0] $end $var wire 32 - runner [31:0] $end $upscope $end $scope module s2 $end $var wire 1 $ start $end $var wire 32 & count [31:0] $end $var wire 32 . runnerm1 [31:0] $end $var wire 32 / runner [31:0] $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 0# 0$ b00000000000000000000000000000000 % b00000000000000000000000000000000 & 0' b00000000000000000000000000000000 ( b00000000 ) b11111111111111111111111111111111 * b00000000000000000000000000000000 + b11111111111111111111111111111111 , b00000000000000000000000000000000 - b11111111111111111111111111111111 . b00000000000000000000000000000000 / #10 1# b00000001 ) #15 0# #20 1# 1$ b00000000000000000000000000000011 % b00000000000000000000000000000011 & 1' b00000000000000000000000000000011 ( b00000010 ) #25 0# #30 1# b00000011 ) #35 0# #40 1# b00000100 ) verilator-5.042/test_regress/t/t_math_synmul.v0000644000542200017500000000577215101701376022153 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg negate; reg enable; wire [31:0] datA = crc[31:0]; wire [31:0] datB = crc[63:32]; // Predict result wire [63:0] muled = (negate ? (-{32'h0, datA} * {32'h0, datB}) : ({32'h0, datA} * {32'h0, datB})); reg [63:0] muled_d1; reg [63:0] muled_d2; reg [63:0] muled_d3; reg [63:0] muled_d4; reg enable_d1; reg enable_d2; reg enable_d3; always @(posedge clk) enable_d1 <= enable; always @(posedge clk) enable_d2 <= enable_d1; always @(posedge clk) enable_d3 <= enable_d2; always @(posedge clk) if (enable) muled_d1 <= muled; always @(posedge clk) if (enable_d1) muled_d2 <= muled_d1; always @(posedge clk) if (enable_d2) muled_d3 <= muled_d2; always @(posedge clk) if (enable_d3) muled_d4 <= muled_d3; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [64:0] product_d4; // From test of t_math_synmul_mul.v // End of automatics t_math_synmul_mul test ( /*AUTOINST*/ // Outputs .product_d4 (product_d4[64:0]), // Inputs .clk (clk), .enable (enable), .negate (negate), .datA (datA[31:0]), .datB (datB[31:0])); integer cycs_enabled; initial cycs_enabled = 0; // Test loop always @(posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x e=%x n=%x a*b=%x synmul=%x\n", $time, cyc, crc, enable, negate, muled_d4, product_d4[63:0]); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; negate <= 1'b0; // Negation not currently supported // Always enable in low cycle counts to clear out the pipe //enable <= 1'b1; // 100% activity factor enable <= (cyc < 10 || cyc[4]); // 50% activity factor //enable <= (cyc<10 || cyc[4]&cyc[3]); // 25% activity factor if (enable) cycs_enabled = cycs_enabled + 1; if (cyc == 0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else begin if (product_d4[63:0] !== muled_d4) begin $write("[%0t] BAD product, got=%x exp=%x at cyc 0x%x\n", $time, product_d4[63:0], muled_d4, cyc); $stop; end if (cyc == 99) begin if (crc !== 64'hc77bb9b3784ea091) $stop; end `ifndef SIM_CYCLES `define SIM_CYCLES 99 `endif if (cyc == `SIM_CYCLES) begin $write("- Cycles=%0d, Activity factor=%0d%%\n", cyc, ((cycs_enabled * 100) / cyc)); $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.042/test_regress/t/t_class_static.py0000755000542200017500000000073415101701376022446 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_display_signed.py0000755000542200017500000000100015101701376022753 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_timing_initial_always.v0000644000542200017500000000072515101701376024164 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; wire sig; foo foo(sig); initial #1 begin $write("*-* All Finished *-*\n"); $finish(); end endmodule module foo(inout sig); reg cond = $c(0); always @(sig) begin if (cond) begin #1; $c(""); end end endmodule verilator-5.042/test_regress/t/t_case_nest.py0000755000542200017500000000073415101701376021736 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_unopt_converge_initial_run_bad.py0000755000542200017500000000122415101701376026225 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_unopt_converge_initial.v" test.compile(v_flags2=['+define+ALLOW_UNOPT', '--output-split 0', "-fno-dfg"]) if test.vlt_all: test.execute(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_func_v_noinl.py0000755000542200017500000000104215101701376022442 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_func_v.v" test.compile(v_flags2=['+define+T_FUNC_V_NOINL']) test.execute() test.passes() verilator-5.042/test_regress/t/t_opt_table_string.v0000644000542200017500000000143415101701376023141 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; string s; reg [2:0] cyc; initial cyc = 0; always @(posedge clk) cyc <= cyc + 1; always @* begin case (cyc) 3'b000: s = "case-0"; 3'b001: s = "case-1"; 3'b010: s = "case-2"; 3'b100: s = "case-4"; 3'b101: s = "case-5"; default: s = "default"; endcase end always @(posedge clk) begin $display("cyle %d = %s", cyc, s); if (cyc == 7) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_trace_two_hdr_sc.out0000644000542200017500000000364415101701376023462 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module topa $end $scope module t $end $var wire 1 # clk $end $var wire 32 $ cyc [31:0] $end $var wire 32 % c_trace_on [31:0] $end $scope module sub $end $var wire 32 & inside_sub_a [31:0] $end $upscope $end $upscope $end $upscope $end $scope module topb $end $scope module t $end $var wire 1 ( clk $end $var wire 32 + cyc [31:0] $end $var wire 32 , c_trace_on [31:0] $end $var real 64 ) r $end $scope module sub $end $var wire 32 - inside_sub_a [31:0] $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 0# b00000000000000000000000000000001 $ b00000000000000000000000000000000 % 0( r0 ) b00000000000000000000000000000001 & b00000000000000000000000000000001 + b00000000000000000000000000000000 , b00000000000000000000000000000010 - #10000 1# b00000000000000000000000000000010 $ b00000000000000000000000000000011 % 1( r0.1 ) #15000 0# 0( #20000 1# b00000000000000000000000000000011 $ b00000000000000000000000000000100 % 1( r0.2 ) #25000 0# 0( #30000 1# b00000000000000000000000000000100 $ b00000000000000000000000000000101 % 1( r0.3 ) #35000 0# 0( #40000 1# b00000000000000000000000000000101 $ b00000000000000000000000000000110 % 1( r0.4 ) #45000 0# 0( #50000 1# b00000000000000000000000000000110 $ b00000000000000000000000000000111 % 1( r0.5 ) #55000 0# 0( #60000 1# b00000000000000000000000000000111 $ b00000000000000000000000000001000 % 1( r0.6 ) #65000 0# 0( #70000 1# b00000000000000000000000000001000 $ b00000000000000000000000000001001 % 1( r0.7 ) #75000 0# 0( #80000 1# b00000000000000000000000000001001 $ b00000000000000000000000000001010 % 1( r0.7999999999999999 ) #85000 0# 0( #90000 1# b00000000000000000000000000001010 $ b00000000000000000000000000001011 % 1( r0.8999999999999999 ) #95000 0# 0( #100000 1# b00000000000000000000000000001011 $ b00000000000000000000000000001100 % 1( r0.9999999999999999 ) verilator-5.042/test_regress/t/t_interface_generic_positional.v0000644000542200017500000000106515101701376025477 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 interface inf; int v; endinterface module GenericModule (interface a, interface b); initial begin #1; if (a.v != 7) $stop; end endmodule module t; inf inf_inst[3](); GenericModule genericModule (.a(inf_inst[1]), .b(inf_inst[2])); initial begin inf_inst[1].v = 7; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_flag_supported_empty.out0000755000542200017500000000000115101701376024370 0ustar mahmoudyfreeshell verilator-5.042/test_regress/t/t_flag_parameter_bad.py0000755000542200017500000000122215101701376023542 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_flag_parameter.v" test.lint( fails=True, # It is not possible to put them into the options file v_flags2=['-GPARAM_THAT_DOES_NON_EXIST=1'], expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_sys_file_scan2.py0000755000542200017500000000073415101701376022675 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_inst_public.py0000755000542200017500000000117115101701376022301 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_make_gmake=False) test.file_grep(test.obj_dir + "/" + test.vm_prefix + "_Pub.h", r'') test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + "__Syms.h", r'Dead') test.passes() verilator-5.042/test_regress/t/t_event_class_fire.v0000644000542200017500000000073315101701376023116 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls; event e; task trig_e(); ->> e; endtask endclass module top(); event e; initial begin Cls c; c = new; c.trig_e(); wait(e.triggered); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_sys_file_autoflush.py0000755000542200017500000000115215101701376023674 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_sys_file_basic.v" test.compile(v_flags2=['+incdir+../include', '+define+AUTOFLUSH'], verilator_flags2=['--autoflush']) test.execute() test.passes() verilator-5.042/test_regress/t/t_opt_table_same.py0000755000542200017500000000130215101701376022740 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--stats"]) if test.vlt_all: test.file_grep(test.stats, r'Optimizations, Tables created\s+(\d+)', 2) test.file_grep(test.stats, r'ConstPool, Tables emitted\s+(\d+)', 1) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_array_pattern_2d.v0000644000542200017500000000242215101701376023040 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2009 by Iztok Jeras. // SPDX-License-Identifier: CC0-1.0 //bug991 module t; logic [31:0] array_assign [3:0]; logic [31:0] array_other [3:0]; logic [31:0] larray_assign [0:3]; logic [31:0] larray_other [0:3]; logic [31:0] array_neg [-1:1]; initial begin array_assign[0] = 32'd1; array_assign[3:1] = '{32'd4, 32'd3, 32'd2}; array_other[0] = array_assign[0]+10; array_other[3:1] = array_assign[3:1]; if (array_other[0] != 11) $stop; if (array_other[1] != 2) $stop; if (array_other[2] != 3) $stop; if (array_other[3] != 4) $stop; larray_assign[0] = 32'd1; larray_assign[1:3] = '{32'd4, 32'd3, 32'd2}; larray_other[0] = larray_assign[0]+10; larray_other[1:3] = larray_assign[1:3]; if (larray_other[0] != 11) $stop; if (larray_other[1] != 4) $stop; if (larray_other[2] != 3) $stop; if (larray_other[3] != 2) $stop; array_neg = '{-1: 5, 1: 7, default: 'd6}; if (array_neg[-1] != 5) $stop; if (array_neg[0] != 6) $stop; if (array_neg[1] != 7) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_select_bad_tri.v0000644000542200017500000000051715101701376022546 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg [72:1] in; initial begin if (in[( (1'h0 / 1'b0) )+:71] != 71'h0) $stop; end endmodule verilator-5.042/test_regress/t/t_func_bad.out0000644000542200017500000000346615101701376021714 0ustar mahmoudyfreeshell%Error: t/t_func_bad.v:9:11: Missing argument on non-defaulted argument 'from2' in function call to FUNC 'add' : ... note: In instance 't' 9 | if (add(3'd1) != 0) $stop; | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_func_bad.v:10:27: Too many arguments in function call to FUNC 'add' : ... note: In instance 't' 10 | if (add(3'd1, 3'd2, 3'd3) != 0) $stop; | ^~~~ %Error: t/t_func_bad.v:11:7: Missing argument on non-defaulted argument 'y' in function call to TASK 'x' : ... note: In instance 't' 11 | x; | ^ %Warning-WIDTHTRUNC: t/t_func_bad.v:11:7: Function output argument 'y' requires 1 bits, but connection's CONST '?32?h0' generates 32 bits. : ... note: In instance 't' 11 | x; | ^ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: t/t_func_bad.v:14:17: No such argument 'no_such' in function call to FUNC 'f' : ... note: In instance 't' 14 | f(.j(1), .no_such(2)); | ^~~~~~~ %Error: t/t_func_bad.v:15:19: Duplicate argument 'dup' in function call to FUNC 'f' : ... note: In instance 't' 15 | f(.dup(1), .dup(3)); | ^~~ %Error: t/t_func_bad.v:16:13: Too many arguments in function call to FUNC 'f' : ... note: In instance 't' 16 | f(1,2,3); | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_timing_dynscope.py0000755000542200017500000000077115101701376023166 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_timing_func_bad.out0000644000542200017500000000270215101701376023253 0ustar mahmoudyfreeshell%Error: t/t_timing_func_bad.v:10:7: Delays are not legal in functions. Suggest use a task (IEEE 1800-2023 13.4.4) : ... note: In instance 't' 10 | #1 $stop; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_timing_func_bad.v:15:12: Timing controls are not legal in functions. Suggest use a task (IEEE 1800-2023 13.4.4) : ... note: In instance 't' 15 | f2 = #5 0; $stop; | ^ %Error: t/t_timing_func_bad.v:20:7: Event controls are not legal in functions. Suggest use a task (IEEE 1800-2023 13.4.4) : ... note: In instance 't' 20 | @e $stop; | ^ %Error: t/t_timing_func_bad.v:25:12: Timing controls are not legal in functions. Suggest use a task (IEEE 1800-2023 13.4.4) : ... note: In instance 't' 25 | f4 = @e 0; $stop; | ^ %Error: t/t_timing_func_bad.v:31:7: Wait statements are not legal in functions. Suggest use a task (IEEE 1800-2023 13.4.4) : ... note: In instance 't' 31 | wait(i == 0) $stop; | ^~~~ %Error: t/t_timing_func_bad.v:42:7: Delays are not legal in final blocks (IEEE 1800-2023 9.2.3) : ... note: In instance 't' 42 | #1; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_pp_line.out0000644000542200017500000000154215101701376021572 0ustar mahmoudyfreeshell-Info: some file:100:1: aaaaaaaa file='some file' : ... note: In instance 't' 100 | $info("aaaaaaaa file='%s'", "some file"); | ^~~~~ -Info: some file:101:1: bbbbbbbb file='some file' : ... note: In instance 't' 101 | $info("bbbbbbbb file='%s'", "some file"); | ^~~~~ -Info: somefile.v:200:1: cccccccc file='somefile.v' : ... note: In instance 't' 200 | $info("cccccccc file='%s'", "somefile.v"); | ^~~~~ -Info: /a/somefile.v:300:1: dddddddd file='/a/somefile.v' : ... note: In instance 't' 300 | $info("dddddddd file='%s'", "/a/somefile.v"); | ^~~~~ -Info: C:\a\somefile.v:400:1: eeeeeeee file='C:\a\somefile.v' : ... note: In instance 't' 400 | $info("eeeeeeee file='%s'", "C:\\a\\somefile.v"); | ^~~~~ verilator-5.042/test_regress/t/t_param_mintypmax.py0000755000542200017500000000073415101701376023200 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_generic_modport_param.py0000755000542200017500000000077115101701376026353 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--timing']) test.execute() test.passes() verilator-5.042/test_regress/t/t_unroll_pragma_full.py0000755000542200017500000000153615101701376023657 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_unroll_pragma.v" test.compile(verilator_flags2=['--unroll-count 4 --unroll-stmts 9999 --stats -DTEST_FULL'], verilator_make_gmake=False, make_top_shell=False, make_main=False) test.file_grep(test.stats, r'Optimizations, Loop unrolling, Unrolled loops\s+(\d+)', 9) test.file_grep(test.stats, r'Optimizations, Loop unrolling, Unrolled iterations\s+(\d+)', 45) test.passes() verilator-5.042/test_regress/t/t_clk_scope_bad.py0000755000542200017500000000070615101701376022541 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.042/test_regress/t/t_trace_saif_cmake.py0000755000542200017500000000122715101701376023230 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_trace_fst_cmake.v" test.compile(v_flags2=["--trace-saif"], verilator_make_gmake=False, verilator_make_cmake=True) test.execute() test.saif_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_trace_array_saif.out0000644000542200017500003645344015101701376023463 0ustar mahmoudyfreeshell// Generated by verilated_saif (SAIFILE (SAIFVERSION "2.0") (DIRECTION "backward") (PROGRAM_NAME "Verilator") (DIVIDER / ) (TIMESCALE 1ps) (DURATION 60) (INSTANCE top (NET (clk (T0 35) (T1 25) (TZ 0) (TX 0) (TB 0) (TC 11)) ) (INSTANCE t (NET (clk (T0 35) (T1 25) (TZ 0) (TX 0) (TB 0) (TC 11)) (cyc\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6)) (cyc\[1\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3)) (cyc\[2\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE biggie (NET (d\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1\] (T0 50) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 2)) (d\[2\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2)) (d\[3\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 2)) (d\[4\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 2)) (d\[5\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 2)) (d\[6\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 3)) (d\[7\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 3)) (d\[8\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3)) (d\[9\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 4)) (d\[10\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 4)) (d\[11\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 5)) (d\[12\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 5)) (d\[13\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4)) (d\[14\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3)) (d\[15\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 2)) (d\[16\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (d\[17\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) (d\[18\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3)) (d\[19\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3)) (d\[20\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 3)) (d\[21\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 5)) (d\[22\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4)) (d\[23\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3)) (d\[24\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 3)) (d\[25\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4)) (d\[26\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3)) (d\[27\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3)) (d\[28\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3)) (d\[29\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 2)) (d\[30\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (d\[31\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) (d\[32\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1)) (d\[33\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1)) (d\[34\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (d\[35\] (T0 50) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1)) (d\[36\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) (d\[37\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[1999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[2999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[3999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[4999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[5999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[6999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[7999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[8999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[9999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[10999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[11999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[12999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[13999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[14999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[15999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[16999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[17999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[18999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[19999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[20999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[21999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[22999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[23999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[24999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[25999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[26999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[27999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[28999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[29999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[30999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[31999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[32999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[33999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[34999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[35999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[36999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[37999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[38999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[39999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[40999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[41999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[42999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[43999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[44999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[45999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[46999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[47999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[48999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[49999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[50999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[51999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[52999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[53999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[54999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[55999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[56999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[57999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[58999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[59999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[60999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[61999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[62999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[63999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[64999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[65999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[66999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[67999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[68999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[69999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[70999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[71999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[72999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[73999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[74999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[75999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[76999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[77999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[78999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[79999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[80999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[81999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[82999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[83999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[84999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[85999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[86999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[87999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[88999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[89999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[90999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[91999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[92999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[93999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[94999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[95999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[96999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[97999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[98999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[99999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[100999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[101999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[102999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[103999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[104999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[105999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[106999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[107999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[108999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[109999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[110999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[111999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[112999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[113999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[114999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[115999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[116999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[117999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[118999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[119999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[120999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[121999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[122999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[123999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[124999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[125999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[126999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[127999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[128999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[129999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130073\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130074\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130075\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130076\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130077\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130078\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130079\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130080\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130081\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130082\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130083\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130084\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130085\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130086\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130087\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130088\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130089\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130090\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130091\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130092\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130093\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130094\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130095\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130096\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130097\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130098\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130099\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130100\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130101\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130102\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130103\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130104\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130105\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130106\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130107\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130108\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130109\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130110\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130111\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130112\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130113\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130114\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130115\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130116\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130117\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130118\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130119\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130120\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130121\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130122\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130123\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130124\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130125\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130126\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130127\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130128\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130129\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130130\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130131\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130132\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130133\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130134\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130135\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130136\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130137\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130138\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130139\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130140\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130141\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130142\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130143\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130144\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130145\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130146\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130147\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130148\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130149\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130150\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130151\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130152\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130153\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130154\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130155\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130156\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130157\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130158\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130159\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130160\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130161\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130162\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130163\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130164\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130165\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130166\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130167\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130168\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130169\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130170\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130171\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130172\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130173\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130174\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130175\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130176\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130177\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130178\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130179\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130180\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130181\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130182\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130183\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130184\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130185\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130186\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130187\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130188\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130189\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130190\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130191\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130192\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130193\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130194\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130195\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130196\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130197\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130198\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130199\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130200\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130201\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130202\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130203\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130204\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130205\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130206\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130207\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130208\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130209\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130210\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130211\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130212\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130213\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130214\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130215\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130216\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130217\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130218\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130219\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130220\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130221\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130222\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130223\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130224\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130225\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130226\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130227\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130228\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130229\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130230\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130231\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130232\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130233\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130234\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130235\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130236\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130237\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130238\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130239\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130240\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130241\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130242\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130243\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130244\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130245\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130246\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130247\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130248\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130249\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130250\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130251\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130252\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130253\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130254\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130255\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130256\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130257\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130258\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130259\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130260\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130261\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130262\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130263\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130264\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130265\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130266\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130267\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130268\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130269\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130270\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130271\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130272\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130273\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130274\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130275\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130276\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130277\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130278\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130279\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130280\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130281\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130282\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130283\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130284\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130285\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130286\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130287\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130288\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130289\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130290\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130291\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130292\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130293\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130294\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130295\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130296\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130297\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130298\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130299\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130300\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130301\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130302\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130303\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130304\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130305\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130306\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130307\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130308\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130309\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130310\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130311\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130312\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130313\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130314\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130315\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130316\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130317\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130318\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130319\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130320\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130321\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130322\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130323\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130324\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130325\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130326\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130327\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130328\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130329\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130330\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130331\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130332\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130333\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130334\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130335\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130336\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130337\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130338\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130339\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130340\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130341\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130342\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130343\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130344\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130345\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130346\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130347\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130348\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130349\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130350\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130351\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130352\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130353\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130354\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130355\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130356\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130357\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130358\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130359\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130360\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130361\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130362\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130363\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130364\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130365\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130366\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130367\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130368\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130369\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130370\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130371\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130372\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130373\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130374\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130375\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130376\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130377\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130378\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130379\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130380\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130381\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130382\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130383\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130384\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130385\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130386\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130387\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130388\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130389\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130390\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130391\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130392\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130393\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130394\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130395\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130396\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130397\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130398\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130399\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130400\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130401\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130402\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130403\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130404\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130405\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130406\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130407\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130408\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130409\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130410\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130411\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130412\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130413\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130414\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130415\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130416\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130417\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130418\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130419\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130420\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130421\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130422\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130423\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130424\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130425\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130426\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130427\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130428\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130429\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130430\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130431\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130432\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130433\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130434\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130435\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130436\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130437\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130438\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130439\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130440\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130441\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130442\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130443\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130444\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130445\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130446\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130447\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130448\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130449\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130450\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130451\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130452\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130453\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130454\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130455\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130456\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130457\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130458\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130459\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130460\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130461\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130462\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130463\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130464\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130465\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130466\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130467\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130468\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130469\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130470\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130471\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130472\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130473\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130474\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130475\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130476\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130477\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130478\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130479\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130480\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130481\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130482\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130483\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130484\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130485\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130486\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130487\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130488\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130489\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130490\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130491\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130492\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130493\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130494\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130495\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130496\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130497\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130498\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130499\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130500\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130501\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130502\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130503\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130504\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130505\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130506\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130507\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130508\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130509\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130510\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130511\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130512\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130513\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130514\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130515\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130516\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130517\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130518\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130519\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130520\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130521\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130522\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130523\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130524\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130525\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130526\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130527\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130528\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130529\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130530\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130531\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130532\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130533\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130534\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130535\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130536\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130537\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130538\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130539\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130540\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130541\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130542\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130543\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130544\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130545\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130546\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130547\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130548\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130549\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130550\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130551\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130552\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130553\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130554\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130555\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130556\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130557\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130558\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130559\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130560\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130561\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130562\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130563\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130564\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130565\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130566\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130567\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130568\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130569\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130570\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130571\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130572\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130573\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130574\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130575\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130576\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130577\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130578\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130579\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130580\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130581\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130582\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130583\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130584\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130585\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130586\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130587\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130588\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130589\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130590\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130591\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130592\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130593\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130594\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130595\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130596\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130597\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130598\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130599\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130600\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130601\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130602\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130603\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130604\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130605\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130606\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130607\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130608\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130609\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130610\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130611\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130612\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130613\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130614\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130615\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130616\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130617\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130618\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130619\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130620\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130621\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130622\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130623\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130624\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130625\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130626\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130627\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130628\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130629\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130630\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130631\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130632\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130633\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130634\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130635\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130636\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130637\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130638\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130639\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130640\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130641\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130642\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130643\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130644\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130645\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130646\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130647\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130648\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130649\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130650\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130651\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130652\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130653\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130654\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130655\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130656\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130657\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130658\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130659\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130660\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130661\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130662\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130663\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130664\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130665\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130666\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130667\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130668\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130669\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130670\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130671\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130672\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130673\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130674\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130675\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130676\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130677\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130678\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130679\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130680\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130681\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130682\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130683\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130684\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130685\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130686\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130687\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130688\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130689\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130690\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130691\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130692\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130693\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130694\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130695\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130696\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130697\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130698\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130699\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130700\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130701\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130702\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130703\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130704\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130705\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130706\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130707\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130708\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130709\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130710\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130711\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130712\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130713\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130714\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130715\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130716\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130717\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130718\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130719\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130720\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130721\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130722\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130723\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130724\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130725\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130726\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130727\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130728\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130729\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130730\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130731\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130732\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130733\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130734\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130735\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130736\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130737\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130738\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130739\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130740\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130741\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130742\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130743\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130744\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130745\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130746\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130747\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130748\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130749\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130750\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130751\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130752\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130753\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130754\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130755\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130756\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130757\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130758\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130759\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130760\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130761\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130762\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130763\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130764\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130765\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130766\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130767\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130768\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130769\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130770\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130771\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130772\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130773\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130774\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130775\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130776\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130777\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130778\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130779\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130780\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130781\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130782\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130783\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130784\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130785\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130786\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130787\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130788\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130789\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130790\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130791\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130792\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130793\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130794\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130795\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130796\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130797\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130798\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130799\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130800\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130801\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130802\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130803\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130804\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130805\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130806\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130807\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130808\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130809\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130810\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130811\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130812\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130813\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130814\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130815\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130816\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130817\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130818\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130819\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130820\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130821\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130822\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130823\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130824\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130825\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130826\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130827\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130828\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130829\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130830\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130831\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130832\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130833\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130834\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130835\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130836\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130837\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130838\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130839\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130840\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130841\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130842\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130843\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130844\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130845\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130846\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130847\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130848\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130849\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130850\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130851\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130852\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130853\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130854\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130855\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130856\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130857\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130858\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130859\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130860\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130861\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130862\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130863\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130864\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130865\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130866\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130867\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130868\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130869\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130870\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130871\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130872\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130873\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130874\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130875\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130876\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130877\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130878\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130879\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130880\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130881\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130882\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130883\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130884\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130885\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130886\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130887\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130888\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130889\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130890\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130891\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130892\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130893\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130894\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130895\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130896\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130897\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130898\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130899\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130900\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130901\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130902\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130903\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130904\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130905\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130906\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130907\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130908\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130909\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130910\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130911\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130912\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130913\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130914\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130915\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130916\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130917\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130918\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130919\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130920\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130921\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130922\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130923\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130924\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130925\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130926\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130927\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130928\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130929\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130930\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130931\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130932\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130933\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130934\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130935\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130936\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130937\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130938\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130939\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130940\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130941\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130942\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130943\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130944\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130945\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130946\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130947\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130948\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130949\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130950\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130951\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130952\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130953\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130954\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130955\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130956\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130957\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130958\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130959\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130960\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130961\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130962\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130963\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130964\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130965\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130966\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130967\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130968\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130969\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130970\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130971\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130972\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130973\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130974\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130975\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130976\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130977\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130978\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130979\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130980\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130981\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130982\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130983\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130984\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130985\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130986\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130987\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130988\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130989\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130990\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130991\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130992\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130993\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130994\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130995\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130996\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130997\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130998\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[130999\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131000\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131001\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131002\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131003\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131004\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131005\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131006\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131007\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131008\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131009\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131010\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131011\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131012\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131013\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131014\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131015\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131016\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131017\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131018\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131019\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131020\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131021\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131022\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131023\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131024\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131025\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131026\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131027\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131028\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131029\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131030\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131031\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131032\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131033\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131034\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131035\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131036\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131037\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131038\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131039\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131040\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131041\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131042\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131043\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131044\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131045\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131046\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131047\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131048\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131049\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131050\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131051\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131052\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131053\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131054\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131055\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131056\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131057\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131058\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131059\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131060\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131061\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131062\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131063\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131064\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131065\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131066\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131067\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131068\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131069\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131070\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131071\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (d\[131072\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) ) verilator-5.042/test_regress/t/t_sys_rand_concat.py0000755000542200017500000000115315101701376023137 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() for filename in test.glob_some(test.obj_dir + "/" + test.vm_prefix + "___024root__*__Slow.cpp"): test.file_grep_not(filename, r'(<<|>>)') test.passes() verilator-5.042/test_regress/t/t_time_print.out0000644000542200017500000000061515101701376022316 0ustar mahmoudyfreeshell[0] In top.t: Hi Time scale of t is 1ns / 1ps Time scale of t is 1ns / 1ps Time scale of t is 1ns / 1ps Time: ' 0' 10ns=10000 Time: ' 0-my-ms' 10ns=0-my-ms Time: ' 0.0-my-ms' 10ns=0.0-my-ms Time: ' 0.00-my-us' 10ns=0.01-my-us Time: ' 0.000-my-ns' 10ns=10.000-my-ns Time: ' 0.000-my-ps' 10ns=10000.000-my-ps Time: ' 0.0000-my-fs' 10ns=10000000.0000-my-fs *-* All Finished *-* verilator-5.042/test_regress/t/t_stack_check.py0000755000542200017500000000100715101701376022226 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=['--binary --debug-stack-check']) test.execute() test.passes() verilator-5.042/test_regress/t/t_process.out0000644000542200017500000000005215101701376021615 0ustar mahmoudyfreeshell'{m_process:process} *-* All Finished *-* verilator-5.042/test_regress/t/t_enum_bad_hide.out0000644000542200017500000000115215101701376022704 0ustar mahmoudyfreeshell%Warning-VARHIDDEN: t/t_enum_bad_hide.v:11:19: Declaration of enum value hides declaration in upper scope: HIDE_VALUE 11 | typedef enum { HIDE_VALUE = 0 } hide_enum_t; | ^~~~~~~~~~ t/t_enum_bad_hide.v:7:16: ... Location of original declaration 7 | typedef enum { HIDE_VALUE = 0 } hide_enum_t; | ^~~~~~~~~~ ... For warning description see https://verilator.org/warn/VARHIDDEN?v=latest ... Use "/* verilator lint_off VARHIDDEN */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_enum_recurse_bad2.v0000644000542200017500000000043215101701376023163 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef enum foo_t; typedef enum foo_t { A = 'b0, B = 'b1 } foo_t; verilator-5.042/test_regress/t/t_wait_const.v0000644000542200017500000000104115101701376021746 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin // This test is separate from t_wait.v because we needed a process with // just one wait of a non-zero to see a bug where GCC gave "return value // not used" // verilator lint_off WAITCONST wait (1); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_clocking_inout.v0000644000542200017500000000176315101701376022616 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; bit clk = 0, foo = 0, bar = 0; always #5 clk = ~clk; clocking cb @(posedge clk); input #11 output #2 foo; inout bar; endclocking initial begin cb.foo <= 1; cb.bar <= 1; if (foo != 0 || cb.foo != 0) $stop; if (bar != 0 || cb.bar != 0) $stop; @(posedge bar) if ($time != 5) $stop; if (foo != 0 || cb.foo != 0) $stop; if (cb.bar != 0) $stop; #1 if (foo != 0 || cb.foo != 0) $stop; if (cb.bar != 1) $stop; @(posedge foo) if ($time != 7) $stop; if (cb.foo != 0) $stop; #9 // $time == 16 if (cb.foo != 0) $stop; #10 // $time == 26 if (cb.foo != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_math_shift_side.v0000644000542200017500000000136115101701376022733 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls; int m_n_bits; function int get_n_bytes; return ((m_n_bits - 1) / 8) + 1; endfunction endclass module t; int i; initial begin Cls c; c = new; c.m_n_bits = 23; if (c.get_n_bytes() != 3) $stop; i = 1 << c.get_n_bytes(); if (i != 8) $stop; i = 32'h1234 >> c.get_n_bytes(); if (i != 32'h246) $stop; i = 32'shffffffff >>> c.get_n_bytes(); if (i != 32'hffffffff) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_var_bad_sv.py0000755000542200017500000000077615101701376022106 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_var_sc_double.py0000755000542200017500000000113015101701376022570 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename, "--sc -fno-inline"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_math_pow.v0000644000542200017500000003141015101701376021415 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" `define stop $stop `ifdef VERILATOR `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) `else `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); end while(0) `endif module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [66:0] a; reg [66:0] b; wire [15:0] aui = a[15:0]; wire [34:0] auq = a[34:0]; wire [66:0] auw = a[66:0]; wire [15:0] bui = b[15:0]; wire [34:0] buq = b[34:0]; wire [66:0] buw = b[66:0]; wire signed [15:0] asi = a[15:0]; wire signed [34:0] asq = a[34:0]; wire signed [66:0] asw = a[66:0]; wire signed [15:0] bsi = b[15:0]; wire signed [34:0] bsq = b[34:0]; wire signed [66:0] bsw = b[66:0]; // verilator lint_off WIDTH wire [66:0] shifted = 32'd2 ** b[20:0]; wire [66:0] shifted_signed = 32'sd2 ** b[20:0]; wire [15:0] uiii = aui ** bui; wire [15:0] uiiq = aui ** buq; wire [15:0] uiiw = aui ** buw; wire [15:0] uiqi = auq ** bui; wire [15:0] uiqq = auq ** buq; wire [15:0] uiqw = auq ** buw; wire [15:0] uiwi = auw ** bui; wire [15:0] uiwq = auw ** buq; wire [15:0] uiww = auw ** buw; wire [34:0] uqii = aui ** bui; wire [34:0] uqiq = aui ** buq; wire [34:0] uqiw = aui ** buw; wire [34:0] uqqi = auq ** bui; wire [34:0] uqqq = auq ** buq; wire [34:0] uqqw = auq ** buw; wire [34:0] uqwi = auw ** bui; wire [34:0] uqwq = auw ** buq; wire [34:0] uqww = auw ** buw; wire [66:0] uwii = aui ** bui; wire [66:0] uwiq = aui ** buq; wire [66:0] uwiw = aui ** buw; wire [66:0] uwqi = auq ** bui; wire [66:0] uwqq = auq ** buq; wire [66:0] uwqw = auq ** buw; wire [66:0] uwwi = auw ** bui; wire [66:0] uwwq = auw ** buq; wire [66:0] uwww = auw ** buw; wire signed [15:0] siii = asi ** bsi; wire signed [15:0] siiq = asi ** bsq; wire signed [15:0] siiw = asi ** bsw; wire signed [15:0] siqi = asq ** bsi; wire signed [15:0] siqq = asq ** bsq; wire signed [15:0] siqw = asq ** bsw; wire signed [15:0] siwi = asw ** bsi; wire signed [15:0] siwq = asw ** bsq; wire signed [15:0] siww = asw ** bsw; wire signed [34:0] sqii = asi ** bsi; wire signed [34:0] sqiq = asi ** bsq; wire signed [34:0] sqiw = asi ** bsw; wire signed [34:0] sqqi = asq ** bsi; wire signed [34:0] sqqq = asq ** bsq; wire signed [34:0] sqqw = asq ** bsw; wire signed [34:0] sqwi = asw ** bsi; wire signed [34:0] sqwq = asw ** bsq; wire signed [34:0] sqww = asw ** bsw; wire signed [66:0] swii = asi ** bsi; wire signed [66:0] swiq = asi ** bsq; wire signed [66:0] swiw = asi ** bsw; wire signed [66:0] swqi = asq ** bsi; wire signed [66:0] swqq = asq ** bsq; wire signed [66:0] swqw = asq ** bsw; wire signed [66:0] swwi = asw ** bsi; wire signed [66:0] swwq = asw ** bsq; wire signed [66:0] swww = asw ** bsw; // verilator lint_on WIDTH task checkpow(input [66:0] ures, input signed [66:0] sres); `ifdef TEST_VERBOSE $write("- lastcyc%0d: %0x**%0x = %0x (exp %0x)\n", last_cyc, a, b, uwww, ures); `endif // verilator lint_off WIDTH `checkh(uiii, ures[15:0]); `checkh(uiiq, ures[15:0]); `checkh(uiiw, ures[15:0]); `checkh(uiqi, ures[15:0]); `checkh(uiqq, ures[15:0]); `checkh(uiqw, ures[15:0]); `checkh(uiwi, ures[15:0]); `checkh(uiwq, ures[15:0]); `checkh(uiww, ures[15:0]); `checkh(uqii, ures[15:0]); `checkh(uqiq, ures[15:0]); `checkh(uqiw, ures[15:0]); `checkh(uqqi, ures[34:0]); `checkh(uqqq, ures[34:0]); `checkh(uqqw, ures[34:0]); `checkh(uqwi, ures[34:0]); `checkh(uqwq, ures[34:0]); `checkh(uqww, ures[34:0]); `checkh(uwii, ures[15:0]); `checkh(uwiq, ures[15:0]); `checkh(uwiw, ures[15:0]); `checkh(uwqi, ures[34:0]); `checkh(uwqq, ures[34:0]); `checkh(uwqw, ures[34:0]); `checkh(uwwi, ures[66:0]); `checkh(uwwq, ures[66:0]); `checkh(uwww, ures[66:0]); `ifdef TEST_VERBOSE $write("- lastcyc%0d: %0d**%0d = signed %0d (exp %0d)\n", last_cyc, asw, bsw, swww, sres); `endif // verilator lint_off WIDTH `checkh(siii, sres[15:0]); `checkh(siiq, sres[15:0]); `checkh(siiw, sres[15:0]); `checkh(siqi, sres[15:0]); `checkh(siqq, sres[15:0]); `checkh(siqw, sres[15:0]); `checkh(siwi, sres[15:0]); `checkh(siwq, sres[15:0]); `checkh(siww, sres[15:0]); `checkh(sqii, sres[34:0]); `checkh(sqiq, sres[34:0]); `checkh(sqiw, sres[34:0]); `checkh(sqqi, sres[34:0]); `checkh(sqqq, sres[34:0]); `checkh(sqqw, sres[34:0]); `checkh(sqwi, sres[34:0]); `checkh(sqwq, sres[34:0]); `checkh(sqww, sres[34:0]); `checkh(swii, sres[66:0]); `checkh(swiq, sres[66:0]); `checkh(swiw, sres[66:0]); `checkh(swqi, sres[66:0]); `checkh(swqq, sres[66:0]); `checkh(swqw, sres[66:0]); `checkh(swwi, sres[66:0]); `checkh(swwq, sres[66:0]); `checkh(swww, sres[66:0]); // verilator lint_on WIDTH endtask `define goldoneu(vu) \ $write("gold: u %0x**%0x: %s = %0x\n", auw, buw, `STRINGIFY(vu), vu); `define goldones(vs) \ $write("gold: s %0d**%0d: %s = %0d\n", asw, bsw, `STRINGIFY(vs), vs); task golddump(); // verilator lint_off WIDTH `goldoneu(uiii); `goldoneu(uiiq); `goldoneu(uiiw); `goldoneu(uiqi); `goldoneu(uiqq); `goldoneu(uiqw); `goldoneu(uiwi); `goldoneu(uiwq); `goldoneu(uiww); `goldoneu(uqii); `goldoneu(uqiq); `goldoneu(uqiw); `goldoneu(uqqi); `goldoneu(uqqq); `goldoneu(uqqw); `goldoneu(uqwi); `goldoneu(uqwq); `goldoneu(uqww); `goldoneu(uwii); `goldoneu(uwiq); `goldoneu(uwiw); `goldoneu(uwqi); `goldoneu(uwqq); `goldoneu(uwqw); `goldoneu(uwwi); `goldoneu(uwwq); `goldoneu(uwww); `goldones(siii); `goldones(siiq); `goldones(siiw); `goldones(siqi); `goldones(siqq); `goldones(siqw); `goldones(siwi); `goldones(siwq); `goldones(siww); `goldones(sqii); `goldones(sqiq); `goldones(sqiw); `goldones(sqqi); `goldones(sqqq); `goldones(sqqw); `goldones(sqwi); `goldones(sqwq); `goldones(sqww); `goldones(swii); `goldones(swiq); `goldones(swiw); `goldones(swqi); `goldones(swqq); `goldones(swqw); `goldones(swwi); `goldones(swwq); `goldones(swww); // verilator lint_on WIDTH endtask integer cyc; initial cyc=1; integer last_cyc; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; last_cyc <= cyc; `ifdef TEST_VERBOSE $write("- cyc%0d: %0x**%0x = sh %0x\n", cyc, a, b, shifted); `endif // Constant versions `checkh(67'h0 ** 21'h0, 67'h1); `checkh(67'h1 ** 21'h0, 67'h1); `checkh(67'h2 ** 21'h0, 67'h1); `checkh(67'h0 ** 21'h1, 67'h0); `checkh(67'h0 ** 21'h4, 67'h0); `checkh(67'h1 ** 21'h31, 67'h1); `checkh(67'h2 ** 21'h10, 67'h10000); `checkh(67'd10 ** 21'h3, 67'h3e8); `checkh(67'h3 ** 21'h7, 67'h88b); `checkh(67'h0 ** 21'h0, 67'h1); `checkh(67'sh0 ** 21'sh0, 67'sh1); `checkh(67'h10 ** 21'h0, 67'h1); `ifndef VCS `checkh(61'h7ab3811219 ** 21'ha6e30, 61'h01ea58c703687e81); `endif if (cyc==0) begin end else if (cyc==1) begin a <= 67'h0; b <= 67'h0; end else if (cyc==2) begin a <= 67'h0; b <= 67'h3; end else if (cyc==3) begin a <= 67'h1; b <= 67'h31; end else if (cyc==4) begin a <= 67'h2; b <= 67'h10; end else if (cyc==5) begin a <= 67'd10; b <= 67'd3; end else if (cyc==6) begin a <= 67'd3; b <= 67'd7; end else if (cyc==7) begin a <= 67'h7ab3811219; b <= 67'ha6e30; end else if (cyc==10) begin a <= 67'h0; b <= 67'h0; end else if (cyc==11) begin a <= 67'h0; b <= 67'h1; end else if (cyc==12) begin a <= 67'h0; b <= -67'h1; end else if (cyc==13) begin a <= 67'h0; b <= 67'h2; end else if (cyc==14) begin a <= 67'h0; b <= 67'h3; end else if (cyc==20) begin a <= 67'h1; b <= 67'h0; end else if (cyc==21) begin a <= 67'h1; b <= 67'h1; end else if (cyc==22) begin a <= 67'h1; b <= -67'h1; end else if (cyc==23) begin a <= 67'h1; b <= 67'h2; end else if (cyc==24) begin a <= 67'h1; b <= 67'h3; end else if (cyc==30) begin a <= -67'h1; b <= 67'h0; end else if (cyc==31) begin a <= -67'h1; b <= 67'h1; end else if (cyc==32) begin a <= -67'h1; b <= -67'h1; end else if (cyc==33) begin a <= -67'h1; b <= 67'h2; end else if (cyc==34) begin a <= -67'h1; b <= 67'h3; end else if (cyc==40) begin a <= 67'h2; b <= 67'h0; end else if (cyc==41) begin a <= 67'h2; b <= 67'h1; end else if (cyc==42) begin a <= 67'h2; b <= -67'h1; end else if (cyc==43) begin a <= 67'h2; b <= 67'h2; end else if (cyc==44) begin a <= 67'h2; b <= 67'h3; end else if (cyc==50) begin a <= 67'h3; b <= 67'h0; end else if (cyc==51) begin a <= 67'h3; b <= 67'h1; end else if (cyc==52) begin a <= 67'h3; b <= -67'h1; end else if (cyc==53) begin a <= 67'h3; b <= 67'h2; end else if (cyc==54) begin a <= 67'h3; b <= 67'h3; end else if (cyc==60) begin a <= -67'h2; b <= 67'h0; end else if (cyc==61) begin a <= -67'h2; b <= 67'h1; end else if (cyc==62) begin a <= -67'h2; b <= -67'h1; end else if (cyc==63) begin a <= -67'h2; b <= 67'h2; end else if (cyc==64) begin a <= -67'h2; b <= 67'h3; end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end // IEEE: // op1 < -1 op1 == -1 op1 == 0 op1 == 1 op1 > 1 // op2 is positive op1 ** op2 op2 is odd -> -1, even -> 1 0 1 op1 ** op2 // op2 is zero 1 1 1 1 1 // op2 is negative 0 op2 is odd -> -1, even -> 1 'x 1 0 case (last_cyc) 32'd10: checkpow(67'h1, 67'h1); // 0 ** 0 -> 1 32'd11: checkpow(67'h0, 67'h0); // 0 ** 1 -> 1 32'd12: ; // 0 ** -1 -> x 32'd13: checkpow(67'h0, 67'h0); // 0 ** 2 -> 0 32'd14: checkpow(67'h0, 67'h0); // 0 ** 3 -> 0 32'd20: checkpow(67'h1, 67'h1); // 1 ** 0 -> 1 32'd21: checkpow(67'h1, 67'h1); // 1 ** 1 -> 1 `ifndef IVERILOG 32'd22: checkpow(67'h1, 67'h1); // 1 ** -1 -> 1 `endif 32'd23: checkpow(67'h1, 67'h1); // 1 ** 2 -> 1 32'd24: checkpow(67'h1, 67'h1); // 1 ** 3 -> 1 32'd30: checkpow(67'h1, 67'h1); // -1 ** 0 -> 1 32'd31: checkpow(-67'h1, -67'h1); // -1 ** 1 -> -1 if odd else 1 32'd32: golddump(); // -1 ** -1 SEE GOLDEN 32'd33: golddump(); // -1 ** 2 SEE GOLDEN 32'd34: golddump(); // -1 ** 3 SEE GOLDEN 32'd40: checkpow(67'h1, 67'h1); // 2 ** 0 -> 1 32'd41: checkpow(67'h2, 67'h2); // 2 ** 1 32'd42: checkpow(67'h0, 67'h0); // 2 ** -1 -> 0 32'd43: checkpow(67'h4, 67'h4); // 2 ** 2 32'd44: checkpow(67'h8, 67'h8); // 2 ** 3 32'd50: checkpow(67'h1, 67'h1); // 3 ** 0 -> 0 32'd51: checkpow(67'h3, 67'h3); // 3 ** 1 32'd52: golddump(); // 3 ** -1 -> 0 (if negative gives 0) 32'd53: checkpow(67'h9, 67'h9); // 3 ** 2 32'd54: checkpow(67'h1b, 67'h1b); // 3 ** 3 32'd60: checkpow(67'h1, 67'h1); // -2 ** 0 -> 1 32'd61: golddump(); // -2 ** 1 SEE GOLDEN 32'd62: golddump(); // -2 ** -1 SEE GOLDEN 32'd63: golddump(); // -2 ** 2 SEE GOLDEN 32'd64: golddump(); // -2 ** 3 SEE GOLDEN default: ; endcase case (cyc) 32'd00: ; 32'd01: ; 32'd02: `checkh(shifted, 67'h0000000000000001); 32'd03: `checkh(shifted, 67'h0000000000000008); 32'd04: `checkh(shifted, 67'h0002000000000000); 32'd05: `checkh(shifted, 67'h0000000000010000); 32'd06: `checkh(shifted, 67'h0000000000000008); 32'd07: `checkh(shifted, 67'h0000000000000080); 32'd08: `checkh(shifted, 67'h0000000000000000); 32'd09: `checkh(shifted, 67'h0000000000000000); default: ; endcase `checkh(shifted_signed, shifted); end endmodule verilator-5.042/test_regress/t/t_lint_latch_casei_bad.py0000755000542200017500000000076615101701376024072 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_pp_underline_bad.out0000644000542200017500000000150315101701376023433 0ustar mahmoudyfreeshell%Error: t/t_pp_underline_bad.v:8:4: Extra underscore in meta-comment; use /*verilator {...}*/ not /*verilator_{...}*/ 8 | // verilator_no_inline_module | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_pp_underline_bad.v:10:19: Extra underscore in meta-comment; use /*synopsys {...}*/ not /*synopsys_{...}*/ 10 | case (1'b1) // synopsys_full_case | ^~~~~~~~~~~~~~~~~~~~~ %Error-BADVLTPRAGMA: t/t_pp_underline_bad.v:8:4: Unknown verilator comment: '/*verilator _no_inline_module*/' 8 | /*verilator _no_inline_module*/ | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ... For error description see https://verilator.org/warn/BADVLTPRAGMA?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_property_recursive_unsup.out0000644000542200017500000000056115101701376025351 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_property_recursive_unsup.v:20:13: Unsupported: Recursive property call: 'check' : ... note: In instance 't' 20 | property check(int n); | ^~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_constraint_xml.out0000644000542200017500000000731315101701376023212 0ustar mahmoudyfreeshell verilator-5.042/test_regress/t/t_interface_modport_coverage.py0000755000542200017500000000106515101701376025347 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_modport.v" test.compile(verilator_flags2=["-fno-inline --coverage"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_export_packed_struct.v0000644000542200017500000000635015101701376024040 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Kefa Chen. // SPDX-License-Identifier: CC0-1.0 typedef logic [5:0] udata6_t; typedef union soft packed { udata6_t a; logic [2 : 0] b; } sub_t; typedef struct packed { logic [40:0] a; udata6_t [3:0] nullptr; // name confict test sub_t get; // name confict test } in_t /*verilator public*/; typedef struct packed { udata6_t [3:0] nullptr; sub_t get; logic [40:0] a; } out_t /*verilator public*/; // struct in1_t should cover parts of VL_ASSIGNSEL_II functions typedef struct packed { logic [3:0] a; logic [11:0] b; } in1_t /*verilator public*/; // 4 + 12 = 16 typedef struct packed { logic [11:0] b; logic [3:0] a; } out1_t /*verilator public*/; // struct in2_t should cover all VL_ASSIGNSEL_II functions typedef struct packed { logic [2:0] a; logic [8:0] b; logic [18:0] c; } in2_t /*verilator public*/; // 3 + 9 + 19 = 31 typedef struct packed { logic [8:0] b; logic [18:0] c; logic [2:0] a; } out2_t /*verilator public*/; // struct in3_t should cover all VL_ASSIGNSEL_XQ functions typedef struct packed { logic [1:0] a; logic [8:0] b; logic [16:0] c; logic [32:0] d; } in3_t /*verilator public*/; // 33 + 17 + 9 + 2 = 61 typedef struct packed { logic [8:0] b; logic [1:0] a; logic [32:0] d; logic [16:0] c; } out3_t /*verilator public*/; // struct in4_t should cover all VL_ASSIGNSEL_XW functions typedef struct packed { logic [4:0] a; logic [12:0] b; logic [24:0] c; logic [48:0] d; logic [80:0] e; } in4_t /*verilator public*/; // 5 + 13 + 25 + 49 + 81 = 173 typedef struct packed { logic [24:0] c; logic [48:0] d; logic [80:0] e; logic [4:0] a; logic [12:0] b; } out4_t /*verilator public*/; module add ( input in_t op1, input in_t op2, output out_t out, // Add some extra ports to test all VL_ASSIGNSEL_XX functions input in1_t op1a, input in1_t op1b, output out1_t out1, // Add some extra ports to test all VL_ASSIGNSEL_XX functions input in2_t op2a, input in2_t op2b, output out2_t out2, // Add some extra ports to test all VL_ASSIGNSEL_XX functions input in3_t op3a, input in3_t op3b, output out3_t out3, // Add some extra ports to test all VL_ASSIGNSEL_XX functions input in4_t op4a, input in4_t op4b, output out4_t out4 ); assign out.a = op1.a + op2.a; generate for (genvar i = 0; i < 4; ++i) begin assign out.nullptr[i] = op1.nullptr[i] + op2.nullptr[i]; end endgenerate assign out.get.a = op1.get.a + op2.get.a; // out1 assign out1.a = op1a.a + op1b.a; assign out1.b = op1a.b + op1b.b; // out2 assign out2.a = op2a.a + op2b.a; assign out2.b = op2a.b + op2b.b; assign out2.c = op2a.c + op2b.c; // out3 assign out3.a = op3a.a + op3b.a; assign out3.b = op3a.b + op3b.b; assign out3.c = op3a.c + op3b.c; assign out3.d = op3a.d + op3b.d; // out4 assign out4.a = op4a.a + op4b.a; assign out4.b = op4a.b + op4b.b; assign out4.c = op4a.c + op4b.c; assign out4.d = op4a.d + op4b.d; assign out4.e = op4a.e + op4b.e; endmodule verilator-5.042/test_regress/t/t_xml_tag.v0000644000542200017500000000334515101701376021240 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Chris Randall. // SPDX-License-Identifier: CC0-1.0 interface ifc; integer value; modport out_modport (output value); endinterface module m ( input clk_ip, // verilator tag clk_ip input rst_ip, output foo_op); // verilator tag foo_op // This is a comment typedef struct packed { logic clk; /* verilator tag this is clk */ logic k; /* verilator lint_off UNUSED */ logic enable; // verilator tag enable logic data; // verilator tag data } my_struct; // verilator tag my_struct // This is a comment ifc itop(); my_struct this_struct [2]; // verilator tag this_struct wire [31:0] dotted = itop.value; function void f(input string m); $display("%s", m); endfunction initial begin // Contains all 256 characters except 0 (null character) f("\x01\x02\x03\x04\x05\x06\a\x08\t\n\v\f\r\x0e\x0f\x10\x11\x12\x13\x14\x15\x16\x17\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f !\"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\\]^_`abcdefghijklmnopqrstuvwxyz{|}~\x7f\x80\x81\x82\x83\x84\x85\x86\x87\x88\x89\x8a\x8b\x8c\x8d\x8e\x8f\x90\x91\x92\x93\x94\x95\x96\x97\x98\x99\x9a\x9b\x9c\x9d\x9e\x9f\xa0\xa1\xa2\xa3\xa4\xa5\xa6\xa7\xa8\xa9\xaa\xab\xac\xad\xae\xaf\xb0\xb1\xb2\xb3\xb4\xb5\xb6\xb7\xb8\xb9\xba\xbb\xbc\xbd\xbe\xbf\xc0\xc1\xc2\xc3\xc4\xc5\xc6\xc7\xc8\xc9\xca\xcb\xcc\xcd\xce\xcf\xd0\xd1\xd2\xd3\xd4\xd5\xd6\xd7\xd8\xd9\xda\xdb\xdc\xdd\xde\xdf\xe0\xe1\xe2\xe3\xe4\xe5\xe6\xe7\xe8\xe9\xea\xeb\xec\xed\xee\xef\xf0\xf1\xf2\xf3\xf4\xf5\xf6\xf7\xf8\xf9\xfa\xfb\xfc\xfd\xfe\xff"); end endmodule verilator-5.042/test_regress/t/t_lint_nolatch_bad.out0000644000542200017500000000055615101701376023434 0ustar mahmoudyfreeshell%Warning-NOLATCH: t/t_lint_nolatch_bad.v:12:4: No latches detected in always_latch block 12 | always_latch | ^~~~~~~~~~~~ ... For warning description see https://verilator.org/warn/NOLATCH?v=latest ... Use "/* verilator lint_off NOLATCH */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_fork_repeat_reset.py0000755000542200017500000000077115101701376023476 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_param_store_bad.v0000644000542200017500000000073615101701376022730 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t #( string S = "" ); initial begin $value$plusargs("S=%s", S); // BAD assignment to S #1; // Original bug got compile time error only with this line $display("S=%s", S); $finish; end endmodule verilator-5.042/test_regress/t/t_display_real.v0000644000542200017500000000405215101701376022251 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; real n0; initial n0 = 0.0; real n1; initial n1 = 1.0; real n2; initial n2 = 0.1; real n3; initial n3 = 1.2345e-15; real n4; initial n4 = 2.579e+15; reg [7:0] r8; initial r8 = 3; integer iconst = 0; initial begin // Display formatting $display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e p=%p", $time, n0,n0,n0,n0,n0); $display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e p=%p", $time, n0,n0,n0,n0,n0); $display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e p=%p", $time, n0,n0,n0,n0,n0); $display; $display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e p=%p", $time, n1,n1,n1,n1,n1); $display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e p=%p", $time, n1,n1,n1,n1,n1); $display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e p=%p", $time, n1,n1,n1,n1,n1); $display; $display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e p=%p", $time, n2,n2,n2,n2,n2); $display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e p=%p", $time, n2,n2,n2,n2,n2); $display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e p=%p", $time, n2,n2,n2,n2,n2); $display; $display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e p=%p", $time, n3,n3,n3,n3,n3); $display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e p=%p", $time, n3,n3,n3,n3,n3); $display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e p=%p", $time, n3,n3,n3,n3,n3); $display; $display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e p=%p", $time, n4,n4,n4,n4,n4); $display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e p=%p", $time, n4,n4,n4,n4,n4); $display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e p=%p", $time, n4,n4,n4,n4,n4); $display; $display("r8=%d n1=%g n2=%g", r8, n1, n2); $display("n1=%g n2=%g r8=%d", n1, n2, r8); $display; $display("iconst=%e %f %g", iconst, iconst, iconst); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_lint_implicit_bad.py0000755000542200017500000000114315101701376023433 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_lint_implicit.v" test.lint(verilator_flags2=["--lint-only -Wwarn-IMPLICIT"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_assoc_method_bad.v0000644000542200017500000000140715101701376023060 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin string a [string]; string k; string v; v = a.num("badarg"); v = a.size("badarg"); v = a.exists(); // Bad v = a.exists(k, "bad2"); v = a.first(); // Bad v = a.next(k, "bad2"); // Bad v = a.last(); // Bad v = a.prev(k, "bad2"); // Bad a.delete(k, "bad2"); a.sort; // Not legal on assoc a.rsort; // Not legal on assoc a.reverse; // Not legal on assoc a.shuffle; // Not legal on assoc a.bad_not_defined(); end endmodule verilator-5.042/test_regress/t/t_select_plusloop.v0000644000542200017500000000404715101701376023021 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [31:0] narrow; reg [63:0] quad; reg [127:0] wide; integer cyc; initial cyc = 0; reg [7:0] crc; reg [6:0] index; always @ (posedge clk) begin //$write("[%0t] cyc==%0d crc=%b n=%x\n", $time, cyc, crc, narrow); cyc <= cyc + 1; if (cyc==0) begin // Setup narrow <= 32'h0; quad <= 64'h0; wide <= 128'h0; crc <= 8'hed; index <= 7'h0; end else if (cyc<90) begin index <= index + 7'h2; crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; // verilator lint_off WIDTH if (index < 9'd20) narrow[index +: 3] <= crc[2:0]; if (index < 9'd60) quad [index +: 3] <= crc[2:0]; if (index < 9'd120) wide [index +: 3] <= crc[2:0]; // narrow[index[3:0]] <= ~narrow[index[3:0]]; quad [~index[3:0]]<= ~quad [~index[3:0]]; wide [~index[3:0]] <= ~wide [~index[3:0]]; // verilator lint_on WIDTH end else if (cyc==90) begin wide[12 +: 4] <=4'h6; quad[12 +: 4] <=4'h6; narrow[12 +: 4] <=4'h6; wide[42 +: 4] <=4'h6; quad[42 +: 4] <=4'h6; wide[82 +: 4] <=4'h6; end else if (cyc==91) begin wide[0] <=1'b1; quad[0] <=1'b1; narrow[0] <=1'b1; wide[41] <=1'b1; quad[41] <=1'b1; wide[81] <=1'b1; end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%b n=%x q=%x w=%x\n", $time, cyc, crc, narrow, quad, wide); if (crc != 8'b01111001) $stop; if (narrow != 32'h001661c7) $stop; if (quad != 64'h16d49b6f64266039) $stop; if (wide != 128'h012fd26d265b266ff6d49b6f64266039) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_interface1_modport_trace.py0000755000542200017500000000105315101701376024730 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface1_modport.v" test.compile(verilator_flags2=['--trace-vcd']) test.execute() test.passes() verilator-5.042/test_regress/t/t_inst_missing_dot_bad.py0000755000542200017500000000076615101701376024161 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_force_rhs_ref_multi_lhs.py0000755000542200017500000000076315101701376024662 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_ref_trace_saif.py0000755000542200017500000000126715101701376024750 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_ref_trace.v" test.golden_filename = "t/t_interface_ref_trace_saif.out" test.compile(verilator_flags2=['--trace-structs --trace-saif']) test.execute() test.saif_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_func_bad_width.py0000755000542200017500000000077615101701376022740 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_math_insert_bound.v0000644000542200017500000000545415101701376023314 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Paul Swirhun. // SPDX-License-Identifier: CC0-1.0 // Demonstrates the bug in https://github.com/verilator/verilator/issues/4850 // // Specifically, _vl_insert_WI() writes to lword and hword when lword != hword // may be unsafe, because (for example), lword was the highest valid place to // perform a write and hword is out-of-bounds (and will in fact clobber other // state in the generated C++ struct!). module t(/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 13; // These need to be generated/consumed in this testbench so that // they do not get pruned away when verilated logic insert = '0; logic [3:0] used, free; logic [95:0] data; always_ff @(posedge clk) begin insert <= '1; cyc <= cyc - 1; `ifdef TEST_VERBOSE $write("used [4'd%2d], free [4'd%2d], data = [96'h%012x]\n", used, free, data); `endif if (used + free != 12) begin $write("used [4'd%2d] + free [4'd%2d] != 4'd12\n", used, free); $stop(); end if (used == 0) begin $write("used [4'd%2d] was clobbered (should always be nonzero).\n", used); $stop(); end if (cyc == 0) begin if (used == 12 && free == 0 && data == 96'hFF) begin $write("*-* All Finished *-*\n"); $finish; end else begin $write("Test Failed! used/free/data had unexpected final value(s).\n"); $stop(); end end end dut dut_i( .clk(clk), .insert(insert), .used(used), .free(free), .data(data) ); endmodule module dut( input logic clk, input logic insert, output logic [3:0] used, output logic [3:0] free, output logic [95:0] data ); // This declaration order matters -- the fact that d_data is *before* d_used/d_free // means that with the existing bug, writes to d_data that extend beyond its length // will overwrite other fields in the state struct -- basically an "unsafe writes" // problem because the existing code wrote beyond the end of the array d_data. logic [11:0][7:0] d_data = '1, d_data_next; logic [3:0] d_used = 4'd1, d_free = 4'd11, d_used_next; assign used = d_used; assign free = d_free; assign data = d_data; always_ff @(posedge clk) begin d_data <= d_data_next; d_used <= d_used_next; d_free <= 12 - d_used_next; end always_comb begin d_data_next = d_data; d_used_next = d_used; if ((insert == 1'b1) && (d_free >= {3'b0, insert})) begin // This write to d_data would clobber d_used before the issue was fixed d_data_next[d_used+:4] = 32'd0; d_used_next += 4'd1; end end endmodule verilator-5.042/test_regress/t/t_castdyn_run_bad.out0000644000542200017500000000021415101701376023276 0ustar mahmoudyfreeshell[0] %Error: t_castdyn_run_bad.v:32: Assertion failed in top.t: 'assert' failed. %Error: t/t_castdyn_run_bad.v:32: Verilog $stop Aborting... verilator-5.042/test_regress/t/t_trace_complex_structs.py0000755000542200017500000000216015101701376024401 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_complex.v" test.compile(verilator_flags2=['--cc --trace-vcd --trace-structs --no-trace-params']) test.execute() test.file_grep(test.trace_filename, r' v_strp ') test.file_grep(test.trace_filename, r' v_strp_strp ') test.file_grep(test.trace_filename, r' v_arrp ') test.file_grep_not(test.trace_filename, r' v_arrp_arrp ') test.file_grep_not(test.trace_filename, r' v_arrp_strp ') test.file_grep(test.trace_filename, r' v_arru\[') test.file_grep(test.trace_filename, r' v_arru_arru\[') test.file_grep(test.trace_filename, r' v_arru_arrp\[') test.file_grep(test.trace_filename, r' v_arru_strp\[') test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_order_dpi_export_2.v0000644000542200017500000000207115101701376023371 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2021 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module testbench( /*AUTOARG*/ // Inputs clk ); input clk; // Top level input clock bit other_clk; // Dependent clock set via DPI export "DPI-C" function set_other_clk; function void set_other_clk(bit val); other_clk = val; endfunction; bit even_other = 1; import "DPI-C" context function void toggle_other_clk(bit val); always @(posedge clk) begin even_other <= ~even_other; toggle_other_clk(even_other); end int n = 0; always @(posedge other_clk) begin $display("[%0t] n=%0d", $time, n); if ($time != (4*n+1) * 500) $stop; if (n == 20) begin $write("*-* All Finished *-*\n"); $finish; end n += 1; end endmodule verilator-5.042/test_regress/t/t_trace_dumporder_bad.v0000644000542200017500000000062615101701376023571 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin // Check error when this missing: $dumpfile("/should/not/be/opened"); $dumpvars; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_lint_width_shift_bad.out0000644000542200017500000000356515101701376024323 0ustar mahmoudyfreeshell%Warning-WIDTHTRUNC: t/t_lint_width_shift_bad.v:19:15: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's SHIFTL generates 4 bits. : ... note: In instance 't' 19 | assign ol3 = i4 << 1; | ^ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Warning-WIDTHTRUNC: t/t_lint_width_shift_bad.v:23:15: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's SHIFTR generates 4 bits. : ... note: In instance 't' 23 | assign or3 = i4 >> 1; | ^ %Warning-WIDTHEXPAND: t/t_lint_width_shift_bad.v:25:20: Operator SHIFTR expects 5 bits on the LHS, but LHS's VARREF 'i4' generates 4 bits. : ... note: In instance 't' 25 | assign or5 = i4 >> 1; | ^~ ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. %Warning-WIDTHTRUNC: t/t_lint_width_shift_bad.v:27:15: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's SHIFTRS generates 4 bits. : ... note: In instance 't' 27 | assign os3 = i4 >>> 1; | ^ %Warning-WIDTHEXPAND: t/t_lint_width_shift_bad.v:29:20: Operator SHIFTRS expects 5 bits on the LHS, but LHS's VARREF 'i4' generates 4 bits. : ... note: In instance 't' 29 | assign os5 = i4 >>> 1; | ^~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_mem_packed_assign.v0000644000542200017500000000157715101701376023243 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); /* verilator lint_off WIDTH */ input clk; integer cyc; initial cyc = 0; logic [31:0] arr_c; initial arr_c = 0; logic [7:0] [3:0] arr; logic [31:0] arr2_c; initial arr2_c = 0; logic [7:0] [3:0] arr2; assign arr2_c = arr2; always @ (posedge clk) begin cyc <= cyc + 1; arr_c <= arr_c + 1; arr2 <= arr2 + 1; `ifdef TEST_VERBOSE $write("cyc%0d c:%0x a0:%0x a1:%0x a2:%0x a3:%0x\n", cyc, arr_c, arr[0], arr[1], arr[2], arr[3]); `endif if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end /* verilator lint_on WIDTH */ endmodule verilator-5.042/test_regress/t/t_type_expression_compare.v0000644000542200017500000000164315101701376024552 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 typedef int Int_T; module t; initial begin Int_T value1 = 7; int value2 = 13; real r; if (type(value1) != type(value2)) $stop; if (type(value1 + value2) != type(value2 + 18)) $stop; case (type(value1)) type(value2): ; type(r): $stop; type(chandle): $stop; type(logic): $stop; default: $stop; endcase case (type(value1 + value2 + 13)) type(type(value2 + 18 - 40)): ; type(r): $stop; type(chandle): $stop; default: $stop; endcase if (type(value1) == type(value2) && type(value1 + value2) == type(value2 + 18)) begin $write("*-* All Finished *-*\n"); $finish; end else begin $stop; end end endmodule verilator-5.042/test_regress/t/t_lint_widthexpand_docs_bad.out0000644000542200017500000000104415101701376025324 0ustar mahmoudyfreeshell%Warning-WIDTHEXPAND: t/t_lint_widthexpand_docs_bad.v:10:31: Bit extraction of array[4:0] requires 3 bit index, not 2 bits. : ... note: In instance 't' 10 | wire [31:0] rd_value = array[rd_addr]; | ^ ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_gate_width_bad.py0000755000542200017500000000076615101701376022724 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_tri_inout.v0000644000542200017500000000723015101701376021616 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2008 by Lane Brooks. // SPDX-License-Identifier: CC0-1.0 module top (input A, input B, input SEL, input clk, output Y1, output Y2, output Z, output done); io io1(.A(A), .OE( SEL), .Z(Z), .Y(Y1)); pass io2(.A(B), .OE(!SEL), .Z(Z), .Y(Y2)); assign Z = 1'bz; pad_checker u_pad_checker(.clk(clk), .done(done)); endmodule module pass (input A, input OE, inout Z, output Y); io_noinline io(.A(A), .OE(OE), .Z(Z), .Y(Y)); assign Z = 1'bz; endmodule module io (input A, input OE, inout Z, output Y); assign Z = (OE) ? A : 1'bz; assign Y = Z; assign Z = 1'bz; endmodule module io_noinline (input A, input OE, inout Z, output Y); /*verilator no_inline_module*/ assign Z = (OE) ? A : 1'bz; assign Y = Z; assign Z = 1'bz; endmodule module pad_checker(input wire clk, output wire done); wire tri_pad; reg [1:0] ie = '0; reg [1:0] oe = '0; reg [1:0] in = '0; wire out_0, out_1; pad u_pad0(.pad(tri_pad), .ie(ie[0]), .oe(oe[0]), .to_pad(in[0]), .from_pad(out_0)); pad u_pad1(.pad(tri_pad), .ie(ie[1]), .oe(oe[1]), .to_pad(in[1]), .from_pad(out_1)); wire bin_pad_in_0, bin_pad_in_1; wire bin_pad_01, bin_pad_10; wire bin_pad_en_01, bin_pad_en_10; wire bin_from_pad_out_0, bin_from_pad_out_1; wire bin_from_pad_en_0, bin_from_pad_en_1; // Expectation model that simulates how Verilator solves tri-state pad_binary u_pad_bin_0(.pad_in(bin_pad_in_0), .pad_out(bin_pad_01), .pad_en(bin_pad_en_01), .ie(ie[0]), .oe(oe[0]), .to_pad(in[0]), .from_pad_out(bin_from_pad_out_0), .from_pad_en(bin_from_pad_en_0)); pad_binary u_pad_bin_1(.pad_in(bin_pad_in_1), .pad_out(bin_pad_10), .pad_en(bin_pad_en_10), .ie(ie[1]), .oe(oe[1]), .to_pad(in[1]), .from_pad_out(bin_from_pad_out_1), .from_pad_en(bin_from_pad_en_1)); assign bin_pad_in_0 = (bin_pad_en_10 & bin_pad_10) | (bin_pad_en_01 & bin_pad_01); assign bin_pad_in_1 = (bin_pad_en_01 & bin_pad_01) | (bin_pad_en_10 & bin_pad_10); logic done_reg = 0; assign done = done_reg; always @(posedge clk) begin if ({ie, oe, in} == 6'b111111) begin done_reg <= 1'b1; end else begin if (out_0 != bin_from_pad_out_0) begin $display("ie:%b oe:%b in:%b out0 act:%b exp:%b", ie[0], oe[0], in[0], out_0, bin_from_pad_out_0); $stop; end if (out_1 != bin_from_pad_out_1) begin $display("ie:%b oe:%b in:%b out1 act:%b exp:%b", ie[1], oe[1], in[1], out_1, bin_from_pad_out_1); $stop; end // Let's try all combination {ie, oe, in} <= {ie, oe, in} + 1; end end endmodule module pad(inout wire pad, input wire ie, input wire oe, input wire to_pad, output wire from_pad); assign pad = oe ? to_pad : 1'bz; assign from_pad = ie ? pad : 1'bz; endmodule module pad_binary(input wire pad_in, output wire pad_out, output wire pad_en, input wire ie, input wire oe, input wire to_pad, output from_pad_out, output wire from_pad_en); assign pad_out = oe & to_pad; assign pad_en = oe; assign from_pad_out = ie & ((oe & to_pad) | pad_in); assign from_pad_en = ie; endmodule verilator-5.042/test_regress/t/t_mem_iforder.py0000755000542200017500000000073415101701376022262 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_cover_lib_legacy.py0000755000542200017500000000211515101701376023255 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_cover_lib.v" test.compile(v_flags2=["--coverage t/t_cover_lib_c.cpp"], verilator_flags2=["--exe -Wall -Wno-DECLFILENAME"], make_flags=['CPPFLAGS_ADD=-DTEST_OBJ_DIR="' + test.obj_dir + '"'], make_top_shell=False, make_main=False) test.execute() test.files_identical_sorted(test.obj_dir + "/coverage1.dat", "t/t_cover_lib__1.out") test.files_identical_sorted(test.obj_dir + "/coverage2.dat", "t/t_cover_lib__2.out") test.files_identical_sorted(test.obj_dir + "/coverage3.dat", "t/t_cover_lib__3.out") test.files_identical_sorted(test.obj_dir + "/coverage4.dat", "t/t_cover_lib__4.out") test.passes() verilator-5.042/test_regress/t/t_var_port_xml.py0000755000542200017500000000133615101701376022505 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') out_filename = test.obj_dir + "/V" + test.name + ".xml" test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only'], verilator_make_gmake=False, make_top_shell=False, make_main=False) test.files_identical(out_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_process_compare.py0000755000542200017500000000077115101701376023157 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--binary']) test.execute() test.passes() verilator-5.042/test_regress/t/t_enum_name3.py0000755000542200017500000000073415101701376022021 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_timing_finish2.v0000644000542200017500000000153415101701376022514 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module tb2 (); parameter CLK_PERIOD = 2; reg clk = 1'b0; int messages; always #(CLK_PERIOD / 2) clk = ~clk; always begin static int counter = 0; while (counter < 3) begin counter += 1; $display("[%0t] Running loop %0d", $time, counter); messages += 1; @(posedge clk); end $write("[%0t] *-* All Finished *-*\n", $time); $finish; end final `checkd(messages, 3); endmodule verilator-5.042/test_regress/t/t_gate_inline_wide_noexclude_varref.py0000755000542200017500000000122715101701376026671 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=['--stats', '--expand-limit 5']) test.file_grep(test.stats, r'Optimizations, Gate excluded wide expressions\s+(\d+)', 0) test.file_grep(test.stats, r'Optimizations, Gate sigs deleted\s+(\d+)', 0) test.passes() verilator-5.042/test_regress/t/t_randomize_unpacked_bad.v0000644000542200017500000000067515101701376024260 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class ex; randc struct {logic m_x;} s; // <--- Bad: randc illegal on unpacked struct randc struct packed {logic m_x;} p_s; // Ok endclass : ex module foo; initial begin ex e; void'(e.randomize()); end endmodule verilator-5.042/test_regress/t/t_array_pattern_scalar_bad.v0000644000542200017500000000047715101701376024616 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; bit bad = '{1'b1}; // <--- BAD: Can't assign pattern to scalar initial $stop; endmodule verilator-5.042/test_regress/t/t_stop_bad.v0000644000542200017500000000046315101701376021376 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin $write("Intentional stop\n"); $stop; end endmodule verilator-5.042/test_regress/t/t_pp_display.v0000644000542200017500000000437515101701376021755 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; wire d1 = 1'b1; wire d2 = 1'b1; wire d3 = 1'b1; wire o1,o2,o3; add1 add1 (d1,o1); add2 add2 (d2,o2); `define ls left_side `define rs right_side `define noarg na//note extra space `define thru(x) x `define thruthru `ls `rs // Doesn't expand `define msg(x,y) `"x: `\`"y`\`"`" `define left(m,left) m // The 'left' as the variable name shouldn't match the "left" in the `" string initial begin //$display(`msg( \`, \`)); // Illegal $display(`msg(pre `thru(thrupre `thru(thrumid) thrupost) post,right side)); $display(`msg(left side,right side)); $display(`msg( left side , right side )); $display(`msg( `ls , `rs )); $display(`msg( `noarg , `rs )); $display(`msg( prep ( midp1 `ls midp2 ( outp ) ) , `rs )); $display(`msg(`noarg,`noarg`noarg)); $display(`msg( `thruthru , `thruthru )); // Results vary between simulators $display(`left(`msg( left side , right side ), left_replaced)); //$display(`msg( `"tickquoted_left`", `"tickquoted_right`" )); // Syntax error `ifndef VCS // Sim bug - wrong number of arguments, but we're right $display(`msg(`thru(),)); // Empty `endif $display(`msg(`thru(left side),`thru(right side))); $display(`msg( `thru( left side ) , `thru( right side ) )); `ifndef NC $display(`"standalone`"); `endif `ifdef VERILATOR // Illegal on some simulators, as the "..." crosses two lines `define twoline first \ second $display(`msg(twoline, `twoline)); `endif $display("Line %0d File \"%s\"",`__LINE__,`__FILE__); //$display(`msg(left side, \ right side \ )); // Not sure \{space} is legal. $write("*-* All Finished *-*\n"); $finish; end endmodule `define ADD_UP(a,c) \ wire tmp_``a = a; \ wire tmp_``c = tmp_``a + 1; \ assign c = tmp_``c ; module add1 ( input wire d1, output wire o1); `ADD_UP(d1,o1) // expansion is OK endmodule module add2 ( input wire d2, output wire o2); `ADD_UP( d2 , o2 ) // expansion is bad endmodule // `ADD_UP( \d3 , \o3 ) // This really is illegal verilator-5.042/test_regress/t/t_attr.v0000644000542200017500000000057315101701376020557 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; (* attr_name1 *) (* attr_name1 = val1 *) (* attr_name1 = val1, attr_name2 *) (* attr_name1 = val1, attr_name2=1 *) initial $finish; endmodule verilator-5.042/test_regress/t/t_udp_bad_line_inputs.py0000755000542200017500000000076615101701376024006 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_flag_quiet_stats.v0000644000542200017500000000047115101701376023140 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_semaphore_concurrent.py0000755000542200017500000000103515101701376024212 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_flag_f_bad_cmt.out0000644000542200017500000000025415101701376023032 0ustar mahmoudyfreeshell%Error: Unterminated /* comment inside -f file. ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_force_release_var_reverse.py0000755000542200017500000000105615101701376025171 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_force_release_var.v" test.compile(verilator_flags2=['+define+REVERSE']) test.execute() test.passes() verilator-5.042/test_regress/t/t_gen_ifelse.py0000755000542200017500000000073415101701376022072 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_fork_join_none_any_nested.py0000755000542200017500000000077115101701376025203 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_dfg_3726.v0000644000542200017500000000053115101701376021020 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Outputs x, // Inputs i ); input i; output x; assign x = (i ? 0 : 1) && 1; endmodule verilator-5.042/test_regress/t/t_timing_func_bad.v0000644000542200017500000000132715101701376022713 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; function int f1; #1 $stop; f1 = 0; endfunction function int f2; f2 = #5 0; $stop; endfunction event e; function int f3; @e $stop; f3 = 0; endfunction function int f4; f4 = @e 0; $stop; endfunction int i; function int f5; wait(i == 0) $stop; f5 = 0; endfunction initial begin i = f1(); $write("*-* All Finished *-*\n"); $finish; end final begin #1; $stop; end endmodule verilator-5.042/test_regress/t/t_const_op_red_scope.v0000644000542200017500000000751415101701376023456 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Use this file as a template for submitting bugs, etc. // This module takes a single clock input, and should either // $write("*-* All Finished *-*\n"); // $finish; // on success, or $stop. // // The code as shown applies a random vector to the Test // module, then calculates a CRC on the Test module's outputs. // // **If you do not wish for your code to be released to the public // please note it here, otherwise:** // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by ____YOUR_NAME_HERE____. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [7:0] in = crc[7:0]; /*AUTOWIRE*/ wire out0; wire out1; wire out2; wire out3; wire out4; wire out5; wire out6; wire out7; /*SelFlop AUTO_TEMPLATE(.n(@), .out(out@)); */ SelFlop selflop0(/*AUTOINST*/ // Outputs .out (out0), // Templated // Inputs .clk (clk), .in (in[7:0]), .n (0)); // Templated SelFlop selflop1(/*AUTOINST*/ // Outputs .out (out1), // Templated // Inputs .clk (clk), .in (in[7:0]), .n (1)); // Templated SelFlop selflop2(/*AUTOINST*/ // Outputs .out (out2), // Templated // Inputs .clk (clk), .in (in[7:0]), .n (2)); // Templated SelFlop selflop3(/*AUTOINST*/ // Outputs .out (out3), // Templated // Inputs .clk (clk), .in (in[7:0]), .n (3)); // Templated // Aggregate outputs into a single result vector wire outo = out0|out1|out2|out3; wire outa = out0&out1&out2&out3; wire outx = out0^out1^out2^out3; wire [63:0] result = {61'h0, outo, outa, outx}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc == 0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc < 10) begin sum <= '0; end else if (cyc < 90) begin end else if (cyc == 99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h118c5809c7856d78 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module SelFlop(/*AUTOARG*/ // Outputs out, // Inputs clk, in, n ); input clk; input [7:0] in; input [2:0] n; output reg out; // verilator no_inline_module always @(posedge clk) begin out <= in[n]; end endmodule verilator-5.042/test_regress/t/t_timing_zerodly.v0000644000542200017500000000253515101701376022644 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class Foo; static task fork_w_zerodly(longint unsigned current_time); bit my_bit; bit zero_dly_first = 0; // Th code below relies on Verilator's deterministic scheduler and is not // compatible across different simulators. // // The `zero_dly` block is going to be executed first and then suspended at the #0 delay. // Then the `finish_before` block is going to be executed. Once that happens, the // execution of `zero_dly` block should be resumed, all within a single time-slot. // // IF THIS TEST FAILS AFTER CHANGES TO VERILATOR'S SCHEDULER, IT DOESN'T NECESSARILY // MEAN THE CHANGES ARE WRONG. fork begin : zero_dly zero_dly_first = 1; #0; if (current_time != $time) $stop; if (my_bit == 0) $stop; end : zero_dly begin : finish_before if (!zero_dly_first) $stop; my_bit = 1; end : finish_before join_none #1 $display("After fork."); // Check if there's no skipped coroutine endtask endclass module test(); initial begin Foo::fork_w_zerodly($time); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_dump_json.out0000644000542200017500000036644015101701376022155 0ustar mahmoudyfreeshell{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"(E)","stdPackagep":"(F)","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"UNLINKED", "modulesp": [ {"type":"MODULE","name":"t","addr":"(G)","loc":"e,7:8,7:9","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"t","level":2,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"PORT","name":"clk","addr":"(H)","loc":"e,9:4,9:7","exprp": []}, {"type":"VAR","name":"clk","addr":"(I)","loc":"e,11:10,11:13","dtypep":"UNLINKED","origName":"clk","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", "childDTypep": [ {"type":"BASICDTYPE","name":"LOGIC_IMPLICIT","addr":"(J)","loc":"e,11:10,11:13","dtypep":"(J)","keyword":"LOGIC_IMPLICIT","generic":false,"rangep": []} ],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"cyc","addr":"(K)","loc":"e,13:12,13:15","dtypep":"UNLINKED","origName":"cyc","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"VAR","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", "childDTypep": [ {"type":"BASICDTYPE","name":"integer","addr":"(L)","loc":"e,13:4,13:11","dtypep":"(L)","keyword":"integer","range":"31:0","generic":false,"rangep": []} ],"delayp": [], "valuep": [ {"type":"CONST","name":"?32?sh0","addr":"(M)","loc":"e,13:18,13:19","dtypep":"(N)"} ],"attrsp": []}, {"type":"VAR","name":"crc","addr":"(O)","loc":"e,14:15,14:18","dtypep":"UNLINKED","origName":"crc","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"VAR","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", "childDTypep": [ {"type":"BASICDTYPE","name":"logic","addr":"(P)","loc":"e,14:4,14:7","dtypep":"(P)","keyword":"logic","generic":false, "rangep": [ {"type":"RANGE","name":"","addr":"(Q)","loc":"e,14:8,14:9","ascending":false,"fromBracket":false, "leftp": [ {"type":"CONST","name":"?32?sh3f","addr":"(R)","loc":"e,14:9,14:11","dtypep":"(S)"} ], "rightp": [ {"type":"CONST","name":"?32?sh0","addr":"(T)","loc":"e,14:12,14:13","dtypep":"(N)"} ]} ]} ],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"sum","addr":"(U)","loc":"e,15:15,15:18","dtypep":"UNLINKED","origName":"sum","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"VAR","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", "childDTypep": [ {"type":"BASICDTYPE","name":"logic","addr":"(V)","loc":"e,15:4,15:7","dtypep":"(V)","keyword":"logic","generic":false, "rangep": [ {"type":"RANGE","name":"","addr":"(W)","loc":"e,15:8,15:9","ascending":false,"fromBracket":false, "leftp": [ {"type":"CONST","name":"?32?sh3f","addr":"(X)","loc":"e,15:9,15:11","dtypep":"(S)"} ], "rightp": [ {"type":"CONST","name":"?32?sh0","addr":"(Y)","loc":"e,15:12,15:13","dtypep":"(N)"} ]} ]} ],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"in","addr":"(Z)","loc":"e,18:16,18:18","dtypep":"UNLINKED","origName":"in","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"WIRE","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", "childDTypep": [ {"type":"BASICDTYPE","name":"logic","addr":"(AB)","loc":"e,18:9,18:10","dtypep":"(AB)","keyword":"logic","generic":false, "rangep": [ {"type":"RANGE","name":"","addr":"(BB)","loc":"e,18:9,18:10","ascending":false,"fromBracket":false, "leftp": [ {"type":"CONST","name":"?32?sh1f","addr":"(CB)","loc":"e,18:10,18:12","dtypep":"(DB)"} ], "rightp": [ {"type":"CONST","name":"?32?sh0","addr":"(EB)","loc":"e,18:13,18:14","dtypep":"(N)"} ]} ]} ],"delayp": [],"valuep": [],"attrsp": []}, {"type":"ALWAYS","name":"","addr":"(FB)","loc":"e,18:19,18:20","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(GB)","loc":"e,18:19,18:20","dtypep":"UNLINKED", "rhsp": [ {"type":"SELEXTRACT","name":"","addr":"(HB)","loc":"e,18:24,18:25","dtypep":"UNLINKED", "fromp": [ {"type":"PARSEREF","name":"crc","addr":"(IB)","loc":"e,18:21,18:24","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ], "leftp": [ {"type":"CONST","name":"?32?sh1f","addr":"(JB)","loc":"e,18:25,18:27","dtypep":"(DB)"} ], "rightp": [ {"type":"CONST","name":"?32?sh0","addr":"(KB)","loc":"e,18:28,18:29","dtypep":"(N)"} ],"attrp": []} ], "lhsp": [ {"type":"PARSEREF","name":"in","addr":"(LB)","loc":"e,18:16,18:18","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ],"timingControlp": [],"strengthSpecp": []} ]}, {"type":"VAR","name":"out","addr":"(MB)","loc":"e,22:25,22:28","dtypep":"UNLINKED","origName":"out","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"WIRE","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", "childDTypep": [ {"type":"BASICDTYPE","name":"logic","addr":"(NB)","loc":"e,22:9,22:10","dtypep":"(NB)","keyword":"logic","generic":false, "rangep": [ {"type":"RANGE","name":"","addr":"(OB)","loc":"e,22:9,22:10","ascending":false,"fromBracket":false, "leftp": [ {"type":"CONST","name":"?32?sh1f","addr":"(PB)","loc":"e,22:10,22:12","dtypep":"(DB)"} ], "rightp": [ {"type":"CONST","name":"?32?sh0","addr":"(QB)","loc":"e,22:13,22:14","dtypep":"(N)"} ]} ]} ],"delayp": [],"valuep": [],"attrsp": []}, {"type":"CELL","name":"test","addr":"(RB)","loc":"e,25:9,25:13","origName":"test","recursive":false,"modp":"(SB)", "pinsp": [ {"type":"PIN","name":"out","addr":"(TB)","loc":"e,27:15,27:18","svDotName":true,"svImplicit":false,"modVarp":"UNLINKED","modPTypep":"UNLINKED", "exprp": [ {"type":"SELEXTRACT","name":"","addr":"(UB)","loc":"e,27:45,27:46","dtypep":"UNLINKED", "fromp": [ {"type":"PARSEREF","name":"out","addr":"(VB)","loc":"e,27:42,27:45","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ], "leftp": [ {"type":"CONST","name":"?32?sh1f","addr":"(WB)","loc":"e,27:46,27:48","dtypep":"(DB)"} ], "rightp": [ {"type":"CONST","name":"?32?sh0","addr":"(XB)","loc":"e,27:49,27:50","dtypep":"(N)"} ],"attrp": []} ]}, {"type":"PIN","name":"clk","addr":"(YB)","loc":"e,29:15,29:18","svDotName":true,"svImplicit":false,"modVarp":"UNLINKED","modPTypep":"UNLINKED", "exprp": [ {"type":"PARSEREF","name":"clk","addr":"(ZB)","loc":"e,29:42,29:45","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ]}, {"type":"PIN","name":"in","addr":"(AC)","loc":"e,30:15,30:17","svDotName":true,"svImplicit":false,"modVarp":"UNLINKED","modPTypep":"UNLINKED", "exprp": [ {"type":"SELEXTRACT","name":"","addr":"(BC)","loc":"e,30:44,30:45","dtypep":"UNLINKED", "fromp": [ {"type":"PARSEREF","name":"in","addr":"(CC)","loc":"e,30:42,30:44","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ], "leftp": [ {"type":"CONST","name":"?32?sh1f","addr":"(DC)","loc":"e,30:45,30:47","dtypep":"(DB)"} ], "rightp": [ {"type":"CONST","name":"?32?sh0","addr":"(EC)","loc":"e,30:48,30:49","dtypep":"(N)"} ],"attrp": []} ]} ],"paramsp": [],"rangep": [],"intfRefsp": []}, {"type":"VAR","name":"result","addr":"(FC)","loc":"e,33:16,33:22","dtypep":"UNLINKED","origName":"result","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"WIRE","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", "childDTypep": [ {"type":"BASICDTYPE","name":"logic","addr":"(GC)","loc":"e,33:9,33:10","dtypep":"(GC)","keyword":"logic","generic":false, "rangep": [ {"type":"RANGE","name":"","addr":"(HC)","loc":"e,33:9,33:10","ascending":false,"fromBracket":false, "leftp": [ {"type":"CONST","name":"?32?sh3f","addr":"(IC)","loc":"e,33:10,33:12","dtypep":"(S)"} ], "rightp": [ {"type":"CONST","name":"?32?sh0","addr":"(JC)","loc":"e,33:13,33:14","dtypep":"(N)"} ]} ]} ],"delayp": [],"valuep": [],"attrsp": []}, {"type":"ALWAYS","name":"","addr":"(KC)","loc":"e,33:23,33:24","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(LC)","loc":"e,33:23,33:24","dtypep":"UNLINKED", "rhsp": [ {"type":"REPLICATE","name":"","addr":"(MC)","loc":"e,33:25,33:26","dtypep":"(NC)", "srcp": [ {"type":"CONCAT","name":"","addr":"(OC)","loc":"e,33:31,33:32","dtypep":"UNLINKED", "lhsp": [ {"type":"CONST","name":"32'h0","addr":"(PC)","loc":"e,33:26,33:31","dtypep":"(QC)"} ], "rhsp": [ {"type":"PARSEREF","name":"out","addr":"(RC)","loc":"e,33:33,33:36","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ]} ], "countp": [ {"type":"CONST","name":"32'h1","addr":"(SC)","loc":"e,33:25,33:26","dtypep":"(QC)"} ]} ], "lhsp": [ {"type":"PARSEREF","name":"result","addr":"(TC)","loc":"e,33:16,33:22","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ],"timingControlp": [],"strengthSpecp": []} ]}, {"type":"ALWAYS","name":"","addr":"(UC)","loc":"e,36:4,36:10","keyword":"always","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"EVENTCONTROL","name":"","addr":"(VC)","loc":"e,36:11,36:12", "sentreep": [ {"type":"SENTREE","name":"","addr":"(WC)","loc":"e,36:11,36:12","isMulti":false, "sensesp": [ {"type":"SENITEM","name":"","addr":"(XC)","loc":"e,36:14,36:21","edgeType":"POS", "sensp": [ {"type":"PARSEREF","name":"clk","addr":"(YC)","loc":"e,36:22,36:25","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ],"condp": []} ]} ], "stmtsp": [ {"type":"BEGIN","name":"","addr":"(ZC)","loc":"e,36:27,36:32","implied":false,"needProcess":false,"unnamed":true,"declsp": [], "stmtsp": [ {"type":"ASSIGNDLY","name":"","addr":"(AD)","loc":"e,40:11,40:13","dtypep":"UNLINKED", "rhsp": [ {"type":"ADD","name":"","addr":"(BD)","loc":"e,40:18,40:19","dtypep":"UNLINKED", "lhsp": [ {"type":"PARSEREF","name":"cyc","addr":"(CD)","loc":"e,40:14,40:17","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ], "rhsp": [ {"type":"CONST","name":"?32?sh1","addr":"(DD)","loc":"e,40:20,40:21","dtypep":"(N)"} ]} ], "lhsp": [ {"type":"PARSEREF","name":"cyc","addr":"(ED)","loc":"e,40:7,40:10","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ],"timingControlp": []}, {"type":"ASSIGNDLY","name":"","addr":"(FD)","loc":"e,41:11,41:13","dtypep":"UNLINKED", "rhsp": [ {"type":"REPLICATE","name":"","addr":"(GD)","loc":"e,41:14,41:15","dtypep":"(NC)", "srcp": [ {"type":"CONCAT","name":"","addr":"(HD)","loc":"e,41:24,41:25","dtypep":"UNLINKED", "lhsp": [ {"type":"SELEXTRACT","name":"","addr":"(ID)","loc":"e,41:18,41:19","dtypep":"UNLINKED", "fromp": [ {"type":"PARSEREF","name":"crc","addr":"(JD)","loc":"e,41:15,41:18","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ], "leftp": [ {"type":"CONST","name":"?32?sh3e","addr":"(KD)","loc":"e,41:19,41:21","dtypep":"(S)"} ], "rightp": [ {"type":"CONST","name":"?32?sh0","addr":"(LD)","loc":"e,41:22,41:23","dtypep":"(N)"} ],"attrp": []} ], "rhsp": [ {"type":"XOR","name":"","addr":"(MD)","loc":"e,41:43,41:44","dtypep":"UNLINKED", "lhsp": [ {"type":"XOR","name":"","addr":"(ND)","loc":"e,41:34,41:35","dtypep":"UNLINKED", "lhsp": [ {"type":"SELBIT","name":"","addr":"(OD)","loc":"e,41:29,41:30","dtypep":"UNLINKED", "fromp": [ {"type":"PARSEREF","name":"crc","addr":"(PD)","loc":"e,41:26,41:29","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ], "bitp": [ {"type":"CONST","name":"?32?sh3f","addr":"(QD)","loc":"e,41:30,41:32","dtypep":"(S)"} ],"thsp": [],"attrp": []} ], "rhsp": [ {"type":"SELBIT","name":"","addr":"(RD)","loc":"e,41:39,41:40","dtypep":"UNLINKED", "fromp": [ {"type":"PARSEREF","name":"crc","addr":"(SD)","loc":"e,41:36,41:39","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ], "bitp": [ {"type":"CONST","name":"?32?sh2","addr":"(TD)","loc":"e,41:40,41:41","dtypep":"(UD)"} ],"thsp": [],"attrp": []} ]} ], "rhsp": [ {"type":"SELBIT","name":"","addr":"(VD)","loc":"e,41:48,41:49","dtypep":"UNLINKED", "fromp": [ {"type":"PARSEREF","name":"crc","addr":"(WD)","loc":"e,41:45,41:48","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ], "bitp": [ {"type":"CONST","name":"?32?sh0","addr":"(XD)","loc":"e,41:49,41:50","dtypep":"(N)"} ],"thsp": [],"attrp": []} ]} ]} ], "countp": [ {"type":"CONST","name":"32'h1","addr":"(YD)","loc":"e,41:14,41:15","dtypep":"(QC)"} ]} ], "lhsp": [ {"type":"PARSEREF","name":"crc","addr":"(ZD)","loc":"e,41:7,41:10","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ],"timingControlp": []}, {"type":"ASSIGNDLY","name":"","addr":"(AE)","loc":"e,42:11,42:13","dtypep":"UNLINKED", "rhsp": [ {"type":"XOR","name":"","addr":"(BE)","loc":"e,42:21,42:22","dtypep":"UNLINKED", "lhsp": [ {"type":"PARSEREF","name":"result","addr":"(CE)","loc":"e,42:14,42:20","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ], "rhsp": [ {"type":"REPLICATE","name":"","addr":"(DE)","loc":"e,42:23,42:24","dtypep":"(NC)", "srcp": [ {"type":"CONCAT","name":"","addr":"(EE)","loc":"e,42:33,42:34","dtypep":"UNLINKED", "lhsp": [ {"type":"SELEXTRACT","name":"","addr":"(FE)","loc":"e,42:27,42:28","dtypep":"UNLINKED", "fromp": [ {"type":"PARSEREF","name":"sum","addr":"(GE)","loc":"e,42:24,42:27","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ], "leftp": [ {"type":"CONST","name":"?32?sh3e","addr":"(HE)","loc":"e,42:28,42:30","dtypep":"(S)"} ], "rightp": [ {"type":"CONST","name":"?32?sh0","addr":"(IE)","loc":"e,42:31,42:32","dtypep":"(N)"} ],"attrp": []} ], "rhsp": [ {"type":"XOR","name":"","addr":"(JE)","loc":"e,42:52,42:53","dtypep":"UNLINKED", "lhsp": [ {"type":"XOR","name":"","addr":"(KE)","loc":"e,42:43,42:44","dtypep":"UNLINKED", "lhsp": [ {"type":"SELBIT","name":"","addr":"(LE)","loc":"e,42:38,42:39","dtypep":"UNLINKED", "fromp": [ {"type":"PARSEREF","name":"sum","addr":"(ME)","loc":"e,42:35,42:38","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ], "bitp": [ {"type":"CONST","name":"?32?sh3f","addr":"(NE)","loc":"e,42:39,42:41","dtypep":"(S)"} ],"thsp": [],"attrp": []} ], "rhsp": [ {"type":"SELBIT","name":"","addr":"(OE)","loc":"e,42:48,42:49","dtypep":"UNLINKED", "fromp": [ {"type":"PARSEREF","name":"sum","addr":"(PE)","loc":"e,42:45,42:48","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ], "bitp": [ {"type":"CONST","name":"?32?sh2","addr":"(QE)","loc":"e,42:49,42:50","dtypep":"(UD)"} ],"thsp": [],"attrp": []} ]} ], "rhsp": [ {"type":"SELBIT","name":"","addr":"(RE)","loc":"e,42:57,42:58","dtypep":"UNLINKED", "fromp": [ {"type":"PARSEREF","name":"sum","addr":"(SE)","loc":"e,42:54,42:57","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ], "bitp": [ {"type":"CONST","name":"?32?sh0","addr":"(TE)","loc":"e,42:58,42:59","dtypep":"(N)"} ],"thsp": [],"attrp": []} ]} ]} ], "countp": [ {"type":"CONST","name":"32'h1","addr":"(UE)","loc":"e,42:23,42:24","dtypep":"(QC)"} ]} ]} ], "lhsp": [ {"type":"PARSEREF","name":"sum","addr":"(VE)","loc":"e,42:7,42:10","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ],"timingControlp": []}, {"type":"IF","name":"","addr":"(WE)","loc":"e,43:7,43:9", "condp": [ {"type":"EQ","name":"","addr":"(XE)","loc":"e,43:15,43:17","dtypep":"(YE)", "lhsp": [ {"type":"PARSEREF","name":"cyc","addr":"(ZE)","loc":"e,43:11,43:14","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ], "rhsp": [ {"type":"CONST","name":"?32?sh0","addr":"(AF)","loc":"e,43:18,43:19","dtypep":"(N)"} ]} ], "thensp": [ {"type":"BEGIN","name":"","addr":"(BF)","loc":"e,43:21,43:26","implied":false,"needProcess":false,"unnamed":true,"declsp": [], "stmtsp": [ {"type":"ASSIGNDLY","name":"","addr":"(CF)","loc":"e,45:14,45:16","dtypep":"UNLINKED", "rhsp": [ {"type":"CONST","name":"64'h5aef0c8dd70a4497","addr":"(DF)","loc":"e,45:17,45:38","dtypep":"(EF)"} ], "lhsp": [ {"type":"PARSEREF","name":"crc","addr":"(FF)","loc":"e,45:10,45:13","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ],"timingControlp": []}, {"type":"ASSIGNDLY","name":"","addr":"(GF)","loc":"e,46:14,46:16","dtypep":"UNLINKED", "rhsp": [ {"type":"CONST","name":"'0","addr":"(HF)","loc":"e,46:17,46:19","dtypep":"(YE)"} ], "lhsp": [ {"type":"PARSEREF","name":"sum","addr":"(IF)","loc":"e,46:10,46:13","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ],"timingControlp": []} ]} ], "elsesp": [ {"type":"IF","name":"","addr":"(JF)","loc":"e,48:12,48:14", "condp": [ {"type":"LT","name":"","addr":"(KF)","loc":"e,48:20,48:21","dtypep":"(YE)", "lhsp": [ {"type":"PARSEREF","name":"cyc","addr":"(LF)","loc":"e,48:16,48:19","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ], "rhsp": [ {"type":"CONST","name":"?32?sha","addr":"(MF)","loc":"e,48:22,48:24","dtypep":"(NF)"} ]} ], "thensp": [ {"type":"BEGIN","name":"","addr":"(OF)","loc":"e,48:26,48:31","implied":false,"needProcess":false,"unnamed":true,"declsp": [], "stmtsp": [ {"type":"ASSIGNDLY","name":"","addr":"(PF)","loc":"e,49:14,49:16","dtypep":"UNLINKED", "rhsp": [ {"type":"CONST","name":"'0","addr":"(QF)","loc":"e,49:17,49:19","dtypep":"(YE)"} ], "lhsp": [ {"type":"PARSEREF","name":"sum","addr":"(RF)","loc":"e,49:10,49:13","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ],"timingControlp": []} ]} ], "elsesp": [ {"type":"IF","name":"","addr":"(SF)","loc":"e,51:12,51:14", "condp": [ {"type":"LT","name":"","addr":"(TF)","loc":"e,51:20,51:21","dtypep":"(YE)", "lhsp": [ {"type":"PARSEREF","name":"cyc","addr":"(UF)","loc":"e,51:16,51:19","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ], "rhsp": [ {"type":"CONST","name":"?32?sh5a","addr":"(VF)","loc":"e,51:22,51:24","dtypep":"(WF)"} ]} ], "thensp": [ {"type":"BEGIN","name":"","addr":"(XF)","loc":"e,51:26,51:31","implied":false,"needProcess":false,"unnamed":true,"declsp": [],"stmtsp": []} ], "elsesp": [ {"type":"IF","name":"","addr":"(YF)","loc":"e,53:12,53:14", "condp": [ {"type":"EQ","name":"","addr":"(ZF)","loc":"e,53:20,53:22","dtypep":"(YE)", "lhsp": [ {"type":"PARSEREF","name":"cyc","addr":"(AG)","loc":"e,53:16,53:19","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ], "rhsp": [ {"type":"CONST","name":"?32?sh63","addr":"(BG)","loc":"e,53:23,53:25","dtypep":"(WF)"} ]} ], "thensp": [ {"type":"BEGIN","name":"","addr":"(CG)","loc":"e,53:27,53:32","implied":false,"needProcess":false,"unnamed":true,"declsp": [], "stmtsp": [ {"type":"DISPLAY","name":"","addr":"(DG)","loc":"e,54:10,54:16", "fmtp": [ {"type":"SFORMATF","name":"","addr":"(EG)","loc":"e,54:10,54:16","dtypep":"(FG)", "exprsp": [ {"type":"CONST","name":"232'h5b2530745d206379633d3d253064206372633d25782073756d3d25780a","addr":"(GG)","loc":"e,54:17,54:49","dtypep":"(HG)"}, {"type":"TIME","name":"","addr":"(IG)","loc":"e,54:51,54:56","dtypep":"(JG)","timeunit":"NONE"}, {"type":"PARSEREF","name":"cyc","addr":"(KG)","loc":"e,54:58,54:61","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []}, {"type":"PARSEREF","name":"crc","addr":"(LG)","loc":"e,54:63,54:66","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []}, {"type":"PARSEREF","name":"sum","addr":"(MG)","loc":"e,54:68,54:71","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ],"scopeNamep": []} ],"filep": []}, {"type":"IF","name":"","addr":"(NG)","loc":"e,55:10,55:12", "condp": [ {"type":"NEQCASE","name":"","addr":"(OG)","loc":"e,55:18,55:21","dtypep":"(YE)", "lhsp": [ {"type":"PARSEREF","name":"crc","addr":"(PG)","loc":"e,55:14,55:17","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ], "rhsp": [ {"type":"CONST","name":"64'hc77bb9b3784ea091","addr":"(QG)","loc":"e,55:22,55:42","dtypep":"(EF)"} ]} ], "thensp": [ {"type":"STOP","name":"","addr":"(RG)","loc":"e,55:44,55:49","isFatal":false} ],"elsesp": []}, {"type":"IF","name":"","addr":"(SG)","loc":"e,58:10,58:12", "condp": [ {"type":"NEQCASE","name":"","addr":"(TG)","loc":"e,58:18,58:21","dtypep":"(YE)", "lhsp": [ {"type":"PARSEREF","name":"sum","addr":"(UG)","loc":"e,58:14,58:17","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ], "rhsp": [ {"type":"CONST","name":"64'h4afe43fb79d7b71e","addr":"(VG)","loc":"e,58:22,58:42","dtypep":"(EF)"} ]} ], "thensp": [ {"type":"STOP","name":"","addr":"(WG)","loc":"e,58:44,58:49","isFatal":false} ],"elsesp": []}, {"type":"DISPLAY","name":"","addr":"(XG)","loc":"e,59:10,59:16", "fmtp": [ {"type":"SFORMATF","name":"","addr":"(YG)","loc":"e,59:10,59:16","dtypep":"(FG)", "exprsp": [ {"type":"CONST","name":"168'h2a2d2a20416c6c2046696e6973686564202a2d2a0a","addr":"(ZG)","loc":"e,59:17,59:41","dtypep":"(AH)"} ],"scopeNamep": []} ],"filep": []}, {"type":"FINISH","name":"","addr":"(BH)","loc":"e,60:10,60:17"} ]} ],"elsesp": []} ]} ]} ]} ]} ]} ]} ]}, {"type":"MODULE","name":"Test","addr":"(SB)","loc":"e,66:8,66:12","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"Test","level":3,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"PORT","name":"out","addr":"(CH)","loc":"e,68:4,68:7","exprp": []}, {"type":"PORT","name":"clk","addr":"(DH)","loc":"e,70:4,70:7","exprp": []}, {"type":"PORT","name":"in","addr":"(EH)","loc":"e,70:9,70:11","exprp": []}, {"type":"VAR","name":"clk","addr":"(FH)","loc":"e,78:10,78:13","dtypep":"UNLINKED","origName":"clk","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", "childDTypep": [ {"type":"BASICDTYPE","name":"LOGIC_IMPLICIT","addr":"(GH)","loc":"e,78:10,78:13","dtypep":"(GH)","keyword":"LOGIC_IMPLICIT","generic":false,"rangep": []} ],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"in","addr":"(HH)","loc":"e,79:17,79:19","dtypep":"UNLINKED","origName":"in","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", "childDTypep": [ {"type":"BASICDTYPE","name":"logic","addr":"(IH)","loc":"e,79:10,79:11","dtypep":"(IH)","keyword":"logic","generic":false, "rangep": [ {"type":"RANGE","name":"","addr":"(JH)","loc":"e,79:10,79:11","ascending":false,"fromBracket":false, "leftp": [ {"type":"CONST","name":"?32?sh1f","addr":"(KH)","loc":"e,79:11,79:13","dtypep":"(DB)"} ], "rightp": [ {"type":"CONST","name":"?32?sh0","addr":"(LH)","loc":"e,79:14,79:15","dtypep":"(N)"} ]} ]} ],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"out","addr":"(MH)","loc":"e,80:22,80:25","dtypep":"UNLINKED","origName":"out","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", "childDTypep": [ {"type":"BASICDTYPE","name":"logic","addr":"(NH)","loc":"e,80:11,80:14","dtypep":"(NH)","keyword":"logic","generic":false, "rangep": [ {"type":"RANGE","name":"","addr":"(OH)","loc":"e,80:15,80:16","ascending":false,"fromBracket":false, "leftp": [ {"type":"CONST","name":"?32?sh1f","addr":"(PH)","loc":"e,80:16,80:18","dtypep":"(DB)"} ], "rightp": [ {"type":"CONST","name":"?32?sh0","addr":"(QH)","loc":"e,80:19,80:20","dtypep":"(N)"} ]} ]} ],"delayp": [],"valuep": [],"attrsp": []}, {"type":"ALWAYS","name":"","addr":"(RH)","loc":"e,82:4,82:10","keyword":"always","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"EVENTCONTROL","name":"","addr":"(SH)","loc":"e,82:11,82:12", "sentreep": [ {"type":"SENTREE","name":"","addr":"(TH)","loc":"e,82:11,82:12","isMulti":false, "sensesp": [ {"type":"SENITEM","name":"","addr":"(UH)","loc":"e,82:13,82:20","edgeType":"POS", "sensp": [ {"type":"PARSEREF","name":"clk","addr":"(VH)","loc":"e,82:21,82:24","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ],"condp": []} ]} ], "stmtsp": [ {"type":"BEGIN","name":"","addr":"(WH)","loc":"e,82:26,82:31","implied":false,"needProcess":false,"unnamed":true,"declsp": [], "stmtsp": [ {"type":"ASSIGNDLY","name":"","addr":"(XH)","loc":"e,83:11,83:13","dtypep":"UNLINKED", "rhsp": [ {"type":"PARSEREF","name":"in","addr":"(YH)","loc":"e,83:14,83:16","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ], "lhsp": [ {"type":"PARSEREF","name":"out","addr":"(ZH)","loc":"e,83:7,83:10","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ],"timingControlp": []}, {"type":"ASSERTCTL","name":"","addr":"(AI)","loc":"e,86:7,86:17", "controlTypep": [ {"type":"CONST","name":"32'h4","addr":"(BI)","loc":"e,86:7,86:17","dtypep":"(QC)"} ], "assertTypesp": [ {"type":"CONST","name":"32'hf","addr":"(CI)","loc":"e,86:7,86:17","dtypep":"(QC)"} ], "directiveTypesp": [ {"type":"CONST","name":"32'h7","addr":"(DI)","loc":"e,86:7,86:17","dtypep":"(QC)"} ]}, {"type":"ASSERTCTL","name":"","addr":"(EI)","loc":"e,87:7,87:18", "controlTypep": [ {"type":"CONST","name":"32'h5","addr":"(FI)","loc":"e,87:7,87:18","dtypep":"(QC)"} ], "assertTypesp": [ {"type":"CONST","name":"32'hf","addr":"(GI)","loc":"e,87:7,87:18","dtypep":"(QC)"} ], "directiveTypesp": [ {"type":"CONST","name":"32'h7","addr":"(HI)","loc":"e,87:7,87:18","dtypep":"(QC)"} ]}, {"type":"ASSERT","name":"","addr":"(II)","loc":"e,88:7,88:13","type":"[SIMPLE_IMMEDIATE]", "propp": [ {"type":"CONST","name":"?32?sh0","addr":"(JI)","loc":"e,88:14,88:15","dtypep":"(N)"} ],"sentreep": [],"failsp": [],"passsp": []}, {"type":"ASSERTCTL","name":"","addr":"(KI)","loc":"e,89:7,89:16", "controlTypep": [ {"type":"CONST","name":"32'h3","addr":"(LI)","loc":"e,89:7,89:16","dtypep":"(QC)"} ], "assertTypesp": [ {"type":"CONST","name":"32'hf","addr":"(MI)","loc":"e,89:7,89:16","dtypep":"(QC)"} ], "directiveTypesp": [ {"type":"CONST","name":"32'h7","addr":"(NI)","loc":"e,89:7,89:16","dtypep":"(QC)"} ]}, {"type":"ASSERTCTL","name":"","addr":"(OI)","loc":"e,90:7,90:21", "controlTypep": [ {"type":"CONST","name":"?32?sh3","addr":"(PI)","loc":"e,90:22,90:23","dtypep":"(UD)"} ], "assertTypesp": [ {"type":"CONST","name":"?32?sh8","addr":"(QI)","loc":"e,90:25,90:26","dtypep":"(NF)"} ],"directiveTypesp": []}, {"type":"BEGIN","name":"blk","addr":"(RI)","loc":"e,91:7,91:12","implied":false,"needProcess":false,"unnamed":false,"declsp": [], "stmtsp": [ {"type":"DISABLE","name":"","addr":"(SI)","loc":"e,92:10,92:17", "targetRefp": [ {"type":"PARSEREF","name":"blk","addr":"(TI)","loc":"e,92:18,92:21","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ]} ]} ]} ]} ]}, {"type":"INITIAL","name":"","addr":"(UI)","loc":"e,95:4,95:11","isSuspendable":false,"needProcess":false, "stmtsp": [ {"type":"BEGIN","name":"","addr":"(VI)","loc":"e,95:12,95:17","implied":false,"needProcess":false,"unnamed":true,"declsp": [], "stmtsp": [ {"type":"BEGIN","name":"assert_simple_immediate_else","addr":"(WI)","loc":"e,96:7,96:35","implied":false,"needProcess":false,"unnamed":false,"declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(XI)","loc":"e,96:37,96:43","type":"[SIMPLE_IMMEDIATE]", "propp": [ {"type":"CONST","name":"?32?sh0","addr":"(YI)","loc":"e,96:44,96:45","dtypep":"(N)"} ],"sentreep": [], "failsp": [ {"type":"DISPLAY","name":"","addr":"(ZI)","loc":"e,96:52,96:60", "fmtp": [ {"type":"SFORMATF","name":"","addr":"(AJ)","loc":"e,96:52,96:60","dtypep":"(FG)", "exprsp": [ {"type":"CONST","name":"32'h6661696c","addr":"(BJ)","loc":"e,96:61,96:67","dtypep":"(QC)"} ],"scopeNamep": []} ],"filep": []} ],"passsp": []} ]}, {"type":"BEGIN","name":"assert_simple_immediate_stmt","addr":"(CJ)","loc":"e,97:7,97:35","implied":false,"needProcess":false,"unnamed":false,"declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(DJ)","loc":"e,97:37,97:43","type":"[SIMPLE_IMMEDIATE]", "propp": [ {"type":"CONST","name":"?32?sh0","addr":"(EJ)","loc":"e,97:44,97:45","dtypep":"(N)"} ],"sentreep": [],"failsp": [], "passsp": [ {"type":"DISPLAY","name":"","addr":"(FJ)","loc":"e,97:47,97:55", "fmtp": [ {"type":"SFORMATF","name":"","addr":"(GJ)","loc":"e,97:47,97:55","dtypep":"(FG)", "exprsp": [ {"type":"CONST","name":"32'h70617373","addr":"(HJ)","loc":"e,97:56,97:62","dtypep":"(QC)"} ],"scopeNamep": []} ],"filep": []} ]} ]}, {"type":"BEGIN","name":"assert_simple_immediate_stmt_else","addr":"(IJ)","loc":"e,98:7,98:40","implied":false,"needProcess":false,"unnamed":false,"declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(JJ)","loc":"e,98:42,98:48","type":"[SIMPLE_IMMEDIATE]", "propp": [ {"type":"CONST","name":"?32?sh0","addr":"(KJ)","loc":"e,98:49,98:50","dtypep":"(N)"} ],"sentreep": [], "failsp": [ {"type":"DISPLAY","name":"","addr":"(LJ)","loc":"e,98:75,98:83", "fmtp": [ {"type":"SFORMATF","name":"","addr":"(MJ)","loc":"e,98:75,98:83","dtypep":"(FG)", "exprsp": [ {"type":"CONST","name":"32'h6661696c","addr":"(NJ)","loc":"e,98:84,98:90","dtypep":"(QC)"} ],"scopeNamep": []} ],"filep": []} ], "passsp": [ {"type":"DISPLAY","name":"","addr":"(OJ)","loc":"e,98:52,98:60", "fmtp": [ {"type":"SFORMATF","name":"","addr":"(PJ)","loc":"e,98:52,98:60","dtypep":"(FG)", "exprsp": [ {"type":"CONST","name":"32'h70617373","addr":"(QJ)","loc":"e,98:61,98:67","dtypep":"(QC)"} ],"scopeNamep": []} ],"filep": []} ]} ]}, {"type":"BEGIN","name":"assume_simple_immediate","addr":"(RJ)","loc":"e,100:7,100:30","implied":false,"needProcess":false,"unnamed":false,"declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(SJ)","loc":"e,100:32,100:38","type":"[SIMPLE_IMMEDIATE]", "propp": [ {"type":"CONST","name":"?32?sh0","addr":"(TJ)","loc":"e,100:39,100:40","dtypep":"(N)"} ],"sentreep": [],"failsp": [],"passsp": []} ]}, {"type":"BEGIN","name":"assume_simple_immediate_else","addr":"(UJ)","loc":"e,101:7,101:35","implied":false,"needProcess":false,"unnamed":false,"declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(VJ)","loc":"e,101:37,101:43","type":"[SIMPLE_IMMEDIATE]", "propp": [ {"type":"CONST","name":"?32?sh0","addr":"(WJ)","loc":"e,101:44,101:45","dtypep":"(N)"} ],"sentreep": [], "failsp": [ {"type":"DISPLAY","name":"","addr":"(XJ)","loc":"e,101:52,101:60", "fmtp": [ {"type":"SFORMATF","name":"","addr":"(YJ)","loc":"e,101:52,101:60","dtypep":"(FG)", "exprsp": [ {"type":"CONST","name":"32'h6661696c","addr":"(ZJ)","loc":"e,101:61,101:67","dtypep":"(QC)"} ],"scopeNamep": []} ],"filep": []} ],"passsp": []} ]}, {"type":"BEGIN","name":"assume_simple_immediate_stmt","addr":"(AK)","loc":"e,102:7,102:35","implied":false,"needProcess":false,"unnamed":false,"declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(BK)","loc":"e,102:37,102:43","type":"[SIMPLE_IMMEDIATE]", "propp": [ {"type":"CONST","name":"?32?sh0","addr":"(CK)","loc":"e,102:44,102:45","dtypep":"(N)"} ],"sentreep": [],"failsp": [], "passsp": [ {"type":"DISPLAY","name":"","addr":"(DK)","loc":"e,102:47,102:55", "fmtp": [ {"type":"SFORMATF","name":"","addr":"(EK)","loc":"e,102:47,102:55","dtypep":"(FG)", "exprsp": [ {"type":"CONST","name":"32'h70617373","addr":"(FK)","loc":"e,102:56,102:62","dtypep":"(QC)"} ],"scopeNamep": []} ],"filep": []} ]} ]}, {"type":"BEGIN","name":"assume_simple_immediate_stmt_else","addr":"(GK)","loc":"e,103:7,103:40","implied":false,"needProcess":false,"unnamed":false,"declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(HK)","loc":"e,103:42,103:48","type":"[SIMPLE_IMMEDIATE]", "propp": [ {"type":"CONST","name":"?32?sh0","addr":"(IK)","loc":"e,103:49,103:50","dtypep":"(N)"} ],"sentreep": [], "failsp": [ {"type":"DISPLAY","name":"","addr":"(JK)","loc":"e,103:75,103:83", "fmtp": [ {"type":"SFORMATF","name":"","addr":"(KK)","loc":"e,103:75,103:83","dtypep":"(FG)", "exprsp": [ {"type":"CONST","name":"32'h6661696c","addr":"(LK)","loc":"e,103:84,103:90","dtypep":"(QC)"} ],"scopeNamep": []} ],"filep": []} ], "passsp": [ {"type":"DISPLAY","name":"","addr":"(MK)","loc":"e,103:52,103:60", "fmtp": [ {"type":"SFORMATF","name":"","addr":"(NK)","loc":"e,103:52,103:60","dtypep":"(FG)", "exprsp": [ {"type":"CONST","name":"32'h70617373","addr":"(OK)","loc":"e,103:61,103:67","dtypep":"(QC)"} ],"scopeNamep": []} ],"filep": []} ]} ]} ]} ]}, {"type":"ALWAYS","name":"","addr":"(PK)","loc":"e,106:4,106:38","keyword":"always_comb","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"BEGIN","name":"assert_observed_deferred_immediate","addr":"(QK)","loc":"e,106:4,106:38","implied":true,"needProcess":false,"unnamed":false,"declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(RK)","loc":"e,106:40,106:46","type":"[OBSERVED_DEFERRED_IMMEDIATE]", "propp": [ {"type":"CONST","name":"?32?sh0","addr":"(SK)","loc":"e,106:51,106:52","dtypep":"(N)"} ],"sentreep": [],"failsp": [],"passsp": []} ]} ]}, {"type":"ALWAYS","name":"","addr":"(TK)","loc":"e,107:4,107:43","keyword":"always_comb","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"BEGIN","name":"assert_observed_deferred_immediate_else","addr":"(UK)","loc":"e,107:4,107:43","implied":true,"needProcess":false,"unnamed":false,"declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(VK)","loc":"e,107:45,107:51","type":"[OBSERVED_DEFERRED_IMMEDIATE]", "propp": [ {"type":"CONST","name":"?32?sh0","addr":"(WK)","loc":"e,107:56,107:57","dtypep":"(N)"} ],"sentreep": [], "failsp": [ {"type":"DISPLAY","name":"","addr":"(XK)","loc":"e,107:64,107:72", "fmtp": [ {"type":"SFORMATF","name":"","addr":"(YK)","loc":"e,107:64,107:72","dtypep":"(FG)", "exprsp": [ {"type":"CONST","name":"32'h6661696c","addr":"(ZK)","loc":"e,107:73,107:79","dtypep":"(QC)"} ],"scopeNamep": []} ],"filep": []} ],"passsp": []} ]} ]}, {"type":"ALWAYS","name":"","addr":"(AL)","loc":"e,108:4,108:43","keyword":"always_comb","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"BEGIN","name":"assert_observed_deferred_immediate_stmt","addr":"(BL)","loc":"e,108:4,108:43","implied":true,"needProcess":false,"unnamed":false,"declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(CL)","loc":"e,108:45,108:51","type":"[OBSERVED_DEFERRED_IMMEDIATE]", "propp": [ {"type":"CONST","name":"?32?sh0","addr":"(DL)","loc":"e,108:56,108:57","dtypep":"(N)"} ],"sentreep": [],"failsp": [], "passsp": [ {"type":"DISPLAY","name":"","addr":"(EL)","loc":"e,108:59,108:67", "fmtp": [ {"type":"SFORMATF","name":"","addr":"(FL)","loc":"e,108:59,108:67","dtypep":"(FG)", "exprsp": [ {"type":"CONST","name":"32'h70617373","addr":"(GL)","loc":"e,108:68,108:74","dtypep":"(QC)"} ],"scopeNamep": []} ],"filep": []} ]} ]} ]}, {"type":"ALWAYS","name":"","addr":"(HL)","loc":"e,109:4,109:48","keyword":"always_comb","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"BEGIN","name":"assert_observed_deferred_immediate_stmt_else","addr":"(IL)","loc":"e,109:4,109:48","implied":true,"needProcess":false,"unnamed":false,"declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(JL)","loc":"e,109:50,109:56","type":"[OBSERVED_DEFERRED_IMMEDIATE]", "propp": [ {"type":"CONST","name":"?32?sh0","addr":"(KL)","loc":"e,109:61,109:62","dtypep":"(N)"} ],"sentreep": [], "failsp": [ {"type":"DISPLAY","name":"","addr":"(LL)","loc":"e,109:87,109:95", "fmtp": [ {"type":"SFORMATF","name":"","addr":"(ML)","loc":"e,109:87,109:95","dtypep":"(FG)", "exprsp": [ {"type":"CONST","name":"32'h6661696c","addr":"(NL)","loc":"e,109:96,109:102","dtypep":"(QC)"} ],"scopeNamep": []} ],"filep": []} ], "passsp": [ {"type":"DISPLAY","name":"","addr":"(OL)","loc":"e,109:64,109:72", "fmtp": [ {"type":"SFORMATF","name":"","addr":"(PL)","loc":"e,109:64,109:72","dtypep":"(FG)", "exprsp": [ {"type":"CONST","name":"32'h70617373","addr":"(QL)","loc":"e,109:73,109:79","dtypep":"(QC)"} ],"scopeNamep": []} ],"filep": []} ]} ]} ]}, {"type":"ALWAYS","name":"","addr":"(RL)","loc":"e,111:4,111:38","keyword":"always_comb","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"BEGIN","name":"assume_observed_deferred_immediate","addr":"(SL)","loc":"e,111:4,111:38","implied":true,"needProcess":false,"unnamed":false,"declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(TL)","loc":"e,111:40,111:46","type":"[OBSERVED_DEFERRED_IMMEDIATE]", "propp": [ {"type":"CONST","name":"?32?sh0","addr":"(UL)","loc":"e,111:51,111:52","dtypep":"(N)"} ],"sentreep": [],"failsp": [],"passsp": []} ]} ]}, {"type":"ALWAYS","name":"","addr":"(VL)","loc":"e,112:4,112:43","keyword":"always_comb","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"BEGIN","name":"assume_observed_deferred_immediate_else","addr":"(WL)","loc":"e,112:4,112:43","implied":true,"needProcess":false,"unnamed":false,"declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(XL)","loc":"e,112:45,112:51","type":"[OBSERVED_DEFERRED_IMMEDIATE]", "propp": [ {"type":"CONST","name":"?32?sh0","addr":"(YL)","loc":"e,112:56,112:57","dtypep":"(N)"} ],"sentreep": [], "failsp": [ {"type":"DISPLAY","name":"","addr":"(ZL)","loc":"e,112:64,112:72", "fmtp": [ {"type":"SFORMATF","name":"","addr":"(AM)","loc":"e,112:64,112:72","dtypep":"(FG)", "exprsp": [ {"type":"CONST","name":"32'h6661696c","addr":"(BM)","loc":"e,112:73,112:79","dtypep":"(QC)"} ],"scopeNamep": []} ],"filep": []} ],"passsp": []} ]} ]}, {"type":"ALWAYS","name":"","addr":"(CM)","loc":"e,113:4,113:43","keyword":"always_comb","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"BEGIN","name":"assume_observed_deferred_immediate_stmt","addr":"(DM)","loc":"e,113:4,113:43","implied":true,"needProcess":false,"unnamed":false,"declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(EM)","loc":"e,113:45,113:51","type":"[OBSERVED_DEFERRED_IMMEDIATE]", "propp": [ {"type":"CONST","name":"?32?sh0","addr":"(FM)","loc":"e,113:56,113:57","dtypep":"(N)"} ],"sentreep": [],"failsp": [], "passsp": [ {"type":"DISPLAY","name":"","addr":"(GM)","loc":"e,113:59,113:67", "fmtp": [ {"type":"SFORMATF","name":"","addr":"(HM)","loc":"e,113:59,113:67","dtypep":"(FG)", "exprsp": [ {"type":"CONST","name":"32'h70617373","addr":"(IM)","loc":"e,113:68,113:74","dtypep":"(QC)"} ],"scopeNamep": []} ],"filep": []} ]} ]} ]}, {"type":"ALWAYS","name":"","addr":"(JM)","loc":"e,114:4,114:48","keyword":"always_comb","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"BEGIN","name":"assume_observed_deferred_immediate_stmt_else","addr":"(KM)","loc":"e,114:4,114:48","implied":true,"needProcess":false,"unnamed":false,"declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(LM)","loc":"e,114:50,114:56","type":"[OBSERVED_DEFERRED_IMMEDIATE]", "propp": [ {"type":"CONST","name":"?32?sh0","addr":"(MM)","loc":"e,114:61,114:62","dtypep":"(N)"} ],"sentreep": [], "failsp": [ {"type":"DISPLAY","name":"","addr":"(NM)","loc":"e,114:87,114:95", "fmtp": [ {"type":"SFORMATF","name":"","addr":"(OM)","loc":"e,114:87,114:95","dtypep":"(FG)", "exprsp": [ {"type":"CONST","name":"32'h6661696c","addr":"(PM)","loc":"e,114:96,114:102","dtypep":"(QC)"} ],"scopeNamep": []} ],"filep": []} ], "passsp": [ {"type":"DISPLAY","name":"","addr":"(QM)","loc":"e,114:64,114:72", "fmtp": [ {"type":"SFORMATF","name":"","addr":"(RM)","loc":"e,114:64,114:72","dtypep":"(FG)", "exprsp": [ {"type":"CONST","name":"32'h70617373","addr":"(SM)","loc":"e,114:73,114:79","dtypep":"(QC)"} ],"scopeNamep": []} ],"filep": []} ]} ]} ]}, {"type":"ALWAYS","name":"","addr":"(TM)","loc":"e,116:4,116:35","keyword":"always_comb","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"BEGIN","name":"assert_final_deferred_immediate","addr":"(UM)","loc":"e,116:4,116:35","implied":true,"needProcess":false,"unnamed":false,"declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(VM)","loc":"e,116:37,116:43","type":"[FINAL_DEFERRED_IMMEDIATE]", "propp": [ {"type":"CONST","name":"?32?sh0","addr":"(WM)","loc":"e,116:51,116:52","dtypep":"(N)"} ],"sentreep": [],"failsp": [],"passsp": []} ]} ]}, {"type":"ALWAYS","name":"","addr":"(XM)","loc":"e,117:4,117:40","keyword":"always_comb","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"BEGIN","name":"assert_final_deferred_immediate_else","addr":"(YM)","loc":"e,117:4,117:40","implied":true,"needProcess":false,"unnamed":false,"declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(ZM)","loc":"e,117:42,117:48","type":"[FINAL_DEFERRED_IMMEDIATE]", "propp": [ {"type":"CONST","name":"?32?sh0","addr":"(AN)","loc":"e,117:56,117:57","dtypep":"(N)"} ],"sentreep": [], "failsp": [ {"type":"DISPLAY","name":"","addr":"(BN)","loc":"e,117:64,117:72", "fmtp": [ {"type":"SFORMATF","name":"","addr":"(CN)","loc":"e,117:64,117:72","dtypep":"(FG)", "exprsp": [ {"type":"CONST","name":"32'h6661696c","addr":"(DN)","loc":"e,117:73,117:79","dtypep":"(QC)"} ],"scopeNamep": []} ],"filep": []} ],"passsp": []} ]} ]}, {"type":"ALWAYS","name":"","addr":"(EN)","loc":"e,118:4,118:40","keyword":"always_comb","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"BEGIN","name":"assert_final_deferred_immediate_stmt","addr":"(FN)","loc":"e,118:4,118:40","implied":true,"needProcess":false,"unnamed":false,"declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(GN)","loc":"e,118:42,118:48","type":"[FINAL_DEFERRED_IMMEDIATE]", "propp": [ {"type":"CONST","name":"?32?sh0","addr":"(HN)","loc":"e,118:56,118:57","dtypep":"(N)"} ],"sentreep": [],"failsp": [], "passsp": [ {"type":"DISPLAY","name":"","addr":"(IN)","loc":"e,118:59,118:67", "fmtp": [ {"type":"SFORMATF","name":"","addr":"(JN)","loc":"e,118:59,118:67","dtypep":"(FG)", "exprsp": [ {"type":"CONST","name":"32'h70617373","addr":"(KN)","loc":"e,118:68,118:74","dtypep":"(QC)"} ],"scopeNamep": []} ],"filep": []} ]} ]} ]}, {"type":"ALWAYS","name":"","addr":"(LN)","loc":"e,119:4,119:45","keyword":"always_comb","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"BEGIN","name":"assert_final_deferred_immediate_stmt_else","addr":"(MN)","loc":"e,119:4,119:45","implied":true,"needProcess":false,"unnamed":false,"declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(NN)","loc":"e,119:47,119:53","type":"[FINAL_DEFERRED_IMMEDIATE]", "propp": [ {"type":"CONST","name":"?32?sh0","addr":"(ON)","loc":"e,119:61,119:62","dtypep":"(N)"} ],"sentreep": [], "failsp": [ {"type":"DISPLAY","name":"","addr":"(PN)","loc":"e,119:87,119:95", "fmtp": [ {"type":"SFORMATF","name":"","addr":"(QN)","loc":"e,119:87,119:95","dtypep":"(FG)", "exprsp": [ {"type":"CONST","name":"32'h6661696c","addr":"(RN)","loc":"e,119:96,119:102","dtypep":"(QC)"} ],"scopeNamep": []} ],"filep": []} ], "passsp": [ {"type":"DISPLAY","name":"","addr":"(SN)","loc":"e,119:64,119:72", "fmtp": [ {"type":"SFORMATF","name":"","addr":"(TN)","loc":"e,119:64,119:72","dtypep":"(FG)", "exprsp": [ {"type":"CONST","name":"32'h70617373","addr":"(UN)","loc":"e,119:73,119:79","dtypep":"(QC)"} ],"scopeNamep": []} ],"filep": []} ]} ]} ]}, {"type":"ALWAYS","name":"","addr":"(VN)","loc":"e,121:4,121:35","keyword":"always_comb","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"BEGIN","name":"assume_final_deferred_immediate","addr":"(WN)","loc":"e,121:4,121:35","implied":true,"needProcess":false,"unnamed":false,"declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(XN)","loc":"e,121:37,121:43","type":"[FINAL_DEFERRED_IMMEDIATE]", "propp": [ {"type":"CONST","name":"?32?sh0","addr":"(YN)","loc":"e,121:51,121:52","dtypep":"(N)"} ],"sentreep": [],"failsp": [],"passsp": []} ]} ]}, {"type":"ALWAYS","name":"","addr":"(ZN)","loc":"e,122:4,122:40","keyword":"always_comb","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"BEGIN","name":"assume_final_deferred_immediate_else","addr":"(AO)","loc":"e,122:4,122:40","implied":true,"needProcess":false,"unnamed":false,"declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(BO)","loc":"e,122:42,122:48","type":"[FINAL_DEFERRED_IMMEDIATE]", "propp": [ {"type":"CONST","name":"?32?sh0","addr":"(CO)","loc":"e,122:56,122:57","dtypep":"(N)"} ],"sentreep": [], "failsp": [ {"type":"DISPLAY","name":"","addr":"(DO)","loc":"e,122:64,122:72", "fmtp": [ {"type":"SFORMATF","name":"","addr":"(EO)","loc":"e,122:64,122:72","dtypep":"(FG)", "exprsp": [ {"type":"CONST","name":"32'h6661696c","addr":"(FO)","loc":"e,122:73,122:79","dtypep":"(QC)"} ],"scopeNamep": []} ],"filep": []} ],"passsp": []} ]} ]}, {"type":"ALWAYS","name":"","addr":"(GO)","loc":"e,123:4,123:40","keyword":"always_comb","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"BEGIN","name":"assume_final_deferred_immediate_stmt","addr":"(HO)","loc":"e,123:4,123:40","implied":true,"needProcess":false,"unnamed":false,"declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(IO)","loc":"e,123:42,123:48","type":"[FINAL_DEFERRED_IMMEDIATE]", "propp": [ {"type":"CONST","name":"?32?sh0","addr":"(JO)","loc":"e,123:56,123:57","dtypep":"(N)"} ],"sentreep": [],"failsp": [], "passsp": [ {"type":"DISPLAY","name":"","addr":"(KO)","loc":"e,123:59,123:67", "fmtp": [ {"type":"SFORMATF","name":"","addr":"(LO)","loc":"e,123:59,123:67","dtypep":"(FG)", "exprsp": [ {"type":"CONST","name":"32'h70617373","addr":"(MO)","loc":"e,123:68,123:74","dtypep":"(QC)"} ],"scopeNamep": []} ],"filep": []} ]} ]} ]}, {"type":"ALWAYS","name":"","addr":"(NO)","loc":"e,124:4,124:45","keyword":"always_comb","isSuspendable":false,"needProcess":false,"sentreep": [], "stmtsp": [ {"type":"BEGIN","name":"assume_final_deferred_immediate_stmt_else","addr":"(OO)","loc":"e,124:4,124:45","implied":true,"needProcess":false,"unnamed":false,"declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(PO)","loc":"e,124:47,124:53","type":"[FINAL_DEFERRED_IMMEDIATE]", "propp": [ {"type":"CONST","name":"?32?sh0","addr":"(QO)","loc":"e,124:61,124:62","dtypep":"(N)"} ],"sentreep": [], "failsp": [ {"type":"DISPLAY","name":"","addr":"(RO)","loc":"e,124:87,124:95", "fmtp": [ {"type":"SFORMATF","name":"","addr":"(SO)","loc":"e,124:87,124:95","dtypep":"(FG)", "exprsp": [ {"type":"CONST","name":"32'h6661696c","addr":"(TO)","loc":"e,124:96,124:102","dtypep":"(QC)"} ],"scopeNamep": []} ],"filep": []} ], "passsp": [ {"type":"DISPLAY","name":"","addr":"(UO)","loc":"e,124:64,124:72", "fmtp": [ {"type":"SFORMATF","name":"","addr":"(VO)","loc":"e,124:64,124:72","dtypep":"(FG)", "exprsp": [ {"type":"CONST","name":"32'h70617373","addr":"(WO)","loc":"e,124:73,124:79","dtypep":"(QC)"} ],"scopeNamep": []} ],"filep": []} ]} ]} ]}, {"type":"PROPERTY","name":"prop","addr":"(XO)","loc":"e,126:13,126:17","dtypep":"UNLINKED","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"prop","fvarp": [],"classOrPackagep": [], "stmtsp": [ {"type":"PROPSPEC","name":"","addr":"(YO)","loc":"e,127:7,127:8","dtypep":"UNLINKED", "sensesp": [ {"type":"SENITEM","name":"","addr":"(ZO)","loc":"e,127:9,127:16","edgeType":"POS", "sensp": [ {"type":"PARSEREF","name":"clk","addr":"(AP)","loc":"e,127:17,127:20","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ],"condp": []} ],"disablep": [], "propp": [ {"type":"CONST","name":"?32?sh0","addr":"(BP)","loc":"e,127:22,127:23","dtypep":"(N)"} ]} ],"scopeNamep": []}, {"type":"BEGIN","name":"assert_concurrent","addr":"(CP)","loc":"e,130:4,130:21","implied":true,"needProcess":false,"unnamed":false,"declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(DP)","loc":"e,130:23,130:29","type":"[CONCURRENT]", "propp": [ {"type":"SAMPLED","name":"","addr":"(EP)","loc":"e,130:23,130:29","dtypep":"UNLINKED", "exprp": [ {"type":"PROPSPEC","name":"","addr":"(FP)","loc":"e,130:40,130:44","dtypep":"UNLINKED","sensesp": [],"disablep": [], "propp": [ {"type":"PARSEREF","name":"prop","addr":"(GP)","loc":"e,130:40,130:44","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ]} ]} ],"sentreep": [],"failsp": [],"passsp": []} ]}, {"type":"BEGIN","name":"assert_concurrent_else","addr":"(HP)","loc":"e,131:4,131:26","implied":true,"needProcess":false,"unnamed":false,"declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(IP)","loc":"e,131:28,131:34","type":"[CONCURRENT]", "propp": [ {"type":"SAMPLED","name":"","addr":"(JP)","loc":"e,131:28,131:34","dtypep":"UNLINKED", "exprp": [ {"type":"PROPSPEC","name":"","addr":"(KP)","loc":"e,131:44,131:48","dtypep":"UNLINKED","sensesp": [],"disablep": [], "propp": [ {"type":"PARSEREF","name":"prop","addr":"(LP)","loc":"e,131:44,131:48","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ]} ]} ],"sentreep": [], "failsp": [ {"type":"DISPLAY","name":"","addr":"(MP)","loc":"e,131:55,131:63", "fmtp": [ {"type":"SFORMATF","name":"","addr":"(NP)","loc":"e,131:55,131:63","dtypep":"(FG)", "exprsp": [ {"type":"CONST","name":"32'h6661696c","addr":"(OP)","loc":"e,131:64,131:70","dtypep":"(QC)"} ],"scopeNamep": []} ],"filep": []} ],"passsp": []} ]}, {"type":"BEGIN","name":"assert_concurrent_stmt","addr":"(PP)","loc":"e,132:4,132:26","implied":true,"needProcess":false,"unnamed":false,"declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(QP)","loc":"e,132:28,132:34","type":"[CONCURRENT]", "propp": [ {"type":"SAMPLED","name":"","addr":"(RP)","loc":"e,132:28,132:34","dtypep":"UNLINKED", "exprp": [ {"type":"PROPSPEC","name":"","addr":"(SP)","loc":"e,132:44,132:48","dtypep":"UNLINKED","sensesp": [],"disablep": [], "propp": [ {"type":"PARSEREF","name":"prop","addr":"(TP)","loc":"e,132:44,132:48","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ]} ]} ],"sentreep": [],"failsp": [], "passsp": [ {"type":"DISPLAY","name":"","addr":"(UP)","loc":"e,132:50,132:58", "fmtp": [ {"type":"SFORMATF","name":"","addr":"(VP)","loc":"e,132:50,132:58","dtypep":"(FG)", "exprsp": [ {"type":"CONST","name":"32'h70617373","addr":"(WP)","loc":"e,132:59,132:65","dtypep":"(QC)"} ],"scopeNamep": []} ],"filep": []} ]} ]}, {"type":"BEGIN","name":"assert_concurrent_stmt_else","addr":"(XP)","loc":"e,133:4,133:31","implied":true,"needProcess":false,"unnamed":false,"declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(YP)","loc":"e,133:33,133:39","type":"[CONCURRENT]", "propp": [ {"type":"SAMPLED","name":"","addr":"(ZP)","loc":"e,133:33,133:39","dtypep":"UNLINKED", "exprp": [ {"type":"PROPSPEC","name":"","addr":"(AQ)","loc":"e,133:49,133:53","dtypep":"UNLINKED","sensesp": [],"disablep": [], "propp": [ {"type":"PARSEREF","name":"prop","addr":"(BQ)","loc":"e,133:49,133:53","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ]} ]} ],"sentreep": [], "failsp": [ {"type":"DISPLAY","name":"","addr":"(CQ)","loc":"e,133:78,133:86", "fmtp": [ {"type":"SFORMATF","name":"","addr":"(DQ)","loc":"e,133:78,133:86","dtypep":"(FG)", "exprsp": [ {"type":"CONST","name":"32'h6661696c","addr":"(EQ)","loc":"e,133:87,133:93","dtypep":"(QC)"} ],"scopeNamep": []} ],"filep": []} ], "passsp": [ {"type":"DISPLAY","name":"","addr":"(FQ)","loc":"e,133:55,133:63", "fmtp": [ {"type":"SFORMATF","name":"","addr":"(GQ)","loc":"e,133:55,133:63","dtypep":"(FG)", "exprsp": [ {"type":"CONST","name":"32'h70617373","addr":"(HQ)","loc":"e,133:64,133:70","dtypep":"(QC)"} ],"scopeNamep": []} ],"filep": []} ]} ]}, {"type":"BEGIN","name":"assume_concurrent","addr":"(IQ)","loc":"e,135:4,135:21","implied":true,"needProcess":false,"unnamed":false,"declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(JQ)","loc":"e,135:23,135:29","type":"[CONCURRENT]", "propp": [ {"type":"SAMPLED","name":"","addr":"(KQ)","loc":"e,135:23,135:29","dtypep":"UNLINKED", "exprp": [ {"type":"PROPSPEC","name":"","addr":"(LQ)","loc":"e,135:39,135:43","dtypep":"UNLINKED","sensesp": [],"disablep": [], "propp": [ {"type":"PARSEREF","name":"prop","addr":"(MQ)","loc":"e,135:39,135:43","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ]} ]} ],"sentreep": [],"failsp": [],"passsp": []} ]}, {"type":"BEGIN","name":"assume_concurrent_else","addr":"(NQ)","loc":"e,136:4,136:26","implied":true,"needProcess":false,"unnamed":false,"declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(OQ)","loc":"e,136:28,136:34","type":"[CONCURRENT]", "propp": [ {"type":"SAMPLED","name":"","addr":"(PQ)","loc":"e,136:28,136:34","dtypep":"UNLINKED", "exprp": [ {"type":"PROPSPEC","name":"","addr":"(QQ)","loc":"e,136:44,136:48","dtypep":"UNLINKED","sensesp": [],"disablep": [], "propp": [ {"type":"PARSEREF","name":"prop","addr":"(RQ)","loc":"e,136:44,136:48","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ]} ]} ],"sentreep": [], "failsp": [ {"type":"DISPLAY","name":"","addr":"(SQ)","loc":"e,136:55,136:63", "fmtp": [ {"type":"SFORMATF","name":"","addr":"(TQ)","loc":"e,136:55,136:63","dtypep":"(FG)", "exprsp": [ {"type":"CONST","name":"32'h6661696c","addr":"(UQ)","loc":"e,136:64,136:70","dtypep":"(QC)"} ],"scopeNamep": []} ],"filep": []} ],"passsp": []} ]}, {"type":"BEGIN","name":"assume_concurrent_stmt","addr":"(VQ)","loc":"e,137:4,137:26","implied":true,"needProcess":false,"unnamed":false,"declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(WQ)","loc":"e,137:28,137:34","type":"[CONCURRENT]", "propp": [ {"type":"SAMPLED","name":"","addr":"(XQ)","loc":"e,137:28,137:34","dtypep":"UNLINKED", "exprp": [ {"type":"PROPSPEC","name":"","addr":"(YQ)","loc":"e,137:44,137:48","dtypep":"UNLINKED","sensesp": [],"disablep": [], "propp": [ {"type":"PARSEREF","name":"prop","addr":"(ZQ)","loc":"e,137:44,137:48","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ]} ]} ],"sentreep": [],"failsp": [], "passsp": [ {"type":"DISPLAY","name":"","addr":"(AR)","loc":"e,137:50,137:58", "fmtp": [ {"type":"SFORMATF","name":"","addr":"(BR)","loc":"e,137:50,137:58","dtypep":"(FG)", "exprsp": [ {"type":"CONST","name":"32'h70617373","addr":"(CR)","loc":"e,137:59,137:65","dtypep":"(QC)"} ],"scopeNamep": []} ],"filep": []} ]} ]}, {"type":"BEGIN","name":"assume_concurrent_stmt_else","addr":"(DR)","loc":"e,138:4,138:31","implied":true,"needProcess":false,"unnamed":false,"declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(ER)","loc":"e,138:33,138:39","type":"[CONCURRENT]", "propp": [ {"type":"SAMPLED","name":"","addr":"(FR)","loc":"e,138:33,138:39","dtypep":"UNLINKED", "exprp": [ {"type":"PROPSPEC","name":"","addr":"(GR)","loc":"e,138:49,138:53","dtypep":"UNLINKED","sensesp": [],"disablep": [], "propp": [ {"type":"PARSEREF","name":"prop","addr":"(HR)","loc":"e,138:49,138:53","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ]} ]} ],"sentreep": [], "failsp": [ {"type":"DISPLAY","name":"","addr":"(IR)","loc":"e,138:78,138:86", "fmtp": [ {"type":"SFORMATF","name":"","addr":"(JR)","loc":"e,138:78,138:86","dtypep":"(FG)", "exprsp": [ {"type":"CONST","name":"32'h6661696c","addr":"(KR)","loc":"e,138:87,138:93","dtypep":"(QC)"} ],"scopeNamep": []} ],"filep": []} ], "passsp": [ {"type":"DISPLAY","name":"","addr":"(LR)","loc":"e,138:55,138:63", "fmtp": [ {"type":"SFORMATF","name":"","addr":"(MR)","loc":"e,138:55,138:63","dtypep":"(FG)", "exprsp": [ {"type":"CONST","name":"32'h70617373","addr":"(NR)","loc":"e,138:64,138:70","dtypep":"(QC)"} ],"scopeNamep": []} ],"filep": []} ]} ]}, {"type":"BEGIN","name":"cover_concurrent","addr":"(OR)","loc":"e,140:4,140:20","implied":true,"needProcess":false,"unnamed":false,"declsp": [], "stmtsp": [ {"type":"COVER","name":"","addr":"(PR)","loc":"e,140:22,140:27","type":"[CONCURRENT]", "propp": [ {"type":"PROPSPEC","name":"","addr":"(QR)","loc":"e,140:37,140:41","dtypep":"UNLINKED","sensesp": [],"disablep": [], "propp": [ {"type":"PARSEREF","name":"prop","addr":"(RR)","loc":"e,140:37,140:41","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ]} ],"sentreep": [],"coverincsp": [],"passsp": []} ]}, {"type":"BEGIN","name":"cover_concurrent_stmt","addr":"(SR)","loc":"e,141:4,141:25","implied":true,"needProcess":false,"unnamed":false,"declsp": [], "stmtsp": [ {"type":"COVER","name":"","addr":"(TR)","loc":"e,141:27,141:32","type":"[CONCURRENT]", "propp": [ {"type":"PROPSPEC","name":"","addr":"(UR)","loc":"e,141:42,141:46","dtypep":"UNLINKED","sensesp": [],"disablep": [], "propp": [ {"type":"PARSEREF","name":"prop","addr":"(VR)","loc":"e,141:42,141:46","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ]} ],"sentreep": [],"coverincsp": [], "passsp": [ {"type":"DISPLAY","name":"","addr":"(WR)","loc":"e,141:48,141:56", "fmtp": [ {"type":"SFORMATF","name":"","addr":"(XR)","loc":"e,141:48,141:56","dtypep":"(FG)", "exprsp": [ {"type":"CONST","name":"32'h70617373","addr":"(YR)","loc":"e,141:57,141:63","dtypep":"(QC)"} ],"scopeNamep": []} ],"filep": []} ]} ]}, {"type":"RESTRICT","name":"","addr":"(ZR)","loc":"e,143:4,143:12","type":"[INTERNAL]", "propp": [ {"type":"PROPSPEC","name":"","addr":"(AS)","loc":"e,143:23,143:27","dtypep":"UNLINKED","sensesp": [],"disablep": [], "propp": [ {"type":"PARSEREF","name":"prop","addr":"(BS)","loc":"e,143:23,143:27","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ]} ],"sentreep": [],"passsp": []} ]}, {"type":"PACKAGE","name":"$unit","addr":"(E)","loc":"a,0:0,0:0","origName":"__024unit","level":3,"modPublic":false,"inLibrary":true,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"PACKAGEIMPORT","name":"*","addr":"(CS)","loc":"d,31:9,31:12","packagep":"(F)","resolvedClassp": []} ]}, {"type":"PACKAGE","name":"std","addr":"(F)","loc":"d,31:9,31:12","origName":"std","level":4,"modPublic":false,"inLibrary":true,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"CLASS","name":"mailbox","addr":"(DS)","loc":"d,32:3,32:8","isExtended":false,"isInterfaceClass":false,"isVirtual":false,"origName":"mailbox","level":5,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","classOrPackagep":"UNLINKED","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"T","addr":"(ES)","loc":"d,33:12,33:13","dtypep":"UNLINKED","origName":"T","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"GPARAM","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":true,"isParam":true,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", "childDTypep": [ {"type":"PARSETYPEDTYPE","name":"","addr":"(FS)","loc":"d,33:7,33:11","dtypep":"UNLINKED","generic":false} ],"delayp": [],"valuep": [],"attrsp": []}, {"type":"TYPEDEFFWD","name":"T","addr":"(GS)","loc":"d,33:12,33:13","fwdType":"none"}, {"type":"VAR","name":"m_bound","addr":"(HS)","loc":"d,35:19,35:26","dtypep":"UNLINKED","origName":"m_bound","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"VAR","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", "childDTypep": [ {"type":"BASICDTYPE","name":"int","addr":"(IS)","loc":"d,35:15,35:18","dtypep":"(IS)","keyword":"int","range":"31:0","generic":false,"rangep": []} ],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"m_queue","addr":"(JS)","loc":"d,36:17,36:24","dtypep":"UNLINKED","origName":"m_queue","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"VAR","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", "childDTypep": [ {"type":"BRACKETARRAYDTYPE","name":"","addr":"(KS)","loc":"d,36:24,36:25","dtypep":"UNLINKED","generic":false, "childDTypep": [ {"type":"REFDTYPE","name":"T","addr":"(LS)","loc":"d,36:15,36:16","dtypep":"UNLINKED","generic":false,"typedefp":"UNLINKED","refDTypep":"UNLINKED","classOrPackagep":"UNLINKED","typeofp": [],"classOrPackageOpp": [],"paramsp": []} ], "elementsp": [ {"type":"UNBOUNDED","name":"","addr":"(MS)","loc":"d,36:25,36:26","dtypep":"(NS)"} ]} ],"delayp": [],"valuep": [],"attrsp": []}, {"type":"FUNC","name":"new","addr":"(OS)","loc":"d,38:14,38:17","dtypep":"UNLINKED","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"new","fvarp": [],"classOrPackagep": [], "stmtsp": [ {"type":"VAR","name":"bound","addr":"(PS)","loc":"d,38:22,38:27","dtypep":"UNLINKED","origName":"bound","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", "childDTypep": [ {"type":"BASICDTYPE","name":"int","addr":"(QS)","loc":"d,38:18,38:21","dtypep":"(QS)","keyword":"int","range":"31:0","generic":false,"rangep": []} ],"delayp": [], "valuep": [ {"type":"CONST","name":"?32?sh0","addr":"(RS)","loc":"d,38:30,38:31","dtypep":"(N)"} ],"attrsp": []}, {"type":"ASSIGN","name":"","addr":"(SS)","loc":"d,39:15,39:16","dtypep":"UNLINKED", "rhsp": [ {"type":"PARSEREF","name":"bound","addr":"(TS)","loc":"d,39:17,39:22","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ], "lhsp": [ {"type":"PARSEREF","name":"m_bound","addr":"(US)","loc":"d,39:7,39:14","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ],"timingControlp": []} ],"scopeNamep": []}, {"type":"FUNC","name":"num","addr":"(VS)","loc":"d,42:18,42:21","dtypep":"UNLINKED","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"num", "fvarp": [ {"type":"BASICDTYPE","name":"int","addr":"(WS)","loc":"d,42:14,42:17","dtypep":"(WS)","keyword":"int","range":"31:0","generic":false,"rangep": []} ],"classOrPackagep": [], "stmtsp": [ {"type":"RETURN","name":"","addr":"(XS)","loc":"d,43:7,43:13", "lhsp": [ {"type":"DOT","name":"","addr":"(YS)","loc":"d,43:21,43:22","dtypep":"UNLINKED","colon":false, "lhsp": [ {"type":"PARSEREF","name":"m_queue","addr":"(ZS)","loc":"d,43:14,43:21","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ], "rhsp": [ {"type":"FUNCREF","name":"size","addr":"(AT)","loc":"d,43:22,43:26","dtypep":"UNLINKED","dotted":"","taskp":"UNLINKED","classOrPackagep":"UNLINKED","namep": [],"pinsp": [],"scopeNamep": []} ]} ]} ],"scopeNamep": []}, {"type":"TASK","name":"put","addr":"(BT)","loc":"d,46:10,46:13","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"put","fvarp": [],"classOrPackagep": [], "stmtsp": [ {"type":"VAR","name":"message","addr":"(CT)","loc":"d,46:16,46:23","dtypep":"UNLINKED","origName":"message","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", "childDTypep": [ {"type":"REFDTYPE","name":"T","addr":"(DT)","loc":"d,46:14,46:15","dtypep":"UNLINKED","generic":false,"typedefp":"UNLINKED","refDTypep":"UNLINKED","classOrPackagep":"UNLINKED","typeofp": [],"classOrPackageOpp": [],"paramsp": []} ],"delayp": [],"valuep": [],"attrsp": []} ],"scopeNamep": []}, {"type":"FUNC","name":"try_put","addr":"(ET)","loc":"d,54:18,54:25","dtypep":"UNLINKED","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"try_put", "fvarp": [ {"type":"BASICDTYPE","name":"int","addr":"(FT)","loc":"d,54:14,54:17","dtypep":"(FT)","keyword":"int","range":"31:0","generic":false,"rangep": []} ],"classOrPackagep": [], "stmtsp": [ {"type":"VAR","name":"message","addr":"(GT)","loc":"d,54:28,54:35","dtypep":"UNLINKED","origName":"message","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", "childDTypep": [ {"type":"REFDTYPE","name":"T","addr":"(HT)","loc":"d,54:26,54:27","dtypep":"UNLINKED","generic":false,"typedefp":"UNLINKED","refDTypep":"UNLINKED","classOrPackagep":"UNLINKED","typeofp": [],"classOrPackageOpp": [],"paramsp": []} ],"delayp": [],"valuep": [],"attrsp": []}, {"type":"IF","name":"","addr":"(IT)","loc":"d,55:7,55:9", "condp": [ {"type":"LOGOR","name":"","addr":"(JT)","loc":"d,55:24,55:26","dtypep":"(YE)", "lhsp": [ {"type":"EQ","name":"","addr":"(KT)","loc":"d,55:19,55:21","dtypep":"(YE)", "lhsp": [ {"type":"PARSEREF","name":"m_bound","addr":"(LT)","loc":"d,55:11,55:18","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ], "rhsp": [ {"type":"CONST","name":"?32?sh0","addr":"(MT)","loc":"d,55:22,55:23","dtypep":"(N)"} ]} ], "rhsp": [ {"type":"LT","name":"","addr":"(NT)","loc":"d,55:33,55:34","dtypep":"(YE)", "lhsp": [ {"type":"FUNCREF","name":"num","addr":"(OT)","loc":"d,55:27,55:30","dtypep":"UNLINKED","dotted":"","taskp":"UNLINKED","classOrPackagep":"UNLINKED","namep": [],"pinsp": [],"scopeNamep": []} ], "rhsp": [ {"type":"PARSEREF","name":"m_bound","addr":"(PT)","loc":"d,55:35,55:42","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ]} ]} ], "thensp": [ {"type":"BEGIN","name":"","addr":"(QT)","loc":"d,55:44,55:49","implied":false,"needProcess":false,"unnamed":true,"declsp": [], "stmtsp": [ {"type":"STMTEXPR","name":"","addr":"(RT)","loc":"d,56:16,56:17", "exprp": [ {"type":"DOT","name":"","addr":"(ST)","loc":"d,56:16,56:17","dtypep":"UNLINKED","colon":false, "lhsp": [ {"type":"PARSEREF","name":"m_queue","addr":"(TT)","loc":"d,56:9,56:16","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ], "rhsp": [ {"type":"TASKREF","name":"push_back","addr":"(UT)","loc":"d,56:17,56:26","dtypep":"(VT)","dotted":"","taskp":"UNLINKED","classOrPackagep":"UNLINKED","namep": [], "pinsp": [ {"type":"ARG","name":"","addr":"(WT)","loc":"d,56:27,56:34", "exprp": [ {"type":"PARSEREF","name":"message","addr":"(XT)","loc":"d,56:27,56:34","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ]} ],"scopeNamep": []} ]} ]}, {"type":"RETURN","name":"","addr":"(YT)","loc":"d,57:9,57:15", "lhsp": [ {"type":"CONST","name":"?32?sh1","addr":"(ZT)","loc":"d,57:16,57:17","dtypep":"(N)"} ]} ]} ],"elsesp": []}, {"type":"RETURN","name":"","addr":"(AU)","loc":"d,59:7,59:13", "lhsp": [ {"type":"CONST","name":"?32?sh0","addr":"(BU)","loc":"d,59:14,59:15","dtypep":"(N)"} ]} ],"scopeNamep": []}, {"type":"TASK","name":"get","addr":"(CU)","loc":"d,62:10,62:13","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"get","fvarp": [],"classOrPackagep": [], "stmtsp": [ {"type":"VAR","name":"message","addr":"(DU)","loc":"d,62:20,62:27","dtypep":"UNLINKED","origName":"message","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"REF","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", "childDTypep": [ {"type":"REFDTYPE","name":"T","addr":"(EU)","loc":"d,62:18,62:19","dtypep":"UNLINKED","generic":false,"typedefp":"UNLINKED","refDTypep":"UNLINKED","classOrPackagep":"UNLINKED","typeofp": [],"classOrPackageOpp": [],"paramsp": []} ],"delayp": [],"valuep": [],"attrsp": []} ],"scopeNamep": []}, {"type":"FUNC","name":"try_get","addr":"(FU)","loc":"d,71:18,71:25","dtypep":"UNLINKED","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"try_get", "fvarp": [ {"type":"BASICDTYPE","name":"int","addr":"(GU)","loc":"d,71:14,71:17","dtypep":"(GU)","keyword":"int","range":"31:0","generic":false,"rangep": []} ],"classOrPackagep": [], "stmtsp": [ {"type":"VAR","name":"message","addr":"(HU)","loc":"d,71:32,71:39","dtypep":"UNLINKED","origName":"message","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"REF","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", "childDTypep": [ {"type":"REFDTYPE","name":"T","addr":"(IU)","loc":"d,71:30,71:31","dtypep":"UNLINKED","generic":false,"typedefp":"UNLINKED","refDTypep":"UNLINKED","classOrPackagep":"UNLINKED","typeofp": [],"classOrPackageOpp": [],"paramsp": []} ],"delayp": [],"valuep": [],"attrsp": []}, {"type":"IF","name":"","addr":"(JU)","loc":"d,72:7,72:9", "condp": [ {"type":"GT","name":"","addr":"(KU)","loc":"d,72:17,72:18","dtypep":"(YE)", "lhsp": [ {"type":"FUNCREF","name":"num","addr":"(LU)","loc":"d,72:11,72:14","dtypep":"UNLINKED","dotted":"","taskp":"UNLINKED","classOrPackagep":"UNLINKED","namep": [],"pinsp": [],"scopeNamep": []} ], "rhsp": [ {"type":"CONST","name":"?32?sh0","addr":"(MU)","loc":"d,72:19,72:20","dtypep":"(N)"} ]} ], "thensp": [ {"type":"BEGIN","name":"","addr":"(NU)","loc":"d,72:22,72:27","implied":false,"needProcess":false,"unnamed":true,"declsp": [], "stmtsp": [ {"type":"ASSIGN","name":"","addr":"(OU)","loc":"d,73:17,73:18","dtypep":"UNLINKED", "rhsp": [ {"type":"DOT","name":"","addr":"(PU)","loc":"d,73:26,73:27","dtypep":"UNLINKED","colon":false, "lhsp": [ {"type":"PARSEREF","name":"m_queue","addr":"(QU)","loc":"d,73:19,73:26","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ], "rhsp": [ {"type":"FUNCREF","name":"pop_front","addr":"(RU)","loc":"d,73:27,73:36","dtypep":"UNLINKED","dotted":"","taskp":"UNLINKED","classOrPackagep":"UNLINKED","namep": [],"pinsp": [],"scopeNamep": []} ]} ], "lhsp": [ {"type":"PARSEREF","name":"message","addr":"(SU)","loc":"d,73:9,73:16","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ],"timingControlp": []}, {"type":"RETURN","name":"","addr":"(TU)","loc":"d,74:9,74:15", "lhsp": [ {"type":"CONST","name":"?32?sh1","addr":"(UU)","loc":"d,74:16,74:17","dtypep":"(N)"} ]} ]} ],"elsesp": []}, {"type":"RETURN","name":"","addr":"(VU)","loc":"d,76:7,76:13", "lhsp": [ {"type":"CONST","name":"?32?sh0","addr":"(WU)","loc":"d,76:14,76:15","dtypep":"(N)"} ]} ],"scopeNamep": []}, {"type":"TASK","name":"peek","addr":"(XU)","loc":"d,79:10,79:14","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"peek","fvarp": [],"classOrPackagep": [], "stmtsp": [ {"type":"VAR","name":"message","addr":"(YU)","loc":"d,79:21,79:28","dtypep":"UNLINKED","origName":"message","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"REF","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", "childDTypep": [ {"type":"REFDTYPE","name":"T","addr":"(ZU)","loc":"d,79:19,79:20","dtypep":"UNLINKED","generic":false,"typedefp":"UNLINKED","refDTypep":"UNLINKED","classOrPackagep":"UNLINKED","typeofp": [],"classOrPackageOpp": [],"paramsp": []} ],"delayp": [],"valuep": [],"attrsp": []} ],"scopeNamep": []}, {"type":"FUNC","name":"try_peek","addr":"(AV)","loc":"d,88:18,88:26","dtypep":"UNLINKED","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"try_peek", "fvarp": [ {"type":"BASICDTYPE","name":"int","addr":"(BV)","loc":"d,88:14,88:17","dtypep":"(BV)","keyword":"int","range":"31:0","generic":false,"rangep": []} ],"classOrPackagep": [], "stmtsp": [ {"type":"VAR","name":"message","addr":"(CV)","loc":"d,88:33,88:40","dtypep":"UNLINKED","origName":"message","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"REF","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", "childDTypep": [ {"type":"REFDTYPE","name":"T","addr":"(DV)","loc":"d,88:31,88:32","dtypep":"UNLINKED","generic":false,"typedefp":"UNLINKED","refDTypep":"UNLINKED","classOrPackagep":"UNLINKED","typeofp": [],"classOrPackageOpp": [],"paramsp": []} ],"delayp": [],"valuep": [],"attrsp": []}, {"type":"IF","name":"","addr":"(EV)","loc":"d,89:7,89:9", "condp": [ {"type":"GT","name":"","addr":"(FV)","loc":"d,89:17,89:18","dtypep":"(YE)", "lhsp": [ {"type":"FUNCREF","name":"num","addr":"(GV)","loc":"d,89:11,89:14","dtypep":"UNLINKED","dotted":"","taskp":"UNLINKED","classOrPackagep":"UNLINKED","namep": [],"pinsp": [],"scopeNamep": []} ], "rhsp": [ {"type":"CONST","name":"?32?sh0","addr":"(HV)","loc":"d,89:19,89:20","dtypep":"(N)"} ]} ], "thensp": [ {"type":"BEGIN","name":"","addr":"(IV)","loc":"d,89:22,89:27","implied":false,"needProcess":false,"unnamed":true,"declsp": [], "stmtsp": [ {"type":"ASSIGN","name":"","addr":"(JV)","loc":"d,90:17,90:18","dtypep":"UNLINKED", "rhsp": [ {"type":"SELBIT","name":"","addr":"(KV)","loc":"d,90:26,90:27","dtypep":"UNLINKED", "fromp": [ {"type":"PARSEREF","name":"m_queue","addr":"(LV)","loc":"d,90:19,90:26","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ], "bitp": [ {"type":"CONST","name":"?32?sh0","addr":"(MV)","loc":"d,90:27,90:28","dtypep":"(N)"} ],"thsp": [],"attrp": []} ], "lhsp": [ {"type":"PARSEREF","name":"message","addr":"(NV)","loc":"d,90:9,90:16","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ],"timingControlp": []}, {"type":"RETURN","name":"","addr":"(OV)","loc":"d,91:9,91:15", "lhsp": [ {"type":"CONST","name":"?32?sh1","addr":"(PV)","loc":"d,91:16,91:17","dtypep":"(N)"} ]} ]} ],"elsesp": []}, {"type":"RETURN","name":"","addr":"(QV)","loc":"d,93:7,93:13", "lhsp": [ {"type":"CONST","name":"?32?sh0","addr":"(RV)","loc":"d,93:14,93:15","dtypep":"(N)"} ]} ],"scopeNamep": []} ],"extendsp": []}, {"type":"CLASS","name":"semaphore","addr":"(SV)","loc":"d,97:3,97:8","isExtended":false,"isInterfaceClass":false,"isVirtual":false,"origName":"semaphore","level":5,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","classOrPackagep":"UNLINKED","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"m_keyCount","addr":"(TV)","loc":"d,98:19,98:29","dtypep":"UNLINKED","origName":"m_keyCount","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"VAR","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", "childDTypep": [ {"type":"BASICDTYPE","name":"int","addr":"(UV)","loc":"d,98:15,98:18","dtypep":"(UV)","keyword":"int","range":"31:0","generic":false,"rangep": []} ],"delayp": [],"valuep": [],"attrsp": []}, {"type":"FUNC","name":"new","addr":"(VV)","loc":"d,100:14,100:17","dtypep":"UNLINKED","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"new","fvarp": [],"classOrPackagep": [], "stmtsp": [ {"type":"VAR","name":"keyCount","addr":"(WV)","loc":"d,100:22,100:30","dtypep":"UNLINKED","origName":"keyCount","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", "childDTypep": [ {"type":"BASICDTYPE","name":"int","addr":"(XV)","loc":"d,100:18,100:21","dtypep":"(XV)","keyword":"int","range":"31:0","generic":false,"rangep": []} ],"delayp": [], "valuep": [ {"type":"CONST","name":"?32?sh0","addr":"(YV)","loc":"d,100:33,100:34","dtypep":"(N)"} ],"attrsp": []}, {"type":"ASSIGN","name":"","addr":"(ZV)","loc":"d,101:18,101:19","dtypep":"UNLINKED", "rhsp": [ {"type":"PARSEREF","name":"keyCount","addr":"(AW)","loc":"d,101:20,101:28","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ], "lhsp": [ {"type":"PARSEREF","name":"m_keyCount","addr":"(BW)","loc":"d,101:7,101:17","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ],"timingControlp": []} ],"scopeNamep": []}, {"type":"TASK","name":"put","addr":"(CW)","loc":"d,104:19,104:22","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"put","fvarp": [],"classOrPackagep": [], "stmtsp": [ {"type":"VAR","name":"keyCount","addr":"(DW)","loc":"d,104:27,104:35","dtypep":"UNLINKED","origName":"keyCount","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", "childDTypep": [ {"type":"BASICDTYPE","name":"int","addr":"(EW)","loc":"d,104:23,104:26","dtypep":"(EW)","keyword":"int","range":"31:0","generic":false,"rangep": []} ],"delayp": [], "valuep": [ {"type":"CONST","name":"?32?sh1","addr":"(FW)","loc":"d,104:38,104:39","dtypep":"(N)"} ],"attrsp": []}, {"type":"ASSIGN","name":"","addr":"(GW)","loc":"d,105:18,105:20","dtypep":"UNLINKED", "rhsp": [ {"type":"ADD","name":"","addr":"(HW)","loc":"d,105:18,105:20","dtypep":"UNLINKED", "lhsp": [ {"type":"PARSEREF","name":"m_keyCount","addr":"(IW)","loc":"d,105:7,105:17","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ], "rhsp": [ {"type":"PARSEREF","name":"keyCount","addr":"(JW)","loc":"d,105:21,105:29","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ]} ], "lhsp": [ {"type":"PARSEREF","name":"m_keyCount","addr":"(KW)","loc":"d,105:7,105:17","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ],"timingControlp": []} ],"scopeNamep": []}, {"type":"TASK","name":"get","addr":"(LW)","loc":"d,108:10,108:13","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"get","fvarp": [],"classOrPackagep": [], "stmtsp": [ {"type":"VAR","name":"keyCount","addr":"(MW)","loc":"d,108:18,108:26","dtypep":"UNLINKED","origName":"keyCount","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", "childDTypep": [ {"type":"BASICDTYPE","name":"int","addr":"(NW)","loc":"d,108:14,108:17","dtypep":"(NW)","keyword":"int","range":"31:0","generic":false,"rangep": []} ],"delayp": [], "valuep": [ {"type":"CONST","name":"?32?sh1","addr":"(OW)","loc":"d,108:29,108:30","dtypep":"(N)"} ],"attrsp": []} ],"scopeNamep": []}, {"type":"FUNC","name":"try_get","addr":"(PW)","loc":"d,117:18,117:25","dtypep":"UNLINKED","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"try_get", "fvarp": [ {"type":"BASICDTYPE","name":"int","addr":"(QW)","loc":"d,117:14,117:17","dtypep":"(QW)","keyword":"int","range":"31:0","generic":false,"rangep": []} ],"classOrPackagep": [], "stmtsp": [ {"type":"VAR","name":"keyCount","addr":"(RW)","loc":"d,117:30,117:38","dtypep":"UNLINKED","origName":"keyCount","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", "childDTypep": [ {"type":"BASICDTYPE","name":"int","addr":"(SW)","loc":"d,117:26,117:29","dtypep":"(SW)","keyword":"int","range":"31:0","generic":false,"rangep": []} ],"delayp": [], "valuep": [ {"type":"CONST","name":"?32?sh1","addr":"(TW)","loc":"d,117:41,117:42","dtypep":"(N)"} ],"attrsp": []}, {"type":"IF","name":"","addr":"(UW)","loc":"d,118:7,118:9", "condp": [ {"type":"GTE","name":"","addr":"(VW)","loc":"d,118:22,118:24","dtypep":"(YE)", "lhsp": [ {"type":"PARSEREF","name":"m_keyCount","addr":"(WW)","loc":"d,118:11,118:21","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ], "rhsp": [ {"type":"PARSEREF","name":"keyCount","addr":"(XW)","loc":"d,118:25,118:33","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ]} ], "thensp": [ {"type":"BEGIN","name":"","addr":"(YW)","loc":"d,118:35,118:40","implied":false,"needProcess":false,"unnamed":true,"declsp": [], "stmtsp": [ {"type":"ASSIGN","name":"","addr":"(ZW)","loc":"d,119:20,119:22","dtypep":"UNLINKED", "rhsp": [ {"type":"SUB","name":"","addr":"(AX)","loc":"d,119:20,119:22","dtypep":"UNLINKED", "lhsp": [ {"type":"PARSEREF","name":"m_keyCount","addr":"(BX)","loc":"d,119:9,119:19","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ], "rhsp": [ {"type":"PARSEREF","name":"keyCount","addr":"(CX)","loc":"d,119:23,119:31","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ]} ], "lhsp": [ {"type":"PARSEREF","name":"m_keyCount","addr":"(DX)","loc":"d,119:9,119:19","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ],"timingControlp": []}, {"type":"RETURN","name":"","addr":"(EX)","loc":"d,120:9,120:15", "lhsp": [ {"type":"CONST","name":"?32?sh1","addr":"(FX)","loc":"d,120:16,120:17","dtypep":"(N)"} ]} ]} ],"elsesp": []}, {"type":"RETURN","name":"","addr":"(GX)","loc":"d,122:7,122:13", "lhsp": [ {"type":"CONST","name":"?32?sh0","addr":"(HX)","loc":"d,122:14,122:15","dtypep":"(N)"} ]} ],"scopeNamep": []} ],"extendsp": []}, {"type":"CLASS","name":"process","addr":"(IX)","loc":"d,126:3,126:8","isExtended":false,"isInterfaceClass":false,"isVirtual":false,"origName":"process","level":5,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","classOrPackagep":"UNLINKED","inlinesp": [], "stmtsp": [ {"type":"TYPEDEF","name":"state","addr":"(JX)","loc":"d,133:7,133:12","dtypep":"UNLINKED","attrPublic":false,"isUnderClass":false, "childDTypep": [ {"type":"DEFIMPLICITDTYPE","name":"__typeimpenum0","addr":"(KX)","loc":"d,127:13,127:17","dtypep":"UNLINKED","generic":false, "childDTypep": [ {"type":"ENUMDTYPE","name":"","addr":"(LX)","loc":"d,127:13,127:17","dtypep":"UNLINKED","enum":true,"generic":false,"refDTypep":"UNLINKED", "childDTypep": [ {"type":"BASICDTYPE","name":"int","addr":"(MX)","loc":"d,127:18,127:19","dtypep":"(MX)","keyword":"int","range":"31:0","generic":false,"rangep": []} ], "itemsp": [ {"type":"ENUMITEM","name":"FINISHED","addr":"(NX)","loc":"d,128:7,128:15","dtypep":"UNLINKED","rangep": [], "valuep": [ {"type":"CONST","name":"?32?sh0","addr":"(OX)","loc":"d,128:18,128:19","dtypep":"(N)"} ]}, {"type":"ENUMITEM","name":"RUNNING","addr":"(PX)","loc":"d,129:7,129:14","dtypep":"UNLINKED","rangep": [], "valuep": [ {"type":"CONST","name":"?32?sh1","addr":"(QX)","loc":"d,129:17,129:18","dtypep":"(N)"} ]}, {"type":"ENUMITEM","name":"WAITING","addr":"(RX)","loc":"d,130:7,130:14","dtypep":"UNLINKED","rangep": [], "valuep": [ {"type":"CONST","name":"?32?sh2","addr":"(SX)","loc":"d,130:17,130:18","dtypep":"(UD)"} ]}, {"type":"ENUMITEM","name":"SUSPENDED","addr":"(TX)","loc":"d,131:7,131:16","dtypep":"UNLINKED","rangep": [], "valuep": [ {"type":"CONST","name":"?32?sh3","addr":"(UX)","loc":"d,131:19,131:20","dtypep":"(UD)"} ]}, {"type":"ENUMITEM","name":"KILLED","addr":"(VX)","loc":"d,132:7,132:13","dtypep":"UNLINKED","rangep": [], "valuep": [ {"type":"CONST","name":"?32?sh4","addr":"(WX)","loc":"d,132:16,132:17","dtypep":"(XX)"} ]} ]} ]} ],"attrsp": []}, {"type":"VAR","name":"m_process","addr":"(YX)","loc":"d,136:23,136:32","dtypep":"UNLINKED","origName":"m_process","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"VAR","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", "childDTypep": [ {"type":"BASICDTYPE","name":"chandle","addr":"(ZX)","loc":"d,136:15,136:22","dtypep":"(ZX)","keyword":"chandle","range":"63:0","generic":false,"rangep": []} ],"delayp": [],"valuep": [],"attrsp": []}, {"type":"FUNC","name":"self","addr":"(AY)","loc":"d,138:29,138:33","dtypep":"UNLINKED","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"self", "fvarp": [ {"type":"REFDTYPE","name":"process","addr":"(BY)","loc":"d,138:21,138:28","dtypep":"UNLINKED","generic":false,"typedefp":"UNLINKED","refDTypep":"UNLINKED","classOrPackagep":"UNLINKED","typeofp": [],"classOrPackageOpp": [],"paramsp": []} ],"classOrPackagep": [], "stmtsp": [ {"type":"VAR","name":"p","addr":"(CY)","loc":"d,139:15,139:16","dtypep":"UNLINKED","origName":"p","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"VAR","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", "childDTypep": [ {"type":"REFDTYPE","name":"process","addr":"(DY)","loc":"d,139:7,139:14","dtypep":"UNLINKED","generic":false,"typedefp":"UNLINKED","refDTypep":"UNLINKED","classOrPackagep":"UNLINKED","typeofp": [],"classOrPackageOpp": [],"paramsp": []} ],"delayp": [], "valuep": [ {"type":"NEW","name":"new","addr":"(EY)","loc":"d,139:19,139:22","dtypep":"UNLINKED","isImplicit":false,"isScoped":false,"dotted":"","taskp":"UNLINKED","classOrPackagep":"UNLINKED","namep": [],"pinsp": [],"scopeNamep": []} ],"attrsp": []}, {"type":"RETURN","name":"","addr":"(FY)","loc":"d,143:7,143:13", "lhsp": [ {"type":"PARSEREF","name":"p","addr":"(GY)","loc":"d,143:14,143:15","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ]} ],"scopeNamep": []}, {"type":"TASK","name":"set_status","addr":"(HY)","loc":"d,146:29,146:39","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"set_status","fvarp": [],"classOrPackagep": [], "stmtsp": [ {"type":"VAR","name":"s","addr":"(IY)","loc":"d,146:46,146:47","dtypep":"UNLINKED","origName":"s","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", "childDTypep": [ {"type":"REFDTYPE","name":"state","addr":"(JY)","loc":"d,146:40,146:45","dtypep":"UNLINKED","generic":false,"typedefp":"UNLINKED","refDTypep":"UNLINKED","classOrPackagep":"UNLINKED","typeofp": [],"classOrPackageOpp": [],"paramsp": []} ],"delayp": [],"valuep": [],"attrsp": []} ],"scopeNamep": []}, {"type":"FUNC","name":"status","addr":"(KY)","loc":"d,152:20,152:26","dtypep":"UNLINKED","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"status", "fvarp": [ {"type":"REFDTYPE","name":"state","addr":"(LY)","loc":"d,152:14,152:19","dtypep":"UNLINKED","generic":false,"typedefp":"UNLINKED","refDTypep":"UNLINKED","classOrPackagep":"UNLINKED","typeofp": [],"classOrPackageOpp": [],"paramsp": []} ],"classOrPackagep": [], "stmtsp": [ {"type":"RETURN","name":"","addr":"(MY)","loc":"d,156:7,156:13", "lhsp": [ {"type":"PARSEREF","name":"RUNNING","addr":"(NY)","loc":"d,156:14,156:21","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ]} ],"scopeNamep": []}, {"type":"TASK","name":"kill","addr":"(OY)","loc":"d,160:19,160:23","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"kill","fvarp": [],"classOrPackagep": [], "stmtsp": [ {"type":"STMTEXPR","name":"","addr":"(PY)","loc":"d,161:7,161:17", "exprp": [ {"type":"TASKREF","name":"set_status","addr":"(QY)","loc":"d,161:7,161:17","dtypep":"(VT)","dotted":"","taskp":"UNLINKED","classOrPackagep":"UNLINKED","namep": [], "pinsp": [ {"type":"ARG","name":"","addr":"(RY)","loc":"d,161:18,161:24", "exprp": [ {"type":"PARSEREF","name":"KILLED","addr":"(SY)","loc":"d,161:18,161:24","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ]} ],"scopeNamep": []} ]} ],"scopeNamep": []}, {"type":"TASK","name":"suspend","addr":"(TY)","loc":"d,164:19,164:26","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"suspend","fvarp": [],"classOrPackagep": [], "stmtsp": [ {"type":"DISPLAY","name":"","addr":"(UY)","loc":"d,165:7,165:13", "fmtp": [ {"type":"SFORMATF","name":"","addr":"(VY)","loc":"d,165:7,165:13","dtypep":"(FG)", "exprsp": [ {"type":"CONST","name":"296'h7374643a3a70726f636573733a3a73757370656e642829206e6f7420737570706f72746564","addr":"(WY)","loc":"d,165:14,165:53","dtypep":"(XY)"} ],"scopeNamep": []} ],"filep": []}, {"type":"STOP","name":"","addr":"(YY)","loc":"d,165:7,165:13","isFatal":false} ],"scopeNamep": []}, {"type":"TASK","name":"resume","addr":"(ZY)","loc":"d,168:19,168:25","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"resume","fvarp": [],"classOrPackagep": [], "stmtsp": [ {"type":"STMTEXPR","name":"","addr":"(AZ)","loc":"d,169:7,169:17", "exprp": [ {"type":"TASKREF","name":"set_status","addr":"(BZ)","loc":"d,169:7,169:17","dtypep":"(VT)","dotted":"","taskp":"UNLINKED","classOrPackagep":"UNLINKED","namep": [], "pinsp": [ {"type":"ARG","name":"","addr":"(CZ)","loc":"d,169:18,169:25", "exprp": [ {"type":"PARSEREF","name":"RUNNING","addr":"(DZ)","loc":"d,169:18,169:25","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ]} ],"scopeNamep": []} ]} ],"scopeNamep": []}, {"type":"TASK","name":"await","addr":"(EZ)","loc":"d,172:10,172:15","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"await","fvarp": [],"classOrPackagep": [],"stmtsp": [],"scopeNamep": []}, {"type":"TASK","name":"killQueue","addr":"(FZ)","loc":"d,178:17,178:26","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"killQueue","fvarp": [],"classOrPackagep": [], "stmtsp": [ {"type":"VAR","name":"processQueue","addr":"(GZ)","loc":"d,178:39,178:51","dtypep":"UNLINKED","origName":"processQueue","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"REF","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", "childDTypep": [ {"type":"BRACKETARRAYDTYPE","name":"","addr":"(HZ)","loc":"d,178:51,178:52","dtypep":"UNLINKED","generic":false, "childDTypep": [ {"type":"REFDTYPE","name":"process","addr":"(IZ)","loc":"d,178:31,178:38","dtypep":"UNLINKED","generic":false,"typedefp":"UNLINKED","refDTypep":"UNLINKED","classOrPackagep":"UNLINKED","typeofp": [],"classOrPackageOpp": [],"paramsp": []} ], "elementsp": [ {"type":"UNBOUNDED","name":"","addr":"(JZ)","loc":"d,178:52,178:53","dtypep":"(NS)"} ]} ],"delayp": [],"valuep": [],"attrsp": []} ],"scopeNamep": []}, {"type":"FUNC","name":"get_randstate","addr":"(KZ)","loc":"d,225:21,225:34","dtypep":"UNLINKED","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"get_randstate", "fvarp": [ {"type":"BASICDTYPE","name":"string","addr":"(LZ)","loc":"d,225:14,225:20","dtypep":"(LZ)","keyword":"string","generic":false,"rangep": []} ],"classOrPackagep": [], "stmtsp": [ {"type":"VAR","name":"s","addr":"(MZ)","loc":"d,227:14,227:15","dtypep":"UNLINKED","origName":"s","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"VAR","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", "childDTypep": [ {"type":"BASICDTYPE","name":"string","addr":"(NZ)","loc":"d,227:7,227:13","dtypep":"(NZ)","keyword":"string","generic":false,"rangep": []} ],"delayp": [], "valuep": [ {"type":"CVTPACKSTRING","name":"","addr":"(OZ)","loc":"d,227:18,227:24","dtypep":"(FG)", "lhsp": [ {"type":"CEXPRUSER","name":"","addr":"(PZ)","loc":"d,227:26,227:28","dtypep":"UNLINKED", "nodesp": [ {"type":"TEXT","name":"","addr":"(QZ)","loc":"d,227:29,227:32","text":"0"} ]} ]} ],"attrsp": []}, {"type":"CSTMTUSER","name":"","addr":"(RZ)","loc":"d,229:7,229:9", "nodesp": [ {"type":"PARSEREF","name":"s","addr":"(SZ)","loc":"d,229:10,229:11","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []}, {"type":"TEXT","name":"","addr":"(TZ)","loc":"d,229:13,229:18","text":" = "}, {"type":"PARSEREF","name":"m_process","addr":"(UZ)","loc":"d,229:20,229:29","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []}, {"type":"TEXT","name":"","addr":"(VZ)","loc":"d,229:31,229:47","text":"->randstate();"} ]}, {"type":"RETURN","name":"","addr":"(WZ)","loc":"d,230:7,230:13", "lhsp": [ {"type":"PARSEREF","name":"s","addr":"(XZ)","loc":"d,230:14,230:15","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ]} ],"scopeNamep": []}, {"type":"TASK","name":"set_randstate","addr":"(YZ)","loc":"d,233:19,233:32","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"set_randstate","fvarp": [],"classOrPackagep": [], "stmtsp": [ {"type":"VAR","name":"s","addr":"(ZZ)","loc":"d,233:40,233:41","dtypep":"UNLINKED","origName":"s","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", "childDTypep": [ {"type":"BASICDTYPE","name":"string","addr":"(AAB)","loc":"d,233:33,233:39","dtypep":"(AAB)","keyword":"string","generic":false,"rangep": []} ],"delayp": [],"valuep": [],"attrsp": []}, {"type":"CSTMTUSER","name":"","addr":"(BAB)","loc":"d,234:7,234:9", "nodesp": [ {"type":"PARSEREF","name":"m_process","addr":"(CAB)","loc":"d,234:10,234:19","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []}, {"type":"TEXT","name":"","addr":"(DAB)","loc":"d,234:21,234:35","text":"->randstate("}, {"type":"PARSEREF","name":"s","addr":"(EAB)","loc":"d,234:37,234:38","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []}, {"type":"TEXT","name":"","addr":"(FAB)","loc":"d,234:40,234:44","text":");"} ]} ],"scopeNamep": []} ],"extendsp": []}, {"type":"FUNC","name":"randomize","addr":"(GAB)","loc":"d,238:16,238:25","dtypep":"UNLINKED","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"randomize", "fvarp": [ {"type":"BASICDTYPE","name":"int","addr":"(HAB)","loc":"d,238:12,238:15","dtypep":"(HAB)","keyword":"int","range":"31:0","generic":false,"rangep": []} ],"classOrPackagep": [], "stmtsp": [ {"type":"ASSIGN","name":"","addr":"(IAB)","loc":"d,239:15,239:16","dtypep":"UNLINKED", "rhsp": [ {"type":"CONST","name":"?32?sh0","addr":"(JAB)","loc":"d,239:17,239:18","dtypep":"(N)"} ], "lhsp": [ {"type":"PARSEREF","name":"randomize","addr":"(KAB)","loc":"d,239:5,239:14","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ],"timingControlp": []} ],"scopeNamep": []} ]} ],"filesp": [], "miscsp": [ {"type":"TYPETABLE","name":"","addr":"(C)","loc":"a,0:0,0:0","constraintRefp":"UNLINKED","emptyQueuep":"UNLINKED","queueIndexp":"UNLINKED","streamp":"UNLINKED","voidp":"(VT)", "typesp": [ {"type":"BASICDTYPE","name":"integer","addr":"(NS)","loc":"d,36:25,36:26","dtypep":"(NS)","keyword":"integer","range":"31:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(N)","loc":"d,38:30,38:31","dtypep":"(N)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(YE)","loc":"d,55:19,55:21","dtypep":"(YE)","keyword":"logic","generic":true,"rangep": []}, {"type":"VOIDDTYPE","name":"","addr":"(VT)","loc":"d,56:17,56:26","dtypep":"(VT)","generic":false}, {"type":"BASICDTYPE","name":"logic","addr":"(UD)","loc":"d,130:17,130:18","dtypep":"(UD)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(XX)","loc":"d,132:16,132:17","dtypep":"(XX)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(XY)","loc":"d,165:14,165:53","dtypep":"(XY)","keyword":"logic","range":"295:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"string","addr":"(FG)","loc":"d,165:7,165:13","dtypep":"(FG)","keyword":"string","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(S)","loc":"e,14:9,14:11","dtypep":"(S)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(DB)","loc":"e,18:10,18:12","dtypep":"(DB)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(QC)","loc":"e,33:26,33:31","dtypep":"(QC)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(NC)","loc":"e,33:25,33:26","dtypep":"(NC)","keyword":"logic","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(EF)","loc":"e,45:17,45:38","dtypep":"(EF)","keyword":"logic","range":"63:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(NF)","loc":"e,48:22,48:24","dtypep":"(NF)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(WF)","loc":"e,51:22,51:24","dtypep":"(WF)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(HG)","loc":"e,54:17,54:49","dtypep":"(HG)","keyword":"logic","range":"231:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"QData","addr":"(JG)","loc":"e,54:51,54:56","dtypep":"(JG)","keyword":"QData","range":"63:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(AH)","loc":"e,59:17,59:41","dtypep":"(AH)","keyword":"logic","range":"167:0","generic":true,"rangep": []} ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ {"type":"MODULE","name":"@CONST-POOL@","addr":"(LAB)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], "stmtsp": [ {"type":"SCOPE","name":"@CONST-POOL@","addr":"(MAB)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(LAB)","varsp": [],"blocksp": [],"inlinesp": []} ]} ]} ]} verilator-5.042/test_regress/t/t_assert_ctl_immediate.py0000755000542200017500000000112115101701376024142 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=['--assert', '--timing']) test.execute(all_run_flags=["+verilator+error+limit+100"], expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_opt_table_display.out0000644000542200017500000000015515101701376023641 0ustar mahmoudyfreeshellClocked Clocked Clocked Clocked Clocked Clocked Clocked Clocked Clocked Clocked Clocked *-* All Finished *-* verilator-5.042/test_regress/t/t_math_shortreal_unsup_bad.py0000755000542200017500000000076615101701376025053 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_std_pkg_bad.py0000755000542200017500000000076615101701376022240 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_clocking_bad3.out0000644000542200017500000000122315101701376022622 0ustar mahmoudyfreeshell%Error: t/t_clocking_bad3.v:14:14: Corresponding variable 'in' does not exist 14 | input in; | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_clocking_bad3.v:15:15: Corresponding variable 'out' does not exist 15 | output out; | ^~~ %Error: t/t_clocking_bad3.v:18:13: Duplicate declaration of CLOCKING 'cb': 'cb' 18 | clocking cb @(posedge clk); | ^~ t/t_clocking_bad3.v:13:13: ... Location of original declaration 13 | clocking cb @(posedge clk); | ^~ %Error: Exiting due to verilator-5.042/test_regress/t/t_lib_prot_inout_bad.out0000644000542200017500000000044715101701376024005 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_lib_prot_inout_bad.v:9:28: Unsupported: --lib-create port direction: INOUT 9 | inout z, | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_select_index.py0000755000542200017500000000073415101701376022440 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_flag_build.py0000755000542200017500000000125515101701376022061 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_flag_make_cmake.v" test.compile( # Don't call cmake nor gmake from driver.py verilator_flags2=[ '--exe --cc --build -j 2', '../' + test.main_filename, '-MAKEFLAGS -p --trace-vcd' ]) test.execute() test.passes() verilator-5.042/test_regress/t/t_clk_latchgate.py0000755000542200017500000000073415101701376022557 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_for_funcbound.py0000755000542200017500000000111315101701376022613 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.file_grep(test.run_log_filename, r"\[10\] hello") test.file_grep(test.run_log_filename, r"\[20\] world") test.passes() verilator-5.042/test_regress/t/t_trace_two_portfst_cc.py0000755000542200017500000000243015101701376024202 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Test tracing with two models instanced import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t_trace_two_a.v" test.pli_filename = "t/t_trace_two_cc.cpp" test.compile(make_main=False, verilator_make_gmake=False, top_filename='t_trace_two_b.v', vm_prefix='Vt_trace_two_b', verilator_flags2=['--trace-fst --trace-threads 1']) test.run(logfile=test.obj_dir + "/make_first_ALL.log", cmd=[ os.environ["MAKE"], "-C", "" + test.obj_dir, "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp" ]) test.compile( make_main=False, top_filename='t_trace_two_a.v', verilator_flags2=['-exe', '--trace-fst --trace-threads 1', '-DTEST_FST', test.pli_filename], v_flags2=['+define+TEST_DUMPPORTS']) test.execute() if test.vlt_all: test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_hier_block_trace_fst.py0000755000542200017500000000211015101701376024113 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_hier_block.v" # CI environment offers 2 VCPUs, 2 thread setting causes the following warning. # %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. # So use 6 threads here though it's not optimal in performance, but ok. test.compile( v_flags2=['t/t_hier_block.cpp'], verilator_flags2=[ '--hierarchical', '--Wno-TIMESCALEMOD', '--trace-fst', '--no-trace-underscore', # To avoid handle mismatches ], threads=(6 if test.vltmt else 1)) test.execute() test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_func_noinl.py0000755000542200017500000000073415101701376022124 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_fork_dynscope_unsup.py0000755000542200017500000000103015101701376024057 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.lint(verilator_flags2=["--timing"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_cover_line_wide_ternary.v0000644000542200017500000000313415101701376024502 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface intf(); logic foo; logic [31:0] bar; logic [127:0] baz; endinterface module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; intf intfs [2] (); intf intf_sel_ff(); intf intf_sel_comb(); intf intf_sel_assign(); always_comb begin intfs[0].bar = 123; intfs[1].bar = 456; end always_ff @ (posedge clk) begin {intf_sel_ff.foo, intf_sel_ff.bar, intf_sel_ff.baz} <= cyc[0] ? {intfs[1].foo, intfs[1].bar, intfs[1].baz} : {intfs[0].foo, intfs[0].bar, intfs[0].baz}; end always_comb begin {intf_sel_comb.foo, intf_sel_comb.bar, intf_sel_comb.baz} = cyc[0] ? {intfs[1].foo, intfs[1].bar, intfs[1].baz} : {intfs[0].foo, intfs[0].bar, intfs[0].baz}; end assign {intf_sel_assign.foo, intf_sel_assign.bar, intf_sel_assign.baz} = cyc[0] ? {intfs[1].foo, intfs[1].bar, intfs[1].baz} : {intfs[0].foo, intfs[0].bar, intfs[0].baz}; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==9) begin if (intf_sel_ff.bar != 123) $stop(); if (intf_sel_comb.bar != 456) $stop(); if (intf_sel_assign.bar != 456) $stop(); $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_time_sc.v0000644000542200017500000000134015101701376021221 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under The Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; time texpect = `TEST_EXPECT; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 1) begin $printtimescale; $write("[%0t] In %m: Hi - expect this is %0t\n", $time, texpect); if ($time != texpect) begin $write("[%0t] delta = %d\n", $time, $time - texpect); $stop; end $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_cast_stream.v0000644000542200017500000000161115101701376022104 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); typedef enum { UVM_TLM_READ_COMMAND, UVM_TLM_WRITE_COMMAND, UVM_TLM_IGNORE_COMMAND } uvm_tlm_command_e; module t; initial begin bit array[] = new [8]; int unsigned m_length; uvm_tlm_command_e m_command; m_length = 2; array = '{0, 0, 0, 0, 0, 0, 1, 0}; array = new [$bits(m_length)] (array); m_command = uvm_tlm_command_e'({ << bit { array }}); `checkh(m_command, 'h40) $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_trace_multi_bad.py0000755000542200017500000000106415101701376023105 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags=['--trace-fst --trace-vcd'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_case_deep.py0000755000542200017500000000106415101701376021677 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile( # We have deep expressions we want to test verilator_flags2=["--compiler msvc"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_struct_param.py0000755000542200017500000000073415101701376022476 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_case_default_bad.py0000755000542200017500000000076615101701376023224 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_randomize_method_bad.py0000755000542200017500000000077615101701376024136 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_clk_first_bad.py0000755000542200017500000000110615101701376022552 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_clk_first_deprecated.v" test.lint(verilator_flags2=["--lint-only"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_initial_dlyass.py0000755000542200017500000000100015101701376022765 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['-Wno-INITIALDLY']) test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_declfilename_bad.out0000644000542200017500000000061715101701376024412 0ustar mahmoudyfreeshell%Warning-DECLFILENAME: t/t_lint_declfilename.v:7:8: Filename 't_lint_declfilename' does not match MODULE name: 't' 7 | module t; | ^ ... For warning description see https://verilator.org/warn/DECLFILENAME?v=latest ... Use "/* verilator lint_off DECLFILENAME */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_case_write2.py0000755000542200017500000000114715101701376022200 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--stats -O3 -x-assign fast"]) test.execute() test.files_identical(test.obj_dir + "/" + test.name + "_logger.log", test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_case_enum_complete.py0000755000542200017500000000077415101701376023625 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["--lint-only -Wwarn-CASEINCOMPLETE"]) test.passes() verilator-5.042/test_regress/t/t_func_dotted_inl0.vlt0000644000542200017500000000041515101701376023360 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. // SPDX-License-Identifier: CC0-1.0 `verilator_config public -module "global_mod" public -module "m*" verilator-5.042/test_regress/t/t_concat_large_bad.py0000755000542200017500000000076615101701376023226 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_scheduling_many_clocks.v0000644000542200017500000000271515101701376024314 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); module t(/*AUTOARG*/ // Inputs clk ); input clk; localparam int ITERATIONS = 5; localparam int N = 227; logic [N-1:0] gclk = {N{1'b0}}; // Not actually used, but creates an extra internal trigger export "DPI-C" function toggle; function void toggle(); gclk = ~gclk; endfunction int cyc = 0; bit par = 0; always @(posedge clk) begin if (~|gclk) begin gclk[0] = 1'b1; end else begin gclk = {gclk[N-2:0], gclk[N-1]}; end // This make the always block requires a 'pre' trigger (and makes it non splitable) par <= ^gclk; cyc <= cyc + 32'd1; if (cyc == ITERATIONS*N - 1) begin $display("final cycle: %0d, par: %0d", cyc, par); $write("*-* All Finished *-*\n"); $finish; end end for (genvar n = 0; n < N; n++) begin : gen int cnt = 0; always @(posedge gclk[n]) cnt <= cnt + 1; int cnt_plus_one; always_comb cnt_plus_one = cnt + 1; final begin `checkh(cnt_plus_one, ITERATIONS + 1); end end endmodule verilator-5.042/test_regress/t/t_always_ff_never.py0000755000542200017500000000073715101701376023147 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_flag_x_assign_bad.py0000755000542200017500000000106015101701376023375 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--x-assign bad_one"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_colonplus_bad.out0000644000542200017500000000063015101701376024013 0ustar mahmoudyfreeshell%Warning-COLONPLUS: t/t_lint_colonplus_bad.v:13:25: Perhaps instead of ':+' the intent was '+:'? 13 | output [2:1] z = r[2 :+ 1]; | ^~ ... For warning description see https://verilator.org/warn/COLONPLUS?v=latest ... Use "/* verilator lint_off COLONPLUS */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_stream5.v0000644000542200017500000000226615101701376021166 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; logic [15:0] i16; logic [15:0] o16; logic [3:0][3:0] p16; logic [31:0] i32; logic [31:0] o32; logic [7:0][3:0] p32; logic [63:0] i64; logic [63:0] o64; logic [15:0][3:0] p64; always_comb begin o16 = {<<4{i16}}; p16 = {<<4{i16}}; o32 = {<<4{i32}}; p32 = {<<4{i32}}; o64 = {<<4{i64}}; p64 = {<<4{i64}}; end initial begin i16 = 16'hfade; i32 = 32'hcafefade; i64 = 64'hdeaddeedcafefade; #100ns; $display("o16=0x%h p16=0x%h i16=0x%h", o16, p16, i16); if (o16 != 16'hEDAF) $stop; if (p16 != 16'hEDAF) $stop; $display("o32=0x%h p32=0x%h i32=0x%h", o32, p32, i32); if (o32 != 32'hEDAFEFAC) $stop; if (p32 != 32'hEDAFEFAC) $stop; $display("o64=0x%h p64=0x%h i64=0x%h", o64, p64, i64); if (o64 != 64'hEDAFEFACDEEDDAED) $stop; if (p64 != 64'hEDAFEFACDEEDDAED) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_var_sc_bv.cpp0000644000542200017500000002347615101701376022075 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include VM_PREFIX_INCLUDE using namespace sc_core; using namespace sc_dt; VM_PREFIX* tb = nullptr; bool pass = true; double sc_time_stamp() { return 0; } void compare_signals(const sc_signal>& ls, const sc_signal>& rs) { if (ls.read() != rs.read()) { pass &= false; VL_PRINTF("%%Error: Data mismatch in signals %s and %s\n", ls.name(), rs.name()); } } void compareWls(int obits, WDataInP const lwp, WDataInP const rwp) { const int words = VL_WORDS_I(obits); bool same = true; for (int i = 0; (i < (words - 1)); ++i) { if (lwp[i] != rwp[i]) same = false; } if ((lwp[words - 1] & VL_MASK_E(obits)) != (rwp[words - 1] & VL_MASK_E(obits))) { same = false; } if (!same) { pass &= false; VL_PRINTF("%%Error: There is a difference in VlWide variable %d bits wide\n", obits); } } // old macro which is correct but has MT issue with range #define VL_ASSIGN_SBW_MT_ISSUE(obits, svar, rwp) \ { \ sc_biguint<(obits)> _butemp; \ for (int i = 0; i < VL_WORDS_I(obits); ++i) { \ int msb = ((i + 1) * VL_IDATASIZE) - 1; \ msb = (msb >= (obits)) ? ((obits) - 1) : msb; \ _butemp.range(msb, i* VL_IDATASIZE) = (rwp)[i]; \ } \ (svar).write(_butemp); \ } #ifdef SYSTEMC_VERSION int sc_main(int, char**) #else int main() #endif { Verilated::debug(0); tb = new VM_PREFIX{"tb"}; VlWide<8> /*255:0*/ input_var; VlWide<8> /*255:0*/ out_var; // msb is always set to F not to be false positive on checking equality input_var.m_storage[0] = 0xF2341234; input_var.m_storage[1] = 0xFEADBEEF; input_var.m_storage[2] = 0xF5A5A5A5; input_var.m_storage[3] = 0xF1B2C3D4; input_var.m_storage[4] = 0xFFFFFFFF; input_var.m_storage[5] = 0xFAAABBBB; input_var.m_storage[6] = 0xF000AAAA; input_var.m_storage[7] = 0xF0101010; #ifdef SYSTEMC_VERSION // clang-format off sc_signal> SC_NAMED(i_29_s), SC_NAMED(i_29_old_s), SC_NAMED(o_29_s), SC_NAMED(o_29_old_s), SC_NAMED(i_30_s), SC_NAMED(i_30_old_s), SC_NAMED(o_30_s), SC_NAMED(o_30_old_s), SC_NAMED(i_31_s), SC_NAMED(i_31_old_s), SC_NAMED(o_31_s), SC_NAMED(o_31_old_s), SC_NAMED(i_32_s), SC_NAMED(i_32_old_s), SC_NAMED(o_32_s), SC_NAMED(o_32_old_s), SC_NAMED(i_59_s), SC_NAMED(i_59_old_s), SC_NAMED(o_59_s), SC_NAMED(o_59_old_s), SC_NAMED(i_60_s), SC_NAMED(i_60_old_s), SC_NAMED(o_60_s), SC_NAMED(o_60_old_s), SC_NAMED(i_62_s), SC_NAMED(i_62_old_s), SC_NAMED(o_62_s), SC_NAMED(o_62_old_s), SC_NAMED(i_64_s), SC_NAMED(i_64_old_s), SC_NAMED(o_64_s), SC_NAMED(o_64_old_s), SC_NAMED(i_119_s), SC_NAMED(i_119_old_s), SC_NAMED(o_119_s), SC_NAMED(o_119_old_s), SC_NAMED(i_120_s), SC_NAMED(i_120_old_s), SC_NAMED(o_120_s), SC_NAMED(o_120_old_s), SC_NAMED(i_121_s), SC_NAMED(i_121_old_s), SC_NAMED(o_121_s), SC_NAMED(o_121_old_s), SC_NAMED(i_127_s), SC_NAMED(i_127_old_s), SC_NAMED(o_127_s), SC_NAMED(o_127_old_s), SC_NAMED(i_128_s), SC_NAMED(i_128_old_s), SC_NAMED(o_128_s), SC_NAMED(o_128_old_s), SC_NAMED(i_255_s), SC_NAMED(i_255_old_s), SC_NAMED(o_255_s), SC_NAMED(o_255_old_s), SC_NAMED(i_256_s), SC_NAMED(i_256_old_s), SC_NAMED(o_256_s), SC_NAMED(o_256_old_s); tb->i_29(i_29_s); tb->i_29_old(i_29_old_s); tb->o_29(o_29_s); tb->o_29_old(o_29_old_s); tb->i_30(i_30_s); tb->i_30_old(i_30_old_s); tb->o_30(o_30_s); tb->o_30_old(o_30_old_s); tb->i_31(i_31_s); tb->i_31_old(i_31_old_s); tb->o_31(o_31_s); tb->o_31_old(o_31_old_s); tb->i_32(i_32_s); tb->i_32_old(i_32_old_s); tb->o_32(o_32_s); tb->o_32_old(o_32_old_s); tb->i_59(i_59_s); tb->i_59_old(i_59_old_s); tb->o_59(o_59_s); tb->o_59_old(o_59_old_s); tb->i_60(i_60_s); tb->i_60_old(i_60_old_s); tb->o_60(o_60_s); tb->o_60_old(o_60_old_s); tb->i_62(i_62_s); tb->i_62_old(i_62_old_s); tb->o_62(o_62_s); tb->o_62_old(o_62_old_s); tb->i_64(i_64_s); tb->i_64_old(i_64_old_s); tb->o_64(o_64_s); tb->o_64_old(o_64_old_s); tb->i_119(i_119_s); tb->i_119_old(i_119_old_s); tb->o_119(o_119_s); tb->o_119_old(o_119_old_s); tb->i_120(i_120_s); tb->i_120_old(i_120_old_s); tb->o_120(o_120_s); tb->o_120_old(o_120_old_s); tb->i_121(i_121_s); tb->i_121_old(i_121_old_s); tb->o_121(o_121_s); tb->o_121_old(o_121_old_s); tb->i_127(i_127_s); tb->i_127_old(i_127_old_s); tb->o_127(o_127_s); tb->o_127_old(o_127_old_s); tb->i_128(i_128_s); tb->i_128_old(i_128_old_s); tb->o_128(o_128_s); tb->o_128_old(o_128_old_s); tb->i_255(i_255_s); tb->i_255_old(i_255_old_s); tb->o_255(o_255_s); tb->o_255_old(o_255_old_s); tb->i_256(i_256_s); tb->i_256_old(i_256_old_s); tb->o_256(o_256_s); tb->o_256_old(o_256_old_s); // clang-format on #endif #ifdef SYSTEMC_VERSION sc_start(1, SC_NS); #else tb->eval(); #endif // This testcase is testing multi-thread safe VL_ASSIGN_SBW and VL_ASSIGN_WSB macros. // Testbench is assigning different number of bits from VlWide input_var variable to different // inputs. Values around multiple of 30 (i.e. BITS_PER_DIGIT defined in SystemC sc_nbdefs.h) // are tested with the special care, since it is the value by which the data_ptr of sc_biguint // underlying data type is increased by (and not expected 32, as width of uint32_t). // Correctness of the output is compared against the 'old' macro, which is correct but has // multi-threaded issue since it's using range function. Second part is testing VL_ASSIGN_WSB // in a reverse way, it is reading signals from the previous test, and comparing the output // with (fraction) of VlWide input_var variable. VL_ASSIGN_SBW(29, i_29_s, input_var); VL_ASSIGN_SBW_MT_ISSUE(29, i_29_old_s, input_var); VL_ASSIGN_SBW(30, i_30_s, input_var); VL_ASSIGN_SBW_MT_ISSUE(30, i_30_old_s, input_var); VL_ASSIGN_SBW(31, i_31_s, input_var); VL_ASSIGN_SBW_MT_ISSUE(31, i_31_old_s, input_var); VL_ASSIGN_SBW(32, i_32_s, input_var); VL_ASSIGN_SBW_MT_ISSUE(32, i_32_old_s, input_var); VL_ASSIGN_SBW(59, i_59_s, input_var); VL_ASSIGN_SBW_MT_ISSUE(59, i_59_old_s, input_var); VL_ASSIGN_SBW(60, i_60_s, input_var); VL_ASSIGN_SBW_MT_ISSUE(60, i_60_old_s, input_var); VL_ASSIGN_SBW(62, i_62_s, input_var); VL_ASSIGN_SBW_MT_ISSUE(62, i_62_old_s, input_var); VL_ASSIGN_SBW(64, i_64_s, input_var); VL_ASSIGN_SBW_MT_ISSUE(64, i_64_old_s, input_var); VL_ASSIGN_SBW(119, i_119_s, input_var); VL_ASSIGN_SBW_MT_ISSUE(119, i_119_old_s, input_var); VL_ASSIGN_SBW(120, i_120_s, input_var); VL_ASSIGN_SBW_MT_ISSUE(120, i_120_old_s, input_var); VL_ASSIGN_SBW(121, i_121_s, input_var); VL_ASSIGN_SBW_MT_ISSUE(121, i_121_old_s, input_var); VL_ASSIGN_SBW(127, i_127_s, input_var); VL_ASSIGN_SBW_MT_ISSUE(127, i_127_old_s, input_var); VL_ASSIGN_SBW(128, i_128_s, input_var); VL_ASSIGN_SBW_MT_ISSUE(128, i_128_old_s, input_var); VL_ASSIGN_SBW(255, i_255_s, input_var); VL_ASSIGN_SBW_MT_ISSUE(255, i_255_old_s, input_var); VL_ASSIGN_SBW(256, i_256_s, input_var); VL_ASSIGN_SBW_MT_ISSUE(256, i_256_old_s, input_var); #ifdef SYSTEMC_VERSION sc_start(1, SC_NS); #else tb->eval(); #endif compare_signals(o_29_s, o_29_old_s); compare_signals(o_30_s, o_30_old_s); compare_signals(o_31_s, o_31_old_s); compare_signals(o_32_s, o_32_old_s); compare_signals(o_59_s, o_59_old_s); compare_signals(o_60_s, o_60_old_s); compare_signals(o_62_s, o_62_old_s); compare_signals(o_64_s, o_64_old_s); compare_signals(o_119_s, o_119_old_s); compare_signals(o_120_s, o_120_old_s); compare_signals(o_121_s, o_121_old_s); compare_signals(o_127_s, o_127_old_s); compare_signals(o_128_s, o_128_old_s); compare_signals(o_255_s, o_255_old_s); compare_signals(o_256_s, o_256_old_s); //////////////////////////////// VL_ASSIGN_WSB(29, out_var, o_29_s); compareWls(29, input_var.data(), out_var.data()); VL_ASSIGN_WSB(30, out_var, o_30_s); compareWls(30, input_var.data(), out_var.data()); VL_ASSIGN_WSB(31, out_var, o_31_s); compareWls(31, input_var.data(), out_var.data()); VL_ASSIGN_WSB(32, out_var, o_32_s); compareWls(32, input_var.data(), out_var.data()); VL_ASSIGN_WSB(59, out_var, o_59_s); compareWls(59, input_var.data(), out_var.data()); VL_ASSIGN_WSB(60, out_var, o_60_s); compareWls(60, input_var.data(), out_var.data()); VL_ASSIGN_WSB(62, out_var, o_62_s); compareWls(62, input_var.data(), out_var.data()); VL_ASSIGN_WSB(64, out_var, o_64_s); compareWls(64, input_var.data(), out_var.data()); VL_ASSIGN_WSB(119, out_var, o_119_s); compareWls(119, input_var.data(), out_var.data()); VL_ASSIGN_WSB(120, out_var, o_120_s); compareWls(120, input_var.data(), out_var.data()); VL_ASSIGN_WSB(121, out_var, o_121_s); compareWls(121, input_var.data(), out_var.data()); VL_ASSIGN_WSB(127, out_var, o_127_s); compareWls(127, input_var.data(), out_var.data()); VL_ASSIGN_WSB(128, out_var, o_128_s); compareWls(128, input_var.data(), out_var.data()); VL_ASSIGN_WSB(255, out_var, o_255_s); compareWls(255, input_var.data(), out_var.data()); VL_ASSIGN_WSB(256, out_var, o_256_s); compareWls(256, input_var.data(), out_var.data()); tb->final(); VL_DO_DANGLING(delete tb, tb); if (pass) { VL_PRINTF("*-* All Finished *-*\n"); } else { vl_fatal(__FILE__, __LINE__, "top", "Unexpected results from test\n"); } return 0; } verilator-5.042/test_regress/t/t_trace_split_cfuncs_dpi_export.py0000755000542200017500000000100215101701376026066 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=["--trace-vcd", "--output-split-cfuncs", "1"]) test.passes() verilator-5.042/test_regress/t/t_mod_dollar$.v0000644000542200017500000000046515101701376021765 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by engr248. // SPDX-License-Identifier: CC0-1.0 module \foo$bar ; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_class_format.py0000755000542200017500000000100015101701376022432 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_var_const.py0000755000542200017500000000073415101701376021770 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_unused_iface.py0000755000542200017500000000077315101701376023455 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME"]) test.passes() verilator-5.042/test_regress/t/t_hier_block_import.v0000644000542200017500000000134015101701376023271 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2024 by Antmicro. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t(/*AUTOARG*/ // inputs clk ); input clk; bit [31:0] outA; bit [31:0] outB; subA subA(.out(outA)); subB subB(.out(outB)); always @(posedge clk) begin if (outA == `VALUE_A && outB == `VALUE_B) begin $write("*-* All Finished *-*\n"); $finish; end else begin $write("Mismatch\n"); $stop; end end endmodule verilator-5.042/test_regress/t/t_preproc_inc_notfound_bad.v0000644000542200017500000000037315101701376024630 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `include "this_file_is_not_found.vh" verilator-5.042/test_regress/t/t_class_super_bad2.v0000644000542200017500000000045015101701376023012 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 Rafal Kapuscik // SPDX-License-Identifier: CC0-1.0 // class Cls; task t; super.i = 1; // Bad - no extends endtask endclass verilator-5.042/test_regress/t/t_stream.v0000644000542200017500000002663315101701376021105 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014 by Glen Gibb. // SPDX-License-Identifier: CC0-1.0 //module t; module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; // The 'initial' code block below tests compilation-time // evaluation/optimization of the stream operator. All occurences of the stream // operator within this block are replaced prior to generation of C code. logic [3:0] dout; logic [31:0] dout32; logic [10:0] dout11; initial begin // Stream operator: << // Location: rhs of assignment // // Test slice sizes from 1 - 5 dout = { << {4'b0001}}; if (dout != 4'b1000) $stop; dout = { << 2 {4'b0001}}; if (dout != 4'b0100) $stop; dout = { << 3 {4'b0001}}; if (dout != 4'b0010) $stop; dout = { << 4 {4'b0001}}; if (dout != 4'b0001) $stop; dout = { << 5 {4'b0001}}; if (dout != 4'b0001) $stop; // Stream operator: >> // Location: rhs of assignment // // Right-streaming operator on RHS does not reorder bits dout = { >> {4'b0001}}; if (dout != 4'b0001) $stop; dout = { >> 2 {4'b0001}}; if (dout != 4'b0001) $stop; dout = { >> 3 {4'b0001}}; if (dout != 4'b0001) $stop; dout = { >> 4 {4'b0001}}; if (dout != 4'b0001) $stop; dout = { >> 5 {4'b0001}}; if (dout != 4'b0001) $stop; // Stream operator: << // Location: lhs of assignment { << {dout}} = 4'b0001; if (dout != 4'b1000) $stop; { << 2 {dout}} = 4'b0001; if (dout != 4'b0100) $stop; { << 3 {dout}} = 4'b0001; if (dout != 4'b0010) $stop; { << 4 {dout}} = 4'b0001; if (dout != 4'b0001) $stop; { << 5 {dout}} = 4'b0001; if (dout != 4'b0001) $stop; // Stream operator: >> // Location: lhs of assignment { >> {dout}} = 4'b0001; if (dout != 4'b0001) $stop; { >> 2 {dout}} = 4'b0001; if (dout != 4'b0001) $stop; { >> 3 {dout}} = 4'b0001; if (dout != 4'b0001) $stop; { >> 4 {dout}} = 4'b0001; if (dout != 4'b0001) $stop; { >> 5 {dout}} = 4'b0001; if (dout != 4'b0001) $stop; // Stream operator: << // Location: lhs of assignment // RHS is *wider* than LHS /* verilator lint_off WIDTH */ { << {dout}} = 5'b00001; if (dout != 4'b1000) $stop; { << 2 {dout}} = 5'b00001; if (dout != 4'b0100) $stop; { << 3 {dout}} = 5'b00001; if (dout != 4'b0010) $stop; { << 4 {dout}} = 5'b00001; if (dout != 4'b0001) $stop; { << 5 {dout}} = 5'b01101; if (dout != 4'b0110) $stop; /* verilator lint_on WIDTH */ // Stream operator: >> // Location: lhs of assignment // RHS is *wider* than LHS /* verilator lint_off WIDTH */ { >> {dout}} = 5'b01101; if (dout != 4'b0110) $stop; { >> 2 {dout}} = 5'b01101; if (dout != 4'b0110) $stop; { >> 3 {dout}} = 5'b01101; if (dout != 4'b0110) $stop; { >> 4 {dout}} = 5'b01101; if (dout != 4'b0110) $stop; { >> 5 {dout}} = 5'b01101; if (dout != 4'b0110) $stop; /* verilator lint_on WIDTH */ // Stream operator: << // Location: both sides of assignment { << {dout}} = { << {4'b0001}}; if (dout != 4'b0001) $stop; { << 2 {dout}} = { << 2 {4'b0001}}; if (dout != 4'b0001) $stop; { << 3 {dout}} = { << 3 {4'b0001}}; if (dout != 4'b0100) $stop; { << 4 {dout}} = { << 4 {4'b0001}}; if (dout != 4'b0001) $stop; { << 5 {dout}} = { << 5 {4'b0001}}; if (dout != 4'b0001) $stop; // Stream operator: << // Location: as an operand within a statement // // Test slice sizes from 1 - 5 if (4'({ << {4'b0001}}) != 4'b1000) $stop; if (4'({ << 2 {4'b0001}}) != 4'b0100) $stop; if (4'({ << 3 {4'b0001}}) != 4'b0010) $stop; if (4'({ << 4 {4'b0001}}) != 4'b0001) $stop; if (4'({ << 5 {4'b0001}}) != 4'b0001) $stop; // case dout32 = { << 3 { 32'b11010111000010100100010010010111 }}; if (dout32 != 32'he92910eb) $stop; dout11 = { << 4 { 11'b10010010111 }}; if (dout11 != 11'h3cc) $stop; end // The two always blocks below test run-time evaluation of the stream // operator in generated C code. // // Various stream operators are optimized away. Here's a brief summary: // // Stream op on RHS of assign // -------------------------- // X = { << a { Y } } --- C function evaluates stream operator // -- if log2(a) == int --> "fast" eval func // -- if log2(a) != int --> "slow" eval func // X = { >> a { Y } } --- stream operator is optimized away // // Stream op on LHS of assign // -------------------------- // Note: if Y.width() > X.width, then the MSBs of Y are used, not the LSBs! // { << a { X } } = Y --- stream operator is moved to RHS, eval as above // { >> a { X } } = Y --- stream operator is optimized away logic [31:0] din_i; logic [63:0] din_q; logic [95:0] din_w; // Stream op on RHS, left-stream operator logic [31:0] dout_rhs_ls_i; logic [63:0] dout_rhs_ls_q; logic [95:0] dout_rhs_ls_w; // Stream op on RHS, right-stream operator logic [31:0] dout_rhs_rs_i; logic [63:0] dout_rhs_rs_q; logic [95:0] dout_rhs_rs_w; // Stream op on both sides, left-stream operator logic [31:0] dout_bhs_ls_i; logic [63:0] dout_bhs_ls_q; logic [95:0] dout_bhs_ls_w; // Stream op on both sides, right-stream operator logic [31:0] dout_bhs_rs_i; logic [63:0] dout_bhs_rs_q; logic [95:0] dout_bhs_rs_w; // Stream operator on LHS (with concatenation on LHS) logic [3:0] din_lhs; logic [1:0] dout_lhs_ls_a, dout_lhs_ls_b; logic [1:0] dout_lhs_rs_a, dout_lhs_rs_b; // Addition operator on LHS, right-shift tests: // Testing various shift sizes to exercise fast + slow funcs logic [22:0] dout_rhs_ls_i_23_3; logic [22:0] dout_rhs_ls_i_23_4; logic [36:0] dout_rhs_ls_q_37_3; logic [36:0] dout_rhs_ls_q_37_4; always @* begin // Stream operator: << // Location: rhs of assignment // // Test each data type (I, Q, W) dout_rhs_ls_i = { << {din_i}}; dout_rhs_ls_q = { << {din_q}}; dout_rhs_ls_w = { << {din_w}}; // Stream operator: >> // Location: rhs of assignment dout_rhs_rs_i = { >> {din_i}}; dout_rhs_rs_q = { >> {din_q}}; dout_rhs_rs_w = { >> {din_w}}; // Stream operator: << // Location: lhs of assignment { << 2 {dout_lhs_ls_a, dout_lhs_ls_b}} = din_lhs; // Stream operator: >> // Location: lhs of assignment { >> 2 {dout_lhs_rs_a, dout_lhs_rs_b}} = din_lhs; // Stream operator: << // Location: both sides of assignment { << 5 {dout_bhs_ls_i}} = { << 5 {din_i}}; { << 5 {dout_bhs_ls_q}} = { << 5 {din_q}}; { << 5 {dout_bhs_ls_w}} = { << 5 {din_w}}; // Stream operator: >> // Location: both sides of assignment { >> 5 {dout_bhs_rs_i}} = { >> 5 {din_i}}; { >> 5 {dout_bhs_rs_q}} = { >> 5 {din_q}}; { >> 5 {dout_bhs_rs_w}} = { >> 5 {din_w}}; // Stream operator: << // Location: both sides of assignment { << 5 {dout_bhs_ls_i}} = { << 5 {din_i}}; { << 5 {dout_bhs_ls_q}} = { << 5 {din_q}}; { << 5 {dout_bhs_ls_w}} = { << 5 {din_w}}; // Stream operator: << // Location: rhs of assignment // // Verify both fast and slow paths (fast: sliceSize = power of 2) dout_rhs_ls_i_23_3 = { << 3 {din_i[22:0]}}; // SLOW dout_rhs_ls_i_23_4 = { << 4 {din_i[22:0]}}; // FAST dout_rhs_ls_q_37_3 = { << 3 {din_q[36:0]}}; // SLOW dout_rhs_ls_q_37_4 = { << 4 {din_q[36:0]}}; // FAST end always @(posedge clk) begin if (cyc != 0) begin cyc <= cyc + 1; if (cyc == 1) begin din_i <= 32'h00_00_00_01; din_q <= 64'h00_00_00_00_00_00_00_01; din_w <= 96'h00_00_00_00_00_00_00_00_00_00_00_01; din_lhs <= 4'b00_01; end if (cyc == 2) begin din_i <= 32'h04_03_02_01; din_q <= 64'h08_07_06_05_04_03_02_01; din_w <= 96'h0c_0b_0a_09_08_07_06_05_04_03_02_01; din_lhs <= 4'b01_11; if (dout_rhs_ls_i != 32'h80_00_00_00) $stop; if (dout_rhs_ls_q != 64'h80_00_00_00_00_00_00_00) $stop; if (dout_rhs_ls_w != 96'h80_00_00_00_00_00_00_00_00_00_00_00) $stop; if (dout_rhs_rs_i != 32'h00_00_00_01) $stop; if (dout_rhs_rs_q != 64'h00_00_00_00_00_00_00_01) $stop; if (dout_rhs_rs_w != 96'h00_00_00_00_00_00_00_00_00_00_00_01) $stop; if (dout_lhs_ls_a != 2'b01) $stop; if (dout_lhs_ls_b != 2'b00) $stop; if (dout_lhs_rs_a != 2'b00) $stop; if (dout_lhs_rs_b != 2'b01) $stop; if (dout_bhs_rs_i != 32'h00_00_00_01) $stop; if (dout_bhs_rs_q != 64'h00_00_00_00_00_00_00_01) $stop; if (dout_bhs_rs_w != 96'h00_00_00_00_00_00_00_00_00_00_00_01) $stop; if (dout_bhs_ls_i != 32'h00_00_00_10) $stop; if (dout_bhs_ls_q != 64'h00_00_00_00_00_00_01_00) $stop; if (dout_bhs_ls_w != 96'h00_00_00_00_00_00_00_00_00_00_00_04) $stop; if (dout_rhs_ls_i_23_3 != 23'h10_00_00) $stop; if (dout_rhs_ls_i_23_4 != 23'h08_00_00) $stop; if (dout_rhs_ls_q_37_3 != 37'h04_00_00_00_00) $stop; if (dout_rhs_ls_q_37_4 != 37'h02_00_00_00_00) $stop; end if (cyc == 3) begin // The values below test the strange shift-merge done at the end of // the fast stream operators. // All-1s in the bits being streamed should end up as all-1s. din_i <= 32'h00_7f_ff_ff; din_q <= 64'h00_00_00_1f_ff_ff_ff_ff; if (dout_rhs_ls_i != 32'h80_40_c0_20) $stop; if (dout_rhs_ls_q != 64'h80_40_c0_20_a0_60_e0_10) $stop; if (dout_rhs_ls_w != 96'h80_40_c0_20_a0_60_e0_10_90_50_d0_30) $stop; if (dout_rhs_rs_i != 32'h04_03_02_01) $stop; if (dout_rhs_rs_q != 64'h08_07_06_05_04_03_02_01) $stop; if (dout_rhs_rs_w != 96'h0c_0b_0a_09_08_07_06_05_04_03_02_01) $stop; if (dout_bhs_ls_i != 32'h40_30_00_18) $stop; if (dout_bhs_ls_q != 64'h06_00_c1_81_41_00_c1_80) $stop; if (dout_bhs_ls_w != 96'h30_2c_28_20_01_1c_1a_04_14_0c_00_06) $stop; if (dout_bhs_rs_i != 32'h04_03_02_01) $stop; if (dout_bhs_rs_q != 64'h08_07_06_05_04_03_02_01) $stop; if (dout_bhs_rs_w != 96'h0c_0b_0a_09_08_07_06_05_04_03_02_01) $stop; if (dout_lhs_ls_a != 2'b11) $stop; if (dout_lhs_ls_b != 2'b01) $stop; if (dout_lhs_rs_a != 2'b01) $stop; if (dout_lhs_rs_b != 2'b11) $stop; if (dout_rhs_ls_i_23_3 != 23'h10_08_c0) $stop; if (dout_rhs_ls_i_23_4 != 23'h08_10_18) $stop; if (dout_rhs_ls_q_37_3 != 37'h04_02_30_10_44) $stop; if (dout_rhs_ls_q_37_4 != 37'h02_04_06_08_0a) $stop; end if (cyc == 4) begin if (dout_rhs_ls_i_23_3 != 23'h7f_ff_ff) $stop; if (dout_rhs_ls_i_23_4 != 23'h7f_ff_ff) $stop; if (dout_rhs_ls_q_37_3 != 37'h1f_ff_ff_ff_ff) $stop; if (dout_rhs_ls_q_37_4 != 37'h1f_ff_ff_ff_ff) $stop; end if (cyc == 9) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.042/test_regress/t/t_param_array2.py0000755000542200017500000000073415101701376022352 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_foreach_iface.v0000644000542200017500000000134615101701376022342 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Pawel Jewstafjew (Pawel.Jewstafjew@gmail.com). // SPDX-License-Identifier: CC0-1.0 interface Iface (input bit [31:0] regs [1]); initial begin string instance_path = $sformatf("%m"); $display("Iface path %s\n", instance_path); $write("*-* All Finished *-*\n"); $finish; end bit [0:0] ppp; always_comb begin // Ok: //for (int index = 1 ; index < 2 ; ++index) begin foreach (regs[index]) begin ppp[index] = 1; end end endinterface module top (input bit [31:0] regs [1]); Iface t1(.regs(regs)); endmodule verilator-5.042/test_regress/t/t_for_disable_dot.v0000644000542200017500000000074215101701376022722 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; int i; initial begin begin : named for (i = 0; i < 10; ++i) begin : loop if (i == 5) disable t.named; end end if (i != 5) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_unopt_combo_bad.py0000755000542200017500000000123415101701376023120 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_unopt_combo.v" test.compile(v_flags2=['+define+ATTRIBUTES', "-fno-dfg"], fails=test.vlt_all, expect_filename=test.golden_filename) if not test.vlt_all: test.execute() test.passes() verilator-5.042/test_regress/t/t_class_this_constructor.v0000644000542200017500000000076315101701376024407 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class Cls; bit x = 1'b0; function new; Cls c; if (c == this) begin x = 1'b1; end endfunction endclass module t; Cls c; initial begin c = new; if (c.x) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_array_query.py0000755000542200017500000000073415101701376022335 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_flag_f.v0000644000542200017500000000150115101701376021013 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `include "t_flag_f_tsub_inc.v" module t; initial begin `ifndef GOT_DEF1 $write("%%Error: NO GOT_DEF1\n"); $stop; `endif `ifndef GOT_DEF2 $write("%%Error: NO GOT_DEF2\n"); $stop; `endif `ifndef GOT_DEF3 $write("%%Error: NO GOT_DEF3\n"); $stop; `endif `ifndef GOT_DEF4 $write("%%Error: NO GOT_DEF4\n"); $stop; `endif `ifndef GOT_DEF5 $write("%%Error: NO GOT_DEF5\n"); $stop; `endif `ifndef GOT_DEF6 $write("%%Error: NO GOT_DEF6\n"); $stop; `endif `ifdef NON_DEF $write("%%Error: NON_DEF\n"); $stop; `endif $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_langext_2012ext.py0000755000542200017500000000105515101701376022616 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_langext_2.v" # This is a compile only test. test.compile(v_flags2=["+1800-2012ext+v"]) test.passes() verilator-5.042/test_regress/t/t_preproc_inc2.vh0000644000542200017500000000046615101701376022343 0ustar mahmoudyfreeshell// DESCRIPTION: Verilog::Preproc: Example source code // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2000-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 At file `__FILE__ line `__LINE__ `define INCFILE `include `INCFILE verilator-5.042/test_regress/t/t_gen_for1.py0000755000542200017500000000073415101701376021472 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_math_countbits_tri.py0000755000542200017500000000077115101701376023674 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--assert']) test.execute() test.passes() verilator-5.042/test_regress/t/t_class_module.py0000755000542200017500000000073415101701376022444 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_var_port2_bad.v0000644000542200017500000000041515101701376022324 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (portwithoin); input portwithin; endmodule verilator-5.042/test_regress/t/t_flag_verilate.py0000755000542200017500000000365415101701376022602 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_flag_make_cmake.v" # We expect below that Vt_flag_verilate.mk and others are not in the build # tree already when doing --no-verilate, so we must remove them when # re-running the test. test.clean_objs() test.compile( # Don't call cmake nor gmake from driver.py. Nothing should be done here. verilator_make_cmake=False, verilator_make_gmake=False, verilator_flags2=['--exe --cc --no-verilate', '../' + test.main_filename]) # --no-verilate should skip Verilation if os.path.exists(test.obj_dir + '/Vt_flag_verilate.mk'): test.error('Vt_flag_verilate.mk is unexpectedly created') # --verilate this time test.compile( # Don't call cmake nor gmake from driver.py. Just verilate here. verilator_make_cmake=False, verilator_make_gmake=False, verilator_flags2=['--exe --cc --verilate', '../' + test.main_filename]) # must be verilated this time if not os.path.exists(test.obj_dir + '/Vt_flag_verilate.mk'): test.error('Vt_flag_verilate.mk does not exist') # Just build, no Verilation. .tree must not be saved even with --dump-tree option. test.compile( # Don't call cmake nor gmake from driver.py. Just build here verilator_flags2=[ '--exe --cc --build --no-verilate', '../' + test.main_filename, '--debugi 1 --dump-tree --dump-tree-addrids' ]) # The previous run must not verilated, only build is expected. if os.path.exists(test.obj_dir + '/Vt_flag_verilate_990_final.tree'): test.error('Unexpectedly verilated.') test.execute() test.passes() verilator-5.042/test_regress/t/t_package_dup_bad.out0000644000542200017500000000171115101701376023213 0ustar mahmoudyfreeshell%Warning-MODDUP: t/t_package_dup_bad.v:11:9: Duplicate declaration of package: 'pkg' 11 | package pkg; | ^~~ t/t_package_dup_bad.v:7:9: ... Location of original declaration 7 | package pkg; | ^~~ ... For warning description see https://verilator.org/warn/MODDUP?v=latest ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message. %Warning-MODDUP: t/t_package_dup_bad.v:19:9: Duplicate declaration of package: 'pkg' 19 | package pkg; | ^~~ t/t_package_dup_bad.v:7:9: ... Location of original declaration 7 | package pkg; | ^~~ %Warning-MODDUP: t/t_package_dup_bad.v:22:9: Duplicate declaration of package: 'pkg' 22 | package pkg; | ^~~ t/t_package_dup_bad.v:7:9: ... Location of original declaration 7 | package pkg; | ^~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_stmt_incr_unsup.v0000644000542200017500000000075715101701376023045 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 Krzysztof Boronski. // SPDX-License-Identifier: CC0-1.0 int i = 0; function int postincrement_i; return i++; endfunction module t; initial begin int arr [3][3] = {{1, 2, 3}, {4, 5, 6}, {7, 8, 9}}; i = 0; arr[postincrement_i()][postincrement_i()]++; $display("Value: %d", i); end endmodule verilator-5.042/test_regress/t/t_interface_nest.v0000644000542200017500000000236715101701376022601 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017. // SPDX-License-Identifier: CC0-1.0 interface if1; integer var1; endinterface interface if2; if1 i1 (); integer var2; endinterface module mod1 ( input clk, input integer modnum, // Don't use parameter, want same module twice for better checking if2 foo ); logic l1, l2; always_ff @(posedge clk) begin if (modnum==1) begin if (foo.i1.var1 != 1) $stop; if (foo.var2 != 2) $stop; end if (modnum==2) begin if (foo.i1.var1 != 1) $stop; if (foo.var2 != 2) $stop; end end endmodule module t (/*AUTOARG*/ // Inputs clk ); input clk; if2 i2a (); if2 i2b (); assign i2a.i1.var1 = 1; assign i2a.var2 = 2; assign i2b.i1.var1 = 3; assign i2b.var2 = 4; mod1 mod1a ( .modnum (1), .clk (clk), .foo (i2a) ); mod1 mod1b ( .modnum (2), .clk (clk), .foo (i2a) ); integer cyc = 0; always_ff @(posedge clk) begin cyc <= cyc+1; if (cyc==2) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_wait_timing.py0000755000542200017500000000104315101701376022277 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_wait.v" test.compile(verilator_flags2=["--binary -Wno-WAITCONST"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_enum_base_bad.py0000755000542200017500000000076615101701376022543 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_process_kill.py0000755000542200017500000000077115101701376022464 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--timing"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_strength_2_uneq_assign.out0000644000542200017500000000126715101701376024623 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_strength_2_uneq_assign.v:10:30: Unsupported: Unable to resolve unequal strength specifier : ... note: In instance 't' 10 | assign (weak0, strong1) a = clk ? 'z : '0; | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_strength_2_uneq_assign.v:11:30: Unsupported: Unable to resolve unequal strength specifier : ... note: In instance 't' 11 | assign (strong0, pull1) a = 6'b110001; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_func_task_bad2.py0000755000542200017500000000102515101701376022631 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=['--timing'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_vpi_get_value_array.cpp0000644000542200017500000006506115101701376024154 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2024 by Diego Roux. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #ifndef IS_VPI #include "verilated.h" #include "verilated_vpi.h" #include "Vt_vpi_get_value_array.h" #endif extern "C" { #include } // These require the above. Comment prevents clang-format moving them #include "TestSimulator.h" #include "TestVpi.h" #include //====================================================================== int test_vpiRawFourStateVal(char* name, PLI_BYTE8* test_data, int index, const unsigned low, const unsigned num, const unsigned size, const unsigned elem_size) { #ifdef TEST_VERBOSE printf("%%\n%s: name=%s index=%u low=%u num=%u size=%u elem_size=%u\n\n", __func__, name, index, low, num, size, elem_size); #endif // prepare index int index_arr[1] = {index}; // get array handle TestVpiHandle arrayhandle = vpi_handle_by_name(name, NULL); CHECK_RESULT_NZ(arrayhandle); // test raw fourstate s_vpi_arrayvalue arrayvalue; arrayvalue.format = vpiRawFourStateVal; arrayvalue.flags = 0; arrayvalue.value.vectors = 0; vpi_get_value_array(arrayhandle, &arrayvalue, index_arr, num); CHECK_RESULT_NZ(!vpi_chk_error(0)); // compare to test data index -= low; for (unsigned i = 0; i < num; i++) { const unsigned offset = (index + i) % size; for (unsigned j = 0; j < elem_size; j++) { #ifdef TEST_VERBOSE printf("arr[%u] == test[%u]\n", (i * 2 * elem_size) + j, (offset * elem_size) + j); #endif CHECK_RESULT_HEX(arrayvalue.value.rawvals[(i * 2 * elem_size) + j], test_data[(offset * elem_size) + j]); } for (unsigned j = 0; j < elem_size; j++) { CHECK_RESULT_HEX(arrayvalue.value.rawvals[(((i * 2) + 1) * elem_size) + j], 0); } } return 0; } int test_vpiRawTwoStateVal(char* name, PLI_BYTE8* test_data, int index, const unsigned low, const unsigned num, const unsigned size, const unsigned elem_size) { #ifdef TEST_VERBOSE printf("%%\n%s: name=%s index=%u low=%u num=%u size=%u elem_size=%u\n\n", __func__, name, index, low, num, size, elem_size); #endif // prepare index int index_arr[1] = {index}; // get array handle TestVpiHandle arrayhandle = vpi_handle_by_name(name, NULL); CHECK_RESULT_NZ(arrayhandle); // test raw two state s_vpi_arrayvalue arrayvalue; arrayvalue.format = vpiRawTwoStateVal; arrayvalue.flags = 0; arrayvalue.value.vectors = 0; vpi_get_value_array(arrayhandle, &arrayvalue, index_arr, num); CHECK_RESULT_NZ(!vpi_chk_error(0)); // compare to test data index -= low; for (unsigned i = 0; i < num; i++) { const unsigned offset = (index + i) % size; for (unsigned j = 0; j < elem_size; j++) { #ifdef TEST_VERBOSE printf("arr[%u] == test[%u]\n", (i * elem_size) + j, (offset * elem_size) + j); #endif CHECK_RESULT_HEX(arrayvalue.value.rawvals[(i * elem_size) + j], test_data[(offset * elem_size) + j]); } } return 0; } int test_vpiVectorVal(char* name, PLI_BYTE8* test_data, int index, const unsigned low, const unsigned num, const unsigned size, const unsigned elem_size) { #ifdef TEST_VERBOSE printf("%%\n%s: name=%s index=%u low=%u num=%u size=%u elem_size=%u\n\n", __func__, name, index, low, num, size, elem_size); #endif // prepare index int index_arr[1] = {index}; const unsigned elem_size_words = (elem_size + 3) / sizeof(PLI_UINT32); const unsigned vec_size = elem_size_words * size; std::vector test_data_vectors; test_data_vectors.resize(vec_size); unsigned test_data_index = 0; for (unsigned i = 0; i < size; i++) { unsigned count = 0; for (unsigned j = 0; j < elem_size_words; j++) { PLI_UINT32& aval = test_data_vectors[(i * elem_size_words) + j].aval; test_data_vectors[(i * elem_size_words) + j].bval = UINT32_MAX; aval = 0; for (unsigned k = 0; k < sizeof(PLI_UINT32); k++) { if (count++ == elem_size) break; aval |= static_cast(test_data[test_data_index++] & 0xFF) << (k * 8); } } } // get array handle TestVpiHandle arrayhandle = vpi_handle_by_name(name, NULL); CHECK_RESULT_NZ(arrayhandle); // test vector s_vpi_arrayvalue arrayvalue; arrayvalue.format = vpiVectorVal; arrayvalue.flags = 0; arrayvalue.value.vectors = 0; vpi_get_value_array(arrayhandle, &arrayvalue, index_arr, num); CHECK_RESULT_NZ(!vpi_chk_error(0)); #ifdef TEST_VERBOSE for (unsigned i = 0; i < vec_size; i++) { printf("arr[%u]=%x test[%u]=%x\n", i, arrayvalue.value.vectors[i].aval, i, test_data_vectors[i].aval); } #endif // compare to test data index -= low; for (unsigned i = 0; i < num; i++) { const unsigned offset = (index + i) % size; for (unsigned j = 0; j < elem_size_words; j++) { #ifdef TEST_VERBOSE printf("array[%u] == test[%u]\n", (i * elem_size_words) + j, (offset * elem_size_words) + j); #endif CHECK_RESULT_HEX(arrayvalue.value.vectors[(i * elem_size_words) + j].aval, test_data_vectors[(offset * elem_size_words) + j].aval); CHECK_RESULT_HEX(arrayvalue.value.vectors[(i * elem_size_words) + j].bval, 0); } } return 0; } int test_vpiIntVal(char* name, PLI_BYTE8* test_data, int index, const unsigned low, const unsigned num, const unsigned size, const unsigned elem_size) { #ifdef TEST_VERBOSE printf("%%\n%s: name=%s index=%u low=%u num=%u size=%u elem_size=%u\n\n", __func__, name, index, low, num, size, elem_size); #endif // prepare index int index_arr[1] = {index}; std::vector test_data_integers; test_data_integers.resize(size); for (unsigned i = 0; i < size; i++) { PLI_INT32& integer = test_data_integers[i]; integer = 0; for (unsigned j = 0; j < elem_size; j++) { integer |= (static_cast(test_data[(i * elem_size) + j]) & 0xFF) << (j * 8); } } // get array handle TestVpiHandle arrayhandle = vpi_handle_by_name(name, NULL); CHECK_RESULT_NZ(arrayhandle); // test raw fourstate s_vpi_arrayvalue arrayvalue; arrayvalue.format = vpiIntVal; arrayvalue.flags = 0; arrayvalue.value.integers = 0; vpi_get_value_array(arrayhandle, &arrayvalue, index_arr, num); CHECK_RESULT_NZ(!vpi_chk_error(0)); #ifdef TEST_VERBOSE for (unsigned i = 0; i < size; i++) { printf("arr[%u]=%x test[%u]=%x\n", i, arrayvalue.value.integers[i], i, test_data_integers[i]); } #endif // compare to test data index -= low; for (unsigned i = 0; i < num; i++) { const unsigned offset = (index + i) % size; #ifdef TEST_VERBOSE printf("array[%u] == test[%u]\n", i, offset); #endif CHECK_RESULT_HEX(arrayvalue.value.integers[i], test_data_integers[offset]); } return 0; } int test_vpiShortIntVal(char* name, PLI_BYTE8* test_data, int index, const unsigned low, const unsigned num, const unsigned size, const unsigned elem_size) { #ifdef TEST_VERBOSE printf("%%\n%s: name=%s index=%u low=%u num=%u size=%u elem_size=%u\n\n", __func__, name, index, low, num, size, elem_size); #endif // prepare index int index_arr[1] = {index}; std::vector test_data_shortints; test_data_shortints.resize(size); for (unsigned i = 0; i < size; i++) { if (elem_size == 2) { test_data_shortints[i] = test_data[i * 2] & 0xFF; test_data_shortints[i] |= test_data[(i * 2) + 1] << 8; } else { test_data_shortints[i] = test_data[i] & 0xFF; } } // get array handle TestVpiHandle arrayhandle = vpi_handle_by_name(name, NULL); CHECK_RESULT_NZ(arrayhandle); // test raw fourstate s_vpi_arrayvalue arrayvalue; arrayvalue.format = vpiShortIntVal; arrayvalue.flags = 0; arrayvalue.value.shortints = 0; vpi_get_value_array(arrayhandle, &arrayvalue, index_arr, num); CHECK_RESULT_NZ(!vpi_chk_error(0)); #ifdef TEST_VERBOSE for (unsigned i = 0; i < size; i++) { printf("arr[%u]=%x test[%u]=%x\n", i, arrayvalue.value.shortints[i], i, test_data_shortints[i]); } #endif // compare to test data index -= low; for (unsigned i = 0; i < num; i++) { const unsigned offset = (index + i) % size; #ifdef TEST_VERBOSE printf("array[%u] == test[%u]\n", i, offset); #endif CHECK_RESULT_HEX(arrayvalue.value.shortints[i], test_data_shortints[offset]); } return 0; } int test_vpiLongIntVal(char* name, PLI_BYTE8* test_data, int index, const unsigned low, const unsigned num, const unsigned size, const unsigned elem_size) { #ifdef TEST_VERBOSE printf("%%\n%s: name=%s index=%u low=%u num=%u size=%u elem_size=%u\n\n", __func__, name, index, low, num, size, elem_size); #endif // prepare index int index_arr[1] = {index}; std::vector test_data_longints; test_data_longints.resize(size); for (unsigned i = 0; i < size; i++) { PLI_INT64& longint = test_data_longints[i]; longint = 0; for (unsigned j = 0; j < elem_size; j++) { longint |= (static_cast(test_data[(i * elem_size) + j]) & 0xFF) << (j * 8); } } // get array handle TestVpiHandle arrayhandle = vpi_handle_by_name(name, NULL); CHECK_RESULT_NZ(arrayhandle); // test raw fourstate s_vpi_arrayvalue arrayvalue; arrayvalue.format = vpiLongIntVal; arrayvalue.flags = 0; arrayvalue.value.longints = 0; vpi_get_value_array(arrayhandle, &arrayvalue, index_arr, num); CHECK_RESULT_NZ(!vpi_chk_error(0)); // compare to test data index -= low; for (unsigned i = 0; i < num; i++) { const unsigned offset = (index + i) % size; #ifdef TEST_VERBOSE printf("array[%u] == test[%u]\n", i, offset); #endif CHECK_RESULT_HEX(arrayvalue.value.longints[i], test_data_longints[offset]); } return 0; } int mon_check_props() { // skip test if not verilator (value_array accessors unimplemented in other sims) if (!TestSimulator::is_verilator()) { #ifdef VERILATOR printf("TestSimulator indicating not verilator, but VERILATOR macro is defined\n"); return 1; #endif return 0; } const unsigned NUM_ELEMENTS = 4; PLI_BYTE8 read_bytes[NUM_ELEMENTS] = {static_cast(0xad), static_cast(0xde), static_cast(0xef), static_cast(0xbe)}; PLI_BYTE8 read_shorts[NUM_ELEMENTS * 2] = { static_cast(0xad), static_cast(0xde), static_cast(0xef), static_cast(0xbe), static_cast(0xfe), static_cast(0xca), static_cast(0x0d), static_cast(0xf0)}; PLI_BYTE8 read_words[NUM_ELEMENTS * 4] = { static_cast(0xef), static_cast(0xbe), static_cast(0xad), static_cast(0xde), static_cast(0x0d), static_cast(0xf0), static_cast(0xfe), static_cast(0xca), static_cast(0x03), static_cast(0x02), static_cast(0x01), static_cast(0x00), static_cast(0x07), static_cast(0x06), static_cast(0x05), static_cast(0x04)}; PLI_BYTE8 read_longs[NUM_ELEMENTS * 8] = { static_cast(0x0d), static_cast(0xf0), static_cast(0xfe), static_cast(0xca), static_cast(0xef), static_cast(0xbe), static_cast(0xad), static_cast(0xde), static_cast(0x07), static_cast(0x06), static_cast(0x05), static_cast(0x04), static_cast(0x03), static_cast(0x02), static_cast(0x01), static_cast(0x00), static_cast(0x0F), static_cast(0x0E), static_cast(0x0D), static_cast(0x0C), static_cast(0x0B), static_cast(0x0A), static_cast(0x09), static_cast(0x08), static_cast(0x17), static_cast(0x16), static_cast(0x15), static_cast(0x14), static_cast(0x13), static_cast(0x12), static_cast(0x11), static_cast(0x10)}; PLI_BYTE8 read_customs[NUM_ELEMENTS * 9] = { static_cast(0x0d), static_cast(0xf0), static_cast(0xfe), static_cast(0xca), static_cast(0xef), static_cast(0xbe), static_cast(0xad), static_cast(0xde), static_cast(0x1A), static_cast(0x07), static_cast(0x06), static_cast(0x05), static_cast(0x04), static_cast(0x03), static_cast(0x02), static_cast(0x01), static_cast(0x00), static_cast(0x15), static_cast(0x0F), static_cast(0x0E), static_cast(0x0D), static_cast(0x0C), static_cast(0x0B), static_cast(0x0A), static_cast(0x09), static_cast(0x08), static_cast(0x0A), static_cast(0x17), static_cast(0x16), static_cast(0x15), static_cast(0x14), static_cast(0x13), static_cast(0x12), static_cast(0x11), static_cast(0x10), static_cast(0x05)}; char read_bytes_name[] = "test.read_bytes"; char read_bytes_nonzero_index_name[] = "test.read_bytes_nonzero_index"; char read_bytes_rl_name[] = "test.read_bytes_rl"; char read_shorts_name[] = "test.read_shorts"; char read_words_name[] = "test.read_words"; char read_integers_name[] = "test.read_integers"; char read_longs_name[] = "test.read_longs"; char read_customs_name[] = "test.read_customs"; char read_customs_nonzero_index_rl_name[] = "test.read_customs_nonzero_index_rl"; for (unsigned i = 0; i < NUM_ELEMENTS; i++) { for (unsigned j = 0; j < (NUM_ELEMENTS + 1); j++) { if (test_vpiRawFourStateVal(read_bytes_name, read_bytes, i, 0, j, NUM_ELEMENTS, 1)) return 1; if (test_vpiRawFourStateVal(read_bytes_nonzero_index_name, read_bytes, i + 1, 1, j, NUM_ELEMENTS, 1)) return 1; if (test_vpiRawFourStateVal(read_bytes_rl_name, read_bytes, i, 0, j, NUM_ELEMENTS, 1)) return 1; if (test_vpiRawFourStateVal(read_shorts_name, read_shorts, i, 0, j, NUM_ELEMENTS, 2)) return 1; if (test_vpiRawFourStateVal(read_words_name, read_words, i, 0, j, NUM_ELEMENTS, 4)) return 1; if (test_vpiRawFourStateVal(read_integers_name, read_words, i, 0, j, NUM_ELEMENTS, 4)) return 1; if (test_vpiRawFourStateVal(read_longs_name, read_longs, i, 0, j, NUM_ELEMENTS, 8)) return 1; if (test_vpiRawFourStateVal(read_customs_name, read_customs, i, 0, j, NUM_ELEMENTS, 9)) return 1; if (test_vpiRawFourStateVal(read_customs_nonzero_index_rl_name, read_customs, i + 1, 1, j, NUM_ELEMENTS, 9)) return 1; if (test_vpiRawTwoStateVal(read_bytes_name, read_bytes, i, 0, j, NUM_ELEMENTS, 1)) return 1; if (test_vpiRawTwoStateVal(read_bytes_rl_name, read_bytes, i, 0, j, NUM_ELEMENTS, 1)) return 1; if (test_vpiRawTwoStateVal(read_bytes_nonzero_index_name, read_bytes, i + 1, 1, j, NUM_ELEMENTS, 1)) return 1; if (test_vpiRawTwoStateVal(read_shorts_name, read_shorts, i, 0, j, NUM_ELEMENTS, 2)) return 1; if (test_vpiRawTwoStateVal(read_words_name, read_words, i, 0, j, NUM_ELEMENTS, 4)) return 1; if (test_vpiRawTwoStateVal(read_integers_name, read_words, i, 0, j, NUM_ELEMENTS, 4)) return 1; if (test_vpiRawTwoStateVal(read_longs_name, read_longs, i, 0, j, NUM_ELEMENTS, 8)) return 1; if (test_vpiRawTwoStateVal(read_customs_name, read_customs, i, 0, j, NUM_ELEMENTS, 9)) return 1; if (test_vpiRawTwoStateVal(read_customs_nonzero_index_rl_name, read_customs, i + 1, 1, j, NUM_ELEMENTS, 9)) return 1; if (test_vpiVectorVal(read_bytes_name, read_bytes, i, 0, j, NUM_ELEMENTS, 1)) return 1; if (test_vpiVectorVal(read_bytes_nonzero_index_name, read_bytes, i + 1, 1, j, NUM_ELEMENTS, 1)) return 1; if (test_vpiVectorVal(read_bytes_rl_name, read_bytes, i, 0, j, NUM_ELEMENTS, 1)) return 1; if (test_vpiVectorVal(read_shorts_name, read_shorts, i, 0, j, NUM_ELEMENTS, 2)) return 1; if (test_vpiVectorVal(read_words_name, read_words, i, 0, j, NUM_ELEMENTS, 4)) return 1; if (test_vpiVectorVal(read_integers_name, read_words, i, 0, j, NUM_ELEMENTS, 4)) return 1; if (test_vpiVectorVal(read_longs_name, read_longs, i, 0, j, NUM_ELEMENTS, 8)) return 1; if (test_vpiVectorVal(read_customs_name, read_customs, i, 0, j, NUM_ELEMENTS, 9)) return 1; if (test_vpiVectorVal(read_customs_nonzero_index_rl_name, read_customs, i + 1, 1, j, NUM_ELEMENTS, 9)) return 1; if (test_vpiShortIntVal(read_bytes_name, read_bytes, i, 0, j, NUM_ELEMENTS, 1)) return 1; if (test_vpiShortIntVal(read_bytes_nonzero_index_name, read_bytes, i + 1, 1, j, NUM_ELEMENTS, 1)) return 1; if (test_vpiShortIntVal(read_bytes_rl_name, read_bytes, i, 0, j, NUM_ELEMENTS, 1)) return 1; if (test_vpiShortIntVal(read_shorts_name, read_shorts, i, 0, j, NUM_ELEMENTS, 2)) return 1; if (test_vpiIntVal(read_bytes_name, read_bytes, i, 0, j, NUM_ELEMENTS, 1)) return 1; if (test_vpiIntVal(read_bytes_nonzero_index_name, read_bytes, i + 1, 1, j, NUM_ELEMENTS, 1)) return 1; if (test_vpiIntVal(read_bytes_rl_name, read_bytes, i, 0, j, NUM_ELEMENTS, 1)) return 1; if (test_vpiIntVal(read_words_name, read_words, i, 0, j, NUM_ELEMENTS, 4)) return 1; if (test_vpiIntVal(read_integers_name, read_words, i, 0, j, NUM_ELEMENTS, 4)) return 1; if (test_vpiLongIntVal(read_bytes_name, read_bytes, i, 0, j, NUM_ELEMENTS, 1)) return 1; if (test_vpiLongIntVal(read_bytes_nonzero_index_name, read_bytes, i + 1, 1, j, NUM_ELEMENTS, 1)) return 1; if (test_vpiLongIntVal(read_bytes_rl_name, read_bytes, i, 0, j, NUM_ELEMENTS, 1)) return 1; if (test_vpiLongIntVal(read_shorts_name, read_shorts, i, 0, j, NUM_ELEMENTS, 2)) return 1; if (test_vpiLongIntVal(read_words_name, read_words, i, 0, j, NUM_ELEMENTS, 4)) return 1; if (test_vpiLongIntVal(read_integers_name, read_words, i, 0, j, NUM_ELEMENTS, 4)) return 1; if (test_vpiLongIntVal(read_longs_name, read_longs, i, 0, j, NUM_ELEMENTS, 8)) return 1; } } { // test unsupported format TestVpiHandle object = vpi_handle_by_name((PLI_BYTE8*)"test.read_longs", NULL); CHECK_RESULT_NZ(object); s_vpi_arrayvalue arrayvalue; arrayvalue.format = vpiRealVal; arrayvalue.flags = 0; arrayvalue.value.integers = 0; PLI_INT32 indexp[1] = {0}; vpi_get_value_array(object, &arrayvalue, indexp, NUM_ELEMENTS); CHECK_RESULT_NZ(vpi_chk_error(0)); } { // test unsupported foramt TestVpiHandle object = vpi_handle_by_name((PLI_BYTE8*)"test.read_words", NULL); CHECK_RESULT_NZ(object); s_vpi_arrayvalue arrayvalue; arrayvalue.format = vpiShortRealVal; arrayvalue.flags = 0; arrayvalue.value.integers = 0; PLI_INT32 indexp[1] = {0}; vpi_get_value_array(object, &arrayvalue, indexp, NUM_ELEMENTS); CHECK_RESULT_NZ(vpi_chk_error(0)); } { // test unsupported format TestVpiHandle object = vpi_handle_by_name((PLI_BYTE8*)"test.read_longs", NULL); CHECK_RESULT_NZ(object); s_vpi_arrayvalue arrayvalue; arrayvalue.format = vpiTimeVal; arrayvalue.flags = 0; arrayvalue.value.integers = 0; PLI_INT32 indexp[1] = {0}; vpi_get_value_array(object, &arrayvalue, indexp, NUM_ELEMENTS); CHECK_RESULT_NZ(vpi_chk_error(0)); } { // test unsupported TestVpiHandle TestVpiHandle object = vpi_handle_by_name((PLI_BYTE8*)"test", NULL); CHECK_RESULT_NZ(object); s_vpi_arrayvalue arrayvalue; arrayvalue.format = vpiIntVal; arrayvalue.flags = 0; arrayvalue.value.integers = 0; PLI_INT32 indexp[1] = {0}; vpi_get_value_array(object, &arrayvalue, indexp, NUM_ELEMENTS); CHECK_RESULT_NZ(vpi_chk_error(0)); } { // test unsupported type TestVpiHandle object = vpi_handle_by_name((PLI_BYTE8*)"test.read_scalar", NULL); CHECK_RESULT_NZ(object); s_vpi_arrayvalue arrayvalue; arrayvalue.format = vpiIntVal; arrayvalue.flags = 0; arrayvalue.value.integers = 0; PLI_INT32 indexp[1] = {0}; vpi_get_value_array(object, &arrayvalue, indexp, NUM_ELEMENTS); CHECK_RESULT_NZ(vpi_chk_error(0)); } { // test indexp out of bounds TestVpiHandle object = vpi_handle_by_name((PLI_BYTE8*)"test.read_bounds", NULL); CHECK_RESULT_NZ(object); s_vpi_arrayvalue arrayvalue; arrayvalue.format = vpiIntVal; arrayvalue.flags = 0; arrayvalue.value.integers = 0; PLI_INT32 indexp[1] = {4}; vpi_get_value_array(object, &arrayvalue, indexp, NUM_ELEMENTS); CHECK_RESULT_NZ(vpi_chk_error(0)); indexp[0] = 0; vpi_get_value_array(object, &arrayvalue, indexp, NUM_ELEMENTS); CHECK_RESULT_NZ(vpi_chk_error(0)); } { // test unsupported flags TestVpiHandle object = vpi_handle_by_name((PLI_BYTE8*)"test.read_words", NULL); CHECK_RESULT_NZ(object); s_vpi_arrayvalue arrayvalue; arrayvalue.format = vpiIntVal; arrayvalue.flags = vpiUserAllocFlag; arrayvalue.value.integers = 0; PLI_INT32 indexp[1] = {0}; vpi_get_value_array(object, &arrayvalue, indexp, NUM_ELEMENTS); CHECK_RESULT_NZ(vpi_chk_error(0)); } { // test unsupported format & vltype combination TestVpiHandle object = vpi_handle_by_name((PLI_BYTE8*)"test.read_words", NULL); CHECK_RESULT_NZ(object); s_vpi_arrayvalue arrayvalue; arrayvalue.format = vpiShortIntVal; arrayvalue.flags = 0; arrayvalue.value.integers = 0; PLI_INT32 indexp[1] = {0}; vpi_get_value_array(object, &arrayvalue, indexp, NUM_ELEMENTS); CHECK_RESULT_NZ(vpi_chk_error(0)); } { // test num out of bounds TestVpiHandle object = vpi_handle_by_name((PLI_BYTE8*)"test.read_words", NULL); CHECK_RESULT_NZ(object); s_vpi_arrayvalue arrayvalue; arrayvalue.format = vpiIntVal; arrayvalue.flags = 0; arrayvalue.value.integers = 0; PLI_INT32 indexp[1] = {0}; vpi_get_value_array(object, &arrayvalue, indexp, 5); CHECK_RESULT_NZ(vpi_chk_error(0)); } { // test null arrayvalue TestVpiHandle object = vpi_handle_by_name((PLI_BYTE8*)"test.read_words", NULL); CHECK_RESULT_NZ(object); PLI_INT32 indexp[1] = {0}; vpi_get_value_array(object, 0, indexp, 0); CHECK_RESULT_NZ(vpi_chk_error(0)); } { // test null indexp TestVpiHandle object = vpi_handle_by_name((PLI_BYTE8*)"test.read_words", NULL); CHECK_RESULT_NZ(object); s_vpi_arrayvalue arrayvalue; arrayvalue.format = vpiIntVal; arrayvalue.flags = 0; arrayvalue.value.integers = 0; vpi_get_value_array(object, &arrayvalue, 0, 0); CHECK_RESULT_NZ(vpi_chk_error(0)); } return 0; } extern "C" int mon_check(void) { return mon_check_props(); } #ifdef IS_VPI static int mon_check_vpi() { TestVpiHandle href = vpi_handle(vpiSysTfCall, 0); s_vpi_value vpi_value; vpi_value.format = vpiIntVal; vpi_value.value.integer = mon_check(); vpi_put_value(href, &vpi_value, NULL, vpiNoDelay); return 0; } static s_vpi_systf_data vpi_systf_data[] = {{vpiSysFunc, vpiIntFunc, (PLI_BYTE8*)"$mon_check", (PLI_INT32(*)(PLI_BYTE8*))mon_check_vpi, 0, 0, 0}, 0}; // cver entry void vpi_compat_bootstrap(void) { p_vpi_systf_data systf_data_p; systf_data_p = &(vpi_systf_data[0]); while (systf_data_p->type != 0) vpi_register_systf(systf_data_p++); } // icarus entry void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0}; #else int main(int argc, char** argv) { Verilated::commandArgs(argc, argv); const std::unique_ptr contextp{new VerilatedContext}; const std::unique_ptr top{new VM_PREFIX{contextp.get(), ""}}; contextp->fatalOnVpiError(0); #ifdef VERILATOR #ifdef TEST_VERBOSE contextp->scopesDump(); #endif #endif while (!contextp->gotFinish()) { top->eval(); } return 0; } #endif verilator-5.042/test_regress/t/t_func_recurse_param_bad.out0000644000542200017500000003035215101701376024616 0ustar mahmoudyfreeshell%Error: t/t_func_recurse_param_bad.v:15:25: Expecting expression to be constant, but can't determine constant for FUNCREF 'recurse_self' : ... note: In instance 't' t/t_func_recurse_param_bad.v:9:26: ... Location of non-constant FUNC 'recurse_self': Constant function recursed more than 1000 times t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 t/t_func_recurse_param_bad.v:12:29: ... Called from 'recurse_self()' with parameters: i = 32'h2329 ... stack truncated 15 | localparam int HUGE = recurse_self(10000); | ^~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_interface_generic_modport_bad2.v0000644000542200017500000000104215101701376025665 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 interface inf; int v; modport mp ( input v ); endinterface module GenericModule (interface.mp a); initial begin #1; a.v = 10; end endmodule module t; inf inf_inst(); GenericModule genericModule (inf_inst); initial begin inf_inst.v = 7; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_generate_fatal_bad.py0000755000542200017500000000076615101701376023546 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_savable.v0000644000542200017500000000611415101701376021217 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk, model ); /*verilator no_inline_module*/ // So we'll get hiearachy we can test input clk; // Parameter so we can test for different model error parameter MODEL_WIDTH = 10; input [MODEL_WIDTH-1:0] model; initial $write("Model width = %0d\n", MODEL_WIDTH); sub sub (/*AUTOINST*/ // Inputs .clk (clk)); endmodule module sub (/*AUTOARG*/ // Inputs clk ); input clk; /*verilator no_inline_module*/ // So we'll get hiearachy we can test integer cyc = 0; reg [127:0] save128; reg [47:0] save48; reg [1:0] save2; bit [255:0] cycdone; // Make sure each cycle executes exactly once reg [31:0] vec[2:1][2:1]; reg [2:1][2:1][31:0] pvec; real r; string s,s2; string sarr[2:1]; string assoc[string]; string si; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d\n", $time, cyc); `endif si = "siimmed"; cyc <= cyc + 1; if (cycdone[cyc[7:0]]) $stop; cycdone[cyc[7:0]] <= '1; if (cyc==0) begin // Setup save128 <= 128'hc77bb9b3784ea0914afe43fb79d7b71e; save48 <= 48'h4afe43fb79d7; save2 <= 2'b10; vec[1][1] <= 32'h0101; vec[1][2] <= 32'h0102; vec[2][1] <= 32'h0201; vec[2][2] <= 32'h0202; pvec[1][1] <= 32'h10101; pvec[1][2] <= 32'h10102; pvec[2][1] <= 32'h10201; pvec[2][2] <= 32'h10202; r <= 1.234; s <= "hello"; // Blocking to avoid delayed to dynamic var sarr[1] = "sarr[1]"; sarr[2] = "sarr[2]"; assoc["mapped"] = "Is mapped"; end if (cyc==1) begin if ($test$plusargs("save_restore") != 0) begin // Don't allow the restored model to run from time 0, it must run from a restore $write("%%Error: didn't really restore\n"); $stop; end end else if (cyc==99) begin if (save128 !== 128'hc77bb9b3784ea0914afe43fb79d7b71e) $stop; if (save48 !== 48'h4afe43fb79d7) $stop; if (save2 !== 2'b10) $stop; if (cycdone !== {{(256-99){1'b0}}, {99{1'b1}}}) $stop; if (vec[1][1] !== 32'h0101) $stop; if (vec[1][2] !== 32'h0102) $stop; if (vec[2][1] !== 32'h0201) $stop; if (vec[2][2] !== 32'h0202) $stop; if (pvec[1][1] !== 32'h10101) $stop; if (pvec[1][2] !== 32'h10102) $stop; if (pvec[2][1] !== 32'h10201) $stop; if (pvec[2][2] !== 32'h10202) $stop; if (r != 1.234) $stop; $display("%s",s); $display("%s",sarr[1]); $display("%s",sarr[2]); if (assoc["mapped"] != "Is mapped") $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_func_ref.v0000644000542200017500000000256415101701376021376 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); class MyInt; int x; function new(int a); x = a; endfunction endclass function int get_val_set_5(ref int x); automatic int y = x; x = 5; return y; endfunction module t; int b; int arr[1]; MyInt mi; task update_inout(inout int flag, input bit upflag); flag = upflag ? 1 + flag : flag; endtask task update_ref(ref int flag, input bit upflag); flag = upflag ? 1 + flag : flag; endtask int my_flag; initial begin mi = new(1); b = get_val_set_5(mi.x); `checkh(mi.x, 5); `checkh(b, 1); arr[0] = 10; b = get_val_set_5(arr[0]); `checkh(arr[0], 5); `checkh(b, 10); update_ref(my_flag, 1); if (my_flag !== 1) $stop; update_ref(my_flag, 0); if (my_flag !== 1) $stop; update_inout(my_flag, 1); if (my_flag !== 2) $stop; update_inout(my_flag, 0); if (my_flag !== 2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_udp_tableend_bad.v0000644000542200017500000000050715101701376023036 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 primitive udp_x (a_bad, b, c_bad); tri a_bad; output b; output c_bad; endtable // BAD endprimitive verilator-5.042/test_regress/t/t_param_package.py0000755000542200017500000000073415101701376022545 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_order_comboloop.py0000755000542200017500000000077115101701376023157 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["-fno-dfg"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_opt_table_signed.v0000644000542200017500000000137315101701376023106 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; int i; reg [2:0] cyc; initial cyc = 0; always @(posedge clk) cyc <= cyc + 1; always @* begin case (cyc) 3'b000: i = 0; 3'b001: i = -1; 3'b010: i = 2; 3'b100: i = -4; 3'b101: i = 5; default: i = -1 << 31; endcase end always @(posedge clk) begin $display("cyle %d = %d", cyc, i); if (cyc == 7) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_func_virt_new_bad.v0000644000542200017500000000061615101701376023261 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class cl #(type T= int); function void f(); T obj = new; endfunction endclass virtual class vcl; endclass; module t; cl #(vcl) c = new; initial begin c.f(); end endmodule verilator-5.042/test_regress/t/t_lint_always_comb_multidriven_compile_public_flat_bad.py0000755000542200017500000000116715101701376032625 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_lint_always_comb_multidriven_bad.v" test.lint(verilator_flags2=['--public-flat-rw --lint-only'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_sampled_expr.py0000755000542200017500000000077115101701376022456 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--assert']) test.execute() test.passes() verilator-5.042/test_regress/t/t_vams_basic.v0000644000542200017500000000323215101701376021707 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `begin_keywords "VAMS-2.3" module t; task check (integer line, real got, real expec); real delta; delta = got-expec; if (delta > 0.001 || delta < -0.001) begin $write("Line%0d: Got %g Exp %g\n", line, got, expec); $stop; end endtask wreal wr; assign wr = 1.1; sub sub (.*); initial begin check(`__LINE__, asin(0.5) , 0.523599); check(`__LINE__, asinh(0.5) , 0.481212); check(`__LINE__, atan(0.5) , 0.463648); check(`__LINE__, atan2(0.5, 0.3) , 1.03038); check(`__LINE__, atanh(0.5) , 0.549306); check(`__LINE__, ceil(2.5) , 3.0); check(`__LINE__, cos(0.5) , 0.877583); check(`__LINE__, cosh(0.5) , 1.12763); check(`__LINE__, exp(2.0) , 7.38906); check(`__LINE__, floor(2.5) , 2.0); check(`__LINE__, ln(2.0) , 0.693147); check(`__LINE__, log(2.0) , 0.30103); check(`__LINE__, pow(2.0,2.0) , 4.0); check(`__LINE__, sin(0.5) , 0.479426); check(`__LINE__, sinh(0.5) , 0.521095); check(`__LINE__, sqrt(2.0) , 1.414); check(`__LINE__, tan(0.5) , 0.546302); check(`__LINE__, tanh(0.5) , 0.462117); $write("*-* All Finished *-*\n"); $finish; end endmodule module sub ( input wreal wr ); initial begin if (wr != 1.1) $stop; end endmodule verilator-5.042/test_regress/t/t_opt_slice_no.py0000755000542200017500000000116615101701376022447 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = 't/t_opt_slice.v' test.compile(verilator_flags2=['--sc', '--stats', '-fno-slice']) test.file_grep(test.stats, r'Optimizations, Slice array assignments\s+(\d+)', 2) test.passes() verilator-5.042/test_regress/t/t_lint_width_cast.py0000755000542200017500000000073415101701376023151 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_static_in_loop_unsup.py0000755000542200017500000000076315101701376024234 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_always_comb_automatic.v0000644000542200017500000000070515101701376025176 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( input logic a, input logic [7:0] b, output logic [7:0] c ); always_comb begin : p c = b; if (a) begin : x automatic logic [7:0] n; n = b; n += 8'h01; c = n; end end endmodule verilator-5.042/test_regress/t/t_trace_fst_cmake.v0000644000542200017500000000447415101701376022723 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // Author: Yu-Sheng Lin johnjohnlys@media.ee.ntu.edu.tw // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs state, // Inputs clk ); input clk; int cyc; reg rstn; output [4:0] state; parameter real fst_gparam_real = 1.23; localparam real fst_lparam_real = 4.56; real fst_real = 1.23; integer fst_integer; bit fst_bit; logic fst_logic; int fst_int; shortint fst_shortint; longint fst_longint; byte fst_byte; parameter fst_parameter = 123; localparam fst_lparam = 456; supply0 fst_supply0; supply1 fst_supply1; tri0 fst_tri0; tri1 fst_tri1; tri fst_tri; wire fst_wire; Test test (/*AUTOINST*/ // Outputs .state (state[4:0]), // Inputs .clk (clk), .rstn (rstn)); // Test loop always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==0) begin // Setup rstn <= ~'1; end else if (cyc<10) begin rstn <= ~'1; end else if (cyc<90) begin rstn <= ~'0; end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test ( input clk, input rstn, output logic [4:0] state ); logic [4:0] state_w; logic [4:0] state_array [3]; assign state = state_array[0]; always_comb begin state_w[4] = state_array[2][0]; state_w[3] = state_array[2][4]; state_w[2] = state_array[2][3] ^ state_array[2][0]; state_w[1] = state_array[2][2]; state_w[0] = state_array[2][1]; end always_ff @(posedge clk or negedge rstn) begin if (!rstn) begin for (int i = 0; i < 3; i++) state_array[i] <= 'b1; end else begin for (int i = 0; i < 2; i++) state_array[i] <= state_array[i+1]; state_array[2] <= state_w; end end endmodule verilator-5.042/test_regress/t/t_trace_cat_fst__0000.out0000644000542200017500000000542615101701376023550 0ustar mahmoudyfreeshell$date Wed Feb 23 00:00:47 2022 $end $version fstWriter $end $timescale 1ps $end $scope module top $end $var wire 1 ! clk $end $scope module t $end $var wire 1 ! clk $end $var integer 32 " cyc [31:0] $end $var integer 32 # unchanged [31:0] $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b00000000000000000000000000101010 # b00000000000000000000000000000000 " 1! $end #1 0! #2 1! b00000000000000000000000000000001 " #3 0! #4 1! b00000000000000000000000000000010 " #5 0! #6 1! b00000000000000000000000000000011 " #7 0! #8 1! b00000000000000000000000000000100 " #9 0! #10 1! b00000000000000000000000000000101 " #11 0! #12 1! b00000000000000000000000000000110 " #13 0! #14 1! b00000000000000000000000000000111 " #15 0! #16 1! b00000000000000000000000000001000 " #17 0! #18 1! b00000000000000000000000000001001 " #19 0! #20 1! b00000000000000000000000000001010 " #21 0! #22 1! b00000000000000000000000000001011 " #23 0! #24 1! b00000000000000000000000000001100 " #25 0! #26 1! b00000000000000000000000000001101 " #27 0! #28 1! b00000000000000000000000000001110 " #29 0! #30 1! b00000000000000000000000000001111 " #31 0! #32 1! b00000000000000000000000000010000 " #33 0! #34 1! b00000000000000000000000000010001 " #35 0! #36 1! b00000000000000000000000000010010 " #37 0! #38 1! b00000000000000000000000000010011 " #39 0! #40 1! b00000000000000000000000000010100 " #41 0! #42 1! b00000000000000000000000000010101 " #43 0! #44 1! b00000000000000000000000000010110 " #45 0! #46 1! b00000000000000000000000000010111 " #47 0! #48 1! b00000000000000000000000000011000 " #49 0! #50 1! b00000000000000000000000000011001 " #51 0! #52 1! b00000000000000000000000000011010 " #53 0! #54 1! b00000000000000000000000000011011 " #55 0! #56 1! b00000000000000000000000000011100 " #57 0! #58 1! b00000000000000000000000000011101 " #59 0! #60 1! b00000000000000000000000000011110 " #61 0! #62 1! b00000000000000000000000000011111 " #63 0! #64 1! b00000000000000000000000000100000 " #65 0! #66 1! b00000000000000000000000000100001 " #67 0! #68 1! b00000000000000000000000000100010 " #69 0! #70 1! b00000000000000000000000000100011 " #71 0! #72 1! b00000000000000000000000000100100 " #73 0! #74 1! b00000000000000000000000000100101 " #75 0! #76 1! b00000000000000000000000000100110 " #77 0! #78 1! b00000000000000000000000000100111 " #79 0! #80 1! b00000000000000000000000000101000 " #81 0! #82 1! b00000000000000000000000000101001 " #83 0! #84 1! b00000000000000000000000000101010 " #85 0! #86 1! b00000000000000000000000000101011 " #87 0! #88 1! b00000000000000000000000000101100 " #89 0! #90 1! b00000000000000000000000000101101 " #91 0! #92 1! b00000000000000000000000000101110 " #93 0! #94 1! b00000000000000000000000000101111 " #95 0! #96 1! b00000000000000000000000000110000 " #97 0! #98 1! b00000000000000000000000000110001 " #99 0! verilator-5.042/test_regress/t/t_flag_werror_bad2.out0000644000542200017500000000061415101701376023344 0ustar mahmoudyfreeshell%Error-WIDTHTRUNC: t/t_flag_werror.v:10:19: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits. : ... note: In instance 't' 10 | wire [3:0] foo = 6'h2e; | ^ ... For error description see https://verilator.org/warn/WIDTHTRUNC?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_disable_fork_notiming.py0000755000542200017500000000101515101701376024313 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(expect_filename=test.golden_filename, v_flags2=["--no-timing"], fails=True) test.passes() verilator-5.042/test_regress/t/t_inside_dyn.v0000644000542200017500000000113315101701376021723 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; int q[$] = '{1, 2, 3}; bit dyn[] = '{0, 0}; string sq[] = '{"C", "D"}; initial begin if (!(1 inside {q})) $stop; if (4 inside {q}) $stop; if (!(4 inside {q, 4})) $stop; if (!(0 inside {dyn})) $stop; if (1 inside {dyn}) $stop; if (!("C" inside {sq})) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_randomize_complex_typedef.py0000755000542200017500000000104615101701376025226 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_clk_concat6.v0000644000542200017500000000425615101701376021775 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty. // SPDX-License-Identifier: CC0-1.0 module some_module ( input [3:0] i_clks ); logic [ 1 : 0 ] some_state; logic [1:0] some_other_state; logic the_clk; assign the_clk = i_clks[3]; always @(posedge the_clk) begin case (some_state) 2'b11: if (some_other_state == 0) some_state <= 2'b00; default: $display ("This is a display statement"); endcase if (the_clk) some_other_state <= 0; $write("*-* All Finished *-*\n"); $finish; end endmodule `define BROKEN module t1( input [3:0] i_clks, input i_clk0, input i_clk1 ); some_module some_module ( .i_clks (i_clks) ); endmodule module ident( input i_ident, output o_ident ); assign o_ident = i_ident; endmodule module t2( input [2:0] i_clks, input i_clk0, input i_clk1, input i_clk2, input i_data ); logic [3:0] the_clks; logic data_q; logic ident_clk1; always @(posedge i_clk0) begin data_q <= i_data; end ident ident ( .i_ident (i_clk1), .o_ident (ident_clk1) ); t1 t1 ( .i_clks ({ident_clk1, i_clk2, ident_clk1, i_clk0}), .i_clk0 (i_clk0), .i_clk1 (i_clk1) ); endmodule module t( /*AUTOARG*/ // Inputs clk /*verilator clocker*/ /*verilator public_flat*/, input clk0 /*verilator clocker*/, input clk1 /*verilator clocker*/, input clk2 /*verilator clocker*/, input data_in ); input clk; logic [2:0] clks; assign clks = {1'b0, clk1, clk0}; t2 t2 ( .i_clks (clks), .i_clk0 (clk0), .i_clk1 (clk), .i_clk2 (clk2), .i_data (data_in) ); endmodule verilator-5.042/test_regress/t/t_sys_writemem_b.gold4.mem0000644000542200017500000000602015101701376024147 0ustar mahmoudyfreeshell000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 011101110101010101000000000001000011011101100101010000110010000100100111011001010100001100100001000101110110010101000011001000010000011101100101010000110010000110101011110011011110111100010000 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 011101110101010101000000000010100011011101100101010000110010000100100111011001010100001100100001000101110110010101000011001000010000011101100101010000110010000110101011110011011110111100010001 011101110101010101000000000010110011011101100101010000110010000100100111011001010100001100100001000101110110010101000011001000010000011101100101010000110010000110101011110011011110111100010010 011101110101010101000000000011000011011101100101010000110010000100100111011001010100001100100001000101110110010101000011001000010000011101100101010000110010000110101011110011011110111100010011 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 verilator-5.042/test_regress/t/t_x_rand_stability_zeros.py0000755000542200017500000000120715101701376024547 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios("vlt") test.top_filename = "t/t_x_rand_stability.v" test.compile(verilator_flags2=["--x-initial unique", "-DNOT_RAND"]) test.execute(all_run_flags=["+verilator+rand+reset+0"], expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_stream_unpack_wider.py0000755000542200017500000000073415101701376024020 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_var_pins_sc1.py0000755000542200017500000000352615101701376022363 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.pli_filename = "t/t_var_pinsizes.cpp" test.top_filename = "t/t_var_pinsizes.v" test.compile(verilator_flags2=[ "-sc -pins-bv 1 --trace-vcd --exe", test.pli_filename, test.t_dir + "/t_var_pinsizes.vlt" ], make_main=False) def hgrep(re): test.file_grep(os.path.join(test.obj_dir, test.vm_prefix + ".h"), re) hgrep(r'sc_core::sc_in\s>\s+&i1;') hgrep(r'sc_core::sc_in\s>\s+&i8;') hgrep(r'sc_core::sc_in\s>\s+&i16;') hgrep(r'sc_core::sc_in\s>\s+&i32;') hgrep(r'sc_core::sc_in\s>\s+&i64;') hgrep(r'sc_core::sc_in\s>\s+&i65;') hgrep(r'sc_core::sc_in\s>\s+&ibv1;') hgrep(r'sc_core::sc_in\s>\s+&ibv16;') hgrep(r'sc_core::sc_in\s>\s+&ibv1_vlt;') hgrep(r'sc_core::sc_in\s>\s+&ibv16_vlt;') hgrep(r'sc_core::sc_out\s>\s+&o1;') hgrep(r'sc_core::sc_out\s>\s+&o8;') hgrep(r'sc_core::sc_out\s>\s+&o16;') hgrep(r'sc_core::sc_out\s>\s+&o32;') hgrep(r'sc_core::sc_out\s>\s+&o64;') hgrep(r'sc_core::sc_out\s>\s+&o65;') hgrep(r'sc_core::sc_out\s>\s+&obv1;') hgrep(r'sc_core::sc_out\s>\s+&obv16;') hgrep(r'sc_core::sc_out\s>\s+&obv1_vlt;') hgrep(r'sc_core::sc_out\s>\s+&obv16_vlt;') test.execute() test.passes() verilator-5.042/test_regress/t/t_always_ff_never.v0000644000542200017500000000153615101701376022757 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface intf (input wire clk /*verilator public*/ ); endinterface module sub ( input wire clk, input wire dat ); intf the_intf (.clk); logic [63:0] last_transition = 123; always_ff @(edge dat) begin last_transition <= $time; end int cyc = 0; always_ff @(posedge clk) begin cyc <= cyc + 1; if (cyc == 2) begin if (last_transition != 123) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module t (/*AUTOARG*/ // Inputs clk ); input clk; sub the_sub (.clk, .dat ('0)); endmodule verilator-5.042/test_regress/t/t_interface_param_another_bad.v0000644000542200017500000000067215101701376025253 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Johan Bjork. // SPDX-License-Identifier: CC0-1.0 module t (); simple_bus sb_intf (); simple_bus #(.PARAMETER(sb_intf.dummy)) simple (); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule interface simple_bus #( PARAMETER = 0 ); logic dummy; endinterface verilator-5.042/test_regress/t/t_timing_intra_assign.py0000755000542200017500000000103515101701376024015 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_nested_link.py0000755000542200017500000000073415101701376023456 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_param_width.py0000755000542200017500000000073415101701376022271 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_case_itemwidth.py0000755000542200017500000000073415101701376022763 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_preproc_resolve_config.vlt0000644000542200017500000000037115101701376024677 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 `verilator_config lint_off -rule NONSTD verilator-5.042/test_regress/t/t_array_rev.v0000644000542200017500000000232215101701376021571 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2016 by Geoff Barrett. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; // verilator lint_off ASCRANGE logic arrd [0:1] = '{ 1'b1, 1'b0 }; // verilator lint_on ASCRANGE logic y0, y1; logic localbkw [1:0]; arr_rev arr_rev_u ( .arrbkw (arrd), .y0(y0), .y1(y1) ); always @ (posedge clk) begin if (arrd[0] != 1'b1) $stop; if (arrd[1] != 1'b0) $stop; localbkw = arrd; `ifdef TEST_VERBOSE $write("localbkw[0]=%b\n", localbkw[0]); $write("localbkw[1]=%b\n", localbkw[1]); `endif if (localbkw[0] != 1'b0) $stop; if (localbkw[1] != 1'b1) $stop; `ifdef TEST_VERBOSE $write("y0=%b\n", y0); $write("y1=%b\n", y1); `endif if (y0 != 1'b0) $stop; if (y1 != 1'b1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module arr_rev ( input var logic arrbkw [1:0], output var logic y0, output var logic y1 ); always_comb y0 = arrbkw[0]; always_comb y1 = arrbkw[1]; endmodule verilator-5.042/test_regress/t/t_detectarray_2.v0000644000542200017500000000127215101701376022332 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Simple test of unoptflat // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 localparam ID_MSB = 1; module t (/*AUTOARG*/ // Inputs clk ); input clk; typedef struct packed { logic [1:0] id; } context_t; context_t tsb; assign tsb.id = {tsb.id[0], clk}; initial begin tsb.id = 0; end always @(posedge clk or negedge clk) begin `ifdef TEST_VERBOSE $write("tsb.id = %x\n", tsb.id); `endif if (tsb.id[1] != 0) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_randomize_complex_queue.v0000644000542200017500000000256715101701376024535 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class SubClass; rand bit [2:0] field; function new (); field = 0; endfunction endclass class MyClass; SubClass sc_inst2[$]; function new (); SubClass inst = new; sc_inst2 = { inst }; endfunction endclass; class Deep; MyClass sc_inst1; function new (); sc_inst1 = new; endfunction endclass; class WeNeedToGoDeeper; Deep sc_inst; function new (); sc_inst = new; endfunction endclass; module t; initial begin WeNeedToGoDeeper inst = new; MyClass inst2 = new; WeNeedToGoDeeper cl_inst[$] = { inst }; MyClass cl_inst2[$] = { inst2 }; repeat(10) begin if (cl_inst[0].sc_inst.sc_inst1.sc_inst2[0].randomize() with {field inside {1, 2, 3};} == 0) begin $stop; end if (cl_inst[0].sc_inst.sc_inst1.sc_inst2[0].field < 1 || cl_inst[0].sc_inst.sc_inst1.sc_inst2[0].field > 3) begin $stop; end if (cl_inst2[0].sc_inst2[0].randomize() with {field inside {1, 2, 3};} == 0) begin $stop; end if (cl_inst2[0].sc_inst2[0].field < 1 || cl_inst2[0].sc_inst2[0].field > 3) begin $stop; end end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_param_implicit_local_bad.py0000755000542200017500000000076615101701376024751 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_castdyn_run_bad.py0000755000542200017500000000101415101701376023121 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface_generic_modport_function.py0000755000542200017500000000077115101701376027100 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--timing']) test.execute() test.passes() verilator-5.042/test_regress/t/t_class_if_assign.py0000755000542200017500000000073415101701376023121 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_gen_for1.v0000644000542200017500000000352015101701376021300 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; wire b; reg reset; integer cyc = 0; Testit testit (/*AUTOINST*/ // Outputs .b (b), // Inputs .clk (clk), .reset (reset)); always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==0) begin reset <= 1'b0; end else if (cyc<10) begin reset <= 1'b1; end else if (cyc<90) begin reset <= 1'b0; end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module Testit (clk, reset, b); input clk; input reset; output b; wire [0:0] c; wire my_sig; wire [0:0] d; genvar i; generate for(i = 0; i >= 0; i = i-1) begin: fnxtclk1 fnxtclk fnxtclk1 (.u(c[i]), .reset(reset), .clk(clk), .w(d[i]) ); end endgenerate assign b = d[0]; assign c[0] = my_sig; assign my_sig = 1'b1; endmodule module fnxtclk (u, reset, clk, w ); input u; input reset; input clk; output reg w; always @ (posedge clk or posedge reset) begin if (reset == 1'b1) begin w <= 1'b0; end else begin w <= u; end end endmodule verilator-5.042/test_regress/t/t_func_numones.v0000644000542200017500000000221415101701376022276 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; reg [31:0] r32; wire [3:0] w4; wire [4:0] w5; assign w4 = NUMONES_8 ( r32[7:0] ); assign w5 = NUMONES_16( r32[15:0] ); function [3:0] NUMONES_8; input [7:0] i8; reg [7:0] i8; begin NUMONES_8 = 4'b1; end endfunction // NUMONES_8 function [4:0] NUMONES_16; input [15:0] i16; reg [15:0] i16; begin NUMONES_16 = ( NUMONES_8( i16[7:0] ) + NUMONES_8( i16[15:8] )); end endfunction integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin r32 <= 32'h12345678; end if (cyc==2) begin if (w4 !== 1) $stop; if (w5 !== 2) $stop; $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.042/test_regress/t/t_interface_gen9_noinl.py0000755000542200017500000000103715101701376024050 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_gen9.v" test.compile(v_flags2=["-fno-inline"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_assert_future_bad.out0000644000542200017500000000315015101701376023642 0ustar mahmoudyfreeshell%Error: t/t_assert_future_bad.v:18:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4) : ... note: In instance 't' 18 | else $display("Future=%0d", $future_gclk(a)); | ^~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_assert_future_bad.v:21:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4) : ... note: In instance 't' 21 | else $display("Future=%0d", $rising_gclk(a)); | ^~~~~~~~~~~~ %Error: t/t_assert_future_bad.v:24:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4) : ... note: In instance 't' 24 | else $display("Future=%0d", $falling_gclk(a)); | ^~~~~~~~~~~~~ %Error: t/t_assert_future_bad.v:27:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4) : ... note: In instance 't' 27 | else $display("Future=%0d", $steady_gclk(a)); | ^~~~~~~~~~~~ %Error: t/t_assert_future_bad.v:30:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4) : ... note: In instance 't' 30 | else $display("Future=%0d", $changing_gclk(a)); | ^~~~~~~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_preproc_defarg_bad.v0000644000542200017500000000047315101701376023374 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 //See bug289 `define A1(x) `define A2(x,y) `A1 `A1(1,2) `A2 `A2(1) `A2(1,2,3) module t; endmodule verilator-5.042/test_regress/t/t_timing_zerodly_unsup.v0000644000542200017500000000150315101701376024070 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; logic v; int num; initial begin num = 1; #1; if (v) $stop; num = 21; // Zero delay should postpone the execution and resume it after // evaluating combinational logic which would update `v`. However, // currently we can't postpone the resumption in the current timeframe // past the combinatorial logic evaluation as that is intertwined with // NBA evaluation and partitioned for multithreading. This causes `v` // to not have its value updated despite being checked after #0 delay. #0 if (v) $finish; $stop; end always_comb v = (num == 21); endmodule verilator-5.042/test_regress/t/t_dpi_export_bad.py0000755000542200017500000000076315101701376022757 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_timing_unset1.py0000755000542200017500000000112315101701376022551 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_notiming.v" test.compile( # --timing/--no-timing not specified fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_xml_flat_no_inline_mod.out0000644000542200017500000000406115101701376024642 0ustar mahmoudyfreeshell verilator-5.042/test_regress/t/t_var_notfound_bad.py0000755000542200017500000000076615101701376023311 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface_array.py0000755000542200017500000000073415101701376023130 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_width_bad.out0000644000542200017500000000746415101701376023130 0ustar mahmoudyfreeshell%Warning-WIDTHTRUNC: t/t_lint_width_bad.v:17:25: Operator VAR 'XS' expects 4 bits on the Initial value, but Initial value's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits. : ... note: In instance 't' 17 | localparam [3:0] XS = 'hx; | ^~ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Warning-WIDTHEXPAND: t/t_lint_width_bad.v:47:19: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'in' generates 4 bits. : ... note: In instance 't.p4' 47 | wire [4:0] out = in; | ^ ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. %Warning-WIDTHEXPAND: t/t_lint_width_bad.v:21:25: Operator SHIFTL expects 5 bits on the LHS, but LHS's CONST '1'h1' generates 1 bits. : ... note: In instance 't' 21 | wire [4:0] d = (1'b1 << 2) + 5'b1; | ^~ %Warning-WIDTHTRUNC: t/t_lint_width_bad.v:27:32: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS's SHIFTL generates 7 bits. : ... note: In instance 't' 27 | wire [WIDTH-1:0] masked = (({{(WIDTH){1'b0}}, one_bit}) << shifter); | ^ %Warning-WIDTHEXPAND: t/t_lint_width_bad.v:32:37: Operator ADD expects 3 bits on the LHS, but LHS's VARREF 'one' generates 1 bits. : ... note: In instance 't' 32 | wire [2:0] cnt = (one + one + one + one); | ^ %Warning-WIDTHEXPAND: t/t_lint_width_bad.v:32:37: Operator ADD expects 3 bits on the RHS, but RHS's VARREF 'one' generates 1 bits. : ... note: In instance 't' 32 | wire [2:0] cnt = (one + one + one + one); | ^ %Warning-WIDTHEXPAND: t/t_lint_width_bad.v:32:43: Operator ADD expects 3 bits on the RHS, but RHS's VARREF 'one' generates 1 bits. : ... note: In instance 't' 32 | wire [2:0] cnt = (one + one + one + one); | ^ %Warning-WIDTHEXPAND: t/t_lint_width_bad.v:32:49: Operator ADD expects 3 bits on the RHS, but RHS's VARREF 'one' generates 1 bits. : ... note: In instance 't' 32 | wire [2:0] cnt = (one + one + one + one); | ^ %Warning-WIDTHEXPAND: t/t_lint_width_bad.v:37:26: Operator GT expects 41 bits on the LHS, but LHS's VARREF 'a' generates 32 bits. : ... note: In instance 't' 37 | initial for (a = 0; a > THREE; ++a) $display(a); | ^ %Warning-WIDTHEXPAND: t/t_lint_width_bad.v:38:26: Operator GTE expects 41 bits on the LHS, but LHS's VARREF 'a' generates 32 bits. : ... note: In instance 't' 38 | initial for (a = 0; a >= THREE; ++a) $display(a); | ^~ %Warning-WIDTHTRUNC: t/t_lint_width_bad.v:40:12: Logical operator IF expects 1 bit on the If, but If's VARREF 'THREE' generates 41 bits. : ... note: In instance 't' 40 | initial if (THREE) $stop; | ^~ %Error: Exiting due to verilator-5.042/test_regress/t/t_randomize_method_types_unsup.out0000644000542200017500000000271315101701376026153 0ustar mahmoudyfreeshell%Warning-CONSTRAINTIGN: t/t_randomize_method_types_unsup.v:23:17: Unsupported: randomizing this expression, treating as state 23 | dynarr[1].size < 10; | ^~~~ ... For warning description see https://verilator.org/warn/CONSTRAINTIGN?v=latest ... Use "/* verilator lint_off CONSTRAINTIGN */" and lint_on around source to disable this message. %Warning-CONSTRAINTIGN: t/t_randomize_method_types_unsup.v:27:9: Size constraint combined with element constraint may not work correctly : ... note: In instance 't' 27 | q.size < 5; | ^~~~ %Warning-CONSTRAINTIGN: t/t_randomize_method_types_unsup.v:31:10: Global constraints ignored (unsupported) 31 | foo.x < y; | ^ %Error-UNSUPPORTED: t/t_randomize_method_types_unsup.v:15:13: Unsupported: random member variable with the type of the containing class : ... note: In instance 't' 15 | rand Cls cls; | ^~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Warning-CONSTRAINTIGN: t/t_randomize_method_types_unsup.v:43:43: Unsupported: randomizing this expression, treating as state 43 | res = obj.randomize() with { dynarr.size > 2; }; | ^~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_math_arith.v0000644000542200017500000001611215101701376021721 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg _ranit; reg [2:0] xor3; reg [1:0] xor2; reg [0:0] xor1; reg [2:0] ma, mb; reg [9:0] mc; reg [4:0] mr1; reg [30:0] mr2; reg [67:0] sh1; reg [67:0] shq; wire foo, bar; assign {foo,bar} = 2'b1_0; // surefire lint_off STMINI initial _ranit = 0; wire [4:0] cond_check = (( xor2 == 2'b11) ? 5'h1 : (xor2 == 2'b00) ? 5'h2 : (xor2 == 2'b01) ? 5'h3 : 5'h4); wire ctrue = 1'b1 ? cond_check[1] : cond_check[0]; wire cfalse = 1'b0 ? cond_check[1] : cond_check[0]; wire cif = cond_check[2] ? cond_check[1] : cond_check[0]; wire cifn = (!cond_check[2]) ? cond_check[1] : cond_check[0]; wire [4:0] doubleconc = {1'b0, 1'b1, 1'b0, cond_check[0], 1'b1}; wire zero = 1'b0; wire one = 1'b1; wire [5:0] rep6 = {6{one}}; // verilator lint_off WIDTH localparam [3:0] bug764_p11 = 1'bx; // verilator lint_on WIDTH always @ (posedge clk) begin if (!_ranit) begin _ranit <= 1; if (rep6 != 6'b111111) $stop; if (!one) $stop; if (~one) $stop; if (( 1'b0 ? 3'h3 : 1'b0 ? 3'h2 : 1'b1 ? 3'h1 : 3'h0) !== 3'h1) $stop; // verilator lint_off WIDTH if (( 8'h10 + 1'b0 ? 8'he : 8'hf) !== 8'he) $stop; // + is higher than ? // verilator lint_on WIDTH // surefire lint_off SEQASS xor1 = 1'b1; xor2 = 2'b11; xor3 = 3'b111; // verilator lint_off WIDTH if (1'b1 & | (!xor3)) $stop; // verilator lint_on WIDTH if ({1{xor1}} != 1'b1) $stop; if ({4{xor1}} != 4'b1111) $stop; if (!(~xor1) !== ~(!xor1)) $stop; if ((^xor1) !== 1'b1) $stop; if ((^xor2) !== 1'b0) $stop; if ((^xor3) !== 1'b1) $stop; if (~(^xor2) !== 1'b1) $stop; if (~(^xor3) !== 1'b0) $stop; if ((^~xor1) !== 1'b0) $stop; if ((^~xor2) !== 1'b1) $stop; if ((^~xor3) !== 1'b0) $stop; if ((~^xor1) !== 1'b0) $stop; if ((~^xor2) !== 1'b1) $stop; if ((~^xor3) !== 1'b0) $stop; xor1 = 1'b0; xor2 = 2'b10; xor3 = 3'b101; if ((^xor1) !== 1'b0) $stop; if ((^xor2) !== 1'b1) $stop; if ((^xor3) !== 1'b0) $stop; if (~(^xor2) !== 1'b0) $stop; if (~(^xor3) !== 1'b1) $stop; if ((^~xor1) !== 1'b1) $stop; if ((^~xor2) !== 1'b0) $stop; if ((^~xor3) !== 1'b1) $stop; if ((~^xor1) !== 1'b1) $stop; if ((~^xor2) !== 1'b0) $stop; if ((~^xor3) !== 1'b1) $stop; // X propagation if (!1'bx !== 1'bx) $stop; if (~2'bx !== 2'bx) $stop; if (-2'bx !== 2'bx) $stop; if ((2'bxx + 2'b1) !== 2'bxx) $stop; if ((2'bxx - 2'b1) !== 2'bxx) $stop; if ((2'bxx * 2'b1) !== 2'bxx) $stop; if ((2'bxx / 2'b1) !== 2'bxx) $stop; if ((2'bxx % 2'b1) !== 2'bxx) $stop; if ((2'sbxx * 2'sb1) !== 2'bxx) $stop; if ((2'sbxx / 2'sb1) !== 2'bxx) $stop; if ((2'sbxx % 2'sb1) !== 2'bxx) $stop; if ((1'bx & 1'b1) !== 1'bx) $stop; if ((1'bx & 1'b0) !== 1'b0) $stop; if ((1'bx | 1'b0) !== 1'bx) $stop; if ((1'bx | 1'b1) !== 1'b1) $stop; if ((1'bx && 1'b1) !== 1'bx) $stop; if ((1'bx && 1'b0) !== 1'b0) $stop; if ((1'bx || 1'b0) !== 1'bx) $stop; if ((1'bx || 1'b1) !== 1'b1) $stop; if ((2'bxx ^ 2'b1) !== 2'bxx) $stop; if ((2'bxx > 2'b1) !== 1'bx) $stop; if ((2'bxx < 2'b1) !== 1'bx) $stop; if ((2'bxx == 2'b1) !== 1'bx) $stop; if ((2'bxx <= 2'b1) !== 1'bx) $stop; if ((2'bxx >= 2'b1) !== 1'bx) $stop; if ((2'sbxx <= 2'sb1) !== 1'bx) $stop; if ((2'sbxx >= 2'sb1) !== 1'bx) $stop; ma = 3'h3; mb = 3'h4; mc = 10'h5; mr1 = ma * mb; // Lint ASWESB: Assignment width mismatch mr2 = 30'h5 * mc; // Lint ASWESB: Assignment width mismatch if (mr1 !== 5'd12) $stop; if (mr2 !== 31'd25) $stop; // Lint CWECBB: Comparison width mismatch sh1 = 68'hf_def1_9abc_5678_1234; shq = sh1 >> 16; if (shq !== 68'hf_def1_9abc_5678) $stop; shq = sh1 << 16; // Lint ASWESB: Assignment width mismatch if (shq !== 68'h1_9abc_5678_1234_0000) $stop; // surefire lint_on SEQASS // Test display extraction widthing $display("[%0t] %x %x %x(%d)", $time, shq[2:0], shq[2:0]<<2, xor3[2:0], xor3[2:0]); // bug736 //verilator lint_off WIDTH if ((~| 4'b0000) != 4'b0001) $stop; if ((~| 4'b0010) != 4'b0000) $stop; if ((~& 4'b1111) != 4'b0000) $stop; if ((~& 4'b1101) != 4'b0001) $stop; //verilator lint_on WIDTH // bug764 //verilator lint_off WIDTH // X does not sign extend if (bug764_p11 !== 4'b000x) $stop; if (~& bug764_p11 !== 1'b1) $stop; //verilator lint_on WIDTH // However IEEE 1800-2023 5.7.1 says for constants that smaller-sizes do extend if (4'bx !== 4'bxxxx) $stop; if (4'bz !== 4'bzzzz) $stop; if (4'b1 !== 4'b0001) $stop; if ((0 -> 0) != 1'b1) $stop; if ((0 -> 1) != 1'b1) $stop; if ((1 -> 0) != 1'b0) $stop; if ((1 -> 1) != 1'b1) $stop; if ((0 <-> 0) != 1'b1) $stop; if ((0 <-> 1) != 1'b0) $stop; if ((1 <-> 0) != 1'b0) $stop; if ((1 <-> 1) != 1'b1) $stop; // bug2912 // verilator lint_off WIDTH if (2'(~1'b1) != 2'b10) $stop; // verilator lint_on WIDTH $write("*-* All Finished *-*\n"); $finish; end end reg [63:0] m_data_pipe2_r; reg [31:0] m_corr_data_w0, m_corr_data_w1; reg [7:0] m_corr_data_b8; initial begin m_data_pipe2_r = 64'h1234_5678_9abc_def0; {m_corr_data_b8, m_corr_data_w1, m_corr_data_w0} = { m_data_pipe2_r[63:57], 1'b0, //m_corr_data_b8 [7:0] m_data_pipe2_r[56:26], 1'b0, //m_corr_data_w1 [31:0] m_data_pipe2_r[25:11], 1'b0, //m_corr_data_w0 [31:16] m_data_pipe2_r[10:04], 1'b0, //m_corr_data_w0 [15:8] m_data_pipe2_r[03:01], 1'b0, //m_corr_data_w0 [7:4] m_data_pipe2_r[0], 3'b000 //m_corr_data_w0 [3:0] }; if (m_corr_data_w0 != 32'haf36de00) $stop; if (m_corr_data_w1 != 32'h1a2b3c4c) $stop; if (m_corr_data_b8 != 8'h12) $stop; end endmodule verilator-5.042/test_regress/t/t_interface_ar2b.py0000755000542200017500000000071415101701376022636 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.passes() verilator-5.042/test_regress/t/t_flag_make_bad.py0000755000542200017500000000103015101701376022474 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--make bad_one"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_alw_nosplit.v0000644000542200017500000001107015101701376022132 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg [15:0] m_din; // We expect none of these blocks to split. // Blocks that can split should go in t_alw_split.v instead. reg [15:0] b_split_1, b_split_2; always @ (/*AS*/m_din) begin b_split_1 = m_din; b_split_2 = b_split_1; end reg [15:0] c_split_1, c_split_2; always @ (/*AS*/m_din) begin c_split_1 = m_din; c_split_2 = c_split_1; c_split_1 = ~m_din; end always @ (posedge clk) begin $write(" foo %x", m_din); $write(" bar %x\n", m_din); end reg [15:0] e_split_1, e_split_2; always @ (posedge clk) begin e_split_1 = m_din; e_split_2 = e_split_1; end reg [15:0] f_split_1, f_split_2; always @ (posedge clk) begin f_split_2 = f_split_1; f_split_1 = m_din; end function logic[15:0] sideeffect_func(logic [15:0] v); /*verilator no_inline_task */ $display(" sideeffect_func() is called %t", $time); return ~v; endfunction reg [15:0] m_split_1 = 0; reg [15:0] m_split_2 = 0; always @(posedge clk) begin if (sideeffect_func(m_split_1) != 16'b0) begin m_split_1 <= m_din; end else begin m_split_2 <= m_din; end end reg [15:0] z_split_1, z_split_2; always @ (posedge clk) begin z_split_1 <= 0; z_split_1 <= ~m_din; end always @ (posedge clk) begin z_split_2 <= 0; z_split_2 <= z_split_1; end reg [15:0] h_split_1; reg [15:0] h_split_2; reg [15:0] h_foo; always @ (posedge clk) begin // $write(" cyc = %x m_din = %x\n", cyc, m_din); h_foo = m_din; if (cyc > 2) begin // This conditional depends on non-primary-input foo. // Its dependency on foo should not be pruned. As a result, // the dependencies of h_split_1 and h_split_2 on this // conditional will also not be pruned, making them all // weakly connected such that they'll end up in the same graph // and we can't split. if (h_foo == 16'h0) begin h_split_1 <= 16'h0; h_split_2 <= 16'h0; end else begin h_split_1 <= m_din; h_split_2 <= ~m_din; end end else begin h_split_1 <= 16'h0; h_split_2 <= 16'h0; end end // always @ (posedge clk) always @ (posedge clk) begin if (cyc!=0) begin cyc<=cyc+1; end if (cyc==1) begin m_din <= 16'hfeed; end if (cyc==4) begin m_din <= 16'he11e; if (!(b_split_1==16'hfeed && b_split_2==16'hfeed)) $stop; if (!(c_split_1==16'h0112 && c_split_2==16'hfeed)) $stop; if (!(e_split_1==16'hfeed && e_split_2==16'hfeed)) $stop; if (!(f_split_1==16'hfeed && f_split_2==16'hfeed)) $stop; if (!(m_split_1==16'hfeed && m_split_2==16'h0000)) $stop; if (!(z_split_1==16'h0112 && z_split_2==16'h0112)) $stop; end if (cyc==5) begin m_din <= 16'he22e; if (!(b_split_1==16'he11e && b_split_2==16'he11e)) $stop; if (!(c_split_1==16'h1ee1 && c_split_2==16'he11e)) $stop; // Two valid orderings, as we don't know which posedge clk gets evaled first if (!(e_split_1==16'hfeed && e_split_2==16'hfeed) && !(e_split_1==16'he11e && e_split_2==16'he11e)) $stop; if (!(f_split_1==16'hfeed && f_split_2==16'hfeed) && !(f_split_1==16'he11e && f_split_2==16'hfeed)) $stop; if (!(m_split_1==16'hfeed && m_split_2==16'h0000)) $stop; if (!(z_split_1==16'h0112 && z_split_2==16'h0112)) $stop; end if (cyc==6) begin m_din <= 16'he33e; if (!(b_split_1==16'he22e && b_split_2==16'he22e)) $stop; if (!(c_split_1==16'h1dd1 && c_split_2==16'he22e)) $stop; // Two valid orderings, as we don't know which posedge clk gets evaled first if (!(e_split_1==16'he11e && e_split_2==16'he11e) && !(e_split_1==16'he22e && e_split_2==16'he22e)) $stop; if (!(f_split_1==16'he11e && f_split_2==16'hfeed) && !(f_split_1==16'he22e && f_split_2==16'he11e)) $stop; if (!(m_split_1==16'he11e && m_split_2==16'h0000)) $stop; if (!(z_split_1==16'h1ee1 && z_split_2==16'h0112)) $stop; end if (cyc==7) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_lint_setout_bad_noinl.out0000644000542200017500000000055215101701376024522 0ustar mahmoudyfreeshell%Error-PORTSHORT: t/t_lint_setout_bad.v:17:8: Output port is connected to a constant pin, electrical short : ... note: In instance 't' 17 | .cpu_if_timeout(1'b0) | ^~~~~~~~~~~~~~ ... For error description see https://verilator.org/warn/PORTSHORT?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_class_extends.v0000644000542200017500000000246715101701376022450 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef class Cls; class Base0; // No members to check that to_string handles this endclass class Base1 extends Base0; int b1member; typedef int T; endclass class Base2 extends Base1; int b2member; endclass class Cls extends Base2; int imembera; int imemberb; T imemberc; endclass : Cls class uvm_object_wrapper; function int create (); return 0; endfunction endclass class uvm__registry #(type T=int) extends uvm_object_wrapper; // This override must be in the new symbol table, not // under the extend's symbol table function int create (); T obj; return 0; endfunction endclass module t; initial begin Cls c; c = new; c.b1member = 10; c.b2member = 30; c.imembera = 100; c.imemberb = 110; c.imemberc = 120; $display("Display: set = \"%p\"", c); // '{all 4 members} if (c.b1member != 10) $stop; if (c.b2member != 30) $stop; if (c.imembera != 100) $stop; if (c.imemberb != 110) $stop; if (c.imemberc != 120) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_select_bad_range6.v0000644000542200017500000000070215101701376023126 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; logic [11:0] i; logic [30:0] o; assign o = i[31:1]; always @(posedge clk) begin i = 12'h123; end always @(negedge clk) begin $write ("Bad select %x\n", o); end endmodule verilator-5.042/test_regress/t/t_class_wide.py0000755000542200017500000000073415101701376022107 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_math_imm2.v0000644000542200017500000000250015101701376021452 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // // Example module to create problem. // // generate a 64 bit value with bits // [HighMaskSel_Bot : LowMaskSel_Bot ] = 1 // [HighMaskSel_Top+32: LowMaskSel_Top+32] = 1 // all other bits zero. module t_math_imm2 (/*AUTOARG*/ // Outputs LogicImm, LowLogicImm, HighLogicImm, // Inputs LowMaskSel_Top, HighMaskSel_Top, LowMaskSel_Bot, HighMaskSel_Bot ); input [4:0] LowMaskSel_Top, HighMaskSel_Top; input [4:0] LowMaskSel_Bot, HighMaskSel_Bot; output [63:0] LogicImm; output [63:0] LowLogicImm, HighLogicImm; /* verilator lint_off UNSIGNED */ /* verilator lint_off CMPCONST */ genvar i; generate for (i=0;i<64;i=i+1) begin : MaskVal if (i >= 32) begin assign LowLogicImm[i] = (LowMaskSel_Top <= i[4:0]); assign HighLogicImm[i] = (HighMaskSel_Top >= i[4:0]); end else begin assign LowLogicImm[i] = (LowMaskSel_Bot <= i[4:0]); assign HighLogicImm[i] = (HighMaskSel_Bot >= i[4:0]); end end endgenerate assign LogicImm = LowLogicImm & HighLogicImm; endmodule verilator-5.042/test_regress/t/t_event_control.v0000644000542200017500000000072315101701376022463 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; initial begin; @(clk); $write("[%0t] Got\n", $time); @(clk); $write("[%0t] Got\n", $time); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_interface_virtual_unsup.v0000644000542200017500000000125015101701376024536 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface Bus; logic [15:0] data; endinterface module t; Bus intf(); virtual Bus vif = intf; function logic write_data(output logic[15:0] data); data = 'hdead; return 1; endfunction // verilator lint_off INFINITELOOP initial begin if (write_data(vif.data)) $write("dummy op"); while (write_data(vif.data)); do ; while (write_data(vif.data)); for (int i = 0; write_data(vif.data++); i++); end endmodule verilator-5.042/test_regress/t/t_array_method.py0000755000542200017500000000073415101701376022450 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_rnd.py0000755000542200017500000000073415101701376020555 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_flag_lib.py0000755000542200017500000000077215101701376021533 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(v_flags2=['-v', 't/t_flag_libinc.v']) test.execute() test.passes() verilator-5.042/test_regress/t/t_preproc_kwd.py0000755000542200017500000000072615101701376022312 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_iface.py0000755000542200017500000000106515101701376022215 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=['--trace-vcd']) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_std_randomize_bad1.v0000644000542200017500000000112115101701376023324 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by PlanV GmbH. // SPDX-License-Identifier: CC0-1.0 module t_std_randomize_bad1; bit [3:0] a; function int run(); int success; success = std::randomize(a + 1); // ERROR: argument is not a variable return success; endfunction initial begin int ok, x; ok = run(); void'(std::randomize(null)); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_gate_delref.py0000755000542200017500000000071415101701376022231 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.passes() verilator-5.042/test_regress/t/t_lint_mod_paren_bad.v0000644000542200017500000000052215101701376023377 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Should have been: //module t #( module t ( FOO=1 ) ( output bar ); assign bar = FOO; endmodule verilator-5.042/test_regress/t/t_force_tri.v0000644000542200017500000000161315101701376021555 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module t(/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; logic [3:0] bus; // Test loop always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 0) begin bus <= 4'b0101; end else if (cyc == 1) begin force bus = 4'bzz10; end else if (cyc == 2) begin `checkh(bus, 4'bzz10); end // else if (cyc == 99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_lint_latch_5.v0000644000542200017500000000070315101701376022145 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module for issue #2863 // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2021 by Julien Margetts (Originally provided by Thomas Sailer) // SPDX-License-Identifier: Unlicense module test (input logic [1:0] a, input logic e, output logic [1:0] z); always_latch if (e) z[0] = a[0]; always_latch if (e) z[1] = a[1]; endmodule verilator-5.042/test_regress/t/t_class_extern_bad.v0000644000542200017500000000061315101701376023100 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Base1; extern task nodef(); extern task nodef(); // <--- Error: duplicate endclass task Base1::noproto(); // <--- Error: Missing prototype endtask module t; endmodule verilator-5.042/test_regress/t/t_hier_parm_under.v0000644000542200017500000000121215101701376022737 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module sub; /* verilator hier_block */ parametrized #(.ARG(1)) parametrized1(); parametrized #(.ARG(2)) parametrized2(); initial begin if (parametrized1.ARG != 1) $stop; if (parametrized2.ARG != 2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module parametrized #(parameter ARG=0); // This is a parametrized non-hier block under a hier block endmodule module t; sub sub(); endmodule verilator-5.042/test_regress/t/t_notiming.v0000644000542200017500000000153015101701376021423 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; event e; initial begin int x; #1 fork @e; @e; join; @e wait(x == 4) x = #1 8; if (x != 8) $stop; if ($time != 0) $stop; @e if (!e.triggered) $stop; if ($time != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end initial #1 ->e; initial #2 $stop; // timeout mailbox#(int) m = new; semaphore s = new; initial begin int i; m.put(i); m.get(i); m.peek(i); s.get(); end endmodule `ifdef VERILATOR_TIMING `error "VERILATOR_TIMING should not be defined with --no-timing" `endif verilator-5.042/test_regress/t/t_interface_generic_modport_function_bad.py0000755000542200017500000000076615101701376027712 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_driver_random.py0000755000542200017500000000134415101701376022623 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap import time test.scenarios('dist') if 'VERILATOR_TEST_RANDOM_FAILURE' not in os.environ: print("Test is for harness checking only, setenv VERILATOR_TEST_RANDOM_FAILURE=1") test.passes() else: # Randomly fail to test driver.py t = time.time() if t % 2: test.error("random failure " + str(t)) test.passes() verilator-5.042/test_regress/t/t_class_copy_bad.py0000755000542200017500000000076615101701376022744 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_order_timing.py0000755000542200017500000000115215101701376022447 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_order.v" test.main_time_multiplier = 1e-8 / 1e-9 test.compile(timing_loop=True, verilator_flags2=["--timescale 10ns/1ns --timing"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_var_port_json_only.out0000644000542200017500000005431115101701376024074 0ustar mahmoudyfreeshell{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"UNLINKED", "modulesp": [ {"type":"MODULE","name":"mh2","addr":"(E)","loc":"d,18:8,18:11","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"mh2","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"x_inout_wire_integer","addr":"(F)","loc":"d,18:27,18:47","dtypep":"(G)","origName":"x_inout_wire_integer","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INOUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"integer","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ]}, {"type":"MODULE","name":"mh5","addr":"(H)","loc":"d,24:8,24:11","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"mh5","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"x_input_wire_logic","addr":"(I)","loc":"d,24:19,24:37","dtypep":"(J)","origName":"x_input_wire_logic","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ]}, {"type":"MODULE","name":"mh6","addr":"(K)","loc":"d,26:8,26:11","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"mh6","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"x_input_var_logic","addr":"(L)","loc":"d,26:23,26:40","dtypep":"(J)","origName":"x_input_var_logic","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ]}, {"type":"MODULE","name":"mh7","addr":"(M)","loc":"d,28:8,28:11","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"mh7","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"x_input_var_integer","addr":"(N)","loc":"d,28:31,28:50","dtypep":"(G)","origName":"x_input_var_integer","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"integer","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ]}, {"type":"MODULE","name":"mh8","addr":"(O)","loc":"d,30:8,30:11","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"mh8","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"x_output_wire_logic","addr":"(P)","loc":"d,30:20,30:39","dtypep":"(J)","origName":"x_output_wire_logic","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ]}, {"type":"MODULE","name":"mh9","addr":"(Q)","loc":"d,32:8,32:11","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"mh9","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"x_output_var_logic","addr":"(R)","loc":"d,32:24,32:42","dtypep":"(J)","origName":"x_output_var_logic","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ]}, {"type":"MODULE","name":"mh10","addr":"(S)","loc":"d,34:8,34:12","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"mh10","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"x_output_wire_logic_signed_p6","addr":"(T)","loc":"d,34:33,34:62","dtypep":"(U)","origName":"x_output_wire_logic_signed_p6","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ]}, {"type":"MODULE","name":"mh11","addr":"(V)","loc":"d,36:8,36:12","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"mh11","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"x_output_var_integer","addr":"(W)","loc":"d,36:28,36:48","dtypep":"(G)","origName":"x_output_var_integer","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"integer","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ]}, {"type":"MODULE","name":"mh12","addr":"(X)","loc":"d,38:8,38:12","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"mh12","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"x_ref_logic_p6","addr":"(Y)","loc":"d,38:23,38:37","dtypep":"(Z)","origName":"x_ref_logic_p6","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"REF","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ]}, {"type":"MODULE","name":"mh13","addr":"(AB)","loc":"d,40:8,40:12","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"mh13","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"x_ref_var_logic_u6","addr":"(BB)","loc":"d,40:17,40:35","dtypep":"(CB)","origName":"x_ref_var_logic_u6","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"REF","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ]}, {"type":"MODULE","name":"mh17","addr":"(DB)","loc":"d,50:8,50:12","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"mh17","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"x_input_var_integer","addr":"(EB)","loc":"d,50:31,50:50","dtypep":"(G)","origName":"x_input_var_integer","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"integer","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"y_input_wire_logic","addr":"(FB)","loc":"d,50:57,50:75","dtypep":"(J)","origName":"y_input_wire_logic","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ]}, {"type":"MODULE","name":"mh18","addr":"(GB)","loc":"d,52:8,52:12","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"mh18","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"x_output_var_logic","addr":"(HB)","loc":"d,52:24,52:42","dtypep":"(J)","origName":"x_output_var_logic","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"y_input_wire_logic","addr":"(IB)","loc":"d,52:50,52:68","dtypep":"(J)","origName":"y_input_wire_logic","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ]}, {"type":"MODULE","name":"mh19","addr":"(JB)","loc":"d,54:8,54:12","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"mh19","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"x_output_wire_logic_signed_p6","addr":"(KB)","loc":"d,54:33,54:62","dtypep":"(U)","origName":"x_output_wire_logic_signed_p6","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"y_output_var_integer","addr":"(LB)","loc":"d,54:72,54:92","dtypep":"(G)","origName":"y_output_var_integer","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"integer","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ]}, {"type":"MODULE","name":"mh20","addr":"(MB)","loc":"d,56:8,56:12","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"mh20","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"x_ref_var_logic_p6","addr":"(NB)","loc":"d,56:23,56:41","dtypep":"(Z)","origName":"x_ref_var_logic_p6","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"REF","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"y_ref_var_logic_p6","addr":"(OB)","loc":"d,56:43,56:61","dtypep":"(Z)","origName":"y_ref_var_logic_p6","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"REF","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ]}, {"type":"MODULE","name":"mh21","addr":"(PB)","loc":"d,58:8,58:12","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"mh21","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"ref_var_logic_u6","addr":"(QB)","loc":"d,58:17,58:33","dtypep":"(RB)","origName":"ref_var_logic_u6","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"REF","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"y_ref_var_logic","addr":"(SB)","loc":"d,58:41,58:56","dtypep":"(J)","origName":"y_ref_var_logic","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"REF","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ]} ],"filesp": [], "miscsp": [ {"type":"TYPETABLE","name":"","addr":"(C)","loc":"a,0:0,0:0","constraintRefp":"UNLINKED","emptyQueuep":"UNLINKED","queueIndexp":"UNLINKED","streamp":"UNLINKED","voidp":"UNLINKED", "typesp": [ {"type":"UNPACKARRAYDTYPE","name":"","addr":"(RB)","loc":"d,58:34,58:35","dtypep":"(RB)","isCompound":false,"declRange":"[5:0]","generic":false,"refDTypep":"(J)","childDTypep": [], "rangep": [ {"type":"RANGE","name":"","addr":"(TB)","loc":"d,58:34,58:35","ascending":false,"fromBracket":false, "leftp": [ {"type":"CONST","name":"32'sh5","addr":"(UB)","loc":"d,58:35,58:36","dtypep":"(VB)"} ], "rightp": [ {"type":"CONST","name":"32'sh0","addr":"(WB)","loc":"d,58:37,58:38","dtypep":"(VB)"} ]} ]}, {"type":"BASICDTYPE","name":"logic","addr":"(J)","loc":"d,58:41,58:56","dtypep":"(J)","keyword":"logic","generic":true,"rangep": []}, {"type":"UNPACKARRAYDTYPE","name":"","addr":"(CB)","loc":"d,40:36,40:37","dtypep":"(CB)","isCompound":false,"declRange":"[5:0]","generic":false,"refDTypep":"(J)","childDTypep": [], "rangep": [ {"type":"RANGE","name":"","addr":"(XB)","loc":"d,40:36,40:37","ascending":false,"fromBracket":false, "leftp": [ {"type":"CONST","name":"32'sh5","addr":"(YB)","loc":"d,40:37,40:38","dtypep":"(VB)"} ], "rightp": [ {"type":"CONST","name":"32'sh0","addr":"(ZB)","loc":"d,40:39,40:40","dtypep":"(VB)"} ]} ]}, {"type":"BASICDTYPE","name":"logic","addr":"(Z)","loc":"d,38:17,38:18","dtypep":"(Z)","keyword":"logic","range":"5:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(U)","loc":"d,34:27,34:28","dtypep":"(U)","keyword":"logic","range":"5:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"integer","addr":"(G)","loc":"d,18:19,18:26","dtypep":"(G)","keyword":"integer","range":"31:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(VB)","loc":"d,40:37,40:38","dtypep":"(VB)","keyword":"logic","range":"31:0","generic":true,"rangep": []} ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ {"type":"MODULE","name":"@CONST-POOL@","addr":"(AC)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], "stmtsp": [ {"type":"SCOPE","name":"@CONST-POOL@","addr":"(BC)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(AC)","varsp": [],"blocksp": [],"inlinesp": []} ]} ]} ]} verilator-5.042/test_regress/t/t_display_type_bad.py0000755000542200017500000000076315101701376023310 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface_virtual_opt.py0000755000542200017500000000073415101701376024362 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_timing_fork_many.py0000755000542200017500000000077115101701376023327 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_unpacked_array_order.py0000755000542200017500000000073415101701376024155 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_program_anonymous.out0000644000542200017500000000035315101701376023722 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_program_anonymous.v:7:1: Unsupported: Anonymous programs 7 | program; | ^~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_select_runtime_range.py0000755000542200017500000000073415101701376024170 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_modport_dir_bad.py0000755000542200017500000000107615101701376024150 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["--lint-only -Wno-DECLFILENAME"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_flag_only_bad.out0000755000542200017500000000040215101701376022721 0ustar mahmoudyfreeshell%Error: The following cannot be used together: --binary, -E, --dpi-hdr-only, --lint-only, --xml-only, --json-only. Suggest see manual ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_duplicated_gen_blocks_bad.out0000644000542200017500000000155615101701376025263 0ustar mahmoudyfreeshell%Error: t/t_duplicated_gen_blocks_bad.v:11:12: Duplicate declaration of generate block: 'block' : ... note: In instance 't' 11 | begin : block | ^~~~~ t/t_duplicated_gen_blocks_bad.v:9:12: ... Location of original declaration 9 | begin : block | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_duplicated_gen_blocks_bad.v:15:23: Duplicate declaration of generate block: 'block1' : ... note: In instance 't' 15 | if (X > 1) begin : block1 | ^~~~~~ t/t_duplicated_gen_blocks_bad.v:13:23: ... Location of original declaration 13 | if (X > 0) begin : block1 | ^~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_math_strwidth.v0000644000542200017500000000073215101701376022463 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008-2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg [4*8:1] strg; initial begin strg = "CHK"; if (strg != "CHK") $stop; if (strg == "JOE") $stop; $write("String = %s = %x\n", strg, strg); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_hier_block_signed_logic.py0000755000542200017500000000124215101701376024574 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--stats', '--hierarchical']) test.execute() test.file_grep(test.obj_dir + "/Vsub/sub.sv", r'^module\s+(\S+)\s+', "sub") test.file_grep(test.stats, r'HierBlock,\s+Hierarchical blocks\s+(\d+)', 1) test.passes() verilator-5.042/test_regress/t/t_vlcov_rank.py0000755000542200017500000000143515101701376022135 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') test.run(cmd=[ os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--rank", "t/t_vlcov_data_a.dat", "t/t_vlcov_data_b.dat", "t/t_vlcov_data_c.dat", "t/t_vlcov_data_d.dat" ], logfile=test.obj_dir + "/vlcov.log", tee=False, verilator_run=True) test.files_identical(test.obj_dir + "/vlcov.log", test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_flag_binary.py0000755000542200017500000000121415101701376022241 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_flag_main.v" test.compile( verilator_flags=[ # Custom as don't want -cc "-Mdir", test.obj_dir, "--debug-check" ], verilator_flags2=['--binary']) test.execute() test.passes() verilator-5.042/test_regress/t/t_mem_multidim.v0000644000542200017500000000630715101701376022270 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; // verilator lint_off ASCRANGE // 3 3 4 reg [71:0] memw [2:0][1:3][5:2]; reg [7:0] memn [2:0][1:3][5:2]; integer cyc; initial cyc = 0; reg [63:0] crc; reg [71:0] wide; reg [7:0] narrow; reg [1:0] index0; reg [1:0] index1; reg [2:0] index2; integer i0,i1,i2; integer imem[2:0][1:3]; reg [2:0] cstyle[2]; // verilator lint_on ASCRANGE initial begin for (i0=0; i0<3; i0=i0+1) begin for (i1=1; i1<4; i1=i1+1) begin imem[i0[1:0]] [i1[1:0]] = i1; for (i2=2; i2<6; i2=i2+1) begin memw[i0[1:0]] [i1[1:0]] [i2[2:0]] = {56'hfe_fee0_fee0_fee0_,4'b0,i0[3:0],i1[3:0],i2[3:0]}; memn[i0[1:0]] [i1[1:0]] [i2[2:0]] = 8'b1000_0001; end end end end reg [71:0] wread; reg wreadb; always @ (posedge clk) begin //$write("cyc==%0d crc=%x i[%d][%d][%d] nar=%x wide=%x\n",cyc, crc, index0,index1,index2, narrow, wide); cyc <= cyc + 1; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; narrow <= 8'h0; wide <= 72'h0; index0 <= 2'b0; index1 <= 2'b0; index2 <= 3'b0; end else if (cyc<90) begin index0 <= crc[1:0]; index1 <= crc[3:2]; index2 <= crc[6:4]; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; // We never read past bounds, or get unspecific results // We also never read lowest indexes, as writing outside of range may corrupt them if (index0>=0+1 && index0<=2 && index1>=1+1 /*&& index1<=3 CMPCONST*/ && index2>=2+1 && index2<=5) begin narrow <= ({narrow[6:0], narrow[7]^narrow[0]} ^ {memn[index0][index1][index2]}); wread = memw[index0][index1][index2]; wreadb = memw[index0][index1][index2][2]; wide <= ({wide[70:0], wide[71]^wide[2]^wide[0]} ^ wread); //$write("Get memw[%d][%d][%d] -> %x\n",index0,index1,index2, wread); end // We may write past bounds of memory memn[index0][index1][index2] [crc[10:8]+:3] <= crc[2:0]; memn[index0][index1][index2] <= {~crc[6:0],crc[7]}; memw[index0][index1][index2] <= {~crc[7:0],crc}; //$write("Set memw[%d][%d][%d] <= %x\n",index0,index1,index2, {~crc[7:0],crc}); cstyle[cyc[0]] <= cyc[2:0]; if (cyc>20) if (cstyle[~cyc[0]] != (cyc[2:0]-3'b1)) $stop; end else if (cyc==90) begin memn[0][1][3] <= memn[0][1][3] ^ 8'ha8; end else if (cyc==91) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x nar=%x wide=%x\n", $time, cyc, crc, narrow, wide); if (crc != 64'h65e3bddcd9bc2750) $stop; if (narrow != 8'hca) $stop; if (wide != 72'h4edafed31ba6873f73) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_clk_first_deprecated.v0000644000542200017500000000046715101701376023747 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk /*verilator sc_clock*/; endmodule verilator-5.042/test_regress/t/t_class_super_bad.v0000644000542200017500000000054315101701376022733 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 Rafal Kapuscik // SPDX-License-Identifier: CC0-1.0 // module t; bit [3:0] addr; initial begin super.addr = 2; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_mod_interface_clocking_bad.out0000644000542200017500000000120715101701376025420 0ustar mahmoudyfreeshell%Error: t/t_mod_interface_clocking_bad.v:16:25: Modport item is not a clocking block: 'reset' 16 | modport mp(input clk, clocking reset, clocking cx); | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_mod_interface_clocking_bad.v:16:41: Modport item not found: 'cx' 16 | modport mp(input clk, clocking reset, clocking cx); | ^~~~~~~~ %Error: t/t_mod_interface_clocking_bad.v:25:10: Can't find definition of 'cb' 25 | x.cb.reset <= 1; | ^~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_trace_array.v0000644000542200017500000000121315101701376022071 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; integer cyc = 0; // Trace would overflow at 256KB which is 256 kb dump, 16 kb in a chunk typedef struct packed { logic [128*1024:0] d; } s1_t; // 128 b s1_t biggie; always @ (posedge clk) begin cyc <= cyc + 1; biggie [ cyc +: 32 ] <= 32'hfeedface; if (cyc == 5) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_flag_debug_noleak.py0000755000542200017500000000113015101701376023371 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(v_flags2=["--debug --no-debug-leak"], verilator_make_gmake=False, make_top_shell=False, make_main=False) test.passes() verilator-5.042/test_regress/t/t_xml_flat.py0000755000542200017500000000142115101701376021572 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_xml_first.v" out_filename = test.obj_dir + "/V" + test.name + ".xml" test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only', '--flatten'], verilator_make_gmake=False, make_top_shell=False, make_main=False) test.files_identical(out_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_unbounded_bad.out0000644000542200017500000000144415101701376022736 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_unbounded_bad.v:9:11: Unsupported/illegal unbounded ('$') in this context. : ... note: In instance 't' 9 | if ($) $stop; | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Warning-WIDTHTRUNC: t/t_unbounded_bad.v:9:7: Logical operator IF expects 1 bit on the If, but If's UNBOUNDED generates 32 bits. : ... note: In instance 't' 9 | if ($) $stop; | ^~ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_lint_iface_topmodule_bad.py0000755000542200017500000000076615101701376024772 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_mailbox_std.py0000755000542200017500000000111015101701376022264 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_mailbox.v" test.compile(verilator_flags2=["--binary -Wall --Wpedantic -DMAILBOX_T=std::mailbox"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_order_dpi_export_7.py0000755000542200017500000000105615101701376023566 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_strength_highz.py0000755000542200017500000000107215101701376023015 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--language 1364-2005"], fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_display_concat2.py0000755000542200017500000000100015101701376023033 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_queue_persistence_inl.py0000755000542200017500000000117515101701376024364 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_queue_persistence.v" if not test.have_coroutines: test.skip("No coroutine support") test.compile(timing_loop=True, verilator_flags2=["--timing"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_array_query_with.v0000644000542200017500000000372315101701376023203 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class Cls; static function bit get_true(); return 1'b1; endfunction static function bit test_find_index_in_class(); if (get_true) begin int q[$] = {0, -1, 3, 1, 4, 1}; int found_idx[$]; found_idx = q.find_index(node) with (node == 1); return found_idx[0] == 3; end return 0; endfunction endclass module t (/*AUTOARG*/ ); function bit test_find; string bar[$]; string found[$]; bar.push_back("baz"); bar.push_back("qux"); found = bar.find(x) with (x == "baz"); return found.size() == 1; endfunction function static bit test_find_index; int q[$] = {1, 2, 3, 4}; int found[$] = q.find_index(x) with (x <= 2); return found.size() == 2; endfunction function static bit test_find_first_index; int q[] = {1, 2, 3, 4, 5, 6}; int first_even_idx[$] = q.find_first_index(x) with (x % 2 == 0); return first_even_idx[0] == 1; endfunction function bit is_even(int a); return a % 2 == 0; endfunction function static bit test_find_first_index_by_func; int q[] = {1, 2, 3, 4, 5, 6}; int first_even_idx[$] = q.find_first_index(x) with (is_even(x)); return first_even_idx[0] == 1; endfunction function automatic bit test_sort; int q[] = {-5, 2, -3, 0, 4}; q.sort(x) with (x >= 0 ? x : -x); return q[1] == 2; endfunction initial begin if (!test_find()) $stop; if (!test_find_index()) $stop; if (!test_find_first_index()) $stop; if (!test_find_first_index_by_func()) $stop; if (!test_sort()) $stop; if (!Cls::test_find_index_in_class()) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_trace_two_dumpfst_cc.out0000644000542200017500000000364715101701376024352 0ustar mahmoudyfreeshell$date Sat Mar 30 14:01:55 2024 $end $version fstWriter $end $timescale 1ps $end $scope module topa $end $var wire 1 ! clk $end $scope module t $end $var wire 1 ! clk $end $var integer 32 " cyc [31:0] $end $var integer 32 # c_trace_on [31:0] $end $scope module sub $end $var integer 32 $ inside_sub_a [31:0] $end $upscope $end $upscope $end $upscope $end $scope module topb $end $var wire 1 % clk $end $scope module t $end $var wire 1 % clk $end $var integer 32 & cyc [31:0] $end $var integer 32 ' c_trace_on [31:0] $end $var real 64 ( r $end $scope module sub $end $var integer 32 ) inside_sub_a [31:0] $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #10 $dumpvars b00000000000000000000000000000010 ) r0 ( b00000000000000000000000000000000 ' b00000000000000000000000000000001 & 1% b00000000000000000000000000000001 $ b00000000000000000000000000000000 # b00000000000000000000000000000001 " 1! $end #15 0! 0% #20 1% 1! b00000000000000000000000000000010 " b00000000000000000000000000000011 # r0.1 ( #25 0! 0% #30 1% 1! r0.2 ( b00000000000000000000000000000100 # b00000000000000000000000000000011 " #35 0! 0% #40 1% 1! b00000000000000000000000000000100 " b00000000000000000000000000000101 # r0.3 ( #45 0! 0% #50 1% 1! r0.4 ( b00000000000000000000000000000110 # b00000000000000000000000000000101 " #55 0! 0% #60 1% 1! b00000000000000000000000000000110 " b00000000000000000000000000000111 # r0.5 ( #65 0! 0% #70 1% 1! r0.6 ( b00000000000000000000000000001000 # b00000000000000000000000000000111 " #75 0! 0% #80 1% 1! b00000000000000000000000000001000 " b00000000000000000000000000001001 # r0.7 ( #85 0! 0% #90 1% 1! r0.7999999999999999 ( b00000000000000000000000000001010 # b00000000000000000000000000001001 " #95 0! 0% #100 1% 1! b00000000000000000000000000001010 " b00000000000000000000000000001011 # r0.8999999999999999 ( #105 0! 0% #110 1% 1! r0.9999999999999999 ( b00000000000000000000000000001100 # b00000000000000000000000000001011 " verilator-5.042/test_regress/t/t_class_new_default.v0000644000542200017500000000101615101701376023260 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class ClsDef; int imembera; function new(default); imembera = i + 1; endfunction endclass class ClsDefFwd; int imembera; extern function new(default); endclass function ClsDefFwd::new(default); endfunction module t; initial begin // TODO real test $stop; end endmodule verilator-5.042/test_regress/t/t_iff.py0000755000542200017500000000073415101701376020536 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_select_lhs_oob.py0000755000542200017500000000073415101701376022756 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_vpi_memory.py0000755000542200017500000000136315101701376022157 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(make_top_shell=False, make_main=False, make_pli=True, iv_flags2=["-g2005-sv -D USE_VPI_NOT_DPI"], v_flags2=["+define+USE_VPI_NOT_DPI"], verilator_flags2=["--exe --vpi --no-l2name", test.pli_filename]) test.execute(use_libvpi=True) test.passes() verilator-5.042/test_regress/t/t_vlcov_merge.py0000755000542200017500000000212515101701376022276 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') test.run(cmd=[ os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--no-unlink", "--nounlink", "--write", test.obj_dir + "/coverage.dat", "t/t_vlcov_data_a.dat", "t/t_vlcov_data_b.dat", "t/t_vlcov_data_c.dat", "t/t_vlcov_data_d.dat", ], verilator_run=True) # Not deleted e.g. parsed --no-unlink properlytest.files_identical(test.t_dir + "/t_vlcov_data_a.dat", test.t_dir + "/t_vlcov_data_a.dat") # Older clib's didn't properly sort maps, but the coverage data doesn't # really care about ordering. So avoid false failures by sorting.test.files_identical_sorted(test.obj_dir + "/coverage.dat", test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_bigmem_bad.v0000644000542200017500000000071315101701376021647 0ustar mahmoudyfreeshell// This test shall generate a warning, but not an internal error. // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Zhanglei Wang. // SPDX-License-Identifier: CC0-1.0 module t_bigmem( input wire clk, input wire [27:0] addr, input wire [255:0] data, input wire wen ); reg [(1<<28)-1:0][255:0] mem; always @(posedge clk) begin if (wen) mem[addr] <= data; end endmodule verilator-5.042/test_regress/t/t_param_bracket.v0000644000542200017500000000065615101701376022402 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by Wilson Snyder; // SPDX-License-Identifier: CC0-1.0 module t #(parameter WIDTH = 8) (/*AUTOARG*/ // Outputs o ); output [WIDTH-1:0] o; localparam DEPTH = $clog2(5); // Note single bracket below reg [WIDTH-1:0] arid [1<= 10) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test1( clk, a, b ); input clk; input [3:0] a, b; always @(posedge clk) begin if (a < 9) $strobe("%0d == %0d, %0d == %0d", a, b, $past(a), $past(b)); end endmodule verilator-5.042/test_regress/t/t_vlcov_unlink.py0000755000542200017500000000156115101701376022502 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap import shutil test.scenarios('dist') tmp = test.obj_dir + "/copied.dat" shutil.copy(test.t_dir + "/t_vlcov_data_a.dat", tmp) test.run(cmd=[ os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--unlink", tmp, "--write", test.obj_dir + "/output.dat" ], verilator_run=True) test.files_identical(test.obj_dir + "/output.dat", "t/t_vlcov_data_a.dat") # --unlink should have removed it if os.path.exists(tmp): test.error("Wan't unlinked") test.passes() verilator-5.042/test_regress/t/t_dpi_imp_gen.v0000644000542200017500000000151015101701376022047 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; parameter integer BLKS = 3; generate for (genvar blkIdx=0; blkIdx < BLKS; blkIdx=blkIdx+1 ) begin : slice import "DPI-C" context function void dpi_genvarTest (); initial begin dpi_genvarTest(); $display("slice = %0d : %m", blkIdx); end end endgenerate always @ (posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_setuphold.py0000755000542200017500000000073415101701376022001 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_udp_bad_line_outputs.out0000644000542200017500000000104015101701376024345 0ustar mahmoudyfreeshell%Error: t/t_udp_bad_line_outputs.v:9:11: syntax error, unexpected UDP table field, expecting : or UDP table line end 9 | ? : 0 0 : 0; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_udp_bad_line_outputs.v:15:15: syntax error, unexpected UDP table field, expecting UDP table line end 15 | ? : 0 : 0 0; | ^ %Error: Cannot continue ... This fatal error may be caused by the earlier error(s); resolve those first. verilator-5.042/test_regress/t/t_param_slice.v0000644000542200017500000000542215101701376022062 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `timescale 1ns/1ps // Test constant parameter slicing of unpacked arrays with various slice ranges. module issue_desc #( parameter int els_p = 1, parameter int val_p [els_p+1:2], parameter int orig_els = 1 ) (); // Drop the lowest index (2) in each recursion: slice [high:3] if (els_p > 1) begin : r issue_desc #( .els_p(els_p-1), .val_p(val_p[els_p+1:3]), .orig_els(orig_els) ) x(); end initial begin int expected = orig_els - els_p + 1; if (val_p[2] !== expected) begin $error("DESC wrong value %0d expected %0d in %m", val_p[2], expected); $finish; end $display("%08x (desc %m)", val_p[2]); end endmodule module issue_rev #( parameter int els_p = 1, parameter int val_p [2:els_p+1], parameter int orig_els = 1 ) (); // Drop the lowest index (2) in each recursion: slice [3:high] if (els_p > 1) begin : r issue_rev #( .els_p(els_p-1), .val_p(val_p[3:els_p+1]), .orig_els(orig_els) ) x(); end initial begin int expected = orig_els - els_p + 1; if (val_p[2] !== expected) begin $error("REV wrong value %0d expected %0d in %m", val_p[2], expected); $finish; end $display("%08x (rev %m)", val_p[2]); end endmodule module issue_def #( parameter int els_p = 1, // Internal default fill is zero; the test overrides this with DEADBEEF. parameter int val_p [els_p+1:2] = '{default:0}, parameter int orig_els = 1 ) (); // Recursively slice off the lowest index (2) if (els_p > 1) begin : r issue_def #( .els_p(els_p-1), .val_p(val_p[els_p+1:3]), .orig_els(orig_els) ) x(); end initial begin // Expect 32'hDEADBEEF when overridden by the top-level test. if (val_p[2] !== 32'hDEADBEEF) begin $error("DEF wrong value %0x expected DEADBEEF in %m", val_p[2]); $finish; end $display("%08x (def %m)", val_p[2]); end endmodule module t; // For els_p=5, the range [els_p+1:2] is [6:2]. // Descending initializer: index 6=5,5=4,4=3,3=2,2=1. parameter int val_desc [6:2] = '{5,4,3,2,1}; // Reverse slice initializer: ascending values on [2:6]. parameter int val_rev [2:6] = '{1,2,3,4,5}; // Override for default-array test: all elements set to 32'hDEADBEEF on [6:2]. parameter int val_def [6:2] = '{default: 32'hDEADBEEF}; issue_desc #(.els_p(5), .val_p(val_desc), .orig_els(5)) iss_desc(); issue_rev #(.els_p(5), .val_p(val_rev), .orig_els(5)) iss_rev(); issue_def #(.els_p(5), .val_p(val_def), .orig_els(5)) iss_def(); initial begin #1; $write("*-* All Finished *-*\\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_timing_dlyassign.v0000644000542200017500000000137015101701376023145 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 // bug3781 module t; logic clk; logic [7:0] data; logic [3:0] ptr; logic [7:0] mem[16]; initial begin clk = 1'b0; fork forever #5 clk = ~clk; join_none ptr = '0; #10 data = 1; #10 if (mem[ptr] != data) $stop; #10 data = 2; #10 if (mem[ptr] != data) $stop; #10 data = 3; #10 if (mem[ptr] != data) $stop; #10 $write("*-* All Finished *-*\n"); $finish; end always @(posedge clk) begin mem[ptr] <= #1 data; end endmodule verilator-5.042/test_regress/t/t_class_param_extends3.v0000644000542200017500000000320515101701376023702 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package u_pkg; typedef class u_report_object; typedef class u_callback; virtual class u_object; endclass class u_queue #(type T=int) extends u_object; int m_value = 6; endclass class u_callbacks_base extends u_object; typedef u_callbacks_base this_type; endclass class u_typed_callbacks#(type T=u_object) extends u_callbacks_base; typedef u_typed_callbacks#(T) this_type; static this_type m_t_inst; static u_queue#(u_callback) m_tw_cb_q; endclass class u_callbacks #(type T=u_object, type CB=u_callback) extends u_typed_callbacks#(T); static function bit m_register_pair(); return 1'b0; endfunction static function void add(u_callback cb); u_queue#(u_callback) qr; qr = u_callbacks#(u_report_object,u_callback)::m_t_inst.m_tw_cb_q; //<<<< if (qr.m_value != 6) $stop; endfunction endclass class u_callback extends u_object; endclass virtual class u_report_catcher extends u_callback; static local bit m_register_cb_u_report_catcher = u_callbacks#(u_report_object,u_report_catcher)::m_register_pair(); endclass // Having this class (versus using #(u_object) is needed to hit the bug class u_report_object extends u_object; endclass endpackage module t; u_pkg::u_callback cb; initial begin cb = new; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_inst_mnpipe.v0000644000542200017500000000307115101701376022126 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc = 0; reg [7:0] crc; reg [2:0] sum; wire [2:0] in = crc[2:0]; wire [2:0] out; MxN_pipeline pipe (in, out, clk); always @ (posedge clk) begin //$write("[%0t] cyc==%0d crc=%b sum=%x\n", $time, cyc, crc, sum); cyc <= cyc + 1; crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; if (cyc==0) begin // Setup crc <= 8'hed; sum <= 3'h0; end else if (cyc>10 && cyc<90) begin sum <= {sum[1:0],sum[2]} ^ out; end else if (cyc==99) begin if (crc !== 8'b01110000) $stop; if (sum !== 3'h3) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module dffn (q,d,clk); parameter BITS = 1; input [BITS-1:0] d; output reg [BITS-1:0] q; input clk; always @ (posedge clk) begin q <= d; end endmodule module MxN_pipeline (in, out, clk); parameter M=3, N=4; input [M-1:0] in; output [M-1:0] out; input clk; // Unsupported: Per-bit array instantiations with output connections to non-wires. //wire [M*(N-1):1] t; //dffn #(M) p[N:1] ({out,t},{t,in},clk); wire [M*(N-1):1] w; wire [M*N:1] q; dffn #(M) p[N:1] (q,{w,in},clk); assign {out,w} = q; endmodule verilator-5.042/test_regress/t/t_sys_writemem.gold3.mem0000644000542200017500000000132015101701376023643 0ustar mahmoudyfreeshell00000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000 400437654321276543211765432107654321abcdef10 00000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000 400a37654321276543211765432107654321abcdef11 400b37654321276543211765432107654321abcdef12 400c37654321276543211765432107654321abcdef13 00000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000 verilator-5.042/test_regress/t/t_var_dotted1.v0000644000542200017500000001331115101701376022013 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); // verilator lint_off MULTIDRIVEN wire [31:0] outb0c0; wire [31:0] outb0c1; wire [31:0] outb1c0; wire [31:0] outb1c1; reg [7:0] lclmem [7:0]; ma ma0 (.outb0c0(outb0c0), .outb0c1(outb0c1), .outb1c0(outb1c0), .outb1c1(outb1c1) ); global_mod #(32'hf00d) global_cell (); global_mod #(32'hf22d) global_cell2 (); input clk; integer cyc=1; always @ (posedge clk) begin cyc <= cyc + 1; `ifdef TEST_VERBOSE $write("[%0t] cyc%0d: %0x %0x %0x %0x\n", $time, cyc, outb0c0, outb0c1, outb1c0, outb1c1); `endif if (cyc==2) begin if (global_cell.globali != 32'hf00d) $stop; if (global_cell2.globali != 32'hf22d) $stop; if ($root.t.global_cell.globali != 32'hf00d) $stop; if ($root.t.global_cell2.globali != 32'hf22d) $stop; if (outb0c0 != 32'h00) $stop; if (outb0c1 != 32'h01) $stop; if (outb1c0 != 32'h10) $stop; if (outb1c1 != 32'h11) $stop; end if (cyc==3) begin // Can we scope down and read and write vars? ma0.mb0.mc0.out <= ma0.mb0.mc0.out + 32'h100; ma0.mb0.mc1.out <= ma0.mb0.mc1.out + 32'h100; ma0.mb1.mc0.out <= ma0.mb1.mc0.out + 32'h100; ma0.mb1.mc1.out <= ma0.mb1.mc1.out + 32'h100; end if (cyc==4) begin // Can we do dotted's inside array sels? ma0.rmtmem[ma0.mb0.mc0.out[2:0]] = 8'h12; lclmem[ma0.mb0.mc0.out[2:0]] = 8'h24; if (outb0c0 != 32'h100) $stop; if (outb0c1 != 32'h101) $stop; if (outb1c0 != 32'h110) $stop; if (outb1c1 != 32'h111) $stop; end if (cyc==5) begin if (ma0.rmtmem[ma0.mb0.mc0.out[2:0]] != 8'h12) $stop; if (lclmem[ma0.mb0.mc0.out[2:0]] != 8'h24) $stop; if (outb0c0 != 32'h1100) $stop; if (outb0c1 != 32'h2101) $stop; if (outb1c0 != 32'h2110) $stop; if (outb1c1 != 32'h3111) $stop; end if (cyc==6) begin if (outb0c0 != 32'h31100) $stop; if (outb0c1 != 32'h02101) $stop; if (outb1c0 != 32'h42110) $stop; if (outb1c1 != 32'h03111) $stop; end if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule `ifdef USE_INLINE_MID `define INLINE_MODULE /*verilator inline_module*/ `define INLINE_MID_MODULE /*verilator no_inline_module*/ `else `ifdef USE_INLINE `define INLINE_MODULE /*verilator inline_module*/ `define INLINE_MID_MODULE /*verilator inline_module*/ `else `define INLINE_MODULE /*verilator public_module*/ `define INLINE_MID_MODULE /*verilator public_module*/ `endif `endif module global_mod; `INLINE_MODULE parameter INITVAL = 0; integer globali; initial globali = INITVAL; endmodule module ma ( output wire [31:0] outb0c0, output wire [31:0] outb0c1, output wire [31:0] outb1c0, output wire [31:0] outb1c1 ); `INLINE_MODULE reg [7:0] rmtmem [7:0]; mb #(0) mb0 (.outc0(outb0c0), .outc1(outb0c1)); mb #(1) mb1 (.outc0(outb1c0), .outc1(outb1c1)); endmodule module mb ( output wire [31:0] outc0, output wire [31:0] outc1 ); `INLINE_MID_MODULE parameter P2 = 0; mc #(P2,0) mc0 (.out(outc0)); mc #(P2,1) mc1 (.out(outc1)); global_mod #(32'hf33d) global_cell2 (); wire reach_up_clk = t.clk; always @(reach_up_clk) begin if (P2==0) begin // Only for mb0 if (outc0 !== t.ma0.mb0.mc0.out) $stop; // Top module name and lower instances if (outc0 !== ma0.mb0.mc0.out) $stop; // Upper module name and lower instances if (outc0 !== ma .mb0.mc0.out) $stop; // Upper module name and lower instances if (outc0 !== mb.mc0.out) $stop; // This module name and lower instances if (outc0 !== mb0.mc0.out) $stop; // Upper instance name and lower instances if (outc0 !== mc0.out) $stop; // Lower instances if (outc1 !== t.ma0.mb0.mc1.out) $stop; // Top module name and lower instances if (outc1 !== ma0.mb0.mc1.out) $stop; // Upper module name and lower instances if (outc1 !== ma .mb0.mc1.out) $stop; // Upper module name and lower instances if (outc1 !== mb.mc1.out) $stop; // This module name and lower instances if (outc1 !== mb0.mc1.out) $stop; // Upper instance name and lower instances if (outc1 !== mc1.out) $stop; // Lower instances end end endmodule module mc (output reg [31:0] out); `INLINE_MODULE parameter P2 = 0; parameter P3 = 0; initial begin out = {24'h0,P2[3:0],P3[3:0]}; //$write("%m P2=%0x p3=%0x out=%x\n",P2, P3, out); end // Can we look from the top module name down? wire [31:0] reach_up_cyc = t.cyc; always @ (posedge t.clk) begin //$write("[%0t] %m: Got reachup, cyc=%0d\n", $time, reach_up_cyc); if (reach_up_cyc==2) begin if (global_cell.globali != 32'hf00d) $stop; if (global_cell2.globali != 32'hf33d) $stop; end if (reach_up_cyc==4) begin out[15:12] <= {P2[3:0]+P3[3:0]+4'd1}; end if (reach_up_cyc==5) begin // Can we set another instance? if (P3==1) begin // Without this, there are two possible correct answers... mc0.out[19:16] <= {mc0.out[19:16]+P2[3:0]+P3[3:0]+4'd2}; $display("%m Set %x->%x %x %x %x %x",mc0.out, {mc0.out[19:16]+P2[3:0]+P3[3:0]+4'd2}, mc0.out[19:16],P2[3:0],P3[3:0],4'd2); end end end endmodule verilator-5.042/test_regress/t/t_timing_intra_assign.v0000644000542200017500000000270215101701376023631 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; logic[3:0] val[3]; wire[3:0] #5 net[2]; logic[1:0] idx1 = 0; logic[1:0] idx2 = 0; logic[0:0] idx3 = 0; event e; always @val $write("[%0t] val[0]=%0d val[1]=%0d val[2]=%0d net[0]=%0d net[1]=%0d\n", $time, val[0], val[1], val[2], net[0], net[1]); assign {net[0], net[1]} = {val[1], 4'hf-val[1]}; assign #4 val[1] = val[0]; assign #6 val[2] = val[0]; always #10 begin // always so we can use NBA val[0] = 1; #10 val[0] = 2; fork #5 val[0] = 3; join_none val[0] = #10 val[0] + 2; val[0] <= #10 val[idx1] + 2; fork begin #5 val[0] = 5; idx1 = 0; idx2 = 0; idx3 = 0; #40 ->e; end join_none idx1 = 2; idx2 = 3; idx3 = 1; val[idx1][idx2[idx3+:2]] = #20 1; @e val[0] = 8; fork begin #1 val[0] = 9; #2 ->e; end join_none val[0] = @e val[0] + 2; val[0] <= @e val[0] + 2; fork begin #1 val[0] = 11; end join_none #2 ->e; idx1 = 0; idx2 = 0; idx3 = 0; fork begin #2 idx1 = 2; idx2 = 3; idx3 = 1; end join_none #1 val[idx1[idx3+:2]][idx2] <= @e 1; #1 ->e; #1 $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_math_mul.v0000644000542200017500000000314215101701376021406 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc = 0; reg [63:0] crc; reg [63:0] sum; wire [31:0] out1; wire [31:0] out2; sub sub (.in1(crc[15:0]), .in2(crc[31:16]), .out1(out1), .out2); always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x sum=%x out=%x %x\n", $time, cyc, crc, sum, out1, out2); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {out2,out1}; if (cyc==1) begin // Setup crc <= 64'h00000000_00000097; sum <= 64'h0; end else if (cyc==90) begin if (sum !== 64'he396068aba3898a2) $stop; end else if (cyc==91) begin end else if (cyc==92) begin end else if (cyc==93) begin end else if (cyc==94) begin end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module sub (/*AUTOARG*/ // Outputs out1, out2, // Inputs in1, in2 ); input [15:0] in1; input [15:0] in2; output reg signed [31:0] out1; output reg unsigned [31:0] out2; always @* begin // verilator lint_off WIDTH out1 = $signed(in1) * $signed(in2); out2 = $unsigned(in1) * $unsigned(in2); // verilator lint_on WIDTH end endmodule verilator-5.042/test_regress/t/t_order_dpi_export_4.py0000755000542200017500000000105615101701376023563 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_sys_strobe.py0000755000542200017500000000100015101701376022151 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_config_work.v0000644000542200017500000000045715101701376022115 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; m1 u_1(); m2 u_2(); final $write("*-* All Finished *-*\n"); endmodule verilator-5.042/test_regress/t/t_semaphore_class_nested.v0000644000542200017500000000203515101701376024312 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class semaphore_cls; class InnerKeyClass; int innerKeys; function new(int keyCount = 0); innerKeys = keyCount; endfunction endclass // Test an implementation similar to what Verilator will do internally InnerKeyClass m_keys; function new(int keyCount = 0); m_keys = new(keyCount); endfunction function void put(int keyCount = 1); m_keys.innerKeys += keyCount; endfunction task get(int keyCount = 1); wait (m_keys.innerKeys >= keyCount); m_keys.innerKeys -= keyCount; endtask function int try_get(int keyCount = 1); if (m_keys.innerKeys >= keyCount) begin m_keys.innerKeys -= keyCount; return 1; end else begin return 0; end endfunction endclass `define SEMAPHORE_T semaphore_cls `include "t_semaphore.v" verilator-5.042/test_regress/t/t_savable_format2_bad.py0000755000542200017500000000170715101701376023650 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_savable.v" test.compile(v_flags2=["--savable"], save_time=500) test.execute(check_finished=False, all_run_flags=['+save_time=500']) if not os.path.exists(test.obj_dir + "/saved.vltsv"): test.error("Saved.vltsv not created") # Break the header test.file_sed(test.obj_dir + "/saved.vltsv", test.obj_dir + "/saved.vltsv", lambda line: re.sub(r'verilatorsave', 'verilatorsavBAD', line)) test.execute(all_run_flags=['+save_restore=1'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_genfor_signed.out0000644000542200017500000000054315101701376022755 0ustar mahmoudyfreeshelltop.t.u_sub1.unnamedblk1 1..1 i=1 top.t.u_sub0.unnamedblk1 1..0 i=1 top.t.u_sub0.unnamedblk1 1..0 i=0 top.t.SUB_PIPE[-1].u_sub.unnamedblk1 1..-1 i=1 top.t.SUB_PIPE[-1].u_sub.unnamedblk1 1..-1 i=0 top.t.SUB_PIPE[-1].u_sub.unnamedblk1 1..-1 i=-1 top.t.SUB_PIPE[0].u_sub.unnamedblk1 1..0 i=1 top.t.SUB_PIPE[0].u_sub.unnamedblk1 1..0 i=0 *-* All Finished *-* verilator-5.042/test_regress/t/t_bitsel_lvalue.py0000755000542200017500000000071415101701376022622 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.passes() verilator-5.042/test_regress/t/t_lint_iface_topmodule2.py0000755000542200017500000000070615101701376024240 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.042/test_regress/t/t_enum.v0000644000542200017500000000441515101701376020550 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef enum logic [4:0] { BIT0 = 5'd0, BIT1 = 5'd1, BIT2 = 5'd2 } three_t; module t; localparam FIVE = 5; enum { e0, e1, e3=3, e5=FIVE, e10_[2] = 10, e12, e20_[5:7] = 25, e20_z, e30_[7:5] = 30, e30_z } EN; enum { z5 = e5 } ZN; enum int unsigned { FIVE_INT = 5 } FI; typedef enum three_t; // Forward typedef enum [2:0] { ONES=~0 } three_t; three_t three = ONES; int array5[z5]; int array5i[FIVE_INT]; var logic [ONES:0] sized_based_on_enum; var enum logic [3:0] { QINVALID='1, QSEND={2'b0,2'h0}, QOP={2'b0,2'h1}, QCL={2'b0,2'h2}, QPR={2'b0,2'h3 }, QACK, QRSP } inv; enum logic [7:0] { ENARRAY = 6 } [3:2] enarray; initial begin if (e0 !== 0) $stop; if (e1 !== 1) $stop; if (e3 !== 3) $stop; if (e5 !== 5) $stop; if (e10_0 !== 10) $stop; if (e10_1 !== 11) $stop; if (e12 !== 12) $stop; if (e20_5 !== 25) $stop; if (e20_6 !== 26) $stop; if (e20_7 !== 27) $stop; if (e20_z !== 28) $stop; if (e30_7 !== 30) $stop; if (e30_6 !== 31) $stop; if (e30_5 !== 32) $stop; if (e30_z !== 33) $stop; if (z5 !== 5) $stop; if (three != 3'b111) $stop; if ($bits(sized_based_on_enum) != 8) $stop; if ($bits(three_t) != 3) $stop; if (FIVE[BIT0] != 1'b1) $stop; if (FIVE[BIT1] != 1'b0) $stop; if (FIVE[BIT2] != 1'b1) $stop; if (QINVALID != 15) $stop; if (QSEND != 0) $stop; if (QOP != 1) $stop; if (QCL != 2) $stop; if (QPR != 3) $stop; if (QACK != 4) $stop; if (QRSP != 5) $stop; if ($size(array5) != 5) $stop; if ($size(array5i) != 5) $stop; enarray[2] = ENARRAY; enarray[3] = ENARRAY; if (enarray[2] !== ENARRAY) $stop; if (enarray[3] !== ENARRAY) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_interface_gen_noinl.py0000755000542200017500000000103615101701376023756 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_gen.v" test.compile(v_flags2=["-fno-inline"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_extend.py0000755000542200017500000000072615101701376021262 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_protect_ids.v0000644000542200017500000000327415101701376022125 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface secret_intf(); logic secret_a; integer secret_b; endinterface module t (/*AUTOARG*/ // Inputs clk ); input clk; secret_sub secret_inst (.*); secret_other secret_inst2 (.*); endmodule module secret_sub ( input clk); // verilator no_inline_module typedef struct { integer secret_field; integer secret_field_r; } secret_st; int secret_cyc; real secret_cyc_r; integer secret_o; real secret_r; secret_st secret_pair; export "DPI-C" task dpix_a_task; task dpix_a_task(input int i, output int o); o = i + 1; endtask import "DPI-C" context task dpii_a_task(input int i, output int o); export "DPI-C" function dpix_a_func; function int dpix_a_func(input int i); return i + 2; endfunction import "DPI-C" context function int dpii_a_func(input int i); // Test loop always @ (posedge clk) begin secret_pair.secret_field += 1; secret_pair.secret_field_r += 2; secret_cyc_r = $itor(secret_cyc)/10.0 - 5.0; secret_cyc <= dpii_a_func(secret_cyc); secret_r += 1.0 + $cos(secret_cyc_r); dpix_a_task(secret_cyc, secret_o); if (secret_cyc==90) begin $write("*-* All Finished *-*\n"); end end endmodule module secret_other ( input clk); int secret_cyc; always @ (posedge clk) begin secret_cyc <= secret_cyc + 1; if (secret_cyc==99) begin $finish; end end secret_intf secret_interface(); endmodule verilator-5.042/test_regress/t/t_pp_misdef_bad.out0000644000542200017500000000100415101701376022711 0ustar mahmoudyfreeshell%Error: t/t_pp_misdef_bad.v:11:4: Define or directive not defined: '`NDEFINED' : ... Suggested alternative: '`DEFINED' 11 | `NDEFINED | ^~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_pp_misdef_bad.v:14:6: Define or directive not defined: '`imescale' : ... Suggested alternative: '`timescale' 14 | `imescale | ^~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_lib_prot_exe_bad.py0000755000542200017500000000122715101701376023251 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=[ "--protect-lib", "secret", "--protect-key", "secret-key", ], verilator_make_gcc=False, fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_vlt_match_error_3.out0000644000542200017500000000057215101701376023562 0ustar mahmoudyfreeshell%Error-NEEDTIMINGOPT: t/t_vlt_match_error.v:21:13: Use --timing or --no-timing to specify how delays should be handled : ... note: In instance 'DECLFILENAME' 21 | initial #1; | ^ ... For error description see https://verilator.org/warn/NEEDTIMINGOPT?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_mem_cond.py0000755000542200017500000000073415101701376021553 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_debug_inputs.py0000755000542200017500000000143015101701376022454 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(v_flags=["--dump-inputs -Wno-MULTITOP t/t_debug_inputs_b.v"]) test.file_grep(test.obj_dir + "/V" + test.name + "__inputs.vpp", r'module t_debug_inputs;') test.file_grep(test.obj_dir + "/V" + test.name + "__inputs.vpp", r'module t_debug_inputs_a;') test.file_grep(test.obj_dir + "/V" + test.name + "__inputs.vpp", r'module t_debug_inputs_b;') test.passes() verilator-5.042/test_regress/t/t_interface_virtual_unused3.v0000644000542200017500000000061315101701376024754 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface stream_ifc #( ) ( input logic clk_i ); endinterface package pkg; class stream_driver #(); virtual stream_ifc stream; endclass endpackage module t; endmodule verilator-5.042/test_regress/t/t_sys_file_scan2.dat0000644000542200017500000000001415101701376023001 0ustar mahmoudyfreeshellvec 6163 16 verilator-5.042/test_regress/t/t_display_p_elab.v0000644000542200017500000000365515101701376022560 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilog_format: off `define stop $stop `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `ifdef verilator `define no_optimize(v) $c(v) `else `define no_optimize(v) (v) `endif // verilog_format: on module t; // $sformatf is not supported as parameter by some simulators parameter int I = 234; parameter string IS = $sformatf(">%p<", I); initial `checks(IS, "> 234<"); parameter real R = 1.234; parameter string RS = $sformatf(">%p<", R); initial `checks(RS, ">1.234<"); int u[2]; parameter int U[2] = '{5, 6}; parameter string US = $sformatf(">%p<", U); initial `checks(US, ">'{'h5, 'h6}<"); `ifndef VERILATOR // Generally not supported by others parameter int Q[$] = '{1, 2}; parameter string QS = $sformatf(">%p<", Q); initial `checks(QS, "x"); // Generally not supported by others parameter int D[] = '{1, 2}; parameter string DS = $sformatf(">%p<", D); initial `checks(DS, ">'{1, 2}<"); parameter int A[int] = '{1: 10, 2: 20}; parameter string AS = $sformatf(">%p<", A); initial `checks(AS, "x"); typedef struct {int f, s;} s_t; parameter s_t S = '{f: 10, s: 20}; parameter string SS = $sformatf(">%p<", S); initial `checks(SS, ">'{f:10, s:20}<"); `endif // Original issue function integer infofunc(); $info("%p", U); return 0; endfunction localparam integer return_val = infofunc(); string s; initial begin #1; u[0] = `no_optimize(5); u[1] = `no_optimize(6); s = $sformatf(">%p<", u); `checks(s, ">'{'h5, 'h6}<"); `checks(US, ">'{'h5, 'h6}<"); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_lint_bsspace_bad.py0000755000542200017500000000076315101701376023250 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_assert_comp.out0000644000542200017500000000052015101701376022456 0ustar mahmoudyfreeshell[0] -Info: t_assert_comp.v:23: top.t [0] -Info: t_assert_comp.v:24: top.t: User run-time info [0] -Info: t_assert_comp.v:25: top.t: Percent=% PctPct=%% Ten=10 [0] %Warning: t_assert_comp.v:26: top.t [0] %Warning: t_assert_comp.v:27: top.t: User run-time warning [0] %Warning: t_assert_comp.v:28: top.t: 1 *-* All Finished *-* verilator-5.042/test_regress/t/t_scope_map.py0000755000542200017500000000111415101701376021731 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(make_top_shell=False, make_main=False, v_flags2=["--trace-vcd --exe", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_complex_params.out0000644000542200017500000001100415101701376024326 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $var wire 1 = clk $end $scope module $unit $end $var wire 1 # global_bit $end $upscope $end $scope module t $end $var wire 1 = clk $end $var wire 32 $ cyc [31:0] $end $var wire 2 % v_strp [1:0] $end $var wire 4 & v_strp_strp [3:0] $end $var wire 2 ' v_unip_strp [1:0] $end $var wire 2 ( v_arrp [2:1] $end $var wire 4 ) v_arrp_arrp [3:0] $end $var wire 4 * v_arrp_strp [3:0] $end $var wire 1 > v_arru[1] $end $var wire 1 ? v_arru[2] $end $var wire 1 @ v_arru_arru[3][1] $end $var wire 1 A v_arru_arru[3][2] $end $var wire 1 B v_arru_arru[4][1] $end $var wire 1 C v_arru_arru[4][2] $end $var wire 2 + v_arru_arrp[3] [2:1] $end $var wire 2 , v_arru_arrp[4] [2:1] $end $var wire 2 - v_arru_strp[3] [1:0] $end $var wire 2 . v_arru_strp[4] [1:0] $end $var real 64 / v_real $end $var real 64 1 v_arr_real[0] $end $var real 64 3 v_arr_real[1] $end $var wire 64 D v_chandle [63:0] $end $var wire 64 5 v_str32x2 [63:0] $end $var wire 32 7 v_enumed [31:0] $end $var wire 32 8 v_enumed2 [31:0] $end $var wire 3 9 v_enumb [2:0] $end $var wire 6 : v_enumb2_str [5:0] $end $var wire 8 F unpacked_array[-2] [7:0] $end $var wire 8 G unpacked_array[-1] [7:0] $end $var wire 8 H unpacked_array[0] [7:0] $end $var wire 1 I LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end $scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end $var wire 32 J PARAM [31:0] $end $upscope $end $scope module p2 $end $var wire 32 K PARAM [31:0] $end $upscope $end $scope module p3 $end $var wire 32 L PARAM [31:0] $end $upscope $end $scope module unnamedblk1 $end $var wire 32 ; b [31:0] $end $scope module unnamedblk2 $end $var wire 32 < a [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 1# b00000000000000000000000000000000 $ b00 % b0000 & b00 ' b00 ( b0000 ) b0000 * b00 + b00 , b00 - b00 . r0 / r0 1 r0 3 b0000000000000000000000000000000000000000000000000000000011111111 5 b00000000000000000000000000000000 7 b00000000000000000000000000000000 8 b000 9 b000000 : b00000000000000000000000000000000 ; b00000000000000000000000000000000 < 0= 0> 0? 0@ 0A 0B 0C b0000000000000000000000000000000000000000000000000000000000000000 D b00000000 F b00000000 G b00000000 H 0I b00000000000000000000000000000100 J b00000000000000000000000000000010 K b00000000000000000000000000000011 L #10 b00000000000000000000000000000001 $ b11 % b1111 & b11 ' b11 ( b1111 ) b1111 * b11 + b11 , b11 - b11 . r0.1 / r0.2 1 r0.3 3 b0000000000000000000000000000000100000000000000000000000011111110 5 b00000000000000000000000000000001 7 b00000000000000000000000000000010 8 b111 9 b00000000000000000000000000000101 ; b00000000000000000000000000000101 < 1= #15 0= #20 b00000000000000000000000000000010 $ b00 % b0000 & b00 ' b00 ( b0000 ) b0000 * b00 + b00 , b00 - b00 . r0.2 / r0.4 1 r0.6 3 b0000000000000000000000000000001000000000000000000000000011111101 5 b00000000000000000000000000000010 7 b00000000000000000000000000000100 8 b110 9 b111111 : 1= #25 0= #30 b00000000000000000000000000000011 $ b11 % b1111 & b11 ' b11 ( b1111 ) b1111 * b11 + b11 , b11 - b11 . r0.3 / r0.6000000000000001 1 r0.8999999999999999 3 b0000000000000000000000000000001100000000000000000000000011111100 5 b00000000000000000000000000000011 7 b00000000000000000000000000000110 8 b101 9 b110110 : 1= #35 0= #40 b00000000000000000000000000000100 $ b00 % b0000 & b00 ' b00 ( b0000 ) b0000 * b00 + b00 , b00 - b00 . r0.4 / r0.8 1 r1.2 3 b0000000000000000000000000000010000000000000000000000000011111011 5 b00000000000000000000000000000100 7 b00000000000000000000000000001000 8 b100 9 b101101 : 1= #45 0= #50 b00000000000000000000000000000101 $ b11 % b1111 & b11 ' b11 ( b1111 ) b1111 * b11 + b11 , b11 - b11 . r0.5 / r1 1 r1.5 3 b0000000000000000000000000000010100000000000000000000000011111010 5 b00000000000000000000000000000101 7 b00000000000000000000000000001010 8 b011 9 b100100 : 1= #55 0= #60 b00000000000000000000000000000110 $ b00 % b0000 & b00 ' b00 ( b0000 ) b0000 * b00 + b00 , b00 - b00 . r0.6 / r1.2 1 r1.8 3 b0000000000000000000000000000011000000000000000000000000011111001 5 b00000000000000000000000000000110 7 b00000000000000000000000000001100 8 b010 9 b011011 : 1= verilator-5.042/test_regress/t/t_sys_readmem_align_h.mem0000644000542200017500000000106715101701376024106 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test data file // // Copyright 2006 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 @4 77554004_37654321_27654321_17654321_07654321_abcdef10 @a 7755400a_37654321_27654321_17654321_07654321_abcdef11 7755400b_37654321_27654321_17654321_07654321_abcdef12 7755400c_37654321_27654321_17654321_07654321_abcdef13 verilator-5.042/test_regress/t/t_enum_const_methods.py0000755000542200017500000000073415101701376023667 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_force_tri.out0000644000542200017500000000052215101701376022115 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_force_tri.v:27:10: Unsupported tristate construct: ASSIGNFORCE : ... note: In instance 't' 27 | force bus = 4'bzz10; | ^~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_pgo_threads_hier.vlt0000644000542200017500000000060415101701376023446 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 `verilator_config hier_workers -module "Test" -workers 2 hier_block -module "Check" hier_workers -module "Check" -workers 2 hier_block -module "CoreHier" hier_workers -module "CoreHier" -workers 2 verilator-5.042/test_regress/t/t_vpi_sc.cpp0000644000542200017500000000067215101701376021405 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include VM_PREFIX_INCLUDE VM_PREFIX* tb = nullptr; int sc_main(int argc, char* argv[]) { tb = new VM_PREFIX{"tb"}; VL_PRINTF("*-* All Finished *-*\n"); tb->final(); VL_DO_DANGLING(delete tb, tb); return 0; } verilator-5.042/test_regress/t/t_interface_down_inlbd.py0000755000542200017500000000112215101701376024121 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_down.v" test.compile(v_flags2=['+define+INLINE_B +define+INLINE_D'], verilator_flags2=['-trace']) test.execute() test.passes() verilator-5.042/test_regress/t/t_sys_readmem_eof.v0000644000542200017500000000133315101701376022741 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define STRINGIFY(x) `"x`" module t(); reg [7:0] rom [4]; initial begin $readmemh({`STRINGIFY(`TEST_OBJ_DIR), "/dat.mem"}, rom); `checkh(rom[0], 8'h1); `checkh(rom[1], 8'h10); `checkh(rom[2], 8'h20); `checkh(rom[3], 8'h30); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_slice_cmp.v0000644000542200017500000000132215101701376021534 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; bit a [5:0]; bit b [5:0]; initial begin a = '{1, 1, 1, 0, 0, 0}; b = '{0, 0, 0, 1, 1, 1}; $display(":assert: ('%b%b%b_%b%b%b' == '111_000')", a[5], a[4], a[3], a[2], a[1], a[0]); $display(":assert: ('%b%b%b_%b%b%b' == '000_111')", b[5], b[4], b[3], b[2], b[1], b[0]); if ((a[5:3] == b[2:0]) != 1'b1) $stop; if ((a[5:3] != b[2:0]) != 1'b0) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_trace_ena_sc.out0000644000542200017500000000243415101701376022553 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $scope module t $end $var wire 1 # clk $end $var wire 32 $ cyc [31:0] $end $var wire 32 % c_trace_on [31:0] $end $var real 64 & r $end $upscope $end $upscope $end $enddefinitions $end #0 0# b00000000000000000000000000000001 $ b00000000000000000000000000000000 % r0 & #10 1# b00000000000000000000000000000010 $ r0.1 & #15 0# #20 1# b00000000000000000000000000000011 $ b00000000000000000000000000000001 % r0.2 & #25 0# #30 1# b00000000000000000000000000000100 $ b00000000000000000000000000000010 % r0.3 & #35 0# #40 1# b00000000000000000000000000000101 $ b00000000000000000000000000000011 % r0.4 & #45 0# #50 1# b00000000000000000000000000000110 $ b00000000000000000000000000000100 % r0.5 & #55 0# #60 1# b00000000000000000000000000000111 $ b00000000000000000000000000000101 % r0.6 & #65 0# #70 1# b00000000000000000000000000001000 $ b00000000000000000000000000000110 % r0.7 & #75 0# #80 1# b00000000000000000000000000001001 $ b00000000000000000000000000000111 % r0.7999999999999999 & #85 0# #90 1# b00000000000000000000000000001010 $ b00000000000000000000000000001000 % r0.8999999999999999 & #95 0# #100 1# b00000000000000000000000000001011 $ b00000000000000000000000000001001 % r0.9999999999999999 & #104 verilator-5.042/test_regress/t/t_mod_empty.v0000644000542200017500000000035715101701376021602 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module emptyModule; endmodule verilator-5.042/test_regress/t/t_interface_top_bad.out0000644000542200017500000000144015101701376023571 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_interface_top_bad.v:17:19: Unsupported: Interfaced port on top level module 17 | ifc.counter_mp c_data | ^~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: t/t_interface_top_bad.v:17:4: Interface 'ifc' not connected as parent's interface not connected : ... Perhaps caused by another error on the parent interface that needs resolving : ... Or, perhaps intended an interface instantiation but are missing parenthesis (IEEE 1800-2023 25.3)? 17 | ifc.counter_mp c_data | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_x_rand_mt_stability_add.out0000644000542200017500000000105615101701376025013 0ustar mahmoudyfreeshelluninitialized = 0xf5bbcbc0 x_assigned (initial) = 0x00000000 uninitialized2 = 0xa979eb54 big = 0xa20c93ac50d8c57d4c80949aa68e82775da6af98ce08f75dc6ccfad97b059a33 random_init = 0x952aaa76 top.t.the_sub_yes_inline_1 no_init 0x4a544f7798b83fc8 top.t.the_sub_yes_inline_2 no_init 0x19b7000ee0472c9 top.t.the_sub_no_inline_1 no_init 0x38121a34978975dd top.t.the_sub_no_inline_2 no_init 0x9022c84ae0fa3cf6 rand = 0xb3cf9302 rand = 0xf0acf3e4 rand = 0xca0ac74c rand = 0x4eddfc2c rand = 0x1919db69 x_assigned = 0x486aeb2d Last rand = 0x2d118c9b *-* All Finished *-* verilator-5.042/test_regress/t/t_order_dpi_export_8.py0000755000542200017500000000100715101701376023563 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(verilator_flags2=["--exe", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_flag_hier0_bad.py0000755000542200017500000000227315101701376022600 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_hier_block.v" test.lint( fails=True, verilator_flags2=[ '--hierarchical-block', 'modName,mangledName,param0,"paramValue0",param0,"paramValue1",param1,2,param3', '--hierarchical-block', 'modName', '--hierarchical-block', 'mod0,mod1,\'"str\\\'', # end with backslash '--hierarchical-block', 'mod2,mod3,\'"str\\a\'', # unexpected 'a' after backslash '--hierarchical-block', 'mod4,mod5,\'"str"abc\',', # not end with " '--hierarchical-block', 'mod6,mod7,\'"str"\',', # end with , '--hierarchical-block', 'mod8,mod9,\'s"tr"\',', # unexpected " '--hierarchical-block', 'modA,modB,param,', # end with , ], expect_filename=test.golden_filename) # yapf:disable test.passes() verilator-5.042/test_regress/t/t_timescale_lint.v0000644000542200017500000000055615101701376022602 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under The Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module pre_no_ts; endmodule `timescale 1ns/1ns module t; pre_no_ts pre_no_ts(); post_no_ts pst_no_ts(); endmodule module post_no_ts; endmodule verilator-5.042/test_regress/t/t_enum_size.v0000644000542200017500000000213615101701376021600 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; // verilator lint_off WIDTH typedef enum logic[2:0] {P=0, W=1'b1, E, N, S} Dirs; typedef enum integer {UP=0, UW=1'b1} UNSIZED; // verilator lint_on WIDTH localparam LEN = 3; localparam COL = 4; localparam [59:0] SEQ = {LEN'(N), LEN'(E), LEN'(W), LEN'(P) ,LEN'(S), LEN'(E), LEN'(W), LEN'(P) ,LEN'(S), LEN'(N), LEN'(W), LEN'(P) ,LEN'(S), LEN'(N), LEN'(E), LEN'(P) ,LEN'(S), LEN'(N), LEN'(E), LEN'(W)}; bit [59:0] SE2 = {N, E, W, P ,S, E, W, P ,S, N, W, P ,S, N, E, P ,S, N, E, W}; initial begin if (SEQ != 60'o32104210431043204321) $stop; if (SE2 != 60'o32104210431043204321) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_gate_array.py0000755000542200017500000000073415101701376022110 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_clocking_bad3.v0000644000542200017500000000063615101701376022267 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; clocking cb @(posedge clk); input in; output out; endclocking clocking cb @(posedge clk); endclocking endmodule verilator-5.042/test_regress/t/t_gen_nonconst_bad.v0000644000542200017500000000037615101701376023106 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; nfound nfound(); endmodule verilator-5.042/test_regress/t/t_mod_interface_array3.py0000755000542200017500000000076615101701376024057 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_cover_line_trace.py0000755000542200017500000000172315101701376023274 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_cover_line.v" test.compile( verilator_flags2=['--cc --coverage-line --trace-vcd --trace-coverage +define+ATTRIBUTE']) test.execute() test.run(cmd=[ os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--annotate-points", "--annotate", test.obj_dir + "/annotated", test.obj_dir + "/coverage.dat", ], verilator_run=True) test.files_identical(test.obj_dir + "/annotated/t_cover_line.v", "t/t_cover_line.out") test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_var_rsvd.v0000644000542200017500000000131015101701376021421 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilator lint_off SYMRSVDWORD module t (/*AUTOARG*/ // Inputs bool ); input bool; // BAD reg vector; // OK, as not public reg switch /*verilator public*/; // Bad typedef struct packed { logic [31:0] vector; // OK, as not public } test; test t; // global is a 1800-2009 reserved word, but we allow it when possible. reg global; initial begin t.vector = 1; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_sys_file_scan.v0000644000542200017500000000200015101701376022411 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" module t; integer infile, outfile; integer count, a; initial begin infile = $fopen("t/t_sys_file_scan.dat", "r"); outfile = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_file_scan_test.log"}, "w"); count = 1234; `ifdef TEST_VERBOSE $display("-count == %0d, infile %d, outfile %d", count, infile, outfile); `endif count = $fscanf(infile, "%d\n", a); `ifdef TEST_VERBOSE // Ifdefing this out gave bug248 $display("-count == %0d, infile %d, outfile %d", count, infile, outfile); `endif if (count == 0) $stop; $fwrite(outfile, "# a\n"); $fwrite(outfile, "%d\n", a); $fclose(infile); $fclose(outfile); $write("*-* All Finished *-*\n"); $finish(0); // Test arguments to finish end endmodule verilator-5.042/test_regress/t/t_enum_name2.py0000755000542200017500000000073415101701376022020 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_param.v0000644000542200017500000000145015101701376022056 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014 by Jonathon Donaldson. // SPDX-License-Identifier: CC0-1.0 package my_funcs; function automatic int simple_func (input int value); begin simple_func = value; end endfunction endpackage package my_module_types; import my_funcs::*; localparam MY_PARAM = 3; localparam MY_PARAM2 /*verilator public*/ = simple_func(12); endpackage module t import my_module_types::*; ( input i_clk, input [MY_PARAM-1:0] i_d, output logic [MY_PARAM-1:0] o_q ); always_ff @(posedge i_clk) o_q <= i_d; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_dpi_display.v0000644000542200017500000000224115101701376022100 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2010 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (); `ifndef VERILATOR `error "Only Verilator supports PLI-ish DPI calls and sformat conversion." `endif import "DPI-C" context dpii_display_call = function void \$dpii_display (input string formatted /*verilator sformat*/ ); integer a; initial begin // Check variable width constant string conversions $dpii_display(""); $dpii_display("c"); $dpii_display("co"); $dpii_display("cons"); $dpii_display("constant"); $dpii_display("constant_value"); a = $c("10"); // Don't optimize away "a" $display ("one10=%x",a); // Check single arg $dpii_display("one10=%x",a); $display ("Mod=%m 16=%d 10=%x",a,a); // Check multiarg $dpii_display("Mod=%m 16=%d 10=%x",a,a); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_cast_param_logic.py0000755000542200017500000000070615101701376023260 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.042/test_regress/t/t_covergroup_with_function_foo_bad.py0000755000542200017500000000077415101701376026602 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_randomize_union_bad.out0000644000542200017500000000043715101701376024154 0ustar mahmoudyfreeshell%Error: t/t_randomize_union_bad.v:7:9: Unpacked unions shall not be declared as rand or randc. (IEEE 1800-2023 18.4) 7 | typedef union { | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_gate_primitives_implicit_net.out0000755000542200017500000004016315101701376026104 0ustar mahmoudyfreeshell%Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:18:20: Signal definition not found, creating implicitly: 'i_and1' 18 | and g_and(o_and, i_and1, i_and2, i_and3), | ^~~~~~ ... For warning description see https://verilator.org/warn/IMPLICIT?v=latest ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message. %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:18:28: Signal definition not found, creating implicitly: 'i_and2' : ... Suggested alternative: 'i_and1' 18 | and g_and(o_and, i_and1, i_and2, i_and3), | ^~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:18:36: Signal definition not found, creating implicitly: 'i_and3' : ... Suggested alternative: 'i_and1' 18 | and g_and(o_and, i_and1, i_and2, i_and3), | ^~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:18:13: Signal definition not found, creating implicitly: 'o_and' : ... Suggested alternative: 'i_and1' 18 | and g_and(o_and, i_and1, i_and2, i_and3), | ^~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:19:11: Signal definition not found, creating implicitly: 'o2_and' : ... Suggested alternative: 'o_and' 19 | g2_and(o2_and, i_and1, i_and2, i_and3); | ^~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:20:29: Signal definition not found, creating implicitly: 'i_not1' 20 | not g_not(o_not1, o_not2, i_not1), | ^~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:20:13: Signal definition not found, creating implicitly: 'o_not1' : ... Suggested alternative: 'i_not1' 20 | not g_not(o_not1, o_not2, i_not1), | ^~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:20:21: Signal definition not found, creating implicitly: 'o_not2' : ... Suggested alternative: 'o_not1' 20 | not g_not(o_not1, o_not2, i_not1), | ^~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:21:11: Signal definition not found, creating implicitly: 'o2_not1' : ... Suggested alternative: 'o_not1' 21 | g2_not(o2_not1, o_not2, i_not1); | ^~~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:22:20: Signal definition not found, creating implicitly: 'i_nor1' : ... Suggested alternative: 'i_not1' 22 | nor g_nor(o_nor, i_nor1, i_nor2, i_nor3), | ^~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:22:28: Signal definition not found, creating implicitly: 'i_nor2' : ... Suggested alternative: 'i_nor1' 22 | nor g_nor(o_nor, i_nor1, i_nor2, i_nor3), | ^~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:22:36: Signal definition not found, creating implicitly: 'i_nor3' : ... Suggested alternative: 'i_nor1' 22 | nor g_nor(o_nor, i_nor1, i_nor2, i_nor3), | ^~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:22:13: Signal definition not found, creating implicitly: 'o_nor' : ... Suggested alternative: 'i_nor1' 22 | nor g_nor(o_nor, i_nor1, i_nor2, i_nor3), | ^~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:23:11: Signal definition not found, creating implicitly: 'o2_nor' : ... Suggested alternative: 'o_nor' 23 | g2_nor(o2_nor, i_nor1, i_nor2, i_nor3); | ^~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:24:17: Signal definition not found, creating implicitly: 'i_or1' : ... Suggested alternative: 'i_nor1' 24 | or g_or(o_or, i_or1, i_or2, i_or3), | ^~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:24:24: Signal definition not found, creating implicitly: 'i_or2' : ... Suggested alternative: 'i_nor2' 24 | or g_or(o_or, i_or1, i_or2, i_or3), | ^~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:24:31: Signal definition not found, creating implicitly: 'i_or3' : ... Suggested alternative: 'i_nor3' 24 | or g_or(o_or, i_or1, i_or2, i_or3), | ^~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:24:11: Signal definition not found, creating implicitly: 'o_or' : ... Suggested alternative: 'o_nor' 24 | or g_or(o_or, i_or1, i_or2, i_or3), | ^~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:25:10: Signal definition not found, creating implicitly: 'o2_or' : ... Suggested alternative: 'o2_nor' 25 | g2_or(o2_or, i_or1, i_or2, i_or3); | ^~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:26:23: Signal definition not found, creating implicitly: 'i_nand1' : ... Suggested alternative: 'i_and1' 26 | nand g_nand(o_nand, i_nand1, i_nand2, i_nand3), | ^~~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:26:32: Signal definition not found, creating implicitly: 'i_nand2' : ... Suggested alternative: 'i_and2' 26 | nand g_nand(o_nand, i_nand1, i_nand2, i_nand3), | ^~~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:26:41: Signal definition not found, creating implicitly: 'i_nand3' : ... Suggested alternative: 'i_and3' 26 | nand g_nand(o_nand, i_nand1, i_nand2, i_nand3), | ^~~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:26:15: Signal definition not found, creating implicitly: 'o_nand' : ... Suggested alternative: 'o_and' 26 | nand g_nand(o_nand, i_nand1, i_nand2, i_nand3), | ^~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:27:12: Signal definition not found, creating implicitly: 'o2_nand' : ... Suggested alternative: 'o2_and' 27 | g2_nand(o2_nand, i_nand1, i_nand2, i_nand3); | ^~~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:28:20: Signal definition not found, creating implicitly: 'i_xor1' : ... Suggested alternative: 'i_nor1' 28 | xor g_xor(o_xor, i_xor1, i_xor2, i_xor3), | ^~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:28:28: Signal definition not found, creating implicitly: 'i_xor2' : ... Suggested alternative: 'i_nor2' 28 | xor g_xor(o_xor, i_xor1, i_xor2, i_xor3), | ^~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:28:36: Signal definition not found, creating implicitly: 'i_xor3' : ... Suggested alternative: 'i_nor3' 28 | xor g_xor(o_xor, i_xor1, i_xor2, i_xor3), | ^~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:28:13: Signal definition not found, creating implicitly: 'o_xor' : ... Suggested alternative: 'o_nor' 28 | xor g_xor(o_xor, i_xor1, i_xor2, i_xor3), | ^~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:29:11: Signal definition not found, creating implicitly: 'o2_xor' : ... Suggested alternative: 'o2_nor' 29 | g2_xor(o2_xor, i_xor1, i_xor2, i_xor3); | ^~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:30:22: Signal definition not found, creating implicitly: 'i_xnor1' : ... Suggested alternative: 'i_nor1' 30 | xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3), | ^~~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:30:31: Signal definition not found, creating implicitly: 'i_xnor2' : ... Suggested alternative: 'i_nor2' 30 | xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3), | ^~~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:30:40: Signal definition not found, creating implicitly: 'i_xnor3' : ... Suggested alternative: 'i_nor3' 30 | xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3), | ^~~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:30:14: Signal definition not found, creating implicitly: 'o_xnor' : ... Suggested alternative: 'o_nor' 30 | xnor g_xor(o_xnor, i_xnor1, i_xnor2, i_xnor3), | ^~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:31:11: Signal definition not found, creating implicitly: 'o2_xnor' : ... Suggested alternative: 'o2_nor' 31 | g2_xor(o2_xnor, i_xnor1, i_xnor2, i_xnor3); | ^~~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:32:29: Signal definition not found, creating implicitly: 'i_buf1' 32 | buf g_buf(o_buf1, o_buf2, i_buf1), | ^~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:32:13: Signal definition not found, creating implicitly: 'o_buf1' : ... Suggested alternative: 'i_buf1' 32 | buf g_buf(o_buf1, o_buf2, i_buf1), | ^~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:32:21: Signal definition not found, creating implicitly: 'o_buf2' : ... Suggested alternative: 'o_buf1' 32 | buf g_buf(o_buf1, o_buf2, i_buf1), | ^~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:33:11: Signal definition not found, creating implicitly: 'o2_buf1' : ... Suggested alternative: 'o_buf1' 33 | g2_buf(o2_buf1, o_buf2, i_buf1); | ^~~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:34:40: Signal definition not found, creating implicitly: 'i_bufif02' 34 | bufif0 g_bufif0(o_bufif0, i_bufif01, i_bufif02), | ^~~~~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:34:29: Signal definition not found, creating implicitly: 'i_bufif01' : ... Suggested alternative: 'i_bufif02' 34 | bufif0 g_bufif0(o_bufif0, i_bufif01, i_bufif02), | ^~~~~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:34:19: Signal definition not found, creating implicitly: 'o_bufif0' : ... Suggested alternative: 'i_bufif01' 34 | bufif0 g_bufif0(o_bufif0, i_bufif01, i_bufif02), | ^~~~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:35:14: Signal definition not found, creating implicitly: 'o2_bufif0' : ... Suggested alternative: 'o_bufif0' 35 | g2_bufif0(o2_bufif0, i_bufif01, i_bufif02); | ^~~~~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:36:40: Signal definition not found, creating implicitly: 'i_bufif12' : ... Suggested alternative: 'i_bufif02' 36 | bufif1 g_bufif1(o_bufif1, i_bufif11, i_bufif12), | ^~~~~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:36:29: Signal definition not found, creating implicitly: 'i_bufif11' : ... Suggested alternative: 'i_bufif01' 36 | bufif1 g_bufif1(o_bufif1, i_bufif11, i_bufif12), | ^~~~~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:36:19: Signal definition not found, creating implicitly: 'o_bufif1' : ... Suggested alternative: 'o_bufif0' 36 | bufif1 g_bufif1(o_bufif1, i_bufif11, i_bufif12), | ^~~~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:37:14: Signal definition not found, creating implicitly: 'o2_bufif1' : ... Suggested alternative: 'o2_bufif0' 37 | g2_bufif1(o2_bufif1, i_bufif11, i_bufif12); | ^~~~~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:38:40: Signal definition not found, creating implicitly: 'i_notif02' : ... Suggested alternative: 'i_bufif02' 38 | notif0 g_notif0(o_notif0, i_notif01, i_notif02), | ^~~~~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:38:29: Signal definition not found, creating implicitly: 'i_notif01' : ... Suggested alternative: 'i_notif02' 38 | notif0 g_notif0(o_notif0, i_notif01, i_notif02), | ^~~~~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:38:19: Signal definition not found, creating implicitly: 'o_notif0' : ... Suggested alternative: 'i_notif01' 38 | notif0 g_notif0(o_notif0, i_notif01, i_notif02), | ^~~~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:39:14: Signal definition not found, creating implicitly: 'o2_notif0' : ... Suggested alternative: 'o_notif0' 39 | g2_notif0(o2_notif0, i_notif01, i_notif02); | ^~~~~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:40:40: Signal definition not found, creating implicitly: 'i_notif12' : ... Suggested alternative: 'i_notif02' 40 | notif1 g_notif1(o_notif1, i_notif11, i_notif12), | ^~~~~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:40:29: Signal definition not found, creating implicitly: 'i_notif11' : ... Suggested alternative: 'i_notif01' 40 | notif1 g_notif1(o_notif1, i_notif11, i_notif12), | ^~~~~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:40:19: Signal definition not found, creating implicitly: 'o_notif1' : ... Suggested alternative: 'o_notif0' 40 | notif1 g_notif1(o_notif1, i_notif11, i_notif12), | ^~~~~~~~ %Warning-IMPLICIT: t/t_gate_primitives_implicit_net.v:41:14: Signal definition not found, creating implicitly: 'o2_notif1' : ... Suggested alternative: 'o2_notif0' 41 | g2_notif1(o2_notif1, i_notif11, i_notif12); | ^~~~~~~~~ verilator-5.042/test_regress/t/t_comb_input_0.v0000644000542200017500000000136515101701376022163 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2022 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module top( clk, inc ); input clk; input [31:0] inc; // Cycle count reg [31:0] cyc = 0; // Combinational logic driven from primary input wire [31:0] sum = cyc + inc; always @(posedge clk) begin $display("cyc: %d sum: %d", cyc, sum); if (sum != 2*cyc + 1) $stop; cyc <= cyc + 1; if (cyc == 100) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_hier_block_type_param_multiple.v0000644000542200017500000000135215101701376026036 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t( clk ); input clk; logic [31:0] in1; logic [31:0] out1; assign in1 = 0; Test #(.TYPE_IN(logic[31:0]), .TYPE_OUT(logic[31:0])) test(.out (out1), .in (in1)); always @ (posedge clk) begin if (out1 !== ~in1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module Test #(parameter type TYPE_IN = logic [4:0], parameter type TYPE_OUT = logic [7:0]) ( output TYPE_IN out, input TYPE_OUT in ); /*verilator hier_block*/ assign out = ~ in; endmodule verilator-5.042/test_regress/t/t_gen_missing_bad2.py0000755000542200017500000000076315101701376023166 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_virtual_interface_member_trigger_realistic_case.v0000755000542200017500000000675315101701376031430 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by PlanV GmbH. // SPDX-License-Identifier: CC0-1.0 `timescale 1ns/1ps interface INTF(); logic clk; logic [7:0] data; logic valid; logic ready; endinterface time TA = 5ns; class intf_driver; virtual INTF intf; function new(virtual INTF intf); this.intf = intf; endfunction task cycle_start(); #TA; endtask task cycle_end(); @(posedge intf.clk); endtask task init_master(); intf.data = '0; intf.valid = 0; endtask task init_slave(); intf.ready = 0; endtask task recv_data(output logic [7:0] data); intf.ready <= #TA 1; cycle_start(); while (!(intf.valid && intf.ready)) begin cycle_end(); cycle_start(); end cycle_end(); data = intf.data; intf.ready <= #TA 0; endtask task send_data(input logic [7:0] data); intf.data <= #TA data; intf.valid <= #TA 1; cycle_start(); while (!(intf.valid && intf.ready)) begin cycle_end(); cycle_start(); end cycle_end(); intf.valid <= #TA 0; endtask endclass module t; logic clk; logic [7:0] data; logic valid; logic ready; logic [7:0] recv_data; INTF read_intf(); assign read_intf.clk = clk; assign read_intf.data = data; assign read_intf.valid = valid; assign ready = read_intf.ready; INTF write_intf(); assign write_intf.clk = clk; assign data = write_intf.data; assign valid = write_intf.valid; assign write_intf.ready = ready; intf_driver driver_master; intf_driver driver_slave; virtual INTF vif_read = read_intf; virtual INTF vif_write = write_intf; initial begin repeat(1000) begin clk = '1; #10ns; clk = '0; #10ns; end end initial begin driver_master = new(vif_write); driver_slave = new(vif_read); driver_master.init_master(); driver_slave.init_slave(); fork begin #35ns; driver_master.send_data(8'h42); // $display("[%0d]: Write data: %02x", $time, write_intf.data); #10ns; driver_master.send_data(8'h43); // $display("[%0d]: Write data: %02x", $time, write_intf.data); #10ns; driver_master.send_data(8'h44); // $display("[%0d]: Write data: %02x", $time, write_intf.data); end begin #10ns; driver_slave.recv_data(recv_data); // $display("[%0d]: Got data: %02x", $time, recv_data); if (recv_data !== 8'h42) $stop; #5ns; driver_slave.recv_data(recv_data); // $display("[%0d]: Got data: %02x", $time, recv_data); if (recv_data !== 8'h43) $stop; #15ns; driver_slave.recv_data(recv_data); // $display("[%0d]: Got data: %02x", $time, recv_data); if (recv_data !== 8'h44) $stop; end join $write("*-* All Finished *-*\n"); $finish; end // Dump waveforms // initial begin // $dumpfile("t_virtual_interface_member_trigger.vcd"); // $dumpvars(0, t_virtual_interface_member_trigger); // end endmodule verilator-5.042/test_regress/t/t_sys_readmem_bad_addr.mem0000644000542200017500000000054415101701376024224 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test data file // // Copyright 2006 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 @121212 10 verilator-5.042/test_regress/t/t_no_trace_top.out0000644000542200017500000014235415101701376022627 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $scope module t $end $var wire 1 # clk $end $var wire 32 $ cyc [31:0] $end $upscope $end $upscope $end $enddefinitions $end #0 1# b00000000000000000000000000000000 $ #1 0# #2 1# b00000000000000000000000000000001 $ #3 0# #4 1# b00000000000000000000000000000010 $ #5 0# #6 1# b00000000000000000000000000000011 $ #7 0# #8 1# b00000000000000000000000000000100 $ #9 0# #10 1# b00000000000000000000000000000101 $ #11 0# #12 1# b00000000000000000000000000000110 $ #13 0# #14 1# b00000000000000000000000000000111 $ #15 0# #16 1# b00000000000000000000000000001000 $ #17 0# #18 1# b00000000000000000000000000001001 $ #19 0# #20 1# b00000000000000000000000000001010 $ #21 0# #22 1# b00000000000000000000000000001011 $ #23 0# #24 1# b00000000000000000000000000001100 $ #25 0# #26 1# b00000000000000000000000000001101 $ #27 0# #28 1# b00000000000000000000000000001110 $ #29 0# #30 1# b00000000000000000000000000001111 $ #31 0# #32 1# b00000000000000000000000000010000 $ #33 0# #34 1# b00000000000000000000000000010001 $ #35 0# #36 1# b00000000000000000000000000010010 $ #37 0# #38 1# b00000000000000000000000000010011 $ #39 0# #40 1# b00000000000000000000000000010100 $ #41 0# #42 1# b00000000000000000000000000010101 $ #43 0# #44 1# b00000000000000000000000000010110 $ #45 0# #46 1# b00000000000000000000000000010111 $ #47 0# #48 1# b00000000000000000000000000011000 $ #49 0# #50 1# b00000000000000000000000000011001 $ #51 0# #52 1# b00000000000000000000000000011010 $ #53 0# #54 1# b00000000000000000000000000011011 $ #55 0# #56 1# b00000000000000000000000000011100 $ #57 0# #58 1# b00000000000000000000000000011101 $ #59 0# #60 1# b00000000000000000000000000011110 $ #61 0# #62 1# b00000000000000000000000000011111 $ #63 0# #64 1# b00000000000000000000000000100000 $ #65 0# #66 1# b00000000000000000000000000100001 $ #67 0# #68 1# b00000000000000000000000000100010 $ #69 0# #70 1# b00000000000000000000000000100011 $ #71 0# #72 1# b00000000000000000000000000100100 $ #73 0# #74 1# b00000000000000000000000000100101 $ #75 0# #76 1# b00000000000000000000000000100110 $ #77 0# #78 1# b00000000000000000000000000100111 $ #79 0# #80 1# b00000000000000000000000000101000 $ #81 0# #82 1# b00000000000000000000000000101001 $ #83 0# #84 1# b00000000000000000000000000101010 $ #85 0# #86 1# b00000000000000000000000000101011 $ #87 0# #88 1# b00000000000000000000000000101100 $ #89 0# #90 1# b00000000000000000000000000101101 $ #91 0# #92 1# b00000000000000000000000000101110 $ #93 0# #94 1# b00000000000000000000000000101111 $ #95 0# #96 1# b00000000000000000000000000110000 $ #97 0# #98 1# b00000000000000000000000000110001 $ #99 0# #100 1# b00000000000000000000000000110010 $ #101 0# #102 1# b00000000000000000000000000110011 $ #103 0# #104 1# b00000000000000000000000000110100 $ #105 0# #106 1# b00000000000000000000000000110101 $ #107 0# #108 1# b00000000000000000000000000110110 $ #109 0# #110 1# b00000000000000000000000000110111 $ #111 0# #112 1# b00000000000000000000000000111000 $ #113 0# #114 1# b00000000000000000000000000111001 $ #115 0# #116 1# b00000000000000000000000000111010 $ #117 0# #118 1# b00000000000000000000000000111011 $ #119 0# #120 1# b00000000000000000000000000111100 $ #121 0# #122 1# b00000000000000000000000000111101 $ #123 0# #124 1# b00000000000000000000000000111110 $ #125 0# #126 1# b00000000000000000000000000111111 $ #127 0# #128 1# b00000000000000000000000001000000 $ #129 0# #130 1# b00000000000000000000000001000001 $ #131 0# #132 1# b00000000000000000000000001000010 $ #133 0# #134 1# b00000000000000000000000001000011 $ #135 0# #136 1# b00000000000000000000000001000100 $ #137 0# #138 1# b00000000000000000000000001000101 $ #139 0# #140 1# b00000000000000000000000001000110 $ #141 0# #142 1# b00000000000000000000000001000111 $ #143 0# #144 1# b00000000000000000000000001001000 $ #145 0# #146 1# b00000000000000000000000001001001 $ #147 0# #148 1# b00000000000000000000000001001010 $ #149 0# #150 1# b00000000000000000000000001001011 $ #151 0# #152 1# b00000000000000000000000001001100 $ #153 0# #154 1# b00000000000000000000000001001101 $ #155 0# #156 1# b00000000000000000000000001001110 $ #157 0# #158 1# b00000000000000000000000001001111 $ #159 0# #160 1# b00000000000000000000000001010000 $ #161 0# #162 1# b00000000000000000000000001010001 $ #163 0# #164 1# b00000000000000000000000001010010 $ #165 0# #166 1# b00000000000000000000000001010011 $ #167 0# #168 1# b00000000000000000000000001010100 $ #169 0# #170 1# b00000000000000000000000001010101 $ #171 0# #172 1# b00000000000000000000000001010110 $ #173 0# #174 1# b00000000000000000000000001010111 $ #175 0# #176 1# b00000000000000000000000001011000 $ #177 0# #178 1# b00000000000000000000000001011001 $ #179 0# #180 1# b00000000000000000000000001011010 $ #181 0# #182 1# b00000000000000000000000001011011 $ #183 0# #184 1# b00000000000000000000000001011100 $ #185 0# #186 1# b00000000000000000000000001011101 $ #187 0# #188 1# b00000000000000000000000001011110 $ #189 0# #190 1# b00000000000000000000000001011111 $ #191 0# #192 1# b00000000000000000000000001100000 $ #193 0# #194 1# b00000000000000000000000001100001 $ #195 0# #196 1# b00000000000000000000000001100010 $ #197 0# #198 1# b00000000000000000000000001100011 $ #199 0# #200 1# b00000000000000000000000001100100 $ #201 0# #202 1# b00000000000000000000000001100101 $ #203 0# #204 1# b00000000000000000000000001100110 $ #205 0# #206 1# b00000000000000000000000001100111 $ #207 0# #208 1# b00000000000000000000000001101000 $ #209 0# #210 1# b00000000000000000000000001101001 $ #211 0# #212 1# b00000000000000000000000001101010 $ #213 0# #214 1# b00000000000000000000000001101011 $ #215 0# #216 1# b00000000000000000000000001101100 $ #217 0# #218 1# b00000000000000000000000001101101 $ #219 0# #220 1# b00000000000000000000000001101110 $ #221 0# #222 1# b00000000000000000000000001101111 $ #223 0# #224 1# b00000000000000000000000001110000 $ #225 0# #226 1# b00000000000000000000000001110001 $ #227 0# #228 1# b00000000000000000000000001110010 $ #229 0# #230 1# b00000000000000000000000001110011 $ #231 0# #232 1# b00000000000000000000000001110100 $ #233 0# #234 1# b00000000000000000000000001110101 $ #235 0# #236 1# b00000000000000000000000001110110 $ #237 0# #238 1# b00000000000000000000000001110111 $ #239 0# #240 1# b00000000000000000000000001111000 $ #241 0# #242 1# b00000000000000000000000001111001 $ #243 0# #244 1# b00000000000000000000000001111010 $ #245 0# #246 1# b00000000000000000000000001111011 $ #247 0# #248 1# b00000000000000000000000001111100 $ #249 0# #250 1# b00000000000000000000000001111101 $ #251 0# #252 1# b00000000000000000000000001111110 $ #253 0# #254 1# b00000000000000000000000001111111 $ #255 0# #256 1# b00000000000000000000000010000000 $ #257 0# #258 1# b00000000000000000000000010000001 $ #259 0# #260 1# b00000000000000000000000010000010 $ #261 0# #262 1# b00000000000000000000000010000011 $ #263 0# #264 1# b00000000000000000000000010000100 $ #265 0# #266 1# b00000000000000000000000010000101 $ #267 0# #268 1# b00000000000000000000000010000110 $ #269 0# #270 1# b00000000000000000000000010000111 $ #271 0# #272 1# b00000000000000000000000010001000 $ #273 0# #274 1# b00000000000000000000000010001001 $ #275 0# #276 1# b00000000000000000000000010001010 $ #277 0# #278 1# b00000000000000000000000010001011 $ #279 0# #280 1# b00000000000000000000000010001100 $ #281 0# #282 1# b00000000000000000000000010001101 $ #283 0# #284 1# b00000000000000000000000010001110 $ #285 0# #286 1# b00000000000000000000000010001111 $ #287 0# #288 1# b00000000000000000000000010010000 $ #289 0# #290 1# b00000000000000000000000010010001 $ #291 0# #292 1# b00000000000000000000000010010010 $ #293 0# #294 1# b00000000000000000000000010010011 $ #295 0# #296 1# b00000000000000000000000010010100 $ #297 0# #298 1# b00000000000000000000000010010101 $ #299 0# #300 1# b00000000000000000000000010010110 $ #301 0# #302 1# b00000000000000000000000010010111 $ #303 0# #304 1# b00000000000000000000000010011000 $ #305 0# #306 1# b00000000000000000000000010011001 $ #307 0# #308 1# b00000000000000000000000010011010 $ #309 0# #310 1# b00000000000000000000000010011011 $ #311 0# #312 1# b00000000000000000000000010011100 $ #313 0# #314 1# b00000000000000000000000010011101 $ #315 0# #316 1# b00000000000000000000000010011110 $ #317 0# #318 1# b00000000000000000000000010011111 $ #319 0# #320 1# b00000000000000000000000010100000 $ #321 0# #322 1# b00000000000000000000000010100001 $ #323 0# #324 1# b00000000000000000000000010100010 $ #325 0# #326 1# b00000000000000000000000010100011 $ #327 0# #328 1# b00000000000000000000000010100100 $ #329 0# #330 1# b00000000000000000000000010100101 $ #331 0# #332 1# b00000000000000000000000010100110 $ #333 0# #334 1# b00000000000000000000000010100111 $ #335 0# #336 1# b00000000000000000000000010101000 $ #337 0# #338 1# b00000000000000000000000010101001 $ #339 0# #340 1# b00000000000000000000000010101010 $ #341 0# #342 1# b00000000000000000000000010101011 $ #343 0# #344 1# b00000000000000000000000010101100 $ #345 0# #346 1# b00000000000000000000000010101101 $ #347 0# #348 1# b00000000000000000000000010101110 $ #349 0# #350 1# b00000000000000000000000010101111 $ #351 0# #352 1# b00000000000000000000000010110000 $ #353 0# #354 1# b00000000000000000000000010110001 $ #355 0# #356 1# b00000000000000000000000010110010 $ #357 0# #358 1# b00000000000000000000000010110011 $ #359 0# #360 1# b00000000000000000000000010110100 $ #361 0# #362 1# b00000000000000000000000010110101 $ #363 0# #364 1# b00000000000000000000000010110110 $ #365 0# #366 1# b00000000000000000000000010110111 $ #367 0# #368 1# b00000000000000000000000010111000 $ #369 0# #370 1# b00000000000000000000000010111001 $ #371 0# #372 1# b00000000000000000000000010111010 $ #373 0# #374 1# b00000000000000000000000010111011 $ #375 0# #376 1# b00000000000000000000000010111100 $ #377 0# #378 1# b00000000000000000000000010111101 $ #379 0# #380 1# b00000000000000000000000010111110 $ #381 0# #382 1# b00000000000000000000000010111111 $ #383 0# #384 1# b00000000000000000000000011000000 $ #385 0# #386 1# b00000000000000000000000011000001 $ #387 0# #388 1# b00000000000000000000000011000010 $ #389 0# #390 1# b00000000000000000000000011000011 $ #391 0# #392 1# b00000000000000000000000011000100 $ #393 0# #394 1# b00000000000000000000000011000101 $ #395 0# #396 1# b00000000000000000000000011000110 $ #397 0# #398 1# b00000000000000000000000011000111 $ #399 0# #400 1# b00000000000000000000000011001000 $ #401 0# #402 1# b00000000000000000000000011001001 $ #403 0# #404 1# b00000000000000000000000011001010 $ #405 0# #406 1# b00000000000000000000000011001011 $ #407 0# #408 1# b00000000000000000000000011001100 $ #409 0# #410 1# b00000000000000000000000011001101 $ #411 0# #412 1# b00000000000000000000000011001110 $ #413 0# #414 1# b00000000000000000000000011001111 $ #415 0# #416 1# b00000000000000000000000011010000 $ #417 0# #418 1# b00000000000000000000000011010001 $ #419 0# #420 1# b00000000000000000000000011010010 $ #421 0# #422 1# b00000000000000000000000011010011 $ #423 0# #424 1# b00000000000000000000000011010100 $ #425 0# #426 1# b00000000000000000000000011010101 $ #427 0# #428 1# b00000000000000000000000011010110 $ #429 0# #430 1# b00000000000000000000000011010111 $ #431 0# #432 1# b00000000000000000000000011011000 $ #433 0# #434 1# b00000000000000000000000011011001 $ #435 0# #436 1# b00000000000000000000000011011010 $ #437 0# #438 1# b00000000000000000000000011011011 $ #439 0# #440 1# b00000000000000000000000011011100 $ #441 0# #442 1# b00000000000000000000000011011101 $ #443 0# #444 1# b00000000000000000000000011011110 $ #445 0# #446 1# b00000000000000000000000011011111 $ #447 0# #448 1# b00000000000000000000000011100000 $ #449 0# #450 1# b00000000000000000000000011100001 $ #451 0# #452 1# b00000000000000000000000011100010 $ #453 0# #454 1# b00000000000000000000000011100011 $ #455 0# #456 1# b00000000000000000000000011100100 $ #457 0# #458 1# b00000000000000000000000011100101 $ #459 0# #460 1# b00000000000000000000000011100110 $ #461 0# #462 1# b00000000000000000000000011100111 $ #463 0# #464 1# b00000000000000000000000011101000 $ #465 0# #466 1# b00000000000000000000000011101001 $ #467 0# #468 1# b00000000000000000000000011101010 $ #469 0# #470 1# b00000000000000000000000011101011 $ #471 0# #472 1# b00000000000000000000000011101100 $ #473 0# #474 1# b00000000000000000000000011101101 $ #475 0# #476 1# b00000000000000000000000011101110 $ #477 0# #478 1# b00000000000000000000000011101111 $ #479 0# #480 1# b00000000000000000000000011110000 $ #481 0# #482 1# b00000000000000000000000011110001 $ #483 0# #484 1# b00000000000000000000000011110010 $ #485 0# #486 1# b00000000000000000000000011110011 $ #487 0# #488 1# b00000000000000000000000011110100 $ #489 0# #490 1# b00000000000000000000000011110101 $ #491 0# #492 1# b00000000000000000000000011110110 $ #493 0# #494 1# b00000000000000000000000011110111 $ #495 0# #496 1# b00000000000000000000000011111000 $ #497 0# #498 1# b00000000000000000000000011111001 $ #499 0# #500 1# b00000000000000000000000011111010 $ #501 0# #502 1# b00000000000000000000000011111011 $ #503 0# #504 1# b00000000000000000000000011111100 $ #505 0# #506 1# b00000000000000000000000011111101 $ #507 0# #508 1# b00000000000000000000000011111110 $ #509 0# #510 1# b00000000000000000000000011111111 $ #511 0# #512 1# b00000000000000000000000100000000 $ #513 0# #514 1# b00000000000000000000000100000001 $ #515 0# #516 1# b00000000000000000000000100000010 $ #517 0# #518 1# b00000000000000000000000100000011 $ #519 0# #520 1# b00000000000000000000000100000100 $ #521 0# #522 1# b00000000000000000000000100000101 $ #523 0# #524 1# b00000000000000000000000100000110 $ #525 0# #526 1# b00000000000000000000000100000111 $ #527 0# #528 1# b00000000000000000000000100001000 $ #529 0# #530 1# b00000000000000000000000100001001 $ #531 0# #532 1# b00000000000000000000000100001010 $ #533 0# #534 1# b00000000000000000000000100001011 $ #535 0# #536 1# b00000000000000000000000100001100 $ #537 0# #538 1# b00000000000000000000000100001101 $ #539 0# #540 1# b00000000000000000000000100001110 $ #541 0# #542 1# b00000000000000000000000100001111 $ #543 0# #544 1# b00000000000000000000000100010000 $ #545 0# #546 1# b00000000000000000000000100010001 $ #547 0# #548 1# b00000000000000000000000100010010 $ #549 0# #550 1# b00000000000000000000000100010011 $ #551 0# #552 1# b00000000000000000000000100010100 $ #553 0# #554 1# b00000000000000000000000100010101 $ #555 0# #556 1# b00000000000000000000000100010110 $ #557 0# #558 1# b00000000000000000000000100010111 $ #559 0# #560 1# b00000000000000000000000100011000 $ #561 0# #562 1# b00000000000000000000000100011001 $ #563 0# #564 1# b00000000000000000000000100011010 $ #565 0# #566 1# b00000000000000000000000100011011 $ #567 0# #568 1# b00000000000000000000000100011100 $ #569 0# #570 1# b00000000000000000000000100011101 $ #571 0# #572 1# b00000000000000000000000100011110 $ #573 0# #574 1# b00000000000000000000000100011111 $ #575 0# #576 1# b00000000000000000000000100100000 $ #577 0# #578 1# b00000000000000000000000100100001 $ #579 0# #580 1# b00000000000000000000000100100010 $ #581 0# #582 1# b00000000000000000000000100100011 $ #583 0# #584 1# b00000000000000000000000100100100 $ #585 0# #586 1# b00000000000000000000000100100101 $ #587 0# #588 1# b00000000000000000000000100100110 $ #589 0# #590 1# b00000000000000000000000100100111 $ #591 0# #592 1# b00000000000000000000000100101000 $ #593 0# #594 1# b00000000000000000000000100101001 $ #595 0# #596 1# b00000000000000000000000100101010 $ #597 0# #598 1# b00000000000000000000000100101011 $ #599 0# #600 1# b00000000000000000000000100101100 $ #601 0# #602 1# b00000000000000000000000100101101 $ #603 0# #604 1# b00000000000000000000000100101110 $ #605 0# #606 1# b00000000000000000000000100101111 $ #607 0# #608 1# b00000000000000000000000100110000 $ #609 0# #610 1# b00000000000000000000000100110001 $ #611 0# #612 1# b00000000000000000000000100110010 $ #613 0# #614 1# b00000000000000000000000100110011 $ #615 0# #616 1# b00000000000000000000000100110100 $ #617 0# #618 1# b00000000000000000000000100110101 $ #619 0# #620 1# b00000000000000000000000100110110 $ #621 0# #622 1# b00000000000000000000000100110111 $ #623 0# #624 1# b00000000000000000000000100111000 $ #625 0# #626 1# b00000000000000000000000100111001 $ #627 0# #628 1# b00000000000000000000000100111010 $ #629 0# #630 1# b00000000000000000000000100111011 $ #631 0# #632 1# b00000000000000000000000100111100 $ #633 0# #634 1# b00000000000000000000000100111101 $ #635 0# #636 1# b00000000000000000000000100111110 $ #637 0# #638 1# b00000000000000000000000100111111 $ #639 0# #640 1# b00000000000000000000000101000000 $ #641 0# #642 1# b00000000000000000000000101000001 $ #643 0# #644 1# b00000000000000000000000101000010 $ #645 0# #646 1# b00000000000000000000000101000011 $ #647 0# #648 1# b00000000000000000000000101000100 $ #649 0# #650 1# b00000000000000000000000101000101 $ #651 0# #652 1# b00000000000000000000000101000110 $ #653 0# #654 1# b00000000000000000000000101000111 $ #655 0# #656 1# b00000000000000000000000101001000 $ #657 0# #658 1# b00000000000000000000000101001001 $ #659 0# #660 1# b00000000000000000000000101001010 $ #661 0# #662 1# b00000000000000000000000101001011 $ #663 0# #664 1# b00000000000000000000000101001100 $ #665 0# #666 1# b00000000000000000000000101001101 $ #667 0# #668 1# b00000000000000000000000101001110 $ #669 0# #670 1# b00000000000000000000000101001111 $ #671 0# #672 1# b00000000000000000000000101010000 $ #673 0# #674 1# b00000000000000000000000101010001 $ #675 0# #676 1# b00000000000000000000000101010010 $ #677 0# #678 1# b00000000000000000000000101010011 $ #679 0# #680 1# b00000000000000000000000101010100 $ #681 0# #682 1# b00000000000000000000000101010101 $ #683 0# #684 1# b00000000000000000000000101010110 $ #685 0# #686 1# b00000000000000000000000101010111 $ #687 0# #688 1# b00000000000000000000000101011000 $ #689 0# #690 1# b00000000000000000000000101011001 $ #691 0# #692 1# b00000000000000000000000101011010 $ #693 0# #694 1# b00000000000000000000000101011011 $ #695 0# #696 1# b00000000000000000000000101011100 $ #697 0# #698 1# b00000000000000000000000101011101 $ #699 0# #700 1# b00000000000000000000000101011110 $ #701 0# #702 1# b00000000000000000000000101011111 $ #703 0# #704 1# b00000000000000000000000101100000 $ #705 0# #706 1# b00000000000000000000000101100001 $ #707 0# #708 1# b00000000000000000000000101100010 $ #709 0# #710 1# b00000000000000000000000101100011 $ #711 0# #712 1# b00000000000000000000000101100100 $ #713 0# #714 1# b00000000000000000000000101100101 $ #715 0# #716 1# b00000000000000000000000101100110 $ #717 0# #718 1# b00000000000000000000000101100111 $ #719 0# #720 1# b00000000000000000000000101101000 $ #721 0# #722 1# b00000000000000000000000101101001 $ #723 0# #724 1# b00000000000000000000000101101010 $ #725 0# #726 1# b00000000000000000000000101101011 $ #727 0# #728 1# b00000000000000000000000101101100 $ #729 0# #730 1# b00000000000000000000000101101101 $ #731 0# #732 1# b00000000000000000000000101101110 $ #733 0# #734 1# b00000000000000000000000101101111 $ #735 0# #736 1# b00000000000000000000000101110000 $ #737 0# #738 1# b00000000000000000000000101110001 $ #739 0# #740 1# b00000000000000000000000101110010 $ #741 0# #742 1# b00000000000000000000000101110011 $ #743 0# #744 1# b00000000000000000000000101110100 $ #745 0# #746 1# b00000000000000000000000101110101 $ #747 0# #748 1# b00000000000000000000000101110110 $ #749 0# #750 1# b00000000000000000000000101110111 $ #751 0# #752 1# b00000000000000000000000101111000 $ #753 0# #754 1# b00000000000000000000000101111001 $ #755 0# #756 1# b00000000000000000000000101111010 $ #757 0# #758 1# b00000000000000000000000101111011 $ #759 0# #760 1# b00000000000000000000000101111100 $ #761 0# #762 1# b00000000000000000000000101111101 $ #763 0# #764 1# b00000000000000000000000101111110 $ #765 0# #766 1# b00000000000000000000000101111111 $ #767 0# #768 1# b00000000000000000000000110000000 $ #769 0# #770 1# b00000000000000000000000110000001 $ #771 0# #772 1# b00000000000000000000000110000010 $ #773 0# #774 1# b00000000000000000000000110000011 $ #775 0# #776 1# b00000000000000000000000110000100 $ #777 0# #778 1# b00000000000000000000000110000101 $ #779 0# #780 1# b00000000000000000000000110000110 $ #781 0# #782 1# b00000000000000000000000110000111 $ #783 0# #784 1# b00000000000000000000000110001000 $ #785 0# #786 1# b00000000000000000000000110001001 $ #787 0# #788 1# b00000000000000000000000110001010 $ #789 0# #790 1# b00000000000000000000000110001011 $ #791 0# #792 1# b00000000000000000000000110001100 $ #793 0# #794 1# b00000000000000000000000110001101 $ #795 0# #796 1# b00000000000000000000000110001110 $ #797 0# #798 1# b00000000000000000000000110001111 $ #799 0# #800 1# b00000000000000000000000110010000 $ #801 0# #802 1# b00000000000000000000000110010001 $ #803 0# #804 1# b00000000000000000000000110010010 $ #805 0# #806 1# b00000000000000000000000110010011 $ #807 0# #808 1# b00000000000000000000000110010100 $ #809 0# #810 1# b00000000000000000000000110010101 $ #811 0# #812 1# b00000000000000000000000110010110 $ #813 0# #814 1# b00000000000000000000000110010111 $ #815 0# #816 1# b00000000000000000000000110011000 $ #817 0# #818 1# b00000000000000000000000110011001 $ #819 0# #820 1# b00000000000000000000000110011010 $ #821 0# #822 1# b00000000000000000000000110011011 $ #823 0# #824 1# b00000000000000000000000110011100 $ #825 0# #826 1# b00000000000000000000000110011101 $ #827 0# #828 1# b00000000000000000000000110011110 $ #829 0# #830 1# b00000000000000000000000110011111 $ #831 0# #832 1# b00000000000000000000000110100000 $ #833 0# #834 1# b00000000000000000000000110100001 $ #835 0# #836 1# b00000000000000000000000110100010 $ #837 0# #838 1# b00000000000000000000000110100011 $ #839 0# #840 1# b00000000000000000000000110100100 $ #841 0# #842 1# b00000000000000000000000110100101 $ #843 0# #844 1# b00000000000000000000000110100110 $ #845 0# #846 1# b00000000000000000000000110100111 $ #847 0# #848 1# b00000000000000000000000110101000 $ #849 0# #850 1# b00000000000000000000000110101001 $ #851 0# #852 1# b00000000000000000000000110101010 $ #853 0# #854 1# b00000000000000000000000110101011 $ #855 0# #856 1# b00000000000000000000000110101100 $ #857 0# #858 1# b00000000000000000000000110101101 $ #859 0# #860 1# b00000000000000000000000110101110 $ #861 0# #862 1# b00000000000000000000000110101111 $ #863 0# #864 1# b00000000000000000000000110110000 $ #865 0# #866 1# b00000000000000000000000110110001 $ #867 0# #868 1# b00000000000000000000000110110010 $ #869 0# #870 1# b00000000000000000000000110110011 $ #871 0# #872 1# b00000000000000000000000110110100 $ #873 0# #874 1# b00000000000000000000000110110101 $ #875 0# #876 1# b00000000000000000000000110110110 $ #877 0# #878 1# b00000000000000000000000110110111 $ #879 0# #880 1# b00000000000000000000000110111000 $ #881 0# #882 1# b00000000000000000000000110111001 $ #883 0# #884 1# b00000000000000000000000110111010 $ #885 0# #886 1# b00000000000000000000000110111011 $ #887 0# #888 1# b00000000000000000000000110111100 $ #889 0# #890 1# b00000000000000000000000110111101 $ #891 0# #892 1# b00000000000000000000000110111110 $ #893 0# #894 1# b00000000000000000000000110111111 $ #895 0# #896 1# b00000000000000000000000111000000 $ #897 0# #898 1# b00000000000000000000000111000001 $ #899 0# #900 1# b00000000000000000000000111000010 $ #901 0# #902 1# b00000000000000000000000111000011 $ #903 0# #904 1# b00000000000000000000000111000100 $ #905 0# #906 1# b00000000000000000000000111000101 $ #907 0# #908 1# b00000000000000000000000111000110 $ #909 0# #910 1# b00000000000000000000000111000111 $ #911 0# #912 1# b00000000000000000000000111001000 $ #913 0# #914 1# b00000000000000000000000111001001 $ #915 0# #916 1# b00000000000000000000000111001010 $ #917 0# #918 1# b00000000000000000000000111001011 $ #919 0# #920 1# b00000000000000000000000111001100 $ #921 0# #922 1# b00000000000000000000000111001101 $ #923 0# #924 1# b00000000000000000000000111001110 $ #925 0# #926 1# b00000000000000000000000111001111 $ #927 0# #928 1# b00000000000000000000000111010000 $ #929 0# #930 1# b00000000000000000000000111010001 $ #931 0# #932 1# b00000000000000000000000111010010 $ #933 0# #934 1# b00000000000000000000000111010011 $ #935 0# #936 1# b00000000000000000000000111010100 $ #937 0# #938 1# b00000000000000000000000111010101 $ #939 0# #940 1# b00000000000000000000000111010110 $ #941 0# #942 1# b00000000000000000000000111010111 $ #943 0# #944 1# b00000000000000000000000111011000 $ #945 0# #946 1# b00000000000000000000000111011001 $ #947 0# #948 1# b00000000000000000000000111011010 $ #949 0# #950 1# b00000000000000000000000111011011 $ #951 0# #952 1# b00000000000000000000000111011100 $ #953 0# #954 1# b00000000000000000000000111011101 $ #955 0# #956 1# b00000000000000000000000111011110 $ #957 0# #958 1# b00000000000000000000000111011111 $ #959 0# #960 1# b00000000000000000000000111100000 $ #961 0# #962 1# b00000000000000000000000111100001 $ #963 0# #964 1# b00000000000000000000000111100010 $ #965 0# #966 1# b00000000000000000000000111100011 $ #967 0# #968 1# b00000000000000000000000111100100 $ #969 0# #970 1# b00000000000000000000000111100101 $ #971 0# #972 1# b00000000000000000000000111100110 $ #973 0# #974 1# b00000000000000000000000111100111 $ #975 0# #976 1# b00000000000000000000000111101000 $ #977 0# #978 1# b00000000000000000000000111101001 $ #979 0# #980 1# b00000000000000000000000111101010 $ #981 0# #982 1# b00000000000000000000000111101011 $ #983 0# #984 1# b00000000000000000000000111101100 $ #985 0# #986 1# b00000000000000000000000111101101 $ #987 0# #988 1# b00000000000000000000000111101110 $ #989 0# #990 1# b00000000000000000000000111101111 $ #991 0# #992 1# b00000000000000000000000111110000 $ #993 0# #994 1# b00000000000000000000000111110001 $ #995 0# #996 1# b00000000000000000000000111110010 $ #997 0# #998 1# b00000000000000000000000111110011 $ #999 0# #1000 1# b00000000000000000000000111110100 $ #1001 0# #1002 1# b00000000000000000000000111110101 $ #1003 0# #1004 1# b00000000000000000000000111110110 $ #1005 0# #1006 1# b00000000000000000000000111110111 $ #1007 0# #1008 1# b00000000000000000000000111111000 $ #1009 0# #1010 1# b00000000000000000000000111111001 $ #1011 0# #1012 1# b00000000000000000000000111111010 $ #1013 0# #1014 1# b00000000000000000000000111111011 $ #1015 0# #1016 1# b00000000000000000000000111111100 $ #1017 0# #1018 1# b00000000000000000000000111111101 $ #1019 0# #1020 1# b00000000000000000000000111111110 $ #1021 0# #1022 1# b00000000000000000000000111111111 $ #1023 0# #1024 1# b00000000000000000000001000000000 $ #1025 0# #1026 1# b00000000000000000000001000000001 $ #1027 0# #1028 1# b00000000000000000000001000000010 $ #1029 0# #1030 1# b00000000000000000000001000000011 $ #1031 0# #1032 1# b00000000000000000000001000000100 $ #1033 0# #1034 1# b00000000000000000000001000000101 $ #1035 0# #1036 1# b00000000000000000000001000000110 $ #1037 0# #1038 1# b00000000000000000000001000000111 $ #1039 0# #1040 1# b00000000000000000000001000001000 $ #1041 0# #1042 1# b00000000000000000000001000001001 $ #1043 0# #1044 1# b00000000000000000000001000001010 $ #1045 0# #1046 1# b00000000000000000000001000001011 $ #1047 0# #1048 1# b00000000000000000000001000001100 $ #1049 0# #1050 1# b00000000000000000000001000001101 $ #1051 0# #1052 1# b00000000000000000000001000001110 $ #1053 0# #1054 1# b00000000000000000000001000001111 $ #1055 0# #1056 1# b00000000000000000000001000010000 $ #1057 0# #1058 1# b00000000000000000000001000010001 $ #1059 0# #1060 1# b00000000000000000000001000010010 $ #1061 0# #1062 1# b00000000000000000000001000010011 $ #1063 0# #1064 1# b00000000000000000000001000010100 $ #1065 0# #1066 1# b00000000000000000000001000010101 $ #1067 0# #1068 1# b00000000000000000000001000010110 $ #1069 0# #1070 1# b00000000000000000000001000010111 $ #1071 0# #1072 1# b00000000000000000000001000011000 $ #1073 0# #1074 1# b00000000000000000000001000011001 $ #1075 0# #1076 1# b00000000000000000000001000011010 $ #1077 0# #1078 1# b00000000000000000000001000011011 $ #1079 0# #1080 1# b00000000000000000000001000011100 $ #1081 0# #1082 1# b00000000000000000000001000011101 $ #1083 0# #1084 1# b00000000000000000000001000011110 $ #1085 0# #1086 1# b00000000000000000000001000011111 $ #1087 0# #1088 1# b00000000000000000000001000100000 $ #1089 0# #1090 1# b00000000000000000000001000100001 $ #1091 0# #1092 1# b00000000000000000000001000100010 $ #1093 0# #1094 1# b00000000000000000000001000100011 $ #1095 0# #1096 1# b00000000000000000000001000100100 $ #1097 0# #1098 1# b00000000000000000000001000100101 $ #1099 0# #1100 1# b00000000000000000000001000100110 $ #1101 0# #1102 1# b00000000000000000000001000100111 $ #1103 0# #1104 1# b00000000000000000000001000101000 $ #1105 0# #1106 1# b00000000000000000000001000101001 $ #1107 0# #1108 1# b00000000000000000000001000101010 $ #1109 0# #1110 1# b00000000000000000000001000101011 $ #1111 0# #1112 1# b00000000000000000000001000101100 $ #1113 0# #1114 1# b00000000000000000000001000101101 $ #1115 0# #1116 1# b00000000000000000000001000101110 $ #1117 0# #1118 1# b00000000000000000000001000101111 $ #1119 0# #1120 1# b00000000000000000000001000110000 $ #1121 0# #1122 1# b00000000000000000000001000110001 $ #1123 0# #1124 1# b00000000000000000000001000110010 $ #1125 0# #1126 1# b00000000000000000000001000110011 $ #1127 0# #1128 1# b00000000000000000000001000110100 $ #1129 0# #1130 1# b00000000000000000000001000110101 $ #1131 0# #1132 1# b00000000000000000000001000110110 $ #1133 0# #1134 1# b00000000000000000000001000110111 $ #1135 0# #1136 1# b00000000000000000000001000111000 $ #1137 0# #1138 1# b00000000000000000000001000111001 $ #1139 0# #1140 1# b00000000000000000000001000111010 $ #1141 0# #1142 1# b00000000000000000000001000111011 $ #1143 0# #1144 1# b00000000000000000000001000111100 $ #1145 0# #1146 1# b00000000000000000000001000111101 $ #1147 0# #1148 1# b00000000000000000000001000111110 $ #1149 0# #1150 1# b00000000000000000000001000111111 $ #1151 0# #1152 1# b00000000000000000000001001000000 $ #1153 0# #1154 1# b00000000000000000000001001000001 $ #1155 0# #1156 1# b00000000000000000000001001000010 $ #1157 0# #1158 1# b00000000000000000000001001000011 $ #1159 0# #1160 1# b00000000000000000000001001000100 $ #1161 0# #1162 1# b00000000000000000000001001000101 $ #1163 0# #1164 1# b00000000000000000000001001000110 $ #1165 0# #1166 1# b00000000000000000000001001000111 $ #1167 0# #1168 1# b00000000000000000000001001001000 $ #1169 0# #1170 1# b00000000000000000000001001001001 $ #1171 0# #1172 1# b00000000000000000000001001001010 $ #1173 0# #1174 1# b00000000000000000000001001001011 $ #1175 0# #1176 1# b00000000000000000000001001001100 $ #1177 0# #1178 1# b00000000000000000000001001001101 $ #1179 0# #1180 1# b00000000000000000000001001001110 $ #1181 0# #1182 1# b00000000000000000000001001001111 $ #1183 0# #1184 1# b00000000000000000000001001010000 $ #1185 0# #1186 1# b00000000000000000000001001010001 $ #1187 0# #1188 1# b00000000000000000000001001010010 $ #1189 0# #1190 1# b00000000000000000000001001010011 $ #1191 0# #1192 1# b00000000000000000000001001010100 $ #1193 0# #1194 1# b00000000000000000000001001010101 $ #1195 0# #1196 1# b00000000000000000000001001010110 $ #1197 0# #1198 1# b00000000000000000000001001010111 $ #1199 0# #1200 1# b00000000000000000000001001011000 $ #1201 0# #1202 1# b00000000000000000000001001011001 $ #1203 0# #1204 1# b00000000000000000000001001011010 $ #1205 0# #1206 1# b00000000000000000000001001011011 $ #1207 0# #1208 1# b00000000000000000000001001011100 $ #1209 0# #1210 1# b00000000000000000000001001011101 $ #1211 0# #1212 1# b00000000000000000000001001011110 $ #1213 0# #1214 1# b00000000000000000000001001011111 $ #1215 0# #1216 1# b00000000000000000000001001100000 $ #1217 0# #1218 1# b00000000000000000000001001100001 $ #1219 0# #1220 1# b00000000000000000000001001100010 $ #1221 0# #1222 1# b00000000000000000000001001100011 $ #1223 0# #1224 1# b00000000000000000000001001100100 $ #1225 0# #1226 1# b00000000000000000000001001100101 $ #1227 0# #1228 1# b00000000000000000000001001100110 $ #1229 0# #1230 1# b00000000000000000000001001100111 $ #1231 0# #1232 1# b00000000000000000000001001101000 $ #1233 0# #1234 1# b00000000000000000000001001101001 $ #1235 0# #1236 1# b00000000000000000000001001101010 $ #1237 0# #1238 1# b00000000000000000000001001101011 $ #1239 0# #1240 1# b00000000000000000000001001101100 $ #1241 0# #1242 1# b00000000000000000000001001101101 $ #1243 0# #1244 1# b00000000000000000000001001101110 $ #1245 0# #1246 1# b00000000000000000000001001101111 $ #1247 0# #1248 1# b00000000000000000000001001110000 $ #1249 0# #1250 1# b00000000000000000000001001110001 $ #1251 0# #1252 1# b00000000000000000000001001110010 $ #1253 0# #1254 1# b00000000000000000000001001110011 $ #1255 0# #1256 1# b00000000000000000000001001110100 $ #1257 0# #1258 1# b00000000000000000000001001110101 $ #1259 0# #1260 1# b00000000000000000000001001110110 $ #1261 0# #1262 1# b00000000000000000000001001110111 $ #1263 0# #1264 1# b00000000000000000000001001111000 $ #1265 0# #1266 1# b00000000000000000000001001111001 $ #1267 0# #1268 1# b00000000000000000000001001111010 $ #1269 0# #1270 1# b00000000000000000000001001111011 $ #1271 0# #1272 1# b00000000000000000000001001111100 $ #1273 0# #1274 1# b00000000000000000000001001111101 $ #1275 0# #1276 1# b00000000000000000000001001111110 $ #1277 0# #1278 1# b00000000000000000000001001111111 $ #1279 0# #1280 1# b00000000000000000000001010000000 $ #1281 0# #1282 1# b00000000000000000000001010000001 $ #1283 0# #1284 1# b00000000000000000000001010000010 $ #1285 0# #1286 1# b00000000000000000000001010000011 $ #1287 0# #1288 1# b00000000000000000000001010000100 $ #1289 0# #1290 1# b00000000000000000000001010000101 $ #1291 0# #1292 1# b00000000000000000000001010000110 $ #1293 0# #1294 1# b00000000000000000000001010000111 $ #1295 0# #1296 1# b00000000000000000000001010001000 $ #1297 0# #1298 1# b00000000000000000000001010001001 $ #1299 0# #1300 1# b00000000000000000000001010001010 $ #1301 0# #1302 1# b00000000000000000000001010001011 $ #1303 0# #1304 1# b00000000000000000000001010001100 $ #1305 0# #1306 1# b00000000000000000000001010001101 $ #1307 0# #1308 1# b00000000000000000000001010001110 $ #1309 0# #1310 1# b00000000000000000000001010001111 $ #1311 0# #1312 1# b00000000000000000000001010010000 $ #1313 0# #1314 1# b00000000000000000000001010010001 $ #1315 0# #1316 1# b00000000000000000000001010010010 $ #1317 0# #1318 1# b00000000000000000000001010010011 $ #1319 0# #1320 1# b00000000000000000000001010010100 $ #1321 0# #1322 1# b00000000000000000000001010010101 $ #1323 0# #1324 1# b00000000000000000000001010010110 $ #1325 0# #1326 1# b00000000000000000000001010010111 $ #1327 0# #1328 1# b00000000000000000000001010011000 $ #1329 0# #1330 1# b00000000000000000000001010011001 $ #1331 0# #1332 1# b00000000000000000000001010011010 $ #1333 0# #1334 1# b00000000000000000000001010011011 $ #1335 0# #1336 1# b00000000000000000000001010011100 $ #1337 0# #1338 1# b00000000000000000000001010011101 $ #1339 0# #1340 1# b00000000000000000000001010011110 $ #1341 0# #1342 1# b00000000000000000000001010011111 $ #1343 0# #1344 1# b00000000000000000000001010100000 $ #1345 0# #1346 1# b00000000000000000000001010100001 $ #1347 0# #1348 1# b00000000000000000000001010100010 $ #1349 0# #1350 1# b00000000000000000000001010100011 $ #1351 0# #1352 1# b00000000000000000000001010100100 $ #1353 0# #1354 1# b00000000000000000000001010100101 $ #1355 0# #1356 1# b00000000000000000000001010100110 $ #1357 0# #1358 1# b00000000000000000000001010100111 $ #1359 0# #1360 1# b00000000000000000000001010101000 $ #1361 0# #1362 1# b00000000000000000000001010101001 $ #1363 0# #1364 1# b00000000000000000000001010101010 $ #1365 0# #1366 1# b00000000000000000000001010101011 $ #1367 0# #1368 1# b00000000000000000000001010101100 $ #1369 0# #1370 1# b00000000000000000000001010101101 $ #1371 0# #1372 1# b00000000000000000000001010101110 $ #1373 0# #1374 1# b00000000000000000000001010101111 $ #1375 0# #1376 1# b00000000000000000000001010110000 $ #1377 0# #1378 1# b00000000000000000000001010110001 $ #1379 0# #1380 1# b00000000000000000000001010110010 $ #1381 0# #1382 1# b00000000000000000000001010110011 $ #1383 0# #1384 1# b00000000000000000000001010110100 $ #1385 0# #1386 1# b00000000000000000000001010110101 $ #1387 0# #1388 1# b00000000000000000000001010110110 $ #1389 0# #1390 1# b00000000000000000000001010110111 $ #1391 0# #1392 1# b00000000000000000000001010111000 $ #1393 0# #1394 1# b00000000000000000000001010111001 $ #1395 0# #1396 1# b00000000000000000000001010111010 $ #1397 0# #1398 1# b00000000000000000000001010111011 $ #1399 0# #1400 1# b00000000000000000000001010111100 $ #1401 0# #1402 1# b00000000000000000000001010111101 $ #1403 0# #1404 1# b00000000000000000000001010111110 $ #1405 0# #1406 1# b00000000000000000000001010111111 $ #1407 0# #1408 1# b00000000000000000000001011000000 $ #1409 0# #1410 1# b00000000000000000000001011000001 $ #1411 0# #1412 1# b00000000000000000000001011000010 $ #1413 0# #1414 1# b00000000000000000000001011000011 $ #1415 0# #1416 1# b00000000000000000000001011000100 $ #1417 0# #1418 1# b00000000000000000000001011000101 $ #1419 0# #1420 1# b00000000000000000000001011000110 $ #1421 0# #1422 1# b00000000000000000000001011000111 $ #1423 0# #1424 1# b00000000000000000000001011001000 $ #1425 0# #1426 1# b00000000000000000000001011001001 $ #1427 0# #1428 1# b00000000000000000000001011001010 $ #1429 0# #1430 1# b00000000000000000000001011001011 $ #1431 0# #1432 1# b00000000000000000000001011001100 $ #1433 0# #1434 1# b00000000000000000000001011001101 $ #1435 0# #1436 1# b00000000000000000000001011001110 $ #1437 0# #1438 1# b00000000000000000000001011001111 $ #1439 0# #1440 1# b00000000000000000000001011010000 $ #1441 0# #1442 1# b00000000000000000000001011010001 $ #1443 0# #1444 1# b00000000000000000000001011010010 $ #1445 0# #1446 1# b00000000000000000000001011010011 $ #1447 0# #1448 1# b00000000000000000000001011010100 $ #1449 0# #1450 1# b00000000000000000000001011010101 $ #1451 0# #1452 1# b00000000000000000000001011010110 $ #1453 0# #1454 1# b00000000000000000000001011010111 $ #1455 0# #1456 1# b00000000000000000000001011011000 $ #1457 0# #1458 1# b00000000000000000000001011011001 $ #1459 0# #1460 1# b00000000000000000000001011011010 $ #1461 0# #1462 1# b00000000000000000000001011011011 $ #1463 0# #1464 1# b00000000000000000000001011011100 $ #1465 0# #1466 1# b00000000000000000000001011011101 $ #1467 0# #1468 1# b00000000000000000000001011011110 $ #1469 0# #1470 1# b00000000000000000000001011011111 $ #1471 0# #1472 1# b00000000000000000000001011100000 $ #1473 0# #1474 1# b00000000000000000000001011100001 $ #1475 0# #1476 1# b00000000000000000000001011100010 $ #1477 0# #1478 1# b00000000000000000000001011100011 $ #1479 0# #1480 1# b00000000000000000000001011100100 $ #1481 0# #1482 1# b00000000000000000000001011100101 $ #1483 0# #1484 1# b00000000000000000000001011100110 $ #1485 0# #1486 1# b00000000000000000000001011100111 $ #1487 0# #1488 1# b00000000000000000000001011101000 $ #1489 0# #1490 1# b00000000000000000000001011101001 $ #1491 0# #1492 1# b00000000000000000000001011101010 $ #1493 0# #1494 1# b00000000000000000000001011101011 $ #1495 0# #1496 1# b00000000000000000000001011101100 $ #1497 0# #1498 1# b00000000000000000000001011101101 $ #1499 0# #1500 1# b00000000000000000000001011101110 $ #1501 0# #1502 1# b00000000000000000000001011101111 $ #1503 0# #1504 1# b00000000000000000000001011110000 $ #1505 0# #1506 1# b00000000000000000000001011110001 $ #1507 0# #1508 1# b00000000000000000000001011110010 $ #1509 0# #1510 1# b00000000000000000000001011110011 $ #1511 0# #1512 1# b00000000000000000000001011110100 $ #1513 0# #1514 1# b00000000000000000000001011110101 $ #1515 0# #1516 1# b00000000000000000000001011110110 $ #1517 0# #1518 1# b00000000000000000000001011110111 $ #1519 0# #1520 1# b00000000000000000000001011111000 $ #1521 0# #1522 1# b00000000000000000000001011111001 $ #1523 0# #1524 1# b00000000000000000000001011111010 $ #1525 0# #1526 1# b00000000000000000000001011111011 $ #1527 0# #1528 1# b00000000000000000000001011111100 $ #1529 0# #1530 1# b00000000000000000000001011111101 $ #1531 0# #1532 1# b00000000000000000000001011111110 $ #1533 0# #1534 1# b00000000000000000000001011111111 $ #1535 0# #1536 1# b00000000000000000000001100000000 $ #1537 0# #1538 1# b00000000000000000000001100000001 $ #1539 0# #1540 1# b00000000000000000000001100000010 $ #1541 0# #1542 1# b00000000000000000000001100000011 $ #1543 0# #1544 1# b00000000000000000000001100000100 $ #1545 0# #1546 1# b00000000000000000000001100000101 $ #1547 0# #1548 1# b00000000000000000000001100000110 $ #1549 0# #1550 1# b00000000000000000000001100000111 $ #1551 0# #1552 1# b00000000000000000000001100001000 $ #1553 0# #1554 1# b00000000000000000000001100001001 $ #1555 0# #1556 1# b00000000000000000000001100001010 $ #1557 0# #1558 1# b00000000000000000000001100001011 $ #1559 0# #1560 1# b00000000000000000000001100001100 $ #1561 0# #1562 1# b00000000000000000000001100001101 $ #1563 0# #1564 1# b00000000000000000000001100001110 $ #1565 0# #1566 1# b00000000000000000000001100001111 $ #1567 0# #1568 1# b00000000000000000000001100010000 $ #1569 0# #1570 1# b00000000000000000000001100010001 $ #1571 0# #1572 1# b00000000000000000000001100010010 $ #1573 0# #1574 1# b00000000000000000000001100010011 $ #1575 0# #1576 1# b00000000000000000000001100010100 $ #1577 0# #1578 1# b00000000000000000000001100010101 $ #1579 0# #1580 1# b00000000000000000000001100010110 $ #1581 0# #1582 1# b00000000000000000000001100010111 $ #1583 0# #1584 1# b00000000000000000000001100011000 $ #1585 0# #1586 1# b00000000000000000000001100011001 $ #1587 0# #1588 1# b00000000000000000000001100011010 $ #1589 0# #1590 1# b00000000000000000000001100011011 $ #1591 0# #1592 1# b00000000000000000000001100011100 $ #1593 0# #1594 1# b00000000000000000000001100011101 $ #1595 0# #1596 1# b00000000000000000000001100011110 $ #1597 0# #1598 1# b00000000000000000000001100011111 $ #1599 0# #1600 1# b00000000000000000000001100100000 $ #1601 0# #1602 1# b00000000000000000000001100100001 $ #1603 0# #1604 1# b00000000000000000000001100100010 $ #1605 0# #1606 1# b00000000000000000000001100100011 $ #1607 0# #1608 1# b00000000000000000000001100100100 $ #1609 0# #1610 1# b00000000000000000000001100100101 $ #1611 0# #1612 1# b00000000000000000000001100100110 $ #1613 0# #1614 1# b00000000000000000000001100100111 $ #1615 0# #1616 1# b00000000000000000000001100101000 $ #1617 0# #1618 1# b00000000000000000000001100101001 $ #1619 0# #1620 1# b00000000000000000000001100101010 $ #1621 0# #1622 1# b00000000000000000000001100101011 $ #1623 0# #1624 1# b00000000000000000000001100101100 $ #1625 0# #1626 1# b00000000000000000000001100101101 $ #1627 0# #1628 1# b00000000000000000000001100101110 $ #1629 0# #1630 1# b00000000000000000000001100101111 $ #1631 0# #1632 1# b00000000000000000000001100110000 $ #1633 0# #1634 1# b00000000000000000000001100110001 $ #1635 0# #1636 1# b00000000000000000000001100110010 $ #1637 0# #1638 1# b00000000000000000000001100110011 $ #1639 0# #1640 1# b00000000000000000000001100110100 $ #1641 0# #1642 1# b00000000000000000000001100110101 $ #1643 0# #1644 1# b00000000000000000000001100110110 $ #1645 0# #1646 1# b00000000000000000000001100110111 $ #1647 0# #1648 1# b00000000000000000000001100111000 $ #1649 0# #1650 1# b00000000000000000000001100111001 $ #1651 0# #1652 1# b00000000000000000000001100111010 $ #1653 0# #1654 1# b00000000000000000000001100111011 $ #1655 0# #1656 1# b00000000000000000000001100111100 $ #1657 0# #1658 1# b00000000000000000000001100111101 $ #1659 0# #1660 1# b00000000000000000000001100111110 $ #1661 0# #1662 1# b00000000000000000000001100111111 $ #1663 0# #1664 1# b00000000000000000000001101000000 $ #1665 0# #1666 1# b00000000000000000000001101000001 $ #1667 0# #1668 1# b00000000000000000000001101000010 $ #1669 0# #1670 1# b00000000000000000000001101000011 $ #1671 0# #1672 1# b00000000000000000000001101000100 $ #1673 0# #1674 1# b00000000000000000000001101000101 $ #1675 0# #1676 1# b00000000000000000000001101000110 $ #1677 0# #1678 1# b00000000000000000000001101000111 $ #1679 0# #1680 1# b00000000000000000000001101001000 $ #1681 0# #1682 1# b00000000000000000000001101001001 $ #1683 0# #1684 1# b00000000000000000000001101001010 $ #1685 0# #1686 1# b00000000000000000000001101001011 $ #1687 0# #1688 1# b00000000000000000000001101001100 $ #1689 0# #1690 1# b00000000000000000000001101001101 $ #1691 0# #1692 1# b00000000000000000000001101001110 $ #1693 0# #1694 1# b00000000000000000000001101001111 $ #1695 0# #1696 1# b00000000000000000000001101010000 $ #1697 0# #1698 1# b00000000000000000000001101010001 $ #1699 0# #1700 1# b00000000000000000000001101010010 $ #1701 0# #1702 1# b00000000000000000000001101010011 $ #1703 0# #1704 1# b00000000000000000000001101010100 $ #1705 0# #1706 1# b00000000000000000000001101010101 $ #1707 0# #1708 1# b00000000000000000000001101010110 $ #1709 0# #1710 1# b00000000000000000000001101010111 $ #1711 0# #1712 1# b00000000000000000000001101011000 $ #1713 0# #1714 1# b00000000000000000000001101011001 $ #1715 0# #1716 1# b00000000000000000000001101011010 $ #1717 0# #1718 1# b00000000000000000000001101011011 $ #1719 0# #1720 1# b00000000000000000000001101011100 $ #1721 0# #1722 1# b00000000000000000000001101011101 $ #1723 0# #1724 1# b00000000000000000000001101011110 $ #1725 0# #1726 1# b00000000000000000000001101011111 $ #1727 0# #1728 1# b00000000000000000000001101100000 $ #1729 0# #1730 1# b00000000000000000000001101100001 $ #1731 0# #1732 1# b00000000000000000000001101100010 $ #1733 0# #1734 1# b00000000000000000000001101100011 $ #1735 0# #1736 1# b00000000000000000000001101100100 $ #1737 0# #1738 1# b00000000000000000000001101100101 $ #1739 0# #1740 1# b00000000000000000000001101100110 $ #1741 0# #1742 1# b00000000000000000000001101100111 $ #1743 0# #1744 1# b00000000000000000000001101101000 $ #1745 0# #1746 1# b00000000000000000000001101101001 $ #1747 0# #1748 1# b00000000000000000000001101101010 $ #1749 0# #1750 1# b00000000000000000000001101101011 $ #1751 0# #1752 1# b00000000000000000000001101101100 $ #1753 0# #1754 1# b00000000000000000000001101101101 $ #1755 0# #1756 1# b00000000000000000000001101101110 $ #1757 0# #1758 1# b00000000000000000000001101101111 $ #1759 0# #1760 1# b00000000000000000000001101110000 $ #1761 0# #1762 1# b00000000000000000000001101110001 $ #1763 0# #1764 1# b00000000000000000000001101110010 $ #1765 0# #1766 1# b00000000000000000000001101110011 $ #1767 0# #1768 1# b00000000000000000000001101110100 $ #1769 0# #1770 1# b00000000000000000000001101110101 $ #1771 0# #1772 1# b00000000000000000000001101110110 $ #1773 0# #1774 1# b00000000000000000000001101110111 $ #1775 0# #1776 1# b00000000000000000000001101111000 $ #1777 0# #1778 1# b00000000000000000000001101111001 $ #1779 0# #1780 1# b00000000000000000000001101111010 $ #1781 0# #1782 1# b00000000000000000000001101111011 $ #1783 0# #1784 1# b00000000000000000000001101111100 $ #1785 0# #1786 1# b00000000000000000000001101111101 $ #1787 0# #1788 1# b00000000000000000000001101111110 $ #1789 0# #1790 1# b00000000000000000000001101111111 $ #1791 0# #1792 1# b00000000000000000000001110000000 $ #1793 0# #1794 1# b00000000000000000000001110000001 $ #1795 0# #1796 1# b00000000000000000000001110000010 $ #1797 0# #1798 1# b00000000000000000000001110000011 $ #1799 0# #1800 1# b00000000000000000000001110000100 $ #1801 0# #1802 1# b00000000000000000000001110000101 $ #1803 0# #1804 1# b00000000000000000000001110000110 $ #1805 0# #1806 1# b00000000000000000000001110000111 $ #1807 0# #1808 1# b00000000000000000000001110001000 $ #1809 0# #1810 1# b00000000000000000000001110001001 $ #1811 0# #1812 1# b00000000000000000000001110001010 $ #1813 0# #1814 1# b00000000000000000000001110001011 $ #1815 0# #1816 1# b00000000000000000000001110001100 $ #1817 0# #1818 1# b00000000000000000000001110001101 $ #1819 0# #1820 1# b00000000000000000000001110001110 $ #1821 0# #1822 1# b00000000000000000000001110001111 $ #1823 0# #1824 1# b00000000000000000000001110010000 $ #1825 0# #1826 1# b00000000000000000000001110010001 $ #1827 0# #1828 1# b00000000000000000000001110010010 $ #1829 0# #1830 1# b00000000000000000000001110010011 $ #1831 0# #1832 1# b00000000000000000000001110010100 $ #1833 0# #1834 1# b00000000000000000000001110010101 $ #1835 0# #1836 1# b00000000000000000000001110010110 $ #1837 0# #1838 1# b00000000000000000000001110010111 $ #1839 0# #1840 1# b00000000000000000000001110011000 $ #1841 0# #1842 1# b00000000000000000000001110011001 $ #1843 0# #1844 1# b00000000000000000000001110011010 $ #1845 0# #1846 1# b00000000000000000000001110011011 $ #1847 0# #1848 1# b00000000000000000000001110011100 $ #1849 0# #1850 1# b00000000000000000000001110011101 $ #1851 0# #1852 1# b00000000000000000000001110011110 $ #1853 0# #1854 1# b00000000000000000000001110011111 $ #1855 0# #1856 1# b00000000000000000000001110100000 $ #1857 0# #1858 1# b00000000000000000000001110100001 $ #1859 0# #1860 1# b00000000000000000000001110100010 $ #1861 0# #1862 1# b00000000000000000000001110100011 $ #1863 0# #1864 1# b00000000000000000000001110100100 $ #1865 0# #1866 1# b00000000000000000000001110100101 $ #1867 0# #1868 1# b00000000000000000000001110100110 $ #1869 0# #1870 1# b00000000000000000000001110100111 $ #1871 0# #1872 1# b00000000000000000000001110101000 $ #1873 0# #1874 1# b00000000000000000000001110101001 $ #1875 0# #1876 1# b00000000000000000000001110101010 $ #1877 0# #1878 1# b00000000000000000000001110101011 $ #1879 0# #1880 1# b00000000000000000000001110101100 $ #1881 0# #1882 1# b00000000000000000000001110101101 $ #1883 0# #1884 1# b00000000000000000000001110101110 $ #1885 0# #1886 1# b00000000000000000000001110101111 $ #1887 0# #1888 1# b00000000000000000000001110110000 $ #1889 0# #1890 1# b00000000000000000000001110110001 $ #1891 0# #1892 1# b00000000000000000000001110110010 $ #1893 0# #1894 1# b00000000000000000000001110110011 $ #1895 0# #1896 1# b00000000000000000000001110110100 $ #1897 0# #1898 1# b00000000000000000000001110110101 $ #1899 0# verilator-5.042/test_regress/t/t_savable.py0000755000542200017500000000131115101701376021377 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=["--savable"], save_time=500) test.execute(check_finished=False, all_run_flags=['+save_time=500']) if not os.path.exists(test.obj_dir + "/saved.vltsv"): test.error("Saved.vltsv not created") test.execute(all_run_flags=['+save_restore=1']) test.passes() verilator-5.042/test_regress/t/t_force_rhs_ref_multi_lhs.v0000644000542200017500000000127015101701376024466 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module t; bit [1:0] a; bit [1:0] b; bit [1:0] d; initial begin a = 0; force b = a; force d = a; a = 2; #1; `checkh(a, 2); `checkh(b, 2); `checkh(d, 2); a = 3; #1; `checkh(a, 3); `checkh(b, 3); `checkh(d, 3); #1 $finish; end endmodule verilator-5.042/test_regress/t/t_config_param.py0000755000542200017500000000131315101701376022411 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["--lint-only"], fails=test.vlt_all, expect_filename=test.golden_filename) # Sort so that 'initial' scheduling order is not relevant # test.files_identical_sorted(test.run_log_filename, test.golden_filename, is_logfile=True) test.passes() verilator-5.042/test_regress/t/t_interface_gen4.v0000644000542200017500000000227515101701376022463 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // bug789 generates module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=1; ifc #(1) itopa(); ifc #(2) itopb(); sub #(1) ca (.isub(itopa), .i_value(4)); sub #(2) cb (.isub(itopb), .i_value(5)); always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==1) begin if (itopa.MODE != 1) $stop; if (itopb.MODE != 2) $stop; end if (cyc==20) begin if (itopa.i != 4) $stop; if (itopb.i != 5) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module sub #(parameter MODE = 0) ( ifc isub, input integer i_value ); // Commercial unsupported Xmrs into scopes within interfaces generate always_comb isub.i = i_value; endgenerate endmodule interface ifc; parameter MODE = 0; // Commercial unsupported Xmrs into scopes within interfaces generate integer i; endgenerate endinterface verilator-5.042/test_regress/t/t_savable_open_bad2.v0000644000542200017500000000055215101701376023130 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; endmodule verilator-5.042/test_regress/t/t_class_extends_bad.py0000755000542200017500000000076615101701376023444 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_sys_writemem_b.py0000755000542200017500000000272015101701376023017 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_sys_readmem.v" # Use random reset to ensure we're fully initializing arrays before # $writememh, to avoid miscompares with X's on 4-state simulators. test.verilated_randReset = 2 # 2 == truly random test.compile(v_flags2=[ "+define+WRITEMEM_READ_BACK=1", "+define+WRITEMEM_BIN=1", '+define+WRITEMEM_READ_BACK=1', '\'+define+OUT_TMP1=\"' + test.obj_dir + '/tmp1.mem\"\'', '\'+define+OUT_TMP2=\"' + test.obj_dir + '/tmp2.mem\"\'', '\'+define+OUT_TMP3=\"' + test.obj_dir + '/tmp3.mem\"\'', '\'+define+OUT_TMP4=\"' + test.obj_dir + '/tmp4.mem\"\'', '\'+define+OUT_TMP5=\"' + test.obj_dir + '/tmp5.mem\"\'', '\'+define+OUT_TMP6=\"' + test.obj_dir + '/tmp6.mem\"\'', '\'+define+OUT_TMP7=\"' + test.obj_dir + '/tmp7.mem\"\'', '\'+define+OUT_TMP8=\"' + test.obj_dir + '/tmp8.mem\"\'', ]) test.execute() for i in range(1, 9): gold = test.t_dir + "/t_sys_writemem_b.gold" + str(i) + ".mem" out = test.obj_dir + "/tmp" + str(i) + ".mem" test.files_identical(out, gold) test.passes() verilator-5.042/test_regress/t/t_select_plus_mul_pow2.py0000755000542200017500000000073415101701376024140 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_enum_type_nomethod_bad.py0000755000542200017500000000076615101701376024507 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_tri_pull_unsup.py0000755000542200017500000000077315101701376023061 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_assert_question.py0000755000542200017500000000077115101701376023223 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--assert']) test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_generic_modport_bad.out0000755000542200017500000000046715101701376026162 0ustar mahmoudyfreeshell%Error: t/t_interface_generic_modport_bad.v:11:33: Modport not found under interface 'inf': 'mp' 11 | module GenericModule (interface.mp a); | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_select_out_of_range.py0000755000542200017500000000075015101701376023776 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["-Wno-SELRANGE"]) test.passes() verilator-5.042/test_regress/t/t_define_override.out0000644000542200017500000000205415101701376023274 0ustar mahmoudyfreeshell%Warning-REDEFMACRO: Redefining existing define: 'TEST_MACRO', with different value: '50' ... Location of previous definition, with value: '20' ... For warning description see https://verilator.org/warn/REDEFMACRO?v=latest ... Use "/* verilator lint_off REDEFMACRO */" and lint_on around source to disable this message. %Warning-DEFOVERRIDE: t/t_define_override.v:9:23: Overriding define: 'TEST_MACRO' with value: '10' to existing command line define value: '50' ... Location of previous definition, with value: '50' ... For warning description see https://verilator.org/warn/DEFOVERRIDE?v=latest ... Use "/* verilator lint_off DEFOVERRIDE */" and lint_on around source to disable this message. %Warning-DEFOVERRIDE: t/t_define_override.v:10:24: Overriding define: 'TEST_MACRO' with value: '100' to existing command line define value: '50' ... Location of previous definition, with value: '50' %Error: Exiting due to verilator-5.042/test_regress/t/t_func_v.py0000755000542200017500000000073415101701376021252 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_stream_trace.py0000755000542200017500000000110015101701376022427 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--cc --trace-vcd']) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_event_control_expr.py0000755000542200017500000000257415101701376023715 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile( # do not test classes for multithreaded, as V3InstrCount doesn't handle MemberSel verilator_flags2=(['-DNO_CLASS'] if test.vltmt else [])) test.execute() for filename in test.glob_some(test.obj_dir + "/" + test.vm_prefix + "*.cpp"): # Check that these simple expressions are not stored in temp variables test.file_grep_not(filename, r'__Vtrigcurr__expression_.* = vlSelf->clk;') test.file_grep_not(filename, r'__Vtrigcurr__expression_.* = vlSelf->t__DOT__q.at\(0U\);') test.file_grep_not(filename, r'__Vtrigcurr__expression_.* = .*vlSelf->t__DOT____Vcellinp__u_array__t') test.file_grep_not(filename, r'__Vtrigcurr__expression_.* = .*vlSymsp->TOP__t__DOT__u_class.__PVT__obj') # The line below should only be generated if concats/replicates aren't converted to separate senitems test.file_grep_not(filename, r'__Vtrigcurr__expression_.* = .*vlSelf->t__DOT__a') test.passes() verilator-5.042/test_regress/t/t_castdyn_run_bad.v0000644000542200017500000000126615101701376022744 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Base; endclass class ExbaseA extends Base; endclass class ExbaseB extends Base; endclass module t; int i; Base b; ExbaseA ba, ba1; ExbaseB bb, bb1; initial begin ba = new; b = ba; i = $cast(ba1, b); if (i != 1) $stop; $cast(ba1, b); // ok at runtime bb = new; b = bb; i = $cast(ba1, b); if (i != 0) $stop; $cast(ba1, b); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_constraint_assoc_arr_bad.py0000755000542200017500000000076615101701376025025 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_package_dup_bad2.py0000755000542200017500000000076615101701376023132 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_unused_iface_bad.out0000644000542200017500000000161515101701376024433 0ustar mahmoudyfreeshell%Warning-UNDRIVEN: t/t_lint_unused_iface_bad.v:8:10: Signal is not driven: 'sig_udrv' : ... note: In instance 't.sub' 8 | logic sig_udrv; | ^~~~~~~~ ... For warning description see https://verilator.org/warn/UNDRIVEN?v=latest ... Use "/* verilator lint_off UNDRIVEN */" and lint_on around source to disable this message. %Warning-UNUSEDSIGNAL: t/t_lint_unused_iface_bad.v:9:10: Signal is not used: 'sig_uusd' : ... note: In instance 't.sub' 9 | logic sig_uusd; | ^~~~~~~~ ... For warning description see https://verilator.org/warn/UNUSEDSIGNAL?v=latest ... Use "/* verilator lint_off UNUSEDSIGNAL */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_class_param_super.py0000755000542200017500000000070615101701376023474 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.passes() verilator-5.042/test_regress/t/t_disable.out0000644000542200017500000000042415101701376021545 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_disable.v:17:13: Unsupported: disabling block that contains a fork 17 | disable forked; | ^~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_trace_public_sig_vlt.py0000755000542200017500000000245415101701376024156 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_trace_public_sig.cpp" test.top_filename = "t/t_trace_public.v" test.golden_filename = "t/t_trace_public.out" out_filename = test.obj_dir + "/V" + test.name + ".tree.json" test.compile(make_top_shell=False, make_main=False, v_flags2=[ "--trace-vcd --exe", test.pli_filename, test.t_dir + "/t_trace_public_sig.vlt --no-json-edit-nums" ]) if test.vlt_all: test.file_grep( out_filename, r'{"type":"VAR","name":"GSR",.*"loc":"\w,47:[^"]*",.*"origName":"GSR",.*"isSigPublic":true,.*"dtypeName":"logic",.*"isSigUserRdPublic":true.*"isSigUserRWPublic":true' ) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) # vcd_identical doesn't detect "$var a.b;" vs "$scope module a; $var b;" test.file_grep(test.trace_filename, r'module glbl') test.passes() verilator-5.042/test_regress/t/t_past_bad.out0000644000542200017500000000232415101701376021720 0ustar mahmoudyfreeshell%Error: t/t_past_bad.v:16:20: Expecting expression to be constant, but variable isn't const: 'num' : ... note: In instance 't' 16 | if ($past(d, num)) $stop; | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_past_bad.v:16:11: $past tick value must be constant (IEEE 1800-2023 16.9.3) : ... note: In instance 't' 16 | if ($past(d, num)) $stop; | ^~~~~ %Error: t/t_past_bad.v:17:20: $past tick value must be >= 1 (IEEE 1800-2023 16.9.3) : ... note: In instance 't' 17 | if ($past(d, 0)) $stop; | ^ %Warning-TICKCOUNT: t/t_past_bad.v:18:20: $past tick value of 10000 may have a large performance cost : ... note: In instance 't' 18 | if ($past(d, 10000)) $stop; | ^~~~~ ... For warning description see https://verilator.org/warn/TICKCOUNT?v=latest ... Use "/* verilator lint_off TICKCOUNT */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_event_control_prev_name_collision.py0000755000542200017500000000077415101701376026766 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["-fno-inline"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_param_shift.py0000755000542200017500000000073415101701376022267 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_vpi_var2.v0000644000542200017500000001101315101701376021324 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2023 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef USE_VPI_NOT_DPI //We call it via $c so we can verify DPI isn't required - see bug572 `else import "DPI-C" context function int mon_check(); `endif module t /* verilator public_flat_on */ #( parameter int visibleParam1 = 0, /* verilator public_off */ parameter int invisibleParam1 = 1, /* verilator public_on */ parameter int visibleParam2 = 2 /* verilator public_off */ ) (/*AUTOARG*/ // Outputs x, // Inputs clk, a ); `ifdef VERILATOR `systemc_header extern "C" int mon_check(); `verilog `endif input clk; input [7:0] a /* verilator public_flat_rw */; output reg [7:0] x /* verilator public_flat_rw */; /*verilator public_flat_rw_on @(posedge clk)*/ reg onebit; reg [2:1] twoone; reg [2:1] fourthreetwoone[4:3]; reg LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND; // verilator lint_off ASCRANGE reg [0:61] quads[2:3] /*verilator public_flat_rw @(posedge clk)*/; /*verilator public_off*/ reg invisible1; // verilator lint_on ASCRANGE /*verilator public_flat_on*/ reg [31:0] count; reg [31:0] half_count = 0; /*verilator public_off*/ /*verilator public_flat_rw_on*/ reg [31:0] delayed; reg [31:0] delayed_mem [16]; /*verilator public_off*/ reg invisible2; /*verilator public_flat_rw_on @(posedge clk)*/ reg [7:0] text_byte; reg [15:0] text_half; reg [31:0] text_word; reg [63:0] text_long; reg [511:0] text; reg [2047:0] too_big; /*verilator public_off*/ integer status; /*verilator public_flat_rw_on*/ real real1; string str1; localparam int nullptr = 123; logic [31:0] some_mem [4] = {0, 0, 0, 432}; /*verilator public_off*/ sub sub(); // Test loop initial begin count = 0; delayed = 0; onebit = 1'b0; fourthreetwoone[3] = 0; // stop icarus optimizing away text_byte = "B"; text_half = "Hf"; text_word = "Word"; text_long = "Long64b"; text = "Verilog Test module"; too_big = "some text"; real1 = 1.0; str1 = "hello"; `ifdef VERILATOR status = $c32("mon_check()"); `endif `ifdef IVERILOG status = $mon_check(); `endif `ifndef USE_VPI_NOT_DPI status = mon_check(); `endif if (status!=0) begin $write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status); $stop; end $write("%%Info: Checking results\n"); if (onebit != 1'b1) $stop; if (quads[2] != 62'h12819213_abd31a1c) $stop; if (quads[3] != 62'h1c77bb9b_3784ea09) $stop; if (text_byte != "A") $stop; if (text_half != "T2") $stop; if (text_word != "Tree") $stop; if (text_long != "44Four44") $stop; if (text != "lorem ipsum") $stop; if (str1 != "something a lot longer than hello") $stop; if (real1 > 123456.7895 || real1 < 123456.7885 ) $stop; end always @(posedge clk) begin count <= count + 2; if (count[1]) half_count <= half_count + 2; if (count == 1000) begin if (delayed != 123) $stop; if (delayed_mem[7] != 456) $stop; $write("*-* All Finished *-*\n"); $finish; end end genvar i; generate for (i=1; i<=6; i=i+1) begin : arr arr #(.LENGTH(i)) arr(); end endgenerate genvar k; generate for (k=1; k<=6; k=k+1) begin : subs sub subsub(); end endgenerate endmodule : t module sub; reg subsig1 /*verilator public_flat_rw*/; reg subsig2 /*verilator public_flat_rd*/; `ifdef IVERILOG // stop icarus optimizing signals away wire redundant = subsig1 | subsig2; `endif endmodule : sub module arr; parameter LENGTH = 1; /*verilator public_flat_rw_on*/ reg [LENGTH-1:0] sig; reg [LENGTH-1:0] rfr; reg check; reg verbose; /*verilator public_off*/ initial begin sig = {LENGTH{1'b0}}; rfr = {LENGTH{1'b0}}; end always @(posedge check) begin if (verbose) $display("%m : %x %x", sig, rfr); if (check && sig != rfr) $stop; check <= 0; end endmodule : arr verilator-5.042/test_regress/t/t_virtual_interface_member_trigger_realistic_case.py0000755000542200017500000000104115101701376031574 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.skip("Test is broken, see #6613") test.scenarios('simulator') test.compile(verilator_flags2=['--binary']) test.execute() test.passes() verilator-5.042/test_regress/t/t_disable_outside3.v0000644000542200017500000000132215101701376023020 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t; initial begin begin : blk int x = 0; fork : fork_blk begin #4; x = 3; end begin : begin_blk x = 1; #2; x = 2; end join_none #1; disable fork_blk.begin_blk; #2; if (x != 1) $stop; #2; if (x != 3) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_interface_array4.v0000644000542200017500000000175115101701376023026 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface Ifc; logic req, grant; logic [7:0] addr, data; endinterface class Cls; virtual Ifc bus; int m_i; function new(virtual Ifc s, int i); bus = s; m_i = i; endfunction task request(); bus.req <= 1'b1; endtask task wait_for_bus(); @(posedge bus.grant); endtask endclass module devA (Ifc s); endmodule module devB (Ifc s); endmodule module t; Ifc s14[1:4] (); devA a1 (s14[1]); devB b1 (s14[2]); devA a2 (s14[3]); devB b2 (s14[4]); Ifc s65[6:5] (); devA a3 (s65[5]); devB b3 (s65[6]); initial begin Cls t14[1:4]; Cls t65[6:5]; t14[1] = new(s14[1], 1); t14[2] = new(s14[2], 2); t14[3] = new(s14[3], 3); t14[4] = new(s14[4], 4); t65[5] = new(s65[5], 5); t65[6] = new(s65[6], 6); end endmodule verilator-5.042/test_regress/t/t_alw_noreorder.py0000755000542200017500000000170215101701376022630 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_alw_reorder.v" test.compile(verilator_flags2=["--stats -fno-reorder"]) test.file_grep(test.stats, r'Optimizations, Split always\s+(\d+)', 0) # Here we should see some dly vars since reorder is disabled. # (Whereas our twin test, t_alw_reorder, should see no dly vars # since it enables the reorder step.) files = test.glob_some(test.obj_dir + "/" + test.vm_prefix + "___024root*.cpp") test.file_grep_any(files, r'dly__t__DOT__v1') test.file_grep_any(files, r'dly__t__DOT__v2') test.execute() test.passes() verilator-5.042/test_regress/t/t_enum_bad_wrap.py0000755000542200017500000000107515101701376022574 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["--lint-only -Wwarn-VARHIDDEN"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_event_control_expr_unsup.out0000644000542200017500000000045715101701376025321 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_event_control_expr_unsup.v:15:21: Unsupported: Impure function calls in sensitivity lists 15 | always @(posedge foo()); | ^~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_udp_bad_line_inputs.v0000644000542200017500000000051215101701376023605 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 primitive udp_0(output o, input i); table ? 1 ? 0 0 : 0; // <--- BAD too many inputs endtable endprimitive verilator-5.042/test_regress/t/t_virtual_interface_param_bind.py0000755000542200017500000000073415101701376025654 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_ena.v0000644000542200017500000000164415101701376021526 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; // verilator tracing_off integer b_trace_off; // verilator tracing_on integer c_trace_on; real r; // verilator tracing_off sub sub (); // verilator tracing_on always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; b_trace_off <= cyc; c_trace_on <= b_trace_off; r <= r + 0.1; if (cyc==4) begin if (c_trace_on != 2) $stop; end if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module sub; integer inside_sub = 0; endmodule verilator-5.042/test_regress/t/t_property_sexpr_bad.py0000755000542200017500000000106215101701376023700 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, verilator_flags2=['--assert', '--timing'], expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_force_tri.py0000755000542200017500000000077615101701376021754 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_func_impure_bad.v0000644000542200017500000000056215101701376022725 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Test of select from constant // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; int sig; task foo; // verilator no_inline_task sig = '1; endtask initial begin foo(); end endmodule verilator-5.042/test_regress/t/t_config_work__liba.v0000644000542200017500000000062515101701376023240 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module m1; m3 u_13(); initial $display("liba:m1 %%m=%m %%l=%l"); endmodule module m3; // Module name duplicated between libraries initial $display("liba:m3 %%m=%m %%l=%l"); endmodule verilator-5.042/test_regress/t/t_class_method_bad.v0000644000542200017500000000063015101701376023052 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Base1; task meth1; endtask endclass class Cls2 extends Base1; task meth2; endtask endclass module t; initial begin Cls2 c; c.meth3(); // Not found end endmodule verilator-5.042/test_regress/t/t_class_super_new.v0000644000542200017500000000625515101701376023004 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); class Foo; int x; function new; this.x = 10; endfunction endclass class Bar extends Foo; function new; super.new; endfunction endclass class BarUnusedArg extends Foo; function new (int a); super.new; endfunction endclass class FooArg; int x; function new (int a); this.x = a; endfunction endclass class BarArg extends FooArg; function new (int a); super.new(a); endfunction endclass class BarArgWithReturnInIf extends FooArg; function new (int a); super.new(a); if (a < 10) begin return; end this.x = 20; endfunction endclass class BarExpr extends FooArg; function new (int a, string b); super.new(a + b.len()); endfunction endclass class Foo2Args; int x; function new (int a, int b); this.x = a + b; endfunction endclass class Bar2Args extends Foo2Args; function new (int a, int b); super.new(a, b); endfunction endclass class OptArgInNew; int x; function new (int y=1); x = y; endfunction endclass class NoNew extends OptArgInNew; endclass class NewWithoutSuper extends OptArgInNew; function new; endfunction endclass class OptArgInNewParam #(parameter int P=1); int x; function new (int y=1); x = y; endfunction endclass class NoNewParam#(parameter int R) extends OptArgInNewParam#(R); endclass class NewWithoutSuperParam#(parameter int R) extends OptArgInNewParam#(); function new; endfunction endclass module t (/*AUTOARG*/ ); class FooInModule; int x; function new; this.x = 15; endfunction endclass class BarInModule extends FooInModule; function new; super.new; endfunction endclass Bar bar; BarInModule barInModule; BarUnusedArg barUnusedArg; BarArg barArg; BarExpr barExpr; Bar2Args bar2Args; NoNew noNew; NewWithoutSuper newWithoutSuper; NoNewParam#(2) noNewParam; NewWithoutSuperParam#(1) newWithoutSuperParam; BarArgWithReturnInIf barIf1, barIf10; initial begin bar = new; `checkh(bar.x, 10); barInModule = new; `checkh(barInModule.x, 15); barUnusedArg = new(2); `checkh(barUnusedArg.x, 10); barArg = new(2); `checkh(barArg.x, 2); barExpr = new (7, "ABCDEFGHI"); `checkh(barExpr.x, 16); bar2Args = new(2, 12); `checkh(bar2Args.x, 14); noNew = new; `checkh(noNew.x, 1); newWithoutSuper = new; `checkh(newWithoutSuper.x, 1); noNewParam = new; `checkh(noNewParam.x, 1); newWithoutSuperParam = new; `checkh(newWithoutSuperParam.x, 1); barIf1 = new(1); `checkh(barIf1.x, 1); barIf10 = new(10); `checkh(barIf10.x, 20); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_interface_virtual_bad.v0000644000542200017500000000203515101701376024114 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Arkadiusz Kozdra. // SPDX-License-Identifier: CC0-1.0 // See also t_interface_virtual.v interface PBus; logic req, grant; logic [7:0] addr, data; modport phy(input addr, ref data); endinterface interface QBus; endinterface typedef virtual PBus vpbus_t; module t; PBus p8(); QBus q8(); vpbus_t v8; virtual PBus.phy v8_phy; logic data; initial begin v8 = p8; p8 = v8; // error v8 = q8; // error v8_phy = p8; v8_phy = v8; v8_phy = p8.phy; v8 = v8_phy; // error v8 = p8.phy; // error data = p8.phy; // error data = v8_phy; // error data = v8; // error data = p8; // error v8 = data; // error v8.grant = 1'b1; $display("q8.grant=", p8.grant, " v8.grant=", v8.grant, v8_phy.addr, v8.gran); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_interface_array_parameter_access.py0000755000542200017500000000073715101701376026514 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_copy.py0000755000542200017500000000073415101701376022131 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_let_arg_bad.v0000644000542200017500000000117115101701376022023 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; let NO_ARG = 10; let ONE_ARG(a) = 10; initial begin if (NO_ARG(10) != 10) $stop; // BAD extra arg if (ONE_ARG != 10) $stop; // BAD need arg if (ONE_ARG() != 10) $stop; // BAD need arg if (ONE_ARG(10, 20) != 10) $stop; // BAD extra arg if (ONE_ARG(.b(1)) != 10) $stop; // BAD wrong arg name $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_hier_trace_noinl.out0000644000542200017500000001403215101701376023446 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $var wire 1 # clk $end $var wire 1 $ reset_l $end $scope module t $end $var wire 1 # clk $end $var wire 1 $ reset_l $end $scope module u0_sub_top $end $var wire 1 # clk $end $var wire 1 $ reset_l $end $upscope $end $scope module u1_sub_top $end $var wire 1 # clk $end $var wire 1 $ reset_l $end $upscope $end $upscope $end $upscope $end $scope module top.t.u0_sub_top $end $var wire 1 & clk $end $var wire 1 ' reset_l $end $scope module sub_top $end $var wire 1 & clk $end $var wire 1 ' reset_l $end $scope module u0 $end $var wire 1 & clk $end $var wire 1 ' reset_l $end $upscope $end $scope module u1 $end $var wire 1 & clk $end $var wire 1 ' reset_l $end $upscope $end $scope module u2 $end $var wire 1 & clk $end $var wire 1 ' reset_l $end $upscope $end $scope module u3 $end $var wire 1 & clk $end $var wire 1 ' reset_l $end $upscope $end $scope module u4 $end $var wire 1 & clk $end $var wire 1 ' reset_l $end $upscope $end $scope module u5 $end $var wire 1 & clk $end $var wire 1 ' reset_l $end $upscope $end $scope module u6 $end $var wire 1 & clk $end $var wire 1 ' reset_l $end $upscope $end $scope module u7 $end $var wire 1 & clk $end $var wire 1 ' reset_l $end $upscope $end $upscope $end $upscope $end $scope module top.t.u1_sub_top $end $var wire 1 ) clk $end $var wire 1 * reset_l $end $scope module sub_top $end $var wire 1 ) clk $end $var wire 1 * reset_l $end $scope module u0 $end $var wire 1 ) clk $end $var wire 1 * reset_l $end $upscope $end $scope module u1 $end $var wire 1 ) clk $end $var wire 1 * reset_l $end $upscope $end $scope module u2 $end $var wire 1 ) clk $end $var wire 1 * reset_l $end $upscope $end $scope module u3 $end $var wire 1 ) clk $end $var wire 1 * reset_l $end $upscope $end $scope module u4 $end $var wire 1 ) clk $end $var wire 1 * reset_l $end $upscope $end $scope module u5 $end $var wire 1 ) clk $end $var wire 1 * reset_l $end $upscope $end $scope module u6 $end $var wire 1 ) clk $end $var wire 1 * reset_l $end $upscope $end $scope module u7 $end $var wire 1 ) clk $end $var wire 1 * reset_l $end $upscope $end $upscope $end $upscope $end $scope module top.t.u0_sub_top.sub_top.u0 $end $var wire 1 , clk $end $var wire 1 - reset_l $end $scope module detail_code $end $var wire 1 , clk $end $var wire 1 - reset_l $end $upscope $end $upscope $end $scope module top.t.u0_sub_top.sub_top.u1 $end $var wire 1 / clk $end $var wire 1 0 reset_l $end $scope module detail_code $end $var wire 1 / clk $end $var wire 1 0 reset_l $end $upscope $end $upscope $end $scope module top.t.u0_sub_top.sub_top.u2 $end $var wire 1 2 clk $end $var wire 1 3 reset_l $end $scope module detail_code $end $var wire 1 2 clk $end $var wire 1 3 reset_l $end $upscope $end $upscope $end $scope module top.t.u0_sub_top.sub_top.u3 $end $var wire 1 5 clk $end $var wire 1 6 reset_l $end $scope module detail_code $end $var wire 1 5 clk $end $var wire 1 6 reset_l $end $upscope $end $upscope $end $scope module top.t.u0_sub_top.sub_top.u4 $end $var wire 1 8 clk $end $var wire 1 9 reset_l $end $scope module detail_code $end $var wire 1 8 clk $end $var wire 1 9 reset_l $end $upscope $end $upscope $end $scope module top.t.u0_sub_top.sub_top.u5 $end $var wire 1 ; clk $end $var wire 1 < reset_l $end $scope module detail_code $end $var wire 1 ; clk $end $var wire 1 < reset_l $end $upscope $end $upscope $end $scope module top.t.u0_sub_top.sub_top.u6 $end $var wire 1 > clk $end $var wire 1 ? reset_l $end $scope module detail_code $end $var wire 1 > clk $end $var wire 1 ? reset_l $end $upscope $end $upscope $end $scope module top.t.u0_sub_top.sub_top.u7 $end $var wire 1 A clk $end $var wire 1 B reset_l $end $scope module detail_code $end $var wire 1 A clk $end $var wire 1 B reset_l $end $upscope $end $upscope $end $scope module top.t.u1_sub_top.sub_top.u0 $end $var wire 1 D clk $end $var wire 1 E reset_l $end $scope module detail_code $end $var wire 1 D clk $end $var wire 1 E reset_l $end $upscope $end $upscope $end $scope module top.t.u1_sub_top.sub_top.u1 $end $var wire 1 G clk $end $var wire 1 H reset_l $end $scope module detail_code $end $var wire 1 G clk $end $var wire 1 H reset_l $end $upscope $end $upscope $end $scope module top.t.u1_sub_top.sub_top.u2 $end $var wire 1 J clk $end $var wire 1 K reset_l $end $scope module detail_code $end $var wire 1 J clk $end $var wire 1 K reset_l $end $upscope $end $upscope $end $scope module top.t.u1_sub_top.sub_top.u3 $end $var wire 1 M clk $end $var wire 1 N reset_l $end $scope module detail_code $end $var wire 1 M clk $end $var wire 1 N reset_l $end $upscope $end $upscope $end $scope module top.t.u1_sub_top.sub_top.u4 $end $var wire 1 P clk $end $var wire 1 Q reset_l $end $scope module detail_code $end $var wire 1 P clk $end $var wire 1 Q reset_l $end $upscope $end $upscope $end $scope module top.t.u1_sub_top.sub_top.u5 $end $var wire 1 S clk $end $var wire 1 T reset_l $end $scope module detail_code $end $var wire 1 S clk $end $var wire 1 T reset_l $end $upscope $end $upscope $end $scope module top.t.u1_sub_top.sub_top.u6 $end $var wire 1 V clk $end $var wire 1 W reset_l $end $scope module detail_code $end $var wire 1 V clk $end $var wire 1 W reset_l $end $upscope $end $upscope $end $scope module top.t.u1_sub_top.sub_top.u7 $end $var wire 1 Y clk $end $var wire 1 Z reset_l $end $scope module detail_code $end $var wire 1 Y clk $end $var wire 1 Z reset_l $end $upscope $end $upscope $end $enddefinitions $end #0 0# 0$ 0& 0' 0) 0* 0, 0- 0/ 00 02 03 05 06 08 09 0; 0< 0> 0? 0A 0B 0D 0E 0G 0H 0J 0K 0M 0N 0P 0Q 0S 0T 0V 0W 0Y 0Z verilator-5.042/test_regress/t/t_dpi_import_mix_bad.v0000644000542200017500000000075515101701376023440 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (); import "DPI-C" function int foo (int i); export "DPI-C" function foo; // Bad mix initial begin $stop; end endmodule verilator-5.042/test_regress/t/t_preproc_preproczero_bad.v0000644000542200017500000000044115101701376024511 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `begin_keywords "1800-2023" `define ZERO 0 `ifdef ( ZERO ) // ... `endif verilator-5.042/test_regress/t/t_metacmt_onoff.out0000644000542200017500000000171615101701376022770 0ustar mahmoudyfreeshell%Warning-ASCRANGE: t/t_metacmt_onoff.v:8:8: Ascending bit range vector: left < right of bit range: [0:1] : ... note: In instance 't' 8 | reg [0:1] show1; /*verilator lint_off ASCRANGE*/ reg [0:2] ign2; /*verilator lint_on ASCRANGE*/ reg [0:3] show3; | ^ ... For warning description see https://verilator.org/warn/ASCRANGE?v=latest ... Use "/* verilator lint_off ASCRANGE */" and lint_on around source to disable this message. %Warning-ASCRANGE: t/t_metacmt_onoff.v:8:107: Ascending bit range vector: left < right of bit range: [0:3] : ... note: In instance 't' 8 | reg [0:1] show1; /*verilator lint_off ASCRANGE*/ reg [0:2] ign2; /*verilator lint_on ASCRANGE*/ reg [0:3] show3; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_protect_ids_bad.out0000644000542200017500000000130515101701376023266 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: Unsupported: Using --protect-ids with --public ... Suggest remove --public. ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Warning-INSECURE: Using --protect-ids with --trace may expose private design details ... Suggest remove --trace. ... For warning description see https://verilator.org/warn/INSECURE?v=latest ... Use "/* verilator lint_off INSECURE */" and lint_on around source to disable this message. %Warning-INSECURE: Using --protect-ids with --vpi may expose private design details ... Suggest remove --vpi. %Error: Exiting due to verilator-5.042/test_regress/t/t_lint_latch_6.v0000644000542200017500000000103715101701376022147 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module for issue #221 // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2023 by Julien Margetts (Originally provided by Adrien Le Masle) // SPDX-License-Identifier: Unlicense module verilator_latch ( input logic state, output logic [31:0] b ); function logic [31:0 ] toto (); logic [31:0] res; res = 10; return res; endfunction always_comb begin b = 0; if (state) b = toto(); end endmodule; verilator-5.042/test_regress/t/t_savable_timing_bad.py0000755000542200017500000000117615101701376023565 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_savable_coverage_bad.v" test.compile(v_flags2=["--savable --timing"], save_time=500, fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_import_name_bad.py0000755000542200017500000000110115101701376024125 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_import_name2_bad.out0000644000542200017500000000057515101701376024401 0ustar mahmoudyfreeshell%Error: t/t_lint_import_name2_bad.v:7:8: Import package not found: 'missing' 7 | import missing::sigs; | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_lint_import_name2_bad.v:9:8: Import package not found: 'missing' 9 | import missing::*; | ^~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_queue_pushpop.py0000755000542200017500000000073415101701376022674 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_complex_structs_fst_sc.py0000755000542200017500000000131015101701376025736 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_complex.v" if not test.have_sc: test.skip("No SystemC installed") test.compile(verilator_flags2=['--sc --trace-fst --trace-structs --no-trace-params']) test.execute() test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_param_passed_to_port.py0000755000542200017500000000073415101701376024177 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_preproc_inc_fn_bad.out0000644000542200017500000000037115101701376023737 0ustar mahmoudyfreeshell%Error: t/t_preproc_inc_fn_bad.v:7:10: Expecting include filename. Found: ELSE 7 | `include `else | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_inst_name_long.v0000644000542200017500000000333315101701376022576 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilator lint_off PINMISSING // verilator lint_off WIDTHEXPAND module t; // Original issue sub #(.PARAM("FALSE")) \$mul$/nxx_xxxxxxx/xxxxxxx/XxxxxxxxXxxxxxxxxx/xxx/.././xxx/xxx_xxxxxxxxxx_xxxxx_xxxx_xxx_xxx.v:30$7 ( ); // Change sizes sub #(.PARAM("FALSE")) \$mul$/nxx_xxxxxxx/xxxxxxx/XxxxxxxXxxxxxxxxx/xxx/.././xxx/xxx_xxxxxxxxxx_xxxxx_xxxx_xxx_xxx.v:30$7 ( ); sub #(.PARAM("FALSE")) \$mul$/nxx_xxxxxxx/xxxxxxx/Xxxxxxxxxxxxxxxx/xxx/.././xxx/xxx_xxxxxxxxxx_xxxxx_xxxx_xxx_xxx.v:30$7 ( ); sub #(.PARAM("FALSE")) \$mul$/nxx_xxxxxxx/xxxxxxx/XxxxxXxxxxxxxxx/xxx/.././xxx/xxx_xxxxxxxxxx_xxxxx_xxxx_xxx_xxx.v:30$7 ( ); sub #(.PARAM("FALSE")) \$mul$/nxx_xxxxxxx/xxxxxxx/XxxxXxxxxxxxxx/xxx/.././xxx/xxx_xxxxxxxxxx_xxxxx_xxxx_xxx_xxx.v:30$7 ( ); sub #(.PARAM("FALSE")) \$mul$/nxx_xxxxxxx/xxxxxxx/XxxXxxxxxxxxx/xxx/.././xxx/xxx_xxxxxxxxxx_xxxxx_xxxx_xxx_xxx.v:30$7 ( ); sub #(.PARAM("FALSE")) \$mul$/nxx_xxxxxxx/xxxxxxx/XxxxxxxxxXxxxxxxxxx/xxx/.././xxx/xxx_xxxxxxxxxx_xxxxx_xxxx_xxx_xxx.v:30$7 ( ); sub #(.PARAM("FALSE")) \$mul$/nxx_xxxxxxx/xxxxxxx/XxxxxxxxxxXxxxxxxxxx/xxx/.././xxx/xxx_xxxxxxxxxx_xxxxx_xxxx_xxx_xxx.v:30$7 ( ); sub #(.PARAM("FALSE")) \$mul$/nxx_xxxxxxx/xxxxxxx/XxxxxxxxxxxXxxxxxxxxx/xxx/.././xxx/xxx_xxxxxxxxxx_xxxxx_xxxx_xxx_xxx.v:30$7 ( ); endmodule module sub #(parameter PARAM = "TRUE") (input [5:0] ACC_FIR); always @(ACC_FIR) $display("WARNING: instance %m input is %d", PARAM); endmodule verilator-5.042/test_regress/t/t_unroll_signed.py0000755000542200017500000000073415101701376022636 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_modscope.py0000755000542200017500000000073415101701376022770 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_order_dpi_export_4.cpp0000644000542200017500000000223015101701376023705 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2021 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include #include #include void toggle_other_clk(svBit val) { set_other_clk(val); } void toggle_third_clk(svBit val) { set_third_clk(val); } int main(int argc, char* argv[]) { VM_PREFIX* const tb = new VM_PREFIX; tb->contextp()->commandArgs(argc, argv); bool clk = true; while (!tb->contextp()->gotFinish()) { // Timeout if (tb->contextp()->time() > 100000) break; // Toggle and set main clock clk = !clk; tb->clk = clk; // Eval tb->eval(); // Advance time tb->contextp()->timeInc(500); } delete tb; return 0; } verilator-5.042/test_regress/t/t_assert_comp_bad.v0000644000542200017500000000124015101701376022722 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; localparam TEN = 10; localparam string PCTPCT = "%%"; if (1) begin $info; $info("User elaboration-time info"); $info("Percent=%% PctPct=%s Ten=%0d", PCTPCT, TEN); $warning; $warning("User elaboration-time warning"); $warning(1); // Check can convert arguments to format $error; $error("User elaboration-time error"); $fatal(0, "User elaboration-time fatal"); $fatal(0); $fatal; end endmodule verilator-5.042/test_regress/t/t_assert_ctl_unsup.v0000755000542200017500000001012615101701376023200 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t(input logic clk); unsupported_ctl_type unsupported_ctl_type(clk ? 1 : 2); unsupported_ctl_type_expr unsupported_ctl_type_expr(); assert_class assert_class(); assert_iface assert_iface(); assert_iface_class assert_iface_class(); endmodule module unsupported_ctl_type(input int a); initial begin let Lock = 1; let Unlock = 2; let PassOn = 6; let PassOff = 7; let FailOn = 8; let FailOff = 9; let NonvacuousOn = 10; let VacuousOff = 11; $assertcontrol(Lock, a); $assertcontrol(Unlock); $assertcontrol(PassOn); $assertpasson; $assertpasson(a); $assertpasson(a, t); $assertcontrol(PassOff); $assertpassoff; $assertpassoff(a); $assertpassoff(a, t); $assertcontrol(FailOn); $assertfailon; $assertfailon(a); $assertfailon(a, t); $assertcontrol(FailOff); $assertfailoff; $assertfailoff(a); $assertfailoff(a, t); $assertcontrol(NonvacuousOn); $assertnonvacuouson; $assertnonvacuouson(a); $assertnonvacuouson(a, t); $assertcontrol(VacuousOff); $assertvacuousoff; $assertvacuousoff(a); $assertvacuousoff(a, t); end endmodule module unsupported_ctl_type_expr; int ctl_type = 1; initial begin $assertcontrol(ctl_type); end endmodule module assert_class; virtual class AssertCtl; pure virtual function void virtual_assert_ctl(); endclass class AssertCls; static function void static_function(); assert(0); endfunction static task static_task(); assert(0); endtask function void assert_function(); assert(0); endfunction task assert_task(); assert(0); endtask virtual function void virtual_assert(); assert(0); endfunction endclass class AssertOn extends AssertCtl; virtual function void virtual_assert_ctl(); $asserton; endfunction endclass class AssertOff extends AssertCtl; virtual function void virtual_assert_ctl(); $assertoff; endfunction endclass AssertCls assertCls; AssertOn assertOn; AssertOff assertOff; initial begin $assertoff; AssertCls::static_function(); AssertCls::static_task(); $asserton; AssertCls::static_function(); AssertCls::static_task(); assertCls = new; assertOn = new; assertOff = new; assertOff.virtual_assert_ctl(); assertCls.assert_function(); assertCls.assert_task(); assertCls.virtual_assert(); assertOn.virtual_assert_ctl(); assertCls.assert_function(); assertCls.assert_task(); assertCls.virtual_assert(); assertOff.virtual_assert_ctl(); assertCls.assert_function(); end endmodule interface Iface; function void assert_func(); assert(0); endfunction function void assertoff_func(); $assertoff; endfunction initial begin assertoff_func(); assert(0); assert_func(); $asserton; assert(0); assert_func(); end endinterface module assert_iface; Iface iface(); virtual Iface vIface = iface; initial begin vIface.assert_func(); vIface.assertoff_func(); vIface.assert_func(); iface.assert_func(); iface.assertoff_func(); iface.assert_func(); end endmodule interface class IfaceClass; pure virtual function void assertoff_func(); pure virtual function void assert_func(); endclass class IfaceClassImpl implements IfaceClass; virtual function void assertoff_func(); $assertoff; endfunction virtual function void assert_func(); assert(0); endfunction endclass module assert_iface_class; IfaceClassImpl ifaceClassImpl = new; initial begin ifaceClassImpl.assertoff_func(); ifaceClassImpl.assert_func(); end endmodule verilator-5.042/test_regress/t/t_constraint_json_only.v0000644000542200017500000000273715101701376024067 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Packet; rand int header; // 0..7 rand int length; // 0..15 rand int sublength; // 0..15 rand bit if_4; rand bit iff_5_6; rand bit if_state_ok; rand int array[2]; // 2,4,6 string state; constraint empty {} constraint size { header > 0 && header <= 7; length <= 15; length >= header; length dist { [0:1], [2:5] :/ 2, 6 := 6, 7 := 10, 1}; } constraint ifs { if (header > 4) { if_4 == '1; } if (header == 5 || header == 6) { iff_5_6 == '1; iff_5_6 == '1; iff_5_6 == '1; } else { iff_5_6 == '0; } } constraint arr_uniq { foreach (array[i]) { array[i] inside {2, 4, 6}; } unique { array[0], array[1] }; } constraint order { solve length before header; } constraint dis { soft sublength; disable soft sublength; sublength <= length; } constraint meth { if (strings_equal(state, "ok")) if_state_ok == '1; } function bit strings_equal(string a, string b); return a == b; endfunction endclass module t; Packet p; initial begin // Not testing use of constraints $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_class_membersel_int.py0000755000542200017500000000073415101701376024004 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_foreach_iface.py0000755000542200017500000000073415101701376022530 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_timescale_unit.out0000644000542200017500000000017715101701376023154 0ustar mahmoudyfreeshellTime scale of $unit is 10ps / 10ps Time scale of from_unit is 10ps / 10ps Time scale of t is 100ps / 10ps *-* All Finished *-* verilator-5.042/test_regress/t/t_class_fwd_cc.py0000755000542200017500000000070315101701376022400 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint() test.passes() verilator-5.042/test_regress/t/t_flag_modprefix_bad.py0000755000542200017500000000114315101701376023561 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = 't/t_EXAMPLE.v' # Anything test.lint(verilator_flags2=["--mod-prefix bad/name"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_covergroup_func_override_bad.py0000755000542200017500000000113715101701376025703 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if test.vlt_all: test.lint(fails=True, expect_filename=test.golden_filename) else: test.compile(nc_flags2=["-coverage", "functional"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_timing_pong.py0000755000542200017500000000077115101701376022305 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_var_vec_sel.py0000755000542200017500000000070615101701376022261 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.042/test_regress/t/t_vlt_match_error_1.py0000755000542200017500000000124515101701376023402 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_vlt_match_error.v" test.lint(verilator_flags2=[ "-DT_VLT_MATCH_ERROR_1 --lint-only -Wall t/t_vlt_match_error.v t/t_vlt_match_error.vlt" ], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_trace_array_threads_1.py0000755000542200017500000000131215101701376024211 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_trace_array.v" test.golden_filename = "t/t_trace_array.out" test.compile( verilator_flags2=['--cc --trace-vcd --trace-threads 1 --trace-structs --trace-max-width 0']) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_var_in_assign_bad.py0000755000542200017500000000124715101701376023422 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--lint-only --Mdir obj_lint_only"], fails=True, expect_filename=test.golden_filename) if os.path.exists("obj_lint_only"): test.error("%Error: lint-only shouldn't make output directory") test.passes() verilator-5.042/test_regress/t/t_bitsel_const_bad.v0000644000542200017500000000071115101701376023075 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Test of select from constant // // This tests issue #508, bit select of constant fails // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 module t; // Note that if we declare "wire [0:0] b", this works just fine. wire a; wire b; assign b = 1'b0; assign a = b[0]; // IEEE illegal can't extract scalar endmodule verilator-5.042/test_regress/t/t_func_default_warn.v0000644000542200017500000000114615101701376023270 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Test for warning (not error) on improperly width'ed // default function argument // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 function automatic logic foo ( // Intentionally provide a non-width'ed default value // This should warn, not error out input logic x = 0 ); return x; endfunction module t; logic foo_val; initial begin foo_val = foo(); if (foo_val != 1'b0) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_vpi_public_params.py0000755000542200017500000000157415101701376023474 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.pli_filename = "t/t_vpi_param.cpp" # same vpi script should work with --public-params instead of inline publics test.compile(make_top_shell=False, make_main=False, make_pli=True, iv_flags2=["-g2005-sv -D USE_VPI_NOT_DPI"], v_flags2=["+define+USE_VPI_NOT_DPI"], verilator_flags2=["--exe --vpi --no-l2name", test.pli_filename, "--public-params"]) test.execute(use_libvpi=True) test.passes() verilator-5.042/test_regress/t/t_select_bad_range.v0000644000542200017500000000072015101701376023040 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; reg [43:0] mi; reg sel; reg [3:0] sel2; always @ (posedge clk) begin mi = 44'h123; sel = mi[44]; sel2 = mi[44:41]; $write ("Bad select %x %x\n", sel, sel2); end endmodule verilator-5.042/test_regress/t/t_assert_pre.v0000644000542200017500000000274515101701376021757 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); module t ( /*AUTOARG*/ // Inputs clk ); input clk; bit toggle = 0; int inc = 0; int dec = 0; assert property (@(negedge clk) not toggle) else ++inc; assert property (@(negedge clk) not toggle) else --dec; int passsInc = 0; int passsDec = 0; assert property (@(negedge clk) not toggle) ++passsInc; else --passsDec; assert property (@(negedge clk) not toggle) ++passsInc; cover property (@(negedge clk) not toggle) ++passsInc; int inc2 = 0; assert property (@(e) not toggle) begin `checkh(inc2, 0); inc2++; `checkh(inc2,1); end event e; int cyc = 0; always @(posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d toggle==%d\n", $time, cyc, toggle); `endif if (cyc % 3 == 0) begin toggle <= 1; end else begin toggle <= 0; end cyc <= cyc + 1; if (cyc == 5) begin ->e; `checkh(inc, 2); `checkh(dec, -2); `checkh(passsInc, 6); `checkh(passsDec, -2); $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_string_type_methods.v0000644000542200017500000001165615101701376023703 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkg(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%g' exp='%g'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t (/*AUTOARG*/ // Inputs clk ); input clk; string s; integer cyc = 0; // Check constification initial begin s="1234"; `checkh(s.len(),4); s="ab7CD"; `checks(s.toupper(), "AB7CD"); s="ab7CD"; `checks(s.tolower(), "ab7cd"); s="1234"; s.putc(-1, "z"); `checks(s, "1234"); s="1234"; s.putc(4, "z"); `checks(s, "1234"); s="1234"; s.putc(2, 0); `checks(s, "1234"); s="1234"; s.putc(2, "z"); `checks(s, "12z4"); s="1234"; `checkh(s.getc(-1), 0); s="1234"; `checkh(s.getc(4), 0); s="1234"; `checkh(s.getc(2), "3"); s="b"; if (s.compare("a") <= 0) $stop; s="b"; if (s.compare("b") != 0) $stop; s="b"; if (s.compare("c") >= 0) $stop; s="b"; if (s.compare("A") <= 0) $stop; s="b"; if (s.compare("B") <= 0) $stop; s="b"; if (s.compare("C") <= 0) $stop; s="B"; if (s.compare("a") >= 0) $stop; s="B"; if (s.compare("b") >= 0) $stop; s="B"; if (s.compare("c") >= 0) $stop; s="b"; if (s.icompare("A") < 0) $stop; s="b"; if (s.icompare("B") != 0) $stop; s="b"; if (s.icompare("C") >= 0) $stop; s="abcd"; `checks(s.substr(-1,1), ""); s="abcd"; `checks(s.substr(1,0), ""); s="abcd"; `checks(s.substr(1,4), ""); s="abcd"; `checks(s.substr(2,3), "cd"); s="101"; `checkh(s.atoi(), 'd101); s="101"; `checkh(s.atohex(), 'h101); s="101"; `checkh(s.atooct(), 'o101); s="101"; `checkh(s.atobin(), 'b101); s="1.23"; `checkg(s.atoreal(), 1.23); s.itoa(123); `checks(s, "123"); s.hextoa(123); `checks(s, "7b"); s.octtoa(123); `checks(s, "173"); s.bintoa(123); `checks(s, "1111011"); s.realtoa(1.23); `checks(s, "1.23"); s = "bAr"; s = s.toupper; `checks(s, "BAR"); s = s.tolower; `checks(s, "bar"); end // Check runtime always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==0) begin // Setup s = "1234"; end else if (cyc==1) begin `checkh(s.len(),4); end else if (cyc==2) begin s.putc(-1, "z"); end else if (cyc==3) begin `checks(s, "1234"); s.putc(4, "z"); end else if (cyc==4) begin `checks(s, "1234"); s.putc(2, 0); end else if (cyc==5) begin `checks(s, "1234"); s.putc(2, "z"); end else if (cyc==6) begin `checks(s, "12z4"); end else if (cyc==7) begin `checkh(s.getc(-1), 0); `checkh(s.getc(4), 0); `checkh(s.getc(2), "z"); s="ab3CD"; end else if (cyc==8) begin `checks(s.toupper(), "AB3CD"); `checks(s.tolower(), "ab3cd"); s="b"; end else if (cyc==9) begin if (s.compare("a") <= 0) $stop; if (s.compare("b") != 0) $stop; if (s.compare("c") >= 0) $stop; if (s.compare("A") <= 0) $stop; if (s.compare("B") <= 0) $stop; if (s.compare("C") <= 0) $stop; if (s.icompare("A") < 0) $stop; if (s.icompare("B") != 0) $stop; if (s.icompare("C") >= 0) $stop; s="abcd"; end else if (cyc==10) begin `checks(s.substr(-1,1), ""); `checks(s.substr(1,0), ""); `checks(s.substr(1,4), ""); `checks(s.substr(2,3), "cd"); s="101"; end else if (cyc==11) begin `checkh(s.atoi(), 'd101); `checkh(s.atohex(), 'h101); `checkh(s.atooct(), 'o101); `checkh(s.atobin(), 'b101); s="1.23"; end else if (cyc==12) begin `checkg(s.atoreal(), 1.23); end else if (cyc==13) begin s.itoa(123); end else if (cyc==14) begin `checks(s, "123"); s.hextoa(123); end else if (cyc==15) begin `checks(s, "7b"); s.octtoa(123); end else if (cyc==16) begin `checks(s, "173"); s.bintoa(123); end else if (cyc==17) begin `checks(s, "1111011"); s.realtoa(1.23); end else if (cyc==18) begin `checks(s, "1.23"); end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_trace_rollover.out0000644000542200017500000014245115101701376023173 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $var wire 1 # clk $end $scope module t $end $var wire 1 # clk $end $var wire 32 $ cyc [31:0] $end $upscope $end $upscope $end $enddefinitions $end #0 1# b00000000000000000000000000000000 $ #1 0# #2 1# b00000000000000000000000000000001 $ #3 0# #4 1# b00000000000000000000000000000010 $ #5 0# #6 1# b00000000000000000000000000000011 $ #7 0# #8 1# b00000000000000000000000000000100 $ #9 0# #10 1# b00000000000000000000000000000101 $ #11 0# #12 1# b00000000000000000000000000000110 $ #13 0# #14 1# b00000000000000000000000000000111 $ #15 0# #16 1# b00000000000000000000000000001000 $ #17 0# #18 1# b00000000000000000000000000001001 $ #19 0# #20 1# b00000000000000000000000000001010 $ #21 0# #22 1# b00000000000000000000000000001011 $ #23 0# #24 1# b00000000000000000000000000001100 $ #25 0# #26 1# b00000000000000000000000000001101 $ #27 0# #28 1# b00000000000000000000000000001110 $ #29 0# #30 1# b00000000000000000000000000001111 $ #31 0# #32 1# b00000000000000000000000000010000 $ #33 0# #34 1# b00000000000000000000000000010001 $ #35 0# #36 1# b00000000000000000000000000010010 $ #37 0# #38 1# b00000000000000000000000000010011 $ #39 0# #40 1# b00000000000000000000000000010100 $ #41 0# #42 1# b00000000000000000000000000010101 $ #43 0# #44 1# b00000000000000000000000000010110 $ #45 0# #46 1# b00000000000000000000000000010111 $ #47 0# #48 1# b00000000000000000000000000011000 $ #49 0# #50 1# b00000000000000000000000000011001 $ #51 0# #52 1# b00000000000000000000000000011010 $ #53 0# #54 1# b00000000000000000000000000011011 $ #55 0# #56 1# b00000000000000000000000000011100 $ #57 0# #58 1# b00000000000000000000000000011101 $ #59 0# #60 1# b00000000000000000000000000011110 $ #61 0# #62 1# b00000000000000000000000000011111 $ #63 0# #64 1# b00000000000000000000000000100000 $ #65 0# #66 1# b00000000000000000000000000100001 $ #67 0# #68 1# b00000000000000000000000000100010 $ #69 0# #70 1# b00000000000000000000000000100011 $ #71 0# #72 1# b00000000000000000000000000100100 $ #73 0# #74 1# b00000000000000000000000000100101 $ #75 0# #76 1# b00000000000000000000000000100110 $ #77 0# #78 1# b00000000000000000000000000100111 $ #79 0# #80 1# b00000000000000000000000000101000 $ #81 0# #82 1# b00000000000000000000000000101001 $ #83 0# #84 1# b00000000000000000000000000101010 $ #85 0# #86 1# b00000000000000000000000000101011 $ #87 0# #88 1# b00000000000000000000000000101100 $ #89 0# #90 1# b00000000000000000000000000101101 $ #91 0# #92 1# b00000000000000000000000000101110 $ #93 0# #94 1# b00000000000000000000000000101111 $ #95 0# #96 1# b00000000000000000000000000110000 $ #97 0# #98 1# b00000000000000000000000000110001 $ #99 0# #100 1# b00000000000000000000000000110010 $ #101 0# #102 1# b00000000000000000000000000110011 $ #103 0# #104 1# b00000000000000000000000000110100 $ #105 0# #106 1# b00000000000000000000000000110101 $ #107 0# #108 1# b00000000000000000000000000110110 $ #109 0# #110 1# b00000000000000000000000000110111 $ #111 0# #112 1# b00000000000000000000000000111000 $ #113 0# #114 1# b00000000000000000000000000111001 $ #115 0# #116 1# b00000000000000000000000000111010 $ #117 0# #118 1# b00000000000000000000000000111011 $ #119 0# #120 1# b00000000000000000000000000111100 $ #121 0# #122 1# b00000000000000000000000000111101 $ #123 0# #124 1# b00000000000000000000000000111110 $ #125 0# #126 1# b00000000000000000000000000111111 $ #127 0# #128 1# b00000000000000000000000001000000 $ #129 0# #130 1# b00000000000000000000000001000001 $ #131 0# #132 1# b00000000000000000000000001000010 $ #133 0# #134 1# b00000000000000000000000001000011 $ #135 0# #136 1# b00000000000000000000000001000100 $ #137 0# #138 1# b00000000000000000000000001000101 $ #139 0# #140 1# b00000000000000000000000001000110 $ #141 0# #142 1# b00000000000000000000000001000111 $ #143 0# #144 1# b00000000000000000000000001001000 $ #145 0# #146 1# b00000000000000000000000001001001 $ #147 0# #148 1# b00000000000000000000000001001010 $ #149 0# #150 1# b00000000000000000000000001001011 $ #151 0# #152 1# b00000000000000000000000001001100 $ #153 0# #154 1# b00000000000000000000000001001101 $ #155 0# #156 1# b00000000000000000000000001001110 $ #157 0# #158 1# b00000000000000000000000001001111 $ #159 0# #160 1# b00000000000000000000000001010000 $ #161 0# #162 1# b00000000000000000000000001010001 $ #163 0# #164 1# b00000000000000000000000001010010 $ #165 0# #166 1# b00000000000000000000000001010011 $ #167 0# #168 1# b00000000000000000000000001010100 $ #169 0# #170 1# b00000000000000000000000001010101 $ #171 0# #172 1# b00000000000000000000000001010110 $ #173 0# #174 1# b00000000000000000000000001010111 $ #175 0# #176 1# b00000000000000000000000001011000 $ #177 0# #178 1# b00000000000000000000000001011001 $ #179 0# #180 1# b00000000000000000000000001011010 $ #181 0# #182 1# b00000000000000000000000001011011 $ #183 0# #184 1# b00000000000000000000000001011100 $ #185 0# #186 1# b00000000000000000000000001011101 $ #187 0# #188 1# b00000000000000000000000001011110 $ #189 0# #190 1# b00000000000000000000000001011111 $ #191 0# #192 1# b00000000000000000000000001100000 $ #193 0# #194 1# b00000000000000000000000001100001 $ #195 0# #196 1# b00000000000000000000000001100010 $ #197 0# #198 1# b00000000000000000000000001100011 $ #199 0# #200 1# b00000000000000000000000001100100 $ #201 0# #202 1# b00000000000000000000000001100101 $ #203 0# #204 1# b00000000000000000000000001100110 $ #205 0# #206 1# b00000000000000000000000001100111 $ #207 0# #208 1# b00000000000000000000000001101000 $ #209 0# #210 1# b00000000000000000000000001101001 $ #211 0# #212 1# b00000000000000000000000001101010 $ #213 0# #214 1# b00000000000000000000000001101011 $ #215 0# #216 1# b00000000000000000000000001101100 $ #217 0# #218 1# b00000000000000000000000001101101 $ #219 0# #220 1# b00000000000000000000000001101110 $ #221 0# #222 1# b00000000000000000000000001101111 $ #223 0# #224 1# b00000000000000000000000001110000 $ #225 0# #226 1# b00000000000000000000000001110001 $ #227 0# #228 1# b00000000000000000000000001110010 $ #229 0# #230 1# b00000000000000000000000001110011 $ #231 0# #232 1# b00000000000000000000000001110100 $ #233 0# #234 1# b00000000000000000000000001110101 $ #235 0# #236 1# b00000000000000000000000001110110 $ #237 0# #238 1# b00000000000000000000000001110111 $ #239 0# #240 1# b00000000000000000000000001111000 $ #241 0# #242 1# b00000000000000000000000001111001 $ #243 0# #244 1# b00000000000000000000000001111010 $ #245 0# #246 1# b00000000000000000000000001111011 $ #247 0# #248 1# b00000000000000000000000001111100 $ #249 0# #250 1# b00000000000000000000000001111101 $ #251 0# #252 1# b00000000000000000000000001111110 $ #253 0# #254 1# b00000000000000000000000001111111 $ #255 0# #256 1# b00000000000000000000000010000000 $ #257 0# #258 1# b00000000000000000000000010000001 $ #259 0# #260 1# b00000000000000000000000010000010 $ #261 0# #262 1# b00000000000000000000000010000011 $ #263 0# #264 1# b00000000000000000000000010000100 $ #265 0# #266 1# b00000000000000000000000010000101 $ #267 0# #268 1# b00000000000000000000000010000110 $ #269 0# #270 1# b00000000000000000000000010000111 $ #271 0# #272 1# b00000000000000000000000010001000 $ #273 0# #274 1# b00000000000000000000000010001001 $ #275 0# #276 1# b00000000000000000000000010001010 $ #277 0# #278 1# b00000000000000000000000010001011 $ #279 0# #280 1# b00000000000000000000000010001100 $ #281 0# #282 1# b00000000000000000000000010001101 $ #283 0# #284 1# b00000000000000000000000010001110 $ #285 0# #286 1# b00000000000000000000000010001111 $ #287 0# #288 1# b00000000000000000000000010010000 $ #289 0# #290 1# b00000000000000000000000010010001 $ #291 0# #292 1# b00000000000000000000000010010010 $ #293 0# #294 1# b00000000000000000000000010010011 $ #295 0# #296 1# b00000000000000000000000010010100 $ #297 0# #298 1# b00000000000000000000000010010101 $ #299 0# #300 1# b00000000000000000000000010010110 $ #301 0# #302 1# b00000000000000000000000010010111 $ #303 0# #304 1# b00000000000000000000000010011000 $ #305 0# #306 1# b00000000000000000000000010011001 $ #307 0# #308 1# b00000000000000000000000010011010 $ #309 0# #310 1# b00000000000000000000000010011011 $ #311 0# #312 1# b00000000000000000000000010011100 $ #313 0# #314 1# b00000000000000000000000010011101 $ #315 0# #316 1# b00000000000000000000000010011110 $ #317 0# #318 1# b00000000000000000000000010011111 $ #319 0# #320 1# b00000000000000000000000010100000 $ #321 0# #322 1# b00000000000000000000000010100001 $ #323 0# #324 1# b00000000000000000000000010100010 $ #325 0# #326 1# b00000000000000000000000010100011 $ #327 0# #328 1# b00000000000000000000000010100100 $ #329 0# #330 1# b00000000000000000000000010100101 $ #331 0# #332 1# b00000000000000000000000010100110 $ #333 0# #334 1# b00000000000000000000000010100111 $ #335 0# #336 1# b00000000000000000000000010101000 $ #337 0# #338 1# b00000000000000000000000010101001 $ #339 0# #340 1# b00000000000000000000000010101010 $ #341 0# #342 1# b00000000000000000000000010101011 $ #343 0# #344 1# b00000000000000000000000010101100 $ #345 0# #346 1# b00000000000000000000000010101101 $ #347 0# #348 1# b00000000000000000000000010101110 $ #349 0# #350 1# b00000000000000000000000010101111 $ #351 0# #352 1# b00000000000000000000000010110000 $ #353 0# #354 1# b00000000000000000000000010110001 $ #355 0# #356 1# b00000000000000000000000010110010 $ #357 0# #358 1# b00000000000000000000000010110011 $ #359 0# #360 1# b00000000000000000000000010110100 $ #361 0# #362 1# b00000000000000000000000010110101 $ #363 0# #364 1# b00000000000000000000000010110110 $ #365 0# #366 1# b00000000000000000000000010110111 $ #367 0# #368 1# b00000000000000000000000010111000 $ #369 0# #370 1# b00000000000000000000000010111001 $ #371 0# #372 1# b00000000000000000000000010111010 $ #373 0# #374 1# b00000000000000000000000010111011 $ #375 0# #376 1# b00000000000000000000000010111100 $ #377 0# #378 1# b00000000000000000000000010111101 $ #379 0# #380 1# b00000000000000000000000010111110 $ #381 0# #382 1# b00000000000000000000000010111111 $ #383 0# #384 1# b00000000000000000000000011000000 $ #385 0# #386 1# b00000000000000000000000011000001 $ #387 0# #388 1# b00000000000000000000000011000010 $ #389 0# #390 1# b00000000000000000000000011000011 $ #391 0# #392 1# b00000000000000000000000011000100 $ #393 0# #394 1# b00000000000000000000000011000101 $ #395 0# #396 1# b00000000000000000000000011000110 $ #397 0# #398 1# b00000000000000000000000011000111 $ #399 0# #400 1# b00000000000000000000000011001000 $ #401 0# #402 1# b00000000000000000000000011001001 $ #403 0# #404 1# b00000000000000000000000011001010 $ #405 0# #406 1# b00000000000000000000000011001011 $ #407 0# #408 1# b00000000000000000000000011001100 $ #409 0# #410 1# b00000000000000000000000011001101 $ #411 0# #412 1# b00000000000000000000000011001110 $ #413 0# #414 1# b00000000000000000000000011001111 $ #415 0# #416 1# b00000000000000000000000011010000 $ #417 0# #418 1# b00000000000000000000000011010001 $ #419 0# #420 1# b00000000000000000000000011010010 $ #421 0# #422 1# b00000000000000000000000011010011 $ #423 0# #424 1# b00000000000000000000000011010100 $ #425 0# #426 1# b00000000000000000000000011010101 $ #427 0# #428 1# b00000000000000000000000011010110 $ #429 0# #430 1# b00000000000000000000000011010111 $ #431 0# #432 1# b00000000000000000000000011011000 $ #433 0# #434 1# b00000000000000000000000011011001 $ #435 0# #436 1# b00000000000000000000000011011010 $ #437 0# #438 1# b00000000000000000000000011011011 $ #439 0# #440 1# b00000000000000000000000011011100 $ #441 0# #442 1# b00000000000000000000000011011101 $ #443 0# #444 1# b00000000000000000000000011011110 $ #445 0# #446 1# b00000000000000000000000011011111 $ #447 0# #448 1# b00000000000000000000000011100000 $ #449 0# #450 1# b00000000000000000000000011100001 $ #451 0# #452 1# b00000000000000000000000011100010 $ #453 0# #454 1# b00000000000000000000000011100011 $ #455 0# #456 1# b00000000000000000000000011100100 $ #457 0# #458 1# b00000000000000000000000011100101 $ #459 0# #460 1# b00000000000000000000000011100110 $ #461 0# #462 1# b00000000000000000000000011100111 $ #463 0# #464 1# b00000000000000000000000011101000 $ #465 0# #466 1# b00000000000000000000000011101001 $ #467 0# #468 1# b00000000000000000000000011101010 $ #469 0# #470 1# b00000000000000000000000011101011 $ #471 0# #472 1# b00000000000000000000000011101100 $ #473 0# #474 1# b00000000000000000000000011101101 $ #475 0# #476 1# b00000000000000000000000011101110 $ #477 0# #478 1# b00000000000000000000000011101111 $ #479 0# #480 1# b00000000000000000000000011110000 $ #481 0# #482 1# b00000000000000000000000011110001 $ #483 0# #484 1# b00000000000000000000000011110010 $ #485 0# #486 1# b00000000000000000000000011110011 $ #487 0# #488 1# b00000000000000000000000011110100 $ #489 0# #490 1# b00000000000000000000000011110101 $ #491 0# #492 1# b00000000000000000000000011110110 $ #493 0# #494 1# b00000000000000000000000011110111 $ #495 0# #496 1# b00000000000000000000000011111000 $ #497 0# #498 1# b00000000000000000000000011111001 $ #499 0# #500 1# b00000000000000000000000011111010 $ #501 0# #502 1# b00000000000000000000000011111011 $ #503 0# #504 1# b00000000000000000000000011111100 $ #505 0# #506 1# b00000000000000000000000011111101 $ #507 0# #508 1# b00000000000000000000000011111110 $ #509 0# #510 1# b00000000000000000000000011111111 $ #511 0# #512 1# b00000000000000000000000100000000 $ #513 0# #514 1# b00000000000000000000000100000001 $ #515 0# #516 1# b00000000000000000000000100000010 $ #517 0# #518 1# b00000000000000000000000100000011 $ #519 0# #520 1# b00000000000000000000000100000100 $ #521 0# #522 1# b00000000000000000000000100000101 $ #523 0# #524 1# b00000000000000000000000100000110 $ #525 0# #526 1# b00000000000000000000000100000111 $ #527 0# #528 1# b00000000000000000000000100001000 $ #529 0# #530 1# b00000000000000000000000100001001 $ #531 0# #532 1# b00000000000000000000000100001010 $ #533 0# #534 1# b00000000000000000000000100001011 $ #535 0# #536 1# b00000000000000000000000100001100 $ #537 0# #538 1# b00000000000000000000000100001101 $ #539 0# #540 1# b00000000000000000000000100001110 $ #541 0# #542 1# b00000000000000000000000100001111 $ #543 0# #544 1# b00000000000000000000000100010000 $ #545 0# #546 1# b00000000000000000000000100010001 $ #547 0# #548 1# b00000000000000000000000100010010 $ #549 0# #550 1# b00000000000000000000000100010011 $ #551 0# #552 1# b00000000000000000000000100010100 $ #553 0# #554 1# b00000000000000000000000100010101 $ #555 0# #556 1# b00000000000000000000000100010110 $ #557 0# #558 1# b00000000000000000000000100010111 $ #559 0# #560 1# b00000000000000000000000100011000 $ #561 0# #562 1# b00000000000000000000000100011001 $ #563 0# #564 1# b00000000000000000000000100011010 $ #565 0# #566 1# b00000000000000000000000100011011 $ #567 0# #568 1# b00000000000000000000000100011100 $ #569 0# #570 1# b00000000000000000000000100011101 $ #571 0# #572 1# b00000000000000000000000100011110 $ #573 0# #574 1# b00000000000000000000000100011111 $ #575 0# #576 1# b00000000000000000000000100100000 $ #577 0# #578 1# b00000000000000000000000100100001 $ #579 0# #580 1# b00000000000000000000000100100010 $ #581 0# #582 1# b00000000000000000000000100100011 $ #583 0# #584 1# b00000000000000000000000100100100 $ #585 0# #586 1# b00000000000000000000000100100101 $ #587 0# #588 1# b00000000000000000000000100100110 $ #589 0# #590 1# b00000000000000000000000100100111 $ #591 0# #592 1# b00000000000000000000000100101000 $ #593 0# #594 1# b00000000000000000000000100101001 $ #595 0# #596 1# b00000000000000000000000100101010 $ #597 0# #598 1# b00000000000000000000000100101011 $ #599 0# #600 1# b00000000000000000000000100101100 $ #601 0# #602 1# b00000000000000000000000100101101 $ #603 0# #604 1# b00000000000000000000000100101110 $ #605 0# #606 1# b00000000000000000000000100101111 $ #607 0# #608 1# b00000000000000000000000100110000 $ #609 0# #610 1# b00000000000000000000000100110001 $ #611 0# #612 1# b00000000000000000000000100110010 $ #613 0# #614 1# b00000000000000000000000100110011 $ #615 0# #616 1# b00000000000000000000000100110100 $ #617 0# #618 1# b00000000000000000000000100110101 $ #619 0# #620 1# b00000000000000000000000100110110 $ #621 0# #622 1# b00000000000000000000000100110111 $ #623 0# #624 1# b00000000000000000000000100111000 $ #625 0# #626 1# b00000000000000000000000100111001 $ #627 0# #628 1# b00000000000000000000000100111010 $ #629 0# #630 1# b00000000000000000000000100111011 $ #631 0# #632 1# b00000000000000000000000100111100 $ #633 0# #634 1# b00000000000000000000000100111101 $ #635 0# #636 1# b00000000000000000000000100111110 $ #637 0# #638 1# b00000000000000000000000100111111 $ #639 0# #640 1# b00000000000000000000000101000000 $ #641 0# #642 1# b00000000000000000000000101000001 $ #643 0# #644 1# b00000000000000000000000101000010 $ #645 0# #646 1# b00000000000000000000000101000011 $ #647 0# #648 1# b00000000000000000000000101000100 $ #649 0# #650 1# b00000000000000000000000101000101 $ #651 0# #652 1# b00000000000000000000000101000110 $ #653 0# #654 1# b00000000000000000000000101000111 $ #655 0# #656 1# b00000000000000000000000101001000 $ #657 0# #658 1# b00000000000000000000000101001001 $ #659 0# #660 1# b00000000000000000000000101001010 $ #661 0# #662 1# b00000000000000000000000101001011 $ #663 0# #664 1# b00000000000000000000000101001100 $ #665 0# #666 1# b00000000000000000000000101001101 $ #667 0# #668 1# b00000000000000000000000101001110 $ #669 0# #670 1# b00000000000000000000000101001111 $ #671 0# #672 1# b00000000000000000000000101010000 $ #673 0# #674 1# b00000000000000000000000101010001 $ #675 0# #676 1# b00000000000000000000000101010010 $ #677 0# #678 1# b00000000000000000000000101010011 $ #679 0# #680 1# b00000000000000000000000101010100 $ #681 0# #682 1# b00000000000000000000000101010101 $ #683 0# #684 1# b00000000000000000000000101010110 $ #685 0# #686 1# b00000000000000000000000101010111 $ #687 0# #688 1# b00000000000000000000000101011000 $ #689 0# #690 1# b00000000000000000000000101011001 $ #691 0# #692 1# b00000000000000000000000101011010 $ #693 0# #694 1# b00000000000000000000000101011011 $ #695 0# #696 1# b00000000000000000000000101011100 $ #697 0# #698 1# b00000000000000000000000101011101 $ #699 0# #700 1# b00000000000000000000000101011110 $ #701 0# #702 1# b00000000000000000000000101011111 $ #703 0# #704 1# b00000000000000000000000101100000 $ #705 0# #706 1# b00000000000000000000000101100001 $ #707 0# #708 1# b00000000000000000000000101100010 $ #709 0# #710 1# b00000000000000000000000101100011 $ #711 0# #712 1# b00000000000000000000000101100100 $ #713 0# #714 1# b00000000000000000000000101100101 $ #715 0# #716 1# b00000000000000000000000101100110 $ #717 0# #718 1# b00000000000000000000000101100111 $ #719 0# #720 1# b00000000000000000000000101101000 $ #721 0# #722 1# b00000000000000000000000101101001 $ #723 0# #724 1# b00000000000000000000000101101010 $ #725 0# #726 1# b00000000000000000000000101101011 $ #727 0# #728 1# b00000000000000000000000101101100 $ #729 0# #730 1# b00000000000000000000000101101101 $ #731 0# #732 1# b00000000000000000000000101101110 $ #733 0# #734 1# b00000000000000000000000101101111 $ #735 0# #736 1# b00000000000000000000000101110000 $ #737 0# #738 1# b00000000000000000000000101110001 $ #739 0# #740 1# b00000000000000000000000101110010 $ #741 0# #742 1# b00000000000000000000000101110011 $ #743 0# #744 1# b00000000000000000000000101110100 $ #745 0# #746 1# b00000000000000000000000101110101 $ #747 0# #748 1# b00000000000000000000000101110110 $ #749 0# #750 1# b00000000000000000000000101110111 $ #751 0# #752 1# b00000000000000000000000101111000 $ #753 0# #754 1# b00000000000000000000000101111001 $ #755 0# #756 1# b00000000000000000000000101111010 $ #757 0# #758 1# b00000000000000000000000101111011 $ #759 0# #760 1# b00000000000000000000000101111100 $ #761 0# #762 1# b00000000000000000000000101111101 $ #763 0# #764 1# b00000000000000000000000101111110 $ #765 0# #766 1# b00000000000000000000000101111111 $ #767 0# #768 1# b00000000000000000000000110000000 $ #769 0# #770 1# b00000000000000000000000110000001 $ #771 0# #772 1# b00000000000000000000000110000010 $ #773 0# #774 1# b00000000000000000000000110000011 $ #775 0# #776 1# b00000000000000000000000110000100 $ #777 0# #778 1# b00000000000000000000000110000101 $ #779 0# #780 1# b00000000000000000000000110000110 $ #781 0# #782 1# b00000000000000000000000110000111 $ #783 0# #784 1# b00000000000000000000000110001000 $ #785 0# #786 1# b00000000000000000000000110001001 $ #787 0# #788 1# b00000000000000000000000110001010 $ #789 0# #790 1# b00000000000000000000000110001011 $ #791 0# #792 1# b00000000000000000000000110001100 $ #793 0# #794 1# b00000000000000000000000110001101 $ #795 0# #796 1# b00000000000000000000000110001110 $ #797 0# #798 1# b00000000000000000000000110001111 $ #799 0# #800 1# b00000000000000000000000110010000 $ #801 0# #802 1# b00000000000000000000000110010001 $ #803 0# #804 1# b00000000000000000000000110010010 $ #805 0# #806 1# b00000000000000000000000110010011 $ #807 0# #808 1# b00000000000000000000000110010100 $ #809 0# #810 1# b00000000000000000000000110010101 $ #811 0# #812 1# b00000000000000000000000110010110 $ #813 0# #814 1# b00000000000000000000000110010111 $ #815 0# #816 1# b00000000000000000000000110011000 $ #817 0# #818 1# b00000000000000000000000110011001 $ #819 0# #820 1# b00000000000000000000000110011010 $ #821 0# #822 1# b00000000000000000000000110011011 $ #823 0# #824 1# b00000000000000000000000110011100 $ #825 0# #826 1# b00000000000000000000000110011101 $ #827 0# #828 1# b00000000000000000000000110011110 $ #829 0# #830 1# b00000000000000000000000110011111 $ #831 0# #832 1# b00000000000000000000000110100000 $ #833 0# #834 1# b00000000000000000000000110100001 $ #835 0# #836 1# b00000000000000000000000110100010 $ #837 0# #838 1# b00000000000000000000000110100011 $ #839 0# #840 1# b00000000000000000000000110100100 $ #841 0# #842 1# b00000000000000000000000110100101 $ #843 0# #844 1# b00000000000000000000000110100110 $ #845 0# #846 1# b00000000000000000000000110100111 $ #847 0# #848 1# b00000000000000000000000110101000 $ #849 0# #850 1# b00000000000000000000000110101001 $ #851 0# #852 1# b00000000000000000000000110101010 $ #853 0# #854 1# b00000000000000000000000110101011 $ #855 0# #856 1# b00000000000000000000000110101100 $ #857 0# #858 1# b00000000000000000000000110101101 $ #859 0# #860 1# b00000000000000000000000110101110 $ #861 0# #862 1# b00000000000000000000000110101111 $ #863 0# #864 1# b00000000000000000000000110110000 $ #865 0# #866 1# b00000000000000000000000110110001 $ #867 0# #868 1# b00000000000000000000000110110010 $ #869 0# #870 1# b00000000000000000000000110110011 $ #871 0# #872 1# b00000000000000000000000110110100 $ #873 0# #874 1# b00000000000000000000000110110101 $ #875 0# #876 1# b00000000000000000000000110110110 $ #877 0# #878 1# b00000000000000000000000110110111 $ #879 0# #880 1# b00000000000000000000000110111000 $ #881 0# #882 1# b00000000000000000000000110111001 $ #883 0# #884 1# b00000000000000000000000110111010 $ #885 0# #886 1# b00000000000000000000000110111011 $ #887 0# #888 1# b00000000000000000000000110111100 $ #889 0# #890 1# b00000000000000000000000110111101 $ #891 0# #892 1# b00000000000000000000000110111110 $ #893 0# #894 1# b00000000000000000000000110111111 $ #895 0# #896 1# b00000000000000000000000111000000 $ #897 0# #898 1# b00000000000000000000000111000001 $ #899 0# #900 1# b00000000000000000000000111000010 $ #901 0# #902 1# b00000000000000000000000111000011 $ #903 0# #904 1# b00000000000000000000000111000100 $ #905 0# #906 1# b00000000000000000000000111000101 $ #907 0# #908 1# b00000000000000000000000111000110 $ #909 0# #910 1# b00000000000000000000000111000111 $ #911 0# #912 1# b00000000000000000000000111001000 $ #913 0# #914 1# b00000000000000000000000111001001 $ #915 0# #916 1# b00000000000000000000000111001010 $ #917 0# #918 1# b00000000000000000000000111001011 $ #919 0# #920 1# b00000000000000000000000111001100 $ #921 0# #922 1# b00000000000000000000000111001101 $ #923 0# #924 1# b00000000000000000000000111001110 $ #925 0# #926 1# b00000000000000000000000111001111 $ #927 0# #928 1# b00000000000000000000000111010000 $ #929 0# #930 1# b00000000000000000000000111010001 $ #931 0# #932 1# b00000000000000000000000111010010 $ #933 0# #934 1# b00000000000000000000000111010011 $ #935 0# #936 1# b00000000000000000000000111010100 $ #937 0# #938 1# b00000000000000000000000111010101 $ #939 0# #940 1# b00000000000000000000000111010110 $ #941 0# #942 1# b00000000000000000000000111010111 $ #943 0# #944 1# b00000000000000000000000111011000 $ #945 0# #946 1# b00000000000000000000000111011001 $ #947 0# #948 1# b00000000000000000000000111011010 $ #949 0# #950 1# b00000000000000000000000111011011 $ #951 0# #952 1# b00000000000000000000000111011100 $ #953 0# #954 1# b00000000000000000000000111011101 $ #955 0# #956 1# b00000000000000000000000111011110 $ #957 0# #958 1# b00000000000000000000000111011111 $ #959 0# #960 1# b00000000000000000000000111100000 $ #961 0# #962 1# b00000000000000000000000111100001 $ #963 0# #964 1# b00000000000000000000000111100010 $ #965 0# #966 1# b00000000000000000000000111100011 $ #967 0# #968 1# b00000000000000000000000111100100 $ #969 0# #970 1# b00000000000000000000000111100101 $ #971 0# #972 1# b00000000000000000000000111100110 $ #973 0# #974 1# b00000000000000000000000111100111 $ #975 0# #976 1# b00000000000000000000000111101000 $ #977 0# #978 1# b00000000000000000000000111101001 $ #979 0# #980 1# b00000000000000000000000111101010 $ #981 0# #982 1# b00000000000000000000000111101011 $ #983 0# #984 1# b00000000000000000000000111101100 $ #985 0# #986 1# b00000000000000000000000111101101 $ #987 0# #988 1# b00000000000000000000000111101110 $ #989 0# #990 1# b00000000000000000000000111101111 $ #991 0# #992 1# b00000000000000000000000111110000 $ #993 0# #994 1# b00000000000000000000000111110001 $ #995 0# #996 1# b00000000000000000000000111110010 $ #997 0# #998 1# b00000000000000000000000111110011 $ #999 0# #1000 1# b00000000000000000000000111110100 $ #1001 0# #1002 1# b00000000000000000000000111110101 $ #1003 0# #1004 1# b00000000000000000000000111110110 $ #1005 0# #1006 1# b00000000000000000000000111110111 $ #1007 0# #1008 1# b00000000000000000000000111111000 $ #1009 0# #1010 1# b00000000000000000000000111111001 $ #1011 0# #1012 1# b00000000000000000000000111111010 $ #1013 0# #1014 1# b00000000000000000000000111111011 $ #1015 0# #1016 1# b00000000000000000000000111111100 $ #1017 0# #1018 1# b00000000000000000000000111111101 $ #1019 0# #1020 1# b00000000000000000000000111111110 $ #1021 0# #1022 1# b00000000000000000000000111111111 $ #1023 0# #1024 1# b00000000000000000000001000000000 $ #1025 0# #1026 1# b00000000000000000000001000000001 $ #1027 0# #1028 1# b00000000000000000000001000000010 $ #1029 0# #1030 1# b00000000000000000000001000000011 $ #1031 0# #1032 1# b00000000000000000000001000000100 $ #1033 0# #1034 1# b00000000000000000000001000000101 $ #1035 0# #1036 1# b00000000000000000000001000000110 $ #1037 0# #1038 1# b00000000000000000000001000000111 $ #1039 0# #1040 1# b00000000000000000000001000001000 $ #1041 0# #1042 1# b00000000000000000000001000001001 $ #1043 0# #1044 1# b00000000000000000000001000001010 $ #1045 0# #1046 1# b00000000000000000000001000001011 $ #1047 0# #1048 1# b00000000000000000000001000001100 $ #1049 0# #1050 1# b00000000000000000000001000001101 $ #1051 0# #1052 1# b00000000000000000000001000001110 $ #1053 0# #1054 1# b00000000000000000000001000001111 $ #1055 0# #1056 1# b00000000000000000000001000010000 $ #1057 0# #1058 1# b00000000000000000000001000010001 $ #1059 0# #1060 1# b00000000000000000000001000010010 $ #1061 0# #1062 1# b00000000000000000000001000010011 $ #1063 0# #1064 1# b00000000000000000000001000010100 $ #1065 0# #1066 1# b00000000000000000000001000010101 $ #1067 0# #1068 1# b00000000000000000000001000010110 $ #1069 0# #1070 1# b00000000000000000000001000010111 $ #1071 0# #1072 1# b00000000000000000000001000011000 $ #1073 0# #1074 1# b00000000000000000000001000011001 $ #1075 0# #1076 1# b00000000000000000000001000011010 $ #1077 0# #1078 1# b00000000000000000000001000011011 $ #1079 0# #1080 1# b00000000000000000000001000011100 $ #1081 0# #1082 1# b00000000000000000000001000011101 $ #1083 0# #1084 1# b00000000000000000000001000011110 $ #1085 0# #1086 1# b00000000000000000000001000011111 $ #1087 0# #1088 1# b00000000000000000000001000100000 $ #1089 0# #1090 1# b00000000000000000000001000100001 $ #1091 0# #1092 1# b00000000000000000000001000100010 $ #1093 0# #1094 1# b00000000000000000000001000100011 $ #1095 0# #1096 1# b00000000000000000000001000100100 $ #1097 0# #1098 1# b00000000000000000000001000100101 $ #1099 0# #1100 1# b00000000000000000000001000100110 $ #1101 0# #1102 1# b00000000000000000000001000100111 $ #1103 0# #1104 1# b00000000000000000000001000101000 $ #1105 0# #1106 1# b00000000000000000000001000101001 $ #1107 0# #1108 1# b00000000000000000000001000101010 $ #1109 0# #1110 1# b00000000000000000000001000101011 $ #1111 0# #1112 1# b00000000000000000000001000101100 $ #1113 0# #1114 1# b00000000000000000000001000101101 $ #1115 0# #1116 1# b00000000000000000000001000101110 $ #1117 0# #1118 1# b00000000000000000000001000101111 $ #1119 0# #1120 1# b00000000000000000000001000110000 $ #1121 0# #1122 1# b00000000000000000000001000110001 $ #1123 0# #1124 1# b00000000000000000000001000110010 $ #1125 0# #1126 1# b00000000000000000000001000110011 $ #1127 0# #1128 1# b00000000000000000000001000110100 $ #1129 0# #1130 1# b00000000000000000000001000110101 $ #1131 0# #1132 1# b00000000000000000000001000110110 $ #1133 0# #1134 1# b00000000000000000000001000110111 $ #1135 0# #1136 1# b00000000000000000000001000111000 $ #1137 0# #1138 1# b00000000000000000000001000111001 $ #1139 0# #1140 1# b00000000000000000000001000111010 $ #1141 0# #1142 1# b00000000000000000000001000111011 $ #1143 0# #1144 1# b00000000000000000000001000111100 $ #1145 0# #1146 1# b00000000000000000000001000111101 $ #1147 0# #1148 1# b00000000000000000000001000111110 $ #1149 0# #1150 1# b00000000000000000000001000111111 $ #1151 0# #1152 1# b00000000000000000000001001000000 $ #1153 0# #1154 1# b00000000000000000000001001000001 $ #1155 0# #1156 1# b00000000000000000000001001000010 $ #1157 0# #1158 1# b00000000000000000000001001000011 $ #1159 0# #1160 1# b00000000000000000000001001000100 $ #1161 0# #1162 1# b00000000000000000000001001000101 $ #1163 0# #1164 1# b00000000000000000000001001000110 $ #1165 0# #1166 1# b00000000000000000000001001000111 $ #1167 0# #1168 1# b00000000000000000000001001001000 $ #1169 0# #1170 1# b00000000000000000000001001001001 $ #1171 0# #1172 1# b00000000000000000000001001001010 $ #1173 0# #1174 1# b00000000000000000000001001001011 $ #1175 0# #1176 1# b00000000000000000000001001001100 $ #1177 0# #1178 1# b00000000000000000000001001001101 $ #1179 0# #1180 1# b00000000000000000000001001001110 $ #1181 0# #1182 1# b00000000000000000000001001001111 $ #1183 0# #1184 1# b00000000000000000000001001010000 $ #1185 0# #1186 1# b00000000000000000000001001010001 $ #1187 0# #1188 1# b00000000000000000000001001010010 $ #1189 0# #1190 1# b00000000000000000000001001010011 $ #1191 0# #1192 1# b00000000000000000000001001010100 $ #1193 0# #1194 1# b00000000000000000000001001010101 $ #1195 0# #1196 1# b00000000000000000000001001010110 $ #1197 0# #1198 1# b00000000000000000000001001010111 $ #1199 0# #1200 1# b00000000000000000000001001011000 $ #1201 0# #1202 1# b00000000000000000000001001011001 $ #1203 0# #1204 1# b00000000000000000000001001011010 $ #1205 0# #1206 1# b00000000000000000000001001011011 $ #1207 0# #1208 1# b00000000000000000000001001011100 $ #1209 0# #1210 1# b00000000000000000000001001011101 $ #1211 0# #1212 1# b00000000000000000000001001011110 $ #1213 0# #1214 1# b00000000000000000000001001011111 $ #1215 0# #1216 1# b00000000000000000000001001100000 $ #1217 0# #1218 1# b00000000000000000000001001100001 $ #1219 0# #1220 1# b00000000000000000000001001100010 $ #1221 0# #1222 1# b00000000000000000000001001100011 $ #1223 0# #1224 1# b00000000000000000000001001100100 $ #1225 0# #1226 1# b00000000000000000000001001100101 $ #1227 0# #1228 1# b00000000000000000000001001100110 $ #1229 0# #1230 1# b00000000000000000000001001100111 $ #1231 0# #1232 1# b00000000000000000000001001101000 $ #1233 0# #1234 1# b00000000000000000000001001101001 $ #1235 0# #1236 1# b00000000000000000000001001101010 $ #1237 0# #1238 1# b00000000000000000000001001101011 $ #1239 0# #1240 1# b00000000000000000000001001101100 $ #1241 0# #1242 1# b00000000000000000000001001101101 $ #1243 0# #1244 1# b00000000000000000000001001101110 $ #1245 0# #1246 1# b00000000000000000000001001101111 $ #1247 0# #1248 1# b00000000000000000000001001110000 $ #1249 0# #1250 1# b00000000000000000000001001110001 $ #1251 0# #1252 1# b00000000000000000000001001110010 $ #1253 0# #1254 1# b00000000000000000000001001110011 $ #1255 0# #1256 1# b00000000000000000000001001110100 $ #1257 0# #1258 1# b00000000000000000000001001110101 $ #1259 0# #1260 1# b00000000000000000000001001110110 $ #1261 0# #1262 1# b00000000000000000000001001110111 $ #1263 0# #1264 1# b00000000000000000000001001111000 $ #1265 0# #1266 1# b00000000000000000000001001111001 $ #1267 0# #1268 1# b00000000000000000000001001111010 $ #1269 0# #1270 1# b00000000000000000000001001111011 $ #1271 0# #1272 1# b00000000000000000000001001111100 $ #1273 0# #1274 1# b00000000000000000000001001111101 $ #1275 0# #1276 1# b00000000000000000000001001111110 $ #1277 0# #1278 1# b00000000000000000000001001111111 $ #1279 0# #1280 1# b00000000000000000000001010000000 $ #1281 0# #1282 1# b00000000000000000000001010000001 $ #1283 0# #1284 1# b00000000000000000000001010000010 $ #1285 0# #1286 1# b00000000000000000000001010000011 $ #1287 0# #1288 1# b00000000000000000000001010000100 $ #1289 0# #1290 1# b00000000000000000000001010000101 $ #1291 0# #1292 1# b00000000000000000000001010000110 $ #1293 0# #1294 1# b00000000000000000000001010000111 $ #1295 0# #1296 1# b00000000000000000000001010001000 $ #1297 0# #1298 1# b00000000000000000000001010001001 $ #1299 0# #1300 1# b00000000000000000000001010001010 $ #1301 0# #1302 1# b00000000000000000000001010001011 $ #1303 0# #1304 1# b00000000000000000000001010001100 $ #1305 0# #1306 1# b00000000000000000000001010001101 $ #1307 0# #1308 1# b00000000000000000000001010001110 $ #1309 0# #1310 1# b00000000000000000000001010001111 $ #1311 0# #1312 1# b00000000000000000000001010010000 $ #1313 0# #1314 1# b00000000000000000000001010010001 $ #1315 0# #1316 1# b00000000000000000000001010010010 $ #1317 0# #1318 1# b00000000000000000000001010010011 $ #1319 0# #1320 1# b00000000000000000000001010010100 $ #1321 0# #1322 1# b00000000000000000000001010010101 $ #1323 0# #1324 1# b00000000000000000000001010010110 $ #1325 0# #1326 1# b00000000000000000000001010010111 $ #1327 0# #1328 1# b00000000000000000000001010011000 $ #1329 0# #1330 1# b00000000000000000000001010011001 $ #1331 0# #1332 1# b00000000000000000000001010011010 $ #1333 0# #1334 1# b00000000000000000000001010011011 $ #1335 0# #1336 1# b00000000000000000000001010011100 $ #1337 0# #1338 1# b00000000000000000000001010011101 $ #1339 0# #1340 1# b00000000000000000000001010011110 $ #1341 0# #1342 1# b00000000000000000000001010011111 $ #1343 0# #1344 1# b00000000000000000000001010100000 $ #1345 0# #1346 1# b00000000000000000000001010100001 $ #1347 0# #1348 1# b00000000000000000000001010100010 $ #1349 0# #1350 1# b00000000000000000000001010100011 $ #1351 0# #1352 1# b00000000000000000000001010100100 $ #1353 0# #1354 1# b00000000000000000000001010100101 $ #1355 0# #1356 1# b00000000000000000000001010100110 $ #1357 0# #1358 1# b00000000000000000000001010100111 $ #1359 0# #1360 1# b00000000000000000000001010101000 $ #1361 0# #1362 1# b00000000000000000000001010101001 $ #1363 0# #1364 1# b00000000000000000000001010101010 $ #1365 0# #1366 1# b00000000000000000000001010101011 $ #1367 0# #1368 1# b00000000000000000000001010101100 $ #1369 0# #1370 1# b00000000000000000000001010101101 $ #1371 0# #1372 1# b00000000000000000000001010101110 $ #1373 0# #1374 1# b00000000000000000000001010101111 $ #1375 0# #1376 1# b00000000000000000000001010110000 $ #1377 0# #1378 1# b00000000000000000000001010110001 $ #1379 0# #1380 1# b00000000000000000000001010110010 $ #1381 0# #1382 1# b00000000000000000000001010110011 $ #1383 0# #1384 1# b00000000000000000000001010110100 $ #1385 0# #1386 1# b00000000000000000000001010110101 $ #1387 0# #1388 1# b00000000000000000000001010110110 $ #1389 0# #1390 1# b00000000000000000000001010110111 $ #1391 0# #1392 1# b00000000000000000000001010111000 $ #1393 0# #1394 1# b00000000000000000000001010111001 $ #1395 0# #1396 1# b00000000000000000000001010111010 $ #1397 0# #1398 1# b00000000000000000000001010111011 $ #1399 0# #1400 1# b00000000000000000000001010111100 $ #1401 0# #1402 1# b00000000000000000000001010111101 $ #1403 0# #1404 1# b00000000000000000000001010111110 $ #1405 0# #1406 1# b00000000000000000000001010111111 $ #1407 0# #1408 1# b00000000000000000000001011000000 $ #1409 0# #1410 1# b00000000000000000000001011000001 $ #1411 0# #1412 1# b00000000000000000000001011000010 $ #1413 0# #1414 1# b00000000000000000000001011000011 $ #1415 0# #1416 1# b00000000000000000000001011000100 $ #1417 0# #1418 1# b00000000000000000000001011000101 $ #1419 0# #1420 1# b00000000000000000000001011000110 $ #1421 0# #1422 1# b00000000000000000000001011000111 $ #1423 0# #1424 1# b00000000000000000000001011001000 $ #1425 0# #1426 1# b00000000000000000000001011001001 $ #1427 0# #1428 1# b00000000000000000000001011001010 $ #1429 0# #1430 1# b00000000000000000000001011001011 $ #1431 0# #1432 1# b00000000000000000000001011001100 $ #1433 0# #1434 1# b00000000000000000000001011001101 $ #1435 0# #1436 1# b00000000000000000000001011001110 $ #1437 0# #1438 1# b00000000000000000000001011001111 $ #1439 0# #1440 1# b00000000000000000000001011010000 $ #1441 0# #1442 1# b00000000000000000000001011010001 $ #1443 0# #1444 1# b00000000000000000000001011010010 $ #1445 0# #1446 1# b00000000000000000000001011010011 $ #1447 0# #1448 1# b00000000000000000000001011010100 $ #1449 0# #1450 1# b00000000000000000000001011010101 $ #1451 0# #1452 1# b00000000000000000000001011010110 $ #1453 0# #1454 1# b00000000000000000000001011010111 $ #1455 0# #1456 1# b00000000000000000000001011011000 $ #1457 0# #1458 1# b00000000000000000000001011011001 $ #1459 0# #1460 1# b00000000000000000000001011011010 $ #1461 0# #1462 1# b00000000000000000000001011011011 $ #1463 0# #1464 1# b00000000000000000000001011011100 $ #1465 0# #1466 1# b00000000000000000000001011011101 $ #1467 0# #1468 1# b00000000000000000000001011011110 $ #1469 0# #1470 1# b00000000000000000000001011011111 $ #1471 0# #1472 1# b00000000000000000000001011100000 $ #1473 0# #1474 1# b00000000000000000000001011100001 $ #1475 0# #1476 1# b00000000000000000000001011100010 $ #1477 0# #1478 1# b00000000000000000000001011100011 $ #1479 0# #1480 1# b00000000000000000000001011100100 $ #1481 0# #1482 1# b00000000000000000000001011100101 $ #1483 0# #1484 1# b00000000000000000000001011100110 $ #1485 0# #1486 1# b00000000000000000000001011100111 $ #1487 0# #1488 1# b00000000000000000000001011101000 $ #1489 0# #1490 1# b00000000000000000000001011101001 $ #1491 0# #1492 1# b00000000000000000000001011101010 $ #1493 0# #1494 1# b00000000000000000000001011101011 $ #1495 0# #1496 1# b00000000000000000000001011101100 $ #1497 0# #1498 1# b00000000000000000000001011101101 $ #1499 0# #1500 1# b00000000000000000000001011101110 $ #1501 0# #1502 1# b00000000000000000000001011101111 $ #1503 0# #1504 1# b00000000000000000000001011110000 $ #1505 0# #1506 1# b00000000000000000000001011110001 $ #1507 0# #1508 1# b00000000000000000000001011110010 $ #1509 0# #1510 1# b00000000000000000000001011110011 $ #1511 0# #1512 1# b00000000000000000000001011110100 $ #1513 0# #1514 1# b00000000000000000000001011110101 $ #1515 0# #1516 1# b00000000000000000000001011110110 $ #1517 0# #1518 1# b00000000000000000000001011110111 $ #1519 0# #1520 1# b00000000000000000000001011111000 $ #1521 0# #1522 1# b00000000000000000000001011111001 $ #1523 0# #1524 1# b00000000000000000000001011111010 $ #1525 0# #1526 1# b00000000000000000000001011111011 $ #1527 0# #1528 1# b00000000000000000000001011111100 $ #1529 0# #1530 1# b00000000000000000000001011111101 $ #1531 0# #1532 1# b00000000000000000000001011111110 $ #1533 0# #1534 1# b00000000000000000000001011111111 $ #1535 0# #1536 1# b00000000000000000000001100000000 $ #1537 0# #1538 1# b00000000000000000000001100000001 $ #1539 0# #1540 1# b00000000000000000000001100000010 $ #1541 0# #1542 1# b00000000000000000000001100000011 $ #1543 0# #1544 1# b00000000000000000000001100000100 $ #1545 0# #1546 1# b00000000000000000000001100000101 $ #1547 0# #1548 1# b00000000000000000000001100000110 $ #1549 0# #1550 1# b00000000000000000000001100000111 $ #1551 0# #1552 1# b00000000000000000000001100001000 $ #1553 0# #1554 1# b00000000000000000000001100001001 $ #1555 0# #1556 1# b00000000000000000000001100001010 $ #1557 0# #1558 1# b00000000000000000000001100001011 $ #1559 0# #1560 1# b00000000000000000000001100001100 $ #1561 0# #1562 1# b00000000000000000000001100001101 $ #1563 0# #1564 1# b00000000000000000000001100001110 $ #1565 0# #1566 1# b00000000000000000000001100001111 $ #1567 0# #1568 1# b00000000000000000000001100010000 $ #1569 0# #1570 1# b00000000000000000000001100010001 $ #1571 0# #1572 1# b00000000000000000000001100010010 $ #1573 0# #1574 1# b00000000000000000000001100010011 $ #1575 0# #1576 1# b00000000000000000000001100010100 $ #1577 0# #1578 1# b00000000000000000000001100010101 $ #1579 0# #1580 1# b00000000000000000000001100010110 $ #1581 0# #1582 1# b00000000000000000000001100010111 $ #1583 0# #1584 1# b00000000000000000000001100011000 $ #1585 0# #1586 1# b00000000000000000000001100011001 $ #1587 0# #1588 1# b00000000000000000000001100011010 $ #1589 0# #1590 1# b00000000000000000000001100011011 $ #1591 0# #1592 1# b00000000000000000000001100011100 $ #1593 0# #1594 1# b00000000000000000000001100011101 $ #1595 0# #1596 1# b00000000000000000000001100011110 $ #1597 0# #1598 1# b00000000000000000000001100011111 $ #1599 0# #1600 1# b00000000000000000000001100100000 $ #1601 0# #1602 1# b00000000000000000000001100100001 $ #1603 0# #1604 1# b00000000000000000000001100100010 $ #1605 0# #1606 1# b00000000000000000000001100100011 $ #1607 0# #1608 1# b00000000000000000000001100100100 $ #1609 0# #1610 1# b00000000000000000000001100100101 $ #1611 0# #1612 1# b00000000000000000000001100100110 $ #1613 0# #1614 1# b00000000000000000000001100100111 $ #1615 0# #1616 1# b00000000000000000000001100101000 $ #1617 0# #1618 1# b00000000000000000000001100101001 $ #1619 0# #1620 1# b00000000000000000000001100101010 $ #1621 0# #1622 1# b00000000000000000000001100101011 $ #1623 0# #1624 1# b00000000000000000000001100101100 $ #1625 0# #1626 1# b00000000000000000000001100101101 $ #1627 0# #1628 1# b00000000000000000000001100101110 $ #1629 0# #1630 1# b00000000000000000000001100101111 $ #1631 0# #1632 1# b00000000000000000000001100110000 $ #1633 0# #1634 1# b00000000000000000000001100110001 $ #1635 0# #1636 1# b00000000000000000000001100110010 $ #1637 0# #1638 1# b00000000000000000000001100110011 $ #1639 0# #1640 1# b00000000000000000000001100110100 $ #1641 0# #1642 1# b00000000000000000000001100110101 $ #1643 0# #1644 1# b00000000000000000000001100110110 $ #1645 0# #1646 1# b00000000000000000000001100110111 $ #1647 0# #1648 1# b00000000000000000000001100111000 $ #1649 0# #1650 1# b00000000000000000000001100111001 $ #1651 0# #1652 1# b00000000000000000000001100111010 $ #1653 0# #1654 1# b00000000000000000000001100111011 $ #1655 0# #1656 1# b00000000000000000000001100111100 $ #1657 0# #1658 1# b00000000000000000000001100111101 $ #1659 0# #1660 1# b00000000000000000000001100111110 $ #1661 0# #1662 1# b00000000000000000000001100111111 $ #1663 0# #1664 1# b00000000000000000000001101000000 $ #1665 0# #1666 1# b00000000000000000000001101000001 $ #1667 0# #1668 1# b00000000000000000000001101000010 $ #1669 0# #1670 1# b00000000000000000000001101000011 $ #1671 0# #1672 1# b00000000000000000000001101000100 $ #1673 0# #1674 1# b00000000000000000000001101000101 $ #1675 0# #1676 1# b00000000000000000000001101000110 $ #1677 0# #1678 1# b00000000000000000000001101000111 $ #1679 0# #1680 1# b00000000000000000000001101001000 $ #1681 0# #1682 1# b00000000000000000000001101001001 $ #1683 0# #1684 1# b00000000000000000000001101001010 $ #1685 0# #1686 1# b00000000000000000000001101001011 $ #1687 0# #1688 1# b00000000000000000000001101001100 $ #1689 0# #1690 1# b00000000000000000000001101001101 $ #1691 0# #1692 1# b00000000000000000000001101001110 $ #1693 0# #1694 1# b00000000000000000000001101001111 $ #1695 0# #1696 1# b00000000000000000000001101010000 $ #1697 0# #1698 1# b00000000000000000000001101010001 $ #1699 0# #1700 1# b00000000000000000000001101010010 $ #1701 0# #1702 1# b00000000000000000000001101010011 $ #1703 0# #1704 1# b00000000000000000000001101010100 $ #1705 0# #1706 1# b00000000000000000000001101010101 $ #1707 0# #1708 1# b00000000000000000000001101010110 $ #1709 0# #1710 1# b00000000000000000000001101010111 $ #1711 0# #1712 1# b00000000000000000000001101011000 $ #1713 0# #1714 1# b00000000000000000000001101011001 $ #1715 0# #1716 1# b00000000000000000000001101011010 $ #1717 0# #1718 1# b00000000000000000000001101011011 $ #1719 0# #1720 1# b00000000000000000000001101011100 $ #1721 0# #1722 1# b00000000000000000000001101011101 $ #1723 0# #1724 1# b00000000000000000000001101011110 $ #1725 0# #1726 1# b00000000000000000000001101011111 $ #1727 0# #1728 1# b00000000000000000000001101100000 $ #1729 0# #1730 1# b00000000000000000000001101100001 $ #1731 0# #1732 1# b00000000000000000000001101100010 $ #1733 0# #1734 1# b00000000000000000000001101100011 $ #1735 0# #1736 1# b00000000000000000000001101100100 $ #1737 0# #1738 1# b00000000000000000000001101100101 $ #1739 0# #1740 1# b00000000000000000000001101100110 $ #1741 0# #1742 1# b00000000000000000000001101100111 $ #1743 0# #1744 1# b00000000000000000000001101101000 $ #1745 0# #1746 1# b00000000000000000000001101101001 $ #1747 0# #1748 1# b00000000000000000000001101101010 $ #1749 0# #1750 1# b00000000000000000000001101101011 $ #1751 0# #1752 1# b00000000000000000000001101101100 $ #1753 0# #1754 1# b00000000000000000000001101101101 $ #1755 0# #1756 1# b00000000000000000000001101101110 $ #1757 0# #1758 1# b00000000000000000000001101101111 $ #1759 0# #1760 1# b00000000000000000000001101110000 $ #1761 0# #1762 1# b00000000000000000000001101110001 $ #1763 0# #1764 1# b00000000000000000000001101110010 $ #1765 0# #1766 1# b00000000000000000000001101110011 $ #1767 0# #1768 1# b00000000000000000000001101110100 $ #1769 0# #1770 1# b00000000000000000000001101110101 $ #1771 0# #1772 1# b00000000000000000000001101110110 $ #1773 0# #1774 1# b00000000000000000000001101110111 $ #1775 0# #1776 1# b00000000000000000000001101111000 $ #1777 0# #1778 1# b00000000000000000000001101111001 $ #1779 0# #1780 1# b00000000000000000000001101111010 $ #1781 0# #1782 1# b00000000000000000000001101111011 $ #1783 0# #1784 1# b00000000000000000000001101111100 $ #1785 0# #1786 1# b00000000000000000000001101111101 $ #1787 0# #1788 1# b00000000000000000000001101111110 $ #1789 0# #1790 1# b00000000000000000000001101111111 $ #1791 0# #1792 1# b00000000000000000000001110000000 $ #1793 0# #1794 1# b00000000000000000000001110000001 $ #1795 0# #1796 1# b00000000000000000000001110000010 $ #1797 0# #1798 1# b00000000000000000000001110000011 $ #1799 0# #1800 1# b00000000000000000000001110000100 $ #1801 0# #1802 1# b00000000000000000000001110000101 $ #1803 0# #1804 1# b00000000000000000000001110000110 $ #1805 0# #1806 1# b00000000000000000000001110000111 $ #1807 0# #1808 1# b00000000000000000000001110001000 $ #1809 0# #1810 1# b00000000000000000000001110001001 $ #1811 0# #1812 1# b00000000000000000000001110001010 $ #1813 0# #1814 1# b00000000000000000000001110001011 $ #1815 0# #1816 1# b00000000000000000000001110001100 $ #1817 0# #1818 1# b00000000000000000000001110001101 $ #1819 0# #1820 1# b00000000000000000000001110001110 $ #1821 0# #1822 1# b00000000000000000000001110001111 $ #1823 0# #1824 1# b00000000000000000000001110010000 $ #1825 0# #1826 1# b00000000000000000000001110010001 $ #1827 0# #1828 1# b00000000000000000000001110010010 $ #1829 0# #1830 1# b00000000000000000000001110010011 $ #1831 0# #1832 1# b00000000000000000000001110010100 $ #1833 0# #1834 1# b00000000000000000000001110010101 $ #1835 0# #1836 1# b00000000000000000000001110010110 $ #1837 0# #1838 1# b00000000000000000000001110010111 $ #1839 0# #1840 1# b00000000000000000000001110011000 $ #1841 0# #1842 1# b00000000000000000000001110011001 $ #1843 0# #1844 1# b00000000000000000000001110011010 $ #1845 0# #1846 1# b00000000000000000000001110011011 $ #1847 0# #1848 1# b00000000000000000000001110011100 $ #1849 0# #1850 1# b00000000000000000000001110011101 $ #1851 0# #1852 1# b00000000000000000000001110011110 $ #1853 0# #1854 1# b00000000000000000000001110011111 $ #1855 0# #1856 1# b00000000000000000000001110100000 $ #1857 0# #1858 1# b00000000000000000000001110100001 $ #1859 0# #1860 1# b00000000000000000000001110100010 $ #1861 0# b00000000000000000000001110100010 $ #1862 1# b00000000000000000000001110100011 $ #1863 0# #1864 1# b00000000000000000000001110100100 $ #1865 0# #1866 1# b00000000000000000000001110100101 $ #1867 0# #1868 1# b00000000000000000000001110100110 $ #1869 0# #1870 1# b00000000000000000000001110100111 $ #1871 0# #1872 1# b00000000000000000000001110101000 $ #1873 0# #1874 1# b00000000000000000000001110101001 $ #1875 0# #1876 1# b00000000000000000000001110101010 $ #1877 0# #1878 1# b00000000000000000000001110101011 $ #1879 0# #1880 1# b00000000000000000000001110101100 $ #1881 0# #1882 1# b00000000000000000000001110101101 $ #1883 0# #1884 1# b00000000000000000000001110101110 $ #1885 0# #1886 1# b00000000000000000000001110101111 $ #1887 0# #1888 1# b00000000000000000000001110110000 $ #1889 0# #1890 1# b00000000000000000000001110110001 $ #1891 0# #1892 1# b00000000000000000000001110110010 $ #1893 0# #1894 1# b00000000000000000000001110110011 $ #1895 0# #1896 1# b00000000000000000000001110110100 $ #1897 0# #1898 1# b00000000000000000000001110110101 $ #1899 0# verilator-5.042/test_regress/t/t_dfg_3872.py0000755000542200017500000000070615101701376021214 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.passes() verilator-5.042/test_regress/t/t_fuzz_negwidth_bad.v0000644000542200017500000000051515101701376023276 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 int a = -12'd1; int b = 65536'd1; int c = 1231232312312312'd1; int e = 12'1; int f = 12'0; int g = 12'z; int h = 12'x; verilator-5.042/test_regress/t/t_tri_and_eqcase.out0000644000542200017500000000110115101701376023074 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_tri_and_eqcase.v:9:29: Unsupported tristate construct: AND in function getEnExprBasedOnOriginalp 9 | logic b = 1'bz === (clk1 & clk2); | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Internal Error: t/t_tri_and_eqcase.v:9:19: ../V3Ast.cpp:#: Null item passed to setOp2p 9 | logic b = 1'bz === (clk1 & clk2); | ^~~ ... This fatal error may be caused by the earlier error(s); resolve those first. verilator-5.042/test_regress/t/t_vlcov_flag_invalid_bad.py0000755000542200017500000000123315101701376024423 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.run(cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", '--invalid-dash'], logfile=test.run_log_filename, fails=True, expect_filename=test.golden_filename, verilator_run=True) test.passes() verilator-5.042/test_regress/t/t_interface_generic_array.py0000755000542200017500000000077115101701376024625 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--timing']) test.execute() test.passes() verilator-5.042/test_regress/t/t_struct_notfound_bad.py0000755000542200017500000000076615101701376024045 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_array_pattern_packed.v0000644000542200017500000001543615101701376023773 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2009 by Iztok Jeras. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; logic [1:0] [3:0] [3:0] array_simp; // descending range array logic [3:0] array_oned; initial begin array_oned = '{2:1'b1, 0:1'b1, default:1'b0}; if (array_oned != 4'b0101) $stop; array_simp[0] = '{ 4'd3, 4'd2, 4'd1, 4'd0}; if (array_simp[0] !== 16'h3210) $stop; // verilator lint_off WIDTH array_simp[0] = '{ 3 ,2 ,1, 0 }; // verilator lint_on WIDTH if (array_simp[0] !== 16'h3210) $stop; // Doesn't seem to work for unpacked arrays in other simulators //if (array_simp[0] !== 16'h3210) $stop; //array_simp[0] = '{ 1:4'd3, default:13}; //if (array_simp[0] !== 16'hDD3D) $stop; array_simp = '{ '{ 4'd3, 4'd2, 4'd1, 4'd0 }, '{ 4'd1, 4'd2, 4'd3, 4'd4 }}; if (array_simp !== 32'h3210_1234) $stop; // IEEE says '{} allowed only on assignments, not !=, ==. // Doesn't seem to work for unpacked arrays in other simulators array_simp = '{2{ '{4'd3, 4'd2, 4'd1, 4'd0 } }}; if (array_simp !== 32'h3210_3210) $stop; array_simp = '{2{ '{4{ 4'd3 }} }}; if (array_simp !== 32'h3333_3333) $stop; // Not legal in other simulators - replication doesn't match // However IEEE suggests this is legal. //array_simp = '{2{ '{2{ 4'd3, 4'd2 }} }}; // Note it's not '{3,2} $write("*-* All Finished *-*\n"); $finish; end //==================== // parameters for array sizes localparam WA = 4; // address dimension size localparam WB = 4; // bit dimension size localparam NO = 11; // number of access events // 2D packed arrays logic [WA-1:0] [WB-1:0] array_dsc; // descending range array /* verilator lint_off ASCRANGE */ logic [0:WA-1] [0:WB-1] array_asc; // ascending range array /* verilator lint_on ASCRANGE */ integer cnt = 0; // event counter always @ (posedge clk) begin cnt <= cnt + 1; end // finish report always @ (posedge clk) if ((cnt[30:2]==(NO-1)) && (cnt[1:0]==2'd3)) begin $write("*-* All Finished *-*\n"); $finish; end // descending range always @ (posedge clk) if (cnt[1:0]==2'd0) begin // initialize to defaults (all bits 1'b0) if (cnt[30:2]== 0) array_dsc <= '0; else if (cnt[30:2]== 1) array_dsc <= '0; else if (cnt[30:2]== 2) array_dsc <= '0; else if (cnt[30:2]== 3) array_dsc <= '0; else if (cnt[30:2]== 4) array_dsc <= '0; else if (cnt[30:2]== 5) array_dsc <= '0; else if (cnt[30:2]== 6) array_dsc <= '0; else if (cnt[30:2]== 7) array_dsc <= '0; else if (cnt[30:2]== 8) array_dsc <= '0; else if (cnt[30:2]== 9) array_dsc <= '0; else if (cnt[30:2]==10) array_dsc <= '0; end else if (cnt[1:0]==2'd1) begin // write data into whole or part of the array using literals if (cnt[30:2]== 0) begin end else if (cnt[30:2]== 1) array_dsc <= '{ 3 ,2 ,1, 0 }; else if (cnt[30:2]== 2) array_dsc <= '{default:13}; else if (cnt[30:2]== 3) array_dsc <= '{0:4, 1:5, 2:6, 3:7}; else if (cnt[30:2]== 4) array_dsc <= '{2:15, default:13}; else if (cnt[30:2]== 5) array_dsc <= '{WA { {WB/2 {2'b10}} }}; else if (cnt[30:2]== 6) array_dsc <= '{cnt[3:0]+0, cnt[3:0]+1, cnt[3:0]+2, cnt[3:0]+3}; end else if (cnt[1:0]==2'd2) begin // chack array agains expected value if (cnt[30:2]== 0) begin if (array_dsc !== 16'b0000000000000000) begin $display("%b", array_dsc); $stop(); end end else if (cnt[30:2]== 1) begin if (array_dsc !== 16'b0011001000010000) begin $display("%b", array_dsc); $stop(); end end else if (cnt[30:2]== 2) begin if (array_dsc !== 16'b1101110111011101) begin $display("%b", array_dsc); $stop(); end end else if (cnt[30:2]== 3) begin if (array_dsc !== 16'b0111011001010100) begin $display("%b", array_dsc); $stop(); end end else if (cnt[30:2]== 4) begin if (array_dsc !== 16'b1101111111011101) begin $display("%b", array_dsc); $stop(); end end else if (cnt[30:2]== 5) begin if (array_dsc !== 16'b1010101010101010) begin $display("%b", array_dsc); $stop(); end end else if (cnt[30:2]== 6) begin if (array_dsc !== 16'b1001101010111100) begin $display("%b", array_dsc); $stop(); end end end // ascending range always @ (posedge clk) if (cnt[1:0]==2'd0) begin // initialize to defaults (all bits 1'b0) if (cnt[30:2]== 0) array_asc <= '0; else if (cnt[30:2]== 1) array_asc <= '0; else if (cnt[30:2]== 2) array_asc <= '0; else if (cnt[30:2]== 3) array_asc <= '0; else if (cnt[30:2]== 4) array_asc <= '0; else if (cnt[30:2]== 5) array_asc <= '0; else if (cnt[30:2]== 6) array_asc <= '0; else if (cnt[30:2]== 7) array_asc <= '0; else if (cnt[30:2]== 8) array_asc <= '0; else if (cnt[30:2]== 9) array_asc <= '0; else if (cnt[30:2]==10) array_asc <= '0; end else if (cnt[1:0]==2'd1) begin // write data into whole or part of the array using literals if (cnt[30:2]== 0) begin end else if (cnt[30:2]== 1) array_asc <= '{ 3 ,2 ,1, 0 }; else if (cnt[30:2]== 2) array_asc <= '{default:13}; else if (cnt[30:2]== 3) array_asc <= '{3:4, 2:5, 1:6, 0:7}; else if (cnt[30:2]== 4) array_asc <= '{1:15, default:13}; else if (cnt[30:2]== 5) array_asc <= '{WA { {WB/2 {2'b10}} }}; else if (cnt[30:2]==10) array_asc <= '{cnt[3:0]+0, cnt[3:0]+1, cnt[3:0]+2, cnt[3:0]+3}; end else if (cnt[1:0]==2'd2) begin // chack array agains expected value if (cnt[30:2]== 0) begin if (array_asc !== 16'b0000000000000000) begin $display("%b", array_asc); $stop(); end end else if (cnt[30:2]== 1) begin if (array_asc !== 16'b0011001000010000) begin $display("%b", array_asc); $stop(); end end else if (cnt[30:2]== 2) begin if (array_asc !== 16'b1101110111011101) begin $display("%b", array_asc); $stop(); end end else if (cnt[30:2]== 3) begin if (array_asc !== 16'b0111011001010100) begin $display("%b", array_asc); $stop(); end end else if (cnt[30:2]== 4) begin if (array_asc !== 16'b1101111111011101) begin $display("%b", array_asc); $stop(); end end else if (cnt[30:2]== 5) begin if (array_asc !== 16'b1010101010101010) begin $display("%b", array_asc); $stop(); end end else if (cnt[30:2]==10) begin if (array_asc !== 16'b1001101010111100) begin $display("%b", array_asc); $stop(); end end end endmodule verilator-5.042/test_regress/t/t_trace_complex_saif_threads_1.py0000755000542200017500000000126215101701376025550 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_complex.v" test.golden_filename = "t/t_trace_complex_saif.out" test.compile(verilator_flags2=['--cc --trace-saif --trace-threads 1']) test.execute() test.saif_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dfg_stats_patterns_pre_inline.out0000644000542200017500000001512315101701376026246 0ustar mahmoudyfreeshellDFG 'pre inline' patterns with depth 1 9 (CONCAT _A:1 _B:a):b 8 (REDXOR _A:a):1 3 (AND _A:a _B:a)*:a 3 (NOT vA:a)*:a 2 (REPLICATE _A:a cA:a)*:b 1 (CONCAT '0:a _A:b):A 1 (CONCAT _A:1 _B:1):a 1 (NOT _A:a):a 1 (REDXOR _A:a)*:1 1 (REPLICATE _A:1 cA:a)*:b 1 (REPLICATE _A:a cA:b)*:b 1 (REPLICATE _A:a cA:b)*:c 1 (SEL@0 _A:a)*:1 1 (SEL@0 _A:a)*:b 1 (SEL@A _A:a):1 DFG 'pre inline' patterns with depth 2 6 (CONCAT (REDXOR _A:a):1 (CONCAT _B:1 _C:b):c):d 3 (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a 3 (REDXOR (AND _A:a _B:a)*:a):1 1 (CONCAT '0:a (REPLICATE _A:a cA:a)*:b):A 1 (CONCAT (REDXOR _A:a)*:1 (CONCAT _B:1 _C:b):c):d 1 (CONCAT (REDXOR _A:a):1 (CONCAT _B:1 _C:1):b):c 1 (CONCAT (REDXOR _A:a):1 (REDXOR _B:b)*:1):c 1 (CONCAT (SEL@0 _A:a)*:1 (CONCAT _B:1 _C:b):c):d 1 (NOT (REPLICATE _A:a cA:b)*:b):b 1 (REDXOR (REPLICATE _A:1 cA:a)*:b):1 1 (REDXOR (REPLICATE _A:a cA:a)*:b)*:1 1 (REDXOR (REPLICATE _A:a cA:a)*:b):1 1 (REDXOR (REPLICATE _A:a cA:b)*:b):1 1 (REDXOR (REPLICATE _A:a cA:b)*:c):1 1 (REDXOR (SEL@0 _A:a)*:b):1 1 (REPLICATE (NOT _A:a):a cA:a)*:b 1 (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c 1 (REPLICATE (REPLICATE _A:a cA:b)*:b cA:b)*:c 1 (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b 1 (REPLICATE (SEL@A _A:a):1 cA:b)*:c 1 (SEL@0 (AND _A:a _B:a)*:a)*:1 1 (SEL@0 (REPLICATE _A:a cA:a)*:b)*:c 1 (SEL@A (AND _A:a _B:a)*:a):1 DFG 'pre inline' patterns with depth 3 3 (REDXOR (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 2 (CONCAT (REDXOR (AND _A:a _B:a)*:a):1 (CONCAT (REDXOR _C:a):1 (CONCAT _D:1 _E:b):c):d):e 1 (CONCAT '0:a (REPLICATE (REPLICATE _A:b cA:a)*:a cA:a)*:c):A 1 (CONCAT (REDXOR (AND _A:a _B:a)*:a):1 (CONCAT (SEL@0 _C:a)*:1 (CONCAT _D:1 _E:b):c):d):e 1 (CONCAT (REDXOR (REPLICATE _A:1 cA:a)*:b):1 (CONCAT (REDXOR _B:c):1 (CONCAT _C:1 _D:d):e):f):g 1 (CONCAT (REDXOR (REPLICATE _A:a cA:a)*:b)*:1 (CONCAT (REDXOR _B:b):1 (CONCAT _C:1 _D:1):c):d):e 1 (CONCAT (REDXOR (REPLICATE _A:a cA:a)*:b):1 (CONCAT (REDXOR _B:c):1 (REDXOR _C:b)*:1):d):e 1 (CONCAT (REDXOR (REPLICATE _A:a cA:b)*:b):1 (CONCAT (REDXOR _B:c)*:1 (CONCAT _C:1 _D:d):e):f):g 1 (CONCAT (REDXOR (REPLICATE _A:a cA:b)*:c):1 (CONCAT (REDXOR _B:b):1 (CONCAT _C:1 _D:d):e):f):g 1 (CONCAT (REDXOR (SEL@0 _A:a)*:b):1 (REDXOR (REPLICATE _B:c cA:c)*:a)*:1):d 1 (CONCAT (SEL@0 (AND _A:a _B:a)*:a)*:1 (CONCAT (REDXOR _C:b):1 (CONCAT _D:1 _E:c):d):e):b 1 (NOT (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b):b 1 (REDXOR (REPLICATE (NOT _A:a):a cA:a)*:b):1 1 (REDXOR (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c):1 1 (REDXOR (REPLICATE (REPLICATE _A:a cA:b)*:b cA:b)*:c)*:1 1 (REDXOR (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b):1 1 (REDXOR (REPLICATE (SEL@A _A:a):1 cA:b)*:c):1 1 (REDXOR (SEL@0 (REPLICATE _A:a cA:a)*:b)*:c):1 1 (REPLICATE (NOT (REPLICATE _A:a cA:b)*:b):b cA:b)*:c 1 (REPLICATE (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c cB:a)*:a 1 (REPLICATE (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b cA:b)*:d 1 (REPLICATE (REPLICATE (SEL@A _A:a):1 cA:b)*:c cB:b)*:d 1 (REPLICATE (SEL@A (AND _A:a _B:a)*:a):1 cA:b)*:c 1 (SEL@0 (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a)*:1 1 (SEL@0 (REPLICATE (NOT _A:a):a cA:a)*:b)*:c 1 (SEL@A (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 DFG 'pre inline' patterns with depth 4 1 (CONCAT '0:a (REPLICATE (REPLICATE (REPLICATE _A:b cA:a)*:c cA:a)*:a cA:a)*:d):A 1 (CONCAT (REDXOR (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 (CONCAT (REDXOR (AND _A:a _B:a)*:a):1 (CONCAT (REDXOR _C:a):1 (CONCAT _D:1 _E:b):c):d):e):f 1 (CONCAT (REDXOR (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 (CONCAT (REDXOR (AND _A:a _B:a)*:a):1 (CONCAT (SEL@0 _C:a)*:1 (CONCAT _D:1 _E:b):c):d):e):f 1 (CONCAT (REDXOR (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 (CONCAT (SEL@0 (AND _A:a _B:a)*:a)*:1 (CONCAT (REDXOR _C:b):1 (CONCAT _D:1 _E:c):d):e):b):f 1 (CONCAT (REDXOR (REPLICATE (NOT _A:a):a cA:a)*:b):1 (CONCAT (REDXOR (SEL@0 _B:b)*:c):1 (REDXOR (REPLICATE _A:a cA:a)*:b)*:1):d):e 1 (CONCAT (REDXOR (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c):1 (CONCAT (REDXOR (REPLICATE _B:c cB:a)*:a):1 (CONCAT (REDXOR _C:d)*:1 (CONCAT _D:1 _E:e):f):g):h):i 1 (CONCAT (REDXOR (REPLICATE (REPLICATE _A:a cA:b)*:b cA:b)*:c)*:1 (CONCAT (REDXOR (REPLICATE _B:b cA:b)*:c):1 (CONCAT (REDXOR _C:d):1 (REDXOR _D:c)*:1):e):f):g 1 (CONCAT (REDXOR (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b):1 (CONCAT (REDXOR (REPLICATE _B:b cA:b)*:d)*:1 (CONCAT (REDXOR _C:d):1 (CONCAT _D:1 _E:1):e):f):g):h 1 (CONCAT (REDXOR (REPLICATE (SEL@A _A:a):1 cA:b)*:c):1 (CONCAT (REDXOR (REPLICATE _B:c cB:b)*:d):1 (CONCAT (REDXOR _C:b):1 (CONCAT _D:1 _E:e):a):f):g):h 1 (CONCAT (REDXOR (SEL@0 (REPLICATE _A:a cA:a)*:b)*:c):1 (REDXOR (REPLICATE (REPLICATE _B:d cA:a)*:a cA:a)*:b)*:1):e 1 (CONCAT (SEL@0 (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a)*:1 (CONCAT (REDXOR (REPLICATE _A:1 cA:b)*:c):1 (CONCAT (REDXOR _B:d):1 (CONCAT _C:1 _D:a):e):f):g):c 1 (NOT (REPLICATE (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c cB:a)*:a):a 1 (REDXOR (REPLICATE (NOT (REPLICATE _A:a cA:b)*:b):b cA:b)*:c):1 1 (REDXOR (REPLICATE (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c cB:a)*:a):1 1 (REDXOR (REPLICATE (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b cA:b)*:d)*:1 1 (REDXOR (REPLICATE (REPLICATE (SEL@A _A:a):1 cA:b)*:c cB:b)*:d):1 1 (REDXOR (REPLICATE (SEL@A (AND _A:a _B:a)*:a):1 cA:b)*:c):1 1 (REDXOR (SEL@0 (REPLICATE (NOT _A:a):a cA:a)*:b)*:c):1 1 (REPLICATE (NOT (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b):b cA:b)*:d 1 (REPLICATE (REPLICATE (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c cB:a)*:a cB:a)*:d 1 (REPLICATE (REPLICATE (REPLICATE (SEL@A _A:a):1 cA:b)*:c cB:b)*:d cB:b)*:b 1 (REPLICATE (REPLICATE (SEL@A (AND _A:a _B:a)*:a):1 cA:b)*:c cB:b)*:d 1 (REPLICATE (SEL@A (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 cA:b)*:c 1 (SEL@0 (REPLICATE (NOT (REPLICATE _A:a cA:b)*:b):b cA:b)*:c)*:d verilator-5.042/test_regress/t/t_mod_topmodule.py0000755000542200017500000000100115101701376022625 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--top-module top"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_slice_cond.v0000644000542200017500000000171715101701376021710 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs dataout, // Inputs clk, sel, d0, d1 ); input clk; input sel; logic [7:0] data [1:0][3:0]; input [7:0] d0, d1; output wire [8*2*4-1:0] dataout; always_comb begin for ( integer j = 0; j <= 1; j++ ) begin if (sel) data[j] = '{ d0, d1, 8'h00, 8'h00 }; else data[j] = '{ 8'h00, 8'h00, 8'h00, 8'h00 }; end for ( integer j = 0; j <= 1; j++ ) begin data[j] = sel ? '{ d0, d1, 8'h00, 8'h00 } : '{ 8'h00, 8'h00, 8'h00, 8'h00 }; end end assign dataout = {data[0][0], data[0][1], data[0][2], data[0][3], data[1][0], data[1][1], data[1][2], data[1][3]}; endmodule verilator-5.042/test_regress/t/t_var_xref_gen.v0000644000542200017500000000166215101701376022252 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This is to test the handling of VarXRef when the referenced VAR is // under a generate construction. // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Jie Xu and Roland Kruse. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk, addr, res ); input clk; input [31:0] addr; output [15:0] res; memory i_mem(.addr(addr),.dout(res)); assign i_mem.cxrow_inst[0].cmem_xrow[0] = 16'h0; endmodule module memory(addr, dout); parameter CM_XROWSIZE = 256; parameter CM_NUMXROWS = 2; input [31:0] addr; output [15:0] dout; generate genvar g_cx; for (g_cx = 0; g_cx < CM_NUMXROWS; g_cx++) begin: cxrow_inst reg [15:0] cmem_xrow[0:CM_XROWSIZE - 1]; end endgenerate assign dout = cxrow_inst[0].cmem_xrow[addr]; endmodule verilator-5.042/test_regress/t/t_preproc_kwd_bad.out0000644000542200017500000000040215101701376023263 0ustar mahmoudyfreeshell%Error: t/t_preproc_kwd_bad.v:8:1: `end_keywords when not inside `begin_keywords block 8 | `end_keywords | ^~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_package_import_param.v0000644000542200017500000000130015101701376023737 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package s_pkg; typedef enum bit [4:0] {MEM_REQ = 5'b00000} P_Type_e; endpackage package pkg; import s_pkg::*; virtual class uvm_sequence #( type REQ = int ); REQ m_req; endclass class cls_txn; P_Type_e m_type; endclass class cls_seq extends uvm_sequence #(cls_txn); endclass class p_mem_seq extends cls_seq; virtual task body(); if (0 == (m_req.randomize() with {m_req.m_type == MEM_REQ;})) begin end endtask endclass endpackage verilator-5.042/test_regress/t/t_inst_paren_bad.py0000755000542200017500000000076615101701376022747 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class2.v0000644000542200017500000000210315101701376020763 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package Pkg; typedef enum { ENUMP_VAL = 33 } enump_t; endpackage module t; class Cls; int imembera; int imemberb; typedef enum { ENUM_VAL = 22 } enum_t; endclass : Cls Cls c; Cls d; Cls::enum_t e; initial begin // Alternate between two versions to make sure we don't // constant propagate between them. c = new; d = new; e = Cls::ENUM_VAL; c.imembera = 10; d.imembera = 11; c.imemberb = 20; d.imemberb = 21; if (c.imembera != 10) $stop; if (d.imembera != 11) $stop; if (c.imemberb != 20) $stop; if (d.imemberb != 21) $stop; if (Pkg::ENUMP_VAL != 33) $stop; if (Cls::ENUM_VAL != 22) $stop; if (c.ENUM_VAL != 22) $stop; if (e != Cls::ENUM_VAL) $stop; if (e != 22) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_case_huge_sub2.v0000644000542200017500000002013515101701376022457 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t_case_huge_sub2 (/*AUTOARG*/ // Outputs outa, // Inputs index ); input [9:0] index; output logic [9:0] outa; // ============================= // Created from Python3: // for i in range(1024): // print(" 10'h%03x: begin outa = 10'h%03x; outb = 2'b%d%d; outc = 1'b%d; end" // % (i, random.randint(0,1024), random.randint(0,1), // random.randint(0,1), random.randint(0,1))) always @(/*AS*/index) begin case (index[7:0]) `ifdef VERILATOR // Harder test 8'h00: begin outa = $c("0"); end // Makes whole table non-optimizable `else 8'h00: outa = 10'h0; `endif 8'h01: outa = 10'h318; 8'h02: outa = 10'h29f; 8'h03: outa = 10'h392; 8'h04: outa = 10'h1ef; 8'h05: outa = 10'h06c; 8'h06: outa = 10'h29f; 8'h07: outa = 10'h29a; 8'h08: outa = 10'h3ce; 8'h09: outa = 10'h37c; 8'h0a: outa = 10'h058; 8'h0b: outa = 10'h3b2; 8'h0c: outa = 10'h36f; 8'h0d: outa = 10'h2c5; 8'h0e: outa = 10'h23a; 8'h0f: outa = 10'h222; 8'h10: outa = 10'h328; 8'h11: outa = 10'h3c3; 8'h12: outa = 10'h12c; 8'h13: outa = 10'h1d0; 8'h14: outa = 10'h3ff; 8'h15: outa = 10'h115; 8'h16: outa = 10'h3ba; 8'h17: outa = 10'h3ba; 8'h18: outa = 10'h10d; 8'h19: outa = 10'h13b; 8'h1a: outa = 10'h0a0; 8'h1b: outa = 10'h264; 8'h1c: outa = 10'h3a2; 8'h1d: outa = 10'h07c; 8'h1e: outa = 10'h291; 8'h1f: outa = 10'h1d1; 8'h20: outa = 10'h354; 8'h21: outa = 10'h0c0; 8'h22: outa = 10'h191; 8'h23: outa = 10'h379; 8'h24: outa = 10'h073; 8'h25: outa = 10'h2fd; 8'h26: outa = 10'h2e0; 8'h27: outa = 10'h337; 8'h28: outa = 10'h2c7; 8'h29: outa = 10'h19e; 8'h2a: outa = 10'h107; 8'h2b: outa = 10'h06a; 8'h2c: outa = 10'h1c7; 8'h2d: outa = 10'h107; 8'h2e: outa = 10'h0cf; 8'h2f: outa = 10'h009; 8'h30: outa = 10'h09d; 8'h31: outa = 10'h28e; 8'h32: outa = 10'h010; 8'h33: outa = 10'h1e0; 8'h34: outa = 10'h079; 8'h35: outa = 10'h13e; 8'h36: outa = 10'h282; 8'h37: outa = 10'h21c; 8'h38: outa = 10'h148; 8'h39: outa = 10'h3c0; 8'h3a: outa = 10'h176; 8'h3b: outa = 10'h3fc; 8'h3c: outa = 10'h295; 8'h3d: outa = 10'h113; 8'h3e: outa = 10'h354; 8'h3f: outa = 10'h0db; 8'h40: outa = 10'h238; 8'h41: outa = 10'h12b; 8'h42: outa = 10'h1dc; 8'h43: outa = 10'h137; 8'h44: outa = 10'h1e2; 8'h45: outa = 10'h3d5; 8'h46: outa = 10'h30c; 8'h47: outa = 10'h298; 8'h48: outa = 10'h080; 8'h49: outa = 10'h35a; 8'h4a: outa = 10'h01b; 8'h4b: outa = 10'h0a3; 8'h4c: outa = 10'h0b3; 8'h4d: outa = 10'h17a; 8'h4e: outa = 10'h3ae; 8'h4f: outa = 10'h078; 8'h50: outa = 10'h322; 8'h51: outa = 10'h213; 8'h52: outa = 10'h11a; 8'h53: outa = 10'h1a7; 8'h54: outa = 10'h35a; 8'h55: outa = 10'h233; 8'h56: outa = 10'h01d; 8'h57: outa = 10'h2d5; 8'h58: outa = 10'h1a0; 8'h59: outa = 10'h3d0; 8'h5a: outa = 10'h181; 8'h5b: outa = 10'h219; 8'h5c: outa = 10'h26a; 8'h5d: outa = 10'h050; 8'h5e: outa = 10'h189; 8'h5f: outa = 10'h1eb; 8'h60: outa = 10'h224; 8'h61: outa = 10'h2fe; 8'h62: outa = 10'h0ae; 8'h63: outa = 10'h1cd; 8'h64: outa = 10'h273; 8'h65: outa = 10'h268; 8'h66: outa = 10'h111; 8'h67: outa = 10'h1f9; 8'h68: outa = 10'h232; 8'h69: outa = 10'h255; 8'h6a: outa = 10'h34c; 8'h6b: outa = 10'h049; 8'h6c: outa = 10'h197; 8'h6d: outa = 10'h0fe; 8'h6e: outa = 10'h253; 8'h6f: outa = 10'h2de; 8'h70: outa = 10'h13b; 8'h71: outa = 10'h040; 8'h72: outa = 10'h0b4; 8'h73: outa = 10'h233; 8'h74: outa = 10'h198; 8'h75: outa = 10'h018; 8'h76: outa = 10'h2f7; 8'h77: outa = 10'h134; 8'h78: outa = 10'h1ca; 8'h79: outa = 10'h286; 8'h7a: outa = 10'h0e6; 8'h7b: outa = 10'h064; 8'h7c: outa = 10'h257; 8'h7d: outa = 10'h31a; 8'h7e: outa = 10'h247; 8'h7f: outa = 10'h299; 8'h80: outa = 10'h02c; 8'h81: outa = 10'h2bb; 8'h82: outa = 10'h180; 8'h83: outa = 10'h245; 8'h84: outa = 10'h0da; 8'h85: outa = 10'h367; 8'h86: outa = 10'h304; 8'h87: outa = 10'h38b; 8'h88: outa = 10'h09f; 8'h89: outa = 10'h1f0; 8'h8a: outa = 10'h281; 8'h8b: outa = 10'h019; 8'h8c: outa = 10'h1f2; 8'h8d: outa = 10'h0b1; 8'h8e: outa = 10'h058; 8'h8f: outa = 10'h39b; 8'h90: outa = 10'h2ec; 8'h91: outa = 10'h250; 8'h92: outa = 10'h3f4; 8'h93: outa = 10'h057; 8'h94: outa = 10'h18f; 8'h95: outa = 10'h105; 8'h96: outa = 10'h1ae; 8'h97: outa = 10'h04e; 8'h98: outa = 10'h240; 8'h99: outa = 10'h3e4; 8'h9a: outa = 10'h3c6; 8'h9b: outa = 10'h109; 8'h9c: outa = 10'h073; 8'h9d: outa = 10'h19f; 8'h9e: outa = 10'h3b8; 8'h9f: outa = 10'h00e; 8'ha0: outa = 10'h1b3; 8'ha1: outa = 10'h2bd; 8'ha2: outa = 10'h324; 8'ha3: outa = 10'h343; 8'ha4: outa = 10'h1c9; 8'ha5: outa = 10'h185; 8'ha6: outa = 10'h37a; 8'ha7: outa = 10'h0e0; 8'ha8: outa = 10'h0a3; 8'ha9: outa = 10'h019; 8'haa: outa = 10'h099; 8'hab: outa = 10'h376; 8'hac: outa = 10'h077; 8'had: outa = 10'h2b1; 8'hae: outa = 10'h27f; 8'haf: outa = 10'h265; 8'hb0: outa = 10'h156; 8'hb1: outa = 10'h1ce; 8'hb2: outa = 10'h008; 8'hb3: outa = 10'h12e; 8'hb4: outa = 10'h199; 8'hb5: outa = 10'h330; 8'hb6: outa = 10'h1ab; 8'hb7: outa = 10'h3bd; 8'hb8: outa = 10'h0ca; 8'hb9: outa = 10'h367; 8'hba: outa = 10'h334; 8'hbb: outa = 10'h040; 8'hbc: outa = 10'h1a7; 8'hbd: outa = 10'h036; 8'hbe: outa = 10'h223; 8'hbf: outa = 10'h075; 8'hc0: outa = 10'h3c4; 8'hc1: outa = 10'h2cc; 8'hc2: outa = 10'h123; 8'hc3: outa = 10'h3fd; 8'hc4: outa = 10'h11e; 8'hc5: outa = 10'h27c; 8'hc6: outa = 10'h1e2; 8'hc7: outa = 10'h377; 8'hc8: outa = 10'h33a; 8'hc9: outa = 10'h32d; 8'hca: outa = 10'h014; 8'hcb: outa = 10'h332; 8'hcc: outa = 10'h359; 8'hcd: outa = 10'h0a4; 8'hce: outa = 10'h348; 8'hcf: outa = 10'h04b; 8'hd0: outa = 10'h147; 8'hd1: outa = 10'h026; 8'hd2: outa = 10'h103; 8'hd3: outa = 10'h106; 8'hd4: outa = 10'h35a; 8'hd5: outa = 10'h254; 8'hd6: outa = 10'h0cd; 8'hd7: outa = 10'h17c; 8'hd8: outa = 10'h37e; 8'hd9: outa = 10'h0a9; 8'hda: outa = 10'h0fe; 8'hdb: outa = 10'h3c0; 8'hdc: outa = 10'h1d9; 8'hdd: outa = 10'h10e; 8'hde: outa = 10'h394; 8'hdf: outa = 10'h316; 8'he0: outa = 10'h05b; 8'he1: outa = 10'h126; 8'he2: outa = 10'h369; 8'he3: outa = 10'h291; 8'he4: outa = 10'h2ca; 8'he5: outa = 10'h25b; 8'he6: outa = 10'h106; 8'he7: outa = 10'h172; 8'he8: outa = 10'h2f7; 8'he9: outa = 10'h2d3; 8'hea: outa = 10'h182; 8'heb: outa = 10'h327; 8'hec: outa = 10'h1d0; 8'hed: outa = 10'h204; 8'hee: outa = 10'h11f; 8'hef: outa = 10'h365; 8'hf0: outa = 10'h2c2; 8'hf1: outa = 10'h2b5; 8'hf2: outa = 10'h1f8; 8'hf3: outa = 10'h2a7; 8'hf4: outa = 10'h1be; 8'hf5: outa = 10'h25e; 8'hf6: outa = 10'h032; 8'hf7: outa = 10'h2ef; 8'hf8: outa = 10'h02f; 8'hf9: outa = 10'h201; 8'hfa: outa = 10'h054; 8'hfb: outa = 10'h013; 8'hfc: outa = 10'h249; 8'hfd: outa = 10'h09a; 8'hfe: outa = 10'h012; 8'hff: outa = 10'h114; endcase end endmodule verilator-5.042/test_regress/t/t_dedupe_clk_gate_off.py0000755000542200017500000000120715101701376023717 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.top_filename = "t/t_dedupe_clk_gate.v" test.compile(verilator_flags2=["--stats", "-fno-dedup"]) if test.vlt_all: test.file_grep_not(test.stats, r'Optimizations, Gate sigs deduped\s+(\d+)') test.passes() verilator-5.042/test_regress/t/t_trace_binary_flag_off.py0000755000542200017500000000125715101701376024260 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_trace_binary.v" test.compile( verilator_flags=[ # Custom as don't want -cc "-Mdir " + test.obj_dir, "--debug-check" ], verilator_flags2=['--binary']) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_randomize_prepost.v0000644000542200017500000000313715101701376023350 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); typedef enum int { RANDOMIZED = 20 } enumed_t; class Base; int m_pre; rand enumed_t r; int m_post; function void pre_randomize; `checkd(m_pre, 0); `checkd(r, enumed_t'(0)); `checkd(m_post, 0); m_pre = 10; endfunction function void post_randomize; `checkd(m_pre, 10); `checkd(r, RANDOMIZED); `checkd(m_post, 0); m_post = 30; endfunction endclass class Cls extends Base; int m_cpre; int m_cpost; function void pre_randomize; m_cpre = 111; super.pre_randomize(); endfunction function void post_randomize; m_cpost = 222; super.post_randomize(); endfunction endclass module t; initial begin Cls c; int rand_result; c = new; rand_result = c.randomize(); `checkd(rand_result, 1); `checkd(c.m_pre, 10); `checkd(c.m_cpre, 111); `checkd(c.r, RANDOMIZED); `checkd(c.m_post, 30); `checkd(c.m_cpost, 222); c = new; rand_result = c.randomize() with { r == RANDOMIZED; }; `checkd(rand_result, 1); `checkd(c.m_pre, 10); `checkd(c.m_cpre, 111); `checkd(c.r, RANDOMIZED); `checkd(c.m_post, 30); `checkd(c.m_cpost, 222); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_func_plog.py0000755000542200017500000000073415101701376021746 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_uses_this_bad.v0000644000542200017500000000054415101701376023604 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 Rafal Kapuscik // SPDX-License-Identifier: CC0-1.0 // module t; bit [3:0] addr; initial begin this.addr = 2; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_inst_darray.v0000644000542200017500000000357015101701376022124 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by John Stevenson. // SPDX-License-Identifier: CC0-1.0 typedef logic [63:0] uid_t; typedef logic [31:0] value_t; interface the_intf #(parameter M = 5); logic valid; uid_t uid; value_t [M-1:0] values; modport i( output valid, output uid, output values ); modport t( input valid, input uid, input values ); endinterface module Contemplator #( parameter IMPL = 0, parameter M = 5, parameter N = 1 ) ( input logic clk, the_intf.i out [N-1:0] ); the_intf #(.M(M)) inp[N-1:0] (); DeepThought #( .N ( N )) ultimateAnswerer( .src ( inp ), .dst ( out )); endmodule module DeepThought #( parameter N = 1 ) ( the_intf.t src[N-1:0], the_intf.i dst[N-1:0] ); endmodule module t (/*AUTOARG*/ // Inputs clk ); input clk; localparam M = 5; localparam N = 1; the_intf #(.M(M)) out0 [N-1:0] (); the_intf #(.M(M)) out1 [N-1:0] (); Contemplator #( .IMPL ( 0 ), .M ( M ), .N ( N )) contemplatorOfTheZerothKind( .clk ( clk ), .out ( out0 )); Contemplator #( .IMPL ( 1 ), .M ( M ), .N ( N )) contemplatorOfTheFirstKind( .clk ( clk ), .out ( out1 )); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_cover_expr_trace.out0000644000542200017500000004172715101701376023507 0ustar mahmoudyfreeshell// // verilator_coverage annotation // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class cls; rand int x; endclass module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; logic [63:32] cyc2; always_comb cyc2 = cyc; integer some_int; integer other_int; logic some_bool; wire t1 = cyc[0]; wire t2 = cyc[1]; wire t3 = cyc[2]; wire t4 = cyc[3]; localparam bit ONE = 1'b1; localparam bit ZERO = 1'b0; function automatic bit invert(bit x); %000005 return ~x; -000004 point: comment=(x==0) => 1 hier=top.t -000005 point: comment=(x==1) => 0 hier=top.t endfunction function automatic bit and_oper(bit a, bit b); %000005 return a & b; -000004 point: comment=(a==0) => 0 hier=top.t -000002 point: comment=(a==1 && b==1) => 1 hier=top.t -000005 point: comment=(b==0) => 0 hier=top.t endfunction localparam int NUM_INTFS = 4; intf the_intfs [NUM_INTFS-1:0] (); genvar intf_i; for (intf_i = 0; intf_i < NUM_INTFS; intf_i++) begin always_comb the_intfs[intf_i].t = cyc[intf_i]; end always @ (posedge clk) begin cyc <= cyc + 1; %000004 if ((~cyc[0] && cyc[1]) || (~cyc[2] && cyc[3])) $write(""); -000002 point: comment=(cyc[0]==0 && cyc[1]==1) => 1 hier=top.t -000002 point: comment=(cyc[0]==1 && cyc[2]==1) => 0 hier=top.t -000004 point: comment=(cyc[0]==1 && cyc[3]==0) => 0 hier=top.t -000002 point: comment=(cyc[1]==0 && cyc[2]==1) => 0 hier=top.t -000003 point: comment=(cyc[1]==0 && cyc[3]==0) => 0 hier=top.t -000002 point: comment=(cyc[2]==0 && cyc[3]==1) => 1 hier=top.t %000004 if ((~cyc2[32] && cyc2[33]) || (~cyc2[34] && cyc2[35])) $write(""); -000002 point: comment=(cyc2[32]==0 && cyc2[33]==1) => 1 hier=top.t -000002 point: comment=(cyc2[32]==1 && cyc2[34]==1) => 0 hier=top.t -000004 point: comment=(cyc2[32]==1 && cyc2[35]==0) => 0 hier=top.t -000002 point: comment=(cyc2[33]==0 && cyc2[34]==1) => 0 hier=top.t -000003 point: comment=(cyc2[33]==0 && cyc2[35]==0) => 0 hier=top.t -000002 point: comment=(cyc2[34]==0 && cyc2[35]==1) => 1 hier=top.t %000004 if ((~the_intfs[0].t && the_intfs[1].t) || (~the_intfs[2].t && the_intfs[3].t)) $write(""); -000002 point: comment=(the_intfs[0].t==0 && the_intfs[1].t==1) => 1 hier=top.t -000002 point: comment=(the_intfs[0].t==1 && the_intfs[2].t==1) => 0 hier=top.t -000004 point: comment=(the_intfs[0].t==1 && the_intfs[3].t==0) => 0 hier=top.t -000002 point: comment=(the_intfs[1].t==0 && the_intfs[2].t==1) => 0 hier=top.t -000003 point: comment=(the_intfs[1].t==0 && the_intfs[3].t==0) => 0 hier=top.t -000002 point: comment=(the_intfs[2].t==0 && the_intfs[3].t==1) => 1 hier=top.t %000004 if ((~t1 && t2) || (~t3 && t4)) $write(""); -000002 point: comment=(t1==0 && t2==1) => 1 hier=top.t -000002 point: comment=(t1==1 && t3==1) => 0 hier=top.t -000004 point: comment=(t1==1 && t4==0) => 0 hier=top.t -000002 point: comment=(t2==0 && t3==1) => 0 hier=top.t -000003 point: comment=(t2==0 && t4==0) => 0 hier=top.t -000002 point: comment=(t3==0 && t4==1) => 1 hier=top.t %000005 if (t3 && (t1 == t2)) $write(""); -000005 point: comment=((t1 == t2)==0) => 0 hier=top.t -000005 point: comment=(t3==0) => 0 hier=top.t -000002 point: comment=(t3==1 && (t1 == t2)==1) => 1 hier=top.t %000005 if (123 == (124 - 32'(t1 || t2))) $write(""); -000002 point: comment=(t1==0 && t2==0) => 0 hier=top.t -000005 point: comment=(t1==1) => 1 hier=top.t -000004 point: comment=(t2==1) => 1 hier=top.t %000004 some_int <= (t2 || t3) ? 345 : 567; -000003 point: comment=(t2==0 && t3==0) => 0 hier=top.t -000004 point: comment=(t2==1) => 1 hier=top.t -000004 point: comment=(t3==1) => 1 hier=top.t %000005 some_bool <= t1 && t2; -000004 point: comment=(t1==0) => 0 hier=top.t -000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t %000005 if (t1 & t2) $write(""); -000004 point: comment=(t1==0) => 0 hier=top.t -000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t %000004 if ((!t1 && t2) | (~t3 && t4)) $write(""); -000002 point: comment=(t1==0 && t2==1) => 1 hier=top.t -000002 point: comment=(t1==1 && t3==1) => 0 hier=top.t -000004 point: comment=(t1==1 && t4==0) => 0 hier=top.t -000002 point: comment=(t2==0 && t3==1) => 0 hier=top.t -000003 point: comment=(t2==0 && t4==0) => 0 hier=top.t -000002 point: comment=(t3==0 && t4==1) => 1 hier=top.t %000003 if (t1 ^ t2) $write(""); -000002 point: comment=(t1==0 && t2==0) => 0 hier=top.t -000002 point: comment=(t1==0 && t2==1) => 1 hier=top.t -000003 point: comment=(t1==1 && t2==0) => 1 hier=top.t -000002 point: comment=(t1==1 && t2==1) => 0 hier=top.t %000005 if (~(t1 & t2)) $write(""); -000004 point: comment=(t1==0) => 1 hier=top.t -000002 point: comment=(t1==1 && t2==1) => 0 hier=top.t -000005 point: comment=(t2==0) => 1 hier=top.t %000004 if (t1 -> t2) $write(""); -000004 point: comment=(t1==0) => 1 hier=top.t -000003 point: comment=(t1==1 && t2==0) => 0 hier=top.t -000004 point: comment=(t2==1) => 1 hier=top.t %000003 if (t1 <-> t2) $write(""); -000002 point: comment=(t1==0 && t2==0) => 1 hier=top.t -000002 point: comment=(t1==0 && t2==1) => 0 hier=top.t -000003 point: comment=(t1==1 && t2==0) => 0 hier=top.t -000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t %000005 if (&cyc[2:0]) $write(""); -000004 point: comment=(cyc[2:0][0]==0) => 0 hier=top.t -000001 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 1 hier=top.t -000005 point: comment=(cyc[2:0][1]==0) => 0 hier=top.t -000005 point: comment=(cyc[2:0][2]==0) => 0 hier=top.t %000007 if (&cyc[3:2]) $write(""); -000005 point: comment=(cyc[3:2][0]==0) => 0 hier=top.t -000000 point: comment=(cyc[3:2][0]==1 && cyc[3:2][1]==1) => 1 hier=top.t -000007 point: comment=(cyc[3:2][1]==0) => 0 hier=top.t %000005 if (|cyc[2:0]) $write(""); -000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 0 hier=top.t -000005 point: comment=(cyc[2:0][0]==1) => 1 hier=top.t -000004 point: comment=(cyc[2:0][1]==1) => 1 hier=top.t -000004 point: comment=(cyc[2:0][2]==1) => 1 hier=top.t %000002 if (^cyc[2:0]) $write(""); -000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 0 hier=top.t -000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==1) => 1 hier=top.t -000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==1 && cyc[2:0][2]==0) => 1 hier=top.t -000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 0 hier=top.t -000002 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 1 hier=top.t -000001 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==0 && cyc[2:0][2]==1) => 0 hier=top.t -000001 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==0) => 0 hier=top.t -000001 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 1 hier=top.t %000005 if (|cyc[2:0] || cyc[3]) $write(""); -000000 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0 && cyc[3]==0) => 0 hier=top.t -000005 point: comment=(cyc[2:0][0]==1) => 1 hier=top.t -000004 point: comment=(cyc[2:0][1]==1) => 1 hier=top.t -000004 point: comment=(cyc[2:0][2]==1) => 1 hier=top.t -000002 point: comment=(cyc[3]==1) => 1 hier=top.t %000005 if (t1 & t2 & 1'b1) $write(""); -000000 point: comment=(1'h1==0) => 0 hier=top.t -000004 point: comment=(t1==0) => 0 hier=top.t -000002 point: comment=(t1==1 && t2==1 && 1'h1==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t %000009 if (t1 & t2 & 1'b0) $write(""); -000009 point: comment=(1'h0==0) => 0 hier=top.t -000004 point: comment=(t1==0) => 0 hier=top.t -000000 point: comment=(t1==1 && t2==1 && 1'h0==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t %000005 if (t1 & t2 & ONE) $write(""); -000000 point: comment=(ONE==0) => 0 hier=top.t -000004 point: comment=(t1==0) => 0 hier=top.t -000002 point: comment=(t1==1 && t2==1 && ONE==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t %000009 if (t1 & t2 & ZERO) $write(""); -000009 point: comment=(ZERO==0) => 0 hier=top.t -000004 point: comment=(t1==0) => 0 hier=top.t -000000 point: comment=(t1==1 && t2==1 && ZERO==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t %000005 if (t1 && t2) begin -000004 point: comment=(t1==0) => 0 hier=top.t -000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t $write(""); %000003 end else if (t1 || t2) begin -000002 point: comment=(t1==0 && t2==0) => 0 hier=top.t -000003 point: comment=(t1==1) => 1 hier=top.t -000002 point: comment=(t2==1) => 1 hier=top.t $write(""); end %000005 if (invert(t1) && t2) $write(""); -000005 point: comment=(invert(t1)==0) => 0 hier=top.t -000002 point: comment=(invert(t1)==1 && t2==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t if (and_oper(t1, t2)) $write(""); %000005 if (t2 && t3) begin -000005 point: comment=(t2==0) => 0 hier=top.t -000002 point: comment=(t2==1 && t3==1) => 1 hier=top.t -000005 point: comment=(t3==0) => 0 hier=top.t %000001 if (t1 && t2) $write(""); -000001 point: comment=(t1==0) => 0 hier=top.t -000001 point: comment=(t1==1 && t2==1) => 1 hier=top.t -000000 point: comment=(t2==0) => 0 hier=top.t end if (0 == 1) begin for (int loop_var = 0; loop_var < 1; loop_var++) begin %000000 if (cyc[loop_var] && t2) $write(""); -000000 point: comment=(cyc[loop_var[4:0]+:1]==0) => 0 hier=top.t -000000 point: comment=(cyc[loop_var[4:0]+:1]==1 && t2==1) => 1 hier=top.t -000000 point: comment=(t2==0) => 0 hier=top.t end end // stop at the first layer even if there's more to find %000007 if ((cyc[3+32'(t1 && t2)+:2] == cyc[5+32'(t3 || t4)+:2]) || cyc[31]) $write(""); -000002 point: comment=((cyc[(32'sh3 + (t1 && t2))[4:0]+:2] == cyc[(32'sh5 + (t3 || t4))[4:0]+:2])==0 && cyc[31]==0) => 0 hier=top.t -000007 point: comment=((cyc[(32'sh3 + (t1 && t2))[4:0]+:2] == cyc[(32'sh5 + (t3 || t4))[4:0]+:2])==1) => 1 hier=top.t -000000 point: comment=(cyc[31]==1) => 1 hier=top.t // impossible branches and redundant terms %000005 if ((t1 && t2) && ~(t1 && t3) && (t1 || t4)) $write(""); -000003 point: comment=(t1==0 && t4==0) => 0 hier=top.t -000004 point: comment=(t1==0) => 0 hier=top.t -000000 point: comment=(t1==1 && t2==1 && t3==0 && t4==1) => 1 hier=top.t -000001 point: comment=(t1==1 && t2==1 && t3==0) => 1 hier=top.t -000002 point: comment=(t1==1 && t3==1) => 0 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t %000005 if ((cyc[0] && cyc[1]) && ~(cyc[0] && cyc[2]) && (cyc[0] || cyc[3])) $write(""); -000003 point: comment=(cyc[0]==0 && cyc[3]==0) => 0 hier=top.t -000004 point: comment=(cyc[0]==0) => 0 hier=top.t -000000 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[3]==1) => 1 hier=top.t -000001 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0) => 1 hier=top.t -000002 point: comment=(cyc[0]==1 && cyc[2]==1) => 0 hier=top.t -000005 point: comment=(cyc[1]==0) => 0 hier=top.t // demonstrate current limitations of term matching scheme %000005 if ((cyc[0] && cyc[1]) && ~(cyc[1-1] && cyc[2]) && (cyc[2-2] || cyc[3])) $write(""); -000002 point: comment=(cyc[(32'sh1 - 32'sh1)[4:0]+:1]==1 && cyc[2]==1) => 0 hier=top.t -000003 point: comment=(cyc[(32'sh2 - 32'sh2)[4:0]+:1]==0 && cyc[3]==0) => 0 hier=top.t -000004 point: comment=(cyc[0]==0) => 0 hier=top.t -000000 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[(32'sh1 - 32'sh1)[4:0]+:1]==0 && cyc[(32'sh2 - 32'sh2)[4:0]+:1]==1) => 1 hier=top.t -000000 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[(32'sh1 - 32'sh1)[4:0]+:1]==0 && cyc[3]==1) => 1 hier=top.t -000001 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[(32'sh2 - 32'sh2)[4:0]+:1]==1) => 1 hier=top.t -000000 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[3]==1) => 1 hier=top.t -000005 point: comment=(cyc[1]==0) => 0 hier=top.t //verilator coverage_off if (t1 && t2) $write(""); //verilator coverage_on if ((~t1 && t2) %000004 || -000002 point: comment=(t1==0 && t2==1) => 1 hier=top.t -000002 point: comment=(t1==1 && t3==1) => 0 hier=top.t -000004 point: comment=(t1==1 && t4==0) => 0 hier=top.t -000002 point: comment=(t2==0 && t3==1) => 0 hier=top.t -000003 point: comment=(t2==0 && t4==0) => 0 hier=top.t -000002 point: comment=(t3==0 && t4==1) => 1 hier=top.t (~t3 && t4)) $write(""); // intentionally testing wonkified expression terms if ( cyc[ 0 %000005 ] & -000004 point: comment=(cyc[0]==0) => 0 hier=top.t -000002 point: comment=(cyc[0]==1 && cyc[1]==1) => 1 hier=top.t -000005 point: comment=(cyc[1]==0) => 0 hier=top.t cyc [1]) $write(""); // for now each ternary condition is considered in isolation %000005 other_int <= t1 ? t2 ? 1 : 2 : 3; -000004 point: comment=(t1==0) => 0 hier=top.t -000005 point: comment=(t1==1) => 1 hier=top.t // no expression coverage for multi-bit expressions if ((cyc[1:0] & cyc[3:2]) == 2'b11) $write(""); // truth table is too large if (^cyc[6:0]) $write(""); // this one is too big even for t_cover_expr_max if (^cyc) $write(""); if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end always_comb begin %000005 if (t1 && t2) $write(""); -000005 point: comment=(t1==0) => 0 hier=top.t -000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t end logic ta, tb, tc; initial begin cls obj = new; cls null_obj = null; int q[5]; int qv[$]; q = '{1, 2, 2, 4, 3}; // lambas not handled // NB: there is a bug w/ tracing find_first (maybe lambdas in general?) // tracing_off does not work around the bug qv = q.find_first with (item[0] & item[1]); ta = '1; tb = '0; tc = '0; %000001 while (ta || tb || tc) begin -000001 point: comment=(ta==0 && tb==0 && tc==0) => 0 hier=top.t -000000 point: comment=(ta==1) => 1 hier=top.t -000000 point: comment=(tb==1) => 1 hier=top.t -000000 point: comment=(tc==1) => 1 hier=top.t tc = tb; tb = ta; ta = '0; end if (!bit'(obj.randomize() with {x < 100;})) $write(""); if (null_obj != null && null_obj.x == 5) $write(""); end sub the_sub_1 (.p(t1), .q(t2)); sub the_sub_2 (.p(t3), .q(t4)); // TODO -- non-process expressions sub the_sub_3 (.p(t1 ? t2 : t3), .q(t4)); // TODO // pragma for expr coverage off / on // investigate cover point sorting in annotated source // consider reporting don't care terms // // Branches which are statically impossible to reach are still reported. // E.g. // -000000 point: comment=(t1=1 && t2=1 && 1'h0=1) => 1 hier=top.t // These could potentially be pruned, but they currently follow suit for // what branch coverage does. Perhaps a switch should be added to not // count statically impossible things. endmodule module sub ( input p, input q ); always_comb begin ~000019 if (p && q) $write(""); +000017 point: comment=(p==0) => 0 hier=top.t.the_sub_* -000002 point: comment=(p==1 && q==1) => 1 hier=top.t.the_sub_* +000019 point: comment=(q==0) => 0 hier=top.t.the_sub_* end endmodule interface intf(); logic t; endinterface verilator-5.042/test_regress/t/t_interface_gen3.v0000644000542200017500000000340715101701376022460 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Very simple test for interface pathclearing module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=1; ifc #(2) itopa(); ifc #(4) itopb(); sub ca (.isub(itopa.out_modport), .clk); sub cb (.isub(itopb.out_modport), .clk); always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d result=%b %b\n", $time, cyc, itopa.valueo, itopb.valueo); `endif cyc <= cyc + 1; itopa.valuei <= cyc[1:0]; itopb.valuei <= cyc[3:0]; if (cyc==1) begin if (itopa.WIDTH != 2) $stop; if (itopb.WIDTH != 4) $stop; if ($bits(itopa.valueo) != 2) $stop; if ($bits(itopb.valueo) != 4) $stop; if ($bits(itopa.out_modport.valueo) != 2) $stop; if ($bits(itopb.out_modport.valueo) != 4) $stop; end if (cyc==4) begin if (itopa.valueo != 2'b11) $stop; if (itopb.valueo != 4'b0011) $stop; end if (cyc==5) begin if (itopa.valueo != 2'b00) $stop; if (itopb.valueo != 4'b0100) $stop; end if (cyc==20) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule interface ifc #(parameter WIDTH = 1); // verilator lint_off MULTIDRIVEN logic [WIDTH-1:0] valuei; logic [WIDTH-1:0] valueo; // verilator lint_on MULTIDRIVEN modport out_modport (input valuei, output valueo); endinterface // Note not parameterized module sub ( ifc.out_modport isub, input clk ); always @(posedge clk) isub.valueo <= isub.valuei + 1; endmodule verilator-5.042/test_regress/t/t_display_recurse.py0000755000542200017500000000100015101701376023152 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_preproc_str_undef.out0000644000542200017500000000011215101701376023657 0ustar mahmoudyfreeshell`PREFIX_my_suffix `PREFIX_my_suffix my_prefix_suffix *-* All Finished *-* verilator-5.042/test_regress/t/t_dfg_regularize_driver_of_sc_var.py0000755000542200017500000000073715101701376026362 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["--sc"]) test.passes() verilator-5.042/test_regress/t/t_hier_task.v0000644000542200017500000000172515101701376021556 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Test for issue #2267 // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by James Pallister. // SPDX-License-Identifier: CC0-1.0 module mod_a; mod_inner u_inner(); mod_a_mon u_a_mon(); initial begin bit x; u_inner.x = 1; u_a_mon.y = 0; u_a_mon.accessor; if (u_a_mon.y != 1) begin $write("%%Error: Incorrect value placed in submodule\n"); $stop; end u_inner.x = 0; u_a_mon.accessor; if (u_a_mon.y != 0) begin $write("%%Error: Incorrect value placed in submodule\n"); $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule : mod_a module mod_inner; logic x; endmodule : mod_inner module mod_a_mon; bit y; function automatic void accessor; begin : accessor_block bit read_x = mod_a.u_inner.x; y = read_x; end endfunction endmodule verilator-5.042/test_regress/t/t_hier_block_struct.py0000755000542200017500000000111715101701376023473 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--hierarchical']) test.execute() test.file_grep(test.obj_dir + "/VTest/Test.sv", r'^module\s+(\S+)\s+', "Test") test.passes() verilator-5.042/test_regress/t/t_force_release_var.v0000644000542200017500000000672015101701376023253 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module t (/*AUTOARG*/ // Inputs clk ); input clk; int cyc = 0; always @(posedge clk) cyc <= cyc + 1; reg var_1 = 0; reg [7:0] var_8 = 0; always @(posedge clk) begin var_1 <= cyc[0]; var_8 <= cyc[1 +: 8]; end always @ (posedge clk) begin $display("%d pre : %x %x", cyc, var_8, var_1); case (cyc) 0: begin // Uninitialized end 14: begin `checkh (var_1, 1); `checkh ({1'b0, var_8}, (cyc[0 +: 9] - 1) >> 1); end 15: begin `checkh (var_1, 1); `checkh (var_8, 8'hf5); end 16: begin `checkh (var_1, 0); `checkh (var_8, 8'hf5); end 17, 18: begin `checkh (var_1, 0); `checkh (var_8, 8'h5f); end 19: begin `checkh (var_1, ~cyc[0]); `checkh (var_8, 8'h5f); end 21, 22: begin `checkh (var_1, 1); `checkh (var_8, 8'h5a); end 23, 24: begin `checkh (var_1, 0); `checkh (var_8, 8'ha5); end default: begin `checkh ({var_8, var_1}, cyc[0 +: 9] - 1); end endcase `ifndef REVERSE if (cyc == 13) force var_1 = 1; if (cyc == 15) force var_1 = 0; if (cyc == 18) release var_1; if (cyc == 14) force var_8 = 8'hf5; if (cyc == 16) force var_8 = 8'h5f; if (cyc == 19) release var_8; if (cyc == 20) force {var_1, var_8} = 9'b1_0101_1010; if (cyc == 22) force {var_8, var_1} = 9'b1010_0101_0; if (cyc == 24) release {var_1, var_8}; `else if (cyc == 18) release var_1; if (cyc == 15) force var_1 = 0; if (cyc == 13) force var_1 = 1; if (cyc == 19) release var_8; if (cyc == 16) force var_8 = 8'h5f; if (cyc == 14) force var_8 = 8'hf5; if (cyc == 24) release {var_1, var_8}; if (cyc == 22) force {var_8, var_1} = 9'b1010_0101_0; if (cyc == 20) force {var_1, var_8} = 9'b1_0101_1010; `endif $display("%d post: %x %x", cyc, var_8, var_1); case (cyc) 0: begin // Uninitialized end 13: begin `checkh (var_1, 1); `checkh ({1'b0, var_8}, (cyc[0 +: 9] - 1) >> 1); end 14: begin `checkh (var_1, 1); `checkh (var_8, 8'hf5); end 15: begin `checkh (var_1, 0); `checkh (var_8, 8'hf5); end 16, 17, 18: begin `checkh (var_1, 0); `checkh (var_8, 8'h5f); end 19: begin `checkh (var_1, ~cyc[0]); `checkh (var_8, 8'h5f); end 20, 21: begin `checkh (var_1, 1); `checkh (var_8, 8'h5a); end 22, 23, 24: begin `checkh (var_1, 0); `checkh (var_8, 8'ha5); end default: begin `checkh ({var_8, var_1}, cyc[0 +: 9] - 1); end endcase if (cyc == 30) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_multitop_sig_bad.out0000644000542200017500000000136615101701376023475 0ustar mahmoudyfreeshell%Warning-MULTITOP: t/t_multitop_sig.v:15:8: Multiple top level modules : ... Suggest see manual; fix the duplicates, or use --top-module to select top. ... For warning description see https://verilator.org/warn/MULTITOP?v=latest ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message. : ... Top module 'a' 7 | module a(in, out); | ^ : ... Top module 'b' 15 | module b(in, out); | ^ : ... Top module 'c' 23 | module c(uniq_in, uniq_out); | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_var_port_bad.out0000644000542200017500000000040015101701376022576 0ustar mahmoudyfreeshell%Error: t/t_var_port_bad.v:16:13: Input/output/inout does not appear in port list: 'b' 16 | input a, b; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_mem_multi_ref_bad.py0000755000542200017500000000107615101701376023424 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint( fails=test.vlt_all, nc=False, # Need to get it not to give the prompt expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_initial.v0000644000542200017500000000177715101701376021245 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg _ranit; `include "t_initial_inc.vh" // surefire lint_off STMINI initial assign user_loaded_value = 1; initial _ranit = 0; always @ (posedge clk) begin if (!_ranit) begin _ranit <= 1; // Test $time // surefire lint_off CWECBB if ($time<20) $write("time<20\n"); // surefire lint_on CWECBB // Test $write $write ("[%0t] %m: User loaded ", $time); $display ("%b", user_loaded_value); if (user_loaded_value!=1) $stop; // Test $c `ifdef VERILATOR $c ("VL_PRINTF(\"Hi From C++\\n\");"); `endif user_loaded_value <= 2; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_trace_ascendingrange_fst.out0000644000542200017500000002673415101701376025160 0ustar mahmoudyfreeshell$date Wed Feb 23 00:02:30 2022 $end $version fstWriter $end $timescale 1ps $end $scope module top $end $var wire 1 ! clk $end $scope module t $end $var parameter 8 " P [0:7] $end $var wire 1 ! clk $end $var int 32 # cyc [31:0] $end $var parameter 8 $ Q [0:7] $end $var logic 1 % v_a [0:0] $end $var logic 2 & v_b [0:1] $end $var logic 8 ' v_c [0:7] $end $var logic 9 ( v_d [0:8] $end $var logic 16 ) v_e [0:15] $end $var logic 17 * v_f [0:16] $end $var logic 32 + v_g [0:31] $end $var logic 33 , v_h [0:32] $end $var logic 64 - v_i [0:63] $end $var logic 65 . v_j [0:64] $end $var logic 128 / v_k [0:127] $end $var logic 129 0 v_l [0:128] $end $var logic 256 1 v_m [0:255] $end $var logic 257 2 v_n [0:256] $end $var logic 512 3 v_o [0:511] $end $var logic 3 4 v_p [-1:1] $end $var logic 15 5 v_q [-7:7] $end $var logic 31 6 v_r [-15:15] $end $var logic 63 7 v_s [-31:31] $end $var logic 127 8 v_t [-63:63] $end $var logic 255 9 v_u [-127:127] $end $var logic 511 : v_v [-255:255] $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 : b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 9 b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 8 b000000000000000000000000000000000000000000000000000000000000000 7 b0000000000000000000000000000000 6 b000000000000000 5 b000 4 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2 b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 1 b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 0 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 / b00000000000000000000000000000000000000000000000000000000000000000 . b0000000000000000000000000000000000000000000000000000000000000000 - b000000000000000000000000000000000 , b00000000000000000000000000000000 + b00000000000000000 * b0000000000000000 ) b000000000 ( b00000000 ' b00 & 0% b00010100 $ b00000000000000000000000000000000 # b00001010 " 0! $end #10 1! b00000000000000000000000000000001 # 1% b11 & b11111111 ' b111111111 ( b1111111111111111 ) b11111111111111111 * b11111111111111111111111111111111 + b111111111111111111111111111111111 , b1111111111111111111111111111111111111111111111111111111111111111 - b11111111111111111111111111111111111111111111111111111111111111111 . b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 / b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 0 b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 1 b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 2 b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 3 b111 4 b111111111111111 5 b1111111111111111111111111111111 6 b111111111111111111111111111111111111111111111111111111111111111 7 b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 8 b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 9 b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 : #15 0! #20 1! b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 : b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 9 b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 8 b111111111111111111111111111111111111111111111111111111111111110 7 b1111111111111111111111111111110 6 b111111111111110 5 b110 4 b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 3 b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 2 b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 1 b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 0 b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 / b11111111111111111111111111111111111111111111111111111111111111110 . b1111111111111111111111111111111111111111111111111111111111111110 - b111111111111111111111111111111110 , b11111111111111111111111111111110 + b11111111111111110 * b1111111111111110 ) b111111110 ( b11111110 ' b10 & 0% b00000000000000000000000000000010 # #25 0! #30 1! b00000000000000000000000000000011 # b00 & b11111100 ' b111111100 ( b1111111111111100 ) b11111111111111100 * b11111111111111111111111111111100 + b111111111111111111111111111111100 , b1111111111111111111111111111111111111111111111111111111111111100 - b11111111111111111111111111111111111111111111111111111111111111100 . b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 / b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 0 b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 1 b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 2 b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 3 b100 4 b111111111111100 5 b1111111111111111111111111111100 6 b111111111111111111111111111111111111111111111111111111111111100 7 b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 8 b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 9 b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 : verilator-5.042/test_regress/t/t_trace_cat_fst.cpp0000644000542200017500000000252215101701376022717 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include #include #include VM_PREFIX_INCLUDE unsigned long long main_time = 0; double sc_time_stamp() { return (double)main_time; } const char* trace_name() { static char name[1000]; VL_SNPRINTF(name, 1000, VL_STRINGIFY(TEST_OBJ_DIR) "/simpart_%04d.fst", (int)main_time); return name; } int main(int argc, char** argv) { Verilated::debug(0); Verilated::traceEverOn(true); Verilated::commandArgs(argc, argv); std::unique_ptr top{new VM_PREFIX{"top"}}; std::unique_ptr tfp{new VerilatedFstC}; top->trace(tfp.get(), 99); tfp->open(trace_name()); top->clk = 0; while (main_time < 190) { // Creates 2 files top->clk = !top->clk; top->eval(); if ((main_time % 100) == 0) { tfp->close(); tfp->open(trace_name()); } tfp->dump((unsigned int)(main_time)); ++main_time; } tfp->close(); top->final(); tfp.reset(); top.reset(); printf("*-* All Finished *-*\n"); return 0; } verilator-5.042/test_regress/t/t_opt_table_real.out0000644000542200017500000000017515101701376023121 0ustar mahmoudyfreeshellcyle 0 = 1.0 cyle 1 = 2.0 cyle 2 = 3.0 cyle 3 = 0.0 cyle 4 = 5.0 cyle 5 = 6.0 cyle 6 = 0.0 cyle 7 = 0.0 *-* All Finished *-* verilator-5.042/test_regress/t/t_math_cv_bitop.v0000644000542200017500000000472315101701376022424 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module sub ( input wire clock_4, input wire clock_8, output wire [28:5] out63 ); reg [28:0] reg_12; reg [28:22] reg_24; wire _0558_ = | reg_24[26:25]; // reg_24 = 0 or 1100110 ---> _0558_ == 0 wire [28:0] _0670_ = _0558_ ? reg_12 : 29'h00000f93; // _0558_ == 0 ---> _0670_ == 29'h00000f93 wire [28:0] _0399_= - _0670_; // _0670_ == 29'h00000f93 ---> _0399_ = 29'b11111111111111111000001101101 wire _0085_ = ~ _0399_[2]; // _0399_[2] == 1 ---> _0085_ == 0 wire [28:0] _0769_; assign { _0769_[28:3], _0769_[1:0] } = { _0399_[28:3], _0399_[1:0] }; // _0769_ != 0 assign _0769_[2] = _0085_; // verilator lint_off WIDTH wire _0305_ = ! _0769_; // _0769_ != 0 ---> _0305_ == 0 wire [23:0] _0306_ = ! _0305_; // _0305_ == 0 ---> _0306_ == 1 // verilator lint_on WIDTH assign out63 = _0306_; // out63 == 1 always @(posedge clock_4, posedge clock_8) if (clock_8) reg_12 <= 29'h00000066; else reg_12 <= { reg_12[28:27], 25'h0000001, reg_12[1:0] }; always @(posedge clock_4, posedge clock_8) if (clock_8) reg_24 <= 7'h66; else reg_24 <= reg_24; endmodule module t; reg clock_4; reg clock_8; wire signed [28:5] out63; reg signed [7:0] tmp = -1; reg signed [0:0] one = 1; reg signed [0:0] onert = 1; sub sub ( .clock_4 (clock_4), .clock_8 (clock_8), .out63 (out63) ); initial begin // All simulators agree: 1'sb1 really shows as decimal -1 $display("one 'd=%d 'b=%b", one, one); `ifdef VERILATOR onert = $c(1); `endif $display("ort 'd=%d 'b=%b", onert, onert); $display("tmp 'd=%d 'b=%b", tmp, tmp); clock_4 = 0; clock_8 = 0; #2000; sub.reg_24 = 0; sub.reg_12 = 0; #2000; clock_4 = 0; clock_8 = 0; #10; $display("out63 'd=%d 'b=%b", out63, out63); #2000; clock_4 = 1; clock_8 = 1; #10; $display("out63 'd=%d 'b=%b", out63, out63); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_typedef_no_bad.v0000644000542200017500000000041315101701376022540 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 typedef sometype; module t; sometype p; endmodule verilator-5.042/test_regress/t/t_wrapper_reuse_context_bad.py0000755000542200017500000000112715101701376025224 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Multiple Model Test Module # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) test.execute(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_unused_iface.v0000644000542200017500000000203415101701376023257 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface dummy_if (); logic signal; modport slave ( input signal ); modport master ( output signal ); endinterface: dummy_if module sub ( input wire signal_i, output wire signal_o, dummy_if.master dummy_in, dummy_if.slave dummy_out ); assign dummy_in.signal = signal_i; assign signal_o = dummy_out.signal; endmodule module t (/*AUTOARG*/ // Outputs signal_o, // Inputs signal_i ); input signal_i; output signal_o; // verila tor lint_off UUSD // verila tor lint_off UNDRIVEN dummy_if dummy_if (); // verila tor lint_on UUSD // verila tor lint_on UNDRIVEN dummy_if uusd_if (); sub sub ( .signal_i(signal_i), .signal_o(signal_o), .dummy_in(dummy_if), .dummy_out(dummy_if) ); endmodule verilator-5.042/test_regress/t/t_preproc_persist2.v0000644000542200017500000000041415101701376023104 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 Inside `__FILE__. `include "t_preproc_persist_inc.v" verilator-5.042/test_regress/t/t_vlcov_info.info.out0000644000542200017500000000026115101701376023237 0ustar mahmoudyfreeshellTN:verilator_coverage SF:file1.sp DA:159,22 BRDA:159,0,0,0 BRDA:159,0,1,1 BRDA:159,0,2,20 BRDA:159,0,3,0 BRDA:159,0,4,1 BRDA:159,0,5,9 BRDA:159,0,6,22 BRF:7 BRH:2 end_of_record verilator-5.042/test_regress/t/t_flag_parameter_pkg.py0000755000542200017500000000102715101701376023600 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['-GPARAM_A=1'], ms_flags2=['-GPARAM_A=1']) test.execute() test.passes() verilator-5.042/test_regress/t/t_order_comboclkloop.v0000644000542200017500000000351515101701376023462 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; // verilator lint_off COMBDLY // verilator lint_off LATCH // verilator lint_off UNOPT // verilator lint_off UNOPTFLAT // verilator lint_off MULTIDRIVEN reg [31:0] runnerm1, runner; initial runner = 0; reg [31:0] runcount; initial runcount = 0; reg [31:0] clkrun; initial clkrun = 0; reg [31:0] clkcount; initial clkcount = 0; always @ (/*AS*/runner) begin runnerm1 = runner - 32'd1; end reg run0; always @ (/*AS*/runnerm1) begin if ((runner & 32'hf)!=0) begin runcount = runcount + 1; runner = runnerm1; $write(" seq runcount=%0d runner =%0x\n", runcount, runnerm1); end run0 = (runner[8:4]!=0 && runner[3:0]==0); end always @ (posedge run0) begin // Do something that forces another combo run clkcount <= clkcount + 1; runner[8:4] <= runner[8:4] - 1; runner[3:0] <= 3; $write ("[%0t] posedge runner=%0x\n", $time, runner); end reg [7:0] cyc; initial cyc = 0; always @ (posedge clk) begin $write("[%0t] %x counts %0x %0x\n", $time, cyc, runcount, clkcount); cyc <= cyc + 8'd1; case (cyc) 8'd00: begin runner <= 0; end 8'd01: begin runner <= 32'h35; end default: ; endcase case (cyc) 8'd02: begin if (runcount!=32'he) $stop; if (clkcount!=32'h3) $stop; end 8'd03: begin $write("*-* All Finished *-*\n"); $finish; end default: ; endcase end endmodule verilator-5.042/test_regress/t/t_interface_generic_modport_task.py0000755000542200017500000000101315101701376026203 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(timing_loop=True, verilator_flags2=['--timing']) test.execute() test.passes() verilator-5.042/test_regress/t/t_var_port_json_only.v0000644000542200017500000000342615101701376023533 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // This checks IEEE ports work correctly, we use XML output to make it easy to // see all attributes are propagated // verilator lint_off MULTITOP `ifndef VERILATOR module mh0 (wire x_inout_wire_logic); endmodule module mh1 (integer x_inout_wire_integer); endmodule `endif module mh2 (inout integer x_inout_wire_integer); endmodule `ifndef VERILATOR module mh3 ([5:0] x_inout_wire_logic_p6); endmodule `endif module mh5 (input x_input_wire_logic); endmodule module mh6 (input var x_input_var_logic); endmodule module mh7 (input var integer x_input_var_integer); endmodule module mh8 (output x_output_wire_logic); endmodule module mh9 (output var x_output_var_logic); endmodule module mh10(output signed [5:0] x_output_wire_logic_signed_p6); endmodule module mh11(output integer x_output_var_integer); endmodule module mh12(ref [5:0] x_ref_logic_p6); endmodule module mh13(ref x_ref_var_logic_u6 [5:0]); endmodule `ifndef VERILATOR module mh14(wire x_inout_wire_logic, y_inout_wire_logic_p8 [7:0]); endmodule module mh15(integer x_inout_wire_integer, signed [5:0] y_inout_wire_logic_signed6); endmodule module mh16([5:0] x_inout_wire_logic_p6, wire y_inout_wire_logic); endmodule `endif module mh17(input var integer x_input_var_integer, wire y_input_wire_logic); endmodule module mh18(output var x_output_var_logic, input y_input_wire_logic); endmodule module mh19(output signed [5:0] x_output_wire_logic_signed_p6, integer y_output_var_integer); endmodule module mh20(ref [5:0] x_ref_var_logic_p6, y_ref_var_logic_p6); endmodule module mh21(ref ref_var_logic_u6 [5:0], y_ref_var_logic); endmodule verilator-5.042/test_regress/t/t_randomize_queue_size.v0000755000542200017500000000365115101701376024036 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `define check_rand(cl, field, cond) \ begin \ longint prev_result; \ int ok = 0; \ if (!bit'(cl.randomize())) $stop; \ prev_result = longint'(field); \ if (!(cond)) $stop; \ repeat(9) begin \ longint result; \ if (!bit'(cl.randomize())) $stop; \ result = longint'(field); \ if (!(cond)) $stop; \ if (result != prev_result) ok = 1; \ prev_result = result; \ end \ if (ok != 1) $stop; \ end class Foo; rand int q[$]; rand int q2[$][$]; int x = 1; constraint c { q.size() == 15; q2.size() == 10; } endclass class Bar; rand int q[$]; rand int min_size; rand int q2[$]; constraint c { min_size > 2; q.size() >= min_size; q.size() < 10; }; constraint c2 { q2.size() < 7; } endclass class Baz; rand Foo foo_arr[]; constraint c_foo { foo_arr.size == 7; } endclass module t; initial begin Foo foo = new; Bar bar = new; Baz baz = new; void'(foo.randomize()); if (foo.q.size() != 15) $stop; if (foo.q2.size() != 10) $stop; `check_rand(bar, bar.q.size(), bar.q.size() > 2 && bar.q.size() < 10); `check_rand(bar, bar.q2.size(), bar.q2.size() < 7); baz.foo_arr = new[4]; for (int i = 0; i < 4; i++) baz.foo_arr[i] = new; baz.foo_arr[2].x = 2; void'(baz.randomize()); if (baz.foo_arr.size() != 7) $stop; for (int i = 0; i < 4; i++) if (baz.foo_arr[i] == null) $stop; for (int i = 4; i < 7; i++) if (baz.foo_arr[i] != null) $stop; if (baz.foo_arr[2].x != 2) $stop; `check_rand(baz, baz.foo_arr[1].q[5], 1'b1); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_inst_array_struct.py0000755000542200017500000000073415101701376023551 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_param_noval_bad.v0000644000542200017500000000054515101701376022711 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t #(parameter P, parameter type T); generate var j; for (j=0; P; j++) initial begin end endgenerate endmodule verilator-5.042/test_regress/t/t_param_if_blk.py0000755000542200017500000000073415101701376022400 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_stop_winos_bad.v0000644000542200017500000000103415101701376022610 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `line 7 "C:\\some\\windows\\path\\t_stop_winos_bad.v" 0 module t; localparam string FILENAME = `__FILE__; initial begin $write("Intentional stop\n"); // Print length to make sure \\ counts as 1 character $write("Filename '%s' Length = %0d\n", FILENAME, FILENAME.len()); $stop; end endmodule verilator-5.042/test_regress/t/t_param_typedef.v0000644000542200017500000000236615101701376022427 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilator lint_off IMPLICIT module fifo_v3 #( parameter int unsigned DATA_WIDTH = 32, parameter int unsigned DEPTH = 8, parameter type dtype_t = logic [DATA_WIDTH-1:0] )( input int data_i, output int data_o ); if (DEPTH == 0) begin : gen_pass_through end endmodule module axi_lite_mux #( parameter int unsigned NoSlvPorts = 32'd32, parameter int unsigned MaxTrans = 32'd0 ) ( input logic clk_i, input logic rst_ni ); wire [31:0] ar_select; wire [31:0] r_select; if (NoSlvPorts == 32'h1) begin : gen_no_mux end else begin : gen_mux typedef logic [$clog2(NoSlvPorts)-1:0] select_t; fifo_v3 #( .DEPTH ( MaxTrans ), .dtype_t ( select_t ) ) i_r_fifo ( .data_i ( ar_select ), .data_o ( r_select ) ); end endmodule module t ( input logic clk_i, input logic rst_ni ); axi_lite_mux i_axi_mux ( .clk_i, .rst_ni); endmodule verilator-5.042/test_regress/t/t_flag_timescale_override.v0000644000542200017500000000071015101701376024434 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under The Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `timescale 1s/1s module t; sub sub (); initial begin $printtimescale; sub.pts(); $write("*-* All Finished *-*\n"); $finish; end endmodule module sub; task pts; $printtimescale; endtask endmodule verilator-5.042/test_regress/t/t_lint_pindup_bad.out0000644000542200017500000000307715101701376023304 0ustar mahmoudyfreeshell%Warning-PINMISSING: t/t_lint_pindup_bad.v:18:4: Instance has missing pin: 'exists' 18 | sub (.o(o), | ^~~ t/t_lint_pindup_bad.v:32:15: ... Location of port declaration 32 | input wire exists | ^~~~~~ ... For warning description see https://verilator.org/warn/PINMISSING?v=latest ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message. %Error: t/t_lint_pindup_bad.v:20:10: Duplicate pin connection: 'i' 20 | .i(i2), | ^ t/t_lint_pindup_bad.v:19:10: ... Location of original pin connection 19 | .i(i), | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error-PINNOTFOUND: t/t_lint_pindup_bad.v:21:10: Pin not found: 'nexist' : ... Suggested alternative: 'exists' 21 | .nexist(i2) | ^~~~~~ ... For error description see https://verilator.org/warn/PINNOTFOUND?v=latest %Error-PINNOTFOUND: t/t_lint_pindup_bad.v:15:9: Parameter not found: 'NEXIST' : ... Suggested alternative: 'EXIST' 15 | #(.NEXIST(1), | ^~~~~~ %Error: t/t_lint_pindup_bad.v:17:9: Duplicate parameter connection: 'P' 17 | .P(3)) | ^ t/t_lint_pindup_bad.v:16:9: ... Location of original parameter connection 16 | .P(2), | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_altera_lpm_compare.py0000755000542200017500000000111115101701376023606 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) test.compile(verilator_flags2=["--top-module", module]) test.passes() verilator-5.042/test_regress/t/t_select_bad_range2.py0000755000542200017500000000077615101701376023323 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_struct_assign.py0000755000542200017500000000100015101701376022645 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface_generic_function_bad.out0000755000542200017500000000070215101701376026313 0ustar mahmoudyfreeshell%Error: t/t_interface_generic_function_bad.v:14:11: Can't find definition of 'get' in dotted task/function: 'a.get' : ... note: In instance 't.genericModule' 14 | if (a.get() != 4) $stop; | ^~~ ... Known scopes under 'get': ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_array_compare.v0000644000542200017500000000273015101701376022426 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2016 by Andrew Bardsley. // SPDX-License-Identifier: CC0-1.0 // bug1071 module t; reg [3:0] array_1 [2:0]; reg [3:0] array_2 [2:0]; reg [3:0] array_3 [3:1]; reg [3:0] elem; reg array_1_ne_array_2; reg array_1_eq_array_2; reg array_1_ne_array_3; reg array_1_eq_array_3; initial begin array_1[0] = 4'b1000; array_1[1] = 4'b1000; array_1[2] = 4'b1000; array_2[0] = 4'b1000; array_2[1] = 4'b1000; array_2[2] = 4'b1000; array_3[1] = 4'b1000; array_3[2] = 4'b0100; array_3[3] = 4'b0100; array_1_ne_array_2 = array_1 != array_2; // 0 array_1_eq_array_2 = array_1 == array_2; // 0 array_1_ne_array_3 = array_1 != array_3; // 1 array_1_eq_array_3 = array_1 == array_3; // 1 //Not legal: array_rxor = ^ array_1; //Not legal: array_rxnor = ^~ array_1; //Not legal: array_ror = | array_1; //Not legal: array_rand = & array_1; `ifdef TEST_VERBOSE $write("array_1_ne_array2==%0d\n", array_1_ne_array_2); $write("array_1_ne_array3==%0d\n", array_1_ne_array_3); `endif if (array_1_ne_array_2 !== 0) $stop; if (array_1_eq_array_2 !== 1) $stop; if (array_1_ne_array_3 !== 1) $stop; if (array_1_eq_array_3 !== 0) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_inst_mism.v0000644000542200017500000000142015101701376021577 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Alex Solomatnikov. // SPDX-License-Identifier: CC0-1.0 //bug595 module t (/*AUTOARG*/ // Inputs clk ); input clk; logic [6-1:0] foo; initial foo = 20; dut #(.W(6)) udut(.clk(clk), .foo(foo-16)); endmodule module dut #(parameter W = 1) (input logic clk, input logic [W-1:0] foo); genvar i; generate for (i = 0; i < W; i++) begin suba ua(.clk(clk), .foo(foo[i])); end endgenerate endmodule module suba (input logic clk, input logic foo); always @(posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_select_plus.v0000644000542200017500000000771315101701376022132 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [83:4] from; reg [83:4] to; reg [6:0] bitn; reg [3:0] nibblep; reg [3:0] nibblem; reg [7:0] cyc; initial cyc = 0; always @* begin nibblep = from[bitn +: 4]; nibblem = from[bitn -: 4]; to = from; to[bitn +: 4] = cyc[3:0]; to[bitn -: 4] = cyc[3:0]; end always @ (posedge clk) begin //$write("[%0t] cyc==%d nibblep==%b nibblem==%b to^from==%x\n", $time, cyc, nibblep, nibblem, from^to); cyc <= cyc + 8'd1; case (cyc) 8'd00: begin from<=80'h7bea9d779b67e48f67da; bitn<=7'd7; end 8'd01: begin from<=80'hefddce326b11ca5dc448; bitn<=7'd8; end 8'd02: begin from<=80'h3f99c5f34168401e210d; bitn<=7'd4; end // truncate -: 8'd03: begin from<=80'hc90635f0a7757614ce3f; bitn<=7'd79; end 8'd04: begin from<=80'hc761feca3820331370ec; bitn<=7'd83; end // truncate +: 8'd05: begin from<=80'hd6e36077bf28244f84b5; bitn<=7'd6; end // half trunc 8'd06: begin from<=80'h90118c5d3d285a1f3252; bitn<=7'd81; end // half trunc 8'd07: begin from<=80'h38305da3d46b5859fe16; bitn<=7'd67; end 8'd08: begin from<=80'h4b9ade23a8f5cc5b3111; bitn<=7'd127; end // truncate 8'd09: begin $write("*-* All Finished *-*\n"); $finish; end default: ; endcase case (cyc) 8'd00: ; 8'd01: begin if ((nibblep & 4'b1111)!==4'b1011) $stop; if ((nibblem & 4'b1111)!==4'b1010) $stop; end 8'd02: begin if ((nibblep & 4'b1111)!==4'b0100) $stop; if ((nibblem & 4'b1111)!==4'b0100) $stop; end 8'd03: begin if ((nibblep & 4'b1111)!==4'b1101) $stop; if ((nibblem & 4'b0000)!==4'b0000) $stop; end 8'd04: begin if ((nibblep & 4'b1111)!==4'b1001) $stop; if ((nibblem & 4'b1111)!==4'b1001) $stop; end 8'd05: begin if ((nibblep & 4'b0000)!==4'b0000) $stop; if ((nibblem & 4'b1111)!==4'b1100) $stop; end 8'd06: begin if ((nibblep & 4'b1111)!==4'b1101) $stop; if ((nibblem & 4'b0000)!==4'b0000) $stop; end 8'd07: begin if ((nibblep & 4'b0000)!==4'b0000) $stop; if ((nibblem & 4'b1111)!==4'b0100) $stop; end 8'd08: begin if ((nibblep & 4'b1111)!==4'b0000) $stop; if ((nibblem & 4'b1111)!==4'b0101) $stop; end 8'd09: begin if ((nibblep & 4'b0000)!==4'b0000) $stop; if ((nibblem & 4'b0000)!==4'b0000) $stop; end default: $stop; endcase case (cyc) 8'd00: ; 8'd01: begin if ((to^from)!==80'h0000000000000000005b) $stop; end 8'd02: begin if ((to^from)!==80'h0000000000000000006c) $stop; end 8'd03: begin if ((to^from)!==80'h0000000000000000000e) $stop; end 8'd04: begin if ((to^from)!==80'h6d000000000000000000) $stop; end 8'd05: begin if (((to^from)&~80'hf)!==80'h90000000000000000000) $stop; end // Exceed bounds, verilator may write index 0 8'd06: begin if (((to^from)&~80'hf)!==80'h00000000000000000020) $stop; end // Exceed bounds, verilator may write index 0 8'd07: begin if (((to^from)&~80'hf)!==80'h4c000000000000000000) $stop; end 8'd08: begin if ((to^from)!==80'h0004d000000000000000) $stop; end 8'd09: begin if (((to^from)&~80'hf)!==80'h00000000000000000000) $stop; end default: $stop; endcase end // Additional constant folding check - this used to trigger a bug reg [23:0] a; reg [3:0] b; initial begin a = 24'd0; b = 4'b0111; a[3*(b[2:0]+0)+:3] = 3'd7; // Check LSB expression goes to 32-bits if (a != 24'b11100000_00000000_00000000) $stop; a = 24'd0; b = 4'b0110; a[3*(b[2:0]+0)-:3] = 3'd7; // Check MSB expression goes to 32-bits if (a != 24'b00000111_00000000_00000000) $stop; end endmodule verilator-5.042/test_regress/t/t_flag_language_bad.py0000755000542200017500000000106015101701376023345 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=['--language 1-2-3-4'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_flag_binary_parallel.py0000755000542200017500000000126515101701376024123 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_flag_main.v" test.compile( verilator_flags=[ # Custom as don't want -cc "-Mdir", test.obj_dir, "--debug-check" ], verilator_flags2=['--binary', '--output-split 1'], make_main=False) test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_packed_struct_fst.out0000644000542200017500000000155615101701376025036 0ustar mahmoudyfreeshell$date Wed Feb 23 00:02:43 2022 $end $version fstWriter $end $timescale 1ps $end $scope module top $end $var wire 1 ! clk $end $scope module t $end $var wire 1 ! clk $end $var int 32 " cnt [31:0] $end $var parameter 96 # v[0] [95:0] $end $var parameter 96 $ v[1] [95:0] $end $var parameter 96 % v[2] [95:0] $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b000100000000000000000000000000100001000000000000000000000000000100010000000000000000000000000000 % b001000000000000000000000000000100010000000000000000000000000000100100000000000000000000000000000 $ b001100000000000000000000000000100011000000000000000000000000000100110000000000000000000000000000 # b00000000000000000000000000000000 " 0! $end #10 1! b00000000000000000000000000000001 " #15 0! #20 1! b00000000000000000000000000000010 " #25 0! #30 1! b00000000000000000000000000000011 " #35 0! #40 1! verilator-5.042/test_regress/t/t_no_sel_assign_merge_in_cpp.py0000755000542200017500000000070315101701376025320 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint() test.passes() verilator-5.042/test_regress/t/t_flag_f_bad_getenvend.vc0000644000542200017500000000002615101701376024024 0ustar mahmoudyfreeshell$(GETENV_NO_END_PAREN verilator-5.042/test_regress/t/t_func_virt_new_bad.out0000755000542200017500000000054515101701376023627 0ustar mahmoudyfreeshell%Error: t/t_func_virt_new_bad.v:9:13: Illegal to call 'new' using an abstract virtual class 'vcl' (IEEE 1800-2023 8.21) : ... note: In instance 't' 9 | T obj = new; | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_pp_defkwd_bad.v0000644000542200017500000000034715101701376022355 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define define 1 verilator-5.042/test_regress/t/t_inst_long_bad.py0000755000542200017500000000076615101701376022601 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_sys_readmem.v0000644000542200017500000002220115101701376022105 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `ifdef WRITEMEM_BIN `define READMEMX $readmemb `define WRITEMEMX $writememb `else `define READMEMX $readmemh `define WRITEMEMX $writememh `endif module t; // verilator lint_off ASCRANGE reg [5:0] binary_string [2:15]; reg [5:0] binary_nostart [2:15]; reg [5:0] binary_start [0:15]; reg [175:0] hex [0:15]; reg [(32*6)-1:0] hex_align [0:15]; reg [55:0] qdata [0:15]; reg [25:0] idata [0:15]; reg [10:0] sdata [0:15]; reg [6:0] cdata [0:15]; string fns; `ifdef WRITEMEM_READ_BACK reg [5:0] binary_string_tmp [2:15]; reg [5:0] binary_nostart_tmp [2:15]; reg [5:0] binary_start_tmp [0:15]; reg [175:0] hex_tmp [0:15]; reg [(32*6)-1:0] hex_align_tmp [0:15]; reg [55:0] qdata_tmp [0:15]; reg [25:0] idata_tmp [0:15]; reg [10:0] sdata_tmp [0:15]; reg [6:0] cdata_tmp [0:15]; string fns_tmp; `endif // verilator lint_on ASCRANGE integer i; initial begin begin // Initialize memories to zero, // avoid differences between 2-state and 4-state. for (i=0; i<16; i=i+1) begin binary_start[i] = '0; hex[i] = '0; hex_align[i] = '0; qdata[i] = '0; idata[i] = '0; sdata[i] = '0; cdata[i] = '0; `ifdef WRITEMEM_READ_BACK binary_start_tmp[i] = '0; hex_tmp[i] = '0; hex_align_tmp[i] = '0; qdata_tmp[i] = '0; idata_tmp[i] = '0; sdata_tmp[i] = '0; cdata_tmp[i] = '0; `endif end for (i=2; i<16; i=i+1) begin binary_string[i] = 6'h0; binary_nostart[i] = 6'h0; `ifdef WRITEMEM_READ_BACK binary_string_tmp[i] = 6'h0; binary_nostart_tmp[i] = 6'h0; `endif end end begin `ifdef WRITEMEM_READ_BACK $readmemb("t/t_sys_readmem_b.mem", binary_nostart_tmp); // Do a round-trip $writememh(b) and $readmemh(b) cycle. // This covers $writememh and ensures we can read our // own memh output file. // If WRITEMEM_BIN is also defined, use $writememb and // $readmemb, otherwise use $writememh and $readmemh. `ifdef TEST_VERBOSE $display("-Writing %s", `OUT_TMP1); `endif `WRITEMEMX(`OUT_TMP1, binary_nostart_tmp); `READMEMX(`OUT_TMP1, binary_nostart); `else $readmemb("t/t_sys_readmem_b.mem", binary_nostart); `endif `ifdef TEST_VERBOSE for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, binary_nostart[i]); `endif if (binary_nostart['h2] != 6'h02) $stop; if (binary_nostart['h3] != 6'h03) $stop; if (binary_nostart['h4] != 6'h04) $stop; if (binary_nostart['h5] != 6'h05) $stop; if (binary_nostart['h6] != 6'h06) $stop; if (binary_nostart['h7] != 6'h07) $stop; if (binary_nostart['h8] != 6'h10) $stop; if (binary_nostart['hc] != 6'h14) $stop; if (binary_nostart['hd] != 6'h15) $stop; end begin binary_start['h0c] = 6'h3f; // Not in read range // `ifdef WRITEMEM_READ_BACK $readmemb("t/t_sys_readmem_b_8.mem", binary_start_tmp, 4, 4+7); `ifdef TEST_VERBOSE $display("-Writing %s", `OUT_TMP2); `endif `WRITEMEMX(`OUT_TMP2, binary_start_tmp, 4, 4+7); `READMEMX(`OUT_TMP2, binary_start, 4, 4+7); `else $readmemb("t/t_sys_readmem_b_8.mem", binary_start, 4, 4+7); // 4-11 `endif `ifdef TEST_VERBOSE for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, binary_start[i]); `endif if (binary_start['h04] != 6'h10) $stop; if (binary_start['h05] != 6'h11) $stop; if (binary_start['h06] != 6'h12) $stop; if (binary_start['h07] != 6'h13) $stop; if (binary_start['h08] != 6'h14) $stop; if (binary_start['h09] != 6'h15) $stop; if (binary_start['h0a] != 6'h16) $stop; if (binary_start['h0b] != 6'h17) $stop; // if (binary_start['h0c] != 6'h3f) $stop; end begin // The 'hex' array is a non-exact multiple of word size // (possible corner case) `ifdef WRITEMEM_READ_BACK $readmemh("t/t_sys_readmem_h.mem", hex_tmp, 0); `ifdef TEST_VERBOSE $display("-Writing %s", `OUT_TMP3); `endif `WRITEMEMX(`OUT_TMP3, hex_tmp, 0); `READMEMX(`OUT_TMP3, hex, 0); `else $readmemh("t/t_sys_readmem_h.mem", hex, 0); `endif `ifdef TEST_VERBOSE for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, hex[i]); `endif if (hex['h04] != 176'h400437654321276543211765432107654321abcdef10) $stop; if (hex['h0a] != 176'h400a37654321276543211765432107654321abcdef11) $stop; if (hex['h0b] != 176'h400b37654321276543211765432107654321abcdef12) $stop; if (hex['h0c] != 176'h400c37654321276543211765432107654321abcdef13) $stop; end begin // The 'hex align' array is similar to 'hex', but it is an // exact multiple of word size -- another possible corner case. `ifdef WRITEMEM_READ_BACK $readmemh("t/t_sys_readmem_align_h.mem", hex_align_tmp, 0); `ifdef TEST_VERBOSE $display("-Writing %s", `OUT_TMP4); `endif `WRITEMEMX(`OUT_TMP4, hex_align_tmp, 0); `READMEMX(`OUT_TMP4, hex_align, 0); `else $readmemh("t/t_sys_readmem_align_h.mem", hex_align, 0); `endif `ifdef TEST_VERBOSE for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, hex_align[i]); `endif if (hex_align['h04] != 192'h77554004_37654321_27654321_17654321_07654321_abcdef10) $stop; if (hex_align['h0a] != 192'h7755400a_37654321_27654321_17654321_07654321_abcdef11) $stop; if (hex_align['h0b] != 192'h7755400b_37654321_27654321_17654321_07654321_abcdef12) $stop; if (hex_align['h0c] != 192'h7755400c_37654321_27654321_17654321_07654321_abcdef13) $stop; end begin `ifdef WRITEMEM_READ_BACK $readmemh("t/t_sys_readmem_q.mem", qdata_tmp, 0); `ifdef TEST_VERBOSE $display("-Writing %s", `OUT_TMP5); `endif `WRITEMEMX(`OUT_TMP5, qdata_tmp, 0); `READMEMX(`OUT_TMP5, qdata, 0); `else $readmemh("t/t_sys_readmem_q.mem", qdata, 0); `endif `ifdef TEST_VERBOSE for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, qdata[i]); `endif `checkh(qdata['h04], 56'hdcba9876540004); `checkh(qdata['h0a], 56'hdcba987654000a); `checkh(qdata['h0b], 56'hdcba987654000b); `checkh(qdata['h0c], 56'hdcba987654000c); end begin `ifdef WRITEMEM_READ_BACK $readmemh("t/t_sys_readmem_i.mem", idata_tmp, 0); `ifdef TEST_VERBOSE $display("-Writing %s", `OUT_TMP6); `endif `WRITEMEMX(`OUT_TMP6, idata_tmp, 0); `READMEMX(`OUT_TMP6, idata, 0); `else $readmemh("t/t_sys_readmem_i.mem", idata, 0); `endif `ifdef TEST_VERBOSE for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, idata[i]); `endif `checkh(idata['h04], 26'h6540004); `checkh(idata['h0a], 26'h654000a); `checkh(idata['h0b], 26'h654000b); `checkh(idata['h0c], 26'h654000c); end begin `ifdef WRITEMEM_READ_BACK $readmemh("t/t_sys_readmem_s.mem", sdata_tmp, 0); `ifdef TEST_VERBOSE $display("-Writing %s", `OUT_TMP7); `endif `WRITEMEMX(`OUT_TMP7, sdata_tmp, 0); `READMEMX(`OUT_TMP7, sdata, 0); `else $readmemh("t/t_sys_readmem_s.mem", sdata, 0); `endif `ifdef TEST_VERBOSE for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, sdata[i]); `endif `checkh(sdata['h04], 11'h654); `checkh(sdata['h0a], 11'h65a); `checkh(sdata['h0b], 11'h65b); `checkh(sdata['h0c], 11'h65c); end begin `ifdef WRITEMEM_READ_BACK $readmemh("t/t_sys_readmem_c.mem", cdata_tmp, 0); `ifdef TEST_VERBOSE $display("-Writing %s", `OUT_TMP8); `endif `WRITEMEMX(`OUT_TMP8, cdata_tmp, 0); `READMEMX(`OUT_TMP8, cdata, 0); `else $readmemh("t/t_sys_readmem_c.mem", cdata, 0); `endif `ifdef TEST_VERBOSE for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, cdata[i]); `endif `checkh(cdata['h04], 7'h14); `checkh(cdata['h0a], 7'h1a); `checkh(cdata['h0b], 7'h1b); `checkh(cdata['h0c], 7'h1c); end begin fns = "t/t_sys_readmem_b.mem"; `ifdef WRITEMEM_READ_BACK fns_tmp = `OUT_TMP8; $readmemb(fns, binary_string_tmp); `ifdef TEST_VERBOSE $display("-Writing %s", `OUT_TMP8); `endif `WRITEMEMX(fns_tmp, binary_string_tmp); `READMEMX(fns_tmp, binary_string); `else $readmemb(fns, binary_string); `endif `ifdef TEST_VERBOSE for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, binary_string[i]); `endif if (binary_string['h2] != 6'h02) $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_rand_stability_process.v0000644000542200017500000000167415101701376024356 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Aleksander Kiryk. // SPDX-License-Identifier: CC0-1.0 // This test checks if calls to get_randstate don't affect // the state of RNG. module t; integer a1, a2, b1, b2; string s1, s2; process p; initial begin p = process::self(); // 1. Take two random values with get_randstate call in between s1 = p.get_randstate(); a1 = $urandom; s2 = p.get_randstate(); a2 = $urandom; // 2. Take two random values again, this time without the call p.set_randstate(s1); b1 = $urandom; b2 = $urandom; // The initial state of RNG was restored before step 2., so each // corresponding call to $urandom should return the same value. if (a1 != b1) $stop; if (a2 != b2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_opt_table_struct.py0000755000542200017500000000130215101701376023337 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--stats"]) if test.vlt_all: test.file_grep(test.stats, r'Optimizations, Tables created\s+(\d+)', 1) test.file_grep(test.stats, r'ConstPool, Tables emitted\s+(\d+)', 1) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_clk_vecgen3.py0000755000542200017500000000104015101701376022144 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_clk_vecgen1.v" test.compile(v_flags2=['+define+T_TEST3']) test.execute() test.passes() verilator-5.042/test_regress/t/t_hier_block_prot_lib_shared.py0000755000542200017500000000344415101701376025314 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all', 'xsim') test.top_filename = "t/t_hier_block.v" secret_prefix = "secret" secret_dir = test.obj_dir + "/" + secret_prefix test.mkdir_ok(secret_dir) abs_secret_dir = os.path.abspath(secret_dir) # Always compile the secret file with Verilator no matter what simulator # we are testing with test.run(logfile=secret_dir + "/vlt_compile.log", cmd=[ "perl", os.environ["VERILATOR_ROOT"] + "/bin/verilator", "-cc", "--hierarchical", "-Mdir", secret_dir, "--protect-lib", secret_prefix, "--protect-key", "PROTECT_KEY", "t/t_hier_block.v", "-DAS_PROT_LIB", '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"', (' --threads 1' if test.vltmt else ''), "--build" ], verilator_run=True) test.compile( v_flags2=['t/t_hier_block.cpp'], verilator_flags2=[ secret_dir + "/secret.sv", "-DPROTLIB_TOP", "--top-module t", "-LDFLAGS", "'-Wl,-rpath," + abs_secret_dir + " -L" + abs_secret_dir + " -l" + secret_prefix + "'" ]) test.execute(run_env="DYLD_FALLBACK_LIBRARY_PATH=" + abs_secret_dir) test.file_grep(secret_dir + "/Vsub0/sub0.sv", r'^module\s+(\S+)\s+', "sub0") test.file_grep(secret_dir + "/Vsub1/sub1.sv", r'^module\s+(\S+)\s+', "sub1") test.file_grep(secret_dir + "/Vsub2/sub2.sv", r'^module\s+(\S+)\s+', "sub2") test.file_grep(test.run_log_filename, r'MACRO:(\S+) is defined', "cplusplus") test.passes() verilator-5.042/test_regress/t/t_concat_sel.v0000644000542200017500000000413715101701376021717 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [3:0] a = crc[3:0]; wire [3:0] b = crc[19:16]; // TEST wire [3:0] out1 = {a,b}[2 +: 4]; wire [3:0] out2 = {a,b}[5 -: 4]; wire [3:0] out3 = {a,b}[5 : 2]; wire [0:0] out4 = {a,b}[2]; // Aggregate outputs into a single result vector wire [63:0] result = {51'h0, out4, out3, out2, out1}; initial begin if ({16'h1234}[0] != 1'b0) $stop; if ({16'h1234}[2] != 1'b1) $stop; if ({16'h1234}[11:4] != 8'h23) $stop; if ({16'h1234}[4+:8] != 8'h23) $stop; if ({16'h1234}[11-:8] != 8'h23) $stop; if ({8'h12, 8'h34}[0] != 1'b0) $stop; if ({8'h12, 8'h34}[2] != 1'b1) $stop; if ({8'h12, 8'h34}[11:4] != 8'h23) $stop; if ({8'h12, 8'h34}[4+:8] != 8'h23) $stop; if ({8'h12, 8'h34}[11-:8] != 8'h23) $stop; $write("*-* All Finished *-*\n"); $finish; end // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc<10) begin sum <= '0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h4afe43fb79d7b71e if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_array_method.v0000644000542200017500000000642115101701376022261 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); // verilog_format: on module t; initial begin int q[5]; int qv[$]; // Value returns int qi[$]; // Index returns int i; string v; q = '{1, 2, 2, 4, 3}; `checkp(q, "'{'h1, 'h2, 'h2, 'h4, 'h3}"); // NOT tested: with ... selectors q.sort; `checkp(q, "'{'h1, 'h2, 'h2, 'h3, 'h4}"); q.sort with (item == 2); `checkp(q, "'{'h1, 'h3, 'h4, 'h2, 'h2}"); q.sort(x) with (x == 3); `checkp(q, "'{'h1, 'h4, 'h2, 'h2, 'h3}"); q.rsort; `checkp(q, "'{'h4, 'h3, 'h2, 'h2, 'h1}"); q.rsort with (item == 2); `checkp(q, "'{'h2, 'h2, 'h4, 'h3, 'h1}"); qv = q.unique; `checkp(qv, "'{'h2, 'h4, 'h3, 'h1}"); qi = q.unique_index; qi.sort; `checkp(qi, "'{'h0, 'h2, 'h3, 'h4}"); q.reverse; `checkp(q, "'{'h1, 'h3, 'h4, 'h2, 'h2}"); q.shuffle(); q.sort; `checkp(q, "'{'h1, 'h2, 'h2, 'h3, 'h4}"); // These require an with clause or are illegal // TODO add a lint check that with clause is provided qv = q.find with (item == 2); `checkp(qv, "'{'h2, 'h2}"); qv = q.find_first with (item == 2); `checkp(qv, "'{'h2}"); qv = q.find_last with (item == 2); `checkp(qv, "'{'h2}"); qv = q.find with (item == 20); `checkp(qv, "'{}"); qv = q.find_first with (item == 20); `checkp(qv, "'{}"); qv = q.find_last with (item == 20); `checkp(qv, "'{}"); qi = q.find_index with (item == 2); qi.sort; `checkp(qi, "'{'h1, 'h2}"); qi = q.find_first_index with (item == 2); `checkp(qi, "'{'h1}"); qi = q.find_last_index with (item == 2); `checkp(qi, "'{'h2}"); qi = q.find_index with (item == 20); qi.sort; `checkp(qi, "'{}"); qi = q.find_first_index with (item == 20); `checkp(qi, "'{}"); qi = q.find_last_index with (item == 20); `checkp(qi, "'{}"); qv = q.min; `checkp(qv, "'{'h1}"); qv = q.max; `checkp(qv, "'{'h4}"); // Reduction methods i = q.sum; `checkh(i, 32'hc); i = q.product; `checkh(i, 32'h30); q = '{32'b1100, 32'b1010, 32'b1100, 32'b1010, 32'b1010}; i = q.and; `checkh(i, 32'b1000); i = q.or; `checkh(i, 32'b1110); i = q.xor; `checkh(i, 32'ha); q = '{1, 2, 2, 4, 3}; // `checkp(q, "'{1, 2, 2, 4, 3}"); i = q.sum with (item + 1); `checkh(i, 32'h11); i = q.product with (item + 1); `checkh(i, 32'h168); q = '{32'b1100, 32'b1010, 32'b1100, 32'b1010, 32'b1010}; i = q.and with (item + 1); `checkh(i, 32'b1001); i = q.or with (item + 1); `checkh(i, 32'b1111); i = q.xor with (item + 1); `checkh(i, 32'hb); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_struct_array_assignment.v0000755000542200017500000000225515101701376024561 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by PlanV GmbH. // SPDX-License-Identifier: CC0-1.0 class unconstrained_struct_array_test; typedef struct { int field_a; int field_b; int field_c; } simple_struct_t; simple_struct_t struct_array[3]; // Unpacked array function new(); // Initialize struct_array struct_array = '{'{default: 0}, '{default: 1}, '{default: 2}}; endfunction // Self-check function to validate the array contents function void self_test(); foreach (struct_array[i]) begin if (struct_array[i].field_a != i) $stop; if (struct_array[i].field_b != i + 1) $stop; if (struct_array[i].field_c != i + 2) $stop; end endfunction endclass module t_struct_array_assignment; unconstrained_struct_array_test cl; initial begin cl = new(); foreach(cl.struct_array[i]) begin cl.struct_array[i].field_a = i; cl.struct_array[i].field_b = i + 1; cl.struct_array[i].field_c = i + 2; end cl.self_test(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_cast.v0000644000542200017500000000747315101701376020545 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface intf; typedef logic [7:0] octet; typedef octet [1:0] word; octet [1:0] octets; word [1:0] words; endinterface module t; typedef logic [3:0] mc_t; typedef mc_t tocast_t; typedef logic [2:0] [7:0] two_dee_t; typedef struct packed { logic [15:0] data; } packed_t; typedef struct packed { logic [31:0] data; } packed2_t; typedef enum [15:0] { ONE = 1 } enum_t; typedef enum_t [3:0] enums_t; packed_t pdata; packed_t pdata_reg; packed2_t pdata2_reg; assign pdata.data = 16'h1234; logic [7:0] logic8bit; assign logic8bit = $bits(logic8bit)'(pdata >> 8); mc_t o; enum_t e; enums_t es; intf the_intf(); logic [15:0] allones = 16'hffff; parameter FOUR = 4; localparam two_dee_t two_dee = two_dee_t'(32'habcdef); // bug925 localparam [6:0] RESULT = 7'((6*9+92)%96); logic signed [14:0] samp0 = 15'h0000; logic signed [14:0] samp1 = 15'h0000; logic signed [14:0] samp2 = 15'h6000; logic signed [11:0] coeff0 = 12'h009; logic signed [11:0] coeff1 = 12'h280; logic signed [11:0] coeff2 = 12'h4C5; logic signed [26:0] mida = ((27'(coeff2 * samp2) >>> 11)); // verilator lint_off WIDTH logic signed [26:0] midb = 15'((27'(coeff2 * samp2) >>> 11)); // verilator lint_on WIDTH logic signed [14:0] outa = 15'((27'(coeff0 * samp0) >>> 11) + // 27' size casting in order for intermediate result to not be truncated to the width of LHS vector (27'(coeff1 * samp1) >>> 11) + (27'(coeff2 * samp2) >>> 11)); // 15' size casting to avoid synthesis/simulator warnings logic one = 1'b1; logic [32:0] b33 = {32'(0), one}; logic [31:0] b32 = {31'(0), one}; logic [31:0] thirty_two_bits; two_dee_t two_dee_sig; int i; initial begin if (logic8bit != 8'h12) $stop; if (4'shf > 4'sh0) $stop; if (signed'(4'hf) > 4'sh0) $stop; if (4'hf < 4'h0) $stop; if (unsigned'(4'shf) < 4'h0) $stop; if (const'(4'shf) !== 4'shf) $stop; if (4'(allones) !== 4'hf) $stop; if (6'(allones) !== 6'h3f) $stop; if ((4)'(allones) !== 4'hf) $stop; if ((4+2)'(allones) !== 6'h3f) $stop; if ((4-2)'(allones) !== 2'h3) $stop; if ((FOUR+2)'(allones) !== 6'h3f) $stop; if (50 !== RESULT) $stop; e = ONE; if (e != 1) $stop; if (e != ONE) $stop; e = enum_t'(ONE); if (e != ONE) $stop; e = enum_t'(16'h1); if (e != ONE) $stop; pdata_reg.data = 1; e = enum_t'(pdata_reg); if (e != ONE) $stop; es = {ONE, ONE, ONE, ONE}; for (i = 0; i < 4; i++) if (es[i] != ONE) $stop; es = enums_t'(64'h0001_0001_0001_0001); for (i = 0; i < 4; i++) if (es[i] != ONE) $stop; o = tocast_t'(4'b1); if (o != 4'b1) $stop; the_intf.octets = 16'd1; pdata_reg = packed_t'(the_intf.octets); if (pdata_reg.data != 16'd1) $stop; the_intf.words = 32'd1; pdata2_reg = packed2_t'(the_intf.words); if (pdata2_reg.data != 32'd1) $stop; if (15'h6cec != outa) $stop; if (27'h7ffecec != mida) $stop; if (27'h7ffecec != midb) $stop; if (b33 != 33'b1) $stop; if (b32 != 32'b1) $stop; if (two_dee[0] != 8'hef) $stop; if (two_dee[1] != 8'hcd) $stop; if (two_dee[2] != 8'hab) $stop; thirty_two_bits = 32'h123456; two_dee_sig = two_dee_t'(thirty_two_bits); if (two_dee_sig[0] != 8'h56) $stop; if (two_dee_sig[1] != 8'h34) $stop; if (two_dee_sig[2] != 8'h12) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_alw_splitord.v0000644000542200017500000001103215101701376022300 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg [15:0] m_din; // OK reg [15:0] c_split_1, c_split_2, c_split_3, c_split_4, c_split_5; always @ (posedge clk) begin if (cyc==0) begin /*AUTORESET*/ // Beginning of autoreset for uninitialized flops c_split_1 <= 16'h0; c_split_2 <= 16'h0; c_split_3 <= 16'h0; c_split_4 <= 0; c_split_5 <= 0; // End of automatics end else begin c_split_1 <= m_din; c_split_2 <= c_split_1; c_split_3 <= c_split_2 & {16{(cyc!=0)}}; if (cyc==1) begin c_split_4 <= 16'h4; c_split_5 <= 16'h5; end else begin c_split_4 <= c_split_3; c_split_5 <= c_split_4; end end end // OK reg [15:0] d_split_1, d_split_2; always @ (posedge clk) begin if (cyc==0) begin /*AUTORESET*/ // Beginning of autoreset for uninitialized flops d_split_1 <= 16'h0; d_split_2 <= 16'h0; // End of automatics end else begin d_split_1 <= m_din; d_split_2 <= d_split_1; d_split_1 <= ~m_din; end end // Not OK always @ (posedge clk) begin if (cyc==0) begin /*AUTORESET*/ // Beginning of autoreset for uninitialized flops // End of automatics end else begin $write(" foo %x", m_din); $write(" bar %x\n", m_din); end end // Not OK reg [15:0] e_split_1, e_split_2; always @ (posedge clk) begin if (cyc==0) begin /*AUTORESET*/ // Beginning of autoreset for uninitialized flops e_split_1 = 16'h0; e_split_2 = 16'h0; // End of automatics end else begin e_split_1 = m_din; e_split_2 = e_split_1; end end // Not OK reg [15:0] f_split_1, f_split_2; always @ (posedge clk) begin if (cyc==0) begin /*AUTORESET*/ // Beginning of autoreset for uninitialized flops f_split_1 = 16'h0; f_split_2 = 16'h0; // End of automatics end else begin f_split_2 = f_split_1; f_split_1 = m_din; end end always @ (posedge clk) begin if (cyc!=0) begin //$write(" C %d %x %x\n", cyc, c_split_1, c_split_2); cyc<=cyc+1; if (cyc==1) begin m_din <= 16'hfeed; end if (cyc==3) begin end if (cyc==4) begin m_din <= 16'he11e; if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop; if (!(e_split_1==16'hfeed && e_split_2==16'hfeed)) $stop; if (!(f_split_1==16'hfeed && f_split_2==16'hfeed)) $stop; end if (cyc==5) begin m_din <= 16'he22e; if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop; // Two valid orderings, as we don't know which posedge clk gets evaled first if (!(e_split_1==16'hfeed && e_split_2==16'hfeed) && !(e_split_1==16'he11e && e_split_2==16'he11e)) $stop; if (!(f_split_1==16'hfeed && f_split_2==16'hfeed) && !(f_split_1==16'he11e && f_split_2==16'hfeed)) $stop; end if (cyc==6) begin m_din <= 16'he33e; if (!(c_split_1==16'he11e && c_split_2==16'hfeed && c_split_3==16'hfeed)) $stop; if (!(d_split_1==16'h1ee1 && d_split_2==16'h0112)) $stop; // Two valid orderings, as we don't know which posedge clk gets evaled first if (!(e_split_1==16'he11e && e_split_2==16'he11e) && !(e_split_1==16'he22e && e_split_2==16'he22e)) $stop; if (!(f_split_1==16'he11e && f_split_2==16'hfeed) && !(f_split_1==16'he22e && f_split_2==16'he11e)) $stop; end if (cyc==7) begin m_din <= 16'he44e; if (!(c_split_1==16'he22e && c_split_2==16'he11e && c_split_3==16'hfeed)) $stop; end if (cyc==8) begin m_din <= 16'he55e; if (!(c_split_1==16'he33e && c_split_2==16'he22e && c_split_3==16'he11e && c_split_4==16'hfeed && c_split_5==16'hfeed)) $stop; end if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.042/test_regress/t/t_inside_assoc_unsup.out0000644000542200017500000000056715101701376024047 0ustar mahmoudyfreeshell%Error: t/t_inside_assoc_unsup.v:12:15: Inside operator not specified on associative arrays (IEEE 1800-2023 11.4.13) : ... note: In instance 't' 12 | m = (10 inside {assoc}); | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_compiler_include_dpi_split.py0000755000542200017500000000135515101701376025356 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_compiler_include_dpi.v" test.compile(v_flags2=["t/t_compiler_include_dpi.cpp"], verilator_flags2=[ "-Wall -Wno-DECLFILENAME --compiler-include", test.t_dir + "/t_compiler_include_dpi.h", "--output-split 1" ]) test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_iface.v0000644000542200017500000000340515101701376022027 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface counter_if; logic valid; logic [3:0] value; logic reset; modport counter_mp (input reset, output valid, output value); modport core_mp (output reset, input valid, input value); endinterface interface counter_if2 (counter_if.counter_mp c_mp); task automatic reset(); c_mp.valid = '0; c_mp.value = '0; endtask task automatic init(); c_mp.valid = '0; c_mp.value = '1; endtask endinterface interface counter_if3 (counter_if.counter_mp c_mp); task automatic reset(); c_mp.valid = '0; c_mp.value = '0; endtask task automatic init(); c_mp.valid = '1; c_mp.value = 4'ha; endtask endinterface module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=1; counter_if c5_data(); counter_if c6_data(); counter_if2 cif2(c5_data.counter_mp); counter_if3 cif3(c6_data.counter_mp); initial begin cif2.reset(); cif3.reset(); end always @ (posedge clk) begin cyc <= cyc + 1; if (cyc<2) begin if (c5_data.valid != '0) $stop; if (c5_data.value != '0) $stop; if (c6_data.valid != '0) $stop; if (c6_data.value != '0) $stop; end if (cyc==2) begin cif2.init(); cif3.init(); end if (cyc==20) begin if (c5_data.valid != '0) $stop; if (c5_data.value != '1) $stop; if (c6_data.valid != '1) $stop; if (c6_data.value != 10) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_concat_casts.py0000755000542200017500000000073415101701376022436 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios("simulator") test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_alw_dly.v0000644000542200017500000000320215101701376021230 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg posedge_wr_clocks; reg prev_wr_clocks; reg [31:0] m_din; reg [31:0] m_dout; always @(negedge clk) begin prev_wr_clocks = 0; end reg comb_pos_1; reg comb_prev_1; always @ (/*AS*/clk or posedge_wr_clocks or prev_wr_clocks) begin comb_pos_1 = (clk &~ prev_wr_clocks); comb_prev_1 = comb_pos_1 | posedge_wr_clocks; comb_pos_1 = 1'b1; end always @ (posedge clk) begin posedge_wr_clocks = (clk &~ prev_wr_clocks); //surefire lint_off_line SEQASS prev_wr_clocks = prev_wr_clocks | posedge_wr_clocks; //surefire lint_off_line SEQASS if (posedge_wr_clocks) begin //$write("[%0t] Wrclk\n", $time); m_dout <= m_din; end end always @ (posedge clk) begin if (cyc!=0) begin cyc<=cyc+1; if (cyc==1) begin $write(" %x\n",comb_pos_1); m_din <= 32'hfeed; end if (cyc==2) begin $write(" %x\n",comb_pos_1); m_din <= 32'he11e; end if (cyc==3) begin m_din <= 32'he22e; $write(" %x\n",comb_pos_1); if (m_dout!=32'hfeed) $stop; end if (cyc==4) begin if (m_dout!=32'he11e) $stop; $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.042/test_regress/t/t_typename_min.v0000644000542200017500000000203015101701376022260 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t; int unsigned array[3] = {1, 2, 3}; int unsigned queue[$] = '{1, 2, 3}; int unsigned q[$]; int unsigned assoc[string] = '{"1":1, "2":2, "3":3}; string s; initial begin s = $typename(array.min); `checks(s, "int$[$]"); s = $sformatf("%p", array.min); `checks(s, "'{'h1}"); s = $typename(queue.min); `checks(s, "int$[$]"); s = $sformatf("%p", queue.min); `checks(s, "'{'h1}"); s = $typename(assoc.min); `checks(s, "int$[$]"); s = $sformatf("%p", assoc.min); `checks(s, "'{'h1}"); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_class_extends_bad.v0000644000542200017500000000050215101701376023242 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Base1; endclass class Base2; endclass class Cls extends Base1, Base2; endclass module t; endmodule verilator-5.042/test_regress/t/t_unpacked_array_p_fmt.v0000644000542200017500000000076715101701376023767 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; reg arr [15:0]; reg mat [3:0] [3:0]; initial begin for (int i = 0; i < 16; i++) begin arr[i] = ^i; mat[i/4][i%4] = ^i; end $display("%%p=%p", arr); $display("%%p=%p", mat); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_package_export.v0000644000542200017500000000255215101701376022600 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 // See issue #591 package pkg1; parameter PARAM2 = 16; parameter PARAM3 = 16; endpackage : pkg1 package pkg10; import pkg1::*; import pkg1::*; // Ignore if already `ifdef T_PACKAGE_EXPORT export *::*; // Not supported on all simulators `endif parameter PARAM1 = 8; endpackage package pkg11; import pkg10::*; endpackage package pkg20; import pkg1::*; `ifdef T_PACKAGE_EXPORT export pkg1::*; `endif parameter PARAM1 = 8; endpackage package pkg21; import pkg20::*; endpackage package pkg30; import pkg1::*; `ifdef T_PACKAGE_EXPORT export pkg1::PARAM2; export pkg1::PARAM3; `endif `ifdef T_PACKAGE_EXPORT_BAD export pkg1::BAD_DOES_NOT_EXIST; `endif parameter PARAM1 = 8; endpackage package pkg31; import pkg30::*; endpackage module t; reg [pkg11::PARAM1 : 0] bus11; reg [pkg11::PARAM2 : 0] bus12; reg [pkg11::PARAM3 : 0] bus13; reg [pkg21::PARAM1 : 0] bus21; reg [pkg21::PARAM2 : 0] bus22; reg [pkg21::PARAM3 : 0] bus23; reg [pkg31::PARAM1 : 0] bus31; reg [pkg31::PARAM2 : 0] bus32; reg [pkg31::PARAM3 : 0] bus33; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_math_sign_extend.v0000644000542200017500000001100315101701376023113 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This test demonstrates an issue with sign extension. // Assigning to localparms larger than 32 bits broke in 3.862 // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Mike Thyer. // SPDX-License-Identifier: CC0-1.0 module t; localparam [ 0:0] one1_lp = 1; localparam [ 1:0] one2_lp = 1; localparam [ 2:0] one3_lp = 1; localparam [ 3:0] one4_lp = 1; localparam [ 4:0] one5_lp = 1; localparam [ 5:0] one6_lp = 1; localparam [ 6:0] one7_lp = 1; localparam [ 7:0] one8_lp = 1; localparam [ 8:0] one9_lp = 1; localparam [ 9:0] one10_lp = 1; localparam [19:0] one20_lp = 1; localparam [29:0] one30_lp = 1; localparam [30:0] one31_lp = 1; localparam [31:0] one32_lp = 1; localparam [32:0] one33_lp = 1; localparam [33:0] one34_lp = 1; localparam [34:0] one35_lp = 1; localparam [35:0] one36_lp = 1; localparam [36:0] one37_lp = 1; localparam [37:0] one38_lp = 1; localparam [38:0] one39_lp = 1; localparam [39:0] one40_lp = 1; localparam [49:0] one50_lp = 1; localparam [59:0] one60_lp = 1; localparam [60:0] one61_lp = 1; localparam [61:0] one62_lp = 1; localparam [62:0] one63_lp = 1; localparam [63:0] one64_lp = 1; localparam [64:0] one65_lp = 1; localparam [65:0] one66_lp = 1; localparam [66:0] one67_lp = 1; localparam [67:0] one68_lp = 1; localparam [68:0] one69_lp = 1; localparam [69:0] one70_lp = 1; bit all_ok = 1; initial begin `ifdef TEST_VERBOSE $display("one1_lp : %x %d", one1_lp, one1_lp==1); $display("one2_lp : %x %d", one2_lp, one2_lp==1); $display("one3_lp : %x %d", one3_lp, one3_lp==1); $display("one4_lp : %x %d", one4_lp, one4_lp==1); $display("one5_lp : %x %d", one5_lp, one5_lp==1); $display("one6_lp : %x %d", one6_lp, one6_lp==1); $display("one7_lp : %x %d", one7_lp, one7_lp==1); $display("one8_lp : %x %d", one8_lp, one8_lp==1); $display("one9_lp : %x %d", one9_lp, one9_lp==1); $display("one10_lp: %x %d", one10_lp, one10_lp==1); $display("one20_lp: %x %d", one20_lp, one20_lp==1); $display("one30_lp: %x %d", one30_lp, one30_lp==1); $display("one31_lp: %x %d", one31_lp, one31_lp==1); $display("one32_lp: %x %d", one32_lp, one32_lp==1); $display("one33_lp: %x %d", one33_lp, one33_lp==1); $display("one34_lp: %x %d", one34_lp, one34_lp==1); $display("one35_lp: %x %d", one35_lp, one35_lp==1); $display("one36_lp: %x %d", one36_lp, one36_lp==1); $display("one37_lp: %x %d", one37_lp, one37_lp==1); $display("one38_lp: %x %d", one38_lp, one38_lp==1); $display("one39_lp: %x %d", one39_lp, one39_lp==1); $display("one40_lp: %x %d", one40_lp, one40_lp==1); $display("one50_lp: %x %d", one50_lp, one50_lp==1); $display("one60_lp: %x %d", one60_lp, one60_lp==1); $display("one61_lp: %x %d", one61_lp, one61_lp==1); $display("one62_lp: %x %d", one62_lp, one62_lp==1); $display("one63_lp: %x %d", one63_lp, one63_lp==1); $display("one64_lp: %x %d", one64_lp, one64_lp==1); $display("one65_lp: %x %d", one65_lp, one65_lp==1); $display("one66_lp: %x %d", one66_lp, one66_lp==1); $display("one67_lp: %x %d", one67_lp, one67_lp==1); $display("one68_lp: %x %d", one68_lp, one68_lp==1); $display("one69_lp: %x %d", one69_lp, one69_lp==1); $display("one70_lp: %x %d", one70_lp, one70_lp==1); `endif all_ok &= one1_lp == 1; all_ok &= one2_lp == 1; all_ok &= one3_lp == 1; all_ok &= one4_lp == 1; all_ok &= one5_lp == 1; all_ok &= one6_lp == 1; all_ok &= one7_lp == 1; all_ok &= one8_lp == 1; all_ok &= one9_lp == 1; all_ok &= one10_lp == 1; all_ok &= one20_lp == 1; all_ok &= one30_lp == 1; all_ok &= one31_lp == 1; all_ok &= one32_lp == 1; all_ok &= one33_lp == 1; all_ok &= one34_lp == 1; all_ok &= one35_lp == 1; all_ok &= one36_lp == 1; all_ok &= one37_lp == 1; all_ok &= one38_lp == 1; all_ok &= one39_lp == 1; all_ok &= one40_lp == 1; all_ok &= one50_lp == 1; all_ok &= one60_lp == 1; all_ok &= one61_lp == 1; all_ok &= one62_lp == 1; all_ok &= one63_lp == 1; all_ok &= one64_lp == 1; all_ok &= one65_lp == 1; all_ok &= one66_lp == 1; all_ok &= one67_lp == 1; all_ok &= one68_lp == 1; all_ok &= one69_lp == 1; all_ok &= one70_lp == 1; if (!all_ok) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_profcfunc.out0000644000542200017500000001140015101701376022123 0ustar mahmoudyfreeshellOverall summary by type: % time type 4.37 C++ 33.48 Common code under Vt_prof 15.82 VLib 6.46 Verilog Blocks under Vt_prof 39.87 Unaccounted for/rounding error Overall summary by design: % time design 4.37 C++ 15.82 VLib 39.94 Vt_prof 39.87 Unaccounted for/rounding error Overall summary by module: % time module 4.37 C++ 15.82 VLib 33.48 Vt_prof common code 6.46 t_prof 39.87 Unaccounted for/rounding error Verilog code profile: These are split into three categories: C++: Time in non-Verilated C++ code Prof: Time in profile overhead VBlock: Time attributable to a block in a Verilog file and line VCommon: Time in a Verilated module, due to all parts of the design VLib: Time in Verilated common libraries, called by the Verilated code % cumulative self time seconds seconds calls design type filename and line number 3.27 1.27 1.27 200 Vt_prof VBlock t_prof:31 1.99 2.26 0.99 200578 - VLib VL_EXTENDS_QQ(int, int, unsigned long) 1.98 3.24 0.98 100000 - VLib VL_POWSS_QQQ(int, int, int, unsigned long, unsigned long, bool, bool) 1.89 4.13 0.89 1407 - VLib Verilated::debug() 1.88 5.01 0.88 202 - VLib VerilatedContext::gotFinish() const 1.87 5.88 0.87 6 - VLib VerilatedContext::randReset() 1.86 6.74 0.86 9 - C++ VlWide<2ul>::operator unsigned int*() 1.79 7.53 0.79 600 Vt_prof VCommon Vt_prof* const& std::__get_helper<0ul, Vt_prof*, std::default_delete >(std::_Tuple_impl<0ul, Vt_prof*, std::default_delete > const&) 1.78 8.31 0.78 3 Vt_prof VCommon Vt_prof*& std::__get_helper<0ul, Vt_prof*, std::default_delete >(std::_Tuple_impl<0ul, Vt_prof*, std::default_delete >&) 1.77 9.08 0.77 1 Vt_prof VCommon Vt_prof::Vt_prof(VerilatedContext*, char const*) 1.76 9.84 0.76 1 Vt_prof VCommon Vt_prof::Vt_prof(char const*) 1.75 10.59 0.75 200 Vt_prof VCommon Vt_prof::eval() 1.74 11.33 0.74 200 Vt_prof VCommon Vt_prof::eval_step() 1.73 12.06 0.73 1 Vt_prof VCommon Vt_prof::final() 1.72 12.78 0.72 1 Vt_prof VCommon Vt_prof::~Vt_prof() 1.71 13.49 0.71 1 Vt_prof VCommon Vt_prof__Syms::Vt_prof__Syms(VerilatedContext*, char const*, Vt_prof*) 1.70 14.19 0.70 1 Vt_prof VCommon Vt_prof__Syms::~Vt_prof__Syms() 1.69 14.88 0.69 1 Vt_prof VCommon Vt_prof___024root::__Vconfigure(Vt_prof__Syms*, bool) 1.68 15.56 0.68 1 Vt_prof VCommon Vt_prof___024root::Vt_prof___024root(char const*) 1.67 16.23 0.67 1 Vt_prof VCommon Vt_prof___024root::~Vt_prof___024root() 1.66 16.89 0.66 201 Vt_prof VCommon Vt_prof___024root___eval(Vt_prof___024root*) 1.65 17.54 0.65 200 Vt_prof VCommon Vt_prof___024root___eval_debug_assertions(Vt_prof___024root*) 1.62 18.16 0.62 100 Vt_prof VBlock t_prof:30 1.61 18.77 0.61 1 Vt_prof VCommon Vt_prof___024root___final(Vt_prof___024root*) 1.60 19.37 0.60 1 Vt_prof VCommon Vt_prof___024root___eval_settle(Vt_prof___024root*) 1.59 19.96 0.59 1 Vt_prof VCommon Vt_prof___024root___eval_initial(Vt_prof___024root*) 1.58 20.54 0.58 1 Vt_prof VCommon Vt_prof___024root___ctor_var_reset(Vt_prof___024root*) 1.57 21.11 0.57 1 Vt_prof VBlock t_prof:13 1.30 21.41 0.30 1 Vt_prof VCommon _eval_initial_loop(Vt_prof__Syms*) 1.29 21.70 0.29 1 - VLib _vl_cmp_w(int, unsigned int const*, unsigned int const*) 1.28 21.98 0.28 2 - VLib _vl_moddiv_w(int, unsigned int*, unsigned int const*, unsigned int const*, bool) 1.27 22.25 0.27 2 - VLib _vl_vsformat(std::__cxx11::basic_string, std::allocator >&, char const*, __va_list_tag*) 1.26 22.51 0.26 1399 - C++ std::unique_ptr >::get() const 1.25 22.76 0.25 3 - C++ unsigned long const& std::max(unsigned long const&, unsigned long const&) 1.19 22.95 0.19 1 - VLib vl_finish(char const*, int, char const*) 1.18 23.13 0.18 2 - VLib vl_time_pow10(int) verilator-5.042/test_regress/t/t_disable_iff_multi_bad.v0000644000542200017500000000054015101701376024046 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs rstn ); input rstn; default disable iff (!rstn); default disable iff (!rstn); endmodule verilator-5.042/test_regress/t/t_dpi_open_oob_bad.v0000644000542200017500000000222615101701376023044 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; import "DPI-C" function void dpii_nullptr(); // verilator lint_off UNDRIVEN int i_int_u3 [2:-2] [-3:3] [4:-4]; import "DPI-C" function void dpii_int_u3(input int i [] [] []); real i_real_u1 [1:0]; import "DPI-C" function void dpii_real_u1(input real i []); bit i_u6 [2][2][2][2][2][2]; import "DPI-C" function void dpii_bit_u6(input bit i [][][][][][]); real i_real_u6 [2][2][2][2][2][2]; import "DPI-C" function void dpii_real_u6(input real i [][][][][][]); initial begin i_int_u3[0][0][0] = 32'hbad; i_real_u1[0] = 1.1; i_u6[0][0][0][0][0][0] = 1'b1; dpii_nullptr(); dpii_int_u3(i_int_u3); dpii_real_u1(i_real_u1); dpii_bit_u6(i_u6); dpii_real_u6(i_real_u6); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_debug_inputs_b.v0000644000542200017500000000044315101701376022572 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Dotted reference that uses another dotted reference // as the select expression // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t_debug_inputs_b; endmodule verilator-5.042/test_regress/t/t_class_param_enum.py0000755000542200017500000000073415101701376023303 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_final.py0000755000542200017500000000073415101701376021063 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_copy.v0000644000542200017500000000155115101701376021741 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls; int imembera; function int inc_methoda; imembera += 1; return imembera; endfunction endclass module t; initial begin Cls c1; Cls c2; Cls c3; c1 = new; c1.imembera = 10; if (c1.inc_methoda() != 11) $stop; // Assignment c2 = c1; if (c1.inc_methoda() != 12) $stop; if (c2.inc_methoda() != 13) $stop; if (c1.inc_methoda() != 14) $stop; // Shallow copy c3 = new c1; if (c1.inc_methoda() != 15) $stop; if (c3.inc_methoda() != 15) $stop; if (c1.inc_methoda() != 16) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_inst_tree_inl0_pub1.py0000755000542200017500000000421215101701376023632 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_inst_tree.v" default_vltmt_threads = test.get_default_vltmt_threads test.compile( verilator_flags2=['--stats', test.t_dir + "/" + test.name + ".vlt"], # Force 3 threads even if we have fewer cores threads=(default_vltmt_threads if test.vltmt else 1)) def check_relative_refs(mod, expect_relative): found_relative = False for filename in test.glob_some(test.obj_dir + "/V" + test.name + "_" + mod + "*.cpp"): if test.verbose: print("FILE " + filename) text = test.file_contents(filename) if re.search(r'this->', text) or re.search(r'vlSelf->', text): if test.verbose: print(" REL " + filename) found_relative = True if found_relative != expect_relative: test.error(filename + " " + ("has 'relative'" if found_relative else "has 'non-relative'") + " variable references but expected " + ("'relative'" if expect_relative else "'non-relative'")) if test.vlt_all: # We expect to combine sequent functions across multiple instances of # l2, l3, l4, l5. If this number drops, please confirm this has not broken. test.file_grep(test.stats, r'Optimizations, Combined CFuncs\s+(\d+)', (99 if test.vltmt else 82)) # Everything should use relative references check_relative_refs("t", True) check_relative_refs("l1", True) check_relative_refs("l2", True) check_relative_refs("l3", True) check_relative_refs("l4", True) check_relative_refs("l5__P1", True) check_relative_refs("l5__P2", True) test.execute() test.file_grep(test.run_log_filename, r"\] (%m|.*t\.ps): Clocked") test.passes() verilator-5.042/test_regress/t/t_sys_file_basic_input.dat0000644000542200017500000000026215101701376024300 0ustar mahmoudyfreeshellhi lquad widestuff string *xa=1f xb=237904689_02348923 *ba=10 bb=11010010101001010101 note_the_two *oa=23 ob=12563 *d=-236123 *u=-236124 *fredfishblah aBCD not_included 12346789 verilator-5.042/test_regress/t/t_display_recurse.out0000644000542200017500000000030515101701376023335 0ustar mahmoudyfreeshell 0: 0000dead 4: 0001dead 8: 0002dead 12: 0003dead 16: 0004dead 20: 0005dead 24: 0006dead 28: 0007dead *-* All Finished *-* verilator-5.042/test_regress/t/t_disable.py0000755000542200017500000000106515101701376021373 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=['--lint-only --timing'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_expect.out0000644000542200017500000000211215101701376021426 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_expect.v:19:32: Unsupported: ## (in sequence expression) 19 | expect (@(posedge clk) a ##1 b) a = 110; | ^~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_expect.v:19:7: Unsupported: expect 19 | expect (@(posedge clk) a ##1 b) a = 110; | ^~~~~~ %Error-UNSUPPORTED: t/t_expect.v:21:32: Unsupported: ## (in sequence expression) 21 | expect (@(posedge clk) a ##1 b) else a = 299; | ^~ %Error-UNSUPPORTED: t/t_expect.v:21:7: Unsupported: expect 21 | expect (@(posedge clk) a ##1 b) else a = 299; | ^~~~~~ %Error-UNSUPPORTED: t/t_expect.v:23:32: Unsupported: ## (in sequence expression) 23 | expect (@(posedge clk) a ##1 b) a = 300; else a = 399; | ^~ %Error-UNSUPPORTED: t/t_expect.v:23:7: Unsupported: expect 23 | expect (@(posedge clk) a ##1 b) a = 300; else a = 399; | ^~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_runflag_errorlimit_fatal_bad.out0000644000542200017500000000050515101701376026025 0ustar mahmoudyfreeshell[0] %Error: t_runflag_errorlimit_fatal_bad.v:9: Assertion failed in top.t: One -Info: t/t_runflag_errorlimit_fatal_bad.v:9: Verilog $stop, ignored due to +verilator+error+limit [0] %Fatal: t_runflag_errorlimit_fatal_bad.v:10: Assertion failed in top.t %Error: t/t_runflag_errorlimit_fatal_bad.v:10: Verilog $stop Aborting... verilator-5.042/test_regress/t/t_assert_ctl_arg.py0000755000542200017500000000153515101701376022766 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile( make_top_shell=False, make_main=False, verilator_flags2=["--assert", "--timing", "--coverage-user", "--exe", test.pli_filename], nc_flags2=["+nccovoverwrite", "+nccoverage+all", "+nccovtest+" + test.name]) test.execute(all_run_flags=["+verilator+error+limit+100"], expect_filename=test.golden_filename) test.files_identical(test.coverage_filename, test.t_dir + "/t_assert_ctl_arg.dat.out") test.passes() verilator-5.042/test_regress/t/t_func_ref_noparen.v0000644000542200017500000000057515101701376023120 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class c; function bit f(); return 1'b0; endfunction endclass module t; c cinst; initial begin cinst = new(); if (cinst.f) begin end end endmodule verilator-5.042/test_regress/t/t_inst_wideconst.py0000755000542200017500000000077015101701376023026 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['-public']) test.execute() test.passes() verilator-5.042/test_regress/t/t_display_wide.v0000644000542200017500000000601415101701376022256 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [4095:0] crc; // Test loop always @ (posedge clk) begin cyc <= cyc + 1; crc <= {crc[4094:0], crc[63] ^ crc[2] ^ crc[0]}; // not a good crc :) if (cyc==0) begin // Setup crc <= 4096'h9f51804b5275c7b6ab9907144a58649bb778f9718062fa5c336fcc9edcad7cf17aad0a656244017bb21d9f97f7c0c147b6fa7488bb9d5bb8d3635b20fba1deab597121c502b21f49b18da998852d29a6b2b649315a3323a31e7e5f41e9bbb7e44046467438f37694857b963250bdb137a922cfce2af1defd1f93db5aa167f316d751bb274bda96fdee5e2c6eb21886633246b165341f0594c27697b06b62b1ad05ebe3c08909a54272de651296dcdd3d1774fc432d22210d8f6afa50b02cf23336f8cc3a0a2ebfd1a3a60366a1b66ef346e0379116d68caa01279ac2772d1f3cd76d2cbbc68ada6f83ec2441b2679b405486df8aa734ea1729b40c3f82210e8e42823eb3fd6ca77ee19f285741c4e8bac1ab7855c3138e84b6da1d897bbe37faf2d0256ad2f7ff9e704a63d824c1e97bddce990cae1578f9537ae2328d0afd69ffb317cbcf859696736e45e5c628b44727557c535a7d02c07907f2dccd6a21ca9ae9e1dbb1a135a8ebc2e0aa8c7329b898d02896273defe21beaa348e11165b71c48cf1c09714942a5a2ddc2adcb6e42c0f630117ee21205677d5128e8efc18c9a6f82a8475541fd722cca2dd829b7e78fef89dbeab63ab7b849910eb4fe675656c4b42b9452c81a4ca6296190a81dc63e6adfaa31995d7dfe3438ee9df66488d6cf569380569ffe6e5ea313d23af6ff08d979af29374ee9aff1fa143df238a1; end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x%x%x%x\n", $time, cyc, crc[4095:3072], crc[2071:2048], crc[2047:1024], crc[1023:0]); $write("[%0t] cyc==%0d crc=%b%b%b%b\n", $time, cyc, crc[4095:3072], crc[2071:2048], crc[2047:1024], crc[1023:0]); //Unsupported: $write("[%0t] cyc==%0d crc=%x\n", $time, cyc, crc); if (crc != 4096'h2961926edde3e5c6018be970cdbf327b72b5f3c5eab42995891005eec8767e5fdf03051edbe9d222ee756ee34d8d6c83ee877aad65c487140ac87d26c636a66214b4a69acad924c568cc8e8c79f97d07a6eedf91011919d0e3cdda5215ee58c942f6c4dea48b3f38abc77bf47e4f6d6a859fcc5b5d46ec9d2f6a5bf7b978b1bac862198cc91ac594d07c165309da5ec1ad8ac6b417af8f0224269509cb79944a5b7374f45dd3f10cb48884363dabe942c0b3c8ccdbe330e828baff468e980d9a86d9bbcd1b80de445b5a32a8049e6b09dcb47cf35db4b2ef1a2b69be0fb09106c99e6d01521b7e2a9cd3a85ca6d030fe08843a390a08facff5b29dfb867ca15d0713a2eb06ade1570c4e3a12db687625eef8dfebcb4095ab4bdffe79c1298f609307a5ef773a6432b855e3e54deb88ca342bf5a7fecc5f2f3e165a59cdb9179718a2d11c9d55f14d69f40b01e41fcb7335a8872a6ba7876ec684d6a3af0b82aa31cca6e26340a2589cf7bf886faa8d23844596dc71233c7025c5250a968b770ab72db90b03d8c045fb8848159df544a3a3bf063269be0aa11d5507f5c8b328b760a6df9e3fbe276faad8eadee126443ad3f99d595b12d0ae514b20693298a58642a07718f9ab7ea8c66575f7f8d0e3ba77d992235b3d5a4e015a7ff9b97a8c4f48ebdbfc2365e6bca4dd3ba6bfc7e850f7c8e2842c717a1d85a977a033f564fc ) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_cover_toggle.out0000644000542200017500000002070315101701376022623 0ustar mahmoudyfreeshell// // verilator_coverage annotation // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef struct packed {logic a;} str_logic; module t (/*AUTOARG*/ // Inputs clk, check_real, check_array_real, check_string ); ~000010 input clk; input real check_real; // Check issue #2741 input real check_array_real [1:0]; input string check_string; // Check issue #2766 typedef struct packed { union packed { logic ua; logic ub; } u; logic b; } str_t; %000001 reg toggle; initial toggle='0; logic _under_toggle = toggle; // For --coverage-underscore %000001 str_t stoggle; initial stoggle='0; ~000010 str_logic strl; initial strl='0; union { real val1; // TODO use bit [7:0] here real val2; // TODO use bit [3:0] here } utoggle; const reg aconst = '0; %000001 reg [1:0][1:0] ptoggle; initial ptoggle=0; integer cyc; initial cyc=1; %000006 wire [7:0] cyc_copy = cyc[7:0]; %000001 wire toggle_up; typedef struct { int q[$]; } str_queue_t; str_queue_t str_queue; typedef struct packed { // verilator lint_off ASCRANGE bit [3:5] x; // verilator lint_on ASCRANGE bit [0:0] y; } str_bit_t; %000001 str_bit_t str_bit; %000001 str_bit_t [5:2] str_bit_arr; assign strl.a = clk; alpha a1 (/*AUTOINST*/ // Outputs .toggle_up (toggle_up), // Inputs .clk (clk), .toggle (toggle), .cyc_copy (cyc_copy[7:0])); alpha a2 (/*AUTOINST*/ // Outputs .toggle_up (toggle_up), // Inputs .clk (clk), .toggle (toggle), .cyc_copy (cyc_copy[7:0])); beta b1 (/*AUTOINST*/ // Inputs .clk (clk), .toggle_up (toggle_up)); off o1 (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle)); param#(1) p1 (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle)); param#() p2 (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle)); mod_struct i_mod_struct (/*AUTOINST*/ // Inputs .input_struct (strl)); %000001 reg [1:0] memory[121:110]; wire [1023:0] largeish = {992'h0, cyc}; // CHECK_COVER_MISSING(-1) always @ (posedge clk) begin if (cyc != 0) begin cyc <= cyc + 1; memory[cyc + 'd100] <= memory[cyc + 'd100] + 2'b1; toggle <= '0; stoggle.u <= toggle; stoggle.b <= toggle; utoggle.val1 <= real'(cyc[7:0]); ptoggle[0][0] <= toggle; if (cyc == 3) begin str_queue.q.push_back(1); toggle <= '1; str_bit.x <= '1; str_bit.y <= '1; str_bit_arr[4].x <= '1; end if (cyc == 4) begin if (str_queue.q.size() != 1) $stop; toggle <= '0; str_bit.x[3] <= 0; str_bit.y[0] <= 0; str_bit_arr[4].x[3] <= 0; end else if (cyc == 10) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module alpha (/*AUTOARG*/ // Outputs toggle_up, // Inputs clk, toggle, cyc_copy ); // t.a1 and t.a2 collapse to a count of 2 000020 input clk; %000002 input toggle; // CHECK_COVER(-1,"top.t.a*","toggle:0->1",2) // CHECK_COVER(-2,"top.t.a*","toggle:1->0",2) // (t.a1 and t.a2) ~000012 input [7:0] cyc_copy; // CHECK_COVER(-1,"top.t.a*","cyc_copy[0]:0->1",12) // CHECK_COVER(-2,"top.t.a*","cyc_copy[0]:1->0",10) // CHECK_COVER(-3,"top.t.a*","cyc_copy[1]:0->1",6) // CHECK_COVER(-4,"top.t.a*","cyc_copy[1]:1->0",4) // CHECK_COVER(-5,"top.t.a*","cyc_copy[2]:0->1",2) // CHECK_COVER(-6,"top.t.a*","cyc_copy[2]:1->0",2) // CHECK_COVER(-7,"top.t.a*","cyc_copy[3]:0->1",2) // CHECK_COVER(-8,"top.t.a*","cyc_copy[3]:1->0",0) // CHECK_COVER(-9,"top.t.a*","cyc_copy[4]:0->1",0) // CHECK_COVER(-10,"top.t.a*","cyc_copy[4]:1->0",0) // CHECK_COVER(-11,"top.t.a*","cyc_copy[5]:0->1",0) // CHECK_COVER(-12,"top.t.a*","cyc_copy[5]:1->0",0) // CHECK_COVER(-13,"top.t.a*","cyc_copy[6]:0->1",0) // CHECK_COVER(-14,"top.t.a*","cyc_copy[6]:1->0",0) // CHECK_COVER(-15,"top.t.a*","cyc_copy[7]:0->1",0) // CHECK_COVER(-16,"top.t.a*","cyc_copy[7]:1->0",0) %000002 reg toggle_internal; // CHECK_COVER(-1,"top.t.a*","toggle_internal:0->1",2) // CHECK_COVER(-2,"top.t.a*","toggle_internal:1->0",2) // (t.a1 and t.a2) %000002 output reg toggle_up; // CHECK_COVER(-1,"top.t.a*","toggle_up:0->1",2) // CHECK_COVER(-2,"top.t.a*","toggle_up:1->0",2) // (t.a1 and t.a2) always @ (posedge clk) begin toggle_internal <= toggle; toggle_up <= toggle; end endmodule module beta (/*AUTOARG*/ // Inputs clk, toggle_up ); ~000010 input clk; %000001 input toggle_up; // CHECK_COVER(-1,"top.t.b1","toggle_up:0->1",1) // CHECK_COVER(-2,"top.t.b1","toggle_up:1->0",1) /* verilator public_module */ always @ (posedge clk) begin if (0 && toggle_up) begin end end endmodule module off (/*AUTOARG*/ // Inputs clk, toggle ); // verilator coverage_off input clk; // CHECK_COVER_MISSING(-1) // verilator coverage_on %000001 input toggle; // CHECK_COVER(-1,"top.t.o1","toggle:0->1",1) // CHECK_COVER(-2,"top.t.o1","toggle:1->0",1) endmodule module param #(parameter P = 2) (/*AUTOARG*/ // Inputs clk, toggle ); ~000010 input clk; %000001 input toggle; %000001 logic z; for (genvar i = 0; i < P; i++) begin %000001 logic x; always @ (posedge clk) begin x <= toggle; end for (genvar j = 0; j < 3; j++) begin %000002 logic [2:0] y; always @ (negedge clk) begin y <= {toggle, ~toggle, 1'b1}; end end end if (P > 1) begin : gen_1 assign z = 1; end endmodule module mod_struct(/*AUTOARG*/ // Inputs input_struct ); ~000010 input str_logic input_struct; endmodule verilator-5.042/test_regress/t/t_process_propagation.py0000755000542200017500000000077115101701376024054 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_stmt_incr_unsup.py0000755000542200017500000000076615101701376023233 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_preproc_ttempty.py0000755000542200017500000000154015101701376023226 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') stdout_filename = os.path.join(test.obj_dir, test.name + "__test.vpp") test.compile( # Override default flags v_flags=[''], verilator_flags=["-E -P +incdir+t -Mdir", test.obj_dir], verilator_flags2=[''], verilator_flags3=[''], verilator_make_gmake=False, make_top_shell=False, make_main=False, stdout_filename=stdout_filename) test.files_identical(stdout_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_preproc_noline.out0000644000542200017500000000010715101701376023156 0ustar mahmoudyfreeshellHello in t_preproc_psl.v yes Multi text multiline line Line: 21 verilator-5.042/test_regress/t/t_unoptflat_simple_3.v0000644000542200017500000000240415101701376023407 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Simple test of unoptflat // // Demonstration of an UNOPTFLAT combinatorial loop using 3 bits and looping // through 2 sub-modules. // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; wire [2:0] x; test1 test1i ( .clk (clk), .xvecin (x[1:0]), .xvecout (x[2:1])); test2 test2i ( .clk (clk), .xvecin (x[2:1]), .xvecout (x[1:0])); always @(posedge clk or negedge clk) begin `ifdef TEST_VERBOSE $write("x = %x\n", x); `endif if (x[1] != 0) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule // t module test1 (/*AUTOARG*/ // Inputs clk, xvecin, // Outputs xvecout ); input clk; input wire [1:0] xvecin; output wire [1:0] xvecout; assign xvecout = {xvecin[0], clk}; endmodule // test module test2 (/*AUTOARG*/ // Inputs clk, xvecin, // Outputs xvecout ); input clk; input wire [1:0] xvecin; output wire [1:0] xvecout; assign xvecout = {clk, xvecin[1]}; endmodule // test verilator-5.042/test_regress/t/t_past_strobe.py0000755000542200017500000000100015101701376022302 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_math_width.py0000755000542200017500000000073415101701376022122 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_new_typed.v0000644000542200017500000000113415101701376022762 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (); class SuperCls; int s = 2; function new(int def = 3); s = def; endfunction endclass class Cls extends SuperCls; function new(int def = 42); s = def; endfunction endclass SuperCls super_obj; initial begin super_obj = Cls::new; if (super_obj.s != 42) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_flag_only_bad2.out0000755000542200017500000000040115101701376023002 0ustar mahmoudyfreeshell%Error: The following cannot be used together: --build, -E, --dpi-hdr-only, --lint-only, --xml-only, --json-only. Suggest see manual ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_preproc.v0000644000542200017500000005273615101701376021267 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2000-2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // This file intentionally includes some tabs //=========================================================================== // Includes `include "t_preproc_inc2.vh" //=========================================================================== // Comments /* verilator pass_thru comment */ // verilator pass_thru_comment2 //=========================================================================== // Defines `define DEF_A3 `define DEF_A1 // DEF_A0 set by command line wire [3:0] q = { `ifdef DEF_A3 1'b1 `else 1'b0 `endif , `ifdef DEF_A2 1'b1 `else 1'b0 `endif , `ifdef DEF_A1 1'b1 `else 1'b0 `endif , `ifdef DEF_A0 1'b1 `else 1'b0 `endif }; text. `define FOOBAR foo /*this */ bar /* this too */ `define FOOBAR2 foobar2 // but not `FOOBAR `FOOBAR2 `define MULTILINE first part \ second part \ third part `define MOREMULTILINE {\ a,\ b,\ c} /*******COMMENT*****/ `MULTILINE `MOREMULTILINE Line_Preproc_Check `__LINE__ //=========================================================================== `define syn_negedge_reset_l or negedge reset_l `define DEEP deep `define DEEPER `DEEP `DEEP `DEEPER `define nosubst NOT_SUBSTITUTED `define WITHTICK "`nosubst" "Inside: `nosubst" `WITHTICK `define withparam(a, b) a b LLZZ a b `withparam(x,y) `withparam(`withparam(p,q),`withparam ( r , s )) `withparam(firstline , comma","line) `define withquote(a, bar) a bar LLZZ "a" bar `withquote( x , y) // IEEE 1800-2023 clarified that "a" not to substitute `define noparam (a,b) `noparam(a,b) `define msg(x,y) `"x: `\`"y`\`"`" $display(`msg(left side, right side)) `define foo(f) f``_suffix `foo(bar) more `define with_space_before_suffix(f) f`` suffix_after_space `with_space_before_suffix(arg) `define zap(which) \ $c("Zap(\"",which,"\");"); `zap(bug1); `zap("bug2"); /* Define inside comment: `DEEPER and `WITHTICK */ // More commentary: `zap(bug1); `zap("bug2"); //====================================================================== // display passthru `define ls left_side `define rs right_side `define noarg na `define thru(x) x `define thruthru `ls `rs // Doesn't expand `define msg(x,y) `"x: `\`"y`\`"`" initial begin //$display(`msg( \`, \`)); // Illegal $display(`msg(pre `thru(thrupre `thru(thrumid) thrupost) post,right side)); $display(`msg(left side,right side)); $display(`msg( left side , right side )); $display(`msg( `ls , `rs )); $display(`msg( `noarg , `rs )); $display(`msg( prep ( midp1 `ls midp2 ( outp ) ) , `rs )); $display(`msg(`noarg,`noarg`noarg)); $display(`msg( `thruthru , `thruthru )); // Results vary between simulators $display(`msg(`thru(),)); // Empty $display(`msg(`thru(left side),`thru(right side))); $display(`msg( `thru( left side ) , `thru( right side ) )); $display(`"standalone`"); // Unspecified when the stringification has multiple lines `define twoline first \ second $display(`msg(twoline, `twoline)); //$display(`msg(left side, \ right side \ )); // Not sure \{space} is legal. $write("*-* All Finished *-*\n"); $finish; end endmodule //====================================================================== // rt.cpan.org bug34429 `define ADD_UP(a,c) \ wire tmp_``a = a; \ wire tmp_``c = tmp_``a + 1; \ assign c = tmp_``c ; module add1 ( input wire d1, output wire o1); `ADD_UP(d1,o1) // expansion is OK endmodule module add2 ( input wire d2, output wire o2); `ADD_UP( d2 , o2 ) // expansion is bad endmodule `define check(mod, width, flopname, gate, path) \ generate for (i=0; i<(width); i=i+1) begin \ psl cover { path.d[i] & ~path.q[i] & !path.cond & (gate)} report `"fondNoRise: mod.flopname`"; \ psl cover { ~path.d[i] & path.q[i] & !path.cond & (gate)} report `"fondNoFall: mod.flopname`"; \ end endgenerate // parameterized macro with arguments that are macros `define MK m5k.f `define MF `MK .ctl `define CK_fr (`MF.alive & `MF.alive_m1) `check(m5kc_fcl, 3, _ctl_mvldx_m1, `CK_fr, `MF._ctl_mvldx_m1) // ignorecmt //====================================================================== // Quotes are legal in protected blocks. Grr. module prot(); `protected I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl) #nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk] `endprotected endmodule //" //====================================================================== // Check IEEE 1800-2017 `pragma protect encrypted modules module t_lint_pragma_protected; `pragma protect begin_protected `pragma protect version=1 `pragma protect encrypt_agent="XXXXX" `pragma protect encrypt_agent_info="YYYYY" `pragma protect data_method="AES128-CBC" `pragma protect key_keyowner="BIG3#1" `pragma protect key_keyname="AAAAAA" `pragma protect key_method="RSA" `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `pragma protect key_block ICAgICAgICAgICAgICAgICAgIEdOVSBMRVNTRVIgR0VORVJBTCBQVUJMSUMgTElDRU5TRQogICAg KSAyMDA3IE== `pragma protect key_keyowner="BIG3#2" `pragma protect key_keyname="BBBBBB" `pragma protect key_method="RSA" `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `pragma protect key_block IEV2ZXJ5b25lIGlzIHBlcm1pdHRlZCB0byBjb3B5IGFuZCBkaXN0cmlidXRlIHZlcmJhdGltIGNv cGllcwogb2YgdGhpcyBsaWNlbnNlIGRvY3VtZW50LCBidXQgY2hhbmdpbmcgaXQgaXMgbm90IGFs bG93ZWQuCgoKICBUaGl= `pragma protect key_keyowner="BIG3#3" `pragma protect key_keyname="CCCCCCCC" `pragma protect key_method="RSA" `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `pragma protect key_block TGljZW5zZSBpbmNvcnBvcmF0ZXMKdGhlIHRlcm1zIGFuZCBjb25kaXRpb25zIG9mIHZlcnNpb24g MyBvZiB0aGUgR05VIEdlbmVyYWwgUHVibGljCkxpY2Vuc2UsIHN1cHBsZW1lbnRlZCBieSB0aGUg YWRkaXRpb25hbCBwZXJ= `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 295) `pragma protect data_block aW5pdGlvbnMuCgogIEFzIHVzZWQgaGVyZWluLCAidGhpcyBMaWNlbnNlIiByZWZlcnMgdG8gdmVy c2lvbiAzIG9mIHRoZSBHTlUgTGVzc2VyCkdlbmVyYWwgUHVibGljIExpY2Vuc2UsIGFuZCB0aGUg IkdOVSBHUEwiIHJlZmVycyB0byB2ZXJzaW9uIDMgb2YgdGhlIEdOVQpHZW5lcmFsIFB1YmxpYyBM aWNlbnNlLgoKICAiVGhlIExpYnJhcnkiIHJlZmVycyB0byBhIGNvdmVyZWQgd29yayBnb3Zlcm5l ZCBieSB0aGlzIExpY2Vuc2UsCm90aGVyIHRoYW4gYW4gQXBwbGljYXRpb24gb3IgYSBDb21iaW5l ZCBXb3JrIGFzIG== `pragma protect end_protected // encoding envelope `pragma protect `pragma protect end endmodule //====================================================================== // macro call with define that has comma `define REG_H 6 `define REG_L 7 `define _H regs[`REG_H] `define _L regs[`REG_L] `define _HL {`_H, `_L} `define EX_WRITE(ad, da) begin addr <= (ad); wdata <= (da); wr <= 1; end `define EX_READ(ad) begin addr <= (ad); rd <= 1; end `EX_READ((`_HL + 1)) and `EX_WRITE((`_HL), rdata) `EX_READ(`_HL + 1) `EX_WRITE(`_HL, rdata) more //====================================================================== // include of parameterized file `define INCNAME "t_preproc_inc4.vh" `include `INCNAME `ifndef T_PREPROC_INC4 `error "No Inc4" `endif `undef T_PREPROC_INC4 `ifdef NOT_DEFINED_INC `include NOT_DEFINED_INC `endif //====================================================================== // macro call with , in {} `define xxerror(logfile, msg) $blah(logfile,msg) `xxerror("ab,cd","e,f"); `xxerror(this.logfile, vec); `xxerror(this.logfile, vec[1,2,3]); `xxerror(this.logfile, {blah.name(), " is not foo"}); //====================================================================== // pragma/default net type `pragma foo = 1 `default_nettype none `default_nettype uwire //====================================================================== // Ifdef `define EMPTY_TRUE `ifndef EMPTY_TRUE `error "Empty is still true" `endif Line_Preproc_Check `__LINE__ //====================================================================== // bug84 `define ARGPAR(a, // Hello, comments MIGHT not be legal /*more,,)cmts*/ b // But newlines ARE legal... who speced THAT? ) (a,b) `ARGPAR(p,q) `ARGPAR( //Here x, y //Too ) Line_Preproc_Check `__LINE__ //====================================================================== // defines split arguments `define BEGIN begin `define END end `define BEGINEND `BEGIN`END `define quoteit(x) `"x`" `BEGIN`END // 2001 spec doesn't require two tokens, so "beginend" ok `BEGINEND // 2001 spec doesn't require two tokens, so "beginend" ok `quoteit(`BEGIN`END) // No space "beginend" //====================================================================== // bug106 `define \esc`def got_escaped `ifdef \esc`def `\esc`def `endif Not a \`define //====================================================================== // misparsed comma in submacro `define sb bee `define appease_emacs_paren_matcher ( `define sa(l) x,y) `define sfoo(q,r) q--r `sfoo(`sa(el),`sb) submacro has comma paren //====================================================================== // bug191 `define bug191(bits) $display("bits %d %d", $bits(foo), bits); `bug191(10) //====================================================================== // 1800-2009 `define UDALL `ifndef PREDEF_COMMAND_LINE `error "Test setup error, PREDEF_COMMAND_LINE pre-missing" `endif `undefineall `ifdef UDALL `error "undefineall failed" `endif `ifndef PREDEF_COMMAND_LINE `error "Deleted too much, no PREDEF_COMMAND_LINE" `endif //====================================================================== // bug202 `define FC_INV3(out, in) \ `ifdef DC \ cell \inv_``out <$typeof(out)> (.a(), .o()); \ /* multi-line comment \ multi-line comment */ \ `else \ `ifdef MACRO_ATTRIBUTE \ (* macro_attribute = `"INV (out``,in``)`" *) \ `endif \ assign out = ~in ; \ `endif `FC_INV3(a3,b3) `define /* multi \ line1*/ \ bug202( i /*multi \ line2*/ \ ) \ /* multi \ line 3*/ \ def i \ `bug202(foo) //====================================================================== `define CMT1 // verilator NOT IN DEFINE `define CMT2 /* verilator PART OF DEFINE */ `define CMT3 /* verilator NOT PART OF DEFINE */ `define CMT4 /* verilator PART \ OF DEFINE */ `define CMT5 // CMT NOT \ also in // BUT TEXT IS \ also3 // CMT NOT 1 `CMT1 (nodef) 2 `CMT2 (hasdef) 3 `CMT3 (nodef) 4 `CMT4 (nodef) 5 `CMT5 (nodef) `define NL HAS a NEW \ LINE `NL //====================================================================== `define msg_fatal(log, msg) \ do \ /* synopsys translate_off */ \ `ifdef NEVER \ `error "WTF" \ `else \ if (start(`__FILE__, `__LINE__)) begin \ `endif \ message(msg); \ end \ /* synopsys translate_on */ \ while(0) `define msg_scen_(cl) cl``_scen `define MSG_MACRO_TO_STRING(x) `"x`" EXP: clxx_scen `msg_scen_(clxx) EXP: clxx_scen `MSG_MACRO_TO_STRING(`msg_scen_(clxx)) `define mf(clx) `msg_fatal(this.log, {"Blah-", `MSG_MACRO_TO_STRING(`msg_scen_(clx)), " end"}); EXP: do if (start("verilog/inc1.v", 25)) begin message({"Blah-", "clx_scen", " end"}); end while(0); `mf(clx) //====================================================================== `define makedefine(name) \ `define def_``name This is name \ `define def_``name``_2 This is name``_2 \ `makedefine(fooed) `ifndef def_fooed `error "No def_fooed" `endif //`ifndef def_fooed_2 `error "No def_fooed_2" `endif EXP: This is fooed `def_fooed EXP: This is fooed_2 `def_fooed_2 //====================================================================== `define NOPARAM() np `NOPARAM() `NOPARAM( ) //====================================================================== // It's unclear if the spec allows this; is text_macro_idenitfier before or after substitution? `define NODS_DEFINED `define NODS_INDIRECT(x) x `ifndef `NODS_INDIRECT(NODS_DEFINED) `error "Indirect failed" `endif `ifdef `NODS_INDIRECT(NODS_UNDEFINED) `error "Indirect2 failed" `endif //====================================================================== // Metaprogramming `define REPEAT_0(d) `define REPEAT_1(d) d `define REPEAT_2(d) `REPEAT_1(d)d `define REPEAT_3(d) `REPEAT_2(d)d `define REPEAT_4(d) `REPEAT_3(d)d `define CONCAT(a, b) a``b `define REPEATC(n, d) `CONCAT(`REPEAT_, n)(d) `define REPEATT(n, d) `REPEAT_``n(d) `REPEATC(3, hello3 ) `REPEATT(4, hello4 ) //====================================================================== // Include from stringification `undef T_PREPROC_INC4 `define NODS_CONC_VH(m) `"m.vh`" `include `NODS_CONC_VH(t_preproc_inc4) `ifndef T_PREPROC_INC4 `error_here `endif //====================================================================== // Defines doing defines // Note the newline on the end - required to form the end of a define `define DEFINEIT(d) d \ `define _DEFIF_Z_0 1 `define DEFIF_NZ(d,n) `undef d `ifndef _DEFIF_Z_``n `DEFINEIT(`define d 1) `endif `DEFIF_NZ(TEMP,1) `ifndef TEMP `error "bad" `endif `DEFIF_NZ(TEMP,0) `ifdef TEMP `error "bad0" `endif Line_Preproc_Check `__LINE__ //====================================================================== // Quoted multiline - track line numbers, and ensure \\n gets propagated `define MULQUOTE "FOO \ BAR " `define MULQUOTE2(mq) `MULQUOTE mq `MULQUOTE Line_Preproc_Check `__LINE__ `MULQUOTE2("arg_line1 \ arg_line2") Line_Preproc_Check `__LINE__ //====================================================================== // bug283 `define A a `define B b `define C c // EXP: abc `define C5 `A``b```C `C5 `undef A `undef B `undef C `define XTYPE sonet `define XJOIN(__arg1, __arg2) __arg1``__arg2 `define XACTION `XJOIN(`XTYPE, _frame) EXP: sonet_frame `XACTION // `define XFRAME frame `define XACTION2 `XJOIN(sonet_, `XFRAME) EXP: sonet_frame `XACTION2 // This result varies between simulators `define sonet_frame other_frame `define XACTION3 `XTYPE``_frame EXP: sonet_frame `XACTION3 // The existance of non-existance of a base define can make a difference `define QA_b zzz `define Q1 `QA``_b EXP: module zzz ; endmodule module `Q1 ; endmodule module `Q1 ; endmodule `define QA a EXP: module a_b ; endmodule module `Q1 ; endmodule module `Q1 ; endmodule //====================================================================== // bug311 integer/*NEED_SPACE*/foo; //====================================================================== // bug441 module t; //----- // case provided // note this does NOT escape as suggested in the mail `define LEX_CAT(lexem1, lexem2) lexem1``lexem2 `define LEX_ESC(name) \name \ initial begin : `LEX_ESC( `LEX_CAT(a[0],_assignment) ) $write("GOT%%m='%m' EXP='%s'\n", "t.\\`LEX_CAT(a[0],_assignment) "); end //----- // SHOULD(simulator-dependant): Backslash doesn't prevent arguments from // substituting and the \ staying in the expansion // Note space after name is important so when substitute it has ending whitespace `define ESC_CAT(name,name2) \name``_assignment_``name2 \ initial begin : `ESC_CAT( a[0],a[1] ) $write("GOT%%m='%m' EXP='%s'\n", "t.\\a[0]_assignment_a[1] "); end `undef ESC_CAT //----- `define CAT(a,b) a``b `define ESC(name) \`CAT(name,suffix) // RULE: Ignoring backslash does NOT allow an additional expansion level // (Because ESC gets expanded then the \ has it's normal escape meaning) initial begin : `ESC(pp) $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(pp,suffix) "); end `undef CAT `undef ESC //----- `define CAT(a,b) a``b `define ESC(name) \name \ // Similar to above; \ does not allow expansion after substitution initial begin : `ESC( `CAT(ff,bb) ) $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(ff,bb) "); end `undef CAT `undef ESC //----- `define ESC(name) \name \ // MUST: Unknown macro with backslash escape stays as escaped symbol name initial begin : `ESC( `zzz ) $write("GOT%%m='%m' EXP='%s'\n", "t.\\`zzz "); end `undef ESC //----- `define FOO bar `define ESC(name) \name \ // SHOULD(simulator-dependant): Known macro with backslash escape expands initial begin : `ESC( `FOO ) $write("GOT%%m='%m' OTHER_EXP='%s'\n OUR_EXP='%s'", "t.bar ","t.\\`FOO "); end // SHOULD(simulator-dependant): Prefix breaks the above initial begin : `ESC( xx`FOO ) $write("GOT%%m='%m' EXP='%s'\n", "t.\\xx`FOO "); end `undef FOO `undef ESC //----- // MUST: Unknown macro not under call with backslash escape doesn't expand `undef UNKNOWN initial begin : \`UNKNOWN $write("GOT%%m='%m' EXP='%s'\n", "t.\\`UNKNOWN "); end //----- // MUST: Unknown macro not under call doesn't expand `define DEF_NO_EXPAND error_dont_expand initial begin : \`DEF_NO_EXPAND $write("GOT%%m='%m' EXP='%s'\n", "t.\\`DEF_NO_EXPAND "); end `undef DEF_NO_EXPAND //----- // bug441 derivative // Clarified in IEEE 1800-2023: Quotes prevent arguments from expanding `define STR(name) "foo name baz" initial $write("GOT='%s' EXP='%s'\n", `STR(bar), "foo bar baz"); `undef STR //----- // RULE: Because there are quotes after substituting STR, the `A does NOT expand `define STR(name) "foo name baz" `define A(name) boo name hiss initial $write("GOT='%s' EXP='%s'\n", `STR(`A(bar)), "foo `A(bar) baz"); `undef A `undef STR //---- // bug845 `define SLASHED "1//2.3" initial $write("Slashed=`%s'\n", `SLASHED); //---- // bug915 `define BUG915(a,b,c) \ $display("%s%s",a,`"b``c``\n`") initial `BUG915("a1",b2,c3); endmodule //====================================================================== //bug1225 `define X_ITEM(SUB,UNIT) `X_STRING(SUB``UNIT) `define X_STRING(A) `"A`" $display(`X_ITEM(RAM,0)); $display(`X_ITEM(CPU,)); `define EMPTY `define EMPTYP(foo) `define SOME some `define SOMEP(foo) foo `define XXE_FAMILY XXE_```EMPTY XXE_FAMILY = `XXE_FAMILY `define XXE_```EMPTY `ifdef XXE_ $display("XXE_ is defined"); `endif `define XYE_FAMILY XYE_```EMPTYP(foo) XYE_FAMILY = `XYE_FAMILY `define XYE_```EMPTYP(foo) `ifdef XYE_ $display("XYE_ is defined"); `endif `define XXS_FAMILY XXS_```SOME XXS_FAMILY = `XXS_FAMILY `define XXS_```SOME `ifdef XXS_some $display("XXS_some is defined"); `endif `define XYS_FAMILY XYS_```SOMEP(foo) XYS_FAMILY = `XYS_FAMILY `define XYS_```SOMEP(foo) `ifdef XYS_foo $display("XYS_foo is defined"); `endif //==== `ifdef NEVER `define NXE_FAMILY NXE_```EMPTY NXE_FAMILY = `NXE_FAMILY `define NXE_```EMPTY `ifdef NXE_ $display("NXE_ is defined"); `endif `define NYE_FAMILY NYE_```EMPTYP(foo) NYE_FAMILY = `NYE_FAMILY `define NYE_```EMPTYP(foo) `ifdef NYE_ $display("NYE_ is defined"); `endif `define NXS_FAMILY NXS_```SOME NXS_FAMILY = `NXS_FAMILY `define NXS_```SOME `ifdef NXS_some $display("NXS_some is defined"); `endif `define NYS_FAMILY NYS_```SOMEP(foo) NYS_FAMILY = `NYS_FAMILY `define NYS_```SOMEP(foo) `ifdef NYS_foo $display("NYS_foo is defined"); `endif `include `EMPTY `endif // NEVER //bug1227 `define INSTANCE(NAME) (.mySig (myInterface.``NAME), `INSTANCE(pa5) //====================================================================== // Stringify bug `define hack(GRP) `dbg_hdl(UVM_LOW, (`"Functional coverage enabled: GRP`")); `hack(paramgrp) `define dbg_hdl(LVL, MSG) $display ("DEBUG : %s [%m]", $sformatf MSG) `define svfcov_new(GRP) \ initial do begin `dbg_hdl(UVM_LOW, (`"Functional coverage enabled: GRP`")); end while(0) `define simple_svfcov_clk(LBL, CLK, RST, ARG) \ covergroup LBL @(posedge CLK); \ c: coverpoint ARG iff ((RST) === 1'b1); endgroup \ LBL u_``LBL; `svfcov_new(u_``LBL) module pcc2_cfg; generate `simple_svfcov_clk(a, b, c, d); endgenerate endmodule //====================================================================== // Verilog-Perl bug1668 `define stringify(text) `"text`" `stringify(`NOT_DEFINED_STR) //====================================================================== """First line with "quoted"\nSecond line\ Third line""" """First line Second line""" `define QQQ """QQQ defform""" `define QQQS(x) x `QQQ `QQQS("""QQQ defval""") // string concat bug `define IDENTITY(arg) ``arg `IDENTITY("string argument") //====================================================================== // See issue #5094 - IEEE 1800-2023 clarified proper behavior `define MAC_WITH_STR(foo) foo "foo foo foo" foo `MAC_WITH_STR(bar) `define MAC_WITH_3STR(foo) foo """foo foo foo""" foo `MAC_WITH_3STR(bar) //====================================================================== // IEEE mandated predefines `undefineall // undefineall should have no effect on these predef `SV_COV_START 0 predef `SV_COV_STOP 1 predef `SV_COV_RESET 2 predef `SV_COV_CHECK 3 predef `SV_COV_MODULE 10 predef `SV_COV_HIER 11 predef `SV_COV_ASSERTION 20 predef `SV_COV_FSM_STATE 21 predef `SV_COV_STATEMENT 22 predef `SV_COV_TOGGLE 23 predef `SV_COV_OVERFLOW -2 predef `SV_COV_ERROR -1 predef `SV_COV_NOCOV 0 predef `SV_COV_OK 1 predef `SV_COV_PARTIAL 2 //====================================================================== // After `undefineall above, for testing --dump-defines `define WITH_ARG(a) (a)(a) //====================================================================== // Stringify in nested macro `define foo test `define a x,y `define bar(a, b) test a b `define baz(a, b) test``a``b `define qux(x) string boo = x; `define quux(x) `qux(`"x`") `quux(`foo) `quux(`bar(`a,`a)) `quux(`baz(`a,`bar(x,`a))) `quux(`baz(`bar(`a,x), quux(`foo))) //====================================================================== // Define with --preproc-defines needs to keep backslashes `define uvm_a(x) foo x bar `define uvm_imp_decl(SFX) \ class uvm_master_imp``SFX \ `uvm_a(SFX, RSP, t) // rsp \ \ `uvm_a(SFX, REQ, t) // req \ \ endclass verilator-5.042/test_regress/t/t_param_array8.v0000644000542200017500000000113315101701376022164 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module sub #( parameter int unsigned VAL[2] = '{1, 2} ) (); endmodule module t; sub sub12 (); sub #(.VAL ( '{3, 4} )) sub34 (); initial begin if (sub12.VAL[0] != 1) $stop; if (sub12.VAL[1] != 2) $stop; if (sub34.VAL[0] != 3) $stop; if (sub34.VAL[1] != 4) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_lint_paramnodefault_bad.out0000644000542200017500000000051415101701376025000 0ustar mahmoudyfreeshell%Error-PARAMNODEFAULT: t/t_lint_paramnodefault.v:8:13: Parameter without default requires ANSI-style parameter list (IEEE 1800-2023 6.20.1): 'NODEF' 8 | parameter NODEF; | ^~~~~ ... For error description see https://verilator.org/warn/PARAMNODEFAULT?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_inst_nansi_dup_bad.out0000644000542200017500000000115115101701376023763 0ustar mahmoudyfreeshell%Error: t/t_inst_nansi_dup_bad.v:16:7: Duplicate declaration of signal: 'bad4' 16 | reg bad4; | ^~~~ t/t_inst_nansi_dup_bad.v:14:10: ... Location of original declaration 14 | output bad4; | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_inst_nansi_dup_bad.v:19:10: Duplicate declaration of signal: 'bad5' 19 | output bad5; | ^~~~ t/t_inst_nansi_dup_bad.v:18:10: ... Location of original declaration 18 | output bad5; | ^~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_json_only_tag.v0000644000542200017500000000334515101701376022452 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Chris Randall. // SPDX-License-Identifier: CC0-1.0 interface ifc; integer value; modport out_modport (output value); endinterface module m ( input clk_ip, // verilator tag clk_ip input rst_ip, output foo_op); // verilator tag foo_op // This is a comment typedef struct packed { logic clk; /* verilator tag this is clk */ logic k; /* verilator lint_off UNUSED */ logic enable; // verilator tag enable logic data; // verilator tag data } my_struct; // verilator tag my_struct // This is a comment ifc itop(); my_struct this_struct [2]; // verilator tag this_struct wire [31:0] dotted = itop.value; function void f(input string m); $display("%s", m); endfunction initial begin // Contains all 256 characters except 0 (null character) f("\x01\x02\x03\x04\x05\x06\a\x08\t\n\v\f\r\x0e\x0f\x10\x11\x12\x13\x14\x15\x16\x17\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f !\"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\\]^_`abcdefghijklmnopqrstuvwxyz{|}~\x7f\x80\x81\x82\x83\x84\x85\x86\x87\x88\x89\x8a\x8b\x8c\x8d\x8e\x8f\x90\x91\x92\x93\x94\x95\x96\x97\x98\x99\x9a\x9b\x9c\x9d\x9e\x9f\xa0\xa1\xa2\xa3\xa4\xa5\xa6\xa7\xa8\xa9\xaa\xab\xac\xad\xae\xaf\xb0\xb1\xb2\xb3\xb4\xb5\xb6\xb7\xb8\xb9\xba\xbb\xbc\xbd\xbe\xbf\xc0\xc1\xc2\xc3\xc4\xc5\xc6\xc7\xc8\xc9\xca\xcb\xcc\xcd\xce\xcf\xd0\xd1\xd2\xd3\xd4\xd5\xd6\xd7\xd8\xd9\xda\xdb\xdc\xdd\xde\xdf\xe0\xe1\xe2\xe3\xe4\xe5\xe6\xe7\xe8\xe9\xea\xeb\xec\xed\xee\xef\xf0\xf1\xf2\xf3\xf4\xf5\xf6\xf7\xf8\xf9\xfa\xfb\xfc\xfd\xfe\xff"); end endmodule verilator-5.042/test_regress/t/t_lint_pinmissing_bad.out0000644000542200017500000000077115101701376024163 0ustar mahmoudyfreeshell%Warning-PINMISSING: t/t_lint_pinmissing_bad.v:8:8: Instance has missing pin: 'port' 8 | sub sub(); | ^~~ t/t_lint_pinmissing_bad.v:11:11: ... Location of port declaration 11 | (output port); | ^~~~ ... For warning description see https://verilator.org/warn/PINMISSING?v=latest ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_interface_generic_submod_param.py0000755000542200017500000000101315101701376026146 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(timing_loop=True, verilator_flags2=['--timing']) test.execute() test.passes() verilator-5.042/test_regress/t/t_force_release_var_trace.py0000755000542200017500000000115115101701376024610 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_force_release_var.v" test.compile(verilator_flags2=['--trace-vcd']) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_cover_lib__1.out0000644000542200017500000000111615101701376022464 0ustar mahmoudyfreeshell# SystemC::Coverage-3 C 'f../../t/t_cover_lib_c.cppl39t_userpagesp_user/t_cover_lib_cP0htop.a*.pi' 500 C 'f../../t/t_cover_lib_c.cppl39t_userpagesp_user/t_cover_lib_cP1htop.a0.npi' 200 C 'f../../t/t_cover_lib_c.cppl39t_userpagesp_user/t_cover_lib_cP1htop.a1.npi' 300 C 'f../../t/t_cover_lib_c.cppl48t_userpagesp_user/t_cover_lib_cokept_onehmain' 100 C 'f../../t/t_cover_lib_c.cppl49t_userpagesp_user/t_cover_lib_cokept_twohmain' 210 C 'f../../t/t_cover_lib_c.cppl50t_userpagesp_user/t_cover_lib_colost_threehmain' 220 verilator-5.042/test_regress/t/t_langext_1_bad.py0000755000542200017500000000116315101701376022457 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.top_filename = "t/t_langext_1.v" test.leak_check_disable() # This is a lint only test. test.lint(v_flags2=["+verilog1995ext+v"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_preproc_cmtend_bad.py0000755000542200017500000000102515101701376023576 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, verilator_flags2=['--no-std'], expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_math_svl.py0000755000542200017500000000112115101701376021576 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() # Make sure we get the finish statement called test.file_grep(test.run_log_filename, r'Goodbye world, at cycle \d') test.passes() verilator-5.042/test_regress/t/t_class_param_bad1.out0000644000542200017500000000075715101701376023327 0ustar mahmoudyfreeshell%Error-PINNOTFOUND: t/t_class_param_bad1.v:12:11: Parameter not found: 'PARAMBAD' : ... Suggested alternative: 'PARAMB' 12 | Cls #(.PARAMBAD(1)) c; | ^~~~~~~~ ... For error description see https://verilator.org/warn/PINNOTFOUND?v=latest %Error-PINNOTFOUND: t/t_class_param_bad1.v:13:14: Parameter not found: '__paramNumber2' 13 | Cls #(13, 1) cd; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_tri_pull_implicit.py0000755000542200017500000000073415101701376023516 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_dfg_synthesis_pre_inline.py0000755000542200017500000000711115101701376025043 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.sim_time = 2000000 if not os.path.exists(test.root + "/.git"): test.skip("Not in a git repository") # Generate the equivalence checks and declaration boilerplate rdFile = test.top_filename plistFile = test.obj_dir + "/portlist.vh" pdeclFile = test.obj_dir + "/portdecl.vh" checkFile = test.obj_dir + "/checks.h" nAlwaysSynthesized = 0 nAlwaysNotSynthesized = 0 nAlwaysReverted = 0 with open(rdFile, 'r', encoding="utf8") as rdFh, \ open(plistFile, 'w', encoding="utf8") as plistFh, \ open(pdeclFile, 'w', encoding="utf8") as pdeclFh, \ open(checkFile, 'w', encoding="utf8") as checkFh: for line in rdFh: if re.search(r'^\s*always.*//\s*nosynth$', line): nAlwaysNotSynthesized += 1 elif re.search(r'^\s*always.*//\s*revert$', line): nAlwaysReverted += 1 elif re.search(r'^\s*always', line): nAlwaysSynthesized += 1 line = line.split("//")[0] m = re.search(r'`signal\((\w+),', line) if not m: continue sig = m.group(1) plistFh.write(sig + ",\n") pdeclFh.write("output " + sig + ";\n") checkFh.write("if (ref." + sig + " != opt." + sig + ") {\n") checkFh.write(" std::cout << \"Mismatched " + sig + "\" << std::endl;\n") checkFh.write(" std::cout << \"Ref: 0x\" << std::hex << (ref." + sig + " + 0) << std::endl;\n") checkFh.write(" std::cout << \"Opt: 0x\" << std::hex << (opt." + sig + " + 0) << std::endl;\n") checkFh.write(" std::exit(1);\n") checkFh.write("}\n") # Compile un-optimized test.compile(verilator_flags2=[ "--stats", "--build", "-fno-dfg", "+incdir+" + test.obj_dir, "-Mdir", test.obj_dir + "/obj_ref", "--prefix", "Vref", "-Wno-UNOPTFLAT" ]) # yapf:disable test.file_grep_not(test.obj_dir + "/obj_ref/Vref__stats.txt", r'DFG.*Synthesis') # Compile optimized - also builds executable test.compile(verilator_flags2=[ "--stats", "--build", "--fdfg-synthesize-all", "-fno-dfg-post-inline", "-fno-dfg-scoped", "--exe", "+incdir+" + test.obj_dir, "-Mdir", test.obj_dir + "/obj_opt", "--prefix", "Vopt", "-fno-const-before-dfg", # Otherwise V3Const makes testing painful "-fno-split", # Dfg will take care of it "--debug", "--debugi", "0", "--dumpi-tree", "0", "-CFLAGS \"-I .. -I ../obj_ref\"", "../obj_ref/Vref__ALL.a", "../../t/" + test.name + ".cpp" ]) # yapf:disable test.file_grep(test.obj_dir + "/obj_opt/Vopt__stats.txt", r'DFG pre inline Synthesis, synt / always blocks considered\s+(\d+)$', nAlwaysSynthesized + nAlwaysReverted + nAlwaysNotSynthesized) test.file_grep(test.obj_dir + "/obj_opt/Vopt__stats.txt", r'DFG pre inline Synthesis, synt / always blocks synthesized\s+(\d+)$', nAlwaysSynthesized + nAlwaysReverted) test.file_grep(test.obj_dir + "/obj_opt/Vopt__stats.txt", r'DFG pre inline Synthesis, synt / reverted \(multidrive\)\s+(\d)$', nAlwaysReverted) # Execute test to check equivalence test.execute(executable=test.obj_dir + "/obj_opt/Vopt") test.passes() verilator-5.042/test_regress/t/t_savable_open_bad2.out0000644000542200017500000000027015101701376023467 0ustar mahmoudyfreeshell%Error: unknown:0: Testbench C called 'dpix_task' but scope wasn't set, perhaps due to dpi import call without 'context', or missing svSetScope. See IEEE 1800-2023 35.5.3. Aborting... verilator-5.042/test_regress/t/t_interface_generic_normal.py0000755000542200017500000000077115101701376024777 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--timing']) test.execute() test.passes() verilator-5.042/test_regress/t/t_enum_type_methods_bad.v0000644000542200017500000000112715101701376024137 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk, increment ); input clk; input [1:0] increment; typedef enum [3:0] { E01 = 1, E03 = 3, E04 = 4, E05 = 5 } my_t; my_t e; always @ (posedge clk) begin e.next(increment); $finish; end endmodule verilator-5.042/test_regress/t/t_fork_initial.v0000644000542200017500000000062215101701376022252 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(); initial fork reg i; i = 1'b1; begin #1; if (i != 1'b1) $stop; $write("*-* All Finished *-*\n"); $finish; end join endmodule verilator-5.042/test_regress/t/t_time_print.v0000644000542200017500000000207515101701376021756 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under The Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; timeunit 1ns; timeprecision 1ps; time t; initial begin t = 10ns; $write("[%0t] In %m: Hi\n", $time); $printtimescale; $printtimescale(); $printtimescale(t); $write("Time: '%t' 10ns=%0t\n", $time, t); $timeformat(-3, 0, "-my-ms", 8); $write("Time: '%t' 10ns=%0t\n", $time, t); $timeformat(-3, 1, "-my-ms", 10); $write("Time: '%t' 10ns=%0t\n", $time, t); $timeformat(-6, 2, "-my-us", 12); $write("Time: '%t' 10ns=%0t\n", $time, t); $timeformat(-9, 3, "-my-ns", 13); $write("Time: '%t' 10ns=%0t\n", $time, t); $timeformat(-12, 3, "-my-ps", 13); $write("Time: '%t' 10ns=%0t\n", $time, t); $timeformat(-15, 4, "-my-fs", 14); $write("Time: '%t' 10ns=%0t\n", $time, t); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_flag_future_bad.out0000644000542200017500000000143615101701376023257 0ustar mahmoudyfreeshell%Error: t/t_flag_future.v:8:7: Unknown verilator lint message code: 'FUTURE1', in '/*verilator lint_off FUTURE1*/' 8 | /*verilator lint_off FUTURE1*/ | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error-BADVLTPRAGMA: t/t_flag_future.v:11:7: Unknown verilator comment: '/*verilator FUTURE2*/' 11 | /*verilator FUTURE2*/ | ^~~~~~~~~~~~~~~~~~~~~ ... For error description see https://verilator.org/warn/BADVLTPRAGMA?v=latest %Error-BADVLTPRAGMA: t/t_flag_future.v:12:7: Unknown verilator comment: '/*verilator FUTURE2 blah blah*/' 12 | /*verilator FUTURE2 blah blah*/ | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_unopt_array_typedef.py0000755000542200017500000000111215101701376024044 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_unopt_array.v" test.compile(verilator_flags2=["-Wno-UNOPTFLAT", "+define+USE_TYPEDEF", "-fno-dfg"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_parse_eof_attr_bad.py0000755000542200017500000000076615101701376023602 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_timing_suspend_two_retrigger.v0000644000542200017500000000141515101701376025574 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module top; event a; event b; initial begin #10; ->b; $display("Sleeping at %0t", $time); @(a or b); // This must wake at due to 'a' from the other block $display("Waking at %0t", $time); if ($time != 20) $stop; #10; ->a; ->b; $display("Sleeping at %0t", $time); @(a or b); // This must wake at due to 'a' from the other block $display("Waking at %0t", $time); if ($time != 40) $stop; $write("*-* All Finished *-*\n"); $finish; end always begin @b; #10; ->a; end endmodule verilator-5.042/test_regress/t/t_bitsel_const_bad.py0000755000542200017500000000076615101701376023275 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_sarif.v0000644000542200017500000000074615101701376020713 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t( input clk1, input clk2, output logic multidriven); wire [1:0] trunced = 5'b11111; // Warned always @ (posedge clk1) multidriven <= '1; always @ (posedge clk2) multidriven <= '0; endmodule module t; // BAD duplicate endmodule verilator-5.042/test_regress/t/t_lint_latch_8.py0000755000542200017500000000070315101701376022336 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint() test.passes() verilator-5.042/test_regress/t/t_constraint_soft_randc_bad.py0000755000542200017500000000077615101701376025174 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_display_brace.py0000755000542200017500000000073415101701376022573 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_randc_oversize_bad.out0000644000542200017500000000054015101701376023764 0ustar mahmoudyfreeshell%Error: t/t_randc_oversize_bad.v:8:21: Maximum implemented width for randc is 32 bits, 'i' is 38 bits : ... note: In instance 't' 8 | randc bit [37:0] i; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_inst_param_override_bad.out0000644000542200017500000000262215101701376025006 0ustar mahmoudyfreeshell%Error: t/t_inst_param_override_bad.v:33:23: Instance attempts to override 'PACKED_DATA_WIDTH' as a parameter, but it is a local parameter 33 | axi_stream_if # (.PACKED_DATA_WIDTH(10)) axis1(clk); | ^~~~~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_inst_param_override_bad.v:35:23: Instance attempts to override 'mytask' as a parameter, but it is a task 35 | axi_stream_if # (.mytask(10)) axis2(clk); | ^~~~~~ %Error: t/t_inst_param_override_bad.v:37:23: Instance attempts to override 'my_genvar' as a parameter, but it is a variable 37 | axi_stream_if # (.my_genvar(10)) axis3(clk); | ^~~~~~~~~ %Error: t/t_inst_param_override_bad.v:39:23: Instance attempts to override 'clk' as a parameter, but it is a port 39 | axi_stream_if # (.clk(10)) axis4(clk); | ^~~ %Error: t/t_inst_param_override_bad.v:41:23: Instance attempts to override 'tvalid' as a parameter, but it is a variable 41 | axi_stream_if # (.tvalid(10)) axis5(clk); | ^~~~~~ %Error: t/t_inst_param_override_bad.v:43:23: Instance attempts to override 'i_sub' as a parameter, but it is an instance 43 | axi_stream_if # (.i_sub(10)) axis6(clk); | ^~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_udp_tableeof_bad.v0000644000542200017500000000053515101701376023042 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 primitive udp_x (a_bad, b, c_bad); tri a_bad; output b; output c_bad; table //a b 0 : 1; 1 : 0; verilator-5.042/test_regress/t/t_property_sexpr.py0000755000542200017500000000107315101701376023074 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(timing_loop=True, verilator_flags2=['--assert', '--timing']) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_restore_bad.py0000755000542200017500000000076315101701376023313 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_pp_resetall_bad.py0000755000542200017500000000102715101701376023106 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["-Wpedantic"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_ccache_report__ccache_report_rebuild.out0000644000542200017500000000035615101701376027475 0ustar mahmoudyfreeshell################################################################################ ccache report (from verilator_ccache_report) : All object files up to date ################################################################################ verilator-5.042/test_regress/t/t_bitsel_struct3.py0000755000542200017500000000073415101701376022743 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_randomize_complex_member_bad.py0000755000542200017500000000114215101701376025640 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') if not test.have_solver: test.skip("No constraint solver installed") test.lint(verilator_flags2=["--lint-only"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_preproc_inc_bad.v0000644000542200017500000000043515101701376022713 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 //See bug289 `include "t_preproc_inc_inc_bad.vh" module t; endmodule verilator-5.042/test_regress/t/t_event_class_fire.py0000755000542200017500000000115415101701376023302 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') # Issue #5597 makes this fail test.compile(fails=test.vlt_all, expect_filename=test.golden_filename, verilator_flags2=['--timing']) #test.execute() test.passes() verilator-5.042/test_regress/t/t_udp_tableend_bad.py0000755000542200017500000000110115101701376023213 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["--lint-only --bbox-unsup"], fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_queue_method3_bad.out0000644000542200017500000000071115101701376023516 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_queue_method3_bad.v:16:52: Unsupported: Member call on object 'SEL' which is a 'BASICDTYPE 'int'' : ... note: In instance 't' 16 | points_qv = points_q.find_first(a) with (a.x.index == 0); | ^~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_queue_unpacked.py0000755000542200017500000000073415101701376022770 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_constraint_mode.v0000644000542200017500000000466415101701376023002 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Foo; rand int x; endclass class Bar extends Foo; rand int y; constraint cons_x {x > 0; x < 10;}; constraint cons_y {y == 10;}; endclass class Qux extends Bar; rand int z; rand Bar bar; constraint cons_z {z == x || z == y;}; function new; bar = new; endfunction function void test; logic[1:0] ok = 0; cons_x.constraint_mode(1); if (cons_x.constraint_mode == 0) $stop; cons_y.constraint_mode(0); if (cons_y.constraint_mode == 1) $stop; bar.cons_x.constraint_mode(0); if (bar.cons_x.constraint_mode == 1) $stop; for (int i = 0; i < 20; ++i) begin x = 11; y = 12; z = 13; bar.x = 8; bar.y = 9; void'(randomize()); if (x <= 0 || x >= 10) $stop; if (y != 10 && y != 12) ok[0] = 1; if (z != x && z != y) $stop; if (bar.x <= 0 || bar.x >= 10) ok[1] = 1; if (bar.y != 10) $stop; end if (ok != 2'b11) $stop; constraint_mode(1); if (cons_x.constraint_mode != 1) $stop; if (cons_y.constraint_mode != 1) $stop; if (cons_z.constraint_mode != 1) $stop; x = 14; y = 15; z = 16; void'(randomize()); if (x <= 0 || x >= 10) $stop; if (y != 10) $stop; if (z != x && z != y) $stop; endfunction endclass module t; initial begin logic[1:0] ok = 0; int res; Qux qux = new; Bar bar = qux; qux.test; qux.bar.constraint_mode(1); bar.cons_y.constraint_mode(1); if (bar.cons_y.constraint_mode == 0) $stop; qux.cons_z.constraint_mode(0); if (qux.cons_z.constraint_mode == 1) $stop; qux.bar.cons_y.constraint_mode(0); if (qux.bar.cons_y.constraint_mode == 1) $stop; for (int i = 0; i < 20; ++i) begin qux.x = 17; qux.y = 18; qux.z = 19; qux.bar.x = 20; qux.bar.y = 10; void'(bar.randomize()); if (qux.x <= 0 || qux.x >= 10) $stop; if (qux.y != 10 && qux.y != 12) $stop; if (qux.z != qux.x && qux.z != qux.y) ok[0] = 1; if (qux.bar.x <= 0 || qux.bar.x >= 10) $stop; if (qux.bar.y != 10) ok[1] = 1; res = qux.randomize() with {z == 100;}; if (qux.z != 100) $stop; end if (ok != 2'b11) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_trace_decoration.v0000644000542200017500000000120415101701376023102 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; integer a_very_long_name_which_we_will_hash_eventually=0; always @ (posedge clk) begin a_very_long_name_which_we_will_hash_eventually <= a_very_long_name_which_we_will_hash_eventually + 1; if (a_very_long_name_which_we_will_hash_eventually == 5) begin fin(); end end task fin; $write("*-* All Finished *-*\n"); $finish; endtask endmodule verilator-5.042/test_regress/t/t_opt_table_enum.v0000644000542200017500000000164315101701376022601 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; enum { CASE_0 = 0, CASE_1 = 1, CASE_2 = 2, CASE_4 = 4, CASE_5 = 5, DEFAULT = 99 } e; reg [2:0] cyc; initial cyc = 0; always @(posedge clk) cyc <= cyc + 1; always @* begin case (cyc) 3'b000: e = CASE_0; 3'b001: e = CASE_1; 3'b010: e = CASE_2; 3'b100: e = CASE_4; 3'b101: e = CASE_5; default: e = DEFAULT; endcase end always @(posedge clk) begin $display("cyle %d = %d", cyc, e); if (cyc == 7) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_trace_ascendingrange_fst_sc.py0000755000542200017500000000177115101701376025463 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_ascendingrange.v" if not test.have_sc: test.skip("No SystemC installed") # CI environment offers 2 VCPUs, 2 thread setting causes the following warning. # %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. # Strangely, asking for more threads makes it go away. test.compile(verilator_flags2=['--sc --trace-fst --trace-params -Wno-ASCRANGE'], threads=(6 if test.vltmt else 1)) test.execute() test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_bind.py0000755000542200017500000000073415101701376020706 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_func_many_return.py0000755000542200017500000000101015101701376023334 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--comp-limit-blocks 100"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_sys_file_zero.v0000644000542200017500000000213015101701376022450 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t; int i; int v; string s; reg [100*8:1] letterl; initial begin // Display formatting $fwrite(0, "Never printed, file closed\n"); i = $feof(0); if (i == 0) $stop; $fflush(0); $fclose(0); i = $ferror(0, letterl); i = $fgetc(0); `checkd(i, -1); i = $ungetc(0, 0); `checkd(i, -1); i = $fgets(letterl, 0); `checkd(i, 0); i = $fscanf(0, "%x", v); `checkd(i, -1); i = $ftell(0); `checkd(i, -1); i = $rewind(0); `checkd(i, -1); i = $fseek(0, 10, 0); `checkd(i, -1); $write("*-* All Finished *-*\n"); $finish(0); // Test arguments to finish end endmodule verilator-5.042/test_regress/t/t_preproc_eof3_bad.out0000644000542200017500000000063115101701376023336 0ustar mahmoudyfreeshell%Error: t/t_preproc_eof3_bad.v:10:1: EOF in define argument list 10 | %Error-internal-contents-bad-ct2-ln10 | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_preproc_eof3_bad.v:10:1: Expecting ) or , to end argument list for define reference. Found: EOF 10 | %Error-internal-contents-bad-ct2-ln10 | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_unoptflat_simple_2_bad.py0000755000542200017500000000125315101701376024403 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_unoptflat_simple_2.v" # Compile only test.compile(verilator_flags3=[], verilator_flags2=["--report-unoptflat", "-fno-dfg"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_opt_dead_enumpkg.v0000644000542200017500000000104515101701376023105 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package pkg; typedef enum logic [2:0] { TWO = 2, THREE = 3 } enum_t; endpackage module t; localparam L_TWO = pkg::TWO; initial begin if (L_TWO != 2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_inst_dff.v0000644000542200017500000000656515101701376021410 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; localparam WIDTH = 31; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [WIDTH-1:0] b; // From test of Test.v wire [WIDTH-1:0] c; // From test of Test.v // End of automatics reg rst_l; Test #(.WIDTH(WIDTH)) test (/*AUTOINST*/ // Outputs .b (b[WIDTH-1:0]), .c (c[WIDTH-1:0]), // Inputs .clk (clk), .rst_l (rst_l), .in (in[WIDTH-1:0])); // Aggregate outputs into a single result vector wire [63:0] result = {1'h0, c, 1'b0, b}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; rst_l <= ~1'b1; end else if (cyc<10) begin sum <= 64'h0; rst_l <= ~1'b1; // Hold reset while summing end else if (cyc<20) begin rst_l <= ~1'b0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'hbcfcebdb75ec9d32 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs b, c, // Inputs clk, rst_l, in ); parameter WIDTH = 5; input clk; input rst_l; input [WIDTH-1:0] in; output wire [WIDTH-1:0] b; output wire [WIDTH-1:0] c; dff # ( .WIDTH (WIDTH), .RESET ('0), // Although this is a single bit, the parameter must be the specified type .RESET_WIDTH (1) ) sub1 ( .clk(clk), .rst_l(rst_l), .q(b), .d(in) ); dff # ( .WIDTH (WIDTH), .RESET ({ 1'b1, {(WIDTH-1){1'b0}} }), .RESET_WIDTH (WIDTH)) sub2 ( .clk(clk), .rst_l(rst_l), .q(c), .d(in) ); endmodule module dff (/*AUTOARG*/ // Outputs q, // Inputs clk, rst_l, d ); parameter WIDTH = 1; parameter RESET = {WIDTH{1'b0}}; parameter RESET_WIDTH = WIDTH; input clk; input rst_l; input [WIDTH-1:0] d; output reg [WIDTH-1:0] q; always_ff @(posedge clk or negedge rst_l) begin if ($bits(RESET) != RESET_WIDTH) $stop; // verilator lint_off WIDTH if (~rst_l) q <= RESET; // verilator lint_on WIDTH else q <= d; end endmodule verilator-5.042/test_regress/t/t_implements_new_bad.out0000644000542200017500000000055115101701376023777 0ustar mahmoudyfreeshell%Error: t/t_implements_new_bad.v:13:11: Illegal to call 'new' using an abstract virtual class 'Icls' (IEEE 1800-2023 8.21) : ... note: In instance 't' 13 | c = new; | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_xml_flat.out0000644000542200017500000001612615101701376021756 0ustar mahmoudyfreeshell verilator-5.042/test_regress/t/t_public_unpacked_port.v0000644000542200017500000000245215101701376023777 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2022 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 module sub ( output logic [31:0] sub_s1up_out[0:0] /* verilator public_flat_rw */, input logic sub_clk, input logic [31:0] sub_s1up_in[0:0] /* verilator public_flat_rw */ ); // Evaluate clock edges always @(posedge sub_clk) begin sub_s1up_out <= sub_s1up_in; end endmodule module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; logic [31:0] s1up_in[1]; logic [31:0] s1up_out[1]; sub the_sub ( .sub_s1up_in (s1up_in), .sub_s1up_out (s1up_out), .sub_clk (clk)); always_comb s1up_in[0] = cyc; always @(posedge clk) begin cyc <= cyc + 1; if (cyc == 10) begin if (s1up_out[0] != 9) begin $display("%%Error: got %0d instead of 9", s1up_out); $stop; end if (the_sub.sub_s1up_in[0] != 10) begin $display("%%Error: the_sub.sub_s1up_in was %0d instead of 10", the_sub.sub_s1up_in[0]); $stop; end $display("final cycle = %0d", cyc); $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_comb_input_2.v0000644000542200017500000000241215101701376022157 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2022 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VERILATOR // The '$c1(1)' is there to prevent inlining of the signal by V3Gate `define IMPURE_ONE ($c(1)) `else // Use standard $random (chaces of getting 2 consecutive zeroes is zero). `define IMPURE_ONE (|($random | $random)) `endif module top( clk, inc ); input clk; input [31:0] inc; // Cycle count reg [31:0] cyc = 0; /* verilator lint_off UNOPTFLAT */ // Circular combinational logic driven from primary input, but with the // cycle itself not involving the primary input wire [31:0] dup = `IMPURE_ONE ? inc : 32'd0; wire [31:0] feedback; wire [31:0] sum = cyc + dup + feedback; wire msb = sum[31]; // Always 0, but Verilator cannot know that assign feedback = {32{msb}}; always @(posedge clk) begin $display("cyc: %d sum: %d", cyc, sum); if (sum != 2*cyc + 1) $stop; cyc <= cyc + 1; if (cyc == 100) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_interface_mp_func.v0000644000542200017500000000157615101701376023260 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface pads_if(); modport mp_dig( import fIn, import fOut ); integer exists[8]; function automatic integer fIn (integer i); fIn = exists[i]; endfunction task automatic fOut (integer i); exists[i] = 33; endtask endinterface module t(); pads_if padsif[1:0](); pads_if padsif_arr[1:0](); initial begin padsif[0].fOut(3); if (padsif[0].fIn(3) != 33) $stop; padsif_arr[0].fOut(3); if (padsif_arr[0].fIn(3) != 33) $stop; padsif_arr[1].fOut(3); if (padsif_arr[1].fIn(3) != 33) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_display_wide_bad.v0000644000542200017500000000336415101701376023071 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [4095:0] crc; // Test loop always @ (posedge clk) begin cyc <= cyc + 1; crc <= {crc[4094:0], crc[63] ^ crc[2] ^ crc[0]}; // not a good crc :) if (cyc==0) begin // Setup crc <= 4096'h9f51804b5275c7b6ab9907144a58649bb778f9718062fa5c336fcc9edcad7cf17aad0a656244017bb21d9f97f7c0c147b6fa7488bb9d5bb8d3635b20fba1deab597121c502b21f49b18da998852d29a6b2b649315a3323a31e7e5f41e9bbb7e44046467438f37694857b963250bdb137a922cfce2af1defd1f93db5aa167f316d751bb274bda96fdee5e2c6eb21886633246b165341f0594c27697b06b62b1ad05ebe3c08909a54272de651296dcdd3d1774fc432d22210d8f6afa50b02cf23336f8cc3a0a2ebfd1a3a60366a1b66ef346e0379116d68caa01279ac2772d1f3cd76d2cbbc68ada6f83ec2441b2679b405486df8aa734ea1729b40c3f82210e8e42823eb3fd6ca77ee19f285741c4e8bac1ab7855c3138e84b6da1d897bbe37faf2d0256ad2f7ff9e704a63d824c1e97bddce990cae1578f9537ae2328d0afd69ffb317cbcf859696736e45e5c628b44727557c535a7d02c07907f2dccd6a21ca9ae9e1dbb1a135a8ebc2e0aa8c7329b898d02896273defe21beaa348e11165b71c48cf1c09714942a5a2ddc2adcb6e42c0f630117ee21205677d5128e8efc18c9a6f82a8475541fd722cca2dd829b7e78fef89dbeab63ab7b849910eb4fe675656c4b42b9452c81a4ca6296190a81dc63e6adfaa31995d7dfe3438ee9df66488d6cf569380569ffe6e5ea313d23af6ff08d979af29374ee9aff1fa143df238a1; end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%d\n", $time, cyc, {crc, crc, crc, crc}); // Too wide $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_class1.v0000644000542200017500000000165115101701376020771 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef class Cls; class Cls; int imembera; int imemberb; endclass : Cls module t; typedef Cls Cls2; initial begin Cls c; Cls2 c2; if (c != null) $stop; if (c) $stop; if (c2) $stop; $display("Display: null = \"%p\"", c); // null c = new; c2 = new; if (c == null) $stop; if (!c) $stop; if (!c2) $stop; $display("Display: newed = \"%p\"", c); // '{imembera:0, imemberb:0} c.imembera = 10; c.imemberb = 20; $display("Display: set = \"%p\"", c); // '{imembera:10, imemberb:20} if (c.imembera != 10) $stop; if (c.imemberb != 20) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_flag_csplit_eval.py0000755000542200017500000000161515101701376023267 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') def check_evals(): got = 0 for filename in test.glob_some(test.obj_dir + "/*.cpp"): wholefile = test.file_contents(filename) if re.search(r'__eval_nba__[0-9]+\(.*\)\s*{', wholefile): got += 1 if got < 2: test.error("Too few _eval functions found: " + str(got)) test.compile(v_flags2=["--output-split 1 --output-split-cfuncs 20"], verilator_make_gmake=False) # Slow to compile, so skip it) check_evals() test.passes() verilator-5.042/test_regress/t/t_sys_delta_monitor.py0000755000542200017500000000106115101701376023522 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary --timescale 1ns/1ns"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_trace_complex_structs_fst.out0000644000542200017500000001246115101701376025436 0ustar mahmoudyfreeshell$date Tue Jun 10 19:02:40 2025 $end $version fstWriter $end $timescale 1ps $end $scope module top $end $attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end $attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end $var wire 1 ! clk $end $scope module $unit $end $var bit 1 " global_bit $end $upscope $end $scope module t $end $var wire 1 ! clk $end $var integer 32 # cyc [31:0] $end $scope struct v_strp $end $var bit 1 $ b1 $end $var bit 1 % b0 $end $upscope $end $scope struct v_strp_strp $end $scope struct x1 $end $var bit 1 & b1 $end $var bit 1 ' b0 $end $upscope $end $scope struct x0 $end $var bit 1 ( b1 $end $var bit 1 ) b0 $end $upscope $end $upscope $end $scope union v_unip_strp $end $scope struct x1 $end $var bit 1 * b1 $end $var bit 1 + b0 $end $upscope $end $scope struct x0 $end $var bit 1 * b1 $end $var bit 1 + b0 $end $upscope $end $upscope $end $var bit 2 , v_arrp [2:1] $end $var bit 2 - v_arrp_arrp[3] [2:1] $end $var bit 2 . v_arrp_arrp[4] [2:1] $end $scope struct v_arrp_strp[3] $end $var bit 1 / b1 $end $var bit 1 0 b0 $end $upscope $end $scope struct v_arrp_strp[4] $end $var bit 1 1 b1 $end $var bit 1 2 b0 $end $upscope $end $var bit 1 3 v_arru[1] $end $var bit 1 4 v_arru[2] $end $var bit 1 5 v_arru_arru[3][1] $end $var bit 1 6 v_arru_arru[3][2] $end $var bit 1 7 v_arru_arru[4][1] $end $var bit 1 8 v_arru_arru[4][2] $end $var bit 2 9 v_arru_arrp[3] [2:1] $end $var bit 2 : v_arru_arrp[4] [2:1] $end $scope struct v_arru_strp[3] $end $var bit 1 ; b1 $end $var bit 1 < b0 $end $upscope $end $scope struct v_arru_strp[4] $end $var bit 1 = b1 $end $var bit 1 > b0 $end $upscope $end $var real 64 ? v_real $end $var real 64 @ v_arr_real[0] $end $var real 64 A v_arr_real[1] $end $var longint 64 B v_chandle [63:0] $end $scope struct v_str32x2[0] $end $var logic 32 C data [31:0] $end $upscope $end $scope struct v_str32x2[1] $end $var logic 32 D data [31:0] $end $upscope $end $attrbegin misc 07 "" 1 $end $var int 32 E v_enumed [31:0] $end $attrbegin misc 07 "" 1 $end $var int 32 F v_enumed2 [31:0] $end $attrbegin misc 07 "" 2 $end $var logic 3 G v_enumb [2:0] $end $scope struct v_enumb2_str $end $attrbegin misc 07 "" 2 $end $var logic 3 H a [2:0] $end $attrbegin misc 07 "" 2 $end $var logic 3 I b [2:0] $end $upscope $end $var logic 8 J unpacked_array[-2] [7:0] $end $var logic 8 K unpacked_array[-1] [7:0] $end $var logic 8 L unpacked_array[0] [7:0] $end $var bit 1 M LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end $scope module unnamedblk1 $end $var integer 32 N b [31:0] $end $scope module unnamedblk2 $end $var integer 32 O a [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b00000000000000000000000000000000 O b00000000000000000000000000000000 N 0M b00000000 L b00000000 K b00000000 J b000 I b000 H b000 G b00000000000000000000000000000000 F b00000000000000000000000000000000 E b00000000000000000000000000000000 D b00000000000000000000000011111111 C b0000000000000000000000000000000000000000000000000000000000000000 B r0 A r0 @ r0 ? 0> 0= 0< 0; b00 : b00 9 08 07 06 05 04 03 02 01 00 0/ b00 . b00 - b00 , 0+ 0* 0) 0( 0' 0& 0% 0$ b00000000000000000000000000000000 # 1" 0! $end #10 1! b00000000000000000000000000000001 # 1$ 1% 1& 1' 1( 1) 1* 1+ b11 , b11 - b11 . 1/ 10 11 12 b11 9 b11 : 1; 1< 1= 1> r0.1 ? r0.2 @ r0.3 A b00000000000000000000000011111110 C b00000000000000000000000000000001 D b00000000000000000000000000000001 E b00000000000000000000000000000010 F b111 G b00000000000000000000000000000101 N b00000000000000000000000000000101 O #15 0! #20 1! b110 G b00000000000000000000000000000100 F b00000000000000000000000000000010 E b00000000000000000000000000000010 D b00000000000000000000000011111101 C r0.6 A r0.4 @ r0.2 ? 0> 0= 0< 0; b00 : b00 9 02 01 00 0/ b00 . b00 - b00 , 0+ 0* 0) 0( 0' 0& 0% 0$ b00000000000000000000000000000010 # b111 H b111 I #25 0! #30 1! b110 I b110 H b00000000000000000000000000000011 # 1$ 1% 1& 1' 1( 1) 1* 1+ b11 , b11 - b11 . 1/ 10 11 12 b11 9 b11 : 1; 1< 1= 1> r0.3 ? r0.6000000000000001 @ r0.8999999999999999 A b00000000000000000000000011111100 C b00000000000000000000000000000011 D b00000000000000000000000000000011 E b00000000000000000000000000000110 F b101 G #35 0! #40 1! b100 G b00000000000000000000000000001000 F b00000000000000000000000000000100 E b00000000000000000000000000000100 D b00000000000000000000000011111011 C r1.2 A r0.8 @ r0.4 ? 0> 0= 0< 0; b00 : b00 9 02 01 00 0/ b00 . b00 - b00 , 0+ 0* 0) 0( 0' 0& 0% 0$ b00000000000000000000000000000100 # b101 H b101 I #45 0! #50 1! b100 I b100 H b00000000000000000000000000000101 # 1$ 1% 1& 1' 1( 1) 1* 1+ b11 , b11 - b11 . 1/ 10 11 12 b11 9 b11 : 1; 1< 1= 1> r0.5 ? r1 @ r1.5 A b00000000000000000000000011111010 C b00000000000000000000000000000101 D b00000000000000000000000000000101 E b00000000000000000000000000001010 F b011 G #55 0! #60 1! b010 G b00000000000000000000000000001100 F b00000000000000000000000000000110 E b00000000000000000000000000000110 D b00000000000000000000000011111001 C r1.8 A r1.2 @ r0.6 ? 0> 0= 0< 0; b00 : b00 9 02 01 00 0/ b00 . b00 - b00 , 0+ 0* 0) 0( 0' 0& 0% 0$ b00000000000000000000000000000110 # b011 H b011 I verilator-5.042/test_regress/t/t_unopt_converge_run_bad.py0000755000542200017500000000124715101701376024521 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_unopt_converge.v" test.compile( v_flags2=['+define+ALLOW_UNOPT', '--output-split 0', '-fno-dfg', '--converge-limit 5']) if test.vlt_all: test.execute(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface1.v0000644000542200017500000000156415101701376021627 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Very simple test for interface pathclearing interface ifc; logic [3:0] value; endinterface module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=1; ifc itop(); sub c1 (.isub(itop), .i_value(4'h4)); always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==20) begin if (c1.i_value != 4) $stop; // 'Normal' crossref just for comparison if (itop.value != 4) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module sub ( ifc isub, input logic [3:0] i_value ); always @* begin isub.value = i_value; end endmodule : sub verilator-5.042/test_regress/t/t_alw_reorder.v0000644000542200017500000000271215101701376022107 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg [15:0] m_din; reg [15:0] v1; reg [15:0] v2; reg [15:0] v3; integer nosplit; always @ (posedge clk) begin // write needed so that V3Dead doesn't kill v0..v3 $write(" values %x %x %x\n", v1, v2, v3); // Locally-set 'nosplit' will prevent the if from splitting // in splitAlwaysAll(). This whole always block should still be // intact when we call splitReorderAll() which is the subject // of this test. nosplit = cyc; if (nosplit > 2) begin /* S1 */ v1 <= 16'h0; /* S2 */ v1 <= m_din; /* S3 */ if (m_din == 16'h0) begin /* X1 */ v2 <= v1; /* X2 */ v3 <= v2; end end // We expect to swap S2 and S3, and to swap X1 and X2. // We can check that this worked by the absense of dly vars // in the generated output; if the reorder fails (or is disabled) // we should see dly vars for v1 and v2. end always @ (posedge clk) begin if (cyc!=0) begin cyc<=cyc+1; if (cyc==7) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.042/test_regress/t/t_inst_dtree.v0000644000542200017500000000273115101701376021743 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; `ifdef INLINE_A //verilator inline_module `else //verilator no_inline_module `endif bmod bsub3 (.clk, .n(3)); bmod bsub2 (.clk, .n(2)); bmod bsub1 (.clk, .n(1)); bmod bsub0 (.clk, .n(0)); endmodule module bmod (input clk, input [31:0] n); `ifdef INLINE_B //verilator inline_module `else //verilator no_inline_module `endif cmod csub (.clk, .n); endmodule module cmod (input clk, input [31:0] n); `ifdef INLINE_C //verilator inline_module `else //verilator no_inline_module `endif reg [31:0] clocal; always @ (posedge clk) clocal <= n; dmod dsub (.clk, .n); endmodule module dmod (input clk, input [31:0] n); `ifdef INLINE_D //verilator inline_module `else //verilator no_inline_module `endif reg [31:0] dlocal; always @ (posedge clk) dlocal <= n; int cyc; always @(posedge clk) begin cyc <= cyc+1; end always @(posedge clk) begin if (cyc>10) begin `ifdef TEST_VERBOSE $display("%m: csub.clocal=%0d dlocal=%0d", csub.clocal, dlocal); `endif if (csub.clocal !== n) $stop; if (dlocal !== n) $stop; end if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_vpi_public_depthn.v0000644000542200017500000000176115101701376023303 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface AXIS_IF ( input logic aclk ); logic [127:0] tdata; logic [ 31:0] tuser; logic tvalid, tready; modport master(input aclk, output tdata, tuser, tvalid, input tready); modport slave(input aclk, input tdata, tuser, tvalid, output tready); endinterface : AXIS_IF module sub ( input clk, AXIS_IF.slave s_axis_if ); assign s_axis_if.tready = s_axis_if.tdata[0]; endmodule module dut ( input clk, AXIS_IF.slave s_axis_if ); sub u_sub(.*); endmodule module t(/*AUTOARG*/ // Inputs clk ); input clk; AXIS_IF s_axis_if (.aclk(clk)); dut u_dut (.clk, .s_axis_if(s_axis_if)); initial begin $c("Verilated::scopesDump();"); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_lint_block_redecl_bad.py0000755000542200017500000000076315101701376024240 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_queue_empty_pin.v0000644000542200017500000000061315101701376023010 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; task tsk(int q[] = {}); if (q.size != 0) $stop; endtask initial begin tsk(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_param.v0000644000542200017500000000337615101701376020711 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); parameter PAR = 3; m1 #(PAR) m1(); m3 #(PAR) m3(); mnooverride #(10) mno(); mreal #1.2 mr(); input clk; integer cyc=1; reg [4:0] bitsel; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==0) begin bitsel = 0; if (PAR[bitsel]!==1'b1) $stop; bitsel = 1; if (PAR[bitsel]!==1'b1) $stop; bitsel = 2; if (PAR[bitsel]!==1'b0) $stop; end if (cyc==1) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module m1; localparam PAR1MINUS1 = PAR1DUP-2-1; localparam PAR1DUP = PAR1+2; // Check we propagate parameters properly parameter PAR1 = 0; m2 #(PAR1MINUS1) m2 (); // Packed arrays localparam [1:0][3:0] PACKED_PARAM = { 4'h3, 4'h6 }; initial if (PACKED_PARAM != 8'h36) $stop; endmodule // See issue #810 module m2 #(/*parameter*/ integer PAR2 = 10); initial begin $display("%x",PAR2); if (PAR2 !== 2) $stop; end endmodule module m3; localparam LOC = 13; parameter PAR = 10; initial begin $display("%x %x",LOC,PAR); if (LOC !== 13) $stop; if (PAR !== 3) $stop; end endmodule module mnooverride; localparam LOC = 13; parameter PAR = 10; initial begin $display("%x %x",LOC,PAR); if (LOC !== 13) $stop; if (PAR !== 10) $stop; end endmodule module mreal; parameter real REAL = 99.99; initial begin $display("%f", REAL); if (REAL !== 1.2) $stop; end endmodule verilator-5.042/test_regress/t/t_sys_writemem.gold5.mem0000644000542200017500000000036015101701376023650 0ustar mahmoudyfreeshell00000000000000 00000000000000 00000000000000 00000000000000 dcba9876540004 00000000000000 00000000000000 00000000000000 00000000000000 00000000000000 dcba987654000a dcba987654000b dcba987654000c 00000000000000 00000000000000 00000000000000 verilator-5.042/test_regress/t/t_interface_modport_export.py0000755000542200017500000000105515101701376025074 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) if not test.vlt_all: test.execute() test.passes() verilator-5.042/test_regress/t/t_clocking_bad1.py0000755000542200017500000000102515101701376022444 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["--timing"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_clocking_unsup1.v0000644000542200017500000000063515101701376022710 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; clocking cb @(posedge clk); output posedge #1 a; output negedge #1 b; output edge #1 b; endclocking endmodule verilator-5.042/test_regress/t/t_emit_accessors.v0000644000542200017500000000077115101701376022610 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t_emit_accessors( input bit in1, input bit in2, input logic [31:0] in3, input logic [31:0] in4, output bit out1, output logic [31:0] out2, output logic [77:0] out3 ); assign out1 = in1 & in2; assign out2 = in3 & in4; assign out3 = 1; endmodule verilator-5.042/test_regress/t/t_vpi_release_dup_bad.v0000644000542200017500000000060115101701376023551 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under The Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 import "DPI-C" context function void dpii_check(); module t; initial begin dpii_check(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_preproc_eof3_bad.py0000755000542200017500000000102515101701376023160 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, verilator_flags2=['--no-std'], expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_trace_array_fst_threads_2_sc.py0000755000542200017500000000141515101701376025557 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_trace_array.v" test.golden_filename = "t/t_trace_array_fst_sc.out" if not test.have_sc: test.skip("No SystemC installed") test.compile( verilator_flags2=['--sc --trace-fst --trace-threads 2 --trace-structs --trace-max-width 0']) test.execute() test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_randomize_inline_var_ctl_unsup_1.out0000644000542200017500000000177315101701376026664 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_randomize_inline_var_ctl_unsup_1.v:20:37: Unsupported: Non-variable expression as 'randomize()' argument : ... note: In instance 't' 20 | void'(foo.randomize(Foo::get().x)); | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_randomize_inline_var_ctl_unsup_1.v:21:34: Unsupported: Non-variable expression as 'randomize()' argument : ... note: In instance 't' 21 | void'(foo.randomize(foos[0].x)); | ^ %Error-UNSUPPORTED: t/t_randomize_inline_var_ctl_unsup_1.v:22:27: Unsupported: 'randomize(null)' : ... note: In instance 't' 22 | void'(foo.randomize(null)); | ^~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_tri_top_en_out.v0000644000542200017500000001615715101701376022643 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Paul Wright. // SPDX-License-Identifier: CC0-1.0 // A submodule to ensure that __en and __out propagate upwards module t_sub_io ( inout my_io, input drv_en, input op_val ); timeunit 1ns; timeprecision 1ps; assign my_io = drv_en ? op_val : 1'bz; endmodule `ifndef T_TRI_TOP_NAME `define T_TRI_TOP_NAME t_tri_top_en_out `endif // The top module // __en and __out should be added for the inout ports module `T_TRI_TOP_NAME ( inout single_bit_io, inout bidir_single_bit_io, inout [63:0] bus_64_io, inout [63:0] bidir_bus_64_io, inout [127:0] bus_128_io, inout [127:0] bidir_bus_128_io, input [3:0] drv_en, input test_en, output logic loop_done, inout sub_io ); timeunit 1ns; timeprecision 1ps; bit rand_bit; assign single_bit_io = 1'bz; assign bidir_single_bit_io = drv_en[0] ? rand_bit : 1'bz; assign bus_64_io = {64{1'bz}}; assign bidir_bus_64_io[15:0] = drv_en[0] ? {16{rand_bit}} : {16{1'bz}}; assign bidir_bus_64_io[31:16] = drv_en[1] ? {16{rand_bit}} : {16{1'bz}}; assign bidir_bus_64_io[47:32] = drv_en[2] ? {16{rand_bit}} : {16{1'bz}}; assign bidir_bus_64_io[63:48] = drv_en[3] ? {16{rand_bit}} : {16{1'bz}}; assign bus_128_io = {128{1'bz}}; assign bidir_bus_128_io[31:0] = drv_en[0] ? {32{rand_bit}} : {32{1'bz}}; assign bidir_bus_128_io[63:32] = drv_en[1] ? {32{rand_bit}} : {32{1'bz}}; assign bidir_bus_128_io[95:64] = drv_en[2] ? {32{rand_bit}} : {32{1'bz}}; assign bidir_bus_128_io[127:96] = drv_en[3] ? {32{rand_bit}} : {32{1'bz}}; int loop_cnt; int error_cnt; initial begin : init_error error_cnt = 'd0; end initial begin : test_and_loop loop_cnt = 0; #(1ps); while (test_en == 1) begin loop_done = 0; rand_bit = (($urandom_range(1,0) & 'd1) == 'd1); chk_sigs; #(1ns) $display("Info:(v): 1ns"); rand_bit = ~rand_bit; chk_sigs; #(1ns) $display("Info:(v): 2ns"); rand_bit = ~rand_bit; chk_sigs; #(1ns); loop_done = 1; loop_cnt++; #(1ps); end if (error_cnt == 'd0) begin $display("Info:(v): Error count was = %0d", error_cnt); $write("*-* All Finished *-*\n"); end else begin $display("Info:(v): Error count was non-zero %0d", error_cnt); end $finish(1); end always @(loop_cnt) begin if (loop_cnt > 32) begin $display("%%Error:(v): Excessive loop count"); $display("drv_en = %b, test_en = %b", drv_en, test_en); $finish(1); end end final begin $display("Info:(v): All done at %t", $time); $display("Info:(v): Error count = %0d", error_cnt); chk_err: assert(error_cnt == 0); end wire internal_sub_io; logic [15:0] my_64_segment; logic [31:0] my_128_segment; task chk_sigs; begin #(1ps); $display("Info:(v): rand_bit = %b", rand_bit); if (|drv_en) begin $display("Info:(v): drv_en = %b", drv_en); $display("Info:(v): bidir_single_bit_io = %b", bidir_single_bit_io); $display("Info:(v): bidir_bus_64_io = %b,%b,%b,%b", bidir_bus_64_io[63:48], bidir_bus_64_io[47:32], bidir_bus_64_io[31:16],bidir_bus_64_io[15:0]); $display("Info:(v): bidir_bus_128_io = %b,%b,%b,%b", bidir_bus_128_io[127:96], bidir_bus_128_io[95:64], bidir_bus_128_io[63:32], bidir_bus_128_io[31:0]); for (int i=0;i<4;i++) begin if (drv_en[0]) begin if (bidir_single_bit_io !== rand_bit) begin $display("%%Error:(v): bidir_single_bit_io is wrong (expect %b got %b)", rand_bit, bidir_single_bit_io); error_cnt++; end if (sub_io !== rand_bit) begin $display("%%Error:(v): sub_io is wrong (expect %b, got %b)", rand_bit, sub_io); end end if (drv_en[1]) begin if (internal_sub_io !== ~rand_bit) begin $display("%%Error:(v): sub_io is wrong"); error_cnt++; end end if (drv_en[i]) begin int msb, lsb; msb = ((i+1)*16-1); lsb = i*16; case(i) 'd0: my_64_segment = bidir_bus_64_io[15:0]; 'd1: my_64_segment = bidir_bus_64_io[31:16]; 'd2: my_64_segment = bidir_bus_64_io[47:32]; default: my_64_segment = bidir_bus_64_io[63:48]; endcase case(i) 'd0: my_128_segment = bidir_bus_128_io[31:0]; 'd1: my_128_segment = bidir_bus_128_io[63:32]; 'd2: my_128_segment = bidir_bus_128_io[95:64]; default: my_128_segment = bidir_bus_128_io[127:96]; endcase if (my_64_segment !== {16{rand_bit}}) begin $display("%%Error:(v): bidir_bus_64_io is wrong"); $display("Error:(v): Should be bidir_bus_64_io[%0d:%0d] = %b, was = %b", msb, lsb, {16{rand_bit}}, my_64_segment); error_cnt++; end else begin $display("Info:(v): Pass: bidir_bus_64_io[%0d:%0d] = %b", msb, lsb, {16{rand_bit}}); end msb = ((i+1)*32-1); lsb = i*32; if (my_128_segment !== {32{rand_bit}}) begin $display("%%Error:(v): bidir_bus_128_io is wrong"); $display("Error:(v):Should be bidir_bus_128_io[%0d:%0d] = %b, was = %b", msb, lsb, {32{rand_bit}}, my_128_segment); error_cnt++; end else begin $display("Info:(v): Pass: bidir_bus_128_io[%0d:%0d] = %b", msb, lsb, {32{rand_bit}}); end end end end end endtask // Connects to top level t_sub_io t_sub_io ( .my_io (sub_io), .drv_en (drv_en[0]), .op_val (rand_bit) ); // Does not connect to top-level t_sub_io t_sub_io_internal ( .my_io (internal_sub_io), .drv_en (drv_en[1]), .op_val (~rand_bit) ); endmodule verilator-5.042/test_regress/t/t_struct_unpacked_init.out0000644000542200017500000000056615101701376024372 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_struct_unpacked_init.v:12:24: Unsupported: Initial values in struct/union members : ... note: In instance 't' 12 | bit [3:0] m_lo = P; | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_constraint_before_randc_bad.out0000644000542200017500000000104615101701376025626 0ustar mahmoudyfreeshell%Error: t/t_constraint_before_randc_bad.v:11:45: Randc variables not allowed in 'solve before' (IEEE 1800-2023 18.5.9) 11 | constraint raint2_bad { solve b1 before b2; } | ^~ t/t_constraint_before_randc_bad.v:11:29: ... Location of restricting expression 11 | constraint raint2_bad { solve b1 before b2; } | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_assign_inline.v0000644000542200017500000000212415101701376022421 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Mike Thyer. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; int cycle=0; // verilator lint_off UNOPTFLAT reg [7:0] a_r; wire [7:0] a_w; reg [7:0] b_r; reg [7:0] c_d_r, c_q_r; assign a_w = a_r; always @(*) begin a_r = 0; b_r = a_w; // Substituting the a_w assignment to get b_r = 0 is wrong, as a_r is not "complete" a_r = c_q_r; c_d_r = c_q_r; end // stimulus + checks always @(posedge clk) begin cycle <= cycle+1; if (cycle==0) begin c_q_r <= 8'b0; end else begin c_q_r <= c_d_r+1; `ifdef TEST_VERBOSE $display("[%0t] a_r=%0d, b_r=%0d", $time, a_r, b_r); // a_r and b_r should always be the same `endif end if (cycle >= 10) begin if (b_r==9) begin $write("*-* All Finished *-*\n"); $finish; end else begin $stop; end end end endmodule verilator-5.042/test_regress/t/t_lib_prot_secret.py0000755000542200017500000000137615101701376023154 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["--protect-lib", "secret", "--protect-key", "SECRET_FAKE_KEY"], verilator_make_gcc=False, verilator_make_gmake=False, make_main=False, make_top_shell=False) test.run(cmd=[os.environ["MAKE"], "-C", test.obj_dir, "-f", "V" + test.name + ".mk"]) test.passes() verilator-5.042/test_regress/t/t_process_kill.v0000644000542200017500000000106415101701376022272 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; process p; initial begin wait (p); p.kill(); p.await(); $write("*-* All Finished *-*\n"); $finish; end always @(posedge clk) begin if (!p) begin p = process::self(); end else begin $stop; end end endmodule verilator-5.042/test_regress/t/t_var_dup2.py0000755000542200017500000000070615101701376021513 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.042/test_regress/t/t_attr.py0000755000542200017500000000070315101701376020740 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint() test.passes() verilator-5.042/test_regress/t/t_lint_modmissing.py0000755000542200017500000000070315101701376023165 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint() test.passes() verilator-5.042/test_regress/t/t_hier_block_type_param_multiple.py0000755000542200017500000000077715101701376026236 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--hierarchical']) test.execute() test.passes() verilator-5.042/test_regress/t/t_dfg_multidriver_non_dfg.py0000755000542200017500000000070615101701376024651 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.passes() verilator-5.042/test_regress/t/t_dpi_vams.v0000644000542200017500000000105515101701376021403 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 //`begin_keywords "VAMS-2.3" `begin_keywords "1800+VAMS" module t (/*AUTOARG*/ // Outputs out, // Inputs in ); input in; wreal in; output out; wreal out; import "DPI-C" context function void dpii_call(input real in, output real out); initial begin dpii_call(in,out); $finish; end endmodule verilator-5.042/test_regress/t/t_order_loop_bad.v0000644000542200017500000000162115101701376022552 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Non-cutable edge in loop // // This code (stripped down from a much larger application) has a loop between // the use of ready in the first two always blocks. However it should // trivially trigger the $write on the first clk posedge. // // This is a regression test against issue #513. // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Jeremy Bennett. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg ready; initial begin ready = 1'b0; end always @(posedge ready) begin if ((ready === 1'b1)) begin $write("*-* All Finished *-*\n"); $finish; end end always @(posedge ready) begin if ((ready === 1'b0)) begin ready = 1'b1 ; end end always @(posedge clk) begin ready = 1'b1; end endmodule verilator-5.042/test_regress/t/t_mod_dup_bad_lib.v0000644000542200017500000000047615101701376022672 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module a(); endmodule module test(); a a(); endmodule module a(); endmodule module b(); endmodule verilator-5.042/test_regress/t/t_std_pkg_bad.v0000644000542200017500000000040215101701376022035 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 package std; endpackage module t; endmodule verilator-5.042/test_regress/t/t_trace_saif_sc.out0000755000542200017500000011061215101701376022733 0ustar mahmoudyfreeshell// Generated by verilated_saif (SAIFILE (SAIFVERSION "2.0") (DIRECTION "backward") (PROGRAM_NAME "Verilator") (DIVIDER / ) (TIMESCALE 1ps) (DURATION 1004) (INSTANCE top (INSTANCE t (NET (clk (T0 505) (T1 499) (TZ 0) (TX 0) (TB 0) (TC 199)) (cyc\[0\] (T0 504) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 100)) (cyc\[1\] (T0 504) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 50)) (cyc\[2\] (T0 520) (T1 484) (TZ 0) (TX 0) (TB 0) (TC 25)) (cyc\[3\] (T0 524) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 12)) (cyc\[4\] (T0 524) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 6)) (cyc\[5\] (T0 640) (T1 364) (TZ 0) (TX 0) (TB 0) (TC 3)) (cyc\[6\] (T0 640) (T1 364) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[7\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (rstn (T0 110) (T1 894) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_gparam_real\[0\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[1\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[2\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[3\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[4\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[5\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[6\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[7\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[8\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[9\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[10\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[11\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[12\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[13\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[14\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[15\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[16\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[17\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[18\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[19\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[20\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[21\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[22\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[23\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[24\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[25\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[26\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[27\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[28\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[29\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[30\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[31\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[32\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[33\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[34\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[35\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[36\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[37\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[38\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[39\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[40\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[41\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[42\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[43\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[44\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[45\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[46\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[47\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[48\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[49\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[50\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[51\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[52\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[53\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[54\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[55\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[56\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[57\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[58\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[59\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[60\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[61\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[62\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_gparam_real\[63\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[0\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[1\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[2\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[3\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[4\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[5\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[6\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[7\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[8\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[9\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[10\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[11\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[12\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[13\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[14\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[15\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[16\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[17\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[18\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[19\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[20\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[21\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[22\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[23\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[24\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[25\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[26\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[27\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[28\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[29\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[30\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[31\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[32\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[33\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[34\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[35\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[36\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[37\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[38\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[39\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[40\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[41\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[42\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[43\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[44\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[45\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[46\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[47\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[48\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[49\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[50\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[51\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[52\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[53\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[54\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[55\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[56\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[57\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[58\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[59\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[60\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[61\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[62\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam_real\[63\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[0\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[1\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[2\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[3\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[4\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[5\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[6\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[7\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[8\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[9\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[10\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[11\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[12\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[13\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[14\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[15\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[16\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[17\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[18\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[19\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[20\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[21\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[22\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[23\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[24\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[25\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[26\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[27\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[28\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[29\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[30\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[31\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[32\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[33\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[34\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[35\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[36\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[37\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[38\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[39\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[40\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[41\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[42\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[43\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[44\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[45\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[46\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[47\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[48\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[49\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[50\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[51\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[52\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[53\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[54\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[55\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[56\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[57\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[58\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[59\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[60\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[61\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[62\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_real\[63\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[0\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[1\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[2\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[3\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[4\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[5\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[6\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[7\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[8\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[9\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[10\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[11\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[12\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[13\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[14\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[15\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[16\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[17\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[18\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[19\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[20\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[21\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[22\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[23\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[24\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[25\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[26\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[27\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[28\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[29\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[30\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_integer\[31\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_bit (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_logic (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[0\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[1\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[2\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[3\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[4\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[5\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[6\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[7\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[8\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[9\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[10\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[11\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[12\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[13\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[14\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[15\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[16\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[17\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[18\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[19\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[20\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[21\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[22\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[23\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[24\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[25\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[26\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[27\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[28\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[29\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[30\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_int\[31\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[0\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[1\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[2\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[3\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[4\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[5\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[6\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[7\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[8\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[9\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[10\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[11\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[12\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[13\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[14\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_shortint\[15\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[0\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[1\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[2\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[3\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[4\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[5\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[6\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[7\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[8\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[9\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[10\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[11\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[12\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[13\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[14\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[15\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[16\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[17\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[18\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[19\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[20\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[21\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[22\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[23\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[24\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[25\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[26\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[27\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[28\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[29\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[30\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[31\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[32\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[33\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[34\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[35\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[36\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[37\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[38\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[39\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[40\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[41\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[42\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[43\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[44\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[45\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[46\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[47\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[48\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[49\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[50\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[51\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[52\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[53\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[54\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[55\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[56\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[57\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[58\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[59\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[60\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[61\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[62\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_longint\[63\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_byte\[0\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_byte\[1\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_byte\[2\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_byte\[3\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_byte\[4\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_byte\[5\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_byte\[6\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_byte\[7\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[0\] (T0 0) (T1 1004) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_parameter\[1\] (T0 0) (T1 1004) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_parameter\[2\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[3\] (T0 0) (T1 1004) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_parameter\[4\] (T0 0) (T1 1004) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_parameter\[5\] (T0 0) (T1 1004) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_parameter\[6\] (T0 0) (T1 1004) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_parameter\[7\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[8\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[9\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[10\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[11\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[12\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[13\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[14\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[15\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[16\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[17\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[18\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[19\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[20\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[21\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[22\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[23\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[24\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[25\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[26\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[27\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[28\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[29\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[30\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_parameter\[31\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[0\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[1\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[2\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[3\] (T0 0) (T1 1004) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_lparam\[4\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[5\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[6\] (T0 0) (T1 1004) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_lparam\[7\] (T0 0) (T1 1004) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_lparam\[8\] (T0 0) (T1 1004) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_lparam\[9\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[10\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[11\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[12\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[13\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[14\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[15\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[16\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[17\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[18\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[19\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[20\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[21\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[22\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[23\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[24\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[25\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[26\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[27\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[28\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[29\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[30\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_lparam\[31\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_supply0 (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_supply1 (T0 0) (T1 1004) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_tri0 (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_tri1 (T0 0) (T1 1004) (TZ 0) (TX 0) (TB 0) (TC 1)) (fst_tri (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (fst_wire (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (state\[0\] (T0 414) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46)) (state\[1\] (T0 540) (T1 464) (TZ 0) (TX 0) (TB 0) (TC 45)) (state\[2\] (T0 534) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state\[3\] (T0 544) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44)) (state\[4\] (T0 540) (T1 464) (TZ 0) (TX 0) (TB 0) (TC 45)) ) (INSTANCE test (NET (clk (T0 505) (T1 499) (TZ 0) (TX 0) (TB 0) (TC 199)) (rstn (T0 110) (T1 894) (TZ 0) (TX 0) (TB 0) (TC 1)) (state\[0\] (T0 414) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46)) (state\[1\] (T0 540) (T1 464) (TZ 0) (TX 0) (TB 0) (TC 45)) (state\[2\] (T0 534) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state\[3\] (T0 544) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44)) (state\[4\] (T0 540) (T1 464) (TZ 0) (TX 0) (TB 0) (TC 45)) (state_w\[0\] (T0 534) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_w\[1\] (T0 534) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_w\[2\] (T0 434) (T1 570) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_w\[3\] (T0 530) (T1 474) (TZ 0) (TX 0) (TB 0) (TC 47)) (state_w\[4\] (T0 424) (T1 580) (TZ 0) (TX 0) (TB 0) (TC 48)) (state_array[0]\[0\] (T0 414) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_array[0]\[1\] (T0 540) (T1 464) (TZ 0) (TX 0) (TB 0) (TC 45)) (state_array[0]\[2\] (T0 534) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_array[0]\[3\] (T0 544) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44)) (state_array[0]\[4\] (T0 540) (T1 464) (TZ 0) (TX 0) (TB 0) (TC 45)) (state_array[1]\[0\] (T0 420) (T1 584) (TZ 0) (TX 0) (TB 0) (TC 47)) (state_array[1]\[1\] (T0 534) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_array[1]\[2\] (T0 534) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_array[1]\[3\] (T0 540) (T1 464) (TZ 0) (TX 0) (TB 0) (TC 45)) (state_array[1]\[4\] (T0 534) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_array[2]\[0\] (T0 424) (T1 580) (TZ 0) (TX 0) (TB 0) (TC 48)) (state_array[2]\[1\] (T0 534) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_array[2]\[2\] (T0 534) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_array[2]\[3\] (T0 534) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_array[2]\[4\] (T0 530) (T1 474) (TZ 0) (TX 0) (TB 0) (TC 47)) ) (INSTANCE unnamedblk1 (NET (i\[0\] (T0 10) (T1 994) (TZ 0) (TX 0) (TB 0) (TC 1)) (i\[1\] (T0 10) (T1 994) (TZ 0) (TX 0) (TB 0) (TC 1)) (i\[2\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[3\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[4\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[5\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[6\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[7\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[8\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[9\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[10\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[11\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[12\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[13\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[14\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[15\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[16\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[17\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[18\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[19\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[20\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[21\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[22\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[23\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[24\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[25\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[26\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[27\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[28\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[29\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[30\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[31\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE unnamedblk2 (NET (i\[0\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[1\] (T0 120) (T1 884) (TZ 0) (TX 0) (TB 0) (TC 1)) (i\[2\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[3\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[4\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[5\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[6\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[7\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[8\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[9\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[10\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[11\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[12\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[13\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[14\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[15\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[16\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[17\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[18\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[19\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[20\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[21\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[22\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[23\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[24\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[25\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[26\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[27\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[28\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[29\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[30\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (i\[31\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) ) ) verilator-5.042/test_regress/t/t_unoptflat_simple_3_bad.out0000644000542200017500000000144515101701376024563 0ustar mahmoudyfreeshell%Warning-UNOPTFLAT: t/t_unoptflat_simple_3.v:16:15: Signal unoptimizable: Circular combinational logic: 't.x' 16 | wire [2:0] x; | ^ ... For warning description see https://verilator.org/warn/UNOPTFLAT?v=latest ... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message. t/t_unoptflat_simple_3.v:16:15: Example path: t.x t/t_unoptflat_simple_3.v:55:19: Example path: ASSIGNW t/t_unoptflat_simple_3.v:53:22: Example path: t.__Vcellout__test1i__xvecout t/t_unoptflat_simple_3.v:20:20: Example path: ASSIGNW t/t_unoptflat_simple_3.v:16:15: Example path: t.x %Error: Exiting due to verilator-5.042/test_regress/t/t_interface_gen12.py0000755000542200017500000000073415101701376022726 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_case_huge_nocase.py0000755000542200017500000000117015101701376023240 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.top_filename = 't/t_case_huge.v' test.compile(verilator_flags2=["--stats -fno-case"]) test.execute() test.file_grep(test.stats, r'Optimizations, Cases parallelized\s+(\d+)', 0) test.passes() verilator-5.042/test_regress/t/t_property_named.v0000644000542200017500000000422615101701376022634 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ clk ); input clk; int cyc = 0; logic val = 0; always @(posedge clk) begin cyc <= cyc + 1; val = ~val; end property check(int cyc_mod_2, logic expected); @(posedge clk) cyc % 2 == cyc_mod_2 |=> val == expected; endproperty // Also checks parsing 'var datatype' property check_if_1(var int cyc_mod_2); check(cyc_mod_2, 1); endproperty // Also checks parsing 'signing range' property check_if_gt_5(signed [31:0] cyc); @(posedge clk) cyc > 5; endproperty property pass_assertion(int cyc); disable iff (cyc <= 10) cyc > 10; endproperty int expected_fails = 0; assert property(check(0, 1)) else begin // Assertion should pass $display("[%0t] Assert failed, but shouldn't", $time); $stop; end assert property(check(1, 1)) else begin // Assertion should fail expected_fails += 1; end assert property(check_if_1(1)) else begin // Assertion should fail expected_fails += 1; end logic out = 1; property prop_a; @(posedge clk) disable iff (cyc <= 1) out; endproperty : prop_a property prop_b(); @(posedge clk) disable iff (cyc <= 1) out; endproperty : prop_b assert property(disable iff (cyc < 5) check_if_gt_5(cyc + 1)); assert property(@(posedge clk) pass_assertion(cyc)); assert property (prop_a) else $error($sformatf("property check failed :assert: (False)")); assert property (prop_a()) else $error($sformatf("property check failed :assert: (False)")); assert property (prop_b) else $error($sformatf("property check failed :assert: (False)")); assert property (prop_b()) else $error($sformatf("property check failed :assert: (False)")); always @(posedge clk) begin if (expected_fails == 2) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_func_task_bad.v0000644000542200017500000000056115101701376022365 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin if (a_task(1'b0)) $stop; // <--- Bad: Calling task _as_ function end task a_task; input ign; endtask endmodule verilator-5.042/test_regress/t/t_assert_implication.v0000644000542200017500000000471515101701376023500 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Peter Monsson. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; Test test (/*AUTOINST*/ // Inputs .clk(clk), .cyc(cyc)); always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; `ifdef TEST_VERBOSE $display("cyc=%0d", cyc); `endif if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module Test ( input clk, input integer cyc ); `ifdef FAIL_ASSERT_1 assert property ( @(posedge clk) 1 |-> 0 ) else $display("[%0t] wrong implication", $time); assert property ( @(posedge clk) 1 |=> 0 ) else $display("[%0t] wrong implication", $time); assert property ( @(posedge clk) cyc%3==1 |=> cyc%3==1 ) else $display("[%0t] wrong implication (step)", $time); assert property ( @(posedge clk) cyc%3==1 |=> cyc%3==0 ) else $display("[%0t] wrong implication (step)", $time); assert property ( @(posedge clk) disable iff (cyc == 3) (cyc == 4) |=> 0 ) else $display("[%0t] wrong implication (disable)", $time); assert property ( @(posedge clk) disable iff (cyc == 6) (cyc == 4) |=> 0 ) else $display("[%0t] wrong implication (disable)", $time); `endif // Test |-> assert property ( @(posedge clk) 1 |-> 1 ); assert property ( @(posedge clk) 0 |-> 0 ); assert property ( @(posedge clk) 0 |-> 1 ); // Test |=> assert property ( @(posedge clk) 1 |=> 1 ); assert property ( @(posedge clk) 0 |=> 0 ); assert property ( @(posedge clk) 0 |=> 1 ); // Test correct handling of time step in |=> assert property ( @(posedge clk) cyc%3==1 |=> cyc%3==2 ); // Test correct handling of disable iff assert property ( @(posedge clk) disable iff (cyc < 3) 1 |=> cyc > 3 ); // Test correct handling of disable iff in current cycle assert property ( @(posedge clk) disable iff (cyc == 4) (cyc == 4) |=> 0 ); // Test correct handling of disable iff in previous cycle assert property ( @(posedge clk) disable iff (cyc == 5) (cyc == 4) |=> 0 ); endmodule verilator-5.042/test_regress/t/t_flag_prefix_bad.py0000755000542200017500000000111315101701376023056 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = 't/t_EXAMPLE.v' # Anything test.lint(verilator_flags2=["--prefix bad/name"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_once_bad.out0000644000542200017500000000137115101701376022724 0ustar mahmoudyfreeshell%Warning-UNUSEDSIGNAL: t/t_lint_once_bad.v:19:14: Signal is not driven, nor used: 'unus1' : ... note: In instance 't.sub1' 19 | reg [A:0] unus1; reg [A:0] unus2; | ^~~~~ ... For warning description see https://verilator.org/warn/UNUSEDSIGNAL?v=latest ... Use "/* verilator lint_off UNUSEDSIGNAL */" and lint_on around source to disable this message. %Warning-UNUSEDSIGNAL: t/t_lint_once_bad.v:19:34: Signal is not driven, nor used: 'unus2' : ... note: In instance 't.sub1' 19 | reg [A:0] unus1; reg [A:0] unus2; | ^~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_inside_unpacked_param.v0000644000542200017500000000113215101701376024102 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; localparam int CHECKLIST_P [2:0] = '{0, 1, 2}; localparam HIT_LP = 1; localparam MISS_LP = 4; localparam HIT_INSIDE = HIT_LP inside {CHECKLIST_P}; localparam MISS_INSIDE = MISS_LP inside {CHECKLIST_P}; initial begin if (HIT_INSIDE != 1) $stop; if (MISS_INSIDE != 0) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_display_p_elab.py0000755000542200017500000000077415101701376022745 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.compile(verilator_flags2=['--binary']) test.execute() test.passes() verilator-5.042/test_regress/t/t_comb_input_0.py0000755000542200017500000000106615101701376022347 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile( #make_top_shell = False, make_main=False, v_flags2=["--exe", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_timing_dynscope.v0000644000542200017500000000166615101701376023004 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `timescale 1ns / 1ns static int counts[10]; class Foo; static task do_something(); for (int i = 0; i < 10; i++) begin // Should create a dynamic scope for `i` int ci = i; // Should create another dynamic scope for `ci`, local to the begin block fork begin #10; $display("ci: %d, i: %d", ci, i); if (i != 10) $stop; if (counts[ci-1]++ > 0) $stop; end join_none ci++; end endtask endclass module t(); initial begin int desired_counts[10]; counts = '{10{0}}; desired_counts = '{10{1}}; Foo::do_something(); #20; if (counts != desired_counts) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_multitop_sig.v0000644000542200017500000000124315101701376022317 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module a(in, out); input in; output out; assign out = !in; sub sub (); initial $display("In '%m'"); endmodule module b(in, out); input in; output out; assign out = in; sub sub (); initial $display("In '%m'"); endmodule module c(uniq_in, uniq_out); input uniq_in; output uniq_out; assign uniq_out = !uniq_in; sub sub (); initial $display("In '%m'"); endmodule module sub; initial $display("In '%m'"); endmodule verilator-5.042/test_regress/t/t_constraint_unpacked_array.v0000755000542200017500000000747715101701376025056 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by PlanV GmbH. // SPDX-License-Identifier: CC0-1.0 `define check_rand(cl, field) \ begin \ longint prev_result; \ int ok = 0; \ void'(cl.randomize()); \ prev_result = longint'(field); \ repeat(9) begin \ longint result; \ void'(cl.randomize()); \ result = longint'(field); \ if (result != prev_result) ok = 1; \ prev_result = result; \ end \ if (ok != 1) $stop; \ end class con_rand_1d_array_test; rand bit [7:0] data[5]; constraint c_data { foreach (data[i]) { data[i] inside {8'h10, 8'h20, 8'h30, 8'h40, 8'h50}; } } function new(); data = '{default: 'h0}; endfunction function void check_randomization(); foreach (data[i]) begin `check_rand(this, data[i]) if (data[i] inside {8'h10, 8'h20, 8'h30, 8'h40, 8'h50}) begin $display("data[%0d] = %h is valid", i, data[i]); end else begin $display("Error: data[%0d] = %h is out of bounds", i, data[i]); $stop; end end endfunction endclass class con_rand_2d_array_test; rand bit [7:0] data[3][3]; constraint c_data { foreach (data[i, j]) { data[i][j] >= 8'h10; data[i][j] <= 8'h50; } } function new(); data = '{default: '{default: 'h0}}; endfunction function void check_randomization(); foreach (data[i, j]) begin `check_rand(this, data[i][j]) if (data[i][j] >= 8'h10 && data[i][j] <= 8'h50) begin $display("data[%0d][%0d] = %h is valid", i, j, data[i][j]); end else begin $display("Error: data[%0d][%0d] = %h is out of bounds", i, j, data[i][j]); $stop; end end endfunction endclass class con_rand_3d_array_test; rand bit [7:0] data[2][2][2]; constraint c_data { foreach (data[i, j, k]) { data[i][j][k] >= 8'h10; data[i][j][k] <= 8'h50; if (i > 0) { data[i][j][k] > data[i-1][j][k] + 8'h05; } if (j > 0) { data[i][j][k] > data[i][j-1][k]; } } } function new(); data = '{default: '{default: '{default: 'h0}}}; endfunction function void check_randomization(); foreach (data[i, j, k]) begin `check_rand(this, data[i][j][k]) if (data[i][j][k] >= 8'h10 && data[i][j][k] <= 8'h50) begin if (i > 0 && data[i][j][k] <= data[i-1][j][k] + 8'h05) begin $display("Error: data[%0d][%0d][%0d] = %h does not satisfy i > 0 constraint", i, j, k, data[i][j][k]); $stop; end if (j > 0 && data[i][j][k] <= data[i][j-1][k]) begin $display("Error: data[%0d][%0d][%0d] = %h does not satisfy j > 0 constraint", i, j, k, data[i][j][k]); $stop; end $display("data[%0d][%0d][%0d] = %h is valid", i, j, k, data[i][j][k]); end else begin $display("Error: data[%0d][%0d][%0d] = %h is out of bounds", i, j, k, data[i][j][k]); $stop; end end endfunction endclass module t_constraint_unpacked_array; con_rand_1d_array_test rand_test_1; con_rand_2d_array_test rand_test_2; con_rand_3d_array_test rand_test_3; initial begin // Test 1: Randomization for 1D array $display("Test 1: Randomization for 1D array:"); rand_test_1 = new(); repeat(2) begin rand_test_1.check_randomization(); end // Test 2: Randomization for 2D array $display("Test 2: Randomization for 2D array:"); rand_test_2 = new(); repeat(2) begin rand_test_2.check_randomization(); end // Test 3: Randomization for 3D array $display("Test 3: Randomization for 3D array:"); rand_test_3 = new(); repeat(2) begin rand_test_3.check_randomization(); end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_time_sc_ms.out0000644000542200017500000000022615101701376022264 0ustar mahmoudyfreeshell Warning: (W516) default time unit changed to time resolution Time scale of t is 1ms / 1ms [20] In top.t: Hi - expect this is 20 *-* All Finished *-* verilator-5.042/test_regress/t/t_sys_file_basic.py0000755000542200017500000000131015101701376022737 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.unlink_ok(test.obj_dir + "/t_sys_file_basic_test.log") test.compile( # Build without cached objects, see bug363 make_flags=['VM_PARALLEL_BUILDS=0']) test.execute() test.files_identical(test.obj_dir + "/t_sys_file_basic_test.log", test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_param_type_fwd_bad.out0000644000542200017500000000647215101701376023762 0ustar mahmoudyfreeshell%Error: t/t_param_type_fwd_bad.v:25:11: Parameter type expression type 'int' violates parameter's forwarding type 'enum' : ... note: In instance 't' 25 | sub #(.E_t(int_t), .S_t(int_t), .U_t(int_t), .C_t(int_t), .IC_t(int_t)) sub(); | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_param_type_fwd_bad.v:25:24: Parameter type expression type 'int' violates parameter's forwarding type 'struct' : ... note: In instance 't' 25 | sub #(.E_t(int_t), .S_t(int_t), .U_t(int_t), .C_t(int_t), .IC_t(int_t)) sub(); | ^~~ %Error: t/t_param_type_fwd_bad.v:25:37: Parameter type expression type 'int' violates parameter's forwarding type 'union' : ... note: In instance 't' 25 | sub #(.E_t(int_t), .S_t(int_t), .U_t(int_t), .C_t(int_t), .IC_t(int_t)) sub(); | ^~~ %Error: t/t_param_type_fwd_bad.v:25:50: Parameter type expression type 'int' violates parameter's forwarding type 'class' : ... note: In instance 't' 25 | sub #(.E_t(int_t), .S_t(int_t), .U_t(int_t), .C_t(int_t), .IC_t(int_t)) sub(); | ^~~ %Error: t/t_param_type_fwd_bad.v:25:63: Parameter type expression type 'int' violates parameter's forwarding type 'interface class' : ... note: In instance 't' 25 | sub #(.E_t(int_t), .S_t(int_t), .U_t(int_t), .C_t(int_t), .IC_t(int_t)) sub(); | ^~~~ %Error: t/t_param_type_fwd_bad.v:26:11: Parameter type expression type 'int' violates parameter's forwarding type 'enum' : ... note: In instance 't' 26 | Cls #(.E_t(int_t), .S_t(int_t), .U_t(int_t), .C_t(int_t), .IC_t(int_t)) c; | ^~~ %Error: t/t_param_type_fwd_bad.v:26:24: Parameter type expression type 'int' violates parameter's forwarding type 'struct' : ... note: In instance 't' 26 | Cls #(.E_t(int_t), .S_t(int_t), .U_t(int_t), .C_t(int_t), .IC_t(int_t)) c; | ^~~ %Error: t/t_param_type_fwd_bad.v:26:37: Parameter type expression type 'int' violates parameter's forwarding type 'union' : ... note: In instance 't' 26 | Cls #(.E_t(int_t), .S_t(int_t), .U_t(int_t), .C_t(int_t), .IC_t(int_t)) c; | ^~~ %Error: t/t_param_type_fwd_bad.v:26:50: Parameter type expression type 'int' violates parameter's forwarding type 'class' : ... note: In instance 't' 26 | Cls #(.E_t(int_t), .S_t(int_t), .U_t(int_t), .C_t(int_t), .IC_t(int_t)) c; | ^~~ %Error: t/t_param_type_fwd_bad.v:26:63: Parameter type expression type 'int' violates parameter's forwarding type 'interface class' : ... note: In instance 't' 26 | Cls #(.E_t(int_t), .S_t(int_t), .U_t(int_t), .C_t(int_t), .IC_t(int_t)) c; | ^~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_trace_open_wrong_order_bad.py0000755000542200017500000000120515101701376025320 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["--cc --trace-vcd --exe", test.pli_filename], make_top_shell=False, make_main=False) test.execute(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_flag_language.py0000755000542200017500000000077715101701376022555 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=['--language 1364-2001']) test.execute() test.passes() verilator-5.042/test_regress/t/t_pp_pragmas.v0000644000542200017500000000250115101701376021727 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `timescale 1ns/10ps `verilog `suppress_faults `nosuppress_faults `enable_portfaults `disable_portfaults `delay_mode_distributed `delay_mode_path `delay_mode_unit `delay_mode_zero `default_decay_time 1 `default_decay_time 1.0 `default_decay_time infinite // unsupported (recommended not to): `default_trireg_strength 10 `default_nettype wire // unsupported: `default_nettype tri // unsupported: `default_nettype tri0 // unsupported: `default_nettype wand // unsupported: `default_nettype triand // unsupported: `default_nettype wor // unsupported: `default_nettype trior // unsupported: `default_nettype trireg `default_nettype none `autoexpand_vectornets `accelerate `noaccelerate `expand_vectornets `noexpand_vectornets `remove_gatenames `noremove_gatenames `remove_netnames `noremove_netnames `resetall // unsupported: `unconnected_drive pull1 // unsupported: `unconnected_drive pull0 `nounconnected_drive `line 100 "hallo.v" 0 // unsupported: `uselib file=../moto_lib.v // unsupported: `uselib dir=../lib.dir libext=.v module t; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_enum_public.py0000755000542200017500000000120015101701376022261 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if test.vlt_all: test.compile(verilator_flags2=["--exe", test.pli_filename], make_top_shell=False, make_main=False) else: test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_force.v0000644000542200017500000000564515101701376020710 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) `define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t(/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [3:0] in; tri [3:0] bus = in; int never_driven; int never_forced; real r; task force_bus; force bus[1:0] = 2'b10; endtask task release_bus; release bus; endtask // Test loop always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 0) begin in <= 4'b0101; end else if (cyc == 1) begin `checkh(in, 4'b0101); end // Check forces with no driver if (cyc == 1) begin force never_driven = 32'h888; end else if (cyc == 2) begin `checkh(never_driven, 32'h888); end // // Check release with no force else if (cyc == 10) begin never_forced <= 5432; end else if (cyc == 11) begin `checkh(never_forced, 5432); end else if (cyc == 12) begin release never_forced; // no-op end else if (cyc == 13) begin `checkh(never_forced, 5432); end // // bus else if (cyc == 20) begin `checkh(bus, 4'b0101); force bus = 4'b0111; end else if (cyc == 21) begin `checkh(bus, 4'b0111); force bus = 4'b1111; end else if (cyc == 22) begin `checkh(bus, 4'b1111); release bus; end else if (cyc == 23) begin `checkh(bus, 4'b0101); end // else if (cyc == 30) begin force_bus(); end else if (cyc == 31) begin `checkh(bus, 4'b0110); end else if (cyc == 32) begin release bus[0]; end else if (cyc == 33) begin `checkh(bus, 4'b0111); release_bus(); end else if (cyc == 34) begin `checkh(in, 4'b0101); `checkh(bus, 4'b0101); end // else if (cyc == 40) begin r <= 1.25; end else if (cyc == 41) begin `checkr(r, 1.25); end else if (cyc == 42) begin force r = 2.5; end else if (cyc == 43) begin `checkr(r, 2.5); end else if (cyc == 44) begin release r; end else if (cyc == 45) begin `checkr(r, 2.5); end // else if (cyc == 99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_math_signed_calc.v0000644000542200017500000000204115101701376023041 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This mode performs signed number computations in the case of a particular // interface definition. // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Raynard Qiao. // SPDX-License-Identifier: CC0-1.0 // issure 3294 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [7:0] in0; reg [7:0] in1; reg [15:0] out; initial begin in0 = 'h2; in1 = 'hff; end Test test(.in0, .in1, .out); always @ (posedge clk) begin `ifdef TEST_VERBOSE $display("[%0t] clk @ out 'h%0x, expect value='hfffe", $time, out); `endif if (out !== 'hfffe) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module Test(in0, in1, out); input [7:0] in0; input [7:0] in1; output [15:0] out; wire signed [7:0] in1; wire signed [7:0] in0; wire signed [15:0] out; assign out = $signed({1'b0, in0}) * in1; // this operator should be signed multiplication endmodule verilator-5.042/test_regress/t/t_foreach_const.py0000755000542200017500000000073415101701376022607 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_string.v0000644000542200017500000000707115101701376021113 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=\"%s\" exp=\"%s\"\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [1*8:1] vstr1; reg [2*8:1] vstr2; reg [6*8:1] vstr6; reg [4*8:1] vstr; const string s = "a"; // Check static assignment string s2; string s3; reg eq; byte unpack1[0:4]; // Operators == != < <= > >= {a,b} {a{b}} a[b] // a.len, a.putc, a.getc, a.toupper, a.tolower, a.compare, a.icompare, a.substr // a.atoi, a.atohex, a.atooct, a.atobin, a.atoreal, // a.itoa, a.hextoa, a.octoa, a.bintoa, a.realtoa initial begin $sformat(vstr1, "%s", s); `checks(vstr1, "a"); $sformat(vstr2, "=%s", s); `checks(vstr2, "=a"); $sformat(vstr6, "--a=%s", s); `checks(vstr6, "--a=a"); $sformat(vstr, "s=%s", s); `checks(vstr, "s=a"); `checks(string'(vstr), "s=a"); `checks(s, "a"); `checks({s,s,s}, "aaa"); `checks({4{s}}, "aaaa"); // Constification `checkh(s == "a", 1'b1); `checkh(s == "b", 1'b0); `checkh(s != "a", 1'b0); `checkh(s != "b", 1'b1); `checkh(s > " ", 1'b1); `checkh(s > "a", 1'b0); `checkh(s >= "a", 1'b1); `checkh(s >= "b", 1'b0); `checkh(s < "a", 1'b0); `checkh(s < "b", 1'b1); `checkh(s <= " ", 1'b0); `checkh(s <= "a", 1'b1); `ifndef VCS `ifndef VERILATOR `ifndef NC // IEEE 1800-2023 5.9 assignment to byte array unpack1 = "five"; `checkh(unpack1[0], "f"); `checkh(unpack1[1], "i"); `checkh(unpack1[2], "v"); `checkh(unpack1[3], "e"); `checkh(unpack1[4], 8'h0); `endif `endif `endif end // Test loop always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==0) begin // Setup s2 = "c0"; end else if (cyc==1) begin $sformat(vstr, "s2%s", s2); `checks(vstr, "s2c0"); end else if (cyc==2) begin s3 = s2; $sformat(vstr, "s2%s", s3); `checks(vstr, "s2c0"); end else if (cyc==3) begin s2 = "a"; s3 = "b"; end else if (cyc==4) begin `checks({s2,s3}, "ab"); `checks({3{s3}}, "bbb"); `checkh(s == "a", 1'b1); `checkh(s == "b", 1'b0); `checkh(s != "a", 1'b0); `checkh(s != "b", 1'b1); `checkh(s > " ", 1'b1); `checkh(s > "a", 1'b0); `checkh(s >= "a", 1'b1); `checkh(s >= "b", 1'b0); `checkh(s < "a", 1'b0); `checkh(s < "b", 1'b1); `checkh(s <= " ", 1'b0); `checkh(s <= "a", 1'b1); end // String character references else if (cyc==10) begin s2 = "astring"; end else if (cyc==11) begin `checks(s2, "astring"); `checkh(s2.len(), 7); `checkh(s2[1], "s"); s2[0] = "0"; s2[3] = "3"; `checks(s2, "0st3ing"); end // else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_class_param_override_local_bad.py0000755000542200017500000000076315101701376026140 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_timing_initial_always.py0000755000542200017500000000077115101701376024353 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_runflag_uninit_bad.out0000644000542200017500000000023515101701376023774 0ustar mahmoudyfreeshell%Error: unknown:0: %Error: Verilog called $test$plusargs or $value$plusargs without testbench C first calling Verilated::commandArgs(argc,argv). Aborting... verilator-5.042/test_regress/t/t_lint_style_bad.py0000755000542200017500000000107115101701376022761 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["--lint-only -Wwarn-style"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_extends_rec_bad.py0000755000542200017500000000076615101701376024275 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dpi_export.v0000644000542200017500000000636615101701376021770 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VCS `define NO_TIME `endif `ifdef NC `define NO_TIME `endif module t; sub a (.inst(1)); sub b (.inst(2)); // Returns integer line number, or -1 for all ok import "DPI-C" context function int dpix_run_tests(); export "DPI-C" task dpix_t_int; task dpix_t_int(input int i, output int o); o = ~i; endtask export "DPI-C" dpix_t_renamed = task dpix_t_ren; task dpix_t_ren(input int i, output int o); o = i+2; endtask export "DPI-C" function dpix_int123; function int dpix_int123(); dpix_int123 = 32'h123; endfunction export "DPI-C" function dpix_f_bit; export "DPI-C" function dpix_f_bit15; export "DPI-C" function dpix_f_int; export "DPI-C" function dpix_f_byte; export "DPI-C" function dpix_f_shortint; export "DPI-C" function dpix_f_longint; export "DPI-C" function dpix_f_chandle; function bit dpix_f_bit (bit i); dpix_f_bit = ~i; endfunction function bit [14:0] dpix_f_bit15 (bit [14:0] i); dpix_f_bit15 = ~i; endfunction function int dpix_f_int (int i); dpix_f_int = ~i; endfunction function byte dpix_f_byte (byte i); dpix_f_byte = ~i; endfunction function shortint dpix_f_shortint(shortint i); dpix_f_shortint = ~i; endfunction function longint dpix_f_longint (longint i); dpix_f_longint = ~i; endfunction function chandle dpix_f_chandle (chandle i); dpix_f_chandle = i; endfunction export "DPI-C" task dpix_t_bit48; task dpix_t_bit48(input bit [47:0] i, output bit [47:0] o); o = ~i; endtask export "DPI-C" task dpix_t_bit95; task dpix_t_bit95(input bit [94:0] i, output bit [94:0] o); o = ~i; endtask export "DPI-C" task dpix_t_bit96; task dpix_t_bit96(input bit [95:0] i, output bit [95:0] o); o = ~i; endtask export "DPI-C" task dpix_t_reg; task dpix_t_reg(input reg i, output reg o); o = ~i; endtask export "DPI-C" task dpix_t_reg15; task dpix_t_reg15(input reg [14:0] i, output reg [14:0] o); o = ~i; endtask export "DPI-C" task dpix_t_reg95; task dpix_t_reg95(input reg [94:0] i, output reg [94:0] o); o = ~i; endtask export "DPI-C" task dpix_t_integer; task dpix_t_integer(input integer i, output integer o); o = ~i; endtask `ifndef NO_TIME export "DPI-C" task dpix_t_time; `endif task dpix_t_time(input time i, output time o); o = ~i; endtask export "DPI-C" function dpix__under___score; function int dpix__under___score(input int i); return i + 1; endfunction int lineno; initial begin lineno = dpix_run_tests(); if (lineno != -1) begin $display("[%0t] %%Error: t_dpix_ort_c.c:%0d: dpix_run_tests returned an error", $time, lineno); $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule module sub (input int inst); export "DPI-C" function dpix_sub_inst; function int dpix_sub_inst (int i); dpix_sub_inst = inst + i; endfunction endmodule verilator-5.042/test_regress/t/t_disable_within_task_unsup.out0000644000542200017500000000043215101701376025402 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_disable_within_task_unsup.v:8:4: Unsupported: disabling fork from task / function 8 | disable t.init.fork_blk; | ^~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_class_local_protect_ids.py0000755000542200017500000000151715101701376024650 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_class_local.v" # This test makes randomly named .cpp/.h files, which tend to collect, so remove them first for filename in (glob.glob(test.obj_dir + "/*_PS*.cpp") + glob.glob(test.obj_dir + "/*_PS*.h") + glob.glob(test.obj_dir + "/*.d")): test.unlink_ok(filename) test.compile(verilator_flags2=["--protect-ids", "--protect-key SECRET_KEY"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_wrapper_context.v0000644000542200017500000000254215101701376023027 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This model counts from 0 to 10. It is instantiated twice in concurrent // threads to check for race conditions/signal interference. // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020-2021 by Andreas Kuster. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" module top ( input clk, input rst, input [31:0] trace_number, input stop, output bit [31:0] counter, output bit done_o ); initial begin string number; string filename; number.itoa(trace_number); `ifdef TRACE_FST filename = {`STRINGIFY(`TEST_OBJ_DIR), "/trace", number, ".fst"}; `else filename = {`STRINGIFY(`TEST_OBJ_DIR), "/trace", number, ".vcd"}; `endif $display("Writing dumpfile '%s'", filename); $dumpfile(filename); $dumpvars(); end always@(posedge clk) begin if (rst) counter <= 0; else counter <= counter + 1; end always_comb begin done_o = '0; if (stop) begin if (counter >= 5 && stop) begin done_o = '1; $stop; end end else begin if (counter >= 10) begin done_o = '1; $finish; end end end endmodule verilator-5.042/test_regress/t/t_math_concat.py0000755000542200017500000000073415101701376022252 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_inst_missing_bad.out0000644000542200017500000000172115101701376023457 0ustar mahmoudyfreeshell%Warning-PINNOCONNECT: t/t_inst_missing_bad.v:13:17: Instance pin is not connected: '__pinNumber2' 13 | sub sub (ok, , nc); | ^ ... For warning description see https://verilator.org/warn/PINNOCONNECT?v=latest ... Use "/* verilator lint_off PINNOCONNECT */" and lint_on around source to disable this message. %Warning-PINMISSING: t/t_inst_missing_bad.v:13:8: Instance has missing pin: 'missing' 13 | sub sub (ok, , nc); | ^~~ t/t_inst_missing_bad.v:16:51: ... Location of port declaration 16 | module sub (input ok, input none, input nc, input missing); | ^~~~~~~ ... For warning description see https://verilator.org/warn/PINMISSING?v=latest ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_hier_block_libmod.v0000644000542200017500000000054615101701376023234 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by Yutetsu TAKATSUKASA // SPDX-License-Identifier: Unlicense module t; t_flag_relinc_sub i_t_flag_relinc_sub(); endmodule `ifdef VERILATOR `verilator_config hier_block -module "t_flag_relinc_sub" `verilog `endif verilator-5.042/test_regress/t/t_vpi_var3.py0000755000542200017500000000160615101701376021522 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.pli_filename = "t/t_vpi_var.cpp" test.compile(make_top_shell=False, make_main=False, make_pli=True, sim_time=2100, iv_flags2=["-g2005-sv -D USE_VPI_NOT_DPI -DWAVES -DT_VPI_VAR3"], v_flags2=["+define+USE_VPI_NOT_DPI"], verilator_flags2=["--exe --vpi --no-l2name --public-flat-rw", test.pli_filename]) test.execute(use_libvpi=True, all_run_flags=['+PLUS +INT=1234 +STRSTR']) test.passes() verilator-5.042/test_regress/t/t_assoc_default_func.v0000644000542200017500000000103015101701376023421 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; class param_comp #( type T = bit ); static function int get_type(); return 0; endfunction endclass class test; virtual function void check_phase(); int m_param_comp_bit_expect_wrapper[string] = '{default: param_comp#(bit)::get_type()}; endfunction endclass endmodule verilator-5.042/test_regress/t/t_gen_nonconst_bad.py0000755000542200017500000000122715101701376023270 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint( v_flags=[], # To avoid -I v_flags2=[], # To avoid -I verilator_flags=["--lint-only"], # To avoid -I verilator_flags2=[], # To avoid -I fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_flag_errorlimit_bad.py0000755000542200017500000000110515101701376023752 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["-Wall -Wno-DECLFILENAME --error-limit 2"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_foreach_const.v0000644000542200017500000001307515101701376022423 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t; // verilator lint_off ASCRANGE // verilator lint_off WIDTH reg [63:0] sum; // Checked not in objects reg [63:0] add; reg [2:1] [4:3] array [5:6] [7:8]; reg [1:2] [3:4] larray [6:5] [8:7]; bit [31:0] depth1_array [0:0]; int oned [3:1]; int twod [3:1][9:8]; typedef struct packed { reg [1:0] [63:0] subarray; } str_t; typedef struct packed { str_t mid; } mid_t; function [63:0] crc (input [63:0] sum, input [31:0] a, input [31:0] b, input [31:0] c, input [31:0] d); crc = {sum[62:0],sum[63]} ^ {4'b0,a[7:0], 4'h0,b[7:0], 4'h0,c[7:0], 4'h0,d[7:0]}; endfunction function [63:0] test1; test1 = 0; // We use 'index_' as the prefix for all loop vars, // this allows t_foreach.py to confirm that all loops // have been unrolled and flattened away and no loop vars // remain in the generated .cpp foreach (depth1_array[index_a]) begin test1 = crc(test1, index_a, 0, 0, 0); // Ensure the index never goes out of bounds. // We used to get this wrong for an array of depth 1. if (index_a == -1) return 7; if (index_a == 1) return 7; end endfunction localparam PAR1 = test1(); function [63:0] test2; test2 = 0; foreach (array[index_a]) begin test2 = crc(test2, index_a, 0, 0, 0); end endfunction localparam PAR2 = test2(); function [63:0] test3; test3 = 0; foreach (array[index_a,index_b]) begin test3 = crc(test3, index_a, index_b, 0, 0); end endfunction localparam PAR3 = test3(); function [63:0] test4; test4 = 0; foreach (array[index_a,index_b,index_c]) begin test4 = crc(test4, index_a, index_b, index_c, 0); end endfunction localparam PAR4 = test4(); function [63:0] test5; test5 = 0; foreach (array[index_a,index_b,index_c,index_d]) begin test5 = crc(test5, index_a, index_b, index_c, index_d); end endfunction localparam PAR5 = test5(); function [63:0] test6; // comma syntax test6 = 0; foreach (array[,index_b]) begin $display(index_b); test6 = crc(test6, 0, index_b, 0, 0); end endfunction localparam PAR6 = test6(); function [63:0] test7; test7 = 0; foreach (larray[index_a]) begin test7 = crc(test7, index_a, 0, 0, 0); end endfunction localparam PAR7 = test7(); function [63:0] test8; test8 = 0; foreach (larray[index_a,index_b]) begin test8 = crc(test8, index_a, index_b, 0, 0); test8 = test8 + {4'b0,index_a[7:0], 4'h0,index_b[7:0]}; end endfunction localparam PAR8 = test8(); function [63:0] test9; test9 = 0; foreach (larray[index_a,index_b,index_c]) begin test9 = crc(test9, index_a, index_b, index_c, 0); end endfunction localparam PAR9 = test9(); function [63:0] test10; test10 = 0; foreach (larray[index_a,index_b,index_c,index_d]) begin test10 = crc(test10, index_a, index_b, index_c, index_d); end endfunction localparam PAR10 = test10(); function [63:0] test11; automatic mid_t strarray[3]; strarray = '{ '{ '{ '{2, 1} } }, '{ '{ '{5, 4} } }, '{ '{ '{7, 6} } } }; test11 = 0; foreach (strarray[s]) foreach (strarray[s].mid.subarray[ss]) test11 += strarray[s].mid.subarray[ss]; endfunction localparam PAR11 = test11(); function [63:0] test12; test12 = 0; foreach (oned[i]) begin ++test12; break; end endfunction localparam PAR12 = test12(); function [63:0] test13; test13 = 0; foreach (oned[i]) begin ++test13; continue; test13 += 100; end endfunction localparam PAR13 = test13(); function [63:0] test14; test14 = 0; foreach (twod[i, j]) begin ++test14; break; end endfunction localparam PAR14 = test14(); function [63:0] test15; test15 = 0; foreach (twod[i, j]) begin ++test15; continue; test15 += 100; end foreach (twod[i, j]); // Null body check endfunction localparam PAR15 = test15(); function automatic [63:0] test16; string str1 = ""; test16 = 0; foreach(str1[i]) begin test16++; end endfunction localparam PAR16 = test16(); initial begin `checkh(PAR1, 64'h0); `checkh(PAR2, 64'h000000c000000000); `checkh(PAR3, 64'h000003601e000000); `checkh(PAR4, 64'h00003123fc101000); `checkh(PAR5, 64'h0030128ab2a8e557); `checkh(PAR6, 64'h0000000006000000); `checkh(PAR7, 64'h0000009000000000); `checkh(PAR8, 64'h000002704b057073); `checkh(PAR9, 64'h00002136f9000000); `checkh(PAR10, 64'h0020179aa7aa0aaa); `checkh(PAR11, 'h19); `checkh(PAR12, 1); // 9 `checkh(PAR13, 3); // 9, 8, 7 // See https://www.accellera.org/images/eda/sv-bc/10303.html `checkh(PAR14, 1); // 3,9 `checkh(PAR15, 6); `checkh(PAR16, 0); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_interface_down_inlbc.py0000755000542200017500000000112215101701376024120 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_down.v" test.compile(v_flags2=['+define+INLINE_B +define+INLINE_C'], verilator_flags2=['-trace']) test.execute() test.passes() verilator-5.042/test_regress/t/t_xml_first.v0000644000542200017500000000173015101701376021610 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs q, // Inputs clk, d ); input clk; input [3:0] d; output wire [3:0] q; logic [3:0] between; mod1 #(.WIDTH(4)) cell1 (.q(between), .clk (clk), .d (d[3:0])); mod2 cell2 (.d(between), .q (q[3:0]), .clk (clk)); endmodule module mod1 #(parameter WIDTH = 32) ( input clk, input [WIDTH-1:0] d, output logic [WIDTH-1:0] q ); localparam IGNORED = 1; always @(posedge clk) q <= d; endmodule module mod2 ( input clk, input [3:0] d, output wire [3:0] q ); assign q = d; endmodule verilator-5.042/test_regress/t/t_genfor_init_o0.v0000644000542200017500000000044215101701376022501 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; genvar i; for (i = 0; i < 0; i = i + 1) begin end endmodule verilator-5.042/test_regress/t/t_display_concat.v0000644000542200017500000000132215101701376022572 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; int cyc = 0; always @ (posedge clk) ++cyc; reg [15 : 0] t2; always@(posedge clk) begin if (cyc == 0) begin t2 <= 16'd0; end else if (cyc == 2) begin t2 <= 16'habcd; end else if (cyc == 4) begin $display("abcd=%x", t2); $display("ab0d=%x", { t2[15:8], 4'd0, t2[3:0] }); $write("*-* All Finished *-*\n"); $finish(32'd0); end end endmodule verilator-5.042/test_regress/t/t_class_short_circuit.py0000755000542200017500000000073415101701376024040 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_eq_wild_unsup.out0000644000542200017500000000056615101701376023027 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_eq_wild_unsup.v:13:13: Unsupported: RHS of ==? or !=? is fourstate but not a constant : ... note: In instance 't' 13 | if (1 ==? get_x_or_0(0)) $stop; | ^~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_constraint_assoc_arr_wide.v0000755000542200017500000000577215101701376025046 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by PlanV GmbH. // SPDX-License-Identifier: CC0-1.0 class AssocIntegralWide; rand bit [31:0] assoc_array[bit[64:0]]; rand bit [31:0] assoc_array_128[bit[128:0]]; rand bit [31:0] assoc_array_2d[bit[64:0]][bit[128:0]]; constraint valid_entries { assoc_array[65'd6] == 32'd8; assoc_array[65'h1FFFFFFFFFFFFFFFF] == 32'hDEADBEEF; assoc_array_128[129'd6] == 32'd16; assoc_array_128[129'h1FFFFFFFFFFFFFFFFFFFFFFFF] == 32'hCAFEBABE; assoc_array_2d[65'd6][129'd6] == 32'd32; assoc_array_2d[65'h1FFFFFFFFFFFFFFFF][129'h1FFFFFFFFFFFFFFFFFFFFFFFF] == 32'hBADF00D; } // Constructor to initialize arrays function new(); assoc_array[65'd0] = 32'd0; assoc_array[65'd6] = 32'd0; assoc_array[65'h1FFFFFFFFFFFFFFFF] = 32'd0; assoc_array_128[129'd0] = 32'd0; assoc_array_128[129'd6] = 32'd0; assoc_array_128[129'h1FFFFFFFFFFFFFFFFFFFFFFFF] = 32'd0; assoc_array_2d[65'd6][129'd6] = 32'd0; assoc_array_2d[65'h1FFFFFFFFFFFFFFFF][129'h1FFFFFFFFFFFFFFFFFFFFFFFF] = 32'd0; endfunction // Self-check function to verify constraints function void self_check(); if (assoc_array[65'd6] != 32'd8) $stop; if (assoc_array[65'h1FFFFFFFFFFFFFFFF] != 32'hDEADBEEF) $stop; if (assoc_array_128[129'd6] != 32'd16) $stop; if (assoc_array_128[129'h1FFFFFFFFFFFFFFFFFFFFFFFF] != 32'hCAFEBABE) $stop; if (assoc_array_2d[65'd6][129'd6] != 32'd32) $stop; if (assoc_array_2d[65'h1FFFFFFFFFFFFFFFF][129'h1FFFFFFFFFFFFFFFFFFFFFFFF] != 32'hBADF00D) $stop; endfunction endclass class AssocStringWide; rand bit [31:0] array_32[string]; rand bit [31:0] array_64[string]; rand bit [31:0] array_96[string]; rand bit [31:0] array_128[string]; constraint valid_entries { // <= 32 bits array_32["pv"] == 32'd10; // > 32 and <= 64 bits array_64["verilog"] == 32'd20; // > 32 and <= 64 bits array_96["verilator"] == 32'd30; // > 64 and <= 96 bits array_128["systemverilog"] == 32'd40; } function new(); array_32["pv"] = 32'd0; array_64["verilog"] = 32'd0; array_96["verilator"] = 32'd0; array_128["systemverilog"] = 32'd0; endfunction function void self_check(); if (array_32["pv"] != 32'd10) $stop; if (array_64["verilog"] != 32'd20) $stop; if (array_96["verilator"] != 32'd30) $stop; if (array_128["systemverilog"] != 32'd40) $stop; endfunction endclass module t_constraint_assoc_arr_wide; AssocIntegralWide integral_wide; AssocStringWide string_wide; int success; initial begin integral_wide = new(); string_wide = new(); success = integral_wide.randomize(); if (success != 1) $stop; integral_wide.self_check(); success = string_wide.randomize(); if (success != 1) $stop; string_wide.self_check(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_interface_generic_modport_task_bad.out0000755000542200017500000000067615101701376027206 0ustar mahmoudyfreeshell%Error: t/t_interface_generic_modport_task_bad.v:23:7: Can't find definition of 'setup' in dotted task/function: 'a.setup' : ... note: In instance 't.genericModule' 23 | a.setup(); | ^~~~~ ... Known scopes under 'setup': ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_class_extends_nf_bad.v0000644000542200017500000000066015101701376023732 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package Pkg; class otFound2; endclass endpackage class IsFound; endclass class Cls extends IsNotFound; // BAD: not found endclass class Cls2 extends Pkg::NotFound2; // BAD: not found endclass module t; endmodule verilator-5.042/test_regress/t/t_func.py0000755000542200017500000000073415101701376020725 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_param_array5.py0000755000542200017500000000073415101701376022355 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_gen.v0000644000542200017500000000274515101701376022401 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Very simple test for interface pathclearing module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=1; ifc #(1) itopa(); ifc #(2) itopb(); sub #(1) ca (.isub(itopa), .i_value(4)); sub #(2) cb (.isub(itopb), .i_value(5)); always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==1) begin if (itopa.MODE != 1) $stop; if (itopb.MODE != 2) $stop; end if (cyc==20) begin if (itopa.get_value() != 4) $stop; if (itopb.get_value() != 5) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module sub #(parameter MODE = 0) ( ifc.out_modport isub, input integer i_value ); always @* isub.value = i_value; endmodule interface ifc; parameter MODE = 0; // Modports under generates not supported by all commercial simulators integer value; modport out_modport (output value); function integer get_value(); return value; endfunction // IEEE 1800-2017 deprecated alowing modports inside generates // generate if (MODE == 0) begin // integer valuea; // modport out_modport (output valuea); // function integer get_valuea(); return valuea; endfunction // end endinterface verilator-5.042/test_regress/t/t_cover_line_wide_ternary.out0000644000542200017500000000651615101701376025053 0ustar mahmoudyfreeshell// // verilator_coverage annotation // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface intf(); logic foo; logic [31:0] bar; logic [127:0] baz; endinterface module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; %000001 initial cyc=1; -000001 point: comment=block hier=top.t intf intfs [2] (); intf intf_sel_ff(); intf intf_sel_comb(); intf intf_sel_assign(); %000001 always_comb begin -000001 point: comment=block hier=top.t %000001 intfs[0].bar = 123; -000001 point: comment=block hier=top.t %000001 intfs[1].bar = 456; -000001 point: comment=block hier=top.t end %000009 always_ff @ (posedge clk) begin -000009 point: comment=block hier=top.t %000009 {intf_sel_ff.foo, intf_sel_ff.bar, intf_sel_ff.baz} <= -000009 point: comment=block hier=top.t %000009 cyc[0] ? -000009 point: comment=cond_then hier=top.t %000009 {intfs[1].foo, intfs[1].bar, intfs[1].baz} : -000009 point: comment=cond_then hier=top.t -000009 point: comment=cond_else hier=top.t %000009 {intfs[0].foo, intfs[0].bar, intfs[0].baz}; -000009 point: comment=cond_else hier=top.t end 000010 always_comb begin +000010 point: comment=block hier=top.t 000010 {intf_sel_comb.foo, intf_sel_comb.bar, intf_sel_comb.baz} = +000010 point: comment=block hier=top.t 000010 cyc[0] ? +000010 point: comment=cond_then hier=top.t 000010 {intfs[1].foo, intfs[1].bar, intfs[1].baz} : +000010 point: comment=cond_then hier=top.t +000010 point: comment=cond_else hier=top.t 000010 {intfs[0].foo, intfs[0].bar, intfs[0].baz}; +000010 point: comment=cond_else hier=top.t end assign {intf_sel_assign.foo, intf_sel_assign.bar, intf_sel_assign.baz} = 000010 cyc[0] ? +000010 point: comment=cond_then hier=top.t 000010 {intfs[1].foo, intfs[1].bar, intfs[1].baz} : +000010 point: comment=cond_then hier=top.t +000010 point: comment=cond_else hier=top.t 000010 {intfs[0].foo, intfs[0].bar, intfs[0].baz}; +000010 point: comment=cond_else hier=top.t %000009 always @ (posedge clk) begin -000009 point: comment=block hier=top.t %000009 cyc <= cyc + 1; -000009 point: comment=block hier=top.t %000008 if (cyc==9) begin -000008 point: comment=else hier=top.t -000001 point: comment=if hier=top.t %000001 if (intf_sel_ff.bar != 123) $stop(); -000001 point: comment=else hier=top.t %000001 if (intf_sel_comb.bar != 456) $stop(); -000001 point: comment=else hier=top.t %000001 if (intf_sel_assign.bar != 456) $stop(); -000001 point: comment=else hier=top.t %000001 $write("*-* All Finished *-*\n"); -000001 point: comment=if hier=top.t %000001 $finish; -000001 point: comment=if hier=top.t end end endmodule verilator-5.042/test_regress/t/t_flag_libinc.v0000644000542200017500000000076615101701376022042 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module liblib_a; liblib_b b (); endmodule module liblib_b; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule module liblib_c; // Unused initial $stop; liblib_d d (); endmodule module liblib_d; // Unused initial $stop; endmodule verilator-5.042/test_regress/t/t_unopt_converge.v0000644000542200017500000000071415101701376022637 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs x, // Inputs clk ); `ifdef ALLOW_UNOPT /*verilator lint_off UNOPTFLAT*/ `endif input clk; output x; // Avoid eliminating x reg x; always @* begin x = ~x; end endmodule verilator-5.042/test_regress/t/t_inst_slice_part_select.v0000644000542200017500000000364015101701376024324 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by engr248. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; wire [31:0] in = 0; wire [31:0] out; Test test( .out(out[31:0]), .clk(clk), .in (in[31:0]) ); always @ (posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule interface Intf (); endinterface module Select #( parameter int NUM_MASTER = 1 ) ( Intf Upstream, Intf Downstream[NUM_MASTER] ); endmodule module Crossbar #( parameter int NUM_MASTER = 1, parameter int NUM_SLAVE = 1 ) ( Intf Masters[NUM_MASTER] ); Intf selectOut[(NUM_MASTER * (NUM_SLAVE))-1 : 0](); genvar i; for (i = 0; i < NUM_MASTER; i = i + 1) begin Select #( .NUM_MASTER(NUM_SLAVE) ) select_inst ( .Upstream(Masters[i]), // Following line seems to trigger a bad calculation for dimension where port // is calculated as width 1 (correctly) and expression is calculated as NUM_MASTER*NUM_SLAVE rather than NUM_SLAVE .Downstream(selectOut[(i)*(NUM_SLAVE) +: (NUM_SLAVE)]) // The following line works as intended and should be functionally identical to the above line // .Downstream(selectOut[(i+1)*(NUM_SLAVE)-1 : i*(NUM_SLAVE)]) ); end endmodule module Test ( input clk, input [31:0] in, output reg [31:0] out ); always @(posedge clk) begin out <= in; end Intf MST[10](); Crossbar #( .NUM_MASTER(10), .NUM_SLAVE(1) ) xbar_inst ( .Masters(MST) ); endmodule verilator-5.042/test_regress/t/t_dotfiles.py0000755000542200017500000000226115101701376021600 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vltmt') # Use a top file which we are sure to be parallelizable test.top_filename = "t/t_gen_alw.v" test.compile(v_flags2=["--dumpi-graph 6"], threads=2) for dotname in [ "linkcells", "task_call", "gate_graph", "gate_final", "acyc_simp", "orderg_pre", "orderg_acyc", "orderg_order", "orderg_domain", "ordermv_initial", "ordermv_hazards", "ordermv_contraction", "ordermv_transitive1", "orderg_done", "pack", "schedule" ]: # Some files with identical prefix are generated multiple times during # Verilation. Ensure that at least one of each dotname-prefixed file is generated. dotFiles = test.glob_some(test.obj_dir + "/*" + dotname + ".dot") for dotFilename in dotFiles: test.file_grep(dotFilename, r'digraph v3graph') test.passes() verilator-5.042/test_regress/t/t_gate_inline_wide_noexclude_arraysel.py0000755000542200017500000000122715101701376027226 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=['--stats', '--expand-limit 5']) test.file_grep(test.stats, r'Optimizations, Gate excluded wide expressions\s+(\d+)', 0) test.file_grep(test.stats, r'Optimizations, Gate sigs deleted\s+(\d+)', 1) test.passes() verilator-5.042/test_regress/t/t_func_recurse2.v0000644000542200017500000000122215101701376022342 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; function automatic int recurse_1; input int i; if (i == 0) recurse_1 = 0; else recurse_1 = i + recurse_2(i); endfunction function automatic int recurse_2; input int i; return recurse_1(i - 1) * 2; endfunction initial begin if (recurse_1(0) != 0) $stop; if (recurse_1(3) != (3 + 2*(2 + 2*(1)))) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_clocking_unsup1.py0000755000542200017500000000102515101701376023070 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["--timing"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_multitop1s.v0000644000542200017500000000052315101701376021721 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t_multitop1s; initial $display("In '%m'"); endmodule module in_subfile; initial $display("In '%m'"); endmodule verilator-5.042/test_regress/t/t_func_io_order.v0000644000542200017500000000324215101701376022416 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire ain = crc[0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) logic bout; // From test of Test.v // End of automatics Test test(/*AUTOINST*/ // Outputs .bout (bout), // Inputs .ain (ain)); // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x\n", $time, cyc, crc); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; if (cyc == 0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc < 10) begin if (bout != ~ain) $stop; end else if (cyc == 99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test(/*AUTOARG*/ // Outputs bout, // Inputs ain ); input logic ain; output logic bout; function automatic void inv (input logic w_in, output logic w_out); w_out = ~w_in; endfunction always_comb inv(.w_out(bout), .w_in(ain)); endmodule verilator-5.042/test_regress/t/t_json_only_flat_no_inline_mod.v0000644000542200017500000000062615101701376025515 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module foo(input logic i_clk); /* verilator no_inline_module */ endmodule // --flatten forces inlining of 'no_inline_module' module foo. module top(input logic i_clk); foo f(.*); endmodule verilator-5.042/test_regress/t/t_math_concat0.py0000755000542200017500000000073415101701376022332 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_param_module.py0000755000542200017500000000073415101701376022437 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_slice_init.py0000755000542200017500000000073415101701376022114 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_func_regfirst.v0000644000542200017500000000323115101701376022437 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; reg [2:0] a; reg [2:0] b; reg q; f6 f6 (/*AUTOINST*/ // Outputs .q (q), // Inputs .a (a[2:0]), .b (b[2:0]), .clk (clk)); integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin a <= 3'b000; b <= 3'b100; end if (cyc==2) begin a <= 3'b011; b <= 3'b001; if (q != 1'b0) $stop; end if (cyc==3) begin a <= 3'b011; b <= 3'b011; if (q != 1'b0) $stop; end if (cyc==9) begin if (q != 1'b1) $stop; $write("*-* All Finished *-*\n"); $finish; end end end endmodule module f6 (a, b, clk, q); input [2:0] a; input [2:0] b; input clk; output q; reg out; function func6; reg result; input [5:0] src; begin if (src[5:0] == 6'b011011) begin result = 1'b1; end else begin result = 1'b0; end func6 = result; end endfunction wire [5:0] w6 = {a, b}; always @(posedge clk) begin out <= func6(w6); end assign q = out; endmodule verilator-5.042/test_regress/t/t_runflag_quiet.py0000755000542200017500000000145515101701376022640 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(verilator_flags2=["--binary --quiet"]) test.execute(all_run_flags=["+verilator+quiet"], logfile=test.obj_dir + "/sim__quiet.log") test.file_grep_not(test.obj_dir + "/sim__quiet.log", r'S i m u l a t') #--- test.execute(all_run_flags=[""], logfile=test.obj_dir + "/sim__noquiet.log") test.file_grep(test.obj_dir + "/sim__noquiet.log", r'S i m u l a t') test.passes() verilator-5.042/test_regress/t/t_dpi_export_scope_bad.v0000644000542200017500000000110215101701376023746 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; s s(); import "DPI-C" context function void dpix_run_tests(); initial dpix_run_tests(); endmodule module s; export "DPI-C" task dpix_task; task dpix_task(); $write("Hello in %m\n"); endtask endmodule verilator-5.042/test_regress/t/t_wait_no_triggered_bad.v0000644000542200017500000000066715101701376024113 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; event e_my_event; initial begin #(1us); wait(e_my_event.triggered); // Ok #(1us); wait(e_my_event); // Bad $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_randomize_inline_funclocal.py0000755000542200017500000000073415101701376025346 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_gate_inline_wide_noexclude_arraysel.v0000644000542200017500000000071015101701376027034 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t; logic [255:0] arrd [0:0] = '{ 1 }; logic [255:0] y0; // Do not exclude from inlining wide arraysels. always_comb y0 = arrd[0]; always_comb begin if (y0 != 1 && y0 != 0) begin $stop; end end endmodule verilator-5.042/test_regress/t/t_opt_subst_off.py0000755000542200017500000000122415101701376022641 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.top_filename = "t/t_opt_life.v" test.compile(verilator_flags2=['--stats', '-fno-subst', '-fno-subst-const']) if test.vlt_all: test.file_grep_not(test.stats, r'Optimizations, Substituted temps\s+(\d+)') test.passes() verilator-5.042/test_regress/t/t_class_extends_vsyment.py0000755000542200017500000000070615101701376024415 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.passes() verilator-5.042/test_regress/t/t_interface_asvar_bad.py0000755000542200017500000000076615101701376023741 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_wait_order.v0000644000542200017500000000250615101701376021742 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t; event a, b, c; bit wif[10], welse[10]; bit nif[10], nelse[10]; initial begin wait_order (a, b) wif[0] = '1; end `ifdef FAIL_ASSERT_1 initial begin wait_order (b, a) nif[0] = '1; end `endif initial begin wait_order (a, b) else welse[1] = '1; end initial begin wait_order (b, a) else nelse[1] = '1; end initial begin wait_order (a, b) wif[2] = '1; else welse[2] = '1; end initial begin wait_order (b, a) nif[2] = '1; else nelse[2] = '1; end initial begin #10; -> a; #10; -> b; #10; -> c; #10; `checkd(wif[0], 1'b1); `checkd(nif[0], 1'b0); `checkd(welse[1], 1'b0); `checkd(nelse[1], 1'b1); `checkd(wif[2], 1'b1); `checkd(welse[2], 1'b0); `checkd(nif[2], 1'b0); `checkd(nelse[2], 1'b1); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_assigndly_deep_ref.py0000755000542200017500000000101315101701376023607 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(timing_loop=True, verilator_flags2=['--timing']) test.execute() test.passes() verilator-5.042/test_regress/t/t_unroll_nested.out0000644000542200017500000000144315101701376023021 0ustar mahmoudyfreeshellexit_a 0 0 A0 B0 C0 D0 B1 C1 D1 B2 C2 D2 Y3 Z3 A13 B10 C10 D10 B11 C11 D11 B12 C12 D12 Y13 Z13 A23 B20 C20 D20 B21 C21 D21 B22 C22 D22 Y23 Z23 exit_a 0 1 A0 B0 C0 D0 B1 B2 C2 D2 Y3 Z3 A13 B10 C10 D10 B11 B12 C12 D12 Y13 Z13 A23 B20 C20 D20 B21 B22 C22 D22 Y23 Z23 exit_a 0 2 A0 B0 C0 D0 B1 C1 D1 B2 C2 D2 Y3 Z3 A13 B10 C10 A20 B20 C20 D20 B21 C21 D21 B22 C22 D22 Y23 Z23 exit_a 1 0 A0 B0 C0 D0 B1 C1 D1 B2 C2 D2 Y3 Z3 A13 B10 C10 D10 B11 C11 D11 B12 C12 D12 Y13 A23 B20 C20 D20 B21 C21 D21 B22 C22 D22 Y23 Z23 exit_a 1 1 A0 B0 C0 D0 B1 B2 C2 D2 Y3 Z3 A13 B10 C10 D10 B11 B12 C12 D12 Y13 A23 B20 C20 D20 B21 B22 C22 D22 Y23 Z23 exit_a 1 2 A0 B0 C0 D0 B1 C1 D1 B2 C2 D2 Y3 Z3 A13 B10 C10 A20 B20 C20 D20 B21 C21 D21 B22 C22 D22 Y23 Z23 *-* All Finished *-* verilator-5.042/test_regress/t/t_unpacked_init.v0000644000542200017500000000172515101701376022422 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module t; int a1[2] = '{12, 13}; int a2[2] = {14, 15}; int a3[1] = '{16}; int a4[1] = {17}; int a5[2][3] = '{'{10, 11, 12}, '{13, 14, 15}}; initial begin `checkh(a1[0], 12); `checkh(a1[1], 13); `checkh(a2[0], 14); `checkh(a2[1], 15); `checkh(a3[0], 16); `checkh(a4[0], 17); `checkh(a5[0][0], 10); `checkh(a5[0][1], 11); `checkh(a5[0][2], 12); `checkh(a5[1][0], 13); `checkh(a5[1][1], 14); `checkh(a5[1][2], 15); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_lint_unused_iface_bad.v0000644000542200017500000000074615101701376024075 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface dummy_if (); logic sig_udrv; logic sig_uusd; endinterface: dummy_if module sub ( dummy_if dummy ); assign dummy.sig_uusd = 1'b0 | dummy.sig_udrv; endmodule module t; dummy_if dummy (); sub sub (.dummy(dummy) ); endmodule verilator-5.042/test_regress/t/t_parse_eof_attr_bad.out0000644000542200017500000000030615101701376023744 0ustar mahmoudyfreeshell%Error: t/t_parse_eof_attr_bad.v:7:1: EOF in (* 7 | (* attr | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_fuzz_eof_bad.py0000755000542200017500000000102115101701376022415 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.leak_check_disable() test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_timing_clkgen3.py0000755000542200017500000000077115101701376022670 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_scope_vlt.v0000644000542200017500000000150015101701376022750 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; int cyc; sub1 #(10) sub1a (.*); sub1 #(20) sub1b (.*); always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 10) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module sub1 #(parameter int ADD) (input int cyc); int value; always_comb value = cyc + ADD; sub2 #(ADD + 1) sub2a(.*); sub2 #(ADD + 2) sub2b(.*); sub2 #(ADD + 3) sub2c(.*); endmodule module sub2 #(parameter int ADD) (input int cyc); int value; always_comb value = cyc + ADD; endmodule verilator-5.042/test_regress/t/t_lint_top_bad.out0000644000542200017500000000043315101701376022600 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_lint_top_bad.v:14:8: Module cannot be named 'TOP' as conflicts with Verilator top-level internals 14 | module TOP( | ^~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_class_param_lvalue.v0000644000542200017500000000051715101701376023440 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class Foo; endclass class Bar #(type BASE=Foo) extends BASE; task body(); int v = 0; v = 1; endtask endclass verilator-5.042/test_regress/t/t_case_overlap_bad.out0000644000542200017500000000347115101701376023420 0ustar mahmoudyfreeshell%Warning-CASEOVERLAP: t/t_case_overlap_bad.v:20:21: Case conditions overlap (example pattern 0x6) 20 | 3'b11?, 3'b???: v++; | ^~~~~~ t/t_case_overlap_bad.v:20:13: ... Location of overlapping condition 20 | 3'b11?, 3'b???: v++; | ^~~~~~ ... For warning description see https://verilator.org/warn/CASEOVERLAP?v=latest ... Use "/* verilator lint_off CASEOVERLAP */" and lint_on around source to disable this message. %Warning-CASEOVERLAP: t/t_case_overlap_bad.v:25:13: Case conditions overlap 25 | 3'b001, 3'b000: $stop; | ^~~~~~ t/t_case_overlap_bad.v:24:13: ... Location of overlapping condition 24 | 3'b00?: $stop; | ^~~~~~ %Warning-CASEOVERLAP: t/t_case_overlap_bad.v:30:13: Case conditions overlap (example pattern 0x7) 30 | 3'b11?: $stop; | ^~~~~~ t/t_case_overlap_bad.v:29:13: ... Location of overlapping condition 29 | 3'b111, 3'b0??: v++; | ^~~~~~ %Warning-CASEOVERLAP: t/t_case_overlap_bad.v:35:13: Case conditions overlap 35 | 3'b001: $stop; | ^~~~~~ t/t_case_overlap_bad.v:34:21: ... Location of overlapping condition 34 | 3'b000, 3'b001, 3'b010, 3'b011: v++; | ^~~~~~ %Warning-CASEOVERLAP: t/t_case_overlap_bad.v:40:13: Case conditions overlap 40 | 3'b011: $stop; | ^~~~~~ t/t_case_overlap_bad.v:39:37: ... Location of overlapping condition 39 | 3'b000, 3'b001, 3'b010, 3'b011: v++; | ^~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_vpi_dump_missing_scopes.iv.out0000644000542200017500000000171015101701376025506 0ustar mahmoudyfreeshellt (vpiModule) t vpiInternalScope: t.top_wrap_1 (vpiModule) t.top_wrap_1 vpiInternalScope: t.top_wrap_1.gen_loop[0] (vpiGenScope) t.top_wrap_1.gen_loop[0] vpiParameter: t.top_wrap_1.gen_loop[0].i (vpiParameter) t.top_wrap_1.gen_loop[0].i vpiConstType=vpiBinaryConst vpiInternalScope: t.top_wrap_1.gen_loop[0].after_gen_loop (vpiModule) t.top_wrap_1.gen_loop[0].after_gen_loop t.top_wrap_2 (vpiModule) t.top_wrap_2 vpiInternalScope: t.top_wrap_2.gen_loop[0] (vpiGenScope) t.top_wrap_2.gen_loop[0] vpiParameter: t.top_wrap_2.gen_loop[0].i (vpiParameter) t.top_wrap_2.gen_loop[0].i vpiConstType=vpiBinaryConst vpiInternalScope: t.top_wrap_2.gen_loop[0].after_gen_loop (vpiModule) t.top_wrap_2.gen_loop[0].after_gen_loop *-* All Finished *-* t/t_vpi_dump_missing_scopes.v:21: $finish called at 0 (1s) verilator-5.042/test_regress/t/t_param_width_loc_bad.py0000755000542200017500000000076615101701376023741 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_split_var_auto.v0000644000542200017500000000452215101701376022636 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); module t(/*AUTOARG*/ // Inputs clk ); input clk; logic [31:0] cnt = 0; logic [31:0] out0; logic [31:0] out1; logic [31:0] out2; logic [31:0] out3; // Splittable sub #(.ADDEND(1), .FORCEABLE(1'b0)) sub_0(clk, cnt, out0); // Unsplittable due to hierarchical reference sub #(.ADDEND(2), .FORCEABLE(1'b0)) sub_1(clk, cnt, out1); // Unsplittable due to hiererchical reference sub #(.ADDEND(3), .FORCEABLE(1'b0)) sub_2(clk, cnt, out2); // Unsplittable due to forceable attribute sub #(.ADDEND(4), .FORCEABLE(1'b1)) sub_3(clk, cnt, out3); task print(); // This hierarchical reference should prevent automatic splitting $display("sub_2.gen_else.tmp[9]: %02d", sub_2.gen_else.tmp[9]); endtask always @(posedge clk) begin `checkh(out0, cnt + 32'd10); `checkh(out1, cnt + 32'd20); `checkh(out2, cnt + 32'd30); `checkh(out3, cnt + 32'd40); // This hierarchical reference should prevent automatic splitting $display("sub_1.gen_else.tmp[9]: %02d", sub_1.gen_else.tmp[9]); print(); cnt <= cnt + 32'd1; if (cnt == 20) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module sub #( parameter logic [31:0] ADDEND, parameter logic FORCEABLE ) ( input wire clk, input logic [31:0] i, output logic [31:0] o ); /* verilator lint_off UNOPTFLAT */ // Both branches do the same thing, difference is the 'forceable' attribute if (FORCEABLE) begin : gen_then wire logic [9:0][31:0] tmp /* verilator forceable */; assign tmp[0] = i; for (genvar n = 1; n < 10; ++n) begin assign tmp[n] = tmp[n-1] + ADDEND; end assign o = tmp[9] + ADDEND; end else begin : gen_else wire logic [9:0][31:0] tmp; assign tmp[0] = i; for (genvar n = 1; n < 10; ++n) begin assign tmp[n] = tmp[n-1] + ADDEND; end assign o = tmp[9] + ADDEND; end /* verilator lint_on UNOPTFLAT */ endmodule verilator-5.042/test_regress/t/t_var_dup_bad.py0000755000542200017500000000076315101701376022242 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_gen_genblk.v0000644000542200017500000001321215101701376021672 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define CONCAT(a,b) a``b `define SHOW_LINED `CONCAT(show, `__LINE__) bit fails; module t (/*AUTOARG*/ // Inputs clk, reset_l ); input clk; input reset_l; generate begin : direct_ignored show #(`__LINE__) show1(); if (1) begin check #(`__LINE__, 1) show2(); end end begin : empty_DISAGREE // DISAGREEMENT: if empty unnamed begin/end counts begin end if (1) begin check #(`__LINE__, 0) show2(); end end begin : empty_named_DISAGREE // DISAGREEMENT: if empty named begin/end counts begin : empty_inside_named end if (1) begin check #(`__LINE__, 0) show2(); end end begin : unnamed_counts // DISAGREEMENT: if unnamed begin/end counts begin show #(`__LINE__) show1(); end if (1) begin check #(`__LINE__, 0) show2(); end end begin : named_counts // DISAGREEMENT: if named begin/end counts begin : named show #(`__LINE__) show1(); end if (1) begin check #(`__LINE__, 0) show2(); end end begin : if_direct_counts if (0) ; else if (0) ; else if (1) show #(`__LINE__) show1(); if (1) begin check #(`__LINE__, 2) show2(); end end begin : if_begin_counts if (0) begin end else if (0) begin show #(`__LINE__) show1_NOT(); end else if (1) begin show #(`__LINE__) show1(); end if (1) begin check #(`__LINE__, 2) show2(); end end begin : if_named_counts if (1) begin : named show #(`__LINE__) show1(); if (1) begin : subnamed show #(`__LINE__) show1s(); end end if (1) begin check #(`__LINE__, 2) show2(); end end begin : begin_if_counts begin if (0) begin end else if (0) begin show #(`__LINE__) show1_NOT(); end else if (1) begin show #(`__LINE__) show1(); end end // DISAGREEMENT: this could be genblk01 if (1) begin check #(`__LINE__, 2) show2(); end end begin : for_empty_counts // DISAGREEMENT: if empty genfor counts for (genvar g = 0; g < 1; ++g) ; if (1) begin check #(`__LINE__, 0) show2(); end end begin : for_direct_counts for (genvar g = 0; g < 1; ++g) show #(`__LINE__) show1(); if (1) begin check #(`__LINE__, 2) show2(); end end begin : for_named_counts for (genvar g = 0; g < 1; ++g) begin : fornamed show #(`__LINE__) show1(); end if (1) begin check #(`__LINE__, 2) show2(); end end begin : for_begin_counts for (genvar g = 0; g < 1; ++g) begin show #(`__LINE__) show1(); end if (1) begin check #(`__LINE__, 2) show2(); end end begin : if_if if (0) ; else if (0) begin : namedb end else begin if (0) begin end else if (1) begin show #(`__LINE__) show1(); end end if (1) begin check #(`__LINE__, 2) show2(); end end begin : case_direct case (1) 0 : show #(`__LINE__) show1a_NOT(); 1 : show #(`__LINE__) show1(); 2 : show #(`__LINE__) show1c_NOT(); endcase if (1) begin check #(`__LINE__, 2) show2(); end end begin : case_begin_counts case (1) 0 : begin show #(`__LINE__) show1a_NOT(); end 1 : begin show #(`__LINE__) show1(); end 2 : begin show #(`__LINE__) show1c_NOT(); end endcase if (1) begin check #(`__LINE__, 2) show2(); end end begin : case_named_counts case (1) 0 : begin : subnamed show #(`__LINE__) show1a_NOT(); end 1 : begin : subnamed show #(`__LINE__) show1(); end 2 : begin : subnamed show #(`__LINE__) show1c_NOT(); end endcase if (1) begin check #(`__LINE__, 2) show2(); end end endgenerate int cyc; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 999) begin if (fails) $stop; else $write("*-* All Finished *-*\n"); $finish; end end endmodule module show #(parameter LINE=0) (); // Each instance compares on unique cycle based on line number // so we get deterministic ordering (versus using an initial) always @ (posedge t.clk) begin if (t.cyc == LINE) begin $display("%03d: got=%m", LINE); end end endmodule module check #(parameter LINE=0, parameter EXP=0) (); string mod; int gennum; int pos; always @ (posedge t.clk) begin if (t.cyc == LINE) begin mod = $sformatf("%m"); gennum = 0; for (int pos = 0; pos < mod.len(); ++pos) begin if (mod.substr(pos, pos+5) == "genblk") begin pos += 6; // verilator lint_off WIDTH gennum = mod[pos] - "0"; // verilator lint_on WIDTH break; end end $write("%03d: got=%s exp=%0d gennum=%0d ", LINE, mod, EXP, gennum); if (EXP == 0) $display(" "); else if (gennum != EXP) begin $display (" %%Error"); fails = 1; end else $display; $display; end end endmodule verilator-5.042/test_regress/t/t_constraint_mode_unsup.py0000755000542200017500000000077315101701376024417 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_unoptflat_simple_2_bad.out0000644000542200017500000000207715101701376024564 0ustar mahmoudyfreeshell%Warning-UNOPTFLAT: t/t_unoptflat_simple_2.v:16:15: Signal unoptimizable: Circular combinational logic: 't.x' 16 | wire [2:0] x; | ^ ... For warning description see https://verilator.org/warn/UNOPTFLAT?v=latest ... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message. t/t_unoptflat_simple_2.v:16:15: Example path: t.x t/t_unoptflat_simple_2.v:19:18: Example path: ASSIGNW t/t_unoptflat_simple_2.v:16:15: Example path: t.x ... Widest variables candidate to splitting: t/t_unoptflat_simple_2.v:16:15: t.x, width 3, circular fanout 2, can split_var ... Candidates with the highest fanout: t/t_unoptflat_simple_2.v:16:15: t.x, width 3, circular fanout 2, can split_var ... Suggest add /*verilator split_var*/ or /*verilator isolate_assignments*/ to appropriate variables above. %Error: Exiting due to verilator-5.042/test_regress/t/t_vlt_warn.vlt0000644000542200017500000000154115101701376021775 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `verilator_config lint_off -rule DEPRECATED -file "t/t_vlt_warn.vlt" -lines 14 lint_off -rule CASEINCOMPLETE -file "t/t_vlt_warn.v" lint_off -rule WIDTH -file "t/t_vlt_warn.v" -lines 19 lint_off -rule DECLFILENAME -file "*/t_vlt_warn.v" // Test wildcard filenames lint_off -rule WIDTH -file "*/t_vlt_warn.v" -lines 20-20 // Test global disables lint_off -file "*/t_vlt_warn.v" -lines 21-21 // Test match lint_off -rule UNUSED -file "*/t_vlt_warn.v" -match "Signal is not used: 'width_warn*'" coverage_off -file "t/t_vlt_warn.v" // Test --flag is also accepted tracing_off --file "t/t_vlt_warn.v" verilator-5.042/test_regress/t/t_wire_types.py0000755000542200017500000000107215101701376022160 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.verilated_randReset = 1 # allow checking if we initialize vars to zero only when needed test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_link_delay.v0000644000542200017500000000233515101701376023103 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs someOutput, // Inputs clk, reset_l, InOne, InTwo ); input clk; input reset_l; input InOne, InTwo; output logic someOutput; typedef enum { STATE_ONE, STATE_TWO, STATE_THREE, STATE_FOUR } some_state_t; some_state_t some_FSM; always_ff @ (posedge clk or negedge reset_l) begin if(!reset_l) some_FSM <= some_FSM.first; else begin unique case (some_FSM) STATE_ONE, STATE_TWO, STATE_THREE: begin if(InOne & InTwo) some_FSM <= some_FSM.next; else if(InOne) some_FSM <= some_FSM; else some_FSM <= some_FSM.first; end default: begin some_FSM <= STATE_ONE; end endcase end end always_comb begin someOutput = (some_FSM == STATE_FOUR); end endmodule verilator-5.042/test_regress/t/t_func_task_bad.out0000644000542200017500000000104615101701376022726 0ustar mahmoudyfreeshell%Error: t/t_func_task_bad.v:10:9: Cannot call a task/void-function as a function: 'a_task' : ... note: In instance 't' 10 | if (a_task(1'b0)) $stop; | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_func_task_bad.v:10:5: Logical operator IF expects a non-complex data type on the If. : ... note: In instance 't' 10 | if (a_task(1'b0)) $stop; | ^~ %Error: Exiting due to verilator-5.042/test_regress/t/t_class_new_ref_bad.v0000644000542200017500000000121115101701376023213 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Base; endclass class Cls extends Base; typedef int txn_type_t; // Bad type rand txn_type_t req_txn_type; static function txn_type_t generate_txn(); txn_type_t txn = new; txn_type_t copy = new txn; return txn; endfunction endclass module t; initial begin Base b = Cls::generate_txn(); $display("%p", b); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_vlt_legacy.v0000644000542200017500000000045215101701376021732 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( input clk /*verilator clock_enable*/ ); initial $finish; endmodule verilator-5.042/test_regress/t/t_enum_bad_dup.out0000644000542200017500000000065415101701376022571 0ustar mahmoudyfreeshell%Error: t/t_enum_bad_dup.v:10:19: Duplicate declaration of enum value: DUP_VALUE 10 | DUP_VALUE = 3 | ^~~~~~~~~ t/t_enum_bad_dup.v:9:19: ... Location of original declaration 9 | typedef enum { DUP_VALUE = 2, | ^~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_math_const.py0000755000542200017500000000073415101701376022131 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_tri_select.v0000644000542200017500000000214615101701376021740 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2008 by Lane Brooks. // SPDX-License-Identifier: CC0-1.0 `define WIDTH 2 module top ( input OE1, input OE2, input [`WIDTH-1:0] A1, input [`WIDTH-1:0] A2, output [`WIDTH-1:0] Y1, output [`WIDTH-1:0] Y2, output [`WIDTH-1:0] Y3, output [`WIDTH**2-1:0] W); assign W[A1] = (OE2) ? A2[0] : 1'bz; assign W[A2] = (OE1) ? A2[1] : 1'bz; // have 2 different 'chips' drive the PAD to act like a bi-directional bus wire [`WIDTH-1:0] PAD; io_ring io_ring1 (.OE(OE1), .A(A1), .O(Y1), .PAD(PAD)); io_ring io_ring2 (.OE(OE2), .A(A2), .O(Y2), .PAD(PAD)); assign Y3 = PAD; pullup p1(PAD); // pulldown p1(PAD); wire [5:0] fill = { 4'b0, A1 }; endmodule module io_ring (input OE, input [`WIDTH-1:0] A, output [`WIDTH-1:0] O, inout [`WIDTH-1:0] PAD); io io[`WIDTH-1:0] (.OE(OE), .I(A), .O(O), .PAD(PAD)); endmodule module io (input OE, input I, output O, inout PAD); assign O = PAD; assign PAD = OE ? I : 1'bz; endmodule verilator-5.042/test_regress/t/t_castdyn.v0000644000542200017500000000306715101701376021253 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Base; endclass class BasedA extends Base; endclass class BasedB extends Base; static function BasedB getBasedB(bit getNull); BasedB b = new; return getNull ? null : b; endfunction endclass module t; int i; int a; int ao; Base b; Base bo; BasedA ba; BasedA bao; BasedB bb; BasedB bbo; // verilator lint_off CASTCONST initial begin a = 1234; i = $cast(ao, a); if (i != 1) $stop; if (ao != 1234) $stop; a = 12345; $cast(ao, a); if (ao != 12345) $stop; i = $cast(ao, 2.1 * 3.7); if (i != 1) $stop; if (ao != 8) $stop; i = $cast(bo, null); if (i != 1) $stop; if (bo != null) $stop; ba = new; b = ba; i = $cast(bao, b); if (i != 1) $stop; if (b != ba) $stop; bb = new; b = bb; i = $cast(bbo, b); if (i != 1) $stop; if (b != bb) $stop; bb = null; b = bb; i = $cast(bbo, b); if (i != 1) $stop; if (b != bb) $stop; bb = BasedB::getBasedB(1); b = bb; i = $cast(bbo, b); if (i != 1) $stop; if (b != bb) $stop; bb = new; b = bb; bao = ba; i = $cast(bao, b); if (i != 0) $stop; if (bao != ba) $stop; // Unchanged $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_hier_block_vlt.vlt0000644000542200017500000000046015101701376023126 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by Yutetsu TAKATSUKASA // SPDX-License-Identifier: Unlicense `verilator_config hier_block -module "sub?" hier_block -module "delay" // matches recursive modules verilator-5.042/test_regress/t/t_net_delay_timing_sc.py0000755000542200017500000000113515101701376023766 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_net_delay.v" test.main_time_multiplier = 2 test.compile(verilator_flags2=["--sc --exe --timing --timescale 10ps/1ps"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_nest_noinl.py0000755000542200017500000000103715101701376024157 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_nest.v" test.compile(v_flags2=["-fno-inline"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_hier_block_trace_vcd.py0000755000542200017500000000211015101701376024073 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_hier_block.v" # CI environment offers 2 VCPUs, 2 thread setting causes the following warning. # %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. # So use 6 threads here though it's not optimal in performance, but ok. test.compile( v_flags2=['t/t_hier_block.cpp'], verilator_flags2=[ '--hierarchical', '--Wno-TIMESCALEMOD', '--trace-vcd', '--no-trace-underscore', # To avoid handle mismatches ], threads=(6 if test.vltmt else 1)) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_hier_block_perf.py0000755000542200017500000000420215101701376023101 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.init_benchmarksim() test.cycles = (int(test.benchmark) if test.benchmark else 100000) test.sim_time = test.cycles * 10 + 1000 THREADS = 2 HIER_BLOCK_THREADS = 2 HIER_THREADS = 4 config_file = test.t_dir + "/" + test.name + ".vlt" test.compile( benchmarksim=1, v_flags2=[ config_file, "+define+SIM_CYCLES=" + str(test.cycles), "--prof-exec", "--hierarchical", "--stats", "-Wno-UNOPTFLAT", (f"-DWORKERS={HIER_BLOCK_THREADS}" if test.vltmt and HIER_BLOCK_THREADS > 1 else ""), (f"--hierarchical-threads {HIER_THREADS}" if test.vltmt and HIER_THREADS > 1 else "") ], threads=(THREADS if test.vltmt else 1), context_threads=(HIER_THREADS if test.vltmt else 1)) test.file_grep(test.obj_dir + "/V" + test.name + "__hier.dir/V" + test.name + "__stats.txt", r'Optimizations, Hierarchical DPI wrappers with costs\s+(\d+)', 6) if test.vltmt: test.file_grep(test.obj_dir + "/V" + test.name + "__hier.dir/V" + test.name + "__stats.txt", r'Optimizations, Thread schedule count\s+(\d+)', 1) test.file_grep(test.obj_dir + "/V" + test.name + "__hier.dir/V" + test.name + "__stats.txt", r'Optimizations, Thread schedule total tasks\s+(\d+)', 2) test.execute(all_run_flags=[ "+verilator+prof+exec+start+2", " +verilator+prof+exec+window+2", " +verilator+prof+exec+file+" + test.obj_dir + "/profile_exec.dat", " +verilator+prof+vlt+file+" + test.obj_dir + "/profile.vlt"]) # yapf:disable gantt_log = test.obj_dir + "/gantt.log" test.run(cmd=[ os.environ["VERILATOR_ROOT"] + "/bin/verilator_gantt", test.obj_dir + "/profile_exec.dat", "--vcd " + test.obj_dir + "/profile_exec.vcd", "| tee " + gantt_log ]) test.passes() verilator-5.042/test_regress/t/t_trace_complex_fst_threads_1.py0000755000542200017500000000125715101701376025426 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_complex.v" test.golden_filename = "t/t_trace_complex_fst.out" test.compile(verilator_flags2=['--cc --trace-fst --trace-threads 1']) test.execute() test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dfg_break_cycles.py0000755000542200017500000001036415101701376023240 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap import os test.scenarios('vlt_all') test.sim_time = 2000000 if not os.path.exists(test.root + "/.git"): test.skip("Not in a git repository") # Read expected source lines hit expectedLines = set() with open(test.root + "/src/V3DfgBreakCycles.cpp", 'r', encoding="utf8") as fd: for lineno, line in enumerate(fd, 1): line = line.split("//")[0] if re.match(r'^[^#]*SET_RESULT', line): expectedLines.add(lineno) if re.match(r'^[^#]*MASK', line): expectedLines.add(lineno) if not expectedLines: test.error("Failed to read expected source line numbers") # Generate the equivalence checks and declaration boilerplate rdFile = test.top_filename plistFile = test.obj_dir + "/portlist.vh" pdeclFile = test.obj_dir + "/portdecl.vh" checkFile = test.obj_dir + "/checks.h" nExpectedCycles = 0 with open(rdFile, 'r', encoding="utf8") as rdFh, \ open(plistFile, 'w', encoding="utf8") as plistFh, \ open(pdeclFile, 'w', encoding="utf8") as pdeclFh, \ open(checkFile, 'w', encoding="utf8") as checkFh: for line in rdFh: line, _, cmt = line.partition("//") cmt, _, _ = cmt.partition("//") if "UNOPTFLAT" in cmt: nExpectedCycles += 1 m = re.search(r'`signal\((\w+),', line) if not m: continue sig = m.group(1) plistFh.write(sig + ",\n") pdeclFh.write("output " + sig + ";\n") checkFh.write("if (ref." + sig + " != opt." + sig + ") {\n") checkFh.write(" std::cout << \"Mismatched " + sig + "\" << std::endl;\n") checkFh.write(" std::cout << \"Ref: 0x\" << std::hex << (ref." + sig + " + 0) << std::endl;\n") checkFh.write(" std::cout << \"Opt: 0x\" << std::hex << (opt." + sig + " + 0) << std::endl;\n") checkFh.write(" std::exit(1);\n") checkFh.write("}\n") # Compile un-optimized test.compile(verilator_flags2=[ "--stats", "--build", "-fno-dfg-break-cycles", "+incdir+" + test.obj_dir, "-Mdir", test.obj_dir + "/obj_ref", "--prefix", "Vref", "-Wno-UNOPTFLAT" ]) # yapf:disable # Check we got the expected number of circular logic warnings test.file_grep(test.obj_dir + "/obj_ref/Vref__stats.txt", r'Warnings, Suppressed UNOPTFLAT\s+(\d+)', nExpectedCycles) # Compile optimized - also builds executable test.compile(verilator_flags2=[ "--stats", "--build", "-fno-dfg-post-inline", "-fno-dfg-scoped", "--exe", "+incdir+" + test.obj_dir, "-Mdir", test.obj_dir + "/obj_opt", "--prefix", "Vopt", "-Werror-UNOPTFLAT", "--dumpi-V3DfgBreakCycles", "9", # To fill code coverage "--debug", "--debugi", "0", "--dumpi-tree", "0", "-CFLAGS \"-I .. -I ../obj_ref\"", "../obj_ref/Vref__ALL.a", "../../t/" + test.name + ".cpp" ]) # yapf:disable # Check all source lines hit coveredLines = set() def readCovered(fileName): if not os.path.exists(fileName): test.error_keep_going("Missing coverage file: " + fileName) return with open(fileName, 'r', encoding="utf8") as fd: for line in fd: coveredLines.add(int(line.strip())) readCovered(test.obj_dir + "/obj_opt/Vopt__V3DfgBreakCycles-TraceDriver-line-coverage.txt") readCovered(test.obj_dir + "/obj_opt/Vopt__V3DfgBreakCycles-IndependentBits-line-coverage.txt") if coveredLines != expectedLines: for n in sorted(expectedLines - coveredLines): test.error_keep_going(f"V3DfgBreakCycles.cpp line {n} not covered") for n in sorted(coveredLines - expectedLines): test.error_keep_going(f"V3DfgBreakCycles.cpp line {n} covered but not expected") test.file_grep_not(test.obj_dir + "/obj_opt/Vopt__stats.txt", r'DFG.*non-representable.*\s[1-9]\d*$') # Execute test to check equivalence test.execute(executable=test.obj_dir + "/obj_opt/Vopt") test.passes() verilator-5.042/test_regress/t/t_dpi_arg_input_type.cpp0000644000542200017500000004622715101701376024015 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2020 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include #include #include // clang-format off #if defined(NCSC) // Used by NC's svdpi.h to pick up svLogicVecVal with _.aval and _.bval fields, // rather than the IEEE 1800-2005 version which has _.a and _.b fields. # define DPI_COMPATIBILITY_VERSION_1800v2012 #endif #include "svdpi.h" #if defined(VERILATOR) // Verilator # include "Vt_dpi_arg_input_type__Dpi.h" typedef long long sv_longint_t; typedef unsigned long long sv_longint_unsigned_t; # define NO_SHORTREAL # define CONSTARG const #elif defined(VCS) // VCS # include "../vc_hdrs.h" typedef long long sv_longint_t; typedef unsigned long long sv_longint_unsigned_t; # define NO_TIME # define CONSTARG const #elif defined(NCSC) // NC # include "dpi-exp.h" # include "dpi-imp.h" typedef long long sv_longint_t; typedef unsigned long long sv_longint_unsigned_t; # define NO_TIME # define NO_INTEGER # define NO_SHORTREAL // Sadly NC does not declare pass-by reference input arguments as const # define CONSTARG #elif defined(MS) // ModelSim # include "dpi.h" typedef int64_t sv_longint_t; typedef uint64_t sv_longint_unsigned_t; # define CONSTARG const #else # error "Unknown simulator for DPI test" #endif // clang-format on //====================================================================== // Implementations of imported functions //====================================================================== #define stop() \ do { \ printf(__FILE__ ":%d Bad value\n", __LINE__); \ abort(); \ } while (0) void check_bvals(CONSTARG svLogicVecVal* v, unsigned n); void check_bvals(CONSTARG svLogicVecVal* v, unsigned n) { for (unsigned i = 0; i < n; i++) { if (v[i].bval != 0) { printf(__FILE__ ":%d Bad svLogicVecVal bval\n", __LINE__); abort(); } } } // Basic types as per IEEE 1800-2023 35.5.6 void i_byte(char i) { static int n = 0; if (i != 10 - n++) stop(); } void i_byte_unsigned(unsigned char i) { static int n = 0; if (i != 20 - n++) stop(); } void i_shortint(short i) { static int n = 0; if (i != 30 - n++) stop(); } void i_shortint_unsigned(unsigned short i) { static int n = 0; if (i != 40 - n++) stop(); } void i_int(int i) { static int n = 0; if (i != 50 - n++) stop(); } void i_int_unsigned(unsigned i) { static int n = 0; if (i != 60 - n++) stop(); } void i_longint(sv_longint_t i) { static int n = 0; if (i != 70 - n++) stop(); } void i_longint_unsigned(sv_longint_unsigned_t i) { static int n = 0; if (i != 80 - n++) stop(); } #ifndef NO_TIME void i_time(CONSTARG svLogicVecVal* i) { static int n = 0; if (i[0].aval != 90 - n++) stop(); if (i[1].aval != 0) stop(); check_bvals(i, 2); } #endif #ifndef NO_INTEGER void i_integer(CONSTARG svLogicVecVal* i) { static int n = 0; if (i[0].aval != 100 - n++) stop(); check_bvals(i, 1); } #endif void i_real(double i) { static int n = 0; if (i != (-2.0 * n++ - 1.0) / 2.0) stop(); } #ifndef NO_SHORTREAL void i_shortreal(float i) { static int n = 0; if (i != (-4.0f * n++ - 1.0f) / 4.0f) stop(); } #endif void i_chandle(void* i) { static int n = 0; printf("i_chandle %d\n", n); if (i) stop(); n++; } void i_string(const char* i) { static int n = 0; printf("i_string %d\n", n); if (n++ % 2 == 0) { if (std::strcmp(i, "World") != 0) stop(); } else { if (std::strcmp(i, "Hello") != 0) stop(); } } void i_bit(svBit i) { static int n = 0; printf("i_bit %d\n", n); if (i != !(n++ % 2)) stop(); } void i_logic(svLogic i) { static int n = 0; printf("i_logic %d\n", n); if (i != n++ % 2) stop(); } // Basic types via typedefs void i_byte_t(char i) { static int n = 0; if (i != 10 - n) stop(); n += 2; } void i_byte_unsigned_t(unsigned char i) { static int n = 0; if (i != 20 - n) stop(); n += 2; } void i_shortint_t(short i) { static int n = 0; if (i != 30 - n) stop(); n += 2; } void i_shortint_unsigned_t(unsigned short i) { static int n = 0; if (i != 40 - n) stop(); n += 2; } void i_int_t(int i) { static int n = 0; if (i != 50 - n) stop(); n += 2; } void i_int_unsigned_t(unsigned i) { static int n = 0; if (i != 60 - n) stop(); n += 2; } void i_longint_t(sv_longint_t i) { static int n = 0; if (i != 70 - n) stop(); n += 2; } void i_longint_unsigned_t(sv_longint_unsigned_t i) { static int n = 0; if (i != 80 - n) stop(); n += 2; } #ifndef NO_TIME void i_time_t(CONSTARG svLogicVecVal* i) { static int n = 0; if (i[0].aval != 90 - n) stop(); if (i[1].aval != 0) stop(); check_bvals(i, 2); n += 2; } #endif #ifndef NO_INTEGER void i_integer_t(CONSTARG svLogicVecVal* i) { static int n = 0; if (i[0].aval != 100 - n) stop(); check_bvals(i, 1); n += 2; } #endif void i_real_t(double i) { static int n = 0; if (i != (-2.0 * n - 1.0) / 2.0) stop(); n += 2; } #ifndef NO_SHORTREAL void i_shortreal_t(float i) { static int n = 0; if (i != (-4.0f * n - 1.0f) / 4.0f) stop(); n += 2; } #endif void i_chandle_t(void* i) { static int n = 0; printf("i_chandle_t %d\n", n); if (i) stop(); n++; } void i_string_t(const char* i) { static int n = 0; printf("i_string_t %d\n", n); if (n++ % 2 == 0) { if (std::strcmp(i, "World") != 0) stop(); } else { if (std::strcmp(i, "Hello") != 0) stop(); } } void i_bit_t(svBit i) { static int n = 0; printf("i_bit_t %d\n", n); if (i != !(n++ % 2)) stop(); } void i_logic_t(svLogic i) { static int n = 0; printf("i_logic_t %d\n", n); if (i != n++ % 2) stop(); } // 2-state packed arrays void i_array_2_state_1(CONSTARG svBitVecVal* i) { static int n = 0; printf("i_array_2_state_1 %d\n", n); if ((*i & 1) != !(n++ % 2)) stop(); } void i_array_2_state_32(CONSTARG svBitVecVal* i) { static int n = 0; printf("i_array_2_state_32 %d\n", n); if (*i != 0xffffffffU << n++) stop(); } void i_array_2_state_33(CONSTARG svBitVecVal* i) { static int n = 0; printf("i_array_2_state_33 %d\n", n); if (i[0] != 0xffffffffU << n++) stop(); if ((i[1] & 1) != 1) stop(); } void i_array_2_state_64(CONSTARG svBitVecVal* i) { static int n = 0; printf("i_array_2_state_64 %d\n", n); if (i[0] != 0xffffffffU << n++) stop(); if (i[1] != -1) stop(); } void i_array_2_state_65(CONSTARG svBitVecVal* i) { static int n = 0; printf("i_array_2_state_65 %d\n", n); if (i[0] != 0xffffffffU << n++) stop(); if (i[1] != -1) stop(); if ((i[2] & 1) != 1) stop(); } void i_array_2_state_128(CONSTARG svBitVecVal* i) { static int n = 0; printf("i_array_2_state_128 %d\n", n); if (i[0] != 0xffffffffU << n++) stop(); if (i[1] != -1) stop(); if (i[2] != -1) stop(); if (i[3] != -1) stop(); } // 2-state packed structures void i_struct_2_state_1(CONSTARG svBitVecVal* i) { static int n = 0; printf("i_struct_2_state_1 %d\n", n); if ((*i & 1) != !(n++ % 2)) stop(); } void i_struct_2_state_32(CONSTARG svBitVecVal* i) { static int n = 0; printf("i_struct_2_state_32 %d\n", n); if (*i != 0xffffffffU << n++) stop(); } void i_struct_2_state_33(CONSTARG svBitVecVal* i) { static int n = 0; printf("i_struct_2_state_33 %d\n", n); if (i[0] != 0xffffffffU << n++) stop(); if ((i[1] & 1) != 1) stop(); } void i_struct_2_state_64(CONSTARG svBitVecVal* i) { static int n = 0; printf("i_struct_2_state_64 %d\n", n); if (i[0] != 0xffffffffU << n++) stop(); if (i[1] != -1) stop(); } void i_struct_2_state_65(CONSTARG svBitVecVal* i) { static int n = 0; printf("i_struct_2_state_65 %d\n", n); if (i[0] != 0xffffffffU << n++) stop(); if (i[1] != -1) stop(); if ((i[2] & 1) != 1) stop(); } void i_struct_2_state_128(CONSTARG svBitVecVal* i) { static int n = 0; printf("i_struct_2_state_128 %d\n", n); if (i[0] != 0xffffffffU << n++) stop(); if (i[1] != -1) stop(); if (i[2] != -1) stop(); if (i[3] != -1) stop(); } // 2-state packed unions void i_union_2_state_1(CONSTARG svBitVecVal* i) { static int n = 0; printf("i_union_2_state_1 %d\n", n); if ((*i & 1) != !(n++ % 2)) stop(); } void i_union_2_state_32(CONSTARG svBitVecVal* i) { static int n = 0; printf("i_union_2_state_32 %d\n", n); if (*i != 0xffffffffU << n++) stop(); } void i_union_2_state_33(CONSTARG svBitVecVal* i) { static int n = 0; printf("i_union_2_state_33 %d\n", n); if (i[0] != 0xffffffffU << n++) stop(); if ((i[1] & 1) != 1) stop(); } void i_union_2_state_64(CONSTARG svBitVecVal* i) { static int n = 0; printf("i_union_2_state_64 %d\n", n); if (i[0] != 0xffffffffU << n++) stop(); if (i[1] != -1) stop(); } void i_union_2_state_65(CONSTARG svBitVecVal* i) { static int n = 0; printf("i_union_2_state_65 %d\n", n); if (i[0] != 0xffffffffU << n++) stop(); if (i[1] != -1) stop(); if ((i[2] & 1) != 1) stop(); } void i_union_2_state_128(CONSTARG svBitVecVal* i) { static int n = 0; printf("i_union_2_state_128 %d\n", n); if (i[0] != 0xffffffffU << n++) stop(); if (i[1] != -1) stop(); if (i[2] != -1) stop(); if (i[3] != -1) stop(); } // 4-state packed arrays void i_array_4_state_1(CONSTARG svLogicVecVal* i) { static int n = 0; printf("i_array_4_state_1 %d\n", n); if ((i->aval & 1) != !(n++ % 2)) stop(); check_bvals(i, 1); } void i_array_4_state_32(CONSTARG svLogicVecVal* i) { static int n = 0; printf("i_array_4_state_32 %d\n", n); if (i->aval != 0xffffffffU << n++) stop(); check_bvals(i, 1); } void i_array_4_state_33(CONSTARG svLogicVecVal* i) { static int n = 0; printf("i_array_4_state_33 %d\n", n); if (i[0].aval != 0xffffffffU << n++) stop(); if ((i[1].aval & 1) != 1) stop(); check_bvals(i, 2); } void i_array_4_state_64(CONSTARG svLogicVecVal* i) { static int n = 0; printf("i_array_4_state_64 %d\n", n); if (i[0].aval != 0xffffffffU << n++) stop(); if (i[1].aval != -1) stop(); check_bvals(i, 2); } void i_array_4_state_65(CONSTARG svLogicVecVal* i) { static int n = 0; printf("i_array_4_state_65 %d\n", n); if (i[0].aval != 0xffffffffU << n++) stop(); if (i[1].aval != -1) stop(); if ((i[2].aval & 1) != 1) stop(); check_bvals(i, 3); } void i_array_4_state_128(CONSTARG svLogicVecVal* i) { static int n = 0; printf("i_array_4_state_128 %d\n", n); if (i[0].aval != 0xffffffffU << n++) stop(); if (i[1].aval != -1) stop(); if (i[2].aval != -1) stop(); if (i[3].aval != -1) stop(); check_bvals(i, 4); } // 4-state packed structures void i_struct_4_state_1(CONSTARG svLogicVecVal* i) { static int n = 0; printf("i_struct_4_state_1 %d\n", n); if ((i->aval & 1) != !(n++ % 2)) stop(); check_bvals(i, 1); } void i_struct_4_state_32(CONSTARG svLogicVecVal* i) { static int n = 0; printf("i_struct_4_state_32 %d\n", n); if (i->aval != 0xffffffffU << n++) stop(); check_bvals(i, 1); } void i_struct_4_state_33(CONSTARG svLogicVecVal* i) { static int n = 0; printf("i_struct_4_state_33 %d\n", n); if (i[0].aval != 0xffffffffU << n++) stop(); if ((i[1].aval & 1) != 1) stop(); check_bvals(i, 2); } void i_struct_4_state_64(CONSTARG svLogicVecVal* i) { static int n = 0; printf("i_struct_4_state_64 %d\n", n); if (i[0].aval != 0xffffffffU << n++) stop(); if (i[1].aval != -1) stop(); check_bvals(i, 2); } void i_struct_4_state_65(CONSTARG svLogicVecVal* i) { static int n = 0; printf("i_struct_4_state_65 %d\n", n); if (i[0].aval != 0xffffffffU << n++) stop(); if (i[1].aval != -1) stop(); if ((i[2].aval & 1) != 1) stop(); check_bvals(i, 3); } void i_struct_4_state_128(CONSTARG svLogicVecVal* i) { static int n = 0; printf("i_struct_4_state_128 %d\n", n); if (i[0].aval != 0xffffffffU << n++) stop(); if (i[1].aval != -1) stop(); if (i[2].aval != -1) stop(); if (i[3].aval != -1) stop(); check_bvals(i, 4); } // 4-state packed unions void i_union_4_state_1(CONSTARG svLogicVecVal* i) { static int n = 0; printf("i_union_4_state_1 %d\n", n); if ((i->aval & 1) != !(n++ % 2)) stop(); check_bvals(i, 1); } void i_union_4_state_32(CONSTARG svLogicVecVal* i) { static int n = 0; printf("i_union_4_state_32 %d\n", n); if (i->aval != 0xffffffffU << n++) stop(); check_bvals(i, 1); } void i_union_4_state_33(CONSTARG svLogicVecVal* i) { static int n = 0; printf("i_union_4_state_33 %d\n", n); if (i[0].aval != 0xffffffffU << n++) stop(); if ((i[1].aval & 1) != 1) stop(); check_bvals(i, 2); } void i_union_4_state_64(CONSTARG svLogicVecVal* i) { static int n = 0; printf("i_union_4_state_64 %d\n", n); if (i[0].aval != 0xffffffffU << n++) stop(); if (i[1].aval != -1) stop(); check_bvals(i, 2); } void i_union_4_state_65(CONSTARG svLogicVecVal* i) { static int n = 0; printf("i_union_4_state_65 %d\n", n); if (i[0].aval != 0xffffffffU << n++) stop(); if (i[1].aval != -1) stop(); if ((i[2].aval & 1) != 1) stop(); check_bvals(i, 3); } void i_union_4_state_128(CONSTARG svLogicVecVal* i) { static int n = 0; printf("i_union_4_state_128 %d\n", n); if (i[0].aval != 0xffffffffU << n++) stop(); if (i[1].aval != -1) stop(); if (i[2].aval != -1) stop(); if (i[3].aval != -1) stop(); check_bvals(i, 4); } //====================================================================== // Check exported functions //====================================================================== void set_bvals(svLogicVecVal* v, unsigned n); void set_bvals(svLogicVecVal* v, unsigned n) { for (unsigned i = 0; i < n; i++) v[i].bval = 0; } void check_exports() { static int n = 0; #ifndef NO_TIME svLogicVecVal x_time[2]; svLogicVecVal x_time_t[2]; #endif #ifndef NO_INTEGER svLogicVecVal x_integer[1]; svLogicVecVal x_integer_t[1]; #endif #ifndef NO_TIME set_bvals(x_time, 2); set_bvals(x_time_t, 2); #endif #ifndef NO_INTEGER set_bvals(x_integer, 1); set_bvals(x_integer_t, 1); #endif // Basic types as per IEEE 1800-2023 35.5.6 e_byte(10 + n); e_byte_unsigned(20 + n); e_shortint(30 + n); e_shortint_unsigned(40 + n); e_int(50 + n); e_int_unsigned(60 + n); e_longint(70 + n); e_longint_unsigned(80 + n); #ifndef NO_TIME x_time[0].aval = 90 + n; x_time[1].aval = 0; e_time(x_time); #endif #ifndef NO_INTEGER x_integer[0].aval = 100 + n; e_integer(x_integer); #endif e_real(1.0 * n + 0.5); #ifndef NO_SHORTREAL e_shortreal(1.0f * n + 0.25f); #endif e_chandle((n % 2) ? reinterpret_cast(&e_chandle) : NULL); e_string((n % 2) ? "World" : "Hello"); e_bit(n % 2); e_logic(!(n % 2)); // Basic types via tyepdef e_byte_t(10 + 2 * n); e_byte_unsigned_t(20 + 2 * n); e_shortint_t(30 + 2 * n); e_shortint_unsigned_t(40 + 2 * n); e_int_t(50 + 2 * n); e_int_unsigned_t(60 + 2 * n); e_longint_t(70 + 2 * n); e_longint_unsigned_t(80 + 2 * n); #ifndef NO_TIME x_time_t[0].aval = 90 + 2 * n; x_time_t[1].aval = 0; e_time_t(x_time_t); #endif #ifndef NO_INTEGER x_integer_t[0].aval = 100 + 2 * n; e_integer_t(x_integer_t); #endif e_real_t(1.0 * (2 * n) + 0.5); #ifndef NO_SHORTREAL e_shortreal_t(1.0f * (2 * n) + 0.25f); #endif e_chandle_t((n % 2) ? NULL : reinterpret_cast(&e_chandle_t)); e_string_t((n % 2) ? "Hello" : "World"); e_bit_t(n % 2); e_logic_t(!(n % 2)); const int m = n == 0 ? 0 : n - 1; svBitVecVal b1[1]; svBitVecVal b2[2]; svBitVecVal b3[3]; svBitVecVal b4[4]; b3[0] = 0xffffffff; b4[0] = 0xffffffff; b4[1] = 0xffffffff; b4[2] = 0xffffffff; // 2-state packed arrays b1[0] = n % 2; e_array_2_state_1(b1); b1[0] = 0xffffffff >> n; e_array_2_state_32(b1); b2[1] = 1 >> n; b2[0] = 0xffffffff >> m; e_array_2_state_33(b2); b2[1] = 0xffffffff >> n; b2[0] = 0xffffffff; e_array_2_state_64(b2); b3[2] = 1 >> n; b3[1] = 0xffffffff >> m; e_array_2_state_65(b3); b4[3] = 0xffffffff >> n; e_array_2_state_128(b4); // 2-state packed structures b1[0] = n % 2; e_struct_2_state_1(b1); b1[0] = 0xffffffff >> n; e_struct_2_state_32(b1); b2[1] = 1 >> n; b2[0] = 0xffffffff >> m; e_struct_2_state_33(b2); b2[1] = 0xffffffff >> n; b2[0] = 0xffffffff; e_struct_2_state_64(b2); b3[2] = 1 >> n; b3[1] = 0xffffffff >> m; e_struct_2_state_65(b3); b4[3] = 0xffffffff >> n; e_struct_2_state_128(b4); // 2-state packed unions b1[0] = n % 2; e_union_2_state_1(b1); b1[0] = 0xffffffff >> n; e_union_2_state_32(b1); b2[1] = 1 >> n; b2[0] = 0xffffffff >> m; e_union_2_state_33(b2); b2[1] = 0xffffffff >> n; b2[0] = 0xffffffff; e_union_2_state_64(b2); b3[2] = 1 >> n; b3[1] = 0xffffffff >> m; e_union_2_state_65(b3); b4[3] = 0xffffffff >> n; e_union_2_state_128(b4); svLogicVecVal l1[1]; svLogicVecVal l2[2]; svLogicVecVal l3[3]; svLogicVecVal l4[4]; // bvals should be ignored, leave them un-initialized set_bvals(l1, 1); set_bvals(l2, 2); set_bvals(l3, 3); set_bvals(l4, 4); l3[0].aval = 0xffffffff; l4[0].aval = 0xffffffff; l4[1].aval = 0xffffffff; l4[2].aval = 0xffffffff; // 4-state packed arrays l1[0].aval = n % 2; e_array_4_state_1(l1); l1[0].aval = 0xffffffff >> n; e_array_4_state_32(l1); l2[1].aval = 1 >> n; l2[0].aval = 0xffffffff >> m; e_array_4_state_33(l2); l2[1].aval = 0xffffffff >> n; l2[0].aval = 0xffffffff; e_array_4_state_64(l2); l3[2].aval = 1 >> n; l3[1].aval = 0xffffffff >> m; e_array_4_state_65(l3); l4[3].aval = 0xffffffff >> n; e_array_4_state_128(l4); // 4-state packed structures l1[0].aval = n % 2; e_struct_4_state_1(l1); l1[0].aval = 0xffffffff >> n; e_struct_4_state_32(l1); l2[1].aval = 1 >> n; l2[0].aval = 0xffffffff >> m; e_struct_4_state_33(l2); l2[1].aval = 0xffffffff >> n; l2[0].aval = 0xffffffff; e_struct_4_state_64(l2); l3[2].aval = 1 >> n; l3[1].aval = 0xffffffff >> m; e_struct_4_state_65(l3); l4[3].aval = 0xffffffff >> n; e_struct_4_state_128(l4); // 4-state packed unions l1[0].aval = n % 2; e_union_4_state_1(l1); l1[0].aval = 0xffffffff >> n; e_union_4_state_32(l1); l2[1].aval = 1 >> n; l2[0].aval = 0xffffffff >> m; e_union_4_state_33(l2); l2[1].aval = 0xffffffff >> n; l2[0].aval = 0xffffffff; e_union_4_state_64(l2); l3[2].aval = 1 >> n; l3[1].aval = 0xffffffff >> m; e_union_4_state_65(l3); l4[3].aval = 0xffffffff >> n; e_union_4_state_128(l4); n++; } verilator-5.042/test_regress/t/t_interface_wrong_bad.out0000644000542200017500000000055715101701376024133 0ustar mahmoudyfreeshell%Error: t/t_interface_wrong_bad.v:32:8: Port 'foo_port' expects 'foo_intf' interface but pin connects 'bar_intf' interface : ... note: In instance 't' 32 | .foo_port (bar) | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_trace_no_top_name2.v0000644000542200017500000000122615101701376023337 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package foo_pkg; function int foo_func; input int b; int b_current; return 0; endfunction endpackage module sub; int a = 1212; endmodule module t (/*AUTOARG*/ // Inputs clk ); input clk; int cyc; import foo_pkg::*; sub sub(); always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 10) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_timing_dlyassign.py0000755000542200017500000000077115101701376023337 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_randomize_complex_arrays.v0000644000542200017500000000247015101701376024703 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class SubClass; rand bit [2:0] field; function new (); field = 0; endfunction endclass class MyClass; SubClass sc_inst2[2]; function new (); sc_inst2[1] = new; endfunction endclass; class Deep; MyClass sc_inst1; function new (); sc_inst1 = new; endfunction endclass; class WeNeedToGoDeeper; Deep sc_inst; function new (); sc_inst = new; endfunction endclass; module t; initial begin WeNeedToGoDeeper cl_inst[100]; MyClass cl_inst2[2]; cl_inst[1] = new; cl_inst2[0] = new; repeat(10) begin if (cl_inst[1].sc_inst.sc_inst1.sc_inst2[1].randomize() with {field inside {1, 2, 3};} == 0) begin $stop; end if (cl_inst[1].sc_inst.sc_inst1.sc_inst2[1].field < 1 || cl_inst[1].sc_inst.sc_inst1.sc_inst2[1].field > 3) begin $stop; end if (cl_inst2[0].sc_inst2[1].randomize() with {field inside {1, 2, 3};} == 0) begin $stop; end if (cl_inst2[0].sc_inst2[1].field < 1 || cl_inst2[0].sc_inst2[1].field > 3) begin $stop; end end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_flag_decorations_bad.out0000644000542200017500000000033515101701376024254 0ustar mahmoudyfreeshell%Error: Unknown setting for --decorations: 'BAD' ... Suggest 'none', 'medium', or 'node' ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_fork_func2_bad.out0000644000542200017500000000050415101701376023005 0ustar mahmoudyfreeshell%Error: t/t_fork_func2_bad.v:10:5: Only fork .. join_none is legal in functions. (IEEE 1800-2023 13.4.4) : ... note: In instance 't' 10 | fork | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_preproc_inc_recurse_bad.v0000644000542200017500000000037515101701376024446 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `include "t_preproc_inc_recurse_bad.v" verilator-5.042/test_regress/t/t_flag_wfatal.out0000644000542200017500000000076315101701376022417 0ustar mahmoudyfreeshell%Warning-WIDTHTRUNC: t/t_flag_wfatal.v:10:19: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits. : ... note: In instance 't' 10 | wire [3:0] foo = 6'h2e; | ^ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. verilator-5.042/test_regress/t/t_let_arg_bad.out0000644000542200017500000000223215101701376022364 0ustar mahmoudyfreeshell%Error: t/t_let_arg_bad.v:13:18: Too many arguments in function call to LET 'NO_ARG' 13 | if (NO_ARG(10) != 10) $stop; | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_let_arg_bad.v:14:11: Missing argument on non-defaulted argument 'a' in function call to LET 'ONE_ARG' 14 | if (ONE_ARG != 10) $stop; | ^~~~~~~ %Error: t/t_let_arg_bad.v:15:11: Missing argument on non-defaulted argument 'a' in function call to LET 'ONE_ARG' 15 | if (ONE_ARG() != 10) $stop; | ^~~~~~~ %Error: t/t_let_arg_bad.v:16:23: Too many arguments in function call to LET 'ONE_ARG' 16 | if (ONE_ARG(10, 20) != 10) $stop; | ^~ %Error: t/t_let_arg_bad.v:17:20: No such argument 'b' in function call to LET 'ONE_ARG' 17 | if (ONE_ARG(.b(1)) != 10) $stop; | ^ %Error: t/t_let_arg_bad.v:17:11: Missing argument on non-defaulted argument 'a' in function call to LET 'ONE_ARG' 17 | if (ONE_ARG(.b(1)) != 10) $stop; | ^~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_fork_port.v0000644000542200017500000000063215101701376021606 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t; logic x; sub s(x); initial #1 x = 1; endmodule module sub(input x); initial fork begin @x; $write("*-* All Finished *-*\n"); $finish; end join_any endmodule verilator-5.042/test_regress/t/t_var_types.py0000755000542200017500000000113315101701376022000 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.verilated_randReset = 1 # allow checking if we initialize vars to zero only when needed test.compile(verilator_flags2=["--x-assign 1"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_lib_prot_inout_bad.py0000755000542200017500000000124215101701376023623 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["--protect-lib", "secret", "--protect-key", "secret-key"], verilator_make_gcc=False, make_main=False, fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dpi_arg_output_type__Dpi.out0000644000542200017500000001455115101701376025171 0ustar mahmoudyfreeshell// Verilated -*- C++ -*- // DESCRIPTION: Verilator output: Prototypes for DPI import and export functions. // // Verilator includes this file in all generated .cpp files that use DPI functions. // Manually include this file where DPI .c import functions are declared to ensure // the C functions match the expectations of the DPI imports. #ifndef VERILATED_VT_DPI_ARG_OUTPUT_TYPE__DPI_H_ #define VERILATED_VT_DPI_ARG_OUTPUT_TYPE__DPI_H_ // guard #include "svdpi.h" #ifdef __cplusplus extern "C" { #endif // DPI EXPORTS extern void e_array_2_state_1(svBitVecVal* o); extern void e_array_2_state_128(svBitVecVal* o); extern void e_array_2_state_32(svBitVecVal* o); extern void e_array_2_state_33(svBitVecVal* o); extern void e_array_2_state_64(svBitVecVal* o); extern void e_array_2_state_65(svBitVecVal* o); extern void e_array_4_state_1(svLogicVecVal* o); extern void e_array_4_state_128(svLogicVecVal* o); extern void e_array_4_state_32(svLogicVecVal* o); extern void e_array_4_state_33(svLogicVecVal* o); extern void e_array_4_state_64(svLogicVecVal* o); extern void e_array_4_state_65(svLogicVecVal* o); extern void e_bit(svBit* o); extern void e_bit_t(svBit* o); extern void e_byte(char* o); extern void e_byte_t(char* o); extern void e_byte_unsigned(unsigned char* o); extern void e_byte_unsigned_t(unsigned char* o); extern void e_chandle(void** o); extern void e_chandle_t(void** o); extern void e_int(int* o); extern void e_int_t(int* o); extern void e_int_unsigned(unsigned int* o); extern void e_int_unsigned_t(unsigned int* o); extern void e_integer(svLogicVecVal* o); extern void e_integer_t(svLogicVecVal* o); extern void e_logic(svLogic* o); extern void e_logic_t(svLogic* o); extern void e_longint(long long* o); extern void e_longint_t(long long* o); extern void e_longint_unsigned(unsigned long long* o); extern void e_longint_unsigned_t(unsigned long long* o); extern void e_real(double* o); extern void e_real_t(double* o); extern void e_shortint(short* o); extern void e_shortint_t(short* o); extern void e_shortint_unsigned(unsigned short* o); extern void e_shortint_unsigned_t(unsigned short* o); extern void e_string(const char** o); extern void e_string_t(const char** o); extern void e_struct_2_state_1(svBitVecVal* o); extern void e_struct_2_state_128(svBitVecVal* o); extern void e_struct_2_state_32(svBitVecVal* o); extern void e_struct_2_state_33(svBitVecVal* o); extern void e_struct_2_state_64(svBitVecVal* o); extern void e_struct_2_state_65(svBitVecVal* o); extern void e_struct_4_state_1(svLogicVecVal* o); extern void e_struct_4_state_128(svLogicVecVal* o); extern void e_struct_4_state_32(svLogicVecVal* o); extern void e_struct_4_state_33(svLogicVecVal* o); extern void e_struct_4_state_64(svLogicVecVal* o); extern void e_struct_4_state_65(svLogicVecVal* o); extern void e_time(svLogicVecVal* o); extern void e_time_t(svLogicVecVal* o); extern void e_union_2_state_1(svBitVecVal* o); extern void e_union_2_state_128(svBitVecVal* o); extern void e_union_2_state_32(svBitVecVal* o); extern void e_union_2_state_33(svBitVecVal* o); extern void e_union_2_state_64(svBitVecVal* o); extern void e_union_2_state_65(svBitVecVal* o); extern void e_union_4_state_1(svLogicVecVal* o); extern void e_union_4_state_128(svLogicVecVal* o); extern void e_union_4_state_32(svLogicVecVal* o); extern void e_union_4_state_33(svLogicVecVal* o); extern void e_union_4_state_64(svLogicVecVal* o); extern void e_union_4_state_65(svLogicVecVal* o); // DPI IMPORTS extern void check_exports(); extern void i_array_2_state_1(svBitVecVal* o); extern void i_array_2_state_128(svBitVecVal* o); extern void i_array_2_state_32(svBitVecVal* o); extern void i_array_2_state_33(svBitVecVal* o); extern void i_array_2_state_64(svBitVecVal* o); extern void i_array_2_state_65(svBitVecVal* o); extern void i_array_4_state_1(svLogicVecVal* o); extern void i_array_4_state_128(svLogicVecVal* o); extern void i_array_4_state_32(svLogicVecVal* o); extern void i_array_4_state_33(svLogicVecVal* o); extern void i_array_4_state_64(svLogicVecVal* o); extern void i_array_4_state_65(svLogicVecVal* o); extern void i_bit(svBit* o); extern void i_bit_t(svBit* o); extern void i_byte(char* o); extern void i_byte_t(char* o); extern void i_byte_unsigned(unsigned char* o); extern void i_byte_unsigned_t(unsigned char* o); extern void i_chandle(void** o); extern void i_chandle_t(void** o); extern void i_int(int* o); extern void i_int_t(int* o); extern void i_int_unsigned(unsigned int* o); extern void i_int_unsigned_t(unsigned int* o); extern void i_integer(svLogicVecVal* o); extern void i_integer_t(svLogicVecVal* o); extern void i_logic(svLogic* o); extern void i_logic_t(svLogic* o); extern void i_longint(long long* o); extern void i_longint_t(long long* o); extern void i_longint_unsigned(unsigned long long* o); extern void i_longint_unsigned_t(unsigned long long* o); extern void i_real(double* o); extern void i_real_t(double* o); extern void i_shortint(short* o); extern void i_shortint_t(short* o); extern void i_shortint_unsigned(unsigned short* o); extern void i_shortint_unsigned_t(unsigned short* o); extern void i_string(const char** o); extern void i_string_t(const char** o); extern void i_struct_2_state_1(svBitVecVal* o); extern void i_struct_2_state_128(svBitVecVal* o); extern void i_struct_2_state_32(svBitVecVal* o); extern void i_struct_2_state_33(svBitVecVal* o); extern void i_struct_2_state_64(svBitVecVal* o); extern void i_struct_2_state_65(svBitVecVal* o); extern void i_struct_4_state_1(svLogicVecVal* o); extern void i_struct_4_state_128(svLogicVecVal* o); extern void i_struct_4_state_32(svLogicVecVal* o); extern void i_struct_4_state_33(svLogicVecVal* o); extern void i_struct_4_state_64(svLogicVecVal* o); extern void i_struct_4_state_65(svLogicVecVal* o); extern void i_time(svLogicVecVal* o); extern void i_time_t(svLogicVecVal* o); extern void i_union_2_state_1(svBitVecVal* o); extern void i_union_2_state_128(svBitVecVal* o); extern void i_union_2_state_32(svBitVecVal* o); extern void i_union_2_state_33(svBitVecVal* o); extern void i_union_2_state_64(svBitVecVal* o); extern void i_union_2_state_65(svBitVecVal* o); extern void i_union_4_state_1(svLogicVecVal* o); extern void i_union_4_state_128(svLogicVecVal* o); extern void i_union_4_state_32(svLogicVecVal* o); extern void i_union_4_state_33(svLogicVecVal* o); extern void i_union_4_state_64(svLogicVecVal* o); extern void i_union_4_state_65(svLogicVecVal* o); #ifdef __cplusplus } #endif #endif // guard verilator-5.042/test_regress/t/t_const_slicesel.py0000755000542200017500000000070715101701376023003 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.042/test_regress/t/t_implements_collision_bad.v0000644000542200017500000000150015101701376024632 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface class Icls1; pure virtual function int icfboth; endclass interface class Icls2; pure virtual function int icfboth; endclass interface class IclsBoth extends Icls1, Icls2; // Bad collision on icfboth endclass class Cls implements IclsBoth; endclass // This is not a collision - diamond interface class Ibase; pure virtual function int fn(); endclass interface class Ic1 extends Ibase; pure virtual function int fn1(); endclass interface class Ic2 extends Ibase; pure virtual function int fn2(); endclass interface class Ic3 extends Ic1, Ic2; endclass module t; Cls c; endmodule verilator-5.042/test_regress/t/t_json_only_output.out0000644000542200017500000000446015101701376023600 0ustar mahmoudyfreeshell{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"UNLINKED", "modulesp": [ {"type":"MODULE","name":"m","addr":"(E)","loc":"d,7:8,7:9","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"m","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"clk","addr":"(F)","loc":"d,8:10,8:13","dtypep":"(G)","origName":"clk","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ]} ],"filesp": [], "miscsp": [ {"type":"TYPETABLE","name":"","addr":"(C)","loc":"a,0:0,0:0","constraintRefp":"UNLINKED","emptyQueuep":"UNLINKED","queueIndexp":"UNLINKED","streamp":"UNLINKED","voidp":"UNLINKED", "typesp": [ {"type":"BASICDTYPE","name":"logic","addr":"(G)","loc":"d,8:10,8:13","dtypep":"(G)","keyword":"logic","generic":true,"rangep": []} ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ {"type":"MODULE","name":"@CONST-POOL@","addr":"(H)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], "stmtsp": [ {"type":"SCOPE","name":"@CONST-POOL@","addr":"(I)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(H)","varsp": [],"blocksp": [],"inlinesp": []} ]} ]} ]} verilator-5.042/test_regress/t/t_var_notfound_bad.out0000644000542200017500000000247515101701376023464 0ustar mahmoudyfreeshell%Error: t/t_var_notfound_bad.v:18:7: Can't find definition of variable: 'nf' 18 | nf = 0; | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_var_notfound_bad.v:19:11: Can't find definition of 'subsubz' in dotted scope/variable: 'sub.subsubz' 19 | sub.subsubz.inss = 0; | ^~~~~~~ ... Known scopes under 'sub': subsub %Error: t/t_var_notfound_bad.v:20:11: Can't find definition of task/function: 'nofunc' : ... Suggested alternative: 'notfunc' 20 | i = nofunc(); | ^~~~~~ %Error: t/t_var_notfound_bad.v:21:15: Can't find definition of 'nofuncs' in dotted task/function: 'sub.nofuncs' : ... Suggested alternative: 'notfuncs' 21 | i = sub.nofuncs(); | ^~~~~~~ ... Known scopes under 'nofuncs': sub %Error: t/t_var_notfound_bad.v:22:7: Can't find definition of task/function: 'notask' : ... Suggested alternative: 'nottask' 22 | notask(); | ^~~~~~ %Error: t/t_var_notfound_bad.v:23:7: Found definition of 'a_var' as a VAR but expected a task/function 23 | a_var(); | ^~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_time_vpi_1ps1fs.py0000755000542200017500000000137115101701376023001 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.pli_filename = "t/t_time_vpi_c.cpp" test.top_filename = "t/t_time_vpi.v" test.main_time_multiplier = 1e-12 / 10e-15 test.compile( v_flags2=['+define+time_scale_units=1ps +define+time_scale_prec=1fs', test.pli_filename], verilator_flags2=['--vpi']) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_vpi_zero_time_cb.py0000755000542200017500000000143715101701376023312 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile( make_main=False, make_pli=True, sim_time=2100, iv_flags2=["-g2005-sv -D USE_VPI_NOT_DPI -DWAVES -DIVERILOG"], v_flags2=["+define+USE_VPI_NOT_DPI"], verilator_flags2=["--exe --vpi --no-l2name", test.pli_filename, "-LDFLAGS '-ldl -rdynamic'"]) test.execute(use_libvpi=True, all_run_flags=['+PLUS +INT=1234 +STRSTR']) test.passes() verilator-5.042/test_regress/t/t_tri_array_pull.v0000644000542200017500000000221115101701376022624 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2018 by Rod Steward. // SPDX-License-Identifier: CC0-1.0 module IOBUF ( input T, input I, output O, inout IO ); assign O = IO; assign IO = T ? 1'bz : I; endmodule module t ( input [7:0] inlines, output [7:0] outlines, inout [7:0] iolines, input inctrl ); generate for (genvar i = 4; i < 8; i = i+1) begin: Gen_D IOBUF d ( .T(inctrl), .I(inlines[i]), .O(outlines[i]), .IO(iolines[i]) ); pullup d_pup (iolines[i]); end endgenerate IOBUF d_0 ( .T(inctrl), .I(inlines[0]), .O(outlines[0]), .IO(iolines[0]) ); pullup d_0_pup (iolines[0]); IOBUF d_1 ( .T(inctrl), .I(inlines[1]), .O(outlines[1]), .IO(iolines[1]) ); pullup d_1_pup (iolines[1]); IOBUF d_2 ( .T(inctrl), .I(inlines[2]), .O(outlines[2]), .IO(iolines[2]) ); pullup d_2_pup (iolines[2]); IOBUF d_3 ( .T(inctrl), .I(inlines[3]), .O(outlines[3]), .IO(iolines[3]) ); pullup d_3_pup (iolines[3]); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_sys_fmonitor.v0000644000542200017500000000261615101701376022340 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" module t(/*AUTOARG*/ // Inputs clk ); input clk; int cyc = 0; int fd; // Test loop always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 5) begin fd = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/open.log"}, "w"); end else if (cyc == 10) begin $fmonitor(fd, "[%0t] cyc=%0d", $time, cyc); $fmonitor(fd, "[%0t] cyc=%0d also", $time, cyc); end else if (cyc == 17) begin $fmonitorb(fd, cyc, "b"); end else if (cyc == 18) begin $fmonitorh(fd, cyc, "h"); end else if (cyc == 19) begin $fmonitoro(fd, cyc, "o"); end else if (cyc == 22) begin $fmonitor(fd, "[%0t] cyc=%0d new-monitor", $time, cyc); end else if (cyc == 24) begin // IEEE suggests $monitoroff doesn't affect $fmonitor, but // other simulators believe it does $monitoroff; end else if (cyc == 26) begin $monitoron; end else if (cyc == 27) begin $fclose(fd); end else if (cyc == 30) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_mem_slice.py0000755000542200017500000000073415101701376021727 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_xml_begin_hier.out0000644000542200017500000001403015101701376023113 0ustar mahmoudyfreeshell verilator-5.042/test_regress/t/t_struct_negate.py0000755000542200017500000000073415101701376022641 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_assign_automatic_bad.v0000644000542200017500000000446015101701376023744 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // 6.21 Scope and lifetime // Automatic variables and elements of dynamically sized array variables shall // not be written with nonblocking, continuous, or procedural continuous // assignments. Non-static class properties shall not be written with continuous // or procedural continuous assignments. class Cls; static int s_ok1; static int s_ok2; static int s_dyn[]; int m_bad1; int m_bad2; endclass module t(clk); input clk; Cls c; int bad_dyn5[]; int bad_dyn6[]; int empty_dyn[]; int empty_queue[$]; int empty_assoc[int]; int bad_queue[$]; int bad_assoc[int]; Cls clist[1]; assign bad_dyn5[0] = empty_dyn; // <--- Error: continuous dynarray element assign bad_dyn5 = empty_dyn; // <--- OK: continuous dynarray assignment, not to its element assign c.m_bad1 = 2; // <--- Error: continuous class non-static // Only one simulator fails on this, probably not legal // assign Cls::s_ok1 = 2; // OK: continuous class static logic ok_7; task mt(output o); // OK: function output o <= 1; endtask always @(posedge clk) begin bad_dyn6[0] <= 2; // <--- Error: nonblocking dynarray element bad_dyn6 <= empty_dyn; // <--- OK: nonblocking dynarray assignment, not to its element bad_queue[0] <= 2; // Error: nonblocking queue element assignment bad_queue <= empty_queue; // OK: nonblocking assignment to queue itself, not to its element bad_assoc[0] <= 2; // Error: nonblocking associative array element assignment bad_assoc <= empty_assoc; // OK: nonblocking assignment to associative array itself, not to its element Cls::s_ok2 <= 2; // OK: nonblocking class static c.m_bad2 <= 2; // <--- Error: nonblocking class automatic Cls::s_dyn <= 2; // OK: nonblocking class static dynarray assignment, not to its element Cls::s_dyn[0] <= 2; // Error: nonblocking class static dynarray element clist[bad_dyn6[0]++].s_dyn <= '1; // OK: direct nonblocking assignment to dynamically-sized array clist[bad_dyn6[0]++].s_dyn[0] <= '1; // Error: nonblocking assigment to dynamically-sized array element mt(ok_7); $stop; end endmodule verilator-5.042/test_regress/t/t_math_signed2.v0000644000542200017500000000314215101701376022144 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2007 by Peter Debacker. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [10:0] in; reg signed[7:0] min; reg signed[7:0] max; wire signed[7:0] filtered_data; reg signed[7:0] delay_minmax[31:0]; integer k; initial begin in = 11'b10000001000; for(k=0;k<32;k=k+1) delay_minmax[k] = 0; end assign filtered_data = $signed(in[10:3]); always @(posedge clk) begin in = in + 8; `ifdef TEST_VERBOSE $write("filtered_data: %d\n", filtered_data); `endif // delay line shift for (k=31;k>0;k=k-1) begin delay_minmax[k] = delay_minmax[k-1]; end delay_minmax[0] = filtered_data; `ifdef TEST_VERBOSE $write("delay_minmax[0] = %d\n", delay_minmax[0]); $write("delay_minmax[31] = %d\n", delay_minmax[31]); `endif // find min and max min = 127; max = -128; `ifdef TEST_VERBOSE $write("max init: %d\n", max); $write("min init: %d\n", min); `endif for(k=0;k<32;k=k+1) begin if ((delay_minmax[k]) > $signed(max)) max = delay_minmax[k]; if ((delay_minmax[k]) < $signed(min)) min = delay_minmax[k]; end `ifdef TEST_VERBOSE $write("max: %d\n", max); $write("min: %d\n", min); `endif if (min == 127) begin $stop; end else if (filtered_data >= -61) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_trace_abort.v0000644000542200017500000000067715101701376022077 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [2:0] cyc = 0; always @(posedge clk) begin cyc <= cyc + 3'd1; // Exit via abort to make sure trace is flushed if (&cyc) $stop; end endmodule verilator-5.042/test_regress/t/t_class_local_bad.v0000644000542200017500000000413615101701376022671 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Let context messages easily know if given line is expected ok or bad task ok; endtask task bad; endtask class Cls; int m_pub = 1; local int m_loc = 2; protected int m_prot = 3; task f_pub; endtask local task f_loc; endtask protected task f_prot; endtask static task s_pub; endtask static local task s_loc; endtask static protected task s_prot; endtask task check; Cls o; ok(); if (m_pub != 1) $stop; ok(); if (m_loc != 10) $stop; ok(); if (m_prot != 20) $stop; ok(); f_pub(); ok(); f_loc(); ok(); f_prot(); ok(); o.f_pub(); ok(); o.f_loc(); ok(); o.f_prot(); ok(); s_pub(); ok(); s_loc(); ok(); s_prot(); ok(); Cls::s_pub(); ok(); Cls::s_loc(); ok(); Cls::s_prot(); endtask endclass class Ext extends Cls; task check; Ext o; ok(); if (m_pub != 1) $stop; bad(); if (m_loc != 10) $stop; ok(); if (m_prot != 20) $stop; ok(); f_pub(); bad(); f_loc(); ok(); f_prot(); ok(); o.f_pub(); bad(); o.f_loc(); ok(); o.f_prot(); ok(); s_pub(); bad(); s_loc(); ok(); s_prot(); ok(); Cls::s_pub(); bad(); Cls::s_loc(); ok(); Cls::s_prot(); endtask endclass module t; initial begin Cls c; Ext e; c = new; e = new; ok(); if (c.m_pub != 1) $stop; bad(); if (c.m_loc != 2) $stop; bad(); if (c.m_prot != 20) $stop; ok(); if (e.m_pub != 1) $stop; bad(); if (e.m_loc != 2) $stop; bad(); if (e.m_prot != 20) $stop; ok(); c.f_pub(); bad(); c.f_loc(); bad(); c.f_prot(); ok(); c.s_pub(); bad(); c.s_loc(); bad(); c.s_prot(); ok(); Cls::s_pub(); bad(); Cls::s_loc(); bad(); Cls::s_prot(); // $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_mod_recurse1.py0000755000542200017500000000073415101701376022362 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_complex.v0000644000542200017500000000651215101701376022431 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 bit global_bit; module t (clk); input clk; integer cyc = 0; typedef struct packed { bit b1; bit b0; } strp_t; typedef struct packed { strp_t x1; strp_t x0; } strp_strp_t; typedef union packed { strp_t x1; strp_t x0; } unip_strp_t; typedef bit [2:1] arrp_t; typedef arrp_t [4:3] arrp_arrp_t; typedef strp_t [4:3] arrp_strp_t; typedef bit arru_t [2:1]; typedef arru_t arru_arru_t [4:3]; typedef arrp_t arru_arrp_t [4:3]; typedef strp_t arru_strp_t [4:3]; strp_t v_strp; strp_strp_t v_strp_strp; unip_strp_t v_unip_strp; arrp_t v_arrp; arrp_arrp_t v_arrp_arrp; arrp_strp_t v_arrp_strp; arru_t v_arru; arru_arru_t v_arru_arru; arru_arrp_t v_arru_arrp; arru_strp_t v_arru_strp; real v_real; real v_arr_real [2]; string v_string; chandle v_chandle; string v_assoc[string]; initial v_assoc["key"] = "value"; typedef struct packed { logic [31:0] data; } str32_t; str32_t [1:0] v_str32x2; // If no --trace-struct, this packed array is traced as 63:0 initial v_str32x2[0] = 32'hff; initial v_str32x2[1] = 0; typedef enum int { ZERO=0, ONE, TWO, THREE } enumed_t; enumed_t v_enumed; enumed_t v_enumed2; typedef enum logic [2:0] { BZERO=0, BONE, BTWO, BTHREE } enumb_t; enumb_t v_enumb; typedef struct packed { enumb_t a; enumb_t b; } enumb2_str_t; enumb2_str_t v_enumb2_str; logic [7:0] unpacked_array[-2:0]; bit LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND; p #(.PARAM(2)) p2 (); p #(.PARAM(3)) p3 (); p #(.PARAM(4)) a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed (); always @ (posedge clk) begin cyc <= cyc + 1; v_strp <= ~v_strp; v_strp_strp <= ~v_strp_strp; v_unip_strp <= ~v_unip_strp; v_arrp_strp <= ~v_arrp_strp; v_arrp <= ~v_arrp; v_arrp_arrp <= ~v_arrp_arrp; v_real <= v_real + 0.1; v_string <= cyc[0] ? "foo" : "bar"; v_arr_real[0] <= v_arr_real[0] + 0.2; v_arr_real[1] <= v_arr_real[1] + 0.3; v_enumed <= enumed_t'(v_enumed + 1); v_enumed2 <= enumed_t'(v_enumed2 + 2); v_enumb <= enumb_t'(v_enumb - 3'd1); v_enumb2_str <= {v_enumb, v_enumb}; for (integer b=3; b<=4; b++) begin v_arru[b] <= ~v_arru[b]; v_arru_strp[b] <= ~v_arru_strp[b]; v_arru_arrp[b] <= ~v_arru_arrp[b]; for (integer a=3; a<=4; a++) begin v_arru_arru[a][b] = ~v_arru_arru[a][b]; end end v_str32x2[0] <= v_str32x2[0] - 1; v_str32x2[1] <= v_str32x2[1] + 1; if (cyc == 5) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module p; parameter PARAM = 1; initial global_bit = 1; endmodule verilator-5.042/test_regress/t/t_vpi_get_value_array.py0000755000542200017500000000141615101701376024017 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(make_top_shell=False, make_main=False, make_pli=True, verilator_flags2=["--exe --vpi --no-l2name", test.pli_filename], iv_flags2=["-g2005-sv -D USE_VPI_NOT_DPI"], v_flags2=["+define+USE_VPI_NOT_DPI +define+VERILATOR_COMMENTS"]) test.execute(use_libvpi=True) test.passes() verilator-5.042/test_regress/t/t_cast_types.py0000755000542200017500000000073415101701376022150 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_clk_dsp.v0000644000542200017500000001104315101701376021216 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [7:0] cyc; initial cyc = 0; reg [7:0] padd; reg dsp_ph1, dsp_ph2, dsp_reset; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [7:0] out; // From dspchip of t_dspchip.v // End of automatics t_dspchip dspchip (/*AUTOINST*/ // Outputs .out (out[7:0]), // Inputs .dsp_ph1 (dsp_ph1), .dsp_ph2 (dsp_ph2), .dsp_reset (dsp_reset), .padd (padd[7:0])); always @ (posedge clk) begin $write("cyc %d\n",cyc); if (cyc == 8'd0) begin cyc <= 8'd1; dsp_reset <= 0; // Need a posedge padd <= 0; end else if (cyc == 8'd20) begin $write("*-* All Finished *-*\n"); $finish; end else begin cyc <= cyc + 8'd1; dsp_ph1 <= ((cyc&8'd3) == 8'd0); dsp_ph2 <= ((cyc&8'd3) == 8'd2); dsp_reset <= (cyc == 8'd1); padd <= cyc; //$write("[%0t] cyc %d %x->%x\n", $time, cyc, padd, out); case (cyc) default: $stop; 8'd01: ; 8'd02: ; 8'd03: ; 8'd04: ; 8'd05: ; 8'd06: ; 8'd07: ; 8'd08: ; 8'd09: if (out!==8'h04) $stop; 8'd10: if (out!==8'h04) $stop; 8'd11: if (out!==8'h08) $stop; 8'd12: if (out!==8'h08) $stop; 8'd13: if (out!==8'h00) $stop; 8'd14: if (out!==8'h00) $stop; 8'd15: if (out!==8'h00) $stop; 8'd16: if (out!==8'h00) $stop; 8'd17: if (out!==8'h0c) $stop; 8'd18: if (out!==8'h0c) $stop; 8'd19: if (out!==8'h10) $stop; endcase end end endmodule module t_dspchip (/*AUTOARG*/ // Outputs out, // Inputs dsp_ph1, dsp_ph2, dsp_reset, padd ); input dsp_ph1, dsp_ph2, dsp_reset; input [7:0] padd; output [7:0] out; wire dsp_ph1, dsp_ph2; wire [7:0] out; wire pla_ph1, pla_ph2; wire out1_r; wire [7:0] out2_r, padd; wire clk_en; t_dspcore t_dspcore (/*AUTOINST*/ // Outputs .out1_r (out1_r), .pla_ph1 (pla_ph1), .pla_ph2 (pla_ph2), // Inputs .dsp_ph1 (dsp_ph1), .dsp_ph2 (dsp_ph2), .dsp_reset (dsp_reset), .clk_en (clk_en)); t_dsppla t_dsppla (/*AUTOINST*/ // Outputs .out2_r (out2_r[7:0]), // Inputs .pla_ph1 (pla_ph1), .pla_ph2 (pla_ph2), .dsp_reset (dsp_reset), .padd (padd[7:0])); assign out = out1_r ? 8'h00 : out2_r; assign clk_en = 1'b1; endmodule module t_dspcore (/*AUTOARG*/ // Outputs out1_r, pla_ph1, pla_ph2, // Inputs dsp_ph1, dsp_ph2, dsp_reset, clk_en ); input dsp_ph1, dsp_ph2, dsp_reset; input clk_en; output out1_r, pla_ph1, pla_ph2; wire dsp_ph1, dsp_ph2, dsp_reset; wire pla_ph1, pla_ph2; reg out1_r; always @(posedge dsp_ph1 or posedge dsp_reset) begin if (dsp_reset) out1_r <= 1'h0; else out1_r <= ~out1_r; end assign pla_ph1 = dsp_ph1; assign pla_ph2 = dsp_ph2 & clk_en; endmodule module t_dsppla (/*AUTOARG*/ // Outputs out2_r, // Inputs pla_ph1, pla_ph2, dsp_reset, padd ); input pla_ph1, pla_ph2, dsp_reset; input [7:0] padd; output [7:0] out2_r; wire pla_ph1, pla_ph2, dsp_reset; wire [7:0] padd; reg [7:0] out2_r; reg [7:0] latched_r; always @(posedge pla_ph1 or posedge dsp_reset) begin if (dsp_reset) latched_r <= 8'h00; else latched_r <= padd; end always @(posedge pla_ph2 or posedge dsp_reset) begin if (dsp_reset) out2_r <= 8'h00; else out2_r <= latched_r; end endmodule verilator-5.042/test_regress/t/t_lint_implicit_def_bad.py0000755000542200017500000000110115101701376024243 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_var_port2_bad.out0000644000542200017500000000066615101701376022676 0ustar mahmoudyfreeshell%Error: t/t_var_port2_bad.v:7:11: Input/output/inout declaration not found for port: 'portwithoin' 7 | module t (portwithoin); | ^~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_var_port2_bad.v:8:10: Input/output/inout does not appear in port list: 'portwithin' 8 | input portwithin; | ^~~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_lint_repeat_bad.v0000644000542200017500000000063415101701376022717 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Test of select from constant // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (); sub #(.Z(0)) sub1 (); sub #(.Z(1)) sub2 (); sub #(.Z(2)) sub3 (); endmodule module sub; parameter Z = 0; wire [1:0] a = 2'b11; wire [0:0] b = a; endmodule verilator-5.042/test_regress/t/t_pipe_filter.py0000755000542200017500000000145315101701376022273 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') stdout_filename = os.path.join(test.obj_dir, test.name + "__test.vpp") test.compile(verilator_flags2=['-E --pipe-filter \'python3 t/t_pipe_filter_pf.pf\' '], verilator_make_gmake=False, make_top_shell=False, make_main=False, stdout_filename=stdout_filename) test.files_identical(stdout_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_time_sc_us.out0000644000542200017500000000022615101701376022274 0ustar mahmoudyfreeshell Warning: (W516) default time unit changed to time resolution Time scale of t is 1us / 1us [20] In top.t: Hi - expect this is 20 *-* All Finished *-* verilator-5.042/test_regress/t/t_interface_array_modport.py0000755000542200017500000000073415101701376024674 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_define_override_empty.out0000644000542200017500000000001515101701376024505 0ustar mahmoudyfreeshellTEST_MACRO verilator-5.042/test_regress/t/t_mem_shift.v0000644000542200017500000000260315101701376021554 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc = 0; reg [63:0] crc; integer i; reg [63:0] mem [7:0]; always @ (posedge clk) begin if (cyc==1) begin for (i=0; i<8; i=i+1) begin mem[i] <= 64'h0; end end else begin mem[0] <= crc; for (i=1; i<8; i=i+1) begin mem[i] <= mem[i-1]; end end end wire [63:0] outData = mem[7]; always @ (posedge clk) begin //$write("[%0t] cyc==%0d crc=%b q=%x\n", $time, cyc, crc, outData); cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc==90) begin if (outData != 64'h1265e3bddcd9bc27) $stop; end else if (cyc==91) begin if (outData != 64'h24cbc77bb9b3784e) $stop; end else if (cyc==92) begin end else if (cyc==93) begin end else if (cyc==94) begin end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_fork_dynscope.py0000755000542200017500000000077115101701376022640 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_constraint_inheritance.v0000644000542200017500000000264615101701376024345 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 `define check_rand(cl, field, cond) \ begin \ longint prev_result; \ int ok = 0; \ if (!bit'(cl.randomize())) $stop; \ prev_result = longint'(field); \ if (!(cond)) $stop; \ repeat(9) begin \ longint result; \ if (!bit'(cl.randomize())) $stop; \ result = longint'(field); \ if (!(cond)) $stop; \ if (result != prev_result) ok = 1; \ prev_result = result; \ end \ if (ok != 1) $stop; \ end typedef class C; class D extends C; constraint x_lt_y { x < y; } endclass class A; endclass class B extends A; rand int x; constraint x_gt_0 { x > 0; } endclass class C extends B; rand int y; endclass class E extends C; constraint x_lt_20 { x < 20; } constraint x_gt_y { x > y; } endclass module t; initial begin B b = new; C c = new; D d = new; E e = new; A a = b; `check_rand(a, b.x, b.x > 0); `check_rand(c, c.x, c.x > 0); `check_rand(c, c.y, c.x > 0); `check_rand(d, d.x, d.x > 0 && d.x < d.y); `check_rand(d, d.y, d.x > 0 && d.x < d.y); `check_rand(e, e.x, e.x > 0 && e.x < 20 && e.x > e.y); `check_rand(e, e.y, e.x > 0 && e.x < 20 && e.x > e.y); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_lint_functimectl_bad.v0000644000542200017500000000133115101701376023747 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; event e; logic s; function void calls_timing_ctl; @e; // <--- Bad IEEE 1800-2023 13.4 time-controlling fork // <--- Bad IEEE 1800-2023 13.4 time-controlling join fork // <--- Bad IEEE 1800-2023 13.4 time-controlling join_any wait (s); // <--- Bad IEEE 1800-2023 13.4 time-controlling // TODO wait_order (e); // TODO ## // TODO expect endfunction // No warning here wire [31:0] #5 __test_wire = 32'd0; function void f; int x; endfunction endmodule verilator-5.042/test_regress/t/t_math_signed6.py0000755000542200017500000000073415101701376022342 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_generic_task_bad.v0000644000542200017500000000106315101701376025064 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 interface inf; int v; endinterface interface inf2; int k; endinterface module GenericModule (interface a); initial begin a.setup(); end endmodule module t; inf inf_inst(); GenericModule genericModule (inf_inst); initial begin #1; if (inf_inst.v != 3) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_lint_declfilename.py0000755000542200017500000000070315101701376023424 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint() test.passes() verilator-5.042/test_regress/t/t_cast_param_type.py0000755000542200017500000000073415101701376023145 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_preproc_noline.v0000644000542200017500000000056715101701376022626 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define CHECK text \ multiline Hello in t_preproc_psl.v `ifdef NEVER not `else yes `endif Multi `CHECK line // Did we end up right? Line: `__LINE__ verilator-5.042/test_regress/t/t_delay_var.v0000644000542200017500000000122615101701376021547 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; parameter PDLY = 1.2; real rdly = 1.3; integer idly = 1; reg in = 1'b0; wire #1.1 d_const = in; wire #idly d_int = in; wire #rdly d_real = in; wire #PDLY d_param = in; initial begin #2 in = 1'b1; #100; if (d_const != 1) $stop; if (d_int != 1) $stop; if (d_real != 1) $stop; if (d_param != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_reloop_cam_off.py0000755000542200017500000000131115101701376022734 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.top_filename = "t/t_reloop_cam.v" test.compile(verilator_flags2=["--stats", "-fno-reloop"]) if test.vlt_all: test.file_grep_not(test.stats, r'Optimizations, Reloop iterations\s+(\d+)') test.file_grep_not(test.stats, r'Optimizations, Reloops\s+(\d+)') test.passes() verilator-5.042/test_regress/t/t_interface_down.v0000644000542200017500000000307515101701376022574 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface ifc; integer value; endinterface module t (/*AUTOARG*/ // Inputs clk ); `ifdef INLINE_A //verilator inline_module `else //verilator no_inline_module `endif input clk; integer cyc=1; ifc itop1a(); ifc itop1b(); ifc itop2a(); ifc itop2b(); wrapper c1 (.isuba(itop1a), .isubb(itop1b), .i_valuea(14), .i_valueb(15)); wrapper c2 (.isuba(itop2a), .isubb(itop2b), .i_valuea(24), .i_valueb(25)); always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==20) begin if (itop1a.value != 14) $stop; if (itop1b.value != 15) $stop; if (itop2a.value != 24) $stop; if (itop2b.value != 25) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module wrapper ( ifc isuba, ifc isubb, input integer i_valuea, input integer i_valueb ); `ifdef INLINE_B //verilator inline_module `else //verilator no_inline_module `endif lower subsuba (.isub(isuba), .i_value(i_valuea)); lower subsubb (.isub(isubb), .i_value(i_valueb)); endmodule module lower ( ifc isub, input integer i_value ); `ifdef INLINE_C //verilator inline_module `else //verilator no_inline_module `endif always @* begin isub.value = i_value; end endmodule verilator-5.042/test_regress/t/t_past.py0000755000542200017500000000115415101701376020736 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--stats']) test.execute() # Check that $past shared common variables test.file_grep(test.stats, r'Assertions, \$past variables\s+(\d+)', 11) test.passes() verilator-5.042/test_regress/t/t_covergroup_in_class_with_sample.py0000755000542200017500000000070615101701376026433 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.passes() verilator-5.042/test_regress/t/t_func_numones.py0000755000542200017500000000073415101701376022471 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_pinnotfound_bad.out0000644000542200017500000000057415101701376024347 0ustar mahmoudyfreeshell%Error-PINNOTFOUND: t/t_lint_pinnotfound_bad.v:12:13: Pin not found: 'x' 12 | b b_inst1 (.x(1'b0)); | ^ ... For error description see https://verilator.org/warn/PINNOTFOUND?v=latest %Error-PINNOTFOUND: t/t_lint_pinnotfound_bad.v:13:6: Parameter not found: 'PX' 13 | b #(.PX(1'b0)) b_inst2 (); | ^~ %Error: Exiting due to verilator-5.042/test_regress/t/t_foreach_bad.v0000644000542200017500000000075015101701376022017 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; integer a, b; reg [2:0][2:0] array; initial begin foreach (array); // no index foreach (array.array[a]); // not supported foreach (array[a.b]); // no index $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_interface_modport_import_export_list.v0000644000542200017500000000167015101701376027336 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Modport import export list test // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Goekce Aydos. // SPDX-License-Identifier: CC0-1.0 interface intf; logic l; function void f1(); endfunction function void f2(); endfunction function void f3(); endfunction function void f4(); endfunction modport mpi ( import f1, f2, input l, import f3, f4 ); modport mpo ( output l, import f1, f2, f3, f4 ); endinterface module mo (intf.mpo intf0); function void ef1(); intf0.f1(); intf0.f2(); endfunction function void ef2(); intf0.f3(); intf0.f4(); endfunction initial begin ef1(); ef2(); end endmodule module mi (intf.mpi intf0); endmodule module t; intf intf0(); mi mi(.*); mo mo(.*); endmodule verilator-5.042/test_regress/t/t_c_this.v0000644000542200017500000000067615101701376021062 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; always @(posedge clk) begin $c("const CData xthis = this->clk;"); $c("const CData thisx = xthis;"); $c("const CData xthisx = thisx;"); $c("this->clk = xthisx;"); end endmodule verilator-5.042/test_regress/t/t_interface_ref_trace_fst.py0000755000542200017500000000117315101701376024616 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_ref_trace.v" test.compile(verilator_flags2=['--trace-structs --trace-fst']) test.execute() test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_randomize_rand_mode.v0000644000542200017500000000577515101701376023616 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); class Base; rand int m_one; task test1; m_one.rand_mode(0); `checkh(m_one.rand_mode(), 0); verify(0); m_one.rand_mode(1); `checkh(m_one.rand_mode(), 1); verify(1); endtask task verify(int mode_one); bit one_ne10 = '0; int v; if (m_one.rand_mode() != mode_one) $stop; for (int i = 0; i < 20; ++i) begin m_one = 10; v = randomize(); if (m_one != 10) one_ne10 = 1'b1; `ifdef TEST_VERBOSE $display("one=%0d(rand_mode=%0d)", m_one, mode_one); `endif end if (mode_one != 0 && !one_ne10) $stop; if (mode_one == 0 && one_ne10) $stop; endtask endclass class Packet extends Base; rand int m_two; task test2; rand_mode(0); `checkh(m_one.rand_mode(), 0); `checkh(m_two.rand_mode(), 0); verify(0, 0); m_one.rand_mode(0); `checkh(m_one.rand_mode(), 0); m_two.rand_mode(1); `checkh(m_two.rand_mode(), 1); verify(0, 1); endtask task verify(int mode_one, int mode_two); bit one_ne10 = '0; bit two_ne10 = '0; int v; if (m_one.rand_mode() != mode_one) $stop; if (m_two.rand_mode() != mode_two) $stop; for (int i = 0; i < 20; ++i) begin m_one = 10; m_two = 10; v = randomize(); if (m_one != 10) one_ne10 = 1'b1; if (m_two != 10) two_ne10 = 1'b1; `ifdef TEST_VERBOSE $display("one=%0d(rand_mode=%0d) two=%0d(rand_mode=%0d)", m_one, mode_one, m_two, mode_two); `endif end if (mode_one != 0 && !one_ne10) $stop; if (mode_two != 0 && !two_ne10) $stop; if (mode_one == 0 && one_ne10) $stop; if (mode_two == 0 && two_ne10) $stop; endtask endclass module t; Packet p; int v; initial begin p = new; p.test1(); p.test2(); // IEEE: function void object[.random_variable].rand_mode(bit on_off); // IEEE: function int object.random_variable.rand_mode(); // Not legal to get current rand() value on a class-only call // We call rand_mode here too becuase the parsing is different from that // called from the class itself p.m_one.rand_mode(0); `checkh(p.m_one.rand_mode(), 0); p.m_two.rand_mode(0); `checkh(p.m_two.rand_mode(), 0); p.verify(0, 0); p.m_one.rand_mode(0); `checkh(p.m_one.rand_mode(), 0); p.m_two.rand_mode(1); `checkh(p.m_two.rand_mode(), 1); p.verify(0, 1); p.rand_mode(1); p.verify(1, 1); p.rand_mode(0); p.verify(0, 0); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_var_sc_double.cpp0000644000542200017500000000314615101701376022730 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2025 by George Polack. // SPDX-License-Identifier: CC0-1.0 #include VM_PREFIX_INCLUDE #include #include using namespace sc_core; using namespace sc_dt; VM_PREFIX* tb = nullptr; bool pass = true; double sc_time_stamp() { return 0; } void compareDoubles(double const lwp, double const rwp, double epsilon = std::numeric_limits::epsilon()) { auto diff = std::fabs(lwp - rwp); if (diff >= epsilon) { pass &= false; VL_PRINTF("%%Error: There is a difference of %f, in double variables\n", diff); } } #ifdef SYSTEMC_VERSION int sc_main(int, char**) #else int main() #endif { Verilated::debug(0); tb = new VM_PREFIX{"tb"}; double input_var = 1.5; double out_var; #ifdef SYSTEMC_VERSION // clang-format off sc_signal SC_NAMED(i_a), SC_NAMED(o_z); tb->i_a(i_a); tb->o_z(o_z); // clang-format on #endif #ifdef SYSTEMC_VERSION sc_start(1, SC_NS); #else tb->eval(); #endif // This testcase is testing conversion to/from Verilog real to/from SystemC double. VL_ASSIGN_SDD(0, i_a, input_var); #ifdef SYSTEMC_VERSION sc_start(1, SC_NS); #else tb->eval(); #endif VL_ASSIGN_DSD(0, out_var, o_z); compareDoubles(input_var, out_var); tb->final(); VL_DO_DANGLING(delete tb, tb); if (pass) { VL_PRINTF("*-* All Finished *-*\n"); } else { vl_fatal(__FILE__, __LINE__, "top", "Unexpected results from test\n"); } return 0; } verilator-5.042/test_regress/t/t_time.py0000755000542200017500000000076615101701376020735 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_cover_lib__3.out0000644000542200017500000000032015101701376022462 0ustar mahmoudyfreeshell# SystemC::Coverage-3 C 'f../../t/t_cover_lib_c.cppl48t_userpagesp_user/t_cover_lib_cokept_onehmain' 0 C 'f../../t/t_cover_lib_c.cppl49t_userpagesp_user/t_cover_lib_cokept_twohmain' 0 verilator-5.042/test_regress/t/t_process.v0000644000542200017500000000304615101701376021261 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Methods defined by IEEE: // class process; // enum state { FINISHED, RUNNING, WAITING, SUSPENDED, KILLED }; // UVM uses KILLED, FINISHED // static function process self(); // function state status(); // function void kill(); // task await(); // Warn as unsupported (no UVM library use) // function void suspend(); // Warn as unsupported (no UVM library use) // function void resume(); // Warn as unsupported (no UVM library use) // function void srandom( int seed ); // Operate on all proceses for now? // function string get_randstate(); // Operate on all proceses for now? // function void set_randstate( string state ); // Operate on all proceses for now? // endclass module t; process p; initial begin if (p != null) $stop; p = process::self(); if (p.status() != process::RUNNING) $stop; if (p.status() == process::WAITING) $stop; if (p.status() == process::SUSPENDED) $stop; if (p.status() == process::KILLED) $stop; if (p.status() == process::FINISHED) $stop; if (0) p.kill(); if (0) p.await(); if (0) p.suspend(); if (0) p.resume(); // See also t_urandom.py p.srandom(0); p.set_randstate(p.get_randstate()); $display("%p", p); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_var_assign_landr.py0000755000542200017500000000073415101701376023306 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_mod_interface_array3.out0000644000542200017500000000072415101701376024225 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_mod_interface_array3.v:22:20: Unsupported: Multidimensional instances/interfaces. 22 | a_if iface [2:0][1:0] (); | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_mod_interface_array3.v:24:18: Unsupported: Multidimensional instances/interfaces. 24 | sub i_sub[2:0][1:0] (.s(str)); | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_uvm_dpi.py0000755000542200017500000000136015101701376021431 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.pli_filename = "t/uvm/dpi/uvm_dpi.cc" if re.search(r'clang', test.cxx_version): test.skip("uvm_regex.cc from upstream has clang warnings") test.compile( verilator_flags2=["--binary", "--build-jobs 4", "--vpi", "+incdir+t/uvm", test.pli_filename]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_dyn_cast_empty_if.v0000644000542200017500000000126515101701376024471 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 typedef class Derived; class Base; function Derived cast(); if (!$cast(cast, this)) begin end endfunction endclass class Derived extends Base; string x; function new(string xval); x = xval; endfunction function string get(); return x; endfunction endclass module t; initial begin Derived d = new("Hello"); Base b = d; Derived c = b.cast(); if (d.get() != c.get()) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_opt_const_no_opt.py0000755000542200017500000000141715101701376023357 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_opt_const.v" # Run the same design as t_opt_const.py without bitopt tree optimization to make sure that the result is same. test.compile(verilator_flags2=[ "-Wno-UNOPTTHREADS", "--stats", "-fno-const-bit-op-tree", test.t_dir + "/t_opt_const.cpp", "-CFLAGS", "-Wno-tautological-compare" ]) test.execute() test.passes() verilator-5.042/test_regress/t/t_package_alone_bad.out0000644000542200017500000000037715101701376023530 0ustar mahmoudyfreeshell%Error: t/t_package_alone_bad.v:7:13: Export package not found: 'pkg' 7 | export pkg::something; | ^~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_dpi_var.py0000755000542200017500000000360115101701376021412 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') out_filename = test.obj_dir + "/V" + test.name + ".tree.json" test.compile( make_top_shell=False, make_main=False, verilator_flags2=["--no-json-edit-nums", "-DATTRIBUTES --exe --no-l2name", test.pli_filename]) if test.vlt_all: test.file_grep( out_filename, r'{"type":"VAR","name":"formatted",.*"loc":"\w,69:[^"]*",.*"origName":"formatted",.*"direction":"INPUT",.*"dtypeName":"string",.*"attrSFormat":true' ) test.file_grep( out_filename, r'{"type":"VAR","name":"t.sub.in",.*"loc":"\w,91:[^"]*",.*"origName":"in",.*"dtypeName":"int",.*"isSigUserRdPublic":true' ) test.file_grep( out_filename, r'{"type":"VAR","name":"t.sub.in_a",.*"loc":"\w,92:[^"]*",.*"origName":"in_a",.*"dtypeName":"int",.*"isSigUserRdPublic":true,.*"isSigUserRWPublic":true' ) test.file_grep( out_filename, r'{"type":"VAR","name":"t.sub.in_b",.*"loc":"\w,93:[^"]*",.*"origName":"in_b",.*"dtypeName":"int",.*"isSigUserRdPublic":true,.*"isSigUserRWPublic":true' ) test.file_grep( out_filename, r'{"type":"VAR","name":"t.sub.fr_a",.*"loc":"\w,94:[^"]*",.*"origName":"fr_a",.*"dtypeName":"int",.*"isSigUserRdPublic":true,.*"isSigUserRWPublic":true' ) test.file_grep( out_filename, r'{"type":"VAR","name":"t.sub.fr_b",.*"loc":"\w,95:[^"]*",.*"origName":"fr_b",.*"dtypeName":"int",.*"isSigUserRdPublic":true,.*"isSigUserRWPublic":true' ) test.execute() test.passes() verilator-5.042/test_regress/t/t_case_huge_noopt.py0000755000542200017500000000117115101701376023130 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.top_filename = 't/t_case_huge.v' test.compile(verilator_flags2=["--stats -fno-combine"]) test.file_grep_not(test.stats, r'Optimizations, Combined CFuncs\s+(\d+)') test.execute() test.passes() verilator-5.042/test_regress/t/t_gen_if.py0000755000542200017500000000071215101701376021215 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile() test.passes() verilator-5.042/test_regress/t/t_covergroup_new_override_bad.out0000644000542200017500000000037715101701376025722 0ustar mahmoudyfreeshell%Error: t/t_covergroup_new_override_bad.v:10:5: syntax error, unexpected function 10 | function new(); | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_lint_didnotconverge_bad.v0000644000542200017500000000056715101701376024456 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ // Outputs a, b ); // verilator lint_off UNOPTFLAT output logic a, b; always_comb b = ~a; always_comb a = b; endmodule verilator-5.042/test_regress/t/t_var_bad_hide2.out0000644000542200017500000000077015101701376022617 0ustar mahmoudyfreeshell%Warning-VARHIDDEN: t/t_var_bad_hide2.v:14:12: Declaration of signal hides declaration in upper scope: 't' 14 | integer t; | ^ t/t_var_bad_hide2.v:7:8: ... Location of original declaration 7 | module t; | ^ ... For warning description see https://verilator.org/warn/VARHIDDEN?v=latest ... Use "/* verilator lint_off VARHIDDEN */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_display_io.v0000644000542200017500000000104215101701376021731 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: $display() test for %l // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Outputs o, // Inputs i ); input logic [95:0] i; output logic [95:0] o; string a_s; initial begin o = ~i; $sformat(a_s, "%h", i); $display(a_s); $sformat(a_s, "%h", o); $display(a_s); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_trace_no_top_name2_saif.py0000755000542200017500000000130115101701376024521 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.pli_filename = "t/t_trace_no_top_name2.cpp" test.top_filename = "t/t_trace_no_top_name2.v" test.compile(make_main=False, verilator_flags2=["--trace-saif --exe", test.pli_filename]) test.execute() test.saif_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_property_sexpr_cov.py0000755000542200017500000000111615101701376023741 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(timing_loop=True, verilator_flags2=['--assert', '--timing', '--coverage-user']) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_increment_bad.out0000644000542200017500000000241215101701376022733 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_increment_bad.v:21:31: Unsupported: Incrementation in this context. 21 | if (0 && test_string[pos++] != "e"); | ^~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_increment_bad.v:22:19: Unsupported: Incrementation in this context. 22 | if (1 || pos-- != 1); | ^~ %Error-UNSUPPORTED: t/t_increment_bad.v:24:17: Unsupported: Incrementation in this context. 24 | if (a <-> --b); | ^~ %Error-UNSUPPORTED: t/t_increment_bad.v:25:16: Unsupported: Incrementation in this context. 25 | if (0 -> ++b); | ^~ %Error-UNSUPPORTED: t/t_increment_bad.v:27:24: Unsupported: Incrementation in this context. 27 | pos = (a > 0) ? a++ : --b; | ^~ %Error-UNSUPPORTED: t/t_increment_bad.v:27:29: Unsupported: Incrementation in this context. 27 | pos = (a > 0) ? a++ : --b; | ^~ %Error-UNSUPPORTED: t/t_increment_bad.v:32:37: Unsupported: Incrementation in this context. 32 | assert property (@(posedge clk) a++ >= 0); | ^~ %Error: Exiting due to verilator-5.042/test_regress/t/t_class_static_member.v0000644000542200017500000000262315101701376023606 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); class Cls; class InnerCls; static function int f_inner_cs_st(); ++c_st; return c_st; endfunction endclass int c_no = 2; //automatic int c_au = 2; // automatic not a legal keyword here static int c_st = 22; function int f_c_no (); ++c_no; return c_no; endfunction function int f_c_st (); ++c_st; return c_st; endfunction static function int f_cs_st (); ++c_st; return c_st; endfunction endclass module t; Cls a = new; Cls b = new; int v; initial begin v = a.f_c_no(); `checkh(v, 3); v = a.f_c_no(); `checkh(v, 4); v = b.f_c_no(); `checkh(v, 3); v = b.f_c_no(); `checkh(v, 4); v = a.f_c_st(); `checkh(v, 23); v = a.f_c_st(); `checkh(v, 24); v = b.f_c_st(); `checkh(v, 25); v = b.f_c_st(); `checkh(v, 26); // v = Cls::f_cs_st(); `checkh(v, 27); v = Cls::InnerCls::f_inner_cs_st(); `checkh(v, 28); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_constraint_dyn_queue_basic.py0000755000542200017500000000104615101701376025372 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_flag_future.py0000755000542200017500000000114515101701376022272 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=[ "--lint-only --future0 thefuture --future1 thefuturei --thefuture -thefuture +thefuture --thefuturei 1 -Wfuture-FUTURE1 -Wfuture-FUTURE2" ]) test.passes() verilator-5.042/test_regress/t/t_mem_multi_io3_cc.py0000755000542200017500000000127715101701376023204 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_mem_multi_io3.cpp" test.top_filename = "t/t_mem_multi_io3.v" test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename, "-fno-inline"], verilator_flags3=[]) test.passes() verilator-5.042/test_regress/t/t_constraint_extern_bad.v0000644000542200017500000000051315101701376024156 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Packet; extern constraint missing_bad; endclass constraint Packet::missing_extern { } module t; endmodule verilator-5.042/test_regress/t/t_scheduling_3.v0000644000542200017500000000217415101701376022153 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2022 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VERILATOR // The '$c1(1)' is there to prevent inlining of the signal by V3Gate `define IMPURE_ONE $c(1); `else // Use standard $random (chaces of getting 2 consecutive zeroes is zero). `define IMPURE_ONE |($random | $random); `endif module top( clk ); input clk; reg clk_half = 0; reg [31:0] cyc = 0; reg [31:0] a, b, c; always @(posedge clk) begin $display("tick %d: a: %d, b: %d, c: %d", cyc, a, b, c); // Check invariant if (a !== cyc + 1) $stop; if (b !== cyc + 2) $stop; if (c !== cyc + 2) $stop; // End of test if (cyc == 100) begin $write("*-* All Finished *-*\n"); $finish; end cyc <= cyc + 1; end always @(a) b = a + `IMPURE_ONE; always @(cyc) a = cyc + `IMPURE_ONE; assign c = a + `IMPURE_ONE; endmodule verilator-5.042/test_regress/t/t_func_public_trace.py0000755000542200017500000000104415101701376023434 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_func_public.v" test.compile(verilator_flags2=["--trace-vcd"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_event_control_star.py0000755000542200017500000000102215101701376023673 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--timing"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_flag_invalid_bad.out0000644000542200017500000000021415101701376023364 0ustar mahmoudyfreeshell%Error: Invalid option: --invalid-dash ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. verilator-5.042/test_regress/t/t_lint_unsup_deassign.v0000644000542200017500000000064315101701376023660 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2016 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( input wire rst ); integer q; // verilator lint_off LATCH always @(*) if (rst) assign q = 0; else deassign q; // verilator lint_on LATCH endmodule verilator-5.042/test_regress/t/t_cover_main.py0000755000542200017500000000127015101701376022110 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--binary --coverage-line']) test.execute(all_run_flags=[" +verilator+coverage+file+" + test.obj_dir + "/coverage_renamed.dat"]) test.files_identical_sorted(test.obj_dir + "/coverage_renamed.dat", "t/t_cover_main.out") test.passes() verilator-5.042/test_regress/t/t_flag_mmd.py0000755000542200017500000000105415101701376021534 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["-MMD -MP"]) test.file_grep(test.obj_dir + "/Vt_flag_mmd__ver.d", r't/t_flag_mmd.v') test.passes() verilator-5.042/test_regress/t/t_interface_generic.py0000755000542200017500000000077115101701376023427 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--timing']) test.execute() test.passes() verilator-5.042/test_regress/t/t_select_bad_range3.v0000644000542200017500000000100515101701376023120 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2015 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs outwires, // Inputs inwires ); input [7:0] inwires [12:10]; output wire [7:0] outwires [12:10]; assign outwires[10] = inwires[11]; assign outwires[11] = inwires[12]; assign outwires[12] = inwires[13]; // must be an error here endmodule verilator-5.042/test_regress/t/t_std_process_self_std.py0000755000542200017500000000104515101701376024201 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_std_process_self.v" test.lint(verilator_flags2=["--binary --DUSE_STD_PREFIX"]) test.passes() verilator-5.042/test_regress/t/t_interface_gen3.py0000755000542200017500000000073415101701376022646 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_bench_mux4k.v0000644000542200017500000001130315101701376022005 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2008 by Lane Brooks. // SPDX-License-Identifier: CC0-1.0 // // This implements a 4096:1 mux via two stages of 64:1 muxing. // change these two parameters to see the speed differences //`define DATA_WIDTH 12 //`define MUX2_SIZE 32 `define DATA_WIDTH 2 `define MUX2_SIZE 8 // if you change these, then the testbench will break `define ADDR_WIDTH 12 `define MUX1_SIZE 64 // Total of DATA_WIDTH*MUX2_SIZE*(MUX1_SIZE+1) instantiations of mux64 module t (/*AUTOARG*/ // Inputs clk ); input clk; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [`DATA_WIDTH-1:0] datao; // From mux4096 of mux4096.v // End of automatics reg [`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0] datai; reg [`ADDR_WIDTH-1:0] addr; // Mux: takes in addr and datai and outputs datao mux4096 mux4096 (/*AUTOINST*/ // Outputs .datao (datao[`DATA_WIDTH-1:0]), // Inputs .datai (datai[`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0]), .addr (addr[`ADDR_WIDTH-1:0])); // calculate what the answer should be from datai. This is bit // tricky given the way datai gets sliced. datai is in bit // planes where all the LSBs are contiguous and then the next bit. reg [`DATA_WIDTH-1:0] datao_check; integer j; always @(datai or addr) begin for(j=0;j<`DATA_WIDTH;j=j+1) begin /* verilator lint_off WIDTH */ datao_check[j] = datai >> ((`MUX1_SIZE*`MUX2_SIZE*j)+addr); /* verilator lint_on WIDTH */ end end // Run the test loop. This just increments the address integer i, result; always @ (posedge clk) begin // initial the input data with random values if (addr == 0) begin result = 1; datai = 0; for(i=0; i<`MUX1_SIZE*`MUX2_SIZE; i=i+1) begin /* verilator lint_off WIDTH */ datai = (datai << `DATA_WIDTH) | ($random & {`DATA_WIDTH{1'b1}}); /* verilator lint_on WIDTH */ end end addr <= addr + 1; if (datao_check != datao) begin result = 0; $stop; end `ifdef TEST_VERBOSE $write("Addr=%d datao_check=%d datao=%d\n", addr, datao_check, datao); `endif // only run the first 10 addresses for now if (addr > 10) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module mux4096 (input [`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0] datai, input [`ADDR_WIDTH-1:0] addr, output [`DATA_WIDTH-1:0] datao ); // DATA_WIDTH instantiations of mux4096_1bit mux4096_1bit mux4096_1bit[`DATA_WIDTH-1:0] (.addr(addr), .datai(datai), .datao(datao) ); endmodule module mux4096_1bit (input [`MUX1_SIZE*`MUX2_SIZE-1:0] datai, input [`ADDR_WIDTH-1:0] addr, output datao ); // address decoding wire [3:0] A = (4'b1) << addr[1:0]; wire [3:0] B = (4'b1) << addr[3:2]; wire [3:0] C = (4'b1) << addr[5:4]; wire [3:0] D = (4'b1) << addr[7:6]; wire [3:0] E = (4'b1) << addr[9:8]; wire [3:0] F = (4'b1) << addr[11:10]; wire [`MUX2_SIZE-1:0] data0; // DATA_WIDTH*(MUX2_SIZE)*MUX1_SIZE instantiations of mux64 // first stage of 64:1 muxing mux64 #(.MUX_SIZE(`MUX1_SIZE)) mux1[`MUX2_SIZE-1:0] (.A(A), .B(B), .C(C), .datai(datai), .datao(data0)); // DATA_WIDTH*MUX2_SIZE instantiations of mux64 // second stage of 64:1 muxing mux64 #(.MUX_SIZE(`MUX2_SIZE)) mux2 (.A(D), .B(E), .C(F), .datai(data0), .datao(datao)); endmodule module mux64 #(parameter MUX_SIZE=64) (input [3:0] A, input [3:0] B, input [3:0] C, input [MUX_SIZE-1:0] datai, output datao ); wire [63:0] colSelA = { 16{ A[3:0] }}; wire [63:0] colSelB = { 4{ {4{B[3]}}, {4{B[2]}}, {4{B[1]}}, {4{B[0]}}}}; wire [63:0] colSelC = { {16{C[3]}}, {16{C[2]}}, {16{C[1]}}, {16{C[0]}}}; wire [MUX_SIZE-1:0] data_bus; // Note each of these becomes a separate wire. //.colSelA(colSelA[MUX_SIZE-1:0]), //.colSelB(colSelB[MUX_SIZE-1:0]), //.colSelC(colSelC[MUX_SIZE-1:0]), drv drv[MUX_SIZE-1:0] (.colSelA(colSelA[MUX_SIZE-1:0]), .colSelB(colSelB[MUX_SIZE-1:0]), .colSelC(colSelC[MUX_SIZE-1:0]), .datai(datai), .datao(data_bus) ); assign datao = |data_bus; endmodule module drv (input colSelA, input colSelB, input colSelC, input datai, output datao ); assign datao = colSelC & colSelB & colSelA & datai; endmodule verilator-5.042/test_regress/t/t_sarif.out0000644000542200017500000000276215101701376021255 0ustar mahmoudyfreeshell%Warning-MODDUP: t/t_sarif.v:21:8: Duplicate declaration of module: 't' 21 | module t; | ^ t/t_sarif.v:7:8: ... Location of original declaration 7 | module t( | ^ ... For warning description see https://verilator.org/warn/MODDUP?v=latest ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message. %Warning-WIDTHTRUNC: t/t_sarif.v:12:23: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's CONST '5'h1f' generates 5 bits. : ... note: In instance 't' 12 | wire [1:0] trunced = 5'b11111; | ^ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Warning-MULTIDRIVEN: t/t_sarif.v:10:18: Signal has multiple driving blocks with different clocking: 'multidriven' t/t_sarif.v:15:6: ... Location of first driving block 15 | multidriven <= '1; | ^~~~~~~~~~~ t/t_sarif.v:17:6: ... Location of other driving block 17 | multidriven <= '0; | ^~~~~~~~~~~ ... For warning description see https://verilator.org/warn/MULTIDRIVEN?v=latest ... Use "/* verilator lint_off MULTIDRIVEN */" and lint_on around source to disable this message. verilator-5.042/test_regress/t/t_tri_select_unsized.py0000755000542200017500000000075315101701376023671 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["-Wno-WIDTH"]) test.passes() verilator-5.042/test_regress/t/t_langext_1.py0000755000542200017500000000101115101701376021641 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') # This is a compile only test. test.compile(v_flags2=["+verilog2001ext+v"]) test.passes() verilator-5.042/test_regress/t/t_trace_dumporder_bad.py0000755000542200017500000000102515101701376023751 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["-trace"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_repeat_bad.out0000644000542200017500000000101415101701376023252 0ustar mahmoudyfreeshell%Warning-WIDTHTRUNC: t/t_lint_repeat_bad.v:18:17: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS's VARREF 'a' generates 2 bits. : ... note: In instance 't.sub3' 18 | wire [0:0] b = a; | ^ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_flag_make_cmake.py0000755000542200017500000000122215101701376023031 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_make_gmake=False, verilator_make_cmake=True) cmakecache = test.obj_dir + "/CMakeCache.txt" if not os.path.exists(cmakecache): test.error(cmakecache + " does not exist") test.execute() test.passes() verilator-5.042/test_regress/t/t_randomize_complex.py0000755000542200017500000000104615101701376023506 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_stream4.v0000644000542200017500000000144315101701376021161 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2021 by Adrien Le Masle. // SPDX-License-Identifier: CC0-1.0 //module t; module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; logic [63:0] din; logic [63:0] dout; always_comb begin dout = {<<8{din}}; end always @(posedge clk) begin if (cyc != 0) begin cyc <= cyc + 1; if (cyc == 1) begin din <= 64'h1122334455667788; end if (cyc == 2) begin if (dout != 64'h8877665544332211) $stop; end if (cyc == 3) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.042/test_regress/t/t_queue.py0000755000542200017500000000073415101701376021116 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_queue_compare.v0000644000542200017500000000316715101701376022441 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Check == and != operations performed on queues // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Ilya Barkov. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define check_comp(lhs, rhs, op, exp) if ((exp) != ((lhs) op (rhs))) begin $write("%%Error: %s:%0d: op comparison shall return 'b%x\n", `__FILE__, `__LINE__, (exp)); `stop; end // Two checks because == and != may not be derived from each other `define check_eq(lhs, rhs) `check_comp(lhs, rhs, ==, 1'b1) `check_comp(lhs, rhs, !=, 1'b0) `define check_ne(lhs, rhs) `check_comp(lhs, rhs, ==, 1'b0) `check_comp(lhs, rhs, !=, 1'b1) class Cls; int i; endclass module t; initial begin begin // integers int q1[$]; bit signed [31:0] q2[$]; q1.push_back(1); q2.push_back(1); q1.push_back(-2); q2.push_back(-2); `check_eq(q1, q2) q2.push_back(3); `check_ne(q1, q2) end begin // strings string q1[$]; string q2[$]; q1.push_back("one"); q2.push_back("one"); q1.push_back("two"); q2.push_back("two"); `check_eq(q1, q2) q2.push_back("three"); `check_ne(q1, q2) end begin // classes Cls a = new; Cls b = new; Cls q1[$]; Cls q2[$]; q1.push_back(a); q2.push_back(b); `check_ne(q1, q2) q1.push_back(b); q2.push_front(a); `check_eq(q1, q2) end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_array_type_methods.v0000644000542200017500000000177015101701376023507 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t; logic [3:0] foo [1:0]; logic [3:0] fooe [1:0]; initial begin foo[0] = 4'b0101; foo[1] = 4'b0011; `checkh(foo.or, 4'b0111); `checkh(foo.and, 4'b0001); `checkh(foo.xor, 4'b0110); `checkh(foo.sum, 4'b1000); `checkh(foo.product, 4'b1111); fooe[0] = 4'b0101; fooe[1] = 4'b0011; if (foo != fooe) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_inst_public.v0000644000542200017500000000100115101701376022103 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; Pub pub(); localparam ZERO = 0; if (ZERO) Dead dead(); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule module Pub; // verilator public_module // no signals here endmodule module Dead; // verilator public_module endmodule verilator-5.042/test_regress/t/t_opt_inline_funcs.py0000755000542200017500000000111215101701376023317 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=['--stats'], verilator_make_gmake=False) test.file_grep(test.stats, r'Optimizations, Functions inlined\s+(\d+)', 2) test.passes() verilator-5.042/test_regress/t/t_clk_vecgen1.py0000755000542200017500000000111115101701376022141 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_clk_vecgen1.v" test.compile(v_flags2=['+define+T_TEST1']) test.execute(all_run_flags=["+verilator+rand+reset+0"]) test.passes() verilator-5.042/test_regress/t/t_interface_modport_import_noinl.py0000755000542200017500000000105115101701376026260 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_modport_import.v" test.compile(v_flags2=["-fno-inline"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_math_insert_bound.py0000755000542200017500000000073415101701376023476 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_flag_bboxsys.py0000755000542200017500000000076515101701376022460 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["--bbox-sys"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_hier_block0_bad.py0000755000542200017500000000103015101701376022747 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, verilator_flags2=['--hierarchical'], expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dpi_accessors.cpp0000644000542200017500000006273015101701376022746 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2012 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // // Contributed by Jeremy Bennett and Jie Xu // //************************************************************************* #include "Vt_dpi_accessors.h" #include "Vt_dpi_accessors__Dpi.h" #include "svdpi.h" #include #include // Convenience function to check we didn't finish unexpectedly static void checkFinish(VerilatedContext* contextp, const char* msg) { if (contextp->gotFinish()) { vl_fatal(__FILE__, __LINE__, "dut", msg); exit(1); } } // Convenience function to log the value of a register in hex. Only in verbose // mode. static void logReg(int clk, const char* desc, int val, const char* note) { #ifdef TEST_VERBOSE std::cout << "clk = " << clk << ", " << desc << " = " << val << note << std::endl; #endif } // Convenience function to log the value of a register in hex. Only in verbose // mode. static void logRegHex(int clk, const char* desc, int bitWidth, int val, const char* note) { #ifdef TEST_VERBOSE std::cout << "clk = " << clk << ", " << desc << " = " << bitWidth << "\'h" << std::hex << std::setw((bitWidth - 1) / 4 + 1) << std::setfill('0') << val << std::setfill(' ') << std::setw(0) << std::dec << note << std::endl; #endif } // Convenience function to check we got an expected result. Silent on success. #define CHECK_RESULT(p, msg_fail) \ do { \ if (!(p)) vl_fatal(__FILE__, __LINE__, "dut", (msg_fail)); \ } while (0) // Main function instantiates the model and steps through the test. int main() { const std::unique_ptr contextp{new VerilatedContext}; const std::unique_ptr dut{new VM_PREFIX{contextp.get(), "dut"}}; svScope scope = svGetScopeFromName("dut.t"); if (!scope) vl_fatal(__FILE__, __LINE__, "dut", "No svGetScopeFromName result"); svSetScope(scope); // evaluate the model with no signal changes to get the initial blocks // executed. dut->eval(); #ifdef TEST_VERBOSE std::cout << "Initial DPI values\n"; std::cout << "==================\n"; #endif int a = (int)a_read(); int b = (int)b_read(); int mem32 = (int)mem32_read(); int c = (int)c_read(); int d = (int)d_read(); int e = (int)e_read(); int f = (int)f_read(); #ifdef TEST_VERBOSE std::cout << "Read a = " << a << std::endl; std::cout << "Read b = 8'h" << std::hex << std::setw(2) << std::setfill('0') << b << std::setfill(' ') << std::setw(0) << std::dec << std::endl; std::cout << "Read mem32 = 8'h" << std::hex << std::setw(2) << std::setfill('0') << mem32 << std::setfill(' ') << std::setw(0) << std::dec << std::endl; std::cout << "Read c = " << c << std::endl; std::cout << "Read d = 8'h" << std::hex << std::setw(2) << std::setfill('0') << d << std::setfill(' ') << std::setw(0) << std::dec << std::endl; std::cout << "Read e = 8'h" << std::hex << std::setw(2) << std::setfill('0') << e << std::setfill(' ') << std::setw(0) << std::dec << std::endl; std::cout << "Read f = 8'h" << std::hex << std::setw(2) << std::setfill('0') << f << std::setfill(' ') << std::setw(0) << std::dec << std::endl; std::cout << std::endl; #endif CHECK_RESULT((0 == a) && (0x00 == b) && (0x20 == mem32) && (1 == c) && (0xff == d) && (0x00 == e) && (0x00 == f), "Bad initial DPI values."); // Initialize the clock dut->clk = 0; // Check we can read a scalar register. #ifdef TEST_VERBOSE std::cout << "Test of scalar register reading\n"; std::cout << "===============================\n"; #endif for (int i = 0; !contextp->gotFinish() && (i < 4); i++) { dut->clk = 1 - dut->clk; a = (int)a_read(); logReg(dut->clk, "read a", a, " (before clk)"); dut->eval(); int a_after = (int)a_read(); logReg(dut->clk, "read a", a_after, " (after clk)"); #ifdef TEST_VERBOSE std::cout << std::endl; #endif // On a posedge, a should toggle, on a negedge it should stay the // same. CHECK_RESULT(((dut->clk == 1) && (a_after == (1 - a))) || ((dut->clk == 0) && (a_after == a)), "Test of scalar register reading failed."); } checkFinish(contextp.get(), "t_dpi_accessors unexpected finish"); // Check we can read a vector register. #ifdef TEST_VERBOSE std::cout << "Test of vector register reading\n"; std::cout << "===============================\n"; #endif for (int i = 0; !contextp->gotFinish() && (i < 4); i++) { dut->clk = 1 - dut->clk; b = (int)b_read(); logRegHex(dut->clk, "read b", 8, b, " (before clk)"); dut->eval(); int b_after = (int)b_read(); logRegHex(dut->clk, "read b", 8, b_after, " (after clk)"); // b should increment on a posedge and stay the same on a negedge. CHECK_RESULT(((dut->clk == 1) && (b_after == (b + 1))) || ((dut->clk == 0) && (b_after == b)), "Test of vector register reading failed."); } checkFinish(contextp.get(), "t_dpi_accessors unexpected finish"); // Test we can read an array element #ifdef TEST_VERBOSE std::cout << std::endl; std::cout << "Test of array element reading\n"; std::cout << "=============================\n"; #endif for (int i = 0; !contextp->gotFinish() && (i < 4); i++) { dut->clk = 1 - dut->clk; mem32 = (int)mem32_read(); logRegHex(dut->clk, "read mem32", 8, mem32, " (before clk)"); dut->eval(); mem32 = (int)mem32_read(); logRegHex(dut->clk, "read mem32", 8, mem32, " (after clk)"); // In this case, the value never changes. But we should check it is // what we expect (0x20). CHECK_RESULT(mem32 == 0x20, "Test of array element reading failed."); } checkFinish(contextp.get(), "t_dpi_accessors unexpected finish"); // Check we can read a scalar wire #ifdef TEST_VERBOSE std::cout << std::endl; std::cout << "Test of scalar wire reading\n"; std::cout << "===========================\n"; #endif for (int i = 0; !contextp->gotFinish() && (i < 4); i++) { dut->clk = 1 - dut->clk; a = (int)a_read(); c = (int)c_read(); logReg(dut->clk, "read a", a, " (before clk)"); logReg(dut->clk, "read c", c, " (before clk)"); dut->eval(); a = (int)a_read(); c = (int)c_read(); logReg(dut->clk, "read a", a, " (after clk)"); logReg(dut->clk, "read c", c, " (after clk)"); // "c" is continuously assigned as the inverse of "a", but in // Verilator, that means that it will only change value when "a" // changes on the posedge of a clock. That is "c" always holds the // inverse of the "after clock" value of "a". CHECK_RESULT(c == (1 - a), "Test of scalar wire reading failed."); } checkFinish(contextp.get(), "t_dpi_accessors unexpected finish"); // Check we can read a vector wire #ifdef TEST_VERBOSE std::cout << std::endl; std::cout << "Test of vector wire reading\n"; std::cout << "===========================\n"; #endif for (int i = 0; !contextp->gotFinish() && (i < 4); i++) { dut->clk = 1 - dut->clk; b = (int)b_read(); d = (int)d_read(); logRegHex(dut->clk, "read b", 8, b, " (before clk)"); logRegHex(dut->clk, "read d", 8, d, " (before clk)"); dut->eval(); b = (int)b_read(); d = (int)d_read(); logRegHex(dut->clk, "read b", 8, b, " (after clk)"); logRegHex(dut->clk, "read d", 8, d, " (after clk)"); // "d" is continuously assigned as the (8-bit) bitwise inverse of "b", // but in Verilator, that means that it will only change value when // "b" changes on the posedge of a clock. That is "d" always holds // the inverse of the "after clock" value of "b". CHECK_RESULT(d == ((~b) & 0xff), "Test of vector wire reading failed."); } checkFinish(contextp.get(), "t_dpi_accessors unexpected finish"); // Check we can write a scalar register #ifdef TEST_VERBOSE std::cout << std::endl; std::cout << "Test of scalar register writing\n"; std::cout << "===============================\n"; #endif for (int i = 0; !contextp->gotFinish() && (i < 4); i++) { dut->clk = 1 - dut->clk; a = 1 - (int)a_read(); a_write(reinterpret_cast(&a)); logReg(dut->clk, "write a", a, " (before clk)"); a = a_read(); logReg(dut->clk, "read a", a, " (before clk)"); dut->eval(); int a_after = (int)a_read(); logReg(dut->clk, "read a", a_after, " (after clk)"); // On a posedge clock, the value of a that is written should toggle, // on a negedge, it should not. CHECK_RESULT(((dut->clk == 1) && (a_after == (1 - a))) || ((dut->clk == 0) && (a_after == a)), "Test of scalar register writing failed."); } checkFinish(contextp.get(), "t_dpi_accessors unexpected finish"); // Check we can write a vector register #ifdef TEST_VERBOSE std::cout << std::endl; std::cout << "Test of vector register writing\n"; std::cout << "===============================\n"; #endif for (int i = 0; !contextp->gotFinish() && (i < 4); i++) { dut->clk = 1 - dut->clk; b = (int)b_read() - 1; b_write(reinterpret_cast(&b)); logRegHex(dut->clk, "write b", 8, b, " (before clk)"); b = (int)b_read(); logRegHex(dut->clk, "read b", 8, b, " (before clk)"); dut->eval(); int b_after = (int)b_read(); logRegHex(dut->clk, "read b", 8, b_after, " (after clk)"); // The value of "b" written should increment on a posedge and stay the // same on a negedge. CHECK_RESULT(((dut->clk == 1) && (b_after == (b + 1))) || ((dut->clk == 0) && (b_after == b)), "Test of vector register writing failed."); } checkFinish(contextp.get(), "t_dpi_accessors unexpected finish"); // Test we can write an array element #ifdef TEST_VERBOSE std::cout << std::endl; std::cout << "Test of array element writing\n"; std::cout << "=============================\n"; #endif for (int i = 0; !contextp->gotFinish() && (i < 4); i++) { dut->clk = 1 - dut->clk; mem32 = (int)mem32_read() - 1; mem32_write(reinterpret_cast(&mem32)); logRegHex(dut->clk, "write mem32", 8, mem32, " (before clk)"); mem32 = (int)mem32_read(); logRegHex(dut->clk, "read mem32", 8, mem32, " (before clk)"); dut->eval(); int mem32_after = (int)mem32_read(); logRegHex(dut->clk, "read mem32", 8, mem32_after, " (after clk)"); // In this case, the value we write never changes (this would only // happen if this part of the test coincided with the 32nd element // being overwritten, which it does not. Check that the value after // the clock is the same as before the clock. CHECK_RESULT(mem32_after == mem32, "Test of array element writing failed."); } checkFinish(contextp.get(), "t_dpi_accessors unexpected finish"); // Check we can read a vector register slice #ifdef TEST_VERBOSE std::cout << std::endl; std::cout << "Test of vector register slice reading\n"; std::cout << "=====================================\n"; #endif for (int i = 0; !contextp->gotFinish() && (i < 4); i++) { dut->clk = 1 - dut->clk; b = (int)b_read(); int b_slice = (int)b_slice_read(); logRegHex(dut->clk, "read b [7:0]", 8, b, " (before clk)"); logRegHex(dut->clk, "read b [3:0]", 4, b_slice, " (before clk)"); dut->eval(); b = (int)b_read(); b_slice = (int)b_slice_read(); logRegHex(dut->clk, "read b [7:0]", 8, b, " (after clk)"); logRegHex(dut->clk, "read b [3:0]", 4, b_slice, " (after clk)"); // The slice of "b" should always be the bottom 4 bits of "b" CHECK_RESULT(b_slice == (b & 0x0f), "Test of vector register slice reading failed."); } checkFinish(contextp.get(), "t_dpi_accessors unexpected finish"); // Test we can read an array element slice #ifdef TEST_VERBOSE std::cout << std::endl; std::cout << "Test of array element slice reading\n"; std::cout << "===================================\n"; #endif for (int i = 0; !contextp->gotFinish() && (i < 4); i++) { dut->clk = 1 - dut->clk; mem32 = (int)mem32_read(); int mem32_slice = (int)mem32_slice_read(); logRegHex(dut->clk, "read mem32 [7:0] ", 8, mem32, " (before clk)"); logRegHex(dut->clk, "read mem32 [7:6,2:0]", 5, mem32_slice, " (before clk)"); dut->eval(); mem32 = (int)mem32_read(); mem32_slice = (int)mem32_slice_read(); logRegHex(dut->clk, "read mem32 [7:0] ", 8, mem32, " (after clk)"); logRegHex(dut->clk, "read mem32 [7:6,2:0]", 5, mem32_slice, " (after clk)"); // The slice of "mem32" should always be the concatenation of the top // 2 and bottom 3 bits of "mem32" CHECK_RESULT(mem32_slice == (((mem32 & 0xc0) >> 3) | (mem32 & 0x07)), "Test of array element slice reading failed."); } checkFinish(contextp.get(), "t_dpi_accessors unexpected finish"); // Check we can read a vector wire slice #ifdef TEST_VERBOSE std::cout << std::endl; std::cout << "Test of vector wire slice reading\n"; std::cout << "=================================\n"; #endif for (int i = 0; !contextp->gotFinish() && (i < 4); i++) { dut->clk = 1 - dut->clk; b = (int)b_read(); d = (int)d_read(); int d_slice = (int)d_slice_read(); logRegHex(dut->clk, "read b [7:0]", 8, b, " (before clk)"); logRegHex(dut->clk, "read d [7:0]", 8, d, " (before clk)"); logRegHex(dut->clk, "read d [6:1]", 6, d_slice, " (before clk)"); dut->eval(); b = (int)b_read(); d = (int)d_read(); d_slice = (int)d_slice_read(); logRegHex(dut->clk, "read b [7:0]", 8, b, " (after clk)"); logRegHex(dut->clk, "read d [7:0]", 8, d, " (after clk)"); logRegHex(dut->clk, "read d [6:1]", 6, d_slice, " (after clk)"); // The slice of "d" should always be the middle 6 bits of "d". CHECK_RESULT(d_slice == ((d & 0x7e) >> 1), "Test of vector wire slice reading failed."); } checkFinish(contextp.get(), "t_dpi_accessors unexpected finish"); // Check we can write a vector register slice #ifdef TEST_VERBOSE std::cout << std::endl; std::cout << "Test of vector register slice writing\n"; std::cout << "=====================================\n"; #endif for (int i = 0; !contextp->gotFinish() && (i < 4); i++) { dut->clk = 1 - dut->clk; b = (int)b_read(); int b_slice = (int)b_slice_read(); logRegHex(dut->clk, "read b [7:0]", 8, b, " (before write)"); logRegHex(dut->clk, "read b [3:0]", 4, b_slice, " (before write)"); b_slice--; b_slice_write(reinterpret_cast(&b_slice)); logRegHex(dut->clk, "write b [3:0]", 4, b_slice, " (before clk)"); int b_after = (int)b_read(); int b_slice_after = (int)b_slice_read(); logRegHex(dut->clk, "read b [7:0]", 8, b_after, " (before clk)"); logRegHex(dut->clk, "read b [3:0]", 4, b_slice_after, " (before clk)"); // We must test that when we wrote the slice of "b", we only wrote the // correct bits. The slice of b is b[3:0] int b_new = (b & 0xf0) | (b_slice & 0x0f); CHECK_RESULT(b_after == b_new, "Test of vector register slice writing failed."); dut->eval(); b = (int)b_read(); b_slice = (int)b_slice_read(); logRegHex(dut->clk, "read b [7:0]", 8, b, " (after clk)"); logRegHex(dut->clk, "read b [3:0]", 4, b_slice, " (after clk)"); } checkFinish(contextp.get(), "t_dpi_accessors unexpected finish"); // Test we can write an array element slice #ifdef TEST_VERBOSE std::cout << std::endl; std::cout << "Test of array element slice writing\n"; std::cout << "===================================\n"; #endif for (int i = 0; !contextp->gotFinish() && (i < 4); i++) { dut->clk = 1 - dut->clk; mem32 = (int)mem32_read(); int mem32_slice = (int)mem32_slice_read(); logRegHex(dut->clk, "read mem32 [7:0] ", 8, mem32, " (before write)"); logRegHex(dut->clk, "read mem32 [7:6,2:0]", 5, mem32_slice, " (before write)"); mem32_slice--; mem32_slice_write(reinterpret_cast(&mem32_slice)); logRegHex(dut->clk, "write mem32 [7:6,2:0]", 5, mem32_slice, " (before clk)"); int mem32_after = (int)mem32_read(); int mem32_slice_after = (int)mem32_slice_read(); logRegHex(dut->clk, "read mem32 [7:0] ", 8, mem32_after, " (before clk)"); logRegHex(dut->clk, "read mem32 [7:6,2:0]", 5, mem32_slice_after, " (before clk)"); // We must test that when we wrote the slice of "mem32", we only wrote // the correct bits. The slice of "mem32" is {mem32[7:6], mem32[2:0]}. int mem32_new = (mem32 & 0x38) | ((mem32_slice & 0x18) << 3) | (mem32_slice & 0x7); CHECK_RESULT(mem32_after == mem32_new, "Test of vector register slice writing failed."); dut->eval(); mem32 = (int)mem32_read(); mem32_slice = (int)mem32_slice_read(); logRegHex(dut->clk, "read mem32 [7:0] ", 8, mem32, " (after clk)"); logRegHex(dut->clk, "read mem32 [7:6,2:0]", 5, mem32_slice, " (after clk)"); // We have already tested that array element writing works, so we just // check that the slice of "mem32" after the clock is the // concatenation of the top 2 and bottom 3 bits of "mem32" CHECK_RESULT(mem32_slice == (((mem32 & 0xc0) >> 3) | (mem32 & 0x07)), "Test of array element slice writing failed."); } checkFinish(contextp.get(), "t_dpi_accessors unexpected finish"); // Check we can read complex registers #ifdef TEST_VERBOSE std::cout << std::endl; std::cout << "Test of complex register reading\n"; std::cout << "================================\n"; #endif for (int i = 0; !contextp->gotFinish() && (i < 4); i++) { dut->clk = 1 - dut->clk; b = (int)b_read(); mem32 = (int)mem32_read(); e = (int)e_read(); int l1 = (int)l1_read(); logRegHex(dut->clk, "read b ", 8, b, " (before clk)"); logRegHex(dut->clk, "read mem32", 8, mem32, " (before clk)"); logRegHex(dut->clk, "read e ", 8, e, " (before clk)"); logRegHex(dut->clk, "read l1 ", 15, l1, " (before clk)"); dut->eval(); b = (int)b_read(); mem32 = (int)mem32_read(); e = (int)e_read(); l1 = (int)l1_read(); logRegHex(dut->clk, "read b ", 8, b, " (after clk)"); logRegHex(dut->clk, "read mem32", 8, mem32, " (after clk)"); logRegHex(dut->clk, "read e ", 8, e, " (after clk)"); logRegHex(dut->clk, "read l1 ", 15, l1, " (after clk)"); // We have already tested that reading of registers, memory elements // and wires works. So we just need to check that l1 reads back as the // correct combination of bits after the clock. It should be the 15 // bits: {b[3:0],mem[32][7:6],e[6:1],mem[32][2:0]}. CHECK_RESULT(l1 == ((((b & 0x0f) >> 0) << 11) | (((mem32 & 0xc0) >> 6) << 9) | (((e & 0x7e) >> 1) << 3) | (((mem32 & 0x07) >> 0) << 0)), "Test of complex register reading l1 failed."); } #ifdef TEST_VERBOSE std::cout << std::endl; #endif checkFinish(contextp.get(), "t_dpi_accessors unexpected finish"); for (int i = 0; !contextp->gotFinish() && (i < 4); i++) { dut->clk = 1 - dut->clk; e = 0x05 | (i << 4); f = 0xa0 | i; e_write(reinterpret_cast(&e)); f_write(reinterpret_cast(&f)); e = (int)e_read(); f = (int)f_read(); int l2 = (int)l2_read(); logRegHex(dut->clk, "read e ", 8, e, " (before clk)"); logRegHex(dut->clk, "read f ", 8, f, " (before clk)"); logRegHex(dut->clk, "read l2", 8, l2, " (before clk)"); dut->eval(); e = (int)e_read(); f = (int)f_read(); l2 = (int)l2_read(); logRegHex(dut->clk, "read e ", 8, e, " (before clk)"); logRegHex(dut->clk, "read f ", 8, f, " (before clk)"); logRegHex(dut->clk, "read l2", 8, l2, " (before clk)"); // We have already tested that reading of registers, memory elements // and wires works. So we just need to check that l1 reads back as the // correct combination of bits after the clock. It should be the 8 // bits: {e[7:4], f[3:0]}. CHECK_RESULT(l2 == ((e & 0xf0) | (f & 0x0f)), "Test of complex register reading l2 failed."); } checkFinish(contextp.get(), "t_dpi_accessors unexpected finish"); // Test we can write a complex register #ifdef TEST_VERBOSE std::cout << std::endl; std::cout << "Test of complex register writing\n"; std::cout << "================================\n"; #endif for (int i = 0; !contextp->gotFinish() && (i < 4); i++) { dut->clk = 1 - dut->clk; b = (int)b_read(); mem32 = (int)mem32_read(); e = (int)e_read(); logRegHex(dut->clk, "read b ", 8, b, " (before write)"); logRegHex(dut->clk, "read mem32", 8, mem32, " (before write)"); logRegHex(dut->clk, "read e ", 8, e, " (before write)"); int l1 = 0x5a5a; l1_write(reinterpret_cast(&l1)); logRegHex(dut->clk, "write l1 ", 15, l1, " (before clk)"); int b_after = (int)b_read(); int mem32_after = (int)mem32_read(); int e_after = (int)e_read(); int l1_after = (int)l1_read(); logRegHex(dut->clk, "read b ", 8, b_after, " (before clk)"); logRegHex(dut->clk, "read mem32", 8, mem32_after, " (before clk)"); logRegHex(dut->clk, "read e ", 8, e_after, " (before clk)"); logRegHex(dut->clk, "read l1 ", 15, l1_after, " (before clk)"); // We need to check that when we write l1, the correct fields, and // only the correct fields are set in its component registers, wires // and memory elements. l1 is 15 bits: // {b[3:0],mem[32][7:6],e[6:1],mem[32][2:0]}. int b_new = (b & 0xf0) | ((l1 & 0x7800) >> 11); int mem32_new = (mem32 & 0x38) | ((l1 & 0x0600) >> 3) | (l1 & 0x0007); int e_new = (e & 0x81) | ((l1 & 0x01f8) >> 2); CHECK_RESULT((b_new == b_after) && (mem32_new == mem32_after) && (e_new == e_after), "Test of complex register writing l1 failed."); dut->eval(); b = (int)b_read(); mem32 = (int)mem32_read(); d = (int)d_read(); l1 = (int)l1_read(); logRegHex(dut->clk, "read b ", 8, b, " (after clk)"); logRegHex(dut->clk, "read mem32", 8, mem32, " (after clk)"); logRegHex(dut->clk, "read d ", 8, d, " (after clk)"); logRegHex(dut->clk, "read l1 ", 15, l1, " (after clk)"); } #ifdef TEST_VERBOSE std::cout << std::endl; #endif checkFinish(contextp.get(), "t_dpi_accessors unexpected finish"); for (int i = 0; !contextp->gotFinish() && (i < 4); i++) { dut->clk = 1 - dut->clk; e = (int)e_read(); f = (int)f_read(); logRegHex(dut->clk, "read e ", 8, e, " (before write)"); logRegHex(dut->clk, "read f ", 8, f, " (before write)"); int l2 = 0xa5 + i; l2_write(reinterpret_cast(&l2)); logRegHex(dut->clk, "write l2", 8, l2, " (before clk)"); int e_after = (int)e_read(); int f_after = (int)f_read(); int l2_after = (int)l2_read(); logRegHex(dut->clk, "read e ", 8, e_after, " (before clk)"); logRegHex(dut->clk, "read f ", 8, f_after, " (before clk)"); logRegHex(dut->clk, "read l2", 8, l2_after, " (before clk)"); // We need to check that when we write l2, the correct fields, and // only the correct fields are set in its component registers. l is 8 // bits: {e[5:2], f[5:2]} int e_new = (e & 0xc3) | ((l2 & 0xf0) >> 2); int f_new = (f & 0xc3) | ((l2 & 0x0f) << 2); CHECK_RESULT((e_new == e_after) && (f_new == f_after), "Test of complex register writing l2 failed."); dut->eval(); e = (int)e_read(); f = (int)f_read(); l2 = (int)l2_read(); logRegHex(dut->clk, "read e ", 8, e, " (before clk)"); logRegHex(dut->clk, "read f ", 8, f, " (before clk)"); logRegHex(dut->clk, "read l2", 8, l2, " (before clk)"); } checkFinish(contextp.get(), "t_dpi_accessors unexpected finish"); // Tidy up dut->final(); std::cout << "*-* All Finished *-*\n"; } // Local Variables: // c-file-style:"cc-mode" // End: verilator-5.042/test_regress/t/t_fuzz_genintf_bad.out0000644000542200017500000000043715101701376023464 0ustar mahmoudyfreeshell%Error: t/t_fuzz_genintf_bad.v:24:11: Mixing positional and .*/named instantiation connection (IEEE 1800-2023 23.3.2) 24 | j.e(0), | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_inst_dff.py0000755000542200017500000000073415101701376021566 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_hier_block_sc_trace_vcd.py0000755000542200017500000000314515101701376024571 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_hier_block.v" # stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. test.clean_objs() # CI environment offers 2 VCPUs, 2 thread setting causes the following warning. # %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. # So use 6 threads here though it's not optimal in performance, but ok. test.compile(v_flags2=['t/t_hier_block.cpp'], verilator_flags2=[ '--sc', '--stats', '--hierarchical', '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"', "--CFLAGS", '"-O0 -ggdb"', "--trace-vcd" ], threads=(6 if test.vltmt else 1)) test.execute() test.file_grep(test.obj_dir + "/Vsub0/sub0.sv", r'^module\s+(\S+)\s+', "sub0") test.file_grep(test.obj_dir + "/Vsub1/sub1.sv", r'^module\s+(\S+)\s+', "sub1") test.file_grep(test.obj_dir + "/Vsub2/sub2.sv", r'^module\s+(\S+)\s+', "sub2") test.file_grep(test.stats, r'HierBlock,\s+Hierarchical blocks\s+(\d+)', 14) test.file_grep(test.run_log_filename, r'MACRO:(\S+) is defined', "cplusplus") test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface_generic_modport.v0000644000542200017500000000105515101701376025001 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 interface inf; int v; modport mp ( input v ); endinterface module GenericModule (interface.mp a); initial begin #1; if (a.v != 7) $stop; end endmodule module t; inf inf_inst(); GenericModule genericModule (inf_inst); initial begin inf_inst.v = 7; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_sequence_sexpr_unsup.py0000755000542200017500000000107115101701376024250 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert --error-limit 1000'], fails=True) test.passes() verilator-5.042/test_regress/t/t_vpi_dump.cpp0000644000542200017500000001270615101701376021746 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "svdpi.h" #include "vpi_user.h" #include extern "C" { #include } // These require the above. Comment prevents clang-format moving them #include "TestCheck.h" #include "TestSimulator.h" #include "TestVpi.h" #include #include int errors = 0; // vpiType -> list of vpiTypes to iterate over std::map> iterate_over = [] { // static decltype(iterate_over) iterate_over = [] { /* for reused lists */ // vpiInstance is the base class for module, program, interface, etc. std::vector instance_options = { vpiNet, vpiNetArray, vpiReg, vpiRegArray, }; std::vector module_options = { // vpiModule, // Aldec SEGV on mixed language // vpiModuleArray, // Aldec SEGV on mixed language // vpiIODecl, // Don't care about these vpiMemory, vpiIntegerVar, vpiRealVar, // vpiRealNet, Vpi extension vpiStructVar, vpiStructNet, vpiNamedEvent, vpiNamedEventArray, vpiParameter, // vpiVariables, // parent of vpiReg, vpiRegArray, vpiIntegerVar, etc vars // vpiSpecParam, // Don't care // vpiParamAssign, // Aldec SEGV on mixed language // vpiDefParam, // Don't care vpiPrimitive, vpiPrimitiveArray, // vpiContAssign, // Don't care // vpiProcess, // Don't care vpiModPath, vpiTchk, vpiAttribute, vpiPort, vpiInternalScope, // vpiInterface, // Aldec SEGV on mixed language // vpiInterfaceArray, // Aldec SEGV on mixed language }; // append base class vpiInstance members module_options.insert(module_options.begin(), instance_options.begin(), instance_options.end()); std::vector struct_options = { vpiNet, vpiReg, vpiRegArray, vpiMemory, vpiParameter, vpiPrimitive, vpiPrimitiveArray, vpiAttribute, vpiMember, }; return decltype(iterate_over){ {vpiModule, module_options}, {vpiInterface, instance_options}, {vpiGenScope, module_options}, {vpiStructVar, struct_options}, {vpiStructNet, struct_options}, {vpiNet, { // vpiContAssign, // Driver and load handled separately // vpiPrimTerm, // vpiPathTerm, // vpiTchkTerm, // vpiDriver, // vpiLocalDriver, // vpiLoad, // vpiLocalLoad, vpiNetBit, }}, {vpiNetArray, { vpiNet, }}, {vpiRegArray, { vpiReg, }}, {vpiMemory, { vpiMemoryWord, }}, {vpiPort, { vpiPortBit, }}, {vpiGate, { vpiPrimTerm, vpiTableEntry, vpiUdpDefn, }}, {vpiPackage, { vpiParameter, }}, }; }(); void modDump(TestVpiHandle& it, int n) { if (n > 8) { printf("going too deep\n"); return; } while (const TestVpiHandle& hndl = vpi_scan(it)) { for (int i = 0; i < n; i++) printf(" "); const int type = vpi_get(vpiType, hndl); const char* name = vpi_get_str(vpiName, hndl); const char* fullname = vpi_get_str(vpiFullName, hndl); printf("%s (%s) %s ", name, strFromVpiObjType(type), fullname); if (type == vpiParameter || type == vpiConstType) { printf(" vpiConstType=%s", strFromVpiConstType(vpi_get(vpiConstType, hndl))); } if (type == vpiModule) printf(" vpiDefName=%s", vpi_get_str(vpiDefName, hndl)); printf("\n"); if (iterate_over.find(type) == iterate_over.end()) continue; for (int type : iterate_over.at(type)) { TestVpiHandle subIt = vpi_iterate(type, hndl); if (subIt) { for (int i = 0; i < n + 1; i++) printf(" "); printf("%s:\n", strFromVpiObjType(type)); modDump(subIt, n + 1); } } } it.freed(); } PLI_INT32 start_of_sim(t_cb_data* data) { TestVpiHandle it = vpi_iterate(vpiModule, NULL); TEST_CHECK_NZ(it); modDump(it, 0); return 0; } //cver, xcelium entry void vpi_compat_bootstrap(void) { // We're able to call vpi_main() here on Verilator/Xcelium, // but Icarus complains (rightfully so) s_cb_data cb_data; s_vpi_time vpi_time; vpi_time.high = 0; vpi_time.low = 0; vpi_time.type = vpiSimTime; cb_data.reason = cbStartOfSimulation; cb_data.cb_rtn = &start_of_sim; cb_data.obj = NULL; cb_data.time = &vpi_time; cb_data.value = NULL; cb_data.index = 0; cb_data.user_data = NULL; TestVpiHandle callback_h = vpi_register_cb(&cb_data); } // Verilator (via t_vpi_main.cpp), and standard LRM entry void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0}; verilator-5.042/test_regress/t/t_property_negated.py0000755000542200017500000000077115101701376023346 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--assert']) test.execute() test.passes() verilator-5.042/test_regress/t/t_dpi_open_elem.v0000644000542200017500000001150515101701376022401 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2017 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module t; bit i_bit_p0_u1 [2:-2]; bit o_bit_p0_u1 [2:-2]; bit q_bit_p0_u1 [2:-2]; bit i_bit_p0_u2 [2:-2] [-3:3]; bit o_bit_p0_u2 [2:-2] [-3:3]; bit q_bit_p0_u2 [2:-2] [-3:3]; bit i_bit_p0_u3 [2:-2] [-3:3] [4:-4]; bit o_bit_p0_u3 [2:-2] [-3:3] [4:-4]; bit q_bit_p0_u3 [2:-2] [-3:3] [4:-4]; import "DPI-C" function void dpii_bit_elem_p0_u1 (int p, int u, input bit i [], output bit o [], output bit q []); import "DPI-C" function void dpii_bit_elem_p0_u2 (int p, int u, input bit i [] [], output bit o [] [], output bit q [] []); import "DPI-C" function void dpii_bit_elem_p0_u3 (int p, int u, input bit i [] [] [], output bit o [] [] [], output bit q [] [] []); logic i_logic_p0_u1 [2:-2]; logic o_logic_p0_u1 [2:-2]; logic q_logic_p0_u1 [2:-2]; logic i_logic_p0_u2 [2:-2] [-3:3]; logic o_logic_p0_u2 [2:-2] [-3:3]; logic q_logic_p0_u2 [2:-2] [-3:3]; logic i_logic_p0_u3 [2:-2] [-3:3] [4:-4]; logic o_logic_p0_u3 [2:-2] [-3:3] [4:-4]; logic q_logic_p0_u3 [2:-2] [-3:3] [4:-4]; import "DPI-C" function void dpii_logic_elem_p0_u1(int p, int u, input logic i [], output logic o [], output logic q []); import "DPI-C" function void dpii_logic_elem_p0_u2(int p, int u, input logic i [] [], output logic o [] [], output logic q [] []); import "DPI-C" function void dpii_logic_elem_p0_u3(int p, int u, input logic i [] [] [], output logic o [] [] [], output logic q [] [] []); import "DPI-C" function int dpii_failure(); reg [95:0] crc; initial begin crc = 96'h8a10a572_5aef0c8d_d70a4497; begin for (int a=-2; a<=2; a=a+1) begin i_bit_p0_u1[a] = crc[0]; for (int b=-3; b<=3; b=b+1) begin i_bit_p0_u2[a][b] = crc[0]; for (int c=-4; c<=4; c=c+1) begin i_bit_p0_u3[a][b][c] = crc[0]; crc = {crc[94:0], crc[95]^crc[2]^crc[0]}; end end end dpii_bit_elem_p0_u1(0, 1, i_bit_p0_u1, o_bit_p0_u1, q_bit_p0_u1); dpii_bit_elem_p0_u2(0, 2, i_bit_p0_u2, o_bit_p0_u2, q_bit_p0_u2); dpii_bit_elem_p0_u3(0, 3, i_bit_p0_u3, o_bit_p0_u3, q_bit_p0_u3); for (int a=-2; a<=2; a=a+1) begin `checkh(o_bit_p0_u1[a], ~i_bit_p0_u1[a]); `checkh(q_bit_p0_u1[a], ~i_bit_p0_u1[a]); for (int b=-3; b<=3; b=b+1) begin `checkh(o_bit_p0_u2[a][b], ~i_bit_p0_u2[a][b]); `checkh(q_bit_p0_u2[a][b], ~i_bit_p0_u2[a][b]); for (int c=-4; c<=4; c=c+1) begin `checkh(o_bit_p0_u3[a][b][c], ~i_bit_p0_u3[a][b][c]); `checkh(q_bit_p0_u3[a][b][c], ~i_bit_p0_u3[a][b][c]); end end end end begin for (int a=-2; a<=2; a=a+1) begin i_logic_p0_u1[a] = crc[0]; for (int b=-3; b<=3; b=b+1) begin i_logic_p0_u2[a][b] = crc[0]; for (int c=-4; c<=4; c=c+1) begin i_logic_p0_u3[a][b][c] = crc[0]; crc = {crc[94:0], crc[95]^crc[2]^crc[0]}; end end end dpii_logic_elem_p0_u1(0, 1, i_logic_p0_u1, o_logic_p0_u1, q_logic_p0_u1); dpii_logic_elem_p0_u2(0, 2, i_logic_p0_u2, o_logic_p0_u2, q_logic_p0_u2); dpii_logic_elem_p0_u3(0, 3, i_logic_p0_u3, o_logic_p0_u3, q_logic_p0_u3); for (int a=-2; a<=2; a=a+1) begin `checkh(o_logic_p0_u1[a], ~i_logic_p0_u1[a]); `checkh(q_logic_p0_u1[a], ~i_logic_p0_u1[a]); for (int b=-3; b<=3; b=b+1) begin `checkh(o_logic_p0_u2[a][b], ~i_logic_p0_u2[a][b]); `checkh(q_logic_p0_u2[a][b], ~i_logic_p0_u2[a][b]); for (int c=-4; c<=4; c=c+1) begin `checkh(o_logic_p0_u3[a][b][c], ~i_logic_p0_u3[a][b][c]); `checkh(q_logic_p0_u3[a][b][c], ~i_logic_p0_u3[a][b][c]); end end end end if (dpii_failure()!=0) begin $write("%%Error: Failure in DPI tests\n"); $stop; end else begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_func_call_order.py0000755000542200017500000000073415101701376023113 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_super_bad3.v0000644000542200017500000000050615101701376023015 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // class Cls; task t; i.super.i = 1; // <--- BAD: cannot dot a reference to get super endtask endclass verilator-5.042/test_regress/t/t_param_local.v0000644000542200017500000000105715101701376022055 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs a, y ); input [1:0] a; output [3:0] y; Test #(.C(2)) test (.*); endmodule module Test #(C = 3, localparam O = 1 << C) (input [C-1:0] a, output reg [O-1:0] y); initial begin if (O != 4) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_flag_libcreate_bad.py0000755000542200017500000000114315101701376023516 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = 't/t_EXAMPLE.v' # Anything test.lint(verilator_flags2=["--lib-create bad/name"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_assert_elab_bad.py0000755000542200017500000000150515101701376023061 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.top_filename = "t/t_assert_elab.v" test.unlink_ok(test.obj_dir + "/t_assert_elab_bad.log") test.compile(v_flags2=[ '+define+FAILING_ASSERTIONS', ('--assert' if test.vlt_all else ('+assert' if test.nc else '')) ], fails=True) test.file_grep(test.compile_log_filename, r'%Warning-USERFATAL: "Parameter 5 is invalid...string and constant both work"') test.passes() verilator-5.042/test_regress/t/t_tri_inz.v0000644000542200017500000000066515101701376021265 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module top (input d, output ext0, output ext1, output extx, output extz); assign ext0 = (d === 1'b0); assign ext1 = (d === 1'b1); assign extx = (d === 1'bx); assign extz = (d === 1'bz); endmodule verilator-5.042/test_regress/t/t_concat_impure.py0000755000542200017500000000073415101701376022622 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_concat_string.py0000755000542200017500000000075615101701376022633 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.timeout(15) test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_wired_net_test.v0000755000542200017500000000427215101701376022627 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkb(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='b%x exp='b%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t( clk /*AUTOARG*/); input clk; wor [3:0] ptrior1; trior [3:0] ptrior2; wand [3:0] ptriand1; triand [3:0] ptriand2; wire [3:0] z1; wire [3:0] z2; wire [3:0] tri_z1; wire [3:0] tri_z2; logic [3:0] x; logic [3:0] y; logic [3:0] tri_x; logic [3:0] tri_y; logic [3:0] tri_x_dat; logic [3:0] tri_y_dat; logic [3:0] tri_x_en; logic [3:0] tri_y_en; assign ptrior1 = x & y; assign ptrior1 = x + y; assign ptrior2 = tri_x & tri_y; assign ptrior2 = tri_x + tri_y; assign ptriand1 = x & y; assign ptriand1 = x + y; assign ptriand2 = tri_x & tri_y; assign ptriand2 = tri_x + tri_y; assign z1 = (x & y) | (x + y); assign z2 = (x & y) & (x + y); assign tri_z1 = (tri_x & tri_y) | (tri_x + tri_y); assign tri_z2 = (tri_x & tri_y) & (tri_x + tri_y); integer cyc = 0; integer xz_index = 0; integer xz_num = 0; integer i; assign tri_x[0] = tri_x_en[0] ? tri_x_dat[0] : 1'bz; assign tri_x[1] = tri_x_en[1] ? tri_x_dat[1] : 1'bz; assign tri_x[2] = tri_x_en[2] ? tri_x_dat[2] : 1'bz; assign tri_x[3] = tri_x_en[3] ? tri_x_dat[3] : 1'bz; assign tri_y[0] = tri_y_en[0] ? tri_y_dat[0] : 1'bz; assign tri_y[1] = tri_y_en[1] ? tri_y_dat[1] : 1'bz; assign tri_y[2] = tri_y_en[2] ? tri_y_dat[2] : 1'bz; assign tri_y[3] = tri_y_en[3] ? tri_y_dat[3] : 1'bz; always @ (posedge clk) begin cyc <= cyc + 1; x = {$random}[3:0]; y = {$random}[3:0]; tri_x_dat = {$random}[3:0]; tri_y_dat = {$random}[3:0]; tri_x_en = {$random}[3:0]; tri_y_en = {$random}[3:0]; `checkb(ptrior1, z1); `checkb(ptrior2, tri_z1); `checkb(ptriand1, z2); `checkb(ptriand2, tri_z2); if (cyc == 20) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_json_only_output.py0000755000542200017500000000245115101701376023422 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') out_filename = test.obj_dir + "/renamed-" + test.name + ".tree.json" meta_filename = test.obj_dir + "/renamed-" + test.name + ".tree.meta.json" test.compile(verilator_flags2=[ "--no-std", "--json-only", "--json-only-output", out_filename, "--json-only-meta-output", meta_filename, '--no-json-edit-nums' ], verilator_make_gmake=False, make_top_shell=False, make_main=False) test.files_identical(out_filename, test.golden_filename) for filename in glob.glob(test.obj_dir + "/*"): if (re.search(r'\.log', filename) # Made by driver.py, not Verilator sources or re.search(r'\.status', filename) # Made by driver.py, not Verilator sources or re.search(r'renamed-', filename)): # Requested output continue test.error("%Error: Created '" + filename + "', but --json-only shouldn't create files") test.passes() verilator-5.042/test_regress/t/t_assert_enabled_off.py0000755000542200017500000000107615101701376023577 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_assert_on.v" test.compile(verilator_flags2=["--assert"]) test.execute(all_run_flags=["+verilator+noassert"]) test.passes() verilator-5.042/test_regress/t/t_unpacked_str_init2.py0000755000542200017500000000100015101701376023544 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_array_index_side.v0000644000542200017500000000236715101701376023121 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); class Cls; int m_index; function automatic int get_index(); int rtn; rtn = m_index; ++m_index; `ifdef VERILATOR return $c(rtn); // Avoid optimizations `else return rtn; `endif endfunction endclass module t; Cls cls; int array[10]; initial begin cls = new; // Common UVM construct 'id_cnt[get_id()]++;' // Properly avoid/handle SIDEEFF warnings cls.m_index = 5; array[5] = 50; array[6] = 60; array[7] = 70; array[8] = 80; array[cls.get_index()]++; `checkd(array[5], 51); array[cls.get_index()]++; `checkd(array[6], 61); ++array[cls.get_index()]; `checkd(array[7], 71); ++array[cls.get_index()]; `checkd(array[8], 81); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_var_dotted2_inl0.py0000755000542200017500000000104515101701376023125 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_var_dotted2.v" test.compile(v_flags2=['+define+NOUSE_INLINE']) test.execute() test.passes() verilator-5.042/test_regress/t/t_math_cond_huge.v0000644000542200017500000007103515101701376022552 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [7:0] sel = crc[7:0]; wire [255+3:0] in = {crc[2:0],crc,crc,crc,crc}; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [3:0] out; // From test of Test.v // End of automatics /* Test AUTO_TEMPLATE ( .i\([0-9]+\) (in[\1 +:4]), ); */ Test test (/*AUTOINST*/ // Outputs .out (out[3:0]), // Inputs .sel (sel[7:0]), .i0 (in[0 +:4]), // Templated .i1 (in[1 +:4]), // Templated .i2 (in[2 +:4]), // Templated .i3 (in[3 +:4]), // Templated .i4 (in[4 +:4]), // Templated .i5 (in[5 +:4]), // Templated .i6 (in[6 +:4]), // Templated .i7 (in[7 +:4]), // Templated .i8 (in[8 +:4]), // Templated .i9 (in[9 +:4]), // Templated .i10 (in[10 +:4]), // Templated .i11 (in[11 +:4]), // Templated .i12 (in[12 +:4]), // Templated .i13 (in[13 +:4]), // Templated .i14 (in[14 +:4]), // Templated .i15 (in[15 +:4]), // Templated .i16 (in[16 +:4]), // Templated .i17 (in[17 +:4]), // Templated .i18 (in[18 +:4]), // Templated .i19 (in[19 +:4]), // Templated .i20 (in[20 +:4]), // Templated .i21 (in[21 +:4]), // Templated .i22 (in[22 +:4]), // Templated .i23 (in[23 +:4]), // Templated .i24 (in[24 +:4]), // Templated .i25 (in[25 +:4]), // Templated .i26 (in[26 +:4]), // Templated .i27 (in[27 +:4]), // Templated .i28 (in[28 +:4]), // Templated .i29 (in[29 +:4]), // Templated .i30 (in[30 +:4]), // Templated .i31 (in[31 +:4]), // Templated .i32 (in[32 +:4]), // Templated .i33 (in[33 +:4]), // Templated .i34 (in[34 +:4]), // Templated .i35 (in[35 +:4]), // Templated .i36 (in[36 +:4]), // Templated .i37 (in[37 +:4]), // Templated .i38 (in[38 +:4]), // Templated .i39 (in[39 +:4]), // Templated .i40 (in[40 +:4]), // Templated .i41 (in[41 +:4]), // Templated .i42 (in[42 +:4]), // Templated .i43 (in[43 +:4]), // Templated .i44 (in[44 +:4]), // Templated .i45 (in[45 +:4]), // Templated .i46 (in[46 +:4]), // Templated .i47 (in[47 +:4]), // Templated .i48 (in[48 +:4]), // Templated .i49 (in[49 +:4]), // Templated .i50 (in[50 +:4]), // Templated .i51 (in[51 +:4]), // Templated .i52 (in[52 +:4]), // Templated .i53 (in[53 +:4]), // Templated .i54 (in[54 +:4]), // Templated .i55 (in[55 +:4]), // Templated .i56 (in[56 +:4]), // Templated .i57 (in[57 +:4]), // Templated .i58 (in[58 +:4]), // Templated .i59 (in[59 +:4]), // Templated .i60 (in[60 +:4]), // Templated .i61 (in[61 +:4]), // Templated .i62 (in[62 +:4]), // Templated .i63 (in[63 +:4]), // Templated .i64 (in[64 +:4]), // Templated .i65 (in[65 +:4]), // Templated .i66 (in[66 +:4]), // Templated .i67 (in[67 +:4]), // Templated .i68 (in[68 +:4]), // Templated .i69 (in[69 +:4]), // Templated .i70 (in[70 +:4]), // Templated .i71 (in[71 +:4]), // Templated .i72 (in[72 +:4]), // Templated .i73 (in[73 +:4]), // Templated .i74 (in[74 +:4]), // Templated .i75 (in[75 +:4]), // Templated .i76 (in[76 +:4]), // Templated .i77 (in[77 +:4]), // Templated .i78 (in[78 +:4]), // Templated .i79 (in[79 +:4]), // Templated .i80 (in[80 +:4]), // Templated .i81 (in[81 +:4]), // Templated .i82 (in[82 +:4]), // Templated .i83 (in[83 +:4]), // Templated .i84 (in[84 +:4]), // Templated .i85 (in[85 +:4]), // Templated .i86 (in[86 +:4]), // Templated .i87 (in[87 +:4]), // Templated .i88 (in[88 +:4]), // Templated .i89 (in[89 +:4]), // Templated .i90 (in[90 +:4]), // Templated .i91 (in[91 +:4]), // Templated .i92 (in[92 +:4]), // Templated .i93 (in[93 +:4]), // Templated .i94 (in[94 +:4]), // Templated .i95 (in[95 +:4]), // Templated .i96 (in[96 +:4]), // Templated .i97 (in[97 +:4]), // Templated .i98 (in[98 +:4]), // Templated .i99 (in[99 +:4]), // Templated .i100 (in[100 +:4]), // Templated .i101 (in[101 +:4]), // Templated .i102 (in[102 +:4]), // Templated .i103 (in[103 +:4]), // Templated .i104 (in[104 +:4]), // Templated .i105 (in[105 +:4]), // Templated .i106 (in[106 +:4]), // Templated .i107 (in[107 +:4]), // Templated .i108 (in[108 +:4]), // Templated .i109 (in[109 +:4]), // Templated .i110 (in[110 +:4]), // Templated .i111 (in[111 +:4]), // Templated .i112 (in[112 +:4]), // Templated .i113 (in[113 +:4]), // Templated .i114 (in[114 +:4]), // Templated .i115 (in[115 +:4]), // Templated .i116 (in[116 +:4]), // Templated .i117 (in[117 +:4]), // Templated .i118 (in[118 +:4]), // Templated .i119 (in[119 +:4]), // Templated .i120 (in[120 +:4]), // Templated .i121 (in[121 +:4]), // Templated .i122 (in[122 +:4]), // Templated .i123 (in[123 +:4]), // Templated .i124 (in[124 +:4]), // Templated .i125 (in[125 +:4]), // Templated .i126 (in[126 +:4]), // Templated .i127 (in[127 +:4]), // Templated .i128 (in[128 +:4]), // Templated .i129 (in[129 +:4]), // Templated .i130 (in[130 +:4]), // Templated .i131 (in[131 +:4]), // Templated .i132 (in[132 +:4]), // Templated .i133 (in[133 +:4]), // Templated .i134 (in[134 +:4]), // Templated .i135 (in[135 +:4]), // Templated .i136 (in[136 +:4]), // Templated .i137 (in[137 +:4]), // Templated .i138 (in[138 +:4]), // Templated .i139 (in[139 +:4]), // Templated .i140 (in[140 +:4]), // Templated .i141 (in[141 +:4]), // Templated .i142 (in[142 +:4]), // Templated .i143 (in[143 +:4]), // Templated .i144 (in[144 +:4]), // Templated .i145 (in[145 +:4]), // Templated .i146 (in[146 +:4]), // Templated .i147 (in[147 +:4]), // Templated .i148 (in[148 +:4]), // Templated .i149 (in[149 +:4]), // Templated .i150 (in[150 +:4]), // Templated .i151 (in[151 +:4]), // Templated .i152 (in[152 +:4]), // Templated .i153 (in[153 +:4]), // Templated .i154 (in[154 +:4]), // Templated .i155 (in[155 +:4]), // Templated .i156 (in[156 +:4]), // Templated .i157 (in[157 +:4]), // Templated .i158 (in[158 +:4]), // Templated .i159 (in[159 +:4]), // Templated .i160 (in[160 +:4]), // Templated .i161 (in[161 +:4]), // Templated .i162 (in[162 +:4]), // Templated .i163 (in[163 +:4]), // Templated .i164 (in[164 +:4]), // Templated .i165 (in[165 +:4]), // Templated .i166 (in[166 +:4]), // Templated .i167 (in[167 +:4]), // Templated .i168 (in[168 +:4]), // Templated .i169 (in[169 +:4]), // Templated .i170 (in[170 +:4]), // Templated .i171 (in[171 +:4]), // Templated .i172 (in[172 +:4]), // Templated .i173 (in[173 +:4]), // Templated .i174 (in[174 +:4]), // Templated .i175 (in[175 +:4]), // Templated .i176 (in[176 +:4]), // Templated .i177 (in[177 +:4]), // Templated .i178 (in[178 +:4]), // Templated .i179 (in[179 +:4]), // Templated .i180 (in[180 +:4]), // Templated .i181 (in[181 +:4]), // Templated .i182 (in[182 +:4]), // Templated .i183 (in[183 +:4]), // Templated .i184 (in[184 +:4]), // Templated .i185 (in[185 +:4]), // Templated .i186 (in[186 +:4]), // Templated .i187 (in[187 +:4]), // Templated .i188 (in[188 +:4]), // Templated .i189 (in[189 +:4]), // Templated .i190 (in[190 +:4]), // Templated .i191 (in[191 +:4]), // Templated .i192 (in[192 +:4]), // Templated .i193 (in[193 +:4]), // Templated .i194 (in[194 +:4]), // Templated .i195 (in[195 +:4]), // Templated .i196 (in[196 +:4]), // Templated .i197 (in[197 +:4]), // Templated .i198 (in[198 +:4]), // Templated .i199 (in[199 +:4]), // Templated .i200 (in[200 +:4]), // Templated .i201 (in[201 +:4]), // Templated .i202 (in[202 +:4]), // Templated .i203 (in[203 +:4]), // Templated .i204 (in[204 +:4]), // Templated .i205 (in[205 +:4]), // Templated .i206 (in[206 +:4]), // Templated .i207 (in[207 +:4]), // Templated .i208 (in[208 +:4]), // Templated .i209 (in[209 +:4]), // Templated .i210 (in[210 +:4]), // Templated .i211 (in[211 +:4]), // Templated .i212 (in[212 +:4]), // Templated .i213 (in[213 +:4]), // Templated .i214 (in[214 +:4]), // Templated .i215 (in[215 +:4]), // Templated .i216 (in[216 +:4]), // Templated .i217 (in[217 +:4]), // Templated .i218 (in[218 +:4]), // Templated .i219 (in[219 +:4]), // Templated .i220 (in[220 +:4]), // Templated .i221 (in[221 +:4]), // Templated .i222 (in[222 +:4]), // Templated .i223 (in[223 +:4]), // Templated .i224 (in[224 +:4]), // Templated .i225 (in[225 +:4]), // Templated .i226 (in[226 +:4]), // Templated .i227 (in[227 +:4]), // Templated .i228 (in[228 +:4]), // Templated .i229 (in[229 +:4]), // Templated .i230 (in[230 +:4]), // Templated .i231 (in[231 +:4]), // Templated .i232 (in[232 +:4]), // Templated .i233 (in[233 +:4]), // Templated .i234 (in[234 +:4]), // Templated .i235 (in[235 +:4]), // Templated .i236 (in[236 +:4]), // Templated .i237 (in[237 +:4]), // Templated .i238 (in[238 +:4]), // Templated .i239 (in[239 +:4]), // Templated .i240 (in[240 +:4]), // Templated .i241 (in[241 +:4]), // Templated .i242 (in[242 +:4]), // Templated .i243 (in[243 +:4]), // Templated .i244 (in[244 +:4]), // Templated .i245 (in[245 +:4]), // Templated .i246 (in[246 +:4]), // Templated .i247 (in[247 +:4]), // Templated .i248 (in[248 +:4]), // Templated .i249 (in[249 +:4]), // Templated .i250 (in[250 +:4]), // Templated .i251 (in[251 +:4]), // Templated .i252 (in[252 +:4]), // Templated .i253 (in[253 +:4]), // Templated .i254 (in[254 +:4]), // Templated .i255 (in[255 +:4])); // Templated // Aggregate outputs into a single result vector wire [63:0] result = {60'h0, out}; // What checksum will we end up with `define EXPECTED_SUM 64'h36f3051d15caf07a // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test ( output wire [3:0] out, input [7:0] sel, // verilog_format: off input [3:0] i0, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15, i16, i17, i18, i19, i20, i21, i22, i23, i24, i25, i26, i27, i28, i29, i30, i31, i32, i33, i34, i35, i36, i37, i38, i39, i40, i41, i42, i43, i44, i45, i46, i47, i48, i49, i50, i51, i52, i53, i54, i55, i56, i57, i58, i59, i60, i61, i62, i63, i64, i65, i66, i67, i68, i69, i70, i71, i72, i73, i74, i75, i76, i77, i78, i79, i80, i81, i82, i83, i84, i85, i86, i87, i88, i89, i90, i91, i92, i93, i94, i95, i96, i97, i98, i99, i100, i101, i102, i103, i104, i105, i106, i107, i108, i109, i110, i111, i112, i113, i114, i115, i116, i117, i118, i119, i120, i121, i122, i123, i124, i125, i126, i127, i128, i129, i130, i131, i132, i133, i134, i135, i136, i137, i138, i139, i140, i141, i142, i143, i144, i145, i146, i147, i148, i149, i150, i151, i152, i153, i154, i155, i156, i157, i158, i159, i160, i161, i162, i163, i164, i165, i166, i167, i168, i169, i170, i171, i172, i173, i174, i175, i176, i177, i178, i179, i180, i181, i182, i183, i184, i185, i186, i187, i188, i189, i190, i191, i192, i193, i194, i195, i196, i197, i198, i199, i200, i201, i202, i203, i204, i205, i206, i207, i208, i209, i210, i211, i212, i213, i214, i215, i216, i217, i218, i219, i220, i221, i222, i223, i224, i225, i226, i227, i228, i229, i230, i231, i232, i233, i234, i235, i236, i237, i238, i239, i240, i241, i242, i243, i244, i245, i246, i247, i248, i249, i250, i251, i252, i253, i254, i255 // verilog_format: on ); assign out = (sel==8'h00) ? i0 : (sel==8'h01) ? i1 : (sel==8'h02) ? i2 : (sel==8'h03) ? i3 : (sel==8'h04) ? i4 : (sel==8'h05) ? i5 : (sel==8'h06) ? i6 : (sel==8'h07) ? i7 : (sel==8'h08) ? i8 : (sel==8'h09) ? i9 : (sel==8'h0a) ? i10 : (sel==8'h0b) ? i11 : (sel==8'h0c) ? i12 : (sel==8'h0d) ? i13 : (sel==8'h0e) ? i14 : (sel==8'h0f) ? i15 : (sel==8'h10) ? i16 : (sel==8'h11) ? i17 : (sel==8'h12) ? i18 : (sel==8'h13) ? i19 : (sel==8'h14) ? i20 : (sel==8'h15) ? i21 : (sel==8'h16) ? i22 : (sel==8'h17) ? i23 : (sel==8'h18) ? i24 : (sel==8'h19) ? i25 : (sel==8'h1a) ? i26 : (sel==8'h1b) ? i27 : (sel==8'h1c) ? i28 : (sel==8'h1d) ? i29 : (sel==8'h1e) ? i30 : (sel==8'h1f) ? i31 : (sel==8'h20) ? i32 : (sel==8'h21) ? i33 : (sel==8'h22) ? i34 : (sel==8'h23) ? i35 : (sel==8'h24) ? i36 : (sel==8'h25) ? i37 : (sel==8'h26) ? i38 : (sel==8'h27) ? i39 : (sel==8'h28) ? i40 : (sel==8'h29) ? i41 : (sel==8'h2a) ? i42 : (sel==8'h2b) ? i43 : (sel==8'h2c) ? i44 : (sel==8'h2d) ? i45 : (sel==8'h2e) ? i46 : (sel==8'h2f) ? i47 : (sel==8'h30) ? i48 : (sel==8'h31) ? i49 : (sel==8'h32) ? i50 : (sel==8'h33) ? i51 : (sel==8'h34) ? i52 : (sel==8'h35) ? i53 : (sel==8'h36) ? i54 : (sel==8'h37) ? i55 : (sel==8'h38) ? i56 : (sel==8'h39) ? i57 : (sel==8'h3a) ? i58 : (sel==8'h3b) ? i59 : (sel==8'h3c) ? i60 : (sel==8'h3d) ? i61 : (sel==8'h3e) ? i62 : (sel==8'h3f) ? i63 : (sel==8'h40) ? i64 : (sel==8'h41) ? i65 : (sel==8'h42) ? i66 : (sel==8'h43) ? i67 : (sel==8'h44) ? i68 : (sel==8'h45) ? i69 : (sel==8'h46) ? i70 : (sel==8'h47) ? i71 : (sel==8'h48) ? i72 : (sel==8'h49) ? i73 : (sel==8'h4a) ? i74 : (sel==8'h4b) ? i75 : (sel==8'h4c) ? i76 : (sel==8'h4d) ? i77 : (sel==8'h4e) ? i78 : (sel==8'h4f) ? i79 : (sel==8'h50) ? i80 : (sel==8'h51) ? i81 : (sel==8'h52) ? i82 : (sel==8'h53) ? i83 : (sel==8'h54) ? i84 : (sel==8'h55) ? i85 : (sel==8'h56) ? i86 : (sel==8'h57) ? i87 : (sel==8'h58) ? i88 : (sel==8'h59) ? i89 : (sel==8'h5a) ? i90 : (sel==8'h5b) ? i91 : (sel==8'h5c) ? i92 : (sel==8'h5d) ? i93 : (sel==8'h5e) ? i94 : (sel==8'h5f) ? i95 : (sel==8'h60) ? i96 : (sel==8'h61) ? i97 : (sel==8'h62) ? i98 : (sel==8'h63) ? i99 : (sel==8'h64) ? i100 : (sel==8'h65) ? i101 : (sel==8'h66) ? i102 : (sel==8'h67) ? i103 : (sel==8'h68) ? i104 : (sel==8'h69) ? i105 : (sel==8'h6a) ? i106 : (sel==8'h6b) ? i107 : (sel==8'h6c) ? i108 : (sel==8'h6d) ? i109 : (sel==8'h6e) ? i110 : (sel==8'h6f) ? i111 : (sel==8'h70) ? i112 : (sel==8'h71) ? i113 : (sel==8'h72) ? i114 : (sel==8'h73) ? i115 : (sel==8'h74) ? i116 : (sel==8'h75) ? i117 : (sel==8'h76) ? i118 : (sel==8'h77) ? i119 : (sel==8'h78) ? i120 : (sel==8'h79) ? i121 : (sel==8'h7a) ? i122 : (sel==8'h7b) ? i123 : (sel==8'h7c) ? i124 : (sel==8'h7d) ? i125 : (sel==8'h7e) ? i126 : (sel==8'h7f) ? i127 : (sel==8'h80) ? i128 : (sel==8'h81) ? i129 : (sel==8'h82) ? i130 : (sel==8'h83) ? i131 : (sel==8'h84) ? i132 : (sel==8'h85) ? i133 : (sel==8'h86) ? i134 : (sel==8'h87) ? i135 : (sel==8'h88) ? i136 : (sel==8'h89) ? i137 : (sel==8'h8a) ? i138 : (sel==8'h8b) ? i139 : (sel==8'h8c) ? i140 : (sel==8'h8d) ? i141 : (sel==8'h8e) ? i142 : (sel==8'h8f) ? i143 : (sel==8'h90) ? i144 : (sel==8'h91) ? i145 : (sel==8'h92) ? i146 : (sel==8'h93) ? i147 : (sel==8'h94) ? i148 : (sel==8'h95) ? i149 : (sel==8'h96) ? i150 : (sel==8'h98) ? i151 : (sel==8'h99) ? i152 : (sel==8'h9a) ? i153 : (sel==8'h9b) ? i154 : (sel==8'h9c) ? i155 : (sel==8'h9d) ? i156 : (sel==8'h9e) ? i157 : (sel==8'h9f) ? i158 : (sel==8'ha0) ? i159 : (sel==8'ha1) ? i160 : (sel==8'ha2) ? i161 : (sel==8'ha3) ? i162 : (sel==8'ha4) ? i163 : (sel==8'ha5) ? i164 : (sel==8'ha6) ? i165 : (sel==8'ha7) ? i166 : (sel==8'ha8) ? i167 : (sel==8'ha9) ? i168 : (sel==8'haa) ? i169 : (sel==8'hab) ? i170 : (sel==8'hac) ? i171 : (sel==8'had) ? i172 : (sel==8'hae) ? i173 : (sel==8'haf) ? i174 : (sel==8'hb0) ? i175 : (sel==8'hb1) ? i176 : (sel==8'hb2) ? i177 : (sel==8'hb3) ? i178 : (sel==8'hb4) ? i179 : (sel==8'hb5) ? i180 : (sel==8'hb6) ? i181 : (sel==8'hb7) ? i182 : (sel==8'hb8) ? i183 : (sel==8'hb9) ? i184 : (sel==8'hba) ? i185 : (sel==8'hbb) ? i186 : (sel==8'hbc) ? i187 : (sel==8'hbd) ? i188 : (sel==8'hbe) ? i189 : (sel==8'hbf) ? i190 : (sel==8'hc0) ? i191 : (sel==8'hc1) ? i192 : (sel==8'hc2) ? i193 : (sel==8'hc3) ? i194 : (sel==8'hc4) ? i195 : (sel==8'hc5) ? i196 : (sel==8'hc6) ? i197 : (sel==8'hc7) ? i198 : (sel==8'hc8) ? i199 : (sel==8'hc9) ? i200 : (sel==8'hca) ? i201 : (sel==8'hcb) ? i202 : (sel==8'hcc) ? i203 : (sel==8'hcd) ? i204 : (sel==8'hce) ? i205 : (sel==8'hcf) ? i206 : (sel==8'hd0) ? i207 : (sel==8'hd1) ? i208 : (sel==8'hd2) ? i209 : (sel==8'hd3) ? i210 : (sel==8'hd4) ? i211 : (sel==8'hd5) ? i212 : (sel==8'hd6) ? i213 : (sel==8'hd7) ? i214 : (sel==8'hd8) ? i215 : (sel==8'hd9) ? i216 : (sel==8'hda) ? i217 : (sel==8'hdb) ? i218 : (sel==8'hdc) ? i219 : (sel==8'hdd) ? i220 : (sel==8'hde) ? i221 : (sel==8'hdf) ? i222 : (sel==8'he0) ? i223 : (sel==8'he1) ? i224 : (sel==8'he2) ? i225 : (sel==8'he3) ? i226 : (sel==8'he4) ? i227 : (sel==8'he5) ? i228 : (sel==8'he6) ? i229 : (sel==8'he7) ? i230 : (sel==8'he8) ? i231 : (sel==8'he9) ? i232 : (sel==8'hea) ? i233 : (sel==8'heb) ? i234 : (sel==8'hec) ? i235 : (sel==8'hed) ? i236 : (sel==8'hee) ? i237 : (sel==8'hef) ? i238 : (sel==8'hf0) ? i239 : (sel==8'hf1) ? i240 : (sel==8'hf2) ? i241 : (sel==8'hf3) ? i242 : (sel==8'hf4) ? i243 : (sel==8'hf5) ? i244 : (sel==8'hf6) ? i245 : (sel==8'hf7) ? i246 : (sel==8'hf8) ? i247 : (sel==8'hf9) ? i248 : (sel==8'hfa) ? i249 : (sel==8'hfb) ? i250 : (sel==8'hfc) ? i251 : (sel==8'hfd) ? i252 : (sel==8'hfe) ? i253 : (sel==8'hff) ? i254 : i255; endmodule verilator-5.042/test_regress/t/t_vlcov_rank.out0000644000542200017500000000041415101701376022305 0ustar mahmoudyfreeshellTests: Covered, Rank, RankPts, Filename 2, 2, 1, "t/t_vlcov_data_a.dat" 3, 1, 3, "t/t_vlcov_data_b.dat" 1, 3, 1, "t/t_vlcov_data_c.dat" 1, 0, 0, "t/t_vlcov_data_d.dat" verilator-5.042/test_regress/t/t_func_const_struct_bad.py0000755000542200017500000000076615101701376024352 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface_hidden.py0000755000542200017500000000073415101701376023245 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_param_enum.v0000644000542200017500000000111315101701376023105 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 typedef enum bit {A = 0, B = 1} enum_t; class Converter #(type T); function int toInt(T t); return int'(t); endfunction endclass module t; initial begin Converter#(enum_t) conv1 = new; Converter#(bit) conv2 = new; if (conv1.toInt(A) != 0) $stop; if (conv2.toInt(1) != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_dpi_type_bad.out0000644000542200017500000000045115101701376022565 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_dpi_type_bad.v:11:4: Unsupported DPI type 'DPI-BAD': Use 'DPI-C' (IEEE 1800-2023 35.5.4) 11 | import "DPI-BAD" task dpix_twice; | ^~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_enum_recurse_bad.v0000644000542200017500000000034615101701376023105 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 enum {u=u} e_t; verilator-5.042/test_regress/t/t_initialstatic_circ.v0000644000542200017500000000115315101701376023441 0ustar mahmoudyfreeshell// DESCRIPTION::Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 package pkg; int unsigned id = 0; function int unsigned func(); int unsigned local_id; local_id = id + 1; id = local_id; return local_id; endfunction : func endpackage module t(/*AUTOARG*/ // Inputs clk ); input clk; import pkg::*; int unsigned func_id = func(); always @ (posedge clk) begin $display(id); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_var_static_param.v0000644000542200017500000000175715101701376023131 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module t; sub #(.P(1)) suba (); sub #(.P(10)) subb (); int v; initial begin v = suba.f_no_st(); `checkh(v, 3); v = suba.f_no_st(); `checkh(v, 4); v = subb.f_no_st(); `checkh(v, 'hc); v = subb.f_no_st(); `checkh(v, 'h16); v = suba.f_no_st(); `checkh(v, 5); $write("*-* All Finished *-*\n"); $finish; end endmodule module sub; parameter P = 1; // verilator lint_off IMPLICITSTATIC function int f_no_st (); // This static is unique within each parameterized module static int st = 2; st += P; return st; endfunction endmodule verilator-5.042/test_regress/t/t_interface2.v0000644000542200017500000000562315101701376021630 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=1; counter_io c1_data(); counter_io c2_data(); //counter_io c3_data; // IEEE illegal, and VCS doesn't allow non-() as it does with cells counter_io c3_data(); counter_ansi c1 (.clkm(clk), .c_data(c1_data), .i_value(4'h1)); counter_ansi c2 (.clkm(clk), .c_data(c2_data), .i_value(4'h2)); `ifdef VERILATOR counter_ansi `else counter_nansi `endif /**/ c3 (.clkm(clk), .c_data(c3_data), .i_value(4'h3)); initial begin c1_data.value = 4'h4; c2_data.value = 4'h5; c3_data.value = 4'h6; end always @ (posedge clk) begin cyc <= cyc + 1; if (cyc<2) begin c1_data.reset <= 1; c2_data.reset <= 1; c3_data.reset <= 1; end if (cyc==2) begin c1_data.reset <= 0; c2_data.reset <= 0; c3_data.reset <= 0; end if (cyc==3) begin if (c1_data.get_lcl() != 12345) $stop; end if (cyc==20) begin $write("[%0t] c1 cyc%0d: c1 %0x %0x c2 %0x %0x c3 %0x %0x\n", $time, cyc, c1_data.value, c1_data.reset, c2_data.value, c2_data.reset, c3_data.value, c3_data.reset); if (c1_data.value != 2) $stop; if (c2_data.value != 3) $stop; if (c3_data.value != 4) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule interface counter_io; logic [3:0] value; logic reset; integer lcl; task set_lcl (input integer a); lcl=a; endtask function integer get_lcl (); return lcl; endfunction endinterface interface ifunused; logic unused; endinterface module counter_ansi ( input clkm, counter_io c_data, input logic [3:0] i_value ); initial begin c_data.set_lcl(12345); end always @ (posedge clkm) begin c_data.value <= c_data.reset ? i_value : c_data.value + 1; end endmodule : counter_ansi `ifndef VERILATOR // non-ansi modports not seen in the wild yet. Verilog-Perl needs parser improvement too. module counter_nansi(clkm, c_data, i_value); input clkm; counter_io c_data; input logic [3:0] i_value; always @ (posedge clkm) begin c_data.value <= c_data.reset ? i_value : c_data.value + 1; end endmodule : counter_nansi `endif // Test uses Verilator --top-module, which means this isn't in the hierarchy // Other simulators will see it, and is illegal to have unconnected interface `ifdef VERILATOR module modunused (ifunused ifinunused); ifunused ifunused(); endmodule `endif verilator-5.042/test_regress/t/t_opt_assemble_cellarray.v0000644000542200017500000000427215101701376024320 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014 by Jie Xu. // SPDX-License-Identifier: CC0-1.0 // change these two parameters to see the speed differences `define DATA_WIDTH 8 `define REP_COUNT4 `DATA_WIDTH/4 `define REP_COUNT2 `DATA_WIDTH/2 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [3:0] count4 = 0; reg [1:0] count2 = 0; reg [`DATA_WIDTH-1:0] a = {`REP_COUNT4{4'b0000}}; reg [`DATA_WIDTH-1:0] b = {`REP_COUNT4{4'b1111}}; reg [`DATA_WIDTH-1:0] c = {`REP_COUNT4{4'b1111}}; reg [`DATA_WIDTH-1:0] d = {`REP_COUNT4{4'b1111}}; reg [`DATA_WIDTH-1:0] res1; reg [`DATA_WIDTH-1:0] res2; reg [`DATA_WIDTH-1:0] res3; reg [`DATA_WIDTH-1:0] res4; drv1 t_drv1 [`DATA_WIDTH-1:0] (.colSelA(a), .datao(res1)); drv2 t_drv2 [`DATA_WIDTH-1:0] (.colSelA(a), .colSelB(b), .datao(res2)); drv3 t_drv3 [`DATA_WIDTH-1:0] (.colSelA(a), .colSelB(b), .colSelC(c), .datao(res3)); drv4 t_drv4 [`DATA_WIDTH-1:0] (.colSelA(a), .colSelB(b), .colSelC(c), .colSelD(d), .datao(res4)); always@(posedge clk) begin count2 <= count2 + 1; count4 <= count4 + 1; a <= {`REP_COUNT4{count4}}; b <= {`REP_COUNT4{count4}}; c <= {`REP_COUNT2{count2}}; d <= {`REP_COUNT2{count2}}; if (res1 != (a)) begin $stop; end if (res2 != (a&b)) begin $stop; end if (res3 != (a&b&c)) begin $stop; end if (res4 != (a&b&c&d)) begin $stop; end if (count4 > 10) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module drv1 (input colSelA, output datao ); assign datao = colSelA; endmodule module drv2 (input colSelA, input colSelB, output datao ); assign datao = colSelB & colSelA; endmodule module drv3 (input colSelA, input colSelB, input colSelC, output datao ); assign datao = colSelB & colSelA & colSelC; endmodule module drv4 (input colSelA, input colSelB, input colSelC, input colSelD, output datao ); assign datao = colSelB & colSelA & colSelC & colSelD; endmodule verilator-5.042/test_regress/t/t_stream_trace.v0000644000542200017500000000121415101701376022247 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; integer cyc = 0; logic [2:0] cmd_ready; logic cmd_ready_unpack[3]; logic cmd_ready_o[3]; assign cmd_ready = {1'b1, clk, ~clk}; assign cmd_ready_unpack = {<<{cmd_ready}}; assign cmd_ready_o = cmd_ready_unpack; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 5) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_fork_dynscope_out.v0000644000542200017500000000076615101701376023345 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t; bit p = 0, q = 0; initial begin t1(p); t2(q); if (p != 1) $stop; if (q != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end task t1(inout p); fork p = 1; join_none endtask task t2(output q); q <= 1; endtask endmodule verilator-5.042/test_regress/t/t_protect_ids_key.py0000755000542200017500000000135715101701376023163 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_protect_ids.v" test.compile(verilator_flags2=["--protect-ids --protect-key SECRET_KEY", "t/t_protect_ids_c.cpp"]) test.execute() # Since using a named key, we can check for always identical maptest.files_identical(test.obj_dir + "/"+test.vm_prefix+"__idmap.xml", test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_flag_threads_bad2.py0000755000542200017500000000130615101701376023301 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = 't/t_EXAMPLE.v' test.run(cmd=["perl", os.environ["VERILATOR_ROOT"] + "/bin/verilator", "--threads-max-mtasks 0"], logfile=test.run_log_filename, fails=True, expect_filename=test.golden_filename, verilator_run=True) test.passes() verilator-5.042/test_regress/t/t_case_x_bad.v0000644000542200017500000000077115101701376021655 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs value ); input [3:0] value; always @ (/*AS*/value) begin casex (value) default: $stop; endcase case (value) 4'b0000: $stop; 4'b1xxx: $stop; default: $stop; endcase end endmodule verilator-5.042/test_regress/t/t_param_scope_bad.out0000644000542200017500000000077415101701376023251 0ustar mahmoudyfreeshell%Warning-CASEOVERLAP: t/t_param_scope_bad.v:28:9: Case conditions overlap 28 | 2'h2: $stop; | ^~~~ t/t_param_scope_bad.v:27:9: ... Location of overlapping condition 27 | CASEVAL: ; | ^~~~~~~ ... For warning description see https://verilator.org/warn/CASEOVERLAP?v=latest ... Use "/* verilator lint_off CASEOVERLAP */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_queue_init.py0000755000542200017500000000073415101701376022141 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_initial_inc.vh0000644000542200017500000000053115101701376022231 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define foo bar `ifdef foo `ifdef baz `else // Test file to make sure includes work; integer user_loaded_value; `endif `endif verilator-5.042/test_regress/t/t_opt_balance_cats_sc.py0000755000542200017500000000140215101701376023731 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_opt_balance_cats.v" test.compile(verilator_flags2=[ "--stats", "--build", "--gate-stmts", "10000", "--expand-limit", "128", "--sc" ]) test.file_grep(test.stats, r'Optimizations, FuncOpt concat trees balanced\s+(\d+)', 1) test.file_grep(test.stats, r'Optimizations, FuncOpt concat splits\s+(\d+)', 0) test.passes() verilator-5.042/test_regress/t/t_trace_public_func_vlt.py0000755000542200017500000000156715101701376024333 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_trace_public_func.cpp" test.top_filename = "t/t_trace_public.v" test.golden_filename = "t/t_trace_public.out" test.compile(make_top_shell=False, make_main=False, v_flags2=[ "-DPUB_FUNC --trace-vcd --exe", test.pli_filename, test.t_dir + "/t_trace_public_func.vlt" ]) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_gen_for.v0000644000542200017500000000777315101701376021235 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [7:0] crc; genvar g; wire [7:0] out_p1; wire [15:0] out_p2; wire [7:0] out_p3; wire [7:0] out_p4; paramed #(.WIDTH(8), .MODE(0)) p1 (.in(crc), .out(out_p1)); paramed #(.WIDTH(16), .MODE(1)) p2 (.in({crc,crc}), .out(out_p2)); paramed #(.WIDTH(8), .MODE(2)) p3 (.in(crc), .out(out_p3)); gencase #(.MODE(3)) p4 (.in(crc), .out(out_p4)); wire [7:0] out_ef; enflop #(.WIDTH(8)) enf (.a(crc), .q(out_ef), .oe_e1(1'b1), .clk(clk)); always @ (posedge clk) begin //$write("[%0t] cyc==%0d crc=%b %x %x %x %x %x\n", $time, cyc, crc, out_p1, out_p2, out_p3, out_p4, out_ef); cyc <= cyc + 1; crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; if (cyc==0) begin // Setup crc <= 8'hed; end else if (cyc==1) begin end else if (cyc==3) begin if (out_p1 !== 8'h2d) $stop; if (out_p2 !== 16'h2d2d) $stop; if (out_p3 !== 8'h78) $stop; if (out_p4 !== 8'h44) $stop; if (out_ef !== 8'hda) $stop; end else if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module gencase (/*AUTOARG*/ // Outputs out, // Inputs in ); parameter MODE = 0; input [7:0] in; output [7:0] out; generate // : genblk1 begin case (MODE) 2: mbuf mc [7:0] (.q(out[7:0]), .a({in[5:0],in[7:6]})); default: mbuf mc [7:0] (.q(out[7:0]), .a({in[3:0],in[3:0]})); endcase end endgenerate endmodule module paramed (/*AUTOARG*/ // Outputs out, // Inputs in ); parameter WIDTH = 1; parameter MODE = 0; input [WIDTH-1:0] in; output [WIDTH-1:0] out; generate if (MODE==0) initial $write("Mode=0\n"); // No else endgenerate `ifndef NC // for(genvar) unsupported `ifndef ATSIM // for(genvar) unsupported generate // Empty loop body, local genvar for (genvar j=0; j<3; j=j+1) begin end // Ditto to make sure j has new scope for (genvar j=0; j<5; j=j+1) begin end endgenerate `endif `endif generate endgenerate genvar i; generate if (MODE==0) begin // Flip bitorder, direct assign method for (i=0; i> 1); `signal(GRAY_REV_SEL, 3); // UNOPTFLAT assign GRAY_REV_SEL = rand_a[2:0] ^ {GRAY_REV_SEL[1:0], 1'b0}; `signal(GRAY_REV_SHIFT, 3); // UNOPTFLAT assign GRAY_REV_SHIFT = rand_a[2:0] ^ (GRAY_REV_SHIFT << 1); ////////////////////////////////////////////////////////////////////////// // Fill coverage ////////////////////////////////////////////////////////////////////////// `signal(CONCAT_RHS, 2); // UNOPTFLAT assign CONCAT_RHS[0] = rand_a[0]; assign CONCAT_RHS[1] = CONCAT_RHS[0]; `signal(CONCAT_LHS, 2); // UNOPTFLAT assign CONCAT_LHS[0] = CONCAT_LHS[1]; assign CONCAT_LHS[1] = rand_a[1]; `signal(CONCAT_MID, 3); // UNOPTFLAT assign CONCAT_MID[0] = |CONCAT_MID[2:1]; assign CONCAT_MID[2:1] = {rand_a[2], ~rand_a[2]}; `signal(SEL, 3); // UNOPTFLAT assign SEL[0] = rand_a[4]; assign SEL[1] = SEL[0]; assign SEL[2] = SEL[1]; `signal(EXTEND, 8); // UNOPTFLAT assign EXTEND[0] = rand_a[3]; assign EXTEND[3:1] = 3'(EXTEND[0]); assign EXTEND[4] = EXTEND[1]; assign EXTEND[6:5] = EXTEND[2:1]; assign EXTEND[7] = EXTEND[3]; `signal(NOT, 3); // UNOPTFLAT assign NOT = ~(rand_a[2:0] ^ 3'(NOT[2:1])); `signal(AND, 3); // UNOPTFLAT assign AND = rand_a[2:0] & 3'(AND[2:1]); `signal(OR, 3); // UNOPTFLAT assign OR = rand_a[2:0] | 3'(OR[2:1]); `signal(SHIFTR, 14); // UNOPTFLAT assign SHIFTR = { SHIFTR[6:5], // 13:12 SHIFTR[7:6], // 11:10 SHIFTR[5:4], // 9:8 SHIFTR[3:0] >> 2, // 7:4 rand_a[3:0] // 3:0 }; `signal(SHIFTR_VARIABLE, 2); // UNOPTFLAT assign SHIFTR_VARIABLE = rand_a[1:0] ^ ({1'b0, SHIFTR_VARIABLE[1]} >> rand_b[0]); `signal(SHIFTL, 14); // UNOPTFLAT assign SHIFTL = { SHIFTL[6:5], // 13:12 SHIFTL[7:6], // 11:10 SHIFTL[5:4], // 9:8 SHIFTL[3:0] << 2, // 7:4 rand_a[3:0] // 3:0 }; `signal(SHIFTL_VARIABLE, 2); // UNOPTFLAT assign SHIFTL_VARIABLE = rand_a[1:0] ^ ({SHIFTL_VARIABLE[0], 1'b0} << rand_b[0]); `signal(VAR_A, 2); // UNOPTFLAT wire logic [1:0] VAR_B; assign VAR_A = {rand_a[0], VAR_B[0]}; assign VAR_B = (VAR_A >> 1) ^ 2'(VAR_B[1]); `signal(REPLICATE, 4); // UNOPTFLAT assign REPLICATE = rand_a[3:0] ^ ({2{REPLICATE[3:2]}} >> 2); `signal(PARTIAL, 4); // UNOPTFLAT assign PARTIAL[0] = rand_a[0]; // PARTIAL[1] intentionally unconnected assign PARTIAL[3:2] = rand_a[3:2] ^ {PARTIAL[2], PARTIAL[0]}; wire [2:0] array_0 [2]; assign array_0[0] = rand_a[2:0]; assign array_0[1] = array_0[0]; `signal(ARRAY_0, 3); // UNOPTFLAT assign ARRAY_0 = array_0[1]; wire [2:0] array_1 [1]; assign array_1[0][0] = rand_a[0]; assign array_1[0][1] = array_1[0][0]; assign array_1[0][2] = array_1[0][1]; `signal(ARRAY_1, 3); // UNOPTFLAT assign ARRAY_1 = array_1[0]; wire [2:0] array_2a [2]; wire [2:0] array_2b [2]; assign array_2a[0][0] = rand_a[0]; assign array_2a[0][1] = array_2b[1][0]; assign array_2a[0][2] = array_2b[1][1]; assign array_2a[1] = array_2a[0]; assign array_2b = array_2a; `signal(ARRAY_2, 3); // UNOPTFLAT assign ARRAY_2 = array_2a[0]; wire [2:0] array_3 [2]; assign array_3[0] = rand_a[2:0] ^ array_3[1] >> 1; assign array_3[1] = array_3[0]; `signal(ARRAY_3, 3); // UNOPTFLAT assign ARRAY_3 = array_3[0]; `signal(ADD_A, 8); // UNOPTFLAT `signal(ADD_B, 8); `signal(ADD_C, 8); assign ADD_C = rand_b[7:0] + ADD_B; assign ADD_B = (ADD_A << 4) + rand_a[7:0]; assign ADD_A = {ADD_C[7], 7'd0}; `signal(SUB_A, 8); // UNOPTFLAT `signal(SUB_B, 8); `signal(SUB_C, 8); assign SUB_C = rand_b[7:0] - SUB_B; assign SUB_B = (SUB_A << 4) - rand_a[7:0]; assign SUB_A = {SUB_C[7], 7'd0}; `signal(EQ_A, 1); // UNOPTFLAT `signal(EQ_B, 3); assign EQ_A = EQ_B >> 1 == rand_b[2:0]; assign EQ_B = {rand_a[1:0], EQ_A}; `signal(NEQ_A, 1); // UNOPTFLAT `signal(NEQ_B, 3); assign NEQ_A = NEQ_B >> 1 != rand_b[2:0]; assign NEQ_B = {rand_a[1:0], NEQ_A}; `signal(LT_A, 1); // UNOPTFLAT `signal(LT_B, 3); assign LT_A = LT_B >> 1 < rand_b[2:0]; assign LT_B = {rand_a[1:0], LT_A}; `signal(LTE_A, 1); // UNOPTFLAT `signal(LTE_B, 3); assign LTE_A = LTE_B >> 1 <= rand_b[2:0]; assign LTE_B = {rand_a[1:0], LTE_A}; `signal(GT_A, 1); // UNOPTFLAT `signal(GT_B, 3); assign GT_A = GT_B >> 1 > rand_b[2:0]; assign GT_B = {rand_a[1:0], GT_A}; `signal(GTE_A, 1); // UNOPTFLAT `signal(GTE_B, 3); assign GTE_A = GTE_B >> 1 >= rand_b[2:0]; assign GTE_B = {rand_a[1:0], GTE_A}; `signal(COND_THEN, 3); // UNOPTFLAT assign COND_THEN = {rand_a[0], rand_a[0] ? 2'(COND_THEN << 2) : rand_b[1:0]}; `signal(COND_ELSE, 3); // UNOPTFLAT assign COND_ELSE = {rand_a[0], rand_a[0] ? rand_b[1:0] : 2'(COND_ELSE << 2)}; `signal(COND_COND, 3); // UNOPTFLAT assign COND_COND = {rand_a[0], (COND_COND >> 2) == 3'b001 ? rand_b[3:2] : rand_b[1:0]}; // verilator lint_off ALWCOMBORDER logic [3:0] always_0; always_comb begin always_0[3] = ~always_0[1]; always_0[2] = always_0[1]; always_0[0] = rand_a[0]; end assign always_0[1] = ~always_0[0]; `signal(ALWAYS_0, 4); // UNOPTFLAT assign ALWAYS_0 = always_0; // verilator lint_on ALWCOMBORDER // verilator lint_off ALWCOMBORDER logic [4:0] always_1; always_comb begin always_1[4] = always_1[0]; always_1[0] = rand_a[0]; always_1[3:2] = always_1[1:0]; end assign always_1[1] = always_1[0]; `signal(ALWAYS_1, 5); // UNOPTFLAT assign ALWAYS_1 = always_1; // verilator lint_on ALWCOMBORDER // verilator lint_off ALWCOMBORDER logic [3:0] always_2; always_comb begin always_2[2:0] = 3'((always_2 << 1) | 4'(rand_a[0])); always_2[3] = rand_a[0]; end `signal(ALWAYS_2, 4); // UNOPTFLAT assign ALWAYS_2 = always_2; // verilator lint_on ALWCOMBORDER logic [31:0] array_4[3]; // UNOPTFLAT // Input assign array_4[0] = rand_a[31:0]; // Sums 1 assign array_4[1][ 0 +: 3] = array_4[0][ 2 +: 2] + array_4[0][ 0 +: 2]; assign array_4[1][ 3 +: 3] = array_4[0][ 6 +: 2] + array_4[0][ 4 +: 2]; assign array_4[1][ 6 +: 3] = array_4[0][10 +: 2] + array_4[0][ 8 +: 2]; assign array_4[1][ 9 +: 3] = array_4[0][14 +: 2] + array_4[0][12 +: 2]; assign array_4[1][12 +: 3] = array_4[0][18 +: 2] + array_4[0][16 +: 2]; assign array_4[1][15 +: 3] = array_4[0][22 +: 2] + array_4[0][20 +: 2]; assign array_4[1][18 +: 3] = array_4[0][26 +: 2] + array_4[0][24 +: 2]; assign array_4[1][21 +: 3] = array_4[0][30 +: 2] + array_4[0][28 +: 2]; // Sums 2 assign array_4[2][ 0 +: 4] = array_4[1][ 3 +: 3] + array_4[1][ 0 +: 3]; assign array_4[2][ 4 +: 4] = array_4[1][ 9 +: 3] + array_4[1][ 6 +: 3]; assign array_4[2][ 8 +: 4] = array_4[1][15 +: 3] + array_4[1][12 +: 3]; assign array_4[2][12 +: 4] = array_4[1][21 +: 3] + array_4[1][18 +: 3]; // Outupt `signal(ARRAY_4, 32); assign ARRAY_4 = array_4[2]; logic [1:0] packed_0; // UNOPTFLAT logic packed_0_lsb; always_comb begin packed_0[1] = rand_b[1]; packed_0_lsb = packed_0[0]; end always_comb packed_0[0] = rand_b[0]; assign PACKED_0 = packed_0; `signal(PACKED_0, 2); `signal(PACKED_0_LSB, 1); assign PACKED_0_LSB = packed_0_lsb; endmodule verilator-5.042/test_regress/t/t_flag_fi_h.h0000644000542200017500000000101715101701376021457 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2010-2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* extern void myfunction(); verilator-5.042/test_regress/t/t_gate_width_bad.out0000644000542200017500000000201115101701376023061 0ustar mahmoudyfreeshell%Error: t/t_gate_width_bad.v:14:26: Gate primitive connection expects 1 bits on the gate port, but the connection generates 2 bits (IEEE 1800-2023 28.3.6) : ... note: In instance 't' 14 | buf buf2[0:0] (out[1], 2'b01); | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_gate_width_bad.v:15:28: Gate primitive connection expects 1 bits on the gate port, but the connection generates 2 bits (IEEE 1800-2023 28.3.6) : ... note: In instance 't' 15 | buf buf3[0:0] (out[2], in[1:0]); | ^ %Error: t/t_gate_width_bad.v:16:28: Gate primitive connection expects 4 bits or 1 bit on the gate port, but the connection generates 2 bits (IEEE 1800-2023 28.3.6) : ... note: In instance 't' 16 | buf buf4[3:0] (out[2], in[1:0]); | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_disable_empty.v0000644000542200017500000000056515101701376022427 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin if (0) begin : block end disable block; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_timing_strobe.v0000644000542200017500000000113215101701376022442 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; event e1; event e2; int v = 0; initial begin #1 $strobe("v = %0d", v); ->e1; @e2 $strobe("v = %0d", v); ->e1; @e2 $strobe("v = %0d", v); ->e1; @e2 $write("*-* All Finished *-*\n"); $finish; end initial begin @e1 v = 1; #1 ->e2; @e1 v = 2; #1 ->e2; @e1 v = 3; #1 ->e2; end initial #5 $stop; // timeout endmodule verilator-5.042/test_regress/t/t_math_real_private.py0000755000542200017500000000126715101701376023462 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = 't/t_math_real_public.v' # Test that --private overrides --public test.compile(verilator_flags2=['--cc --public --private']) test.execute() test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + "___024root.h", r'REAL_PARAM') test.passes() verilator-5.042/test_regress/t/t_gen_missing_bad.out0000644000542200017500000000145715101701376023261 0ustar mahmoudyfreeshell%Error-MODMISSING: t/t_gen_missing.v:43:20: Cannot find file containing module: 'foo_not_needed' 43 | foo_not_needed i_foo(.x(foo[j]), .y(bar[j])); | ^~~~~~~~~~~~~~ ... For error description see https://verilator.org/warn/MODMISSING?v=latest ... Looked in: t/foo_not_needed t/foo_not_needed.v t/foo_not_needed.sv foo_not_needed foo_not_needed.v foo_not_needed.sv obj_vlt/t_gen_missing_bad/foo_not_needed obj_vlt/t_gen_missing_bad/foo_not_needed.v obj_vlt/t_gen_missing_bad/foo_not_needed.sv %Error: Exiting due to verilator-5.042/test_regress/t/t_interface_localparam.py0000755000542200017500000000073415101701376024125 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_mailbox_notiming.py0000755000542200017500000000101715101701376023324 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--exe --main --no-timing -Wall"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_array_modport.v0000644000542200017500000000125715101701376024507 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Connecting an interface array slice to a module's portmap // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 interface foo_intf; logic a; modport m(input a); endinterface module foo_mod ( foo_intf foo, foo_intf.m bars[4] ); endmodule module t; localparam N = 4; foo_intf foos [N-1:0] (); foo_intf bars [N] (); //foo_intf foos (); foo_mod foo_mod ( .foo (foos[2]), .bars (bars) //.foo (foos) ); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_emit_constw.v0000644000542200017500000001433615101701376022142 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2015 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkhw(gotv,w,expv) do if (gotv[(w)*32+:$bits(expv)] !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv[(w)*32+:32]), (expv)); `stop; end while(0); module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; bit [4*32-1:0] w4 = {32'h7c709753, 32'hbc8f6059, 32'h3b0db464, 32'h721a8fad}; bit [8*32-2:0] w8m = {31'h7146e1bf, 32'ha8549e42, 32'hca6960bd, 32'h191b7f9b, 32'h93d79866, 32'hf4489e2b, 32'h8e9a3236, 32'h1d2a2d1d}; bit [8*32-1:0] w8 = {32'hc211addc, 32'he5d4a057, 32'h5cbf88fe, 32'h42cf42e2, 32'heb584263, 32'ha585f118, 32'h231531c8, 32'hc73f7b06}; bit [8*32-0:0] w8p = {1'b1, 32'h096aa54b, 32'h48aae18e, 32'hf9502cea, 32'h518c8b61, 32'h9e8641a2, 32'h0dc0249c, 32'hd421a87a, 32'hb8ee9199}; bit [9*32-1:0] w9 = {32'hca800ac1, 32'h0de4823a, 32'ha51663ac, 32'h96351446, 32'h6b0bbcd5, 32'h4a64b530, 32'h4967d59a, 32'hfcc17292, 32'h57926621}; bit [16*32-2:0] w16m = {31'h77ad72c7, 32'h73aa9cbb, 32'h7ecf026d, 32'h985a3ed2, 32'hfe961c1d, 32'h7a01df72, 32'h79e13d71, 32'hb69e2e32, 32'h09fcbc45, 32'hcfd738c1, 32'hc197ac7c, 32'hc316d727, 32'h903034e4, 32'h92a047d1, 32'h6a5357af, 32'ha82ce9c8}; bit [16*32-1:0] w16 = {32'he49548a7, 32'ha02336a2, 32'h2bb48f0d, 32'h9974e098, 32'h34ae644f, 32'hca46dc2c, 32'h9f71a468, 32'h64ae043e, 32'h7bc94d66, 32'h57aba588, 32'h5b9bb4fe, 32'hb87ed644, 32'hd34b5b20, 32'h712928de, 32'h4bdbd28e, 32'ha0576784}; bit [16*32-0:0] w16p = {1'b1, 32'hd278a306, 32'h374ce262, 32'hb608c88e, 32'h43d3e446, 32'h42e26866, 32'h44c31148, 32'hd3db659f, 32'hb3b84b2e, 32'h1aa7a184, 32'h73b28538, 32'h6384e801, 32'h98d58e00, 32'h9c1d1429, 32'hb407730e, 32'he974c1fd, 32'he787c302}; bit [17*32-1:0] w17 = {32'hf1e322ac, 32'hbbdbd761, 32'h760fe07d, 32'h3808cb28, 32'haf313051, 32'h37dc63b9, 32'hdddb418b, 32'he65a9d64, 32'hc1b6ab23, 32'h11131ac1, 32'h0050e0bc, 32'h442e3754, 32'h0eb4556e, 32'hd153064b, 32'h41349f97, 32'hb6f4149f, 32'h34bb1fb1}; function [7:0] bytehash (input [32*32-1:0] data); integer i; bytehash = 0; for (i=0; i<32*32; ++i) begin bytehash = {bytehash[0], bytehash[7:1]} ^ data[i +: 8]; end return bytehash; endfunction // Aggregate outputs into a single result vector // verilator lint_off WIDTH wire [63:0] result = (bytehash(w4) ^ bytehash(w8m) ^ bytehash(w8) ^ bytehash(w8p) ^ bytehash(w9) ^ bytehash(w16m) ^ bytehash(w16) ^ bytehash(w16p) ^ bytehash(w17)); // verilator lint_on WIDTH `define EXPECTED_SUM 64'h2bc7c2a98a302891 // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; // verilator lint_off SELRANGE `checkhw(w4,3,32'h7c709753); `checkhw(w4,2,32'hbc8f6059); `checkhw(w4,1,32'h3b0db464); `checkhw(w4,0,32'h721a8fad); `checkhw(w8m,7,31'h7146e1bf); `checkhw(w8m,6,32'ha8549e42); `checkhw(w8m,5,32'hca6960bd); `checkhw(w8m,4,32'h191b7f9b); `checkhw(w8m,3,32'h93d79866); `checkhw(w8m,2,32'hf4489e2b); `checkhw(w8m,1,32'h8e9a3236); `checkhw(w8m,0,32'h1d2a2d1d); `checkhw(w8,7,32'hc211addc); `checkhw(w8,6,32'he5d4a057); `checkhw(w8,5,32'h5cbf88fe); `checkhw(w8,4,32'h42cf42e2); `checkhw(w8,3,32'heb584263); `checkhw(w8,2,32'ha585f118); `checkhw(w8,1,32'h231531c8); `checkhw(w8,0,32'hc73f7b06); `checkhw(w8p,8,1'b1); `checkhw(w8p,7,32'h096aa54b); `checkhw(w8p,6,32'h48aae18e); `checkhw(w8p,5,32'hf9502cea); `checkhw(w8p,4,32'h518c8b61); `checkhw(w8p,3,32'h9e8641a2); `checkhw(w8p,2,32'h0dc0249c); `checkhw(w8p,1,32'hd421a87a); `checkhw(w8p,0,32'hb8ee9199); `checkhw(w9,8,32'hca800ac1); `checkhw(w9,7,32'h0de4823a); `checkhw(w9,6,32'ha51663ac); `checkhw(w9,5,32'h96351446); `checkhw(w9,4,32'h6b0bbcd5); `checkhw(w9,3,32'h4a64b530); `checkhw(w9,2,32'h4967d59a); `checkhw(w9,1,32'hfcc17292); `checkhw(w9,0,32'h57926621); `checkhw(w16m,15,31'h77ad72c7); `checkhw(w16m,14,32'h73aa9cbb); `checkhw(w16m,13,32'h7ecf026d); `checkhw(w16m,12,32'h985a3ed2); `checkhw(w16m,11,32'hfe961c1d); `checkhw(w16m,10,32'h7a01df72); `checkhw(w16m,9,32'h79e13d71); `checkhw(w16m,8,32'hb69e2e32); `checkhw(w16m,7,32'h09fcbc45); `checkhw(w16m,6,32'hcfd738c1); `checkhw(w16m,5,32'hc197ac7c); `checkhw(w16m,4,32'hc316d727); `checkhw(w16m,3,32'h903034e4); `checkhw(w16m,2,32'h92a047d1); `checkhw(w16m,1,32'h6a5357af); `checkhw(w16m,0,32'ha82ce9c8); // verilator lint_on SELRANGE end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin w4 = w4 >>> 1; w8m = w8m >>> 1; w8 = w8 >>> 1; w8p = w8p >>> 1; w9 = w9 >>> 1; w16m = w16m >>> 1; w16 = w16 >>> 1; w16p = w16p >>> 1; w17 = w17 >>> 1; end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_param_hier_bad.out0000644000542200017500000000202015101701376023051 0ustar mahmoudyfreeshell%Error-HIERPARAM: t/t_param_hier_bad.v:36:32: Parameter values cannot use hierarchical values (IEEE 1800-2023 6.20.2) : ... note: In instance 't' 36 | localparam int SUB_Y = u_sub.Y; | ^ ... For error description see https://verilator.org/warn/HIERPARAM?v=latest %Error: t/t_param_hier_bad.v:38:35: Parameter values cannot call hierarchical functions (IEEE 1800-2023 6.20.2) : ... note: In instance 't' 38 | localparam int SUB_FUNC = u_sub.sub_func(); | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_param_hier_bad.v:44:18: Parameter values cannot call hierarchical functions (IEEE 1800-2023 6.20.2) : ... note: In instance 't' 44 | sub #(.X(block.block_func())) u_sub2 (); | ^~~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_disable_inside.v0000644000542200017500000000423115101701376022536 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t; initial begin int x = 0; fork : fork_blk begin #1; disable fork_blk; // Disables both forked processes $stop; end begin if ($time != 0) $stop; x = 1; #2; $stop; end join_none #1; if (x != 1) begin $display(x); $stop; end end initial begin int y = 0; fork begin : fork_branch #1; disable fork_branch; // Disables only this branch of the fork $stop; end begin if ($time != 0) $stop; y = 1; #2; if ($time != 2) $stop; y = 2; end join_none #1; if (y != 1) begin $display(y); $stop; end #1; if (y != 2) begin $display(y); $stop; end end // TODO: This doesn't work due to the second fork branch not being added to // the killQueue when the 'disable' is executed with no delay after // the fork starts. See the case below which is the same, but the // fork branches are in the opposite order so it happens to work. //initial begin // fork : fork_blk2 // begin // if ($time != 0) $stop; // disable fork_blk2; // $stop; // end // begin // if ($time != 0) $stop; // #1 $stop; // end // join_none //end initial begin fork : fork_blk3 begin if ($time != 0) $stop; #1 $stop; end begin if ($time != 0) $stop; disable fork_blk3; $stop; end join_none end initial begin fork : fork_blk4 begin if ($time != 0) $stop; if ($c("false")) begin disable fork_blk4; $stop; end #1; end begin if ($time != 0) $stop; #1; if ($time != 1) $stop; end join_none end initial begin #10; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_force_struct_partial.py0000755000542200017500000000073415101701376024210 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_hier_construction.v0000644000542200017500000000401015101701376024521 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Petr Nohavica // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); interface class IBottomMid; pure virtual function void moo(int i); endclass interface class IBottom; pure virtual function bit foo(); endclass interface class IMid extends IBottomMid; pure virtual function string bar(); endclass class bottom_class implements IBottom; string name; function new(string name); this.name = name; endfunction virtual function bit foo(); $display("%s", name); return 1'b0; endfunction endclass class middle_class extends bottom_class implements IMid, IBottom; function new(string name); super.new($sformatf("middle %0s", name)); endfunction virtual function bit foo(); $display("%s", name); return 0; endfunction virtual function void moo(int i); $display("moo: %d", i); endfunction virtual function string bar(); return name; endfunction endclass class top_class extends middle_class; int i; function new(string name, int i); super.new($sformatf("%0s %0d", name, i)); this.i = i; endfunction endclass class sky_class extends top_class; function new(string name); super.new(name, 42); endfunction endclass module t; initial begin sky_class s = new("ahoj"); bottom_class b = s; top_class t = s; IMid im; `checks( b.name, "middle ahoj 42" ); `checks( s.name, "middle ahoj 42" ); `checks( t.name, "middle ahoj 42" ); `checkh( t.i, 42); `checks(s.bar(), "middle ahoj 42"); im = s; im.moo(42); $finish; end endmodule verilator-5.042/test_regress/t/t_lint_always_comb_multidriven_bad.v0000644000542200017500000000274615101701376026367 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs out1, out2, out3, out4, out5, out6, out7, out8, // Inputs clk, d ); input clk; input d; output reg out1; output reg out2; output reg out3; output reg out4; output reg out5; output reg out6; output reg out7; output reg out8; assign out1 = 1'b0; always_comb out1 = d; // <--- Warning assign out2 = d; always_comb out2 = 1'b0; // <--- Warning always_comb out3 = d; assign out3 = 1'b0; // <--- Warning always_comb out4 = 1'b0; assign out4 = d; // <--- Warning always_comb out5 = 1'b0; always_comb out5 = d; // <--- Warning always_comb out6 = d; always_comb out6 = 1'b0; // <--- Warning always_comb begin out7 = 1'b0; out7 = d; end always_comb begin out8 = d; out8 = 1'b0; end reg [1:0] arr_packed; reg arr_unpacked [0:1]; reg [1:0] gen_arr_packed; reg gen_arr_unpacked [0:1]; genvar g; always_comb begin arr_packed[0] = d; arr_packed[1] = d; end always_comb begin arr_unpacked[0] = d; arr_unpacked[1] = d; end generate for (g=0; g<2; ++g) begin always_comb gen_arr_packed[g] = d; always_comb gen_arr_unpacked[g] = d; end endgenerate endmodule verilator-5.042/test_regress/t/t_dpi_import.py0000755000542200017500000000105315101701376022133 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=["t/t_dpi_import_c.cpp"], verilator_flags2=["-Wall -Wno-DECLFILENAME"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_x_rand_mt_stability.py0000755000542200017500000000147015101701376024027 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap import glob test.scenarios("vltmt") test.top_filename = "t/t_x_rand_stability.v" test.compile(verilator_flags2=["--x-initial unique"]) test.execute(all_run_flags=["+verilator+rand+reset+2"], expect_filename=test.golden_filename) test.passes() other_logs = [x for x in glob.glob("t/t_x_rand_mt_stability_*.out") if "_zero" not in x] for other_log in other_logs: test.files_identical(test.golden_filename, other_log) verilator-5.042/test_regress/t/t_assigndly_deep_ref_array.py0000755000542200017500000000101315101701376025005 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(timing_loop=True, verilator_flags2=['--timing']) test.execute() test.passes() verilator-5.042/test_regress/t/t_emit_accessors.py0000755000542200017500000000105015101701376022765 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(make_main=False, verilator_flags2=["--emit-accessors", "--exe", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_assert_iff.v0000644000542200017500000000177715101701376021741 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; logic[3:0] enable; int cyc = 0; Test test(.*); always @ (posedge clk) begin cyc <= cyc + 1; `ifdef FAIL1 enable[0] <= 1; `endif enable[1] <= 1; `ifdef FAIL2 enable[2] <= 1; `endif enable[3] <= 1; if (cyc != 0) begin if (cyc == 10) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module Test( input clk, input[3:0] enable ); assert property ( @(posedge clk iff enable[0]) 0 ) else $stop; assert property ( @(posedge clk iff enable[1]) 1 ); cover property ( @(posedge clk iff enable[2]) 1 ) $stop; cover property ( @(posedge clk iff enable[3]) 0 ) $stop; endmodule verilator-5.042/test_regress/t/t_preproc_preproczero_bad.out0000644000542200017500000000077315101701376025063 0ustar mahmoudyfreeshell%Warning-PREPROCZERO: t/t_preproc_preproczero_bad.v:11:10: Preprocessor expression evaluates define with 0: 'ZERO' with value '0' ... Suggest change define 'ZERO' to non-zero value if used in preprocessor expression 11 | `ifdef ( ZERO ) | ^~~~ ... For warning description see https://verilator.org/warn/PREPROCZERO?v=latest ... Use "/* verilator lint_off PREPROCZERO */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_flag_version.py0000755000542200017500000000256015101701376022447 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') n = 0 for prog in [ # See also t_flag_help.py os.environ["VERILATOR_ROOT"] + "/bin/verilator", os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", #os.environ["VERILATOR_ROOT"] + "/bin/verilator_difftree", #os.environ["VERILATOR_ROOT"] + "/bin/verilator_gantt", #os.environ["VERILATOR_ROOT"] + "/bin/verilator_profcfunc", ]: n += 1 log_filename = test.obj_dir + "/vlt_" + str(n) + ".log" test.run(fails=False, cmd=["perl", prog, "--version"], tee=test.verbose, logfile=log_filename, verilator_run=True) test.file_grep(log_filename, r'Verilator') n += 1 log_filename = test.obj_dir + "/vlt_" + str(n) + ".log" test.run(fails=False, cmd=["perl", prog, "-V"], tee=test.verbose, logfile=log_filename, verilator_run=True) test.file_grep(log_filename, r'Verilator') test.passes() verilator-5.042/test_regress/t/t_gate_inline_wide_noexclude_varref.v0000644000542200017500000000066315101701376026506 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t(input [255:0] clk); // Do not exclude from inlining wide reference assignments. mod1 mod1(clk); mod2 mod2(clk); endmodule module mod1(input [255:0] clk); endmodule module mod2(input [255:0] clk); endmodule verilator-5.042/test_regress/t/t_hier_block_type_param.py0000755000542200017500000000112515101701376024307 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--hierarchical']) test.execute() test.file_grep(test.obj_dir + "/VTest_1/Test_1.sv", r'^module\s+(\S+)\s+', "Test_1") test.passes() verilator-5.042/test_regress/t/t_sys_readmem_bad_addr.out0000644000542200017500000000014115101701376024246 0ustar mahmoudyfreeshell%Error: t/t_sys_readmem_bad_addr.mem:9: $readmem file address beyond bounds of array Aborting... verilator-5.042/test_regress/t/t_gen_cond_bitrange_bad.py0000755000542200017500000000076615101701376024234 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_math_pow.py0000755000542200017500000000330015101701376021600 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['-fno-gate']) test.execute(expect_filename=test.golden_filename) # Check for coverage on all POW functions os.system("cat " + test.obj_dir + "/" + test.vm_prefix + "_*.cpp > " + test.obj_dir + "/all.cpp") test.file_grep(test.obj_dir + "/all.cpp", r'VL_POW_III') test.file_grep(test.obj_dir + "/all.cpp", r'VL_POW_IIQ') test.file_grep(test.obj_dir + "/all.cpp", r'VL_POW_IIW') test.file_grep(test.obj_dir + "/all.cpp", r'VL_POW_QQI') test.file_grep(test.obj_dir + "/all.cpp", r'VL_POW_QQQ') test.file_grep(test.obj_dir + "/all.cpp", r'VL_POW_QQW') test.file_grep(test.obj_dir + "/all.cpp", r'VL_POW_WWI') test.file_grep(test.obj_dir + "/all.cpp", r'VL_POW_WWQ') test.file_grep(test.obj_dir + "/all.cpp", r'VL_POW_WWW') test.file_grep(test.obj_dir + "/all.cpp", r'VL_POWSS_III') test.file_grep(test.obj_dir + "/all.cpp", r'VL_POWSS_IIQ') test.file_grep(test.obj_dir + "/all.cpp", r'VL_POWSS_IIW') test.file_grep(test.obj_dir + "/all.cpp", r'VL_POWSS_QQI') test.file_grep(test.obj_dir + "/all.cpp", r'VL_POWSS_QQQ') test.file_grep(test.obj_dir + "/all.cpp", r'VL_POWSS_QQW') test.file_grep(test.obj_dir + "/all.cpp", r'VL_POWSS_WWI') test.file_grep(test.obj_dir + "/all.cpp", r'VL_POWSS_WWQ') test.file_grep(test.obj_dir + "/all.cpp", r'VL_POWSS_WWW') test.passes() verilator-5.042/test_regress/t/t_gate_basic_specify_bad.py0000755000542200017500000000103215101701376024373 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = 't/t_gate_basic.v' test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_extends_alias_unsup.v0000644000542200017500000000134515101701376025045 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ ); class foo; int x = 1; function int get_x; return x; endfunction function int get_3; return 3; endfunction endclass typedef foo foo_t; class bar extends foo_t; endclass bar bar_foo_t_i; initial begin bar_foo_t_i = new; if (bar_foo_t_i.get_x() == 1 && bar_foo_t_i.get_3() == 3) begin $write("*-* All Finished *-*\n"); $finish; end else begin $stop; end end endmodule verilator-5.042/test_regress/t/t_class_param_subtype_constsim.py0000755000542200017500000000105115101701376025742 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_class_param_subtype.v" test.compile(v_flags2=['+define+CONSTSIM']) test.execute() test.passes() verilator-5.042/test_regress/t/t_tri_various.v0000644000542200017500000001303715101701376022152 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2008 by Lane Brooks. // SPDX-License-Identifier: CC0-1.0 module t ( clk ); input clk; reg [31:0] state; initial state = 0; wire A = state[0]; wire OE = state[1]; wire Z1, Z2, Z3, Z4, Z5, Z6, Z7, Z8, Z9; wire [3:0] Z10; wire Z11; Test1 test1 ( /*AUTOINST*/ // Inouts .Z1 (Z1), // Inputs .OE (OE), .A (A)); Test2 test2 ( /*AUTOINST*/ // Inouts .Z2 (Z2), // Inputs .OE (OE), .A (A)); Test3 test3 ( /*AUTOINST*/ // Inouts .Z3 (Z3), // Inputs .OE (OE), .A (A)); Test4 test4 ( /*AUTOINST*/ // Outputs .Z4 (Z4), // Inouts .Z5 (Z5)); Test5 test5 ( /*AUTOINST*/ // Inouts .Z6 (Z6), .Z7 (Z7), .Z8 (Z8), .Z9 (Z9), // Inputs .OE (OE)); Test6 test6 ( /*AUTOINST*/ // Inouts .Z10 (Z10[3:0]), // Inputs .OE (OE)); Test7 test7 ( /*AUTOINST*/ // Outputs .Z11 (Z11), // Inputs .state (state[2:0])); always @(posedge clk) begin state <= state + 1; `ifdef TEST_VERBOSE $write("[%0t] state=%d Z1=%b 2=%b 3=%b 4=%b 5=%b 6=%b 7=%b 8=%b 9=%b 10=%b 11=%b\n", $time, state, Z1, Z2, Z3, Z4, Z5, Z6, Z7, Z8, Z9, Z10, Z11); `endif if (state == 0) begin if (Z1 !== 1'b1) $stop; // tests pullups if (Z2 !== 1'b1) $stop; if (Z3 !== 1'b1) $stop; `ifndef VERILATOR if (Z4 !== 1'b1) $stop; `endif if (Z5 !== 1'b1) $stop; if (Z6 !== 1'b1) $stop; if (Z7 !== 1'b0) $stop; if (Z8 !== 1'b0) $stop; if (Z9 !== 1'b1) $stop; if (Z10 !== 4'b0001) $stop; if (Z11 !== 1'b0) $stop; end else if (state == 1) begin if (Z1 !== 1'b1) $stop; // tests pullup if (Z2 !== 1'b1) $stop; if (Z3 !== 1'b1) $stop; `ifndef VERILATOR if (Z4 !== 1'b1) $stop; `endif if (Z5 !== 1'b1) $stop; if (Z6 !== 1'b1) $stop; if (Z7 !== 1'b0) $stop; if (Z8 !== 1'b0) $stop; if (Z9 !== 1'b1) $stop; if (Z10 !== 4'b0001) $stop; if (Z11 !== 1'b1) $stop; end else if (state == 2) begin if (Z1 !== 1'b0) $stop; // tests output driver low if (Z2 !== 1'b0) $stop; if (Z3 !== 1'b1 && Z3 !== 1'bx) $stop; // Conflicts `ifndef VERILATOR if (Z4 !== 1'b1) $stop; `endif if (Z5 !== 1'b1) $stop; if (Z6 !== 1'b0) $stop; if (Z7 !== 1'b1) $stop; if (Z8 !== 1'b1) $stop; if (Z9 !== 1'b0) $stop; if (Z10 !== 4'b0010) $stop; //if(Z11 !== 1'bx) $stop; // Doesn't matter end else if (state == 3) begin if (Z1 !== 1'b1) $stop; // tests output driver high if (Z2 !== 1'b1) $stop; if (Z3 !== 1'b1) $stop; `ifndef VERILATOR if (Z4 !== 1'b1) $stop; `endif if (Z5 !== 1'b1) $stop; if (Z6 !== 1'b0) $stop; if (Z7 !== 1'b1) $stop; if (Z8 !== 1'b1) $stop; if (Z9 !== 1'b0) $stop; if (Z10 !== 4'b0010) $stop; if (Z11 !== 1'b1) $stop; end else if (state == 4) begin $write("*-* All Finished *-*\n"); $finish; end end pullup (Z1), (Z2); pullup (Z3); pullup (Z4); pullup (Z5); pullup (Z6); pulldown (Z7), (Z9); pullup (Z8); pulldown pd10[3:0] (Z10); endmodule module Test1 ( input OE, input A, inout Z1 ); assign Z1 = (OE) ? A : 1'bz; endmodule module Test2 ( input OE, input A, inout Z2 ); assign Z2 = (OE) ? A : 1'bz; endmodule // mixed low-Z and tristate module Test3 ( input OE, input A, inout Z3 ); assign Z3 = (OE) ? A : 1'bz; assign Z3 = 1'b1; endmodule // floating output and inout `ifndef VERILATOR // Note verilator doesn't know to make Z4 a tristate unless marked an inout `endif module Test4 ( output Z4, inout Z5 ); endmodule // AND gate tristates module Test5 ( input OE, inout Z6, inout Z7, inout Z8, inout Z9 ); assign Z6 = (OE) ? 1'b0 : 1'bz; assign Z7 = (OE) ? 1'b1 : 1'bz; assign Z8 = (OE) ? 1'bz : 1'b0; assign Z9 = (OE) ? 1'bz : 1'b1; endmodule // AND gate tristates module Test6 ( input OE, inout [3:0] Z10 ); wire [1:0] i; Test6a a ( .OE(OE), .Z({Z10[0], Z10[1]}) ); Test6a b ( .OE(~OE), .Z({Z10[2], Z10[0]}) ); endmodule module Test6a ( input OE, inout [1:0] Z ); assign Z = (OE) ? 2'b01 : 2'bzz; endmodule module Test7 ( input [2:0] state, output reg Z11 ); always @(*) begin casez (state) 3'b000: Z11 = 1'b0; 3'b0?1: Z11 = 1'b1; default: Z11 = 1'bx; endcase end endmodule // This is not implemented yet //module Test3(input OE, input A, inout Z3); // always @(*) begin // if(OE) begin // Z3 = A; // end else begin // Z3 = 1'bz; // end // end //endmodule verilator-5.042/test_regress/t/t_trace_scstruct.py0000755000542200017500000000107615101701376023022 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--sc --trace-vcd --trace-structs --pins-bv 2']) #test.execute() # didn't bother with top shell test.passes() verilator-5.042/test_regress/t/t_inc_relink.py0000755000542200017500000000076015101701376022106 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["-Wno-WIDTHTRUNC"]) test.passes() verilator-5.042/test_regress/t/t_math_countbits.v0000644000542200017500000001272015101701376022625 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 Yossi Nivin. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; reg [15:0] in16; reg [31:0] in32; reg [63:0] in64; // Non-standard size reg [9:0] in10; reg [20:0] in21; reg [58:0] in59; reg [69:0] in70; reg [31:0] ctrl0; reg [31:0] ctrl1; reg [31:0] ctrl2; int result_16_1; int result_16_2; int result_16_3; int result_32_1; int result_32_2; int result_32_3; int result_64_1; int result_64_2; int result_64_3; int result_10_3; int result_21_3; int result_59_3; int result_70_3; initial begin if ($countbits(32'b111100000000, '1) != 4) $stop; if ($countbits(32'b111100000000, '0) != 28) $stop; if ($countbits(32'b111100000000, '0, '1) != 32) $stop; if ($countbits(4'bxxx0, 'x) != 3) $stop; if ($countbits(4'bzzz0, 'z) != 3) $stop; if ($countbits(4'b1zz0, 'z, '0) != 3) $stop; if ($countbits(4'b1xx0, 'x, '0) != 3) $stop; if ($countbits(4'b1xx0, 'x, '0, '1) != 4) $stop; if ($countbits(4'bzzx0, 'x, 'z) != 3) $stop; end always @* begin result_16_1 = $countbits(in16, ctrl0); result_16_2 = $countbits(in16, ctrl0, ctrl1); result_16_3 = $countbits(in16, ctrl0, ctrl1, ctrl2); result_32_1 = $countbits(in32, ctrl0); result_32_2 = $countbits(in32, ctrl0, ctrl1); result_32_3 = $countbits(in32, ctrl0, ctrl1, ctrl2); result_64_1 = $countbits(in64, ctrl0); result_64_2 = $countbits(in64, ctrl0, ctrl1); result_64_3 = $countbits(in64, ctrl0, ctrl1, ctrl2); result_10_3 = $countbits(in10, ctrl0, ctrl1, ctrl2); result_21_3 = $countbits(in21, ctrl0, ctrl1, ctrl2); result_59_3 = $countbits(in59, ctrl0, ctrl1, ctrl2); result_70_3 = $countbits(in70, ctrl0, ctrl1, ctrl2); end logic [31:0] val = 32'h70008421; integer cyc = 0; // Test loop always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 0) begin // Constants if ($countbits(32'b11001011101, '1) != 7) $stop; if ($countbits(32'b11001011101, '1, 'z) != 7) $stop; if ($countbits(32'b11001011101, '1, '0) != 32) $stop; if ($countbits(20'b11001011101, '1, '0) != 20) $stop; if ($countbits(20'b1100x01z101, '1, '0) != 18) $stop; if ($countbits(20'b1100x01z101, 2, 2'bx1) != 18) $stop; if ($countbits(32'b1100x01z101, 'x, 'z) != 2) $stop; if ($countbits(32'b1100x01z101, 'x, 'z, '1) != 7) $stop; if ($countbits(val, '1) != 7) $stop; if ($countones(val) != 7) $stop; if ($countbits(val, '0) != 25) $stop; if ($countbits(val, '0, '1) != 32) $stop; // Optimization may depend on position of X, so need to walk it if ($countbits(val, 'x) != 0) $stop; if ($countbits(val, 'x, '1) != 7) $stop; if ($countbits(val, '1, 'x) != 7) $stop; if ($countbits(val, '1, '1, 'x) != 7) $stop; if ($countbits(val, 'x, '0) != 25) $stop; if ($countbits(val, 'x, '0, '1) != 32) $stop; // Optimization may depend on position of Z, so need to walk it if ($countbits(val, 'z) != 0) $stop; if ($countbits(val, 'z, '1) != 7) $stop; if ($countbits(val, '1, 'z) != 7) $stop; if ($countbits(val, '1, '1, 'z) != 7) $stop; if ($countbits(val, 'z, '0) != 25) $stop; if ($countbits(val, 'z, '0, '1) != 32) $stop; // if ($countbits(val, 'x, 'z) != 0) $stop; end else if (cyc == 1) begin in16 <= 16'h0AF0; in32 <= 32'hA0F300; in64 <= 64'hA5A5A5A5A5A5A5A5; in10 <= 10'b1010_1011; in21 <= 21'h10F102; in59 <= 59'h7050137210; in70 <= 70'hF00030008000; ctrl0 <= '0; ctrl1 <= '1; ctrl2 <= '1; end else if (cyc == 2) begin if (result_16_1 != 10) $stop; if (result_16_2 != 16) $stop; if (result_16_3 != 16) $stop; if (result_32_1 != 24) $stop; if (result_32_2 != 32) $stop; if (result_32_3 != 32) $stop; if (result_64_1 != 32) $stop; if (result_64_2 != 64) $stop; if (result_64_3 != 64) $stop; if (result_10_3 != 10) $stop; if (result_21_3 != 21) $stop; if (result_59_3 != 59) $stop; if (result_70_3 != 70) $stop; in16 <= 16'h82B; in32 <= 32'h305372; in64 <= 64'h7777777777777777; in10 <= 10'b1001_0111; in21 <= 21'h91040C; in59 <= 59'h12345678; in70 <= 70'hF11111111; // Confirm upper bits of the control arguments are ignored ctrl0 <= 5; ctrl1 <= 3; ctrl2 <= 2; end else if (cyc == 3) begin if (result_16_1 != 5) $stop; if (result_16_2 != 5) $stop; if (result_16_3 != 16) $stop; if (result_32_1 != 10) $stop; if (result_32_2 != 10) $stop; if (result_32_3 != 32) $stop; if (result_64_1 != 48) $stop; if (result_64_2 != 48) $stop; if (result_64_3 != 64) $stop; if (result_10_3 != 10) $stop; if (result_21_3 != 21) $stop; if (result_59_3 != 59) $stop; if (result_70_3 != 70) $stop; end else if (cyc == 4) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_interface_virtual_controlflow.out0000644000542200017500000000042215101701376026276 0ustar mahmoudyfreeshell[0] vif1.data==0000 [0] intf2.data==0000 [0] vif3.data==0000 [0] intf4.data==0000 [5000] intf2.data==beef [15000] vif1.data==dead [15000] vif3.data==fafa [15000] intf4.data==face [75000] intf4.data==cafe [95000] vif3.data==cafe [95000] intf4.data==deaf *-* All Finished *-* verilator-5.042/test_regress/t/t_case_string2.py0000755000542200017500000000073415101701376022355 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_flag_wwarn_bad.py0000755000542200017500000000114115101701376022720 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_flag_werror.v" test.lint(fails=True, verilator_flags=["-cc -Wwarn-NOSUCHERRORASTHIS"], expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_select_negative.v0000644000542200017500000000377115101701376022751 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; wire [15:-16] sel2 = crc[31:0]; wire [80:-10] sel3 = {crc[26:0],crc}; wire [3:0] out21 = sel2[-3 : -6]; wire [3:0] out22 = sel2[{1'b0,crc[3:0]} - 16 +: 4]; wire [3:0] out23 = sel2[{1'b0,crc[3:0]} - 10 -: 4]; wire [3:0] out31 = sel3[-3 : -6]; wire [3:0] out32 = sel3[crc[5:0] - 6 +: 4]; wire [3:0] out33 = sel3[crc[5:0] - 6 -: 4]; // Aggregate outputs into a single result vector wire [63:0] result = {40'h0, out21, out22, out23, out31, out32, out33}; reg [15:-16] sel1; initial begin // Path clearing sel1 = 32'h12345678; if (sel1 != 32'h12345678) $stop; if (sel1[-13 : -16] != 4'h8) $stop; if (sel1[3:0] != 4'h4) $stop; if (sel1[4 +: 4] != 4'h3) $stop; if (sel1[11 -: 4] != 4'h2) $stop; end // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] sels=%x,%x,%x %x,%x,%x\n", $time, out21,out22,out23, out31,out32,out33); $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; `define EXPECTED_SUM 64'hba7fe1e7ac128362 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_force_multi.py0000755000542200017500000000073415101701376022302 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_order_dpi_export_5.cpp0000644000542200017500000000232515101701376023713 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2021 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include #include #include int main(int argc, char* argv[]) { VM_PREFIX* const tb = new VM_PREFIX; tb->contextp()->commandArgs(argc, argv); bool clk = true; while (!tb->contextp()->gotFinish()) { // Timeout if (tb->contextp()->time() > 100000) break; // Toggle and set main clock clk = !clk; tb->clk = clk; // Reset counter at falling clock edge, once it reached value 4 svSetScope(svGetScopeFromName("TOP.testbench")); if (get_cnt() == 4 && !clk) set_cnt(0); // Eval tb->eval(); // Advance time tb->contextp()->timeInc(500); } delete tb; return 0; } verilator-5.042/test_regress/t/t_struct_unused.v0000644000542200017500000000072715101701376022515 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module x; typedef struct { int fst, snd; } uselessA_t; typedef struct { bit [3:0] n; uselessA_t b; } uselessB_t; uselessA_t useless; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_mod_interface_array6.v0000644000542200017500000001004315101701376023661 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) interface intf (); integer index; endinterface module t ( clk ); input clk; intf ifa1_intf[4:1](); intf ifa2_intf[4:1](); intf ifb1_intf[1:4](); intf ifb2_intf[1:4](); int cyc; sub sub0 ( .n(0), .clk, .cyc, .alh(ifa1_intf[2:1]), .ahl(ifa2_intf[2:1]), .blh(ifb1_intf[1:2]), .bhl(ifb2_intf[1:2]) ); sub sub1 ( .n(1), .clk, .cyc, .alh(ifa1_intf[4:3]), .ahl(ifa2_intf[4:3]), .blh(ifb1_intf[3:4]), .bhl(ifb2_intf[3:4]) ); `ifndef verilator // Backwards slicing not supported sub sub2 ( .n(2), .clk, .cyc, .alh(ifa1_intf[1:2]), // backwards vs decl .ahl(ifa2_intf[1:2]), // backwards vs decl .blh(ifb1_intf[2:1]), // backwards vs decl .bhl(ifb2_intf[2:1]) // backwards vs decl ); sub sub3 ( .n(3), .clk, .cyc, .alh(ifa1_intf[3:4]), // backwards vs decl .ahl(ifa2_intf[3:4]), // backwards vs decl .blh(ifb1_intf[4:3]), // backwards vs decl .bhl(ifb2_intf[4:3]) // backwards vs decl ); `endif always @(posedge clk) begin cyc <= cyc + 1; if (cyc == 1) begin ifa1_intf[1].index = 'h101; ifa1_intf[2].index = 'h102; ifa1_intf[3].index = 'h103; ifa1_intf[4].index = 'h104; ifa2_intf[1].index = 'h201; ifa2_intf[2].index = 'h202; ifa2_intf[3].index = 'h203; ifa2_intf[4].index = 'h204; ifb1_intf[1].index = 'h301; ifb1_intf[2].index = 'h302; ifb1_intf[3].index = 'h303; ifb1_intf[4].index = 'h304; ifb2_intf[1].index = 'h401; ifb2_intf[2].index = 'h402; ifb2_intf[3].index = 'h403; ifb2_intf[4].index = 'h404; end end endmodule module sub ( input logic clk, input int cyc, input int n, intf alh[1:2], intf ahl[2:1], intf blh[1:2], intf bhl[2:1] ); always @(posedge clk) begin if (cyc == 5) begin if (n == 0) begin `checkh(alh[1].index, 'h102); `checkh(alh[2].index, 'h101); `checkh(ahl[1].index, 'h201); `checkh(ahl[2].index, 'h202); `checkh(blh[1].index, 'h301); `checkh(blh[2].index, 'h302); `checkh(bhl[1].index, 'h402); `checkh(bhl[2].index, 'h401); end else if (n == 1) begin `checkh(alh[1].index, 'h104); `checkh(alh[2].index, 'h103); `checkh(ahl[1].index, 'h203); `checkh(ahl[2].index, 'h204); `checkh(blh[1].index, 'h303); `checkh(blh[2].index, 'h304); `checkh(bhl[1].index, 'h404); `checkh(bhl[2].index, 'h403); end else if (n == 2) begin `checkh(alh[1].index, 'h101); `checkh(alh[2].index, 'h102); `checkh(ahl[1].index, 'h202); `checkh(ahl[2].index, 'h201); `checkh(blh[1].index, 'h302); `checkh(blh[2].index, 'h301); `checkh(bhl[1].index, 'h401); `checkh(bhl[2].index, 'h402); end else if (n == 3) begin `checkh(alh[1].index, 'h103); `checkh(alh[2].index, 'h104); `checkh(ahl[1].index, 'h204); `checkh(ahl[2].index, 'h203); `checkh(blh[1].index, 'h304); `checkh(blh[2].index, 'h303); `checkh(bhl[1].index, 'h403); `checkh(bhl[2].index, 'h404); end end if (cyc == 9 && n == 0) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_unroll_nested_unroll.py0000755000542200017500000000147315101701376024243 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = 't/t_unroll_nested.v' test.golden_filename = 't/t_unroll_nested.out' test.compile(v_flags2=['+define+TEST_FULL', '--stats']) test.execute(expect_filename=test.golden_filename) test.file_grep(test.stats, r'Optimizations, Loop unrolling, Unrolled iterations\s+(\d+)', 107) test.file_grep(test.stats, r'Optimizations, Loop unrolling, Unrolled loops\s+(\d+)', 27) test.passes() verilator-5.042/test_regress/t/t_foreach_bad.out0000644000542200017500000000070115101701376022355 0ustar mahmoudyfreeshell%Error: t/t_foreach_bad.v:14:7: Foreach missing bracketed loop variable is no-operation (IEEE 1800-2023 12.7.3) 14 | foreach (array); | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_foreach_bad.v:18:23: 'foreach' loop variable expects simple variable name 18 | foreach (array[a.b]); | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_time_vpi_1ms10ns.py0000755000542200017500000000147515101701376023073 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.pli_filename = "t/t_time_vpi_c.cpp" test.top_filename = "t/t_time_vpi.v" test.main_time_multiplier = 1e-3 / 10e-9 test.compile( v_flags2=['+define+time_scale_units=1ms +define+time_scale_prec=10ns', test.pli_filename], verilator_flags2=['--vpi --trace-vcd']) test.execute(expect_filename=test.golden_filename) test.file_grep(test.trace_filename, r'timescale +10ns') test.passes() verilator-5.042/test_regress/t/t_func_twocall_noexpand.py0000755000542200017500000000103715101701376024343 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_func_twocall.v" test.compile(verilator_flags2=['-fno-expand']) test.execute() test.passes() verilator-5.042/test_regress/t/t_vlt_match_error.v0000644000542200017500000000110615101701376022770 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Ethan Sifferman. // SPDX-License-Identifier: CC0-1.0 module DECLFILENAME; logic UNUSEDSIGNAL; logic [0:1] ASCRANGE_UNDRIVEN; always_comb begin case (ASCRANGE_UNDRIVEN) 2'b0x: UNUSEDSIGNAL = 1; endcase end `ifdef T_VLT_MATCH_ERROR_1 import hi::*; `elsif T_VLT_MATCH_ERROR_2 initial $readmemh("", EC_ERROR); `elsif T_VLT_MATCH_ERROR_3 initial #1; `endif endmodule verilator-5.042/test_regress/t/t_mem_multi_io3_sc.py0000755000542200017500000000130415101701376023213 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_mem_multi_io3.cpp" test.top_filename = "t/t_mem_multi_io3.v" test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename, "--sc -fno-inline"], verilator_flags3=[]) test.passes() verilator-5.042/test_regress/t/t_gate_fdup.py0000755000542200017500000000100215101701376021715 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.lint(verilator_flags2=["--language 1364-2005"]) test.passes() verilator-5.042/test_regress/t/t_display_brace.v0000644000542200017500000000214115101701376022377 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef int unsigned ahb_addr_t; typedef int unsigned ahb_data_t; class ahb_seq_item; ahb_addr_t address; ahb_data_t data[]; function string to_string(); string result_str, data_str; result_str = $sformatf(" addr=0x%0x ", address); data_str = " data="; if (data.size() == 0) data_str = {data_str, "-"}; else if (data.size() == 1) data_str = {data_str, $sformatf("0x%0x", data[0])}; else begin data_str = {data_str, $sformatf("%0d'{", data.size())}; foreach (data[i]) data_str = {data_str, $sformatf(" 0x%0x", data[i])}; data_str = {data_str, " }"}; end result_str = {result_str, data_str}; return result_str; endfunction endclass module top; initial begin ahb_seq_item tr; tr = new(); tr.data = '{'h11, 'h22, 'h33, 'h44, 'h55, 'h66}; $display(" tr(bytes, LE) @0x10: %0s", tr.to_string()); $finish; end endmodule verilator-5.042/test_regress/t/t_sys_readmem_assoc_bad.out0000644000542200017500000000140615101701376024451 0ustar mahmoudyfreeshell%Error: t/t_sys_readmem_assoc_bad.v:13:24: $readmemb address/key must be integral (IEEE 1800-2023 21.4.1) : ... note: In instance 't' 13 | $readmemb("not", assoc_bad_key); | ^~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error-UNSUPPORTED: t/t_sys_readmem_assoc_bad.v:14:24: Unsupported: $readmemb array values must be integral : ... note: In instance 't' 14 | $readmemb("not", assoc_bad_value); | ^~~~~~~~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_unroll_automatic_task_fork.out0000644000542200017500000000266515101701376025577 0ustar mahmoudyfreeshelltask_example start: module 0, channel 0 task_example end: module 0, channel 0 task_example start: module 0, channel 1 task_example end: module 0, channel 1 task_example start: module 1, channel 0 task_example end: module 1, channel 0 task_example start: module 1, channel 1 task_example end: module 1, channel 1 *-* Test 1 Finished *-* task_example start: module 0, channel 0 task_example end: module 0, channel 0 task_example start: module 0, channel 1 task_example end: module 0, channel 1 task_example start: module 1, channel 0 task_example end: module 1, channel 0 task_example start: module 1, channel 1 task_example end: module 1, channel 1 *-* Test 2 Finished *-* task_example start: module 0, channel 0 extra statement task_example start: module 0, channel 1 extra statement task_example start: module 1, channel 0 extra statement task_example start: module 1, channel 1 extra statement task_example end: module 0, channel 0 task_example end: module 0, channel 1 task_example end: module 1, channel 0 task_example end: module 1, channel 1 *-* Test 3 Finished *-* task_example start: module 0, channel 0 task_example start: module 0, channel 1 task_example start: module 1, channel 0 task_example start: module 1, channel 1 task_example end: module 0, channel 0 task_example end: module 0, channel 1 task_example end: module 1, channel 0 task_example end: module 1, channel 1 *-* Test 4 Finished *-* *-* All Finished *-* verilator-5.042/test_regress/t/t_dist_docs_options.py0000755000542200017500000001533615101701376023524 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Primitive C++ style checker # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') Doc_Waivers = [ '+verilator+prof+threads+file+', # Deprecated '+verilator+prof+threads+start+', # Deprecated '+verilator+prof+threads+window+', # Deprecated '-clk', # Deprecated '-lineno', # Deprecated '-order-clock-delay', # Deprecated '-pp-comments', # Deprecated '-prof-threads', # Deprecated ] Test_Waivers = [ # Covered: '-G', # Covered; other text fallows option letter '-O', # Covered; other text fallows option letter '-U', # Covered; other text fallows option letter '-gdb', # Covered: no way to test, part of --gdbbt '-rr', # Not testing; not requiring rr installation # Need testing: '-fconst', # TODO breaks due to some needed V3Const steps ] Sums = {} Docs = {} Srcs = {} Tests = {} def read_sums(): for filename in test.glob_some(test.root + "/bin/*"): with open(filename, "r", encoding="latin-1") as fh: on = False lineno = 0 for line in fh: lineno += 1 line = line.rstrip() m1 = re.search(r'^\s+((-|\+)+[^ ]+)', line) m2 = re.search(r"parser.add_argument\('((-|\+)[^']+)'", line) if re.search(r'ARGUMENT SUMMARY', line): on = True elif re.search(r'=head1', line): on = False elif on and m1: opt = opt_clean(m1.group(1)) key = opt_key(opt) if test.verbose: print("A '" + opt + "' " + line) Sums[key] = filename + ":" + str(lineno) + ": " + opt elif m2: opt = opt_clean(m2.group(1)) key = opt_key(opt) if test.verbose: print("A '" + opt + "' " + line) Sums[key] = filename + ":" + str(lineno) + ": " + opt def read_docs(): for filename in test.glob_some(test.root + "/docs/guide/*.rst"): with open(filename, "r", encoding="latin-1") as fh: lineno = 0 for line in fh: lineno += 1 line = line.rstrip() m = re.search(r'option:: ((-|\+)+[^ `]+)', line) if not m: m = re.search(r':vlopt:`[^`]+ <([^>]+)>', line) if not m: m = re.search(r':vlopt:`((-|\+)+[^ `]+)', line) if m: opt = opt_clean(m.group(1)) key = opt_key(opt) if test.verbose: print("D '" + opt + "' " + line) Docs[key] = filename + ":" + str(lineno) + ": " + opt def read_srcs(): filename = "bin/verilator --debug-options" opts = test.run_capture("perl " + os.environ["VERILATOR_ROOT"] + "/bin/verilator" + " --debug-options 2>&1") lineno = 0 for line in opts.split("\n"): lineno += 1 m1 = re.search(r'OPTION: "([^"]+)"', line) if m1: opt = opt_clean(m1.group(1)) key = opt_key(opt) if re.match(r'-Werror-[A-Z ]', opt): continue if re.match(r'-Wno-[A-Z ]', opt): continue if re.match(r'-Wwarn-[A-Z ]', opt): continue if test.verbose: print("S '" + opt + "' " + line) Srcs[key] = filename + ":" + str(lineno) + ": " + opt if len(Srcs) < 5: test.error("Didn't parse any options") return Srcs def read_tests(): filename = "test_regress/t/*.py" for filename in (test.glob_some(test.root + "/test_regress/t/*.py")): if "t_dist_docs_options" in filename: # Avoid our own suppressions continue with open(filename, 'r', encoding="latin-1") as fh: lineno = 0 for line in fh: lineno += 1 line = line.lstrip().rstrip() for opt in re.findall(r'[-+]+[-+a-zA-Z0-9]+', line): opt = opt_clean(opt) key = opt_key(opt) if test.verbose: print("T '" + opt + "' " + line) Tests[key] = filename + ":" + str(lineno) + ": " + opt # For e.g. +verilator+seed+ and -dumpi-<#> pos = max(opt.rfind('+'), opt.rfind('-')) if pos > 1: subkey = opt[:pos + 1] if test.verbose: print("t '" + subkey + "' " + line) Tests[subkey] = filename + ":" + str(lineno) + ": " + opt def opt_clean(opt): opt = re.sub(r'--', '-', opt) opt = re.sub(r'<.*', '', opt) opt = re.sub(r'\\', '', opt) return opt def opt_key(opt): opt = opt_clean(opt) opt = re.sub(r'^-fno-', '-f', opt) opt = re.sub(r'^-no-', '-', opt) return opt if not os.path.exists(test.root + "/.git"): test.skip("Not in a git repository") read_sums() read_docs() read_srcs() read_tests() both = {} both.update(Sums) both.update(Docs) both.update(Srcs) doc_waiver = {k: 1 for k in Doc_Waivers} for opt in sorted(both.keys()): if opt in doc_waiver: continue is_in = [] not_in = [] summ = None if opt in Sums: summ = Sums[opt] is_in.append("summary " + summ) else: if not re.match(r'-f', opt): not_in.append("ARGUMENT SUMMARY in bin/verilator or bin/verilator_coverage") doc = None if opt in Docs: doc = Docs[opt] is_in.append("documentation " + doc) else: not_in.append("documentation in docs/guide/exe_*.rst") src = None if opt in Srcs: src = Srcs[opt] is_in.append("sources " + src) # Ok if not in sources if opt in Tests: if opt in Test_Waivers: print("Unnecessary Test_Waiver for option: '" + opt + "'") else: if opt in Test_Waivers: is_in.append("Test_Waiver for test_regress/t/*.py") else: not_in.append("uncovered in test_regress/t/*.py") if not_in: test.error_keep_going("Option '" + opt + "' has inconsistent references\n" + " Missing in " + "\n Missing in ".join(not_in) + "\n Found in " + "\n Found in ".join(is_in)) test.passes() verilator-5.042/test_regress/t/t_hier_block_cmake/0000755000542200017500000000000015101701376022652 5ustar mahmoudyfreeshellverilator-5.042/test_regress/t/t_hier_block_cmake/main.cpp0000644000542200017500000000216515101701376024306 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2020 by Yutetsu TAKATSUKASA. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include #include "Vt_hier_block.h" int main(int argc, char *argv[]) { const std::unique_ptr contextp{new VerilatedContext}; // TEST_THREADS is set in t_hier_block_cmake.py contextp->threads(TEST_THREADS); contextp->commandArgs(argc, argv); std::unique_ptr top{new Vt_hier_block{contextp.get(), "top"}}; for (int i = 0; i < 100 && !contextp->gotFinish(); ++i) { top->eval(); top->clk ^= 1; } if (!contextp->gotFinish()) { vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); } top->final(); return 0; } verilator-5.042/test_regress/t/t_hier_block_cmake/CMakeLists.txt0000644000542200017500000000174215101701376025416 0ustar mahmoudyfreeshell###################################################################### # # DESCRIPTION: CMake script for t_hier_block_cmake # # Copyright 2003-2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ###################################################################### cmake_minimum_required(VERSION 3.12) cmake_policy(SET CMP0074 NEW) project (t_hier_block_cmake) find_package(verilator REQUIRED) add_executable(t_hier_block_cmake main.cpp ../t_hier_block.cpp) if(TEST_THREADS) set(VERILATOR_OPTIONS "${VERILATOR_OPTIONS}" --threads ${TEST_THREADS}) endif() set(VERILATOR_OPTIONS "${VERILATOR_OPTIONS}" --hierarchical --stats --CFLAGS "-pipe -DCPP_MACRO=cplusplus") verilate(t_hier_block_cmake VERILATOR_ARGS ${VERILATOR_OPTIONS} SOURCES ../t_hier_block.v ) verilator-5.042/test_regress/t/t_unpacked_array_order.v0000644000542200017500000000160315101701376023763 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Duraid Madina. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; parameter logic [1:0] t0 [ 2][ 2] = '{'{2'd0, 2'd1}, '{2'd2, 2'd3}}; parameter logic [1:0] t1 [0:1][0:1] = '{'{2'd0, 2'd1}, '{2'd2, 2'd3}}; parameter logic [1:0] t2 [1:0][1:0] = '{'{2'd3, 2'd2}, '{2'd1, 2'd0}}; always @ (posedge clk) begin if (t0[0][0] != t1[0][0]) $stop; if (t0[0][1] != t1[0][1]) $stop; if (t0[1][0] != t1[1][0]) $stop; if (t0[1][1] != t1[1][1]) $stop; if (t0[0][0] != t2[0][0]) $stop; if (t0[0][1] != t2[0][1]) $stop; if (t0[1][0] != t2[1][0]) $stop; if (t0[1][1] != t2[1][1]) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_let_unsup.py0000755000542200017500000000076615101701376022015 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_preproc_ttempty.v0000644000542200017500000000043115101701376023036 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 //`define TARGET_PACKAGE `define TARGET_PACKAGE_```TARGET_PACKAGE verilator-5.042/test_regress/t/t_event_control_pass.v0000644000542200017500000000152515101701376023512 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class Bar; event evt; task automatic wait_for_event(); @evt; endtask function automatic event get_event(); return evt; endfunction endclass class Foo; task automatic send_event(Bar b); ->b.get_event(); endtask endclass bit got_event; module t(); initial begin Bar bar; Foo foo; foo = new; bar = new; got_event = 0; fork begin bar.wait_for_event(); $display("Got the event!"); got_event = 1; end #10 foo.send_event(bar); join #99; if (!got_event) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_trace_fst.py0000755000542200017500000000106115101701376021736 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(v_flags2=["--trace-fst"]) test.execute() test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dynarray_bad.py0000755000542200017500000000076615101701376022436 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_constraint_operators.v0000644000542200017500000000556015101701376024070 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Packet; rand int x; rand bit [31:0] b; rand bit [31:0] c; rand bit [31:0] d; rand bit tiny; rand bit zero; rand bit one; rand int out0, out1, out2, out3, out4, out5, out6; bit state; typedef bit signed [63:0] s64; typedef bit [63:0] u64; constraint arith { x + x - x == x; } constraint divmod { int'((x % 5) / 2) != (b % 99) / 7; } constraint mul { x * 9 != b * 3; } constraint impl { tiny == 1 -> x != 10; } constraint concat { {c, b} != 'h1111; } constraint unary { !(-~c == 'h22); } constraint log { ((b ^ c) & (b >>> c | b >> c | b << c)) > 0; } constraint cmps { x < x || x <= x || x > x || x >= x; } constraint cmpu { b < b || b <= b || b > b || b >= b; } constraint ext { s64'(x) != u64'(tiny); } constraint cond { (tiny == 1 ? b : c) != 17; } constraint zero_c { zero == 0; } constraint one_c { one == 1; } constraint sel { d[15:8] == 8'h55; } constraint ifelse { if (one) out0 == 'h333; if (!one) tiny != tiny; else out1 == 'h333; if (one == 1) out2 == 'h333; else tiny != tiny; if (0) tiny != tiny; else out3 == 'h333; if (1) out4 == 'h333; else tiny != tiny; if (one == 1) if (1) { out5 == 'h333; out5 == 'h333; out5 == 'h333; } else tiny != tiny; else if (1) tiny != tiny; else { tiny != tiny; } if (1) if (one == 1) { out6 == 'h333; out6 == 'h333; out6 == 'h333; } else tiny != tiny; else if (one == 1) tiny != tiny; else { tiny != tiny; } if (one && zero) tiny != tiny; if (~one && zero) tiny != tiny; if (zero || (one & zero)) tiny != tiny; if (zero && (one | zero)) tiny != tiny; } endclass module t; Packet p; int v; initial begin p = new; v = p.randomize(); if (v != 1) $stop; if ((p.x % 5) / 2 == (p.b % 99) / 7) $stop; if (p.x * 9 == p.b * 3) $stop; if (p.tiny && p.x == 10) $stop; if ({p.c, p.b} == 'h1111) $stop; if (-~p.c == 'h22) $stop; if (((p.b ^ p.c) & (p.b >>> p.c | p.b >> p.c | p.b << p.c)) <= 0) $stop; if (p.x == int'(p.tiny)) $stop; if ((p.tiny == 1 ? p.b : p.c) == 17) $stop; if ((p.tiny == 1 ? p.b : p.c) == 17) $stop; if (p.zero != 0) $stop; if (p.one != 1) $stop; if (p.out0 != 'h333) $stop; if (p.out1 != 'h333) $stop; if (p.out2 != 'h333) $stop; if (p.out3 != 'h333) $stop; if (p.out4 != 'h333) $stop; if (p.out5 != 'h333) $stop; if (p.out6 != 'h333) $stop; if (p.d[15:8] != 'h55) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_lint_latch_7.py0000755000542200017500000000070315101701376022335 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint() test.passes() verilator-5.042/test_regress/t/t_interface_array_bad.out0000644000542200017500000000113315101701376024104 0ustar mahmoudyfreeshell%Error: t/t_interface_array_bad.v:23:16: Expecting expression to be constant, but variable isn't const: 'bar' : ... note: In instance 't' 23 | assign foos[bar].a = 1'b1; | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_interface_array_bad.v:23:15: Could not expand constant selection inside dotted reference: 'bar' : ... note: In instance 't' 23 | assign foos[bar].a = 1'b1; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_typedef_array.py0000755000542200017500000000073415101701376022630 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_sys_readmem_assoc__w_h.mem.out0000644000542200017500000000034715101701376025417 0ustar mahmoudyfreeshell000000000000000000000002 000000000000000000000003 000000000000000000000004 000000000000000000000005 000000000000000000000006 000000000000000000000007 @8 000000000000000000000010 @c 000000000000000000000014 000000000000000000000015 verilator-5.042/test_regress/t/t_nba_mixed_update_comb.py0000755000542200017500000000164715101701376024266 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(verilator_flags2=["--stats", "--unroll-count", "1"]) test.execute() test.file_grep(test.stats, r'NBA, variables using ShadowVar scheme\s+(\d+)', 1) test.file_grep(test.stats, r'NBA, variables using ShadowVarMasked scheme\s+(\d+)', 2) test.file_grep(test.stats, r'NBA, variables using FlagUnique scheme\s+(\d+)', 1) test.file_grep(test.stats, r'Optimizations, Loop unrolling, Unrolled loops\s+(\d+)', 0) test.file_grep(test.stats, r'Warnings, Suppressed BLKANDNBLK\s+(\d+)', 2) test.passes() verilator-5.042/test_regress/t/t_dpi_instr_count_large.v0000644000542200017500000000116015101701376024153 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(clk); input clk; sub_0 sub_0(clk); sub_1 sub_1(clk); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule import "DPI-C" context function void dpii_call(); module sub_0(input clk); /*verilator hier_block*/ always @(posedge clk) dpii_call(); endmodule module sub_1(input clk); /*verilator hier_block*/ always @(posedge clk) dpii_call(); endmodule verilator-5.042/test_regress/t/t_class_typedef.v0000644000542200017500000000216515101701376022431 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class uvm_resource_types; typedef int rsrc_q_t; endclass class uvm_resource_pool; uvm_resource_types::rsrc_q_t rtab [string]; endclass virtual class C#(parameter type T = logic, parameter SIZE = 1); typedef logic [SIZE-1:0] t_vector; typedef T t_array [SIZE-1:0]; typedef struct { t_vector m0 [2*SIZE-1:0]; t_array m1; } t_struct; endclass module t; initial begin uvm_resource_pool pool = new; typedef logic [7:0] t_t0; C#(t_t0,3)::t_vector v0; C#(t_t0,3)::t_array a0; C#(bit,4)::t_struct s0; pool.rtab["a"] = 1; if ($bits(pool.rtab["a"]) != 32) $stop; if ($bits(v0) != 3) $stop; if ($size(a0) != 3) $stop; if ($bits(a0[0]) != 8) $stop; if ($size(s0.m0) != 8) $stop; if ($size(s0.m1) != 4) $stop; if ($bits(s0.m1[2]) != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_sys_readmem_bad_end.v0000644000542200017500000000105315101701376023543 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg [175:0] hex [15:0]; integer i; initial begin // No warning as has addresses $readmemh("t/t_sys_readmem_bad_end2.mem", hex, 0, 15); // Warning as wrong end address $readmemh("t/t_sys_readmem_bad_end.mem", hex, 0, 15); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_typedef_id_bad.out0000644000542200017500000000042215101701376023062 0ustar mahmoudyfreeshell%Error: t/t_typedef_id_bad.v:9:34: Expecting a data type: 'i' 9 | class Cls #(parameter type P_T = i); | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_dedupe_clk_gate.py0000755000542200017500000000161315101701376023066 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') out_filename = test.obj_dir + "/V" + test.name + ".tree.json" test.compile(verilator_flags2=["--no-json-edit-nums", "--stats"]) if test.vlt_all: test.file_grep( out_filename, r'{"type":"VAR","name":"t.f0.clock_gate.clken_latched","addr":"[^"]*","loc":"\w,44:[^"]*","dtypep":"\(\w+\)",.*"origName":"clken_latched",.*"isLatched":true,.*"dtypeName":"logic"' ) test.file_grep(test.stats, r'Optimizations, Gate sigs deduped\s+(\d+)', 4) test.passes() verilator-5.042/test_regress/t/t_while_finish.py0000755000542200017500000000077115101701376022443 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--binary']) test.execute() test.passes() verilator-5.042/test_regress/t/t_cover_main.v0000644000542200017500000000047215101701376021725 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_flag_make_bad.out0000644000542200017500000000025715101701376022662 0ustar mahmoudyfreeshell%Error: Unknown --make system specified: 'bad_one' ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_delay_compare.v0000644000542200017500000000141115101701376022401 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; int tim1; int tim2; real rtim1; real rtim2; initial begin tim1 = 2; tim2 = 3; // verilator lint_off WIDTHEXPAND # (tim1 < tim2); // verilator lint_on WIDTHEXPAND if ($time != 1) $stop; // verilator lint_off WIDTHEXPAND # (tim1); // verilator lint_on WIDTHEXPAND if ($time != 1 + 2) $stop; rtim1 = 2; rtim2 = 2.6; # (rtim1 + rtim2); // Rounds up if ($time != 1 + 2 + 5) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_enum_large_methods.py0000755000542200017500000000073415101701376023633 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_randomize_union.v0000755000542200017500000001425715101701376023014 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by PlanV GmbH. // SPDX-License-Identifier: CC0-1.0 typedef union packed { int int_value; bit [31:0] bits; } SimpleUnion; typedef struct packed { rand bit [3:0] field_a; rand bit [7:0] field_b; } PackedStruct; typedef union packed { PackedStruct struct_fields; bit [11:0] inner_bits; } StructInUnion; typedef union packed { StructInUnion inner_union; bit [11:0] outer_bits; } UnionInUnion; // SimpleUnion Constrained Test Class class SimpleUnionConstrainedTest; rand SimpleUnion union_instance; function new(); union_instance.bits = 32'b0; endfunction constraint union_constraint { union_instance.bits[11:0] inside {[0:4095]}; } endclass // SimpleUnion Unconstrained Test Class class SimpleUnionUnconstrainedTest; rand SimpleUnion union_instance; function new(); union_instance.bits = 32'b0; endfunction endclass // StructInUnion Constrained Test Class class StructInUnionConstrainedTest; rand StructInUnion union_instance; function new(); union_instance.inner_bits = 12'b0; endfunction constraint union_constraint { union_instance.inner_bits inside {[0:4095]}; } endclass // StructInUnion Unconstrained Test Class class StructInUnionUnconstrainedTest; rand StructInUnion union_instance; function new(); union_instance.inner_bits = 12'b0; endfunction endclass // UnionInUnion Constrained Test Class class UnionInUnionConstrainedTest; rand UnionInUnion union_instance; function new(); union_instance.outer_bits = 12'b0; endfunction constraint union_constraint { union_instance.outer_bits inside {[0:4095]}; } endclass // UnionInUnion Unconstrained Test Class class UnionInUnionUnconstrainedTest; rand UnionInUnion union_instance; function new(); union_instance.outer_bits = 12'b0; endfunction endclass // Top-Level Test Module module t_randomize_union; // Instances of each test class SimpleUnionConstrainedTest test_simple_union_constrained; SimpleUnionUnconstrainedTest test_simple_union_unconstrained; StructInUnionConstrainedTest test_struct_in_union_constrained; StructInUnionUnconstrainedTest test_struct_in_union_unconstrained; UnionInUnionConstrainedTest test_union_in_union_constrained; UnionInUnionUnconstrainedTest test_union_in_union_unconstrained; initial begin // Test 1: SimpleUnion Constrained Test test_simple_union_constrained = new(); $display("\n--- Test 1: SimpleUnion Constrained Test ---"); repeat(10) begin int success; success = test_simple_union_constrained.randomize(); if (success != 1) $stop; $display("SimpleUnion (Constrained): int_value: %b, bits: %b", test_simple_union_constrained.union_instance.int_value, test_simple_union_constrained.union_instance.bits); end // Test 2: SimpleUnion Unconstrained Test test_simple_union_unconstrained = new(); $display("\n--- Test 2: SimpleUnion Unconstrained Test ---"); repeat(10) begin int success; success = test_simple_union_unconstrained.randomize(); if (success != 1) $stop; $display("SimpleUnion (Unconstrained): int_value: %b, bits: %b", test_simple_union_unconstrained.union_instance.int_value, test_simple_union_unconstrained.union_instance.bits); end // Test 3: StructInUnion Constrained Test test_struct_in_union_constrained = new(); $display("\n--- Test 3: StructInUnion Constrained Test ---"); repeat(10) begin int success; success = test_struct_in_union_constrained.randomize(); if (success != 1) $stop; $display("StructInUnion (Constrained): struct.a: %b, struct.b: %b, inner_bits: %b", test_struct_in_union_constrained.union_instance.struct_fields.field_a, test_struct_in_union_constrained.union_instance.struct_fields.field_b, test_struct_in_union_constrained.union_instance.inner_bits); end // Test 4: StructInUnion Unconstrained Test test_struct_in_union_unconstrained = new(); $display("\n--- Test 4: StructInUnion Unconstrained Test ---"); repeat(10) begin int success; success = test_struct_in_union_unconstrained.randomize(); if (success != 1) $stop; $display("StructInUnion (Unconstrained): struct.a: %b, struct.b: %b, inner_bits: %b", test_struct_in_union_unconstrained.union_instance.struct_fields.field_a, test_struct_in_union_unconstrained.union_instance.struct_fields.field_b, test_struct_in_union_unconstrained.union_instance.inner_bits); end // Test 5: UnionInUnion Constrained Test test_union_in_union_constrained = new(); $display("\n--- Test 5: UnionInUnion Constrained Test ---"); repeat(10) begin int success; success = test_union_in_union_constrained.randomize(); if (success != 1) $stop; $display("UnionInUnion (Constrained): outer_bits: %b, inner_union.struct: %b, b: %b", test_union_in_union_constrained.union_instance.outer_bits, test_union_in_union_constrained.union_instance.inner_union.struct_fields.field_a, test_union_in_union_constrained.union_instance.inner_union.struct_fields.field_b); end // Test 6: UnionInUnion Unconstrained Test test_union_in_union_unconstrained = new(); $display("\n--- Test 6: UnionInUnion Unconstrained Test ---"); repeat(10) begin int success; success = test_union_in_union_unconstrained.randomize(); if (success != 1) $stop; $display("UnionInUnion (Unconstrained): outer_bits: %b, inner_union.struct: %b, inner_union.inner_bits: %b", test_union_in_union_unconstrained.union_instance.outer_bits, test_union_in_union_unconstrained.union_instance.inner_union.struct_fields, test_union_in_union_unconstrained.union_instance.inner_union.inner_bits); end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_assign_automatic_bad.out0000644000542200017500000000434215101701376024305 0ustar mahmoudyfreeshell%Error: t/t_assign_automatic_bad.v:35:10: Dynamically-sized variable not allowed in continuous assignment (IEEE 1800-2023 6.21): 'bad_dyn5' : ... note: In instance 't' 35 | assign bad_dyn5[0] = empty_dyn; | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_assign_automatic_bad.v:37:12: Automatic lifetime variable not allowed in continuous assignment (IEEE 1800-2023 6.21): 'm_bad1' : ... note: In instance 't' 37 | assign c.m_bad1 = 2; | ^~~~~~ %Error: t/t_assign_automatic_bad.v:47:5: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 'bad_dyn6' : ... note: In instance 't' 47 | bad_dyn6[0] <= 2; | ^~~~~~~~ %Error: t/t_assign_automatic_bad.v:49:5: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 'bad_queue' : ... note: In instance 't' 49 | bad_queue[0] <= 2; | ^~~~~~~~~ %Error: t/t_assign_automatic_bad.v:51:5: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 'bad_assoc' : ... note: In instance 't' 51 | bad_assoc[0] <= 2; | ^~~~~~~~~ %Error: t/t_assign_automatic_bad.v:54:7: Automatic lifetime variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 'm_bad2' : ... note: In instance 't' 54 | c.m_bad2 <= 2; | ^~~~~~ %Error: t/t_assign_automatic_bad.v:56:10: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 's_dyn' : ... note: In instance 't' 56 | Cls::s_dyn[0] <= 2; | ^~~~~ %Error: t/t_assign_automatic_bad.v:58:26: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 's_dyn' : ... note: In instance 't' 58 | clist[bad_dyn6[0]++].s_dyn[0] <= '1; | ^~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_preproc_cmtend_bad.v0000644000542200017500000000034215101701376023411 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 /*Blah blah verilator-5.042/test_regress/t/t_case_wild.v0000644000542200017500000000632415101701376021537 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc = 0; reg [63:0] crc; reg [63:0] sum; reg out1; reg [4:0] out2; sub sub (.in(crc[23:0]), .out1(out1), .out2(out2)); always @ (posedge clk) begin //$write("[%0t] cyc==%0d crc=%x sum=%x out=%x,%x\n", $time, cyc, crc, sum, out1,out2); cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {58'h0,out1,out2}; if (cyc==0) begin // Setup crc <= 64'h00000000_00000097; sum <= 64'h0; end else if (cyc==90) begin if (sum !== 64'hf0afc2bfa78277c5) $stop; end else if (cyc==91) begin end else if (cyc==92) begin end else if (cyc==93) begin end else if (cyc==94) begin end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module sub (/*AUTOARG*/ // Outputs out1, out2, // Inputs in ); input [23:0] in; output reg out1; output reg [4:0] out2; always @* begin casez (in) 24'b0000_0000_0000_0000_0000_0000 : {out1,out2} = {1'b0,5'h00}; 24'b????_????_????_????_????_???1 : {out1,out2} = {1'b1,5'h00}; 24'b????_????_????_????_????_??10 : {out1,out2} = {1'b1,5'h01}; 24'b????_????_????_????_????_?100 : {out1,out2} = {1'b1,5'h02}; 24'b????_????_????_????_????_1000 : {out1,out2} = {1'b1,5'h03}; 24'b????_????_????_????_???1_0000 : {out1,out2} = {1'b1,5'h04}; 24'b????_????_????_????_??10_0000 : {out1,out2} = {1'b1,5'h05}; 24'b????_????_????_????_?100_0000 : {out1,out2} = {1'b1,5'h06}; 24'b????_????_????_????_1000_0000 : {out1,out2} = {1'b1,5'h07}; // Same pattern, but reversed to test we work OK. 24'b1000_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h17}; 24'b?100_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h16}; 24'b??10_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h15}; 24'b???1_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h14}; 24'b????_1000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h13}; 24'b????_?100_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h12}; 24'b????_??10_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h11}; 24'b????_???1_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h10}; 24'b????_????_1000_0000_0000_0000 : {out1,out2} = {1'b1,5'h0f}; 24'b????_????_?100_0000_0000_0000 : {out1,out2} = {1'b1,5'h0e}; 24'b????_????_??10_0000_0000_0000 : {out1,out2} = {1'b1,5'h0d}; 24'b????_????_???1_0000_0000_0000 : {out1,out2} = {1'b1,5'h0c}; 24'b????_????_????_1000_0000_0000 : {out1,out2} = {1'b1,5'h0b}; 24'b????_????_????_?100_0000_0000 : {out1,out2} = {1'b1,5'h0a}; 24'b????_????_????_??10_0000_0000 : {out1,out2} = {1'b1,5'h09}; 24'b????_????_????_???1_0000_0000 : {out1,out2} = {1'b1,5'h08}; endcase end endmodule verilator-5.042/test_regress/t/t_constraint_unsup.v0000644000542200017500000000061515101701376023220 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Packet; rand int m_one; constraint cons { $onehot(m_one) == 1; } endclass module t; Packet p; initial begin p = new; void'(p.randomize()); end endmodule verilator-5.042/test_regress/t/t_real_param.v0000644000542200017500000000155615101701376021712 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 module foo #( parameter real BAR = 2.0) (); endmodule module t(); genvar m, r; generate for (m = 10; m <= 20; m+=10) begin : gen_m for (r = 0; r <= 1; r++) begin : gen_r localparam real LPARAM = m + (r + 0.5); initial begin if (LPARAM != foo_inst.BAR) begin $display("%m: LPARAM != foo_inst.BAR (%f, %f)", LPARAM, foo_inst.BAR); $stop(); end end foo #(.BAR (LPARAM)) foo_inst (); end end endgenerate initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_castdyn_enum.v0000644000542200017500000000275615101701376022303 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef enum {TEN=10, ELEVEN=11, SIXTEEN=16} enum_t; module t (/*AUTOARG*/ // Inputs clk ); input clk; int i; int i_const; int cyc; enum_t en; // Constant propagation tests initial begin en = SIXTEEN; i_const = $cast(en, 1); if (i_const != 0) $stop; if (en != SIXTEEN) $stop; en = SIXTEEN; i_const = $cast(en, 10); if (i_const != 1) $stop; if (en != TEN) $stop; end // Test loop always @ (posedge clk) begin i = $cast(en, cyc); `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d i=%0d en=%0d\n", $time, cyc, i, en); `endif cyc <= cyc + 1; if (cyc == 10) begin if (i != 1) $stop; if (en != TEN) $stop; end else if (cyc == 11) begin if (i != 1) $stop; if (en != ELEVEN) $stop; end else if (cyc == 12) begin if (i != 0) $stop; if (en != ELEVEN) $stop; end else if (cyc == 16) begin if (i != 1) $stop; if (en != SIXTEEN) $stop; end else if (cyc == 17) begin if (i != 0) $stop; if (en != SIXTEEN) $stop; end else if (cyc == 99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_assoc_nokey_bad.out0000644000542200017500000000111515101701376023263 0ustar mahmoudyfreeshell%Error: t/t_assoc_nokey_bad.v:12:28: Missing pattern key (need an expression then a ':') : ... note: In instance 't' 12 | int dict[string] = '{1, 2}; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_assoc_nokey_bad.v:12:31: Missing pattern key (need an expression then a ':') : ... note: In instance 't' 12 | int dict[string] = '{1, 2}; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_param_no_parentheses.v0000644000542200017500000000303715101701376024000 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // // This is a copy of t_param.v with the parentheses around the module parameters // removed. module t (/*AUTOARG*/ // Inputs clk ); parameter PAR = 3; m1 #PAR m1(); m3 #PAR m3(); mnooverride #10 mno(); input clk; integer cyc=1; reg [4:0] bitsel; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==0) begin bitsel = 0; if (PAR[bitsel]!==1'b1) $stop; bitsel = 1; if (PAR[bitsel]!==1'b1) $stop; bitsel = 2; if (PAR[bitsel]!==1'b0) $stop; end if (cyc==1) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module m1; localparam PAR1MINUS1 = PAR1DUP-2-1; localparam PAR1DUP = PAR1+2; // Check we propagate parameters properly parameter PAR1 = 0; m2 #PAR1MINUS1 m2 (); endmodule module m2; parameter PAR2 = 10; initial begin $display("%x",PAR2); if (PAR2 !== 2) $stop; end endmodule module m3; localparam LOC = 13; parameter PAR = 10; initial begin $display("%x %x",LOC,PAR); if (LOC !== 13) $stop; if (PAR !== 3) $stop; end endmodule module mnooverride; localparam LOC = 13; parameter PAR = 10; initial begin $display("%x %x",LOC,PAR); if (LOC !== 13) $stop; if (PAR !== 10) $stop; end endmodule verilator-5.042/test_regress/t/t_inst_nansi_mism_bad.v0000644000542200017500000000124215101701376023577 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef int T; module test ( /*AUTOARG*/ // Outputs bad1, bad2, bad3, bad4 ); output [15:0] bad1; shortint bad1; // <--- Error (type doesn't match above) output [31:0] bad2; T bad2; // <--- Error (type doesn't match above due to range) output [3:0] bad3; reg [7:0] bad3; // <--- Error (range doesn't match) (output-before-reg) reg [7:0] bad4; // <--- Error (range doesn't match) (reg-before-output) output [3:0] bad4; endmodule verilator-5.042/test_regress/t/t_trace_param_override.out0000644000542200017500000000041515101701376024317 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module t $end $var wire 32 # POVERRODE [31:0] $end $var wire 32 $ PORIG [31:0] $end $upscope $end $enddefinitions $end #0 b00000000000000000000000000011111 # b00000000000000000000000000010000 $ verilator-5.042/test_regress/t/t_wired_net_test.py0000755000542200017500000000073415101701376023011 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_timing_reentry.py0000755000542200017500000000077115101701376023032 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_gen2_collision.py0000755000542200017500000000105515101701376024715 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_gen2.v" test.compile(verilator_flags2=["--debug-collision"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_alias_simple.v0000644000542200017500000000150515101701376022243 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ // Inputs clk ); input clk; wire [31:0] a, b; wire [31:0] x, y; integer cyc = 0; alias a = b; assign a = cyc; alias x = y; assign x[15:0] = cyc[15:0]; assign y[31:16] = cyc[31:16]; sub s (cyc); always @(posedge clk) begin cyc <= cyc + 1; if (a != cyc) $stop; if (b != cyc) $stop; if (x != cyc) $stop; if (y != cyc) $stop; if (s.a != cyc) $stop; if (s.b != cyc) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module sub ( input integer cyc ); wire [31:0] a, b; assign a = cyc; alias a = b; endmodule verilator-5.042/test_regress/t/t_string_to_bit.v0000644000542200017500000000564515101701376022460 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=\"%s\" exp=\"%s\"\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; string str0; string str1; string str2; typedef bit [31:0] bit_t; typedef logic [31:0] logic_t; typedef bit [55:0] quad_t; typedef bit [87:0] wide_t; bit_t bdata[3]; bit_t ldata[3]; quad_t qdata[3]; wide_t wdata[3]; initial begin str0 = "sm"; str1 = "medium"; str2 = "veryverylongwilltruncate"; bdata[0] = bit_t'(str0); bdata[1] = bit_t'(str1); bdata[2] = bit_t'(str2); `checks(bdata[0], "sm"); `checks(bdata[1], "dium"); `checks(bdata[2], "cate"); if (bdata[0] != 32'h0000736d) $stop; if (bdata[1] != 32'h6469756d) $stop; ldata[0] = logic_t'(str0); ldata[1] = logic_t'(str1); ldata[2] = logic_t'(str2); `checks(ldata[0], "sm"); `checks(ldata[1], "dium"); `checks(ldata[2], "cate"); qdata[0] = quad_t'(str0); qdata[1] = quad_t'(str1); qdata[2] = quad_t'(str2); `checks(qdata[0], "sm"); `checks(qdata[1], "medium"); `checks(qdata[2], "runcate"); wdata[0] = wide_t'(str0); wdata[1] = wide_t'(str1); wdata[2] = wide_t'(str2); `checks(wdata[0], "sm"); `checks(wdata[1], "medium"); `checks(wdata[2], "illtruncate"); end // Test loop always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 1) begin str0 = "z"; str1 = "zmedi"; str2 = "ziggylonglonglongtruncate"; end else if (cyc == 2) begin bdata[0] = bit_t'(str0); bdata[1] = bit_t'(str1); bdata[2] = bit_t'(str2); ldata[0] = logic_t'(str0); ldata[1] = logic_t'(str1); ldata[2] = logic_t'(str2); qdata[0] = quad_t'(str0); qdata[1] = quad_t'(str1); qdata[2] = quad_t'(str2); wdata[0] = wide_t'(str0); wdata[1] = wide_t'(str1); wdata[2] = wide_t'(str2); end else if (cyc == 3) begin `checks(bdata[0], "z"); `checks(bdata[1], "medi"); `checks(bdata[2], "cate"); `checks(ldata[0], "z"); `checks(ldata[1], "medi"); `checks(ldata[2], "cate"); `checks(qdata[0], "z"); `checks(qdata[1], "zmedi"); `checks(qdata[2], "runcate"); `checks(wdata[0], "z"); `checks(wdata[1], "zmedi"); `checks(wdata[2], "ongtruncate"); end // else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_math_swap.py0000755000542200017500000000073415101701376021755 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_procassinit_bad.v0000644000542200017500000000204715101701376023775 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ // Inputs clk, reset_l, in, enable ); input clk; input reset_l; input in; input enable; logic ok1 = 1; logic ok2 = 1; logic ok3 = ok2; initial begin ok1 = 1; end //== Faulty example logic flop_out = 1; // <--- Warning always @(posedge clk, negedge reset_l) begin if (enable) begin flop_out <= ~in; // <--- Use of initialized end end //== Fixed example logic flop2_out; always @(posedge clk, negedge reset_l) begin if (!reset_l) begin flop2_out <= '1; // <--- Added reset init end else if (enable) begin flop2_out <= ~in; end end // Combo version logic bad_comb = 1; // but this is not fine always @* begin bad_comb = ok2; end wire _unused_ok = &{1'b0, flop_out, flop2_out, bad_comb, ok1, ok2, ok3}; endmodule verilator-5.042/test_regress/t/t_class_new_typed.py0000755000542200017500000000073415101701376023155 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_inst_misarray_bad.v0000644000542200017500000000144215101701376023273 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; logic foo; initial foo = 0; // dut #(.W(4)) udut(.*); dut #(.W(4)) udut(.clk(clk), .foo(foo)); // Assigning logic to logic array endmodule module dut #(parameter W = 1) (input logic clk, input logic foo[W-1:0]); genvar i; generate for (i = 0; i < W; i++) begin suba ua(.clk(clk), .foo(foo[i])); end endgenerate endmodule module suba (input logic clk, input logic foo); always @(posedge clk) $display("foo=%b", foo); endmodule verilator-5.042/test_regress/t/t_param_type4.v0000644000542200017500000000201515101701376022023 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); input clk; wire o0, o1; sub #(1) a(.i(1'b0), .o(o0)); sub #(2) b(.i(1'b0), .o(o1)); always @(posedge clk) begin if (o0 != 1'b0) begin $write("Bad o0\n"); $stop; end if (o1 != 1'b1) begin $write("Bad o1\n"); $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule module sub #( parameter int W ) ( input wire i, output wire o ); typedef struct packed { logic [W-1:0] a; } s; sub2 #(s) c(.i(i), .o(o)); endmodule module sub2 # ( parameter type T = logic ) ( input wire i, output wire o ); if ($bits(T) % 2 == 1) begin assign o = i; end else begin assign o = ~i; end endmodule verilator-5.042/test_regress/t/t_flag_timescale.out0000644000542200017500000000013015101701376023073 0ustar mahmoudyfreeshellt: Time scale of t is 1ms / 1us sub: Time scale of sub is 1s / 1us *-* All Finished *-* verilator-5.042/test_regress/t/t_assert_basic.py0000755000542200017500000000102015101701376022421 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--assert'], nc_flags2=['+assert']) test.execute() test.passes() verilator-5.042/test_regress/t/t_vpi_module_empty.v0000644000542200017500000000115115101701376023157 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2023 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 interface sv_if(); logic a /*verilator public_flat_rw*/; endinterface module top (); sv_if sv_if_i(); // Workaround for bug3937: // logic d /*verilator public_flat_rw*/; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_trace_complex_params_fst_sc.py0000755000542200017500000000131015101701376025512 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_complex.v" if not test.have_sc: test.skip("No SystemC installed") test.compile(verilator_flags2=['--sc --trace-fst --no-trace-structs --trace-params']) test.execute() test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_waitconst_bad.py0000755000542200017500000000107315101701376023636 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_timing_wait1.v" test.lint(verilator_flags2=["--timing"], expect_filename=test.golden_filename, fails=True) test.passes() verilator-5.042/test_regress/t/t_trace_cat_renew__0000.out0000644000542200017500000000526115101701376024071 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $var wire 1 # clk $end $scope module t $end $var wire 1 # clk $end $var wire 32 $ cyc [31:0] $end $upscope $end $upscope $end $enddefinitions $end #0 1# b00000000000000000000000000000000 $ #1 0# #2 1# b00000000000000000000000000000001 $ #3 0# #4 1# b00000000000000000000000000000010 $ #5 0# #6 1# b00000000000000000000000000000011 $ #7 0# #8 1# b00000000000000000000000000000100 $ #9 0# #10 1# b00000000000000000000000000000101 $ #11 0# #12 1# b00000000000000000000000000000110 $ #13 0# #14 1# b00000000000000000000000000000111 $ #15 0# #16 1# b00000000000000000000000000001000 $ #17 0# #18 1# b00000000000000000000000000001001 $ #19 0# #20 1# b00000000000000000000000000001010 $ #21 0# #22 1# b00000000000000000000000000001011 $ #23 0# #24 1# b00000000000000000000000000001100 $ #25 0# #26 1# b00000000000000000000000000001101 $ #27 0# #28 1# b00000000000000000000000000001110 $ #29 0# #30 1# b00000000000000000000000000001111 $ #31 0# #32 1# b00000000000000000000000000010000 $ #33 0# #34 1# b00000000000000000000000000010001 $ #35 0# #36 1# b00000000000000000000000000010010 $ #37 0# #38 1# b00000000000000000000000000010011 $ #39 0# #40 1# b00000000000000000000000000010100 $ #41 0# #42 1# b00000000000000000000000000010101 $ #43 0# #44 1# b00000000000000000000000000010110 $ #45 0# #46 1# b00000000000000000000000000010111 $ #47 0# #48 1# b00000000000000000000000000011000 $ #49 0# #50 1# b00000000000000000000000000011001 $ #51 0# #52 1# b00000000000000000000000000011010 $ #53 0# #54 1# b00000000000000000000000000011011 $ #55 0# #56 1# b00000000000000000000000000011100 $ #57 0# #58 1# b00000000000000000000000000011101 $ #59 0# #60 1# b00000000000000000000000000011110 $ #61 0# #62 1# b00000000000000000000000000011111 $ #63 0# #64 1# b00000000000000000000000000100000 $ #65 0# #66 1# b00000000000000000000000000100001 $ #67 0# #68 1# b00000000000000000000000000100010 $ #69 0# #70 1# b00000000000000000000000000100011 $ #71 0# #72 1# b00000000000000000000000000100100 $ #73 0# #74 1# b00000000000000000000000000100101 $ #75 0# #76 1# b00000000000000000000000000100110 $ #77 0# #78 1# b00000000000000000000000000100111 $ #79 0# #80 1# b00000000000000000000000000101000 $ #81 0# #82 1# b00000000000000000000000000101001 $ #83 0# #84 1# b00000000000000000000000000101010 $ #85 0# #86 1# b00000000000000000000000000101011 $ #87 0# #88 1# b00000000000000000000000000101100 $ #89 0# #90 1# b00000000000000000000000000101101 $ #91 0# #92 1# b00000000000000000000000000101110 $ #93 0# #94 1# b00000000000000000000000000101111 $ #95 0# #96 1# b00000000000000000000000000110000 $ #97 0# #98 1# b00000000000000000000000000110001 $ #99 0# verilator-5.042/test_regress/t/t_select_c.v0000644000542200017500000000125515101701376021364 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; // verilator lint_off WIDTH // verilator lint_off IMPLICIT wire [22:0] w274; wire w412; wire w413; wire w509; assign w104 = ! w509; assign w201 = w258 > 12'hab7; assign w204 = 7'h7f <= w104; wire [11:0] w258 = 3'h3 || w274; assign w538 = w412 ? out21 : w201; wire [16:0] w539 = w413 ? w538 : 17'h00570; wire [21:5] out21 = w204; assign out51 = w539[0]; initial begin $display("%0d", out51); end endmodule verilator-5.042/test_regress/t/t_dpi_type_bad.v0000644000542200017500000000066515101701376022232 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2021 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; import "DPI-BAD" task dpix_twice; initial begin $stop; end endmodule verilator-5.042/test_regress/t/t_unopt_combo_bad.out0000644000542200017500000000141115101701376023271 0ustar mahmoudyfreeshell%Warning-UNOPTFLAT: t/t_unopt_combo.v:23:25: Signal unoptimizable: Circular combinational logic: 't.b' 23 | wire [31:0] b; | ^ ... For warning description see https://verilator.org/warn/UNOPTFLAT?v=latest ... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message. t/t_unopt_combo.v:23:25: Example path: t.b t/t_unopt_combo.v:124:4: Example path: ALWAYS t/t_unopt_combo.v:24:25: Example path: t.c t/t_unopt_combo.v:81:4: Example path: ALWAYS t/t_unopt_combo.v:23:25: Example path: t.b %Error: Exiting due to verilator-5.042/test_regress/t/t_split_var_4.v0000644000542200017500000000445515101701376022036 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 Yutetsu TAKATSUKASA. // SPDX-License-Identifier: CC0-1.0 `ifdef ENABLE_SPLIT_VAR `define SPLIT_VAR_COMMENT /* verilator split_var */ `else `define SPLIT_VAR_COMMENT /* verilator lint_off UNOPTFLAT */ `endif module t(/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; wire o0; wire [15:0] vec_i = crc[15:0]; wire [31:0] i = crc[31:0]; Test test(/*AUTOINST*/ // Outputs .o0 (o0), // Inputs .clk (clk), .i (i[1:0])); // Aggregate outputs into a single result vector // verilator lint_off WIDTH wire [63:0] result = {o0}; // verilator lint_on WIDTH // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); $display("o %b", o0); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc == 0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc == 99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'hb58b16c592557b30 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test(/*AUTOARG*/ // Outputs o0, // Inputs clk, i ); input wire clk; input wire [1:0] i; output reg o0; typedef struct packed { logic v0, v1; } packed_type0; packed_type0 value0 `SPLIT_VAR_COMMENT; wire value0_v0; assign value0.v0 = i[0]; assign value0.v1 = i[1] & !value0_v0; assign value0_v0 = value0.v0; always_ff @(posedge clk) begin o0 <= |value0; end endmodule `ifdef ENABLE_SPLIT_VAR /* verilator lint_on UNOPTFLAT */ `endif verilator-5.042/test_regress/t/t_preproc_comments.py0000755000542200017500000000152015101701376023343 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_preproc.v" stdout_filename = os.path.join(test.obj_dir, test.name + "__test.vpp") test.compile(verilator_flags2=['-DDEF_A0 -DPREDEF_COMMAND_LINE -E --preproc-comments'], verilator_make_gmake=False, make_top_shell=False, make_main=False, stdout_filename=stdout_filename) test.files_identical(stdout_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_assert_casez.v0000644000542200017500000000116215101701376022266 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2016 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg [1:0] value; initial begin value = 2'b00; unique casez (value) 2'b00 : ; 2'b01 : ; 2'b1? : ; endcase value = 2'b11; unique casez (value) 2'b00 : ; 2'b01 : ; 2'b1? : ; endcase unique casez (1'b1) default: ; endcase $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_case_x_bad.out0000644000542200017500000000135115101701376022212 0ustar mahmoudyfreeshell%Warning-CASEX: t/t_case_x_bad.v:14:7: Suggest casez (with ?'s) in place of casex (with X's) 14 | casex (value) | ^~~~~ ... For warning description see https://verilator.org/warn/CASEX?v=latest ... Use "/* verilator lint_off CASEX */" and lint_on around source to disable this message. %Warning-CASEWITHX: t/t_case_x_bad.v:19:9: Use of x/? constant in case statement, (perhaps intended casex/casez) 19 | 4'b1xxx: $stop; | ^~~~~~~ ... For warning description see https://verilator.org/warn/CASEWITHX?v=latest ... Use "/* verilator lint_off CASEWITHX */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_cover_expr_associative_array_class.py0000755000542200017500000000100015101701376027106 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--coverage-expr']) test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_public_func.py0000755000542200017500000000137215101701376023440 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_trace_public.v" test.golden_filename = "t/t_trace_public.out" test.compile(make_top_shell=False, make_main=False, v_flags2=["-DATTRIBUTES -DPUB_FUNC --trace-vcd --exe", test.pli_filename]) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_preproc_persist.py0000755000542200017500000000162015101701376023210 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') stdout_filename = os.path.join(test.obj_dir, test.name + "__test.vpp") test.compile( # Override default flags v_flags=[''], v_other_filenames=["t_preproc_persist2.v"], verilator_flags=["-E -P +incdir+t -Mdir", test.obj_dir], verilator_flags2=[''], verilator_flags3=[''], verilator_make_gmake=False, make_top_shell=False, make_main=False, stdout_filename=stdout_filename) test.files_identical(stdout_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_unbounded_bad.py0000755000542200017500000000076615101701376022570 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_trace_saif.py0000755000542200017500000000120615101701376022065 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_trace_fst.v" test.golden_filename = "t/t_trace_saif.out" test.compile(v_flags2=["--trace-saif"]) test.execute() test.saif_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_capitalization.py0000755000542200017500000000073415101701376024172 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_virtual_interface_param.v0000644000542200017500000000106415101701376024467 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 interface b_if #( parameter p ); int x = p; endinterface module t; m #(.p(2)) m_i (); initial begin virtual b_if#(2) vif = m_i.b; int y = m_i.b.x; if (vif.x != 2) $stop; if (y != 2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module m #( parameter p = 1 ) (); b_if #(p) b (); endmodule verilator-5.042/test_regress/t/t_dist_attributes/0000755000542200017500000000000015101701376022622 5ustar mahmoudyfreeshellverilator-5.042/test_regress/t/t_dist_attributes/mt_disabled.h0000644000542200017500000000303615101701376025244 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // //************************************************************************* // // Code available from: https://verilator.org // // Copyright 2022-2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #ifndef T_DIST_ATTRIBUTES_MT_DISABLED_H_ #define T_DIST_ATTRIBUTES_MT_DISABLED_H_ #include "verilatedos.h" void unannotatedMtDisabledFunctionBad(); // Duplicate to check that every declaration is reported void unannotatedMtDisabledFunctionBad(); class UnannotatedMtDisabledClass final { public: void unannotatedMtDisabledMethodBad(); static void unannotatedMtDisabledStaticMethodBad(); int unannotatedInlineMethodOK() const { return 42; } static int unannotatedInlineStaticMethodOK() { return -42; } }; void annotatedMtDisabledFunctionOK() VL_MT_DISABLED; // Duplicate void annotatedMtDisabledFunctionOK() VL_MT_DISABLED; class AnnotatedMtDisabledClass final { public: void annotatedMtDisabledMethodOK() VL_MT_DISABLED; static void annotatedMtDisabledStaticMethodOK() VL_MT_DISABLED; int annotatedInlineMethodOK() const VL_MT_DISABLED { return 42; } static int annotatedInlineStaticMethodOK() VL_MT_DISABLED { return -42; } }; #endif // T_DIST_ATTRIBUTES_MT_DISABLED_H_ verilator-5.042/test_regress/t/t_dist_attributes/mt_enabled.h0000644000542200017500000003303215101701376025066 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // //************************************************************************* // // Code available from: https://verilator.org // // Copyright 2022-2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #ifndef T_DIST_ATTRIBUTES_MT_ENABLED_H_ #define T_DIST_ATTRIBUTES_MT_ENABLED_H_ #include "verilatedos.h" #include "verilated.h" #include #define NO_ANNOTATION #define CALL_0(prefix, annotation, aarg_type, aarg, val) prefix##_##annotation(val) #define CALL_1(prefix, annotation, aarg_type, aarg, val) prefix##_##annotation(val) #define SIG_ANNOTATED_0(prefix, annotation, aarg_type, aarg, val) \ void prefix##_##annotation(aarg_type aarg) annotation #define SIG_ANNOTATED_1(prefix, annotation, aarg_type, aarg, val) \ void prefix##_##annotation(aarg_type aarg) annotation(aarg) #define SIG_UNANNOTATED_0(prefix, annotation, aarg_type, aarg, val) \ void prefix##_##annotation(aarg_type aarg) #define SIG_UNANNOTATED_1(prefix, annotation, aarg_type, aarg, val) \ void prefix##_##annotation(aarg_type aarg) // clang-format off #define EMIT_ALL(before, sig_prefix, val, after) \ before##_0(sig_prefix, NO_ANNOTATION, VerilatedMutex&, mtx, val) after \ before##_0(sig_prefix, VL_PURE, VerilatedMutex&, mtx, val) after \ before##_0(sig_prefix, VL_MT_SAFE, VerilatedMutex&, mtx, val) after \ before##_0(sig_prefix, VL_MT_SAFE_POSTINIT, VerilatedMutex&, mtx, val) after \ before##_0(sig_prefix, VL_MT_UNSAFE, VerilatedMutex&, mtx, val) after \ before##_0(sig_prefix, VL_MT_UNSAFE_ONE, VerilatedMutex&, mtx, val) after \ before##_0(sig_prefix, VL_MT_START, VerilatedMutex&, mtx, val) after \ before##_1(sig_prefix, VL_ACQUIRE, VerilatedMutex&, mtx, val) after \ before##_1(sig_prefix, VL_REQUIRES, VerilatedMutex&, mtx, val) after \ before##_1(sig_prefix, VL_RELEASE, VerilatedMutex&, mtx, val) after \ before##_1(sig_prefix, VL_ACQUIRE_SHARED, VerilatedMutex&, mtx, val) after \ before##_1(sig_prefix, VL_RELEASE_SHARED, VerilatedMutex&, mtx, val) after \ before##_1(sig_prefix, VL_EXCLUDES, VerilatedMutex&, mtx, val) after \ before##_1(sig_prefix, VL_MT_SAFE_EXCLUDES, VerilatedMutex&, mtx, val) after // clang-format on // Non-Static Functions, Annotated declaration, Unannotated definition. // (declarations) EMIT_ALL(SIG_ANNOTATED, nsf_au, /**/, ;) // Non-Static Functions, Unannotated declaration, Annotated definition. // (declarations) EMIT_ALL(SIG_UNANNOTATED, nsf_ua, /**/, ;) // Non-Static Functions, Annotated declaration, Annotated definition. // (declarations) EMIT_ALL(SIG_ANNOTATED, nsf_aa, /**/, ;) // Non-Static Functions, Annotated declaration, Annotated definition. // Definitions have extra annotations. // (declarations) EMIT_ALL(SIG_ANNOTATED, nsf_ae, /**/, ;) // Non-Static Functions, Annotated declaration, Annotated definition. // Declarations have extra annotations. // (declarations) EMIT_ALL(SIG_ANNOTATED, nsf_ea, /**/, VL_PURE VL_MT_SAFE;) // Non-Static Functions (call test in header). EMIT_ALL(inline SIG_ANNOTATED, nsf_test_caller_func_hdr, /**/, { VerilatedMutex m; EMIT_ALL(CALL, nsf_au, m, ;) EMIT_ALL(CALL, nsf_ua, m, ;) EMIT_ALL(CALL, nsf_aa, m, ;) EMIT_ALL(CALL, nsf_ae, m, ;) EMIT_ALL(CALL, nsf_ea, m, ;) }) // Inline Functions in Header. EMIT_ALL(inline SIG_ANNOTATED, ifh, /**/, {}) // Inline Functions in Header (call test in header). EMIT_ALL(inline SIG_ANNOTATED, ifh_test_caller_func_hdr, /**/, { VerilatedMutex m; EMIT_ALL(CALL, ifh, m, ;) }) struct GuardMe { void safe_if_guarded_or_local() {} operator int() const { return 4; } GuardMe& operator+=(int) { return *this; } }; class TestClass { VerilatedMutex m_mtx; GuardMe m_guardme VL_GUARDED_BY(m_mtx); GuardMe m_guardme_unguarded; public: // Static Class Methods, Annotated declaration, Unannotated definition. // (declarations) EMIT_ALL(static SIG_ANNOTATED, scm_au, /**/, ;) // Static Class Methods, Unannotated declaration, Annotated definition. // (declarations) EMIT_ALL(static SIG_UNANNOTATED, scm_ua, /**/, ;) // Static Class Methods, Annotated declaration, Annotated definition. // (declarations) EMIT_ALL(static SIG_ANNOTATED, scm_aa, /**/, ;) // Static Class Methods, Annotated declaration, Annotated definition. // Definitions have extra annotations. // (declarations) EMIT_ALL(static SIG_ANNOTATED, scm_ae, /**/, ;) // Static Class Methods, Annotated declaration, Annotated definition. // Declarations have extra annotations. // (declarations) EMIT_ALL(static SIG_ANNOTATED, scm_ea, /**/, VL_PURE VL_MT_SAFE;) // Static Class Methods (call test in header). EMIT_ALL(static SIG_ANNOTATED, scm_test_caller_smethod_hdr, /**/, { VerilatedMutex m; EMIT_ALL(CALL, TestClass::scm_au, m, ;) EMIT_ALL(CALL, TestClass::scm_ua, m, ;) EMIT_ALL(CALL, TestClass::scm_aa, m, ;) EMIT_ALL(CALL, TestClass::scm_ae, m, ;) EMIT_ALL(CALL, TestClass::scm_ea, m, ;) TestClass tc; EMIT_ALL(CALL, tc.scm_au, m, ;) EMIT_ALL(CALL, tc.scm_ua, m, ;) EMIT_ALL(CALL, tc.scm_aa, m, ;) EMIT_ALL(CALL, tc.scm_ae, m, ;) EMIT_ALL(CALL, tc.scm_ea, m, ;) TestClass* tcp = &tc; EMIT_ALL(CALL, tcp->scm_au, m, ;) EMIT_ALL(CALL, tcp->scm_ua, m, ;) EMIT_ALL(CALL, tcp->scm_aa, m, ;) EMIT_ALL(CALL, tcp->scm_ae, m, ;) EMIT_ALL(CALL, tcp->scm_ea, m, ;) }) // Static Class Methods (call test). // (declaration) EMIT_ALL(static SIG_ANNOTATED, scm_test_caller_smethod, /**/, ;) // Inline Static Class Methods. EMIT_ALL(static SIG_ANNOTATED, iscm, /**/, {}) // Inline Static Class Methods (call test in header). EMIT_ALL(static SIG_ANNOTATED, iscm_test_caller_smethod_hdr, /**/, { VerilatedMutex m; EMIT_ALL(CALL, TestClass::iscm, m, ;) TestClass tc; EMIT_ALL(CALL, tc.iscm, m, ;) TestClass* tcp = &tc; EMIT_ALL(CALL, tcp->iscm, m, ;) }) // Inline Static Class Methods (call test). // (declaration) EMIT_ALL(static SIG_ANNOTATED, iscm_test_caller_smethod, /**/, ;) // Class Methods, Annotated declaration, Unannotated definition. // (declarations) EMIT_ALL(SIG_ANNOTATED, cm_au, /**/, ;) // Class Methods, Unannotated declaration, Annotated definition. // (declarations) EMIT_ALL(SIG_UNANNOTATED, cm_ua, /**/, ;) // Class Methods, Annotated declaration, Annotated definition. // (declarations) EMIT_ALL(SIG_ANNOTATED, cm_aa, /**/, ;) // Class Methods, Annotated declaration, Annotated definition. // Definitions have extra annotations. // (declarations) EMIT_ALL(SIG_ANNOTATED, cm_ae, /**/, ;) // Class Methods, Annotated declaration, Annotated definition. // Declarations have extra annotations. // (declarations) EMIT_ALL(SIG_ANNOTATED, cm_ea, /**/, VL_PURE VL_MT_SAFE;) // Class Methods (call test in header). EMIT_ALL(SIG_ANNOTATED, cm_test_caller_smethod_hdr, /**/, { VerilatedMutex m; TestClass tc; EMIT_ALL(CALL, tc.cm_au, m, ;) EMIT_ALL(CALL, tc.cm_ua, m, ;) EMIT_ALL(CALL, tc.cm_aa, m, ;) EMIT_ALL(CALL, tc.cm_ae, m, ;) EMIT_ALL(CALL, tc.cm_ea, m, ;) TestClass* tcp = &tc; EMIT_ALL(CALL, tcp->cm_au, m, ;) EMIT_ALL(CALL, tcp->cm_ua, m, ;) EMIT_ALL(CALL, tcp->cm_aa, m, ;) EMIT_ALL(CALL, tcp->cm_ae, m, ;) EMIT_ALL(CALL, tcp->cm_ea, m, ;) }) // Class Methods (call test). // (declaration) EMIT_ALL(SIG_ANNOTATED, cm_test_caller_smethod, /**/, ;) // Inline Class Methods. EMIT_ALL(SIG_ANNOTATED, icm, /**/, {}) // Inline Class Methods (call test in header). EMIT_ALL(SIG_ANNOTATED, icm_test_caller_smethod_hdr, /**/, { VerilatedMutex m; TestClass tc; EMIT_ALL(CALL, tc.icm, m, ;) TestClass* tcp = &tc; EMIT_ALL(CALL, tcp->icm, m, ;) }) // Inline Class Methods (call test). // (declaration) EMIT_ALL(SIG_ANNOTATED, icm_test_caller_smethod, /**/, ;) void guarded_by_test_pass(GuardMe& guardme_arg) VL_MT_SAFE { guardme_arg.safe_if_guarded_or_local(); int a = guardme_arg; guardme_arg += 4; m_mtx.lock(); m_guardme.safe_if_guarded_or_local(); int b = m_guardme; m_guardme += 4; m_mtx.unlock(); GuardMe guardme_local; guardme_local.safe_if_guarded_or_local(); int c = guardme_local; guardme_local += 4; } void guarded_by_test_fail() VL_MT_SAFE { m_guardme_unguarded.safe_if_guarded_or_local(); int a = m_guardme_unguarded; m_guardme_unguarded += 4; } }; static void static_function() {} class StaticClass { public: static void static_class_function() {} }; class ConstructorCallsUnsafeLocalFunction { public: void unsafe_function() VL_MT_UNSAFE {}; ConstructorCallsUnsafeLocalFunction() { unsafe_function(); } }; class ConstructorCallsStaticFunctionNoAnnotation { public: ConstructorCallsStaticFunctionNoAnnotation() { static_function(); } }; class ConstructorCallsLocalFunction { public: void local_function() {} ConstructorCallsLocalFunction() { local_function(); } }; class ConstructorCallsLocalFunctionCallsGlobal { public: void local_function() { static_function(); } ConstructorCallsLocalFunctionCallsGlobal() { local_function(); } }; class SafeFunction { public: void safe_function() VL_MT_SAFE {} }; class UnsafeFunction { public: void unsafe_function() VL_MT_UNSAFE {} }; class ConstructorWithPointer { public: ConstructorWithPointer(SafeFunction* p) { p->safe_function(); } }; class ConstructorWithReference { public: ConstructorWithReference(SafeFunction& p) { p.safe_function(); } }; class ConstructorWithUnsafePointer { public: ConstructorWithUnsafePointer(UnsafeFunction* p) { p->unsafe_function(); } }; class ConstructorWithUnsafeReference { public: ConstructorWithUnsafeReference(UnsafeFunction& p) { p.unsafe_function(); } }; class ConstructorCallsLocalCallsGlobal { void local_function2() { static_function(); } void local_function() { local_function2(); } public: ConstructorCallsLocalCallsGlobal() { local_function(); } }; class ConstructorCallsLocalCallsClassGlobal { void local_function2() { StaticClass::static_class_function(); } void local_function() { local_function2(); } public: ConstructorCallsLocalCallsClassGlobal() { local_function(); } }; class DummyClass2 { public: void dummy_function2() {} }; class DummyClass { public: DummyClass2 d; void dummy_function() {} }; DummyClass dummyGlobalVar; class ConstructorCallsGlobalObject { public: ConstructorCallsGlobalObject() { dummyGlobalVar.dummy_function(); } }; class ConstructorCallsGlobalObjectMember { public: ConstructorCallsGlobalObjectMember() { dummyGlobalVar.d.dummy_function2(); } }; namespace VirtualInheritance { struct Base1 { virtual int func(int a, int b) const VL_PURE = 0; virtual ~Base1() = default; }; struct Base2 { virtual int func() const VL_PURE = 0; virtual ~Base2() = default; }; struct Derived final : public Base1, Base2 { int func(int a, int b) const override VL_PURE { return notPure(); } int func() const override VL_PURE { return notPure(); } static int notPure() { static int s_counter; return ++s_counter; } }; } //namespace VirtualInheritance class TestClassConstructor { void safe_function_unsafe_constructor_bad() VL_MT_SAFE { ConstructorCallsUnsafeLocalFunction f{}; }; void safe_function_static_constructor_bad() VL_MT_SAFE { ConstructorCallsStaticFunctionNoAnnotation f{}; }; void safe_function_local_function_global_bad() VL_MT_SAFE { ConstructorCallsLocalFunctionCallsGlobal f{}; } void safe_function_local_function_constructor_good() VL_MT_SAFE { ConstructorCallsLocalFunction f{}; } void safe_function_calls_constructor_with_pointer_good() VL_MT_SAFE { SafeFunction* i = new SafeFunction{}; ConstructorWithPointer f{i}; } void safe_function_calls_constructor_with_reference_good() VL_MT_SAFE { SafeFunction i; ConstructorWithReference f{i}; } void safe_function_calls_constructor_with_unsafepointer_bad() VL_MT_SAFE { UnsafeFunction* i = new UnsafeFunction{}; ConstructorWithUnsafePointer f{i}; } void safe_function_calls_constructor_with_unsafereference_bad() VL_MT_SAFE { UnsafeFunction i; ConstructorWithUnsafeReference f{i}; } void safe_function_calls_constructor_local_calls_global_bad() VL_MT_SAFE { ConstructorCallsLocalCallsGlobal f{}; } void safe_function_calls_constructor_local_calls_class_global_bad() VL_MT_SAFE { ConstructorCallsLocalCallsClassGlobal f{}; } void safe_function_calls_constructor_global_object_bad() VL_MT_STABLE { ConstructorCallsGlobalObject f{}; } void safe_function_calls_constructor_global_object_member_bad() VL_MT_STABLE { ConstructorCallsGlobalObjectMember f{}; } void virtual_function_mismatch() { VirtualInheritance::Derived pd{}; } }; #endif // T_DIST_ATTRIBUTES_MT_ENABLED_H_ verilator-5.042/test_regress/t/t_dist_attributes/mt_enabled.cpp0000644000542200017500000001270715101701376025427 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // //************************************************************************* // // Code available from: https://verilator.org // // Copyright 2022-2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "verilatedos.h" #include "mt_enabled.h" // Non-Static Functions, Annotated declaration, Unannotated definition. // (definitions) EMIT_ALL(SIG_UNANNOTATED, nsf_au, /**/, {}) // Non-Static Functions, Unannotated declaration, Annotated definition. // (definitions) EMIT_ALL(SIG_ANNOTATED, nsf_ua, /**/, {}) // Non-Static Functions, Annotated declaration, Annotated definition. // (definitions) EMIT_ALL(SIG_ANNOTATED, nsf_aa, /**/, {}) // Non-Static Functions, Annotated declaration, Annotated definition. // Definitions have extra annotations. // (definitions) EMIT_ALL(SIG_ANNOTATED, nsf_ae, /**/, VL_PURE VL_MT_SAFE{}) // Non-Static Functions, Annotated declaration, Annotated definition. // Declarations have extra annotations. // (definitions) EMIT_ALL(SIG_ANNOTATED, nsf_ea, /**/, {}) // Non-Static Functions (call test). EMIT_ALL(VL_ATTR_UNUSED static SIG_ANNOTATED, nsf_test_caller_func, /**/, { VerilatedMutex m; EMIT_ALL(CALL, nsf_au, m, ;) EMIT_ALL(CALL, nsf_ua, m, ;) EMIT_ALL(CALL, nsf_aa, m, ;) EMIT_ALL(CALL, nsf_ae, m, ;) EMIT_ALL(CALL, nsf_ea, m, ;) }) // Inline Functions in Header (call test). EMIT_ALL(VL_ATTR_UNUSED static SIG_ANNOTATED, ifh_test_caller_func, /**/, { VerilatedMutex m; EMIT_ALL(CALL, ifh, m, ;) }) // Static Functions in Cpp file. EMIT_ALL(inline SIG_ANNOTATED, sfc, /**/, {}) // Static Functions in Cpp file (call test). EMIT_ALL(VL_ATTR_UNUSED static SIG_ANNOTATED, sfc_test_caller_func, /**/, { VerilatedMutex m; EMIT_ALL(CALL, sfc, m, ;) }) // Static Class Methods, Annotated declaration, Unannotated definition. // (definitions) EMIT_ALL(SIG_UNANNOTATED, TestClass::scm_au, /**/, {}) // Static Class Methods, Unannotated declaration, Annotated definition. // (definitions) EMIT_ALL(SIG_ANNOTATED, TestClass::scm_ua, /**/, {}) // Static Class Methods, Annotated declaration, Annotated definition. // (definitions) EMIT_ALL(SIG_ANNOTATED, TestClass::scm_aa, /**/, {}) // Static Class Methods, Annotated declaration, Annotated definition. // Definitions have extra annotations. // (definitions) EMIT_ALL(SIG_ANNOTATED, TestClass::scm_ae, /**/, VL_PURE VL_MT_SAFE{}) // Static Class Methods, Annotated declaration, Annotated definition. // Declarations have extra annotations. // (definitions) EMIT_ALL(SIG_ANNOTATED, TestClass::scm_ea, /**/, {}) // Static Class Methods (call test). // (definition) EMIT_ALL(SIG_ANNOTATED, TestClass::scm_test_caller_smethod, /**/, { VerilatedMutex m; EMIT_ALL(CALL, TestClass::scm_au, m, ;) EMIT_ALL(CALL, TestClass::scm_ua, m, ;) EMIT_ALL(CALL, TestClass::scm_aa, m, ;) EMIT_ALL(CALL, TestClass::scm_ae, m, ;) EMIT_ALL(CALL, TestClass::scm_ea, m, ;) TestClass tc; EMIT_ALL(CALL, tc.scm_au, m, ;) EMIT_ALL(CALL, tc.scm_ua, m, ;) EMIT_ALL(CALL, tc.scm_aa, m, ;) EMIT_ALL(CALL, tc.scm_ae, m, ;) EMIT_ALL(CALL, tc.scm_ea, m, ;) TestClass* tcp = &tc; EMIT_ALL(CALL, tcp->scm_au, m, ;) EMIT_ALL(CALL, tcp->scm_ua, m, ;) EMIT_ALL(CALL, tcp->scm_aa, m, ;) EMIT_ALL(CALL, tcp->scm_ae, m, ;) EMIT_ALL(CALL, tcp->scm_ea, m, ;) }) // Inline Static Class Methods (call test). // (definition) EMIT_ALL(SIG_ANNOTATED, TestClass::iscm_test_caller_smethod, /**/, { VerilatedMutex m; EMIT_ALL(CALL, TestClass::iscm, m, ;) TestClass tc; EMIT_ALL(CALL, tc.iscm, m, ;) TestClass* tcp = &tc; EMIT_ALL(CALL, tcp->iscm, m, ;) }) // Class Methods, Annotated declaration, Unannotated definition. // (definitions) EMIT_ALL(SIG_UNANNOTATED, TestClass::cm_au, /**/, {}) // Class Methods, Unannotated declaration, Annotated definition. // (definitions) EMIT_ALL(SIG_ANNOTATED, TestClass::cm_ua, /**/, {}) // Class Methods, Annotated declaration, Annotated definition. // (definitions) EMIT_ALL(SIG_ANNOTATED, TestClass::cm_aa, /**/, {}) // Class Methods, Annotated declaration, Annotated definition. // Definitions have extra annotations. // (definitions) EMIT_ALL(SIG_ANNOTATED, TestClass::cm_ae, /**/, VL_PURE VL_MT_SAFE{}) // Class Methods, Annotated declaration, Annotated definition. // Declarations have extra annotations. // (definitions) EMIT_ALL(SIG_ANNOTATED, TestClass::cm_ea, /**/, {}) // Class Methods (call test). // (definition) EMIT_ALL(SIG_ANNOTATED, TestClass::cm_test_caller_smethod, /**/, { VerilatedMutex m; TestClass tc; EMIT_ALL(CALL, tc.cm_au, m, ;) EMIT_ALL(CALL, tc.cm_ua, m, ;) EMIT_ALL(CALL, tc.cm_aa, m, ;) EMIT_ALL(CALL, tc.cm_ae, m, ;) EMIT_ALL(CALL, tc.cm_ea, m, ;) TestClass* tcp = &tc; EMIT_ALL(CALL, tcp->cm_au, m, ;) EMIT_ALL(CALL, tcp->cm_ua, m, ;) EMIT_ALL(CALL, tcp->cm_aa, m, ;) EMIT_ALL(CALL, tcp->cm_ae, m, ;) EMIT_ALL(CALL, tcp->cm_ea, m, ;) }) // Inline Class Methods (call test). // (definition) EMIT_ALL(SIG_ANNOTATED, TestClass::icm_test_caller_smethod, /**/, { VerilatedMutex m; TestClass tc; EMIT_ALL(CALL, tc.icm, m, ;) TestClass* tcp = &tc; EMIT_ALL(CALL, tcp->icm, m, ;) }) verilator-5.042/test_regress/t/t_dist_attributes/mt_disabled.cpp0000644000542200017500000000243515101701376025601 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // //************************************************************************* // // Code available from: https://verilator.org // // Copyright 2022-2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #define VL_MT_DISABLED_CODE_UNIT 1 #include "mt_disabled.h" #include "mt_enabled.h" void unannotatedMtDisabledFunctionBad() { } void UnannotatedMtDisabledClass::unannotatedMtDisabledMethodBad() { } void UnannotatedMtDisabledClass::unannotatedMtDisabledStaticMethodBad() { } // Declarations in .cpp don't have to be annotated with VL_MT_DISABLED. void annotatedMtDisabledFunctionOK(); void annotatedMtDisabledFunctionOK() { VerilatedMutex m; // REQUIRES should be ignored and mutex locking not needed. nsf_aa_VL_REQUIRES(m); } void AnnotatedMtDisabledClass::annotatedMtDisabledMethodOK() { annotatedMtDisabledFunctionOK(); } void AnnotatedMtDisabledClass::annotatedMtDisabledStaticMethodOK() { annotatedMtDisabledFunctionOK(); } verilator-5.042/test_regress/t/t_preproc_str_undef.v0000644000542200017500000000147615101701376023333 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define PREFIX_ my_prefix_ `define SUFFIX my_suffix `define PREFIX_SUFFIX my_prefix_suffix `define name1 `PREFIX``_```SUFFIX `define name2(p,s) p``_``s `define name3(p) ```p``_SUFFIX `define stringify(text) `"text`" module t(); initial begin // Another simulator gives: // `PREFIX_my_suffix // `name2(`PREFIX, my_suffix) // `name3(PREFIX) $display(`stringify(`name1)); $display(`stringify(`name2(`PREFIX, `SUFFIX))); $display(`stringify(`name3(PREFIX))); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_bitsel_2d_slice.py0000755000542200017500000000073415101701376023020 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios("simulator") test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_semaphore_always.v0000644000542200017500000000071015101701376023141 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; semaphore s = new; initial begin s.put(); end always @(posedge clk) begin s.get(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_param_type_id_bad.v0000644000542200017500000000041415101701376023222 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 int i; class Cls #(parameter type P_T = i); endclass verilator-5.042/test_regress/t/t_dfg_multidriver_non_dfg.v0000644000542200017500000000066415101701376024466 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 `default_nettype none module t( input wire i, output wire o ); logic a; logic b; initial begin a = 1'd0; b = 1'd0; end assign a = ~i; assign b = a; assign o = b; endmodule verilator-5.042/test_regress/t/t_clocking_notiming.v0000644000542200017500000000051115101701376023272 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; logic clk; logic out; clocking cb @(posedge clk); output #1 out; endclocking endmodule verilator-5.042/test_regress/t/t_trace_public_sig.vlt0000644000542200017500000000037615101701376023444 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. // SPDX-License-Identifier: CC0-1.0 `verilator_config public -module "glbl" -var "GSR" verilator-5.042/test_regress/t/t_class_member_bad2.out0000644000542200017500000000224615101701376023472 0ustar mahmoudyfreeshell%Error: t/t_class_member_bad2.v:9:8: Duplicate declaration of signal: 'vardup' 9 | int vardup; | ^~~~~~ t/t_class_member_bad2.v:8:8: ... Location of original declaration 8 | int vardup; | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_class_member_bad2.v:12:9: Duplicate declaration of task: 'memdup' 12 | task memdup; | ^~~~~~ t/t_class_member_bad2.v:10:9: ... Location of original declaration 10 | task memdup; | ^~~~~~ %Error: t/t_class_member_bad2.v:17:18: Duplicate declaration of task: 'funcdup' 17 | function void funcdup; | ^~~~~~~ t/t_class_member_bad2.v:15:18: ... Location of original declaration 15 | function void funcdup; | ^~~~~~~ %Error: t/t_class_member_bad2.v:12:9: Duplicate declaration of member name: 'memdup' 12 | task memdup; | ^~~~~~ %Error: t/t_class_member_bad2.v:17:18: Duplicate declaration of member name: 'funcdup' 17 | function void funcdup; | ^~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_randomize_inline_var_ctl_unsup_2.v0000644000542200017500000000060215101701376026311 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Foo; int x; static function Foo get; Foo foo = new; return foo; endfunction endclass module t; initial void'(Foo::get().randomize(x)); endmodule verilator-5.042/test_regress/t/t_inst_signed1.v0000644000542200017500000000177715101701376022203 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg signed i; wire signed o1; wire signed o2; integer cyc; initial cyc = 0; sub1 sub1 (.i(i), .o(o1)); sub2 sub2 (.i(o1), .o(o2)); always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==0) begin i <= 1'b0; end else if (cyc==1) begin if (o2 != 1'b0) $stop; i <= 1'b1; end else if (cyc==2) begin if (o2 != 1'b1) $stop; end if (cyc==3) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule //msg2540 module sub1 ( input signed i, output wire signed o); assign o = ~i; endmodule module sub2 (i,o); input signed i; output signed o; wire signed o = ~i; endmodule verilator-5.042/test_regress/t/t_class_static_default_arg.v0000644000542200017500000000112215101701376024605 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Foo; static function bit get_first(bit q[$] = {1'b1}); return q[0]; endfunction endclass module t; initial begin bit first; bit arg[$] = {1'b0, 1'b1}; first = Foo::get_first(); if (first != 1) $stop; first = Foo::get_first(arg); if (first != 0) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_dpi_open_query.py0000755000542200017500000000171715101701376023016 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if test.nc: # For NC, compile twice, first just to generate DPI headers test.compile(nc_flags2=["+ncdpiimpheader+" + test.obj_dir + "/dpi-imp.h"]) test.compile( v_flags2=["t/t_dpi_open_query.cpp"], verilator_flags2=["-Wall -Wno-DECLFILENAME"], # NC: Gdd the obj_dir to the C include path nc_flags2=["+ncscargs+-I" + test.obj_dir], # ModelSim: Generate DPI header, add obj_dir to the C include path ms_flags2=["-dpiheader " + test.obj_dir + "/dpi.h", "-ccflags -I" + test.obj_dir]) test.execute() test.passes() verilator-5.042/test_regress/t/t_mailbox.py0000755000542200017500000000077715101701376021434 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary -Wall"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_pp_pragma_bad.py0000755000542200017500000000103215101701376022536 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["-E -Wpedantic"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_cover_toggle__all.out0000644000542200017500000002070315101701376023612 0ustar mahmoudyfreeshell// // verilator_coverage annotation // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef struct packed {logic a;} str_logic; module t (/*AUTOARG*/ // Inputs clk, check_real, check_array_real, check_string ); 000010 input clk; input real check_real; // Check issue #2741 input real check_array_real [1:0]; input string check_string; // Check issue #2766 typedef struct packed { union packed { logic ua; logic ub; } u; logic b; } str_t; 000001 reg toggle; initial toggle='0; logic _under_toggle = toggle; // For --coverage-underscore 000001 str_t stoggle; initial stoggle='0; 000010 str_logic strl; initial strl='0; union { real val1; // TODO use bit [7:0] here real val2; // TODO use bit [3:0] here } utoggle; const reg aconst = '0; ~000001 reg [1:0][1:0] ptoggle; initial ptoggle=0; integer cyc; initial cyc=1; ~000006 wire [7:0] cyc_copy = cyc[7:0]; 000001 wire toggle_up; typedef struct { int q[$]; } str_queue_t; str_queue_t str_queue; typedef struct packed { // verilator lint_off ASCRANGE bit [3:5] x; // verilator lint_on ASCRANGE bit [0:0] y; } str_bit_t; ~000001 str_bit_t str_bit; ~000001 str_bit_t [5:2] str_bit_arr; assign strl.a = clk; alpha a1 (/*AUTOINST*/ // Outputs .toggle_up (toggle_up), // Inputs .clk (clk), .toggle (toggle), .cyc_copy (cyc_copy[7:0])); alpha a2 (/*AUTOINST*/ // Outputs .toggle_up (toggle_up), // Inputs .clk (clk), .toggle (toggle), .cyc_copy (cyc_copy[7:0])); beta b1 (/*AUTOINST*/ // Inputs .clk (clk), .toggle_up (toggle_up)); off o1 (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle)); param#(1) p1 (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle)); param#() p2 (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle)); mod_struct i_mod_struct (/*AUTOINST*/ // Inputs .input_struct (strl)); ~000001 reg [1:0] memory[121:110]; wire [1023:0] largeish = {992'h0, cyc}; // CHECK_COVER_MISSING(-1) always @ (posedge clk) begin if (cyc != 0) begin cyc <= cyc + 1; memory[cyc + 'd100] <= memory[cyc + 'd100] + 2'b1; toggle <= '0; stoggle.u <= toggle; stoggle.b <= toggle; utoggle.val1 <= real'(cyc[7:0]); ptoggle[0][0] <= toggle; if (cyc == 3) begin str_queue.q.push_back(1); toggle <= '1; str_bit.x <= '1; str_bit.y <= '1; str_bit_arr[4].x <= '1; end if (cyc == 4) begin if (str_queue.q.size() != 1) $stop; toggle <= '0; str_bit.x[3] <= 0; str_bit.y[0] <= 0; str_bit_arr[4].x[3] <= 0; end else if (cyc == 10) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module alpha (/*AUTOARG*/ // Outputs toggle_up, // Inputs clk, toggle, cyc_copy ); // t.a1 and t.a2 collapse to a count of 2 000020 input clk; 000002 input toggle; // CHECK_COVER(-1,"top.t.a*","toggle:0->1",2) // CHECK_COVER(-2,"top.t.a*","toggle:1->0",2) // (t.a1 and t.a2) ~000012 input [7:0] cyc_copy; // CHECK_COVER(-1,"top.t.a*","cyc_copy[0]:0->1",12) // CHECK_COVER(-2,"top.t.a*","cyc_copy[0]:1->0",10) // CHECK_COVER(-3,"top.t.a*","cyc_copy[1]:0->1",6) // CHECK_COVER(-4,"top.t.a*","cyc_copy[1]:1->0",4) // CHECK_COVER(-5,"top.t.a*","cyc_copy[2]:0->1",2) // CHECK_COVER(-6,"top.t.a*","cyc_copy[2]:1->0",2) // CHECK_COVER(-7,"top.t.a*","cyc_copy[3]:0->1",2) // CHECK_COVER(-8,"top.t.a*","cyc_copy[3]:1->0",0) // CHECK_COVER(-9,"top.t.a*","cyc_copy[4]:0->1",0) // CHECK_COVER(-10,"top.t.a*","cyc_copy[4]:1->0",0) // CHECK_COVER(-11,"top.t.a*","cyc_copy[5]:0->1",0) // CHECK_COVER(-12,"top.t.a*","cyc_copy[5]:1->0",0) // CHECK_COVER(-13,"top.t.a*","cyc_copy[6]:0->1",0) // CHECK_COVER(-14,"top.t.a*","cyc_copy[6]:1->0",0) // CHECK_COVER(-15,"top.t.a*","cyc_copy[7]:0->1",0) // CHECK_COVER(-16,"top.t.a*","cyc_copy[7]:1->0",0) 000002 reg toggle_internal; // CHECK_COVER(-1,"top.t.a*","toggle_internal:0->1",2) // CHECK_COVER(-2,"top.t.a*","toggle_internal:1->0",2) // (t.a1 and t.a2) 000002 output reg toggle_up; // CHECK_COVER(-1,"top.t.a*","toggle_up:0->1",2) // CHECK_COVER(-2,"top.t.a*","toggle_up:1->0",2) // (t.a1 and t.a2) always @ (posedge clk) begin toggle_internal <= toggle; toggle_up <= toggle; end endmodule module beta (/*AUTOARG*/ // Inputs clk, toggle_up ); 000010 input clk; 000001 input toggle_up; // CHECK_COVER(-1,"top.t.b1","toggle_up:0->1",1) // CHECK_COVER(-2,"top.t.b1","toggle_up:1->0",1) /* verilator public_module */ always @ (posedge clk) begin if (0 && toggle_up) begin end end endmodule module off (/*AUTOARG*/ // Inputs clk, toggle ); // verilator coverage_off input clk; // CHECK_COVER_MISSING(-1) // verilator coverage_on 000001 input toggle; // CHECK_COVER(-1,"top.t.o1","toggle:0->1",1) // CHECK_COVER(-2,"top.t.o1","toggle:1->0",1) endmodule module param #(parameter P = 2) (/*AUTOARG*/ // Inputs clk, toggle ); 000010 input clk; 000001 input toggle; ~000001 logic z; for (genvar i = 0; i < P; i++) begin 000001 logic x; always @ (posedge clk) begin x <= toggle; end for (genvar j = 0; j < 3; j++) begin ~000002 logic [2:0] y; always @ (negedge clk) begin y <= {toggle, ~toggle, 1'b1}; end end end if (P > 1) begin : gen_1 assign z = 1; end endmodule module mod_struct(/*AUTOARG*/ // Inputs input_struct ); 000010 input str_logic input_struct; endmodule verilator-5.042/test_regress/t/t_sys_monitor_changes.v0000644000542200017500000000112315101701376023652 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; bit clk; int a, b; always #10 clk = ~clk; initial begin $monitor("[%0t] a=%0d b=%0d", $time, a, b); #1; // So not on clock edge #100; a = 10; #10; b = 20; #10; a = 11; #10; b = 22; #100; #10; $monitoroff; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_package_identifier_bad.v0000644000542200017500000000051415101701376024203 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 package Foo; endpackage package Bar; static int baz; endpackage module t; int baz = Foo::Bar::baz; endmodule verilator-5.042/test_regress/t/t_dpi_2exp_bad.v0000644000542200017500000000105415101701376022120 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; export "DPI-C" task dpix_twice; export "DPI-C" dpix_t_int_renamed = task dpix_twice; task dpix_twice(input int i, output int o); o = ~i; endtask initial begin $stop; end endmodule verilator-5.042/test_regress/t/t_vpi_public_depthn_2.out0000644000542200017500000000021215101701376024054 0ustar mahmoudyfreeshell scopesDump: SCOPE 0x#: top.TOP SCOPE 0x#: top.t SCOPE 0x#: top.t.s_axis_if SCOPE 0x#: top.t.u_dut *-* All Finished *-* verilator-5.042/test_regress/t/t_func_const_packed_struct_bad.v0000644000542200017500000000160615101701376025465 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 module t; typedef struct packed { logic [ 31 : 0 ] a; logic [ 31 : 0 ] b; } params_t; localparam P24 = f_add2(7, 8, 9); initial begin // Should never get here $write("*-* All Finished *-*\n"); $finish; end function integer f_add(input params_t [ 1 : 0 ] params); f_add = params[0].a+params[1].b; if (f_add == 15) $fatal(2, "f_add = 15"); endfunction // Speced ok: function called from function function integer f_add2(input [31:0] a, input [31:0] b, input [31:0] c); params_t [ 1 : 0 ] params; params[0] = '{a:a, b:555}; params[1] = '{a:12345, b:b}; f_add2 = f_add(params)+c; endfunction endmodule verilator-5.042/test_regress/t/t_vpi_param.cpp0000644000542200017500000001734515101701376022105 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #ifdef IS_VPI #include "vpi_user.h" #include #else #include "verilated.h" #include "verilated_vcd_c.h" #include "verilated_vpi.h" #include "svdpi.h" #ifdef T_VPI_PARAM #include "Vt_vpi_param.h" #include "Vt_vpi_param__Dpi.h" #elif defined(T_VPI_PUBLIC_PARAMS) #include "Vt_vpi_public_params.h" #else #error "Bad test" #endif #endif #include #include #include extern "C" { #include } // These require the above. Comment prevents clang-format moving them #include "TestSimulator.h" #include "TestVpi.h" int check_param_int(std::string name, PLI_INT32 format, int exp_value, bool verbose) { int vpi_type; TestVpiHandle param_h; s_vpi_value value; value.format = format; value.value.integer = 0; s_vpi_error_info e; const char* p; vpi_printf((PLI_BYTE8*)"Check parameter %s vpi ...\n", name.c_str()); param_h = vpi_handle_by_name((PLI_BYTE8*)TestSimulator::rooted(name.c_str()), NULL); CHECK_RESULT_NZ(param_h); vpi_type = vpi_get(vpiType, param_h); CHECK_RESULT(vpi_type, vpiParameter); if (verbose) { vpi_printf((PLI_BYTE8*)" vpiType: %s (%d)\n", vpi_get_str(vpiType, param_h), vpi_type); } // attributes p = vpi_get_str(vpiName, param_h); CHECK_RESULT_CSTR(p, name.c_str()); p = vpi_get_str(vpiFullName, param_h); CHECK_RESULT_CSTR(p, std::string{"t." + name}.c_str()); p = vpi_get_str(vpiType, param_h); CHECK_RESULT_CSTR(p, "vpiParameter"); vpi_type = vpi_get(vpiLocalParam, param_h); CHECK_RESULT_NZ(vpi_chk_error(&e)); if (verbose && vpi_chk_error(&e)) { vpi_printf((PLI_BYTE8*)" vpi_chk_error: %s\n", e.message); } // values if (verbose) vpi_printf((PLI_BYTE8*)" Try writing value to %s ...\n", name.c_str()); value.value.integer = exp_value; vpi_put_value(param_h, &value, NULL, vpiNoDelay); CHECK_RESULT_NZ(vpi_chk_error(&e)); if (verbose && vpi_chk_error(&e)) { vpi_printf((PLI_BYTE8*)" vpi_chk_error: %s\n", e.message); } if (verbose) vpi_printf((PLI_BYTE8*)" Try reading value of %s ...\n", name.c_str()); vpi_get_value(param_h, &value); CHECK_RESULT_NZ(!vpi_chk_error(&e)); if (verbose && vpi_chk_error(&e)) { vpi_printf((PLI_BYTE8*)" vpi_chk_error: %s\n", e.message); } if (verbose) { vpi_printf((PLI_BYTE8*)" value of %s: %d\n", name.c_str(), value.value.integer); } CHECK_RESULT(value.value.integer, exp_value); return 0; } int check_param_str(std::string name, PLI_INT32 format, std::string exp_value, bool verbose) { int vpi_type; TestVpiHandle param_h; s_vpi_value value; value.format = format; value.value.integer = 0; s_vpi_error_info e; const char* p; vpi_printf((PLI_BYTE8*)"Check parameter %s vpi ...\n", name.c_str()); param_h = vpi_handle_by_name((PLI_BYTE8*)TestSimulator::rooted(name.c_str()), NULL); CHECK_RESULT_NZ(param_h); vpi_type = vpi_get(vpiType, param_h); CHECK_RESULT(vpi_type, vpiParameter); if (verbose) { vpi_printf((PLI_BYTE8*)" vpiType: %s (%d)\n", vpi_get_str(vpiType, param_h), vpi_type); } // attributes p = vpi_get_str(vpiName, param_h); CHECK_RESULT_CSTR(p, name.c_str()); p = vpi_get_str(vpiFullName, param_h); CHECK_RESULT_CSTR(p, std::string{"t." + name}.c_str()); p = vpi_get_str(vpiType, param_h); CHECK_RESULT_CSTR(p, "vpiParameter"); vpi_type = vpi_get(vpiLocalParam, param_h); CHECK_RESULT_NZ(vpi_chk_error(&e)); if (verbose && vpi_chk_error(&e)) { vpi_printf((PLI_BYTE8*)" vpi_chk_error: %s\n", e.message); } // values if (verbose) vpi_printf((PLI_BYTE8*)" Try writing value to %s ...\n", name.c_str()); value.value.str = (PLI_BYTE8*)exp_value.c_str(); vpi_put_value(param_h, &value, NULL, vpiNoDelay); CHECK_RESULT_NZ(vpi_chk_error(&e)); if (verbose && vpi_chk_error(&e)) { vpi_printf((PLI_BYTE8*)" vpi_chk_error: %s\n", e.message); } if (verbose) vpi_printf((PLI_BYTE8*)" Try reading value of %s ...\n", name.c_str()); vpi_get_value(param_h, &value); CHECK_RESULT_NZ(!vpi_chk_error(&e)); if (verbose && vpi_chk_error(&e)) { vpi_printf((PLI_BYTE8*)" vpi_chk_error: %s\n", e.message); } if (verbose) { vpi_printf((PLI_BYTE8*)" value of %s: %s\n", name.c_str(), value.value.str); } CHECK_RESULT_CSTR(value.value.str, exp_value.c_str()); return 0; } int _mon_check_param() { int status = 0; #ifdef TEST_VERBOSE bool verbose = true; #else bool verbose = false; #endif status += check_param_int("WIDTH", vpiIntVal, 32, verbose); status += check_param_int("DEPTH", vpiIntVal, 16, verbose); status += check_param_str("PARAM_LONG", vpiHexStrVal, "fedcba9876543210", verbose); status += check_param_str("PARAM_STR", vpiStringVal, "'some string value'", verbose); return status; } extern "C" int mon_check() { // Callback from initial block in monitor if (int status = _mon_check_param()) return status; return 0; // Ok } //====================================================================== #ifdef IS_VPI static int mon_check_vpi() { TestVpiHandle href = vpi_handle(vpiSysTfCall, 0); s_vpi_value vpi_value; vpi_value.format = vpiIntVal; vpi_value.value.integer = mon_check(); vpi_put_value(href, &vpi_value, NULL, vpiNoDelay); return 0; } static s_vpi_systf_data vpi_systf_data[] = {{vpiSysFunc, vpiIntFunc, (PLI_BYTE8*)"$mon_check", (PLI_INT32(*)(PLI_BYTE8*))mon_check_vpi, 0, 0, 0}, 0}; // cver entry void vpi_compat_bootstrap(void) { p_vpi_systf_data systf_data_p; systf_data_p = &(vpi_systf_data[0]); while (systf_data_p->type != 0) vpi_register_systf(systf_data_p++); } // icarus entry void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0}; #else int main(int argc, char** argv) { const std::unique_ptr contextp{new VerilatedContext}; uint64_t sim_time = 1100; contextp->debug(0); contextp->commandArgs(argc, argv); // We're going to be checking for these errors so don't crash out contextp->fatalOnVpiError(0); const std::unique_ptr topp{new VM_PREFIX{contextp.get(), // Note null name - we're flattening it out ""}}; #ifdef VERILATOR #ifdef TEST_VERBOSE contextp->scopesDump(); #endif #endif #if VM_TRACE contextp->traceEverOn(true); VL_PRINTF("Enabling waves...\n"); VerilatedVcdC* tfp = new VerilatedVcdC; topp->trace(tfp, 99); tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); #endif topp->eval(); topp->clk = 0; contextp->timeInc(10); while (contextp->time() < sim_time && !contextp->gotFinish()) { contextp->timeInc(1); topp->eval(); VerilatedVpi::callValueCbs(); topp->clk = !topp->clk; // mon_do(); #if VM_TRACE if (tfp) tfp->dump(contextp->time()); #endif } if (!contextp->gotFinish()) { vl_fatal(FILENM, __LINE__, "main", "%Error: Timeout; never got a $finish"); } topp->final(); #if VM_TRACE if (tfp) tfp->close(); #endif return 0; } #endif verilator-5.042/test_regress/t/t_force_input_assign_bad.py0000755000542200017500000000106015101701376024452 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(expect_filename=test.golden_filename, verilator_flags2=['--error-limit 1000'], fails=True) test.passes() verilator-5.042/test_regress/t/t_class_reference_name_colision.py0000755000542200017500000000071415101701376026012 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.passes() verilator-5.042/test_regress/t/t_class_virtual_bad.out0000644000542200017500000000056415101701376023630 0ustar mahmoudyfreeshell%Error: t/t_class_virtual_bad.v:12:17: Illegal to call 'new' using an abstract virtual class 'VBase' (IEEE 1800-2023 8.21) : ... note: In instance 't' 12 | VBase b = new; | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_select_index.v0000644000542200017500000000224515101701376022251 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs clk ); // surefire lint_off NBAJAM input clk; reg [7:0] _ranit; reg [2:0] a; reg [7:0] vvector; reg [7:0] vvector_flip; // surefire lint_off STMINI initial _ranit = 0; always @ (posedge clk) begin a <= a + 3'd1; vvector[a] <= 1'b1; // This should use "old" value for a vvector_flip[~a] <= 1'b1; // This should use "old" value for a // //======== if (_ranit==8'd0) begin _ranit <= 8'd1; $write("[%0t] t_select_index: Running\n", $time); vvector <= 0; vvector_flip <= 0; a <= 3'b1; end else _ranit <= _ranit + 8'd1; // if (_ranit==8'd3) begin $write("%x %x\n",vvector,vvector_flip); if (vvector !== 8'b0000110) $stop; if (vvector_flip !== 8'b0110_0000) $stop; // $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_interface_gen13.v0000644000542200017500000000207315101701376022537 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty. // SPDX-License-Identifier: CC0-1.0 // bug998 interface intf #(parameter PARAM = 0) (); int p1; generate initial p1 = 1; endgenerate int p2; generate begin initial p2 = 1; end endgenerate int p3; int p3_no; if (PARAM == 1) initial p3 = 1; else initial p3_no = 1; int p4; int p4_no; case (PARAM) 1: initial p4 = 1; default: initial p4_no = 1; endcase int p5; for (genvar g=0; g<=PARAM; ++g) initial p5 = 1; endinterface module t(/*AUTOARG*/ // Inputs clk ); input clk; intf #(.PARAM(1)) my_intf (); always @ (posedge clk) begin if (my_intf.p1 != 1) $stop; if (my_intf.p2 != 1) $stop; if (my_intf.p3 != 1) $stop; if (my_intf.p3_no != 0) $stop; if (my_intf.p4 != 1) $stop; if (my_intf.p4_no != 0) $stop; if (my_intf.p5 != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_func_recurse.v0000644000542200017500000000110115101701376022254 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; function automatic int recurse_self; input int i; if (i == 0) recurse_self = 0; else recurse_self = i + recurse_self(i - 1) * 2; endfunction initial begin if (recurse_self(0) != 0) $stop; if (recurse_self(3) != (3 + 2*(2 + 2*(1)))) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_select_index2.v0000644000542200017500000000156615101701376022340 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg [7:0] x; wire [3:0] en; wire sel; wire a; // bug675 generate genvar g_k; for ( g_k = 0; g_k < 8; g_k = g_k + 1 ) begin: g_index always @* begin // Note this isn't a genif, but normal if // verilator lint_off SELRANGE if(g_k<4) begin x[g_k] = (sel == 1'b1) ? 1'b1 : (en[g_k] == 1'b0) ? 1'b1 : a; end else begin x[g_k] = (sel == 1'b0) ? 1'b1 : (en[g_k-4] == 1'b0) ? 1'b1 : a; end // verilator lint_on SELRANGE end end endgenerate endmodule verilator-5.042/test_regress/t/t_var_port_xml.out0000644000542200017500000001552115101701376022662 0ustar mahmoudyfreeshell verilator-5.042/test_regress/t/t_hierarchy_identifier_bad.out0000644000542200017500000000206315101701376025131 0ustar mahmoudyfreeshell%Error-ENDLABEL: t/t_hierarchy_identifier_bad.v:34:10: End label 'if_cnt_finish_bad' does not match begin label 'if_cnt_finish' 34 | end : if_cnt_finish_bad | ^~~~~~~~~~~~~~~~~ ... For error description see https://verilator.org/warn/ENDLABEL?v=latest %Error-ENDLABEL: t/t_hierarchy_identifier_bad.v:40:10: End label 'generate_for_bad' does not match begin label 'generate_for' 40 | end : generate_for_bad | ^~~~~~~~~~~~~~~~ %Error-ENDLABEL: t/t_hierarchy_identifier_bad.v:47:10: End label 'generate_if_if_bad' does not match begin label 'generate_if_if' 47 | end : generate_if_if_bad | ^~~~~~~~~~~~~~~~~~ %Error-ENDLABEL: t/t_hierarchy_identifier_bad.v:51:10: End label 'generate_if_else_bad' does not match begin label 'generate_if_else' 51 | end : generate_if_else_bad | ^~~~~~~~~~~~~~~~~~~~ %Error-ENDLABEL: t/t_hierarchy_identifier_bad.v:54:13: End label 't_bad' does not match begin label 't' 54 | endmodule : t_bad | ^~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_udp_bad_multi_output.v0000755000542200017500000000107115101701376024032 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 primitive t_gate(dout1, dout2, a, b, c); output dout1, dout2; input a, b, c; table x 0 1 : 1; 0 ? 1 : 1; 0 1 0 : 0; 1 1 ? : 1; 1 0 0 : 0; 0 0 0 : 1; endtable endprimitive module top (a, b, c, o1, o2); input a, b, c; output o1, o2; t_gate(o1, o2, a, b, c); endmodule verilator-5.042/test_regress/t/t_class_override_bad.out0000644000542200017500000002714115101701376023761 0ustar mahmoudyfreeshell%Error: t/t_class_override_bad.v:22:26: Member 'get_e' marked ':extends' but no base class function is being extend (IEEE 1800-2023 8.20) : ... note: In instance 't' 22 | function :extends int get_e; return 1; endfunction | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_class_override_bad.v:24:33: Member 'get_ef' marked ':extends' but no base class function is being extend (IEEE 1800-2023 8.20) : ... note: In instance 't' 24 | function :extends :final int get_ef; return 1; endfunction | ^~~~~~ %Error: t/t_class_override_bad.v:55:26: Member 'get_x_e' marked ':extends' but no base class function is being extend (IEEE 1800-2023 8.20) : ... note: In instance 't' 55 | function :extends int get_x_e; return 1; endfunction | ^~~~~~~ %Error: t/t_class_override_bad.v:56:33: Member 'get_x_ef' marked ':extends' but no base class function is being extend (IEEE 1800-2023 8.20) : ... note: In instance 't' 56 | function :extends :final int get_x_ef; return 1; endfunction | ^~~~~~~~ %Error: t/t_class_override_bad.v:64:26: Member 'get_n_i' is marked ':initial' but is being extended (IEEE 1800-2023 8.20) : ... note: In instance 't' 64 | function :initial int get_n_i; return 1; endfunction | ^~~~~~~ t/t_class_override_bad.v:18:17: ... Location of declaration being extended 18 | function int get_n_i; return 1; endfunction | ^~~~~~~ %Error: t/t_class_override_bad.v:65:33: Member 'get_n_if' is marked ':initial' but is being extended (IEEE 1800-2023 8.20) : ... note: In instance 't' 65 | function :initial :final int get_n_if; return 1; endfunction | ^~~~~~~~ t/t_class_override_bad.v:19:17: ... Location of declaration being extended 19 | function int get_n_if; return 1; endfunction | ^~~~~~~~ %Error: t/t_class_override_bad.v:73:26: Member 'get_i_i' is marked ':initial' but is being extended (IEEE 1800-2023 8.20) : ... note: In instance 't' 73 | function :initial int get_i_i; return 1; endfunction | ^~~~~~~ t/t_class_override_bad.v:30:26: ... Location of declaration being extended 30 | function :initial int get_i_i; return 1; endfunction | ^~~~~~~ %Error: t/t_class_override_bad.v:74:33: Member 'get_i_if' is marked ':initial' but is being extended (IEEE 1800-2023 8.20) : ... note: In instance 't' 74 | function :initial :final int get_i_if; return 1; endfunction | ^~~~~~~~ t/t_class_override_bad.v:31:26: ... Location of declaration being extended 31 | function :initial int get_i_if; return 1; endfunction | ^~~~~~~~ %Error: t/t_class_override_bad.v:77:17: Member 'get_if_n' is being extended from member marked ':final' (IEEE 1800-2023 8.20) : ... note: In instance 't' 77 | function int get_if_n; return 1; endfunction | ^~~~~~~~ t/t_class_override_bad.v:35:33: ... Location of ':final' declaration being extended 35 | function :initial :final int get_if_n; return 1; endfunction | ^~~~~~~~ %Error: t/t_class_override_bad.v:78:26: Member 'get_if_e' is being extended from member marked ':final' (IEEE 1800-2023 8.20) : ... note: In instance 't' 78 | function :extends int get_if_e; return 1; endfunction | ^~~~~~~~ t/t_class_override_bad.v:36:33: ... Location of ':final' declaration being extended 36 | function :initial :final int get_if_e; return 1; endfunction | ^~~~~~~~ %Error: t/t_class_override_bad.v:79:33: Member 'get_if_ef' is being extended from member marked ':final' (IEEE 1800-2023 8.20) : ... note: In instance 't' 79 | function :extends :final int get_if_ef; return 1; endfunction | ^~~~~~~~~ t/t_class_override_bad.v:37:33: ... Location of ':final' declaration being extended 37 | function :initial :final int get_if_ef; return 1; endfunction | ^~~~~~~~~ %Error: t/t_class_override_bad.v:80:26: Member 'get_if_i' is marked ':initial' but is being extended (IEEE 1800-2023 8.20) : ... note: In instance 't' 80 | function :initial int get_if_i; return 1; endfunction | ^~~~~~~~ t/t_class_override_bad.v:38:33: ... Location of declaration being extended 38 | function :initial :final int get_if_i; return 1; endfunction | ^~~~~~~~ %Error: t/t_class_override_bad.v:80:26: Member 'get_if_i' is being extended from member marked ':final' (IEEE 1800-2023 8.20) : ... note: In instance 't' 80 | function :initial int get_if_i; return 1; endfunction | ^~~~~~~~ t/t_class_override_bad.v:38:33: ... Location of ':final' declaration being extended 38 | function :initial :final int get_if_i; return 1; endfunction | ^~~~~~~~ %Error: t/t_class_override_bad.v:81:33: Member 'get_if_if' is marked ':initial' but is being extended (IEEE 1800-2023 8.20) : ... note: In instance 't' 81 | function :initial :final int get_if_if; return 1; endfunction | ^~~~~~~~~ t/t_class_override_bad.v:39:33: ... Location of declaration being extended 39 | function :initial :final int get_if_if; return 1; endfunction | ^~~~~~~~~ %Error: t/t_class_override_bad.v:81:33: Member 'get_if_if' is being extended from member marked ':final' (IEEE 1800-2023 8.20) : ... note: In instance 't' 81 | function :initial :final int get_if_if; return 1; endfunction | ^~~~~~~~~ t/t_class_override_bad.v:39:33: ... Location of ':final' declaration being extended 39 | function :initial :final int get_if_if; return 1; endfunction | ^~~~~~~~~ %Error: t/t_class_override_bad.v:82:24: Member 'get_if_f' is being extended from member marked ':final' (IEEE 1800-2023 8.20) : ... note: In instance 't' 82 | function :final int get_if_f; return 1; endfunction | ^~~~~~~~ t/t_class_override_bad.v:40:33: ... Location of ':final' declaration being extended 40 | function :initial :final int get_if_f; return 1; endfunction | ^~~~~~~~ %Error: t/t_class_override_bad.v:84:17: Member 'get_f_n' is being extended from member marked ':final' (IEEE 1800-2023 8.20) : ... note: In instance 't' 84 | function int get_f_n; return 1; endfunction | ^~~~~~~ t/t_class_override_bad.v:43:24: ... Location of ':final' declaration being extended 43 | function :final int get_f_n; return 1; endfunction | ^~~~~~~ %Error: t/t_class_override_bad.v:85:26: Member 'get_f_e' is being extended from member marked ':final' (IEEE 1800-2023 8.20) : ... note: In instance 't' 85 | function :extends int get_f_e; return 1; endfunction | ^~~~~~~ t/t_class_override_bad.v:44:24: ... Location of ':final' declaration being extended 44 | function :final int get_f_e; return 1; endfunction | ^~~~~~~ %Error: t/t_class_override_bad.v:86:33: Member 'get_f_ef' is being extended from member marked ':final' (IEEE 1800-2023 8.20) : ... note: In instance 't' 86 | function :extends :final int get_f_ef; return 1; endfunction | ^~~~~~~~ t/t_class_override_bad.v:45:24: ... Location of ':final' declaration being extended 45 | function :final int get_f_ef; return 1; endfunction | ^~~~~~~~ %Error: t/t_class_override_bad.v:87:26: Member 'get_f_i' is marked ':initial' but is being extended (IEEE 1800-2023 8.20) : ... note: In instance 't' 87 | function :initial int get_f_i; return 1; endfunction | ^~~~~~~ t/t_class_override_bad.v:46:24: ... Location of declaration being extended 46 | function :final int get_f_i; return 1; endfunction | ^~~~~~~ %Error: t/t_class_override_bad.v:87:26: Member 'get_f_i' is being extended from member marked ':final' (IEEE 1800-2023 8.20) : ... note: In instance 't' 87 | function :initial int get_f_i; return 1; endfunction | ^~~~~~~ t/t_class_override_bad.v:46:24: ... Location of ':final' declaration being extended 46 | function :final int get_f_i; return 1; endfunction | ^~~~~~~ %Error: t/t_class_override_bad.v:88:33: Member 'get_f_if' is marked ':initial' but is being extended (IEEE 1800-2023 8.20) : ... note: In instance 't' 88 | function :initial :final int get_f_if; return 1; endfunction | ^~~~~~~~ t/t_class_override_bad.v:47:24: ... Location of declaration being extended 47 | function :final int get_f_if; return 1; endfunction | ^~~~~~~~ %Error: t/t_class_override_bad.v:88:33: Member 'get_f_if' is being extended from member marked ':final' (IEEE 1800-2023 8.20) : ... note: In instance 't' 88 | function :initial :final int get_f_if; return 1; endfunction | ^~~~~~~~ t/t_class_override_bad.v:47:24: ... Location of ':final' declaration being extended 47 | function :final int get_f_if; return 1; endfunction | ^~~~~~~~ %Error: t/t_class_override_bad.v:89:24: Member 'get_f_f' is being extended from member marked ':final' (IEEE 1800-2023 8.20) : ... note: In instance 't' 89 | function :final int get_f_f; return 1; endfunction | ^~~~~~~ t/t_class_override_bad.v:48:24: ... Location of ':final' declaration being extended 48 | function :final int get_f_f; return 1; endfunction | ^~~~~~~ %Error: t/t_class_override_bad.v:101:42: Class 'CClsBadExtendsFinal' is being extended from class marked ':final' (IEEE 1800-2023 8.20) : ... note: In instance 't' 101 | class :final CClsBadExtendsFinal extends CClsF; | ^~~~~ t/t_class_override_bad.v:98:1: ... Location of ':final' class being extended 98 | class :final CClsF extends CBase; | ^~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_event_control_star_never.py0000755000542200017500000000101215101701376025071 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--binary', '-Wno-ALWNEVER']) test.execute() test.passes() verilator-5.042/test_regress/t/t_x_rand_mt_stability_zeros.out0000644000542200017500000000076315101701376025431 0ustar mahmoudyfreeshelluninitialized = 0x00000000 x_assigned (initial) = 0x00000000 uninitialized2 = 0x00000000 big = 0x0000000000000000000000000000000000000000000000000000000000000000 random_init = 0x952aaa76 top.t.the_sub_yes_inline_1 no_init 0x0 top.t.the_sub_yes_inline_2 no_init 0x0 top.t.the_sub_no_inline_1 no_init 0x0 top.t.the_sub_no_inline_2 no_init 0x0 rand = 0xb3cf9302 rand = 0xf0acf3e4 rand = 0xca0ac74c rand = 0x4eddfc2c rand = 0x1919db69 x_assigned = 0x486aeb2d Last rand = 0x2d118c9b *-* All Finished *-* verilator-5.042/test_regress/t/t_clk_2in.v0000644000542200017500000000766015101701376021132 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `ifndef VERILATOR module t; /*AUTOREGINPUT*/ // Beginning of automatic reg inputs (for undeclared instantiated-module inputs) reg c0; // To t2 of t2.v reg c1; // To t2 of t2.v reg check; // To t2 of t2.v reg [1:0] clks; // To t2 of t2.v // End of automatics t2 t2 (/*AUTOINST*/ // Inputs .clks (clks[1:0]), .c0 (c0), .c1 (c1), .check (check)); task clockit (input v1, v0); c1 = v1; c0 = v0; clks[1] = v1; clks[0] = v0; `ifdef TEST_VERBOSE $write("[%0t] c1=%x c0=%x\n", $time,v0,v1); `endif #1; endtask initial begin check = '0; c0 = '0; c1 = '0; clks = '0; #1 t2.clear(); #10; for (int i=0; i<2; i++) begin clockit(0, 0); clockit(0, 0); clockit(0, 1); clockit(1, 1); clockit(0, 0); clockit(1, 1); clockit(1, 0); clockit(0, 0); clockit(1, 0); clockit(0, 1); clockit(0, 0); end check = 1; clockit(0, 0); end endmodule `endif `ifdef VERILATOR `define t2 t `else `define t2 t2 `endif module `t2 ( input [1:0] clks, input c0, input c1, input check ); `ifdef T_CLK_2IN_VEC wire clk0 = clks[0]; wire clk1 = clks[1]; `else wire clk0 = c0; wire clk1 = c1; `endif integer p0 = 0; integer p1 = 0; integer p01 = 0; integer n0 = 0; integer n1 = 0; integer n01 = 0; integer vp = 0; integer vn = 0; integer vpn = 0; task clear; `ifdef TEST_VERBOSE $display("[%0t] clear\n", $time); `endif p0 = 0; p1 = 0; p01 = 0; n0 = 0; n1 = 0; n01 = 0; vp = 0; vn = 0; vpn = 0; endtask `define display_counts(text) begin \ $write("[%0t] ", $time); \ `ifdef T_CLK_2IN_VEC $write(" 2v "); `endif \ $write(text); \ $write(": %0d %0d %0d %0d %0d %0d %0d %0d %0d\n", p0, p1, p01, n0, n1, n01, vp, vn, vpn); \ end always @ (posedge clk0) begin p0 = p0 + 1; // Want blocking, so don't miss clock counts `ifdef TEST_VERBOSE `display_counts("posedge 0"); `endif end always @ (posedge clk1) begin p1 = p1 + 1; `ifdef TEST_VERBOSE `display_counts("posedge 1"); `endif end always @ (posedge clk0 or posedge clk1) begin p01 = p01 + 1; `ifdef TEST_VERBOSE `display_counts("posedge *"); `endif end always @ (negedge clk0) begin n0 = n0 + 1; `ifdef TEST_VERBOSE `display_counts("negedge 0"); `endif end always @ (negedge clk1) begin n1 = n1 + 1; `ifdef TEST_VERBOSE `display_counts("negedge 1"); `endif end always @ (negedge clk0 or negedge clk1) begin n01 = n01 + 1; `ifdef TEST_VERBOSE `display_counts("negedge *"); `endif end `ifndef VERILATOR always @ (posedge clks) begin vp = vp + 1; `ifdef TEST_VERBOSE `display_counts("pos vec"); `endif end always @ (negedge clks) begin vn = vn + 1; `ifdef TEST_VERBOSE `display_counts("neg vec"); `endif end always @ (posedge clks or negedge clks) begin vpn = vpn + 1; `ifdef TEST_VERBOSE `display_counts("or vec"); `endif end `endif always @ (posedge check) begin if (p0!=6) $stop; if (p1!=6) $stop; if (p01!=10) $stop; if (n0!=6) $stop; if (n1!=6) $stop; if (n01!=10) $stop; `ifndef VERILATOR if (vp!=6) $stop; if (vn!=6) $stop; if (vpn!=12) $stop; `endif $write("*-* All Finished *-*\n"); end endmodule verilator-5.042/test_regress/t/t_param_type_bad3.out0000644000542200017500000000041015101701376023167 0ustar mahmoudyfreeshell%Error: t/t_param_type_bad3.v:9:26: Expecting a data type: 'PI' 9 | localparam type P_T = PI; | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_constraint_pure.py0000755000542200017500000000104615101701376023206 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_dpi_shortcircuit_c.cpp0000644000542200017500000000345215101701376024001 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2011-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "svdpi.h" #include #include //====================================================================== // clang-format off #if defined(VERILATOR) # if defined(T_DPI_SHORTCIRCUIT) # include "Vt_dpi_shortcircuit__Dpi.h" # elif defined(T_DPI_SHORTCIRCUIT2) # include "Vt_dpi_shortcircuit2__Dpi.h" # else # error "Unknown test" # endif #elif defined(VCS) # include "../vc_hdrs.h" #elif defined(CADENCE) # define NEED_EXTERNS #else # error "Unknown simulator for DPI test" #endif // clang-format on #ifdef NEED_EXTERNS extern "C" { extern void dpii_clear(); extern int dpii_count(int idx); extern unsigned char dpii_inc0(int idx); extern unsigned char dpii_inc1(int idx); extern unsigned char dpii_incx(int idx, unsigned char value); } #endif //====================================================================== #define COUNTERS 16 static int global_count[COUNTERS]; void dpii_clear() { for (int i = 0; i < COUNTERS; ++i) global_count[i] = 0; } int dpii_count(int idx) { return (idx >= 0 && idx < COUNTERS) ? global_count[idx] : -1; } unsigned char dpii_incx(int idx, unsigned char value) { if (idx >= 0 && idx < COUNTERS) ++global_count[idx]; return value; } unsigned char dpii_inc0(int idx) { return dpii_incx(idx, 0); } unsigned char dpii_inc1(int idx) { return dpii_incx(idx, 1); } verilator-5.042/test_regress/t/t_gantt.v0000644000542200017500000000304115101701376020713 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t( input clk ); integer cyc = 0; wire [63:0] result; Test test(/*AUTOINST*/ // Outputs .result (result[63:0]), // Inputs .clk (clk), .cyc (cyc)); reg [63:0] sum; always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d result=%x\n", $time, cyc, result); `endif cyc <= cyc + 1; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc == 0) begin // Setup sum <= '0; end else if (cyc < 10) begin sum <= '0; end else if (cyc == 99) begin $write("[%0t] cyc==%0d sum=%x\n", $time, cyc, sum); // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'haf665a181ead5e12 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test(/*AUTOARG*/ // Outputs result, // Inputs clk, cyc ); input clk; input int cyc; output reg [63:0] result; logic [63:0] adder; import "DPI-C" pure function int dpii_return(input int i); always @(posedge clk) begin adder = 0; for (int i = 0; i < 100000; ++i) adder += {32'h0, (cyc+i)} ** 3 + {32'h0, dpii_return(1)}; result <= adder; end endmodule verilator-5.042/test_regress/t/t_display_wide_bad.py0000755000542200017500000000076315101701376023257 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_sys_readmem_bad_digit.out0000644000542200017500000000014515101701376024440 0ustar mahmoudyfreeshell%Error: t/t_sys_readmem_bad_digit.mem:8: $readmemb (binary) file contains hex characters Aborting... verilator-5.042/test_regress/t/t_inst_misarray_bad.py0000755000542200017500000000076615101701376023471 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_tri_inz.cpp0000644000542200017500000000260115101701376021572 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include "Vt_tri_inz.h" #include "Vt_tri_inz___024root.h" VM_PREFIX* tb = nullptr; bool pass = true; double sc_time_stamp() { return 0; } void checkone(const char* name, int got, int exp) { if (got != exp) { printf("%%Error: For %s got=%d exp=%d\n", name, got, exp); pass = false; } } void check(int d, int en, int exp0, int exp1, int expx, int expz) { tb->d = d; tb->rootp->d__en0 = en; tb->eval(); #ifdef TEST_VERBOSE printf("Drive d=%d en=%d got0=%d/1=%d/x=%d/z=%d exp0=%d/1=%d/x=%d/z=%d\n", d, en, tb->ext0, tb->ext1, tb->extx, tb->extz, exp0, exp1, expx, expz); #endif if (!expz) checkone("ext0", tb->ext0, exp0); if (!expz) checkone("ext1", tb->ext1, exp1); checkone("extx", tb->extx, expx); checkone("extz", tb->extz, expz); } int main() { Verilated::debug(0); tb = new VM_PREFIX{"tb"}; check(0, 1, 1, 0, 0, 0); check(1, 1, 0, 1, 0, 0); check(0, 0, 0, 0, 0, 1); if (pass) { VL_PRINTF("*-* All Finished *-*\n"); tb->final(); } else { vl_fatal(__FILE__, __LINE__, "top", "Unexpected results from t_tri_inz\n"); } VL_DO_DANGLING(delete tb, tb); return 0; } verilator-5.042/test_regress/t/t_opt_life_off.py0000755000542200017500000000164215101701376022424 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.top_filename = "t/t_opt_life.v" test.compile(verilator_flags2=['--stats', '-fno-life', '-fno-life-post']) if test.vlt_all: test.file_grep_not(test.stats, r'Optimizations, Lifetime assign deletions\s+(\d+)') test.file_grep_not(test.stats, r'Optimizations, Lifetime creset deletions\s+(\d+)') test.file_grep_not(test.stats, r'Optimizations, Lifetime constant prop\s+(\d+)') test.file_grep_not(test.stats, r'Optimizations, Lifetime postassign deletions\s+(\d+)') test.passes() verilator-5.042/test_regress/t/t_trace_two_dump_cc.py0000755000542200017500000000245215101701376023452 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Test tracing with two models instanced import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t_trace_two_a.v" test.pli_filename = "t/t_trace_two_cc.cpp" test.compile(make_main=False, verilator_make_gmake=False, top_filename='t_trace_two_b.v', vm_prefix='Vt_trace_two_b', verilator_flags2=['-trace']) test.run(logfile=test.obj_dir + "/make_first_ALL.log", cmd=[ os.environ["MAKE"], "-C", "" + test.obj_dir, "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp" ]) test.compile(make_main=False, top_filename='t_trace_two_a.v', verilator_flags2=['-exe', '-trace', test.pli_filename], v_flags2=['+define+TEST_DUMP']) test.execute() if test.vlt_all: test.file_grep(test.trace_filename, r'\$enddefinitions') test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface_generic_modport_function2.v0000644000542200017500000000121115101701376026762 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 interface inf; int v; function int get(); return v; endfunction modport mp( output v ); endinterface interface inf2; int k; endinterface module GenericModule (interface.mp a); initial begin a.v = 5; end endmodule module t; inf inf_inst(); GenericModule genericModule (inf_inst); initial begin #1; if(inf_inst.get() != 5) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_alias_var_bad.v0000644000542200017500000000061515101701376022351 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias' // // Alias width check error test. // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ // Inputs clk ); input clk; logic [31:0] a; logic [31:0] b; alias a = b; endmodule verilator-5.042/test_regress/t/t_extend_class.py0000755000542200017500000000072615101701376022447 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_func_twocall.v0000644000542200017500000000337415101701376022267 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; reg [7:0] crc; wire [61:59] ah = crc[5:3]; wire [61:59] bh = ~crc[4:2]; wire [41:2] al = {crc,crc,crc,crc,crc}; wire [41:2] bl = ~{crc[6:0],crc[6:0],crc[6:0],crc[6:0],crc[6:0],crc[6:2]}; reg sel; wire [61:28] q = ( sel ? func(ah, al) : func(bh, bl)); function [61:28] func; input [61:59] inh; input [41:2] inl; reg [42:28] func_mid; reg carry; begin carry = &inl[27:2]; func_mid = {1'b0,inl[41:28]} + {14'b0, carry}; func[61:59] = inh + {2'b0, func_mid[42]}; func[58:42] = {17{func_mid[41]}}; func[41:28] = func_mid[41:28]; end endfunction integer cyc; initial cyc=1; always @ (posedge clk) begin //$write("%d %x\n", cyc, q); if (cyc!=0) begin cyc <= cyc + 1; sel <= ~sel; crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; if (cyc==1) begin sel <= 1'b1; crc <= 8'h12; end if (cyc==2) if (q!=34'h100000484) $stop; if (cyc==3) if (q!=34'h37fffeddb) $stop; if (cyc==4) if (q!=34'h080001212) $stop; if (cyc==5) if (q!=34'h1fffff7ef) $stop; if (cyc==6) if (q!=34'h200000848) $stop; if (cyc==7) if (q!=34'h380001ebd) $stop; if (cyc==8) if (q!=34'h07fffe161) $stop; if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.042/test_regress/t/t_assert_synth_full.vlt0000644000542200017500000000041415101701376023707 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. // SPDX-License-Identifier: CC0-1.0 `verilator_config full_case -file "t/t_assert_synth.v" -lines 32 verilator-5.042/test_regress/t/t_order_dpi_export_7.v0000644000542200017500000000205015101701376023373 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2022 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module testbench; logic clk; logic data; export "DPI-C" function set_inputs; function void set_inputs(bit val); clk = val; data = val; endfunction; // This needs to be in the 'ico' region. Written with $c1 to prevent // gate optimization. wire invdata = $c1(1) ^ data; int n = 0; always @(edge clk) begin // The combinational update needs to have take effect (in the 'ico' // region), before this always block is executed if (invdata != ~data) $stop; $display("t=%t n=%d", $time, n); if ($time != (1*n+1) * 500) $stop; if (n == 20) begin $write("*-* All Finished *-*\n"); $finish; end n += 1; end endmodule verilator-5.042/test_regress/t/t_benchmarksim.py0000755000542200017500000000340215101701376022430 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_gen_alw.v" # Use any top file test.init_benchmarksim() # As an example, compile and simulate the top file with varying optimization level l_opts = ['-O0', '-O1', '-O2', '-O3'] for l_opt in l_opts: test.compile(benchmarksim=1, v_flags2=[l_opt]) test.execute() filename = test.benchmarksim_filename gotn = 0 with open(filename, 'r', encoding="utf8") as fh: lineno = 0 headered = False for line in fh: lineno += 1 if re.match(r'^#', line): continue if not headered: headered = True if not re.search(r'evals, ', line): test.error(filename + ":" + str(lineno) + ": Expected header but found: " + line) else: m = re.search(r'(\d+\.?\d*),(\d+\.?\d*)', line) if not m: test.error(filename + ":" + str(lineno) + ": Expected 2 tokens on line: " + line) continue cycles = float(m.group(1)) time = float(m.group(2)) if cycles <= 0.0 or time <= 0.0: test.error(filename + ":" + str(lineno) + ": Invalid data on line: " + line) continue gotn += 1 n_lines_expected = len(l_opts) if gotn != int(n_lines_expected): test.error("Expected " + str(n_lines_expected) + " lines but found " + str(gotn)) test.passes() verilator-5.042/test_regress/t/t_enum_bad_circdecl.out0000644000542200017500000000104315101701376023542 0ustar mahmoudyfreeshell%Error: t/t_enum_bad_circdecl.v:10:41: Typedef has self-reference: 'bad_redecl' : ... note: In instance 't' 10 | typedef enum bad_redecl [2:0] {VALUE} bad_redecl; | ^~~~~~~~~~ t/t_enum_bad_circdecl.v:10:16: ... Location of reference 10 | typedef enum bad_redecl [2:0] {VALUE} bad_redecl; | ^~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_queue_insert_at_end.v0000644000542200017500000000077215101701376023630 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t(); initial begin int queue[$]; queue.insert(0, 0); if (queue.size() != 1) $stop; queue.insert(1, 1); if (queue.size() != 2) $stop; if (queue[0] != 0) $stop; if (queue[1] != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_force_struct_partial.v0000644000542200017500000000143215101701376024016 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) typedef struct packed { logic sig1; logic sig2; logic not_forced; } s1; module t(clk); input clk; s1 s1inst; logic a = 1'b0; logic b; initial force s1inst.sig1 = a; always @(posedge clk) begin force s1inst.sig2 = 1'b1; force s1inst.sig1 = b; `checkh(s1inst.sig1, b); `checkh(s1inst.sig2, 1'b1); $finish; end endmodule verilator-5.042/test_regress/t/t_lint_misindent_bad.v0000644000542200017500000000206615101701376023432 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Do not reindent - spaces are critical to this test // verilator lint_off UNUSEDLOOP module t; initial begin if (0) $display("ok"); $display("bad1"); // <--- Bad if (0) $display("ok"); else $display("ok"); $display("bad2"); // <--- Bad for (;0;) $display("ok"); $display("bad3"); // <--- Bad while (0) $display("ok"); $display("bad4"); // <--- Bad // Normal styles if (0) $display("ok"); $display("ok"); for (;0;) $display("ok"); $display("ok"); while (0) $display("ok"); $display("ok"); // Questionable but pops up in some cases e.g. SweRV // (all statements have similar indent) if (0) begin $display("ok"); end $display("ok"); end endmodule verilator-5.042/test_regress/t/t_lint_waitconst_bad.out0000644000542200017500000000125115101701376024010 0ustar mahmoudyfreeshell%Warning-WAITCONST: t/t_timing_wait1.v:52:12: Wait statement condition is constant 52 | wait(1); | ^ ... For warning description see https://verilator.org/warn/WAITCONST?v=latest ... Use "/* verilator lint_off WAITCONST */" and lint_on around source to disable this message. %Warning-WAITCONST: t/t_timing_wait1.v:54:14: Wait statement condition is constant 54 | wait(0 < 1) $write("*-* All Finished *-*\n"); | ^ %Warning-WAITCONST: t/t_timing_wait1.v:59:19: Wait statement condition is constant 59 | initial wait(1 == 0) $stop; | ^~ %Error: Exiting due to verilator-5.042/test_regress/t/t_class_extends_this3.py0000755000542200017500000000073415101701376023743 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_unsup_bad.out0000644000542200017500000000134215101701376023307 0ustar mahmoudyfreeshell%Error: t/t_class_unsup_bad.v:24:21: Syntax error: 'static'/'virtual'/'rand'/'randc' not allowed before typedef declaration 24 | rand typedef int irand_t; | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_class_unsup_bad.v:25:22: Syntax error: 'static'/'virtual'/'rand'/'randc' not allowed before typedef declaration 25 | randc typedef int icrand_t; | ^~~~~~~~ %Error: t/t_class_unsup_bad.v:31:24: Syntax error: 'const'/'rand'/'randc' not allowed before function/task declaration 31 | const function void func_const; endfunction | ^~~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_vlcov_data_b.dat0000644000542200017500000000026715101701376022533 0ustar mahmoudyfreeshell# SystemC::Coverage-3 C 'CoverPoint2ffile1.sphl159' 10 C 'CoverPoint3ffile1.sphl159' 0 C 'CoverPoint4ffile1.sphl159' 1 C 'CoverPoint5ffile1.sphl159' 9 verilator-5.042/test_regress/t/t_struct_unpacked_init.py0000755000542200017500000000076615101701376024220 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_gen_self_return.v0000644000542200017500000000303215101701376022757 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Roman Popov. // SPDX-License-Identifier: CC0-1.0 module dut #( parameter DEPTH = 16, parameter WIDTH = 32, parameter RAM_SPLIT_WIDTH = 16 ) ( output logic [WIDTH-1:0] ram_dataout ); localparam RAM_ADDR_WIDTH = $clog2(DEPTH); // = 4 localparam NUM_RAM_BLOCKS = (WIDTH/RAM_SPLIT_WIDTH) + {31'h0, ((WIDTH % RAM_SPLIT_WIDTH) > 0)}; // = 2 typedef logic [NUM_RAM_BLOCKS:0][31:0] block_index_t; // width 96 function automatic block_index_t index_calc(input int WIDTH, NUM_RAM_BLOCKS); index_calc[0] = '0; for(int i = 0; i < NUM_RAM_BLOCKS; i++) index_calc[i+1] = WIDTH/NUM_RAM_BLOCKS + {31'h0, (i < (WIDTH%NUM_RAM_BLOCKS))}; for(int i = 0; i < NUM_RAM_BLOCKS; i++) index_calc[i+1] = index_calc[i+1] + index_calc[i]; // bug1467 was this return return index_calc; endfunction localparam block_index_t RAM_BLOCK_INDEX = index_calc(WIDTH, NUM_RAM_BLOCKS); generate begin : ram_dataout_gen for (genvar i = 0; i < NUM_RAM_BLOCKS; i++) begin always_comb ram_dataout[RAM_BLOCK_INDEX[i+1]-1:RAM_BLOCK_INDEX[i]] = 0; end end endgenerate initial begin if (RAM_BLOCK_INDEX != {32'd32, 32'd16, 32'd0}) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module t ( input clk, output logic [31:0] ram_dataout ); dut dut0(.*); endmodule verilator-5.042/test_regress/t/t_sys_file_scan.dat0000644000542200017500000000000615101701376022720 0ustar mahmoudyfreeshell1 2 3 verilator-5.042/test_regress/t/t_func_unit.v0000644000542200017500000000071215101701376021572 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 task tsk(output tfo); tfo = 1'b0; endtask module t (/*AUTOARG*/ // Outputs to ); output reg to[2:0]; integer i = 0; initial begin tsk(to[i]); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_foreach_sideeff_uvm.py0000755000542200017500000000073715101701376023760 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_vpi_escape.py0000755000542200017500000000176115101701376022111 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.pli_filename = "t/t_vpi_escape.cpp" test.compile(make_top_shell=False, make_main=False, make_pli=True, sim_time=100, iv_flags2=["-g2005-sv -D USE_VPI_NOT_DPI -DWAVES"], v_flags2=["+define+USE_VPI_NOT_DPI"], verilator_flags2=["--exe --vpi --no-l2name t/t_vpi_escape.vlt", test.pli_filename]) test.execute( # run_env = "VPI_TRACE=" . Cwd::getcwd() . "/" + test.obj_dir + "/" + test.name + "_vpi.log", # run_env = "VPI_TRACE=/tmp/"+test.name+"_vpi.log", use_libvpi=True) test.passes() verilator-5.042/test_regress/t/t_langext_2.py0000755000542200017500000000101315101701376021644 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') # This is a compile only test. test.compile(v_flags2=["+systemverilogext+v"]) test.passes() verilator-5.042/test_regress/t/t_interface_import_param.py0000755000542200017500000000073415101701376024504 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_randc_oversize_bad.v0000644000542200017500000000053215101701376023423 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls; randc bit [37:0] i; endclass module t; Cls c; initial begin c = new; c.randomize; end endmodule verilator-5.042/test_regress/t/t_unroll_pragma_none.py0000755000542200017500000000172515101701376023654 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_unroll_pragma.v" test.compile(verilator_flags2=['--unroll-count 4 --unroll-stmts 9999 --stats -DTEST_NONE'], verilator_make_gmake=False, make_top_shell=False, make_main=False) test.file_grep(test.stats, r'Optimizations, Loop unrolling, Unrolled loops\s+(\d+)', 3) test.file_grep(test.stats, r'Optimizations, Loop unrolling, Unrolled iterations\s+(\d+)', 9) test.file_grep(test.stats, r'Optimizations, Loop unrolling, Failed - reached --unroll-count\s+(\d+)', 2) test.passes() verilator-5.042/test_regress/t/t_param_const_part.py0000755000542200017500000000073415101701376023326 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_vlcov_opt_toggle.info.out0000644000542200017500000000322315101701376024450 0ustar mahmoudyfreeshellTN:verilator_coverage SF:t/t_cover_line.v DA:12,19 DA:14,2 DA:20,11 BRDA:20,0,0,11 BRDA:20,0,1,5 BRDA:20,0,2,2 BRDA:20,0,3,1 BRDA:20,0,4,0 BRDA:20,0,5,0 BRDA:20,0,6,0 BRDA:20,0,7,0 DA:138,38 DA:139,4 DA:159,38 DA:160,4 DA:210,19 DA:211,2 DA:241,19 DA:242,2 DA:261,19 DA:262,10 BRDA:262,0,0,10 BRDA:262,0,1,5 BRDA:262,0,2,2 BRDA:262,0,3,1 DA:309,19 BRDA:309,0,0,19 BRDA:309,0,1,11 BRDA:309,0,2,0 BRDA:309,0,3,0 BRDA:309,0,4,0 BRDA:309,0,5,0 BRDA:309,0,6,0 BRDA:309,0,7,0 BRDA:309,0,8,0 BRDA:309,0,9,0 BRDA:309,0,10,0 BRDA:309,0,11,0 BRDA:309,0,12,5 BRDA:309,0,13,0 BRDA:309,0,14,0 BRDA:309,0,15,0 BRDA:309,0,16,0 BRDA:309,0,17,0 BRDA:309,0,18,0 BRDA:309,0,19,0 BRDA:309,0,20,0 BRDA:309,0,21,0 BRDA:309,0,22,0 BRDA:309,0,23,2 BRDA:309,0,24,0 BRDA:309,0,25,0 BRDA:309,0,26,1 BRDA:309,0,27,0 BRDA:309,0,28,0 BRDA:309,0,29,0 BRDA:309,0,30,0 BRDA:309,0,31,0 BRDA:309,0,32,0 DA:310,19 BRDA:310,0,0,0 BRDA:310,0,1,2 BRDA:310,0,2,19 BRDA:310,0,3,6 BRDA:310,0,4,7 BRDA:310,0,5,1 BRDA:310,0,6,19 BRDA:310,0,7,3 BRDA:310,0,8,0 BRDA:310,0,9,0 BRDA:310,0,10,0 DA:311,1 BRDA:311,0,0,1 BRDA:311,0,1,1 BRDA:311,0,2,0 BRDA:311,0,3,0 BRDA:311,0,4,0 BRDA:311,0,5,0 DA:313,2 BRDA:313,0,0,0 BRDA:313,0,1,2 BRDA:313,0,2,0 BRDA:313,0,3,0 BRDA:313,0,4,0 BRDA:313,0,5,0 BRDA:313,0,6,0 BRDA:313,0,7,0 BRDA:313,0,8,2 BRDA:313,0,9,0 BRDA:313,0,10,0 BRDA:313,0,11,0 BRDA:313,0,12,0 BRDA:313,0,13,0 BRDA:313,0,14,0 BRDA:313,0,15,0 BRDA:313,0,16,0 BRDA:313,0,17,0 BRDA:313,0,18,0 BRDA:313,0,19,0 BRDA:313,0,20,0 BRDA:313,0,21,0 BRDA:313,0,22,0 BRDA:313,0,23,0 BRDA:313,0,24,0 BRDA:313,0,25,0 BRDA:313,0,26,0 BRDA:313,0,27,0 BRDA:313,0,28,0 BRDA:313,0,29,0 BRDA:313,0,30,0 BRDA:313,0,31,0 BRF:94 BRH:6 end_of_record verilator-5.042/test_regress/t/t_class_nested_link.v0000644000542200017500000000201215101701376023257 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Anthony Donlon. // SPDX-License-Identifier: CC0-1.0 /// Test for bug4553 // bit0: 'new' called // bit1: 'myfunc' called // bit2: 'myfunc' in class called int calls = 0; module t; // int calls = 0; // TODO: Error: Internal Error: Can't locate varref scope function void myfunc(); calls |= 32'b10; endfunction : myfunc class Cls #(int A = 0); function new(); calls |= 32'b1; endfunction : new function void myfunc(); calls |= 32'b100; endfunction : myfunc endclass Cls #(100) cls; // this block is following the definition of Cls initial begin cls = new; myfunc(); if (calls != 32'b011) begin $write("calls: %0b\n", calls); $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_math_real_public.v0000644000542200017500000000073215101701376023074 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2018 by Alex Solomatnikov // SPDX-License-Identifier: CC0-1.0 module t; sub #(.REAL_PARAM(2.0)) sub(); endmodule module sub (); parameter REAL_PARAM = 0.0; // Magic name grepped for in .py file initial begin $display("REAL_PARAM=%g", REAL_PARAM); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_sys_file_basic.out0000644000542200017500000000026415101701376023122 0ustar mahmoudyfreeshell[0] hello v=12345667 [0] Hello2 d: 12 12 h: 0000000c 0000000c o: 00000000014 00000000014 b: 00000000000000000000000000001100 00000000000000000000000000001100 verilator-5.042/test_regress/t/t_clk_powerdn.py0000755000542200017500000000073415101701376022301 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_covergroup_extends_newfirst.v0000644000542200017500000000233115101701376025445 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off COVERIGN */ module t; class base; function new(); g1 = new(0); endfunction enum {red, green, blue} color; covergroup g1 (bit [3:0] a) with function sample(bit b); option.weight = 10; option.per_instance = 1; coverpoint a; coverpoint b; c: coverpoint color; endgroup endclass class derived extends base; bit d; function new(); super.new(); endfunction covergroup extends g1; option.weight = 1; // overrides the weight from base g1 // uses per_instance = 1 from base g1 c: coverpoint color // overrides the c coverpoint in base g1 { ignore_bins ignore = {blue}; } coverpoint d; // adds new coverpoint cross a, d; // crosses new coverpoint with inherited one endgroup :g1 endclass endmodule verilator-5.042/test_regress/t/t_flag_incdir.v0000644000542200017500000000047015101701376022042 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `include "t_flag_f_tsub_inc.v" `ifndef GOT_DEF5 `error "No GOT_DEF5" `endif module t; endmodule verilator-5.042/test_regress/t/t_lint_genunnamed_bad.out0000644000542200017500000000347715101701376024132 0ustar mahmoudyfreeshell%Warning-GENUNNAMED: t/t_lint_genunnamed_bad.v:14:6: Unnamed generate block 'genblk2' (IEEE 1800-2023 27.6) : ... Suggest assign a label with 'begin : gen_' 14 | begin | ^~~~~ ... For warning description see https://verilator.org/warn/GENUNNAMED?v=latest ... Use "/* verilator lint_off GENUNNAMED */" and lint_on around source to disable this message. %Warning-GENUNNAMED: t/t_lint_genunnamed_bad.v:18:6: Unnamed generate block 'genblk2' (IEEE 1800-2023 27.6) : ... Suggest assign a label with 'begin : gen_' 18 | begin | ^~~~~ %Warning-GENUNNAMED: t/t_lint_genunnamed_bad.v:22:4: Unnamed generate block 'genblk3' (IEEE 1800-2023 27.6) : ... Suggest assign a label with 'begin : gen_' 22 | for (genvar v = 0; v < P; ++v) ; | ^~~ %Warning-GENUNNAMED: t/t_lint_genunnamed_bad.v:24:4: Unnamed generate block 'genblk4' (IEEE 1800-2023 27.6) : ... Suggest assign a label with 'begin : gen_' 24 | for (genvar v = 0; v < P; ++v) | ^~~ %Warning-GENUNNAMED: t/t_lint_genunnamed_bad.v:30:9: Unnamed generate block 'genblk5' (IEEE 1800-2023 27.6) : ... Suggest assign a label with 'begin : gen_' 30 | 1: initial begin end | ^~~~~~~ %Warning-GENUNNAMED: t/t_lint_genunnamed_bad.v:31:9: Unnamed generate block 'genblk5' (IEEE 1800-2023 27.6) : ... Suggest assign a label with 'begin : gen_' 31 | 2: begin | ^~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_trace_rollover.cpp0000644000542200017500000000224515101701376023142 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include #include #include VM_PREFIX_INCLUDE unsigned long long main_time = 0; double sc_time_stamp() { return (double)main_time; } int main(int argc, char** argv) { Verilated::debug(0); Verilated::traceEverOn(true); Verilated::commandArgs(argc, argv); std::unique_ptr top{new VM_PREFIX{"top"}}; std::unique_ptr tfp{new VerilatedVcdC}; top->trace(tfp.get(), 99); tfp->rolloverSize(1000); // But will be increased to 8kb chunk size tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simrollover.vcd"); top->clk = 0; while (main_time < 1900) { // Creates 2 files top->clk = !top->clk; top->eval(); tfp->dump((unsigned int)(main_time)); ++main_time; } tfp->close(); top->final(); tfp.reset(); top.reset(); printf("*-* All Finished *-*\n"); return 0; } verilator-5.042/test_regress/t/t_savable_open_bad2.py0000755000542200017500000000105215101701376023312 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(v_flags2=["--savable --exe", test.pli_filename], make_main=False) test.execute(check_finished=False) test.passes() verilator-5.042/test_regress/t/t_class_method_struct.py0000755000542200017500000000073415101701376024043 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_embed1_child.v0000644000542200017500000000201115101701376022072 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t_embed1_child (/*AUTOARG*/ // Outputs bit_out, vec_out, wide_out, did_init_out, // Inputs clk, bit_in, vec_in, wide_in, is_ref ); input clk; input bit_in; output bit_out; input [30:0] vec_in; output logic [30:0] vec_out; input [123:0] wide_in; output logic [123:0] wide_out; output did_init_out; input is_ref; reg did_init; initial did_init = 0; initial begin did_init = 1; end reg did_final; initial did_final = 0; final begin did_final = 1; if (!is_ref) $write("*-* All Finished *-*\n"); //$finish is in parent end // Note async use! wire bit_out = bit_in; wire did_init_out = did_init; always @ (posedge clk) begin vec_out <= vec_in; wide_out <= wide_in; end endmodule verilator-5.042/test_regress/t/t_struct_circ_bad.py0000755000542200017500000000076615101701376023131 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_clocking_unsup2.out0000644000542200017500000000047115101701376023251 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_clocking_unsup2.v:16:11: Unsupported: ##0 delays : ... note: In instance 't' 16 | always ##0; | ^~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_math_pow.out0000644000542200017500000003703015101701376021763 0ustar mahmoudyfreeshellgold: u 7ffffffffffffffff**7ffffffffffffffff: uiii = ffff gold: u 7ffffffffffffffff**7ffffffffffffffff: uiiq = ffff gold: u 7ffffffffffffffff**7ffffffffffffffff: uiiw = ffff gold: u 7ffffffffffffffff**7ffffffffffffffff: uiqi = ffff gold: u 7ffffffffffffffff**7ffffffffffffffff: uiqq = ffff gold: u 7ffffffffffffffff**7ffffffffffffffff: uiqw = ffff gold: u 7ffffffffffffffff**7ffffffffffffffff: uiwi = ffff gold: u 7ffffffffffffffff**7ffffffffffffffff: uiwq = ffff gold: u 7ffffffffffffffff**7ffffffffffffffff: uiww = ffff gold: u 7ffffffffffffffff**7ffffffffffffffff: uqii = 7fffeffff gold: u 7ffffffffffffffff**7ffffffffffffffff: uqiq = 6fffeffff gold: u 7ffffffffffffffff**7ffffffffffffffff: uqiw = 6fffeffff gold: u 7ffffffffffffffff**7ffffffffffffffff: uqqi = 7ffffffff gold: u 7ffffffffffffffff**7ffffffffffffffff: uqqq = 7ffffffff gold: u 7ffffffffffffffff**7ffffffffffffffff: uqqw = 7ffffffff gold: u 7ffffffffffffffff**7ffffffffffffffff: uqwi = 7ffffffff gold: u 7ffffffffffffffff**7ffffffffffffffff: uqwq = 7ffffffff gold: u 7ffffffffffffffff**7ffffffffffffffff: uqww = 7ffffffff gold: u 7ffffffffffffffff**7ffffffffffffffff: uwii = 300007ffffffeffff gold: u 7ffffffffffffffff**7ffffffffffffffff: uwiq = 30006fffefffeffff gold: u 7ffffffffffffffff**7ffffffffffffffff: uwiw = 6fffefffefffeffff gold: u 7ffffffffffffffff**7ffffffffffffffff: uwqi = 7fff7ffffffff gold: u 7ffffffffffffffff**7ffffffffffffffff: uwqq = 7fffffff7ffffffff gold: u 7ffffffffffffffff**7ffffffffffffffff: uwqw = 7fffffff7ffffffff gold: u 7ffffffffffffffff**7ffffffffffffffff: uwwi = 7ffffffffffffffff gold: u 7ffffffffffffffff**7ffffffffffffffff: uwwq = 7ffffffffffffffff gold: u 7ffffffffffffffff**7ffffffffffffffff: uwww = 7ffffffffffffffff gold: s -1**-1: siii = -1 gold: s -1**-1: siiq = -1 gold: s -1**-1: siiw = -1 gold: s -1**-1: siqi = -1 gold: s -1**-1: siqq = -1 gold: s -1**-1: siqw = -1 gold: s -1**-1: siwi = -1 gold: s -1**-1: siwq = -1 gold: s -1**-1: siww = -1 gold: s -1**-1: sqii = -1 gold: s -1**-1: sqiq = -1 gold: s -1**-1: sqiw = -1 gold: s -1**-1: sqqi = -1 gold: s -1**-1: sqqq = -1 gold: s -1**-1: sqqw = -1 gold: s -1**-1: sqwi = -1 gold: s -1**-1: sqwq = -1 gold: s -1**-1: sqww = -1 gold: s -1**-1: swii = -1 gold: s -1**-1: swiq = -1 gold: s -1**-1: swiw = -1 gold: s -1**-1: swqi = -1 gold: s -1**-1: swqq = -1 gold: s -1**-1: swqw = -1 gold: s -1**-1: swwi = -1 gold: s -1**-1: swwq = -1 gold: s -1**-1: swww = -1 gold: u 7ffffffffffffffff**2: uiii = 1 gold: u 7ffffffffffffffff**2: uiiq = 1 gold: u 7ffffffffffffffff**2: uiiw = 1 gold: u 7ffffffffffffffff**2: uiqi = 1 gold: u 7ffffffffffffffff**2: uiqq = 1 gold: u 7ffffffffffffffff**2: uiqw = 1 gold: u 7ffffffffffffffff**2: uiwi = 1 gold: u 7ffffffffffffffff**2: uiwq = 1 gold: u 7ffffffffffffffff**2: uiww = 1 gold: u 7ffffffffffffffff**2: uqii = fffe0001 gold: u 7ffffffffffffffff**2: uqiq = fffe0001 gold: u 7ffffffffffffffff**2: uqiw = fffe0001 gold: u 7ffffffffffffffff**2: uqqi = 1 gold: u 7ffffffffffffffff**2: uqqq = 1 gold: u 7ffffffffffffffff**2: uqqw = 1 gold: u 7ffffffffffffffff**2: uqwi = 1 gold: u 7ffffffffffffffff**2: uqwq = 1 gold: u 7ffffffffffffffff**2: uqww = 1 gold: u 7ffffffffffffffff**2: uwii = fffe0001 gold: u 7ffffffffffffffff**2: uwiq = fffe0001 gold: u 7ffffffffffffffff**2: uwiw = fffe0001 gold: u 7ffffffffffffffff**2: uwqi = 7fffffff000000001 gold: u 7ffffffffffffffff**2: uwqq = 7fffffff000000001 gold: u 7ffffffffffffffff**2: uwqw = 7fffffff000000001 gold: u 7ffffffffffffffff**2: uwwi = 1 gold: u 7ffffffffffffffff**2: uwwq = 1 gold: u 7ffffffffffffffff**2: uwww = 1 gold: s -1**2: siii = 1 gold: s -1**2: siiq = 1 gold: s -1**2: siiw = 1 gold: s -1**2: siqi = 1 gold: s -1**2: siqq = 1 gold: s -1**2: siqw = 1 gold: s -1**2: siwi = 1 gold: s -1**2: siwq = 1 gold: s -1**2: siww = 1 gold: s -1**2: sqii = 1 gold: s -1**2: sqiq = 1 gold: s -1**2: sqiw = 1 gold: s -1**2: sqqi = 1 gold: s -1**2: sqqq = 1 gold: s -1**2: sqqw = 1 gold: s -1**2: sqwi = 1 gold: s -1**2: sqwq = 1 gold: s -1**2: sqww = 1 gold: s -1**2: swii = 1 gold: s -1**2: swiq = 1 gold: s -1**2: swiw = 1 gold: s -1**2: swqi = 1 gold: s -1**2: swqq = 1 gold: s -1**2: swqw = 1 gold: s -1**2: swwi = 1 gold: s -1**2: swwq = 1 gold: s -1**2: swww = 1 gold: u 7ffffffffffffffff**3: uiii = ffff gold: u 7ffffffffffffffff**3: uiiq = ffff gold: u 7ffffffffffffffff**3: uiiw = ffff gold: u 7ffffffffffffffff**3: uiqi = ffff gold: u 7ffffffffffffffff**3: uiqq = ffff gold: u 7ffffffffffffffff**3: uiqw = ffff gold: u 7ffffffffffffffff**3: uiwi = ffff gold: u 7ffffffffffffffff**3: uiwq = ffff gold: u 7ffffffffffffffff**3: uiww = ffff gold: u 7ffffffffffffffff**3: uqii = 50002ffff gold: u 7ffffffffffffffff**3: uqiq = 50002ffff gold: u 7ffffffffffffffff**3: uqiw = 50002ffff gold: u 7ffffffffffffffff**3: uqqi = 7ffffffff gold: u 7ffffffffffffffff**3: uqqq = 7ffffffff gold: u 7ffffffffffffffff**3: uqqw = 7ffffffff gold: u 7ffffffffffffffff**3: uqwi = 7ffffffff gold: u 7ffffffffffffffff**3: uqwq = 7ffffffff gold: u 7ffffffffffffffff**3: uqww = 7ffffffff gold: u 7ffffffffffffffff**3: uwii = fffd0002ffff gold: u 7ffffffffffffffff**3: uwiq = fffd0002ffff gold: u 7ffffffffffffffff**3: uwiw = fffd0002ffff gold: u 7ffffffffffffffff**3: uwqi = 17ffffffff gold: u 7ffffffffffffffff**3: uwqq = 17ffffffff gold: u 7ffffffffffffffff**3: uwqw = 17ffffffff gold: u 7ffffffffffffffff**3: uwwi = 7ffffffffffffffff gold: u 7ffffffffffffffff**3: uwwq = 7ffffffffffffffff gold: u 7ffffffffffffffff**3: uwww = 7ffffffffffffffff gold: s -1**3: siii = -1 gold: s -1**3: siiq = -1 gold: s -1**3: siiw = -1 gold: s -1**3: siqi = -1 gold: s -1**3: siqq = -1 gold: s -1**3: siqw = -1 gold: s -1**3: siwi = -1 gold: s -1**3: siwq = -1 gold: s -1**3: siww = -1 gold: s -1**3: sqii = -1 gold: s -1**3: sqiq = -1 gold: s -1**3: sqiw = -1 gold: s -1**3: sqqi = -1 gold: s -1**3: sqqq = -1 gold: s -1**3: sqqw = -1 gold: s -1**3: sqwi = -1 gold: s -1**3: sqwq = -1 gold: s -1**3: sqww = -1 gold: s -1**3: swii = -1 gold: s -1**3: swiq = -1 gold: s -1**3: swiw = -1 gold: s -1**3: swqi = -1 gold: s -1**3: swqq = -1 gold: s -1**3: swqw = -1 gold: s -1**3: swwi = -1 gold: s -1**3: swwq = -1 gold: s -1**3: swww = -1 gold: u 3**7ffffffffffffffff: uiii = aaab gold: u 3**7ffffffffffffffff: uiiq = aaab gold: u 3**7ffffffffffffffff: uiiw = aaab gold: u 3**7ffffffffffffffff: uiqi = aaab gold: u 3**7ffffffffffffffff: uiqq = aaab gold: u 3**7ffffffffffffffff: uiqw = aaab gold: u 3**7ffffffffffffffff: uiwi = aaab gold: u 3**7ffffffffffffffff: uiwq = aaab gold: u 3**7ffffffffffffffff: uiww = aaab gold: u 3**7ffffffffffffffff: uqii = 64da6aaab gold: u 3**7ffffffffffffffff: uqiq = 2aaaaaaab gold: u 3**7ffffffffffffffff: uqiw = 2aaaaaaab gold: u 3**7ffffffffffffffff: uqqi = 64da6aaab gold: u 3**7ffffffffffffffff: uqqq = 2aaaaaaab gold: u 3**7ffffffffffffffff: uqqw = 2aaaaaaab gold: u 3**7ffffffffffffffff: uqwi = 64da6aaab gold: u 3**7ffffffffffffffff: uqwq = 2aaaaaaab gold: u 3**7ffffffffffffffff: uqww = 2aaaaaaab gold: u 3**7ffffffffffffffff: uwii = 78fa2e79e4da6aaab gold: u 3**7ffffffffffffffff: uwiq = 5b187c28aaaaaaaab gold: u 3**7ffffffffffffffff: uwiw = 2aaaaaaaaaaaaaaab gold: u 3**7ffffffffffffffff: uwqi = 78fa2e79e4da6aaab gold: u 3**7ffffffffffffffff: uwqq = 5b187c28aaaaaaaab gold: u 3**7ffffffffffffffff: uwqw = 2aaaaaaaaaaaaaaab gold: u 3**7ffffffffffffffff: uwwi = 78fa2e79e4da6aaab gold: u 3**7ffffffffffffffff: uwwq = 5b187c28aaaaaaaab gold: u 3**7ffffffffffffffff: uwww = 2aaaaaaaaaaaaaaab gold: s 3**-1: siii = 0 gold: s 3**-1: siiq = 0 gold: s 3**-1: siiw = 0 gold: s 3**-1: siqi = 0 gold: s 3**-1: siqq = 0 gold: s 3**-1: siqw = 0 gold: s 3**-1: siwi = 0 gold: s 3**-1: siwq = 0 gold: s 3**-1: siww = 0 gold: s 3**-1: sqii = 0 gold: s 3**-1: sqiq = 0 gold: s 3**-1: sqiw = 0 gold: s 3**-1: sqqi = 0 gold: s 3**-1: sqqq = 0 gold: s 3**-1: sqqw = 0 gold: s 3**-1: sqwi = 0 gold: s 3**-1: sqwq = 0 gold: s 3**-1: sqww = 0 gold: s 3**-1: swii = 0 gold: s 3**-1: swiq = 0 gold: s 3**-1: swiw = 0 gold: s 3**-1: swqi = 0 gold: s 3**-1: swqq = 0 gold: s 3**-1: swqw = 0 gold: s 3**-1: swwi = 0 gold: s 3**-1: swwq = 0 gold: s 3**-1: swww = 0 gold: u 7fffffffffffffffe**1: uiii = fffe gold: u 7fffffffffffffffe**1: uiiq = fffe gold: u 7fffffffffffffffe**1: uiiw = fffe gold: u 7fffffffffffffffe**1: uiqi = fffe gold: u 7fffffffffffffffe**1: uiqq = fffe gold: u 7fffffffffffffffe**1: uiqw = fffe gold: u 7fffffffffffffffe**1: uiwi = fffe gold: u 7fffffffffffffffe**1: uiwq = fffe gold: u 7fffffffffffffffe**1: uiww = fffe gold: u 7fffffffffffffffe**1: uqii = fffe gold: u 7fffffffffffffffe**1: uqiq = fffe gold: u 7fffffffffffffffe**1: uqiw = fffe gold: u 7fffffffffffffffe**1: uqqi = 7fffffffe gold: u 7fffffffffffffffe**1: uqqq = 7fffffffe gold: u 7fffffffffffffffe**1: uqqw = 7fffffffe gold: u 7fffffffffffffffe**1: uqwi = 7fffffffe gold: u 7fffffffffffffffe**1: uqwq = 7fffffffe gold: u 7fffffffffffffffe**1: uqww = 7fffffffe gold: u 7fffffffffffffffe**1: uwii = fffe gold: u 7fffffffffffffffe**1: uwiq = fffe gold: u 7fffffffffffffffe**1: uwiw = fffe gold: u 7fffffffffffffffe**1: uwqi = 7fffffffe gold: u 7fffffffffffffffe**1: uwqq = 7fffffffe gold: u 7fffffffffffffffe**1: uwqw = 7fffffffe gold: u 7fffffffffffffffe**1: uwwi = 7fffffffffffffffe gold: u 7fffffffffffffffe**1: uwwq = 7fffffffffffffffe gold: u 7fffffffffffffffe**1: uwww = 7fffffffffffffffe gold: s -2**1: siii = -2 gold: s -2**1: siiq = -2 gold: s -2**1: siiw = -2 gold: s -2**1: siqi = -2 gold: s -2**1: siqq = -2 gold: s -2**1: siqw = -2 gold: s -2**1: siwi = -2 gold: s -2**1: siwq = -2 gold: s -2**1: siww = -2 gold: s -2**1: sqii = -2 gold: s -2**1: sqiq = -2 gold: s -2**1: sqiw = -2 gold: s -2**1: sqqi = -2 gold: s -2**1: sqqq = -2 gold: s -2**1: sqqw = -2 gold: s -2**1: sqwi = -2 gold: s -2**1: sqwq = -2 gold: s -2**1: sqww = -2 gold: s -2**1: swii = -2 gold: s -2**1: swiq = -2 gold: s -2**1: swiw = -2 gold: s -2**1: swqi = -2 gold: s -2**1: swqq = -2 gold: s -2**1: swqw = -2 gold: s -2**1: swwi = -2 gold: s -2**1: swwq = -2 gold: s -2**1: swww = -2 gold: u 7fffffffffffffffe**7ffffffffffffffff: uiii = 0 gold: u 7fffffffffffffffe**7ffffffffffffffff: uiiq = 0 gold: u 7fffffffffffffffe**7ffffffffffffffff: uiiw = 0 gold: u 7fffffffffffffffe**7ffffffffffffffff: uiqi = 0 gold: u 7fffffffffffffffe**7ffffffffffffffff: uiqq = 0 gold: u 7fffffffffffffffe**7ffffffffffffffff: uiqw = 0 gold: u 7fffffffffffffffe**7ffffffffffffffff: uiwi = 0 gold: u 7fffffffffffffffe**7ffffffffffffffff: uiwq = 0 gold: u 7fffffffffffffffe**7ffffffffffffffff: uiww = 0 gold: u 7fffffffffffffffe**7ffffffffffffffff: uqii = 0 gold: u 7fffffffffffffffe**7ffffffffffffffff: uqiq = 0 gold: u 7fffffffffffffffe**7ffffffffffffffff: uqiw = 0 gold: u 7fffffffffffffffe**7ffffffffffffffff: uqqi = 0 gold: u 7fffffffffffffffe**7ffffffffffffffff: uqqq = 0 gold: u 7fffffffffffffffe**7ffffffffffffffff: uqqw = 0 gold: u 7fffffffffffffffe**7ffffffffffffffff: uqwi = 0 gold: u 7fffffffffffffffe**7ffffffffffffffff: uqwq = 0 gold: u 7fffffffffffffffe**7ffffffffffffffff: uqww = 0 gold: u 7fffffffffffffffe**7ffffffffffffffff: uwii = 0 gold: u 7fffffffffffffffe**7ffffffffffffffff: uwiq = 0 gold: u 7fffffffffffffffe**7ffffffffffffffff: uwiw = 0 gold: u 7fffffffffffffffe**7ffffffffffffffff: uwqi = 0 gold: u 7fffffffffffffffe**7ffffffffffffffff: uwqq = 0 gold: u 7fffffffffffffffe**7ffffffffffffffff: uwqw = 0 gold: u 7fffffffffffffffe**7ffffffffffffffff: uwwi = 0 gold: u 7fffffffffffffffe**7ffffffffffffffff: uwwq = 0 gold: u 7fffffffffffffffe**7ffffffffffffffff: uwww = 0 gold: s -2**-1: siii = 0 gold: s -2**-1: siiq = 0 gold: s -2**-1: siiw = 0 gold: s -2**-1: siqi = 0 gold: s -2**-1: siqq = 0 gold: s -2**-1: siqw = 0 gold: s -2**-1: siwi = 0 gold: s -2**-1: siwq = 0 gold: s -2**-1: siww = 0 gold: s -2**-1: sqii = 0 gold: s -2**-1: sqiq = 0 gold: s -2**-1: sqiw = 0 gold: s -2**-1: sqqi = 0 gold: s -2**-1: sqqq = 0 gold: s -2**-1: sqqw = 0 gold: s -2**-1: sqwi = 0 gold: s -2**-1: sqwq = 0 gold: s -2**-1: sqww = 0 gold: s -2**-1: swii = 0 gold: s -2**-1: swiq = 0 gold: s -2**-1: swiw = 0 gold: s -2**-1: swqi = 0 gold: s -2**-1: swqq = 0 gold: s -2**-1: swqw = 0 gold: s -2**-1: swwi = 0 gold: s -2**-1: swwq = 0 gold: s -2**-1: swww = 0 gold: u 7fffffffffffffffe**2: uiii = 4 gold: u 7fffffffffffffffe**2: uiiq = 4 gold: u 7fffffffffffffffe**2: uiiw = 4 gold: u 7fffffffffffffffe**2: uiqi = 4 gold: u 7fffffffffffffffe**2: uiqq = 4 gold: u 7fffffffffffffffe**2: uiqw = 4 gold: u 7fffffffffffffffe**2: uiwi = 4 gold: u 7fffffffffffffffe**2: uiwq = 4 gold: u 7fffffffffffffffe**2: uiww = 4 gold: u 7fffffffffffffffe**2: uqii = fffc0004 gold: u 7fffffffffffffffe**2: uqiq = fffc0004 gold: u 7fffffffffffffffe**2: uqiw = fffc0004 gold: u 7fffffffffffffffe**2: uqqi = 4 gold: u 7fffffffffffffffe**2: uqqq = 4 gold: u 7fffffffffffffffe**2: uqqw = 4 gold: u 7fffffffffffffffe**2: uqwi = 4 gold: u 7fffffffffffffffe**2: uqwq = 4 gold: u 7fffffffffffffffe**2: uqww = 4 gold: u 7fffffffffffffffe**2: uwii = fffc0004 gold: u 7fffffffffffffffe**2: uwiq = fffc0004 gold: u 7fffffffffffffffe**2: uwiw = fffc0004 gold: u 7fffffffffffffffe**2: uwqi = 7ffffffe000000004 gold: u 7fffffffffffffffe**2: uwqq = 7ffffffe000000004 gold: u 7fffffffffffffffe**2: uwqw = 7ffffffe000000004 gold: u 7fffffffffffffffe**2: uwwi = 4 gold: u 7fffffffffffffffe**2: uwwq = 4 gold: u 7fffffffffffffffe**2: uwww = 4 gold: s -2**2: siii = 4 gold: s -2**2: siiq = 4 gold: s -2**2: siiw = 4 gold: s -2**2: siqi = 4 gold: s -2**2: siqq = 4 gold: s -2**2: siqw = 4 gold: s -2**2: siwi = 4 gold: s -2**2: siwq = 4 gold: s -2**2: siww = 4 gold: s -2**2: sqii = 4 gold: s -2**2: sqiq = 4 gold: s -2**2: sqiw = 4 gold: s -2**2: sqqi = 4 gold: s -2**2: sqqq = 4 gold: s -2**2: sqqw = 4 gold: s -2**2: sqwi = 4 gold: s -2**2: sqwq = 4 gold: s -2**2: sqww = 4 gold: s -2**2: swii = 4 gold: s -2**2: swiq = 4 gold: s -2**2: swiw = 4 gold: s -2**2: swqi = 4 gold: s -2**2: swqq = 4 gold: s -2**2: swqw = 4 gold: s -2**2: swwi = 4 gold: s -2**2: swwq = 4 gold: s -2**2: swww = 4 gold: u 7fffffffffffffffe**3: uiii = fff8 gold: u 7fffffffffffffffe**3: uiiq = fff8 gold: u 7fffffffffffffffe**3: uiiw = fff8 gold: u 7fffffffffffffffe**3: uiqi = fff8 gold: u 7fffffffffffffffe**3: uiqq = fff8 gold: u 7fffffffffffffffe**3: uiqw = fff8 gold: u 7fffffffffffffffe**3: uiwi = fff8 gold: u 7fffffffffffffffe**3: uiwq = fff8 gold: u 7fffffffffffffffe**3: uiww = fff8 gold: u 7fffffffffffffffe**3: uqii = 2000bfff8 gold: u 7fffffffffffffffe**3: uqiq = 2000bfff8 gold: u 7fffffffffffffffe**3: uqiw = 2000bfff8 gold: u 7fffffffffffffffe**3: uqqi = 7fffffff8 gold: u 7fffffffffffffffe**3: uqqq = 7fffffff8 gold: u 7fffffffffffffffe**3: uqqw = 7fffffff8 gold: u 7fffffffffffffffe**3: uqwi = 7fffffff8 gold: u 7fffffffffffffffe**3: uqwq = 7fffffff8 gold: u 7fffffffffffffffe**3: uqww = 7fffffff8 gold: u 7fffffffffffffffe**3: uwii = fffa000bfff8 gold: u 7fffffffffffffffe**3: uwiq = fffa000bfff8 gold: u 7fffffffffffffffe**3: uwiw = fffa000bfff8 gold: u 7fffffffffffffffe**3: uwqi = 5ffffffff8 gold: u 7fffffffffffffffe**3: uwqq = 5ffffffff8 gold: u 7fffffffffffffffe**3: uwqw = 5ffffffff8 gold: u 7fffffffffffffffe**3: uwwi = 7fffffffffffffff8 gold: u 7fffffffffffffffe**3: uwwq = 7fffffffffffffff8 gold: u 7fffffffffffffffe**3: uwww = 7fffffffffffffff8 gold: s -2**3: siii = -8 gold: s -2**3: siiq = -8 gold: s -2**3: siiw = -8 gold: s -2**3: siqi = -8 gold: s -2**3: siqq = -8 gold: s -2**3: siqw = -8 gold: s -2**3: siwi = -8 gold: s -2**3: siwq = -8 gold: s -2**3: siww = -8 gold: s -2**3: sqii = -8 gold: s -2**3: sqiq = -8 gold: s -2**3: sqiw = -8 gold: s -2**3: sqqi = -8 gold: s -2**3: sqqq = -8 gold: s -2**3: sqqw = -8 gold: s -2**3: sqwi = -8 gold: s -2**3: sqwq = -8 gold: s -2**3: sqww = -8 gold: s -2**3: swii = -8 gold: s -2**3: swiq = -8 gold: s -2**3: swiw = -8 gold: s -2**3: swqi = -8 gold: s -2**3: swqq = -8 gold: s -2**3: swqw = -8 gold: s -2**3: swwi = -8 gold: s -2**3: swwq = -8 gold: s -2**3: swww = -8 *-* All Finished *-* verilator-5.042/test_regress/t/t_inside_extend.v0000644000542200017500000000071415101701376022424 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 typedef enum bit [4:0] {V0 = 1} my_enum; class Cls; my_enum sp = V0; endclass module t; initial begin Cls c = new; int i = 0; if (i inside {c.sp}) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_inst_signed.v0000644000542200017500000000335415101701376022113 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc = 0; wire signed [7:0] sgn_wide; wire [7:0] unsgn_wide; // The instantiation will Z extend, not sign extend // verilator lint_off WIDTH sub sub (.clk, .sgn(sgn_wide), .unsgn(unsgn_wide), .iss(3'sh7), .isu(3'h7), .ius(3'sh7), .iuu(3'h7)); // verilator lint_on WIDTH always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("out: 'b%b 'b%b\n", sgn_wide, unsgn_wide); `endif if (sgn_wide[2:0] != 3'sh7) $stop; if (unsgn_wide[2:0] != 3'h7) $stop; // Simulators differ here. if (sgn_wide !== 8'sbzzzzz111 // z-extension - NC && sgn_wide !== 8'sb11111111) $stop; // sign extension - VCS if (unsgn_wide !== 8'sbzzzzz111 && unsgn_wide!== 8'sb00000111) $stop; cyc <= cyc + 1; if (cyc==3) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module sub ( input clk, output wire signed [2:0] sgn, output wire [2:0] unsgn, input signed [7:0] iss, input signed [7:0] isu, input [7:0] ius, input [7:0] iuu); assign sgn = 3'sh7; assign unsgn = 3'h7; always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("in: %x %x %x %x\n", iss, isu, ius, iuu); if (iss != 8'hff) $stop; if (isu != 8'h07) $stop; if (ius != 8'hff) $stop; if (iuu != 8'h07) $stop; `endif end endmodule verilator-5.042/test_regress/t/t_uvm_dpi.v0000644000542200017500000001142715101701376021250 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilator lint_off WIDTH `include "dpi/uvm_dpi.svh" // verilator lint_on WIDTH // verilog_format: off `define stop $stop `define checkh(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); // verilog_format: on // Undocumented DPI available version of uvm_report // UVM declares without 'context' package uvm_pkg; export "DPI-C" function m__uvm_report_dpi; function void m__uvm_report_dpi(int severity, string id, string message, int verbosity, string filename, int line); $display("UVM Report %s:%0d: %s %s", filename, line, id, message); endfunction endpackage module t; int i; string s; chandle h; // To cover testing cases, this has non-zero LSB/LO logic [31+8:8] exposed /*verilator public*/; uvm_hdl_data_t lval; initial begin // TODO TEST: // extern const char* uvm_dpi_get_next_arg_c(int init); //===== Exports uvm_pkg::m__uvm_report_dpi(1, "id", "message", 1, `__FILE__, `__LINE__); //===== Tool s = uvm_dpi_get_tool_name_c(); $display("uvm_dpi_get_tool_name_c() = %s", s); `checks(s, "Verilator"); s = uvm_dpi_get_tool_version_c(); // - is so doesn't compare in .out file, in case version changes $display("- uvm_dpi_get_tool_version_c() = %s", s); if (s == "") $stop; //===== Regexp $display("= uvm_re"); h = uvm_dpi_regcomp("a.*b"); i = uvm_dpi_regexec(h, "__a_b__"); `checkh(i, 0); i = uvm_dpi_regexec(h, "__a_z__"); `checkh(i, 1); uvm_dpi_regfree(h); i = uvm_re_match("a.*b", "__a__b__"); `checkh(i, 0); i = uvm_re_match("a.*b", "__a__z__"); `checkh(i, 1); s = uvm_glob_to_re("a foo bar"); `checks(s, "/^a foo bar$/"); //===== Hier `ifdef VERILATOR `ifdef TEST_VERBOSE $c("Verilated::scopesDump();"); `endif `endif $display("= uvm_hdl_check_path"); i = uvm_hdl_check_path("t.__NOT_FOUND"); `checkh(i, 0); i = uvm_hdl_check_path("t.exposed"); `checkh(i, 1); i = uvm_hdl_check_path("$root.t.exposed"); `checkh(i, 1); $display("= uvm_hdl_read simple variable"); exposed = 32'hb001; lval = '0; // Upper bits not cleared by uvm_hdl_read i = uvm_hdl_read("t.exposed", lval); `checkh(i, 1); `checkh(lval[31:0], exposed); lval = '0; $display("= uvm_hdl_read not found (bad)"); $display("===\nUVM Report expected on next line:"); i = uvm_hdl_deposit("t.__DEPOSIT_NOT_FOUND", lval); `checkh(i, 0); $display("= uvm_hdl_deposit simple variable"); lval = 1024'hab; i = uvm_hdl_deposit("t.exposed", lval); `checkh(i, 1); `checkh(exposed, 32'hab); $display("= uvm_hdl_read single bit"); exposed = 32'habcd; lval = '0; // Upper bits not cleared by uvm_hdl_read i = uvm_hdl_read("t.exposed[11]", lval); `checkh(i, 1); `checkh(lval[0], exposed[11]); $display("= uvm_hdl_deposit single bit"); lval = 1024'h0; i = uvm_hdl_deposit("t.exposed[11]", lval); `checkh(i, 1); `checkh(exposed, 32'habc5); $display("= uvm_hdl_read multi-bit"); exposed = 32'habcd; lval = '0; // Upper bits not cleared by uvm_hdl_read i = uvm_hdl_read("t.exposed[19:12]", lval); `checkh(i, 1); `checkh(lval[7:0], exposed[19:12]); $display("= uvm_hdl_deposit multi-bit"); lval = 1024'h12; i = uvm_hdl_deposit("t.exposed[19:12]", lval); `checkh(i, 1); `checkh(exposed, 32'ha12d); $display("= uvm_hdl_deposit bad ranges"); $display("===\nUVM Report expected on next line:"); i = uvm_hdl_deposit("t.exposed[10:3]", lval); `checkh(i, 0); $display("===\nUVM Report expected on next line:"); i = uvm_hdl_deposit("t.exposed[99:15]", lval); `checkh(i, 0); `ifdef VERILATOR // UNSUPPORTED: force/release via VPI // If support, validate or throw unsupported on force/release part-selects $display("= uvm_hdl_force"); $display("===\nUVM Report expected on next line:"); i = uvm_hdl_force("t.exposed", 62); `checkh(i, 0); $display("= uvm_hdl_release"); $display("===\nUVM Report expected on next line:"); i = uvm_hdl_release("t.exposed"); `checkh(i, 0); $display("= uvm_hdl_release_and_read"); $display("===\nUVM Report expected on next line:"); i = uvm_hdl_release_and_read("t.exposed", lval); `checkh(i, 0); `endif $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_sys_writemem_b.gold2.mem0000644000542200017500000000007015101701376024144 0ustar mahmoudyfreeshell010000 010001 010010 010011 010100 010101 010110 010111 verilator-5.042/test_regress/t/t_fuzz_triand_bad.out0000644000542200017500000000130415101701376023305 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_fuzz_triand_bad.v:8:12: Unsupported: Member call on object 'VARREF 'g'' which is a 'BASICDTYPE 'logic'' : ... note: In instance 't' 8 | tri g=g.and.g; | ^~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: t/t_fuzz_triand_bad.v:8:16: Member selection of non-struct/union object 'METHODCALL 'and'' which is a 'VOIDDTYPE' : ... note: In instance 't' 8 | tri g=g.and.g; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_class_extends_alias_unsup.out0000644000542200017500000000045315101701376025406 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_class_extends_alias_unsup.v:22:22: Unsupported: TYPEDEF 'foo_t' in AstClassExtends 22 | class bar extends foo_t; | ^~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_interface2_noinl.py0000755000542200017500000000106215101701376023206 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface2.v" test.compile(verilator_flags2=["--top-module t -fno-inline"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_vpi_escape.v0000644000542200017500000001031015101701376021711 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2010-2023 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef USE_VPI_NOT_DPI //We call it via $c so we can verify DPI isn't required - see bug572 `else import "DPI-C" context function int mon_check(); `endif module \t.has.dots (/*AUTOARG*/ // Outputs \escaped_normal , double__underscore, double__underscore__vlt, \9num , \bra[ket]slash/dash-colon:9backslash\done , \x.y , // Inputs clk, a, \b.c ); `ifdef VERILATOR `systemc_header extern "C" int mon_check(); `verilog `endif input clk; input [7:0] a /*verilator public_flat_rw*/; input \b.c /*verilator public_flat_rw*/; int cyc /*verilator public_flat_rd*/; output \escaped_normal /*verilator public_flat_rd*/; wire \escaped_normal = cyc[0]; output double__underscore /*verilator public_flat_rd*/; wire double__underscore = cyc[0]; output double__underscore__vlt; // public in .vlt wire double__underscore__vlt = cyc[0]; // C doesn't allow leading non-alpha, so must escape output \9num ; wire \9num = cyc[0]; output \bra[ket]slash/dash-colon:9backslash\done ; wire \bra[ket]slash/dash-colon:9backslash\done = cyc[0]; output \x.y /*verilator public_flat_rd*/; wire \x.y = cyc[0]; wire \wire = cyc[0]; wire \check_alias /*verilator public_flat_rd*/ = cyc[0]; wire \check:alias /*verilator public_flat_rd*/ = cyc[0]; wire \check;alias /*verilator public_flat_rd*/ = !cyc[0]; // These are *different entities*, bug83 wire [31:0] \a0.cyc = ~a0.cyc; wire [31:0] \other.cyc = ~a0.cyc; integer status; sub_with_very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very_long_name a0 (.cyc(cyc)); sub_with_very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very_long_name \mod.with_dot (.cyc(cyc)); // Check if scope names are not decoded twice sub_with_very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very_long_name ___0F_ (.cyc(cyc)); sub_with_very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very_long_name ___0_ (.cyc(cyc)); initial begin `ifdef VERILATOR status = $c32("mon_check()"); `endif `ifdef IVERILOG status = $mon_check(); `endif `ifndef USE_VPI_NOT_DPI status = mon_check(); `endif if (status != 0) begin $write("%%Error: C Test failed with %0d error(s)\n", status); $stop; end $write("%%Info: Checking results\n"); end always @ (posedge clk) begin cyc <= cyc + 1; if (escaped_normal != cyc[0]) $stop; if (\escaped_normal != cyc[0]) $stop; if (double__underscore != cyc[0]) $stop; if (\9num != cyc[0]) $stop; if (\bra[ket]slash/dash-colon:9backslash\done != cyc[0]) $stop; if (\x.y != cyc[0]) $stop; if (\wire != cyc[0]) $stop; if (\check_alias != cyc[0]) $stop; if (\check:alias != cyc[0]) $stop; if (\check;alias != !cyc[0]) $stop; if (\a0.cyc != ~cyc) $stop; if (\other.cyc != ~cyc) $stop; if (cyc==10) begin if (a != 2) $stop; if (\b.c != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module sub_with_very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very__very_long_name ( input [31:0] cyc /*verilator public_flat_rd*/ ); reg \b.c /*verilator public_flat_rw*/; reg subsig1 /*verilator public_flat_rd*/; reg subsig2; // public in .vlt `ifdef IVERILOG // stop icarus optimizing signals away wire redundant = subsig1 | subsig2 | \b.c ; `endif endmodule verilator-5.042/test_regress/t/t_union_soft.v0000644000542200017500000000144715101701376021771 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; union soft { bit [7:0] val1; bit [3:0] val2; } u; union soft packed { bit [7 : 0] val1; bit [3 : 0] val2; } u2; initial begin u.val1 = 8'h7c; if (u.val1 != 8'h7c) $stop; u.val2 = 4'h6; if (u.val2 != 4'h6) $stop; $display("%p", u); if(u.val1 != 8'h76) $stop; u2.val1 = 8'h7c; if(u2.val1 != 8'h7c) $stop; u2.val2 = 4'h6; if(u2.val2 != 4'h6) $stop; $display("%p", u2); if(u2.val1 != 8'h76) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_class_member_bad.v0000644000542200017500000000061015101701376023037 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Base1; int memb1; endclass class Cls2 extends Base1; int memb2; endclass module t; initial begin Cls2 c; c.memb3 = 3; // Not found end endmodule verilator-5.042/test_regress/t/t_time_sc_us.py0000755000542200017500000000121315101701376022115 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_time_sc.v" test.sc_time_resolution = 'SC_US' test.compile(verilator_flags2=['-sc', '-timescale 1us/1us', '+define+TEST_EXPECT=20us']) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_trace_wide_struct.v0000644000542200017500000000065015101701376023313 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; typedef struct { logic [64:0] long_signal; } mystruct_t; mystruct_t mystruct; initial begin $finish; end endmodule verilator-5.042/test_regress/t/t_interface_ref_trace_inlab.py0000755000542200017500000000136315101701376025110 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_ref_trace.v" test.golden_filename = "t/t_interface_ref_trace.out" test.compile(v_flags2=['+define+NO_INLINE_A +define+NO_INLINE_B'], verilator_flags2=['--trace-structs --trace-vcd']) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_trace_dumporder_bad.out0000644000542200017500000000011515101701376024124 0ustar mahmoudyfreeshell%Warning: $dumpvar ignored as not preceded by $dumpfile *-* All Finished *-* verilator-5.042/test_regress/t/t_parse_eof_str_bad.v0000644000542200017500000000036315101701376023243 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 localparam string STR = "str verilator-5.042/test_regress/t/t_flag_main_sc_bad.out0000644000542200017500000000032115101701376023346 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: --main not usable with SystemC. Suggest see examples for sc_main(). ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_display_noopt.py0000755000542200017500000000114515101701376022653 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_display.v" test.golden_filename = "t/t_display.out" test.compile(verilator_flags2=["-O0"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface_virtual_unsup.out0000644000542200017500000000132715101701376025105 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_interface_virtual_unsup.v:22:22: Unsupported: Write to virtual interface in if condition 22 | if (write_data(vif.data)) $write("dummy op"); | ^~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_interface_virtual_unsup.v:23:25: Unsupported: Write to virtual interface in loop condition 23 | while (write_data(vif.data)); | ^~~ %Error-UNSUPPORTED: t/t_interface_virtual_unsup.v:24:30: Unsupported: Write to virtual interface in loop condition 24 | do ; while (write_data(vif.data)); | ^~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_protect_ids_bad.v0000644000542200017500000000035215101701376022725 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; endmodule verilator-5.042/test_regress/t/t_altera_lpm_or.py0000755000542200017500000000111115101701376022600 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) test.compile(verilator_flags2=["--top-module", module]) test.passes() verilator-5.042/test_regress/t/t_vlt_match_error.vlt0000644000542200017500000000043515101701376023334 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Ethan Sifferman. // SPDX-License-Identifier: CC0-1.0 `verilator_config lint_off -file "*/t_vlt_match_error.v" -match "*" verilator-5.042/test_regress/t/t_clocking_sched_timing_forkproc.out0000755000542200017500000000112415101701376026356 0ustar mahmoudyfreeshell0 | posedge 0 | cb.y=0 0 | b=0 0 | z<=0 0 | x<=0 0 | y=0 0 | c<=0 0 | c<=1 0 | cb.a=1 0 | cb.b=1 0 | posedge 0 | x<=1 0 | y=1 0 | c<=0 0 | cb.a=0 0 | cb.b=1 0 | cb.y=1 0 | b=1 0 | x<=0 0 | y=0 0 | 0 1 0 0 0 0 2 | z<=1 3 | posedge 3 | c<=1 3 | cb.a=1 3 | cb.b=1 3 | cb.y=0 3 | b=0 3 | posedge 3 | x<=1 3 | y=1 3 | c<=0 3 | cb.a=0 3 | cb.b=1 3 | cb.y=1 3 | b=1 3 | x<=0 3 | y=0 3 | 0 1 0 0 0 1 5 | posedge 5 | z<=0 5 | c<=1 5 | cb.a=1 5 | cb.b=1 5 | cb.y=0 5 | b=0 5 | posedge 5 | x<=1 5 | y=1 5 | c<=0 5 | cb.a=0 5 | cb.b=1 5 | cb.y=1 5 | b=1 5 | x<=0 5 | y=0 5 | 0 1 0 0 0 0 *-* All Finished *-* verilator-5.042/test_regress/t/t_flag_language_default.py0000755000542200017500000000106115101701376024244 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = 't/t_flag_language.v' test.compile(verilator_flags2=['--default-language 1364-2001']) test.execute() test.passes() verilator-5.042/test_regress/t/t_class_format.out0000644000542200017500000000040115101701376022612 0ustar mahmoudyfreeshell''{b:'h1, i:'h2a, carray4:'{'h11, 'h22, 'h33, 'h44}, cwide:'{'h0, 'h0}, name:"object_name", r:2.2}' ''{b:'h1, i:'h2a, carray4:'{'h911, 'h922, 'h933, 'h944}, cwide:'{'h0, 'h0}, name:"object_name", r:2.2}' DEBUG: object_name (@0) message *-* All Finished *-* verilator-5.042/test_regress/t/t_interface_ref_trace.py0000755000542200017500000000111315101701376023734 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--trace-structs --trace-vcd']) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_program_extern.py0000755000542200017500000000105515101701376023023 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) if not test.vlt_all: test.execute() test.passes() verilator-5.042/test_regress/t/t_queue_method.py0000755000542200017500000000073415101701376022456 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_func_arg_complex.v0000644000542200017500000000527315101701376023122 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); class Cls; enum { ONEK = 1000, TWOK = 2000 } sev_t; int m_default_data; function int trigger(int data=get_default_data()); return data; endfunction task triggert(output int o, input int data=get_default_data()); o = data; endtask virtual function int get_default_data(); return m_default_data; endfunction function int uvm_report(int severity, int verbosity = (severity == 1) ? ONEK : TWOK); return verbosity; endfunction endclass module t; function int mod_trigger(int data=mod_data()); return data; endfunction task mod_triggert(output int o, input int data=mod_data()); o = data; endtask int mod_default_data; function int mod_data(); return mod_default_data; endfunction int v; initial begin begin mod_triggert(v, 1234); `checkd(v, 1234); mod_default_data = 42; v = mod_trigger(); `checkd(v, 42); v = mod_trigger(11); `checkd(v, 11); mod_default_data = 43; v = mod_trigger(); `checkd(v, 43); v = mod_trigger(); // Multiple to test look up of duplicates `checkd(v, 43); mod_default_data = 52; mod_triggert(v); `checkd(v, 52); mod_triggert(v); // Multiple to test look up of duplicates `checkd(v, 52); end begin Cls c = new; c.m_default_data = 42; v = c.trigger(); `checkd(v, 42); v = c.trigger(11); `checkd(v, 11); c.m_default_data = 43; v = c.trigger(); `checkd(v, 43); v = c.trigger(); // Multiple to test look up of duplicates `checkd(v, 43); v = c.trigger(); // Multiple to test look up of duplicates `checkd(v, 43); c.m_default_data = 52; c.triggert(v); `checkd(v, 52); c.triggert(v); // Multiple to test look up of duplicates `checkd(v, 52); v = c.uvm_report(1); `checkd(v, 1000); v = c.uvm_report(2); `checkd(v, 2000); v = c.uvm_report(1, 111); `checkd(v, 111); v = c.uvm_report(1, 222); `checkd(v, 222); end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_dos.py0000755000542200017500000000105415101701376020553 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['-Wall -Wno-DECLFILENAME']) # To check EOFNEWLINE with DOS CRs test.execute() test.passes() verilator-5.042/test_regress/t/t_assert_elab_p.out0000644000542200017500000000040415101701376022743 0ustar mahmoudyfreeshell-Info: t/t_assert_elab_p.v:14:5: %m test.sv:25: 4=4 2=2 STAGE_IDS='{'h1, 'h1, 'h1, 'h1} : ... note: In instance 't.pipe' 14 | $info("%m %s:%0d: 4=%0d 2=%0d STAGE_IDS=%p", "test.sv", 25, 4, 2, STAGE_IDS); | ^~~~~ verilator-5.042/test_regress/t/t_inst_dtree_inlac.py0000755000542200017500000000111615101701376023273 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_inst_dtree.v" test.compile(v_flags2=['+define+INLINE_A +define+INLINE_C'], verilator_flags2=['-trace']) test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_in_inc_bad.py0000755000542200017500000000107315101701376023062 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(v_flags2=["-Wall -Wno-DECLFILENAME --if-depth 10"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_math_equal.py0000755000542200017500000000073415101701376022112 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_override.py0000755000542200017500000000073415101701376022776 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_var_lifetime_module_bad.py0000755000542200017500000000076615101701376024620 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_param_typedef2.v0000644000542200017500000000116115101701376022501 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Foo #(type T); endclass class Bar #(type T); endclass typedef Bar#(string) s_t; class Some #(type T); typedef Bar#(string) s_t; endclass module t; initial begin Some#(int)::s_t x[string]; Bar#(string) y[string]; if ($typename(Foo#(s_t)) != $typename(Foo#(Bar#(string)))) $stop; if ($typename(x) != $typename(y)) $stop; $write("*-* All finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_interconnect_bad.v0000644000542200017500000000066515101701376023110 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; interconnect a; assign a = 1; // Bad IEEE 6.6.8 - shall not be used in continuous assignment initial begin a = 2; // Bad IEEE 6.6.8 - shall not be used in procedural assignment end endmodule verilator-5.042/test_regress/t/t_castdyn_unsup_bad.py0000755000542200017500000000076615101701376023504 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lib_prot_shared.py0000755000542200017500000000434015101701376023127 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all', 'xsim') test.top_filename = "t/t_lib_prot.v" if test.benchmark: test.sim_time = test.benchmark * 100 trace_opt = "" if re.search(r'--no-trace', ' '.join(test.driver_verilator_flags)) else "-trace" secret_prefix = "secret" secret_dir = test.obj_dir + "/" + secret_prefix abs_secret_dir = os.path.abspath(secret_dir) test.mkdir_ok(secret_dir) # Always compile the secret file with Verilator no matter what simulator # we are testing with test.run(logfile=secret_dir + "/vlt_compile.log", cmd=["perl", os.environ["VERILATOR_ROOT"] + "/bin/verilator", (' --threads 6' if test.vltmt else ''), '--no-timing', "--prefix", "Vt_lib_prot_secret", "-cc", "-Mdir", secret_dir, "--protect-lib", secret_prefix, "--protect-key", "secret-key", "t/t_lib_prot_secret.v"], verilator_run=True) # yapf:disable test.run(logfile=secret_dir + "/secret_gcc.log", cmd=[os.environ["MAKE"], "-C", secret_dir, "-f", "Vt_lib_prot_secret.mk"]) test.compile(verilator_flags2=['--no-timing', "-LDFLAGS", "'-Wl,-rpath," + abs_secret_dir + " -L" + abs_secret_dir + " -l" + secret_prefix + "'", secret_dir + "/secret.sv"], xsim_flags2=[secret_dir + "/secret.sv"], threads=1, context_threads=(6 if test.vltmt else 1)) # yapf:disable test.execute(run_env="DYLD_FALLBACK_LIBRARY_PATH=" + abs_secret_dir, xsim_run_flags2=["--sv_lib", secret_dir + "/libsecret", "--dpi_absolute"]) if test.vlt and test.trace: # We can see the ports of the secret module test.file_grep(test.trace_filename, r'accum_in') # but we can't see what's inside test.file_grep_not(test.trace_filename, r'secret_') test.passes() verilator-5.042/test_regress/t/t_param_array3.v0000644000542200017500000000213415101701376022161 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; parameter int SIZES [3:0] = '{1,2,3,4}; typedef int calc_sums_t [3:0]; function static calc_sums_t calc_sums; int sum = 0; for (int i=0; i<4; i++) begin sum = sum + SIZES[i]; calc_sums[i] = sum; //TODO: calc_sums[i][31:0] = sum; end endfunction parameter int SUMS[3:0] = calc_sums(); parameter int SUMS1[3:0] = calc_sums(); initial begin if (SUMS[0] != 4) $stop; if (SUMS[1] != 4+3) $stop; if (SUMS[2] != 4+3+2) $stop; if (SUMS[3] != 4+3+2+1) $stop; // According to IEEE 1800-2023 13.4.3 // execution at elaboration has no effect on the initial values // of the variables used either at simulation time or among // multiple invocations of a function at elaboration time if (SUMS1 != SUMS) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_udp_bad_input_num.py0000755000542200017500000000076615101701376023473 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_genvar_misuse_bad.v0000644000542200017500000000111715101701376023255 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // See bug408 module top ( output logic [1:0] q, input logic [1:0] d, input logic clk ); genvar i; assign q[i] = d[i]; // <--- Error: Misusing genvar i genvar a, b, c; for (a = 0; a < 2; ++a) begin if (a); for (b = 0; b < 2; ++b) begin if (a); if (b); if (c); // <--- Error: Misusing genvar c end end endmodule verilator-5.042/test_regress/t/t_tri_pullup.py0000755000542200017500000000105615101701376022167 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_complex_fst_threads_2.py0000755000542200017500000000125715101701376025427 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_complex.v" test.golden_filename = "t/t_trace_complex_fst.out" test.compile(verilator_flags2=['--cc --trace-fst --trace-threads 2']) test.execute() test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_inst_slice.v0000644000542200017500000000416015101701376021735 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Varun Koyyalagunta. // SPDX-License-Identifier: CC0-1.0 // bug1015 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [1:0] i = crc[1:0]; logic [1:0] o [13:10] ; Test test (/*AUTOINST*/ // Outputs .o (o/*[1:0].[3:0]*/), // Inputs .i (i[1:0])); // Aggregate outputs into a single result vector wire [63:0] result = {32'h0, 6'h0,o[13], 6'h0,o[12], 6'h0,o[11], 6'h0,o[10]}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x sum=%x\n", $time, cyc, crc, result, sum); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end else if (cyc<10) begin sum <= '0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'hb42b2f48a0a9375a if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test ( output logic [1:0] o [3:0], //but this works //logic [N-1:0] o input [1:0] i); parameter N = 4; logic [1:0] a [3:0]; initial a = '{2'h0,2'h1,2'h2,2'h3}; sub sub [N-1:0] (.o (o), // many-to-many .a (a), // many-to-many .i (i)); // many-to-one endmodule module sub ( input logic [1:0] i, input logic [1:0] a, output logic [1:0] o ); assign o = i + a; endmodule verilator-5.042/test_regress/t/t_module_input_default_value_3_bad.v0000644000542200017500000000221215101701376026231 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Andrew Ranck // SPDX-License-Identifier: CC0-1.0 // Test for Issue#5358: Support default value on module input. // This test *is* expected to not compile, and must match .out file. module dut_should_fail_compile1 ( input logic i = 1'b1, output logic o ); initial i = 1'b0; // bad, should fail post link in V3Width assign o = i; endmodule module t (/*AUTOARG*/ // Inputs clk ); input clk; int cyc = 0; // 1800-2009, a few flavors to test: // We should have some DUT instances that fail to compile, // if you tried having a default value on port output. logic dut_should_fail_o; dut_should_fail_compile1 u_dut_should_fail_compile1 (.i(1'b0), .o(dut_should_fail_o) ); always @(posedge clk) begin : main cyc <= cyc + 1; if (cyc == 10) begin // done checking various DUTs and finish $display("%t %m: cyc=%0d", $time, cyc); $write("*-* All Finished *-*\n"); $finish(); end end endmodule : t verilator-5.042/test_regress/t/t_opt_subst.v0000644000542200017500000000206015101701376021620 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2025 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t ( input clk ); integer i; reg [94:0] w95; integer cyc = 0; // Test loop always @(posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d\n", $time, cyc); `endif cyc <= cyc + 1; if (cyc == 0) begin // Setup w95 = {95{1'b1}}; end else if (cyc == 1) begin if (w95++ != {95{1'b1}}) $stop; if (w95 != {95{1'b0}}) $stop; if (w95-- != {95{1'b0}}) $stop; if (w95 != {95{1'b1}}) $stop; if (++w95 != {95{1'b0}}) $stop; if (w95 != {95{1'b0}}) $stop; if (--w95 != {95{1'b1}}) $stop; if (w95 != {95{1'b1}}) $stop; end else if (cyc == 99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_dfg_circular.v0000644000542200017500000000132415101701376022224 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 // verilator lint_off UNOPTFLAT module t ( input wire i, output wire o ); wire a; wire b; wire c; wire d; assign c = i + 1'b1; assign d = c + 1'b1; assign a = b + d; assign b = a + 1'b1; wire p; wire q; wire r; wire s; assign p = i + 1'b1; assign q = p + 1'b1; assign r = s ^ q; assign s = r + 1'b1; wire x; wire y; wire z; wire w; assign x = y ^ i; assign y = x; assign z = w; assign w = y & z; assign o = b | x; endmodule verilator-5.042/test_regress/t/t_display.out0000644000542200017500000001627115101701376021616 0ustar mahmoudyfreeshell[0] In top.t: Hi [0] In top.t.sub.write_m (work.sub) [0] In top.t.sub.write_m.subblock (work.sub) [0] In top.t.sub2.write_m (work.sub2) [0] In top.t.sub2.write_m.subblock2 (work.sub2) a: -0.4=> 0.4 0 0 0 [0] Back \ Quote " [0] %b=000001100 %0b=1100 %b=00000101010111011101110111100110011001100 %0b=101010111011101110111100110011001100 %b=000001010101111000001001000110100010101100111100000010010001101000101011001111000 %0b=1010101111000001001000110100010101100111100000010010001101000101011001111000 [0] %B=000001100 %0B=1100 %B=00000101010111011101110111100110011001100 %0B=101010111011101110111100110011001100 %B=000001010101111000001001000110100010101100111100000010010001101000101011001111000 %0B=1010101111000001001000110100010101100111100000010010001101000101011001111000 [0] %d= 12 %0d=12 %d= 46099320012 %0d=46099320012 %d= 50692964483019020981880 %0d=50692964483019020981880 [0] %D= 12 %0D=12 %D= 46099320012 %0D=46099320012 %D= 50692964483019020981880 %0D=50692964483019020981880 [0] %h=00c %0h=c %h=00abbbbcccc %0h=abbbbcccc %h=00abc1234567812345678 %0h=abc1234567812345678 [0] %H=00c %0H=c %H=00abbbbcccc %0H=abbbbcccc %H=00abc1234567812345678 %0H=abc1234567812345678 [0] %o=014 %0o=14 %o=00527356746314 %0o=527356746314 %o=012570110642547402215053170 %0o=12570110642547402215053170 [0] %O=014 %0O=14 %O=00527356746314 %0O=527356746314 %O=012570110642547402215053170 %0O=12570110642547402215053170 [0] %x=00c %0x=c %x=00abbbbcccc %0x=abbbbcccc %x=00abc1234567812345678 %0x=abc1234567812345678 [0] %X=00c %0X=c %X=00abbbbcccc %0X=abbbbcccc %X=00abc1234567812345678 %0X=abc1234567812345678 [0] %d= 12 %0d=12 %d= -46099320012 %0d=-46099320012 %d= 50692964483019020981880 %0d=50692964483019020981880 [0] %D= 12 %0D=12 %D= -46099320012 %0D=-46099320012 %D= -50692964483019020981880 %0D=-50692964483019020981880 [0] %b=000001100 %0b=1100 %b=00000101010111011101110111100110011001100 %0b=101010111011101110111100110011001100 %b=000001010101111000001001000110100010101100111100000010010001101000101011001111000 %0b=1010101111000001001000110100010101100111100000010010001101000101011001111000 [0] %B=000001100 %0B=1100 %B=00000101010111011101110111100110011001100 %0B=101010111011101110111100110011001100 %B=000001010101111000001001000110100010101100111100000010010001101000101011001111000 %0B=1010101111000001001000110100010101100111100000010010001101000101011001111000 [0] %d= 12 %0d=12 %d= 46099320012 %0d=46099320012 %d= 50692964483019020981880 %0d=50692964483019020981880 [0] %D= 12 %0D=12 %D= 46099320012 %0D=46099320012 %D= 50692964483019020981880 %0D=50692964483019020981880 [0] %h=00c %0h=c %h=00abbbbcccc %0h=abbbbcccc %h=00abc1234567812345678 %0h=abc1234567812345678 [0] %H=00c %0H=c %H=00abbbbcccc %0H=abbbbcccc %H=00abc1234567812345678 %0H=abc1234567812345678 [0] %o=014 %0o=14 %o=00527356746314 %0o=527356746314 %o=012570110642547402215053170 %0o=12570110642547402215053170 [0] %O=014 %0O=14 %O=00527356746314 %0O=527356746314 %O=012570110642547402215053170 %0O=12570110642547402215053170 [0] %x=00c %0x=c %x=00abbbbcccc %0x=abbbbcccc %x=00abc1234567812345678 %0x=abc1234567812345678 [0] %X=00c %0X=c %X=00abbbbcccc %0X=abbbbcccc %X=00abc1234567812345678 %0X=abc1234567812345678 [0] %d= -12 %0d=-12 %d= -46099320012 %0d=-46099320012 %d= -50692964483019020981880 %0d=-50692964483019020981880 [0] %D= -12 %0D=-12 %D= -46099320012 %0D=-46099320012 %D= -50692964483019020981880 %0D=-50692964483019020981880 [0] %C=m %0C=m [0] %c=m %0c=m [0] %v=St0 St0 St0 St0 St0 St1 St1 St0 St0 %0v=St0 St0 St0 St0 St0 St1 St1 St0 St0 %v=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0 %0v=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0 %v=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0 %0v=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0 < [0] %V=St0 St0 St0 St0 St0 St1 St1 St0 St0 %0V=St0 St0 St0 St0 St0 St1 St1 St0 St0 %V=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0 %0V=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0 %V=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0 %0V=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0 < [0] %p= 12 %0p='hc %p= 46099320012 %0p='habbbbcccc %p= 50692964483019020981880 %0p='habc1234567812345678 [0] %P= 12 %0P='hc %P= 46099320012 %0P='habbbbcccc %P= 50692964483019020981880 %0P='habc1234567812345678 [0] %P="sv-str" [0] %u=dcba %0u=dcba [0] %U=dcba %0U=dcba [0] %D= 12 %d= 12 %01d=12 %06d=000012 %6d= 12 %-06d=12 %-6d=12 [0] %X=00c %x=00c %01x=c %06x=00000c %6x=00000c %-06x=c %-6x=c [0] %O=014 %o=014 %01o=14 %06o=000014 %6o=000014 %-06o=14 %-6o=14 [0] %B=000001100 %b=000001100 %01b=1100 %06b=001100 %6b=001100 %-06b=1100 %-6b=1100 [0] %t= 0 %03t= 0 %0t=0 [0] %s=! %s= what! %s= hmmm!1234 [0] %6s=: !: %6s=: what!: %6s=: hmmm!1234: [0] %8s=: sv-str: d: 12 12 h: 00c 00c o: 014 014 b: 000001100 000001100 -1431655766 -1431655766 4294967294 4294967294 2863311530 2863311530 assoc_c='{} [0] hello, from a very long string. Percent %s are literally substituted in. hello, from a concatenated string. hello, from a concatenated format string [0]. two 2 args 3with commas extra argument: 0 0 : pre argument after empty: > < [0] Embedded tab ' ' and <#013> return [0] Embedded multiline '23 23 23' '23 23 23 ' '23 23 23' '23 23 23 ' ' 24' '24 ' ' 0' '0 ' ' sv-str' 'sv-str ' ' meep' 'meep ' ' beep' 'beep ' log10(2) = 2 x xxXa xxxX2 XXX Zx5X zx5X x z X Z ZzX ZzXx XXXx 10 [50] FIFTY 50 [0] FIFTY 50 [0] not-fmt %-d 60 [0] fmt-as-string-not-%0x 70 s=[0] fmt-string-not-%s *-* All Finished *-* verilator-5.042/test_regress/t/t_implements_noninterface_bad.py0000755000542200017500000000076615101701376025515 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_if_same_bad.py0000755000542200017500000000106015101701376022174 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint( # expect_filename = test.golden_filename fails=False) # bug3806 - this test should fail but does not test.passes() verilator-5.042/test_regress/t/t_dist_fixme.py0000755000542200017500000000224015101701376022117 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') if not os.path.exists(test.root + "/.git"): test.skip("Not in a git repository") ### Must trim output before and after our file list files = test.run_capture("cd " + test.root + " && git ls-files --exclude-standard") if test.verbose: print("ST " + files) names = {} files = re.sub(r'\s+', ' ', files) regex = r'(FIX[M]E|BO[Z]O)' for filename in files.split(): if re.search(regex, filename): names[filename] = True filename = os.path.join(test.root, filename) if not os.path.exists(filename): continue wholefile = test.file_contents(filename) if re.search(regex, wholefile): names[filename] = True if len(names): test.error("Files with FIX" + "MEs: " + ' '.join(sorted(names.keys()))) test.passes() verilator-5.042/test_regress/t/t_gate_elim_cycle.py0000755000542200017500000000071415101701376023075 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.passes() verilator-5.042/test_regress/t/t_lint_caseincomplete_bad.v0000644000542200017500000000062715101701376024434 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Test of select from constant // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs i ); input [1:0] i; always_comb begin case (i) 2'b00: ; 2'b10: ; 2'b11: ; endcase end endmodule verilator-5.042/test_regress/t/t_trace_wide_struct.py0000755000542200017500000000077415101701376023510 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--trace-vcd --trace-structs']) test.passes() verilator-5.042/test_regress/t/t_case_enum_incomplete_wildcard_bad.py0000755000542200017500000000102515101701376026621 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=['--assert'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_param_func.v0000644000542200017500000000147015101701376021715 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This test examines Verilator against paramter definition with functions. // Particularly the function takes in argument which is multi-dimentional. // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Roland Kruse and Jie Xu. // SPDX-License-Identifier: CC0-1.0 module test#( parameter SIZE = 4, parameter P = sum({32'h1,32'h2,32'h3,32'h4}, SIZE)) (input clk, input logic sel, output [P:0] res); logic [P:0] cc = 'h45; assign res = sel ? cc : {(P+1){1'b1}}; function integer sum; input [3:0][31:0] values; input int size; sum = 0; begin for (int i = 0; i < size; i ++) sum += values[i]; end endfunction endmodule verilator-5.042/test_regress/t/t_timing_class_static_delay.py0000755000542200017500000000076315101701376025175 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_genfor_hier.v0000644000542200017500000000115515101701376022071 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Demonstrate deferred linking across module // bondaries // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 module m1(); logic v1; endmodule module t; for (genvar the_genvar = 0; the_genvar < 4; the_genvar++) begin : m1_b m1 m1_inst(); end for (genvar the_other_genvar = 0; the_other_genvar < 4; the_other_genvar++) begin always_comb m1_b[the_other_genvar].m1_inst.v1 = 1'b0; end initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_timing_wait2.py0000755000542200017500000000103515101701376022362 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_assert_pre.py0000755000542200017500000000073415101701376022141 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_order_blkloopinit_bad.out0000644000542200017500000000063315101701376024473 0ustar mahmoudyfreeshell%Error-BLKLOOPINIT: t/t_order_blkloopinit_bad.v:26:20: Unsupported: Non-blocking assignment to array with compound element type inside loop : ... note: In instance 't' 26 | array2[i] <= null; | ^~ ... For error description see https://verilator.org/warn/BLKLOOPINIT?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_lint_latch_5.py0000755000542200017500000000070315101701376022333 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint() test.passes() verilator-5.042/test_regress/t/t_queue_method_bad.out0000644000542200017500000000414415101701376023437 0ustar mahmoudyfreeshell%Error: t/t_queue_method_bad.v:15:9: The 1 arguments passed to .reverse method does not match its requiring 0 arguments : ... note: In instance 't' 15 | q.reverse(1); | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_queue_method_bad.v:16:9: The 1 arguments passed to .shuffle method does not match its requiring 0 arguments : ... note: In instance 't' 16 | q.shuffle(1); | ^~~~~~~ %Error: t/t_queue_method_bad.v:17:14: 'with' statement is required for .find method : ... note: In instance 't' 17 | qv = q.find; | ^~~~ %Error: t/t_queue_method_bad.v:18:14: 'with' statement is required for .find_first method : ... note: In instance 't' 18 | qv = q.find_first; | ^~~~~~~~~~ %Error: t/t_queue_method_bad.v:19:14: 'with' statement is required for .find_last method : ... note: In instance 't' 19 | qv = q.find_last; | ^~~~~~~~~ %Error: t/t_queue_method_bad.v:20:14: 'with' statement is required for .find_index method : ... note: In instance 't' 20 | qi = q.find_index; | ^~~~~~~~~~ %Error: t/t_queue_method_bad.v:21:14: 'with' statement is required for .find_first_index method : ... note: In instance 't' 21 | qi = q.find_first_index; | ^~~~~~~~~~~~~~~~ %Error: t/t_queue_method_bad.v:22:14: 'with' statement is required for .find_last_index method : ... note: In instance 't' 22 | qi = q.find_last_index; | ^~~~~~~~~~~~~~~ %Error: t/t_queue_method_bad.v:24:19: 'with' not legal on this method : ... note: In instance 't' 24 | qi = q.size with (1); | ^~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_x_rand_stability_add_trace.py0000755000542200017500000000122415101701376025312 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios("vlt") test.top_filename = "t/t_x_rand_stability.v" test.compile(verilator_flags2=["--x-initial unique", "-DADD_SIGNAL", "--trace"]) test.execute(all_run_flags=["+verilator+rand+reset+2"], expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_vpi_onetime_cbs.cpp0000644000542200017500000002312115101701376023261 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2021 by Wilson Snyder and Marlon James. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // Setup multiple one-time callbacks with different time delays. // Ensure they are not called before the delay has elapsed. #ifdef IS_VPI #include "vpi_user.h" #include #else #include "verilated.h" #include "verilated_vpi.h" #include VM_PREFIX_INCLUDE #endif extern "C" { #include } // These require the above. Comment prevents clang-format moving them #include "TestSimulator.h" #include "TestVpi.h" #include #include #include #include #include typedef struct { PLI_UINT32 count; PLI_UINT32* exp_times; PLI_UINT32 number_of_exp_times; } cb_stats; static cb_stats CallbackStats[cbAtEndOfSimTime + 1]; bool got_error = false; static vpiHandle ValueHandle, ToggleHandle, ClockHandle; #ifdef TEST_VERBOSE bool verbose = true; #else bool verbose = false; #endif #define STRINGIFY_CB_CASE(_cb) \ case _cb: return #_cb static const char* cb_reason_to_string(int cb_name) { switch (cb_name) { STRINGIFY_CB_CASE(cbAtStartOfSimTime); STRINGIFY_CB_CASE(cbReadWriteSynch); STRINGIFY_CB_CASE(cbReadOnlySynch); STRINGIFY_CB_CASE(cbNextSimTime); STRINGIFY_CB_CASE(cbStartOfSimulation); STRINGIFY_CB_CASE(cbEndOfSimulation); STRINGIFY_CB_CASE(cbAtEndOfSimTime); default: return "Unsupported callback"; } } #undef STRINGIFY_CB_CASE bool cb_time_is_delay(int cb_name) { // For some callbacks, time is interpreted as a delay from current time // instead of an absolute time if (cb_name == cbReadOnlySynch || cb_name == cbReadWriteSynch) return true; return false; } // forward declaration static PLI_INT32 TheCallback(s_cb_data* data); static PLI_INT32 AtEndOfSimTimeCallback(s_cb_data* data) { s_vpi_time t; cb_stats* stats = &CallbackStats[data->reason]; t.type = vpiSimTime; vpi_get_time(0, &t); if (verbose) vpi_printf(const_cast("- [@%d] AtEndOfSimTime Callback\n"), t.low); CHECK_RESULT(t.low, stats->exp_times[stats->count]); stats->count += 1; s_cb_data cb_data; s_vpi_time time = {vpiSimTime, 0, 417, 0}; // non-zero time to check that it's ignored cb_data.time = &time; cb_data.reason = cbNextSimTime; cb_data.cb_rtn = TheCallback; vpiHandle Handle = vpi_register_cb(&cb_data); CHECK_RESULT_NZ(Handle); return 0; } static PLI_INT32 TheCallback(s_cb_data* data) { s_vpi_time t; cb_stats* stats = &CallbackStats[data->reason]; t.type = vpiSimTime; vpi_get_time(0, &t); if (verbose) { vpi_printf(const_cast("- [@%d] %s Callback\n"), t.low, cb_reason_to_string(data->reason)); } CHECK_RESULT(t.low, stats->exp_times[stats->count]); stats->count += 1; if (stats->count >= stats->number_of_exp_times) return 0; s_cb_data cb_data; PLI_UINT32 next_time; if (data->reason == cbNextSimTime) { // if a cbNextSimTime calback is scheduled from // another cbNextSimTime callback, it will // be called in the same timestep, so we need // to delay registering next_time = t.low; cb_data.reason = cbAtEndOfSimTime; cb_data.cb_rtn = AtEndOfSimTimeCallback; } else { next_time = stats->exp_times[stats->count]; if (cb_time_is_delay(data->reason)) next_time -= t.low; cb_data.reason = data->reason; cb_data.cb_rtn = TheCallback; } if (verbose) { vpi_printf(const_cast("- [@%d] Registering %s Callback with time = %d\n"), t.low, cb_reason_to_string(cb_data.reason), next_time); } s_vpi_time time = {vpiSimTime, 0, next_time, 0}; cb_data.time = &time; vpiHandle Handle = vpi_register_cb(&cb_data); CHECK_RESULT_NZ(Handle); return 0; } static PLI_INT32 StartOfSimulationCallback(s_cb_data* data) { s_cb_data cb_data; s_vpi_time timerec = {vpiSimTime, 0, 0, 0}; s_vpi_time t; t.type = vpiSimTime; vpi_get_time(0, &t); if (verbose) vpi_printf(const_cast("- [@%d] cbStartOfSimulation Callback\n"), t.low); CHECK_RESULT(t.low, CallbackStats[data->reason].exp_times[0]); CallbackStats[data->reason].count += 1; cb_data.time = &timerec; cb_data.value = 0; cb_data.user_data = 0; cb_data.obj = 0; cb_data.cb_rtn = TheCallback; CallbackStats[cbAtStartOfSimTime].exp_times = new PLI_UINT32[3]{5, 15, 20}; CallbackStats[cbAtStartOfSimTime].number_of_exp_times = 3; timerec.low = 5; cb_data.reason = cbAtStartOfSimTime; vpiHandle ASOSHandle = vpi_register_cb(&cb_data); CHECK_RESULT_NZ(ASOSHandle); CallbackStats[cbReadWriteSynch].exp_times = new PLI_UINT32[3]{6, 16, 21}; CallbackStats[cbReadWriteSynch].number_of_exp_times = 3; timerec.low = 6; cb_data.reason = cbReadWriteSynch; vpiHandle RWHandle = vpi_register_cb(&cb_data); CHECK_RESULT_NZ(RWHandle); CallbackStats[cbReadOnlySynch].exp_times = new PLI_UINT32[3]{7, 17, 22}; CallbackStats[cbReadOnlySynch].number_of_exp_times = 3; timerec.low = 7; cb_data.reason = cbReadOnlySynch; vpiHandle ROHandle = vpi_register_cb(&cb_data); CHECK_RESULT_NZ(ROHandle); CallbackStats[cbNextSimTime].exp_times = new PLI_UINT32[9]{5, 6, 7, 15, 16, 17, 20, 21, 22}; CallbackStats[cbNextSimTime].number_of_exp_times = 9; timerec.low = 8; cb_data.reason = cbNextSimTime; vpiHandle NSTHandle = vpi_register_cb(&cb_data); CHECK_RESULT_NZ(NSTHandle); CallbackStats[cbAtEndOfSimTime].exp_times = new PLI_UINT32[8]{5, 6, 7, 15, 16, 17, 20, 21}; CallbackStats[cbAtEndOfSimTime].number_of_exp_times = 8; return (0); } static int EndOfSimulationCallback(p_cb_data cb_data) { s_vpi_time t; t.type = vpiSimTime; vpi_get_time(0, &t); (void)cb_data; // Unused if (verbose) vpi_printf(const_cast("- [@%d] cbEndOfSimulation Callback\n"), t.low); CHECK_RESULT(t.low, CallbackStats[cbEndOfSimulation].exp_times[0]); CallbackStats[cbEndOfSimulation].count += 1; CHECK_RESULT(CallbackStats[cbStartOfSimulation].count, 1); CHECK_RESULT(CallbackStats[cbAtStartOfSimTime].count, 3); CHECK_RESULT(CallbackStats[cbNextSimTime].count, 9); CHECK_RESULT(CallbackStats[cbReadWriteSynch].count, 3); CHECK_RESULT(CallbackStats[cbReadOnlySynch].count, 3); CHECK_RESULT(CallbackStats[cbAtEndOfSimTime].count, 8); CHECK_RESULT(CallbackStats[cbEndOfSimulation].count, 1); if (!got_error) printf("*-* All Finished *-*\n"); return 0; } // cver entry static void VPIRegister(void) { // Clear stats for (int cb = 1; cb <= cbAtEndOfSimTime; cb++) CallbackStats[cb].count = 0; CallbackStats[cbStartOfSimulation].exp_times = new PLI_UINT32(0); CallbackStats[cbEndOfSimulation].exp_times = new PLI_UINT32(22); s_cb_data cb_data; s_vpi_time timerec = {vpiSuppressTime, 0, 0, 0}; cb_data.time = &timerec; cb_data.value = 0; cb_data.user_data = 0; cb_data.obj = 0; cb_data.reason = cbStartOfSimulation; cb_data.cb_rtn = StartOfSimulationCallback; vpi_register_cb(&cb_data); cb_data.reason = cbEndOfSimulation; cb_data.cb_rtn = EndOfSimulationCallback; vpi_register_cb(&cb_data); } #ifdef IS_VPI // icarus entry void (*vlog_startup_routines[])(void) = {VPIRegister, 0}; #else int main(int argc, char** argv, char** env) { double sim_time = 100; const std::unique_ptr contextp{new VerilatedContext}; bool cbs_called; contextp->commandArgs(argc, argv); // contextp->debug(9); const std::unique_ptr topp{new VM_PREFIX{contextp.get(), // Note null name - we're flattening it out ""}}; topp->clk = 1; // StartOfSimulationCallback(nullptr); VPIRegister(); VerilatedVpi::callCbs(cbStartOfSimulation); topp->clk = 0; topp->eval(); while (contextp->time() < sim_time && !contextp->gotFinish()) { VerilatedVpi::callTimedCbs(); VerilatedVpi::callCbs(cbNextSimTime); VerilatedVpi::callCbs(cbAtStartOfSimTime); topp->eval(); VerilatedVpi::callValueCbs(); VerilatedVpi::callCbs(cbReadWriteSynch); VerilatedVpi::callCbs(cbReadOnlySynch); VerilatedVpi::callCbs(cbAtEndOfSimTime); const uint64_t next_time = VerilatedVpi::cbNextDeadline(); if (next_time != -1) contextp->time(next_time); if (verbose) vpi_printf(const_cast("- [@%" PRId64 "] time change\n"), contextp->time()); if (next_time == -1 && !contextp->gotFinish()) { if (got_error) { vl_stop(__FILE__, __LINE__, "TOP-cpp"); } else { VerilatedVpi::callCbs(cbEndOfSimulation); contextp->gotFinish(true); } } // Count updates on rising edge, so cycle through falling edge as well topp->clk = !topp->clk; topp->eval(); topp->clk = !topp->clk; } if (!contextp->gotFinish()) { vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); } topp->final(); exit(0L); } #endif verilator-5.042/test_regress/t/t_langext_4_bad.out0000644000542200017500000000053115101701376022634 0ustar mahmoudyfreeshell%Error: t/t_langext_2.v:49:21: syntax error, unexpected case 49 | unique0 case (i) | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Cannot continue ... This fatal error may be caused by the earlier error(s); resolve those first. verilator-5.042/test_regress/t/t_mod_dup_ign.py0000755000542200017500000000070315101701376022252 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint() test.passes() verilator-5.042/test_regress/t/t_opt_table_sparse.out0000644000542200017500000000027515101701376023474 0ustar mahmoudyfreeshellcyle 0 = 0 cyle 1 = 1 cyle 2 = 1 cyle 3 = 99 cyle 4 = 4 cyle 5 = 5 cyle 6 = 99 cyle 7 = 99 *-* All Finished *-* verilator-5.042/test_regress/t/t_opt_const_shortcut.py0000755000542200017500000000110015101701376023721 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=["t/" + test.name + ".cpp"], verilator_flags2=["-Wno-UNOPTTHREADS", "--stats"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_ref_trace_fst_sc.py0000755000542200017500000000127315101701376025304 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_ref_trace.v" if not test.have_sc: test.skip("No SystemC installed") test.compile(verilator_flags2=['--trace-structs --trace-fst --sc']) test.execute() test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_assert_cover_off.py0000755000542200017500000000102015101701376023310 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_assert_cover.v" test.compile(v_flags2=[]) test.execute() test.passes() verilator-5.042/test_regress/t/t_func_return.py0000755000542200017500000000073415101701376022324 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_mod_uselib.v0000644000542200017500000000067715101701376021734 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; // // `uselib {dir= | file= | libext= | lib= `uselib libext=.v s s (); endmodule module s; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_constraint_foreach.v0000644000542200017500000000306715101701376023461 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `define check_rand(cl, field, cond) \ begin \ longint prev_result; \ int ok = 0; \ if (!bit'(cl.randomize())) $stop; \ prev_result = longint'(field); \ if (!(cond)) $stop; \ repeat(9) begin \ longint result; \ if (!bit'(cl.randomize())) $stop; \ result = longint'(field); \ if (!(cond)) $stop; \ if (result != prev_result) ok = 1; \ prev_result = result; \ end \ if (ok != 1) $stop; \ end class C; rand int x; int q[$] = {0, 0, 0, 0, 0}; constraint fore { x < 7; foreach(q[i]) x > i; foreach(q[i]) // loop again with the same index name x > i; }; endclass class D; rand bit posit; rand int x; int o[$]; // empty int p[$] = {1}; int q[$] = {0, 0, 0, 0, 0}; constraint fore { if (posit == 1) { foreach(o[i]) o[i] > 0; } if (posit == 1) { foreach(p[i]) p[i] > 0; } if (posit == 1) { x < 7; foreach(q[i]) x > i; } else { x > -3; foreach(q[i]) x < i; } }; endclass module t; initial begin C c = new; D d = new; `check_rand(c, c.x, 4 < c.x && c.x < 7); `check_rand(d, d.posit, (d.posit ? 4 : -3) < d.x && d.x < (d.posit ? 7 : 0)); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_sys_file_basic_mcd.out0000644000542200017500000000011415101701376023737 0ustar mahmoudyfreeshellSean Connery was the best Bond. To file and to stdout *-* All Finished *-* verilator-5.042/test_regress/t/t_alw_nosplit.py0000755000542200017500000000112415101701376022317 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--stats"]) if test.vlt_all: test.file_grep(test.stats, r'Optimizations, Split always\s+(\d+)', 0) test.execute() test.passes() verilator-5.042/test_regress/t/t_fork_jumpblock.py0000755000542200017500000000077115101701376023002 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_gate_strength.v0000644000542200017500000000422015101701376022434 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; logic [31:0] a; // verilator lint_off IMPLICIT assign (highz0, supply1) nt00 = a[0]; assign (supply0, highz1) nt01 = a[0]; assign (supply0, supply1) nt02 = a[0]; assign (strong0, strong1) nt03 = a[0]; assign (pull0, pull1) nt04 = a[0]; assign (weak0, weak1) nt05 = a[0]; assign (highz0, supply1) nt10 = a[0]; assign (supply0, highz1) nt11 = a[0]; assign (supply0, supply1) nt12 = a[0]; assign (strong0, strong1) nt13 = a[0]; assign (pull0, pull1) nt14 = a[0]; assign (weak0, weak1) nt15 = a[0]; // verilator lint_on IMPLICIT always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin a <= 32'h18f6b030; end if (cyc==2) begin a <= 32'h18f6b03f; if (nt00 !== 1'b0) $stop; if (nt01 !== 1'b0) $stop; if (nt02 !== 1'b0) $stop; if (nt03 !== 1'b0) $stop; if (nt04 !== 1'b0) $stop; if (nt05 !== 1'b0) $stop; if (nt10 !== 1'b0) $stop; if (nt11 !== 1'b0) $stop; if (nt12 !== 1'b0) $stop; if (nt13 !== 1'b0) $stop; if (nt14 !== 1'b0) $stop; if (nt15 !== 1'b0) $stop; end if (cyc==3) begin if (nt00 !== 1'b1) $stop; if (nt01 !== 1'b1) $stop; if (nt02 !== 1'b1) $stop; if (nt03 !== 1'b1) $stop; if (nt04 !== 1'b1) $stop; if (nt05 !== 1'b1) $stop; if (nt10 !== 1'b1) $stop; if (nt11 !== 1'b1) $stop; if (nt12 !== 1'b1) $stop; if (nt13 !== 1'b1) $stop; if (nt14 !== 1'b1) $stop; if (nt15 !== 1'b1) $stop; end if (cyc==4) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.042/test_regress/t/t_inst_tree_inl0_pub0.vlt0000644000542200017500000000036415101701376024007 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. // SPDX-License-Identifier: CC0-1.0 `verilator_config no_inline -module "l*" verilator-5.042/test_regress/t/t_class_param_nested_bad.out0000644000542200017500000000144115101701376024577 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_class_param_nested_bad.v:51:23: dotted expressions in parameters : ... note: In instance 't' : ... Suggest use a typedef 51 | Wrap2 #(Wrap#(19)::PBASE * 2) w38; | ^~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Internal Error: t/t_class_param_nested_bad.v:51:23: ../V3Width.cpp:#: Node has no type : ... note: In instance 't' 51 | Wrap2 #(Wrap#(19)::PBASE * 2) w38; | ^~~~~ ... This fatal error may be caused by the earlier error(s); resolve those first. verilator-5.042/test_regress/t/t_gen_class.py0000755000542200017500000000077115101701376021731 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--binary']) test.execute() test.passes() verilator-5.042/test_regress/t/t_randstate_obj.py0000755000542200017500000000073415101701376022611 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_param_type.v0000644000542200017500000000404515101701376021744 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Iztok Jeras. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; // counters int cnt; int cnt_bit ; int cnt_byte; int cnt_int ; int cnt_ar1d; int cnt_ar2d; // sizes int siz_bit ; int siz_byte; int siz_int ; int siz_ar1d; int siz_ar2d; // add all counters assign cnt = cnt_bit + cnt_byte + cnt_int + cnt_ar1d + cnt_ar2d; // finish report always @ (posedge clk) if (cnt == 5) begin if (siz_bit != 1) $stop(); if (siz_byte != 8) $stop(); if (siz_int != 32) $stop(); if (siz_ar1d != 24) $stop(); if (siz_ar2d != 16) $stop(); end else if (cnt > 5) begin $write("*-* All Finished *-*\n"); $finish; end // instances with various types mod_typ #(.TYP (bit )) mod_bit (clk, cnt_bit [ 1-1:0], siz_bit ); mod_typ #(.TYP (byte )) mod_byte (clk, cnt_byte[ 8-1:0], siz_byte); mod_typ #(.TYP (int )) mod_int (clk, cnt_int [32-1:0], siz_int ); mod_typ #(.TYP (bit [23:0] )) mod_ar1d (clk, cnt_ar1d[24-1:0], siz_ar1d); mod_typ #(.TYP (bit [3:0][3:0])) mod_ar2d (clk, cnt_ar2d[16-1:0], siz_ar2d); // double types mod_typ2 #(.WIDTH1(3), .WIDTH2(3), .TYP1(bit [2:0])) mod2_3_3(); mod_typ2 #(.WIDTH1(3), .WIDTH2(5), .TYP1(bit [2:0]), .TYP2(bit[4:0])) mod2_3_5(); endmodule : t module mod_typ #( parameter type TYP = byte )( input logic clk, output TYP cnt, output int siz ); initial cnt = 0; always @ (posedge clk) cnt <= cnt + 1; assign siz = $bits (cnt); endmodule module mod_typ2 #( parameter int WIDTH1 = 0, parameter int WIDTH2 = WIDTH1, parameter type TYP1 = byte, // Below we need to imply that TYP2 is a type TYP2 = TYP1 )(); TYP1 t1; TYP2 t2; initial begin if ($bits(t1) != WIDTH1) $stop; if ($bits(t2) != WIDTH2) $stop; end endmodule verilator-5.042/test_regress/t/t_dpi_arg_input_type.v0000644000542200017500000010126715101701376023474 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2020 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VCS `define NO_TIME `endif `ifdef NC `define NO_TIME `define NO_INTEGER `define NO_SHORTREAL `endif `ifdef MS `endif `ifdef VERILATOR `define NO_SHORTREAL `define NULL 64'd0 `else `define NULL null `endif module t (/*AUTOARG*/ // Inputs clk ); input clk; `ifdef VERILATOR wire _unused = &{1'b0, clk}; `endif // Legal input argument types for DPI functions //====================================================================== // Type definitions //====================================================================== // Basic types as per IEEE 1800-2023 35.5.6 typedef byte byte_t; typedef byte unsigned byte_unsigned_t; typedef shortint shortint_t; typedef shortint unsigned shortint_unsigned_t; typedef int int_t; typedef int unsigned int_unsigned_t; typedef longint longint_t; typedef longint unsigned longint_unsigned_t; `ifndef NO_TIME typedef time time_t; `endif `ifndef NO_INTEGER typedef integer integer_t; `endif typedef real real_t; `ifndef NO_SHORTREAL typedef shortreal shortreal_t; `endif typedef chandle chandle_t; typedef string string_t; typedef bit bit_t; typedef logic logic_t; // 2-state packed structures typedef struct packed { bit x; } struct_2_state_1; typedef struct packed { bit [15:0] x; bit [15:0] y; } struct_2_state_32; typedef struct packed { bit [15:0] x; bit [16:0] y; } struct_2_state_33; typedef struct packed { bit [31:0] x; bit [31:0] y; } struct_2_state_64; typedef struct packed { bit [31:0] x; bit [32:0] y; } struct_2_state_65; typedef struct packed { bit [63:0] x; bit [63:0] y; } struct_2_state_128; // 2-state packed unions typedef union packed { bit x; bit y; } union_2_state_1; typedef union packed { bit [31:0] x; bit [31:0] y; } union_2_state_32; typedef union packed { bit [32:0] x; bit [32:0] y; } union_2_state_33; typedef union packed { bit [63:0] x; bit [63:0] y; } union_2_state_64; typedef union packed { bit [64:0] x; bit [64:0] y; } union_2_state_65; typedef union packed { bit [127:0] x; bit [127:0] y; } union_2_state_128; // 4-state packed structures typedef struct packed { logic x; } struct_4_state_1; typedef struct packed { logic [15:0] x; bit [15:0] y; } struct_4_state_32; typedef struct packed { logic [15:0] x; bit [16:0] y; } struct_4_state_33; typedef struct packed { logic [31:0] x; bit [31:0] y; } struct_4_state_64; typedef struct packed { logic [31:0] x; bit [32:0] y; } struct_4_state_65; typedef struct packed { logic [63:0] x; bit [63:0] y; } struct_4_state_128; // 4-state packed unions typedef union packed { logic x; bit y; } union_4_state_1; typedef union packed { logic [31:0] x; bit [31:0] y; } union_4_state_32; typedef union packed { logic [32:0] x; bit [32:0] y; } union_4_state_33; typedef union packed { logic [63:0] x; bit [63:0] y; } union_4_state_64; typedef union packed { logic [64:0] x; bit [64:0] y; } union_4_state_65; typedef union packed { logic [127:0] x; bit [127:0] y; } union_4_state_128; //====================================================================== // Imports //====================================================================== // Basic types as per IEEE 1800-2023 35.5.6 import "DPI-C" function void i_byte (input byte i); import "DPI-C" function void i_byte_unsigned (input byte unsigned i); import "DPI-C" function void i_shortint (input shortint i); import "DPI-C" function void i_shortint_unsigned (input shortint unsigned i); import "DPI-C" function void i_int (input int i); import "DPI-C" function void i_int_unsigned (input int unsigned i); import "DPI-C" function void i_longint (input longint i); import "DPI-C" function void i_longint_unsigned (input longint unsigned i); `ifndef NO_TIME import "DPI-C" function void i_time (input time i); `endif `ifndef NO_INTEGER import "DPI-C" function void i_integer (input integer i); `endif import "DPI-C" function void i_real (input real i); `ifndef NO_SHORTREAL import "DPI-C" function void i_shortreal (input shortreal i); `endif import "DPI-C" function void i_chandle (input chandle i); import "DPI-C" function void i_string (input string i); import "DPI-C" function void i_bit (input bit i); import "DPI-C" function void i_logic (input logic i); // Basic types via typedef import "DPI-C" function void i_byte_t (input byte_t i); import "DPI-C" function void i_byte_unsigned_t (input byte_unsigned_t i); import "DPI-C" function void i_shortint_t (input shortint_t i); import "DPI-C" function void i_shortint_unsigned_t (input shortint_unsigned_t i); import "DPI-C" function void i_int_t (input int_t i); import "DPI-C" function void i_int_unsigned_t (input int_unsigned_t i); import "DPI-C" function void i_longint_t (input longint_t i); import "DPI-C" function void i_longint_unsigned_t (input longint_unsigned_t i); `ifndef NO_TIME import "DPI-C" function void i_time_t (input time_t i); `endif `ifndef NO_INTEGER import "DPI-C" function void i_integer_t (input integer_t i); `endif import "DPI-C" function void i_real_t (input real_t i); `ifndef NO_SHORTREAL import "DPI-C" function void i_shortreal_t (input shortreal_t i); `endif import "DPI-C" function void i_chandle_t (input chandle_t i); import "DPI-C" function void i_string_t (input string_t i); import "DPI-C" function void i_bit_t (input bit_t i); import "DPI-C" function void i_logic_t (input logic_t i); // 2-state packed arrays import "DPI-C" function void i_array_2_state_1 (input bit [ 0:0] i); import "DPI-C" function void i_array_2_state_32 (input bit [ 31:0] i); import "DPI-C" function void i_array_2_state_33 (input bit [ 32:0] i); import "DPI-C" function void i_array_2_state_64 (input bit [ 63:0] i); import "DPI-C" function void i_array_2_state_65 (input bit [ 64:0] i); import "DPI-C" function void i_array_2_state_128(input bit [127:0] i); // 2-state packed structures import "DPI-C" function void i_struct_2_state_1 (input struct_2_state_1 i); import "DPI-C" function void i_struct_2_state_32 (input struct_2_state_32 i); import "DPI-C" function void i_struct_2_state_33 (input struct_2_state_33 i); import "DPI-C" function void i_struct_2_state_64 (input struct_2_state_64 i); import "DPI-C" function void i_struct_2_state_65 (input struct_2_state_65 i); import "DPI-C" function void i_struct_2_state_128 (input struct_2_state_128 i); // 2-state packed unions import "DPI-C" function void i_union_2_state_1 (input union_2_state_1 i); import "DPI-C" function void i_union_2_state_32 (input union_2_state_32 i); import "DPI-C" function void i_union_2_state_33 (input union_2_state_33 i); import "DPI-C" function void i_union_2_state_64 (input union_2_state_64 i); import "DPI-C" function void i_union_2_state_65 (input union_2_state_65 i); import "DPI-C" function void i_union_2_state_128(input union_2_state_128 i); // 4-state packed arrays import "DPI-C" function void i_array_4_state_1 (input logic [ 0:0] i); import "DPI-C" function void i_array_4_state_32 (input logic [ 31:0] i); import "DPI-C" function void i_array_4_state_33 (input logic [ 32:0] i); import "DPI-C" function void i_array_4_state_64 (input logic [ 63:0] i); import "DPI-C" function void i_array_4_state_65 (input logic [ 64:0] i); import "DPI-C" function void i_array_4_state_128(input logic [127:0] i); // 4-state packed structures import "DPI-C" function void i_struct_4_state_1 (input struct_4_state_1 i); import "DPI-C" function void i_struct_4_state_32 (input struct_4_state_32 i); import "DPI-C" function void i_struct_4_state_33 (input struct_4_state_33 i); import "DPI-C" function void i_struct_4_state_64 (input struct_4_state_64 i); import "DPI-C" function void i_struct_4_state_65 (input struct_4_state_65 i); import "DPI-C" function void i_struct_4_state_128 (input struct_4_state_128 i); // 4-state packed unions import "DPI-C" function void i_union_4_state_1 (input union_4_state_1 i); import "DPI-C" function void i_union_4_state_32 (input union_4_state_32 i); import "DPI-C" function void i_union_4_state_33 (input union_4_state_33 i); import "DPI-C" function void i_union_4_state_64 (input union_4_state_64 i); import "DPI-C" function void i_union_4_state_65 (input union_4_state_65 i); import "DPI-C" function void i_union_4_state_128(input union_4_state_128 i); //====================================================================== // Exports //====================================================================== // Basic types as per IEEE 1800-2023 35.5.6 export "DPI-C" function e_byte; export "DPI-C" function e_byte_unsigned; export "DPI-C" function e_shortint; export "DPI-C" function e_shortint_unsigned; export "DPI-C" function e_int; export "DPI-C" function e_int_unsigned; export "DPI-C" function e_longint; export "DPI-C" function e_longint_unsigned; `ifndef NO_TIME export "DPI-C" function e_time; `endif `ifndef NO_INTEGER export "DPI-C" function e_integer; `endif export "DPI-C" function e_real; `ifndef NO_SHORTREAL export "DPI-C" function e_shortreal; `endif export "DPI-C" function e_chandle; export "DPI-C" function e_string; export "DPI-C" function e_bit; export "DPI-C" function e_logic; // Basic types via typedef export "DPI-C" function e_byte_t; export "DPI-C" function e_byte_unsigned_t; export "DPI-C" function e_shortint_t; export "DPI-C" function e_shortint_unsigned_t; export "DPI-C" function e_int_t; export "DPI-C" function e_int_unsigned_t; export "DPI-C" function e_longint_t; export "DPI-C" function e_longint_unsigned_t; `ifndef NO_TIME export "DPI-C" function e_time_t; `endif `ifndef NO_INTEGER export "DPI-C" function e_integer_t; `endif export "DPI-C" function e_real_t; `ifndef NO_SHORTREAL export "DPI-C" function e_shortreal_t; `endif export "DPI-C" function e_chandle_t; export "DPI-C" function e_string_t; export "DPI-C" function e_bit_t; export "DPI-C" function e_logic_t; // 2-state packed arrays export "DPI-C" function e_array_2_state_1; export "DPI-C" function e_array_2_state_32; export "DPI-C" function e_array_2_state_33; export "DPI-C" function e_array_2_state_64; export "DPI-C" function e_array_2_state_65; export "DPI-C" function e_array_2_state_128; // 2-state packed structures export "DPI-C" function e_struct_2_state_1; export "DPI-C" function e_struct_2_state_32; export "DPI-C" function e_struct_2_state_33; export "DPI-C" function e_struct_2_state_64; export "DPI-C" function e_struct_2_state_65; export "DPI-C" function e_struct_2_state_128; // 2-state packed unions export "DPI-C" function e_union_2_state_1; export "DPI-C" function e_union_2_state_32; export "DPI-C" function e_union_2_state_33; export "DPI-C" function e_union_2_state_64; export "DPI-C" function e_union_2_state_65; export "DPI-C" function e_union_2_state_128; // 4-state packed arrays export "DPI-C" function e_array_4_state_1; export "DPI-C" function e_array_4_state_32; export "DPI-C" function e_array_4_state_33; export "DPI-C" function e_array_4_state_64; export "DPI-C" function e_array_4_state_65; export "DPI-C" function e_array_4_state_128; // 4-state packed structures export "DPI-C" function e_struct_4_state_1; export "DPI-C" function e_struct_4_state_32; export "DPI-C" function e_struct_4_state_33; export "DPI-C" function e_struct_4_state_64; export "DPI-C" function e_struct_4_state_65; export "DPI-C" function e_struct_4_state_128; // 4-state packed unions export "DPI-C" function e_union_4_state_1; export "DPI-C" function e_union_4_state_32; export "DPI-C" function e_union_4_state_33; export "DPI-C" function e_union_4_state_64; export "DPI-C" function e_union_4_state_65; export "DPI-C" function e_union_4_state_128; //====================================================================== // Definitions of exported functions //====================================================================== // Basic types as per IEEE 1800-2023 35.5.6 byte n_byte = 0; function void e_byte(input byte i); if (i !== 8'd10 + n_byte) $stop; n_byte++; endfunction byte n_byte_unsigned = 0; function void e_byte_unsigned(input byte unsigned i); if (i !== 8'd20 + n_byte_unsigned) $stop; n_byte_unsigned++; endfunction shortint n_shortint = 0; function void e_shortint(input shortint i); if (i !== 16'd30 + n_shortint) $stop; n_shortint++; endfunction shortint n_shortint_unsigned = 0; function void e_shortint_unsigned(input shortint unsigned i); if (i !== 16'd40 + n_shortint_unsigned) $stop; n_shortint_unsigned++; endfunction int n_int = 0; function void e_int(input int i); if (i !== 32'd50 + n_int) $stop; n_int++; endfunction int n_int_unsigned = 0; function void e_int_unsigned(input int unsigned i); if (i !== 32'd60 + n_int_unsigned) $stop; n_int_unsigned++; endfunction longint n_longint = 0; function void e_longint(input longint i); if (i !== 64'd70 + n_longint) $stop; n_longint++; endfunction longint n_longint_unsigned = 0; function void e_longint_unsigned(input longint unsigned i); if (i !== 64'd80 + n_longint_unsigned) $stop; n_longint_unsigned++; endfunction `ifndef NO_TIME longint n_time = 0; function void e_time(input time i); if (i !== 64'd90 + n_time) $stop; n_time++; endfunction `endif `ifndef NO_INTEGER int n_integer = 0; function void e_integer(input integer i); if (i !== 32'd100 + n_integer) $stop; n_integer++; endfunction `endif int n_real = 0; function void e_real(input real i); if (i != real'(2*n_real + 1) / 2.0) $stop; n_real++; endfunction `ifndef NO_SHORTREAL int n_shortreal = 0; function void e_shortreal(input shortreal i); if (i != shortreal'(4*n_shortreal + 1)/ 4.0) $stop; n_shortreal++; endfunction `endif int n_chandle = 0; function void e_chandle(input chandle i); $display("e_chandle %1d", n_chandle); if (!n_chandle[0]) begin if (i !== `NULL) $stop; end else begin if (i === `NULL) $stop; end n_chandle++; endfunction int n_string = 0; function void e_string(input string i); $display("e_string %1d", n_string); if (!n_string[0]) begin if (i != "Hello") $stop; end else begin if (i != "World") $stop; end n_string++; endfunction int n_bit = 0; function void e_bit(input bit i); $display("e_bit %1d", n_bit); if (i !== n_bit[0]) $stop; n_bit++; endfunction int n_logic = 0; function void e_logic(input logic i); $display("e_logic %1d", n_logic); if (i !== ~n_logic[0]) $stop; n_logic++; endfunction // Basic types via typedefs byte_t n_byte_t = 0; function void e_byte_t(input byte_t i); if (i !== 8'd10 + n_byte_t) $stop; n_byte_t += 2; endfunction byte n_byte_unsigned_t = 0; function void e_byte_unsigned_t(input byte_unsigned_t i); if (i !== 8'd20 + n_byte_unsigned_t) $stop; n_byte_unsigned_t += 2; endfunction shortint_t n_shortint_t = 0; function void e_shortint_t(input shortint_t i); if (i !== 16'd30 + n_shortint_t) $stop; n_shortint_t += 2; endfunction shortint n_shortint_unsigned_t = 0; function void e_shortint_unsigned_t(input shortint_unsigned_t i); if (i !== 16'd40 + n_shortint_unsigned_t) $stop; n_shortint_unsigned_t += 2; endfunction int_t n_int_t = 0; function void e_int_t(input int_t i); if (i !== 32'd50 + n_int_t) $stop; n_int_t += 2; endfunction int n_int_unsigned_t = 0; function void e_int_unsigned_t(input int_unsigned_t i); if (i !== 32'd60 + n_int_unsigned_t) $stop; n_int_unsigned_t += 2; endfunction longint_t n_longint_t = 0; function void e_longint_t(input longint_t i); if (i !== 64'd70 + n_longint_t) $stop; n_longint_t += 2; endfunction longint n_longint_unsigned_t = 0; function void e_longint_unsigned_t(input longint_unsigned_t i); if (i !== 64'd80 + n_longint_unsigned_t) $stop; n_longint_unsigned_t += 2; endfunction `ifndef NO_TIME longint n_time_t = 0; function void e_time_t(input time_t i); if (i !== 64'd90 + n_time_t) $stop; n_time_t += 2; endfunction `endif `ifndef NO_INTEGER int n_integer_t = 0; function void e_integer_t(input integer_t i); if (i !== 32'd100 + n_integer_t) $stop; n_integer_t += 2; endfunction `endif int n_real_t = 0; function void e_real_t(input real_t i); if (i != real'(2*n_real_t + 1) / 2.0) $stop; n_real_t += 2; endfunction `ifndef NO_SHORTREAL int n_shortreal_t = 0; function void e_shortreal_t(input shortreal_t i); if (i != shortreal'(4*n_shortreal_t + 1)/ 4.0) $stop; n_shortreal_t += 2; endfunction `endif int n_chandle_t = 0; function void e_chandle_t(input chandle_t i); $display("e_chandle_t %1d", n_chandle_t); if (!n_chandle_t[0]) begin if (i === `NULL) $stop; end else begin if (i !== `NULL) $stop; end n_chandle_t++; endfunction int n_string_t = 0; function void e_string_t(input string_t i); $display("e_string_t %1d", n_string_t); if (!n_string_t[0]) begin if (i != "World") $stop; end else begin if (i != "Hello") $stop; end n_string_t++; endfunction int n_bit_t = 0; function void e_bit_t(input bit_t i); $display("e_bit_t %1d", n_bit_t); if (i !== n_bit_t[0]) $stop; n_bit_t++; endfunction int n_logic_t = 0; function void e_logic_t(input logic_t i); $display("e_logic_t %1d", n_logic_t); if (i !== ~n_logic_t[0]) $stop; n_logic_t++; endfunction // 2-state packed arrays int n_array_2_state_1 = 0; function void e_array_2_state_1(input bit [ 0:0] i); $display("e_array_2_state_1 %1d", n_array_2_state_1); if (i !== n_array_2_state_1[0]) $stop; n_array_2_state_1++; endfunction int n_array_2_state_32 = 0; function void e_array_2_state_32(input bit [31:0] i); $display("e_array_2_state_32 %1d", n_array_2_state_32); if (i !== ~32'd0 >> n_array_2_state_32) $stop; n_array_2_state_32++; endfunction int n_array_2_state_33 = 0; function void e_array_2_state_33(input bit [32:0] i); $display("e_array_2_state_33 %1d", n_array_2_state_33); if (i !== ~33'd0 >> n_array_2_state_33) $stop; n_array_2_state_33++; endfunction int n_array_2_state_64 = 0; function void e_array_2_state_64(input bit [63:0] i); $display("e_array_2_state_64 %1d", n_array_2_state_64); if (i !== ~64'd0 >> n_array_2_state_64) $stop; n_array_2_state_64++; endfunction int n_array_2_state_65 = 0; function void e_array_2_state_65(input bit [64:0] i); $display("e_array_2_state_65 %1d", n_array_2_state_65); if (i !== ~65'd0 >> n_array_2_state_65) $stop; n_array_2_state_65++; endfunction int n_array_2_state_128 = 0; function void e_array_2_state_128(input bit [127:0] i); $display("e_array_2_state_128 %1d", n_array_2_state_128); if (i !== ~128'd0 >> n_array_2_state_128) $stop; n_array_2_state_128++; endfunction // 2-state packed structures int n_struct_2_state_1 = 0; function void e_struct_2_state_1(input struct_2_state_1 i); $display("e_struct_2_state_1 %1d", n_struct_2_state_1); if (i !== n_struct_2_state_1[0]) $stop; n_struct_2_state_1++; endfunction int n_struct_2_state_32 = 0; function void e_struct_2_state_32(input struct_2_state_32 i); $display("e_struct_2_state_32 %1d", n_struct_2_state_32); if (i !== ~32'd0 >> n_struct_2_state_32) $stop; n_struct_2_state_32++; endfunction int n_struct_2_state_33 = 0; function void e_struct_2_state_33(input struct_2_state_33 i); $display("e_struct_2_state_33 %1d", n_struct_2_state_33); if (i !== ~33'd0 >> n_struct_2_state_33) $stop; n_struct_2_state_33++; endfunction int n_struct_2_state_64 = 0; function void e_struct_2_state_64(input struct_2_state_64 i); $display("e_struct_2_state_64 %1d", n_struct_2_state_64); if (i !== ~64'd0 >> n_struct_2_state_64) $stop; n_struct_2_state_64++; endfunction int n_struct_2_state_65 = 0; function void e_struct_2_state_65(input struct_2_state_65 i); $display("e_struct_2_state_65 %1d", n_struct_2_state_65); if (i !== ~65'd0 >> n_struct_2_state_65) $stop; n_struct_2_state_65++; endfunction int n_struct_2_state_128 = 0; function void e_struct_2_state_128(input struct_2_state_128 i); $display("e_struct_2_state_128 %1d", n_struct_2_state_128); if (i !== ~128'd0 >> n_struct_2_state_128) $stop; n_struct_2_state_128++; endfunction // 2-state packed unions int n_union_2_state_1 = 0; function void e_union_2_state_1(input union_2_state_1 i); $display("e_union_2_state_1 %1d", n_union_2_state_1); if (i !== n_union_2_state_1[0]) $stop; n_union_2_state_1++; endfunction int n_union_2_state_32 = 0; function void e_union_2_state_32(input union_2_state_32 i); $display("e_union_2_state_32 %1d", n_union_2_state_32); if (i !== ~32'd0 >> n_union_2_state_32) $stop; n_union_2_state_32++; endfunction int n_union_2_state_33 = 0; function void e_union_2_state_33(input union_2_state_33 i); $display("e_union_2_state_33 %1d", n_union_2_state_33); if (i !== ~33'd0 >> n_union_2_state_33) $stop; n_union_2_state_33++; endfunction int n_union_2_state_64 = 0; function void e_union_2_state_64(input union_2_state_64 i); $display("e_union_2_state_64 %1d", n_union_2_state_64); if (i !== ~64'd0 >> n_union_2_state_64) $stop; n_union_2_state_64++; endfunction int n_union_2_state_65 = 0; function void e_union_2_state_65(input union_2_state_65 i); $display("e_union_2_state_65 %1d", n_union_2_state_65); if (i !== ~65'd0 >> n_union_2_state_65) $stop; n_union_2_state_65++; endfunction int n_union_2_state_128 = 0; function void e_union_2_state_128(input union_2_state_128 i); $display("e_union_2_state_128 %1d", n_union_2_state_128); if (i !== ~128'd0 >> n_union_2_state_128) $stop; n_union_2_state_128++; endfunction // 4-state packed arrays int n_array_4_state_1 = 0; function void e_array_4_state_1(input logic [ 0:0] i); $display("e_array_4_state_1 %1d", n_array_4_state_1); if (i !== n_array_4_state_1[0]) $stop; n_array_4_state_1++; endfunction int n_array_4_state_32 = 0; function void e_array_4_state_32(input logic [31:0] i); $display("e_array_4_state_32 %1d", n_array_4_state_32); if (i !== ~32'd0 >> n_array_4_state_32) $stop; n_array_4_state_32++; endfunction int n_array_4_state_33 = 0; function void e_array_4_state_33(input logic [32:0] i); $display("e_array_4_state_33 %1d", n_array_4_state_33); if (i !== ~33'd0 >> n_array_4_state_33) $stop; n_array_4_state_33++; endfunction int n_array_4_state_64 = 0; function void e_array_4_state_64(input logic [63:0] i); $display("e_array_4_state_64 %1d", n_array_4_state_64); if (i !== ~64'd0 >> n_array_4_state_64) $stop; n_array_4_state_64++; endfunction int n_array_4_state_65 = 0; function void e_array_4_state_65(input logic [64:0] i); $display("e_array_4_state_65 %1d", n_array_4_state_65); if (i !== ~65'd0 >> n_array_4_state_65) $stop; n_array_4_state_65++; endfunction int n_array_4_state_128 = 0; function void e_array_4_state_128(input logic [127:0] i); $display("e_array_4_state_128 %1d", n_array_4_state_128); if (i !== ~128'd0 >> n_array_4_state_128) $stop; n_array_4_state_128++; endfunction // 4-state packed structures int n_struct_4_state_1 = 0; function void e_struct_4_state_1(input struct_4_state_1 i); $display("e_struct_4_state_1 %1d", n_struct_4_state_1); if (i !== n_struct_4_state_1[0]) $stop; n_struct_4_state_1++; endfunction int n_struct_4_state_32 = 0; function void e_struct_4_state_32(input struct_4_state_32 i); $display("e_struct_4_state_32 %1d", n_struct_4_state_32); if (i !== ~32'd0 >> n_struct_4_state_32) $stop; n_struct_4_state_32++; endfunction int n_struct_4_state_33 = 0; function void e_struct_4_state_33(input struct_4_state_33 i); $display("e_struct_4_state_33 %1d", n_struct_4_state_33); if (i !== ~33'd0 >> n_struct_4_state_33) $stop; n_struct_4_state_33++; endfunction int n_struct_4_state_64 = 0; function void e_struct_4_state_64(input struct_4_state_64 i); $display("e_struct_4_state_64 %1d", n_struct_4_state_64); if (i !== ~64'd0 >> n_struct_4_state_64) $stop; n_struct_4_state_64++; endfunction int n_struct_4_state_65 = 0; function void e_struct_4_state_65(input struct_4_state_65 i); $display("e_struct_4_state_65 %1d", n_struct_4_state_65); if (i !== ~65'd0 >> n_struct_4_state_65) $stop; n_struct_4_state_65++; endfunction int n_struct_4_state_128 = 0; function void e_struct_4_state_128(input struct_4_state_128 i); $display("e_struct_4_state_128 %1d", n_struct_4_state_128); if (i !== ~128'd0 >> n_struct_4_state_128) $stop; n_struct_4_state_128++; endfunction // 4-state packed unions int n_union_4_state_1 = 0; function void e_union_4_state_1(input union_4_state_1 i); $display("e_union_4_state_1 %1d", n_union_4_state_1); if (i !== n_union_4_state_1[0]) $stop; n_union_4_state_1++; endfunction int n_union_4_state_32 = 0; function void e_union_4_state_32(input union_4_state_32 i); $display("e_union_4_state_32 %1d", n_union_4_state_32); if (i !== ~32'd0 >> n_union_4_state_32) $stop; n_union_4_state_32++; endfunction int n_union_4_state_33 = 0; function void e_union_4_state_33(input union_4_state_33 i); $display("e_union_4_state_33 %1d", n_union_4_state_33); if (i !== ~33'd0 >> n_union_4_state_33) $stop; n_union_4_state_33++; endfunction int n_union_4_state_64 = 0; function void e_union_4_state_64(input union_4_state_64 i); $display("e_union_4_state_64 %1d", n_union_4_state_64); if (i !== ~64'd0 >> n_union_4_state_64) $stop; n_union_4_state_64++; endfunction int n_union_4_state_65 = 0; function void e_union_4_state_65(input union_4_state_65 i); $display("e_union_4_state_65 %1d", n_union_4_state_65); if (i !== ~65'd0 >> n_union_4_state_65) $stop; n_union_4_state_65++; endfunction int n_union_4_state_128 = 0; function void e_union_4_state_128(input union_4_state_128 i); $display("e_union_4_state_128 %1d", n_union_4_state_128); if (i !== ~128'd0 >> n_union_4_state_128) $stop; n_union_4_state_128++; endfunction //====================================================================== // Invoke all functions 3 times (they have side effects) //====================================================================== import "DPI-C" context function void check_exports(); initial begin for (int i = 0 ; i < 3; i++) begin // Check the imports // Basic types as per IEEE 1800-2023 35.5.6 i_byte( 8'd10 - 8'(i)); i_byte_unsigned( 8'd20 - 8'(i)); i_shortint( 16'd30 - 16'(i)); i_shortint_unsigned( 16'd40 - 16'(i)); i_int( 32'd50 - 32'(i)); i_int_unsigned( 32'd60 - 32'(i)); i_longint( 64'd70 - 64'(i)); i_longint_unsigned( 64'd80 - 64'(i)); `ifndef NO_TIME i_time( 64'd90 - 64'(i)); `endif `ifndef NO_INTEGER i_integer( 32'd100- 32'(i)); `endif i_real( -1.0*i - 0.50); `ifndef NO_SHORTREAL i_shortreal( -1.0*i - 0.25); `endif if (~i[0]) begin i_chandle(`NULL); i_string("World"); end else begin i_chandle(`NULL); i_string("Hello"); end i_bit(~i[0]); i_logic(i[0]); // Basic types via typedefs i_byte_t( 8'd10 - 8'(2*i)); i_byte_unsigned_t( 8'd20 - 8'(2*i)); i_shortint_t( 16'd30 - 16'(2*i)); i_shortint_unsigned_t( 16'd40 - 16'(2*i)); i_int_t( 32'd50 - 32'(2*i)); i_int_unsigned_t( 32'd60 - 32'(2*i)); i_longint_t( 64'd70 - 64'(2*i)); i_longint_unsigned_t( 64'd80 - 64'(2*i)); `ifndef NO_TIME i_time_t( 64'd90 - 64'(2*i)); `endif `ifndef NO_INTEGER i_integer_t( 32'd100- 32'(2*i)); `endif i_real_t( -1.0*(2*i) - 0.50); `ifndef NO_SHORTREAL i_shortreal_t( -1.0*(2*i) - 0.25); `endif if (~i[0]) begin i_chandle_t(`NULL); i_string_t("World"); end else begin i_chandle_t(`NULL); i_string_t("Hello"); end i_bit_t(~i[0]); i_logic_t(i[0]); // 2-state packed arrays i_array_2_state_1(~i[0]); i_array_2_state_32(~32'd0 << i); i_array_2_state_33(~33'd0 << i); i_array_2_state_64(~64'd0 << i); i_array_2_state_65(~65'd0 << i); i_array_2_state_128(~128'd0 << i); // 2-state packed structures i_struct_2_state_1(~i[0]); i_struct_2_state_32(~32'd0 << i); i_struct_2_state_33(~33'd0 << i); i_struct_2_state_64(~64'd0 << i); i_struct_2_state_65(~65'd0 << i); i_struct_2_state_128(~128'd0 << i); // 2-state packed unions i_union_2_state_1(~i[0]); i_union_2_state_32(~32'd0 << i); i_union_2_state_33(~33'd0 << i); i_union_2_state_64(~64'd0 << i); i_union_2_state_65(~65'd0 << i); i_union_2_state_128(~128'd0 << i); // 4-state packed arrays i_array_4_state_1(~i[0]); i_array_4_state_32(~32'd0 << i); i_array_4_state_33(~33'd0 << i); i_array_4_state_64(~64'd0 << i); i_array_4_state_65(~65'd0 << i); i_array_4_state_128(~128'd0 << i); // 4-state packed structures i_struct_4_state_1(~i[0]); i_struct_4_state_32(~32'd0 << i); i_struct_4_state_33(~33'd0 << i); i_struct_4_state_64(~64'd0 << i); i_struct_4_state_65(~65'd0 << i); i_struct_4_state_128(~128'd0 << i); // 4-state packed unions i_union_4_state_1(~i[0]); i_union_4_state_32(~32'd0 << i); i_union_4_state_33(~33'd0 << i); i_union_4_state_64(~64'd0 << i); i_union_4_state_65(~65'd0 << i); i_union_4_state_128(~128'd0 << i); // Check the exports check_exports(); end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_unpacked_concat.v0000644000542200017500000000506715101701376022731 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2023 by Yutetsu TAKATSUKASA. // SPDX-License-Identifier: CC0-1.0 module t; typedef int ai3_t[1:3]; ai3_t a3; int a9[1:9]; logic [2:0] s0; logic [2:0] s1[1:3]; logic [2:0] s1b[3:1]; logic [2:0] s3[2:8]; logic [2:0] s3b[8:2]; initial begin s0 = 3'd1; s1[1] = 3'd2; s1[2] = 3'd3; s1[3] = 3'd4; s1b[1] = 3'd5; s1b[2] = 3'd6; s1b[3] = 3'd7; a3 = '{1, 2, 3}; a9 = {a3, 4, 5, a3, 6}; if (a9[1] != 1) $stop; if (a9[2] != 2) $stop; if (a9[3] != 3) $stop; if (a9[4] != 4) $stop; if (a9[5] != 5) $stop; if (a9[6] != 1) $stop; if (a9[7] != 2) $stop; if (a9[8] != 3) $stop; if (a9[9] != 6) $stop; s3 = {s0, s1, s1b}; if (s3[2] != s0) $stop; if (s3[3] != s1[1]) $stop; if (s3[4] != s1[2]) $stop; if (s3[5] != s1[3]) $stop; if (s3[6] != s1b[3]) $stop; if (s3[7] != s1b[2]) $stop; if (s3[8] != s1b[1]) $stop; s3[2:8] = {s0, s1[1:2], s1[3], s1b[3], s1b[2:1]}; if (s3[2] != s0) $stop; if (s3[3] != s1[1]) $stop; if (s3[4] != s1[2]) $stop; if (s3[5] != s1[3]) $stop; if (s3[6] != s1b[3]) $stop; if (s3[7] != s1b[2]) $stop; if (s3[8] != s1b[1]) $stop; s3 = {s0, s1[1], s1[2:3], s1b[3:2], s1b[1]}; if (s3[2] != s0) $stop; if (s3[3] != s1[1]) $stop; if (s3[4] != s1[2]) $stop; if (s3[5] != s1[3]) $stop; if (s3[6] != s1b[3]) $stop; if (s3[7] != s1b[2]) $stop; if (s3[8] != s1b[1]) $stop; s3b = {s0, s1, s1b}; if (s3b[8] != s0) $stop; if (s3b[7] != s1[1]) $stop; if (s3b[6] != s1[2]) $stop; if (s3b[5] != s1[3]) $stop; if (s3b[4] != s1b[3]) $stop; if (s3b[3] != s1b[2]) $stop; if (s3b[2] != s1b[1]) $stop; s3b[8:2] = {s0, s1[1:2], s1[3], s1b[3], s1b[2:1]}; if (s3b[8] != s0) $stop; if (s3b[7] != s1[1]) $stop; if (s3b[6] != s1[2]) $stop; if (s3b[5] != s1[3]) $stop; if (s3b[4] != s1b[3]) $stop; if (s3b[3] != s1b[2]) $stop; if (s3b[2] != s1b[1]) $stop; s3b = {s0, s1[1], s1[2:3], s1b[3:2], s1b[1]}; if (s3b[8] != s0) $stop; if (s3b[7] != s1[1]) $stop; if (s3b[6] != s1[2]) $stop; if (s3b[5] != s1[3]) $stop; if (s3b[4] != s1b[3]) $stop; if (s3b[3] != s1b[2]) $stop; if (s3b[2] != s1b[1]) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_detectarray_3.v0000644000542200017500000000140015101701376022324 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Simple test of unoptflat // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014 by Jie Xu. // SPDX-License-Identifier: CC0-1.0 localparam ID_MSB = 1; module t (/*AUTOARG*/ // Inputs clk, res ); input clk; output [8:0][8:0] res; logic a = 1'b1; logic [8:0] b [8:0]; // where the error is reported logic [8:0][8:0] c; // where the error is reported // following just to make c as circular assign c[0] = c[0] | a << 1; assign b[0] = b[0] | a << 2; assign res[0] = c[0]; assign res[1] = b[0]; always @(posedge clk or negedge clk) begin if (res != 0) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_nettype.out0000644000542200017500000000122015101701376021625 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_nettype.v:25:4: Unsupported: nettype with 25 | nettype real real1_n with Pkg::resolver; | ^~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_nettype.v:29:4: Unsupported: nettype with 29 | nettype real real2_n with local_resolver; | ^~~~~~~ %Error-UNSUPPORTED: t/t_nettype.v:34:4: Unsupported: nettype 34 | nettype real2_n real3_n; | ^~~~~~~ %Error-UNSUPPORTED: t/t_nettype.v:38:4: Unsupported: nettype with 38 | nettype Pkg::real_t real4_n with Pkg::resolver; | ^~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_gantt_io.py0000755000542200017500000000145415101701376021576 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') test.run(cmd=[ "cd " + test.obj_dir + " && " + os.environ["VERILATOR_ROOT"] + "/bin/verilator_gantt" + " " + test.t_dir + "/" + test.name + ".dat > gantt.log" ], check_finished=False) test.files_identical(test.obj_dir + "/gantt.log", test.golden_filename) test.vcd_identical(test.obj_dir + "/profile_exec.vcd", test.t_dir + "/" + test.name + ".vcd.out") test.passes() verilator-5.042/test_regress/t/t_type_compare.py0000755000542200017500000000073415101701376022461 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_nansi.py0000755000542200017500000000073415101701376023122 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_vpi_put_value_array.cpp0000644000542200017500000007134115101701376024203 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2024 by Diego Roux. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #ifndef IS_VPI #include "verilated.h" #include "verilated_vpi.h" #include "Vt_vpi_put_value_array.h" #endif extern "C" { #include } // These require the above. Comment prevents clang-format moving them #include "TestSimulator.h" #include "TestVpi.h" #include //====================================================================== int test_vpiRawFourStateVal(char* name, PLI_BYTE8* test_data, int index, const unsigned num, const unsigned size, const unsigned elem_size) { #ifdef TEST_VERBOSE printf("%%\n%s: name=%s index=%u num=%u size=%u elem_size=%u\n\n", __func__, name, index, num, size, elem_size); #endif // prepare index and test data arrays int index_arr[1] = {index}; std::vector test_data_four_state; test_data_four_state.resize(size * elem_size * 2); for (unsigned i = 0; i < size; i++) { for (unsigned j = 0; j < elem_size; j++) { test_data_four_state[(i * 2 * elem_size) + j] = test_data[(i * elem_size) + j]; } for (unsigned j = 0; j < elem_size; j++) { test_data_four_state[(((i * 2) + 1) * elem_size) + j] = -1; // bval should be ignored } } // get array handle TestVpiHandle arrayhandle = vpi_handle_by_name(name, NULL); CHECK_RESULT_NZ(arrayhandle); // test raw fourstate s_vpi_arrayvalue arrayvalue; arrayvalue.format = vpiRawFourStateVal; arrayvalue.flags = 0; arrayvalue.value.rawvals = test_data_four_state.data(); vpi_put_value_array(arrayhandle, &arrayvalue, index_arr, num); CHECK_RESULT_NZ(!vpi_chk_error(0)); // get value to nu arrayvalue.value.rawvals = 0; vpi_get_value_array(arrayhandle, &arrayvalue, index_arr, size); CHECK_RESULT_NZ(!vpi_chk_error(0)); #ifdef TEST_VERBOSE for (unsigned i = 0; i < (2 * size * elem_size); i++) { printf("arr[%u]=%x test[%u]=%x\n", i, arrayvalue.value.rawvals[i] & 0xFF, i, test_data_four_state[i] & 0xFF); } #endif // compare to test data for (unsigned i = 0; i < num; i++) { const unsigned offset = (index + i) % size; for (unsigned j = 0; j < elem_size; j++) { #ifdef TEST_VERBOSE printf("arr[%u] == test[%u]\n", (i * 2 * elem_size) + j, (i * elem_size) + j); #endif CHECK_RESULT_HEX(arrayvalue.value.rawvals[(i * 2 * elem_size) + j], test_data[(i * elem_size) + j]); } for (unsigned j = 0; j < elem_size; j++) { CHECK_RESULT_HEX(arrayvalue.value.rawvals[(((i * 2) + 1) * elem_size) + j], 0); } } return 0; } int test_vpiRawTwoStateVal(char* name, PLI_BYTE8* test_data, int index, const unsigned num, const unsigned size, const unsigned elem_size) { #ifdef TEST_VERBOSE printf("%%\n%s: name=%s index=%u num=%u size=%u elem_size=%u\n\n", __func__, name, index, num, size, elem_size); #endif // prepare index int index_arr[1] = {index}; // get array handle TestVpiHandle arrayhandle = vpi_handle_by_name(name, NULL); CHECK_RESULT_NZ(arrayhandle); // test raw fourstate s_vpi_arrayvalue arrayvalue; arrayvalue.format = vpiRawTwoStateVal; arrayvalue.flags = 0; arrayvalue.value.rawvals = test_data; vpi_put_value_array(arrayhandle, &arrayvalue, index_arr, num); CHECK_RESULT_NZ(!vpi_chk_error(0)); // get value to check arrayvalue.value.rawvals = 0; vpi_get_value_array(arrayhandle, &arrayvalue, index_arr, size); CHECK_RESULT_NZ(!vpi_chk_error(0)); #ifdef TEST_VERBOSE for (unsigned i = 0; i < (size * elem_size); i++) { printf("arr[%u]=%x test[%u]=%x\n", i, arrayvalue.value.rawvals[i] & 0xFF, i, test_data[i] & 0xFF); } #endif // compare to test data for (unsigned i = 0; i < num; i++) { const unsigned offset = (index + i) % size; for (unsigned j = 0; j < elem_size; j++) { #ifdef TEST_VERBOSE printf("arr[%u] == test[%u]\n", (i * elem_size) + j, (i * elem_size) + j); #endif CHECK_RESULT_HEX(arrayvalue.value.rawvals[(i * elem_size) + j], test_data[(i * elem_size) + j]); } } return 0; } int test_vpiVectorVal(char* name, PLI_BYTE8* test_data, int index, const unsigned num, const unsigned size, const unsigned elem_size) { #ifdef TEST_VERBOSE printf("%%\n%s: name=%s index=%u num=%u size=%u elem_size=%u\n\n", __func__, name, index, num, size, elem_size); #endif // prepare index int index_arr[1] = {index}; const unsigned elem_size_words = (elem_size + 3) / sizeof(PLI_UINT32); const unsigned vec_size = elem_size_words * size; std::vector test_data_vectors; test_data_vectors.resize(vec_size); unsigned test_data_index = 0; for (unsigned i = 0; i < size; i++) { unsigned count = 0; for (unsigned j = 0; j < elem_size_words; j++) { PLI_UINT32& aval = test_data_vectors[(i * elem_size_words) + j].aval; test_data_vectors[(i * elem_size_words) + j].bval = UINT32_MAX; aval = 0; for (unsigned k = 0; k < sizeof(PLI_UINT32); k++) { if (count++ == elem_size) break; aval |= static_cast(test_data[test_data_index++] & 0xFF) << (k * 8); } } } // get array handle TestVpiHandle arrayhandle = vpi_handle_by_name(name, NULL); CHECK_RESULT_NZ(arrayhandle); // test raw fourstate s_vpi_arrayvalue arrayvalue; arrayvalue.format = vpiVectorVal; arrayvalue.flags = 0; arrayvalue.value.vectors = test_data_vectors.data(); vpi_put_value_array(arrayhandle, &arrayvalue, index_arr, num); CHECK_RESULT_NZ(!vpi_chk_error(0)); // get value to check arrayvalue.value.vectors = 0; vpi_get_value_array(arrayhandle, &arrayvalue, index_arr, size); CHECK_RESULT_NZ(!vpi_chk_error(0)); #ifdef TEST_VERBOSE for (unsigned i = 0; i < vec_size; i++) { printf("arr[%u]=%x test[%u]=%x\n", i, arrayvalue.value.vectors[i].aval, i, test_data_vectors[i].aval); } #endif // compare to test data for (unsigned i = 0; i < num; i++) { const unsigned offset = (index + i) % size; for (unsigned j = 0; j < elem_size_words; j++) { #ifdef TEST_VERBOSE printf("arr[%u] == test[%u]\n", (i * elem_size_words) + j, (i * elem_size_words) + j); #endif CHECK_RESULT_HEX(arrayvalue.value.vectors[(i * elem_size_words) + j].aval, test_data_vectors[(i * elem_size_words) + j].aval); } for (unsigned j = 0; j < elem_size_words; j++) { CHECK_RESULT_HEX(arrayvalue.value.vectors[(i * elem_size_words) + j].bval, 0); } } return 0; } int test_vpiIntVal(char* name, PLI_BYTE8* test_data, int index, const unsigned num, const unsigned size, const unsigned elem_size) { #ifdef TEST_VERBOSE printf("%%\n%s: name=%s index=%u num=%u size=%u elem_size=%u\n\n", __func__, name, index, num, size, elem_size); #endif // prepare index int index_arr[1] = {index}; std::vector test_data_integers; test_data_integers.resize(size); for (unsigned i = 0; i < size; i++) { PLI_INT32& integer = test_data_integers[i]; integer = 0; for (unsigned j = 0; j < elem_size; j++) { integer |= (static_cast(test_data[(i * elem_size) + j]) & 0xFF) << (j * 8); } } // get array handle TestVpiHandle arrayhandle = vpi_handle_by_name(name, NULL); CHECK_RESULT_NZ(arrayhandle); // test raw fourstate s_vpi_arrayvalue arrayvalue; arrayvalue.format = vpiIntVal; arrayvalue.flags = 0; arrayvalue.value.integers = test_data_integers.data(); vpi_put_value_array(arrayhandle, &arrayvalue, index_arr, num); CHECK_RESULT_NZ(!vpi_chk_error(0)); // get value to check arrayvalue.value.vectors = 0; vpi_get_value_array(arrayhandle, &arrayvalue, index_arr, size); CHECK_RESULT_NZ(!vpi_chk_error(0)); #ifdef TEST_VERBOSE for (unsigned i = 0; i < size; i++) { printf("arr[%u]=%x test[%u]=%x\n", i, arrayvalue.value.integers[i], i, test_data_integers[i]); } #endif // compare to test data for (unsigned i = 0; i < num; i++) { #ifdef TEST_VERBOSE printf("arr[%u] == test[%u]\n", i, i); #endif CHECK_RESULT_HEX(arrayvalue.value.integers[i], test_data_integers[i]); } return 0; } int test_vpiShortIntVal(char* name, PLI_BYTE8* test_data, int index, const unsigned num, const unsigned size, const unsigned elem_size) { #ifdef TEST_VERBOSE printf("%%\n%s: name=%s index=%u num=%u size=%u elem_size=%u\n\n", __func__, name, index, num, size, elem_size); #endif // prepare index int index_arr[1] = {index}; std::vector test_data_shortints; test_data_shortints.resize(size); for (unsigned i = 0; i < size; i++) { if (elem_size == 2) { test_data_shortints[i] = test_data[i * 2] & 0xFF; test_data_shortints[i] |= test_data[(i * 2) + 1] << 8; } else { test_data_shortints[i] = test_data[i] & 0xFF; } } // get array handle TestVpiHandle arrayhandle = vpi_handle_by_name(name, NULL); CHECK_RESULT_NZ(arrayhandle); // test raw fourstate s_vpi_arrayvalue arrayvalue; arrayvalue.format = vpiShortIntVal; arrayvalue.flags = 0; arrayvalue.value.shortints = test_data_shortints.data(); vpi_put_value_array(arrayhandle, &arrayvalue, index_arr, num); CHECK_RESULT_NZ(!vpi_chk_error(0)); // get value to check arrayvalue.value.vectors = 0; vpi_get_value_array(arrayhandle, &arrayvalue, index_arr, size); CHECK_RESULT_NZ(!vpi_chk_error(0)); #ifdef TEST_VERBOSE for (unsigned i = 0; i < size; i++) { printf("arr[%u]=%x test[%u]=%x\n", i, arrayvalue.value.shortints[i], i, test_data_shortints[i]); } #endif // compare to test data for (unsigned i = 0; i < num; i++) { #ifdef TEST_VERBOSE printf("arr[%u] == test[%u]\n", i, i); #endif CHECK_RESULT_HEX(arrayvalue.value.shortints[i], test_data_shortints[i]); } return 0; } int test_vpiLongIntVal(char* name, PLI_BYTE8* test_data, int index, const unsigned num, const unsigned size, const unsigned elem_size) { #ifdef TEST_VERBOSE printf("%%\n%s: name=%s index=%u num=%u size=%u elem_size=%u\n\n", __func__, name, index, num, size, elem_size); #endif // prepare index int index_arr[1] = {index}; std::vector test_data_longints; test_data_longints.resize(size); for (unsigned i = 0; i < size; i++) { PLI_INT64& longint = test_data_longints[i]; longint = 0; for (unsigned j = 0; j < elem_size; j++) { longint |= (static_cast(test_data[(i * elem_size) + j]) & 0xFF) << (j * 8); } } // get array handle TestVpiHandle arrayhandle = vpi_handle_by_name(name, NULL); CHECK_RESULT_NZ(arrayhandle); // test raw fourstate s_vpi_arrayvalue arrayvalue; arrayvalue.format = vpiLongIntVal; arrayvalue.flags = 0; arrayvalue.value.longints = test_data_longints.data(); vpi_put_value_array(arrayhandle, &arrayvalue, index_arr, num); CHECK_RESULT_NZ(!vpi_chk_error(0)); // get value to check arrayvalue.value.vectors = 0; vpi_get_value_array(arrayhandle, &arrayvalue, index_arr, size); CHECK_RESULT_NZ(!vpi_chk_error(0)); // compare to test data for (unsigned i = 0; i < num; i++) { #ifdef TEST_VERBOSE printf("arr[%u] == test[%u]\n", i, i); #endif CHECK_RESULT_HEX(arrayvalue.value.longints[i], test_data_longints[i]); } return 0; } int mon_check_props(void) { // skip test if not verilator (value_array accessors unimplemented in other sims) if (!TestSimulator::is_verilator()) { #ifdef VERILATOR printf("TestSimulator indicating not verilator, but VERILATOR macro is defined\n"); return 1; #endif return 0; } const unsigned NUM_ELEMENTS = 4; PLI_BYTE8 write_bytes[NUM_ELEMENTS] = {static_cast(0xad), static_cast(0xde), static_cast(0xef), static_cast(0xbe)}; PLI_BYTE8 write_shorts[NUM_ELEMENTS * 2] = { static_cast(0xad), static_cast(0xde), static_cast(0xef), static_cast(0xbe), static_cast(0xfe), static_cast(0xca), static_cast(0x0d), static_cast(0xf0)}; PLI_BYTE8 write_words[NUM_ELEMENTS * 4] = { static_cast(0xef), static_cast(0xbe), static_cast(0xad), static_cast(0xde), static_cast(0x0d), static_cast(0xf0), static_cast(0xfe), static_cast(0xca), static_cast(0x03), static_cast(0x02), static_cast(0x01), static_cast(0x00), static_cast(0x07), static_cast(0x06), static_cast(0x05), static_cast(0x04)}; PLI_BYTE8 write_longs[NUM_ELEMENTS * 8] = { static_cast(0x0d), static_cast(0xf0), static_cast(0xfe), static_cast(0xca), static_cast(0xef), static_cast(0xbe), static_cast(0xad), static_cast(0xde), static_cast(0x07), static_cast(0x06), static_cast(0x05), static_cast(0x04), static_cast(0x03), static_cast(0x02), static_cast(0x01), static_cast(0x00), static_cast(0x0F), static_cast(0x0E), static_cast(0x0D), static_cast(0x0C), static_cast(0x0B), static_cast(0x0A), static_cast(0x09), static_cast(0x08), static_cast(0x17), static_cast(0x16), static_cast(0x15), static_cast(0x14), static_cast(0x13), static_cast(0x12), static_cast(0x11), static_cast(0x10)}; PLI_BYTE8 write_customs[NUM_ELEMENTS * 9] = { static_cast(0x0d), static_cast(0xf0), static_cast(0xfe), static_cast(0xca), static_cast(0xef), static_cast(0xbe), static_cast(0xad), static_cast(0xde), static_cast(0x1A), static_cast(0x07), static_cast(0x06), static_cast(0x05), static_cast(0x04), static_cast(0x03), static_cast(0x02), static_cast(0x01), static_cast(0x00), static_cast(0x15), static_cast(0x0F), static_cast(0x0E), static_cast(0x0D), static_cast(0x0C), static_cast(0x0B), static_cast(0x0A), static_cast(0x09), static_cast(0x08), static_cast(0x0A), static_cast(0x17), static_cast(0x16), static_cast(0x15), static_cast(0x14), static_cast(0x13), static_cast(0x12), static_cast(0x11), static_cast(0x10), static_cast(0x05)}; char write_bytes_name[] = "test.write_bytes"; char write_bytes_nonzero_index_name[] = "test.write_bytes_nonzero_index"; char write_bytes_rl_name[] = "test.write_bytes_rl"; char write_shorts_name[] = "test.write_shorts"; char write_words_name[] = "test.write_words"; char write_integers_name[] = "test.write_integers"; char write_longs_name[] = "test.write_longs"; char write_customs_name[] = "test.write_customs"; char write_customs_nonzero_index_rl_name[] = "test.write_customs_nonzero_index_rl"; for (unsigned i = 0; i < NUM_ELEMENTS; i++) { for (unsigned j = 0; j < (NUM_ELEMENTS + 1); j++) { if (test_vpiRawFourStateVal(write_bytes_name, write_bytes, i, j, NUM_ELEMENTS, 1)) return 1; if (test_vpiRawFourStateVal(write_bytes_nonzero_index_name, write_bytes, i + 1, j, NUM_ELEMENTS, 1)) return 1; if (test_vpiRawFourStateVal(write_bytes_rl_name, write_bytes, i, j, NUM_ELEMENTS, 1)) return 1; if (test_vpiRawFourStateVal(write_shorts_name, write_shorts, i, j, NUM_ELEMENTS, 2)) return 1; if (test_vpiRawFourStateVal(write_words_name, write_words, i, j, NUM_ELEMENTS, 4)) return 1; if (test_vpiRawFourStateVal(write_integers_name, write_words, i, j, NUM_ELEMENTS, 4)) return 1; if (test_vpiRawFourStateVal(write_longs_name, write_longs, i, j, NUM_ELEMENTS, 8)) return 1; if (test_vpiRawFourStateVal(write_customs_name, write_customs, i, j, NUM_ELEMENTS, 9)) return 1; if (test_vpiRawFourStateVal(write_customs_nonzero_index_rl_name, write_customs, i + 1, j, NUM_ELEMENTS, 9)) return 1; if (test_vpiRawTwoStateVal(write_bytes_name, write_bytes, i, j, NUM_ELEMENTS, 1)) return 1; if (test_vpiRawTwoStateVal(write_bytes_rl_name, write_bytes, i, j, NUM_ELEMENTS, 1)) return 1; if (test_vpiRawTwoStateVal(write_bytes_nonzero_index_name, write_bytes, i + 1, j, NUM_ELEMENTS, 1)) return 1; if (test_vpiRawTwoStateVal(write_shorts_name, write_shorts, i, j, NUM_ELEMENTS, 2)) return 1; if (test_vpiRawTwoStateVal(write_words_name, write_words, i, j, NUM_ELEMENTS, 4)) return 1; if (test_vpiRawTwoStateVal(write_integers_name, write_words, i, j, NUM_ELEMENTS, 4)) return 1; if (test_vpiRawTwoStateVal(write_longs_name, write_longs, i, j, NUM_ELEMENTS, 8)) return 1; if (test_vpiRawTwoStateVal(write_customs_name, write_customs, i, j, NUM_ELEMENTS, 9)) return 1; if (test_vpiRawTwoStateVal(write_customs_nonzero_index_rl_name, write_customs, i + 1, j, NUM_ELEMENTS, 9)) return 1; if (test_vpiVectorVal(write_bytes_name, write_bytes, i, j, NUM_ELEMENTS, 1)) return 1; if (test_vpiVectorVal(write_bytes_nonzero_index_name, write_bytes, i + 1, j, NUM_ELEMENTS, 1)) return 1; if (test_vpiVectorVal(write_bytes_rl_name, write_bytes, i, j, NUM_ELEMENTS, 1)) return 1; if (test_vpiVectorVal(write_shorts_name, write_shorts, i, j, NUM_ELEMENTS, 2)) return 1; if (test_vpiVectorVal(write_words_name, write_words, i, j, NUM_ELEMENTS, 4)) return 1; if (test_vpiVectorVal(write_integers_name, write_words, i, j, NUM_ELEMENTS, 4)) return 1; if (test_vpiVectorVal(write_longs_name, write_longs, i, j, NUM_ELEMENTS, 8)) return 1; if (test_vpiVectorVal(write_customs_name, write_customs, i, j, NUM_ELEMENTS, 9)) return 1; if (test_vpiVectorVal(write_customs_nonzero_index_rl_name, write_customs, i + 1, j, NUM_ELEMENTS, 9)) return 1; if (test_vpiShortIntVal(write_bytes_name, write_bytes, i, j, NUM_ELEMENTS, 1)) return 1; if (test_vpiShortIntVal(write_bytes_nonzero_index_name, write_bytes, i + 1, j, NUM_ELEMENTS, 1)) return 1; if (test_vpiShortIntVal(write_bytes_rl_name, write_bytes, i, j, NUM_ELEMENTS, 1)) return 1; if (test_vpiShortIntVal(write_shorts_name, write_shorts, i, j, NUM_ELEMENTS, 2)) return 1; if (test_vpiIntVal(write_bytes_name, write_bytes, i, j, NUM_ELEMENTS, 1)) return 1; if (test_vpiIntVal(write_bytes_nonzero_index_name, write_bytes, i + 1, j, NUM_ELEMENTS, 1)) return 1; if (test_vpiIntVal(write_bytes_rl_name, write_bytes, i, j, NUM_ELEMENTS, 1)) return 1; if (test_vpiIntVal(write_words_name, write_words, i, j, NUM_ELEMENTS, 4)) return 1; if (test_vpiIntVal(write_integers_name, write_words, i, j, NUM_ELEMENTS, 4)) return 1; if (test_vpiLongIntVal(write_bytes_name, write_bytes, i, j, NUM_ELEMENTS, 1)) return 1; if (test_vpiLongIntVal(write_bytes_nonzero_index_name, write_bytes, i + 1, j, NUM_ELEMENTS, 1)) return 1; if (test_vpiLongIntVal(write_bytes_rl_name, write_bytes, i, j, NUM_ELEMENTS, 1)) return 1; if (test_vpiLongIntVal(write_shorts_name, write_shorts, i, j, NUM_ELEMENTS, 2)) return 1; if (test_vpiLongIntVal(write_words_name, write_words, i, j, NUM_ELEMENTS, 4)) return 1; if (test_vpiLongIntVal(write_integers_name, write_words, i, j, NUM_ELEMENTS, 4)) return 1; if (test_vpiLongIntVal(write_longs_name, write_longs, i, j, NUM_ELEMENTS, 8)) return 1; } } { // test unsupported format TestVpiHandle object = vpi_handle_by_name((PLI_BYTE8*)"test.write_longs", NULL); CHECK_RESULT_NZ(object); double datap[4] = {0, 0, 0, 0}; s_vpi_arrayvalue arrayvalue; arrayvalue.format = vpiRealVal; arrayvalue.flags = 0; arrayvalue.value.reals = datap; PLI_INT32 indexp[1] = {0}; vpi_put_value_array(object, &arrayvalue, indexp, 4); CHECK_RESULT_NZ(vpi_chk_error(0)); arrayvalue.format = vpiShortRealVal; vpi_put_value_array(object, &arrayvalue, indexp, 4); CHECK_RESULT_NZ(vpi_chk_error(0)); arrayvalue.format = vpiTimeVal; vpi_put_value_array(object, &arrayvalue, indexp, 4); CHECK_RESULT_NZ(vpi_chk_error(0)); } { // test null array value TestVpiHandle object = vpi_handle_by_name((PLI_BYTE8*)"test.write_words", NULL); CHECK_RESULT_NZ(object); PLI_INT32 indexp[1] = {0}; vpi_put_value_array(object, 0, indexp, 4); CHECK_RESULT_NZ(vpi_chk_error(0)); } { // test unsupported TestVpiHandle TestVpiHandle object = vpi_handle_by_name((PLI_BYTE8*)"test", NULL); CHECK_RESULT_NZ(object); int datap[4] = {0, 0, 0, 0}; s_vpi_arrayvalue arrayvalue; arrayvalue.format = vpiIntVal; arrayvalue.flags = 0; arrayvalue.value.integers = datap; PLI_INT32 indexp[1] = {0}; vpi_put_value_array(object, &arrayvalue, indexp, 4); CHECK_RESULT_NZ(vpi_chk_error(0)); } { // test unsupported type TestVpiHandle object = vpi_handle_by_name((PLI_BYTE8*)"test.write_scalar", NULL); CHECK_RESULT_NZ(object); int datap[4] = {0, 0, 0, 0}; s_vpi_arrayvalue arrayvalue; arrayvalue.format = vpiIntVal; arrayvalue.flags = 0; arrayvalue.value.integers = datap; PLI_INT32 indexp[1] = {0}; vpi_put_value_array(object, &arrayvalue, indexp, 4); CHECK_RESULT_NZ(vpi_chk_error(0)); } { // test index out of bounds TestVpiHandle object = vpi_handle_by_name((PLI_BYTE8*)"test.write_bounds", NULL); CHECK_RESULT_NZ(object); int datap[4] = {0, 0, 0, 0}; s_vpi_arrayvalue arrayvalue; arrayvalue.format = vpiIntVal; arrayvalue.flags = 0; arrayvalue.value.integers = datap; PLI_INT32 indexp[1] = {4}; vpi_put_value_array(object, &arrayvalue, indexp, 4); CHECK_RESULT_NZ(vpi_chk_error(0)); indexp[0] = 0; vpi_put_value_array(object, &arrayvalue, indexp, 4); CHECK_RESULT_NZ(vpi_chk_error(0)); } { // test inaccessible TestVpiHandle object = vpi_handle_by_name((PLI_BYTE8*)"test.write_inaccessible", NULL); CHECK_RESULT_NZ(object); int datap[4] = {0, 0, 0, 0}; s_vpi_arrayvalue arrayvalue; arrayvalue.format = vpiIntVal; arrayvalue.flags = 0; arrayvalue.value.integers = datap; PLI_INT32 indexp[1] = {0}; vpi_put_value_array(object, &arrayvalue, indexp, 4); CHECK_RESULT_NZ(vpi_chk_error(0)); } { // test unsupported flags TestVpiHandle object = vpi_handle_by_name((PLI_BYTE8*)"test.write_words", NULL); CHECK_RESULT_NZ(object); int datap[4] = {0, 0, 0, 0}; s_vpi_arrayvalue arrayvalue; arrayvalue.format = vpiPropagateOff; arrayvalue.flags = 0; arrayvalue.value.integers = datap; PLI_INT32 indexp[1] = {0}; vpi_put_value_array(object, &arrayvalue, indexp, 4); CHECK_RESULT_NZ(vpi_chk_error(0)); arrayvalue.flags = vpiOneValue; vpi_put_value_array(object, &arrayvalue, indexp, 4); CHECK_RESULT_NZ(vpi_chk_error(0)); } { // test unsupported format & type combination TestVpiHandle object = vpi_handle_by_name((PLI_BYTE8*)"test.write_words", NULL); CHECK_RESULT_NZ(object); int datap[4] = {0, 0, 0, 0}; s_vpi_arrayvalue arrayvalue; arrayvalue.format = vpiShortIntVal; arrayvalue.flags = 0; arrayvalue.value.integers = datap; PLI_INT32 indexp[1] = {0}; vpi_put_value_array(object, &arrayvalue, indexp, 4); CHECK_RESULT_NZ(vpi_chk_error(0)); arrayvalue.flags = vpiOneValue; vpi_put_value_array(object, &arrayvalue, indexp, 4); CHECK_RESULT_NZ(vpi_chk_error(0)); } { // test num out of bounds TestVpiHandle object = vpi_handle_by_name((PLI_BYTE8*)"test.write_words", NULL); CHECK_RESULT_NZ(object); int datap[4] = {0, 0, 0, 0}; s_vpi_arrayvalue arrayvalue; arrayvalue.format = vpiIntVal; arrayvalue.flags = 0; arrayvalue.value.integers = datap; PLI_INT32 indexp[1] = {0}; vpi_put_value_array(object, &arrayvalue, indexp, 5); CHECK_RESULT_NZ(~vpi_chk_error(0)); } { // test null arrayvalue TestVpiHandle object = vpi_handle_by_name((PLI_BYTE8*)"test.write_words", NULL); CHECK_RESULT_NZ(object); PLI_INT32 indexp[1] = {0}; vpi_get_value_array(object, 0, indexp, 0); CHECK_RESULT_NZ(vpi_chk_error(0)); } { // test null indexp TestVpiHandle object = vpi_handle_by_name((PLI_BYTE8*)"test.write_words", NULL); CHECK_RESULT_NZ(object); int datap[4] = {0, 0, 0, 0}; s_vpi_arrayvalue arrayvalue; arrayvalue.format = vpiIntVal; arrayvalue.flags = 0; arrayvalue.value.integers = datap; vpi_get_value_array(object, &arrayvalue, 0, 0); CHECK_RESULT_NZ(vpi_chk_error(0)); } return 0; } extern "C" int mon_check(void) { return mon_check_props(); } #ifdef IS_VPI static int mon_check_vpi() { TestVpiHandle href = vpi_handle(vpiSysTfCall, 0); s_vpi_value vpi_value; vpi_value.format = vpiIntVal; vpi_value.value.integer = mon_check(); vpi_put_value(href, &vpi_value, NULL, vpiNoDelay); return 0; } static s_vpi_systf_data vpi_systf_data[] = {{vpiSysFunc, vpiIntFunc, (PLI_BYTE8*)"$mon_check", (PLI_INT32(*)(PLI_BYTE8*))mon_check_vpi, 0, 0, 0}, 0}; // cver entry void vpi_compat_bootstrap(void) { p_vpi_systf_data systf_data_p; systf_data_p = &(vpi_systf_data[0]); while (systf_data_p->type != 0) vpi_register_systf(systf_data_p++); } // icarus entry void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0}; #else int main(int argc, char** argv) { Verilated::commandArgs(argc, argv); const std::unique_ptr contextp{new VerilatedContext}; const std::unique_ptr top{new VM_PREFIX{contextp.get(), ""}}; contextp->fatalOnVpiError(0); #ifdef VERILATOR #ifdef TEST_VERBOSE contextp->scopesDump(); #endif #endif while (!contextp->gotFinish()) { top->eval(); } return 0; } #endif verilator-5.042/test_regress/t/t_xml_flat_vlvbound.out0000644000542200017500000003315015101701376023671 0ustar mahmoudyfreeshell verilator-5.042/test_regress/t/t_unroll_forfor.py0000755000542200017500000000073415101701376022662 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_assoc_default_func.py0000755000542200017500000000070615101701376023620 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.042/test_regress/t/t_trace_event_fst.py0000755000542200017500000000114615101701376023143 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_trace_event.v" test.compile(verilator_flags2=['--trace-fst --binary']) test.execute() test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dpi_arg_input_type.out0000644000542200017500000001206115101701376024027 0ustar mahmoudyfreeshelli_chandle 0 i_string 0 i_bit 0 i_logic 0 i_chandle_t 0 i_string_t 0 i_bit_t 0 i_logic_t 0 i_array_2_state_1 0 i_array_2_state_32 0 i_array_2_state_33 0 i_array_2_state_64 0 i_array_2_state_65 0 i_array_2_state_128 0 i_struct_2_state_1 0 i_struct_2_state_32 0 i_struct_2_state_33 0 i_struct_2_state_64 0 i_struct_2_state_65 0 i_struct_2_state_128 0 i_union_2_state_1 0 i_union_2_state_32 0 i_union_2_state_33 0 i_union_2_state_64 0 i_union_2_state_65 0 i_union_2_state_128 0 i_array_4_state_1 0 i_array_4_state_32 0 i_array_4_state_33 0 i_array_4_state_64 0 i_array_4_state_65 0 i_array_4_state_128 0 i_struct_4_state_1 0 i_struct_4_state_32 0 i_struct_4_state_33 0 i_struct_4_state_64 0 i_struct_4_state_65 0 i_struct_4_state_128 0 i_union_4_state_1 0 i_union_4_state_32 0 i_union_4_state_33 0 i_union_4_state_64 0 i_union_4_state_65 0 i_union_4_state_128 0 e_chandle 0 e_string 0 e_bit 0 e_logic 0 e_chandle_t 0 e_string_t 0 e_bit_t 0 e_logic_t 0 e_array_2_state_1 0 e_array_2_state_32 0 e_array_2_state_33 0 e_array_2_state_64 0 e_array_2_state_65 0 e_array_2_state_128 0 e_struct_2_state_1 0 e_struct_2_state_32 0 e_struct_2_state_33 0 e_struct_2_state_64 0 e_struct_2_state_65 0 e_struct_2_state_128 0 e_union_2_state_1 0 e_union_2_state_32 0 e_union_2_state_33 0 e_union_2_state_64 0 e_union_2_state_65 0 e_union_2_state_128 0 e_array_4_state_1 0 e_array_4_state_32 0 e_array_4_state_33 0 e_array_4_state_64 0 e_array_4_state_65 0 e_array_4_state_128 0 e_struct_4_state_1 0 e_struct_4_state_32 0 e_struct_4_state_33 0 e_struct_4_state_64 0 e_struct_4_state_65 0 e_struct_4_state_128 0 e_union_4_state_1 0 e_union_4_state_32 0 e_union_4_state_33 0 e_union_4_state_64 0 e_union_4_state_65 0 e_union_4_state_128 0 i_chandle 1 i_string 1 i_bit 1 i_logic 1 i_chandle_t 1 i_string_t 1 i_bit_t 1 i_logic_t 1 i_array_2_state_1 1 i_array_2_state_32 1 i_array_2_state_33 1 i_array_2_state_64 1 i_array_2_state_65 1 i_array_2_state_128 1 i_struct_2_state_1 1 i_struct_2_state_32 1 i_struct_2_state_33 1 i_struct_2_state_64 1 i_struct_2_state_65 1 i_struct_2_state_128 1 i_union_2_state_1 1 i_union_2_state_32 1 i_union_2_state_33 1 i_union_2_state_64 1 i_union_2_state_65 1 i_union_2_state_128 1 i_array_4_state_1 1 i_array_4_state_32 1 i_array_4_state_33 1 i_array_4_state_64 1 i_array_4_state_65 1 i_array_4_state_128 1 i_struct_4_state_1 1 i_struct_4_state_32 1 i_struct_4_state_33 1 i_struct_4_state_64 1 i_struct_4_state_65 1 i_struct_4_state_128 1 i_union_4_state_1 1 i_union_4_state_32 1 i_union_4_state_33 1 i_union_4_state_64 1 i_union_4_state_65 1 i_union_4_state_128 1 e_chandle 1 e_string 1 e_bit 1 e_logic 1 e_chandle_t 1 e_string_t 1 e_bit_t 1 e_logic_t 1 e_array_2_state_1 1 e_array_2_state_32 1 e_array_2_state_33 1 e_array_2_state_64 1 e_array_2_state_65 1 e_array_2_state_128 1 e_struct_2_state_1 1 e_struct_2_state_32 1 e_struct_2_state_33 1 e_struct_2_state_64 1 e_struct_2_state_65 1 e_struct_2_state_128 1 e_union_2_state_1 1 e_union_2_state_32 1 e_union_2_state_33 1 e_union_2_state_64 1 e_union_2_state_65 1 e_union_2_state_128 1 e_array_4_state_1 1 e_array_4_state_32 1 e_array_4_state_33 1 e_array_4_state_64 1 e_array_4_state_65 1 e_array_4_state_128 1 e_struct_4_state_1 1 e_struct_4_state_32 1 e_struct_4_state_33 1 e_struct_4_state_64 1 e_struct_4_state_65 1 e_struct_4_state_128 1 e_union_4_state_1 1 e_union_4_state_32 1 e_union_4_state_33 1 e_union_4_state_64 1 e_union_4_state_65 1 e_union_4_state_128 1 i_chandle 2 i_string 2 i_bit 2 i_logic 2 i_chandle_t 2 i_string_t 2 i_bit_t 2 i_logic_t 2 i_array_2_state_1 2 i_array_2_state_32 2 i_array_2_state_33 2 i_array_2_state_64 2 i_array_2_state_65 2 i_array_2_state_128 2 i_struct_2_state_1 2 i_struct_2_state_32 2 i_struct_2_state_33 2 i_struct_2_state_64 2 i_struct_2_state_65 2 i_struct_2_state_128 2 i_union_2_state_1 2 i_union_2_state_32 2 i_union_2_state_33 2 i_union_2_state_64 2 i_union_2_state_65 2 i_union_2_state_128 2 i_array_4_state_1 2 i_array_4_state_32 2 i_array_4_state_33 2 i_array_4_state_64 2 i_array_4_state_65 2 i_array_4_state_128 2 i_struct_4_state_1 2 i_struct_4_state_32 2 i_struct_4_state_33 2 i_struct_4_state_64 2 i_struct_4_state_65 2 i_struct_4_state_128 2 i_union_4_state_1 2 i_union_4_state_32 2 i_union_4_state_33 2 i_union_4_state_64 2 i_union_4_state_65 2 i_union_4_state_128 2 e_chandle 2 e_string 2 e_bit 2 e_logic 2 e_chandle_t 2 e_string_t 2 e_bit_t 2 e_logic_t 2 e_array_2_state_1 2 e_array_2_state_32 2 e_array_2_state_33 2 e_array_2_state_64 2 e_array_2_state_65 2 e_array_2_state_128 2 e_struct_2_state_1 2 e_struct_2_state_32 2 e_struct_2_state_33 2 e_struct_2_state_64 2 e_struct_2_state_65 2 e_struct_2_state_128 2 e_union_2_state_1 2 e_union_2_state_32 2 e_union_2_state_33 2 e_union_2_state_64 2 e_union_2_state_65 2 e_union_2_state_128 2 e_array_4_state_1 2 e_array_4_state_32 2 e_array_4_state_33 2 e_array_4_state_64 2 e_array_4_state_65 2 e_array_4_state_128 2 e_struct_4_state_1 2 e_struct_4_state_32 2 e_struct_4_state_33 2 e_struct_4_state_64 2 e_struct_4_state_65 2 e_struct_4_state_128 2 e_union_4_state_1 2 e_union_4_state_32 2 e_union_4_state_33 2 e_union_4_state_64 2 e_union_4_state_65 2 e_union_4_state_128 2 *-* All Finished *-* verilator-5.042/test_regress/t/t_randomize_queue_size.py0000755000542200017500000000104615101701376024215 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_inst_array_connect.v0000644000542200017500000000352715101701376023473 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module for Issue#1631 // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Julien Margetts. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ clk ); input clk; localparam N = 4; wire [7:0] cval1[0:N-1]; wire [7:0] cval2[N-1:0]; wire [7:0] cval3[0:N-1]; wire [7:0] cval4[N-1:0]; wire [3:0] inc; assign inc = 4'b0001; // verilator lint_off ASCRANGE COUNTER UCOUNTER1[N-1:0] ( .clk (clk), .inc (inc), .o (cval1) // Twisted ); COUNTER UCOUNTER2[N-1:0] ( .clk (clk), .inc (inc), .o (cval2) // Matches ); COUNTER UCOUNTER3[0:N-1] ( .clk (clk), .inc (inc), .o (cval3) // Matches ); COUNTER UCOUNTER4[0:N-1] ( .clk (clk), .inc (inc), .o (cval4) // Twisted ); always @(posedge clk) begin if ((cval1[3] != cval2[0]) || (cval3[3] != cval4[0])) $stop; if ((cval1[0] + cval1[1] + cval1[2] + cval2[1] + cval2[2] + cval2[3] + cval3[0] + cval3[1] + cval3[2] + cval4[1] + cval4[2] + cval4[3]) != 0) $stop; `ifdef TEST_VERBOSE $display("%d %d %d %d", cval1[0], cval1[1], cval1[2], cval1[3]); $display("%d %d %d %d", cval2[0], cval2[1], cval2[2], cval2[3]); $display("%d %d %d %d", cval3[0], cval3[1], cval3[2], cval3[3]); $display("%d %d %d %d", cval4[0], cval4[1], cval4[2], cval4[3]); `endif if (cval1[0] + cval1[3] > 3) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module COUNTER ( input clk, input inc, output reg [7:0] o ); initial o = 8'd0; // No reset input always @(posedge clk) if (inc) o <= o + 1; endmodule verilator-5.042/test_regress/t/t_verilated_debug.v0000644000542200017500000000113115101701376022721 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [95:0] wide; initial begin // internal code coverage for _vl_debug_print_w wide = {32'haa, 32'hbb, 32'hcc}; $c("_vl_debug_print_w(", $bits(wide), ", ", wide, ");"); end // Test loop always @ (posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_class_dict.v0000644000542200017500000000135015101701376021707 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); class Cls; int x; function new(int a); x = a; endfunction endclass module t; initial begin int dict[Cls]; Cls c1 = new(1); Cls c2 = new(2); dict[c1] = 1; dict[c2] = 2; `checkh(dict[c1], 1); `checkh(dict[c2], 2); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_timescale_nobackwards.out0000644000542200017500000000024515101701376024467 0ustar mahmoudyfreeshellTime scale of mod is 1ps / 1ps 0 Time scale of pkg is 1ps / 1ps 0 Time scale of CHK is 1ps / 1ps 0 Time scale of PRG is 1ps / 1ps 0 Time scale of CLS is 1ps / 1ps 0 verilator-5.042/test_regress/t/t_sys_readmem_b_8.mem0000644000542200017500000000076015101701376023154 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test data file // // Copyright 2006 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // ** Note this file has DOS CR's so we can test them! 10000 10001 10010 10011 /* multi line ignored */ 10100 10101 10110 10111 verilator-5.042/test_regress/t/t_class_extends_int_param_bad.py0000755000542200017500000000076615101701376025476 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_virtual_interface_pkg.v0000644000542200017500000000247015101701376024152 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Yilou Wang. // SPDX-License-Identifier: CC0-1.0 package my_pkg; virtual class CallBackBase; pure virtual function void add(int a, int b); endclass class my_class extends CallBackBase; virtual my_interface vif; function new(virtual my_interface vif); this.vif = vif; $display("my_class::new"); vif.register_callback(this); endfunction function void add(int a, int b); // $display("a + b = %0d", a + b); endfunction endclass endpackage interface my_interface; import my_pkg::*; CallBackBase callback_obj; function void register_callback(CallBackBase obj); callback_obj = obj; endfunction logic clk; always @(posedge clk) begin if (callback_obj != null) callback_obj.add(1, 2); else $display("callback_obj is null"); end endinterface module t; import my_pkg::*; logic clk = 0; my_interface vif(); my_class cl; assign vif.clk = clk; initial begin forever #5 clk = ~clk; end initial begin #10; cl = new(vif); #100; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_interface_array_bad.v0000644000542200017500000000217015101701376023544 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Demonstrate deferred linking error messages // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 interface foo_intf; logic a; endinterface function integer the_other_func (input integer val); return val; endfunction module t; localparam N = 4; foo_intf foos [N-1:0] (); logic [ 7 : 0 ] bar; // Non-constant dotted select is not allowed assign foos[bar].a = 1'b1; baz baz_inst (); // Unsure how to produce V3Param AstCellRef visitor errors //assign baz_inst.x = 1'b1; //assign baz_inst.N = 1'b1; //assign baz_inst.7 = 1'b1; //assign baz_inst.qux_t = 1'b1; //assign baz_inst.the_func = 1'b1; //assign baz_inst.THE_LP = 1'b1; //assign bar.x = 1'b1; //assign fake_inst.x = 1'b1; //assign the_other_func.x = 1'b1; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule module baz; typedef integer qux_t; function integer the_func (input integer val); return val; endfunction localparam THE_LP = 5; endmodule verilator-5.042/test_regress/t/t_wrapper_del_context_bad.out0000644000542200017500000000013115101701376025013 0ustar mahmoudyfreeshell%Error: Attempt to create model using a bad/deleted VerilatedContext pointer Aborting... verilator-5.042/test_regress/t/t_dpi_open_elem_c.cpp0000644000542200017500000001524415101701376023224 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2017 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "svdpi.h" #include #include #include // These require the above. Comment prevents clang-format moving them #include "TestCheck.h" //====================================================================== // clang-format off #if defined(VERILATOR) # include "Vt_dpi_open_elem__Dpi.h" #elif defined(VCS) # include "../vc_hdrs.h" #elif defined(NC) # define NEED_EXTERNS // #elif defined(MS) // # define NEED_EXTERNS #else # error "Unknown simulator for DPI test" #endif // clang-format on #ifdef NEED_EXTERNS extern "C" { // If get ncsim: *F,NOFDPI: Function {foo} not found in default libdpi. // Then probably forgot to list a function here. void dpii_bit_elem_p0_u1(int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o, const svOpenArrayHandle q); void dpii_bit_elem_p0_u2(int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o, const svOpenArrayHandle q); void dpii_bit_elem_p0_u3(int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o, const svOpenArrayHandle q); void dpii_logic_elem_p0_u1(int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o, const svOpenArrayHandle q); void dpii_logic_elem_p0_u2(int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o, const svOpenArrayHandle q); void dpii_logic_elem_p0_u3(int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o, const svOpenArrayHandle q); extern int dpii_failure(); } #endif int errors = 0; int dpii_failure() { return errors; } void dpii_unused(const svOpenArrayHandle u) {} //====================================================================== static void _dpii_bit_elem_ux(int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o, const svOpenArrayHandle q) { int dim = svDimensions(i); #ifndef NC // NC always returns zero and warns TEST_CHECK_HEX_EQ(dim, u); #endif for (int a = svLow(i, 1); a <= svHigh(i, 1); ++a) { fflush(stdout); if (dim == 1) { svBit v = svGetBitArrElem(i, a); svBit v2 = svGetBitArrElem1(i, a); TEST_CHECK_HEX_EQ(v, v2); svPutBitArrElem(o, v ? 0 : 1, a); svPutBitArrElem1(q, v ? 0 : 1, a); } else { for (int b = svLow(i, 2); b <= svHigh(i, 2); ++b) { if (dim == 2) { svBit v = svGetBitArrElem(i, a, b); svBit v2 = svGetBitArrElem2(i, a, b); TEST_CHECK_HEX_EQ(v, v2); svPutBitArrElem(o, v ? 0 : 1, a, b); svPutBitArrElem2(q, v ? 0 : 1, a, b); } else { for (int c = svLow(i, 3); c <= svHigh(i, 3); ++c) { if (dim == 3) { svBit v = svGetBitArrElem(i, a, b, c); svBit v2 = svGetBitArrElem3(i, a, b, c); TEST_CHECK_HEX_EQ(v, v2); svPutBitArrElem(o, v ? 0 : 1, a, b, c); svPutBitArrElem3(q, v ? 0 : 1, a, b, c); } } } } } } fflush(stdout); } void dpii_bit_elem_p0_u1(int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o, const svOpenArrayHandle q) { _dpii_bit_elem_ux(p, u, i, o, q); } void dpii_bit_elem_p0_u2(int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o, const svOpenArrayHandle q) { _dpii_bit_elem_ux(p, u, i, o, q); } void dpii_bit_elem_p0_u3(int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o, const svOpenArrayHandle q) { _dpii_bit_elem_ux(p, u, i, o, q); } //====================================================================== static void _dpii_logic_elem_ux(int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o, const svOpenArrayHandle q) { int dim = svDimensions(i); #ifndef NC // NC always returns zero and warns TEST_CHECK_HEX_EQ(dim, u); #endif int sizeInputOfArray = svSizeOfArray(i); // svSizeOfArray(i) undeterministic as not in C representation (void)sizeInputOfArray; // unused for (int a = svLow(i, 1); a <= svHigh(i, 1); ++a) { if (dim == 1) { svLogic v = svGetLogicArrElem(i, a); svLogic v2 = svGetLogicArrElem1(i, a); TEST_CHECK_HEX_EQ(v, v2); svPutLogicArrElem(o, v ? 0 : 1, a); svPutLogicArrElem1(q, v ? 0 : 1, a); } else { for (int b = svLow(i, 2); b <= svHigh(i, 2); ++b) { if (dim == 2) { svLogic v = svGetLogicArrElem(i, a, b); svLogic v2 = svGetLogicArrElem2(i, a, b); TEST_CHECK_HEX_EQ(v, v2); svPutLogicArrElem(o, v ? 0 : 1, a, b); svPutLogicArrElem2(q, v ? 0 : 1, a, b); } else { for (int c = svLow(i, 3); c <= svHigh(i, 3); ++c) { if (dim == 3) { svLogic v = svGetLogicArrElem(i, a, b, c); svLogic v2 = svGetLogicArrElem3(i, a, b, c); TEST_CHECK_HEX_EQ(v, v2); svPutLogicArrElem(o, v ? 0 : 1, a, b, c); svPutLogicArrElem3(q, v ? 0 : 1, a, b, c); } } } } } } fflush(stdout); } void dpii_logic_elem_p0_u1(int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o, const svOpenArrayHandle q) { _dpii_logic_elem_ux(p, u, i, o, q); } void dpii_logic_elem_p0_u2(int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o, const svOpenArrayHandle q) { _dpii_logic_elem_ux(p, u, i, o, q); } void dpii_logic_elem_p0_u3(int p, int u, const svOpenArrayHandle i, const svOpenArrayHandle o, const svOpenArrayHandle q) { _dpii_logic_elem_ux(p, u, i, o, q); } verilator-5.042/test_regress/t/t_gate_ormux.py0000755000542200017500000000143515101701376022143 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.cycles = (100000000 if test.benchmark else 100) test.sim_time = test.cycles * 10 + 1000 test.compile(v_flags2=["+define+SIM_CYCLES=" + str(test.cycles)], verilator_flags2=["-Wno-UNOPTTHREADS", "--stats", "-fno-dfg"]) if test.vlt: test.file_grep(test.stats, r'Optimizations, Const bit op reduction\s+(\d+)', 1058) test.execute() test.passes() verilator-5.042/test_regress/t/t_sys_file_basic_mcd_test2_0.dat0000644000542200017500000000020215101701376025236 0ustar mahmoudyfreeshellScotland is the greatest country. All other countries are inferior. Woe betide those to stand against the mighty Scottish nation. verilator-5.042/test_regress/t/t_langext_order.py0000755000542200017500000000100715101701376022621 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') # This is a compile only test. test.compile(v_flags2=["+1364-2005ext+v"]) test.passes() verilator-5.042/test_regress/t/t_math_concat.v0000644000542200017500000000666015101701376022070 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg [255:0] i; wire [255:0] q; assign q = { i[176],i[168],i[126],i[177],i[097],i[123],i[231],i[039], i[156],i[026],i[001],i[052],i[005],i[240],i[157],i[048], i[111],i[088],i[133],i[225],i[046],i[038],i[004],i[234], i[115],i[008],i[069],i[099],i[137],i[130],i[255],i[122], i[223],i[195],i[224],i[083],i[094],i[018],i[067],i[034], i[221],i[105],i[104],i[107],i[053],i[066],i[020],i[174], i[010],i[196],i[003],i[041],i[071],i[194],i[154],i[110], i[186],i[210],i[040],i[044],i[243],i[236],i[239],i[183], i[164],i[064],i[086],i[193],i[055],i[206],i[203],i[128], i[190],i[233],i[023],i[022],i[135],i[108],i[061],i[139], i[180],i[043],i[109],i[090],i[229],i[238],i[095],i[173], i[208],i[054],i[025],i[024],i[148],i[079],i[246],i[142], i[181],i[129],i[120],i[220],i[036],i[159],i[201],i[119], i[216],i[152],i[175],i[138],i[242],i[143],i[101],i[035], i[228],i[082],i[211],i[062],i[076],i[124],i[150],i[149], i[235],i[227],i[250],i[134],i[068],i[032],i[060],i[144], i[042],i[163],i[087],i[059],i[213],i[251],i[200],i[070], i[145],i[204],i[249],i[191],i[127],i[247],i[106],i[017], i[028],i[045],i[215],i[162],i[205],i[073],i[065],i[084], i[153],i[158],i[085],i[197],i[212],i[114],i[096],i[118], i[146],i[030],i[058],i[230],i[141],i[000],i[199],i[171], i[182],i[185],i[021],i[016],i[033],i[237],i[015],i[112], i[222],i[253],i[244],i[031],i[248],i[092],i[226],i[179], i[189],i[056],i[132],i[116],i[072],i[184],i[027],i[002], i[103],i[125],i[009],i[078],i[178],i[245],i[170],i[161], i[102],i[047],i[192],i[012],i[057],i[207],i[187],i[151], i[218],i[254],i[214],i[037],i[131],i[165],i[011],i[098], i[169],i[209],i[167],i[202],i[100],i[172],i[147],i[013], i[136],i[166],i[252],i[077],i[051],i[074],i[140],i[050], i[217],i[198],i[081],i[091],i[075],i[121],i[188],i[219], i[160],i[241],i[080],i[155],i[019],i[006],i[014],i[029], i[089],i[049],i[113],i[232],i[007],i[117],i[063],i[093] }; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; `ifdef TEST_VERBOSE $write("%x %x\n", q, i); `endif if (cyc==1) begin i <= 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26; end if (cyc==2) begin i <= 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8; if (q != 256'h697bad4b0cf2d7fa4ad22809293710bb67d1eb3131e8eb2135f2c7bd820baa84) $stop; end if (cyc==3) begin if (q != 256'h320eda5078b3e942353d16dddc8b29fd773b4fcec8323612dadfb1fa483f602c) $stop; end if (cyc==4) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.042/test_regress/t/t_struct_unpacked.v0000644000542200017500000000313615101701376023001 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009-2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); class Cls; typedef struct { string m_strg; } underclass_t; underclass_t m_cstr; function underclass_t get_cstr(); m_cstr.m_strg = "foo"; return m_cstr; endfunction endclass module x; typedef struct { int a, b; logic [3:0] c; } embedded_t; typedef struct { embedded_t b; embedded_t tab [3:0]; } notembedded_t; typedef struct { logic [15:0] m_i; string m_s; } istr_t; notembedded_t p; embedded_t t [1:0]; istr_t istr; string s; Cls c; initial begin t[1].a = 2; p.b.a = 1; if (t[1].a != 2) $stop; if (p.b.a != 1) $stop; istr.m_i = 12; istr.m_s = "str1"; `checkp(istr, "'{m_i:'hc, m_s:\"str1\"}"); istr = '{m_i: '1, m_s: "str2"}; `checkp(istr, "'{m_i:'hffff, m_s:\"str2\"}"); c = new; s = c.get_cstr().m_strg; `checks(s, "foo"); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_math_repl3_bad.v0000644000542200017500000000113015101701376022437 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t #( parameter NUM_LANES = 1); reg [(NUM_LANES*8)-1:0] link_data_reg, link_data_reg_in; reg [1:0] other; always @(*) begin if (NUM_LANES >= 2) begin // Not a generate if link_data_reg_in = {{((NUM_LANES - 2) * 8) {1'b0}}, link_data_reg[15:8]}; end other = {32'bz{1'b1}}; end wire ok1 = 1'b1; wire [6:0] ok7 = {3'b111{ok1}}; // Ok endmodule verilator-5.042/test_regress/t/t_sys_fread.out0000644000542200017500000000502315101701376022121 0ustar mahmoudyfreeshellDump: r_i: 00010203 r_upb: 0e 0d 0c 0b 0a 09 08 07 06 05 04 r_dnb: 0f 10 11 12 13 14 15 16 17 18 19 r_ups: 2e2f 2c2d 2a2b 2829 2627 2425 2223 2021 1e1f 1c1d 1a1b r_dns: 3031 3233 3435 3637 3839 3a3b 3c3d 3e3f 0041 0243 0445 r_upi: 6e6f7071 6a6b6c6d 66676869 62636465 5e5f6061 5a5b5c5d 56575859 52535455 4e4f5051 4a4b4c4d 46474849 r_dni: 72737475 76777879 7a7b7c7d 7e7f8081 02838485 06878889 0a8b8c8d 0e8f9091 12939495 16979899 1a9b9c9d r_upq: 2eeff0f1f2f3f4f5 26e7e8e9eaebeced 1edfe0e1e2e3e4e5 16d7d8d9dadbdcdd 0ecfd0d1d2d3d4d5 06c7c8c9cacbcccd 3ebfc0c1c2c3c4c5 36b7b8b9babbbcbd 2eafb0b1b2b3b4b5 26a7a8a9aaabacad 1e9fa0a1a2a3a4a5 r_dnq: 36f7f8f9fafbfcfd 3eff000102030405 060708090a0b0c0d 0e0f101112131415 161718191a1b1c1d 1e1f202122232425 262728292a2b2c2d 2e2f303132333435 363738393a3b3c3d 3e3f404142434445 064748494a4b4c4d r_upw: a8a9aaabacadaeafb0 9fa0a1a2a3a4a5a6a7 969798999a9b9c9d9e 8d8e8f909192939495 8485868788898a8b8c 7b7c7d7e7f80818283 72737475767778797a 696a6b6c6d6e6f7071 606162636465666768 5758595a5b5c5d5e5f 4e4f50515253545556 r_dnw: b1b2b3b4b5b6b7b8b9 babbbcbdbebfc0c1c2 c3c4c5c6c7c8c9cacb cccdcecfd0d1d2d3d4 d5d6d7d8d9dadbdcdd dedfe0e1e2e3e4e5e6 e7e8e9eaebecedeeef f0f1f2f3f4f5f6f7f8 f9fafbfcfdfeff0001 02030405060708090a 0b0c0d0e0f10111213 Dump: r_i: ffffffff r_upb: 05 04 03 02 01 00 ff 0e ff ff 0c r_dnb: 0d ff ff 0f ff 06 07 08 09 0a 0b r_ups: 3fff 3fff 3fff 3fff 1213 1011 3fff 3fff 3fff 3fff 3fff r_dns: 3fff 3fff 3fff 3fff 3fff 3fff 3fff 3fff 3fff 3fff 3fff r_upi: 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff r_dni: 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff r_upq: 3fffffffffffffff 3fffffffffffffff 3fffffffffffffff 3fffffffffffffff 3fffffffffffffff 3fffffffffffffff 3fffffffffffffff 3fffffffffffffff 3fffffffffffffff 3fffffffffffffff 3fffffffffffffff r_dnq: 3fffffffffffffff 3fffffffffffffff 3fffffffffffffff 3fffffffffffffff 3fffffffffffffff 3fffffffffffffff 3fffffffffffffff 3fffffffffffffff 3fffffffffffffff 3fffffffffffffff 3fffffffffffffff r_upw: ffffffffffffffffff ffffffffffffffffff ffffffffffffffffff ffffffffffffffffff ffffffffffffffffff ffffffffffffffffff ffffffffffffffffff ffffffffffffffffff ffffffffffffffffff ffffffffffffffffff ffffffffffffffffff r_dnw: ffffffffffffffffff ffffffffffffffffff ffffffffffffffffff ffffffffffffffffff ffffffffffffffffff ffffffffffffffffff ffffffffffffffffff ffffffffffffffffff ffffffffffffffffff ffffffffffffffffff ffffffffffffffffff *-* All Finished *-* verilator-5.042/test_regress/t/t_class_enum.py0000755000542200017500000000073415101701376022123 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_vlt_warn_file_bad.py0000755000542200017500000000121515101701376023426 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint( # See also t/t_lint_warn_incfile1_bad # See also t/t_lint_warn_incfile2_bad verilator_flags2=["--no-std t/t_vlt_warn_file_bad.vlt"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_var_static.v0000644000542200017500000000673015101701376021745 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); function automatic int f_au_st_global (); static int st = 0; st++; return st; endfunction package my_pkg; function int f_no_st_pkg (); static int st = 0; st++; return st; endfunction endpackage class my_cls; static function int get_cnt1; static int cnt = 0; return ++cnt; endfunction endclass module t (/*AUTOARG*/ // Inputs clk ); input clk; function int f_no_no (); int st = 2; st++; return st; endfunction function int f_no_st (); static int st = 2; st++; return st; endfunction function int f_no_au (); automatic int au = 2; au++; return au; endfunction function static int f_st_no (); int st = 2; st++; return st; endfunction function static int f_st_st (); static int st = 2; st++; return st; endfunction function static int f_st_au (); automatic int au = 2; au++; return au; endfunction function automatic int f_au_no (); int au = 2; au++; return au; endfunction function automatic int f_au_st (); static int st = 2; st++; return st; endfunction function automatic int f_au_au (); automatic int au = 2; au++; return au; endfunction string plusarg = ""; bit has_plusarg = |($value$plusargs("plusarg=%s", plusarg)); int v; initial begin if (has_plusarg) begin if (plusarg == "") begin $fatal(1, "%m: +plusarg must not be empty"); end end v = f_no_no(); `checkh(v, 3); v = f_no_no(); `checkh(v, 4); v = f_no_st(); `checkh(v, 3); v = f_no_st(); `checkh(v, 4); v = f_no_au(); `checkh(v, 3); v = f_no_au(); `checkh(v, 3); // v = f_st_no(); `checkh(v, 3); v = f_st_no(); `checkh(v, 4); v = f_st_st(); `checkh(v, 3); v = f_st_st(); `checkh(v, 4); v = f_st_au(); `checkh(v, 3); v = f_st_au(); `checkh(v, 3); // v = f_au_no(); `checkh(v, 3); v = f_au_no(); `checkh(v, 3); v = f_au_st(); `checkh(v, 3); v = f_au_st(); `checkh(v, 4); v = f_au_au(); `checkh(v, 3); v = f_au_au(); `checkh(v, 3); // v = f_au_st_global(); `checkh(v, 1); v = f_au_st_global(); `checkh(v, 2); v = my_pkg::f_no_st_pkg(); `checkh(v, 1); v = my_pkg::f_no_st_pkg(); `checkh(v, 2); // v = my_cls::get_cnt1(); `checkh(v, 1); v = my_cls::get_cnt1(); `checkh(v, 2); // end int cyc = 0; always @ (posedge clk) begin int ist1; static int ist2; automatic int iau3; cyc <= cyc + 1; if (cyc == 0) begin ist1 = 10; ist2 = 20; iau3 = 30; v = ist1; `checkh(v, 10); v = ist2; `checkh(v, 20); v = iau3; `checkh(v, 30); ++ist1; ++ist2; ++iau3; end else if (cyc == 1) begin v = ist1; `checkh(v, 11); v = ist2; `checkh(v, 21); //TODO v = iau3; `checkh(v, 0); end else if (cyc == 5) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_tri_gate_notif0_pins_inout.py0000755000542200017500000000141215101701376025310 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_tri_gate.cpp" test.top_filename = "t/t_tri_gate.v" test.compile(make_top_shell=False, make_main=False, v_flags2=['+define+T_NOTIF0'], make_flags=['CPPFLAGS_ADD=-DT_NOTIF0'], verilator_flags2=["--exe --pins-inout-enables", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_pp_line.v0000644000542200017500000000104015101701376021221 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Anthony Donlon. // SPDX-License-Identifier: CC0-1.0 module t; `line 100 "some file" 0 $info("aaaaaaaa file='%s'", `__FILE__); $info("bbbbbbbb file='%s'", `__FILE__); `line 200 "somefile.v" 0 $info("cccccccc file='%s'", `__FILE__); `line 300 "/a/somefile.v" 0 $info("dddddddd file='%s'", `__FILE__); `line 400 "C:\\a\\somefile.v" 0 $info("eeeeeeee file='%s'", `__FILE__); endmodule verilator-5.042/test_regress/t/t_flag_csplit_off.py0000755000542200017500000000476315101701376023121 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_flag_csplit.v" def check_no_splits(): for filename in test.glob_some(test.obj_dir + "/*.cpp"): filename = re.sub(r'__024root', '', filename) if re.search(r'__[1-9]', filename): test.error("Split file found: " + filename) def check_all_file(): for filename in test.glob_some(test.obj_dir + "/*.cpp"): if re.search(r'__ALL.cpp', filename): return def check_gcc_flags(filename): # Coverage collection alters optimization flags if test.have_dev_gcov: return with open(filename, 'r', encoding="utf8") as fh: for line in fh: line = line.rstrip() if test.verbose: print(":log: " + line) if re.search(r'\.cpp', line) and re.search('-O0', line): test.error("File built as slow (should be in __ALL.cpp) : " + line) # This rule requires GNU make > 4.1 (or so, known broken in 3.81) #%__Slow.o: %__Slow.cpp # $(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_SLOW) -c -o $@ $< if not test.make_version or float(test.make_version) < 4.1: test.skip("Test requires GNU Make version >= 4.1") test.compile(v_flags2=["--trace-vcd --output-split 0 --exe ../" + test.main_filename], verilator_make_gmake=False) # We don't use the standard test_regress rules, as want to test the rules # properly build test.run(logfile=test.obj_dir + "/vlt_gcc.log", tee=test.verbose, cmd=[ os.environ["MAKE"], "-C " + test.obj_dir, "-f " + test.vm_prefix + ".mk", "-j 4", "VM_PREFIX=" + test.vm_prefix, "TEST_OBJ_DIR=" + test.obj_dir, "CPPFLAGS_DRIVER=-D" + test.name.upper(), ("CPPFLAGS_DRIVER2=-DTEST_VERBOSE=1" if test.verbose else ""), "OPT_FAST=-O2", "OPT_SLOW=-O0" ]) test.execute() # Never spliting, so should set VM_PARALLEL_BUILDS to 0 by default test.file_grep(test.obj_dir + "/" + test.vm_prefix + "_classes.mk", r'VM_PARALLEL_BUILDS\s*=\s*0') check_no_splits() check_all_file() check_gcc_flags(test.obj_dir + "/vlt_gcc.log") test.passes() verilator-5.042/test_regress/t/t_flag_main_top_name.py0000755000542200017500000000127515101701376023572 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_flag_main_top_name.v" test.compile(verilator_flags=["-Mdir " + test.obj_dir, "--exe", "--build", "--main"], verilator_flags2=["--top-module top", "--main-top-name ALTOP"], make_main=False) test.execute() test.passes() verilator-5.042/test_regress/t/tsub/0000755000542200017500000000000015101701376020043 5ustar mahmoudyfreeshellverilator-5.042/test_regress/t/tsub/t_flag_f_tsub_inc.v0000644000542200017500000000010115101701376023651 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module `define GOT_DEF5 verilator-5.042/test_regress/t/tsub/t_flag_f_tsub.vc0000644000542200017500000000013515101701376023172 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module +define+GOT_DEF4=1 +incdir+. t_flag_f_tsub.v verilator-5.042/test_regress/t/tsub/t_flag_f_tsub.v0000644000542200017500000000010115101701376023020 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module `define GOT_DEF6 verilator-5.042/test_regress/t/t_struct_type_bad.out0000644000542200017500000000034415101701376023336 0ustar mahmoudyfreeshell%Error: t/t_struct_type_bad.v:13:7: Expecting a data type: 'i' 13 | i badi; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_clk_concat2.v0000644000542200017500000000375515101701376021774 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty. // SPDX-License-Identifier: CC0-1.0 module some_module ( input wrclk ); logic [ 1 : 0 ] some_state; logic [1:0] some_other_state; always @(posedge wrclk) begin case (some_state) 2'b11: if (some_other_state == 0) some_state <= 2'b00; default: $display ("This is a display statement"); endcase if (wrclk) some_other_state <= 0; end endmodule `define BROKEN module t1( input [3:0] i_clks, input i_clk0, input i_clk1 ); some_module some_module ( `ifdef BROKEN .wrclk (i_clks[3]) `else .wrclk (i_clk1) `endif ); endmodule module t2( input [2:0] i_clks, input i_clk0, input i_clk1, input i_clk2, input i_data ); logic [3:0] the_clks; logic data_q; assign the_clks[3] = i_clk1; assign the_clks[2] = i_clk2; assign the_clks[1] = i_clk1; assign the_clks[0] = i_clk0; always @(posedge i_clk0) begin data_q <= i_data; end t1 t1 ( .i_clks (the_clks), .i_clk0 (i_clk0), .i_clk1 (i_clk1) ); endmodule module t( /*AUTOARG*/ // Inputs clk /*verilator clocker*/, input clk0 /*verilator clocker*/, input clk1 /*verilator clocker*/, input clk2 /*verilator clocker*/, input data_in ); input clk; logic [2:0] clks; assign clks = {1'b0, clk1, clk0}; t2 t2 ( .i_clks (clks), .i_clk0 (clk0), .i_clk1 (clk), .i_clk2 (clk2), .i_data (data_in) ); always @(posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_wrapper_clone.cpp0000644000542200017500000000545415101701376022765 0ustar mahmoudyfreeshell// // DESCRIPTION: Verilator: Verilog Test module for prepareClone/atClone APIs // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2023 by Yinan Xu. // SPDX-License-Identifier: CC0-1.0 #include #include #include // These require the above. Comment prevents clang-format moving them #include "TestCheck.h" #include VM_PREFIX_INCLUDE double sc_time_stamp() { return 0; } // Note: Since the pthread_atfork API accepts only function pointers, // we are using a static variable for the TOP just for a simple example. // Without using the pthread_atfork API, the user can instead manually call // prepareClone and atClone before and after calling fork, and topp can be // allocated dynamically. static VM_PREFIX* topp = nullptr; static auto prepareClone = []() { topp->prepareClone(); }; static auto atClone = []() { topp->atClone(); }; void single_cycle(VM_PREFIX* topp) { topp->clock = 1; topp->eval(); topp->clock = 0; topp->eval(); } int main(int argc, char** argv) { // We disable the buffering for stdout in this test. // Redirecting the stdout to files with buffering causes duplicated stdout // outputs in both parent and child processes, even if they are actually // called before the fork. setvbuf(stdout, nullptr, _IONBF, 0); VerilatedContext* contextp = new VerilatedContext; topp = new VM_PREFIX{contextp}; // To avoid resource leaks, prepareClone must be called before fork to // free all the allocated resources. Though this would bring performance // overhead to the parent process, we believe that fork should not be // called frequently, and the overhead is minor compared to simulation. pthread_atfork(prepareClone, atClone, atClone); // If you care about critical performance, prepareClone can be avoided, // with atClone being called only at the child process, as follows. // It has the same functionality as the previous one, but has memory leaks. // According to the sanitizer, 288 bytes are leaked for one fork call. // pthread_atfork(nullptr, nullptr, atClone); topp->reset = 1; topp->is_parent = 0; for (int i = 0; i < 5; i++) single_cycle(topp); topp->reset = 0; while (!contextp->gotFinish()) { single_cycle(topp); if (topp->do_clone) { const int pid = fork(); if (pid < 0) { printf("fork failed\n"); } else if (pid == 0) { printf("child: here we go\n"); } else { while (wait(nullptr) > 0); printf("parent: here we go\n"); topp->is_parent = 1; } } } topp->final(); VL_DO_DANGLING(delete topp, topp); VL_DO_DANGLING(delete contextp, contextp); return 0; } verilator-5.042/test_regress/t/t_split_var_0.v0000644000542200017500000004442215101701376022030 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by Yutetsu TAKATSUKASA. // SPDX-License-Identifier: CC0-1.0 // If split_var pragma is removed, UNOPTFLAT appears. module barshift_1d_unpacked #(parameter DEPTH = 2, localparam WIDTH = 2**DEPTH) (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out /*verilator split_var*/); localparam OFFSET = -3; `ifdef TEST_ATTRIBUTES logic [WIDTH-1:0] tmp[DEPTH+OFFSET:OFFSET] /*verilator split_var*/; `else logic [WIDTH-1:0] tmp[DEPTH+OFFSET:OFFSET]; `endif generate for(genvar i = 0; i < DEPTH; ++i) begin always_comb if (shift[i]) begin /*verilator lint_off ALWCOMBORDER*/ tmp[i+1+OFFSET] = {tmp[i+OFFSET][(1 << i)-1:0], tmp[i+OFFSET][WIDTH-1:(2**i)]}; /*verilator lint_on ALWCOMBORDER*/ end else begin tmp[i+1+OFFSET] = tmp[i+OFFSET]; end end endgenerate assign tmp[0+OFFSET] = in; assign out[WIDTH-1-:WIDTH-1] = tmp[DEPTH+OFFSET][WIDTH-1:1]; assign out[0] = tmp[DEPTH+OFFSET][0+:1]; endmodule module barshift_1d_unpacked_le #(parameter DEPTH = 2, localparam WIDTH = 2**DEPTH) (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out); localparam OFFSET = -3; // almost same as above module, but tmp[smaller:bigger] here. logic [WIDTH-1:0] tmp[OFFSET:DEPTH+OFFSET] /*verilator split_var*/; generate for(genvar i = 0; i < DEPTH; ++i) begin always_comb if (shift[i]) begin /*verilator lint_off ALWCOMBORDER*/ tmp[i+1+OFFSET] = {tmp[i+OFFSET][(1 << i)-1:0], tmp[i+OFFSET][WIDTH-1:(2**i)]}; /*verilator lint_on ALWCOMBORDER*/ end else begin tmp[i+1+OFFSET] = tmp[i+OFFSET]; end end endgenerate assign tmp[0+OFFSET] = in; assign out = tmp[DEPTH+OFFSET]; endmodule module barshift_1d_unpacked_struct0 #(parameter DEPTH = 2, localparam WIDTH = 2**DEPTH) (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out); localparam OFFSET = 1; typedef struct packed { logic [WIDTH-1:0] data; } data_type; data_type tmp[DEPTH+OFFSET:OFFSET] /*verilator split_var*/; generate for(genvar i = 0; i < DEPTH; ++i) begin always_comb if (shift[i]) begin /*verilator lint_off ALWCOMBORDER*/ tmp[i+1+OFFSET] = {tmp[i+OFFSET][(1 << i)-1:0], tmp[i+OFFSET][WIDTH-1:(2**i)]}; /*verilator lint_on ALWCOMBORDER*/ end else begin tmp[i+1+OFFSET] = tmp[i+OFFSET]; end end endgenerate assign tmp[0+OFFSET] = in; assign out = tmp[DEPTH+OFFSET]; endmodule module barshift_2d_unpacked #(parameter DEPTH = 2, localparam WIDTH = 2**DEPTH) (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out); localparam OFFSET = 1; localparam N = 3; reg [WIDTH-1:0] tmp0[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1] /*verilator split_var*/; reg [WIDTH-1:0] tmp1[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1] /*verilator split_var*/; reg [WIDTH-1:0] tmp2[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1]; reg [WIDTH-1:0] tmp3[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1] /*verilator split_var*/; reg [WIDTH-1:0] tmp4[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1] /*verilator split_var*/; reg [WIDTH-1:0] tmp5[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1]; reg [WIDTH-1:0] tmp6[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1] /*verilator split_var*/; reg [WIDTH-1:0] tmp7[DEPTH+OFFSET+1:OFFSET+1][OFFSET:OFFSET+N-1] /*verilator split_var*/; reg [WIDTH-1:0] tmp8[DEPTH+OFFSET+3:OFFSET-1][OFFSET:OFFSET+N-1] /*verilator split_var*/; reg [WIDTH-1:0] tmp9[DEPTH+OFFSET+3:OFFSET+3][OFFSET:OFFSET+N-1] /*verilator split_var*/; reg [WIDTH-1:0] tmp10[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1] /*verilator split_var*/; // because tmp11 is not split for testing mixture usage of split_var and no-spliv_ar, // UNOPTFLAT appears, but it's fine. /*verilator lint_off UNOPTFLAT*/ reg [WIDTH-1:0] tmp11[-1:1][DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1]; /*verilator lint_on UNOPTFLAT*/ reg [WIDTH-1:0] tmp12[-1:0][DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1] /*verilator split_var*/; reg [WIDTH-1:0] tmp13[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1] /*verilator split_var*/; generate for(genvar i = 0; i < DEPTH; ++i) begin for(genvar j = OFFSET; j < N + OFFSET; ++j) begin always_comb if (shift[i]) begin /*verilator lint_off ALWCOMBORDER*/ tmp0[i+1+OFFSET][j] = {tmp0[i+OFFSET][j][(1 << i)-1:0], tmp0[i+OFFSET][j][WIDTH-1:(2**i)]}; /*verilator lint_on ALWCOMBORDER*/ end else begin tmp0[i+1+OFFSET][j] = tmp0[i+OFFSET][j]; end end end for(genvar j = OFFSET; j < N + OFFSET; ++j) begin assign tmp0[0 + OFFSET][j] = in; end endgenerate assign tmp1 = tmp0; // split both side assign tmp2 = tmp1; // split only rhs assign tmp3 = tmp2; // split only lhs always_comb tmp4 = tmp3; // split both side always_comb tmp5 = tmp4; // split only rhs always_comb tmp6 = tmp5; // split only lhs assign tmp7 = tmp6; assign tmp8[DEPTH+OFFSET+1:OFFSET+1] = tmp7; assign tmp9 = tmp8[DEPTH+OFFSET+1:OFFSET+1]; assign tmp10[DEPTH+OFFSET:OFFSET] = tmp9[DEPTH+OFFSET+3:OFFSET+3]; assign tmp11[1] = tmp10; assign tmp11[-1] = tmp11[1]; assign tmp11[0] = tmp11[-1]; assign tmp12 = tmp11[0:1]; assign out = tmp12[1][DEPTH+OFFSET][OFFSET]; endmodule module barshift_1d_unpacked_struct1 #(parameter DEPTH = 2, localparam WIDTH = 2**DEPTH) (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out); localparam OFFSET = 2; typedef struct packed { int data; } data_type; data_type tmp[DEPTH+OFFSET:OFFSET] /*verilator split_var*/; localparam [32-WIDTH-1:0] PAD = 0; generate for(genvar i = 0; i < DEPTH; ++i) begin always_comb if (shift[i]) begin /*verilator lint_off ALWCOMBORDER*/ tmp[i+1+OFFSET] = {PAD, tmp[i+OFFSET][(1 << i)-1:0], tmp[i+OFFSET][WIDTH-1:(2**i)]}; /*verilator lint_on ALWCOMBORDER*/ end else begin tmp[i+1+OFFSET] = tmp[i+OFFSET]; end end endgenerate assign tmp[0+OFFSET] = {PAD, in}; logic _dummy; always_comb {_dummy, out[WIDTH-1:1], out[0]} = tmp[DEPTH+OFFSET][WIDTH:0]; endmodule module barshift_2d_packed_array #(parameter DEPTH = 2, localparam WIDTH = 2**DEPTH) (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out); localparam OFFSET = -2; /*verilator lint_off ASCRANGE*/ reg [OFFSET:DEPTH+OFFSET][WIDTH-1:0] tmp /*verilator split_var*/; /*verilator lint_on ASCRANGE*/ generate for(genvar i = 0; i < DEPTH; ++i) begin always @(shift or tmp) /*verilator lint_off ALWCOMBORDER*/ if (shift[i]) begin tmp[i+1+OFFSET] = {tmp[i+OFFSET][(1 << i)-1:0], tmp[i+OFFSET][WIDTH-1:(2**i)]}; end else begin tmp[i+1+OFFSET][1:0] = tmp[i+OFFSET][1:0]; tmp[i+1+OFFSET][WIDTH-1:2] = tmp[i+OFFSET][WIDTH-1:2]; end /*verilator lint_on ALWCOMBORDER*/ end endgenerate assign tmp[0+OFFSET] = in; assign out = tmp[DEPTH+OFFSET]; endmodule module barshift_2d_packed_array_le #(parameter DEPTH = 2, localparam WIDTH = 2**DEPTH) (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out); localparam OFFSET = -2; /*verilator lint_off ASCRANGE*/ reg [OFFSET:DEPTH+OFFSET][OFFSET:WIDTH-1+OFFSET] tmp /*verilator split_var*/; /*verilator lint_on ASCRANGE*/ generate for(genvar i = 0; i < DEPTH; ++i) begin always_comb /*verilator lint_off ALWCOMBORDER*/ if (shift[i]) begin tmp[i+1+OFFSET] = {tmp[i+OFFSET][WIDTH-(2**i)+OFFSET:WIDTH-1+OFFSET], tmp[i+OFFSET][OFFSET:WIDTH-(2**i)-1+OFFSET]}; end else begin // actulally just tmp[i+1+OFFSET] = tmp[i+OFFSET] tmp[i+1+OFFSET][0+OFFSET:2+OFFSET] = tmp[i+OFFSET][0+OFFSET:2+OFFSET]; tmp[i+1+OFFSET][3+OFFSET] = tmp[i+OFFSET][3+OFFSET]; {tmp[i+1+OFFSET][4+OFFSET],tmp[i+1+OFFSET][5+OFFSET]} = {tmp[i+OFFSET][4+OFFSET], tmp[i+OFFSET][5+OFFSET]}; {tmp[i+1+OFFSET][7+OFFSET],tmp[i+1+OFFSET][6+OFFSET]} = {tmp[i+OFFSET][7+OFFSET], tmp[i+OFFSET][6+OFFSET]}; end /*verilator lint_on ALWCOMBORDER*/ end endgenerate assign tmp[0+OFFSET] = in; assign out = tmp[DEPTH+OFFSET]; endmodule module barshift_1d_packed_struct #(localparam DEPTH = 3, localparam WIDTH = 2**DEPTH) (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out); typedef struct packed { logic [WIDTH-1:0] v0, v1, v2, v3; } data_type; wire data_type tmp /*verilator split_var*/; assign tmp.v0 = in; assign tmp.v1 = shift[0] == 1'b1 ? {tmp.v0[(1 << 0)-1:0], tmp.v0[WIDTH-1:2**0]} : tmp.v0; assign tmp.v2 = shift[1] == 1'b1 ? {tmp.v1[(1 << 1)-1:0], tmp.v1[WIDTH-1:2**1]} : tmp.v1; assign tmp.v3 = shift[2] == 1'b1 ? {tmp.v2[(1 << 2)-1:0], tmp.v2[WIDTH-1:2**2]} : tmp.v2; assign out = tmp.v3; endmodule module barshift_bitslice #(parameter DEPTH = 2, localparam WIDTH = 2**DEPTH) (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out); /*verilator lint_off ASCRANGE*/ wire [0:WIDTH*(DEPTH+1) - 1] tmp /*verilator split_var*/; /*verilator lint_on ASCRANGE*/ generate for(genvar i = 0; i < DEPTH; ++i) begin always_comb if (shift[i]) begin tmp[WIDTH*(i+1):WIDTH*(i+1+1)-1] = {tmp[WIDTH*(i+1)-(1<= 4) begin if (!unpack_sig0[16] || !unpack_sig1[16]) $stop; if (!unpack_sig2[16] || !unpack_sig3[16]) $stop; end else begin if (unpack_sig0[16] || unpack_sig1[16]) $stop; if (unpack_sig2[16] || unpack_sig3[16]) $stop; end end endmodule module hash_descending ( input logic [31:1] i /* verilator split_var */, output logic [8:0] o ); assign o = i[23:15] ^ i[14:6]; endmodule // Does the same as hash_descending but with 'i' using an ascending range module hash_ascending ( /*verilator lint_off ASCRANGE*/ input logic [1:31] i /* verilator split_var */, /*verilator lint_on ASCRANGE*/ output logic [8:0] o ); assign o = i[9:17] ^ i[18:26]; endmodule module t(/*AUTOARG*/ clk); input clk; localparam DEPTH = 3; localparam WIDTH = 2**DEPTH; localparam NUMSUB = 9; logic [WIDTH-1:0] in; logic [WIDTH-1:0] out[0:NUMSUB-1]; logic [WIDTH-1:0] through_tmp; logic [DEPTH-1:0] shift = 0; // barrel shifter barshift_1d_unpacked #(.DEPTH(DEPTH)) shifter0(.in(in), .out(out[0]), .shift(shift)); barshift_1d_unpacked_le #(.DEPTH(DEPTH)) shifter1(.in(in), .out(out[1]), .shift(shift)); barshift_1d_unpacked_struct0 #(.DEPTH(DEPTH)) shifter2(.in(in), .out(out[2]), .shift(shift)); barshift_2d_unpacked #(.DEPTH(DEPTH)) shifter3(.in(in), .out(out[3]), .shift(shift)); barshift_1d_unpacked_struct1 #(.DEPTH(DEPTH)) shifter4(.in(in), .out(out[4]), .shift(shift)); barshift_2d_packed_array #(.DEPTH(DEPTH)) shifter5(.in(in), .out(out[5]), .shift(shift)); barshift_2d_packed_array_le #(.DEPTH(DEPTH)) shifter6(.in(in), .out(out[6]), .shift(shift)); barshift_1d_packed_struct shifter7(.in(in), .out(out[7]), .shift(shift)); barshift_bitslice #(.DEPTH(DEPTH)) shifter8(.in(in), .out(out[8]), .shift(shift)); through #(.WIDTH(WIDTH)) though0 (.in(out[8]), .out(through_tmp)); delay delay0(.clk(clk)); var_decl_with_init i_var_decl_with_init(); t_array_rev i_t_array_rev(clk); logic [31:1] hash_input_d = 31'h3210abcd; // 1 based on purpose /*verilator lint_off ASCRANGE*/ logic [1:31] hash_input_a = 31'h3210abcd; // 1 based on purpose /*verilator lint_on ASCRANGE*/ logic [8:0] hash_output_dd; logic [8:0] hash_output_da; logic [8:0] hash_output_ad; logic [8:0] hash_output_aa; hash_descending i_hash_dd(hash_input_d, hash_output_dd); hash_descending i_hash_da(hash_input_a, hash_output_da); hash_ascending i_hash_ad(hash_input_d, hash_output_ad); hash_ascending i_hash_aa(hash_input_a, hash_output_aa); assign in = 8'b10001110; /*verilator lint_off ASCRANGE*/ logic [7:0] [7:0] expc = {8'b10001110, 8'b01000111, 8'b10100011, 8'b11010001, 8'b11101000, 8'b01110100, 8'b00111010, 8'b00011101}; /*verilator lint_on ASCRANGE*/ always @(posedge clk) begin : always_block automatic bit failed = 0; automatic logic [8:0] hash_expected = hash_input_d[23:15] ^ hash_input_d[14:6]; $display("in:%b shift:%d expc:%b", in, shift, expc[7-shift]); for (int i = 0; i < NUMSUB; ++i) begin if (out[i] != expc[7-shift]) begin $display("Missmatch out[%d]:%b", i, out[i]); failed = 1; end end if (through_tmp != expc[7-shift]) begin $display("Missmatch through_tmp:%b", through_tmp); failed = 1; end if (hash_output_dd != hash_expected) begin $display("Missmatch hash_output_dd: in=0x%08x out=0x%02x expected=0x%02x", hash_input_d, hash_output_dd, hash_expected); failed = 1; end if (hash_output_da != hash_expected) begin $display("Missmatch hash_output_da: in=0x%08x out=0x%02x expected=0x%02x", hash_input_a, hash_output_da, hash_expected); failed = 1; end if (hash_output_ad != hash_expected) begin $display("Missmatch hash_output_ad: in=0x%08x out=0x%02x expected=0x%02x", hash_input_d, hash_output_ad, hash_expected); failed = 1; end if (hash_output_aa != hash_expected) begin $display("Missmatch hash_output_aa: in=0x%08x out=0x%02x expected=0x%02x", hash_input_a, hash_output_aa, hash_expected); failed = 1; end hash_input_d = {hash_input_d[ 1], hash_input_d[31:2]}; hash_input_a = {hash_input_a[31], hash_input_a[1:30]}; if (failed) $stop; if (shift == 7) begin $write("*-* All Finished *-*\n"); $finish; end shift <= shift + 1; end endmodule verilator-5.042/test_regress/t/t_randomize_union.py0000755000542200017500000000104615101701376023167 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_paramnodefault.v0000644000542200017500000000063215101701376023631 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module sub; parameter NODEF; //<--- Warning initial begin if (NODEF != 6) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module t; sub #(6) sub(); endmodule verilator-5.042/test_regress/t/t_mem_multi_ref_bad.out0000644000542200017500000000504515101701376023600 0ustar mahmoudyfreeshell%Error: t/t_mem_multi_ref_bad.v:15:11: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' : ... note: In instance 't' 15 | dimn[1:0] = 0; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Warning-SELRANGE: t/t_mem_multi_ref_bad.v:15:11: Extracting 2 bits from only 1 bit number : ... note: In instance 't' 15 | dimn[1:0] = 0; | ^ ... For warning description see https://verilator.org/warn/SELRANGE?v=latest ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Error: t/t_mem_multi_ref_bad.v:16:14: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' : ... note: In instance 't' 16 | dim0[1][1] = 0; | ^ %Warning-SELRANGE: t/t_mem_multi_ref_bad.v:16:14: Selection index out of range: 1:1 outside 0:0 : ... note: In instance 't' 16 | dim0[1][1] = 0; | ^ %Error: t/t_mem_multi_ref_bad.v:17:17: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' : ... note: In instance 't' 17 | dim1[1][1][1] = 0; | ^ %Warning-SELRANGE: t/t_mem_multi_ref_bad.v:17:17: Selection index out of range: 1:1 outside 0:0 : ... note: In instance 't' 17 | dim1[1][1][1] = 0; | ^ %Warning-SELRANGE: t/t_mem_multi_ref_bad.v:19:19: Selection index out of range: 1 outside 0:0 : ... note: In instance 't' 19 | dim2[0 +: 1][1] = 0; | ^ %Error: t/t_mem_multi_ref_bad.v:23:16: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' : ... note: In instance 't' 23 | dim0nv[1][1] = 0; | ^ %Warning-SELRANGE: t/t_mem_multi_ref_bad.v:23:16: Selection index out of range: 1:1 outside 0:0 : ... note: In instance 't' 23 | dim0nv[1][1] = 0; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_disable_empty.py0000755000542200017500000000103015101701376022601 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.lint(verilator_flags2=['--timing'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_trace_cat_fst__0100.out0000644000542200017500000000520015101701376023537 0ustar mahmoudyfreeshell$date Wed Feb 23 00:26:16 2022 $end $version fstWriter $end $timescale 1ps $end $scope module top $end $var wire 1 ! clk $end $scope module t $end $var wire 1 ! clk $end $var integer 32 " cyc [31:0] $end $var integer 32 # unchanged [31:0] $end $upscope $end $upscope $end $enddefinitions $end #100 $dumpvars b00000000000000000000000000101010 # b00000000000000000000000000110010 " 1! $end #101 0! #102 1! b00000000000000000000000000110011 " #103 0! #104 1! b00000000000000000000000000110100 " #105 0! #106 1! b00000000000000000000000000110101 " #107 0! #108 1! b00000000000000000000000000110110 " #109 0! #110 1! b00000000000000000000000000110111 " #111 0! #112 1! b00000000000000000000000000111000 " #113 0! #114 1! b00000000000000000000000000111001 " #115 0! #116 1! b00000000000000000000000000111010 " #117 0! #118 1! b00000000000000000000000000111011 " #119 0! #120 1! b00000000000000000000000000111100 " #121 0! #122 1! b00000000000000000000000000111101 " #123 0! #124 1! b00000000000000000000000000111110 " #125 0! #126 1! b00000000000000000000000000111111 " #127 0! #128 1! b00000000000000000000000001000000 " #129 0! #130 1! b00000000000000000000000001000001 " #131 0! #132 1! b00000000000000000000000001000010 " #133 0! #134 1! b00000000000000000000000001000011 " #135 0! #136 1! b00000000000000000000000001000100 " #137 0! #138 1! b00000000000000000000000001000101 " #139 0! #140 1! b00000000000000000000000001000110 " #141 0! #142 1! b00000000000000000000000001000111 " #143 0! #144 1! b00000000000000000000000001001000 " #145 0! #146 1! b00000000000000000000000001001001 " #147 0! #148 1! b00000000000000000000000001001010 " #149 0! #150 1! b00000000000000000000000001001011 " #151 0! #152 1! b00000000000000000000000001001100 " #153 0! #154 1! b00000000000000000000000001001101 " #155 0! #156 1! b00000000000000000000000001001110 " #157 0! #158 1! b00000000000000000000000001001111 " #159 0! #160 1! b00000000000000000000000001010000 " #161 0! #162 1! b00000000000000000000000001010001 " #163 0! #164 1! b00000000000000000000000001010010 " #165 0! #166 1! b00000000000000000000000001010011 " #167 0! #168 1! b00000000000000000000000001010100 " #169 0! #170 1! b00000000000000000000000001010101 " #171 0! #172 1! b00000000000000000000000001010110 " #173 0! #174 1! b00000000000000000000000001010111 " #175 0! #176 1! b00000000000000000000000001011000 " #177 0! #178 1! b00000000000000000000000001011001 " #179 0! #180 1! b00000000000000000000000001011010 " #181 0! #182 1! b00000000000000000000000001011011 " #183 0! #184 1! b00000000000000000000000001011100 " #185 0! #186 1! b00000000000000000000000001011101 " #187 0! #188 1! b00000000000000000000000001011110 " #189 0! verilator-5.042/test_regress/t/t_waiveroutput.vlt0000644000542200017500000000060515101701376022717 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `verilator_config lint_off -rule WIDTH -file "*t/t_waiveroutput.v" -match "Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CONST '2'h3' generates 2 bits." verilator-5.042/test_regress/t/t_pipe_filter_inc.vh0000644000542200017500000000050215101701376023100 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 inc line 6; inc line 7; // example_lint_off_line FOO inc line 8; // example_lint_off_line BAR inc line 9; verilator-5.042/test_regress/t/t_castdyn_castconst_bad.v0000644000542200017500000000100315101701376024126 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005-2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Base; endclass class Other; endclass enum { ZERO } e; module t; int i; int v; Base b; Other o; initial begin i = $cast(v, 1); // 1 i = $cast(b, b); // 1 i = $cast(b, o); // 0 i = $cast(e, 0); // 1 i = $cast(e, 10); // 0 end endmodule verilator-5.042/test_regress/t/t_lint_pinmissing_bad.v0000644000542200017500000000045715101701376023622 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; sub sub(); // <--- Warning endmodule module sub (output port); endmodule verilator-5.042/test_regress/t/t_func_const_packed_array_bad.out0000644000542200017500000000213715101701376025621 0ustar mahmoudyfreeshell%Warning-USERFATAL: "f_add = 15" ... For warning description see https://verilator.org/warn/USERFATAL?v=latest ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. %Error: t/t_func_const_packed_array_bad.v:12:21: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2' : ... note: In instance 't' t/t_func_const_packed_array_bad.v:23:9: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing t/t_func_const_packed_array_bad.v:31:16: ... Called from 'f_add()' with parameters: params = [0 = 32'h7, 1 = 32'h8] t/t_func_const_packed_array_bad.v:12:21: ... Called from 'f_add2()' with parameters: a = ?32?h7 b = ?32?h8 c = ?32?h9 12 | localparam P24 = f_add2(7, 8, 9); | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_dist_attributes_bad.py0000755000542200017500000000470215101701376024010 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import json import vltest_bootstrap test.scenarios('dist') def have_clang_check(): cmd = 'python3 -c "from clang.cindex import Index; index = Index.create(); print(\\"Clang imported\\")";' if test.verbose: print("\t" + cmd) nout = test.run_capture(cmd, check=False) if not nout or not re.search(r'Clang imported', nout): return False return True if 'VERILATOR_TEST_NO_ATTRIBUTES' in os.environ: test.skip("Skipping due to VERILATOR_TEST_NO_ATTRIBUTES") if not os.path.exists(test.root + "/.git"): test.skip("Not in a git repository") if not have_clang_check(): test.skip("No libclang installed") aroot = os.path.abspath(test.root) ccjson_file = test.obj_dir + "/compile_commands.json" aroot_dir = os.path.abspath(test.root) srcs_dir = os.path.abspath("./t/t_dist_attributes") common_args = [ "clang++", "-std=c++14", "-I" + aroot_dir + "/include", "-I" + aroot_dir + "/src", "-c" ] ccjson = [ { "directory": srcs_dir, "file": srcs_dir + "/mt_enabled.cpp", "output": srcs_dir + "/mt_enabled.o", "arguments": [*common_args, "-o", srcs_dir + "/mt_enabled.o", srcs_dir + "/mt_enabled.cpp"] }, { "directory": srcs_dir, "file": srcs_dir + "/mt_disabled.cpp", "output": srcs_dir + "/mt_disabled.o", "arguments": [*common_args, "-o", srcs_dir + "/mt_enabled.o", srcs_dir + "/mt_enabled.cpp"] }, ] ccjson_str = json.dumps(ccjson) srcfiles = [] for entry in ccjson: srcfiles.append(entry["file"]) srcfiles_str = ' '.join(srcfiles) test.write_wholefile(ccjson_file, ccjson_str) test.run( logfile=test.run_log_filename, tee=True, # With `--verilator-root` set to the current directory # (i.e. `test_regress`) the script will skip annotation issues in # headers from the `../include` directory. cmd=[ "python3", aroot + "/nodist/clang_check_attributes", "--verilator-root=.", "--compile-commands-dir=" + test.obj_dir, "--jobs=1", srcfiles_str ]) test.files_identical(test.run_log_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_vpi_public_depthn_2.py0000755000542200017500000000121515101701376023704 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_vpi_public_depthn.v" test.compile(verilator_flags2=['--public-depth 2']) test.execute() test.files_identical(test.run_log_filename, test.golden_filename, is_logfile=True, strip_hex=True) test.passes() verilator-5.042/test_regress/t/t_func_wide.py0000755000542200017500000000073415101701376021735 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_assert_disable_count.py0000755000542200017500000000077115101701376024167 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--assert']) test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_array_saif_threads_2.py0000755000542200017500000000141015101701376025213 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_trace_array.v" test.golden_filename = "t/t_trace_array_saif.out" test.compile( verilator_flags2=['--cc --trace-saif --trace-threads 2 --trace-structs --trace-max-width 0']) test.execute() # saif_identical is very slow, so require exact match test.files_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_parse_eof_qqq_bad.v0000644000542200017500000000033515101701376023234 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 """str verilator-5.042/test_regress/t/t_struct_pat_width.v0000644000542200017500000000165615101701376023177 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2016 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; typedef struct packed { logic [2:0] _foo; logic [2:0] _bar; } struct_t; logic [2:0] meh; struct_t param; localparam integer TWENTYONE = 21; // verilator lint_off WIDTH assign param = '{ _foo: TWENTYONE % 8 + 1, _bar: (TWENTYONE / 8) + 1 }; assign meh = TWENTYONE % 8 + 1; // verilator lint_on WIDTH always @ (posedge clk) begin `ifdef TEST_VERBOSE $display("param: %d, %d, %b, %d", param._foo, param._bar, param, meh); `endif if (param._foo != 6) $stop; if (param._bar != 3) $stop; if (param != 6'b110011) $stop; if (meh != 6) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_enum_recurse_bad.out0000644000542200017500000000074115101701376023446 0ustar mahmoudyfreeshell%Error: t/t_enum_recurse_bad.v:7:9: Recursive enum value: 'u' 7 | enum {u=u} e_t; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_enum_recurse_bad.v:7:9: Expecting expression to be constant, but enum value isn't const: 'u' 7 | enum {u=u} e_t; | ^ %Error: t/t_enum_recurse_bad.v:7:9: Enum value isn't a constant 7 | enum {u=u} e_t; | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_interface_localparam.out0000644000542200017500000000024715101701376024300 0ustar mahmoudyfreeshell*-* All Finished *-* top.t.intf: symbolsPerBeat 16, symbolsPerBeatDivBy2 8, mismatch 0 top.t.theCore.core_intf: symbolsPerBeat 64, symbolsPerBeatDivBy2 32, mismatch 0 verilator-5.042/test_regress/t/t_split_var_0.vlt0000644000542200017500000000041215101701376022357 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by Marco Widmer. // SPDX-License-Identifier: CC0-1.0 `verilator_config split_var -module "barshift_1d_unpacked" -var "tmp" verilator-5.042/test_regress/t/t_lint_caseincomplete_bad.py0000755000542200017500000000076615101701376024626 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_math_pow7.v0000644000542200017500000000152315101701376021506 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" `define stop $stop `ifdef VERILATOR `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) `else `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); end while(0) `endif module t (/*AUTOARG*/ // Outputs out_data ); output [11:0] out_data; wire [11:0] out_data; wire [11:0] a; wire [2:0] b; assign a = 12'h000 ** { b }; assign b = 3'b0; assign out_data = a; endmodule verilator-5.042/test_regress/t/t_randomize_unpacked_bad.out0000644000542200017500000000045515101701376024616 0ustar mahmoudyfreeshell%Error: t/t_randomize_unpacked_bad.v:8:9: Unpacked structs shall not be declared as randc (IEEE 1800-2023 18.4) 8 | randc struct {logic m_x;} s; | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_split_var_3_wreal.v0000644000542200017500000000234215101701376023220 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Yutetsu TAKATSUKASA. // SPDX-License-Identifier: CC0-1.0 `begin_keywords "VAMS-2.3" module t (/*autoarg*/ // Inputs clk ); input clk; integer cyc = 0; real vin[0:1] /*verilator split_var*/; wreal vout[0:1] /*verilator split_var*/; swap i_swap(.in0(vin[0]), .in1(vin[1]), .out0(vout[0]), .out1(vout[1])); always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==0) begin // Setup vin[0] = 1.0; vin[1] = 2.0; end else if (cyc==2) begin vin[0] = 3.0; vin[1] = 4.0; end else if (cyc==3) begin if (vout[0] == vin[1] && vout[1] == vin[0]) begin $write("*-* All Finished *-*\n"); $finish; end else begin $write("Mismatch %f %f\n", vout[0], vout[1]); $stop; end end end endmodule module swap (input wreal in0, in1, output wreal out0, out1); wreal tmp[0:1] /* verilator split_var*/; assign tmp[0] = in0; assign tmp[1] = in1; assign out0 = tmp[1]; assign out1 = tmp[0]; endmodule verilator-5.042/test_regress/t/t_enum_bad_cell.v0000644000542200017500000000056515101701376022357 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; sub s1(); endmodule module sub; enum {s0, s1} state; initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_inst_noname_bad.v0000644000542200017500000000042415101701376022720 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Anthony Donlon. // SPDX-License-Identifier: CC0-1.0 module t; m (); m (); endmodule module m; endmodule verilator-5.042/test_regress/t/t_force_select_bad.v0000644000542200017500000000163615101701376023051 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; wire array1[2:1]; wire [2:-1] vec; integer bad_index = 1; parameter P_ONE = 1; initial begin force array1[P_ONE] = 1'b1; // ok release array1[P_ONE]; // ok force vec[P_ONE+:1] = 1'b1; // ok release vec[P_ONE+:1]; // ok // IEEE 1800-2023 10.6.2 [A force] shall not be a bit-select or a // part-select of a [non-constant] variable or of a net with a user-defined // nettype. force array1[bad_index] = 1'b1; // <---- BAD not constant index release array1[bad_index]; // <---- BAD not constant index force vec[bad_index+:1] = 1'b1; // <---- BAD not constant index release vec[bad_index+:1]; // <---- BAD not constant index end endmodule verilator-5.042/test_regress/t/t_blocking.v0000644000542200017500000000441315101701376021372 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer _mode; initial _mode=0; reg [7:0] a; reg [7:0] b; reg [7:0] c; reg [7:0] mode_d1r; reg [7:0] mode_d2r; reg [7:0] mode_d3r; // surefire lint_off ITENST // surefire lint_off STMINI // surefire lint_off NBAJAM always @ (posedge clk) begin // filp-flops with asynchronous reset if (0) begin _mode <= 0; end else begin _mode <= _mode + 1; if (_mode==0) begin $write("[%0t] t_blocking: Running\n", $time); a <= 8'd0; b <= 8'd0; c <= 8'd0; end else if (_mode==1) begin if (a !== 8'd0) $stop; if (b !== 8'd0) $stop; if (c !== 8'd0) $stop; a <= b; b <= 8'd1; c <= b; if (a !== 8'd0) $stop; if (b !== 8'd0) $stop; if (c !== 8'd0) $stop; end else if (_mode==2) begin if (a !== 8'd0) $stop; if (b !== 8'd1) $stop; if (c !== 8'd0) $stop; a <= b; b <= 8'd2; c <= b; if (a !== 8'd0) $stop; if (b !== 8'd1) $stop; if (c !== 8'd0) $stop; end else if (_mode==3) begin if (a !== 8'd1) $stop; if (b !== 8'd2) $stop; if (c !== 8'd1) $stop; end else if (_mode==4) begin if (mode_d3r != 8'd1) $stop; $write("*-* All Finished *-*\n"); $finish; end end end always @ (posedge clk) begin mode_d3r <= mode_d2r; mode_d2r <= mode_d1r; mode_d1r <= _mode[7:0]; end reg [14:10] bits; // surefire lint_off SEQASS always @ (posedge clk) begin if (_mode==1) begin bits[14:13] <= 2'b11; bits[12] <= 1'b1; end if (_mode==2) begin bits[11:10] <= 2'b10; bits[13] <= 0; end if (_mode==3) begin if (bits !== 5'b10110) $stop; end end endmodule verilator-5.042/test_regress/t/vltest_bootstrap.py0000755000542200017500000000121315101701376023056 0ustar mahmoudyfreeshell# DESCRIPTION: Verilator: Verilog Test bootstrap loader # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import os import re import sys os.chdir(os.path.dirname(os.path.realpath(__file__)) + "/..") # Avoid chdir leaving the .. which confuses later commands os.environ['PWD'] = os.getcwd() args = list(map(lambda arg: re.sub(r'.*/test_regress/', '', arg), sys.argv)) os.execl("./driver.py", "driver.py", *args) verilator-5.042/test_regress/t/t_virtual_interface_member_trigger.py0000755000542200017500000000104115101701376026542 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.skip("Test is broken, see #6613") test.scenarios('simulator') test.compile(verilator_flags2=['--binary']) test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_iface_array_topmodule2.py0000755000542200017500000000070615101701376025436 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.042/test_regress/t/t_leak.py0000755000542200017500000000120115101701376020674 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename], make_flags=['CPPFLAGS_ADD=-DVL_NO_LEGACY']) test.execute() test.passes() verilator-5.042/test_regress/t/t_sys_writemem.gold6.mem0000644000542200017500000000020015101701376023642 0ustar mahmoudyfreeshell0000000 0000000 0000000 0000000 2540004 0000000 0000000 0000000 0000000 0000000 254000a 254000b 254000c 0000000 0000000 0000000 verilator-5.042/test_regress/t/t_pp_dupdef_pragma_bad.py0000755000542200017500000000076315101701376024077 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_func_grey.v0000644000542200017500000000313415101701376021562 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); // surefire lint_off _NETNM // surefire lint_off STMINI input clk; integer _mode; initial _mode = 0; wire [2:0] b3; reg [2:0] g3; wire [5:0] b6; reg [5:0] g6; t_func_grey2bin #(3) g2b3 (.b(b3), .g(g3)); t_func_grey2bin #(6) g2b6 (.b(b6), .g(g6)); always @ (posedge clk) begin if (_mode==0) begin _mode <= 1; g3 <= 3'b101; g6 <= 6'b110101; end else if (_mode==1) begin if (b3 !== 3'b110) $stop; if (b6 !== 6'b100110) $stop; _mode <= 2; $write("*-* All Finished *-*\n"); $finish; end end endmodule // Module gray2bin // convert an arbitrary width gray coded number to binary. The conversion // of a 4 bit gray (represented as "g") to binary ("b") would go as follows: // b[3] = ^g[3] = g[3] // b[2] = ^g[3:2] // b[1] = ^g[3:1] // b[0] = ^g[3:[SZ-1:0] cur0] module t_func_grey2bin (/*AUTOARG*/ // Outputs b, // Inputs g ); // surefire lint_off STMFOR parameter SZ = 5; output [SZ-1:0] b; input [SZ-1:0] g; /*AUTOREG*/ // Beginning of automatic regs (for this module's undeclared outputs) reg [SZ-1:0] b; // End of automatics integer i; always @(/*AUTOSENSE*/g) for (i=0; i> i); // surefire lint_off_line LATASS endmodule verilator-5.042/test_regress/t/t_trace_param_override.v0000644000542200017500000000076215101701376023762 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" module t #( parameter int POVERRODE = 16, parameter int PORIG = 16 ); initial begin $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); $dumpvars; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_flag_stats.py0000755000542200017500000000100315101701376022107 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(verilator_flags2=["--stats --stats-vars"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_event_fst.out0000644000542200017500000000147415101701376023323 0ustar mahmoudyfreeshell$date Tue Jun 10 19:02:19 2025 $end $version fstWriter $end $timescale 1ps $end $scope module t $end $var event 1 ! ev_test $end $var int 32 " i [31:0] $end $var bit 1 # toggle $end $var bit 1 $ clk $end $upscope $end $enddefinitions $end #0 $dumpvars 0$ 0# b00000000000000000000000000000000 " $end #10 b00000000000000000000000000000001 " 1$ #20 0$ #30 1$ b00000000000000000000000000000010 " #40 0$ #50 1$ b00000000000000000000000000000011 " #60 0$ #70 1$ b00000000000000000000000000000100 " #80 0$ #90 1$ b00000000000000000000000000000101 " #100 0$ #110 1$ b00000000000000000000000000000110 " 1# 1! #120 0$ #130 1$ b00000000000000000000000000000111 " #140 0$ #150 1$ b00000000000000000000000000001000 " #160 0$ #170 1$ b00000000000000000000000000001001 " #180 0$ #190 1$ b00000000000000000000000000001010 " #200 0$ #210 1$ verilator-5.042/test_regress/t/t_class_param_extends_static_member_function_access.v0000644000542200017500000000115115101701376031741 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Class1 #(type T); static function int get_p(); return 7; endfunction endclass class Class2 #(type T) extends Class1 #(T); static function int get_p2; return T::get_p(); endfunction endclass module t; initial begin typedef Class2#(Class1#(int)) Class; if (Class::get_p2() != Class1#(int)::get_p()) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_order_comboclkloop.py0000755000542200017500000000077115101701376023651 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["-fno-dfg"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_fuzz_negwidth_bad.py0000755000542200017500000000076615101701376023474 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_net_delay.v0000644000542200017500000000302215101701376021541 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module t; // verilator lint_off UNOPTFLAT // verilator lint_off PROCASSINIT logic clk = 0; // verilator lint_on UNOPTFLAT // verilator lint_on PROCASSINIT always #2 clk = ~clk; // verilator lint_off UNDRIVEN wire[3:0] x; // verilator lint_on UNDRIVEN bit [3:0] cyc; wire[3:0] #3 val1; wire[3:0] #3 val2; wire[3:0] #5 val3 = cyc; wire[3:0] #5 val4; wire[3:0] #3 val5 = x, val6 = cyc; assign val1 = cyc; assign #3 val2 = cyc; assign val4 = cyc; assign val5 = cyc; always @(posedge clk) begin if ($time > 0) cyc <= cyc + 1; if (cyc == 15) begin $write("*-* All Finished *-*\n"); $finish; end end always @(posedge clk) #1 begin `ifdef TEST_VERBOSE $display("[%0t] cyc=%0d val1=%0d val2=%0d val3=%0d val4=%0d val5=%0d val6=%0d", $time, cyc, val1, val2, val3, val4, val5, val6); `endif if (cyc >= 3) begin `checkh(val1, cyc - 1); `checkh(val2, cyc - 2); `checkh(val3, 0); `checkh(val4, 0); `checkh(val5, cyc); `checkh(val6, cyc - 1); end end endmodule verilator-5.042/test_regress/t/t_package_export_bad.out0000644000542200017500000000325515101701376023751 0ustar mahmoudyfreeshell%Error: t/t_package_export.v:45:17: Export object not found: 'pkg1::BAD_DOES_NOT_EXIST' 45 | export pkg1::BAD_DOES_NOT_EXIST; | ^~~~~~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_package_export.v:56:16: Can't find definition of scope/variable/func: 'PARAM2' : ... Suggested alternative: 'PARAM1' 56 | reg [pkg11::PARAM2 : 0] bus12; | ^~~~~~ %Error: t/t_package_export.v:57:16: Can't find definition of scope/variable/func: 'PARAM3' : ... Suggested alternative: 'PARAM1' 57 | reg [pkg11::PARAM3 : 0] bus13; | ^~~~~~ %Error: t/t_package_export.v:60:16: Can't find definition of scope/variable/func: 'PARAM2' : ... Suggested alternative: 'PARAM1' 60 | reg [pkg21::PARAM2 : 0] bus22; | ^~~~~~ %Error: t/t_package_export.v:61:16: Can't find definition of scope/variable/func: 'PARAM3' : ... Suggested alternative: 'PARAM1' 61 | reg [pkg21::PARAM3 : 0] bus23; | ^~~~~~ %Error: t/t_package_export.v:64:16: Can't find definition of scope/variable/func: 'PARAM2' : ... Suggested alternative: 'PARAM1' 64 | reg [pkg31::PARAM2 : 0] bus32; | ^~~~~~ %Error: t/t_package_export.v:65:16: Can't find definition of scope/variable/func: 'PARAM3' : ... Suggested alternative: 'PARAM1' 65 | reg [pkg31::PARAM3 : 0] bus33; | ^~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_func_public.py0000755000542200017500000000101715101701376022256 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['+define+VERILATOR_PUBLIC_TASKS']) test.execute() test.passes() verilator-5.042/test_regress/t/t_castdyn_castconst_bad.out0000644000542200017500000000230415101701376024475 0ustar mahmoudyfreeshell%Warning-CASTCONST: t/t_castdyn_castconst_bad.v:20:11: $cast will always return one as 'int' is always castable from 'logic[31:0]' : ... note: In instance 't' : ... Suggest static cast 20 | i = $cast(v, 1); | ^~~~~ ... For warning description see https://verilator.org/warn/CASTCONST?v=latest ... Use "/* verilator lint_off CASTCONST */" and lint_on around source to disable this message. %Warning-CASTCONST: t/t_castdyn_castconst_bad.v:21:11: $cast will always return one as 'class{}Base' is always castable from 'class{}Base' : ... note: In instance 't' : ... Suggest static cast 21 | i = $cast(b, b); | ^~~~~ %Warning-CASTCONST: t/t_castdyn_castconst_bad.v:22:11: $cast will always return zero as 'class{}Base' is not castable from 'class{}Other' : ... note: In instance 't' 22 | i = $cast(b, o); | ^~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_mod_recurse1.v0000644000542200017500000000127415101701376022174 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Sean Moore. // SPDX-License-Identifier: CC0-1.0 module t; rec rec (); endmodule module rec; parameter DEPTH = 1; generate if (DEPTH==1) begin rec #(.DEPTH(DEPTH+1)) sub(); end else if (DEPTH==2) begin rec #(.DEPTH(DEPTH+1)) subb(); end else if (DEPTH==3) begin bottom #(.DEPTH(DEPTH+1)) bot(); end endgenerate endmodule module bottom; parameter DEPTH = 1; initial begin if (DEPTH!=4) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_trace_split_cfuncs.v0000644000542200017500000000047415101701376023457 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Varun Koyyalagunta. // SPDX-License-Identifier: CC0-1.0 module t (); initial begin $dumpfile("dump.vcd"); $dumpvars(); end endmodule verilator-5.042/test_regress/t/t_process_bad.v0000644000542200017500000000067715101701376022076 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; process p; initial begin if (p != null) $stop; p = process::self(); if (p.bad_method() != 0) $stop; p.bad_method_2(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_clk_first_deprecated.py0000755000542200017500000000076615101701376024137 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--lint-only", "-Wno-DEPRECATED"]) test.passes() verilator-5.042/test_regress/t/t_select_bound2.py0000755000542200017500000000073415101701376022522 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_inst_name_long.py0000755000542200017500000000070615101701376022765 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.passes() verilator-5.042/test_regress/t/t_struct_unpacked_clean.py0000755000542200017500000000104415101701376024325 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--x-assign unique --x-initial unique -Wno-WIDTH -O0"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_opt_localize_max_size.v0000644000542200017500000000061715101701376024167 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2016 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; int x; initial begin x = $c32(1); $display(x); x = $c32(2); $display(x); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_clk_powerdn.v0000644000542200017500000000676015101701376022120 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg reset_l; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) // End of automatics reg clkgate_e2r; reg clkgate_e1r_l; always @(posedge clk or negedge reset_l) begin if (!reset_l) begin clkgate_e1r_l <= ~1'b1; end else begin clkgate_e1r_l <= ~clkgate_e2r; end end reg clkgate_e1f; always @(negedge clk) begin // Yes, it's really a = clkgate_e1f = ~clkgate_e1r_l | ~reset_l; end wire clkgated = clk & clkgate_e1f; reg [31:0] countgated; always @(posedge clkgated or negedge reset_l) begin if (!reset_l) begin countgated <= 32'h1000; end else begin countgated <= countgated + 32'd1; end end reg [31:0] count; always @(posedge clk or negedge reset_l) begin if (!reset_l) begin count <= 32'h1000; end else begin count <= count + 32'd1; end end reg [7:0] cyc; initial cyc = 0; always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] rs %x cyc %d cg1f %x cnt %x cg %x\n", $time,reset_l,cyc,clkgate_e1f,count,countgated); `endif cyc <= cyc + 8'd1; case (cyc) 8'd00: begin reset_l <= ~1'b0; clkgate_e2r <= 1'b1; end 8'd01: begin reset_l <= ~1'b0; end 8'd02: begin end 8'd03: begin reset_l <= ~1'b1; // Need a posedge end 8'd04: begin end 8'd05: begin reset_l <= ~1'b0; end 8'd09: begin clkgate_e2r <= 1'b0; end 8'd11: begin clkgate_e2r <= 1'b1; end 8'd20: begin $write("*-* All Finished *-*\n"); $finish; end default: ; endcase case (cyc) 8'd00: ; 8'd01: ; 8'd02: ; 8'd03: ; 8'd04: if (count!=32'h00001000 || countgated!=32'h 00001000) $stop; 8'd05: if (count!=32'h00001000 || countgated!=32'h 00001000) $stop; 8'd06: if (count!=32'h00001000 || countgated!=32'h 00001000) $stop; 8'd07: if (count!=32'h00001001 || countgated!=32'h 00001001) $stop; 8'd08: if (count!=32'h00001002 || countgated!=32'h 00001002) $stop; 8'd09: if (count!=32'h00001003 || countgated!=32'h 00001003) $stop; 8'd10: if (count!=32'h00001004 || countgated!=32'h 00001004) $stop; 8'd11: if (count!=32'h00001005 || countgated!=32'h 00001005) $stop; 8'd12: if (count!=32'h00001006 || countgated!=32'h 00001005) $stop; 8'd13: if (count!=32'h00001007 || countgated!=32'h 00001005) $stop; 8'd14: if (count!=32'h00001008 || countgated!=32'h 00001006) $stop; 8'd15: if (count!=32'h00001009 || countgated!=32'h 00001007) $stop; 8'd16: if (count!=32'h0000100a || countgated!=32'h 00001008) $stop; 8'd17: if (count!=32'h0000100b || countgated!=32'h 00001009) $stop; 8'd18: if (count!=32'h0000100c || countgated!=32'h 0000100a) $stop; 8'd19: if (count!=32'h0000100d || countgated!=32'h 0000100b) $stop; 8'd20: if (count!=32'h0000100e || countgated!=32'h 0000100c) $stop; default: $stop; endcase end endmodule verilator-5.042/test_regress/t/t_class_param_upcast.py0000755000542200017500000000071415101701376023634 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.passes() verilator-5.042/test_regress/t/t_assert_iff_clk_unsup.py0000755000542200017500000000102215101701376024171 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert'], fails=True) test.passes() verilator-5.042/test_regress/t/t_class_new_noparen.v0000644000542200017500000000167415101701376023310 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class u_object; string m_name; function new(string name); m_name = name; endfunction endclass class u_cache#(type KEY_T=int, type DATA_T=int) extends u_object; typedef int unsigned size_t; int m_max_size; extern function new(string name="u_cache", size_t max_size = 256); endclass // #() not required below, see IEEE 1800-2023 8.25.1 function u_cache::new(string name="u_cache", u_cache::size_t max_size = 256); super.new(name); this.m_max_size = max_size; endfunction module t; u_cache #(real, real) obj; initial begin obj = new("fred", 62); if (obj.m_name != "fred") $stop; if (obj.m_max_size != 62) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_interface_gen8.py0000755000542200017500000000073415101701376022653 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_func_dotted_inl1.vlt0000644000542200017500000000041515101701376023361 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. // SPDX-License-Identifier: CC0-1.0 `verilator_config inline -module "global_mod" inline -module "m*" verilator-5.042/test_regress/t/t_flag_suggest.out0000644000542200017500000000404115101701376022613 0ustar mahmoudyfreeshell%Error: Invalid option: -ccc... Suggested alternative: '-cc' ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Invalid option: --ccc... Suggested alternative: '-cc' ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Invalid option: -no-asserT... Suggested alternative: '-no-assert' ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Invalid option: -noasserT... Suggested alternative: '-no-assert' ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Invalid option: -asserT... Suggested alternative: '-assert' ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Invalid option: +definE+A=B... Suggested alternative: '+define+' ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Invalid option: -CFLAGs... Suggested alternative: '-CFLAGS' ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Invalid option: -debug-aborT ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Invalid option: -Won-SPLITVAR... Suggested alternative: '-Wno-SPLITVAR' ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Unknown warning specified: -Wno-SPLITVER... Suggested alternative: '-Wno-SPLITVAR' ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Unknown language specified: 1364-1997... Suggested alternative: '1364-1995' ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: verilator: No Input Verilog file specified on command line, see verilator --help for more information ... This fatal error may be caused by the earlier error(s); resolve those first. verilator-5.042/test_regress/t/t_config_param.v0000644000542200017500000000135215101701376022226 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module m1; parameter string P1 = "p1.unchanged"; parameter string P2 = "p2.unchanged"; initial $display("m1 %%m=%m %%l=%l P1=%s P2=%s", P1, P2); endmodule module t; m1 u_1a(); m1 u_1b(); m1 u_1c(); final $write("*-* All Finished *-*\n"); endmodule config cfg1; localparam P1 = "cfg.p1"; localparam P2 = "cfg.p2"; design t; instance t.u_1a use #(.P1(), .P2("override.u_a.p2")); instance t.u_1b use #(); // All parameters back to default instance t.u_1c use #(.P1(P1), .P2(P2)); endconfig verilator-5.042/test_regress/t/t_covergroup_with_sample_namedargs.v0000644000542200017500000000066415101701376026416 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off COVERIGN */ module t; covergroup cgN with function sample (int addr, bit is_read); endgroup cgN cov = new(); function void run(); cov.sample(.addr(11), .is_read(1'b1)); endfunction endmodule verilator-5.042/test_regress/t/t_preproc_defines.out0000644000542200017500000006444415101701376023325 0ustar mahmoudyfreeshell`line 0 "" 0 `define TEST_OBJ_DIR obj_vlt/t_preproc_defines `define TEST_DUMPFILE obj_vlt/t_preproc_defines/simx.vcd `line 1 "t/t_preproc.v" 1 `line 1 "t/t_preproc.v" 0 `line 6 "t/t_preproc.v" 0 `line 8 "t/t_preproc.v" 0 `line 10 "t/t_preproc.v" 0 `line 1 "t/t_preproc_inc2.vh" 1 `line 2 "t/t_preproc_inc2.vh" 0 At file "t/t_preproc_inc2.vh" line 5 `define INCFILE `line 7 "t/t_preproc_inc2.vh" 0 `line 7 "t/t_preproc_inc2.vh" 0 `line 1 "t/t_preproc_inc3.vh" 1 `line 2 "t/t_preproc_inc3.vh" 0 `line 6 "t/t_preproc_inc3.vh" 0 `define _EXAMPLE_INC2_V_ 1 `line 8 "t/t_preproc_inc3.vh" 0 `define _EMPTY `line 9 "t/t_preproc_inc3.vh" 0 At file "t/t_preproc_inc3.vh" line 10 `line 12 "inc3_a_filename_from_line_directive_with_LINE" 0 At file "inc3_a_filename_from_line_directive_with_LINE" line 12 `line 100 "inc3_a_filename_from_line_directive" 0 At file "inc3_a_filename_from_line_directive" line 100 `line 103 "inc3_a_filename_from_line_directive" 0 `line 106 "inc3_a_filename_from_line_directive" 0 `line 110 "inc3_a_filename_from_line_directive" 0 `line 7 "t/t_preproc_inc2.vh" 2 `line 9 "t/t_preproc_inc2.vh" 0 `line 10 "t/t_preproc.v" 2 `line 12 "t/t_preproc.v" 0 `line 15 "t/t_preproc.v" 0 /*verilator pass_thru comment*/ `line 17 "t/t_preproc.v" 0 /*verilator pass_thru_comment2*/ `line 19 "t/t_preproc.v" 0 `line 22 "t/t_preproc.v" 0 `define DEF_A3 `line 23 "t/t_preproc.v" 0 `define DEF_A1 `line 24 "t/t_preproc.v" 0 wire [3:0] q = { 1'b1 , 1'b0 , 1'b1 , 1'b1 }; `line 32 "t/t_preproc.v" 0 text. `line 34 "t/t_preproc.v" 0 `define FOOBAR foo /*this */ bar /* this too */ `line 35 "t/t_preproc.v" 0 `define FOOBAR2 foobar2 `line 36 "t/t_preproc.v" 0 foo bar foobar2 `line 39 "t/t_preproc.v" 0 `define MULTILINE first part \ second part \ third part `line 43 "t/t_preproc.v" 0 `line 43 "t/t_preproc.v" 0 `define MOREMULTILINE {\ a,\ b,\ c} `line 48 "t/t_preproc.v" 0 `line 48 "t/t_preproc.v" 0 first part `line 49 "t/t_preproc.v" 0 second part `line 49 "t/t_preproc.v" 0 third part { `line 50 "t/t_preproc.v" 0 a, `line 50 "t/t_preproc.v" 0 b, `line 50 "t/t_preproc.v" 0 c} Line_Preproc_Check 51 `line 53 "t/t_preproc.v" 0 `line 55 "t/t_preproc.v" 0 `define syn_negedge_reset_l or negedge reset_l `line 57 "t/t_preproc.v" 0 `define DEEP deep `line 58 "t/t_preproc.v" 0 `define DEEPER `DEEP `DEEP `line 59 "t/t_preproc.v" 0 deep deep `line 61 "t/t_preproc.v" 0 `define nosubst NOT_SUBSTITUTED `line 62 "t/t_preproc.v" 0 `define WITHTICK "`nosubst" `line 63 "t/t_preproc.v" 0 "Inside: `nosubst" "`nosubst" `line 66 "t/t_preproc.v" 0 `define withparam(a, b) a b LLZZ a b `line 67 "t/t_preproc.v" 0 x y LLZZ x y p q LLZZ p q r s LLZZ r s LLZZ p q LLZZ p q r s LLZZ r s `line 72 "t/t_preproc.v" 0 firstline comma","line LLZZ firstline comma","line `line 74 "t/t_preproc.v" 0 `define withquote(a, bar) a bar LLZZ "a" bar `line 75 "t/t_preproc.v" 0 x y LLZZ "a" y `line 77 "t/t_preproc.v" 0 `define noparam (a,b) `line 78 "t/t_preproc.v" 0 (a,b)(a,b) `line 80 "t/t_preproc.v" 0 `define msg(x,y) `"x: `\`"y`\`"`" `line 81 "t/t_preproc.v" 0 $display("left side: \"right side\"") `line 83 "t/t_preproc.v" 0 `define foo(f) f``_suffix `line 84 "t/t_preproc.v" 0 bar_suffix more `line 86 "t/t_preproc.v" 0 `define with_space_before_suffix(f) f`` suffix_after_space `line 87 "t/t_preproc.v" 0 arg suffix_after_space `line 89 "t/t_preproc.v" 0 `define zap(which) \ $c("Zap(\"",which,"\");"); `line 91 "t/t_preproc.v" 0 `line 91 "t/t_preproc.v" 0 $c("Zap(\"",bug1,"\");");; `line 92 "t/t_preproc.v" 0 $c("Zap(\"","bug2","\");");; `line 94 "t/t_preproc.v" 0 `line 97 "t/t_preproc.v" 0 `line 100 "t/t_preproc.v" 0 `define ls left_side `line 101 "t/t_preproc.v" 0 `define rs right_side `line 102 "t/t_preproc.v" 0 `define noarg na `line 103 "t/t_preproc.v" 0 `define thru(x) x `line 104 "t/t_preproc.v" 0 `define thruthru `ls `rs `line 105 "t/t_preproc.v" 0 `define msg(x,y) `"x: `\`"y`\`"`" `undef msg `line 106 "t/t_preproc.v" 0 initial begin $display("pre thrupre thrumid thrupost post: \"right side\""); $display("left side: \"right side\""); $display("left side: \"right side\""); $display("left_side: \"right_side\""); $display("na: \"right_side\""); $display("prep ( midp1 left_side midp2 ( outp ) ): \"right_side\""); $display("na: \"nana\""); $display("left_side right_side: \"left_side right_side\""); $display(": \"\""); $display("left side: \"right side\""); $display("left side: \"right side\""); $display("standalone"); `line 121 "t/t_preproc.v" 0 `define twoline first \ second `line 124 "t/t_preproc.v" 0 $display("twoline: \"first second\""); $write("*-* All Finished *-*\n"); $finish; end endmodule `line 131 "t/t_preproc.v" 0 `line 134 "t/t_preproc.v" 0 `define ADD_UP(a,c) \ wire tmp_``a = a; \ wire tmp_``c = tmp_``a + 1; \ assign c = tmp_``c ; `line 139 "t/t_preproc.v" 0 `line 139 "t/t_preproc.v" 0 module add1 ( input wire d1, output wire o1); `line 140 "t/t_preproc.v" 0 wire tmp_d1 = d1; `line 140 "t/t_preproc.v" 0 wire tmp_o1 = tmp_d1 + 1; `line 140 "t/t_preproc.v" 0 assign o1 = tmp_o1 ; endmodule module add2 ( input wire d2, output wire o2); `line 143 "t/t_preproc.v" 0 wire tmp_d2 = d2; `line 143 "t/t_preproc.v" 0 wire tmp_o2 = tmp_d2 + 1; `line 143 "t/t_preproc.v" 0 assign o2 = tmp_o2 ; endmodule `line 146 "t/t_preproc.v" 0 `define check(mod, width, flopname, gate, path) \ generate for (i=0; i<(width); i=i+1) begin \ psl cover { path.d[i] & ~path.q[i] & !path.cond & (gate)} report `"fondNoRise: mod.flopname`"; \ psl cover { ~path.d[i] & path.q[i] & !path.cond & (gate)} report `"fondNoFall: mod.flopname`"; \ end endgenerate `line 152 "t/t_preproc.v" 0 `line 152 "t/t_preproc.v" 0 `define MK m5k.f `line 154 "t/t_preproc.v" 0 `define MF `MK .ctl `line 155 "t/t_preproc.v" 0 `define CK_fr (`MF.alive & `MF.alive_m1) `line 157 "t/t_preproc.v" 0 `line 157 "t/t_preproc.v" 0 generate for (i=0; i<(3); i=i+1) begin `line 157 "t/t_preproc.v" 0 psl cover { m5k.f .ctl._ctl_mvldx_m1.d[i] & ~m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoRise: m5kc_fcl._ctl_mvldx_m1"; `line 157 "t/t_preproc.v" 0 psl cover { ~m5k.f .ctl._ctl_mvldx_m1.d[i] & m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoFall: m5kc_fcl._ctl_mvldx_m1"; `line 157 "t/t_preproc.v" 0 end endgenerate `line 159 "t/t_preproc.v" 0 module prot(); `protected I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl) #nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk] `line 165 "t/t_preproc.v" 0 `endprotected endmodule `line 169 "t/t_preproc.v" 0 module t_lint_pragma_protected; `line 173 "t/t_preproc.v" 0 `pragma protect begin_protected `pragma protect version=1 `pragma protect encrypt_agent="XXXXX" `pragma protect encrypt_agent_info="YYYYY" `pragma protect data_method="AES128-CBC" `pragma protect key_keyowner="BIG3#1" `pragma protect key_keyname="AAAAAA" `pragma protect key_method="RSA" `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `pragma protect key_block ICAgICAgICAgICAgICAgICAgIEdOVSBMRVNTRVIgR0VORVJBTCBQVUJMSUMgTElDRU5TRQogICAg KSAyMDA3IE== `line 186 "t/t_preproc.v" 0 `pragma protect key_keyowner="BIG3#2" `pragma protect key_keyname="BBBBBB" `pragma protect key_method="RSA" `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `pragma protect key_block IEV2ZXJ5b25lIGlzIHBlcm1pdHRlZCB0byBjb3B5IGFuZCBkaXN0cmlidXRlIHZlcmJhdGltIGNv cGllcwogb2YgdGhpcyBsaWNlbnNlIGRvY3VtZW50LCBidXQgY2hhbmdpbmcgaXQgaXMgbm90IGFs bG93ZWQuCgoKICBUaGl= `line 195 "t/t_preproc.v" 0 `pragma protect key_keyowner="BIG3#3" `pragma protect key_keyname="CCCCCCCC" `pragma protect key_method="RSA" `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `pragma protect key_block TGljZW5zZSBpbmNvcnBvcmF0ZXMKdGhlIHRlcm1zIGFuZCBjb25kaXRpb25zIG9mIHZlcnNpb24g MyBvZiB0aGUgR05VIEdlbmVyYWwgUHVibGljCkxpY2Vuc2UsIHN1cHBsZW1lbnRlZCBieSB0aGUg YWRkaXRpb25hbCBwZXJ= `line 204 "t/t_preproc.v" 0 `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 295) `pragma protect data_block aW5pdGlvbnMuCgogIEFzIHVzZWQgaGVyZWluLCAidGhpcyBMaWNlbnNlIiByZWZlcnMgdG8gdmVy c2lvbiAzIG9mIHRoZSBHTlUgTGVzc2VyCkdlbmVyYWwgUHVibGljIExpY2Vuc2UsIGFuZCB0aGUg IkdOVSBHUEwiIHJlZmVycyB0byB2ZXJzaW9uIDMgb2YgdGhlIEdOVQpHZW5lcmFsIFB1YmxpYyBM aWNlbnNlLgoKICAiVGhlIExpYnJhcnkiIHJlZmVycyB0byBhIGNvdmVyZWQgd29yayBnb3Zlcm5l ZCBieSB0aGlzIExpY2Vuc2UsCm90aGVyIHRoYW4gYW4gQXBwbGljYXRpb24gb3IgYSBDb21iaW5l ZCBXb3JrIGFzIG== `line 214 "t/t_preproc.v" 0 `pragma protect end_protected `line 216 "t/t_preproc.v" 0 `pragma protect `pragma protect end `line 220 "t/t_preproc.v" 0 endmodule `line 222 "t/t_preproc.v" 0 `define REG_H 6 `line 225 "t/t_preproc.v" 0 `define REG_L 7 `line 226 "t/t_preproc.v" 0 `define _H regs[`REG_H] `line 227 "t/t_preproc.v" 0 `define _L regs[`REG_L] `line 228 "t/t_preproc.v" 0 `define _HL {`_H, `_L} `line 229 "t/t_preproc.v" 0 `define EX_WRITE(ad, da) begin addr <= (ad); wdata <= (da); wr <= 1; end `line 230 "t/t_preproc.v" 0 `define EX_READ(ad) begin addr <= (ad); rd <= 1; end `line 232 "t/t_preproc.v" 0 begin addr <= (({regs[6], regs[7]} + 1)); rd <= 1; end and begin addr <= (({regs[6], regs[7]})); wdata <= (rdata); wr <= 1; end begin addr <= ({regs[6], regs[7]} + 1); rd <= 1; end begin addr <= ({regs[6], regs[7]}); wdata <= (rdata); wr <= 1; end more `line 236 "t/t_preproc.v" 0 `define INCNAME "t_preproc_inc4.vh" `line 239 "t/t_preproc.v" 0 `line 239 "t/t_preproc.v" 0 `line 1 "t/t_preproc_inc4.vh" 1 `line 2 "t/t_preproc_inc4.vh" 0 `line 6 "t/t_preproc_inc4.vh" 0 `define T_PREPROC_INC4 `line 8 "t/t_preproc_inc4.vh" 0 `line 239 "t/t_preproc.v" 2 `line 240 "t/t_preproc.v" 0 `line 243 "t/t_preproc.v" 0 `undef T_PREPROC_INC4 `line 245 "t/t_preproc.v" 0 `line 249 "t/t_preproc.v" 0 `line 252 "t/t_preproc.v" 0 `define xxerror(logfile, msg) $blah(logfile,msg) `line 253 "t/t_preproc.v" 0 $blah("ab,cd","e,f"); $blah(this.logfile,vec); $blah(this.logfile,vec[1,2,3]); $blah(this.logfile,{blah.name(), " is not foo"}); `line 258 "t/t_preproc.v" 0 `line 261 "t/t_preproc.v" 0 `pragma foo = 1 `default_nettype none `default_nettype uwire `line 265 "t/t_preproc.v" 0 `line 268 "t/t_preproc.v" 0 `define EMPTY_TRUE `line 269 "t/t_preproc.v" 0 `line 272 "t/t_preproc.v" 0 Line_Preproc_Check 272 `line 274 "t/t_preproc.v" 0 `line 277 "t/t_preproc.v" 0 `define ARGPAR(a, b ) (a,b) `line 280 "t/t_preproc.v" 0 (p,q) `line 284 "t/t_preproc.v" 0 (x,y) Line_Preproc_Check 285 `line 287 "t/t_preproc.v" 0 `line 290 "t/t_preproc.v" 0 `define BEGIN begin `line 291 "t/t_preproc.v" 0 `define END end `line 292 "t/t_preproc.v" 0 `define BEGINEND `BEGIN`END `line 293 "t/t_preproc.v" 0 `define quoteit(x) `"x`" `line 294 "t/t_preproc.v" 0 beginend beginend "beginend" `line 298 "t/t_preproc.v" 0 `define \esc`def got_escaped `line 301 "t/t_preproc.v" 0 `\esc`def `line 304 "t/t_preproc.v" 0 Not a \`define `line 306 "t/t_preproc.v" 0 `define sb bee `line 309 "t/t_preproc.v" 0 `define appease_emacs_paren_matcher ( `line 310 "t/t_preproc.v" 0 `define sa(l) x,y) `line 311 "t/t_preproc.v" 0 `define sfoo(q,r) q--r `line 312 "t/t_preproc.v" 0 x,y)--bee submacro has comma paren `line 314 "t/t_preproc.v" 0 `define bug191(bits) $display("bits %d %d", $bits(foo), bits); `line 317 "t/t_preproc.v" 0 $display("bits %d %d", $bits(foo), 10); `line 319 "t/t_preproc.v" 0 `define UDALL `line 322 "t/t_preproc.v" 0 `undefineall `line 324 "t/t_preproc.v" 0 `line 327 "t/t_preproc.v" 0 `define FC_INV3(out, in) \ `ifdef DC \ cell \inv_``out <$typeof(out)> (.a(), .o()); \ /* multi-line comment \ multi-line comment */ \ `else \ `ifdef MACRO_ATTRIBUTE \ (* macro_attribute = `"INV (out``,in``)`" *) \ `endif \ assign out = ~in ; \ `endif `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 `line 341 "t/t_preproc.v" 0 assign a3 = ~b3 ; `line 341 "t/t_preproc.v" 0 `line 343 "t/t_preproc.v" 0 \ `define bug202( i \ ) \ /* multi \ line 3*/ \ def i \ `line 352 "t/t_preproc.v" 0 `line 352 "t/t_preproc.v" 0 `line 352 "t/t_preproc.v" 0 `line 352 "t/t_preproc.v" 0 def i `line 354 "t/t_preproc.v" 0 `line 356 "t/t_preproc.v" 0 `define CMT1 /*verilator NOT IN DEFINE*/ `line 357 "t/t_preproc.v" 0 `define CMT2 /* verilator PART OF DEFINE */ `line 358 "t/t_preproc.v" 0 `line 360 "t/t_preproc.v" 0 `define CMT3 /*verilator NOT PART\ OF DEFINE*/ `line 360 "t/t_preproc.v" 0 `define CMT4 /* verilator PART \ OF DEFINE */ `line 362 "t/t_preproc.v" 0 `define CMT5 also in \ also3 `line 366 "t/t_preproc.v" 0 `line 366 "t/t_preproc.v" 0 1 /*verilator NOT IN DEFINE*/ (nodef) 2 /*verilator PART OF DEFINE*/ (hasdef) 3 `line 368 "t/t_preproc.v" 0 /*verilator NOT PART OF DEFINE*/ (nodef) `line 369 "t/t_preproc.v" 0 4 `line 369 "t/t_preproc.v" 0 /*verilator PART OF DEFINE*/ (nodef) `line 370 "t/t_preproc.v" 0 5 also in `line 370 "t/t_preproc.v" 0 also3 (nodef) `define NL HAS a NEW \ LINE `line 373 "t/t_preproc.v" 0 HAS a NEW `line 373 "t/t_preproc.v" 0 LINE `line 375 "t/t_preproc.v" 0 `line 377 "t/t_preproc.v" 0 `define msg_fatal(log, msg) \ do \ /* synopsys translate_off */ \ `ifdef NEVER \ `error "WTF" \ `else \ if (start(`__FILE__, `__LINE__)) begin \ `endif \ message(msg); \ end \ /* synopsys translate_on */ \ while(0) `line 390 "t/t_preproc.v" 0 `line 390 "t/t_preproc.v" 0 `define msg_scen_(cl) cl``_scen `line 391 "t/t_preproc.v" 0 `define MSG_MACRO_TO_STRING(x) `"x`" `line 393 "t/t_preproc.v" 0 EXP: clxx_scen clxx_scen EXP: clxx_scen "clxx_scen" `define mf(clx) `msg_fatal(this.log, {"Blah-", `MSG_MACRO_TO_STRING(`msg_scen_(clx)), " end"}); `line 398 "t/t_preproc.v" 0 EXP: do if (start("verilog/inc1.v", 25)) begin message({"Blah-", "clx_scen", " end"}); end while(0); `line 399 "t/t_preproc.v" 0 do `line 399 "t/t_preproc.v" 0 `line 399 "t/t_preproc.v" 0 `line 399 "t/t_preproc.v" 0 `line 399 "t/t_preproc.v" 0 `line 399 "t/t_preproc.v" 0 if (start("t/t_preproc.v", 399)) begin `line 399 "t/t_preproc.v" 0 `line 399 "t/t_preproc.v" 0 message({"Blah-", "clx_scen", " end"}); `line 399 "t/t_preproc.v" 0 end `line 399 "t/t_preproc.v" 0 `line 399 "t/t_preproc.v" 0 while(0); `line 401 "t/t_preproc.v" 0 `line 403 "t/t_preproc.v" 0 `define makedefine(name) \ `define def_``name This is name \ `define def_``name``_2 This is name``_2 \ `line 407 "t/t_preproc.v" 0 `line 407 "t/t_preproc.v" 0 `line 407 "t/t_preproc.v" 0 `define def_fooed This is fooed `line 407 "t/t_preproc.v" 0 `line 407 "t/t_preproc.v" 0 `define def_fooed_2 This is fooed``_2 `line 408 "t/t_preproc.v" 0 EXP: This is fooed This is fooed EXP: This is fooed_2 This is fooed_2 `line 415 "t/t_preproc.v" 0 `define NOPARAM() np `line 417 "t/t_preproc.v" 0 np np `define NODS_DEFINED `line 422 "t/t_preproc.v" 0 `define NODS_INDIRECT(x) x `line 423 "t/t_preproc.v" 0 `line 426 "t/t_preproc.v" 0 `line 429 "t/t_preproc.v" 0 `define REPEAT_0(d) `line 432 "t/t_preproc.v" 0 `define REPEAT_1(d) d `line 433 "t/t_preproc.v" 0 `define REPEAT_2(d) `REPEAT_1(d)d `line 434 "t/t_preproc.v" 0 `define REPEAT_3(d) `REPEAT_2(d)d `line 435 "t/t_preproc.v" 0 `define REPEAT_4(d) `REPEAT_3(d)d `line 437 "t/t_preproc.v" 0 `define CONCAT(a, b) a``b `line 438 "t/t_preproc.v" 0 `define REPEATC(n, d) `CONCAT(`REPEAT_, n)(d) `line 439 "t/t_preproc.v" 0 `define REPEATT(n, d) `REPEAT_``n(d) `line 441 "t/t_preproc.v" 0 hello3hello3hello3 hello4hello4hello4hello4 `undef T_PREPROC_INC4 `line 446 "t/t_preproc.v" 0 `define NODS_CONC_VH(m) `"m.vh`" `line 447 "t/t_preproc.v" 0 `line 447 "t/t_preproc.v" 0 `line 1 "t/t_preproc_inc4.vh" 1 `line 2 "t/t_preproc_inc4.vh" 0 `line 6 "t/t_preproc_inc4.vh" 0 `define T_PREPROC_INC4 `line 8 "t/t_preproc_inc4.vh" 0 `line 447 "t/t_preproc.v" 2 `line 448 "t/t_preproc.v" 0 `define DEFINEIT(d) d \ `line 454 "t/t_preproc.v" 0 `define _DEFIF_Z_0 1 `line 455 "t/t_preproc.v" 0 `define DEFIF_NZ(d,n) `undef d `ifndef _DEFIF_Z_``n `DEFINEIT(`define d 1) `endif `line 456 "t/t_preproc.v" 0 `undef TEMP `line 456 "t/t_preproc.v" 0 `line 456 "t/t_preproc.v" 0 `define TEMP 1 `line 456 "t/t_preproc.v" 0 `undef TEMP `line 458 "t/t_preproc.v" 0 Line_Preproc_Check 460 `define MULQUOTE "FOO \ BAR " `line 465 "t/t_preproc.v" 0 `define MULQUOTE2(mq) `MULQUOTE mq `MULQUOTE `line 466 "t/t_preproc.v" 0 Line_Preproc_Check 466 "FOO \ BAR " "arg_line1 \ arg_line2" "FOO \ BAR " `line 469 "t/t_preproc.v" 0 Line_Preproc_Check 469 `line 473 "t/t_preproc.v" 0 `define A a `line 474 "t/t_preproc.v" 0 `define B b `line 475 "t/t_preproc.v" 0 `define C c `line 476 "t/t_preproc.v" 0 `define C5 `A``b```C `line 478 "t/t_preproc.v" 0 abc `undef A `line 480 "t/t_preproc.v" 0 `undef B `line 481 "t/t_preproc.v" 0 `undef C `line 483 "t/t_preproc.v" 0 `define XTYPE sonet `line 484 "t/t_preproc.v" 0 `define XJOIN(__arg1, __arg2) __arg1``__arg2 `line 485 "t/t_preproc.v" 0 `define XACTION `XJOIN(`XTYPE, _frame) `line 486 "t/t_preproc.v" 0 EXP: sonet_frame sonet_frame `line 489 "t/t_preproc.v" 0 `define XFRAME frame `line 490 "t/t_preproc.v" 0 `define XACTION2 `XJOIN(sonet_, `XFRAME) `line 491 "t/t_preproc.v" 0 EXP: sonet_frame sonet_frame `define sonet_frame other_frame `line 495 "t/t_preproc.v" 0 `define XACTION3 `XTYPE``_frame `line 496 "t/t_preproc.v" 0 EXP: sonet_frame sonet_frame `line 499 "t/t_preproc.v" 0 `define QA_b zzz `line 501 "t/t_preproc.v" 0 `define Q1 `QA``_b `line 502 "t/t_preproc.v" 0 EXP: module zzz ; endmodule module zzz ; endmodule module zzz ; endmodule `line 506 "t/t_preproc.v" 0 `define QA a `line 507 "t/t_preproc.v" 0 EXP: module a_b ; endmodule module a_b ; endmodule module a_b ; endmodule `line 511 "t/t_preproc.v" 0 integer foo; module t; `define LEX_CAT(lexem1, lexem2) lexem1``lexem2 `line 521 "t/t_preproc.v" 0 `define LEX_ESC(name) \name \ `line 523 "t/t_preproc.v" 0 initial begin : \`LEX_CAT(a[0],_assignment) `line 523 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\`LEX_CAT(a[0],_assignment) "); end `define ESC_CAT(name,name2) \name``_assignment_``name2 \ `line 530 "t/t_preproc.v" 0 initial begin : \a[0]_assignment_a[1] `line 530 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\a[0]_assignment_a[1] "); end `undef ESC_CAT `line 532 "t/t_preproc.v" 0 `define CAT(a,b) a``b `line 534 "t/t_preproc.v" 0 `define ESC(name) \`CAT(name,suffix) `line 535 "t/t_preproc.v" 0 initial begin : \`CAT(pp,suffix) $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(pp,suffix) "); end `undef CAT `line 538 "t/t_preproc.v" 0 `undef ESC `line 539 "t/t_preproc.v" 0 `define CAT(a,b) a``b `line 541 "t/t_preproc.v" 0 `define ESC(name) \name \ `line 543 "t/t_preproc.v" 0 initial begin : \`CAT(ff,bb) `line 544 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(ff,bb) "); end `undef CAT `line 545 "t/t_preproc.v" 0 `undef ESC `line 546 "t/t_preproc.v" 0 `define ESC(name) \name \ `line 549 "t/t_preproc.v" 0 initial begin : \`zzz `line 550 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\`zzz "); end `undef ESC `line 552 "t/t_preproc.v" 0 `define FOO bar `line 554 "t/t_preproc.v" 0 `define ESC(name) \name \ `line 556 "t/t_preproc.v" 0 initial begin : \`FOO `line 557 "t/t_preproc.v" 0 $write("GOT%%m='%m' OTHER_EXP='%s'\n OUR_EXP='%s'", "t.bar ","t.\\`FOO "); end initial begin : \xx`FOO `line 559 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\xx`FOO "); end `undef FOO `line 560 "t/t_preproc.v" 0 `undef ESC `line 561 "t/t_preproc.v" 0 `undef UNKNOWN `line 564 "t/t_preproc.v" 0 initial begin : \`UNKNOWN $write("GOT%%m='%m' EXP='%s'\n", "t.\\`UNKNOWN "); end `define DEF_NO_EXPAND error_dont_expand `line 568 "t/t_preproc.v" 0 initial begin : \`DEF_NO_EXPAND $write("GOT%%m='%m' EXP='%s'\n", "t.\\`DEF_NO_EXPAND "); end `undef DEF_NO_EXPAND `line 570 "t/t_preproc.v" 0 `define STR(name) "foo name baz" `line 574 "t/t_preproc.v" 0 initial $write("GOT='%s' EXP='%s'\n", "foo name baz", "foo bar baz"); `undef STR `line 576 "t/t_preproc.v" 0 `define STR(name) "foo name baz" `line 579 "t/t_preproc.v" 0 `define A(name) boo name hiss `line 580 "t/t_preproc.v" 0 initial $write("GOT='%s' EXP='%s'\n", "foo name baz", "foo `A(bar) baz"); `undef A `line 581 "t/t_preproc.v" 0 `undef STR `line 582 "t/t_preproc.v" 0 `define SLASHED "1//2.3" `line 585 "t/t_preproc.v" 0 initial $write("Slashed=`%s'\n", "1//2.3"); `define BUG915(a,b,c) \ $display("%s%s",a,`"b``c``\n`") `line 590 "t/t_preproc.v" 0 initial `line 590 "t/t_preproc.v" 0 $display("%s%s","a1","b2c3\n"); endmodule `line 593 "t/t_preproc.v" 0 `line 596 "t/t_preproc.v" 0 `define X_ITEM(SUB,UNIT) `X_STRING(SUB``UNIT) `line 597 "t/t_preproc.v" 0 `define X_STRING(A) `"A`" `line 598 "t/t_preproc.v" 0 $display("RAM0"); $display("CPU"); `line 601 "t/t_preproc.v" 0 `define EMPTY `line 602 "t/t_preproc.v" 0 `define EMPTYP(foo) `line 603 "t/t_preproc.v" 0 `define SOME some `line 604 "t/t_preproc.v" 0 `define SOMEP(foo) foo `line 606 "t/t_preproc.v" 0 `define XXE_FAMILY XXE_```EMPTY `line 607 "t/t_preproc.v" 0 XXE_FAMILY = XXE_ `define XXE_ `line 609 "t/t_preproc.v" 0 $display("XXE_ is defined"); `line 613 "t/t_preproc.v" 0 `define XYE_FAMILY XYE_```EMPTYP(foo) `line 614 "t/t_preproc.v" 0 XYE_FAMILY = XYE_ `define XYE_ `line 616 "t/t_preproc.v" 0 $display("XYE_ is defined"); `line 620 "t/t_preproc.v" 0 `define XXS_FAMILY XXS_```SOME `line 621 "t/t_preproc.v" 0 XXS_FAMILY = XXS_some `define XXS_some `line 623 "t/t_preproc.v" 0 $display("XXS_some is defined"); `line 627 "t/t_preproc.v" 0 `define XYS_FAMILY XYS_```SOMEP(foo) `line 628 "t/t_preproc.v" 0 XYS_FAMILY = XYS_foo `define XYS_foo `line 630 "t/t_preproc.v" 0 $display("XYS_foo is defined"); `line 634 "t/t_preproc.v" 0 `line 636 "t/t_preproc.v" 0 `line 644 "t/t_preproc.v" 0 `line 651 "t/t_preproc.v" 0 `line 658 "t/t_preproc.v" 0 `line 665 "t/t_preproc.v" 0 `line 667 "t/t_preproc.v" 0 `line 669 "t/t_preproc.v" 0 `define INSTANCE(NAME) (.mySig (myInterface.``NAME), `line 671 "t/t_preproc.v" 0 (.mySig (myInterface.pa5), `line 673 "t/t_preproc.v" 0 `line 676 "t/t_preproc.v" 0 `define hack(GRP) `dbg_hdl(UVM_LOW, (`"Functional coverage enabled: GRP`")); `line 677 "t/t_preproc.v" 0 `dbg_hdl(UVM_LOW, ("Functional coverage enabled: paramgrp")); `line 679 "t/t_preproc.v" 0 `define dbg_hdl(LVL, MSG) $display ("DEBUG : %s [%m]", $sformatf MSG) `line 680 "t/t_preproc.v" 0 `define svfcov_new(GRP) \ initial do begin `dbg_hdl(UVM_LOW, (`"Functional coverage enabled: GRP`")); end while(0) `line 682 "t/t_preproc.v" 0 `define simple_svfcov_clk(LBL, CLK, RST, ARG) \ covergroup LBL @(posedge CLK); \ c: coverpoint ARG iff ((RST) === 1'b1); endgroup \ LBL u_``LBL; `svfcov_new(u_``LBL) `line 687 "t/t_preproc.v" 0 `line 687 "t/t_preproc.v" 0 module pcc2_cfg; generate `line 689 "t/t_preproc.v" 0 covergroup a @(posedge b); `line 689 "t/t_preproc.v" 0 c: coverpoint d iff ((c) === 1'b1); endgroup `line 689 "t/t_preproc.v" 0 a u_a; `line 689 "t/t_preproc.v" 0 initial do begin $display ("DEBUG : %s [%m]", $sformatf ("Functional coverage enabled: u_a")); end while(0); endgenerate endmodule `line 693 "t/t_preproc.v" 0 `define stringify(text) `"text`" `line 696 "t/t_preproc.v" 0 "`NOT_DEFINED_STR" `line 698 "t/t_preproc.v" 0 """First line with "quoted"\nSecond line\ Third line""" """First line Second line""" `line 705 "t/t_preproc.v" 0 `define QQQ """QQQ defform""" `line 706 "t/t_preproc.v" 0 `define QQQS(x) x `line 707 "t/t_preproc.v" 0 """QQQ defform""" """QQQ defval""" `line 710 "t/t_preproc.v" 0 `define IDENTITY(arg) ``arg `line 712 "t/t_preproc.v" 0 "string argument" `line 714 "t/t_preproc.v" 0 `line 717 "t/t_preproc.v" 0 `define MAC_WITH_STR(foo) foo "foo foo foo" foo `line 718 "t/t_preproc.v" 0 bar "foo foo foo" bar `define MAC_WITH_3STR(foo) foo """foo foo foo""" foo `line 720 "t/t_preproc.v" 0 bar """foo foo foo""" bar `line 722 "t/t_preproc.v" 0 `undefineall `line 724 "t/t_preproc.v" 0 predef 0 0 predef 1 1 predef 2 2 predef 3 3 predef 10 10 predef 11 11 predef 20 20 predef 21 21 predef 22 22 predef 23 23 predef -2 -2 predef -1 -1 predef 0 0 predef 1 1 predef 2 2 `define WITH_ARG(a) (a)(a) `line 744 "t/t_preproc.v" 0 `define foo test `line 747 "t/t_preproc.v" 0 `define a x,y `line 748 "t/t_preproc.v" 0 `define bar(a, b) test a b `line 749 "t/t_preproc.v" 0 `define baz(a, b) test``a``b `line 750 "t/t_preproc.v" 0 `define qux(x) string boo = x; `line 751 "t/t_preproc.v" 0 `define quux(x) `qux(`"x`") `line 752 "t/t_preproc.v" 0 string boo = "test"; string boo = "test x,y x,y"; string boo = "testx,ytest x x,y"; string boo = "testtest x,y xquux(test)"; `line 757 "t/t_preproc.v" 0 `line 760 "t/t_preproc.v" 0 `define uvm_a(x) foo x bar `line 761 "t/t_preproc.v" 0 `define uvm_imp_decl(SFX) \ class uvm_master_imp``SFX \ `uvm_a(SFX, RSP, t) \ \ `uvm_a(SFX, REQ, t) \ \ endclass `line 769 "t/t_preproc.v" 0 `line 769 "t/t_preproc.v" 0 verilator-5.042/test_regress/t/t_case_huge.v0000644000542200017500000002350715101701376021532 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg [9:0] index; wire [7:0] index0 = index[7:0] + 8'h0; wire [7:0] index1 = index[7:0] + 8'h1; wire [7:0] index2 = index[7:0] + 8'h2; wire [7:0] index3 = index[7:0] + 8'h3; wire [7:0] index4 = index[7:0] + 8'h4; wire [7:0] index5 = index[7:0] + 8'h5; wire [7:0] index6 = index[7:0] + 8'h6; wire [7:0] index7 = index[7:0] + 8'h7; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [9:0] outa0; // From s0 of t_case_huge_sub.v wire [9:0] outa1; // From s1 of t_case_huge_sub.v wire [9:0] outa2; // From s2 of t_case_huge_sub.v wire [9:0] outa3; // From s3 of t_case_huge_sub.v wire [9:0] outa4; // From s4 of t_case_huge_sub.v wire [9:0] outa5; // From s5 of t_case_huge_sub.v wire [9:0] outa6; // From s6 of t_case_huge_sub.v wire [9:0] outa7; // From s7 of t_case_huge_sub.v wire [1:0] outb0; // From s0 of t_case_huge_sub.v wire [1:0] outb1; // From s1 of t_case_huge_sub.v wire [1:0] outb2; // From s2 of t_case_huge_sub.v wire [1:0] outb3; // From s3 of t_case_huge_sub.v wire [1:0] outb4; // From s4 of t_case_huge_sub.v wire [1:0] outb5; // From s5 of t_case_huge_sub.v wire [1:0] outb6; // From s6 of t_case_huge_sub.v wire [1:0] outb7; // From s7 of t_case_huge_sub.v wire outc0; // From s0 of t_case_huge_sub.v wire outc1; // From s1 of t_case_huge_sub.v wire outc2; // From s2 of t_case_huge_sub.v wire outc3; // From s3 of t_case_huge_sub.v wire outc4; // From s4 of t_case_huge_sub.v wire outc5; // From s5 of t_case_huge_sub.v wire outc6; // From s6 of t_case_huge_sub.v wire outc7; // From s7 of t_case_huge_sub.v wire [9:0] outq; // From q of t_case_huge_sub4.v wire [3:0] outr; // From sub3 of t_case_huge_sub3.v wire [9:0] outsmall; // From sub2 of t_case_huge_sub2.v // End of automatics t_case_huge_sub2 sub2 ( // Outputs .outa (outsmall[9:0]), /*AUTOINST*/ // Inputs .index (index[9:0])); t_case_huge_sub3 sub3 (/*AUTOINST*/ // Outputs .outr (outr[3:0]), // Inputs .clk (clk), .index (index[9:0])); /* t_case_huge_sub AUTO_TEMPLATE ( .outa (outa@[]), .outb (outb@[]), .outc (outc@[]), .index (index@[])); */ t_case_huge_sub s0 (/*AUTOINST*/ // Outputs .outa (outa0[9:0]), // Templated .outb (outb0[1:0]), // Templated .outc (outc0), // Templated // Inputs .index (index0[7:0])); // Templated t_case_huge_sub s1 (/*AUTOINST*/ // Outputs .outa (outa1[9:0]), // Templated .outb (outb1[1:0]), // Templated .outc (outc1), // Templated // Inputs .index (index1[7:0])); // Templated t_case_huge_sub s2 (/*AUTOINST*/ // Outputs .outa (outa2[9:0]), // Templated .outb (outb2[1:0]), // Templated .outc (outc2), // Templated // Inputs .index (index2[7:0])); // Templated t_case_huge_sub s3 (/*AUTOINST*/ // Outputs .outa (outa3[9:0]), // Templated .outb (outb3[1:0]), // Templated .outc (outc3), // Templated // Inputs .index (index3[7:0])); // Templated t_case_huge_sub s4 (/*AUTOINST*/ // Outputs .outa (outa4[9:0]), // Templated .outb (outb4[1:0]), // Templated .outc (outc4), // Templated // Inputs .index (index4[7:0])); // Templated t_case_huge_sub s5 (/*AUTOINST*/ // Outputs .outa (outa5[9:0]), // Templated .outb (outb5[1:0]), // Templated .outc (outc5), // Templated // Inputs .index (index5[7:0])); // Templated t_case_huge_sub s6 (/*AUTOINST*/ // Outputs .outa (outa6[9:0]), // Templated .outb (outb6[1:0]), // Templated .outc (outc6), // Templated // Inputs .index (index6[7:0])); // Templated t_case_huge_sub s7 (/*AUTOINST*/ // Outputs .outa (outa7[9:0]), // Templated .outb (outb7[1:0]), // Templated .outc (outc7), // Templated // Inputs .index (index7[7:0])); // Templated t_case_huge_sub4 q (/*AUTOINST*/ // Outputs .outq (outq[9:0]), // Inputs .index (index[7:0])); integer cyc; initial cyc=1; initial index = 10'h0; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; //$write("%x: %x\n",cyc,outr); //$write("%x: %x %x %x %x\n", cyc, outa1,outb1,outc1,index1); if (cyc==1) begin index <= 10'h236; end if (cyc==2) begin index <= 10'h022; if (outsmall != 10'h282) $stop; if (outr != 4'b0) $stop; if ({outa0,outb0,outc0}!={10'h282,2'd3,1'b0}) $stop; if ({outa1,outb1,outc1}!={10'h21c,2'd3,1'b1}) $stop; if ({outa2,outb2,outc2}!={10'h148,2'd0,1'b1}) $stop; if ({outa3,outb3,outc3}!={10'h3c0,2'd2,1'b0}) $stop; if ({outa4,outb4,outc4}!={10'h176,2'd1,1'b1}) $stop; if ({outa5,outb5,outc5}!={10'h3fc,2'd2,1'b1}) $stop; if ({outa6,outb6,outc6}!={10'h295,2'd3,1'b1}) $stop; if ({outa7,outb7,outc7}!={10'h113,2'd2,1'b1}) $stop; if (outq != 10'h001) $stop; end if (cyc==3) begin index <= 10'h165; if (outsmall != 10'h191) $stop; if (outr != 4'h5) $stop; if ({outa1,outb1,outc1}!={10'h379,2'd1,1'b0}) $stop; if ({outa2,outb2,outc2}!={10'h073,2'd0,1'b0}) $stop; if ({outa3,outb3,outc3}!={10'h2fd,2'd3,1'b1}) $stop; if ({outa4,outb4,outc4}!={10'h2e0,2'd3,1'b1}) $stop; if ({outa5,outb5,outc5}!={10'h337,2'd1,1'b1}) $stop; if ({outa6,outb6,outc6}!={10'h2c7,2'd3,1'b1}) $stop; if ({outa7,outb7,outc7}!={10'h19e,2'd3,1'b0}) $stop; if (outq != 10'h001) $stop; end if (cyc==4) begin index <= 10'h201; if (outsmall != 10'h268) $stop; if (outr != 4'h2) $stop; if ({outa1,outb1,outc1}!={10'h111,2'd1,1'b0}) $stop; if ({outa2,outb2,outc2}!={10'h1f9,2'd0,1'b0}) $stop; if ({outa3,outb3,outc3}!={10'h232,2'd0,1'b1}) $stop; if ({outa4,outb4,outc4}!={10'h255,2'd3,1'b0}) $stop; if ({outa5,outb5,outc5}!={10'h34c,2'd1,1'b1}) $stop; if ({outa6,outb6,outc6}!={10'h049,2'd1,1'b1}) $stop; if ({outa7,outb7,outc7}!={10'h197,2'd3,1'b0}) $stop; if (outq != 10'h001) $stop; end if (cyc==5) begin index <= 10'h3ff; if (outr != 4'hd) $stop; if (outq != 10'h001) $stop; end if (cyc==6) begin index <= 10'h0; if (outr != 4'hd) $stop; if (outq != 10'h114) $stop; end if (cyc==7) begin if (outr != 4'h4) $stop; end if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.042/test_regress/t/t_enum_type_pins.v0000644000542200017500000000634715101701376022650 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: System Verilog test of enumerated type methods // // This code exercises the various enumeration methods // // This file ONLY is placed into the Public Domain, for any use, without // warranty. // SPDX-License-Identifier: CC0-1.0 // Contributed 2012 by M W Lund, Atmel Corporation and Jeremy Bennett, Embecosm. // **** Pin Identifiers **** typedef enum int { PINID_A0 = 32'd0, // MUST BE ZERO! // - Standard Ports - PINID_A1, PINID_A2, PINID_A3, PINID_A4, PINID_A5, PINID_A6, PINID_A7, PINID_B0, PINID_B1, PINID_B2, PINID_B3, PINID_B4, PINID_B5, PINID_B6, PINID_B7, PINID_C0, PINID_C1, PINID_C2, PINID_C3, PINID_C4, PINID_C5, PINID_C6, PINID_C7, PINID_D0, PINID_D1, PINID_D2, PINID_D3, PINID_D4, PINID_D5, PINID_D6, PINID_D7, PINID_E0, PINID_E1, PINID_E2, PINID_E3, PINID_E4, PINID_E5, PINID_E6, PINID_E7, PINID_F0, PINID_F1, PINID_F2, PINID_F3, PINID_F4, PINID_F5, PINID_F6, PINID_F7, PINID_G0, PINID_G1, PINID_G2, PINID_G3, PINID_G4, PINID_G5, PINID_G6, PINID_G7, PINID_H0, PINID_H1, PINID_H2, PINID_H3, PINID_H4, PINID_H5, PINID_H6, PINID_H7, // PINID_I0, PINID_I1, PINID_I2, PINID_I3, PINID_I4, PINID_I5, PINID_I6, PINID_I7,-> DO NOT USE!!!! I == 1 PINID_J0, PINID_J1, PINID_J2, PINID_J3, PINID_J4, PINID_J5, PINID_J6, PINID_J7, PINID_K0, PINID_K1, PINID_K2, PINID_K3, PINID_K4, PINID_K5, PINID_K6, PINID_K7, PINID_L0, PINID_L1, PINID_L2, PINID_L3, PINID_L4, PINID_L5, PINID_L6, PINID_L7, PINID_M0, PINID_M1, PINID_M2, PINID_M3, PINID_M4, PINID_M5, PINID_M6, PINID_M7, PINID_N0, PINID_N1, PINID_N2, PINID_N3, PINID_N4, PINID_N5, PINID_N6, PINID_N7, // PINID_O0, PINID_O1, PINID_O2, PINID_O3, PINID_O4, PINID_O5, PINID_O6, PINID_O7,-> DO NOT USE!!!! O == 0 PINID_P0, PINID_P1, PINID_P2, PINID_P3, PINID_P4, PINID_P5, PINID_P6, PINID_P7, PINID_Q0, PINID_Q1, PINID_Q2, PINID_Q3, PINID_Q4, PINID_Q5, PINID_Q6, PINID_Q7, PINID_R0, PINID_R1, PINID_R2, PINID_R3, PINID_R4, PINID_R5, PINID_R6, PINID_R7, // - AUX Port (Custom) - PINID_X0, PINID_X1, PINID_X2, PINID_X3, PINID_X4, PINID_X5, PINID_X6, PINID_X7, // - PDI Port - PINID_D2W_DAT, PINID_D2W_CLK, // - Power Pins - PINID_VDD0, PINID_VDD1, PINID_VDD2, PINID_VDD3, PINID_GND0, PINID_GND1, PINID_GND2, PINID_GND3, // - Maximum number of pins - PINID_MAX } t_pinid; module t (/*AUTOARG*/ // Inputs clk ); input clk; wire a = clk; wire b = 1'b0; reg c; test test_i (/*AUTOINST*/ // Inputs .clk (clk)); // This is a compile time only test. Immediately finish always @(posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end endmodule module test (/*AUTOARG*/ // Inputs clk ); input clk; // Use the enumeration size to initialize a dynamic array t_pinid e; int myarray1 [] = new [e.num]; always @(posedge clk) begin `ifdef TEST_VERBOSE $write ("Enumeration has %d members\n", e.num); `endif e = e.first; forever begin myarray1[e] = e.prev; `ifdef TEST_VERBOSE $write ("myarray1[%d] (enum %s) = %d\n", e, e.name, myarray1[e]); `endif if (e == e.last) begin break; end else begin e = e.next; end end end endmodule verilator-5.042/test_regress/t/t_const_slicesel_bad.out0000644000542200017500000000061315101701376023761 0ustar mahmoudyfreeshell%Error: t/t_const_slicesel_bad.v:12:42: Slice selection index '[3:1]' outside data type's '[2:0]' : ... note: In instance 't' 12 | localparam int unsigned B32_T[1:0] = A3[3:1]; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_struct_unpacked_clean.v0000644000542200017500000000107115101701376024137 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef struct { logic [4:0] w5; } Data_t; module t; reg en; reg [7:0] r_id; Data_t ts; initial begin en = 1; r_id = 42; ts = '{w5: en ? r_id[4:0] : 5'b0}; $display("ts.w5 = %h", ts.w5); if ($c32(ts.w5) != 5'h0a) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_time_sscanf.py0000755000542200017500000000073415101701376022265 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_case_huge_sub.v0000644000542200017500000004246515101701376022407 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t_case_huge_sub (/*AUTOARG*/ // Outputs outa, outb, outc, // Inputs index ); input [7:0] index; output logic [9:0] outa; output logic [1:0] outb; output logic outc; // ============================= // Created from Python3: // for i in range(1024): // print(" 10'h%03x: begin outa = 10'h%03x; outb = 2'b%d%d; outc = 1'b%d; end" // % (i, random.randint(0,1024), random.randint(0,1), // random.randint(0,1), random.randint(0,1))) always @* begin // verilog_format: off case (index) 8'h00: begin outa = 10'h152; outb = 2'b00; outc = 1'b1; end 8'h01: begin outa = 10'h318; outb = 2'b11; outc = 1'b1; end 8'h02: begin outa = 10'h29f; outb = 2'b11; outc = 1'b0; end 8'h03: begin outa = 10'h392; outb = 2'b01; outc = 1'b1; end 8'h04: begin outa = 10'h1ef; outb = 2'b00; outc = 1'b0; end 8'h05: begin outa = 10'h06c; outb = 2'b10; outc = 1'b1; end 8'h06: begin outa = 10'h29f; outb = 2'b11; outc = 1'b0; end 8'h07: begin outa = 10'h29a; outb = 2'b10; outc = 1'b0; end 8'h08: begin outa = 10'h3ce; outb = 2'b01; outc = 1'b0; end 8'h09: begin outa = 10'h37c; outb = 2'b01; outc = 1'b0; end 8'h0a: begin outa = 10'h058; outb = 2'b10; outc = 1'b0; end 8'h0b: begin outa = 10'h3b2; outb = 2'b01; outc = 1'b1; end 8'h0c: begin outa = 10'h36f; outb = 2'b11; outc = 1'b0; end 8'h0d: begin outa = 10'h2c5; outb = 2'b11; outc = 1'b0; end 8'h0e: begin outa = 10'h23a; outb = 2'b00; outc = 1'b0; end 8'h0f: begin outa = 10'h222; outb = 2'b01; outc = 1'b1; end 8'h10: begin outa = 10'h328; outb = 2'b00; outc = 1'b1; end 8'h11: begin outa = 10'h3c3; outb = 2'b00; outc = 1'b1; end 8'h12: begin outa = 10'h12c; outb = 2'b01; outc = 1'b0; end 8'h13: begin outa = 10'h1d0; outb = 2'b00; outc = 1'b1; end 8'h14: begin outa = 10'h3ff; outb = 2'b01; outc = 1'b1; end 8'h15: begin outa = 10'h115; outb = 2'b11; outc = 1'b1; end 8'h16: begin outa = 10'h3ba; outb = 2'b10; outc = 1'b0; end 8'h17: begin outa = 10'h3ba; outb = 2'b00; outc = 1'b0; end 8'h18: begin outa = 10'h10d; outb = 2'b00; outc = 1'b1; end 8'h19: begin outa = 10'h13b; outb = 2'b01; outc = 1'b1; end 8'h1a: begin outa = 10'h0a0; outb = 2'b10; outc = 1'b1; end 8'h1b: begin outa = 10'h264; outb = 2'b11; outc = 1'b0; end 8'h1c: begin outa = 10'h3a2; outb = 2'b10; outc = 1'b0; end 8'h1d: begin outa = 10'h07c; outb = 2'b00; outc = 1'b1; end 8'h1e: begin outa = 10'h291; outb = 2'b00; outc = 1'b0; end 8'h1f: begin outa = 10'h1d1; outb = 2'b10; outc = 1'b0; end 8'h20: begin outa = 10'h354; outb = 2'b11; outc = 1'b1; end 8'h21: begin outa = 10'h0c0; outb = 2'b00; outc = 1'b1; end 8'h22: begin outa = 10'h191; outb = 2'b00; outc = 1'b0; end 8'h23: begin outa = 10'h379; outb = 2'b01; outc = 1'b0; end 8'h24: begin outa = 10'h073; outb = 2'b00; outc = 1'b0; end 8'h25: begin outa = 10'h2fd; outb = 2'b11; outc = 1'b1; end 8'h26: begin outa = 10'h2e0; outb = 2'b11; outc = 1'b1; end 8'h27: begin outa = 10'h337; outb = 2'b01; outc = 1'b1; end 8'h28: begin outa = 10'h2c7; outb = 2'b11; outc = 1'b1; end 8'h29: begin outa = 10'h19e; outb = 2'b11; outc = 1'b0; end 8'h2a: begin outa = 10'h107; outb = 2'b10; outc = 1'b0; end 8'h2b: begin outa = 10'h06a; outb = 2'b01; outc = 1'b1; end 8'h2c: begin outa = 10'h1c7; outb = 2'b01; outc = 1'b1; end 8'h2d: begin outa = 10'h107; outb = 2'b10; outc = 1'b0; end 8'h2e: begin outa = 10'h0cf; outb = 2'b01; outc = 1'b1; end 8'h2f: begin outa = 10'h009; outb = 2'b11; outc = 1'b1; end 8'h30: begin outa = 10'h09d; outb = 2'b00; outc = 1'b1; end 8'h31: begin outa = 10'h28e; outb = 2'b00; outc = 1'b0; end 8'h32: begin outa = 10'h010; outb = 2'b01; outc = 1'b0; end 8'h33: begin outa = 10'h1e0; outb = 2'b10; outc = 1'b0; end 8'h34: begin outa = 10'h079; outb = 2'b01; outc = 1'b1; end 8'h35: begin outa = 10'h13e; outb = 2'b10; outc = 1'b1; end 8'h36: begin outa = 10'h282; outb = 2'b11; outc = 1'b0; end 8'h37: begin outa = 10'h21c; outb = 2'b11; outc = 1'b1; end 8'h38: begin outa = 10'h148; outb = 2'b00; outc = 1'b1; end 8'h39: begin outa = 10'h3c0; outb = 2'b10; outc = 1'b0; end 8'h3a: begin outa = 10'h176; outb = 2'b01; outc = 1'b1; end 8'h3b: begin outa = 10'h3fc; outb = 2'b10; outc = 1'b1; end 8'h3c: begin outa = 10'h295; outb = 2'b11; outc = 1'b1; end 8'h3d: begin outa = 10'h113; outb = 2'b10; outc = 1'b1; end 8'h3e: begin outa = 10'h354; outb = 2'b01; outc = 1'b1; end 8'h3f: begin outa = 10'h0db; outb = 2'b11; outc = 1'b0; end 8'h40: begin outa = 10'h238; outb = 2'b01; outc = 1'b0; end 8'h41: begin outa = 10'h12b; outb = 2'b01; outc = 1'b1; end 8'h42: begin outa = 10'h1dc; outb = 2'b10; outc = 1'b0; end 8'h43: begin outa = 10'h137; outb = 2'b01; outc = 1'b1; end 8'h44: begin outa = 10'h1e2; outb = 2'b01; outc = 1'b1; end 8'h45: begin outa = 10'h3d5; outb = 2'b11; outc = 1'b1; end 8'h46: begin outa = 10'h30c; outb = 2'b11; outc = 1'b0; end 8'h47: begin outa = 10'h298; outb = 2'b11; outc = 1'b0; end 8'h48: begin outa = 10'h080; outb = 2'b00; outc = 1'b1; end 8'h49: begin outa = 10'h35a; outb = 2'b11; outc = 1'b1; end 8'h4a: begin outa = 10'h01b; outb = 2'b00; outc = 1'b0; end 8'h4b: begin outa = 10'h0a3; outb = 2'b11; outc = 1'b0; end 8'h4c: begin outa = 10'h0b3; outb = 2'b11; outc = 1'b1; end 8'h4d: begin outa = 10'h17a; outb = 2'b00; outc = 1'b0; end 8'h4e: begin outa = 10'h3ae; outb = 2'b11; outc = 1'b0; end 8'h4f: begin outa = 10'h078; outb = 2'b11; outc = 1'b0; end 8'h50: begin outa = 10'h322; outb = 2'b00; outc = 1'b1; end 8'h51: begin outa = 10'h213; outb = 2'b11; outc = 1'b0; end 8'h52: begin outa = 10'h11a; outb = 2'b11; outc = 1'b0; end 8'h53: begin outa = 10'h1a7; outb = 2'b00; outc = 1'b0; end 8'h54: begin outa = 10'h35a; outb = 2'b00; outc = 1'b1; end 8'h55: begin outa = 10'h233; outb = 2'b00; outc = 1'b0; end 8'h56: begin outa = 10'h01d; outb = 2'b01; outc = 1'b1; end 8'h57: begin outa = 10'h2d5; outb = 2'b00; outc = 1'b0; end 8'h58: begin outa = 10'h1a0; outb = 2'b00; outc = 1'b1; end 8'h59: begin outa = 10'h3d0; outb = 2'b00; outc = 1'b1; end 8'h5a: begin outa = 10'h181; outb = 2'b01; outc = 1'b1; end 8'h5b: begin outa = 10'h219; outb = 2'b01; outc = 1'b1; end 8'h5c: begin outa = 10'h26a; outb = 2'b01; outc = 1'b1; end 8'h5d: begin outa = 10'h050; outb = 2'b10; outc = 1'b0; end 8'h5e: begin outa = 10'h189; outb = 2'b10; outc = 1'b0; end 8'h5f: begin outa = 10'h1eb; outb = 2'b01; outc = 1'b1; end 8'h60: begin outa = 10'h224; outb = 2'b00; outc = 1'b1; end 8'h61: begin outa = 10'h2fe; outb = 2'b00; outc = 1'b0; end 8'h62: begin outa = 10'h0ae; outb = 2'b00; outc = 1'b1; end 8'h63: begin outa = 10'h1cd; outb = 2'b00; outc = 1'b0; end 8'h64: begin outa = 10'h273; outb = 2'b10; outc = 1'b1; end 8'h65: begin outa = 10'h268; outb = 2'b10; outc = 1'b0; end 8'h66: begin outa = 10'h111; outb = 2'b01; outc = 1'b0; end 8'h67: begin outa = 10'h1f9; outb = 2'b00; outc = 1'b0; end 8'h68: begin outa = 10'h232; outb = 2'b00; outc = 1'b1; end 8'h69: begin outa = 10'h255; outb = 2'b11; outc = 1'b0; end 8'h6a: begin outa = 10'h34c; outb = 2'b01; outc = 1'b1; end 8'h6b: begin outa = 10'h049; outb = 2'b01; outc = 1'b1; end 8'h6c: begin outa = 10'h197; outb = 2'b11; outc = 1'b0; end 8'h6d: begin outa = 10'h0fe; outb = 2'b11; outc = 1'b0; end 8'h6e: begin outa = 10'h253; outb = 2'b01; outc = 1'b1; end 8'h6f: begin outa = 10'h2de; outb = 2'b11; outc = 1'b0; end 8'h70: begin outa = 10'h13b; outb = 2'b10; outc = 1'b1; end 8'h71: begin outa = 10'h040; outb = 2'b10; outc = 1'b0; end 8'h72: begin outa = 10'h0b4; outb = 2'b00; outc = 1'b1; end 8'h73: begin outa = 10'h233; outb = 2'b11; outc = 1'b1; end 8'h74: begin outa = 10'h198; outb = 2'b00; outc = 1'b1; end 8'h75: begin outa = 10'h018; outb = 2'b00; outc = 1'b1; end 8'h76: begin outa = 10'h2f7; outb = 2'b00; outc = 1'b1; end 8'h77: begin outa = 10'h134; outb = 2'b11; outc = 1'b0; end 8'h78: begin outa = 10'h1ca; outb = 2'b10; outc = 1'b0; end 8'h79: begin outa = 10'h286; outb = 2'b10; outc = 1'b1; end 8'h7a: begin outa = 10'h0e6; outb = 2'b11; outc = 1'b1; end 8'h7b: begin outa = 10'h064; outb = 2'b10; outc = 1'b1; end 8'h7c: begin outa = 10'h257; outb = 2'b00; outc = 1'b1; end 8'h7d: begin outa = 10'h31a; outb = 2'b10; outc = 1'b1; end 8'h7e: begin outa = 10'h247; outb = 2'b01; outc = 1'b0; end 8'h7f: begin outa = 10'h299; outb = 2'b00; outc = 1'b0; end 8'h80: begin outa = 10'h02c; outb = 2'b00; outc = 1'b0; end 8'h81: begin outa = 10'h2bb; outb = 2'b11; outc = 1'b0; end 8'h82: begin outa = 10'h180; outb = 2'b10; outc = 1'b0; end 8'h83: begin outa = 10'h245; outb = 2'b01; outc = 1'b1; end 8'h84: begin outa = 10'h0da; outb = 2'b10; outc = 1'b0; end 8'h85: begin outa = 10'h367; outb = 2'b10; outc = 1'b0; end 8'h86: begin outa = 10'h304; outb = 2'b01; outc = 1'b0; end 8'h87: begin outa = 10'h38b; outb = 2'b11; outc = 1'b0; end 8'h88: begin outa = 10'h09f; outb = 2'b01; outc = 1'b0; end 8'h89: begin outa = 10'h1f0; outb = 2'b10; outc = 1'b1; end 8'h8a: begin outa = 10'h281; outb = 2'b10; outc = 1'b1; end 8'h8b: begin outa = 10'h019; outb = 2'b00; outc = 1'b0; end 8'h8c: begin outa = 10'h1f2; outb = 2'b10; outc = 1'b0; end 8'h8d: begin outa = 10'h0b1; outb = 2'b01; outc = 1'b1; end 8'h8e: begin outa = 10'h058; outb = 2'b01; outc = 1'b1; end 8'h8f: begin outa = 10'h39b; outb = 2'b00; outc = 1'b1; end 8'h90: begin outa = 10'h2ec; outb = 2'b10; outc = 1'b1; end 8'h91: begin outa = 10'h250; outb = 2'b00; outc = 1'b1; end 8'h92: begin outa = 10'h3f4; outb = 2'b10; outc = 1'b1; end 8'h93: begin outa = 10'h057; outb = 2'b10; outc = 1'b1; end 8'h94: begin outa = 10'h18f; outb = 2'b01; outc = 1'b1; end 8'h95: begin outa = 10'h105; outb = 2'b01; outc = 1'b1; end 8'h96: begin outa = 10'h1ae; outb = 2'b00; outc = 1'b1; end 8'h97: begin outa = 10'h04e; outb = 2'b10; outc = 1'b0; end 8'h98: begin outa = 10'h240; outb = 2'b11; outc = 1'b0; end 8'h99: begin outa = 10'h3e4; outb = 2'b01; outc = 1'b0; end 8'h9a: begin outa = 10'h3c6; outb = 2'b01; outc = 1'b0; end 8'h9b: begin outa = 10'h109; outb = 2'b00; outc = 1'b1; end 8'h9c: begin outa = 10'h073; outb = 2'b10; outc = 1'b1; end 8'h9d: begin outa = 10'h19f; outb = 2'b01; outc = 1'b0; end 8'h9e: begin outa = 10'h3b8; outb = 2'b01; outc = 1'b0; end 8'h9f: begin outa = 10'h00e; outb = 2'b00; outc = 1'b1; end 8'ha0: begin outa = 10'h1b3; outb = 2'b11; outc = 1'b1; end 8'ha1: begin outa = 10'h2bd; outb = 2'b11; outc = 1'b0; end 8'ha2: begin outa = 10'h324; outb = 2'b00; outc = 1'b1; end 8'ha3: begin outa = 10'h343; outb = 2'b10; outc = 1'b0; end 8'ha4: begin outa = 10'h1c9; outb = 2'b01; outc = 1'b0; end 8'ha5: begin outa = 10'h185; outb = 2'b00; outc = 1'b1; end 8'ha6: begin outa = 10'h37a; outb = 2'b00; outc = 1'b1; end 8'ha7: begin outa = 10'h0e0; outb = 2'b01; outc = 1'b1; end 8'ha8: begin outa = 10'h0a3; outb = 2'b10; outc = 1'b0; end 8'ha9: begin outa = 10'h019; outb = 2'b11; outc = 1'b0; end 8'haa: begin outa = 10'h099; outb = 2'b00; outc = 1'b1; end 8'hab: begin outa = 10'h376; outb = 2'b01; outc = 1'b1; end 8'hac: begin outa = 10'h077; outb = 2'b00; outc = 1'b1; end 8'had: begin outa = 10'h2b1; outb = 2'b11; outc = 1'b1; end 8'hae: begin outa = 10'h27f; outb = 2'b00; outc = 1'b0; end 8'haf: begin outa = 10'h265; outb = 2'b11; outc = 1'b0; end 8'hb0: begin outa = 10'h156; outb = 2'b10; outc = 1'b1; end 8'hb1: begin outa = 10'h1ce; outb = 2'b00; outc = 1'b0; end 8'hb2: begin outa = 10'h008; outb = 2'b01; outc = 1'b0; end 8'hb3: begin outa = 10'h12e; outb = 2'b11; outc = 1'b1; end 8'hb4: begin outa = 10'h199; outb = 2'b11; outc = 1'b0; end 8'hb5: begin outa = 10'h330; outb = 2'b10; outc = 1'b0; end 8'hb6: begin outa = 10'h1ab; outb = 2'b01; outc = 1'b1; end 8'hb7: begin outa = 10'h3bd; outb = 2'b00; outc = 1'b0; end 8'hb8: begin outa = 10'h0ca; outb = 2'b10; outc = 1'b0; end 8'hb9: begin outa = 10'h367; outb = 2'b00; outc = 1'b0; end 8'hba: begin outa = 10'h334; outb = 2'b00; outc = 1'b0; end 8'hbb: begin outa = 10'h040; outb = 2'b00; outc = 1'b1; end 8'hbc: begin outa = 10'h1a7; outb = 2'b10; outc = 1'b1; end 8'hbd: begin outa = 10'h036; outb = 2'b11; outc = 1'b1; end 8'hbe: begin outa = 10'h223; outb = 2'b11; outc = 1'b1; end 8'hbf: begin outa = 10'h075; outb = 2'b01; outc = 1'b0; end 8'hc0: begin outa = 10'h3c4; outb = 2'b00; outc = 1'b1; end 8'hc1: begin outa = 10'h2cc; outb = 2'b01; outc = 1'b0; end 8'hc2: begin outa = 10'h123; outb = 2'b01; outc = 1'b0; end 8'hc3: begin outa = 10'h3fd; outb = 2'b01; outc = 1'b1; end 8'hc4: begin outa = 10'h11e; outb = 2'b00; outc = 1'b0; end 8'hc5: begin outa = 10'h27c; outb = 2'b11; outc = 1'b1; end 8'hc6: begin outa = 10'h1e2; outb = 2'b11; outc = 1'b0; end 8'hc7: begin outa = 10'h377; outb = 2'b11; outc = 1'b0; end 8'hc8: begin outa = 10'h33a; outb = 2'b11; outc = 1'b0; end 8'hc9: begin outa = 10'h32d; outb = 2'b11; outc = 1'b1; end 8'hca: begin outa = 10'h014; outb = 2'b11; outc = 1'b0; end 8'hcb: begin outa = 10'h332; outb = 2'b10; outc = 1'b0; end 8'hcc: begin outa = 10'h359; outb = 2'b00; outc = 1'b0; end 8'hcd: begin outa = 10'h0a4; outb = 2'b10; outc = 1'b1; end 8'hce: begin outa = 10'h348; outb = 2'b00; outc = 1'b1; end 8'hcf: begin outa = 10'h04b; outb = 2'b11; outc = 1'b1; end 8'hd0: begin outa = 10'h147; outb = 2'b10; outc = 1'b1; end 8'hd1: begin outa = 10'h026; outb = 2'b00; outc = 1'b1; end 8'hd2: begin outa = 10'h103; outb = 2'b00; outc = 1'b0; end 8'hd3: begin outa = 10'h106; outb = 2'b00; outc = 1'b1; end 8'hd4: begin outa = 10'h35a; outb = 2'b00; outc = 1'b0; end 8'hd5: begin outa = 10'h254; outb = 2'b01; outc = 1'b0; end 8'hd6: begin outa = 10'h0cd; outb = 2'b01; outc = 1'b0; end 8'hd7: begin outa = 10'h17c; outb = 2'b11; outc = 1'b1; end 8'hd8: begin outa = 10'h37e; outb = 2'b10; outc = 1'b1; end 8'hd9: begin outa = 10'h0a9; outb = 2'b11; outc = 1'b1; end 8'hda: begin outa = 10'h0fe; outb = 2'b01; outc = 1'b0; end 8'hdb: begin outa = 10'h3c0; outb = 2'b11; outc = 1'b1; end 8'hdc: begin outa = 10'h1d9; outb = 2'b10; outc = 1'b1; end 8'hdd: begin outa = 10'h10e; outb = 2'b00; outc = 1'b1; end 8'hde: begin outa = 10'h394; outb = 2'b01; outc = 1'b0; end 8'hdf: begin outa = 10'h316; outb = 2'b01; outc = 1'b0; end 8'he0: begin outa = 10'h05b; outb = 2'b11; outc = 1'b0; end 8'he1: begin outa = 10'h126; outb = 2'b01; outc = 1'b1; end 8'he2: begin outa = 10'h369; outb = 2'b11; outc = 1'b0; end 8'he3: begin outa = 10'h291; outb = 2'b10; outc = 1'b1; end 8'he4: begin outa = 10'h2ca; outb = 2'b00; outc = 1'b1; end 8'he5: begin outa = 10'h25b; outb = 2'b01; outc = 1'b1; end 8'he6: begin outa = 10'h106; outb = 2'b00; outc = 1'b0; end 8'he7: begin outa = 10'h172; outb = 2'b11; outc = 1'b1; end 8'he8: begin outa = 10'h2f7; outb = 2'b00; outc = 1'b1; end 8'he9: begin outa = 10'h2d3; outb = 2'b11; outc = 1'b1; end 8'hea: begin outa = 10'h182; outb = 2'b00; outc = 1'b0; end 8'heb: begin outa = 10'h327; outb = 2'b00; outc = 1'b1; end 8'hec: begin outa = 10'h1d0; outb = 2'b10; outc = 1'b0; end 8'hed: begin outa = 10'h204; outb = 2'b00; outc = 1'b1; end 8'hee: begin outa = 10'h11f; outb = 2'b00; outc = 1'b1; end 8'hef: begin outa = 10'h365; outb = 2'b11; outc = 1'b1; end 8'hf0: begin outa = 10'h2c2; outb = 2'b01; outc = 1'b1; end 8'hf1: begin outa = 10'h2b5; outb = 2'b10; outc = 1'b0; end 8'hf2: begin outa = 10'h1f8; outb = 2'b10; outc = 1'b1; end 8'hf3: begin outa = 10'h2a7; outb = 2'b01; outc = 1'b1; end 8'hf4: begin outa = 10'h1be; outb = 2'b10; outc = 1'b1; end 8'hf5: begin outa = 10'h25e; outb = 2'b10; outc = 1'b1; end 8'hf6: begin outa = 10'h032; outb = 2'b10; outc = 1'b0; end 8'hf7: begin outa = 10'h2ef; outb = 2'b00; outc = 1'b0; end 8'hf8: begin outa = 10'h02f; outb = 2'b00; outc = 1'b1; end 8'hf9: begin outa = 10'h201; outb = 2'b10; outc = 1'b0; end 8'hfa: begin outa = 10'h054; outb = 2'b01; outc = 1'b1; end 8'hfb: begin outa = 10'h013; outb = 2'b10; outc = 1'b0; end 8'hfc: begin outa = 10'h249; outb = 2'b01; outc = 1'b0; end 8'hfd: begin outa = 10'h09a; outb = 2'b10; outc = 1'b0; end 8'hfe: begin outa = 10'h012; outb = 2'b00; outc = 1'b0; end 8'hff: begin outa = 10'h114; outb = 2'b10; outc = 1'b1; end endcase // verilog_format: on end endmodule verilator-5.042/test_regress/t/t_flag_f_bad_cmt.py0000755000542200017500000000103215101701376022651 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(v_flags2=["-f t/t_flag_f_bad_cmt.vc"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_select_bad_width0.py0000755000542200017500000000077615101701376023344 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_param_default_bad.v0000644000542200017500000000044215101701376023212 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module m #(parameter int Foo); endmodule module t; m foo(); endmodule verilator-5.042/test_regress/t/t_opt_0.v0000644000542200017500000000056715101701376020631 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; for (genvar k = 0; k < 1; k++) begin : gen_empty // empty end initial for (int i = 0; i < 1; i++) begin : gen_i // empty end endmodule verilator-5.042/test_regress/t/t_constraint_method_bad.py0000755000542200017500000000077615101701376024332 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_unroll_pragma_disable.py0000755000542200017500000000154215101701376024315 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_unroll_pragma.v" test.compile(verilator_flags2=['--unroll-count 4 --unroll-stmts 9999 --stats -DTEST_DISABLE'], verilator_make_gmake=False, make_top_shell=False, make_main=False) test.file_grep(test.stats, r'Optimizations, Loop unrolling, Pragma unroll_disable\s+(\d+)', 4) test.file_grep(test.stats, r'Optimizations, Loop unrolling, Unrolled loops\s+(\d+)', 0) test.passes() verilator-5.042/test_regress/t/t_sys_readmem_4state.mem0000644000542200017500000000054515101701376023711 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test data file // // Copyright 2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 0 1 x X z Z verilator-5.042/test_regress/t/t_class_param_bad_paren.v0000644000542200017500000000125015101701376024056 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class Cls #(int PARAM = 1); parameter OTHER = 12; endclass class Other extends Cls#(); // Ok endclass class OtherMaybe extends Cls; // Questionable but others do not warn endclass module t; typedef Cls#(2) Cls2_t; // Ok typedef Cls ClsNone_t; // Ok Cls c; // Ok initial begin if (Cls#()::OTHER != 12) $stop; // Ok if (Cls2_t::OTHER != 12) $stop; // ok if (Cls::OTHER != 12) $stop; // Bad #() required end endmodule verilator-5.042/test_regress/t/t_covergroup_in_class_with_sample.v0000644000542200017500000000064715101701376026251 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off COVERIGN */ class C; covergroup embedded(int x) with function sample (int a, bit b); endgroup function new(); embedded = new(1); embedded.sample(2, 1'b0); endfunction endclass verilator-5.042/test_regress/t/t_genfor_hier.py0000755000542200017500000000073415101701376022261 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_dfg_3817.v0000644000542200017500000000063515101701376021026 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module for issue #3817 // addDriver() was causing use-after-free and segfaulting during Verilation // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Jevin Sweval. // SPDX-License-Identifier: CC0-1.0 module t ( output [2:0] c_b_a, input a, input b, input c ); assign c_b_a = {c, {b, a}}; endmodule verilator-5.042/test_regress/t/t_altera_lpm_ram_dp.py0000755000542200017500000000111115101701376023422 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) test.compile(verilator_flags2=["--top-module", module]) test.passes() verilator-5.042/test_regress/t/t_gen_upscope.v0000644000542200017500000000404015101701376022105 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 /* Acceptable answer 1 created tag with scope = top.t.tag created tag with scope = top.t.b.gen[0].tag created tag with scope = top.t.b.gen[1].tag mod a has scope = top.t mod a has tag = top.t.tag mod b has scope = top.t.b mod b has tag = top.t.tag mod c has scope = top.t.b.gen[0].c mod c has tag = top.t.b.gen[0].tag mod c has scope = top.t.b.gen[1].c mod c has tag = top.t.b.gen[1].tag */ /* Acceptable answer 2 created tag with scope = top.t.tag created tag with scope = top.t.b.gen[0].tag created tag with scope = top.t.b.gen[1].tag mod a has scope = top.t mod a has tag = top.t.tag mod b has scope = top.t.b mod b has tag = top.t.tag mod c has scope = top.t.b.gen[0].c mod c has tag = top.t.tag mod c has scope = top.t.b.gen[1].c mod c has tag = top.t.tag */ module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; tag tag (); b b (); always @ (t.cyc) begin if (t.cyc == 2) $display("mod a has scope = %m"); if (t.cyc == 2) $display("mod a has tag = %0s", tag.scope); end always @(posedge clk) begin cyc <= cyc + 1; if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module b (); genvar g; generate for (g=0; g<2; g++) begin : gen tag tag (); c c (); end endgenerate always @ (t.cyc) begin if (t.cyc == 3) $display("mod b has scope = %m"); if (t.cyc == 3) $display("mod b has tag = %0s", tag.scope); end endmodule module c (); always @ (t.cyc) begin if (t.cyc == 4) $display("mod c has scope = %m"); if (t.cyc == 4) $display("mod c has tag = %0s", tag.scope); end endmodule module tag (); bit [100*8-1:0] scope; initial begin $sformat(scope,"%m"); $display("created tag with scope = %0s",scope); end endmodule verilator-5.042/test_regress/t/t_struct_pat_toomany_bad.py0000755000542200017500000000076615101701376024543 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_math_pow2.v0000644000542200017500000000266215101701376021506 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Aggregate outputs into a single result vector //wire [31:0] pow32b = {24'h0,crc[15:8]}**crc[7:0]; // Overflows wire [3:0] pow4b = crc[7:4] ** crc[3:0]; wire [31:0] pow2 = 2 ** crc[3:0]; // Optimizes to shift wire [63:0] result = {pow2, 28'h0, pow4b}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; `define EXPECTED_SUM 64'h056ea1c5a63aff6a if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_select_little_pack.py0000755000542200017500000000073415101701376023624 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_math_signed7.v0000644000542200017500000000227415101701376022156 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Iztok Jeras. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module t (/*AUTOARG*/ // Inputs clk ); input clk; reg alu_ltu, alu_lts; logic [3:0] in_op1; logic [3:0] in_op2; reg aaa_ltu, aaa_lts; always @(posedge clk) begin in_op1 = 4'sb1110; in_op2 = 4'b0010; aaa_ltu = in_op1 < in_op2; // bug999 aaa_lts = $signed(in_op1) < $signed(in_op2); `checkh (aaa_ltu, 1'b0); `checkh (aaa_lts, 1'b1); end generate if (1) begin always @(posedge clk) begin in_op1 = 4'sb1110; in_op2 = 4'b0010; alu_ltu = in_op1 < in_op2; // bug999 alu_lts = $signed(in_op1) < $signed(in_op2); `checkh (alu_ltu, 1'b0); `checkh (alu_lts, 1'b1); $write("*-* All Finished *-*\n"); $finish; end end endgenerate endmodule verilator-5.042/test_regress/t/t_opt_localize_deep.v0000644000542200017500000001071115101701376023261 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 `ifdef verilator `define dontOptimize $c1("1") `else `define dontOptimize 1'b1 `endif module t (/*AUTOARG*/ // Inputs clk ); input clk; int cyc = 0; int x = 0; always @(posedge clk) begin cyc <= cyc + 1; x = 32'hcafe1234; // verilog_format: off if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) x = cyc; // verilog_format: on $write("[%0t] cyc=%0d x=%x\n", $time, cyc, x); if (x !== cyc) $stop; if (cyc == 99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_dpi_imp_gen.py0000755000542200017500000000077615101701376022252 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=["t/t_dpi_imp_gen_c.cpp"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_cast_class_incompat_bad.v0000644000542200017500000000114215101701376024415 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Base; endclass class BaseExtended extends Base; endclass class Other; endclass typedef Base Base_t; typedef BaseExtended BaseExtended_t; typedef Other Other_t; module t; Base_t cls_a; BaseExtended_t cls_ab; Other_t other; initial begin cls_a = new; cls_ab = BaseExtended'(cls_a); // bad-need dyn other = Other'(cls_ab); // bad-incompat end endmodule verilator-5.042/test_regress/t/t_timing_trace_fst.out0000644000542200017500000000127215101701376023465 0ustar mahmoudyfreeshell$date Tue Jun 10 19:01:39 2025 $end $version fstWriter $end $timescale 1ps $end $scope module t $end $var parameter 32 ! CLK_PERIOD [31:0] $end $var parameter 32 " CLK_HALF_PERIOD [31:0] $end $var logic 1 # rst $end $var logic 1 $ clk $end $var logic 1 % a $end $var logic 1 & b $end $var logic 1 ' c $end $var logic 1 ( d $end $var event 1 ) ev $end $upscope $end $enddefinitions $end #0 $dumpvars 1) 0( 1' 1& 0% 0$ 1# b00000000000000000000000000000101 " b00000000000000000000000000001010 ! $end #5 1$ #10 0$ 0' 1) #15 1$ #20 0$ 1) 1' #25 1$ #30 0$ 0' 1) #35 1$ #40 0$ 1) 1' #45 1$ #50 0$ 0' 1) #55 1$ #60 0$ 1) 1' #65 1$ #70 0$ 0' 1) #75 1$ #80 0$ 1) 1' #85 1$ #90 0$ 0' 1) #95 1$ #100 0$ 0& verilator-5.042/test_regress/t/t_vpi_finish.v0000644000542200017500000000077015101701376021742 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; import "DPI-C" function void dpii_test(); initial begin $write("*-* All Finished *-*\n"); dpii_test(); // $finish end endmodule verilator-5.042/test_regress/t/t_compiler_include_dpi.py0000755000542200017500000000135515101701376024143 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_compiler_include_dpi.v" test.compile(v_flags2=["t/t_compiler_include_dpi.cpp"], verilator_flags2=[ "-Wall -Wno-DECLFILENAME --compiler-include", test.t_dir + "/t_compiler_include_dpi.h", "--output-split 0" ]) test.execute() test.passes() verilator-5.042/test_regress/t/t_dpi_2exparg_bad.v0000644000542200017500000000146515101701376022620 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2023 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module a; import "DPI-C" task dpii_twice; // Legal export "DPI-C" task dpix_twice; // Bad task dpix_twice(input int i, output [2:0] o); o = ~i; endtask initial dpii_twice(); endmodule module b; import "DPI-C" task dpii_twice; // Legal export "DPI-C" task dpix_twice; // Bad task dpix_twice(input int i, output [63:0] o); o = ~i; endtask initial dpii_twice(); endmodule module t; a a(); b b(); initial begin $stop; end endmodule verilator-5.042/test_regress/t/t_tri_and_eqcase.v0000644000542200017500000000065015101701376022542 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t (clk1, clk2); input wire clk1, clk2; logic b = 1'bz === (clk1 & clk2); always begin if (!b) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_hier_block_threads_bad.out0000644000542200017500000000133115101701376024561 0ustar mahmoudyfreeshell%Error: t/t_hier_block_threads_bad.v:23:8: Hierarchical blocks cannot be scheduled on more threads than in thread pool, threads = 4 hierarchical block threads = 8 : ... note: In instance 't.genblk1[1].hierCore' 23 | module Core(input clk); /*verilator hier_block*/ | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error-UNSUPPORTED: t/t_hier_block_threads_bad.vlt:9:1: Specifying workers for nested hierarchical blocks 9 | hier_workers -module "SubCore" -workers 8 | ^~~~~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_dpi_2exparg_bad.py0000755000542200017500000000077615101701376023012 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_super_bad3.py0000755000542200017500000000076615101701376023213 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_trace_two_a.v0000644000542200017500000000355215101701376022074 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define CONCAT(a, b) a``b `define STRINGIFY(x) `"x`" module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; integer c_trace_on; sub sub (); // verilator tracing_off string filename; // verilator tracing_on initial begin `ifdef TEST_FST filename = {`STRINGIFY(`TEST_OBJ_DIR), "/simx.fst"}; `else filename = {`STRINGIFY(`TEST_OBJ_DIR), "/simx.vcd"}; `endif `ifdef TEST_DUMP $dumpfile(filename); $dumpvars(0); // Intentionally no ", top" for parsing coverage with just (expr) $dumpvars(1, top); // Intentionally checking parsing coverage $dumpvars(1, top, top); // Intentionally checking parsing coverage $dumplimit(10 * 1024 * 1024); `elsif TEST_DUMPPORTS $dumpports(top, filename); $dumpportslimit(10 * 1024 * 1024, filename); `endif end always @ (posedge clk) begin if (cyc != 0) begin cyc <= cyc + 1; c_trace_on <= cyc + 2; if (cyc == 3) begin `ifdef TEST_DUMP $dumpoff; `elsif TEST_DUMPPORTS $dumpportsoff(filename); `endif end else if (cyc == 5) begin `ifdef TEST_DUMP $dumpall; $dumpflush; `elsif TEST_DUMPPORTS $dumpportsall(filename); $dumpportsflush(filename); `endif end else if (cyc == 7) begin `ifdef TEST_DUMP $dumpon; `elsif TEST_DUMPPORTS $dumpportson(filename); `endif end else if (cyc == 10) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module sub; integer inside_sub_a = 1; endmodule verilator-5.042/test_regress/t/t_assert_unique_case_bad.v0000644000542200017500000000241515101701376024272 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Yutetsu TAKATSUKASA. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs hit, // Inputs clk ); input clk; output logic hit; logic [31:0] addr; logic [11:0] match_item0, match_item1; int cyc; string s; initial addr = 32'h380; always @ (posedge clk) begin cyc <= cyc + 1; addr <= 32'h380 + cyc; match_item0 = 12'h 380 + cyc[11:0]; match_item1 = 12'h 390 - cyc[11:0]; $sformat(s, "%1d", cyc); if (cyc == 9) begin $write("*-* All Finished *-*\n"); $finish; end end always_comb begin hit = 1; unique case (addr[11:0]) match_item0: $display("match_item0"); match_item1: $display("match_item1"); default: hit = 0; endcase end `ifdef NO_STOP_FAIL always_comb begin unique case (s) "": ; "0": ; "2": ; "4": ; "6": ; endcase end always_comb begin priority case (s) $sformatf("%1d", cyc - 1): ; "0": ; "6": ; endcase end `endif endmodule verilator-5.042/test_regress/t/t_case_genx_bad.py0000755000542200017500000000076615101701376022541 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_trace_two_cc.cpp0000644000542200017500000000454415101701376022560 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test // // Copyright 2003-2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // clang-format off #include "verilatedos.h" #include VM_PREFIX_INCLUDE #include "Vt_trace_two_b.h" #include "verilated.h" #ifdef TEST_HDR_TRACE # ifdef TEST_FST # include "verilated_fst_c.h" # else # include "verilated_vcd_c.h" # endif #endif // clang-format on // Compile in place #include "Vt_trace_two_b__ALL.cpp" VM_PREFIX* ap; Vt_trace_two_b* bp; int main(int argc, char** argv) { const std::unique_ptr contextp{new VerilatedContext}; uint64_t sim_time = 1100; contextp->debug(0); contextp->commandArgs(argc, argv); contextp->traceEverOn(true); srand48(5); ap = new VM_PREFIX{contextp.get(), "topa"}; bp = new Vt_trace_two_b{contextp.get(), "topb"}; // clang-format off #ifdef TEST_HDR_TRACE contextp->traceEverOn(true); # ifdef TEST_FST VerilatedFstC* tfp = new VerilatedFstC; ap->trace(tfp, 99); bp->trace(tfp, 99); tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.fst"); # else VerilatedVcdC* tfp = new VerilatedVcdC; ap->trace(tfp, 99); bp->trace(tfp, 99); tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); # endif #endif // clang-format on #ifdef TEST_HDR_TRACE ap->eval_step(); bp->eval_step(); ap->eval_end_step(); bp->eval_end_step(); if (tfp) tfp->dump(contextp->time()); #endif { ap->clk = false; contextp->timeInc(10); } while (contextp->time() < sim_time && !contextp->gotFinish()) { ap->clk = !ap->clk; bp->clk = ap->clk; ap->eval_step(); bp->eval_step(); ap->eval_end_step(); bp->eval_end_step(); #ifdef TEST_HDR_TRACE if (tfp) tfp->dump(contextp->time()); #endif contextp->timeInc(5); } if (!contextp->gotFinish()) { vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); } ap->final(); bp->final(); #ifdef TEST_HDR_TRACE if (tfp) tfp->close(); VL_DO_DANGLING(delete tfp, tfp); #endif VL_DO_DANGLING(delete ap, ap); VL_DO_DANGLING(delete bp, bp); return 0; } verilator-5.042/test_regress/t/t_interface_parent_scope.py0000755000542200017500000000107515101701376024473 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint( # Should fail, Verilator unsupported, bug1623 # expect_filename = test.golden_filename, fails=not test.vlt) test.passes() verilator-5.042/test_regress/t/t_interface_array_noinl.py0000755000542200017500000000104015101701376024316 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_array.v" test.compile(v_flags2=["-fno-inline"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_arraysel_wide.py0000755000542200017500000000071415101701376022622 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.passes() verilator-5.042/test_regress/t/t_string_size.out0000644000542200017500000000022315101701376022477 0ustar mahmoudyfreeshell> < == >< (or > < also legal) > < == >< (or > < also legal) > < == > < > < == > < > < == > < >< == >< *-* All Finished *-* verilator-5.042/test_regress/t/t_vpi_finish_c.cpp0000644000542200017500000000145715101701376022564 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2009-2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #include "svdpi.h" #include "vpi_user.h" #include #include //====================================================================== extern "C" { extern void dpii_test(); } //====================================================================== void dpii_test() { vpi_control(vpiFinish); } verilator-5.042/test_regress/t/t_lint_iface_topmodule3.py0000755000542200017500000000070615101701376024241 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.042/test_regress/t/t_gantt_io_arm.dat0000644000542200017500000000460015101701376022546 0ustar mahmoudyfreeshellVLPROFVERSION 2.0 VLPROF arg +verilator+prof+exec+start+1 VLPROF arg +verilator+prof+exec+window+2 VLPROF info numa 0,2;1,3 VLPROF stat threads 2 VLPROF stat yields 51 VLPROFPROC processor : 0 VLPROFPROC model name : Phytium,FT-2500/128 VLPROFPROC BogoMIPS : 100.00 VLPROFPROC Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid VLPROFPROC CPU implementer : 0x70 VLPROFPROC CPU architecture: 8 VLPROFPROC CPU variant : 0x1 VLPROFPROC CPU part : 0x663 VLPROFPROC CPU revision : 3 VLPROFPROC VLPROFPROC processor : 1 VLPROFPROC model name : Phytium,FT-2500/128 VLPROFPROC BogoMIPS : 100.00 VLPROFPROC Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid VLPROFPROC CPU implementer : 0x70 VLPROFPROC CPU architecture: 8 VLPROFPROC CPU variant : 0x1 VLPROFPROC CPU part : 0x663 VLPROFPROC CPU revision : 3 VLPROFPROC VLPROFPROC processor : 2 VLPROFPROC model name : Phytium,FT-2500/128 VLPROFPROC BogoMIPS : 100.00 VLPROFPROC Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid VLPROFPROC CPU implementer : 0x70 VLPROFPROC CPU architecture: 8 VLPROFPROC CPU variant : 0x1 VLPROFPROC CPU part : 0x663 VLPROFPROC CPU revision : 3 VLPROFPROC VLPROFPROC processor : 3 VLPROFPROC model name : Phytium,FT-2500/128 VLPROFPROC BogoMIPS : 100.00 VLPROFPROC Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid VLPROFPROC CPU implementer : 0x70 VLPROFPROC CPU architecture: 8 VLPROFPROC CPU variant : 0x1 VLPROFPROC CPU part : 0x663 VLPROFPROC CPU revision : 3 VLPROFPROC VLPROFTHREAD 0 VLPROFEXEC EXEC_GRAPH_BEGIN 58532 VLPROFEXEC MTASK_BEGIN 90465 id 85 predictStart 14315 cpu 2 VLPROFEXEC MTASK_END 155034 predictCost 30533 VLPROFEXEC MTASK_BEGIN 156555 id 79 predictStart 44848 cpu 2 VLPROFEXEC MTASK_END 294309 predictCost 48001 VLPROFEXEC THREAD_SCHEDULE_WAIT_BEGIN 295000 cpu 2 VLPROFEXEC THREAD_SCHEDULE_WAIT_END 296000 cpu 2 VLPROFEXEC EXEC_GRAPH_END 300000 VLPROFTHREAD 1 VLPROFEXEC MTASK_BEGIN 77352 id 90 predictStart 14315 cpu 3 VLPROFEXEC MTASK_END 78511 predictCost 21592 VLPROFEXEC MTASK_BEGIN 79799 id 81 predictStart 35907 cpu 3 VLPROFEXEC MTASK_END 80667 predictCost 29215 VLPROFEXEC MTASK_BEGIN 81746 id 87 predictStart 65147 cpu 3 VLPROFEXEC MTASK_END 82633 predictCost 33809 VLPROFEXEC THREAD_SCHEDULE_WAIT_BEGIN 83000 cpu 3 VLPROFEXEC THREAD_SCHEDULE_WAIT_END 84000 cpu 3 VLPROF stat ticks 300000 verilator-5.042/test_regress/t/t_class_param_enum_bad.v0000644000542200017500000000123215101701376023715 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 typedef enum bit {A = 0, B = 1} enum_t; class Converter #(type T); function int toInt(T t); return int'(t); endfunction endclass module t; initial begin Converter#(enum_t) conv1 = new; // enum types does not match with other types (IEEE 1800-2023 6.22.1 and 6.22.4) // The assignment and the function call should throw an error. Converter#(bit) conv2 = conv1; conv1.toInt(0); $stop; end endmodule verilator-5.042/test_regress/t/t_enum_huge_methods.v0000644000542200017500000000404715101701376023304 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t (/*AUTOARG*/ // Inputs clk ); input clk; typedef enum logic [59:0] { E01 = 60'h1, ELARGE = 60'h1234_4567_abcd } my_t; integer cyc = 0; my_t e; string all; int i_cast; // Check runtime always @ (posedge clk) begin cyc <= cyc + 1; if (cyc == 0) begin // Setup e <= E01; end else if (cyc == 1) begin `checks(e.name, "E01"); `checkh(e.next, ELARGE); `checkh(e.next(0), E01); `checkh(e.prev(0), E01); e <= ELARGE; end else if (cyc == 3) begin `checks(e.name, "ELARGE"); `checkh(e.next, E01); `checkh(e.prev, E01); `checkh(e.next(0), ELARGE); `checkh(e.prev(0), ELARGE); e <= E01; end // else if (cyc == 10) begin i_cast <= $cast(e, 60'h1234); end else if (cyc == 11) begin `checkh(i_cast, 0); i_cast <= $cast(e, 60'h1); end else if (cyc == 12) begin `checkh(i_cast, 1); i_cast <= $cast(e, 60'h1234_4567_abcd); end else if (cyc == 13) begin `checkh(i_cast, 1); end // else if (cyc == 20) begin e <= my_t'('h11); // Unknown end else if (cyc == 21) begin `checks(e.name, ""); // Unknown end else if (cyc == 99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_mem_slice_dtype_bad.v0000644000542200017500000000162215101701376023551 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014 by Alex Solomatnikov. // SPDX-License-Identifier: CC0-1.0 typedef logic [$clog2(26+1)-1:0] way_cnt_t; module t(/*AUTOARG*/ // Inputs clk ); input logic clk; int cyc; //bug795 way_cnt_t completed_cnt [31:0][1:0]; way_cnt_t completed_cnt_dp [1:0]; assign completed_cnt_dp = completed_cnt[id]; always_ff @(posedge clk) begin completed_cnt[id] <= completed_cnt_dp + 1; end // bug796 logic [4:0] id; logic [39:0] way_mask; logic [39:0] addr[31:0][1:0]; always_ff @(posedge clk) begin cyc <= cyc + 1; id <= cyc[4:0]; if (cyc==1) begin way_mask <= '0; id <= 1; end else if (cyc==2) begin assert((addr[id] & way_mask) == 0); end end endmodule verilator-5.042/test_regress/t/t_class_param_typedef.py0000755000542200017500000000073415101701376023777 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_warn_line_bad.v0000644000542200017500000000065115101701376023414 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Check that `line `__LINE__ still shows proper warning context `line `__LINE__ "the_line_file" 1 `line `__LINE__ "the_line_file" 2 module t; int warn_t = 64'h1; // Not suppressed - should warn endmodule verilator-5.042/test_regress/t/t_interface_paren_missing_bad.py0000755000542200017500000000076315101701376025460 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_pinmissing_bad.py0000755000542200017500000000143515101701376024005 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.extract(in_filename=test.top_filename, out_filename=test.root + "/docs/gen/ex_PINMISSING_faulty.rst", lines="7-12") test.extract(in_filename=test.golden_filename, out_filename=test.root + "/docs/gen/ex_PINMISSING_msg.rst", lines="1-1") test.passes() verilator-5.042/test_regress/t/t_var_outoforder.v0000644000542200017500000000311315101701376022636 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2004 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; reg [125:0] a; wire q; sub sub ( .q (q), .a (a), .clk (clk)); always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==1) begin a <= 126'b1000; end if (cyc==2) begin a <= 126'h1001; end if (cyc==3) begin a <= 126'h1010; end if (cyc==4) begin a <= 126'h1111; if (q !== 1'b0) $stop; end if (cyc==5) begin if (q !== 1'b1) $stop; end if (cyc==6) begin if (q !== 1'b0) $stop; end if (cyc==7) begin if (q !== 1'b0) $stop; end if (cyc==8) begin if (q !== 1'b0) $stop; $write("*-* All Finished *-*\n"); $finish; end end end endmodule module sub ( input clk, input [125:0] a, output reg q ); // verilator public_module reg [125:0] g_r; wire [127:0] g_extend = { g_r, 1'b1, 1'b0 }; reg [6:0] sel; wire g_sel = g_extend[sel]; always @ (posedge clk) begin g_r <= a; sel <= a[6:0]; q <= g_sel; end endmodule verilator-5.042/test_regress/t/t_clk_dpulse.py0000755000542200017500000000073415101701376022117 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_dpi_lib.py0000755000542200017500000000105015101701376021364 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=["t/t_dpi_lib_c.cpp"], verilator_flags2=["-Wall -Wno-DECLFILENAME"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_unpacked_concat_bad3.out0000644000542200017500000000125015101701376024152 0ustar mahmoudyfreeshell%Error: t/t_unpacked_concat_bad3.v:9:41: Assignment pattern missed initializing elements: 3 : ... note: In instance 't' 9 | localparam logic [7:0] TOO_FEW [5] = '{0, 1, 2**8-1}; | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_unpacked_concat_bad3.v:9:41: Assignment pattern missed initializing elements: 4 : ... note: In instance 't' 9 | localparam logic [7:0] TOO_FEW [5] = '{0, 1, 2**8-1}; | ^~ %Error: Exiting due to verilator-5.042/test_regress/t/t_lint_warn_incfile2_bad.py0000755000542200017500000000115615101701376024347 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint( # See also t/t_lint_warn_incfile1_bad # See also t/t_vlt_warn_file_bad verilator_flags2=["--no-std"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_warn_incfile2_bad.out0000644000542200017500000000104215101701376024515 0ustar mahmoudyfreeshell%Warning-WIDTHTRUNC: t/t_lint_warn_incfile2_bad.v:13:17: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's CONST '64'h1' generates 64 bits. : ... note: In instance 't' 13 | int warn_t = 64'h1; | ^~~~~ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_sys_writemem.py0000755000542200017500000000300615101701376022514 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_sys_readmem.v" # Use random reset to ensure we're fully initializing arrays before # $writememh, to avoid miscompares with X's on 4-state simulators. test.verilated_randReset = 2 # 2 == truly random # TODO make test more generic to take the data type as a define # then we can call test multiple times in different tests test.compile(v_flags2=[ '+define+WRITEMEM_READ_BACK=1', '\'+define+OUT_TMP1=\"' + test.obj_dir + '/tmp1.mem\"\'', '\'+define+OUT_TMP2=\"' + test.obj_dir + '/tmp2.mem\"\'', '\'+define+OUT_TMP3=\"' + test.obj_dir + '/tmp3.mem\"\'', '\'+define+OUT_TMP4=\"' + test.obj_dir + '/tmp4.mem\"\'', '\'+define+OUT_TMP5=\"' + test.obj_dir + '/tmp5.mem\"\'', '\'+define+OUT_TMP6=\"' + test.obj_dir + '/tmp6.mem\"\'', '\'+define+OUT_TMP7=\"' + test.obj_dir + '/tmp7.mem\"\'', '\'+define+OUT_TMP8=\"' + test.obj_dir + '/tmp8.mem\"\'', ]) test.execute() for i in range(1, 9): gold = test.t_dir + "/t_sys_writemem.gold" + str(i) + ".mem" out = test.obj_dir + "/tmp" + str(i) + ".mem" test.files_identical(out, gold) test.passes() verilator-5.042/test_regress/t/t_lint_only.py0000755000542200017500000000154715101701376022004 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint() for filename in glob.glob(test.obj_dir + "/*"): if (re.search(r'\.log', filename) # Made by driver.py, not Verilator sources or re.search(r'\.status', filename) # Made by driver.py, not Verilator sources or re.search(r'\.gcda', filename)): # Made by gcov, not Verilator sources continue test.error("%Error: Created '" + filename + "', but --lint-only shouldn't create files") test.passes() verilator-5.042/test_regress/t/t_udp_sequential.py0000755000542200017500000000073415101701376023014 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_flag_werror.v0000644000542200017500000000043715101701376022115 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; // Width error below wire [3:0] foo = 6'h2e; endmodule verilator-5.042/test_regress/t/t_inst_tree_inl1_pub1.vlt0000644000542200017500000000041715101701376024010 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. // SPDX-License-Identifier: CC0-1.0 `verilator_config inline -module "l*" public -module "l*" -var "z*" verilator-5.042/test_regress/t/t_parse_eof_str_bad.py0000755000542200017500000000110515101701376023424 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=['--debug-preproc-passthru', '--no-std'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_package_struct.out0000644000542200017500000000005115101701376023135 0ustar mahmoudyfreeshellhello, world (0, 0) *-* All Finished *-* verilator-5.042/test_regress/t/t_param_type_cmp.py0000755000542200017500000000077115101701376022773 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--binary']) test.execute() test.passes() verilator-5.042/test_regress/t/t_func_wide_out_bad.out0000644000542200017500000001466515101701376023616 0ustar mahmoudyfreeshell%Warning-WIDTHTRUNC: t/t_func_wide_out.v:76:27: Function output argument 'value' requires 12 bits, but connection's VARREF 'ds70' generates 70 bits. : ... note: In instance 't' 76 | Cls#(s12_t)::get(ds70); | ^~~~ ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. %Warning-WIDTHTRUNC: t/t_func_wide_out.v:76:23: Operator TASKREF 'get' expects 12 bits on the Function Argument, but Function Argument's VARREF 'ds70' generates 70 bits. : ... note: In instance 't' 76 | Cls#(s12_t)::get(ds70); | ^~~ %Warning-WIDTHTRUNC: t/t_func_wide_out.v:79:27: Function output argument 'value' requires 12 bits, but connection's VARREF 'ds70' generates 70 bits. : ... note: In instance 't' 79 | Cls#(s12_t)::get(ds70); | ^~~~ %Warning-WIDTHTRUNC: t/t_func_wide_out.v:79:23: Operator TASKREF 'get' expects 12 bits on the Function Argument, but Function Argument's VARREF 'ds70' generates 70 bits. : ... note: In instance 't' 79 | Cls#(s12_t)::get(ds70); | ^~~ %Warning-WIDTHTRUNC: t/t_func_wide_out.v:83:27: Function output argument 'value' requires 12 bits, but connection's VARREF 'du70' generates 70 bits. : ... note: In instance 't' 83 | Cls#(u12_t)::get(du70); | ^~~~ %Warning-WIDTHTRUNC: t/t_func_wide_out.v:83:23: Operator TASKREF 'get' expects 12 bits on the Function Argument, but Function Argument's VARREF 'du70' generates 70 bits. : ... note: In instance 't' 83 | Cls#(u12_t)::get(du70); | ^~~ %Warning-WIDTHTRUNC: t/t_func_wide_out.v:86:27: Function output argument 'value' requires 12 bits, but connection's VARREF 'du70' generates 70 bits. : ... note: In instance 't' 86 | Cls#(u12_t)::get(du70); | ^~~~ %Warning-WIDTHTRUNC: t/t_func_wide_out.v:86:23: Operator TASKREF 'get' expects 12 bits on the Function Argument, but Function Argument's VARREF 'du70' generates 70 bits. : ... note: In instance 't' 86 | Cls#(u12_t)::get(du70); | ^~~ %Warning-WIDTHTRUNC: t/t_func_wide_out.v:108:10: Operator TASKREF 'dpii_inv_s12' expects 12 bits on the Function Argument, but Function Argument's VARREF 'ds70' generates 70 bits. : ... note: In instance 't' 108 | dpii_inv_s12(ds70, qs70); | ^~~~~~~~~~~~ %Warning-WIDTHTRUNC: t/t_func_wide_out.v:108:29: Function output argument 'out' requires 12 bits, but connection's VARREF 'qs70' generates 70 bits. : ... note: In instance 't' 108 | dpii_inv_s12(ds70, qs70); | ^~~~ %Warning-WIDTHTRUNC: t/t_func_wide_out.v:108:10: Operator TASKREF 'dpii_inv_s12' expects 12 bits on the Function Argument, but Function Argument's VARREF 'qs70' generates 70 bits. : ... note: In instance 't' 108 | dpii_inv_s12(ds70, qs70); | ^~~~~~~~~~~~ %Warning-WIDTHTRUNC: t/t_func_wide_out.v:111:10: Operator TASKREF 'dpii_inv_s12' expects 12 bits on the Function Argument, but Function Argument's VARREF 'ds70' generates 70 bits. : ... note: In instance 't' 111 | dpii_inv_s12(ds70, qs70); | ^~~~~~~~~~~~ %Warning-WIDTHTRUNC: t/t_func_wide_out.v:111:29: Function output argument 'out' requires 12 bits, but connection's VARREF 'qs70' generates 70 bits. : ... note: In instance 't' 111 | dpii_inv_s12(ds70, qs70); | ^~~~ %Warning-WIDTHTRUNC: t/t_func_wide_out.v:111:10: Operator TASKREF 'dpii_inv_s12' expects 12 bits on the Function Argument, but Function Argument's VARREF 'qs70' generates 70 bits. : ... note: In instance 't' 111 | dpii_inv_s12(ds70, qs70); | ^~~~~~~~~~~~ %Warning-WIDTHTRUNC: t/t_func_wide_out.v:115:10: Operator TASKREF 'dpii_inv_u12' expects 12 bits on the Function Argument, but Function Argument's VARREF 'du70' generates 70 bits. : ... note: In instance 't' 115 | dpii_inv_u12(du70, qu70); | ^~~~~~~~~~~~ %Warning-WIDTHTRUNC: t/t_func_wide_out.v:115:29: Function output argument 'out' requires 12 bits, but connection's VARREF 'qu70' generates 70 bits. : ... note: In instance 't' 115 | dpii_inv_u12(du70, qu70); | ^~~~ %Warning-WIDTHTRUNC: t/t_func_wide_out.v:115:10: Operator TASKREF 'dpii_inv_u12' expects 12 bits on the Function Argument, but Function Argument's VARREF 'qu70' generates 70 bits. : ... note: In instance 't' 115 | dpii_inv_u12(du70, qu70); | ^~~~~~~~~~~~ %Warning-WIDTHTRUNC: t/t_func_wide_out.v:118:10: Operator TASKREF 'dpii_inv_u12' expects 12 bits on the Function Argument, but Function Argument's VARREF 'du70' generates 70 bits. : ... note: In instance 't' 118 | dpii_inv_u12(du70, qu70); | ^~~~~~~~~~~~ %Warning-WIDTHTRUNC: t/t_func_wide_out.v:118:29: Function output argument 'out' requires 12 bits, but connection's VARREF 'qu70' generates 70 bits. : ... note: In instance 't' 118 | dpii_inv_u12(du70, qu70); | ^~~~ %Warning-WIDTHTRUNC: t/t_func_wide_out.v:118:10: Operator TASKREF 'dpii_inv_u12' expects 12 bits on the Function Argument, but Function Argument's VARREF 'qu70' generates 70 bits. : ... note: In instance 't' 118 | dpii_inv_u12(du70, qu70); | ^~~~~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_func_under2.py0000755000542200017500000000073415101701376022204 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_disable_task_simple.v0000644000542200017500000000144215101701376023577 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 class Cls; int x = 0; int y = 0; task disable_outside_fork; fork : fork_blk begin x = 1; #2; x = 2; end join_none #1; disable fork_blk; endtask task disable_inside_fork; fork : fork_blk begin y = 1; disable fork_blk; y = 2; end join_none endtask endclass module t; initial begin Cls c = new; c.disable_outside_fork(); #2; if (c.x != 1) $stop; c.disable_inside_fork(); if (c.y != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_select_bad_msb.out0000644000542200017500000000162415101701376023073 0ustar mahmoudyfreeshell%Warning-ASCRANGE: t/t_select_bad_msb.v:12:8: Ascending bit range vector: left < right of bit range: [0:22] : ... note: In instance 't' 12 | reg [0:22] backwd; | ^ ... For warning description see https://verilator.org/warn/ASCRANGE?v=latest ... Use "/* verilator lint_off ASCRANGE */" and lint_on around source to disable this message. %Warning-SELRANGE: t/t_select_bad_msb.v:16:16: [1:4] Slice range has ascending bit ordering, perhaps you wanted [4:1] : ... note: In instance 't' 16 | sel2 = mi[1:4]; | ^ ... For warning description see https://verilator.org/warn/SELRANGE?v=latest ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_array_backw_index_bad.py0000755000542200017500000000076615101701376024261 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_vpi_repetitive_cbs.v0000644000542200017500000000074015101701376023466 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 Wilson Snyder and Marlon James. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs input clk ); reg [31:0] count /*verilator public_flat_rd */; // Test loop initial begin count = 0; end always @(posedge clk) begin count <= count + 2; end endmodule : t verilator-5.042/test_regress/t/t_hier_block_signed_logic.v0000644000542200017500000000256215101701376024414 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2024 by Antmicro. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t(/*AUTOARG*/ // inputs clk ); input clk; logic signed [31:0] in1 = 3; logic signed [31:0] in2 = 4; logic signed in_small1 = 1; logic signed in_small2 = -1; logic signed [31:0] out1; logic signed [31:0] out2; logic signed out_small1; logic signed out_small2; sub sub1(.in(in1), .in_small(in_small1), .out(out1), .out_small(out_small1)); sub sub2(.in(in2), .in_small(in_small2), .out(out2), .out_small(out_small2)); always_ff @(posedge clk) begin if (out1 == signed'(-3) && out2 == signed'(-4) && out_small1 == signed'(1'b1) && out_small2 == signed'(1'b1)) begin $write("*-* All Finished *-*\n"); $finish; end else begin $write("Mismatch\n"); $stop; end end endmodule module sub( input logic signed [31:0] in, input logic signed in_small, output logic signed [31:0] out, output logic signed out_small ); /*verilator hier_block*/ assign out = -in; assign out_small = -in_small; endmodule verilator-5.042/test_regress/t/t_math_countbits_bad.v0000644000542200017500000000046315101701376023434 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 Yossi Nivin. // SPDX-License-Identifier: CC0-1.0 module t; integer count; assign count = $countbits(32'h123456, '0, '1, 'x, 'z); endmodule verilator-5.042/test_regress/t/t_var_rsvd_bad.py0000755000542200017500000000105015101701376022416 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.top_filename = "t/t_var_rsvd_port.v" test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_math_shortcircuit_dynsel.py0000755000542200017500000000073415101701376025103 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_preproc_eof1_bad.py0000755000542200017500000000076615101701376023171 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_func_const3_bad.v0000644000542200017500000000114015101701376022626 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 module c9 #(parameter A = 1, parameter B = 1); localparam BITS = A*B; localparam SOMEP = {BITS{1'b0}}; endmodule module b9 #(parameter A = 1); c9 #(.A (A), .B (9)) c9(); endmodule module t; b9 b9(); b9 #(.A (100)) b900(); b9 #(.A (1000)) b9k(); initial begin // Should never get here $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_param_in_func.py0000755000542200017500000000162615101701376022574 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--stats"]) test.execute() # The parameter array should have been put in the constant pool if test.vlt_all: test.file_grep(test.stats, r'ConstPool, Tables emitted\s+(\d+)', 3) # Shouldn't have any references to the parameter array for filename in (test.glob_some(test.obj_dir + "/" + test.vm_prefix + "*.h") + test.glob_some(test.obj_dir + "/" + test.vm_prefix + "*.cpp")): test.file_grep_not(filename, r'digits') test.passes() verilator-5.042/test_regress/t/t_inst_nansi_param.v0000644000542200017500000000061415101701376023126 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module sub(i); parameter N = 3; input [N : 0] i; // Note 3:0 conflicts until parameterize wire [2:0] i; endmodule module t; wire [2:0] i; sub #(.N(2)) sub(.i); endmodule verilator-5.042/test_regress/t/t_assoc_wildcard_map.py0000755000542200017500000000076315101701376023612 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_queue_method2_bad.v0000644000542200017500000000105115101701376023151 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin int q[$]; int qe[$]; // Empty int qv[$]; // Value returns int qi[$]; // Index returns q = '{2, 2, 4, 1, 3}; qi = q.find(a,b) with (0); // b is extra qi = q.find(1) with (0); // 1 is illegal $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_recursive_module_bug_2.v0000644000542200017500000000130515101701376024231 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2022 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module a #(parameter N) (); generate if (N > 1) begin // With N == 5, this will first expand N == 2, then expand N == 3, // which instantiates N == 2. This requires fixing up topological order // in V3Param. a #(.N( N/2)) sub_lo(); a #(.N(N-N/2)) sub_hi(); end endgenerate endmodule module top(); a #(.N(5)) root (); endmodule verilator-5.042/test_regress/t/t_lint_unsup_deassign.py0000755000542200017500000000076015101701376024046 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--lint-only --bbox-unsup"]) test.passes() verilator-5.042/test_regress/t/t_a6_examples.py0000755000542200017500000000134515101701376022175 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') test.clean_command = '/bin/rm -rf ../examples/*/build ../examples/*/obj*' if not os.path.exists(test.root + "/.git"): test.skip("Not in a git repository") examples = sorted(test.glob_some(test.root + "/examples/*")) for example in examples: test.run(cmd=[os.environ["MAKE"], "-C", example]) test.passes() verilator-5.042/test_regress/t/t_order_quad.py0000755000542200017500000000112615101701376022113 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename, "-fno-dfg"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_forceable_net_cmt.py0000755000542200017500000000125315101701376023422 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.pli_filename = "t/t_forceable_net.cpp" test.top_filename = "t/t_forceable_net.v" test.compile(make_top_shell=False, make_main=False, verilator_flags2=['-DCMT=1', '--exe', test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_assoc_method_bad.out0000644000542200017500000000754615101701376023434 0ustar mahmoudyfreeshell%Error: t/t_assoc_method_bad.v:14:13: The 1 arguments passed to .num method does not match its requiring 0 arguments : ... note: In instance 't' 14 | v = a.num("badarg"); | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_assoc_method_bad.v:15:13: The 1 arguments passed to .size method does not match its requiring 0 arguments : ... note: In instance 't' 15 | v = a.size("badarg"); | ^~~~ %Error: t/t_assoc_method_bad.v:16:13: The 0 arguments passed to .exists method does not match its requiring 1 arguments : ... note: In instance 't' 16 | v = a.exists(); | ^~~~~~ %Error: t/t_assoc_method_bad.v:17:13: The 2 arguments passed to .exists method does not match its requiring 1 arguments : ... note: In instance 't' 17 | v = a.exists(k, "bad2"); | ^~~~~~ %Error: t/t_assoc_method_bad.v:18:13: The 0 arguments passed to .first method does not match its requiring 1 arguments : ... note: In instance 't' 18 | v = a.first(); | ^~~~~ %Error-UNSUPPORTED: t/t_assoc_method_bad.v:18:13: Unsupported: Non-variable on LHS of built-in method 'first' : ... note: In instance 't' 18 | v = a.first(); | ^~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: t/t_assoc_method_bad.v:19:13: The 2 arguments passed to .next method does not match its requiring 1 arguments : ... note: In instance 't' 19 | v = a.next(k, "bad2"); | ^~~~ %Error: t/t_assoc_method_bad.v:20:13: The 0 arguments passed to .last method does not match its requiring 1 arguments : ... note: In instance 't' 20 | v = a.last(); | ^~~~ %Error-UNSUPPORTED: t/t_assoc_method_bad.v:20:13: Unsupported: Non-variable on LHS of built-in method 'last' : ... note: In instance 't' 20 | v = a.last(); | ^~~~ %Error: t/t_assoc_method_bad.v:21:13: The 2 arguments passed to .prev method does not match its requiring 1 arguments : ... note: In instance 't' 21 | v = a.prev(k, "bad2"); | ^~~~ %Error: t/t_assoc_method_bad.v:22:9: The 2 arguments passed to .delete method does not match its requiring 0 to 1 arguments : ... note: In instance 't' 22 | a.delete(k, "bad2"); | ^~~~~~ %Error: t/t_assoc_method_bad.v:24:9: Array method 'sort' not legal on associative arrays : ... note: In instance 't' 24 | a.sort; | ^~~~ %Error: t/t_assoc_method_bad.v:25:9: Array method 'rsort' not legal on associative arrays : ... note: In instance 't' 25 | a.rsort; | ^~~~~ %Error: t/t_assoc_method_bad.v:26:9: Array method 'reverse' not legal on associative arrays : ... note: In instance 't' 26 | a.reverse; | ^~~~~~~ %Error: t/t_assoc_method_bad.v:27:9: Array method 'shuffle' not legal on associative arrays : ... note: In instance 't' 27 | a.shuffle; | ^~~~~~~ %Error: t/t_assoc_method_bad.v:29:9: Unknown built-in associative array method 'bad_not_defined' : ... note: In instance 't' 29 | a.bad_not_defined(); | ^~~~~~~~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_struct_packed_value_list.v0000644000542200017500000001211415101701376024661 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2009 by Iztok Jeras. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; localparam NO = 7; // number of access events // packed structures struct packed { logic e0; logic [1:0] e1; logic [3:0] e2; logic [7:0] e3; } struct_dsc; // descending range structure /* verilator lint_off ASCRANGE */ struct packed { logic e0; logic [0:1] e1; logic [0:3] e2; logic [0:7] e3; } struct_asc; // ascending range structure /* verilator lint_on ASCRANGE */ localparam WS = 15; // $bits(struct_dsc) integer cnt = 0; // event counter always @ (posedge clk) begin cnt <= cnt + 1; end // finish report always @ (posedge clk) if ((cnt[30:2]==(NO-1)) && (cnt[1:0]==2'd3)) begin $write("*-* All Finished *-*\n"); $finish; end // descending range always @ (posedge clk) if (cnt[1:0]==2'd0) begin // initialize to defaults (all bits 1'b0) if (cnt[30:2]==0) struct_dsc <= '0; else if (cnt[30:2]==1) struct_dsc <= '0; else if (cnt[30:2]==2) struct_dsc <= '0; else if (cnt[30:2]==3) struct_dsc <= '0; else if (cnt[30:2]==4) struct_dsc <= '0; else if (cnt[30:2]==5) struct_dsc <= '0; else if (cnt[30:2]==6) struct_dsc <= '0; end else if (cnt[1:0]==2'd1) begin // write data into whole or part of the array using literals if (cnt[30:2]==0) begin end else if (cnt[30:2]==1) struct_dsc <= '{0 ,1 , 2, 3}; else if (cnt[30:2]==2) struct_dsc <= '{e0:1, e1:2, e2:3, e3:4}; else if (cnt[30:2]==3) struct_dsc <= '{e3:6, e2:4, e1:2, e0:0}; // verilator lint_off WIDTH else if (cnt[30:2]==4) struct_dsc <= '{default:13}; else if (cnt[30:2]==5) struct_dsc <= '{e2:8'haa, default:1}; else if (cnt[30:2]==6) struct_dsc <= '{cnt+0 ,cnt+1 , cnt+2, cnt+3}; // verilator lint_on WIDTH end else if (cnt[1:0]==2'd2) begin // chack array agains expected value if (cnt[30:2]==0) begin if (struct_dsc !== 15'b0_00_0000_00000000) begin $display("%b", struct_dsc); $stop(); end end else if (cnt[30:2]==1) begin if (struct_dsc !== 15'b0_01_0010_00000011) begin $display("%b", struct_dsc); $stop(); end end else if (cnt[30:2]==2) begin if (struct_dsc !== 15'b1_10_0011_00000100) begin $display("%b", struct_dsc); $stop(); end end else if (cnt[30:2]==3) begin if (struct_dsc !== 15'b0_10_0100_00000110) begin $display("%b", struct_dsc); $stop(); end end else if (cnt[30:2]==4) begin if (struct_dsc !== 15'b1_01_1101_00001101) begin $display("%b", struct_dsc); $stop(); end end else if (cnt[30:2]==5) begin if (struct_dsc !== 15'b1_01_1010_00000001) begin $display("%b", struct_dsc); $stop(); end end else if (cnt[30:2]==6) begin if (struct_dsc !== 15'b1_10_1011_00011100) begin $display("%b", struct_dsc); $stop(); end end end // ascending range always @ (posedge clk) if (cnt[1:0]==2'd0) begin // initialize to defaults (all bits 1'b0) if (cnt[30:2]==0) struct_asc <= '0; else if (cnt[30:2]==1) struct_asc <= '0; else if (cnt[30:2]==2) struct_asc <= '0; else if (cnt[30:2]==3) struct_asc <= '0; else if (cnt[30:2]==4) struct_asc <= '0; else if (cnt[30:2]==5) struct_asc <= '0; else if (cnt[30:2]==6) struct_asc <= '0; end else if (cnt[1:0]==2'd1) begin // write data into whole or part of the array using literals if (cnt[30:2]==0) begin end else if (cnt[30:2]==1) struct_asc <= '{0 ,1 , 2, 3}; else if (cnt[30:2]==2) struct_asc <= '{e0:1, e1:2, e2:3, e3:4}; else if (cnt[30:2]==3) struct_asc <= '{e3:6, e2:4, e1:2, e0:0}; // verilator lint_off WIDTH else if (cnt[30:2]==4) struct_asc <= '{default:13}; else if (cnt[30:2]==5) struct_asc <= '{e2:8'haa, default:1}; else if (cnt[30:2]==6) struct_asc <= '{cnt+0 ,cnt+1 , cnt+2, cnt+3}; // verilator lint_on WIDTH end else if (cnt[1:0]==2'd2) begin // chack array agains expected value if (cnt[30:2]==0) begin if (struct_asc !== 15'b0_00_0000_00000000) begin $display("%b", struct_asc); $stop(); end end else if (cnt[30:2]==1) begin if (struct_asc !== 15'b0_01_0010_00000011) begin $display("%b", struct_asc); $stop(); end end else if (cnt[30:2]==2) begin if (struct_asc !== 15'b1_10_0011_00000100) begin $display("%b", struct_asc); $stop(); end end else if (cnt[30:2]==3) begin if (struct_asc !== 15'b0_10_0100_00000110) begin $display("%b", struct_asc); $stop(); end end else if (cnt[30:2]==4) begin if (struct_asc !== 15'b1_01_1101_00001101) begin $display("%b", struct_asc); $stop(); end end else if (cnt[30:2]==5) begin if (struct_asc !== 15'b1_01_1010_00000001) begin $display("%b", struct_asc); $stop(); end end else if (cnt[30:2]==6) begin if (struct_asc !== 15'b1_10_1011_00011100) begin $display("%b", struct_asc); $stop(); end end end endmodule verilator-5.042/test_regress/t/t_interface_gen5.v0000644000542200017500000000244015101701376022456 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty. // SPDX-License-Identifier: CC0-1.0 // bug998 interface intf #(parameter PARAM = 0) (); logic val; function integer func (); return 5; endfunction endinterface module t1(intf mod_intf); initial begin $display("%m %d", mod_intf.val); end endmodule module t(); generate begin : TestIf intf #(.PARAM(1)) my_intf (); assign my_intf.val = '0; t1 t (.mod_intf(my_intf)); // initial $display("%0d", my_intf.func()); end endgenerate generate begin intf #(.PARAM(1)) my_intf (); assign my_intf.val = '1; t1 t (.mod_intf(my_intf)); // initial $display("%0d", my_intf.func()); end endgenerate localparam LP = 1; logic val; generate begin if (LP) begin intf #(.PARAM(2)) my_intf (); assign my_intf.val = '1; assign val = my_intf.val; end else begin intf #(.PARAM(3)) my_intf (); assign my_intf.val = '1; assign val = my_intf.val; end end endgenerate initial begin $display("%0d", val); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_disable_task_unsup.v0000644000542200017500000000073415101701376023463 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 int x = 0; task increment_x; x++; #2; x++; endtask module t; initial begin fork increment_x(); #1 disable increment_x; join if (x != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_bind_nfound.py0000755000542200017500000000070615101701376022256 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.042/test_regress/t/t_initarray_nonarray.v0000644000542200017500000000111715101701376023513 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // The code here is used to trigger Verilator internal error // "InitArray on non-array" // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Jie Xu. // SPDX-License-Identifier: CC0-1.0 typedef logic [7:0] mask_t [7:0]; // parameter logic [7:0] IMP_MASK[7:0] = '{8'hE1, 8'h03, 8'h07, 8'h3F, 8'h33, 8'hC3, 8'hC3, 8'h37}; parameter mask_t IMP_MASK = '{8'hE1, 8'h03, 8'h07, 8'h3F, 8'h33, 8'hC3, 8'hC3, 8'h37}; module t; mask_t a; //logic [7:0] a[7:0]; assign a = IMP_MASK; endmodule verilator-5.042/test_regress/t/t_fork_port.py0000755000542200017500000000076315101701376022001 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_inst_recurse_bad.out0000644000542200017500000000067715101701376023467 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_inst_recurse_bad.v:13:8: Unsupported: Recursive multiple modules (module instantiates something leading back to itself): 'looped' : ... note: self-recursion (module instantiating itself directly) is supported. 13 | module looped; | ^~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_altera_lpm_mux.py0000755000542200017500000000111115101701376022771 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) test.compile(verilator_flags2=["--top-module", module]) test.passes() verilator-5.042/test_regress/t/t_enum_x_bad.v0000644000542200017500000000062715101701376021706 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; enum bit [1:0] { BADX = 2'b1x } BAD1; enum logic [3:0] { e0 = 4'b1xx1, e1 } BAD2; initial begin $stop; end endmodule verilator-5.042/test_regress/t/t_case_incrdecr.v0000644000542200017500000000755515101701376022400 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; int cyc = 0; logic [1:0] case_sel; always @ (posedge clk) begin : main cyc <= cyc + 1; case_sel <= 2'($urandom); if (cyc > 100) begin $write("*-* All Finished *-*\n"); $finish(); end end // ------------------------- // Simple case-stmt with ++/-- logic [3:0] count_d; logic [3:0] count_q = '0; logic [3:0] want_count_d; logic [3:0] want_count_q = '0; always_ff @(posedge clk) begin : flops count_q <= count_d; want_count_q <= want_count_d; end always @(posedge clk) begin : simple_check if (cyc > 0) begin if (count_q !== want_count_q) begin $error("%m: Checks cyc=%0d, count_q (%0d) !== want_count_q (%0d)", cyc, count_q, want_count_q); $stop; // don't finish to fail the test. end end end always_comb begin : update_golden_counts want_count_d = want_count_q; if (case_sel == 2'b10) want_count_d++; else if (case_sel == 2'b01) want_count_d--; end // Make sure the ++ and -- operators are handled correctly in case stmts. // Test for https://github.com/verilator/verilator/issues/3346 always_comb begin : update_counts count_d = count_q; case (case_sel) 2'b10: count_d++; 2'b01: count_d--; default : ; endcase // case (case_sel) end // ------------------------- // FSM with ++/-- // A more elaborate case statement, with if-else, for loops, etc // to confirm that ++/-- is handled by V3LinkInc.cpp logic [3:0] state_d, state_q; initial state_q = '0; logic [3:0] state_counter_d, state_counter_q; always_ff @(posedge clk) begin state_q <= state_d; state_counter_q <= state_counter_d; end always_comb begin : update_state state_d = state_q; state_counter_d = state_counter_q; case (state_q) // state 0, no begin/end, goes to state 1 4'd0: state_d = 4'd1; // state 1, clears state_counter_d, goes to state 2 4'd1: begin state_d = 4'd2; state_counter_d = '0; end // state 2, wait until state_counter_d increments to 4. 4'd2: begin state_counter_d++; if (state_counter_q == 4) begin state_d = 4'd3; end end // state 3, decrements state_counter_d from 5 to 0. 4'd3: begin state_counter_d--; if (state_counter_q == 1) begin state_d = 4'd4; end end 4'd4: begin // add 4 with for-loop and ++. for (int unsigned i = 0; i < 4; i++) begin state_counter_d++; end if (state_counter_q == 12) begin state_counter_d = '0; state_d = 4'd5; end end 4'd5: begin // add 8 with a while loop and go to state 6. while (state_counter_d <= 7) begin state_counter_d++; end if (state_counter_d == 8) begin state_d = 4'd15; end end 4'd15 : begin // success, stay here. state_counter_d = 4'd7; // pick and hold some success number. end default: ; endcase // case (state_q) end // block: state always @(posedge clk) begin : simple_state_check //$display("%m: debug, cyc=%0d, state_q=%0d, state_counter_q=%0d", // cyc, state_q, state_counter_q); if (cyc >= 90) begin // the above FSM should finish before 90 cycles. // Make sure we made it to state 4'd15. if (state_q !== 4'd15 || state_counter_q !== 4'd7) begin $error("%m: EOT checks, cyc=%0d, state_q=%0d (want 15), state_counter_q=%0d (want 7)", cyc, state_q, state_counter_q); $stop; // don't finish to fail the test. end end end endmodule : t verilator-5.042/test_regress/t/t_concat_casts.v0000644000542200017500000000157015101701376022247 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package my_pkg; typedef enum logic [1:0] { SIG_0, SIG_1, SIG_2 } sig_t; endpackage : my_pkg module t; import my_pkg::*; typedef logic [7:0] foo_t; typedef logic [31:0] bar_t; bar_t [1:0] the_bars; foo_t [0:0][1:0] the_foos; always_comb begin the_bars = {32'd7, 32'd8}; the_foos[0] = {foo_t'(the_bars[1]), foo_t'(the_bars[0])}; end logic [6:0] data; logic [2:0] opt; assign data = 7'b110_0101; assign opt = {data[5], sig_t'(data[1:0])}; initial begin if (the_foos != 'h0708) $stop(); if (opt != 'b101) $stop(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_fork_repeat_reset.v0000644000542200017500000000270415101701376023306 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; logic clock; initial begin clock = '0; forever begin clock = #5ns ~clock; end end task static has_fork_task(input [31:0] address); @(posedge clock); fork begin repeat($urandom_range(9)) @(posedge clock); end join endtask // Intentionally created a recursive task chain (that should be unreachable anyway): // call_task() // --> (unreachable) --> calls local_sub_task() // --> calls call_task() // --> ... // --> (reachable) --> calls has_fork_task() done. task static call_task(input [31:0] address); if (1) begin // Workaround1: Comment this out to pass the compile. has_fork_task(address); end else begin // Workaround2: Comment this out to pass the compile // Should be unreachable anyway. local_sub_task(.address(address)); end endtask task static local_sub_task(input [31:0] address); logic [63:0] req; logic [39:0] resp; req = '0; call_task(.address(32'h0000_1234)); resp = '0; endtask initial begin : main #100ns; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_class_member_var_virt_bad.v0000644000542200017500000000042615101701376024760 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Foo; virtual int member; endclass module t; endmodule verilator-5.042/test_regress/t/t_enum_huge_methods.py0000755000542200017500000000073415101701376023471 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_virtual_inl.py0000755000542200017500000000131615101701376024337 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_virtual.v" test.golden_filename = "t/t_interface_virtual.out" test.compile( # Avoid inlining so we find bugs in the non-inliner connection code verilator_flags2=["-fno-inline"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_order_dpi_export_3.py0000755000542200017500000000105615101701376023562 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_order_doubleloop.v0000644000542200017500000000522415101701376023142 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; // verilator lint_off LATCH // verilator lint_off UNOPT // verilator lint_off UNOPTFLAT // verilator lint_off MULTIDRIVEN // verilator lint_off BLKANDNBLK reg [31:0] comcnt; reg [31:0] dlycnt; initial dlycnt=0; reg [31:0] lastdlycnt; initial lastdlycnt = 0; reg [31:0] comrun; initial comrun = 0; reg [31:0] comrunm1; reg [31:0] dlyrun; initial dlyrun = 0; reg [31:0] dlyrunm1; always @ (posedge clk) begin $write("[%0t] cyc %d\n", $time,cyc); cyc <= cyc + 1; if (cyc==2) begin // Test # of iters lastdlycnt = 0; comcnt = 0; dlycnt <= 0; end if (cyc==3) begin dlyrun <= 5; dlycnt <= 0; end if (cyc==4) begin comrun = 4; end end always @ (negedge clk) begin if (cyc==5) begin $display("%d %d\n", dlycnt, comcnt); if (dlycnt != 32'd5) $stop; if (comcnt != 32'd19) $stop; $write("*-* All Finished *-*\n"); $finish; end end // This forms a "loop" where we keep going through the always till comrun=0 reg runclk; initial runclk = 1'b0; always @ (/*AS*/comrunm1 or dlycnt) begin if (lastdlycnt != dlycnt) begin comrun = 3; $write ("[%0t] comrun=%0d start\n", $time, comrun); end else if (comrun > 0) begin comrun = comrunm1; if (comrunm1==1) begin runclk = 1; $write ("[%0t] comrun=%0d [trigger clk]\n", $time, comrun); end else $write ("[%0t] comrun=%0d\n", $time, comrun); end lastdlycnt = dlycnt; end always @ (/*AS*/comrun) begin if (comrun!=0) begin comrunm1 = comrun - 32'd1; comcnt = comcnt + 32'd1; $write("[%0t] comcnt=%0d\n", $time,comcnt); end end // This forms a "loop" where we keep going through the always till dlyrun=0 reg runclkrst; always @ (posedge runclk) begin runclkrst <= 1; $write ("[%0t] runclk\n", $time); if (dlyrun > 0) begin dlyrun <= dlyrun - 32'd1; dlycnt <= dlycnt + 32'd1; $write ("[%0t] dlyrun<=%0d\n", $time, dlyrun-32'd1); end end always @* begin if (runclkrst) begin $write ("[%0t] runclk reset\n", $time); runclkrst = 0; runclk = 0; end end endmodule verilator-5.042/test_regress/t/t_opt_merge_cond_bug_3409.py0000755000542200017500000000140115101701376024262 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--stats"]) test.execute() if test.vlt_all: test.file_grep(test.stats, r'Optimizations, MergeCond merges\s+(\d+)', 0) test.file_grep(test.stats, r'Optimizations, MergeCond merged items\s+(\d+)', 0) test.file_grep(test.stats, r'Optimizations, MergeCond longest merge\s+(\d+)', 0) test.passes() verilator-5.042/test_regress/t/t_hierarchy_identifier_bad.v0000644000542200017500000000214415101701376024567 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Iztok Jeras. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; parameter SIZE = 8; integer cnt = 0; logic [SIZE-1:0] vld_for; logic vld_if = 1'b0; logic vld_else = 1'b0; genvar i; // event counter always @ (posedge clk) begin cnt <= cnt + 1; end // finish report always @ (posedge clk) if (cnt==SIZE) begin : if_cnt_finish $write("*-* All Finished *-*\n"); $finish; end : if_cnt_finish_bad generate for (i=0; i0) begin : generate_if_if always @ (posedge clk) vld_if <= 1'b1; end : generate_if_if_bad else begin : generate_if_else always @ (posedge clk) vld_else <= 1'b1; end : generate_if_else_bad endgenerate endmodule : t_bad verilator-5.042/test_regress/t/t_alias_ports_unsup.v0000644000542200017500000000117015101701376023351 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ // Inputs clk ); input clk; wire [31:0] a, b; integer cyc = 0; assign a = cyc; sub s ( .a(a), .b(b) ); always @(posedge clk) begin cyc <= cyc + 1; if (a != cyc) $stop; if (b != cyc) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module sub ( inout wire [31:0] a, inout wire [31:0] b ); alias a = b; endmodule verilator-5.042/test_regress/t/t_class_local_nested_bad.out0000644000542200017500000000107115101701376024570 0ustar mahmoudyfreeshell%Error-ENCAPSULATED: t/t_class_local_nested_bad.v:14:22: 'name' is hidden as 'local' within this context (IEEE 1800-2023 8.18) : ... note: In instance 't' 14 | name = Node::name; | ^~~~ t/t_class_local_nested_bad.v:14:22: ... Location of definition 9 | static local string name; | ^~~~ ... For error description see https://verilator.org/warn/ENCAPSULATED?v=latest %Error: Exiting due to verilator-5.042/test_regress/t/t_assoc_wildcard_method.py0000755000542200017500000000073415101701376024313 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_tri_compass_bad.v0000644000542200017500000000063415101701376022734 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Outputs o, // Inputs i ); input i; output o; sub sub(i, o); endmodule module sub(input i, output o); assign o = (i===1'bz) ? 1'b0 : i; endmodule verilator-5.042/test_regress/t/t_dfg_true_cycle_bad.out0000644000542200017500000000143015101701376023724 0ustar mahmoudyfreeshell%Warning-UNOPTFLAT: t/t_dfg_true_cycle_bad.v:10:23: Signal unoptimizable: Circular combinational logic: 't.o' 10 | output wire [9:0] o | ^ ... For warning description see https://verilator.org/warn/UNOPTFLAT?v=latest ... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message. t/t_dfg_true_cycle_bad.v:10:23: Example path: t.o t/t_dfg_true_cycle_bad.v:10:23: Example path: ASSIGNW t/t_dfg_true_cycle_bad.v:10:23: Example path: o t/t_dfg_true_cycle_bad.v:10:23: Example path: ASSIGNW t/t_dfg_true_cycle_bad.v:10:23: Example path: t.o %Error: Exiting due to verilator-5.042/test_regress/t/t_class_virtual_pure_bad.out0000644000542200017500000000050015101701376024651 0ustar mahmoudyfreeshell%Error: t/t_class_virtual_pure_bad.v:8:22: Illegal to have 'pure virtual' in non-virtual class (IEEE 1800-2023 8.21) 8 | pure virtual task pure_task; | ^~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_forceable_var.vlt0000644000542200017500000000041015101701376022725 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 `verilator_config forceable -module "*" -var "var_*" verilator-5.042/test_regress/t/t_randomize_prepost_alone.v0000644000542200017500000000105515101701376024523 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package uvm_pkg; class uvm_sequence_item; endclass endpackage package tb_cpu_pkg; import uvm_pkg::*; class tb_cpu_seq_item extends uvm_sequence_item; function void pre_randomize(); super.pre_randomize(); endfunction function void post_randomize(); super.post_randomize(); endfunction endclass endpackage verilator-5.042/test_regress/t/t_interface_generic_modport_task_bad.py0000755000542200017500000000102515101701376027014 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=['--timing'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_urandom.v0000644000542200017500000000454315101701376021253 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Methods defined by IEEE: // function int unsigned $urandom [ (int seed ) ] ; // function int unsigned $urandom_range( int unsigned maxval, // int unsigned minval = 0 ); module t; `ifndef VERILATOR `define PROC `endif `ifdef PROC process p; `endif int unsigned v1; int unsigned v2; int unsigned v3; string s; initial begin `ifdef PROC if (p != null) $stop; p = process::self(); `endif v1 = $urandom; v2 = $urandom; v3 = $urandom(); if (v1 == v2 && v1 == v3) $stop; // Possible, but 2^-64 // Range v2 = $urandom_range(v1, v1); if (v1 != v2) $stop; v2 = $urandom_range(0, 32'hffffffff); if (v2 == v1) $stop; for (int test = 0; test < 20; ++test) begin v1 = 2; v1 = $urandom_range(0, v1); if (v1 != 0 && v1 != 1 && v1 != 2) $stop; v1 = $urandom_range(2, 0); if (v1 != 0 && v1 != 1 && v1 !=2) $stop; v1 = $urandom_range(3); if (v1 != 0 && v1 != 1 && v1 != 2 && v1 != 3) $stop; end // Seed stability // Note UVM doesn't use $urandom seeding v1 = $urandom(1); v2 = $urandom(1); if (v1 != v2) $stop; v2 = $urandom(1); if (v1 != v2) $stop; `ifdef PROC // Seed stability via process.srandom p.srandom(1); v1 = $urandom(); p.srandom(1); v2 = $urandom(); if (v1 != v2) $stop; p.srandom(1); v2 = $urandom(); if (v1 != v2) $stop; // Seed stability via process.srandom p.srandom(32'h88888888); // "Large" seed to check a VlRNG::srandom edge case v1 = $urandom(); p.srandom(32'h88888888); v2 = $urandom(); if (v1 != v2) $stop; p.srandom(32'h88888888); v2 = $urandom(); if (v1 != v2) $stop; // Seed stability via process.get_randstate s = p.get_randstate(); v1 = $urandom(); p.set_randstate(s); v2 = $urandom(); if (v1 != v2) $stop; p.set_randstate(s); v2 = $urandom(); if (v1 != v2) $stop; `endif $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_inst_array_bad.out0000644000542200017500000000075015101701376023125 0ustar mahmoudyfreeshell%Error: t/t_inst_array_bad.v:14:28: Input port connection 'onebit' as part of a module instance array requires 1 or 8 bits, but connection's VARREF 'onebitbad' generates 9 bits. (IEEE 1800-2023 23.3.3) : ... note: In instance 't' 14 | sub sub [7:0] (allbits, onebitbad, bitout); | ^~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_clocking_unsup2.py0000755000542200017500000000102515101701376023071 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["--timing"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_unpacked_array_p_fmt.out0000644000542200017500000000031315101701376024314 0ustar mahmoudyfreeshell%p='{'h0, 'h1, 'h1, 'h0, 'h1, 'h0, 'h0, 'h1, 'h1, 'h0, 'h0, 'h1, 'h0, 'h1, 'h1, 'h0} %p='{'{'h0, 'h1, 'h1, 'h0}, '{'h1, 'h0, 'h0, 'h1}, '{'h1, 'h0, 'h0, 'h1}, '{'h0, 'h1, 'h1, 'h0}} *-* All Finished *-* verilator-5.042/test_regress/t/t_inst_ccall.py0000755000542200017500000000073415101701376022105 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_expr_incr_unsup.py0000755000542200017500000000076615101701376023222 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_randomize_rand_mode_bad.out0000644000542200017500000000360415101701376024753 0ustar mahmoudyfreeshell%Error: t/t_randomize_rand_mode_bad.v:22:15: Cannot call 'rand_mode()' on non-random, non-class variable : ... note: In instance 't' 22 | p.m_val.rand_mode(0); | ^~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_randomize_rand_mode_bad.v:23:19: Cannot call 'rand_mode()' on packed array element : ... note: In instance 't' 23 | p.m_pack[0].rand_mode(0); | ^~~~~~~~~ %Error: t/t_randomize_rand_mode_bad.v:24:39: Cannot call 'rand_mode()' as a function on non-random variable : ... note: In instance 't' 24 | $display("p.rand_mode()=%0d", p.rand_mode()); | ^~~~~~~~~ %Error: t/t_randomize_rand_mode_bad.v:25:18: 'rand_mode()' with arguments cannot be called as a function : ... note: In instance 't' 25 | $display(p.rand_mode(0)); | ^~~~~~~~~ %Warning-IGNOREDRETURN: t/t_randomize_rand_mode_bad.v:26:21: Ignoring return value of non-void function (IEEE 1800-2023 13.4.1) : ... note: In instance 't' 26 | p.m_other_val.rand_mode(); | ^~~~~~~~~ ... For warning description see https://verilator.org/warn/IGNOREDRETURN?v=latest ... Use "/* verilator lint_off IGNOREDRETURN */" and lint_on around source to disable this message. %Error: t/t_randomize_rand_mode_bad.v:13:14: Cannot call 'rand_mode()' as a function on non-random variable : ... note: In instance 't' 13 | return rand_mode(); | ^~~~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_class_extends_this_protect_ids.py0000755000542200017500000000152615101701376026257 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_class_extends_this.v" # This test makes randomly named .cpp/.h files, which tend to collect, so remove them first for filename in (glob.glob(test.obj_dir + "/*_PS*.cpp") + glob.glob(test.obj_dir + "/*_PS*.h") + glob.glob(test.obj_dir + "/*.d")): test.unlink_ok(filename) test.compile(verilator_flags2=["--protect-ids", "--protect-key SECRET_KEY"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_bench_mux4k_onecpu.py0000755000542200017500000000174415101701376023554 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_bench_mux4k.v" test.compile(v_flags2=["--stats", test.wno_unopthreads_for_few_cores]) # WSL2 gives a warning and we must skip the test: # "physcpubind: 0 1 2 3 ...\n No NUMA support available on this system." nout = test.run_capture("numactl --show", check=False) if not nout or not re.search(r'cpu', nout) or re.search(r'No NUMA support available', nout, re.IGNORECASE): test.skip("No numactl available") test.execute(run_env='numactl -m 0 -C 0,0,0,0,0,0,0,0') test.passes() verilator-5.042/test_regress/t/t_display_signed_noopt.py0000755000542200017500000000116315101701376024204 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_display_signed.v" test.golden_filename = "t/t_display_signed.out" test.compile(verilator_flags2=["-O0"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_flag_threads_bad2.out0000644000542200017500000000022215101701376023451 0ustar mahmoudyfreeshell%Error: --threads-max-mtasks must be >= 1: 0 ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. verilator-5.042/test_regress/t/t_langext_1d.py0000755000542200017500000000106015101701376022011 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_langext_1.v" # This is a compile only test. test.compile(v_flags2=["+verilog2001ext+.v"]) test.passes() verilator-5.042/test_regress/t/t_const_number_v_bad.out0000644000542200017500000000244115101701376023774 0ustar mahmoudyfreeshell%Warning-NEWERSTD: t/t_const_number_v_bad.v:11:25: Unbased unsized literals require IEEE 1800-2005 or later. 11 | wire [127:0] FOO1 = '0; | ^~ ... For warning description see https://verilator.org/warn/NEWERSTD?v=latest ... Use "/* verilator lint_off NEWERSTD */" and lint_on around source to disable this message. %Warning-NEWERSTD: t/t_const_number_v_bad.v:12:25: Unbased unsized literals require IEEE 1800-2005 or later. 12 | wire [127:0] FOO2 = '1; | ^~ %Warning-NEWERSTD: t/t_const_number_v_bad.v:13:25: Unbased unsized literals require IEEE 1800-2005 or later. 13 | wire [127:0] FOO3 = 'x; | ^~ %Warning-NEWERSTD: t/t_const_number_v_bad.v:14:25: Unbased unsized literals require IEEE 1800-2005 or later. 14 | wire [127:0] FOO4 = 'X; | ^~ %Warning-NEWERSTD: t/t_const_number_v_bad.v:15:25: Unbased unsized literals require IEEE 1800-2005 or later. 15 | wire [127:0] FOO5 = 'z; | ^~ %Warning-NEWERSTD: t/t_const_number_v_bad.v:16:25: Unbased unsized literals require IEEE 1800-2005 or later. 16 | wire [127:0] FOO6 = 'Z; | ^~ %Error: Exiting due to verilator-5.042/test_regress/t/t_flag_build_bad_cmake.out0000644000542200017500000000076215101701376024205 0ustar mahmoudyfreeshell%Warning-DEPRECATED: Option '--make cmake' is deprecated, use '--make json' instead ... For warning description see https://verilator.org/warn/DEPRECATED?v=latest ... Use "/* verilator lint_off DEPRECATED */" and lint_on around source to disable this message. %Error: --make cannot be used together with --build. Suggest see manual ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_enum_overlap_bad.py0000755000542200017500000000076615101701376023301 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_struct_pat.py0000755000542200017500000000073415101701376022162 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_timing_wait_long.out0000644000542200017500000000076615101701376023505 0ustar mahmoudyfreeshellCurrent realtime: 5000000 == 5000000000 Current realtime: 10000001 == 10000001 Current realtime: 15000000 == 15000000 FULL_TIME: 5000000.000000 Current realtime: 20000000 == 20000000 FIT_TIME: 5000000 -- 5000000.000000 Current realtime: 25000000 == 25000000 TRUNCATED_TIME: 805696 -- 805696.000000 Current realtime: 25805696 == 25805696 *-* All Finished *-* verilator-5.042/test_regress/t/t_gen_for_interface.py0000755000542200017500000000073415101701376023431 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_forceable_public_flat.v0000644000542200017500000000111415101701376024063 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( input x, input y, output z ); logic t2 /* verilator public */; logic t3; sub u_sub ( x, y, t3 ); assign t2 = t3 | x; assign z = t2; endmodule module sub ( input a /* verilator forceable */ /* verilator public_flat */, input b, output c ); logic t1; assign t1 = a & b; assign c = t1; endmodule verilator-5.042/test_regress/t/t_force_readwrite.py0000755000542200017500000000076315101701376023140 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_gen_inc.py0000755000542200017500000000073415101701376021374 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_func_task_bad.py0000755000542200017500000000076615101701376022562 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_constraint_xml.v0000644000542200017500000000273715101701376022655 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Packet; rand int header; // 0..7 rand int length; // 0..15 rand int sublength; // 0..15 rand bit if_4; rand bit iff_5_6; rand bit if_state_ok; rand int array[2]; // 2,4,6 string state; constraint empty {} constraint size { header > 0 && header <= 7; length <= 15; length >= header; length dist { [0:1], [2:5] :/ 2, 6 := 6, 7 := 10, 1}; } constraint ifs { if (header > 4) { if_4 == '1; } if (header == 5 || header == 6) { iff_5_6 == '1; iff_5_6 == '1; iff_5_6 == '1; } else { iff_5_6 == '0; } } constraint arr_uniq { foreach (array[i]) { array[i] inside {2, 4, 6}; } unique { array[0], array[1] }; } constraint order { solve length before header; } constraint dis { soft sublength; disable soft sublength; sublength <= length; } constraint meth { if (strings_equal(state, "ok")) if_state_ok == '1; } function bit strings_equal(string a, string b); return a == b; endfunction endclass module t; Packet p; initial begin // Not testing use of constraints $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_dpi_open.v0000644000542200017500000001462715101701376021407 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2017 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module t; // verilator lint_off UNUSED reg i_rl_p0_u1 [-2:2]; reg o_rl_p0_u1 [-2:2]; reg [1:-1] i_rl_p1_u1 [-2:2]; reg [1:-1] o_rl_p1_u1 [-2:2]; reg [1:-1] i_rl_p1_u2 [-2:2] [-3:3]; reg [1:-1] o_rl_p1_u2 [-2:2] [-3:3]; reg [1:-1] i_rl_p1_u3 [-2:2] [-3:3] [-4:4]; reg [1:-1] o_rl_p1_u3 [-2:2] [-3:3] [-4:4]; reg i_rb_p0_u1 [2:-2]; reg o_rb_p0_u1 [2:-2]; reg [1:-1] i_rb_p1_u1 [2:-2]; reg [1:-1] o_rb_p1_u1 [2:-2]; reg [1:-1] i_rb_p1_u2 [2:-2] [3:-3]; reg [1:-1] o_rb_p1_u2 [2:-2] [3:-3]; reg [1:-1] i_rb_p1_u3 [2:-2] [3:-3] [4:-4]; reg [1:-1] o_rb_p1_u3 [2:-2] [3:-3] [4:-4]; reg i_rw_p0_u1 [2:-2]; reg o_rw_p0_u1 [2:-2]; reg [95:1] i_rw_p1_u1 [2:-2]; reg [95:1] o_rw_p1_u1 [2:-2]; reg [95:1] i_rw_p1_u2 [2:-2] [3:-3]; reg [95:1] o_rw_p1_u2 [2:-2] [3:-3]; reg [95:1] i_rw_p1_u3 [2:-2] [3:-3] [4:-4]; reg [95:1] o_rw_p1_u3 [2:-2] [3:-3] [4:-4]; bit i_bit [1:0]; bit o_bit [1:0]; logic i_logic [1:0]; logic o_logic [1:0]; byte i_byte [1:0]; byte o_byte [1:0]; integer i_integer [1:0]; integer o_integer [1:0]; import "DPI-C" function int dpii_failure(); import "DPI-C" function void dpii_unused(input reg u []); // [] on packed arrays is unsupported in VCS & NC, so not supporting this // p is number of packed dimensions, u is number of unpacked dimensions import "DPI-C" function void dpii_open_p0_u1(input int c,p,u, input reg i [], output reg o []); import "DPI-C" function void dpii_open_p1_u1(input int c,p,u, input reg [1:-1] i [], output reg [1:-1] o []); import "DPI-C" function void dpii_open_p1_u2(input int c,p,u, input reg [1:-1] i [] [], output reg [1:-1] o [] []); import "DPI-C" function void dpii_open_p1_u3(input int c,p,u, input reg [1:-1] i [] [] [], output reg [1:-1] o [] [] []); import "DPI-C" function void dpii_open_pw_u1(input int c,p,u, input reg [95:1] i [], output reg [95:1] o []); import "DPI-C" function void dpii_open_pw_u2(input int c,p,u, input reg [95:1] i [] [], output reg [95:1] o [] []); import "DPI-C" function void dpii_open_pw_u3(input int c,p,u, input reg [95:1] i [] [] [], output reg [95:1] o [] [] []); import "DPI-C" function void dpii_open_bit(input bit i [], output bit o []); import "DPI-C" function void dpii_open_logic(input logic i [], output logic o []); import "DPI-C" function void dpii_open_byte(input byte i [], output byte o []); import "DPI-C" function void dpii_open_integer(input integer i [], output integer o []); int i_int_u1 [2:-2]; int o_int_u1 [2:-2]; int i_int_u2 [2:-2] [-3:3]; int o_int_u2 [2:-2] [-3:3]; int i_int_u3 [2:-2] [-3:3] [4:-4]; int o_int_u3 [2:-2] [-3:3] [4:-4]; import "DPI-C" function void dpii_open_int_u1(int u, input int i [], output int o []); import "DPI-C" function void dpii_open_int_u2(int u, input int i [] [], output int o [] []); import "DPI-C" function void dpii_open_int_u3(int u, input int i [] [] [], output int o [] [] []); // verilator lint_on UNUSED reg [95:0] crc; initial begin crc = 96'h8a10a572_5aef0c8d_d70a4497; for (int a=0; a<2; a=a+1) begin i_bit[a] = crc[0]; i_logic[a] = crc[0]; i_byte[a] = crc[7:0]; i_integer[a] = crc[31:0]; crc = {crc[94:0], crc[95]^crc[2]^crc[0]}; end dpii_open_bit(i_bit, o_bit); dpii_open_logic(i_logic, o_logic); dpii_open_byte(i_byte, o_byte); dpii_open_integer(i_integer, o_integer); for (int a=-2; a<=2; a=a+1) begin i_rl_p0_u1[a] = crc[0]; i_rb_p0_u1[a] = crc[0]; i_rw_p0_u1[a] = crc[0]; i_rl_p1_u1[a] = crc[2:0]; i_rb_p1_u1[a] = crc[2:0]; i_rw_p1_u1[a] = crc[94:0]; i_int_u1[a] = crc[31:0]; for (int b=-3; b<=3; b=b+1) begin i_rl_p1_u2[a][b] = crc[2:0]; i_rb_p1_u2[a][b] = crc[2:0]; i_rw_p1_u2[a][b] = crc[94:0]; i_int_u2[a][b] = crc[31:0]; for (int c=-4; c<=4; c=c+1) begin i_rl_p1_u3[a][b][c] = crc[2:0]; i_rb_p1_u3[a][b][c] = crc[2:0]; i_rw_p1_u3[a][b][c] = crc[94:0]; i_int_u3[a][b][c] = crc[31:0]; crc = {crc[94:0], crc[95]^crc[2]^crc[0]}; end end end dpii_open_p0_u1(0,0,1, i_rl_p0_u1, o_rl_p0_u1); dpii_open_p0_u1(1,0,1, i_rb_p0_u1, o_rb_p0_u1); dpii_open_p0_u1(2,0,1, i_rw_p0_u1, o_rw_p0_u1); dpii_open_p1_u1(0,1,1, i_rl_p1_u1, o_rl_p1_u1); dpii_open_p1_u2(0,1,2, i_rl_p1_u2, o_rl_p1_u2); dpii_open_p1_u3(0,1,3, i_rl_p1_u3, o_rl_p1_u3); dpii_open_p1_u1(1,1,1, i_rb_p1_u1, o_rb_p1_u1); dpii_open_p1_u2(1,1,2, i_rb_p1_u2, o_rb_p1_u2); dpii_open_p1_u3(1,1,3, i_rb_p1_u3, o_rb_p1_u3); dpii_open_pw_u1(2,1,1, i_rw_p1_u1, o_rw_p1_u1); dpii_open_pw_u2(2,1,2, i_rw_p1_u2, o_rw_p1_u2); dpii_open_pw_u3(2,1,3, i_rw_p1_u3, o_rw_p1_u3); for (int a=-2; a<=2; a=a+1) begin for (int b=-3; b<=3; b=b+1) begin for (int c=-4; c<=4; c=c+1) begin `checkh(o_rw_p1_u3[a][b][c], ~i_rw_p1_u3[a][b][c]); end end end dpii_open_int_u1(1, i_int_u1, o_int_u1); dpii_open_int_u2(2, i_int_u2, o_int_u2); dpii_open_int_u3(3, i_int_u3, o_int_u3); for (int a=-2; a<=2; a=a+1) begin `checkh(o_int_u1[a], ~i_int_u1[a]); for (int b=-3; b<=3; b=b+1) begin `checkh(o_int_u2[a][b], ~i_int_u2[a][b]); for (int c=-4; c<=4; c=c+1) begin `checkh(o_int_u3[a][b][c], ~i_int_u3[a][b][c]); end end end if (dpii_failure()!=0) begin $write("%%Error: Failure in DPI tests\n"); $stop; end else begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_sys_writemem_b.gold7.mem0000644000542200017500000000030015101701376024145 0ustar mahmoudyfreeshell00000000000 00000000000 00000000000 00000000000 11001010100 00000000000 00000000000 00000000000 00000000000 00000000000 11001011010 11001011011 11001011100 00000000000 00000000000 00000000000 verilator-5.042/test_regress/t/t_force.py0000755000542200017500000000073415101701376021070 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_mod_dup_bad_lib.out0000644000542200017500000000207715101701376023233 0ustar mahmoudyfreeshell%Warning-MODDUP: t/t_mod_dup_bad_lib.v:14:8: Duplicate declaration of module: 'a' 14 | module a(); | ^ t/t_mod_dup_bad_lib.v:7:8: ... Location of original declaration 7 | module a(); | ^ ... For warning description see https://verilator.org/warn/MODDUP?v=latest ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message. %Warning-MULTITOP: t/t_mod_dup_bad_lib.v:17:8: Multiple top level modules : ... Suggest see manual; fix the duplicates, or use --top-module to select top. ... For warning description see https://verilator.org/warn/MULTITOP?v=latest ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message. : ... Top module 'test' 10 | module test(); | ^~~~ : ... Top module 'b' 17 | module b(); | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_flag_main.v0000644000542200017500000000056315101701376021521 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by engr248. // SPDX-License-Identifier: CC0-1.0 module t; initial begin $write("[%0t] Hello\n", $time); // Check timestamp works $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_trace_primitive_saif.py0000755000542200017500000000114115101701376024153 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_primitive.v" test.compile(v_flags2=["--trace-saif"]) test.execute() test.saif_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface_gen11_noinl.py0000755000542200017500000000104015101701376024113 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface_gen11.v" test.compile(v_flags2=["-fno-inline"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_property_untyped_unsup.v0000644000542200017500000000135715101701376024474 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ clk ); input clk; int cyc = 0; logic [4:0] val = 0; always @(posedge clk) begin cyc <= cyc + 1; val = ~val; end property check(cyc_mod_2, logic [4:0] expected, arg3, untyped arg4, arg5); @(posedge clk) cyc % 2 == cyc_mod_2 |=> val == expected; endproperty assert property(check(0, 5'b11111, 100, 25, 17)); always @(posedge clk) begin if (cyc == 10) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_interface_ar2b.v0000644000542200017500000000104715101701376022450 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: SystemVerilog interface test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by Thierry Tambe. // SPDX-License-Identifier: CC0-1.0 module t (); sub sub [1] (); ahb_slave_intf AHB_S[1](); AHB_MEM uMEM(.S(AHB_S[0])); // AHB_MEM uMEM(.S(AHB_S[0].source)); endmodule module sub; endmodule module AHB_MEM ( ahb_slave_intf.source S ); endmodule interface ahb_slave_intf (); logic [31:0] HADDR; modport source (input HADDR); endinterface verilator-5.042/test_regress/t/t_program_extern.v0000644000542200017500000000071515101701376022637 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 extern program ex_pgm; extern interface ex_ifc; extern module ex_mod; module t; ex_pgm u_pgm(); ex_ifc u_ifc(); ex_mod u_mod(); initial begin ex_task(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_process_redecl.py0000755000542200017500000000070615101701376022765 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.042/test_regress/t/t_stream_bad.py0000755000542200017500000000076615101701376022100 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_func_tie_bad.py0000755000542200017500000000076615101701376022401 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_block_redecl_bad.out0000644000542200017500000000071415101701376024410 0ustar mahmoudyfreeshell%Error: t/t_lint_block_redecl_bad.v:17:27: Duplicate declaration of block: 'COMB' 17 | for(i=0; i<9; i++ ) begin: COMB | ^~~~~ t/t_lint_block_redecl_bad.v:14:28: ... Location of original declaration 14 | for(i=0; i<10; i++ ) begin: COMB | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_dpi_arg_inout_unpack.py0000755000542200017500000000237515101701376024161 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if test.nc: # For NC, compile twice, first just to generate DPI headers test.compile(nc_flags2=[ "+ncdpiheader+" + test.obj_dir + "/dpi-exp.h", "+ncdpiimpheader+" + test.obj_dir + "/dpi-imp.h" ]) test.compile( v_flags2=["t/" + test.name + ".cpp"], # --no-decoration so .out file doesn't comment on source lines verilator_flags2=["-Wall -Wno-DECLFILENAME --no-decoration"], # NC: Gdd the obj_dir to the C include path nc_flags2=["+ncscargs+-I" + test.obj_dir], # ModelSim: Generate DPI header, add obj_dir to the C include path ms_flags2=["-dpiheader " + test.obj_dir + "/dpi.h", "-ccflags -I" + test.obj_dir]) if test.vlt_all: test.files_identical(test.obj_dir + "/" + test.vm_prefix + "__Dpi.h", "t/" + test.name + "__Dpi.out") test.execute() test.passes() verilator-5.042/test_regress/t/t_generate_fatal_bad.v0000644000542200017500000000220715101701376023350 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 function integer get_baz(input integer bar); get_baz = bar; $fatal(2, "boom"); endfunction module foo #(parameter BAR = 0); localparam integer BAZ = get_baz(BAR); endmodule module foo2 #(parameter QUX = 0); genvar x; generate for (x = 0; x < 2; x++) begin: foo2_loop foo #(.BAR (QUX + x)) foo_in_foo2_inst(); end endgenerate endmodule module t; genvar i, j; generate for (i = 0; i < 2; i++) begin: genloop foo #(.BAR (i)) foo_inst(); end for (i = 2; i < 4; i++) begin: gen_l1 for (j = 0; j < 2; j++) begin: gen_l2 foo #(.BAR (i + j*2)) foo_inst2(); end end if (1 == 1) begin: cond_true foo #(.BAR (6)) foo_inst3(); end if (1 == 1) begin // unnamed foo #(.BAR (7)) foo_inst4(); end for (i = 8; i < 12; i = i + 2) begin: nested_loop foo2 #(.QUX (i)) foo2_inst(); end endgenerate endmodule verilator-5.042/test_regress/t/t_uniqueif_fail1.out0000644000542200017500000000025115101701376023041 0ustar mahmoudyfreeshelltesting fail 1: 1 [10] %Error: t_uniqueif.v:74: Assertion failed in top.t: 'unique if' statement violated %Error: t/t_uniqueif.v:74: Verilog $stop Aborting... verilator-5.042/test_regress/t/t_select_bad_range4.v0000644000542200017500000000117115101701376023125 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk, unk, nonconst, mi ); input clk; input unk; input nonconst; input [45:40] mi; reg [3:0] sel2; reg [1<<29 : 0] hugerange; always @ (posedge clk) begin sel2 = mi[44 +: -1]; sel2 = mi[44 +: 1<<29]; sel2 = mi[44 +: nonconst]; sel2 = mi[nonconst]; sel2 = mi[nonconst : nonconst]; sel2 = mi[1<<29 : 0]; end endmodule verilator-5.042/test_regress/t/t_lint_implicit_def_bad.out0000644000542200017500000000127215101701376024430 0ustar mahmoudyfreeshell%Warning-IMPLICIT: t/t_lint_implicit_def_bad.v:13:11: Signal definition not found, creating implicitly: 'imp_warn' 13 | assign imp_warn = 1'b1; | ^~~~~~~~ ... For warning description see https://verilator.org/warn/IMPLICIT?v=latest ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message. %Error: t/t_lint_implicit_def_bad.v:18:11: Signal definition not found, and implicit disabled with `default_nettype: 'imp_err' 18 | assign imp_err = 1'b1; | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_var_set_link.py0000755000542200017500000000073415101701376022452 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_dpi_arg_input_type__Dpi.out0000644000542200017500000001542315101701376024767 0ustar mahmoudyfreeshell// Verilated -*- C++ -*- // DESCRIPTION: Verilator output: Prototypes for DPI import and export functions. // // Verilator includes this file in all generated .cpp files that use DPI functions. // Manually include this file where DPI .c import functions are declared to ensure // the C functions match the expectations of the DPI imports. #ifndef VERILATED_VT_DPI_ARG_INPUT_TYPE__DPI_H_ #define VERILATED_VT_DPI_ARG_INPUT_TYPE__DPI_H_ // guard #include "svdpi.h" #ifdef __cplusplus extern "C" { #endif // DPI EXPORTS extern void e_array_2_state_1(const svBitVecVal* i); extern void e_array_2_state_128(const svBitVecVal* i); extern void e_array_2_state_32(const svBitVecVal* i); extern void e_array_2_state_33(const svBitVecVal* i); extern void e_array_2_state_64(const svBitVecVal* i); extern void e_array_2_state_65(const svBitVecVal* i); extern void e_array_4_state_1(const svLogicVecVal* i); extern void e_array_4_state_128(const svLogicVecVal* i); extern void e_array_4_state_32(const svLogicVecVal* i); extern void e_array_4_state_33(const svLogicVecVal* i); extern void e_array_4_state_64(const svLogicVecVal* i); extern void e_array_4_state_65(const svLogicVecVal* i); extern void e_bit(svBit i); extern void e_bit_t(svBit i); extern void e_byte(char i); extern void e_byte_t(char i); extern void e_byte_unsigned(unsigned char i); extern void e_byte_unsigned_t(unsigned char i); extern void e_chandle(void* i); extern void e_chandle_t(void* i); extern void e_int(int i); extern void e_int_t(int i); extern void e_int_unsigned(unsigned int i); extern void e_int_unsigned_t(unsigned int i); extern void e_integer(const svLogicVecVal* i); extern void e_integer_t(const svLogicVecVal* i); extern void e_logic(svLogic i); extern void e_logic_t(svLogic i); extern void e_longint(long long i); extern void e_longint_t(long long i); extern void e_longint_unsigned(unsigned long long i); extern void e_longint_unsigned_t(unsigned long long i); extern void e_real(double i); extern void e_real_t(double i); extern void e_shortint(short i); extern void e_shortint_t(short i); extern void e_shortint_unsigned(unsigned short i); extern void e_shortint_unsigned_t(unsigned short i); extern void e_string(const char* i); extern void e_string_t(const char* i); extern void e_struct_2_state_1(const svBitVecVal* i); extern void e_struct_2_state_128(const svBitVecVal* i); extern void e_struct_2_state_32(const svBitVecVal* i); extern void e_struct_2_state_33(const svBitVecVal* i); extern void e_struct_2_state_64(const svBitVecVal* i); extern void e_struct_2_state_65(const svBitVecVal* i); extern void e_struct_4_state_1(const svLogicVecVal* i); extern void e_struct_4_state_128(const svLogicVecVal* i); extern void e_struct_4_state_32(const svLogicVecVal* i); extern void e_struct_4_state_33(const svLogicVecVal* i); extern void e_struct_4_state_64(const svLogicVecVal* i); extern void e_struct_4_state_65(const svLogicVecVal* i); extern void e_time(const svLogicVecVal* i); extern void e_time_t(const svLogicVecVal* i); extern void e_union_2_state_1(const svBitVecVal* i); extern void e_union_2_state_128(const svBitVecVal* i); extern void e_union_2_state_32(const svBitVecVal* i); extern void e_union_2_state_33(const svBitVecVal* i); extern void e_union_2_state_64(const svBitVecVal* i); extern void e_union_2_state_65(const svBitVecVal* i); extern void e_union_4_state_1(const svLogicVecVal* i); extern void e_union_4_state_128(const svLogicVecVal* i); extern void e_union_4_state_32(const svLogicVecVal* i); extern void e_union_4_state_33(const svLogicVecVal* i); extern void e_union_4_state_64(const svLogicVecVal* i); extern void e_union_4_state_65(const svLogicVecVal* i); // DPI IMPORTS extern void check_exports(); extern void i_array_2_state_1(const svBitVecVal* i); extern void i_array_2_state_128(const svBitVecVal* i); extern void i_array_2_state_32(const svBitVecVal* i); extern void i_array_2_state_33(const svBitVecVal* i); extern void i_array_2_state_64(const svBitVecVal* i); extern void i_array_2_state_65(const svBitVecVal* i); extern void i_array_4_state_1(const svLogicVecVal* i); extern void i_array_4_state_128(const svLogicVecVal* i); extern void i_array_4_state_32(const svLogicVecVal* i); extern void i_array_4_state_33(const svLogicVecVal* i); extern void i_array_4_state_64(const svLogicVecVal* i); extern void i_array_4_state_65(const svLogicVecVal* i); extern void i_bit(svBit i); extern void i_bit_t(svBit i); extern void i_byte(char i); extern void i_byte_t(char i); extern void i_byte_unsigned(unsigned char i); extern void i_byte_unsigned_t(unsigned char i); extern void i_chandle(void* i); extern void i_chandle_t(void* i); extern void i_int(int i); extern void i_int_t(int i); extern void i_int_unsigned(unsigned int i); extern void i_int_unsigned_t(unsigned int i); extern void i_integer(const svLogicVecVal* i); extern void i_integer_t(const svLogicVecVal* i); extern void i_logic(svLogic i); extern void i_logic_t(svLogic i); extern void i_longint(long long i); extern void i_longint_t(long long i); extern void i_longint_unsigned(unsigned long long i); extern void i_longint_unsigned_t(unsigned long long i); extern void i_real(double i); extern void i_real_t(double i); extern void i_shortint(short i); extern void i_shortint_t(short i); extern void i_shortint_unsigned(unsigned short i); extern void i_shortint_unsigned_t(unsigned short i); extern void i_string(const char* i); extern void i_string_t(const char* i); extern void i_struct_2_state_1(const svBitVecVal* i); extern void i_struct_2_state_128(const svBitVecVal* i); extern void i_struct_2_state_32(const svBitVecVal* i); extern void i_struct_2_state_33(const svBitVecVal* i); extern void i_struct_2_state_64(const svBitVecVal* i); extern void i_struct_2_state_65(const svBitVecVal* i); extern void i_struct_4_state_1(const svLogicVecVal* i); extern void i_struct_4_state_128(const svLogicVecVal* i); extern void i_struct_4_state_32(const svLogicVecVal* i); extern void i_struct_4_state_33(const svLogicVecVal* i); extern void i_struct_4_state_64(const svLogicVecVal* i); extern void i_struct_4_state_65(const svLogicVecVal* i); extern void i_time(const svLogicVecVal* i); extern void i_time_t(const svLogicVecVal* i); extern void i_union_2_state_1(const svBitVecVal* i); extern void i_union_2_state_128(const svBitVecVal* i); extern void i_union_2_state_32(const svBitVecVal* i); extern void i_union_2_state_33(const svBitVecVal* i); extern void i_union_2_state_64(const svBitVecVal* i); extern void i_union_2_state_65(const svBitVecVal* i); extern void i_union_4_state_1(const svLogicVecVal* i); extern void i_union_4_state_128(const svLogicVecVal* i); extern void i_union_4_state_32(const svLogicVecVal* i); extern void i_union_4_state_33(const svLogicVecVal* i); extern void i_union_4_state_64(const svLogicVecVal* i); extern void i_union_4_state_65(const svLogicVecVal* i); #ifdef __cplusplus } #endif #endif // guard verilator-5.042/test_regress/t/t_sys_rand.v0000644000542200017500000000160315101701376021422 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg [31:0] lastrand; reg [31:0] thisrand; integer same = 0; integer i; `define TRIES 20 initial begin // There's a 1^32 chance of the numbers being the same twice, // so we'll allow one failure lastrand = $random; for (i=0; i<`TRIES; i=i+1) begin thisrand = $random; `ifdef TEST_VERBOSE $write("Random = %x\n", thisrand); `endif if (thisrand == lastrand) same=same+1; lastrand = thisrand; end if (same > 1) begin $write("%%Error: Too many similar numbers: %d\n", same); $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_wrapper_context_fst.py0000755000542200017500000000152215101701376024066 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Multiple Model Test Module # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_wrapper_context.cpp" test.top_filename = "t/t_wrapper_context.v" test.compile( make_top_shell=False, make_main=False, # link threads library, add custom .cpp code, add tracing & coverage support verilator_flags2=["--exe", test.pli_filename, "--trace-fst --coverage -cc +define+TRACE_FST"], threads=1, make_flags=['CPPFLAGS_ADD=-DVL_NO_LEGACY']) test.execute() test.passes() verilator-5.042/test_regress/t/t_class1.py0000755000542200017500000000100015101701376021143 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_property.v0000644000542200017500000000243615101701376021471 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; Test test (/*AUTOINST*/ // Inputs .clk (clk), .cyc (cyc[31:0])); always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module Test ( input clk, input [31:0] cyc ); `ifdef FAIL_ASSERT_1 assert property (@(posedge clk) cyc==3) else $display("cyc != 3, cyc == %0d", cyc); assume property (@(posedge clk) cyc==3) else $display("cyc != 3, cyc == %0d", cyc); `endif `ifdef FAIL_ASSERT_2 assert property (@(posedge clk) cyc!=3); assume property (@(posedge clk) cyc!=3); `endif assert property (@(posedge clk) cyc < 100); assume property (@(posedge clk) cyc < 100); restrict property (@(posedge clk) cyc==1); // Ignored in simulators // Unclocked is not supported: // assert property (cyc != 6); endmodule verilator-5.042/test_regress/t/t_queue_class.py0000755000542200017500000000073415101701376022303 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_timing_clkgen_unsup.py0000755000542200017500000000110015101701376024022 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.top_filename = "t/t_timing_clkgen1.v" test.lint(verilator_flags2=["--timing"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_property_pexpr.v0000644000542200017500000000442515101701376022707 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t(/*AUTOARG*/ // Inputs clk ); input clk; int cyc; reg [63:0] crc; // Take CRC data and apply to testblock inputs wire a = crc[0]; wire b = crc[1]; /*AUTOWIRE*/ Test test(.*); // Test loop always @(posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x\n", $time, cyc, crc); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; if (cyc == 0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc == 99) begin `checkh(crc, 64'hc77bb9b3784ea091); // Result check `checkd(test.count_hits_iff, 48); `checkd(test.count_hits_implies, 24); `checkd(test.count_hits_not, 47); `checkd(test.count_hits_event, 1); $write("*-* All Finished *-*\n"); $finish; end end always @(negedge clk) begin if (cyc == 10) -> test.e; end endmodule module Test(input clk, input int cyc, input a, input b); int count_hits_iff; int count_hits_implies; int count_hits_not; int count_hits_event; event e; default disable iff cyc < 5; // property_expr1 iff property_expr2: true if (!property_expr1 && !property_expr2) || (property_expr1 && property_expr2) assert property ( @(negedge clk) a iff b ) else count_hits_iff = count_hits_iff + 1; // property_expr1 implies property_expr2: true if !property_expr1 || property_expr2 assert property ( @(negedge clk) a implies b ) else count_hits_implies = count_hits_implies + 1; assert property ( @(negedge clk) not a ) else count_hits_not = count_hits_not + 1; assert property ( @e not a ) else count_hits_event = count_hits_event + 1; endmodule verilator-5.042/test_regress/t/t_stream_unpack.py0000755000542200017500000000073415101701376022626 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_opt_const_shortcut.cpp0000644000542200017500000000104315101701376024056 0ustar mahmoudyfreeshell// This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include extern "C" int import_func0() { static int c = 0; return ++c; } extern "C" int import_func1() { static int c = 0; return ++c; } extern "C" int import_func2() { static int c = 0; return ++c; } extern "C" int import_func3() { static int c = 0; return ++c; } extern "C" int import_func4() { static int c = 0; return ++c; } verilator-5.042/test_regress/t/t_var_ref_bad1.v0000644000542200017500000000066415101701376022121 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Make sure type errors aren't suppressable // verilator lint_off WIDTH module t; bit bad_parent; sub sub (.bad_sub_ref(bad_parent)); // Type mismatch endmodule module sub(ref real bad_sub_ref); endmodule verilator-5.042/test_regress/t/t_savable_format2_bad.out0000644000542200017500000000040415101701376024015 0ustar mahmoudyfreeshellModel width = 10 Restoring model from 'obj_vlt/t_savable_format2_bad/saved.vltsv' %Error: obj_vlt/t_savable_format2_bad/saved.vltsv:0: Can't deserialize; file has wrong header signature, or file not found: obj_vlt/t_savable_format2_bad/saved.vltsv Aborting... verilator-5.042/test_regress/t/t_altera_lpm.v0000644000542200017500000072121515101701376021730 0ustar mahmoudyfreeshell//------------------------------------------------------------------------- // This Verilog file was developed by Altera Corporation. It may be // freely copied and/or distributed at no cost. Any persons using this // file for any purpose do so at their own risk, and are responsible for // the results of such use. Altera Corporation does not guarantee that // this file is complete, correct, or fit for any particular purpose. // NO WARRANTY OF ANY KIND IS EXPRESSED OR IMPLIED. This notice must // accompany any copy of this file. //------------------------------------------------------------------------ // // Quartus Prime 16.1.0 Build 196 10/24/2016 // //------------------------------------------------------------------------ // LPM Synthesizable Models (Support string type generic) // These models are based on LPM version 220 (EIA-IS103 October 1998). //------------------------------------------------------------------------ // //----------------------------------------------------------------------------- // Assumptions: // // 1. The default value for LPM_SVALUE, LPM_AVALUE, LPM_PVALUE, and // LPM_STRENGTH is string UNUSED. // //----------------------------------------------------------------------------- // Verilog Language Issues: // // Two dimensional ports are not supported. Modules with two dimensional // ports are implemented as one dimensional signal of (LPM_SIZE * LPM_WIDTH) // bits wide. // //----------------------------------------------------------------------------- //START_MODULE_NAME------------------------------------------------------------ // // Module Name : LPM_MEMORY_INITIALIZATION // // Description : Common function to read intel-hex format data file with // extension .hex and creates the equivalent verilog format // data file with extension .ver. // // Limitation : Supports only record type '00'(data record), '01'(end of // file record) and '02'(extended segment address record). // // Results expected: Creates the verilog format data file with extension .ver // and return the name of the file. // //END_MODULE_NAME-------------------------------------------------------------- //See also: https://github.com/twosigma/verilator_support // verilator lint_off COMBDLY,INITIALDLY,LATCH,MULTIDRIVEN,UNSIGNED,WIDTH // BEGINNING OF MODULE `timescale 1 ps / 1 ps `define LPM_TRUE 1 `define LPM_FALSE 0 `define LPM_NULL 0 `define LPM_EOF -1 `define LPM_MAX_NAME_SZ 128 `define LPM_MAX_WIDTH 256 `define LPM_COLON ":" `define LPM_DOT "." `define LPM_NEWLINE "\n" `define LPM_CARRIAGE_RETURN 8'h0D `define LPM_SPACE " " `define LPM_TAB "\t" `define LPM_OPEN_BRACKET "[" `define LPM_CLOSE_BRACKET "]" `define LPM_OFFSET 9 `define LPM_H10 8'h10 `define LPM_H10000 20'h10000 `define LPM_AWORD 8 `define LPM_MASK15 32'h000000FF `define LPM_EXT_STR "ver" `define LPM_PERCENT "%" `define LPM_MINUS "-" `define LPM_SEMICOLON ";" `define LPM_EQUAL "=" // MODULE DECLARATION module LPM_MEMORY_INITIALIZATION; /****************************************************************/ /* convert uppercase character values to lowercase. */ /****************************************************************/ function [8:1] tolower; input [8:1] given_character; reg [8:1] conv_char; begin if ((given_character >= 65) && (given_character <= 90)) // ASCII number of 'A' is 65, 'Z' is 90 begin conv_char = given_character + 32; // 32 is the difference in the position of 'A' and 'a' in the ASCII char set tolower = conv_char; end else tolower = given_character; end endfunction /****************************************************************/ /* Read in Altera-mif format data to verilog format data. */ /****************************************************************/ task convert_mif2ver; input[`LPM_MAX_NAME_SZ*8 : 1] in_file; input width; output [`LPM_MAX_NAME_SZ*8 : 1] out_file; reg [`LPM_MAX_NAME_SZ*8 : 1] in_file; reg [`LPM_MAX_NAME_SZ*8 : 1] out_file; reg [`LPM_MAX_NAME_SZ*8 : 1] buffer; reg [`LPM_MAX_WIDTH : 0] memory_data1, memory_data2; reg [8 : 1] c; reg [3 : 0] hex, tmp_char; reg [24 : 1] address_radix, data_radix; reg get_width; reg get_depth; reg get_data_radix; reg get_address_radix; reg width_found; reg depth_found; reg data_radix_found; reg address_radix_found; reg get_address_data_pairs; reg get_address; reg get_data; reg display_address; reg invalid_address; reg get_start_address; reg get_end_address; reg done; reg error_status; reg first_rec; reg last_rec; integer width; integer memory_width, memory_depth; integer value; integer ifp, ofp, r, r2; integer i, j, k, m, n; integer off_addr, nn, address, tt, cc, aah, aal, dd, sum ; integer start_address, end_address; integer line_no; integer character_count; integer comment_with_percent_found; integer comment_with_double_minus_found; begin done = `LPM_FALSE; error_status = `LPM_FALSE; first_rec = `LPM_FALSE; last_rec = `LPM_FALSE; comment_with_percent_found = `LPM_FALSE; comment_with_double_minus_found = `LPM_FALSE; off_addr= 0; nn= 0; address = 0; start_address = 0; end_address = 0; tt= 0; cc= 0; aah= 0; aal= 0; dd= 0; sum = 0; line_no = 1; c = 0; hex = 0; value = 0; buffer = ""; character_count = 0; memory_width = 0; memory_depth = 0; memory_data1 = {(`LPM_MAX_WIDTH+1) {1'b0}}; memory_data2 = {(`LPM_MAX_WIDTH+1) {1'b0}}; address_radix = "hex"; data_radix = "hex"; get_width = `LPM_FALSE; get_depth = `LPM_FALSE; get_data_radix = `LPM_FALSE; get_address_radix = `LPM_FALSE; width_found = `LPM_FALSE; depth_found = `LPM_FALSE; data_radix_found = `LPM_FALSE; address_radix_found = `LPM_FALSE; get_address_data_pairs = `LPM_FALSE; display_address = `LPM_FALSE; invalid_address = `LPM_FALSE; get_start_address = `LPM_FALSE; get_end_address = `LPM_FALSE; if((in_file[4*8 : 1] == ".dat") || (in_file[4*8 : 1] == ".DAT")) out_file = in_file; else begin ifp = $fopen(in_file, "r"); if (ifp == `LPM_NULL) begin $display("ERROR: cannot read %0s.", in_file); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; end out_file = in_file; if((out_file[4*8 : 1] == ".mif") || (out_file[4*8 : 1] == ".MIF")) out_file[3*8 : 1] = `LPM_EXT_STR; else begin $display("ERROR: Invalid input file name %0s. Expecting file with .mif extension and Altera-mif data format.", in_file); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; end if (!done) begin ofp = $fopen(out_file, "w"); if (ofp == `LPM_NULL) begin $display("ERROR : cannot write %0s.", out_file); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; end end while((!done) && (!error_status)) begin : READER r = $fgetc(ifp); if (r == `LPM_EOF) begin // to do : add more checking on whether a particular assigment(width, depth, memory/address) are mising if(!first_rec) begin error_status = `LPM_TRUE; $display("WARNING: %0s, Intel-hex data file is empty.", in_file); $display ("Time: %0t Instance: %m", $time); end else if (!get_address_data_pairs) begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Missing `content begin` statement.", in_file, line_no); $display("Time: %0t Instance: %m", $time); end else if(!last_rec) begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Missing `end` statement.", in_file, line_no); $display("Time: %0t Instance: %m", $time); end done = `LPM_TRUE; end else if ((r == `LPM_NEWLINE) || (r == `LPM_CARRIAGE_RETURN)) begin if ((buffer == "contentbegin") && (get_address_data_pairs == `LPM_FALSE)) begin get_address_data_pairs = `LPM_TRUE; get_address = `LPM_TRUE; buffer = ""; end else if (buffer == "content") begin // continue to next character end else if (buffer != "") begin // found invalid syntax in the particular line. error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid Altera-mif record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); disable READER; end line_no = line_no +1; end else if ((r == `LPM_SPACE) || (r == `LPM_TAB)) begin // continue to next character; end else if (r == `LPM_PERCENT) begin // Ignore all the characters which which is part of comment. r = $fgetc(ifp); while ((r != `LPM_PERCENT) && (r != `LPM_NEWLINE) && (r != `LPM_CARRIAGE_RETURN)) begin r = $fgetc(ifp); end if ((r == `LPM_NEWLINE) || (r == `LPM_CARRIAGE_RETURN)) begin line_no = line_no +1; if ((buffer == "contentbegin") && (get_address_data_pairs == `LPM_FALSE)) begin get_address_data_pairs = `LPM_TRUE; get_address = `LPM_TRUE; buffer = ""; end end end else if (r == `LPM_MINUS) begin r = $fgetc(ifp); if (r == `LPM_MINUS) begin // Ignore all the characters which which is part of comment. r = $fgetc(ifp); while ((r != `LPM_NEWLINE) && (r != `LPM_CARRIAGE_RETURN)) begin r = $fgetc(ifp); end if ((r == `LPM_NEWLINE) || (r == `LPM_CARRIAGE_RETURN)) begin line_no = line_no +1; if ((buffer == "contentbegin") && (get_address_data_pairs == `LPM_FALSE)) begin get_address_data_pairs = `LPM_TRUE; get_address = `LPM_TRUE; buffer = ""; end end end else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid Altera-mif record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; disable READER; end end else if (r == `LPM_EQUAL) begin if (buffer == "width") begin if (width_found == `LPM_FALSE) begin get_width = `LPM_TRUE; buffer = ""; end else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Width has already been specified once.", in_file, line_no); $display("Time: %0t Instance: %m", $time); end end else if (buffer == "depth") begin get_depth = `LPM_TRUE; buffer = ""; end else if (buffer == "data_radix") begin get_data_radix = `LPM_TRUE; buffer = ""; end else if (buffer == "address_radix") begin get_address_radix = `LPM_TRUE; buffer = ""; end else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Unknown setting (%0s).", in_file, line_no, buffer); $display("Time: %0t Instance: %m", $time); end end else if (r == `LPM_COLON) begin if (!get_address_data_pairs) begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Missing `content begin` statement.", in_file, line_no); $display("Time: %0t Instance: %m", $time); end else if (invalid_address == `LPM_TRUE) begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); end begin get_address = `LPM_FALSE; get_data = `LPM_TRUE; display_address = `LPM_TRUE; end end else if (r == `LPM_DOT) begin r = $fgetc(ifp); if (r == `LPM_DOT) begin if (get_start_address == `LPM_TRUE) begin start_address = address; address = 0; get_start_address = `LPM_FALSE; get_end_address = `LPM_TRUE; end else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid Altera-mif record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; disable READER; end end else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid Altera-mif record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; disable READER; end end else if (r == `LPM_OPEN_BRACKET) begin get_start_address = `LPM_TRUE; end else if (r == `LPM_CLOSE_BRACKET) begin if (get_end_address == `LPM_TRUE) begin end_address = address; address = 0; get_end_address = `LPM_FALSE; end else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid Altera-mif record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; disable READER; end end else if (r == `LPM_SEMICOLON) begin if (get_width == `LPM_TRUE) begin width_found = `LPM_TRUE; memory_width = value; value = 0; get_width = `LPM_FALSE; end else if (get_depth == `LPM_TRUE) begin depth_found = `LPM_TRUE; memory_depth = value; value = 0; get_depth = `LPM_FALSE; end else if (get_data_radix == `LPM_TRUE) begin data_radix_found = `LPM_TRUE; get_data_radix = `LPM_FALSE; if ((buffer == "bin") || (buffer == "oct") || (buffer == "dec") || (buffer == "uns") || (buffer == "hex")) begin data_radix = buffer[24 : 1]; end else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid assignment (%0s) to data_radix.", in_file, line_no, buffer); $display("Time: %0t Instance: %m", $time); end buffer = ""; end else if (get_address_radix == `LPM_TRUE) begin address_radix_found = `LPM_TRUE; get_address_radix = `LPM_FALSE; if ((buffer == "bin") || (buffer == "oct") || (buffer == "dec") || (buffer == "uns") || (buffer == "hex")) begin address_radix = buffer[24 : 1]; end else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid assignment (%0s) to address radix.", in_file, line_no, buffer); $display("Time: %0t Instance: %m", $time); end buffer = ""; end else if (buffer == "end") begin if (get_address_data_pairs == `LPM_TRUE) begin last_rec = `LPM_TRUE; buffer = ""; end else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Missing `content begin` statement.", in_file, line_no); $display("Time: %0t Instance: %m", $time); end end else if (get_data == `LPM_TRUE) begin get_address = `LPM_TRUE; get_data = `LPM_FALSE; buffer = ""; character_count = 0; if (start_address != end_address) begin for (address = start_address; address <= end_address; address = address+1) begin $fdisplay(ofp,"@%0h", address); for (i = memory_width -1; i >= 0; i = i-1 ) begin hex[(i % 4)] = memory_data1[i]; if ((i % 4) == 0) begin $fwrite(ofp, "%0h", hex); hex = 0; end end $fwrite(ofp, "\n"); end start_address = 0; end_address = 0; address = 0; hex = 0; memory_data1 = {(`LPM_MAX_WIDTH+1) {1'b0}}; end else begin if (display_address == `LPM_TRUE) begin $fdisplay(ofp,"@%0h", address); display_address = `LPM_FALSE; end for (i = memory_width -1; i >= 0; i = i-1 ) begin hex[(i % 4)] = memory_data1[i]; if ((i % 4) == 0) begin $fwrite(ofp, "%0h", hex); hex = 0; end end $fwrite(ofp, "\n"); address = 0; hex = 0; memory_data1 = {(`LPM_MAX_WIDTH+1) {1'b0}}; end end else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid assigment.", in_file, line_no); $display("Time: %0t Instance: %m", $time); end end else if ((get_width == `LPM_TRUE) || (get_depth == `LPM_TRUE)) begin if ((r >= "0") && (r <= "9")) value = (value * 10) + (r - 'h30); else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid assignment to width/depth.", in_file, line_no); $display("Time: %0t Instance: %m", $time); end end else if (get_address == `LPM_TRUE) begin if (address_radix == "hex") begin if ((r >= "0") && (r <= "9")) value = (r - 'h30); else if ((r >= "A") && (r <= "F")) value = 10 + (r - 'h41); else if ((r >= "a") && (r <= "f")) value = 10 + (r - 'h61); else begin invalid_address = `LPM_TRUE; end address = (address * 16) + value; end else if ((address_radix == "dec")) begin if ((r >= "0") && (r <= "9")) value = (r - 'h30); else begin invalid_address = `LPM_TRUE; end address = (address * 10) + value; end else if (address_radix == "uns") begin if ((r >= "0") && (r <= "9")) value = (r - 'h30); else begin invalid_address = `LPM_TRUE; end address = (address * 10) + value; end else if (address_radix == "bin") begin if ((r >= "0") && (r <= "1")) value = (r - 'h30); else begin invalid_address = `LPM_TRUE; end address = (address * 2) + value; end else if (address_radix == "oct") begin if ((r >= "0") && (r <= "7")) value = (r - 'h30); else begin invalid_address = `LPM_TRUE; end address = (address * 8) + value; end if ((r >= 65) && (r <= 90)) c = tolower(r); else c = r; {tmp_char,buffer} = {buffer, c}; end else if (get_data == `LPM_TRUE) begin character_count = character_count +1; if (data_radix == "hex") begin if ((r >= "0") && (r <= "9")) value = (r - 'h30); else if ((r >= "A") && (r <= "F")) value = 10 + (r - 'h41); else if ((r >= "a") && (r <= "f")) value = 10 + (r - 'h61); else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; disable READER; end memory_data1 = (memory_data1 * 16) + value; end else if ((data_radix == "dec")) begin if ((r >= "0") && (r <= "9")) value = (r - 'h30); else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; disable READER; end memory_data1 = (memory_data1 * 10) + value; end else if (data_radix == "uns") begin if ((r >= "0") && (r <= "9")) value = (r - 'h30); else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; disable READER; end memory_data1 = (memory_data1 * 10) + value; end else if (data_radix == "bin") begin if ((r >= "0") && (r <= "1")) value = (r - 'h30); else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; disable READER; end memory_data1 = (memory_data1 * 2) + value; end else if (data_radix == "oct") begin if ((r >= "0") && (r <= "7")) value = (r - 'h30); else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; disable READER; end memory_data1 = (memory_data1 * 8) + value; end end else begin first_rec = `LPM_TRUE; if ((r >= 65) && (r <= 90)) c = tolower(r); else c = r; {tmp_char,buffer} = {buffer, c}; end end $fclose(ifp); $fclose(ofp); end end endtask // convert_mif2ver /****************************************************************/ /* Read in Intel-hex format data to verilog format data. */ /* Intel-hex format :nnaaaaattddddcc */ /****************************************************************/ task convert_hex2ver; input[`LPM_MAX_NAME_SZ*8 : 1] in_file; input width; output [`LPM_MAX_NAME_SZ*8 : 1] out_file; reg [`LPM_MAX_NAME_SZ*8 : 1] in_file; reg [`LPM_MAX_NAME_SZ*8 : 1] out_file; reg [8:1] c; reg [3:0] hex, tmp_char; reg done; reg error_status; reg first_rec; reg last_rec; integer width; integer ifp, ofp, r, r2; integer i, j, k, m, n; integer off_addr, nn, aaaa, tt, cc, aah, aal, dd, sum ; integer line_no; begin done = `LPM_FALSE; error_status = `LPM_FALSE; first_rec = `LPM_FALSE; last_rec = `LPM_FALSE; off_addr= 0; nn= 0; aaaa= 0; tt= 0; cc= 0; aah= 0; aal= 0; dd= 0; sum = 0; line_no = 1; c = 0; hex = 0; if((in_file[4*8 : 1] == ".dat") || (in_file[4*8 : 1] == ".DAT")) out_file = in_file; else begin ifp = $fopen(in_file, "r"); if (ifp == `LPM_NULL) begin $display("ERROR: cannot read %0s.", in_file); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; end out_file = in_file; if((out_file[4*8 : 1] == ".hex") || (out_file[4*8 : 1] == ".HEX")) out_file[3*8 : 1] = `LPM_EXT_STR; else begin $display("ERROR: Invalid input file name %0s. Expecting file with .hex extension and Intel-hex data format.", in_file); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; end if (!done) begin ofp = $fopen(out_file, "w"); if (ofp == `LPM_NULL) begin $display("ERROR : cannot write %0s.", out_file); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; end end while((!done) && (!error_status)) begin : READER r = $fgetc(ifp); if (r == `LPM_EOF) begin if(!first_rec) begin error_status = `LPM_TRUE; $display("WARNING: %0s, Intel-hex data file is empty.", in_file); $display ("Time: %0t Instance: %m", $time); end else if(!last_rec) begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Missing the last record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); end end else if (r == `LPM_COLON) begin first_rec = `LPM_TRUE; nn= 0; aaaa= 0; tt= 0; cc= 0; aah= 0; aal= 0; dd= 0; sum = 0; // get record length bytes for (i = 0; i < 2; i = i+1) begin r = $fgetc(ifp); if ((r >= "0") && (r <= "9")) nn = (nn * 16) + (r - 'h30); else if ((r >= "A") && (r <= "F")) nn = (nn * 16) + 10 + (r - 'h41); else if ((r >= "a") && (r <= "f")) nn = (nn * 16) + 10 + (r - 'h61); else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; disable READER; end end // get address bytes for (i = 0; i < 4; i = i+1) begin r = $fgetc(ifp); if ((r >= "0") && (r <= "9")) hex = (r - 'h30); else if ((r >= "A") && (r <= "F")) hex = 10 + (r - 'h41); else if ((r >= "a") && (r <= "f")) hex = 10 + (r - 'h61); else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; disable READER; end aaaa = (aaaa * 16) + hex; if (i < 2) aal = (aal * 16) + hex; else aah = (aah * 16) + hex; end // get record type bytes for (i = 0; i < 2; i = i+1) begin r = $fgetc(ifp); if ((r >= "0") && (r <= "9")) tt = (tt * 16) + (r - 'h30); else if ((r >= "A") && (r <= "F")) tt = (tt * 16) + 10 + (r - 'h41); else if ((r >= "a") && (r <= "f")) tt = (tt * 16) + 10 + (r - 'h61); else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; disable READER; end end if((tt == 2) && (nn != 2) ) begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); end else begin // get the sum of all the bytes for record length, address and record types sum = nn + aah + aal + tt ; // check the record type case(tt) // normal_record 8'h00 : begin first_rec = `LPM_TRUE; i = 0; k = width / `LPM_AWORD; if ((width % `LPM_AWORD) != 0) k = k + 1; // k = no. of bytes per entry. while (i < nn) begin $fdisplay(ofp,"@%0h", (aaaa + off_addr)); for (j = 1; j <= k; j = j +1) begin if ((k - j +1) > nn) begin for(m = 1; m <= 2; m= m+1) begin if((((k-j)*8) + ((3-m)*4) - width) < 4) $fwrite(ofp, "0"); end end else begin // get the data bytes for(m = 1; m <= 2; m= m+1) begin r = $fgetc(ifp); if ((r >= "0") && (r <= "9")) hex = (r - 'h30); else if ((r >= "A") && (r <= "F")) hex = 10 + (r - 'h41); else if ((r >= "a") && (r <= "f")) hex = 10 + (r - 'h61); else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; disable READER; end if((((k-j)*8) + ((3-m)*4) - width) < 4) $fwrite(ofp, "%h", hex); dd = (dd * 16) + hex; if(m % 2 == 0) begin sum = sum + dd; dd = 0; end end end end $fwrite(ofp, "\n"); i = i + k; aaaa = aaaa + 1; end // end of while (i < nn) end // last record 8'h01: begin last_rec = `LPM_TRUE; done = `LPM_TRUE; end // address base record 8'h02: begin off_addr= 0; // get the extended segment address record for(i = 1; i <= (nn*2); i= i+1) begin r = $fgetc(ifp); if ((r >= "0") && (r <= "9")) hex = (r - 'h30); else if ((r >= "A") && (r <= "F")) hex = 10 + (r - 'h41); else if ((r >= "a") && (r <= "f")) hex = 10 + (r - 'h61); else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; disable READER; end off_addr = (off_addr * `LPM_H10) + hex; dd = (dd * 16) + hex; if(i % 2 == 0) begin sum = sum + dd; dd = 0; end end off_addr = off_addr * `LPM_H10; end // address base record 8'h03: // get the start segment address record for(i = 1; i <= (nn*2); i= i+1) begin r = $fgetc(ifp); if ((r >= "0") && (r <= "9")) hex = (r - 'h30); else if ((r >= "A") && (r <= "F")) hex = 10 + (r - 'h41); else if ((r >= "a") && (r <= "f")) hex = 10 + (r - 'h61); else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; disable READER; end dd = (dd * 16) + hex; if(i % 2 == 0) begin sum = sum + dd; dd = 0; end end // address base record 8'h04: begin off_addr= 0; // get the extended linear address record for(i = 1; i <= (nn*2); i= i+1) begin r = $fgetc(ifp); if ((r >= "0") && (r <= "9")) hex = (r - 'h30); else if ((r >= "A") && (r <= "F")) hex = 10 + (r - 'h41); else if ((r >= "a") && (r <= "f")) hex = 10 + (r - 'h61); else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; disable READER; end off_addr = (off_addr * `LPM_H10) + hex; dd = (dd * 16) + hex; if(i % 2 == 0) begin sum = sum + dd; dd = 0; end end off_addr = off_addr * `LPM_H10000; end // address base record 8'h05: // get the start linear address record for(i = 1; i <= (nn*2); i= i+1) begin r = $fgetc(ifp); if ((r >= "0") && (r <= "9")) hex = (r - 'h30); else if ((r >= "A") && (r <= "F")) hex = 10 + (r - 'h41); else if ((r >= "a") && (r <= "f")) hex = 10 + (r - 'h61); else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; disable READER; end dd = (dd * 16) + hex; if(i % 2 == 0) begin sum = sum + dd; dd = 0; end end default: begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Unknown record type.", in_file, line_no); $display("Time: %0t Instance: %m", $time); end endcase // get the checksum bytes for (i = 0; i < 2; i = i+1) begin r = $fgetc(ifp); if ((r >= "0") && (r <= "9")) cc = (cc * 16) + (r - 'h30); else if ((r >= "A") && (r <= "F")) cc = 10 + (cc * 16) + (r - 'h41); else if ((r >= "a") && (r <= "f")) cc = 10 + (cc * 16) + (r - 'h61); else begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; disable READER; end end // Perform check sum. if(((~sum+1)& `LPM_MASK15) != cc) begin error_status = `LPM_TRUE; $display("ERROR: %0s, line %0d, Invalid checksum.", in_file, line_no); $display("Time: %0t Instance: %m", $time); end end end else if ((r == `LPM_NEWLINE) || (r == `LPM_CARRIAGE_RETURN)) begin line_no = line_no +1; end else if (r == `LPM_SPACE) begin // continue to next character; end else begin error_status = `LPM_TRUE; $display("ERROR:%0s, line %0d, Invalid INTEL HEX record.", in_file, line_no); $display("Time: %0t Instance: %m", $time); done = `LPM_TRUE; end end $fclose(ifp); $fclose(ofp); end end endtask // convert_hex2ver task convert_to_ver_file; input[`LPM_MAX_NAME_SZ*8 : 1] in_file; input width; output [`LPM_MAX_NAME_SZ*8 : 1] out_file; reg [`LPM_MAX_NAME_SZ*8 : 1] in_file; reg [`LPM_MAX_NAME_SZ*8 : 1] out_file; integer width; begin if((in_file[4*8 : 1] == ".hex") || (in_file[4*8 : 1] == ".HEX") || (in_file[4*8 : 1] == ".dat") || (in_file[4*8 : 1] == ".DAT")) convert_hex2ver(in_file, width, out_file); else if((in_file[4*8 : 1] == ".mif") || (in_file[4*8 : 1] == ".MIF")) convert_mif2ver(in_file, width, out_file); else begin $display("ERROR: Invalid input file name %0s. Expecting file with .hex extension (with Intel-hex data format) or .mif extension (with Altera-mif data format).", in_file); $display("Time: %0t Instance: %m", $time); end end endtask // convert_to_ver_file endmodule // LPM_MEMORY_INITIALIZATION //START_MODULE_NAME------------------------------------------------------------ // // Module Name : LPM_HINT_EVALUATION // // Description : Common function to grep the value of altera specific parameters // within the lpm_hint parameter. // // Limitation : No error checking to check whether the content of the lpm_hint // is valid or not. // // Results expected: If the target parameter found, return the value of the parameter. // Otherwise, return empty string. // //END_MODULE_NAME-------------------------------------------------------------- // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module LPM_HINT_EVALUATION; // FUNCTON DECLARATION // This function will search through the string (given string) to look for a match for the // a given parameter(compare_param_name). It will return the value for the given parameter. function [8*200:1] GET_PARAMETER_VALUE; input [8*200:1] given_string; // string to be searched input [8*50:1] compare_param_name; // parameter name to be looking for in the given_string. integer param_value_char_count; // to indicate current character count in the param_value integer param_name_char_count; // to indicate current character count in the param_name integer white_space_count; reg extract_param_value; // if 1 mean extracting parameters value from given string reg extract_param_name; // if 1 mean extracting parameters name from given string reg param_found; // to indicate whether compare_param_name have been found in the given_string reg include_white_space; // if 1, include white space in the parameter value reg [8*200:1] reg_string; // to store the value of the given string reg [8*50:1] param_name; // to store parameter name reg [8*20:1] param_value; // to store parameter value reg [8:1] tmp; // to get the value of the current byte begin reg_string = given_string; param_value_char_count = 0; param_name_char_count =0; extract_param_value = 1; extract_param_name = 0; param_found = 0; include_white_space = 0; white_space_count = 0; tmp = reg_string[8:1]; // checking every bytes of the reg_string from right to left. while ((tmp != 0 ) && (param_found != 1)) begin tmp = reg_string[8:1]; //if tmp != ' ' or should include white space (trailing white space are ignored) if((tmp != 32) || (include_white_space == 1)) begin if(tmp == 32) begin white_space_count = 1; end else if(tmp == 61) // if tmp = '=' begin extract_param_value = 0; extract_param_name = 1; // subsequent bytes should be part of param_name include_white_space = 0; // ignore the white space (if any) between param_name and '=' white_space_count = 0; param_value = param_value >> (8 * (20 - param_value_char_count)); param_value_char_count = 0; end else if (tmp == 44) // if tmp = ',' begin extract_param_value = 1; // subsequent bytes should be part of param_value extract_param_name = 0; param_name = param_name >> (8 * (50 - param_name_char_count)); param_name_char_count = 0; if(param_name == compare_param_name) param_found = 1; // the compare_param_name have been found in the reg_string end else begin if(extract_param_value == 1) begin param_value_char_count = param_value_char_count + white_space_count + 1; include_white_space = 1; if(white_space_count > 0) begin param_value = {8'b100000, param_value[20*8:9]}; white_space_count = 0; end param_value = {tmp, param_value[20*8:9]}; end else if(extract_param_name == 1) begin param_name = {tmp, param_name[50*8:9]}; param_name_char_count = param_name_char_count + 1; end end end reg_string = reg_string >> 8; // shift 1 byte to the right end // for the case whether param_name is the left most part of the reg_string if(extract_param_name == 1) begin param_name = param_name >> (8 * (50 - param_name_char_count)); if(param_name == compare_param_name) param_found = 1; end if (param_found == 1) GET_PARAMETER_VALUE = param_value; // return the value of the parameter been looking for else GET_PARAMETER_VALUE = ""; // return empty string if parameter not found end endfunction endmodule // LPM_HINT_EVALUATION // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module LPM_DEVICE_FAMILIES; function IS_FAMILY_CYCLONE; input[8*20:1] device; reg is_cyclone; begin if ((device == "Cyclone") || (device == "CYCLONE") || (device == "cyclone") || (device == "ACEX2K") || (device == "acex2k") || (device == "ACEX 2K") || (device == "acex 2k") || (device == "Tornado") || (device == "TORNADO") || (device == "tornado")) is_cyclone = 1; else is_cyclone = 0; IS_FAMILY_CYCLONE = is_cyclone; end endfunction //IS_FAMILY_CYCLONE function IS_FAMILY_MAX3000A; input[8*20:1] device; reg is_max3000a; begin if ((device == "MAX3000A") || (device == "max3000a") || (device == "MAX 3000A") || (device == "max 3000a")) is_max3000a = 1; else is_max3000a = 0; IS_FAMILY_MAX3000A = is_max3000a; end endfunction //IS_FAMILY_MAX3000A function IS_FAMILY_MAX7000A; input[8*20:1] device; reg is_max7000a; begin if ((device == "MAX7000A") || (device == "max7000a") || (device == "MAX 7000A") || (device == "max 7000a")) is_max7000a = 1; else is_max7000a = 0; IS_FAMILY_MAX7000A = is_max7000a; end endfunction //IS_FAMILY_MAX7000A function IS_FAMILY_MAX7000AE; input[8*20:1] device; reg is_max7000ae; begin if ((device == "MAX7000AE") || (device == "max7000ae") || (device == "MAX 7000AE") || (device == "max 7000ae")) is_max7000ae = 1; else is_max7000ae = 0; IS_FAMILY_MAX7000AE = is_max7000ae; end endfunction //IS_FAMILY_MAX7000AE function IS_FAMILY_MAX7000B; input[8*20:1] device; reg is_max7000b; begin if ((device == "MAX7000B") || (device == "max7000b") || (device == "MAX 7000B") || (device == "max 7000b")) is_max7000b = 1; else is_max7000b = 0; IS_FAMILY_MAX7000B = is_max7000b; end endfunction //IS_FAMILY_MAX7000B function IS_FAMILY_MAX7000S; input[8*20:1] device; reg is_max7000s; begin if ((device == "MAX7000S") || (device == "max7000s") || (device == "MAX 7000S") || (device == "max 7000s")) is_max7000s = 1; else is_max7000s = 0; IS_FAMILY_MAX7000S = is_max7000s; end endfunction //IS_FAMILY_MAX7000S function IS_FAMILY_STRATIXGX; input[8*20:1] device; reg is_stratixgx; begin if ((device == "Stratix GX") || (device == "STRATIX GX") || (device == "stratix gx") || (device == "Stratix-GX") || (device == "STRATIX-GX") || (device == "stratix-gx") || (device == "StratixGX") || (device == "STRATIXGX") || (device == "stratixgx") || (device == "Aurora") || (device == "AURORA") || (device == "aurora")) is_stratixgx = 1; else is_stratixgx = 0; IS_FAMILY_STRATIXGX = is_stratixgx; end endfunction //IS_FAMILY_STRATIXGX function IS_FAMILY_STRATIX; input[8*20:1] device; reg is_stratix; begin if ((device == "Stratix") || (device == "STRATIX") || (device == "stratix") || (device == "Yeager") || (device == "YEAGER") || (device == "yeager")) is_stratix = 1; else is_stratix = 0; IS_FAMILY_STRATIX = is_stratix; end endfunction //IS_FAMILY_STRATIX function FEATURE_FAMILY_BASE_STRATIX; input[8*20:1] device; reg var_family_base_stratix; begin if (IS_FAMILY_STRATIX(device) || IS_FAMILY_STRATIXGX(device) ) var_family_base_stratix = 1; else var_family_base_stratix = 0; FEATURE_FAMILY_BASE_STRATIX = var_family_base_stratix; end endfunction //FEATURE_FAMILY_BASE_STRATIX function FEATURE_FAMILY_BASE_CYCLONE; input[8*20:1] device; reg var_family_base_cyclone; begin if (IS_FAMILY_CYCLONE(device) ) var_family_base_cyclone = 1; else var_family_base_cyclone = 0; FEATURE_FAMILY_BASE_CYCLONE = var_family_base_cyclone; end endfunction //FEATURE_FAMILY_BASE_CYCLONE function FEATURE_FAMILY_MAX; input[8*20:1] device; reg var_family_max; begin if ((device == "MAX5000") || IS_FAMILY_MAX3000A(device) || (device == "MAX7000") || IS_FAMILY_MAX7000A(device) || IS_FAMILY_MAX7000AE(device) || (device == "MAX7000E") || IS_FAMILY_MAX7000S(device) || IS_FAMILY_MAX7000B(device) || (device == "MAX9000") ) var_family_max = 1; else var_family_max = 0; FEATURE_FAMILY_MAX = var_family_max; end endfunction //FEATURE_FAMILY_MAX function IS_VALID_FAMILY; input[8*20:1] device; reg is_valid; begin if (((device == "Arria 10") || (device == "ARRIA 10") || (device == "arria 10") || (device == "Arria10") || (device == "ARRIA10") || (device == "arria10") || (device == "Arria VI") || (device == "ARRIA VI") || (device == "arria vi") || (device == "ArriaVI") || (device == "ARRIAVI") || (device == "arriavi") || (device == "Night Fury") || (device == "NIGHT FURY") || (device == "night fury") || (device == "nightfury") || (device == "NIGHTFURY") || (device == "Arria 10 (GX/SX/GT)") || (device == "ARRIA 10 (GX/SX/GT)") || (device == "arria 10 (gx/sx/gt)") || (device == "Arria10(GX/SX/GT)") || (device == "ARRIA10(GX/SX/GT)") || (device == "arria10(gx/sx/gt)") || (device == "Arria 10 (GX)") || (device == "ARRIA 10 (GX)") || (device == "arria 10 (gx)") || (device == "Arria10(GX)") || (device == "ARRIA10(GX)") || (device == "arria10(gx)") || (device == "Arria 10 (SX)") || (device == "ARRIA 10 (SX)") || (device == "arria 10 (sx)") || (device == "Arria10(SX)") || (device == "ARRIA10(SX)") || (device == "arria10(sx)") || (device == "Arria 10 (GT)") || (device == "ARRIA 10 (GT)") || (device == "arria 10 (gt)") || (device == "Arria10(GT)") || (device == "ARRIA10(GT)") || (device == "arria10(gt)")) || ((device == "Arria GX") || (device == "ARRIA GX") || (device == "arria gx") || (device == "ArriaGX") || (device == "ARRIAGX") || (device == "arriagx") || (device == "Stratix II GX Lite") || (device == "STRATIX II GX LITE") || (device == "stratix ii gx lite") || (device == "StratixIIGXLite") || (device == "STRATIXIIGXLITE") || (device == "stratixiigxlite")) || ((device == "Arria II GX") || (device == "ARRIA II GX") || (device == "arria ii gx") || (device == "ArriaIIGX") || (device == "ARRIAIIGX") || (device == "arriaiigx") || (device == "Arria IIGX") || (device == "ARRIA IIGX") || (device == "arria iigx") || (device == "ArriaII GX") || (device == "ARRIAII GX") || (device == "arriaii gx") || (device == "Arria II") || (device == "ARRIA II") || (device == "arria ii") || (device == "ArriaII") || (device == "ARRIAII") || (device == "arriaii") || (device == "Arria II (GX/E)") || (device == "ARRIA II (GX/E)") || (device == "arria ii (gx/e)") || (device == "ArriaII(GX/E)") || (device == "ARRIAII(GX/E)") || (device == "arriaii(gx/e)") || (device == "PIRANHA") || (device == "piranha")) || ((device == "Arria II GZ") || (device == "ARRIA II GZ") || (device == "arria ii gz") || (device == "ArriaII GZ") || (device == "ARRIAII GZ") || (device == "arriaii gz") || (device == "Arria IIGZ") || (device == "ARRIA IIGZ") || (device == "arria iigz") || (device == "ArriaIIGZ") || (device == "ARRIAIIGZ") || (device == "arriaiigz")) || ((device == "Arria V GZ") || (device == "ARRIA V GZ") || (device == "arria v gz") || (device == "ArriaVGZ") || (device == "ARRIAVGZ") || (device == "arriavgz")) || ((device == "Arria V") || (device == "ARRIA V") || (device == "arria v") || (device == "Arria V (GT/GX)") || (device == "ARRIA V (GT/GX)") || (device == "arria v (gt/gx)") || (device == "ArriaV(GT/GX)") || (device == "ARRIAV(GT/GX)") || (device == "arriav(gt/gx)") || (device == "ArriaV") || (device == "ARRIAV") || (device == "arriav") || (device == "Arria V (GT/GX/ST/SX)") || (device == "ARRIA V (GT/GX/ST/SX)") || (device == "arria v (gt/gx/st/sx)") || (device == "ArriaV(GT/GX/ST/SX)") || (device == "ARRIAV(GT/GX/ST/SX)") || (device == "arriav(gt/gx/st/sx)") || (device == "Arria V (GT)") || (device == "ARRIA V (GT)") || (device == "arria v (gt)") || (device == "ArriaV(GT)") || (device == "ARRIAV(GT)") || (device == "arriav(gt)") || (device == "Arria V (GX)") || (device == "ARRIA V (GX)") || (device == "arria v (gx)") || (device == "ArriaV(GX)") || (device == "ARRIAV(GX)") || (device == "arriav(gx)") || (device == "Arria V (ST)") || (device == "ARRIA V (ST)") || (device == "arria v (st)") || (device == "ArriaV(ST)") || (device == "ARRIAV(ST)") || (device == "arriav(st)") || (device == "Arria V (SX)") || (device == "ARRIA V (SX)") || (device == "arria v (sx)") || (device == "ArriaV(SX)") || (device == "ARRIAV(SX)") || (device == "arriav(sx)")) || ((device == "BS") || (device == "bs")) || ((device == "Cyclone II") || (device == "CYCLONE II") || (device == "cyclone ii") || (device == "Cycloneii") || (device == "CYCLONEII") || (device == "cycloneii") || (device == "Magellan") || (device == "MAGELLAN") || (device == "magellan") || (device == "CycloneII") || (device == "CYCLONEII") || (device == "cycloneii")) || ((device == "Cyclone III LS") || (device == "CYCLONE III LS") || (device == "cyclone iii ls") || (device == "CycloneIIILS") || (device == "CYCLONEIIILS") || (device == "cycloneiiils") || (device == "Cyclone III LPS") || (device == "CYCLONE III LPS") || (device == "cyclone iii lps") || (device == "Cyclone LPS") || (device == "CYCLONE LPS") || (device == "cyclone lps") || (device == "CycloneLPS") || (device == "CYCLONELPS") || (device == "cyclonelps") || (device == "Tarpon") || (device == "TARPON") || (device == "tarpon") || (device == "Cyclone IIIE") || (device == "CYCLONE IIIE") || (device == "cyclone iiie")) || ((device == "Cyclone III") || (device == "CYCLONE III") || (device == "cyclone iii") || (device == "CycloneIII") || (device == "CYCLONEIII") || (device == "cycloneiii") || (device == "Barracuda") || (device == "BARRACUDA") || (device == "barracuda") || (device == "Cuda") || (device == "CUDA") || (device == "cuda") || (device == "CIII") || (device == "ciii")) || ((device == "Cyclone IV E") || (device == "CYCLONE IV E") || (device == "cyclone iv e") || (device == "CycloneIV E") || (device == "CYCLONEIV E") || (device == "cycloneiv e") || (device == "Cyclone IVE") || (device == "CYCLONE IVE") || (device == "cyclone ive") || (device == "CycloneIVE") || (device == "CYCLONEIVE") || (device == "cycloneive")) || ((device == "Cyclone IV GX") || (device == "CYCLONE IV GX") || (device == "cyclone iv gx") || (device == "Cyclone IVGX") || (device == "CYCLONE IVGX") || (device == "cyclone ivgx") || (device == "CycloneIV GX") || (device == "CYCLONEIV GX") || (device == "cycloneiv gx") || (device == "CycloneIVGX") || (device == "CYCLONEIVGX") || (device == "cycloneivgx") || (device == "Cyclone IV") || (device == "CYCLONE IV") || (device == "cyclone iv") || (device == "CycloneIV") || (device == "CYCLONEIV") || (device == "cycloneiv") || (device == "Cyclone IV (GX)") || (device == "CYCLONE IV (GX)") || (device == "cyclone iv (gx)") || (device == "CycloneIV(GX)") || (device == "CYCLONEIV(GX)") || (device == "cycloneiv(gx)") || (device == "Cyclone III GX") || (device == "CYCLONE III GX") || (device == "cyclone iii gx") || (device == "CycloneIII GX") || (device == "CYCLONEIII GX") || (device == "cycloneiii gx") || (device == "Cyclone IIIGX") || (device == "CYCLONE IIIGX") || (device == "cyclone iiigx") || (device == "CycloneIIIGX") || (device == "CYCLONEIIIGX") || (device == "cycloneiiigx") || (device == "Cyclone III GL") || (device == "CYCLONE III GL") || (device == "cyclone iii gl") || (device == "CycloneIII GL") || (device == "CYCLONEIII GL") || (device == "cycloneiii gl") || (device == "Cyclone IIIGL") || (device == "CYCLONE IIIGL") || (device == "cyclone iiigl") || (device == "CycloneIIIGL") || (device == "CYCLONEIIIGL") || (device == "cycloneiiigl") || (device == "Stingray") || (device == "STINGRAY") || (device == "stingray")) || ((device == "Cyclone V") || (device == "CYCLONE V") || (device == "cyclone v") || (device == "CycloneV") || (device == "CYCLONEV") || (device == "cyclonev") || (device == "Cyclone V (GT/GX/E/SX)") || (device == "CYCLONE V (GT/GX/E/SX)") || (device == "cyclone v (gt/gx/e/sx)") || (device == "CycloneV(GT/GX/E/SX)") || (device == "CYCLONEV(GT/GX/E/SX)") || (device == "cyclonev(gt/gx/e/sx)") || (device == "Cyclone V (E/GX/GT/SX/SE/ST)") || (device == "CYCLONE V (E/GX/GT/SX/SE/ST)") || (device == "cyclone v (e/gx/gt/sx/se/st)") || (device == "CycloneV(E/GX/GT/SX/SE/ST)") || (device == "CYCLONEV(E/GX/GT/SX/SE/ST)") || (device == "cyclonev(e/gx/gt/sx/se/st)") || (device == "Cyclone V (E)") || (device == "CYCLONE V (E)") || (device == "cyclone v (e)") || (device == "CycloneV(E)") || (device == "CYCLONEV(E)") || (device == "cyclonev(e)") || (device == "Cyclone V (GX)") || (device == "CYCLONE V (GX)") || (device == "cyclone v (gx)") || (device == "CycloneV(GX)") || (device == "CYCLONEV(GX)") || (device == "cyclonev(gx)") || (device == "Cyclone V (GT)") || (device == "CYCLONE V (GT)") || (device == "cyclone v (gt)") || (device == "CycloneV(GT)") || (device == "CYCLONEV(GT)") || (device == "cyclonev(gt)") || (device == "Cyclone V (SX)") || (device == "CYCLONE V (SX)") || (device == "cyclone v (sx)") || (device == "CycloneV(SX)") || (device == "CYCLONEV(SX)") || (device == "cyclonev(sx)") || (device == "Cyclone V (SE)") || (device == "CYCLONE V (SE)") || (device == "cyclone v (se)") || (device == "CycloneV(SE)") || (device == "CYCLONEV(SE)") || (device == "cyclonev(se)") || (device == "Cyclone V (ST)") || (device == "CYCLONE V (ST)") || (device == "cyclone v (st)") || (device == "CycloneV(ST)") || (device == "CYCLONEV(ST)") || (device == "cyclonev(st)")) || ((device == "Cyclone") || (device == "CYCLONE") || (device == "cyclone") || (device == "ACEX2K") || (device == "acex2k") || (device == "ACEX 2K") || (device == "acex 2k") || (device == "Tornado") || (device == "TORNADO") || (device == "tornado")) || ((device == "HardCopy II") || (device == "HARDCOPY II") || (device == "hardcopy ii") || (device == "HardCopyII") || (device == "HARDCOPYII") || (device == "hardcopyii") || (device == "Fusion") || (device == "FUSION") || (device == "fusion")) || ((device == "HardCopy III") || (device == "HARDCOPY III") || (device == "hardcopy iii") || (device == "HardCopyIII") || (device == "HARDCOPYIII") || (device == "hardcopyiii") || (device == "HCX") || (device == "hcx")) || ((device == "HardCopy IV") || (device == "HARDCOPY IV") || (device == "hardcopy iv") || (device == "HardCopyIV") || (device == "HARDCOPYIV") || (device == "hardcopyiv") || (device == "HardCopy IV (GX)") || (device == "HARDCOPY IV (GX)") || (device == "hardcopy iv (gx)") || (device == "HardCopy IV (E)") || (device == "HARDCOPY IV (E)") || (device == "hardcopy iv (e)") || (device == "HardCopyIV(GX)") || (device == "HARDCOPYIV(GX)") || (device == "hardcopyiv(gx)") || (device == "HardCopyIV(E)") || (device == "HARDCOPYIV(E)") || (device == "hardcopyiv(e)") || (device == "HCXIV") || (device == "hcxiv") || (device == "HardCopy IV (GX/E)") || (device == "HARDCOPY IV (GX/E)") || (device == "hardcopy iv (gx/e)") || (device == "HardCopy IV (E/GX)") || (device == "HARDCOPY IV (E/GX)") || (device == "hardcopy iv (e/gx)") || (device == "HardCopyIV(GX/E)") || (device == "HARDCOPYIV(GX/E)") || (device == "hardcopyiv(gx/e)") || (device == "HardCopyIV(E/GX)") || (device == "HARDCOPYIV(E/GX)") || (device == "hardcopyiv(e/gx)")) || ((device == "MAX 10") || (device == "max 10") || (device == "MAX 10 FPGA") || (device == "max 10 fpga") || (device == "Zippleback") || (device == "ZIPPLEBACK") || (device == "zippleback") || (device == "MAX10") || (device == "max10") || (device == "MAX 10 (DA/DF/DC/SA/SC)") || (device == "max 10 (da/df/dc/sa/sc)") || (device == "MAX10(DA/DF/DC/SA/SC)") || (device == "max10(da/df/dc/sa/sc)") || (device == "MAX 10 (DA)") || (device == "max 10 (da)") || (device == "MAX10(DA)") || (device == "max10(da)") || (device == "MAX 10 (DF)") || (device == "max 10 (df)") || (device == "MAX10(DF)") || (device == "max10(df)") || (device == "MAX 10 (DC)") || (device == "max 10 (dc)") || (device == "MAX10(DC)") || (device == "max10(dc)") || (device == "MAX 10 (SA)") || (device == "max 10 (sa)") || (device == "MAX10(SA)") || (device == "max10(sa)") || (device == "MAX 10 (SC)") || (device == "max 10 (sc)") || (device == "MAX10(SC)") || (device == "max10(sc)")) || ((device == "MAX II") || (device == "max ii") || (device == "MAXII") || (device == "maxii") || (device == "Tsunami") || (device == "TSUNAMI") || (device == "tsunami")) || ((device == "MAX V") || (device == "max v") || (device == "MAXV") || (device == "maxv") || (device == "Jade") || (device == "JADE") || (device == "jade")) || ((device == "MAX3000A") || (device == "max3000a") || (device == "MAX 3000A") || (device == "max 3000a")) || ((device == "MAX7000A") || (device == "max7000a") || (device == "MAX 7000A") || (device == "max 7000a")) || ((device == "MAX7000AE") || (device == "max7000ae") || (device == "MAX 7000AE") || (device == "max 7000ae")) || ((device == "MAX7000B") || (device == "max7000b") || (device == "MAX 7000B") || (device == "max 7000b")) || ((device == "MAX7000S") || (device == "max7000s") || (device == "MAX 7000S") || (device == "max 7000s")) || ((device == "Stratix 10") || (device == "STRATIX 10") || (device == "stratix 10") || (device == "Stratix10") || (device == "STRATIX10") || (device == "stratix10") || (device == "nadder") || (device == "NADDER") || (device == "Stratix 10 (GX/SX)") || (device == "STRATIX 10 (GX/SX)") || (device == "stratix 10 (gx/sx)") || (device == "Stratix10(GX/SX)") || (device == "STRATIX10(GX/SX)") || (device == "stratix10(gx/sx)") || (device == "Stratix 10 (GX)") || (device == "STRATIX 10 (GX)") || (device == "stratix 10 (gx)") || (device == "Stratix10(GX)") || (device == "STRATIX10(GX)") || (device == "stratix10(gx)") || (device == "Stratix 10 (SX)") || (device == "STRATIX 10 (SX)") || (device == "stratix 10 (sx)") || (device == "Stratix10(SX)") || (device == "STRATIX10(SX)") || (device == "stratix10(sx)")) || ((device == "Stratix GX") || (device == "STRATIX GX") || (device == "stratix gx") || (device == "Stratix-GX") || (device == "STRATIX-GX") || (device == "stratix-gx") || (device == "StratixGX") || (device == "STRATIXGX") || (device == "stratixgx") || (device == "Aurora") || (device == "AURORA") || (device == "aurora")) || ((device == "Stratix II GX") || (device == "STRATIX II GX") || (device == "stratix ii gx") || (device == "StratixIIGX") || (device == "STRATIXIIGX") || (device == "stratixiigx")) || ((device == "Stratix II") || (device == "STRATIX II") || (device == "stratix ii") || (device == "StratixII") || (device == "STRATIXII") || (device == "stratixii") || (device == "Armstrong") || (device == "ARMSTRONG") || (device == "armstrong")) || ((device == "Stratix III") || (device == "STRATIX III") || (device == "stratix iii") || (device == "StratixIII") || (device == "STRATIXIII") || (device == "stratixiii") || (device == "Titan") || (device == "TITAN") || (device == "titan") || (device == "SIII") || (device == "siii")) || ((device == "Stratix IV") || (device == "STRATIX IV") || (device == "stratix iv") || (device == "TGX") || (device == "tgx") || (device == "StratixIV") || (device == "STRATIXIV") || (device == "stratixiv") || (device == "Stratix IV (GT)") || (device == "STRATIX IV (GT)") || (device == "stratix iv (gt)") || (device == "Stratix IV (GX)") || (device == "STRATIX IV (GX)") || (device == "stratix iv (gx)") || (device == "Stratix IV (E)") || (device == "STRATIX IV (E)") || (device == "stratix iv (e)") || (device == "StratixIV(GT)") || (device == "STRATIXIV(GT)") || (device == "stratixiv(gt)") || (device == "StratixIV(GX)") || (device == "STRATIXIV(GX)") || (device == "stratixiv(gx)") || (device == "StratixIV(E)") || (device == "STRATIXIV(E)") || (device == "stratixiv(e)") || (device == "StratixIIIGX") || (device == "STRATIXIIIGX") || (device == "stratixiiigx") || (device == "Stratix IV (GT/GX/E)") || (device == "STRATIX IV (GT/GX/E)") || (device == "stratix iv (gt/gx/e)") || (device == "Stratix IV (GT/E/GX)") || (device == "STRATIX IV (GT/E/GX)") || (device == "stratix iv (gt/e/gx)") || (device == "Stratix IV (E/GT/GX)") || (device == "STRATIX IV (E/GT/GX)") || (device == "stratix iv (e/gt/gx)") || (device == "Stratix IV (E/GX/GT)") || (device == "STRATIX IV (E/GX/GT)") || (device == "stratix iv (e/gx/gt)") || (device == "StratixIV(GT/GX/E)") || (device == "STRATIXIV(GT/GX/E)") || (device == "stratixiv(gt/gx/e)") || (device == "StratixIV(GT/E/GX)") || (device == "STRATIXIV(GT/E/GX)") || (device == "stratixiv(gt/e/gx)") || (device == "StratixIV(E/GX/GT)") || (device == "STRATIXIV(E/GX/GT)") || (device == "stratixiv(e/gx/gt)") || (device == "StratixIV(E/GT/GX)") || (device == "STRATIXIV(E/GT/GX)") || (device == "stratixiv(e/gt/gx)") || (device == "Stratix IV (GX/E)") || (device == "STRATIX IV (GX/E)") || (device == "stratix iv (gx/e)") || (device == "StratixIV(GX/E)") || (device == "STRATIXIV(GX/E)") || (device == "stratixiv(gx/e)")) || ((device == "Stratix V") || (device == "STRATIX V") || (device == "stratix v") || (device == "StratixV") || (device == "STRATIXV") || (device == "stratixv") || (device == "Stratix V (GS)") || (device == "STRATIX V (GS)") || (device == "stratix v (gs)") || (device == "StratixV(GS)") || (device == "STRATIXV(GS)") || (device == "stratixv(gs)") || (device == "Stratix V (GT)") || (device == "STRATIX V (GT)") || (device == "stratix v (gt)") || (device == "StratixV(GT)") || (device == "STRATIXV(GT)") || (device == "stratixv(gt)") || (device == "Stratix V (GX)") || (device == "STRATIX V (GX)") || (device == "stratix v (gx)") || (device == "StratixV(GX)") || (device == "STRATIXV(GX)") || (device == "stratixv(gx)") || (device == "Stratix V (GS/GX)") || (device == "STRATIX V (GS/GX)") || (device == "stratix v (gs/gx)") || (device == "StratixV(GS/GX)") || (device == "STRATIXV(GS/GX)") || (device == "stratixv(gs/gx)") || (device == "Stratix V (GS/GT)") || (device == "STRATIX V (GS/GT)") || (device == "stratix v (gs/gt)") || (device == "StratixV(GS/GT)") || (device == "STRATIXV(GS/GT)") || (device == "stratixv(gs/gt)") || (device == "Stratix V (GT/GX)") || (device == "STRATIX V (GT/GX)") || (device == "stratix v (gt/gx)") || (device == "StratixV(GT/GX)") || (device == "STRATIXV(GT/GX)") || (device == "stratixv(gt/gx)") || (device == "Stratix V (GX/GS)") || (device == "STRATIX V (GX/GS)") || (device == "stratix v (gx/gs)") || (device == "StratixV(GX/GS)") || (device == "STRATIXV(GX/GS)") || (device == "stratixv(gx/gs)") || (device == "Stratix V (GT/GS)") || (device == "STRATIX V (GT/GS)") || (device == "stratix v (gt/gs)") || (device == "StratixV(GT/GS)") || (device == "STRATIXV(GT/GS)") || (device == "stratixv(gt/gs)") || (device == "Stratix V (GX/GT)") || (device == "STRATIX V (GX/GT)") || (device == "stratix v (gx/gt)") || (device == "StratixV(GX/GT)") || (device == "STRATIXV(GX/GT)") || (device == "stratixv(gx/gt)") || (device == "Stratix V (GS/GT/GX)") || (device == "STRATIX V (GS/GT/GX)") || (device == "stratix v (gs/gt/gx)") || (device == "Stratix V (GS/GX/GT)") || (device == "STRATIX V (GS/GX/GT)") || (device == "stratix v (gs/gx/gt)") || (device == "Stratix V (GT/GS/GX)") || (device == "STRATIX V (GT/GS/GX)") || (device == "stratix v (gt/gs/gx)") || (device == "Stratix V (GT/GX/GS)") || (device == "STRATIX V (GT/GX/GS)") || (device == "stratix v (gt/gx/gs)") || (device == "Stratix V (GX/GS/GT)") || (device == "STRATIX V (GX/GS/GT)") || (device == "stratix v (gx/gs/gt)") || (device == "Stratix V (GX/GT/GS)") || (device == "STRATIX V (GX/GT/GS)") || (device == "stratix v (gx/gt/gs)") || (device == "StratixV(GS/GT/GX)") || (device == "STRATIXV(GS/GT/GX)") || (device == "stratixv(gs/gt/gx)") || (device == "StratixV(GS/GX/GT)") || (device == "STRATIXV(GS/GX/GT)") || (device == "stratixv(gs/gx/gt)") || (device == "StratixV(GT/GS/GX)") || (device == "STRATIXV(GT/GS/GX)") || (device == "stratixv(gt/gs/gx)") || (device == "StratixV(GT/GX/GS)") || (device == "STRATIXV(GT/GX/GS)") || (device == "stratixv(gt/gx/gs)") || (device == "StratixV(GX/GS/GT)") || (device == "STRATIXV(GX/GS/GT)") || (device == "stratixv(gx/gs/gt)") || (device == "StratixV(GX/GT/GS)") || (device == "STRATIXV(GX/GT/GS)") || (device == "stratixv(gx/gt/gs)") || (device == "Stratix V (GS/GT/GX/E)") || (device == "STRATIX V (GS/GT/GX/E)") || (device == "stratix v (gs/gt/gx/e)") || (device == "StratixV(GS/GT/GX/E)") || (device == "STRATIXV(GS/GT/GX/E)") || (device == "stratixv(gs/gt/gx/e)") || (device == "Stratix V (E)") || (device == "STRATIX V (E)") || (device == "stratix v (e)") || (device == "StratixV(E)") || (device == "STRATIXV(E)") || (device == "stratixv(e)")) || ((device == "Stratix") || (device == "STRATIX") || (device == "stratix") || (device == "Yeager") || (device == "YEAGER") || (device == "yeager")) || ((device == "eFPGA 28 HPM") || (device == "EFPGA 28 HPM") || (device == "efpga 28 hpm") || (device == "eFPGA28HPM") || (device == "EFPGA28HPM") || (device == "efpga28hpm") || (device == "Bedrock") || (device == "BEDROCK") || (device == "bedrock"))) is_valid = 1; else is_valid = 0; IS_VALID_FAMILY = is_valid; end endfunction // IS_VALID_FAMILY endmodule // LPM_DEVICE_FAMILIES //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_constant // // Description : Parameterized constant generator megafunction. lpm_constant // may be useful for convert a parameter into a constant. // // Limitation : n/a // // Results expected: Value specified by the argument to LPM_CVALUE. // //END_MODULE_NAME-------------------------------------------------------------- // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module lpm_constant ( result // Value specified by the argument to LPM_CVALUE. (Required) ); // GLOBAL PARAMETER DECLARATION parameter lpm_width = 1; // Width of the result[] port. (Required) parameter lpm_cvalue = 0; // Constant value to be driven out on the // result[] port. (Required) parameter lpm_strength = "UNUSED"; parameter lpm_type = "lpm_constant"; parameter lpm_hint = "UNUSED"; // OUTPUT PORT DECLARATION output [lpm_width-1:0] result; // INTERNAL REGISTERS DECLARATION reg[32:0] int_value; // INITIAL CONSTRUCT BLOCK initial begin if (lpm_width <= 0) begin $display("Value of lpm_width parameter must be greater than 0(ERROR)"); $display("Time: %0t Instance: %m", $time); $finish; end int_value = lpm_cvalue; end // CONTINOUS ASSIGNMENT assign result = int_value[lpm_width-1:0]; endmodule // lpm_constant //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_inv // // Description : Parameterized inverter megafunction. // // Limitation : n/a // // Results expected: Inverted value of input data // //END_MODULE_NAME-------------------------------------------------------------- // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module lpm_inv ( data, // Data input to the lpm_inv. (Required) result // inverted result. (Required) ); // GLOBAL PARAMETER DECLARATION parameter lpm_width = 1; // Width of the data[] and result[] ports. (Required) parameter lpm_type = "lpm_inv"; parameter lpm_hint = "UNUSED"; // INPUT PORT DECLARATION input [lpm_width-1:0] data; // OUTPUT PORT DECLARATION output [lpm_width-1:0] result; // INTERNAL REGISTERS DECLARATION reg [lpm_width-1:0] result; // INITIAL CONSTRUCT BLOCK initial begin if (lpm_width <= 0) begin $display("Value of lpm_width parameter must be greater than 0 (ERROR)"); $display("Time: %0t Instance: %m", $time); $finish; end end // ALWAYS CONSTRUCT BLOCK always @(data) result = ~data; endmodule // lpm_inv //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_and // // Description : Parameterized AND gate. This megafunction takes in data inputs // for a number of AND gates. // // Limitation : n/a // // Results expected: Each result[] bit is the result of each AND gate. // //END_MODULE_NAME-------------------------------------------------------------- // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module lpm_and ( data, // Data input to the AND gate. (Required) result // Result of the AND operators. (Required) ); // GLOBAL PARAMETER DECLARATION // Width of the data[][] and result[] ports. Number of AND gates. (Required) parameter lpm_width = 1; // Number of inputs to each AND gate. Number of input buses. (Required) parameter lpm_size = 1; parameter lpm_type = "lpm_and"; parameter lpm_hint = "UNUSED"; // INPUT PORT DECLARATION input [(lpm_size * lpm_width)-1:0] data; // OUTPUT PORT DECLARATION output [lpm_width-1:0] result; // INTERNAL REGISTER/SIGNAL DECLARATION reg [lpm_width-1:0] result_tmp; // LOCAL INTEGER DECLARATION integer i; integer j; integer k; // INITIAL CONSTRUCT BLOCK initial begin if (lpm_width <= 0) begin $display("Value of lpm_width parameter must be greater than 0(ERROR)"); $display("Time: %0t Instance: %m", $time); $finish; end if (lpm_size <= 0) begin $display("Value of lpm_size parameter must be greater than 0(ERROR)"); $display("Time: %0t Instance: %m", $time); $finish; end end // ALWAYS CONSTRUCT BLOCK always @(data) begin for (i=0; i 1) pipe_ptr <= (pipe_ptr + 1) % lpm_pipeline; end end // CONTINOUS ASSIGNMENT assign result = (lpm_pipeline > 0) ? result_pipe[pipe_ptr] : tmp_result; endmodule // lpm_mux // END OF MODULE //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_decode // // Description : Parameterized decoder megafunction. // // Limitation : n/a // // Results expected: Decoded output. // //END_MODULE_NAME-------------------------------------------------------------- // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module lpm_decode ( data, // Data input. Treated as an unsigned binary encoded number. (Required) enable, // Enable. All outputs low when not active. clock, // Clock for pipelined usage. aclr, // Asynchronous clear for pipelined usage. clken, // Clock enable for pipelined usage. eq // Decoded output. (Required) ); // GLOBAL PARAMETER DECLARATION parameter lpm_width = 1; // Width of the data[] port, or the // input value to be decoded. (Required) parameter lpm_decodes = 1 << lpm_width; // Number of explicit decoder outputs. (Required) parameter lpm_pipeline = 0; // Number of Clock cycles of latency parameter lpm_type = "lpm_decode"; parameter lpm_hint = "UNUSED"; // INPUT PORT DECLARATION input [lpm_width-1:0] data; input enable; input clock; input aclr; input clken; // OUTPUT PORT DECLARATION output [lpm_decodes-1:0] eq; // INTERNAL REGISTER/SIGNAL DECLARATION reg [lpm_decodes-1:0] eq_pipe [(lpm_pipeline+1):0]; reg [lpm_decodes-1:0] tmp_eq; // LOCAL INTEGER DECLARATION integer i; integer pipe_ptr; // INTERNAL TRI DECLARATION tri1 enable; tri0 clock; tri0 aclr; tri1 clken; wire i_clock; wire i_clken; wire i_aclr; wire i_enable; buf (i_clock, clock); buf (i_clken, clken); buf (i_aclr, aclr); buf (i_enable, enable); // INITIAL CONSTRUCT BLOCK initial begin if (lpm_width <= 0) begin $display("Value of lpm_width parameter must be greater than 0 (ERROR)"); $display("Time: %0t Instance: %m", $time); $finish; end if (lpm_decodes <= 0) begin $display("Value of lpm_decodes parameter must be greater than 0 (ERROR)"); $display("Time: %0t Instance: %m", $time); $finish; end if (lpm_decodes > (1 << lpm_width)) begin $display("Value of lpm_decodes parameter must be less or equal to 2^lpm_width (ERROR)"); $display("Time: %0t Instance: %m", $time); $finish; end if (lpm_pipeline < 0) begin $display("Value of lpm_pipeline parameter must be greater or equal to 0 (ERROR)"); $display("Time: %0t Instance: %m", $time); $finish; end pipe_ptr = 0; end // ALWAYS CONSTRUCT BLOCK always @(data or i_enable) begin tmp_eq = {lpm_decodes{1'b0}}; if (i_enable) tmp_eq[data] = 1'b1; end always @(posedge i_clock or posedge i_aclr) begin if (i_aclr) begin for (i = 0; i <= lpm_pipeline; i = i + 1) eq_pipe[i] <= {lpm_decodes{1'b0}}; pipe_ptr <= 0; end else if (clken == 1'b1) begin eq_pipe[pipe_ptr] <= tmp_eq; if (lpm_pipeline > 1) pipe_ptr <= (pipe_ptr + 1) % lpm_pipeline; end end assign eq = (lpm_pipeline > 0) ? eq_pipe[pipe_ptr] : tmp_eq; endmodule // lpm_decode // END OF MODULE //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_clshift // // Description : Parameterized combinatorial logic shifter or barrel shifter // megafunction. // // Limitation : n/a // // Results expected: Return the shifted data and underflow/overflow status bit. // //END_MODULE_NAME-------------------------------------------------------------- // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module lpm_clshift ( data, // Data to be shifted. (Required) distance, // Number of positions to shift data[] in the direction specified // by the direction port. (Required) direction, // Direction of shift. Low = left (toward the MSB), // high = right (toward the LSB). clock, // Clock for pipelined usage. aclr, // Asynchronous clear for pipelined usage. clken, // Clock enable for pipelined usage. result, // Shifted data. (Required) underflow, // Logical or arithmetic underflow. overflow // Logical or arithmetic overflow. ); // GLOBAL PARAMETER DECLARATION parameter lpm_width = 1; // Width of the data[] and result[] ports. Must be // greater than 0 (Required) parameter lpm_widthdist = 1; // Width of the distance[] input port. (Required) parameter lpm_shifttype = "LOGICAL"; // Type of shifting operation to be performed. parameter lpm_pipeline = 0; // Number of Clock cycles of latency parameter lpm_type = "lpm_clshift"; parameter lpm_hint = "UNUSED"; // INPUT PORT DECLARATION input [lpm_width-1:0] data; input [lpm_widthdist-1:0] distance; input direction; input clock; input aclr; input clken; // OUTPUT PORT DECLARATION output [lpm_width-1:0] result; output underflow; output overflow; // INTERNAL REGISTERS DECLARATION reg [lpm_width-1:0] ONES; reg [lpm_width-1:0] ZEROS; reg [lpm_width-1:0] tmp_result; reg tmp_underflow; reg tmp_overflow; reg [lpm_width-1:0] result_pipe [(lpm_pipeline+1):0]; reg [(lpm_pipeline+1):0] overflow_pipe; reg [(lpm_pipeline+1):0] underflow_pipe; // LOCAL INTEGER DECLARATION integer i; integer i1; integer pipe_ptr; // INTERNAL TRI DECLARATION tri0 direction; tri0 clock; tri0 aclr; tri1 clken; wire i_direction; wire i_clock; wire i_clken; wire i_aclr; buf (i_direction, direction); buf (i_clock, clock); buf (i_clken, clken); buf (i_aclr, aclr); // FUNCTON DECLARATION // Perform logival shift operation function [lpm_width+1:0] LogicShift; input [lpm_width-1:0] data; input [lpm_widthdist-1:0] shift_num; input direction; reg [lpm_width-1:0] tmp_buf; reg underflow; reg overflow; begin tmp_buf = data; overflow = 1'b0; underflow = 1'b0; if ((direction) && (shift_num > 0)) // shift right begin tmp_buf = data >> shift_num; if ((data != ZEROS) && ((shift_num >= lpm_width) || (tmp_buf == ZEROS))) underflow = 1'b1; end else if (shift_num > 0) // shift left begin tmp_buf = data << shift_num; if ((data != ZEROS) && ((shift_num >= lpm_width) || ((data >> (lpm_width-shift_num)) != ZEROS))) overflow = 1'b1; end LogicShift = {overflow,underflow,tmp_buf[lpm_width-1:0]}; end endfunction // LogicShift // Perform Arithmetic shift operation function [lpm_width+1:0] ArithShift; input [lpm_width-1:0] data; input [lpm_widthdist-1:0] shift_num; input direction; reg [lpm_width-1:0] tmp_buf; reg underflow; reg overflow; integer i; integer i1; begin tmp_buf = data; overflow = 1'b0; underflow = 1'b0; if (shift_num < lpm_width) begin if ((direction) && (shift_num > 0)) // shift right begin if (data[lpm_width-1] == 1'b0) // positive number begin tmp_buf = data >> shift_num; if ((data != ZEROS) && ((shift_num >= lpm_width) || (tmp_buf == ZEROS))) underflow = 1'b1; end else // negative number begin tmp_buf = (data >> shift_num) | (ONES << (lpm_width - shift_num)); if ((data != ONES) && ((shift_num >= lpm_width-1) || (tmp_buf == ONES))) underflow = 1'b1; end end else if (shift_num > 0) // shift left begin tmp_buf = data << shift_num; for (i=lpm_width-1; i >= lpm_width-shift_num; i=i-1) begin if(data[i-1] != data[lpm_width-1]) overflow = 1'b1; end end end else // shift_num >= lpm_width begin if (direction) begin for (i=0; i < lpm_width; i=i+1) tmp_buf[i] = data[lpm_width-1]; underflow = 1'b1; end else begin tmp_buf = {lpm_width{1'b0}}; if (data != ZEROS) begin overflow = 1'b1; end end end ArithShift = {overflow,underflow,tmp_buf[lpm_width-1:0]}; end endfunction // ArithShift // Perform rotate shift operation function [lpm_width+1:0] RotateShift; input [lpm_width-1:0] data; input [lpm_widthdist-1:0] shift_num; input direction; reg [lpm_width-1:0] tmp_buf; begin tmp_buf = data; if ((direction) && (shift_num > 0)) // shift right tmp_buf = (data >> shift_num) | (data << (lpm_width - shift_num)); else if (shift_num > 0) // shift left tmp_buf = (data << shift_num) | (data >> (lpm_width - shift_num)); RotateShift = {2'bx, tmp_buf[lpm_width-1:0]}; end endfunction // RotateShift // INITIAL CONSTRUCT BLOCK initial begin if ((lpm_shifttype != "LOGICAL") && (lpm_shifttype != "ARITHMETIC") && (lpm_shifttype != "ROTATE") && (lpm_shifttype != "UNUSED")) // non-LPM 220 standard begin $display("Error! LPM_SHIFTTYPE value must be \"LOGICAL\", \"ARITHMETIC\", or \"ROTATE\"."); $display("Time: %0t Instance: %m", $time); end if (lpm_width <= 0) begin $display("Value of lpm_width parameter must be greater than 0(ERROR)"); $display("Time: %0t Instance: %m", $time); $finish; end if (lpm_widthdist <= 0) begin $display("Value of lpm_widthdist parameter must be greater than 0(ERROR)"); $display("Time: %0t Instance: %m", $time); $finish; end for (i=0; i < lpm_width; i=i+1) begin ONES[i] = 1'b1; ZEROS[i] = 1'b0; end for (i = 0; i <= lpm_pipeline; i = i + 1) begin result_pipe[i] = ZEROS; overflow_pipe[i] = 1'b0; underflow_pipe[i] = 1'b0; end tmp_result = ZEROS; tmp_underflow = 1'b0; tmp_overflow = 1'b0; pipe_ptr = 0; end // ALWAYS CONSTRUCT BLOCK always @(data or i_direction or distance) begin // verilator lint_off SIDEEFFECT if ((lpm_shifttype == "LOGICAL") || (lpm_shifttype == "UNUSED")) {tmp_overflow, tmp_underflow, tmp_result} = LogicShift(data, distance, i_direction); else if (lpm_shifttype == "ARITHMETIC") {tmp_overflow, tmp_underflow, tmp_result} = ArithShift(data, distance, i_direction); else if (lpm_shifttype == "ROTATE") {tmp_overflow, tmp_underflow, tmp_result} = RotateShift(data, distance, i_direction); // verilator lint_on SIDEEFFECT end always @(posedge i_clock or posedge i_aclr) begin if (i_aclr) begin for (i1 = 0; i1 <= lpm_pipeline; i1 = i1 + 1) begin result_pipe[i1] <= {lpm_width{1'b0}}; overflow_pipe[i1] <= 1'b0; underflow_pipe[i1] <= 1'b0; end pipe_ptr <= 0; end else if (i_clken == 1'b1) begin result_pipe[pipe_ptr] <= tmp_result; overflow_pipe[pipe_ptr] <= tmp_overflow; underflow_pipe[pipe_ptr] <= tmp_underflow; if (lpm_pipeline > 1) pipe_ptr <= (pipe_ptr + 1) % lpm_pipeline; end end assign result = (lpm_pipeline > 0) ? result_pipe[pipe_ptr] : tmp_result; assign overflow = (lpm_pipeline > 0) ? overflow_pipe[pipe_ptr] : tmp_overflow; assign underflow = (lpm_pipeline > 0) ? underflow_pipe[pipe_ptr] : tmp_underflow; endmodule // lpm_clshift //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_add_sub // // Description : Parameterized adder/subtractor megafunction. // // Limitation : n/a // // Results expected: If performs as adder, the result will be dataa[]+datab[]+cin. // If performs as subtractor, the result will be dataa[]-datab[]+cin-1. // Also returns carry out bit and overflow status bit. // //END_MODULE_NAME-------------------------------------------------------------- // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module lpm_add_sub ( dataa, // Augend/Minuend datab, // Addend/Subtrahend cin, // Carry-in to the low-order bit. add_sub, // If the signal is high, the operation = dataa[]+datab[]+cin. // If the signal is low, the operation = dataa[]-datab[]+cin-1. clock, // Clock for pipelined usage. aclr, // Asynchronous clear for pipelined usage. clken, // Clock enable for pipelined usage. result, // dataa[]+datab[]+cin or dataa[]-datab[]+cin-1 cout, // Carry-out (borrow-in) of the MSB. overflow // Result exceeds available precision. ); // GLOBAL PARAMETER DECLARATION parameter lpm_width = 1; // Width of the dataa[],datab[], and result[] ports. parameter lpm_representation = "SIGNED"; // Type of addition performed parameter lpm_direction = "UNUSED"; // Specify the operation of the lpm_add_sub function parameter lpm_pipeline = 0; // Number of Clock cycles of latency parameter lpm_type = "lpm_add_sub"; parameter lpm_hint = "UNUSED"; // INPUT PORT DECLARATION input [lpm_width-1:0] dataa; input [lpm_width-1:0] datab; input cin; input add_sub; input clock; input aclr; input clken; // OUTPUT PORT DECLARATION output [lpm_width-1:0] result; output cout; output overflow; // INTERNAL REGISTER/SIGNAL DECLARATION reg [lpm_width-1:0] result_pipe [(lpm_pipeline+1):0]; reg [(lpm_pipeline+1):0] cout_pipe; reg [(lpm_pipeline+1):0] overflow_pipe; reg tmp_cout; reg tmp_overflow; reg [lpm_width-1:0] tmp_result; reg i_cin; // LOCAL INTEGER DECLARATION integer borrow; integer i; integer pipe_ptr; // INTERNAL TRI DECLARATION tri1 i_add_sub; tri0 i_aclr; tri1 i_clken; tri0 i_clock; // INITIAL CONSTRUCT BLOCK initial begin // check if lpm_width < 0 if (lpm_width <= 0) begin $display("Error! LPM_WIDTH must be greater than 0.\n"); $display("Time: %0t Instance: %m", $time); $finish; end if ((lpm_direction != "ADD") && (lpm_direction != "SUB") && (lpm_direction != "UNUSED") && // non-LPM 220 standard (lpm_direction != "DEFAULT")) // non-LPM 220 standard begin $display("Error! LPM_DIRECTION value must be \"ADD\" or \"SUB\"."); $display("Time: %0t Instance: %m", $time); $finish; end if ((lpm_representation != "SIGNED") && (lpm_representation != "UNSIGNED")) begin $display("Error! LPM_REPRESENTATION value must be \"SIGNED\" or \"UNSIGNED\"."); $display("Time: %0t Instance: %m", $time); $finish; end if (lpm_pipeline < 0) begin $display("Error! LPM_PIPELINE must be greater than or equal to 0.\n"); $display("Time: %0t Instance: %m", $time); $finish; end for (i = 0; i <= (lpm_pipeline+1); i = i + 1) begin result_pipe[i] = 'b0; cout_pipe[i] = 1'b0; overflow_pipe[i] = 1'b0; end pipe_ptr = 0; end // ALWAYS CONSTRUCT BLOCK always @(cin or dataa or datab or i_add_sub) begin i_cin = 1'b0; borrow = 1'b0; // cout is the same for both signed and unsign representation. if ((lpm_direction == "ADD") || ((i_add_sub == 1) && ((lpm_direction == "UNUSED") || (lpm_direction == "DEFAULT")) )) begin i_cin = (cin === 1'bz) ? 0 : cin; {tmp_cout, tmp_result} = dataa + datab + i_cin; tmp_overflow = tmp_cout; end else if ((lpm_direction == "SUB") || ((i_add_sub == 0) && ((lpm_direction == "UNUSED") || (lpm_direction == "DEFAULT")) )) begin i_cin = (cin === 1'bz) ? 1 : cin; borrow = (~i_cin) ? 1 : 0; {tmp_overflow, tmp_result} = dataa - datab - borrow; tmp_cout = (dataa >= (datab+borrow))?1:0; end if (lpm_representation == "SIGNED") begin // perform the addtion or subtraction operation if ((lpm_direction == "ADD") || ((i_add_sub == 1) && ((lpm_direction == "UNUSED") || (lpm_direction == "DEFAULT")) )) begin tmp_result = dataa + datab + i_cin; tmp_overflow = ((dataa[lpm_width-1] == datab[lpm_width-1]) && (dataa[lpm_width-1] != tmp_result[lpm_width-1])) ? 1 : 0; end else if ((lpm_direction == "SUB") || ((i_add_sub == 0) && ((lpm_direction == "UNUSED") || (lpm_direction == "DEFAULT")) )) begin tmp_result = dataa - datab - borrow; tmp_overflow = ((dataa[lpm_width-1] != datab[lpm_width-1]) && (dataa[lpm_width-1] != tmp_result[lpm_width-1])) ? 1 : 0; end end end always @(posedge i_clock or posedge i_aclr) begin if (i_aclr) begin for (i = 0; i <= (lpm_pipeline+1); i = i + 1) begin result_pipe[i] <= {lpm_width{1'b0}}; cout_pipe[i] <= 1'b0; overflow_pipe[i] <= 1'b0; end pipe_ptr <= 0; end else if (i_clken == 1) begin result_pipe[pipe_ptr] <= tmp_result; cout_pipe[pipe_ptr] <= tmp_cout; overflow_pipe[pipe_ptr] <= tmp_overflow; if (lpm_pipeline > 1) pipe_ptr <= (pipe_ptr + 1) % lpm_pipeline; end end // CONTINOUS ASSIGNMENT assign result = (lpm_pipeline > 0) ? result_pipe[pipe_ptr] : tmp_result; assign cout = (lpm_pipeline > 0) ? cout_pipe[pipe_ptr] : tmp_cout; assign overflow = (lpm_pipeline > 0) ? overflow_pipe[pipe_ptr] : tmp_overflow; assign i_clock = clock; assign i_aclr = aclr; assign i_clken = clken; assign i_add_sub = add_sub; endmodule // lpm_add_sub // END OF MODULE //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_compare // // Description : Parameterized comparator megafunction. The comparator will // compare between data[] and datab[] and return the status of // comparation for the following operation. // 1) dataa[] < datab[]. // 2) dataa[] == datab[]. // 3) dataa[] > datab[]. // 4) dataa[] >= datab[]. // 5) dataa[] != datab[]. // 6) dataa[] <= datab[]. // // Limitation : n/a // // Results expected: Return status bits of the comparision between dataa[] and // datab[]. // //END_MODULE_NAME-------------------------------------------------------------- // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module lpm_compare ( dataa, // Value to be compared to datab[]. (Required) datab, // Value to be compared to dataa[]. (Required) clock, // Clock for pipelined usage. aclr, // Asynchronous clear for pipelined usage. clken, // Clock enable for pipelined usage. // One of the following ports must be present. alb, // High (1) if dataa[] < datab[]. aeb, // High (1) if dataa[] == datab[]. agb, // High (1) if dataa[] > datab[]. aleb, // High (1) if dataa[] <= datab[]. aneb, // High (1) if dataa[] != datab[]. ageb // High (1) if dataa[] >= datab[]. ); // GLOBAL PARAMETER DECLARATION parameter lpm_width = 1; // Width of the dataa[] and datab[] ports. (Required) parameter lpm_representation = "UNSIGNED"; // Type of comparison performed: // "SIGNED", "UNSIGNED" parameter lpm_pipeline = 0; // Specifies the number of Clock cycles of latency // associated with the alb, aeb, agb, ageb, aleb, // or aneb output. parameter lpm_type = "lpm_compare"; parameter lpm_hint = "UNUSED"; // INPUT PORT DECLARATION input [lpm_width-1:0] dataa; input [lpm_width-1:0] datab; input clock; input aclr; input clken; // OUTPUT PORT DECLARATION output alb; output aeb; output agb; output aleb; output aneb; output ageb; // INTERNAL REGISTERS DECLARATION reg [lpm_pipeline+1:0] alb_pipe; reg [lpm_pipeline+1:0] aeb_pipe; reg [lpm_pipeline+1:0] agb_pipe; reg [lpm_pipeline+1:0] aleb_pipe; reg [lpm_pipeline+1:0] aneb_pipe; reg [lpm_pipeline+1:0] ageb_pipe; reg tmp_alb; reg tmp_aeb; reg tmp_agb; reg tmp_aleb; reg tmp_aneb; reg tmp_ageb; // LOCAL INTEGER DECLARATION integer i; integer pipe_ptr; // INTERNAL TRI DECLARATION tri0 aclr; tri0 clock; tri1 clken; wire i_aclr; wire i_clock; wire i_clken; buf (i_aclr, aclr); buf (i_clock, clock); buf (i_clken, clken); // INITIAL CONSTRUCT BLOCK initial begin if ((lpm_representation != "SIGNED") && (lpm_representation != "UNSIGNED")) begin $display("Error! LPM_REPRESENTATION value must be \"SIGNED\" or \"UNSIGNED\"."); $display("Time: %0t Instance: %m", $time); $finish; end if (lpm_width <= 0) begin $display("Value of lpm_width parameter must be greater than 0(ERROR)"); $display("Time: %0t Instance: %m", $time); $finish; end pipe_ptr = 0; end // ALWAYS CONSTRUCT BLOCK // get the status of comparison always @(dataa or datab) begin tmp_aeb = (dataa == datab); tmp_aneb = (dataa != datab); if ((lpm_representation == "SIGNED") && ((dataa[lpm_width-1] ^ datab[lpm_width-1]) == 1)) begin // create latency tmp_alb = (dataa > datab); tmp_agb = (dataa < datab); tmp_aleb = (dataa >= datab); tmp_ageb = (dataa <= datab); end else begin // create latency tmp_alb = (dataa < datab); tmp_agb = (dataa > datab); tmp_aleb = (dataa <= datab); tmp_ageb = (dataa >= datab); end end // pipelining process always @(posedge i_clock or posedge i_aclr) begin if (i_aclr) // reset all variables begin for (i = 0; i <= (lpm_pipeline + 1); i = i + 1) begin aeb_pipe[i] <= 1'b0; agb_pipe[i] <= 1'b0; alb_pipe[i] <= 1'b0; aleb_pipe[i] <= 1'b0; aneb_pipe[i] <= 1'b0; ageb_pipe[i] <= 1'b0; end pipe_ptr <= 0; end else if (i_clken == 1) begin alb_pipe[pipe_ptr] <= tmp_alb; aeb_pipe[pipe_ptr] <= tmp_aeb; agb_pipe[pipe_ptr] <= tmp_agb; aleb_pipe[pipe_ptr] <= tmp_aleb; aneb_pipe[pipe_ptr] <= tmp_aneb; ageb_pipe[pipe_ptr] <= tmp_ageb; if (lpm_pipeline > 1) pipe_ptr <= (pipe_ptr + 1) % lpm_pipeline; end end // CONTINOUS ASSIGNMENT assign alb = (lpm_pipeline > 0) ? alb_pipe[pipe_ptr] : tmp_alb; assign aeb = (lpm_pipeline > 0) ? aeb_pipe[pipe_ptr] : tmp_aeb; assign agb = (lpm_pipeline > 0) ? agb_pipe[pipe_ptr] : tmp_agb; assign aleb = (lpm_pipeline > 0) ? aleb_pipe[pipe_ptr] : tmp_aleb; assign aneb = (lpm_pipeline > 0) ? aneb_pipe[pipe_ptr] : tmp_aneb; assign ageb = (lpm_pipeline > 0) ? ageb_pipe[pipe_ptr] : tmp_ageb; endmodule // lpm_compare //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_mult // // Description : Parameterized multiplier megafunction. // // Limitation : n/a // // Results expected: dataa[] * datab[] + sum[]. // //END_MODULE_NAME-------------------------------------------------------------- // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module lpm_mult ( dataa, // Multiplicand. (Required) datab, // Multiplier. (Required) sum, // Partial sum. aclr, // Asynchronous clear for pipelined usage. sclr, // Synchronous clear for pipelined usage. clock, // Clock for pipelined usage. clken, // Clock enable for pipelined usage. result // result = dataa[] * datab[] + sum. The product LSB is aligned with the sum LSB. ); // GLOBAL PARAMETER DECLARATION parameter lpm_widtha = 1; // Width of the dataa[] port. (Required) parameter lpm_widthb = 1; // Width of the datab[] port. (Required) parameter lpm_widthp = 1; // Width of the result[] port. (Required) parameter lpm_widths = 1; // Width of the sum[] port. (Required) parameter lpm_representation = "UNSIGNED"; // Type of multiplication performed parameter lpm_pipeline = 0; // Number of clock cycles of latency parameter lpm_type = "lpm_mult"; parameter lpm_hint = "UNUSED"; // INPUT PORT DECLARATION input [lpm_widtha-1:0] dataa; input [lpm_widthb-1:0] datab; input [lpm_widths-1:0] sum; input aclr; input sclr; input clock; input clken; // OUTPUT PORT DECLARATION output [lpm_widthp-1:0] result; // INTERNAL REGISTER/SIGNAL DECLARATION reg [lpm_widthp-1:0] result_pipe [lpm_pipeline+1:0]; reg [lpm_widthp-1:0] i_prod; reg [lpm_widthp-1:0] t_p; reg [lpm_widths-1:0] i_prod_s; reg [lpm_widths-1:0] t_s; reg [lpm_widtha+lpm_widthb-1:0] i_prod_ab; reg [lpm_widtha-1:0] t_a; reg [lpm_widthb-1:0] t_b; reg sign_ab; reg sign_s; reg [8*5:1] input_a_is_constant; reg [8*5:1] input_b_is_constant; reg [8*lpm_widtha:1] input_a_fixed_value; reg [8*lpm_widthb:1] input_b_fixed_value; reg [lpm_widtha-1:0] dataa_fixed; reg [lpm_widthb-1:0] datab_fixed; // LOCAL INTEGER DECLARATION integer i; integer pipe_ptr; // INTERNAL WIRE DECLARATION wire [lpm_widtha-1:0] dataa_wire; wire [lpm_widthb-1:0] datab_wire; // INTERNAL TRI DECLARATION tri0 aclr; tri0 sclr; tri0 clock; tri1 clken; wire i_aclr; wire i_sclr; wire i_clock; wire i_clken; buf (i_aclr, aclr); buf (i_sclr, sclr); buf (i_clock, clock); buf (i_clken, clken); // COMPONENT INSTANTIATIONS LPM_HINT_EVALUATION eva(); // FUNCTION DECLARATION // convert string to binary bits. function integer str2bin; input [8*256:1] str; input str_width; reg [8*256:1] reg_str; reg [255:0] bin; reg [8:1] tmp; integer m; integer str_width; begin reg_str = str; for (m=0; m < str_width; m=m+1) begin tmp = reg_str[8:1]; reg_str = reg_str >> 8; case (tmp) "0" : bin[m] = 1'b0; "1" : bin[m] = 1'b1; default: bin[m] = 1'bx; endcase end str2bin = bin; end endfunction // INITIAL CONSTRUCT BLOCK initial begin // check if lpm_widtha > 0 if (lpm_widtha <= 0) begin $display("Error! lpm_widtha must be greater than 0.\n"); $display("Time: %0t Instance: %m", $time); $finish; end // check if lpm_widthb > 0 if (lpm_widthb <= 0) begin $display("Error! lpm_widthb must be greater than 0.\n"); $display("Time: %0t Instance: %m", $time); $finish; end // check if lpm_widthp > 0 if (lpm_widthp <= 0) begin $display("Error! lpm_widthp must be greater than 0.\n"); $display("Time: %0t Instance: %m", $time); $finish; end // check if lpm_widthp > 0 if (lpm_widths <= 0) begin $display("Error! lpm_widths must be greater than 0.\n"); $display("Time: %0t Instance: %m", $time); $finish; end // check for valid lpm_rep value if ((lpm_representation != "SIGNED") && (lpm_representation != "UNSIGNED")) begin $display("Error! lpm_representation value must be \"SIGNED\" or \"UNSIGNED\".", $time); $display("Time: %0t Instance: %m", $time); $finish; end input_a_is_constant = eva.GET_PARAMETER_VALUE(lpm_hint, "INPUT_A_IS_CONSTANT"); if (input_a_is_constant == "FIXED") begin input_a_fixed_value = eva.GET_PARAMETER_VALUE(lpm_hint, "INPUT_A_FIXED_VALUE"); dataa_fixed = str2bin(input_a_fixed_value, lpm_widtha); end input_b_is_constant = eva.GET_PARAMETER_VALUE(lpm_hint, "INPUT_B_IS_CONSTANT"); if (input_b_is_constant == "FIXED") begin input_b_fixed_value = eva.GET_PARAMETER_VALUE(lpm_hint, "INPUT_B_FIXED_VALUE"); datab_fixed = str2bin(input_b_fixed_value, lpm_widthb); end pipe_ptr = 0; end // ALWAYS CONSTRUCT BLOCK always @(dataa_wire or datab_wire or sum) begin t_a = dataa_wire; t_b = datab_wire; t_s = sum; sign_ab = 1'b0; sign_s = 1'b0; // if inputs are sign number if (lpm_representation == "SIGNED") begin sign_ab = dataa_wire[lpm_widtha-1] ^ datab_wire[lpm_widthb-1]; sign_s = sum[lpm_widths-1]; // if negative number, represent them as 2 compliment number. if (dataa_wire[lpm_widtha-1] == 1) t_a = (~dataa_wire) + 1; if (datab_wire[lpm_widthb-1] == 1) t_b = (~datab_wire) + 1; if (sum[lpm_widths-1] == 1) t_s = (~sum) + 1; end // if sum port is not used if (sum === {lpm_widths{1'bz}}) begin t_s = {lpm_widths{1'b0}}; sign_s = 1'b0; end if (sign_ab == sign_s) begin i_prod = (t_a * t_b) + t_s; i_prod_s = (t_a * t_b) + t_s; i_prod_ab = (t_a * t_b) + t_s; end else begin i_prod = (t_a * t_b) - t_s; i_prod_s = (t_a * t_b) - t_s; i_prod_ab = (t_a * t_b) - t_s; end // if dataa[] * datab[] produces negative number, compliment the result if (sign_ab) begin i_prod = (~i_prod) + 1; i_prod_s = (~i_prod_s) + 1; i_prod_ab = (~i_prod_ab) + 1; end if ((lpm_widthp < lpm_widths) || (lpm_widthp < (lpm_widtha+lpm_widthb))) for (i = 0; i < lpm_widthp; i = i + 1) i_prod[lpm_widthp-1-i] = (lpm_widths > lpm_widtha+lpm_widthb) ? i_prod_s[lpm_widths-1-i] : i_prod_ab[lpm_widtha+lpm_widthb-1-i]; end always @(posedge i_clock or posedge i_aclr) begin if (i_aclr) // clear the pipeline for result to 0 begin for (i = 0; i <= (lpm_pipeline + 1); i = i + 1) result_pipe[i] <= {lpm_widthp{1'b0}}; pipe_ptr <= 0; end else if (i_clken == 1) begin if(i_sclr) begin for (i = 0; i <= (lpm_pipeline + 1); i = i + 1) result_pipe[i] <= {lpm_widthp{1'b0}}; pipe_ptr <= 0; end else begin result_pipe[pipe_ptr] <= i_prod; if (lpm_pipeline > 1) pipe_ptr <= (pipe_ptr + 1) % lpm_pipeline; end end end // CONTINOUS ASSIGNMENT assign dataa_wire = (input_a_is_constant == "FIXED") ? dataa_fixed : dataa; assign datab_wire = (input_b_is_constant == "FIXED") ? datab_fixed : datab; assign result = (lpm_pipeline > 0) ? result_pipe[pipe_ptr] : i_prod; endmodule // lpm_mult // END OF MODULE //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_divide // // Description : Parameterized divider megafunction. This function performs a // divide operation such that denom * quotient + remain = numer // The function allows for all combinations of signed(two's // complement) and unsigned inputs. If any of the inputs is // signed, the output is signed. Otherwise the output is unsigned. // The function also allows the remainder to be specified as // always positive (in which case remain >= 0); otherwise remain // is zero or the same sign as the numerator // (this parameter is ignored in the case of purely unsigned // division). Finally the function is also pipelinable. // // Limitation : n/a // // Results expected: Return quotient and remainder. // //END_MODULE_NAME-------------------------------------------------------------- // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module lpm_divide ( numer, // The numerator (Required) denom, // The denominator (Required) clock, // Clock input for pipelined usage aclr, // Asynchronous clear signal clken, // Clock enable for pipelined usage. quotient, // Quotient (Required) remain // Remainder (Required) ); // GLOBAL PARAMETER DECLARATION parameter lpm_widthn = 1; // Width of the numer[] and quotient[] port. (Required) parameter lpm_widthd = 1; // Width of the denom[] and remain[] port. (Required) parameter lpm_nrepresentation = "UNSIGNED"; // The representation of numer parameter lpm_drepresentation = "UNSIGNED"; // The representation of denom parameter lpm_pipeline = 0; // Number of Clock cycles of latency parameter lpm_type = "lpm_divide"; parameter lpm_hint = "LPM_REMAINDERPOSITIVE=TRUE"; // INPUT PORT DECLARATION input [lpm_widthn-1:0] numer; input [lpm_widthd-1:0] denom; input clock; input aclr; input clken; // OUTPUT PORT DECLARATION output [lpm_widthn-1:0] quotient; output [lpm_widthd-1:0] remain; // INTERNAL REGISTER/SIGNAL DECLARATION reg [lpm_widthn-1:0] quotient_pipe [lpm_pipeline+1:0]; reg [lpm_widthd-1:0] remain_pipe [lpm_pipeline+1:0]; reg [lpm_widthn-1:0] tmp_quotient; reg [lpm_widthd-1:0] tmp_remain; reg [lpm_widthn-1:0] not_numer; reg [lpm_widthn-1:0] int_numer; reg [lpm_widthd-1:0] not_denom; reg [lpm_widthd-1:0] int_denom; reg [lpm_widthn-1:0] t_numer; reg [lpm_widthn-1:0] t_q; reg [lpm_widthd-1:0] t_denom; reg [lpm_widthd-1:0] t_r; reg sign_q; reg sign_r; reg sign_n; reg sign_d; reg [8*5:1] lpm_remainderpositive; // LOCAL INTEGER DECLARATION integer i; integer rsig; integer pipe_ptr; // INTERNAL TRI DECLARATION tri0 aclr; tri0 clock; tri1 clken; wire i_aclr; wire i_clock; wire i_clken; buf (i_aclr, aclr); buf (i_clock, clock); buf (i_clken, clken); // COMPONENT INSTANTIATIONS LPM_HINT_EVALUATION eva(); // INITIAL CONSTRUCT BLOCK initial begin // check if lpm_widthn > 0 if (lpm_widthn <= 0) begin $display("Error! LPM_WIDTHN must be greater than 0.\n"); $display("Time: %0t Instance: %m", $time); $finish; end // check if lpm_widthd > 0 if (lpm_widthd <= 0) begin $display("Error! LPM_WIDTHD must be greater than 0.\n"); $display("Time: %0t Instance: %m", $time); $finish; end // check for valid lpm_nrepresentation value if ((lpm_nrepresentation != "SIGNED") && (lpm_nrepresentation != "UNSIGNED")) begin $display("Error! LPM_NREPRESENTATION value must be \"SIGNED\" or \"UNSIGNED\"."); $display("Time: %0t Instance: %m", $time); $finish; end // check for valid lpm_drepresentation value if ((lpm_drepresentation != "SIGNED") && (lpm_drepresentation != "UNSIGNED")) begin $display("Error! LPM_DREPRESENTATION value must be \"SIGNED\" or \"UNSIGNED\"."); $display("Time: %0t Instance: %m", $time); $finish; end // check for valid lpm_remainderpositive value lpm_remainderpositive = eva.GET_PARAMETER_VALUE(lpm_hint, "LPM_REMAINDERPOSITIVE"); if ((lpm_remainderpositive == "TRUE") && (lpm_remainderpositive == "FALSE")) begin $display("Error! LPM_REMAINDERPOSITIVE value must be \"TRUE\" or \"FALSE\"."); $display("Time: %0t Instance: %m", $time); $finish; end for (i = 0; i <= (lpm_pipeline+1); i = i + 1) begin quotient_pipe[i] <= {lpm_widthn{1'b0}}; remain_pipe[i] <= {lpm_widthd{1'b0}}; end pipe_ptr = 0; end // ALWAYS CONSTRUCT BLOCK always @(numer or denom or lpm_remainderpositive) begin sign_q = 1'b0; sign_r = 1'b0; sign_n = 1'b0; sign_d = 1'b0; t_numer = numer; t_denom = denom; if (lpm_nrepresentation == "SIGNED") if (numer[lpm_widthn-1] == 1'b1) begin t_numer = ~numer + 1; // numer is negative number sign_n = 1'b1; end if (lpm_drepresentation == "SIGNED") if (denom[lpm_widthd-1] == 1'b1) begin t_denom = ~denom + 1; // denom is negative numbrt sign_d = 1'b1; end t_q = t_numer / t_denom; // get quotient t_r = t_numer % t_denom; // get remainder sign_q = sign_n ^ sign_d; sign_r = (t_r != {lpm_widthd{1'b0}}) ? sign_n : 1'b0; // Pipeline the result tmp_quotient = (sign_q == 1'b1) ? (~t_q + 1) : t_q; tmp_remain = (sign_r == 1'b1) ? (~t_r + 1) : t_r; // Recalculate the quotient and remainder if remainder is negative number // and LPM_REMAINDERPOSITIVE=TRUE. if ((sign_r) && (lpm_remainderpositive == "TRUE")) begin tmp_quotient = tmp_quotient + ((sign_d == 1'b1) ? 1 : -1 ); tmp_remain = tmp_remain + t_denom; end end always @(posedge i_clock or posedge i_aclr) begin if (i_aclr) begin for (i = 0; i <= (lpm_pipeline+1); i = i + 1) begin quotient_pipe[i] <= {lpm_widthn{1'b0}}; remain_pipe[i] <= {lpm_widthd{1'b0}}; end pipe_ptr <= 0; end else if (i_clken) begin quotient_pipe[pipe_ptr] <= tmp_quotient; remain_pipe[pipe_ptr] <= tmp_remain; if (lpm_pipeline > 1) pipe_ptr <= (pipe_ptr + 1) % lpm_pipeline; end end // CONTINOUS ASSIGNMENT assign quotient = (lpm_pipeline > 0) ? quotient_pipe[pipe_ptr] : tmp_quotient; assign remain = (lpm_pipeline > 0) ? remain_pipe[pipe_ptr] : tmp_remain; endmodule // lpm_divide // END OF MODULE //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_abs // // Description : Parameterized absolute value megafunction. This megafunction // requires the input data to be signed number. // // Limitation : n/a // // Results expected: Return absolute value of data and the overflow status // //END_MODULE_NAME-------------------------------------------------------------- // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module lpm_abs ( data, // Signed number (Required) result, // Absolute value of data[]. overflow // High if data = -2 ^ (LPM_WIDTH-1). ); // GLOBAL PARAMETER DECLARATION parameter lpm_width = 1; // Width of the data[] and result[] ports.(Required) parameter lpm_type = "lpm_abs"; parameter lpm_hint = "UNUSED"; // INPUT PORT DECLARATION input [lpm_width-1:0] data; // OUTPUT PORT DECLARATION output [lpm_width-1:0] result; output overflow; // INTERNAL REGISTER/SIGNAL DECLARATION reg [lpm_width-1:0] result_tmp; reg overflow; // INITIAL CONSTRUCT BLOCK initial begin if (lpm_width <= 0) begin $display("Value of lpm_width parameter must be greater than 0(ERROR)"); $display("Time: %0t Instance: %m", $time); $finish; end end // ALWAYS CONSTRUCT BLOCK always @(data) begin result_tmp = (data[lpm_width-1] == 1) ? (~data) + 1 : data; overflow = (data[lpm_width-1] == 1) ? (result_tmp == (1<<(lpm_width-1))) : 0; end // CONTINOUS ASSIGNMENT assign result = result_tmp; endmodule // lpm_abs //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_counter // // Description : Parameterized counter megafunction. The lpm_counter // megafunction is a binary counter that features an up, // down, or up/down counter with optional synchronous or // asynchronous clear, set, and load ports. // // Limitation : n/a // // Results expected: Data output from the counter and carry-out of the MSB. // //END_MODULE_NAME-------------------------------------------------------------- // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module lpm_counter ( clock, // Positive-edge-triggered clock. (Required) clk_en, // Clock enable input. Enables all synchronous activities. cnt_en, // Count enable input. Disables the count when low (0) without // affecting sload, sset, or sclr. updown, // Controls the direction of the count. High (1) = count up. // Low (0) = count down. aclr, // Asynchronous clear input. aset, // Asynchronous set input. aload, // Asynchronous load input. Asynchronously loads the counter with // the value on the data input. sclr, // Synchronous clear input. Clears the counter on the next active // clock edge. sset, // Synchronous set input. Sets the counter on the next active clock edge. sload, // Synchronous load input. Loads the counter with data[] on the next // active clock edge. data, // Parallel data input to the counter. cin, // Carry-in to the low-order bit. q, // Data output from the counter. cout, // Carry-out of the MSB. eq // Counter decode output. Active high when the counter reaches the specified // count value. ); // GLOBAL PARAMETER DECLARATION parameter lpm_width = 1; //The number of bits in the count, or the width of the q[] // and data[] ports, if they are used. (Required) parameter lpm_direction = "UNUSED"; // Direction of the count. parameter lpm_modulus = 0; // The maximum count, plus one. parameter lpm_avalue = "UNUSED"; // Constant value that is loaded when aset is high. parameter lpm_svalue = "UNUSED"; // Constant value that is loaded on the rising edge // of clock when sset is high. parameter lpm_pvalue = "UNUSED"; parameter lpm_port_updown = "PORT_CONNECTIVITY"; parameter lpm_type = "lpm_counter"; parameter lpm_hint = "UNUSED"; // INPUT PORT DECLARATION input clock; input clk_en; input cnt_en; input updown; input aclr; input aset; input aload; input sclr; input sset; input sload; input [lpm_width-1:0] data; input cin; // OUTPUT PORT DECLARATION output [lpm_width-1:0] q; output cout; output [15:0] eq; // INTERNAL REGISTER/SIGNAL DECLARATION reg [lpm_width-1:0] tmp_count; reg [lpm_width-1:0] adata; reg use_adata; reg tmp_updown; reg [lpm_width:0] tmp_modulus; reg [lpm_width:0] max_modulus; reg [lpm_width-1:0] svalue; reg [lpm_width-1:0] avalue; reg [lpm_width-1:0] pvalue; // INTERNAL WIRE DECLARATION wire w_updown; wire [lpm_width-1:0] final_count; // LOCAL INTEGER DECLARATION integer i; // INTERNAL TRI DECLARATION tri1 clk_en; tri1 cnt_en; tri0 aclr; tri0 aset; tri0 aload; tri0 sclr; tri0 sset; tri0 sload; tri1 cin; tri1 updown_z; wire i_clk_en; wire i_cnt_en; wire i_aclr; wire i_aset; wire i_aload; wire i_sclr; wire i_sset; wire i_sload; wire i_cin; wire i_updown; buf (i_clk_en, clk_en); buf (i_cnt_en, cnt_en); buf (i_aclr, aclr); buf (i_aset, aset); buf (i_aload, aload); buf (i_sclr, sclr); buf (i_sset, sset); buf (i_sload, sload); buf (i_cin, cin); buf (i_updown, updown_z); // TASK DECLARATION task string_to_reg; input [8*40:1] string_value; output [lpm_width-1:0] value; reg [8*40:1] reg_s; reg [8:1] digit; reg [8:1] tmp; reg [lpm_width-1:0] ivalue; integer m; begin ivalue = {lpm_width{1'b0}}; reg_s = string_value; for (m=1; m<=40; m=m+1) begin tmp = reg_s[320:313]; digit = tmp & 8'b00001111; reg_s = reg_s << 8; ivalue = ivalue * 10 + digit; end value = ivalue; end endtask // INITIAL CONSTRUCT BLOCK initial begin max_modulus = 1 << lpm_width; // check if lpm_width < 0 if (lpm_width <= 0) begin $display("Error! LPM_WIDTH must be greater than 0.\n"); $display("Time: %0t Instance: %m", $time); $finish; end // check if lpm_modulus < 0 if (lpm_modulus < 0) begin $display("Error! LPM_MODULUS must be greater or equal to 0.\n"); $display("Time: %0t Instance: %m", $time); $finish; end // check if lpm_modulus > 1< max_modulus) begin $display("Warning! LPM_MODULUS should be within 1 to 2^LPM_WIDTH. Assuming no modulus input.\n"); $display ("Time: %0t Instance: %m", $time); end // check if lpm_direction valid if ((lpm_direction != "UNUSED") && (lpm_direction != "DEFAULT") && (lpm_direction != "UP") && (lpm_direction != "DOWN")) begin $display("Error! LPM_DIRECTION must be \"UP\" or \"DOWN\" if used.\n"); $display("Time: %0t Instance: %m", $time); $finish; end if (lpm_avalue == "UNUSED") avalue = {lpm_width{1'b1}}; else string_to_reg(lpm_avalue, avalue); if (lpm_svalue == "UNUSED") svalue = {lpm_width{1'b1}}; else string_to_reg(lpm_svalue, svalue); if (lpm_pvalue == "UNUSED") pvalue = {lpm_width{1'b0}}; else string_to_reg(lpm_pvalue, pvalue); tmp_modulus = ((lpm_modulus == 0) || (lpm_modulus > max_modulus)) ? max_modulus : lpm_modulus; tmp_count = pvalue; use_adata = 1'b0; end // NCSIM will only assigns 1'bZ to unconnected port at time 0fs + 1 // verilator lint_off STMTDLY initial #0 // verilator lint_on STMTDLY begin // // check if lpm_direction valid if ((lpm_direction != "UNUSED") && (lpm_direction != "DEFAULT") && (updown !== 1'bz) && (lpm_port_updown == "PORT_CONNECTIVITY")) begin $display("Error! LPM_DIRECTION and UPDOWN cannot be used at the same time.\n"); $display("Time: %0t Instance: %m", $time); $finish; end end // ALWAYS CONSTRUCT BLOCK always @(posedge i_aclr or posedge i_aset or posedge i_aload or posedge clock) begin if (i_aclr || i_aset || i_aload) use_adata <= 1'b1; else if ($time > 0) begin if (i_clk_en) begin use_adata <= 1'b0; if (i_sclr) tmp_count <= 0; else if (i_sset) tmp_count <= svalue; else if (i_sload) tmp_count <= data; else if (i_cnt_en && i_cin) begin if (w_updown) tmp_count <= (final_count == tmp_modulus-1) ? 0 : final_count+1; else tmp_count <= (final_count == 0) ? tmp_modulus-1 : final_count-1; end else tmp_count <= final_count; end end end always @(i_aclr or i_aset or i_aload or data or avalue) begin if (i_aclr) begin adata <= 0; end else if (i_aset) begin adata <= avalue; end else if (i_aload) adata <= data; end // CONTINOUS ASSIGNMENT assign q = final_count; assign final_count = (use_adata == 1'b1) ? adata : tmp_count; assign cout = (i_cin && (((w_updown==0) && (final_count==0)) || ((w_updown==1) && ((final_count==tmp_modulus-1) || (final_count=={lpm_width{1'b1}}))) )) ? 1'b1 : 1'b0; assign updown_z = updown; assign w_updown = (lpm_port_updown == "PORT_USED") ? i_updown : (lpm_port_updown == "PORT_UNUSED") ? ((lpm_direction == "DOWN") ? 1'b0 : 1'b1) : ((((lpm_direction == "UNUSED") || (lpm_direction == "DEFAULT")) && (i_updown == 1)) || (lpm_direction == "UP")) ? 1'b1 : 1'b0; assign eq = {16{1'b0}}; endmodule // lpm_counter // END OF MODULE //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_latch // // Description : Parameterized latch megafunction. // // Limitation : n/a // // Results expected: Data output from the latch. // //END_MODULE_NAME-------------------------------------------------------------- // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module lpm_latch ( data, // Data input to the latch. gate, // Latch enable input. High = flow-through, low = latch. (Required) aclr, // Asynchronous clear input. aset, // Asynchronous set input. aconst, q // Data output from the latch. ); // GLOBAL PARAMETER DECLARATION parameter lpm_width = 1; // Width of the data[] and q[] ports. (Required) parameter lpm_avalue = "UNUSED"; // Constant value that is loaded when aset is high. parameter lpm_pvalue = "UNUSED"; parameter lpm_type = "lpm_latch"; parameter lpm_hint = "UNUSED"; // INPUT PORT DECLARATION input [lpm_width-1:0] data; input gate; input aclr; input aset; input aconst; // OUTPUT PORT DECLARATION output [lpm_width-1:0] q; // INTERNAL REGISTER/SIGNAL DECLARATION reg [lpm_width-1:0] q; reg [lpm_width-1:0] avalue; reg [lpm_width-1:0] pvalue; // INTERNAL TRI DECLARATION tri0 [lpm_width-1:0] data; tri0 aclr; tri0 aset; tri0 aconst; wire i_aclr; wire i_aset; buf (i_aclr, aclr); buf (i_aset, aset); // TASK DECLARATION task string_to_reg; input [8*40:1] string_value; output [lpm_width-1:0] value; reg [8*40:1] reg_s; reg [8:1] digit; reg [8:1] tmp; reg [lpm_width-1:0] ivalue; integer m; begin ivalue = {lpm_width{1'b0}}; reg_s = string_value; for (m=1; m<=40; m=m+1) begin tmp = reg_s[320:313]; digit = tmp & 8'b00001111; reg_s = reg_s << 8; ivalue = ivalue * 10 + digit; end value = ivalue; end endtask // INITIAL CONSTRUCT BLOCK initial begin if (lpm_width <= 0) begin $display("Value of lpm_width parameter must be greater than 0 (ERROR)"); $display("Time: %0t Instance: %m", $time); $finish; end if (lpm_pvalue != "UNUSED") begin string_to_reg(lpm_pvalue, pvalue); q = pvalue; end if (lpm_avalue == "UNUSED") avalue = {lpm_width{1'b1}}; else string_to_reg(lpm_avalue, avalue); end // ALWAYS CONSTRUCT BLOCK always @(data or gate or i_aclr or i_aset or avalue) begin if (i_aclr) q <= {lpm_width{1'b0}}; else if (i_aset) q <= avalue; else if (gate) q <= data; end endmodule // lpm_latch //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_ff // // Description : Parameterized flipflop megafunction. The lpm_ff function // contains features that are not available in the DFF, DFFE, // DFFEA, TFF, and TFFE primitives, such as synchronous or // asynchronous set, clear, and load inputs. // // Limitation : n/a // // Results expected: Data output from D or T flipflops. // //END_MODULE_NAME-------------------------------------------------------------- // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module lpm_ff ( data, // T-type flipflop: Toggle enable // D-type flipflop: Data input clock, // Positive-edge-triggered clock. (Required) enable, // Clock enable input. aclr, // Asynchronous clear input. aset, // Asynchronous set input. aload, // Asynchronous load input. Asynchronously loads the flipflop with // the value on the data input. sclr, // Synchronous clear input. sset, // Synchronous set input. sload, // Synchronous load input. Loads the flipflop with the value on the // data input on the next active clock edge. q // Data output from D or T flipflops. (Required) ); // GLOBAL PARAMETER DECLARATION parameter lpm_width = 1; // Width of the data[] and q[] ports. (Required) parameter lpm_avalue = "UNUSED"; // Constant value that is loaded when aset is high. parameter lpm_svalue = "UNUSED"; // Constant value that is loaded on the rising edge // of clock when sset is high. parameter lpm_pvalue = "UNUSED"; parameter lpm_fftype = "DFF"; // Type of flipflop parameter lpm_type = "lpm_ff"; parameter lpm_hint = "UNUSED"; // INPUT PORT DECLARATION input [lpm_width-1:0] data; input clock; input enable; input aclr; input aset; input aload; input sclr; input sset; input sload ; // OUTPUT PORT DECLARATION output [lpm_width-1:0] q; // INTERNAL REGISTER/SIGNAL DECLARATION reg [lpm_width-1:0] tmp_q; reg [lpm_width-1:0] adata; reg use_adata; reg [lpm_width-1:0] svalue; reg [lpm_width-1:0] avalue; reg [lpm_width-1:0] pvalue; // INTERNAL WIRE DECLARATION wire [lpm_width-1:0] final_q; // LOCAL INTEGER DECLARATION integer i; // INTERNAL TRI DECLARATION tri1 [lpm_width-1:0] data; tri1 enable; tri0 sload; tri0 sclr; tri0 sset; tri0 aload; tri0 aclr; tri0 aset; wire i_enable; wire i_sload; wire i_sclr; wire i_sset; wire i_aload; wire i_aclr; wire i_aset; buf (i_enable, enable); buf (i_sload, sload); buf (i_sclr, sclr); buf (i_sset, sset); buf (i_aload, aload); buf (i_aclr, aclr); buf (i_aset, aset); // TASK DECLARATION task string_to_reg; input [8*40:1] string_value; output [lpm_width-1:0] value; reg [8*40:1] reg_s; reg [8:1] digit; reg [8:1] tmp; reg [lpm_width-1:0] ivalue; integer m; begin ivalue = {lpm_width{1'b0}}; reg_s = string_value; for (m=1; m<=40; m=m+1) begin tmp = reg_s[320:313]; digit = tmp & 8'b00001111; reg_s = reg_s << 8; ivalue = ivalue * 10 + digit; end value = ivalue; end endtask // INITIAL CONSTRUCT BLOCK initial begin if (lpm_width <= 0) begin $display("Value of lpm_width parameter must be greater than 0(ERROR)"); $display("Time: %0t Instance: %m", $time); $finish; end if ((lpm_fftype != "DFF") && (lpm_fftype != "TFF") && (lpm_fftype != "UNUSED")) // non-LPM 220 standard begin $display("Error! LPM_FFTYPE value must be \"DFF\" or \"TFF\"."); $display("Time: %0t Instance: %m", $time); $finish; end if (lpm_avalue == "UNUSED") avalue = {lpm_width{1'b1}}; else string_to_reg(lpm_avalue, avalue); if (lpm_svalue == "UNUSED") svalue = {lpm_width{1'b1}}; else string_to_reg(lpm_svalue, svalue); if (lpm_pvalue == "UNUSED") pvalue = {lpm_width{1'b0}}; else string_to_reg(lpm_pvalue, pvalue); tmp_q = pvalue; use_adata = 1'b0; end // ALWAYS CONSTRUCT BLOCK always @(posedge i_aclr or posedge i_aset or posedge i_aload or posedge clock) begin // Asynchronous process if (i_aclr || i_aset || i_aload) use_adata <= 1'b1; else if ($time > 0) begin // Synchronous process if (i_enable) begin use_adata <= 1'b0; if (i_sclr) tmp_q <= 0; else if (i_sset) tmp_q <= svalue; else if (i_sload) // Load data tmp_q <= data; else begin if (lpm_fftype == "TFF") // toggle begin for (i = 0; i < lpm_width; i=i+1) if (data[i] == 1'b1) tmp_q[i] <= ~final_q[i]; else tmp_q[i] <= final_q[i]; end else // DFF, load data tmp_q <= data; end end end end always @(i_aclr or i_aset or i_aload or data or avalue or pvalue) begin if (i_aclr === 1'b1) adata <= {lpm_width{1'b0}}; else if (i_aclr === 1'bx) adata <= {lpm_width{1'bx}}; else if (i_aset) adata <= avalue; else if (i_aload) adata <= data; else if ((i_aclr === 1'b0) && ($time == 0)) adata <= pvalue; end // CONTINOUS ASSIGNMENT assign q = final_q; assign final_q = (use_adata == 1'b1) ? adata : tmp_q; endmodule // lpm_ff // END OF MODULE //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_shiftreg // // Description : Parameterized shift register megafunction. // // Limitation : n/a // // Results expected: Data output from the shift register and the Serial shift data output. // //END_MODULE_NAME-------------------------------------------------------------- // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module lpm_shiftreg ( data, // Data input to the shift register. clock, // Positive-edge-triggered clock. (Required) enable, // Clock enable input shiftin, // Serial shift data input. load, // Synchronous parallel load. High (1): load operation; // low (0): shift operation. aclr, // Asynchronous clear input. aset, // Asynchronous set input. sclr, // Synchronous clear input. sset, // Synchronous set input. q, // Data output from the shift register. shiftout // Serial shift data output. ); // GLOBAL PARAMETER DECLARATION parameter lpm_width = 1; // Width of the data[] and q ports. (Required) parameter lpm_direction = "LEFT"; // Values are "LEFT", "RIGHT", and "UNUSED". parameter lpm_avalue = "UNUSED"; // Constant value that is loaded when aset is high. parameter lpm_svalue = "UNUSED"; // Constant value that is loaded on the rising edge // of clock when sset is high. parameter lpm_pvalue = "UNUSED"; parameter lpm_type = "lpm_shiftreg"; parameter lpm_hint = "UNUSED"; // INPUT PORT DECLARATION input [lpm_width-1:0] data; input clock; input enable; input shiftin; input load; input aclr; input aset; input sclr; input sset; // OUTPUT PORT DECLARATION output [lpm_width-1:0] q; output shiftout; // INTERNAL REGISTER/SIGNAL DECLARATION reg [lpm_width-1:0] tmp_q; reg abit; reg [lpm_width-1:0] svalue; reg [lpm_width-1:0] avalue; reg [lpm_width-1:0] pvalue; // LOCAL INTEGER DECLARATION integer i; // INTERNAL WIRE DECLARATION wire tmp_shiftout; // INTERNAL TRI DECLARATION tri1 enable; tri1 shiftin; tri0 load; tri0 aclr; tri0 aset; tri0 sclr; tri0 sset; wire i_enable; wire i_shiftin; wire i_load; wire i_aclr; wire i_aset; wire i_sclr; wire i_sset; buf (i_enable, enable); buf (i_shiftin, shiftin); buf (i_load, load); buf (i_aclr, aclr); buf (i_aset, aset); buf (i_sclr, sclr); buf (i_sset, sset); // TASK DECLARATION task string_to_reg; input [8*40:1] string_value; output [lpm_width-1:0] value; reg [8*40:1] reg_s; reg [8:1] digit; reg [8:1] tmp; reg [lpm_width-1:0] ivalue; integer m; begin ivalue = {lpm_width{1'b0}}; reg_s = string_value; for (m=1; m<=40; m=m+1) begin tmp = reg_s[320:313]; digit = tmp & 8'b00001111; reg_s = reg_s << 8; ivalue = ivalue * 10 + digit; end value = ivalue; end endtask // INITIAL CONSTRUCT BLOCK initial begin if (lpm_width <= 0) begin $display("Value of lpm_width parameter must be greater than 0 (ERROR)"); $display("Time: %0t Instance: %m", $time); $finish; end if ((lpm_direction != "LEFT") && (lpm_direction != "RIGHT") && (lpm_direction != "UNUSED")) // non-LPM 220 standard begin $display("Error! LPM_DIRECTION value must be \"LEFT\" or \"RIGHT\"."); $display("Time: %0t Instance: %m", $time); $finish; end if (lpm_avalue == "UNUSED") avalue = {lpm_width{1'b1}}; else string_to_reg(lpm_avalue, avalue); if (lpm_svalue == "UNUSED") svalue = {lpm_width{1'b1}}; else string_to_reg(lpm_svalue, svalue); if (lpm_pvalue == "UNUSED") pvalue = {lpm_width{1'b0}}; else string_to_reg(lpm_pvalue, pvalue); tmp_q = pvalue; end // ALWAYS CONSTRUCT BLOCK always @(i_aclr or i_aset or avalue) begin if (i_aclr) tmp_q <= {lpm_width{1'b0}}; else if (i_aset) tmp_q <= avalue; end always @(posedge clock) begin if (i_aclr) tmp_q <= (i_aset) ? {lpm_width{1'bx}} : {lpm_width{1'b0}}; else if (i_aset) tmp_q <= avalue; else begin if (i_enable) begin if (i_sclr) tmp_q <= {lpm_width{1'b0}}; else if (i_sset) tmp_q <= svalue; else if (i_load) tmp_q <= data; else if (!i_load) begin if ((lpm_direction == "LEFT") || (lpm_direction == "UNUSED")) {abit,tmp_q} <= {tmp_q,i_shiftin}; else if (lpm_direction == "RIGHT") {tmp_q,abit} <= {i_shiftin,tmp_q}; end end end end // CONTINOUS ASSIGNMENT assign tmp_shiftout = (lpm_direction == "RIGHT") ? tmp_q[0] : tmp_q[lpm_width-1]; assign q = tmp_q; assign shiftout = tmp_shiftout; endmodule // lpm_shiftreg // END OF MODULE //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_ram_dq // // Description : Parameterized RAM with separate input and output ports megafunction. // lpm_ram_dq implement asynchronous memory or memory with synchronous // inputs and/or outputs. // // Limitation : n/a // // Results expected: Data output from the memory. // //END_MODULE_NAME-------------------------------------------------------------- // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module lpm_ram_dq ( data, // Data input to the memory. (Required) address, // Address input to the memory. (Required) inclock, // Synchronizes memory loading. outclock, // Synchronizes q outputs from memory. we, // Write enable input. Enables write operations to the memory when high. (Required) q // Data output from the memory. (Required) ); // GLOBAL PARAMETER DECLARATION parameter lpm_width = 1; // Width of data[] and q[] ports. (Required) parameter lpm_widthad = 1; // Width of the address port. (Required) parameter lpm_numwords = 1 << lpm_widthad; // Number of words stored in memory. parameter lpm_indata = "REGISTERED"; // Controls whether the data port is registered. parameter lpm_address_control = "REGISTERED"; // Controls whether the address and we ports are registered. parameter lpm_outdata = "REGISTERED"; // Controls whether the q ports are registered. parameter lpm_file = "UNUSED"; // Name of the file containing RAM initialization data. parameter use_eab = "ON"; // Specified whether to use the EAB or not. parameter intended_device_family = "Stratix"; parameter lpm_type = "lpm_ram_dq"; parameter lpm_hint = "UNUSED"; // INPUT PORT DECLARATION input [lpm_width-1:0] data; input [lpm_widthad-1:0] address; input inclock; input outclock; input we; // OUTPUT PORT DECLARATION output [lpm_width-1:0] q; // INTERNAL REGISTER/SIGNAL DECLARATION reg [lpm_width-1:0] mem_data [lpm_numwords-1:0]; reg [lpm_width-1:0] tmp_q; reg [lpm_width-1:0] pdata; reg [lpm_width-1:0] in_data; reg [lpm_widthad-1:0] paddress; reg pwe; reg [lpm_width-1:0] ZEROS, ONES, UNKNOWN; `ifdef VERILATOR reg [`LPM_MAX_NAME_SZ*8:1] ram_initf; `else reg [8*256:1] ram_initf; `endif // LOCAL INTEGER DECLARATION integer i; // INTERNAL TRI DECLARATION tri0 inclock; tri0 outclock; wire i_inclock; wire i_outclock; buf (i_inclock, inclock); buf (i_outclock, outclock); // COMPONENT INSTANTIATIONS LPM_DEVICE_FAMILIES dev (); LPM_MEMORY_INITIALIZATION mem (); // FUNCTON DECLARATION // Check the validity of the address. function ValidAddress; input [lpm_widthad-1:0] paddress; begin ValidAddress = 1'b0; if (^paddress === {lpm_widthad{1'bx}}) begin $display("%t:Error! Invalid address.\n", $time); $display("Time: %0t Instance: %m", $time); end else if (paddress >= lpm_numwords) begin $display("%t:Error! Address out of bound on RAM.\n", $time); $display("Time: %0t Instance: %m", $time); end else ValidAddress = 1'b1; end endfunction // INITIAL CONSTRUCT BLOCK initial begin // Initialize the internal data register. pdata = {lpm_width{1'b0}}; paddress = {lpm_widthad{1'b0}}; pwe = 1'b0; if (lpm_width <= 0) begin $display("Error! LPM_WIDTH parameter must be greater than 0."); $display("Time: %0t Instance: %m", $time); $finish; end if (lpm_widthad <= 0) begin $display("Error! LPM_WIDTHAD parameter must be greater than 0."); $display("Time: %0t Instance: %m", $time); $finish; end // check for number of words out of bound if ((lpm_numwords > (1 << lpm_widthad)) || (lpm_numwords <= (1 << (lpm_widthad-1)))) begin $display("Error! The ceiling of log2(LPM_NUMWORDS) must equal to LPM_WIDTHAD."); $display("Time: %0t Instance: %m", $time); $finish; end if ((lpm_address_control != "REGISTERED") && (lpm_address_control != "UNREGISTERED")) begin $display("Error! LPM_ADDRESS_CONTROL must be \"REGISTERED\" or \"UNREGISTERED\"."); $display("Time: %0t Instance: %m", $time); $finish; end if ((lpm_indata != "REGISTERED") && (lpm_indata != "UNREGISTERED")) begin $display("Error! LPM_INDATA must be \"REGISTERED\" or \"UNREGISTERED\"."); $display("Time: %0t Instance: %m", $time); $finish; end if ((lpm_outdata != "REGISTERED") && (lpm_outdata != "UNREGISTERED")) begin $display("Error! LPM_OUTDATA must be \"REGISTERED\" or \"UNREGISTERED\"."); $display("Time: %0t Instance: %m", $time); $finish; end if (dev.IS_VALID_FAMILY(intended_device_family) == 0) begin $display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family); $display("Time: %0t Instance: %m", $time); $finish; end for (i=0; i < lpm_width; i=i+1) begin ZEROS[i] = 1'b0; ONES[i] = 1'b1; UNKNOWN[i] = 1'bX; end for (i = 0; i < lpm_numwords; i=i+1) mem_data[i] = {lpm_width{1'b0}}; // load data to the RAM if (lpm_file != "UNUSED") begin mem.convert_to_ver_file(lpm_file, lpm_width, ram_initf); $readmemh(ram_initf, mem_data); end tmp_q = ZEROS; end // ALWAYS CONSTRUCT BLOCK always @(posedge i_inclock) begin if (lpm_address_control == "REGISTERED") begin if ((we) && (use_eab != "ON") && (lpm_hint != "USE_EAB=ON")) begin if (lpm_indata == "REGISTERED") mem_data[address] <= data; else mem_data[address] <= pdata; end paddress <= address; pwe <= we; end if (lpm_indata == "REGISTERED") pdata <= data; end always @(data) begin if (lpm_indata == "UNREGISTERED") pdata <= data; end always @(address) begin if (lpm_address_control == "UNREGISTERED") paddress <= address; end always @(we) begin if (lpm_address_control == "UNREGISTERED") pwe <= we; end always @(pdata or paddress or pwe) begin :UNREGISTERED_INCLOCK if (ValidAddress(paddress)) begin if ((lpm_address_control == "UNREGISTERED") && (pwe)) mem_data[paddress] <= pdata; end else begin if (lpm_outdata == "UNREGISTERED") tmp_q <= {lpm_width{1'bx}}; end end always @(posedge i_outclock) begin if (lpm_outdata == "REGISTERED") begin if (ValidAddress(paddress)) tmp_q <= mem_data[paddress]; else tmp_q <= {lpm_width{1'bx}}; end end always @(i_inclock or pwe or paddress or pdata) begin if ((lpm_address_control == "REGISTERED") && (pwe)) if ((use_eab == "ON") || (lpm_hint == "USE_EAB=ON")) begin if (i_inclock == 1'b0) mem_data[paddress] = pdata; end end // CONTINOUS ASSIGNMENT assign q = (lpm_outdata == "UNREGISTERED") ? mem_data[paddress] : tmp_q; endmodule // lpm_ram_dq // END OF MODULE //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_ram_dp // // Description : Parameterized dual-port RAM megafunction. // // Limitation : n/a // // Results expected: Data output from the memory. // //END_MODULE_NAME-------------------------------------------------------------- // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module lpm_ram_dp ( data, // Data input to the memory. (Required) rdaddress, // Read address input to the memory. (Required) wraddress, // Write address input to the memory. (Required) rdclock, // Positive-edge-triggered clock for read operation. rdclken, // Clock enable for rdclock. wrclock, // Positive-edge-triggered clock for write operation. wrclken, // Clock enable for wrclock. rden, // Read enable input. Disables reading when low (0). wren, // Write enable input. (Required) q // Data output from the memory. (Required) ); // GLOBAL PARAMETER DECLARATION parameter lpm_width = 1; // Width of the data[] and q[] ports. (Required) parameter lpm_widthad = 1; // Width of the rdaddress[] and wraddress[] ports. (Required) parameter lpm_numwords = 1 << lpm_widthad; // Number of words stored in memory. parameter lpm_indata = "REGISTERED"; // Determines the clock used by the data port. parameter lpm_rdaddress_control = "REGISTERED"; // Determines the clock used by the rdaddress and rden ports. parameter lpm_wraddress_control = "REGISTERED"; // Determines the clock used by the wraddress and wren ports. parameter lpm_outdata = "REGISTERED"; // Determines the clock used by the q[] pxort. parameter lpm_file = "UNUSED"; // Name of the file containing RAM initialization data. parameter use_eab = "ON"; // Specified whether to use the EAB or not. parameter rden_used = "TRUE"; // Specified whether to use the rden port or not. parameter intended_device_family = "Stratix"; parameter lpm_type = "lpm_ram_dp"; parameter lpm_hint = "UNUSED"; // INPUT PORT DECLARATION input [lpm_width-1:0] data; input [lpm_widthad-1:0] rdaddress; input [lpm_widthad-1:0] wraddress; input rdclock; input rdclken; input wrclock; input wrclken; input rden; input wren; // OUTPUT PORT DECLARATION output [lpm_width-1:0] q; // INTERNAL REGISTER/SIGNAL DECLARATION reg [lpm_width-1:0] mem_data [(1<= lpm_numwords) begin $display("%t:Error! Address out of bound on RAM.\n", $time); $display("Time: %0t Instance: %m", $time); end else ValidAddress = 1'b1; end endfunction // INITIAL CONSTRUCT BLOCK initial begin // Check for invalid parameters if (lpm_width < 1) begin $display("Error! lpm_width parameter must be greater than 0."); $display("Time: %0t Instance: %m", $time); $finish; end if (lpm_widthad < 1) begin $display("Error! lpm_widthad parameter must be greater than 0."); $display("Time: %0t Instance: %m", $time); $finish; end if ((lpm_indata != "REGISTERED") && (lpm_indata != "UNREGISTERED")) begin $display("Error! lpm_indata must be \"REGISTERED\" or \"UNREGISTERED\"."); $display("Time: %0t Instance: %m", $time); $finish; end if ((lpm_outdata != "REGISTERED") && (lpm_outdata != "UNREGISTERED")) begin $display("Error! lpm_outdata must be \"REGISTERED\" or \"UNREGISTERED\"."); $display("Time: %0t Instance: %m", $time); $finish; end if ((lpm_wraddress_control != "REGISTERED") && (lpm_wraddress_control != "UNREGISTERED")) begin $display("Error! lpm_wraddress_control must be \"REGISTERED\" or \"UNREGISTERED\"."); $display("Time: %0t Instance: %m", $time); end if ((lpm_rdaddress_control != "REGISTERED") && (lpm_rdaddress_control != "UNREGISTERED")) begin $display("Error! lpm_rdaddress_control must be \"REGISTERED\" or \"UNREGISTERED\"."); $display("Time: %0t Instance: %m", $time); $finish; end if (dev.IS_VALID_FAMILY(intended_device_family) == 0) begin $display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family); $display("Time: %0t Instance: %m", $time); $finish; end // Initialize mem_data i_numwords = (lpm_numwords) ? lpm_numwords : (1< 0)) i_data_reg <= data; if (lpm_wraddress_control == "REGISTERED") if ((i_inclocken == 1'b1) && ($time > 0)) begin i_wraddress_reg <= wraddress; i_wren_reg <= i_wren; end end always @(posedge i_outclock) begin if (lpm_outdata == "REGISTERED") if ((i_outclocken == 1'b1) && ($time > 0)) begin i_q_reg <= i_q_tmp; end if (lpm_rdaddress_control == "REGISTERED") if ((i_outclocken == 1'b1) && ($time > 0)) begin i_rdaddress_reg <= rdaddress; i_rden_reg <= i_rden; end end //========= // Memory //========= always @(i_data_tmp or i_wren_tmp or i_wraddress_tmp or negedge i_inclock) begin if (i_wren_tmp == 1'b1) if (ValidAddress(i_wraddress_tmp)) begin if (((use_eab == "ON") || (lpm_hint == "USE_EAB=ON")) && (lpm_wraddress_control == "REGISTERED")) begin if (i_inclock == 1'b0) mem_data[i_wraddress_tmp] <= i_data_tmp; end else mem_data[i_wraddress_tmp] <= i_data_tmp; end end always @(i_rden_tmp or i_rdaddress_tmp or mem_data[i_rdaddress_tmp]) begin if (i_rden_tmp == 1'b1) i_q_tmp = (ValidAddress(i_rdaddress_tmp)) ? mem_data[i_rdaddress_tmp] : {lpm_width{1'bx}}; end //======= // Sync //======= always @(wraddress or i_wraddress_reg) i_wraddress_tmp = (lpm_wraddress_control == "REGISTERED") ? i_wraddress_reg : wraddress; always @(rdaddress or i_rdaddress_reg) i_rdaddress_tmp = (lpm_rdaddress_control == "REGISTERED") ? i_rdaddress_reg : rdaddress; always @(i_wren or i_wren_reg) i_wren_tmp = (lpm_wraddress_control == "REGISTERED") ? i_wren_reg : i_wren; always @(i_rden or i_rden_reg) i_rden_tmp = (lpm_rdaddress_control == "REGISTERED") ? i_rden_reg : i_rden; always @(data or i_data_reg) i_data_tmp = (lpm_indata == "REGISTERED") ? i_data_reg : data; // CONTINOUS ASSIGNMENT assign q = (lpm_outdata == "REGISTERED") ? i_q_reg : i_q_tmp; endmodule // lpm_ram_dp // END OF MODULE //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_ram_io // // Description : Parameterized RAM with a single I/O port megafunction // // Limitation : This megafunction is provided only for backward // compatibility in Cyclone, Stratix, and Stratix GX designs; // instead, Altera recommends using the altsyncram // megafunction // // Results expected: Output of RAM content at bi-directional DIO. // //END_MODULE_NAME-------------------------------------------------------------- `timescale 1 ps / 1 ps // MODULE DECLARATION module lpm_ram_io ( dio, inclock, outclock, we, memenab, outenab, address ); // PARAMETER DECLARATION parameter lpm_type = "lpm_ram_io"; parameter lpm_width = 1; parameter lpm_widthad = 1; parameter lpm_numwords = 1<< lpm_widthad; parameter lpm_indata = "REGISTERED"; parameter lpm_address_control = "REGISTERED"; parameter lpm_outdata = "REGISTERED"; parameter lpm_file = "UNUSED"; parameter lpm_hint = "UNUSED"; parameter use_eab = "ON"; parameter intended_device_family = "UNUSED"; // INPUT PORT DECLARATION input [lpm_widthad-1:0] address; input inclock, outclock, we; input memenab; input outenab; // INPUT/OUTPUT PORT DECLARATION inout [lpm_width-1:0] dio; // INTERNAL REGISTERS DECLARATION reg [lpm_width-1:0] mem_data [lpm_numwords-1:0]; reg [lpm_width-1:0] tmp_io; reg [lpm_width-1:0] tmp_q; reg [lpm_width-1:0] pdio; reg [lpm_widthad-1:0] paddress; reg [lpm_widthad-1:0] paddress_tmp; reg pwe; `ifdef VERILATOR reg [`LPM_MAX_NAME_SZ*8:1] ram_initf; `else reg [8*256:1] ram_initf; `endif // INTERNAL WIRE DECLARATION wire [lpm_width-1:0] read_data; wire i_inclock; wire i_outclock; wire i_memenab; wire i_outenab; // LOCAL INTEGER DECLARATION integer i; // INTERNAL TRI DECLARATION tri0 inclock; tri0 outclock; tri1 memenab; tri1 outenab; // INTERNAL BUF DECLARATION buf (i_inclock, inclock); buf (i_outclock, outclock); buf (i_memenab, memenab); buf (i_outenab, outenab); // FUNCTON DECLARATION function ValidAddress; input [lpm_widthad-1:0] paddress; begin ValidAddress = 1'b0; if (^paddress === {lpm_widthad{1'bx}}) begin $display("%t:Error: Invalid address.", $time); $display("Time: %0t Instance: %m", $time); $finish; end else if (paddress >= lpm_numwords) begin $display("%t:Error: Address out of bound on RAM.", $time); $display("Time: %0t Instance: %m", $time); $finish; end else ValidAddress = 1'b1; end endfunction // COMPONENT INSTANTIATIONS LPM_MEMORY_INITIALIZATION mem (); // INITIAL CONSTRUCT BLOCK initial begin if (lpm_width <= 0) begin $display("Error! LPM_WIDTH parameter must be greater than 0."); $display("Time: %0t Instance: %m", $time); $finish; end if (lpm_widthad <= 0) begin $display("Error! LPM_WIDTHAD parameter must be greater than 0."); $display("Time: %0t Instance: %m", $time); $finish; end // check for number of words out of bound if ((lpm_numwords > (1 << lpm_widthad)) ||(lpm_numwords <= (1 << (lpm_widthad-1)))) begin $display("Error! The ceiling of log2(LPM_NUMWORDS) must equal to LPM_WIDTHAD."); $display("Time: %0t Instance: %m", $time); $finish; end if ((lpm_indata != "REGISTERED") && (lpm_indata != "UNREGISTERED")) begin $display("Error! LPM_INDATA must be \"REGISTERED\" or \"UNREGISTERED\"."); $display("Time: %0t Instance: %m", $time); $finish; end if ((lpm_address_control != "REGISTERED") && (lpm_address_control != "UNREGISTERED")) begin $display("Error! LPM_ADDRESS_CONTROL must be \"REGISTERED\" or \"UNREGISTERED\"."); $display("Time: %0t Instance: %m", $time); $finish; end if ((lpm_outdata != "REGISTERED") && (lpm_outdata != "UNREGISTERED")) begin $display("Error! LPM_OUTDATA must be \"REGISTERED\" or \"UNREGISTERED\"."); $display("Time: %0t Instance: %m", $time); $finish; end for (i = 0; i < lpm_numwords; i=i+1) mem_data[i] = {lpm_width{1'b0}}; // Initialize input/output pwe = 1'b0; pdio = {lpm_width{1'b0}}; paddress = {lpm_widthad{1'b0}}; paddress_tmp = {lpm_widthad{1'b0}}; tmp_io = {lpm_width{1'b0}}; tmp_q = {lpm_width{1'b0}}; // load data to the RAM if (lpm_file != "UNUSED") begin mem.convert_to_ver_file(lpm_file, lpm_width, ram_initf); $readmemh(ram_initf, mem_data); end end // ALWAYS CONSTRUCT BLOCK always @(dio) begin if (lpm_indata == "UNREGISTERED") pdio <= dio; end always @(address) begin if (lpm_address_control == "UNREGISTERED") paddress <= address; end always @(we) begin if (lpm_address_control == "UNREGISTERED") pwe <= we; end always @(posedge i_inclock) begin if (lpm_indata == "REGISTERED") pdio <= dio; if (lpm_address_control == "REGISTERED") begin paddress <= address; pwe <= we; end end always @(pdio or paddress or pwe or i_memenab) begin if (ValidAddress(paddress)) begin paddress_tmp <= paddress; if (lpm_address_control == "UNREGISTERED") if (pwe && i_memenab) mem_data[paddress] <= pdio; end else begin if (lpm_outdata == "UNREGISTERED") tmp_q <= {lpm_width{1'bx}}; end end always @(read_data) begin if (lpm_outdata == "UNREGISTERED") tmp_q <= read_data; end always @(negedge i_inclock or pdio) begin if (lpm_address_control == "REGISTERED") if ((use_eab == "ON") || (lpm_hint == "USE_EAB=ON")) if (pwe && i_memenab && (i_inclock == 1'b0)) mem_data[paddress] = pdio; end always @(posedge i_inclock) begin if (lpm_address_control == "REGISTERED") if ((use_eab == "OFF") && pwe && i_memenab) mem_data[paddress] <= pdio; end always @(posedge i_outclock) begin if (lpm_outdata == "REGISTERED") tmp_q <= mem_data[paddress]; end always @(i_memenab or i_outenab or tmp_q) begin if (i_memenab && i_outenab) tmp_io = tmp_q; else if ((!i_memenab) || (i_memenab && (!i_outenab))) tmp_io = {lpm_width{1'bz}}; end // CONTINOUS ASSIGNMENT assign dio = tmp_io; assign read_data = mem_data[paddress_tmp]; endmodule // lpm_ram_io //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_rom // // Description : Parameterized ROM megafunction. This megafunction is provided // only for backward compatibility in Cyclone, Stratix, and // Stratix GX designs; instead, Altera recommends using the // altsyncram megafunction. // // Limitation : This option is available for all Altera devices supported by // the Quartus II software except MAX 3000 and MAX 7000 devices. // // Results expected: Output of memory. // //END_MODULE_NAME-------------------------------------------------------------- // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module lpm_rom ( address, // Address input to the memory. (Required) inclock, // Clock for input registers. outclock, // Clock for output registers. memenab, // Memory enable input. q // Output of memory. (Required) ); // GLOBAL PARAMETER DECLARATION parameter lpm_width = 1; // Width of the q[] port. (Required) parameter lpm_widthad = 1; // Width of the address[] port. (Required) parameter lpm_numwords = 0; // Number of words stored in memory. parameter lpm_address_control = "REGISTERED"; // Indicates whether the address port is registered. parameter lpm_outdata = "REGISTERED"; // Indicates whether the q and eq ports are registered. parameter lpm_file = ""; // Name of the memory file containing ROM initialization data parameter intended_device_family = "Stratix"; parameter lpm_type = "lpm_rom"; parameter lpm_hint = "UNUSED"; // LOCAL_PARAMETERS_BEGIN parameter NUM_WORDS = (lpm_numwords == 0) ? (1 << lpm_widthad) : lpm_numwords; // LOCAL_PARAMETERS_END // INPUT PORT DECLARATION input [lpm_widthad-1:0] address; input inclock; input outclock; input memenab; // OUTPUT PORT DECLARATION output [lpm_width-1:0] q; // INTERNAL REGISTER/SIGNAL DECLARATION reg [lpm_width-1:0] mem_data [0:NUM_WORDS-1]; reg [lpm_widthad-1:0] address_reg; reg [lpm_width-1:0] tmp_q_reg; `ifdef VERILATOR reg [`LPM_MAX_NAME_SZ*8:1] rom_initf; `else reg [8*256:1] rom_initf; `endif // INTERNAL WIRE DECLARATION wire [lpm_widthad-1:0] w_address; wire [lpm_width-1:0] w_read_data; wire i_inclock; wire i_outclock; wire i_memenab; // LOCAL INTEGER DECLARATION integer i; // INTERNAL TRI DECLARATION tri0 inclock; tri0 outclock; tri1 memenab; buf (i_inclock, inclock); buf (i_outclock, outclock); buf (i_memenab, memenab); // COMPONENT INSTANTIATIONS LPM_DEVICE_FAMILIES dev (); LPM_MEMORY_INITIALIZATION mem (); // FUNCTON DECLARATION // Check the validity of the address. function ValidAddress; input [lpm_widthad-1:0] address; begin ValidAddress = 1'b0; if (^address == {lpm_widthad{1'bx}}) begin $display("%d:Error: Invalid address.", $time); $display("Time: %0t Instance: %m", $time); $finish; end else if (address >= NUM_WORDS) begin $display("%d:Error: Address out of bound on ROM.", $time); $display("Time: %0t Instance: %m", $time); $finish; end else ValidAddress = 1'b1; end endfunction // INITIAL CONSTRUCT BLOCK initial begin // Initialize output tmp_q_reg = {lpm_width{1'b0}}; address_reg = {lpm_widthad{1'b0}}; if (lpm_width <= 0) begin $display("Error! LPM_WIDTH parameter must be greater than 0."); $display("Time: %0t Instance: %m", $time); $finish; end if (lpm_widthad <= 0) begin $display("Error! LPM_WIDTHAD parameter must be greater than 0."); $display("Time: %0t Instance: %m", $time); $finish; end // check for number of words out of bound if ((NUM_WORDS > (1 << lpm_widthad)) || (NUM_WORDS <= (1 << (lpm_widthad-1)))) begin $display("Error! The ceiling of log2(LPM_NUMWORDS) must equal to LPM_WIDTHAD."); $display("Time: %0t Instance: %m", $time); $finish; end if ((lpm_address_control != "REGISTERED") && (lpm_address_control != "UNREGISTERED")) begin $display("Error! LPM_ADDRESS_CONTROL must be \"REGISTERED\" or \"UNREGISTERED\"."); $display("Time: %0t Instance: %m", $time); $finish; end if ((lpm_outdata != "REGISTERED") && (lpm_outdata != "UNREGISTERED")) begin $display("Error! LPM_OUTDATA must be \"REGISTERED\" or \"UNREGISTERED\"."); $display("Time: %0t Instance: %m", $time); $finish; end if (dev.IS_VALID_FAMILY(intended_device_family) == 0) begin $display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family); $display("Time: %0t Instance: %m", $time); $finish; end if (dev.FEATURE_FAMILY_MAX(intended_device_family) == 1) begin $display ("Error! LPM_ROM megafunction does not support %s devices.", intended_device_family); $display("Time: %0t Instance: %m", $time); $finish; end for (i = 0; i < NUM_WORDS; i=i+1) mem_data[i] = {lpm_width{1'b0}}; // load data to the ROM if ((lpm_file == "") || (lpm_file == "UNUSED")) begin $display("Warning: LPM_ROM must have data file for initialization.\n"); $display ("Time: %0t Instance: %m", $time); end else begin mem.convert_to_ver_file(lpm_file, lpm_width, rom_initf); $readmemh(rom_initf, mem_data); end end always @(posedge i_inclock) begin if (lpm_address_control == "REGISTERED") address_reg <= address; // address port is registered end always @(w_address or w_read_data) begin if (ValidAddress(w_address)) begin if (lpm_outdata == "UNREGISTERED") // Load the output register with the contents of the memory location // pointed to by address[]. tmp_q_reg <= w_read_data; end else begin if (lpm_outdata == "UNREGISTERED") tmp_q_reg <= {lpm_width{1'bx}}; end end always @(posedge i_outclock) begin if (lpm_outdata == "REGISTERED") begin if (ValidAddress(w_address)) tmp_q_reg <= w_read_data; else tmp_q_reg <= {lpm_width{1'bx}}; end end // CONTINOUS ASSIGNMENT assign w_address = (lpm_address_control == "REGISTERED") ? address_reg : address; assign w_read_data = mem_data[w_address]; assign q = (i_memenab) ? tmp_q_reg : {lpm_width{1'bz}}; endmodule // lpm_rom // END OF MODULE //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_fifo // // Description : // // Limitation : // // Results expected: // //END_MODULE_NAME-------------------------------------------------------------- `timescale 1 ps / 1 ps module lpm_fifo ( data, clock, wrreq, rdreq, aclr, sclr, q, usedw, full, empty ); // GLOBAL PARAMETER DECLARATION parameter lpm_width = 1; parameter lpm_widthu = 1; parameter lpm_numwords = 2; parameter lpm_showahead = "OFF"; parameter lpm_type = "lpm_fifo"; parameter lpm_hint = ""; // INPUT PORT DECLARATION input [lpm_width-1:0] data; input clock; input wrreq; input rdreq; input aclr; input sclr; // OUTPUT PORT DECLARATION output [lpm_width-1:0] q; output [lpm_widthu-1:0] usedw; output full; output empty; // INTERNAL REGISTERS DECLARATION reg [lpm_width-1:0] mem_data [(1< (1 << lpm_widthu))) begin $display ("Error! LPM_NUMWORDS must equal to the ceiling of log2(LPM_WIDTHU)."); $display("Time: %0t Instance: %m", $time); $stop; end if (lpm_numwords <= (1 << (lpm_widthu - 1))) begin $display ("Error! LPM_WIDTHU is too big for the specified LPM_NUMWORDS."); $display("Time: %0t Instance: %m", $time); $stop; end overflow_checking = eva.GET_PARAMETER_VALUE(lpm_hint, "OVERFLOW_CHECKING"); if(overflow_checking == "") overflow_checking = "ON"; else if ((overflow_checking != "ON") && (overflow_checking != "OFF")) begin $display ("Error! OVERFLOW_CHECKING must equal to either 'ON' or 'OFF'"); $display("Time: %0t Instance: %m", $time); $stop; end underflow_checking = eva.GET_PARAMETER_VALUE(lpm_hint, "UNDERFLOW_CHECKING"); if(underflow_checking == "") underflow_checking = "ON"; else if ((underflow_checking != "ON") && (underflow_checking != "OFF")) begin $display ("Error! UNDERFLOW_CHECKING must equal to either 'ON' or 'OFF'"); $display("Time: %0t Instance: %m", $time); $stop; end allow_rwcycle_when_full = eva.GET_PARAMETER_VALUE(lpm_hint, "ALLOW_RWCYCLE_WHEN_FULL"); if (allow_rwcycle_when_full == "") allow_rwcycle_when_full = "OFF"; else if ((allow_rwcycle_when_full != "ON") && (allow_rwcycle_when_full != "OFF")) begin $display ("Error! ALLOW_RWCYCLE_WHEN_FULL must equal to either 'ON' or 'OFF'"); $display("Time: %0t Instance: %m", $time); $stop; end intended_device_family = eva.GET_PARAMETER_VALUE(lpm_hint, "INTENDED_DEVICE_FAMILY"); if (intended_device_family == "") intended_device_family = "Stratix II"; else if (dev.IS_VALID_FAMILY(intended_device_family) == 0) begin $display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family); $display("Time: %0t Instance: %m", $time); $stop; end for (i = 0; i < (1<= ((1 << lpm_widthu) - 1)) begin if (lpm_showahead == "ON") tmp_q <= mem_data[0]; else tmp_q <= mem_data[read_id]; read_id <= 0; end else begin if (lpm_showahead == "ON") tmp_q <= mem_data[read_id + 1]; else tmp_q <= mem_data[read_id]; read_id <= read_id + 1; end end // WRITE operation only else if (valid_wreq) begin tmp_data <= data; empty_flag <= 1'b0; write_flag <= 1'b1; if (count_id >= (1 << lpm_widthu) - 1) count_id <= 0; else count_id <= count_id + 1; if ((count_id == lpm_numwords - 1) && (empty_flag == 1'b0)) full_flag <= 1'b1; if (lpm_showahead == "ON") tmp_q <= mem_data[read_id]; end // READ operation only else if (valid_rreq) begin full_flag <= 1'b0; if (count_id <= 0) count_id <= {lpm_widthu{1'b1}}; else count_id <= count_id - 1; if ((count_id == 1) && (full_flag == 1'b0)) empty_flag <= 1'b1; if (read_id >= ((1<= ((1 << lpm_widthu) - 1))) write_id <= 0; else write_id <= write_id + 1; end if ((lpm_showahead == "ON") && ($time > 0)) tmp_q <= ((write_flag == 1'b1) && (write_id == read_id)) ? tmp_data : mem_data[read_id]; end // @(negedge clock) // CONTINOUS ASSIGNMENT assign valid_rreq = (underflow_checking == "OFF") ? rdreq : rdreq && ~empty_flag; assign valid_wreq = (overflow_checking == "OFF") ? wrreq : (allow_rwcycle_when_full == "ON") ? wrreq && (!full_flag || rdreq) : wrreq && !full_flag; assign q = tmp_q; assign full = full_flag; assign empty = empty_flag; assign usedw = count_id; endmodule // lpm_fifo // END OF MODULE //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_fifo_dc_dffpipe // // Description : Dual Clocks FIFO // // Limitation : // // Results expected: // //END_MODULE_NAME-------------------------------------------------------------- // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module lpm_fifo_dc_dffpipe (d, clock, aclr, q); // GLOBAL PARAMETER DECLARATION parameter lpm_delay = 1; parameter lpm_width = 64; // INPUT PORT DECLARATION input [lpm_width-1:0] d; input clock; input aclr; // OUTPUT PORT DECLARATION output [lpm_width-1:0] q; // INTERNAL REGISTERS DECLARATION reg [lpm_width-1:0] dffpipe [lpm_delay:0]; reg [lpm_width-1:0] q; // LOCAL INTEGER DECLARATION integer delay; integer i; // INITIAL CONSTRUCT BLOCK initial begin delay <= lpm_delay - 1; for (i = 0; i <= lpm_delay; i = i + 1) dffpipe[i] <= 0; q <= 0; end // ALWAYS CONSTRUCT BLOCK always @(posedge aclr or posedge clock) begin if (aclr) begin for (i = 0; i <= lpm_delay; i = i + 1) dffpipe[i] <= 0; q <= 0; end else if (clock) begin if ((lpm_delay > 0) && ($time > 0)) begin `ifdef VERILATOR if (lpm_delay > 0) `else if (delay > 0) `endif begin `ifdef VERILATOR for (i = lpm_delay-1; i > 0; i = i - 1) `else for (i = delay; i > 0; i = i - 1) `endif dffpipe[i] <= dffpipe[i - 1]; q <= dffpipe[delay - 1]; end else q <= d; dffpipe[0] <= d; end end end // @(posedge aclr or posedge clock) always @(d) begin if (lpm_delay == 0) q <= d; end // @(d) endmodule // lpm_fifo_dc_dffpipe // END OF MODULE //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_fifo_dc_fefifo // // Description : Dual Clock FIFO // // Limitation : // // Results expected: // //END_MODULE_NAME-------------------------------------------------------------- // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module lpm_fifo_dc_fefifo ( usedw_in, wreq, rreq, clock, aclr, empty, full); // GLOBAL PARAMETER DECLARATION parameter lpm_widthad = 1; parameter lpm_numwords = 1; parameter underflow_checking = "ON"; parameter overflow_checking = "ON"; parameter lpm_mode = "READ"; parameter lpm_hint = ""; // INPUT PORT DECLARATION input [lpm_widthad-1:0] usedw_in; input wreq; input rreq; input clock; input aclr; // OUTPUT PORT DECLARATION output empty; output full; // INTERNAL REGISTERS DECLARATION reg [1:0] sm_empty; reg lrreq; reg i_empty; reg i_full; reg [8*5:1] i_overflow_checking; reg [8*5:1] i_underflow_checking; // LOCAL INTEGER DECLARATION integer almostfull; // COMPONENT INSTANTIATIONS LPM_HINT_EVALUATION eva(); // INITIAL CONSTRUCT BLOCK initial begin if ((lpm_mode != "READ") && (lpm_mode != "WRITE")) begin $display ("Error! LPM_MODE must be READ or WRITE."); $display("Time: %0t Instance: %m", $time); $stop; end i_overflow_checking = eva.GET_PARAMETER_VALUE(lpm_hint, "OVERFLOW_CHECKING"); if (i_overflow_checking == "") begin if ((overflow_checking != "ON") && (overflow_checking != "OFF")) begin $display ("Error! OVERFLOW_CHECKING must equal to either 'ON' or 'OFF'"); $display("Time: %0t Instance: %m", $time); $stop; end else i_overflow_checking = overflow_checking; end else if ((i_overflow_checking != "ON") && (i_overflow_checking != "OFF")) begin $display ("Error! OVERFLOW_CHECKING must equal to either 'ON' or 'OFF'"); $display("Time: %0t Instance: %m", $time); $stop; end i_underflow_checking = eva.GET_PARAMETER_VALUE(lpm_hint, "UNDERFLOW_CHECKING"); if(i_underflow_checking == "") begin if ((underflow_checking != "ON") && (underflow_checking != "OFF")) begin $display ("Error! UNDERFLOW_CHECKING must equal to either 'ON' or 'OFF'"); $display("Time: %0t Instance: %m", $time); $stop; end else i_underflow_checking = underflow_checking; end else if ((i_underflow_checking != "ON") && (i_underflow_checking != "OFF")) begin $display ("Error! UNDERFLOW_CHECKING must equal to either 'ON' or 'OFF'"); $display("Time: %0t Instance: %m", $time); $stop; end sm_empty <= 2'b00; i_empty <= 1'b1; i_full <= 1'b0; lrreq <= 1'b0; if (lpm_numwords >= 3) almostfull <= lpm_numwords - 3; else almostfull <= 0; end // ALWAYS CONSTRUCT BLOCK always @(posedge aclr) begin sm_empty <= 2'b00; i_empty <= 1'b1; i_full <= 1'b0; lrreq <= 1'b0; end // @(posedge aclr) always @(posedge clock) begin if (i_underflow_checking == "OFF") lrreq <= rreq; else lrreq <= rreq && ~i_empty; if (~aclr && ($time > 0)) begin if (lpm_mode == "READ") begin // verilator lint_off CASEX casex (sm_empty) // verilator lint_on CASEX // state_empty 2'b00: if (usedw_in != 0) sm_empty <= 2'b01; // state_non_empty // verilator lint_off CMPCONST 2'b01: if (rreq && (((usedw_in == 1) && !lrreq) || ((usedw_in == 2) && lrreq))) sm_empty <= 2'b10; // state_emptywait 2'b10: if (usedw_in > 1) sm_empty <= 2'b01; else sm_empty <= 2'b00; // verilator lint_on CMPCONST default: begin $display ("Error! Invalid sm_empty state in read mode."); $display("Time: %0t Instance: %m", $time); end endcase end // if (lpm_mode == "READ") else if (lpm_mode == "WRITE") begin // verilator lint_off CASEX casex (sm_empty) // verilator lint_on CASEX // state_empty 2'b00: if (wreq) sm_empty <= 2'b01; // state_one 2'b01: if (!wreq) sm_empty <= 2'b11; // state_non_empty 2'b11: if (wreq) sm_empty <= 2'b01; else if (usedw_in == 0) sm_empty <= 2'b00; default: begin $display ("Error! Invalid sm_empty state in write mode."); $display("Time: %0t Instance: %m", $time); end endcase end // if (lpm_mode == "WRITE") if (~aclr && (usedw_in >= almostfull) && ($time > 0)) i_full <= 1'b1; else i_full <= 1'b0; end // if (~aclr && $time > 0) end // @(posedge clock) always @(sm_empty) begin i_empty <= !sm_empty[0]; end // @(sm_empty) // CONTINOUS ASSIGNMENT assign empty = i_empty; assign full = i_full; endmodule // lpm_fifo_dc_fefifo // END OF MODULE //START_MODULE_NAME------------------------------------------------------------ // // Module Name : lpm_fifo_dc_async // // Description : Asynchronous Dual Clocks FIFO // // Limitation : // // Results expected: // //END_MODULE_NAME-------------------------------------------------------------- // BEGINNING OF MODULE `timescale 1 ps / 1 ps // MODULE DECLARATION module lpm_fifo_dc_async ( data, rdclk, wrclk, aclr, rdreq, wrreq, rdfull, wrfull, rdempty, wrempty, rdusedw, wrusedw, q); // GLOBAL PARAMETER DECLARATION parameter lpm_width = 1; parameter lpm_widthu = 1; parameter lpm_numwords = 2; parameter delay_rdusedw = 1; parameter delay_wrusedw = 1; parameter rdsync_delaypipe = 3; parameter wrsync_delaypipe = 3; parameter lpm_showahead = "OFF"; parameter underflow_checking = "ON"; parameter overflow_checking = "ON"; parameter lpm_hint = "INTENDED_DEVICE_FAMILY=Stratix"; // INPUT PORT DECLARATION input [lpm_width-1:0] data; input rdclk; input wrclk; input aclr; input wrreq; input rdreq; // OUTPUT PORT DECLARATION output rdfull; output wrfull; output rdempty; output wrempty; output [lpm_widthu-1:0] rdusedw; output [lpm_widthu-1:0] wrusedw; output [lpm_width-1:0] q; // INTERNAL REGISTERS DECLARATION reg [lpm_width-1:0] mem_data [(1< 0)) begin i_data_tmp <= data; i_wrptr_tmp <= i_wrptr; i_wren_tmp <= w_wren; if (w_wren) begin if (~aclr && ((i_wrptr < (1< 0)) begin if (i_wren_tmp) begin mem_data[i_wrptr_tmp] <= i_data_tmp; end if (lpm_showahead == "ON") i_showahead_flag1 <= 1'b1; end end // @(negedge wrclk) always @(posedge rdclk) begin if (aclr && (!(dev.FEATURE_FAMILY_BASE_STRATIX(intended_device_family) || dev.FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)) || (use_eab == "OFF"))) begin if (lpm_showahead == "ON") i_q_tmp <= mem_data[0]; else i_q_tmp <= 0; end else if (rdclk && w_rden && ($time > 0)) begin if (~aclr && ((i_rdptr < (1<call_task();"); `else call_task(); `endif end else if (cyc==10) begin $write("*-* All Finished *-*\n"); $finish; end end end task call_task; /* verilator public */ t1.center_task(1'b1); endtask endmodule module alpha (/*AUTOARG*/ // Inputs clk, toggle ); input clk; input toggle; always @ (posedge clk) begin if (toggle) begin // CHECK_COVER(0,"top.t.a*",18) $write(""); // t.a1 and t.a2 collapse to a count of 2 end if (toggle) begin // *** t_cover_line.vlt turns this off $write(""); // CHECK_COVER_MISSING(0) // This doesn't even get added `ifdef ATTRIBUTE // verilator coverage_block_off `endif end end endmodule module beta (/*AUTOARG*/ // Inputs clk, toggle ); input clk; input toggle; /* verilator public_module */ always @ (posedge clk) begin $write(""); // Always covered if (0) begin // CHECK_COVER(0,"top.t.b*",0) // Make sure that we don't optimize away zero buckets $write(""); end if (toggle) begin // CHECK_COVER(0,"top.t.b*",2) // t.b1 and t.b2 collapse to a count of 2 $write(""); end if (toggle) begin : block // This doesn't `ifdef ATTRIBUTE // verilator coverage_block_off `endif begin end // *** t_cover_line.vlt turns this off (so need begin/end) if (1) begin end // CHECK_COVER_MISSING(0) $write(""); // CHECK_COVER_MISSING(0) end end endmodule class Cls; bit m_toggle; function new(bit toggle); m_toggle = toggle; if (m_toggle) begin // CHECK_COVER(0,"top.$unit::Cls",1) $write(""); end endfunction static function void fstatic(bit toggle); if (1) begin // CHECK_COVER(0,"top.$unit::Cls",1) $write(""); end endfunction function void fauto(); if (m_toggle) begin // CHECK_COVER(0,"top.$unit::Cls",11) $write(""); end endfunction endclass module tsk (/*AUTOARG*/ // Inputs clk, toggle ); input clk; input toggle; /* verilator public_module */ always @ (posedge clk) begin center_task(1'b0); end task automatic center_task; input external; begin if (toggle) begin // CHECK_COVER(0,"top.t.t1",1) $write(""); end if (external) begin // CHECK_COVER(0,"top.t.t1",1) $write("[%0t] Got external pulse\n", $time); end end begin Cls c; c = new(1'b1); c.fauto(); Cls::fstatic(1'b1); end endtask endmodule module off (/*AUTOARG*/ // Inputs clk, toggle ); input clk; input toggle; // verilator coverage_off always @ (posedge clk) begin if (toggle) begin $write(""); // CHECK_COVER_MISSING(0) // because under coverage_module_off end end // verilator coverage_on always @ (posedge clk) begin if (toggle) begin // because under coverage_module_off $write(""); if (0) ; // CHECK_COVER(0,"top.t.o1",1) end end endmodule module tab (input clk); bit [3:0] cyc4; int decoded; always @ (posedge clk) begin case (cyc4) 1: decoded = 10; 2: decoded = 20; 3: decoded = 30; 4: decoded = 40; 5: decoded = 50; default: decoded = 0; endcase end always @ (posedge clk) begin cyc4 <= cyc4 + 1; end endmodule module par(); localparam int CALLS_FUNC = param_func(1); // We don't currently count elaboration time use towards coverage. This // seems safer for functions used both at elaboration time and not - but may // revisit this. function automatic int param_func(int i); if (i == 0) begin i = 99; // Uncovered end else begin i = i + 1; end return i; endfunction endmodule package my_pkg; int x = 1 ? 1 : 0; endpackage class Getter1; function int get_1; return 1; endfunction endclass module cond(input logic clk, input int cyc); logic a, b, c, d, e, f, g, h, k, l, m; logic [5:0] tab; typedef logic [7:0] arr_t[1:0]; arr_t data[1:0]; Getter1 getter1 = new; string s; function logic func_side_effect; $display("SIDE EFFECT"); return 1; endfunction function arr_t get_arr; arr_t arr; return arr; endfunction assign a = (cyc == 0) ? clk : 1'bz; assign b = (cyc == 1) ? clk : 0; assign c = func_side_effect() ? clk : 0; always @(posedge clk) begin d = (cyc % 3 == 0) ? 1 : 0; s = (getter1.get_1() == 0) ? "abcd" : $sformatf("%d", getter1.get_1()[4:0]); end assign e = (cyc % 3 == 1) ? (clk ? 1 : 0) : 1; // ternary operator in condition shouldn't be included to the coverae assign f = (cyc != 0 ? 1 : 0) ? 1 : 0; // the same as in index assign tab[clk ? 1 : 0] = 1; assign m = tab[clk ? 3 : 4]; for (genvar i = 0; i < 2; i++) begin assign g = clk ? 1 : 0; end always begin if (cyc == 5) h = cyc > 5 ? 1 : 0; else h = 1; data[0] = (cyc == 2) ? '{8'h01, 8'h02} : get_arr(); // ternary operator in conditions should be skipped for (int i = 0; (i < 5) ? 1 : 0; i++) begin k = 1'(i); end for (int i = 0; i < 7; i = (i > 4) ? i + 1 : i + 2) begin k = 1'(i); end if (k ? 1 : 0) k = 1; else k = 0; end endmodule verilator-5.042/test_regress/t/t_struct_pat_toomany_bad.out0000644000542200017500000000055115101701376024707 0ustar mahmoudyfreeshell%Error: t/t_struct_pat_toomany_bad.v:12:18: Assignment pattern contains more entries than structure members : ... note: In instance 't' 12 | } sp = '{1, 2, 3}; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_unroll_automatic_task_fork.py0000755000542200017500000000103515101701376025411 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--binary']) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_func_nvoid_bad.py0000755000542200017500000000076615101701376024124 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_packed_concat_bad.py0000755000542200017500000000076615101701376023363 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface_top_bad.py0000755000542200017500000000076615101701376023427 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_mem_twoedge.v0000644000542200017500000000570615101701376022104 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // verilator lint_off MULTIDRIVEN /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [31:0] out; // From test of Test.v wire [15:0] out2; // From test of Test.v // End of automatics // verilator lint_on MULTIDRIVEN Test test ( .en (crc[21:20]), .a1 (crc[19:18]), .a0 (crc[17:16]), .d1 (crc[15:8]), .d0 (crc[7:0]), /*AUTOINST*/ // Outputs .out (out[31:0]), .out2 (out2[15:0]), // Inputs .clk (clk)); // Aggregate outputs into a single result vector wire [63:0] result = {out2, 16'h0, out}; // Test loop `ifdef TEST_VERBOSE always @ (negedge clk) begin $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); end `endif always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; test.clear(); end else if (cyc<10) begin sum <= 64'h0; test.clear(); end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'hc68a94a34ec970aa if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test (/*AUTOARG*/ // Outputs out, out2, // Inputs clk, en, a0, a1, d0, d1 ); input clk; input [1:0] en; input [1:0] a0; input [1:0] a1; input [7:0] d0; input [7:0] d1; output reg [31:0] out; // verilator lint_off MULTIDRIVEN output reg [15:0] out2; reg [7:0] mem [4]; // verilator lint_on MULTIDRIVEN task clear(); for (int i=0; i<4; ++i) mem[i] = 0; endtask always @(posedge clk) begin if (en[0]) begin mem[a0] <= d0; out2[7:0] <= d0; end end always @(negedge clk) begin if (en[1]) begin mem[a1] <= d1; out2[15:8] <= d0; end end assign out = {mem[3],mem[2],mem[1],mem[0]}; endmodule verilator-5.042/test_regress/t/t_udp_bad.py0000755000542200017500000000110115101701376021355 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["--lint-only --bbox-unsup"], fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_opt_life.v0000644000542200017500000000607615101701376021412 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc=1; // Life analysis checks reg [15:0] life; // Ding case reg [7:0] din; reg [15:0] fixin; always @* begin fixin = {din[7:0],din[7:0]}; case (din[1:0]) 2'b00: begin fixin = {fixin[14:0], 1'b1}; if (cyc==101) $display("Prevent ?: optimization a"); end 2'b01: begin fixin = {fixin[13:0], 2'b11}; if (cyc==101) $display("Prevent ?: optimization b"); end 2'b10: begin fixin = {fixin[12:0], 3'b111}; if (cyc==101) $display("Prevent ?: optimization c"); end 2'b11: begin fixin = {fixin[11:0], 4'b1111}; if (cyc==101) $display("Prevent ?: optimization d"); end endcase end // Remove CResets function int f(int in); automatic int aut; aut = in; return aut; endfunction always @ (posedge clk) begin if (cyc!=0) begin cyc<=cyc+1; if (cyc==1) begin life = 16'h8000; // Dropped life = 16'h0010; // Used below if (life != 16'h0010) $stop; // life = 16'h0020; // Used below if ($time < 10000) if (life != 16'h0020) $stop; // life = 16'h8000; // Dropped if ($time > 100000) begin if ($time != 0) $stop; // Prevent conversion to ?: life = 16'h1030; end else life = 16'h0030; if (life != 16'h0030) $stop; // life = 16'h0040; // Not dropped, no else below if ($time > 100000) life = 16'h1040; if (life != 16'h0040) $stop; // life = 16'h8000; // Dropped if ($time > 100000) begin life = 16'h1050; if (life != 0) $stop; // Ignored, as set is first end else begin if ($time > 100010) life = 16'h1050; else life = 16'h0050; end if (life != 16'h0050) $stop; end if (cyc==2) begin din <= 8'haa; end if (cyc==3) begin din <= 8'hfb; if (fixin != 16'h5557) $stop; end if (cyc==4) begin din <= 8'h5c; if (fixin != 16'hbfbf) $stop; end if (cyc==5) begin din <= 8'hed; if (fixin != 16'hb8b9) $stop; end if (cyc==6) begin if (fixin != 16'hb7b7) $stop; end if (cyc==8) begin if (f(123) != 123) $stop; end if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule verilator-5.042/test_regress/t/t_lint_always_comb_iface.py0000755000542200017500000000070615101701376024446 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.042/test_regress/t/t_timing_osc.py0000755000542200017500000000112515101701376022120 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary --trace-vcd"], make_main=False) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_gen_defparam_nfound_bad.py0000755000542200017500000000076315101701376024563 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_disable_fork2_split.py0000755000542200017500000000113715101701376023711 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t_disable_fork2.v" # Validate if splitted functions get vlProcess handle test.compile(verilator_flags2=["--timing --output-split-cfuncs 1"]) test.passes() verilator-5.042/test_regress/t/t_display_io.py0000755000542200017500000000073415101701376022126 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_gen_for_overlap.v0000644000542200017500000000207015101701376022746 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2014 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // bug749 module t (/*AUTOARG*/ // Inputs clk ); input clk; genvar g; for (g=1; g<3; ++g) begin : gblk sub2 #(.IN(g)) u (); //sub #(.IN(g)) u2 (); end sub1 #(.IN(0)) u (); always @ (posedge clk) begin if (t.u.IN != 0) $stop; if (t.u.FLAVOR != 1) $stop; //if (t.u2.IN != 0) $stop; // This should be not found if (t.gblk[1].u.IN != 1) $stop; if (t.gblk[2].u.IN != 2) $stop; if (t.gblk[1].u.FLAVOR != 2) $stop; if (t.gblk[2].u.FLAVOR != 2) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module sub1; parameter [31:0] IN = 99; parameter FLAVOR = 1; `ifdef TEST_VERBOSE initial $display("%m"); `endif endmodule module sub2; parameter [31:0] IN = 99; parameter FLAVOR = 2; `ifdef TEST_VERBOSE initial $display("%m"); `endif endmodule verilator-5.042/test_regress/t/t_json_only_first.v0000644000542200017500000000173015101701376023022 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs q, // Inputs clk, d ); input clk; input [3:0] d; output wire [3:0] q; logic [3:0] between; mod1 #(.WIDTH(4)) cell1 (.q(between), .clk (clk), .d (d[3:0])); mod2 cell2 (.d(between), .q (q[3:0]), .clk (clk)); endmodule module mod1 #(parameter WIDTH = 32) ( input clk, input [WIDTH-1:0] d, output logic [WIDTH-1:0] q ); localparam IGNORED = 1; always @(posedge clk) q <= d; endmodule module mod2 ( input clk, input [3:0] d, output wire [3:0] q ); assign q = d; endmodule verilator-5.042/test_regress/t/t_sys_readmem_4state.v0000644000542200017500000000133015101701376023371 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" module t; reg [3:0] MEMB [6]; reg [3:0] MEMH [6]; initial begin $readmemb("t/t_sys_readmem_4state.mem", MEMB); $display("MEMB=%p", MEMB); $writememh({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_readmem_4state_b.mem"}, MEMB); $readmemh("t/t_sys_readmem_4state.mem", MEMH); $display("MEMH=%p", MEMH); $writememh({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_readmem_4state_h.mem"}, MEMH); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_mem_iforder.v0000644000542200017500000000507115101701376022073 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc = 0; reg [63:0] crc; reg [31:0] sum; wire [15:0] out0; wire [15:0] out1; wire [15:0] inData = crc[15:0]; wire wr0a = crc[16]; wire wr0b = crc[17]; wire wr1a = crc[18]; wire wr1b = crc[19]; fifo fifo ( // Outputs .out0 (out0[15:0]), .out1 (out1[15:0]), // Inputs .clk (clk), .wr0a (wr0a), .wr0b (wr0b), .wr1a (wr1a), .wr1b (wr1b), .inData (inData[15:0])); always @ (posedge clk) begin //$write("[%0t] cyc==%0d crc=%x q=%x\n", $time, cyc, crc, sum); cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 32'h0; end else if (cyc>10 && cyc<90) begin sum <= {sum[30:0],sum[31]} ^ {out1, out0}; end else if (cyc==99) begin if (sum !== 32'he8bbd130) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module fifo (/*AUTOARG*/ // Outputs out0, out1, // Inputs clk, wr0a, wr0b, wr1a, wr1b, inData ); input clk; input wr0a; input wr0b; input wr1a; input wr1b; input [15:0] inData; output [15:0] out0; output [15:0] out1; reg [15:0] mem [1:0]; reg [15:0] memtemp2 [1:0]; reg [15:0] memtemp3 [1:0]; assign out0 = {mem[0] ^ memtemp2[0]}; assign out1 = {mem[1] ^ memtemp3[1]}; always @(posedge clk) begin // These mem assignments must be done in order after processing if (wr0a) begin memtemp2[0] <= inData; mem[0] <= inData; end if (wr0b) begin memtemp3[0] <= inData; mem[0] <= ~inData; end if (wr1a) begin memtemp3[1] <= inData; mem[1] <= inData; end if (wr1b) begin memtemp2[1] <= inData; mem[1] <= ~inData; end end endmodule verilator-5.042/test_regress/t/t_class_param_mod.py0000755000542200017500000000073415101701376023116 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_func_return_bad.py0000755000542200017500000000076615101701376023137 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_implements_noninterface_bad.v0000644000542200017500000000060315101701376025315 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class NotIcls; endclass class ClsBad1 implements NotIcls; endclass interface class Icls; endclass class ClsBad2 extends Icls; endclass module t; ClsBad2 c; endmodule verilator-5.042/test_regress/t/t_pp_circ_subst_bad.v0000644000542200017500000000035215101701376023245 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define e fun `e `e verilator-5.042/test_regress/t/t_func_rand.cpp0000644000542200017500000000155115101701376022056 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include VM_PREFIX_INCLUDE double sc_time_stamp() { return 0; } int main(int argc, char* argv[]) { Verilated::debug(0); Verilated::commandArgs(argc, argv); VM_PREFIX* topp = new VM_PREFIX; printf("\nTesting\n"); for (int i = 0; i < 10; i++) { topp->clk = 0; topp->eval(); topp->clk = 1; topp->eval(); } if (topp->Rand != 0xfeed0fad) { vl_fatal(__FILE__, __LINE__, "top", "Unexpected value for Rand output\n"); } topp->final(); VL_DO_DANGLING(delete topp, topp); printf("*-* All Finished *-*\n"); } verilator-5.042/test_regress/t/t_package_import_param.py0000755000542200017500000000070615101701376024136 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.042/test_regress/t/t_wait_no_triggered_bad.py0000755000542200017500000000102515101701376024266 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=['--timing'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_flag_compiler_gcc.py0000755000542200017500000000105115101701376023402 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_flag_compiler.v" test.compile(verilator_flags2=["--compiler gcc"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_gate_delay_unsup.out0000644000542200017500000000066215101701376023476 0ustar mahmoudyfreeshell%Warning-RISEFALLDLY: t/t_gate_basic.v:26:12: Unsupported: rising/falling/turn-off delays. Using the first delay 26 | nand #(2,3) ND0 (nd0, a[0], b[0], b[1]); | ^ ... For warning description see https://verilator.org/warn/RISEFALLDLY?v=latest ... Use "/* verilator lint_off RISEFALLDLY */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_flag_verilate_threads_bad.py0000755000542200017500000000110315101701376025105 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_flag_werror.v" test.lint(fails=True, verilator_flags=["--verilate-jobs -1"], expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_extends_nf_bad.py0000755000542200017500000000076615101701376024127 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_package_dot.v0000644000542200017500000000106615101701376022044 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2015 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package pkg; typedef struct packed { logic [3:0] msk; logic [3:0] dat; } STR_t; endpackage; package csr_pkg; typedef pkg::STR_t reg_t; localparam reg_t REG_RST = 8'h34; endpackage module t; initial begin if (csr_pkg::REG_RST.msk != 4'h3) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_constraint_operators.py0000755000542200017500000000104615101701376024251 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_struct_assign.v0000644000542200017500000000140615101701376022471 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t; typedef struct { int fst, snd; } pair_t; class Cls; pair_t p; endclass pair_t a, b; Cls c = new; initial begin a.fst = 1; a.snd = 2; b.fst = 3; b.snd = 4; a = b; $display("(%d, %d) (%d, %d)", a.fst, a.snd, b.fst, b.snd); $display("%%p=%p", a); c.p.fst = 5; if (c.p.fst != 5) $stop; a = c.p; if (a.fst != 5) $stop; c.p = b; if (c.p.fst != 3) $stop; if (c.p.snd != 4) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_math_shift_huge.v0000644000542200017500000000070715101701376022742 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Outputs outl, outr, // Inputs lhs ); input [95:0] lhs; output [95:0] outl; output [95:0] outr; assign outl = lhs << 95'hffff_00000000; assign outr = lhs >> 95'hffff_00000000; endmodule verilator-5.042/test_regress/t/t_tri_dangle.py0000755000542200017500000000100515101701376022072 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(all_run_flags=['+verilator+rand+reset+0']) test.passes() verilator-5.042/test_regress/t/t_force_rhs_ref.py0000755000542200017500000000076315101701376022602 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_iface_array_topmodule3.v0000644000542200017500000000342115101701376025246 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Josh Redford. // SPDX-License-Identifier: CC0-1.0 interface my_if #( parameter integer DW = 8 ) (input clk); localparam DW_LOCAL = DW; logic valid; logic [DW-1:0] data; modport slave_mp ( input valid, input data ); modport master_mp ( output valid, output data ); function automatic integer width(); return $bits(data); endfunction generate if (DW < 4) begin: dw_lt_4_G function automatic integer min_width(); return 4; endfunction end else begin: dw_ge_4_G function automatic integer min_width(); return 8; endfunction end endgenerate endinterface module t ( input wire clk, my_if in_if [2], my_if out_if [2] ); assign out_if[0].valid = in_if[0].valid; assign out_if[0].data = in_if[0].data; assign out_if[1].valid = in_if[1].valid; assign out_if[1].data = in_if[1].data; my_if my_i (.clk(clk)); initial begin $display(in_if[0].DW_LOCAL); $display(in_if[0].width()); $display(in_if[0].dw_ge_4_G.min_width()); $display(out_if[0].DW_LOCAL); $display(out_if[0].width()); $display(out_if[0].dw_ge_4_G.min_width()); $display(in_if[1].DW_LOCAL); $display(in_if[1].width()); $display(in_if[1].dw_ge_4_G.min_width()); $display(out_if[1].DW_LOCAL); $display(out_if[1].width()); $display(out_if[1].dw_ge_4_G.min_width()); end endmodule verilator-5.042/test_regress/t/t_array_query_with.py0000755000542200017500000000077115101701376023371 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--assert']) test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_colon_bad.py0000755000542200017500000000076615101701376023737 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_trace_array_fst_threads_2.py0000755000542200017500000000131615101701376025072 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_trace_array.v" test.golden_filename = "t/t_trace_array_fst.out" test.compile( verilator_flags2=['--cc --trace-fst --trace-threads 2 --trace-structs --trace-max-width 0']) test.execute() test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_struct_unused.py0000755000542200017500000000126115101701376022675 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') # Use --debug-protect to assist debug test.compile() test.execute() if test.vlt_all: # Check for unused structs in any outputs for filename in test.glob_some(test.obj_dir + "/*.[ch]*"): test.file_grep_not(filename, r'useless') test.passes() verilator-5.042/test_regress/t/t_interface_dearray.v0000644000542200017500000000166315101701376023255 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface A; endinterface typedef virtual A a_t; typedef a_t a_array_t[6]; class B; function new(virtual A va); endfunction endclass class C; a_array_t vif; function void set(int index, a_t iface); vif[index] = iface; endfunction endclass module tb_top(); A a[6](); C c, d, e; a_array_t g; initial begin static a_t aa = a[0]; B b = new(a[0]); c = new(); c.vif = a; d = new(); d.set(0, a[0]); d.vif[1] = a[1]; g[0] = a[0]; g = a; d.vif[0] = g[0]; d.vif = g; e = new(); for (int i = 0; i < 6; ++i) begin e.vif[i] = g[i]; end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_enum_type_bad.v0000644000542200017500000000127515101701376022420 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; typedef enum {ZERO, ONE, TWO} e_t; typedef enum {THREE=3, FOUR, FIVE} o_t; typedef struct packed { e_t m_e; o_t m_o; } struct_t; initial begin e_t e; o_t o; struct_t str; e = ONE; e = $random() == 0 ? ONE : TWO; e = e_t'(1); e = e; e = 1; // Bad o = e; // Bad str.m_e = ONE; str.m_o = THREE; e = str.m_e; o = str.m_o; o = str.m_e; // Bad end endmodule verilator-5.042/test_regress/t/t_unroll_stmt.v0000644000542200017500000000343715101701376022171 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; int static_loop_cond; function logic f_loop_cond(); return ++static_loop_cond < 8; endfunction initial begin // Basic loop for (int i = 0; i < 3; ++i) begin : loop_0 $display("loop_0 %0d", i); end // Loop with 2 init/step for (int i = 0, j = 5; i < j; i += 2, j += 1) begin : loop_1 $display("loop_1 %0d %0d", i, j); end // While loop with non-trivial init begin automatic int i = 0; automatic int j = 5; // Not a variable while (i < j) begin : loop_2 $display("loop_2 %0d %0d", i++, j); end end // Do loop with non-trivial init begin automatic int i = 5; automatic int j = 0; // Not a variable do begin : loop_3 $display("loop_3 %0d %0d", --i, j); end while (i > j); end // Do loop that executes once - replaced by V3Const, not unrolled do begin: loop_4 $display("loop_4"); end while(0); // Loop with inlined function as condition static_loop_cond = 0; while (f_loop_cond()) begin : loop_5 $display("loop_5 %0d", static_loop_cond); end // Self disabling loop in via 'then' branch of 'if' begin automatic logic found = 0; for (int i = 0; i < 10; ++i) begin : loop_6 if (!found) begin $display("loop_6 %0d", i); if (i == $c32("5")) begin // Unknown condition $display("stopping loop_6"); // This line is important found = 1; end end end end // Done $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_order_dpi_export_1.v0000644000542200017500000000172015101701376023370 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2021 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module testbench; logic clk; export "DPI-C" function set_clk; function void set_clk(bit val); clk = val; endfunction; // Downstream signal dependent on clk demonstrates scheduling issue. // The '$c("1") &' ensures that dependent_clk does not get // replaced with clk early and hence hiding the issue wire dependent_clk = $c1("1") & clk; int n = 0; always @(posedge dependent_clk) begin $display("t=%t n=%d", $time, n); if ($time != (2*n+1) * 500) $stop; if (n == 20) begin $write("*-* All Finished *-*\n"); $finish; end n += 1; end endmodule verilator-5.042/test_regress/t/t_vpi_var2.py0000755000542200017500000000160615101701376021521 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.pli_filename = "t/t_vpi_var.cpp" test.compile(make_top_shell=False, make_main=False, make_pli=True, sim_time=2100, iv_flags2=["-g2005-sv -D USE_VPI_NOT_DPI -DWAVES -DT_VPI_VAR2"], v_flags2=["+define+USE_VPI_NOT_DPI"], verilator_flags2=["-Wno-SYMRSVDWORD --exe --vpi --no-l2name", test.pli_filename]) test.execute(use_libvpi=True, all_run_flags=['+PLUS +INT=1234 +STRSTR']) test.passes() verilator-5.042/test_regress/t/t_package.v0000644000542200017500000000313015101701376021170 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef int unit_type_t; function [3:0] unit_plusone(input [3:0] i); unit_plusone = i+1; endfunction package p; typedef int package_type_t; integer pi = 123; function [3:0] plusone(input [3:0] i); plusone = i+1; endfunction endpackage package p2; typedef int package2_type_t; function [3:0] plustwo(input [3:0] i); plustwo = i+2; endfunction function automatic bit realCompare(real r); logic [63:0] b = $realtobits(r); return b > 0; endfunction endpackage module t (/*AUTOARG*/ // Inputs clk ); input clk; unit_type_t vu; $unit::unit_type_t vdu; p::package_type_t vp; t2 t2 (); initial begin if (unit_plusone(1) !== 2) $stop; if ($unit::unit_plusone(1) !== 2) $stop; if (p::plusone(1) !== 2) $stop; p::pi = 124; if (p::pi !== 124) $stop; $write("*-* All Finished *-*\n"); $finish; end always @ (posedge clk) begin p::pi += 1; if (p::pi < 124) $stop; end endmodule module t2; import p::*; import p2::plustwo; import p2::realCompare; import p2::package2_type_t; package_type_t vp; package2_type_t vp2; initial begin bit x = realCompare(1.0); if (plusone(1) !== 2) $stop; if (plustwo(1) !== 3) $stop; if (p::pi !== 123 && p::pi !== 124) $stop; // may race with other initial, so either value end endmodule verilator-5.042/test_regress/t/t_tri_struct.py0000755000542200017500000000077415101701376022200 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.compile(verilator_flags2=['--binary']) test.execute() test.passes() verilator-5.042/test_regress/t/t_gen_for0.v0000644000542200017500000000170615101701376021303 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; Testit testit (/*AUTOINST*/ // Inputs .clk (clk)); always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==0) begin end else if (cyc<10) begin end else if (cyc<90) begin end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module Testit (clk); input clk; genvar igen; generate for (igen=0; igen<0; igen=igen+1) begin : test_gen always @ (posedge clk) begin $display("igen1 = %d", igen); $stop; end end endgenerate endmodule verilator-5.042/test_regress/t/t_tri_eqcase.v0000644000542200017500000000772015101701376021725 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; wire [3:0] drv_a = crc[3:0]; wire [3:0] drv_b = crc[7:4]; wire [3:0] drv_e = crc[19:16]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [8:0] match1; // From test1 of Test1.v wire [8:0] match2; // From test2 of Test2.v // End of automatics Test1 test1 (/*AUTOINST*/ // Outputs .match1 (match1[8:0]), // Inputs .drv_a (drv_a[3:0]), .drv_e (drv_e[3:0])); Test2 test2 (/*AUTOINST*/ // Outputs .match2 (match2[8:0]), // Inputs .drv_a (drv_a[3:0]), .drv_e (drv_e[3:0])); // Aggregate outputs into a single result vector wire [63:0] result = {39'h0, match2, 7'h0, match1}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x m1=%x m2=%x (%b??%b:%b)\n", $time, cyc, crc, match1, match2, drv_e,drv_a,drv_b); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; end else if (cyc<10) begin sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'hc0c4a2b9aea7c4b4 if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test1 ( input wire [3:0] drv_a, input wire [3:0] drv_e, output wire [8:0] match1 ); wire [2:1] drv_all; bufif1 bufa [2:1] (drv_all, drv_a[2:1], drv_e[2:1]); `ifdef VERILATOR // At present Verilator only allows comparisons with Zs assign match1[0] = (drv_a[2:1]== 2'b00 && drv_e[2:1]==2'b11); assign match1[1] = (drv_a[2:1]== 2'b01 && drv_e[2:1]==2'b11); assign match1[2] = (drv_a[2:1]== 2'b10 && drv_e[2:1]==2'b11); assign match1[3] = (drv_a[2:1]== 2'b11 && drv_e[2:1]==2'b11); `else assign match1[0] = drv_all === 2'b00; assign match1[1] = drv_all === 2'b01; assign match1[2] = drv_all === 2'b10; assign match1[3] = drv_all === 2'b11; `endif assign match1[4] = drv_all === 2'bz0; assign match1[5] = drv_all === 2'bz1; assign match1[6] = drv_all === 2'bzz; assign match1[7] = drv_all === 2'b0z; assign match1[8] = drv_all === 2'b1z; endmodule module Test2 ( input wire [3:0] drv_a, input wire [3:0] drv_e, output wire [8:0] match2 ); wire [2:1] drv_all; bufif1 bufa [2:1] (drv_all, drv_a[2:1], drv_e[2:1]); `ifdef VERILATOR assign match2[0] = (drv_all !== 2'b00 || drv_e[2:1]!=2'b11); assign match2[1] = (drv_all !== 2'b01 || drv_e[2:1]!=2'b11); assign match2[2] = (drv_all !== 2'b10 || drv_e[2:1]!=2'b11); assign match2[3] = (drv_all !== 2'b11 || drv_e[2:1]!=2'b11); `else assign match2[0] = drv_all !== 2'b00; assign match2[1] = drv_all !== 2'b01; assign match2[2] = drv_all !== 2'b10; assign match2[3] = drv_all !== 2'b11; `endif assign match2[4] = drv_all !== 2'bz0; assign match2[5] = drv_all !== 2'bz1; assign match2[6] = drv_all !== 2'bzz; assign match2[7] = drv_all !== 2'b0z; assign match2[8] = drv_all !== 2'b1z; endmodule verilator-5.042/test_regress/t/t_altera_lpm_fifo_dc.py0000755000542200017500000000111115101701376023551 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) test.compile(verilator_flags2=["--top-module", module]) test.passes() verilator-5.042/test_regress/t/t_assign_expr.v0000644000542200017500000000314215101701376022122 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t; int a; int b; int i; // verilator lint_off ASSIGNEQEXPR initial begin a = 10; i = (a = 2); `checkd(a, 2); `checkd(i, 2); a = 10; i = (a += 2); `checkd(a, 12); `checkd(i, 12); a = 10; i = (a -= 2); `checkd(a, 8); `checkd(i, 8); a = 10; i = (a *= 2); `checkd(a, 20); `checkd(i, 20); a = 10; i = (a /= 2); `checkd(a, 5); `checkd(i, 5); a = 11; i = (a %= 2); `checkd(a, 1); `checkd(i, 1); a = 10; i = (a &= 2); `checkd(a, 2); `checkd(i, 2); a = 8; i = (a |= 2); `checkd(a, 10); `checkd(i, 10); a = 10; i = (a ^= 2); `checkd(a, 8); `checkd(i, 8); a = 10; i = (a <<= 2); `checkd(a, 40); `checkd(i, 40); a = 10; i = (a >>= 2); `checkd(a, 2); `checkd(i, 2); a = 10; i = (a >>>= 2); `checkd(a, 2); `checkd(i, 2); a = 10; i = (a = (b = 5)); `checkd(a, 5); `checkd(i, 5); `checkd(b, 5); a = 10; b = 6; i = ((a += (b += 1) + 1)); `checkd(a, 18); `checkd(i, 18); `checkd(b, 7); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_package_ddecl_timing.py0000755000542200017500000000104315101701376024061 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_package_ddecl.v" test.compile(verilator_flags2=['--binary']) test.execute() test.passes() verilator-5.042/test_regress/t/t_time_sc_ns.out0000644000542200017500000000013015101701376022257 0ustar mahmoudyfreeshellTime scale of t is 1ns / 1ns [20] In top.t: Hi - expect this is 20 *-* All Finished *-* verilator-5.042/test_regress/t/t_fork_none_var.v0000644000542200017500000000240415101701376022430 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; logic [3:0] m_mask; initial begin int i; int n = 4; m_mask = 0; fork begin fork begin fork begin for(i = 0; i < n; i++) begin fork automatic int k = i; begin // see issue #4493 $display("[%0t] start %0d", $time, k); // UVM's arb_sequence_q[is_relevant_entries[k]].wait_for_relevant(); m_mask[k] = 1; #1; end join_none wait (m_mask[i]); end end join_any end join_any end join if (m_mask != {4{1'b1}}) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_class_extends_bad.out0000644000542200017500000000047615101701376023616 0ustar mahmoudyfreeshell%Error: t/t_class_extends_bad.v:13:26: Multiple inheritance illegal on non-interface classes (IEEE 1800-2023 8.13) 13 | class Cls extends Base1, Base2; | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_vlcov_opt_line.py0000755000542200017500000000133615101701376023013 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') test.run(cmd=[ os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--write-info", test.obj_dir + "/coverage.info", "--filter-type line", "t/t_vlcov_data_e.dat" ], verilator_run=True) test.files_identical(test.obj_dir + "/coverage.info", "t/" + test.name + ".info.out") test.passes() verilator-5.042/test_regress/t/t_recursive_method.v0000644000542200017500000000313215101701376023146 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 class Fib; function int get_fib(int n); if (n == 0 || n == 1) return n; else return get_fib(n - 1) + get_fib(n - 2); endfunction endclass class FibStatic; static function int get_fib(int n); if (n == 0 || n == 1) return n; else return get_fib(n - 1) + get_fib(n - 2); endfunction endclass class Factorial; static function int factorial(int n); return fact(n, 1); endfunction static function int fact(int n, int acc); if (n < 2) fact = acc; else fact = fact(n - 1, acc * n); endfunction endclass class Getter3 #(int T=5); static function int get_3(); if (T == 3) return 3; else return Getter3#(3)::get_3(); endfunction endclass module t; initial begin Fib fib = new; Getter3 getter3 = new; if (fib.get_fib(0) != 0) $stop; if (fib.get_fib(1) != 1) $stop; if (fib.get_fib(8) != 21) $stop; if (FibStatic::get_fib(0) != 0) $stop; if (FibStatic::get_fib(1) != 1) $stop; if (FibStatic::get_fib(8) != 21) $stop; if (Factorial::factorial(0) != 1) $stop; if (Factorial::factorial(1) != 1) $stop; if (Factorial::factorial(6) != 720) $stop; if (getter3.get_3() != 3) $stop; if (Getter3#(3)::get_3() != 3) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_preproc_ifexpr_bad.out0000644000542200017500000000405115101701376023777 0ustar mahmoudyfreeshell%Error: t/t_preproc_ifexpr_bad.v:12:14: `elsif with no matching `if 12 | `elsif ( ONE ) // BAD: elsif without if | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_preproc_ifexpr_bad.v:13:1: `endif with no matching `if 13 | `endif | ^~~~~~ %Error: t/t_preproc_ifexpr_bad.v:15:10: Syntax error in `ifdef () expression 15 | `ifdef ( ) // BAD: Missing value | ^ %Error: t/t_preproc_ifexpr_bad.v:18:17: Syntax error in `ifdef () expression 18 | `ifdef ( && ZERO) // BAD: Expr | ^ %Error: t/t_preproc_ifexpr_bad.v:21:18: Syntax error in `ifdef () expression 21 | `ifdef ( ZERO && ) // BAD: Expr | ^ %Error: t/t_preproc_ifexpr_bad.v:24:10: Syntax error in `ifdef () expression; unexpected: 'TEXT' 24 | `ifdef ( 1 ) // BAD: Constant | ^ %Error: t/t_preproc_ifexpr_bad.v:24:12: Syntax error in `ifdef () expression 24 | `ifdef ( 1 ) // BAD: Constant | ^ %Error: t/t_preproc_ifexpr_bad.v:27:14: Syntax error in `ifdef () expression; unexpected: 'TEXT' 27 | `ifdef ( ONE & ZERO) // BAD: Operator | ^ %Error: t/t_preproc_ifexpr_bad.v:30:10: Syntax error in `ifdef () expression; unexpected: 'TEXT' 30 | `ifdef ( % ) // BAD: % is syntax error | ^ %Error: t/t_preproc_ifexpr_bad.v:30:12: Syntax error in `ifdef () expression 30 | `ifdef ( % ) // BAD: % is syntax error | ^ %Error: t/t_preproc_ifexpr_bad.v:34:1: Expecting define name. Found: ENDIF 34 | `endif | ^~~~~~ %Error: t/t_preproc_ifexpr_bad.v:36:1: Expecting define name. Found: IFDEF 36 | `ifdef ( ONE // BAD: Missing paren | ^~~~~~ %Error: t/t_preproc_ifexpr_bad.v:37:1: Syntax error in `ifdef () expression; unexpected: 'TEXT' 37 | `endif | ^ %Error: t/t_preproc_ifexpr_bad.v:40:1: EOF in unterminated preprocessor expression %Error: t/t_preproc_ifexpr_bad.v:33:2: syntax error, unexpected ')' 33 | ) | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_unopt_converge_run_bad.out0000644000542200017500000000024015101701376024665 0ustar mahmoudyfreeshell-V{t#,#} 'stl' region trigger index 0 is active: @([hybrid] x) %Error: t/t_unopt_converge.v:7: Settle region did not converge after 5 tries Aborting... verilator-5.042/test_regress/t/t_lint_functimectl_bad.py0000755000542200017500000000150715101701376024142 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=['--timing'], fails=test.vlt_all, expect_filename=test.golden_filename) test.extract(in_filename=test.top_filename, out_filename=test.root + "/docs/gen/ex_FUNCTIMECTL_faulty.rst", lines="11-12") test.extract(in_filename=test.golden_filename, out_filename=test.root + "/docs/gen/ex_FUNCTIMECTL_msg.rst", lines="1-1") test.passes() verilator-5.042/test_regress/t/t_class_misstatic_bad.v0000644000542200017500000000176215101701376023601 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls; int m_field = get_ok(); function int get_ok(); return 1; endfunction function void nonstatic(); endfunction static function void isst(); endfunction endclass class Bar; function void bar(); Cls::nonstatic(); // <--- bad static ref Cls::isst(); endfunction endclass class Extends extends Cls; function void ok(); nonstatic(); isst(); endfunction static function void extstatic(); nonstatic(); // <--- bad static ref isst(); endfunction endclass module t; function void nonclassfunc(); Cls::nonstatic(); // <--- bad static ref Cls::isst(); endfunction initial begin Bar obj = new(); obj.bar(); Cls::nonstatic(); // <--- bad static ref Cls::isst(); Extends::isst(); $stop; end endmodule verilator-5.042/test_regress/t/t_interface_gen9.v0000644000542200017500000000125715101701376022467 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty. // SPDX-License-Identifier: CC0-1.0 // bug998 module t1(input logic foo); initial begin $display("%m %d", foo); end endmodule module t(); logic [1:0] my_foo; generate genvar the_genvar; for (the_genvar = 0; the_genvar < 2; the_genvar++) begin : TestIf //logic tmp_foo; //assign tmp_foo = my_foo[the_genvar]; t1 t (.foo(my_foo[the_genvar])); //t1 t (.foo(tmp_foo)); end endgenerate initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_a5_attributes_src.py0000755000542200017500000000372415101701376023416 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') test.rerunnable = False def have_clang_check(): cmd = 'python3 -c "from clang.cindex import Index; index = Index.create(); print(\\"Clang imported\\")";' if test.verbose: print("\t" + cmd) nout = test.run_capture(cmd, check=False) if not nout or not re.search(r'Clang imported', nout): return False return True if 'VERILATOR_TEST_NO_ATTRIBUTES' in os.environ: test.skip("Skipping due to VERILATOR_TEST_NO_ATTRIBUTES") if not os.path.exists(test.root + "/src/obj_dbg/compile_commands.json"): test.skip("compile_commands.json not found. Please install 'bear > 3.0' and rebuild Verilator") if not have_clang_check(): test.skip("No libclang installed") # some of the files are only used in Verilation # and are only in "include" folder srcfiles = test.glob_some(test.root + "/src/*.cpp") + test.glob_some(test.root + "/src/obj_dbg/V3Const__gen.cpp") srcfiles = [f for f in srcfiles if re.search(r'\/(V3Const|Vlc\w*|\w*_test|\w*_sc|\w*.yy).cpp$', f)] srcfiles_str = " ".join(srcfiles) test.run(logfile=test.run_log_filename, tee=True, cmd=["python3", test.root + "/nodist/clang_check_attributes", "--verilator-root=" + test.root, "--compilation-root=" + test.root + "/src/obj_dbg", "--compile-commands-dir=" + test.root + "/src/obj_dbg", srcfiles_str]) # yapf:disable test.file_grep(test.run_log_filename, r'Number of functions reported unsafe: +(\d+)', 0) test.passes() verilator-5.042/test_regress/t/t_define_override_output.out0000644000542200017500000000001615101701376024710 0ustar mahmoudyfreeshellTEST_MACRO 50 verilator-5.042/test_regress/t/t_interface_param_genblk.out0000644000542200017500000000233215101701376024604 0ustar mahmoudyfreeshell-Info: t/t_interface_param_genblk.v:35:9: correct : ... note: In instance 't.i_sub' 35 | $info("correct"); | ^~~~~ -Info: t/t_interface_param_genblk.v:44:13: i = 98, j = 2 : ... note: In instance 't.i_sub' 44 | $info("i = %0d, j = %0d", i, j); | ^~~~~ -Info: t/t_interface_param_genblk.v:44:13: i = 98, j = 1 : ... note: In instance 't.i_sub' 44 | $info("i = %0d, j = %0d", i, j); | ^~~~~ -Info: t/t_interface_param_genblk.v:44:13: i = 100, j = 2 : ... note: In instance 't.i_sub' 44 | $info("i = %0d, j = %0d", i, j); | ^~~~~ -Info: t/t_interface_param_genblk.v:44:13: i = 100, j = 1 : ... note: In instance 't.i_sub' 44 | $info("i = %0d, j = %0d", i, j); | ^~~~~ -Info: t/t_interface_param_genblk.v:50:26: correct : ... note: In instance 't.i_sub' 50 | intf.B * 50: $info("correct"); | ^~~~~ verilator-5.042/test_regress/t/t_param_ddeep_width.py0000755000542200017500000000070615101701376023431 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.042/test_regress/t/t_queue_bounded.py0000755000542200017500000000073415101701376022616 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_math_pow7.cpp0000644000542200017500000000171015101701376022021 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include VM_PREFIX_INCLUDE #include "TestCheck.h" int errors = 0; std::unique_ptr topp; int main(int argc, char** argv) { vluint64_t sim_time = 1100; const std::unique_ptr contextp{new VerilatedContext}; contextp->commandArgs(argc, argv); topp.reset(new VM_PREFIX{"top"}); topp->eval(); { contextp->timeInc(10); } int cyc = 0; while ((contextp->time() < sim_time) && !contextp->gotFinish()) { topp->eval(); contextp->timeInc(5); ++cyc; if (cyc > 10) break; } TEST_CHECK_EQ(topp->out_data, 1); topp->final(); topp.reset(); printf("*-* All Finished *-*\n"); return errors != 0; } verilator-5.042/test_regress/t/t_interface.py0000755000542200017500000000073415101701376021732 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_math_shortreal.v0000644000542200017500000001050715101701376022617 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `define is_near_real(a,b) (( ((a)<(b)) ? (b)-(a) : (a)-(b)) < (((a)/(b))*0.0001)) module t (/*AUTOARG*/ // Inputs clk ); input clk; // verilator lint_off SHORTREAL integer i; reg [63:0] b; shortreal r, r2; integer cyc = 0; realtime uninit; initial if (uninit != 0.0) $stop; initial begin if (1_00_0.0_1 != 1000.01) $stop; // rtoi truncates if ($rtoi(36.7) != 36) $stop; if ($rtoi(36.5) != 36) $stop; if ($rtoi(36.4) != 36) $stop; // casting rounds if ((integer '(36.7)) != 37) $stop; if ((integer '(36.5)) != 37) $stop; if ((integer '(36.4)) != 36) $stop; // assignment rounds // verilator lint_off REALCVT i = 36.7; if (i != 37) $stop; i = 36.5; if (i != 37) $stop; i = 36.4; if (i != 36) $stop; r = 10'd38; if (r!=38.0) $stop; // verilator lint_on REALCVT // operators if ((-(1.5)) != -1.5) $stop; if ((+(1.5)) != 1.5) $stop; if (((1.5)+(1.25)) != 2.75) $stop; if (((1.5)-(1.25)) != 0.25) $stop; if (((1.5)*(1.25)) != 1.875) $stop; if (((1.5)/(1.25)) != 1.2) $stop; // if (((1.5)==(2)) != 1'b0) $stop; // note 2 becomes real 2.0 if (((1.5)!=(2)) != 1'b1) $stop; if (((1.5)> (2)) != 1'b0) $stop; if (((1.5)>=(2)) != 1'b0) $stop; if (((1.5)< (2)) != 1'b1) $stop; if (((1.5)<=(2)) != 1'b1) $stop; if (((1.5)==(1.5)) != 1'b1) $stop; if (((1.5)!=(1.5)) != 1'b0) $stop; if (((1.5)> (1.5)) != 1'b0) $stop; if (((1.5)>=(1.5)) != 1'b1) $stop; if (((1.5)< (1.5)) != 1'b0) $stop; if (((1.5)<=(1.5)) != 1'b1) $stop; if (((1.6)==(1.5)) != 1'b0) $stop; if (((1.6)!=(1.5)) != 1'b1) $stop; if (((1.6)> (1.5)) != 1'b1) $stop; if (((1.6)>=(1.5)) != 1'b1) $stop; if (((1.6)< (1.5)) != 1'b0) $stop; if (((1.6)<=(1.5)) != 1'b0) $stop; // if (((0.0)?(2.0):(1.1)) != 1.1) $stop; if (((1.5)?(2.0):(1.1)) != 2.0) $stop; // if (!1.7) $stop; if (!(!0.0)) $stop; if (1.8 && 0.0) $stop; if (!(1.8 || 0.0)) $stop; // i=0; for (r=1.0; r<2.0; r=r+0.1) i++; if (i!=10) $stop; // bug r = $bitstoshortreal($shortrealtobits(1.414)); if (r != 1.414) $stop; end // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d\n", $time, cyc); `endif cyc <= cyc + 1; if (cyc==0) begin // Setup end else if (cyc<90) begin if ($time != {32'h0, $rtoi($realtime)}) $stop; if ($itor(cyc) != cyc) $stop; //Unsup: if ((real `($time)) != $realtime) $stop; r = $itor(cyc*2); i = $rtoi(r); if (i!=cyc*2) $stop; // r = $itor(cyc)/1.5; b = $realtobits(r); r2 = $bitstoreal(b); if (r != r2) $stop; // // Trust the integer math as a comparison r = $itor(cyc); if ($rtoi(-r) != -cyc) $stop; if ($rtoi(+r) != cyc) $stop; if ($rtoi(r+2.0) != (cyc+2)) $stop; if ($rtoi(r-2.0) != (cyc-2)) $stop; if ($rtoi(r*2.0) != (cyc*2)) $stop; if ($rtoi(r/2.0) != (cyc/2)) $stop; r2 = (2.0/(r-60)); // When zero, result indeterminate, but no crash // r2 = $itor(cyc); case (r) (r2-1.0): $stop; r2: ; default: $stop; endcase // r = $itor(cyc); if ((r==50.0) != (cyc==50)) $stop; if ((r!=50.0) != (cyc!=50)) $stop; if ((r> 50.0) != (cyc> 50)) $stop; if ((r>=50.0) != (cyc>=50)) $stop; if ((r< 50.0) != (cyc< 50)) $stop; if ((r<=50.0) != (cyc<=50)) $stop; // if ($rtoi((r-50.0) ? 10.0 : 20.0) != (((cyc-50)!=0) ? 10 : 20)) $stop; // if ((!(r-50.0)) != (!((cyc-50) != 0))) $stop; end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_sys_rand_concat.v0000644000542200017500000000354115101701376022754 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) module t; `define TRIES 100 bit [6:0] b5a; // We use larger than [4:0] so make sure we truncate bit [6:0] b5b; // We use larger than [4:0] so make sure we truncate bit [6:0] b7c; bit [6:0] b7d; bit [59:0] b60c; bit [89:0] b90c; bit [6:0] max_b5a; bit [6:0] max_b5b; bit [6:0] max_b7c; bit [6:0] max_b7d; bit [59:0] max_b60c; bit [89:0] max_b90c; initial begin for (int i = 0; i < `TRIES; ++i) begin // verilator lint_off WIDTH // Optimize away extracts b5a = {$random}[4:0]; b5b = {$random}[14:10]; // Optimize away concats b7c = {$random, $random, $random, $random, $random, $random, $random}; b7d = {{{$random}[0]}, {{$random}[0]}, {{$random}[0]}, {{$random}[0]}, {{$random}[0]}}; b60c = {$random, $random, $random, $random, $random, $random, $random}; b90c = {$random, $random, $random, $random, $random, $random, $random}; // verilator lint_on WIDTH max_b5a = max_b5a | b5a; max_b5b = max_b5b | b5b; max_b7c = max_b7c | b7c; max_b7d = max_b7d | b7d; max_b60c = max_b60c | b60c; max_b90c = max_b90c | b90c; end `checkh(max_b5a, 7'h1f); `checkh(max_b5b, 7'h1f); `checkh(max_b7c, 7'h7f); `checkh(max_b7d, 7'h1f); `checkh(max_b60c, ~ 60'h0); `checkh(max_b90c, ~ 90'h0); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_gantt_io_noproc.out0000644000542200017500000000255215101701376023332 0ustar mahmoudyfreeshellVerilator Gantt report Argument settings: +verilator+prof+exec+start+2 +verilator+prof+exec+window+2 Summary: Total elapsed time = 23415 rdtsc ticks Parallelized code = 82.51% of elapsed time Waiting time = 8.54% of elapsed time Total threads = 2 Total CPUs used = 2 Total mtasks = 7 Total yields = 0 NUMA assignment: NUMA status = no data Parallelized code, measured: Thread utilization = 14.22% Speedup = 0.284x Parallelized code, predicted during static scheduling: Thread utilization = 63.22% Speedup = 1.26x All code, measured: Thread utilization = 20.48% Speedup = 0.41x All code, measured, scaled by predicted speedup: Thread utilization = 56.80% Speedup = 1.14x MTask statistics: Longest mtask id = 5 Longest mtask time = 6.16% of time elapsed in parallelized code min log(p2e) = -3.681 from mtask 5 (predict 30, elapsed 1190) max log(p2e) = -2.409 from mtask 8 (predict 107, elapsed 1190) mean = -2.992 stddev = 0.459 e ^ stddev = 1.583 CPU info: Id | Time spent executing MTask | Socket | Core | Model | % of elapsed ticks / ticks | | | ====|============================|========|======|====== 10 | 20.18% / 4725 | | | 19 | 3.29% / 770 | | | verilator-5.042/test_regress/t/t_display_l.v0000644000542200017500000000057315101701376021565 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: $display() test for %l // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 module t; initial begin assert (0 == 0) else $fatal(2, "%l %m : %d", 0); $display("%l %m"); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_dpi_openfirst.py0000755000542200017500000000105615101701376022635 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=["t/t_dpi_openfirst_c.cpp"], verilator_flags2=["-Wall -Wno-DECLFILENAME"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_time_vpi_1s10ns.py0000755000542200017500000000136615101701376022715 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.pli_filename = "t/t_time_vpi_c.cpp" test.top_filename = "t/t_time_vpi.v" test.main_time_multiplier = 1e0 / 10e-9 test.compile( v_flags2=['+define+time_scale_units=1s +define+time_scale_prec=10ns', test.pli_filename], verilator_flags2=['--vpi']) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_lint_multidriven_bad.py0000755000542200017500000000144515101701376024170 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.extract(in_filename=test.top_filename, out_filename=test.root + "/docs/gen/ex_MULTIDRIVEN_faulty.rst", lines="31-36") test.extract(in_filename=test.golden_filename, out_filename=test.root + "/docs/gen/ex_MULTIDRIVEN_msg.rst", lines="10,11,14") test.passes() verilator-5.042/test_regress/t/t_flag_main.py0000755000542200017500000000135515101701376021707 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile( verilator_flags=[ # Custom as don't want -cc "-Mdir " + test.obj_dir, "--debug-check" ], verilator_flags2=['--exe --build --main'], # Check that code --main produces uses only most modern API features make_flags=['CPPFLAGS_ADD=-DVL_NO_LEGACY']) test.execute() test.passes() verilator-5.042/test_regress/t/t_flag_build_bad.out0000644000542200017500000000030415101701376023035 0ustar mahmoudyfreeshell%Error: --make cannot be used together with --build. Suggest see manual ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_case_zx_bad.py0000755000542200017500000000076615101701376022241 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_trace_noflag_bad_c.cpp0000644000542200017500000000144215101701376023652 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Yu-Sheng Lin. // SPDX-License-Identifier: CC0-1.0 #include #include #include VM_PREFIX_INCLUDE int main(int argc, char** argv) { std::unique_ptr contextp{new VerilatedContext}; contextp->traceEverOn(true); std::unique_ptr tfp{new VerilatedVcdC}; const std::unique_ptr topp{new VM_PREFIX{contextp.get()}}; topp->trace(tfp.get(), 99); // Error! tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/dump.vcd"); // Error! shall put to the next line! tfp->dump(0); tfp->close(); return 0; } verilator-5.042/test_regress/t/t_flag_getenv.py0000755000542200017500000000174115101701376022252 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.setenv('FOOBARTEST', "gotit") test.run(cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator --getenv FOOBARTEST"], logfile=test.compile_log_filename, verilator_run=True) test.file_grep(test.compile_log_filename, r'gotit') for var in [ 'MAKE', 'PERL', 'PYTHON3', 'SYSTEMC', 'SYSTEMC_ARCH', 'SYSTEMC_INCLUDE', 'SYSTEMC_LIBDIR', 'VERILATOR_ROOT' ]: test.run(cmd=[os.environ["VERILATOR_ROOT"] + "/bin/verilator", "--getenv", var], logfile=test.obj_dir + "/simx.log", verilator_run=True) test.passes() verilator-5.042/test_regress/t/t_simulate_array.v0000644000542200017500000000077015101701376022625 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 function integer fun; integer array[0:0]; begin array[0] = 10; fun = array[0]; end endfunction module test (); begin localparam something = fun(); initial begin if (something !== 10) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_func_range.py0000755000542200017500000000073415101701376022101 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_hier_block_type_param.v0000644000542200017500000000124615101701376024125 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t( clk ); input clk; logic [31:0] in1; logic [31:0] out1; assign in1 = 0; Test #(.TYPE_t(logic[31:0])) test(.out (out1), .in (in1)); always @ (posedge clk) begin if (out1 !== ~in1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module Test #(parameter type TYPE_t = logic [4:0]) ( output TYPE_t out, input TYPE_t in ); /*verilator hier_block*/ assign out = ~ in; endmodule verilator-5.042/test_regress/t/t_struct_literal_param.v0000644000542200017500000000132715101701376024023 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Demonstrate struct literal param assignment problem // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package Some_pkg; typedef struct packed { int foo; } some_struct_t; endpackage module sub #( parameter Some_pkg::some_struct_t the_some_struct ) (); endmodule module t (/*AUTOARG*/ // Inputs clk ); input clk; // finish report always @ (posedge clk) begin $write("*-* All Finished *-*\n"); $finish; end sub #( .the_some_struct( Some_pkg::some_struct_t'{ foo: 1 })) the_sub (); endmodule verilator-5.042/test_regress/t/t_interface_modport.v0000644000542200017500000000663715101701376023320 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 interface counter_if; logic [3:0] value; logic reset; modport counter_mp (input reset, output value); modport core_mp (output reset, input value); endinterface // Check can have inst module before top module module counter_ansi ( input clkm, counter_if c_data, input logic [3:0] i_value ); always @ (posedge clkm) begin c_data.value <= c_data.reset ? i_value : c_data.value + 1; end endmodule : counter_ansi module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=1; counter_if c1_data(); counter_if c2_data(); counter_if c3_data(); counter_if c4_data(); counter_ansi c1 (.clkm(clk), .c_data(c1_data.counter_mp), .i_value(4'h1)); `ifdef VERILATOR counter_ansi `else counter_nansi `endif /**/ c2 (.clkm(clk), .c_data(c2_data.counter_mp), .i_value(4'h2)); counter_ansi_m c3 (.clkm(clk), .c_data(c3_data), .i_value(4'h3)); `ifdef VERILATOR counter_ansi_m `else counter_nansi_m `endif /**/ c4 (.clkm(clk), .c_data(c4_data), .i_value(4'h4)); initial begin c1_data.value = 4'h4; c2_data.value = 4'h5; c3_data.value = 4'h6; c4_data.value = 4'h7; end always @ (posedge clk) begin cyc <= cyc + 1; if (cyc<2) begin c1_data.reset <= 1; c2_data.reset <= 1; c3_data.reset <= 1; c4_data.reset <= 1; end if (cyc==2) begin c1_data.reset <= 0; c2_data.reset <= 0; c3_data.reset <= 0; c4_data.reset <= 0; end if (cyc==20) begin $write("[%0t] cyc%0d: c1 %0x %0x c2 %0x %0x c3 %0x %0x c4 %0x %0x\n", $time, cyc, c1_data.value, c1_data.reset, c2_data.value, c2_data.reset, c3_data.value, c3_data.reset, c4_data.value, c4_data.reset); if (c1_data.value != 2) $stop; if (c2_data.value != 3) $stop; if (c3_data.value != 4) $stop; if (c4_data.value != 5) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule `ifndef VERILATOR // non-ansi modports not seen in the wild yet. Verilog-Perl needs parser improvement too. module counter_nansi (clkm, c_data, i_value); input clkm; counter_if c_data; input logic [3:0] i_value; always @ (posedge clkm) begin c_data.value <= c_data.reset ? i_value : c_data.value + 1; end endmodule : counter_nansi `endif module counter_ansi_m ( input clkm, counter_if.counter_mp c_data, input logic [3:0] i_value ); always @ (posedge clkm) begin c_data.value <= c_data.reset ? i_value : c_data.value + 1; end endmodule : counter_ansi_m `ifndef VERILATOR // non-ansi modports not seen in the wild yet. Verilog-Perl needs parser improvement too. module counter_nansi_m (clkm, c_data, i_value); input clkm; counter_if.counter_mp c_data; input logic [3:0] i_value; always @ (posedge clkm) begin c_data.value <= c_data.reset ? i_value : c_data.value + 1; end endmodule : counter_nansi_m `endif verilator-5.042/test_regress/t/t_interface_array_nocolon_bad.out0000644000542200017500000000267115101701376025643 0ustar mahmoudyfreeshell%Warning-ASCRANGE: t/t_interface_array_nocolon_bad.v:26:26: Ascending instance range connecting to vector: left < right of instance range: [0:2] : ... note: In instance 't' 26 | foo_intf foos [N] (.x(X)); | ^ ... For warning description see https://verilator.org/warn/ASCRANGE?v=latest ... Use "/* verilator lint_off ASCRANGE */" and lint_on around source to disable this message. %Warning-ASCRANGE: t/t_interface_array_nocolon_bad.v:27:28: Ascending instance range connecting to vector: left < right of instance range: [1:3] : ... note: In instance 't' 27 | foo_intf fool [1:3] (.x(X)); | ^ %Warning-ASCRANGE: t/t_interface_array_nocolon_bad.v:30:26: Ascending instance range connecting to vector: left < right of instance range: [0:2] : ... note: In instance 't' 30 | foo_subm subs [N] (.x(X)); | ^ %Warning-ASCRANGE: t/t_interface_array_nocolon_bad.v:31:28: Ascending instance range connecting to vector: left < right of instance range: [1:3] : ... note: In instance 't' 31 | foo_subm subl [1:3] (.x(X)); | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_trace_complex.out0000644000542200017500000001100415101701376022763 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $var wire 1 = clk $end $scope module $unit $end $var wire 1 # global_bit $end $upscope $end $scope module t $end $var wire 1 = clk $end $var wire 32 $ cyc [31:0] $end $var wire 2 % v_strp [1:0] $end $var wire 4 & v_strp_strp [3:0] $end $var wire 2 ' v_unip_strp [1:0] $end $var wire 2 ( v_arrp [2:1] $end $var wire 4 ) v_arrp_arrp [3:0] $end $var wire 4 * v_arrp_strp [3:0] $end $var wire 1 > v_arru[1] $end $var wire 1 ? v_arru[2] $end $var wire 1 @ v_arru_arru[3][1] $end $var wire 1 A v_arru_arru[3][2] $end $var wire 1 B v_arru_arru[4][1] $end $var wire 1 C v_arru_arru[4][2] $end $var wire 2 + v_arru_arrp[3] [2:1] $end $var wire 2 , v_arru_arrp[4] [2:1] $end $var wire 2 - v_arru_strp[3] [1:0] $end $var wire 2 . v_arru_strp[4] [1:0] $end $var real 64 / v_real $end $var real 64 1 v_arr_real[0] $end $var real 64 3 v_arr_real[1] $end $var wire 64 D v_chandle [63:0] $end $var wire 64 5 v_str32x2 [63:0] $end $var wire 32 7 v_enumed [31:0] $end $var wire 32 8 v_enumed2 [31:0] $end $var wire 3 9 v_enumb [2:0] $end $var wire 6 : v_enumb2_str [5:0] $end $var wire 8 F unpacked_array[-2] [7:0] $end $var wire 8 G unpacked_array[-1] [7:0] $end $var wire 8 H unpacked_array[0] [7:0] $end $var wire 1 I LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end $scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end $var wire 32 J PARAM [31:0] $end $upscope $end $scope module p2 $end $var wire 32 K PARAM [31:0] $end $upscope $end $scope module p3 $end $var wire 32 L PARAM [31:0] $end $upscope $end $scope module unnamedblk1 $end $var wire 32 ; b [31:0] $end $scope module unnamedblk2 $end $var wire 32 < a [31:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 1# b00000000000000000000000000000000 $ b00 % b0000 & b00 ' b00 ( b0000 ) b0000 * b00 + b00 , b00 - b00 . r0 / r0 1 r0 3 b0000000000000000000000000000000000000000000000000000000011111111 5 b00000000000000000000000000000000 7 b00000000000000000000000000000000 8 b000 9 b000000 : b00000000000000000000000000000000 ; b00000000000000000000000000000000 < 0= 0> 0? 0@ 0A 0B 0C b0000000000000000000000000000000000000000000000000000000000000000 D b00000000 F b00000000 G b00000000 H 0I b00000000000000000000000000000100 J b00000000000000000000000000000010 K b00000000000000000000000000000011 L #10 b00000000000000000000000000000001 $ b11 % b1111 & b11 ' b11 ( b1111 ) b1111 * b11 + b11 , b11 - b11 . r0.1 / r0.2 1 r0.3 3 b0000000000000000000000000000000100000000000000000000000011111110 5 b00000000000000000000000000000001 7 b00000000000000000000000000000010 8 b111 9 b00000000000000000000000000000101 ; b00000000000000000000000000000101 < 1= #15 0= #20 b00000000000000000000000000000010 $ b00 % b0000 & b00 ' b00 ( b0000 ) b0000 * b00 + b00 , b00 - b00 . r0.2 / r0.4 1 r0.6 3 b0000000000000000000000000000001000000000000000000000000011111101 5 b00000000000000000000000000000010 7 b00000000000000000000000000000100 8 b110 9 b111111 : 1= #25 0= #30 b00000000000000000000000000000011 $ b11 % b1111 & b11 ' b11 ( b1111 ) b1111 * b11 + b11 , b11 - b11 . r0.3 / r0.6000000000000001 1 r0.8999999999999999 3 b0000000000000000000000000000001100000000000000000000000011111100 5 b00000000000000000000000000000011 7 b00000000000000000000000000000110 8 b101 9 b110110 : 1= #35 0= #40 b00000000000000000000000000000100 $ b00 % b0000 & b00 ' b00 ( b0000 ) b0000 * b00 + b00 , b00 - b00 . r0.4 / r0.8 1 r1.2 3 b0000000000000000000000000000010000000000000000000000000011111011 5 b00000000000000000000000000000100 7 b00000000000000000000000000001000 8 b100 9 b101101 : 1= #45 0= #50 b00000000000000000000000000000101 $ b11 % b1111 & b11 ' b11 ( b1111 ) b1111 * b11 + b11 , b11 - b11 . r0.5 / r1 1 r1.5 3 b0000000000000000000000000000010100000000000000000000000011111010 5 b00000000000000000000000000000101 7 b00000000000000000000000000001010 8 b011 9 b100100 : 1= #55 0= #60 b00000000000000000000000000000110 $ b00 % b0000 & b00 ' b00 ( b0000 ) b0000 * b00 + b00 , b00 - b00 . r0.6 / r1.2 1 r1.8 3 b0000000000000000000000000000011000000000000000000000000011111001 5 b00000000000000000000000000000110 7 b00000000000000000000000000001100 8 b010 9 b011011 : 1= verilator-5.042/test_regress/t/t_pp_defnettype_bad.py0000755000542200017500000000076615101701376023453 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_assert_clock_event_unsup.py0000755000542200017500000000102215101701376025070 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert'], fails=True) test.passes() verilator-5.042/test_regress/t/t_display.v0000644000542200017500000002607715101701376021261 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg [40:0] quad; initial quad = 41'ha_bbbb_cccc; reg [80:0] wide; initial wide = 81'habc_1234_5678_1234_5678; reg [8:0] nine; initial nine = 12; reg signed [40:0] quads; initial quads = -(41'sha_bbbb_cccc); reg signed [80:0] wides; initial wides = -(81'shabc_1234_5678_1234_5678); reg signed [8:0] nines; initial nines = -12; reg [31:0] str; initial str = "\000\277\021\n"; reg [47:0] str2; initial str2 = "\000what!"; reg [79:0] str3; initial str3 = "\000hmmm!1234"; int n; initial n = 23; reg [7:0] m; initial m = 24; string svs = "sv-str"; reg [31:0] regstr = "meep"; reg [5:0] assoc_c[int]; string s; string not_fmt; sub sub (); sub2 sub2 (); sub3 sub3 (); initial begin $write("[%0t] In %m: Hi\n", $time); sub.write_m; sub2.write_m; sub3.write_m; // Escapes $display("[%0t] Back \\ Quote \"", $time); // Old bug when \" last on the line. // Display formatting - constants $display("[%0t] %%b=%b %%0b=%0b %%b=%b %%0b=%0b %%b=%b %%0b=%0b", $time, 9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc, 81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678); $display("[%0t] %%B=%B %%0B=%0B %%B=%B %%0B=%0B %%B=%B %%0B=%0B", $time, 9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc, 81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678); $display("[%0t] %%d=%d %%0d=%0d %%d=%d %%0d=%0d %%d=%d %%0d=%0d", $time, 9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc, 81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678); $display("[%0t] %%D=%D %%0D=%0D %%D=%D %%0D=%0D %%D=%D %%0D=%0D", $time, 9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc, 81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678); $display("[%0t] %%h=%h %%0h=%0h %%h=%h %%0h=%0h %%h=%h %%0h=%0h", $time, 9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc, 81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678); $display("[%0t] %%H=%H %%0H=%0H %%H=%H %%0H=%0H %%H=%H %%0H=%0H", $time, 9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc, 81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678); $display("[%0t] %%o=%o %%0o=%0o %%o=%o %%0o=%0o %%o=%o %%0o=%0o", $time, 9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc, 81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678); $display("[%0t] %%O=%O %%0O=%0O %%O=%O %%0O=%0O %%O=%O %%0O=%0o", $time, 9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc, 81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678); $display("[%0t] %%x=%x %%0x=%0x %%x=%x %%0x=%0x %%x=%x %%0x=%0x", $time, 9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc, 81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678); $display("[%0t] %%X=%X %%0X=%0X %%X=%X %%0X=%0X %%X=%X %%0X=%0X", $time, 9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc, 81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678); $display("[%0t] %%d=%d %%0d=%0d %%d=%d %%0d=%0d %%d=%d %%0d=%0d", $time, 9'sd12, 9'sd12, -(41'shabbbbcccc), -(41'shabbbbcccc), 81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678); $display("[%0t] %%D=%D %%0D=%0D %%D=%D %%0D=%0D %%D=%D %%0D=%0D", $time, 9'sd12, 9'sd12, -(41'shabbbbcccc), -(41'shabbbbcccc), -(81'shabc_1234_5678_1234_5678), -(81'shabc_1234_5678_1234_5678)); // Display formatting $display("[%0t] %%b=%b %%0b=%0b %%b=%b %%0b=%0b %%b=%b %%0b=%0b", $time, nine, nine, quad, quad, wide, wide); $display("[%0t] %%B=%B %%0B=%0B %%B=%B %%0B=%0B %%B=%B %%0B=%0B", $time, nine, nine, quad, quad, wide, wide); $display("[%0t] %%d=%d %%0d=%0d %%d=%d %%0d=%0d %%d=%d %%0d=%0d", $time, nine, nine, quad, quad, wide, wide); $display("[%0t] %%D=%D %%0D=%0D %%D=%D %%0D=%0D %%D=%D %%0D=%0D", $time, nine, nine, quad, quad, wide, wide); $display("[%0t] %%h=%h %%0h=%0h %%h=%h %%0h=%0h %%h=%h %%0h=%0h", $time, nine, nine, quad, quad, wide, wide); $display("[%0t] %%H=%H %%0H=%0H %%H=%H %%0H=%0H %%H=%H %%0H=%0H", $time, nine, nine, quad, quad, wide, wide); $display("[%0t] %%o=%o %%0o=%0o %%o=%o %%0o=%0o %%o=%o %%0o=%0o", $time, nine, nine, quad, quad, wide, wide); $display("[%0t] %%O=%O %%0O=%0O %%O=%O %%0O=%0O %%O=%O %%0O=%0o", $time, nine, nine, quad, quad, wide, wide); $display("[%0t] %%x=%x %%0x=%0x %%x=%x %%0x=%0x %%x=%x %%0x=%0x", $time, nine, nine, quad, quad, wide, wide); $display("[%0t] %%X=%X %%0X=%0X %%X=%X %%0X=%0X %%X=%X %%0X=%0X", $time, nine, nine, quad, quad, wide, wide); $display("[%0t] %%d=%d %%0d=%0d %%d=%d %%0d=%0d %%d=%d %%0d=%0d", $time, nines, nines, quads, quads, wides, wides); $display("[%0t] %%D=%D %%0D=%0D %%D=%D %%0D=%0D %%D=%D %%0D=%0D", $time, nines, nines, quads, quads, wides, wides); // // verilator lint_off WIDTH $display("[%0t] %%C=%C %%0C=%0C", $time, "a"+nine, "a"+nine); $display("[%0t] %%c=%c %%0c=%0c", $time, "a"+nine, "a"+nine); // verilator lint_on WIDTH $display("[%0t] %%v=%v %%0v=%0v %%v=%v %%0v=%0v %%v=%v %%0v=%0v <", $time, nine, nine, quad, quad, wide, wide); $display("[%0t] %%V=%V %%0V=%0V %%V=%V %%0V=%0V %%V=%V %%0V=%0V <", $time, nine, nine, quad, quad, wide, wide); $display("[%0t] %%p=%p %%0p=%0p %%p=%p %%0p=%0p %%p=%p %%0p=%0p", $time, nine, nine, quad, quad, wide, wide); $display("[%0t] %%P=%P %%0P=%0P %%P=%P %%0P=%0P %%P=%P %%0P=%0P", $time, nine, nine, quad, quad, wide, wide); $display("[%0t] %%P=%P", $time, svs); $display("[%0t] %%u=%u %%0u=%0u", $time, {"a","b","c","d"}, {"a","b","c","d"}); // Avoid binary output $display("[%0t] %%U=%U %%0U=%0U", $time, {"a","b","c","d"}, {"a","b","c","d"}); // Avoid binary output // %z is tested in t_sys_sformat.v $display("[%0t] %%D=%D %%d=%d %%01d=%01d %%06d=%06d %%6d=%6d %%-06d=%-06d %%-6d=%-6d", $time, nine, nine, nine, nine, nine, nine, nine); $display("[%0t] %%X=%X %%x=%x %%01x=%01x %%06x=%06x %%6x=%6x %%-06x=%-06x %%-6x=%-6x", $time, nine, nine, nine, nine, nine, nine, nine); $display("[%0t] %%O=%O %%o=%o %%01o=%01o %%06o=%06o %%6o=%6o %%-06o=%-06o %%-6o=%-6o", $time, nine, nine, nine, nine, nine, nine, nine); $display("[%0t] %%B=%B %%b=%b %%01b=%01b %%06b=%06b %%6b=%6b %%-06b=%-06b %%-6b=%-6b", $time, nine, nine, nine, nine, nine, nine, nine); $display("[%0t] %%t=%t %%03t=%03t %%0t=%0t", $time, $time, $time, $time); $display; // Not testing %0s, it does different things in different simulators $display("[%0t] %%s=%s %%s=%s %%s=%s", $time, str2[7:0], str2, str3); $display("[%0t] %%6s=:%6s: %%6s=:%6s: %%6s=:%6s:", $time, str2[7:0], str2, str3); $display("[%0t] %%8s=:%8s:", $time, svs); // Displays without format, must use default $write("d: "); $write(nine); $write(" "); $display(nine); $write; $display; $writeh("h: "); $writeh(nine); $writeh(" "); $displayh(nine); $writeh; $displayh; $writeo("o: "); $writeo(nine); $writeo(" "); $displayo(nine); $writeb; $displayb; $writeb("b: "); $writeb(nine); $writeb(" "); $displayb(nine); $writeo; $displayo; $display("%d", $signed(32'haaaaaaaa)); // -1431655766 $display($signed(32'haaaaaaaa)); // -1431655766 $display("%d", $unsigned(-2)); // 4294967294 $display($unsigned(-2)); // 4294967294 $display("%d", 32'haaaaaaaa); // 2863311530 $display(32'haaaaaaaa); // 2863311530 $display("assoc_c=", assoc_c); // Default to %p $display("[%0t] %s%s%s", $time, "hel", "lo, fr", "om a very long string. Percent %s are literally substituted in."); $display("hel", "lo, fr", "om a concatenated string."); $write("hel", "lo, fr", "om a concatenated format string [%0t].\n", $time); $display("two %d", 2, " args %d", 3, "with commas"); $display("extra argument: ", $time); $display($time,, ": pre argument",, "after"); $display("empty: >%s<", ""); $write("[%0t] Embedded tab '\t' and \r return\n", $time); $display("[%0t] Embedded\ multiline", $time); // Str check `ifndef NC // NC-Verilog 5.3 chokes on this test if (str !== 32'h00_bf_11_0a) $stop; `endif // Padding $write("'%0d %2d %8d'\n", 23, 23, 23); $write("'%-0d %-2d %-8d'\n", 23, 23, 23); $write("'%0d %2d %8d'\n", n, n, n); $write("'%-0d %-2d %-8d'\n", n, n, n); $write("'%8d'\n", m); $write("'%-8d'\n", m); $write("'%8t'\n", $time); $write("'%-8t'\n", $time); $write("'%8s'\n", svs); $write("'%-8s'\n", svs); $write("'%8s'\n", regstr); $write("'%-8s'\n", regstr); $write("'%8s'\n", "beep"); $write("'%-8s'\n", "beep"); // $itord conversion bug, note a %d instead of proper float // verilator lint_off REALCVT $display("log10(2) = %d", $log10(100)); // verilator lint_on REALCVT // unknown and high-impedance values $display("%d", 1'bx); $display("%h", 14'bx01010); $display("%o", 14'bx01010); $display("%h", 12'b001x_xx10_1x01); $display("%o", 12'bz01_xxx_101_x01); $display("%o", 12'bzzz_xxx_101_x01); $display("%d", 32'bx); $display("%d", 32'bz); $display("%d", 32'b11x11z111); $display("%d", 32'b11111z111); $display("%h", 12'b1zz1_zzzz_1x1z); $display("%o", 12'b1zz_zzz_x1x_xxx); $display("%o", 12'b1zx_zzx_x1z_xxx); $display(,, 10); // Strange but legal // $sformat allows only single format while $display/write allow multiple $display("[50] FIFTY 50"); $display("[%0t]", $time, " FIFTY %-d", 50); // This prints as %s, the %-d is not a format, as not_fmt is not literal not_fmt = " not-fmt %-d"; $display("[%0t]", $time, not_fmt, 60); // This prints as %s as forces the literal to a string $display("[%0t] %s", $time, " fmt-as-string-not-%0x", 70); // Sformat takes only single format per IEEE s = $sformatf("[%0t] %s", $time, " fmt-string-not-%s"); $display("s=%s", s); $write("*-* All Finished *-*\n"); $finish; end endmodule module sub; task write_m; $write("[%0t] In %m (%l)\n", $time); begin : subblock $write("[%0t] In %M (%L)\n", $time); // Uppercase %M test end endtask endmodule module sub2; // verilator no_inline_module task write_m; $write("[%0t] In %m (%l)\n", $time); begin : subblock2 $write("[%0t] In %m (%L)\n", $time); end endtask endmodule module sub3; function real copyr(input real r); copyr = r; endfunction real a, d; task write_m; a = 0.4; // verilator lint_off REALCVT $display("a: -0.4=> %.1f %0d %0x %0b", copyr(a), copyr(a), copyr(a), copyr(a)); // verilator lint_on REALCVT endtask endmodule verilator-5.042/test_regress/t/t_var_static_assign_decl_bad.py0000755000542200017500000000076615101701376025277 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_mem_multi_ref_bad.v0000644000542200017500000000155715101701376023242 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2005 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg dimn; reg [1:0] dim0; reg [1:0] dim1 [1:0]; reg [1:0] dim2 [1:0][1:0]; reg dim0nv[1:0]; initial begin dimn[1:0] = 0; // Bad: Not ranged dim0[1][1] = 0; // Bad: Not arrayed dim1[1][1][1] = 0; // Bad: Not arrayed to right depth dim2[1][1][1] = 0; // OK dim2[0 +: 1][1] = 0; // Bad: Range on non-bits dim2[1 : 0][1] = 0; // Bad: Range on non-bits dim2[1][1:0] = 0; // Bad: Bitsel too soon dim0nv[1:0] = 0; // Bad: Not vectored dim0nv[1][1] = 0; // Bad: Not arrayed to right depth end endmodule verilator-5.042/test_regress/t/t_hier_block.cpp0000644000542200017500000000114515101701376022217 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2020 by Yutetsu TAKATSUKASA. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* extern "C" int dpi_export_func(int); extern "C" int dpi_import_func(int v) { return dpi_export_func(v) - 1; } verilator-5.042/test_regress/t/t_assoc.v0000644000542200017500000001120215101701376020704 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; integer i; always @ (posedge clk) begin cyc <= cyc + 1; begin // Type typedef bit [3:0] nibble_t; typedef string dict_t [nibble_t]; dict_t a; string b [nibble_t]; nibble_t k; string v; a[4'd3] = "fooed"; a[4'd2] = "bared"; i = a.num(); `checkh(i, 2); i = a.size; `checkh(i, 2); // Also checks no parens v = a[4'd3]; `checks(v, "fooed"); v = a[4'd2]; `checks(v, "bared"); i = a.exists(4'd0); `checkh(i, 0); if (a.exists(4'd0)) $stop; // Check no width warning i = a.exists(4'd2); `checkh(i, 1); if (!a.exists(4'd2)) $stop; // Check no width warning i = a.first(k); `checkh(i, 1); `checks(k, 4'd2); i = a.next(k); `checkh(i, 1); `checks(k, 4'd3); i = a.next(k); `checkh(i, 0); i = a.last(k); `checkh(i, 1); `checks(k, 4'd3); i = a.prev(k); `checkh(i, 1); `checks(k, 4'd2); i = a.prev(k); `checkh(i, 0); `checkp(a, "'{'h2:\"bared\", 'h3:\"fooed\"}"); a.first(k); `checks(k, 4'd2); a.next(k); `checks(k, 4'd3); a.next(k); a.last(k); `checks(k, 4'd3); a.prev(k); `checks(k, 4'd2); a.delete(4'd2); i = a.size(); `checkh(i, 1); b = a; // Copy assignment i = b.size(); `checkh(i, 1); end begin // Strings string a [string]; string k; string v; a["foo"] = "fooed"; a["bar"] = "bared"; i = a.num(); `checkh(i, 2); i = a.size(); `checkh(i, 2); v = a["foo"]; `checks(v, "fooed"); v = a["bar"]; `checks(v, "bared"); i = a.exists("baz"); `checkh(i, 0); i = a.exists("bar"); `checkh(i, 1); i = a.first(k); `checkh(i, 1); `checks(k, "bar"); i = a.next(k); `checkh(i, 1); `checks(k, "foo"); i = a.next(k); `checkh(i, 0); i = a.last(k); `checkh(i, 1); `checks(k, "foo"); i = a.prev(k); `checkh(i, 1); `checks(k, "bar"); i = a.prev(k); `checkh(i, 0); `checkp(a["foo"], "\"fooed\""); `checkp(a, "'{\"bar\":\"bared\", \"foo\":\"fooed\"}"); a.delete("bar"); i = a.size(); `checkh(i, 1); a.delete(); i = a.size(); `checkh(i, 0); i = a.first(k); `checkh(i, 0); i = a.last(k); `checkh(i, 0); // Patterns & default a = '{ "f": "fooed", "b": "bared", default: "defaulted" }; i = a.size(); `checkh(i, 2); // Default doesn't count v = a["f"]; `checks(v, "fooed"); v = a["b"]; `checks(v, "bared"); v = a["NEXISTS"]; `checks(v, "defaulted"); a = '{}; i = a.size(); `checkh(i, 0); end begin // Wide-wides - need special array container classes, ick. logic [91:2] a [ logic [65:1] ]; int b [ bit [99:0] ]; a[~65'hfe] = ~ 90'hfee; `checkh(a[~65'hfe], ~ 90'hfee); b[100'b1] = 1; `checkh(b[100'b1], 1); end begin int a [string]; int sum; sum = 0; a["one"] = 1; a["two"] = 2; foreach (a[i]) sum += a[i]; `checkh(sum, 1 + 2); end begin // Issue #5435 int a; int ok; int dict [int]; dict[3] = 'h13; dict[4] = 'h14; dict[5] = 'h15; a = 4; ok = dict.first(a); if (a != 3) $stop; if (ok != 1) $stop; a = 4; ok = dict.next(a); if (a != 5) $stop; if (ok != 1) $stop; a = 4; ok = dict.last(a); if (a != 5) $stop; if (ok != 1) $stop; end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_structu_wide.py0000755000542200017500000000100115101701376022477 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['-DWIDE_WIDTH=128']) test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_array_fst_portable.py0000755000542200017500000000133315101701376025026 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_trace_array.v" test.golden_filename = "t/t_trace_array_fst.out" test.compile(verilator_flags2=[ '--cc --trace-fst --trace-structs --trace-max-width 0', '-CFLAGS -DVL_PORTABLE_ONLY' ]) test.execute() test.fst_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_class_param_virtual_bad.out0000644000542200017500000000121515101701376025002 0ustar mahmoudyfreeshell%Error: t/t_class_param_virtual_bad.v:23:28: Illegal to call 'new' using an abstract virtual class 'ClsVirt' (IEEE 1800-2023 8.21) : ... note: In instance 't' 23 | ClsVirt#(VBase) cv = new; | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_class_param_virtual_bad.v:13:11: Illegal to call 'new' using an abstract virtual class 'VBase' (IEEE 1800-2023 8.21) : ... note: In instance 't' 13 | t = new; | ^~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_castdyn_enum.py0000755000542200017500000000073415101701376022463 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_gate_opt.py0000755000542200017500000000073415101701376021574 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_top_bad.v0000644000542200017500000000135215101701376022237 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module sub(input wire clk, cpu_reset); reg reset_r; always @(posedge clk) begin reset_r <= cpu_reset; // The problematic one end endmodule module TOP(/*AUTOARG*/ // Inputs clk, reset_l ); input clk; input reset_l; reg sync_0, sync_1, sync_2; wire _cpu_reset_chain_io_q = sync_0; sub sub (.clk(clk), .cpu_reset(_cpu_reset_chain_io_q | !reset_l)); always @(posedge clk) begin sync_0 <= sync_1; sync_1 <= sync_2; sync_2 <= !reset_l; end endmodule verilator-5.042/test_regress/t/t_lint_unusedloop_removed_bad.out0000644000542200017500000000454615101701376025725 0ustar mahmoudyfreeshell%Warning-UNUSEDLOOP: t/t_lint_unusedloop_removed_bad.v:169:7: Loop condition is always false : ... note: In instance 't.with_always' 169 | while(0); | ^~~~~ ... For warning description see https://verilator.org/warn/UNUSEDLOOP?v=latest ... Use "/* verilator lint_off UNUSEDLOOP */" and lint_on around source to disable this message. %Warning-UNUSEDLOOP: t/t_lint_unusedloop_removed_bad.v:155:7: Loop condition is always false : ... note: In instance 't.non_parametrized_initial' 155 | while(0); | ^~~~~ %Warning-UNUSEDLOOP: t/t_lint_unusedloop_removed_bad.v:158:7: Loop condition is always false : ... note: In instance 't.non_parametrized_initial' 158 | do ; while(0); | ^~ %Warning-UNUSEDLOOP: t/t_lint_unusedloop_removed_bad.v:114:7: Loop condition is always false 114 | while(always_zero < 0) begin | ^~~~~ %Warning-UNUSEDLOOP: t/t_lint_unusedloop_removed_bad.v:156:7: Loop condition is always false 156 | while(always_false); | ^~~~~ %Warning-UNUSEDLOOP: t/t_lint_unusedloop_removed_bad.v:157:7: Loop condition is always false 157 | while(always_zero < 0); | ^~~~~ %Warning-UNUSEDLOOP: t/t_lint_unusedloop_removed_bad.v:171:7: Loop condition is always false 171 | while(always_false) begin | ^~~~~ %Warning-UNUSEDLOOP: t/t_lint_unusedloop_removed_bad.v:181:7: Loop condition is always false 181 | while(always_zero) begin | ^~~~~ %Warning-UNUSEDLOOP: t/t_lint_unusedloop_removed_bad.v:185:7: Loop condition is always false 185 | for (int i = 0; always_zero; i++) | ^~~ %Warning-UNUSEDLOOP: t/t_lint_unusedloop_removed_bad.v:190:7: Loop condition is always false 190 | for (int i = 0; i < always_zero; i++) | ^~~ %Warning-UNUSEDLOOP: t/t_lint_unusedloop_removed_bad.v:136:7: Loop is not used and will be optimized out 136 | while(param_unused_while < always_zero) begin | ^~~~~ %Warning-UNUSEDLOOP: t/t_lint_unusedloop_removed_bad.v:280:7: Loop is not used and will be optimized out 280 | while (m_2_ticked); | ^~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_lint_always_comb_iface.v0000644000542200017500000000404215101701376024255 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Josh Redford. // SPDX-License-Identifier: CC0-1.0 interface my_if; logic valid; logic [7:0] data ; modport slave_mp ( input valid, input data ); modport master_mp ( output valid, output data ); endinterface module t ( input wire in_valid, input wire [7:0] in_data ); my_if in_i (); my_if out1_i (); my_if out2_i (); my_if out3_i (); assign in_i.valid = in_valid; assign in_i.data = in_data ; my_module1 my_module1_i ( .in_i (in_i ), .out_i (out1_i) ); my_module2 my_module2_i ( .in_i (in_i ), .out_i (out2_i) ); my_module3 my_module3_i ( .in_i (in_i ), .out_i (out3_i) ); endmodule module my_module1 ( my_if.slave_mp in_i, my_if.master_mp out_i ); // Gives ALWCOMBORDER warning always_comb begin out_i.valid = in_i.valid; out_i.data = in_i.data ; end endmodule module my_module2 ( my_if.slave_mp in_i, my_if.master_mp out_i ); // Works if you initialise to non-interface signal first always_comb begin out_i.valid = '0; out_i.data = 'X; out_i.valid = in_i.valid; out_i.data = in_i.data ; end endmodule module my_module3 ( my_if.slave_mp in_i, my_if.master_mp out_i ); // Works if you use assign signal assign out_i.valid = in_i.valid; assign out_i.data = in_i.data ; endmodule verilator-5.042/test_regress/t/t_timescale_lint.py0000755000542200017500000000100315101701376022754 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=["--lint-only --timescale-override 1ns/1ns"]) test.passes() verilator-5.042/test_regress/t/t_case_write2.out0000644000542200017500000001155715101701376022362 0ustar mahmoudyfreeshell[2] crc=0000000000000097 1009 1410 [3] crc=000000000000012e 1009 1410 [4] crc=000000000000025d 1009 1410 [5] crc=00000000000004ba 1009 1410 [6] crc=0000000000000974 1009 1410 [7] crc=00000000000012e9 1009 1410 [8] crc=00000000000025d3 1009 1410 [9] crc=0000000000004ba7 1009 1410 [10] crc=000000000000974e 1009 1410 [11] crc=0000000000012e9d 1009 1410 [12] crc=0000000000025d3a 1009 1410 [13] crc=000000000004ba74 1009 1410 [14] crc=00000000000974e9 1009 1410 [15] crc=000000000012e9d3 1009 1410 [16] crc=000000000025d3a7 1009 1410 [17] crc=00000000004ba74e 1009 1410 [18] crc=0000000000974e9d 1009 1410 [19] crc=00000000012e9d3a 1009 1410 [20] crc=00000000025d3a74 1009 1410 [21] crc=0000000004ba74e9 1009 1410 [22] crc=000000000974e9d3 1009 23 1303 138 dude 1304 [23] crc=0000000012e9d3a7 1009 46 1309 1311 143 1312 dude 1313 [24] crc=0000000025d3a74e 1009 172 407 175 408 409 410 1106 dude 1129 [25] crc=000000004ba74e9d 1009 223 1014 880 885 1015 1016:0 1007 dude 1017 [26] crc=00000000974e9d3a 1009 1229 967 1230 718 dude 1231 [27] crc=000000012e9d3a74 1009 1410 [28] crc=000000025d3a74e9 1009 58 1369 19 dude 1370 [29] crc=00000004ba74e9d3 1009 194 1033 1034 1008 1035 880 dude 1036 [30] crc=0000000974e9d3a7 1009 1409:69 [31] crc=00000012e9d3a74e 1009 29 1320 137 144 141 138 148 dude 1321 [32] crc=00000025d3a74e9d 1009 1383:3a7 [33] crc=0000004ba74e9d3a 1009 216 1018 882 884 1019 1020 1007 dude 1021 [34] crc=000000974e9d3a74 1009 197 1014 882 883 1015 1016:1 1008 dude 1017 [35] crc=0000012e9d3a74e9 1009 1228 979 1230 713 dude 1231 [36] crc=0000025d3a74e9d3 1009 194 1011 1006 1008 1012 880 dude 1013 [37] crc=000004ba74e9d3a7 1009 1409:69 [38] crc=00000974e9d3a74e 1009 29 1320 137 144 141 138 148 dude 1321 [39] crc=000012e9d3a74e9d 1009 1383:3a7 [40] crc=000025d3a74e9d3a 1009 216 1018 882 884 1019 1020 1007 dude 1021 [41] crc=00004ba74e9d3a74 1009 197 1014 882 883 1015 1016:1 1008 dude 1017 [42] crc=0000974e9d3a74e9 1009 1228 979 1230 713 dude 1231 [43] crc=00012e9d3a74e9d3 1009 194 1011 1006 1008 1012 880 dude 1013 [44] crc=00025d3a74e9d3a7 1009 1409:69 [45] crc=0004ba74e9d3a74e 1009 29 1320 137 144 141 138 148 dude 1321 [46] crc=000974e9d3a74e9d 1009 1383:3a7 [47] crc=0012e9d3a74e9d3a 1009 216 1018 882 884 1019 1020 1007 dude 1021 [48] crc=0025d3a74e9d3a74 1009 197 1014 882 883 1015 1016:1 1008 dude 1017 [49] crc=004ba74e9d3a74e9 1009 1228 979 1230 713 dude 1231 [50] crc=00974e9d3a74e9d3 1009 194 1011 1006 1008 1012 880 dude 1013 [51] crc=012e9d3a74e9d3a7 1009 1409:69 [52] crc=025d3a74e9d3a74e 1009 29 1320 137 144 141 138 148 dude 1321 [53] crc=04ba74e9d3a74e9d 1009 1383:3a7 [54] crc=0974e9d3a74e9d3a 1009 216 1018 882 884 1019 1020 1007 dude 1021 [55] crc=12e9d3a74e9d3a74 1009 197 1014 882 883 1015 1016:1 1008 dude 1017 [56] crc=25d3a74e9d3a74e9 1009 1228 979 1230 713 dude 1231 [57] crc=4ba74e9d3a74e9d3 1009 194 1011 1006 1008 1012 880 dude 1013 [58] crc=974e9d3a74e9d3a7 1009 1409:69 [59] crc=2e9d3a74e9d3a74f 1009 29 1320 137 144 141 138 149 dude 1321 [60] crc=5d3a74e9d3a74e9e 1009 1383:3a7 [61] crc=ba74e9d3a74e9d3d 1009 216 1018 882 884 1019 1020 1007 dude 1021 [62] crc=74e9d3a74e9d3a7b 1009 197 1014 882 883 1015 1016:1 1008 dude 1017 [63] crc=e9d3a74e9d3a74f7 1009 1228 979 1230 713 dude 1231 [64] crc=d3a74e9d3a74e9ef 1009 194 1011 1006 1008 1012 880 dude 1013 [65] crc=a74e9d3a74e9d3df 1009 1409:69 [66] crc=4e9d3a74e9d3a7bf 1009 29 1320 137 144 141 145 149 dude 1321 [67] crc=9d3a74e9d3a74f7e 1009 1383:3a7 [68] crc=3a74e9d3a74e9efc 1009 216 1018 882 884 1019 1020 1007 dude 1021 [69] crc=74e9d3a74e9d3df9 1009 197 1014 882 883 1015 1016:1 1008 dude 1017 [70] crc=e9d3a74e9d3a7bf3 1009 1228 979 1230 713 dude 1231 [71] crc=d3a74e9d3a74f7e6 1009 194 1011 1006 1008 1012 880 dude 1013 [72] crc=a74e9d3a74e9efcc 1009 1409:69 [73] crc=4e9d3a74e9d3df98 1009 29 1320 137 147 149 143 142 dude 1321 [74] crc=9d3a74e9d3a7bf30 1009 1383:3a7 [75] crc=3a74e9d3a74f7e61 1009 216 1018 882 885 1019 1020 1007 dude 1021 [76] crc=74e9d3a74e9efcc3 1009 197 1014 882 884 1015 1016:1 1008 dude 1017 [77] crc=e9d3a74e9d3df987 1009 1228 982 1230 713 dude 1231 [78] crc=d3a74e9d3a7bf30f 1009 194 1011 1006 1008 1012 881 885 dude 1013 [79] crc=a74e9d3a74f7e61f 1009 1409:77 [80] crc=4e9d3a74e9efcc3f 1009 30 1320 149 146 146 137 149 dude 1321 [81] crc=9d3a74e9d3df987e 1009 1383:3df [82] crc=3a74e9d3a7bf30fc 1009 225 1018 882 885 1019 1020 1008 dude 1021 [83] crc=74e9d3a74f7e61f9 1009 218 1014 882 884 1015 1016:1 1008 dude 1017 [84] crc=e9d3a74e9efcc3f3 1009 1228 981 1230 708 dude 1231 [85] crc=d3a74e9d3df987e6 1009 232 1011 1005 1008 1012 881 883 dude 1013 [86] crc=a74e9d3a7bf30fcc 1009 1409:73 [87] crc=4e9d3a74f7e61f98 1009 1006 1258 846 1259 1006 1260 833 1261 dude 1262 [88] crc=9d3a74e9efcc3f30 1009 124 1320 146 137 149 137 134 dude 1321 [89] crc=3a74e9d3df987e61 1009 1383:f98 [90] crc=74e9d3a7bf30fcc3 1009 215 1033 1034 1008 1035 879 dude 1036 verilator-5.042/test_regress/t/t_func_while2.py0000755000542200017500000000073715101701376022202 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_extends.py0000755000542200017500000000101315101701376022620 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(make_flags=['VM_PARALLEL_BUILDS=1']) # bug2775) test.execute() test.passes() verilator-5.042/test_regress/t/t_array_list_bad.v0000644000542200017500000000172015101701376022557 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package pkg; typedef struct packed { logic t1; logic t2; logic t3; } type_t; endpackage : pkg module t ( input logic sys_clk, input logic sys_rst_n, input logic sys_ena, input pkg::type_t test_in, output pkg::type_t test_out ); import pkg::*; always_ff @(posedge sys_clk or negedge sys_rst_n) begin if (~sys_rst_n) begin test_out <= '{'0, '0, '0}; end else begin if(sys_ena) begin test_out.t1 <= ~test_in.t1; test_out.t2 <= ~test_in.t2; test_out.t3 <= ~test_in.t3; end else begin test_out <= '{'0, '0}; /* Inconsistent array list; */ end end end endmodule: t verilator-5.042/test_regress/t/t_struct_array.v0000644000542200017500000000166715101701376022334 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package TEST_TYPES; typedef struct a_struct_t; // Forward typedef struct packed { logic stuff; } a_struct_t; endpackage // TEST_TYPES module t(clk); input clk; TEST_TYPES::a_struct_t [3:0] a_out; sub sub (.a_out); always @ (posedge clk) begin if (a_out[0] != 1'b0) $stop; if (a_out[1] != 1'b1) $stop; if (a_out[2] != 1'b0) $stop; if (a_out[3] != 1'b1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule module sub(a_out); parameter N = 4; output TEST_TYPES::a_struct_t [N-1:0] a_out; always_comb begin for (int i=0;i 1 hier=top.t -000005 point: comment=(x==1) => 0 hier=top.t endfunction function automatic bit and_oper(bit a, bit b); %000005 return a & b; -000004 point: comment=(a==0) => 0 hier=top.t -000002 point: comment=(a==1 && b==1) => 1 hier=top.t -000005 point: comment=(b==0) => 0 hier=top.t endfunction localparam int NUM_INTFS = 4; intf the_intfs [NUM_INTFS-1:0] (); genvar intf_i; for (intf_i = 0; intf_i < NUM_INTFS; intf_i++) begin always_comb the_intfs[intf_i].t = cyc[intf_i]; end always @ (posedge clk) begin cyc <= cyc + 1; %000004 if ((~cyc[0] && cyc[1]) || (~cyc[2] && cyc[3])) $write(""); -000002 point: comment=(cyc[0]==0 && cyc[1]==1) => 1 hier=top.t -000002 point: comment=(cyc[0]==1 && cyc[2]==1) => 0 hier=top.t -000004 point: comment=(cyc[0]==1 && cyc[3]==0) => 0 hier=top.t -000002 point: comment=(cyc[1]==0 && cyc[2]==1) => 0 hier=top.t -000003 point: comment=(cyc[1]==0 && cyc[3]==0) => 0 hier=top.t -000002 point: comment=(cyc[2]==0 && cyc[3]==1) => 1 hier=top.t %000004 if ((~cyc2[32] && cyc2[33]) || (~cyc2[34] && cyc2[35])) $write(""); -000002 point: comment=(cyc2[32]==0 && cyc2[33]==1) => 1 hier=top.t -000002 point: comment=(cyc2[32]==1 && cyc2[34]==1) => 0 hier=top.t -000004 point: comment=(cyc2[32]==1 && cyc2[35]==0) => 0 hier=top.t -000002 point: comment=(cyc2[33]==0 && cyc2[34]==1) => 0 hier=top.t -000003 point: comment=(cyc2[33]==0 && cyc2[35]==0) => 0 hier=top.t -000002 point: comment=(cyc2[34]==0 && cyc2[35]==1) => 1 hier=top.t %000004 if ((~the_intfs[0].t && the_intfs[1].t) || (~the_intfs[2].t && the_intfs[3].t)) $write(""); -000002 point: comment=(the_intfs[0].t==0 && the_intfs[1].t==1) => 1 hier=top.t -000002 point: comment=(the_intfs[0].t==1 && the_intfs[2].t==1) => 0 hier=top.t -000004 point: comment=(the_intfs[0].t==1 && the_intfs[3].t==0) => 0 hier=top.t -000002 point: comment=(the_intfs[1].t==0 && the_intfs[2].t==1) => 0 hier=top.t -000003 point: comment=(the_intfs[1].t==0 && the_intfs[3].t==0) => 0 hier=top.t -000002 point: comment=(the_intfs[2].t==0 && the_intfs[3].t==1) => 1 hier=top.t %000004 if ((~t1 && t2) || (~t3 && t4)) $write(""); -000002 point: comment=(t1==0 && t2==1) => 1 hier=top.t -000002 point: comment=(t1==1 && t3==1) => 0 hier=top.t -000004 point: comment=(t1==1 && t4==0) => 0 hier=top.t -000002 point: comment=(t2==0 && t3==1) => 0 hier=top.t -000003 point: comment=(t2==0 && t4==0) => 0 hier=top.t -000002 point: comment=(t3==0 && t4==1) => 1 hier=top.t %000005 if (t3 && (t1 == t2)) $write(""); -000005 point: comment=((t1 == t2)==0) => 0 hier=top.t -000005 point: comment=(t3==0) => 0 hier=top.t -000002 point: comment=(t3==1 && (t1 == t2)==1) => 1 hier=top.t %000005 if (123 == (124 - 32'(t1 || t2))) $write(""); -000002 point: comment=(t1==0 && t2==0) => 0 hier=top.t -000005 point: comment=(t1==1) => 1 hier=top.t -000004 point: comment=(t2==1) => 1 hier=top.t %000004 some_int <= (t2 || t3) ? 345 : 567; -000003 point: comment=(t2==0 && t3==0) => 0 hier=top.t -000004 point: comment=(t2==1) => 1 hier=top.t -000004 point: comment=(t3==1) => 1 hier=top.t %000005 some_bool <= t1 && t2; -000004 point: comment=(t1==0) => 0 hier=top.t -000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t %000005 if (t1 & t2) $write(""); -000004 point: comment=(t1==0) => 0 hier=top.t -000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t %000004 if ((!t1 && t2) | (~t3 && t4)) $write(""); -000002 point: comment=(t1==0 && t2==1) => 1 hier=top.t -000002 point: comment=(t1==1 && t3==1) => 0 hier=top.t -000004 point: comment=(t1==1 && t4==0) => 0 hier=top.t -000002 point: comment=(t2==0 && t3==1) => 0 hier=top.t -000003 point: comment=(t2==0 && t4==0) => 0 hier=top.t -000002 point: comment=(t3==0 && t4==1) => 1 hier=top.t %000003 if (t1 ^ t2) $write(""); -000002 point: comment=(t1==0 && t2==0) => 0 hier=top.t -000002 point: comment=(t1==0 && t2==1) => 1 hier=top.t -000003 point: comment=(t1==1 && t2==0) => 1 hier=top.t -000002 point: comment=(t1==1 && t2==1) => 0 hier=top.t %000005 if (~(t1 & t2)) $write(""); -000004 point: comment=(t1==0) => 1 hier=top.t -000002 point: comment=(t1==1 && t2==1) => 0 hier=top.t -000005 point: comment=(t2==0) => 1 hier=top.t %000004 if (t1 -> t2) $write(""); -000004 point: comment=(t1==0) => 1 hier=top.t -000003 point: comment=(t1==1 && t2==0) => 0 hier=top.t -000004 point: comment=(t2==1) => 1 hier=top.t %000003 if (t1 <-> t2) $write(""); -000002 point: comment=(t1==0 && t2==0) => 1 hier=top.t -000002 point: comment=(t1==0 && t2==1) => 0 hier=top.t -000003 point: comment=(t1==1 && t2==0) => 0 hier=top.t -000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t %000005 if (&cyc[2:0]) $write(""); -000004 point: comment=(cyc[2:0][0]==0) => 0 hier=top.t -000001 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 1 hier=top.t -000005 point: comment=(cyc[2:0][1]==0) => 0 hier=top.t -000005 point: comment=(cyc[2:0][2]==0) => 0 hier=top.t %000007 if (&cyc[3:2]) $write(""); -000005 point: comment=(cyc[3:2][0]==0) => 0 hier=top.t -000000 point: comment=(cyc[3:2][0]==1 && cyc[3:2][1]==1) => 1 hier=top.t -000007 point: comment=(cyc[3:2][1]==0) => 0 hier=top.t %000005 if (|cyc[2:0]) $write(""); -000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 0 hier=top.t -000005 point: comment=(cyc[2:0][0]==1) => 1 hier=top.t -000004 point: comment=(cyc[2:0][1]==1) => 1 hier=top.t -000004 point: comment=(cyc[2:0][2]==1) => 1 hier=top.t %000002 if (^cyc[2:0]) $write(""); -000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 0 hier=top.t -000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==1) => 1 hier=top.t -000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==1 && cyc[2:0][2]==0) => 1 hier=top.t -000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 0 hier=top.t -000002 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 1 hier=top.t -000001 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==0 && cyc[2:0][2]==1) => 0 hier=top.t -000001 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==0) => 0 hier=top.t -000001 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 1 hier=top.t %000005 if (|cyc[2:0] || cyc[3]) $write(""); -000000 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0 && cyc[3]==0) => 0 hier=top.t -000005 point: comment=(cyc[2:0][0]==1) => 1 hier=top.t -000004 point: comment=(cyc[2:0][1]==1) => 1 hier=top.t -000004 point: comment=(cyc[2:0][2]==1) => 1 hier=top.t -000002 point: comment=(cyc[3]==1) => 1 hier=top.t %000005 if (t1 & t2 & 1'b1) $write(""); -000000 point: comment=(1'h1==0) => 0 hier=top.t -000004 point: comment=(t1==0) => 0 hier=top.t -000002 point: comment=(t1==1 && t2==1 && 1'h1==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t %000009 if (t1 & t2 & 1'b0) $write(""); -000009 point: comment=(1'h0==0) => 0 hier=top.t -000004 point: comment=(t1==0) => 0 hier=top.t -000000 point: comment=(t1==1 && t2==1 && 1'h0==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t %000005 if (t1 & t2 & ONE) $write(""); -000000 point: comment=(ONE==0) => 0 hier=top.t -000004 point: comment=(t1==0) => 0 hier=top.t -000002 point: comment=(t1==1 && t2==1 && ONE==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t %000009 if (t1 & t2 & ZERO) $write(""); -000009 point: comment=(ZERO==0) => 0 hier=top.t -000004 point: comment=(t1==0) => 0 hier=top.t -000000 point: comment=(t1==1 && t2==1 && ZERO==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t %000005 if (t1 && t2) begin -000004 point: comment=(t1==0) => 0 hier=top.t -000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t $write(""); %000003 end else if (t1 || t2) begin -000002 point: comment=(t1==0 && t2==0) => 0 hier=top.t -000003 point: comment=(t1==1) => 1 hier=top.t -000002 point: comment=(t2==1) => 1 hier=top.t $write(""); end %000005 if (invert(t1) && t2) $write(""); -000005 point: comment=(invert(t1)==0) => 0 hier=top.t -000002 point: comment=(invert(t1)==1 && t2==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t if (and_oper(t1, t2)) $write(""); %000005 if (t2 && t3) begin -000005 point: comment=(t2==0) => 0 hier=top.t -000002 point: comment=(t2==1 && t3==1) => 1 hier=top.t -000005 point: comment=(t3==0) => 0 hier=top.t %000001 if (t1 && t2) $write(""); -000001 point: comment=(t1==0) => 0 hier=top.t -000001 point: comment=(t1==1 && t2==1) => 1 hier=top.t -000000 point: comment=(t2==0) => 0 hier=top.t end if (0 == 1) begin for (int loop_var = 0; loop_var < 1; loop_var++) begin %000000 if (cyc[loop_var] && t2) $write(""); -000000 point: comment=(cyc[loop_var[4:0]+:1]==0) => 0 hier=top.t -000000 point: comment=(cyc[loop_var[4:0]+:1]==1 && t2==1) => 1 hier=top.t -000000 point: comment=(t2==0) => 0 hier=top.t end end // stop at the first layer even if there's more to find %000007 if ((cyc[3+32'(t1 && t2)+:2] == cyc[5+32'(t3 || t4)+:2]) || cyc[31]) $write(""); -000002 point: comment=((cyc[(32'sh3 + (t1 && t2))[4:0]+:2] == cyc[(32'sh5 + (t3 || t4))[4:0]+:2])==0 && cyc[31]==0) => 0 hier=top.t -000007 point: comment=((cyc[(32'sh3 + (t1 && t2))[4:0]+:2] == cyc[(32'sh5 + (t3 || t4))[4:0]+:2])==1) => 1 hier=top.t -000000 point: comment=(cyc[31]==1) => 1 hier=top.t // impossible branches and redundant terms %000005 if ((t1 && t2) && ~(t1 && t3) && (t1 || t4)) $write(""); -000003 point: comment=(t1==0 && t4==0) => 0 hier=top.t -000004 point: comment=(t1==0) => 0 hier=top.t -000000 point: comment=(t1==1 && t2==1 && t3==0 && t4==1) => 1 hier=top.t -000001 point: comment=(t1==1 && t2==1 && t3==0) => 1 hier=top.t -000002 point: comment=(t1==1 && t3==1) => 0 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t %000005 if ((cyc[0] && cyc[1]) && ~(cyc[0] && cyc[2]) && (cyc[0] || cyc[3])) $write(""); -000003 point: comment=(cyc[0]==0 && cyc[3]==0) => 0 hier=top.t -000004 point: comment=(cyc[0]==0) => 0 hier=top.t -000000 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[3]==1) => 1 hier=top.t -000001 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0) => 1 hier=top.t -000002 point: comment=(cyc[0]==1 && cyc[2]==1) => 0 hier=top.t -000005 point: comment=(cyc[1]==0) => 0 hier=top.t // demonstrate current limitations of term matching scheme %000005 if ((cyc[0] && cyc[1]) && ~(cyc[1-1] && cyc[2]) && (cyc[2-2] || cyc[3])) $write(""); -000002 point: comment=(cyc[(32'sh1 - 32'sh1)[4:0]+:1]==1 && cyc[2]==1) => 0 hier=top.t -000003 point: comment=(cyc[(32'sh2 - 32'sh2)[4:0]+:1]==0 && cyc[3]==0) => 0 hier=top.t -000004 point: comment=(cyc[0]==0) => 0 hier=top.t -000000 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[(32'sh1 - 32'sh1)[4:0]+:1]==0 && cyc[(32'sh2 - 32'sh2)[4:0]+:1]==1) => 1 hier=top.t -000000 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[(32'sh1 - 32'sh1)[4:0]+:1]==0 && cyc[3]==1) => 1 hier=top.t -000001 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[(32'sh2 - 32'sh2)[4:0]+:1]==1) => 1 hier=top.t -000000 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[3]==1) => 1 hier=top.t -000005 point: comment=(cyc[1]==0) => 0 hier=top.t //verilator coverage_off if (t1 && t2) $write(""); //verilator coverage_on if ((~t1 && t2) %000004 || -000002 point: comment=(t1==0 && t2==1) => 1 hier=top.t -000002 point: comment=(t1==1 && t3==1) => 0 hier=top.t -000004 point: comment=(t1==1 && t4==0) => 0 hier=top.t -000002 point: comment=(t2==0 && t3==1) => 0 hier=top.t -000003 point: comment=(t2==0 && t4==0) => 0 hier=top.t -000002 point: comment=(t3==0 && t4==1) => 1 hier=top.t (~t3 && t4)) $write(""); // intentionally testing wonkified expression terms if ( cyc[ 0 %000005 ] & -000004 point: comment=(cyc[0]==0) => 0 hier=top.t -000002 point: comment=(cyc[0]==1 && cyc[1]==1) => 1 hier=top.t -000005 point: comment=(cyc[1]==0) => 0 hier=top.t cyc [1]) $write(""); // for now each ternary condition is considered in isolation %000005 other_int <= t1 ? t2 ? 1 : 2 : 3; -000004 point: comment=(t1==0) => 0 hier=top.t -000005 point: comment=(t1==1) => 1 hier=top.t // no expression coverage for multi-bit expressions if ((cyc[1:0] & cyc[3:2]) == 2'b11) $write(""); // truth table is too large if (^cyc[6:0]) $write(""); // this one is too big even for t_cover_expr_max if (^cyc) $write(""); if (cyc==9) begin $write("*-* All Finished *-*\n"); $finish; end end always_comb begin %000005 if (t1 && t2) $write(""); -000005 point: comment=(t1==0) => 0 hier=top.t -000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t -000005 point: comment=(t2==0) => 0 hier=top.t end logic ta, tb, tc; initial begin cls obj = new; cls null_obj = null; int q[5]; int qv[$]; q = '{1, 2, 2, 4, 3}; // lambas not handled // NB: there is a bug w/ tracing find_first (maybe lambdas in general?) // tracing_off does not work around the bug qv = q.find_first with (item[0] & item[1]); ta = '1; tb = '0; tc = '0; %000001 while (ta || tb || tc) begin -000001 point: comment=(ta==0 && tb==0 && tc==0) => 0 hier=top.t -000000 point: comment=(ta==1) => 1 hier=top.t -000000 point: comment=(tb==1) => 1 hier=top.t -000000 point: comment=(tc==1) => 1 hier=top.t tc = tb; tb = ta; ta = '0; end if (!bit'(obj.randomize() with {x < 100;})) $write(""); if (null_obj != null && null_obj.x == 5) $write(""); end sub the_sub_1 (.p(t1), .q(t2)); sub the_sub_2 (.p(t3), .q(t4)); // TODO -- non-process expressions sub the_sub_3 (.p(t1 ? t2 : t3), .q(t4)); // TODO // pragma for expr coverage off / on // investigate cover point sorting in annotated source // consider reporting don't care terms // // Branches which are statically impossible to reach are still reported. // E.g. // -000000 point: comment=(t1=1 && t2=1 && 1'h0=1) => 1 hier=top.t // These could potentially be pruned, but they currently follow suit for // what branch coverage does. Perhaps a switch should be added to not // count statically impossible things. endmodule module sub ( input p, input q ); always_comb begin ~000019 if (p && q) $write(""); +000017 point: comment=(p==0) => 0 hier=top.t.the_sub_* -000002 point: comment=(p==1 && q==1) => 1 hier=top.t.the_sub_* +000019 point: comment=(q==0) => 0 hier=top.t.the_sub_* end endmodule interface intf(); logic t; endinterface verilator-5.042/test_regress/t/t_covergroup_in_class_duplicate_bad.out0000755000542200017500000000075015101701376027055 0ustar mahmoudyfreeshell%Error: t/t_covergroup_in_class_duplicate_bad.v:13:16: Duplicate declaration of CLASS '__vlAnonCG_embeddedCg': '__vlAnonCG_embeddedCg' 13 | covergroup embeddedCg; | ^~~~~~~~~~ t/t_covergroup_in_class_duplicate_bad.v:9:16: ... Location of original declaration 9 | covergroup embeddedCg; | ^~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_enum_recurse_bad.py0000755000542200017500000000076615101701376023301 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_order_loop_bad.py0000755000542200017500000000072615101701376022745 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_public_clk.cpp0000644000542200017500000000216515101701376022230 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Todd Strader. // SPDX-License-Identifier: CC0-1.0 // Generated header #include "Vt_public_clk.h" #include "Vt_public_clk___024root.h" // General headers #include "verilated.h" std::unique_ptr topp; int main(int argc, char** argv) { vluint64_t sim_time = 1100; const std::unique_ptr contextp{new VerilatedContext}; contextp->debug(0); contextp->commandArgs(argc, argv); srand48(5); topp.reset(new VM_PREFIX{"top"}); topp->rootp->t__DOT__clk = 0; topp->eval(); { contextp->timeInc(10); } while ((contextp->time() < sim_time) && !contextp->gotFinish()) { topp->rootp->t__DOT__clk = !topp->rootp->t__DOT__clk; topp->eval(); contextp->timeInc(5); } if (!contextp->gotFinish()) { vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); } topp->final(); topp.reset(); return 0; } verilator-5.042/test_regress/t/t_vpi_get.cpp0000644000542200017500000002105315101701376021553 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* #ifdef IS_VPI #include "vpi_user.h" #include #else #include "verilated.h" #include "verilated_vcd_c.h" #include "verilated_vpi.h" #include "Vt_vpi_get.h" #include "Vt_vpi_get__Dpi.h" #include "svdpi.h" #endif #include #include #include extern "C" { #include } // These require the above. Comment prevents clang-format moving them #include "TestSimulator.h" #include "TestVpi.h" #define TEST_MSG \ if (0) printf //====================================================================== static int _mon_check_props(TestVpiHandle& handle, int size, int direction, int scalar, int type) { s_vpi_value value; value.format = vpiIntVal; value.value.integer = 0; // check size of object int vpisize = vpi_get(vpiSize, handle); CHECK_RESULT(vpisize, size); // icarus verilog does not support vpiScalar, vpiVector or vpi*Range if (TestSimulator::has_get_scalar() && type != vpiParameter) { int vpiscalar = vpi_get(vpiScalar, handle); CHECK_RESULT((bool)vpiscalar, (bool)scalar); int vpivector = vpi_get(vpiVector, handle); CHECK_RESULT((bool)vpivector, (bool)!scalar); } // Icarus only supports ranges on memories if (!scalar && type != vpiIntVar && type != vpiParameter && !(TestSimulator::is_icarus() && type != vpiMemory)) { // check coherency for vectors int coherency = 1; TestVpiHandle iter_h = vpi_iterate(vpiRange, handle); while (TestVpiHandle range_h = vpi_scan(iter_h)) { int rangeSize; TestVpiHandle left_h, right_h; // get left hand side of range left_h = vpi_handle(vpiLeftRange, range_h); CHECK_RESULT_NZ(left_h); vpi_get_value(left_h, &value); rangeSize = value.value.integer; // get right hand side of range right_h = vpi_handle(vpiRightRange, range_h); CHECK_RESULT_NZ(right_h); vpi_get_value(right_h, &value); rangeSize = abs(rangeSize - value.value.integer) + 1; coherency *= rangeSize; } iter_h.freed(); CHECK_RESULT(coherency, size); } // Only check direction on ports if (type == vpiPort) { // check direction of object int vpidir = vpi_get(vpiDirection, handle); // Don't check port directions in verilator // See issue #681 if (!TestSimulator::is_verilator() && !TestSimulator::is_questa()) CHECK_RESULT(vpidir, direction); } // check type of object int vpitype = vpi_get(vpiType, handle); if (!TestSimulator::is_verilator() && !TestSimulator::is_questa() && type == vpiPort) { // Don't check for ports in verilator // See issue #681 CHECK_RESULT(vpitype, type); } return 0; // Ok } struct params { const char* signal; struct { unsigned int size; unsigned int direction; unsigned int scalar; int type; } attributes, children; }; int mon_check_props() { // This table needs to be function-static. // This avoids calling is_verilator() below at global-static init time. // When global-static led to a race between the is_verilator call below, and // the code that sets up the VerilatedAssertOneThread() check in // verilated_vpi.cc, it was causing the check to falsely fail // (due to m_threadid within the check not being initted yet.) static struct params values[] = { {"onebit", {1, vpiNoDirection, 1, vpiReg}, {0, 0, 0, 0}}, {"twoone", {2, vpiNoDirection, 0, vpiReg}, {0, 0, 0, 0}}, {"onetwo", {2, vpiNoDirection, 1, vpiRegArray}, {0, 0, 0, 0}}, {"fourthreetwoone", {2, vpiNoDirection, 0, vpiRegArray}, {2, vpiNoDirection, 0, vpiReg}}, {"theint", {32, vpiNoDirection, 0, TestSimulator::is_verilator() ? vpiReg : vpiIntVar}, {0, 0, 0, 0}}, {"clk", {1, vpiInput, 1, vpiPort}, {0, 0, 0, 0}}, {"testin", {16, vpiInput, 0, vpiPort}, {0, 0, 0, 0}}, {"testout", {24, vpiOutput, 0, vpiPort}, {0, 0, 0, 0}}, {"sub.subin", {1, vpiInput, 1, vpiPort}, {0, 0, 0, 0}}, {"sub.subout", {1, vpiOutput, 1, vpiPort}, {0, 0, 0, 0}}, {"sub.subparam", {32, vpiNoDirection, 0, vpiParameter}, {0, 0, 0, 0}}, {"sub.the_intf.bytesig", {8, vpiNoDirection, 0, vpiReg}, {0, 0, 0, 0}}, {"sub.the_intf.param", {32, vpiNoDirection, 0, vpiParameter}, {0, 0, 0, 0}}, {"sub.the_intf.lparam", {32, vpiNoDirection, 0, vpiParameter}, {0, 0, 0, 0}}, {"twobytwo", {4, vpiNoDirection, 0, vpiReg}, {0, 0, 0, 0}}, {NULL, {0, 0, 0, 0}, {0, 0, 0, 0}}}; struct params* value = values; while (value->signal) { TestVpiHandle h = VPI_HANDLE(value->signal); TEST_MSG("%s\n", value->signal); CHECK_RESULT_NZ(h); if (int status = _mon_check_props(h, value->attributes.size, value->attributes.direction, value->attributes.scalar, value->attributes.type)) return status; if (value->children.size) { int size = 0; TestVpiHandle iter_h = vpi_iterate(vpiReg, h); while (TestVpiHandle word_h = vpi_scan(iter_h)) { // check size and range if (int status = _mon_check_props(word_h, value->children.size, value->children.direction, value->children.scalar, value->children.type)) return status; size++; } iter_h.freed(); // IEEE 37.2.2 vpi_scan at end does a vpi_release_handle CHECK_RESULT(size, value->attributes.size); } value++; } return 0; } extern "C" int mon_check() { // Callback from initial block in monitor if (int status = mon_check_props()) return status; return 0; // Ok } void dpi_print(const char* somestring) { printf("SOMESTRING = %s\n", somestring); } //====================================================================== #ifdef IS_VPI static int mon_check_vpi() { TestVpiHandle href = vpi_handle(vpiSysTfCall, 0); s_vpi_value vpi_value; vpi_value.format = vpiIntVal; vpi_value.value.integer = mon_check(); vpi_put_value(href, &vpi_value, NULL, vpiNoDelay); return 0; } static s_vpi_systf_data vpi_systf_data[] = {{vpiSysFunc, vpiIntFunc, (PLI_BYTE8*)"$mon_check", (PLI_INT32(*)(PLI_BYTE8*))mon_check_vpi, 0, 0, 0}, 0}; // cver entry void vpi_compat_bootstrap(void) { p_vpi_systf_data systf_data_p; systf_data_p = &(vpi_systf_data[0]); while (systf_data_p->type != 0) vpi_register_systf(systf_data_p++); } // icarus entry void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0}; #else int main(int argc, char** argv) { const std::unique_ptr contextp{new VerilatedContext}; uint64_t sim_time = 1100; contextp->debug(0); contextp->commandArgs(argc, argv); const std::unique_ptr topp{new VM_PREFIX{contextp.get(), // Note null name - we're flattening it out ""}}; #ifdef VERILATOR #ifdef TEST_VERBOSE contextp->scopesDump(); #endif #endif #if VM_TRACE contextp->traceEverOn(true); VL_PRINTF("Enabling waves...\n"); VerilatedVcdC* tfp = new VerilatedVcdC; topp->trace(tfp, 99); tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); #endif topp->eval(); topp->clk = 0; contextp->timeInc(10); while (contextp->time() < sim_time && !contextp->gotFinish()) { contextp->timeInc(1); topp->eval(); VerilatedVpi::callValueCbs(); topp->clk = !topp->clk; // mon_do(); #if VM_TRACE if (tfp) tfp->dump(contextp->time()); #endif } if (!contextp->gotFinish()) { vl_fatal(FILENM, __LINE__, "main", "%Error: Timeout; never got a $finish"); } topp->final(); #if VM_TRACE if (tfp) tfp->close(); #endif return 0; } #endif verilator-5.042/test_regress/t/t_mem_fifo.v0000644000542200017500000000613515101701376021366 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2006 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc; initial cyc = 0; reg [63:0] crc; wire [65:0] outData; // From fifo of fifo.v wire [15:0] inData = crc[15:0]; wire [1:0] inWordPtr = crc[17:16]; wire wrEn = crc[20]; wire [1:0] wrPtr = crc[33:32]; wire [1:0] rdPtr = crc[34:33]; fifo fifo ( // Outputs .outData (outData[65:0]), // Inputs .clk (clk), .inWordPtr (inWordPtr[1:0]), .inData (inData[15:0]), .rdPtr (rdPtr), .wrPtr (wrPtr), .wrEn (wrEn)); always @ (posedge clk) begin //$write("[%0t] cyc==%0d crc=%b q=%x\n", $time, cyc, crc, outData); cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; end else if (cyc==90) begin if (outData[63:0] != 64'hd9bcbc276f0984ea) $stop; end else if (cyc==91) begin if (outData[63:0] != 64'hef77cd9b13a866f0) $stop; end else if (cyc==92) begin if (outData[63:0] != 64'h2750cd9b13a866f0) $stop; end else if (cyc==93) begin if (outData[63:0] != 64'h4ea0bc276f0984ea) $stop; end else if (cyc==94) begin if (outData[63:0] != 64'h9d41bc276f0984ea) $stop; end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule module fifo (/*AUTOARG*/ // Outputs outData, // Inputs clk, inWordPtr, inData, wrPtr, rdPtr, wrEn ); parameter fifoDepthLog2 = 1; parameter fifoDepth = 1< BB 1 / BB 2 if (rand_a[1:0] == 2'd0) begin nsp_a = 3'd1; // BB 1 -> BB 4 end else begin nsp_a = 3'd2; // BB 2 -> BB 3 / BB 4 if (rand_a[1:0] == 2'd1) begin nsp_a = 3'd3; // BB3 -> BB 5 break; end end nsp_a = 3'd4; // BB 4 -> BB 5 end while (0); //nsp_a = 3'd5; // BB 5 end `signal(NSP_A, nsp_a); logic [2:0] nsp_b; // Non series-parallel CFG always_comb begin do begin nsp_b = 3'd0; if (rand_a[1:0] == 2'd0) begin nsp_b = 3'd1; end else begin nsp_b = 3'd2; if (rand_a[1:0] == 2'd1) begin nsp_b = 3'd3; break; end else begin nsp_b = 3'd4; if (rand_a[1:0] == 2'd2) begin nsp_b = 3'd5; end else begin nsp_b = 3'd6; break; end end end nsp_b = 3'd7; end while (0); end `signal(NSP_B, nsp_b); logic [2:0] part_sp_a; // Contains series-parallel sub-graph CFG always_comb begin do begin part_sp_a = 3'd0; if (rand_a[0]) begin part_sp_a = 3'd1; if (rand_a[1]) begin part_sp_a = 3'd2; end end else begin part_sp_a = 3'd3; if (rand_a[2]) begin part_sp_a = 3'd4; if (rand_a[3]) begin part_sp_a = 3'd5; end break; end end part_sp_a = 3'd6; if (rand_a[4]) begin part_sp_a = 3'd7; end end while (0); end `signal(PART_SP_A, part_sp_a); logic [1:0] both_break; always_comb begin do begin if (rand_a[0]) begin both_break = 2'd0; break; end else begin both_break = 2'd1; break; end // Unreachable if (rand_a[1]) begin both_break = 2'd2; end end while(0); end `signal(BOTH_BREAK, both_break); endmodule verilator-5.042/test_regress/t/t_property_sexpr_parse_unsup.py0000755000542200017500000000121415101701376025515 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_property_sexpr_unsup.v" test.lint(expect_filename=test.golden_filename, verilator_flags2=['-DPARSING_TIME', '--assert', '--timing', '--error-limit 1000'], fails=True) test.passes() verilator-5.042/test_regress/t/t_lint_latch_bad.v0000644000542200017500000000104315101701376022525 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs bl, cl, bc, cc, // Inputs a ); input logic a; output logic bl; output logic cl; always_latch begin bl <= a; // No warning cl = a; end output logic bc; output logic cc; always_comb begin bc <= a; // Warning cc = a; end endmodule verilator-5.042/test_regress/t/t_clk_vecgen2.py0000755000542200017500000000104015101701376022143 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_clk_vecgen1.v" test.compile(v_flags2=['+define+T_TEST2']) test.execute() test.passes() verilator-5.042/test_regress/t/t_dynarray_bits.out0000644000542200017500000000121315101701376023011 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_dynarray_bits.v:12:11: Unsupported: $bits for dynamic array : ... note: In instance 't' 12 | if ($bits(a) != 0) $stop; | ^~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Internal Error: t/t_dynarray_bits.v:12:11: ../V3Width.cpp:#: Node has no type : ... note: In instance 't' 12 | if ($bits(a) != 0) $stop; | ^~~~~ ... This fatal error may be caused by the earlier error(s); resolve those first. verilator-5.042/test_regress/t/t_select_bad_tri.out0000644000542200017500000000123515101701376023106 0ustar mahmoudyfreeshell%Error: t/t_select_bad_tri.v:11:24: Selection index is constantly unknown or tristated: 1'bx 11 | if (in[( (1'h0 / 1'b0) )+:71] != 71'h0) $stop; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Internal Error: t/t_select_bad_tri.v:11:24: ../V3Number.cpp:#: toUInt with 4-state 1'bx : ... note: In instance 't' 11 | if (in[( (1'h0 / 1'b0) )+:71] != 71'h0) $stop; | ^ ... This fatal error may be caused by the earlier error(s); resolve those first. verilator-5.042/test_regress/t/t_rnd.v0000644000542200017500000000210415101701376020360 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; reg _ranit; reg [2:0] a; reg [33:0] wide; reg unused_r; initial _ranit = 0; always @ (posedge clk) begin : blockName begin // Verify begin/begin is legal unused_r <= 1'b1; end begin end // Verify empty is legal end wire one = 1'b1; wire [7:0] rand_bits = 8'b01xx_xx10; always @ (posedge clk) begin if (!_ranit) begin _ranit <= 1; // a = 3'b1xx; wide <= 34'bx1_00000000_xxxxxxxx_00000000_xxxx0000; if (one !== 1'b1) $stop; if ((rand_bits & 8'b1100_0011) !== 8'b0100_0010) $stop; // $write("*-* All Finished *-*\n"); $finish; end end // verilator lint_off UNUSED wire _unused_ok = |{1'b1, wide}; // verilator lint_on UNUSED endmodule verilator-5.042/test_regress/t/t_var_lifetime_module_bad.v0000644000542200017500000000037515101701376024426 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; automatic int i; endmodule verilator-5.042/test_regress/t/t_clk_first_bad.out0000644000542200017500000000062615101701376022734 0ustar mahmoudyfreeshell%Warning-DEPRECATED: t/t_clk_first_deprecated.v:12:14: sc_clock is ignored 12 | input clk /*verilator sc_clock*/ ; | ^~~~~~~~~~~~~~~~~~~~~~ ... For warning description see https://verilator.org/warn/DEPRECATED?v=latest ... Use "/* verilator lint_off DEPRECATED */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_class_param_unused_default.py0000755000542200017500000000073415101701376025346 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_std_waiver.py0000755000542200017500000000070615101701376022140 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint() test.passes() verilator-5.042/test_regress/t/t_class_wide.v0000644000542200017500000000111315101701376021711 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Jomit626. // SPDX-License-Identifier: CC0-1.0 `ifndef WIDTH `define WIDTH 128 `endif class item; bit [`WIDTH-1:0] data; endclass module t (); logic [`WIDTH-1:0] data; item item0 = new; initial begin item0.data = `WIDTH'hda7ada7a; data = item0.data; if (data != `WIDTH'hda7ada7a) $stop(); $write("*-* All Finished *-*\n"); $finish(); end endmodule verilator-5.042/test_regress/t/t_func_const_struct_bad.out0000644000542200017500000000210015101701376024506 0ustar mahmoudyfreeshell%Warning-USERFATAL: "f_add = 15" ... For warning description see https://verilator.org/warn/USERFATAL?v=latest ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. %Error: t/t_func_const_struct_bad.v:17:21: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2' : ... note: In instance 't' t/t_func_const_struct_bad.v:28:9: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing t/t_func_const_struct_bad.v:38:16: ... Called from 'f_add()' with parameters: params = '{a: 32'h7, b: 32'h8} t/t_func_const_struct_bad.v:17:21: ... Called from 'f_add2()' with parameters: a = ?32?h7 b = ?32?h8 c = ?32?h9 17 | localparam P24 = f_add2(7, 8, 9); | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_difftree.b.tree0000644000542200017500000000140015101701376022275 0ustar mahmoudyfreeshellVerilator Tree Dump (format 0x3900) from to NETLIST 0x55d6994da000 {a0aa} $root [1ps/1ps] 1: MODULE 0x55d6994e4120 {d19ai} t L2 [1ps] 1:2: PORT 0x55d6994ea0d0 {d21ae} clk 1:2: VAR 0x55d6994e2180 {d23ak} @dt=0@ clkmod INPUT PORT 1:2:1: BASICDTYPE 0x55d6994ea1a0 {d23ak} @dt=this@(nw0) LOGIC_IMPLICIT kwd=LOGIC_IMPLICIT 3: TYPETABLE 0x55d6994e0000 {a0aa} logic -> BASICDTYPE 0x55d699595a00 {d55ap} @dt=this@(G/nw1) logic [GENERIC] kwd=logic 3: CONSTPOOL 0x55d6994e2000 {a0aa} 3:1: MODULE 0x55d6994e4000 {a0aa} @CONST-POOL@ L0 [NONE] 3:1:2: SCOPE 0x55d6994da0f0 {a0aa} @CONST-POOL@ [abovep=0] [cellp=0] [modp=0x55d6994e4000] verilator-5.042/test_regress/t/t_array_method_bad.out0000644000542200017500000000045515101701376023432 0ustar mahmoudyfreeshell%Error: t/t_array_method_bad.v:11:9: Unknown built-in array method 'mex' : ... note: In instance 't' 11 | q.mex; | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_dpi_arg_inout_type.v0000644000542200017500000012664315101701376023500 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2020 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VCS `define NO_TIME `endif `ifdef NC `define NO_TIME `define NO_INTEGER `define NO_SHORTREAL `endif `ifdef MS `endif `ifdef VERILATOR `define NO_SHORTREAL `define NULL 64'd0 `else `define NULL null `endif module t (/*AUTOARG*/ // Inputs clk ); input clk; `ifdef VERILATOR wire _unused = &{1'b0, clk}; `endif // Legal inout argument types for DPI functions //====================================================================== // Type definitions //====================================================================== // Basic types as per IEEE 1800-2023 35.5.6 typedef byte byte_t; typedef byte unsigned byte_unsigned_t; typedef shortint shortint_t; typedef shortint unsigned shortint_unsigned_t; typedef int int_t; typedef int unsigned int_unsigned_t; typedef longint longint_t; typedef longint unsigned longint_unsigned_t; `ifndef NO_TIME typedef time time_t; `endif `ifndef NO_INTEGER typedef integer integer_t; `endif typedef real real_t; `ifndef NO_SHORTREAL typedef shortreal shortreal_t; `endif typedef chandle chandle_t; typedef string string_t; typedef bit bit_t; typedef logic logic_t; // 2-state packed structures typedef struct packed { bit x; } struct_2_state_1; typedef struct packed { bit [15:0] x; bit [15:0] y; } struct_2_state_32; typedef struct packed { bit [15:0] x; bit [16:0] y; } struct_2_state_33; typedef struct packed { bit [31:0] x; bit [31:0] y; } struct_2_state_64; typedef struct packed { bit [31:0] x; bit [32:0] y; } struct_2_state_65; typedef struct packed { bit [63:0] x; bit [63:0] y; } struct_2_state_128; // 2-state packed unions typedef union packed { bit x; bit y; } union_2_state_1; typedef union packed { bit [31:0] x; bit [31:0] y; } union_2_state_32; typedef union packed { bit [32:0] x; bit [32:0] y; } union_2_state_33; typedef union packed { bit [63:0] x; bit [63:0] y; } union_2_state_64; typedef union packed { bit [64:0] x; bit [64:0] y; } union_2_state_65; typedef union packed { bit [127:0] x; bit [127:0] y; } union_2_state_128; // 4-state packed structures typedef struct packed { logic x; } struct_4_state_1; typedef struct packed { logic [15:0] x; bit [15:0] y; } struct_4_state_32; typedef struct packed { logic [15:0] x; bit [16:0] y; } struct_4_state_33; typedef struct packed { logic [31:0] x; bit [31:0] y; } struct_4_state_64; typedef struct packed { logic [31:0] x; bit [32:0] y; } struct_4_state_65; typedef struct packed { logic [63:0] x; bit [63:0] y; } struct_4_state_128; // 4-state packed unions typedef union packed { logic x; bit y; } union_4_state_1; typedef union packed { logic [31:0] x; bit [31:0] y; } union_4_state_32; typedef union packed { logic [32:0] x; bit [32:0] y; } union_4_state_33; typedef union packed { logic [63:0] x; bit [63:0] y; } union_4_state_64; typedef union packed { logic [64:0] x; bit [64:0] y; } union_4_state_65; typedef union packed { logic [127:0] x; bit [127:0] y; } union_4_state_128; //====================================================================== // Imports //====================================================================== // Basic types as per IEEE 1800-2023 35.5.6 import "DPI-C" function void i_byte (inout byte x); import "DPI-C" function void i_byte_unsigned (inout byte unsigned x); import "DPI-C" function void i_shortint (inout shortint x); import "DPI-C" function void i_shortint_unsigned (inout shortint unsigned x); import "DPI-C" function void i_int (inout int x); import "DPI-C" function void i_int_unsigned (inout int unsigned x); import "DPI-C" function void i_longint (inout longint x); import "DPI-C" function void i_longint_unsigned (inout longint unsigned x); `ifndef NO_TIME import "DPI-C" function void i_time (inout time x); `endif `ifndef NO_INTEGER import "DPI-C" function void i_integer (inout integer x); `endif import "DPI-C" function void i_real (inout real x); `ifndef NO_SHORTREAL import "DPI-C" function void i_shortreal (inout shortreal x); `endif import "DPI-C" function void i_chandle (inout chandle x); import "DPI-C" function void i_string (inout string x); import "DPI-C" function void i_bit (inout bit x); import "DPI-C" function void i_logic (inout logic x); // Basic types via typedef import "DPI-C" function void i_byte_t (inout byte_t x); import "DPI-C" function void i_byte_unsigned_t (inout byte_unsigned_t x); import "DPI-C" function void i_shortint_t (inout shortint_t x); import "DPI-C" function void i_shortint_unsigned_t (inout shortint_unsigned_t x); import "DPI-C" function void i_int_t (inout int_t x); import "DPI-C" function void i_int_unsigned_t (inout int_unsigned_t x); import "DPI-C" function void i_longint_t (inout longint_t x); import "DPI-C" function void i_longint_unsigned_t (inout longint_unsigned_t x); `ifndef NO_TIME import "DPI-C" function void i_time_t (inout time_t x); `endif `ifndef NO_INTEGER import "DPI-C" function void i_integer_t (inout integer_t x); `endif import "DPI-C" function void i_real_t (inout real_t x); `ifndef NO_SHORTREAL import "DPI-C" function void i_shortreal_t (inout shortreal_t x); `endif import "DPI-C" function void i_chandle_t (inout chandle_t x); import "DPI-C" function void i_string_t (inout string_t x); import "DPI-C" function void i_bit_t (inout bit_t x); import "DPI-C" function void i_logic_t (inout logic_t x); // 2-state packed arrays import "DPI-C" function void i_array_2_state_1 (inout bit [ 0:0] x); import "DPI-C" function void i_array_2_state_32 (inout bit [ 31:0] x); import "DPI-C" function void i_array_2_state_33 (inout bit [ 32:0] x); import "DPI-C" function void i_array_2_state_64 (inout bit [ 63:0] x); import "DPI-C" function void i_array_2_state_65 (inout bit [ 64:0] x); import "DPI-C" function void i_array_2_state_128(inout bit [127:0] x); // 2-state packed structures import "DPI-C" function void i_struct_2_state_1 (inout struct_2_state_1 x); import "DPI-C" function void i_struct_2_state_32 (inout struct_2_state_32 x); import "DPI-C" function void i_struct_2_state_33 (inout struct_2_state_33 x); import "DPI-C" function void i_struct_2_state_64 (inout struct_2_state_64 x); import "DPI-C" function void i_struct_2_state_65 (inout struct_2_state_65 x); import "DPI-C" function void i_struct_2_state_128 (inout struct_2_state_128 x); // 2-state packed unions import "DPI-C" function void i_union_2_state_1 (inout union_2_state_1 x); import "DPI-C" function void i_union_2_state_32 (inout union_2_state_32 x); import "DPI-C" function void i_union_2_state_33 (inout union_2_state_33 x); import "DPI-C" function void i_union_2_state_64 (inout union_2_state_64 x); import "DPI-C" function void i_union_2_state_65 (inout union_2_state_65 x); import "DPI-C" function void i_union_2_state_128 (inout union_2_state_128 x); // 4-state packed arrays import "DPI-C" function void i_array_4_state_1 (inout logic [ 0:0] x); import "DPI-C" function void i_array_4_state_32 (inout logic [ 31:0] x); import "DPI-C" function void i_array_4_state_33 (inout logic [ 32:0] x); import "DPI-C" function void i_array_4_state_64 (inout logic [ 63:0] x); import "DPI-C" function void i_array_4_state_65 (inout logic [ 64:0] x); import "DPI-C" function void i_array_4_state_128(inout logic [127:0] x); // 4-state packed structures import "DPI-C" function void i_struct_4_state_1 (inout struct_4_state_1 x); import "DPI-C" function void i_struct_4_state_32 (inout struct_4_state_32 x); import "DPI-C" function void i_struct_4_state_33 (inout struct_4_state_33 x); import "DPI-C" function void i_struct_4_state_64 (inout struct_4_state_64 x); import "DPI-C" function void i_struct_4_state_65 (inout struct_4_state_65 x); import "DPI-C" function void i_struct_4_state_128 (inout struct_4_state_128 x); // 4-state packed unions import "DPI-C" function void i_union_4_state_1 (inout union_4_state_1 x); import "DPI-C" function void i_union_4_state_32 (inout union_4_state_32 x); import "DPI-C" function void i_union_4_state_33 (inout union_4_state_33 x); import "DPI-C" function void i_union_4_state_64 (inout union_4_state_64 x); import "DPI-C" function void i_union_4_state_65 (inout union_4_state_65 x); import "DPI-C" function void i_union_4_state_128 (inout union_4_state_128 x); //====================================================================== // Exports //====================================================================== // Basic types as per IEEE 1800-2023 35.5.6 export "DPI-C" function e_byte; export "DPI-C" function e_byte_unsigned; export "DPI-C" function e_shortint; export "DPI-C" function e_shortint_unsigned; export "DPI-C" function e_int; export "DPI-C" function e_int_unsigned; export "DPI-C" function e_longint; export "DPI-C" function e_longint_unsigned; `ifndef NO_TIME export "DPI-C" function e_time; `endif `ifndef NO_INTEGER export "DPI-C" function e_integer; `endif export "DPI-C" function e_real; `ifndef NO_SHORTREAL export "DPI-C" function e_shortreal; `endif export "DPI-C" function e_chandle; export "DPI-C" function e_string; export "DPI-C" function e_bit; export "DPI-C" function e_logic; // Basic types via typedef export "DPI-C" function e_byte_t; export "DPI-C" function e_byte_unsigned_t; export "DPI-C" function e_shortint_t; export "DPI-C" function e_shortint_unsigned_t; export "DPI-C" function e_int_t; export "DPI-C" function e_int_unsigned_t; export "DPI-C" function e_longint_t; export "DPI-C" function e_longint_unsigned_t; `ifndef NO_TIME export "DPI-C" function e_time_t; `endif `ifndef NO_INTEGER export "DPI-C" function e_integer_t; `endif export "DPI-C" function e_real_t; `ifndef NO_SHORTREAL export "DPI-C" function e_shortreal_t; `endif export "DPI-C" function e_chandle_t; export "DPI-C" function e_string_t; export "DPI-C" function e_bit_t; export "DPI-C" function e_logic_t; // 2-state packed arrays export "DPI-C" function e_array_2_state_1; export "DPI-C" function e_array_2_state_32; export "DPI-C" function e_array_2_state_33; export "DPI-C" function e_array_2_state_64; export "DPI-C" function e_array_2_state_65; export "DPI-C" function e_array_2_state_128; // 2-state packed structures export "DPI-C" function e_struct_2_state_1; export "DPI-C" function e_struct_2_state_32; export "DPI-C" function e_struct_2_state_33; export "DPI-C" function e_struct_2_state_64; export "DPI-C" function e_struct_2_state_65; export "DPI-C" function e_struct_2_state_128; // 2-state packed unions export "DPI-C" function e_union_2_state_1; export "DPI-C" function e_union_2_state_32; export "DPI-C" function e_union_2_state_33; export "DPI-C" function e_union_2_state_64; export "DPI-C" function e_union_2_state_65; export "DPI-C" function e_union_2_state_128; // 4-state packed arrays export "DPI-C" function e_array_4_state_1; export "DPI-C" function e_array_4_state_32; export "DPI-C" function e_array_4_state_33; export "DPI-C" function e_array_4_state_64; export "DPI-C" function e_array_4_state_65; export "DPI-C" function e_array_4_state_128; // 4-state packed structures export "DPI-C" function e_struct_4_state_1; export "DPI-C" function e_struct_4_state_32; export "DPI-C" function e_struct_4_state_33; export "DPI-C" function e_struct_4_state_64; export "DPI-C" function e_struct_4_state_65; export "DPI-C" function e_struct_4_state_128; // 4-state packed unions export "DPI-C" function e_union_4_state_1; export "DPI-C" function e_union_4_state_32; export "DPI-C" function e_union_4_state_33; export "DPI-C" function e_union_4_state_64; export "DPI-C" function e_union_4_state_65; export "DPI-C" function e_union_4_state_128; //====================================================================== // Definitions of exported functions //====================================================================== // Basic types as per IEEE 1800-2023 35.5.6 byte n_byte = 0; function void e_byte(inout byte x); if (x !== 8'd10 + n_byte) $stop; x += 8'd100; n_byte++; endfunction byte n_byte_unsigned = 0; function void e_byte_unsigned(inout byte unsigned x); if (x !== 8'd20 + n_byte_unsigned) $stop; x += 8'd200; n_byte_unsigned++; endfunction shortint n_shortint = 0; function void e_shortint(inout shortint x); if (x !== 16'd30 + n_shortint) $stop; x += 16'd300; n_shortint++; endfunction shortint n_shortint_unsigned = 0; function void e_shortint_unsigned(inout shortint unsigned x); if (x !== 16'd40 + n_shortint_unsigned) $stop; x += 16'd400; n_shortint_unsigned++; endfunction int n_int = 0; function void e_int(inout int x); if (x !== 32'd50 + n_int) $stop; x += 32'd500; n_int++; endfunction int n_int_unsigned = 0; function void e_int_unsigned(inout int unsigned x); if (x !== 32'd60 + n_int_unsigned) $stop; x += 32'd600; n_int_unsigned++; endfunction longint n_longint = 0; function void e_longint(inout longint x); if (x !== 64'd70 + n_longint) $stop; x += 64'd700; n_longint++; endfunction longint n_longint_unsigned = 0; function void e_longint_unsigned(inout longint unsigned x); if (x !== 64'd80 + n_longint_unsigned) $stop; x += 64'd800; n_longint_unsigned++; endfunction `ifndef NO_TIME longint n_time = 0; function void e_time(inout time x); if (x !== 64'd90 + n_time) $stop; x += 64'd900; n_time++; endfunction `endif `ifndef NO_INTEGER int n_integer = 0; function void e_integer(inout integer x); if (x !== 32'd100 + n_integer) $stop; x += 32'd1000; n_integer++; endfunction `endif int n_real = 0; function void e_real(inout real x); if (x != real'(2*n_real + 1) / 2.0) $stop; x += 100.0; n_real++; endfunction `ifndef NO_SHORTREAL int n_shortreal = 0; function void e_shortreal(inout shortreal x); if (x != shortreal'(4*n_shortreal + 1)/ 4.0) $stop; x += 200.0; n_shortreal++; endfunction `endif int n_chandle = 0; function void e_chandle(inout chandle x); $display("e_chandle %1d", n_chandle); if (!n_chandle[0]) begin if (x === `NULL) $stop; end else begin if (x !== `NULL) $stop; end x = `NULL; n_chandle++; endfunction int n_string = 0; function void e_string(inout string x); $display("e_string %1d", n_string); if (!n_string[0]) begin if (x != "Good") $stop; x = "Hello"; end else begin if (x != "Bye") $stop; x = "World"; end n_string++; endfunction int n_bit = 0; function void e_bit(inout bit x); $display("e_bit %1d", n_bit); if (x !== n_bit[0]) $stop; x = ~x; n_bit++; endfunction int n_logic = 0; function void e_logic(inout logic x); $display("e_logic %1d", n_logic); if (x !== ~n_logic[0]) $stop; x = ~x; n_logic++; endfunction // Basic types via typedefs byte_t n_byte_t = 0; function void e_byte_t(inout byte_t x); if (x !== 8'd10 + n_byte_t) $stop; x += 8'd101; n_byte_t += 2; endfunction byte n_byte_unsigned_t = 0; function void e_byte_unsigned_t(inout byte_unsigned_t x); if (x !== 8'd20 + n_byte_unsigned_t) $stop; x += 8'd202; n_byte_unsigned_t += 2; endfunction shortint_t n_shortint_t = 0; function void e_shortint_t(inout shortint_t x); if (x !== 16'd30 + n_shortint_t) $stop; x += 16'd303; n_shortint_t += 2; endfunction shortint n_shortint_unsigned_t = 0; function void e_shortint_unsigned_t(inout shortint_unsigned_t x); if (x !== 16'd40 + n_shortint_unsigned_t) $stop; x += 16'd404; n_shortint_unsigned_t += 2; endfunction int_t n_int_t = 0; function void e_int_t(inout int_t x); if (x !== 32'd50 + n_int_t) $stop; x += 32'd505; n_int_t += 2; endfunction int n_int_unsigned_t = 0; function void e_int_unsigned_t(inout int_unsigned_t x); if (x !== 32'd60 + n_int_unsigned_t) $stop; x += 32'd606; n_int_unsigned_t += 2; endfunction longint_t n_longint_t = 0; function void e_longint_t(inout longint_t x); if (x !== 64'd70 + n_longint_t) $stop; x += 64'd707; n_longint_t += 2; endfunction longint n_longint_unsigned_t = 0; function void e_longint_unsigned_t(inout longint_unsigned_t x); if (x !== 64'd80 + n_longint_unsigned_t) $stop; x += 64'd808; n_longint_unsigned_t += 2; endfunction `ifndef NO_TIME longint n_time_t = 0; function void e_time_t(inout time_t x); if (x !== 64'd90 + n_time_t) $stop; x += 64'd909; n_time_t += 2; endfunction `endif `ifndef NO_INTEGER int n_integer_t = 0; function void e_integer_t(inout integer_t x); if (x !== 32'd100 + n_integer_t) $stop; x += 32'd1001; n_integer_t += 2; endfunction `endif int n_real_t = 0; function void e_real_t(inout real_t x); if (x != real'(2*n_real_t + 1) / 2.0) $stop; x += 111.0; n_real_t += 2; endfunction `ifndef NO_SHORTREAL int n_shortreal_t = 0; function void e_shortreal_t(inout shortreal_t x); if (x != shortreal'(4*n_shortreal_t + 1)/ 4.0) $stop; x += 222.0; n_shortreal_t += 2; endfunction `endif int n_chandle_t = 0; function void e_chandle_t(inout chandle_t x); $display("e_chandle_t %1d", n_chandle_t); if (!n_chandle_t[0]) begin if (x !== `NULL) $stop; end else begin if (x === `NULL) $stop; end x = `NULL; n_chandle_t++; endfunction int n_string_t = 0; function void e_string_t(inout string_t x); $display("e_string_t %1d", n_string_t); if (!n_string_t[0]) begin if (x != "Bye") $stop; x = "World"; end else begin if (x != "Good") $stop; x = "Hello"; end n_string_t++; endfunction int n_bit_t = 0; function void e_bit_t(inout bit_t x); $display("e_bit_t %1d", n_bit_t); if (x !== n_bit_t[0]) $stop; x = ~x; n_bit_t++; endfunction int n_logic_t = 0; function void e_logic_t(inout logic_t x); $display("e_logic_t %1d", n_logic_t); if (x !== ~n_logic_t[0]) $stop; x = ~x; n_logic_t++; endfunction // 2-state packed arrays int n_array_2_state_1 = 0; function void e_array_2_state_1(inout bit [ 0:0] x); $display("e_array_2_state_1 %1d", n_array_2_state_1); if (x !== n_array_2_state_1[0]) $stop; x = ~x; n_array_2_state_1++; endfunction int n_array_2_state_32 = 0; function void e_array_2_state_32(inout bit [31:0] x); $display("e_array_2_state_32 %1d", n_array_2_state_32); if (x !== ~32'd0 >> n_array_2_state_32) $stop; x <<= n_array_2_state_32; n_array_2_state_32++; endfunction int n_array_2_state_33 = 0; function void e_array_2_state_33(inout bit [32:0] x); $display("e_array_2_state_33 %1d", n_array_2_state_33); if (x !== ~33'd0 >> n_array_2_state_33) $stop; x <<= n_array_2_state_33; n_array_2_state_33++; endfunction int n_array_2_state_64 = 0; function void e_array_2_state_64(inout bit [63:0] x); $display("e_array_2_state_64 %1d", n_array_2_state_64); if (x !== ~64'd0 >> n_array_2_state_64) $stop; x <<= n_array_2_state_64; n_array_2_state_64++; endfunction int n_array_2_state_65 = 0; function void e_array_2_state_65(inout bit [64:0] x); $display("e_array_2_state_65 %1d", n_array_2_state_65); if (x !== ~65'd0 >> n_array_2_state_65) $stop; x <<= n_array_2_state_65; n_array_2_state_65++; endfunction int n_array_2_state_128 = 0; function void e_array_2_state_128(inout bit [127:0] x); $display("e_array_2_state_128 %1d", n_array_2_state_128); if (x !== ~128'd0 >> n_array_2_state_128) $stop; x <<= n_array_2_state_128; n_array_2_state_128++; endfunction // 2-state packed structures int n_struct_2_state_1 = 0; function void e_struct_2_state_1(inout struct_2_state_1 x); $display("e_struct_2_state_1 %1d", n_struct_2_state_1); if (x !== n_struct_2_state_1[0]) $stop; x = ~x; n_struct_2_state_1++; endfunction int n_struct_2_state_32 = 0; function void e_struct_2_state_32(inout struct_2_state_32 x); $display("e_struct_2_state_32 %1d", n_struct_2_state_32); if (x !== ~32'd0 >> n_struct_2_state_32) $stop; x <<= n_struct_2_state_32; n_struct_2_state_32++; endfunction int n_struct_2_state_33 = 0; function void e_struct_2_state_33(inout struct_2_state_33 x); $display("e_struct_2_state_33 %1d", n_struct_2_state_33); if (x !== ~33'd0 >> n_struct_2_state_33) $stop; x <<= n_struct_2_state_33; n_struct_2_state_33++; endfunction int n_struct_2_state_64 = 0; function void e_struct_2_state_64(inout struct_2_state_64 x); $display("e_struct_2_state_64 %1d", n_struct_2_state_64); if (x !== ~64'd0 >> n_struct_2_state_64) $stop; x <<= n_struct_2_state_64; n_struct_2_state_64++; endfunction int n_struct_2_state_65 = 0; function void e_struct_2_state_65(inout struct_2_state_65 x); $display("e_struct_2_state_65 %1d", n_struct_2_state_65); if (x !== ~65'd0 >> n_struct_2_state_65) $stop; x <<= n_struct_2_state_65; n_struct_2_state_65++; endfunction int n_struct_2_state_128 = 0; function void e_struct_2_state_128(inout struct_2_state_128 x); $display("e_struct_2_state_128 %1d", n_struct_2_state_128); if (x !== ~128'd0 >> n_struct_2_state_128) $stop; x <<= n_struct_2_state_128; n_struct_2_state_128++; endfunction // 2-state packed unions int n_union_2_state_1 = 0; function void e_union_2_state_1(inout union_2_state_1 x); $display("e_union_2_state_1 %1d", n_union_2_state_1); if (x !== n_union_2_state_1[0]) $stop; x = ~x; n_union_2_state_1++; endfunction int n_union_2_state_32 = 0; function void e_union_2_state_32(inout union_2_state_32 x); $display("e_union_2_state_32 %1d", n_union_2_state_32); if (x !== ~32'd0 >> n_union_2_state_32) $stop; x <<= n_union_2_state_32; n_union_2_state_32++; endfunction int n_union_2_state_33 = 0; function void e_union_2_state_33(inout union_2_state_33 x); $display("e_union_2_state_33 %1d", n_union_2_state_33); if (x !== ~33'd0 >> n_union_2_state_33) $stop; x <<= n_union_2_state_33; n_union_2_state_33++; endfunction int n_union_2_state_64 = 0; function void e_union_2_state_64(inout union_2_state_64 x); $display("e_union_2_state_64 %1d", n_union_2_state_64); if (x !== ~64'd0 >> n_union_2_state_64) $stop; x <<= n_union_2_state_64; n_union_2_state_64++; endfunction int n_union_2_state_65 = 0; function void e_union_2_state_65(inout union_2_state_65 x); $display("e_union_2_state_65 %1d", n_union_2_state_65); if (x !== ~65'd0 >> n_union_2_state_65) $stop; x <<= n_union_2_state_65; n_union_2_state_65++; endfunction int n_union_2_state_128 = 0; function void e_union_2_state_128(inout union_2_state_128 x); $display("e_union_2_state_128 %1d", n_union_2_state_128); if (x !== ~128'd0 >> n_union_2_state_128) $stop; x <<= n_union_2_state_128; n_union_2_state_128++; endfunction // 4-state packed arrays int n_array_4_state_1 = 0; function void e_array_4_state_1(inout logic [ 0:0] x); $display("e_array_4_state_1 %1d", n_array_4_state_1); if (x !== n_array_4_state_1[0]) $stop; x = ~x; n_array_4_state_1++; endfunction int n_array_4_state_32 = 0; function void e_array_4_state_32(inout logic [31:0] x); $display("e_array_4_state_32 %1d", n_array_4_state_32); if (x !== ~32'd0 >> n_array_4_state_32) $stop; x <<= n_array_4_state_32; n_array_4_state_32++; endfunction int n_array_4_state_33 = 0; function void e_array_4_state_33(inout logic [32:0] x); $display("e_array_4_state_33 %1d", n_array_4_state_33); if (x !== ~33'd0 >> n_array_4_state_33) $stop; x <<= n_array_4_state_33; n_array_4_state_33++; endfunction int n_array_4_state_64 = 0; function void e_array_4_state_64(inout logic [63:0] x); $display("e_array_4_state_64 %1d", n_array_4_state_64); if (x !== ~64'd0 >> n_array_4_state_64) $stop; x <<= n_array_4_state_64; n_array_4_state_64++; endfunction int n_array_4_state_65 = 0; function void e_array_4_state_65(inout logic [64:0] x); $display("e_array_4_state_65 %1d", n_array_4_state_65); if (x !== ~65'd0 >> n_array_4_state_65) $stop; x <<= n_array_4_state_65; n_array_4_state_65++; endfunction int n_array_4_state_128 = 0; function void e_array_4_state_128(inout logic [127:0] x); $display("e_array_4_state_128 %1d", n_array_4_state_128); if (x !== ~128'd0 >> n_array_4_state_128) $stop; x <<= n_array_4_state_128; n_array_4_state_128++; endfunction // 4-state packed structures int n_struct_4_state_1 = 0; function void e_struct_4_state_1(inout struct_4_state_1 x); $display("e_struct_4_state_1 %1d", n_struct_4_state_1); if (x !== n_struct_4_state_1[0]) $stop; x = ~x; n_struct_4_state_1++; endfunction int n_struct_4_state_32 = 0; function void e_struct_4_state_32(inout struct_4_state_32 x); $display("e_struct_4_state_32 %1d", n_struct_4_state_32); if (x !== ~32'd0 >> n_struct_4_state_32) $stop; x <<= n_struct_4_state_32; n_struct_4_state_32++; endfunction int n_struct_4_state_33 = 0; function void e_struct_4_state_33(inout struct_4_state_33 x); $display("e_struct_4_state_33 %1d", n_struct_4_state_33); if (x !== ~33'd0 >> n_struct_4_state_33) $stop; x <<= n_struct_4_state_33; n_struct_4_state_33++; endfunction int n_struct_4_state_64 = 0; function void e_struct_4_state_64(inout struct_4_state_64 x); $display("e_struct_4_state_64 %1d", n_struct_4_state_64); if (x !== ~64'd0 >> n_struct_4_state_64) $stop; x <<= n_struct_4_state_64; n_struct_4_state_64++; endfunction int n_struct_4_state_65 = 0; function void e_struct_4_state_65(inout struct_4_state_65 x); $display("e_struct_4_state_65 %1d", n_struct_4_state_65); if (x !== ~65'd0 >> n_struct_4_state_65) $stop; x <<= n_struct_4_state_65; n_struct_4_state_65++; endfunction int n_struct_4_state_128 = 0; function void e_struct_4_state_128(inout struct_4_state_128 x); $display("e_struct_4_state_128 %1d", n_struct_4_state_128); if (x !== ~128'd0 >> n_struct_4_state_128) $stop; x <<= n_struct_4_state_128; n_struct_4_state_128++; endfunction // 4-state packed unions int n_union_4_state_1 = 0; function void e_union_4_state_1(inout union_4_state_1 x); $display("e_union_4_state_1 %1d", n_union_4_state_1); if (x !== n_union_4_state_1[0]) $stop; x = ~x; n_union_4_state_1++; endfunction int n_union_4_state_32 = 0; function void e_union_4_state_32(inout union_4_state_32 x); $display("e_union_4_state_32 %1d", n_union_4_state_32); if (x !== ~32'd0 >> n_union_4_state_32) $stop; x <<= n_union_4_state_32; n_union_4_state_32++; endfunction int n_union_4_state_33 = 0; function void e_union_4_state_33(inout union_4_state_33 x); $display("e_union_4_state_33 %1d", n_union_4_state_33); if (x !== ~33'd0 >> n_union_4_state_33) $stop; x <<= n_union_4_state_33; n_union_4_state_33++; endfunction int n_union_4_state_64 = 0; function void e_union_4_state_64(inout union_4_state_64 x); $display("e_union_4_state_64 %1d", n_union_4_state_64); if (x !== ~64'd0 >> n_union_4_state_64) $stop; x <<= n_union_4_state_64; n_union_4_state_64++; endfunction int n_union_4_state_65 = 0; function void e_union_4_state_65(inout union_4_state_65 x); $display("e_union_4_state_65 %1d", n_union_4_state_65); if (x !== ~65'd0 >> n_union_4_state_65) $stop; x <<= n_union_4_state_65; n_union_4_state_65++; endfunction int n_union_4_state_128 = 0; function void e_union_4_state_128(inout union_4_state_128 x); $display("e_union_4_state_128 %1d", n_union_4_state_128); if (x !== ~128'd0 >> n_union_4_state_128) $stop; x <<= n_union_4_state_128; n_union_4_state_128++; endfunction //====================================================================== // Invoke all functions 3 times (they have side effects) //====================================================================== import "DPI-C" context function void check_exports(); initial begin for (int i = 0 ; i < 3; i++) begin // Check the imports byte x_byte; byte unsigned x_byte_unsigned; shortint x_shortint; shortint unsigned x_shortint_unsigned; int x_int; int unsigned x_int_unsigned; longint x_longint; longint unsigned x_longint_unsigned; `ifndef NO_TIME time x_time; `endif `ifndef NO_INTEGER integer x_integer; `endif real x_real; `ifndef NO_SHORTREAL shortreal x_shortreal; `endif chandle x_chandle; string x_string; bit x_bit; logic x_logic; byte_t x_byte_t; byte_unsigned_t x_byte_unsigned_t; shortint_t x_shortint_t; shortint_unsigned_t x_shortint_unsigned_t; int_t x_int_t; int_unsigned_t x_int_unsigned_t; longint_t x_longint_t; longint_unsigned_t x_longint_unsigned_t; `ifndef NO_TIME time_t x_time_t; `endif `ifndef NO_INTEGER integer_t x_integer_t; `endif real_t x_real_t; `ifndef NO_SHORTREAL shortreal_t x_shortreal_t; `endif chandle_t x_chandle_t; string_t x_string_t; bit_t x_bit_t; logic_t x_logic_t; bit [ 0:0] x_bit_1; bit [ 31:0] x_bit_32; bit [ 32:0] x_bit_33; bit [ 63:0] x_bit_64; bit [ 64:0] x_bit_65; bit [127:0] x_bit_128; struct_2_state_1 x_struct_2_state_1; struct_2_state_32 x_struct_2_state_32; struct_2_state_33 x_struct_2_state_33; struct_2_state_64 x_struct_2_state_64; struct_2_state_65 x_struct_2_state_65; struct_2_state_128 x_struct_2_state_128; union_2_state_1 x_union_2_state_1; union_2_state_32 x_union_2_state_32; union_2_state_33 x_union_2_state_33; union_2_state_64 x_union_2_state_64; union_2_state_65 x_union_2_state_65; union_2_state_128 x_union_2_state_128; logic [ 0:0] x_logic_1; logic [ 31:0] x_logic_32; logic [ 32:0] x_logic_33; logic [ 63:0] x_logic_64; logic [ 64:0] x_logic_65; logic [127:0] x_logic_128; struct_4_state_1 x_struct_4_state_1; struct_4_state_32 x_struct_4_state_32; struct_4_state_33 x_struct_4_state_33; struct_4_state_64 x_struct_4_state_64; struct_4_state_65 x_struct_4_state_65; struct_4_state_128 x_struct_4_state_128; union_4_state_1 x_union_4_state_1; union_4_state_32 x_union_4_state_32; union_4_state_33 x_union_4_state_33; union_4_state_64 x_union_4_state_64; union_4_state_65 x_union_4_state_65; union_4_state_128 x_union_4_state_128; // Basic types as per IEEE 1800-2023 35.5.6 x_byte = 8'd10 - 8'(i); i_byte(x_byte); if (x_byte !== 8'd110 - 8'(i)) $stop; x_byte_unsigned = 8'd20 - 8'(i); i_byte_unsigned(x_byte_unsigned); if (x_byte_unsigned !== 8'd220 - 8'(i)) $stop; x_shortint = 16'd30 - 16'(i); i_shortint(x_shortint); if (x_shortint !== 16'd330 - 16'(i)) $stop; x_shortint_unsigned = 16'd40 - 16'(i); i_shortint_unsigned(x_shortint_unsigned); if (x_shortint_unsigned !== 16'd440 - 16'(i)) $stop; x_int = 32'd50 - 32'(i); i_int(x_int); if (x_int !== 32'd550 - 32'(i)) $stop; x_int_unsigned = 32'd60 - 32'(i); i_int_unsigned(x_int_unsigned); if (x_int_unsigned !== 32'd660 - 32'(i)) $stop; x_longint = 64'd70 - 64'(i); i_longint(x_longint); if (x_longint !== 64'd770 - 64'(i)) $stop; x_longint_unsigned = 64'd80 - 64'(i); i_longint_unsigned(x_longint_unsigned); if (x_longint_unsigned !== 64'd880 - 64'(i)) $stop; `ifndef NO_TIME x_time = 64'd90 - 64'(i); i_time(x_time); if (x_time !== 64'd990 - 64'(i)) $stop; `endif `ifndef NO_INTEGER x_integer = 32'd100- 32'(i); i_integer(x_integer); if (x_integer !== 32'd1100- 32'(i)) $stop; `endif x_real = -1.0*i - 0.50; i_real(x_real); if (x_real != -100.0 + -1.0*i - 0.50) $stop; `ifndef NO_SHORTREAL x_shortreal = -1.0*i - 0.25; i_shortreal(x_shortreal); if (x_shortreal != -200.0 + -1.0*i - 0.25) $stop; `endif if (~i[0]) begin x_chandle = `NULL; i_chandle(x_chandle); if (x_chandle !== `NULL) $stop; x_string = "Hello"; i_string(x_string); if (x_string != "Good") $stop; end else begin x_chandle = `NULL; i_chandle(x_chandle); if (x_chandle === `NULL) $stop; x_string = "World"; i_string(x_string); if (x_string != "Bye" ) $stop; end x_bit = ~i[0]; i_bit(x_bit); if (x_bit !== i[0]) $stop; x_logic = i[0]; i_logic(x_logic); if (x_logic !== ~i[0]) $stop; // Basic types via typedefs x_byte_t = 8'd10 - 8'(2*i); i_byte_t(x_byte_t); if (x_byte_t !== 8'd111 - 8'(2*i)) $stop; x_byte_unsigned_t = 8'd20 - 8'(2*i); i_byte_unsigned_t(x_byte_unsigned_t); if (x_byte_unsigned_t !== 8'd222 - 8'(2*i)) $stop; x_shortint_t = 16'd30 - 16'(2*i); i_shortint_t(x_shortint_t); if (x_shortint_t !== 16'd333 - 16'(2*i)) $stop; x_shortint_unsigned_t = 16'd40 - 16'(2*i); i_shortint_unsigned_t(x_shortint_unsigned_t); if (x_shortint_unsigned_t !== 16'd444 - 16'(2*i)) $stop; x_int_t = 32'd50 - 32'(2*i); i_int_t(x_int_t); if (x_int_t !== 32'd555 - 32'(2*i)) $stop; x_int_unsigned_t = 32'd60 - 32'(2*i); i_int_unsigned_t(x_int_unsigned_t); if (x_int_unsigned_t !== 32'd666 - 32'(2*i)) $stop; x_longint_t = 64'd70 - 64'(2*i); i_longint_t(x_longint_t); if (x_longint_t !== 64'd777 - 64'(2*i)) $stop; x_longint_unsigned_t = 64'd80 - 64'(2*i); i_longint_unsigned_t(x_longint_unsigned_t); if (x_longint_unsigned_t !== 64'd888 - 64'(2*i)) $stop; `ifndef NO_TIME x_time_t = 64'd90 - 64'(2*i); i_time_t(x_time_t); if (x_time_t !== 64'd999 - 64'(2*i)) $stop; `endif `ifndef NO_INTEGER x_integer_t = 32'd100- 32'(2*i); i_integer_t(x_integer_t); if (x_integer_t !== 32'd1101- 32'(2*i)) $stop; `endif x_real_t = -1.0*(2*i) - 0.50; i_real_t(x_real_t); if (x_real_t != -111.0 + -1.0*(2*i) - 0.50) $stop; `ifndef NO_SHORTREAL x_shortreal_t = -1.0*(2*i) - 0.25; i_shortreal_t(x_shortreal_t); if (x_shortreal_t != -222.0 + -1.0*(2*i) - 0.25) $stop; `endif if (~i[0]) begin x_chandle_t = `NULL; i_chandle_t(x_chandle_t); if (x_chandle_t === `NULL) $stop; x_string_t = "World"; i_string_t(x_string_t); if (x_string_t != "Bye") $stop; end else begin x_chandle_t = `NULL; i_chandle_t(x_chandle_t); if (x_chandle_t !== `NULL) $stop; x_string_t = "Hello"; i_string_t(x_string_t); if (x_string_t != "Good") $stop; end x_bit_t = ~i[0]; i_bit_t(x_bit_t); if (x_bit_t !== i[0]) $stop; x_logic_t = i[0]; i_logic_t(x_logic_t); if (x_logic_t !== ~i[0]) $stop; // 2-state packed arrays x_bit_1 = ~i[0]; i_array_2_state_1(x_bit_1); if (x_bit_1 !== i[0] ) $stop; x_bit_32 = ~32'd0 << i; i_array_2_state_32(x_bit_32); if (x_bit_32 !== ~32'd0 >> i) $stop; x_bit_33 = ~33'd0 << i; i_array_2_state_33(x_bit_33); if (x_bit_33 !== ~33'd0 >> i) begin $display("%d %x %0x", i, x_bit_33, ~33'd0 >> i); $stop; end x_bit_64 = ~64'd0 << i; i_array_2_state_64(x_bit_64); if (x_bit_64 !== ~64'd0 >> i) $stop; x_bit_65 = ~65'd0 << i; i_array_2_state_65(x_bit_65); if (x_bit_65 !== ~65'd0 >> i) $stop; x_bit_128 = ~128'd0<< i; i_array_2_state_128(x_bit_128); if (x_bit_128 !== ~128'd0>> i) $stop; // 2-state packed structures x_struct_2_state_1 = ~i[0]; i_struct_2_state_1(x_struct_2_state_1); if (x_struct_2_state_1 !== i[0] ) $stop; x_struct_2_state_32 = ~32'd0 << i; i_struct_2_state_32(x_struct_2_state_32); if (x_struct_2_state_32 !== ~32'd0 >> i) $stop; x_struct_2_state_33 = ~33'd0 << i; i_struct_2_state_33(x_struct_2_state_33); if (x_struct_2_state_33 !== ~33'd0 >> i) $stop; x_struct_2_state_64 = ~64'd0 << i; i_struct_2_state_64(x_struct_2_state_64); if (x_struct_2_state_64 !== ~64'd0 >> i) $stop; x_struct_2_state_65 = ~65'd0 << i; i_struct_2_state_65(x_struct_2_state_65); if (x_struct_2_state_65 !== ~65'd0 >> i) $stop; x_struct_2_state_128= ~128'd0<< i; i_struct_2_state_128(x_struct_2_state_128); if (x_struct_2_state_128!== ~128'd0>> i) $stop; // 2-state packed unions x_union_2_state_1 = ~i[0]; i_union_2_state_1(x_union_2_state_1); if (x_union_2_state_1 !== i[0] ) $stop; x_union_2_state_32 = ~32'd0 << i; i_union_2_state_32(x_union_2_state_32); if (x_union_2_state_32 !== ~32'd0 >> i) $stop; x_union_2_state_33 = ~33'd0 << i; i_union_2_state_33(x_union_2_state_33); if (x_union_2_state_33 !== ~33'd0 >> i) $stop; x_union_2_state_64 = ~64'd0 << i; i_union_2_state_64(x_union_2_state_64); if (x_union_2_state_64 !== ~64'd0 >> i) $stop; x_union_2_state_65 = ~65'd0 << i; i_union_2_state_65(x_union_2_state_65); if (x_union_2_state_65 !== ~65'd0 >> i) $stop; x_union_2_state_128 = ~128'd0<< i; i_union_2_state_128(x_union_2_state_128); if (x_union_2_state_128 !== ~128'd0>> i) $stop; // 4-state packed arrays x_logic_1 = ~i[0]; i_array_4_state_1(x_logic_1); if (x_logic_1 !== i[0] ) $stop; x_logic_32 = ~32'd0 << i; i_array_4_state_32(x_logic_32); if (x_logic_32 !== ~32'd0 >> i) $stop; x_logic_33 = ~33'd0 << i; i_array_4_state_33(x_logic_33); if (x_logic_33 !== ~33'd0 >> i) $stop; x_logic_64 = ~64'd0 << i; i_array_4_state_64(x_logic_64); if (x_logic_64 !== ~64'd0 >> i) $stop; x_logic_65 = ~65'd0 << i; i_array_4_state_65(x_logic_65); if (x_logic_65 !== ~65'd0 >> i) $stop; x_logic_128 = ~128'd0<< i; i_array_4_state_128(x_logic_128); if (x_logic_128 !== ~128'd0>> i) $stop; // 4-state packed structures x_struct_4_state_1 = ~i[0]; i_struct_4_state_1(x_struct_4_state_1); if (x_struct_4_state_1 !== i[0] ) $stop; x_struct_4_state_32 = ~32'd0 << i; i_struct_4_state_32(x_struct_4_state_32); if (x_struct_4_state_32 !== ~32'd0 >> i) $stop; x_struct_4_state_33 = ~33'd0 << i; i_struct_4_state_33(x_struct_4_state_33); if (x_struct_4_state_33 !== ~33'd0 >> i) $stop; x_struct_4_state_64 = ~64'd0 << i; i_struct_4_state_64(x_struct_4_state_64); if (x_struct_4_state_64 !== ~64'd0 >> i) $stop; x_struct_4_state_65 = ~65'd0 << i; i_struct_4_state_65(x_struct_4_state_65); if (x_struct_4_state_65 !== ~65'd0 >> i) $stop; x_struct_4_state_128= ~128'd0<< i; i_struct_4_state_128(x_struct_4_state_128); if (x_struct_4_state_128!== ~128'd0>> i) $stop; // 4-state packed unions x_union_4_state_1 = ~i[0]; i_union_4_state_1(x_union_4_state_1); if (x_union_4_state_1 !== i[0] ) $stop; x_union_4_state_32 = ~32'd0 << i; i_union_4_state_32(x_union_4_state_32); if (x_union_4_state_32 !== ~32'd0 >> i) $stop; x_union_4_state_33 = ~33'd0 << i; i_union_4_state_33(x_union_4_state_33); if (x_union_4_state_33 !== ~33'd0 >> i) $stop; x_union_4_state_64 = ~64'd0 << i; i_union_4_state_64(x_union_4_state_64); if (x_union_4_state_64 !== ~64'd0 >> i) $stop; x_union_4_state_65 = ~65'd0 << i; i_union_4_state_65(x_union_4_state_65); if (x_union_4_state_65 !== ~65'd0 >> i) $stop; x_union_4_state_128 = ~128'd0<< i; i_union_4_state_128(x_union_4_state_128); if (x_union_4_state_128 !== ~128'd0>> i) $stop; // Check the exports check_exports(); end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_func_bad.py0000755000542200017500000000076615101701376021540 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_pp_defparen_bad.out0000644000542200017500000000052415101701376023234 0ustar mahmoudyfreeshell%Error: t/t_pp_defparen_bad.v:10:2: Illegal text before '(' that starts define arguments 10 | ( 1,2) | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_pp_defparen_bad.v:10:1: syntax error, unexpected '(' 10 | ((val 1) + (2)) | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_preproc_strify_join.out0000644000542200017500000000004115101701376024226 0ustar mahmoudyfreeshell"foo-bar-qux" ""foo-bar-qux"" "" verilator-5.042/test_regress/t/t_package_dimport.py0000755000542200017500000000073415101701376023123 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() # Compile only test.passes() verilator-5.042/test_regress/t/t_dynarray_unpacked.py0000755000542200017500000000073415101701376023475 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_cast_class_incompat_bad.py0000755000542200017500000000076615101701376024616 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_delay_stmtdly_bad.py0000755000542200017500000000114315101701376023451 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_delay.v" test.lint(verilator_flags2=['--no-timing -Wall -Wno-DECLFILENAME'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_recursive_module_bug.v0000644000542200017500000000236415101701376024016 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2022 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // This hits a case where parameter specialization of recursive modules // used to yield a module list that was not topologically sorted, which // then caused V3Inline to blow up as it assumes that. module top #( parameter N=8 ) ( input wire [N-1:0] i, output wire [N-1:0] o, output wire [N-1:0] a ); sub #(.N(N)) inst(.i(i), .o(a)); generate if (N > 1) begin: recursive top #(.N(N/2)) hi(.i(i[N - 1:N/2]), .o(o[N - 1:N/2]), .a()); top #(.N(N/2)) lo(.i(i[N/2 - 1: 0]), .o(o[N/2 - 1: 0]), .a()); end else begin: base assign o = i; end endgenerate endmodule module sub #( parameter N = 8 ) ( input wire [N-1:0] i, output wire [N-1:0] o ); generate if (N > 1) begin: recursive sub #(.N(N/2)) hi(.i(i[N - 1:N/2]), .o(o[N - 1:N/2])); sub #(.N(N/2)) lo(.i(i[N/2 - 1: 0]), .o(o[N/2 - 1: 0])); end else begin: base assign o = i; end endgenerate endmodule verilator-5.042/test_regress/t/t_const_slicesel_bad.v0000644000542200017500000000056715101701376023427 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Michael Lefebvre. // SPDX-License-Identifier: CC0-1.0 module t; localparam int unsigned A3[2:0] = '{4, 5, 6}; // slicesel out of range should fail localparam int unsigned B32_T[1:0] = A3[3:1]; endmodule verilator-5.042/test_regress/t/t_strength_highz.out0000644000542200017500000000126715101701376023177 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_strength_highz.v:8:17: Unsupported: highz strength 8 | wire (weak0, highz1) a = 1; | ^~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_strength_highz.v:9:19: Unsupported: highz strength 9 | wire (strong1, highz0) b = 0; | ^~~~~~ %Error-UNSUPPORTED: t/t_strength_highz.v:10:10: Unsupported: highz strength 10 | wire (highz0, pull1) c = 0; | ^~~~~~ %Error-UNSUPPORTED: t/t_strength_highz.v:11:10: Unsupported: highz strength 11 | wire (highz1, supply0) d = 1; | ^~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_cover_unused_bad.out0000644000542200017500000000071115101701376023450 0ustar mahmoudyfreeshell%Warning-UNUSEDSIGNAL: t/t_cover_unused_bad.v:14:10: Signal is not used: 'unu3' : ... note: In instance 't' 14 | logic unu3 = 0; | ^~~~ ... For warning description see https://verilator.org/warn/UNUSEDSIGNAL?v=latest ... Use "/* verilator lint_off UNUSEDSIGNAL */" and lint_on around source to disable this message. %Error: Exiting due to verilator-5.042/test_regress/t/t_struct_cons_cast.py0000755000542200017500000000073415101701376023352 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_constraint_assoc_arr_basic.v0000644000542200017500000001777015101701376025175 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by PlanV GmbH. // SPDX-License-Identifier: CC0-1.0 class constrained_associative_array_basic; rand int int_index_arr [int]; rand int string_index_arr [string]; rand int string_index_arr_2 [string]; /* verilator lint_off SIDEEFFECT */ // Constraints for both arrays constraint int_index_constraints { foreach (int_index_arr[i]) int_index_arr[i] inside {10, 20, 30, 40, 50}; } constraint string_index_constraints { string_index_arr["Alice"] == 35; string_index_arr["Bob"] inside {50, 60}; string_index_arr["Charlie"] > 25; } constraint string_index_2_constraints { foreach (string_index_arr_2[i]) string_index_arr_2[i] > 10; // nodep->bitp() would be VARREF, instead of CVTPACKSTRING } // Constructor to initialize arrays function new(); int_index_arr = '{1: 0, 8: 0, 7: 0}; string_index_arr = '{"Alice": 25, "Bob": 50, "Charlie": 45}; string_index_arr_2 = '{"key1": 15, "key2": 20, "key3": 30}; endfunction // Function to check and display the arrays function void self_check(); foreach (int_index_arr[i]) begin if (!(int_index_arr[i] inside {10, 20, 30, 40, 50})) $stop; end foreach (string_index_arr[name]) begin if ((name == "Alice" && string_index_arr[name] != 35) || (name == "Bob" && !(string_index_arr[name] inside {50, 60})) || (name == "Charlie" && string_index_arr[name] <= 25)) $stop; end foreach (string_index_arr_2[i]) begin if (string_index_arr_2[i] <= 10) $stop; end endfunction endclass class constrained_1d_associative_array; rand int string_index_arr [string]; rand int int_index_arr [int]; rand int shortint_index_arr [shortint]; rand int longint_index_arr[longint]; rand int byte_index_arr [byte]; rand int bit_index_arr [bit[5:0]]; rand int logic_index_arr [logic[3:0]]; rand int bit_index_arr_1 [bit[55:0]]; // Constraints constraint associative_array_constraints { string_index_arr["key1"] == 100; string_index_arr["key2"] inside {200, 300, 400}; int_index_arr[40000] + int_index_arr[2000000000] == 2; shortint_index_arr[2000] == 200; longint_index_arr[64'd4000000000] == 300; byte_index_arr[8'd255] == 50; bit_index_arr[6'd30] - bit_index_arr_1[56'd66] == 3; logic_index_arr[4'b0011] == 70; } function new(); string_index_arr = '{"key1":0, "key2":0}; int_index_arr = '{40000:0, 2000000000:0}; shortint_index_arr = '{2000:0}; longint_index_arr = '{64'd4000000000:0}; byte_index_arr = '{8'd255:0}; bit_index_arr = '{6'd30:0}; bit_index_arr_1 = '{56'd66:0}; logic_index_arr = '{4'd3:0}; endfunction function void self_check(); if (string_index_arr["key1"] != 100) $stop; if (!(string_index_arr["key2"] inside {200, 300, 400})) $stop; if ((int_index_arr[40000] + int_index_arr[2000000000]) != 2) $stop; if (shortint_index_arr[2000] != 200) $stop; if (longint_index_arr[64'd4000000000] != 300) $stop; if (byte_index_arr[8'd255] != 50) $stop; if (bit_index_arr[6'd30] - bit_index_arr_1[56'd66] != 3) $stop; if (logic_index_arr[4'd3] != 70) $stop; endfunction function void debug_display(); $display("string_index_arr[\"key1\"] = %0d", string_index_arr["key1"]); $display("string_index_arr[\"key2\"] = %0d", string_index_arr["key2"]); $display("int_index_arr[40000] = %0d", int_index_arr[40000]); $display("int_index_arr[2000000000] = %0d", int_index_arr[2000000000]); $display("shortint_index_arr[2000] = %0d", shortint_index_arr[2000]); $display("longint_index_arr[4000000000] = %0d", longint_index_arr[64'd4000000000]); $display("byte_index_arr[255] = %0d", byte_index_arr[8'd255]); $display("bit_index_arr[30] = %0d", bit_index_arr[6'd30]); $display("bit_index_arr_1[66] = %0d", bit_index_arr_1[56'd66]); $display("logic_index_arr[3] = %0d", logic_index_arr[4'd3]); endfunction endclass class constrained_2d_associative_array; rand int string_int_index_arr [string][int]; rand int int_bit_index_arr [int][bit[5:0]]; rand int string_bit_index_arr [string][bit[7:0]]; rand int unpacked_assoc_array_2d [string][2]; // Constraints constraint associative_array_constraints { string_int_index_arr["key1"][2000] == 100; string_int_index_arr["key2"][3000] inside {200, 300, 400}; int_bit_index_arr[40000][6'd30] == 60; int_bit_index_arr[50000][6'd40] inside {100, 200}; string_bit_index_arr["key3"][8'd100] == 150; string_bit_index_arr["key4"][8'd200] inside {250, 350}; unpacked_assoc_array_2d["key5"][0] == 7; } function new(); string_int_index_arr = '{"key1":'{2000:0}, "key2":'{3000:0}}; int_bit_index_arr = '{40000:'{6'd30:0}, 50000:'{6'd40:0}}; string_bit_index_arr = '{"key3":'{8'd100:0}, "key4":'{8'd200:0}}; unpacked_assoc_array_2d["key5"][0] = 0; unpacked_assoc_array_2d["key5"][1] = 0; endfunction function void self_check(); if (string_int_index_arr["key1"][2000] != 100) $stop; if (!(string_int_index_arr["key2"][3000] inside {200, 300, 400})) $stop; if (int_bit_index_arr[40000][6'd30] != 60) $stop; if (!(int_bit_index_arr[50000][6'd40] inside {100, 200})) $stop; if (string_bit_index_arr["key3"][8'd100] != 150) $stop; if (!(string_bit_index_arr["key4"][8'd200] inside {250, 350})) $stop; if (unpacked_assoc_array_2d["key5"][0] != 7) $stop; endfunction function void debug_display(); $display("string_int_index_arr[\"key1\"][2000] = %0d", string_int_index_arr["key1"][2000]); $display("string_int_index_arr[\"key2\"][3000] = %0d", string_int_index_arr["key2"][3000]); $display("int_bit_index_arr[40000][30] = %0d", int_bit_index_arr[40000][6'd30]); $display("int_bit_index_arr[50000][40] = %0d", int_bit_index_arr[50000][6'd40]); $display("string_bit_index_arr[\"key3\"][100] = %0d", string_bit_index_arr["key3"][8'd100]); $display("string_bit_index_arr[\"key4\"][200] = %0d", string_bit_index_arr["key4"][8'd200]); $display("unpacked_assoc_array_2d[\"key5\"][0] = %0d", unpacked_assoc_array_2d["key5"][0]); endfunction /* verilator lint_off SIDEEFFECT */ endclass class AssocArray64bitMoreTest; rand int bit_index_arr [bit[78:0]]; rand int logic_index_arr [logic[64:0]]; constraint c { bit_index_arr[79'd66] == 65; logic_index_arr[65'd3] == 70; } function new(); bit_index_arr = '{79'd66:0}; logic_index_arr = '{65'd3:0}; endfunction function void self_check(); if (bit_index_arr[79'd66] != 65) $stop; if (logic_index_arr[65'd3] != 70) $stop; endfunction endclass module t_constraint_assoc_arr_basic; constrained_associative_array_basic my_array; constrained_1d_associative_array my_1d_array; constrained_2d_associative_array my_2d_array; AssocArray64bitMoreTest test_obj; int success; initial begin my_array = new(); success = my_array.randomize(); if (success == 0) $stop; my_array.self_check(); my_1d_array = new(); success = my_1d_array.randomize(); if (success == 0) $stop; my_1d_array.self_check(); my_2d_array = new(); success = my_2d_array.randomize(); if (success == 0) $stop; my_2d_array.self_check(); test_obj = new(); repeat(2) begin success = test_obj.randomize(); if (success != 1) $stop; end // my_1d_array.debug_display(); // my_2d_array.debug_display(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_inst_first_a.v0000644000542200017500000000157615101701376022275 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t_inst_first_a (/*AUTOARG*/ // Outputs o_w5, o_w5_d1r, o_w40, o_w104, // Inputs clk, i_w5, i_w40, i_w104 ); input clk; input [4:0] i_w5; output [4:0] o_w5; output [4:0] o_w5_d1r; input [39:0] i_w40; output [39:0] o_w40; input [104:0] i_w104; output [104:0] o_w104; wire [4:0] o_w5 = i_w5; wire [39:0] o_w40 = i_w40; wire [104:0] o_w104 = i_w104; /*AUTOREG*/ // Beginning of automatic regs (for this module's undeclared outputs) reg [4:0] o_w5_d1r; // End of automatics always @ (posedge clk) begin o_w5_d1r <= i_w5; end endmodule verilator-5.042/test_regress/t/t_split_var_1_bad.py0000755000542200017500000000106415101701376023020 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, verilator_flags2=['--stats', "-fno-dfg"], expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_param_while.v0000644000542200017500000000126215101701376022071 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 //bug505 module t; parameter WIDTH = 33; localparam MAX_WIDTH = 11; localparam NUM_OUT = num_out(WIDTH); wire [NUM_OUT-1:0] z; function integer num_out; input integer width; num_out = 1; while ((width + num_out - 1) / num_out > MAX_WIDTH) num_out = num_out * 2; endfunction initial begin if (NUM_OUT != 4) $stop; if ($bits(z) != 4) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_flag_fi.cpp0000644000542200017500000000153015101701376021503 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- // // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2017 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include #include VM_PREFIX_INCLUDE //====================================================================== unsigned int main_time = 0; double sc_time_stamp() { return main_time; } VM_PREFIX* topp = nullptr; bool gotit = false; void myfunction() { gotit = true; } int main(int argc, char* argv[]) { Verilated::debug(0); Verilated::commandArgs(argc, argv); topp = new VM_PREFIX; topp->eval(); if (!gotit) vl_fatal(__FILE__, __LINE__, "dut", "Never got call to myfunction"); topp->final(); VL_DO_DANGLING(delete topp, topp); return 0; } verilator-5.042/test_regress/t/t_randomize_method_constraints.v0000644000542200017500000000361715101701376025566 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 typedef enum bit[15:0] { ONE = 3, TWO = 5, THREE = 8, FOUR = 13 } Enum; class Cls; constraint A { v inside {ONE, THREE}; } constraint B { w == 5; x inside {1,2} || x inside {4,5}; } constraint C { z < 3 * 7; z > 5 + 8; u > 0; } rand logic[79:0] u; rand Enum v; rand logic[63:0] w; rand logic[47:0] x; rand logic[31:0] y; rand logic[22:0] z; function new; u = 0; v = ONE; w = 0; x = 0; y = 0; z = 0; endfunction endclass module t; Cls obj; initial begin int rand_result; longint prev_checksum; $display("===================\nSatisfiable constraints:"); for (int i = 0; i < 25; i++) begin obj = new; rand_result = obj.randomize(); $display("obj.u == %0d", obj.u); $display("obj.v == %0d", obj.v); $display("obj.w == %0d", obj.w); $display("obj.x == %0d", obj.x); $display("obj.y == %0d", obj.y); $display("obj.z == %0d", obj.z); $display("rand_result == %0d", rand_result); $display("-------------------"); if (!(obj.v inside {ONE, THREE})) $stop; if (obj.w != 5) $stop; if (!(obj.x inside {1,2,4,5})) $stop; if (obj.z <= 13 || obj.z >= 21) $stop; end //$display("===================\nUnsatisfiable constraints for obj.y:"); //rand_result = obj.randomize() with { 256 < y && y < 256; }; //$display("obj.y == %0d", obj.y); //$display("rand_result == %0d", rand_result); //if (rand_result != 0) $stop; //rand_result = obj.randomize() with { 16 <= z && z <= 32; }; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_interface.v0000644000542200017500000000624315101701376021545 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: SystemVerilog interface test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Iztok Jeras. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; logic rst = 1'b1; // reset integer rst_cnt = 0; // reset is removed after a delay always @ (posedge clk) begin rst_cnt <= rst_cnt + 1; rst <= rst_cnt <= 3; end // counters int cnt; int cnt_src; int cnt_drn; // add all counters assign cnt = cnt_src + cnt_drn + inf.cnt; // finish report always @ (posedge clk) if (cnt == 3*16) begin $write("*-* All Finished *-*\n"); $finish; end // interface instance handshake inf ( .clk (clk), .rst (rst) ); // source instance source #( .RW (8), .RP (8'b11100001) ) source ( .clk (clk), .rst (rst), .inf (inf), .cnt (cnt_src) ); // drain instance drain #( .RW (8), .RP (8'b11010100) ) drain ( .clk (clk), .rst (rst), .inf (inf), .cnt (cnt_drn) ); endmodule : t // interface definition interface handshake #( parameter int unsigned WC = 32 )( input logic clk, input logic rst ); // modport signals logic req; // request logic grt; // grant logic inc; // increment // local signals integer cnt; // counter // source modport src ( output req, input grt ); // drain modport drn ( input req, output grt ); // incremet condition assign inc = req & grt; // local logic (counter) always @ (posedge clk, posedge rst) if (rst) cnt <= '0; else cnt <= cnt + {31'h0, inc}; endinterface : handshake // source module module source #( // random generator parameters parameter int unsigned RW=1, // LFSR width parameter bit [RW-1:0] RP='0, // LFSR polinom parameter bit [RW-1:0] RR='1 // LFSR reset state )( input logic clk, input logic rst, handshake.src inf, output integer cnt ); // LFSR logic [RW-1:0] rnd; // LFSR in Galois form always @ (posedge clk, posedge rst) if (rst) rnd <= RR; else rnd <= {rnd[0], rnd[RW-1:1]} ^ ({RW{rnd[0]}} & RP); // counter always @ (posedge clk, posedge rst) if (rst) cnt <= 32'd0; else cnt <= cnt + {31'd0, (inf.req & inf.grt)}; // request signal assign inf.req = rnd[0]; endmodule : source // drain module module drain #( // random generator parameters parameter int unsigned RW=1, // LFSR width parameter bit [RW-1:0] RP='0, // LFSR polinom parameter bit [RW-1:0] RR='1 // LFSR reset state )( input logic clk, input logic rst, handshake.drn inf, output integer cnt ); // LFSR logic [RW-1:0] rnd; // LFSR in Galois form always @ (posedge clk, posedge rst) if (rst) rnd <= RR; else rnd <= {rnd[0], rnd[RW-1:1]} ^ ({RW{rnd[0]}} & RP); // counter always @ (posedge clk, posedge rst) if (rst) cnt <= 32'd0; else cnt <= cnt + {31'd0, (inf.req & inf.grt)}; // grant signal assign inf.grt = rnd[0]; endmodule : drain verilator-5.042/test_regress/t/t_hier_trace.v0000644000542200017500000000077615101701376021717 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t( input clk, input reset_l); sub_top u0_sub_top( .clk(clk), .reset_l(reset_l) ); sub_top u1_sub_top( .clk(clk), .reset_l(reset_l) ); initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_var_rsvd_bad.out0000644000542200017500000000114215101701376022574 0ustar mahmoudyfreeshell%Warning-SYMRSVDWORD: t/t_var_rsvd_port.v:12:10: Symbol matches C++ keyword: 'bool' 12 | input bool; | ^~~~ ... For warning description see https://verilator.org/warn/SYMRSVDWORD?v=latest ... Use "/* verilator lint_off SYMRSVDWORD */" and lint_on around source to disable this message. %Warning-SYMRSVDWORD: t/t_var_rsvd_port.v:15:9: Symbol matches C++ keyword: 'switch' : ... note: In instance 't' 15 | reg switch /*verilator public*/ ; | ^~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_mem_slice_conc_bad.v0000644000542200017500000000542115101701376023347 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // // bug354 typedef logic [5:0] data_t; module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire rst; data_t iii_in = crc[5:0]; data_t jjj_in = crc[11:6]; data_t iii_out; data_t jjj_out; logic [1:0] ctl0 = crc[63:62]; aaa aaa (.*); // Aggregate outputs into a single result vector wire [63:0] result = {64'h0}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= 64'h0; rst <= 1'b0; end else if (cyc<10) begin sum <= 64'h0; rst <= 1'b1; end else if (cyc<90) begin rst <= 1'b0; end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h4afe43fb79d7b71e if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module bbb ( output data_t ggg_out[1:0], input data_t ggg_in [1:0], input [1:0] [1:0] ctl, input logic clk, input logic rst ); genvar i; generate for (i=0; i<2; i++) begin: PPP always_ff @(posedge clk) begin if (rst) begin ggg_out[i] <= 6'b0; end else begin if (ctl[i][0]) begin if (ctl[i][1]) begin ggg_out[i] <= ~ggg_in[i]; end else begin ggg_out[i] <= ggg_in[i]; end end end end end endgenerate endmodule module aaa ( input data_t iii_in, input data_t jjj_in, input [1:0] ctl0, output data_t iii_out, output data_t jjj_out, input logic clk, input logic rst ); // Below is a bug; {} concat isn't used to make arrays bbb bbb ( .ggg_in ({jjj_in, iii_in}), .ggg_out ({jjj_out, iii_out}), .ctl ({{1'b1,ctl0[1]}, {1'b0,ctl0[0]}}), .*); endmodule verilator-5.042/test_regress/t/t_lint_realcvt_bad.v0000644000542200017500000000164315101701376023100 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `timescale 1ns / 1ps module sub; time t_ok1 = 9ns; // > 1ns units time t_bad1 = 9.001ns; // < 1ns units time t_bad2 = 9.999ns; // < 1ns units time t_ok2 = 9.001us; // > 1ns units time t_bad3 = 9ps; // < 1ns units realtime rt_ok10 = 9.001ns; // < 1ns units realtime rt_ok11 = 9ps; // < 1ns units integer i_ok20 = 23.0; // No warning integer i_bad21 = 23.1; initial begin int i; i = $signed(1.0); // Error, doesn't support real, not just warning i = $unsigned(1.0); // Error, doesn't support real, not just warning i = {1.2, 1.3}; // Error, doesn't support real, not just warning i = {6{1.2}}; // Error, doesn't support real, not just warning end endmodule verilator-5.042/test_regress/t/t_func_real_abs.v0000644000542200017500000000232515101701376022365 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2012 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 //bug591 module t; function real ABS (real num); ABS = (num < 0) ? -num : num; endfunction function logic range_chk; input real last; input real period; input real cmp; range_chk = 0; if ( last >= 0 ) begin if ( ABS(last - period) > cmp ) begin range_chk = 1; end end endfunction function integer ceil; input num; real num; if (num > $rtoi(num)) ceil = $rtoi(num) + 1; else // verilator lint_off REALCVT ceil = num; // verilator lint_on REALCVT endfunction initial begin if (range_chk(-1.1, 2.2, 3.3) != 1'b0) $stop; if (range_chk(1.1, 2.2, 0.3) != 1'b1) $stop; if (range_chk(1.1, 2.2, 2.3) != 1'b0) $stop; if (range_chk(2.2, 1.1, 0.3) != 1'b1) $stop; if (range_chk(2.2, 1.1, 2.3) != 1'b0) $stop; if (ceil(-2.1) != -2) $stop; if (ceil(2.1) != 3) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_param_mem_attr.v0000644000542200017500000000215615101701376022574 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // A test case for parameterized module. // // When a module is instantiatied with parameter, there will be two modules in // the tree and eventually one will be removed after param and deadifyModules. // // This test is to check that the removal of dead module will not cause // compilation error. Possible error was/is seen as: // // pure virtual method called // terminate called without an active exception // %Error: Verilator aborted. Consider trying --debug --gdbbt // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Jie Xu. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; wire [71:0] ctrl; wire [7:0] cl; // this line is added memory #(.WORDS(72)) i_memory (.clk (clk)); assign ctrl = i_memory.mem[0]; assign cl = i_memory.mem[0][7:0]; // and this line endmodule // memory module, which is used with parameter module memory (clk); input clk; parameter WORDS = 16384, BITS = 72; reg [BITS-1 :0] mem[WORDS-1 : 0]; endmodule verilator-5.042/test_regress/t/t_constraint_extern.py0000755000542200017500000000111515101701376023535 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile(verilator_flags2=['-Wno-CONSTRAINTIGN']) test.execute() test.passes() verilator-5.042/test_regress/t/t_array_packed_endian.v0000644000542200017500000000463615101701376023554 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) typedef struct packed { logic [7:0] a; } tb_t; typedef struct packed { // verilator lint_off ASCRANGE logic [0:7] a; // verilator lint_on ASCRANGE } tl_t; typedef struct packed { logic [7:0] bb; // verilator lint_off ASCRANGE tb_t [0:1] cbl; tb_t [1:0] cbb; tl_t [0:1] cll; tl_t [1:0] clb; logic [0:7] dl; // verilator lint_on ASCRANGE } t2; logic [2:0][31:0] test2l; // verilator lint_off ASCRANGE logic [0:2][31:0] test2b; logic [0:2][31:0] test1b; // verilator lint_on ASCRANGE logic [2:0][31:0] test1l; module t; t2 t; initial begin t = 80'hcd_1f2f3f4f_5f6f7f8f_c2; `checkh(t.bb, 8'hcd); `checkh(t.cbl[0].a, 8'h1f); `checkh(t.cbl[1].a, 8'h2f); `checkh(t.cbb[0].a, 8'h4f); `checkh(t.cbb[1].a, 8'h3f); `checkh(t.cll[0].a, 8'h5f); `checkh(t.cll[1].a, 8'h6f); `checkh(t.clb[0].a, 8'h8f); `checkh(t.clb[1].a, 8'h7f); `checkh(t.dl, 8'hc2); t = '0; t.bb = 8'h13; t.cbl[0].a = 8'hac; t.cbl[1].a = 8'had; t.cbb[0].a = 8'hae; t.cbb[1].a = 8'haf; t.cll[0].a = 8'hbc; t.cll[1].a = 8'hbd; t.clb[0].a = 8'hbe; t.clb[1].a = 8'hbf; t.dl = 8'h31; `checkh(t, 80'h13_acadafae_bcbdbfbe_31); t = '0; t.bb[7] = 1'b1; t.cbl[1].a[1] = 1'b1; t.cbb[1].a[2] = 1'b1; t.cll[1].a[3] = 1'b1; t.clb[1].a[4] = 1'b1; t.dl[7] = 1'b1; `checkh(t, 80'h80_0002040000100800_01); test1b = '{0, 1, 2}; test1l = test1b; test2l = '{2, 1, 0}; test2b = test2l; `checkh(test2l[0], 0); `checkh(test2l[2], 2); `checkh(test2l, {32'h2, 32'h1, 32'h0}); `checkh(test2b[0], 2); `checkh(test2b[2], 0); `checkh(test2b, {32'h2, 32'h1, 32'h0}); `checkh(test1b[0], 0); `checkh(test1b[2], 2); `checkh(test1b, {32'h0, 32'h1, 32'h2}); `checkh(test1l[0], 2); `checkh(test1l[2], 0); `checkh(test1l, {32'h0, 32'h1, 32'h2}); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_nba_commit_queue_suspenable.py0000755000542200017500000000130415101701376025521 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(verilator_flags2=["--binary", "-unroll-count 1", "--stats"]) test.execute() test.file_grep(test.stats, r'NBA, variables using ValueQueueWhole scheme\s+(\d+)', 2) test.file_grep(test.stats, r'NBA, variables using ValueQueuePartial scheme\s+(\d+)', 0) test.passes() verilator-5.042/test_regress/t/t_lint_nolatch_bad.v0000644000542200017500000000056215101701376023067 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module for issue #1609 // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by Julien Margetts. // SPDX-License-Identifier: Unlicense module t (/*AUTOARG*/ a, b, o); input a; input b; output reg o; always_latch if (a) o = b; else o = ~b; endmodule verilator-5.042/test_regress/t/t_constraint_inheritance_with.py0000755000542200017500000000104615101701376025557 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_solver: test.skip("No constraint solver installed") test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_var_suggest_bad.py0000755000542200017500000000077615101701376023137 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_compiler_include.cpp0000644000542200017500000000166515101701376023442 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // Copyright 2024 by Antmicro. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // t_compiler_include.h is implicitly included by `--compiler-include` #include #include VM_PREFIX_INCLUDE int main() { Verilated::debug(0); VM_PREFIX* topp = new VM_PREFIX; topp->in = 123; topp->eval(); if (ext_equal(topp->in, topp->out)) VL_PRINTF("*-* All Finished *-*\n"); else VL_PRINTF("in (%d) != out (%d)\n", topp->in, topp->out); topp->final(); VL_DO_DANGLING(delete topp, topp); } verilator-5.042/test_regress/t/t_func_virt_new_bad.py0000755000542200017500000000076315101701376023452 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_math_eq_bad.v0000644000542200017500000000051415101701376022024 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; logic [31:0] a; initial begin a = 1234; if (a ==? 1.0) $stop; // Bad end endmodule verilator-5.042/test_regress/t/t_timing_zerodly_unsup.out0000644000542200017500000000035315101701376024434 0ustar mahmoudyfreeshell%Warning: t/t_timing_zerodly_unsup.v:22: Encountered #0 delay. #0 scheduling support is incomplete and the process will be resumed before combinational logic evaluation. %Error: t/t_timing_zerodly_unsup.v:23: Verilog $stop Aborting... verilator-5.042/test_regress/t/t_event_control_expr_unsup.py0000755000542200017500000000105515101701376025140 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') # no vltmt, as AstMemberSel is unhandled in V3InstrCount test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_property_var_unsup.py0000755000542200017500000000107115101701376023753 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert --error-limit 1000'], fails=True) test.passes() verilator-5.042/test_regress/t/t_sys_sformat_noopt.py0000755000542200017500000000141515101701376023557 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_sys_sformat.v" test.compile( # Avoid inlining our simple example, to make sure verilated.h works right verilator_flags2=["-O0"]) if re.search(r'clang', test.cxx_version): test.skip("Known clang bug") #Here: if (VL_UNLIKELY(VL_NEQ_W(12, __Vtemp1, vlSymsp->TOP__t.__PVT__str))) test.execute() test.passes() verilator-5.042/test_regress/t/t_interface_gen4.py0000755000542200017500000000073415101701376022647 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_const_bitoptree_bug3096.v0000644000542200017500000000164015101701376024163 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // Copyright 2021 by Geza Lore. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // From issue #3096 module decoder( input wire [31:0] instr_i, // Making 'a' an output preserves it as a sub-expression and causes a missing clean output wire a, output wire illegal_instr_o ); /* verilator lint_off WIDTH */ wire b = ! instr_i[12:5]; wire c = ! instr_i[1:0]; wire d = ! instr_i[15:13]; /* verilator lint_on WIDTH */ assign a = d ? b : 1'h1; assign illegal_instr_o = c ? a : 1'h0; endmodule verilator-5.042/test_regress/t/t_queue_method_bad.v0000644000542200017500000000155215101701376023075 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; initial begin int q[$]; int qe[$]; // Empty int qv[$]; // Value returns int qi[$]; // Index returns q = '{2, 2, 4, 1, 3}; q.reverse(1); // Bad no args allowed q.shuffle(1); // Bad no args allowed qv = q.find; // Bad missing with qv = q.find_first; // Bad missing with qv = q.find_last; // Bad missing with qi = q.find_index; // Bad missing with qi = q.find_first_index; // Bad missing with qi = q.find_last_index; // Bad missing with qi = q.size with (1); // with not allowed $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_constraint.v0000644000542200017500000000103615101701376021764 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Packet; rand int one; constraint a { one > 0 && one < 2; } constraint empty { } endclass module t; Packet p; int v; initial begin p = new; v = p.randomize(); if (v != 1) $stop; if (p.one != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_interface_generic_bad3.py0000755000542200017500000000102515101701376024311 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(verilator_flags2=['--timing'], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_assert_on.v0000644000542200017500000000062115101701376021574 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2007 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; always @ (posedge clk) begin assert (0); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_gate_unsup.py0000755000542200017500000000102615101701376022137 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint( # Unsupported: UDP Tables verilator_flags2=["--lint-only --bbox-unsup"]) test.passes() verilator-5.042/test_regress/t/t_inside_tolerance_unsup.v0000644000542200017500000000133315101701376024341 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); // verilog_format: on module t; real r; bit b; initial begin r = 1492.4; `checkh(r inside {[1492 +/- 2]}, 1'b1); `checkh(r inside {[1482 +/- 2]}, 1'b0); `checkh(r inside {[1490 +%- 10]}, 1'b1); `checkh(r inside {[1090 +%- 10]}, 1'b0); end endmodule verilator-5.042/test_regress/t/t_tri_gate_notif1.py0000755000542200017500000000136515101701376023051 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_tri_gate.cpp" test.top_filename = "t/t_tri_gate.v" test.compile(make_top_shell=False, make_main=False, v_flags2=['+define+T_NOTIF1'], make_flags=['CPPFLAGS_ADD=-DT_NOTIF1'], verilator_flags2=["--exe", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_class_super_new_bad_nfirst.v0000644000542200017500000000124215101701376025166 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Base; int imemberb; function new(int adder); imemberb = 5 + adder; endfunction endclass class Cls extends Base; int imemberc; function new(); imemberc = 10; super.new(imemberc); // BAD not first endfunction endclass module t; initial begin Cls c; c = new; if (c.imemberc != 10) $stop; if (c.imemberb != 5) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_package_import_bad2.py0000755000542200017500000000076615101701376023654 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_stream_string_array.py0000755000542200017500000000073415101701376024051 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_slice_cond_side_effect.py0000755000542200017500000000073415101701376024414 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_math_shift_rep.py0000755000542200017500000000073415101701376022766 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_altera_lpm_mult_noinl.py0000755000542200017500000000117715101701376024354 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_altera_lpm.v" module = re.sub(r'.*t_altera_', '', test.name) module = re.sub(r'_noinl', '', module) test.compile(verilator_flags2=["--top-module", module, "-fno-inline"]) test.passes() verilator-5.042/test_regress/t/t_array_method_bad.py0000755000542200017500000000076615101701376023263 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_runflag_bad__b.out0000644000542200017500000000015715101701376023051 0ustar mahmoudyfreeshell%Error: COMMAND_LINE:0: Argument '+verilator+rand+reset+' must be an unsigned integer, less than 3 Aborting... verilator-5.042/test_regress/t/t_stream_unpack_lhs.py0000755000542200017500000000104715101701376023472 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) if not test.vlt_all: test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_iface_topmodule1.v0000644000542200017500000000146715101701376024056 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Josh Redford. // SPDX-License-Identifier: CC0-1.0 interface my_if; logic valid; logic [7:0] data ; modport slave_mp ( input valid, input data ); modport master_mp ( output valid, output data ); endinterface module t ( input wire clk, my_if.slave_mp in_if, my_if.master_mp out_if ); my_if my_i (); always @(posedge clk) begin my_i.valid <= in_if.valid; my_i.data <= in_if.data; end assign out_if.valid = my_i.valid; assign out_if.data = my_i.data; endmodule verilator-5.042/test_regress/t/t_interface_generic_modport_task2.v0000644000542200017500000000112315101701376026101 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 interface inf; int v; task setup(); v = 3; endtask modport mp( input v ); endinterface module GenericModule (interface.mp a); initial begin #1; if (a.v != 3) $stop; end endmodule module t; inf inf_inst(); GenericModule genericModule (inf_inst); initial begin inf_inst.setup(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_time_vpi_100s10ms.py0000755000542200017500000000137215101701376023051 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator_st') test.pli_filename = "t/t_time_vpi_c.cpp" test.top_filename = "t/t_time_vpi.v" test.main_time_multiplier = 100e0 / 10e-6 test.compile( v_flags2=['+define+time_scale_units=100s +define+time_scale_prec=10ms', test.pli_filename], verilator_flags2=['--vpi']) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_select_bad_range5.v0000644000542200017500000000053615101701376023132 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk, unk, mi ); input clk; input unk; output mi; assign mi = unk[3:2]; endmodule verilator-5.042/test_regress/t/t_stream_trace.out0000644000542200017500000000210215101701376022606 0ustar mahmoudyfreeshell$version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end $var wire 1 * clk $end $scope module t $end $var wire 1 * clk $end $var wire 32 + cyc [31:0] $end $var wire 3 # cmd_ready [2:0] $end $var wire 1 $ cmd_ready_unpack[0] $end $var wire 1 % cmd_ready_unpack[1] $end $var wire 1 & cmd_ready_unpack[2] $end $var wire 1 ' cmd_ready_o[0] $end $var wire 1 ( cmd_ready_o[1] $end $var wire 1 ) cmd_ready_o[2] $end $upscope $end $upscope $end $enddefinitions $end #0 b101 # 1$ 0% 1& 1' 0( 1) 0* b00000000000000000000000000000000 + #10 b110 # 0$ 1% 0' 1( 1* b00000000000000000000000000000001 + #15 b101 # 1$ 0% 1' 0( 0* #20 b110 # 0$ 1% 0' 1( 1* b00000000000000000000000000000010 + #25 b101 # 1$ 0% 1' 0( 0* #30 b110 # 0$ 1% 0' 1( 1* b00000000000000000000000000000011 + #35 b101 # 1$ 0% 1' 0( 0* #40 b110 # 0$ 1% 0' 1( 1* b00000000000000000000000000000100 + #45 b101 # 1$ 0% 1' 0( 0* #50 b110 # 0$ 1% 0' 1( 1* b00000000000000000000000000000101 + #55 b101 # 1$ 0% 1' 0( 0* #60 b110 # 0$ 1% 0' 1( 1* b00000000000000000000000000000110 + verilator-5.042/test_regress/t/t_cover_sva_trace.py0000755000542200017500000000123015101701376023127 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_cover_sva_notflat.v" test.compile(verilator_flags2=['--assert --cc --coverage-user --trace-vcd --trace-coverage']) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_unopt_converge_initial_run_bad.out0000644000542200017500000000025215101701376026401 0ustar mahmoudyfreeshell-V{t#,#} 'stl' region trigger index 0 is active: @([hybrid] x) %Error: t/t_unopt_converge_initial.v:7: Settle region did not converge after 100 tries Aborting... verilator-5.042/test_regress/t/t_cover_trace_always.py0000755000542200017500000000126415101701376023645 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--binary --coverage --trace-coverage --trace-vcd']) test.execute(all_run_flags=["+verilator+coverage+file+" + test.obj_dir + "/coverage_renamed.dat"]) test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_struct_genfor.v0000644000542200017500000000120115101701376022456 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (); for (genvar g = 0; g < 2; ++g) begin : genfor typedef struct packed { logic [31:0] val1; logic [31:0] val2; } struct_t; struct_t forvar; initial begin forvar.val1 = 1; forvar.val2 = 2; if (forvar.val1 != 1) $stop; if (forvar.val2 != 2) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_func_first.py0000755000542200017500000000073415101701376022134 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_enum_value_assign.v0000644000542200017500000000200715101701376023303 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; localparam logic [9:0] V2 = (1 << 2); localparam logic [9:0] V1 = (1 << 1); localparam logic [9:0] V0 = (1 << 0); typedef enum logic [9:0] { ZERO = '0, VAL0 = V0, VAL1 = V1, VAL01 = V0 | V1 } enum_t; localparam enum_t PARAMVAL1 = VAL1; localparam enum_t PARAMVAL1CONST = enum_t'(2); typedef enum {I_ZERO, I_ONE, I_TWO} inte_t; localparam inte_t I_PARAM = inte_t'(1); initial begin enum_t e; e = VAL01; if (e != VAL01) $stop; if (PARAMVAL1 != VAL1) $stop; if (PARAMVAL1CONST != VAL1) $stop; if (I_PARAM != I_ONE) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_vlcov_opt_wild.py0000755000542200017500000000133515101701376023022 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('dist') test.run(cmd=[ os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage", "--write-info", test.obj_dir + "/coverage.info", "--filter-type '*'", "t/t_vlcov_data_e.dat" ], verilator_run=True) test.files_identical(test.obj_dir + "/coverage.info", "t/" + test.name + ".info.out") test.passes() verilator-5.042/test_regress/t/t_virtual_interface_method.py0000755000542200017500000000101515101701376025031 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(v_flags2=["--binary"], verilator_make_gmake=False) test.execute() test.passes() verilator-5.042/test_regress/t/t_stream_integer_type.v0000644000542200017500000003706015101701376023657 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // Ref. to IEEE 1800-2023 11.4.14 & A.8.1 // // stream pack/unpack for integer_type only // slice_size ::= simple_type | constant_expression // simple_type ::= // integer_type | non_integer_type | ps_type_identifier | ps_parameter_identifier // non_integer_type ::= shortreal | real | realtime // integer_type ::= // integer_vector_type | integer_atom_type // integer_atom_type ::= byte | shortint | int | longint | integer | time // integer_vector_type ::= bit | logic | reg // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Victor Besyakov. // SPDX-License-Identifier: CC0-1.0 module t; logic [31:0] packed_data_32; logic [31:0] packed_data_32_ref; logic [31:0] v_packed_data_32; logic [31:0] v_packed_data_32_ref; logic [63:0] packed_data_64; logic [63:0] packed_data_64_ref; logic [63:0] v_packed_data_64; logic [63:0] v_packed_data_64_ref; logic [127:0] packed_data_128; logic [127:0] packed_data_128_ref; logic [127:0] v_packed_data_128; logic [127:0] v_packed_data_128_ref; logic [127:0] packed_data_128_i; logic [127:0] packed_data_128_i_ref; logic [255:0] packed_data_256; logic [255:0] packed_data_256_ref; logic [255:0] packed_time_256; logic [255:0] packed_time_256_ref; logic [511:0] v_packed_data_512; logic [511:0] v_packed_data_512_ref; // //integer_atom_type // byte byte_in[4]; byte byte_out[4]; // int int_in[4]; int int_out[4]; // // shortint shortint_in[4]; shortint shortint_out[4]; // longint longint_in[4]; longint longint_out[4]; // integer integer_in[4]; integer integer_out[4]; // time time_in[4]; time time_out[4]; //integer_vector_type typedef bit [7:0] test_byte; typedef bit [15:0] test_short; typedef bit [31:0] test_word; typedef bit [63:0] test_long; typedef bit [127:0] test_wide; // test_byte bit_in[4]; test_byte bit_out[4]; // test_short logic_in[4]; test_short logic_out[4]; // test_word reg_in[4]; test_word reg_out[4]; // test_wide wide_in[4]; test_wide wide_out[4]; // string error = ""; initial begin //init $write("*-* START t_stream_pack_unpack *-*\n"); error = test_integer_type_1(error); `ifdef TEST_VERBOSE print_all_data("test_integer_type_1"); `endif error = test_integer_type_2(error); `ifdef TEST_VERBOSE print_all_data("test_integer_type_2"); `endif // if (error == "") $write("*-* All Finished *-*\n"); else begin $write("*-* TEST failed error %s *-*:\n", error); print_data_error(error); end $finish; end // initial begin function string test_integer_type_1(string error); automatic string error_; automatic string function_name_ = "test_integer_type_1"; error_ = error; if (error_ == "") begin clean_packed_data (); init_data(); //pack packed_data_32 = {<<8{byte_in}}; packed_data_64 = {<<16{shortint_in}}; packed_data_128 = {<<32{int_in}}; packed_data_128_i = {<<32{integer_in}}; packed_data_256 = {<<64{longint_in}}; packed_time_256 = {<<64{time_in}}; v_packed_data_32 = {<<8{bit_in}}; v_packed_data_64 = {<<16{logic_in}}; v_packed_data_128 = {<<32{reg_in}}; v_packed_data_512 = {<<32{wide_in}}; //unpack {<<8{byte_out}} = packed_data_32; {<<16{shortint_out}} = packed_data_64; {<<32{int_out}} = packed_data_128; {<<32{integer_out}} = packed_data_128_i; {<<64{longint_out}} = packed_data_256; {<<64{time_out}} = packed_time_256; {<<8{bit_out}} = v_packed_data_32; {<<16{logic_out}} = v_packed_data_64; {<<32{reg_out}} = v_packed_data_128; {<<32{wide_out}} = v_packed_data_512; error_ = comp_in_out(); end // if (error == "") return error_; endfunction : test_integer_type_1 function string test_integer_type_2(string error); automatic string error_; automatic string function_name_ = "test_integer_type_2"; error_ = error; if (error_ == "") begin clean_packed_data (); init_data(); //pack packed_data_32 = {< 40) begin // $past(expression, ticks, expression, clocking) // In clock expression if (dly0 != $past(in)) $stop; if (dly0 != $past(in,)) $stop; if (dly1 != $past(in, 2)) $stop; if (dly1 != $past(in, 2, )) $stop; if (dly1 != $past(in, 2, , )) $stop; // $sampled(expression) -> expression if (in != $sampled(in)) $stop; end end assert property (@(posedge clk) $time < 40 || dly0 == $past(in)); endmodule module Test2 (/*AUTOARG*/ // Inputs clk, in ); input clk; input [31:0] in; reg [31:0] dly0; reg [31:0] dly1; always @(posedge clk) begin dly0 <= in; dly1 <= dly0; end default clocking @(posedge clk); endclocking assert property (@(posedge clk) $time < 40 || dly1 == $past(in, 2)); endmodule verilator-5.042/test_regress/t/t_stream_unpack_narrower.py0000755000542200017500000000077115101701376024546 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_array_pattern_bad.py0000755000542200017500000000076615101701376023460 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_package_using_dollar_unit.v0000644000542200017500000000267515101701376025006 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); typedef int my_type; class my_class; static int a = 1; endclass function int get_val; return 2; endfunction package my_pkg; int my_type_size = $bits(my_type); int my_class_a = my_class::a; int get_val_result = get_val(); endpackage package overwriting_pkg; typedef logic [9:0] my_type; class my_class; static int a = 2; endclass function int get_val; return 3; endfunction int my_type_size = $bits(my_type); int my_class_a = my_class::a; int get_val_result = get_val(); endpackage module t (/*AUTOARG*/ // Inputs clk ); input clk; int cyc; always @(posedge clk) begin cyc <= cyc + 1; if (cyc == 2) begin `checkh(my_pkg::my_type_size, 32); `checkh(my_pkg::my_class_a, 1); `checkh(my_pkg::get_val_result, 2); `checkh(overwriting_pkg::my_type_size, 10); `checkh(overwriting_pkg::my_class_a, 2); `checkh(overwriting_pkg::get_val_result, 3); $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_mem_slice_conc_bad.py0000755000542200017500000000076615101701376023544 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_vlt_match_error_2.out0000644000542200017500000000044715101701376023562 0ustar mahmoudyfreeshell%Error: t/t_vlt_match_error.v:19:27: Can't find definition of variable: 'EC_ERROR' 19 | initial $readmemh("", EC_ERROR); | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_unpacked_to_queue.v0000644000542200017500000000631215101701376023302 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Casting queues and dynamic arrays // into queues as function arguments // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop() `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin \ $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", \ `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); \ `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin \ $write("%%Error: %s:%0d: got='%s' exp='%s'\n", \ `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); class check #(parameter WIDTH=8); static function automatic void check_array (int n, logic [WIDTH-1:0] array []); for (int r=0; r1 array size to trigger dearrayAll segfault Crossbar #( .NUM_MASTER(2), .NUM_SLAVE(1) ) xbar_inst ( .Masters(MST) ); endmodule verilator-5.042/test_regress/t/t_gen_var_bad.out0000644000542200017500000000047215101701376022374 0ustar mahmoudyfreeshell%Error: t/t_gen_var_bad.v:10:7: Non-genvar used in generate for: 'i' : ... note: In instance 't' 10 | for (i=0; i<3; i=i+1) begin | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_inst_comma_inl0.py0000755000542200017500000000104415101701376023040 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_inst_comma.v" test.compile(v_flags2=['+define+NOUSE_INLINE']) test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_abort_fst_sc.out0000644000542200017500000000063115101701376023770 0ustar mahmoudyfreeshell$date Sat Apr 5 13:56:20 2025 $end $version fstWriter $end $timescale 1ps $end $scope module top $end $scope module t $end $var wire 1 ! clk $end $var logic 3 " cyc [2:0] $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b000 " 0! $end #10 1! b001 " #15 0! #20 1! b010 " #25 0! #30 1! b011 " #35 0! #40 1! b100 " #45 0! #50 1! b101 " #55 0! #60 1! b110 " #65 0! #70 1! b111 " #75 0! #79 verilator-5.042/test_regress/t/t_queue_method2_bad.out0000644000542200017500000000066715101701376023527 0ustar mahmoudyfreeshell%Error: t/t_queue_method2_bad.v:16:21: 'with' function expects only up to one argument 16 | qi = q.find(a,b) with (0); | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_queue_method2_bad.v:17:19: 'with' function expects simple variable name 17 | qi = q.find(1) with (0); | ^ %Error: Exiting due to verilator-5.042/test_regress/t/t_queue_pushpop.v0000644000542200017500000000216515101701376022506 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t (/*AUTOARG*/ // Inputs clk ); input clk; logic q [$]; int cycle = 0; always @(posedge clk) begin cycle <= cycle + 1'b1; end always @(posedge clk) begin q.push_front(1'b1); end // Important this is a separate always to expose bug where "q" thought unused always @(posedge clk) begin if (cycle == 1) begin if (q.pop_back() != 1) $stop; end end always @(posedge clk) begin if (cycle == 2) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_sys_writemem_b.gold1.mem0000644000542200017500000000014215101701376024143 0ustar mahmoudyfreeshell000010 000011 000100 000101 000110 000111 010000 000000 000000 000000 010100 010101 000000 000000 verilator-5.042/test_regress/t/t_flag_decoration.py0000755000542200017500000000141415101701376023106 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_flag_decoration.v" test.compile(verilator_flags2=["--decoration"]) test.file_grep_not(test.obj_dir + "/V" + test.name + ".h", r'\n// CONSTRUCTORS') test.file_grep(test.obj_dir + "/V" + test.name + ".h", r'\n // CONSTRUCTORS') test.file_grep_not(test.obj_dir + "/V" + test.name + ".h", r'/\*t/t_flag_decoration') test.passes() verilator-5.042/test_regress/t/t_assert_dup_bad.out0000644000542200017500000000054715101701376023127 0ustar mahmoudyfreeshell%Error: t/t_assert_dup_bad.v:17:4: Duplicate declaration of block: 'covlabel' 17 | covlabel: | ^~~~~~~~ t/t_assert_dup_bad.v:15:4: ... Location of original declaration 15 | covlabel: | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_select_lhs_oob.v0000644000542200017500000000452415101701376022571 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc = 0; reg [6:0] mem1d; reg [6:0] mem2d [5:0]; reg [6:0] mem3d [4:0][5:0]; integer i,j,k; // Four different test cases for out of bounds // = // <= // Continuous assigns // Output pin interconnect (also covers cont assigns) // Each with both bit selects and array selects initial begin mem1d[0] = 1'b0; i=7; mem1d[i] = 1'b1; if (mem1d[0] !== 1'b0) $stop; // for (i=0; i<8; i=i+1) begin for (j=0; j<8; j=j+1) begin for (k=0; k<8; k=k+1) begin mem1d[k] = k[0]; mem2d[j][k] = j[0]+k[0]; mem3d[i][j][k] = i[0]+j[0]+k[0]; end end end for (i=0; i<5; i=i+1) begin for (j=0; j<6; j=j+1) begin for (k=0; k<7; k=k+1) begin if (mem1d[k] !== k[0]) $stop; if (mem2d[j][k] !== j[0]+k[0]) $stop; if (mem3d[i][j][k] !== i[0]+j[0]+k[0]) $stop; end end end end integer wi; wire [31:0] wd = cyc; reg [31:0] reg2d[6:0]; always @ (posedge clk) reg2d[wi[2:0]] <= wd; always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d reg2d[%0d]=%0x wd=%0x\n", $time, cyc, wi[2:0], reg2d[wi[2:0]], wd); `endif cyc <= cyc + 1; if (cyc<10) begin wi <= 0; end else if (cyc==10) begin wi <= 1; end else if (cyc==11) begin if (reg2d[0] !== 10) $stop; wi <= 6; end else if (cyc==12) begin if (reg2d[0] !== 10) $stop; if (reg2d[1] !== 11) $stop; wi <= 7; // Will be ignored end else if (cyc==13) begin if (reg2d[0] !== 10) $stop; if (reg2d[1] !== 11) $stop; if (reg2d[6] !== 12) $stop; end else if (cyc==14) begin if (reg2d[0] !== 10) $stop; if (reg2d[1] !== 11) $stop; if (reg2d[6] !== 12) $stop; end else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_randomize_inline_funclocal.v0000644000542200017500000000127115101701376025155 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls; function int do_randomize(); int flocal, success; success = std::randomize(flocal); if (success !== 1) $stop; do_randomize = flocal; endfunction endclass module t; int r1, r2, r3; initial begin Cls c; c = new; r1 = c.do_randomize(); r2 = c.do_randomize(); r3 = c.do_randomize(); $display("%x %x %x", r1, r2, r3); if (r1 == r2 && r2 == r3) $stop; // Not impossible but 2^63 odds of failure $finish; end endmodule verilator-5.042/test_regress/t/t_package_abs.py0000755000542200017500000000073415101701376022212 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_class_func_dot.v0000644000542200017500000000122415101701376022565 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 class Cls_report_object; string m_msg; function string get_msg; return m_msg; endfunction endclass function Cls_report_object get_report_object; Cls_report_object c; c = new; c.m_msg = "hello"; return c; endfunction module t; string s; initial begin Cls_report_object _local_report_object; s = get_report_object().get_msg(); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_trace_dumpvars_dyn_saif_1.out0000644000542200017500000007563715101701376025277 0ustar mahmoudyfreeshell// Generated by verilated_saif (SAIFILE (SAIFVERSION "2.0") (DIRECTION "backward") (PROGRAM_NAME "Verilator") (DIVIDER / ) (TIMESCALE 1ps) (DURATION 20) (INSTANCE top (INSTANCE t (NET (cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE sub1a (NET (ADD\[0\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[1\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (ADD\[2\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[3\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (ADD\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10)) (value\[1\] (T0 9) (T1 11) (TZ 0) (TX 0) (TB 0) (TC 6)) (value\[2\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 3)) (value\[3\] (T0 9) (T1 11) (TZ 0) (TX 0) (TB 0) (TC 2)) (value\[4\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE sub2a ) (INSTANCE sub2b ) (INSTANCE sub2c ) ) (INSTANCE sub1b (NET (ADD\[0\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[1\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[2\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (ADD\[3\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[4\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (ADD\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10)) (value\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5)) (value\[2\] (T0 8) (T1 12) (TZ 0) (TX 0) (TB 0) (TC 3)) (value\[3\] (T0 7) (T1 13) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[4\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) (INSTANCE sub2a (NET (ADD\[0\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (ADD\[1\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[2\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (ADD\[3\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[4\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (ADD\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 11)) (value\[1\] (T0 9) (T1 11) (TZ 0) (TX 0) (TB 0) (TC 5)) (value\[2\] (T0 8) (T1 12) (TZ 0) (TX 0) (TB 0) (TC 3)) (value\[3\] (T0 5) (T1 15) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[4\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE sub2b (NET (ADD\[0\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[1\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (ADD\[2\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (ADD\[3\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[4\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (ADD\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10)) (value\[1\] (T0 9) (T1 11) (TZ 0) (TX 0) (TB 0) (TC 6)) (value\[2\] (T0 9) (T1 11) (TZ 0) (TX 0) (TB 0) (TC 4)) (value\[3\] (T0 4) (T1 16) (TZ 0) (TX 0) (TB 0) (TC 2)) (value\[4\] (T0 1) (T1 19) (TZ 0) (TX 0) (TB 0) (TC 2)) (value\[5\] (T0 19) (T1 1) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) (INSTANCE sub2c (NET (ADD\[0\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (ADD\[1\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (ADD\[2\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (ADD\[3\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[4\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1)) (ADD\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (ADD\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10)) (cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5)) (cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2)) (cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1)) (cyc\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (cyc\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 11)) (value\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 6)) (value\[2\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 4)) (value\[3\] (T0 4) (T1 16) (TZ 0) (TX 0) (TB 0) (TC 2)) (value\[4\] (T0 3) (T1 17) (TZ 0) (TX 0) (TB 0) (TC 2)) (value\[5\] (T0 17) (T1 3) (TZ 0) (TX 0) (TB 0) (TC 1)) (value\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) (value\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) ) ) ) ) verilator-5.042/test_regress/t/t_cover_toggle__points.out0000644000542200017500000005260315101701376024362 0ustar mahmoudyfreeshell// // verilator_coverage annotation // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef struct packed {logic a;} str_logic; module t (/*AUTOARG*/ // Inputs clk, check_real, check_array_real, check_string ); ~000010 input clk; +000010 point: comment=clk:0->1 hier=top.t -000009 point: comment=clk:1->0 hier=top.t input real check_real; // Check issue #2741 input real check_array_real [1:0]; input string check_string; // Check issue #2766 typedef struct packed { union packed { logic ua; logic ub; } u; logic b; } str_t; %000001 reg toggle; initial toggle='0; -000001 point: comment=toggle:0->1 hier=top.t -000001 point: comment=toggle:1->0 hier=top.t logic _under_toggle = toggle; // For --coverage-underscore %000001 str_t stoggle; initial stoggle='0; -000001 point: comment=stoggle.b:0->1 hier=top.t -000001 point: comment=stoggle.b:1->0 hier=top.t -000001 point: comment=stoggle.u.ua:0->1 hier=top.t -000001 point: comment=stoggle.u.ua:1->0 hier=top.t ~000010 str_logic strl; initial strl='0; +000010 point: comment=strl.a:0->1 hier=top.t -000009 point: comment=strl.a:1->0 hier=top.t union { real val1; // TODO use bit [7:0] here real val2; // TODO use bit [3:0] here } utoggle; const reg aconst = '0; %000001 reg [1:0][1:0] ptoggle; initial ptoggle=0; -000001 point: comment=ptoggle[0][0]:0->1 hier=top.t -000001 point: comment=ptoggle[0][0]:1->0 hier=top.t -000000 point: comment=ptoggle[0][1]:0->1 hier=top.t -000000 point: comment=ptoggle[0][1]:1->0 hier=top.t -000000 point: comment=ptoggle[1][0]:0->1 hier=top.t -000000 point: comment=ptoggle[1][0]:1->0 hier=top.t -000000 point: comment=ptoggle[1][1]:0->1 hier=top.t -000000 point: comment=ptoggle[1][1]:1->0 hier=top.t integer cyc; initial cyc=1; %000006 wire [7:0] cyc_copy = cyc[7:0]; -000006 point: comment=cyc_copy[0]:0->1 hier=top.t -000005 point: comment=cyc_copy[0]:1->0 hier=top.t -000003 point: comment=cyc_copy[1]:0->1 hier=top.t -000002 point: comment=cyc_copy[1]:1->0 hier=top.t -000001 point: comment=cyc_copy[2]:0->1 hier=top.t -000001 point: comment=cyc_copy[2]:1->0 hier=top.t -000001 point: comment=cyc_copy[3]:0->1 hier=top.t -000000 point: comment=cyc_copy[3]:1->0 hier=top.t -000000 point: comment=cyc_copy[4]:0->1 hier=top.t -000000 point: comment=cyc_copy[4]:1->0 hier=top.t -000000 point: comment=cyc_copy[5]:0->1 hier=top.t -000000 point: comment=cyc_copy[5]:1->0 hier=top.t -000000 point: comment=cyc_copy[6]:0->1 hier=top.t -000000 point: comment=cyc_copy[6]:1->0 hier=top.t -000000 point: comment=cyc_copy[7]:0->1 hier=top.t -000000 point: comment=cyc_copy[7]:1->0 hier=top.t %000001 wire toggle_up; -000001 point: comment=toggle_up:0->1 hier=top.t -000001 point: comment=toggle_up:1->0 hier=top.t typedef struct { int q[$]; } str_queue_t; str_queue_t str_queue; typedef struct packed { // verilator lint_off ASCRANGE bit [3:5] x; // verilator lint_on ASCRANGE bit [0:0] y; } str_bit_t; %000001 str_bit_t str_bit; -000001 point: comment=str_bit.x[3]:0->1 hier=top.t -000001 point: comment=str_bit.x[3]:1->0 hier=top.t -000001 point: comment=str_bit.x[4]:0->1 hier=top.t -000000 point: comment=str_bit.x[4]:1->0 hier=top.t -000001 point: comment=str_bit.x[5]:0->1 hier=top.t -000000 point: comment=str_bit.x[5]:1->0 hier=top.t -000001 point: comment=str_bit.y[0]:0->1 hier=top.t -000001 point: comment=str_bit.y[0]:1->0 hier=top.t %000001 str_bit_t [5:2] str_bit_arr; -000000 point: comment=str_bit_arr[2].x[3]:0->1 hier=top.t -000000 point: comment=str_bit_arr[2].x[3]:1->0 hier=top.t -000000 point: comment=str_bit_arr[2].x[4]:0->1 hier=top.t -000000 point: comment=str_bit_arr[2].x[4]:1->0 hier=top.t -000000 point: comment=str_bit_arr[2].x[5]:0->1 hier=top.t -000000 point: comment=str_bit_arr[2].x[5]:1->0 hier=top.t -000000 point: comment=str_bit_arr[2].y[0]:0->1 hier=top.t -000000 point: comment=str_bit_arr[2].y[0]:1->0 hier=top.t -000000 point: comment=str_bit_arr[3].x[3]:0->1 hier=top.t -000000 point: comment=str_bit_arr[3].x[3]:1->0 hier=top.t -000000 point: comment=str_bit_arr[3].x[4]:0->1 hier=top.t -000000 point: comment=str_bit_arr[3].x[4]:1->0 hier=top.t -000000 point: comment=str_bit_arr[3].x[5]:0->1 hier=top.t -000000 point: comment=str_bit_arr[3].x[5]:1->0 hier=top.t -000000 point: comment=str_bit_arr[3].y[0]:0->1 hier=top.t -000000 point: comment=str_bit_arr[3].y[0]:1->0 hier=top.t -000001 point: comment=str_bit_arr[4].x[3]:0->1 hier=top.t -000001 point: comment=str_bit_arr[4].x[3]:1->0 hier=top.t -000001 point: comment=str_bit_arr[4].x[4]:0->1 hier=top.t -000000 point: comment=str_bit_arr[4].x[4]:1->0 hier=top.t -000001 point: comment=str_bit_arr[4].x[5]:0->1 hier=top.t -000000 point: comment=str_bit_arr[4].x[5]:1->0 hier=top.t -000000 point: comment=str_bit_arr[4].y[0]:0->1 hier=top.t -000000 point: comment=str_bit_arr[4].y[0]:1->0 hier=top.t -000000 point: comment=str_bit_arr[5].x[3]:0->1 hier=top.t -000000 point: comment=str_bit_arr[5].x[3]:1->0 hier=top.t -000000 point: comment=str_bit_arr[5].x[4]:0->1 hier=top.t -000000 point: comment=str_bit_arr[5].x[4]:1->0 hier=top.t -000000 point: comment=str_bit_arr[5].x[5]:0->1 hier=top.t -000000 point: comment=str_bit_arr[5].x[5]:1->0 hier=top.t -000000 point: comment=str_bit_arr[5].y[0]:0->1 hier=top.t -000000 point: comment=str_bit_arr[5].y[0]:1->0 hier=top.t assign strl.a = clk; alpha a1 (/*AUTOINST*/ // Outputs .toggle_up (toggle_up), // Inputs .clk (clk), .toggle (toggle), .cyc_copy (cyc_copy[7:0])); alpha a2 (/*AUTOINST*/ // Outputs .toggle_up (toggle_up), // Inputs .clk (clk), .toggle (toggle), .cyc_copy (cyc_copy[7:0])); beta b1 (/*AUTOINST*/ // Inputs .clk (clk), .toggle_up (toggle_up)); off o1 (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle)); param#(1) p1 (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle)); param#() p2 (/*AUTOINST*/ // Inputs .clk (clk), .toggle (toggle)); mod_struct i_mod_struct (/*AUTOINST*/ // Inputs .input_struct (strl)); %000001 reg [1:0] memory[121:110]; -000001 point: comment=memory[110][0]:0->1 hier=top.t -000000 point: comment=memory[110][0]:1->0 hier=top.t -000000 point: comment=memory[110][1]:0->1 hier=top.t -000000 point: comment=memory[110][1]:1->0 hier=top.t -000000 point: comment=memory[111][0]:0->1 hier=top.t -000000 point: comment=memory[111][0]:1->0 hier=top.t -000000 point: comment=memory[111][1]:0->1 hier=top.t -000000 point: comment=memory[111][1]:1->0 hier=top.t -000000 point: comment=memory[112][0]:0->1 hier=top.t -000000 point: comment=memory[112][0]:1->0 hier=top.t -000000 point: comment=memory[112][1]:0->1 hier=top.t -000000 point: comment=memory[112][1]:1->0 hier=top.t -000000 point: comment=memory[113][0]:0->1 hier=top.t -000000 point: comment=memory[113][0]:1->0 hier=top.t -000000 point: comment=memory[113][1]:0->1 hier=top.t -000000 point: comment=memory[113][1]:1->0 hier=top.t -000000 point: comment=memory[114][0]:0->1 hier=top.t -000000 point: comment=memory[114][0]:1->0 hier=top.t -000000 point: comment=memory[114][1]:0->1 hier=top.t -000000 point: comment=memory[114][1]:1->0 hier=top.t -000000 point: comment=memory[115][0]:0->1 hier=top.t -000000 point: comment=memory[115][0]:1->0 hier=top.t -000000 point: comment=memory[115][1]:0->1 hier=top.t -000000 point: comment=memory[115][1]:1->0 hier=top.t -000000 point: comment=memory[116][0]:0->1 hier=top.t -000000 point: comment=memory[116][0]:1->0 hier=top.t -000000 point: comment=memory[116][1]:0->1 hier=top.t -000000 point: comment=memory[116][1]:1->0 hier=top.t -000000 point: comment=memory[117][0]:0->1 hier=top.t -000000 point: comment=memory[117][0]:1->0 hier=top.t -000000 point: comment=memory[117][1]:0->1 hier=top.t -000000 point: comment=memory[117][1]:1->0 hier=top.t -000000 point: comment=memory[118][0]:0->1 hier=top.t -000000 point: comment=memory[118][0]:1->0 hier=top.t -000000 point: comment=memory[118][1]:0->1 hier=top.t -000000 point: comment=memory[118][1]:1->0 hier=top.t -000000 point: comment=memory[119][0]:0->1 hier=top.t -000000 point: comment=memory[119][0]:1->0 hier=top.t -000000 point: comment=memory[119][1]:0->1 hier=top.t -000000 point: comment=memory[119][1]:1->0 hier=top.t -000000 point: comment=memory[120][0]:0->1 hier=top.t -000000 point: comment=memory[120][0]:1->0 hier=top.t -000000 point: comment=memory[120][1]:0->1 hier=top.t -000000 point: comment=memory[120][1]:1->0 hier=top.t -000000 point: comment=memory[121][0]:0->1 hier=top.t -000000 point: comment=memory[121][0]:1->0 hier=top.t -000000 point: comment=memory[121][1]:0->1 hier=top.t -000000 point: comment=memory[121][1]:1->0 hier=top.t wire [1023:0] largeish = {992'h0, cyc}; // CHECK_COVER_MISSING(-1) always @ (posedge clk) begin if (cyc != 0) begin cyc <= cyc + 1; memory[cyc + 'd100] <= memory[cyc + 'd100] + 2'b1; toggle <= '0; stoggle.u <= toggle; stoggle.b <= toggle; utoggle.val1 <= real'(cyc[7:0]); ptoggle[0][0] <= toggle; if (cyc == 3) begin str_queue.q.push_back(1); toggle <= '1; str_bit.x <= '1; str_bit.y <= '1; str_bit_arr[4].x <= '1; end if (cyc == 4) begin if (str_queue.q.size() != 1) $stop; toggle <= '0; str_bit.x[3] <= 0; str_bit.y[0] <= 0; str_bit_arr[4].x[3] <= 0; end else if (cyc == 10) begin $write("*-* All Finished *-*\n"); $finish; end end end endmodule module alpha (/*AUTOARG*/ // Outputs toggle_up, // Inputs clk, toggle, cyc_copy ); // t.a1 and t.a2 collapse to a count of 2 000020 input clk; +000020 point: comment=clk:0->1 hier=top.t.a* +000018 point: comment=clk:1->0 hier=top.t.a* %000002 input toggle; -000002 point: comment=toggle:0->1 hier=top.t.a* -000002 point: comment=toggle:1->0 hier=top.t.a* // CHECK_COVER(-1,"top.t.a*","toggle:0->1",2) // CHECK_COVER(-2,"top.t.a*","toggle:1->0",2) // (t.a1 and t.a2) ~000012 input [7:0] cyc_copy; +000012 point: comment=cyc_copy[0]:0->1 hier=top.t.a* +000010 point: comment=cyc_copy[0]:1->0 hier=top.t.a* -000006 point: comment=cyc_copy[1]:0->1 hier=top.t.a* -000004 point: comment=cyc_copy[1]:1->0 hier=top.t.a* -000002 point: comment=cyc_copy[2]:0->1 hier=top.t.a* -000002 point: comment=cyc_copy[2]:1->0 hier=top.t.a* -000002 point: comment=cyc_copy[3]:0->1 hier=top.t.a* -000000 point: comment=cyc_copy[3]:1->0 hier=top.t.a* -000000 point: comment=cyc_copy[4]:0->1 hier=top.t.a* -000000 point: comment=cyc_copy[4]:1->0 hier=top.t.a* -000000 point: comment=cyc_copy[5]:0->1 hier=top.t.a* -000000 point: comment=cyc_copy[5]:1->0 hier=top.t.a* -000000 point: comment=cyc_copy[6]:0->1 hier=top.t.a* -000000 point: comment=cyc_copy[6]:1->0 hier=top.t.a* -000000 point: comment=cyc_copy[7]:0->1 hier=top.t.a* -000000 point: comment=cyc_copy[7]:1->0 hier=top.t.a* // CHECK_COVER(-1,"top.t.a*","cyc_copy[0]:0->1",12) // CHECK_COVER(-2,"top.t.a*","cyc_copy[0]:1->0",10) // CHECK_COVER(-3,"top.t.a*","cyc_copy[1]:0->1",6) // CHECK_COVER(-4,"top.t.a*","cyc_copy[1]:1->0",4) // CHECK_COVER(-5,"top.t.a*","cyc_copy[2]:0->1",2) // CHECK_COVER(-6,"top.t.a*","cyc_copy[2]:1->0",2) // CHECK_COVER(-7,"top.t.a*","cyc_copy[3]:0->1",2) // CHECK_COVER(-8,"top.t.a*","cyc_copy[3]:1->0",0) // CHECK_COVER(-9,"top.t.a*","cyc_copy[4]:0->1",0) // CHECK_COVER(-10,"top.t.a*","cyc_copy[4]:1->0",0) // CHECK_COVER(-11,"top.t.a*","cyc_copy[5]:0->1",0) // CHECK_COVER(-12,"top.t.a*","cyc_copy[5]:1->0",0) // CHECK_COVER(-13,"top.t.a*","cyc_copy[6]:0->1",0) // CHECK_COVER(-14,"top.t.a*","cyc_copy[6]:1->0",0) // CHECK_COVER(-15,"top.t.a*","cyc_copy[7]:0->1",0) // CHECK_COVER(-16,"top.t.a*","cyc_copy[7]:1->0",0) %000002 reg toggle_internal; -000002 point: comment=toggle_internal:0->1 hier=top.t.a* -000002 point: comment=toggle_internal:1->0 hier=top.t.a* // CHECK_COVER(-1,"top.t.a*","toggle_internal:0->1",2) // CHECK_COVER(-2,"top.t.a*","toggle_internal:1->0",2) // (t.a1 and t.a2) %000002 output reg toggle_up; -000002 point: comment=toggle_up:0->1 hier=top.t.a* -000002 point: comment=toggle_up:1->0 hier=top.t.a* // CHECK_COVER(-1,"top.t.a*","toggle_up:0->1",2) // CHECK_COVER(-2,"top.t.a*","toggle_up:1->0",2) // (t.a1 and t.a2) always @ (posedge clk) begin toggle_internal <= toggle; toggle_up <= toggle; end endmodule module beta (/*AUTOARG*/ // Inputs clk, toggle_up ); ~000010 input clk; +000010 point: comment=clk:0->1 hier=top.t.b1 -000009 point: comment=clk:1->0 hier=top.t.b1 %000001 input toggle_up; -000001 point: comment=toggle_up:0->1 hier=top.t.b1 -000001 point: comment=toggle_up:1->0 hier=top.t.b1 // CHECK_COVER(-1,"top.t.b1","toggle_up:0->1",1) // CHECK_COVER(-2,"top.t.b1","toggle_up:1->0",1) /* verilator public_module */ always @ (posedge clk) begin if (0 && toggle_up) begin end end endmodule module off (/*AUTOARG*/ // Inputs clk, toggle ); // verilator coverage_off input clk; // CHECK_COVER_MISSING(-1) // verilator coverage_on %000001 input toggle; -000001 point: comment=toggle:0->1 hier=top.t.o1 -000001 point: comment=toggle:1->0 hier=top.t.o1 // CHECK_COVER(-1,"top.t.o1","toggle:0->1",1) // CHECK_COVER(-2,"top.t.o1","toggle:1->0",1) endmodule module param #(parameter P = 2) (/*AUTOARG*/ // Inputs clk, toggle ); ~000010 input clk; +000010 point: comment=clk:0->1 hier=top.t.p2 -000009 point: comment=clk:1->0 hier=top.t.p2 +000010 point: comment=clk:0->1 hier=top.t.p1 -000009 point: comment=clk:1->0 hier=top.t.p1 %000001 input toggle; -000001 point: comment=toggle:0->1 hier=top.t.p2 -000001 point: comment=toggle:1->0 hier=top.t.p2 -000001 point: comment=toggle:0->1 hier=top.t.p1 -000001 point: comment=toggle:1->0 hier=top.t.p1 %000001 logic z; -000001 point: comment=z:0->1 hier=top.t.p2 -000000 point: comment=z:1->0 hier=top.t.p2 -000000 point: comment=z:0->1 hier=top.t.p1 -000000 point: comment=z:1->0 hier=top.t.p1 for (genvar i = 0; i < P; i++) begin %000001 logic x; -000001 point: comment=genblk1[0].x:0->1 hier=top.t.p2 -000001 point: comment=genblk1[0].x:1->0 hier=top.t.p2 -000001 point: comment=genblk1[1].x:0->1 hier=top.t.p2 -000001 point: comment=genblk1[1].x:1->0 hier=top.t.p2 -000001 point: comment=genblk1[0].x:0->1 hier=top.t.p1 -000001 point: comment=genblk1[0].x:1->0 hier=top.t.p1 always @ (posedge clk) begin x <= toggle; end for (genvar j = 0; j < 3; j++) begin %000002 logic [2:0] y; -000001 point: comment=genblk1[0].genblk1[0].y[0]:0->1 hier=top.t.p2 -000000 point: comment=genblk1[0].genblk1[0].y[0]:1->0 hier=top.t.p2 -000002 point: comment=genblk1[0].genblk1[0].y[1]:0->1 hier=top.t.p2 -000001 point: comment=genblk1[0].genblk1[0].y[1]:1->0 hier=top.t.p2 -000001 point: comment=genblk1[0].genblk1[0].y[2]:0->1 hier=top.t.p2 -000001 point: comment=genblk1[0].genblk1[0].y[2]:1->0 hier=top.t.p2 -000001 point: comment=genblk1[0].genblk1[1].y[0]:0->1 hier=top.t.p2 -000000 point: comment=genblk1[0].genblk1[1].y[0]:1->0 hier=top.t.p2 -000002 point: comment=genblk1[0].genblk1[1].y[1]:0->1 hier=top.t.p2 -000001 point: comment=genblk1[0].genblk1[1].y[1]:1->0 hier=top.t.p2 -000001 point: comment=genblk1[0].genblk1[1].y[2]:0->1 hier=top.t.p2 -000001 point: comment=genblk1[0].genblk1[1].y[2]:1->0 hier=top.t.p2 -000001 point: comment=genblk1[0].genblk1[2].y[0]:0->1 hier=top.t.p2 -000000 point: comment=genblk1[0].genblk1[2].y[0]:1->0 hier=top.t.p2 -000002 point: comment=genblk1[0].genblk1[2].y[1]:0->1 hier=top.t.p2 -000001 point: comment=genblk1[0].genblk1[2].y[1]:1->0 hier=top.t.p2 -000001 point: comment=genblk1[0].genblk1[2].y[2]:0->1 hier=top.t.p2 -000001 point: comment=genblk1[0].genblk1[2].y[2]:1->0 hier=top.t.p2 -000001 point: comment=genblk1[1].genblk1[0].y[0]:0->1 hier=top.t.p2 -000000 point: comment=genblk1[1].genblk1[0].y[0]:1->0 hier=top.t.p2 -000002 point: comment=genblk1[1].genblk1[0].y[1]:0->1 hier=top.t.p2 -000001 point: comment=genblk1[1].genblk1[0].y[1]:1->0 hier=top.t.p2 -000001 point: comment=genblk1[1].genblk1[0].y[2]:0->1 hier=top.t.p2 -000001 point: comment=genblk1[1].genblk1[0].y[2]:1->0 hier=top.t.p2 -000001 point: comment=genblk1[1].genblk1[1].y[0]:0->1 hier=top.t.p2 -000000 point: comment=genblk1[1].genblk1[1].y[0]:1->0 hier=top.t.p2 -000002 point: comment=genblk1[1].genblk1[1].y[1]:0->1 hier=top.t.p2 -000001 point: comment=genblk1[1].genblk1[1].y[1]:1->0 hier=top.t.p2 -000001 point: comment=genblk1[1].genblk1[1].y[2]:0->1 hier=top.t.p2 -000001 point: comment=genblk1[1].genblk1[1].y[2]:1->0 hier=top.t.p2 -000001 point: comment=genblk1[1].genblk1[2].y[0]:0->1 hier=top.t.p2 -000000 point: comment=genblk1[1].genblk1[2].y[0]:1->0 hier=top.t.p2 -000002 point: comment=genblk1[1].genblk1[2].y[1]:0->1 hier=top.t.p2 -000001 point: comment=genblk1[1].genblk1[2].y[1]:1->0 hier=top.t.p2 -000001 point: comment=genblk1[1].genblk1[2].y[2]:0->1 hier=top.t.p2 -000001 point: comment=genblk1[1].genblk1[2].y[2]:1->0 hier=top.t.p2 -000001 point: comment=genblk1[0].genblk1[0].y[0]:0->1 hier=top.t.p1 -000000 point: comment=genblk1[0].genblk1[0].y[0]:1->0 hier=top.t.p1 -000002 point: comment=genblk1[0].genblk1[0].y[1]:0->1 hier=top.t.p1 -000001 point: comment=genblk1[0].genblk1[0].y[1]:1->0 hier=top.t.p1 -000001 point: comment=genblk1[0].genblk1[0].y[2]:0->1 hier=top.t.p1 -000001 point: comment=genblk1[0].genblk1[0].y[2]:1->0 hier=top.t.p1 -000001 point: comment=genblk1[0].genblk1[1].y[0]:0->1 hier=top.t.p1 -000000 point: comment=genblk1[0].genblk1[1].y[0]:1->0 hier=top.t.p1 -000002 point: comment=genblk1[0].genblk1[1].y[1]:0->1 hier=top.t.p1 -000001 point: comment=genblk1[0].genblk1[1].y[1]:1->0 hier=top.t.p1 -000001 point: comment=genblk1[0].genblk1[1].y[2]:0->1 hier=top.t.p1 -000001 point: comment=genblk1[0].genblk1[1].y[2]:1->0 hier=top.t.p1 -000001 point: comment=genblk1[0].genblk1[2].y[0]:0->1 hier=top.t.p1 -000000 point: comment=genblk1[0].genblk1[2].y[0]:1->0 hier=top.t.p1 -000002 point: comment=genblk1[0].genblk1[2].y[1]:0->1 hier=top.t.p1 -000001 point: comment=genblk1[0].genblk1[2].y[1]:1->0 hier=top.t.p1 -000001 point: comment=genblk1[0].genblk1[2].y[2]:0->1 hier=top.t.p1 -000001 point: comment=genblk1[0].genblk1[2].y[2]:1->0 hier=top.t.p1 always @ (negedge clk) begin y <= {toggle, ~toggle, 1'b1}; end end end if (P > 1) begin : gen_1 assign z = 1; end endmodule module mod_struct(/*AUTOARG*/ // Inputs input_struct ); ~000010 input str_logic input_struct; +000010 point: comment=input_struct.a:0->1 hier=top.t.i_mod_struct -000009 point: comment=input_struct.a:1->0 hier=top.t.i_mod_struct endmodule verilator-5.042/test_regress/t/t_trace_cat.v0000644000542200017500000000055015101701376021525 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t ( input wire clk ); integer cyc; initial cyc = 0; always @ (posedge clk) begin cyc <= cyc + 1; end endmodule verilator-5.042/test_regress/t/t_ccache_report.py0000755000542200017500000000305415101701376022571 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') if test.have_dev_gcov: test.skip("Code coverage build upsets ccache") test.top_filename = "t_a1_first_cc.v" if not test.cfg_with_ccache: test.skip("Requires configuring with ccache") # This test requires rebuilding the object files to check the ccache log for filename in glob.glob(test.obj_dir + "/*.o"): test.unlink_ok(filename) test.compile(verilator_flags2=['--trace-vcd'], make_flags=["ccache-report"]) report = test.obj_dir + "/" + test.vm_prefix + "__ccache_report.txt" # We do not actually want to make this test depend on whether the file was # cached or not, so trim the report to ignore actual caching behaviour test.run(cmd=["sed", "-i", "-e", "'s/ : .*/ : IGNORED/; /|/s/.*/IGNORED/;'", report]) test.files_identical(report, "t/" + test.name + "__ccache_report_initial.out") # Now rebuild again (should be all up to date) test.run(logfile=test.obj_dir + "/rebuild.log", cmd=[ os.environ["MAKE"], "-C " + test.obj_dir, "-f " + test.vm_prefix + ".mk", test.vm_prefix, "ccache-report" ]) test.files_identical(report, "t/" + test.name + "__ccache_report_rebuild.out") test.passes() verilator-5.042/test_regress/t/t_lint_mod_paren_bad.py0000755000542200017500000000107315101701376023567 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.lint(verilator_flags2=["--lint-only -Wno-DECLFILENAME"], fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_mod_dollar$.py0000755000542200017500000000141115101701376022143 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') # This doesn't use the general compile rule as we want to make sure we form # prefix properly using post-escaped identifiers test.run(cmd=[ os.environ["VERILATOR_ROOT"] + "/bin/verilator", "--cc", "--Mdir " + test.obj_dir + "/t_mod_dollar", "--exe --build --main", 't/t_mod_dollar$.v', ], verilator_run=True) test.passes() verilator-5.042/test_regress/t/t_class_new_scoped_bad.v0000644000542200017500000000052315101701376023721 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package Pkg; endpackage class C; endclass module t; C c; initial begin c = Pkg::new; // Bad end endmodule verilator-5.042/test_regress/t/t_class_param_extends_static_member_function_access.py0000755000542200017500000000073415101701376032135 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_func_nansi_dup_bad.v0000644000542200017500000000071415101701376023403 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 typedef int T; module test; task t4; input [7:0] bad4; reg bad4; reg bad4; // <--- Error (duplicate) endtask task t5; input [7:0] bad5; input [7:0] bad5; // <--- Error (duplicate) reg bad5; endtask endmodule verilator-5.042/test_regress/t/t_math_signed.py0000755000542200017500000000073415101701376022254 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_force_release_var.py0000755000542200017500000000073415101701376023440 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_trace_saif_sc.py0000755000542200017500000000124615101701376022556 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_trace_fst_sc.v" if not test.have_sc: test.skip("No SystemC installed") test.compile(verilator_flags2=["--trace-saif --sc"]) test.execute() test.saif_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_gantt_c.cpp0000644000542200017500000000064415101701376021540 0ustar mahmoudyfreeshell// -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // //************************************************************************* extern "C" { int dpii_return(int i) { return i; } } verilator-5.042/test_regress/t/t_func_const_bad.py0000755000542200017500000000076615101701376022746 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_pipe_filter.out0000644000542200017500000000202615101701376022444 0ustar mahmoudyfreeshell`line 1 "t/t_pipe_filter.v" 1 `line 3 "t/t_pipe_filter.v" 0 `line 7 "t/t_pipe_filter.v" 0 `line 11 "t/t_pipe_filter.v" 0 example line 10; example line 11; `line 14 "t/t_pipe_filter.v" 0 `line 14 "t/t_pipe_filter.v" 0 `line 1 "t/t_pipe_filter_inc.vh" 1 int lint_off_line_8 = 1; `line 2 "t/t_pipe_filter_inc.vh" 0 int lint_off_line_9 = 1; `line 5 "t/t_pipe_filter_inc.vh" 0 `line 9 "t/t_pipe_filter_inc.vh" 0 inc line 6; inc line 7; inc line 8; inc line 9; `line 14 "t/t_pipe_filter_inc.vh" 0 `line 14 "t/t_pipe_filter.v" 2 `line 15 "t/t_pipe_filter.v" 0 `line 16 "t/t_pipe_filter.v" 0 `line 1 "t/t_pipe_filter_inc.vh" 1 int lint_off_line_8 = 1; `line 2 "t/t_pipe_filter_inc.vh" 0 int lint_off_line_9 = 1; `line 5 "t/t_pipe_filter_inc.vh" 0 `line 9 "t/t_pipe_filter_inc.vh" 0 inc line 6; inc line 7; inc line 8; inc line 9; `line 14 "t/t_pipe_filter_inc.vh" 0 `line 16 "t/t_pipe_filter.v" 2 `line 18 "t/t_pipe_filter.v" 0 example line 15; example line 16; `line 21 "t/t_pipe_filter.v" 0 verilator-5.042/test_regress/t/t_queue_concat_assign.v0000644000542200017500000000135615101701376023624 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t; initial begin bit q1[$] = {1'b1}; bit q2[$]; bit q3[$]; bit [1:0] d1[$] = {2'b10}; bit [1:0] d2[$]; bit [1:0] d3[$]; q2 = {q1}; // consCC if (q2.size != 1) $stop; if (q2[0] != 1) $stop; q3 = q1; if (q3.size != 1) $stop; if (q3[0] != 1) $stop; if (d1[0] != 2'b10) $stop; d2 = {2'b11}; if (d2[0] != 2'b11) $stop; d3 = {d1, d2}; if (d3[0] != 2'b10) $stop; if (d3[1] != 2'b11) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_split_var_types.py0000755000542200017500000000077315101701376023224 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--trace-vcd']) test.execute() test.passes() verilator-5.042/test_regress/t/t_var_assign_landr_noexpand.py0000755000542200017500000000104315101701376025174 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_var_assign_landr.v" test.compile(verilator_flags2=['-fno-expand']) test.execute() test.passes() verilator-5.042/test_regress/t/t_lint_latch_bad_3.v0000644000542200017500000000264115101701376022754 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module for issue #1609 // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by Julien Margetts. // SPDX-License-Identifier: Unlicense module t (/*AUTOARG*/ reset, a, b, c, en, o1, o2, o3, o4, o5); input reset; input a; input b; input c; input en; output reg o1; // Always assigned output reg o2; // " output reg o3; // " output reg o4; // " output reg o5; // Latch always_comb if (reset) begin o1 = 1'b0; o2 = 1'b0; o3 = 1'b0; o4 = 1'b0; o5 = 1'b0; end else begin o1 = 1'b1; if (en) begin o2 = 1'b0; if (a) begin o3 = a; o5 = 1'b1; end else begin o3 = ~a; o5 = a; end // o3 is not assigned in either path of this if/else // but no latch because always assigned above if (c) begin o2 = a ^ b; o4 = 1'b1; end else o4 = ~a ^ b; o2 = 1'b1; end else begin o2 = 1'b1; if (b) begin o3 = ~a | b; o5 = ~b; end else begin o3 = a & ~b; // No assignment to o5, expect Warning-LATCH end o4 = 1'b0; end end endmodule verilator-5.042/test_regress/t/t_param_default_presv_bad.out0000644000542200017500000000142715101701376024777 0ustar mahmoudyfreeshell%Warning-NEWERSTD: t/t_param_default_bad.v:7:26: Parameter requires default value, or use IEEE 1800-2009 or later. 7 | module m #(parameter int Foo); | ^~~ ... For warning description see https://verilator.org/warn/NEWERSTD?v=latest ... Use "/* verilator lint_off NEWERSTD */" and lint_on around source to disable this message. %Error: t/t_param_default_bad.v:7:26: Parameter without default value is never given value (IEEE 1800-2023 6.20.1): 'Foo' : ... note: In instance 't.foo' 7 | module m #(parameter int Foo); | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_interface_gen2.v0000644000542200017500000000335715101701376022463 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2013 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 // Very simple test for interface pathclearing module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=1; ifc #(2) itopa(); ifc #(4) itopb(); sub ca (.isub(itopa), .clk); sub cb (.isub(itopb), .clk); always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d result=%b %b\n", $time, cyc, itopa.valueo, itopb.valueo); `endif cyc <= cyc + 1; itopa.valuei <= cyc[1:0]; itopb.valuei <= cyc[3:0]; if (cyc==1) begin if (itopa.WIDTH != 2) $stop; if (itopb.WIDTH != 4) $stop; if ($bits(itopa.valueo) != 2) $stop; if ($bits(itopb.valueo) != 4) $stop; if ($bits(itopa.out_modport.valueo) != 2) $stop; if ($bits(itopb.out_modport.valueo) != 4) $stop; end if (cyc==4) begin if (itopa.valueo != 2'b11) $stop; if (itopb.valueo != 4'b0011) $stop; end if (cyc==5) begin if (itopa.valueo != 2'b00) $stop; if (itopb.valueo != 4'b0100) $stop; end if (cyc==20) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule interface ifc #(parameter WIDTH = 1); // verilator lint_off MULTIDRIVEN logic [WIDTH-1:0] valuei; logic [WIDTH-1:0] valueo; // verilator lint_on MULTIDRIVEN modport out_modport (input valuei, output valueo); endinterface // Note not parameterized module sub ( ifc.out_modport isub, input clk ); always @(posedge clk) isub.valueo <= isub.valuei + 1; endmodule verilator-5.042/test_regress/t/t_func_recurse_param.py0000755000542200017500000000073415101701376023635 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute() test.passes() verilator-5.042/test_regress/t/t_opt_table_struct.v0000644000542200017500000000167015101701376023161 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; struct packed { bit [31:0] a; bit [15:0] b; bit [ 7:0] c; } s; reg [2:0] cyc; initial cyc = 0; always @(posedge clk) cyc <= cyc + 1; always @* begin case (cyc) 3'b000: s = {32'd0, 16'd1, 8'd2}; 3'b001: s = {32'd1, 16'd2, 8'd3}; 3'b010: s = {32'd2, 16'd3, 8'd4}; 3'b100: s = {32'd4, 16'd5, 8'd6}; 3'b101: s = {32'd5, 16'd6, 8'd7}; default: s = '0; endcase end always @(posedge clk) begin $display("cyle %d = { %d, %d, %d }", cyc, s.a, s.b, s.c); if (cyc == 7) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule verilator-5.042/test_regress/t/t_uniqueif_fail2.py0000755000542200017500000000131415101701376022667 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_uniqueif.v" test.compile(v_flags2=['+define+FAILING_ASSERTION2'], verilator_flags2=['--assert'], nc_flags2=['+assert'], fails=test.nc) test.execute(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface_virtual_sched_nba.py0000755000542200017500000000103515101701376025461 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute(expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_strength_strong1_strong1_bad.py0000755000542200017500000000076615101701376025575 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('linter') test.lint(fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_sys_readmem_bad_addr.py0000755000542200017500000000102415101701376024073 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile() test.execute(fails=test.vlt_all, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_struct_assign.out0000644000542200017500000000014215101701376023027 0ustar mahmoudyfreeshell( 3, 4) ( 3, 4) %p='{fst:'h3, snd:'h4} *-* All Finished *-* verilator-5.042/test_regress/t/t_assert_enabled_bad.py0000755000542200017500000000110015101701376023537 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_assert_on.v" test.compile(verilator_flags2=['--assert'], nc_flags2=['+assert']) test.execute(fails=True) test.passes() verilator-5.042/test_regress/t/t_x_assign_unique_1.py0000755000542200017500000000124615101701376023412 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you can # redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_x_assign.cpp" test.top_filename = "t/t_x_assign.v" test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--x-assign unique --exe", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_stack_check_fail.py0000755000542200017500000000125015101701376023221 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_stack_check.v" test.compile( verilator_flags2=['--binary --debug-stack-check', '--CFLAGS', '"-D_VL_TEST_RLIMIT_FAIL"']) test.execute() test.file_grep(test.run_log_filename, r'.*%Warning: System has stack size') test.passes() verilator-5.042/test_regress/t/t_tagged.v0000644000542200017500000000222615101701376021035 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; typedef union tagged { void m_invalid; int m_int; } u_t; u_t u; string s; initial begin begin u = tagged m_invalid; s = $sformatf("%p", u); $display("%s e.g. '{tagged m_invalid:void}", s); end case (u) matches default: ; endcase case (u) matches tagged m_invalid: ; tagged m_int: $stop; default: $stop; endcase if (u matches tagged m_invalid) ; if (u matches tagged m_int .n) $stop; u = tagged m_int (123); s = $sformatf("%p", u); $display("'%s e.g. '{tagged m_int:123}", s); case (u) matches tagged m_invalid: $stop; tagged m_int .n: if (n !== 123) $stop; default: $stop; endcase if (u matches tagged m_invalid) $stop; if (u matches tagged m_int .n) if (n != 123) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_randomize_union_bad.v0000644000542200017500000000167415101701376023616 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2024 by PlanV GmbH. // SPDX-License-Identifier: CC0-1.0 typedef union { int int_value; bit [31:0] bits; } UnpackedUnion; class UnpackedUnionErrorTest; rand UnpackedUnion union_instance; function new(); union_instance.bits = 32'b0; endfunction endclass module t_randomize_union_bad; UnpackedUnionErrorTest test_unpacked_union; initial begin test_unpacked_union = new(); repeat(10) begin int success; success = test_unpacked_union.randomize(); if (success != 1) $stop; $display("UnpackedUnion: int_value: %b, bits: %b", test_unpacked_union.union_instance.int_value, test_unpacked_union.union_instance.bits); end $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_class_new_default.out0000644000542200017500000000120615101701376023623 0ustar mahmoudyfreeshell%Error-UNSUPPORTED: t/t_class_new_default.v:10:17: Unsupported: new constructor 'default' argument 10 | function new(default); | ^~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_class_new_default.v:17:24: Unsupported: new constructor 'default' argument 17 | extern function new(default); | ^~~~~~~ %Error-UNSUPPORTED: t/t_class_new_default.v:20:25: Unsupported: new constructor 'default' argument 20 | function ClsDefFwd::new(default); | ^~~~~~~ %Error: Exiting due to verilator-5.042/test_regress/t/t_alias_cyclic_bad.v0000644000542200017500000000120215101701376023020 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias' // // Simple bi-directional transitive alias test. // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2025 by Antmicro. // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ // Inputs clk ); input clk; wire [31:0] a = 32'hdeadbeef; wire [31:0] b; alias a = a; alias a = b; alias b = a; always @(posedge clk) begin `ifdef TEST_VERBOSE $write("a = %x, b = %x\n", a, b); `endif if (b != 32'hdeadbeef) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_clk_concat5.v0000644000542200017500000000402015101701376021761 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty. // SPDX-License-Identifier: CC0-1.0 module some_module ( input [3:0] i_clks ); logic [ 1 : 0 ] some_state; logic [1:0] some_other_state; always @(posedge i_clks[3]) begin case (some_state) 2'b11: if (some_other_state == 0) some_state <= 2'b00; default: $display ("This is a display statement"); endcase if (i_clks[3]) some_other_state <= 0; $write("*-* All Finished *-*\n"); $finish; end endmodule `define BROKEN module t1( input [3:0] i_clks, input i_clk0, input i_clk1 ); some_module some_module ( .i_clks (i_clks) ); endmodule module t2( input [2:0] i_clks, input i_clk0, input i_clk1, input i_clk2, input i_data ); logic [3:0] the_clks; logic data_q; assign the_clks[3] = i_clk1; assign the_clks[2] = i_clk2; assign the_clks[1] = i_clk1; assign the_clks[0] = i_clk0; always @(posedge i_clk0) begin data_q <= i_data; end t1 t1 ( .i_clks (the_clks), .i_clk0 (i_clk0), .i_clk1 (i_clk1) ); endmodule module t( /*AUTOARG*/ // Inputs clk /*verilator clocker*/, input clk0 /*verilator clocker*/, input clk1 /*verilator clocker*/, input clk2 /*verilator clocker*/, input data_in ); input clk; logic [2:0] clks; assign clks = {1'b0, clk1, clk0}; t2 t2 ( .i_clks (clks), .i_clk0 (clk0), .i_clk1 (clk), .i_clk2 (clk2), .i_data (data_in) ); // initial begin // $write("*-* All Finished *-*\n"); // $finish; // end endmodule verilator-5.042/test_regress/t/t_func_const.v0000644000542200017500000000711015101701376021740 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 package testpackage; localparam PARAM = 1024 >> 3; endpackage import testpackage::*; module t; localparam P4 = f_add(P3,1); localparam P8 = f_add2(P3,P3,f_add(1,1)); localparam P5 = f_while(7); localparam P16 = f_for(P4); localparam P18 = f_case(P4); localparam P6 = f_return(P4); localparam P3 = 3; localparam P128 = f_package(); localparam [15:0] PSEL = f_concat_sel(16'h4321); typedef struct packed { logic [7:0] data; } type_t; typedef type_t [1:0] flist; localparam flist PLIST = {8'd4,8'd8}; localparam flist PARR = f_list_swap_2(PLIST); typedef struct packed { logic first; logic second; logic [31:0] data; } bigstruct_t; localparam bigstruct_t bigparam = f_return_struct(1'b1, 1'b0, 32'hfff12fff); initial begin `ifdef TEST_VERBOSE $display("P5=%0d P8=%0d P16=%0d P18=%0d",P5,P8,P16,P18); `endif if (P3 !== 3) $stop; if (P4 !== 4) $stop; if (P5 !== 5) $stop; if (P6 !== 6) $stop; if (P8 !== 8) $stop; if (P16 !== 16) $stop; if (P18 !== 18) $stop; if (PARR[0] != PLIST[1]) $stop; if (PARR[1] != PLIST[0]) $stop; if (bigparam.first != 1'b1) $stop; if (bigparam.second != 1'b0) $stop; if (bigparam.data != 32'hfff12fff) $stop; if (P128 != 128) $stop; if (PSEL != 16'h1234) $stop; $write("*-* All Finished *-*\n"); $finish; end function integer f_package(); return PARAM; endfunction function integer f_add(input [31:0] a, input [31:0] b); f_add = a+b; endfunction // Speced ok: function called from function function integer f_add2(input [31:0] a, input [31:0] b, input [31:0] c); f_add2 = f_add(a,b)+c; endfunction // Speced ok: local variables function integer f_for(input [31:0] a); integer i; integer times; begin times = 1; for (i=0; i1) break; end while (1) begin out = out+1; if (a>1) return 2+out; end f_return = 0; endfunction function flist f_list_swap_2(input flist in_list); f_list_swap_2[0].data = in_list[1].data; f_list_swap_2[1].data = in_list[0].data; endfunction function bigstruct_t f_return_struct(input first, input second, input [31:0] data); bigstruct_t result; result.data = data; result.first = first; result.second = second; return result; endfunction function [15:0] f_concat_sel(input [15:0] in); reg [3:0] tmp1, tmp2, tmp3, tmp4; {tmp4, tmp3, tmp2, tmp1} = in; f_concat_sel = {tmp1, tmp2, tmp3, tmp4}; endfunction endmodule verilator-5.042/test_regress/t/t_trace_two_port_sc.py0000755000542200017500000000250615101701376023511 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') if not test.have_sc: test.skip("No SystemC installed") top_filename = "t_trace_two_a.v" test.pli_filename = "t/t_trace_two_sc.cpp" test.compile(make_main=False, verilator_make_gmake=False, top_filename='t_trace_two_b.v', vm_prefix='Vt_trace_two_b', verilator_flags2=['-sc -trace']) test.run(logfile=test.obj_dir + "/make_first_ALL.log", cmd=[ os.environ["MAKE"], "-C", test.obj_dir, "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp" ]) test.compile(make_main=False, top_filename='t_trace_two_a.v', verilator_flags2=['-sc', '-exe', '-trace', test.pli_filename], v_flags2=['+define+TEST_DUMPPORTS']) test.execute() if test.vlt_all: test.file_grep(test.trace_filename, r'\$enddefinitions') test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_dfg_circular_merged_scc.py0000755000542200017500000000070615101701376024570 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.compile() test.passes() verilator-5.042/test_regress/t/t_strength_strongest_constant.v0000644000542200017500000000143415101701376025461 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 module t (clk1, clk2); input wire clk1; input wire clk2; wire a; nor (pull0, weak1) n1(a, 0, 0); assign (strong0, weak1) a = 0; wire [1:0] b; assign (weak0, supply1) b = '1; assign b = clk1 ? '0 : 'z; wire c = 1; assign (weak0, pull1) c = clk1 & clk2; always begin if (!a && b === '1 && c) begin $write("*-* All Finished *-*\n"); $finish; end else begin $write("Error: a = %b, b = %b, c = %b ", a, b, c); $write("expected: a = 0, b = 11, c = 1\n"); $stop; end end endmodule verilator-5.042/test_regress/t/t_flag_quiet_stats3.py0000755000542200017500000000126015101701376023406 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.top_filename = "t/t_flag_quiet_stats.v" test.compile(verilator_flags2=['--quiet --no-quiet-stats'], verilator_make_gcc=False, logfile=test.run_log_filename) test.file_grep(test.compile_log_filename, r'V e r i l a t') test.passes() verilator-5.042/test_regress/t/t_case_call_count.py0000755000542200017500000000107315101701376023105 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=['--stats']) test.execute() test.file_grep(test.stats, r'Impure case expressions\s+(\d+)', 2) test.passes() verilator-5.042/test_regress/t/t_constraint_pure_nonabs_bad.out0000644000542200017500000000062215101701376025527 0ustar mahmoudyfreeshell%Error: t/t_constraint_pure_nonabs_bad.v:8:21: Illegal to have 'pure constraint' in non-abstract class (IEEE 1800-2023 18.5.2) : ... note: In instance 't' 8 | pure constraint raintBad; | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_lint_edge_real_bad.v0000644000542200017500000000074615101701376023352 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2022 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs rbad, rok ); input real rbad; input real rok; event ebad; struct packed { int a; } sok; always @ (rok) $stop; always @ (sok) $stop; always @ (posedge rbad) $stop; always @ (posedge ebad) $stop; endmodule verilator-5.042/test_regress/t/t_timing_unset3.py0000755000542200017500000000113415101701376022555 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_clocking_notiming.v" test.compile( # --timing/--no-timing not specified fails=True, expect_filename=test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_interface_arraymux.v0000644000542200017500000000625215101701376023475 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by John Stevenson. // SPDX-License-Identifier: CC0-1.0 package pkg; typedef logic [31:0] unique_id_t; typedef struct packed { unique_id_t foo; } inner_thing_t; typedef struct packed { inner_thing_t bar; inner_thing_t baz; } outer_thing_t; endpackage import pkg::*; interface the_intf #(parameter M=5); outer_thing_t [M-1:0] things; logic valid; modport i ( output things, output valid); modport t ( input things, input valid); endinterface module ThingMuxOH #( parameter NTHINGS = 1, parameter M = 5 ) ( input logic [NTHINGS-1:0] select_oh, the_intf.t things_in [NTHINGS-1:0], the_intf.i thing_out ); assign thing_out.valid = things_in[0].valid; endmodule module ThingMuxShort #( parameter NTHINGS = 1, parameter M = 5 ) ( input logic [NTHINGS-1:0] select_oh, the_intf.t things_in [NTHINGS], the_intf.i thing_out ); assign thing_out.valid = things_in[0].valid; endmodule module Thinker #( parameter M = 5, parameter N = 2) ( input logic clk, input logic reset, input unique_id_t uids[0:N-1], the_intf.t thing_inp, the_intf.i thing_out ); the_intf #(.M(M)) curr_things [N-1:0] (); the_intf #(.M(M)) prev_things [N-1:0] (); the_intf #(.M(M)) s_things [N] (); the_intf #(.M(M)) curr_thing (); the_intf #(.M(M)) prev_thing (); the_intf #(.M(M)) s_thing (); logic [N-1:0] select_oh; // 1st mux: ThingMuxOH #( .NTHINGS ( N ), .M ( M )) curr_thing_mux( .select_oh( select_oh ), .things_in( curr_things ), .thing_out( curr_thing )); // 2nd mux, comment this out and no problem: ThingMuxOH #( .NTHINGS ( N ), .M ( M )) prev_thing_mux( .select_oh( select_oh ), .things_in( prev_things ), .thing_out( prev_thing )); // 3rd mux, using short array nomenclature: ThingMuxShort #( .NTHINGS ( N ), .M ( M )) s_thing_mux( .select_oh( select_oh ), .things_in( s_things ), .thing_out( s_thing )); endmodule module t ( input logic clk, input logic reset ); localparam M = 5; localparam N = 2; unique_id_t uids[0:N-1]; the_intf #(.M(M)) thing_inp(); the_intf #(.M(M)) thing_out(); Thinker #( .M ( M ), .N ( N )) thinker( .clk ( clk ), .reset ( reset ), .uids ( uids ), .thing_inp( thing_inp ), .thing_out( thing_out )); // Previously there was a problem in V3Inst if non-default parameters was used localparam K = 2; the_intf #(.M(K)) thing_inp2(); the_intf #(.M(K)) thing_out2(); Thinker #( .M ( K ), .N ( N )) thinker2( .clk ( clk ), .reset ( reset ), .uids ( uids ), .thing_inp( thing_inp2 ), .thing_out( thing_out2 )); endmodule verilator-5.042/test_regress/t/t_interface_generic_task_bad.out0000755000542200017500000000065615101701376025440 0ustar mahmoudyfreeshell%Error: t/t_interface_generic_task_bad.v:17:7: Can't find definition of 'setup' in dotted task/function: 'a.setup' : ... note: In instance 't.genericModule' 17 | a.setup(); | ^~~~~ ... Known scopes under 'setup': ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to verilator-5.042/test_regress/t/t_sys_readmem_bad_notfound.v0000644000542200017500000000062015101701376024630 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2003 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t; reg [175:0] hex [15:0]; initial begin $readmemh("t/t_sys_readmem_bad_NOTFOUND.mem", hex); $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_lint_iface_topmodule_bad.v0000644000542200017500000000153315101701376024575 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Josh Redford. // SPDX-License-Identifier: CC0-1.0 interface my_if #( parameter integer DW ) (); logic valid; logic [DW-1:0] data ; modport slave_mp ( input valid, input data ); modport master_mp ( output valid, output data ); endinterface module t ( input wire clk, my_if.slave_mp in_if, my_if.master_mp out_if ); my_if my_i (); always @(posedge clk) begin my_i.valid <= in_if.valid; my_i.data <= in_if.data; end assign out_if.valid = my_i.valid; assign out_if.data = my_i.data; endmodule verilator-5.042/test_regress/t/t_typedef_array.v0000644000542200017500000000120215101701376022431 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by James Pallister. // SPDX-License-Identifier: CC0-1.0 typedef logic logic_alias_t; module t; logic_alias_t [6:1] signal; // verilator lint_off ASCRANGE logic_alias_t [1:6] signal2; // verilator lint_on ASCRANGE initial begin signal[6:1] = 'b100001; signal[3] = 'b1; signal2[1:6] = 'b100001; signal2[4] = 'b1; if (signal != 'b100101) $stop; if (signal2 != 'b100101) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_trace_no_top_name2_vcd.py0000755000542200017500000000127715101701376024367 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.pli_filename = "t/t_trace_no_top_name2.cpp" test.top_filename = "t/t_trace_no_top_name2.v" test.compile(make_main=False, verilator_flags2=["--trace-vcd --exe", test.pli_filename]) test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() verilator-5.042/test_regress/t/t_trace_param.py0000755000542200017500000000076215101701376022251 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.compile(v_flags2=["--trace-vcd"]) test.execute() test.passes() verilator-5.042/test_regress/t/t_flag_parameter_pkg.v0000644000542200017500000000071115101701376023411 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2021 by Adrien Le Masle. // SPDX-License-Identifier: CC0-1.0 package pack_a; parameter PARAM_A = 0; endpackage : pack_a //module t; module t; parameter PARAM_A = 0; initial begin $display(PARAM_A); if (PARAM_A != 1) $stop; $write("*-* All Finished *-*\n"); $finish; end endmodule verilator-5.042/test_regress/t/t_tri_gate_notif0.py0000755000542200017500000000136515101701376023050 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') test.pli_filename = "t/t_tri_gate.cpp" test.top_filename = "t/t_tri_gate.v" test.compile(make_top_shell=False, make_main=False, v_flags2=['+define+T_NOTIF0'], make_flags=['CPPFLAGS_ADD=-DT_NOTIF0'], verilator_flags2=["--exe", test.pli_filename]) test.execute() test.passes() verilator-5.042/test_regress/t/t_forceable_var.cpp0000644000542200017500000000654015101701376022714 0ustar mahmoudyfreeshell// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2021 by Geza Lore. // SPDX-License-Identifier: CC0-1.0 #include "verilatedos.h" #include "verilated.h" #include #if VM_TRACE #include "verilated_vcd_c.h" #endif #include VM_PREFIX_INCLUDE #include VM_PREFIX_ROOT_INCLUDE int main(int argc, char** argv) { const std::unique_ptr contextp{new VerilatedContext}; contextp->debug(0); contextp->commandArgs(argc, argv); srand48(5); const std::unique_ptr topp{new VM_PREFIX{"top"}}; topp->clk = false; topp->rst = true; topp->eval(); #if VM_TRACE contextp->traceEverOn(true); std::unique_ptr tfp{new VerilatedVcdC}; topp->trace(tfp.get(), 99); tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); tfp->dump(contextp->time()); #endif contextp->timeInc(5); topp->clk = true; topp->eval(); topp->rst = false; topp->eval(); #if VM_TRACE tfp->dump(contextp->time()); #endif contextp->timeInc(5); while (contextp->time() < 1000 && !contextp->gotFinish()) { topp->clk = !topp->clk; topp->eval(); if (topp->clk) { bool needsSecondEval = false; if (topp->cyc == 13) { topp->rootp->t__DOT__var_1__VforceEn = 1; topp->rootp->t__DOT__var_1__VforceVal = 1; needsSecondEval = true; } if (topp->cyc == 15) { topp->rootp->t__DOT__var_1__VforceVal = 0; needsSecondEval = true; } if (topp->cyc == 18) { topp->rootp->t__DOT__var_1__VforceEn = 0; needsSecondEval = true; } if (topp->cyc == 14) { topp->rootp->t__DOT__var_8__VforceEn = 0xff; topp->rootp->t__DOT__var_8__VforceVal = 0xf5; needsSecondEval = true; } if (topp->cyc == 16) { topp->rootp->t__DOT__var_8__VforceVal = 0x5f; needsSecondEval = true; } if (topp->cyc == 19) { topp->rootp->t__DOT__var_8__VforceEn = 0; needsSecondEval = true; } if (topp->cyc == 20) { topp->rootp->t__DOT__var_1__VforceEn = 1; topp->rootp->t__DOT__var_8__VforceEn = 0xff; topp->rootp->t__DOT__var_1__VforceVal = 1; topp->rootp->t__DOT__var_8__VforceVal = 0x5a; needsSecondEval = true; } if (topp->cyc == 22) { topp->rootp->t__DOT__var_1__VforceVal = 0; topp->rootp->t__DOT__var_8__VforceVal = 0xa5; needsSecondEval = true; } if (topp->cyc == 24) { topp->rootp->t__DOT__var_1__VforceEn = 0; topp->rootp->t__DOT__var_8__VforceEn = 0; needsSecondEval = true; } if (needsSecondEval) topp->eval(); } #if VM_TRACE tfp->dump(contextp->time()); #endif contextp->timeInc(5); } if (!contextp->gotFinish()) { vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); } topp->final(); #if VM_TRACE tfp->close(); #endif return 0; } verilator-5.042/test_regress/t/t_var_in_fork.py0000755000542200017500000000077115101701376022272 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=["--binary"]) test.execute() test.passes() verilator-5.042/test_regress/driver.py0000755000542200017500000037322415101701376020506 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # pylint: disable=C0103,C0114,C0115,C0116,C0209,C0302,R0902,R0903,R0904,R0912,R0913,R0914,R0915,R0916,W0212,W0511,W0603,W1201 ###################################################################### import argparse import collections import ctypes import glob import hashlib import json import logging import multiprocessing import os import pickle import platform import pty import re import resource import runpy import shutil import signal import subprocess import sys import time from functools import lru_cache # Eventually use python 3.9's cache from pprint import pformat, pprint from typing import Optional import distro if False: # pylint: disable=using-constant-test pprint(pformat("Ignored")) # Prevent unused warning # Map of all scenarios, with the names used to enable them All_Scenarios = { # yapf: disable 'dist': ['dist'], 'atsim': ['simulator', 'simulator_st', 'atsim'], 'ghdl': ['linter', 'simulator', 'simulator_st', 'ghdl'], 'iv': ['simulator', 'simulator_st', 'iv'], 'ms': ['linter', 'simulator', 'simulator_st', 'ms'], 'nc': ['linter', 'simulator', 'simulator_st', 'nc'], 'vcs': ['linter', 'simulator', 'simulator_st', 'vcs'], 'xrun': ['linter', 'simulator', 'simulator_st', 'xrun'], 'xsim': ['linter', 'simulator', 'simulator_st', 'xsim'], 'vlt': ['linter', 'simulator', 'simulator_st', 'vlt_all', 'vlt'], 'vltmt': ['simulator', 'vlt_all', 'vltmt'], # yapf: enable } # Globals test = None Arg_Tests: list[str] = [] Quitting = False Vltmt_Threads = 3 forker = None Start = None nodist_directory = "../nodist" # So an 'import vltest_bootstrap' inside test files will do nothing sys.modules['vltest_bootstrap'] = {} ####################################################################### ####################################################################### # Decorators class staticproperty(property): def __get__(self, owner_self, owner_cls): return self.fget() ####################################################################### ####################################################################### # VtOs -- OS extensions class VtOs: @staticmethod def delenv(var: str) -> None: """Delete environment variable, if exists""" if var in os.environ: del os.environ[var] @staticmethod def getenv_def(var: str, default=None) -> str: """Return environment variable, returning default if does not exist""" if var in os.environ: return os.environ[var] return default @staticproperty @lru_cache(maxsize=1) def max_procs() -> int: # pylint: disable=no-method-argument """Return maximum processor count can use (system CPUs or numactl setting)""" try: procs = len(os.sched_getaffinity(0)) except AttributeError: procs = multiprocessing.cpu_count() if procs < 2: print("driver.py: Python didn't find at least two CPUs") procs = 2 return procs @staticmethod def mkdir_ok(path: str) -> None: """Make directory, no error if exists""" try: os.mkdir(path) except FileExistsError: pass @staticmethod def run_capture(command: str, check=True) -> str: """Run a command and return results""" proc = subprocess.run([command], capture_output=True, text=True, shell=True, check=False) if check and proc.returncode: sys.exit("%Error: command failed '" + command + "':\n" + proc.stderr + proc.stdout) return str(proc.stdout) @staticmethod def unlink_ok(filename: str) -> None: """Unlink a file, no error if fails""" try: os.unlink(filename) except OSError: pass ####################################################################### ####################################################################### # Capabilities -- What OS/Verilator is built to support class Capabilities: # @lru_cache(maxsize=1024) broken with @staticmethod on older pythons we use _cached_cmake_version = None _cached_cxx_version = None _cached_have_coroutines = None _cached_have_dev_asan = None _cached_have_dev_gcov = None _cached_have_gdb = None _cached_have_sc = None _cached_have_solver = None _cached_make_version = None @staticproperty def cmake_version() -> str: # pylint: disable=no-method-argument if Capabilities._cached_cmake_version is None: out = VtOs.run_capture('cmake --version', check=False) match = re.search(r'cmake version (\d+)\.(\d+)', out, re.IGNORECASE) if match: Capabilities._cached_cmake_version = match.group(1) + "." + match.group(2) else: Capabilities._cached_cmake_version = "none" return Capabilities._cached_cmake_version @staticproperty def cxx_version() -> str: # pylint: disable=no-method-argument if Capabilities._cached_cxx_version is None: Capabilities._cached_cxx_version = VtOs.run_capture( os.environ['MAKE'] + " --silent -C " + os.environ['TEST_REGRESS'] + " -f Makefile print-cxx-version", check=False) return Capabilities._cached_cxx_version @staticproperty def have_coroutines() -> bool: # pylint: disable=no-method-argument if Capabilities._cached_have_coroutines is None: Capabilities._cached_have_coroutines = bool( Capabilities._verilator_get_supported('COROUTINES')) return Capabilities._cached_have_coroutines @staticproperty def have_dev_asan() -> bool: # pylint: disable=no-method-argument if Capabilities._cached_have_dev_asan is None: Capabilities._cached_have_dev_asan = bool( Capabilities._verilator_get_supported('DEV_ASAN')) return Capabilities._cached_have_dev_asan @staticproperty def have_dev_gcov() -> bool: # pylint: disable=no-method-argument if Capabilities._cached_have_dev_gcov is None: Capabilities._cached_have_dev_gcov = bool( Capabilities._verilator_get_supported('DEV_GCOV')) return Capabilities._cached_have_dev_gcov @staticproperty def have_gdb() -> bool: # pylint: disable=no-method-argument if Capabilities._cached_have_gdb is None: out = VtOs.run_capture('gdb --version 2>/dev/null', check=False) Capabilities._cached_have_gdb = bool('Copyright' in out) return Capabilities._cached_have_gdb @staticproperty def have_sc() -> bool: # pylint: disable=no-method-argument if Capabilities._cached_have_sc is None: if 'SYSTEMC' in os.environ: Capabilities._cached_have_sc = True elif 'SYSTEMC_INCLUDE' in os.environ: Capabilities._cached_have_sc = True elif 'CFG_HAVE_SYSTEMC' in os.environ: Capabilities._cached_have_sc = True else: Capabilities._cached_have_sc = bool( Capabilities._verilator_get_supported('SYSTEMC')) return Capabilities._cached_have_sc @staticproperty def have_solver() -> bool: # pylint: disable=no-method-argument if Capabilities._cached_have_solver is None: out = VtOs.run_capture('(z3 --help || cvc5 --help || cvc4 --help) 2>/dev/null', check=False) Capabilities._cached_have_solver = bool('usage' in out.casefold()) return Capabilities._cached_have_solver @staticproperty @lru_cache(maxsize=1024) def make_version() -> str: # pylint: disable=no-method-argument if Capabilities._cached_make_version is None: out = VtOs.run_capture(os.environ['MAKE'] + ' --version', check=False) match = re.search(r'make ([0-9]+\.[0-9]+)', out, flags=re.IGNORECASE) if match: Capabilities._cached_make_version = match.group(1) else: Capabilities._cached_make_version = "none" return Capabilities._cached_make_version # Fetch @staticmethod def warmup_cache() -> None: _ignore = Capabilities.have_coroutines _ignore = Capabilities.have_dev_asan _ignore = Capabilities.have_dev_gcov _ignore = Capabilities.have_gdb _ignore = Capabilities.have_sc _ignore = Capabilities.have_solver # Internals @staticmethod def _verilator_get_supported(feature) -> bool: # Returns if given feature is supported cmd = "perl " + os.environ['VERILATOR_ROOT'] + "/bin/verilator -get-supported " + feature out = VtOs.run_capture(cmd, check=False).strip() if out == '1': return True if out in ('', '0'): return False sys.exit("%Error: couldn't verilator_get_supported: " + cmd + "\n" + out) ####################################################################### ####################################################################### # Forker class - run multprocess pool of processes # Similar interface to Perl's Parallel::Forker. class Forker: class Job: def __init__(self, _id, name, scenario, args, quiet, rerun_skipping, run_pre_start, run_on_start, run_on_finish): self.fail_max_skip = False self.id = _id self.name = name self.scenario = scenario self.args = args self.quiet = quiet self.rerun_skipping = rerun_skipping self.run_pre_start = run_pre_start self.run_on_start = run_on_start self.run_on_finish = run_on_finish self.mprocess = None # Set once call run() @property def pid(self) -> int: return self.mprocess.pid @property def exitcode(self) -> int: return self.mprocess.exitcode def __init__(self, max_processes): self._max_processes = max_processes self._id_next = 0 self._left = collections.deque() # deque of Job self._running = {} # key of pid, value of Job def is_any_left(self) -> bool: return self.num_running() > 0 or (len(self._left) > 0 and not Quitting) def max_proc(self, n: int) -> None: self._max_processes = n def poll(self) -> bool: """Run threads, returning if more work to do (if False, sleep)""" # We don't use SIGCHLD as conflicted with other handler, instead just poll completed = [] # Need two passes to avoid changing the list we are iterating nrunning = 0 more_now = False for process in self._running.values(): if process.exitcode is not None: completed.append(process) more_now = True else: nrunning += 1 # Start new work now, so running in background while we then collect completions while len(self._left) and nrunning < self._max_processes and not Quitting: process = self._left.popleft() self._run(process) nrunning += 1 more_now = True for process in completed: self._finished(process) return more_now def running(self) -> list: return self._running.values() def num_running(self) -> int: return len(self._running) def schedule(self, name, scenario, args, quiet, rerun_skipping, run_pre_start, run_on_start, run_on_finish): # print("-Forker::schedule: [" + name + "]") process = Forker.Job(self._id_next, name=name, scenario=scenario, args=args, quiet=quiet, rerun_skipping=rerun_skipping, run_pre_start=run_pre_start, run_on_start=run_on_start, run_on_finish=run_on_finish) self._id_next += 1 self._left.append(process) def kill_tree_all(self) -> None: # print("-Forker: kill_tree_all") for process in self._running.values(): process.mprocess.kill() def _run(self, process) -> None: # print("-Forker: [" + process.name + "] run_pre_start") process.run_pre_start(process) ctx = multiprocessing.get_context('forkserver') process.mprocess = ctx.Process( # target=forker.child_start, # pylint: disable=used-before-assignment args=(process, )) process.mprocess.start() # print("-Forker: [" + process.name + "] RUNNING pid=" + str(process.pid)) self._running[process.pid] = process @staticmethod def child_start(process) -> None: # Runs in context of child # print("-Forker: [" + process.name + "] run_on_start") process.run_on_start(process) # print("-Forker: [" + process.name + "] FINISHED run_on_start") sys.exit(0) # Don't close anything def _finished(self, process) -> None: del self._running[process.pid] # print("-Forker: [" + process.name + "] run_on_finish exitcode=" + str(process.exitcode)) process.run_on_finish(process) process.mprocess.close() ####################################################################### ####################################################################### # Runner class class Runner: def __init__(self, driver_log_filename, quiet, ok_cnt=0, fail1_cnt=0, skip_cnt=0): self.driver_log_filename = driver_log_filename self.quiet = quiet # Counts self.all_cnt = 0 self.left_cnt = 0 self.ok_cnt = ok_cnt self.fail1_cnt = fail1_cnt self.fail_cnt = 0 self.skip_cnt = skip_cnt self.skip_msgs = [] self.fail_msgs = [] self.fail_tests = [] self._last_proc_finish_time = 0 self._last_summary_time = 0 self._last_summary_left = 0 self._running_ids = {} self._msg_fail_max_skip = False Runner.runner = self def one_test(self, py_filename: str, scenario: str, rerun_skipping=False) -> None: self.all_cnt += 1 self.left_cnt += 1 forker.schedule(name=py_filename, scenario=scenario, args=Args, quiet=self.quiet, rerun_skipping=rerun_skipping, run_pre_start=self._run_pre_start_static, run_on_start=self._run_on_start_static, run_on_finish=self._run_on_finish_static) @staticmethod def _run_pre_start_static(process) -> None: Runner.runner._run_pre_start(process) # pylint: disable=protected-access def _run_pre_start(self, process) -> None: # Running in context of parent, before run_on_start # Make an identifier that is unique across all current running jobs i = 1 while i in self._running_ids: i += 1 process.running_id = i self._running_ids[process.running_id] = 1 if Args.fail_max and Args.fail_max <= self.fail_cnt: if not self._msg_fail_max_skip: self._msg_fail_max_skip = True print("== Too many test failures; exceeded --fail-max\n", file=sys.stderr) process.fail_max_skip = 1 @staticmethod def _run_on_start_static(process) -> None: # Running in context of child, so can't pass data to parent directly if process.quiet: sys.stdout = open(os.devnull, 'w') # pylint: disable=R1732,unspecified-encoding sys.stderr = open(os.devnull, 'w') # pylint: disable=R1732,unspecified-encoding print("=" * 70) global Args Args = process.args global test test = VlTest(py_filename=process.name, scenario=process.scenario, running_id=process.running_id) test.oprint("=" * 50) test._prep() if process.rerun_skipping: print(" ---------- Earlier logfiles below; test was rerunnable = False\n") os.system("cat " + test.obj_dir + "/*.log") print(" ---------- Earlier logfiles above; test was rerunnable = False\n") elif process.fail_max_skip: test.skip("Too many test failures; exceeded --fail-max") else: VtOs.unlink_ok(test._status_filename) test._read() # Don't put anything other than _exit after _read, # as may call _exit via another path test._exit() @staticmethod def _run_on_finish_static(process) -> None: Runner.runner._run_on_finish(process) # pylint: disable=protected-access def _run_on_finish(self, process) -> None: # Running in context of parent global test test = VlTest(py_filename=process.name, scenario=process.scenario, running_id=process.running_id) test._quit = Quitting test._read_status() if test.ok: self.ok_cnt += 1 if Args.driver_clean: test.clean() elif test._quit: pass elif test._scenario_off and not test.errors: pass elif test._skips and not test.errors and not test.errors_keep_going: self.skip_msgs.append("\t#" + test.soprint("-Skip: " + test._skips)) self.skip_cnt += 1 else: error_msg = test.errors if test.errors else test.errors_keep_going test.oprint("FAILED: " + error_msg) makecmd = VtOs.getenv_def('VERILATOR_MAKE', os.environ['MAKE'] + " &&") upperdir = 'test_regress/' if re.search(r'test_regress', os.getcwd()) else '' self.fail_msgs.append("\t#" + test.soprint("%Error: " + error_msg) + "\t\t" + makecmd + " " + upperdir + test.py_filename + ' ' + ' '.join(self._manual_args()) + " --" + test.scenario + "\n") self.fail_tests.append(test) self.fail_cnt += 1 self.report(self.driver_log_filename) other = "" for proc in forker.running(): other += " " + proc.name if other != "" and not Args.quiet: test.oprint("Simultaneous running tests:" + other) if Args.stop: sys.exit("%Error: --stop and errors found\n") self.left_cnt -= 1 self._last_proc_finish_time = time.time() if process.running_id: del self._running_ids[process.running_id] def wait_and_report(self) -> None: self.print_summary(force=True) # Wait for all children to finish while forker.is_any_left(): more_now = forker.poll() if not Args.interactive_debugger: self.print_summary(force=False) if not more_now: time.sleep(0.1) self.report(None) self.report(self.driver_log_filename) def report(self, filename: str) -> None: if filename: with open(filename, "w", encoding="utf8") as fh: self._report_fh(fh) else: self._report_fh(sys.stdout) def _report_fh(self, fh) -> None: fh.write("\n") fh.write('=' * 70 + "\n") for f in sorted(self.fail_msgs): fh.write(f.strip() + "\n") for f in sorted(self.skip_msgs): fh.write(f.strip() + "\n") if self.fail_cnt: sumtxt = 'FAILED' elif self.skip_cnt: sumtxt = 'PASSED w/SKIPS' else: sumtxt = 'PASSED' fh.write("==TESTS DONE, " + sumtxt + ": " + self.sprint_summary() + "\n") def print_summary(self, force=False): change = self._last_summary_left != self.left_cnt if (force or ((time.time() - self._last_summary_time) >= 15) or (not self.quiet and change)): self._last_summary_left = self.left_cnt self._last_summary_time = time.time() print("==SUMMARY: " + self.sprint_summary(), file=sys.stderr) if (self._last_proc_finish_time != 0 and ((time.time() - self._last_proc_finish_time) > 15)): self._last_proc_finish_time = time.time() other = "" for proc in forker.running(): other += " " + proc.name print("==STILL RUNNING:" + other, file=sys.stderr) @staticmethod def _py_filename_adjust(py_filename: str, tdir_def: str) -> tuple[str, str]: # Return (py_filename, t_dir) for tdir in Args.test_dirs: # pylint: disable=redefined-outer-name # t_dir used both absolutely and under obj_dir try_py_filename = tdir + "/" + os.path.basename(py_filename) if os.path.exists(try_py_filename): # Note most tests require error messages of the form t/x.v # Therefore py_filename must be t/ for local tests # t_dir must be absolute - used under t or under obj_dir tdir_abs = os.path.abspath(tdir) return (try_py_filename, tdir_abs) return (py_filename, os.path.abspath(tdir_def)) def sprint_summary(self) -> str: delta = time.time() - Start # pylint: disable=used-before-assignment # Fudge of 120% works out about right so ETA correctly predicts completion time eta = 1.2 * ((self.all_cnt * (delta / ((self.all_cnt - self.left_cnt) + 0.001))) - delta) if delta < 10: eta = 0 out = "" if self.left_cnt: out += "Left " + str(self.left_cnt) + " " out += "Passed " + str(self.ok_cnt) # Ordered below most severe to least severe out += " Failed " + str(self.fail_cnt) if self.fail1_cnt: out += " Failed-First " + str(self.fail1_cnt) if self.skip_cnt: out += " Skipped " + str(self.skip_cnt) if forker.num_running(): out += " Running " + str(forker.num_running()) if self.left_cnt > 10 and eta > 10 and self.all_cnt != self.left_cnt: out += " Eta %d:%02d" % (int(eta / 60), eta % 60) out += " Time %d:%02d" % (int(delta / 60), delta % 60) return out def _manual_args(self) -> list[str]: # Return command line with scenarios stripped out = [] for oarg in Args.orig_argv_sw: showarg = True for val in All_Scenarios.values(): for allscarg in val: if oarg == "--" + allscarg: showarg = False # Also strip certain flags that per-test debugging won't want if showarg and oarg != '--rerun' and oarg != '--quiet': out.append(oarg) return out ####################################################################### ####################################################################### # Test exceptions class VtSkipException(Exception): pass class VtErrorException(Exception): pass ####################################################################### ####################################################################### # Test class class VlTest: _file_contents_cache = {} # @lru_cache(maxsize=1024) broken with @staticmethod on older pythons we use _cached_aslr_off = None _cached_cfg_with_ccache = None def __init__(self, py_filename, scenario, running_id): self.py_filename = py_filename # Name of .py file to get setup from self.running_id = running_id self.scenario = scenario self.root = '..' # Relative path to git root (above test_regress) self._force_pass = False self._have_solver_called = False self._inputs = {} self._ok = False self._quit = False self._scenario_off = False # scenarios() didn't match running scenario self._skips = None match = re.match(r'^(.*/)?([^/]*)\.py', self.py_filename) self.name = match.group(2) # Name of this test self.benchmark = Args.benchmark self.benchmarksim = False self.clean_command = None self.context_threads = 0 # Number of threads to allocate in the context self.errors = None self.errors_keep_going = None self.main_time_multiplier = 1 self.make_main = 1 # Make __main.cpp self.make_pli = 0 # need to compile pli self.make_top_shell = 1 # Make a default __top.v file self.rerunnable = True # Rerun if fails self.sc_time_resolution = "SC_PS" # Keep - PS is SystemC default self.sim_time = 1100 # simulation time units for main wrapper self.threads = -1 # --threads (negative means auto based on scenario) self.verbose = Args.verbose self.verilated_randReset = "" self.vm_prefix = "V" + self.name # Make e.g. self.vlt, self.vltmt etc self.vlt = False # Set below also self.vltmt = False # Set below also self.xsim = False # Set below also for ascenario in All_Scenarios: self.__dict__[ascenario] = False self.__dict__[scenario] = True self.vlt_all = self.vlt or self.vltmt # Any Verilator scenario (self.py_filename, self.t_dir) = Runner._py_filename_adjust(self.py_filename, ".") for tdir in Args.test_dirs: # pylint: disable=redefined-outer-name # t_dir used both absolutely and under obj_dir self.t_dir = None if os.path.exists(tdir + "/" + self.name + ".py"): # Note most tests require error messages of the form t/x.v # Therefore py_filename must be t/ for local tests self.py_filename = os.path.relpath(tdir + "/" + self.name + ".py") # t_dir must be absolute - used under t or under obj_dir self.t_dir = os.path.abspath(tdir) break if not self.t_dir: sys.exit("%Error: Can't locate dir for " + self.name) scen_dir = os.path.relpath(self.t_dir + "/../obj_" + self.scenario) # Simplify filenames on local runs scen_dir = re.sub(r'^t/\.\./', '', scen_dir) # Not mkpath so error if try to build somewhere odd VtOs.mkdir_ok(scen_dir) self.obj_dir = scen_dir + "/" + self.name + Args.obj_suffix define_opt = self._define_opt_calc() # All compilers self.v_flags = [] if self.xsim: self.v_flags += ["-f input.xsim.vc"] elif os.path.exists('input.vc'): self.v_flags += ["-f input.vc"] if not re.search(r'/test_regress', self.t_dir): # Don't include standard dir, only site's self.v_flags += ["+incdir+" + self.t_dir + " -y " + self.t_dir] self.v_flags += [define_opt + "TEST_OBJ_DIR=" + self.obj_dir] if Args.verbose: self.v_flags += [define_opt + "TEST_VERBOSE=1"] if Args.benchmark: self.v_flags += [define_opt + "TEST_BENCHMARK=Args.benchmark"] if Args.trace: self.v_flags += [define_opt + "WAVES=1"] self.v_flags2 = [] # Overridden in some sim files self.v_other_filenames = [] self.all_run_flags = [] self.pli_flags = [ "-I" + os.environ['VERILATOR_ROOT'] + "/include/vltstd", "-I" + os.environ['VERILATOR_ROOT'] + "/include", "-fPIC", "-shared" ] if platform.system() == 'Darwin': self.pli_flags += ["-Wl,-undefined,dynamic_lookup"] else: self.pli_flags += ["-rdynamic"] if Args.verbose: self.pli_flags += ["-DTEST_VERBOSE=1"] self.pli_flags += ["-o", self.obj_dir + "/libvpi.so"] self.tool_c_flags = [] # ATSIM self.atsim_define = 'ATSIM' self.atsim_flags = [ "-c", "+sv", "+define+ATSIM", ("+sv_dir+" + self.obj_dir + "/.athdl_compile") ] self.atsim_flags2 = [] # Overridden in some sim files self.atsim_run_flags = [] # GHDL self.ghdl_define = 'GHDL' self.ghdl_work_dir = self.obj_dir + "/ghdl_compile" self.ghdl_flags = [("-v" if Args.debug else ""), ("--workdir=" + self.obj_dir + "/ghdl_compile")] self.ghdl_flags2 = [] # Overridden in some sim files self.ghdl_run_flags = [] # IV self.iv_define = 'IVERILOG' self.iv_flags = ["+define+IVERILOG", "-g2012", ("-o" + self.obj_dir + "/simiv")] self.iv_flags2 = [] # Overridden in some sim files self.iv_run_flags = [] # VCS self.vcs_define = 'VCS' self.vcs_flags = [ "+vcs+lic+wait", "+cli", "-debug_access", "+define+VCS+1", "-q", "-sverilog", "-CFLAGS", "'-DVCS'" ] self.vcs_flags2 = [] # Overridden in some sim files self.vcs_run_flags = ["+vcs+lic_wait"] # NC self.nc_define = 'NC' self.nc_flags = [ "+licqueue", "+nowarn+LIBNOU", "+define+NC=1", "-q", "+assert", "+sv", "-c", "-xmlibdirname", (self.obj_dir + "/xcelium.d"), ("+access+r" if Args.trace else "") ] self.nc_flags2 = [] # Overridden in some sim files self.nc_run_flags = [ "+licqueue", "-q", "+assert", "+sv", "-R", "-covoverwrite", "-xmlibdirname", (self.obj_dir + "/xcelium.d"), ] # ModelSim self.ms_define = 'MS' self.ms_flags = [ "-sv", "-work", (self.obj_dir + "/work"), "+define+MS=1", "-ccflags", '\"-DMS=1\"' ] self.ms_flags2 = [] # Overridden in some sim files self.ms_run_flags = ["-lib", self.obj_dir + "/work", "-c", "-do", "'run -all;quit'"] # XSim self.xsim_define = 'XSIM' self.xsim_flags = [ "--nolog", "--sv", "--define", "XSIM", "--work", (self.name + "=" + self.obj_dir + "/xsim") ] self.xsim_flags2 = [] # Overridden in some sim files self.xsim_run_flags = [ "--nolog", "--runall", "--lib", (self.name + "=" + self.obj_dir + "/xsim"), (" --debug all" if Args.trace else "") ] self.xsim_run_flags2 = [] # Overridden in some sim files # Xcelium (xrun) self.xrun_define = 'XRUN' self.xrun_flags = [] # Doesn't really have a compile step self.xrun_flags2 = [] # Overridden in some sim files self.xrun_run_flags = [ "-64", "-access", "+rwc", "-newsv", "-sv", "-xmlibdirname", self.obj_dir + "/work", "-l", self.obj_dir + "/history", "-quiet", "-plinowarn" ] # Verilator self.verilator_define = 'VERILATOR' self.verilator_flags = [ "-cc", "-Mdir", self.obj_dir, "--fdedup", # As currently disabled unless -O3 "--debug-check", "--comp-limit-members", "10" ] self.verilator_flags2 = [] self.verilator_flags3 = [] self.verilator_make_gmake = True self.verilator_make_cmake = False self.verilated_debug = Args.verilated_debug self._status_filename = self.obj_dir + "/V" + self.name + ".status" self.coverage_filename = self.obj_dir + "/coverage.dat" self.golden_filename = re.sub(r'\.py$', '.out', self.py_filename) self.main_filename = self.obj_dir + "/" + self.vm_prefix + "__main.cpp" self.compile_log_filename = self.obj_dir + "/vlt_compile.log" self.run_log_filename = self.obj_dir + "/vlt_sim.log" self.stats = self.obj_dir + "/V" + self.name + "__stats.txt" if Args.top_filename: self.top_filename = Args.top_filename else: self.top_filename = re.sub(r'\.py$', '', self.py_filename) + '.' + self.v_suffix self.pli_filename = re.sub(r'\.py$', '', self.py_filename) + '.cpp' self.top_shell_filename = self.obj_dir + "/" + self.vm_prefix + "__top.v" def _define_opt_calc(self) -> str: return "--define " if self.xsim else "+define+" def init_benchmarksim(self) -> None: # Simulations with benchmarksim enabled append to the same file between runs. # Test files must ensure a clean benchmark data file before executing tests. filename = self.benchmarksim_filename with open(filename, 'w', encoding="utf8") as fh: fh.write("# Verilator simulation benchmark data\n") fh.write("# Test name: " + self.name + "\n") fh.write("# Top file: " + self.top_filename + "\n") fh.write("evals, time[s]\n") def soprint(self, message: str) -> str: message = message.rstrip() + "\n" message = self.scenario + "/" + self.name + ": " + message return message def oprint(self, message: str) -> None: message = message.rstrip() + "\n" print(self.soprint(message), end="") def error(self, message: str) -> None: """Called from tests as: error("Reason message") Newline is optional. Only first line is passed to summaries Throws a VtErrorException, so rest of testing is not executed""" if self._force_pass: return message = message.rstrip() + "\n" print("%Warning: " + self.scenario + "/" + self.name + ": " + message, file=sys.stderr, end="") if not self.errors: message = re.sub(r'\n.*', '\n', message) self.errors = message raise VtErrorException def error_keep_going(self, message: str) -> None: """Called from tests as: error_keep_going("Reason message") Newline is optional. Only first line is passed to summaries""" if self._quit or self._force_pass: return message = message.rstrip() + "\n" print("%Warning: " + self.scenario + "/" + self.name + ": " + message, file=sys.stderr, end="") if not self.errors_keep_going: message = re.sub(r'\n.*', '\n', message) self.errors_keep_going = message def skip(self, message: str) -> None: """Called from tests as: skip("Reason message"[, ...]) Newline is optional. Only first line is passed to summaries. Throws a VtSkipException, so rest of testing is not executed""" message = message.rstrip() + "\n" print("-Skip: " + self.scenario + "/" + self.name + ": " + message, file=sys.stderr, end="") if not self._skips: message = re.sub(r'\n.*', '\n', message) self._skips = message raise VtSkipException def scenarios(self, *scenario_list) -> None: """Called from tests as: scenarios() to specify which scenarios this test runs under. Where ... is one cases listed in All_Scenarios. All scenarios must be on one line; this is parsed outside Python.""" enabled_scenarios = {} for param in scenario_list: hit = False for allsc, allscs in All_Scenarios.items(): for allscarg in allscs: if param == allscarg: hit = True enabled_scenarios[allsc] = True if not hit: self.error("scenarios(...) has unknown scenario '" + param + "'") if not enabled_scenarios.get(self.scenario, None): self._scenario_off = True self.skip("scenario '" + self.scenario + "' not enabled for test") # self._exit() implied by skip's exception @staticmethod def _prefilter_scenario(py_filename: str, scenario: str) -> bool: """Read a python file to see if scenarios require it to be run. Much faster than parsing the file for a runtime check.""" (py_filename, _) = Runner._py_filename_adjust(py_filename, ".") with open(py_filename, 'r', encoding="utf-8") as fh: for line in fh: m = re.search(r'^\s*test.scenarios\((.*?)\)', line) if m: for param in re.findall(r"""["']([^,]*)["']""", m.group(1)): for allscarg in All_Scenarios[scenario]: if param == allscarg: return True return False def _prep(self) -> None: VtOs.mkdir_ok(self.obj_dir) # Ok if already exists def _read(self) -> None: if not os.path.exists(self.py_filename): self.error("Can't open " + self.py_filename) return global test test = self sys.path.append(self.t_dir) # To find vltest_bootstrap.py # print("_read/exec py_filename=" + self.py_filename) # print("_read/exec dir=", ' '.join(dir())) # print("_read/exec vars=", ' '.join(vars().keys())) # print("_read/exec globals=", ' '.join(globals().keys())) # print("_read/exec locals=", ' '.join(locals().keys())) try: runpy.run_path(self.py_filename, globals()) except (VtErrorException, VtSkipException): pass def _exit(self): if self.ok: self.oprint("Self PASSED") elif self._skips and not self.errors: self.oprint("-Skip: " + self._skips) else: # If no worse errors, promote errors_keep_going to normal errors if not self.errors and self.errors_keep_going: self.errors = self.errors_keep_going if not self.errors: self.error("Missing ok") self.oprint("%Error: " + self.errors) self._write_status() sys.exit(0) def _write_status(self) -> None: with open(self._status_filename, "wb") as fh: pass_to_driver = { '_ok': self._ok, '_scenario_off': self._scenario_off, '_skips': self._skips, 'errors': self.errors, } pickle.dump(pass_to_driver, fh) def _read_status(self) -> None: filename = self._status_filename if not os.path.isfile(filename): self.error_keep_going("Child test did not return status (test has Python error?): " + self.py_filename) return with open(filename, "rb") as fh: dic = pickle.load(fh) for k in dic.keys(): # print("_read_status " + filename + ".test['" + k + "]=" + pformat(dic[k])) setattr(self, k, dic[k]) #---------------------------------------------------------------------- # Methods invoked by tests def clean(self, for_rerun=False) -> None: """Called on a --driver-clean or rerun to cleanup files.""" if self.clean_command: os.system(self.clean_command) os.system('/bin/rm -rf ' + self.obj_dir + '__fail1') if for_rerun: # Prevents false-failures when switching compilers # Remove old results to force hard rebuild os.system('/bin/mv ' + self.obj_dir + ' ' + self.obj_dir + '__fail1') else: os.system('/bin/rm -rf ' + self.obj_dir) def clean_objs(self) -> None: os.system("/bin/rm -rf " + ' '.join(glob.glob(self.obj_dir + "/*"))) def _checkflags(self, param): checkflags = ( ' ' + ' '.join(param['v_flags']) + # ' ' + ' '.join(param['v_flags2']) + # ' ' + ' '.join(param['verilator_flags']) + # ' ' + ' '.join(param['verilator_flags2']) + # ' ' + ' '.join(param['verilator_flags3']) + ' ') return checkflags def compile_vlt_cmd(self, **kwargs) -> list: """Return default command list to run verilator""" param = {'stdout_filename': None} param.update(vars(self)) param.update(kwargs) vlt_cmd = [ "perl", os.environ["VERILATOR_ROOT"] + "/bin/verilator", *self._compile_vlt_flags(**param), param['top_filename'], *param['v_other_filenames'] ] if param['stdout_filename']: vlt_cmd += ["> " + param['stdout_filename']] return vlt_cmd def _compile_vlt_flags(self, **param) -> list: checkflags = self._checkflags(param) d_verilator_flags = ' ' + ' '.join(self.driver_verilator_flags) + ' ' self.pins_sc_uint_bool = ( # pylint: disable=attribute-defined-outside-init bool( re.search(r'-pins-sc-uint-bool\b', checkflags) or re.search(r'-pins-sc-uint-bool\b', d_verilator_flags))) self.savable = ( # pylint: disable=attribute-defined-outside-init bool(re.search(r'-savable\b', checkflags))) self.coverage = ( # pylint: disable=attribute-defined-outside-init bool(re.search(r'-coverage\b', checkflags))) self.sc = ( # pylint: disable=attribute-defined-outside-init bool(re.search(r'-sc\b', checkflags))) self.timing = ( # pylint: disable=attribute-defined-outside-init bool(re.search(r'( -?-timing\b| -?-binary\b)', checkflags))) self.trace = ( # pylint: disable=attribute-defined-outside-init bool(Args.trace or re.search(r'-trace\b|-trace-fst\b', checkflags))) if re.search(r'-trace-fst', checkflags): if self.sc: self.trace_format = 'fst-sc' # pylint: disable=attribute-defined-outside-init else: self.trace_format = 'fst-c' # pylint: disable=attribute-defined-outside-init elif re.search(r'-trace-saif', checkflags): if self.sc: self.trace_format = 'saif-sc' # pylint: disable=attribute-defined-outside-init else: self.trace_format = 'saif-c' # pylint: disable=attribute-defined-outside-init elif self.sc: self.trace_format = 'vcd-sc' # pylint: disable=attribute-defined-outside-init else: self.trace_format = 'vcd-c' # pylint: disable=attribute-defined-outside-init if param.get('benchmarksim', None): self.benchmarksim = True # pylint: disable=attribute-defined-outside-init verilator_flags = [*param.get('verilator_flags', "")] if Args.gdb: verilator_flags += ["--gdb"] if Args.gdbbt: verilator_flags += ["--gdbbt"] if Args.rr: verilator_flags += ["--rr"] if Args.trace: verilator_flags += ["--trace-vcd"] if Args.gdbsim or Args.rrsim: verilator_flags += ["-CFLAGS -ggdb -LDFLAGS -ggdb"] verilator_flags += ["--x-assign unique"] # More likely to be buggy if param['vltmt']: verilator_flags += ["--debug-partition"] if param['threads'] >= 0: verilator_flags += ["--threads", str(param['threads'])] if param['vltmt'] and re.search(r'-trace-fst ', checkflags): verilator_flags += ["--trace-threads 2"] if param['make_main'] and param['verilator_make_gmake']: verilator_flags += ["--exe"] if param['make_main'] and param['verilator_make_gmake']: verilator_flags += ["../" + self.main_filename] cmdargs = [ "--prefix", param['vm_prefix'], *verilator_flags, *param['verilator_flags2'], *param['verilator_flags3'], *param['v_flags'], *param['v_flags2'], # Flags from driver cmdline override default flags and # flags from the test itself *self.driver_verilator_flags, ] return cmdargs def lint(self, **kwargs) -> None: """Run a linter. Arguments similar to run(); default arguments are from self""" param = {} param.update(vars(self)) param.update({ # Lint-specific default overrides 'make_main': False, 'make_top_shell': False, 'verilator_flags2': ["--lint-only"], 'verilator_make_gmake': False }) param.update(kwargs) self.compile(**param) def compile(self, **kwargs) -> None: """Run simulation compiler. Arguments similar to run(); default arguments are from self""" param = { 'expect_filename': None, 'fails': False, 'make_flags': [], 'tee': True, 'timing_loop': False, } param.update(vars(self)) param.update(kwargs) if self.verbose: self.oprint("Compile") if param['vlt'] and param['threads'] > 1: self.error("'threads =' argument must be <= 1 for vlt scenario") # Compute automatic parameter values checkflags = self._checkflags(param) if re.search(r'(^|\s)-?-threads\s', checkflags): self.error("Specify threads via 'threads=' argument, not as a command line option") if param['threads'] < 0 and param['vltmt']: param['threads'] = calc_threads(Vltmt_Threads) if not param['context_threads']: param['context_threads'] = param['threads'] if (param['threads'] >= 1) else 1 if re.search(r'( -?-main\b| -?-binary\b)', checkflags): param['make_main'] = False if re.search(r'( -?-build\b| -?-binary\b)', checkflags): param['verilator_make_cmake'] = False param['verilator_make_gmake'] = False self.threads = param['threads'] self.context_threads = param['context_threads'] self.compile_vlt_cmd(**param) if not re.search(r'TEST_DUMPFILE', ' '.join(self.v_flags)): self.v_flags += [self._define_opt_calc() + "TEST_DUMPFILE=" + self.trace_filename] if not param['make_top_shell']: self.top_shell_filename = "" else: self.top_shell_filename = self.obj_dir + "/" + self.vm_prefix + "__top." + self.v_suffix param['top_shell_filename'] = self.top_shell_filename if param['atsim']: tool_define = param['atsim_define'] self._make_top(param['make_top_shell']) self.run(logfile=self.obj_dir + "/atsim_compile.log", fails=param['fails'], cmd=[ VtOs.getenv_def('VERILATOR_ATSIM', "atsim"), ' '.join(param['atsim_flags']), ' '.join(param['atsim_flags2']), ' '.join(param['v_flags']), ' '.join(param['v_flags2']), param['top_filename'], param['top_shell_filename'], ' '.join(param['v_other_filenames']), ]) elif param['ghdl']: tool_define = param['ghdl_define'] VtOs.mkdir_ok(self.ghdl_work_dir) self._make_top(param['make_top_shell']) tool_exe = VtOs.getenv_def('VERILATOR_GHDL', "ghdl") self.run( logfile=self.obj_dir + "/ghdl_compile.log", fails=param['fails'], cmd=[ tool_exe, # Add -c here, as having -c twice freaks it out ("" if re.search(r' -c\b', tool_exe) else "-c"), ' '.join(param['ghdl_flags']), ' '.join(param['ghdl_flags2']), #' '.join(param['v_flags']), # Not supported #' '.join(param['v_flags2']), # Not supported param['top_filename'], param['top_shell_filename'], ' '.join(param['v_other_filenames']), "-e t", ]) elif param['vcs']: tool_define = param['vcs_define'] self._make_top(param['make_top_shell']) self.run(logfile=self.obj_dir + "/vcs_compile.log", fails=param['fails'], cmd=[ VtOs.getenv_def('VERILATOR_VCS', "vcs"), ' '.join(param['vcs_flags']), ' '.join(param['vcs_flags2']), ("-CFLAGS -DTEST_VERBOSE=1" if Args.verbose else ""), ' '.join(param['v_flags']), ' '.join(param['v_flags2']), param['top_filename'], param['top_shell_filename'], ' '.join(param['v_other_filenames']), ]) elif param['nc']: tool_define = param['nc_define'] self._make_top(param['make_top_shell']) self.run(logfile=self.obj_dir + "/nc_compile.log", fails=param['fails'], cmd=[ VtOs.getenv_def('VERILATOR_NCVERILOG', "ncverilog"), ' '.join(param['nc_flags']), ' '.join(param['nc_flags2']), ' '.join(param['v_flags']), ' '.join(param['v_flags2']), param['top_filename'], param['top_shell_filename'], ' '.join(param['v_other_filenames']), ]) elif param['ms']: tool_define = param['ms_define'] self._make_top(param['make_top_shell']) self.run(logfile=self.obj_dir + "/ms_compile.log", fails=param['fails'], cmd=[ ("vlib " + self.obj_dir + "/work && "), VtOs.getenv_def('VERILATOR_MODELSIM', "vlog"), ' '.join(param['ms_flags']), ' '.join(param['ms_flags2']), ' '.join(param['v_flags']), ' '.join(param['v_flags2']), param['top_filename'], param['top_shell_filename'], ]) elif param['iv']: tool_define = param['iv_define'] self._make_top(param['make_top_shell']) cmd = (VtOs.getenv_def('VERILATOR_IVERILOG', "iverilog"), ' '.join(param['iv_flags']), ' '.join(param['iv_flags2']), ' '.join(param['v_flags']), ' '.join(param['v_flags2']), param['top_filename'], param['top_shell_filename'], ' '.join(param['v_other_filenames'])) cmd = list(map(lambda str: re.sub(r'\+define\+', '-D ', str), cmd)) self.run(logfile=self.obj_dir + "/iv_compile.log", fails=param['fails'], cmd=cmd) elif param['xrun']: tool_define = param['xrun_define'] self._make_top(param['make_top_shell']) elif param['xsim']: tool_define = param['xsim_define'] self._make_top(param['make_top_shell']) self.run(logfile=self.obj_dir + "/xsim_compile.log", fails=param['fails'], cmd=[ VtOs.getenv_def('VERILATOR_XVLOG', "xvlog"), ' '.join(param['xsim_flags']), ' '.join(param['xsim_flags2']), ' '.join(param['v_flags']), ' '.join(param['v_flags2']), param['top_filename'], param['top_shell_filename'], ]) elif param['vlt_all']: tool_define = param['verilator_define'] if self.sc and not self.have_sc: self.skip("Test requires SystemC; ignore error since not installed\n") return if self.timing and not self.have_coroutines: self.skip("Test requires Coroutines; ignore error since not available\n") return if self.timing and self.sc and re.search(r'Ubuntu 24.04', distro.name( pretty=True)) and re.search(r'clang', self.cxx_version): self.skip( "Test requires SystemC and Coroutines; broken on Ubuntu 24.04 w/clang\n" + " OS=" + distro.name(pretty=True) + " CXX=" + self.cxx_version) return if param['verilator_make_cmake'] and not self.have_cmake: self.skip( "Test requires CMake; ignore error since not available or version too old\n") return if not param['fails'] and param['make_main']: self._make_main(param['timing_loop']) if (param['verilator_make_gmake'] or (not param['verilator_make_gmake'] and not param['verilator_make_cmake'])): vlt_cmd = self.compile_vlt_cmd(**param) if self.verbose: self.oprint("Running Verilator (gmake)") if Args.verilation: self.run(logfile=self.obj_dir + "/vlt_compile.log", fails=param['fails'], tee=param['tee'], expect_filename=param['expect_filename'], verilator_run=True, cmd=vlt_cmd) if param['verilator_make_cmake']: vlt_args = self._compile_vlt_flags(**param) if self.verbose: self.oprint("Running cmake") VtOs.mkdir_ok(self.obj_dir) csources = [] if param['make_main']: csources.append(self.main_filename) self.run( logfile=self.obj_dir + "/vlt_cmake.log", fails=param['fails'], tee=param['tee'], expect_filename=param['expect_filename'], verilator_run=True, cmd=[ "cd \"" + self.obj_dir + "\" && cmake", "\"" + self.t_dir + "/..\"", "-DTEST_VERILATOR_ROOT=" + os.environ['VERILATOR_ROOT'], "-DTEST_NAME=" + self.name, "-DTEST_CSOURCES=\"" + ' '.join(csources) + "\"", "-DTEST_VERILATOR_ARGS=\"" + ' '.join(vlt_args) + "\"", "-DTEST_VERILATOR_SOURCES=\"" + param['top_filename'] + ' ' + ' '.join(param['v_other_filenames']) + "\"", "-DTEST_VERBOSE=\"" + ("1" if self.verbose else "0") + "\"", "-DTEST_SYSTEMC=\"" + ("1" if self.sc else "0") + "\"", "-DCMAKE_PREFIX_PATH=\"" + (VtOs.getenv_def('SYSTEMC_INCLUDE', VtOs.getenv_def('SYSTEMC', '')) + "/..\""), "-DTEST_OPT_FAST=\"" + ("-Os" if param['benchmark'] else "-O0") + "\"", "-DTEST_OPT_GLOBAL=\"" + ("-Os" if param['benchmark'] else "-O0") + "\"", "-DTEST_VERILATION=\"" + ("1" if Args.verilation else "0") + "\"", ]) if not param['fails'] and param['verilator_make_gmake']: if self.verbose: self.oprint("Running make (gmake)") self.run( logfile=self.obj_dir + "/vlt_gcc.log", entering=self.obj_dir, cmd=[ os.environ['MAKE'], (("-j " + str(Args.driver_build_jobs)) if Args.driver_build_jobs else ""), "-C " + self.obj_dir, "-f " + os.path.abspath(os.path.dirname(__file__)) + "/Makefile_obj", ("" if self.verbose else "--no-print-directory"), "VM_PREFIX=" + self.vm_prefix, "TEST_OBJ_DIR=" + self.obj_dir, "CPPFLAGS_DRIVER=-D" + self.name.upper(), ("CPPFLAGS_DRIVER2=-DTEST_VERBOSE=1" if self.verbose else ""), ("" if param['benchmark'] else "OPT_FAST=-O0"), ("" if param['benchmark'] else "OPT_GLOBAL=-O0"), self.vm_prefix, # bypass default rule, as we don't need archive *param['make_flags'], ]) if not param['fails'] and param['verilator_make_cmake']: if self.verbose: self.oprint("Running cmake --build") self.run(logfile=self.obj_dir + "/vlt_cmake_build.log", cmd=[ "cmake", "--build", self.obj_dir, ("--verbose" if self.verbose else ""), ]) else: self.error("No compile step defined for '%s' scenario" % self.scenario) if param['make_pli']: if self.verbose: self.oprint("Compile vpi") cmd = [ os.environ['CXX'], *param['pli_flags'], "-D" + tool_define, "-DIS_VPI", VtOs.getenv_def('CFLAGS', ''), self.pli_filename ] self.run(logfile=self.obj_dir + "/pli_compile.log", fails=param['fails'], cmd=cmd) def timeout(self, seconds): """Limit the CPU time of the test - this limit is inherited by all of the spawned child processess""" # An unprivileged process may set only its soft limit # to a value in the range from 0 up to the hard limit _, hardlimit = resource.getrlimit(resource.RLIMIT_CPU) softlimit = ctypes.c_long(min(seconds, ctypes.c_ulong(hardlimit).value)).value # Casting is required due to a quirk in Python, # rlimit values are interpreted as LONG, instead of ULONG # https://github.com/python/cpython/issues/137044 rlimit = (softlimit, hardlimit) resource.setrlimit(resource.RLIMIT_CPU, rlimit) def leak_check_disable(self): """Disable memory leak detection when leaks are expected, e.g.: on early abnormal termination""" asan_options = os.environ.get("ASAN_OPTIONS", "") self.setenv("ASAN_OPTIONS", asan_options + ":detect_leaks=0") def execute(self, **kwargs) -> None: """Run simulation executable. Arguments similar to run(); default arguments are from self""" # Default arguments are from self # params may be expect or {tool}_expect param = { 'aslr_off': False, 'entering': False, 'check_finished': False, 'executable': None, 'expect_filename': None, 'fails': False, 'run_env': '', 'tee': True, 'use_libvpi': False } param.update(vars(self)) param.update(kwargs) if self.verbose: self.oprint("Run") if not self.verbose: os.environ['SYSTEMC_DISABLE_COPYRIGHT_MESSAGE'] = 'DISABLE' else: VtOs.delenv('SYSTEMC_DISABLE_COPYRIGHT_MESSAGE') if not self._have_solver_called: os.environ['VERILATOR_SOLVER'] = "test.py-file-needs-have_solver()-call" if param['check_finished'] is None and not param['fails']: param['check_finished'] = 1 run_env = param['run_env'] if run_env: run_env = run_env + ' ' if param['atsim']: cmd = [ "echo q | " + run_env + self.obj_dir + "/athdl_sv", ' '.join(param['atsim_run_flags']), ' '.join(param['all_run_flags']) ] self.run(cmd=cmd, check_finished=param['check_finished'], entering=param['entering'], expect_filename=param.get('atsim_run_expect_filename', None), fails=param['fails'], logfile=param.get('logfile', self.obj_dir + "/atsim_sim.log"), tee=param['tee']) elif param['ghdl']: cmd = [ run_env + self.obj_dir + "/simghdl", ' '.join(param['ghdl_run_flags']), ' '.join(param['all_run_flags']) ] self.run(cmd=cmd, check_finished=param['check_finished'], entering=param['entering'], expect_filename=param.get('ghdl_run_expect_filename', None), fails=param['fails'], logfile=param.get('logfile', self.obj_dir + "/ghdl_sim.log"), tee=param['tee']) elif param['iv']: cmd = [ run_env + self.obj_dir + "/simiv", ' '.join(param['iv_run_flags']), ' '.join(param['all_run_flags']) ] if param['use_libvpi']: # Don't enter command line on $stop, include vpi cmd += ["vvp -n -m " + self.obj_dir + "/libvpi.so"] self.run(cmd=cmd, check_finished=param['check_finished'], entering=param['entering'], expect_filename=param.get('iv_run_expect_filename', None), fails=param['fails'], logfile=param.get('logfile', self.obj_dir + "/vlt_sim.log"), tee=param['tee']) elif param['ms']: pli_opt = "" if param['use_libvpi']: pli_opt = "-pli " + self.obj_dir + "/libvpi.so" cmd = [ "echo q | " + run_env + VtOs.getenv_def('VERILATOR_MODELSIM', "vsim"), ' '.join(param['ms_run_flags']), ' '.join(param['all_run_flags']), pli_opt, (" t") ] self.run(cmd=cmd, check_finished=param['check_finished'], entering=param['entering'], expect_filename=param.get('ms_run_expect_filename', None), fails=param['fails'], logfile=param.get('logfile', self.obj_dir + "/ms_sim.log"), tee=param['tee']) elif param['nc']: cmd = [ "echo q | " + run_env + VtOs.getenv_def('VERILATOR_NCVERILOG', "ncverilog"), ' '.join(param['nc_run_flags']), ' '.join(param['all_run_flags']) ] self.run(cmd=cmd, check_finished=param['check_finished'], entering=param['entering'], expect_filename=param.get('nc_run_expect_filename', None), fails=param['fails'], logfile=param.get('logfile', self.obj_dir + "/nc_sim.log"), tee=param['tee']) elif param['vcs']: # my $fh = IO::File->new(">simv.key") or die "%Error: $! simv.key," # fh.print("quit\n"); fh.close() cmd = [ "echo q | " + run_env + "./simv", ' '.join(param['vcs_run_flags']), ' '.join(param['all_run_flags']) ] self.run(cmd=cmd, check_finished=param['check_finished'], entering=param['entering'], expect_filename=param.get('vcs_run_expect_filename', None), fails=param['fails'], logfile=param.get('logfile', self.obj_dir + "/vcs_sim.log"), tee=param['tee']) elif param['xrun']: pli_opt = "" if param['use_libvpi']: pli_opt = "-loadvpi " + self.obj_dir + "/libvpi.so:vpi_compat_bootstrap" cmd = [ "echo q | " + run_env + VtOs.getenv_def('VERILATOR_XRUN', "xrun"), ' '.join(param['xrun_run_flags']), ' '.join(param['xrun_flags2']), ' '.join(param['all_run_flags']), pli_opt, param['top_filename'], ] self.run(cmd=cmd, check_finished=param['check_finished'], entering=param['entering'], expect_filename=param.get('xrun_run_expect_filename', None), fails=param['fails'], logfile=param.get('logfile', self.obj_dir + "/xrun_sim.log"), tee=param['tee']) elif param['xsim']: cmd = [ run_env + VtOs.getenv_def('VERILATOR_XELAB', "xelab"), ' '.join(param['xsim_run_flags']), ' '.join(param['xsim_run_flags2']), ' '.join(param['all_run_flags']), (" " + self.name + ".top") ] self.run(cmd=cmd, check_finished=param['check_finished'], entering=param['entering'], expect_filename=param.get('xsim_run_expect_filename', None), fails=param['fails'], logfile=param.get('logfile', self.obj_dir + "/xsim_sim.log"), tee=param['tee']) elif param['vlt_all']: if not param['executable']: param['executable'] = self.obj_dir + "/" + param['vm_prefix'] debugger = "" if Args.gdbsim: debugger = VtOs.getenv_def('VERILATOR_GDB', "gdb") + " " elif Args.rrsim: debugger = "rr record " cmd = [ (run_env + debugger + param['executable'] + (" -ex 'run " if Args.gdbsim else "")), *param['all_run_flags'], ("'" if Args.gdbsim else ""), ] cmd += self.driver_verilated_flags self.run( cmd=cmd, aslr_off=param['aslr_off'], # Disable address space layour randomization check_finished=param['check_finished'], # Check for All Finished entering=param['entering'], # Print entering directory information expect_filename=param['expect_filename'], fails=param['fails'], logfile=param.get('logfile', self.obj_dir + "/vlt_sim.log"), tee=param['tee'], verilator_run=True, ) else: self.error("No execute step for this simulator") #--------------------------------------------------------------- # Accessors @property def aslr_off(self) -> str: if VlTest._cached_aslr_off is None: out = VtOs.run_capture('setarch --addr-no-randomize echo OK 2>/dev/null', check=False) if re.search(r'OK', out): VlTest._cached_aslr_off = "setarch --addr-no-randomize " else: VlTest._cached_aslr_off = "" return VlTest._cached_aslr_off @property def benchmarksim_filename(self) -> str: return self.obj_dir + "/" + self.name + "_benchmarksim.csv" @property def driver_verilator_flags(self) -> list: return Args.passdown_verilator_flags @property def driver_verilated_flags(self) -> list: return Args.passdown_verilated_flags @property def get_default_vltmt_threads(self) -> int: return Vltmt_Threads @property def ok(self) -> bool: if self.errors or self.errors_keep_going or self._skips: self._ok = False return self._ok def passes(self, is_ok=True): if not self.errors: self._ok = is_ok @property def too_few_cores(self) -> bool: return calc_threads(Vltmt_Threads) < Vltmt_Threads @property def trace_filename(self) -> str: if re.match(r'^fst', self.trace_format): return self.obj_dir + "/simx.fst" if re.match(r'^saif', self.trace_format): return self.obj_dir + "/simx.saif" return self.obj_dir + "/simx.vcd" def skip_if_too_few_cores(self) -> None: if self.too_few_cores: self.skip("Skipping due to too few cores") @property def v_suffix(self) -> str: return "v" @property def wno_unopthreads_for_few_cores(self) -> str: if self.too_few_cores: print("Too few cores, using -Wno-UNOPTTHREADS") return "-Wno-UNOPTTHREADS" return "" #--------------------------------------------------------------- # Capabilities @property def cmake_version(self) -> str: return Capabilities.cmake_version @property def cxx_version(self) -> str: return Capabilities.cxx_version @property def have_cmake(self) -> bool: ver = Capabilities.cmake_version if not ver: return False m = re.match(r'^(\d+)\.(\d+)$', ver) if not m: return False return int(m.group(1)) > 3 or int(m.group(2)) >= 8 # >= 3.8 @property def have_coroutines(self) -> bool: return Capabilities.have_coroutines @property def have_dev_asan(self) -> bool: return Capabilities.have_dev_asan @property def have_dev_gcov(self) -> bool: return Capabilities.have_dev_gcov @property def have_gdb(self) -> bool: return Capabilities.have_gdb @property def have_sc(self) -> bool: return Capabilities.have_sc @property def have_solver(self) -> bool: self._have_solver_called = True return Capabilities.have_solver @property def make_version(self) -> str: return Capabilities.make_version #--------------------------------------------------------------- # OS functions def getenv_def(self, var: str, default=None) -> str: """Return environment variable, returning default if does not exist""" return VtOs.getenv_def(var, default) @staticproperty def max_procs() -> int: # pylint: disable=no-method-argument """Return maximum processor count can use (system CPUs or numactl setting)""" return VtOs.max_procs def mkdir_ok(self, filename) -> None: """Make directory, no error if exists""" if test.verbose: print("\tmkdir " + filename) VtOs.mkdir_ok(filename) def run_capture(self, cmd: str, check=True) -> str: """Run a command and return results""" if test.verbose: print("\t" + cmd) return VtOs.run_capture(cmd, check=check) def setenv(self, var: str, val: str) -> None: """Set environment variable""" print("\texport %s='%s'" % (var, val)) os.environ[var] = val def unlink_ok(self, filename) -> None: """Unlink a file, no error if fails""" if test.verbose: print("\trm " + filename) VtOs.unlink_ok(filename) #---------------------------------------------------------------------- def run( self, # cmd: list, aslr_off=False, # Disable address space layour randomization check_finished=False, # Check for All Finished entering=None, # Print entering directory information expect_filename=None, # Filename that should match logfile fails=False, # True: normal 1 exit code, 'any': any exit code logfile=None, # Filename to write putput to tee=True, verilator_run=False) -> bool: # Move gcov data to parallel area try: command = ' '.join(cmd) except TypeError: print('run(cmd=' + pformat(cmd)) command = ' '.join(cmd) if aslr_off and aslr_off != "": prefix = self.aslr_off if prefix: command = prefix + " " + command if Args.benchmark and re.match(r'^cd ', command): command = "time " + command print("\t" + command + ((" > " + logfile) if logfile else "")) if entering: print("driver: Entering directory '" + os.path.abspath(entering) + "'") # Execute command redirecting output, keeping order between stderr and stdout. # Must do low-level IO so GCC interaction works (can't be line-based) status = None # process_caller_block # pylint: disable=using-constant-test logfh = None if logfile: logfh = open(logfile, 'wb') # pylint: disable=consider-using-with if not Args.interactive_debugger: # Some parallel job's run() may attempt to capture driver.py's # terminal, e.g. gdb does this. So, unless known we want to run GDB # (where we want it to control the terminal), become a controlling # terminal for this job so such a capture won't break driver.py's # signaling, which would e.g. break control-C. pid, fd = pty.fork() if pid == 0: os.environ['TERM'] = "dumb" subprocess.run(["stty", "nl"], check=True) # No carriage returns os.execlp("bash", "/bin/bash", "-c", command) else: while True: try: data = os.read(fd, 2048) self._run_output(data, logfh, tee) # Parent detects child termination by checking for b'' if not data: break except OSError: break (pid, rc) = os.waitpid(pid, 0) else: # Do not redirect output when using an interactive debugger, so it # can have direct access to the user terminal (so terminal control # characters and the like work). That means the log file will be # empty but hopefully that's ok, just re-run the test without the # interactive debugger to confirm a fix. with subprocess.Popen(command, shell=True, bufsize=0) as proc: proc.wait() rc = proc.returncode # Negative if killed by signal if logfh: logfh.close() if (rc in ( -4, # SIGILL -8, # SIGFPA -11)): # SIGSEGV self.error("Exec failed with core dump") status = 128 + (-rc) # So is "normal" shell 0-255 status elif rc >= 256: # waitpid returns status << 8; subprocess otherwise; handle both status = int(rc / 256) # So is shell $?-like elif rc: status = rc else: status = 0 sys.stdout.flush() sys.stderr.flush() if entering: print("driver: Leaving directory '" + os.path.abspath(entering) + "'") if not fails and status: firstline = self._error_log_summary(logfile) # Strip ANSI escape sequences firstline = re.sub(r'\x1B(?:[@-Z\\-_]|\[[0-?]*[ -/]*[@-~])', '', firstline) self.error("Exec of " + self._error_cmd_simplify(cmd) + " failed: " + firstline) if fails and status: if not verilator_run: print("(Exec failed, matching expected fail)") elif fails == 'any': print("(Exec failed, matching expected 'any' exit code fail)") elif fails is True: if status == 1: print("(Exec failed, matching expected 'True' exit code 1 fail)") else: self.error("Exec of " + self._error_cmd_simplify(cmd) + " failed with exit code " + str(status) + ", but expected 'True' exit code 1 fail") else: # Future: support numeric exit code? self.error("fails=" + str(fails) + " is not legal value") if fails and not status: self.error("Exec of " + self._error_cmd_simplify(cmd) + " ok, but expected to fail") if self.errors or self._skips: return False # Read the log file a couple of times to allow for NFS delays if check_finished: delay = 0.25 for tryn in range(Args.log_retries - 1, -1, -1): if tryn != Args.log_retries - 1: time.sleep(delay) delay = min(1, delay * 2) moretry = tryn != 0 if not self._run_log_try(logfile, check_finished, moretry): break if expect_filename: self.files_identical(logfile, expect_filename, is_logfile=True) return False return True def _run_output(self, data, logfh, tee): if re.search(r'--debug-exit-uvm23: Exiting', str(data)): self._force_pass = True print("EXIT: " + str(data)) if tee: sys.stdout.write(data.decode('latin-1')) if Args.interactive_debugger: sys.stdout.flush() if logfh: logfh.write(data) def _run_log_try(self, logfile: str, check_finished: bool, moretry: bool) -> bool: # If moretry, then return true to try again with open(logfile, 'r', encoding='latin-1', newline='\n') as fh: if not fh and moretry: return True wholefile = str(fh.read()) # Finished? if check_finished and not re.search(r'\*\-\* All Finished \*\-\*', wholefile): if moretry: return True self.error("Missing '*-* All Finished *-*'") return False ####################################################################### # Little utilities @staticmethod def _error_cmd_simplify(cmd: list) -> str: if cmd[0] == "perl" and re.search(r'/bin/verilator', cmd[1]): return "verilator" return cmd[0] def _error_log_summary(self, filename: str) -> str: size = "" if False: # Show test size for fault grading # pylint: disable=using-constant-test if self.top_filename and os.path.exists(self.top_filename): size = "(Test " + str(os.stat(self.top_filename).st_size) + " B) " if not filename: return size firstline = "" with open(filename, 'r', encoding="utf8") as fh: lineno = 0 for line in fh: lineno += 1 if lineno > 100: break line = line.rstrip() if re.match(r'^- ', line): # Debug message continue if not firstline: firstline = line if (re.search(r'error|warn', line, re.IGNORECASE) and not re.search(r'-Werror', line)): return size + line return size + firstline def _make_main(self, timing_loop: bool) -> None: if timing_loop and self.sc: self.error("Cannot use timing loop and SystemC together!") self._read_inputs_v() filename = self.main_filename with open(filename, "w", encoding="utf8") as fh: fh.write("// Test defines\n") fh.write("#define MAIN_TIME_MULTIPLIER " + str(int(round(self.main_time_multiplier, 0))) + "\n") fh.write("#include \n") if self.benchmarksim: fh.write("#include \n") fh.write("#include \n") fh.write("#include \n") fh.write("// OS header\n") fh.write('#include "verilatedos.h"' + "\n") fh.write("// Generated header\n") fh.write('#include "' + self.vm_prefix + '.h"' + "\n") fh.write("// General headers\n") fh.write('#include "verilated.h"' + "\n") if self.sc: fh.write('#include "systemc.h"' + "\n") if self.trace and self.trace_format == 'fst-c': fh.write("#include \"verilated_fst_c.h\"\n") if self.trace and self.trace_format == 'fst-sc': fh.write("#include \"verilated_fst_sc.h\"\n") if self.trace and self.trace_format == 'vcd-c': fh.write("#include \"verilated_vcd_c.h\"\n") if self.trace and self.trace_format == 'vcd-sc': fh.write("#include \"verilated_vcd_sc.h\"\n") if self.trace and self.trace_format == 'saif-c': fh.write("#include \"verilated_saif_c.h\"\n") if self.trace and self.trace_format == 'saif-sc': fh.write("#include \"verilated_saif_sc.h\"\n") if self.savable: fh.write("#include \"verilated_save.h\"\n") fh.write("std::unique_ptr<" + self.vm_prefix + "> topp;\n") if self.savable: fh.write("\n") fh.write("void save_model(const char* filenamep) {\n") fh.write(" VL_PRINTF(\"Saving model to '%s'\\n\", filenamep);\n") fh.write(" VerilatedSave os;\n") fh.write(" os.open(filenamep);\n") fh.write(" os << *topp;\n") fh.write(" os.close();\n") fh.write("}\n") fh.write("\n") fh.write("void restore_model(const char* filenamep) {\n") fh.write(" VL_PRINTF(\"Restoring model from '%s'\\n\", filenamep);\n") fh.write(" VerilatedRestore os;\n") fh.write(" os.open(filenamep);\n") fh.write(" os >> *topp;\n") fh.write(" os.close();\n") fh.write("}\n") #### Main if self.sc: fh.write("extern int sc_main(int argc, char** argv);\n") fh.write("int sc_main(int argc, char** argv) {\n") if 'fastclk' in self._inputs: if self.pins_sc_uint_bool: fh.write(" sc_signal> fastclk;\n") else: fh.write(" sc_signal fastclk;\n") if 'clk' in self._inputs: if self.pins_sc_uint_bool: fh.write(" sc_signal> clk;\n") else: fh.write(" sc_signal clk;\n") fh.write(" sc_set_time_resolution(1, " + self.sc_time_resolution + ");\n") fh.write(" sc_time sim_time(" + str(self.sim_time) + ", " + self.sc_time_resolution + ");\n") else: fh.write("int main(int argc, char** argv) {\n") fh.write(" uint64_t sim_time = " + str(self.sim_time) + ";\n") fh.write( " const std::unique_ptr contextp{new VerilatedContext};\n") fh.write(" contextp->threads(" + str(self.context_threads) + ");\n") fh.write(" contextp->commandArgs(argc, argv);\n") fh.write(" contextp->debug(" + ('1' if self.verilated_debug else '0') + ");\n") fh.write(" srand48(5);\n") # Ensure determinism if self.verilated_randReset is not None and self.verilated_randReset != "": fh.write(" contextp->randReset(" + str(self.verilated_randReset) + ");\n") fh.write(" topp.reset(new " + self.vm_prefix + "{\"top\"});\n") if self.verilated_debug: fh.write(" contextp->internalsDump()\n;") if self.sc: if 'fastclk' in self._inputs: fh.write(" topp->fastclk(fastclk);\n") if 'clk' in self._inputs: fh.write(" topp->clk(clk);\n") setp = "" else: fh.write(" topp->eval();\n") setp = "topp->" if self.benchmarksim: fh.write(" std::chrono::time_point starttime;\n") fh.write(" bool warm = false;\n") fh.write(" uint64_t n_evals = 0;\n") if self.trace: fh.write("\n") fh.write("#if VM_TRACE\n") fh.write(" contextp->traceEverOn(true);\n") if self.trace_format == 'fst-c': fh.write(" std::unique_ptr tfp{new VerilatedFstC};\n") if self.trace_format == 'fst-sc': fh.write(" std::unique_ptr tfp{new VerilatedFstSc};\n") if self.trace_format == 'vcd-c': fh.write(" std::unique_ptr tfp{new VerilatedVcdC};\n") if self.trace_format == 'vcd-sc': fh.write(" std::unique_ptr tfp{new VerilatedVcdSc};\n") if self.trace_format == 'saif-c': fh.write(" std::unique_ptr tfp{new VerilatedSaifC};\n") if self.trace_format == 'saif-sc': fh.write(" std::unique_ptr tfp{new VerilatedSaifSc};\n") if self.sc: fh.write(" sc_core::sc_start(sc_core::SC_ZERO_TIME);" + " // Finish elaboration before trace and open\n") fh.write(" topp->trace(tfp.get(), 99);\n") fh.write(" tfp->open(\"" + self.trace_filename + "\");\n") if self.trace and not self.sc: fh.write(" if (tfp) tfp->dump(contextp->time());\n") fh.write("#endif\n") if self.savable: fh.write(" const char* save_time_strp" " = contextp->commandArgsPlusMatch(\"save_time=\");\n") fh.write(" unsigned int save_time = !save_time_strp[0]" " ? 0 : std::atoi(save_time_strp + std::strlen(\"+save_time=\"));\n") fh.write(" const char* save_restore_strp" " = contextp->commandArgsPlusMatch(\"save_restore=\");\n") fh.write(" unsigned int save_restore = !save_restore_strp[0] ? 0 : 1;\n") if self.savable: fh.write(" if (save_restore) {\n") fh.write(" restore_model(\"" + self.obj_dir + "/saved.vltsv\");\n") fh.write(" } else {\n") else: fh.write(" {\n") if 'fastclk' in self._inputs: fh.write(" " + setp + "fastclk = false;\n") if 'clk' in self._inputs: fh.write(" " + setp + "clk = false;\n") if not timing_loop: self._print_advance_time(fh, 10, None) fh.write(" }\n") timestamp = "sc_time_stamp()" if self.sc else "contextp->time()" fh.write(" while (") if not timing_loop or 'clk' in self._inputs: fh.write("(" + timestamp + " < sim_time * MAIN_TIME_MULTIPLIER) && ") fh.write("!contextp->gotFinish()) {\n") if timing_loop: fh.write(" topp->eval();\n") if self.trace: fh.write("#if VM_TRACE\n") fh.write(" if (tfp) tfp->dump(contextp->time());\n") fh.write("#endif // VM_TRACE\n") if 'clk' in self._inputs: fh.write(" const uint64_t cycles" " = contextp->time() / MAIN_TIME_MULTIPLIER;\n") fh.write(" uint64_t new_time = (cycles + 1) * MAIN_TIME_MULTIPLIER;\n") fh.write(" if (topp->eventsPending() &&\n") fh.write(" topp->nextTimeSlot()" " / MAIN_TIME_MULTIPLIER <= cycles) {\n") fh.write(" new_time = topp->nextTimeSlot();\n") fh.write(" } else {\n") if self.pins_sc_uint_bool: fh.write(" " + setp + "clk.write(!" + setp + "clk.read());\n") else: fh.write(" " + setp + "clk = !" + setp + "clk;\n") fh.write(" }\n") fh.write(" contextp->time(new_time);\n") else: fh.write(" if (!topp->eventsPending()) break;\n") fh.write(" contextp->time(topp->nextTimeSlot());\n") else: for i in range(5): action = False if 'fastclk' in self._inputs: if self.pins_sc_uint_bool: fh.write(" " + setp + "fastclk.write(!" + setp + "fastclk.read());\n") else: fh.write(" " + setp + "fastclk = !" + setp + "fastclk;\n") action = True if i == 0 and 'clk' in self._inputs: if self.pins_sc_uint_bool: fh.write(" " + setp + "clk.write(!" + setp + "clk.read());\n") else: fh.write(" " + setp + "clk = !" + setp + "clk;\n") action = True if self.savable: fh.write(" if (save_time && " + timestamp + " == save_time) {\n") fh.write(" save_model(\"" + self.obj_dir + "/saved.vltsv\");\n") fh.write(" printf(\"Exiting after save_model\\n\");\n") fh.write(" topp.reset(nullptr);\n") fh.write(" return 0;\n") fh.write(" }\n") self._print_advance_time(fh, 1, action) if self.benchmarksim: fh.write(" if (VL_UNLIKELY(!warm)) {\n") fh.write(" starttime = std::chrono::steady_clock::now();\n") fh.write(" warm = true;\n") fh.write(" } else {\n") fh.write(" ++n_evals;\n") fh.write(" }\n") fh.write(" }\n") if self.benchmarksim: fh.write(" {\n") fh.write(" const std::chrono::duration exec_s" " = std::chrono::steady_clock::now() - starttime;\n") fh.write(" std::ofstream benchfile(\"" + self.benchmarksim_filename + "\", std::ofstream::out | std::ofstream::app);\n") fh.write(" benchfile << std::fixed << std::setprecision(9)" " << n_evals << \",\" << exec_s.count() << std::endl;\n") fh.write(" benchfile.close();\n") fh.write(" }\n") fh.write(" if (!contextp->gotFinish()) {\n") fh.write(' vl_fatal(__FILE__, __LINE__, "main",' + ' "%Error: Timeout; never got a $finish");' + "\n") fh.write(" }\n") fh.write(" topp->final();\n") fh.write("\n") if self.coverage: fh.write("#if VM_COVERAGE\n") fh.write(" contextp->coveragep()->write(\"" + self.coverage_filename + "\");\n") fh.write("#endif // VM_COVERAGE\n") if self.trace: fh.write("#if VM_TRACE\n") fh.write(" if (tfp) tfp->close();\n") fh.write(" tfp.reset();\n") fh.write("#endif // VM_TRACE\n") fh.write(" topp.reset();\n") fh.write(" return 0;\n") fh.write("}\n") def _print_advance_time(self, fh, timeinc: str, action: bool) -> None: setp = "" if self.sc else "topp->" if self.sc: fh.write(" sc_start(" + str(timeinc) + " * MAIN_TIME_MULTIPLIER, " + self.sc_time_resolution + ");\n") else: if action: fh.write(" " + setp + "eval();\n") if self.trace and not self.sc: fh.write("#if VM_TRACE\n") fh.write(" if (tfp) tfp->dump(contextp->time());\n") fh.write("#endif // VM_TRACE\n") fh.write(" contextp->timeInc(" + str(timeinc) + " * MAIN_TIME_MULTIPLIER);\n") ####################################################################### def _make_top(self, needed=True) -> None: if not needed: return self._make_top_v() def _make_top_v(self) -> None: self._read_inputs_v() with open(self.top_shell_filename, 'w', encoding="utf8") as fh: fh.write("module top;\n") for inp in sorted(self._inputs.keys()): fh.write(" reg " + inp + ";\n") # Inst fh.write(" t t (\n") comma = "" for inp in sorted(self._inputs.keys()): fh.write(" " + comma + "." + inp + " (" + inp + ")\n") comma = "," fh.write(" );\n") # Waves fh.write("\n") fh.write("`ifdef WAVES\n") fh.write(" initial begin\n") fh.write(" $display(\"-Tracing Waves to Dumpfile: " + self.trace_filename + "\");\n") fh.write(" $dumpfile(\"" + self.trace_filename + "\");\n") fh.write(" $dumpvars(0, top);\n") fh.write(" end\n") fh.write("`endif\n") # Test fh.write("\n") fh.write(" initial begin\n") if 'fastclk' in self._inputs: fh.write(" fastclk = 0;\n") if 'clk' in self._inputs: fh.write(" clk = 0;\n") fh.write(" #10;\n") if 'fastclk' in self._inputs: fh.write(" fastclk = 1;\n") if 'clk' in self._inputs: fh.write(" clk = 1;\n") fh.write(" while ($time < " + str(self.sim_time) + ") begin\n") for i in range(6): fh.write(" #1;\n") if 'fastclk' in self._inputs: fh.write(" fastclk = !fastclk;\n") if i == 4 and 'clk' in self._inputs: fh.write(" clk = !clk;\n") fh.write(" end\n") fh.write(" end\n") fh.write("endmodule\n") ####################################################################### def _read_inputs_v(self) -> None: filename = self.top_filename if not os.path.exists(filename): filename = self.t_dir + '/' + filename with open(filename, 'r', encoding="utf8") as fh: get_sigs = True inputs = {} for line in fh: if get_sigs: # Does not support escaped signals, we only need "clk" and a few others m = re.match(r'^\s*input\s*(logic|bit|reg|wire)?\s*([A-Za-z0-9_]+)', line) if m: inputs[m.group(2)] = m.group(2) if re.match(r'^\s*(function|task|endmodule)', line): get_sigs = False # Ignore any earlier inputs; Module 't' has precedence if re.match(r'^\s*module\s+t\b', line): inputs = {} get_sigs = True for sig, val in inputs.items(): self._inputs[sig] = val ####################################################################### # File utilities def files_identical(self, fn1: str, fn2: str, is_logfile=False, strip_hex=False) -> None: """Test if two files have identical contents""" delay = 0.25 for tryn in range(Args.log_retries, -1, -1): if tryn != Args.log_retries - 1: time.sleep(delay) delay = min(1, delay * 2) moretry = tryn != 0 if not self._files_identical_try( fn1=fn1, fn2=fn2, is_logfile=is_logfile, strip_hex=strip_hex, moretry=moretry): break def _files_identical_try(self, fn1: str, fn2: str, is_logfile: bool, strip_hex: bool, moretry: bool) -> bool: # If moretry, then return true to try again try: f1 = open( # pylint: disable=consider-using-with fn1, 'r', encoding='latin-1', newline='\n') except FileNotFoundError: f1 = None if not moretry: self.error("Files_identical file does not exist: " + fn1) return True # Retry try: f2 = open( # pylint: disable=consider-using-with fn2, 'r', encoding='latin-1', newline='\n') except FileNotFoundError: f2 = None if not moretry: self.copy_if_golden(fn1, fn2) self.error("Files_identical file does not exist: " + fn2) return True # Retry again = self._files_identical_reader(f1, f2, fn1=fn1, fn2=fn2, is_logfile=is_logfile, strip_hex=strip_hex, moretry=moretry) if f1: f1.close() if f2: f2.close() return again def _files_identical_reader(self, f1, f2, fn1: str, fn2: str, is_logfile: bool, strip_hex: bool, moretry: bool) -> bool: # If moretry, then return true to try again l1s = f1.readlines() l2s = f2.readlines() if f2 else [] # print(" rawGOT="+pformat(l1s)+"\n rawEXP="+pformat(l2s)) if is_logfile: l1o = [] for line in l1s: if (re.match(r'^- [^\n]+\n', line) # or re.match(r'^- [a-z.0-9]+:\d+:[^\n]+\n', line) or re.match(r'^-node:', line) # or re.match(r'^dot [^\n]+\n', line) # or re.match(r'^Aborted', line) # or re.match(r'^In file: .*\/sc_.*:\d+', line) # or re.match(r'^libgcov.*', line) # or re.match(r'--- \/tmp\/', line) # t_difftree.py or re.match(r'\+\+\+ \/tmp\/', line) # t_difftree.py or re.match(r'^==[0-9]+== ?[^\n]*\n', line)): # valgrind continue # Don't put control chars or unstable lines into source repository while True: (line, didn) = re.subn(r'(Internal Error: [^\n]+?\.(cpp|h)):[0-9]+', r'\1:#', line) if not didn: break # --vlt vs --vltmt run differences line = re.sub(r'^-V\{t[0-9]+,[0-9]+\}', '-V{t#,#}', line) line = re.sub(r'\r', '<#013>', line) line = re.sub(r'Command Failed[^\n]+', 'Command Failed', line) line = re.sub(r'Version: Verilator[^\n]+', 'Version: Verilator ###', line) line = re.sub(r'"version": "[^"]+"', '"version": "###"', line) line = re.sub(r'CPU Time: +[0-9.]+ seconds[^\n]+', 'CPU Time: ###', line) line = re.sub(r'\?v=[0-9.]+', '?v=latest', line) # warning URL line = re.sub(r'_h[0-9a-f]{8}_', '_h########_', line) line = re.sub(r'%Error: /[^: ]+/([^/:])', r'%Error: .../\1', line) # Avoid absolute paths line = re.sub(r'("file://)/[^: ]+/([^/:])', r'\1/.../\2', line) # Avoid absolute paths line = re.sub(r' \/[^ ]+\/verilated_std.sv', ' verilated_std.sv', line) # (line, n) = re.subn(r'Exiting due to.*', r"Exiting due to", line) if n: l1o.append(line) break # Trunc rest l1o.append(line) # l1s = l1o if strip_hex: l1o = [] for line in l1s: line = re.sub(r'\b0x[0-9a-f]+', '0x#', line) l1o.append(line) l1s = l1o for lineno_m1 in range(0, max(len(l1s), len(l2s))): l1 = l1s[lineno_m1] if lineno_m1 < len(l1s) else "*EOF*\n" l2 = l2s[lineno_m1] if lineno_m1 < len(l2s) else "*EOF*\n" if l1 != l2: # print(" clnGOT="+pformat(l1s)+"\n clnEXP="+pformat(l2s)) if moretry: return True # Retry self.error_keep_going("Line " + str(lineno_m1) + " miscompares; " + fn1 + " != " + fn2) for c in range(min(len(l1), len(l2))): if ord(l1[c]) != ord(l2[c]): print("Miscompare starts at column " + str(c) + (" w/ F1(got)=0x%02x F2(exp)=0x%02x" % (ord(l1[c]), ord(l2[c]))), file=sys.stderr) break print("F1(got): " + l1 + "F2(exp): " + l2, file=sys.stderr) if 'HARNESS_UPDATE_GOLDEN' in os.environ: # Update golden files with current print("%Warning: HARNESS_UPDATE_GOLDEN set: cp " + fn1 + " " + fn2, file=sys.stderr) with open(fn2, 'w', encoding="utf8") as fhw: fhw.write(''.join(l1s)) else: print("To update reference: HARNESS_UPDATE_GOLDEN=1 {command} or --golden", file=sys.stderr) return False # No retry - bad return False # No retry - good def files_identical_sorted(self, fn1: str, fn2: str, is_logfile=False) -> None: """Test if two files, after sorting both, have identical contents""" # Set LC_ALL as suggested in the sort manpage to avoid sort order # changes from the locale. os.environ['LC_ALL'] = 'C' fn1sort = fn1 + '.sort' self.run(cmd=['sort', fn1, "> " + fn1sort]) self.files_identical(fn1sort, fn2, is_logfile) def copy_if_golden(self, fn1: str, fn2: str) -> None: """Copy a file if updating golden .out files""" if 'HARNESS_UPDATE_GOLDEN' in os.environ: # Update golden files with current print("%Warning: HARNESS_UPDATE_GOLDEN set: cp " + fn1 + " " + fn2, file=sys.stderr) shutil.copy(fn1, fn2) def vcd_identical(self, fn1: str, fn2: str) -> None: """Test if two VCD files have logically-identical contents""" # vcddiff to check transitions, if installed cmd = "vcddiff --help" out = test.run_capture(cmd, check=True) cmd = 'vcddiff ' + fn1 + ' ' + fn2 out = test.run_capture(cmd, check=True) if out != "": cmd = 'vcddiff ' + fn2 + " " + fn1 # Reversed arguments out = VtOs.run_capture(cmd, check=False) if out != "": print(out) self.copy_if_golden(fn1, fn2) self.error("VCD miscompares " + fn2 + " " + fn1) # vcddiff doesn't check module and variable scope, so check that # Also provides backup if vcddiff not installed h1 = self._vcd_read(fn1) h2 = self._vcd_read(fn2) a = json.dumps(h1, sort_keys=True, indent=1) b = json.dumps(h2, sort_keys=True, indent=1) if a != b: self.copy_if_golden(fn1, fn2) self.error("VCD hier miscompares " + fn1 + " " + fn2 + "\nGOT=" + a + "\nEXP=" + b + "\n") def fst2vcd(self, fn1: str, fn2: str) -> None: cmd = "fst2vcd -h" out = VtOs.run_capture(cmd, check=False) if out == "" or not re.search(r'Usage:', out): self.skip("No fst2vcd installed") return cmd = 'fst2vcd -e -f "' + fn1 + '" -o "' + fn2 + '"' print("\t " + cmd + "\n") # Always print to help debug race cases out = VtOs.run_capture(cmd, check=False) print(out) def fst_identical(self, fn1: str, fn2: str) -> None: """Test if two FST files have logically-identical contents""" tmp = fn1 + ".vcd" self.fst2vcd(fn1, tmp) self.vcd_identical(tmp, fn2) def saif_identical(self, fn1: str, fn2: str) -> None: """Test if two SAIF files have logically-identical contents""" cmd = nodist_directory + '/verilator_saif_diff --first "' + fn1 + '" --second "' + fn2 + '"' print("\t " + cmd + "\n") out = test.run_capture(cmd, check=True) if out != '': print(out) self.copy_if_golden(fn1, fn2) self.error("SAIF files don't match!") def _vcd_read(self, filename: str) -> dict: data = {} with open(filename, 'r', encoding='latin-1') as fh: hier_stack = ["TOP"] var = [] for line in fh: match1 = re.search(r'\$scope (module|struct|interface)\s+(\S+)', line) match2 = re.search(r'(\$var (\S+)\s+\d+\s+)\S+\s+(\S+)', line) match3 = re.search(r'(\$attrbegin .* \$end)', line) line = line.rstrip() # print("VR"+ ' '*len(hier_stack) +" L " + line) if match1: # $scope name = match1.group(2) # print("VR"+ ' '*len(hier_stack) +" scope " + line) hier_stack += [name] scope = '.'.join(hier_stack) data[scope] = match1.group(1) + " " + name elif match2: # $var # print("VR"+ ' '*len(hier_stack) +" var " + line) scope = '.'.join(hier_stack) var = match2.group(2) data[scope + "." + var] = match2.group(1) + match2.group(3) elif match3: # $attrbegin # print("VR"+ ' '*len(hier_stack) +" attr " + line) if var: scope = '.'.join(hier_stack) data[scope + "." + var + "#"] = match3.group(1) elif re.search(r'\$enddefinitions', line): break n = len(re.findall(r'\$upscope', line)) if n: for i in range(0, n): # pylint: disable=unused-variable # print("VR"+ ' '*len(hier_stack) +" upscope " + line) hier_stack.pop() return data def inline_checks(self) -> None: covfn = self.coverage_filename contents = self.file_contents(covfn) if self.verbose: self.oprint("Extract checks") with open(self.top_filename, 'r', encoding="utf8") as fh: flineno = 0 for line in fh: flineno += 1 if re.search(r'CHECK', line): match1 = re.search( r'CHECK_COVER *\( *((-|[0-9])+) *,' r'*"([^"]+)" *, *("([^"]+)" *,|) *(\d+) *\)', line) match2 = re.search(r'CHECK_COVER_MISSING *\( *((-|[0-9])+) *\)', line) if match1: lineno = flineno + int(match1.group(1)) hier = match1.group(3) comment = match1.group(5) count = match1.group(6) regexp = "\001l\002" + str(lineno) if comment: regexp += ".*\001o\002" + re.escape(comment) if hier: regexp += ".*\001h\002" + re.escape(hier) regexp += ".*' " + str(count) if not re.search(regexp, contents): self.error("CHECK_COVER: " + covfn + ":" + str(flineno) + ": Regexp not found: " + regexp + "\n" + "From " + self.top_filename + ": " + line) elif match2: lineno = flineno + int(match2.group(1)) regexp = "\001l\002" + str(lineno) if re.search(regexp, contents): self.error("CHECK_COVER_MISSING: " + covfn + ":" + str(flineno) + ": Regexp found: " + regexp + "\n" + "From " + self.top_filename + ": " + line) else: self.error(self.top_filename + ":" + str(flineno) + ": Unknown CHECK request: " + line) @staticproperty def cfg_with_ccache() -> bool: # pylint: disable=no-method-argument if VlTest._cached_cfg_with_ccache is None: mkf = VlTest._file_contents_static(os.environ['VERILATOR_ROOT'] + "/include/verilated.mk") VlTest._cached_cfg_with_ccache = bool(re.search(r'OBJCACHE \?= ccache', mkf)) return VlTest._cached_cfg_with_ccache def glob_some(self, pattern: str) -> list: """Return list of filenames matching a glob, with at least one match required.""" files = glob.glob(pattern) # print("glob_some('" + pattern + "') files =\n " + pformat(files)) if not files: self.error("glob_one: pattern '" + pattern + "' does not match any files") return ['No_file_found'] return sorted(files) def glob_one(self, pattern: str) -> str: """Return a filename matching a glob, with exactly one match required.""" files = self.glob_some(pattern) if files and len(files) > 1: msg = "glob_one: pattern '" + pattern + "' matches multiple files:\n" for file in files: msg += file + "\n" self.error(msg) return 'Multiple_files_found' return files[0] def file_grep_not(self, filename: str, regexp) -> None: contents = self.file_contents(filename) if contents == "_Already_Errored_": return if re.search(regexp, contents, re.MULTILINE): self.error("File_grep_not: " + filename + ": Regexp found: '" + regexp + "'") def file_grep(self, filename: str, regexp, expvalue=None) -> Optional[list]: contents = self.file_contents(filename) if contents == "_Already_Errored_": return None match = re.search(regexp, contents, re.MULTILINE) if not match: self.error("File_grep: " + filename + ": Regexp not found: " + regexp) return None if expvalue is not None and str(expvalue) != match.group(1): self.error("File_grep: " + filename + ": Got='" + match.group(1) + "' Expected='" + str(expvalue) + "' in regexp: '" + regexp + "'") return None return [match.groups()] def file_grep_count(self, filename: str, regexp, expcount: int) -> None: contents = self.file_contents(filename) if contents == "_Already_Errored_": return count = len(re.findall(regexp, contents)) if expcount != count: self.error("File_grep_count: " + filename + ": Got='" + str(count) + "' Expected='" + str(expcount) + "' in regexp: '" + regexp + "'") def file_grep_any(self, filenames: list, regexp, expvalue=None) -> None: for filename in filenames: contents = self.file_contents(filename) if contents == "_Already_Errored_": return match = re.search(regexp, contents) if match: if expvalue is not None and str(expvalue) != match.group(1): self.error("file_grep: " + filename + ": Got='" + match.group(1) + "' Expected='" + str(expvalue) + "' in regexp: " + regexp) return msg = "file_grep_any: Regexp '" + regexp + "' not found in any of the following files:\n" for filename in filenames: msg += filename + "\n" self.error(msg) def file_contents(self, filename: str) -> str: if filename not in self._file_contents_cache: if not os.path.exists(filename): self._file_contents_cache[filename] = "_Already_Errored_" self.error("File_contents file not found: " + filename) else: with open(filename, 'r', encoding='latin-1') as fh: self._file_contents_cache[filename] = str(fh.read()) return self._file_contents_cache[filename] @staticmethod def _file_contents_static(filename: str) -> str: if filename not in VlTest._file_contents_cache: if not os.path.exists(filename): VlTest._file_contents_cache[filename] = "_Already_Errored_" sys.exit("_file_contents_static file not found: " + filename) else: with open(filename, 'r', encoding='latin-1') as fh: VlTest._file_contents_cache[filename] = str(fh.read()) return VlTest._file_contents_cache[filename] def write_wholefile(self, filename: str, contents: str) -> None: with open(filename, 'wb') as fh: fh.write(contents.encode('latin-1')) if filename in self._file_contents_cache: del self._file_contents_cache[filename] def file_sed(self, in_filename: str, out_filename, edit_lambda) -> None: contents = self.file_contents(in_filename) contents = edit_lambda(contents) self.write_wholefile(out_filename, contents) def extract( self, in_filename: str, out_filename: str, regexp=r'.*', lineno_adjust=-9999, # lines=None) -> None: #'#, #-#' if not os.path.exists(test.root + "/.git"): self.skip("Not in a git repository") return temp_fn = out_filename temp_fn = re.sub(r'.*/', '', temp_fn) temp_fn = self.obj_dir + "/" + temp_fn out = [] emph = "" lineno = 0 lineno_out = 0 with open(in_filename, 'r', encoding="latin-1") as fh: for line in fh: lineno += 1 if re.search(regexp, line) and self._lineno_match(lineno, lines): match = re.search(r't/[A-Za-z0-9_]+.v:(\d+):(\d+):', line) if match: mlineno = int(match.group(1)) + lineno_adjust col = int(match.group(2)) mlineno = max(1, mlineno) line = re.sub(r't/[A-Za-z0-9_]+.v:(\d+):(\d+):', 'example.v:' + str(mlineno) + ':' + str(col), line) out.append(" " + line) lineno_out += 1 if '<--' in line: if emph: emph += "," emph += str(lineno_out) with open(temp_fn, 'w', encoding="latin-1") as fhw: lang = " sv" if re.search(r'\.s?vh?$', in_filename) else "" fhw.write(".. comment: generated by " + self.name + "\n") fhw.write(".. code-block::" + lang + "\n") if lang != "" and len(out) > 1: fhw.write(" :linenos:\n") if emph: fhw.write(" :emphasize-lines: " + emph + "\n") fhw.write("\n") for line in out: line = re.sub(r' +$', '', line) fhw.write(line) self.files_identical(temp_fn, out_filename) @staticmethod def _lineno_match(lineno: int, lines: str) -> bool: if not lines: return True for lc in lines.split(','): match1 = re.match(r'^(\d+)$', lc) match2 = re.match(r'^(\d+)-(\d+)$', lc) if match1 and int(match1.group(1)) == lineno: return True if match2 and int(match2.group(1)) <= lineno <= int(match2.group(2)): return True return False ###################################################################### ###################################################################### # Global Functions def calc_jobs() -> int: ok_threads = VtOs.max_procs print("driver.py: Found %d cores, using -j %d" % (ok_threads, ok_threads)) return ok_threads def calc_threads(default_threads) -> int: ok_threads = int(VtOs.max_procs) # int() to appease pylint return ok_threads if (ok_threads < default_threads) else default_threads def _calc_hashset() -> None: match = re.match(r'^(\d+)/(\d+)$', Args.hashset) if not match: sys.exit("%Error: Need number/number format for --hashset: " + Args.hashset) setn = int(match.group(1)) nsets = int(match.group(2)) new = [] global Arg_Tests for t in Arg_Tests: checksum = int(hashlib.sha256(t.encode("utf-8")).hexdigest()[0:4], 16) if (setn % nsets) == (checksum % nsets): new.append(t) Arg_Tests = new ####################################################################### ####################################################################### # Verilator utilities def _parameter(param: str) -> None: global _Parameter_Next_Level if _Parameter_Next_Level: if not re.match(r'^(\d+)$', param): sys.exit("%Error: Expected number following " + _Parameter_Next_Level + ": " + param) Args.passdown_verilator_flags.append(param) _Parameter_Next_Level = None elif re.match(r'^(\+verilator\+.*)', param): Args.passdown_verilated_flags.append(param) elif re.search(r'\.py', param): Arg_Tests.append(param) elif re.match(r'^-?(-debugi|-dumpi)', param): Args.passdown_verilator_flags.append(param) _Parameter_Next_Level = param elif re.match(r'^-?(-W||-debug-check)', param): Args.passdown_verilator_flags.append(param) else: sys.exit("%Error: Unknown parameter: " + param) def run_them() -> None: VtOs.mkdir_ok("obj_dist") timestart = time.strftime("%Y%m%d_%H%M%S") runner = Runner(driver_log_filename="obj_dist/driver_" + timestart + ".log", quiet=Args.quiet) for test_py in Arg_Tests: for scenario in sorted(set(Args.scenarios)): if VlTest._prefilter_scenario(test_py, scenario): runner.one_test(py_filename=test_py, scenario=scenario) runner.wait_and_report() if Args.rerun and runner.fail_cnt and not Quitting: print('=' * 70) print('=' * 70) print("RERUN ==\n") # Avoid parallel run to ensure that isn't causing problems # If > 10 failures something more wrong and get results quickly if runner.fail_cnt < 10: forker.max_proc(1) orig_runner = runner runner = Runner(driver_log_filename="obj_dist/driver_" + timestart + "_rerun.log", quiet=False, fail1_cnt=orig_runner.fail_cnt, ok_cnt=orig_runner.ok_cnt, skip_cnt=orig_runner.skip_cnt) for ftest in orig_runner.fail_tests: # Reschedule test if ftest.rerunnable: ftest.clean(for_rerun=True) runner.one_test(py_filename=ftest.py_filename, scenario=ftest.scenario, rerun_skipping=not ftest.rerunnable) runner.wait_and_report() if runner.fail_cnt: sys.exit(10) ###################################################################### ###################################################################### # Main if __name__ == '__main__': os.environ['PYTHONUNBUFFERED'] = "1" if ('VERILATOR_ROOT' not in os.environ) and os.path.isfile('../bin/verilator'): os.environ['VERILATOR_ROOT'] = os.getcwd() + "/.." if 'MAKE' not in os.environ: os.environ['MAKE'] = "make" if 'CXX' not in os.environ: os.environ['CXX'] = "c++" if 'TEST_REGRESS' in os.environ: sys.exit("%Error: TEST_REGRESS environment variable is already set") os.environ['TEST_REGRESS'] = os.getcwd() Start = time.time() _Parameter_Next_Level = None def sig_int(signum, env) -> None: # pylint: disable=unused-argument global Quitting if Quitting: sys.exit("\nQuitting (immediately)...") print("\nQuitting... (send another interrupt signal for immediate quit)") Quitting = True if forker: forker.kill_tree_all() signal.signal(signal.SIGINT, sig_int) #--------------------------------------------------------------------- parser = argparse.ArgumentParser( allow_abbrev=False, formatter_class=argparse.RawDescriptionHelpFormatter, description="""Run Verilator regression tests""", epilog="""driver.py invokes Verilator or another simulator on each test file. See docs/internals.rst in the distribution for more information. Copyright 2024-2025 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") parser.add_argument('--benchmark', action='store', help='enable benchmarking') parser.add_argument('--debug', action='store_const', const=9, help='enable debug') # --debugi: see _parameter() parser.add_argument('--driver-clean', action='store_true', help='clean after test passes') parser.add_argument('--fail-max', action='store', default=None, help='after specified number of failures, skip remaining tests') parser.add_argument('--gdb', action='store_true', help='run Verilator executable with gdb') parser.add_argument('--gdbbt', action='store_true', help='run Verilated executable with gdb and backtrace') parser.add_argument('--gdbsim', action='store_true', help='run Verilated executable with gdb') parser.add_argument('--golden', '--gold', action='store_true', help='update golden .out files') parser.add_argument('--hashset', action='store', help='split tests based on /') parser.add_argument('--jobs', '-j', action='store', default=0, type=int, help='parallel job count (0=cpu count)') parser.add_argument('--obj-suffix', action='store', default='', help='suffix to add to obj_ test directory name') parser.add_argument('--quiet', action='store_true', help='suppress output except failures and progress') parser.add_argument('--rerun', action='store_true', help='rerun all tests that fail') parser.add_argument('--rr', action='store_true', help='run Verilator executable with rr') parser.add_argument('--rrsim', action='store_true', help='run Verilated executable with rr') parser.add_argument('--site', action='store_true', help='include VERILATOR_TEST_SITE test list') parser.add_argument('--stop', action='store_true', help='stop on the first error') parser.add_argument("--top-filename", help="override the default Verilog file name") parser.add_argument('--trace', action='store_true', help='enable simulator waveform tracing') parser.add_argument('--verbose', action='store_true', help='compile and run test in verbose mode') parser.add_argument( '--verilation', # -no-verilation undocumented debugging action='store_true', default=True, help="don't run verilator compile() phase") parser.add_argument('--verilated-debug', action='store_true', help='enable Verilated executable debug') ## Scenarios for scen, v in All_Scenarios.items(): parser.add_argument('--' + scen, dest='scenarios', action='append_const', const=scen, help='scenario-enable ' + scen) (Args, rest) = parser.parse_known_intermixed_args() Args.passdown_verilator_flags = [] Args.passdown_verilated_flags = [] for arg in rest: _parameter(arg) if Args.debug: Args.passdown_verilator_flags.append("--debug --no-skip-identical") logging.basicConfig(level=logging.DEBUG) logging.info("In driver.py, ARGV=" + ' '.join(sys.argv)) # Use Args for some global information, so gets passed to forked process Args.interactive_debugger = Args.gdb or Args.gdbsim or Args.rr or Args.rrsim if Args.jobs > 1 and Args.interactive_debugger: sys.exit("%Error: Unable to use -j > 1 with --gdb* and --rr* options") if Args.golden: os.environ['HARNESS_UPDATE_GOLDEN'] = '1' if Args.jobs == 0: Args.jobs = 1 if Args.interactive_debugger else calc_jobs() if not Args.scenarios: Args.scenarios = [] Args.scenarios.append('dist') Args.scenarios.append('vlt') Args.orig_argv_sw = [] for arg in sys.argv: if re.match(r'^-', arg) and not re.match(r'^-j$', arg): Args.orig_argv_sw.append(arg) Args.test_dirs = ["t"] if 'VERILATOR_TESTS_SITE' in os.environ: if Args.site or len(Arg_Tests) >= 1: for tdir in os.environ['VERILATOR_TESTS_SITE'].split(':'): Args.test_dirs.append(tdir) if not Arg_Tests: # Run everything uniq = {} for tdir in Args.test_dirs: # Uniquify by inode, so different paths to same place get combined stats = os.stat(tdir) if stats.st_ino not in uniq: uniq[stats.st_ino] = 1 Arg_Tests += sorted(glob.glob(tdir + "/t_*.py")) if Args.hashset: _calc_hashset() # Number of retries when reading logfiles, generally only need many # retries when system is busy running a lot of tests Args.log_retries = 10 if (len(Arg_Tests) > 3) else 2 forker = Forker(Args.jobs) Args.driver_build_jobs = None if len(Arg_Tests) >= 2 and Args.jobs >= 2: # Read supported into master process, so don't call every subprocess Capabilities.warmup_cache() # Without this tests such as t_debug_sigsegv_bt_bad.py will occasionally # block on input and cause a SIGSTOP, then a "fg" was needed to resume testing. print("== Many jobs; redirecting STDIN", file=sys.stderr) # sys.stdin = open("/dev/null", 'r', encoding="utf8") # pylint: disable=consider-using-with else: # Speed up single-test makes Args.driver_build_jobs = calc_jobs() run_them() verilator-5.042/test_regress/input.vc0000644000542200017500000000007015101701376020311 0ustar mahmoudyfreeshell +librescan +notimingchecks +libext+.v -y t +incdir+t verilator-5.042/test_regress/Makefile0000644000542200017500000001003415101701376020261 0ustar mahmoudyfreeshell#***************************************************************************** # # DESCRIPTION: Verilator Example: Makefile for inside source directory # # This calls the object directory makefile. That allows the objects to # be placed in the "current directory" which simplifies the Makefile. # # Copyright 2003-2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # #****************************************************************************/ default: test # This must point to the root of the VERILATOR kit VERILATOR_ROOT ?= $(shell pwd)/.. export VERILATOR_ROOT # Pick up PERL and other variable settings include $(VERILATOR_ROOT)/include/verilated.mk ###################################################################### ifneq ($(VCS_HOME),) #Default to off, even with vcs; not all tests are ensured to be working #PRODUCTS += --vcs endif ifneq ($(NC_ROOT),) #Default to off, even with vcs; not all tests are ensured to be working #PRODUCTS += --nc endif # Run tests in parallel. ifeq ($(CFG_WITH_LONGTESTS),yes) DRIVER_FLAGS ?= -j 0 --quiet --rerun endif .SUFFIXES: ###################################################################### SCENARIOS ?= --vlt --vltmt --dist DRIVER_HASHSET ?= .PHONY: test test: $(PYTHON3) driver.py $(DRIVER_FLAGS) $(SCENARIOS) $(DRIVER_HASHSET) ###################################################################### vcs: $(PYTHON3) driver.py $(DRIVER_FLAGS) --vcs --stop ###################################################################### nc: $(PYTHON3) driver.py $(DRIVER_FLAGS) --nc --stop ###################################################################### vlt: $(PYTHON3) driver.py $(DRIVER_FLAGS) --vlt --stop vltmt: $(PYTHON3) driver.py $(DRIVER_FLAGS) --vltmt --stop ###################################################################### random: $(PYTHON3) driver.py $(DRIVER_FLAGS) --optimize : --stop random_forever: while ( VERILATOR_NO_DEBUG=1 CPPFLAGS_ADD=-Wno-error $(MAKE) random ) ; do \ echo ; \ done ####################################################################### # Informational - used by some tests print-cxx-version: $(CXX) --version ###################################################################### maintainer-copy:: clean mostlyclean distclean maintainer-clean:: -rm -rf obj_* simv* simx* csrc cov_work INCA_libs *.log *.key logs vc_hdrs.h -rm -rf t/obj_* t/__pycache__ distclean:: -rm -rf snapshot ###################################################################### # Generated code snapshot and diff for tests # Can be overridden for multiple snapshots TEST_SNAP_DIR ?= snapshot # Command to diff directories TEST_DIFF_TOOL ?= $(if $(shell which icdiff), icdiff -N -r, diff -r) TEST_SNAP_IGNORE := \ *.status *.log *.dat *.d *.o *.a *.so *stats*.txt *.html *.includecache \ *.out *.fst *.fst.vcd *.tree *.tree*.json *.dot *.csv *.xml *.hash \ *.cmake gmon.out.* CMakeFiles profile_exec.vcd *line-coverage*.txt \ profile.vlt *linkdot.txt *linkcells.txt *.log.sort *.vpp *.sarif \ t_flag_debugi9 t_flag_decorations_node t_flag_runtime_debug t_mod_empty \ t_pgo_threads t_pgo_threads_hier t_trace_ub_misaligned_address \ define TEST_SNAP_template mkdir -p $(TEST_SNAP_DIR) rm -rf $(TEST_SNAP_DIR)/obj_$(1) cp -r obj_$(1) $(TEST_SNAP_DIR)/ find $(TEST_SNAP_DIR)/obj_$(1) \( $(TEST_SNAP_IGNORE:%=-name "%" -o) \ -type f -executable \) -prune | xargs rm -r endef .PHONY: test-snap test-snap: $(call TEST_SNAP_template,vlt) $(call TEST_SNAP_template,vltmt) $(call TEST_SNAP_template,dist) .PHONY: impl-test-diff impl-test-diff: $(TEST_DIFF_TOOL) $(TEST_SNAP_DIR)/obj_vlt obj_vlt || true $(TEST_DIFF_TOOL) $(TEST_SNAP_DIR)/obj_vltmt obj_vltmt || true $(TEST_DIFF_TOOL) $(TEST_SNAP_DIR)/obj_dist obj_dist || true .PHONY: test-diff test-diff: $(MAKE) impl-test-diff | grep -v "Only in obj_" \ | $$(git config --default less --global --get core.pager) verilator-5.042/test_regress/input.xsim.vc0000644000542200017500000000014015101701376021266 0ustar mahmoudyfreeshell --sourcelibext .v --sourcelibdir t --sourcelibdir obj_dir/ --include t --include obj_dir/ verilator-5.042/test_regress/.gitignore0000644000542200017500000000022415101701376020611 0ustar mahmoudyfreeshell*.old obj_dir obj_* vcs.key csrc cov_work simv* simx* *.log *.key ncverilog.* INCA_libs logs transcript .vcsmx_rebuild vc_hdrs.h xsim.*/ *.jou *.pb verilator-5.042/test_regress/CMakeLists.txt0000644000542200017500000000707515101701376021374 0ustar mahmoudyfreeshell###################################################################### # # DESCRIPTION: CMake script for regression tests # # This CMake file is meant to be consumed by regression tests. # # Copyright 2003-2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ###################################################################### cmake_minimum_required(VERSION 3.12) cmake_policy(SET CMP0074 NEW) set(TEST_REQUIRED_VARS NAME CSOURCES OPT_FAST OPT_GLOBAL VERILATOR_ROOT VERILATOR_ARGS VERILATOR_SOURCES SYSTEMC VERBOSE VERILATION ) foreach(var ${TEST_REQUIRED_VARS}) if(NOT DEFINED TEST_${var}) message( FATAL_ERROR "TEST_${var} not defined. This CMakeLists.txt file is meant to be run by driver.py." ) endif() endforeach() project("${TEST_NAME}") if(TEST_VERBOSE) add_definitions(-DTEST_VERBOSE=1) endif() separate_arguments(TEST_VERILATOR_ARGS UNIX_COMMAND "${TEST_VERILATOR_ARGS}") # filter out empty arguments list(FILTER TEST_VERILATOR_ARGS EXCLUDE REGEX "$^") set(TEST_PREFIX ${TEST_NAME}) # If --ARG is present, set OUT = function(getarg LST ARG OUT) list(FIND ${LST} ${ARG} _INDEX) if(NOT _INDEX EQUAL -1) list(REMOVE_AT ${LST} ${_INDEX}) list(GET ${LST} ${_INDEX} VAL) set(${OUT} ${VAL} PARENT_SCOPE) endif() endfunction() # Normalise -- to - string( REGEX REPLACE "(^|;)--" "\\1-" TEST_VERILATOR_ARGS_NORM "${TEST_VERILATOR_ARGS}" ) getarg(TEST_VERILATOR_ARGS_NORM "-prefix" TEST_PREFIX) getarg(TEST_VERILATOR_ARGS_NORM "-threads" TEST_THREADS) getarg(TEST_VERILATOR_ARGS_NORM "-trace-threads" TEST_TRACE_THREADS) # Strip unwanted args with 1 parameter string( REGEX REPLACE "(^|;)--?(Mdir|make|prefix|threads|trace-threads);[^;]*" "" TEST_VERILATOR_ARGS "${TEST_VERILATOR_ARGS}" ) # Strip unwanted args string( REGEX REPLACE "(^|;)--?(sc|cc)" "" TEST_VERILATOR_ARGS "${TEST_VERILATOR_ARGS}" ) separate_arguments( TEST_VERILATOR_SOURCES UNIX_COMMAND "${TEST_VERILATOR_SOURCES}" ) # filter out empty sources list(FILTER TEST_VERILATOR_SOURCES EXCLUDE REGEX "$^") find_package(verilator REQUIRED HINTS ${TEST_VERILATOR_ROOT}) set(verilate_ARGS MAIN) if(TEST_PREFIX) list(APPEND verilate_ARGS PREFIX ${TEST_PREFIX}) endif() if(TEST_OPT_FAST) list(APPEND verilate_ARGS OPT_FAST ${TEST_OPT_FAST}) endif() if(TEST_OPT_GLOBAL) list(APPEND verilate_ARGS OPT_GLOBAL ${TEST_OPT_GLOBAL}) endif() if(TEST_THREADS) list(APPEND verilate_ARGS THREADS ${TEST_THREADS}) endif() if(TEST_TRACE_THREADS) list(APPEND verilate_ARGS TRACE_THREADS ${TEST_TRACE_THREADS}) endif() if(TEST_SYSTEMC) list(APPEND verilate_ARGS SYSTEMC) endif() set(TARGET_NAME "V${TEST_NAME}") add_executable(${TARGET_NAME} ${TEST_CSOURCES}) if(TEST_VERILATION) verilate(${TARGET_NAME} ${verilate_ARGS} VERILATOR_ARGS ${TEST_VERILATOR_ARGS} DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} SOURCES ${TEST_VERILATOR_SOURCES} ) endif() if(TEST_SYSTEMC) verilator_link_systemc("${TARGET_NAME}") endif() string(TOUPPER "${TEST_NAME}" TEST_NAME_UC) target_compile_definitions( ${TARGET_NAME} PRIVATE "TEST_OBJ_DIR=${CMAKE_CURRENT_BINARY_DIR}" "VM_PREFIX=${TEST_PREFIX}" "VM_PREFIX_INCLUDE=<${TEST_PREFIX}.h>" "${TEST_NAME_UC}" ) verilator-5.042/.devcontainer/0000755000542200017500000000000015101701376016651 5ustar mahmoudyfreeshellverilator-5.042/.devcontainer/devcontainer.json0000644000542200017500000000020715101701376022224 0ustar mahmoudyfreeshell{ "name": "Verilator Build Environment", "build": { "dockerfile": "../ci/docker/buildenv/Dockerfile" } } verilator-5.042/Makefile.in0000644000542200017500000006466315101701376016176 0ustar mahmoudyfreeshell#***************************************************************************** # DESCRIPTION: Verilator top level: Makefile pre-configure version # # This file is part of Verilator. # # Code available from: https://verilator.org # #***************************************************************************** # # Copyright 2003-2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # #****************************************************************************/ # # make all to compile and build Verilator. # make install to install it. # make TAGS to update tags tables. # # make clean or make mostlyclean # Delete all files from the current directory that are normally # created by building the program. Don't delete the files that # record the configuration. Also preserve files that could be made # by building, but normally aren't because the distribution comes # with them. # # make distclean # Delete all files from the current directory that are created by # configuring or building the program. If you have unpacked the # source and built the program without creating any other files, # `make distclean' should leave only the files that were in the # distribution. # # make maintainer-clean # Delete everything from the current directory that can be # reconstructed with this Makefile. This typically includes # everything deleted by distclean, plus more: C source files # produced by Bison, tags tables, info files, and so on. #### Start of system configuration section. #### srcdir = @srcdir@ VPATH = @srcdir@ HOST = @HOST@ EXEEXT = @EXEEXT@ DOXYGEN = doxygen INSTALL = @INSTALL@ INSTALL_PROGRAM = @INSTALL_PROGRAM@ INSTALL_DATA = @INSTALL_DATA@ MAKEINFO = makeinfo POD2TEXT = pod2text PYTHON3 = @PYTHON3@ MKINSTALLDIRS = $(SHELL) $(srcdir)/src/mkinstalldirs # Version (for docs/guide/conf.py) PACKAGE_VERSION_NUMBER = @PACKAGE_VERSION_NUMBER@ # Destination prefix for RPMs DESTDIR = #### Don't edit: You're much better using configure switches to set these prefix = @prefix@ exec_prefix = @exec_prefix@ # Directory in which to install scripts. bindir = @bindir@ # Directory in which to install manpages. mandir = @mandir@ # Directory in which to install library files. datadir = @datadir@ # Directory in which to install documentation info files. infodir = @infodir@ # Directory in which to install package-specific files # Generally ${prefix}/share/verilator pkgdatadir = @pkgdatadir@ # Directory in which to install pkgconfig file # Generally ${prefix}/share/pkgconfig pkgconfigdir = @pkgconfigdir@ # Directory in which to install data across multiple architectures datarootdir = @datarootdir@ # Compile options CFG_WITH_CCWARN = @CFG_WITH_CCWARN@ CFG_WITH_DEFENV = @CFG_WITH_DEFENV@ CFG_WITH_DEV_GCOV = @CFG_WITH_DEV_GCOV@ CFG_WITH_LONGTESTS = @CFG_WITH_LONGTESTS@ CFG_WITH_SOLVER = @CFG_WITH_SOLVER@ PACKAGE_VERSION = @PACKAGE_VERSION@ #### End of system configuration section. #### ###################################################################### # Main build targets .SUFFIXES: SHELL = /bin/sh SUBDIRS = docs src test_regress \ examples/cmake_hello_c \ examples/cmake_hello_sc \ examples/cmake_tracing_c \ examples/cmake_tracing_sc \ examples/cmake_protect_lib \ examples/make_hello_binary \ examples/make_hello_c \ examples/make_hello_sc \ examples/make_tracing_c \ examples/make_tracing_sc \ examples/make_protect_lib \ examples/json_py \ INFOS = verilator.html verilator.pdf INFOS_OLD = README README.html README.pdf EXAMPLES_FIRST = \ examples/make_hello_c \ examples/make_hello_sc \ EXAMPLES = $(EXAMPLES_FIRST) $(filter-out $(EXAMPLES_FIRST), $(sort $(wildcard examples/*))) # See uninstall also - don't put wildcards in this variable, it might uninstall other stuff # No verilator_ccache_report.1, verilator_difftree.1 as those are not bin/ installed VL_INST_MAN_FILES = \ verilator.1 \ verilator_coverage.1 \ verilator_gantt.1 \ verilator_profcfunc.1 \ default: all all: all_nomsg msg_test all_nomsg: verilator_exe $(VL_INST_MAN_FILES) .PHONY: verilator_exe .PHONY: verilator_bin$(EXEEXT) .PHONY: verilator_bin_dbg$(EXEEXT) .PHONY: verilator_coverage_bin_dbg$(EXEEXT) verilator_exe verilator_bin$(EXEEXT) verilator_bin_dbg$(EXEEXT) verilator_coverage_bin_dbg$(EXEEXT): @echo ------------------------------------------------------------ @echo "making verilator in src" $(MAKE) -C src $(OBJCACHE_JOBS) ###################################################################### # Tests .PHONY: msg_test msg_test: all_nomsg @echo "Build complete!" @echo @echo "Now type 'make test' to test." @echo .PHONY: test ifeq ($(CFG_WITH_LONGTESTS),yes) # Local... Else don't burden users test: smoke-test test_regress # examples is part of test_regress's test_regress/t/t_a2_examples.py # (because that allows it to run in parallel with other test_regress's) else test: smoke-test examples endif @echo "Tests passed!" @echo @echo "Now type 'make install' to install." @echo "Or type 'make' inside an examples subdirectory." @echo smoke-test: all_nomsg test_regress/t/t_a1_first_cc.py test_regress/t/t_a2_first_sc.py test_regress: all_nomsg $(MAKE) -C test_regress .PHONY: test-snap test-diff test-snap test-diff: $(MAKE) -C test_regress $@ examples: all_nomsg for p in $(EXAMPLES) ; do \ $(MAKE) -C $$p VERILATOR_ROOT=`pwd` || exit 10; \ done ###################################################################### # Docs .PHONY: docs docs: info $(VL_INST_MAN_FILES) info: $(INFOS) verilator.1: ${srcdir}/bin/verilator pod2man $< $@ verilator_coverage.1: ${srcdir}/bin/verilator_coverage pod2man $< $@ %.1: ${srcdir}/bin/% help2man --no-info --no-discard-stderr --version-string=- \ -n "$(shell $< --help | head -n 3 | tail -n 1)" $< -o $@ .PHONY: verilator.html verilator.html: $(MAKE) -C docs html # PDF needs DIST variables; but having configure.ac as dependency isn't detected .PHONY: verilator.pdf verilator.pdf: Makefile $(MAKE) -C docs verilator.pdf TAGFILES = ${srcdir}/*/*.cpp ${srcdir}/*/*.h ${srcdir}/*/*.in \ ${srcdir}/*.in ${srcdir}/*.pod TAGS: $(TAGFILES) etags $(TAGFILES) .PHONY: doxygen doxygen: $(MAKE) -C docs doxygen .PHONY: spelling spelling: $(MAKE) -C docs spelling ###################################################################### # Install # Public executables intended to be invoked directly by the user # Don't put wildcards in these variables, it might cause an uninstall of other stuff VL_INST_PUBLIC_SCRIPT_FILES = \ verilator \ verilator_coverage \ verilator_gantt \ verilator_profcfunc \ VL_INST_PUBLIC_BIN_FILES = \ verilator_bin$(EXEEXT) \ verilator_bin_dbg$(EXEEXT) \ verilator_coverage_bin_dbg$(EXEEXT) \ # Private executabels intended to be invoked by internals # Don't put wildcards in these variables, it might cause an uninstall of other stuff VL_INST_PRIVATE_SCRIPT_FILES = \ verilator_ccache_report \ verilator_includer \ VL_INST_INC_BLDDIR_FILES = \ include/verilated_config.h \ include/verilated.mk \ # Files under srcdir, instead of build time VL_INST_INC_SRCDIR_FILES = \ include/*.[chv]* \ include/*.vlt \ include/*.sv \ include/gtkwave/*.[chv]* \ include/vltstd/*.[chv]* \ VL_INST_DATA_SRCDIR_FILES = \ examples/*/*.[chv]* \ examples/*/CMakeLists.txt \ examples/*/Makefile* \ examples/*/vl_* \ mkbindirs: $(MKINSTALLDIRS) $(DESTDIR)$(pkgdatadir)/bin $(MKINSTALLDIRS) $(DESTDIR)$(bindir) installbin: | mkbindirs cd $(srcdir)/bin; \ for p in $(VL_INST_PUBLIC_SCRIPT_FILES) ; do \ $(INSTALL_PROGRAM) $$p $(DESTDIR)$(bindir)/$$p; \ done perl -p -i -e 'use File::Spec;' \ -e' $$path = File::Spec->abs2rel("$(realpath $(DESTDIR)$(pkgdatadir))", "$(realpath $(DESTDIR)$(bindir))");' \ -e 's/my \$$verilator_pkgdatadir_relpath = .*/my \$$verilator_pkgdatadir_relpath = "$$path";/g' \ -- "$(DESTDIR)/$(bindir)/verilator" cd bin; \ for p in $(VL_INST_PUBLIC_BIN_FILES) ; do \ $(INSTALL_PROGRAM) $$p $(DESTDIR)$(bindir)/$$p; \ done cd $(srcdir)/bin; \ for p in $(VL_INST_PRIVATE_SCRIPT_FILES) ; do \ $(INSTALL_PROGRAM) $$p $(DESTDIR)$(pkgdatadir)/bin/$$p; \ done installredirect: installbin | mkbindirs cp ${srcdir}/bin/redirect ${srcdir}/bin/redirect.tmp perl -p -i -e 'use File::Spec;' \ -e' $$path = File::Spec->abs2rel("$(realpath $(DESTDIR)$(bindir))", "$(realpath $(DESTDIR)$(pkgdatadir)/bin)");' \ -e 's/RELPATH.*/"$$path";/g' -- "${srcdir}/bin/redirect.tmp" cd $(srcdir)/bin; \ for p in $(VL_INST_PUBLIC_SCRIPT_FILES) $(VL_INST_PUBLIC_BIN_FILES) ; do \ $(INSTALL_PROGRAM) redirect.tmp $(DESTDIR)$(pkgdatadir)/bin/$$p; \ done rm ${srcdir}/bin/redirect.tmp # Man files can either be part of the original kit, or built in current directory # So important we use $^ so VPATH is searched installman: $(VL_INST_MAN_FILES) $(MKINSTALLDIRS) $(DESTDIR)$(mandir)/man1 for p in $^ ; do \ $(INSTALL_DATA) $$p $(DESTDIR)$(mandir)/man1/$$p; \ done installdata: $(MKINSTALLDIRS) $(DESTDIR)$(pkgdatadir)/include/gtkwave $(MKINSTALLDIRS) $(DESTDIR)$(pkgdatadir)/include/vltstd for p in $(VL_INST_INC_BLDDIR_FILES) ; do \ $(INSTALL_DATA) $$p $(DESTDIR)$(pkgdatadir)/$$p; \ done cd $(srcdir) \ ; for p in $(VL_INST_INC_SRCDIR_FILES) ; do \ $(INSTALL_DATA) $$p $(DESTDIR)$(pkgdatadir)/$$p; \ done $(MKINSTALLDIRS) $(DESTDIR)$(pkgdatadir)/examples/make_hello_binary $(MKINSTALLDIRS) $(DESTDIR)$(pkgdatadir)/examples/make_hello_c $(MKINSTALLDIRS) $(DESTDIR)$(pkgdatadir)/examples/make_hello_sc $(MKINSTALLDIRS) $(DESTDIR)$(pkgdatadir)/examples/make_tracing_c $(MKINSTALLDIRS) $(DESTDIR)$(pkgdatadir)/examples/make_tracing_sc $(MKINSTALLDIRS) $(DESTDIR)$(pkgdatadir)/examples/make_protect_lib $(MKINSTALLDIRS) $(DESTDIR)$(pkgdatadir)/examples/cmake_hello_c $(MKINSTALLDIRS) $(DESTDIR)$(pkgdatadir)/examples/cmake_hello_sc $(MKINSTALLDIRS) $(DESTDIR)$(pkgdatadir)/examples/cmake_tracing_c $(MKINSTALLDIRS) $(DESTDIR)$(pkgdatadir)/examples/cmake_tracing_sc $(MKINSTALLDIRS) $(DESTDIR)$(pkgdatadir)/examples/cmake_protect_lib $(MKINSTALLDIRS) $(DESTDIR)$(pkgdatadir)/examples/json_py cd $(srcdir) \ ; for p in $(VL_INST_DATA_SRCDIR_FILES) ; do \ $(INSTALL_DATA) $$p $(DESTDIR)$(pkgdatadir)/$$p; \ done $(MKINSTALLDIRS) $(DESTDIR)$(pkgconfigdir) $(INSTALL_DATA) verilator.pc $(DESTDIR)$(pkgconfigdir) $(INSTALL_DATA) verilator-config.cmake $(DESTDIR)$(pkgdatadir) $(INSTALL_DATA) verilator-config-version.cmake $(DESTDIR)$(pkgdatadir) # We don't trust rm -rf, so rmdir instead as it will fail if user put in other files uninstall: -cd $(DESTDIR)$(bindir) && rm -f $(VL_INST_PUBLIC_SCRIPT_FILES) -cd $(DESTDIR)$(bindir) && rm -f $(VL_INST_PUBLIC_BIN_FILES) -cd $(DESTDIR)$(pkgdatadir)/bin && rm -f $(VL_INST_PUBLIC_SCRIPT_FILES) -cd $(DESTDIR)$(pkgdatadir)/bin && rm -f $(VL_INST_PUBLIC_BIN_FILES) -cd $(DESTDIR)$(pkgdatadir)/bin && rm -f $(VL_INST_PRIVATE_SCRIPT_FILES) -cd $(DESTDIR)$(mandir)/man1 && rm -f $(VL_INST_MAN_FILES) -cd $(DESTDIR)$(pkgdatadir) && rm -f $(VL_INST_INC_BLDDIR_FILES) -cd $(DESTDIR)$(pkgdatadir) && rm -f $(VL_INST_INC_SRCDIR_FILES) -cd $(DESTDIR)$(pkgdatadir) && rm -f $(VL_INST_DATA_SRCDIR_FILES) -rm $(DESTDIR)$(pkgconfigdir)/verilator.pc -rm $(DESTDIR)$(pkgdatadir)/verilator-config.cmake -rm $(DESTDIR)$(pkgdatadir)/verilator-config-version.cmake -rmdir $(DESTDIR)$(pkgdatadir)/bin -rmdir $(DESTDIR)$(pkgdatadir)/include/gtkwave -rmdir $(DESTDIR)$(pkgdatadir)/include/vltstd -rmdir $(DESTDIR)$(pkgdatadir)/include -rmdir $(DESTDIR)$(pkgdatadir)/examples/make_hello_binary -rmdir $(DESTDIR)$(pkgdatadir)/examples/make_hello_c -rmdir $(DESTDIR)$(pkgdatadir)/examples/make_hello_sc -rmdir $(DESTDIR)$(pkgdatadir)/examples/make_tracing_c -rmdir $(DESTDIR)$(pkgdatadir)/examples/make_tracing_sc -rmdir $(DESTDIR)$(pkgdatadir)/examples/make_protect_lib -rmdir $(DESTDIR)$(pkgdatadir)/examples/cmake_hello_c -rmdir $(DESTDIR)$(pkgdatadir)/examples/cmake_hello_sc -rmdir $(DESTDIR)$(pkgdatadir)/examples/cmake_tracing_c -rmdir $(DESTDIR)$(pkgdatadir)/examples/cmake_tracing_sc -rmdir $(DESTDIR)$(pkgdatadir)/examples/cmake_protect_lib -rmdir $(DESTDIR)$(pkgdatadir)/examples/json_py -rmdir $(DESTDIR)$(pkgdatadir)/examples -rmdir $(DESTDIR)$(pkgdatadir) -rmdir $(DESTDIR)$(pkgconfigdir) install: all_nomsg install-all install-all: installbin installredirect installman installdata install-msg install-here: installman info install-msg: @echo @echo "Installed binaries to $(DESTDIR)$(bindir)/verilator" @echo "Installed man to $(DESTDIR)$(mandir)/man1" @echo "Installed examples to $(DESTDIR)$(pkgdatadir)/examples" @echo @echo "For documentation see 'man verilator' or 'verilator --help'" @echo "For forums and to report bugs see https://verilator.org" @echo ###################################################################### # Format/Lint CPPCHECK_VERILATOR_CPP = $(wildcard $(srcdir)/src/V3*.cpp $(srcdir)/src/Verilator*.cpp) CPPCHECK_RUNTIME_CPP = $(wildcard $(srcdir)/include/*.cpp) CPPCHECK_VLC_CPP = $(wildcard $(srcdir)/src/Vlc*.cpp) CPPCHECK_EXAMPLES_CPP = $(wildcard $(srcdir)/examples/*/*.cpp) CHECK_CPP = $(CPPCHECK_VERILATOR_CPP) $(CPPCHECK_RUNTIME_CPP) $(CPPCHECK_VLC_CPP) $(CPPCHECK_EXAMPLES_CPP) CHECK_H = $(wildcard \ $(srcdir)/include/*.h \ $(srcdir)/src/*.h ) CHECK_YL = $(wildcard \ $(srcdir)/src/*.y \ $(srcdir)/src/*.l ) CPPCHECK = cppcheck CPPCHECK_JOBS = $(shell nproc) CPPCHECK_CACHE = $(srcdir)/src/obj_dbg/cppcheck-cache CPPCHECK_FLAGS = --enable=all CPPCHECK_FLAGS += --inline-suppr CPPCHECK_FLAGS += --suppressions-list=$(srcdir)/src/cppcheck-suppressions.txt CPPCHECK_FLAGS += --cppcheck-build-dir=$(CPPCHECK_CACHE) CPPCHECK_FLAGS += -DVL_DEBUG=1 -DVL_CPPCHECK=1 -DINFILTER_PIPE=1 -D__GNUC__=1 CPPCHECK_FLAGS += -j$(CPPCHECK_JOBS) CPPCHECK_INC = -I$(srcdir)/include CPPCHECK_INC += -I$(srcdir)/include/gtkwave CPPCHECK_INC += -I$(srcdir)/include/vltstd CPPCHECK_INC += -I$(srcdir)/src/obj_dbg CPPCHECK_INC += -I$(srcdir)/src $(CPPCHECK_CACHE): $(CHECK_CPP) $(CHECK_H) $(CHECK_YL) /bin/rm -rf $@ /bin/mkdir -p $@ cppcheck-verilator: | $(CPPCHECK_CACHE) $(CPPCHECK) $(CPPCHECK_FLAGS) $(CPPCHECK_INC) $(CPPCHECK_VERILATOR_CPP) cppcheck-runtime: | $(CPPCHECK_CACHE) $(CPPCHECK) $(CPPCHECK_FLAGS) $(CPPCHECK_INC) $(CPPCHECK_RUNTIME_CPP) cppcheck-vlc: | $(CPPCHECK_CACHE) $(CPPCHECK) $(CPPCHECK_FLAGS) $(CPPCHECK_INC) $(CPPCHECK_VLC_CPP) cppcheck-examples: | $(CPPCHECK_CACHE) $(CPPCHECK) $(CPPCHECK_FLAGS) $(CPPCHECK_INC) $(CPPCHECK_EXAMPLES_CPP) cppcheck: $(MAKE) cppcheck-vlc $(MAKE) cppcheck-examples $(MAKE) cppcheck-runtime $(MAKE) cppcheck-verilator CLANGTIDY = clang-tidy CLANGTIDY_FLAGS = -config='' \ -header-filter='.*' \ -checks='-fuchsia-*,-cppcoreguidelines-avoid-c-arrays,-cppcoreguidelines-init-variables,-cppcoreguidelines-avoid-goto,-modernize-avoid-c-arrays,-readability-magic-numbers,-readability-simplify-boolean-expr,-cppcoreguidelines-macro-usage' \ CLANGTIDY_DEP = $(subst .cpp,.cpp.tidy,$(CHECK_CPP)) CLANGTIDY_DEFS = -DVL_DEBUG=1 -DVL_CPPCHECK=1 clang-tidy: $(CLANGTIDY_DEP) %.cpp.tidy: %.cpp $(CLANGTIDY) $(CLANGTIDY_FLAGS) $< -- $(CLANGTIDY_DEFS) $(CPPCHECK_INC) | 2>&1 tee $@ %.h.tidy: %.h $(CLANGTIDY) $(CLANGTIDY_FLAGS) $< -- $(CLANGTIDY_DEFS) $(CPPCHECK_INC) -x c++-header | 2>&1 tee $@ analyzer-src: -rm -rf src/obj_dbg scan-build $(MAKE) -k verilator_coverage_bin_dbg$(EXEEXT) verilator_bin_dbg$(EXEEXT) analyzer-include: -rm -rf examples/*/obj* scan-build $(MAKE) -k examples format: $(MAKE) -j 5 format-c format-cmake format-exec format-py CLANGFORMAT = clang-format-18 CLANGFORMAT_FLAGS = -i CLANGFORMAT_FILES = $(CHECK_CPP) $(CHECK_H) $(CHECK_YL) test_regress/t/*.c* test_regress/t/*.h format-c clang-format: $(CLANGFORMAT) --version @$(CLANGFORMAT) --version | fgrep 'version 18' > /dev/null \ || echo "*** You are not using clang-format-18, indents may differ from master's ***" $(CLANGFORMAT) $(CLANGFORMAT_FLAGS) $(CLANGFORMAT_FILES) YAMLFIX = YAMLFIX_WHITELINES=1 YAMLFIX_LINE_LENGTH=200 YAMLFIX_preserve_quotes=true yamlfix yamlfix: $(YAMLFIX) . # CMake files CMAKE_FILES = \ CMakeLists.txt \ examples/*/CMakeLists.txt \ src/CMakeLists.txt \ test_regress/CMakeLists.txt \ *.cmake.in \ # Makefiles MAKE_FILES = \ Makefile*.in \ docs/Makefile* \ include/verilated.mk.in \ examples/*/Makefile* \ src/Makefile*.in \ test_regress/Makefile* \ # Python programs, subject to format and lint PY_PROGRAMS = \ bin/verilator_ccache_report \ bin/verilator_difftree \ bin/verilator_gantt \ bin/verilator_includer \ bin/verilator_profcfunc \ examples/json_py/vl_file_copy \ examples/json_py/vl_hier_graph \ docs/guide/conf.py \ docs/bin/vl_sphinx_extract \ docs/bin/vl_sphinx_fix \ src/astgen \ src/bisonpre \ src/config_rev \ src/flexfix \ src/vlcovgen \ src/.gdbinit.py \ test_regress/*.py \ test_regress/t/*.pf \ nodist/clang_check_attributes \ nodist/dot_importer \ nodist/fuzzer/actual_fail \ nodist/fuzzer/generate_dictionary \ nodist/install_test \ nodist/log_changes \ # Python files, subject to format but not lint PY_FILES = \ $(PY_PROGRAMS) \ test_regress/t/*.py \ # Python files, test_regress tests PY_TEST_FILES = test_regress/t/*.py YAPF = yapf3 YAPF_FLAGS = -i --parallel format-py yapf: $(YAPF) --version $(YAPF) $(YAPF_FLAGS) $(PY_FILES) GERSEMI = gersemi GERSEMI_FLAGS = -i --no-warn-about-unknown-commands format-cmake: $(GERSEMI) $(GERSEMI_FLAGS) $(CMAKE_FILES) MBAKE = mbake MBAKE_FLAGS = format --config ./.bake.toml format-make: $(MBAKE) $(MBAKE_FLAGS) $(MAKE_FILES) format-yaml: yamlfix MYPY = mypy MYPY_FLAGS = --strict --no-error-summary PYLINT = pylint PYLINT_FLAGS = --recursive=n --score=n --disable=R0801 PYLINT_TEST_FLAGS = $(PYLINT_FLAGS) --disable=C0103,C0114,C0116,C0209,C0411,C0413,C0301,R0801,R0912,R0915,R0916,R1702,W0511,W0621 RUFF = ruff RUFF_FLAGS = check --ignore=E402,E501,E701 # "make -k" so can see all tool result errors lint-py: $(MAKE) -k lint-py-mypy lint-py-mypy-none lint-py-pylint lint-py-pylint-tests lint-py-ruff lint-py-mypy: for filename in `fgrep -l '# mypy' $(PY_PROGRAMS)`; do \ echo "$(MYPY) $(MYPY_FLAGS) $$filename" ; \ $(MYPY) $(MYPY_FLAGS) $$filename ; \ done lint-py-mypy-none: @echo "mypy not checking: " `fgrep -L '# mypy' $(PY_PROGRAMS)` lint-py-pylint: $(PYLINT) $(PYLINT_FLAGS) $(PY_PROGRAMS) lint-py-pylint-tests: $(PYLINT) $(PYLINT_TEST_FLAGS) $(PY_TEST_FILES) | $(PYTHON3) nodist/lint_py_test_filter lint-py-ruff: $(RUFF) $(RUFF_FLAGS) $(PY_PROGRAMS) format-exec: -chmod a+x test_regress/t/*.py ###################################################################### # Configure IN_WILD := ${srcdir}/*.in ${srcdir}/*/*.in # autoheader might not change config_package.h.in, so touch it ${srcdir}/config_package.h: ${srcdir}/config_package.h.in configure cd ${srcdir} && autoheader touch $@ Makefile: Makefile.in config.status $(IN_WILD) ./config.status src/Makefile: src/Makefile.in Makefile config.status: configure ./config.status --recheck configure: configure.ac ifeq ($(CFG_WITH_CCWARN),yes) # Local... Else don't burden users autoconf --warnings=all else autoconf endif ###################################################################### # Coverage collection and reporting COVERAGE_DIR := obj_coverage ifeq ($(CFG_WITH_DEV_GCOV),yes) # Figure out base and head refs for coverage report COVERAGE_REF_BASE := $(if $(COVERAGE_BASE),$(shell git rev-parse --short $(COVERAGE_BASE))) COVERAGE_REF_HEAD := $(shell git rev-parse --short HEAD) override undefine COVERAGE_BASE # Use the above variabels instead # 'fastcov' setup FASTCOV := nodist/fastcov.py FASTCOV_OPT := -j $(shell nproc) FASTCOV_OPT += --lcov FASTCOV_OPT += --process-gcno FASTCOV_OPT += --branch-coverage FASTCOV_OPT += --dump-statistic # Files matching the following glob patterns will be excluded from coverage FASTCOV_OPT += --exclude-glob FASTCOV_OPT += '/usr/*' FASTCOV_OPT += '*examples/*' FASTCOV_OPT += '*include/gtkwave/*' FASTCOV_OPT += '*src/obj_dbg/*' FASTCOV_OPT += '*src/obj_opt/*.yy.cpp' FASTCOV_OPT += '*src/obj_opt/V3Ast*' FASTCOV_OPT += '*src/obj_opt/V3Dfg*' FASTCOV_OPT += '*src/obj_opt/V3ParseBison.c' FASTCOV_OPT += '*test_regress/*' # Lines *containing* these substrings will be excluded from *all* coverage FASTCOV_OPT += --custom-exclusion-marker FASTCOV_OPT += ASTGEN_MEMBERS FASTCOV_OPT += ERROR_RSVD_WORD FASTCOV_OPT += LCOV_EXCL_LINE FASTCOV_OPT += V3ERROR_NA FASTCOV_OPT += VL_DEFINE_DEBUG_FUNCTIONS FASTCOV_OPT += VL_FATAL FASTCOV_OPT += VL_RTTI_IMPL FASTCOV_OPT += VL_UNREACHABLE FASTCOV_OPT += v3fatalSrc # Lines *starting* with these substrings will be ecluded from *branch* coverage FASTCOV_OPT += --exclude-br-lines-starting-with FASTCOV_OPT += BROKEN_BASE_RTN FASTCOV_OPT += BROKEN_RTN FASTCOV_OPT += NUM_ASSERT FASTCOV_OPT += SELF_CHECK FASTCOV_OPT += UASSERT FASTCOV_OPT += UINFO FASTCOV_OPT += assert FASTCOV_OPT += 'if (VL_UNCOVERABLE' FASTCOV_OPT += '} else if (VL_UNCOVERABLE' # 'genhtml' setup GENHTML := genhtml GENHTML_OPT := -j $(shell nproc) GENHTML_OPT += --branch-coverage GENHTML_OPT += --demangle-cpp GENHTML_OPT += --missed GENHTML_OPT += --rc branch_coverage=1 GENHTML_OPT += --rc genhtml_hi_limit=100 GENHTML_OPT += --ignore-errors negative ifeq ($(COVERAGE_REF_BASE),) GENHTML_OPT += --header-title "Code coverage for Verilator $(shell git describe --dirty)" else GENHTML_OPT += --header-title "Patch coverage for Verilator $(COVERAGE_REF_BASE)..$(COVERAGE_REF_HEAD)$(if $(shell git status --porcelain),-dirty)" endif GENHTML_OPT += --flat GENHTML_OPT += --precision 2 GENHTML_OPT += --legend GENHTML_OPT += --show-proportion GENHTML_OPT += --filter brace,blank,range # There are loads (~20k combined), but using this seems fine on modern hardware GCNO_FILES = $(shell find . -name '*.gcno') GCDA_FILES = $(shell find . -name '*.gcda') # Combine all .gcda coverage date files into lcov .info file $(COVERAGE_DIR)/verilator.info: $(GCNO_FILES) $(GCDA_FILES) @echo "####################################################################" @echo "# fastcov: combining all .gcda files into lcov .info" @echo "####################################################################" @mkdir -p $(COVERAGE_DIR) /usr/bin/time -f "That took %E" \ $(FASTCOV) $(FASTCOV_OPT) --output $@ # Filter combined .info file for patch coverage $(COVERAGE_DIR)/verilator-patch.info: $(COVERAGE_DIR)/verilator.info @echo "####################################################################" @echo "# fastcov: Filtering for patch coverage" @echo "####################################################################" rm -f $(COVERAGE_DIR)/empty-patch git diff $(COVERAGE_REF_BASE) -- include src > $(COVERAGE_DIR)/filter.patch [ -s $(COVERAGE_DIR)/filter.patch ]] || touch $(COVERAGE_DIR)/empty-patch $(FASTCOV) -C $^ --lcov -o $@ --diff-filter $(COVERAGE_DIR)/filter.patch # Build coverage report $(COVERAGE_DIR)/report/index.html: $(COVERAGE_DIR)/verilator$(if $(COVERAGE_REF_BASE),-patch).info @echo "####################################################################" @echo "# genhtml: Generating coverage report" @echo "####################################################################" @rm -rf $(COVERAGE_DIR)/report [ -f $(COVERAGE_DIR)/empty-patch ]] || /usr/bin/time -f "That took %E" \ $(GENHTML) $(GENHTML_OPT) --output-directory $(COVERAGE_DIR)/report $^ || true @# Uncommitted changes not tracked, force rebuild on next run if patch coverage @$(if $(COVERAGE_REF_BASE),mv $(COVERAGE_DIR)/verilator-patch.info $(COVERAGE_DIR)/verilator-patch-last.info) # Convenience targets .PHONY: coverage-combine coverage-combine: $(COVERAGE_DIR)/verilator.info # Via recursive make, so the message is always printed .PHONY: coverage-report coverage-report: @$(MAKE) --no-print-directory $(COVERAGE_DIR)/report/index.html || true @if [ -f $(COVERAGE_DIR)/report/index.html ]; then \ echo "####################################################################"; \ echo "# Coverage report is at: $(COVERAGE_DIR)/report/index.html"; \ echo "# Use 'make coverage-view' to open it in your default browser"; \ echo "####################################################################"; \ elif [ -f $(COVERAGE_DIR)/empty-patch ]; then \ echo "####################################################################"; \ echo "# Patch is empty"; \ echo "####################################################################"; \ else \ echo "####################################################################"; \ echo "# Failed to create coverage report. Maybe no data, or error?"; \ echo "####################################################################"; \ false; \ fi # Open covarage report in default web browser .PHONY: coverage-view coverage-view: coverage-report @test -f $(COVERAGE_DIR)/report/index.html && open $(COVERAGE_DIR)/report/index.html || true # Deletes all coverage data files (.gcda) .PHONY: coverage-zero coverage-zero: # 'rm $(GCDA_FILES)' might fail with too many args $(FASTCOV) --zerocounters endif ###################################################################### # Clean maintainer-clean:: @echo "This command is intended for maintainers to use;" @echo "rebuilding the deleted files requires autoconf." rm -f configure clean mostlyclean distclean maintainer-clean maintainer-copy:: for dir in $(SUBDIRS); do \ echo making $@ in $$dir ; \ $(MAKE) -C $$dir $@ ; \ done clean mostlyclean distclean maintainer-clean:: rm -f $(SCRIPTS) *.tmp rm -f *.aux *.cp *.cps *.dvi *.fn *.fns *.ky *.kys *.log rm -f *.pg *.pgs *.toc *.tp *.tps *.vr *.vrs *.idx rm -f *.ev *.evs *.ov *.ovs *.cv *.cvs *.ma *.mas rm -f *.tex rm -rf examples/*/obj_dir* examples/*/logs rm -rf test_*/obj_dir rm -rf src/*.tidy include/*.tidy examples/*/*.tidy rm -rf .ruff_cache rm -rf nodist/fuzzer/dictionary rm -rf $(COVERAGE_DIR) rm -rf verilator.txt distclean maintainer-clean:: rm -f *.info* *.1 $(INFOS) $(INFOS_OLD) $(VL_INST_MAN_FILES) rm -f Makefile config.status config.cache config.log TAGS rm -f verilator_bin* verilator_coverage_bin* rm -f bin/verilator_bin* bin/verilator_coverage_bin* rm -f include/verilated.mk include/verilated_config.h ###################################################################### # Distributions DISTTITLE := Verilator $(word 1,$(PACKAGE_VERSION)) DISTNAME := verilator-$(word 1,$(PACKAGE_VERSION)) DISTDATEPRE := $(word 2,$(PACKAGE_VERSION)) DISTDATE := $(subst /,-,$(DISTDATEPRE)) DISTTAGNAME := $(subst .,_,$(subst -,_,$(DISTNAME))) tag: svnorcvs tag $(DISTTAGNAME) maintainer-diff: svnorcvs diff $(DISTTAGNAME) preexist: svnorcvs nexists $(DISTTAGNAME) maintainer-dist: preexist tag svnorcvs release $(DISTTAGNAME) verilator-5.042/verilator.pc.in0000644000542200017500000000045215101701376017053 0ustar mahmoudyfreeshellprefix=@prefix@ exec_prefix=@exec_prefix@ libdir=@libdir@ datarootdir=@datarootdir@ includedir=@pkgdatadir@/include Name: verilator Description: fast free Verilog simulator URL: https://verilator.org Version: @PACKAGE_VERSION_NUMBER@ Requires: Libs: Cflags: -I${includedir} -I${includedir}/vltstd verilator-5.042/install-sh0000644000542200017500000001271115101701376016115 0ustar mahmoudyfreeshell#! /bin/sh # # install - install a program, script, or datafile # This comes from X11R5 (mit/util/scripts/install.sh). # # Copyright 1991 by the Massachusetts Institute of Technology # # Permission to use, copy, modify, distribute, and sell this software and its # documentation for any purpose is hereby granted without fee, provided that # the above copyright notice appear in all copies and that both that # copyright notice and this permission notice appear in supporting # documentation, and that the name of M.I.T. not be used in advertising or # publicity pertaining to distribution of the software without specific, # written prior permission. M.I.T. makes no representations about the # suitability of this software for any purpose. It is provided "as is" # without express or implied warranty. # # Calling this script install-sh is preferred over install.sh, to prevent # `make' implicit rules from creating a file called install from it # when there is no Makefile. # # This script is compatible with the BSD install script, but was written # from scratch. It can only install one file at a time, a restriction # shared with many OS's install programs. # set DOITPROG to echo to test this script # Don't use :- since 4.3BSD and earlier shells don't like it. doit="${DOITPROG-}" # put in absolute paths if you don't have them in your path; or use env. vars. mvprog="${MVPROG-mv}" cpprog="${CPPROG-cp}" chmodprog="${CHMODPROG-chmod}" chownprog="${CHOWNPROG-chown}" chgrpprog="${CHGRPPROG-chgrp}" stripprog="${STRIPPROG-strip}" rmprog="${RMPROG-rm}" mkdirprog="${MKDIRPROG-mkdir}" transformbasename="" transform_arg="" instcmd="$mvprog" chmodcmd="$chmodprog 0755" chowncmd="" chgrpcmd="" stripcmd="" rmcmd="$rmprog -f" mvcmd="$mvprog" src="" dst="" dir_arg="" while [ x"$1" != x ]; do case $1 in -c) instcmd="$cpprog" shift continue;; -d) dir_arg=true shift continue;; -m) chmodcmd="$chmodprog $2" shift shift continue;; -o) chowncmd="$chownprog $2" shift shift continue;; -g) chgrpcmd="$chgrpprog $2" shift shift continue;; -s) stripcmd="$stripprog" shift continue;; -t=*) transformarg=`echo $1 | sed 's/-t=//'` shift continue;; -b=*) transformbasename=`echo $1 | sed 's/-b=//'` shift continue;; *) if [ x"$src" = x ] then src=$1 else # this colon is to work around a 386BSD /bin/sh bug : dst=$1 fi shift continue;; esac done if [ x"$src" = x ] then echo "install: no input file specified" exit 1 else true fi if [ x"$dir_arg" != x ]; then dst=$src src="" if [ -d $dst ]; then instcmd=: else instcmd=mkdir fi else # Waiting for this to be detected by the "$instcmd $src $dsttmp" command # might cause directories to be created, which would be especially bad # if $src (and thus $dsttmp) contains '*'. if [ -f $src -o -d $src ] then true else echo "install: $src does not exist" exit 1 fi if [ x"$dst" = x ] then echo "install: no destination specified" exit 1 else true fi # If destination is a directory, append the input filename; if your system # does not like double slashes in filenames, you may need to add some logic if [ -d $dst ] then dst="$dst"/`basename $src` else true fi fi ## this sed command emulates the dirname command dstdir=`echo $dst | sed -e 's,[^/]*$,,;s,/$,,;s,^$,.,'` # Make sure that the destination directory exists. # this part is taken from Noah Friedman's mkinstalldirs script # Skip lots of stat calls in the usual case. if [ ! -d "$dstdir" ]; then defaultIFS=' ' IFS="${IFS-${defaultIFS}}" oIFS="${IFS}" # Some sh's can't handle IFS=/ for some reason. IFS='%' set - `echo ${dstdir} | sed -e 's@/@%@g' -e 's@^%@/@'` IFS="${oIFS}" pathcomp='' while [ $# -ne 0 ] ; do pathcomp="${pathcomp}${1}" shift if [ ! -d "${pathcomp}" ] ; then $mkdirprog "${pathcomp}" else true fi pathcomp="${pathcomp}/" done fi if [ x"$dir_arg" != x ] then $doit $instcmd $dst && if [ x"$chowncmd" != x ]; then $doit $chowncmd $dst; else true ; fi && if [ x"$chgrpcmd" != x ]; then $doit $chgrpcmd $dst; else true ; fi && if [ x"$stripcmd" != x ]; then $doit $stripcmd $dst; else true ; fi && if [ x"$chmodcmd" != x ]; then $doit $chmodcmd $dst; else true ; fi else # If we're going to rename the final executable, determine the name now. if [ x"$transformarg" = x ] then dstfile=`basename $dst` else dstfile=`basename $dst $transformbasename | sed $transformarg`$transformbasename fi # don't allow the sed command to completely eliminate the filename if [ x"$dstfile" = x ] then dstfile=`basename $dst` else true fi # Make a temp file name in the proper directory. dsttmp=$dstdir/#inst.$$# # Move or copy the file name to the temp name $doit $instcmd $src $dsttmp && trap "rm -f ${dsttmp}" 0 && # and set any options; do chmod last to preserve setuid bits # If any of these fail, we abort the whole thing. If we want to # ignore errors from any of these, just make sure not to ignore # errors from the above "$doit $instcmd $src $dsttmp" command. if [ x"$chowncmd" != x ]; then $doit $chowncmd $dsttmp; else true;fi && if [ x"$chgrpcmd" != x ]; then $doit $chgrpcmd $dsttmp; else true;fi && if [ x"$stripcmd" != x ]; then $doit $stripcmd $dsttmp; else true;fi && if [ x"$chmodcmd" != x ]; then $doit $chmodcmd $dsttmp; else true;fi && # Now rename the file to the real destination. $doit $rmcmd -f $dstdir/$dstfile && $doit $mvcmd $dsttmp $dstdir/$dstfile fi && exit 0 verilator-5.042/.pre-commit-hooks.yaml0000644000542200017500000000036015101701376020250 0ustar mahmoudyfreeshell--- - id: verilator name: verilator-lint description: Runs verilator Docker image to lint (System) Verilog designs args: [--lint-only] language: docker_image entry: verilator/verilator:latest types_or: [verilog, system-verilog] verilator-5.042/bin/0000755000542200017500000000000015101701376014662 5ustar mahmoudyfreeshellverilator-5.042/bin/verilator_gantt0000755000542200017500000006226015101701376020022 0ustar mahmoudyfreeshell#!/usr/bin/env python3 # pylint: disable=C0103,C0114,C0116,C0209,C0301,R0914,R0912,R0915,W0511,W0603,eval-used ###################################################################### import argparse import bisect import collections import math import re import statistics from collections import OrderedDict # from pprint import pprint Sections = OrderedDict() LongestVcdStrValueLength = 0 Threads = collections.defaultdict(lambda: []) # List of records per thread id Mtasks = collections.defaultdict(lambda: {'elapsed': 0, 'end': 0}) Cpus = collections.defaultdict(lambda: {'mtask_time': 0}) Global = { 'args': {}, 'cpuinfo': collections.defaultdict(lambda: {}), 'info': { 'numa': 'no data' }, 'stats': {} } ElapsedTime = None # total elapsed time ExecGraphTime = 0 # total elapsed time executing an exec graph WaitingTime = 0 # total elapsed time waiting for mtasks ExecGraphIntervals = [] # list of (start, end) pairs ThreadScheduleWaitIntervals = [] # list of (start, tick, ecpu) pairs ###################################################################### def read_data(filename: str) -> None: with open(filename, "r", encoding="utf8") as fh: re_thread = re.compile(r'^VLPROFTHREAD (\d+)$') re_record = re.compile(r'^VLPROFEXEC (\S+) (\d+)(.*)$') # The hierBlock argument is optional re_payload_mtaskBegin = re.compile( r'id (\d+) predictStart (\d+) cpu (\d+)(?: hierBlock)?\s*(\w+)?') re_payload_mtaskEnd = re.compile(r'predictCost (\d+)') re_payload_wait = re.compile(r'cpu (\d+)') re_arg1 = re.compile(r'VLPROF arg\s+(\S+)\+([0-9.]*)\s*') re_arg2 = re.compile(r'VLPROF arg\s+(\S+)\s+([0-9.]*)\s*$') re_info = re.compile(r'VLPROF info\s+(\S+)\s+(.*)$') re_stat = re.compile(r'VLPROF stat\s+(\S+)\s+(\S+)') re_proc_cpu = re.compile(r'VLPROFPROC processor\s*:\s*(\d+)\s*$') re_proc_dat = re.compile(r'VLPROFPROC ([a-z_ ]+)\s*:\s*(.*)$') cpu = None thread = 0 thread_last_ecpu = None global LongestVcdStrValueLength global ExecGraphTime global WaitingTime ExecGraphStack = [] SectionStack = [] MtasksStack = [] ThreadScheduleWait = collections.defaultdict(list) for line in fh: recordMatch = re_record.match(line) if recordMatch: kind, tick, payload = recordMatch.groups() tick = int(tick) payload = payload.strip() if kind == "SECTION_PUSH": LongestVcdStrValueLength = max(LongestVcdStrValueLength, len(payload)) SectionStack.append(payload) Sections[thread].append((tick, tuple(SectionStack))) elif kind == "SECTION_POP": assert SectionStack, "SECTION_POP without SECTION_PUSH" SectionStack.pop() Sections[thread].append((tick, tuple(SectionStack))) elif kind == "MTASK_BEGIN": mtask, predict_start, ecpu, hier_block = re_payload_mtaskBegin.match( payload).groups() hier_block = "" if hier_block is None else hier_block mtask = int(mtask) predict_start = int(predict_start) ecpu = int(ecpu) records = Threads[thread] records.append({ 'start': tick, 'mtask': mtask, 'predict_start': predict_start, 'hier_block': hier_block, 'cpu': ecpu }) Mtasks[(hier_block, mtask)]['begin'] = tick Mtasks[(hier_block, mtask)]['predict_start'] = predict_start Mtasks[(hier_block, mtask)]['thread'] = thread MtasksStack.append((hier_block, mtask, records[-1])) elif kind == "MTASK_END": predict_cost, = re_payload_mtaskEnd.match(payload).groups() mtask = int(mtask) hier_block, mtask, record = MtasksStack.pop() predict_cost = int(predict_cost) begin = Mtasks[(hier_block, mtask)]['begin'] record['end'] = tick assert record and records[-1]['start'] <= records[-1]['end'] <= tick record['predict_cost'] = predict_cost Mtasks[(hier_block, mtask)]['elapsed'] += tick - begin Mtasks[(hier_block, mtask)]['predict_cost'] = predict_cost Mtasks[(hier_block, mtask)]['end'] = max(Mtasks[(hier_block, mtask)]['end'], tick) elif kind == "THREAD_SCHEDULE_WAIT_BEGIN": ecpu = int(re_payload_wait.match(payload).groups()[0]) thread_last_ecpu = ecpu ThreadScheduleWait[ecpu].append(tick) elif kind == "THREAD_SCHEDULE_WAIT_END": # Might have ended on different CPU then we got THREAD_SCHEDULE_WAIT_BEGIN assert thread_last_ecpu is not None, "THREAD_SCHEDULE_WAIT_END without BEGIN" ecpu = thread_last_ecpu thread_last_ecpu = None start = ThreadScheduleWait[ecpu].pop() WaitingTime += tick - start ThreadScheduleWaitIntervals.append((start, tick, ecpu)) elif kind == "EXEC_GRAPH_BEGIN": ExecGraphStack.append(tick) elif kind == "EXEC_GRAPH_END": assert ExecGraphStack, "EXEC_GRAPH_END without EXEC_GRAPH_BEGIN" execGraphStart = ExecGraphStack.pop() ExecGraphTime += tick - execGraphStart ExecGraphIntervals.append((execGraphStart, tick)) elif Args.debug: print("-Unknown execution trace record: %s" % line) elif re_thread.match(line): thread = int(re_thread.match(line).group(1)) Sections[thread] = [] elif re.match(r'^VLPROF(THREAD|VERSION)', line): pass elif re_arg1.match(line): match = re_arg1.match(line) Global['args'][match.group(1)] = match.group(2) elif re_arg2.match(line): match = re_arg2.match(line) Global['args'][match.group(1)] = match.group(2) elif re_info.match(line): match = re_info.match(line) Global['info'][match.group(1)] = match.group(2) elif re_stat.match(line): match = re_stat.match(line) Global['stats'][match.group(1)] = match.group(2) elif re_proc_cpu.match(line): match = re_proc_cpu.match(line) cpu = int(match.group(1)) elif cpu is not None and re_proc_dat.match(line): match = re_proc_dat.match(line) term = match.group(1) value = match.group(2) term = re.sub(r'\s+$', '', term) term = re.sub(r'\s+', '_', term) value = re.sub(r'\s+$', '', value) Global['cpuinfo'][cpu][term] = value elif re.match(r'^#', line): pass elif Args.debug: print("-Unk: %s" % line) def re_match_result(regexp, line, result_to): result_to = re.match(regexp, line) return result_to ###################################################################### def report() -> None: print("Verilator Gantt report") print("\nArgument settings:") for arg in sorted(Global['args'].keys()): plus = "+" if re.match(r'^\+', arg) else " " print(" %s%s%s" % (arg, plus, Global['args'][arg])) for records in Threads.values(): for record in records: cpu = record['cpu'] elapsed = record['end'] - record['start'] Cpus[cpu]['mtask_time'] += elapsed global ElapsedTime ElapsedTime = int(Global['stats']['ticks']) nthreads = int(Global['stats']['threads']) ncpus = max(len(Cpus), 1) print("\nSummary:") print(" Total elapsed time = {} rdtsc ticks".format(ElapsedTime)) print(" Parallelized code = {:.2%} of elapsed time".format(ExecGraphTime / ElapsedTime)) print(" Waiting time = {:.2%} of elapsed time".format(WaitingTime / ElapsedTime)) print(" Total threads = %d" % nthreads) print(" Total CPUs used = %d" % ncpus) print(" Total mtasks = %d" % len(Mtasks)) print(" Total yields = %d" % int(Global['stats'].get('yields', 0))) report_numa() report_mtasks() report_cpus() report_sections() if nthreads > ncpus: print() print("%%Warning: There were fewer CPUs (%d) than threads (%d)." % (ncpus, nthreads)) print(" : See docs on use of numactl.") else: if 'cpu_socket_cores_warning' in Global: print() print("%Warning: Multiple threads scheduled on same hyperthreaded core.") print(" : See docs on use of numactl.") if 'cpu_sockets_warning' in Global: print() print("%Warning: Threads scheduled on multiple sockets.") print(" : See docs on use of numactl.") print() def report_numa() -> None: print("\nNUMA assignment:") print(" NUMA status = %s" % Global['info']['numa']) def report_mtasks() -> None: if not Mtasks: return nthreads = int(Global['stats']['threads']) # If we know cycle time in the same (rdtsc) units, # this will give us an actual utilization number, # (how effectively we keep the cores busy.) # # It also gives us a number we can compare against # serial mode, to estimate the overhead of data sharing, # which will show up in the total elapsed time. (Overhead # of synchronization and scheduling should not.) total_mtask_time = 0 thread_mtask_time = collections.defaultdict(lambda: 0) long_mtask_time = 0 long_mtask = None long_mtask_hier_block = None predict_mtask_time = 0 predict_elapsed = 0 for (hier_block, mtask_id) in Mtasks: record = Mtasks[(hier_block, mtask_id)] predict_mtask_time += record['predict_cost'] total_mtask_time += record['elapsed'] thread_mtask_time[record['thread']] += record['elapsed'] predict_end = record['predict_start'] + record['predict_cost'] predict_elapsed = max(predict_elapsed, predict_end) if record['elapsed'] > long_mtask_time: long_mtask_time = record['elapsed'] long_mtask = mtask_id long_mtask_hier_block = hier_block Global['predict_last_end'] = predict_elapsed serialTime = ElapsedTime - ExecGraphTime def subReport(elapsed, work): print(" Thread utilization = {:7.2%}".format(work / (elapsed * nthreads))) print(" Speedup = {:6.3}x".format(work / elapsed)) print("\nParallelized code, measured:") subReport(ExecGraphTime, total_mtask_time) print("\nParallelized code, predicted during static scheduling:") subReport(predict_elapsed, predict_mtask_time) print("\nAll code, measured:") subReport(ElapsedTime, serialTime + total_mtask_time) print("\nAll code, measured, scaled by predicted speedup:") expectedParallelSpeedup = predict_mtask_time / predict_elapsed scaledElapsed = serialTime + total_mtask_time / expectedParallelSpeedup subReport(scaledElapsed, serialTime + total_mtask_time) p2e_ratios = [] min_p2e = 1000000 min_mtask = None max_p2e = -1000000 max_mtask = None min_hier_block = None max_hier_block = None for (hier_block, mtask_id) in sorted(Mtasks.keys()): mtask = Mtasks[(hier_block, mtask_id)] if mtask['elapsed'] > 0: if mtask['predict_cost'] == 0: mtask['predict_cost'] = 1 # don't log(0) below p2e_ratio = math.log(mtask['predict_cost'] / mtask['elapsed']) p2e_ratios.append(p2e_ratio) if p2e_ratio > max_p2e: max_p2e = p2e_ratio max_mtask = mtask_id max_hier_block = hier_block if p2e_ratio < min_p2e: min_p2e = p2e_ratio min_mtask = mtask_id min_hier_block = hier_block print("\nMTask statistics:") if long_mtask_hier_block: print(" Longest mtask id = {} from hier_block '{}'".format(long_mtask, long_mtask_hier_block)) else: print(" Longest mtask id = {}".format(long_mtask)) print(" Longest mtask time = {:.2%} of time elapsed in parallelized code".format( long_mtask_time / ExecGraphTime)) print(" min log(p2e) = %0.3f" % min_p2e, end="") if min_hier_block: print(" from hier_block '%s' mtask %d (predict %d," % (min_hier_block, min_mtask, Mtasks[(min_hier_block, min_mtask)]['predict_cost']), end="") else: print(" from mtask %d (predict %d," % (min_mtask, Mtasks[(min_hier_block, min_mtask)]['predict_cost']), end="") print(" elapsed %d)" % Mtasks[(min_hier_block, min_mtask)]['elapsed']) print(" max log(p2e) = %0.3f" % max_p2e, end="") if max_hier_block: print(" from hier_block '%s' mtask %d (predict %d," % (max_hier_block, max_mtask, Mtasks[(max_hier_block, max_mtask)]['predict_cost']), end="") else: print(" from mtask %d (predict %d," % (max_mtask, Mtasks[(max_hier_block, max_mtask)]['predict_cost']), end="") print(" elapsed %d)" % Mtasks[(max_hier_block, max_mtask)]['elapsed']) stddev = statistics.pstdev(p2e_ratios) mean = statistics.mean(p2e_ratios) print(" mean = %0.3f" % mean) print(" stddev = %0.3f" % stddev) print(" e ^ stddev = %0.3f" % math.exp(stddev)) def report_cpus() -> None: print("\nCPU info:") Global['cpu_sockets'] = collections.defaultdict(lambda: 0) Global['cpu_socket_cores'] = collections.defaultdict(lambda: 0) print(" Id | Time spent executing MTask | Socket | Core | Model") print(" | % of elapsed ticks / ticks | | |") print(" ====|============================|========|======|======") for cpu in sorted(Cpus): socket = "" core = "" model = "" if cpu in Global['cpuinfo']: cpuinfo = Global['cpuinfo'][cpu] if 'physical_id' in cpuinfo and 'core_id' in cpuinfo: socket = cpuinfo['physical_id'] Global['cpu_sockets'][socket] += 1 core = cpuinfo['core_id'] Global['cpu_socket_cores'][socket + "__" + core] += 1 if 'model_name' in cpuinfo: model = cpuinfo['model_name'] print(" {:3d} | {:7.2%} / {:16d} | {:>6s} | {:>4s} | {}".format( cpu, Cpus[cpu]['mtask_time'] / ElapsedTime, Cpus[cpu]['mtask_time'], socket, core, model)) if len(Global['cpu_sockets']) > 1: Global['cpu_sockets_warning'] = True for scn in Global['cpu_socket_cores'].values(): if scn > 1: Global['cpu_socket_cores_warning'] = True def report_sections() -> None: for thread, section in Sections.items(): if section: print(f"\nSection profile for thread {thread}:") report_section(section) def report_section(section) -> None: totalTime = collections.defaultdict(lambda: 0) selfTime = collections.defaultdict(lambda: 0) sectionTree = [0, {}, 1] # [selfTime, childTrees, numberOfTimesEntered] prevTime = 0 prevStack = () for time, stack in section: if len(stack) > len(prevStack): scope = sectionTree for item in stack: scope = scope[1].setdefault(item, [0, {}, 0]) scope[2] += 1 dt = time - prevTime assert dt >= 0 scope = sectionTree for item in prevStack: scope = scope[1].setdefault(item, [0, {}, 0]) scope[0] += dt if prevStack: for name in prevStack: totalTime[name] += dt selfTime[prevStack[-1]] += dt prevTime = time prevStack = stack def treeSum(tree): n = tree[0] for subTree in tree[1].values(): n += treeSum(subTree) return n # Make sure the tree sums to the elapsed time sectionTree[0] += ElapsedTime - treeSum(sectionTree) def printTree(prefix, name, entries, tree): print(" {:7.2%} | {:7.2%} | {:8} | {:10.2f} | {}".format( treeSum(tree) / ElapsedTime, tree[0] / ElapsedTime, tree[2], tree[2] / entries, prefix + name)) for k in sorted(tree[1], key=lambda _: -treeSum(tree[1][_])): printTree(prefix + " ", k, tree[2], tree[1][k]) print(" Total | Self | Total | Relative | Section") print(" time | time | entries | entries | name ") print("==========|=========|==========|============|========") printTree("", "*TOTAL*", 1, sectionTree) ###################################################################### def write_vcd(filename: str) -> None: print("Writing %s" % filename) with open(filename, "w", encoding="utf8") as fh: # dict of dicts of hierarchy elements/signal name -> (code, width) scopeSigs = {} # map from time -> code -> value values = collections.defaultdict(lambda: {}) parallelism = { 'measured': collections.defaultdict(lambda: 0), 'predicted': collections.defaultdict(lambda: 0) } parallelism['measured'][0] = 0 parallelism['predicted'][0] = 0 nextFreeCode = 0 def getCode(width, *names): nonlocal nextFreeCode scope = scopeSigs *path, name = names for item in path: scope = scope.setdefault(item, {}) code, oldWidth = scope.setdefault(name, (nextFreeCode, width)) assert oldWidth == width if code == nextFreeCode: nextFreeCode += 1 return code def addValue(code, time, val): if isinstance(val, str): buf = "" for c in val: buf += bin(ord(c))[2:].rjust(8, "0") val = buf.ljust(LongestVcdStrValueLength * 8, "0") values[time][code] = val def addXValue(code, time): values[time][code] = 'x' # Measured graph for thread in sorted(Threads): mcode = getCode(32, 'measured', 't%d_mtask' % thread) for record in Threads[thread]: start = record['start'] mtask = record['mtask'] end = record['end'] cpu = record['cpu'] addValue(mcode, start, mtask) addValue(mcode, end, None) parallelism['measured'][start] += 1 parallelism['measured'][end] -= 1 code = getCode(32, 'measured', 'cpu%d_thread' % cpu) addValue(code, start, thread) addValue(code, end, None) code = getCode(32, 'measured', 'cpu%d_mtask' % cpu) addValue(code, start, mtask) addValue(code, end, None) tStart = sorted(_['start'] for records in Threads.values() for _ in records) tEnd = sorted(_['end'] for records in Threads.values() for _ in records) # Measured waiting time for (start, end, cpu) in ThreadScheduleWaitIntervals: mcode = getCode(32, 'measured', 'cpu%d_waiting' % cpu) addXValue(mcode, start) addValue(mcode, end, None) # Predicted graph for start, end in ExecGraphIntervals: # Find the earliest MTask start after the start point, and the # latest MTask end before the end point, so we can scale to the # same range tStartIdx = bisect.bisect_left(tStart, start) if tStartIdx >= len(tStart): continue start = tStart[tStartIdx] end = tEnd[bisect.bisect_right(tEnd, end) - 1] # Compute scale so predicted graph is of same width as interval measured_scaling = (end - start) / Global['predict_last_end'] # Predict mtasks that fill the time the execution occupied for (hier_block, mtask_id) in Mtasks: mtask = Mtasks[(hier_block, mtask_id)] thread = mtask['thread'] pred_scaled_start = start + int(mtask['predict_start'] * measured_scaling) pred_scaled_end = start + int( (mtask['predict_start'] + mtask['predict_cost']) * measured_scaling) if pred_scaled_start == pred_scaled_end: continue mcode = getCode(32, 'predicted', 't%d_mtask' % thread) addValue(mcode, pred_scaled_start, mtask_id) addValue(mcode, pred_scaled_end, None) parallelism['predicted'][pred_scaled_start] += 1 parallelism['predicted'][pred_scaled_end] -= 1 # Parallelism graph for measpred in ('measured', 'predicted'): pcode = getCode(32, 'stats', '%s_parallelism' % measpred) value = 0 for time in sorted(parallelism[measpred].keys()): value += parallelism[measpred][time] addValue(pcode, time, value) # Section graph for thread, section in Sections.items(): if section: scode = getCode(LongestVcdStrValueLength * 8, "section", f"t{thread}_trace") dcode = getCode(32, "section", f"t{thread}_depth") for time, stack in section: addValue(scode, time, stack[-1] if stack else None) addValue(dcode, time, len(stack)) # Create output file fh.write("$version Generated by verilator_gantt $end\n") fh.write("$timescale 1ns $end\n") fh.write("\n") all_codes = set() def writeScope(scope): assert isinstance(scope, dict) for key in sorted(scope): val = scope[key] if isinstance(val, dict): fh.write(" $scope module %s $end\n" % key) writeScope(val) fh.write(" $upscope $end\n") else: (code, width) = val all_codes.add(code) fh.write(" $var wire %d v%x %s [%d:0] $end\n" % (width, code, key, width - 1)) fh.write(" $scope module gantt $end\n") writeScope(scopeSigs) fh.write(" $upscope $end\n") fh.write("$enddefinitions $end\n") fh.write("\n") first = True for time in sorted(values): if first: first = False # Start with Z for any signals without time zero data for code in sorted(all_codes): if code not in values[time]: addValue(code, time, None) fh.write("#%d\n" % time) for code in sorted(values[time]): value = values[time][code] if value is None: fh.write("bz v%x\n" % code) elif value == 'x': fh.write("bx v%x\n" % code) elif isinstance(value, str): fh.write("b%s v%x\n" % (value, code)) else: fh.write("b%s v%x\n" % (format(value, 'b'), code)) ###################################################################### parser = argparse.ArgumentParser( allow_abbrev=False, formatter_class=argparse.RawDescriptionHelpFormatter, description="""Create Gantt chart of Verilator multi-threaded execution Verilator_gantt creates a visual representation to help analyze Verilator #xmultithreaded simulation performance, by showing when each macro-task #xstarts and ends, and showing when each thread is busy or idle. For documentation see https://verilator.org/guide/latest/exe_verilator_gantt.html""", epilog="""Copyright 2018-2025 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") parser.add_argument('--debug', action='store_true', help='enable debug') parser.add_argument('--no-vcd', help='disable creating vcd', action='store_true') parser.add_argument('--vcd', help='filename for vcd output', default='profile_exec.vcd') parser.add_argument('filename', help='input profile_exec.dat filename to process', default='profile_exec.dat') Args = parser.parse_args() read_data(Args.filename) report() if not Args.no_vcd: write_vcd(Args.vcd) ###################################################################### # Local Variables: # compile-command: "./verilator_gantt ../test_regress/t/t_gantt_io.dat" # End: verilator-5.042/bin/verilator0000755000542200017500000006670715101701376016637 0ustar mahmoudyfreeshell#!/usr/bin/env perl ###################################################################### # # Copyright 2003-2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ###################################################################### require 5.006_001; use warnings; use Getopt::Long; use FindBin qw($RealBin $RealScript); use IO::File; use Pod::Usage; use Cwd qw(realpath); use strict; use vars qw($Debug @Opt_Verilator_Sw); ####################################################################### ####################################################################### # main autoflush STDOUT 1; autoflush STDERR 1; $Debug = 0; my $opt_aslr; my $opt_gdb; my $opt_rr; my $opt_gdbbt; my $opt_quiet_exit; my $opt_unlimited_stack = 1; my $opt_valgrind; # No arguments can't do anything useful. Give help if ($#ARGV < 0) { pod2usage(-exitstatus => 2, -verbose => 0); } # Insert debugging options up front push @ARGV, (split ' ', $ENV{VERILATOR_TEST_FLAGS} || ""); # We sneak a look at the flags so we can do some pre-environment checks # All flags will hit verilator... foreach my $sw (@ARGV) { push @Opt_Verilator_Sw, $sw; } Getopt::Long::config("no_auto_abbrev", "pass_through"); if (! GetOptions( # Major operating modes "help" => \&usage, "debug" => \&debug, # "version!" => \&version, # Also passthru'ed # Switches "aslr!" => \$opt_aslr, "gdb!" => \$opt_gdb, "gdbbt!" => \$opt_gdbbt, "quiet!" => \$opt_quiet_exit, # As -quiet implies -quiet-exit "quiet-exit!" => \$opt_quiet_exit, "rr!" => \$opt_rr, "unlimited-stack!" => \$opt_unlimited_stack, "valgrind!" => \$opt_valgrind, # Additional parameters "<>" => sub {}, # Ignored )) { pod2usage(-exitstatus => 2, -verbose => 0); } # WARNING: $verilator_pkgdatadir_relpath is substituted during Verilator 'make install' my $verilator_pkgdatadir_relpath = ".."; my $verilator_root = realpath("$RealBin/$verilator_pkgdatadir_relpath"); if (defined $ENV{VERILATOR_ROOT}) { if ((!-d $ENV{VERILATOR_ROOT}) || $verilator_root ne realpath($ENV{VERILATOR_ROOT})) { warn "%Error: verilator: VERILATOR_ROOT is set to inconsistent path. Suggest leaving it unset.\n"; warn "%Error: VERILATOR_ROOT=$ENV{VERILATOR_ROOT}\n"; exit 1; } } else { print "export VERILATOR_ROOT='$verilator_root'\n" if $Debug; $ENV{VERILATOR_ROOT} = $verilator_root; } if ($opt_gdbbt && !gdb_works()) { warn "-Info: --gdbbt ignored: gdb doesn't seem to be working\n" if $Debug; $opt_gdbbt = 0; } # Determine runtime flags and run # Opt_Verilator_Sw is what we want verilator to see on its argc/argv. # Starting with that, escape all special chars for the shell; # The shell will undo the escapes and the verilator binary should # then see exactly the contents of @Opt_Verilator_Sw. my @quoted_sw = map { sh_escape($_) } @Opt_Verilator_Sw; if ($opt_gdb) { # Generic GDB interactive run (ulimit_stack_unlimited() . aslr(0) . ($ENV{VERILATOR_GDB} || "gdb") . " " . verilator_bin() # Note, uncomment to set breakpoints before running: # ." -ex 'break main'" # Note, we must use double-quotes ("run ") # and not single ('run ') below. Bash swallows # escapes as you would expect in a double-quoted string. # That's not true for a single-quoted string, where \' # actually terminates the string -- not what we want! . " -ex \"run " . join(' ', @quoted_sw) . "\"" . " -ex 'set width 0'" . " -ex 'bt'"); } elsif ($opt_rr) { # Record with rr run (ulimit_stack_unlimited() . aslr(0) . "rr record " . verilator_bin() . " " . join(' ', @quoted_sw)); } elsif ($opt_gdbbt && $Debug) { # Run under GDB to get gdbbt run (ulimit_stack_unlimited() . aslr(0) . "gdb" . " " . verilator_bin() . " --batch --quiet --return-child-result" . " -ex \"run " . join(' ', @quoted_sw)."\"" . " -ex 'set width 0'" . " -ex 'bt' -ex 'quit'"); } elsif ($opt_valgrind) { # Run under valgrind my $valgrind_bin = ($ENV{VERILATOR_VALGRIND} || "valgrind --error-exitcode=1 --max-stackframe=2815880" # Magic number suggested by Valgrind, may need to be increased in future # if you get warnings. See: https://valgrind.org/docs/manual/manual-core.html#opt.max-stackframe ); run (ulimit_stack_unlimited() . aslr(0) . $valgrind_bin . " " . verilator_bin() . " " . join(' ', @quoted_sw)); } elsif ($Debug) { # Debug run(ulimit_stack_unlimited() . aslr(0) . verilator_bin() . " " . join(' ', @quoted_sw)); } else { # Normal, non gdb run(ulimit_stack_unlimited() . aslr(1) . verilator_bin() . " " . join(' ', @quoted_sw)); } #---------------------------------------------------------------------- sub usage { pod2usage(-verbose => 2, -exitval => 0, -output => \*STDOUT); } sub debug { shift; my $level = shift; $Debug = $level || 3; } ####################################################################### ####################################################################### # Builds sub verilator_bin { my $basename = ($ENV{VERILATOR_BIN} || ($Debug ? "verilator_bin_dbg" : "verilator_bin")); if (-x "$RealBin/$basename" || -x "$RealBin/$basename.exe") { return "$RealBin/$basename"; } else { return $basename; # Find in PATH } } ####################################################################### ####################################################################### # Utilities sub gdb_works { $! = undef; # Cleanup -x system("gdb /bin/echo" . " --batch-silent --quiet --return-child-result" . " -ex 'run -n'" # `echo -n` . " -ex 'set width 0'" . " -ex 'bt'" . " -ex 'quit'"); my $status = $?; return $status == 0; } sub aslr { my $want_on = shift; $want_on = $opt_aslr if defined $opt_aslr; if (!$want_on) { my $ok = `setarch --addr-no-randomize echo ok 2>/dev/null` || ""; if ($ok =~ /ok/) { return "setarch --addr-no-randomize "; } } return ""; } sub ulimit_stack_unlimited { return "" if !$opt_unlimited_stack; my $limit = "unlimited"; # AddressSanitizer doesn't work with 'ulimit -s unlimted' if (`${\(verilator_bin())} --get-supported DEV_ASAN` eq "1\n") { # Use host 'physical memory / #cores / 8' instead open(my $fh, "<", "/proc/meminfo") || die "Can't read host memory for asan"; while (<$fh>) { if (m/MemTotal:\s+(\d+)\s+kB/) { $limit = int(int($1)/`nproc`/8); last; } } close($fh); } system("ulimit -s $limit 2>/dev/null"); my $status = $?; if ($status == 0) { return "ulimit -s $limit 2>/dev/null; exec "; } else { return ""; } } sub run { # Run command, check errors my $command = shift; $! = undef; # Cleanup -x print "\t$command\n" if $Debug >= 3; system($command); my $status = $?; if ($status) { if ($! =~ /no such file or directory/i) { warn "%Error: verilator: Misinstalled, or VERILATOR_ROOT might need to be in environment\n"; } if ($Debug) { # For easy rerunning warn "%Error: export VERILATOR_ROOT=" . ($ENV{VERILATOR_ROOT} || "") . "\n"; warn "%Error: $command\n"; } my $signal = ($status & 127); if ($signal) { if ($signal == 4 # SIGILL || $signal == 8 # SIGFPA || $signal == 11) { # SIGSEGV warn "%Error: Verilator internal fault, sorry. " . "Suggest trying --debug --gdbbt\n" if !$Debug; } elsif ($signal == 6) { # SIGABRT warn "%Error: Verilator aborted. " . "Suggest trying --debug --gdbbt\n" if !$Debug; } else { warn "%Error: Verilator threw signal $signal. " . "Suggest trying --debug --gdbbt\n" if !$Debug; } } if (!$opt_quiet_exit && ($status != 256 || $Debug)) { # i.e. not normal exit(1) warn "%Error: Command Failed $command\n"; } exit $! if $!; # errno exit $? >> 8 if $? >> 8; # pass along child exit code exit 128 + $signal; # last resort } } sub sh_escape { my ($arg) = @_; # This is similar to quotemeta() but less aggressive. # There's no need to escape hyphens, periods, or forward slashes # for the shell as these have no special meaning to the shell. $arg =~ s/([^0-9a-zA-Z_\-\+\=\.\/:])/\\$1/g; return $arg; } ####################################################################### ####################################################################### package main; __END__ =pod =head1 NAME Verilator - Lint, compile and simulate SystemVerilog code using C++/SystemC =head1 SYNOPSIS verilator --help verilator --version verilator --binary -j 0 [options] [source_files.v]... [opt_c_files.cpp/c/cc/a/o/so] verilator --cc [options] [source_files.v]... [opt_c_files.cpp/c/cc/a/o/so] verilator --sc [options] [source_files.v]... [opt_c_files.cpp/c/cc/a/o/so] verilator --lint-only -Wall [source_files.v]... =head1 DESCRIPTION The "Verilator" package converts all synthesizable, and many behavioral, Verilog and SystemVerilog designs into a C++ or SystemC model that after compiling can be executed. Verilator is not a traditional simulator, but a compiler. For documentation see L. =head1 ARGUMENT SUMMARY This is a short summary of the arguments to the "verilator" executable. See L for the detailed descriptions of these arguments. =for VL_SPHINX_EXTRACT "_build/gen/args_verilator.rst" Verilog package, module, and top module filenames Optional C++ files to compile in Optional C++ files to link in +1364-1995ext+ Use Verilog 1995 with file extension +1364-2001ext+ Use Verilog 2001 with file extension +1364-2005ext+ Use Verilog 2005 with file extension +1800-2005ext+ Use SystemVerilog 2005 with file extension +1800-2009ext+ Use SystemVerilog 2009 with file extension +1800-2012ext+ Use SystemVerilog 2012 with file extension +1800-2017ext+ Use SystemVerilog 2017 with file extension +1800-2023ext+ Use SystemVerilog 2023 with file extension --no-aslr Disable address space layout randomization --no-assert Disable all assertions --no-assert-case Disable unique/unique0/priority-case assertions --autoflush Flush streams after all $displays --bbox-sys Blackbox unknown $system calls --bbox-unsup Blackbox unsupported language features --binary Build model binary --build Build model executable/library after Verilation --build-dep-bin Override build dependency Verilator binary --build-jobs Parallelism for --build --cc Create C++ output -CFLAGS C++ compiler arguments for makefile --compiler Tune for specified C++ compiler --compiler-include Include additional header in the precompiled one --converge-limit Tune convergence settle time --coverage Enable all coverage --coverage-expr Enable expression coverage --coverage-expr-max Maximum permutations allowed for an expression --coverage-line Enable line coverage --coverage-max-width Maximum array depth for coverage --coverage-toggle Enable toggle coverage --coverage-underscore Enable coverage of _signals --coverage-user Enable SVL user coverage -D[=] Set preprocessor define --debug Enable debugging --debug-check Enable debugging assertions --no-debug-leak Disable leaking memory in --debug mode --debugi Enable debugging at a specified level --debugi- Enable debugging a source file at a level --no-decoration Disable comments and lower spacing level --decorations Set output comment and spacing level --default-language Default language to parse +define+= Set preprocessor define --diagnostics-sarif Enable SARIF diagnostics output --diagnostics-sarif-output Set SARIF diagnostics output file --dpi-hdr-only Only produce the DPI header file --dump- Enable dumping everything in source file --dump-defines Show preprocessor defines with -E --dump-dfg Enable dumping DfgGraphs to .dot files --dump-graph Enable dumping V3Graphs to .dot files --dump-inputs Enable dumping preprocessed input files --dump-tree Enable dumping Ast .tree files --dump-tree-addrids Use short identifiers instead of addresses --dump-tree-dot Enable dumping Ast .tree.dot debug files --dump-tree-json Enable dumping Ast .tree.json files and .tree.meta.json file --dumpi- Enable dumping everything in source file at level --dumpi-dfg Enable dumping DfgGraphs to .dot files at level --dumpi-graph Enable dumping V3Graphs to .dot files at level --dumpi-tree Enable dumping Ast .tree files at level --dumpi-tree-json Enable dumping Ast .tree.json files at level -E Preprocess, but do not compile --emit-accessors Emit getter and setter methods for model top class --error-limit Abort after this number of errors --exe Link to create executable --expand-limit Set expand optimization limit -F Parse arguments from a file, relatively -f Parse arguments from a file -FI Force include of a file --flatten Force inlining of all modules, tasks and functions --future0